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MSP430 Peripheral Driver Library for FR5xx and FR6xx Devices

1. Clear SFR Fault Flag SFR_clearInterrupt SFR_BASE OFIFG Test oscillator fault flag Jwhile SFR_getInterruptStatus SFR_BASE OFIFG 2013 05 2009 07 07_0500 67 TI Information Selective Disclosure SFR Module 68 TI Information Selective Disclosure 2013 05 2009 07 07_0500 23 23 1 23 2 SYS Module SYS Module ROUT HON EEE UNS O PO EP PE O PRT O O PE R O R O O R P N 69 Pl V as ich vedic O OP REE RO O O O weed a ee T CO PO P 69 Programming Banden 22 Introduction The System Control SYS API provides a set of functions for using the MSP430Ware SYS mod ule Functions are provided to control various SYS controls setup the BSL and control the JTAG Mailbox This driver is contained in sys c with sys h containing the API definitions for use by applications API Functions The SYS API is broken into 3 groups the various SYS controls the BSL controls and the JTAG mailbox controls The various SYS controls are handled by m SYS enableDedicatedJTAGPins m SYS_getBSLEntryIndication m SYS_enablePMMAccessProtect m SYS_enableRAMBasedinterruptVectors m SYS_disableRAMBasedinterruptVectors The BSL controls are handled by m SYS_enableBSLProtect m SYS disableBSL Protect m SYS disableBSLMemory m SYS enableBSLMemory m SYS setRAMAssignedToBSL m SYS setBSLSize The JTAG Mailbox controls are handled by m SYS JTAGMailboxlnit m SYS getJTAGMailboxFlagStatus m SYS getJTAGInboxMessage16Bit
2. API Functions TIMER_B configuration and initialization is handled by m TIMER_B_startCounter m TIMER B configureContinuousModef m TIMER B configureUpMode m TIMER B configureUpDownModef m TIMER B startContinuousModef m TIMER B startUpMode m TIMER B startUpDownMode m TIMER B initCapture m TIMER B initComparef m TIMER_B_clear m TIMER B stop m TIMER B initCompareLatchLoadEvent m TIMER_B_selectLatchingGroup m TIMER B selectCounterLength TIMER B outputs are handled by m TIMER B getSynchronizedCaptureComparelnput m TIMER B getOutputForOutputModeOutBitValue m TIMER B setOutputForOutputModeOutBitValue m TIMER B generatePWM m TIMER_B_getCaptureCompareCount m TIMER B setCompareValuef m TIMER B getCounterValue The interrupt handler for the TIMER B interrupt is managed with m TIMER B enablelnterrupt m TIMER B disablelnterrupt TI Information Selective Disclosure The TIMER_B API provides a set of functions for dealing with the TIMER_B module Functions are provided to configure and control the timer along with functions to modify timer counter values and to manage interrupt handling for the timer Control is also provided over interrupt sources and events Interrupts can be generated to indicate that an event has been captured This driver is contained in TIMER_B c with TIMER B h containing the API definitions for use by applications The TIMER_B AP
3. 070500 79 TI Information Selective Disclosure Tag Length Value 80 TI Information Selective Disclosure 2013 05 2009 07 07_0500 WatchDog Timer WDT_A 27 WatchDog Timer WDT_A ils Te Ne TETEE ENTER ERENTO E 81 APUROS eek 81 Programming Bande see 81 27 1 Introduction The Watchdog Timer WDT_A API provides a set of functions for using the MSP430Ware WDT_A modules Functions are provided to initialize the Watchdog in either timer interval mode or watch dog mode with selectable clock sources and dividers to define the timer interval The WDT_A module can generate only 1 kind of interrupt in timer interval mode If in watchdog mode then the WDT_A module will assert a reset once the timer has finished This driver is contained in wdt_a c with wdt_a h containing the API definitions for use by appli cations 27 2 API Functions The WDT_A API is one group that controls the WDT_A module m WDT_A_hold a WDT_A start m WDT A clearCounter m WDT A watchdogTimerlnit m WDT A intervalTimerlnit 27 3 Programming Example The following example shows how to initialize and use the WDT A API to interrupt about every 32 ms toggling the LED in the ISR Initialize WDT A module in timer interval mode with SMCLK as source at an interval of 32 ms WDT A intervalTimerInit WDT A BASE WDT A CLOCKSOURCE SMCIK WDT A CLOCKDIVIDER 32K Enable Watchdog Interupt SFR enableInterrupt SFR BASE WDT AIE Set P
4. 07_0500 6 1 6 2 Advanced Encryption Standard AES256 Advanced Encryption Standard AES256 ROUT HON k BZ no io bd odd o k ode edk on odk kouka lk book k n TER 25 PAPUE ROS ee ee en ee eee 25 Pregramnimng Bande sehe 26 Introduction The AES256 accelerator module performs encryption and decryption of 128 bit data with 128 bit keys according to the advanced encryption standard AES256 FIPS PUB 197 in hardware The AES256 accelerator features are m Encryption and decryption according to AES256 FIPS PUB 197 with 128 bit key m On the fly key expansion for encryption and decryption m Off line key generation for decryption m Byte and word access to key input and output data m AES256 ready interrupt flag The AES256256 accelerator module performs encryption and de cryption of 128 bit data with 128 1 92 256 bit keys according to the advanced encryption stan dard AES256 FIPS PUB 197 in hardware The AES256 accelerator features are AES256 encryption U 128 bit 168 cycles U 192 bit 204 cycles U 256 bit 234 cycles AES256 decryption U 128 bit 168 cycles U 192 bit 206 cycles U 256 bit 234 cycles m On the fly key expansion for encryption and decryption m Offline key generation for decryption m Shadow register storing the initial key for all key lengths m Byte and word access to key input data and output data m AES256 ready interrupt flag This driver is contained in aes256 c with aes256 h containing the API defi
5. m SYS getJTAGInboxMessage32Bit m SYS_setJTAGOutgoingMessage 16Bit m SYS_setJTAGOutgoingMessage32Bit m SYS clearJTAGMailboxFlagStatus 2013 05 2009 07 070500 69 TI Information Selective Disclosure SYS Module 23 3 Programming Example The following example shows how to initialize and use the SYS API SYS_enableBSLProtect SYS_BASE 70 2013 05 2009 07 070500 TI Information Selective Disclosure TIMER_A 24 TIMER A IMO A o ieh 71 AP SIE ale A EEE TEN ai EN SS Sp Bl et dat B bb AS 6 Bl h n ubit dn ty EES 72 Programme Example an Le 24 1 Introduction TIMER_A is a 16 bit timer counter with multiple capture compare registers TIMER_A can support multiple capture compares PWM outputs and interval timing TIMER_A also has extensive inter rupt capabilities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers This peripheral API handles Timer A hardware peripheral TIMER_A features include m Asynchronous 16 bit timer counter with four operating modes m Selectable and configurable clock source m Up to seven configurable capture compare registers m Configurable outputs with pulse width modulation PWM capability m Asynchronous input and output latching m Interrupt vector register for fast decoding of all Timer interrupts TIMER_A can operate in 3 modes m Continuous Mode m Up Mode m Down Mode TIMER A Interrupts may be generated o
6. ule is now ready for transmit and receive It is recommended to iniailize the EUSI A UART via EUSCI A UART init enable the reguired interrupts and then enable EUSI A UART via EU SCI A UART enablef The EUSI A UART API is broken into three groups of functions those that deal with configuration and control of the EUSI A UART modules those used to send and receive data and those that deal with interrupt handling and those dealing with DMA Configuration and control of the EUSI UART are handled by the m EUSCI A UART init 2013 05 2009 07 070500 39 TI Information Selective Disclosure EUSCI Universal Asynchronous Receiver Transmitter EUSCI_A_UART 11 3 40 m EUSCI_A_UART_initAdvance m EUSCI_A_UART_enable EUSCI_A_UART_disable EUSCI_A_UART_setDormant m EUSCI A UART resetDormant m EUSCI A UART selectDeglitchTime Sending and receiving data via the EUSI UART is handled by the m EUSCI A UART transmitData m EUSCI A UART receiveData m EUSCI A UART transmitAddress m EUSCI A UART transmitBreak Managing the EUSI UART interrupts and status are handled by the m EUSCI A UART enablelnterrupt m EUSCI A UART disablelnterrupt m EUSCI A UART getlnterruptStatus m EUSCI A UART clearlnterruptFlag m EUSCI A UART aueryStatusFlags DMA related m EUSCI A UART getReceiveBufferAddressForDMA m EUSCI A UART getIransmitBufferAddressForDMA Programming Example The following example shows how t
7. PMM PMMBORIFG PMM_clearInterrupt PMM BASE PMM_PMMBORIFG __delay_cycles 1000000 PMM_lockLPM5 PMM_BASE Disable SVSH Base Address of Comparator D High side SVS SVSH is disabled in LPM4 5 SVSH is Was this device in LPMx 5 mode before Clear the LPMx 5 flac Was this reset triggered by the Reset Clear reset flag Software tric Was this reset triggered by the BOR 1 Clear BOR flag 60 TI Information Selective Disclosure 2013 05 2009 07 07_0500 Power Management Module PMM always enabled in active mode and LPM0 1 2 3 4 and LPM3 5 x PMM disableSVSH PMM BASE Disable SVSL Base Address of Comparator D Low side SVS SVSL is disabled in low power modes SVSL is always enabled in active mode and LPMO x PMM disableSVSL PMM BASE Disable Regulator Base Address of Comparator D Regulator is turned off when going to LPM3 4 System enters LPM3 5 or LPM4 5 respectively PMM_regOff PMM_BASE __bis_SR_register LPM4 bits Enter LPM4 5 This automatically locks if not locked already all GPIO pir and will set the LPM5 flag and set in the PM5CTLO register upon wake 11 5 while 1 __no_operation Don t sleep 2013 05 2009 07 070500 61 TI Information Selective Disclosure Power Management Module PMM 62 TI Information Selective Disclosure 2013 05 2009 07 07_0500 20 20 1 20 2 Internal Referenc
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9. 070500 37 TI Information Selective Disclosure Direct Memory Access DMA 10 3 Programming Example 38 The following example shows how to initialize and use the DMA API to transfer words from one spot in RAM to another Initialize and Setup DMA Channel 0 Base Address of the DMA Module Configure DMA channel 0 Configure channel for repeated block transfers DMA interrupt flag will be set after every 16 transfers Use DMA startTransfer function to trigger transfers Transfer Word to Word Trigger upon Rising Edge of Trigger Source Signal DMA_init DMA_BASE DMA CHANNEL 0 DMA TRANSFER REPEATED BLOCK 16 DMA TRIGGERSOURCE 0 DMA_SIZE_SRCWORD_DSTWORD DMA TRIGGER RISINGEDGE Base Address of the DMA Module Configure DMA channel 0 Use 0x1C00 as source Increment source address after every transfer x DMA_setSrcAddress DMA BASE DMA CHANNEL 0 0x1C00 DMA_DIRECTION_INCREMENT Base Address of the DMA Module Configure DMA channel 0 Use 0x1C20 as destination Increment destination address after every transfer x DMA_setDstAddress DMA BASE DMA CHANNEL 0 0x1C20 DMA_DIRECTION_INCREMENT Enable transfers on DMA channel 0 DMA_enableTransfers DMA_BASE DMA CHANNEL 0 while 1 Start block tranfer on DMA channel 0 DMA_startTransfer DMA_BASE DMA CHANNEL 0 TI Information Selective Disclosure 2013 05 2009 07 07_0500 11 11 1 11 2 EUSCI Universal Asynchrono
10. Fe dein Dem uae ska e t 63 EI III 0 ida de E e E ee er ROE a ade eS AS Ge ne ED ee Te Spat Sen Bes 63 20 3 Programming EXT u ra ae ee ee ice a 64 21 Real time Clock RIG o cd A rar aka 65 21 1 Ido i u ea a amp Glad Bi GONE ode aoe c r e Gay a a are Ge EE 65 212 irl MAM GPRS c doc ac a at ae ee he ee Ed ee Gees a ae eas as ae Amir k RR dete we gS Ok ai rae pcg ST AS ee 18 65 213 Pra mila Examples se 6 oa 20 donk ee ware ee bate ee bade ae a Be Po aa 66 22 SFR Module 500 wor a eS A RR a RL ee es 67 22 1 MMPOG MOM oi he de ao dy Se Se ae tea eects dh oh Bh eH AS ie AS Hoes A ae Ee eae we ah Pe Sd wh ae Me ee a ae AN 67 PEARL TERN fae ce ate cae as a ares u broths E OB dar OR Gwe Re ae Aa we fae Be Pe O eds KE Doe Ge ae aye eee A 67 223 Programing Damp un ne ae a ae eo et Ha a Av de EA EO A A A Aby Asko 67 23 SVS Module ice A ee ee ee Be ere RR Ee ee BO Gee VG ees 69 23 1 COMMON lt lt ee Sa Bae Poe Dade obje eh Oe Sie aoe E A eo Ha we ae yee en Dae Gd we a E 69 ZI FA EVANS i e ra a Be lance oS See a a DA Se ee AA e Goan a cd A A Bea v v var he ee ehe 69 233 Pregramming Example i254 ee by dup wae a oY ERG we EA DE SEER ES Paes Ete SSeS db Bae ees 70 20 MERA cei Se ee eae clu oie o ds ee eee e Be ee aoe eee Sere Sees ae 71 23 1 MPO OMG INS gt 0 are ANNAN 71 242 PA TRACI 22 seng ee aan Ve ee ee a Ee EGE Ba Ae eae ae She k dv Re AS eh aw Be NS 72 243 Progamming AA 72 25 TIMER B oo u
11. Peso are otter methods fo stat a proyect debug seamen Select he proyect the Project Explorer ves and chek on the bug toolbar button To relaunch a prowovs debug season click on Pe anal arrow 2 Desde Pe bug holder hA and select one of Me debug season tom Pe Satory d oe o aereed Dann Now click on Build the imported project on the right to build the example project 12 2013 05 2009 07 070500 TI Information Selective Disclosure Navigating to driverlib through CCS Resource Explorer Y CCS Edt TI Resource Explorer Code Conny Hilado Me Me mer ruge Pet hm Soga Winde ve 3 9 Ar Dri Fi voss FO reed Explorer b4 0k De ni run Diurno 4 Y mee Write a Word to Port A Porr Por MI to o MA 4 W men te Toen These are the steps to import the project build the project and debug the project Aurore ir error o ems Step 1 Es Import the example project into CCS J cis vam Cack om Se ink above to mporn the proyect The mported proyect is available n the Project Explorer wen expand te or proyect nade to browse fre emported source files To mody sauce code doble choks on Se saroe fie win Pe ox proyect to open the source fle editor va wm Sup Bald me imported project y Y na W sat To enge Oud peona GM cick on Pe pros and se Properties tom fe contes menu To Oud Pe rec po select Pe ir above oF select he Buld hobr bution or sect Pe Project Build Project mer t
12. and those that deal with interrupt handling TIMER_A configuration and initialization is handled by m TIMER_A_startCounter m TIMER_A_configureContinuousMode m TIMER A configureUpMode m TIMER A configureUpDownModef m TIMER A startContinuousModef m TIMER A startUpModef m TIMER A startUpDownModef m TIMER A initCapture m TIMER A initComparef m TIMER A clear m TIMER A stop TIMER A outputs are handled by m TIMER A getSynchronizedCaptureComparelnput m TIMER A getOutputForOutputModeOutBitValue m TIMER A setOutputForOutputModeOutBitValue m TIMER A generatePWM m TIMER A getCaptureCompareCount m TIMER A setCompareValuef m TIMER A getCounterValue The interrupt handler for the TIMER A interrupt is managed with m TIMER A enablelnterrupt m TIMER A disablelnterrupt m TIMER A oetlnterruptStatus m TIMER A enableCaptureComparelnterrupt m TIMER A disableCaptureComparelnterrupt m TIMER A getCaptureComparelnterruptStatus m TIMER A dlearCaptureComparelnterruptFlag m TIMER A dlearTimerlnterruptFlag 24 3 Programming Example The following example shows some TIMER A operations using the APIs 72 2013 05 2009 07 070500 TI Information Selective Disclosure TIMER_A Start TIMER_A TIMER A configureUpDownMode TIMER Al BASE TIMER A CLOCKSOURCE SMCLK TIMER A CLOCKSOURCE DIVIDER 1 TIMER PERIOD TIMER A TAIE INTERRUPT DISABLE TIMER A CCIE CCR0 IN
13. as sample hold signal to start conversion MODOSC 5MHZ Digital Oscillator as clock source default clock divider pre divider of 1 to internal channel 0 x ADC12_B_init ADC12 B BASE ADC12 B SAMPLEHOLDSOURCE SC ADC12 B CLOCKSOURCE ADC120SC ADC12 B CLOCKDIVIDER 1 ADC12 B CLOCKPREDIVIDER 1 ADC12 B MAPINTCHO TI Information Selective Disclosure 2013 05 2009 07 070500 21 21 1 21 2 Real Time Clock RTC Real Time Clock RTC MOGUCOM APP Pon nn PP EET Ea 65 A ee ee 65 fiere les TD EEN DE see 66 Introduction The Real Time Clock RTC API provides a set of functions for using the MSP430Ware RTC mod ules Functions are provided to calibrate the clock initialize the RTC modules in Calendar mode and setup conditions for and enable interrupts for the RTC modules If an RTC_B_A module is used then Counter mode may also be intialized as well as prescale counters The RTC module provides the ability to keep track of the current time and date in calendar mode or can be setup as a 32 bit counter RTC_B_A Only The RTC module generates multiple interrupts There are 2 interrupts that can be defined in cal endar mode and 1 interrupt in counter mode for counter overflow as well as an interrupt for each prescaler This driver is contained in rtc_b c with rtc_b h containing the API definitions for use by appli cations API Functions The RTC API is broken into 4 groups of functions clock settings calender mod
14. on the bus by calling the transmit or receive related APIs as listed below Slave Transmission API m EUSCI B 12C_slaveDataPut Slave Reception API m EUSCI B I2C slaveDataGet 2013 05 2009 07 070500 TI Information Selective Disclosure EUSCI Inter Integrated Circuit EUSCI B I2C For the interrupt driven transaction the user must register an interrupt handler for the I2C devices and enable the 12C interrupt This driver is contained in eusci_b_i2c c with eusci_b_i2c h containing the API definitions for use by applications 14 2 API Functions The eUSCI 12C API is broken into three groups of functions those that deal with interrupts those that handle status and initialization and those that deal with sending and receiving data The 12C master and slave interrupts are handled by m EUSCI B I2C enablelnterrupt m EUSCI B I2C disablelnterrupt m EUSCI B I2C cdlearlnterruptFlag m EUSCI B I2C getlnterruptStatus Status and initialization functions for the I2C modules are m EUSCI B I2C masterlnit m EUSCI B I2C enable m EUSCI B I2C disable m EUSCI B I2C isBusBusy m EUSCI B I2C isBusy m EUSCI B 12C slavelnit m EUSCI B I2C interruptStatus m EUSCI B I2C setSlaveAddress m EUSCI B I2C setMode m EUSCI B I2C masterlsStopSent m EUSCI B I2C masterlsStartSent m EUSCI B I2C selectMasterEnvironmentSelect Sending and receiving data from the I2C slave module is handled by m EUSCI B 12C slaveDataPut m EUSCI B I2C slaveDataGe
15. project 20 r Edit directory path Directory If the driverlib files are linked into project Include the MSP430ware driverlib install path to the include paths In this example C ti ccs5 3 0 ccsv5 ccs_base msp430 MSP430ware_1_30_00_15 driverlib MSP430FR5xx_6xx Add directory path Directory Eitilccs5 3 0 ccsySiccs_baselmsp430 MSP430ware_1_30_00_151driverlibif Cancel Workspace File system STEP 3 In the source files that use driverlib API calls include Sinc hw memmap h instead of including msp430 h STEP 4 To use driverlib APIs to configure use any peripheral include the corresponding header file in the user file For example if you would like to use WDT_A_hold API use include Swdt_a hT 2013 05 2009 07 070500 TI Information Selective Disclosure 5 5 1 5 2 12 Bit Analog to Digital Converter ADC12_B 12 Bit Analog to Digital Converter ADC12_B IHANOANENEN ESS POP AP P R a ii dd e 21 O 2 200 een LESS ss bad boa ERE res 21 Programming Rampe een 22 Introduction The 12 Bit Analog to Digital ADC12_B API provides a set of functions for using the MSP430Ware ADC12_B modules Functions are provided to initializae the ADC12_B modules setup signal sources and reference voltages for each memory buffer and manage interrupts for the ADC12_B modules The ADC12_B module provides the ability to convert analog signals into a digital value in respect t
16. specific example you are interested in On the right side there are options to Import Build Download and 10 2013 05 2009 07 070500 TI Information Selective Disclosure Navigating to driverlib through CCS Resource Explorer Debug Import the project by clicking on the SImport the example project into CCST gt CCS k n Ti Resource Explorer Code composer Stute I mE gt gt a De pe ye as poa Ba Sows miw ly O 6 ee LN tease Lotre pn mi mini Active Del Pakage Al 2 tes a F Bungie Projects acute ame je ge mi aan Y wa Y outer rr a i5 ge mi mann mi yoso ME 2 toms a AD Fy gpio ex1 outputHi Whine Word to Poe A Porri Por These are the steps to import the project build the project and debug the project tepi impor Ihe example prosta info CC Y lt re the Project Explorer ves arpas Pe Baa he imported praec 1 k 07 ent Properties Me contest me e prue no ot me Bash o y pe Fe Project Bild Project me p3 Y Debugger Combos none Sep4 Debug the imported prosect a Pe ir above Yo DE TEE r e gvo es cutpu CCS Debug Perspective Ad pe O50 e Per neruda lo Slat 4 royal e sess select Pe roer lt Project Exg cenr vor je ar the Dug toolbar bution Ta rete e provova deb Se am Pe sel ere The imported project can be viewed on the left in the Project Explorer All required driverlib source and header files are included inside the driverlib folder All driverlib sou
17. to generate a PUC on access violation on the second segment MPU enablePUCOnViolation MPU BASE MPU SECOND SEG Enables the MPU module MPU start MPU BASE 2013 05 2009 07 070500 TI Information Selective Disclosure 32 Bit Hardware Multiplier MPY32 18 32 Bit Hardware Multiplier MPY32 is Te Me pobod n rt Tee eee O 57 AP FURER HE eek 57 Pe Bande see 58 18 1 Introduction The 32 Bit Hardware Multiplier MPY32 API provides a set of functions for using the MSP430Ware MPY32 modules Functions are provided to setup the MPY32 modules set the operand registers and obtain the results The MPY32 Modules does not generate any interrupts This driver is contained in mpy32 c with mpy32 h containing the API definitions for use by appli cations 18 2 API Functions The MPY32 API is broken into three groups of functions those that control the settings those that set the operand registers and those that return the results sum extension and carry bit value The settings are handled by MPY32_setWriteDelay MPY32_setSaturationMode MPY32_resetSaturationMode MPY32_setFractionMode MPY32_resetFractionMode The operand registers are set by m MPY32_setOperandOne8Bit m MPY32_setOperandOne16Bit m MPY32_setOperandOne24Bit m MPY32_setOperandOne32Bit m MPY32 setOperandTwo8Bit m MPY32 setOperandTwo16Bit m MPY32 setOperandTwo24Bit m MPY32 setOperandTwo32Bit The results can be returned by m MPY32 getResult8Bit m MPY32 ge
18. 1 0 to output direction GPIO_setAsOutputPin GPIO_PORT_P1 GPIO_PINO i 2013 05 2009 07 070500 81 TI Information Selective Disclosure WatchDog Timer WDT_A Enter LPMO enable interrupts __bis_SR_register LPMO_bits GIE For debugger __no operation 82 TI Information Selective Disclosure 2013 05 2009 07 07_0500 2013 05 2009 07 070500 TI Information Selective Disclosure 83 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed Tl assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications
19. 500 21 TI Information Selective Disclosure 12 Bit Analog to Digital Converter ADC12_B 5 3 22 ADC12 B init ADC12 B memoryConfigure ADC12 B setWindowCompAdvanced ADC12 B setupSamplingTimer ADC12 B disableSamplingTimer ADC12 B startConversion ADC12 B disableConversions ADC12 B getResults ADC12 B isBusy The ADC12 B interrupts are handled by m ADC12 B enablelnterrupt m ADC12 B disablelnterrupt m ADC12 B clearlnterrupt m ADC12 B getlnterruptStatus Auxilary features of the ADC12 B are handled by ADC12 B setResolution ADC12_B_setSampleHoldSignallnversion ADC12 B setDataReadBackFormat ADC12 B enableReferenceBurst ADC12 B disableReferenceBurst ADC12 B setAdcPowerMode ADC12 B getMemoryAddressForDMA ADC12 B enable ADC12 B disable Programming Example The following example shows how to initialize and use the ADC12 B API to start a single channel with single conversion using an external positive reference for the ADC12 B Initialize the ADC12 Module Base address of ADC12 Module Use internal ADC12 bit as sample hold signal to start conversion USE MODOSC 5MHZ Digital Oscillator as clock source Use default clock divider pre divider of 1 Map to internal channel 0 x ADC12_B_init ADC12 B BASE ADC12 B SAMPLEHOLDSOURCE SC ADC12 B CLOCKSOURCE ADC120SC ADC12 B CLOCKDIVIDER 1 ADC12 B CLOCKPREDIVIDER 1 ADC12 B MAPINTCHO Enable the ADC12 B module ADC12 B enable ADC12 B BASE Base addre
20. 70500 33 TI Information Selective Disclosure Clock System CS 9 2 34 is granted the OFIE is not reset automatically as it is in previous MSP430 families It is no longer required to reset the OFIE NMI entry exit circuitry removes this requirement The OFIFG flag must be cleared by software The source of the fault can be identified by checking the individual fault bits If LFXT is sourcing any system clock ACLK MCLK or SMCLK and a fault is detected the system clock is automatically switched to LFMODCLK for its clock source The LFXT fault logic works in all power modes including LPM3 5 If HFXT is sourcing MCLK or SMCLK and a fault is detected the system clock is automatically switched to MODCLK for its clock source By default the HFXT fault logic works in all power modes except LPM3 5 or LPM4 5 because high frequency operation in these modes is not supported The fail safe logic does not change the respective SELA SELM and SELS bit settings The fail safe mechanism behaves the same in normal and bypass modes This driver is contained in cs_a c with cs_a h containing the API definitions for use by applica tions API Functions The CS API is broken into four groups of functions an API that initializes the clock module those that deal with clock configuration and control and external crystal and bypass specific configuration and initialization and those that handle interrupts General CS configuration and in
21. A decal 50 TO GPIO a ee 51 16 1 IMPONEN 2 nu Su 4 4 408 ra Pe A a DER OR A ee kn S 51 162 API Functions 2 nee Ka ee he AR ee Ree rn Pee ee ae DER 52 169 Frogramming EXSMpIE s ar aan de awe Ga ate Tae vk decid SK ar ice aks Re a 5 eR en cee ud a a ko a ee RRR a de 52 17 Memory Protection Unit MPU ara nta rone Ekru Sau 55 17 1 Inwoduchen RP ERR EAR REE ERA RR AA AAA ee 55 17 2 API FUNCIONS ee ARA A AA NR eee a A 55 122 Programming EXampie s ee a Ar ae ae ee toc SEP ay er rat ko een ana eal IR decade tar see Bay re 56 18 32 Bit Hardware Multiplier MPY32 lt lt lt lt eee 57 18 1 IMPONEN oro ore ERE RR EE A a db R OE o K KR ee A 57 2013 05 2009 07 070500 3 TI Information Selective Disclosure Table of Contents 192 DR PSC NOM S e ria E e ee ah Gen he i AI A eee ae Cd Sev an aR 16 Ge he daa dee Rhode eke ser 57 183 Programme Example om ee he a en 58 19 Power Management Module PMM 59 TEL AR BEE A an tc At Aad Ts Tame he ae EEE p gm avi ay es A as EEE WS cee Er ER ER G AOR IE ae gs Weve tate ie Bee oe 59 ar ERNIO 2 een sn Sy aye der Boe om A rear ae ee Gon Ge Sd tt ee my NR Be ey Ge chs de en 59 193 Programming Example 202 224 2 802 G dont JV Yee ee ee A Oe PE PE eee A na 59 20 internal Reference REF A lt lt o se u cd v 00 u vu a a a a a ROR 63 I o A O E Tepe Bind apost le SE dan car aa Bp jel kan Sl ough Pg laden Bee lamino en
22. I is broken into three groups of functions those that deal with timer configuration and control those that deal with timer contents and those that deal with interrupt handling 2013 05 2009 07 07_0500 TIMER B m TIMER B getinterruptStatus m TIMER B _enableCaptureComparelnterrupt m TIMER B disableCaptureComparelnterrupt m TIMER B getCaptureComparelnterruptStatus m TIMER B dlearCaptureComparelnterruptFlag m TIMER B dlearTimerlnterruptFlag 25 3 Programming Example The following example shows some TIMER B operations using the APIs Start TIMER_B TIMER_B_configureUpMode TIMER_BO_BASE TIMER_B_CLOCKSOURCE_SMCLK TIMER B CLOCKSOURCE DIVIDER 1 oe TIMER_B_TBIE_INTERRUPT_DISABLE TIMER_B_CCIE_CCRO_INTERRUPT_DISABLE TIMER_B_DO_CLEAR i TIMER_B_startCounter TIMER_BO_BASE TIMER_B_UP_MODE i Initialize compare mode to generate PWM1 TIMER_B_initCompare TIMER_BO_BASE TIMER_B_CAPTURECOMPARE_REGISTER_1 TIMER B CAPTURECOMPARE INTERRUPT DISABLE TIMER B OUTPUTMODE RESET SET 383 i Initialize compare mode to generate PWM2 TIMER_B_initCompare TIMER_BO_BASE TIMER_B_CAPTURECOMPARE_REGISTER_2 TIMER_B_CAPTURECOMPARE_INTERRUPT_ENABLE TIMER_B_OUTPUTMODE_RESET_SET 128 i 2013 05 2009 07 07_0500 77 TI Information Selective Disclosure TIMER_B 78 TI Information Selective Disclosure 2013 05 2009 07 07_0500 26 26 1 26 2 26 3 Tag Length Value Tag Length Value MON
23. I_B_12C 14 1 2 46 Master Single Byte Trasnmission m EUSCI B I2C masterSendSingleByte Master Mulitple Byte Transmission m EUSCI B I2C masterMultiByteSendStart m EUSCI B I2C masterMultiByteSendNext m EUSCI B I2C masterMultiByteSendStop Master Single Byte Reception m EUSCI B I2C masterReceiveStart m EUSCI B I2C masterSingleReceive Master Multiple Byte Reception m EUSCI B I2C masterMultiByteReceiveStart m EUSCI B I2C masterMultiByteReceiveNext m EUSCI B I2C masterMultiByteReceiveFinish m EUSCI B I2C masterMultiByteReceiveStop For the interrupt driven transaction the user must register an interrupt handler for the I2C devices and enable the 12C interrupt Slave Operations To drive the slave module the APIs need to be invoked in the following order m EUSCI B I2C slavelnit m EUSCI B I2C setMode m EUSCI B I2C enable m EUSCI B I2C enablelnterrupt if interrupts are being used This may be followed by the APIs for transmit or receive as required The user must first call the EUSCI B 12C slavelnit to initialize the slave module in I2C mode and set the slave address This is followed by a call to set the mode of operation transmit or receive The I2C module may now be enabled using EUSCI B 12C enable It is recommneded to en able the I2C module before enabling the interrupts Any transmission or reception of data may be initiated at this point after interrupts are enabled if any The transaction can then be initiated
24. MINUTECHANGE Enable interrupt for RTC Ready Status which asserts when the RTC Calendar registers are ready to read Also enable interrupts for the Calendar alarm and Calendar event RTC B enableInterrupt RTC B BASE RTCRDYIE RTCTEVIE Start RTC Clock RTCAIE RTC B startClock RTC B BASE Enter LPM3 mode with interrupts enabled bis SR register LPM3 bits GIE __no operation 66 2013 05 2009 07 070500 TI Information Selective Disclosure 22 22 1 22 2 22 3 SFR Module SFR Module DROW HON ae ee 67 Pe MG a RE er 67 PMEZ DNE sc ee 67 Introduction The Special Function Registers API provides a set of functions for using the MSP430Ware SFR module Functions are provided to enable and disable interrupts and control the RST NMI pin The SFR module can enable interrupts to be generated from other peripherals of the device This driver is contained in sfr c with sfr h containing the API definitions for use by applications API Functions The SFR API is broken into 2 groups the SFR interrupts and the SFR RST NMI pin control The SFR interrupts are handled by SFR_enablelnterrupt SFR_disablelnterrupt m SFR_getinterruptStatus m SFR dlearlnterrupt The SFR RST NMI pin is controlled by m SFR_setResetPinPullResistor m SFR_setNMIEdge m SFR setResetNMIPinFunction Programming Example The following example shows how to initialize and use the SFR API do
25. O to produce a secondary core voltage VCORE from the primary one applied to the device DVCC In general VCORE supplies the CPU memories and the digital modules while DVCC supplies the I Os and analog modules The VCORE output is maintained using a dedicated voltage reference The input or primary side of the regulator is referred to as its high side The output or secondary side is referred to as its low side 19 2 API Functions PMM_enableLowPowerReset PMM_disableLowPowerReset If enabled SVSH does not re set device but triggers a system NMI If disabled SVSH resets device PMM_enableSVSH PMM_disableSVSH If disabled on FR58xx FR59xx High side SVS SVSH is disabled in LPM2 LPM3 LPM4 LPM3 5 and LPM4 5 SVSH is always enabled in active mode LPMO and LPM1 If enabled SVSH is always enabled Note this API has different functionality depending on the part PMM_regOff PMM_regOn If off Regulator is turned off when going to LPM3 4 System enters LPM3 5 or LPM4 5 respectively If on Regulator remains on when going into LPM3 4 PMM_clearlnterrupt Clear selected or all interrupt flags for the PMM PMM_getinterruptStatus Returns interrupt status of the selected flag in the PMM module PMM_lockLPM5 PMM_unlockLPM5 If unlocked LPMx 5 configuration is not locked and de faults to its reset condition if locked LPMx 5 configuration remains locked Pin state is held during LPMx 5 entry and exit This driver is c
26. O errar 79 EPP RE IORS ae ea 79 Pregramming Example aan ea 79 Introduction The TLV structure is a table stored in flash memory that contains device specific information This table is read only and is write protected It contains important information for using and calibrating the device A list of the contents of the TLV is available in the device specific data sheet in the Device Descriptors section and an explanation on its functionality is available in the MSP430x5xx MSP430x6xx Family UserSs Guide This driver is contained in t1v c with t1v h containing the API definitions for use by applications API Functions The APIs that help in querying the information in the TLV structure are listed m TLV_getinfo This function retrieves the value of a tag and the length of the tag m TLV_getDeviceType This function retrieves the unique device ID from the TLV structure m TLV_getMemory The returned value is zero if the end of the memory list is reached m TLV_getPeripheral The returned value is zero if the specified tag value peripheral is not available in the device m TLV_getinterrupt The returned value is zero is the specified interrupt vector is not defined Programming Example The following example shows some tlv operations using the APIs struct s_TLV_Die_Record pDIEREC unsigned char bDieRecord_bytes TLV_get Info TLV_TAG_DIERECORD 0 F amp bDieRecord_bytes unsigned int xx amp pDIEREC 3 2013 05 2009 07
27. PORT_P1 GPIO_PIN4 i P1 4 Hi Lo edge GPIO_interruptEdgeSelect GPIO_PORT_P1 GPIO_PIN4 GPIO_HIGH_TO_LOW_TRANSITION i P1 4 IFG cleared GPIO clearInterruptFlag GPIO PORT PI GPIO PIN4 i Enter LPM4 w interrupt bis SR register LPM4 bits GIE For debugger __no operation TKK k k k k e KR ROR RRR AXA HH HH RR RR HH HH HH k k RARA k k k k KR This is the PORT1 VECTOR interrupt vector service routine J K k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k k ee k k k k k k k k k k k k k k k k k k k k k k k k k k k kk k k k k k k k k k k pragma vector PORT1_VECTOR __interrupt void Port 1 void P1 0 toggle GPIO_toggleOutputOnPin GPIO_PORT_P1 GPIO_PINO i P1 4 IFG cleared GPIO clearInterruptFlag GPIO PORT P1 GPIO PIN4 i 2013 05 2009 07 07_0500 53 TI Information Selective Disclosure GPIO 54 TI Information Selective Disclosure 2013 05 2009 07 07_0500 17 17 1 17 2 Memory Protection Unit MPU Memory Protection Unit MPU Lal ee HON EEE STEUER SEE ovn do kask d n kdo 25 VE ROT Uae ee a a o o ad VAE R o ts Sa la o AA 55 PMEZ DE see 56 Introduction The MPU protects against accidental writes to designated read only memory segments or execu tion of code from a constant memory segment memory Clearing the MPUENA bit disables the MPU making the complete memory accessible for read write and execute operations After a BOR the
28. T CS CLOCK DIVIDER 1 2013 05 2009 07 070500 35 TI Information Selective Disclosure Clock System CS 36 TI Information Selective Disclosure 2013 05 2009 07 07_0500 Direct Memory Access DMA 10 Direct Memory Access DMA A ete een aL er RR OU ee TORTEN reer eer reer ee cetera were eres eT a or AP NOS nen 37 PMEZ DNE see 38 10 1 Introduction The Direct Memory Access DMA API provides a set of functions for using the MSP430Ware DMA modules Functions are provided to initialize and setup each DMA channel with the source and destination addresses manage the interrupts for each channel and set bits that affect all DMA channels The DMA module provides the ability to move data from one address in the device to another and that includes other peripheral addresses to RAM or vice versa all without the actual use of the CPU Please be advised that the DMA module does halt the CPU for 2 cycles while transfering but does not have to edit any registers or anything The DMA can transfer by bytes or words at a time and will automatically increment or decrement the source or destination address if desired There are also 6 different modes to transfer by including single transfer block transfer and burst block transfer as well as repeated versions of those three different kinds which allows transfers to be repeated without having re enable transfers The DMA settings that affect all DMA channels include prioriti
29. TERRUPT DISABLE TIMER A DO CLEAR i TIMER_A_startCounter TIMER Al BASE TIMER A UPDOWN MODE i Initialze compare registers to generate PWM1 TIMER_A_initCompare TIMER Al BASE TIMER A CAPTURECOMPARE REGISTER 1 TIMER A CAPTURECOMPARE INTERRUPT ENABLE TIMER A OUTPUTMODE TOGGLE SET DUTY CYCLE1 i Initialze compare registers to generate PWM2 TIMER_A_initCompare TIMER Al BASE TIMER A CAPTURECOMPARE REGISTER 2 TIMER A CAPTURECOMPARE INTERRUPT DISABLE TIMER A OUTPUTMODE TOGGLE SET DUTY CYCLE2 i lt Enter LPMO __bis_SR_register LPMO_bits For debugger __no_operation 2013 05 2009 07 07_0500 TI Information Selective Disclosure 73 TIMER_A 74 TI Information Selective Disclosure 2013 05 2009 07 07_0500 TIMER B 25 TIMER B IMON o a a a a AEEA EAE ES 15 A ae OHR LEE re 76 Pregamnng Example a 77 25 1 Introduction TIMER_B is a 16 bit timer counter with multiple capture compare registers TIMER_B can support multiple capture compares PWM outputs and interval timing TIMER_B also has extensive inter rupt capabilities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers This peripheral API handles Timer B harware peripheral TIMER_B features include m Asynchronous 16 bit timer counter with four operating modes m Selectable and configurable clock source m Up to seven configurable capture compare regi
30. TI Information Selective Disclosure 19 TEXAS INSTRUMENTS MSP430 Peripheral Driver Library for FR5xx and FR6xx Devices USER S GUIDE Copyright 2013 Texas Instruments Incorporated Copyright Copyright 2013 Texas Instruments Incorporated All rights reserved MSP430 and 430ware are registered trademarks of Texas Instruments Other names and brands may be claimed as the property of others Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semicon ductor products and disclaimers thereto appears at the end of this document Texas Instruments I TEXAS ieee INSTRUMENTS http www ti com msp430 Revision Information This is version 1 40 01 00 of this document last updated on 2013 05 2009 07 070500 2 2013 05 2009 07 07_0500 TI Information Selective Disclosure Table of Contents Table of Contents GOBYTIghl O ne a AR A A Be ES a ee amp 2 Revision Information 2 c o 22 Be ae A N A Erin be 2 1 INIKOGJUEHON coa deo S ae a A a Re rn i Jeny oa ee ee ee 5 2 Navigating to driverlib through CCS Resource Explorer 2 222 ee eee ee 7 3 How to create a new user project that uses Driverlib 15 4 How to include driverlib into your existing project lt lt rn 17 5 12 Bit Analog to Digital Converter ADC12 B lt lt lt lt s e
31. USCI B SPI receiveData The SPI API is broken into 3 groups of functions those that deal with status and initialization those that handle data and those that manage interrupts The status and initialization of the SPI module are managed by m EUSCI B SP masterlnit EUSCI B SPI slavelnit EUSCI B SPI disable EUSCI B SPI enable EUSCI B SPI masterChangeClock EUSCI B SPI isBusy 2013 05 2009 07 070500 43 TI Information Selective Disclosure EUSCI Synchronous Peripheral Interface EUSCI_B_SPI 13 3 44 m EUSCI B SPI select4PinFunctionality m EUSCI B SPI changeClockPhasePolarity Data handling is done by m EUSCI B SPI transmitData m EUSCI B SPI receiveData Interrupts from the SPI module are managed using m EUSCI B SPI disablelnterrupt EUSCI B SPI enablelnterrupt m EUSCI B SPI getlnterruptStatus m EUSCI B SPI clearlnterruptFlag DMA related m EUSCI B SPI getReceiveBufferAddressForDMA m EUSCI B SPI getTransmitBufferAddressForDMA Programming Example The following example shows how to use the SPI API to configure the SPI module as a master device and how to do a simple send of data Initialize slave to MSB first inactive high clock polarity and 3 wire SPI returnValue EUSCI B SPI slaveInit EUSCI BO BASE BUSCI B SPI MSB FIRST EBUSCI B SPI PHASE DATA CHANGED ONFIRST CAPTURED ON NEXT EUSCI B SPI CLOCKPOLARITY INACTIVITY HIGH i if STATUS_FAIL returnValue return Enable SPI Modul
32. ality m EUSCI A SPI changeClockPhasePolarity Data handling is done by m EUSCI A SPI transmitData m EUSCI A SPI receiveData Interrupts from the SPI module are managed using m EUSCI A SPI disablelnterrupt EUSCI A SPI enablelnterrupt m EUSCI A SPI getlnterruptStatus m EUSCI A SPI clearlnterruptFlag DMA related m EUSCI A SPI getReceiveBufferAddressForDMA m EUSCI A SPI getTransmitBufferAddressForDMA Programming Example The following example shows how to use the SPI API to configure the SPI module as a master device and how to do a simple send of data Initialize slave to MSB first inactive high clock polarity and 3 wire SPI returnValue EUSCI A SPI slaveInit EUSCI A0 BASE BUSCI A SPI MSB FIRST EBEUSCI A SPI PHASE DATA CHANGED ONFIRST CAPTURED ON NEXT EUSCI A SPI CLOCKPOLARITY INACTIVITY HIGH i if STATUS_FAIL returnValue return Enable SPI Module EUSCI_A_SPI_enable EUSCI A0 BASE Enable Receive interrupt EUSCI A SPI enableInterrupt EUSCI A0 BASE EUSCI A SPI RECEIVE INTERRUPT i 2013 05 2009 07 07_0500 TI Information Selective Disclosure 13 13 1 13 2 EUSCI Synchronous Peripheral Interface EUSCI_B_SPI EUSCI Synchronous Peripheral Interface EUSCI_B_SPI Tit Tree S10 2 24 A a O O RR O OR V O PO NO ee 43 APEU HO cs so EA o NAAA o n AA re 43 Programming EAN A a A ea Eere E EEEO 44 Introduction The Serial Peripheral Interface Bus or SPI bus is a synchronou
33. als They are written entirely in C except where absolutely not possible They demonstrate how to use the peripheral in its common mode of operation They are easy to understand They are reasonably efficient in terms of memory and processor usage They are as self contained as possible Where possible computations that can be performed at compile time are done there instead of at run time They can be built with more than one tool chain Some consequences of these design goals are m The drivers are not necessarily as efficient as they could be from a code size and or execution speed point of view While the most efficient piece of code for operating a peripheral would be written in assembly and custom tailored to the specific requirements of the application further size optimizations of the drivers would make them more difficult to understand m The drivers do not support the full capabilities of the hardware Some of the peripherals provide complex capabilities which cannot be utilized by the drivers in this library though the existing code can be used as a reference upon which to add support for the additional capabilities m The APIs have a means of removing all error checking code Because the error checking is usually only useful during initial program development it can be removed to improve code size and speed For many applications the drivers can be used as is But in some cases the drivers will have to be enhanced or rewr
34. at give status of FRAM FRAM writes are managed by m FRAM vwrite8 m FRAM vwrite16 m FRAM _write32 FRAM memoryFill32 The FRAM interrupts are handled by 2013 05 2009 07 070500 49 TI Information Selective Disclosure FRAM Controller m FRAM enablelnterrupt m FRAM oetlnterruptStatus m FRAM disablelnterrupt The status is given by m FRAM status 15 3 Programming Example The following example shows some FRAM operations using the APIs Writes the value of data 128 times to FRAM FRAM_memoryFill32 FRAM BASE data unsigned long FRAM TEST START 128 50 2013 05 2009 07 070500 TI Information Selective Disclosure 16 16 1 GPIO GPIO MPR AAA an O 51 Pe TT A fe tr is che uate cae nd ahaa RER 52 Programming Bande sec ee 52 Introduction The Digital I O GPIO API provides a set of functions for using the MSP430Ware GPIO modules Functions are provided to setup and enable use of input output pins setting them up with or without interrupts and those that access the pin value The digital I O features include m Independently programmable individual I Os m Any combination of input or output Individually configurable P1 and P2 interrupts Some devices may include additional port interrupts m Independent input and output data registers m Individually configurable pullup or pulldown resistors Devices within the family may have up to twelve digital I O ports implemented P1 to P11 and PJ Most p
35. ate interrupts The I2C module configured as a master will generate interrupts when a transmit or receive operation is completed or aborted due to an error The I2C module configured as a slave will generate interrupts when data has been sent or requested by a master Master Operations To drive the master module the APIs need to be invoked in the following order m EUSCI B I2C masterlnit m EUSCI B I2C setSlaveAddress EUSCI B I2C setMode m EUSCI B I2C enable EUSCI B I2C enablelnterrupt if interrupts are being used This may be followed by the APIs for transmit or receive as required The user must first initialize the I2C module and configure it as a master with a call to EU SCI B I2C masterlnit That function will set the clock and data rates This is followed by a call to set the slave address with which the master intends to communicate with using EU SCI B I2C setSlaveAddress Then the mode of operation transmit or receieve is chosen using EUSCI B I2C setMode The I2C module may now be enabled using EUSCI B I2C enable It is recommneded to enable the EUSCI B I2C module before enabling the interrupts Any transmis sion or reception of data may be initiated at this point after interrupts are enabled if any The transaction can then be initiated on the bus by calling the transmit or receive related APIs as listed below 2013 05 2009 07 070500 45 TI Information Selective Disclosure EUSCI Inter Integrated Circuit EUSC
36. c12 b c Le adc12_b h aes256 c aes256 h comp_e c Le comp_e h Le CICE crc h Le cs c cs h Filter Types Deselect All Into folder MyProject driverlib Options Overwrite existing resources without warning If the user prefers to create a link to the original MSP430ware driverlib source header files then before clicking finish click on Advanced gt Create links in workspace Also pick how the files should be linked from the options in the SCreate link locations relative to Scombo box 18 2013 05 2009 07 070500 TI Information Selective Disclosure How to include driverlib into your existing project File system Import resources from the local file system From directory C ti ccs5 3 0 ccsv5 ccs_base msp430 MSP430ware_1_30_00_15 v gt ME MSP430FR5xx_6xx Le adc12 b c Le adc12 b h aes256 c aes256 h comp_e c Le comp_e h Le crc c Lo crc h cs c Ae Into folder MyProject driverlib Options Overwrite existing resources without warning Create top level Folder Create links in workspace Create virtual folders Create link locations relative to STEP2 In the project setting include the path of the driverlib source header files If the driverlib files are copied into project Include the following path 2013 05 2009 07 070500 19 TI Information Selective Disclosure How to include driverlib into your existing
37. complete memory is accessible without restrictions for read write and execute opera tions MPU features include m Main memory can be configured up to three segments of variable size m Access rights for each segment can be set independently m Information memory can have its access rights set independently m All MPU registers are protected from access by password This driver is contained in mpu c with mpu h containing the API definitions for use by applications API Functions The MPU API is broken into three group of functions those that handle initialization those that deal with memory segmentation and access rights definition and those that handle interrupts The MPU initialization function is MPU start The MPU memory segmentation and access right definition functions are m MPU_createTwoSegments m MPU_createThreeSegments The MPU interrupt handler functions MPU enablePUCOnViolation MPU disablePUCOnViolation MPU getlnterruptStatus MPU cdlearlnterruptFlag MPU_clearAlllnterruptFlags MPU_enableNMlevent 2013 05 2009 07 070500 55 TI Information Selective Disclosure Memory Protection Unit MPU 17 3 Programming Example 56 The following example shows some MPU operations using the APIs Define memory segment boundaries and set access right for each memory segment MPU_createThreeSegments MPU_BASE 0x04 0x08 MPU_READ MPU_WRITE MPU_EXEC MPU_READ MPU READ MPU WRITE MPU EXEC Configures MPU
38. e EUSCI B SPI enable EUSCI A0 BASE Enable Receive interrupt EUSCI B SPI enableInterrupt EUSCI A0 BASE EUSCI B SPI RECEIVE INTERRUPT i 2013 05 2009 07 07_0500 TI Information Selective Disclosure 14 14 1 14 1 1 EUSCI Inter Integrated Circuit EUSCI B I2C EUSCI Inter Integrated Circuit EUSCI B I2C MAOUE as KARET OR ee P O NOE OM R O RR O OR V O Te ee 45 APIF HO AAA AA o n A d ooo A 47 Programming Example ae 48 Introduction In I2C mode the eUSCI_B module provides an interface between the device and I2C compatible devices connected by the two wire 12C serial bus External components attached to the I2C bus serially transmit and or receive serial data to from the eUSCI_B module through the 2 wire 12C in terface The Inter Integrated Circuit I2C API provides a set of functions for using the MSP430Ware 12 modules Functions are provided to initialize the I2C modules to send and receive data obtain status and to manage interrupts for the I2C modules The I2C module provide the ability to communicate to other IC devices over an I2C bus The I2C bus is specified to support devices that can both transmit and receive write and read data Also devices on the I2C bus can be designated as either a master or a slave The MSP430Ware 12C modules support both sending and receiving data as either a master or a slave and also support the simultaneous operation as both a master and a slave 12C module can gener
39. e REF_A Internal Reference REF_A lle ae ee 63 EI a Re 63 POSEL DE sehe 64 Introduction The Internal Reference REF A API provides a set of functions for using the MSP430Ware REF A modules Functions are provided to setup and enable use of the Reference voltage enable or disable the internal temperature sensor and view the status of the inner workings of the REF A module The reference module REF is responsible for generation of all critical reference voltages that can be used by various analog peripherals in a given device The heart of the reference system is the bandgap from which all other references are derived by unity or non inverting gain stages The REFGEN sub system consists of the bandgap the bandgap bias and the non inverting buffer stage which generates the three primary voltage reference available in the system namely 1 2 V 2 0 V and 2 5 V In addition when enabled a buffered bandgap voltage is available This driver is contained in ref a c with ref a h containing the API definitions for use by appli cations API Functions The DMA API is broken into three groups of functions those that deal with the REF Aerence voltage those that handle the internal temperature sensor and those that return the status of the REF A module The REF Aerence voltage of the REF A module is handled by m REF A setReferenceVoltage m REF A enableReference VoltageOutput m REF A disableReference Voltage Output m REF A
40. e counter mode and interrupt condition setup and enable functions The RTC clock settings are handled by m RTC B startClock m RTC B holdClock RTC B setCalibrationFreguency m RTC B setCalibrationData The RTC Calender Mode is initialized and setup by m RTC B calenderlnit RTC B getCalenderTime m RTC B getPrescaleValue m RTC B setPrescaleValue The RTC interrupts are handled by m RTC B setCalenderAlarm m RTC B setCalenderEvent m RTC B definePrescaleEvent 2013 05 2009 07 070500 65 TI Information Selective Disclosure Real Time Clock RTC m RTC_B_enablelnterrupt m RTC B disablelnterrupt m RTC B oetlnterruptStatus m RTC B clearinterrupt The RTC conversions are handled by m RTC B convertBCDToBinary m RTC B convertBinaryToBCD 21 3 Programming Example The following example shows how to initialize and use the RTC API to setup Calender Mode with the current time and various interrupts Initialize Calendar Mode of RTC Base Address of the RTC_B_A Pass in current time intialized above Use BCD as Calendar Register Format RTC B calendarInit RTC B BASE currentTime RTC B FORMAT BCD Setup Calendar Alarm for 5 00pm on the 5th day of the week Note Does not specify day of the week RTC B setCalendarAlarm 0x00 0x17 RTC B ALARMCONDITIO 0x05 RTC B BASE OFF Specify an interrupt to assert every minute RTC B setCalendarEvent RTC B BASE RTC B CALENDAREVENT
41. e eee nn 21 S51 A Be ade we sky ce Gh ele ae p dn de Glee BA ae duchu ee ae ede ae ee 21 52 PL PUNGHONS occur carnada hee a R oc Ao RA A A Kluk kod dock 21 5 3 Programming Example 256 ss 4 86 4 8 a d a tata ka KB AA E ROK EO ew edd 22 6 Advanced Encryption Standard AES256 lt lt ee 25 Gj MISSION ve eat ae ee R en RAN 25 G2 APIUFUNCHONS 2 v una lt v OR ee bee ee Ee ee Rk 25 6 3 Programming Example 25 lt lt k 4 4 48s sos RE EP a O bee V K R A D e A 26 7 Comparator COMP JEJ cs ccc ec Beebe ah ee edad ERE SESE rare 27 21 gt MSG 2 4 o ha ae tees See et Bead Ad we ew ee ek ees aid db ed 27 T2 BPUPONCIONS d e ais sanpa A ee eee de A kodek ABO Ed eRe RSA GE a A eld 27 73 Programming Example z s ss eee Re EO a ewe a d A 28 8 Cyclical Redundancy Check CRC lt scios sca eee eee nn 31 1 ss os eae ee oe hee ee aS Re Ee ER ead Sa aa SASS baw Sa De BB 31 qe API FUNCIONS o 54 3 6 84 ee ee ee ee ede a RE A ee a ee El Pee 31 83 Programming Example se ua ke Se Ee a Ee ee OR 31 9 Glock System CS seces ra ORE E no era 33 SI le pe 3 1 3 ke eek dew r AA A 33 9 2 API FuNCHIONS 5 z ce 82 ha ke ee Saw ee 34 93 Programming Example 4 cc mu 0 88 RR Ee AAA RD ROE iod 35 10 Direct Memory Access DMA 4 4 ee eee 37 TOT CCUM so aaa re O a O O O O es 37 102 API Functions lt 2 z 4 ee An Ok B pe o AA RA EK K ee nb RD kA 37 10 3 Programming E
42. e gpio er catpatlll poeci and seich to the OCS Debug Perspective Addtonaly Pese are other methods lo start a prowct debug seamen Select the proyect m the Project Explorer wee and chok on Pe bug fooler button To relaunch e perous debug season cick on Pe snel eow Desde Pe bug fooler bulbo and selec one of Pe debug pesar for Pe hatory wu fe 18 Wie hear Poet hn top Winde m Ar R o 4 OM or El ost FS BRS Drummer H o tee a tome M gt 2 am gpio ex1 outputHi Write a Word to Port A Port Port These are the steps to import the project build the project and debug the project Step 1 Os Import the example protect into CCS V Ciel on Pe irk above lo pert Pe pect The mooted proyect a avatebe e Pe Project Explorer ven espard Pe proyect node lo Drama De ported source Mes To madly sorce code double choke oF Pe source fie mire Pe proyect lo open Pe soros Me editor g Step 2 amp Buld the imported proa A To change buks aptona ngt cich on e proyect and select Properties fom Me contest mens To uid Pe project select he ink above or select the Bald bode Sutton or select Se Project Hatid Project maru dem Step3 Y Debugger Configuration ww am nl ate ae Corrector mene Cock o Pe Ik above fo change Ihe Once Omen ADIOS Pos 0000 6 450 amade n Ihe proyect properties Step 4 Det he mooded ret sek on the link above fo launch a debug seamen for the g de ex oukpustl preci and swich fo the OCS Debug Perspective Addtcnaly
43. ecrypt data with keys that were generated during encryption takes 214 MCLK This function will generate all round keys needed for decryption first and then the encryption process starts AES256_decryptDataUsingEncryptionKey AES256_BASE DataAESencrypted DataAESdecrypted 26 2013 05 2009 07 07_0500 TI Information Selective Disclosure 7 1 7 2 Comparator COMP_E Comparator COMP E Lil eMe HON MOS PPR SE PPR PP TP PP P A R 27 a M A ET E A E Renee 27 Programming Bande see 28 Introduction The Comparator E COMP_E API provides a set of functions for using the MSP430Ware COMP_E modules Functions are provided to initialize the COMP_E modules setup reference voltages for input and manage interrupts for the COMP_E modules The COMP_E module provides the ability to compare two analog signals and use the output in software and on an output pin The output represents whether the signal on the positive terminal is higher than the signal on the negative terminal The COMP_E may be used to generate a hysteresis There are 16 different inputs that can be used as well as the ability to short 2 input together The COMP_E module also has control over the REF module to generate a reference voltage as an input The COMP_E module can generate multiple interrupts An interrupt may be asserted for the output with seperate interrupts on whether the output rises or falls This driver is contained in comp_e c with comp e h contain
44. enableReferenceVoltage m REF A disableReferenceVoltage The internal temperature sensor is handled by m REF A disable TempSensor m REF A enableTempSensor The status of the REF A module is handled by m REF A _getBandgapMode m REF A isBandgapActive m REF A isRefGenBusy 2013 05 2009 07 070500 63 TI Information Selective Disclosure Internal Reference REF_A 20 3 64 REF_A_isRefGenActive REF_A_getBufferedBandgapVoltageStatus REF_A_getVariableReferenceVoltageStatus REF_A_setReferenceVoltageOneTimeTrigger REF_A_setBufBandgapVoltageOneTimeTrigger Programming Example The following example shows how to initialize and use the REF_A API with the ADC12 module to use the internal 2 5V reference and perform a single converson on channel AO The conversion results are stored in ADC12BMEMO Test by applying a voltage to channel AO then setting and running to a break point atthe __no_operation instruction To view the conversion results open an ADC12B register window in debugger and view the contents of ADC12BMEMO Bas Use USE Use Map 1f ref generator busy WAIT while REF_A_isRefGenBusy REF_A_BASE Select internal ref 2 5V REF_A_setReferenceVoltage REF_A_BASE REF A VREF2 SV Internal Reference ON REF_A_enableReferenceVoltage REF_A_BASE Delay 75us for Ref to settle __delay_cycles 75 Initialize the ADC12 Module e address of ADC12 Module internal ADC12 bit
45. er am oo Sen 1 gt e Step 3 Y Debugger Conbauabon IS aoan w gu 22 roh e u Connection sone Y Cook n Pe ink above jo Rage Fe Groce Corrector Aurora Ma Geor 4 8180 En Me proect vpn propetes A uch Sep 4 Debug the imones pr nA as Cock oF Pe jrk above gt inch a debug seston ky Pe pato er ocupatii pec and seich to Me COS Debug u Perspective Asstona Pese are cer meins fo sist a prowe deOug essor Sec Pe sye m Me Project ora Explorer v v ard cick on Pe Dug Noir Sutton To relaunch 8 prevced Be season CK on Ne amt rum Desde Pe bug tower befor and esisel ore of Pe debug season tom fe ren Lon o and The COM port to download to can be changed using the Debugger Configuration option on the right if required To get started on a new project we recommend getting started on an empty project we provide This project has all the driverlib source files header files project paths are set by default CCS EGR TI Resource Explorer Code U fie oa Weer M de rt may Jeres Mr Fete rte 6 e El osa FS B4770 Ananas tte ve ern Den Pasa Al gt ve M 2 nex m ff lt ele u wen sear une EN D DO A IA om l mene U maroni peal Ben r Ban Comm Fy emptyProject N Toots 4 D traes Vo Empty Proyect Mat mciades tre une of drivertih e semcceernvemevmscnenereeseecnorarrnconscnerureneoucsneseresrassacrnsencones I vun ass wine O eet rome These are the steps to import the project build the
46. ference Voltage of 2 0 V Upper Limit of 2 0 32 32 2 0V Lower Limit of 2 0x 32 32 2 0V Static Accuracy x COMP E setReferenceVoltage COMP E BASE COMP_E_VREFBASE2_0V 32 32 COMP E ACCURACY STATIC i Disable Input Buffer on P1 2 CD2 Base Address of Comparator E Input Buffer port Selecting the CEx input pin to the comparator multiplexer with the CEx bits automatically disables output driver and input buffer for that pin regardless of the state of the associated CEPD x bit COMP_E_disableInputBuffer COMP_E_BASE COMP_E_INPUT2 Allow power to Comparator module COMP_E_enable COMP_E_BASE TI Information Selective Disclosure The following example shows how to initialize and use the COMP_E API to turn on an LED when the input to the positive terminal is highed than the input to the negative terminal terminal 2013 05 2009 07 07_0500 Comparator COMP_E __delay_cycles 400 delay for the reference to settle 2013 05 2009 07 070500 29 TI Information Selective Disclosure Comparator COMP_E 30 TI Information Selective Disclosure 2013 05 2009 07 07_0500 8 1 8 3 Cyclical Redundancy Check CRC Cyclical Redundancy Check CRC ll ee EEE o nn SER EEENENT TREE ELUOESERTERERBEUTR 31 VE as ER RER SEEREN SETE RAE eae 31 PAMA DE see 31 Introduction The Cyclic Redundancy Check CRC API provides a set of functions for using the MSP430Ware CRC module Functions are
47. ing the API definitions for use by applications API Functions The COMP_E API is broken into three groups of functions those that deal with initialization and output those that handle interrupts and those that handle auxillary features of the COMP_E The COMP E initialization and output functions are m COMP E init m COMP E setReferenceVoltage m COMP E enable m COMP E disable m COMP E outputValue m COMP E setPowerMode The COMP E interrupts are handled by m COMP E enablelnterrupt m COMP E disablelnterrupt m COMP E dlearlnterrupt m COMP E getlnterruptStatus m COMP E interruptSetEdgeDirection m COMP E interruptToggleEdgeDirection 2013 05 2009 07 070500 27 TI Information Selective Disclosure Comparator COMP_E 7 3 28 Auxilary features of the COMP_E are handled by COMP_E_enableShortOflnputs COMP_E_disableShortOflnputs COMP_E_disablelnputBuffer COMP E enablelnputBuffer COMP E IOSwap COMP E setReferenceAccuracy COMP E setPowerMode Programming Example Initialize the Comparator E module Base Address of Comparator E Pin CD2 to Positive Terminal Reference Voltage to Negative Terminal Normal Power Mode Output Filter On with minimal delay Non Inverted Output Polarity x COMP E init COMP E BASE COMP E INPUT2 COMP E VREF COMP E FILTEROUTPUT OFF COMP E NORMALOUTPUTPOLARITY i Set the reference voltage that is being supplied to the x Base Address of Comparator E Re
48. initions for use by applications Functions To use the module as a master the user must call EUSCI_A_SPI_masterlnit to configure the SPI Master This is followed by enabling the SPI module using EUSCI_A_SPI_enable The interrupts are then enabled if needed It is recommended to enable the SPI module before enabling the interrupts A data transmit is then initiated using EUSCI A SPI transmitData and then when the receive flag is set the received data is read using EUSCI A SPI receiveData and this indicates that an RX TX operation is complete To use the module as a slave initialization is done using EUSCI_A_SPI_slavelnit and this is followed by enabling the module using EUSCI_A_SPl_enable Following this the interrupts may be enabled as needed When the receive flag is set data is first transmitted using EU SCI A SPI transmitData and this is followed by a data reception by EUSCI_A_SPI_receiveData The SPI API is broken into 3 groups of functions those that deal with status and initialization those that handle data and those that manage interrupts The status and initialization of the SPI module are managed by m EUSCI_A_SPI_masterlnit EUSCI A SPI slavelnit EUSCI A SPI disable EUSCI A SPI enable EUSCI A SPI masterChangeClock EUSCI A SPI isBusy 2013 05 2009 07 070500 41 TI Information Selective Disclosure EUSCI Synchronous Peripheral Interface EUSCI_A_SPI 12 3 42 m EUSCI_A_SPI_select4PinFunction
49. ith programmable sampling periods controlled by software or timers m Conversion initiation by software or timers a Software selectable on chip reference voltage generation 1 2 V 2 0 V or 2 5 V with option to make available exter nally Software selectable internal or external reference Up to 32 individually configurable external input channels single ended or differential input selection available m Internal conversion channels for internal temperature sensor and 2 3 x AVCC and four more internal channels avail able on select devices see device data sheet for availability as well as function m Independent channel selectable reference sources for both positive and negative references m Selectable conversion clock source m Single channel repeat single channel sequence autoscan and repeat sequence repeated autoscan conversion modes m Interrupt vector register for fast decoding of 38 ADC interrupts 32 conversion result storage registers m Window comparator for low power monitoring of input signals of conversion result registers This driver is contained in adc12 b c with adc12 b h containing the API definitions for use by applications API Functions The ADC12_B API is broken into three groups of functions those that deal with initialization and conversions those that handle interrupts and those that handle auxillary features of the ADC12_B The ADC12_B initialization and conversion functions are 2013 05 2009 07 070
50. itialization are handled by the following API m CS_clockSignallnit m CS_enableClockRequest m CS_disableClockRequest m CS_getACLK m CS_getSMCLK m CS getMCLK m CS setDCOFreg The following external crystal and bypass specific configuration and initialization functions are avail able m CS LFXTStart m CS bypassLFXT m CS bypassLFXTWithTimeout m CS LFXTStartWithTimeout m CS LFXTOff m CS HFXTStart m CS bypassHFXT m CS HFXTStartWithTimeout m CS bypassHFXTWithTimeout m CS HFXTOff 2013 05 2009 07 070500 TI Information Selective Disclosure 9 3 Clock System CS m CS_VLOoff The CS interrupts are handled by m CS_enableClockRequest m CS_disableClockRequest m CS_faultFlagStatus m CS_clearFaultFlag m CS_clearAllOscFlagsWithTimeout CS_setExternalClockSource must be called if an external crystal LFXT or HFXT is used and the user intends to call CS_getMCLK CS_getSMCLK or CS_getACLK APIs and HFXTStart HFXTBy Pass HFXTStartWithTimeout HFXTByPassWithTimeout If not any of the previous API are going to be called it is not necessary to invoke this API Programming Example The following example shows the configuration of the CS module that sets SMCLK MCLK 8MHz Set DCO Frequency to 8MHz CS setDCOFreg CS BASE CS DCORSEL 0 CS DCOFSEL 6 configure MCLK SMCLK to be source by DCOCLK CS_clockSignalInit CS BASE CS_SMCLK CS_DCOCLK_SELECT CS CLOCK DIVIDER 1 CS clockSignalInit CS BASE CS MCLK CS DCOCLK SELEC
51. itten in order to meet the functionality memory or processing requirements of the application If so the existing driver can be used as a reference on how to operate the peripheral Each MSP430ware driverlib API takes in the base address of the corresponding peripheral as the first parameter This base address is obtained from the msp430 device specific header files or from the device datasheet The example code for the various peripherals show how base address is used When using CCS the eclipse shortcut Ctrl Space helps Type __MSP430 and Ctrl Space and the list of base addresses from the included device specific header files is listed The following tool chains are supported m IAR Embedded Workbench m Texas Instruments Code Composer Studio Using assert statements to debug Assert statements are disabled by default To enable the assert statement edit the hw_regaccess h file in the inc folder Comment out the statement define NDEBUG gt define NDEBUG Asserts in CCS work only if the project is optimized for size 2013 05 2009 07 070500 5 TI Information Selective Disclosure Introduction 6 2013 05 2009 07 070500 TI Information Selective Disclosure Navigating to driverlib through CCS Resource Explorer 2 Navigating to driverlib through CCS Resource Explorer In CCS click View gt TI Resource Explorer Too f r Code Comper Me tm Ree megas Peet fu ie Wier rep o Tl y oct 5 he a ona A
52. l Four system clock signals are available from the clock module m ACLK Auxiliary clock The ACLK is software selectable as LFXTCLK VLOCLK or LFMOD CLK ACLK can be divided by 1 2 4 8 16 or 32 ACLK is software selectable by individual peripheral modules m MCLK Master clock MCLK is software selectable as LFXTCLK VLOCLK LFMODCLK DCOCLK MODCLK or HFXTCLK MCLK can be divided by 1 2 4 8 16 or 32 MCLK is used by the CPU and system m SMCLK Sub system master clock SMCLK is software selectable as LFXTCLK VLOCLK LFMODCLK DCOCLK MODCLK or HFXTCLK SMCLK is software selectable by individual peripheral modules m MODCLK Module clock MODCLK may also be used by various peripheral modules and is sourced by MODOSC m VLOCLK VLO clock VLOCLK may also be used directly by various peripheral modules and is sourced by VLO Fail Safe logic The crystal oscillator faults are set if the corresponding crystal oscillator is turned on and not operating properly Once set the fault bits remain set until reset in software regardless if the fault condition no longer exists If the user clears the fault bits and the fault condition still exists the fault bits are automatically set otherwise they remain cleared The OFIFG oscillator fault interrupt flag is set and latched at POR or when any oscillator fault is detected When OFIFG is set and OFIE is set the OFIFG requests a user NMI When the interrupt 2013 05 2009 07 0
53. m to be compared for later crcResult CRC getResult CRC BASE 32 2013 05 2009 07 070500 TI Information Selective Disclosure 9 1 Clock System CS Clock System CS PRT HON k Bado EURE do a ata dane deans een eater dokola 33 VE Al 286 0 nee 34 PM Bande see 35 Introduction The clock system module supports low system cost and low power consumption Using three inter nal clock signals the user can select the best balance of performance and low power consumption The clock module can be configured to operate without any external components with one or two external crystals or with resonators under full software control The clock system module includes the following clock sources m LFXTCLK Low frequency oscillator that can be used either with low frequency 32768 Hz watch crystals standard crystals resonators or external clock sources in the 50 kHz or below range When in bypass mode LFXTCLK can be driven with an external square wave signal m VLOCLK Internal very low power low frequency oscillator with 10 kHz typical frequency m DCOCLK Internal digitally controlled oscillator DCO with selectable frequencies m MODCLK Internal low power oscillator with 5 MHz typical frequency LFMODCLK is MOD CLK divided by 128 m HFXTCLK High frequency oscillator that can be used with standard crystals or resonators in the 4 MHz to 24 MHz range When in bypass mode HFXTCLK can be driven with an external square wave signa
54. more a Lo Project bpe Ek rems O w B sopera orae Z ieot org mens tome O amory wone T epim tas Mo conection to Gagtny at the tme toute Land O tans cats In Resource Explorer View click on MSP430ware 2013 05 2009 07 070500 TI Information Selective Disclosure Navigating to driverlib through CCS Resource Explorer COOOL Y terco iphone Code Composer Suto TI lt gt gt mE i OF ye paga een ba Soe dom te D oven e 4 Terror Latoa a z x k TI Resource Explorer Baci Forward These are some availabte examples and documentation that you can download and install click on the ink for more ind O Configure Resource Explorer to discover installed examples and documentation o 7 Pto It Nee Corn La dir at Ves Come im rar emoce Pat ates Clicking MSP430ware takes you to the introductory page The version of the latest MSP430ware installed is available in this page In this screenshot the version is 1 30 00 15 The various software collateral code examples datasheets and user guides can be navigated by clicking the different topics under MSP430ware To proceed to driverlib click on Libraries gt Driverlib as shown in the next two screenshots CCS k r T tevource Cupioros Code Composer Shodo lt A E O fe dk pen pyc fot en Sop rd opp E E O E Made O cru 8 2013 05 2009 07 070500 TI Information Selective Disclosure Navigating to driverlib through CCS Resou
55. n Selective Disclosure How to create a new user project that uses Driverlib 3 How to create a new user project that uses Driverlib To get started on a new project we recommend getting started on an empty project we provide This project has all the driverlib source files header files project paths are set by default OO o Untere Code coena udo u Em gt mc Me bm Wie free rm an dens Winden Mk rye 4 9 E coso FES D Ti Resosce Explorer e mm rasm raams an tee m ras o dob el y haben Ms dy hh ANI AA ond po Y ekono macros ni seai e Erro de n py Qon i m emptyProject Diem e Y mtb Empry Proyect the de e anne el dh e Y JO se P gt fe These are the steps to import the project build the project and debug the project tagte Projects 6 A I vun Gade ep 1 impo Ihe example pros info CCS i Y Ser e Project Explorer A s MARA to I vers Gate Fe kn gt e Proper e me W outer try sis o ink above eet Pe Bf ne oe Project Build Project E UB eras Package WO capaci Pouch Seren trary wp3 Y Debugger Confious none 4 Y Debug c p mn gt oo nut to OCS Debug Pepe bre ote ot de o vor lt Project 7 a er n E tems ne The main c included with the empty project can be modified to include user code 2013 05 2009 07 070500 15 TI Information Selective Disclosure How to create a new user project that uses Driverlib 16 2013 05 2009 07 070500 TI Information Selecti
56. n counter overflow conditions and during capture compare evenis The TIMER A may also be used to generate PWM outputs PWM outputs can be generated by initializing the compare mode with TIMER A initCompare and the necessary parameters The PWM may be customized by selecting a desired timer mode continuous up upDown duty cycle output mode timer period etc The library also provides a simpler way to generate PWM using TIMER A generatePWM API However the level of customization and the kinds of PWM gener ated are limited in this API Depending on how complex the PWM is and what level of customization is required the user can use TIMER A generatePWM or a combination of Timer initComparef and timer start APIs The TIMER A API provides a set of functions for dealing with the TIMER A module Functions are provided to configure and control the timer along with functions to modify timer counter values and to manage interrupt handling for the timer Control is also provided over interrupt sources and events Interrupts can be generated to indicate that an event has been captured This driver is contained in TIMER A c with TIMER A h containing the API definitions for use by applications 2013 05 2009 07 070500 71 TI Information Selective Disclosure TIMER_A 24 2 API Functions The TIMER_A API is broken into three groups of functions those that deal with timer configuration and control those that deal with timer contents
57. nitions for use by applications API Functions The AES256 module APIs are m AES256_setCipherKey m AES256256_setCipherKey m AES256 encryptData m AES256_decryptDataUsingEncryptionKey m AES256 generateFirstRoundkey m AES256 decryptData m AES256 reset m AES256 startEncryptData 2013 05 2009 07 070500 25 TI Information Selective Disclosure Advanced Encryption Standard AES256 m AES256_startDecryptDataUsingEncryptionKey m AES256_startDecryptData m AES256_startGenerateFirstRoundKey m AES256_getDataOut The AES256 interrupt handler functions m AES256_enablelnterrupt m AES256_disablelnterrupt m AES256 clearlnterruptFlag 6 3 Programming Example The following example shows some AES256 operations using the APIs unsigned char Data 16 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 0x30 I unsigned char CipherKey 32 OxAA OxBB 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A Ox0B 0x0C Ox0D 0x0E Ox0F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 I unsigned char DataAESencrypted 16 Encrypted data unsigned char DataAESdecrypted 16 Decrypted data Load a cipher key to module AES256_setCipherKey AES256_BASE CipherKey Key_256BIT Encrypt data with preloaded cipher key AES256_encryptData AES256_BASE Data DataAESencrypted D
58. o given reference voltages The module implements a 12 bit SAR core sample select control and up to 32 independent conversion and control buffers The conversion and control buffer allows up to 32 independent analog to digital converter ADC samples to be converted and stored without any CPU intervention The ADC12_B can also generate digital values from 0 to Vcc with an 8 10 or 12 bit resolution and it can operate in 2 different sampling modes and 4 different conversion modes The sampling modes are extended sampling and pulse sampling in extended sampling the sample hold signal must stay high for the duration of sampling while in pulse mode a sampling timer is setup to start on a rising edge of the sample hold signal and sample for a specified amount of clock cycles The 4 conversion modes are single channel single conversion sequence of channels single conversion repeated single channel conversions and repeated sequence of channels conversions The ADC12_B module can generate multiple interrupts An interrupt can be asserted for each memory buffer when a conversion is complete or when a conversion is about to overwrite the converted data in any of the memory buffers before it has been read out and or when a conversion is about to start before the last conversion is complete ADC12_B features include m 200 ksps maximum conversion rate at maximum resolution of 12 bits m Monotonic 12 bit converter with no missing codes m Sample and hold w
59. o use the EUSI UART API to initialize the EUSI UART transmit characters and receive characters Configure UART if STATUS FAIL EUSCI_A_UART_init EUSCI_AO_BASE EUSCI A UART CLOCKSOURCE ACIK CLOCK VALUE 32768 EUSCI A UART NO PARITY EUSCI A UART LSB FIRST EUSCI A UART ONE STOP BIT EUSCI A UART MODE EUSCI A UART LOW FREQUENCY BAUDRATE GENERATION return EUSCI_A_UART_enable EUSCI A0 BASE Enable USCI_AO RX interrupt EUSCI_A_UART_enableInterrupt EUSCI A0 BASE EUSCI_A_UART_RECEIVE_INTERRUPT 2013 05 2009 07 07_0500 TI Information Selective Disclosure 12 12 1 12 2 EUSCI Synchronous Peripheral Interface EUSCI_A_SPI EUSCI Synchronous Peripheral Interface EUSCI_A_SPI A a En Er TE Ta et 41 PE HNS O AA NAAA A A AAA 41 Programming EAN A A 42 Introduction The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode Devices communicate in master slave mode where the master device initiates the data frame This library provides the API for handling a SPI communication using EUSCI The SPI module can be configured as either a master or a slave device The SPI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the module s input clock This driver is contained in eusci_a_spi c With eusci_a_spi h containing the API def
60. ontained in pmm c with pmm h containing the API definitions for use by applications 19 3 Programming Example Unlock the GPIO pins Base Address of Comparator D By default the pins are unlocked unless waking 2013 05 2009 07 070500 59 TI Information Selective Disclosure Power Management Module PMM up from an LPMx 5 state in which case all GPIO are previously locked x PMM_unlockLPM5 PMM BASE Get Interrupt Status from the PMMIFG register x Base Address of Comparator D mask PMM PMMBORIFG PMM PMMRSTIFG PMM PMMPORIFG PMM_SVSLIFG PMM_SVSHIFG PMM_PMMLPM5IFG return STATUS_SUCCESS 0x01 or STATUS_FAIL 0x00 x if PMM_getInterruptStatus PMM BASE PMM PMMLPM5IFG Clear Interrupt Flag from the PMMIFG register x Base Address of Comparator D mask PMM_PMMBORIFG PMM_PMMRSTIFG PMM_PMMPORIFG PMM_SVSLIFG PMM_SVSHIFG PMM PMMLPM5IFG PMM ALL PMM_clearInterrupt PMM BASE PMM PMMLPM5IFG if PMM getInterruptStatus PMM BASE PMM PMMRSTIFG PMM clearInterrupt PMM BASE PMM_PMMRSTIFG __delay_cycles 1000000 Lock GPIO output states before triggering a BOR Base Address of Comparator D Forces all GPIO to retain their output states during a reset x PMM_lockLPM5 PMM BASE Trigger a software Brown Out Reset BOR Base Address of Comparator D Forces the devices to perform a BOR x PMM trigBOR PMM BASE if PMM_getInterruptStatus PMM BASE
61. orts contain eight I O lines however some ports may contain less see the device specific data sheet for ports available Each I O line is individually configurable for input or output direction and each can be individually read or written Each I O line is individually configurable for pullup or pulldown resistors PJ contains only four I O lines Ports P1 and P2 always have interrupt capability Each interrupt for the P1 and P2 I O lines can be individually enabled and configured to provide an interrupt on a rising or falling edge of an input signal All P1 I O lines source a single interrupt vector P1IV and all P2 I O lines source a different single interrupt vector P2IV On some devices additional ports with interrupt capability may be available see the device specific data sheet for details and contain their own respective interrupt vectors Individual ports can be accessed as byte wide ports or can be combined into word wide ports and accessed via word formats Port pairs P1 P2 P3 P4 P5 P6 P7 P8 etc are associated with the names PA PB PC PD etc respectively All port registers are handled in this manner with this naming convention except for the interrupt vector registers P1IV and P2IV that is PAIV does not exist When writing to port PA with word operations all 16 bits are written to the port When writing to the lower byte of the PA port using byte operations the upper byte remains unchanged Similarly writing to the upper b
62. project and debug the project NE Comets peas e IA m P Step 1 impor he example proa nto CCS y Me ai raters E ret rome Cock on the Ink above fo emport Pe proyect The mported proyect a saisie Pe Project Explorer ves expard Pe O Crete ans Prorec node lo browse Pe emported source Mes To modify source code double coches on Pe source Me thn Pe RO reo oper Me nme fe etter I rr Gade M Step 2 4 Bull ihe imported project To Change Ould opt ght abc On Pe proyect and select Properties trom he content mery To build the prospect AP ota ray select Pe iak KOV OF ect e Bill Polar Sutton or select Fre Project Dasig Project mer de A ua lag Package U cra Touch Seren rar Sep 3 Y Debugger Confozaico Corrector sone Gick on the ink above fo change Pe dewce corrector Addtonaly Pra opfion aizo avelsbe n Pe proyect properties Step 4 Y Debug the imported project Chok OF Pe ink Kv ID n 4 dan ron for Pe EMP promo and satah to Pe CCS Dodog Perspective Ad tonely Meee we ENDE O Stat amp ect Ber season Select Pe proyect m Pe Project Enp orws ros 000 Och OF Pe Dr er Ino OOM y Dres MO 50550 CA 00 he ome W700 Desde Pe Dug AIT Dhar A SCT One Of IME Ang Deon fom Pe Musi The main c included with the empty project can be modified to include user code 2013 05 2009 07 070500 TI Information Selective Disclosure Navigating to driverlib through CCS Resource Explorer 14 2013 05 2009 07 070500 TI Informatio
63. provided to initialize the CRC and create a CRC signature to check the validity of data This is mostly useful in the communication of data or as a startup procedure to as a more complex and accurate check of data The CRC module offers no interrupts and is used only to generate CRC signatures to verify against pre made CRC signatures Checksums This driver is contained in crc c with crc h containing the API definitions for use by applications API Functions The CRC API is one group that controls the CRC module m CRC setSeed m CRC_setDataByte m CRC setDataWord m CRC setSignatureByteReversed m CRC getSignature m CRC ogetResult m CRC getResultBitReversed Programming Example The following example shows how to initialize and use the CRC API to generate a CRC signature on an array of data that can be included in a UART message with the data to check for validity unsigned int crcSeed OxBEEF unsigned int data 0x0123 0x4567 0x8910 0x1112 0x1314 unsigned int crcResult ine 1 Stop WDT 2013 05 2009 07 07_0500 31 TI Information Selective Disclosure Cyclical Redundancy Check CRC WDT hold WDT A BASE Set P1 0 as an output GPIO_setAsOutputPin GPIO_PORT_P1 GPIO_PINO Set the CRC seed CRC_setSeed CRC BASE crcSeed for i 0 i lt 5 i Add all of the values into the CRC signature CRC_setDataWord CRC BASE data i Save the current CRC signature checksu
64. r AAT AE EEA AE A ET TETEE 49 AP PCOS ne 49 PoE Example see 50 15 1 Introduction FRAM memory is a non volatile memory that reads and writes like standard SRAM The MSP430 FRAM memory features include m Byte or word write access m Automatic and programmable wait state control with independent wait state settings for access and cycle times m Error Correction Code with bit error correction extended bit error detection and flag indicators m Cache for fast read m Power control for disabling FRAM on non usage This driver is contained in fram c With fram h containing the API definitions for use by applica tions 15 2 API Functions FRAM enablelnterrupt enables selected FRAM interrupt sources FRAM getlnterruptStatus returns the status of the selected FRAM interrupt flags FRAM disablelnterrupt disables selected FRAM interrupt sources Depending on the kind of writes being performed to the FRAM this library provides APIs for FRAM writes FRAM write8 facilitates writing into the FRAM memory in byte format FRAM write16 facilitates writing into the FRAM memory in word format FRAM write32 facilitates writing into the FRAM memory in long format pass by reference FRAM memoryFill32 facilitates writing into the FRAM memory in long format pass by value FRAM status checks if the FRAM is currently busy pro gramming The FRAM API is broken into 3 groups of functions those that write into FRAM those that handle interrupts and those th
65. rce Explorer sat 1 cioe C6 55 E OE O te dt Meer pyte pet ba Soga Window telo 6 4 O s ne bug T Peed Loire 8 E wanna he Nie Te SVCD Janet OPPA Ogre X O IN Be OA Omara PDA Dawe Id ja Bret Cr Driverlib is designed per Family If a common device family userSs guide exists for a group of devices these devices belong to the same SfamilyS Currently driverlib is available for the following family of devices MSP430F5xx_6xx MSP430FR57xx MSP430FR5xx_6xx est terca Cupieror Code Cm te O O O y Die M em pore fen pn os jde ope f gt mm a 5 y Project Explorer T Resource Late MSP430ware Welcome to Click on the MSP430FR5xx_6xx to navigate to the driverlib based example code for that family 2013 05 2009 07 070500 9 TI Information Selective Disclosure Navigating to driverlib through CCS Resource Explorer Fe Trance love Code Comp co EEE RR CR Ea X Yew rats Poet Bun Sopu Window io a The various peripherals are listed in alphabetical order The names of peripherals are as in device family userSs guide Clicking on a peripheral name lists the driverlib example code for that peripheral The screenshot below shows an example when the user clicks on GPIO peripheral o hh TT TTT a fe R ven fete fort En Sort Mine tbl a gpio ex1 outputHi aade These are the steps to import the project build the project and debug the project wm mos e m e owe Now click on the
66. rce and header files are linked to the example projects So if the user modifies any of these source or header files the original copy of the installed MSP430ware driverlib source and header files get modified 2013 05 2009 07 070500 11 TI Information Selective Disclosure Navigating to driverlib through CCS Resource Explorer E CCS C41 TI Revource Explorer Code Comparar Sido ge La yu eee Ort Be foe Eee tue f3 amp DE G R RE DE T osos GS BTTO Drnemre tal H ws ni pce o overs a opus M o asten gpio_ex1_outputHi Write a Word te Por A Partt Port These are the steps to import the project build the project and debug the project Step 1 Ga import the example project into CCS y Chick on fre ink above fo mpor the project The mooted project a spisce n te Project Explorer v r expand Pe proyect node lo Drau the mported source fes To modiy source code double cicka on the source fie mitten the pruect to open Pe source Nie edi Stop 2 Buki the ported project Y Te Merge id OA A CCM OF Pe rol ar select Properties 0 Pe cortar mew To Dil Me pret telnet De lnk ao oF Select Pe Build fooler Outton o select Pe Project Dud Project merw dem Slep 3 X Detsager Corhouabco Gormecton mone Chok on Pe ink above fo Change Pe dente corrector Aditonay Pos option is also avelable n Pe proyect proever Step 4 Deka De imparted prost Gack on fre link above fo launch a debug season for P
67. regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio arm Data Converters dataconverter ti com Automotive ee ee DLP Products WON m BL Broadband www ti com digitalcontrol DSP dsp ti com Digital Control Clocks and Timers www ti com clocks Medical aren TSome mealies Interface interface ti com Military event tL conv military Logic logic ti com Optical Networking www ti com opticalnetwork Power Mgmt power ti com Security www ti com security Microcontrollers microcontroller ti com Telephony www ti com telephony RFID www ti rfid com Video amp Imaging www ti com video RF IF and ZigBee Solutions www ti com Iprf Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2013 Texas Instruments Incorporated 84 2013 05 2009 07 070500 TI Information Selective Disclosure
68. s driver is contained in gpio c With gpio h containing the API definitions for use by applica tions API Functions The GPIO API is broken into three groups of functions those that deal with configuring the GPIO pins those that deal with interrupts and those that access the pin value The GPIO pins are configured with m GPIO_setAsOutputPin m GPIO_setAsInputPin m GPIO setAsInputPinWithPullDownresistor m GPIO_setAsInputPinWithPullUpresistor m GPIO_setAsPeripheralModuleFunctionOutputPin m GPIO_setAsPeripheralModuleFunctionInputPin The GPIO interrupts are handled with m GPIO_enablelnterrupt m GPIO_disblelnterrupt m GPIO clearlnterruptFlag m GPIO getlnterruptStatus m GPIO_interruptEdgeSelect The GPIO pin state is accessed with m GPIO_setOutputHighOnPin m GPIO_setOutputLowOnPin m GPIO toggleOutputOnPin m GPIO getlnputPinValue Programming Example The following example shows how to use the GPIO API A trigger is generated on a hi TO low transition on P1 4 pulled up input pin which will generate P1 ISR In the ISR we toggle P1 0 output pin 2013 05 2009 07 070500 TI Information Selective Disclosure GPIO Set P1 0 to output direction GPIO_setAsOutputPin GPIO_PORT_P1 GPIO_PINO i Enable P1 4 internal resistance as pull Up resistance GPIO_setAsInputPinWithPullUpresistor GPIO_PORT_P1 GPIO_PIN4 i P1 4 interrupt enabled GPIO_enablelnterrupt GPIO_
69. s serial data link standard named by Motorola that operates in full duplex mode Devices communicate in master slave mode where the master device initiates the data frame This library provides the API for handling a SPI communication using EUSCI The SPI module can be configured as either a master or a slave device The SPI module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the module s input clock This driver is contained in eusci_b_spi c with eusci_b_spi h containing the API definitions for use by applications Functions To use the module as a master the user must call EUSCI_B_SPI_masterlnit to configure the SPI Master This is followed by enabling the SPI module using EUSCI B SPI enable The interrupts are then enabled if needed It is recommended to enable the SPI module before enabling the interrupts A data transmit is then initiated using EUSCI_B_SPI_transmitData and then when the receive flag is set the received data is read using EUSCI B SPI receiveData and this indicates that an RX TX operation is complete To use the module as a slave initialization is done using EUSCI_B_SPI_slavelnit and this is followed by enabling the module using EUSCI_B_SPI_enable Following this the interrupts may be enabled as needed When the receive flag is set data is first transmitted using EU SCI B SPI transmitData and this is followed by a data reception by E
70. se a A ae Oo eh ee A br 75 orl OOO y a eK eee Bee le ew Ad AR A ee Sok cae te I EL Ed ae ar oe BA ae ee 75 22 A P LAM NON 65 aaa koe Ga GS a eh ee Seas ee aaa t v es ye ae ete a da km Resa atl Speen RA 76 233 PRO m EXAMP a 0 a we a OR a ee a A Oe ee ae A Ba Far AA 77 26 Tag Length Val e je i c 408002 an ae ww ee REA E 79 SB MOOG SGE 0200 ne ee to a RAR dean A ae eo eet Bee ak ede et mow ah Se hte ee 79 202 AR PUNCS A at ag E el ta a Aa ah Be Pee a BE Ro di RED eee im aye om ee Er 79 26 2 Progamming Example 5 43 ee ha Rea a AE Ge Ee ee Oe a le Dae B o Pa ee ae 8 79 27 WatchDog TimerQVDT A is sa Kara ee A dB ee Ta en 81 27 OONO a AN 81 27 2 AR EAN 73 a a a OS oR en rer a DA 1 Re ao ge n a ASA AA vB nt a ee gm BE 81 223 Programing EXAME ociosos aaa We wee ee A A A A RR 81 IMPORTANT NOTICE 050 A A eR ee RE a en 84 4 2013 05 2009 07 070500 TI Information Selective Disclosure Introduction 1 Introduction The Texas Instruments MSP430 Peripheral Driver Library is a set of drivers for accessing the peripherals found on the MSP430 FR5xx FR6xx family of microcontrollers While they are not drivers in the pure operating system sense that is they do not have a common interface and do not connect into a global device driver infrastructure they do provide a mechanism that makes it easy to use the device s peripherals The capabilities and organization of the drivers are governed by the following design go
71. ss of ADC12 Module For memory buffers 0 7 sample hold for 16 clock cycles 2013 05 2009 07 TI Information Selective Disclosure 07_0500 12 Bit Analog to Digital Converter ADC12_B For memory buffers 8 15 sample hold for 4 clock cycles default Disable Multiple Sampling x ADC12 B setupSamplingTimer ADC12 B BASE ADC12_B_CYCLEHOLD_16_CYCLES ADC12_B_CYCLEHOLD_4_CYCLES ADC12_B_MULTIPLESAMPLESDISABLE Configure Memory Buffer Base address of the ADC12 Module Configure memory buffer 0 Map input AO to memory buffer 0 Vref AVcc Vref EXT Positive Memory buffer 0 is not the end of a sequence x ADC12 B memoryConfigure ADC12 B BASE ADC12 B MEMORY 0 ADC12 B INPUT A0 ADC12 B VREFPOS EXTPOS VREFNEG VSS ADC12 B NOTENDOFSEOUENCE ADC12 B WINDOW COMPARATOR DISABLE ADC12 B DIFFERENTIAL MODE DISABLE while 1 Enable Start first sampling and conversion cycle Base address of ADC12 Module Start the conversion into memory buffer 0 Use the single channel single conversion mode x ADC12_B_startConversion ADC12 B BASE ADC12 B MEMORY 0 ADC12 B SINGLECHANNEL Poll for interrupt on memory buffer 0 while ADC12 B getInterruptStatus ADC12 B BASE 0 ADC12 B IFG0 __no_operation SET BREAKPOINT HERE 2013 05 2009 07 070500 TI Information Selective Disclosure 23 12 Bit Analog to Digital Converter ADC12_B 24 TI Information Selective Disclosure 2013 05 2009 07
72. sters m Configurable outputs with pulse width modulation PWM capability m Asynchronous input and output latching m Interrupt vector register for fast decoding of all Timer B interrupts Differences From Timer_A Timer_B is identical to Timer_A with the following exceptions m The length of Timer B is programmable to be 8 10 12 or 16 bits m Timer B TBxCCRn registers are double buffered and can be grouped m All Timer B outputs can be put into a high impedance state m The SCCI bit function is not implemented in Timer B TIMER_B can operate in 3 modes m Continuous Mode m Up Mode Down Mode TIMER B Interrupts may be generated on counter overflow conditions and during capture compare evenis The TIMER B may also be used to generate PWM outputs PWM outputs can be generated by initializing the compare mode with TIMER B initCompare and the necessary parameters The PWM may be customized by selecting a desired timer mode continuous up upDown duty cycle output mode timer period etc The library also provides a simpler way to generate PWM using TIMER B generatePWM API However the level of customization and the kinds of PWM gener ated are limited in this API Depending on how complex the PWM is and what level of customization is required the user can use TIMER B generatePWM or a combination of Timer initComparef and timer start APIs 2013 05 2009 07 070500 75 TI Information Selective Disclosure TIMER_B 25 2 76
73. t Sending and receiving data from the I2C slave module is handled by EUSCI B I2C masterSendSingleByte EUSCI B I2C masterSendStart EUSCI B I2C masterMultiByteSendStart EUSCI B I2C masterMultiByteSendNext EUSCI B I2C masterMultiByteSenaFinish EUSCI B I2C masterMultiByteSendStop 2013 05 2009 07 070500 47 TI Information Selective Disclosure EUSCI Inter Integrated Circuit EUSCI_B_12C EUSCI B I2C masterMultiByteReceiveNext EUSCI B I2C masterMultiByteReceiveFinish EUSCI B I2C masterMultiByteReceiveStop EUSCI B I2C masterReceiveStart EUSCI B I2C masterSingleReceive EUSCI B I2C getReceiveBufferAddressForDMA EUSCI B I2C getTransmitBufferAddressForDMA DMA related m EUSCI B I2C getReceiveBufferAddressForDMA m EUSCI B I2C getTransmitBufferAddressForDMA 14 3 Programming Example 48 The following example shows how to use the I2C API to send data as a master Initialize Slave EUSCI_B_I2C_slavelnit EUSCI_B_BO_BASE 0x48 EUSC EUSC Set in receive B_I2C_OWN_ADDRESS_OFFSETO B_I2C_OWN_ADDRESS_ENABLE mode EUSCI_B_I2C_setMode EUSCI_BO_BASE EUSC EUSCI_B_I2C_enab EUSCI B I2C enabl EUSC B I2C TRANSMIT MODE le EUSCI BO BASE leInterrupt EUSCI BO BASE B I2C TRANSMIT INTERRUPTO0 EUSC _B_I2C_STOP_INTERRUPT 2013 05 2009 07 07_0500 TI Information Selective Disclosure FRAM Controller 15 FRAM Controller ul hate Te Me DATE EEE ee eee ree te ener RR U tee Te
74. tResulti6Bit m MPY32 getResult24Bit 2013 05 2009 07 070500 57 TI Information Selective Disclosure 32 Bit Hardware Multiplier MPY32 MPY32 getResult32Bit MPY32 getResult64Bit MPY32 getSumExtension MPY32 getCarryBitValue 18 3 Programming Example The following example shows how to initialize and use the MPY32 API to calculate a 16 bit by 16 bit unsigned multiplication operation WDT hold WDT A BASE Stop WDT Set a 16 bit Operand into the specific Operand 1 register to specify unsigned multiplication MPY32_setOperandOnel6Bit MPY32_BASE MPY32_MULTIPLY_UNSIGNED 0x1234 Set Operand 2 to begin the multiplication operation MPY32_setOperandTwol6Bit MPY32_BASE 0x5678 __bis_SR_register LPM4_bits Enter LPM4 __no_operation BREAKPOINT HERE to verify the correct result in the registers 58 2013 05 2009 07 07_0500 TI Information Selective Disclosure Power Management Module PMM 19 Power Management Module PMM ils Te Ne eee ere eT eter Tere te Senay erent koda Aby v A ree Teer eT eta A ETTET TT 59 AP MONON ne 59 PMMA DE see 59 19 1 Introduction The PMM manages all functions related to the power supply and its supervision for the device Its primary functions are first to generate a supply voltage for the core logic and second provide several mechanisms for the supervision of the voltage applied to the device DVCC The PMM uses an integrated low dropout voltage regulator LD
75. us Receiver Transmitter EUSCI_A_UART EUSCI Universal Asynchronous Receiver Transmitter EUSCI_A_UART III A a a re ae 39 ARMENIOS IS AAA NAAA A he 39 Programming Example ee 40 Introduction The MSP430Ware library for UART mode features include m Odd even or non parity m Independent transmit and receive shift registers m Separate transmit and receive buffer registers LSB first or MSB first data transmit and receive m Built in idle line and address bit communication protocols for multiprocessor systems Receiver start edge detection for auto wake up from LPMx modes Status flags for error detection and suppression m Status flags for address detection m Independent interrupt capability for receive and transmit In UART mode the USCI transmits and receives characters at a bit rate asynchronous to another device Timing for each character is based on the selected baud rate of the USCI The transmit and receive functions use the same baud rate frequency This driver is contained in eusci_a_uart c with eusci a uart h containing the API defini tions for use by applications API Functions The EUSI_A_UART API provides the set of functions required to implement an interrupt driven EUSI_A_UART driver The EUSI_A_UART initialization with the various modes and features is done by the EUSCI_A_UART_init At the end of this fucntion EUSI_A_UART is initial ized and stays disabled EUSCI_A_UART_enable enables the EUSI A UART and the mod
76. ve Disclosure How to include driverlib into your existing project 4 How to include driverlib into your existing project STEP 1 Create a subfolder MyProject gt driverlib Import the family folder from the installed SMSP430ware driverlibT by choosing Import gt general gt File system as shown in the screenshot below C 3 0 r Select Import resources from the local file system into an existing project Select an import source type filter 4 gt General E Archive File Existing Projects into Workspace I File System Preferences cic 4 gt Code Composer Studio EN Build Variables Existing CCS Eclipse Projects ES Legacy CCSv3 3 Projects gt Git gt Install gt Run Debug gt Team Make sure you check the SCreate top level folder checkbox This ensures that a top level folder with the family name is created withing driverlib sub folder A local copy of the driverlib source and header files are created within the project and are included in the project when the filesystem is imported this way Any change made to the driverlib source or header files reflects only in the local copy and not in the original installed version of the MSP430ware driverlib source header files 2013 05 2009 07 070500 17 TI Information Selective Disclosure How to include driverlib into your existing project File system Import resources From the local file system gt Y MSP430FR5xx_6xx Le ad
77. vice and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifi cally designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and
78. xample lt 3 lt s ER eh OBR E V C a AS 38 11 EUSCI Universal Asynchronous Receiver Transmitter EUSCI A UART lt lt lt lt ee 39 MLS LAIGAARD sce AAA ARA ede ce A 39 112 API Funslians lt lt Ree RE BE AAO ee eR ee R N 39 11 9 Programming EMMONS 5 a eier nabs Aba Gas ba jo eee faved Bowe Ue ae Rh en 40 12 EUSCI Synchronous Peripheral Interface EUSCI A SPI lt lt lt nn 4 Tel ISA o a era Re re nee A Rd u ES 41 122 FUNCUONS uz eee ae Pe eee ok lk ne re a ee 41 123 Programming Eine a 5 a ie ne RL ia aa ake lt a ne ne bs es Hepa ae de Rc a ade 42 13 EUSCI Synchronous Peripheral Interface EUSCI_B_SPl 22222200 nn nn 43 V351 PRAG CANON oo ar a ae ee e o dc Wo Be ne er Ae ea we ee 43 132 FUNCIONS lt 5x a a AR RA eR A ee A 43 13 PORTS MIO EMIS s asa ac E ig nee in j en na aaa an nd ca aaa NO Sm ewe Jem daer car see ara re 44 14 EUSCI Inter Integrated Circuit EUSCI B I2C o 45 TA MOGUCOM ee a Pew en Baek as 45 142 API Fungti ns co cis Ae a Ee eee Re Dee ae ae eee ae ee ee Oe A 47 143 Programming EN gt iais 0000 ne em ck ca ote ea dda Skonto ncn na Ss ees E col Pe a a eae gm ee ee en ehe vd 48 15 FRAM Controler cc 0 5 020650245 5646228 WER SE LR RR ee keine BO E 49 19 1 INWOAHCHEN cs eas s sapa ee a ee ee Re a ee Re ee 49 15 2 BPIUFUNCIONS z asaos RR a BROD Re AA ew eR E V S A er s 49 192 Programming BISMRlE sa rca se e a ea a a a em eae A Seca he es ae
79. yte of the PA port using byte instructions leaves the lower byte unchanged When writing to a port that contains less than the maximum number of bits possible the unused bits are a don t care Ports PB PC PD PE and PF behave similarly Reading of the PA port using word operations causes all 16 bits to be transferred to the destination Reading the lower or upper byte of the PA port P1 or P2 and storing to memory using byte operations causes only the lower or upper byte to be transferred to the destination respectively Reading of the PA port and storing to a general purpose register using byte operations causes the byte transferred to be written to the least significant byte of the register The upper significant byte of the destination register is cleared automatically Ports PB PC PD PE and PF behave similarly When reading from ports that contain less than the maximum bits possible unused bits are read as zeros similarly for port PJ 2013 05 2009 07 070500 51 TI Information Selective Disclosure GPIO 16 2 16 3 52 The GPIO pin may be configured as an lO pin with GPIO_setAsOutputPin GPIO_setAsInputPin GPIO_setAsInputPinWithPullDownresistor or GPIO_setAsInputPinWithPullUpresistor The GPIO pin may instead be con figured to operate in the Peripheral Module assigned function by config uring the GPIO using GPIO_setAsPeripheralModuleFunctionOutputPin or GPIO setAsPeripheralModuleFunctionlnputPin Thi
80. zation from a fixed priority to dynamic round robin priority Another setting that can be changed is when transfers occur the CPU may be in a read modify write operation which can be disasterous to time sensitive material so this can be disabled And Non Maskable Interrupts can indeed be maskable to the DMA module if not enabled The DMA module can generate one interrupt per channel The interrupt is only asserted when the specified amount of transfers has been completed With single transfer this occurs when that many single transfers have occured while with block or burst block transfers once the block is completely transfered the interrupt is asserted 10 2 API Functions The DMA API is broken into three groups of functions those that deal with initialization and trans fers those that handle interrupts and those that affect all DMA channels The DMA initialization and transfer functions are DMA init DMA setSrcAddress DMA setDstAddress DMA enable Transfers DMA disable Transfers DMA startTransfer DMA _setTransferSize The DMA interrupts are handled by DMA enablelnterrupt DMA disablelnterrupt DMA getlnterruptStatus DMA clearlnterrupt DMA NMIAbortStatus DMA clearNMIAbort Features of the DMA that affect all channels are handled by DMA disable TransferDuringReadModifyWrite DMA enableTransferDuringReadModifyWrite DMA enableRoundRobinPriority DMA disable RoundRobinPriority DMA enableNMIAbort DMA disableNMIlAbort 2013 05 2009 07

MSP430 Peripheral Driver Library for FR5xx and FR6xx Devices

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