Si5380 EVB User's Guide
Contents
1. Power only 5V USB Power Supply Power only 5V_Aux g O MM OaJaNM NOKOO 9 ooo ooo ooo o Ua ao af AAAA AAAA 12C A OA AAAAOAAAAOAA gt gt SSS 55 55 gt 5 gt gt oO mM OAN MTN OR OOD aa DDNS ie We beh le O ooo0oo0oo0oo0oo0o 0oo0oo0 i AA AA AAAAAAAA QO Oo Q2qg0qeqgqg aang a a SSS SeS S425 b gt CLKOUT_OA _ gt Output 5 diekin lt gt n T gt I2C SPI Bus CLKOUT_OAB gt Termination utput Cloc C8051F380 gt CLKOUT_0 gt Output Control dence Output Clock 0 MCU m Status CLKOUT_OB gt _ Termination CLKOUT_1 gt Output Gurunciacel sale utput Cloc Peripherals lt intr CLKOUT_1B _ Termination lt j Alarm_Status CLKOUT_2 gt Output a doda CLKOUT_2B gt Termination utput iog a end output Output Clock 3 CLKOUT_3B gt Termination XA i CLKOUT_4 gt Output in XB 315380 CLKOUT_4B gt _ Termination one Input Clock 0 opie ia e eddie Output Clock 5 Termination P CLKIN_ 0B CLKOUT_5B gt Termination utput Cloc Input Clock 1 thal il Seow ek Output Clock 6 Termination CLKIN_1B CLKOUT_6B a utput Cloc Input Clock 2 ee ene oe reel hak Output Clock 7 Termination CLKIN 2B CLKOUT_7B gt Termination i eaa Input Clock 3 loput e2. www silabs com CBPro Timing Portfolio SW HW Support and Community www silabs com timing www silabs com CBPro www silabs com quality community silabs com Disclaimer Silicon Laboratories intends to provide customers with the latest accurate and in depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products Characterization data available modules and peripherals memory sizes and memory addresses refer to each specific device and Typical parameters provided can and do vary in different applications Application examples described herein are for illustrative purposes only Silicon Laboratories reserves the right to make changes without further notice and limitation to product information specifications and descriptions herein and does not give warranties as to the accuracy or completeness of the included information Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories A Life Support System is any product or system intended to support or sustain life and or health which if it fails can be reasonably expected to result in significant personal injury
3. Figure 6 8 CBPro Write Design Dialog Select Yes to write the default plan to the Si5380 device mounted on your EVB This ensures the device on the EVB is configured with the latest parameters from Silicon Labs Si5380 Design Write Writing Si5380 Design to EVB Address 0x0263 Figure 6 9 CBPro Write Progress Window After CBPro writes the default plan to the EVB click on Open EVB GUI as shown in the figure below _ Si5380 EVB Default Configuration ClockBuilder Pro Po F C OC kB u d er P rO vis M standard frequency planner no setting overrides Design Dashboard Configuring Si5380 in LTE Mode Default plan for Si5380 EVB has been loaded You can make edits to the EVB s configuration using the interactive Wizard XR Edit Configuration with Wizard a Evaluation Board Detected Design ID amp Notes Host Interface XA XB ZDB i5380 EVB S N 00 00 16 B1 91 1D ar Input Clocks Input Clock Select Output Clocks Write Design to EVB Open EVB GUI 3 l DSPLL LOS OOF LOL INTR a Figure 6 10 CBPro Open EVB GUI Button The EVB GUI window will appear on the desktop Note all power supplies on the Regulators tab will be set to the values defined in the device s default CBPro project as shown in the figure below i5380 EVB S N 00 00 16 B1 91 1D ClockBuilder File Help Info DUTSPI I2C DUT Register Editor eguet Jan Voltages
4. GPIO Status Registers Voltage Current Power VDD 180v M 1785v 163 mA 291 mW VDDA H zv 128mA 424 mW vopoo 33v B EA 3308 v 46mA 152 mW vooo isov B 0 021 V 0 mA 0 mw voDo2 1s0v M ov 0 mA 0 mw voDo3 330v M 3 303 v 25 mA 83 mW vopo4 33v B EA 2v 26 mA 86 mW vopos 1sv BO EA oov 1 mA 0 mw vopos 33v B EA 24v 22mA 72mW vppo7 3 30v 3 297 V 22 mA 73 mW vpDos 1 80v M 0 022 V 0 mA 0 mw vopos 33v B RH soov 58mA 177mW u Total 489 mA 1 358 W C Read All All Output Select Voltage Compare Design Estimates to Measurements Figure 6 11 EVB GUI Regulators silabs com Smart Connected Energy friendly Si5380 Evaluation Board User s Guide Using the Si5380 EVB and Installing ClockBuilderPro CBPro Desktop Software 6 6 1 Verify Free Run Mode Operation Assuming no external clocks have yet been connected to the INPUT CLOCK differential SMA connectors labeled INx INxB and loca ted around the perimeter of the EVB the DUT should now be operating in free run mode and locked to the EVB crystal You can run a quick check to determine if the device is powered up generating output clocks and consuming power by clicking on the Read All button highlighted above and then reviewing the voltage current and power readings for each VDDx supply Note Turning Vpp or Vppa Off will power down and reset the DUT Once both of these supplies are turned On again you must reload the desired fr
5. standard frequency planner no setting overrides 5 l N A i 5 Design Dashboard Configuring Si5380 in LTE Mode Default plan for Si5380 EVB has been loaded You can make edits to the EVB s configuration using the interactive Wizard XR Edit Configuration with Wizard ij Evaluation Board Detected Design ID amp Notes Host Interface XA XB ZDB Si5380 EVB S N 00 00 16 B1 91 1D Input Clocks Input Clock Select Output Clocks Write Design to EVB Open EVB GUI DSPLL LOS OOF LOL INTR Save Design to Project File Export Your configuration is stored to a project file which can You can export your configuration to a format suitable be opened in ClockBuilder Pro at a later time for in system programming Documentation Please contact your Silicon Labs representive for documentation regarding this pre release device Create Custom Part Number Ask for Help With just a few clicks you can order factory pre Have a question about your design Click here to get programmed devices based on your configuration assistance Design ox pd 1 280 w 7 95 C Figure 6 13 CBPro Design Report Button and Link Your configuration s design report will appear in a new window as shown below Compare the observed output clocks to the frequen cies and formats noted in your default project s Design Report silabs com Smart Connected Energy friendly Si5380 Evaluation Board User s Guide Using the Si53
6. CLKOUT_8 Output Output Clock 8 Termination CLKIN_ 3B CLKOUT_8B gt Termination EAS NERE CLKOUT_9 gt Output 0 Clock 9 CLKOUT_ 98 gt gt Termination utput Lge CLKOUT_9A gt Output 0 Clock 9A CLKOUT_ 9AB gt Termination utput cioc Figure 1 1 Functional Block Diagram of Si5380 EVB silabs com Smart Connected Energy friendly Si5380 Evaluation Board User s Guide Quick Start and Jumper Defaults 2 Quick Start and Jumper Defaults Perform the following steps to quick start the ClockBuilderPro software 1 Install ClockBuilderPro desktop software http www silabs com CBPro 2 Connect a USB cable from the Si5380 EVB to the PC where the software was installed 3 Leave the jumpers as installed from the factory and launch the ClockBuilderPro software 4 You can use ClockBuilderPro to create download and verify a frequency plan on the Si5380 EVB 5 For the Si5380 data sheet go to http Awww silabs com timing and search for Si5380 datasheet The following table lists the Si5380 EVB jumper defaults Table 2 1 Si5380 EVB Jumper Defaults Location I Installed Location Installed O Open O Open JP1 2 pin O JP23 2 pin O JP2 2 pin O JP24 3 pin all open JP3 2 pin O JP25 2 pin O JP4 2 pin JP26 3 pin all open JP5 2 pin O JP27 2 pin O JP6 2 pin O JP28 3 pin all open JP7 2 pin JP29 2 pin O JP8 2 pin O JP30 3 pin
7. DUT_SCLKk as the 12C SCLK Please note the external 12C controller will need to supply its own I2C signal pull up resistors 2 1 DUT_A0_CSB lt _ T 3 MCU MOS DUT_SDA_SDI_ gt 5 MCU MISO DUT_A1_SDO lt _ gt p 7___MCU_SCLK DUT_SCLK lt _____ 10 9 HEADER 5x2 Figure 8 1 Serial Communications Header J36 silabs com Smart Connected Energy friendly Rev 1 1 18 Si5380 Evaluation Board User s Guide Si5380 EVB Schematic and Bill of Materials BOM 9 15380 EVB Schematic and Bill of Materials BOM The Si5380 EVB Schematic and Bill of Materials BOM can be found online at http www silabs com si538x 4x evb Note Please be aware the Si5380 EVB schematic is in OrCad Capture hierarchical format and not in a typical flat schematic format silabs com Smart Connected Energy friendly Rev 1 1 19 Konsi CON LABS YY ClockBuilder Pro Wizard We Make Timing Simple k With a Desiar I Create New Design Open Design Project File tom Part Number tookus Open Sample Design Applications Documentation Quick Links No EVB Present No Si5 38x 4x evaluation board has been detected timizing SiS34x Jit forma Ns r n S and IEEE 1588 App N Export Configuration ClockBuilder Pro Documentatii RP enco t K ClockBuilder Pro One click access to Timing tools documentation software source code libraries amp more Available for Windows and iOS CBGo only
8. Export Settings File Register File PAbout Register Export rrr mmtm mm tmnm i This export will contain the registers that need to be written to the Si538x 4x device to achieve your design configuration Each line in the file is an address data pair in hexadecimal format The address is two bytes wide and the data is a single byte A comma separates the address and data fields Please refer to the Si538x 4x Family Reference Manual for information on register addressing and how to write the data contained within this export Note the file includes a write to soft reset the device and load the configuration Options NI Include summary header If checked an informational header will be included at the top of the file Each line in the header will be prefixed by the character The header will contain some basic information about the design tool and a timestamp M Include pre and post write control register writes Certain control registers must be written before and after writing the volatile configuration registers This ensures the device is stable during configuration download and resumes normal operation after the download is complete You can turn inclusion of this sequence off if your host system is managing this process already C Lam targeting pre production samples e Preview Export Save to File Figure 6 22 CBPro Export Configuration Window silabs com Smart Connected Energy friendly Si5380 Evaluatio
9. Knowledge Base Version 1 3 3 Built on 11 5 2014 Figure 6 4 ClockBuilderPro Wizard Use the CBPro Wizard to do the following e Create a new design e Review or edit an existing design e Export Create in system programming files Application 2 i5380 EVB S N 00 00 16 File Help Info DUTSPI I2C DUT Register Editor Regulators All Voltages GPIO Status Registers Voltage Current Power voo 127 B EA vov 149mA 267 mW VDDA Oy asv 123mA 408 mW vopoo 33v B E 20v 36mA 118 mW vooo isov BO EA ooi7v 0 mA 0 mw vooo isov BO EA oov 0 mA 0 mw vooo 3300 B 2v 15mA 49mW vopo4 33v B EA ov 16 mA 53 mW vopos isov MO EA oov 0 mA 0 mw vopos 33v B EA ov 15 mA 49 mW vopo7 33v B EA 3z02v 16 mA 53 mw vopos 12v BO EA oov 0 mA 0 mw vooos 3300 B EA ezv 37mMA 121mW Total 407 MA 1118W All Output select vottage E Supplies Compare Design Estimates to Measurements Figure 6 5 EVB GUI Use the EVB GUI to do the following e Download configuration to EVB s DUT Si5380 e Control the EVB s regulators e Monitor voltage current power on the EVB silabs com Smart Connected Energy friendly Si5380 Evaluation Board User s Guide Using the Si5380 EVB and Installing ClockBuilderPro CBPro Desktop Software 6 5 Common ClockBuilderPro Work Flow Scenarios There are three common workflow scenarios when using CBPro and the Si5380 EVB These workflow scenarios ar
10. PM 3 28 2014 8 50 AM 10 16 2014 11 18 9 4 2014 5 24 PM 11 19 2014 11 51 10 16 2014 4 49 PM 11 1 2013 11 54 AM 11 1 2013 11 52 AM 5 19 2014 10 05 AM 9 2 2014 12 27 PM 12 13 2013 3 32 PM 11 5 2014 4 15 PM Type File folder File folder File folder File folder File folder File folder File folder File folder File folder File folder File folder File folder Shortcut 2 KB Shortcut 3 KB Silicon Labs Timin 8 KB v Silicon Labs Timing Project s v open fe cme Figure 6 19 CBPro Windows File Browser Select Yes when the WRITE DESIGN to EVB popup appears ClockBuilder Pro v1 5 Write Design to EVB The EVB may be out of sync with your design Would you like to write your design to the EVB Figure 6 20 CBPro Write Design Dialog silabs com Smart Connected Energy friendly Si5380 Evaluation Board User s Guide Using the Si5380 EVB and Installing ClockBuilderPro CBPro Desktop Software The progress bar will be launched Once the new design project file has been written to the device verify the presence and frequencies of your output clocks and other operating configurations using external instrumentation 6 9 Exporting the Register Map File for Device Programming by a Host Processor You can also export your configuration to a file format suitable for in system programming by selecting Export as shown below Si5380 EVB Default Configuration ClockBuil
11. Pd 1 280 W Tj 95 C Figure 6 15 CBPro Edit Settings Links and Pulldown You will now be taken to the Wizard s step by step menu pages to allow you to change any of the default plan s operating configura tions i5380 EVB Default Configuration ClockBuilder Pro gt gu a ClockBuilder Pro v15 My standard frequency planner no setting overrides 5 l N A i 5 Step 1 of 12 Design ID amp Notes Configuring Si5380 in LTE Mode Design ID The device has 8 registers DESIGN_IDO through DESIGN_ID7 that can be used to store a design configuration revision identifier Design ID 5380EVB1 optional max 8 characters The string you enter here is stored as ASCII bytes in registers DESIGN_IDO through DESIGN_ID7 Padding Mode NULL Padded If you do not enter the full 8 characters the reamining bytes of DESIGN_IDx will be padded with 0x00 bytes aka NULL character Space Padded If you do not enter the full 8 characters the reamining bytes of DESIGN_IDx will be padded with 0x20 bytes space character Design Notes Enter anything you want here The text is stored in your project file and included in design reports and custom part number datasheet addendums While the text is word wrapped in reports you can use newlines to start a new paragraph _ soun Figure 6 16 CBPro Design ID and Notes Edit Page silabs com Smart Connected Energy friendly Si5380 Evaluation Board Use
12. or death Silicon Laboratories products are generally not intended for military applications Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including but not limited to nuclear biological or chemical weapons or missiles capable of delivering such weapons Trademark Information Silicon Laboratories Inc Silicon Laboratories Silicon Labs SiLabs and the Silicon Labs logo CMEMS EFM EFM32 EFR Energy Micro Energy Micro logo and combinations thereof the world s most energy friendly microcontrollers Ember EZLink EZMac EZRadio EZRadioPRO DSPLL SOmodem Precision32 ProSLIC SiPHY USBXpress and others are trademarks or registered trademarks of Silicon Laboratories Inc ARM CORTEX Cortex M3 and THUMB are trademarks or registered trademarks of ARM Holdings Keil is a registered trademark of ARM Limited All other products or brand names mentioned herein are trademarks of their respective holders Silicon Laboratories Inc 400 West Cesar Chavez Austin TX 78701 USA SILICON LABS
13. 80 EVB and Installing ClockBuilderPro CBPro Desktop Software Frequency Plan Result H z Si5380 f Design ID 5380EVB1 f Created By ClockBuilder Pro v1 5 2014 12 03 Timestamp 2014 12 08 11 56 05 GMT 06 00 Design Rule Check Errors f No errors f Warnings f No warnings Design f Host Interface I O Power Supply VDD Core SPI Mode 4 Wire f I2C Address Range 104d to 107d 0x68 to 0x6B selected via A0 A1 pins XA XB 54 MHz XTAL Crystal 30 72 MHz 30 18 25 MHz Differential IN1 61 44 MHz 61 11 25 MHz j Differential IN2 122 88 MHz 122 22 25 MHz Differential 245 76 MHz 245 19 25 MHz Differential f 245 76 MHz 245 19 25 Enabled LVPECL 3 3 V 245 76 MHz 245 19 25 Enabled LVPECL 3 3 V Unused Unused 491 52 MHz 491 13 25 Enabled LVPECL 3 3 V 491 52 MHz 491 13 25 Copy to Clipboard Ask for Help Figure 6 14 CBPro Design Report 6 6 2 Verify Locked Mode Operation Now assuming that you connect the input clocks to the EVB as shown in the Design Report above the DUT on your EVB will be run ning in locked mode silabs com Smart Connected Energy friendly Si5380 Evaluation Board User s Guide Using the Si5380 EVB and Installing ClockBuilderPro CBPro Desktop Software 6 7 Workflow Scenario 2 Modifying the Default Silicon Labs Created Device Configuration To modify the configuration using t
14. B to Your Host PC Once ClockBuilderPro software in installed connect to the EVB with a USB cable as shown below Output Clocks Output Clocks Output Clocks Figure 6 1 EVB Connection Diagram silabs com Smart Connected Energy friendly Si5380 Evaluation Board User s Guide Using the Si5380 EVB and Installing ClockBuilderPro CBPro Desktop Software 6 3 Additional Power Supplies The Si5380 EVB comes preconfigured with jumpers installed on JP15 and JP16 pins 1 2 in both cases in order to select USB These jumpers together with the components installed configure the evaluation board to obtain 5 V power to all EVB power solely through the J37 USB connector This setup is the default EVB configuration and is sufficient to configure the device and run multiple clock outputs simultaneously In some cases when enabling all outputs or at high output frequencies the EVB requires more power than a single USB connection can provide This may result in intermittent device behavior or unexplained increases in jitter pnhase noise This condition may be checked using the EVB GUI which is described further below Selecting the All Voltages tab of the GUI and clicking on the Read All button produces a display similar to this one i5380 EVB S N 00 00 16 B1 91 1D ClockBuilder File Help Info DUTSPI I2C DUT Register Editor Regulators All Voltages GPIO Status Registers Voltage Regulator Pins Volt
15. ON LABS Work With a Design Create New Design Open Design Project File gt Open Sample Design a Evaluation Board Detected Quick Links Jitter Attenuator Clock Products Knowledge Base Custom Part Number Lookup ClockBuilder Go iOS App Applications Documentation 10 40 100G Line Card White Paper Clock Generators for Cloud Data Centers White Paper Optimizing Si534x Jitter Performance App Note Tools SyncE and IEEE 1588 App Note gt Export Configuration ClockBuilder Pro Documentation CBPro Overview CBPro Knowledge Base Version 1 5 Built on 12 3 2014 Figure 6 18 CBPro Open Design Project Link Using the windows file browser popup locate your CBPro design file slabtimeproj or sitproj file a L rD searc EVDS New folder Organize v A d Competition D M Customers m Debug D M EVBs gt J HighLevelPriorities m Knowledge Base gt Marketing gt D OPNs ry Planning gt B ProductDocuments gt B ReferenceDocuments Jl SAP_MDM gt m Software gt Sustaining gt M Tester_Corr gt B Users gt M Xfer File name B 5338_Customer_EVB_Mods B Components m Customer_EVBs J EVB_Default_CBPro_Plans J EVB_REFERENCE_SCHEMATICS d EVB_REFERENCE_SW_AND_GUIDES p EVB_User_Guides M EVBsHardware d EVBsSoftware p Harnesses d Planning D XTALs_TCXOs Date modified 4 22 2013 11 27 AM 3 3 2014 6 43 PM 11 24 2014 1 22 PM 11 19 2014 1 47
16. SILICON LABS 15380 Evaluation Board User s Guide The Si5380 EVB is used for evaluating the Ultra Low Jitter Any Frequency 12 output JESD204B Clock Generator The Si5380 employs 4th generation DSPLL technology to enable clock gen eration for LTE JESD204B applications which require the high est level of jitter performance The Si5380 EVB has four inde pendent input clocks and a total of 12 outputs The Si5380 EVB can be easily controlled and configured using Silicon Labs Clock Builder Pro CBPro software tool H Bi F i V i h 4 Ty ff SP Bose SL Se we 3 he gus 2i 5i 33 Be a 31 Oo P25 7 3v 3 3V T 3 3V AN 3 3v 3 3V et OPEN OPEN 2sv Y olasy 18V olasy 18V olasy 7 Ovppos O vppos yppos GND GND 5an rz s ENB 3 3V 2 5V TPs ig ts r e S a da Ia i z 4 5 or B E 2 435 JiS gt iy f Si5380 Evaluation Board User s Guide Si5380 Functional Block Diagram 1 i5380 Functional Block Diagram Below is a functional block diagram of the Si5380 EVB This EVB can be connected to a PC via the main USB connector for program ming control and monitoring See 2 Quick Start and Jumper Defaults or 6 1 Installing ClockBuilderPro CBPro Desktop Software for more information Note All Si5380 schematics BOMs User s Guides and software can be found online at the following link http www silabs com Si538x 4x evb
17. TxB Each of the twenty four output drivers 12 differential pairs is ac coupled to its respective SMA connector The output clock termination circuit is shown in the figure below The output signal will have no dc bias If dc coupling is required the ac coupling capacitors can be replaced with a resistor of appropriate value The Si5380 EVB provides pads for optional output termination resistors and or low fre quency capacitors Note that components with schematic NI designation are not normally populated on the Si5380 EVB and provide locations on the PCB for optional dc ac terminations by the end user C21 R88 OUT_CKT Sma OUTO R89 0 1uF C22 10K GND NI a ap C23 R90 in OUT_CKTB sma OUTOB R91 hike 0 1uF iii NI 0 01uF NI Figure 5 2 Output Clock Termination Circuit silabs com Smart Connected Energy friendly Si5380 Evaluation Board User s Guide Using the Si5380 EVB and Installing ClockBuilderPro CBPro Desktop Software 6 Using the Si5380 EVB and Installing ClockBuilderPro CBPro Desktop Software 6 1 Installing ClockBuilderPro CBPro Desktop Software To install the CBPro software on any Windows 7 or above PC Go to http Awww silabs com si538x 4x evb and download the ClockBuilderPro software Installation instructions release notes and a user s guide for ClockBuilderPro can be found at the download link shown above Please follow the instructions as indicated 6 2 Connecting the EV
18. age Regulator VDD_PIN 1945 V Read VDD_REG 1 785 V Read VDDAPIN 3 445 V Read VDDA REG 3 317 V Read VDDOO_PIN 4 703 V Read VDDO0_REG 3 309 V Read VDDO1PIN 21 000 mV Read VDDO1_REG 8 000 mV Read VDDO2 PIN 0 000 V Read VDDO2_REG 0 000 V Read VDDO3_PIN 4 057 V Read VDDO3_REG 3 305 V Read VDDO4 PIN 4 089 V Read VDDO4 REG 3 322 V Read VDDOS_PIN 30 000 mV Read VDDO5_REG 20 000 mv Read VDDO6_PIN 3 951 V Read VDDO6_REG 3 275 V Read VDDO7 PIN 3 963 V Read VDDO7_REG 3 299 V Read VDDO8_PIN 29 000 mV Read VDDO8_REG 16 000 mV Read VDDO9_PIN 4 819 V Read VDDO9_ REG 3 071 V Read eee Misc Rails eRe eel RAIL SV 4 849 V Read RAIL 3P3V 3 343 V Read Figure 6 2 EVB GUI Power Supply Check Verify that the RAIL_5V measurement shows the EVB voltage gt 4 7 V An EVB voltage lower than this level may cause the issues described above In this case J33 can be used to provide power to the output drivers separately from the main SI5380 device supplies To make this change move jumper JP15 to connect pins 2 3 EXT Connect J33 to an external 5 V 0 5A or higher power source Make sure that the polarity of the 5 V and GND connections are correct Verify that the RAIL_5V voltage is 4 7 V or higher The EVB should be pow ered by the USB connector when turning this auxiliary 5 V supply on or off See the figure below for the correct installation of the jumper shunts at JP15 and JP16 for default or standard operat
19. all open JP9 2 pin O JP31 2 pin O JP10 2 pin O JP32 3 pin all open JP13 2 pin O JP33 2 pin O JP14 2 pin JP34 3 pin all open JP15 3 pin 1 to 2 JP35 2 pin O JP16 3 pin 1 to 2 JP36 3 pin all open JP17 2 pin O JP39 2 pin O JP18 3 pin all open JP40 2 pin O JP19 2 pin O JP41 2 pin O JP20 3 pin all open JP21 2 pin O JP22 3 pin all open J36 5x2 Hdr All 5 installed Note Refer to the Si5380 EVB schematics for the functionality associated with each jumper silabs com Smart Connected Energy friendly Si5380 Evaluation Board User s Guide 3 Status LEDs Table 3 1 Si5380 EVB Status LEDs Location Silkscreen Status Function Indication D11 INTRB Blue DUT Interrupt Active D12 LOLB Blue DUT Loss of Lock Indicator D21 READY Green MCU Ready D22 3P3V Blue DUT 3 3 V is present D24 BUSY Green MCU Busy D25 INTR Red MCU Interrupt active D26 VDD DUT Blue DUT VDD voltage present D27 5VUSBMAIN Blue Main USB 5 V present D27 D22 and D26 are illuminated when USB 5 V Si5380 3 3 V and Si5380 Output 5 V supply voltages respectively are present D25 D21 and D24 are status LEDs showing on board MCU activity D11 and D12 are status indicators from the DUT Figure 3 1 Status LEDs Si5380 Evaluation Board User s Guide External Reference Input XA XB 4 External Reference Input XA XB An external reference XTAL is used in combination with the internal oscillator to produce an ul
20. der Pro _ an a SILICON LABS Configuring Si5380 in LTE Mode C OC k B Ul d er P DETER standard frequency planner no setting overrides Design Dashboard Default plan for Si5380 EVB has been loaded You can make edits to the EVB s configuration using the interactive Wizard Edit Configuration with Wizard a Evaluation Board Detected Host Interface XA XB ZDB Save Design to Project File Your configuration is stored to a project file which can be opened in ClockBuilder Pro at a later time Design Report amp Datasheet Addendum You can view a design report text or create a draft datasheet addendum PDF for your design Create Custom Part Number With just a few clicks you can order factory pre programmed devices based on your configuration Si5380 EVB S N 00 00 16 B1 91 1D Write Design to EVB Open EVB GUI Keson ot your configuration to a format suitable for in system programming Documentation Please contact your Silicon Labs representive for documentation regarding this pre release device Ask for Help Have a question about your design Click here to get assistance Frequency Plan Valid Design OK Pd 1 280 W Tj 95 C Figure 6 21 CBPro Export Design Programming File You can now write your device s complete configuration to file formats suitable for in system programming E ES Ie rns Multi Project Register Settings T 15380
21. e e Workflow Scenario 1 Testing a Silicon Labs created Default Configuration e Workflow Scenario 2 Modifying the Default Silicon Labs created Device Configuration e Workflow Scenario 3 Testing a User created Device Configuration Each is described in more detail in the following sections 6 6 Workflow Scenario 1 Testing a Silicon Labs Created Default Configuration Verify that the PC and EVB are connected then launch ClockBuilder Pro by clicking on this icon on your PC s desktop fjePro ClockBuilder Pro Figure 6 6 ClockBuilder Pro Icon CBPro automatically detects the EVB and device type When the EVB has been detected click on the Open Default Plan button ClockBuilder Pro Wizard Silicon Labs ClockBuilder Pro SILICON LABS We Make Timing Simp Work With a Design Create New Design E m Open Design Project File 5 ex Open Sample Design a Evaluation Board_Detected Si5380 EVB Open Default Plan Open EVB GUI Tools Export Configuration i Figure 6 7 CBPro Open Default Plan Button Once you open the default plan a popup will appear silabs com Smart Connected Energy friendly Si5380 Evaluation Board User s Guide Using the Si5380 EVB and Installing ClockBuilderPro CBPro Desktop Software ClockBuilder Pro v1 5 Write Design to EVB The EVB may be out of sync with your design Would you like to write your design to the EVB
22. equency plan back into the device memory by selecting the Write Design to EVB button on the CBPro home screen m i5380 EVB Default Configuration ClockBuilder Pro az ClockBuilder Pro v1 5 Mo standard frequency planner no setting overrides 5 l N A i 5 Design Dashboard Configuring Si5380 in LTE Mode Default plan for Si5380 EVB has been loaded You can make edits to the EVB s configuration using the interactive Wizard Edit Configuration with Wizard a Evaluation Board Detected Design ID amp Notes Host Interface XA XB ZDB e i5380 EVB S N 00 00 16 B1 91 1D Input Clocks Input Clock Select Output Clocks DSPLL LOS OOF LOL INTR d Write Design to EVB gt Open EVB GUI Figure 6 12 CBPro Write Design Button Failure to do the step above will cause the device to read in the preprogrammed plan from its non volatile memory NVM However the plan loaded from the NVM may not be the latest plan recommended by Silicon Labs for evaluation At this point you should verify the presence and frequencies of the output clocks running in free run mode from the crystal using ex ternal instrumentation connected to the output clock SMA connectors labeled OUTx OUTs To verify plan inputs go to the appropriate configuration page or click on Frequency Plan Valid to see the design report a Si5380 EVB Default Configuration ClockBuilder Pro EE eS m ClockBuilder Pro v15 Me
23. he CBPro Wizard click on the appropriate category The category may also be selected from a drop down list by clicking on the Design Dashboard button above this section i Si5380 EVB Default Configuration ClockBuilder Pro NII m a n ClockBuilder Pro v15 Mo standard frequency planner no setting overrides 5 l N A i 5 Design Dashboard Configuring Si5380 in LTE Mode Default plan for Si5380 EVB has been loaded You can make edits to the EVB s configuration using the interactive Wizard a Evaluation Board Detected Si5380 EVB S N 00 00 16 B1 91 1D Input Clocks Input Clock Select Output Clocks Write Design to EVB Open EVB GUI DSPLL LOS OOF LOL INTR Save Design to Project File Export Your configuration is stored to a project file which can You can export your configuration to a format suitable W be opened in ClockBuilder Pro at a later time for in system programming I Design Report amp Datasheet Addendum Documentation You can view a design report text or create a Please contact your Silicon Labs representive for I draft datasheet addendum PDF for your design documentation regarding this pre release device I Create Custom Part Number Ask for Help With just a few clicks you can order factory pre Have a question about your design Click here to get programmed devices based on your configuration assistance Frequency Plan Valid Design OK
24. ion Figure 6 3 JP15 JP16 Standard Jumper Shunt Installation Errata Note Some early versions of the 64 pin Si534x EVBs may have the silkscreen text at JP15 JP16 reversed regarding EXT and USB i e USB EXT instead of EXT USB Regardless the correct installation of the jumper shunts for default or standard operation is on the right hand side as read and viewed in the above figure silabs com Smart Connected Energy friendly Si5380 Evaluation Board User s Guide Using the Si5380 EVB and Installing ClockBuilderPro CBPro Desktop Software 6 4 Overview of ClockBuilderPro Applications The ClockBuilderPro installer will install two main applications Application 1 fa ClockBuilder Pro Wizard Silicon Labs ae _ e sc Io ce SILICON LABS Work With a Design Create New Design amp Open Design Project File a Evaluation Board Detected ClockBuilder Pro Wizard We Make Timing Simple ex Open Sample Design Si5380 EVB Tools gt Export Configuration Open Default Plan Open EVB GUI Quick Links Jitter Attenuator Clock Products Knowledge Base Custom Part Number Lookup ClockBuilder Go iOS App Applications Documentation 10 40 100G Line Card White Paper Clock Generators for Cloud Data Centers White Paper Optimizing Si534x Jitter Performance App Note Sync and IEEE 1588 App Note ClockBuilder Pro Documentation CBPro Overview CBPro
25. n Board User s Guide Writing A New Frequency Plan or Device Configuration to Non volatile Memory OTP 7 Writing A New Frequency Plan or Device Configuration to Non volatile Memory OTP The Si5380 device loads the Non Volatile Memory OTP on either a powerup or a hard reset overwriting any previous volatile register changes This allows the device to begin functioning as desired on powerup hard reset without manual intervention To restart the de vice while preserving volatile changes and without loading the OTP use soft reset through the registers or EVB GUI Note Writing to the device non volatile memory OTP is NOT the same as writing a configuration into the Si5380 using ClockBuilder Pro on the Si5380 EVB Writing a configuration into the EVB from ClockBuilderPro is done using Si5380 RAM space and can be done virtually an unlimited number of times Writing to OTP is limited as described below Refer to the Si5380 Family Reference Manual and device datasheet for information on how to write a configuration to the EVB DUT s non volatile memory OTP The OTP can be programmed a maximum of two times only Care must be taken to ensure the configura tion desired is valid when choosing to write to OTP silabs com Smart Connected Energy friendly Rev 1 1 17 Si5380 Evaluation Board User s Guide Serial Device Communications Si5380 lt gt MCU 8 Serial Device Communications Si5380 lt gt MCU 8 1 On Board SPI Suppor
26. r s Guide Using the Si5380 EVB and Installing ClockBuilderPro CBPro Desktop Software As you edit the settings you may notice the Frequency Plan Valid link in the lower left corner updating You can click on this link to bring up the design report to confirm that the information is correct When you are finished editing each page you may click on the gt Next or lt Back buttons to move from page to page When you are done making all your desired changes you can click on Write to EVB to reconfigure your device The Design Write status window will appear each time you write to the EVB r Si5380 Design Write Writing Si5380 Design to EVB Address 0x0263 Figure 6 17 CBPro Design Write Progress Window When you have verified your design settings you may save the design project Click on the Finish button to return to the home page and then click on the Save Design to Project File link You can use the windows file browser to reach the correct location and enter a filename for this new project silabs com Smart Connected Energy friendly Rev 1 1 14 Si5380 Evaluation Board User s Guide Using the Si5380 EVB and Installing ClockBuilderPro CBPro Desktop Software 6 8 Workflow Scenario 3 Testing a User Created Device Configuration ClockBuilder Pro Wizard Silicon Labs s E gt ClockBuilder Pro Wizard We Make Timing Simple SILIC
27. t The MCU on board the Si5380 EVB communicates with the Si5380 device through a 4 wire SPI Serial Peripheral Interface link The MCU is the SPI master and the Si5380 device is the SPI slave The Si5380 device can also support a 2 wire 12C serial interface al though the Si5380 EVB does NOT support the 12C mode of operation SPI mode was chosen for the EVB because of the relatively higher speed transfers supported by SPI vs 12C 8 2 External 12C Support I2C can be supported if driven from an external 12C controller The serial interface signals between the MCU and Si5380 pass through shunts loaded on header J36 These jumper shunts must be installed in J36 for normal EVB operation using SPI with CBPro If testing of 12C operation via external controller is desired the shunts in J36 can be removed thereby isolating the on board MCU from the Si5380 device The shunt at J4 I2C_SEL must also be removed to select I2C as Si5380 interface type An external 12C controller con nected to the Si5380 side of J36 can then communicate to the Si5380 device For more information on I C signal protocol please refer to the Si5380 data sheet The figure below illustrates the J36 header schematic J36 even numbered pins 2 4 6 etc connect to the Si5380 device and the odd numbered pins 1 3 5 etc connect to the MCU Once the jumper shunts have been removed from J36 and J4 IC operation should use J36 pin 4 DUT _SDA_SDIO as the 12C SDA and J36 pin 8
28. tra low jitter reference clock for the DSPLL and for providing a stable reference for the free run and holdover modes The Si5380 EVB can also accommodate an external reference clock instead of a crystal To evaluate the device with a REFCLK C111 and C113 must be populated and the XTAL removed see figure below The REFCLK can then be applied to J39 and J40 Note The remaining components marked NI are not installed m i Figure 4 1 External Reference Input Circuit silabs com Smart Connected Energy friendly Si5380 Evaluation Board User s Guide Clock Input and Output Circuits 5 Clock Input and Output Circuits 5 1 Clock Input Circuits INx INxB and FB_IN FB_INB The Si5380 EVB has eight SMA connectors INO INOB IN2 IN2B and IN3 FB_IN IN3B FB_INB for receiving external clock signals All input clocks are terminated as shown in the figure below Note input clocks are ac coupled and 50 terminated This represents four differential input clock pairs Single ended clocks can be used by appropriately driving one side of the differential pair with a single ended clock For details on how to configure inputs as single ended please refer to the Si5380 data sheet Gi6 PCB19 TP PAD GND gt CLKIN PCB15 C38 49 9 i GND PCBI6 TP PAD T OAF R85 a9 F GND C19 CLKIN oB 2 gt CLKINB SMA 0 1uF C20 10uF Figure 5 1 Input Clock Termination Circuit 5 2 Clock Output Circuits OUTx OU
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