Evaluation Board User Guide UG-045
Contents
1. 192 Figure 17 Board Schematics 1 ADC Buffer Circuits Rev 0 Page 9 of 32 8 0 12980 3989 440 3801 3801 3801 ado 480 440 440 3989 1991 gt SUEY gt 646 5 412 gt 646 mie 2 2 azo 182 982 62 862 2610 an l ELAT s DOW WONT LICH lt 72 19 23 74 3avdsczu h lt 191 191 y oav zad 5867 191 1v1vasv ziidd gt DELLA BG zvivasv z8aH 6869 52222 tH VVv 91 lt 91 lt 20 tn 1v1vosq 112 zvivosa zudH lt ty lt EN 1 05 3 gt suzy 61 onon iydi gt 5 35 2 3 ivas uon _ 021 Buvds lt 191 uia gt 5 4888 4901 4601 48882. 3noro 690 yek 620 442 38082080 25901240 aan 25981040 25950290 8 T 1 090 eaa 5 Jnoro i Zao gt 66 15964240 SOM SBMA 289911240 y 2 WN d z ay 193 3 225 novo 19 soku 2900 4001 exer s d zm 11 Pree 25991140 182 sto T sno 569 penu nok bupous yenu ZEMA mi GND J 434A t gt zal 25951190 2 Isa 8981 25981040 a un naL 5 du EP mot mans mans nS 193 asz 185 WN Sia a 0010 19 51 3noro T vVv aoe n CI 4 063 n tg 800 9841 8981 2921 PR 20001 oer stor 499 55 8 v z n v an 2596 240 any 9246 9239 4 n WN 4 92 eri LS Vs 992 3802
3. 11 12 in T AAA Jurino vas 25954240 9 sow 71 VAV A VV A VV Jauno 1953 oro zcu 36022 1819 ver N M Sv ado 3 3315 2902 0 9912 vz PTZ very m 2 AAA AAA C ino t rsi z E k ien s 924 Figure 23 Board Schematics Page 7 DAC Buffer Circuits Rev 0 Page 15 of 32 s s aq 3204 ay 104 14 Kuy 8 0 y 104 sr VOS VZNid 826 19 0 4 15 104 S318 8891 04015 8997 8484 221 986610 apow 221 19315 0 y 0 2 921 9 610 103 uonijsod Z 0 8 Gdf IdS 896107 404 0 0 L L 1 r lt Ho Oe tg s v e zi 1 d si 195 81 8 6 1 of ick vas 81 921 oy 181 18751 29 9 135 181 1951 e M 1951 zo OFF 109181 A
4. END IF Logic Rev 0 Page 25 of 32 ORDERING INFORMATION BILL OF MATERIALS Table 1 Qty Designator Description Manufacturer Part Number 18 C85 C90 to C94 C101 to C103 Multilayer ceramic capacitor 16 V X7R Panasonic EC ECJ 0EX1C104K 46 12 16 32 12 12 10 C107 C108 C110 C115 C116 C121 C127 C132 C134 C2 C5 C8 to C10 C20 C21 C28 C29 C38 C42 C48 to C51 C58 to C60 C62 C64 C69 C73 C76 C79 C82 C99 C112 C118 C128 C135 C146 C147 C149 C151 C155 C156 C158 C162 C168 C174 C176 C177 C193 C194 C197 C203 C37 C65 C67 C83 C88 C124 C129 C157 C160 R28 R30 R51 R59 R166 R167 R169 R172 R185 R189 R212 R214 C68 C71 C87 C89 C130 C138 C159 C161 R24 R31 R44 R60 R77 R84 R93 R106 R136 R149 R159 R170 R180 R191 R207 R217 C84 R6 R7 R13 R14 R18 R20 R40 R43 R47 to R49 R54 R55 R63 R64 R74 R78 R80 R82 R102 R117 R158 R164 R173 R176 R177 R184 R186 R224 to R227 C6 C39 C40 C15 to C17 C81 C86 C95 C98 C170 C175 C178 C180 C183 C104 C106 C109 C111 C117 C123 C140 to C145 C4 C74 C61 C77 C113 C150 D1 D3 D4 C23 C33 C43 C55 C114 C166 C184 C188 C200 C36 C153 C154 R76 R81 R90 R101 R134 R141 R157 R168 R4 R91 R94 R98 R99 R108 R109 R114 R115 R118 8123 0402 Multilayer ceramic capacitor 50 V X7R 0603 Multilayer cer
5. 8889 NAA 549 555 n 5 zi 5 82 sri 0 2 6869 200 5 aic 619 gal aaraca n 143 5869 AAA 01 5 2191 Zvivasv LOH euer WN tel lt 5869 A AA tel 1 lt tel 1v1vasa 191 ZV1vOSU lt vivasaciuiQH lt Figure 18 Board Schematics Page 2 Serial Digital Audio Interface Headers with MCLK Direction Switching Rev 0 Page 10 of 32 610 2780 5 537 20 45695 134 5 120 410 yes 5923 0 55 x x 8 2 n teu 088 te s A 9058 D ONH g y 9098 lt 4045 ls te ud NEN 8 a c 1999 158 13538 un m pio z unash 0098092 tel 01935 013 9048 tvi 42 DOH
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7. a a 04572358 1595 18581 1863 93v 19 521 1 45 993 zvivasy 1 03 310810 1963 co s 218050 161 0142 1 050 9562 evivasa co s v69 Figure 20 Board Schematics Page 4 Serial Digital Audio Routing and Control CPLD Rev 0 Page 12 of 32 120 2780 8641 8 41 0041 Y Y 19691 M gt dsa aug augnav TZ ON 1SdS E TT ss n sri 43634 jy 1 ba quracaq zo 2 4 xass rri los 161 Sud 44nH OY10n pri gt 2m Eu mE 55522 22222 5 roo 1891 m 4 own acs WS ata A yi 5 1991 eel 3 2 Ep 1912 sr 19 175 prog 18591 5 2 n wino Cj zn 2 n v R kn m QOS WW wino lt ro Z
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11. HEADER _12WAY_UNSHROUD 37 3 5 Sto 99510 21 Wo 48 151 1938 11 2 5 4 GND 16 7 8 91 OUT3L 5 7 00141 5 7 RESET 3 51 12 5 4 5 16 7 8 91 DSDATAS 4 51 4 5 DLRCLK 4 5 5 1 4 5 ALRCLK 4 51 1938 PIN24 5 81 1938 PIN26 5 8 OUTIL 15 72 09721 15 71 GND 1 2 3 4 5 6 7 8 9 CN 5 INIL 1 51 N R 1 51 IN2L 1 53 IN2R 1 51 2 1938 5 6 08421 022 Figure 22 Board Schematics Page 6 Daughter Card Interface Useful as Test Points Rev 0 Page 14 of 32 220 12780 m 469 3906 001 OdN 2 022 shy XL 11 pis 9612 3805 6819 TY 1 4 jarino 963 AU AZI AZI 3800 us 65 792 15951240 15991290 1598140 75961240 2 62 2 2 92 60 02 90 9 9 8 8 72 612 282 99 sai yl NN DT 582 YL 71 42170 1951 250 1595129 E 200121 eso 2 39069 von Y 5 Lwin t ri 0241 a s 49 48069 uz d rz s l 4922
12. HERB Linet EH f B t 25 evoe 203 EL 13 is HED OD DE 1 1 xi m l 13V300 GND TRO 2 __Js BOWER SUPPLY Stonddone Moster Mode 15 6 6 8 0 Far t t 2387 503 SCL Eu HE zu SPI 4 om 7 S PDIF ons DAC 182 zc iH ce INTERFACE sib 2 4 ma AUDIO d s HE AE 1 223 anseres h ur r ss input butters 19 AD185 ADC er Selon PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS D mise 00000000 00000000 ES ap 12 mimi BEL D 8224 CLOCK amp DATA RQUTING 23 B urus m B gre x Lay 98 EVAL AD1938AZ UE z Rev 1 0 9 ni CIm 1 8 2 3 Figure 1 Rev 0 Page 1 of 32 TABLE OF CONTENTS EVAL AD1938AZ Package Contents see 1 Poweritig the Board eet eet 3 Other Supporting Documentation eene 1 Setting Up the Master Clock MCLK sss 4 Evaluation Board sse 1 Configuring the PLL Filter seen 5 Functional Block Diagram seen 1
13. 2 4 DL4001 TP 8 1 3 Figure 25 Board Schematics Page 9 Power Supply Rev 0 Page 17 of 32 z d Or QE e Control Interface s 8 7 E 1 915 cI z m 1143 iul 8 RS l 12VDC HD 12VDC cJ m B 5 z A uu zi 1 A3V 3DD D3V3DD GND OPTICAL N EERE a L Ju For Standalone Master Mode J5 1 J6 8 0 T For Standalone Slave mode 5 8 0 p m For SP Control 401938 45 8 COUT CIN CEATCH LH 8 GND a VS 2122 ues e en 1 e 299895899 OUTIL 5 E Ur ut ELE cm x COAX al TPS TZA OUTI E 89 SPDIF INPUT SELECT 831 k z 27 5 IN OUTIR shore OUTIR SPDIF Receive Settings OPTICAL OUT GND NVERR un ESSET DUT2L aE m 3976 9 SPD ouTPUT 0072 Si ENS 1 Apply 4 JP12 JP13 18 14 JP17 JP21 JP26
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15. r T tore WN ix 1 1 185 1040 11 axo anoo 00 009 21 Figure 19 Board Schematics Page 3 S PDIF Receive and Transmit Interfaces Rev 0 Page 11 of 32 020 12980 003 104 0301 2 CZ AVIVI ZYH Z ZYLVOSY_ZYOH 121 vivosv zugH 2 23 10 6 i NTON 908 t VLVOS 90v8 1 1 4108 9098 62 12 9098 2 SWaY 008 62 1135 9059 163 01145 9099 152 NOUT Nye t 119878199 te vavos siya 16 013845 79198 swos 9178 163 113625 918 88 28 Hia 066914 ANVIOM 75 E ir 18 woo T 2 066914 Auv1OU zl PEL 21 5025 030 538 75087138 zay Wavasc ZuaHtz ZVLVOSG ZUOH IZ SVLVOSO_ZYOH Z 290 21 X128 LYOH 23 DEV LY LYOSV LAOH CZI TViVOSV iMOHIC 085723597 1545 23 LYOHIZI Vyivqsi hitHtz 1 h HtZ1 PY IVOSO LYOHIZ 9001N62 A9ZI2T 391L1v1 050 1 an 0301 5388 13N 1814 12 001 e i eo 2051 2005 101 097
16. 02 Conversion 2 U18 U22 Buffer three state single gate Texas Instruments SN74LVC1G125DRLR 1 U4 Octal three state buffer driver Texas Instruments SN74LVC541ADBR Rev 0 Page 28 of 32 Qty Designator Description Manufacturer Part Number 2 SW2 SW3 SPDT slide switch PC mount E Switch EG1218 2 S2 53 8 position SPST SMD switch flush actuated CTS Corp 219 8LPST 1 S6 Tact switch 6 mm gull wing Tyco Alcoswitch FSM6JSMA 1 U5 15 Mb sec fiber optic receiving module Toshiba TORX147L FT with shutter 1 U7 Fiber optic transmit module 15 Mb sec Toshiba TOTX147L FT 60 TP1 to TP6 TP8 to TP10 TP12 to Mini test point white 0 1 inch OD Keystone 5002 TP15 TP17 TP19 to TP23 TP25 to Electronics TP52 TP54 to TP60 TP62 TP64 to TP68 Rev 0 Page 29 of 32 NOTES Rev 0 Page 30 of 32 NOTES Rev 0 Page 31 of 32 NOTES ESD Caution ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Legal Terms and Conditions By using the evaluation board discussed herein together with any tools components documentation or support materials the Evaluation Board you are agreeing to be bound by the
17. 11504 9 uonisod 14011504 65 YOUMS diq 34919181 31518161 31518161 31518161 49159 ndino ndino 9 19159 ndino ndino ndino yndu 8 indino indu 29152 dul 6 Josey indu 8 V N V N ndul 1 9 8 V N v 1 Y N indu T B dul V N dul dul 2 1152 V N L BA V N Y N Y N Y N 0 LAOH 446 bvivasd 1 V1VOSQ vivasd 1 1V1VOSG 1 050 vova cova zv1vasa zovq tvivasa ova 4011504 75 SUID OVQ JOJOBUUOD 1 pue suld JO OY sejeoipur JUBJUOD ULUNJOD V1VOSQ ZYLYASA 1 ereisu t aLYLSIHL 31 181 1 BIVISIHI BIVISIML 01 091915 3 3 a NQ L uo OS Zv1 VOS seur geq 10 99UU0D LHOH indino zovq xny indui zoav xny
18. HDR1 ABCLK oe ADC S PDIF 4 ADC 1 ADC DAC HDR1 ALRCLK oe ADC S PDIF 4 ADC 1 ADC DAC BCLK 8416 0e DAC S PDIF IRCLK_8416 0e DAC S PDIF BCLK 8416 I DBCLK 8416 I DLRCLK DSDATAl1 oe DAC DATA HIZ DSDATA2 oe DAC 1 DAC DUAL DAC DATA HIZ DSDATA2 is output DAC TDM daisy chain mode DSDATA3 oe DAC DATA HIZ DSDATA4 0e DAC DUAL ADC HDR AUX DAC HDRI AUX 4 DAC DATA HIZ SECOND TDM OUT IN DUAL LINE DAC TDM MODE ASDATA2 oe ADC HDR TDM ASDATA2 is input in TDM mode HDR1 DSDATA2 oe DAC HDRI DAC DUAL Rev 0 Page 24 of 32 HDR1 DSDATA4 oe DAC DUAL ADC HDR AUX DAC HDR1 AUX 1 ASDATA2 0e ADC HDR DBCLK I DBCLK DLRCLK I DLRCLK ABCLK I ABCLK ALRCLK I ALRCLK DSDATAl HDR1 5 1 6 DAC HDRI ALL DAC 1 IND DAC RX 2 DAC RX 3 DAC RX 4 4 DAC 1 DAC DUAL AUX SDATA 8416 amp DAC RX ALL DAC RX 1 amp DATA ZERO DSDATA2 1 DSDATA1 6 DAC HDRI ALL HDRI DSDATA2 amp DAC HDRI IND ADC HDR AUX DAC HDRI AUX DA
19. S PDIF changes active on reset Rev 0 Page 23 of 32 BCLK 8416 and LRCLK 8416 are bi DAC S PDIF SOMS 0 DIR RJ DIR RJ16 Serial Output Master Slave Select Serial Format Select 1 1 DIR I2S 4 DIR DSP Serial Format Select 0 S PDIF MCLK RATE lt RMCKF M3 8414 CS8404 Tx interface mode select APMS TX 0 Tx serial port is always slave in this application SFMT1 SFMTO TX 1 Tx data format is 125 always M 8404 M1 8404 M2 8404 0 0 1 I2S format only divide 256Fs clock by 2 for 128Fs clock to the the S PDIF Tx Qdivide clk CPLD MCLK Odivide d Qdivide MCLK_8406 Qdivide MCLK 8406 CPLD MCLK BCLK_8406 I_ABCLK LRCLK_8406 I_ALRCLK SDATA 8406 ASDATA1 6 S PDIF OUT ASDATA2 6 S PDIF OUT MUX For SPI mode let external port drive the SPI port DBCLK oe DAC S PDIF DAC HDRI DAC ADC 4 DAC DAC amp DAC CLK OFF DLRCLK oe DAC S PDIF DAC HDRI DAC ADC 4 DAC DAC 6 DAC OFF ABCLK oe ADC S PDIF 4 ADC HDR1 ADC ADC ADC DAC 6 CLK OFF ALRCLK oe ADC S PDIF 4 ADC HDR1 ADC ADC ADC DAC 6 CLK OFF HDR1 DBCLK oe DAC S PDIF 4 DAC 1 DAC ADC 4 DAC DAC HDR1 DLRCLK oe DAC S PDIF DAC_HDR1 DAC ADC 4 DAC DAC
20. both DIP switches 52 and 53 set to off and both rotary hex mode switches 54 and 55 set to 0 the S PDIF receiver is the LRCLK BCLK and SDATA source The default MCLK jumper setting routes MCLK from the S PDIF receiver to the AD1938 With a valid S PDIF data stream connected to the selected S PDIF input port the board passes audio from the S PDIF port to all four stereo outputs and from Stereo INI to the S PDIF output ports IN2 can be selected by changing 3 Position 8 to on Other serial audio clock and data routing configurations are described in the Switch and Jumper Settings section SPI CONTROL The evaluation board can be configured for interactive control of the registers in the AD1938 by connecting the SPI port to the USBi The SPI jumper settings are shown in Figure 4 08421 004 Figure 4 SPI Control The Automated Register Window Builder software controls the AD1938 and is available at www analog com AD1938 AUTOMATED REGISTER WINDOW BUILDER SOFTWARE INSTALLATION The Automated Register Window Builder is a program that launches a graphical user interface for direct live control of the AD1938 registers The GUI content for the part is defined in a part specific xml file this file is included in the software installation To install the Automated Register Window Builder software follow these steps 1 Atwww analog com AD1938 find the Resources Tools list 2 In the list find Evaluation Boards amp
21. of the Evaluation Board are reserved by ADI CONFIDENTIALITY This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason Upon discontinuation of use of the Evaluation Board or termination of this Agreement Customer agrees to promptly return the Evaluation Board to ADI ADDITIONAL RESTRICTIONS Customer may not disassemble decompile or reverse engineer chips on the Evaluation Board Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board including but not limited to soldering or any other activity that affects the material content of the Evaluation Board Modifications to the Evaluation Board must comply with applicable law including but not limited to the RoHS Directive TERMINATION ADI may terminate this Agreement at any time upon giving written notice to Customer Customer agrees to return to ADI the Evaluation Board at that time LIMITATION OF LIABILITY THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED AS IS AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS ENDORSEMENTS GUARANTEES OR WARRANTIES EXPRESS OR IMPLIED RELATED TO THE EVALUATION BOARD INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY TITLE FITNESS FOR A PARTICULA
22. terms and conditions set forth below Agreement unless you have purchased the Evaluation Board in which case the Analog Devices Standard Terms and Conditions of Sale shall govern Do not use the Evaluation Board until you have read and agreed to the Agreement Your use of the Evaluation Board shall signify your acceptance of the Agreement This Agreement is made by and between you Customer and Analog Devices Inc ADI with its principal place of business at One Technology Way Norwood 02062 USA Subject to the terms and conditions of the Agreement ADI hereby grants to Customer a free limited personal temporary non exclusive non sublicensable non transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above and agrees not to use the Evaluation Board for any other purpose Furthermore the license granted is expressly made subject to the following additional limitations Customer shall not i rent lease display sell transfer assign sublicense or distribute the Evaluation Board and ii permit any Third Party to access the Evaluation Board As used herein the term Third Party includes any entity other than ADI Customer their employees affiliates and in house consultants The Evaluation Board is NOT sold to Customer all rights not expressly granted herein including ownership
23. 19 41085 eounogs 4 1 922005 51198V 20 uonisod 2 uonisod syoolo OAV eieisu eigesiq uo syoolo lqeuzi lqesiq 2012 1 8 uondu s q uonisog uonisod zs dia Figure 15 Settings Chart 1 Rev 0 Page 7 of 32 ROTARY AND DIP SWITCH SETTINGS eoinos 8 8 2055 ul 1 164 pue 624 ezdr Bulsn PINOYS 1 1 6 LAY SUL 2 Ahu pu d pul p llonuo2 si jenas pue OGY ANNOS eui eq ULI 8 Oyq JO 50010 eues JAY LHOH 4012euu02 91 850 49AI928H JI ads uo p seq 53 9 s 5 24 05 YOOID 1 0 JO BUD 1 9 y ol pue OAV XE6 LAY 9ui ZS YOUMS diq L 25 pue uonoejes 419H1 51198 49019 1 pue uonejedo 2211415 40 eq ued sjeduinf aape y gr pue f Gr eu uogejedo Ozl l4S euojepueis eui xe6 LAY 991 2 JeyiusueJ pue 19419991 41045 94 jo 10 dn jewod Jaye
24. 1938AZ 200 870 6201 OUT4R ya Rev 1 0 px H EJ ED 8 4 Figure 26 Top Assembly Layer Rev 0 Page 18 of 32 08421 026 Evaluation Board User Guide 08421 027 Figure 27 Bottom Assembly Layer Rev 0 Page 19 of 32 CPLD CODE MODULE IF_Logic TITLE AD1938 EVB Input Interface Logic FILE AD1938_pld_revE abl REVISION DATE 04 16 09 rev E REVISION E DESCRIPTION LIBRARY MACH INPUTS AD1938 CODEC pins DSDATA1 DSDATA2 pin 86 87 istype com DSDATA3 DSDATA4 pin 91 92 istype com DBCLK DLRCLK pin 85 84 istype com ASDATA1 ASDATA2 pin 80 81 istype com ABCLK ALRCLK pin 78 79 istype com 25 pin header connector HDRI pins HDR1_DSDATA1 pin 20 istype com HDR1_DSDATA2 pin 19 istype com HDR1_DSDATA3 pin 17 istype com HDR1_DSDATA4 pin 16 istype com HDR1_DBCLK pin 21 istype com HDR1_DLRCLK pin 22 istype com HDR1_ASDATA1 pin 29 istype com buffer HDR1_ASDATA2 pin 28 istype com buffer HDR1_ABCLK pin 30 istype com HDR1_ALRCLK pin 31 istype com 25 pin header connector DR2 DR2 DR2 S PDIF Rx CS8414 pins HDR2 HDR2 HDR2 HDR2_ HDR2_ HDR2_ DS DS DS DS DL _AS _AS _AL DATA1 DATAZ DATA3 DATA4 DBCLK RCLK DATA1 DATA2 HDR2_ABCLK RCLK SDATA_8416
25. ANALOG DEVICES Evaluation Board User Guide UG 045 One Technology Way Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 Fax 781 461 3113 www analog com Evaluating the AD1938 Four ADC Eight DAC with PLL 192 kHz 24 Bit Codec EVAL AD1938AZ PACKAGE CONTENTS AD1938 evaluation board USBi control interface board USB cable OTHER SUPPORTING DOCUMENTATION AD1938 data sheet EVALUATION BOARD OVERVIEW This document explains the design and setup of the evaluation board for the AD1938 The evaluation board must be connected to an external 12 V dc power supply and ground On board regulators derive 3 3 V supplies for the AD1938 The AD1938 is controlled through an SPI interface A small external interface board EVAL ADUSB2EBZ also called USBi connects to a PC USB port and provides SPI access to the evaluation board through a ribbon cable A graphical user interface GUI program is provided for easy programming of the chip in a Microsoft Windows PC environment The evaluation board allows demonstration and performance testing of most AD1938 features including four ADCs and eight DACs as well as the digital audio ports Additional analog circuitry ADC input filters DAC output filter buffer and digital interfaces such as S PDIF are provided to ease product evaluation All analog audio interfaces are accessible with stereo audio 3 5 mm TRS connectors FUNCTIONAL BLOCK DIAGRAM
26. BC10DAAN or cut PBC36DAAN 2 120 126 Connector header 0 100 dual STR 72 POS Sullins PBC13DAAN or cut PBC36DAAN 4 J5 to J8 Connector header 0 100 dual STR 72 POS Sullins PBCOGDAAN or cut PBC36DAAN 2 SA S5 16 position rotary switch hex APEM PT65503 19 JP4 to JP7 11 to JP 14 JP17 2 pin header unshrouded jumper 0 10 Sullins PBCO2SAAN or cut JP18 JP20 to JP22 JP24 JP26 use shunt Tyco 881545 2 PBC36SAAN JP28 to JP31 11 to JP8 JP10 JP15 JP19 3 position SIP header Sullins PBCO3SAAN or cut JP23 25 JP27 PBC36SAAN 1 U16 Complex programmable logic devices Lattice LC4128V 75TN100C CPLD HI PERF E2CMOS PLD Semiconductor 1 D11 Green diffused 10 millicandela 565 nm Lumex Opto SML LX1206GW TR 1206 2 D6 D9 Red diffused 6 0 millicandela 635 nm Lumex Opto SML LX1206IW TR 1206 2 D7 D10 Yellow diffused 4 0 millicandela 585 nm CML Innovative CMD15 21VYD TR8 1206 Tech 2 U2 U3 3 term adjustable voltage regulator DPak STMicroelectronics LM317MDT TR 6 J10 J11 J13 J21 J27 J28 Sterero mini jack SMT CUI 5 3523 5 2 R161 R162 Resistor network bussed 9 res CTS 773091103 8 U6 U9 U12 U14 U17 U20 U24 Dual bipolar JFET audio op amp Analog Devices OP275GSZ U25 1 U21 12 288 MHz fixed SMD oscillator 1 8 V dc to Abracon Corp AP3S 12 288MHz F J B 3 3 V dc 2 J9 J12 RCA jack PCB TH mount R A yellow Connect Tech CTP 021A S YEL Products 1 U10 110 AES EBU transformer Scientific 5 937
27. C ERJ 3EKF4992V film 0603 20 R103 R104 R110 to R112 R116 Chip resistor 49 9 1 63 mW thick film Rohm MCRO1MZPF49R9 R119 R124 R126 to R128 R130 to 0402 R132 R142 to R147 35 R8 to R10 R15 to R17 R19 R92 Chip resistor 49 9 kQ 1 100 mW thick Panasonic EC ERJ 3EKF49R9OV R95 R100 R105 R113 R120 R125 film 0603 R133 R135 R139 R153 R155 R156 R160 R174 R175 R178 R187 R188 R190 R194 R196 R200 R201 R203 R206 R210 R215 16 R25 R26 R32 R34 R45 R46 R61 Chip resistor 49 9 kQ 1 100 mW thick Panasonic EC ERJ 3EKF4641V R68 R181 R182 R192 R195 R208 film 0603 R209 R218 R220 16 R21 to R23 R27 R33 R35 to R37 Chip resistor 49 9 kQ 1 100 mW thick Panasonic EC ERJ 3EKF4751V R39 R41 R42 R50 R62 R69 to film 0603 R71 1 C131 Multilayer ceramic capacitor 25 V NPO TDK Corp C1608C0G1E562J 0603 1 R138 Chip resistor 562 196 125 mW thickfilm Panasonic EC ERJ 3EKF5620V 0603 16 R72 R73 R79 R85 to R87 R97 Chip resistor 5 76 kO 196 125 mW thick Panasonic EC ERJ 3EKF5761V R107 R121 R122 R137 R150 to film 0603 R152 R165 R171 4 C78 C137 C171 C195 Multilayer ceramic capacitor 100 V NPO Panasonic EC ECJ 1VC2A680J 0603 1 U11 IC inverter hex TTL LSTTL 14 SOIC NXP Semi 74HCO4D T 2 U19 U26 IC buffer quad three state 14 SOIC Texas Instruments SN74LV125AD 1 R29 Chip resistor 75 196 100 mW thick film Panasonic EC ERJ 3EKF75ROV 0603 1 R67 Chip re
28. C RX 1 DAC RX 3 RX 4 SDATA 8416 DAC RX ALL DAC RX 2 0 amp DAC DATA ZERO DSDATA3 1 DSDATA1 6 DAC HDRI ALL 1 DSDATA3 amp DAC HDR1 IND DAC DUAL 4 AUX DAC HDRI AUX DAC RX 1 DAC RX 2 DAC RX 4 SDATA 8416 amp DAC RX ALL DAC RX 3 0 amp DAC DATA ZERO DSDATA4 1 DSDATA1 6 DAC HDRI ALL HDR1_DSDATA4 8 DAC HDR1 IND DAC RX 1 4 DAC RX 2 DAC RX 3 SDATA 8416 amp DAC RX ALL DAC RX 4 0 amp DAC DATA ZERO HDR1_DBCLK I DBCLK HDR1 DLRCLK I DLRCLK HDR1 ABCLK I ABCLK HDR1 ALRCLK I ALRCLK HDR1 ASDATA1 ASDATA1 amp HDR NORMAL ADC HDR ADC HDR AUX DAC 1 AUX 4 ASDATA2 amp HDR DATA2 DATA1 HDR1_ASDATA2 ASDATA2 ASDATA2 HDR1_ASDATA2 HDR1_DSDATA2 DSDATA2 HDR1_DSDATA4 DSDATA4 Internal node signals I_DBCLK BCLK 8416 amp DAC S PDIF HDRI DBCLK amp DAC HDR1 4 DBCLK amp DAC DAC 4 1 ABCLK amp DAC ADC I DLRCLK LRCLK 8416 amp DAC S PDIF HDR1_DLRCLK 6 DAC HDR1 DLRCLK 6 DAC DAC 4 I ALRCLK 6 I_ABCLK BCLK 8416 amp ADC S PDIF HDRI ABCLK amp ADC HDR1 ABCLK amp ADC_ADC 4 I_DBCLK amp DAC I ALRCLK LRCLK 8416 6 S PDIF HDRI ALRCLK amp HDR1 ALRCLK 6 ADC 4 I DLRCLK amp ADC DAC
29. C1H220J ERJ 3EKF2370V ERJ 3EKF2430V MCRO1MZPF24R9 Rev 0 Page 26 of 32 Qty Designator Description Manufacturer Part Number 16 R56 R57 R65 R66 R88 R89 R140 Chip resistor 24 9 1 100 mW thick film Rohm MCRO3EZPFX24R9 R154 R179 R183 R213 R216 0603 R228 to R231 8 C25 C31 C45 C53 C169 C181 Multilayer ceramic capacitor 50 V NPO Rohm MCH185A271JK C190 C198 0603 3 R3 R11 R58 Chip resistor 374 O 1 100 mW thick film Rohm MCRO3EZPFX3740 0603 1 C125 Multilayer ceramic capacitor 50 V NPO Panasonic EC ECJ 1VC1H391J 0603 4 R5 R52 R53 R75 Chip resistor 392 O 196 100 mW thick film Rohm MCRO3EZPFX3920 0603 1 C120 Multilayer ceramic capacitor 16 V ECH U Panasonic EC ECH U1C393JB5 1206 33 R38 Chip resistor 3 01 kO 196 100 mW thick Rohm MCRO3EZPFX301 1 film 0603 1 R129 Chip resistor 3 32 kO 196 100 mW thick Rohm MCRO3EZPFX3321 film 0603 8 C24 C34 C44 C56 C167 C185 Multilayer ceramic capacitor 50 V NPO Murata ENA GRM1885C1H431JA01D C189 C201 0603 30 C11 C14 C22 C26 C27 C30 C32 Aluminum electrolytic capacitor 16 V Panasonic EC EEE FC1C470P C35 C41 C46 C47 C52 C54 C57 FC 105 deg SMD_D C63 C66 C72 C75 C80 C105 C119 C133 C139 C148 C152 C164 C172 C179 C191 C196 3 C12 C18 C19 Aluminum electrolytic capacitor FC Panasonic EC EEE FC1E470P 105 deg SMD_E 4 R83 R96 R148 R163 Chip resistor 49 9 kQ 1 100 mW thick Panasonic E
30. CLKO port to drive the CPLD and possibly the g l m ERF HDRs The passive crystal runs the AD1938 at 12 288 MHz C168 A 22 M EXT CLK IN Figure 11 shows the MCLKI shut off this is the case when the d us e m 8 PLL is set to LRCLK instead of MCLK 8 193X_MCLKI Figure 6 S PDIF Receiver as MCLK Master the AD1938 and CPLD as Slaves JP20 MCLKO C147 193X_MCLKI sk ALT DISABLE u rki el 7 E 8 Mg JP18 5 JP20 MCLKO C147 R160 22 oy m e J22 17 sim elem rig os e Ta 78 s s Coe S mis R160 JP22 o lz sml d lm e m 193X_MCLKO aim ejm lb 021 Ea C158 LL cole ele fl o 193X MCLKO 5 J23 Er 2 OSCDISABLE z nrr28 m el 9 JP28 a R169 EXT e m ale m JP27 H o 323 R175 OSC DISABLE ibar F Mn JP28 5 g l EXT CLK IN EXT dil m lale 2 c170 mE R175 HDR2 e m e 5 elem EXT CLK IN 8 s l m 170 xi HDR2 5 Figure 10 Passive Crystal AD1938 Is Master CPLD Is Slave from E the MCLKO Port Figure 7 HDR1 as MCLK Master the AD1938 CPLD and HDR2 as Slaves Rev 0 Page 4 of 32 193X_MCLKI DISABLE JP18 JP20 MCLKO C147 ax ES gp le xr 29 922 1938 MCLKI n
31. Connecting Audio 5 Revision 2 Switch and Jumper 2 5 Setting Up the Evaluation 3 Rotary and DIP Switch Settings 7 Standalone reed e een 3 Schematics and Artwork serene 9 HH ER 3 Code indie aE EREE Rene 20 Automated Register Window Builder Software Installation 3 Ordering Information sese 26 Hardware Setup USBi 3 26 REVISION HISTORY 2 10 Revision 0 Initial Version Rev 0 Page 2 of 32 SETTING UP THE EVALUATION BOARD STANDALONE MODE It is possible to run the board and the AD1938 codec in stand alone mode which fixes the functionality of the AD1938 into the 125 data format running at 256 x fs default register con dition The ADC BCLK and LRCLK ports are flipped between slave and master input and output by tying SDA COUT Pin 24 to low or high This is accomplished by moving the J5 jumper to either 0 or SDA 1 see Figure 2 and Figure 3 for the correct settings 45 46 J7 J REE 8 ADDRO ADDR1 SDA 1 COUT CIN SCL CCLK 08421 002 o Figure 2 Standalone Slave Mode 102202302 5 5 orzo a or 5 2 x 5 5 ADDROO ADDRIIE 4 5 Figure 3 Standalone Master Mode With the control jumpers set to standalone slave mode
32. Development Kits and click Evaluation Boards Tools to open the provided ARWBvXX zip file 3 Double click the provided msi file to extract the files to an empty folder on your PC 4 Then double click setup exe and follow the prompts to install the Automated Register Window Builder A computer restart is not required 5 Copy the xml file for the AD1938 from the extraction folder into the C Program Files Analog Devices Inc AutomatedRegWin folder if it does not appear in the folder after installation HARDWARE SETUP USBi To set up the USBi hardware follow these steps 1 Plug the USBi ribbon cable into the J1 header Connect the USB cable to your computer and to the USBi When prompted for drivers follow these steps a Choose Install from a list or a specific location b Choose Search for the best driver in these locations c Check the box for Include this location in the search d Find the USBi driver in C Program Files Analog Devices Inc AutomatedRegWin USB drivers Click Next If prompted to choose a driver select CyUSB sys g Ifthe PC is running Windows XP and you receive a message that the software has not passed Windows logo testing click Continue Anyway mo You can now open the Automated Register Window Builder application and load the xml file for the part on the evaluation board POWERING THE BOARD The AD1938 evaluation board requires a power supply input of 12 V dc and ground to t
33. HDR2 pins pin pin pin pin pin pin pin pin pin pin pin 37 istype com 36 istype com 35 istype com 34 istype com 41 istype com 42 istype com 44 istype com 43 istype com buffer 47 istype com 48 istype com 61 istype com Rev 0 Page 20 of 32 BCLK_8416 pin 60 istype com LRCLK_8416 pin 59 istype com SOMS RX SFSEL1 RX SFSELO RX RMCKF pin 66 67 64 65 istype com S PDIF Tx CS8404 pins SDATA 8406 pin 50 istype com BCLK 8406 LRCLK 8406 pin 53 54 istype com MCLK 8406 pin 49 istype com 5 5 1 TX SFMTO TX pin 55 56 58 istype com CPLD MCLK pin 89 istype com AD1938 SPI port pins CCLK CDATA CLATCH pin 84 83 85 istype com COUT pin 82 istype com CLATCH2 CLATCH3 CLATCH4 pin 86 56 4 istype com CONTROL pin 81 istype com S PDIF RESET OUT pin 69 istype Looms Switch S1 S2 53 and S4 pins ADC CLK OFF pin 93 istype com S2 1 ADC CLK SRC1 pin 94 istype com 82 2 ADC CLK SRCO pin 97 istype com S2 3 DAC CLK OFF pin 98 istype com 52 4 DAC_CLK_SRC1 pin 99 istype com 52 5 DAC_CLK_SRCO pin 100 istype com 52 6 S PDIF_MCLK_RATE pin 3 istype com Lf 2 1 S PDIF RESET IN pin 4 istype com 52 8 MODE11 MODE12 MODE13 MODE14 pin 5 6 8 9 isty
34. MODE13 6 MODE12 amp MODE11 S4 position 9 DAC HDR1 IND MODE14 8 MODE13 6 MODE12 amp MODE11 S4 position A DAC 1 MODE14 8 MODE13 6 MODE12 8 MODE11 Rev 0 Page 22 of 32 S4 position DAC DUAL MODE14 8 MODE13 6 MODE12 8 MODE11 S4 position C DAC_HDR1_AUX MODE14 amp MODE13 6 12 amp 11 S4 position D NA3 MODE14 amp MODE13 6 MODE12 6 MODE11 S4 position E NA4 MODE14 amp MODE13 amp IMODE12 6 MODE11 S4 position F DAC DATA HIZ MODE14 amp MODE13 amp IMODE12 amp IMODE11 Switch S2 DAC S PDIF DAC CLK 5 6 DAC CLK SRCO DAC HDRI DAC CLK SRCI amp DAC CLK SRCO DAC ADC DAC CLK 58 1 amp DAC CLK SRCO DAC DAC DAC CLK SRCI amp DAC CLK SRCO S PDIF ADC CLK SRC1 amp SRCO ADC HDRI CLK SRCI 6 ADC CLK SRCO ADC ADC ADC CLK 58 1 amp ADC CLK SRCO ADC DAC ADC CLK 58 1 amp ADC CLK SRCO EQUATIONS S PDIF_RESET_OUT S PDIF_RESET_IN Configuration of the CS8416 directional signals SOMS_RX SFSEL1_RX SFSELO_RX RMCKF_RX SFSI zl SFSI ET 0 Receive Master Clock Frequency 0 8414 1 8414 2 8414 0 1 0 DAC
35. Position 7 This shows the SNR of the DACs To use other rates the USBi must be connected and the AD1938 registers must be programmed accordingly For example adjusting the fs rate to 96 kHz requires that the ADC and DAC Control 0 registers have sample rates set to 96 KHz see Figure 15 and Figure 16 for the complete list of options The CPLD code is presented in the CPLD Code section and is included with the evaluation board alterations and additions to the functionality of the CPLD are possible by altering the code and reprogramming the CPLD Rev 0 Page 6 of 32 8 0 12980 5 88 XL 1048 1 0 ESay eui 4q eui 2 5 seuruuejep A Spxggz XL 1446 0 0 eS3v jo 2 5 indul A 0 Older 5 909869 XL 41445 yoyew oipne siseudui3 oipne siseudu3 0 p l s 90852 XL 41046 nil y o 40128 ep ayes nil 12 euuoN 0 917850 41045
36. R PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER S POSSESSION OR USE OF THE EVALUATION BOARD INCLUDING BUT NOT LIMITED TO LOST PROFITS DELAY COSTS LABOR COSTS OR LOSS OF GOODWILL ADI S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS 100 00 EXPORT Customer agrees that it will not directly or indirectly export the Evaluation Board to another country and that it will comply with all applicable United States federal laws and regulations relating to exports GOVERNING LAW This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts excluding conflict of law rules Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County Massachusetts and Customer hereby submits to the personal jurisdiction and venue of such courts The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed 2010 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners UG08421 0 2 10 0 DEVICES www analog com Rev 0 Page 32 of 32
37. V AB 5 AVMS 3H GNOYHSNN AV AB H30V3H Ln gn Br VA Bia m 2 2 3801 3801 380 913 gt 6 gt 6967 1002 ae ine ine _ 182995 Diol 1812708 CH o o 192 1109 0110 216 Mi l 22 x ni sn oe 1047 AVMO 6867 181 181 4199 181 21 12 ozu 2012 1 070 0101 5 1H21v32 SPI Control Interface Figure 24 Board Schematics Page 8 Rev 0 Page 16 of 32 D3V3DD TPS 2 3 ADJ 1 LM317MDT cs 2438 374R 5i dicm z 1 0158 cn 0 10uF SER 47uF 0 10uF 47uF 47 E R5 v 392R Na 600 Ohm 100 MHz Yellow Diffused gt A3V3DD 122 12V 05 1 J4 121 12V DL4001 TP 2 1N out 5 155 6 SD ERR id 4 3 SNO MR 61 3748 R ADP3303ARZ 3 3 E TL ct C28 es 47uF 0 10uF 0 10uF 47uF M Y 15V D6 TP58 43 d L cis 05 47uF 15V N 21N 12
38. a si onon zadn lt w a rin C re v1vas evivasa Ig s y oni RES iivas o 01 wino zen 00 0 009 BUA Zisagce oy Um vas T unu CHo lt wa wino Cyn auno 1 5 n sc 2 2 wa Carto z an gt gt gt gt 5555 5 ONTON eu bend xiu rn i08 o a Y T AAA sza 2 MWOSZISI2ATeZNS 8 g 3 8 tel vas mE wr 3 Qo c orar Figure 21 Board Schematic Page 5 AD1938 with MCLK Selection Jumpers Rev 0 Page 13 of 32 11 2 5 4 51 6 7 8 9 GND 1511938 MCLKO 15 61 001 1958 5 7 OUT3R 5 7 00148 2 5 50 4 570 00 1938 14 51 050 2 14 51 DBCLK 4 5 ASDATA2 4 51 ABCLK 15 811938 23 2 3 4 51 6 7 8 9 GND 5 81 1938 PIN27 5 71 OUTIR 5 71 OUT2R 5 61 1 1938 151 FILTR 15 61 AVDD2 1938 E55 INIL 1 5 INIR 1 5 IN2L 1 51 IN2R 5112 418 HEADER 12WA Y UNSHROUD 24 415 HEADER_12WAY_UNSHROUD 25 1 7 51 12 417 HEADER_12WAY_UNSHROUD gt 15 11111 H 5 7 119042 36
39. amic capacitor 50 V NPO 0603 Chip resistor 100 kQ 1 125 mW thick film 0603 Multilayer ceramic capacitor 50 V NPO 0603 Chip resistor 100 kQ 1 100 mW thick film 0603 Aluminum electrolytic capacitor 100 pF 16 V FC 105 deg SMD E Chip resistor 10 kO 196 125 mW thick film 0603 Multilayer ceramic capacitor 25 V NPO 0603 Multilayer ceramic capacitor 100 V NPO 0603 Multilayer ceramic capacitor 50 V NPO 0402 Aluminum electrolytic capacitor 16 V FC 105 deg SMD B Multilayer ceramic capacitor 50 V NPO 0603 TVS Zener 15 V 600 W SMB Multilayer ceramic capacitor 50 V NPO 0603 Multilayer ceramic capacitor 25 V NPO 0805 Multilayer ceramic capacitor 50 V NPO 0603 Chip resistor 237 O 196 125 mW thick film 0603 Chip resistor 243 O 196 100 mW thick film 0603 Chip resistor 24 9 O 196 63 mW thick film 0402 Panasonic EC Panasonic EC Panasonic EC Panasonic EC Panasonic EC Panasonic EC Panasonic EC TDK Corp Panasonic EC Kemet Panasonic EC Panasonic EC ON Semiconductor Murata Electronics Murata ENA Panasonic EC Panasonic EC Panasonic EC Rohm ECJ 1VB1H104K ECJ 1VC1H102J ERJ 3EKF 1003V ECJ 1VC1H101J ERJ 3EKF 1000V EEE FC1C101P ERJ 3EKF 1002V C1608C0G1E103J ECJ 1VC2A100D C0402C100J5GACTU EEE FC1C100R ECJ 1VC1H121J 1SMB15AT3G GRM1885C1H222JA01D GRM21B5C1H223JA01L ECJ 1V
40. ete serial The input and output S PDIF ports have optical and coaxial connectors The serial audio connectors use 1 x 2 100 mil spaced headers with pins for both signal and ground The LRCLK BCLK and SDATA paths are available for both the ADC and DAC on the and HDR2 connectors Each has a connection for MCLK each HDR MCLK interface has a switch to set the port as an input or output depending on the master or slave state of the AD1938 SWITCH AND JUMPER SETTINGS Clock and Control The AD1938 is designed to run in standalone mode at a sample rate fs of 48 kHz with an MCLK of 12 288 MHz 256 x fs In standalone slave mode both ADC and DAC ports must receive valid BCLK and LRCLK The AD1938 can be clocked from either the S PDIF receiver or the HDRI connector the ADC BCLK and LRCK port sources are selected with S2 Position 2 and Position 3 For the S PDIF master both switches should be off For HDRI S2 Position 3 should be on see the detail in Figure 15 and Figure 16 The DAC BCLK and LRCK port sources are selected with S2 Position 5 and Position 6 For the S PDIF master both switches should be off For HDRI S2 Position 6 should be on Note that HDR2 is not implemented in the CPLD routing code It is also possible to configure the AD1938 ADC BCLK and LRCK ports to run in standalone master mode moving J5 to SDA 1 as shown in Figure 3 changes the state of the AD1938 Setting S2 Position 2 and Position 5 to on select
41. he differential signal to drive the ADC with 2 V rms at the maximum level The DAC puts out a 0 8775 V rms single ended signal at 0 dBFS this signal is buffered and filtered before the OUT connectors There are test points that allow direct access to the ADC and DAC pins note that the ADC and DAC have a common mode voltage of 1 5 V dc These test points require proper care so that improper loading does not drag down the common mode voltage and the headroom and performance of the part do not suffer The ADC buffer circuit is designed with a switch S1 that allows the user to change the voltage reference for all of the amplifiers GND CM and FILTR can be selected as a reference it is advisable to shut down the power to the board before changing this switch The CM and FILTR lines are very sensitive and do not react well to a change in load while the AD1938 is active A series of jumpers allows the user to dc couple the buffer circuit to the ADC analog port when CM and FILTR are selected see Figure 14 C63 Hi gt C60 26 8 3 Parting 81 74 95 B ci TP25 C69 4 R86 9 RI J I 5 rag TP32 FILTER VREF SELECT 2 C77 53 et R C82 122 et wis En R107 R106 R93 er 79 08421 014 Figure 14 VREF Selection and DC Coupling Jumpers Digital Audio There are two types of digital interfacing S PDIF and discr
42. he three binding posts 12 V draws 250 mA and 12 V draws 100mA The on board regulators provide two 3 3 V rails one each for AVDD and DVDD for the AD1938 DVDD also supplies power for the active peripheral components on the board Jumpers are provided to allow access to the power connections of the AD1938 These are convenient points to insert a current measuring device The only compon ents on the AD1938 side of the jumper are the part itself and the local power supply decoupling The jumper blocks on the evaluation board are shown in Figure 5 Rev 0 Page 3 of 32 SELECTION 193X_MCLKI DISABLE JP18 m e 4 JP20MCLKO C147 XTAL 122 JP19 1938 n mds POWE R e B 5 lt lt DVDD JP5 JP6 JP7 08421 005 o 86 13 2212 cS Bi coool 154 R155 m 6 Fi 5 AD1938 P J igure ower Jumpers i oT m a 021 SETTING UP THE MASTER CLOCK MCLK ogee R169 X The evaluation board has a series of jumpers that give the user OSC DISABLE 51027 9 great flexibility in the MCLK clock source for the AD1938 b sez 022 me E MCLK can come from six different sources passive crystal bes R174 R175 active oscillator external clock in S PDIF receiver and two 8 ml EXT CLK IN C170 header connections Note that the complex programmable logic x HDR2 device CPLD on the board must have a valid clock source the m y freque
43. mlg 160 22 HF oom 193X_MCLKO 221 OSC DISABLE 159 Ri728 EXT Cir m me m 5 HDR2 mil E 3 Figure 11 LRCLK Is the Master Clock Using the PLL MCLKI Is Disabled and CPLD Is Slave to the MCLKO Port CONFIGURING THE PLL FILTER The PLL for the AD1938 can run from either MCLK or LRCLK according to its setting in the PLL and Clock Control 0 register Bits 6 5 The matching RC loop filter must be connected to LF Pin 47 using JP15 See Figure 12 and Figure 13 for the jumper positions PLL SELECT C120 BI R129 125 1 1 181 215 C131 MCLK LRCLK 08421 012 Figure 12 MCLK Loop Filter Selected PLL SELECT C120 x Riz 88 x C131 Figure 13 LRCLK Loop Filter Selected Normally the MCLK filter is the default selection it is also possible to use the register control window to program the PLL to run from the LRCLK In this case the jumper must be changed as shown in Figure 13 CONNECTING AUDIO CABLES Analog Audio The analog inputs and outputs use 3 5 mm TRS jacks they are configured in the standard configuration tip left ring right sleeve ground The analog inputs to IN1 and IN2 generate 0 dBFS from a 1 V rms analog signal The on board buffer circuit creates t
44. ncy is not critical These jumper blocks can assign the Figure 8 External Clock In as Master the AD1938 and CPLD as Slaves CPLD clock as well Most applications of the board use MCLK doc mand from either the S PDIF receiver or one of the header HDR DISABLE 5 2 7 18 JP20 MCLKO C147 inputs Figure 6 to Figure 9 show the on board active oscillator ge le 422 disabled so that it does not interfere with the selected clock The 1938 MCLKI e e m 2 mM z JP22 2 clock feed to the CPLD comes directly from the clock source B n C158 1222 Note that if the HDR connectors are to be driven with MCLK sm l l el a 193X MCLKO from a source on the evaluation board SVV2 and or SVV3 must EL asm e e be switched from the IN position to the OUT position l 23 rer OSC DISABLE 2278 z nrr28 DISABLE 022 di m el JP20 MCLKO C147 e R174 His ge XTAL J22 zao 1 q E 1938 2 27 2 2 mg 2 5169 im a EXT CLK IN sega ame mius Tun Zim d 8 r m alo Q e m 5 pm cole ejo 193X MCLKO 5215 Ee Figure 9 Active On Board Oscillator as Master the AD1938 and ET m e l CPLD as Slaves 423 OSC DISABLE pus s The MCLK configurations shown in Figure 10 and Figure 11 use ext G l m T me 5 2 the AD1938 M
45. pe com S4 STAND ALONE MODE22 MODE23 MODE24 pin 10 11 14 15 istype com S5 NODES I DSDATA I DSDATA2 I DSDATA3 I DSDATA4 node istype com I DBCLK I DLRCLK node istype com I ASDATA1 I ASDATA2 node istype com buffer I ABCLK I ALRCLK node istype com Qdivide node istype reg buffer Rev 0 Page 21 of 32 MACROS Switch 53 DIP POSITIONS 6 AND 7 ADC_HDR_NORMAL MODE22 amp MODE23 ADC HDR DATA2 DATA1 MODE22 amp MODE23 MODE22 6 MODE23 HDR AUX 1 22 6 MODE23 S PDIF_OUT_MUX EX Switch 54 MODE24 S4 position 0 DAC_RX_ALL MODE14 6 MODE13 6 12 amp 11 S4 position 1 DAC 1 14 8 MODE13 amp MODE12 amp MODE11 S4 position 2 DAC RX 2 14 8 MODE13 amp MODE12 amp MODE11 S4 position 3 DAC_RX_3 MODE14 amp MODE13 amp IMODE12 amp MODE11 S4 position 4 DAC RX 4 14 amp MODE13 8 MODE12 amp MODE11 S4 position 5 MODE14 6 MODE13 6 MODE12 6 MODE11 S4 position 6 NA2 MODE14 amp MODE13 amp IMODE12 6 MODE11 S4 position 7 DAC DATA ZERO MODE14 amp MODE13 amp IMODE12 amp MODE S4 position 8 DAC HDRI ALL MODE14 6
46. s the proper routing to both the S PDIF receiver and the HDRI connector Rev 0 Page 5 of 32 In this mode the AD1938 ADC port generates BCLK LRCLK when given a valid MCLK For full flexibility of the AD1938 the part can be put in SPI control mode and programmed with the Automated Register Window Builder application see Figure 4 for the appropriate jumper settings Changing the registers and setting the DIP switches allow many possible configurations In the various master and slave modes the AD1938 takes MCLK from a selected source and can be set to generate or receive either BCLK or LRCLK to or from either the ADC or the DAC port depending on the settings and requirements As an example to set the ADC port as master switch the ADC Control 2 register bits for BCLK and LRCLK to master and change 52 Position 2 and Position 5 to on In this mode the board is configured so that the ADC BCLK and LRCLK pins are the clock source for both the ADC destination and the DAC data source For the DAC port to be the master the DAC Control 1 register bits for BCLK and LRCLK must be changed to master and 52 Position 2 and Position 3 and 52 Position 5 and Position 6 must all be on On this evaluation board these settings allow the master port on the AD1938 to drive both the S PDIF and the HDR connections Many combinations of master and slave are possible see Figure 15 and Figure 16 for the correct settings S PDIF Audio The
47. settings shown in Figure 15 and Figure 16 show the details of clock routing and control for both the ADC and DAC ports The board is shipped with the S PDIF port selected as the default the hex switches are set to 0 and all DIP switches are set to off The AD1938 is shipped in standalone mode see Figure 2 the BCLK and LRCLK signals run from the S PDIF receiver to the ADC and DAC ports of the AD1938 In this default configuration the DAC audio path routes the S PDIF audio signal to all four stereo AD1938 DSDATA inputs simultaneously The rotary switch S4 allows the user to select individual stereo pairs for transmission of the analog signal Position 0 is the default Position 1 through Position 4 allow the S PDIF input signal to be assigned to Pair 1 to Pair 4 respectively Also in this default configuration the IN1 analog is routed through the AD1938 ADC ASDATAT path to the S PDIF output IN2 is selected by changing the S3 DIP switch Position 8 from 0 to 1 HDR Connectors Serial Audio Routing of serial audio to and from the HDRI connector is con trolled by DIP 53 Position 6 and Position 7 and Rotary S4 For the DAC audio signal path S4 Position 8 assigns the data signal coming into HDR1 DSDATA1 to all four DSDATA ports on the AD1938 54 Position 9 assigns the HDRI labeled ports to the associated port on the AD1938 Other Options It is possible to mute all data going to the DSDATA ports of the AD1938 by selecting S4
48. sistor 90 9 1 100 mW thick film Rohm MCRO3EZPFX90R9 0603 Rev 0 Page 27 of 32 Qty Designator Description Manufacturer Part Number 1 1 Crystal 12 288 MHz SMT 10 pF Abracon Corp ABM3B 12 288MHZ 10 1 U T 1 U15 Four ADC eight DAC with PLL 192 kHz 24 Analog Devices AD1938YSTZ bit CODEC 1 U23 Microprocessor voltage supervisor Analog Devices ADM811RARTZ REEL7 1 U1 Voltage regulator low dropout Analog Devices ADP3303ARZ 3 3 1 12 5 way binding post black uninsulated Deltron 552 0100 BLK base TH Components 1 J3 5 way binding post mini green Deltron 552 0400 GRN uninsulated base TH Components 1 J4 5 way binding post mini red uninsulated Deltron 552 0500 RED base TH Components 2 J22 J23 SMA receptacle straight PCB mount Amp RF Division 901 144 8RFX 1 U8 192 kHz digital audio receiver DGTL RCVR Cirrus Logic CS8416 CZZ 28 TSSOP 1 U13 192 kHz digital audio interface S PDIF Cirrus Logic CS8406 CZZ transmitter 2 02 D5 Passivated rectifier 1 50 V Micro Commercial DL4001 TP 1 S1 Switch slide DP3T PC MNT L 4 mm E Switch EG2305 1 SW1 DPDT slide switch vertical E Switch EG2207 6 L2 to L7 Chip ferrite bead 600 at 100 MHz TDK 216085601 1 11 Chip ferrite bead 600 at 100 MHz Steward HZ0805E601R 10 2 J1 J14 10 way shrouded polarized header 3M N2510 6002RB 4 J15 to J18 16 way unshrouded not populated 3M N A 1 J19 Connector header 0 100 dual STR 72 POS Sullins P
49. to DC couple 16 input buffers to AD193X ADC m Power Selection mE Kl HB 28 oxx OUT 2 38 y 829 e 00 GU GND Validity Bit 3 WS FE 27 A mar VREF SELECT Ore NHS 2 10 8151 5 1 9 2 2 u T a 2 a FDO ms 3 ALRCEK 20 m SEE gt ABCLK ine 5 NN 275977 Apar r mz ASDATAY TE 5 DLRCLK S DSDATAT 8126 OO sun 1 ident Tog Ka co 5 0 DSDATA2 TU 7 ps B DSDATA3 EE EE 55 050 4 BI zm 5 tus NC E 1 5 193X in INZR m 3 5 mec 5 ER f 21 1 ig 2 mr R ER D00 5 TPS 8177 MCLK 2 1128 csal 2 eo S em H r an 6 9 oz 2 OSC DISABLE s p 567 m OUTS E LU sie att m ES 4 2 q z 001381 B wre P60 s 575 GND ASDATAZ 5 Dies 5 100 sES DSDATAT GND 0188 Rez pee ANALOG DSDATAZ ovra 4 DSDATAS E DEVICES pom A b 8 0974 Eu aE pe 0 E m 457 q sr Sg E HDR1 hu REET 5 EVAL AD
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