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MSP430x4xx Family User's Guide (Rev. B)

1. REFON 2 5V INCH 0Ah e 4 VREF VREF on on E VREF VeREF 1 5V or 2 5V 1 Reference ec ADC12CTLx 0 3 AVss Internal nw ol AVSS ADC12SSEL a0 gt Oscillator ai d ADCi2CTLx4 6 ABCIeDIV ADC1208C al gt ADC12CLK Divide by ACLK a4 gt Analog 1 2 3 4 5 6 7 8 MCLK a5 Multiplexer Sample SMCLK gt 12 1 gt Hold a7 E S H Sampling ADC12SC Ly a9 44 SAMPCON 0 j Timer lt Timer QUT 210 lt SHI MSC Timer B OUT1 gt all 12 bit Conversion CTL v Ref X 0140 ADC12MEMO ADCi2MCTLO ogoh 0142h ADC12MEM1 ADC12MCTL1 081h ADC12MCTL 0144h ADC12MEM2 ADC12MCTL2 082h 0146h ADC12MEM3 ADC12MCTL3 083h 0148h ADC12MEM4 ADC12MCTL4 084h 014Ah ADC12MEM5 ADC12MCTL5 085h 014Ch ADC12MEM6 ADC12MCTL6 086h lt 014 ADC12MEM7 ADC12MCTL7 087h AVss 0150h ADC12MEM8 ADC12MCTL8 088h 0152h ADC12MEM9 ADC12MCTL9 089h 0154h ADC12MEM10 ADC12MCTL10 08Ah 0156h ADC12MEM11 ADC12MCTL11 08Bh 0158h ADC12MEM12 ADC12MCTL12 08Ch 015Ah ADC12MEM13 ADC12MCTL13 08Dh 015Ch ADC12MEM14 ADC12MCTL14 08Eh 015Eh ADC12MEM15 ADC12MCTL15 08Fh 16 x 12 bit 16 x 8 bi ADC Memory ADC Memory Control 17 2 The ADC12 can conv
2. 5 1 4 The Constant Generator Registers CG1 CG2 Commonly used constants are generated with the constant generator registers R2 and R3 without requiring an additional 16 bit word of program code The constant used for immediate values is defined by the addressing mode bits As as described in Table 5 3 See Section 5 3 for a description of the addressing mode bits As Table 5 3 Values of Constant Generators CG1 CG2 Register As Constant Remarks R2 00 Register mode R2 01 0 Absolute address mode R2 10 00004h 4 bit processing R2 11 00008h 8 bit processing R3 00 00000h 0 word processing R3 01 00001h 1 10 000021 2 bit processing R3 11 OFFFFh 1 word processing The major advantages of this type of constant generation are No special instructions required Reduced code memory requirements no additional word for the six most used constants Reduced instruction cycle time no code memory access to retrieve the constant The assembler uses the constant generator automatically if one of the six constants is used as a source operand in the immediate addressing mode The status register SR R2 used as a source or destination register can be used in the register mode only The remaining combinations of addressing mode bits are used to support absolute address modes and bit processing without any additional
3. n n 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 0 0 0 0 0 0 0 0 t Registers are reserved on devices with Timer B3 2 2 2 2 2 r 2 r 2 r 2 r 3 2 rw 2 rw 2 rw 2 rw 2 rw 2 rw 2 rw 2 rw 4 2 2 2 2 2 2 2 2 W W r rw r r r rw r r r rw r r r rw r r r rw r r r rw r r r rw r r r rw r r r rw r r r rw r r r rw r r 2 2 2 2 W W W 2 2 2 W W W 2 2 2 W W W 2 2 2 W W W 2 2 2 W W W 2 2 2 W W W 2 2 2 W W W 2 2 2 W W W W W W W W W W W W W W W W W W W W W 3 3 3 3 3 3 3 3 r r r r r r r 6 OUTe cove CCIFG6 W W 5 5 0 0 0 5 0 0 0 5 0 0 0 5 0 0 0 5 0 0 0 5 0 0 0 5 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 j 0 j 0 j 0 0 0 7 0 0 0 0 0 0 0 0 0 0 4 0 0 4 0 0 4 0 0 4 0 0 4 0 0 4 0 0 4 0 0 4 0 0 0 0 0 0 0 0 0 0 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 2 0 0 0 0 0 0 0 0 0 Peripheral File Map A 17 Timer B Registe
4. ee One MSP430 flash memory module will have in addition to its code segments extra flash memory called information memory Flash Memory C 3 Flash Memory Organization Figure 3 Flash Memory Module Example ONE module Flash Memory 4Kbyte 256Byte C4 FFFFh FOOOh 010FFh 256 Byte 01000h Flash Memory A module has several segments The information memory has two segments of 128 bytes each In the example in Figure C 4 the 4 module has eight segments of 512 bytes Segment0 to Segment7 and two 128 byte segments SegmentA and SegmentB SegmentO0 to Segment7 can be erased individually or as a group SegmentA and SegmentB can be erased individually or as a group with segments 0 to 7 The segment structure is described in the device s data sheet The information memory can be located directly below the main memory s address or at a different address but will be in the same module i M1 Note Flash memory modules may have different numbers of segments Segment are numbered from 0 up to n e g segment 0 to segment n LLLLLLSSS Flash Memory Data Structure and Opera
5. A A OEOO OA C 3 Flash Memory Control Registers Defining the correct control bits of three control registers enables write program erase or mass erase All three registers should be accessed using word instructions only The control registers are protected against false write or erase cycles via a key word Any violation of this keyword sets the KEYV bit and requests a nonmaskable interrupt NMI The keyword is different to the keyword used with the Watchdog Timer All control bits are reset during PUC PUC is activated after Vcc is applied a reset condition is applied to the RST NMI pin or watchdog or a flash operation was not performed normally C 3 1 Flash Memory Control Register FCTL1 Any write to control register FCTL1 during erase mass erase or write programming will end in an access violation with ACCVIFG 1 In an active segment write mode the control register can be written if wait mode is active WAIT 1 In an active block write mode and while WAIT 0 writing to control register FCTL1 will also end in an access violation with ACCVIFG 1 Read access is possible at any time without restrictions Any write to control register FCTL1 during erase mass erase or write programming will end in an access violation with ACCVIFG 1 In an active segment write mode the control register can be written if wait mode is active WAIT 1 In an active block write mode and while
6. ADC12SSEL B Oscillator ADC120N ADC12DIV T ADC120SC Vp VR ADC12CLK Divider by analog Sample 1 2 3 4 5 6 7 8 MCLK input and 12 bit A D converter core SHTO SMCLK signal Hold SHT1 gt ISSH pi Sampling ADC12SC q SAMPCON Lo Timer 4 O lt Timer A OUT1 O 4 SHi e O Timer_B OUTO Misc Timer_B OUT1 12 bit SAR Conversion CTL ENC SHS ADC12 17 25 Sampling Figure 17 19 Pulse Sample Mode Example Timing Timer B OUTO Additional edges are ignored until after conversion completes SAMPCON ADC12CLK GaERSRCETETQSTRBTRBUCIFSWARSRTIRY MOT tsample tconvert Next sync and sample 17 7 3 2 Extended Sample Mode In extended sample mode the input signal selected by the SHS bits is used to control the sampling SAMPCON signal directly The internal sampling timer is not used As shown in Figure 17 20 the sampling period is active while SAMPCON is high Hold mode is active when SAMPCON is low The conversion starts with the falling edge of SAMPCON after a synchronization time tsync The conversion takes 13 x ADC12CLK tconyer Figure 17 20 Conversion Timing for Extended Sample Mode Sample Input Signal SAMPCON ADC12CLK 17 26 7 t convert t sample tsync The extended sample mode allows total control of the sampling period and the start of a conversion The exte
7. 11 30 Timer Modes e 12 6 Compare Latch Operating Modes 12 21 State of OUTx at Next Rising Edge of Timer Clock 12 26 Timer B Registers sueseeeeseeeeseee e n 12 29 Mode Control a i six tic ee 12 30 Input Clock Divider Control Bits 00 cece eee eens 12 30 Clock Source Selection a a ene nett eens 12 30 Capture Compare Control Register Output Mode 12 34 Capture Compare Control Register Capture Mode 12 35 Vector Register TBIV lt 12 37 USART Interrupt Control and Enable Bits UART Mode 13 11 USARTO Control and Status Registers 13 15 USART1 Control and Status Registers 13 15 Interrupt Flag Set Conditions 0 cc cece eee eens 13 20 Receive Data Buffer Characters 13 22 Commonly Used Baud Rates Baud Rate Data and Errors 13 29 USART Interrupt Control and Enable Bits SPI Mode 14 9 USART Control and Status Registers 14 15 USART1 Control and Status Registers
8. 7 8 7 3 4 Disabling the FLL nee 7 9 f 3 b MCEK Stability AAG eque ei ette etui ves 7 9 7 4 Oscillator Fault Detection eens 7 10 9 10 11 Contents 7 5 FLL4 Operating Modes sees hn 7 10 7 5 1 Starting From Power Up Clear 7 10 7 5 2 Adjusting the FLL Frequency 7 10 7 5 8 Features for Low Power Applications 7 11 7 6 Buffered Clock Output 0 00 sehn 7 12 7 7 FLL Module Control Registers 00 0 cece ee eee eee 7 13 7 7 4 MCLK SMCLK Frequency Control saunaan aneen 7 13 7 7 2 Special Function Register Bits 7 16 Digital I O Configuration 00 cece IRI mh nn 8 1 8 1 1 2 p ct an c a dtr auis tr a cra Ira tuia e Rer 8 2 9 2 Ports PIPZ e ones du RUE 8 3 8 2 4 Port P1 Port P2 Control Registers 8 4 8 2 2 Port P1 Port P2 Schemat erra Rc p Rui 8 7 8 23 Port P1 P2 Interrupt Control Functions 8 8 8 3 Ports P3 P4 Pb PG xu oss MESA os teh Saas DURER IIS 8 9 8 3 1 Port P3 P6 Control Registers 8 9 8 3 2 Port P3 P6 Schematic eens
9. hn 44 Mri es ueni ud B 47 REG and BEG B Emulation 2 ud Hees B 48 Borrow Is Treated as a NOT B 52 Borrow Is Treated as a NOT e nh B 56 Borrow Is Treated as a NOT Carry 0 00 tenet eens B 57 Flash Memory Module s in MSP430 Devices C 2 xxii Chapter 1 Introduction This chapter outlines the features and capabilities of the Texas Instruments MSP430x4xx family of microcontrollers The MSP430 employs a von Neumann architecture therefore all memory and peripherals are in one address space The MSP430 devices constitute a family of ultralow power 16 bit RISC microcontrollers with an advanced architecture and extensive peripheral set The architecture uses advanced timing and design features as well as a highly orthogonal structure to deliver a processor that is both powerful and flexible The MSP430 consumes less than 300 uA in active mode operating at 1 MHz in a typical 3 V system and can wake up from a lt 2 standby mode to fully synchronized operation in less than 6 us These exceptionally low current requirements combined with the fast wake up time enable a user to build a system with minimum current consumption and maximum battery life Additionally the MSP430 family has an abundant mix of peripher
10. 14 15 Comparator A Control Registers eee eens 15 5 EGDM Selections 2 Len nde nds os bre bi or EE bal 16 11 LCDM Signal Outputs for Port Functions 0 00 cece cece eee 16 12 Reference Voltage Configurations 0 0 cece eee nee 17 5 Conversion Modes Summary 17 9 ADC12IV Interrupt Vector Values ccc cece tenet eee eee 17 38 Control Bits for Write or Erase Operation C 8 Conditions to Read Data From Flash Memory C 12 xix Examples 13 1 13 2 13 3 13 4 XX 4800 Baud cer ard aides aes nee Gees ebur X eee Ree a ea 13 6 19 200 ie eh ute ee 13 6 Error Example for 2400 Baud e ee ES 13 28 Synchronization Error 2400 Baud 13 31 Notes Cautions and Warnings Word Byte Operations seh rhe 4 7 Status Register Bits V N 4 and C ow n 5 5 Data Registers nex re crx eer eir ded ed ed dd s x Rara 5 7 Instruction Format Il Immediate Mode 5 15 Destination Address 0 ccc ee hh 5 16 Instructions and SUB 2 cece a n 5 17 Effective Load Capacitance
11. 3 7 3 8 MSP430 Interrupt Priority Scheme 3 8 3 4 Processing 3 11 3 5 Operating 3 20 3 6 Basic Hints for Low Power Applications 3 26 3 1 System Reset and Initialization 3 1 System Reset and Initialization 3 1 1 Introduction The MSP430 system reset circuitry shown in Figure 3 1 sources two internal reset signals power on reset POR and power up clear PUC Different events trigger these reset signals and different initial conditions exist depending on which signal was generated Figure 3 1 Brownout Reset SVS Reset and Power Up Clear Schematic P6 7 A7 SVSin Brownout SVS 1 Reset Supply Voltage POR ov ped RST MNI NMI WDTCTL 5 t X E PUC FLL TMSEL E Wonca gt Resetwd1 S S PUC EQut Resetwd2 R KEYV From Flash Module T From watchdog timer peripheral module MCLK A POR is a device reset It is only generated by the following events Powering up the device A low signal on the RST NMI pin when configured in the reset mode Asupply voltage drop below a reference voltage level if SVS is enabled A brownout A PUC is always generated when a POR is generated but a POR is not generated by a PUC The following events trigger a PUC A POR signal A Watchdog Timer expir
12. 5 2 5 1 3 The Status Register SR 5 4 5 1 4 The Constant Generator Registers CG1 and CG2 5 5 5 2 Addressing Modes enna 5 6 5 24 Register Mode nc ise etes nb ee 5 7 5 2 2 Indexed Mode a e eens 5 8 5 2 3 Symbolic Mode eens 5 9 5 2 4 Absolute 5 10 5 2 5 Jdndirect Mode tebe rin ieee ee ed Re ee pd 5 11 5 2 6 Indirect Autoincrement Mode 5 12 5 2 7 Immediate Mode cc eee cece teen nena 5 13 5 2 8 Clock Cycles Length of Instruction c ee eee eee 5 14 5 3 Instruction Set Overview 5 16 5 3 1 Double Operand Format 1 Instructions 5 17 5 3 2 Single Operand Format Il Instructions 5 18 5 3 8 Conditional Jumps 5 19 5 3 4 Short Form of Emulated Instructions 5 20 5 3 5 Miscellaneous ee hh hn 5 21 gA Instruction Map iE RE RARE BPEOISRQ 5 22 6 Hardware 6 1 6 14 Hardware Multiplie
13. 5 16 5 4xuinstructloniMapiter eee I Nee 5 22 5 1 CPU Registers 5 1 CPU Registers Sixteen 16 bit registers RO R1 and R4 to R15 are used for data and addresses and are implemented in the CPU They can address up to 64 Kbytes code memory RAM peripherals etc without any segmentation The complete CPU register set is described in Table 5 1 Registers RO R1 R2 and R3 have dedicated functions which are described in detail later Table 5 1 Register by Functions 5 1 1 Program counter PC Stack pointer SP Status register SR Constant generator CG1 Constant generator CG2 Working register R4 Working register R5 Working register R13 Working register R14 Working register R15 R15 The Program Counter PC The 16 bit program counter points to the next instruction to be executed Each instruction uses an even number of bytes two four or six and the program counter is incremented accordingly Instruction accesses are performed on word boundaries and the program counter is aligned to even addresses Figure 5 1 shows the program counter bits Figure 5 1 Program Counter 15 1 0 Program Counter Bits 15 to 1 E 5 1 2 The System Stack Pointer SP The system stack pointer must always be aligned to even addresses because the stack is accessed with word data during an interrupt request service The system SP is used by the CPU to store the return addresse
14. a EQU 002h b EQU 020h EQU 008h d EQU 004h e EQU 040h f EQU 001h g EQU 080h h EQU 010h The register content of Rx should be displayed The Table represents the on segments according to the content of Rx MOV B Table Rx Ry Load segment information into temporary memory MOV B Ry amp LCD Ry 0000 0000 gebh Note All bits of an LCD memory byte are written RRA Ry Ry 0000 0000 hcda RRA Ry Ry 0000 0000 00ge bhcd MOV B Ry amp LCDy 1 Note All bits of an LCD memory byte are written Table DB atbt ctd displays 0 DB atbt ctd displays 8 DB 16 20 Code Examples 16 3 3 Example Code for Three MUX 1 3 Bias LCD The 3MUX rate can easily support nine segments for each 4 lt digi t The nine segments of a digit are located in 1 1 2 display memory bytes rhe Th EQU EQU EQU EQU EQU EQU EQU EQU EQU LSDigit of register Rx should be displayed 0040 0400 0200 0010 0001 0002 0020 0100 0004 LSD The ODDDIG EVNDIG Table RLA OV Tabl OV LA LA LA S BIC BIS UJ UJ represents the igit of register of Rx register Ry is used for temporary memory Rx Table Rx Ry Ry amp LCDy Ry 07h amp LCDyy1 7 Ry amp LCDn 1 A Table Rx Ry Ry Ry i Ry
15. 16 17 Example With the Four MUX Mode 16 18 ADCT2 Schermalie dre dbrteRl sigle 17 2 ADC Core Input Multiplexer and Sample and Hold 17 4 Analog Multiplexer Channel eee en 17 6 Stopping Conversion With ENC Bit eee eee eee 17 10 Single Channel Single Conversion Mode 17 11 Example Conversion Memory Setup 17 12 ENC Does Not Effect Active Sequence 17 13 Sequence of Channels Mode 17 14 Sequence of Channels Mode Flow 17 15 Sequence of Channels Mode Example 17 16 Repeat Single Channel Mode 0 0 0 0 17 17 Repeat Sequence of Channels Mode 17 19 The Conversion Clock ADC12CLK nett eens 17 21 The Sample and Hold Function 17 22 Sample and Conversion Basic Signal Timing 17 23 Synchronized Sample and Conversion Signal With Enable Conversion 17 24 Conversion Timing Pulse Sample Mode 17 25 Pulse Samp
16. 13 3 Asynchronous Frame Format 13 4 Asynchronous Bit Format Example for n or n 1 Clock Periods 13 4 Typical Baud Rate Generation Other Than MSP430 13 5 MSP430 Baud Rate Generation Example for n or n 1 Clock Periods 13 6 Idle Line Multiprocessor II 13 7 USART Receiver Idle Detect 13 8 Double Buffered WUT and TX Shift Register 13 8 USART Transmitter Idle Generation 13 9 Address Bit Multiprocessor Format 13 10 State Diagram of Receiver Enable 13 11 State Diagram of Transmitter Enable 13 12 Receive Interrupt Operation 13 13 Transmit Interrupt Operation 13 14 USART Control Register UOCTL UTCTL 13 16 Transmitter Control Register UOTCTL U1TCTL 13 18 13 18 13 19 13 20 13 21 13 22 13 23 13 24 13 25 13 26 13 27 13 28 13 29 14 1 14 2 14 3 14 4 14 5 14 6 14 7 14 8 14 9 14 10 14 11 14 12 14 13 14 14 14 15 14 16 14 17 14
17. 2 R1 2 1 e b o 1 o Reference o Voltage pA 1 a CA1 0 li 2581 2 5 oV Vcc Signal 60 1 Wy Voltage CAON 3 2110 CARSEL o 0 5 2 1 0 25 x Vcc 3 Adding hysteresis can only be done if CAOUT is available externally Refer to the device s data sheet to determine if CAOUT is available at an external pin The hysteresis can be calculated as follows R2 Vinyst Rr Comparator_A 15 23 15 24 Chapter 16 Liquid Crystal Display Drive This chapter describes the MSP430x4xx liquid crystal display LCD driver The 41x devices can control 96 segments the 43x devices can control 128 or 160 segments varies with package option and the 44x devices can con trol 160 segments The multiplex rates are 1 2 3 and 4 All or most of the LCD signals are shared at the pin with digital functions Topic Page 16 1 LCD Drive Basics 79 16 2 16 25 1 ake E E 16 7 16 3 Gode Examples 16 19 16 1 LCD Drive Basics 16 1 LCD Drive Basics 16 2 LCDs must be driven with ac voltages DC voltage signals applied to LCD segments can harm and even destroy an LCD The LCD controller driver on the MSP430 devices simplifies the use of LCD displays by creating the ac voltage signals automatically Static LCDs have one pin for each segment and one pin for the gro
18. rh 5 22 Connection of the Hardware Multiplier Module to the Bus System 6 2 Block Diagram of the MSP430 16y16 Bit Hardware Multiplier 6 3 Registers of the Hardware Multiplier 6 6 Frequency Locked 7 3 Principle of LFXT1 Oscillator ett eens 7 4 Digitally Controlled Oscillator tenets 7 6 Fractional Tap Frequency 7 7 Modulator Hop Patterns E ete eens 7 8 ON ere ty ROT e 10 2 10 3 10 4 10 5 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 11 10 11 11 11 12 11 13 11 14 11 15 11 16 11 17 11 18 11 19 11 20 11 21 11 22 11 23 11 24 11 25 11 26 11 27 11 28 11 29 11 30 11 31 11 32 11 33 Contents Schematic of Clock Buffer es n 7 12 SGEQGTL Reglstet IDA 7 13 SCFIO and SCFI1 Registers eee 7 14 FLL Control Registers 0 and 1 eens 7 14 Port P 1 Port P2 Configuration 222 iu a tr ep REP waded Unido LORI 8 3 Schematic of One Bit in Port P1 2_ cee eee eens 8 7 Ports P3 P6 Configuration eee eens 8 9 Schematic Bits PA Kee ces Pad ee ea
19. Operation Emulation Description Status Bits Mode Bits Example Instruction Set Overview Enable general interrupts EINT 1 GIE or 0008h OR SR gt SR NOT src OR dst gt dst BIS 8 SR All interrupts are enabled The constant 08h and the status register SR are logically ORed The result is placed into the SR N Not affected 7 Not affected C Not affected V Not affected is set OscOff and CPUOff are not affected The general interrupt enable GIE bit in the status register is set Interrupt routine of ports P1 2 to P1 7 P1IN is the address of the register where all port bits are read P1IFG is the address of the register where all interrupt events are latched MaskOK PUSH B amp 1 BIC B SP amp P1IFG Reset only accepted flags EINT Preset port 0 interrupt flags stored on stack other interrupts are allowed BIT Mask SP JEQ MaskOK Flags are present identically to mask jump BIC Mask SP INCD SP Housekeeping inverse to PUSH instruction at the start of interrupt subroutine Corrects the stack pointer RETI Note Enable Interrupt The instruction following the enable interrupt instruction EINT is always executed even if an interrupt service request is pending when the interrupts are enable LLLLLL AIiISDUI
20. 4 9 S17 gt 18 5h 5b 092h 2 Digiti 518 4 19 5d 5c 0918 b h a f oo S19 4 20 Se 5g 20 gt 21 61 21 4 22 6h 6b Serial S22 gt 23 6d Conversion S23 4 6e 24 gt 5 7 7 25 4 gt 26 7h 7b 26 4 27 7d Sn 1 Sn 27 4 28 7e 79 S28 gt 29 amp S29 4 30 8h 8 S30 4 31 8d 8 931 4 32 8e 89 COMO 4 33 COMI 34 COMI COM2 NC coms NC 16 16 LCD Controller Driver 16 2 6 3 Example Using Three MUX 1 3 Bias Drive Mode The three MUX drive mode uses COMO COM1 and COMA In this mode bits 0 1 2 4 5 and 6 are used for segment information The other bits can be used like any other memory Figure 16 16 shows an example three MUX LCD pin out LCD to 430 connections and the resulting data mapping Note this is only an example Segment mapping in a user s application completely depends on the LCD pin out and on the 430 to LCD connections Figure 16 12 Example With the 3 MUX Mode LCD DIGIT10 DIGIT1 Pinout and Connections Display Memory Connections 430 Pins LCD Pinout 21110 21110 PIN comocom1com2 09Fh 9 d y f e n 30 eee 9 5 Si gt 2 id 19 v f o o 26 S in de m a o a 2 3E T m e
21. 15 2 15 2 Comparator A Description 15 3 15 3 Comparator A Control Registers 15 5 15 4 Comparator in Applications 15 9 15 1 Comparator A Overview 15 1 Comparator A Overview The primary function of the comparator module is to support precision A D slope conversion applications battery voltage supervision and monitoring of external analog signals The comparator is controlled via twelve control bits in registers CACTL1 and CACTL2 Figure 15 1 Schematic of Comparator A CAOUT to Internal Module CAOUT to External Pin Lp Set CAIFG Flag OV Voc iid CAEX O CAON T 9 ol cao Low Pass Filter CA0 96 1 7 0 Q Q 0 Ao olo o CAI 16 e Q caist i So ov zl OV P2CA1 T 2 0 us 000 05xVcoc L 1o 20 o 0 eo o 025xVcc VCAREF 3 gt OV OV 15 2 The input and output pins of Comparator_A are often multiplexed with other pin functions on the MSP430 Additionally the internal connections to Comparator_Acan differ among MSP430 devices The data sheet of a desired device should always be consulted to determine the specific connection implementations Comparator Description 15 2 Comparator A Description The comparator A peripheral module is comprised
22. 3 19 3 5 Operating Modes utres te pus ot ue be Debes Lope 3 20 3 5 1 Low Power Modes and 1 LPMO 1 3 24 3 5 2 Low Power Modes 2 and LPM2 and 3 25 3 5 8 Low Power Mode 4 LPM4 3 25 3 6 Basic Hints for Low Power Applications 3 26 Memory s ot lig 4 1 4 1 e 4 2 4 2 Datai n the Memory Iker usSRETReRDeI RILIBeCRR8SeRLiLgs 4 3 4 3 Internal ROM Organization 4 4 4 3 1 Processing of Memory Tables 4 4 4 3 2 Computed Branches and Calls 4 5 4 4 and Peripheral Organization 4 5 Contents 4 4 1 Random Access Memory 4 5 4 4 2 Peripheral Modules Address Allocation 4 7 4 4 3 Peripheral Modules Special Function Registers SFRs 4 9 5 T16 BIE CPU sedet EE eR e e ges 5 1 GPU Registers cx ee EUR e eu EEE ek AIV ERE Mace hie UR Mee nee eu da dra 5 2 5 1 1 The Program Counter PC 3 5 2 5 1 2 The System Stack Pointer
23. INSTRUMENTS MSP430x4xx Family User s Guide 2002 Mixed Signal Products SLAU056B IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed Tl assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right
24. 6 4 Hardware Multiplier Registers 6 6 The DCO Range Control Bits 8 3 e 7 9 8 1 8 2 8 3 9 1 10 1 10 2 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 12 1 12 2 12 3 12 4 12 5 12 6 12 7 12 8 12 9 12 10 13 1 13 2 13 3 13 4 13 5 13 6 14 1 14 2 14 3 15 1 16 1 16 2 17 1 17 2 17 3 C 1 2 Contents Port PT Beglsters en EROR Der Dese our etre weed Dulce eo edens 8 4 Port P2 Registers EORR Re Res 8 4 Port P3 P6 Registers ic cocer rer rege rait eta etie 8 10 WBTGN T TapS o9 Ld i LA Kp EL aah Ec 9 3 Basic Timer1 Registers 20 n 10 3 2 Input Frequency Sources 10 4 imer Modes LIN VMULIi 11 3 State of OUTx at Next Rising Edge of Timer Clock 11 20 Timer A Registers oi ce toe pene seine dene PERS pa ete ere oot weed Nd p n Nd s 11 22 shore 11 23 Input Clock Divider Control Bits eee eee ees 11 24 Clock Source Selection e eee eens 11 24 Capture Compare Control Register Output Mode 11 27 Capture Compare Control Register Capture Mode 11 27 Vector Register Description
25. 2 0 0 cece E EEES EES IE EES m nh 11 9 11 4 Capture Compare Blocks cece eee eee 11 12 11 4 1 Capture Compare Block Capture Mode 11 13 11 4 2 Capture Compare Block Compare Mode 11 17 11 4 3 Output Unit Output Modes 11 18 11 4 4 Output Control Block aeann ccc esee 11 19 11 4 5 Output Examples 0 00 00 cece ete een 11 20 11 5 tT ei nied eed Ga DR e 11 22 11 5 1 Timer A Control Register TACTL 11 23 11 5 2 Timer A Register TAR teens 11 25 vii Contents 11 5 3 Capture Compare Control Register CCTLx 11 25 11 5 4 Timer A Interrupt Vector Register 11 28 11 6 Omer AVARET e a ueber Ee Rie eee 11 32 12 Timer EL 12 1 12 4 Sea ade aee sues aa 12 2 12 1 1 Similarities and Differences From Timer 12 2 12 2 Timer B Operation eh 12 5 2 241 Dmer Eengtlr wis uxo sk eres oar as e ar 12 5 12 2 2 Timer Mode Control 0 00 c cece 12 5 12 2 3 Clock Source Select and 12 6 12 2 4 Starting the Timer 2 0 cece teenies 12 7 1
26. 5 4 Values of Constant Generators CG1 2 8 5 5 Source Destination Operand Addressing Modes 5 6 Register Mode Description een eens 5 7 Indexed Mode 5 8 Symbolic Mode Description III n 5 9 Absolute Mode Description RII 5 10 Indirect Mode Description 5 11 Indirect Autoincrement Mode Description 5 12 Immediate Mode Description 5 13 Instruction Format and Addressing 5 14 Execution Cycles for Double Operand Instructions 5 14 Instruction Format Il and Addressing Modes 5 15 Execution Cycles for Single Operand Instructions 5 15 Miscellaneous Instructions or Operations 5 16 Double Operand Instruction Format Results 5 17 Single Operand Instruction Format Results 5 18 Conditional Jump Instructions eee 5 19 Emulated Instructions 5 20 Sum Extension Register Contents
27. Ifx lt 15thenx x 1 Ifx lt 15thenx x 1 else x 0 else x 0 d Y lt 12 x ADC12CLK MSC 1 Convert Use SHP 1 12 x ADC12CLK and EOS x 0 1 ADC12CLK Conversion Completed Result Stored Into ADC12MEMXx ADC12IFG x Is Set X pointer to conversion memory register ADC12MEMO ADC12MEM 15 and conversion memory control register ADC12MCTLO ADC12MCTL15 17 14 Conversion Modes An example showing a sequence of conversions is shown and flow charted in Figures 17 9 and 17 10 The example shows the sequence a0 a5 a0 a0 uses ADC12MEM6 for storing the first conversion results The set up of each conversion in the sequence is O O O O O L a0 using reference voltages VR and Vp_ AVss a5 using reference voltages Vn at and Vp AVss a7 using reference voltages Vp at VngE and Vp Vengr VREF a0 using reference voltages Vg AVcc and Vp AVss a0 using reference voltages Vg AVcc and Vp AVss using reference voltages Vn AVcc and Vp Vengr VREF Figure 17 9 Sequence of Channels Mode Flow Define basic conversion conditions via control registers ADC12CTLO 1 x26 CStartAdd 6 Define reference and channel in control registers ADC12MCTL6x ADC12MCTL6 Oh ADC12MCTL7 015h ADC12MCTL8 057h ADC12MCTL9 Oh ADC12MCTL10 Oh ADC12MCTL11 0C3h P lt Samp
28. 2 bit switches off the XT2 oscillator only if it is unused by MCLK SELM lt gt 2 or CPUOff 1 and SMCLK SELS 0 or SMCLKOFF 1 Tl The XT2 oscillator is implemented in the MSP430x43x and MSP430x44x devices The LFxT1CLK signal is used in place of the XT2CLK signal on MSP430x41 x devices doo pexoo 1 KouenbaJ4 1 LFXT1 Oscillator 7 2 LFXT1 Oscillator The LFXT1 oscillator starts operating on a valid PUC condition A valid PUC condition resets the OscOff bit in the status register which enables the low frequency oscillator of LFXT1 Software can disable LFXT1 by setting OscOff if this signal does not source SMCLK or MCLK The design of the LFXT1 oscillator shown in Figure 7 2 supports the low current consumption feature and the use of a 32 768 Hz watch crystal when in LF mode XTS_FLL 0 A watch crystal connects to the clock module via two terminals without any other external components Components necessary to stabilize the clock operation have been integrated into the MSP430 The design of the LFXT1 oscillator also supports high speed crystals or resonators when in HF mode XTS_FLL 1 The crystal or resonator connects to the terminals and normally requires additional external capacitors on both terminals These capacitors minus the internal ones should be sized according to crystal or resonator specifications Waa a a aS Note Effective Load Capacitance Crystal manufactures typically define the effec
29. OMx2 OMx1 OMx0 The timer is Incremented with the rising edge of the timer clock MM CAE UNE SE Timer W m V V V V V V V mp A X KX 1 A TAR n EQUx CCRx n EQUO TAR 0 or TAR CCRO EQUO Delayed Used in Up Mode Only EQUO delayed is used in up mode not EQUO EQUO is active high when TAR EQUO delayed is active high when TAR 0 Timer_A 11 19 Timer Modes Table 11 2 State of OUTx at Next Rising Edge of Timer Clock Mode EQUO EQUx D 0 X X X OUTx bit 1 X 0 OUTx no change X 1 1 set 2 0 0 OUTx no change 0 1 OUTx toggle 1 0 0 reset 1 1 1 set 3 0 0 OUTx no change 0 1 1 set 1 0 0 reset 1 1 1 set 4 X 0 OUTx no change x 1 OUTx toggle 5 0 OUTx no change x 1 0 reset 6 0 0 OUTx no change 0 1 OUTx toggle 1 0 1 set 1 1 0 reset 7 0 0 OUTx no change 0 1 0 reset 1 0 1 set 1 1 0 reset 11 4 5 Output Examples The following are some examples of possible output signals using the various timer and output modes 11 4 5 1 Output Examples Timer in Up Mode The OUTx signal is changed when the timer counts up to the CCRx value and rolls CCRO to zero depending on the output mode as shown in Figure 11 24 11 20 Figure 11 24 Output Examples Timer Up Mode Timer Modes OFFFFh Example EQU1 Used C
30. expanded into the RAM location TIMEXT MSBs TIMOVH Vector 14 TIMOV Flag INC TIMEX Handle Timer Overflow RETI TIMMOD2 Vector 4 Module 2 ADD NN amp TBCCR2 Add time difference ee Task starts here RETI Back to main program TIMMOD1 Vector 2 Module 1 ADD amp TBCCR1 Add time difference SIS Task starts here RETI Back to main program The Module 3 handler shows a way to look if any other interrupt is pending 5 cycles have to be spent but 9 cycles may be saved if another interrupt is pending TIMMOD3 Vector 6 Module 3 ADD PP amp TBCCR3 Add time difference Task starts here JMP TIM HND Look for pending interrupts Timer B Registers 12 6 4 4 Timer Interrupt Vector Register Software Example Timer B3 The following software example describes the use of vector word TBIV of Timer and the handling overhead The numbers at the right margin show the necessary cycles for every instruction The example is written for continuous mode the time difference to the next interrupt is added to the corresponding compare register Software example for the interrupt part Cycles Interrupt handler for Capture Compare Module 0 The interrupt flag CCIFGO is reset automatically TIMMODO MS Start of handler Interrupt latency 6 RETI 5 Interrupt handler for Capture Compare Modules 1 to 6 The interrupt flags CCIFGx and TBIFG are reset by hardware Only th
31. 71 TPSSEL1 TPSSELO Timer Clock Data 16 Bit Timer 4 TACLK o o a ee 9 Input c Timer Mode SMCLK 3 Divider RC Control EquO INCLK os J 4 gt ID Camy Zero Set_TAIFG L Timer Bus J EE E ee ee ee ponte eee ee uem ee See ice benc d SS SS SS Sa Se SS SS SS SS SS SS SS SSS Se SS eS SS SS eS SS SS Capture Compare Register CCRO TERN A OM02 OMO0 CCIOA SET e CCIOB Capture SMS 1 Output Unit 0 GND Vec 9 eg EQUO CCI CCMO0 a a SS A QA J 0 Capture Compare Register CCIS11 CCIS10 A 19 OM12 OM11 10 0 zi Capture Compare ccna 0 0 0 Caire Register CCR1 8 CCHB 9 Capture uti GND Mode Output Unit 1 NE EQU1 CCI CCM11 CCM10 poli mett MICAT es Se ee eee 2 1 POR Capture Compare Register CCR2 CCIS21 CCIS20 A 18 22 21 20 0 Capture Compare 2 0 0 Capture Register CCR2 es CCI2B Capture ut GND Mode Output Unit 2 EE EQU2 CCM21 20 ERR dc P Mr qq es J Timer A Operation 11 2 Timer A Operation The 16 bit timer has 4 modes of operation selectable with the and MC1 bits in the TACTL register The timer increments or decrements depending on mode of operation with each rising e
32. CAPx Capture Mode CCMx1 0 0 Disabled 0 1 Positive Edge 1 0 Negative Edge CAPx 1 1 Both Edges EQUx 0 1 Set CCIFGx EN Y SCCIx A CCIx 11 12 Timer Modes 11 4 1 Capture Compare Block Capture Mode The capture mode is selected if the mode bit CAPx located in control word CCTLx is set The capture mode is used to fix time events It can be used for speed computations or time measurements The timer value is copied into the capture register CCRx with the selected edge positive negative or both of the input signal Captures may also be initiated by software as described in section 11 4 1 1 If a capture is performed The interrupt flag CCIFGx located in control word CCTLx is set An interrupt is requested if both interrupt enable bits CCIEx and are set The input signal to the capture compare block is selected using control bits CCISx1 and CCISxO0 as shown in Figure 11 18 The input signal can be read at any time by the software by reading bit CCIx The input signal may also be latched with compare signal EQUx see SCCIx bit below when in compare mode This feature was designed specifically to support implementing serial communications with Timer A See section 11 6 Timer UART for more details on using Timer A as a UART Figure 11 18 Capture Logic Input Signal CCISx1 CCISxO CCIxA 00 0 o GND
33. ERE E NOU MMC RENE MD NECEM ME MEN 4 1 Capture Compare Register TBCCRO 501 00 15 OM02 OM01 OMOO g Capture Compare COIDA Register TBCCRO E CCIOB 9 Capture 0 uto GND SE Output Unit 0 Voc 9 Compare Latch Comparator 0 EQUO EQUO en EL 4 a a ae me ee ae te oe tem es ae a Peel ig a ars q Capture Compare Register 1 CCIS11 CCIS10 A 15 0 12 11 10 0 Capture Compare CCHA 9 97 Register TBCCR1 o M GND 3 TBCL1 VEG 56 Comparator Latch 1 CCM11 CCM10 Comparator 1 EQU1 EQUO a ee EENE 4 Module 2 Module 3 Module 4 Module 5 a ae a i he a E 1 Capture Compare Register TBCCR6 CCIS61 CCIS60 15 0 OM62 OM61 OM60 0 CCI6A Capture Register TBCCR6 6 9 Capture 0 Gulgut Unit Qut6 ON 55S 2 TBCL6 Voc 9 Compare Latch CCI6 CCM61 60 EQUe EQUO J 12 4 Timer B Operation 12 2 Timer B Operation The 16 bit timer has four modes of operation selectable with the and MC1 bits in the TBCTL register and four selectable lengths also configured in the TBCTL register The
34. User s Software User s Software User s Software Oscillator Fault Flash Access External NMI Handler Violation Handler Handler Optional Set OFIE Example 1 ACCVIE Within One BIS NMIIE OFIE ACCVIE amp IE1 Instruction Example 2 BIS Mask amp IE1 Mask enables only interrupt sources RETI End of NMI Interrupt Handler The NMI handlertakes care of all sources requesting a nonmaskable interrupt The NMI interrupt is a multiple source interrupt per MSP430 definition The hardware resets the interrupt enable flags the external nonmaskable interrupt enable NMIIE the oscillator fault interrupt enable OFIE and the flash memory access violation interrupt enable The individual software handlers reset the interrupt flags and reenables the interrupt enable bits according to the application needs After all software is processed the interrupt enable bits have to be set if another NMI event is to be accepted Setting the interrupt enable bits should be the last instruction before the return from interrupt instruction RETI If this rule is violated the stack can grow out of control while other NMI requests are already pending Setting the interrupt enable bits can be accomplished by using a bit set instruction BIS using immediate data or a mask The mask data can be modified anywhere via software for example in RAM this constitutes the nonmaskable interrupt processing C 4 2 Protecting One
35. WDTHOLD 0 or left disabled or be restored to the previous level Flash Memory C 21 Flash Memory Access JTAG and Software C 5 Flash Memory Access via JTAG and Software C 5 1 Flash Memory Protection Flash memory access via the serial test and programming interface JTAG can be inhibited when the security fuse is activated The security fuse is activated via serial instructions shifted into the JTAG Activating the fuse is not reversible and any access to the internal system is disrupted The bypass function described in the IEEE1149 1 standard is active C 5 2 Program Flash Memory Module via Serial Data Link Using JTAG Feature The hardware interconnection to the JTAG pins is done via four separate pins plus the ground or Vss reference level The JTAG pins are TMS TDI and TDO TDI Figure C 11 Signal Connections to MSP430 JTAG Pins Level Shifter VCC TMS gt TMS TCK gt tle TCK EN1 TDI gt TDI TDO TDO TDI 1 SN74AHC244 MSP430Fxxx TCLK gt XOUT TCLK EN2 Test VPP gt To tl Vcc DVcc gt Vss DVss C 5 3 Programming a Flash Memory Module via Controller Software No special external hardware is required to program a flash memory module The power supply at Vcc should supply sufficient current during write program and erase modes Please separate the device s data sheet for flash write end erase current The soft
36. Y from Reference ADC120N ADC12CLK 12 bit A D converter core Analog Multiplexer 12 1 SAMPCON to ADC12MEMx Itis important to note that the 3 LSBs of the conversion are resolved resistively Therefore when the 3 LSBs are being resolved during a conversion approximately 200 will be required from the reference The user should keep this in mind when choosing and decoupling an external reference Refer to the device data sheet for more details on ADC12 specifications 17 2 2 Reference ADC12 Description and Operation Caution ADC12 Turnon Time When the ADC12 is turned on with the ADC120ON bit the turnon time noted in the data sheet 12 must be observed before conversion is started Otherwise the results will be false The ADC12 A D converter contains a built in reference with two selectable reference voltage levels 1 5 V and 2 5 V Either of these reference voltages may be applied to Vp of the A D core and also may be available externally on pin check device data sheet for availability of Vp gp pin Additionally an external reference may be supplied for Vp through pin Venger check data sheet for availability of Vengr pin The reference voltage level for Vp can be selected to be AVss or may be supplied externally through the Vngr Vepmgr pin check device data sheet for Vngr Vengr pin If the VaEgr Vengr pin is not available then Vp is con
37. cee 7 4 Writing to Read Only Registers P2IN ssssssssssssee te eens 8 4 Port P1 Port P2 Interrupt Sensitivity eee eens 8 6 Function Select With PISEL P2SEL 6 cette teen eee eae 8 7 Writing to Read Only Register 0 ccc cect eens 8 10 Function Select With PnSEL Registers 0c cece eee ee nee eens 8 11 Watchdog Timer Changing the Time Interval 9 6 Capture With Timer Halted m 11 15 Changing Timer A Control Bits essen 11 24 Modifying Timer A Register TAR m 11 25 Simultaneous Capture and Capture Mode Selection 11 28 Writing to Read Only Register 11 30 Capture With Timer Halted ete mn 12 18 Changing Timer B Control Bits 12 32 Modifying Timer B Register OEA EERE 12 32 Simultaneous Capture and Capture Mode Selection 12 35 Writing to Read Only Register TBIV nnn 12 37 URXE Re Enabled UART Mode 0 00 cece cette eee eee eens 13 11 Writing to UTXBUF UART Mode 00 cece sss 13 12 Write to UTXBUF Reset of Transmitter UART Mode 13 12
38. 12 12 Timer Up Down Direction eh 12 13 Up Down Mode Flag Setting 12 13 Altering TBCLO Timer in Up Down Mode 12 14 Capture Compare Blocks cece eee nnn 12 15 Capture Logic Input Signal 00 eee cnet 12 16 Capture Signals Ces i en nte di wu nia 12 16 Gapt re Cycle MEN RUP eee te ee 12 17 Software Capture Example eee eee eee n 12 19 Output Unites i eas 12 23 Output Control Block i necem EL nere E 12 25 Output Examples Timer in Up Mode 12 27 Output Examples Timer in Continuous Mode 12 27 Output Examples Timer in Up Down Mode l 12 28 Timer B Control Register TBCTL cece eee eens 12 29 TBR Register 12 32 Capture Compare Control Register TBCCTLX 12 32 Capture Compare Interrupt Flag 12 35 Schematic of Capture Compare Interrupt Vector Word 12 36 Vector Word Register cece eee eee n 12 36 Block Diagram of USART mn 123 2 Block Diagram of USART UART Mode
39. o HU ooo Input SHI tssync 1 n Pug Au Sample and conversions Trigger signal enabled 17 7 3 Sampling Modes The sampling circuitry has two modes of operation pulse sampling mode and extended sampling mode In pulse sampling mode the sample signal input selected by the SHS bits in ADC12CTL1 is used to trigger the internal sampling timer and the actual sample timing signal SAMPCON is then generated by the sampling timer and is an integer multiple of the ADC12CLK signal In extended sampling mode the sampling signal input bypasses the sample timer and is used to source SAMPCON directly therefore completely controlling the sample timing asynchronously to ADC12CLK Note that 13 ADC12CLK cycles are still required to complete one conversion 17 7 3 1 Pulse Sample Mode 17 24 In the pulse sample mode the sample input signal selected by the SHS bits triggers the sampling timer with its rising edge The sampling timer then generates the sample timing The sampling time is programmable by the SHTO or SHT1 bits located in ADC12CTLO When conversion memory registers ADC12MEMO to ADC12MEM7 are selected to store the conversion result s the SHTO bits are used to program the sampling time When conversion memory registers ADC12MEM8 to ADC12MEM15 are selected for the conversion data the SHT1 bits are used to program the sampling timing Therefore it is possible to program two
40. 4 Single channel NL 2 3 4 Sequence of SAMPCON 4 Channel 5 sic sic sic sic 1 2 3 4 2 3 4 Sequence of SAMPCON 1 Channel sic sic 5 5 sic sic SiC Sic sic Conversion Period Sample Period Figure 17 24 Use of MSC Bit With Repeated Modes ADC12CLK SHTO SHT1 SHP tT 1 Sampling Q4 SAMPCON 0 4 Timer 5 0 SHI F E E LN A X A KA a Ka Repeat Single SAMPCON Ay Channel S C Repeat Single SAMPCON 4 mI Channel X sic sic se sic sic sc sic SiG Sic PR 2 3 V1 2 V 1 Repeat Sequence SAMPCON 4 4 4 4 of Channel Sic Sic Sic sic 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 epeat Sequenci 1 L of Channels SIC sic S C 5 se sce SC se SC se sc sic sic sic sic sic 17 28 S C Conversion Period Sample Period MSC 0 MSC 1 MSC 0 MSC 1 MSC 0 MSC 1 MSC 0 MSC 1 Sampling 17 7 5 Sample Timing Considerations The A D converter uses the charge redistribution method Thus when the inputs are internally switched to sample the input analog signal the switching action causes displacement currents to flow into and out of the analog inputs These current spikes or transients occur atthe leading and falling edges of the sample pulse and usually decay and settle before causing any problems because typically the external time constant is less than that
41. Right Shift 51 Destination Operand Byte Swap B 58 Destination Operand Sign Extension B 59 Interconnection of Flash Memory Module s C 2 Flash Memory Module1 Disabled Module2 Can Execute Code Simultaneously C 3 Flash Memory Module Example Ih C 4 in Flash Memory Module 4 Example Flash Memory Module Block Diagram C 6 Block Diagram of the Timing Generator in the Flash Memory Module C 7 Basic Flash EEPROM Module Timing During the Erase Cycle C 9 Basic Flash Memory Module Timing During Write Single Byte or Word Cycle C 11 Basic Flash Memory Module Timing During a Block Write Cycle C 11 Access Violation Non Maskable Interrupt Scheme in Flash Memory Module C 19 Signal Connections to MSP430 JTAG Pins C 22 xvii Tables RON s RWONMHWNHHHHHHOOAONDA V Ny d dead hcl docu dio do th C1 C1 O1 D N xviii Interrupt Control
42. The Sref bits select one of six reference voltage combinations used for conversion The conversion is done between the selected voltage range Vp and Vg 0 Vn AVcc and Vn AVss 1 Vn VREF and VR AVss 2 3 Vn VeREF and VR AVss 4 VR and Vp Vengr 5 VR VREF and Vp Vngr Vengr 6 7 VR Verner and Vp Vngr The end of sequence bit when set indicates the last conversion in a sequence of conversions Note A sequence will roll over from ADC12MEM15 ADC12MCTL15 to ADC12MEMO ADC12MCTLO if the EOS bit ADC12MCTL 15 is not set Note If none of the EOS bits is set and a sequence of channels CONSEQ 1 3 is selected resetting the ENC bit will not stop the sequence To stop the sequence first select a single channel mode CONSEQ 0 2 and then reset ENC See also the ENC bit description ADC12 Control Registers 17 8 4 ADC12 Interrupt Flags ADC12IFG x and Interrupt Enable Registers ADC12IEN x There are 16 ADC12IFG x interrupt flags 16 ADC12IE x interrupt enable bits and one interrupt vector word The interrupt flags and enable bits are associated with the 16 ADC12MEMX registers All interrupt flags and interrupt enable bits are reset during POR ADC12IFG 0184h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12IFG x bits 0 15 The ADC12IFG x interrupt flag is set if a conversi
43. n i n 1 2 3 n 2 x n 2 n 2 x 1 n 1 2 Bae POTE urxp Data Bit Period or n 1 BRCLK Periods URXD L Data Period n or n 1 BRCLK Periods _ 13 4 Asynchronous Operation 13 3 2 Baud Rate Generation in Asynchronous Communication Format Baud rate generation in the MSP430 differs from other standard serial communication interface implementations 13 3 2 1 Typical Baud Rate Generation Typical baud rate generation uses a prescaler from any clock source and a fixed second clock divider that is usually divide by 16 Figure 13 5 shows typical baud rate generation Figure 13 5 Typical Baud Rate Generation Other Than MSP430 0 7 0 7 UxBRO UxBR1 8 8 15 16 Bit P ler Divider Select Clock Source Clock1 Clockn BRSCLK Start H 1 2 83 4 5 6 7 8 9 1011 12 13 14 15 16 1 BRSCLK L n Take Majority Vote of Receive Bit BITCLK L4 Baud rate BRCLK n x 16 Typical baud rate schemes often require specific crystal frequencies or cannot generate some baud rates required by some applications For example division factors of 18 are not possible nor are noninteger factors such as 13 67 13 3 2 2 MSP430 Baud Rate Generation The MSP430 baud rate generator uses one prescaler divider and a modulator as shown in Figure 13 6 This combination works with crystals whose frequencies are
44. ne cena E 2 19 20 Contents A 2 Special Function Register of MSP430x4xx Family Byte Access A 3 Digital Byte Access hh A 3 A 4 Basic Timer1 Registers Byte Access A 5 A 5 FLL Registers Byte A 5 A 6 SVS Register Byte Access hn A 5 A 7 A Registers Byte Access A 5 8 USARTO USART1 UART Mode Sync 0 Byte Access A 6 A 9 USARTO USART1 SPI Mode Sync 1 Byte Access A 7 A 10 ADC12 Registers Byte Word A 8 A 11 LCD Registers Byte Access 00 cece eet eee eae A 11 12 Watchdog Timer Word Access 0c cece tent n A 12 A 13 Flash Control Registers Word Access A 12 A 14 Hardware Multiplier Word Access 006 cece eee teen t eee eae A 13 A 15 Timer A Registers Word Access t et seh A 14 16 Timer B Registers Word Access 0 0 0 A 16 Instruction Set Description 000s c eee eee nnn nnn B 1 B 1 Instruction Set Overview sss ne B 2 B 1 1 Instruction Formats eens 4 B 1 2 Conditional and Unconditional Jumps
45. 0 ADC12BUSY bito The ADC12BUSY bit indicates an active sample or conversion operation It is used specifically when the conversion mode is single channel single conversion because if the ENC bit is reset in this mode the conversion stops immediately and the results are invalid Therefore the ADC12BUSY bit should be tested to verify that it is 0 before resetting the ENC bit when in single channel single conversion mode The busy bit is not useful in all other operating modes because resetting the ENC bit does not immediately affect any other mode 0 No operation is active 1 Asample period conversion or conversion sequence is active CONSEQ bits The CONSEQ bits select the conversion mode Repeat mode is on if the 1 2 CONSEQ 1 is set 0 Single channel single conversion mode One single channel is converted once 1 Sequence of channels mode A sequence of conversions is executed once 2 Repeat single channel mode Conversions on a single channel are repeated until CONSEQ is set to O or 1 3 Repeat sequence of channels A sequence of conversions is repeated until CONSEQ is set to 0 or 1 NOTE See also section Conversion Modes ADC12 17 33 ADC12 Control Registers ADC12SSEL ADC12DIV ISSH SHP SHS CStartAdd 17 34 bits 3 4 bits bit8 bit9 bits 10 11 bits 12 15 Select the clock source for the converter core 0 ADC12 internal oscillator ADC120SC 1 ACLK 2 MCLK 3 SMCLK Select
46. 5 0 5 R5 PUSH R5 R5x0 5 TOS RRA SP TOS x 0 5 0 5 x R5 x 0 5 0 25 x R5 TOS ADD SP R5 R5x0 5 R5 0 25 0 75 x R5 R5 The low byte of R5 is shifted right one position The MSB retains the old value operates equal to an arithmetic division by 2 RRA B R5 R5 2 R5 operation is on low byte only High byte of R5 is reset The value in R5 low byte only is multiplied by 0 75 0 5 0 25 PUSH B R5 hold low byte of R5 temporarily using stack RRA B R5 R5x0 5 R5 ADD B SP R5 R5x05 R5 1 5xR5 R5 RRA B R5 1 5 x R5 x 0 5 0 75 x R5 R5 RRA B R5 R5x0 5 R5 PUSH B R5 R5x0 5 TOS RRA B SP TOS x 0 5 0 5 x R5 x 0 5 0 25 x R5 gt TOS ADD B SP R5 5 0 5 5 0 25 0 75 x R5 R5 RRC W RRC B Syntax Operation Description Instruction Set Overview Rotate right through carry Rotate right through carry RRC dst or RRC W dst RRC dst C gt MSB 1 LSB 1 gt LSB gt C The destination operand is shifted right one position as shown in Figure 6 The carry bit C is shifted into the MSB the LSB is shifted into the carry bit C Figure B 9 Destination Operand Carry Right Shift Status Bits Mode Bits Example Example Word 15 0 ue Byte 7 0 N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Loaded from the LSB V Setif initial destination is positiv
47. CAON e g 0 CAF Capture CAO Input of 1_ 0 2 gt o Timer A 09 p P2CA1 Vref The Voffset in this configuration is in series with as shown in Figure 15 19 Vref Voffset Figure 15 19 Offset Voltage of the Comparator CAEX 0 oV Vcc 60 1 e g Capture Input of 5 gt Timer NN VCAO0 in offset Next execute a conversion with CAEX 1 VcAo is applied to the terminal of the comparator and Vier is applied to the terminal of the comparator as shown in Figure 15 20 15 20 Comparator A Applications Figure 15 20 Measuring the Offset Voltage of the Comparator CAEX 1 OV Vcc RECAD CAEX 9 p CAON e g 5 CAF Capture CAO B Input of P m Timer A 09 x ew P2CA1 Vref Figure 15 21 The Voffsetin this configuration is in series with VcAo as shown in Figure 15 21 Vref Voffset Vcao Vref Voffset Offset Voltage of the Comparator CAEX 1 e g Capture Input of r Timer A lt to IHO 4 Voffset gt 1 Finally calculate from the below formulas TV offset x R x CC VCAO V V ref offset R x Cx In VCAO CC This leads to 2N1 V In Ad 0612 Vottset X 4 ref timer counts Comparator A 15 21
48. Ee a i ee Se CCISx0 CCIx Capture CCISx1 CCISx0 Capture Capture GND 3 Vee o o ee CClx CCMx1 Both Edges Selected 1 1 The following is a software example of a capture performed by software The data of capture compare register TBCCRx are taken by the software It is assumed that CCMx1 CCMx0 and 5 1 bits are set Bit CCISO selects the CCIx signal to be high or low gt gt Ne Ne gt XOR CCISx0 amp TBCCTLx 12 4 2 Capture Compare Block Compare Mode The compare mode is selected if the CAPx bit located in control word TBCCTLx is reset In compare mode all the capture hardware circuitry is inactive and the capture mode overflow logic is inactive The compare mode is most often used to generate interrupts at specific time intervals or used in conjunction with the output unit to generate output signals such as PWM signals The compare data is double buffered The software writes the compare data to the capture compare register but the data is transferred to the compare latch TBCLx to be compared by the compare logic The transfer of the compare data from the TBCCRx register to the compare latch is user selectable to be either immediate or dependent upon a timer event This double buffering allows the user to update multiple compare values simultaneously This is useful for example with PWM signals where the period or d
49. Overflow interrupt enable Individual enable for the overflow interrupt vector The overflow happens if a conversion result is written into an ADC memory ADC12MEMXx but the previous result was not read An interrupt service is requested if the overflow vector is generated the overflow interrupt enable flag ADC12OVIE is set and the general interrupt enable bit GIE is set There is no individual interrupt flag See the ADC12 Interrupt Vector Register ADC 12IV section for more information on ADC12 interrupts ADC120N bit4 Turn on the 12 bit ADC core Settling time constraints must be met when the ADC 12 core is powered up 0 Power consumption of the core is off No conversion will be started 1 ADC core is supplied with power If no A D conversion is needed ADC12ON can be reset to conserve power REFON bit5 Reference voltage ON 0 The internal reference voltage is switched off No power is consumed from the reference voltage generator 1 The internal reference voltage is switched The reference voltage generator consumes power When the reference generator is switched on the settling time of the reference voltage must be completed before the first sampling and conversion is started 2_5V bit6 Reference voltage level 0 The internal reference voltage is 1 5V if REFON 1 1 Theinternal reference voltage is 2 5V if REFON 1 MSC bit7 Multiple sample and conversion Valid only when the sample timer is selected to generate
50. The environment defines whether the value of the frequency integrator should be held or corrected A correction should be made when ambient conditions are anticipated to change drastically enough to increase or decrease the system frequency while the device is in LPM4 System Resets Interrupts and Operating Modes 3 25 Basic Hints for Low Power Applications 3 6 Basic Hints for Low Power Applications 3 26 There are some basic practices to follow when current consumption is a critical part of a system application Oooo Switch off analog circuitry when possible Switch off the MCLK source for the CPU when not required Use interrupts to activate the CPU Program execution starts in less than 6 us Select the lowest possible operating frequency for the individual peripheral module Disable unused peripherals Select the weakest drive capability if an LCD is used or switch the drive off Tie all unused inputs to an applicable voltage level The list below defines the correct termination for all unused pins Pin Potential Comment AVcc DVcc AVss DVss P6 0 A0 to P6 7 A7 open Switch unused pins to port function and output direction VREF open VeREF DVss Vner Vener DVss XIN If no crystal resonator clock source is used XT2IN DVcc XOUT TCLK open XT2OUT open Px 0 to Px 7 open Unused ports switched to output direction R03
51. The up down mode also supports applications that require dead times between output signals For example to avoid overload conditions two outputs driving an H bridge must never be in a high state simultaneously In the following example see Figure 11 13 the tgeag is tdead timer CCR1 CCR2 With tgeag Time during which both outputs need to be inactive ttimer Cycle time of the timer clock CCRx Content of capture compare register x Figure 11 13 Output Unit in Up Down Mode 11 OFFFFh CCRO CCR1 CCR2 Oh b 4 gt Dead Time Output Mode 6 PWM Toggle Set Output Mode 2 PWM Toggle Reset TAIFG EQU1 EQU1 TAIFG EQU1 EQU1 Interrupt Events EQU2 EQUO EQU2 EQU2 EQUO EQU2 The count direction is always latched with a flip flop Figure 11 14 This is useful because it allows the user to stop the timer and then restartitin the same direction it was counting before it was stopped For example if the timer was counting down when the MCx bits were reset then it will continue counting in the down direction if it is restarted in up down mode If this is not desired the CLR bitinthe TACTL register must be used to clear the direction Note that the CLR bit affects other setup conditions of the timer Refer to Section 11 6 for a discussion of the Timer A registers Figure 11 14 Timer Up Down Direction Control POR CLR in TACTL Up Down For 16 Bit Timer TAR Low Down Dir
52. 1 BIS 1 SR SETN Set negative bit 1 BIS 4 SR SETZ Set zero bit 1 BIS 2 SR TSTLW dst Test destination 0 1 CMP 0 9 TST B dst Test destination 0 1 CMP B 0 dst Program flow instructions BR dst Branch to MOV dst PC DINT Disable interrupt BIC 8 SR EINT Enable interrupt BIS 8 SR NOP No operation MOV 0h 0h RET Return from subroutine MOV SP PC Instruction Set Description B 7 Instruction Set Overview B 2 Instruction Set Description This section catalogues and describes all core and emulated instructions in alphabetical order Some examples serve as explanations and others as application hints The suffix W or no suffix in the instruction mnemonic results in a word operation The suffix B at the instruction mnemonic results in a byte operation B 8 ADC W ADC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Instruction Set Overview Add carry to destination Add carry to destination ADC dst or ADC W dst ADC B dst dst C dst ADDC 0 dst ADDC B 0 dst The carry bit C is added to the destination operand The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if dst was incremented from OFFFFh to 0000 reset otherwise Set if dst was incremented from OFFh to 00 reset otherwise V Set if an arithmetic
53. ACLK bis b DCOP amp FLL_CTLO Select f DCOCLK for MCLK and SMCLK bic SCGO SR Enable frequency control loop again bis GIE SR Enable interrupts 7 5 3 FLL Features for Low Power Applications Three conflicting requirements typically exist in battery powered MSP430x4xx real time applications _j Low frequency clock for energy conservation and time keeping High frequency clock for fast reaction to events and fast burst processing capability Clock stability The MSP430x4xx FLL clock system addresses the above conflicting requirements by providing both a low frequency ACLK with crystal stability and a stable high frequency MCLK with near instant on capability The DCO available in MSP430x4xx devices for MCLK and SMCLK is operational in less than 6 us The choice of a digital frequency locked loop versus an analog phase locked loop enables the benefit of fast start and stability A phase locked loop takes hundreds or thousands of clock cycles to start and stabilize The MSP430x4xx frequency locked loop starts immediately at the exact setting prior to shut down For minimum power consumption the MSP430x4xx system operates for extended periods in low power mode 3 with only the ACLK active for timers and low power peripherals Interrupts both from external and internal events drive the activation of MCLK SMCLK for the CPU and high speed peripherals In the MSP430x4xx any interrupt st
54. ACLK 8 timer stopped timer cleared BIS 101 amp Start timer with up mode LLLLLLS A M P OMOM3Y 12 6 2 Timer B Register TBR The TBR register is the value of the timer Figure 12 28 TBR Register 15 B TOR Timer Val 190h imer Value rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw O rw 0 rw 0 rw 0 Note Modifying Timer Register TBR When ACLK SMCLK or the external clock TBCLK or INCLK is selected for the timer clock any write to timer register TBR should occur while the timer is not operating otherwise the results may be unpredictable In this case the timer clock is asynchronous to the CPU clock MCLK and critical race conditions exist 12 6 3 Capture Compare Control Register TBCCTLx Each capture compare block has its own control word TBCCTLx shown in Figure 12 29 The POR signal resets all bits of TBCCTLx the PUC signal does not affect these bits Figure 12 29 ads Control Register TBCCTLx 44x CTLx 182h to Timer B3 41x 743 Wt WS 182h to 186h 12 32 Bit Bit 1 Bit 2 Bit 3 Bit 4 Bits 5 to 7 Timer B Registers Capture compare interrupt flag CCIFGx Capture mode If set it indicates that a timer value was captured in the TBCCRx register Compare mode If set it i
55. NOT src C gt dst or dst src 1 C dst The source operand is subtracted from the destination operand by adding the Source operand s 1s complement and the carry bit C The source operand is not affected The previous contents of the destination are lost N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Setif there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Setif an arithmetic overflow occurs reset otherwise OscOff CPUOff and GIE are not affected Two floating point mantissas 24 bits are subtracted LSBs are in R13 and R10 MSBs are in R12 and R9 SUB W R13 R10 16 bit part LSBs SUBC B R12 R9 8 bit part MSBs The 16 bit counter pointed to by R13 is subtracted from a 16 bit counter in R10 and R11 MSD SUB B R13 R10 Subtract LSDs without carry SUBC B R13 R11 Subtract MSDs with carry resulting from the LSDs Note Borrow Is Treated as a NOT Carry The borrow is treated carry Borrow Carry bit Yes 0 No 1 Instruction Set Description B 57 Instruction Set Overview SWPB Syntax Operation Description Status Bits Mode Bits Swap bytes SWPB dst Bits 15 to 8 lt gt bits 7 to 0 The destination operand high and low bytes are exchanged as shown in Figure 10 N Not affected Z Not affected C Not affected V Not affected OscOff CPUOff a
56. Note The XT2OF bit is always read as 0 in MSP430x41x devices because no XT2 oscillator is implemented on those devices OscCap The oscillator pins have internal capacitors that can be varied in a small range The capacitance at the pin can be varied from 0 pF to 18 pF When combined with a typical capacitance value of 2 pF for the pin and circuit board the effective crystal load capacitance can be varied from 1 pF to 10 pF 7 14 XTS FLL DCO FLL DIV XT2OFF FLL Module Control Registers 0 Effective crystal load capacitance is 1 pF 1 Effective crystal load capacitance is 6 pF 2 Effective crystal load capacitance is 8 pF 3 Effective crystal load capacitance is 10 pF Note The default value of OscCap is 0 providing an effective crystal load capacitance of 1 pF Reliable crystal operation may not be achieved unless the crystal is provided with the proper load capacitance either by selection of OscCap values or by external capacitors The LFXT1 oscillator operates with a low frequency crystal typically 32768 Hz LF mode or with a high frequency crystal or resonator HF mode 0 LF mode is selected 1 HF mode is selected The DCO bit selects if the DCO output is predivided before sourcing MCLK or SMCLK The division rate when used is selected with the FLL bits 0 DCO output is not divided 1 DCO output is divided before sourcing MCLK or SMCLK The FLL_DIV bits select division rate o
57. Timer B Registers Word Access A 15 Timer B Registers Word Access Continued Bit Cap com register TBCCRet 019Eh Cap com register TBCCR5t 019Ch Cap com register TBCCR4t 019Ah Cap com register TBCCRst 0198h Cap com register TBCCR2 0196h Cap com register TBCCR1 0194h Cap com register TBCCRO 0192h Timer_B register TBR 0190h Cap com control TBCCTL6f 018Eh Cap com control TBCCTL5t 018Ch Cap com control TBCCTLA4f 018Ah Cap com control 0188h Cap com control 2 0186h Cap com control TBCCTL1 0184h Cap com control TBCCTLO 0182h Timer_B control TBCTL 0180h Mod62 7 27 w 0 27 w 0 27 w 0 27 w 0 27 w 0 27 w 0 27 w 0 27 w 0 w 0 w 0 w 0 w 0 w 0 w 0 w 0 0 Mod61 CCIE4 cova CCIFG4 OutMod32 Mod31 OutMod30 CCIE3 COV3 CCIFG3 n rw n rw OutMod22 OutMod21 OutMod20 ouT2 cove cciFG2 n rw OutModi2 OutModit OutModio 1 OUT covi CCIFG1 n rw OutMod02 OutModo1 OutMod00 CCIEO CCIFGO rw rw rw rw rw rw TBID1 TBIDO 1 TBMCO Unused TBCLR TBIE TBIFG rw rw rw rw rw rw rw rw 6 2 rw 2 rw 2 rw 2 rw 2 rw 2 rw 2 rw 2 rw rw u rw rw u rw rw u rw
58. gt lt gt lt gt lt gt lt Single Conversion Single Conversion Single Conversion Single Conversion Single Conversion Time Time Time Time Time Single Period gt Single Period gt Single Period Single Period of Sequence of Sequence of Sequence of Sequence Period of Sequences Next Period of Sequences CL gt An active sequence may be stopped immediately by selecting single channel single conversion mode reset CONSEQ 1 bit and then resetting the enable conversion bit ENC The data in memory register ADC12MEMXx is unpredictable and the interrupt flag ADC12IFG x may or may not be set This is generally not recommended but may be used as an emergency exit Each time a conversion is completed the results are loaded into the appropriate ADC12MEMXx register and the corresponding interrupt flag ADC12 17 18 Conversion Modes ADC12IFG xis set to indicate completion of the conversion Additionally If the appropriate interrupt enable flags are set an interrupt request is generated see the ADC12 Interrupt Vector Register ADC 12IV section An illustration of sequence of channels mode is shown in Figure 17 8 Figure 17 8 Sequence of Channels Mode CONSEQ 1 ADC120N 1 4 x CStartAdd Wait for Enable SHS 0 1 4 ADC12SC 4 Wait for Trigger SAMPCON 47 EOS x 1 SAMPCON 1 Sample Input Channel Defined in ADC12MCTLx
59. next instruction s start condition is defined DADD R5 0 R8 Add LSDs C DADC 2 R8 Add carry to MSD The two digit decimal number contained in R5 is added to a four digit decimal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD B R5 0 R8 Add LSDs C DADC 1 R8 Add carry to MSDs Instruction Set Description B 23 Instruction Set Overview DADD W DADD B Syntax Operation Description Status Bits Mode Bits Example Example B 24 Source and carry added decimally to destination Source and carry added decimally to destination DADD src dst or DADD W src dst DADD B src dst src dst C dst decimally The source operand and the destination operand are treated as four binary coded decimals BCD with positive signs The source operand and the carry bit C are added decimally to the destination operand The source operand is not affected The previous contents of the destination are lost The result is not defined for non BCD numbers N Setif the MSB is 1 reset otherwise Z Setif result is zero reset otherwise C Setif the result is greater than 9999 Set if the result is greater than 99 V Undefined OscOff CPUOff and GIE are not affected The eight digit BCD number contained in R5 and R6 is added decimally to an eight digit BCD number contained in R3 and R4 R6 and R4 contain the MSDs CLRC CLEAR CARRY DADD R5 R3 add LSDs D
60. 1 Note After a PUC shared LCD port pins are configured as port function input di rection and are high impedence Ve LCD Controller Driver 16 2 5 LCD Control Register The LCD control register contents define the mode and operating conditions The LCD module is byte structured and should be accessed using byte instructions suffix B All LCD control register bits are reset with a PUC signal Figure 16 7 LCD Control and Mode Register LCDCTL 030h LCDM6 LCDM5 LCDM4 LCDMS LCDM2 LCDM1 LCDMO rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 LCDMO LCDMO 0 The timing generator is switched off Common and segment lines are low Ron is off Outputs selected as port output lines are not affected LCDMO 1 Common and segment lines active Ron is on Outputs selected as port output lines are not affected LCDM1 Not used LCDM2 to 4 These three bits select the display mode as described in Table 16 1 Table 16 1 LCDM Selections All segments are deselected The port outputs remain stable This supports flashing LCD o o 3 _ Staiomode o 3 3 pwee SMUXmoe The primary function of the LCDM2 bit is to support flashing or blinking the LCD The LCDM2 bit is logically ANDed with each segment s display memory value to turn each LCD segment on or off see Figure 16 8
61. 2 When using groups all TBCCRx registers must be updated with new data before the load will take place except when using immediate mode even if new data old data When using immediate mode each compare latch is updated immediately when its corresponding TBCCRx register is updated 3 When using groups different load modes may be selected for each group For example when grouped by 3 immediate mode may be selected via CLLDx bits in TBCCTL1 for TBCL1 TBCL2 and TBCL3 and mode 2 may be selected via CLLDx bits in TBCCTL4 for TBCL4 TBCL5 and TBCL6 12 5 The Output Unit Figure 12 22 Output Unit EQUO EQUx The Output Unit Each capture compare block contains an output unit shown in Figure 12 22 The output unit is used to generate output signals such as PWM signals Each output unit has eight operating modes that can generate a variety of signals based on the EQUO and EQUXx signals The output mode is selected with the bits located in the TBCCTLx register OUTx OMx2 OMx1 OMx0 3 4 4A 0000 0 Output Control 0 1 0 1 0 1 0 1 OUTx Signal Timer Clock j4 OUTx Output mode OUTx signal reflects the value of the OUTx bit Set mode OUT x signal reflects the value of signal EQUx PWM toggle reset EQUx toggles OUTx EQUO resets OUTx PWM set reset EQUx sets OUTx EQUO resets OUTx Toggle EQUx toggles OUTx signal Reset EQU
62. ADD amp ADC12IV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP ADC120V Vector 2 ADC overflow 2 JMP ADC12TOV Vector 4 ADC timing overflow 2 JMP ADC12MODO Vector 6 ADC12MEMO was loaded Nets subiicere antudeces ADC12IFG 0 2 JMP 12 1 Vector 8 ADC12MEM1 was loaded Die area Por NEN ADC12IFG 1 2 JMP ADC12MOD13 Vector 34 ADC12MEM14 was loaded ADC12IFG 14 2 JMP ADC12MOD14 Vector 36 ADC12MEM15 was loaded ADC12IFG 15 2 Module 15 Handler for ADC12IFG 15 starts here Note a JMP instruction is not needed to get here because the PC is already here after the ADD amp ADC12IV PC instruction i ADC120V Vector 2 ADC120V Flag First instruction to handle ADC12 overflow condition i ADCIA2TOV Vector 4 ADC120V Flag First instruction to handle ADC12 timing overflow condition ADC12MOD2 Vector 10 ADC12MEM2 was loaded ADC12IFG 2 MOV amp ADC12MEM2 R6 ADCI2IFG2 is reset due to access of ADC memory Task starts here ADC12 17 39 ADC12 Control Registers 17 40 RETI Back to main program 5 i ADC12MOD1 Vector 8 ADC12MEM1 was loaded ADC12IFG 1 ADD amp ADC12MEM1 R6 ADC12IFG1 is reset due to access of ADC memory Task starts here RETI Back to main program 5 The Module 3 handler shows a way to look if any other interrupt is pending 5 cycles have to be spent but 9 cycles
63. DVss R13 DVss R23 DVss R33 open S0 to S31 open Unused ports switched to port function and output direction to Com3 open RST NMI DVcc or Pullup resistor 100k TDI open TMS open TCK open Chapter 4 Memory MSP430 devices are configured as a von Neumann architecture It has code memory data memory and peripherals in one address space As a result the same instructions are used for code data or peripheral accesses Also code may be executed from RAM Topic Page Tete 4 2 4 2 the Memory 5514721211121 4 3 4 3 Internal ROM Organization 4 4 4 4 Peripheral Organization 4 5 4 1 Introduction 4 1 Introduction All of the physically separated memory areas ROM RAM SFRs and peripheral modules are mapped into the common address space as shown in Figure 4 1 for the MSP430 family The addressable memory space is 64KB Future expansion is possible Figure 4 1 Memory Map of Basic Address Space Address Function Access Hex OFFFFh Interrupt Vector Table ROM Word Byte OFFEOh OFFDFh Program Memory Branch Control Tables ROM Word Byte Data Tables 0200h Data Memory RAM Word Byte 01 Timer Word E 16 Bit Peripheral Modules ADC 0100h OFFh LCD Bi i 8 Bit P
64. EQUO EQUx OUTx Output Control Block OUTx Signal Timer Clock j OUTx OMx2 OMx1 OMx0 0000 0 3O0 0o Output mode OUTx signal reflects the value of the OUTx bit Set mode OUT x signal reflects the value of signal EQUx PWM toggle reset EQUx toggles OUTx EQUO resets OUTx PWM set reset EQUx sets OUTx EQUO resets OUTx Toggle EQUx toggles OUTx signal Reset EQUx resets OUTx PWM toggle set EQUx toggles OUTx EQUO sets OUTx PWM reset set EQUx resets OUTx EQUO sets OUTx O 0O07 00 Note OUTx signal updates with rising edge of timer clock for all modes except mode 0 Modes 2 3 6 7 not useful for output unit 0 Timer_A 11 17 Timer Modes 11 4 3 Output Unit Output Modes 11 18 The output modes are defined by the OMx bits and are discussed below The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0 Output modes 2 3 6 and 7 are not useful for output unit O Output mode 0 Output mode 1 Output mode 2 Output mode 3 Output mode 4 Output mode 5 Output mode 6 Output mode 7 Output mode The output signal OUTx is defined by the OUTx bit in control register CCTLx The OUTx signal updates immediately upon completion of writing the bit information Set mode The output is set when the timer value becomes equal to capture compare data CCRx It remains set until a reset of the timer or until a
65. INC R5 R5 is now negated R5 OFF52h Content of memory byte LEO is negated MOV B SOAEh LEO INV B LEO Invert LEO 051h INC B LEO MEM LEO is negated MEM LEO 052h JC JHS Syntax Operation Description Status Bits Example Example Instruction Set Overview Jump if carry set Jump if higher or same JC label JHS label If C 1 PC 2x offset gt PC If C 2 0 execute following instruction The status register carry bit C is tested If it is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If C is reset the next instruction following the jump is executed JC jump if carry higher or same is used for the comparison of unsigned numbers 0 to 65536 Status bits are not affected The P1IN 1 signal is used to define or control the program flow BIT 01h amp P1IN State of signal gt Carry JC PROGA If carry 1 then execute program routine A Carry 0 execute program here R5 is compared to 15 If the content is higher or the same branch to LABEL CMP 15 R5 JHS LABEL Jump is taken if R5 gt 15 zii Continue here if R5 15 Instruction Set Description B 33 Instruction Set Overview JEQ JZ Syntax Operation Description Status Bits Example Example Example B 34 Jump if equal jump if zero JEQ label JZ label lfZ 1 PC 2x offset PC If Z 0 execute followin
66. Instruction Set Description B 13 Instruction Set Overview BIS W Set bits in destination BIS B Set bits in destination Syntax BIS src dst BIS W src dst BIS B src dst Operation src OR dst dst Description The source operand and the destination operand are logically ORed The result is placed into the destination The source operand is not affected Status Bits N Not affected Z Not affected C Not affected V Not affected Mode Bits OscOff CPUOff and GIE are not affected Example The six LSBs of the RAM word TOM are set BIS 003Fh TOM set the six LSBs in RAM location TOM Example The three MSBs of RAM byte TOM are set BIS B 0E0h TOM set the 3 MSBs in RAM location TOM BIT W BIT B Syntax Operation Description Status Bits Mode Bits Example Example Example Instruction Set Overview Test bits in destination Test bits in destination BIT src dst src dst src dst The source and destination operands are logically ANDed The result affects only the status bits The source and destination operands are not affected N Set if MSB of result is set reset otherwise Z Setif result is zero reset otherwise C Setif result is not zero reset otherwise NOT Zero V Reset OscOff CPUOff and GIE are not affected If bit 9 of R8 is set a branch is taken to label TOM BIT 0200h R8 bit 9 of R8 set JNZ TOM Yes branch to TOM No proceed If bit 3 of R8 is se
67. N XOR V 2 0 JL Label Jump to label if N XOR V 1 JMP Label Jump to label unconditionally 16 Bit CPU 5 19 Instruction Set Overview 5 3 4 Short Form of Emulated Instructions The basic instruction set together with the register implementations of the program counter stack pointer status register and constant generator form the emulated instruction set these make up the popular instruction set The status bits are set according to the result of the execution of the basic instruction that replaces the emulated instruction Table 5 18 describes these instructions Table 5 20 Emulated Instructions Mnemonic Description Status Bits Emulation 2 Arlthmetic Instructions ADC W Add carry to destination ADDC 0 dst Add carry decimal to destination DADD 0 dat DADC B dst Add carry decimal to destination DADD B 0 dst DEC W Decrement destination SUB 1 dst DEC B Decrement destination SUB B 1 dst DECD W Double decrement destination 2 dst DECD B Double decrement destination SUB B 2 dst INC W Increment destination ADD 1 dst INC B dst Increment destination ADD B 1 dst INCD W Increment destination 2 dst INCD B Increment destination ADD B 2 dst SBC W Subtract carry from destination SUBC 0 dst SBC B Subtract carry from destination SUBC B 0 dst Logical Instructions INV W Invert destination 0FFFFh dst INV B Invert destination XOR B 1 dst RLA W Rotate left arithmetically DD dst dst RLA B
68. Rotate left arithmetically Rotate left arithmetically RLA dst or RLA W dst RLA B dst lt MSB 1 LSB 1 LSB 0 ADD dst dst ADD B dst dst The destination operand is shifted left one position as shown in Figure 6 The MSB is shifted into the carry bit C and the LSB is filled with 0 The RLA instruction acts as a signed multiplication by 2 An overflow occurs if dst gt 04000h and dst lt 0C000h before operation is performed the result has changed sign Figure B 6 Destination Operand Arithmetic Shift Left Status Bits Mode Bits Example Example Word 15 0 Byte 7 0 An overflow occurs if dst gt 040h and dst lt OCOh before the operation is performed the result has changed sign N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Loaded from the MSB V Setif an arithmetic overflow occurs the initial value is 04000h lt dst lt 0C000h otherwise it is reset Set if an arithmetic overflow occurs the initial value is 040h lt dst lt OCOh otherwise it is reset OscOff CPUOff and GIE are not affected R7 is multiplied by 4 RLA R7 Shift left R7 x 2 emulated by ADD R7 R7 RLA R7 Shift left R7 x 4 emulated by ADD R7 R7 The low byte of R7 is multiplied by 4 RLA B R7 Shift left low byte of R7 x 2 emulated by ADD B R7 R7 RLA B R7 Shift left low byte of R7 x 4 emulated by ADD B R7 R7 Note
69. SPI Mode The universal synchronous asynchronous receive transmit USART serial communication peripheral supports two serial modes with one hardware configuration These modes shift a serial bit stream in and out of the MSP430 at a programmed rate or at a rate defined by an external clock The first mode is the universal asynchronous receive transmit UART communication protocol discussed in Chapter 13 the second is the serial peripheral interface SPI protocol Bit SYNC in control register UOCTL for UARTO and U1CTL for USART1 selects the required mode SYNC 0 UART asynchronous mode selected SYNC 1 SPI synchronous mode selected This chapter describes the SPI mode Topic Page 14 1 USART Peripheral Interface 14 2 14 2 USART Peripheral Interface SPI Mode 14 3 14 3 Synchronous Operation 14 4 14 4 Interrupt and Control Functions 14 9 14 5 Control and Status Registers 14 15 14 1 14 1 USART Peripheral Interface The USART peripheral interface connects to the CPU as a byte peripheral module It connects the MSP430 to the external system environment with three or four external pins Figure 14 1 shows the USART peripheral interface module Figure 14 1 Block Diagram of USART Receive Buffer U1RXBUF or UORXBUF Receive Status SYNC
70. SPI Mode Chapter 15 Comparator A Chapter 16 Liquid Crystal Display Drive Chapter 17 ADC12 Appendix A Peripheral File Map Appendix B Instruction Set Description Appendix C Flash Memory This document uses the following conventions Program listings program examples and interactive displays are shown ina special typeface similar to a typewriter s Here is a sample program listing 0011 0005 0001 field Ty 2 0012 0005 0003 field 3 4 0013 0005 0006 field 6 3 0014 0006 even Related Documentation From Texas Instruments FCC Warning For related documentation see the web site http www ti com sc msp430 This equipment is intended for use in a laboratory test environment only It gen erates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other en vironments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to correct this interference 1 Contents EE 1 1 1 1 Features and Capabilities III 1 2 C ees A 1 3 19 ASX DEVICES Toutes db aac ea ame are tesa ca sath tase a a 1
71. Set if result is zero reset otherwise Set if result is not zero reset otherwise NOT Zero V Set if both operands are negative OscOff CPUOff and GIE are not affected The bits set in R6 toggle the bits in the RAM word TONI XOR R6 TONI Toggle bits of word TONI on the bits set in R6 The bits set in R6 toggle the bits in the RAM byte TONI XOR B R6 TONI Toggle bits in word TONI on bits set in low byte of R6 Reset to 0 those bits in low byte of R7 that are different from bits in RAM byte EDE XOR B EDE R7 Set different bit to 1s INV B R7 Invert Lowbyte Highbyte is Oh Instruction Set Description B 61 62 Appendix Flash Memory This chapter describes the MSP430 flash memory module The flash memory module is electrically erasable and programmable Devices with a flash memory module are multiple time programmable devices MTP They can be erased and programmed off board or in a system via the MSP430 s JTAG pe ripheral module a bootstrap loader or via the processor s resources Software running on an MSP430 device can erase and program the flash memory module This active software may run in RAM in ROM or in the flash memory The flash memory may be a different memory module or the same memory module Topic Page C 1 Flash Memory Organization 2 C 2 Flash Memory Data Structure and Operation 5 Flash Memory Contro
72. Transmit buffer UOTXBUF Read 077h Unchanged Table 14 3 USAHT1 Control and Status Registers Register T Scr Address Initial State USART control U1CTL Read write 078h See Section 14 5 1 Transmit control U1TCTL Read write 079h See Section 14 5 2 Receive control U1RCTL Read write 07Ah See Section 14 5 3 Modulation control U1MCTL Read write 07Bh Unchanged Baud rate 0 U1BRO Read write 07Ch Unchanged Baud rate 1 U1BR1 Read write 0701 Unchanged Receive buffer U1RXBUF Read write 07Eh Unchanged Transmit buffer U1TXBUF Read 07Fh Unchanged All bits are random following the PUC signal unless otherwise noted by the detailed functional description Reset of the USART module is performed by the PUC signal ora SWRST After a PUC signal the SWRST bit remains set and the USART module remains in the reset condition It is disabled by resetting the SWRST bit The SPI mode is disabled after the PUC signal The USART module operates in asynchronous or synchronous mode as defined by the SYNC bit The bits in the control registers can have different functions in the two modes All bits are described with their function in the synchronous mode SYNC 1 Their function in the asynchronous mode is described in Chapter 13 USART Peripheral Interface SPI Mode 14 15 Control and Status Registers 14 5 1 USART Control Register The information stored in the control register shown in Figure 14 15 determines the basic oper
73. Up mode TAIFG is set if the timer counts from CCRO value to 0000h Continuous mode TAIFG is set if the timer counts from OFFFFh to 0000h Up down mode TAIFG is set if the timer counts down from 0001h to 0000h Timer overflow interrupt enable TAIE bit An interrupt request from the timer overflow bit is enabled if this bit is set and is disabled if reset Timer clear CLR bit The timer and input divider are reset with the POR signal or if bit CLR is set The CLR bit is automatically reset andis always read as zero The timer starts in the upward direction with the next valid clock edge unless halted by cleared mode control bits Not used Mode control Table 11 4 describes the mode control bits MC1 Count Mode Description 0 1 0 1 Stop Timer is halted Up to CCRO Timer counts up to CCRO and restarts at O Continuous up Timer counts up to OFFFFh and restarts at 0 Up down Timer continuously counts up to CCRO and back down to 0 Timer A 11 23 Timer A Registers Bits 6 7 Input divider control bits Table 11 5 describes the input divider control bits Table 11 5 Input Clock Divider Control Bits ID1 IDO Operation Description 0 0 Input clock source is passed to the timer 0 1 2 Input clock source is divided by two 1 0 4 Input clock source is divided by four 1 1 8 Input clock source is divided by eight Bits 8 9 Clock source selection bits Table 11 6 describes the
74. and GIE are not affected Instruction Set Description B 55 Instruction Set Overview SUBLW SUB B Syntax Operation Description Status Bits Mode Bits Example Example Subtract source from destination Subtract source from destination SUB src dst or SUB W src dst SUB B src dst dst NOT src 1 gt dst or dst src gt dst The source operand is subtracted from the destination operand by adding the source operand s 1s complement and the constant 1 The source operand is not affected The previous contents of the destination are lost N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Setif there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Setif an arithmetic overflow occurs otherwise reset OscOff CPUOff and GIE are not affected See example at the SBC instruction See example at the SBC B instruction 7 Note Borrow Is Treated as The borrow is treated as carry Borrow bit Yes 0 No 1 SUBC W SBB W SUBC B SBB B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Overview Subtract source and borrow NOT carry from destination Subtract source and borrow NOT carry from destination SUBC src dst or SUBC W src dst or SBB src dst or SBB W src dst SUBC B src dst or SBB B src dst dst
75. may be saved if another interrupt is pending i ADC12MODO Vector 6 ADC12MEMO was loaded ADCI2IFG 0 First instruction to be executed x Task starts here JMP ADC12_HND With this instruction the software does not leave the handler it looks for pending ADC12 interrupts 2 Note Basic Clock System If the CPU clock MCLK is turned off CPUOff 1 then two or three additional cycles need to be added for synchronous start of the CPU system The delta of one clock cycle is caused when clocks are asynchronous to the restart of CPU clock MCLK A D Grounding and Noise Considerations 17 9 A D Grounding and Noise Considerations As with any high resolution converter care and special attention must be paid to the printed circuit board layout and the grounding scheme to eliminate ground loops and any unwanted parasitic components effects and noise Industry standard grounding and layout techniques should be followed to reduce these unwanted effects Ground Loops are formed when return current from the A D flows through paths that are common with other analog or digital circuitry If care is not taken this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the A D converter One way to avoid ground loops is to use a star connection scheme for AVgg shown in Figure 17 26 This way the ground current or reference curren
76. o Voc 9 1 o2 CAPx CMPx 1 Capture 0 9 Set CCIFGx Mode Timer Synchronize XE CCMx1 CCMx0 Clock Capture SCSx apture 0 O Disabled 0 1 Positive Edge 1 0 Negative Edge 1 1 Both Edges eS Y SCOCIx A CCIx The capture signal can also be synchronized with the timer clock to avoid race conditions between the timer data and the capture signal This is illustrated in Figure 11 19 The bit SCSx in capture compare control register CCTLx selects the capture signal synchronization Timer A 11 13 Timer Modes Figure 11 19 Capture Signal Timer Clock Timer CCIx Capture Set CCIFGx Applications with slow timer clocks can use the nonsynchronized capture signal In this scenario the software can validate the data and correct it if necessary as shown in the following example Software example for the handling of asynchronous capture signals The data of the capture compare register CCRx are taken by the software in the according interrupt routine they are taken only after a CCIFG was set The timer clock is much slower than the system clock SMCLK CCRx Int hand Start of interrupt handler CMP amp amp TAR Test if the data TAR JEQ Data Valid MOV amp TAR amp CCRx The data in CCRx is wrong use the timer data Data Valid s The data in CCRx are valid RETI
77. signal Otherwise the input divider remains unchanged when the timer is modified The state of the input divider is invisible to software Figure 12 3 Schematic of 16 Bit Timer TBSSEL1 TBSSELO Timer Clock Data 15 D ram 16 Bit Timert 1 CLK iiia ACLK Divider RC Control Equo SMCLK 2 d IDO MCO Set TBIFG 2 POR TBCLR INCLK 63 Pass 0 0 Stop Mode 0 1 1 2 0 1 Up Mode 1 0 1 4 1 0 Continuous Mode 1 1 1 8 1 1 Up Down Mode t Length is selectable for 8 10 12 or 16 bit operation 12 6 Timer B Operation Figure 12 4 Schematic of Clock Source Select and Input Divider TBSSEL1 TBSSELO TBCLK O o Input Divider 0 16 Bit Timer Clock ID1 IDO POR TBCLR 0 0 Pass 0 1 1 2 1 0 1 4 1 1 1 8 12 2 4 Starting the Timer The timer may be started or restarted in a variety of ways Release Halt Mode The timer counts in the selected direction when a timer mode other than stop mode is selected with the bits Halted by TBCLO 0 restarted by TBCLO gt 0 when the mode is either up or up down When the timer mode is selected to be either up or up down the timer may be stopped by loading 0 in compare latch 0 TBCLO via capture compare register TBCCRO The timer may then be restarted by loading a nonzero value to TBCLO In this scenario the timer starts incrementing in the up direction f
78. when in the up down mode on the next rising edge of the timer clock However if the new smaller period is written during a low phase of the timer clock then the timer continues to increment with the old period for one more clock cycle before adopting the new period and rolling to zero or beginning counting down This is shown in Figure 12 8 Note If TBCLO gt TBR max the counter rolls to zero with the next rising edge of timer clock Figure 12 7 New Period Old Period Timer TBCLOold 2 Register TBCLOnew 3 XX CX XXX DOO Timer B 12 9 Timer Modes Figure 12 8 New Period lt Old Period Timer Timer Register TBCLOold 5 Register TBCLOnew 2 TBCLOold 5 TBCLOnew 2 OI O ANWLOI 3 4 5 0 12 3 40 2101 TBCLO TBCLO 5 X 2 BOLO Loaded With 2 During High Clock Phase __ TBCLO Loaded With 2 During Low Clock Phase Timer Clock Timer Clock Timer Timer Xn X nu Xon TBCLO TBCLold TBCLnew TBCLO TBCLold TBCLnew Load New TBCLO Load New TBCLO During High Phase of Clock During Low Phase of Clock 1 Up mode 0 up down mode n 1 1 Up mode 0 up down mode n 12 3 3 Timer Continuous Mode The cont
79. 0 and CCISx1 bits are set Bit CCISO selects the CCIx Signal to be high or low XOR fCCISx0O amp CCTLx 11 16 Timer Modes 11 4 2 Capture Compare Block Compare Mode The compare mode is selected if the CAPx bit located in control word CCTLx is reset In compare mode all the capture hardware circuitry is inactive and the capture mode overflow logic is inactive The compare mode is most often used to generate interrupts at specific time intervals or used in conjunction with the output unit to generate output signals such as PWM signals If the timer becomes equal to the value in compare register x then Interrupt flag CCIFGx located in control word CCTLx is set An interrupt is requested if interrupt enable bits CCIEx and GIE are set Signal EQUx is output to the output unit This signal affects the output OUTx depending on the selected output mode The EQUO signal is true when the timer value is greater or equal to the CCRO value The EQU1 to EQU signals are true when the timer value is equal to the corresponding CCR1 to CCR2 values Each capture compare block contains an output unit shown in Figure 11 22 The output unitis used to generate output signals such as PWM signals Each output unit has 8 operating modes that can generate a variety of signals based on the EQUO and EQUx signals The output mode is selected with the OMx bits located in the CCTLx register Figure 11 22 Output Unit
80. 0 to 0 TBCL1 TBCL2 updated TBCL3 TBCL4 updated TBCL5 TBCL6 updated TBR counts to 0 simultaneously when TBR simultaneously when simultaneously when counts to 0 TBR counts to 0 TBR counts to 0 TBR counts to 0 TBCL1 TBCL2 updated TBCL3 TBCL4 updated TBCL5 TBCL6 updated or to TBCLO simultaneously when TBR counts to simultaneously when TBR counts to simultaneously when TBR counts to 0 or to TBCLO 0 or to TBCLO 0 or to TBCLO 3 1 3 TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to E TBCLO TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 t Timer B3 has only three CCR blocks TBCCR1 and TBCCR2 The load conditions for TBCL3 4 5 6 are not relevant and can be ignored saw eccl Table 12 2 Compare Latch Operating Modes Continued CLLDx From Load Conditions load TBCCRx data to compare latch TBCLx Lowest Counter TBCLGRP TBCCTLx in Mode inmediat TBCL1 TBCL2 TBCL3 loaded immediately when the TBCL4 TBCL5 TBCL6 loaded immediately when the corresponding TBCCRx register is loaded corresponding TBCCRx register is loaded TBR ts to 0 TBCL1 TBCL2 TBCL3 updated simultaneously when TBCL4 TBCL5 TBCL6 updated simultaneously when TBR counts to 0 TBR counts to 0 TBR ts to 0 TBCL1 TBCL2 TBCL3 updated simultaneously when TBCL4 TBCL5 TBCL6 updated simultaneously when TBR counts to 0 TBR counts to 0 TBR counts to 0 TBCL1 TBCL2 TBCL3 updated si
81. 0 to P2IFG 7 Interrupt enable bit P1IE 0 to P11E 7 and P2IE 0O to P2IE 7 Interrupt edge select bit P1IES 0 to P1IES 7 and 21 5 0 to P2IES 7 The interrupt flags P1IFG 0 to P1IFG 7 source one interrupt and P2IFG 0 to P2IFG 7 source one interrupt Any interrupt event on one or more pins of P1 0 to P1 7 or P2 0 to P2 7 requests an interrupt when two conditions are met the appropriate individual bit PnIE x is set and the GIE bit is set Interrupt flags P1IFG 0 to P1IFG 7 or P2IFG 0 to P2IFG 7 are not automatically reset The software of the interrupt service routine should handle the detection of the source and reset the appropriate flag when it is serviced Ports P3 P4 P5 P6 8 3 Ports P3 P4 P5 P6 General purpose ports P3 P6 function as shown in Figure 8 3 Each pin can be selected to operate with the I O port function or to be used with a different peripheral module This multiplexing of pins allows for a reduced pin count on MSP430 devices Four registers control each of the ports see Section 8 3 1 Ports P3 P6 are connected to the processor core through the 8 bit MDB and the MAB They should be accessed with byte instructions using the absolute address mode Figure 8 3 Ports P3 P6 Configuration MDB MSB LSB Pn 7 0 8 3 1 Port P3 P6 Control Registers The four control registers of each port give maximum configuration flexibility of digital I O All individual I O bits are programme
82. 14 9 Interrupt and Control Functions Figure 14 7 State Diagram of Receiver Enable Operation MSP430 as Master No Data Written to UXTXBUF USPIIE 0 Not Completed USPIIE 1 Idle State Receiver Enabled Receiver Collects Character Receive USPIIE 1 Disable Handle Interrupt Conditions USPIIE 0 Character Received PUC USPIIE 0 14 4 1 2 Receive Transmit Enable Bit MSP430 as Slave Three Pin Mode The receive operation functions differently for three pin and four pin modes when the MSP430 USART module is selected to be the SPI slave In the three pin mode shown in Figure 14 8 no external SPI receive control signal stops an active receive operation A PUC signal a software reset SWRST or areceive transmit enable USPIIE signal can stop a receive operation and reset the USART Figure 14 8 State Diagram of Receive Transmit Enable MSP430 as Slave Three Pin PUC Mode USPIIE 0 No Clock at UCLK Not Completed Idle State Receive Enabled Receiver Collects Character USPIIE 1 External Clock Present Receive Disable Handle Interrupt Conditions Character USPIIE 1 Received USPIIE 0 Note USPIIE Re Enabled SPI Mode After the receiver is completely disabled a reenabling of the receiver is asyn chronous to any data stream on the communication l
83. 3 pf orem 2 P2IFG 0 see Notes 1 and 2 port P2 eight flags To Maskable OFFE2h P2IFG 7 see Notes 1 and 2 BTIFG Maskable OFFEOh NOTES 1 Multiple source flags 2 Interrupt flags are located in the module 3 Non maskable the individual interrupt enable bit can disable an interrupt event but the general interrupt enable can not disable it System Resets Interrupts and Operating Modes 3 19 Operating Modes Table 3 12 Interrupt Sources Flags and Vectors of 43x 44x Configurations INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT ME PRIORITY Power up OFFFEh 15 highest External Reset Watchdog WDTIFG Flash memory KEYV see Note 4 NMI NMIIFG see Notes 4 and 6 Non maskable Oscillator Fault OFIFG see Notes 4 and 6 Non maskable OFFFCh Flash memory access violation ACCVIFG see Notes 4 and 6 Non maskable Timer B7t CCIFGO see Note 5 Maskable OFFFAh 13 CCIFG1 to CCIFG6 Timer B7t TBIFG see Notes 4 and 5 Maskable OFFF8h 9 s 6 cor om P1IFG O Notes 4 and gt l O port P1 eight flags To Maskable OFFE8h 4 P1IFG 7 see Notes 4 and 5 USART1 receivet URXIFG1 Maskable OFFE6h USART1 transmitt UTXIFG1 Maskable OFFE4h 2 P2IFG 0 see Notes 4 and 5 l O port P2 eight flags To Maskable OFFE2h P2IFG 7 see Notes 4 and 5 BTIFG Maskable OFFEOh T 43xuses Timer B3 with CCIFGO CC
84. 3 1 4 44xXiIDEVICEST s iege DEED Malena vad dls natn 1 4 Architectural Overview nnn nnn n 2 1 2 1 INMOGQUCTION 22 2 2 2 2 Central Processing nee meee ioe ene ES 2 2 2 3 Program Memory m 2 3 2 4 DataMemory mmn 2 3 2 5 Operation hh 2 3 2 5 Penpherals 2 s co ee consRDLEPRDUDLERDSHTREDUILCRTUERTULCAR eee hee UD eR D Ded 2 4 2 7 Oscillator and Clock Generator 2 4 System Resets Interrupts and Operating Modes 3 1 3 1 System Reset and Initialization nets 3 2 Introductlonis ial aa Pia 3 2 3 1 2 Device Initialization After System Reset 3 6 3 2 Global Interrupt Structure nh 3 7 3 3 MSP430 Interrupt Priority Scheme 3 8 3 3 1 Operation of Global Interrupt Reset NMI 3 10 3 3 2 Operation of Global Interrupt Oscillator Fault Control 3 10 3 4 Interrupt Processing 2 0 0 n 3 11 3 4 4 Interrupt Control Bits in Special Function Registers SFRs 3 13 3 4 2 Interrupt Vector
85. 4 P6DIR 3 rw 0 rw 0 rw 0 3 P6SEL 2 rw 0 P6DIR 2 rw 0 P6OUT 2 1 P6SEL 1 rw 0 P6DIR 1 rw 0 P6OUT 1 rw P6IN 7 P6IN 6 P6IN 5 P6IN 4 P6IN 3 P6IN 2 P6IN 1 r r r r P5SEL 7 P5SEL 6 PeSEL 5 P5SEL 4 P5SEL 3 rw 0 rw 0 rw 0 P5OUT 7 P5OUT 6 P5OUT 5 P5OUT 4 P5OUT 3 rw rw rw 2 r r WwW P5SEL 2 rw 0 Ww P5SEL 1 rw 0 P5DIR 1 rw 0 P5OUT 1 rw PSIN 7 PSIN 6 P5IN 5 P5IN 4 5 PSIN 2 5 1 r r r P2SEL 7 P2SEL 6 P2SEL 5 P2SEL 4 P2SEL 3 P2SEL 2 P2SEL 1 rw 0 rw 0 rw 0 rw 0 rw 0 6 4 rw rw rw rw P6OUT 7 PeOUT 6 5 4 PeOUT 3 rw r rw r rw P5DIR 7 P5DIR 6 P5DIR 5 P5DIR 4 P5DIR 3 rw 0 rw rw 0 rw rw 0 rw rw rw rw r r r P2OUT 7 P2OUT 6 P2OUT 5 P2OUTA P2OUT 3 P2OUT 2 P2OUT 1 rw rw r rw rw P2IN 7 P2IN 6 P2IN 5 P2IN 4 P2IN 3 r r r P2IN 2 r Mm P1SEL 7 P1SEL 6 P1SEL 5 P1SEL 4 P1SEL 3 P1SEL 2 P1SEL 1 rw 0 rw rw 0 rw rw 0 rw 0 rw 0 P1IE 7 P1IE 6 P1IE 5 P1IE 4 P1IE 3 P1IE 2 P1IE 1 rw 0 rw rw 0 rw rw 0 rw rw 0 P1IES 7 P1IES 6 P1IES 5 P1IES 4 P1IES 3 P1IES 2 P1IES 1 rw r rw r rw rw rw P1IFG 7 P1IFG 6 P1IFG 5 P1IFG 4 P1IFG 3 rw 0 rw rw 0 rw rw 0 P1DIR 7 P1DIR 6 P1DIR 5 P1DIR 4 P1DIR 3 rw 0 rw rw 0 rw rw 0 1 7 6 PIOUT 5 P1OUT 4 P1OUT 3 rw rw rw rw rw P1IN 7 1 6 P1IN 5 P1IN 4 P1IN 3 r r r r r Ww Ww Ww Ww P2IES 7 P2IES 6 P2IES 5 P2I
86. 6 2 XTS FLL DIV OscOff XIN 2 4 8 32 768 kHz crystal P1 5 TACLK ACLK XTS_FLL 0 ACLK n lt LFXT1 oscillator SCGO Auxiliary Clock 455 kHz XOUT re fans 8 as pei Osc XTS_FLL 1 SELMt T gt N 1 Frequency Integrator I I 3 I ferystal 0 t Need of ext Capacitors I O O Q MCLK See crystal parameter 1 2 fsystem 1 yste fpcocL A 2 4 8 DCO Modulation j CPUOTf DCO ferysta X D X N 1 1 1 ferystal X N 1 lo 6 SELS Le eee eee ei ei ee UM UM 0 455 kHz XT2IN DCOCLK o 0 8 MHz Lec XT oscillator fl XT2CLK SMCLK Co 6 l lt 1 O XT2OUT Oscillator Fault 4 1 2 peo Fanii DCOF SMCLKOFF LF Osc Fault 1 1 1 mcs XTS FLL OFIFG ext Capacitors i 1 1 Set Osc Fault flag see crystal parameter XT1 Osc Fault XT2 Osc Fault T The clock source for MCLK is forced to DCOLCK if the selected clock source for MCLK fails Failing includes the crystal oscillator has not started or stopped working Note that if MCLK is automaticaly switched to DCLOCK because of a failure the SELM bits will NOT change They will retain their previous setting and should be reset by doftware t OscOff bit switches off the LFXT1 oscillator only if the oscillator is unused by MCLK SELM lt gt 3 or CPUOff 1
87. 8 11 Watchdog Timer Ihm hm 9 1 9 1 The Watchdog Timer Hm 9 2 9 1 1 Watchdog 9 3 9 1 2 Watchdog Timer Interrupt Control Functions 9 5 9 1 3 Watchdog Timer Operation 9 5 Basic Timer 22 22 E eda i ee ee ee ee tere eee RE 10 1 1019 Basie Men cnet 10 2 10 1 1 Basic Timer Registers eens 10 3 10 1 2 Special Function Register Bits 10 5 10 1 3 Basic Timert Operation he n RR VR E rS 10 5 10 1 4 Basic Timer Operation Signal 10 6 AD ecc 11 1 i scies ir ert P Ce e EE NL EE REL MERERI 11 2 11 2 Timer A Operation css opine eran Lunes ere Luar paceman 11 3 11 2 1 Timer Mode Control n 11 3 11 2 2 Clock Source Select and 11 4 11 2 3 Starting the Timer ix eccorsaserethcnrererfsnvaReneih nepLeez ns 11 5 11 3 Timer Modes ee e TI Cet ge E E 11 5 11 3 1 Timer Stop Mode 11 5 11 32 Timar Up MOIE Pea ala aa 11 5 11 3 3 Timer Continuous Mode 11 8 11 3 4 Timer Up Down Mode
88. 9 ADC12 Registers Byte and Word Access Continued Bit 4 15 14 13 12 11 0 ADC12MEM 15 Unused Unused Unused Unused MSB Conversion Result LSB 015Eh ro ro ro ro All conversion result bits of type rw ADC12MEM 14 Unused Unused Unused Unused MSB Conversion Result gt LSB 015Ch ro ro ro ro All conversion result bits of type rw ADC12MEM 13 Unused Unused Unused Unused MSB Conversion Result gt LSB 015Ah ro ro ro ro All conversion result bits of type rw ADC12MEM 12 Unused Unused Unused Unused MSB Conversion Result gt LSB 0158h ro ro ro ro All conversion result bits of type rw ADC12MEM11 Unused Unused Unused Unused MSB Conversion Result gt LSB 0156h ro ro ro ro All conversion result bits of type rw ADC12MEM 10 Unused Unused Unused Unused MSB Conversion Result gt LSB 0154h ro ro 0 ro All conversion result bits of type rw ADC12MEM9O Unused Unused Unused Unused MSB lt Conversion Result gt LSB r ro ro All conversion result bits of type rw ADC12MEM8B Unused Unused Unused Unused MSB Conversion Result gt LSB 0150h ro ro ro All conversion result bits of type rw ADC12MEM7 Unused Unused Unused Unused MSB lt _ Conversion Re
89. A AND src dst src and dst gt dst 0 i BIT src dst src and dst 0 BIC src dst not src and dst gt dst BIS src dst src or dst dst gt XOR src dst src xor dst dst bi The status bit is affected The status bit is not affected 0 The status bit is cleared 1 The status bit is set SS OS eed Note Instructions CMP and SUB The instructions CMP and SUB are identical except for the storage of the result The same is true for the BIT and AND instructions LLLLLLL IIBANSaAAaA3aaa 16 Bit CPU 5 17 Instruction Set Overview 5 3 2 Single Operand Format Il Instructions Figure 5 8 illustrates the single operand instruction format See section 5 2 8 for information on number of code words and execution cycles per instruction Figure 5 8 Single Operand Instruction Format 15 ide 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Table 5 16 describes the effects of an instruction on the single operand instruction status bits Table 5 18 Single Operand Instruction Format Results Mnemonic S Reg D Reg Operation V N Z Cc C MSB 1SB C gt dst MSB MSB SB C 0 PUSH sc X O SP 2 SPsc QSP SWPB dst 1 CAL dti SP 2 8P 2 stack dst PC REM TOSGSRSP SP 2 X X X X TOS SP lt SP 2
90. Bit Timer Counter mode counter BTCNT1 is incremented constantly with ACLK When reading the counters the user should be aware that the counter clock and CPU clock may be asynchronous Therefore special software consideration may be required to assure a correct reading The 2 clock signal can be selected to be SMCLK ACLK or ACLK 256 using the control signals SSEL and DIV Counter BTCNT2 is incremented with the signal selected One of the eight counter outputs can be selected to set the Basic Timer1 interrupt flag Read and write access can be asynchronous when ACLK or ACLK 256 is selected The hold bit stops all operations 10 1 3 2 16 bit Counter Mode The 16 bit timer counter mode is selected when control bit DIV is set In this mode the clock source of counters BTCNT1 and 2 is the ACLK signal The hold bit stops all operations 10 1 4 Basic Timer Operation Signal fj cp 10 6 The LCD controller uses the f signal from the Basic Timer1 to generate the timing for common and segment lines The frequency of signal fj is generated from ACLK Using a 32 768 Hz crystal the fj frequency can be 1024 Hz 512 Hz 256 Hz or 128 Hz Bits FRFQ1 and FRFQO allow the correct selection of frame frequency The proper frequency fj cp depends on the LCD s requirement for framing frequency and LCD multiplex rate and is calculated by 2 x MUX rate x fFraming A 3 MUX example follows LCD data sheet fFra
91. Bits in SFRS 20 00 eee tee eee ees 3 13 MSP340x41x Interrupt Enable Registers 1 2 3 14 MSP430x43x Interrupt Enable Registers 1 2 3 14 MSP430x44x Interrupt Enable Registers 1 2 3 15 MSP430x41x Interupt Flag Registers 1 and 2 3 15 MSP430x43x Interrupt Flag Registers 1 and 2 3 16 MSP430x44x Interrupt Flag Registers 1 and 2 3 16 MSP430x41x Module Enable Registers 1 and 2 3 17 MSP430x43x Module Enable Registers 1 2 3 17 MSP430x44x Module Enable Registers 1 2 3 18 Interrupt Sources Flags and Vectors of 41x Configurations 3 19 Interrupt Sources Flags and Vectors of 43x 44x Configurations 3 20 Low Power Mode Logic Chart 3 23 Peripheral File Address Map Word 4 8 Peripheral File Address Map Byte Modules 4 9 Special Function Register Address 4 10 Register by Functions eR hh nnn 5 2 Description of Status Register Bits
92. Byte Operation High Byte Low Byte ees Register Memory Byte Register Operation High Byte Low Byte RAM and Peripheral Organization The following examples describe the register byte and byte register operations Example Register Byte Operation Example Byte Register Operation R5 0A28Fh R5 01202h R6 0203h R6 0223h Mem 0203h 012h Mem 0223h 05Fh ADD B R5 0 R6 ADD B R6 R5 08 05Fh 012h 002h Low byte of R5 OA1h 00061h Store into R5 High byte is 0 Mem 02031 0 1 R5 00061h 0 7 0 1 0 4 0 0 Low byte of register Addressed byte Addressed byte Low byte of register gt Addressed byte Low byte of register zero to High byte OAM aem Note Word Byte Operations Word byte or byte word operations on memory data are not supported Each register byte or byte register is performed as a byte operation 4 4 2 Peripheral Modules Address Allocation Some peripheral modules are accessible only with byte instructions while others are accessible only with word instructions The address space from 0100 to 01FFh is reserved for word modules and the address space from 00h to OFFh is reserved for byte modules Peripheral modules that are mapped into the word address space must be accessed using word instructions for example MOV R5 amp WDTCTL Peripheral modules that are mapped into the byte address space must be accessed with byte instru
93. Core Instructions B 5 B 1 3 Emulated Instructions eee eens B 6 B 2 Instruction Set Description B 8 Fl sh Memory IA EUER ee ee eee 1 C 1 Flash Memory Organization C 2 C 1 1 Why Is a Flash Memory Module Divided Into Several Segments 5 C 2 Flash Memory Data Structure and Operation 5 C 2 1 Flash Memory Basic Functions C 6 C 2 2 Flash Memory Block Diagram C 6 C 2 3 Flash Memory Basic Operation C 6 C 2 4 Flash Memory Status During Code Execution C 8 C 2 5 Flash Memory Status During Erase C 8 C 2 6 Flash Memory Status During Write Programming C 10 Flash Memory Control Registers 0 00 eee eee eens C 13 C 3 1 Flash Memory Control Register FCTL1 C 13 C 3 2 Flash Memory Control Register FCTL2 C 15 C 3 3 Flash Memory Control Register FCTL3 C 16 C 4 Flash Memory Interrupt and Security Key Violation C 18 C 4 1 Example of an NMI Interrupt C 20 C 4 2 Protecting One
94. DEC R9 Decrement counter JNZ Loop Counter z 0 continue copying NS Copying completed The contents of table EDE byte data are copied to table TOM The length of the tables should be 020h locations MOV EDE R10 Prepare pointer MOV 020h R9 Prepare counter MOV B QR10 TOM EDE 1 R10 Use pointer in R10 for both tables DEC R9 Decrement counter JNZ Loop Counter z 0 continue copying ERN Copying completed Instruction Set Description B 41 Instruction Set Overview NOP Syntax Operation Emulation Description Status Bits B 42 No operation NOP None MOV 0 R3 No operation is performed The instruction may be used for the elimination of instructions during the software check or for defined waiting times Status bits are not affected The NOP instruction is mainly used for two purposes _j To hold one two or three memory words To adjust software timing Note Emulating No Operation Instruction Other instructions can emulate the NOP function while providing different numbers of instruction cycles and code words Some examples are Examples MOV 0 R4 0 R4 6 cycles 3 words MOV R4 0 R4 5 cycles 2 words BIC 0 EDE R4 4 cycles 2 words 2 2 cycles 1 word BIC 0 R5 1 cycle 1 word However care should be taken when using these examples to prevent unintended results For example if MOV 0 R4 0 R4 is used and the value in R4 is 120h then a security
95. FFFFh and for negative numbers is 1 OFFFF FFFFh to 231 8000 0000h An overflow occurs when the sum of two negative numbers yields a resultthat is in the range given above for a positive number An under flow occurs when the sum of two positive numbers yields a result that is in the range for a negative number The maximum number of successive MACS instructions without underflow or overflow is limited by the individual application and should be determined us ing a worst case calculation Care should then be exercised to not exceed the maximum number or to handle the conditions accordingly Hardware Multiplier 6 9 6 10 Chapter 7 FLL Clock Module This chapter discusses the clock module used in the MSP430x4xx families The FLL clock module in the MSP430x4xx includes a watch crystal oscillator a high frequency crystal or resonator oscillator RC type digitally controlled oscillator DCO and a frequency locked loop FLL to ensure the accuracy of the DCO The FLL is an extended version of the FLL module in the MSP430x3xx family It supports a larger clock frequency range and a watch crystal or high frequency crystal operation of the oscillator and oscillator fault detection Topic Page TA The FEL Glock Module 7 2 T2 EEXIdOscillatorz 9 5 25 em 7 4 7 3 Digitally Controlled Oscillator DCO and eere reis 7 5 7 4 Os
96. Family Byte Access A 3 Digitalil O Byte Access eie meme 3 A 4 Basic Timer1 Registers Byte Access A 5 A 5 FLL Registers Byte Access A 5 6 SVS Register Bye AO CESS e E A 5 A 7 Comparator_A Register Byte A 5 A 8 USARTO USART1 UART Mode Sync 0 Byte Access A 6 A 9 USARTO USARTI SPI Mode Sync 1 Byte Access A 7 A 10 ADC12 Registers Byte and Word Access A 8 A 11 LCD Registers Byte Access A 11 A 12 Watchdog Timer Word Access A 12 A 13 Flash Control Registers Word 5 A 12 A 14 Hardware Multiplier Word Access A 13 A 15 Timer A Registers Word lt 5 A 14 16 Timer B Registers Word lt 5 A 16 A 1 Overview A 1 Overview A 2 Bit accessibility and or hardware definitions are indicated following each bit symbol L G TL O G L5 rw r r0 r1 w 0 wi Read write Read only Read as 0 Read as 1 Write only Write as 0 Write as 1 No register bit implemented writing a 1 results in a pulse The register bit is always read as 0 Cleared by hardware Set by hardware Condition after PUC si
97. Mark and Space Definitions 00 cece cette m 13 17 Receive Status Control aed 13 20 Break Detect BRK Bit With Halted UART Clock 13 25 USART Synchronous Master Mode Receive Initiation 14 7 USPIIE Re Enabled SPI Mode e cece eee eens 14 10 Writing to UXTXBUF SPI Mode ene e ene eeneeees 14 12 Writing to UXTXBUF Reset of Transmitter SPI Mode 14 12 Availability of ADC12CLK During Conversion 17 22 Warning Modifying ADC control register during active conversion 17 34 Warning SOFTWARE WRITE TO REGISTER ADC12MEMx 17 35 Writing to Read Only Register ADC121V ete eee 17 38 B asic Glocle System 2 2 wae ee eet oer aduer E 17 40 Asterisked Instructions 3 Contents Operations Using the Status Register SR for Destination B 4 Conditional and Unconditional Jumps esee B 6 Disable Interrupt eee hear ie Gener le elec B 28 Enable Intermpt cadet she nere E tete te ebbe Dee B 29 Emulating No Operation Instruction eh B 42 The System Stack Pointer eee ened eee teens 43 The System Stack Pointer
98. Note Any external interrupt event should be at least 1 5 times MCLK or longer to ensure that it is accepted and the corresponding interrupt flag is set Digital I O Configuration 8 5 Ports P1 P2 8 2 1 5 Interrupt Edge Select P1IES P2IES Each interrupt edge select register contains a bit for each corresponding I O pin to select what type of transition triggers the interrupt flag When Bit 0 The interrupt flag is set with a low to high transition Bit 1 The interrupt flag is set with a high to low transition Changing the P1IES and P2IES bits can result in setting the associated interrupt flags PnIES x PnIN x PnIFG x 0 5 1 0 Unchanged 0 5 1 1 May be set 10 0 May be set 10 1 Unchanged ______ _ _ aAA AEE 8 2 1 6 Interrupt Enable P1IE P2IE Each interrupt enable register contains bits to enable the interrupt for each pin in the port Each of the sixteen bits corresponding to pins P1 0 to P1 7 and P2 0 to P2 7 is located in the P1IE and P2IE registers When Bit 0 The interrupt request is disabled Bit 1 The interrupt request is enabled E Wo Qm A GEM eS eS Oooo Note Port P1 Port P2 Interrupt Sensitivity Only transitions not static levels cause interrupts If an interrupt flag is still set when the RETI instruction is executed for example a transition occurs during the interrupt service routine an interrupt occurs again after RETI is co
99. Overflow logic is provided with each capture compare register to flag the user if a second capture is performed before data from the first capture was read successfully Bit COVx in register CCTLx is set when this occurs as shown in Figure 11 20 11 14 Timer Modes Figure 11 20 Capture Cycle Idle Capture Capture Read Read Taken Capture No Capture Taken Capture Taken Capture Capture Read and No Capture Capture Clear Bit COV in Register CCTL Second Capture Taken COV 1 Idle Overflow bit COVx is reset by the software as described in the following example Software example for the handling of captured data looking for overflow condition The data of the capture compare register CCRx are taken by the software and immediately with the next instruction the overflow bit is tested and a decision is made to proceed regularly or with an error handler CCRx_Int_hand Aes Start of handler Interrupt MOV amp CCRx RAM Buffer BIT COV amp CCTLx JNZ Overflow Hand RETI Overflow Hand BIC COV amp CCTLx reset capture overflow flag get back to lost Synchronization RETI Note Capture With Timer Halted The capture should be disabled when the timer is halted The sequence to follow is stop the capture then stop the timer When the capture function is restarted the sequence should be start the
100. PCB layout techniques Analog Inputs and Multiplexer 17 3 2 Input Signal Considerations During sampling the analog input signal is applied to the internal capacitor array of the A D core Therefore the charge of the capacitor array is supplied directly by the source The capacitor array has to be charged completely during the sampling period Therefore the external source resistances dynamic impedances and capacitance of the capacitor array must be matched with the sampling period so the analog signal can settle to within 12 bit accuracy Additionally source impedances also affect the accuracy of the converter The source signal can drop at the input of the device due to leakage current or averaged dc input currents due to input switching currents For a 12 bit converter the error in LSBs due to leakage current is Error LSBs 4 096 x uA of leakage current x of source resistance VR Vn For example a 50 nA leakage current with a 10 kO source resistance and a 1 5 V Veer gives 1 4 LSBs of error These errors due to source impedance also apply to the output impedance of any external voltage reference source applied to Veper The output impedance must be low enough to enable the transients to settle within 0 2 ADCLK and generate leakage current induced errors of lt lt 1LSB See the Sampling section for more details on sample timing and sampling con siderations 17 3 3 Using the Temperature Diode To use t
101. PUSH R5 R5 WILL HOLD THE ADDRESS MOV RESLO R5 THE RESLO REGISTER MOV amp amp MPY LOAD 1ST OPERAND DEFINES ADD UNSIGNED MULTIPLY MOV amp 2 amp 2 LOAD 2ND OPERAND AND START ULTIPLICATION Ck Ck Ck ck ck ck kk ck ck ck ck kk Ck ck ck kk Ck Ck ck Ck kk Ck kk kk Ck Ck ck ck ck kk ck ck ck kk Ck ck ck ko Mk ko kk ko ko ko ko kock ok is EXAMPLE TO ADD THE RESULT OF THE HARDWARE ULTIPLICATION TO THE RAM DATA 64BITS KKK KKK KK KKK ck kk kk ck kk Ck Ck ck Ck kk Ck ck ck kk Ck ko ck ck kk ko ck ck ck kk Ck ck ck ko kk Sk kc k ko ok NOP MIN ONE CYCLES BETWEEN MOVING HE OPERAND2 TO HW MULTIPLIER AND PROCESSING THE RESULT WITH INDIRECT ADDRESS MODE ADD R5 amp RAM ADD LOW RESUL RA ADDC R5 amp RAM 2 ADD HIGH RESULT TO RAM 2 ADC amp RAM 4 ADD CARRY TO EXTENSION WORD ADC amp RAM 6 IF 64 BIT LENGTH IS USED POP R5 The previous example shows that the indirect or indirect autoincrement address modes when used to transfer the result of a multiplication operation to the destination need more cycles and code than the absolute address mode There is no need to access the hardware multiplier using the indirect addressing mode Hardware Multiplier 6 7 Hardware Multiplier So
102. RETI Vector 0 No interrupt 5 JMP TIMMOD1 Vector 2 Module 1 2 11 5 4 4 Timing Limits Timer A Registers JMP TIMMOD2 Vector 4 Module 2 2 RETI Reserved 2 RETI Reserved 2 i Module 5 Timer Overflow Handler the Timer Register is expanded into the RAM location TIMEXT MSBs T T TIMOVH Vector 10 TIMOV Flag INC TIMEXT Handle Timer Overflow 4 RETI 5 F TIMMOD2 Vector 4 Module 2 ADD NN amp CCR2 Add time difference 5 E Task starts here RETI Back to main program 5 TIMMOD1 Vector 2 Module 1 ADD MM amp CCR1 Add time difference 5 pet Task starts here RETI Back to main program 5 The vector address may be different for different devices WORD TIM HND Vector for Capture Compare Module 1 4 and timer overflow TAIFG WORD TIMMODO Vector for Capture Compare Module 0 If the FLL is turned off then two additional cycles need to be added for a synchronous start of the CPU and system clock MCLK The software overhead for different interrupt sources includes interrupt latency and return from interrupt cycles but not the task handling itself as described Capture compare block CCRO 11 cycles Capture compare blocks CCR1 to CCR4 16 cycles Timer overflow TAIFG 14 cycles With the TAIV register and the previous software the shortest repetitive time distance tcRmin between two events using a compare register is tcRmin ttaskma
103. Ry 070 n amp 1 0 1 amp LCDn 1 i atb c d e f b c 9 E on segments according to the LCD in 3MUX has 9 segments per digit word table required for displayed characters Load segment information to temporary mem Ry 0000 Obch Oagd Oyfe write g d y t e of Digit n LowByte Ry Oyfe 0000 Obch by c bh of Digit HighByte LCD in 3MUX has 9 segments per digit word table required for displayed characters Load segment information to temporary mem Ry 0000 Obch Oagd Oyfe Ry 0000 bchO 0 Ry 000b ch0a fe00 Ry 00bc hOag dOyf e000 Ry Obch Oagd Oyfe 0000 write y f of Digit ntl LowByte Ry Oyfe 0000 Obch Oagd write h a 9 otf Digit 1 HighByte isplays 0 isplays 1 displays F Liquid Crystal Display Drive 16 21 Code Examples 16 3 4 Example Code for Four MUX 1 3 Bias LCD The 4 16 22 lt TM lt lt EQU All ei one di EQU EQU EQU EQU EQU EQU EQU L UX rate is the most easy to handle display rate ght segments of a digit can often be located in splay memory byte 080h 040 020 001 002 008 004 010 Pp YP 23023 2 SDigit of register Rx should be displayed The Table represents the on segments according to the lt gt lt content of R
104. SPI Mode USART Peripheral Interface UART Mode 13 15 Control and Status Registers 13 5 1 USART Control Register UOCTL U1CTL The information stored in the USART control register UOCTL for USARTO and U1CTL for USART1 shown in Figure 13 16 determines the basic operation of the USART module The register bits select the communications protocol communication format and parity bit All bits must be programmed according to the selected mode before resetting the SWRST bit to disable the reset Figure 13 16 USART Control E n UOCTL U1CTL 18 16 UOCTL 070h U1CTL 078h Bit 0 n 5 w 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 The USART state machines and operating flags are initialized to the reset condition URXIFG URXIE UTXIE 0 UTXIFG 1 if the software reset bit is set Until the SWRST bit is reset all affected logic is held in the reset state This implies that after a system reset the USART must be reenabled by resetting this bit The receive and transmit enable flags URXE and UTXE are not altered by SWRST The SWRST bit resets the following bits and flags URXIE UTXIE URXIFG RXWAKE TXWAKE RXERR PE and FE The SWRST bit sets the following bits UTXIFG TXEPT 7 Note The USART initialization sequence should be Initialize per application requirements while leaving SWRST 1 Clear SWRST Enable interrupts if desired Bit 1 Bit 2 Multiprocessor mode addr
105. SX ds Bit7 Bit8 Btlb The status bit is affected The status bit is not affected 0 The status bit is cleared 1 The status bit is set All addressing modes are possible for the CALL instruction If the symbolic mode ADDRESS the immediate mode N the absolute mode amp EDE or the indexed mode X RN is used the word that follows contains the address information 5 18 Instruction Set Overview 5 3 3 Conditional Jumps Conditional jumps support program branching relative to the program counter The possible jump range is from 511 to 512 words relative to the program counter state of the jump instruction The 10 bit program counter offset value is treated as a signed 10 bit value that is doubled and added to the program counter None of the jump instructions affect the status bits The instruction code fetch and the program counter increment technique end with the formula Figure 5 9 shows the conditional jump instruction format Figure 5 9 Conditional Jump Instruction Format 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Table 5 17 describes these conditional jump instructions Table 5 19 Conditional Jump Instructions Mnemonic S Reg D Reg Operation JEQ JZ Label Jump to label if zero bit is set JNE JNZ Label Jump to label if zero bit is reset JC Label Jump to label if carry bit is set JNC Label Jump to label if carry bit is reset JN Label Jump to label if negative bit is set JGE Label Jump to label if
106. Sn 1 Sn 28 4229 15d 15 159 15 29 430 15h 15c 156 15 COMO 4 31 COM1 4 32 COM1 COM2 33 2 COM3 4 34 COM3 16 18 16 3 Code Examples Code Examples Code examples for the four modes follow 16 3 1 Example Code for Static LCD All eight segments of a digit are often located in four display memory bytes with the static display method a EQU 001h b EQU 010h EQU 002h d EQU 020h e EQU 004h f EQU 040h g EQU 008h h EQU 080h The register content of Rx should be displayed The Table represents the on segments according to the content of Rx OV B Table Rx RY Load segment information into temporary memory Ry 0000 0000 hfdb geca OV B Ry amp LCDn Note All bits of an LCD memory byte are written RRA Ry Ry 0000 0000 Ohfd bgec OV B Ry amp LCDn 1 Note All bits of an LCD memory byte are written RRA Ry Ry 0000 0000 OOhf dbge OV B Ry amp LCDn 2 Note All bits of an LCD memory byte are written RRA Ry Ry 0000 0000 000h fdbg OV B amp LCDn 3 Note All bits of an LCD memory byte are written Table DB atb ctdtetf displays 0 DB DFC displays 1 DB Liquid Crystal Display Drive 16 19 Code Examples 16 3 2 Example Code for Two MUX 1 2 Bias LCD All eight segments of a digit are often located in two display memory bytes with the 2MUX display rate
107. Synchronous Operation 14 3 1 1 Four Pin SPI Master Mode The signal on STE is used by the active master to prevent bus conflicts with another master The STE pin is an input when the corresponding PnSEL bit in the I O registers selects the module function The master operates normally while the STE signal is high Whenever the STE signal is low for example when another device makes a request to become master the actual master reacts such that The pins that drive the SPI bus lines SIMO and UCLK are set to inputs The error bit FE and the interrupt flag URXIFG in registers UORCTL and U1RCTL respectively are set The bus conflict is then removed SIMO and UCLK do not drive the bus lines and the error flag indicates the system integrity violation to the software Pins SIMO and UCLK are forced to the input state while STE is in a low state and they return to the conditions defined by the corresponding control bits when STE returns to a high state In the three pin mode the STE input signal is not relevant 14 3 2 Slave SPI Mode The slave mode is selected when bit MM of the control register is reset and synchronous mode is selected The UCLK pin is used as the input for the serial shift clock supplied by an external master The data transfer rate is determined by this clock and not by the internal bit rate generator The data loaded into the transmit shift register through the transmit buffer UxTXBUF before the start o
108. Table 14 1 USART Interrupt Control and Enable Bits SPI Mode Receive interrupt flag URXIFG Initial state reset by PUC SWRST Receive interrupt enable URXIEt Initial state reset by PUC SWRST Receive transmit enablet USPIIEt Initial state reset by Transmit interrupt flag UTXIFG Initial state set by PUC SWRST Transmit interrupt enable UTXIEt Initial state reset by PUC SWRST t Different for UART mode see Chapter 13 Suffix 0 for USARTO and 1 for USART1 The USART receiver and transmitter operate in parallel and use the same baud rate generator in synchronous master mode In synchronous slave mode the external clock applied to UCLK is used for the receiver and the transmitter The receiver and transmitter are enabled and disabled together with the USPIIE bit 14 4 1 USART Receive Transmit Enable Bit Receive Operation The receive transmit enable bit USPIIE enables or disables collection of the bit stream on the URXD SOMI data line Disabling the USART receiver USPIIE 0 stops the receive operation after completion or stops a pending operation if no receive operation is active In synchronous mode UCLK does not shift any data into the receiver shift register 14 4 1 1 Receive Transmit Enable Bit MSP430 as Master The receive operation functions identically for three pin and four pin modes as shown in Figure 14 7 when the MSP430 USART is selected to be the SPI master USART Peripheral Interface SPI Mode
109. The destination operand is cleared Status bits are not affected RAM word TONI is cleared CLR TONI 0 Register R5 is cleared CLR R5 RAM byte TONI is cleared CLR B TONI 0 gt CLRC Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Overview Clear carry bit CLRC 0 gt BIC 1 5 The carry bit C is cleared The clear carry instruction is a word instruction N Not affected Z Not affected C Cleared V Not affected OscOff CPUOff and GIE are not affected The 16 bit decimal counter pointed to by R13 is added to a 32 bit counter pointed to by R12 CLRC C20 defines start DADD R13 0 R12 16 bit counter to low word of 32 bit counter DADC 2 R12 add carry to high word of 32 bit counter Instruction Set Description B 19 Instruction Set Overview CLRN Syntax Operation Emulation Description Status Bits Mode Bits Example SUBR SUBRET B 20 Clear negative bit CLRN 0 N or NOT src AND dst gt dst BIC 4 SR The constant 04h is inverted OFFFBh and is logically ANDed with the destination operand The result is placed into the destination The clear negative bit instruction is a word instruction N Reset to 0 7 Not affected C Not affected V Not affected OscOff CPUOff and GIE are not affected The Negative bit in the status register is cleared This avoids special tre
110. UxBRO shown in Figure 14 19 to generate the serial data stream bit timing The smallest division factor is two Figure 14 19 USART Baud Rate Select Register 7 0 mess Ce Jee gt U1BRO 07Ch rw rw rw rw rw rw rw rw 7 0 ad ad A U1BR1 07Dh rw rw rw rw rw rw rw rw Baud rate BACLK with UxBR UxBR1 UxBRO UxBR iXmi The maximum baud rate that can be selected for transmission in master mode is half of the clock input frequency of the baud rate generator In slave mode the rate is determined by the external clock applied to UCLK The modulation control register shown in Figure 14 20 is not used for serial synchronous communication It is best kept in reset mode bits mO to m7 0 Figure 14 20 USART Modulation Control Register 7 0 CE U1MCTL 07Bh rw rw rw rw rw rw rw rw 14 5 5 Receive Data Buffer UORXBUF U1RXBUF The receive data buffer UxRXBUF shown in Figure 14 21 contains previous data from the receiver shift register UxRXBUF is cleared with a SWRST signal Reading UxRXBUF resets the receive error bits and the receive interrupt flag URXIFG Figure 14 21 Receive Data Buffer VORXBUF U1RXBUF 7 0 Te TT T2 T4 T2 T U1RXBUF 07Eh rw rw rw rw rw rw rw rw The MSB of the UxRXBUF is always reset in seven bit length mode USART Peripheral Interface SPI Mode 14 19 Control and Status Registers 14 5 6 Transmit Data Buffer UOTXBUF UTTXBUF The tr
111. VcC start RL Be e cELI ra gt Brownout TH Brownout Brownout Region Region 1 0 lt gt t BOR SVS Circuit is active from VLD gt to Vcc lt gt SVSOut lt pz gt 1 0 gt t asian SVSon lt t SVSR 1 Undefined 0 a perating SVS Operating Voltage gt re gt re Voltage gt SVS Operating Range Voltage Range le Brownout Operating Voltage Range gt i Brownout Operating Voltage Range System Resets Interrupts and Operating Modes 3 5 System Reset and Initialization 3 1 2 Device Initialization After System Reset 3 6 After a device reset POR PUC combination the initial system conditions are d d pins switched to input mode I O flags are cleared as described in the Digital I O Configuration chapter Other peripherals and registers initialized as described in their respective chapters Status register is reset Program counter is loaded with address contained at reset vector location OFFFEh CPU execution begins at that address FLL begins regulation of the DCO The starts with the same default frequency target as the FLL in 3XX devices After a system reset the user program can evaluate the various flags to determine the source of the reset and take appropriate action The initial state of registers
112. WAIT 0 writing to control register FCTL1 will also end in an access violation with ACCVIFG 1 Flash Memory C 13 Flash Memory Control Registers Read access is possible at any time without restrictions The control bits of control register FCTL1 are 096h w 0 0 10 ro ro rw 0 rw 0 10 FCTL1 read 4 FCTL1 write Erase 0128h bit1 MEras 0128h bit2 WRT 0128h bit6 BLKWRT 0128h bit7 OASh gt Erase a segment 0 No segment erase is started 1 Erase of one segment is enabled The segment n to be erased is defined by a dummy write into any address within the segment The Erase bit is automatically reset when the erase operation is completed Note Instruction fetch access during erase is allowed Any other access to the flash memory during erase results in setting the ACCVIFG bit and an NMI interrupt is requested The NMI interrupt routine should handle such violations Mass erase Segment0 to Segmenin are erased together Segnmentn is highest numbered segment of the device but not the information segments 0 No erase is started 1 Erase of SegmentO to Segmentn is enabled When a dummy write into any address in SegmentO to Segmentn is executed mass erase is started The MEras bit is automatically reset when the erase operation is completed Note Instruction fetch access during mass erase is allowed Any other access to the flash memory during erase results in setting the ACCVIF
113. address following the subroutine call Status bits are not affected Instruction Set Description B 45 Instruction Set Overview RETI Syntax Operation Description Status Bits Mode Bits Example Return from interrupt RETI TOS SR SP 2 SP TOS PC SP 2 SP The status register is restored to the value at the beginning of the interrupt service routine by replacing the present SR contents with the TOS contents The stack pointer SP is incremented by two The program counter is restored to the value at the beginning of interrupt service This is the consecutive step after the interrupted program flow Restoration is performed by replacing the present PC contents with the TOS memory contents The stack pointer SP is incremented N restored from system stack Z restored from system stack C restored from system stack V restored from system stack OscOff CPUOff and GIE are restored from system stack Figure B 5 illustrates the main program interrupt Figure B 5 Main Program Interrupt B 46 PC 6 PC 4 Interrupt Request PC 2 Interrupt Accepted v gt 2 2 is Stored PC PCi Onto Stack PC 4 2 PC 6 4 8 n 4 PCi n 2 PCi n pal RLA W RLA B Syntax Operation Emulation Description Instruction Set Overview
114. also be configured to perform conversions on a sequence of channels running through the sequence once or repeatedly When performing conversions on a sequence of channels the sequence is completely definable by the user For example a possible sequence of channels could be ai a3 a1 a6 a2 etc In addition each channel may be individually configured for which reference s are to be used for the conversion Conversion results are stored in 16 conversion memory registers Each of these registers has its own configuration and control register allowing the user to select the input channel and the reference s used for the conversion result that is stored in that register Some key and unique features of the ADC12 are 200 ksps maximum conversion rate 12 bit converter with 1LSB differential nonlinearity DNL and 1LSB in tegral nonlinearity INL Lj Built in sample and hold with selectable sampling periods controlled by software via a control bit a sampling timer or by other MSP430 timers On chip dedicated RC oscillator used as an option for sample and conversion timing Integrated diode for temperature measurement Eightindividually configurable channels for conversion of external signals J Four internal channels for conversion of temperature and external references On chip reference voltages 1 5 V or 2 5 V selected by software Selectable internal or external sources for bo
115. and described in detail in the follow ing sections Table 17 2 Conversion Modes Summary CONVERSION MODE Single channel Sequence of channels Repeat single channel Repeat sequence of channels CONSEQ 00 01 10 OPERATION Single conversion from a selected channel X CstartAdd points to the conversion start address Result is in ADC12MEMx interrupt flag is ADC121FG x Channel INCH and reference voltage Sref are selected in ADC12MCTLx A sequence of channels is converted X CstartAdd points to the conversion start address The last channel in a sequence y is marked with EOS 1 ADC12MCTLx 7 all other EOS bits in ADC12MCTLx ADC12MCTL x 1 ADC12MCTL y 1 are reset Result is in ADC12MEMx ADC12MEM x 1 ADC12MEMy Interrupt flags are ADC12IFG x ADC12IFG x 1 ADC12IFG y More than one sequence is possible Channel INCH and reference voltage Sref are selected in ADC12MCTLx The conversion of one single channel is permanently repeated until repeat is off or ENC is reset x CstartAdd points to the conversion start address Result is in ADC12MEMx interrupt flag is ADC121FG x Channel INCH and reference voltage Sref are selected in ADC12MCTLx The conversion of a sequence of channels is permanently repeated until repeat is off or ENC is reset x CstartAdd points to the conversion start address The last channel in a sequence y is marked with EOS 1 ADC12MCTL 7 all other EOS
116. and peripherals is discussed in each applicable section of this manual Each register is shown with a key indicating the accessibility of the register and the initial condition for example rw 0 or rw 0 In these examples the r indicates read the w indicates write and the value after the dash indicates the initial condition If the value is in parenthesis the initial condition takes effect only after a POR a PUC alone will not effect the bit s If the value is not in parenthesis it takes effect after a PUC alone or after a POR PUC combination Some examples follow Type Description rw 0 Read write reset with POR rw 0 Read write reset with POR or PUC r 1 Read only set with POR or PUC r Read only no initial state w Write only no initial state Global Interrupt Structure 3 2 Global Interrupt Structure There are three types of interrupts System reset Maskable Non maskable System reset POR PUC is discussed in section 3 1 Maskable interrupts are caused by A Watchdog Timer overflow if timer mode is selected Other modules with interrupt capability Non maskable interrupts are not masked by the general interrupt enable bit GIE but are individually enabled or disabled by an individual interrupt enable bit When a non maskable interrupt is accepted the corresponding interrupt enable bit is automatically reset therefore disabling the interrupt for execution of the interrupt service r
117. bit 1 Error 6 Stop bit 2 Error 6 BRCLK Pag rate x 1 x UxBR 2 2 x 100 5 08 pag rale x 1 x UxBR 2 3 100 0 29 rate y 1 x UxBR 3 4 x 100 2 83 1 x UxBR 3 5 100 1 95 pag rate x 5 1 x UxBR 4 6 x 100 0 59 Dina 1 x UxBR 5 7 100 3 13 1 x UxBR 5 8 100 1 66 rate x 8 1 UxBR i e x 100 0 88 1 x UxBR 7 10 x 100 3 42 Be x 10 1 x UxBR 7 11 x 100 1 37 x 11 1 x UxBR 8 12 100 1 17 Baud Rate Considerations 13 7 2 Typical Baud Rates and Errors The standard baud rate data needed for the baud rate registers and the modulation register are listed in Table 13 6 for the 32 768 Hz watch crystal ACLK and MCLK assumed to be 32 times the ACLK frequency The error listed is calculated for the transmit and receive paths In addition to the error for the receive operation the synchronization error must be considered Table 13 6 Commonly Used Baud Rates Baud Rate Data and Errors Baud Rate 75 110 150 300 600 1200 2400 4800 9600 19 200 38 400 76 800 115 200 Divide by MCLK 13 981 9532 51 6990 5 3495 25 1747 63 873 81 436 91 218 45 109 23 54 61 27 31 13 65 9 10 UxBR1 UxBRO ACLK 32 768 Hz MCLK 1 048 576 Hz pec Max RX RX UxMCTL SR 96 Error 96 Eno 96 UxBR1 UxBRO UxMCTL En E
118. bit can be used to configure the converter to perform the successive conver sions automatically and as quickly as possible If MSC 0 then a rising edge of the SHI signal is required to trigger each sample and conversion regardless of what mode the converter is in When MSC 1 and gt 0 the first rising edge of the SHI signal triggers the first conversion but successive conversions are triggered automatically as soon as the prior conversion is completed Additional rising edges on SHI are ignored until the sequence is completed or until the ENC bit is toggled depending on mode The function of the ENC bit is unchanged when using the MSC bit See Figures 17 23 and 17 24 ADC12 17 27 Sampling Figure 17 23 4 SAMPCON Lo SHP ADC12CLK SHTO SHT1 r Sampling Timer Use of MSC Bit With Nonrepeated Modes SHI ENC SHI S Ay Single channel
119. bit multiprocessor mode the address bit of a character can be controlled by writing to the TXWake bit The value of the TXWake bit is loaded into the address bit of that character each time a character is transferred from transmit buffer UxTXBUF to the transmitter The TXWake bit is then cleared by the USART 18 10 Interrupt and Enable Functions 13 4 Interrupt and Enable Functions The USART peripheral interface serves two main interrupt sources for transmission and reception Two interrupt vectors serve receive and transmit events The interrupt control bits and flags and enable bits of the USART peripheral interface are located in the SFR registers They are discussed in Table 13 1 See the peripheral file map in Appendix A for the exact bit locations Table 13 1 USART Interrupt Control and Enable Bits UART Mode Receive interrupt flag URXIFG Initial state reset by PUC SWRST Receive interrupt enable URXIEt Initial state reset by PUC SWRST Receive enablet URXEt Initial state reset by PUC Transmit interrupt flag UTXIFGt Initial state set by PUC SWRST Transmit interrupt enable UTXIEt Initial state reset PUC SWRST Transmit enablet UTXEt Initial state reset by 1 Different for SPI mode see Chapter 14 t Suffix 0 for USARTO and 1 for USART1 The USART receiver and transmitter operate independently but use the same baud rate 13 4 1 USART Receive Enable Bit The receive enable bit URXE shown in Figure
120. clock source selections Table 11 6 Clock Source Selection SSEL1 SSELO O PSignal Comment 0 0 TACLK See data sheet device description 0 1 ACLK Auxiliary clock ACLK is used 1 0 SMCLK Peripheral module clock SMCLK 1 1 INCLK See device description in data sheet Bits 10 to 15 Unused eee Note Changing Timer_A Control Bits If the timer operation is modified by the control bits in the TACTL register the timer should be halted during this modification Critical modifications are the input select bits input divider bits and the timer clear bit Asynchronous clocks input clock and system clock can result in race conditions where the timer reacts unpredictably The recommended instruction flow is 1 Modify the control register and stop the timer 2 Start the timer operation For example MOV 01C6 amp TACTL ACLK 8 timer stopped timer cleared BIS 10h amp TACTL Start timer with up mode 11 24 Timer A Registers 11 5 2 Timer A Register TAR The TAR register is the value of the timer Figure 11 28 TAR Register 15 0 Timer Val 170h imer Value rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw O rw 0 rw 0 rw 0 rw 0 rw 0 rw O rw 0 rw 0 rw 0 cac ttc Note Modifying Timer A Register TAR When ACLK or the external clock TACLK or INCLK is selected for the timer clock any write to timer register TAR should occur while the timer is not operating otherwise the re
121. contain an extra bit used as an address indicator The first character in a block of data carries an address bit which indicates that the character is an address The RXWake bit is set when a received character is an address character It is transferred into the receive buffer receive conditions are true Usually if the USART URXWIE bit is set data characters are assembled by the receiver but are not transferred to the receiver buffer UXRXBUF nor are interrupts generated When a character that has an address bit set is received the receiver is temporarily activated to transfer the character to UXRXBUF and to set the URXIFG Error status flags are set as applicable The application software processes the succeeding operation to optimize resource handling or reduce current consumption The application software can validate the received address If there is a match the processor can read the remainder of the data block If there is not a match the processor waits for the next address character to arrive USART Peripheral Interface UART Mode 13 9 Asynchronous Operation Figure 13 11 Adaress Bit Multiprocessor Format e Block of Frames SSSR EE tret Ge Fd I S ER pe Idle Periods of No Significance pere TXD RXD Expanded UTXD URXD First Frame Within Block ADDR DATA Bit Is O Is an Address The for Data Within Block ADDR DATA Bit Is 1 Idle Time Is of No Significance In the address
122. content of compare latch TBCLO as shown in Figure 12 5 When the timer value and the value of compare latch TBCLO are equal or if the timer value is greater than the TBCLO value the timer restarts counting from zero Figure 12 5 Timer Up Mode TBR max TBCLO Oh Flag CCIFGO is set when the timer equals the TBCLO value The TBIFG flag is set when the timer counts from TBCLO to zero All interrupt flags are set independently of the corresponding interrupt enable bit but an interrupt is requested only if the corresponding interrupt enable bit and the GIE bit are set Figure 12 6 shows the flag set cycle Figure 12 6 Up Mode Flag Setting Timer Clock Timer Set Flag TBIFG Set Flag CCIFGO 12 8 Timer Modes 12 3 2 1 Timer in Up Mode Changing the Period Register TBCLO Value Immediate Mode for TBCLO Changing the timer period register TBCLO while the timer is running and when the transfer mode from TBCCRO is immediate can be a little tricky When the new period is greater than or equal to the old period the timer simply counts up to the new period and no special attention is required see Figure 12 7 However when the new period is less than the old period the phase of the timer clock during the TBCLO update affects how the timer reacts to the new period If the new smaller period is transferred from TBCCRO to TBCLO during a high phase of the timer clock then the timer rolls to zero or begins counting down
123. continuous mode can be used to generate time intervals for the application software Each time an interval is completed an interrupt can be generated In the interrupt service routine of this event the time until the next event is added to capture compare register TBCCRx and subsequently compare latch TBCLx as shown in Figure 12 11 Up to seven independent time events can be generated using all seven capture compare blocks Figure 12 11 Output Unit in Continuous Mode for Time Intervals TBCLOf TBCLOI TBCLOe TBCLOk TBCLOd TBCLOj TBCLOc TBCLOi TBCLOb TBCLOh TBCLOa Oh TBR max Interrupt Events Time intervals can be produced with other modes as well where capture compare block 0 is used to determine the period Their handling is more complex since the sum of the old TBCCRx data and the new period can be higher than the TBCLO value When the sum TBCCRxold plus At is greater than the TBCLO data the old TBCCRO value must be subtracted to obtain the correct time interval Timer B 12 11 Timer Modes 12 3 4 Timer Up Down Mode The up down mode is used if the timer period must be different from the TBR max clock cycles and if symmetrical pulse waveform generation is needed In up down mode the timer counts up to the content of compare latch TBCLO then back down to zero as shown in Figure 12 12 The period is twice the value in the TBCLO latch Note If TBCLO g
124. control Special function 4 4 3 Peripheral Modules Special Function Registers SFRs The system configuration and the individual reaction of the peripheral modules to the processor operation is configured in the SFRs as described in Table 4 3 The SFRs are located in the lower address range and are organized by bytes SFRs must be accessed using byte instructions only Memory 4 9 RAM and Peripheral Organization Table 4 3 Special Function Register Address Map 4 10 Address Data Bus 7 0 000Fh Not yet defined or implemented 000E o00Ch 0008 000A 0009h 0008h 0007h 0006h 0005 0004h 0003h 0002h Interrupt flag reg 1 IFG1 x 0001h 0000h The system power consumption is influenced by the number of enabled modules and their functions Disabling a module from the actual operation mode reduces power consumption while other parts of the controller remain fully active unused pins must be tied appropriately or power consumption will increase see Basic Hints for Low Power Applications in Section 3 6 5 16 Bit CPU The MSP430 von Neumann architecture has RAM code memory and peripherals in one address space both using a single address and data bus This allows using the same instruction to access either RAM code memory or peripherals and also allows code execution from RAM Topic Page Gel CPU Registers 5 5 2 5 21 Addressing Modes 5 6 5 3 Instruction Set Overview
125. direction change does not modify the output buffer contents 8 3 1 3 Direction Registers The direction registers contain eight independent bits that define the direction of each I O pin All bits are reset by the signal When Bit 0 The port pin is switched to input direction Bit 1 The port pin is switched to output direction 8 10 Ports P3 P4 P5 P6 8 3 1 4 Function Select Registers PnSEL Ports P3 P6 pins are often multiplexed with other peripheral modules to reduce overall pin count on MSP430 devices see the specific device data sheet to determine which other peripherals also use the device pins Control registers PnSEL are used to select the desired pin function O port or other peripheral module Each register contains eight bits corresponding to each pin and each pin s function is individually selectable All bits in these registers are reset by the PUC signal The bit definitions are Bit 0 Port function is selected for the pin Bit 1 Other peripheral module function is selected for the pin TE MMM Note Function Select With PnSEL Registers The interrupt edge select circuitry is disabled if control bit PnSEL x is set Therefore the input signal can no longer generate an interrupt LLLLLSS A X A OA M A When a po
126. dst Rotate left arithmetically ADD B dst dst CLR W Clear destination MOV 0 dst CLRN Clear negative bit 4 SR CLRZ Clear zero bit BIC 2 SR POP dst from stack MOV SP dst SETN Set negative bit SR SETZ Set zero bit BIS 2 SR 5 20 Table 5 18 Emulated Instructions Continued Mnemonic Description Data Instructions common use continued TSTLW TST B dst dst Test destination Test destination Program Flow Instructions BR DINT EINT NOP RET dst Branch to Disable interrupt Enable interrupt No operation Return from subroutine 5 3 5 Miscellaneous V Status Bits N Instruction Set Overview Emulation CMP CMP B MOV BIC BIS MOV MOV 0 dst 0 dst dst PC 8 SR 8 SR 0h 0h SP PC Instructions without operands such as CPUOff are not provided Their functions are switched on or off by setting or clearing the function bits in the status register or the appropriate I O register Other functions are emulated using dual operand instructions Some examples are as follows BIS 28h SR BIS 18h SR BIC P1DIRO amp P1DIR Enter OscOff mode t Enable general interrupt Enter CPUOff mode Enable general interrupt GIE Switch port P1 0 to input direction 16 Bit CPU 5 21 Instruction 5 4 Instruction The instruction map in Figure 5 10 shows the encoding of the instructions There is room for mor
127. for speed and data throughput despite conflicting needs for ultralow power Minimization of individual current consumption Limitation of the activity state to the minimum required by the use of low power modes There are four bits that control the CPU and the system clock generator CPUOff OscOff SCGO and SCG1 These four bits support discontinuous active mode AM requests to limit the time period of the full operating mode and are located in the status register The major advantage of including the operating mode bits in the status register is that the present state of the operating condition is saved onto the stack during an interrupt service request As long as the stored status register information is not altered the processor continues after RETI with the same operating mode as before the interrupt event Another program flow may be selected by manipulating the data stored on the stack or the stack pointer Being able to access the stack and stack pointer with the instruction set allows the program structures to be individually optimized as illustrated in the following program flow Enter interrupt routine The interrupt routine is entered and processed if an enabled interrupt awakens the MSP430 B TheSRandPC are stored on the stack with the content present at the interrupt event B Subsequently the operation mode control bits OscOff SCG1 and CPUOff are cleared automatically in the status register Return
128. generated by different events in the clock system Crystal oscillator LFXT1 oscillator XT2 in 43x and 44x families and the can set an oscillator fault interrupt flag The oscillator fault signal is triggered if the 5 MSB 29 25 DCO control taps in the SCFI1 register are equal to 0 or greater than or equal to 28h The oscillator fault signal is also triggered if the LFXT1 LF or HF mode or the XT2 oscillator is not running stops running after being operational or restarts Interrupt Processing running also from off mode Note that a PUC signal triggers an oscillator fault because the switches the 5 29 25 DCO control taps to 0 The oscillator fault signal can be enabled to generate an NMI by bit IE1 1 in the SFRs The interrupt flag IFG1 1 in the SFRs can then be tested by the interrupt service routine to determine if the NMI was caused by an oscillator fault See Chapter 7 for more details on the operation of the DCO oscillator the FLL and the crystal oscillators 3 4 Interrupt Processing The MSP430 programmable interrupt structure allows flexible on chip and external interrupt configurations to meet real time interrupt driven system requirements Interrupts may be initiated by the processor s operating conditions such as watchdog overflow or by peripheral modules or external events Each interrupt source can be disabled individually by an interrupt enable bit or all maskable interrupts can be disable
129. highly transparent instruction formats Using these formats core instructions are implemented into the hardware Emulated instructions are also supported by the assembler Emulated instructions use the core instructions with the built in constant generators CG1 and CG2 and or the program counter PC The core and emulated instructions are described in detail in this section The emulated instruction mnemonics are listed with examples Program memory words used by an instruction vary from one to three words depending on the combination of addressing modes Topic Page B 1 Instruction Set Overview B 2 B 2 Instruction Set Description B 8 B 1 Instruction Set Overview B 1 Instruction Set Overview The following list gives an overview of the instruction set Status Bits VNZC ADC W ADC B dst dst C dst S oW ium ADD W ADD B src dst src dst dst A ADDC W ADDC B src dst src dst C dst AND W AND B src dst src and dst dst BIC W BIC B src dst not src and dst dst DAE BIS W BIS B src dst src or dst dst SS ees BIT W BIT B src dst src and dst Qe ce ot BR dst Branch to CALL dst PC 2 stack dst CLR W CLR B dst Clear destination CLRC Clear carry bit 0 CLRN Clear negative bit 0 CLRZ Clear zero bit 0 CMP W CMP B src dst dst src
130. if an arithmetic overflow occurs otherwise reset OscOff CPUOff and GIE are not affected R5 and R6 are compared If they are equal the program continues at the label EQUAL CMP R5 R6 R5 R6 JEQ EQUAL YES JUMP Two RAM blocks are compared If they are not equal the program branches to the label ERROR MOV NUM R5 number of words to be compared L 1 amp BLOCK1 amp BLOCK2 Are Words equal JNZ ERROR No branch to ERROR DEC R5 Are all words compared JNZ L 1 No another compare The RAM bytes addressed by EDE and TONI are compared If they are equal the program continues at the label EQUAL EDE TONI MEM EDE MEM TONI JEQ EQUAL YES JUMP DADC W DADC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Instruction Set Overview Add carry decimally to destination Add carry decimally to destination DADC dst DADC W src dst DADC B dst dst C dst decimally DADD 0 dst DADD B 0 dst The carry bit C is added decimally to the destination N Set if MSB is 1 Z Set if dst is 0 reset otherwise C Set if destination increments from 9999 to 0000 reset otherwise Set if destination increments from 99 to 00 reset otherwise V Undefined OscOff CPUOff and GIE are not affected The four digit decimal number contained in 5 is added to an eight digit deci mal number pointed to by R8 CLRC Reset carry
131. inputs of the comparator are exchanged This is used to measure or compensate for the offset of the comparator Comparator A Control Registers 15 3 2 Comparator A Control Register CACTL2 The control register CACTL2 is shown and described below CACTL2 05Ah CAF bit P2CAQ bit2 2 1 bit3 Bits 4 7 7 0 CACTL CACTL CACTL CACTL rw 0 CAOUT bit0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 The comparator output Writing to this bit for example when writing a new register value has no affect or negative impact The comparator output filter is bypassed CAF 0 or switched into the output path CAF 1 Pin to CAO 0 The external pin signal is not connected to the Comparator_A 1 The external pin signal is connected to the Comparator A Pin to CA1 0 The external pin signal is not connected to the Comparator A 1 The external pin signal is connected to the Comparator A See device data sheet for implementation Comparator A 15 7 Comparator A Control Registers 15 3 3 Comparator A Port Disable Register CAPD 15 8 Typically the comparator input and output functions are multiplexed with digital I O port pins to save pin count on a device Also slope A D applications often utilize multiple digital ports for charging and discharging to provide multiple channels of slope A D conversion In these multichannel applications a useful feature of the digital I O pins is
132. interrupt enable bit is set Capture overflow flag COV Compare mode selected CAP 0 Capture signal generation is reset No compare event will set COV bit Capture mode selected CAP 1 The overflow flag COV is set if a second capture is performed before the first capture value is read The overflow flag must be reset with software It is not reset by reading the capture value The OUTx bit determines the value of the OUTx signal if the output mode is 0 Capture compare input signal CCIx The selected input signal CCIxA CCIxB or GND can be read by this bit See Figure 11 18 Interrupt enable CCIEx Enables or disables the interrupt request signal of capture compare block x Note that the GIE bit must also be set to enable the interrupt 0 Interrupt disabled 1 Interrupt enabled Output mode select bits Table 11 7 describes the output mode selections Timer A Registers Table 11 7 Capture Compare Control Register Output Mode Bit Value Output Mode Description 0 Output only The OUTx signal reflects the value of the OUTx bit 1 Set EQUXx sets OUTx 2 PWM EQUx toggles OUTx EQUO resets OUTx toggle reset 3 PWM set reset EQUx sets OUTx EQUO resets OUTx 4 Toggle EQUx toggles OUTx signal 5 Reset EQUx resets OUTx 6 PWM EQUx toggles EQUO sets OUTx toggle set 7 PWM reset set EQUx resets OUTx EQUO sets OUTx Note OUTx updates with rising edge of timer clock for all modes except mode
133. is set BTCNT1 is held if the hold and DIV bits are set Bit 7 The SSEL and DIV bits select the frequency source for BTCNT2 as described in Table 10 2 Basic Timer 10 3 Basic Timer1 Table 10 2 BTCNT2 Input Frequency Sources SSEL DIV CLK2 0 0 ACLK 0 1 ACLK 256 1 0 SMCLK 1 1 ACLK 256 Figure 10 3 Basic Timer1 Control Register Function 7 0 BICTE SSEL Hol DIV FRFQ1 FRFQO IP2 IP1 040h od nw rw rw rw rw rw rw rw Interrupt Frequenc foLk2 2 foLk2 2 foLk2 8 foLk2 16 fci ko 32 fci ko 64 fci 2 128 fci 2 256 facLk 32 fAcL 64 128 fAcLK 256 10 1 1 2 Basic Timer1 Counter BTCNT1 The Basic Timer1 counter BTCNT1 shown in Figure 10 4 divides the auxiliary clock ACLK The frame frequency for the LCD drive is selected from four outputs of the counter s bits The output of the most significant bit can be used for the clock input to the second counter BTCNT2 The value of bits Q0 to Q7 can be read and the software can write to bits to Q7 Figure 10 4 Basic Timer1 Counter BTCNT1 7 0 BTCNT1 w rw rw wo rw rw rw rw r 10 4 Basic 10 1 1 3 Basic Timer1 Counter BTCNT2 The Basic Timer1 counter BTCNT2 shown in Figure 10 5 divides the input clock frequency The input clock source can be SMCLK ACLK or ACLK 256 The interrupt period can be se
134. non maskable interrupt input Bit 6 If the NMI function is selected this bit selects the activating edge of the RST NMI input It is cleared by the PUC signal NMIES 2 0 A rising edge triggers an NMI interrupt NMIES 1 A falling edge triggers an NMI interrupt CAUTION Changing the NMIES bit with software can generate an NMI interrupt Bit 7 This bit stops the operation of the watchdog counter The clock multiplexer is disabled and the counter stops incrementing It holds the last value until the hold bit is reset and the operation continues It is cleared by the PUC signal HOLD 0 The WDT is fully active HOLD 1 The clock multiplexer and counter are stopped 9 1 1 1 Accessing the WDTCTL Watchdog Timer Control Register The WDTCTL register can be read or written to As illustrated in Figure 9 3 WDTCTL can be read without the use of a password A read access is performed by accessing word address 0120h The low byte contains the value of WDTCTL The value of the high byte is always read as 069h Figure 9 3 Reading WDTCTL 15 8 7 0 WDTCTL 0120h 0 1 1 0 1 0 0 1 Read Data rrr r rr rr rw x w Write access to WDTCTL illustrated in Figure 9 4 is only possible using the correct high byte password To change register WDTCTL write to word address 0120h The low byte contains the data to write to WDTCTL The high byte is the password which is 05Ah A system reset PUC is generated if any value other than 05Ah is w
135. not multiples of the standard baud rates allowing the protocol to run at maximum baud rate with a watch crystal 82 768 Hz This technique results in power advantages because sophisticated MSP430 low power operations are possible USART Peripheral Interface UART Mode 13 5 Asynchronous Operation Figure 13 6 MSP430 Baud Generation Example for n or n 1 Clock Periods 0 7 UxBRO 1 7 SSEL1 SSELO UCLKI o o 9 o SMCLK o SMCLK o o 34 0 7 UxBR1 Start 8 15 BRCLK L 15 Bit Prescaler Divider Q1 Q15 Compare 0 or 1 Shift Modulation Register Data lt Shift out Shift in Pr ee BITCLK m 0 7 Modulation Register UOMCTL or UTMCTL H Start L BRCLK Counter my2 1102 11 022 1 1 n 2 1 21 1 1 2 1 2 2 1 0 2 n 2 1 1 1 az H BITCLK n Even m 0 Divide By n Odd or n Even m 1 1 The modulation register LSB is first used for modulation which begins with the start bit A set modulation bit increases the division factor by one Example 13 1 4800 Baud Assuming a clock frequency of 32 768 Hz for the BRCLK signal and a required baud rate of 4800 the division factor is 6 83 The baud rate generation in the MSP430 USART uses a factor of six plus a modulation register load of 6Fh 0110 1111 The divider runs the following seq
136. of several major blocks These blocks are described in this section 15 2 1 Input Analog Switches The input analog switches connect or disconnect the comparator input terminals to associated port pins using the P2CAO and P2CA1 control bits Both terminal inputs can be controlled individually 2 and P2CA1 allow L Application of an external signalto the and terminals of the comparator or Routing of an internal reference voltage if applied to a comparator input terminal as an output on an associated port pin In this way the internal reference voltage can be used to bias external circuitry Internally the input switch is constructed as a T switch to suppress distortion in the signal path When a comparator terminal is not connected to an external pin it should be connected to an internal reference voltage level LL Note Ensure that the comparator input terminals are connected to signal power or ground level Otherwise floating levels may cause unexpected interrupts and current consumption may increase 15 2 2 Input Multiplexer Control bit CAEX controls the input multiplexer to select which input signals are connected to the comparator s and terminals Additionally when the comparator terminals are exchanged the output signal from the comparator is inverted This allows the user to determine or compensate for the c
137. one CONSEQ bit per instruction For example to change from mode 0 to mode 3 while the converter is actively running the following instructions could be used BIS CONSEQ_0 amp ADC12CTL1 Example 0 3 first step is0 1 BIS CONSEQ_1 amp ADC12CTL1 second step is 1 gt 3 Acceptable sequence modifications are 0 gt 1 05 2 1 50 153 290 2 gt 3 3 1 and3 2 The ADC12 incorporates two bits ADC12ON and REFON for power savings ADC120ON turns on the A D core and REFON turns on the reference genera tor Each bit is individually controllable by software The ADC12 is turned off completely if both bits are reset The ADC12 registers are not affected by either of these bits and can be accessed and modified at any time see the ADC12 Control Registers section Note however that ADC12ON and REFON may only be modified if ENC 0 Additionally other ADC12 functions are automatically switched on and off as needed if possible to realize additional power savings even while the ADC12 is running Caution Do not power down the converter or the reference generator while the converter is active Conversion results will be false It is possible to disable the reference generator and the ADC12 by resetting bits ADC12ON and REFON before an active conversion or sequence of conversions has completed For example if the conversion mode is set to sequence of channels and software resets the ENC bit im
138. overhead for different interrupt sources includes interrupt latency and return from interrupt cycles but not the task handling itself as described Capture compare block TBCCRO 11 cycles Capture compare blocks TBCCR1 to TBCCR6 16 cycles Li Timer overflow TBIFG 14 cycles 12 6 4 5 Timing Limits 12 40 With the TBIV register and the previous software the shortest repetitive time distance tcRmin between two events using a compare register is tcRmin ttaskmax 16 X tcycle With ttaskmax Maximum worst case time to perform the task during the interrupt routine for example incrementing a counter tcycle Cycle time of the system frequency MCLK The shortest repetitive time distance tcLmin between two events using capture register is ttaskmax 16 X Chapter 13 USART Peripheral Interface UART Mode The universal synchronous asynchronous receive transmit USART serial communication peripheral supports two serial modes with one hardware configuration These modes shift a serial bit stream in and out of the MSP430 at a programmed rate or at a rate defined by an external clock The first mode is the universal asynchronous receive transmit UART communication protocol the second is the serial peripheral interface SPI protocol discussed in Chapter 14 Bit SYNC in control register UCTL UOCTL for USARTO or U1CTL for USART1 selects the required mode SYNC 0 UART asynchronous m
139. presented by the internal effective RC Internally the analog inputs see an effective maximum nominal RC of a 30 pF C array capacitor in series with a 2 kO resistor Ron of switches However if the external dynamic source impedance is large then these transients may not settle within the allocated sampling time to ensure 12 bits of accuracy It is imperative that the proper sample timing be used for accurate conver sions The next section discusses how to calculate the sample timing 17 7 5 1 Simplified Sample Timing Analysis Using the equivalent circuit shown in Figure 17 25 the time required to charge the analog input capacitance from 0 to VS within 1 2 LSB can be derived as follows Figure 17 25 Equivalent Circuit MSP430 V Input voltage at pin Ax Zi Vg External driving source voltage Vc Rg Source resistance must be real at input frequency Zi Input resistance MUX on resistance Ci Input capacitance TS Vc Capacitance charging voltage 11 The capacitance charging voltage is given by _ M tc 1 Vo Vgl 1 x 1 Where Ri Zi te Cycle time The input impedance Zi is 1 at 3 0 V and is higher 2 at 1 8 V The final voltage to 1 2 LSB is given by S 2 Vc 1 2LSB Vs 8192 Equating equation 1 to equation 2 and solving for cycle time tc gives V NE T X _ CN 3 Ya a xol ADC12 17 29 ADC12 Control Registers and the time
140. request service is started or a character is written to the UxTXBUF This flag activates a transmitter interrupt if bits USPIIE and GIE are set The UTXIFG is set after a system reset PUC signal or removal of SWRST Figure 14 14 Transmit Interrupt Operation 14 14 USPIIE 1 1 pose PUC or SWRST Request _ UTXIFG Interrupt Service Character Moved From Buffer to Shift Register SWRST UxTXBUF Written Into Transmit Shift Register IRQA The transmit interrupt enable bit UTXIE controls the ability of the UTXIFG to request an interrupt but does not prevent the UTXIFG flag from being set The USPIIE is reset with a PUC signal or a SWRST The UTXIFG bit is set after a system reset PUC signal or a SWRST but the USPIIE bit is resetto ensure full interrupt control capability Control and Status Registers 14 5 Control and Status Registers The USART registers shown in Table 14 2 are byte structured and should be accessed using byte instructions Table 14 2 USAHT Control and Status Registers Register Address Initial State USART control UOCTL Read write 070h See Section 14 5 1 Transmit control UOCTL Read write 07th See Section 14 5 2 Receive control UORCTL Read write 072h See Section 14 5 3 Modulation control UOMCTL Read write 073h Unchanged Baud rate 0 UOBRO Read write 074h Unchanged Baud rate 1 UOBR1 Read write 075h Unchanged Receive buffer UORXBUF Read write 076h Unchanged
141. reset automatically After the RETI instruction of the interrupt service routine is executed the CCIFG2 flag will generate another interrupt MM ee OO See Note Writing to Read Only Register TAIV Register TAIV should not be written to If a write operation to TAIV is performed the interrupt flag of the highest pending interrupt is reset Therefore the requesting interrupt event is missed Additionally writing to this read only register results in increased current consumption as long as the write operation is active 11 5 4 3 Timer Interrupt Vector Register Software Example 11 30 The following software example describes the use of vector word TAIV and the handling overhead The numbers at the right margin show the necessary cycles for every instruction The example is written for continuous mode the time difference to the next interrupt is added to the corresponding compare register Software example for the interrupt part Cycles Interrupt handler for Capture Compare Module 0 The interrupt flag CCIFGO is reset automatically IMMODO ties Start of handler Interrupt latency 6 RETI 5 Interrupt handler for Capture Compare Modules 1 to 4 The interrupt flags CCIFGx and TAIFG are reset by hardware Only the flag with the highest priority responsible for the interrupt vector word is reset TIM HND Interrupt latency 6 ADD amp TAIV PC Add offset to Jump table 3
142. resistive elements are compared using a capacitor charge discharge cycle as shown in Figure 15 8 This is based on a ratiometric conversion principle as the ratio of two capacitor discharge times is compared Absolute Vcc and the actual capacitor value are not critical as the ratiometric principle cancels these values out Vcc and the capacitor value should simply remain constant during the conversion V R meas X C x In v Nmeas E CC N V rer R eX C X In va CC Nmeas _ N R ref ref Nmeas Hg X N ref Comparator A 15 11 Comparator A Applications Figure 15 8 Timing for Temperature Measurement Systems Vc Voc 0 25 x 15 12 Phase I Phase Il Phase Phase IV t gt Charge Up Discharge C gt Charge Up M Discharge gt iet tmeas gt MSP430 resources used to calculate the temperature sensed by R meas Digital Two digital outputs to charge and discharge the capacitor Port pins are set to provide a output charge a capacitor reset to discharge a capacitor and switched to high impedance including correct state of CAPD x bit when not in use One output discharges the capacitor via reference resistor R ref the other output discharges it via R meas Comparator The terminal is connected to a reference level for example 0 25 x Vcc The terminal is connected to the positive
143. sampling timer or to the SAMPCON signal under control of the ENC bit This is discussed in detail further ahead ADC12SC is a control bit located in ADC12CTLO Its value is set by software Depending on the selected sampling mode this bit allows the software to either start a sample and conversion S C cycle SHP 1 or to completely control the sampling period SHP 0 The sample signal input can be asynchronous to a conversion enable and is synchronized and enabled by the ENC bit Without synchronization the first sampling period after the ENC bit is set could be erroneous depending on where the bit is set within the cycle of the input signal In Figure 17 16 for example note that the ENC bit is set in the middle of a high pulse from the sample signal input If the sample input signal were simply passed directly to the S H the first conversion of the example would be erroneous because the first sampling period is too short ADC12 17 23 Sampling To prevent this problem synchronization logic is implemented in the sample input selection switch This ensures that the first sample and conversion cycle begins with the first rising edge of the sample input signal applied after the ENC bit is set Additionally the last sample and conversion begins with the first rising edge of the sample input signal after ENC has been reset Figure 17 16 Synchronized Sample and Conversion Signal With Enable Conversion Enable Conversion ENC
144. selected SHP 1 Possible clock sources are the internal oscillator ADC120SC ACLK MCLK and SMCLK The internal oscillator generates the ADC12OSC signal and is in the 5 MHz range see device data sheet for specifications The internal oscillator frequency will vary with individual devices supply voltage and temperature A stable clock source should be used for the conversion clock when accurate conversion timing is required Figure 17 13 The Conversion Clock ADC12CLK VRE VR 12 bit A D converter core ADC12SSEL Internal Oscillator ADC120N ADC12DIV ADC120SC ADC12CLK Divide by ACLK 1 2 3 4 5 6 7 8 MCLK SMCLK to Sample amp Hold ADC12 17 21 Sampling 17 7 Sampling The conversion starts with the falling edge of the sample signal SAMPCON see the Sampling section and Figure 17 14 Thirteen conversion clocks ADC12CLK are required to complete a conversion The conversion time is tconversion 13 x ADC12DIV fApc12CLK Where ADC12DIV is any integer from 1 to 8 The ADC12CLK frequency must not exceed the maximum and minimum frequencies specified in the data sheet Either violation may result in inaccurate conversion results Note Availability of ADC12CLK During Conversion Users mustensure thatthe clock chosen for ADC12CLK remains active until the ADC12 can complete its operation If the clock is removed while the ADC12 is active the operation can not b
145. sources FXKEY set 03300h and Watchdog FWKEY set OA500h No interrupt request may happen while the flash is programmed LOCK 0 WRT 1 Write Data to Flash Address MOV FWKEY amp FCTL3 LOCK 0 MOV FWKEY WRT amp FCTL1 Enable Write to flash MOV 123h 80FF1Eh Write a word to flash WRT 0 LOCK 1 MOV FWKEY amp FCTL1 Reset Write bit XOR s FXKEY LOCK amp FCTL3 Change Lock bit to 1 Restore or Enable Required Interrupt Sources and Enable those interrupt sources that should be accepted Watchdog Flash Memory Access JTAG and Software C 5 3 3 Example Programming Byte Sequences Into a Flash Memory Module via Software Sequences of data bytes or words can use the block write feature This reduces the programming time by about one half FXKEY set 03300h FWKEY set 0A500h FRKEY set 09600h Ensure that neither Watchdog Timer nor sinterrupts nor Low Power Modes may corrupt proper execution RAM2FLASH MOV Start_Ptr Rx MOV Ptr Ry MOV FWKEY amp FCTL3 Test Busy1 BIT BUSY amp FCTL3 JNZ Test 1 Set Pointer for Start and End Clear Lock Bit Test WAIT1 BIT WAIT amp FCTL3 Test WAIT1 JZ End Seg Write BIT 03Fh Rx JNZ Test_Wait1 Block border yes Test_Wait2 BIT WAIT amp FCTL3 JZ Test_Wait2 MOV FWKEY amp FCTL1 JMP Test_busy1 End_Seg_Write MOV FWKEY amp FCTL1 Test_Busy2 BIT BUSY amp FCTL3 JNZ Test Busy2
146. starts at the lowest tap on PUC enough time must be allowed for the DCO to settle on the proper tap for normal operation This is necessary only after or when SCFIO and SCFI1 are cleared 32 ACLK cycles are required to get from one tap to another Twenty nine taps are implemented requiring 27 x 32 ACLK cycles as the worst case for the DCO to settle on the proper tap taps 0 and 27 are not counted since OFIFG is set at these taps During initialization this time should be left prior to precise MCLK SMCLK timing During normal operation the FLL constantly adjusts the DCO requiring no special considerations 7 5 2 Adjusting the FLL Frequency User software can adjust the FLL frequency at any time by changing the N multiplier in the SCFQCTL register Also bits FN_2 FN_3 FN_4 and FN_8 are adjusted to the appropriate MCLK frequency range 7 10 FLL Operating Modes Example MCLK 64 x ACLK 2097152 bic GIE SR Disable interrupts mov b 64 1 amp SCFQTL CLK 64 ACLK DCO 0 mov b FN_2 amp SCFIO DCO centered at 2 MHz bis GIE SR Enable interrupts Example MCLK 200 x ACLK 6553600 bic GIE SR Disable interrupts bis SCGO SR Open loop f DCOCLK remains at present frequency mov b 200 2 1 amp SCFQTL MCLK 100 ACLK mov b OFh amp SCFI1 Set DCO control and modulation control bits to the lowest possible mov b D 40h FN_3 amp SCFIO DCO centered at 6 MHz D 2 MCLK 200
147. tested If it is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If N is reset the next instruction following the jump is executed Status Bits Status bits are not affected Example The result of a computation in R5 is to be subtracted from COUNT If the result is negative COUNT is to be cleared and the program continues execution in another path SUB R5 COUNT COUNT R5 COUNT JN L 1 If negative continue with COUNT 0 at PC L 1 pe Continue with COUNT20 L 1 CLR COUNT B 38 JNC JLO Syntax Operation Description Status Bits Example ERROR CONT Example Instruction Set Overview Jump if carry not set Jump if lower JNC label JNC label if C 0 PC 2 x offset gt PC if C 1 execute following instruction The status register carry bit C is tested If itis reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If C is set the next instruction following the jump is executed JNC jump if no carry lower is used for the comparison of unsigned numbers 0 to 65536 Status bits are not affected The result in R6 is added in BUFFER If an overflow occurs an error handling routine at address ERROR is used ADD R6 BUFFER BUFFER R6 BUFFER JNC CONT No carry jump to CONT Error handler start Continue with normal program flow Branch to STL2 if byte STATUS contains 1 or 0 C
148. the reference settles Once all internal and external references have settled no additional settling time is required when selecting or changing the conversion range for each channel 17 3 Analog Inputs and Multiplexer 17 3 1 Analog Multiplexer The eight external analog input channels and four internal signals are selected as the channel for conversion by the analog multiplexer Channel selection is made for each conversion memory register with the corresponding ADC12MCTLx register The input multiplexer is a break before make type shown in Figure 17 3 to reduce input to input noise injection resulting from channel switching The input multiplexer is also a T switch to minimize the coupling between channels Channels that are not selected are isolated from the A D and the intermediate node is connected to analog ground AVss so that the stray capacitance is grounded to help eliminate crosstalk Figure 17 3 Analog Multiplexer Channel 17 6 R 1000hm ADC12MCTLx 0 3 nee a ESD protection Crosstalk can exist because there is always some parasitic coupling capacitance across the switch and between switches This can take several forms such as coupling from the input to the output of an off switch or coupling from an off analog input channel to the output of an adjacent on channel For high accuracy conversions crosstalk interference should be minimized by shielding and other well known printed circuit board
149. the SAMPCON signal SHP 1 and the A D mode is chosen as repeat single channel sequence of channel or repeat sequence of channels CONSEQz0O 0 The sampling timer requires a rising edge of the SHI signal to trigger each sample and conversion 1 The first rising edge of the SHI signal triggers the sampling timer but further sample and conversion are performed automatically as soon as the prior conversion is completed without additional rising edges of SHI Additional rising edges of SHI are ignored until the sequence has completed or the ENC bit has been toggled depending on mode 17 32 ADC12 Control Registers SHTO bits Sample and hold TimeO These bits define the sample timing for 8 11 conversions whose results are stored in conversion memory registers ADC12MEMO to ADC12MEM7 The sample time is a multiple of the ADC12CLK x 4 tsample 4 X tADC12CLK X ERI OR EC ee SHT1 bits Sample and hold Time1 These bits define the sample timing for 12 15 conversions whose results are stored in conversion memory registers 12 8 to ADC12MEM15 The sample time is a multiple of the ADC12CLK x 4 tsample 4 X tADC12CLK X EEG EE EE 88 15 8 7 0 ADC12CTL1 i m CSStartAdd SHS SHP issH ADC12DIV ADC12SSEL CONSEQ 01 2 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0
150. the Switching between Conversion Modes section Conversion Modes If the conversion mode is changed after the sequence begins but before it has completed and the ENC bit is left high the sequence completes normally and the new mode takes effect after the sequence completes unless the new mode is single channel single conversion If the new mode is single channel single conversion the current sequence of channels stops proceeding when no sample and conversion is active or after an active sample and conversion is completed The original sequence may not be completed but all completed conversion results are valid See also the Switching Between Conversion Modes section If the conversion mode is changed after the sequence begins but before it has completed and the ENC bit is toggled then the original sequence completes normally and the new mode takes effect and is started after the original sequence completes unless the new mode is single channel single conversion lf the new mode is single channel single conversion then the original sequence stops when no sample and conversion is active or after an active sample and conversion is completed or when the ENC bit is reset whichever comes first Then the single conversion begins when the ENC bit is set again See also the Switching Between Conversion Modes section Figure 17 7 ENC Does Not Effect Active Sequence ENC SAMPCON and ADC128C ADC12SC reset ADC12SC set ADC12S
151. the division rate for the clock source selected by ADC12SSEL bits Oto 7 Divide selected clock source by 1 to 8 The divider s output signal name is ADC12CLK Thirteen of these clocks are required for a conversion Invert sample input signal 0 The sample input signal is not inverted 1 The sample input signal is inverted The SHP bit selects the source of the sampling signal SAMPCON to be either the output of the sampling timer or the sample input signal directly 0 SAMPCOM signal is sourced directly from the sample input signal 1 SAMPCON signal is sourced from the sampling timer The rising edge of the sample input signal triggers the sampling timer Source select for the sample input signal 0 Control bit ADC12SC is selected 1 Timer A OUT1 2 Timer B OUTO 3 Timer B OUT1 Conversion start address CStartAdd is used to define which ADC12 conversion memory register ADC12MEMx is used for a single conversion or for the first conversion in a sequence of conversions The value of CStartAdd is 0 to OFh corresponding to ADC12MEMO to ADC12MEM 15 Since there is one corresponding conversion memory control register ADC12MCTLx for each conversion memory register ADC12MEMX CStartAdd also points to the corresponding ADC12MCTLx register Warning Modifying ADC control register during active conversion Theenable conversion control bit ENC in the ADC12CTLO register protects most bits from modification during an active conver
152. the modulation bit M SCFQCTL 7 In this case the MCLK SMCLK is stabilized to N 1 x ACLK every 1024 cycles to the nearest 32 DCO taps 7 85 MCLK Stability The DCO is absolutely monotonic and the 10 bits of the frequency integrator continuously count up down by one The accuracy of MCLK SMCLK is the same as that of ACLK if the FLL is running continuously The accumulated error in MCLK SMCLK tends to zero over a long period The 10 bit FLL integrator is automatically adjusted every period of the ACLK Thus a positive frequency deviation over one ACLK period is compensated with a negative deviation over the next ACLK period Variation between MCLK SMCLK clock periods can be approximately 1096 due to the modulator mixing of DCO taps while the accumulated system clock error over longer time periods is zero FLL Clock Module 7 9 FLL Operating Modes 7 4 Oscillator Fault Detection MSP430x4xx devices have a fail safe mode when the external crystal fails The crystal fault LFOF XTS_FLL 0 the XT1OF XTS_FLL 1 or the XT2OF indicate when the crystal is not operating Additionally if the crystal fails and no ACLK signal is generated the FLL continues to count down to zero in an attempt to lock ACLK and MCLK Dx N 1 An internal oscillator fault is detected if the DCO tap moves out of the range 0 lt Ndco lt 28 that is an oscillator fault is signaled if the five bits SCFI1 7 SCFI1 3 contain one the values 0 28 29 30 or 31 An o
153. the operating mode for the shadow registers TBCLGRP 1 Three groups are selected TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 TBCL1 TBCL2 The CLLD bits in TBCCTL1 define the operating mode TBCL3 TBCL4 The CLLD bits in TBCCTL3 define the operating mode TBCL5 TBCL6 The CLLD bits in TBCCTL5 define the operating mode TBCLGRP 21 Two groups are selected TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 1 TBCL2 TBCL3 The CLLD bits in TBCCTL1 define the operating mode TBCL4 TBCL5 TBCL6 The CLLD bits in TBCCTLA define the operating mode TBCLGRP 3 One group is selected all TBCLx registers The CLLD bits in TBCCTL1 define the operating mode for all shadow registers Bit 15 Unused T TBCLGRP 2 is not possible with Timer 41x and 43x devices TBCLGRP is treated as TBCLGRP 1 Timer B 12 31 Timer B Registers ER 7 71 Note Changing Timer B Control Bits If the timer operation is modified by the control bits in the TBCTL register the timer should be halted during this modification Critical modifications are the input select bits input divider bits and the timer clear bit Asynchronous clocks input clock and system clock can result in race conditions where the timer reacts unpredictably The recommended instruction flow is 1 Modify the control register and stop the timer with one instruction 2 Start the timer operation For example MOV Z0286h amp TBCTL
154. the requesting interrupt event is missed Additionally writing to this read only register results in increased current consumption as long as the write operation is active 0 4 Timer 12 37 Timer B Registers 12 6 4 3 Timer Interrupt Vector Register Software Example Timer B7 12 38 The following software example describes the use of vector word TBIV of Timer and the handling overhead The numbers at the right margin show the necessary cycles for every instruction The example is written for continuous mode the time difference to the next interrupt is added to the corresponding compare register Software example for the interrupt part Cycles Interrupt handler for Capture Compare Module 0 The interrupt flag is reset automatically TIMMODO Lus Start of handler Interrupt latency RETI Interrupt handler for Capture Compare Modules 1 to 6 The interrupt flags CCIFGx and TBIFG are reset by hardware Only the flag with the highest priority responsible for the interrupt vector word is reset TIM HND Interrupt latency ADD amp TBIV PC Add offset to Jump table RETI Vector 0 No interrupt JMP TIMMOD1 Vector 2 Module 1 JMP TIMMOD2 Vector 4 Module 2 JMP TIMMOD3 Vector 6 Module 3 JMP TIMMOD4 Vector 8 Module 4 JMP TIMMOD5 Vector 10 Module 5 JMP TIMMOD6 Vector 12 Module 6 6 5 Module 7 Timer Overflow Handler the Timer Register is
155. the required drive signals for the segment pins and common pins can be complicated Each segment and common pin of a multiplexed LCD requires a time division multiplexed signal in order to only turn on the desired segments and to avoid having a dc voltage on any segment Some examples of segment and common signals are shown below Fortunately for the user the MSP430 creates all these signals automatically With static LCDs each segment pin drives one segment Figure 16 1 shows some example waveforms with a typical pin assignment Figure 16 1 Static Wave Form Drive COMO spe b SP2 AID 5 7 SP3 SP5 Pur n D A SP Segment Pin Vpp COMO GND Vpp Vpp Resulting Voltage for Segment COMO SP1 OV Segment Is On Vpp Resulting Voltage for Segment b COMO SP2 0 V Segment Is Off Liquid Crystal Display Drive 16 3 LCD Drive Basics With 2 MUX LCDs each segment pin drives two segments see Figure 16 2 Figure 16 2 Two MUX Wave Form Drive COM1 Vpp gt frame Vpp COM 1 A MISIMS I V3 Vpp 2 GND COMO Vpp GND STER EIER RU CUR f VDD Resulting Voltage for Vpp 2 SP4 Segment h COMO SP2 OV SP2 Segment Is On Vpp 2 SP3 Vpp SP Segment Pin VDD Resulting Voltage for Vpp 2 Segment b COM1 SP2 H HHH oV Segment Is Off Vpp 2 VDD 16 4 LCD Drive Basics With three MUX LCDs each segmen
156. two independent of the byte suffix Instruction Set Description B 43 Instruction Set Overview PUSH W PUSH B Syntax Operation Description Status Bits Mode Bits Example Example B 44 Push word onto stack Push byte onto stack PUSH src or PUSH W src PUSH B SIC SP 2 gt SP src gt SP The stack pointer is decremented by two then the source operand is moved to the RAM word addressed by the stack pointer TOS N Not affected Z Not affected C Not affected V Not affected OscOff CPUOff and GIE are not affected The contents of the status register and R8 are saved on the stack PUSH SR save status register PUSH R8 save R8 The contents of the peripheral TCDAT is saved on the stack PUSH B amp TCDAT save data from 8 bit peripheral module address TCDAT onto stack XL SO Note The System Stack Pointer The system stack pointer SP is always decremented by two independent of the byte suffix LLLL O C ACA Operation Emulation Description Status Bits Return from subroutine RET SP 2 SP MOV SP PC Instruction Set Overview The return address pushed onto the stack by a CALL instruction is moved to the program counter The program continues at the code
157. uses the 16 bit memory data bus MDB and as many of the least significant address lines of the memory address bus MAB as required to access the memory locations Blocks of memory are automatically selected through module enable signals This technique reduces overall current consumption Program memory is integrated as programmable or mask programmed memory In addition to program code data may also be placed in the code memory section of the memory map and may be accessed using word or byte instructions this is useful for data tables for example This unique feature gives the MSP430 an advantage over other microcontrollers because the data tables do not have to be copied to RAM for usage Sixteen words of memory are reserved for reset and interrupt vectors at the top of the 64 kilobytes address space from OFFFFh down to OFFEOh 2 4 Data Memory The data memory is connected to the CPU through the same two buses as the program memory flash the memory address bus MAB and the memory data bus MDB The data memory can be accessed with full word data width or with reduced byte data width Additionally because the RAM and flash are connected to the CPU via the same busses program code can be loaded into and executed from RAM This is another unique feature of the MSP430 devices and provides valuable easy to use debugging capability 2 5 Operation Control The operation of the different MSP430 members is controlled mainly by th
158. while PNSEL x 1 the internal input signal simply follows the signal at the pin However if the PnSEL x bit is reset then the output of the latch and therefore the input to the other peripheral module represents the value of the signal at the device pin just prior to the bit being reset 8 2 2 Port P1 Port P2 Schematic The pin logic of each individual port P1 and port P2 signal is identical Each bit can be read and written to as shown in Figure 8 2 Figure 8 2 Schematic of One Bit in Port P1 P2 PnSEL x PnDIR x Output Direction Control gt MUX From Module SS PnOUT x gt Pad Logic gt Module X OUT gt a _ PnIN x 4 Module x IN Y AL e PnIRQ x Interrupt jd PnIFG x Flag Select PnIES x Request PnSEL x Interrupt Penn Pn 07 PnIRQ z X 0 to 7 according to bits O to 7 n 1 for Port P1 and 2 for Port P2 Digital I O Configuration 8 7 Ports P1 P2 8 2 3 Port P1 P2 Interrupt Control Functions 8 8 Ports P1 and P2 use eight bits for interrupt flags eight bits to enable interrupts eight bits to select the effective edge of an interrupt event one interrupt vector address for port P1 and one interrupt vector address for port P2 Each signal uses three bits for configuration and interrupt Interrupt flag P1IFG 0 to P1IFG 7 and P2IFG
159. would notbe set even though the values inthe timer and the CCRO registers are the same SSS SSS SSS ss Topic Page 11 2 112 TimertA 11 3 11 5 11 4 Capture Compare Blocks 11 12 11 5mimer A Registers uei eye 11 22 AST 11 32 Introduction 11 1 Introduction Timer A is an extremely versatile timer made up of d d d 16 bit counter with 4 operating modes Selectable and configurable clock source Three independently configurable capture compare configurable inputs registers with Three individually configurable output modules with 8 output modes Timer A can support multiple simultaneous timings multiple capture compares multiple output waveforms such as PWM signals and any combination of these Additionally Timer A has extensive interrupt capabilities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers on captures or compares Each capture compare block is individually configurable and can produce interrupts on compares or onr The ising falling or both edges of an external capture signal block diagram of Timer A is shown in Figure 11 1 Figure 11 1 Timer A Block Diagram
160. x Voc Comparator A 15 13 Comparator A Applications In Figure 15 10 the active signal paths are shown when the upper independent system is selected for conversion This example uses the 0 25 internal reference and shows the software selectable RC filter as active Figure 15 10 Temperature Measurement Via Temperature Sensor H meas B a oT R1 meas R1 ret e g Capture Input of e Timer A 91 CAREF CARSEL 16 VCAREF 1 025 15 14 Comparator A Applications Figure 15 11 shows the active signal paths for the lower independent system This example uses the 0 25 internal reference and shows the software selectable RC filter as active Figure 15 11 Temperature Measurement Via Temperature Sensor R2meas OV Vcc 40 1 Ri meas 1 ROAD CAEX E P2CA1 e g Capture Input of Timer A CAREF CARSEL VCAREF 0 1 0 25 e 9 O Comparator A 15 15 Comparator A Applications 15 4 4 Comparator A Used to Detect a Current or Voltage Level Comparator_A can be used to detect current or voltage levels if they are below or above a reference level shown in Figure 15 12 The reference level can be selected from the internal reference voltage generator or by applying an external reference level Application software can poll the CAO
161. 0 Modes 2 3 6 7 not useful for output unit 0 Bit 8 Bit 9 Bit 10 Bit 11 Bits 12 13 Bits 14 15 CAP sets capture or compare mode 0 Compare mode 1 Capture mode Read only always read as 0 SCCIx bit The selected input signal CCIxA CCIxB or GND is latched with the EQUx signal into a transparent latch and can be read via this bit SCSx bit This bit is used to synchronize the capture input signal with the timer clock 0 asynchronous capture 1 synchronous capture Input select CCISO and CCIS1 These two bits define the capture signal source These bits are not used in compare mode 0 Input CCIxA is selected 1 Input CCIxB is selected 2 GND 3 Vcc Capture mode bits Table 11 8 describes the capture mode selections Table 11 8 Capture Compare Control Register Capture Mode Valls Capture Mode Description 0 Disabled The capture mode is disabled 1 Pos Edge Capture is done with rising edge 2 Neg Edge Capture is done with falling edge 3 Both Edges Capture is done with both rising and falling edges Timer A 11 27 Timer A Registers Note Simultaneous Capture and Capture Mode Selection Captures must not be performed simultaneously with switching from compare to capture mode Otherwise the result in the capture compare register will be unpredictable The recommended instruction flow is 1 Modify the control register to switch from compare to capture 2 Captu
162. 0 FCTL2 SSEL1 SSELO FN5 FN4 FN3 FN2 FN1 FNO 012Ah rw 0 rw 1 rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 FCTL1 SEGWRT WRT Reserved Reserved Reserved MEras Erase Reserved 0128H rw 0 rw 0 ro ro ro rw 0 rw 0 ro A 12 14 Hardware Multiplier Word Access Bit O13Eh Result high word ResHI 013Ch Result low word ResLO 013Ah Second operand OP2 0138h MPYS ACC MACS 0136h MPY ACC MAC 0134h Multiply signed MPYS 0132h Multiply unsigned MPY 0130h Bit Sum extend SumExt 013Eh Result high word ResHI 013Ch Result low word ResLO 013Ah Second operand OP2 0138h MPYS ACC MACS 0136h MPY ACC MAC 0134h Multiply signed MPYS 0132h Multiply unsigned MPY 0130h 15 t r 215 rw 215 rw 215 rw 215 rw 215 rw 25 14 214 rw 214 rw 214 rw 214 rw 214 rw a 13 213 rw 213 rw 213 rw 213 rw 213 rw ah 12 212 rw 212 rw 212 rw 212 rw 212 rw 11 211 rw 211 rw 211 rw 211 rw 211 rw z Hardware Multiplier Word Access 210 rw 210 rw 210 rw 210 rw 210 29 rw rw ae A A T The Sum Extend register SumExt holds 16x16 bit multiplication MPYS sign result or the overflow of the multiply and mulate MAC operation or the sign of the signed multiply and accumulate MACS operation Overflow and underflow of the MACS operation must be handled by software Peripheral File Map A 13 T
163. 0h to OFO3Fh OF040h to OF07Fh 0F080h to OFOBFh OFOCOh to OFOFFh OF100 to OF13Fh The block write program operation at the 64 byte boundaries needs special software support test of address Oxx3Fh Oxx7Fh OxxBFh or OxxFFh was successful Waituntil the WAIT bitis set indicating that the write ofthe last byte or word was completed Reset control bit BLKWRT The BUSY bit remains set until the programming voltage is removed from the flash memory module and overstress is avoided Wait the recovery time troy before another block write is started Flash Memory C 11 Flash Memory Data Structure and Operation The write cycle is successfully completed if none of the following restrictions is violated set The predivider is not modified Lj The selected clock source is available until the cycle is completed The access to the flash memory module is restricted as long as BUSY is The conditions to read data from the flash memory with and without access violation are listed in Table 2 Table C 2 Conditions to Read Data From Flash Memory Flash Operation Instruction BUSY WAIT Data on Memory Data Action Fetch Bus MDB see Note 1 Byte word program No Access violation cycle see Note 2 Yes 3FFF JMP Nothing Flash read mode Memory contents from PC PC 2 applied address Page erase cycle No 3FFF Access violation see Note 3 Yes 3FFF JMP Nothi
164. 1 x facLk DCO 1 fcocuk D x N 1 x facLk MCLK SMCLK are stabilized using a frequency locked loop technique When combined with the DCO two important benefits result Fast start up The MSP430x4xx DCO is active in less than 6 us which supports extended sleep periods and burst performance Digital control signals The DCO starts at exactly the same setting as when shutoff Thus a long locking period is not required for normal operation User software can modify the DCO frequency used for MCLK SMCLK by changing the multipliers and D plus bit at any time The exact minimum and maximum frequency for MCLK SMCLK is specified in the device data sheet FLL Clock Module 7 5 9 2 S6 6 5 1 0 7 0 FI SCFQCTL Seon D M 2 6 2 5 2 4 2 3 2 2 2M 2 0 rw 0 rw i rw 0 n 0 rw 0 rw 0 rw 0 rw 0 rw i rw i rw i rw i rw i 42 7 f fx f DCOCLK e 1 2 4 8 DCOCLK N 1 x ACLK gt gt facii D x 1 fACLK X 1 x correct fACLK frequency ACLK gt ACLK 0 gt DCOCLK DCO 43 44x 43x 44x 41x to MCLK and SMCLK to MCLK SELM 0 1 to SMCLK SELS 0 0 pajoyuog Ayeybiq doo pexooT Kouenba4 pue 19181250 payjoquog Ayjeyvbiq Digitally Controlled Oscillator Frequency Locked Loop 7 31 FLL Op
165. 1 and 0 1 The LSB m0 of the modulation register is used first Start bit Error raie x 2x 1 6 0 x UxBR 0 0 1 100 2 54 Data bit DO Error Paud rate x 2x 1 6 1 x UxBR nH x 100 5 08 baud rate gt tox 6 2 x UxBR 1 1 2 Data bit 01 Error BRCLK x 100 0 29 7 baud rate oe o Data bit 02 Error BRCLK x 2x 1 6 8 x UxBR 2 1 3 x 100 2 83 baud rate x 2x 1 Data bit D3 Error 76 BRCLK 6 4 x UxBR 2 1 4 x 100 1 95 baud rate x 2x 1 Data bit D4 Error BRCLK 6 5 x UxBR 3 1 5 x 100 0 59 Data bit D5 Error BRCLK BRCLK x 100 1 66 baud rate e E BRCLK x 2x 1 6 8 x UxBR 5 1 8 baud rate BRCLK 2x 1 baud rate gt fox 4 6 10 UxBR 6 1 Data bit D7 Error 100 0 88 Parity bit Error 100 3 42 baud rate x lox 6 6 x UxBR 4 1 6 x 100 3 13 6 9 x UxBR 6 I 1 8 1 Stop bit 1 Error 0 x 100 1 37 BRCLK baud rate X 2x 1 6 11 x UxBR 7 H1 11 x x 100 1 1796 ors Data bit 06 Error aud rate rate y 2 1 6 7 UxBR 4 1 7 adate BRCLK Stop bit 2 Error 6 USART Peripheral Interface UART Mode 13 31 13 32 Chapter 14 USART Peripheral Interface
166. 10198761504 00 0 0 0 X x x x 1 2 X x x x x x x x x x x x 1 0 4 X x x x 1X X 1X fx X x 0 0 6 X x x x 1X X 1X X X x X 0 0 8 1 00 0 34 110 0 0 36 17 38 Note Writing to Read Only Register ADC12IV When write to vector word register ADC12IV occurs the highest pending interrupt flag is reset Therefore the interrupt event is missed 8 6 ADC12 Control Registers 17 8 5 1 ADC Interrupt Vector Register Software Example The following software example shows the use of vector word ADC12IV and the associated software overhead The numbers at the right margin show the cycles required for every instruction The example shows a basic interrupt handler structure that can be adopted to individual application requirements The software overhead for the different interrupt sources including interrupt latency and return from interrupt cycles but not the task handling itself is ADC12IFG 0 to ADC121FG 14 ADC120OV 16 cycles ADCi2IFG 15 14 cycles Interrupt handler for the 12 bit ADC The flag which is enabled and has the highest priority determines the interrupt vector word and is reset by hardware after accessing instruction ADD amp TADC12IV PC Flags ADC120V ADC12TOV and ADC12IFG x are reset by hardware ADC HND Interrupt latency 6
167. 11 9 Output Unit in Up Down Mode Il 11 10 Timer Up Down Direction 11 10 Up Down Mode Flag Setting eee 11 11 Altering CCRO Timer in Up Down Mode 11 11 Capture Compare Blocks eens 11 12 Capture Logic Input Signal eens 11 13 Capt re Signal Puede dba big uu Bei e n a 11 14 Capture Cycle se mnn 11 15 Software Capture Example en 11 16 Output U nib dI M uA p Me it 11 17 Output Control Block WR aW 11 19 Output Examples Timer in Up Mode 11 21 Output Examples Timer in Continuous Mode 11 21 Output Examples Timer in Up Down Mode 11 22 Timer A Control Register _ 11 23 TAR ROGIStEM LL ree eee neben ten dies 11 25 Capture Compare Control Register CCTLX 11 25 Capture Compare Interrupt Flag 11 28 Schematic of Capture Compare Interrupt Vector Word 11 29 Vector Word Reg
168. 12 the receive interrupt flag URXIFG is set each time a character is received and loaded into the receive buffer Figure 14 12 Receive Interrupt Operation SYNC r 1 SYNC 1 Valid Start Bit URXS Eu DEM Receiver Collects Character URXSE From URXD PE URXIE Request FE Interrupt Service BRK URXEIE URXIFG URXWIE e RXWake e SWRST Character Received PUC or UxRXBUF Read Master Overrun USPIIE IRQA URXIFG is reset by a system reset PUC signal or by a software reset SWRST UxRXIFG is reset automatically if the interrupt is served or the receive buffer UxRXBUF is read The receive interrupt enable bit USPIIE if set enables a CPU interrupt request as shown in Figure 14 13 The receive interrupt flag bits URXIFG and USPIIE are reset with a PUC signal or a SWRST Figure 14 13 Receive Interrupt State Diagram Wait For Next Start USPIIE 1 SWRST 1 USPIIE 0 Interrupt USPIIE 1 and Service Started Completed GIE 1 and 0 Priority Valid URXIFG 0 USART Peripheral Interface SPI Mode 14 13 Interrupt and Control Functions 14 4 4 Transmit Interrupt Operation In the transmit interrupt operation shown in Figure 14 14 the transmit interrupt flag UTXIFG is set by the transmitter to indicate that the transmitter buffer UXTXBUF is ready to accept another character This bit is automatically reset if the interrupt
169. 13 12 enables or disables receipt of the bit stream on the URXD data line Disabling the USART receiver stops the receive operation after completion of receiving the character or stops immediately if no receive operation is active Start bit detection is also disabled Figure 13 12 State Diagram of Receiver Enable No Valid Start Bit URXE 0 Not Completed URXE 1 Valid Start Bit Idle State Receiver Enabled Receiver Collects Character Receive Handle Interrupt Disable Conditions Character Received Note URXE Re Enabled UART Mode Because the receiver is completely disabled reenabling the receiver is asynchronous to any data stream on the communication line Synchronization can be performed by looking for an idle line condition before receiving a character LLLA A A USART Peripheral Interface UART Mode 13 11 Interrupt and Enable Functions 13 4 2 USART Transmit Enable Bit The transmit enable bit UTXE shown in Figure 13 13 enables or disables a character transmission on the serial data line If this bit is reset the transmitter is disabled but any active transmission does not halt until the data in the transmit shift register and the transmit buffer are transmitted Data written to the transmit buffer before UTXE has been reset may be modified or overwritten even after UTXE is reset until it is shif
170. 16 10 16 2 5 LCD Control Register 000 ees 16 11 16 2 6 ECD MEMO doe eter dad atau andes a data 16 12 16 3 Code Examples 5 e tes E aces yeni EM EE MED EEG 16 19 16 3 1 Example Code for Static LCD 16 19 16 3 2 Example Code for Two MUX 1 2 Bias LCD 16 20 16 3 3 Example Code for Three MUX 1 3 LCD 16 21 16 3 4 Example Code for Four MUX 1 3 LCD 16 22 2 LL 17 1 TVA Introd ctlon s ossium 17 2 17 2 ADC12 Description and Operation 17 4 17 23 GO ii eo dee o soe ete a laters 17 4 17 2 2 Heterence vore elc ELA e eee ete oe ah ace 17 5 17 3 Analog Inputs and Multiplexer 17 6 17 3 1 Analog Multiplexer eee eee eee nee 17 6 17 3 2 Input Signal Considerations 00 cece etnies 17 7 17 3 3 Using the Temperature Diode 17 7 17 4 Conversion Memory eet n 17 8 17 5 Conversion Modes 5 aed pie aoe ete eas 17 9 17 5 1 Single Channel Single Conversion Mode 17 9 17 5 2 Sequence of Channels Mode 17 12 17 5 3 Repeat Single Channel Mode 17 16 17 5 4 R
171. 17 23 17 24 17 25 17 26 B 1 B 2 B 3 B 4 B 5 xvi A D Converter for Voltage Sources Conversion Timing 15 19 Measuring the Offset Voltage of the Comparator CAEX 0 15 20 Offset Voltage of the Comparator CAEX 0 15 20 Measuring the Offset Voltage of the Comparator CAEX 1 15 21 Offset Voltage of the Comparator CAEX 1 15 21 Use CAOUT at an External Pin to Add Hysteresis to the Reference Level 15 23 Static Wave Form Drive een teens 16 3 Two MUX Wave Form Drive 16 4 Three MUX Wave Form Drive 16 5 Four MUX Wave Form Drive m 16 6 LCD Controller Driver Block Diagram 16 7 External LCD Module Analog Voltage 16 9 LCD Control and Mode Register 16 11 Information Control e hh 16 11 Display Memory Bits Attached to Segment Lines in 4xx Family 16 12 Example With the Static Drive Mode 16 14 Example With the Two MUX Mode 16 16 Example With the 3 MUX Mode
172. 18 14 19 14 20 14 21 14 22 15 1 15 2 15 3 15 4 15 5 15 6 15 7 15 8 15 9 15 10 15 11 15 12 15 13 15 14 15 15 15 16 Contents Receiver Control Register UORCTL 1 13 19 USART Baud Rate Select Register 13 21 USART Modulation Control Register 13 21 USART Receive Data Buffer UORXBUF U1RXBUF 13 22 Transmit Data Buffer UOTXBUF U1TXBUF 13 22 Receive Start Conditions 00 6 13 23 Receive Start Timing Using URXS Flag Start Bit Accepted 13 24 Receive Start Timing Using URXS Flag Start Bit Not Accepted 13 24 Receive Start Timing Using URXS Flag Glitch Suppression 13 24 MSP430 Transmit Bit Timing nent eee 13 27 MSP430 Transmit Bit Timing Errors 13 27 Synchronization ETFOE sce echoed nase irae anaes 13 30 Block Diagram of USART eet hn 14 2 Block Diagram of USART SPI Mode 14 3 MSP430 USART as Master External Device With SPI as Slave 14 5 Serial Synchronous Data Transfer 14 6 Data Transfer Cycle Reb eee tbe rq ek hb nere re oed 14 6 MSP430 USART as Slave in Three Pin or Four Pin Configura
173. 198h Cap com register TBCCR2 0196h Cap com register TBCCR1 0194h Cap com register TBCCRO 0192h Timer B register TBR 0190h Cap com control TBCCTLef 018Eh Cap com control TBCCTLS5T 018Ch Cap com control TBCCTL4T 018Ah Cap com control 0188h Cap com control TBCCTL2 0186h Cap com control TBCCTL1 0184h Cap com control TBCCTLO 0182h Timer_B control TBCTL 0180h 215 rw 0 215 rw 0 215 rw 0 215 rw 0 215 rw 0 215 rw 0 215 rw 0 215 rw 0 Pv m 29 38 g Sk 2 Se 50 S9 szssN Unused rw 0 14 rw s rw a rw eA rw rw ais rw 2 rw un rw ovn om rw ovs coe sose rw rw rw co coisa rw rw coissi soss rw rw nen xs rw rw rw cos ss rw rw rw cos cas 55 rw rw rw rcu m rw rw t Registers are reserved on devices with Timer B3 A 16 x 1 pes 1 1 1 cu 1 cur 1 cum 1 pir rw 0 CLLD6 0 rw 0 CLLD5 0 rw 0 CCLD4 0 ro CCLD3 0 ro CCLD2 0 ro CCLD1 0 ro CCLDO 0 ro TBSSEL1 rw 0 rw 0 CAP6 rw 0 CAP5 rw 0 4 rw 0 rw 0 CAP2 rw 0 CAP1 rw 0 CAPO rw 0 TBSSELO rw 0
174. 2 9 Timer oer oon certe ds ae decere Dee cere 12 8 12 3 1 Timer Stop Mode ssssssssssessss eens 12 8 12 3 2 limer U p Mode EMIL Meu EDT ERN DER 12 8 12 3 3 Timer Continuous Mode 12 10 12 3 4 Timer Up Down Mode Ie 12 12 12 4 Capture Compare Blocks 0c cece enn 12 15 12 4 4 Capture Compare Block Capture Mode 12 16 12 4 2 Capture Compare Block Compare Mode 12 19 12 5 The Output Unit carian eens ey oe ens bee 12 23 12 5 2 Output Control Block 0 0 ccc 12 25 12 5 3 OUTPUT Exambples ovens 12 26 12 6 Timer B Registers eee nn 12 29 12 6 1 Timer B Control Register TBCTL 12 29 12 6 2 Timer B Register TBR 0 0 0 eee 12 32 12 6 3 Capture Compare Control Register TBCCTLX 12 32 12 6 4 Timer B Interrupt Vector Register 12 35 13 USART Peripheral Interface UART Mode 13 1 13 1 USART Peripheral Interface nh 13 2 13 2 USART Peripheral Interface UART Mode 13 3 13 2 1 UART Serial Asynchronous Communication Features 13 3 13 3 A
175. 22 w 0 22 w 0 22 w 0 w 0 w 0 w 0 0 r rw rw rw rw rw 0 rw rw rw n n n n 5 1 0 25 4 21 20 r rw 0 0 n rw 0 rw 0 25 4 21 20 r rw 0 0 n rw 0 rw 0 25 4 21 20 r rw 0 0 n rw 0 rw 0 25 4 21 20 rw 0 0 n rw 0 rw 0 r rw 0 0 n rw 0 rw 0 r rw 0 0 n rw 0 rw 0 r rw 0 0 n rw 0 rw 0 0 0 0 0 7 27 w 0 27 w 0 27 w 0 27 w 0 w 0 w 0 w 0 0 6 26 w 0 26 w 0 26 w 0 26 w 0 w 0 w 0 w 0 0 Timer A Registers Word Access A 14 Timer A Registers Word Access Continued Bit 15 14 13 12 11 10 9 8 Timer A interrupt vector 0 0 0 0 0 0 0 0 TAIV 12Eh ro ro ro ro ro Bit 2 1 0 7 6 5 4 3 Timer A interrupt vector 0 0 0 0 TAIV 0 TAIV 12Eh ro ro r 0 r 0 r 0 ro TAIV Vector Timer A3 three capture compare blocks integrated No interrupt pending CCIFG1 flag set interrupt flag of capture compare block 1 CCIFG2 flag set interrupt flag of capture compare block 2 CCIFG1 0 Reserved Reserved TAIFG flag set interrupt flag of Timer A register counter CCIFG1 CCIFG2 CCIFG3 CCIFG4 0 Peripheral File Map A 15 Timer B Registers Word Access A 16 Timer B Registers Word Access Bit 4 Cap com register TBCCRef 019Eh Cap com register TBCCR5t 019Ch Cap com register TBCCR4T 019Ah Cap com register TBCCR3t 0
176. 4 m5 m6 m7 m0 2 USART Peripheral Interface UART Mode 13 21 Control and Status Registers 13 5 5 Receive Data Buffer UORXBUF U1RXBUF The receive data buffer shown in Figure 13 21 contains previous data from the receiver shift register Reading the receive data buffer resets the receive error bits the RXWake bit and the interrupt flag URXIFG Figure 13 21 USART Receive Data Buffer UORXBUF U1RXBUF 7 0 UORXBUF 076h mene Te T8 T2 T2 T2 T2 T r r r r r r r r In seven bit length mode the MSB of the UxRXBUF is always reset The receive data buffer is loaded with the recently received character as described in Table 13 5 when receive and control conditions are true Table 13 5 Receive Data Buffer Characters URXEIE URXWIE Load UxRXBUF With PE FE BRK 0 1 Error free address characters 0 0 0 1 1 All address characters X X X 0 0 Error free characters 0 0 0 1 0 All characters X X X 13 5 6 Transmit Data Buffer UOTXBUF UTTXBUF The transmit data buffer shown in Figure 13 22 contains current data to be transmitted Figure 13 22 Transmit Data Buffer UOTXBUF UTTXBUF 7 0 UOTXBUF 077h wares Te Te Te T4 T4 T rw rw rw rw rw rw rw rw The UTXIFG flag indicates that the UxTXBUF buffer is ready to accept another character for transmission The transmission is initialized by writing data to UXTXBUF The data is moved to transmit shift register and transmission is started o
177. 51 CAON CAF o 0 1 O 0 7 L CA1 Set P2CA1 CAIFG VCC CAREF oqo SG CARSEL vont mn 0 25x Vcc o o 5 The equation for the voltage Vmeas iS 4X In 0 5 _ Re tittis V meas m X 1 Figure 15 17 A D Converter for Voltage Sources Conversion Timing Vc Lco LE MEME mu CE 0 5 x Vcc gt lt gt Phase I Phase II Charge Up Charge Up Determine Tau RC Note During phase control bit P2CAO 1 and CAREF 0 During phase ll control bit 2 0 CARSEL 0 and CAREF 1 Comparator A 15 19 Comparator A Applications 15 4 6 Measuring the Offset Voltage of Comparator A The input offset voltage of the comparator varies with each device and also with temperature supply voltage and input voltage If the input voltage is stable reference voltage it will not influence the offset voltage significantly To increase the precision of voltage measurements the comparator offset voltage can be measured by the following steps To simply compensate for the offset without measuring it see Section 15 4 7 First execute a conversion with CAEX 0 is applied to the terminal of the comparator and Vref is applied to the terminal of the comparator as shown in Figure 15 18 Figure 15 18 Measuring the Offset Voltage of the Comparator CAEX 0 oV Vcc P2CA0 C EX 40 E
178. 8 bit 8x16 bit 8x8 bit The following is an example of unsigned multiply and accumulate 16x16 Unsigned Multiply and Accumulate MOV 012341 amp MAC Load first operand into appropriate register MOV 05678h amp OP2 Load 2nd operand Result is now available 8x8 Unsigned Multiply and Accumulate MOV B 4012h amp MAC Load first operand into appropriate register 034h amp 0 2 Load 2nd operand Result is now available 6 2 4 Multiply Signed and Accumulate 16x16bit 16x8bit 8x16bit 8x8bit The following is an example of signed multiply and accumulate 16x16 Signed Multiply and Accumulate MOV 012341 amp MACS Load first operand into appropriate register MOV 056781 amp OP2 Load 2nd operand Result is now available 8x8 Signed Multiply and Accumulate OV B 012h amp MPYS Load first operand into appropriate register SXT amp MPYS Sign extend first operand OV B 034h R5 Temporary location for 2nd operand SXT amp 2 Sign extend 2nd operand OV R5 amp 2 Load signed extended 2nd operand 16 bit value Result is now available Hardware Multiplier 6 5 Hardware Multiplier Registers 6 3 Hardware Multiplier Registers Hardware multiplier registers are word structured but can be accessed using word or byte processing instructions Table 6 2 describes the hardware multiplier registers Table 6 2 Hardware Multipli
179. 8 for 8000h lt N lt FFFFh Figure 13 29 Synchronization Error target 0 1 2 to t 112131 4 5 6 7 8 9 10 11 12 13 14 1 2 8 4 5 7 8 o to 1213114 1 2 3 4 5 6 7 URXD ST DO D2 ae URXDS ST DO D2 to ty to 9 Synchronization Error 0 5x BLSCLK Sample URXDS Int UxBR 2 m0 UxBR m1 1341 14 UxBR m2 13 0 13 int 13 2 1 6 1 7 13 30 LIA LIA Majority Vote Taken Majority Vote Taken Majority Vote Taken Baud Rate Considerations The target start bit detection baud rate timing trarget o is half the baud rate timing tpaug rate because the bit is tested in the middle of its period The target baud rate timing trargetifor all of the other succeeding bits is the baud rate timing lbaud rate n 1 n tactualy trargety 2 tactual m Larger 1 x 100 0 5 x trargety lrarget Error OR Error 2 x int UxBR 2 i x UxBR Em 100 Where baud rate is the required baud rate BRCLK is the input frequency selected for UCLK ACLK or MCLK i for the start bit 1 for data bit DO and so on UxBR is the division factor in registers UXBR1 and UxBRO Example 13 4 Synchronization Error 2400 Baud The following data are assumed Baud rate 2400 BRCLK 32 768 Hz ACLK UxBR 13 since the ideal division factor is 13 67 m 6Bh m7 0 1 m5 1 m4 0 m3 1 m2 0 m1
180. 9 1 3 Watchdog Timer Operation The WDT module can be configured in two modes watchdog and the interval timer modes 9 1 3 1 Watchdog Mode When the WDT is configured to operate in watchdog mode both a watchdog overflow and a security violation trigger the PUC signal which automatically clears the appropriate system register bits This results in a system configuration for the WDTCTL bits where the WDT is set into the watchdog mode and the RST NMI pin is switched to the reset configuration After a power on reset or a system reset the WDT module automatically enters the watchdog mode and all bits in the WDTCTL register and the watchdog counter WDTCNT are cleared The initial conditions at register WDTCTL cause the WDT to start running at a relatively low frequency due to the range of the digitally controlled oscillator DCO automatically being set in these situations Since the WDTONT is reset the user software has ample time to set up or halt the WDT and to adjust the system frequency Users must refer to the specific data sheets and the clock system chapter of this manual to determine the details of the clocking circuit on the MSP430 device chosen Watchdog Timer 9 5 The Watchdog Timer 9 1 3 2 Timer Mode When the module is used in watchdog mode the software should periodically reset the WDTCNT by writing a 1 to bit CNTCL of WDTCTL to prevent expiration of the selected time interval If a software problem occurs and the time i
181. ADD R6 R4 add MSDs with carry JC OVERFLOW If carry occurs go to error handling routine The two digit decimal counter in the RAM byte CNT is incremented by one CLRC clear Carry DADD B 1 CNT increment decimal counter Or SETC DADD B 80 DADC B DEC W DEC B Operation Emulation Emulation Description Status Bits Mode Bits Instruction Set Overview Decrement destination Decrement destination DEC dst or DEC W dst DEC B dst dst 1 dst SUB 1 dst SUB B 1 dst The destination operand is decremented by one The original contents are lost N Set if result is negative reset if positive Z Set if dst contained 1 reset otherwise C Reset if dst contained 0 set otherwise V Set if an arithmetic overflow occurs otherwise reset Set if initial value of destination was 080001 otherwise reset Set if initial value of destination was 080h otherwise reset OscOff CPUOff and GIE are not affected Instruction Set Description B 25 Instruction Set Overview Example R10 is decremented by 1 DEC R10 Decrement R10 Move a block of 255 bytes from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination address TONI must not be within the range EDE to EDE 0FEh MOV EDE R6 MOV 255 R10 L 1 MOV B R6 TONI EDE 1 R6 DEC R10 JNZ L 1 Do not transfer tables using the routine above with the o
182. Bit 1 Up mode Continuous mode Up down mode TBIFG is set if the timer counts from TBCLO value to 0000h TBIFG is set if the timer counts from TBR max to 0000h TBIFG is set if the timer counts down from 0001h to 0000h Timer overflow interrupt enable TBIE bit An interrupt request from the timer overflow bit is enabled if this bit is set and is disabled if reset Timer_B 12 29 Timer B Registers Bit 2 Timer clear TBCLR bit The timer and input divider are reset with the POR signal or if bit TBCLR is set The TBCLR bit is automatically reset and is always read as zero The timer starts in the upward direction with the next valid clock edge unless halted by cleared mode control bits Bit 3 Not used Bits 4 5 Mode control Table 12 5 describes the mode control bits Table 12 5 Mode Control Description Timer is halted MC1 Count Mode 0 0 Stop 0 1 Up to TBCCRO 1 0 Continuous up 1 1 Up down Bits 6 7 bits Table 12 6 Input Clock Divider Control Bits 101 IDO Operation 0 0 0 1 2 1 0 4 1 1 8 Timer counts up to TBCLO and restarts at 0 Note If TBCLO gt the counter counts to zero with the next rising edge of timer clock Timer counts up and restarts at 0 The maximum value of TBR TBR max is OFFFFh for 16 bit configuration OOFFFh for 12 bit configuration 003FFh for 10 bit configuration OOOFFh for 8 bit configuration Time
183. C 4 Wait for Trigger 0 EOS x 1 SAMPCON 4 SAMPCON 1 Sample Input Channel Defined in ADC12MCTLx If EOS x 1 then x CStartAdd else if lt 15 thenx 2 x 1 else x 0 SAMPCON Y If EOS x 1 then x CStartAdd else if lt 15 then x 2 x 1 12 x ADC12CLK Convert Use else x 0 12 x ADC12CLK MSC 1 and 1 1 x ADC12CLK ENC 1 and Conversion ENC 1 Completed or Result Stored Into EOS x 0 ADC12MEMXx ADC12IFG x Is Set X pointer to conversion memory register ADC12MEMO ADC12MEM 15 and conversion memory control register ADC12MCTLO ADC12MCTL15 17 5 5 Switching Between Conversion Modes Changing the mode of operation of the ADC12 while the converter is not actively running is done simply by selecting the new mode of operation with the CONSEQ bits However if the conversion mode is changed while the converter is actively running intermediate and undesirable modes can be accidentally selected if both CONSEQ bits are changed in a single instruction ADC12 17 19 Conversion Modes 17 5 6 Power Down 17 20 Therefore the following mode changes should be avoided while the converter is running 0 gt 3 1 2 2 1 gt 0 The intermediate modes are caused by the asynchronous clocks for the CPU and the ADC12 These intermediate modes can be avoided simply by changing only
184. C reset ADC12SC set ADC12SC reset may be set together starts conversion starts sampling starts conversion starts sampling starts conversion 7177771 T irrrrrrrrrrrrrmnrrrrrrrrrrrrrrrrrrri A DOL DAA D DA OAD DA DAADA DALOL DAL irr vvvvvvvvvyvvvvv Yvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvev TTTTTTTTTTTTTTTT UU Un nt Sample Sample Sample Conversion Sample Sample gt lt gt lt gt lt gt lt gt lt Single Conversion Single Conversion Single Conversion Single Conversion Single Conversion Time Time Time Time Time Single Period gt Single Period f Single Period Single Period of Sequence of Sequence of Sequence of Sequence Peri f n Next Peri f n le eriod of Sequences gt lt ext Period of Sequences S First with ADC12SC reset ADC12SC set ADC12SC reset ADC12SC set ADC12SC reset ENC set start S amp C starts conversion starts sampling starts conversion starts sampling starts conversion SAMPCON TTT1 qirrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrri ria vvvv 77 71 11 2 T ER Sample Sample Conversion a uum gt lt
185. CFQCTL Read write 052h 0318 System clock SCFIO Read write 050h 040h frequency integrator 0 System clock SCFI Read write 051h Oh frequency integrator 1 FLL control 0 FLL CTLO Read write 053h 03h FLL control 1 FLL CTL1 Read write 054h Oh 7 7 1 MCLK SMCLK Frequency Control The contents of register SCFQCTL and control bits D if DCO 1 SCFIO control the frequency of DCOCLK available for MCLK and SMCLK The contents of register SCFQCTL is shown in Figure 7 7 Figure 7 7 SCFQCTL Register 7 0 SCFQCTL rw 0 rw O0 rw 0 rw 1 rw 1 rw 1 rw 1 rw 1 The seven bits indicate a range of 1 1 to 127 1 Any value below 1 results in unpredictable operation The user should ensure that the value selected does not exceed the maximum system clock MCLK and SMCLK value specified in the device data sheet fgystem 26 x 25 24 23 22 21 x 20 1 forystal DCO 0 fsystem D x 26 25 24 23 22 x 21 x 20 1 ferystal DCO 1 The default value in SCFQCTL is 31 after a PUC signal is active resulting in a factor of 32 x DCO 0 The output of the frequency integrator controls the DCO This value can be read using the SCFI1 and SCFIO addresses as shown in Figure 7 8 If the modulation bit M is set only the DCO taps determine the system frequency Adjacent DCO taps are not mixed Note however that if the FLL remains active SCGO 0 it will continue to adjust the DCO taps If an appl
186. CH 2 INCH 1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 rw 0 rw 0 rw 0 0 0 rw 0 rw 0 rw 0 0 0 0 EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 rw 0 rw 0 rw 0 0 0 rw 0 rw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rW EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 rw 0 rw rw 0 rw rw 0 rw 0 rw 0 EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 rw 0 rw rw 0 rw rw 0 rw 0 rw 0 EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 rw 0 rw rw 0 rw rw 0 rw 0 rw 0 bits of ADC12MCTLx registers are only modifiable when ENC 0 0 rw rw 0 Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 rw 0 rw 0 rw rw 0 rw 0 rw 0 0 rw rw 0 EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 rw 0 rw 0 rw rw 0 rw 0 rw 0 0 INCH O rw 0 INCH O rw 0 INCH O rw 0 INCH O rw 0 INCH O rw 0 INCH O rw 0 INCH O rw 0 INCH O rw 0 INCH O rw 0 INCH O rw 0 INCH O rw 0 INCH O rw 0 INCH O rw 0 INCH O rw 0 INCH O rw 0 INCH O rw 0 z z z ADC12 Registers Byte Word Access
187. CRO CCR1 Oh Du d Output Mode 1 Set S Output Mode 2 PWM Toggle Reset Output Mode 3 PWM Set Reset im eem im mE Output Mode 4 Toggle oceani Output Mode 5 Reset Sas m Output Mode 6 PWM Toggle Set ER ho il Output Mode 7 PWM Reset Set EQUO EQU1 EQUO EQUi EQUO Interrupt Events 11 4 5 2 Output Examples Timer in Continuous Mode The signal is changed when the timer reaches the CCRx and CCRO values depending on the output mode as shown in Figure 11 25 Figure 11 25 Output Examples Timer in Continuous Mode Output Mode 2 PWM Toggle Reset Output Mode 3 PWM Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 PWM Toggle Set Output Mode 7 PWM Reset Set OFFFFh CCRO CCR1 Oh TER Output Mode 1 Set TAOV EQU1 EQUO TAOV EQU1 EQUO Interrupt Events Timer A 11 21 Timer A Registers 11 4 5 3 Output Examples Timer Up Down Mode The OUTx signal changes when the timer equals CCRx in either count direction and when the timer equals CCRO depending on the output mode as shown in Figure 11 26 Figure 11 26 Output Examples Timer in Up Down Mode 1 OFFFFh CCRO CCR2 Oh 25 Output Mode 1 Set 3 Output Mode 2 PWM Toggle Reset ah Output Mode 3 PWM Set Reset L loOutput Mode 4 Toggle Output Mode 5 Reset E Output Mode 6 PWM Toggle Set zs es Output Mode 7
188. Comparator A Applications 15 4 7 Compensating for the Offset Voltage of Comparator A Another way to improve the accuracy is to compensate for the effect of input offset voltage without actually measuring it When CAEX 0 the is in series with Vref Vcao Vref Voffset When 1 the is in series with Vref Voffset Vref Vottset Adding the result of two conversions one with each input configuration and dividing by two will cancel the effect of the offset voltage ret Voffset V V cA ren iud NI 5 _ Conversion without offset 2 2 V et Timer count 15 4 8 Adding Hysteresis to Comparator A 15 22 When the voltage level applied to the terminal is close to the voltage level at the terminal the output of the comparator may oscillate This can cause the following two situations The current consumption increases since the signal path driven by the comparator output is constantly charged and discharged The software receives constant requests for service either via interrupt service requests or after successful polling of CAOUT or CAIFG Comparator A Applications Figure 15 22 shows how to add hysteresis to the comparatorto prevent output oscillation Figure 15 22 Use CAOUT at an External Pin to Add Hysteresis to the Reference Level 1 It Feedback is Possible
189. D signal exceeds the deglitch time t but the majority vote on the signal fails to detect a start bit as shown in Figure 13 25 The software should handle this condition and return the system to the appropriate low power mode The interrupt flag URXIFG is not set Figure 13 25 Receive Start Timing Using URXS Flag Start Bit Not Accepted Majority Vote URXD URXS 7 EEA EE t URXS is Reset in The Interrupt Handler Using Control Bit URXSE Glitches atthe URXD line are suppressed automatically and no further activity occurs in the MSP430 as shown in Figure 13 26 The data for the deglitch time t is noted in the corresponding device specification Figure 13 26 Receive Start Timing Using URXS Flag Glitch Suppression Majority Vote URXD URXS L LLL a The interrupt handler must reset the URXSE bit in control register UxCTL to prevent further interrupt service requests from the URXS signal and to enable the basic function of the receive interrupt flag URXIFG 13 24 Utilizing Features of Low Power Modes Ck Ck Ck ck ck ck ck ck kk ck ck kk Ck ck ck ck KKK ck kk Ck Ck ko ck kk Ck Ck ck ck ck kk ck ck ck kk Ck ck Sk ko Mk Mk Sk kc k ko ko ko kock ok Interrupt handler for frame start condition and Character receive UORX Int URXIFGO amp IF
190. DCI2IE 13 121 12 ADC12IE 11 ADC12IE 10 ADC12IE 9 01A6h rw 0 rw 0 rw 0 rw rw 13 12 1 8 ADCI2IE 8 rw 0 0 rw 0 0 rw 0 ADC12IFG ADC12IFG 15 ADC12IFG 14 ADC12IFG 13 ADC12IFG 12 ADC12IFG 11 ADC12IFG 10 ADC12IFG 9 ADC12IFG 8 01A4h rw 0 rw 0 rw 0 rw 0 0 rw 0 rw 0 rw 0 ADC12CTL1 CStartAdd st CStartAdd 2t CStartadd it CStartAdd ot SHs it SHS ot SHPt ISSH 01A2h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12CTLO SHT1 3T SHT1 2t SHT1 1T SHT1 0T 5 21 5 1 SHTO 0 01A0h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 t Only modifiable when 0 Bit t 7 6 5 4 3 2 1 0 ADC12IE ADC12IE 7 ADC12IE 6 ADC12IE 5 ADC12IE 4 ADC12IE 3 ADC12IE 2 ADC12IE 1 ADC12IE 0 01A6h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12IFG ADC12IFG 7 ADC12IFG 6 ADC12IFG 5 ADC12IFG 4 ADC12IFG 3 ADC12IFG 2 ADC12IFG 1 ADC12IFG 0 01A4h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12CTL1 ADC12DIV 2T ADC12DIV 1t ADC12DIV Ot ADC12SSEL 1T ADC12SSEL 0t CONSEQ 1 CONSEQ 0 ADC12BUSY 01A2h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 ADC12CTLO msct 2 51 REFONT ADC120NT ADC120VIE ADC12TOVIE ENC ADC12SC 01A0h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 t Only modifiable when 0 A 10 LCD Registers Byte Access A 11 LCD Registers Byte Access Bit 4 7 6 5 4 3 2 1 0 LCD
191. E R6 amp EDE R8 3 R4 6 R9 EDE TONI 2 R5 amp TONI EDE amp TONI R4 R5 R5 8 R6 R5 EDE R5 amp EDE R5 R6 R9 20 R9 2AEh R9 2 R4 33 EDE R9 amp 8EDE 33 amp EDE Table 5 13 shows a simple way to determine CPU instruction cycles for Format l double operand instructions Table 5 13 Execution Cycles for Double Operand Instructions Source Addressing Mode 1 Add one cycle if Rm is the PC EXAMPLE the instruction ADD execution 5 14 Rn Rn Rn 3 x Rn Symbolic Absolute amp 5006 16 R5 Destination Addressing Mode x Rm Symbolic Absolute amp needs 5 cycles for the Addressing Modes 5 2 8 2 Format ll Single Operand Instructions Table 5 13 describes the CPU format Il instructions and addressing modes Table 5 14 Instruction Format Il and Addressing Modes No of Cycles RRA RRC Length of Address Mode SWPB PUSH Instruction A s d SXT CALL words Example 00 Rn 1 3 4 1 SWPB R5 01 X Rn 4 5 2 CALL 2 R7 01 EDE 4 5 2 PUSH EDE 01 amp EDE SXT amp EDE 10 Rn 3 4 1 RRC R9 11 Rn 3 4 5 1 SWPB R10 see Note CALL 81H 11 N 2 Note Instruction Format Il Immediate Mode Do not use instructions RRA RRC SWPB and SXT with the immediate mode in the destination field Use of these in the immediate mode will result in an unpredictable program operation Table 5 15 shows a simple way to determine CPU instru
192. ED eo Table supported program flows RAM and Peripheral Organization 4 3 2 Computed Branches and Calls Computed branches and subroutine calls are possible using standard instructions The call and branch instructions use the same addressing modes as the other instructions The addressing modes allow indirect indirect addressing that is ideally suited for computed branches and calls This programming technique permits a program structure that is different from conventional 8 and 16 bit microcontrollers Most of the routines can be handled easily by using software status handling instead of flag type program flow control The computed branch and subroutine calls are valid throughout the entire memory space 4 4 RAM and Peripheral Organization The entire RAM can be accessed with byte or word instructions using the appropriate instruction suffix The peripheral modules however are located in two different address spaces and must be accessed with the appropriate instruction length The SFRs are byte oriented and mapped into the address space from Oh up to OFh Peripheral modules that are byte oriented are mapped into the address space from 010h up to OFFh Peripheral modules that are word oriented are mapped into the address space from 100h up to 01FFh 4 4 4 Random Access Memory RAM can be used for both code and data memory Code accesses are always performed on even byte addresses The instruction mnemonic suffi
193. ES 4 P2IES 3 P2IES 2 P2IES 1 rw Ww rw Ww rw rw Ww Ww Ww Ww P1IFG 2 rw P1DIR 2 rw 0 P1OUT 2 rw P1IN 2 r r r rw rw rw 0 P2DIR 7 P2DIR 6 P2DIR 5 P2DIR 4 P2DIR 3 P2DIR 2 P2DIR 1 rw 0 rw rw 0 rw rw 0 rw 0 rw 0 rw r 0 0 P5DIR 2 rw 0 P5OUT 2 0 0 0 0 r r 0 0 0 0 r r 0 0 P2IE 7 P2IE 6 P2IE 5 P2IE 4 P2IE 3 P2IE 2 P2IE 1 rw 0 0 rw 0 0 rw 0 rw 0 rw 0 P2IFG 7 P2IFG 6 P2IFG 5 P2IFG 4 P2IFG 3 P2IFG 2 P2IFG 1 rw 0 0 rw 0 0 rw 0 rw rw 0 0 0 r r 0 0 0 0 0 0 0 0 P1IFG 1 rw 0 P1DIR 1 rw 0 P1OUT 1 rw 1 1 r 0 P6SEL 0 rw 0 P6DIR O rw 0 P6OUT 0 rw P6IN O r P5SEL 0 rw 0 P5DIR O rw 0 P5OUT 0 rw PSIN O r P2SEL 0 rw 0 P2IE 0 rw 0 P2IES O rw P2IFG 0 rw 0 P2DIR 0 rw 0 P20UT 0 rw P2IN 0 r P1SEL O rw 0 P1IE O rw 0 P1IES O rw P1IFG O rw 0 P1DIR O rw 0 P1OUT 0 rw P1IN O r Basic 1 Registers Byte Access 4 Basic Timer1 Registers Byte Access Bit 7 6 5 4 3 2 1 0 2 Counter data 8 Bit Basic Timer 2 0047h Counter data 8 Bit 7 26 25 24 23 nw rw rw rw rw 7 4 Basic Timer 1 26 25 2 23 0046h rw rw rw rw rw Basic Timer BTCTL SSEL Hold DIV FRFQ1 FRFQO IP2 IP1 0040h rw rw rw rw rw A 5 FLL Registers Byte Access 2 rw 2 rw rw Bit 4 7 6 5 4 3 2 1 0 control 0 FLL CTLO M 26 25 24 23 22 21 20 0053h rw 0 rw 0 rw 0
194. FF14h OF016h 04292h OFF12h 042921 0A123h OF016h 0A123h 01234h 01114h OA123h This address mode is mainly for hardware peripheral modules that are located at an absolute fixed address These are addressed with absolute mode to ensure software transportability for example position independent code 5 10 Addressing Modes 5 2 5 Indirect Mode The indirect mode is described in Table 5 9 Table 5 9 Indirect Mode Description Assembler Code Content of ROM MOV R10 0 R11 MOV QR10 0 R11 Length One or two words Operation Move the contents of the source address contents of R10 to the destination address contents of R11 The registers are not modified Comment Valid only for source operand The substitute for destination operand is O Rd Example MOV B GR10 0 R11 Before After Address Register Address Register Space Space Oxxxxh Oxxxxh PC OFF16h OFF14h OFF12h 0000h R10 OFA33h OFF16h 0000h R10 OFA33h O4AEBh PC R11 002A7h OFF14h O4AEBh R11 002A7h OFA32h 05BC1h OFA32h 05BC1h 002A8h 002A7h 002A6h 002A8h 002A7h 002A6h 16 Bit CPU 5 11 Addressing Modes 5 2 6 Indirect Autoincrement Mode The indirect autoincrement mode is described in Table 5 10 Table 5 10 Indirect Autoincrement Mode Description Assembler Code MOV R10 0 R11 Content of ROM MOV R10 0 R11 Move the contents of the source address contents of R10 to the destina
195. Flash Memory Control Registers Access violation interrupt flag The access violation interrupt flag is set when the flash memory module is improperly accessed while a write or erase operation is active The violation situations are described in section C 2 When the access violation interrupt enable bit is set the interrupt service request is accepted and the program continues at the NMI interrupt vector address Reading the control registers will not set the ACCVIFG bit Note The proper interrupt enable bit ACCVIE is located in interrupt enable register IE1 of the special function register Software can set the ACCVIFG bit in this case an NMI is also executed Wait In the block write mode the WAIT bit indicates that the flash memory is ready to receive the next data for programming The WAIT bit is read only but a write to the WAIT bit is allowed The WAIT bit is automatically reset if the BLKWRT bit is reset or the LOCK bitis set Block write operation is completed and then the WAIT bit returns to 1 Condition BLKWRT 1 see Figure C 9 After each successful write operation the BUSY bit is reset to indicate that another byte or word can be written programmed The BUSY bit does not indicate the condition when the timing generator has completed the entire programming The high voltage portion and voltage generator remain active The maximum time should not be violated 0 Block write operation has started and pro
196. Flash Memory Module Systems From Corruption C 20 C 5 Flash Memory Access via JTAG and Software C 22 C 5 1 Flash Memory Protection C 22 C 5 2 Program Flash Memory Module via Serial Data Link Using JTAG Feature C 22 C 5 3 Programming a Flash Memory Module via Controller Software C 22 1 Figures Logd d ddl gd PPRPP PEPPER PpP HHH po TT NOOO O 7 3 TI xii MSP430 System Configuration eh 2 2 Bus Connection of 2 4 Brownout Reset SVS Reset and Power Up Clear Schematic 3 2 Block Diagram of Brownout and SVS Circuits 3 3 Brownout Circuit Operating Levels eee eee sh 3 4 Operating Levels for SVS and Brownout Reset Circuit 3 5 Interrupt Priority Scheme cece eee nee teenies 3 8 Block Diagram of NMI Interrupt Sources 3 9 RST NMI Mode Selection nent eens 3 9 Interrupt Processing cece enn ttn 3 12 Return From Intermpt cese stesskreuberteureteu tare us need Reg 3 12 Status Regist
197. Flash Memory Module Systems From Corruption MSP430 configurations having one flash memory module use this module for program code and interrupt vectors When the flash memory module is in a Write erase or mass erase operation and the program accesses it an access violation occurs This violation will request an interrupt service but when the interrupt vector is read from the flash memory OSFFFh will be read independent of the data in the flash memory at the vector s memory location Flash Memory Interrupt and Security Key Violation To protect the software from this error situation all interrupt sources have to be disabled since all interrupt requests will fail The flash memory returns the vector OSFFFh Before the interrupt enable bits are modified they can be stored RAM to be restored when the flash memory is ready for access again The following interrupt enable bits should be reset to stop all interrupt service requests J GIE 0 NMIIE ACCVIE OFIE 0 Additionally the watchdog should be halted to prevent its expiration when flash memory is busy WDTHOLD 1 When the flash memory is ready the interrupt sources be enabled again Before they are enabled critical interrupt flags should be checked and if necessary served or reset by software 1 or left disabled or be restored to the previous level NMIIE ACCVIE OFIE 1 or left disabled or be restored to the previous level
198. G bit and an NMI interrupt is requested The NMI interrupt routine should handle such violations The bit WRT should be set to get a successful write execution If bit WRT is reset and write access to the flash memory is performed an access violation occurs and ACCVIFG is set Note Instruction fetch access during erase is allowed Any other access to the flash memory during erase results in setting the ACCVIFG bit and an NMI interrupt is requested The NMI interrupt routine should handle such violations Bit BLKWRT can be used to reduce total programming time The block write bit BLKWRT is useful if larger sequences of data have to be programmed If programming of one block is completed a reset and set sequence should be performed to enable access to the next block The WAIT bit should be high before the next write instruction is executed See also paragraph C 1 1 and Figure C 9 0 No block write accelerate is selected 1 Block write is used This bit needs to be reset and set between borders of blocks Flash Memory Control Registers C 3 2 Flash Memory Control Register FCTL2 A PUC resets the flash timing generator The generator is also reset if the emergency exit bit EMEX is set The timing generator generates the timing necessary to write erase and mass erase from a selected clock source Two control bits SSELO and SSEL1 in control register FCTL2 can select one of three clock sources The clock source selected should b
199. G2 test URXIFG signal to JNE ST COND check if frame start condition ST COND BIC B 4URXSE amp UOTCTL clear ff signal URXS stop further interrupt requests BIS B 4URXSE amp UOTCTL Prepare FF URXS for next frame start bits and set the conditions to run the clock needed for UART RX Ne Ne Ne Note Break Detect BRK Bit With Halted UART Clock If the UART operates with the wake up on start condition mode and switches off the UCLK whenever a character is completely received a communication line break cannot be detected automatically by the UART hardware The break detection requires the baud rate generator BRSCLK but it is stopped upon the missing UCLK 13 6 2 Maximum Utilization of Clock Frequency vs Baud Rate UART Mode The current consumption increases linearly with the clock frequency It should be kept to the minimum required to meet application conditions Fast communication speed is needed for calibration and testing in manufacturing processes alarm responses in critical applications and response time to human requests for information MSP430 USART can generate baud rates up to one third of the clock frequency An additional modulation of the baud rate timing adjusts timing for individual bits within a frame The timing is adjusted from bit to bit to meet timing requirements even when a noninteger division is needed Baud rates up to 4800 baud can be generated from a 32 768 Hz c
200. IFG1to CCIFG2 flags and TBIFG 44xuses Timer B7 with CCIFGO PEE to o CCIFGS and TBIFG t USARTI is implemented in 44x only NOTES 4 Multiple source flags 5 Interrupt flags are located in the module 6 Non maskable the individual interrupt enable bit can disable an interrupt event but the general interrupt enable can not disable it 3 4 2 1 External Interrupts All eight bits of ports P1 and P2 are designed for interrupt processing of external events All individual I O bits are independently programmable Any combinations of inputs outputs and interrupt conditions are possible This allows easy adaptation to different I O configurations See Chapter 8 for more details on I O ports 3 5 Operating Modes The MSP430 family was developed for ultralow power applications and uses different levels of operating modes The MSP430 operating modes shown in Figure 3 10 give advanced support to various requirements for ultra low power and ultralow energy consumption This support is combined with an 3 20 Operating Modes intelligent management of operations during the different module and CPU states Aninterrupt event wakes the system from each of the various operating modes and the RETI instruction returns operation to the mode that was selected before the interrupt event The ultralow power system design which uses complementary metal oxide semiconductor CMOS technology takes into account three different needs The desire
201. L1 is shown and described below 7 0 CACTL1 CA CA CA 059h CAEX RSEL REF1 REFO CAON CAIES CAIE CAIFG rw 0 CAIE bit1 CAIES bit2 CAON bit3 CAREF bit4 5 CARSEL bit6 CAEX bit7 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 The Comparator_A interrupt flag The Comparator_A interrupt enable The Comparator_A interrupt edge select bit 0 The rising edge of the comparator output sets the Comparator_A interrupt flag CAIFG 1 The falling edge of the comparator output sets the Comparator_A interrupt flag CAIFG The comparator is switched on or off When off the current consumption of the comparator is stopped The current consumption of the reference circuitry is enabled or disabled independently 0 The comparator is disabled current consumption is stopped and the output of the comparator is low 1 The comparator is enabled and active 0 Internal reference is switched off An external reference can be applied 1 0 25 Vcc reference is selected 2 0 50 Vcc reference is selected 3 Diode reference is selected The diode reference varies with each individual device temperature and supply voltage See device data sheet The internal reference VcAngr selected by CAREF bits is applied to the terminal or terminal 0 Reference is selected to the terminal CAEX 0 or terminal CAEX 1 1 Reference is selected to the terminal CAEX 0 or terminal CAEX 1 The
202. LA Instruction Set Description B 29 Instruction Set Overview INC W INC B Syntax Operation Emulation Description Status Bits Mode Bits Example B 30 Increment destination Increment destination INC dst or INC W dst INC B dst dst 1 dst ADD 1 dst The destination operand is incremented by one The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise V Set if dst contained O7FFFh reset otherwise Set if dst contained 07Fh reset otherwise OscOff CPUOff and GIE are not affected The status byte of a process STATUS is incremented When it is equal to 11 a branch to OVFL is taken INC B STATUS CMPB 11 5 5 JEQ OVFL INCD W INCD B Syntax Operation Emulation Emulation Example Status Bits Mode Bits Example Example Instruction Set Overview Double increment destination Double increment destination INCD dst or INCD W dst INCD B dst dst 2 dst ADD 2 dst ADD B 2 dst The destination operand is incremented by two The original contents are lost N Setif result is negative reset if positive 7 Set if dst contained OFFFEh reset otherwise Set if dst contained OFEh reset otherwise C Setif dst contained OFFFEh or OFFFFh reset otherwi
203. LL CALL CALL CALL CALL CALL CALL Callonlabel EXEC or immediate address e g 0A4h SP 2 5 SP 2 5 SP PC PC EXEC Call on the address contained in EXEC SP 2 2 SP PC 2 2 SP X PC gt PC Indirect address amp EXEC Call on the address contained in absolute address EXEC SP 2 2 SP PC 2 5 SP X PC gt PC Indirect address R5 Call on the address contained in R5 SP 2 gt SP 2 5 SP R5 5 PC Indirect R5 R5 Call on the address contained in the word pointed to by R5 SP 2 SP 2 gt SP R5 gt PC Indirect indirect R5 R5 Call on the address contained in the word pointed to by R5 and increment pointer in R5 The next time S W flow uses R5 pointer it can alter the program execution due to access to next address in a table pointed to by R5 SP 2 5 SP 2 5 GSP R5 gt PC Indirect indirect R5 with autoincrement X R5 Call on the address contained in the address pointed to by R5 X e g table with address starting at X X be an address or a label SP 2 2 SP PC 2 5 SP X R5 gt PC Indirect indirect R5 X Instruction Set Description 17 Instruction Set Overview CLR W CLR B Syntax Operation Emulation Description Status Bits Example Example Example Clear destination Clear destination CLR dst CLR W dst CLR B dst 0 dst MOV 0 dst MOV B 0 dst
204. MPB 2 STATUS JLO STL2 STATUS lt 2 T STATUS gt 2 continue here Instruction Set Description B 39 Instruction Set Overview JNE JNZ Syntax Operation Description Status Bits Example B 40 Jump if not equal jump if not zero JNE label JNZ label If Z 0 PC 2x offset PC If Z 2 1 execute following instruction The status register zero bit Z is tested If it is reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If Z is set the next instruction following the jump is executed Status bits are not affected Jump to address TONI if R7 and R8 have different contents CMP R7 R8 COMPARE R7 WITH R8 JNE TONI if different jump zh if equal continue MOV W MOV B Syntax Operation Description Status Bits Mode Bits Example Loop Example Loop Instruction Set Overview Move source to destination Move source to destination MOV src dst or MOV W 9 src dst MOV B src dst src gt dst The source operand is moved to the destination The source operand is not affected The previous contents of the destination are lost Status bits are not affected OscOff CPUOff and GIE are not affected The contents of table EDE word data are copied to table TOM The length of the tables must be 020h locations MOV EDE R10 Prepare pointer MOV 020h R9 Prepare counter MOV R10 TOM EDE 2 R10 Use pointer in R10 for both tables
205. MSP430x4xx family products by assembling together and presenting hardware and software information in a manner that is easy for engineers and programmers to use This manual discusses modules and peripherals of the MSP430x4xx family of devices Each discussion presents the module or peripheral in a general sense Not all features and functions of all modules or peripherals are present on all devices In addition modules or peripherals may differ in their exact implementation between device families or may not be fully implemented on an individual device or device family Therefore a user must always consult the data sheet of any device of interest to determine what peripherals and modules are implemented and exactly how they are implemented on that particular device How to Use This Manual This document contains the following chapters and appendixes Chapter 1 Introduction Chapter 2 Architectural Overview Chapter 3 System Resets Interrupts and Operating Modes Chapter 4 Memory Chapter 5 16 Bit CPU Chapter 6 Hardware Multiplier Chapter 7 FLL Clock Module Chapter 8 Digital 1 0 Configuration Chapter 9 Watchdog Timer Related Documentation From Texas Instruments Notational Conventions E E Chapter 10 Basic Timer1 Chapter 11 Timer_A Chapter 12 Timer_B Chapter 13 USART Peripheral Interface UART Mode Chapter 14 USART Peripheral Interface
206. Measure resistive elements Detect external voltage or current levels Measure external voltage and current sources Measure the voltage of a battery used in the system 15 4 1 Analog Signals at Digital Inputs Typically Comparator A inputs are multiplexed with digital I O pins When analog signals are applied to these digital CMOS gates parasitic current can flow from the positive terminal Vpp Vcc to the negative terminal Vss GND See Figure 15 4 This parasitic current occurs if the input voltage is around the transition level of the input gate Figure 15 4 Transfer Characteristic and Power Dissipation in a CMOS Inverter Buffer loc 4 Vo VI v 0 Vcc Vss Figure 15 5 Transfer Characteristic and Power Dissipation in a CMOS Gate VI er Vo lcc lcc v Z VI V gt 0 Lo 1 Vss MSP430 devices with the Comparator A module have additional circuitry on the associated digital I O port pins to allow the input buffers to be disabled see Figure 15 5 The buffers are enabled or disabled with the CAPD x bits see Section 15 3 3 Note that the circuitry is added to all pins of the associated I O port not just the pins for the Comparator_A inputs Disabling the input buffer for a specific pin will disable the parasitic current flow and therefore reduce overall current consumption It
207. NORA E eth E HE E HI lil UUL 0 12 3 4 5 4 3 2 1 0 1 2 3 4 3 2 1 011 2 3 21 01 2 10 1 2 3 4 5 4 3 2 11012 1 CCRO 2 Timer A 11 11 Timer Modes 11 4 Capture Compare Blocks Five identical capture compare blocks shown in Figure 11 17 provide flexible control for real time processing Any one of the blocks may be used to capture the timer data at an applied event or to generate time intervals Each time a capture occurs or a time interval is completed interrupts can be generated from the applicable capture compare register The mode bit CAPx in control word CCTLx selects the compare or capture operation and the capture mode bits CCMx1 and in control word CCTLx define the conditions under which the capture function is performed Both the interrupt enable bit CCIEx and the interrupt flag CCIFGx are used for capture and compare modes CCIEx enables the corresponding interrupt CCIFGx is set on a capture or compare event The capture inputs CCIxA and CCIxB are connected to external pins or internal signals Different MSP430 devices may have different signals connected to CCIxA and CCIxB The data sheet should always be consulted to determine the Timer A connections for a particular device Figure 11 17 Capture Compare Blocks CCISx1 CCISx0 o CClxA O o CCkB o GND o Vcc Overflow x Timer Bus
208. NSEQ 3 When this is done the current sequence of conversions is completed normally and no further conversions take place The conversion results are loaded into registers ADC12MEMXx and the corresponding interrupt flags ADC12IFG x are set 2 Reset ENC bit ADC12CTLO 1 This stops the conversions after the current sequence is completed The conversion results of all conversions in the sequence are stored in their appropriate ADC12MEMXx register and the associated interrupt flags ADC12IFG x are set 3 Select repeat single channel mode CONSEQ 2 instead of the repeat sequence of channel mode and then select single channel mode The current conversion is completed normally The current conversion result is loaded into register ADC12MEMx and the associated interrupt flags ADC12IFG x are set The data for x is somewhere between CStartAdd and the last register of the sequence 4 Select single channel mode CONSEQ 0 and reset enable conversion bit ENC The current conversion is stopped immediately The data in memory register ADC12MEMXx is unpredictable and the interrupt flag ADC12IFG x or may not be set This method is generally not recommended Conversion Modes An illustration of repeat sequence of channels mode is shown in Figure 17 12 Figure 17 12 Repeat Sequence of Channels Mode CONSEQ 3 ADC120N 1 ENC x CStartAdd Wait for Enable SHS 0 and 1 or ADC12S
209. Output Unfiltered at CAOUT Comparator Output Filtered at CAOUT 15 2 5 The Voltage Reference Generator 15 4 The voltage reference generator is used to generate VcAnEr can be applied to either of the comparator input terminals Control bits CAREFO and CAREF1 control the output of the voltage generator Control bit CARSEL selects the comparator terminal to which VcAngr is applied If external signals are applied to the comparator input terminals the internal reference generator should be shut off to reduce current consumption The divider in the voltage reference generator can generate a fraction of the device s or a fixed transistor threshold voltage This threshold voltage tolerance is specified in the specific device s data sheet Ratiometric measurement principles that compare unknown values such as resistive or capacitive sensors with a known value such as a precision resistor or capacitor can use an internal reference and achieve accurate results with out an absolute needs to be stable but not necessarily known The accuracy of ratiometric measurements is determined by the accuracy of the known resistor or capacitor value Absolute measurement principles require a stable Vcc to ensure that the voltage reference generated produces accurate reference voltage levels Comparator A Control Registers 15 2 6 Comparator A Interrupt Circuitry One interrupt a
210. P Clears the CPUOff bit in the SR contents that were stored on the stack RETI RETI restores the CPU to the active state because the SR values that are stored on the stack were manipulated This occurs because the SR is pushed onto the stack upon an interrupt then restored from the Stack after the RETI instruction 3 5 2 Low Power Modes 2 and 3 LPM2 and LPM3 Low power mode 2 or 3 is selected if bits CPUOff and SCG1 in the status register are set Immediately after the bits are set CPU and MCLK operations halt and all internal bus activities stop until an interrupt request or reset occurs Peripherals that operate with the MCLK signal are inactive because the clock signal is inactive Peripherals that operate with the ACLK signal are active or inactive according with the individual control registers and the module enable bits in the SFRs All port pins and the RAM registers are unchanged Wake up is possible by enabled interrupts coming from active peripherals or RST NMI 3 5 3 Low Power Mode 4 LPM4 In low power mode 4 all activities cease only the RAM contents ports and registers are maintained Wake up is only possible by enabled external interrupts Before activating LPM4 the software should consider the system conditions during the low power mode period The two most important conditions are environmental that is temperature effect on the DCO and the clocked operation conditions
211. P POP SP instruction sequence The POP SP instruction places SP1 into the stack pointer SP SP2 SP1 is stack pointer after this instruction is stack pointer after this instruction The stack pointer is two bytes lower than before this sequence 16 Bit CPU 5 3 CPU Registers 5 1 3 The Status Register SR The status register SR contains the following CPU status bits OV Overflow bit 0 SCG1 System clock generator control bit 1 Li SCGO System clock generator control bit 0 Li OscOff Crystal oscillator off bit J CPUOff CPU off bit General interrupt enable bit g N Negative bit uz Zero bit Oc Carry bit Figure 5 5 shows the SR bits Figure 5 5 Status Register Bits 15 9 8 7 0 OSC CPU Reserved For Future Enhancements SCG1 SCGO rw 0 Table 5 2 describes the status register bits Table 5 2 Description of Status Register Bits Bit Description V Overflow bit Set if the result of an arithmetic operation overflows the signed variable range The bit is valid for both data formats byte and word ADD B ADDC B Set when Positive Positive Negative Negative Negative Positive otherwise reset SUB B SUBC B CMP B Set when Positive Negative Negative Negative Positive Positive otherwise reset SCG1 SCGO These bits control four activity states of the system clock generator and therefore influence the operation of the processor system OscOFF If set the crystal osci
212. P430 Interrupt Priority Scheme Figure 3 6 Block Diagram of NMI Interrupt Sources ACCV S FCTL1 1 ACCVIE Flash Module IE1 5 Flash Module Clear Flash Module ACCVIFG KEYV VCC PUC System Reset Generator POR p NMIRS IES TMSEL NMI WDTQn EQU PUC POR A A WDT Counter OSCFault OFIFG E IFG1 1 OFIE IE1 1 Clear NMI IRQA PUC IRQA Interrupt Request Accepted PUC Watchdog Timer Module Figure 3 7 RST NMI Mode Selection 7 0 enr HOLD NMIES NMI TMSEL CNTCL ssEL rw 0 rw 0 rw 0 rw 0 w 0 rw 0 rw 0 rw 0 System Resets Interrupts and Operating Modes 3 9 MSP430 Interrupt Priority Scheme BITS 0 4 7 See Watchdog Timer chapter BIT 5 BIT 6 3 3 1 3 3 2 The NMI bit selects the function of the RST NMI input pin It is cleared after a PUC signal NMI 0 The RST NMI input works as reset input As long as the RST NMI pin is held low the internal PUC signal is active level sensitive NMI 1 The RST NMI input works as an edge sensitive non maskable interrupt input This bit selects the activating edge of the RST NMI input if the NMI function is selected It is cleared after a PUC signal NMIES 20 A rising edge triggers an NMI interrupt NMIES 21 A falling edge triggers an NMI interrupt Operation of Global Interrupt Reset NMI Ifthe RST NMI pin is s
213. PU Off FLL Off MCLK On ACLK On CPUOff 1 SCGO 0 SCG1 1 LP Mode LPM2 CPU Off FLL Off MCLK Off ACLK On System Resets Interrupts and Operating Modes CPUOff 1 SCG0 1 1 RST NMI NMI Active CPUOff 1 OscOff 1 0 1 X LP Mode LPM4 CPU Off FLL Off MCLK Off ACLK Off DC Generator Off LP Mode LPM3 CPU Off FLL Off MCLK Off ACLK On DC Generator Off 3 23 Operating Modes Figure 3 12 Typical Current Consumption vs Operating Modes 3 5 1 3 24 450 405 360 315 270 225 180 135 90 45 0 ICC LA AM LPMO LPM2 LPM3 LPM4 Operating Modes The low power modes 1 4 enable or disable the CPU and the clocks In addition to the CPU and clocks enabling or disabling specific peripherals may further reduce total current consumption of the individual modes The activity state of each peripheral is controlled by the control registers for the individual peripherals An example is the enable disable function of the segment lines of the LCD peripheral they can be turned on or off using a single register bit in the LCD control and mode register In addition the SFRs include module enable bits that may be used to enable or disable the operation of specific peripheral modules see Table 3 4 Low Power Modes 0 and 1 LPMO and LPM1 Low power mode 0 or 1 is selected if bit CPUOff in the status re
214. PWM Reset Set TIMOV EQUO gg TIMOV eguz EQUO pouz Interrupt Events 11 5 Timer A Registers The Timer_A registers described in Table 11 3 are word structured and must be accessed using word instructions Table 11 3 Timer A Registers Register Short Form Register Type Address Initial State Timer A control TACTL Read write 160h POR reset Timer A register TAR Read write 170h POR reset Cap com control 0 CCTLO Read write 162h POR reset 0 CCRO Read write 172h POR reset Cap com control 1 CCTL1 Read write 164h POR reset Capture compare 1 CCR1 Read write 174h POR reset Cap com control 2 CCTL2 Read write 166h POR reset Capture compare 2 CCR2 Read write 176h POR reset Interrupt vector TAIV Read 12Eh POR reset 11 22 11 5 1 Timer A Control Regis The timer Timer A Registers ter TACTL and timer operation control bits are located in the timer control register TACTL shown in Figure 11 27 All control bits are reset automati cally by the POR signal but are not affected by the PUC signal The control register must be accessed using word instructions Figure 11 27 Timer A Control Register TACTL 15 0 TACTL Input Input Mode Un rw rw rw rw rw rw rw w rw rw rw rw rw rw 0 0 0 0 Bit 0 Bit 1 Bit 2 Bit 3 Bits 4 5 Table 11 4 Mode Control rw rw 0 0 9 9 0 0 0 0 0 0 TAIFG This flag indicates a timer overflow event
215. RLA Substitution The assembler does not recognize the instruction RLA R5 nor RLAB R5 It must be substituted by ADD R5 2 R5 or ADD B R5 1 R5 Instruction Set Description B 47 Instruction Set Overview RLC W RLC B Syntax Operation Emulation Description Rotate left through carry Rotate left through carry RLC dst or RLC W dst RLC B dst lt MSB 1 LSB 1 lt LSB lt C ADDC dst dst The destination operand is shifted left one position as shown in Figure 7 The carry bit C is shifted into the LSB and the MSB is shifted into the carry bit C Figure B 7 Destination Operand Carry Left Shift Status Bits Mode Bits Example Example Example Example B 48 0 Byte 7 0 Set if result is negative reset if positive Set if result is zero reset otherwise Loaded from the MSB Set if arithmetic overflow occurs reset otherwise Set if OSFFFh lt dstinitiaj lt 0C000h reset otherwise Set if OSFh lt lt OCOh reset otherwise OscOff CPUOff and are not affected R5 is shifted left one position RLC R5 R5 x 2 C R5 The input P11N 1 information is shifted into the LSB of R5 BIT B 2 amp 1 Information Carry RLC R5 0 1 LSB of R5 The MEM LEO content is shifted left one position RLC B LEO Mem LEO x 2 Mem LEO The input P1IN 1 information is to be shi
216. RT Mode Disabling the transmitter should be done only if all data to be transmitted has been movedtothe transmit shift register Data is moved from UTXBUF to the transmit shift register on the next bit clock after the shift register is ready MOV B amp U0TXBUF BIC B UTXE 0 amp ME2 If BITCLK lt MCLK then the transmitter might be stopped before the buffer is loaded into the transmitter shift register _______ Interrupt and Enable Functions 13 4 3 USART Receive Interrupt Operation In the receive interrupt operation shown in Figure 13 14 the receive interrupt flag URXIFG is set or is unchanged each time a character is received and loaded into the receive buffer Erroneous characters parity frame or break error do not set interrupt flag URXIFG when URXEIE is reset URXIFG is unchanged All types of characters URXWIE 0 or only address characters URXWIE 1 set the interrupt flag URXIFG When URXEIE is set erroneous characters can also set the interrupt flag URXIFG Figure 13 14 Receive Interrupt Operation SYNC Valid Start Bit URXS Receiver Collects Character d URXSE e From URXD eee 6 05 Erroneous Character Will Not Set Flag URXIFG EE URXIE Request _ BRK SYNC Interrupt Service URXEIE URXIFG URXWIE RXWake SWRST Each Character or Addre
217. RXE Listen MM SYNC Leho SOMI Receive Shift Register gt URXD SSEL1 SSELO SYNC a 0 Baud Rate Generator 0 UCLKI ES STE ACLK e 2 Baud Rate Register lt SMCLK o 3 U1BR or UOBR SMCLK o o gt Boum UTXD Ir gt Baud Rate Generator UCLKS Transmit Shift Register ole SIMO OX D TXWake CKPH SYNC Transmit Buffer U1TXBUF or UOTXBUF UCLKI Clock Phase and Polarity UCLKS 14 2 14 2 USART Peripheral Interface SPI Mode The USART peripheral interface is a serial channel that shifts a serial bit stream of 7 or 8 bits in and out of the MSP430 The SPI mode is chosen when control bit SYNC in the USART control register UOCTL for UARTO and U1CTL for USART1 is set 14 2 1 SPI Mode Features The features of the SPI mode are Supports three pin and four pin SPI operations via SOMI SIMO UCLK and STE Master or slave mode Separate shift registers for receive UXRXBUF and transmit UxTXBUF Double buffers for receiving and transmitting Has clock polarity and clock phase control Has clock frequency control in master mode t Supports a character length of seven or eight bits per character Figure 14 2 shows the USART module in SPI mode Figure 14 2 Block Diagram of USART SPI Mode SYNC 1 Receive Buffer SLM RES Receive Status U1RXBUF or UORXBUF T m pd SOMI i Q e o Receive Shift Register M
218. S7C2 S7C1 S7C0 S6C3 S6C2 S6C1 S6CO 094h rw rw rw rw rw rw rw rw LCD memory 3 S5C3 S5C2 S5C1 5 0 S4C3 S4C2 4 1 S4CO 093h rw rw rw rw rw rw rw rw LCD memory 2 S3C3 S3C2 3 1 S3C0 S2C3 S2C2 S2C1 S2C0 092h rw rw rw rw rw rw rw rw LCD memory 1 103 S1C2 S1C1 1 0 S0C3 S0C2 0 1 S0CO 091h rw rw rw rw rw rw rw rw LCD control amp mode LCDM7 LCDM6 LCDM5 LCDM4 LCDM3 LCDM2 LCDM1 LCDMO 090h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Note TheLCD memory bits are named with the MSP430 convention The first part of the bit name indicates the corresponding segment line and the second indicates the corresponding common line Example for a segment using S4 and Com3 S4C3 Ww Ww W r r r Ww wW 17C3 17 2 17 1 17C0 S16C3 S16C2 16 1 16 0 r r r Ww W rw rw Ww wW Ww wW Peripheral File Map A 11 Watchdog Timer Word Access A 12 Watchdog Timer Word Access Bit 15 Watchdog Timer Read as 069h Control register WDTCTL Written as 05Ah 120h Bit 4 7 6 5 4 3 2 Watchdog Timer 1 HOLD NMIES NMI TMSEL CNTCL SSEL IS1 A 13 Flash Control Registers Word Access Bit 4 15 14 13 12 11 10 9 8 FCTL3 Read as 096h 012Ch Written as 0A5h FCTL2 Read as 096h 012Ah Written as 0A5h FCTL1 Read as 096h 0128H Written as 0A5h Bit 7 6 5 4 3 2 1 FCTL3 Reserved Reserved EMEX Lock WAIT ACCVIFG KEYV Busy 012Ch ro ro rw 0 rw 1 1 rw 0 rw 0 r w
219. SB First A UCLKI 2 SMCLK o oJ T MSB First Transmit Shift Register ES gt SIMO 0 Transmit Buffer U1TXBUF or UOTXBUF CKPH SYNC CKPL UCLKI UCLKS USART Peripheral Interface SPI Mode 14 3 Synchronous Operation 14 3 Synchronous Operation 14 4 In USART synchronous mode data and clock signals transmit and receive serial data The master supplies the clock and data The slaves use this clock to shift serial information in and out The four pin SPI mode also uses a control line to enable a slave to receive and transmit data The line is controlled by the master Three or four signals are used for data exchange SIMO Slave in master out The direction is defined by SIMODIR SIMODIR 0 input direction SIMODIR SYNC and MM and STC or STE Output direction is selected when SPI Master Mode is selected When 4 pin SPI is selected STC 0 input direction is forced by a low level on external STE pin SOMI Slave out master in The direction is defined by SOMIDIR SIMODIR 0 input direction SOMIDIR SYNC and not MM or STC or not STE Output direction is selected when SPI Slave Mode is selected When 4 pin SPI is selected STC 0 input direction is forced by a low level on external STE pin UCLK USART clock The master drives this signal and the slave uses it to receive and transmit data The direction is defined by UCLKDIR
220. SC bit the bit can remain set or may be set at the same time as ADC10SC However when any other trigger source ADC10I1 ADC1012 or ADC1013 is being used to start conversions the ENC bit must be toggled between each conversion All additional incoming sample input signals will be ignored until the ENC bit is reset and set again The conversion mode may be changed after the conversion begins but before ithas completed and the new mode will take effect after the current conversion has completed See also the Switching between Conversion Modes section An illustration of single channel single conversion mode is shown in Figure 17 5 17 10 Conversion Modes Figure 17 5 Single Channel Single Conversion Mode CONSEQ 0 x CStartAdd Pd Wait for Enable SHS 0 1 or ADC12SC 4 hy j ENC 0 SAMPCON 4 MN SAMPCON 1 id Sample Input Channel Defined in ot ADC12MCTLx SAMPCON Y lt 12 x ADC12CLK Es Convert Use 12 x ADC12CLK ENC ot 1 x ADC12CLK ET Conversion N Completed n Result Stored Into ADC12MEMXx ADC12IFG x Is Set T Conversion result is unpredictable An example of the conversion memory setup is shown in Figure 17 6 for single channel conversion The example uses the following conditions Single conversion of channel a4 L Internal reference voltage with Vp at AVcc and w
221. SWRST Unused The TXWake bit controls the transmit features of the multiprocessor communication modes Each transmission started by loading the UxTXBUF uses the state of the TXWake bitto initialize the address identification feature It must not be cleared the USART hardware clears this bit once it is transferred to the WUT a SWRST also clears the TXWake bit The receive start edge control bit if set requests a receive interrupt service For a successful interrupt service the corresponding enable bits URXIE and GIE must be set The advantage of this bit is that it starts the controller clock system including MCLK along with the interrupt service and keeps it running by modifying the mode control bits If the selected clock Source is activated then the receive operation starts even from low power modes Source select 0 and 1 The source select bit defines which clock source is used for baud rate generation SSEL1 SSELO 0 External clock UCLKI 1 ACLK 2 9 SMCLK Clock polarity CKPL The CKPL bit controls the polarity of the UCLKI signal CKPL 0 The UCLKI signal has the same polarity as the UCLK signal CKPL 2 1 The UCLKI signal has an inverted polarity to the UCLK signal Unused Control and Status Registers 13 5 3 Receiver Control Register UORCTL UTRCTL The receiver control register shown in Figure 13 18 controls the USART hardware associated with the receiver operation and holds error and wake up co
222. TBR 0 Timer_B 12 25 The Output Unit Table 12 3 State of OUTx at Next Rising Edge of Timer Clock Mode EQUO EQUx D 0 X X X OUTx bit 1 X 0 OUTx no change X 1 1 set 2 0 0 OUTx no change 0 1 OUTx toggle 1 0 0 reset 1 1 1 set 3 0 0 OUTx no change 0 1 1 set 1 0 0 reset 1 1 1 set 4 X 0 OUTx no change x 1 OUTx toggle 5 0 OUTx no change x 1 0 reset 6 0 0 OUTx no change 0 1 OUTx toggle 1 0 1 set 1 1 0 reset 7 0 0 OUTx no change 0 1 0 reset 1 0 1 set 1 1 0 reset 12 5 3 Output Examples The following are some examples of possible output signals using the various timer and output modes 12 5 3 1 Output Examples Timer in Up Mode The OUTx signal is changed when the timer counts up to the TBCLx value and rolls from TBCLO to zero depending on the output mode as shown in Figure 12 24 12 26 Figure 12 24 Output Examples Timer Up Mode The Output Unit TBR max Example EQU1 Used TBCLO TBCL1 Oh Du d Output Mode 1 Set RM Output Mode 2 PWM Toggle Reset ieri cm E Output Mode 3 PWM Set Reset mE Output Mode 4 Toggle Output Mode 5 Reset Sas Output Mode 6 PWM Toggle Set Ium ho il Output Mode 7 PWM Reset Set EQUO EQUi EQUO EQU1 EQUO Interrupt Events 12 5 3 2 Output Examples Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TBCLx and TBCLO values depe
223. TL 079h USART1 USART control U1CTL 078h USARTO Transmit buffer UOTXBUF 077h USARTO Receive buffer UORXBUF 076h USARTO Baud rate UOBR1 075h USARTO Baud rate UOBRO 074h USARTO Modulation control UOMCTL 073h USARTO Receive control UORCTL 072h USARTO Transmit control UOTCTL 071h USARTO USART control UOCTL 070h A 6 rw FE rw 0 Unused rw 0 PENA rw 0 27 rw 27 r 215 rw 27 rw m7 rw FE rw 0 Unused rw 0 PENA rw 0 6 8 rw 0 CKPL rw 0 PEV rw 0 U o eo N i BRIE Oo 2 x gt rw 0 CKPL rw 0 PEV rw 0 5 rw 0 SSEL1 rw 0 SP rw 0 2 aN D IN rw 0 SSEL1 rw 0 SP rw 0 4 23 BRK rw 0 SSELO rw 0 CHAR rw 0 2 R 2 gt N BRK rw 0 SSELO rw 0 CHAR rw 0 3 23 URXEIE rw 0 URXSE rw 0 Listen rw 0 2 0 zN gt o URXEIE rw 0 URXSE rw 0 Listen rw 0 2 2 URXWIE rw 0 TXWAKE rw 0 SYNC rw 0 TN 3N 5 gt 2 URXWIE rw 0 TXWAKE rw 0 SYNC rw 0 1 21 rw 21 r 29 rw 21 rw m1 rw RXWake rw 0 Unused rw 0 MM rw 0 21 rw 21 r 29 rw 21 rw m1 rw RXWake rw 0 Unused rw 0 MM rw 0 20 rw rw RXERR rw 0 TXEPT rw 1 SWRST
224. TO e DADC W DADC B dst dst C dst decimal DADD W DADD B src dst src dst dst decimal DEC W DEC B dst dst 1 dst amy DECD W DECD B dst dst 2 dst DELE DINT Disable interrupt E c EINT Enable interrupt eere INC W INC B dst Increment destination dst 1 dst We ts X INCD W INCD B dst Double Increment destination dst 2 gt dst ae Pad INV W INV B dst Invert destination SS ape a JC JHS Label Jump to Label if Carry bit is set Sg oa JEQ JZ Label Jump to Label if Zero bit is set So rect JGE Label Jump to Label if N XOR V 20 JL Label Jump to Label if N XOR V 1 JMP Label Jump to Label unconditionally JN Label Jump to Label if Negative bit is set JNC JLO Label to Label if Carry bit is reset DE JNE JNZ Label Jump to Label if Zero bit is reset e B 2 MOV W MOV B NOP POPLW POPB PUSH W PUSH B RETI RET RLA W RLA B RLC W RLC B RRA W RRA B RRC W RRC B SBC W SBC B SETC SETN SETZ SUB W SUB B SUBC W SUBC B SWPB SXT TSTLWI TST B XOR W XOR B src dst dst src dst dst dst dst dst src dst src dst dst dst dst src dst Instruction Set Overview Status Bits src gt dst No operation from stack SP 2 SP SP 2 SP src gt SP Return from interrupt TOSS SR SP 2 gt SP TOS gt PC SP 2 SZP Return from
225. UCLKDIR O input direction UCLKDIR SYNC and MM and STC or STE Output direction is selected when SPI Master Mode is selected When 4 pin SPI is selected STC 0 input direction is forced by a low level on external STE pin STE Slave transmit enable Used in four pin mode to control more than one slave in a multiple master and slave system The interconnection of the USART in synchronous mode to another device s serial port with one common transmit receive shift register is shown in Figure 14 3 where MSP430 is master or slave The operation of both devices is identical Synchronous Operation Figure 14 3 MSP430 USART as Master External Device With SPI as Slave Receive Buffer UXRXBUF Transmit Buffer UXTXBUF SPI Receive Buffer Receive Shift Register LSB MSB MASTER MSP430 USART COMMON SPI The master initiates the transfer by sending the UCLK signal For the master data is shifted out of the transmit shift register on one clock edge and shifted into the receive shift register on the opposite edge For the slave the data shifting operation is the same and uses one common register for transmitting and receiving data Master and slave send and receive data at the same time Whether the data is meaningful or dummy data depends on the application software Master sends data and slave sends dummy data Master sends data and slave sends data Master sends dummy data and slave sends
226. URXIFG It operates identically in both multiprocessor modes The wake up interrupt enable feature depends on the receive erroneous character feature See also Bit 3 URXEIE The receive erroneous character interrupt enable bit URXEIE selects whether an erroneous character is to set the interrupt flag URXIFG URXEIE 0 Each erroneous character received does alter the interrupt flag URXIFG URXEIE 1 All characters can set the interrupt flag URXIFG as described in Table 13 4 depending on the conditions set by the URXWIE bit USART Peripheral Interface UART Mode 13 19 Control and Status Registers Table 13 4 Interrupt Flag Set Conditions 13 20 Char Char Description Flag URXIFG URXEIE URXWIE w Error Address After a Character Is Received 0 O O O Bit 4 Bit 5 Bit 6 Bit 7 X 1 X Unchanged Set Unchanged Set Set Receives all characters Unchanged 0 1 1 0 1 1 Set X 0 1 X 0 1 The break detect bit BRK is set when break condition occurs and the URXEIE bit is set The break condition is recognized if the RXD line remains continuously low for at least 10 bits beginning after a missing first stop bit It is not cleared by receipt of a character after the break is detected but is reset by a SWRST a system reset or by reading the UxRXBUF The receive interrupt flag URXIFG is set if a break is detected The overrun error flag bit OE is set
227. UT bit for the status of the comparator or use the interrupt flag CAIFG to determine if the level of the current or voltage source has crossed the comparator threshold In Figure 15 12 two external voltages are compared Application software can poll the CAOUT bit CAOUT 0 V signal lt V ref CAOUT 1 V signal gt V ref Figure 15 12 Detect a Voltage Level Using an External Reference Level oV Vcc 0 11 2 CAREX 5 0 X Signal 0 0 CAOUT to Voltage 9 5 CA1 Set P2CA1 CAIFG x Reference Voltage I CAREF CARSEL vonner 15 16 Voc Y long as CAOUT is reset oV Vcc PeCA0 60 0 CAON CAF 0 Lo e o 4 ES Risense CA1 d d Set 7 2 1 CAIFG Optional T 2US R hyst OV Vcc 40 1 Px y CAON 2 CARSEL __1 2 0 1 0 5 x Voc 0 25 15 4 5 Comparator A Used to Measure a Current or Voltage Level In addition to detecting levels the comparator can be used to measure currents or voltages To measure a voltage a known stable voltage source is used to charge up an RC combination The time required to charge the combination to a threshold value set by the voltage to be measured is then used to calculate the voltage level see Figure 15 16 VcAngr can be used requi
228. When LCDM2 1 each LCD segment is on or off according to the LCD display memory When LCDM2 0 each LCD segment is off therefore blanking the LCD Figure 16 8 Information Control Segment Information lj To Output Control LCDM2 LCDM5 to 7 These three bits select groups of outputs to be used for LCD segment drive or as port function general purpose I O as described in Table 16 2 The pins selected as general purpose function as discussed in Chapter 8 and no longer function as part of the LCD segment lines Liquid Crystal Display Drive 16 11 LCD Controller Driver Table 16 2 LCDM Signal Outputs for Port Functions Function Loc reg HEN MT IEEE BER EE o loejo LE o zem Ep SEES DASS NET ERAT 16 2 6 LCD Memory The LCD memory map is shown in Figure 16 9 Each individual memory bit corresponds to one LCD segment To turn on an LCD segment the memory bit is simply set To turn off an LCD segment the memory is reset The mapping of each LCD segment in an application depends on the connections between the 430 and the LCD and on the LCD pin out Examples for each of the four modes follow including an LCD with pin out the 430 to LCD connections and the resulting data mapping Figure 16 9 Display Memory Bits Attached to Segment Lines in 4xx Family Associated Common Pin Address OA4h OA3h 0A2h OA1h OAOh O9Fh O9Eh 09D
229. XOR FXKEY LOCK amp FCTL3 no End of Block Write MOV FWKEY WRT BLKWRT amp FCTL3 Clear lock bit Flash busy BLKWRT ended Block write All data programmed Program data in this example one byte MOV B Rx Flash_Start_Ptr Start_ptr 1 Rx Block border Test if data written Stop block write Block write ends if busy 0 All data are programmed Stop block write Block write ended Change Lock bit to 1 Flash Memory C 25 Flash Memory Access JTAG and Software C 5 3 4 Example Erase Flash Memory Segment or Module via Software Execution Outside This Flash Module The following sequence can be used to erase a segment or mass erase of segments Erase or Mass Erase FWKEY LOCK amp FCTL3 Reset lock bit Test Busy1 BIT BUSY amp FCTLS3 JNZ Test Busy1 Segment Erase Erase 1 or Mass Erase MEras 1 MOV FWKEY Erase amp FCTL1 select segment erase CLR amp 0F000h Dummy Write yes Test_Busy2 BIT BUSY amp FCTL3 JNZ Test_Busy2 End of Erase or XOR FXKEY LOCK amp FCTL3 Mass Erase C 5 3 5 Example Erase Flash Memory Segment Module in the Same Flash Memory Module via Software Disable all interrupt sources Disable all possible interrupt sources and watchdog and Watchdog MOV FWKEY Eras amp FCTL1 Enable Erase of Flash CLR amp OFAO0h Dummy Write to Flash Erase Segment 2 Program execution in information memo
230. ad New CCRO During High Phase of Clock During Low Phase of Clock T Up mode 0 up down mode 1 T Up mode 0 up down mode n Timer A 11 7 Timer Modes 11 3 3 Timer Continuous Mode The continuous mode is used if the timer period of 65 536 clock cycles is used for the application A typical application of the continuous mode is to generate multiple independent timings In continuous mode the capture compare register CCRO works in the same way as the other compare registers The capture compare registers and different output modes of each output unit are useful to capture timer data based on external events or to generate various different types of output signals Examples of the different output modes used with timer continuous mode are shown in Figure 11 25 In continuous mode the timer starts counting from its present value The counter counts up to OFFFFh and restarts by counting from zero as shown in Figure 11 9 Figure 11 9 Timer Continuous Mode OFFFFh Oh The TAIFG flag is set when the timer counts from OFFFFh to zero The interrupt flag is set independently of the corresponding interrupt enable bit as shown in Figure 11 10 An interrupt is requested if the corresponding interrupt enable bit and the GIE bit are set Figure 11 10 Continuous Mode Flag Setting Timer Clock Timer Set Interrupt Flag TAIFG Timer Modes 11 3 3 1 Timer Use of the Continuous Mode The continuous mode can be us
231. age should be within the devices electrical specifications defined in the respective data sheet however slight variations can be tolerated Control bit BUSY indicates an active erase cycle It is set immediately after a dummy write starts the timing generator It remains set until the entire erase cycle is completed and the erased segment or block is ready to be accessed again The BUSY bit can not be set by software But it can be reset In case of emergency set the emergency exit EMEX bit and the erase operation will be stopped immediately BUSY bit is reset One example of stop erase by soft ware is when the supply voltage drops drastically and the operating conditions of the controller are exceeded Another example is when the timing of the erase cycle gets out of control for example when the clock source signal is lost Flash Memory C 9 Flash Memory Data Structure and Operation Note When the erase cycle is stopped before its normal completion by the hard ware the timing generator is stopped and erasure of the flash memory can be marginal An incomplete erasure can be verified But an erase level of 1 can be inconsistently read as valid when supply voltage temperature access time instruction execution data read and frequency vary C 2 6 Flash Memory Status During Write Programming The flash memory erase bit level is 1 Bits can only be written programmed to a 0 level Once a
232. ait for Trigger ENC 0 SAMPCON 47 SAMPCON 1 Sample Input Channel Defined in ADC12MCTLx SAMPCON Y lt 12 x ADC12CLK MSC 1 and SHP 1 and ENC 1 Convert Use 12 x ADC12CLK 1 x ADC12CLK Conversion Completed Result Stored Into ADC12MEMXx ADC12IFG x Is Set 17 5 4 Repeat Sequence of Channels Mode The repeat sequence of channel mode is identical to the sequence of channel mode except the sequence is repeated continuously until stopped by software Each time a conversion is completed the results are loaded into the appropriate ADC12MEMXx register and the corresponding interrupt flag ADC12IFG x is set to indicate completion of the conversion Additionally If the appropriate interrupt enable flags are set an interrupt request is generated see the ADC12 Interrupt Vector Register ADC 12IV section The conversion mode may be changed without first stopping the conversions When this is done the new mode takes effect after the current sequence ADC12 17 17 Conversion Modes 17 18 completes except when the new mode is repeat single channel In this case the sequence does not complete and the new mode takes effect immediately see also the Switching Between Conversion Modes section There are four ways to stop repeat sequence of channels conversions 1 Select sequence of channels mode CONSEQ 1 instead of repeated sequence of channels mode CO
233. als and memory sizes enabling true system on a chip designs The peripherals include a 12 bit A D slope A D timers some with capture compare registers and PWM output capability an LCD driver on chip clock generation a hardware multiplier USART a Watchdog Timer GPIO and others See http www ti com for the latest device information and literature for the MSP430 family Topic Page 1 1 Features and Capabilities 1 2 1 25 1 3 1 3 1 4 44X Devices eles 1 4 Features and Capabilities 1 1 Features and Capabilities The TI MSP430x4xx family of controllers has the following features and capabilities Ultralow power architecture 0 1 300 nominal operating current at 1 MHz 1 8 3 6 V operation 6 wake up from standby mode Extensive interrupt capability relieves need for polling Flexible and powerful processing capabilities Seven source address modes Four destination address modes Only 27 core instructions Prioritized nested interrupts No interrupt or subroutine level limits Large register file Ram execution capability Efficient table processing Fast hex to decimal conversion Extensive memory mapped peripheral set including 12 bit A D converter Integrated precision comparator Multiple timers and PWM capability Slope A D conversion all devices Integrate
234. alted by CCRO 0 restarted by CCRO gt 0 when the mode is either up or up down When the timer mode is selected to be either up or up down the timer may be stopped by writing O to capture compare register O CCRO The timer may then be restarted by writing a non zero value to CCRO In this scenario the timer starts incrementing in the up direction from zero Setting the CLR bit in TACTL register Setting the CLR bit in the TACTL register clears the timer value and input clock divider value The timer increments upward from zero with the next clock cycle as long as stop mode is not selected with the MCx bits TAR is loaded with 0 When the counter TAR register is loaded with zero with a software instruction the timer increments upward from zero with the next clock cycle as long as stop mode is not selected with the MCx bits 11 3 1 Timer Stop Mode Stopping and starting the timer is done simply by changing the mode control bits MCx The value of the timer is not affected When the timer is stopped from up down mode and then restarted in up down mode the timer counts in the same direction as it was counting before it was stopped For example if the timeris in up down mode and counting in the down direction when the MCx bits are reset when they are set back to the up down direction the timer starts counting in the down direction from its previous value If this is not desired in an application the CLR bit in the TACTL regis
235. always reads EMEX as 0 C 4 Flash Memory Interrupt and Security Key Violation One NMI vector is used for three non maskable interrupt NMI events RST NMI oscillator fault OFIFG and flash access violation ACCVIFG The soft ware can determine the source of the interrupt request by testing interrupt flags NMIIFG OFIFG and ACCVIFG They remain setuntil reset by software Flash Memory Interrupt and Security Key Violation Figure C 10 Access Violation Non Maskable Interrupt Scheme in Flash Memory Module ACCV S ACCVIFG FCTL1 1 gt Flash Module Flash Module F Flash Module IE1 5 Clear v RST NMI System Reset Generator 4 2 OF OS 4 94 4 4 r L 4 NMIIFG ole IFG1 4 ar NMIRS gt EQU POR i PUC r 7 NMIIE e WDTIFG meg E NI z gt z isi o 2 IE1 4 IRQ Counter EN emat L oL IE1 0 Clear IE1 4 Clear A e Watchdog Timer Module PUC NMI_IRQA ah EE IRQA Interrupt Request Accepted Flash Memory C 19 Flash Memory Interrupt and Security Key Violation C 4 1 Example of an NMI Interrupt Handler Start of NMI Interrupt Handler Reset by HW OFIE NMIE NMIIFG r rp Reset OFIFG Reset NMIIFG
236. ansmit data buffer UxTXBUF shown in Figure 14 22 contains current data for the transmitter to transmit Figure 14 22 Transmit Data Buffer UOTXBUF U1TXBUF 14 20 7 7 0 UOTXBUF 077h s los la P wager T T2 T2 rw rw rw rw rw rw rw rw The UTXIFG bit indicates that UXTXBUF is ready to accept another character for transmission In master mode the transmission is initialized by writing data to UxTXBUF The transmission of this data is started on the next bit clock if the transmit shift register is empty When seven bit character length is used the data moved into the transmit buffer must be left justified since the MSB is shifted out first a a a Note Writing to UxTXBUF Writing data to the transmit data buffer must only be done if buffer UxT XBUF is empty otherwise an unpredictable character can be transmitted ss Chapter 15 Comparator A The Comparator A peripheral module is used to compare analog signals to support various forms of analog to digital conversion The Comparator A module includes Comparator with on off capability and no input hysteresis _j Internal analog voltage reference generator Internal reference levels available externally Input multiplexer to exchange the comparator terminals Software selectable RC filter at the comparator output One interrupt vector Topic Page 15 1 A
237. ap com control Capture compare 3T Cap com control 4T Capture compare 4t Capture compare 51 Capture compare 5t Capture compare 6T Capture compare 6t Interrupt vector Short Form TBCTL TBR TBCCTLO TBCCRO TBCCTL1 TBCCR1 TBCCTL2 TBCCR2 TBCCTL3 TBCCR3 TBCCTL4 TBCCR4 TBCCTL5 TBCCR5 TBCCTL6 TBCCR6 TBIV Register Type Address Initial State Read write 180h POR reset Read write 190h POR reset Read write 182h POR reset Read write 192h POR reset Read write 184h POR reset Read write 194h POR reset Read write 186h POR reset Read write 196h POR reset Read write 188h POR reset Read write 198h POR reset Read write 18Ah POR reset Read write 19Ah POR reset Read write 18Ch POR reset Read write 19Ch POR reset Read write 18Eh POR reset Read write 19Eh POR reset Read 11Eh POR reset T TBCCTL3 TO TBCCTL6 and TBCCR3 to TBCCR6 implemented in 44x devices only 12 6 1 Timer B Control Register TBCTL The timer and timer operation control bits are located in the timer control register TBCTL shown in Figure 12 27 control bits are reset automati cally by the POR signal but are not affected by the PUC signal The control register must be accessed using word instructions Figure 12 27 Timer B Control Register TBCTL 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 0 0 0 rw 0 0 0 0 0 TBIFG This flag indicates a timer overflow event
238. are register TBCCRx are taken by the software in the according interrupt routine E they are taken only after a CCIFG was set The timer clock is much slower than the system clock MCLK TBCCRx Int hand Start of interrupt handler CMP amp amp Test if the data TBCCRX TBR JEQ Data Valid MOV amp TBR amp The data in TBCCRx is wrong use the timer data Data Valid sd The data in TBCCRx are valid RETI F Overflow logic is provided with each capture compare register to flag the user if a second capture is performed before data from the first capture was read successfully Bit COVx in register TBCCTLx is set when this occurs as shown in Figure 12 20 Figure 12 20 Capture Cycle Idle Capture Capture Read Read Taken Capture No Capture Taken Capture Taken Capture Capture Read and No Capture Capture Clear Bit COV in Register TBCCTL Second Capture Taken COV 1 Idle Timer_B 12 17 Timer Modes Overflow bit COVx is reset by the software as described in the following example Software example for the handling of captured data looking for overflow condition The data of the capture compare register TBCCRx are taken by the software and immediately with the next instruction the overflow bit is tested and a decision is made to proceed regularly or with an error
239. ation in watchdog mode only A Watchdog Timer security key violation A low signal on the RST NMI pin when configured in the reset mode DL D DD Q A Flash memory security key violation SS Note If desired software can cause a by simply writing to the watchdog timer control register with an incorrect password 3 2 System Reset and Initialization 7 4 Note Generation ofthe POR PUC signals does not necessarily generate a system reset interrupt Anytime a POR is activated a system reset interrupt is generated However when a PUC is activated a system reset interrupt may or may not be generated Instead a lower priority interrupt vector may be generated depending on what action caused the PUC Each device data sheet gives a detailed table of what action generates each interrupt This table should be consulted for the proper handling of all interrupts ________ Two circuits monitor the supply voltage as shown Figure 3 2 brownout reset circuit detects low supply voltages such as when a supply voltage is ap plied to or removed from the Vcc terminal whereas the supply voltage supervi sor circuit SVS detects if the supply voltage connected to the Vcc terminal drops below the minimum supply voltage that is recommended for operation The SVS function is off at reset and power up to conserve power The SVS function may be activated b
240. ation of the USART module The register bits select the communication mode and the number of bits per character All bits should be programmed to the desired mode before resetting the SWRST bit Figure 14 15 USART Control Register 14 16 UOCTL 070h CHAR Li SYNC MM SWRST U1CTL 078h Unused Unused Unused isten rw 0 rw 0 rw 0 rw 0 rw 0 rw O0 rw O0 rw 1 Bit 0 The USART state machines and operating flags are initialized to the reset condition URXIFG USPIIE 0 UTXIFG 1 if the software reset bit is set Until the SWRST bitis reset all affected logic is held in the reset state This implies that after a system reset the USART must be reenabled by resetting this bit I DLO 3 Note The USART initialization sequence should be Initialize per application requirements while leaving SWRST 1 Clear SWRST Enable interrupts if desired X Bit 1 Master mode is selected when the MM bit is set The USART module slave mode is selected when the MM bit is reset Bit 2 Peripheral module mode select The SYNC bit sets the function of the USART peripheral interface module Some of the USART control bits have different functions in UART and SPI modes SYNC 0 UART function is selected SYNC 1 SPI function is selected Bit 3 The listen bit determines the transmitted data to feed back internally to the receiv
241. atment with negative numbers of the subroutine called CLRN CALL SUBR JN SUBRET input is negative do nothing and return RET CLRZ Operation Emulation Description Status Bits Mode Bits Example Instruction Set Overview Clear zero bit CLRZ 02Z or NOT src AND dst dst BIC 2 SR The constant 02h is inverted OFFFDh and logically ANDed with the destination operand The result is placed into the destination The clear zero bit instruction is a word instruction N Not affected Z Resetto 0 C Not affected V Not affected OscOff CPUOff and GIE are not affected The zero bit in the status register is cleared CLRZ Instruction Set Description B 21 Instruction Set Overview CMPI W CMP B Syntax Operation Description Status Bits Mode Bits Example Example Example B 22 Compare source and destination Compare source and destination CMP src dst or CMP W src dst CMP B src dst dst NOT src 1 or dst src The source operand is subtracted from the destination operand This is accomplished by adding the 1s complement of the source operand plus 1 The two operands are not affected and the result is not stored only the status bits are affected N Set if result is negative reset if positive src gt dst Z Set if result is zero reset otherwise src dst C Set if there is a carry from the MSB of the result reset otherwise V Set
242. be correct but the programming is marginal Reading of the data may be inconsistently valid when varying the supply volt age the temperature the access time instruction execution data read or the time LLL 3 Flash Memory Data Structure and Operation Figure C 8 Basic Flash Memory Module Timing During Write Single Byte or Word Cycle lt gt lt gt lt gt Programming Operation Active Generate Remove Programming Voltage Entire Programming Cycle Timing Programming Voltage lt Time of Increased Current Consumption From Supply VCC BUSY 33 fx Figure C 9 Basic Flash Memory Module Timing During Block Write Cycle BLKWRT bit Write to Flash e g MOV 1231 amp Flash Y 55 31 313 EE t gt 574 0 Programming Operation Active Remove Programming Voltage Programming Voltage Entire Programming Cycle Timing gt Time of Increased Current Consumption From Supply VCC BUSTI lt W prog all lt 2578 _ WAIT I 1 30 fx liprog2 20 fx Uprog2 20 fx The block write can be used on sequential addresses of the memory module One block is 64 bytes long starting at Oxx00h Oxx40h 0xx80h or OxxCOh and ending at Oxx3Fh Oxx7Fh OxxBFh or OxxFFh Examples of sequential block addresses are l prog3 5 fx OF00
243. bit is programmed only the erase function can reset it back to the 1 level The byte or word 0 level can not be written programmed in one cycle Any bit can be programmed from 1 to 0 at any time but not from 0 to 1 Two slightly different write operations can be performed write a single byte or word of data or write a sequence of bytes or words A write sequence of bytes or words can be performed as multiple sequential or as a block write The block write is approximately twice as fast as a multiple sequential write algorithm The write program operation starts with the following sequence Setthe correct input clock frequency of the timing generator by selecting the clock source and predivider Reset the LOCK control bit if set Watch the BUSY bit Continue with the next steps only if the BUSY bit is reset Set the write control bit WRT when a single byte of word data is to be written Set the write WRT and BLKWRT control bits when block write is chosen to write multiple bytes or words to the flash memory module L Writing the data to the selected address starts the timing generator The data is written programmed while the timing generator proceeds Note Whenever the write cycle is stopped before its normal ending by the hard ware the timing generator is stopped and the data written to the flash memory can be marginal The data may be incorrect which can be verified or the data are verified to
244. bits in ADC12MCTLx ADC12MCTL x 1 ADC12MCTL y 1 are reset Result is in ADC12MEMx ADC12MEMx 1 interrupt flag is ADC12IFG x ADC12IFG x 1 More than one sequence is possible Channel INCH and reference voltage Sref are selected in ADC12MCTLx 17 5 1 Single Channel Single Conversion Mode The single channel mode converts a single channel once The channel to be converted is selected by the INCH bits in the conversion memory control regis ter ADC12MCTLx associated with the conversion memory register pointed to by the CStartAdd bits located ADC12CTL1x The conversion range ADC12 17 9 Conversion Modes Vp is configured in the same conversion memory control register by the Sref bits The conversion result is stored in conversion memory register ADC12MEMXx pointed to by the CStartAdd bits The conversion may be stopped immediately by resetting the enable conversion bit ENC located in ADC12CTLO but the conversion results will be unreliable or the conversion may not be performed This is illustrated in Figure 17 4 Figure 17 4 Stopping Conversion With ENC Bit ENC and ADC12SC ENC and ADC12SC may be set together may be set together ENC SAMPCON ben Sample Period Conversion Period Sample Period Conversion Period Operational Mode ENC is reset before conversio
245. bits with four MSBs equal to 1h L byte operation identifier one bit B W L destination field six bits destination register Ad The destination field is composed of two addressing bits and the four bit register number 0 15 The destination field bit position is the same as that of the two operand instructions The byte identifier B W indicates whether the instruction is executed as a byte B W 1 or as a word B W 0 Figure 2 Single Operand Instructions 15 12 1 10 9 7 6 5 4 3 0 Operational Code Field Destination Field Status Bits VN ZC RRA W RRA B dst MSB MSB LSB gt C Os te RRC W RRC B dst MSB LSB gt C PUSH W PUSH B dst 5 2 5 5 SP SWPB dst swap bytes mE CALL dst PC 2 SP dst gt PC RETI dst TOSS SR SP 25 SP VEA S TOS gt PC SP 2 gt SP SXT dst Bit 7 Bit 8 Bit 15 Qm ow os B 1 2 Conditional and Unconditional Jumps Core Instructions The instruction format for conditional and unconditional jumps as shown in Figure B 3 consists of two main fields to form a 16 bit code operational code op code field six bits jump offset field ten bits The operational code field is composed of the op code three bits and three bits according to the following conditions Figure B 3 Conditional and Unconditional Jump Instructions 15 13 312 10 9 0 OP Code Jump On Cone Sign Offset Opera
246. btract LSDs SBC B 1 R12 Subtract carry from MSD Note Borrow Is Treated as a NOT The borrow is treated carry Borrow Carry bit Yes 0 No 1 Operation Emulation Description Status Bits Mode Bits Example DSUB Instruction Set Overview Set carry bit SETC 1C BIS 1 5 The carry bit C is set N Not affected Z Not affected C Set V Not affected OscOff CPUOff and GIE are not affected Emulation of the decimal subtraction Subtract R5 from R6 decimally Assume that R5 3987 and R6 4137 ADD 6666h R5 Move content R5 from 0 9 to 6 0Fh R5 03987 6666 09FEDh INV R5 Invert this result back to 0 9 R5 R5 06012h SETC Prepare carry 1 DADD R5 R6 Emulate subtraction by addition of 10000 R5 1 R5 1 4137 06012 1 1 0150 0150 Instruction Set Description B 53 Instruction Set Overview SETN Syntax Operation Emulation Description Status Bits Mode Bits Set negative bit SETN 1 gt BIS 4 SR The negative bit N is set N Set Z Not affected C Not affected V Not affected OscOff CPUOff and GIE are not affected Instruction Set Overview SETZ Set zero bit Syntax SETZ Operation 1 Z Emulation BIS 2 SR Description The zero bit Z is set Status Bits N Not affected Z Set C Not affected V Not affected Mode Bits OscOff CPUOff
247. capture then start the timer LLLLLSS A A A A X A AXA A A OX Timer A 11 15 Timer Modes 11 4 1 1 Capture Compare Block Capture Mode Capture Initiated by Software In addition to internal and external signals captures can be initiated by software This is useful for various purposes such as To measure time used by software routines To measure time between hardware events To measure the system frequency Two bits CCISx1 and CCISx0 and the capture mode selected by bits CCMx1 and are used by the software to initiate the capture The simplest realization is when the capture mode is selected to capture on both edges of CCIx and bit CCISx1 is set Software then toggles bit CCISxO to switch the capture signal between Vcc and GND initiating a capture each time the input is toggled as shown in Figure 11 21 Figure 11 21 Software Capture Example CCISX1 CCISx0 CCIx Capture CCISx1 CCISx0 0 CClxA 9 9 73 I o Capture Capture GND 3 CIx CCMx1 Both Edges Selected 1 1 The following is a software example of a capture performed by software The data of capture compare register CCRx are taken by the software It is assumed that CCMx1
248. ccurs If the selected time interval expires a system reset is generated If the watchdog function is not needed in an application the module can work as an interval timer to generate an interrupt after the selected time interval The WDT diagram is shown in Figure 9 1 Figure 9 1 Schematic of Watchdog Timer See Interrupt WDTCNT WDTCTL MSB Definition Bourne Password Cmp Pulse Generator 16 PUC Write Enable Low Byte RW SMCLK ACLK 4 LSB Watchdog Timer Control Register Features of the Watchdog Timer include d d 9 2 Eight software selectable time intervals Two operating modes as watchdog or interval timer Expiration of the time interval in watchdog mode which generates a sys tem reset or in timer mode which generates an interrupt request Safeguards which ensure that writing to the WDT control register is only possible using a password Support of ultralow power using the hold mode The Watchdog Timer 9 1 1 Watchdog Timer Register The Watchdog Timer counter WDTONT is a 16 bit up counter that is not directly accessible by software The WDTONT is controlled through the Watchdog Timer control register WDTCTL shown in Figure 9 2 which is a 16 bit read write register located at the low byte of word address 0120h Any read or write access must be done using word instructions with no suffix or w suffix In both opera
249. ce UART Mode 13 2 USART Peripheral Interface UART Mode The USART peripheral interface is a serial channel that shifts a serial bit stream of 7 or 8 bits in and out of the MSP430 The UART mode is chosen when control bit SYNC in the USART control register UOCTL for USARTO or U1CTL for USART1 is reset 13 2 1 UART Serial Asynchronous Communication Features Some of the UART features include Asynchronous formats that include idle line address bit communication protocols Two shift registers that shift a serial data stream into URXD and out of UTXD Data that is transmitted received with the LSB first Programmable transmit and receive bit rates Status flags Figure 13 2 shows the USART in UART mode Figure 13 2 Block Diagram of USART UART Mode 58653 UORXBUF or U1TRXBUF RXE sm qaae 9 URXD Receive Shift Register Receive Status SSEL1 SSELO 0 Baud Rate Generator UCLKS UCLKI m ary ACLK e 2 Baud Rate Register SMCLK o 3 UOBR or U1BR SMCLK o Baud Rate Generator MR LSB First Transmit Shift Register gt e gt UTXD Transmit Buffer TXWake UOTXBUF or U1TXBUF CKPL UCLKI UCLKS Clock Polarity UCLK USART Peripheral Interface UART Mode 13 3 Asynchronous Operation 13 3 Asynchronous Operation In the asynchronous mode the receiver synchronizes itself to frames but the external transmitting and receiving device
250. cessing Figure 3 8 Interrupt Processing Before Interrupt Item1 SP Item2 TOS After Interrupt Item1 Item2 PC SP SR The interrupt handling routine terminates with the instruction which performs the following actions RETI return from an interrupt service routine TOS 1 The status register with all previous settings pops from the stack All pre vious settings of GIE CPUOFF etc are now in effect regardless of the settings utilized during the interrupt service routine 2 The program counter pops from the stack and begins execution at the point where it was interrupted The return from the interrupt is illustrated in Figure 3 9 Figure 3 9 Return From Interrupt Before After Return From Interrupt Item1 Item1 Item2 SP Item2 TOS PC PC SP SR TOS SR A RETI instruction takes five cycles Interrupt nesting is activated if the GIE bit is set inside the interrupt handling routine The GIE bit is located in status register SR R2 which is included in the CPU as shown in Figure 3 10 Figure 3 10 Status Register SR 15 8 7 0 OSC CPU Reserved For Future Enhancements V SCG1 SCGO rw 0 Apart from the GIE bit other sources of interrupt requests can be enabled disabled individually or in groups The interrupt enable flags are located 3 12 Interrupt P
251. cillator Fault Detection 7 10 T5 EbEEOperatingi Modes 082663977000 7 10 T6 m Buffered 7 12 7 7 FLL Module Control Registers 7 13 7 1 7 1 The FLL Clock Module 7 2 The frequency locked loop FLL clock module shown in Figure 7 1 follows the major design targets of low system cost and low power consumption The FLL operates completely using a 32768 Hz watch crystal A second asynchronous high speed clock signal is generated on chip using a digitally controlled oscillator DCO The DCO frequency is stabilized to a multiple of the watch crystal frequency by dividing the DCO frequency and digitally locking the two frequencies This technique is known as frequency locked loop The FLL module supplies the MSP430x4xx family of devices with two 41x or three 43x 44x clock signals and an associated software selectable buffered clock output ACLK crystal oscillator signal used by peripheral modules This signal is identicalto the frequency ofthe crystal oscillator input XIN ACLK is also known as fcrystal Li MCLK the controller s main system clock used by the CPU MCLK is also known as fsystem SMCLK is used for peripheral modules SMCLK is identical to MCLK or XT2 clock 43x 44x ACLK n buffered output of ACLK ACLK 2 ACLK 4 or ACLK 8 It is only for external use on a device pin 20 714
252. ck during the CCRO update affects how the timer reacts to the new period If the new smaller period is written to CCRO during a high phase of the timer clock then the timer rolls to zero or begins counting down when in the up down mode on the next rising edge of the timer clock However if the new smaller period is written during a low phase of the timer clock then the timer continues to increment with the old period for one more clock cycle before adopting the new period and rolling to zero or beginning counting down This is shown in Figure 11 8 Timer Modes Figure 11 7 New Period Old Period Timer CCROold 2 Register CCROnew 3 ERR SOOO Figure 11 8 New Period lt Old Period Timer Register Timer CCROold 5 Register CCROnew 2 CCROold 5 CCROnew 2 5 5 4 4 3 3 2 2 1 1 0 0 5 0 1 2 3 01 2 1 01112314 510 1123 410 1 201 2 0r CCRO 5 X 2 CCRO 5 X 2 GCRO Loaded With 2 During High ClockPhase _ CCRO Loaded With 2 During Low Clock Phase Timer Clock A Timer Clock Y y L Timer Timer X_n X X Oornt X T 1 CCRO CCRoldX CCRnew CCRO CCRold X CCRnew Load New CCRO Lo
253. ck write operation a segment erase or a mass erase Once the timing generator has completed its function the BUSY bit is reset by hardware The program and erase timing are shown in Figures C 7 C 8 and C 9 0 Flash memory is not busy Read write erase and mass erase are possible without any violation of the internal flash timing The BUSY bit is reset by POR and by the flash timing generator 1 Flash memory is busy Remains in busy state if block write function is in wait mode The conditions for access to the flash memory during BUSY 1 are described in paragraph C 2 6 KEYV 012Ch bit1 Key Violated 0 Key 0 5 high byte was not violated 1 Key 0A5h high byte was violated Violation occurs when a write access to register FCTL1 FCTL2 or FCTL3 is executed and the high byte is not equal to OA5h If the security key is violated bit KEYV is set and a PUC is performed The KEYV bit can be used to determine the source that forced a start of the program at the reset vector s address The KEYV bitis not automatically reset and should reset by software Note Any key violation results independent ofthe state ofthe KEYV bit To avoid endless software loops the flash memory control registers should not be written during a key violation service routine Note The software can set the KEYV bit A PUC is also performed if itis set by software ACCVIFG WAIT Lock bit2 012Ch bit3 012Ch bit4
254. code Registers R2 and R3 used in the constant mode cannot be addressed explicitly they act like source only registers 16 Bit CPU 5 5 Addressing Modes The RISC instruction set ofthe MSP430 has only 27 instructions However the constant generator allows the MSP430 assembler to support 24 additional emulated instructions For example the single operand instruction CLR dst is emulated by the double operand instruction with the same length MOV R3 dst or the equivalent MOV 0 dst where 0 is replaced by the assembler and is used with As 00 which results in LJ One word instruction No additional control operation or hardware within the CPU Register addressing mode for source no extra fetch cycle for constants 0 5 2 Addressing Modes All seven addressing modes for the source operand and all four addressing modes for the destination operand can address the complete address space The bit numbers in Table 5 4 describe the contents of the As and Ad mode bits See Section 5 3 for a description of the source address As and the destination address Ad bits Table 5 4 Source Destination Operand Addressing Modes As Ad 5 6 00 0 01 1 01 1 01 1 10 11 11 Addressing Mode Syntax Description Register mode Indexed mode Symbolic mode Absolute mode Rn Register contents are operand X Rn Rn X points to the operand X is stored in the next word ADDR PC X p
255. conversion memory ADC12 conversion memory Multiplier Watchdog Timer flash control Reserved Reserved Byte modules are peripherals that are connected to the reduced eight LSB MDB Access to byte modules is always by byte instructions The hardware in the peripheral byte modules takes the low byte the LSBs during a write operation 4 8 RAM and Peripheral Organization Byte instructions operate on byte modules without any restrictions Read access to peripheral byte modules using word instructions results in unpredictable data in the high byte Word data is written into a byte module by writing the low byte to the appropriate peripheral register and ignoring the high byte The peripheral file address space is organized into sixteen frames as described in Table 4 2 Address OOFOh OOFFh OOEFh 00D0h OODFh 00 00 00 OOBFh 00 OOAFh 0090h 009Fh 0080h 008Fh 0070h 007Fh 0060h 006Fh 0050h 005Fh 0040h 004Fh 0030h 003Fh 0020h 002Fh 0010h 001Fh 0000h 000Fh Table 4 2 Peripheral File Address Map Byte Modules Description Reserved Reserved Reserved Reserved Reserved LCD LCD ADC12 memory control USARTO Reserved System clock generator Comparator A brownout SVS Basic timer 8 Bit Timer Counter Timer Port Digital port P5 and P6 control Digital port P1 and P2 control Digital port and P4
256. cording to the number of odd or even 1 bits in both the transmitted and received characters the address bit address bit multiprocessor mode and the parity bit PEV 0 odd parity PEV 1 even parity Parity enable If parity is disabled no parity bit is generated during transmission or expected during reception A received parity bit is not transferred to the UxRXBUF with the received data as it is not considered one of the data bits In address bit multi processor mode the address bit is included in the parity calculation 0 Parity disable 1 Parity enable OOOO Note Mark and Space Definitions The mark condition is identical to the signal level in the idle state Space is the opposite signal level the start bit is always space USART Peripheral Interface UART Mode 13 17 Control and Status Registers 13 5 2 Transmit Control Register UOTCTL U1TCTL The transmit control register shown in Figure 13 17 controls the USART hardware associated with the transmit operation Figure 13 17 Transmitter Control abd UOTCTL U1TCTL UOTCTL 071h U1TCTL 078h Bit 0 Bit 1 Bit 2 Bit 3 Bits 4 5 Bit 6 Bit 7 18 18 CKPL SSEL1 SSELO URXSE X rw 0 rw 0 rw 0 rw 0 rw 0 rw O rw O0 rw 1 The transmitter empty TXEPT flag is set when the transmitter shift register and UxTXBUF are empty and is reset when data is written to UXTXBUF It is set by a
257. ction cycles for Format ll single operand instructions Table 5 15 Execution Cycles for Single Operand Instructions Instruction Addressing Mode CALL Rn 4 Rn 4 Rn N 5 x Rn Symbolic Absolute amp 5 Example the instruction PUSH 500h needs 4 cycles for the execution 5 2 8 3 Format lll Jump Instructions Format lll instructions are described as follows Jxx all instructions need the same number of cycles independent of whether a jump is taken or not Clock cycle Two cycles Length of instruction word 16 Bit CPU 5 15 Instruction Set Overview 5 2 8 4 Miscellaneous Format Instructions Table 5 14 describes miscellaneous format instructions Table 5 16 Miscellaneous Instructions or Operations Activity Clock Cycle RETI 5 cycles 1 wordt Interrupt 6 cycles WDT reset 4 cycles Reset RST NMI 4 cycles t Length of instruction 5 3 Instruction Set Overview This section gives a short overview of the instruction set The addressing modes are described in Section 5 2 Instructions are either single or dual operand or jump The source and destination parts of an instruction are defined by the following fields src The source operand defined by As and S reg dst The destination operand defined by Ad and D reg As The addressing bits responsible for the addressing mode used for the source src S reg The working register used for the source src Ad The addressing b
258. ctions MOV B 1 amp TCCTL The addressing of both is through the absolute addressing mode or the 16 bit working registers using the indexed indirect or indirect autoincrement addressing mode See Figure 4 7 for the RAM peripheral organization Memory 4 7 RAM and Peripheral Organization Figure 4 7 Example of RAM Peripheral Organization Address Function Access Hex 7 0 01FFh Timer Word 16 Bit Peripheral Modules 0100h LCD 8 Peripheral Modules 8b TIC Byte OFh Oh Special Function Registers SFR Byte 4 4 2 1 Word Modules Word modules are peripherals that are connected to the 16 bit MDB Word modules can be accessed with word or byte instructions If byte instructions are used only even addresses are permissible and the high byte of the result is always 0 The peripheral file address space is organized into sixteen frames with each frame representing eight words as described in Table 4 1 Table 4 1 Peripheral File Address Map Word Modules Address 1FFh 1E0h 1EFh 1DOh 1DFH 1 1CFH 1BOh 1BFH 1A0h 1AFH 190h 19FH 180h 18FH 170h 17FH 160h 16FH 150h 15FH 140h 14FH 130h 13FH 120h 12FH 110h 11FH 100h 10FH 4 4 2 2 Byte Modules Description Reserved Reserved Reserved Reserved Reserved ADC12 control and interrupt Reserved Reserved Timer A Timer A ADC12
259. d USART Integrated LCD driver Watchdog Timer Multiple with extensive interrupt capability Integrated programmable oscillator 32 kHz crystal oscillator all devices 450 kHz 8 MHz crystal oscillator all devices Powerful easy to use development tools including Simulator including peripheral and interrupt simulation C compiler Assembler Linker Flash emulator kit Device programmer Application notes Example code Lj Versatile ultralow power device options including Flash in system programmable 40 to 85 C operating temperature range Up to 64K addressing space Memory mixes to support all types of applications 41x Devices 1 2 41x Devices The 41x devices contain the following peripherals clock system on chip DCO crystal oscillator Watchdog Timer general purpose timer Comparator_A precision analog comparator ideal for slope A D conversion Brownout SVS Basic Timer1 two 8 bit timers or one 16 bit timer LCD controller driver up to 96 segments Timer_A3 16 bit timer with three capture compare registers and PWM output I O port 1 2 8 I Os each all with interrupt ports 3 4 5 6 eight I Os each OO OULU The 41x device family includes MSP430F412 4 KB flash memory 256B RAM MSP430C412f 4 ROM 256B RAM MSP430F413 8 KB flash memory 256B RAM MSP430C413f 8 ROM 256B RAM 1 3 43x Devicest The 43x devices contain the following p
260. d by the general interrupt enable GIE bit in the status register Whenever an interrupt is requested and the appropriate interrupt enable bit and general interrupt enable GIE bit are set the interrupt service routine becomes active as follows 1 CPU active The currently executing instruction is completed 2 CPU stopped The low power modes are terminated 3 The program counter pointing to the next instruction is pushed onto the stack 4 The status register is pushed onto the stack 5 The interrupt with the highest priority is selected if multiple interrupts occurred during the last instruction and are pending for service 6 The appropriate interrupt request flag resets automatically on single source flags Multiple source flags remain set for servicing by software 7 The GIE bit is reset the CPUOff bit the OscOff bit and the SCG1 bit are cleared the status bits V N Z and C are reset SCGO is left unchanged and loop control remains in the previous operating condition 8 The content of the appropriate interrupt vector is loaded into the program counter the program continues with the interrupt handling routine at that address The interrupt latency is six cycles starting with the acceptance of an interrupt request and lasting until the start of execution of the appropriate interrupt service routine first instruction as shown in Figure 3 8 System Resets Interrupts and Operating Modes 3 11 Interrupt Pro
261. d independently Any combination of input is possible L Any combination of port or module function is possible The four registers for each port are shown in Table 8 3 They each contain eight bits and should be accessed with byte instructions Digital I O Configuration 8 9 Ports P4 P5 P6 Table 8 3 Port P3 P6 Registers Register Short Form Address Register Type Initial State Input 018h Read ony P4IN 01Ch Read ony 030h Read ony P6IN 034h Read ony Output P3OUT 019h Read write Unchanged PAOUT 01Dh Read write Unchanged P5OUT 031h Read write Unchanged P6OUT 035h Read write Unchanged Direction P3DIR 01Ah Read write Reset P4DIR 01Eh Read write Reset P5DIR 032h Read write Reset P6DIR 036h Read write Reset Port Select P3SEL 01Bh Read write Reset P4SEL 01Fh Read write Reset P5SEL 033h Read write Reset P6SEL 037h Read write Reset 8 3 1 1 Input Registers The input registers are read only registers that reflect the signal at the I O pins Note Writing to Read Only Register Any attempt to write to these read only registers results in an increased current consumption while the write attempt is active 8 3 1 2 Output Registers The output registers show the information of the output buffers The output buffers can be modified by all instructions that write to a destination If read the contents of the output buffer are independent of the pin direction A
262. d to compare mode and the receive bits are latched automatically with the EQUx signal The interrupt routine collects the bits for later software processing Figure 11 33 illustrates the UART implementation Figure 11 33 UART Implementation CCISx1 1 0 Timer A UART Timer Bus 0 CCIxA zo S o E Mode o 3 Capture cc 9 0 1 0 0 Disabled 0 1 Positive Edge 1 O Negative Edge 1 1 Both Edges 7 Set_CCIFGx Receive Data Path EN LL c 7 Y SCCIx e ee ee J 1 Se a 1 OUTx Signal Timer Clock Transmit Data Path 2 1 0 0 1 Set EQUx set OUTx signal clock synchronized with timer clock 1 0 1 Reset EQUx resets signal clock synchronized with timer clock wh a SS Se Timer 11 33 Timer UART One capture compare block is used when half duplex communication mode is desired Two capture compare blocks are used for full duplex mode Figure 11 34 illustrates the capture compare timing for the UART Figure 11 34 Timer A UART Timing Capture Compare EEUU Receive Capture Compare Compare UTXD Signal T
263. data Figures 14 4 and 14 5 show an example of a serial synchronous data transfer for a character length of seven bits The initial content of the receive shift register is 00 The following events occur in order A Slave writes 98h to the data shift register DSR and waits for the master to shift data out B Master writes BOh to UxTXBUF which is immediately transferred to the transmit shift register and starts the transmission C First character is finished and sets the interrupt flags D Slave reads 58h from the receive buffer right justified E Slave writes 54h to the DSR and waits for the master to shift out data F Master reads 4Ch from the receive buffer UXRXBUF right justified G Master writes E8h to the transmit buffer UxTXBUF and starts the transmission Note If USART is in slave mode no UCLK is needed after D until G However in master mode two clocks are used internally not on UCLK signal to end transmit receive of first character and prepare the transmit receive of the next character USART Peripheral Interface SPI Mode 14 5 Synchronous Operation H Second character is finished and sets the interrupt flag I Master receives 2Ah and slave receives 74h right justified Figure 14 4 Serial Synchronous Data Transfer CKPL 0 CDEF G HI dici mapa E mE HHHH SIMO From ico ordeo prete esee sempe Ie T SOMI From Slave ERO UIN STE P Master Interrup
264. de makes the first bit of data available after the transmit shift register is loaded and before the first edge of the UCLK In this mode data is latched on the first edge of UCLK and transmitted on the second edge 14 5 3 Receive Control Register UURCTL U1RCTL The receive control register shown in Figure 14 18 controls the USART hardware associated with the receiver operation and holds error conditions Figure 14 18 Receive Control Register UORCTL U1RCTL 14 18 7 0 De oa U1RCTL 07Ah rw O0 rw 0 rw 0 rw 0 rw 0 rw 0 0 rw 0 Bit 0 Undefined driven by USART hardware Bit 1 Undefined driven by USART hardware Bit 2 Unused Bit 3 Unused Bit 4 Undefined driven by USART hardware Bit 5 The overrun error flag bit OE is set when a character is transferred to UXRXBUF before the previous character is read The previous character is overwritten and lost OE is reset by a SWRST a system reset by reading the UxRXBUF or by an instruction Bit 6 Undefined driven by USART hardware Bit 7 Frame error The FE bit is set when four pin mode is selected and a bus conflict stops an active master by applying a negative transition signal to pin STE FE is reset by a SWRST a system reset by reading the UxRXBUF or by an instruction Control and Status Registers 14 5 4 Baud Rate Select and Modulation Control Registers The baud rate generator uses the content of baud rate select registers UXBR1 and
265. ded number can be added to the program counter to automatically enter the software routine for handling each specific interrupt see software example section 17 8 5 1 An interrupt request is immediately generated if an interrupt flag is pending ADC121Vz0 if the corresponding interrupt enable bit ADC12OVIE ADC12TOVIE or ADC12IE x is set and if the general interrupt enable bit GIE is set When an interrupt request is generated the service is requested by the highest priority interrupt that is enabled ADC12 17 37 ADC12 Control Registers Table 17 3 ADC12IV Interrupt Vector Values is important to note that ADC12OVIFG and ADC12TOVIFG are reset automatically when either is the highest pending interrupt and the ADC12IV register is accessed For example if both are pending simultaneously ADC120OVIFG will be reset automatically with the first access of ADC12IV and ADC12TOVIFG will be reset automatically with the next access to the ADC12lV assuming ADC12OVIFG was not set again However flags ADC12IFG x must be reset by software or reset by accessing the corresponding conversion memory register ADC12MEMx Also note that the flags ADC12OVIFG and ADC12TOVIFG can not be accessed by software They are visible only via the interrupt vector word ADC12IV data ADC Interrupt Flags ADC12IFG ADC12TOV ADC120V ADC12IV 15 14 13 12 11
266. dge of the clock signal The timer can be read or written to with software Additionally the timer can generate an interrupt with its ripple carry output when it overflows 11 2 1 Timer Mode Control The timer has four modes of operation as shown in Figure 11 2 and described in Table 11 1 stop up continuous and up down The operating mode is soft ware selectable with the and 1 bits in the TACTL register Figure 11 2 Mode Control Data 16 Bit Timer CLK Timer Clock EquO pesi Control gt Carry Zero Men Set TAIFG POR Table 11 1 Timer Modes 0 0 Stop Mode 0 1 Up Mode 1 0 Continuous Mode 1 1 Up Down Mode Mode Control MC1 MCO Description 0 0 Stop The timer is halted 0 1 Up The timer counts upward until value is equal to value of compare register CCRO 1 0 Continuous The timer counts upward continuously 1 1 Up Down The timer counts up until the timer value is equal to compare register 0 and then it counts down to zero Timer A 11 3 Timer Operation 11 2 2 Clock Source Select and Divider The timer clock can be sourced from internal clocks ACLK SMCLK or from two external source TACLK INCLK as shown in Figure 11 3 The clock source is selectable with the SSELO and SSEL 1 bits in the TACTL register It is important to note that when changing the clock source for the timer errant timings can occur For this reason it is recommended to stop t
267. different sampling times for a sequence of conversions by using both upper and lower conversion memory registers in the sequence This feature is useful when different external source impedance conditions exist and require different sample timings Sampling In pulse sampling mode sampling time is a multiple ofthe ADC12CLK x4 and is calculated by tsample 4 x tapc42cLk X SHTx SHTx is determined by bits SHTO or SHT1 see table in Control Registers ADC12CTLO and ADC12CTL 1 section The sampling signal SAMPCON remains in the sampling state high for the synchronization time and the selected sample time tsample as Shown in Figure 17 17 The conversion takes 13 x ADC12CLK cycles tconyer It is im portant to note that after a sample and conversion cycle has been triggered by the sample input signal additional triggers via a rising edge on the sample input signal will be missed ignored until the prior sample and conversion cycle is completed Figure 17 17 Conversion Timing Pulse Sample Mode SAMPCON aeae ar SC Ap Seed N tsample tconvert t sync An example of the pulse sample mode configuration is shown in Figure 17 18 The selected input signal source is Timer B OUTO The timing for the example is shown in Figure 17 19 Figure 17 18 Pulse Sample Mode Example Configuration Internal
268. ditions under which the capture function is performed Both the interrupt enable bit CCIEx and the interrupt flag CCIFGx are used for capture and compare modes CCIEx enables the corresponding interrupt CCIFGx is set on a capture or compare event Thecapture inputs CCIxA and CCIxB are connected to external pins or internal signals Different MSP430 devices may have different signals connected to CCIxA and CCIxB The data sheet should always be consulted to determine the Timer B connections for a particular device Figure 12 17 Capture Compare Blocks CCISx1 1 0 0 0 74 CCIXB o GND o Vcc o 0 0 3 CCMx1 CCMxO 0 0 0 1 1 0 1 1 Overflow x CAPx Capture Mode Capture Compare Register TBCCRx Reset CCMx1 Disabled CLLDO m Reset Positive Edge CLLD1 Compare Latch TBCLx Negative Edge Both Edges 1 High Comparator x Zero Up Down ve EQUX 0 1 Set CCIFGx Timer B 12 15 Timer Modes 12 4 1 Capture Compare Block Capture Mode The capture mode is selected if the mode bit CAPx located in control word TBCCTLx is set The capture mode is used to fix time events It can be used for speed computations or time measurements The timer value is copied into the capture register TBCCRx with the selected edge positive negative or both of the input signal Captures may also be initiated by softwa
269. dst Add carry to destination ye qu ADDC 0 dst ADC B dst Add carry to destination ADDC B 0 dst DADC W dst Add carry decimal to destination DADD 0 dst DADC B dst Add carry decimal to destination DADD B 0 dst DEC W dst Decrement destination e SUB 1 dst DEC B dst Decrement destination po Fy bee SUB B 1 dst DECD W dst Double decrement destination Eo SUB 2 dst DECD B dst Double decrement destination dE UR SUB B 2 dst INC W dst Increment destination E MENS ADD 1 dst INC B dst Increment destination ADD B 1 dst INCD W dst Increment destination R R ADD 2 dst INCD B dst Increment destination mee se XR ADD B 2 dst SBC W dst Subtract carry from destination tage SUBC 0 dst SBC B dst Subtract carry from destination dE NE SUBC B 0 dst Logical instructions INV W dst Invert destination e ey em XOR 0OFFFFh dst INV B dst Invert destination a ve ty XOR B 0FFFFh dst RLA W dst Rotate left arithmetically xU ZUM ADD dst dst RLA B dst Rotate left arithmetically ADD B dst dst RLC W dst Rotate left through carry qe Te NS ADDC dst dst RLC B dst Rotate left through carry S ADDC B dst dst Data instructions common use CLR W Clear destination MOV 0 dst CLR B Clear destination MOV B 0 dst CLRC Clear carry bit 0 BIC 1 SR CLRN Clear negative bit 0 BIC 4 SR CLRZ Clear zero bit 0 BIC 2 SR POP dst Item from stack MOV SP dst SETC Set carry bit
270. e when TBR counts to TBCLO or counts to 0 When TBR counts to TBCLx saws 12 01 The groupings and load conditions are summarized below Table 12 2 Table 12 2 Compare Latch Operating Modes CLLDX From Load Conditionst load TBCCRx data to compare latch TBCLx Lowest Counter Group see MCx Note 1 03 immediate immediate immediate immediate immediate TBR counts 0 TBR counts toO counts 0 TBR counts toO TBR counts toO counts toO TBR counts to 0 TBR counts 0 TBR counts toO counts toO TBR counts toO TBR counts toO counts toO TBR counts to 0 2 3 TBR counts 0 TBR counts toO counts 0 TBR counts toO TBR counts toO counts toO TBR counts to 0 orto TBCLO orto TBCLO orto TBCLO orto TBCLO orto TBCLO orto TBCLO orto TBCLO 3 1 3 TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to x TBCLO TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 TBCL1 TBCL2 loaded immediately TBCL3 TBCL4 loaded immediately TBCL5 TBCL6 loaded immediately Immediate when the corresponding TBCCRx when the corresponding TBCCRx when the corresponding TBCCRx register is loaded register is loaded register is loaded TBCL1 TBCL2 updated TBCL3 TBCL4 updated TBCL5 TBCL6 updated TBR counts to 0 simultaneously when TBR counts simultaneously when TBR counts simultaneously when TBR counts to 0 to
271. e compare latch for the comparison The timing of the transfer of the compare Introduction data from each TBCCRx register to the corresponding compare latch TBCLx is user selectable to be either immediate or on a timer event See section 12 4 2 1 for a complete discussion on using and configuring the compare latches The addition of the compare latch gives the user more control over when exactly a compare period updates In addition multiple compare latches may be grouped together allowing the compare period of multiple compare registers to be updated simultaneously This is useful for example when there is a need to change the period or duty cycle of multiple PWM signals simultaneously It is useful to note that in Timer B s default condition the compare data is immediately transferred from each TBCCRx register to the corresponding compare latch Therefore in the default condition the compare mode of Timer B functions identically to the compare mode of Timer A Timer B 12 3 Introduction Figure 12 1 Timer B Block Diagram 16 Bit Timer TBSSEL1 TBSSELO Timer Clock Data a 15 0 1 mum Input 16 Bit Timer Mode ivi CLK1 RC E QUE H 690 101 IDO INCLK oJ Carry Zero POR TBCLRI X y MC1 Mco Set TBIFG ae ea Rc T oL E 4 Eq EUER EQ CH 2
272. e information stored in the special function registers SFRs The different bits in the SFRs enable interrupts provide information about the status of interrupt flags and define the operating modes of the peripherals Total current consumption can be reduced by disabling peripherals that are not needed during an operation The individual peripherals are described later in this manual Architectural Overview 2 3 Peripherals 2 6 Peripherals Peripheral modules are connected to the CPU through the MAB the MDB and the interrupt service and request lines The MAB is usually a 5 bit bus for most of the peripherals The MDB is an 8 bit or 16 bit bus Most of the peripherals operate in byte format Modules with an 8 bit data bus are connected by bus conversion circuitry to the 16 bit CPU The data exchange with these modules must be handled with byte instructions The SFRs are also handled with byte instructions The operation for 8 bit peripherals follows the order described in Figure 2 2 Figure 2 2 Bus Connection of Modules Peripherals Interrupt Request Interrupt Bus Grant MAB MDB Interrupt Request Module Peripheral Interrupt Bus Grant PUC 2 7 Oscillator and Clock Generator 2 4 The LFXT1 oscillator is designed for the commonly used 32 768 Hz low current consumption clock crystal or to be used with a high speed crystal All analog components for the 32 768 Hz oscillator are integrated into the MSP430 only t
273. e ER ER LE ERE ornate 8 11 Schematic of Watchdog Timer enia Dra 9 2 Watchdog Timer Control Register 9 3 Reading WDTCTL mens 9 4 Writing to WDTGTE Siis at nitens he ates 9 4 Basic Timer1 Configuration 10 2 Basic 1 Control Register eee eee 10 3 Basic Timer1 Control Register Function 10 4 Basic Timer1 Counter BTCNT1 10 4 Basic Timer1 Counter BTCNT2 een 10 5 Timer A Block Diagram ne teens 11 2 Mode Controlere RU 11 3 schematic of T6 Bit TIME ces yes Psi peewee nek E EE A EEE 11 4 Schematic of Clock Source Select and Input Divider 11 4 Timer Up Modes eee eared EBD 11 6 Up Mode Flag Setting n 11 6 New Period gt Old Period n 11 7 New Period lt Old Period n 11 7 Timer Continuous e eens 11 8 Continuous Mode Flag Setting 11 8 Output Unit in Continuous Mode for Time Intervals 11 9 Timer Up Down Mode seeseeeeseeee e n
274. e M m panty fete fete S5 gt 6 2h 2 2b 09Ah Digit 7 IRIS 77 S7 8 3g 3a cosh e c 16 Digite 58 gt 9 3h 3c 3b y f b 14 enc E P cms 12 20 E E Cae ye ae One o 99 11 4 12 4h 4c 4b 095h 7 EE i Digit 4 12 4 13 5e bt 5y 8 Digit 3 513 4 14 5d 5g 5 o94h j Ey 6 __ S14 4 5 sh Se sb os e 9 9 4 Sis s5 om Y 2 poe S16 gt 17 6d 6g Digit 1 Spe Paci eee pleat see osth o 518 4 gt 19 7e 2 Y um 19 20 7d 79 7a Parallel 20 4 21 7h 7 70 Serial 21 4 22 8e 8 By Conversion S22 gt 23 8g 8a S23 4 24 8h 8c 8b 524 4 25 9 9f 9y Sn 1 Sn S25 4 26 9d 9g 9a S26 4 27 9h 9c 9b 27 4 28 10e 10f 10 28 4 29 10d 109 10 29 4 30 10h 10c 10 COMO 31 COMI 4 32 4 33 COM2 COM3 NC Liquid Crystal Display Drive 16 17 LCD Controller Driver 16 2 6 4 Example Using Four MUX 1 3 Bias Drive Mode The four MUX drive mode uses all four common lines In this mode bits 0 through 7 are used for segment information Figure 16 17 shows an example four MUX LCD pin out LCD to 430 connections and the resulting data mapping Note this is only an example Segment mapping in a user s application completely depends on the LCD pin
275. e and initial carry is set otherwise reset OscOff CPUOff and GIE are not affected R5 is shifted right one position The MSB is loaded with 1 SETC Prepare carry for MSB RRC R5 R5 2 8000h R5 R5 is shifted right one position The MSB is loaded with 1 SETC Prepare carry for MSB RRC B R5 R5 2 80h R5 low byte of R5 is used Instruction Set Description B 51 Instruction Set Overview SBC W SBC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Subtract borrow from destination Subtract borrow from destination SBC dst or SBC W dst SBC B dst dst OFFFFh C dst dst OFFh C dst SUBC 0 dst SUBC B 0 dst The carry bit C is added to the destination operand minus one The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Reset if dst was decremented from 0000 to OFFFFh set otherwise Reset if dst was decremented from 00 to OFFh set otherwise V Set if initially 0 and dst 08000h Set if initially C 0 and dst 0801 OscOff CPUOff and GIE are not affected The 16 bit counter pointed to by R13 is subtracted from a 32 bit counter pointed to by R12 SUB R13 0 R12 Subtract LSDs SBC 2 R12 Subtract carry from MSD The 8 bit counter pointed to by R13 is subtracted from a 16 bit counter pointed to by R12 SUB B R13 0 R12 Su
276. e completed and the end of conversion feedback to the program is not possible O A A The ADC12 sample and hold S H circuitry shown in Figure 17 14 is flex ible and configurable The configuration is done by software via control bits in the ADC12CTLO and ADC12CTL1 registers Configuration and operation of the S H circuitry is discussed in this section Figure 17 14 The Sample and Hold Function analog input gt signal Sample and Hold SiH 12 bit A D converter core Internal ADC12SSEL Oscillator ADC120N ADC12DIV ADC120SC ADC12CLK Divide by ACLK 1 2 3 4 5 6 7 8 MCLK SMCLK Sampling ADC12SC q SAMPCON Timer A OUT1 O e Timer B OUTO SHI asc Timer B OUT1 12 bit SAR Conversion CTL v 17 7 1 Sampling Operation 17 22 The sample and hold circuitry samples the analog signal when the sampling signal SAMPCON see Figure 17 14 is high Conversion starts immediately with the falling edge of SAMPCON The sample and hold holds the signal value when SAMPCON is low Conversion takes 13 ADC12CLK cycles see Figure 17 15 Sampling Figure 17 15 Sample and Conversion Basic Signal Timing SAMPCON Start Stop Sam
277. e divided to meet the frequency requirements for fy as specified in the device s data sheet Writing to control register FCTL2 should not be attempted if the BUSY bit is set otherwise an access violation will occur ACCVIFG 1 Read access to FCTL2 is possible at any time without restrictions FCTL2 012Ah FCTL2 read 096h W 0 rw 1 rw 0 rw 0 rw 0 rw 0 rw i rw O0 FCTL2 write OASh gt The control bits are FNO 012Ah bitO These six bits define the division rate of the clock signal The division to rate can be 1 to 64 depending on the digital value of FN5 to FNO FN5 012Ah bit5 Plus one SSELO 012 bitO Determine the clock source SSEL1 0124Ah bit6 bit7 0 ACLK 1 MCLK 2 3 SMCLK Flash Memory C 15 Flash Memory Control Registers C 3 3 Flash Memory Control Register FCTL3 There are no restrictions on modifying this control register The control bits are reset or set WAIT by a PUC but key violation bit KEYV is reset by POR FCTL3 012Ch FCTL3 read lt 096h ro rw 0 rw 1 r 1 rw O rw 0 r w O FCTL3 write 0A5h gt BUSY 0128h bitO The bit BUSY shows if an access to the flash memory is possible BUSY 0 or if an access violation can occur The BUSY bit is read only but a write operation is allowed The BUSY bit should be tested before each write and erase cycle The flash timing generator hardware immediately sets the BUSY bit after the start of a write operation a blo
278. e drop Generally if the width of the voltage drop is small a deeper voltage drop is required to trigger a POR signal See the device data sheet for electrical parameters 3 1 1 2 Supply Voltage Supervisor 3 4 The supply voltage supervisor circuit resets the device by triggering a POR signal when Vcc drops below the appropriate level The operating levels for the SVS and the brownout reset circuit are shown in Figure 3 4 The SVS is initially disabled by the brownout function and is enabled by software by bits in the SVSCTL register Any brownout situation deactivates the SVS function When the supply voltage is below V sys start the SVS may or may nottrigger a POR Proper SVS operation is ensured when the supply voltage is above the V svs start level When the supply voltage is between V sys star and V SvS IT the POR signal is reliably triggered When the supply voltage is above V svys iT4 the trigger for the POR signal becomes inactive after time t svsR elapses When the supply voltage drops below Vsys T another POR is triggered The MSP430x41x devices have one Vsyg level The MSP430x43x and MSP430x44x devices have 14 selectable V sys levels In addition the MSP430x43x and MSP430x44x devices can compare any external voltage not necessarily Vcc that is applied to pin P6 7 A7 SVSin to the internal 1 2 V reference See the specific device data sheet for specifications of the V SYS IT levels System Reset and In
279. e flag with the highest priority responsible for the interrupt vector word is reset TIM HND Interrupt latency 6 ADD amp TBIV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP TIMMOD1 Vector 2 Module 1 2 JMP TIMMOD2 Vector 4 Module 2 2 RETI Vector 6 RETI Vector 8 RETI Vector 10 RETI Vector 12 Timer Overflow Handler the Timer Register is expanded into the RAM location TIMEXT MSBs TIMOVH Vector 14 TIMOV Flag INC TIMEX Handle Timer Overflow 4 RETI 5 TIMMOD2 Vector 4 Module 2 ADD NN amp TBCCR2 Add time difference 5 do Task starts here RETI Back to main program 5 The Module 1 handler shows a way to look if any other interrupt is pending 5 cycles have to be spent but 9 cycles may be saved if another interrupt is pending TIMMOD1 Vector 6 Module 3 ADD PP amp TBCCR1 Add time difference 5 Task starts here JMP TIM HND Look for pending interrupts 2 Ifthe FLL on applicable devices is turned off then two additional cycles need to be added for a synchronous start of the CPU and system clock MCLK If the CPU clock MCLK was turned off in devices with the Basic Clock Module CPUOFF 1 then 2 or 3 additional cycles need to be added for synchronous start of the CPU The delta of one clock cycle is caused when clocks are asynchronous to the restart of CPU clock MCLK Timer B 12 39 Timer B Registers The software
280. e independent of pin direction A direction change does not modify the output buffer contents 8 2 1 3 Direction Registers P1DIR P2DIR The direction registers contain eight independent bits that define the direction of the I O pin All bits are reset by the PUC signal When Bit 0 The port pin is switched to input direction 3 state Bit 1 The port pin is switched to output direction 8 2 1 4 Interrupt Flags P1IFG P2IFG Each interrupt flag register contains eight flags that reflect whether or not an interrupt is pending for the corresponding pin if the I O is interrupt enabled When Bit 0 No interrupt is pending Bit 1 An interrupt is pending due to a transition at the I O pin or from software setting the bit 7 6 Note Manipulating P1OUT and P1DIR as well as P2OUT and P2DIR can result in setting the P1IFG or P2IFG bits 1 Writing a zero to an interrupt flag resets it writing a one to an interrupt flag sets it and generates an interrupt Each group of interrupt flags P1FLG 0 to P1FLG 7 and P2FLG 0 to P2FLG 7 sources its own interrupt vector Interrupt flags P1IFG 0 to P1IFG 7 and P2IFG 0 to P2IFG 7 are not reset automatically when an interrupt from these events is serviced The software should determine the origin of the interrupt and reset the appropriate flag s E 1
281. e instructions if needed See section 5 2 8 for information on number of code words and execution cycles per instruction Figure 5 10 Core Instruction Map 000 040 080 OCO 100 140 180 1CO 200 240 280 2C0 300 340 380 3C0 JNE JNZ JEQ JZ JNC o LL JGE JMP MOV MOV B ADD ADD B ADDC ADDC B SUBC SUBC B SUB SUB B CMP CMP B DADD DADD B BIT BIT B BIC BIC B BIS BIS B XOR XOR B AND AND B POV MOV 0 Po SBE SUBS PSB SUB Z S O PIT BIB BG IC ees BIS BIB S O 5 22 Chapter 6 Hardware Multiplier The hardware multiplier is a 16 bit peripheral module It is not integrated into the CPU Therefore it requires no special instructions and operates independent of the CPU To use the hardware multiplier the operands are loaded into registers and the results are available the next instruction no extra cycles are required for a multiplication Topic Page 6 1 Hardware Multiplier Module Support 6 2 6 2 Hardware Multiplier Operation 6 3 6 3 Hardware Multiplier Registers 6 7 6 4 Hardware Multiplier Special Function lt 6 8 6 5 Hardware Multiplier Software Restrictions 6 8 6 1 Hardware Multiplier Module Support 6 1 Hardware Multiplier Module Su
282. e is executed This has some time benefits since the write process is executed via the flash memory timing generator with out further CPU intervention It is important that the clock source remains active until BUSY is reset by the flash memory hardware The power or clock management responsible for entering low power modes has to make sure that it does not switch off the clock source used by the flash controller For flash memory blocks that hold program code it is a good practice to test the BUSY bit after the write is executed The program can only proceed if the module can be accessed again No special attention is needed during execution of software code Every write to the flash memory module has to leave the programming cycle with the BUSY bit reset Testing the BUSY bit before writing to a flash memory block that holds program code ensures that the active program will not access the flash memory module Two types of access are visible execute program code or read and write data on this flash memory module Flash Memory C 23 Flash Memory Access JTAG and Software C 5 3 2 Example Programming One Word Into the Same Flash Memory Module via Software The program execution waits after the write to flash instruction MOV 123h amp 0FF1Eh until the busy bit is reset again If no other write to flash instruction method is used the BUSY bit test may not be needed to ensure correct flash write handling Disable all interrupt
283. e or more flash memory modules A A flash memory module can not be accessed while being programmed or erased Ifthe active software and thetarget programming location are inthe same flash memory module the program execution is halted flag BUSY 1 until the pro gramming cycle is completed flag BUSY 0 Then it proceeds with the next instruction The active software may also erase segments of the flash memory module The user should be careful not to erase memory locations that are necessary to execute the software correctly Figure C 2 shows the flash memory Module1 in program or erase operation During this operation the module is disconnected from the memory address 2 Flash Memory Organization bus and memory data bus When a second module here Module2 is implemented program code in this module can be executed while Modulet1 is disconnected Figure 2 Flash Memory Module1 Disabled Module2 Can Execute Code Simultaneously e DM oe SEIT UU ete 1 ROM RAM TDI TDO TDI ra lt 16 Bit ZN gt CPU Test To Other Incl 16 Reg JTAG Peripheral Modules NZ DVA X MDB 16 Bit TMS TCK B Flash Flash Test VPP Optional Module 1 Module 2 LILX LL LL
284. e set an interrupt request is generated see the ADC12 Interrupt Vector Register ADC 12IV section The conversion mode may be changed without first stopping the conversions When this is done the new mode takes effect after the current conversion completes see also the Switching Between Conversion Modes section There are three ways to stop repeated conversions on a single channel 1 Select single channel mode instead of repeat single channel mode with the CONSEQ bits When this is done the current conversion is completed normally the result is loaded into ADC12MEM x and the associated interrupt ADC12IFG x is set 2 Reset the ENC bit ADC12CTLO 1 to stop conversions after the current conversion is completed Again the result is loaded into ADC12MEMx and the associated interrupt ADC12IFG x is set 3 Select single channel mode instead of repeat single channel mode and then reset the enable conversion bit ENC When this is done the current conversion stops immediately However the data in memory register ADC12MEMx is unpredictable and the associated interrupt flag ADC12IFG x or may not be set This method is generally not recommended Conversion Modes An illustration of repeat single channel mode is shown in Figure 17 11 Figure 17 11 Repeat Single Channel Mode CONSEQ 2 ADC120N 1 x CStartAdd Wait for Enable SHS 0 and 10r4 and ADC12SC 4 W
285. ecified in the applicable data sheet The control bit BUSY indicates that the write or block write cycle is active It is set by the instruction that writes data to the flash memory module and starts the timing generator It remains set until the write cycle is completed and the programming voltage is removed In the write mode the BUSY bit indicates if the flash memory is ready for another write operation In block write mode the WAIT bit indicates if the flash memory is ready for another write operation and the BUSY bit indicates the block write operation is completed In case of emergency the emergency exit bit EMEX is set and stops the write cycle immediately The programming voltage is switched off One situation where the write cycle should be stopped by software is when the supply voltage drops drastically and the controller s operating conditions may be exceeded Another case is when the flash memory timing gets out of control as when the clock source signal is lost Note Whenever the write cycle is stopped before its normal ending by the hard ware the timing generator is stopped and the data written in flash memory may be marginal Data reading may be inconsistently valid when varying the supply voltage the temperature the access time instruction execution data read or the time LLLLLS A A A A A
286. ected 2 GND 3 Vcc Bits 14 15 Capture mode bits Table 12 9 describes the capture mode selections 12 34 Timer B Registers Table 12 9 Capture Compare Control Register Capture Mode Capture Mode Description 0 Disabled The capture mode is disabled 1 Pos Edge Capture is done with rising edge 2 Neg Edge Capture is done with falling edge 3 Both Edges Capture is done with both rising and falling edges pU ee Note Simultaneous Capture and Capture Mode Selection Captures must not be performed simultaneously with switching from compare to capture mode Otherwise the result in the capture compare reg ister will be unpredictable The recommended instruction flow is 1 Modify the control register to switch from compare to capture 2 Capture For example BIS CAP amp TBCCTL2 Select capture with register TBCCR2 XOR CCIS1 amp TBCCTL2 Software capture CCISO 0 Capture mode 3 LLLLLL O DOEIXI 12 6 4 Timer B Interrupt Vector Register Two interrupt vectors are associated with the 16 bit Timer B module TBCCRO interrupt vector highest priority TBIV interrupt vector for flags CCIFG1 CCIFGx and TBIFG 12 6 4 1 TBCCRO Interrupt Vector The interrupt flag associated with capture compare register TBCCRO as shown in Figure 12 30 is set if the timer value is equal to the compare registe
287. ection High Up Direction Up Down Mode TAR gt CCRO Timer Clock 11 10 Timer Modes In up down mode the interrupt flags CCIFGO and TAIFG are set at equal time intervals Figure 11 15 Each flag is set only once during the period but they are separated by 1 2 the timer period CCIFGO is set when the timer counts from CCRO 1 to CCRO and TAIFG is set when the timer completes counting down from 0001h to 0000h Each flag is capable of producing a CPU interrupt when enabled Figure 11 15 Up Down Mode Flag Setting Timer Clock Timer Up Down Set CCIFGO Set TAIFG 11 3 4 1 Timer In Up Down Mode Changing the Value of Period Register CCRO Changing the period value while the timer is running in up down mode is even trickier than in up mode As in up mode the phase of the timer clock when CCRO is changed affects the timer s behavior Additionally in up down mode the direction of the timer also affects the behavior If the timer is counting in the up direction when the new period is written to CCRO the conditions in the up down mode are identical to those in the up mode See Section 11 3 2 1 for details However if the timer is counting in the down direction when CCRO is updated it continues its descent until it reaches zero The new period takes effect only after the counter finishes counting down to zero See Figure 11 16 Figure 11 16 Altering CCRO Timer in Up Down Mode Timer Register O
288. ed Undefined Undefined Undefined Undefined Undefined Unchanged Comments Set on Watchdog Timer overflow in watchdog mode or security key violation Reset with VCC power up or a reset condition at the RST NMI pin in reset mode Flag set on oscillator fault Not implemented Not implemented Set through the RST NMI pin Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Basic timer flag System Resets Interrupts and Operating Modes 3 15 Interrupt Processing Table 3 6 MSP430x43x Interrupt Flag Registers 1 and 2 Bit Position IFG1 0 IFG1 1 IFG1 2 IFG1 3 IFG1 4 IFG1 5 IFG1 6 IFG1 7 IFG2 0 IFG2 1 IFG2 2 IFG2 3 IFG2 4 IFG2 5 IFG2 6 IFG2 7 Short Form WDTIFG OFIFG NMIIFG URXIFGO UTXIFGO BTIFG Initial State Set Or reset Set Undefined Undefined Reset Undefined Reset Set Undefined Undefined Undefined Undefined Undefined Undefined Undefined Unchanged Comments Set on Watchdog Timer overflow in watchdog mode or security key violation Reset with VCC power up or a reset condition at the RST NMI pin in reset mode Flag set on oscillator fault Not implemented Not implemented Set through the RST NMI pin Not implemented USARTO receive flag USARTO transmit flag Not implemented Not implemented Not implemented Not implemented Not implemented Not implem
289. ed to generate time intervals for the application software Each time an interval is completed an interrupt can be generated In the interrupt service routine of this event the time until the next event is added to capture compare register CCRx as shown in Figure 11 11 Up to five independent time events can be generated using all five capture compare blocks Figure 11 11 Output Unit in Continuous Mode for Time Intervals OFFFFh Interrupt Events CCROf CCROI CCROe CCROd CCROc CCROb CCR0a Oh At At At At At At At Atl At At At At Time intervals can be produced with other modes as well where CCRO is used as the period register Their handling is more complex since the sum of the old CCRx data and the new period can be higher than the CCRO value When the sum CCRxold plus At is greater than the CCRO data the CCRO value must be subtracted to obtain the correct time interval The period is twice the value in the CCRO register 11 3 4 Timer Up Down Mode The up down mode is used if the timer period must be different from the 65 536 clock cycles and if symmetrical pulse waveform generation is needed In up down mode the timer counts up to the content of compare register CCRO then back down to zero as shown in Figure 11 12 The period is twice the value in the CCRO register Figure 11 12 Timer Up Down Mode CCRO Oh Timer_A 11 9 Timer Modes
290. efined Reset Watchdog Timer enable signal Inactive if watchdog mode is selected Active if Watchdog Timer is configured as general purpose timer Oscillator fault interrupt enable Not implemented Not implemented NMI interrupt enable Flash access violation enable Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Basic timer interrupt enable signal t The initial state is the logical state after the PUC signal Table 3 3 MSP430x43x Interrupt Enable Registers 1 and 2 Bit Position IE1 0 IE1 1 IE1 2 IE1 3 IE1 4 IE1 5 IE1 6 IE1 7 IE2 0 IE2 1 IE2 2 IE2 3 IE2 4 IE2 5 IE2 6 IE2 7 Short Form WDTIE OFIE NMIIE ACCVIE URXIEO UTXIEO BTIE Initial Statet Comments Reset Reset Undefined Undefined Reset Reset Reset Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Reset Watchdog Timer enable signal Inactive if watchdog mode is selected Active if Watchdog Timer is configured as general purpose timer Oscillator fault interrupt enable Not implemented Not implemented NMI interrupt enable Flash access violation enable USARTO receive interrupt enable USARTO transmit interrupt enable Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Basic timer interrupt enable signal t The initial
291. elections Timer B 12 33 Timer B Registers Table 12 8 Capture Compare Control Register Output Mode uM Output Mode Description 0 Output only The OUTx signal reflects the value of the OUTx bit 1 Set EQUx sets OUTx 2 PWM EQUx toggles OUTx EQUO resets OUTx toggle reset 3 PWM set reset EQUx sets OUTx EQUO resets OUTx 4 Toggle EQUx toggles OUTx signal 5 Reset EQUx resets OUTx 6 PWM EQUx toggles OUTx EQUO sets OUTx toggle set 7 PWM reset set EQUx resets OUTx EQUO sets OUTx Note OUTx updates with rising edge of timer clock for all modes except mode 0 Modes 2 3 6 7 not useful for output unit 0 Bit 8 CAP sets capture or compare mode 0 Compare mode 1 Capture mode Bits 9 10 CLLD Select load source for compare latch TBCLx also see description of bits TBCLGRP 13 and 14 in TBCTL CLLD 0 Immediate CLLD 1 Load TBCCRx data to TBCLx when TBR counts to 0 CLLD 2 UP DOWN mode load TBCCRx data to TBCLx when TBR counts to TBCLO or to 0 Continuous mode or UP mode load TBCCRx data to TBCLx when TBR counts to 0 CLLD 3 TBCCRx data are loaded to TBCLx when TBR counts to TBCLx Bit 11 SCSx bit This bit is used to synchronize the capture input signal with the timer clock 0 asynchronous capture 1 synchronous capture Bits 12 13 Input select CCISO and CCIS1 These two bits define the capture signal source These bits are not used in compare mode 0 Input CCIxA is selected 1 Input CCIxB is sel
292. em Configuration Oscillator System Clock PROGRAM DATA SMCLK Port Port MAB 16 Bit MDB 16 Bit ipm v Basic Timer Comparator gt Logic Lp Module Select 2 2 Central Processing Unit 2 2 The CPU incorporates a reduced and highly transparent instruction set and a highly orthogonal design It consists of a 16 bit arithmetic logic unit ALU 16 registers and instruction control logic Four of these registers are used for special purposes These are the program counter PC the stack pointer SP the status register SR and the constant generator CGx All registers except the constant generator registers R3 CG2 and part of R2 CG1 can be accessed using the complete instruction set The constant generator supplies instruction constants and is not used for data storage The addressing mode used on CG1 separates the data from the constants The CPU control over the program counter the status register and the stack pointer with the reduced instruction set allows the development of applications with sophisticated addressing modes and software algorithms 2 3 Instruction fetches from program memory are always 16 bit accesses whereas data memory can be accessed using word 16 bit or byte 8 bit instructions Any access
293. ented Not implemented Basic timer flag Table 3 7 MSP430x44x Interrupt Flag Registers 1 and 2 Bit Position IFG1 0 IFG1 1 IFG1 2 IFG1 3 IFG1 4 IFG1 5 IFG1 6 IFG1 7 IFG2 0 IFG2 1 IFG2 2 IFG2 3 IFG2 4 IFG2 5 IFG2 6 IFG2 7 3 16 Short Form WDTIFG OFIFG NMIIFG URXIFGO UTXIFGO URXIFG1 UTXIFG1 BTIFG Initial State Set Or reset Set Undefined Undefined Reset Undefined Reset Set Undefined Undefined Undefined Undefined Reset Reset Undefined Unchanged Comments Set on Watchdog Timer overflow in watchdog mode or security key violation Reset with VCC power up or a reset condition at the RST NMI pin in reset mode Flag set on oscillator fault Not implemented Not implemented Set through the RST NMI pin Not implemented USARTO receive flag USARTO transmit flag Not implemented Not implemented Not implemented Not implemented USART1 receive flag USART1 transmit flag Not implemented Basic timer flag Table 3 8 MSP430x41x Module Enable Registers 1 and 2 Bit Position ME1 0 ME1 1 ME1 2 ME1 3 ME1 4 ME1 5 ME1 6 ME1 7 ME2 0 ME2 1 ME2 2 ME2 3 ME2 4 ME2 5 ME2 6 ME2 7 Table 3 9 MSP430x43x Module Enable Registers 1 and 2 Bit Position ME1 0 ME1 1 ME1 2 ME1 3 ME1 4 ME1 5 ME1 6 ME1 7 ME2 0 ME2 1 ME2 2 ME2 3 ME2 4 ME2 5 ME2 6 ME2 7 Short Form Short Form URXEO USPIEO UTXEO Initial State Undefined Undefined Undefined Undefined Undefined U
294. epeat Sequence of Channels Mode 17 17 17 5 5 Switching Between Conversion Modes 17 19 17 5 6 Power DOWN peste RR 17 20 17 6 Conversion Clock and Conversion Speed 17 21 T Sampling PLE EU 17 22 17 7 1 Sampling Operation ete eee ees 17 22 17 7 2 Sample Signal Input Selection 17 23 17 7 8 Sampling Modes eet eee eens 17 24 177 4 Using the MSO Bit karei ER Odo RESIDEO RP EP hie abe 17 27 17 7 5 Sample Timing Considerations 17 29 17 8 ADC12 Control Registers nn 17 30 17 8 1 Control Registers ADC12CTLO and ADC12CTL1 17 31 17 8 2 Conversion Memory Registers ADC12MEMXx 17 35 17 8 3 Control Registers ADC12MCTLx 17 35 17 8 4 ADC12 Interrupt Flags ADC12IFG x and Interrupt Enable Registers 2 X DEE A aibi SES 17 37 17 8 5 ADC12 Interrupt Vector Register 121 17 37 17 9 A D Grounding and Noise Considerations 17 41 Peripheral File Map 2 1 daonra a eR II ul IIR 1 OVEIVIOW
295. er SR eee ent eee eee 3 12 MSP430x3xx Family Operating Modes 3 23 Typical Current Consumption vs Operating Modes 3 24 Memory Map of Basic Address Space 4 2 Memory Data BUS sani MPH S Abe eR Een eben Ea Fui LREDU 4 2 Bits Bytes and Words in a Byte Organized Memory 4 3 ROM Organization nni iste Eu eere EIE REL LEIDEN DELE 4 4 Byte and Word Operation eee eee eens 4 6 Register Byte Byte Register lt 4 6 Example of RAM Peripheral Organization 4 8 Program ux IE TUM eMe dee eese deret 5 2 System Stack Pointer penu fer nee putt dada 5 2 Stack Ulsag68 oto Lec E eme dci aioe aap eed eae eam Dae nte 5 3 PUSH SP and POP SP uncis or teri o nci dac eoe e Gad Lee ne 5 3 Status Register Bits nn 5 4 Operand Fetch Operation cece tenet eens 5 12 Double Operand Instruction Format 5 17 Single Operand Instruction Format eee nett 5 18 Conditional Jump Instruction 5 19 Core Instruction Map
296. er This is commonly called loopback mode Bit 4 Character length This register bit sets the length of the character to be transmitted as either seven or eight bits CHAR 0 7 bit data CHAR 1 8 bit data Bit 5 Unused Bit 6 Unused Bit 7 Unused Control and Status Registers 14 5 2 Transmit Control Register UOTCTL UTTCTL The transmit control register shown in Figure 14 16 controls the USART hardware associated with transmitter operations Figure 14 16 Transmit Control Register U1TCTL e om oom U1TCTL 079h Bit 0 Bit 1 Bit 2 Bit 3 Bits 4 5 Bits 6 7 Un rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 0 rw 1 Master mode The transmitter empty flag TXEPT is set when the transmitter shift register and UXTXBUF are empty and reset when data written to UXTXBUF It is set again by a SWRST Slave mode The transmitter empty flag TXEPT is not set when the trans mitter shift register and UxTXBUF are empty The slave transmit control bit STC selects if the STE pin is used for master and slave mode STC 0 The four pin mode of SPI is selected The STE signal is used by the master to avoid bus conflicts or is used in slave mode to control transmit and receive enable STC 1 The three pin SPI mode is selected STE is not used in master or slave mode Unused Unused Source select 0 and 1 The source select bits define which clock source is used for baud rate generation o
297. er on the SIMO pin starting with the most significant bit At the same time received data is shifted into the receive shift register and upon receiving the selected number of bits the data is transferred to the receive buffer UxRXBUF setting the receive interrupt flag URXIFG Data is shifted into the receive shift register starting with the most significant bit It is stored and right justified in the receive buffer UXRXBUF When previous data is not read from the receive buffer UxRXBUF the overrun error bit OE is set Note USART Synchronous Master Mode Receive Initiation The master writes data to the transmit buffer UxTXBUF to receive a character The receive starts when the transmit shift register is empty and the data is transferred to it Receive and transmit operations always take place together at opposite clock edges S The protocol can be controlled using the transmit interrupt flag UTXIFG or the receive interrupt flag URXIFG By using UTXIFG immediately after sending the shift register data to the slave the buffer data is transferred to the shift register and the transmission starts The slave receive timing should ensure that there is a timely pick up of the data The URXIFG flag indicates when the data shifts out and in completely The master can use URXIFG to ensure that the slave is ready to correctly receive the next data USART Peripheral Interface SPI Mode 14 7
298. er Registers Register Short Form Register Address Initial State Multiply Unsigned Operand1 MPY Read write 0130h Unchanged Multiply Signed Operand1 MPYS Read write 0132h Unchanged Multiply Accumulate Operand1 MAC Read write 0134h Unchanged Multiply Signed Accumulate Operand1 MACS Read write 0136h Unchanged Second Operand OP2 Read write 0138h Unchanged Result Low Word ResLo Read write 013Ah Undefined Result High Word ResHi Read write 013Ch Undefined Sum Extend SumExt Read 01 Undefined Two registers are implemented for both operands OP1 and OP2 as shown in Figure 6 3 Operand 1 uses four different addresses to address the same register The different address information is decoded and defines the type of multiplication operation used Figure 6 3 Registers of the Hardware Multiplier 6 6 15 130h MPYS 132h MAC 134h MACS 136h bos nd OP2 138h Operand 2 OP2 ResLo 13Ah Result Low Word ResLo ResHi 13Ch Result High Word ResHi SumExt 13Eh Sum Extension Word SumExt The multiplication result is located in two word registers result high RESHI and result low RESLO The sum extend register SumExt holds the result sign of a signed operation or the overflow of the multiply and accumulate MAC operation See Section 6 5 3 for a description of overflow and underflow when using the MACS operations All registers have the least significant bit LSB at bitO and the most sign
299. er number 0 15 The byte identifier B W indicates whether the instruction is executed as a byte B W 1 or as a word instruction B W 0 Figure B 1 Double Operand Instructions B 4 15 12 11 8 7 6 5 4 3 0 OP Code Source Register Destination Register Operational Code Field ADD W ADD B src dst src dst dst ADDC W ADDC B src dst src dst C dst AND W AND B src dst src and dst dst BIC W BIC B src dst not src and dst dst BISL W BIS B src dst src or dst dst BITB srcdst src and dst CMP W 05 dst src DADD W DADD B src dst src dst C dst dec MOV W MOVB src dst src gt dst SUB W 50 src dst dst not src 1 dst SUBC W SUBC B src dst dst not src C dst XOR W XOR B src dst src dst dst Status Bits VN Note Operations Using the Status Register SR for Destination All operations using Status Register SR for destination overwrite the SR contents with the operation result as described in that operation the status bits are not affected Example ADD 3 SR Operation SR 3 gt SR Instruction Set Overview B 1 1 2 Single Operand Instructions Core Instructions The instruction format using a single operand as shown in Figure 2 consists of two main fields to form a 16 bit code L operational code field nine
300. eration As with any RC type oscillator frequency varies with temperature and voltage The FLL hardware automatically stabilizes MCLK SMCLK The FLL compares the ACLK to MCLK Dx N 1 and counts up or down a 10 bit frequency integrator The MCLK SMCLK is constantly adjusted to one of 1024 possible settings The output of the frequency integrator that drives the DCO can be read in SCFI1 and SCFIO The count is adjusted 1 or 1 with each crystal period 30 5 us using 32 768 Hz Of the 10 bits from the frequency integrator 5 bits are used for DCO frequency taps and 5 bits are used for a modulator The 5 bits for the DCO tap are contained in the SCFI1 1 7 SCFI11 3 There are 29 taps implemented in the DCO TAPS 28 29 30 and 31 are equivalent each being approximately 10 higher than the previous In most applications a fraction tap may be required to achieve the programmed MCLK SMCLK over the full range of system operation see Figure 7 4 Figure 7 4 Fractional Tap Frequency Required fn 2 fn 1 fn fn 2 ae Discrete DCO Taps DCO Output P Frequency Spectrum Required Fractional Tap FLL Clock Module 7 7 Digitally Controlled Oscillator DCO and Frequency Locked Loop 7 3 2 Modulator Operation The modulator overcomes relatively large tap steps by mixing a DCO tap with the next higher frequency tap DCO 1 The DCO mixing or hop pattern is controlled with 5 bits thus there are 32 possible m
301. eripheral Modules 8bT C yte OFh Oh Special Function Registers SFR Byte The memory data bus MDB is 16 or 8 bits wide For those modules that can be accessed with word data the width is always 16 bits For the other modules the width is 8 bits and they must be accessed using byte instructions only The program memory ROM and the data memory RAM can be accessed with byte or word instructions Figure 4 2 Memory Data Bus Address Range 0000h 00 8 Bit Peripheral Modules Byte Word 16 Bit Peripheral Modules Byte Access Access Word Access 4 2 Data the Memory 4 2 Data in the Memory Bytes are located at even or odd addresses as shown in Figure 4 3 However words are only located at even addresses Therefore when using word instructions only even addresses may be used The low byte of a word is always at an even address The high byte of a word is at the next odd address after the address of the word For example if a data word is located at address xxx2h then the low byte of that data word is located at address xxx2h and the high byte of that word is located at address xxx3h Figure 4 3 Bits Bytes and Words a Byte Organized Memory Te TT rr e m Eo Memory 4 3 Internal ROM Organization 4 3 Internal ROM Organization Various sizes of on chip memory are available within the 64 address space as shown in Figure 4 4 The common address space is shared with SFRs
302. eripherals clock system on chip DCO 2 crystal oscillators Watchdog Timer general purpose timer ADC12 12 bit A D Comparator A precision analog comparator ideal for slope A D conversion Brownout SVS Basic Timer1 two 8 bit timers or one 16 bit timer LCD controller driver up to 160 segments Timer 16 bit timer with three capture compare registers and PWM output Timer 16 bit timer with three capture compare registers PWM output port 1 2 eight I Os each all with interrupt ports 3 4 5 6 eight I Os each USARTO Package option 80 pin QFP or 100 pin QFP D DDDD O The 43x device family includes MSP430F435t 16 KB flash memory 512 KB RAM MSP430F436f 24 KB flash memory 1 MSP430F4371 32 KB flash memory 1 KB RAM t Advanced Information future devices Introduction 1 3 44x Devices 1 4 44x Devicest The 44x devices contain the following peripherals COOCOO D DUDDD O OOL FLL clock system on chip DCO 2 crystal oscillators Watchdog Timer general purpose timer ADC12 12 bit A D Comparator_A precision analog comparator ideal for slope A D conversion Brownout SVS Basic Timer1 two 8 bit timers or one 16 bit timer LCD controller driver up to 160 segments Timer 16 bit timer with three capture compare registers PWM output Timer B37 16 bit timer with seven capture compare registers and PWM out
303. ert one of eight external analog inputs or one of four internal voltages The four internal channels are used for temperature measurement via on chip temperature diode and for measurement of Vcc via Vcc 2 and the positive and negative references applied on Veggf and Vngr Vengr The ADC12 can use its internal reference or it can use external reference s or a combination of internal and external reference voltage levels Introduction The ADC12 has versatile sample and hold circuitry giving the user many options for control of the sample timing The sample timing may be directly controlled by software via a control bit or any one of three internal or external signals depending on device configuration see the Sampling section and check the data sheet for details Typically the internal timing signals come from other MSP430 timers such as Timer A Additionally the sample timing may be programmed as a multiple of the ADC12 conversion clock As with sample timing the user has several choices for the ADC12 conversion clock The ADC12 conversion clock may be chosen from any available internal MSP430 clock or may be selected from a dedicated oscillator contained in the ADC12 peripheral Additionally the chosen clock source may be divided by any factor from 1 to 8 The ADC12 has four operating modes It can be configured to perform a single conversion on a single channel or multiple conversions on a single channel The ADC12 can
304. es Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers on captures or compares Each capture compare block is individually configurable and can produce interrupts on compares or on rising falling or both edges of an external capture signal The block diagram of Timer B is shown in Figure 12 1 12 1 1 Similarities and Differences From Timer A 12 2 Timer Bis almost identical to Timer A except for a few enhancements noted below and operates identically to Timer A in it s default condition Timer B is different from Timer A in the following ways 1 The length of Timer B is programmable to be 8 10 12 or 16 bits where as Timer A is only a 16 bit timer 2 The SCCI bit functionality of the capture compare registers of Timer A is not implemented in Timer B 3 The function of the capture compare registers for the compare mode of Timer B has changed slightly 4 On some devices a pin is implemented to put all Timer B outputs into a high impedance state Check the device data sheet for the presence of this pin On Timer A the capture compare register CCRx holds the data for the comparison to the timer value On Timer B each TBCCRx acts as a buffer for a compare latch and the compare latch holds the data used for the comparison So compare data is written to each capture compare register in both timers however in Timer the compare data is then transferred to th
305. ess idle line wake up Two multiprocessor protocols idle line and address bit are supported by the USART module The choice of multiprocessor mode affects the operation of the automatic address decoding functions MM 0 Idle line multiprocessor protocol MM 1 Address bit multiprocessor protocol The conventional asynchronous protocol uses MM bit reset Mode or function of USART module selected The SYNC bit selects the function of the USART peripheral interface module Some of the USART control bits have different functions in UART and SPI mode SYNC 0 UART function is selected SYNC 1 SPI function is selected Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Control and Status Registers The listen bit selects if the transmitted data is fed back internally to the receiver Listen 0 No feedback Listen 1 Transmitsignalis internally fed backto the receiver This is commonly known as loopback mode Character length This register bit selects the length of the character to be transmitted as either 7 or 8 bits 7 bit characters do not use the eighth bit in UXRXBUF and UxTXBUF This bit is padded with 0 CHAR 0 7 bit data CHAR 1 8 bit data Number of stop bits This bit determines the number of stop bits transmitted The receiver checks for one stop bit only SP 0 one stop bit SP 1 two stop bits Parity odd even If the PENA bit is set parity bit is enabled the PEV bit defines odd or even parity ac
306. et to the reset function the CPU is held in the reset state as long as the RST NMI pin is held low After the input changes to a high state the CPU starts program execution at the word address stored in word location OFFFEh reset vector If the RST NMI pin is set to the NMI function a signal edge selected by the NMIES bit will generate an unconditional interrupt When accepted program execution begins at the address stored in location OFFFCh The RST NMI flag in the SFR IFG1 4 is also set When configured in the NMI mode a signal generating NMI event should not hold the RST NMI pin low When a PUC is generated see Section 3 1 1 the resets the bits in the WDTCTL register This results in the RST NMI pin being configured in the reset mode If the signal on the RST NMI pin that generated the NMI event holds the pin low the processor will be held in the reset state When NMI mode is selected and the NMI edge select bit is changed an NMI can be generated depending on the actual level at RST NMI pin When the NMI edge select bit is changed before selecting the NMI mode no NMI is generated The NMI interrupt is maskable by the NMIIE bit LLLLLLL 3 Operation of Global Interrupt Oscillator Fault Control The oscillator fault signal warns of a possible error condition with the crystal oscillator It is
307. f UCLK is transmitted on the SOMI pin using the UCLK supplied from the master Simultaneously the serial data applied to the SIMO pin are shifted into the receive shift register on the opposite edge of the clock The receive interrupt flag URXIFG indicates when the data is received and transferred into the receive buffer The overrun error bit is set when the previously received data is not read before the new data is written to the receive buffer 14 3 2 1 Four Pin SPI Slave Mode 14 8 In the four pin SPI mode the STE signal is used by the slave to enable the transmit and receive operations It is applied from the SPI master The receive andtransmit operations are disabled when the STE signalis high and enabled when it is low Whenever the STE signal becomes high any receive operation in progress is halted and then continues when the STE signal is low again The STE signal enables one slave to access the data lines The SOMI is input if STE is set high Interrupt and Control Functions 14 4 Interrupt and Control Functions The USART peripheral interface serves two main interrupt sources for transmission and reception Two interrupt vectors serve receive and transmit interrupt events The interrupt control bits and flags and enable bits of the USART peripheral interface are located in the SFR address range The bit functions are described below in Table 14 1 See the peripheral file map in Appendix A for the exact bit locations
308. f the LCD voltages thereby providing for temperature compensation or contrast adjustment If this not desired the user may simply connect to Vss Figure 16 6 External LCD Module Analog Voltage Analog Levels Voltage Connections For the Different Modes Static 2 4 open Open R R Analog MUX open e9 9 R R LCD Phases LCDMO LCDM3 Vss LCDM4 OscOff OscOff LCDM4 LCDM3 LCDMO VA VB VD R33t 0 0 1 X X X 0 0 0 0 OFF 0 0 0 1 V5 V1 V1 V5 V5 V1 V1 V5 0 0 1 1 V5 V1 V1 V5 V3 V3 VINV5 ON 0 1 X 1 V5 V1 2 4 4 2 V1N5 ON T Indicates the position of the Ron switch controlled by the LCDMO bit t Supply pins for V1 and V5 are optional Devices without R33 and R03 pins have V1 tied to Vcc and V5 tied to Vss In this case the resistor ladder should also be tied to Vss Liquid Crystal Display Drive 16 9 LCD Controller Driver 16 2 4 LCD Outputs 16 10 The LCD outputs use transmission gates to transfer the analog voltage at pins R33 R23 R13 and to the output pin where they are used to drive liquid crystal displays Groups of LCD outputs can be configured to operate as digital outputs Digital outputs are standard port outputs LCD segments common lines and the analog level pins R33 R03 may be shared with digital port functions See the device data sheet 7
309. f the LFXT1 frequency for signal ACLK n Signal ACLK n can be selected to be used at pin P1 5 TACLK ACLK n 1 ACLK n signal is ACLK n 2 ACLK n signal is ACLK 2 n 4 ACLK n signal is ACLK 4 n 8 ACLK n signal is ACLK 8 SELS selects the clock source signal for peripheral module clock 0 SMCLK DCOCLK 1 SMCLK XT2CLK SELM selects the clock source signal for MCLK used by the CPU 0 1 MCLK DCOCLK 2 MCLK XT2CLK 3 MCLK ACLK from LFXT1 oscillator Switches off the second crystal oscillator XT2 0 XT2 oscillator off if it is not used for MCLK SELM 2 or CPUOff 1 and if it is not used for SMCLK SELS 0 or SMCLKOFF 1 1 XT2 oscillator is on SMCLKOFF Switfhes off clock SMCLK 0 SMCLK on 1 SMCLK off FLL Clock Module 7 15 FLL Module Control Registers 7 7 2 Special Function Register Bits 7 16 The FLL clock module affects two bits in the special function registers OFIFG and OFIE The oscillator fault interrupt enable bit OFIE is located in bit 1 of the interrupt enable register IE1 The oscillator fault interrupt flag bit OFIFG is located in bit 1 of the interrupt flag register IFG1 IE1 7 6 5 4 3 2 1 0 o C ENS rw 0 IFG1 7 6 5 4 3 2 1 0 oh 0 rw 1 The oscillator fault signal sets the OFIFG as long as the oscillator fault condition is active The detection and effect of the oscillator fault condition is described in section 7 4 The oscillat
310. from interrupt Two different modes are available to return from the interrupt service routine and continue the flow of operation B Return with low power mode bits set When returning from the interrupt the program counter points to the next instruction The instruction pointed to is not executed since the restored low power mode stops CPU activity System Resets Interrupts and Operating Modes 3 21 Operating Modes 3 22 B Return with low power mode bits reset When returning from the interrupt the program continues at the address following the instruction that set the OscOff or in the status register To use this mode the interrupt service routine must reset the OscOff CPUOff SCGO and SCG1 bits on the stack Then when the SR contents are popped from the stack upon RETI the operating mode will be active mode AM The software can configure five operating modes Active mode SCG1 0 5660 0 OscOff 0 CPUOff 0 CPU clocks are active Low power mode 0 LPMO SCG1 0 SCGO 0 OscOff 0 CPUOff 1 CPU is disabled 41x ACLK MCLK and SMCLK MCLK SMCLK remain active 43x 44x ACLK and SMCLK remain active MCLK is disabled Loop control for MCLK remains active Low power mode 1 LPM1 SCG1 0 SCGO 1 OscOff 0 CPUOff 1 CPU is disabled Loop control for MCLK is disabled 41x ACLK MCLK SMCLK MCLK SMCLK remain active 43x 44x ACLK and SMCLK remain active MCLK is disabled Low
311. fted into the LSB of R5 BIT B 2 amp 1 Information Carry RLC B R5 Carry POin 1 LSB of R5 High byte of R5 is reset Note RLC and RLC B Emulation The assembler does not recognize the instruction RLC QR5 It must be substituted by ADDC R5 2 R5 RRA W RRA B Syntax Operation Description Instruction Set Overview Rotate right arithmetically Rotate right arithmetically RRA dst or RRA W dst RRA B dst MSB MSB MSB MSB 1 LSB 1 gt LSB LSB gt C The destination operand is shifted right one position as shown in Figure 8 The MSB is shifted into the MSB the MSB is shifted into the MSB 1 and the LSB 1 is shifted into the LSB Figure B 8 Destination Operand Arithmetic Right Shift Word 15 0 Status Bits Mode Bits Set if result is negative reset if positive Set if result is zero reset otherwise Loaded from the LSB Reset OscOff CPUOff and GIE are not affected Instruction Set Description B 49 Running Title Attribute Reference Example OR Example OR R5 is shifted right one position The MSB retains the old value It operates equal to an arithmetic division by 2 5 R5 2 gt R5 The value in R5 is multiplied by 0 75 0 5 0 25 PUSH R5 hold R5 temporarily using stack RRA R5 5 0 5 R5 ADD SP R5 5 0 5 5 1 5 5 R5 R5 1 5 x R5 x 0 5 0 75 x R5 R5 RRA R5
312. ftware Restrictions 6 5 2 Hardware Multiplier Software Restrictions Interrupt Routines 6 5 2 1 The entire multiplication routine requires only three steps 1 Moveoperand OP1 tothe hardware multiplier this defines the type of mul tiplication 2 Move operand OP2 to the hardware multiplier the multiplication starts 3 Process the result of the multiplication in the RESLO RESHI and SUMEXT registers The following considerations describe the main routines that use hardware multiplication If no hardware multiplication is used in the main routine multiplication in an interrupt routine is protected from further interrupts because the GIE bit is reset after entering the interrupt service routine Typically a multiplication operation that uses the entire data process occurs outside an interrupt routine and the interrupt routines are as short as possible A multiplication operation in an interrupt routine has some feedback to the multiplication operation in the main routine Interrupt Following an OP1 Transfer The two LSBs of the first operand address define the type of multiplication operation This information cannot be recovered by any later operation Therefore an interrupt must not be accepted between the first two steps move operand OP1 and OP2 to the multiplier 6 5 2 2 Interrupt Following an OP2 Transfer After the first two steps the multiplication result is in the corresponding registers RESLO RESHI and SUMEXT I
313. g instruction The status register zero bit Z is tested If it is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If Z is not set the instruction following the jump is executed Status bits are not affected Jump to address TONI if R7 contains zero TST R7 Test R7 JZ TONI if zero JUMP Jump to address LEO if R6 is equal to the table contents CMP R6 Table R5 Compare content of R6 with content of MEM table address content of R5 JEQ LEO Jump if both data are equal de No data are not equal continue here Branch to LABEL if R5 is O TST R5 JZ LABEL Operation Description Status Bits Example Instruction Set Overview Jump if greater or equal JGE label If N XOR V 0 then jump to label PC 2 x offset gt PC If N XOR V 1 then execute the following instruction The status register negative bit N and overflow bit V are tested If both N and V are set or reset the 10 bit signed offset contained the instruction LSBs is added to the program counter If only one is set the instruction following the jump is executed This allows comparison of signed integers Status bits are not affected When the content of R6 is greater or equal to the memory pointed to by R7 the program continues at label EDE CMP QR7 R6 R6 gt R7 compare on signed numbers JGE EDE Yes R6 R7 cr No proceed Instructio
314. gister is set Immediately after the bit is set the CPU stops operation and the normal operation of the system core stops The operation of the CPU halts and all internal bus activities stop until an interrupt request or reset occurs The System clock generator continues operation and the clock signals MCLK SMCLK and ACLK stay active depending on the state of the other three status register bits SCGO SCG1 and The peripherals are enabled or disabled according with their individual control register settings and with the module enable registers in the SFRs All port pins and RAM registers are unchanged Wake up is possible through all enabled interrupts The following are examples of entering and exiting LPMO The method shown is applicable to all low power modes The following example describes entering into low power mode 0 Main program flow with switch to CPUOff Mod BIS 18h SR Enter LPMO enable general interrupt GIE CPUOff 1 GIE 1 The PC is incremented during execution of this instruction and points to the consecutive program step VPE The program continues here if the CPUOff Operating Modes bit is reset during the interrupt service routine Otherwise the PC retains its value and the processor returns to LPMO The following example describes clearing low power mode 0 Interrupt service routin CPU is active while handling interrupts 10h 0 S
315. gnal active Condition after POR signal active The tables in the following sections describe byte access to each peripheral file according to the previously described definitions Special Function Register of MSP430x4xx Family Byte Access A 2 Special Function Register of MSP430x4xx Family Byte Access Module enable 2 ME2 0005h Module enable 1 ME1 URXE1 USPIE1 rw 0 UTXE1 rw 0 0004h Interrupt flag 2 IFG2 UTXIFG1 URXIFG1 0003h rw 1 rw 0 Interrupt flag 1 IFG1 UXIFGO URXIFGO NMIIFG 0002h rw 1 rw 0 rw 0 Interrupt enable 2 IE2 UTXIE1 URXIE1 0001h rw 0 rw 0 Interrupt enable 1 IE1 UTXIEO URXIEO ACCVIE NMIIE 0000h rw 0 rw 0 rw 0 rw 0 Note SFR bits are not implemented on devices without the corresponding peripheral Digital I O Byte Access Bit 7 6 5 4 3 2 1 0 Function select PASEL P4SEL 7 PASEL 6 P4SEL 5 P4SEL 4 P4SEL 3 PASEL 2 PASEL 1 PASEL O 001Fh rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Direction register PADIR P4DIR 7 P4DIR 6 P4DIR 5 P4DIR 4 P4DIR 3 P4DIR 2 P4DIR 1 PADIR O 001Eh rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Output register PAOUT PAOUT 7 PAOUT 6 PAOUT 5 PAOUT 4 PAOUT 3 PAOUT 2 4 1 PAOUT O 001Dh rw rw rw rw rw rw rw rw Input register P4IN 7 P4IN 6 PAIN 5 P4IN 4 PAIN 3 P4IN 2 PAIN 1 PAIN O 001Ch r r r r r r r P3SEL 7 P3SEL 6 P3SEL 5 PSSEL 4 PSSEL 3 PSSEL 2 PSSEL 1 PSSEL O rw 0 rw 0 rw 0 rw 0 rw 0 r
316. gramming is in progress 1 Block write operation is active and programming of data is completed Waiting for the next data to be programmed The Lock bit can be set during any write erase of a segment or mass erase request The active sequence is completed normally In block write mode if the Lock bit is set and BLKWRT and WAIT are set the BLKWRT and WAIT bits are reset and the mode ends normally The WAIT bit is 1 after block write mode has ended Software or hardware can control the Lock bit If an access violation occurs see conditions described in paragraph C 1 1 the ACCVIFG and the Lock bit are set 0 Flash memory can be read programmed erased and mass erased 1 Flash memory can be read but not programmed erased or mass erased A current program erase or mass erase operation is completed normally The access violation interrupt flag ACCVIFG is set when the flash memory module is accessed while the Lock bit is set Flash Memory C 17 Flash Memory Interrupt and Security Key Violation EMEX 012Ch bit5 Emergency exit The emergency exit should only be used when a flash memory write or erase operation is out of control 0 No function 1 Stopsthe active operation immediately and shuts down all internal parts of the flash memory controller Current consumption immediately drops back to the active mode All bits in control register FCTL1 are reset Since the EMEX bitis automatically reset by hardware the software
317. h 09Ch 09Bh 09Ah 099h 098h 097h 096h 095h 094h 093h 092h 091h 16 12 3 di Associated 4 d Segment Line 38 36 34 32 30 28 26 24 39 38 37 36 85 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lt reset condition LCD Controller Driver 16 2 6 1 Example Using the Static Drive Mode The static drive mode uses one common line COMO In this mode only bit 0 and bit 4 are used for segment information The other bits can be used like any other memory Figure 16 10 shows an example static LCD pin out LCD to 430 connections and the resulting data mapping Note this is only an example Segment mapping in a user s application completely depends on the LCD pin out and on the 430 to LCD connections Liquid Crystal Display Drive 16 13 LCD Controller Driver Figure 16 10 Example With the Static Drive Mode LCD Pinout and Connections Display Memory Connections COM 131 2 1 0 Sf 2 1 0 430 Pins LCD Pinout PIN como 0A0h O9Fh O9Eh 09Dh 09Ch O9Bh 09Ah 099h 098h 097h 096h 095h 094h 093h 092h 091h 0 1 2 3 54 55 56 57 58 59 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 1 2 Parallel Serial Conversi
318. handler 7 T BCCRx Int hand Start of handler Interrupt MOV amp Buffer COV amp TBCCTLx JNZ Overflow_Hand correct capture data RETI Overflow Hand BIC COV amp reset capture overflow flag get back to lost Synchronization Proceed RETI p SOO OO ch Note Capture With Timer Halted The capture should be disabled when the timer is halted The sequence to follow is stop the capture then stop the timer When the capture function is restarted the sequence should be start the capture then start the timer a 12 4 1 1 Capture Compare Block Capture Mode Capture Initiated by Software 12 18 In addition to internal and external signals captures can be initiated by software This is useful for various purposes such as To measure time used by software routines To measure time between hardware events To measure the system frequency Two bits CCISx1 and CCISx0 and the capture mode selected by bits CCMx1 and CCMxO are used by the software to initiate the capture The simplest realization is when the capture mode is selected to capture on both edges of CCIx and bit CCISx1 is set Software then toggles bit CCISxO to switch the capture signal between Vcc and GND initiating a capture each time the input is toggled as shown in Figure 12 21 Timer Modes Figure 12 21 Software Capture Example OH
319. he Flash Memory Module Write 1 to SSEL1 FNS FNO EMEX SSELO ACLK MCLK 1 Reset SMCLK O Flash Timing Generator SMCLK Busy Wait The selected clock source should be divided to meet the frequency require ment fx of the flash timing generator If the clock signals are not available throughout the duration of the write or erase operation or their frequencies change drastically the result of the write or erase may be marginal or the flash memory module may be stressed above the limits of reliable operation Table 1 shows all useful combinations of control bits for proper write and erase operation Flash Memory C 7 Flash Memory Data Structure and Operation Table C 1 Control Bits for Write or Erase Operation FUNCTION PERFORMED BLKWRT WRT Meras Erase BUSY WAIT Lock Write word or byte 0 1 0 0 0 0 0 Write word or byte in same block block write 1 1 0 0 0 1 0 mode Erase one segment by writing to any address 0 0 0 1 0 0 0 in the target segment 0 to n or A or B Erase all segments 0 to n but not the infor 0 0 1 0 0 0 0 mation memory SegmentA and SegmentB Erase all segments 0 to n and A and B by 0 0 1 1 0 0 0 writing to any address in the flash memory module Note A write to flash memory performed with any other combination of bits BLKWRT WRT Meras Eras BUSY WAIT and Lock will result in an access violation ACCVIFG is set and NMI is req
320. he crystal needs to be connected and no other external components are required Additional load capacitors are required when using the LFXT1 oscillator with a high speed crystal In addition to the crystal oscillator all MSP430 devices contain a digitally controlled RC oscillator DCO The DCO is different from RC oscillators found on other microcontrollers because it is digitally controllable and tuneable MSP430x4xx devices contain an additional logic block called the frequency locked loop FLL The FLL continuously and automatically adjusts the frequency of the DCO relative to the 32768 Hz crystal oscillator to stabilize the DCO over voltage and temperature This provides an effective stable ultralow power oscillator for the CPU and peripherals Clock source selection for peripherals and CPU is very flexible Most peripherals are capable of using the 32 768 Hz crystal oscillator clock the high speed crystal oscillator clock where applicable or the DCO clock The CPU uses the DCO clock for execution Additionally the LFXT1 and XT2 clock signals may be used for CPU execution on 43x and 44x devices See Chapter 7 for details on the clock system Chapter 3 System Resets Interrupts and Operating Modes This chapter discusses the MSP430x4xx system resets interrupts and operating modes Topic Page 3 4 System Reset and 3 2 3 2 Global Interrupt Structure
321. he on chip temperature diode the user simply selects the analog input channel to 10 Any other configuration is done as if an external channel was selected including reference selection conversion memory selection etc Selecting the diode channel automatically turns on the on chip reference generator see Figure 17 1 as a voltage source for the temperature diode However itdoes not enable the Vngr outputor affect the reference selections for the conversion so reference selections are the same as with any other channel See the device data sheet for the temperature diode specifications ADC12 17 7 Conversion Memory 17 4 Conversion Memory 17 8 A typical approach in single channel converters uses an interrupt request to signal the end of the conversion and requires the conversion data to be moved to another location before another conversion can be performed However the ADC12 incorporates 16 conversion memory registers ADC12MEMx see Figure 17 1 allowing the A D converter to run multiple conversions without software intervention This increases the system performance by reducing software overhead Additionally each of the 16 conversion memory registers has an associated control register ADC12MCTLx allowing total flexibility for each conversion The memory control registers allow the user to specify the channel and reference s used for each individual conversion All other control bits that configure the other operating c
322. he software via ADC12SC or external signals can start a conversion only if the enable conversion bit ENC is high Most of the control bits in ADC12CTLO and ADC12CTL 1 and all bits in ADCMCTL x may be changed only if ENC is low 0 No conversion can be started This is the initial state 1 The first sample and conversion starts with the first rising edge of the SAMPCON signal The selected operation proceeds as long as ENC is set CONSEQ 0 ADC12BUSY 1 1 0 In this mode if ENC is reset the current conversion is immediately stopped The conversion results are unpredictable CONSEQx2zO0 ADC12BUSY x ENC 1 0 In these modes if ENC is reset the current conversion or sequence is completed and the conversion results are valid The conversion activities are stopped after the current conversion or sequence is completed ADC12 17 31 ADC12 Control Registers ADC12TOVIE bit2 Conversion time overflow interrupt enable The timing overflow happens if another sample and conversion is requested while the current conversion is not completed This is independent of the conversion modes selected by CONSEQ If the timing overflow vector is generated and the timing overflow interrupt enable flag ADC12TOVIE and the general interrupt enable bit GIE are set an interrupt service is requested There is no individual interrupt flag See the ADC12 Interrupt Vector Register ADC 121V section for more information on ADC12 interrupts ADC12OVIE
323. he timer before changing the clock source The selected clock source may be passed directly to the timer or divided by 2 4 or 8 as shown in Figure 11 4 The IDO and ID1 bits in the TACTL register select the clock division Note that the input divider is reset by a POR signal see chapter 3 System Resets Interrupts and Operating Modes for more information on the POR signal or by setting the CLR bit in the TACTL register Otherwise the input divider remains unchanged when the timer is modified The state of the input divider is invisible to software Figure 11 3 Schematic of 16 Bit Timer SSEL1 SSELO Timer Clock Data Input Divider SMCLK 5 24 ipi TACLK o o 2 1 o gt IDO Carry Zero Mco Set 3 POR CLR INCLK 5o 0 0 Pass 0 5 0 1 1 2 0 1 Up Mode 1 0 1 4 1 0 Continuous Mode 1 1 1 8 1 1 Up Down Mode Figure 11 4 Schematic of Clock Source Select and Input Divider SSEL1 SSELO TACLK 0 0 0 Input Divider 16 Bit Timer Clock o 63 100 CLR 0 Pass 0 1 12 1 14 1 1 18 Timer Modes 11 2 3 Starting the Timer 11 3 Timer Modes The timer may be started or restarted in a variety of ways Release Halt Mode The timer counts in the selected direction when a timer mode other than stop mode is selected with the MCx bits H
324. iated with the each conversion memory register used in the sequence For example if a sequence of conversions uses ADC12MEM3 ADC12MEM6 then the channel and reference s for each conversion are individually configurable with ADC12MCTL3 ADC12MCTL6 The end of a sequence is marked by the end of sequence bit EOS in the last conversion memory control register used in the sequence Each conversion memory control register contains an EOS bit All EOS bits of the conversion memory control registers used in a sequence must be reset except for the last one in the sequence For example if a sequence starts with ADC12MEM7 and ends with ADC12MEM12 then the EOS bit of registers ADC12MCTL7 ADC12MCTL11 must be reset and the EOS bit of ADC12MCTL12 must be set Conversions stop when the end of a sequence is reached When software is using the ADC10SC bit to initiate a sequence successive sequences can be initiated by simply setting the ADC10SC bit the ENC bit can remain set or may be set at the same time as ADC 10SC However when any other trigger source ADC10I1 ADC1012 or ADC10I3 is being used to start a sequence the ENC bit must be toggled between each sequence All additional incoming sample input signals will be ignored until the ENC bit is reset and set again The conversion mode may be changed after the conversion begins but before it has completed and the new mode will take effect after the current sequence has completed See also
325. ication requires the system frequency to remain constant for a short period of time both the modulation and the FLL should be disabled M 1 SCGO 1 FLL Clock Module 7 13 FLL Module Control Registers Figure 7 8 SCFIO and SCFI1 Registers 7 0 SCFIO 050h FN_8 FN_4 FN3 FN2 2 1 2 0 rw 0 rw 1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 0 SCFH 051h 2 9 2 8 2 7 2 6 2 5 2 4 2 8 2 2 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 NDCO NOTE DCO Fault indicates that the upper Np co 0 and lower Np co 0 limit of the DCO frequency range is used FN 2to FN 8 DCO range control bits see Table 7 1 D Divides the system frequency fsystem by 1 2 4 8 0 1 1 2 2 14 3 8 Figure 7 9 FLL Control Registers 0 and 1 7 0 FLL CTLO rw 0 rw 0 rw 0 rw 0 ro ro r 1 r 1 0 7 FLL CTL1 ro ro rw 1 rw 0 rw 0 rw 0 rw 0 rw 0 Additional Control Bits in vs FLL in 3xx devices 1 Not present on 41x devices Bits 0 3 The DCOF LFOF XT1OF and XT2OF bits are used to signal an oscillator fault DCOF is used for the DCO LFOF is ued for the LFXT1 oscillator in LF mode XT1OF is used for the LFXT1 oscillator in HF mode and XT2OF is used for the XT2 oscillator The oscillator fault flag OFIFG is set if one or more of these fault signals are set These bits are read only and are set or reset according to the fault condition 0 No fault condition preset 1 Respective fault condition is preset
326. ificant bit MSB at bit7 byte data or bit15 word data Hardware Multiplier Special Function Bits 6 4 Hardware Multiplier Special Function Bits Because the hardware multiplier module completes all multiplication operations quickly without interrupt intervention no special function bits are used 6 5 Hardware Multiplier Software Restrictions 6 5 1 Two restrictions require attention when the hardware multiplier is used The indirect or indirect autoincrement address mode used to process the result The hardware multiplier used in an interrupt routine Hardware Multiplier Software Restrictions Address Mode The result of the multiplication operation can be accessed in indexed indirect or indirect autoincrement mode The result registers may be accessed without any restrictions if you use the indexed address mode including the symbolic and absolute address modes However when you use the indirect and indirect autoincrement address modes to access the result registers you need atleast one instruction between loading the second operand and accessing one of the result registers KKK KKK ck ck ck KKK kk Ck Ck ck ck kk Ck ck Ck kk ck ck ck kk Ck ck ck ck kk ck ck ck kk Ck ck ck ko Mk Mk Sk kc k ko kx ko ko ko k EXAMPLE MULTIPLY OPERAND1 AND OPERAND2 Ck Ck Ck ck ck KKK KEK KKK Ck Ck ck ck Sk Ck Ck ck Ck kk Ck ck ck kk Ck Ck ck ck ok kk ck ck ck kk Ck ck Sk ko Mk ko Sk Sk kA kv kx ko kock ok
327. ift Register 13 8 TX Buffer UXTXBUF TX Shift Register TXWake Start Bit Parity Bit i gt TXSignal Asynchronous Operation The following procedure sends out an idle frame to identify an address character 1 Setthe TXWake bit and then write any word don t care to the UXTXBUF UTXIFG must be set When the transmitter shift register is empty the contents of UXTXBUF are shifted to the transmit shift register and the TXWake value is shifted to WUT 2 Set bit WUT which suppresses the start data and parity bits and transmits an idle period of exactly 11 bits as shown in Figure 13 10 The next data word shifted out of the serial port after the address character identifying idle period is the second word written to the UxTXBUF after the TXWake bit has been set The first data word written is suppressed while the address identifier is sent out and ignored thereafter Writing the first don t care word to UxTXBUF is necessary to shift the TXWAKE bit to WUT and generate an idle line condition Figure 13 10 USART Transmitter Idle Generation Example Bi M 11 Bit Idle Period Mark XXXX SP ST XXXXXXX Space Example Two Stop Bits 11 Bit Idle Period Mark XXXX SP SP sT XXXXXXX Space SP Stop Bit ST Start Bit 13 3 5 Address Bit Multiprocessor Format In the address bit multiprocessor format shown in Figure 13 11 characters
328. imer A Registers Word Access A 15 Timer A Registers Word Access Bit 4 017Eh 017Ch 017Ah 0178h Cap com register CCR2 0176h Cap com register CCR1 0174h Cap com register CCRO 0172h Timer A register TAR 0170h 016Eh 016Ch 016Ah 0168h Cap com control CCTL2 0166h Cap com control CCTL1 0164h Cap com control CCTLO 0162h Timer A control 0160h Bit 017Eh 017Ch 017Ah 0178h Cap com register CCR2 0176h Cap com register CCR1 0174h Cap com register CCRO 0172h Timer A register TAR 0170h 016Eh 016Ch 016Ah 0168h Cap com control CCTL2 0166h Cap com control CCTL1 0164h Cap com control CCTLO 0162h Timer A control 0160h A 14 215 214 213 212 211 210 29 28 215 214 213 212 211 210 29 28 215 214 213 212 211 210 29 28 215 214 213 212 211 210 29 28 CM 1 CM20 CCIS21 CCIS20 SCS2 SCCI2 Unused CAP2 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ro rw 0 CM11 CM10 CCIS11 CCIS10 SCS1 SCCH Unused CAP1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ro rw 0 1 CM00 CCISO1 CCIS00 SCSO sccio Unused CAPO rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ro rw 0 Unused Unused Unused Unused Unused SSEL2 SSEL1 SSELO rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 4 p ue ee p d ld Ecc S f 2 FRE REF 5 RENE rw FRE RENE rw Aa TATA rw psp __ S ee REC rw rw rw 2 22 w 0
329. iming for common and segment lines The frequency f cp of signal is generated from ACLK Using a 32 768 Hz crystal the fj cp frequency can be 1024 Hz 512 Hz 256 Hz or 128 Hz Bits FRFQ1 and FRFQO allow the correct selection of frame frequency The proper frequency fj cp depends on the LCD s requirement for framing frequency and LCD multiplex rate and is calculated by fL cp 2 x MUX rate x fFraming A 3 MUX example follows LCD data sheet fFraming 100 Hz 30 Hz FRFQ 6 fFraming 6 x 100 Hz 600 Hz 6 x 30 Hz 180 Hz Select f cp 1024 Hz 512 Hz 256 Hz or 128 Hz fL cp 32 768 128 256 Hz FRFQ1 1 FRFQ0 0 16 8 LCD Controller Driver 16 2 3 LCD Voltage Generation The voltages required for the LCD signals are supplied externally and are applied to pins R33 R23 R13 and R03 see Figure 16 6 Generally the voltages are generated with an equal weighted resistor ladder Note that pins R33 and are not present on all MSP430 devices Check the datasheet for the presence of these pins When pins R33 and R03 are not preset voltage V1 is tied to Vcc and voltage V5 is tied to Vgs internally When these pins are present they provide two advantages to the user First R33 is a switched Voc output This allows the power to the resistor ladder to be turned off reducing current consumption Also when these pins are present RO3 is tied internally to Vss This allows the user to control the offset o
330. ination address must not be within the range EDE to EDE 0FEh Example MOV EDE R6 MOV 510 R10 L 1 MOV R6 TONI EDE 2 R6 DECD R10 JNZ L 1 Memory at location LEO is decremented by two DECD B LEO Decrement MEM LEO Decrement status byte STATUS by two DECD B STATUS Instruction Set Description B 27 Instruction Set Overview DINT Syntax Operation Emulation Description Status Bits Mode Bits Example B 28 Disable general interrupts DINT 0 GIE or OFFF7h AND SR SR NOT src AND dst dst BIC 8 5 All interrupts are disabled The constant 08h is inverted and logically ANDed with the status register SR The result is placed into the SR N Not affected Z Not affected C Not affected V Not affected GIE is reset OscOff and CPUOff are not affected The general interrupt enable GIE bit in the status register is cleared to allow a nondisrupted move of a 32 bit counter This ensures that the counter is not modified during the move by any interrupt DINT All interrupt events using the GIE bit are disabled NOP MOV COUNTHI R5 Copy counter MOV COUNTLO R6 EINT All interrupt events using the GIE bit are enabled Ss Note Disable Interrupt If any code sequence needs to be protected from interruption the DINT should be executed at least one instruction before the beginning of the uninterruptible sequence or should be followed by an NOP ee
331. ine Synchronization to the data stream is handled by the software protocol in three pin SPI mode LLLLLL 3 14 4 1 3 Receive Transmit Enable Bit MSP430 as Slave Four Pin Mode 14 10 In the four pin mode shown in Figure 14 9 the external SPI receive control signal applied to pin STE stops a started receive operation A PUC signal a software reset SWRST or a receive transmit enable USPIIE can stop a receive operation and reset the operation control state machine Whenever the STE signal is set to high the receive operation is halted Interrupt and Control Functions Figure 14 9 State Diagram of Receive Enable MSP430 as Slave Four Pin Mode No Clock at UCLK USPIIE 0 Not Completed USPIIE 1 USPIIE 1 ana STEA Idle State PIIE 1 Receiver Receive US Handle Interrupt Disabl Receive Collects Conditions SEP Enabled External Clock Character Present Character Received USPIIE 1 PUC USPIIE 0 14 4 2 USART Receive Transmit Enable Bit Transmit Operation The receive transmit enable bit USPIIE shown in Figures 14 10 and 14 11 enables or disables the shifting of a character on the serial data line If this bit is reset the transmitter is disabled but any active transmission does not halt until all data previously written to the transmit buffer is tran
332. ines and all of the registers required to control and configure them Each I O line is capable of being controlled independently In addition each I O line is capable of producing an interrupt Separate vectors are allocated to ports P1 and P2 modules The pins for port P1 1 0 7 source one interrupt and the pins for port P2 P2 0 7 source another interrupt Seven registers are used to control the port pins see Section 8 2 1 Ports P1 and P2 are connected to the processor core through the 8 bit MDB and the MAB They should be accessed using byte instructions in the absolute address mode Figure 8 1 Port P1 Port P2 Configuration MDB 1 020h n 2 028h n 1 021h Direction Register 2 029 PnDIR n 1 022h n 2 02Ah 1 0231 Interrupt Edge Select n 2 02Bh PnIES Interrupt Enable PnIE R W Function Select PnSEL n 1 026h n 2 02 MSB LSB Pn 7 0 Digital I O Configuration 8 3 Ports P1 P2 8 2 1 Port P1 Port P2 Control Registers The seven control registers give maximum digital input output configuration flexibility All individual I O bits are independently programmable Lj Any combination of input output and interrupt condition is possible Interrupt processing of external events is fully implemented for all eight bits of ports P1 and P2 The seven registers for port P1 and the seven registers for port P2 are shown in Table 8 1 and Table 8 2 re
333. ints to the word following the instruction and moves the contents to the destination Valid only for a source operand MOV 456 Address Register Space Po OFF16h 01192h 01234h 010A8h fter OFF18h OFF16h OFF14h OFF12h 010AAh 010A8h 010A6h Address Space Oxxxxh PC 16 Bit CPU Register 5 13 Addressing Modes 5 2 8 Clock Cycles Length of Instruction The operating speed of the CPU depends on the instruction format and addressing modes The number of clock cycles refers to the MCLK 5 2 8 1 Format l Double Operand Instructions Table 5 12 describes the CPU format l instructions and addressing modes Table 5 12 Instruction Format and Addressing Modes Address Mode As 00 Rn 00 Rn 01 x Rn 01 EDE 01 amp EDE 01 x Rn 01 EDE 01 amp EDE 10 Rn 10 Rn 11 11 N 11 11 N 11 11 N Ad 0 Rm 0 PC 1 x Rm 1 EDE 1 amp EDE 0 Rm 1 x Rm 1 TONI 1 amp TONI 0 Rm 1 x Rm 1 EDE 1 amp EDE 0 Rm 0 PC 0 Rm 0 PC 1 x Rm 1 EDE 1 amp EDE No of Cycles 1 2 or ro W IO Length of Instruction MOV BR ADD XOR MOV MOV AND MOV ADD CMP MOV ADD AND XOR MOV XOR ADD BR MOV BR MOV ADD MOV ADD lt lt Example R5 R8 R9 R5 3 R6 R8 EDE R5 amp EDE 2 R5 R7 ED
334. inuous mode is used if the timer period of clock cycles is used for the application A typical application of the continuous mode is to generate multiple independent timings In continuous mode the capture compare block 0 works in the same way as the other capture compare blocks The capture compare blocks and different output modes of each output unit are useful to capture timer data based on external events or to generate various different types of output signals Examples of the different output modes used with timer continuous mode are shown in Figure 12 25 In continuous mode the timer starts counting from its present value The counter counts up to and restarts by counting from zero as shown in Figure 12 9 The maximum value of TBR TBR may in continuous mode is OFFFFh for 16 bit configuration OOFFFh for 12 bit configuration 003FFh for 10 bit configuration OOOFFh for 8 bit configuration Figure 12 9 Timer Continuous Mode 12 10 Timer Modes The TBIFG flag is set when the timer counts from to zero The interrupt flag is set independently of the corresponding interrupt enable bit as shown in Figure 12 10 An interrupt is requested if the corresponding interrupt enable bit and the GIE bit are set Figure 12 10 Continuous Mode Flag Setting Timer Clock Timer TBR max 1 Set Interrupt Flag TBIFG 12 3 3 1 Timer Use of the Continuous Mode The
335. ion when the new period is transferred from TBCCRO to TBCLO the conditions in the up down mode are identical to Timer B 12 13 Timer Modes those in the up mode See section 12 3 2 1 for details However if the timer is counting in the down direction when TBCLO is updated it continues its descent until it reaches zero The new period takes effect only after the counter finishes counting down to zero See Figure 12 16 Note If TBCLO gt TBR may the counter operates as if it were configured for continuous mode It will not count down from to zero Figure 12 16 Altering TBCLO Timer in Up Down Mode Timer Register 5 4 Tin ES Ho UU LLL Hl lil Il 0j 1 2 3 4 5 4 3 2 1 0 1 2 3 4 3 2 1 0 1 2 3 21 01 2 10 1 2 3 4 5 4 312111012 1 TBCLO 2 12 14 Timer Modes 12 4 Capture Compare Blocks Seven identical capture compare blocks shown in Figure 12 17 provide flexible control for real time processing Any one of the blocks may be used to capture the timer data at an applied event or to generate time intervals Each time a capture occurs or a time interval is completed interrupts can be generated from the applicable capture compare register The mode bit CAPx in control word TBCCTLx selects the compare or capture operation and the capture mode bits CCMx1 and CCMXxO in control word TBCCTLx define the con
336. irect address BR amp EXEC Branch to the address contained in absolute address EXEC Core instruction MOV X 0 PC Indirect address BR R5 Branch to the address contained in R5 Core instruction MOV R5 PC Indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 and increment pointer R5 afterwards The next time S W flow uses R5 pointer it can alter program execution due to access to next address in a table pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 with autoincrement BR X R5 Branch to the address contained in the address pointed to by R5 X e g table with address starting at X X can be an address or a label Core instruction MOV X R5 PC Indirect indirect R5 X CALL Syntax Operation Description Status Bits Example Instruction Set Overview Subroutine CALL dst dst tmp dst is evaluated and stored SP 2 SP PC SP PC updated to TOS tmp PC dst saved to PC A subroutine call is made to an address anywhere in the 64K address space All addressing modes can be used The return address the address of the following instruction is stored on the stack The call instruction is a word instruction Status bits are not affected Examples for all addressing modes are given CA
337. is important to disable the buffer for any I O pin that is not being actively driven if current consumption is critical see Figure 15 6 Comparator_A 15 9 15 10 Comparator A Applications With Applied Analog Signals Figure 15 6 Application Example With One Active Driving R3 and Three Passive Pins Control1 0 4 gt vs CAPD x 0 Control2 0 Ya CAPD x 0 Control3 1 1 lt Pr Ya gt CAPD x 0 or 1 Control4 0 4 gt Ya CAPD x 1 The specific implementation which digital inputs outputs can be controlled by CAPD x varies with each MSP430 device configuration Refer to the specific device s data sheet to see which I O port is associated with Comparator A Comparator A Applications 15 4 2 Comparator A Used to Measure Resistive Elements The Comparator_A can be used to measure resistive elements For example temperature can be converted into digital data via a thermistor by comparing the thermistor s discharge time to that of a reference resistor See Figure 15 7 Figure 15 7 Temperature Measurement Systems VCC VCC OV Vcc R f 2 TUE CAON e g R us A CAF Capture meas 0 Input of e 1 0 r limer A Ki L 1 i a ns P2CA1 ccn 2 5 OV Vcc 6 0 1 2 CARSEL __1 VCAREF 1 e 0 25x Vcc The
338. ister e n 11 29 UART Implementation RR or YR ee ata Ree RERO Y eee ERR RR E 11 33 xiii Contents 11 34 12 1 12 2 12 3 12 4 12 5 12 6 12 7 12 8 12 9 12 10 12 11 12 12 12 13 12 14 12 15 12 16 12 17 12 18 12 19 12 20 12 21 12 22 12 23 12 24 12 25 12 26 12 27 12 28 12 29 12 30 12 31 12 32 13 1 13 2 13 3 13 4 13 5 13 6 13 7 13 8 13 9 13 10 13 11 13 12 13 13 13 14 13 15 13 16 13 17 xiv Timer A VART Timing teen eee 11 34 Timer B Block Diagram obrone enr ra eee nn nnn 12 4 Mode Coritrol 12 5 Schematic of 16 Bit Timer n 12 6 Schematic of Clock Source Select and Input Divider 12 7 Timer Up Mode ure dre x vitet bentes 12 8 Up Mode Flag Setting Rr 12 8 New Period gt Old Period n 12 9 New Period lt Old Period nh 12 10 Timer Continuous 12 10 Continuous Mode Flag Setting 12 11 Output Unit in Continuous Mode for Time Intervals 12 11 Timer Up Down Mode 12 12 Output Unit in Up Down Il
339. ith Vp at AVss Conversion result to be stored in conversion memory register ADC12MEM1 This means that control bit CStartAdd in ADC12CTLO is assigned a value of 1 The channel INCH 4 and reference voltages Sref 0 are selected via ADC12MCTL1 ADC12 17 11 Conversion Modes Figure 17 6 Example Conversion Memory Setup 140h 2 x CStartAdd c 0142h 0 conversion result i 5 Select VR VR cz 0 0140h ADC12MEMO ADC12MCTLO 080h Oh CStartAdd 100 on ADC12MEM2 ADC12MCTL2 16 x 12 bit 16 x 8 bit ADC Memory ADC Memory Controls 015Ch ADC12MEM14 ADC12MCTL14 O8Eh 015Eh ADC12MEM15 ADC12MCTL15 O8Fh 17 5 2 Sequence of Channels Mode 17 12 The sequence of channels mode converts a sequence of channels The CStartAdd bits in ADC12CTL1 point to the first conversion memory register used for the sequence The results of the remaining conversions in the sequence are stored in sequential conversion memory registers For example if a sequence is three conversions long and the CStartAdd bits point to conversion memory register 4 then when the sequence is started the first conversion result is stored in ADC12MEM4 the second result is stored in ADC12MEMS5S and the third result is stored in ADC12MEM6O When performing sequences of conversions the channels and references for each conversion are individually configurable via the conversion memory control register assoc
340. itialization The SVS can be configured to generate a POR signal when a fault is detected or to only set a bit in the control register The PORON bit the SVSCTL regis ter determines this function The minimum supply voltage required to generate a reliable POR when Voc glitches or dips depends on the pulse width of the voltage drop Generally if the width of the voltage drop is small a deeper voltage drop is required to trigger a POR signal See the device data sheet for electrical parameters The VLD bits control the on off state of the supply voltage supervisor SVS circuitry The SVS function is off if VLD 0 and on if VLD 1 Bit PORON enables or disables the automatic reset of MSP430 upon a low voltage situation If PORON 1 a low voltage situation generates a POR signal and resets the MSP430 Bit SVSOP is used to watch the actual SVS comparator output Bit SVSFG is set if a low voltage situation is detected remains set until the low voltage situation is removed and then it is reset by software SVSFG latches such events whereas SVSOP represents the actual output of the comparator oF Note Whenever the supply voltage conditions trigger a POR from the brownout the SVS is disabled and must be reenabled by software Figure 3 4 Operating Levels for SVS and Brownout Reset Circuit _ Software sets VLD gt 0 SVS is active Voc vvs 17 ae IT V SVS IT VB IT
341. its responsible for the addressing mode used for the destination dst D reg The working register used for the destination dst B W Byte or word operation 0 word operation 1 byte operation gt SS X ee eee Note Destination Address Destination addresses are valid anywhere in the memory map However when using an instruction that modifies the contents of the destination the user must ensure the destination address is writeable For example a masked ROM location would be a valid destination address but the contents are not modifiable so the results of the instruction would be lost Cd 5 16 Instruction Set Overview 5 3 1 Double Operand Format 1 Instructions Figure 5 7 illustrates the double operand instruction format Figure 5 7 Double Operand Instruction Format 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 As Table 5 15 describes the effects of an instruction double operand instruction status bits See section 5 2 8 for information on number of code words and execution cycles per instruction Table 5 17 Double Operand Instruction Format Results Mnemonic S Reg D Reg Operation Status Bits V N 2 MOV src dst Src gt dst B ADD src dst src dst gt dst d ADDC src dst src dst C dst E i SUB src dst dst not src 1 dst ii B SUBC src dst dst not src C gt dst CMP src dst dst src src dst src dst C dst dec n
342. ix patterns see Figure 7 5 The 5 bits for the modulator are contained in SCFI1 and SCFIO SCFI1 2 SCFI1 0 SCFIO 1 and SCFIO 0 Figure 7 5 Modulator Hop Patterns NpCOmod Lower DCO Tap Frequency fn Upper DCO Tap Frequency fn 1 f DCOCLK Cycles Shown for f DCOCLK f ACLK x 32 One ACLK Cycle 7 3 3 DCO Frequency Range The fundamental frequency range of the DCO is centered based on fnominal approximately equal to 2 MHz using bits FN x SCFIO see Table 7 1 The range control allows the DCO to operate near the center of the available taps for a given MCLK SMCLK The initial MCLK SMCLK frequency is typically 1 MHz similar to the FLL in 3xx devices 7 8 Digitally Controlled Oscillator and Frequency Locked Loop Table 7 1 The DCO Range Control Bits FC rs rs AVE feos FREQUENCY o 0 9 ee xe E 1 The user must ensure the resulting MCLK frequency does not violate the operating conditions in the device data sheet 7 3 4 Disabling the FLL loop control and modulation can be disabled independently loop control can be disabled by setting the SCGO bit in the status register SR In this case the DCO runs at the previous tap open loop Then the MCLK SMCLK is not automatically stabilized to D x N 1 x DCO is set or 1 x ACLK DCO is reset The influence ofthe modulator can be disabled by setting
343. kes the MSP430 and the system returns to active mode supporting the USART transfer Figure 13 23 Receive Start Conditions SYNC Valid Start Bit d URXS Receiver Collects Character URXSE e From URXD CA UU ETAT Request_ BRK Interrupt_Service LIII E URXWIE _ RXWake e SWRST PUC UxRXBUF Read J URXSE IRQA Three character streams do not set the interrupt flag URXIFG Erroneous characters URXEIE 0 L Address characters URXWIE 1 Invalid start bit detection The interrupt software should handle these conditions USART Peripheral Interface UART Mode 13 23 Utilizing Features of Low Power Modes 13 6 1 1 Start Conditions The URXD signal feeds into the USART module by first going into a deglitch circuit Glitches cannot trigger the receive start condition flag URXS which prevents the module from being started from small glitches on the URXD line Because glitches do not start the system or the USART module current consumption is reduced in noisy environments Figure 13 24 shows the accepted receive start timing condition Figure 13 24 Receive Start Timing Using URXS Flag Start Bit Accepted Majority Vote RC S URXS gt 1 URXS is Reset in the Interrupt Handler Using Control Bit URXSE The UART stops receiving a character when the URX
344. l Registers C 13 C 4 Flash Memory Interrupt and Security Key Violation C 18 C 5 Flash Memory Access via JTAG and Software 22 C 1 Flash Memory Organization C 1 Flash Memory Organization The flash memory may have one or more modules of different sizes as shown in Figure C 1 A module is a physical memory unit that operates independent from other modules In an MSP430 configuration with more than one flash memory module all modules are located in one linear address range Figure C 1 Interconnection of Flash Memory Module s p UENIT TUR ke M es E SEL US e A S 1 ROM RAM TDI 4 TDO TDI 16 Bit E YN gt CPU Test To Other Incl 16 Reg JTAG Peripheral Modules gt MDB 16 Bit TMS TCK E Flash Flash Test VPP p Optional Module 1 Module 2 bo ee E Independent modules such as Module1 and Module2 are intended to execute software code from one module while simultaneously programming or erasing another module LR _ Note Flash Memory Module s MSP430 Devices Different devices may have on
345. le Conversion Sample and convert channel using ADC12MCTLx and store conversion result in ADC12MEMx EOS in ADC12MCTLx 1 Yes Stop conversion sequence ADC12 17 15 Conversion Modes Figure 17 10 Sequence of Channels Mode Example 140h 2 x CStartAdd gt 0180h Conversjon result 1 M 0182h Conversion result 1 os 0 cowespnrsut gt ose 0 conversjonresutt Sequence 0140h ADC12MEMO ADC12MCTLO 080h 0142h ADC12MEM1 ADC12MCTL1 08th 0144h ADC12MEM2 ADC12MCTL2 082h 0146h ADC12MEM3 ADC12MCTL3 083h 0148h ADC12MEM4 ADC12MCTL4 084h 014Ah ADC12MEM5 ADC12MCTL5 085 gt 0 T i gt on 0 conversion resur h E select Vng Vn Multiplexer EE 0158h ADC12MEM12 ADC12MCTL12 08Ch 015Ah ADC12MEM13 ADC12MCTL13 08Dh 015Ch ADC12MEM14 ADC12MCTL14 08Eh 015Eh ADC12MEM15 ADC12MCTL15 08Fh 17 5 3 Repeat Single Channel Mode 17 16 The repeat single channel mode is identical to the single channel mode ex cept that conversions are repeated on the chosen channel until stopped by Software Each time a conversion is completed the results are loaded into the appropriate ADC12MEMXx register and the corresponding interrupt flag ADC12IFG xis set to indicate completion of the conversion Additionally If the appropriate interrupt enable flags ar
346. le Mode Example Configuration 17 25 Pulse Sample Mode Example Timing 17 26 Conversion Timing for Extended Sample Mode 17 26 Extended Sample Mode Example 17 27 Extended Sample Mode Example Timing 17 27 Use of MSC Bit With Nonrepeated Modes 17 28 Use of MSC Bit With Repeated Modes 17 28 Equivalent Circuit ir cba adios Ghee Peds Bie ede a dea Relea 17 29 A D Grounding and Noise Considerations 17 41 Double Operand Instructions B 4 Single Operand Instructions eee e B 5 Conditional and Unconditional Jump Instructions B 5 Decrement Overlap nent eens B 26 Main Program Interrupt cece nett eee B 46 ie U W vv ON 0 o RO oopoopoooo 0 Destination Operand Arithmetic Shift Left B 47 Destination Operand Carry Left Shift B 48 Destination Operand Arithmetic Right Shift 49 Destination
347. lected using IPO to IP2 located in the Basic Timer1 control register BTCTL It selects one of the eight bits of BTCNT2 as the source signal to set the Basic Timer1 interrupt flag BTIFG The value of the counter bits can be read as well as written Figure 10 5 Basic Timer Counter BTCNT2 7 0 2 rw rw rw rw rw rw rw rw 10 1 2 Special Function Register Bits Two SFR bits pertain to the Basic Timer1 Interrupt Basic Timer1 interrupt flag BTIFG located in IFG2 7 Basic Timer interrupt enable BTIE located in IE2 7 The BTIFG flag indicates that a Basic Timer1 interrupt is pending and is reset automatically when the interrupt is accepted The BTIE bit enables or disables the interrupt from the Basic Timer1 and is reset with a The Basic Timer1 interrupt is also enabled or disabled with the general interrupt enable bit GIE 10 1 3 Basic Timer1 Operation The Basic Timer1 is constantly incremented by the selected clock source The hold bit inhibits all functions of the module and reduces power consumption The Basic Timer1 registers may be accessed at any time regardless of the state of the hold bit An interrupt can be used to control system operation The interrupt is a single source interrupt The basic timer can operate in two different modes Two independent 8 Bit Timer Counters One 16 bit timer counter Basic Timer1 10 5 Basic Timer1 10 1 3 1 8 Bit Counter Mode In the 8
348. led Transmit Disable USPIIE 1 Transmission Active Handle Interrupt Conditions External Clock Present Character USPIIE 1 Transmitted PUC USPIIE 0 When USPIIE is reset any data can be written regularly into the transmit buffer but no transmission is started Once the USPIIE bit is set the data in the transmit buffer are immediately loaded into the transmit shift register and character transmission is started Note Writing to UXTXBUF SPI Mode Data should never be written to transmit buffer UXTXBUF when the buffer is not ready UTXIFG 0 and the transmitter is enabled USPIIE is set Otherwise the transmission may have errors M A A Note Writing to UXTXBUF Reset of Transmitter SPI Mode Disabling of the transmitter should be done only if all data to be transmitted have been moved to the transmit shift register Data is moved from UTXBUF to the transmit shift register on the next bit clock after the shift register is ready MOV B 14 amp U0TXBUF BIC B USPIEO amp ME2 If BITCLK lt SMCLK then the transmitter might be stopped before the buffer is loaded into the transmitter shift register Interrupt and Control Functions 14 4 3 USART Receive Interrupt Operation In the receive interrupt operation shown in Figure 14
349. lizing Features of Low Power Modes 13 23 13 6 1 Receive Start Operation From UART Frame 13 23 13 6 2 Maximum Utilization of Clock Frequency vs Baud Rate UART Mode 13 25 13 6 3 Support of Multiprocessor Modes for Reduced Use of MSP430 Resources sssssssssesses nen 13 26 13 7 Baud Rate Considerations 13 26 13 7 1 Bit Timing in Transmit Operation 13 27 13 7 2 Typical Baud Rates and Errors 13 29 13 7 3 Synchronization 13 30 14 USART Peripheral Interface SPI Mode 14 1 14 1 USART Peripheral Interface 14 2 14 2 USART Peripheral Interface SPI Mode 14 3 14 2 1 SPI Mode Features 14 3 14 3 Synchronous Operation en 14 4 14 31 Master SPI Mode 14 7 14 3 2 Slave SPI Mode 0 ete ene eens 14 8 14 4 Interrupt and Control Functions eee eens 14 9 14 4 1 USART Receive Transmit Enable Bit Receive Operation 14 9 14 4 2 USART Receive Transmit Enable Bit Transmit Operation 14 11 14 4 3 USART Receive Interrupt Operatio
350. llator enters off mode all activities cease however the RAM contents the port and the registers are maintained Wake up is possible only through enabled external interrupts when the GIE bit is set and from the NMI CPU Off If set the CPU enters off mode program execution stops However the RAM the port registers and especially the enabled peripherals for example basic timer UART etc stay active Wake up is possible through all enabled interrupts GIE If set all enabled maskable interrupts are handled If reset all maskable interrupts are disabled The GIE bit is cleared by interrupts and restored by the RETI instruction as well as by other appropriate instructions N Set if the result of an operation is negative Word operation Negative bit is set to the value of bit 15 of the result Byte operation Negative bit is set to the value of bit 7 of the result Z Set if the result of byte or word operation is 0 cleared if the result is not 0 C Setifthe result of an operation produced a carry cleared if no carry occurred Some instructions modify the carry bit using the inverted zero bits 5 4 CPU Registers V7 1 Note Status Register Bits V N Z and C The status register bits V N Z and C are modified only with the appropriate instruction For additional information see the detailed description of the instruction set in Appendix B
351. lly so that program execution continues with the next instruction Comment Valid for source and destination Example MOV EDE TONI Source address EDE OF016h dest address TONI 01114h Before After Address Register Address Register Space Space Oxxxxh PC OFF16h 011FEh OFF16h 011FEh OFF14h OF102h OFF14h OF102h OFF12h 04090h PC OFF12h 04090h OFF14h OF018h 0F102h OF018h oFo16h OA123h OF016h gEo16h OA123h OFF16h 1 01114h 01234h 21 01114h 0A123h 16 Bit CPU 5 9 Addressing Modes 5 2 4 Absolute Mode The absolute mode is described in Table 5 8 Table 5 8 Absolute Mode Description Assembler Code Content of ROM MOV amp EDE amp TONI MOV 0 0 X EDE Y Length Operation Comment Example Before OFF16h OFF14h OFF12h OF018h OF016h OF014h 01116h 01114h 01112h Two or three words Move the contents of the source address EDE to the destination address TONI The words after the instruction contain the absolute address of the source and destination addresses With absolute mode the PC is incremented automatically so that program execution continues with the next instruction Valid for source and destination MOV amp EDE amp TONI Source address SEDE 020165 dest address TONI 01114h After Address Register Address Register Space Space Oxxxxh PC 01114h OFF16h 01114h OF016h O
352. mediately after the sequence begins the ADC120N and REFON bits can then be reset before the sequence completes If this occurs the ADC12 will be powered down immediately and the conversion results will be false Conversion Clock and Conversion Speed Caution The following must be considered when turning the ADC12 and voltage reference on or off ADC12 turnon time when the ADC12 is turned on with the ADC120N bit the turnon time noted in the data sheet tApc120N must be observed before a conversion is started Otherwise the results will be false Reference voltage settling Time When the built in reference is turned on with the VREFON bit the settling timing noted in the data sheet must be observed before a conversion is started Otherwise the results will be false until the reference settles Once all internal and external references have settled no additional settling time is required when selecting or changing the conversion range for each channel Settling time of external signals external signals must be settled before performing the first conversion after turning on the ADC12 Otherwise the conversion results will be false 17 6 Conversion Clock and Conversion Speed The conversion clock for the ADC12 ADC12CLK shown in Figure 17 13 can be selected from several sources and can be divided by any factor from 1 8 The ADC12CLK is used for the A D conversion and to generate the sampling period if pulse sampling mode is
353. memory 19 S39C3 S39C2 S39C1 39 0 S38C3 S38C2 S38C1 S38C0 0A4h rw rw rw rw rw rw rw rw LCD memory 18 S37C3 37C2 S37C1 37C0 S36C3 S36C2 S36C1 S36C0 OA3h rw rw rw rw rw rw rw rw LCD memory 18 S35C3 S35C2 S35C1 35 0 S34C3 S34C2 S34C1 S34C0 0A2h rw rw rw rw rw rw rw rw LCD memory 17 S33C3 33C2 S33C1 33C0 S32C3 S32C2 S32C1 S32C0 OA1h rw rw rw rw rw rw rw rw LCD memory 16 S31C3 S31C2 S31C1 31C0 S30C3 S30C2 S30C1 S30C0 OAOh rw rw rw rw rw rw rw rw LCD memory 15 S29C3 S29C2 S29C1 29 0 S28C3 S28C2 S28C1 S28C0 O9Fh rw rw rw rw rw rw rw rw LCD memory 14 S27C3 S27C2 S27C1 27C0 S26C3 S26C2 S26C1 S26C0 009Eh rw rw rw rw rw rw rw rw LCD memory 13 S25C3 S25C2 S25C1 25 0 S24C3 S24C2 S24C1 S24C0 rw rw rw rw LCD memory 9 099h LCD memory 8 09Dh rw rw rw rw LCD memory 12 S23C3 S23C2 S23C1 23C0 S22C3 S22C2 S22C1 S22C0 09Ch rw rw rw rw n rw rw rw LCD memory 11 S21C3 21C2 S21C1 21C0 S20C3 S20C2 S20C1 S20C0 09Bh rw rw rw rw n r rw rw LCD memory 10 S19C3 19C2 19C1 19C0 18C3 18C2 18C1 1800 09Ah n r rw rw w w r w w r S1503 S1502 15C1 15 0 51463 51462 S14C1 14C0 098h r n n n n r rw rw LCD memory 7 S13C3 S13C2 13C1 13C0 12C3 12C2 12C1 12C0 097h rw rw rw rw n r rw rw LCD memory 6 S11C3 11 2 S11C1 11 0 S10C3 S10C2 S10C1 S10CO0 096h rw rw rw rw rw rw rw rw LCD memory 5 S9C3 S9C2 S9C1 S9CO S8C3 S8C2 S8C1 S8C0 095h rw rw rw rw rw rw rw rw LCD memory 4 S7C3
354. ming 100 Hz 30 Hz FRFQ 6 fFraming fi cp 6x 100 Hz 600 Hz 6x30 Hz 180 Hz Select f cp 1024 Hz 512 Hz 256 Hz or 128 Hz fL cp 32 768 128 256 Hz FRFQ1 1 FRFQ0 0 Seethe Liquid Crystal Display Drive chapter for more details on the LCD driver Chapter 11 Timer A This chapter describes the basic functions of the MSP430 general purpose 16 bit Timer A The implementation of Timer A differs between MSP430 devices Always check the device s data sheet to determine the connections and the number of identical capture compare registers Also the data sheets use additional nomenclature to indicate the number of capture compare registers implemented on a specific device For example if Timer A3 is discussed in a data sheet then that device s implementation of Timer A contains three capture compare registers All capture compare blocks CCR are identical p 1l Note Throughout this chapter the word countis used in the text As used in these instances it refers to the literal act of counting It means that the counter must be in the process of counting for the action to take place If a particular value is directly written to the counter then the associated action will nottake place For example the CCRO interrupt flag is set when the timer counts up tothe value in CCRO The counter must countfrom CCRO 1 to CCRO If the CCRO value were simply written directly to the timer with software the interrupt flag
355. mpleted This ensures that each transition is acknowledged by the software 8 2 1 7 Function Select Registers P1SEL P2SEL 8 6 P1 and P2 port pins are often multiplexed with other peripheral modules to reduce overall pin count on MSP430 devices see the specific device data sheet to determine which other peripherals also use the device pins Control registers P1SEL and P2SEL are used to select the desired pin function l O port or other peripheral module Each register contains eight bits corresponding to each pin and each pin s function is individually selectable All bits in these registers are reset by the signal The bit definitions are Bit 0 Port P1 or P2 function is selected for the pin Bit 1 Other peripheral module function is selected for the pin Ports P1 P2 Note Function Select With P1SEL P2SEL The interrupt edge select circuitry is disabled if control bit PnSEL x is set Therefore the input signal can no longer generate an interrupt LLLLLSSSS A A AO OA When a port pin is selected to be used as an input to a peripheral module other than the I O port PNSEL x 1 the actual input signal to the peripheral module is a latched representation of the signal at the device pin see Figure 8 2 schematic The latch uses the PnSEL x bit as its enable so
356. multaneously when TBCL4 TBCL5 TBCL6 updated simultaneously when or to TBCLO TBR counts to 0 or to TBCLO TBR counts to 0 or to TBCLO TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBCLO TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 TBCLO TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 Loaded immediately when the corresponding register is loaded TBCLO TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 updated simultaneously when TBR counts to 0 TBCLO TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 updated simultaneously when TBR counts to 0 TBCLO TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 updated simultaneously when TBR counts to 0 or to TBCLO TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBR counts to TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 t Timer B3 has only three CCR blocks No triple group is possible with 3 CCR s If TBCLGRP 2 then it is treated as TBCLGRP 1 t Timer B3 has only three CCR blocks TBCCRO TBCCR1 and TBCCR2 are one group TBCLGRP 3 CLLDx 0 1 2 Notes 1 Whenusing groups load mode for the group is selected with the CLLDx bits of the lowest numbered TBCCTLx register in the group except when TBCLGRP 3 For example when grouped by 2 the CLLDx bits of TBCCTL3 determine the load mode for TBCL3 and TBCL4 When grouped by 3 the bits of TBCCTL4 determine the load mode for TBCL4 TBCL5 and TBCL6 etc When TBCLGRP 3 the CLLDx bits from TBCTL1 are used
357. n 14 13 14 4 4 Transmit Interrupt Operation 14 14 14 5 Control and Status Registers 14 15 14 5 1 USART Control Register 14 16 14 5 2 Transmit Control Register UOTCTL UITCOTL 14 17 14 5 3 Receive Control Register UORCTL UIRCTL 14 18 14 5 4 Baud Rate Select and Modulation Control Registers 14 19 14 5 5 Receive Data Buffer UORXBUF U1RXBUF 14 19 14 5 6 Transmit Data Buffer UOTXBUF UTTXBUF 14 20 15 Comparator ele eet iacu seen ceu soe en e rom 15 1 15 1 Comparator A Overview ssssssssssssss e 15 2 15 2 Comparator A Descriptlon parades IDE ieee 15 3 15 2 1 Input Analog Switches 15 3 15 2 2 Input Multiplexer eens 15 3 15 23 The Comparato iw sete haces teretes ete eee eoe ded 15 3 15 2 4 The Output Filler 0 teens 15 3 15 2 5 The Voltage Reference Generator 15 4 15 2 6 Comparator A Interrupt Circuitry 15 5 15 3 Comparator_A Control Registers 15 5 15 3 1 Compara
358. n Set Description B 35 Instruction Set Overview JL Jump if less Syntax JL label Operation If N XOR V 1 then jump to label PC 2 x offset PC If N XOR V 2 0 then execute following instruction Description The status register negative bit N and overflow bit V are tested If only one is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If both N and V are set or reset the instruction following the jump is executed This allows comparison of signed integers Status Bits Status bits are not affected Example When the content of R6 is less than the memory pointed to by R7 the program continues at label EDE CMP R7 R6 lt R7 compare on signed numbers JL EDE Yes R6 lt R7 No proceed B 36 Operation Description Status Bits Hint Instruction Set Overview Jump unconditionally JMP label PC 2 x offset PC The 10 bit signed offset contained in the instruction LSBs is added to the program counter Status bits are not affected This one word instruction replaces the BRANCH instruction in the range of 511 to 512 words relative to the current program counter Instruction Set Description B 37 Instruction Set Overview JN Jump if negative Syntax JN label Operation if N 2 1 PC 2x offset PC if N 2 0 execute following instruction Description The negative bit N of the status register is
359. n Set Overview Add source and carry to destination Add source and carry to destination ADDC src dst or ADDC W src dst ADDC B src dst SIC dst C dst The source operand and the carry bit C are added to the destination operand The source operand is not affected The previous contents of the destination are lost N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Setif there is a carry from the MSB of the result reset otherwise V Setif an arithmetic overflow occurs otherwise reset OscOff CPUOff and GIE are not affected The 32 bit counter pointed to by R13 is added to a 32 bit counter eleven words 20 2 2 2 above the pointer in R13 ADD R13 20 R13 ADD LSDs with no carry in ADDC R13 20 R13 ADD MSDs with carry resulting from the LSDs The 24 bit counter pointed to by R13 is added to a 24 bit counter eleven words above the pointer in R13 ADD B R13 10 R13 ADD LSDs with no carry in ADDC B R13 10 R13 ADD medium Bits with carry ADDC B R13 10 R13 ADD MSDs with carry resulting from the LSDs Instruction Set Description 11 Instruction Set Overview AND W AND B Syntax Operation Description Status Bits Mode Bits Example Example Source AND destination Source AND destination AND src dst or AND W src dst AND B src dst src AND dst dst The source operand and the destination operand are logically ANDed The res
360. n period is completed no conversion executed or unreliable conversion result Sample and conversion SAMPCOM signal can be reset ENC is reset after conversion period is completed conversion is executed regularly Sample and conversion signal can be reset and conversion started when appropriate It ENC and conversion started when appropriate Operational Mode EN Conversion Period Sample Period Conversion Period Sample Period ENC is reset before conversion period is completed no conversion executed or unreliable conversion result Sample and conversion SAMPCOM signal can be reset and conversion started when appropriate ENC is reset after conversion period is completed conversion is executed regularly Sample and conversion SAMPCOM signal can be reset and conversion started when appropriate When the conversion is complete and the results are written to the selected conversion memory register the corresponding interrupt ADC12IFG x is set and if the appropriate interrupt enables are set an interrupt request is generated see the ADC12 Interrupt Vector Register ADC 12IV section When software is using the ADC10SC bit to initiate conversion successive conversions can be initiated by simply setting the ADC10
361. n the next bit clock after the transmit shift register is empty and UTXBUF is loaded qr UA Note Writing to UXTXBUF Writing data to the transmit data buffer must only be done if buffer UXTXBUF is empty otherwise an unpredictable character can be transmitted LLLLLLSSSS A A A A A N 13 22 Utilizing Features of Low Power Modes 13 6 Utilizing Features of Low Power Modes There are several functions or features of the USART that supportthe ultralow power architecture of the MSP430 These include Support system start up from any processor mode by sensing of UART frame start condition Usethe lowest input clock frequency for the required baud rate Support multiprocessor modes to reduce use of MSP430 resources 13 6 1 Receive Start Operation From UART Frame The most effective use of start detection in the receive path is achieved when the baud rate clock runs from SMCLK In this configuration the MSP430 can be put into a low power mode with SMCLK disabled The receive start condition is the negative edge from the signal on pin URXD Each time the negative edge triggers the interrupt flag URXS it requests a service when enable bits URXIE and GIE are set This wa
362. nd GIE are not affected Figure 10 Destination Operand Byte Swap Example Example 15 8 7 0 MOV 040BFh R7 0100000010111111 R7 SWPB R7 1011111101000000 R7 The value in R5 is multiplied by 256 The result is stored in R5 R4 SWPB R5 MOV R5 R4 the swapped value to R4 BIC 0FF00h R5 Correct the result BIC 800FFh R4 Correct the result SXT Syntax Operation Description Status Bits Mode Bits Instruction Set Overview Extend Sign SXT dst Bit 7 Bit 8 Bit 15 The sign ofthe low byte is extended into the high byte as Figure 11 N Setif result is negative reset if positive Z Setif result is zero reset otherwise C Setif result is not zero reset otherwise NOT Zero V Reset OscOff CPUOff and GIE are not affected Figure B 11 Destination Operand Sign Extension Example 15 8 7 0 R7 is loaded with the P1IN value The operation of the sign extend instruction expands bit 8 to bit 15 with the value of bit 7 R7 is then added to R6 MOV B amp P1IN R7 P1IN 080h 1000 0000 SXT R7 R7 OFF80h 1111 1111 1000 0000 ADD R7 R6 add value of EDE to 16 bit ACCU Instruction Set Description B 59 Instruction Set Overview TST W TST B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Test destination Test destination TST dst TST W dst TST B dst dst OFFFFh 1 ds
363. nd one interrupt vector are associated with the Comparator A see Figure 15 3 The interrupt flag CAIFG is set on either the rising or falling edge of the comparator output The interrupt edge select bit CAIES deter mines which edge of the output signal sets the CAIFG flag The interrupt enable bit CAIE along with the general interrupt enable bit GIE control if the CAIFG bit generates a CPU interrupt If both the CAIE and the GIE bits are set then the CAIFG flag will generate a CPU interrupt request The CAIFG flag is automatically reset when the CPU interrupt request is serviced The CAIFG CAIES and CAIE bits are all located in the CACTL1 register Figure 15 3 Comparator A Interrupt System POR IRACC Interrupt Request Accepted 15 3 Comparator A Control Registers The Comparator A module is configured with three module registers as shown in Table 15 1 The module registers are mapped into the lower peripheral file address range where all byte modules are located and should be accessed with byte instructions suffix B Table 15 1 Comparator A Control Registers Short Initial Register Form Register Type Address State C Acontrol register 1 CACTL1 Read write 059h Reset C Acontrol register 2 CACTL2 Read write 05Ah Reset C A port dissipation reg CAPD Read write 05Bh Reset Comparator A 15 5 Comparator A Control Registers 15 3 1 Comparator A Control Register CACTL1 15 6 The control register CACT
364. nd the data is written correctly The associated interrupt flag is reset 17 8 3 Control Registers ADC12MCTLx Each conversion memory register ADC12MEMXx has its own control register ADC12CTLx The conversion memory registers hold the conversion results and the control register for each conversion memory register selects basic conversion conditions such as selecting the analog channel the reference voltage sources for VR and Vp_ and indicating the end of a sequence All control bits in ADC12CTLx are reset during POR see Chapter 3 for POR details The control registers ADC12MCTL x can be modified only if the en able conversion control bit ENC is reset Any instruction that writes to an ADC12MCTL register while the ENC bit is set will have no effect ADC12 17 35 ADC12 Control Registers 7 ADC12MCTLx EOS 080h 08Fh rw 0 INCH bits 0 3 Sref bits4 6 EOS bit7 17 36 1 1 Sref source of reference INCH input channel a0 to a11 1 1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 The INCH input channel bits select one of eight external or one of four internal analog signals for conversion 0 7 a0toa7 8 VeREF 9 VnEr VenEr 10 Temperature diode 11 15 AVcc AVgs 2 Note Selecting channel 10 automatically turns on the on chip reference generator for a voltage source for the temperature diode However it does not enable the output or effect the reference selections for the conversion
365. nded sample mode is useful in applications that require an extended sampling period to accommodate different input source impedances or in applications where the maximum sampling period supplied by the internal sampling timer is insufficient An example of the extended sample mode configuration is shown in Figure 17 21 The selected input signal source is Timer B OUTO The timing for the example is shown in Figure 17 22 Figure 17 21 Sampling Extended Sample Mode Example Configuration Internal ADC12SSEL Oscillator ADC120N ADC12DIV ADC120SC Vg V ADG12CLK Divide by ACLK analog 1 2 3 4 5 6 7 8 MCLK Sample input p and 12 bit A D converter core SHTO SMCLK Hold SHTI signal SHP 9m Sampling ADC12SC _ SAMPCON Timer Timer A OUT1 lt Timer B OUTO SHI Timer B OUT1 12 bit SAR M9 Conversion CTL v Figure 17 22 Timer B OUTO Extended Sample Mode Example Timing ADC12CLK tsample tconvert t EFA a sync 17 7 4 Using the MSC Bit The multiple sample and conversion MSC control bit is not used if the sam ple signal SAMPCON is generated without the sampling timer However when the sampling timer is used to generate the SAMPCON signal andthe operating mode is other than single channel single conversion CONSEQ gt 0 the MSC
366. ndefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Initial State Undefined Undefined Undefined Undefined Undefined Undefined Reset Reset Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Comments Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Comments Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented USARTO receiver enable UART mode USARTO SPI enable SPI mode USARTO transmit enable UART mode Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented Interrupt Processing System Resets Interrupts and Operating Modes 3 17 Interrupt Processing Table 3 10 MSP430x44x Module Enable Registers 1 and 2 Bit Position ME1 0 ME1 1 ME1 2 ME1 3 ME1 4 ME1 5 ME1 6 ME1 7 ME2 0 ME2 1 ME2 2 ME2 3 ME2 4 ME2 5 ME2 6 ME2 7 3 18 Short Form URXEO USPIEO UTXEO URXE1 USPIEO UTXE1 Initial State Undefined Undefined Undefined Undefined Undefined Undefined Reset Reset Reset Undefined Undefined Undefined Undefi
367. ndexed Mode Description 5 8 Assembler Code Content of ROM MOV 2 R5 6 R6 MOV X R5 Y R6 X22 Y 6 Length Operation Comment Example Before OFF16h OFF14h OFF12h 01094h 01092h 01090h 01084h 01082h 01080h Address Space Two or three words Move the contents of the source address contents of R5 2 to the destination address contents of R6 6 The source and destination registers R5 and R6 are not affected In indexed mode the program counter is incremented automatically so that program execution continues with the next instruction Valid for source and destination MOV 2 R5 6 R6 After Register Address Register Space Oxxxxh PC 0108Ch 05555h 01092h o1092n o1234h 01080h Oxxxxh 0002h 01084h Oxxxxh en 01234h 01082h 01234h Addressing Modes 5 2 3 Symbolic Mode The symbolic mode is described in Table 5 7 Table 5 7 Symbolic Mode Description Assembler Code Content of ROM MOV EDE TONI MOV X PC Y PC X EDE PC Y TONI PC Length Two or three words Operation Move the contents of the source address EDE contents of PC X to the destination address contents of PC Y The words after the instruction contain the differences between the PC and the source or destination addresses The assembler computes and inserts offsets X and Y automatically With symbolic mode the program counter PC is incremented automatica
368. ndicates that a timer value was equal to the data in the TBCLx latch CCIFGO flag CCIFGO is automatically reset when the interrupt request is accepted CCIFG1 to CCIFGx flags The flag that caused the interrupt is automatically reset after the TBIV word is accessed If the TBIV register is not accessed the flags must be reset with software No interrupt is generated if the corresponding interrupt enable bit is reset but the flag will be set In this scenario the flag must be reset by the software Setting the CCIFGx flag with software will request an interrupt if the interrupt enable bit is set Capture overflow flag COV Compare mode selected CAP 0 Capture signal generation is reset No compare event will set COV bit Capture mode selected CAP 1 The overflow flag COV is set if a second capture is performed before the first capture value is read The overflow flag must be reset with software It is not reset by reading the capture value The OUTx bit determines the value of the OUTx signal if the output mode is 0 Capture compare input signal CCIx The selected input signal CCIxA CCIxB Vcc or GND can be read by this bit See Figure 12 18 Interrupt enable CCIEx Enables or disables the interrupt request signal of capture compare block x Note that the GIE bit must also be set to enable the interrupt 0 Interrupt disabled 1 Interrupt enabled Output mode select bits Table 12 8 describes the output mode s
369. nding on the output mode as shown in Figure 12 25 Figure 12 25 Output Examples Timer in Continuous Mode Output Mode 2 PWM Toggle Reset Output Mode 3 PWM Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 PWM Toggle Set Output Mode 7 PWM Reset Set TBR max TBCLO TBCL1 Oh TER Output Mode 1 Set TBOV EQU1 EQUO TBOV EQU1 EQUO Interrupt Events Timer B 12 27 The Output Unit 12 5 3 3 Output Examples Timer in Up Down Mode The OUTx signal changes when the timer equals TBCLx in either count direction and when the timer equals TBCLO depending on the output mode as shown in Figure 12 26 Figure 12 26 Output Examples Timer in Up Down Mode 1 TBR max TBCLO TBCL3 Oh Output Mode 1 Set Output Mode 2 PWM Toggle Reset ah Output Mode 3 PWM Set Reset L loOutput Mode 4 Toggle Output Mode 5 Reset E Output Mode 6 PWM Toggle Set EN Output Mode 7 PWM Reset Set TIMOV EQUO EqusTIMOV EQUO boug Interrupt Events 12 28 12 6 Timer B Registers Timer B Registers The Timer B registers described in Table 12 4 word structured and must be accessed using word instructions Table 12 4 Timer B Registers Register Timer B control Timer B register Cap com control 0 Capture compare 0 Cap com control 1 Capture compare 1 Cap com control 2 Capture compare 2 C
370. nditions modified by the latest character written to the receive buffer UxRXBUF Once any one of the bits FE PE OE BRK RXERR or RXWake is set none are reset by receiving another character The bits are reset by accessing the receive buffer by a USART software reset SWRST by a system reset PUC signal or by an instruction Figure 13 18 Receiver Control ore UORCTL U1RCTL UORCTL 072h U1RCTL 07Ah Bit 0 Bit 1 Bit 2 Bit 3 URXEIE URXWIE RXWake RXERR rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 The receive error bit RXERR indicates that one or more error flags FE PE OE or BRK is set It is not reset when the error flags are cleared by instruction Receiver wake up detect The RXWake bit is set when a received character is an address character and is transferred into the receive buffer Address bit multiprocessor mode RXWake is set when the address bit is set in the character received Idle line multiprocessor mode RXWake is set if an idle URXD line is detected 11 bits of mark level in front of the received character RXWake is reset by accessing the receive buffer UxRXBUF by a USART software reset or by a system reset PUC signal The receive wake up interrupt enable bit URXWIE selects the type of character to set the interrupt flag URXIFG URXWIE 0 Each character received sets the URXIFG URXWIE 1 Only characters that are marked as address characters set the interrupt flag
371. nected to AVss Configuration of the reference voltage s is done with the Sref bits bits 4 5 and 6 in the ADC12MCTLx registers Up to six combinations of positive and negative reference voltages are supported as described in Table 17 1 If only external references are used the internal reference generator can be turned off with the REFON bit to conserve power Table 17 1 Reference Voltage Configurations Sref Voltage at Vg Voltage at _ 0 AVcc AVss 1 Vrer internal AVSS 2 3 Vengr external AVss 4 AVcc Vngr Veger internal or external 5 Vrer internal Vngr Veger internal or external 6 7 Vengr external _ Veger internal or external The voltage levels Vg and Vp establish the upper and lower limits of the analog inputs to produce a full scale and zero scale reading respectively The values of Vn and the analog input should not exceed the positive supply or be lower than AVsg consistent with the absolute maximum ratings specified in the device data sheet The digital output is full scale when the input signal is equal to or higher than and zero when the input signal is equal to or lower than Vp ADC12 17 5 Analog Inputs Multiplexer Warning Reference Voltage Settling Time When the built in reference is turned on with the VREFON bit the settling timing noted in the data sheet must be observed before starting a conversion Otherwise the results will be false until
372. ned Reset Reset Reset Undefined Undefined Comments Not implemented Not implemented Not implemented Not implemented Not implemented Not implemented USARTO receiver enable UART mode USARTO SPI enable SPI mode USARTO transmit enable UART mode Not implemented Not implemented Not implemented Not implemented USART1 receiver enable UART mode USART1 SPI enable SPI mode USART1 transmit enable UART mode Not implemented Not implemented Interrupt Processing 3 4 2 Interrupt Vector Addresses The interrupt vectors and the power up starting address are located in the address range OFFFFh OFFEOh as described in Table 3 5 The vector contains the 16 bit address of the appropriate interrupt handler The interrupt vectors for 4xx devices are shown in the following tables Table 83 11 Interrupt Sources Flags and Vectors of 41x Configurations INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT PRIORITY Power up Reset OFFFEh 15 highest External Reset Watchdog WDTIFG Flash memory KEYV see Note 1 NMI NMIIFG see Notes 1 and 3 Non maskable Oscillator Fault OFIFG see Notes 1 and 3 Non maskable OFFFCh Flash memory access violation ACCVIFG see Notes 1 and 3 Non maskable bo ee 2 297 EET UL ems gr cast IM P1IFG O Notes 1 and gt port P1 eight flags To Maskable OFFE8h P1IFG 7 see Notes 1 and 2
373. ng Mass erase cycle No 3FFF Access violation see Note 3 Yes 3FFF JMP Nothing All erase mass and in No 3FFF Access violation formation memory Yes 3FFF JMP Nothing Block write N A 3FFF Access violation and see Note 4 LOCK see Note 5 No 3FFF Nothing Yes 3FFF Access violation and LOCK see Note 5 Notes 1 Instruction fetch refers to the fetch part of an instruction and reads one word The instruction fetch reads the first word of instructions with more than one word The JMP instruction has one word The data fetched 8FFFh is used by the CPU as an instruction 2 Ensure that the programmed data does not result in unpredictable program execution such as destruction of executable code sequences 3 If the PC points to the memory location being erased no access violation indicates this situation After erase no executable code is available and an unpredictable situation occurs 4 Any software located in a flash memory module can not use the BLKWRT mode to program the same flash memory module Using the byte or word programming mode allows programming data in the flash memory module holding the software code currently executing 5 The access violation sets the LOCK bit to 1 Setting the LOCK bit allows completion of the active block write operation in the normal manner Flash Memory Control Registers Thesupply voltage should be within the devices electrical conditions and can only vary slightly as sp
374. nly when master mode is selected SSEL1 SSELO 0 External clock UCLK selected 1 Auxiliary clock ACLK selected 2 3 SMCLK In master mode MM 1 an external clock at UCLK cannot be selected since the master supplies the UCLK signal for any slave In slave mode bits SSEL1 and SSELO are not relevant The external clock UCLK is always used Clock polarity CKPL and clock phase CKPH The CKPL bit controls the polarity of the SPICLK signal CKPL 0 The inactive level is low data is output with the rising edge of UCLK input data is latched with the falling edge of UCLK CKPL 1 The inactive level is high data is output with the falling edge of UCLK input data is latched with the rising edge of SPICLK The CKPH bit controls the polarity of the SPICLK signal as shown in Figure 14 17 CKPH 0 Normal UCLK clocking scheme CKPH 1 UCLK is delayed by one half cycle USART Peripheral Interface SPI Mode 14 17 Control and Status Registers Figure 14 17 USART Clock Phase and Polarity ckPLckeu 99 Were spem ct p sees hee Te He UGK rt ppp TEES Er TES 0 0 1 UCLK 1 1 1 hka SIMO x 0 SOMI SIMO x 1 SOMI Bac lt gt ai vl TXBUF Receive Sample Points Previous Data Bit When operating with the CKPH bit set the USART synchronous mo
375. nother output mode is selected PWM toggle reset mode The output is toggled when the timer value becomes equal to capture compare data CCRx It is reset when the timer value becomes equal to CCRO PWM set reset mode The output is set when the timer value becomes equal to capture compare data CCRx It is reset when the timer value becomes equal to CCRO Toggle mode The output is toggled when the timer value becomes equal to capture compare data CCRx The output period is double the timer period Reset mode The output is reset when the timer value becomes equal to capture compare data CCRx It remains reset until another output mode is selected PWM toggle set mode The output is toggled when the timer value becomes equal to capture compare data CCRx It is set when the timer value becomes equal to CCRO PWM toggle set mode The output is reset when the timer value becomes equal to capture compare data CCRx It is set when the timer value becomes equal to CCRO Timer Modes 11 4 4 Output Control Block The output control block prepares the value of the OUTx signal which is latched into the OUTx flip flop with the next positive timer clock edge as shown in Figure 11 23 and Table 11 2 The equal signals EQUx and EQUO are sampled during the negative level of the timer clock as shown in Figure 11 23 Figure 11 23 Output Control Block OUTx OUTx Signal Output a Control Timer Clock x Block
376. nsferred into the receive buffer Figure 13 8 USART Receiver Idle Detect Example One Stop Bit M 10 Bit Idle Period Mark XXXX SP ST XXXXXXX Space Example Two Stop Bits 10 Bit Idle Period gt Mark XXXX SP SP ST XXXXXXX Space SP Stop Bit ST Start Bit Normally if the USART URXWIE bit is set in the receive control register characters are assembled as usual by the receiver They are not however transferred to the receiver buffer UXRXBUF nor are interrupts generated When an address character is received the receiver is temporarily activated to transfer the character to UxRXBUF and to set the URXIFG interrupt flag Applicable error status flags are set The application software can validate the received address If there is a match the application software further processes the data and executes the operation If there is no match the processor waits for the next address character to arrive The URXWIE bit is not modified by the USART it must be modified manually to receive nonaddress or address characters In idle line multiprocessor format a precise idle period can be generated to create efficient address character identifiers The wake up temporary WUT flag is an internal flag and is double buffered with TXWake When the transmitter is loaded from UxTXBUF WUT is loaded from TXWake and the TXWake bit is reset as shown in Figure 13 9 Figure 13 9 Double Buffered WUT and TX Sh
377. nterval expires because the counter is no longer being reset a system reset is generated and a system PUC signal is activated The system restarts atthe same program address that follows a power up The cause of reset can be determined by testing bit O of interrupt flag register 1 in the SFRs The appropriate time interval is selected by setting bits SSEL ISO and IS1 accordingly Setting WDTCTL register bit TMSEL to 1 selects the timer mode This mode provides periodic interrupts at the selected time interval A time interval can also be initiated by writing a 1 to bit CNTCL in the WDTCTL register When the WDT is configured to operate in timer mode the WDTIFG flag is set after the selected time interval and it requests a standard interrupt service The WDT interrupt flag is a single source interrupt flag and is automatically reset when it is serviced The enable bit remains unchanged In interval timer mode the WDT interrupt enable bit and the GIE bit must be set to allow the WDT to request an interrupt The interrupt vector address in timer mode is different from that in watchdog mode RR Note Watchdog Timer Changing the Time Interval Changing the time interval without clearing the WDTCNT may result in an unexpected and immediate system reset or interrupt The time interval must be changed together with a counter clear command using a single instruction for example MOV 05A0Ah amp WDTCTL Changing the clock
378. ode for the source operand When indirect or indirect autoincrement address modes are used another instruction is needed between the writing of the second operand and accessing the result registers Both operands OP1 and OP2 utilize all seven address mode capabilities No instruction is necessary for the multiplication as a result the real time operation does not require additional clock cycles and the interrupt latency is unchanged The multiplier architecture is illustrated in Figure 6 2 Figure 6 2 Block Diagram of the MSP430 16x16 Bit Hardware Multiplier 15 rw 0 0 15 rw 0 Operand 2 138h Operand 1 address defines operation Operand 1 Mode Accumulator ACC SumHi 13Ch SumLo 013Ah Hardware Multiplier 6 3 Hardware Multiplier Operation The sum extension register contents differ depending on the operation and on the results of the operation Table 6 1 Sum Extension Register Contents Register MPY MPYS MAC MACS see Notes Operand1 x 1 2 OP1xOP2 OP1xOP2 OP1xOP2 ACO lt ACC gt ACC gt ACC lt Operand2 X TS QFFFFFFFFh OFFFFFFFFh 7 07FFFFFFFh SumExt 0000h 0000h OFFFFh 0000h 0001h OFFFFh 0000h Note following two overflow conditions may occur when using the MACS function and should be handled by software or avoided 1 The result of a MACS operation is positive and larger than 07FFF FFFFh In this case
379. ode selected SYNC 1 SPI synchronous mode selected The 43x has one USART named USARTO The 44x has two USARTs imple mented USARTO and USART1 This chapter addresses the UART mode Topic Page 13 1 USART Peripheral Interface 13 2 13 2 USART Peripheral Interface UART Mode 13 3 13 3 Asynchronous Operation 13 4 13 4 Interrupt and Enable Functions 13 11 13 5 Control and Status Registers 13 15 13 6 Utilizing Features of Low Power Modes 13 23 13 7 Baud Rate Considerations 13 26 13 1 USART Peripheral Interface 13 1 USART Peripheral Interface The USART peripheral interface connects to the CPU as a byte peripheral module It connects the MSP430 to the external system environment with three or four external pins Figure 13 1 shows the USART peripheral interface module Figure 13 1 Block Diagram of USART Receive Buffer R eceive Status UORXBUF or UtRXBUF SYNC RXE Listen MM SYNC Jr en SOMI Receive Shift Register 1 0 SYNC BS SSEL1 SSELO Dio prese 910 ine UCLKI X STE ACLK o ius aH ae 3 SMCLK o UTXD e gt 4115 SIMO lt gt 0 TXWake CKPH SYNC CKPL UCLKI UCLKS 13 2 USART Peripheral Interfa
380. of 250 ms the following instruction sequence can be used MOV WDTPW WDTCNTCL WDTTMSEL WDTISO amp WDTCTL Clear WDTCNT and select 250 ms and timer mode Note The time interval and clear of WDTCNT should be modified within one instruction to avoid E unexpected reset or interrupt Watchdog Timer 9 7 9 8 Chapter 10 Basic Timer1 This chapter discusses the Basic Timer1 Topic Page 1 10 2 10 1 Basic Timer1 10 1 Basic Timer1 The Basic Timer1 shown in Figure 10 1 supplies other peripheral modules orthe software with low frequency control signals The Basic Timer1 operation supports two independent 8 bit timing counting functions or one 16 bit timing counting function Some uses for the Basic Timer1 include Li Real time clock RTC Lj Debouncing keys keyboard Software time increments Figure 10 1 Basic Timer1 Configuration 10 2 Control Register BTCTL SSEL DIV1 0 2 1 0 Hold FRFQ IP IP IP Hold EN1 ue BTCNT1 Q4Q5 Q6 Q7 FHFQ1 9 9 9 9 FRFQ0 o 0 1 2 3 n js 0 ACLK 256 o BTCNT2 2 gt CLK2 SMCLK o 3 Q1 Q2 Q3 Q4 Q5 Q6 Q7 1 2 lt Set Interrupt 0 le Is 5 Ic y BTIFG Basic 10 1 1 Basic Timer1 Regis
381. of ADC12CTLx are reset during POR Most of the control bits in registers ADC12CTLO ADC12CTL1 and ADC12MCTLx can only be modi fied if ENC is reset These bits are marked LJ All other bits can be modified at any time The control bits of control register ADC12CTLO and ADC12CTL1 are 8 7 0 rw 0 bit1 REF 12 ADC12 ADC12 ADC12 2 5V rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Sample and convert The ADC12SC bit can be used to control the conversion with software if is set It is recommended to have ISSH 0 If the sampling signal SAMPCON is generated by the sampling timer SHP 1 changing the ADC12SC bit from 0 to 1 starts the sample and conversion operation When the A D conversion is complete BUSY 0 the ADC12SC bit is automatically reset If the sample signal is directly controlled by ADC12SC SHP 0 then the high level of the ADC12SC bit defines the sample time The conversion starts once it is reset All automatic sequence functions CONSEQ 1 2 3 and multiple sample and conversion functions MSC 1 are executed normally Therefore when using ADC12SC the software must ensure that the frequency of the timing of the ADC12SC bit meets the applicable timing requirements NOTE The start of a conversion by software SHS 0 in ADC12CTL1 is possible by setting both ENC and ADC12SC control bits within one instruction Enable conversion T
382. oints to the operand X is stored in the next word Indexed mode is used amp ADDR The word following the instruction contains the absolute address Indirect register mode Rn Rnis used as a pointer to the operand Indirect autoincrement Immediate mod Rn Rn is used as a pointer to the operand Rn is incremented afterwards e N The word following the instruction contains the immediate constant N Indirect autoincrement mode PC is used The seven addressing modes are explained in detail in the following sections Most of the examples show the same addressing mode for the source and destination but any valid combination of source and destination addressing modes is possible in an instruction Addressing Modes 5 2 1 Register Mode The register mode is described in Table 5 5 Table 5 5 Register Mode Description Assembler Code Content of ROM MOV R10 R11 MOV R10 R11 Length One or two words Operation Move the content of R10 to R11 R10 is not affected Comment Valid for source and destination Example MOV R10 R11 Before After Note Data in Registers The data in the register can be accessed using word or byte instructions If byte instructions are used the high byte is always 0 in the result The status bits are handled according to the result of the byte instruction 16 Bit CPU 5 7 Addressing Modes 5 2 2 Indexed Mode The indexed mode is described in Table 5 6 Table 5 6 I
383. ompara tor offset 15 2 3 The Comparator The comparator compares the analog voltages at the and input terminals If the terminal is more positive than the terminal the comparator output will be high note that the value of signal CAOUT also depends on the value of CAEX The comparator can be switched on or off using control bit CAON The comparator should be switched off when not in use to stop its current consumption When the comparator is switched off the output is low Note that the value of CAOUT still depends on the value of CAEX even when the comparator is off 15 2 4 The Output Filter The output of the comparator can be used with or without internal filtering When control bit CAF is set the output is filtered with an chip RC filter The filter is bypassed when CAF is reset Comparator_A 15 3 Comparator A Description A comparator output will oscillate if the voltage difference across the input terminals is small Internal and external parasitic effects and cross coupling on and between signal lines power supply lines and other parts of the system are responsible for this behavior see Figure 15 2 The comparator output oscillation reduces accuracy and resolution of the comparison result Selecting the output filter can reduce errors associated with comparator oscillation Figure 15 2 RC Filter Response at the Output of the Comparator 4 Terminal Terminal EE III Comparator Inputs Comparator
384. on Sn 1 Sn 33 COMO Sie ser cere ree Teer eee ee SS Terese ee ee 16 14 LCD Controller Driver 16 2 6 2 Example Using Two MUX 1 2 Bias Drive Mode The two MUX drive mode uses COMO In this mode bits 0 1 4 and 5 are used for segment information The other bits can be used like any other memory Figure 16 11 shows an example two MUX LCD pin out LCD to 430 connections and the resulting data mapping Note this is only an example Segment mapping in a user s application completely depends on the LCD pin out and on the 430 to LCD connections Liquid Crystal Display Drive 16 15 LCD Controller Driver Figure 16 11 Example With the Two MUX Mode DIGIT8 DIGIT1 Pinout and Connections Display Memory Connections COM 131 2 1 0 2 1 0 1430 LCD Pinout PIN cou 0A0h n 30 1 Digit8 S0 si ta 09Fh 28 __ 51 22 ih ib 0Eh 9g e c d 26 S ijid 2 h 26 29 93 gt 4 te 19 S4 a3 5 2 2 O09Ch g e d 22 Digit 6 s 20 Toe x S gt 8 2e 29 SAAR js Digit 5 S8 3 099h 16 59 10 3h 3b 098h 14 pigit4 S10 11 3d 3c 097h b h a f 12 11 4 12 39 35 mE 12 4 13 4f 4a 096h 9 E g 10 Digit 3 S13 4 14 4h 4 o95hj b f 8 5 gy Sie si
385. on 13 5 3 Modulation control UOMCTL Read write 073h Unchanged Baud rate 0 UOBRO Read write 074h Unchanged Baud rate 1 UOBR1 Read write 075h Unchanged Receive buffer UORXBUF Read write 076h Unchanged Transmit buffer UOTXBUF Read 077h Unchanged Table 13 3 USAHT1 Control and Status Registers Short Register Register Form Type Address Initial State USART control U1CTL Read write 078h See section 13 5 1 Transmit control U1TCTL Read write 079h See section 13 5 2 Receive control U1RCTL Read write 07Ah See section 13 5 3 Modulation control U1MCTL Read write 07Bh Unchanged Baud rate 0 U1BRO Read write 07Ch Unchanged Baud rate 1 U1BR1 Read write 0708 Unchanged Receive buffer U1RXBUF Read write 07Eh Unchanged Transmit buffer U1TXBUF Read 07Fh Unchanged All bits are random after a PUC signal unless otherwise noted by the detailed functional description The reset of the USART peripheral interface is performed by a PUC signal or a SWRST After a PUC signal the SWRST bit remains set and the USART interface remains in the reset condition until it is disabled by resetting the SWRST bit The USART module operates in asynchronous or synchronous mode as defined by the SYNC bit The bits in the control registers can have different functions in the two modes All bits in this section are described with their functions in the asynchronous mode SYNC 0 Their functions in the synchronous mode are described in Chapter 14 USART Peripheral Interface
386. on result register ADC12MENMXx is loaded with the result of a conversion The range for x is 15 The interrupt flags are reset if their corresponding ADC12MEMx conversion result register is accessed To enable correct handling of overflow conditions they are not reset by accessing the interrupt vector word ADC12IV The overflow condition exists if another conversion result is written to ADC12MEMXx and the corresponding ADC12IFG x is not reset ADC12IE ADC ADC 01A6h 1 12 IE 10 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADCi2IE x bits 0 15 ADC12IE x interrupt enable bit enables or disables the interrupt request service generated if the corresponding interrupt flag ADC121FG x is set The range for x is O to 15 17 8 5 ADC12 Interrupt Vector Register ADC12IV The 12 bit ADC has one interrupt vector to assist the handling of the 18 possible interrupt flags Each of the 18 interrupt flags is prioritized and aunique vector word is generated according to the highest pending interrupt The priorities and corresponding vector word values are shown in Table 17 3 Overflow flag ADC12OVIFG has the highest priority followed by timing overflow flag ADC12TOVIFG and then by the interrupt flags for each conversion memory register ADC121FG 0 to ADC12IFG 15 The highest pending interrupt flag generates a number from 0 no interrupt is pending to 36 This enco
387. onditions of the ADC12 such as conversion modes sample and conversion control signal ADC clock and sample timing are located in control registers ADC12CTLO and ADC12CTL1 Each conversion memory register is individually accessible by software in the address range 0140h 015Eh Using the conversion memory involves control bits in two places First the CStartAdd bits located in ADC12CTL1 point to the conversion memory register to be used for single channel conversions or the first conversion memory register to be used for a sequence The conversion start address CStartAdd can be any value Oh OFh and points to ADC12MEMO ADC12MEM15 respectively Second the end of sequence EOS bit in each conversion memory control register marks the end of an automatic conversion sequence The EOS bit when set defines the end of a conversion sequence When cleared an internal conversion memory pointer not visible to software is in cremented after the current conversion is completed and the conversion result is stored in the conversion memory The conversion memory pointer is then prepared to use the next conversion memory register to store the results of the next conversion The internal conversion memory pointer is incremented with each conversion until aset EOS bit is encountered Note that defining the end of a sequence is independent from defining the mode of operation see the Conversion Modes section and that the EOS bits are igno
388. opriate software routine without the need for reading and evaluating the interrupt vector The software example in section 12 6 4 3 shows this technique 12 36 Timer B Registers Table 12 10 Vector Register TBIV Description Interrupt Vector Register Priority Interrupt Source Short Form TBIV Contents Highestt Capture compare 1 CCIFG1 2 Capture compare 2 CCIFG2 4 Capture compare 3t CCIFG3 6 Capture compare 4t CCIFG4 8 Capture compare 5 CCIFG5 10 Capture compare 6t CCIFG6 12 Lowest Timer overflow TBIFG 14 No interrupt pending 0 T Highest pending interrupt other than CCIFGO CCIFGO is always the highest priority Timer B interrupt t 44x devices only TBIV content reserved in 41x and 43x devices Accessing the TBIV register automatically resets the highest pending interrupt flag If another interrupt flag is set then another interrupt will be immediately generated after servicing the initial interrupt For example if both CCIFG2 and CCIFG3 are set when the interrupt service routine accesses the TBIV register either by reading it or by adding it directly to the PC CCIFG2 will be reset automatically After the RETI instruction of the interrupt service routine is executed the flag will generate another interrupt Note Writing to Read Only Register TBIV Register TBIV should not be written to If a write operation to TBIV is performed the interrupt flag of the highest pending interrupt is reset Therefore
389. or fault interrupt requests a nonmaskable interrupt if the OFIE bit is set The oscillator interrupt enable bit is reset automatically if a non maskable interrupt is accepted The initial state of the OFIE bit is reset and no oscillator fault requests an interrupt even if a fault condition occurs Chapter 8 Digital I O Configuration This chapter describes the digital I O configuration Topic Page 8 1 Introd ction Seti 8 2 8 26 Generali Ports PA P2 A 8 3 8 9 8 3 General Ports P3 P4 P5 P6 8 1 Introduction 8 1 8 2 Introduction The general purpose ports of the MSP430 are designed to give maximum flexibility Each line is individually configurable and most have interrupt capability There are two different types of I O port modules in the MSP430x4xx family devices Ports P1 and P2 are of one type and ports P3 to P6 are of another type Both types have the capability to control input output direction and output level to read the level applied to a pin and to control if a port or module function is applied to a pin The port module for P1 and P2 have interrupt capability flag enable and edge sensitivity are available individually for each bit See the device data sheet for the implementation of ports on a specific device Ports P1 P2 8 2 Ports P1 P2 Each of the general purpose ports P1 and P2 contain 8 general purpose I O l
390. or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice is not responsible or liable for any such statements Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2002 Texas Instruments Incorporated About This Manual Preface Read This First The MSP430x4xx user s guide is intended to assist in the development of
391. ores the SR operating modes FLL Clock Module 7 11 Buffered Clock Output on the stack and then clears the SCG1 bit in the SR automatically starting the DCO and MCLK SMCLK After the interrupt handler has completed the saved SR is popped from the stack with the RETI instruction restoring the previous operating mode 7 6 Buffered Clock Output The clock buffer shown in Figure 7 6 allows ACLK ACLK 2 ACLK 4 or ACLK 8 to be output as secondary pin function outputs The clock buffer is controlled using the FLL_DIV bits which define the division rate of the ACLK signal Figure 7 6 Schematic of Clock Buffer FLL DIV ACLK 1 2 4 8 FLL DIV 0 1 1 2 2 4 3 8 Example output ACLK on P1 5 bis b P1SEL_5 amp P1SEL bis b P1DIR_5 amp P1DIR 7 12 Select output Select signal ACLK n P1 5 TACLK ACLK ACLK n signal as for port P1 5 if port P1 5 to ACLK n for output FLL Module Control Registers 7 7 FLL Module Control Registers The module is configured using control registers SCFQCTL SCFIO SCFI1 CBCTL and four bits from the CPU status register SCG1 SCGO OscOff and CPUOff User software can modify these control registers from their default condition at any time The FLL control registers are located in the byte wide peripheral map and should be accessed with byte B instructions Register Short Form Register Type Address lnitial State System clock control S
392. out and on the 430 to LCD connections Figure 16 13 Example With the Four MUX Mode LCD DIGIT15 DIGIT1 Pinout and Connections Display Memory Connections COM 3 2 1 0 3 2 1 0 430 Pins LCD Pinout gt PIN 1 2 09Fh a b h 30 Digit 16 S0 1 O9Eh a8 b c h 28 Digit 15 gt 09Dh 8 b h fig e d 26 Digit 14 lt gt a b h f e d 24 Digi 53 e gt 4 09Ch 9 Digit 13 S4 a5 09Bh 22 Digit 12 55 4 6 09Ah a b f g e d 20 Digit 11 S6 4 7 a b f g e d 18 Digit 10 57 4 8 099h b 1 d 58 4 9 5d 5g 5 osh 16 Digit 9 S9 lt 10 5h 5 5 5a a bj c h 14 Digit 8 bond c 09 12 Digit7 S11 4 12 6h 6c 66 096h eee 12 13 7d 7 79 7 nen fjg e d 10 Digit 6 S13 4 14 7h 7 7b 7a al b f g e d 8 Digit5 Da Ne ee E ee Quan ble mts eT igi 515 16 8h 8c 8 8a REN 6 die 516 17 9d 9e 9 9 09 4 Digit3 517 4 18 9h 9c 9b 9a 092h b C h f g e d 2 Digit2 enc dou a oMh alb c n ft 0 Digit S20 21 1 119 11 _ 521 4 22 iih 1 116 tia Parallel S22 lt 23 12d 12 129 12 Serial 523 4 24 12h 12c 126 12a Conversion S24 4225 13 13 139 13 25 lt 26 13h 13 136 13a 26 4 27 14d 14 149 14 S27 4228 14h 14 146 14
393. outine ISR The RETI return from interrupt instruction has no effect on the individual enable bits of the non maskable interrupts So the software must set the corresponding interrupt enable bit in the ISR before execution of the RETI instruction for the interrupt to be reenabled after the ISR A non maskable interrupt NMI can be generated by an edge on the RST NMI pin if NMI mode is selected by the occurrence of an oscillator fault if the oscillator fault interrupt is enabled or by an access violation to the flash memory if the access violation interrupt is enabled System Resets Interrupts and Operating Modes 3 7 MSP430 Interrupt Priority Scheme 3 3 MSP430 Interrupt Priority Scheme The interrupt priority of the modules as shown in Figure 3 5 is defined by the arrangement of the modules in the connection chain the nearer a module is to the CPU NMIRS the higher the priority Figure 3 5 Interrupt Priority Scheme High Priority Low Circuit OSCfault Flash ACCV Reset NMI WDT Security Key A7 Flash Security Key SZ NZ Nu Non MAB 5LSBs Reset and NMI as shown in Figure 3 6 can only be used as alternative interrupts because they use the same input pin The associated control bits are located in the watchdog timer control register shown in Figure 3 7 and are password protected 3 8 MS
394. overflow occurs otherwise reset OscOff CPUOff and GIE are not affected The 16 bit counter pointed to by R13 is added to a 32 bit counter pointed to by R12 ADD R13 0 R12 Add LSDs ADC 2 R12 Add carry to MSD The 8 bit counter pointed to by R13 is added to a 16 bit counter pointed to by R12 ADD B R13 0 R12 Add LSDs ADC B 1 R12 Add carry to MSD Instruction Set Description B 9 Instruction Set Overview ADD W ADD B Syntax Operation Description Status Bits Mode Bits Example Example Add source to destination Add source to destination ADD src dst or ADD W Src dst ADD B src dst src dst dst The source operand is added to the destination operand The source operand is not affected The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the result cleared if not V Set if an arithmetic overflow occurs otherwise reset OscOff CPUOff and GIE are not affected 5 is increased by 10 The jump to TONI is performed on a carry ADD 10 R5 JC TONI Carry occurred No carry R5 is increased by 10 The jump to TONI is performed on a carry ADD B 10 5 Add 10 to Lowbyte of R5 JC TONI Carry occurred if R5 gt 246 DAh 0F6h x No carry ADDC W ADDC B Syntax Operation Description Status Bits Mode Bits Example Example Instructio
395. peripheral module registers data and code memory The SFRs and peripheral modules are mapped into the address range starting with 0 and ending with O1FFh The remaining address space 0200h to OFFFFh is shared by data and code memory The start address for code memory depends on the amount of memory present The interrupt vector table is mapped into the the upper 16 words of memory address space with the highest priority interrupt vector at the highest memory word address OFFFEh See the individual data sheets for specific memory maps Figure 4 4 ROM Organization OFFFEh _ vx Vectors Vectors Vectors i d OFO00h _ OEFFFh e e e O0DOO0h OCFFFh e e e 08000h 4 3 1 Processing of Memory Tables 4 4 The 430 architecture allows for the storage and usage of large tables in memory without the need to copy the tables to RAM before using them This memory accessing of tables allows fast and clear programming in applications where data tables are necessary This offers the flexible advantages listed below and saves on memory and RAM requirements To access these tables all word and byte instructions can be used Memory storage of an output programmable logic array OPLA for display character conversion The use of as many OPLA terms as needed no restriction on n terms MTP flash version automatically includes OPLA programmability Computed table accessibility for example for a bar graph display
396. pling Sampling Start Conversion Stop Conversion Y Y Y Sample Conversion and Hold The analog input signal must be valid and steady during the sampling period in order to obtain an accurate conversion It is also desirable not to have any digital activity on any adjacent channels during the whole conversion period to ensure that errors due to supply glitching ground bounce or crosstalk do not corrupt the conversion results In addition gains and losses in internal charge limit the hold time The user should ensure that the data sheet limits are not violated Otherwise the sampled analog voltage may increase or decrease resulting in false conver sion values 17 7 2 Sample Signal Input Selection The SAMPCON signal which controls sample timing and the start of a conversion may be sourced by one of several signals SAMPCON may be sourced directly from one of the signals available at the input selection switch see Figure 17 16 further called sample signal input or from the integrated sampling timer When the sampling timer is used to source SAMPCON the sample signal input is used to trigger the sampling timer The sample signal input is selected by the SHS bits in ADC12CTL1 There are four choices for the sample signal input ADC12SC Timer A OUTI1 Timer B OUTO and Timer B OUT1 The polarity of the sample signal input may be selected by the ISSH bit see Figure 17 16 Also the sample signal input is passed to the
397. power mode 2 LPM2 SCG1 1 SCGO 0 OscOff 0 CPUOff 1 CPU is disabled MCLK and loop control for MCLK are disabled DCO s dc generator remains enabled ACLK remains active Low power mode LPM3 SCG1 1 SCGO 1 OscOff 0 CPUOff 1 CPU is disabled MCLK and loop control for MCLK are disabled DCO oscillator is disabled DCO s dc generator is disabled ACLK remains active Low power mode 4 LPM4 SCG1 X SCG0 X OscOff 1 CPUOff 1 CPU is disabled ACLK is disabled MCLK and loop control for MCLK are disabled DCO oscillator is disabled dc generator is disabled Crystal oscillator is stopped Note Peripheral operation is not halted by CPUOff Peripherals are controlled by their individual control registers Cd Table 3 13 Low Power Mode Logic Chart SCG1 SCGO LPMO 0 0 LPM1 0 1 LPM2 1 0 LPMS3 1 1 LPM4 X X OscOff Operating Modes CPUOff 1 r These modes are illustrated in Figure 3 11 Figure 3 11 MSP430x3xx Family Operating Modes RST NMI Reset Active WDTIFG 0 WDT Active Jime Expired Overflow WDTIFG 1 WDTIFG 1 RST NMI is Reset Pin is Slowed Down WDT is Active WDT Active Security Key Violation 1 SCGO 1 0 LP Mode LPMO CPU Off FLL On MCLK on ACLK On Active Mode CPU Is Active Various Modules Are Active CPUOff 1 SCGO 1 SCG1 0 LP Mode 1 C
398. pport The hardware multiplier module expands the capabilities of the MSP430 family without changing the basic architecture Multiplication is possible for 16x16 bits Lj 16x8 bits 8x16 bits 8x8 bits The hardware multiplier module supports four types of multiplication unsigned multiplication MPY signed multiplication MPYS unsigned multiplication with accumulation MAC and signed multiplication with accumulation MACS Figure 6 1 shows how the hardware multiplier module interfaces with the bus system to support multiplication operations Figure 6 1 Connection of the Hardware Multiplier Module to the Bus System 6 2 TDI TDO MAB 16 Bit CPU Test Incl 16 Reg JTAG MDB 16 Bit TMS TCK r Hardware Multiplier Operation 6 2 Hardware Multiplier Operation The hardware multiplier has two 16 bit registers for both operands and three registers to store the results of the multiplication The multiplication is executed correctly when the first operand is written to the operand register OP1 prior to writing the second operand to OP2 Writing the first operand to the applicable register selects the type of multiplication Writing the second operand to OP2 starts the multiplication Multiplication is completed before the result registers are accessed using the indexed address m
399. put I O port 1 2 eight I Os each all with interrupt ports 4 5 6 eight I Os each Two USARTs USARTO and USART1 Hardware multiplier Package option 100 pin QFP The 44x device family includes MSP430F4471 32 KB flash memory 1 KB RAM MSP430F448t 48 KB flash memory 2 RAM MSP430F449T 60 KB flash memory 2 RAM t Advanced Information future devices Chapter 2 Architectural Overview This section describes the basic functions of an MSP430 based system The MSP430 devices contain the following main elements Central processing unit L Program memory Data memory Operation control Lj Peripheral modules L Oscillator and clock generator Topic Page IINTFOGUCTION 2 2 2 22 2 2 2 3 Programi Memory 2 3 241 Data i Memory 2 3 2 5 Operation Control sec isis cae Mee dele ea eae 2 3 216 SS SEI 2 4 27 Oscillator and Clock Generator 2 4 2 1 Introduction 2 1 Introduction The architecture of the MSP430 family is based on a memory to memory architecture a common address space for all functional blocks and a reduced instruction set applicable to all functional blocks as illustrated in Figure 2 1 See specific device data sheets for complete block diagrams of individual devices Figure 2 1 MSP430 Syst
400. qual to compare data TBCLx The output period is double the timer period Reset mode The output is reset when the timer value becomes equal to compare data TBCLx It remains reset until another output mode is selected to control the output PWM toggle set mode The output is toggled when the timer value becomes equal to compare data TBCLx It is set when the timer value becomes equal to TBCLO PWM toggle set mode The output is reset when the timer value becomes equal to compare data TBCLx It is set when the timer value becomes equal to TBCLO The Output Unit 12 5 2 Output Control Block The output control block prepares the value of the OUTx signal which is latched into the OUTx flip flop with the next positive timer clock edge as shown in Figure 12 23 and Table 12 3 The equal signals EQUx and EQUO are sampled during the negative level of the timer clock as shown in Figure 12 23 Figure 12 23 Output Control Block OUTx OUTx Signal Output a Control Timer Clock x Block OMx2 OMx1 OMx0 The timer is Incremented with the rising edge of the timer clock Timer W m V V V V TBRmag V V V A TBR n EQUx TBCLx n EQUO TBR 0 or TBR TBCLO EQUO Delayed Used in Up Mode Only EQUO delayed is used in up mode not EQUO EQUO is active high when TBR TBCLO EQUO delayed is active high when
401. r This bit is automatically reset if the interrupt request service is started or a character is written into the UxTXBUF This flag asserts a transmitter interrupt if the local UTXIE and general interrupt enable GIE bits are set The UTXIFG is set after a system reset signal or removal of a SWRST Figure 13 15 Transmit Interrupt Operation PUC or SWRST Request _ UTXIFG Interrupt Service Character Moved From SWRST Buffer to Shift Register IRQA UxRXBUF Written Into Transmit Shift Register The transmit interrupt enable UTXIE bit controls the ability of the UTXIFG to request an interrupt but does not prevent the flag UTXIFG from being set The UTXIE is reset with a PUC signal or a software reset SWRST bit The UTXIFG bit is set after a system reset PUC signal or software reset SWRST but the UTXIE bit is reset to ensure full interrupt control capability 13 14 Control and Status Registers 13 5 Control and Status Registers The USART control and status registers are byte structured and should be accessed using byte processing instructions suffix B Table 13 3 lists the registers and their access modes Table 13 2 USAHTO Control and Status Registers Short Register Register Form Type Address Initial State USART control UOCTL Read write 070h See section 13 5 1 Transmit control UOTCTL Read write 071h See section 13 5 2 Receive control UORCTL Read write 0728 See secti
402. r value Figure 12 30 Capture Compare Interrupt Flag Capture EQO IRQ Interrupt Service Requested TBCLO Timer CAP Timer Clock IRACC Interrupt_Request_Accepted Capture compare register 0 has the highest Timer_B interrupt priority and uses its own interrupt vector Timer_B 12 35 Timer B Registers 12 6 4 2 Vector Word TBIFG CCIFG1 to CCIFGx Flags The CCIFGx other than CCIFGO and TBIFG interrupt flags are prioritized and combined to source a single interrupt as shown in Figure 12 31 The interrupt vector register TBIV shown in Figure 12 32 is used to determine which flag requested an interrupt Figure 12 31 Schematic of Capture Compare Interrupt Vector Word CCH CCIFG1 EQ1 1 Timer Clock CCI2 EQ2 CMP2 Timer Clock Interrupt Service Request Module 3 Priority and Module 4 Vector Word Generator Module 5 Interrupt Vector Address CCIFG6 CCI6 EQ6 CMP6 Timer Clock TBR MAX Timer TBCLO XXX Timer Clock Figure 12 32 Vector Word Register 15 0 o o o o o 0 0 r 0 r0 r0 roO ro r0 rO ro 0 roO rO r r TBIV 11Eh The flag with the highest priority generates a number from 2 to 14 in the TBIV register as shown in Table 12 10 If the value of the TBIV register is 0 no interrupt is pending This number can be added to the program counter to automatically enter the appr
403. r FFFF Timer CCRO XXX Timer Clock Figure 11 32 Vector Word Register 15 0 0 100 700 10 ro ro 0 rO ro r0 roO ro rO ro n r TAIV 12Eh The flag with the highest priority generates a number from 2 to 12 in the TAIV register as shown in Table 11 9 If the value of the register is 0 no interrupt is pending This number can be added to the program counter to automatically enter the appropriate software routine without the need for reading and evaluating the interrupt vector The software example in Section 11 5 4 3 shows this technique Timer A 11 29 Timer A Registers Table 11 9 Vector Register TAIV Description Interrupt Vector Register Priority Interrupt Source Short Form TAIV Contents Highestt Capture compare 1 CCIFG1 2 Capture compare 2 CCIFG2 4 Reserved 6 Reserved 8 Timer overflow TAIFG 10 Reserved 12 Lowest Reserved 14 No interrupt pending 0 t Highest pending interrupt other than CCIFGO CCIFGO is always the highest priority Timer A interrupt Accessing the TAIV register automatically resets the highest pending interrupt flag If another interrupt flag is set then another interrupt will be immediately generated after servicing the initial interrupt For example if both CCIFG1 and CCIFG2 are set when the interrupt service routine accesses the register either by reading it or by adding it directly to the PC CCIFG1 will be
404. r Module Support 6 2 6 2 Hardware Multiplier Operation 6 3 6 2 1 Multiply Unsigned 16x16 bit 16x 8 bit 8x 16 bit 8 x8 bit 6 4 6 2 2 Multiply Signed 16 x16 bit 168 bit 8x16 bit 8x8 6 4 6 2 3 Multiply Unsigned and Accumulate 16x16 bit 16x8 bit 8x16 bit 8x8 bit 6 5 6 2 4 Multiply Signed and Accumulate 16x16 bit 16x8 bit 8x16 bit 8x8 bit 6 5 6 3 Hardware Multiplier Registers 6 6 6 4 Hardware Multiplier Special Function Bits 6 7 6 5 Hardware Multiplier Software Restrictions 6 7 6 5 1 Hardware Multiplier Software Restrictions Address Mode 6 7 6 5 2 Hardware Multiplier Software Restrictions Interrupt Routines 6 8 6 5 3 Hardware Multiplier Software Restrictions MACS 6 9 7 Clock Module ohh eee eds eee beds gus 7 1 Z4 The FEE ClockiModuile 3 21 27 dated thesia Rb RIETI 7 2 4 2 OSCIALOR oie Ito eem eb ume UN Ee 7 4 7 3 Digitally Controlled Oscillator DCO and Frequency Locked Loop 7 5 Fal FEL Operations tu 7 7 7 3 2 Modulator Operation 7 8 7 3 3 Frequency Range
405. r continuously counts up to TBCCRO and back down to 0 Note If TBCCRO gt TBR max the counter oper ates as if it were configured for continuous mode It will not count down from TBR max to zero Input divider control bits Table 12 6 describes the clock divider Description Input clock source is passed to the timer Input clock source is divided by two Input clock source is divided by four Input clock source is divided by eight Bits 8 9 Clock source selection bits Table 12 7 describes the clock source selections Table 12 7 Clock Source Selection TBSSEL1 0 0 1 1 0 1 0 1 TBSSELO Signal TBCLK ACLK SMCLK INCLK Comment See data sheet device description Auxiliary clock ACLK is used System clock SMCLK See device description in data sheet 12 30 Timer B Registers Bit 10 Unused Bits 11 12 Configure 16 bit timer TBR for 8 bit 10 bit 12 bit or 16 bit operation CNTL 0 16 bit length TBR max is OFFFFH CNTL 1 12 bit length TBR may is OFFFH CNTL 2 10 bit length TBR max is O3FFH CNTL 3 8 bit length TBR max is Bits 13 14 Load compare latches individually or in groups The load signal is controlled via the CLLDx bits located in the appropriate capture compare control register TBCCTLx TBCLGRP 0 load individually Load ofthe shadow registers is defined in each individual TBCCTLx register by bits CLLDx The CLLD bits in each TBCCTLx register define
406. ransmit Compare Compare Acomplete application note including connection diagrams and complete soft ware listing may be found at www ti com sc msp430 11 34 Chapter 12 Timer This section describes the basic functions of the MSP430 general purpose 16 bit Timer B Timer B implementation differs among MSP430 devices Always check the device s data sheet to determine the connections and the number of identical capture compare registers Also the data sheets use additional nomenclature to indicate the number of capture compare registers implemented for a specific device For example if Timer is discussed in a data sheet then that device s implementation of Timer B contains 3 capture compare registers In its default condition Timer B operates identically to Timer A except the SCCI bit is not implemented on Timer B p A A M A A M Note Throughout this chapter the word countis used in the text As used in these instances it refers to the literal act of counting It means that the counter must be in the process of counting for the action to take place If a particular value is directly written to the counter then the associated action will nottake place For example the TBCCRO interrupt flag is set when the timer counts up to the
407. re For example BIS CAP amp CCTL2 Select capture with register CCR2 XOR CCIS1 amp CCTL2 Software capture CCISO 0 Capture mode 3 ee 11 5 4 Timer_A Interrupt Vector Register Two interrupt vectors are associated with the 16 bit Timer_A module CCRO interrupt vector highest priority interrupt vector for flags CCIFG1 CCIFGx and TAIFG 11 5 4 1 CCRO Interrupt Vector The interrupt flag associated with capture compare register CCRO as shown in Figure 11 30 is set if the timer value is equal to the compare register value Figure 11 30 Capture Compare Interrupt Flag Capture EQUO IRQ Interrupt Service Requested CCRO Timer CAP Timer Clock IRACC Interrupt Request Accepted Capture compare register 0 has the highest Timer A interrupt priority and uses its own interrupt vector 11 28 Timer A Registers 11 5 4 2 Vector Word TAIFG CCIFG1 to CCIFG4 Flags The CCIFGx other than CCIFGO and TAIFG interruptflags are prioritized and combined to source a single interrupt as shown in Figure 11 31 The interrupt vector register TAIV shown in Figure 11 32 is used to determine which flag requested an interrupt Figure 11 31 Schematic of Capture Compare Interrupt Vector Word CCIFG1 1 1 Timer Clock Interrupt Service Request CCI2 EQ2 Priority and CMP2 Vector Word Timer Clock Generator Interrupt_Vector_Address gt Time
408. re as described in section 11 4 1 1 If a capture is performed The interrupt flag CCIFGx located in control word TBCCTLx is set An interrupt is requested if both interrupt enable bits CCIEx and GIE are set The input signal to the capture compare block is selected using control bits CCISx1 and CCISx0 as shown in Figure 12 18 The input signal can be read at any time by the software by reading bit CCIx Figure 12 18 Capture Logic Input Signal CCISx1 CCISx0 CAPx 0 Set EQUx l CClxA 0 0 4 0 Set CCIFGx GND i G Timer Synchronize 1 Clock Capture SCSx apture 0 0 Disabled 0 1 Positive Edge 1 0 Negative Edge 1 1 Both Edges CCIx The capture signal can also be synchronized with the timer clock to avoid race conditions between the timer data and the capture signal This is illustrated in Figure 12 19 The bit SCSx in capture compare control register TBCCTLx selects the capture signal synchronization Figure 12 19 Capture Signal Timer Clock Timer CCIx 774 Capture Set CCIFGx 12 16 Timer Modes Applications with slow timer clocks can use the nonsynchronized capture signal In this scenario the software can validate the data and correct it if necessary as shown in the following example Software example for the handling of asynchronous capture signals The data of the capture comp
409. red stability and accuracy as the known stable voltage source if Vcc in the user s system meets the through a known resistance see Figure 15 14 A similar approach is used to measure a current A known stable voltage source is again used to charge an RC combination to a threshold value In this case the threshold voltage is created by passing the current to be measured Comparator A 15 17 In Figure 15 13 current is transferred to an input voltage by x R sense The current limit is set for example to 0 25 The current is below the limit as Figure 15 13 Detect a Current Level Using an Internal Reference Level Comparator A in Applications Comparator A Applications Figure 15 14 Measuring a Current Source en R 0 70 90 r o OV 0 41 P2CA0 5 e CAON 0 1 1 o 7 P2CA1 VCC RV R meas CARSEL The equation for the current is vonner R sense s Voc X 1 e 6 AEN t4 0 5 tytto Figure 15 15 Timing for Measuring a Current Source Ve 0 5 Ix R 15 18 gt lt Phase Phase Il Charge Up Charge Up Determine Tau RC Comparator A Applications Figure 15 16 A D Converter for Voltage Sources V meas OV Vcc P2CAO ex 60
410. red when using single conversion mode or repeated conversion of a single channel mode Conversion sequences always use sequential conversion memory registers can start with any conversion memory register and do not necessarily require any EOS bit to be set For example if the CONSEQ bits define the mode of operation to be conversion of a sequence single or repeated the CStartAdd bits point to conversion memory register 14 and no EOS bits are set for any of the conversion memory registers then the conversion memory registers will be used in sequential order 14 15 0 1 2 14 15 0 1 2 etc for each consecutive conversion and the sequence of conversions will continue until stopped by software This is useful for example in an application that must take advantage of the buffering supplied by the conversion memory but requires more than 16 repeated conversions of a single channel In this instance the user should set up each memory control register identically specifying the same channel and reference s for each conversion and all EOS bits must be cleared Once the converter is started it will continue to run until stopped by software 17 5 Conversion Modes Conversion Modes The ADC12 has four conversion modes Single channel single conversion Single channel repeated conversions Sequence of channels single sequence Sequence of channels repeated sequence Each mode is summarized in Table 17 2
411. required baud rate determines the required division factor N BRCOLK baud rate The required division factor N usually has an integer part and a fraction The divider in the baud rate generator realizes the integer portion of the division factor N and the modulator meets the fractional part as closely as possible The factor N is defined as N UxBR 15 mi 0 Where N Target division factor UxBR 16 bit representation of registers UXBR1 and UxBRO Actual bit the frame n Number of bits in the frame mj Data of the actual modulation bit BRCLK BRCLK UxBR 3S m i 0 Baud Rate Considerations 13 7 1 Bit Timing in Transmit Operation The timing for each individual bit in one frame or character is the sum of the actual bit timings as shown in Figure 13 27 The baud rate generation error shown in Figure 13 28 in relation to the required ideal timing is calculated for each individual bit The relevant error information is the error relative to the actual bit not the overall relative error Figure 13 27 5 430 Transmit Bit Timing i Oe te Bea Uf DU UU UU AOU UD DUD amp tof tr tj ts te ts te t TES ar ST D0 eee 06107 j pj Spats ____ 2nd Stop Bit SP 1 Parity Bit PE 1 Address Bit MM 1 8th Data Bit Char 1 Figure 13 28 MSP430 Transmit Bit Timing Error
412. ritten to the high byte of address 0120h Figure 9 4 Writing to WDTCTL 9 4 15 8 7 0 WDTCTL w w w w w w w w rw x w A The Watchdog Timer 9 1 2 Watchdog Timer Interrupt Control Functions The Watchdog Timer WDT uses two bits in the SFRs for interrupt control The WDT interrupt flag WDTIFG located in IFG1 0 initial state is reset The WDT interrupt enable WDTIE located in IE1 0 initial state is reset When using the watchdog mode the WDTIFG flag is used by the reset interrupt service routine to determine if the watchdog caused the device to reset If the flag is set then the Watchdog Timer initiated the reset condition either by timing out or by a security key violation If the flag is cleared then the PUC was caused by a different source See Chapter 3 for more details on the PUC and POR signals When using the Watchdog Timer in interval timer mode the WDTIFG flag is set after the selected time interval and a watchdog interval timer interrupt is requested The interrupt vector address in interval timer mode is different from that in watchdog mode In interval timer mode the WDTIFG flag is reset automatically when the interrupt is serviced The WDTIE bit is used to enable or disable the interrupt from the Watchdog Timer when it is being used in interval timer mode Also the GIE bit enables or disables the interrupt from the Watchdog Timer when it is being used in interval timer mode
413. rocessing together within two addresses of the special function registers SFRs The program flow conditions on interrupt requests can be easily adjusted using the interrupt enable masks The hardware serves the highest priority within the empowered interrupt source 3 4 4 Interrupt Control Bits in Special Function Registers SFRs Most of the interrupt control bits interrupt flags and interrupt enable bits are collected in SFRs under a few addresses as shown in Table 3 1 The SFRs are located in the lower address range and are implemented in byte format SFRs must be accessed using byte instructions Table 3 1 Interrupt Control Bits in SFRs Address 7 000Fh Not yet defined or implemented 0 000Eh 000Dh 0000h 0008h 000A 0009h 0007 o006 00059 oooh 0002h 0001h 0000h Interrupt enable 1 IE1 x The Module Enable bits Interrupt Enable bits and Interrupt flags contained in the SFRs are shown in the following tables System Resets Interrupts and Operating Modes 3 13 Interrupt Processing Table 3 2 MSP340x41x Interrupt Enable Registers 1 and 2 Bit Position IE1 0 IE1 1 IE1 2 IE1 3 IE1 4 IE1 5 IE1 6 IE1 7 IE2 0 IE2 1 IE2 2 IE2 3 IE2 4 IE2 5 IE2 6 IE2 7 Short Form WDTIE OFIE NMIIE ACCVIE BTIE Initial Statet Comments Reset Reset Undefined Undefined Reset Reset Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Und
414. rom zero Setting the TBCLR bit in TBCTL register Setting the TBCLR bit in the TBCTL register clears the timer value and input clock divider value The timer increments upward from zero with the next clock cycle as long as stop mode is not selected with the bits TBR is loaded with 0 When the counter TBR register is loaded with zero with a software instruction the timer increments upward from zero with the next clock cycle as long as stop mode is not selected with the MCx bits Timer B 12 7 Timer Modes 12 3 Timer Modes 12 3 1 Timer Stop Mode Stopping and starting the timer is done simply by changing the mode control bits MCx The value of the timer is not affected When the timer is stopped from up down mode and then restarted in up down mode the timer counts in the same direction as it was counting before it was stopped For example if the timer is in up down mode and counting in the down direction when the bits are reset when they are set back to the up down direction the timer starts counting in the down direction from its previous value If this is not desired in an application the TBCLR bit in the TBCTL register can be used to clear this direction memory feature 12 3 2 Timer Up Mode The up mode is used if the timer period must be different from the TBR max clock cycles of the continuous mode periods The capture compare register TBCCRO data defines the timer period The counter counts up to the
415. rror 0 3 0 7 0 3 0 7 2 pa fie cp The maximum error is calculated for the receive and transmit modes The receive mode error is the accumulated time versus the ideal scanning time in the middle of each bit The transmit error is the accumulated timing error versus the ideal time of the bit period The MSP430 USART peripheral interface allows baud rates nearly as high as the clock rate It has a low error accumulation as a result of modulating the individual bit timing In practice an error margin of 2096 to 3096 supports standard serial communication USART Peripheral Interface UART Mode 13 29 Baud Rate Considerations 13 7 3 Synchronization Error The synchronization error shown in Figure 13 29 results from the asynchronous timing between the URXD pin data signal and the internal clock system The receive signal is synchronized with the BRSCLK clock The BRSCLK clock is sixteen to thirty one times faster than the bit timing as described BRSCLK BRCLK for N lt 1 BRSCLK BRCLK 2 for 20h lt lt BRSCLK BRCLK 4 for 40h lt N lt 7Fh BRSCLK BRCLK 8 for 80h lt N lt FFh BRSCLK BRCLK 16 for 100 lt N lt 1FF BRSCLK BRCLK 32 for 200 lt N lt 3FFh BRSCLK BRCLK 64 for 400 lt N lt 7FFh BRSCLK BRCLK 128 for 800h lt lt FFFh BRSCLK BRCLK 256 for 1000h lt N lt 1FFFh BRSCLK BRCLK 512 for 2000h lt N lt SFFFh BRSCLK BRCLK 1024 for 4000h lt N lt 7FFFh BRSCLK BRCLK 204
416. rs Word Access A 15 Timer B Registers Word Access Continued Bit 4 15 14 13 12 11 10 9 8 Timer B interrupt vector 0 0 0 0 0 0 0 0 TBIV 11Eh ro ro ro ro ro ro ro ro Bit 2 1 0 7 6 5 4 3 Timer B interrupt vector 0 0 0 0 TBIV 0 TBIV 11Eh ro ro ro ro r 0 r 0 r 0 ro TBIV Vector Timer B7 seven capture compare blocks integrated 0 No interrupt pending 2 CCIFG1 flag set interrupt flag of capture compare block 1 4 CCIFG2 flag set interrupt flag of capture compare block 2 CCIFG1 0 6 CCIFG3 flag set interrupt flag of capture compare block 3 CCIFG1 CCIFG2 0 8 CCIFGA flag set interrupt flag of capture compare block 4 CCIFG1 CCIFG2 CCIFG3 0 10 CCIFG5 flag set interrupt flag of capture compare block 5 CCIFG1 CCIFG2 CCIFG3 CCIFG4 0 12 CCIFG6 flag set interrupt flag of capture compare block 6 CCIFG1 CCIFG2 CCIFG3 CCIFG4 CCIFG5 0 14 TBIFG flag set interrupt flag of Timer B register counter CCIFG1 CCIFG2 CCIFG3 CCIFG4 CCIFG5 CCIFG6 0 TBIV Vector Timer_B3 three capture compare blocks integrated 0 No interrupt pending 2 CCIFG1 flag set interrupt flag of capture compare block 1 4 CCIFG2 flag set interrupt flag of capture compare block 2 CCIFG1 0 6 Reserved 8 Reserved 10 Reserved 12 Reserved 14 TBIFG flag set interrupt flag of Timer B register counter CCIFG1 CCIFG2 0 A 18 Appendix B Instruction Set Description The MSP430 core CPU architecture evolved from a reduced instruction set with
417. rt set Oxxxxh Start address of code in the flash to be prg ed Prg source end Oyyyyh End address of code in the flash to be prg ed Prg dest start Set Flash ram load flash routine The code of the program which moves push push mov mov Flash access code write erase starts st r9 10 Prg source start R9 Prg dest start R10 load flash prg mov incd incd cmp jne pop pop ret QR9 0 R10 R10 R9 Prg source end R9 load flash prg 19 r10 label load flash routine load pointer source load pointer destination move a word destination pointer 2 source pointer 2 compare to end of code Flash Memory C 27
418. rt pin is selected to be used as an input to a peripheral module other than the I O port PnSEL x 1 the actual input signal to the peripheral module is a latched representation of the signal at the device pin see Figure 8 4 schematic The latch uses the PnSEL x bit as its enable so while PNSEL x 1 the internal input signal simply follows the signal at the pin However if the PnSEL x bit is reset then the output of the latch and therefore the input to the other peripheral module represents the value of signal at the device pin just prior to the bit being reset 8 3 2 P3 P6 Schematic The pin logic of each individual port signal is shown in Figure 8 4 Figure 8 4 Schematic of Bits Pn x PnSEL x PnDIR x Direction Control From Module PnOUT x Module x OUT PnIN x Module x IN e Output MUX E eA Pad Logic gt Output 5 Enx a fece 4 o Y AL n 3 for Port3 4 for Port P4 5 for Port P5 and 6 for Port P6 X 0 to 7 according to bits O to 7 Digital I O Configuration 8 11 8 12 Chapter 9 Watchdog Timer This chapter discusses the Watchdog Timer Topic Page 9 The Watchdog Timer Ieri 9 2 9 1 The Watchdog Timer 9 1 The Watchdog Timer The primary function of the Watchdog Timer module WDT is to perform a controlled system restart after a software problem o
419. rw 0 Unused STC rw 0 rw 0 SYNC MM rw 0 rw 0 21 rw 21 h 29 rw rw m2 m1 rw rw Unused Undef rw 0 rw 0 Unused STC rw 0 rw 0 SYNC MM rw 0 rw 0 2 A Peripheral File Map 3 o Undef rw 0 TXEPT 2 Undef rw 0 TXEPT rw 1 SWRST rw 1 A 7 ADC12 Registers Byte and Word Access A 10 ADC12 Registers Byte and Word Access Bit ADC12MCTL15t 008Fh ADC12MCTL14t 008Eh ADC12MCTL13t 008Dh ADC12MCTL12t 008Ch ADC12MCTL11t 008Bh ADC12MCTL10t 008Ah ADC12MCTL9t 0089h ADC12MCTL8t 0088h ADC12MCTL7t 0087h ADC12MCTL6t 0086h ADC12MCTL5t 0085h ADC12MCTL4t 0084h ADC12MCTL3t 0083h ADC12MCTLat 0082h ADC12MCTL1it 0081h ADC12MCTLot 0080h A 8 7 EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 rw 0 rw rw 0 rw rw 0 rw 0 rw 0 EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 rw 0 rw rw 0 rw rw 0 rw 0 rw 0 EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 rw 0 rw rw 0 rw rw 0 rw 0 rw 0 0 0 0 0 EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 rw 0 rw rw 0 rw rw 0 rw 0 rw 0 EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 rw 0 rw rw 0 rw rw 0 rw 0 rw 0 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EOS Sref 2 Sref 1 Sref 0 INCH 3 INCH 2 INCH 1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 EOS Sref 2 Sref 1 Sref 0 INCH 3 IN
420. rw 0 rw 0 rw 0 rw 0 rw 0 FLL control 1 FLL CTL1 M 26 25 24 23 22 21 20 0054h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 rw 1 Frequency control SCFQCTL M 26 25 24 23 22 21 20 0052h rw 0 rw 0 rw 0 rw 1 rw 1 rw 1 rw 1 rw 1 Frequency integrator SCFI1 29 28 27 26 25 24 23 22 0051h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Frequency integrator SCFIO D D 8 FN 4 FN3 FN 2 21 20 0050h rw 0 rw 1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 A 6 SVS Register Byte Access Bit 4 7 6 5 4 3 2 1 0 SVSCTL 0053h A 7 Comparator A Registers Byte Access Bit 4 7 6 5 4 3 2 1 0 Comparator_A Port Disable CAPD CAPD 7 CAPD 6 CAPD 5 CAPD 4 CAPD 3 CAPD 2 CAPD 1 0 005Bh rw 0 rw 0 rw 0 rw 0 rw 0 mw 0 rmw 0 rw 0 Comparator A control reg 2 CACTL2 CACTL2 7 CACTL2 6 CACTL2 5 CACTL2 4 CA1 CAO CAF CAOUT 005Ah rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 Comparator A control reg 1 CACTL1 CAEX CARSEL CAREF1 CAREFO CAON CAIES CAIE CAIFG 0059h rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Peripheral File Map A 5 USARTO USART1 UART Mode Sync 0 Byte Access 8 USARTO USART1 UART Mode Sync 0 Byte Access Bit USART1 Transmit buffer U1 TXBUF 07Fh USART1 Receive buffer U1 RXBUF 07Eh USART1 Baud rate U1BR1 07Dh USART1 Baud rate U1BRO 07Ch USART1 Modulation control U1MCTL 07Bh USART1 Receive control U1RCTL 07Ah USART1 Transmit control UTTC
421. rw 1 20 rw 20 r 20 rw rw RXERR rw 0 TXEPT rw 1 SWRST rw 1 USARTO USART1 SPI Mode Sync 1 Byte Access A 9 USARTO USART1 SPI Mode Sync 1 Byte Access Bit USART1 Transmit buffer U1 TXBUF 07Fh USART1 Receive buffer U1 RXBUF 07Eh USART1 Baud rate U1BR1 07Dh USART1 Baud rate U1BRO 07Ch USART1 Modulation control U1MCTL 07Bh USART1 Receive control U1RCTL 07Ah USART1 Transmit control U1TCTL 079h USART1 USART control U1CTL 078h USARTO Transmit buffer UOTXBUF 077h USARTO Receive buffer UURXBUF 076h USARTO Baud rate UOBR1 075h USARTO Baud rate UOBRO 074h USARTO Modulation control UOMCTL 073h USARTO Receive control UORCTL 072h USARTO Transmit control UOTCTL 071h USARTO USART control UOCTL 070h 7 rw FE rw 0 CKPH rw 0 Unused rw 0 6 gt 8 Undef rw 0 CKPL rw 0 Unused rw 0 26 rw 26 r 3 o CKPL rw 0 Unused rw 0 o 5 rw 0 SSEL1 rw 0 Unused rw 0 m5 rw 23 gt a rw 0 SSEL1 rw 0 Unused rw 0 4 5 m4 rw Undef rw 0 SSELO rw 0 CHAR rw 0 24 rw 24 r 3 gt Undef rw 0 SSELO rw 0 CHAR rw 0 3 0 2 Unused rw 0 Unused rw 0 Listen rw 0 2 z Unused rw 0 Unused rw 0 Listen rw 0 A n gt s rw m1 rw rw Unused Undef rw 0
422. ry if MEras 1 Eras 0 XOR FXKEY Lock amp FCTL3 Change Lock bit to 1 LOCK 1 The erase bit Eras is automatically reset Restore or Enable Required Enable those interrupt sources that should be accepted Interrupt Sources and Watchdog C 5 3 6 Code for Write Program Erase and Mass Erase LOCK 0 1 or MEras 1 Dummy Write to Flash Address in the Target Segment Software that controls write erase or mass erase can be located in the flash memory module and copied during execution into RAM In this case the code should be written position independent and should be loaded for instance to RAM before itis used The algorithm runs in RAM during the programming sequence to avoid conflict when the flash memory is written or erased 26 Flash Memory Access JTAG and Software In the following example a subroutine moves the programming code sequence to another memory such as RAM Start of Subroutine Load Flash Routine Source Start Address of The Code Sequence R7 Destination Start Address of The Code Sequence R10 Move One Word R7 R10 Increment Source and Destination Pointer in R7 and R10 End of Source Code End of Subroutine RET Definitions used in Subroutine Move programming code sequence into RAM load flash routine Flash ram set 0222h Start address of flash program in the RAM program in the RAM Prg source sta
423. rystal with maximum errors of 11 percent Standard UARTs even with the worst maximum error 714 6 percent can obtain maximum baud rates of 75 baud USART Peripheral Interface UART Mode 13 25 Baud Rate Considerations 13 6 3 Support of Multiprocessor Modes for Reduced Use of MSP430 Resources Communication systems can use multiprocessor modes with multiple character idle line or address bit protocols The first character can be a target address a message identifier or can have another definition This character is interpreted by the software and if it is of any significance to the application the succeeding characters are collected and further activities are defined An insignificant first character would stop activity for the processing device This application is supported by the wake up interrupt feature in the receive operation and sends wake up conditions along with a transmission Avoiding activity on insignificant characters reduces consumption of MSP430 resources and the system can remain in the most efficient power conserving mode In addition to the multiprocessor modes rejecting erroneous characters saves MSP430 resources This practice prevents interrupt handling of the erroneous characters The processor waits in the most efficient power conserving mode until a character is processed 13 7 Baud Rate Considerations 13 26 The MSP430 baud rate generator uses a divider and a modulator A given crystal frequency and a
424. s i o 1 9 ES target to ty tg tg to 111 terror Mark URXD ST DO D7 PA 0 e t to Even small errors per bit relative errors can result large cumulative errors They must be considered to be cumulative not relative The error of an individual bit can be calculated by n i n i x tactual 2 AR x 10096 baud rate Error baud rate y i41 x UxBR m i 1 x 100 BRCLK 0 With baud rate Required baud rate BRCLK frequency selected for UCLK ACLK or MCLK i Ofor the start bit 1 for the data bit DO and so on UxBR Division factor in registers UxBR1 and UxBRO USART Peripheral Interface UART Mode 13 27 Baud Rate Considerations Example 13 3 Error Example for 2400 Baud 13 28 The following data are assumed Baud rate 2400 BRCLK 32 768 Hz UxBR 13 since the ideal division factor is 13 67 m 6Bh 7 0 m6 1 m5 1 4 0 m3z1 m2 0 m1 1 and m0 1 The LSB m0 of the modulation register is used first Start bit Error a x 0 1 x UxBR n2 x 100 2 54 Data bit DO Error Data bit D1 Error 96 Data bit D2 Error 96 Data bit D3 Error 96 Data bit D4 Error 96 Data bit D5 Error 96 Data bit D6 Error 96 Data bit D7 Error 96 Parity bit Error Stop
425. s S O47w9OrxcC OON Control and Status Registers 13 5 4 Baud Rate Select and Modulation Control Registers The baud rate generator uses the content of the baud rate select registers UxBRO and UxBR1 shown in Figure 13 19 with the modulation control register to generate the serial data stream bit timing Figure 13 19 USART Baud Rate Select Register 7 0 UOBRO 074h rw rw rw rw rw rw rw rw 7 0 UOBR1 075h wanes ep epe n e rw rw rw rw rw rw rw rw BRCLK Baud rate __ with UxBR UxBR1 UxBRO UxBR gt mi The baud rate control register range is 3 lt UxBR lt OFFFFh Note Unpredictable receive and transmission occur if UXBR 3 The modulation control register shown in Figure 13 20 ensures propertiming generation with the UXBRO and UxBR1 even with crystal frequencies that are not integer multiples of the required baud rate Figure 13 20 USART Modulation Control Register 7 0 UOMCTL 073h U1MCTL 07Bh m7 m6 m5 m4 m3 m2 m1 rw rw rw rw rw rw rw rw The timing of the running bit is expanded by one clock cycle of the baud rate divider input clock if bit is set Each time a bit is received or transmitted the next bit in the modulation control register determines the present bit timing The first bit time in the protocol the start bit time is determined by UxBR plus the next bit is determined by UxBR plus m1 and so on The modulation sequence is m0 m1 m2 m3 m
426. s do not use the same clock source the baud rate is generated locally 13 3 1 Asynchronous Frame Format The asynchronous frame format shown in Figure 13 3 consists of a start bit seven or eight data bits an even odd no parity bit an address bit in address bit mode and one or two stop bits The bit period is defined by the selected clock source and the data in the baud rate registers Figure 13 3 Asynchronous Frame Format Mark ST 06 5 DIR 2nd Stop Bit SP 1 Parity Bit PENA 1 Address Bit MM 1 Optional Bit Condition 8th Data Bit CHAR 1 The receive RX operation is initiated by the receipt of a valid start bit It begins with a negative edge at URXD followed by the taking of a majority vote from three samples where two of the samples must be zero These samples occur at 2 n 2 and n 2 X of the BRCLK periods following the negative edge This sequence provides false start bit rejection and also locates the center of the bits in the frame where the bits can be read on a majority basis The timing of X is 1 32 to 1 63 times that of the BRCLK depending on the division rate of the baud rate generator and provides complete coverage of at least two BRCLK periods Figure 13 4 shows an asynchronous bit format Figure 13 4 Asynchronous Bit Format Example for n or n 1 Clock Periods Falling Edge Majority Vote on UEXD Taken From Indicates Start bit URXD Data Line T
427. s in the range to be erased Flash Memory Data Structure and Operation The dummy write starts the erase cycle An example of dummy write is CLR amp 0 012 Note that a dummy write is ignored in a segment where the selected operation can not be executed successfully An example of such a situation can take place when Segment 1 is to be erased the control bits are set properly but the dummy write is sent to the information memory No flag indicates this unsuccessful erase situation Figure C 7 Basic Flash EEPROM Module Timing During the Erase Cycle 4 7 101 3 h31D LE 4 gt lt gt lt gt Erase Operation Active Generate Remove Erase Voltage Entire Erase Cycle Timing Prase Voltage amp Time of Increased Current Consumption From Supply BUSY Mass Erase 5296 fx Segment Erase 4817 fx The erase cycle completes successfully when none of the following restrictions is violated The selected clock source is available until the cycle is completed The predivider should not be modified during the operation No further access to the flash memory module is performed while BUSY is set B No read of data from this block B write into this block B No further erase of this block An access will result in setting the KEYV bit and requesting an NMI interrupt The NMI interrupt routine should handle such violations The supply volt
428. s of subroutine calls and interrupts It uses a predecrement postincrement scheme The advantage of this scheme is that the item on the top of the stack is available The SP can be used by the user software PUSH and POP instructions but the user should remember that the CPU also uses the SP Figure 5 2 shows the system SP bits Figure 5 2 System Stack Pointer 5 2 15 1 0 System Stack Pointer Bits 15 to 1 ES CPU Registers 5 1 2 1 Examples for System SP Addressing Refer to Figure 5 4 OV SP R4 H OV QSP R5 OV 2 SP R6 OV R7 0 SP OV R8 4 SP PUSH R12 A POP R12 OV SP R5 E SP gt R4 Item I3 TOS gt R5 Item I2 gt R6 Overwrite TOS with R7 Modify item I1 Store R12 in address Oxxxh 6 SP points to same address Restore R12 from address Oxxxh 6 SP points to Oxxxh 4 Item I3 gt R5 popped from stack POP instruction Same as Figure 5 3 shows stack usage Figure 5 3 Stack Usage Address Oxxxh Oxxxh 2 Oxxxh 4 Oxxxh 6 Oxxxh 8 5 1 2 2 Special Cases PUSH SP and POP SP The special cases of using the SP as an argument to the PUSH and POP instructions are described below Figure 5 4 PUSH SP and POP SP PUSH SP SPolg SP4 SP4 The stack pointer is changed after a PUSH SP instruction After the sequence PUSH SP SP1 POP SP SP2 POP SP SP2 SP4 The stack pointer is not changed after a PUSH S
429. scillator fault LFOF XT1OF XT2OF or DCOF sets the oscillator fault interrupt flag OFIFG in the interrupt flag register 1 IFG1 permanently as long as the fault condition is valid If the oscillator fault interrupt enable bit OFIE is set by user software in the interrupt enable register 1 IE1 and an oscillator fault occurs a nonmaskable interrupt NMI is generated When the interrupt is granted the OFIE is reset automatically by hardware user software must reset OFIFG The NMI interrupt has three sources User software must interrogate the OFIFG bit to determine if the NMI was generated by an oscillator fault The individual fault bits LFOF XT10OF XT2OF and DCOF are used to further identify the oscillator fault conditions Note MCLK SMCLK is active even at the lowest DCO tap The MCLK SMCLK signal is available for the CPU to execute code and service an NMI 7 5 FLL Operating Modes Control bits SCGO SCG1 OscOff and CPUOff in the status register configure the MSP430x4xx operating modes as discussed in Chapter 3 System Resets Interrupts and Operating Modes 7 5 1 Starting From Power Up Clear PUC On avalid PUC SCFQCTL 31 SCFIO 40h Oh and SCGO SCG1 OscOff and CPUOff in the status register are reset The FLL is fully operational and will adjust the DCO until MCLK SMCLK 3141 x ACLK When a 32 768 Hz watch crystal is used for ACLK MCLK SMCLK will stabilize to 1 048576 MHz Because the DCO
430. se Set if dst contained OFEh or OFFh reset otherwise V Set if dst contained O7FFEh or 07FFFh reset otherwise Set if dst contained 07Eh or 07Fh reset otherwise OscOff CPUOff and GIE are not affected The item on the top of the stack TOS is removed without using a register PUSH R5 R5 is the result of a calculation which is stored in the system stack INCD SP Remove TOS by double increment from stack Do not use INCD B SP is a word aligned register RET The byte on the top of the stack is incremented by two INCD B 0 SP Byte on TOS is increment by two Instruction Set Description B 31 Instruction Set Overview INVLW INV B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Example B 32 Invert destination Invert destination INV dst INV B dst NOT dst dst XOR 0OFFFFh dst XOR B 0FFh dst The destination operand is inverted The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise Set if result is not zero reset otherwise NOT Zero Set if result is not zero reset otherwise NOT Zero V Set if initial destination operand was negative otherwise reset OscOff CPUOff and GIE are not affected Content of R5 is negated twos complement MOV 00 5 R5 000AEh INV R5 Invert R5 R5 OFF51h
431. sed In these situations flash control registers FCTL1 FCTL2 and FCTL3 need to be set up properly to ensure correct write or erase C 6 Flash Memory Data Structure and Operation operation Once these registers are set up and write or erase is started the timing generator controls the entire operation and applies all signals internally If the BUSY control signal is set it indicates that the timing generator is active and a write or erase cycle is active The block write mode also uses a second control bit WAIT There are three basic parts to a write or erase cycle preparation of program erase voltage control timing for the program or erase operation and the switch off sequence of the program erase voltage Once a write or erase function is started the software should not access the flash memory until the BUSY signal indicates with 0 that it can be accessed again In critical situations where flash programming or erase should be immediately stopped the emergency exit bit EMEX can be set The current operation may be incomplete or the result may be incorrect Different clock sources ACLK MCLK or SMCLK can be selected to clock the timing generator The connected clock sources applied to the timing generator may vary with the device see data sheet for details The clock source selected should be active from the beginning of write or erase until the operation is fully completed Figure C 6 Block Diagram of the Timing Generator in t
432. sion However some bits that are necessary for proper completion of active conversions and interrupt enable bits can be modified independently of ENC The user must use caution when modifying theses bits to ensure an active conversion is not corrupted or to not use corrupted data To avoid corrupting any active conversions stop the conversion wait for the busy bit to be reset reset the ENC bit then modify the control bits ADC12 Control Registers 17 8 2 Conversion Memory Registers ADC12MEMx ADC12MEM 0140h 015Eh ADC12MEMO to ADC12MEM 15 bits There are sixteen conversion memory registers ADC12MEMXx as follows Conversion results The 12 bit conversion results are right justified and 0 15 the four MSBs are always read as 0 The ADC120OV interrupt flag will be set in time to indicate that a overflow situation occurred Software can detect it if it reads the conversion result and then tests for overflow condition The corresponding interrupt flag is reset if ADC12MEMXx is accessed Warning SOFTWARE WRITE TO REGISTER ADC12MEMx Typically software should not write to the conversion result registers ADC12MEMx If software writes to one of these registers while the ADC12 is attempting to write to the same register the data in the register will be unpredictable if software ensures that it is writing to a conversion result register that is not being accessed by the ADC12 then the write completes normally a
433. smitted If the transmission is completed any further write operation to the transmitter buffer does not transmit When the UxTXBUF is ready any pending request for transmission remains which results in an immediate start of transmission when USPIIE is set and the transmitter is empty A low state on the STE signal removes the active master four pin mode from the bus It also indicates that another master is requesting the active master function 14 4 2 1 Receive Transmit Enable MSP430 as Master Figure 14 10 shows the transmit enable activity when the MSP430 is master Figure 14 10 State Diagram of Transmit Enable MSP430 as Master No Data Written to Transfer Buffer USPIIE 1 Data Written to Transmit Buffer USPIIE 0 Not Completed USPIIE 1 USPIIE 1 Idle State Transmitter Enabled Handle Interrupt Conditions Transmission Active Transmit Disable Character Transmitted PUC USPIIE 0 And Last Buffer Entry Is Transmitted USART Peripheral Interface SPI Mode 14 11 Interrupt and Control Functions 14 4 2 2 Receive Transmit Enable MSP430 is Slave Figure 14 11 shows the receive transmit enable bit activity when the MSP430 is slave Figure 14 11 State Diagram of Transmit Enable MSP430 as Slave 14 12 USPIIE 0 No Clock at UCLK Not Completed USPIIE 1 USPIIE 1 Idle State Transmitter Enab
434. source during normal operation may result in an incorrect interval The timer should be halted before changing the clock source ee 9 1 3 3 Operation in Low Power Modes 9 6 The MSP430 devices have several low power modes Different clock signals are available in different low power modes The requirements of the user s application and the type of clocking circuit on the MSP430 device determine how the Watchdog Timer and clocking signals should be configured Review the device data sheet and clock system chapter to determine the clocking circuit clock signals and low power modes available For example the WDT should not be configured in watchdog mode with SMCLK as its clock source if the user wants to use low power mode 3 because SMCLK is not active in therefore the WDT would not function properly The WDT hold condition can also be used to support low power operation The hold condition can be used in conjunction with low power modes when needed The Watchdog Timer 9 1 3 4 Software Example The following example illustrates the watchdog reset operation After RESET or power up the WDTCTL register and WDTCNT are cleared and the initial operating conditions are watchdog mode with a time interval of 32 ms As long as watchdog mode is selected watchdog reset has to be done periodically through an instruction e g MOV WDTPW WDTCNTCL amp WDTCTL To change to timer mode and a time interval
435. spectively Table 8 1 Port P1 Registers Short Register Register Form Type Address Initial State Input Read only 0200 Output P1OUT Read write 0211 Unchanged Direction P1DIR Read write 0221 Reset Interrupt flags P1IFG Read write 0238 Reset Interrupt edge select P1IES Read write 0241 Unchanged Interrupt enable 1 Read write 0251 Reset Function select P1SEL Read write 0261 Reset Table 8 2 Port P2 Registers Short Register Register Form Type Address Initial State Input P2IN Read only 028h Output P2OUT Read write 0291 Unchanged Direction P2DIR Read write 2 Reset Interrupt flags P2IFG Read write O2Bh Reset Interrupt edge select P2IES Read write 02Ch Unchanged Interrupt enable P2IE Read write 02Dh Reset Function select P2SEL Read write O2Eh Reset These registers contain eight bits and should be accessed using byte instructions in absolute address mode 8 2 1 1 Input Registers P2IN Both Input registers are read only registers that reflect the signals at the I O pins Note Writing to Read Only Registers P1IN P2IN Writing to these read only registers results in increased current consumption while the write attempt is active 8 4 Ports P1 P2 8 2 1 2 Output Registers P1OUT P2OUT Each output register shows the information of the output buffer The output buffer can be modified by all instructions that write to a destination If read the contents of the output buffer ar
436. ss Character Received L Will Set Flag URXIFG J or unie m n a m o Break Detected URXSE IRQA URXIFG is reset by a system reset PUC signal or with a software reset SWRST URXIFG is reset automatically if the interrupt is served URXSE 0 or the receive buffer UxRXBUF is read A set receive interrupt flag URXIFG indicates that an interrupt event is waiting to be served A set receive interrupt enable bit URXIE enables serving a waiting interrupt request Both the receive interrupt flag URXIFG and the receive interrupt enable bit URXIE are reset with the PUC signal and a SWRST Signal URXIFG can be accessed by the software whereas signal URXS cannot When both interrupt events character receive action and receive start detection are enabled by the software the flag URXIFG indicates that a character was received but the start detect interrupt was not Because the interrupt software handler for the receive start detection resets the URXSE bit this clears the URXS bit and prevents further interrupt requests from URXS The URXIFG should already be reset since no set condition was active during URXIFG latch time USART Peripheral Interface UART Mode 13 13 Interrupt and Enable Functions 13 4 4 USART Transmit Interrupt Operation In the transmit interrupt operation shown in Figure 13 15 the transmit interrupt flag UTXIFG is set by the transmitter to indicate that the transmitter buffer UXTXBUF is ready to accept another characte
437. state is the logical state after the PUC signal 3 14 Interrupt Processing Table 3 4 MSP430x44x Interrupt Enable Registers 1 and 2 Bit Position IE1 0 IE1 1 IE1 2 IE1 3 IE1 4 IE1 5 IE1 6 IE1 7 IE2 0 IE2 1 IE2 2 IE2 3 IE2 4 IE2 5 IE2 6 IE2 7 Short Form WDTIE OFIE NMIIE ACCVIE URXIEO UTXIEO URXIE1 UTXIE1 BTIE Initial Statet Comments Reset Reset Undefined Undefined Reset Reset Reset Reset Undefined Undefined Undefined Undefined Reset Reset Undefined Reset Watchdog Timer enable signal Inactive if watchdog mode is selected Active if Watchdog Timer is configured as general purpose timer Oscillator fault interrupt enable Not implemented Not implemented NMI interrupt enable Flash access violation enable USARTO receive interrupt enable USARTO transmit interrupt enable Not implemented Not implemented Not implemented Not implemented USART1 receive interrupt enable USART1 transmit interrupt enable Not implemented Basic timer interrupt enable signal t The initial state is the logical state after the PUC signal Table 3 5 MSP430x41x Interupt Flag Registers 1 and 2 Bit Position IFG1 0 IFG1 1 IFG1 2 IFG1 3 IFG1 4 IFG1 5 IFG1 6 IFG1 7 IFG2 0 IFG2 1 IFG2 2 IFG2 3 IFG2 4 IFG2 5 IFG2 6 IFG2 7 Short Form WDTIFG OFIFG NMIIFG BTIFG Initial State Set Or reset Set Undefined Undefined Reset Undefined Undefined Undefined Undefined Undefin
438. subroutine TOS gt PC SP 2 gt SP Rotate left arithmetically Rotate left through carry MSB MSB LSB gt C 2 gt LSB gt Subtract carry from destination Set carry bit Set negative bit Set zero bit dst not src 1 dst dst not src gt dst swap bytes Bit7 Bit8 Bit15 Test destination src xor dst dst V N 2 c M Note Asterisked Instructions Asterisked instructions are emulated They are replaced with core instructions by the assembler LLLLLLL D AA Instruction Set Description B 3 Instruction Set Overview B 1 1 Instruction Formats The following sections describe the instruction formats B 1 1 1 Double Operand Instructions Core Instructions The instruction format using double operands as shown in Figure 1 consists of four main fields to form a 16 bit code L operational code field four bits op code _j source field six bits source register As _j byte operation identifier one bit BW destination field five bits dest register Ad The source field is composed of two addressing bits and a four bit register number 0 15 The destination field is composed of one addressing bit and a four bit regist
439. sult gt LSB 014Eh ro ro ro All conversion result bits of type rw ro i 0152h 0 ADC12MEM4 Unused Unused Unused Unused MSB lt _ Conversion Result gt LSB 0148h ro ro ro All conversion result bits of type rw ADC12MEMS Unused Unused Unused Unused MSB lt _ Conversion Result gt LSB 0146h ro ro ro r All conversion result bits of type rw ADC12MEM2 Unused Unused Unused Unused MSB lt _ Conversion Result gt LSB 0144h ro ro ro r All conversion result bits of type rw ADC12MEM 1 Unused Unused Unused Unused MSB Conversion Result gt LSB 0142h ro ro ro r All conversion result bits of type rw ADC12MEMO Unused Unused Unused Unused MSB lt _ Conversion Result gt LSB 0140h ro ro ro ro All conversion result bits of type rw n ro ro ro ADC12MEM6 Unused Unused Unused Unused MSB Conversion Result LSB 014Ch ro ro ro All conversion result bits of type rw ADC12MEM5 Unused Unused Unused Unused MSB Conversion Result LSB 014Ah ro ro ro ro All conversion result bits of type rw ro 0 0 0 Peripheral File Map A 9 ADC12 Registers Byte and Word Access 9 12 Registers Byte Word Access Continued Bit 15 14 0 9 11 ADC12IE 12 15 ADC12IE 14 A
440. sults may be unpredictable Inthis case the timer clock is asynchronous to the CPU clock MCLK and critical race conditions exist SMCLK should be treated asynchronous if it is not MCLK 11 5 3 Capture Compare Control Register CCTLx Each capture compare block has its own control word CCTLx shown in Figure 11 29 The POR signal resets all bits of CCTLx the PUC signal does not affect these bits Figure 11 29 Capture Compare Control Register CCTLx 15 CCTLx Capture Input rw 0 rw 0 rw 0 rw O rw 0 rw 0 r 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw O rw 0 rw O Timer A 11 25 Timer A Registers Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bits 5 to 7 11 26 Capture compare interrupt flag CCIFGx Capture mode If set it indicates that a timer value was captured in the CCRx register Compare mode If set it indicates that a timer value was equal to the data in the CCRx register CCIFGO flag CCIFGO is automatically reset when the interrupt request is accepted CCIFG1 to CCIFG2 flags The flag that caused the interrupt is automatically reset after the TAIV word is accessed If the TAIV register is not accessed the flags must be reset with software No interrupt is generated if the corresponding interrupt enable bit is reset but the flag will be set In this scenario the flag must be reset by the software Setting the CCIFGx flag with software will request an interrupt if the
441. synchronous Operation 13 4 13 3 1 Asynchronous Frame Format 13 4 13 3 2 Baud Rate Generation in Asynchronous Communication Format 13 5 13 3 3 Asynchronous Communication Formats 13 7 13 3 4 ldle Line Multiprocessor Format 13 7 13 3 5 Address Bit Multiprocessor Format 13 9 13 4 Interrupt and Enable Functions 13 11 13 4 1 USART Receive Enable Bit 13 11 13 4 2 USART Transmit Enable 13 12 13 4 8 USART Receive Interrupt Operation 13 13 13 4 4 USART Transmit Interrupt Operation 13 14 13 5 Control and Status Registers 00 0 cece cece eens 13 15 13 5 1 USART Control Register UOCTL UTCTL 13 16 13 5 2 Transmit Control Register UOTCTL U1TCTL 13 18 13 5 3 Receiver Control Register UORCTL UTRCTL 13 19 13 5 4 Baud Rate Select and Modulation Control Registers 13 21 13 5 5 Receive Data Buffer UORXBUF UTRXBUF 13 22 13 5 6 Transmit Data Buffer UOTXBUF U1TXBUF 13 22 viii Contents 13 6 Uti
442. t OFFh 1 CMP 0 451 0 dst The destination operand is compared with zero The status bits are set accord ing to the result The destination is not affected N Set if destination is negative reset if positive Z Set if destination contains zero reset otherwise C Set V Reset OscOff CPUOff and GIE are not affected R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TST R7 Test R7 JN R7NEG R7 is negative JZ R7ZERO R7 is zero R7POS a R7 is positive but not zero R7NEG R7 is negative R7ZERO R7 is zero The low byte of R7 is tested If itis negative continue at R7NEG if it is positive but not zero continue at R7POS TST B R7 Test low byte of R7 JN R7NEG Low byte of R7 is negative JZ R7ZERO Low byte of R7 is zero R7POS Low byte of R7 is positive but not zero R7NEG Low byte of R7 is negative R7ZERO Low byte of R7 is zero XOR W XOR B Syntax Operation Description Status Bits Mode Bits Example Example Example Instruction Set Overview Exclusive OR of source with destination Exclusive OR of source with destination XOR src dst or XOR W src dst XOR B src dst src XOR dst dst The source and destination operands are exclusive ORed The result is placed into the destination The source operand is not affected N Set if result MSB is set reset if not set Z
443. t TBR may the counter operates as if it were configured for continuous mode It will not count down from to zero LLLLLL Figure 12 12 Timer Up Down Mode TBCLO Oh The up down mode also supports applications that require dead times between output signals For example to avoid overload conditions two outputs driving an H bridge must never be in a high state simultaneously In the following example see Figure 12 13 the tgeag is tdead ttimer X TBCL1 TBCL3 With tgeag Time during which both outputs need to be inactive ttimer Cycle time of the timer clock TBCLx Content of compare latch x SS ODO ee Note The dead time is ensured by the ability to simultaneously load the compare latches Figure 12 13 Output Unit in Up Down Mode 11 TBCLO TBCL1 TBCL3 Oh b X b Dead Time Output Mode 6 PWM Toggle Set Output Mode 2 PWM Toggle Reset TBIFG EQU1 EQU1 TBIFG EQU1 EQU1 Interrupt Events 12 12 EQU3 EQUO EQU3 EQU3 EQUO EQUS Timer Modes The count direction is always latched with a flip flop Figure 12 14 This is useful because it allows the user to stop the timer and then restart it in the same direction it was counting before it was stopped For example if the timer was counting down when the MCx bits were reset then it will continue co
444. t a branch is taken to label TOM BIT B 8 R8 JC TOM A serial communication receive bit RCV is tested Because the carry bit is equal to the state of the tested bit while using the BIT instruction to test a single bit the carry bit is used by the subsequent instruction the read information is shifted into register RECBUF Serial communication with LSB is shifted first XXXX XXXX XXXX BIT B RCV RCCTL Bit info into carry RRC RECBUF Carry gt MSB of RECBUF CXXX XXXX ds repeat previous two instructions m 8 times CCCC CCCC MSB LSB Serial communication with MSB is shifted first BIT B RCV RCCTL Bit info into carry RLC B RECBUF Carry gt LSB of RECBUF XXXC SS repeat previous two instructions uns 8 times CCCC CCCC sl LSB MSB Instruction Set Description B 15 Instruction Set Overview BR BRANCH Syntax Operation Emulation Description Status Bits Example Branch to destination BR dst dst PC MOV dst PC An unconditional branch is taken to an address anywhere in the 64K address space All source addressing modes can be used The branch instruction is a word instruction Status bits are not affected Examples for all addressing modes are given BR EXEC Branch to label EXEC or direct branch e g 0A4h Core instruction MOV PC PC BR EXEC Branch to the address contained in EXEC Core instruction MOV X PC PC Ind
445. t can be saved on the stack using the PUSH instruction and can be restored after completing another multiplication operation using the POP instruction However this operation takes additional code and cycles in the interrupt routine You can avoid this by making an entire multiplication routine uninterruptible by disabling any interrupt DINT before entering the multiplication routine and by enabling interrupts EINT after the multiplication routine is completed The negative aspect of this method is that the critical interrupt latency is increased drastically for events that occur during this period 6 5 2 3 General Recommendation 6 8 In general one should avoid a hardware multiplication operation within an interrupt routine when a hardware multiplication is already used in the main program This will depend upon the application specific software applied libraries and other included software The methods previously discussed have some negative implications therefore the best practice is to keep interrupt routines as short as possible Hardware Multiplier Software Restrictions 6 5 3 Hardware Multiplier Software Restrictions MACS The multiplier does not automatically detect underflow or overflow in the MACS mode An overflow occurs when the sum of the accumulator register and the result of the signed multiplication exceed the maximum binary range The binary range of the accumulator for positive numbers is 0 to 231 1 7FFF
446. t line drives three segments Figure 16 3 Three MUX Wave Form Drive COM2 VDD V2 2 3VDD COMO Ai sob frame 39 GND m VDD V2 2 3VDD COM1 Scat pss V4 1 3VDD GND VDD COMO V2 2 3VDD ppc eroe E GND VDD V2 2 aVDD GND VDD e se GND d SP1 SP3 VDD SP2 SP3 GND SP Segment Pin VDD Resulting Voltage for Segment e 5 1 H 37H CE EP ov Segment Is Off VDD VDD Resulting Voltage for Segment COMO SP2 OV Segment Is On VDD Liquid Crystal Display Drive 16 5 LCD Drive Basics With 4 MUX LCDs each segment pin drives four segments Figure 16 4 Four MUX Wave Form Drive COMS COMO COM2 oras ewe riri S nan SP1 SP Segment Pin Segment e COM1 SP1 Segment Is Off inm Resulting Voltage for Segment c COM1 SP2 Segment Is On 16 6 VDD V2 2 3 VDD V4 1 3 VDD GND VDD V2 2 3 VDD V4 1 3 VDD GND VDD V2 2 3 VDD V4 1 3 VDD GND VDD V2 2 3 VDD V4 1 3 VDD GND VDD V2 2 3 VDD V4 1 3 VDD GND VDD V2 2 3 VDD V4 1 3 VDD GND VDD ov VDD VDD ov VDD LCD Controller Driver 16 2 LCD Controller Driver The LCD controller driver peripheral shown in Figure 16 5 contains all the functional blocks and generates the segment and common signals required to drive an LCD Figure 16 5 LCD Con
447. t s Hee 1 4 L UTXIFG Ed Slave Interrupt Shift Data Out Shift Data In pepe Figure 14 5 Data Transfer Cycle MSB LSB MSB LSB CN 100110 ojoj S BOh gt UxTXBUF 1 0110000 0101 1000 A 98h DSR C F UxRXBUF M C D DSR from Initial State CN 0 1 0 1 0 1 ofo 5 G E8h UxTXBUF 00101010 M DSR T In 7 bit mode the MSB of RXBUF is always read as 0 S Slave M Master E 54h DSR UXxRXBUF 14 6 Synchronous Operation Figure 14 6 illustrates the USART module functioning as a slave in a three or four pin SPI configuration Figure 14 6 MSP430 USART as Slave in Three Pin or Four Pin Configuration MASTER MSB COMMON SPI SPI Receive Buffer Receive Buffer UXRXBUF Receive Shift Register MSP430 USART 14 3 1 Master SPI Mode The master mode is selected when the master mode bit MM in control register UXCTL is set The USART module controls the serial communication network by providing UCLK at the UCLK pin Data is output on the SIMO pin during the first UCLK period and latched from the SOMI pin in the middle of the corresponding UCLK period The data written to the transmit buffer UXTXBUF is moved to the transmit shift register as soon as the shift register is empty This initiates the data transf
448. ted to the transmit shift register For example if software writes a byte to the transmit buffer and then resets UTXE the byte written to the transmit buffer will be transmitted and may be modified or overwritten until it is transferred into the transmit shift register However after the byte is transferred to the transmit shift register any subsequent writes to UxTXBUF while UTXE is reset will not result in transmission but UXTXBUF will be updated with the new value Figure 13 13 State Diagram of Transmitter Enable 18 12 Transmit Disable UTXE 0 UTXE 0 And Last Buffer No Data Written to Transmit Buffer ud Completed UTXE 1 Data Written to Idle State Transmitter Enabled Handle Interrupt Conditions Character Transmitted Entry Is Transmitted When UTXE is reset and the current transmission is completed new data written to the transmit buffer will not be transmitted Once the UTXE bit is set the data in the transmit buffer are immediately loaded into the transmit shift register and character transmission is started Ce Note Writing to UXTXBUF UART Mode Data should never be written to transmit buffer UXTXBUF when the buffer is not ready UTXIFG 0 and when the transmitter is enabled UTXE is set Otherwise the transmission may have errors ee Note Write to UXTXBUF Reset of Transmitter UA
449. tem 15 5 Transfer Characteristic and Power Dissipation in a CMOS Inverter Buffer 15 9 Transfer Characteristic and Power Dissipation in a CMOS Gate 15 9 Application Example With One Active Driving R3 and Three Passive Pins With Applied Analog Signals 15 10 Temperature Measurement Systems 15 11 Timing for Temperature Measurement Systems 15 12 Two Independent Temperature Measurement 15 13 Temperature Measurement Via Temperature Sensor R1 meas 15 14 Temperature Measurement Via Temperature Sensor R2 meas 15 15 Detect a Voltage Level Using an External Reference Level 15 16 Detect a Current Level Using an Internal Reference Level 15 17 Measuring a Current Source seh 15 18 Timing for Measuring a Current Source 15 18 A D Converter for Voltage Sources 15 19 XV Contents 15 17 15 18 15 19 15 20 15 21 15 22 16 1 16 2 16 3 16 4 16 5 16 6 16 7 16 8 16 9 16 10 16 11 16 12 16 13 17 1 17 2 17 3 17 4 17 5 17 6 17 7 17 8 17 9 17 10 17 11 17 12 17 13 17 14 17 15 17 16 17 17 17 18 17 19 17 20 17 21 17 22
450. ter can be used to clear this direction memory feature 11 3 2 Timer Up Mode The up mode is used if the timer period must be different from the 65 536 16 bit clock cycles of the continuous mode period The capture compare register CCRO data define the timer period The counter counts up to the content of compare register CCRO as shown in Figure 11 5 When the timer value and the value of compare register CCRO are equal or if the timer value is greater than the CCRO value the timer restarts counting from zero Timer A 11 5 Timer Modes Figure 11 5 Timer Up Mode OFFFFh CCRO Oh Flag CCIFGO is set when the timer equals the CCRO value The TAIFG flag is set when the timer counts from CCRO to zero All interrupt flags are set independently of the corresponding interrupt enable bit but an interrupt is requested only if the corresponding interrupt enable bit and the GIE bit are set Figure 11 6 shows the flag set cycle Figure 11 6 Up Mode Flag Setting Timer Clock Timer Set Flag TAIFG Set Flag CCIFGO 11 3 2 1 Timer Up Mode Changing the Period Register CCRO Value Changing the timer period register CCRO while the timer is running can be a little tricky When the new period is greater than or equal to the old period the timer simply counts up to the new period and no special attention is required see Figure 11 7 However when the new period is less than the old period the phase of the timer clo
451. terminal of the capacitor d CAOUT or CAIFG utilized to measure the discharge time The output filter should be used to minimize multiple switching when the voltages at the comparator inputs are close together If CAOUT is available as an input to a timer capture register such as Timer A the capacitor discharge time can be measured very precisely without software polling for a change of CAOUT by using the timer capture function N Rmeas Pref X meas Tmeas f Rmeas ref Comparator A Applications 15 4 3 Measuring Two Independent Resistive Element Systems Itis possible to measure two independent systems with one comparator The input multiplexer which is controlled via CAEX allows the two independent systems to be isolated See Figure 15 9 An example could be if one temperature sensor has resistor range of 10 to 200 The other sensor is in the range of 1 kO to 1 5 kO Two independent measurement paths are used to optimize individual measurement performance The conversion principle is identical to the one described in the previous section Figure 15 9 Two Independent Temperature Measurement Systems _ _ oV Vcc 0 1 2 6 R1 R1 ret CAEX an e g meas ref E CAON CAF Capture 0 1 r C1 p T T R2 meas CAREF e c CARSEL 15 VCAREF o 1 0 25
452. ters The Basic Timer1 register is byte structured and should be accessed using byte processing instructions suffix B Table 10 1 describes the Basic Timer1 registers Table 10 1 Basic Timer1 Registers Register Short Form Register Type Address Initial State BT Control BTCTL Read write 040h Unchanged BT Counter 1 BTCNT1 Read write 046h Unchanged BT Counter 2 BTCNT2 Read write 047h Unchanged Note Theuser s software should configure these registers at power up as there is no defined initial state 10 1 1 1 Basic Timer1 Control Register Theinformation stored in the control register determines the operation of Basic Timer1 The state of the different bits selects the frequency source the interrupt frequency and the framing frequency of the LCD control circuitry as shown in Figure 10 2 Figure 10 2 Basic Timer1 Control Register 7 0 BTCTL 040h SSEL Hold FRFQ1 FRFQO IP2 IP1 rw rw rw rw rw rw rw rw Bits 0 to 2 The three least significant bits 2 to IPO determine the interrupt interval time It is the interval of consecutive settings of the interrupt request flag BTIFG as illustrated in Figure 10 3 Bits to 4 The two bits FRFQ1 and FRFQO select the frequency f cp as described in Figure 10 3 Devices with the LCD peripheral on the chip use this frequency to generate the timing of the common and select lines Bit 5 See bit 7 Bit 6 The hold bit stops the counter operation BTCNT2 is held if the hold bit
453. th positive and negative reference voltage levels selectable for each channel independently Selectable conversion clock source ADC12 17 3 ADC12 Description and Operation Versatile conversion modes including single channel repeated single channel sequence and repeated sequence Li Sixteen 12 bit registers for storage of conversion results Each register is individually accessible by software and individually configurable to define the channel and references for its conversion result ADC core and reference voltage powered down separately 17 2 ADC12 Description and Operation 17 2 1 ADC Core The ADC core shown in Figure 17 2 converts the analog input to its 12 bit representation and stores the results in the conversion memory The core uses two programmable selectable voltage levels Vp and Vp to define the upper and lower limits of the conversion range and to define the full scale and zero scale readings The digital output is full scale when the input signal is equal to or higher than and zero when the input signal is equal to or lower than Vg The input channel and the reference voltage levels VR and Vp are defined in the conversion control memory The conversion formula is Vin Vp NADC 4095 x V R T VR Figure 17 2 ADC Core Input Multiplexer and Sample and Hold ADC12MCTLx 0 3 VeREF VREF Temperature AVCC 2 17 4 ADC12MCTLx 4 6 1 1
454. the SumExt register contains OFFFFh and the ACC register contains a negative number 8000 0000h OFFFF FFFFh 2 The result of a MACS operation is negative and less than or equal to 07FFF FFFFh In this case the SumExt register contains 0000h and the ACC register contains a positive number 0000 0000h O7FFF FFFFh 6 2 1 Multiply Unsigned 16 16 bit 16x 8 bit 8x 16 bit 8 x8 bit The following is an example of unsigned multiplication 16x16 Unsigned Multiply MOV 01234h amp MPY Load first operand into appropriate register MOV 05678h amp OP2 Load 2nd operand Result is now available 8x8 Unsigned Multiply 0126 amp MPY Load first operand into appropriate register MOV B 4034h amp OP2 Load 2nd operand Result is now available 6 2 2 Multiply Signed 16 16 bit 16 8 bit 8x16 bit 8x8 bit The following is an example of signed multiplication 16x16 Signed Multiply MOV 01234h amp MPYS Load first operand into appropriate register MOV 056781 amp OP2 Load 2nd operand Result is now available 8x8 Signed Multiply MOV B 012h amp MPYS Load first operand into appropriate register SXT amp MPYS Sign extend first operand MOV B 0345 amp 0 2 Load 2nd operand SXT amp OP2 Sign extend 2nd operand triggers 2nd multiplication Result is now available Hardware Multiplier Operation 6 2 3 Multiply Unsigned and Accumulate 16x16 bit 16x
455. the TBCTL register When using groups the CLLDx bits of the lowest numbered TBCCRx register in the group determine the load event for each compare latch of the group except when all seven compare latches are grouped together TBCLGRP 3 For example if a user selects the compare latches to be grouped in groups of three then there are two groups of three TBCL1 TBCL2 and TBCL3 form one group and TBCL4 TBCL5 and TBCL6 form the other group In this scenario the CLLDx bits for TBCL1 determine the load event for the first group and the CLLDx bits for TBCL4 determine the load event for the second group The CLLDx bits in TBCCTL2 TBCCTL3 TBCCTL5 and TBCCTL6 are unused When all compare latches are grouped together TBCLGRP 3 then the CLLDx bits in TBCL1 determine the load event When using groups two conditions must exist for the compare latches to be loaded First all TBCCRx registers of the group must be updated except when using immediate mode second the load event must occur This means that if a user intends to retain any TBCCRx register data of a group when up dating the group the old data must be written to the TBCCRx register again Otherwise the compare latches will not be updated The CLLDx bits in the applicable TBCCTLx register select the load event There are four choices for the load event _j Immediate Lj When the Timer B register TBR counts to 0 Continuous mode or up mode when TBR counts to 0 Up down mod
456. the ability to disable the input buffer Typically all channels except the one being converted are disabled providing a high impedance input and avoiding current consumption caused by through put current See Section 15 4 1 The typical digital ports on MSP430 do not have the ability to disable the input buffer However on devices with the Comparator A the capability has been added and is controlled with the CAPD x bits The control bits to CAPD 7 are initially reset enabling all the input buffers for the associated port The port input buffer is disabled if the according CAPD x bit is set See device data sheet for port associations The ability to disable the input buffer for the device pin applies to up to eight inputs of the associated digital port check device data sheet for implementation details For example the 41x devices have CA1 multiplexed on pin P1 7 and CAO multiplexed on pin P1 6 so the Comparator A is associated with port P1 On this device all input buffers associated with all P1 pins P1 x may have the capability to be disabled with the CAPD register 7 0 CAPD 7 CAPD 6 CAPD 5 CAPD 4 CAPD 3 CAPD 2 CAPD 1 CAPD 0 CAPD 05Bh rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 CAPD x 0 The input buffer for the pin enabled 1 The input buffer for the pin is disabled Comparator A Applications 15 4 Comparator A in Applications The Comparator A can be used to
457. timer increments or decrements depending on mode of operation with each rising edge of the clock signal The timer can be read or written to with software Additionally the timer can generate an interrupt with its ripple carry output when it overflows 12 2 1 Timer Length Timer Bis configurable to operate as a true 8 bit 10 bit 12 bit or 16 bit timer The length of the counter is configured in the TBCTL register Leading bits are read as zero in 8 bit 10 bit and 12 bit mode Data written to the TBR register in 8 bit 10 bit and 12 bit mode will show leading Os The maximum count value for the various lengths is Timer B Configuration TBR max 16 bit OFFFFh 12 bit OFFFh 10 bit O3FFh 8 bit OFFh 12 2 2 Timer Mode Control The timer has four modes of operation as shown Figure 12 2 and described in Table 12 1 stop up continuous and up down The operating mode is soft ware selectable with the and 1 bits in the TBCTL register Figure 12 2 Mode Control Data 15 16 Bit Timert CLK Timer Clock EquO p os Control gt Carry Zero MOS Set TBIFG POR 0 0 Stop Mode 0 1 Up Mode 1 0 Continuous Mode 1 1 Up Down Mode t Length is selectable for 8 10 12 or 16 bit operation Timer_B 12 5 Timer B Operation Table 12 1 Timer Modes 12 2 3 Clock Source Mode Control MC1 MCO Description 0 0 Stop The timer is halted 0 1 Up The timer coun
458. ting modes watchdog or timer it is only possible to write to WDTCTL using the correct password Figure 9 2 S aig Timer Control ia WDTCTL rw 0 rw 0 rw 0 rw O0 rO w rw O0 rw 0 rw 0 WDTCTL 4 069h read WDTCTL write 4 05Ah Bits 0 1 Bits ISO 151 select one of four taps from the WDTCNT as described in Table 9 1 Assuming forystal 32 768 Hz and fsMCLK 1 MHz the following intervals are possible Table 9 1 WDTCNT Taps SSEL IS1 ISO Interval ms 0 1 1 0 064 28 0 1 0 0 5 tsMcLk x 29 1 1 1 1 9 tACLK x 28 0 0 1 8 tsmcLk x 213 1 1 0 160 tacik x 29 0 0 0 32 tsMCLK x 215 Value after reset 1 0 1 250 tack x 213 1 0 1000 tacgik x 215 Bit 2 The SSEL bit selects the clock source for WDTONT SSEL 0 WDTONT is clocked by SMCLK SSEL 1 WDTCNT is clocked by ACLK Bit 3 Counter clear bit In both operating modes writing a 1 to this bit restarts the WDTCNT at 00000h The value read is not defined Bit 4 The TMSEL bit selects the operating mode watchdog or timer TMSEL 0 Watchdog mode TMSEL 1 Interval timer mode Watchdog Timer 9 3 The Watchdog Timer Bit 5 The NMI bit selects the function of the RST NMI input pin It is cleared by the PUC signal NMI 0 The RST NMI input works as reset input As long as the RST NMI pin is held low the internal signal is active level sensitive NMI 1 The RST NMI input works as an edge sensitive
459. tion 14 7 State Diagram of Receiver Enable Operation MSP430 as Master 14 10 State Diagram of Receive Transmit Enable MSP430 as Slave Three Pin Mode 14 10 State Diagram of Receive Enable MSP430 as Slave Four Pin Mode 14 11 State Diagram of Transmit Enable MSP430 as Master 14 11 State Diagram of Transmit Enable MSP430 as Slave 14 12 Receive Interrupt Operation ete eee ees 14 13 Receive Interrupt State Diagram 14 13 Transmit Interrupt Operation 14 14 USART Control Register 0c cece n 14 16 Transmit Control Register UOTCTL U1TCTL 14 17 USART Clock Phase and Polarity 14 18 Receive Control Register UORCTL UTRCTL 14 18 USART Baud Rate Select Register 14 19 USART Modulation Control Register 14 19 Receive Data Buffer UORXBUF UTRXBUF 14 19 Transmit Data Buffer UOTXBUF U1TXBUF 14 20 Schematic of _ ccc sen 15 2 RC Filter Response at the Output of the Comparator 15 4 Comparator_A Interrupt Sys
460. tion Figure C 4 Segments in Flash Memory Module 4K Byte Example Flash Memory Flash Memory One Module One Module 4Kbyte 256Byte Several Segments FFFFh FFFFh Segmento 4 kbyte FEOOh Main Memory Segment1 Segment2 Segment3 FOOOh 010FFh 256 Byte 01000h Flash Information Memory SegmentA SegmentB C 1 1 Why Is a Flash Memory Module Divided Into Several Segments Once a bit in flash memory has been programmed it cannot be erased without erasing a whole segment For this reason the MSP430 flash memory modules have been heavily segmented to allow erasing and reprogramming of smaller memory segments C 2 Flash Memory Data Structure and Operation The flash memory can be read and written programmed in bytes or words Bits can be written as Os once between erase cycles The read access does not differ from access to masked ROM or RAM Flash memory has restrictions in write operation _j The default erased level for all bits is 1 Bits that are not programmed to 0 can be programmed to 0 at any time _j The smallest memory portion to be erased is a segment No single byte or word erase is possible Access to a flash memory module is only possible when the module is not in a write or erase operation For example program code can not be executed in a module while it is processing a write or erase operation The access limitation has no critical impact on program execution but an access
461. tion address contents of R11 Register R10 is incremented by 1 for a byte operation or 2 for a word operation after the fetch it points to the next address without any overhead This is useful for table processing Valid only for source operand The substitute for destination operand is O Rd plus second instruction INCD Rd Length One or two words Operation Comment Example MOV QGR10 0 R11 Before Address Register Space OFF18h OFF16h R10 OFF 14h PC R11 OFF12h OFA32h 05BC1h 010A8h 01234h Address Space OFF18h PC OFF16h OFF14h OFF12h Register R10 OFA34h 11 010A8h OFA32h 05BC1h 010A8h 05BC1h The autoincrementing of the register contents occurs after the operand is fetched This is shown in Figure 5 6 Figure 5 6 Operand Fetch Operation 5 12 Instruction Address 5 2 7 Immediate Mode The immediate mode is described in Table 5 11 Table 5 11 Immediate Mode Description Length Operation Comment Example Before OFF16h OFF14h OFF12h 010AAh 010A8h 010A6h Assembler Code MOV 451 Two or three words Addressing Modes Content of ROM MOV 45 X TONI PC It is one word less if a constant of CG1 or CG2 can be used Move the immediate constant 45h which is contained in the word following the instruction to destination address TONI When fetching the source the program counter po
462. tional Code Field Jump Offset Field Conditional jumps jump to addresses in the range of 511 to 4512 words relative to the current address The assembler computes the signed offsets and inserts them into the op code Instruction Set Description B 5 Instruction Set Overview JC JHS JEQ JZ JGE JL JMP JN JNC JLO JNE JNZ Label Label Label Label Label Label Label Label Jump to label if carry bit is set Jump to label if zero bit is set Jump to label if N XOR V 2 0 Jump to label if N XOR V 1 Jump to label unconditionally Jump to label if negative bit is set Jump to label if carry bit is reset Jump to label if zero bit is reset Note Conditional and Unconditional Jumps Conditional and unconditional jumps do not affect the status bits A jump that is taken alters the PC with the offset PCnew POold 2 2 offset A jump that is not taken continues the program with the ascending instruction B 1 3 Emulated Instructions B 6 The following instructions can be emulated with the reduced instruction set without additional code words The assembler accepts the emulated instruction mnemonic and inserts the applicable core instruction op code Instruction Set Overview The following list describes the emulated instruction short form Mnemonic Description Status Bits Emulation VNZC Arithmetical instructions ADC W
463. tive load capacitance in the crystals data sheet Electrically the capacitors are connected serially on pins XIN and XOUT and the effective load capacitance is then C eff C XIN x C XOUT V C XIN C XOUT So an effective load capacitance of 12 pF specified by the crystal s data sheet requires 24 pF 22 pF 2 pF parasitic capacitance at each pin XIN and XOUT Figure 7 2 Principle of LFXT1 Oscillator 74 0pR i0pF i4pEor iBpF e e ov XINI ca xou1 FLL MSP430 gt e OV 32 768 Hz 0 pF 10 pF 14 pF or 18 pF or oe es J 450 kHz to 8 MHz Digitally Controlled Oscillator and Frequency Locked Loop 7 3 Digitally Controlled Oscillator DCO and Frequency Locked Loop The DCO is an integrated RC type oscillator in the MSP430x4xx clock module The DCO generates a clock signal called This signal is used by the MSP430x4xx CPU MCLK andis available to on chip peripherals SMCLK MCLK is set to a multiple of ACLK The N multiplier is contained in the lowest 7 bits of control register SCFQCTL SCFQCTL 6 SCFQCTL 0 Initially N is set to 31 on D is set to 2 is reset resulting in an effective ACLK multiplier of 32 and an MCLK and SMCLK of 1 048576 MHz assuming that ACLK is 32 768 Hz The multiplier N 1 and D set the frequency of MCLK and SMCLK DCO 0
464. to charge to 1 2 LSB minimum sampling time is ten 1 2 LSB Ry x Cj x In 8192 Where In 8192 9 011 Therefore with the values given the time for the analog input signal to settle is tcn 1 2 LSB Rt x Cj x 9 011 4 This time must be less than the sampling time If the pulse sampling mode is used the maximum ADC12CLK frequency is max f ADC12CLK 5 ch This frequency must not exceed the maximum ADC12CLK frequency specified in the data sheet 17 8 ADC12 Control Registers Five control registers sixteen conversion memory registers and sixteen conversion memory control registers are used to configure the ADC12 Register Short Form Register Type Address Initial State ADC control register 0 ADC12CTLO Read write 01A0h Reset with POR ADC control register 1 ADC12CTL1 Read write 01A2h Reset with POR ADC interrupt flag register ADC12IFG Read write 01A4h Reset with POR ADC interrupt enable register ADC12IE Read write 01A6h Reset with POR ADC interrupt vector word ADC12IV Read 01A8h Reset with POR memory 0 ADC12MEMO 0140h to Read Unchanged ADC memory 15 ADC12MEM15 015Eh memory control 0 ADC12MCTLO 080h to Read Reset with POR ADC memory control 15 ADC12MCTL15 08Fh Note All registers may bea 17 30 ccessed by any instruction subject to register access restrictions ADC12 Control Registers 17 8 1 Control Registers ADC12CTLO and ADC12CTL1 ADC12CTLO 01A0h ADC12SC ENC All control bits
465. to save current consumption or processing resources The control register bit MM defines the address bit or idle line multiprocessor format Both use the wake up on transfer mode by activating the TXWake bit address feature function and RXWake bit The URXWIE and URXIE bits control the transmit and receive features of these asynchronous communication formats 13 3 4 Idle Line Multiprocessor Format In the idle line multiprocessor format shown in Figure 13 7 blocks of data are separated by an idle time An idle receive line is detected when ten or more 1s in a row are received after the first stop bit of a character Figure 13 7 Idle Line Multiprocessor Format Block of Frames HER a dB N A Oe ce ES EST SE SIS t t es Idle Periods of 10 Bits or More UTXD URXD Expanded UTXD URXD eee First Frame Within Block Frame Within Block Frame Within Block is Address It Follows Idle Period of 10 Bits or More Idle Period Less Than 10 Bits USART Peripheral Interface UART Mode 13 7 Asynchronous Operation When two stop bits are used for the idle line as shown in Figure 13 8 the second one is counted as the first mark bit of the idle period The first character received after an idle period is an address character The RXWake bit can be used as an address tag for the character In the idle line multiprocessor format the RXWake bit is set when a received character is an address character and is tra
466. tor A Control Register CACTL1 15 6 15 3 2 Comparator Control Register CACTL2 15 7 15 3 8 Comparator_A Port Disable Register CAPD 15 8 15 4 Comparator A in Applications 15 9 15 4 1 Analog Signals at Digital Inputs 15 9 15 4 2 Comparator A Used to Measure Resistive Elements 15 11 15 4 8 Measuring Two Independent Resistive Element Systems 15 13 15 4 4 Comparator A Used to Detect a Current or Voltage Level 15 16 15 4 5 Comparator A Used to Measure a Current or Voltage Level 15 17 15 4 6 Measuring the Offset Voltage of _ 15 20 15 4 7 Compensating for the Offset Voltage of Comparator A 15 22 Contents 16 17 18 15 4 8 Adding Hysteresis to Comparator A 15 22 Liquid Crystal Display Drive lluseeeeeeeese III 16 1 16 1 LCD Drive Basics ese hh 16 2 16 2 LCD Controller Driver ss IRI n 16 7 16 2 1 LCD Controller Driver Features 16 8 16 2 2 LCD Timing Generation llsulsssssesssse eh 16 8 16 2 8 LCD Voltage Generation 0 00 cee eee 16 9 16 2 4 LGD Outputs ic cones mec ence seen MEL Sea eee
467. troller Driver Block Diagram Segment 391 Segment 381 Segment Output Control Display Memory 20x8 Bit Segment S1 Segment SO ADR 091h 0A4h LCD ET Control 1 COM2 utput Mode Control COM1 Register COMO COM3 Analog Voltage Multiplexer fL cp Timing Generator OscOff gt t The maximum number of segments lines available on devices pins may be different 41 device SO to S23 43 device SO to S31 80 pin package or SO to S39 100 pin package 44x device SO to S39 Liquid Crystal Display Drive 16 7 LCD Controller Driver 16 2 1 LCD Controller Driver Features The LCD controller driver features are _j Display memory Automatic signal generation Support for 4 types of LCDs Static 2MUX 1 2 bias 3 MUX 1 3 bias 4 MUX 1 3 bias Multiple frame frequencies Unused segment outputs may be used as general purpose outputs _j Unused display memory may be used as normal memory Operates using the basic timer with the auxiliary clock ACLK The LCD line frame frequencies include LJ Static mode 2 flop Lj 2 MUX frame 4 LCD 3 MUX frame 6 LCD f ixf 4 MUX frame 8 LCD 16 2 2 LCD Timing Generation The LCD controller uses the fj cp signal from the Basic Timer1 discussed Chapter 10 to generate the t
468. ts do not flow through any common input leads eliminating any error voltages In addition to grounding ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result The ripple can become more dominant by reducing the value of the conversion voltage range Vn therefore reducing the value of the LSB and the noise margin Thus a clean noise free setup becomes even more important to achieve the desired accuracy Adding carefully placed bypass capacitors returned to the respective ground planes can help in reducing ripple in the supply current and minimizing these effects Figure 17 26 A D Grounding and Noise Considerations Note zm d0uF 750 1 uF rx 10 uF 0 1 uF T1 If the internal Vref is used add 10 uF 100 nF to the reference voltage terminals External reference voltage source should meet low dynamic impedance to ensure 12 bit conversion accuracy ADC12 17 41 17 42 Appendix Peripheral File This appendix summarizes the MSP430x4xx peripheral file PF and control bit information into a single location for reference Each PF register is presented as arow of boxes containing the control or status bits belonging to the register The register symbol e g POIN and the PF hex address are to the left of each register Topic Page 2 A 2 Special Function Register of MSP430x4xx
469. ts upward until its value is equal to the value of compare latch TBCLO Note If TBCLO gt TBR max the counter counts to zero with the next rising edge of timer clock 1 0 Continuous The timer counts upward continuously The maximum value of TBR TBR max is OFFFFh for 16 bit configuration OOFFFh for 12 bit configuration 003FFh for 10 bit configuration OOOFFh for 8 bit configuration 1 1 Up Down The timer counts up until the timer value is equal to compare latch 0 and then it counts down to zero Note If TBCLO gt TBR max the counter operates as if it were configured for continuous mode It will not count down from TBR may to zero Select and Divider The timer clock can be sourced from internal clocks i e ACLK MCLK or SMCLK or from an external source TBCLK as shown in Figure 12 3 The clock source is selectable with the TBSSELO and TBSSEL1 bits in the TBCTL register Itis important to note that when changing the clock source for the tim er errant timings can occur For this reason stopping the timer before changing the clock source is recommended The selected clock source may be passed directly to the timer or divided by 2 4 or 8 as shown in Figure 12 4 The IDO and 101 bits in the TBCTL register select the clock division Note that the input divider is reset by a POR signal or by setting the TBCLR bit in the TBCTL register see chapter 3 System Resets Interrupts and Operating Modes for more information on the POR
470. uence 7 7 7 7 6 7 7 6 so The sequence repeats after all eight bits of the modulator are used Example 13 2 19 200 Baud Assuming a clock frequency of 1 04 MHz 32 x 32 768 Hz for the BRCLK signal and a required baud rate of 19 200 the division factor is 54 61 The baud rate generation in the MSP430 USART uses a factor of 54 36h plus a modulation register load of OD5h The divider runs the following sequence 55 54 55 54 55 54 55 55 and so on The sequence repeats after all eight bits of the modulator are used 13 6 Asynchronous Operation 13 3 3 Asynchronous Communication Formats The USART module supports two multiprocessor communication formats when asynchronous mode is used These formats can transfer information between many microcomputers on the same serial link Information is transferred as a block of frames from a particular source to one or more destinations The USART has features that identify the start of blocks and suppress interrupts and status information from the receiver until a block start is identified In both multiprocessor formats the sequence of data exchanged with the USART module is based on data polling or on the use of the receive interrupt features Both of the asynchronous multiprocessor formats idle line and address bit allow efficient data transfer between multiple communication systems They can also minimize the activity of the system
471. uested if ACCVIE 1 C 2 4 Flash Memory Status During Code Execution The flash memory module delivers data for code execution in the same manner as any masked ROM or RAM The flash memory module should be in read mode with no write programming or erase operation active By default power on reset POR puts the flash memory into read mode No control bits need to be defined in the flash memory control registers after POR for code execution C 2 5 Flash Memory Status During Erase C 8 The default bit level of the flash memory is 1 Any successful erase sets all bits of a segment or a block to this default level Once a bit is programmed to the 0 level only the erase function can reset it back to 1 Erase can be performed for one segment a group of segments or for an entire module This can vary for each device configuration and the exact implementation should be noted in the data sheet The erase operation starts with the following sequence 1 Setthe correct input clock frequency of the timing generator by selecting the clock source and predivider 2 Reset the LOCK control bit if set 3 Watch the BUSY bit Continue to the next steps only if the BUSY bit is reset 4 Setthe erase control bit Erase to erase a segment or 5 Setthe mass erase control bit MEras to erase all numbered segments 6 Set the mass erase MEras and erase Erase control bits to erase all flash memory segments 7 Execute a dummy write to any addres
472. ult is placed into the destination N Setif result MSB is set reset if not set Z Setif result is zero reset otherwise C Set if result is not zero reset otherwise NOT Zero V Reset OscOff CPUOff and GIE are not affected The bits set in R5 are used as a mask OAA55h for the word addressed by TOM If the result is zero a branch is taken to label TONI MOV 0AA55h R5 Load mask into register R5 AND R5 TOM mask word addressed by TOM with R5 JZ TONI ae Result is not zero or AND 0AA55h TOM JZ TONI The bits of mask 40A5h are logically ANDed with the low byte TOM If the result is zero a branch is taken to label TONI AND B 0A5h TOM mask Lowbyte TOM with R5 JZ TONI Result is not zero BIC W BIC B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Overview Clear bits in destination Clear bits in destination BIC src dst or BIC W src dst BIC B src dst NOT src AND dst dst The inverted source operand and the destination operand are logically ANDed The result is placed into the destination The source operand is not affected N Not affected Z Not affected C Not affected V Not affected OscOff CPUOff and GIE are not affected The six MSBs of the RAM word LEO are cleared BIC 0FC00h LEO Clear 6 MSBs in MEM LEO The five MSBs of the RAM byte LEO are cleared BIC B 0F8h LEO Clear 5 MSBs in Ram location LEO
473. und plane so one can see how the pin counts of large LCDs with many segments could easily become cumbersome For example an 80 segment static LCD requires 81 pins To reduce pin counts LCDs are often multiplexed This means the individual LCD segments are arranged in a matrix of the segment pins and common pins such that each LCD segment has a unique combination of a segment pin and a common pin for activation but each segment pin can be used for more than one segment For example a 2 MUX LCD contains one segment pin for every two segments and 2 common layers each with a pin The two segments that share any pin are connected to different common layers for individual control The table below shows a possible pin configuration for a 2 MUX 16 segment LCD There are 10 total pins Pin 3 segment 6 common 0 1 LCDs with more common planes realize greater pin count reductions For example a possible pin configuration of a 4 MUX 16 segment LCD is shown below This LCD has 8 total pins for a reduction of 2 pins over the 2 MUX configuration above Two pins is generally not significant however in the case of a 128 segment LCD for example the required pins for a 2 MUX version would be 66 128 2 2 whereas the required pins for a 4 MUX version would be 36 128 4 4 common 0 1 2 common 3 LCD Drive Basics Because of the multiplexing of segments with segment pins
474. unting in the down direction if it is restarted in up down mode If this is not desired the TBCLR bit in the TBCTL register must be used to clear the direction Note that the TBCLR bit affects other setup conditions of the timer Refer to section 12 6 for a discussion of the Timer B registers Figure 12 14 Timer Up Down Direction Control POR TBCLR in TBCTL Up Down For Timer TBR Low Down Direction High Up Direction Up Down Mode TBR gt TBCLO Timer Clock In up down mode the interrupt flags CCIFGO and TBIFG are set at equal time intervals Figure 12 15 Each flag is set only once during the period but they are separated by 1 2 the timer period CCIFGO is set when the timer counts from TBCLO 1 to TBCLO and TBIFG is set when the timer completes counting down from 0001h to 0000h Each flag is capable of producing a CPU interrupt when enabled Figure 12 15 Up Down Mode Flag Setting Timer Clock Timer Up Down Set CCIFGO Set TBIFG 12 3 4 1 Timer In Up Down Mode Changing the Value of Period Register TBCLO Immediate Mode for TBCLO Changing the period value while the timer is running in up down mode and the transfer mode for TBCLO is immediate is even trickier than in up mode Like in up mode the phase of the timer clock when TBCLO is changed affects the timer s behavior Additionally in up down mode the direction of the timer also affects the behavior If the timer is counting in the up direct
475. uty cycle of multiple signals needs to be updated simultaneously See section 12 4 2 1 for more discussion on how to use and configure the compare latches If the timer becomes equal to the value in compare latch TBCLx then Timer B 12 19 Timer Modes Interrupt flag CCIFGx located in control word TBCCTLx is set interrupt is requested if interrupt enable bits CCIEx and GIE are set Signal EQUx is output to the output unit This signal affects the output OUTx depending on the selected output mode The EQUO signal is true when the timer value is greater or equal to the TBCLO value The EQU1 to EQUx signals are true when the timer value is equal to the corresponding TBCL1 to TBCLx values 12 4 2 1 Capture Compare Block Compare Mode Compare Latch TBCLx 12 20 The compare logic uses the data in the compare latch for its comparison with the timer value The compare data is first written by software to the capture compare register TBCCRx and then automatically transferred to the compare latch on a user selectable load event The load event is selected with the CLLDx bits in each TBCCTLx register In addition the compare latches may be grouped together so that each compare latch in a group is updated simultaneously on the load event All compare latches may be grouped together in a single group or they may be grouped in groups of two or three compare latches The grouping is configured with the TBCLGRP bits in
476. value in TBCCRO compare latch TBCLO The counter must count from TBCLO 1 to TBCLO If the TBCLO value were simply written directly to the timer with software the interrupt flag would not be set even though the val ues in the timer and TBCLO would be the same LLLLLLL OAXAA CA Topic Page 12 1 Introduction ene nee gere ee eee PEE 12 2 12 2 mimer B Operation 11 12 5 12 3 IMO MOGES 12 8 12 4 Capture Compare Blocks 12 15 12 5 The Output 12 23 12 6 Timer B Registers 12 29 12 1 Introduction 12 1 Introduction Timer B is an extremely versatile timer made up of 16 bit counter with 4 operating modes and four selectable lengths 8 bit 10 bit 12 bit or 16 bit Selectable and configurable clock source Up to seven independently configurable capture compare registers with configurable inputs and double buffered compare registers Up to seven individually configurable output modules with eight output modes Timer B can support multiple simultaneous timings multiple capture compares multiple output waveforms such as PWM signals and any combination of these In addition with the double buffering of compare data multiple PWM periods can be updated simultaneously Additionally Timer B has extensive interrupt capabiliti
477. verlap shown in Figure 4 Figure B 4 Decrement Overlap EDE o TONI EDE 254 TONI 254 Example Memory byte at address LEO is decremented by one DEC B LEO Decrement MEM LEO Move a block of 255 bytes from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination address TONI must not be within the range EDE to EDE 0FEh MOV EDE R6 MOV B 255 LEO L 1 MOV B R6 TONI EDE 1 R6 DEC B LEO JNZ L 1 B 26 DECD W DECD B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Instruction Set Overview Double decrement destination Double decrement destination DECD dst or DECD W dst DECD B dst dst 2 dst SUB 2 dst SUB B 2 dst The destination operand is decremented by two The original contents are lost N Setif result is negative reset if positive Z Setif dst contained 2 reset otherwise C Resetif dst contained 0 or 1 set otherwise V Setif an arithmetic overflow occurs otherwise reset Set if initial value of destination was 08001 or 08000h otherwise reset Set if initial value of destination was 081 or 080h otherwise reset OscOff CPUOff and GIE are not affected R10 is decremented by 2 DECD R10 Decrement R10 by two Move a block of 255 words from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of dest
478. violation can be flagged in some situations see flash memory register section in this appendix Flash Memory C 5 Flash Memory Data Structure and Operation C 2 4 Flash Memory Basic Functions The basic functions of flash memory are to Supply program code and data during program execution Lj Erase under software or JTAG control parts of a module one segment multiple segments or an entire module Write data to a memory location under software or JTAG control A double speed programming sequence is implemented within a 64 byte section of the address range xxOOh to xx3fh C 2 2 Flash Memory Block Diagram The flash memory module has a minimum of three control registers a timing generator a voltage generator to supply program and erase voltages and the flash memory itself Data and address are latched when execution of a write program or erase operation is in progress Figure C 5 Flash Memory Module Block Diagram Address Latch Data Latch Enable Address Latch Timing Generator Enable Data Latch Programming Voltage Generator C 2 3 Flash Memory Basic Operation The flash memory module normally works in read mode the address and data latch are transparent and the timing generator and programming voltage generator are off The flash memory module changes its mode of operation when data is written programmed to the module or when the flash memory or parts of it are era
479. violation will occur with the watchdog timer address 120h because the security key was not used ee POP W Operation Emulation Emulation Description Status Bits Example Example Example Example Instruction Set Overview Pop word from stack to destination Pop byte from stack to destination POP dst dst SP temp SP 2 gt SP temp gt dst MOV SP dst or SP dst MOV B SP dst The stack location pointed to by the stack pointer TOS is moved to the destination The stack pointer is incremented by two afterwards Status bits are not affected The contents of R7 and the status register are restored from the stack POP R7 POP SR Restore R7 Restore status register The contents of RAM byte LEO is restored from the stack LEO The low byte of the stack is moved to LEO The contents of R7 is restored from the stack R7 low byte of the stack is moved to R7 the high byte of R7 is 00h The contents of the memory pointed to by R7 and the status register are restored from the stack O R7 The low byte of the stack is moved to the the byte which is pointed to by R7 Example R7 203h Mem R7 low byte of system stack Example R7 20Ah 4 Mem R7 low byte of system stack POP SR S Note The System Stack Pointer The system stack pointer SP is always incremented by
480. w 0 rw 0 rw 0 Function select PSSEL 001Bh Direction register PSDIR P3DIR 7 P3DIR 6 PSDIR 5 P3DIR 4 PSDIR 3 P3DIR 2 P3DIR 1 P3DIR O 001Ah rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Output register PBOUT 7 P3OUT 6 5 4 PSOUT 3 PSOUT 2 PSOUT 1 P3OUT 0 0019h rw rw rw rw rw rw rw rw Input register P3IN PSIN 7 P3IN 6 P3IN 5 P3IN 4 P3IN 3 P3IN 2 PSIN 1 P3IN O 0018h r r r r r r r r 0017h 0016h 0010h Peripheral File A 3 Digital Byte Access Digital Byte Access Continued Bit Function select POSEL 0037h Direction register PEDIR 0036h Output register POUT 0035h Input register P6IN 0034h Function select PSSEL 0033h Direction register PSDIR 0032h Output register PBOUT 0031h Input register 0030h 002Fh Function select P2SEL 002Eh Interrupt enable P2IE 002Dh Interrupt edge select P2IES 002Ch Interrupt flags P2IFG 002Bh Direction register P2DIR 002Ah Output register PROUT 0029h Input register P2IN 0028h 0027h Function select P1SEL 0026h Interrupt enable 0025h Interrupt edge select P1IES 0024h Interrupt flags P1IFG 0023h Direction register P1DIR 0022h Output register Pl OUT 0021h Input register P1IN 0020h 4 7 5 P6SEL 7 PeSEL 6 PeSEL 5 PeSEL 4 P6SEL 3 rw 0 rw 0 rw 0 P6DIR 7 PeDIR 6 P6DIR 5 PeDIR
481. ware algorithm is simple The embedded timing generator in the flash memory module controls the program and erase cycles Software can run in the same flash memory module where data is to be written on in other memory modules such as ROM RAM or another flash memory module Flash Memory Access via JTAG and Software C 5 3 1 Example Programming One Word Into a Flash Memory Module via Software Execution Outside This Module This example assumes that the code to program the flash location is not executed from the target flash memory module Disable all Interrupt Sources FXKEY set 033008 and Watchdog FWKEY set 0A500h No interrupt request may happen while the flash is programmed Test 1 BIT BUSY amp FCTL3 JNZ Test_Busy1 LOCK 0 WRT 1 MOV FWKEY amp FCTL3 Clear lock bit Write Data to Flash Address MOV FWKEY WRT amp FCTL1 Enable write to flash MOV 123h 80FF1Eh Write a word to flash Test_Busy2 BIT BUSY amp FCTL3 still busy JNZ Test_Busy2 yes repeat busy test MOV FWKEY amp FCTL1 Reset write bit XOR FXKEY LOCK amp FCTL3 Change lock bit to 1 Restore or Enable Required Enable those interrupt sources that should be accepted Interrupt Sources and Watchdog The BUSY bit can be tested before the write to the flash memory module is don e or after write program starts For flash memory locations that hold data it is a good practice to test the BUSY bit before the writ
482. when a character is transferred into the UXRXBUF before the previous character is read out The previous character is overwritten and lost OE is reset by a SWRST a system reset or by reading the UXRXBUF The parity error flag bit PE is set when a character is received with a mismatch between the number of 1s and its parity bit The parity checker includes the address bit used in the address bit multiprocessor mode in the calculation The flag is disabled if parity generation and detection are not enabled In this case the flag is read as 0 It is reset by SWRST a system reset or by reading the UxRXBUF The framing error flag bit FE is set when a character is received with 0 stop bit and is loaded into the receive buffer Only the first stop bitis checked when more than one is used The missing stop bit indicates that the start bit synchronization is lost and the character is incorrectly framed FE is reset by a SWRST a System reset or by reading the UXRXBUF n C Note Receive Status Control Bits The receive status control bits FE PE OE BRK and RXWake are set by the hardware according to the conditions of the characters received Once the bits are set they remain set until the software resets them directly or there is a reading of the receive buffer False character interpretation or missing interrupt capability can result in uncleared error bit
483. x MOV B Table Rx amp LCDu 1l 15 all eight segments are written to the display memory Table DI D atb ctdtetf displays 0 btc displays 1 displays d displays E a f g displays F Chapter 17 ADC12 The ADC12 12 bit analog to digital converter is a high speed extremely ver analog to digital converter implemented on MSP430x43x and MSP430x44x devices This chapter discusses the ADC12 and how to use it Topic Page seemed 17 2 17 2 ADC Description and Operation 17 4 17 3 Analog Inputs and Multiplexer 17 6 17 4 Gonversion Memory erreur 17 8 17 59 17 9 17 6 Conversion Clock and Conversion Speed 17 21 et wr 17 22 17 8 ADC12 Control Registers 17 30 17 1 Introduction 17 1 Introduction The ADC12 12 bit analog to digital converter shown in Figure 17 1 has five main functional blocks that can be individually configured and optimized O O O O L Figure 17 1 ADC12 Schematic ADC core with sample and hold Conversion memory and configuration Reference voltage and configuration Conversion clock source select and control Sample timing and conversion control
484. x 16 X tcycle With ttaskmax Maximum worst case time to perform the task during the interrupt routine for example incrementing a counter tcycle Cycle time of the system frequency MCLK The shortest repetitive time distance tc between two events using capture register is ttaskmax 16 X Timer 11 31 Timer UART 11 6 Timer A UART 11 32 The Timer A is uniquely capable of implementing a UART function with the following features Automatic start bit detection even from ultralow power modes Hardware baud rate generation Hardware latching of RXD and TXD data Baud rates of 75 to 115 200 baud Lovo wo Full duplex operation This UART implementation is different from other microcontroller implementations where a UART may be implemented with general purpose and manual bit manipulation via software polling Those implementations require great CPU overhead and therefore increase power consumption and decrease the usability of the CPU The transmit feature uses one compare function to shift data through the output unit to the selected pin The baud rate is ensured by reconfiguring the compare data with each interrupt The receive feature uses one capture compare function to shift pin data into memory through bit SCCIx The receive start time is recognized by capturing the timer data with the negative edge of the input signal The same capture compare block is then switche
485. x defines the data as being word or byte data Example ADD B amp TCDATA TCSUM 1 Byte access ADDC B TCSUM H Byte access ADD R5 SUM A ADD W R5 SUM A Word access ADDC SUM B ADDC W SUM_A Word access A word consists of two bytes a high byte bit 15 to bit 8 and a low byte bit 7 to bit as shown in Figure 4 5 It must always align to an even address Memory 4 5 Figure 4 5 Byte and Word Operation Byte1 012h xxx9h Byte2 034h xxx8h Word1 High Byte 056h xxx7h Word1 Low Byte 078h xxx6h Word High Byte 09Ah xxx5h Word2 Low Byte OBCh Xxx4h ADD B Byte1 Byte2 Byte2 012h 034h 046h ADD W Word1 Word2 Word2 05678h O9ABCh OF134h All operations on the stack and PC are word operations and use even aligned memory addresses In the following examples word to word and byte to byte operations show the results of the operation and the status bit information Example Word Word Operation R5 OF28Eh EDE EQU 0212h m OF28Eh OFFFEh em 0212h 00112h 0 ADD R5 amp EDE Mem 0212h 00110h 1 2 0 N 0 Example Byte Byte Operation R5 0223h EDE EQU 02026 m 0223h 05Fh m 0202h 043h ADD B QR5 amp EDE Mem 0202h 0A2h 0 2 0 N71 Figure 4 6 shows the register byte and byte register operations Figure 4 6 Register Byte Byte Register Operations 4 6 Register
486. x resets OUTx PWM toggle set EQUx toggles OUTx EQUO sets OUTx PWM reset set EQUx resets OUTx EQUO sets OUTx Note OUTx signal updates with rising edge of timer clock for all modes except mode 0 Modes 2 3 6 7 not useful for output unit 0 Timer B 12 23 The Output Unit 12 5 1 12 24 Output Unit Output Modes The output modes are defined by the OMx bits and are discussed below The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0 Output modes 2 3 6 and 7 are not useful for output unit O Output mode 0 Output mode 1 Output mode 2 Output mode 3 Output mode 4 Output mode 5 Output mode 6 Output mode 7 Output mode The output signal OUTx is defined by the OUTx bit in control register TBCCTLx The OUTx signal updates immediately upon completion of writing the bit information Set mode The output is set when the timer value becomes equal to compare data TBCLx Itremains set until a reset ofthe timer or until another output mode is selected to control the output PWM toggle reset mode The output is toggled when the timer value becomes equal to compare data TBCLx It is reset when the timer value becomes equal to TBCLO PWM set reset mode The output is set when the timer value becomes equal to compare data TBCLx It is reset when the timer value becomes equal to TBCLO Toggle mode The output is toggled when the timer value becomes e
487. y software using control bits inthe SVS control reg ister SVSCTL Figure 3 2 Block Diagram of Brownout and SVS Circuits Voc Brownout P6 7 A7 SVSin gt Set POR tReset 5005 P1 3 SVSOut 41x devices P1 3 TBOutH SVSOut 43x and 44x devices Set SVSFG 0 rw 0 rw 0 rw 0 rw 0 rw r r rw 0 SVSCTL 056h SVSCTL Bits 3 1 1 1 Brownout Reset The brownout reset circuit resets the device by triggering a POR signal when power is applied or removed The operating levels are shown in Figure 3 3 When ramping up the POR signal becomes active once Vcc crosses the VCccC start level It remains active until Voc crosses the V g threshold and the delay elapses The hysteresis VHys B ensures that the supply voltage has to drop below Vg jr to generate another POR signal from the brownout reset circuitry System Resets Interrupts and Operating Modes 3 3 System Reset and Initialization Figure 3 3 Brownout Circuit Operating Levels Vcc B IT Set Signal for POR circuitry Vnys B IT BB IT4 VB IT 1 lt Operating Voltage Range 3 The minimum supply voltage to generate a reliable POR when Voc glitches or dips depends on the pulse width of the voltag

MSP430x4xx Family User's Guide (Rev. B)

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