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Xilinx UG332 Spartan-3 Generation Configuration User Guide

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1. Open Drain with Open Drain with DONE Actively Drives Internal Pull up Default External Pull Up FPGA FPGA FPGA VCCAUX VCCAUX Active driver 3300 to Diagram LVCMOS 3 3kQ VCCAUX NICCAUX Startup Startup Startup Sequencer UG332 c2 01 120106a Sequencer UG332 c2 01 120106b Sequencer UG332 c2 01 120106c DriveDone Yes No No DonePin Pullnone Pullup Pullnone Recommended Usage for Various Configuration Topographies Single FPGA Best OK OK but requires external pull up For all down stream FPGAs in Daisy Chain HMM 2 0 iS the chain Also allowed on the OK but requires external pull up 7 first FPGA in the chain Broadside Do Not Use AN ide Mes roading OK but requires external pull up configuration DONE cycle The DONE cycle option controls during which cycle the DONE pin is asserted during the Startup sequence just prior to the completion of a successful configuration See Startup page 233 This option is set graphically in the ISE Project Navigator page 28 by adjusting the Done Output Events setting during Step 14 in Figure 1 8 page 30 DonePipe The DonePipe option is used in a some multi FPGA applications After all DONE pins are released in a multi FPGA configuration the DONE pin must transition from Low to High in a single Startup clock cycle StartupClk If additional time is required for the DONE signal to rise within a single Startup cycle set the DonePipe Yes bitstream generator option for
2. The example PROMGen command provided below generates a PROM file for an XC3S700AN FPGA with the following characteristics e Formatted for the SPI based In System Memory by specifying the spi option e Formatted using the Intel MCS format by specifying the p mcs option The output filename is specified by the o lt promdata gt mcs option where promdata is a user specified file name e The XC3S700AN In System Flash memory is only slightly larger than 8M bits or 1 024 bytes However set the size option to twice the size or s 2048 because the default addressing method uses an additional address line If using the optional power of 2 addressing mode which requires an additional separate special programming step set the size option to s 1024 212 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Programming Spartan 3AN FPGAs Using iMPACT e The first FPGA bitstream bit st ream0 is loaded in the upward direction starting at address 0 by specifying the u 0 option A second MultiBoot bitstream bitstream1 is loaded at the next sector boundary shown in Table 10 3 page 209 0x0C_0000 for the XC3S700AN e The FPGA bitstreams to be added to the In System Flash memory are specified as the last option lt bitstream0 gt bit and lt bitstream1 gt bit where lt inputfile gt is the user specified file name used when generating the FPGA bitstream promgen spi
3. PROG_B e Recommend open drain driver 2 5V JTAG TDI TMS TCK TDO DS312 2_54_022305 Figure 8 1 Slave Serial Configuration The mode select pins M 2 0 are sampled when the FPGA s INIT_B output goes High and must be at defined logic levels during this time After configuration when the FPGA s DONE output goes High the mode pins are available as full featured user I O pins Similarly the FPGA s HSWAP pin must be Low to enable pull up resistors on all user 17U pins or High to disable the pull up resistors The HSWAP control must remain at a constant logic level throughout FPGA configuration After configuration when the FPGA s DONE output goes High the HSWAP pin is available as full featured user I O pin and is powered by the VCCO 0 supply Voltage Compatibility V Most Slave Serial interface signals are within the FPGA s I O Bank 2 supplied by the VCCO 2 supply input The VCCO 2 voltage can be 3 3V 2 5V or 1 8V to match the requirements of the external host ideally 2 5V Using 3 3V or 1 8V requires additional 180 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Daisy Chaining design considerations as the DONE and PROG B pins are powered by the FPGA s 2 5V VccaAux supply See XAPP453 The 3 3V Configuration of Spartan 3 FPGAs for additional information Daisy Chaining If the application requires multiple
4. x8 or x8 x16 Parallel NOR Flash 48 ball FBGA Part number varies by vendor Notes 1 Platform Flash PROMs also work in Master BPI mode as described in Using Xilinx Platform Flash PROMs with Master BPI Mode page 146 The SPI serial Flash vendors offer a wider migration range but do require a multi package footprint For example the Atmel DataFlash SPI serial Flash family spans the range of 1 Mbit to 64 Mbit using a single footprint that accommodates the JEDEC and EIAJ versions of the 8 pin SOIC package along with the 8 connector CASON package The STMicro SPI serial Flash has uses a different footprint that uses a combined 8 pin and 16 pin SOIC footprint and is also compatible with devices from multiple SPI Flash vendors See Multi Package Layout page 126 Similarly parallel Flash supports a wide density range in a common multi vendor package footprint What is the anticipated production lifetime for the end product Consider whether your application has a relatively short or a relatively long production lifetime Commodity memories generally have a shorter production lifetime than the proprietary Xilinx Platform Flash PROMs For example if building an industrial application that will be manufactured for five years or more then Xilinx Platform Flash PROMs may provide better long term availability Similarly the In System Flash ISF memory on Spartan 3AN comes integrated with the FPGA Pr
5. GTS_cycle All I O pins Configuration 1 2 3 4 5 6 Default Selects the Configuration Startup phase that releases the internal three state control holding all I O buffers in high impedance Hi Z Output buffers actively drive if so configured after this point See Startup page 233 Done Waits for the DONE pin input to go High before releasing the internal three state control holding all I O buffers in high impedance Hi Z Output buffers actively drive if so configured after this point Keep Retains the current GTS_cycle setting for partial reconfiguration applications LCK_cycle DCMs Configuration Startup NoWait Default The FPGA does not wait for selected DCMs to lock before completing configuration 0 1 2 3 4 5 6 If one or more DCMs in the design have the STARTUP WAIT TRUE attribute the FPGA waits for such DCMs to acquire their respective input clock and assert their LOCKED output This setting selects the Configuration Startup phase where the FPGA waits for the DCMs to lock See Waiting for DCMs to Lock DCI to Match page 235 Match_cycle Spartan 3 FPGA only DCI Auto The BitGen software examines the FPGA design for any I O standards that use DCI If found BitGen automatically sets Match cycle 2 causing the Startup sequence to stall in state 2 while the DCI circuitry matches the target impedance Otherwise Match cycle NoWait NoWait The
6. 0 0 1 x x x x x x x X x x x x x 1 Type 001 for Type 1 and 010 for Type 2 2 Op 10 for Write and 01 for Read Figure 1 4 Spartan 3A 3AN 3A DSP Type 1 Packet Header For information on Spartan 3 FPGA packet formats see XAPP452 Spartan 3 Advanced Configuration Architecture Setting Bitstream Options Generating an FPGA Bitstream After specifying and compiling an FPGA design generate an FPGA bitstream using either the ISE Project Navigator or the bitstream generator command line utility BitGen The specific details of the bitstream options are described throughout this user guide Spartan 3 Generation Configuration User Guide www xilinx com 27 UG332 v1 2 May 23 2007 Chapter 1 Overview and Design Considerations Z XILINX ISE Project Navigator Figure 1 5 shows how to set options for the Bitstream Generator from within the ISE Project Navigator window Processes e Generate Programming File M HP Generate PROM ACE Rerun E Configure Device MP E Rerun alll ot Stop Open Witho Properties UG332_c1_04_120306 Figure 1 5 Setting Bitstream Generator Options from ISE Project Navigator 1 Right click Generate Programming File 2 Click Properties E Process Properties Category General Options z Startup ptions Readback Options Run Design Rules Checker DRC Create Bit File Create Binary Configuration File Create ASCII Configuration File Create
7. 142 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Daisy Chaining FPGAs located in the middle of the chain between the first and last FPGAs must from either the Spartan 3E Spartan 3A 3AN 3A DSP or Virtex 5 FPGA families These three FPGA families are the only ones that provide a CSO_B output while in Slave Parallel SelectM AP mode Spartan 3A 3AN 3A DSP Parallel NOR BPI Mode Spartan 3E FPGAs Flash 0 HswAP P5 0 PUDC B przg BUSY DOUT CCLK CSI B CSO B RDWR B INIT B PROG B DONE Master FPGA CSI B CSO B RDWR B Slave M2 Parallel M1 M1 Mode Mo INIT_B MO PROG B DONE PROG B DONE Intermediate Last FPGA in FPGAs Daisy Chain Spartan 3A 3AN 3A DSP Any Xilinx FPGA Spartan 3E Virtex 5 FPGAs UG332_c5_05_040107 Figure 5 4 Parallel Daisy Chain using BPI Mode After the master FRGA the FPGA on the top left in Figure 5 4 finishes loading its configuration data from the parallel Flash PROM the master device continues generating addresses to the Flash PROM and asserts its CSO B output Low enabling the next FPGA in the daisy chain The next FPGA then receives parallel configuration data from the Flash PROM The master FPGA s CCLK output synchronizes data capture If the FPGA s HSWAP or PUDC B pin is High then pull up resistors are disabled during configuration and an external 4 7kQ pull up resistor must be added on the CSO B pin w
8. b JTAG mode UG332 c1 02 080706 Figure 1 2 Spartan 3 Generation Downloaded Slave Configuration Modes 14 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Design Considerations The Slave Parallel mode also called SelectMAP mode in other FPGA architectures is essentially a simple byte wide processor peripheral interface including a chip select input and a read write control input The Slave Serial mode is extremely simple consisting only of a clock and serial data input The four wire JTAG interface is common on many board testers and debugging hardware In fact the Xilinx programming cables for Spartan 3 Generation FPGAs listed below use the JTAG interface for prototype download and debugging Regardless of which configuration mode is ultimately used in the application it is best to also include a JTAG configuration path for easy design development Also see Programming Cables and Headers page 193 e Platform Cable USB www xilinx com xInx xebiz designResources ip product details jsp key HW USB G e Parallel Cable IV www xilinx com xlInx xebiz designResources ip product details jsp key HW PC4 e MultiPRO Desktop Tool www xilinx com xlnx xebiz designResources ip product details jsp key HW MULTIPRO Spartan 3 Generation Configuration User Guide www xilinx com 15 UG332 v1 2 May 23 2007 Chapter 1 Overview and Design Considerations XILIN
9. General Options t7 Configuration Options H E n Readback Options Property Name IVaue Security Disable Readback Create ReadBack Data Files Allow SelectMAP Pins to Persist Create Logic Allocation File Create Mask File UG332_c1_08_091106 Figure 1 9 Bitstream Generator Readback Options 17 Click Readback Options as shown in Figure 1 9 18 By default FPGA bitstreams can be read back via JTAG Other options exist to disable FPGA readback See Basic FPGA Hardware Level Security Options page 273 19 Click OK when finished Spartan 3 Generation Configuration User Guide www xilinx com 31 UG332 v1 2 May 23 2007 Chapter 1 Overview and Design Considerations XILINX BitGen Command Line Utility For designers that prefer command line processing and to support scripting the ISE software also provides a command line bitstream generator utility called BitGen For a quick summary of available options for particular FPGA family type the command shown in Table 1 7 in a DOS box or command window Table 1 7 Command Line to Review Bitstream Generator Options per Family FPGA Family Command Line Spartan 3 FPGAs bitgen help spartan3 Spartan 3E FPGAs bitgen help spartan3e Spartan 3A FPGAs bitgen help spartan3a Spartan 3AN FPGAs bitgen help spartan3an Spartan 3A DSP FPGAs bitgen help spartan3adsp For complete documentation on the bitstream genera
10. lt Back UG332 c4 11 19 Figure 10 4 Prepare a PROM File 3 Click Next 206 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Preparing an In System Flash Programming File 4 As shown in Figure 10 5 format the FPGA bitstream or bitstreams for a PROM Supporting Multiple Design Versions ES iMPACT Prepare PROM Files lel ka want to target a C Xiling PROM C Generic Parallel PROM C 3rd Party SPI PROM v PROM Supporting Multiple Design Versions PROM File Format C TEK C UFP C format C BIN d ISE Spartan3AN Y C EXD C HEX Swap Bits Checksum Fill Value 2 Hex Digits FF PROM File Name Spartan 3 N Example J Location eee eee ey Browse Cancel UGS332 c10 02 022307 Figure 10 5 Set Options for Spartan 3AN In System Flash PROM 5 Select Spartan3AN from the drop list 6 Select a PROM File Format 7 Entera PROM File Name 8 Click Next Spartan 3 Generation Configuration User Guide www xilinx com 207 UG332 v1 2 May 23 2007 Chapter 10 Internal Master SPI Mode XILINX 9 Click the drop list to Select Device E iMPACT Spartan3AN Select Device mn Select Device xc3s700an 8388608 c3sb an 1048576 xc3s200an 4194304 Cancel UG332_c10_03_052207 Figure 10 6 Select a Spartan 3AN FPGA 10 Choose a specific Spartan 3AN FPGA device The bit size of the In System
11. MultiBoot hexadecimal value The specified value is loaded into the GENERALI and GENERAL2 registers during configuration See Spartan 3A 3AN 3A DSP MultiBoot page 257 for details on use Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 223 Chapter 11 Configuration Bitstream Generator BitGen Settings XILINX Table 11 2 Spartan 3 Generation Bitstream Generator BitGen Options Continued Pins Function Values Option Name Affected default Description Configuration CRC Checking Options See Chapter 16 Configuration CRC CRC Configuration Enable Default Enable CRC checking on the FPGA bitstream If error detected FPGA asserts INIT B Low and DONE pin stays Low Disable Turn off CRC checking Reset on err Spartan 3A No Default The FPGA halts upon encountering a configuration Spartan 3AN CRC error Spartan 3A DSP FPGA only Yes If a configuration CRC error occurs the FPGA automatically re initializes and retries the configuration process Three MultiBoot CRC attempts may occur before finally halting watchdog timer post crc en Spartan 3A No Default Disable the post configuration CRC checker Spartan 3AN Y ble th 7 k Spartan 3A DSP es Enable the post configuration CRC checker FPGA only Post configuration CRC checker post crc freq Spartan 3A 1 3 6 7 8 10 Sets the clock f
12. Gen M or JTAG File Configure Device IMPACT St Processes UG332_c4_10_110206 Figure 4 9 Double click Generate PROM ACE or JTAG File Generate Programming File 2 As shown in Figure 4 10 select Prepare a PROM File 3 iMPACT Welcome to iMPACT PIS Fi Please select an action from the list below C Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary 5can chain Prepare a PROM File Prepare a System ACE File C Prepare a Boundary Scan File C Configure devices UG332 c4 11 19 Figure 4 10 Prepare a PROM File Click Next Spartan 3 Generation Configuration User Guide www xilinx com 111 UG332 v1 2 May 23 2007 112 Chapter 4 Master SPI Mode XILINX 4 As shown in Figure 4 11 format the FPGA bitstream or bitstreams for a 3rd Party SPI PROM This option automatically invokes the spi option for generating the PROM file iMPACT Prepare PROM Files lel Es want to target a C Xilins PROM C Generic Parallel PROM 3rd Party SPI PROM C PROM Supporting Multiple Design Versions Spartan3E MultiBoot z PROM File Fo C TEK C UFP C format C EXO BIN fo IS C HEX F Swap Bits Checksum Fill Value 2 Hex Digits FF MySPIFlashPROM Location C Data my designs led crazy PROM File Name W Browse Cancel UG332_c4_12_110206 Figur
13. Program or Reset FPGA PROG B The PROG B pin is an asynchronous control input to the FPGA When Low the PROG B pin resets the FPGA initializing the configuration memory When released the PROG_B begins the configuration processes The initialization process does not start until PROG B returns High Asserting PROG B Low for an extended period delays the configuration process The various PROG B functions are outlined in Table 2 7 Spartan 3 Generation Configuration User Guide www xilinx com 39 UG332 v1 2 May 23 2007 Chapter 2 Configuration Pins and Behavior during Configuration XILINX At power up or after a master reset PROG B always has a pull up resistor to Vecaux regardless of the Pull Up Resistors During Configuration control input After configuration the bitstream generator option ProgPin defines whether or not the pull up resistor is remains active By default the ProgPin option retains the pull up resistor Table 2 7 PROG B Operation PROG B Input Response Internal Power On Reset POR circuit automatically initiates FPGA Power u P configuration process Low going pulse Initiate re configuration process and continue to completion Ext nded Low Initiate re configuration process and stall process in the Clear Configuration Memory Initialization step Configuration is stalled o until PROG_B returns High If the configuration process is started continue to completion
14. L rECeYa te rRidv ad 277 Spartan 3A 3AN 3A DSP Unique Device Identifier Device DNA 278 Identifier Values unde uestes ento lee dated tuc editae erect oed dente Mek bs 278 Operation 2 epe pe ERE ees a e ee Oe s RU es Ya teas dies energie 278 Intertace Duming i ie eis CAE serae e RR EHbeSeeUREE PER EMO ERR eR n saci oe 279 Identifier Memory Specifications 2 6666s 280 Extending Identifier Length 0 0 6 0 occ eens 280 JTAG Access to Device Identifier 0 eens 281 Authentication Design Examples ss esceedeeE rer RR weber navn ae RR n 281 Spartan 3A 3AN 3A DSP FPGA Imprinting or Watermarking the Configuration PROM with Device DNA creari ia esa eg de rune edge ei eg HERREN e E EORR ale Ha dani ne 282 Spartan 3E FPGA Leveraging Security Features in Select Commodity Flash PROMs283 Spartan 3A 3AN 3A DSP FPGA Authenticating a Downloaded Design 285 Authenticating any FPGA Design Using External Secure PROM 286 Handling Failed Authentications 0 0 287 No Functionality legi i niet EEA Rae Peis hie PS bao dea i 287 Limited Functionality 22 2 isses eR cree cies heed isid cede ped netia 287 Full Functionality with Time Out 066s 288 Active Defense si ics cred erie ied esc ie rele br e ke epi XR V Er AR eed 288 Authentication Algorithm 0 00 cece cece e 288 Manufacturing Logistics 2 0 0 2 sicvissenieiied jivddnesweniiadieeneteed anions 288 Addition
15. The processor deasserts CSI B and the data on D 7 0 is ignored The processor deasserts CSI B and the data on D 7 0 is ignored A D 7 0 data byte is loaded on the rising CCLK edge 10 A D 7 0 data byte is loaded on the rising CCLK edge 29 90 ML Oe ven Spartan 3 Generation Configuration User Guide www xilinx com 173 UG332 v1 2 May 23 2007 Chapter 7 Slave Parallel SelectMAP Mode XILINX 11 The processor deasserts CSI_B and the data on D 7 0 is ignored 12 A D 7 0 data byte is loaded on the rising CCLK edge 13 A D 7 0 data byte is loaded on the rising CCLK edge 14 A D 7 0 data byte is loaded on the rising CCLK edge Pausing CCLK DATAI 0 77777777777777777 y Se NIIT e XT XT UG332 c7 07 081106 Figure 7 7 Non Continuous SelectMAP Data Loading with Controlled CCLK The following numbered items correspond to the markers provided in Figure 7 7 1 The D 7 0 data pins are high impedance Hi Z while CSI B is deasserted 2 RDWR B has no effect on the device while CSI B is deasserted 3 CSI B is asserted by the processor The FPGA captures configuration data on rising CCLK edges A D 7 0 data byte is loaded on the rising CCLK edge A D 7 0 data byte is loaded on the rising CCLK edge A D 7 0 data byte is loaded on the rising CCLK edge SelectMAP ABORT An ABORT is an interruption in the SelectMAP configuration process or in the Readback sequence that occurs if the RDWR B pin changes stat
16. USER1 and USER Registers The USERI and USER2 registers are only available after configuration These two registers if used in the application must be implemented using FPGA logic The Boundary Scan BSCAN library primitive is required when creating these registers This primitive is only required for driving internal scan chains USER1 and USER2 These registers can be accessed after they are defined via the JTAG interface A common input pin TDI and shared output pins represent the state of the TAP controller RESET SHIFT and UPDATE Using Boundary Scan in Spartan 3 Generation FPGAs Figure 9 5 shows an example timing waveform for boundary scan operations Timing specifications for the relationships shown in Figure 9 5 are listed in the data sheet for each Spartan 3 Generation FPGA family Trkmpo ToO X Xaa X gt Data to be cptued O Owo y Data to be driven out Data Valid KY UG332_c9_05_081506 Figure 9 5 Spartan 3 Generation Boundary Scan Timing Waveforms 192 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Programming Cables and Headers Programming Cables and Headers Xilinx provide various programming cables that support the design and development phase of a project e Platform Cable USB www xilinx com xInx xebiz designResources ip_product_details jsp key HW USB G e Parallel Cable IV www xilinx
17. from the Processes pane as shown in Figure 9 7 Processes NO Generate Programming File Proarammina File Generation Report enera M A T e ap Processes Figure 9 7 Double click Configure Device iMPACT UG332 c9 14 112006 2 As shown in Figure 9 8 select Configure devices using Boundary Scan JTAG 194 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Programming an FPGA Using JTAG iMPACT Welcome to iMPACT C X Please select an action from the list below Configure devices using Boundary Scan JTAG Automatically connect to a cable and identity Boundary Scan chai C Prepare a PROM File Prepare a System ACE File C Prepare a Boundary Scan File SVF X Configure devices using Slave Serial mode A lt Back 3 Figure 9 8 Configure Devices Using JTAG 3 Ifthe board is powered and the Xilinx programming cable properly connected the iMPACT software automatically initializes the JTAG chain and detects the various devices on the chain Click Finish 5 As shown in Figure 9 9 the iMPACT software automatically detected the devices on the chain In this example a Xilinx XC3S500E Spartan 3E FPGA is first in the chain followed by a Xilinx XCF045 Platform Flash PROM followed by a Xilinx XC2C64A CPLD in the final position The devices are yet unprogrammed iMPACT C Datamy desi
18. As shown in Figure 15 4 the Device DNA value is 57 bits long The two most significant bits are always 1 and 0 The remaining 55 bits are unique to a specific Spartan 3A 3AN 3A DSP FPGA Operation Figure 15 4 shows the general functionality of the DNA PORT design primitive An FPGA application must first instantiate the DNA PORT primitive shown in Figure 15 3 within a design To read the Device DNA the FPGA application must first transfer the identifier value into the DNA PORT output shift register Assert the READ input during a rising edge of CLK as shown in Table 15 5 This action parallel loads the output shift register with all 57 bits of the identifier Because bit 56 of the identifier is always 1 the DOUT output is also 1 The READ operation overrides a SHIFT operation To continue reading the identifier values assert SHIFT followed by a rising edge of CLK as shown in Table 15 5 This action causes the output shift register to shift its contents toward the DOUT output The value on the DIN input is shifted into the shift register Caution Avoid a Low to High transition on SHIFT when CLK is High as this causes a spurious initial clock edge Ideally only assert SHIFT when CLK is Low or on a falling edge of CLK 278 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Spartan 3A 3AN 3A DSP Unique Device Identifier Device DNA SHIFT 1 0 RE
19. CHECK IFF REQUEST UG332_c16_10_120406 Figure 15 14 FPGA Authentication Using SHA 1 Secure EEPROM The FPGA configures normally from any configuration PROM Alternatively the FPGA bitstream can be downloaded using one of the Slave configuration modes The FPGA application contains an Authentication Core that communicates to an external DS2432 secure EEPROM The authentication challenge between the FPGA and the EEPROM uses a random number and SHA 1 hashing to thwart attacks If the authentication challenge fails the FPGA application is disabled Similarly the FPGA application can re authenticate the design at any time during normal operation This application is discussed in more detail in Xilinx application note XAPP780 The Spartan 3E Starter Kit board includes all the necessary components e XAPP780 FPGA IFF Copy Protection Using Dallas Semiconductor Maxim DS2432 Secure EEPROMs http www xilinx com bvdocs appnotes xapp780 pdf e DS24321Kb Protected 1 Wire EEPROM with SHA 1 Engine http www maxim ic com quick view2 cfm qv pk 2914 e Spartan 3E Starter Kit http www xilinx com s3estarter 286 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Handling Failed Authentications Although not supported by an application note or example design similar solutions are possible using external components with similar security features such as the following e STMicroe
20. CPU Code Decrypter Data Memory Instruction Memory Device DNA Figure 15 15 Spartan 3A 3AN 3A DSP Device DNA Used as an Key to Protect Embedded Processing Applications UG332 c16 14 092806 U S Legal Protection of FPGA Configuration Bitstream Programs The FPGA configuration bitstream program may qualify as a computer program as defined in Section101 Title 17 of the United States Code and as such may be protected under the copyright law It may also be protected as a trade secret if it is identified as such Xilinx suggests that a company wishing to claim copyright and or trade secret protection in the FPGA configuration bitstream consider taking the following steps Spartan 3 Generation Configuration User Guide www xilinx com 289 UG332 v1 2 May 23 2007 Chapter 15 Protecting FPGA Designs XILINX Place an appropriate copyright notice on the FPGA or adjacent to it on the printed circuit board PCB giving notice to third parties of the copyright For example because of space limitations this notice on the FPGA device could read 2006 XYZ Company or if on the PCB could read Bitstream 2006 XYZ Company File an application to register the copyright claim for the bitstream program with the U S Copyright Office If practicable given the size of the printed circuit board notice should also be given that the user is claiming that the bit stream program is the company s trade secret A sta
21. Chapter 12 Sequence of Events XILINX Table 12 4 Spartan 3 Generation FPGA Array ID Codes 32 bit Array Identifier 4 bit Revision 28 bit Vendor Array Identifier FPGA Family FPGA Array Code hexadecimal XC3S50 0x14 OC 093 XC3S200 0x14 14 093 XC3S400 0x14 1C 093 Spartan 3 XC3S1000 0x14 28 093 FPGAs XC3S1500 0x14 34 093 XC3S2000 0x14 40 093 XC3S4000 0x14 48 093 XC3S5000 0x14 50 093 The FPGA indicates if the array value does not match by setting Bit 1 ID Err in the STAT Status register as shown in Table 12 5 There are various methods to read the status register including via JTAG using the Xilinx iMPACT software or by using the Select MAP interface Table 12 5 STAT Register Name Bit Description 0 Array ID value matched expected value ID Err 1 t Array ID value embedded in bitstream does not match the value read from the FPGA Load Configuration Data Frames Steps 2 3 4 5 l l l 1 7 8 Wake from Clear Reset Configuration power onor Memory M 2 0 VS 2 0 PROG B Sample Control Startup Synchronization Array ID CRC Check Sequence Check Bitstream Loading Setup Finish UG332 c12 07 110406 a Start Figure 12 9 Load Configuration Data Frames After the synchronization word is loaded and the array ID is checked the configuration data frames are loaded 232 www xilinx com S
22. FPGA array size while the additional four bits are a mask revision code which varies between 0x0 to OxF There are three components to the 28 bit vendor array identifier value The least significant 12 bits 0x093 represent the Xilinx vendor code 0x49 appended to the least significant which is always 1 resulting in the value 0x093 These 12 bits are consistent for all Spartan 3 Generation FPGAs The most significant 8 bits represent the FPGA family code 0x22 Spartan 3A family 0x26 Spartan 3AN family 0x38 Spartan 3A DSP family 0x1C Spartan 3E family 0x14 Spartan 3 family The middle 8 bits represent an array specific code Table 12 4 Spartan 3 Generation FPGA Array ID Codes 32 bit Array Identifier 4 bit Revision 28 bit Vendor Array Identifier FPGA Family FPGA Array Code hexadecimal XC3S50A 0x22 10 093 XC3S200A 0x22 18 093 Spartan 3A FPGAs XC3S400A 0x22 20 093 XC3S700A 0x22 28 093 XC3S1400A 0x22 30 093 XC3S50AN 0x26 10 093 XC3S200AN 0x26 18 093 Spartan 3AN FPGAs XC3S400AN 0x26 20 093 XC3S700AN 0x26 28 093 XC3S1400AN 0x26 30 093 Spartan 3A DSP XC3SD1800A 0x38 40 093 FPGAs XC3SD3400A 0x38 4E 093 XC3S100E Ox1C 10 093 XC3S250E Ox1C 1A 093 Spartan 3E p FPGAs XC3S500E Ox1C 22 093 XC3S1200E Ox1C 2E 093 XC3S1600E Ox1C 3A 093 Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 231
23. PUDCB PUDC_B PUDC B PUDC B PUDC B PUDC B 0 Yes 0 0 0 0 1 1 1 2 Yes 0 0 1 1 0 1 1 2 Yes 0 1 1 0 1 1 0 2 E CCLK CCLK CCLK CCLK CCLK 2 OUTPUT OUTPUT OUTPUT INPUT INPUT Yes INIT B INIT B INIT B INIT B INIT B INIT B 2 CSO B CSO B CSO B 2 DOUT DOUT DOUT DOUT DOUT 2 MOSI CSI B CSI B 2 D 7 1 D 7 1 2 DIN DIN DO DIN DO 2 RDWR_B RDWR_B 2 Yes VS 2 0 VS 2 0 2 A 25 0 1 LDC2 1 LDC1 1 M LDCO 1 HDC 1 Notes 1 Gray shaded cells represent pins that are in a high impedance state Hi Z floating during configuration These pins have an optional internal pull up resistor to their respective Vcco supply pin that is active throughout configuration if the PUDC_B input is Low See Pull Up Resistors During Configuration page 46 2 The Spartan 3E HSWAP pin and the Spartan 3A 3AN 3A DSP PUDC_B pin have identical behavior just different names See Pull Up Resistors During Configuration page 46 3 The Internal Master SPI mode M 2 0 lt 0 1 1 gt is only available on the Spartan 3AN FPGA family Vecayx must be 3 3V when using this mode 4 CCLK is always in input pin in Slave configuration modes For Master modes CCLK must be treated as a bidirectional I O pin for Spartan 3E FPGAs and is an output pin for Spartan 3A 3AN 3A DSP FPGAs 5 The BUSY output is not required an
24. SRL16 Logic LUT LUTRAM SRL16 LUTRAM SRL16 C checker Tar All flip flop and latch bits are automatically ignored All other writable bits such as distributed RAM LUTRAM and SRL16 shift registers found in SLICEM slices are also ignored If used only as logic these LUTs can be optionally included in the CRC calculation Cyclic Redundancy Checker CRC Internal pull u resistor to VCCO 2 VCCO 2 Calculated CRC Open drain output The internal oscillator is the most common clock source However see Clock Source for additional information If the calculated CRC value does not match the expected CRC the FPGA drives the INIT B pin Low UG332_c17_01_092006 Figure 16 1 Conceptual Overview of Post Configuration CRC Calculator If the POST_CRC ENABLE configuration constraint is set then the CRC checker circuit continuously scans the FPGA bitstream calculates a resulting CRC value then compares this value against a previously calculated expected CRC value If there is a difference between the two CRC check values then the CRC checker flags the error by driving the FPGA s INIT_B pin Low The calculated CRC value changes if any unmasked bit in any location changes for any reason Obviously the FPGA application will modify some locations during the course of normal operation Consequently all writable bits such as flip flops latches
25. The TDO serial data output of the last device in the chain feeds back to the JTAG connector Lastly Figure 1 3c shows a parallel daisy chain All of the FPGA connections are common except for the chip select inputs which are unique per FPGA Caution The Spartan 3AN FPGA family does not support configuration daisy chains when configured using the Internal Master SPI mode Spartan 3 Generation Configuration User Guide www xilinx com 17 UG332 v1 2 May 23 2007 Chapter 1 Overview and Design Considerations XILINX Xilinx Xilinx Xilinx First FPGA FPGA FPGA FPGA DIN CCLK DOUT a Serial Daisy Chain using Slave Serial mode Xilinx Xilinx Xilinx FPGA FPGA FPGA b Multi FPGA configuration JTAG mode DATA 7 0 Spartan 3 Spartan 3 Generation Generation FPGA FPGA Select FPGA1 Select FPGA2 c Parallel Daisy Chain using Slave Parallel mode UG332 c1 03 080706 Figure 1 3 Spartan 3 Generation Configuration Daisy Chain Options Is the easiest possible configuration solution the more important consideration Let s face it in some applications the easiest solution is the best solution The best solution for these applications is either Internal Master SPI mode supported only by Spartan 3AN FPGAs or Master Serial mode using a Xilinx Platform Flash PROM which is available for any Spartan 3 Generation FPGA These solutions use the fewest FPGA pins have flexible I O voltage support and is
26. This pattern is shifted out onto TDO LSB first while an instruction is shifted into the instruction register from TDI To invoke an operation load the desired OPCODE from Table 9 4 into the Instruction Register IR The length of the instruction register varies by device type However the IR is six bits wide for all Spartan 3 Generation FPGAs Note n general all JTAG OPCODEs are identical among Spartan 3 Generation FPGA families However the EXTEST instruction is different between Spartan 3 FPGAs and FPGAs from the Spartan 3E or Spartan 3A 3AN 3A DSP families Table 9 4 Spartan 3 Generation Boundary Scan Instructions Boundary Scan Command Instruction Description EXTEST Enables Boundary Scan EXTEST operation Spartan 3E Spartan 3A 3AN 001111 Spartan 3A DSP FPGAs EXTEST 000000 Spartan 3 FPGA SAMPLE 000001 Enables Boundary Scan SAMPLE operation USER1 000010 Access user defined register 1 USER2 000011 Access user defined register 2 CFG_OUT 000100 Access the configuration bus for readback CFG_IN 000101 Access the configuration bus for configuration INTEST 000111 Enables Boundary Scan INTEST operation USERCODE 001000 Enables shifting out user code IDCODE 001001 Enables shifting out of ID code HIGHZ 001010 3 state output pins while enabling BYPASS Register JPROGRAM 001011 Equivalent to and has the same effect as PROGRAM JSTART od Clocks the startup sequence when Startup
27. esee 48 Pin Description coeno bI aero E ESO HORE IRE weed EROR ICE CREE OS 50 Pin Behavior During Configuration sussusessssseeeeeeee 54 Spattan93E EDGAS xia aed ha bea p aE iced dea Ma qiie ds 55 Spartan 3 Generation Configuration User Guide www xilinx com UG332 v1 2 May 23 2007 EZ XILINX Spartan 3A 3AN 3A DSP FPGA isssssss en 56 Spattan 9 FPGA Sre sca coat eancet edens boafea Qa deed a d acces deed aad 57 Default I O Standard During Configuration 0 0005 57 Design Considerations for the HSWAP M 2 0 and VS 2 0 Pins 58 Dedicating the HSWAP PUDC B M 2 0 and VS 2 0 Pins isses 59 Reusing HSWAP PUDC B M 2 0 and VS 2 0 After Configuration 59 Spartan 3E HSWAP Considerations liss eee 59 Dual Purpose Pins Become User I O 0 0 0 0 ccc eee ee 60 Chapter 3 Master Serial Mode Master Serial Mode Connections 0 0 0 cece cece cee eee 67 Voltage Compatibility isses 68 Platformi Flash PROM J tette rele sce pactis Sek ert e et te on 68 FPGA ie eerte ee bte ce de e NU UR RUE ec NOI ERR E ent ab eh gl d estate es 68 Spartan 3E and Spartan 3A 3A DSP FPGAs with Vocayx at 2 5V oo eee eee eee 68 Spart n 3 EPGAS deserto he EXER Rhen acid spiri Adi ide ewes 68 JEAG Interface 22 brit ety mee Re Edea a Rx De UR Ree de een Races 68 Supported Platform Flash PROMs sss see 69 CCLK Preque cyasiss
28. flexible and changeable The algorithm need only be as simple or complex as required by the application being protected The algorithm can be changed between design releases or versions Similarly multiple and different authentication checks can co exist in the same application This approach tunes the cost and complexity of security to the needs of the application Manufacturing Logistics Authentication simplifies manufacturing logistics especially for high volume applications built at contract manufacturers e There are no special keys that need to be programmed into the FPGA There is aa programming step where the PROM is married to or authenticated with either the FPGA s Device DNA the PROM s Unique ID or both but this operation does not affect the FPGA bitstream e The FPGA bitstream is common to all units There is no need to match a bitstream to a specific FPGA or a set of FPGAs The authentication step can be completely separate from bitstream programming e Configuration PROMs can be bulk programmed There is no need to match a PROM to a specific FPGA or a set of FPGAs during high volume manufacturing The authentication step can occur at any time such as in final system test in a secure facility or at the end customer site 288 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Additional Uses of Authentication and Device ID e Using the Limited Functionality
29. hus 0xC0000 MultiBoot Spartan 3A PEE Bitstream 1 Aup nitial Bitstream XC3S700A EN lu Always at 0 0x0 UG332 c14 19 082106 Figure 14 11 Spartan 3A MultiBoot Example using XC3S700A and SPI Flash 1 Invoke the iMPACT programming software 2 As shown in Figure 14 3 choose Prepare a PROM File 264 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Spartan 3A 3AN 3A DSP MultiBoot iMPACT Welcome to iMPACT me x Please select an action from the list below C Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain Prepare a PROM File C Prepare a System ACE File Prepare a Boundary Scan File C Configure devices using Slave Serial mode Cancel UG332_c14_04_112906 Figure 14 12 Prepare a MultiBoot PROM Image 3 Click Next 4 Asshownin Figure 14 13 target a PROM Supporting Multiple Design Revisions Spartan 3 Generation Configuration User Guide www xilinx com 265 UG332 v1 2 May 23 2007 Chapter 14 Reconfiguration and MultiBoot XILINX iMPACT Prepare PROM Files Eel Xx want to target a C Xiling PROM Generic Parallel PROM We 3rd Party SPI PROM PROM Supporting Multiple Design Versions Spartan34 MultiBoot v PROM File Forma MCS EK C UFP C format C EXO C BIN ISL PROM File Name MySpartan 34
30. 1 XC3S400AN 1 024 0x08 0000 0x04 0000 XC3S700AN 1 536 OxOC 0000 0x06 0000 XC3S1400AN 1 280 0x14 0000 OxOA 0000 14 By default leave this option box unchecked Check this box only if the intended Spartan 3AN target was previously and specifically programmed to support the optional Power of 2 addressing mode See UG333 Spartan 3AN In System Flash User Guide for more information 15 Click Next Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com Chapter 10 Internal Master SPI Mode XILINX 16 As shown in Figure 10 8 review that the settings are correct to format the Spartan 3AN In System Flash Click Finish to confirm the settings or Back to change the settings EE iMPACT File Generation Summary fel Ed You have entered following information PROM Type Spartan34N Device File Format mes Fill Value fp PROM filename Spartan 34N_Example Number of PROMs 1 xc3s700an Click Finish to start adding device files UG332_c10_05_022307 Figure 10 8 Review Spartan 3AN In System Memory Formatting Settings 17 As shown in Figure 10 9 click OK to start adding FPGA configuration bitstreams to the In System Flash image ES add Device d Look in C3 switches leds Pe My Recent Documents Start adding device File to First Bitstream ngo y _xmsgs top level bit 3 MET File name top levet
31. 14 3 uses 20 steps and consequently 20 CLK cycles and 20 memory locations The sequence can be shortened to 12 CLK cycles by making the following simple changes e Align the next MultiBoot address to a 16 bit 64K boundary and pre assign the contents of the GENERAL register to 0x0000 by setting the next config addr 00000000 bitstream generator option The next MultiBoot address is then selectable solely by writing to the GENERAL2 register This eliminates the four steps between CLK cycles 3 and 6 e Keep the next MultiBoot address within the same PROM For example if the FPGA booted from SPI serial Flash then jump to the next MultiBoot within the same SPI Flash This eliminates the four steps between CLK cycles 11 and 14 Table 14 3 Command Sequence to Initiate MultiBoot to a Specified Address CLK High or Cycle Command Low Byte DO D1 D2 D3 D4 D5 D6 D7 Hex 1 High 1 0 1 0 1 0 1 0 oxaa SYNC WORD 2 Low 1 0 0 1 1 0 0 1 ox99 3 Type 1 Write GENERALI see pow po qoe mue qm esse 4 1 Word Low 0 1 1 0 0 0 0 1 ox61 5 Lower 16 bits of MultiBoot High A15 A14 A13 A12 A11 A10 A9 A8 6 Address Low A7 A6 AS A4 A3 A2 Al AO 7 Type 1 Write GENERAL2 High O 7 O 7 1 1 O O 1 0 0x2 8 1 Word Low 1 0 olol o 0 0 1 oxe1 9 Upper bits of MultiBoot Address High
32. 14 98414 G06 14 98464 G61 14 www fciconnect com Comm Con 2475 14G2 2422 14G2 2401R G2 14 www commcon com Connectors Notes 1 Some manufacturer pin assignments may not conform to Xilinx pin assignments Please refer to the manufacturer s data sheet for more information 2 Additional ribbon cables can be purchased separately from the Xilinx Online Store www xilinx com store Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 193 Chapter 9 JTAG Configuration Mode and Boundary Scan XILINX Pin 2 of the connector provides a reference voltage for the output buffers that drive the TDI TCK and TMS pins Because these pins are powered by Vecayx on Spartan 3 Generation FPGAs connect the Vecayx supply to pin 2 of the connector Programming an FPGA Using JTAG The JTAG interface is also a convenient means for downloading an FPGA design during development and debugging First generate an FPGA bitstream as described in Setting Bitstream Options Generating an FPGA Bitstream page 27 The following steps graphically describe how to create a PROM file using iMPACT from within the ISE Project Navigator This particular example shows how to configure the XC3S500E FPGA on the Spartan 3E Starter Kit board Besides the FPGA the JTAG chain on the board includes a Xilinx Platform Flash PROM and a Xilinx CPLD 1 From within the ISE Project Navigator double click Configure Device IMPACT
33. 3td Party SPI PROM C PROM Supporting Multiple Design Versions Spartan3E MultiBoot zj PROM File Format 5 6 MCS TEK C UFP E format C EXO C BIN ISC C HEX Swap Bits Checksum Fill Value 2 Hex Digits FF PROM File Name MyParallelNORFlash 29 Location C Data my_designs led_crazy Browse Cancel UG332 c5 10 111806 Figure 5 9 Set Options for a Generic Parallel PROM 5 Select a PROM File Format 6 Name the output PROM File Name 7 Click Next 150 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Preparing an Parallel NOR Flash PROM File 8 As shown in Figure 5 10 select the Parallel PROM Density measured in bytes This example uses a 32 Mbit Flash PROM equivalent to 4 Mbytes iMPACT Specify Parallel PROM Device Auto Select PROM Select a Parallel PROM Density Bytes 4M 4194304 E Delete All reate BPI Mode PROM Number af Data Streams 1 BPI Master Device Family Loading Direction Spartan 3E Data Stream O Start Address Spartan 34 Maximum amp hex digits C Vitex5 Downstream D aisy Chain Type Parallel Serial UG332_c5_12_111806 Figure 5 10 Select Parallel PROM Size and Configuration Style 9 Click Add 10 The selected PROM size appears in the 0 position The Master BPI mode uses a single PROM 11 Check Create BPI mode PROM 12 Choose whether
34. 4 7 page 104 for an example Caution The Spartan 3AN FPGA family does not support configuration daisy chains when configured using the Internal Master SPI mode Where to go for debugging support This user guide attempts to make FPGA configuration easy and straight forward Should problems occur please visit the interactive Configuration Debug Guide to you through the configuration debugging process e Configuration Debug Guide beta http survey xilinx com ss wsb dll Xilinx Configuration Debug Guide htm Spartan 3 Generation Configuration User Guide www xilinx com 23 UG332 v1 2 May 23 2007 Chapter 1 Overview and Design Considerations XILINX FPGA Configuration Bitstream Sizes By default FPGA configuration images are uncompressed In an uncompressed FPGA bitstream the size of the image is constant regardless of the complexity of the underlying FPGA application Put another way a single inverter requires the same bitstream size as a complex MPEG4 encoder implemented in the same FPGA array Uncompressed Bitstream Image Size Table 1 4 provides the number of bits in an uncompressed FPGA bitstream for each specific part number of the Spartan 3 Generation Table 1 4 Number of Bits in an Uncompressed FPGA Bitstream Image Spartan 3 Generation Number of FPGA Family FPGA Part Number Configuration Bits XC3550A AN 437 312 XC38200A AN 1 196 128 Spartan 3A 3
35. 5V Spartan 3E FPGAs always have VccAux 2 9V Spartan 3A and Spartan 3A DSP FPGAs support both Vecaux 2 5V or 3 3V Table 3 1 page 64 lists the FPGA PROM connections e Figure 3 2 page 65 illustrates the Master Serial configuration interface for Spartan 3A 3AN 3A DSP FPGAs when VccAux 3 3V Spartan 3AN FPGAs always have Vecaux 3 3V Table 3 1 page 64 lists the FPGA PROM connections e Figure 3 3 page 66 illustrates the Master Serial configuration interface for Spartan 3 FPGAs Spartan 3 Generation Configuration User Guide www xilinx com 63 UG332 v1 2 May 23 2007 Ch apter 3 Master Serial Mode EZ XILINX Serial Master Mode o o o JTAG Voltage Resistors dg ARS dsa ve ueueds Ve ueue 1 2V VCCINT XILINX Spartan 3E Spartan 3A 2 5V XCFxxS 3 3V XCFxxP 1 8V VCCINT DO VCCO CLK OE RESET XILINX Platform Flash XCF Spartan 3A DSP 2 5V A 3 So re vg ac 50 et Eel x _2 Dedicated internal pull up resistor Figure 3 1 UG332 c3 03 040107 Master Serial Mode Using Platform Flash PROM Spartan 3E or Spartan 3A 3A DSP FPGA VccAyx 2 5V Table 3 1 Spartan 3E Spartan 3A 3A DSP FPGA Connections Platform Flash FPGA Pin PROM Pin Comments DIN DO CCLK CLK Watch signal integrity on this trace See CCLK Design Considerations page 42 INIT_B OE RESET FPGA resets PROM during initialization
36. A E PROM File Form SPI IMPACT Modes PRON l 15M 43 36 96 Full xc3s700a Figure 14 19 Generate the PROM File Using the Specified Parameters 28 The iMPACT software successfully generates a PROM file using the name specified in Step 7 with the format and file extension specified in Step 6 The file is created in the current directory A PROMGen Report File is also created Configuration Watchdog Timer CWDT and Fallback Spartan 3A 3AN 3A DSP FPGAs contain a configuration watchdog timer CWDT The CWDT provides protection against errant MultiBoot operations such as the following e MultiBoot operations to an invalid start location e MultiBoot operations to a valid start location but loaded with an invalid configuration bitstream The CWDT is a 16 bit counter clocked by the CCLK configuration clock signal Upon any FPGA configuration operation be it from a PROG B pulse or a MultiBoot event the CCLK clock begins operation at its lowest ConfigRate setting which is approximately 1 MHz The CWDT expires 64K clock cycles after the start of configuration or in approximately 65 ms If during a MultiBoot operation the FPGA does not see a valid configuration synchronization word before the CWDT expires then the FPGA will automatically fallback to the default bitstream located at address 0 The FPGA automatically reconfigures from 270 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23
37. ACE or JTAG File 2 As shown in Figure 3 8 select Prepare a PROM File iMPACT Welcome to iMPACT Be E Please select an action from the list below C Configure devices using Boundary Scan JTAG Automatically connect to a cable and identify Boundary Scan chain Prepare a PROM File Prepare a System ACE File C Prepare a Boundary Scan File C Configure devices UG332 c4 11 19 Figure 3 8 Prepare a PROM File Spartan 3 Generation Configuration User Guide www xilinx com 75 UG332 v1 2 May 23 2007 Chapter 3 Master Serial Mode XILINX 3 Click Next 4 Asshownin Figure 3 9 format the FPGA bitstream or bitstreams for a Xilinx PROM iMPACT Prepare PROM Files C x want to target a Xilinx PROM C Generic Parallel PROM C 3rd Party SPI PROM PROM Supporting Multiple Design Versions Spartan3E MultiBoot PROM File Format MCS UFP E format C EXO BIN ISC C HEX Swap Bits Checksum Fill Value 2 Hex Digits FF PROM File Name MyPlatformFlash Location C Data my_designs led_crazy Browse lt Back Figure 3 9 Set Options for Xilinx Platform Flash PROM 5 Select a PROM File Format 6 Enter a PROM File Name 7 Click Next 76 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Preparing an Platform Flash PROM File 8 As shown in
38. Behavior during Configuration XILINX The Spartan 3 FPGA family uses dedicated configuration pins as shown in Table 2 11 The post configuration behavior is controlled by bitstream settings Table 2 11 Pins with Dedicated Pull Up Resistors during Configuration Spartan 3 FPGA Family Only Pull Up Resistor Pin Name Supply Rail Post Configuration Control M2 VCCAUX M2Pin BitGen setting M1 VCCAUX M1Pin BitGen setting MO VCCAUX MOPin BitGen setting CCLK VCCAUX CclkPin BitGen setting Pins with Optional Pull Up Resistors during Configuration All user I O pins input only pins and dual purpose pins that are not actively involved in the currently selected configuration mode are high impedance floating three stated Hi Z during the configuration process These pins are indicated in Table 2 16 as gray shaded table entries or cells A control input determines whether all user I O pins input only pins and dual purpose pins have a pull up resistor to the supply rail or not The control input has different names on different FPGA families as shown in Table 2 12 but all function similarly When the control is Low each pin has an internal pull up resistor that is active throughout configuration starting immediately on power up After configuration pull up and pull down resistors are available in the FPGA application by instantiating PULLUP or PULLDOWN primitive or by applying similarly named constraints to a sp
39. Byte Wide Peripheral Interface BPI Connections Continued Pin Name HDC FPGA Direction Output Description PROM Write Enable During Configuration Connect to PROM write enable input WE FPGA drives this signal High throughout configuration After Configuration User I O LDC2 Output PROM Byte Mode This signal is not used for x8 PROMs For PROMs with a x8 x16 data width control connect to PROM byte mode input BYTE See Precautions Using x8 x16 Flash PROMs FPGA drives this signal Low throughout configuration User I O Drive this pin High after configuration to use a x8 x16 PROM in x16 mode Spartan 3E FPGAs A 23 0 Spartan 3A Spartan 3AN Spartan 3A DSP FPGAs A 25 0 Output Address Connect to PROM address inputs High order address lines may not be available in all packages and not all may be required Number of address lines required depends on the size of the attached Flash PROM Spartan 3E FPGA address generation controlled by MO mode pin Addresses presented on falling CCLK edge User I O D 7 0 Input Data Input FPGA receives byte wide data on these pins in response the address presented on A 23 0 or A 25 0 Data captured by FPGA falling edge of CCLK User I O CSO_B Output Chip Select Output Active Low Not used in single FPGA applications In a daisy chain configuration this pin connects to the CSI_B pin of the next FPGA
40. CSI B has been asserted because this triggers an ABORT See SelectMAP ABORT page 174 3 If CSI_B is tied Low BUSY drives Low before INIT B returns High 4 The FPGA samples the M 2 0 mode select pins when INIT B goes High 5 Assert RDWR B before CSI B to avoid causing an abort 6 CSI Bis asserted enabling the SelectMAP interface 7 BUSY Spartan 3 3E only remains in High Z state until CSI B is asserted 8 The first D 7 0 byte is loaded on the first rising CCLK edge after CSI B is asserted 9 The configuration bitstream is loaded one byte per rising CCLK edge 10 After the last byte is loaded the FPGA enters the Startup sequence 11 The startup sequence lasts a minimum of eight CCLK cycles 12 The DONE pin goes High during the startup sequence Additional CCLK cycles can be required to complete the startup sequence See Startup page 233 13 After configuration has finished the CSI B signal can be deasserted 14 After the CSI B signal is deasserted RDWR B can be deasserted 172 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Non Continuous SelectMAP Data Loading Non Continuous SelectMAP Data Loading Non continuous data loading is used in applications where the processor or controller cannot provide an uninterrupted stream of configuration data This may occur for example if the controller pauses configuration while it fetches additional data switche
41. Clear T Load Start Reset Configuration Synchronization Array ID Configuration CRC Check qus Check g Sequence power on or Memory Data PROG B Bitstream Loadin m Start 9 Finish UG332 c12 04 110406 Figure 12 6 Sample Control Pins Mode Select Variant Select When the INIT B pin returns High after initialization the FPGA samples the M 2 0 mode select pins and the VS 2 0 variant select pins Shortly after the FPGA begins driving CCLK if the M 2 0 mode select pins define one of the Master configuration modes The VS 2 0 values are only used in Master SPI configuration mode At this point the FPGA begins sampling the configuration data input pins on the rising edge of the configuration clock Delaying Configuration There are three methods to delay configuration for Spartan 3 Generation FPGAs 1 Hold the PROG B pin Low which holds the FPGA in reset Step 1 shown in Figure 12 2 page 225 2 Hold the INIT B pin Low during initialization which stalls the configuration process in Step 2 shown in Figure 12 5 page 228 However after the FPGA releases INIT B High the application cannot subsequently delay configuration by pulling INIT B Low 3 Hold the DONE pin Low which prevents the FPGA from completing the Startup Sequence shown as Step 8 in Figure 12 11 page 233 Bitstream Loading Steps 4 7 The bitstream loading process is similar for all configuration modes the primary difference between modes is th
42. DRCK2 RESET SEL1 SEL1 SEL2 SHIFT TDI TDO2 UPDATE SEL2 SHIFT TDI TDO2 UPDATE UG332 C13 01 04010 Figure 13 1 BSCAN Primitive for Spartan 3A 3AN 3A DSP FPGAs Spartan 3 Generation Configuration User Guide www xilinx com 239 UG332 v1 2 May 23 2007 Chapter 13 Configuration Related Design Primitives XILINX Usage Table 13 1 BSCAN Primitives by FPGA Family FPGA Family Primitive Spartan 3A 3AN FPGAs Spartan 3A DSP FPGAs BSCAN SPARTAN3A Spartan 3E FPGAs BSCAN SPARTANS3 Spartan 3 FPGAs The BSCAN primitive on Spartan 3 Generation FPGAs allows up to two internal private boundary scan chains called USER1 and USER2 A signal on the TDO1 input is passed to the external TDO output when the USER1 instruction is executed the SEL1 output goes High to indicate that the USERI instruction is active The DRCK1 output provides USERI access to the data register clock generated by the TAP controller The TDO2 and SEL2 pins perform a similar function for the USER2 instruction and the DRCK2 output provides USER2 access to the data register clock generated by the TAP controller The RESET UPDATE SHIFT and CAPTURE pins represent the decoding of the corresponding state of the boundary scan internal state machine The TDI pin provides access to the TDI signal of the JTAG port in order to shift data into an internal scan chain The BSCAN component is generally used with IP such as the Chi
43. DSP bitstream depending on device logic density ranges between approximately 0 5M to 11 5M bits per FPGA e Spartan 3A 3AN 3A DSP FPGAs can MultiBoot between different configuration modes For example the FPGA can initially configure from parallel Flash using BPI mode then MultiBoot to a configuration image stored in SPI serial Flash using Master SPI mode See the Spartan 3AN Errata for limitations on MultiBoot after configuring from internal SPI Flash in Spartan 3AN FPGAs e The initial configuration image is always located at address 0 regardless of configuration mode e Subsequent MultiBoot images can be located anywhere in memory aligned to a byte location with some restrictions Ifthe FPGA is set to wait for the Digital Clock Managers DCMs to lock before finishing configuration then there must be sufficient padding between images to allow for this time The padded region can contain data but it cannot contain a valid configuration synchronization word Individual bitstream images may be aligned to a sector or page boundary within the attached Flash memory device e A built in configuration watchdog timer prevents a MultiBoot operation from hanging on an invalid FPGA configuration image Ifnosynchronization word is detected within the watchdog time out period the FPGA automatically returns to and reloads the default initial configuration image Specifying the Next MultiBoot Configuration Address The initi
44. FPGA does not wait for DCI circuitry to match impedance 0 1 2 3 4 5 6 Specify the Startup cycle where the FPGA waits for the DCI circuitry to match the target impedance value specified using external resistors DCIUpdateMode Spartan 3 FPGA only DCI AsRequired Default DCI impedance adjustments are made only when needed to maintain tracking Continuous DCI impedance adjustments are made continuously Quiet After the initial DCI impedance match is achieved no further adjustments occur Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 221 Chapter 11 Configuration Bitstream Generator BitGen Settings XILINX Table 11 2 Spartan 3 Generation Bitstream Generator BitGen Options Continued Option Name Pins Function Affected JTAG Related Options See Chapter 9 JTAG Configuration Mode and Boundary Scan Values default Description TckPin JTAG TCK pin Pullup Default Internally connects a pull up resistor between JTAG TCK pin and VCCAUX Pulldown Internally connects a pull down resistor between JTAG TCK pin and GND Pullnone No internal pull up resistor on JTAG TCK pin TdiPin JTAG TDI pin Pullup Default Internally connects a pull up resistor between JTAG TDI pin and VCCAUX Pulldown Internally connects a pull down resistor between JTAG TDI pin and GND Pullnone No
45. Flash memory for the associated FPGA is also displayed 11 Click Next 208 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 Preparing an In System Flash Programming File XILINX 12 The Default Spartan 3AN configuration bitstream Bitstream 0 is always located at address 0 Bitstream 0 is the bitstream that the FPGA automatically loads when power is applied or whenever the PROG_B pin is pulsed Low ES iMPACT Spartan3AN Enter Start Address Select the number of Bitstreams The Start Address will be pre determined based on the device selection jitstream O lm itstream 1 m H se Power of 2 for Start Address Add Data Files UG332_c10_04_022307 Figure 10 7 Specify the FPGA Configuration Bitstream s 13 Click the option box to include a second MultiBoot bitstream Bitstream 1 Bitstream 1 is always aligned to the next ISF memory sector boundary following Bitstream 0 The iMPACT software displays the sector address based on the current addressing mode as shown in Table 10 3 This is the address used for MultiBoot operations to load the second bitstream Table 10 3 Locations of Default Bitstream and Second MultiBoot Bitstream Spartan 3AN ISF Memory Bitstream Starting Address Hex Bitstream FPGA Page Default Optional Power of 2 Bitstream 0 All 0 0x00 0000 0x00 0000 XC3S50AN 256 0x02 0000 0x01 0000 XC3S200AN 768 0x06 0000 0x03 0000 Bitstream
46. Generation Configuration User Guide www xilinx com 259 UG332 v1 2 May 23 2007 Chapter 14 Reconfiguration and MultiBoot XILINX e Ifthe next address is fixed and already known at design time preload the GENERAL1 and GENERAL2 registers with default values by setting the next config addr bitstream generation BitGen option FPGA Application Run Time e Issue the synchronization start word to the ICAP interface e Ifthe FPGA application calculates the next MultiBoot configuration start address load the GENERAL1 and GENERAL2 registers via ICAP with the start address of the next MultiBoot configuration image e OPTIONAL If rebooting from a different configuration source write the appropriate values to the MODE REG register See Switching between MultiBoot Configuration Memory Types page 271 for more information e Issue the REBOOT command to the CMD register e Issue a NoOp command to the ICAP interface MultiBoot from an Address Preloaded during Configuration Table 14 2 shows the command sequence to initiate a MultiBoot event assuming the following e The GENERAL and GENERAL registers are preloaded during configuration via the next config addr bitstream generation BitGen option e The next MultiBoot address is in the same memory originally used to configure the FPGA or the same memory used during the last MultiBoot operation Each 16 bit command is written as two bytes to the ICAP interface with the high by
47. HSWAP or PUDC_B 0 during configuration the FPGA holds the chip select line High via an internal pull up resistor If HSWAP or PUDC B 1 connect the select line to 3 3V via an external 4 7 kQ pull up resistor to avoid spurious read or write operations After configuration drive the select line Low to select the desired peripheral Refer to the individual peripheral data sheet for specific interface and communication protocol requirements The FPGA optionally supports a 16 bit peripheral interface by driving the LDC2 BYTE control pin High after configuration See Precautions Using x8 x16 Flash PROMs for additional information A Spartan 3E FPGA provides up to 24 address lines during configuration addressing up to 128 Mbits 16 Mbytes A Spartan 3A 3AN 3A DSP provides up to 26 address lines addressing up to 512 Mbits 64 Mbytes If using a larger parallel PROM connect the upper PROM address lines to FPGA user I O During configuration the upper address lines will be pulled High if HSWAP or PUDC B 0 Otherwise use external pull up or pull down resistors on these address lines to define their values during configuration Precautions Using x8 x16 Flash PROMs D Most low to mid density PROMs typically 8 Mbits and below are only available as byte wide x8 memories Many higher density Flash PROMs usually 16 Mbits and above support both byte wide x8 and word wide x16 data paths and include a mode input pin called BYTE th
48. Locate and select the desired FPGA bitstream 13 Click Open Spartan 3 Generation Configuration User Guide www xilinx com 113 UG332 v1 2 May 23 2007 Chapter 4 Master SPI Mode XILINX 14 As shown in Figure 4 15 the iMPACT software graphically displays the SPI PROM and associated FPGA bitstream s iMPACT C Datamy designsXCRC Checker default ipf PROM File Formatter S Fie Edit View Operations Options Output Debug Window Help lg fal amp B x 2 3x i H BA Boundary Scan H malslaveSerial Ba SelectMAP H malDesktop Configu xc3s700a led crazy bit UG332 c4 06 110206 Figure 4 15 Generate PROM File 15 Click Generate File 16 The iMPACT software indicates when the PROM file is successfully created PROMGen PROMGen is a command line utility that provides an alternate means to create an SPI PROM programming file PROMGen can be invoked from within a command window or from within a script file Table 4 14 shows the relevant options for SPI Flash PROM formatting Table 4 14 PROM Generator Command Options PROMGen Option Description p REQUIRED FOR SPI FLASH PROMS Specifies the correct bit SE ordering required to configure from an SPI Flash memory device PROM output file format Specifies the file format required by the SPI p format programming software Refer to the third party programmer documentation for details digas
49. Pee tera e end ded denies 243 Internal Configuration Access Port ICAP uuuuuuuusesseessses 244 SAS EE 244 Port D sctiptlOtt cys uere erre rhe ANI cie e eU oe ae oer wed 245 Device DNA Access Port DNA PORT sssseseee cee eee ee 245 Usage esc ctus bees s eked baee seda alo nie a apte qu ae ccm iti nce 246 Port Descriptions oso E rp rer equ ea gue eragd DERE DELS nd s 246 Attributes s cii le tere a v adv de e i ey a E EG gana eae eg Eo ve 246 Chapter 14 Reconfiguration and MultiBoot VErVIEW 1 iuskadeekexsek d axe 3 brad ee Gud debui sd bues EE Rand ERR eq 247 MultiBoot Options Compared between Spartan 3 Generation FPGA Families 247 Spartan 3E MultiBoot 1 rece r tr Re ER RR REA E n 249 Generating a Spartan 3E MultiBoot PROM Image using iMPACT 250 PROMGen Report File 0 nee 255 Spartan 3E MultiBoot using Xilinx Platform Flash PROMS 5 256 Spartan 3A 3AN 3A DSP MultiBoot 0 0 0 257 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Specifying the Next MultiBoot Configuration Address iiie 257 Required Data Spacing between MultiBootImages sese 258 Flash Sector Block or Page Boundaries 6 2 6 ccc cee eee nee 258 Additional Memory Space Required for DOM WAIT 0 0 0 0c cece eee 258 MultiBoot Command Sequence ICAP Example 06 0 0 cece eee eee eee 259 Des
50. Set M0 0 to start User I O A configuration mode Spartan at address 0 increment addresses 3A 3AN 3A DSP FPGAs have On Spartan 3E FPGAs optionally dedicated internal pull up set MO 1 to start at address resistors on these pins See OxFFFFFF and decrement Design Considerations for the addresses Sampled when INIT_B HSWAP M 2 0 and VS 2 0 goes High Pins page 58 Spartan 3E Input Chip Select Input Active Low Must be Low throughout User I O FPGAs only configuration This input is ignored CSI B on Spartan 3A 3AN 3A DSP E FPGAs Spartan 3E Input Read Write Control Active Low Must be Low throughout User I O FPGAs only write enable Read functionality configuration This input is ignored RDWR B typically only used after on Spartan 3A 3AN 3A DSP B configuration if bitstream option FPGAs Persist Yes LDCO Output PROM Chip Enable Connect to PROM chip select input User I O If the FPGA CSf FPGA drives this signal Low does not access the throughout configuration PROM after configuration drive this pin High to deselect the PROM A 23 0 D 7 0 LDC2 LDC1 and HDC then become available as user I O LDC1 Output PROM Output Enable Connect to the PROM output User I O enable input OE The FPGA drives this signal Low throughout configuration 134 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX PROM Address Generation Table 5 3
51. Starter Kit board provides a design example that programs the on board Intel StrataFlash PROM using the board s RS 232 serial port Similarly the Spartan 3A Starter Kit board provides a similar example but for the STMicro M29DW323DT parallel Flash PROM e PicoBlaze RS 232 StrataFlash Programmer www xilinx com products boards s3estarter reference_designs htm picoblaze_nor_flash_programmer e Programmer for the ST Microelectronics M29DW323DT Parallel NOR Flash www xilinx com products boards s3astarter reference_designs htm parallel_flash programmer Power On Precautions if 3 3V Supply is Last in Sequence Spartan 3A 3AN 3A DSP and Spartan 3E FPGAs have a built in power on reset POR circuit as shown in Figure 12 3 page 226 The FPGA waits for its three power supplies Veer Vecaux and Veco to I O Bank 2 VCCO 2 to reach their respective power on thresholds before beginning the configuration process The parallel NOR Flash PROM is powered by the same voltage supply feeding the FPGA s VCCO_2 voltage input typically 3 3V Parallel NOR Flash PROMs specify that they cannot be accessed until their Vcc supply reaches its minimum data sheet voltage followed by an additional delay often called a Vcc setup time Table 5 9 shows some representative values Table 5 9 Example Minimum Power On to Setup Times for Various Parallel NOR Flash PROMs Flash PROM Data Sheet Minimum Time from Vcc min to Select Low Ve
52. Sync to DONE Start Up Clock LFLELFLELELELELT T Pase o X2 yo 4X XXe DONE High DONE GTS GWE UG332_c12_10_110406 Figure 12 12 Default Start Up Sequence Startup Clock Source There are three possible clock sources for the Startup sequencer controlled by the StartupClk bitstream generator option 1 By default the start up sequence is synchronized to CCLK The Cclk option or the UserClk option is required for Master Mode or Slave Mode configuration 2 Alternatively the start up sequence can be synchronized to a user specified clock from within the FPGA application using the Start Up STARTUP page 241 library primitive and by setting the StartupClk UserClk bitstream generator option 3 When using JTAG configuration the start up sequence must be synchronized to the TCK clock input StartupClk JtagClk Waiting for DCMs to Lock DCI to Match The startup sequence can be forced to wait for the DCMs to lock or for DCI to match with the appropriate BitGen options These options are typically set to prevent DONE GTS and GWE from being asserted preventing FPGA operation before the DCMs have locked and or DCI has matched Spartan 3 Generation Configuration User Guide www xilinx com 235 UG332 v1 2 May 23 2007 Chapter 12 Sequence of Events XILINX The DONE signal is released by the startup sequencer on the cycle indicated in the bitstream set by the DONE cycle bitstream generator optio
53. Table 12 3 Spartan 3 Generation FPGA Synchronization Word FPGA Family Length bits Contents hexadecimal ERE is oaas Tar 32 0xAA995566 Check Array ID Steps 6 7 8 Load S tartup Configuration CRC Check Sequence Data 1 2 l 3 4 Wake from Clear Sample Control Reset Configuration Pins power onor Memory M 2 0 VS 2 0 PROG B Synchronization Bitstream Loading Finish UG332_c12_06_110406 Start Figure 12 8 Check Array ID After the FPGA is synchronized the FPGA checks that the array ID embedded in the bitstream matches its internal array ID This prevents the FPGA from mistakenly attempting to load configuration data intended for a different FPGA array For example the array ID check prevents an XC3S1000 from being configured with an XC35200 bitstream The array ID check is built into the bitstream making this step transparent to most designers Table 12 4 shows the Spartan 3 Generation array ID codes Although the array ID code is identical to the JTAG IDCODE register value the array ID check is performed 230 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Bitstream Loading Steps 4 7 using bitstream commands to the internal configuration logic not through the JTAG IDCODE register The array identifier is a 32 bit value Within the 32 bit value 28 bits are unique to a specific
54. active M Tecua MCCL1 MCCH1 Pin initially pulled High by internal pull up resistor if HSWAP or PUDC B input is Low Pin initially high impedance Hi Z if HSWAP input is High External pull up resistor required on CSO B Shaded values indicate specifications on attached SPI Flash PROM UG332 c4 17 110206 Figure 4 29 Waveforms for Serial Peripheral Interface SPI Configuration 1 The FPGA powers on releasing the internal Power On Reset POR circuit or the PROG B input returns High 2 The FPGA begins clearing its internal configuration memory The FPGA actively drives the INIT B output Low 3 Ensure that HSWAP or PUDC B is at a stable logic level throughout the configuration process The value on this input pin defines whether pull up resistors are enabled during configuration Some applications may depend on the pull up resistors to define the VS 2 0 variant select pins and to hold CSO B High before the FPGA actively drives it Low 124 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Serial Peripheral Interface SPI Configuration Timing 10 11 The VS 2 0 variant select pins must be defined and stable before the INIT B pin returns High The value on VS 2 0 defines the specific read command that the FPGA issues to the SPI serial PROM See Table 4 2 page 89 The M 2 0 mode select pins must be defined for Master SPI mode lt 0 0 1 gt and stable
55. aircraft navigation or communications systems air traffic control life support or weapons systems High Risk Applications Xilinx specifically disclaims any express or implied warranties of fitness for such High Risk Applications You represent that use of the Design in such High Risk Applications is fully at your risk 2006 2007 Xilinx Inc All rights reserved XILINX the Xilinx logo and other designated brands included herein are trademarks of Xilinx Inc All other trademarks are the property of their respective owners Revision History The following table shows the revision history for this document Date Version Revision 12 05 06 1 0 Initial release 02 26 07 141 Added configuration information for the Spartan 3AN FPGA family Added Chapter 10 Internal Master SPI Mode describing how a Spartan 3AN FPGA configures from its internal In System Flash memory Increased ConfigRate settings for Spartan 3A 3AN FPGAs based on improved data setup time Table 4 11 and Table 5 8 Added links to new reference designs using the Spartan 3E and Spartan 3A Starter Kit boards 05 23 07 1 2 Added Spartan 3A DSP family configuration information Added Bitstream Format page 24 Added Indirect Programming using iMPACT page 118 Updated Limitations when Reprogramming via JTAG if FPGA Set for BPI Configuration page 158 Updated JTAG ID values in Table 12 4 page 231 Added more information to Configuration Watchdo
56. all devices in the daisy chain or broadside configuration Set this option graphically in ISE Project Navigator page 28 by checking the Enable Internal Done Pipe option box shown in Figure 1 8 page 30 DONE Synchronizes Multiple FPGAs in a Daisy Chain or Broadside Ganged Configuration In a single FPGA application the DONE pin merely indicates when the FPGA successfully configures In a multi FPGA daisy chain or broadside application however the DONE pin also synchronizes the Startup sequence of all the FPGAs ensuring that the FPGAs transition smoothly from the configuration process to the active FPGA application Figure 2 1 provides a three FPGA example In a daisy chain application FPGAs of different densities 38 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX General Configuration Control Pins and architectures are configured in series with different bitstreams In a broad side example multiple identical FPGAs are simultaneously loaded with the same bitstream Common INIT_B node Common DONE node synchronizes initialization synchronizes the Startup clearing configuration memory sequence between between different array sizes different FPGAs FPGA FPGA FPGA OQ resistors provide a means to isolate an individual FPGA to easily debug a configuration Issue UG332 c2 02 111406 Figure 2 1 DONE and INIT B Synchronize Daisy Chain or Broadside Configurations Co
57. always loaded starting at address 0 13 To add additional images check Enable Data Stream 14 Specify the starting address of each MultiBoot image using hexadecimal notation Spartan 3 Generation Configuration User Guide www xilinx com 267 UG332 v1 2 May 23 2007 Chapter 14 Reconfiguration and MultiBoot XILINX What is the size of the FPGA configuration bitstream Is the bitstream for a single FPGA or a multi FPGA daisy chain Spartan 3A 3AN 3A DSP FPGAs do support daisy chains when using MultiBoot What are the page or sector boundaries of the Flash device Ideally the FPGA bitstream should start on a Flash sector boundary If using the DCM WAIT option on a Digital Clock Manager DCM with the FPGA application is there enough additional spacing between images to accommodate the extra lock time An uncompressed Spartan 3A XC35700A FPGA configuration bitstream requires 2 732 640 bits Dividing that number by eight provides the required number of bytes 341 580 bytes Divide the number of bytes by 1 024 to determine the number of kilobytes or 333 57K The Atmel AT45DB161D serial Flash uses 128Kbyte sectors Consequently a single XC35700A configuration bitstream occupies 2 6 sectors The first bitstream always starts at address 0 The next Spartan 3A 3AN 3A DSP MultiBoot image should be placed on a following Flash sector boundary The next available boundary after the first configuration image begins at address he
58. an FPGA Bitstream have the greatest overall compression factor Similarly FPGA designs with an empty column of block RAM have a high compression factor The overall benefits of a compressed bitstream are as follows e Smaller memory footprint e Faster programming time for nonvolatile memory There are two methods to generate a compressed bitstream from within the ISE Project Navigator or from the command line From Project Navigator check the Enable BitStream Compression option shown as Step 4 in Figure 1 6 From the command line add the g Compress option to the BitGen command line bitgen g Compress lt other options gt Furthermore the parallel Platform Flash PROMs offer their own compression mechanisms Packet Format A Spartan 3 Generation bitstream consists of a specific sequence of writes to the configuration registers After synchronization all data register writes and frame data are encapsulated in packets There are two kinds of packets Type 1 and Type 2 A Type 1 packet consists of two parts a header and the data The header see Figure 1 4 describes which register is being accessed whether it is a read or write operation and the size of the data to follow The data portion always immediately following the header is the number of 32 bit words specified in the header 15 14 13 12 11 10 9 8 7 6 5 4 3 2 141 0 Type Op Register Address Word Count
59. and BitGen Options Spartan 3A 3AN Spartan 3 Spartan 3A DSP Value Spartan 3E FPGAs FPGAs Enable Readback and Reconfiguration default None None Disable Readback Levell Levell Disable Readback and Reconfiguration Level2 Level3 BitGen Command Line Utility The security options are also available via the BitGen command line utility as shown below The available Security options are provided in Table 15 1 or Table 15 2 depending on the Spartan 3 Generation FPGA family used Table 15 3 shows how the options entered via the ISE Project Navigator relate to the BitGen command line options An example that disables Readback is provided below bitgen g Security Levell remaining options Approaches to Design Security Xilinx programmable logic devices incorporate a variety of approaches to design security as summarized in Table 15 4 Xilinx employs each of these security options in different product families The Spartan 3 Generation FPGAs introduce a new option called Authentication which is described throughout the remainder of this chapter Table 15 4 Programmable Logic Security Options Compared Security Bits Encryption Authentication Xilinx product family that uses this security Spartan 3A 3AN opum VirtexII viriel a PPartan 3A DSP Xilinx CPLDs Pro Virtex 4 Virtex 5 FPGA but variations FPGAs possible in Spartan 3 3E FPGAs Is bitstream or programming file visible after Yes but can
60. authentication check value locally or communicates to a remote host that generates the check value or looks up the value in a list of authenticated devices Te al Spartan 3A 3AN 3A DSP FPGA FPGA Bitstream Authentication Device DNA Check Value UG332_c16_12_040107 Figure 15 12 Host Reads Device DNA Generates Authentication Value In Figure 15 13 the intelligent hosts writes the resulting authentication check value back into the FPGA The FPGA then uses this value and the Device DNA value to authenticate the bitstream If deemed authentic then FPGA application is enabled for full operation Spartan 3 Generation Configuration User Guide www xilinx com 285 UG332 v1 2 May 23 2007 Chapter 15 Protecting FPGA Designs XILINX Intelligent Spartan 3A 3AN 3A DSP FPGA Authentication Check Value FPGA Bitstream Device DNA UG332_c16_13_040107 Figure 15 13 Host Writes Authentication Value to Enable FPGA Application Authenticating any FPGA Design Using External Secure PROM Authentication techniques are possible on any FPGA using an external secure PROM Xilinx provides an example design using a Dallas Semiconductor Maxim DS2432 SHA 1 Secure EEPROM as shown in Figure 15 14 This technique works with any Xilinx FPGA family with block RAM Configuration FPGA PROM DS2432 Authentication Core FPGA Secure 1 Block RAM Application LL EEPROM 6800 100 Slices SIO SIO DESIGN FOE DISABLE
61. before the INIT B pin returns High After the FPGA completes clearing the internal configuration memory the FPGA release the INIT B pin allowing it to float High via the dedicated internal pull up resistor to VCCO 2 After the INIT B pin returns High the FPGA begins toggling the CCLK output which controls all the configuration timing The CCLK output initially starts at its lowest default frequency approximately 1 MHz The SPI Flash requires a High to Low transition on the CSO B output The FPGA actively drives the CSO B output High for one CCLK cycle before asserting the CSO B pin Low This begins the SPI bus transaction Based on the VS 2 0 pin values sampled when INIT B pin returned High the FPGA begins issuing a SPI Flash read command The FPGA sends the command most significant bit first The FPGA subsequently sends a 24 bit address all zeros and the appropriate number of dummy bits also zero for the select Flash memory The FPGA clocks out the command address and dummy bits on the MOSI output clocked on the falling edge of CCLK Within the first 256 bits of the configuration bitstream the FPGA loads the ConfigRate setting for the remainder of the configuration process The ConfigRate setting defines the CCLK frequency All interface timing must be evaluated for the specific setting See CCLK Frequency page 98 and ConfigRate CCLK Frequency page 109 The SPI Flash PROM provides data on the falling edge of C
62. chain Use Slave Parallel mode M 2 0 lt 1 1 0 gt for all FPGAs in the daisy chain There are two possible topologies available one that supports only Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs and another that works with any modern Xilinx FPGA Virtex or Spartan II FPGA and later 168 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Daisy Chaining Spartan 3E Spartan 3A 3AN 3A DSP Slave Parallel Daisy Chains Figure 7 3 page 169 shows a daisy chain topology that primarily supports Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs although the last FPGA in the chain can be from any modern Xilinx FPGA family It essentially leverages the BPI mode daisy chain technique The upstream FPGA in the chain drives its CSO_B Low enabling the downstream FPGA s CSI_B or CS_B input Only Spartan 3E Spartan 3A Spartan 3AN Spartan 3A DSP and Virtex 5 FPGAs have a CSO_B output Consequently one of these FPGAs must be the first and intermediate FPGAs in the daisy chain Pull up resistors on the CSO_B to CSI B connect are required if the FPGAs HSWAP PUDC_B HSWAP_EN or input is High meaning that the FPGA s internal pull up resistors are disabled during configuration RDWR_B M2 M1 MO INIT B MO INIT B PROG B DONE PROG B DONE PROG B First Intermediate Last FPGA in FPGAs Daisy Chain Spartan 3A 3AN 3A DSP Any Xilinx FPGA Spartan 3E Virtex 5 FPGAs UG332_c7_03_040107 Figu
63. com xInx xebiz designResources ip product details jsp key HW PC4 e MultiPRO Desktop Tool www xilinx com xlnx xebiz designResources ip product details jsp key HW MULTIPRO If possible place a target interface connector on the FPGA board to facilitate easy programming Xilinx recommends using the high performance ribbon cable option pictured in Figure 9 6 page 193 for maximum performance and best signal integrity Slave Serial INIT B N C DIN DONE CCLK PROG B VREF Figure 9 6 SPI N C N C MOSI MISO SCK SS B VREF 2x7 14 position 2 mm connector surface mount for ribbon cable Molex part no 87832 1420 Also available in through hole mounting GND GND GND GND GND GND GND 0 0 020 0 5 mm SQ TYP UG332 c9 06 1 Target Interface Connector Dimensions and Pin Assignments Such connectors are available in both through hole and surface mount configurations as shown in Table 9 5 Use shrouded or keyed connectors to ensure guarantee proper orientation when inserting the cable The specified connector requires only 0 162 square inches of board space Table 9 5 Mating Connectors for 2 mm pitch 14 Conductor Ribbon Cable Connector Style and Vendor Part Number Surface Mount Through Hole Through Hole Right Manufacturer Vertical Vertical Angle Vendor Web Site Molex 87832 1420 87831 1420 87833 1420 www molex com FCI 98424 G52
64. configuration data file corresponds to the data ordering expected by the FPGA In SelectMAP the byte wide configuration data is loaded one byte per CCLK with the most significant bit of each byte presented to the FPGA s D0 data pin Table 7 5 provides an example of how the FPGA would like to see the hexadecimal value OXABCD presented on the SelectM AP data bus Note how the bits within each byte need to be reversed Table 7 5 Bit Ordering for SelectMAP 8 Bit Mode CCLK Hex Cycle Equivalent D7 D6 D5 D4 D3 D2 D1 DO 1 OxAB 1 1 0 1 0 1 0 1 2 OxCD 1 0 1 1 0 0 1 1 Notes 1 D 0 7 represent the Select MAP DATA pins Some applications can accommodate the non conventional data ordering without much difficulty For other applications it may be more convenient to store the source configuration data file with the data bits already bit swapped meaning that the bits in each byte of the data stream are reversed The Xilinx PROM file generation software provides the option to generate bit swapped PROM files 178 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Chapter 8 Slave Serial Mode In Slave Serial mode M 2 0 lt 1 1 1 gt an external host such as a microprocessor or microcontroller writes serial configuration data into the FPGA using the synchronous serial interface shown in Figure 8 1 The figure shows optional components in
65. detected during configuration FPGA drives INIT_B Low Spartan 3 Generation Configuration User Guide www xilinx com 67 UG332 v1 2 May 23 2007 Chapter 3 Master Serial Mode EZ XILINX Table 3 3 Master Serial Configuration Mode Connections Continued FPGA After Pin Name Direction Description During Configuration Configuration FPGA Configuration Done Low Connects to PROM s chip When High Open drain during configuration Goes High enable CE input Enables indicates that DONE bidirectional when FPGA successfully completes PROM during configuration the FPGA I O configuration Disables PROM after successfully configuration configured Program FPGA Active Low When Must be High during Drive PROG B asserted Low for 500 ns or longer configuration to allow Low and release forces the FPGA to restart its configuration to start Connects to reprogram PROG B Input configuration process by clearing to PROM s CF pin allowing FPGA configuration memory and resetting JTAG PROM programming the DONE and INIT B pins once algorithm to reprogram the PROG B returns High FPGA Voltage Compatibility Platform Flash PROM The Platform Flash PROM Vccryr supply must be either 3 3V for the serial XCFxxS Platform Flash PROMs or 1 8V for the serial parallel XCFxxP PROMs FPGA Spartan 3E and Spartan 3A 3A DSP FPGAs with Vocayx at 2 5V The Spartan 3E or Spartan 3A 3A DSP FPGA VCCO 2 supply input and
66. gray The serial configuration data is presented on the FPGA s DIN input pin with sufficient setup time before each rising edge of the externally generated CCLK clock input The intelligent host starts the configuration process by pulsing PROG B and monitoring that the INIT B pin goes High indicating that the FPGA is ready to receive its first data The host then continues supplying data and clock signals until either the DONE pin goes High indicating a successful configuration or until the INIT B pin goes Low indicating a configuration error The configuration process requires more clock cycles than indicated from the configuration file size Additional clocks are required during the FPGA s start up sequence especially if the FPGA is programmed to wait for selected Digital Clock Managers DCMs to lock to their respective clock inputs see Startup page 233 Spartan 3 Generation Configuration User Guide www xilinx com UG332 v1 2 May 23 2007 179 Chapter 8 Slave Serial Mode XILINX 1 2V VCCINT P HSWAP VCCO 0 VCCO 0 Slave v Serial Mode M2 4 Intelligent Vv 4 M1 1 0 XILINX lt Spartan 3E Download Host Configuration rin urati Memory CLOCK Source SERIAL OUT PROG B e Internal memory DONE e Disk drive e Over network INIT_B e Over RF link CCLK FPGA DIN DOUT VCCAUX 2 5V TDO e Microcontroller e Processor e Tester e Computer
67. image is loaded starting at the highest PROM address which is at hexadecimal OxFFFFF for a IMbyte PROM The image is loaded downward decrementing address and ends at hexadecimal address 0xBAB80 Spartan 3E MultiBoot using Xilinx Platform Flash PROMs While the Spartan 3E MultiBoot feature was primarily designed to leverage commodity parallel NOR Flash PROMs it is also possible to use Xilinx Parallel Platform Flash PROMs specifically the XCFxxP PROM family The final P in the product name indicates the Parallel version See XAPP483 for additional details e XAPP483 Multiple Boot using Platform Flash PROMs http www xilinx com bvdocs appnotes xapp483 pdf 256 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Spartan 3A 3AN 3A DSP MultiBoot Spartan 3A 3AN 3A DSP MultiBoot Starting with the Spartan 3A FPGA family MultiBoot is expanded and enhanced to provide additional flexibility and capabilities e Spartan 3A 3AN 3A DSP MultiBoot supports multiple FPGA bitstream images beyond just the two images supported on Spartan 3E FPGAs e The maximum number of FPGA images supported is limited either by the size of the configuration PROM or the total number of address bits BPI mode supports up to 26 address bits which addresses up to 64M bytes or 512M bits SPI mode supports up to 24 address bits which addressees up to 16M bytes or 128M bits ASpartan 3A 3AN 3A
68. in the CAPTURE DR state Identification IDCODE Register Spartan 3 Generation FPGAs have a 32 bit identification register called the IDCODE register The IDCODE is based on the IEEE 1149 1 standard and is a fixed vendor assigned value that is used to identify electrically the manufacturer and the type of device that is being addressed This register allows easy identification of the part being tested or programmed by Boundary Scan and it can be shifted out for examination by using the IDCODE instruction The last bit of the IDCODE is always 1 based on JTAG IEEE 1149 1 The last three hex digits appear as 0x093 JTAG Configuration Register Boundary Scan The JTAG Configuration register is a 32 bit register This register allows access to the configuration bus and readback operations USERCODE Register The USERCODE instruction is supported in Spartan 3 Generation FPGAs This register allows a user to specify a design specific identification code The USERCODE can be programmed into the device and can be read back for verification later The USERCODE is embedded into the bitstream during bitstream generation BitGen g UserID option and is Spartan 3 Generation Configuration User Guide www xilinx com 191 UG332 v1 2 May 23 2007 Chapter 9 JTAG Configuration Mode and Boundary Scan XILINX valid only after configuration If the device is blank or the USERCODE was not programmed the USERCODE register contains 0xFFFFFFFF
69. in the second FPGA bitstream before completing the current configuration it starts interpreting data from the second bitstream However the FPGA s configuration logic may complete the current configuration even though the FPGA has read data from the second bitstream Caution FPGA applications that use the DOM WAIT option on a DCM must ensure sufficient spacing between Spartan 3A 3AN 3A DSP MultiBoot configuration images Spacing MultiBoot bitstreams sufficiently apart in memory prevents the FPGA from ever seeing the second synchronization word The following are some points to consider e Is the DCM WAIT option being used in the FPGA application The potential issue only occurs if DCM_WAIT TRUE e Which DCM outputs are used There are two lock time specifications in the data sheet LOCK_DLL specifies the lock time for the DLL outputs from the DCM CLKO CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV and LOCK_DFS specifies the lock time for the DFS outputs CLKFX CLKFX180 258 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Spartan 3A 3AN 3A DSP MultiBoot The specified lock time also depends on the input clock frequency Again consider both the DLL and DFS specifications The lock time is longest at 5 ms for input frequencies below 15 MHz The amount of spacing between bitstreams also depends on the ConfigRate bitstream option setting in the bitstream and the maximum frequen
70. internal pull up resistor on JTAG TDI pin TdoPin JTAG TDO pin Pullup Default Internally connects a pull up resistor between JTAG TDO pin and VCCAUX Pulldown Internally connects a pull down resistor between JTAG TDO pin and GND Pullnone No internal pull up resistor on JTAG TDO pin TmsPin JTAG TMS pin Pullup Default Internally connects a pull up resistor between JTAG TMS pin and VCCAUX Pulldown Internally connects a pull down resistor between JTAG TMS pin and GND Pullnone No internal pull up resistor on JTAG TMS pin UserID JTAG User ID OxFFFFFFFF The 32 bit JTAG User ID register value is loaded during register configuration The default value is all ones OXFFFFFFFF hexadecimal To specify another value enter an 8 character hexadecimal value Spartan 3A 3AN 3A DSP Power Saving Suspend Feature See XAPP480 Using Suspend Mode in Spartan 3 Generation FPGAs en suspend Spartan 3A No Default Suspend mode not used Connect the SUSPEND pin Spartan 3AN to GND Spartan 3A DSP Y bias th FPGA only es Enables the power saving Suspend feature controlled by the SUSPEND pin Suspend mode drive awake Spartan 3A No Default If Suspend mode is enabled indicates the present Spartan 3AN Spartan 3A DSP FPGA only Suspend mode AWAKE pin status on AWAKE using an open drain output An external pull up resistor or High signal is required to exit SUSPEND mode Yes If Suspend mode is enabled indicates the pr
71. of the FPGA pins used during configuration have dedicated pull up resistors during configuration However the majority of user I O pins have optional pull up resistors that can be enabled during the configuration process During configuration a single control line determines whether the pull up resistors are enabled or disabled The name of the control pin varies by Spartan 3 Generation family On Spartan 3A 3AN 3A DSP FPGAs this pin is called PUDC B pull up during configuration active Low and on Spartan 3E FPGAs this same pin is called HSWAP short for hot swap On Spartan 3 FPGAs the same pin is called HSWAP EN Why enable the pull up resistors during configuration Floating signal levels are problematic in CMOS logic systems Other logic components in the system may require a valid input level from the FPGA The internal pull up resistors generate a logic High level on each pin Generally a device driving signals into the FPGA can overcome the pull up resistor Similarly an individual pin can be pulled down using an appropriately sized external pull down resistor Why disable pull up resistors during configuration In hot swap or hot insertion applications the pull up resistors provide a potential current path to the I O power rail Turning off the pull up resistors disables this potential path However then external pull up or pull down resistors may be required on each individual I O pin See Pull Up Resistors During Configuration p
72. only require the 3 3V Vcc Aux supply because there are no Dual Purpose pins involved In all other configuration modes the Dual Purpose pins are involved Design Considerations for the HSWAP M 2 0 and VS 2 0 Pins Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs are unlike previous Spartan FPGA families Nearly all of the Spartan 3E 3A 3AN 3A DSP dual purpose configuration pins are available as full featured user I O pins after successful configuration The HSWAP or PUDC B pin the mode select pins M 2 0 and the variant select pins VS 2 0 must have valid and stable logic values at the start of configuration VS 2 0 are only used in the Master SPI configuration mode The levels on the M 2 0 pins and VS 2 0 pins are sampled when the INIT B pin returns High See Figure 2 6 for a timing example The HSWAP or PUDC B pin defines whether FPGA user I O pins have a pull up resistor connected to their associated Vcco supply pin during configuration or not as shown 58 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Design Considerations for the HSWAP M 2 0 and VS 2 0 Pins Table 2 20 HSWAP or PUDC B must be valid at the start of configuration and remain constant throughout the configuration process The detailed schematics for each configuration mode indicate the required logic values for HSWAP or PUDC_B M 2 0 and VS 2 0 but do not specify how the application provides the l
73. or pages Nearly all PROMs have multiple sectors Some architectures provide additional granularity splitting a sector into smaller blocks or even smaller still pages Ideally a Spartan 3A 3AN 3A DSP MultiBoot configuration image should be aligned to a sector block or page boundary The specific requirement depends on the Flash PROM architecture If the smallest erasable element in the Flash PROM is a sector then align the FPGA bitstream to a sector boundary This way one FPGA bitstream can be updated without affecting others in the PROM Additional Memory Space Required for DOM WAIT A Spartan 3A 3AN 3A DSP application may contain one or more Digital Clock Managers DCMs Each DCM provides an option setting that during configuration causes the FPGA to wait for the DCM to acquire and lock to its input clock frequency before the DCM allows the FPGA to finish the configuration process The lock time which is specified in the Spartan 3A 3AN 3A DSP data sheet depends on the DCM mode and the input clock frequency Even if the FPGA is waiting for one or more DCMs to lock before completing configuration the FPGA s configuration controller continues searching for the next synchronization word If two adjacent MultiBoot images are placed one immediately following the other and the first FPGA bitstream contains a DCM with the DCM WAIT option set then potential configuration problems can occur If the controller sees the synchronization word
74. p mcs o lt promdata gt mcs s 2048 u 0 lt bitstream0 gt bit d u c0000 bitstreaml bit Programming Spartan 3AN FPGAs Using iMPACT Beginning in ISE 9 1i Service Pack 3 the iMPACT software will provide programming support for prototyping and initial hardware development Production programming support is described in Third Party Programmer Support page 213 The iMPACT software programs the Spartan 3AN FPGA using the Xilinx programming cables described in Programming Cables and Headers page 193 using the connections shown in Figure 10 1 page 201 Third Party Programmer Support The Xilinx iMPACT software starting with ISE 9 1i Service Pack 3 provides in system programming support for prototyping and initial development However the iMPACT software is not intended for production programming The available Spartan 3AN production programming solutions are listed below by vendor BPM Microsystems BPM Microsystems is a global supplier of engineering and production device programmers and is the leading supplier of automated programming systems to the semiconductor and electronics industries e BPM Microsystems Web Site www bpmicrosystems com Production Hardware Programming Solutions Table 10 6 lists the BPM Microsystems programming solutions for Spartan 3AN FPGAs Support is available both for new installations and for pre existing programmers Socket adapters are required Spartan 3 Generation Configuration U
75. page 147 for ConfigRate settings when using parallel Platform Flash PROMs Despite using slower ConfigRate settings BPI mode is equally fast as the other configuration modes In BPI mode data is accessed at the ConfigRate frequency and internally serialized with an 8X clock frequency Using the BPI Interface after Configuration After the FPGA successfully completes configuration all pins connected to the parallel Flash PROM are available as user I Os If not using the parallel Flash PROM after configuration drive LDCO High to disable the PROM s chip select input The remainder of the BPI pins then become available to the FPGA application including all A 25 0 or A 23 0 address lines the eight D 7 0 data lines and the LDC2 LDC1 and HDC control pins Because all the interface pins are user I Os after configuration the FPGA application can continue to use the interface pins to communicate with the parallel Flash PROM Parallel Flash PROMS are available in densities ranging from 1 Mbit up to 128 Mbits and beyond However a single Spartan 3E 3A 3AN FPGA requires typically less than 6 Mbits for configuration If desired use a larger parallel Flash PROM to contain additional Spartan 3 Generation Configuration User Guide www xilinx com 139 UG332 v1 2 May 23 2007 Chapter 5 Master BPI Mode XILINX nonvolatile application data such as MicroBlaze processor code or other user data such as serial numbers and Ethernet MA
76. page 227 and ranges from approximately 0 4V to 2 0V substantially lower than the NOR Flash PROM s minimum voltage Once all three FPGA supplies reach their respective Power On Reset POR thresholds the FPGA starts the configuration process and begins initializing its internal configuration memory The initialization varies by family and arrays size listed in Table 12 2 page 228 After initialization the FPGA deasserts INIT B selects the NOR Flash PROM and starts accessing data The parallel NOR Flash PROM must be ready for read operations at this time If the 3 3V supply is last in the sequence and does not ramp fast enough or if the parallel NOR Flash PROM cannot be ready when required by the FPGA delay the FPGA configuration process by holding either the FPGA s PROG B input or INIT B input Low described in Delaying Configuration page 229 Release the FPGA when the parallel NOR Flash PROM is ready For example a simple R C delay circuit attached to the INIT B pin forces the FPGA to wait for a preselected amount of time Alternately a Power Good signal from the 3 3V supply or a system reset signal accomplishes the same purpose If using a multi FPGA daisy chain configuration use an open drain or open collector output when driving PROG B or INIT B as multiple FPGAs are connected to the same node Similarly if the Power Good signal is a 3 3V signal remember that PROG B is powered by VccAux Which must be 2 5V on Spartan 3 and Spartan 3
77. re uses the CCLK pin as a user I O after configuration In these cases there might be unrelated devices attached to CCLK which add additional trace length and signal destinations In the Master Serial SPI and BPI configuration modes the FPGA drives the CCLK pin and CCLK should be treated as a full bidirectional I O pin for signal integrity analysis In BPI mode CCLK is only connected to other devices in multi FPGA daisy chains but switching noise at the FPGA pin could potentially cause false clocking The best signal integrity is ensured by following these basic PCB guidelines e Route the CCLK signal as a 50 Q controlled impedance transmission line e Route the CCLK signal without any branching Do not use a star topology e Keep stubs if required shorter than 12 5 mm 0 5 inches e Terminate the end of the CCLK transmission line The clock termination examples shown below use parallel termination Thevenin but other approaches are acceptable In parallel termination the resistor values are twice the characteristic impedance of the board trace The examples shown assume 50 Q trace impedance The disadvantage of parallel termination is that there is always a current path Using series termination at the source and the end minimizes power but use IBIS simulation to optimize resistor values for the specific application 42 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Genera
78. respective VCCO_ supplies The voltage supplied to the JTAG programming cable shown as VREF in Figure 9 1 may be different than the Vccaux supply If the JTAG and VccAux voltages are the same simply connect the FPGA directly to the JTAG programming socket or use 0Q resistors as shown in Table 9 1 The interface becomes a bit more complex if the JTAG voltage is different than the FPGA s VccaAux voltage because current limiting resistors are required If the JTAG cable interface needs to be 3 3V to support devices in the JTAG chain then place a series resistor between the 3 3V interface and the TDI TMS and TCK pins on the FPGA as indicated in Table 9 1 The FPGA s TDO pin is a CMOS output powered by the VccAux supply Even when VccAux 2 5V the TDO output can directly drive a 3 3V input but with reduced noise immunity See XAPP453 The 3 3V Configuration of Spartan 3 FPGAs for additional information Table 9 1 JTAG Cable Interface and Current Limiting Resistor Requirements JTAG Connector FPGA Vccaux Supply Voltage Supply Voltage Current Limiting Resistors 2 5V 2 5V None required or 0 ohm Both voltages are identical 3 3V 2 5V Use current limiting resistors of 68Q or larger 3 3V 3 3V None required or 0 ohm Both voltages are identical JTAG Device ID JTAG User ID Each Spartan 3 Generation FPGA array type has a 32 bit device specific JTAG device identifier as shown in Table 12 4 page 231 The lower 2
79. s internal oscillator generates the configuration clock frequency that controls all the interface timing The FPGA starts configuration at its lowest frequency and increases its frequency for the remainder of the configuration process if so specified in the configuration bitstream The maximum frequency is specified using the ConfigRate bitstream generator option 138 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Using the BPI Interface after Configuration Table 5 6 Maximum ConfigRate Settings for Parallel Flash PROMs Commercial Temperature Range Parallel NOR Flash Read Access Time TAcc tavev ConfigRate Spartan 3A 3AN Bitstream Setting Spartan 3E FPGAs Spartan 3A DSP FPGAs Units 3 260 ns lt 370 ns 6 lt 120 ns 175ns 7 N A lt 150 ns 8 N A lt 129ns 10 N A lt 98 ns 12 49 ns 79ns ns 13 N A 70 ns 17 N A 50ns 22 N A 33ns 25 N A 27ns 27 N A 24ns 33 N A 16ns Notes 1 PCB signal propagation time assumed to be 1 ns Table 5 6 shows the maximum ConfigRate settings for various PROM read access times over the Commercial temperature operating range See Byte Peripheral Interface BPI Timing page 156 for more detailed timing information Spartan 3A 3AN 3A DSP FPGAs have more ConfigRate options and therefore offer finer matching to specific memory interface speeds See Table 5 8
80. support the Read command The Read command command code 0x03 is a legacy command set offered on all 25 series SPI serial Flash devices Set VS 2 0 lt 1 0 1 gt to use this command The Read Array command command code 0xE8 is offered on all Atmel AT45 series DataFlash PROMs Set VS 2 0 lt 1 1 0 gt to use this command Some recent SPI Flash PROMs like the Atmel AT45DB D series PROMs support all three read commands Table 4 4 SPI Read Commands Supported by Spartan 3 Generation FPGAs VS 2 0 Pins Hexadecimal Read Command VS2 VS1 VS0 Command Code Address Bits Dummy Bits 1 1 1 Fast Read OxOB 8 bits all zeros 1 0 1 Read 0x03 24 bit all zeros None 1 1 0 Read Array OxE8 32 bits all zeros Others Reserved e The specific SPI serial memory must be large enough to contain one or more FPGA bitstreams plus any other nonvolatile memory requirements to support the FPGA application after configuration The size of an individual uncompressed FPGA bitstream is provided in Table 4 6 page 92 although the size requirements might be reduced by using Bitstream Format page 24 If using MultiBoot on a Spartan 3A 3AN 3A DSP FPGA add the size of each MultiBoot configuration image Essentially it is the same as an individual FPGA image but MultiBoot allows multiple selectable images within a single FPGA Using a daisy chained configuration scheme a single SPI Flash PROM can s
81. terminate this output to maintain signal integrity See CCLK Design Considerations page 42 INIT_B Open Initialization Indicator Active Active during configuration If User I O If unused in drain Low Goes Low at start of CRC error detected during the application drive bidirectio configuration during the configuration FPGA drives INIT_B INIT_B High nall O Initialization memory clearing Low process Released at the end of memory clearing when the mode select pins are sampled DONE Open FPGA Configuration Done Low Low indicates that the FPGA is not Pulled High via drain during configuration Goes High yet configured external pull up bidirectio when FPGA successfully When High indicates nalI O completes configuration that the FPGA is successfully configured PROG B Input Program FPGA Active Low Must be High to allow Drive PROG B Low When asserted Low for 500 ns or configuration to start and release to longer forces the FPGA to restart reprogram FPGA its configuration process by Hold PROG B to force clearing configuration memory FPGA I O pins into and resetting the DONE and Hi Z allowing direct INIT_B pins once PROG_B programmung access returns High to Flash PROM pins Voltage Compatibility The FPGA s parallel Flash interface signals are within I O Banks 1 and 2 The majority of parallel Flash PROMs use a single 3 3V supply voltage Consequently in most cases the FPGA s VCCO 1 an
82. the DONE pin goes High the INIT B pin is available as a full user I O pin The only exception if the Spartan 3A 3AN 3A DSP Post Configuration CRC feature is enabled in the application in which case the INIT B is dedicated after configuration as well Spartan 3 Generation Configuration User Guide www xilinx com 45 UG332 v1 2 May 23 2007 Chapter 2 Configuration Pins and Behavior during Configuration XILINX If the INIT_B pin is not used by the FPGA application after configuration actively drive it High or Low If left undefined INIT_B like all other unused pins is defined by default as an input with an internal pull down resistor If the FPGA board uses an external pull up resistor on INIT_B then the unused pin will float at an intermediate value due to the presence of both a pull up and pull down resistor To change the default configuration for unused pins change the UnusedPin bitstream generator option setting If the bitstream generator optionPersist Yes is set then INIT B is reserved after configuration completes Spartan 3A 3AN 3A DSP Post Configuration CRC If using a Spartan 3A FPGA and if using the post configuration CRC feature then the INIT B pin becomes a dedicated pin and flags any difference in the CRC signature during normal FPGA operation See Post Configuration CRC Spartan 3A 3AN 3A DSP Only page 292 for more information Spartan 3A 3AN 3A DSP and Spartan 3E FPGA Families INIT B is located
83. the data sheet for the specific device to determine compatibility Daisy Chained Configuration Caution SPI mode daisy chains are supported for Spartan 3E FPGAs only in Stepping 1 and later silicon versions SPI mode daisy chains are supported on all Spartan 3A 3AN 3A DSP FPGA versions If the application requires multiple FPGAs with different configurations then configure the FPGAs using a daisy chain as shown in Figure 4 6 page 103 Daisy chaining from a single SPI serial Flash PROM is supported in Spartan 3E Stepping 1 and later devices It is not supported in Stepping 0 devices Use SPI Flash mode M 2 0 lt 0 0 1 gt for the FPGA connected to the SPI PROM and Slave Serial mode M 2 0 lt 1 1 1 gt for all other FPGAs in 102 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Daisy Chained Configuration SPI Serial Flash PROM PROGRAM the daisy chain After the master FPGA the FPGA on the left in the diagram finishes loading its configuration data from the SPI Flash PROM the master FPGA supplies data to the next FPGA in the daisy chain via the DOUT output pin clocked on the falling CCLK edge Also to successfully configure a daisy chain the GTS_cycle bitstream option must be set to a Startup phase after the DONE_cycle setting for all FPGAs in the chain This is the software default setting Optionally set GTS cycle Done The 0 ohm resistors at the outpu
84. when INIT B goes High DIN Serial Input Serial Data Input for all Receives serial data User I O Modes SPI serial configuration modes from PROM serial data output CCLK Master Output Configuration Clock Drives PROM s clock User I O dedicated Modes SPI treat as Generated by FPGA input on Spartan 3 FPGAs BPI I O for internal oscillator sional Frequency controlled by Man ConfigRate bitstream integrity f generator option See Configuration Clock CCLK page 40 Slave Input Configuration clock input Input configuration Modes clock source DOUT Output Serial Data Output Not used in single User I O FPGA designs DOUT is pulled up not actively driving In a serial daisy chain configuration this pin connects to DIN input of the next FPGA in the chain 50 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Pin Description Table 2 15 Spartan 3 Generation Configuration Pins Associated Modes and Function Continued Spartan 3AN Spartan 3A DSP FPGA MOSI Config FPGA Pin Name Mode s Direction Description During Configuration After Configuration INIT_B All Open drain Initialization Indicator Drives Low after User I O If unused bidirec Active Low See power on reset POR in the application tionalI O Initializing Configuration or when PROG B driveINIT B High or Memory Configuration puls
85. which resets the FPGA The FPGA is reset via the dedicated JTAG interface using the JPROGRAM instruction The FPGA is reset via the Spartan 3A 3AN 3A DSP REBOOT command available using the SelectMAP JTAG or ICAP interfaces 5 On Spartan 3A 3AN 3A DSP FPGAs the FPGA is reset if the Configuration Watchdog Timer CWDT expires during configuration and less than three configuration retries have occurred Power On Reset POR As shown in Figure 12 3 Spartan 3 Generation FPGAs include a Power On Reset POR circuit that holds the FPGA in reset until all of the supply rails required for configuration have reached their threshold levels The three supplies required are the following 1 Vecinr which supplies the internal FPGA core logic 2 Vecaux Which supplies the dedicated configuration pins 3 VCCO_2 on Spartan 3A 3AN 3A DSP and Spartan 3E FPGAs or VCCO_4 or VCCO_BOTTOM in some packages on Spartan 3 FPGAs which supplies the interface pins connected to the external configuration data source i e PROM or processor Power On Reset POR Power rails involved in Configuration Glitch Filter JPROGRAM instruction UG332_c12_11_113006 Figure 12 3 Spartan 3A 3AN 3A DSP and Spartan 3E Reset Circuitry Spartan 3 is similar The FPGA monitors all three supplies Once all three supplies exceed the specified threshold voltage summarized in Table 12 1 page 227 from the associated FPGA data sheet the POR circuit releases t
86. 0 V supplies are already applied and valid The time from when the FPGA s Tiu Power On Reset POR circuit is 1to7 1to 18 released to the rising transition of the INIT B pin Spartan 3A 3AN 3A DSP and Configuration Watchdog Timer Spartan 3A 3AN 3A DSP FPGAs include a configuration watchdog timer CWDT which makes SPI Flash configuration more robust even when the 3 3V supply is applied last In Master SPI mode the CWDT ensures that the FPGA reads a valid synchronization word from the SPI Flash PROM within the first 216 1 cycles of CCLK The synchronization word is part of the FPGA configuration bitstream If the FPGA does not find the synchronization word the CWDT forces the FPGA to automatically resend the SPI Flash read command and to retry the configuration process The CWDT retries to successfully configure from SPI Flash three times before failing If the FPGA fails to configure it then drives the INIT B pin Low indicating a failure CCLK Frequency In SPI Flash mode the FPGA s internal oscillator generates the configuration clock frequency The FPGA provides this clock on its CCLK output pin driving the PROM s Slave Clock input pin The FPGA begins configuring using its lowest frequency setting If so specified in the configuration bitstream the FPGA increases the CCLK frequency to the specified setting for the remainder of the configuration process The maximum frequency is specified using the ConfigRa
87. 1 Address 01 0011 0x13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 AO The context of the GENERAL2 register depends on whether the next MultiBoot address is in an external parallel NOR Flash BPI mode or an external SPI serial Flash SPI mode In BPI mode the GENERAL2 register contains the upper 10 bits of the 26 bit BPI address as shown in Table 14 5 The upper six bits of the register are reserved Table 14 5 GENERAL2 Register Definition for BPI Mode Options GENERAL2 Address 01 0100 0x14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD A24 A23 A22 A21 A20 A19 A18 A17 A16 In SPI mode the GENERAL2 register contains the upper 8 bits of the 24 bit SPI address as shown in Table 14 6 The upper eight bits of the register contain the specific byte wide read command for the attached external SPI serial Flash device Table 14 6 GENERAL2 Register Definition for SPI Mode Options 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPI Flash Read Command Upper Byte of 24 bit SPI Read Address C7 C6 C5 C4 C3 C2 C1 CO A23 A22 A21 A20 A19 A18 A17 A16 Command Register CMD Configuration commands cont
88. 1 If so be careful to connect x8 x16 Flash PROMs correctly as shown in Figure 5 3 and Table 5 7 Also remember that the D 14 8 data connections require FPGA user I O pins but that the D15 data is already connected for the FPGA s AO pin Spartan 3 Generation Configuration User Guide www xilinx com 141 UG332 v1 2 May 23 2007 Chapter 5 Master BPI Mode EZ XILINX Table 5 7 FPGA Connections to Flash PROM with 1015 A 1 Pin Connection to Flash PROM with x8 Flash PROM Interface After x16 Flash PROM Interface After FPGA Pin 1015 A 1 Pin FPGA Configuration FPGA Configuration LDC2 BYTE Drive LDC2 Low or leave Drive LDC2 High unconnected and tie PROM BYTE input to GND LDC1 OE Active Low Flash PROM Active Low Flash PROM output enable control output enable control LDCO CS Active Low Flash PROM chip Active Low Flash PROM chip select control select control HDC WE Flash PROM write enable Flash PROM write enable control control A 23 1 A n 0 A n 0 A n 0 AO IO15 A 1 IO15 A 1 is the least IO15 A 1 is the most significant significant address input data line IO15 D 7 0 IO 7 0 IO 7 0 IO 7 0 UserI O Upper data lines IO 14 8 not Upper data lines IO 14 8 not IO 14 8 required unless used as x16 Flash interface after configuration required Some x8 x16 Flash PROMs have a long setup time requirement on the BYTE signal For the FPGA to configure correctly the PR
89. 1 2 May 23 2007 Chapter 4 Master SPI Mode XILINX 11 Select Bypass when prompted for the Platform Flash PROM programming file as shown in Figure 4 26 p Assign New Configuration File G3 C3 msas Ongo O templates O sst File type All Design Files mes exo isc bsd None Cancel All C Enable Programming of SPI Flash Device Attached to this FPGA C Enable Programming of BPI Flash Device Attached to this FPGA UG332_c4_28 032907 Figure 4 26 Bypass the Platform Flash PROM 12 As shown in Figure 4 27 the iMPACT software then displays the JTAG chain for the XC3S700A Spartan 3A FPGA followed by the XCF045S Platform Flash PROM Click to highlight the FLASH memory attached to the XC35700A FPGA This action enables the command options shown in Step 13 iMPACT C Data my_designs switches_leds default ipf Boundary Scan File Edit View Operations Output Debug Window Help aalBoundary Scan H 2915laveSerial Sai SelectMAP i Ta Desktop Configuration H 2 Direct SPI Configurati m E SystemACE xc3s700a xcf 4s B PROM File Formatter top level bit bypass Program Succeeded UGS332 c4 25 032907 Figure 4 27 iMPACT Presents JTAG Chain Shows Attached Flash PROM 122 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Indirect Programming using iMPACT 13 Double click Program Note Step
90. 18 Click Open 19 When asked to add another design file click Yes 20 Select the second FPGA bitstream 21 Click Open Continue with Steps 19 21 until all FPGA bitstream files are selected After entering the last bitstream click No from Step 19 when asked to add another design file 22 Click OK 152 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX In System Programming Support 23 As shown in Figure 5 12 the iMPACT software graphically displays the selected configuration topography In this example a single parallel PROM provides the bitstreams to two XC3S700A FPGAs using a serial daisy chain configuration iMPACT C Data my_designs led_crazy default ipf PROM File Formatter Z File Edit View Operations Options Output Debug Window Help le BB Xs 5 1 xf H BS Boundary Scan aa SlaveSerial m SelectMAP 1 Desktop Configu t malDirect SPI Config gt iMPACT Modes xc3s700a first_fpga bit xc3s700a second_fpga bit Figure 5 12 Generate Parallel PROM File 24 Click Generate File 25 The iMPACT software indicates when the PROM File Generation Succeeded In System Programming Support In production applications the parallel Flash PROM is typically preprogrammed before it is mounted on the printed circuit board In system programming support is available from third par
91. 18 occurs later 14 Click the Programming Properties option under Category as shown in Figure 4 28 Programming Properties Fa Programming Properties UG332 c4 29 032907 Figure 4 28 SPI PROM Programming Options 15 Check Verify Unchecking Verify reduces programming time but the iMPACT software can only guarantee correct programming for a verified PROM 16 Check Erase Before Programming Unchecking the Erase option reduces programming time However Xilinx recommends erasing the PROM when downloading a new FPGA bitstream 17 Click OK 18 TheiMPACT software indicates successful programming as shown in Figure 4 28 The FPGA is configured with the new programming file Spartan 3 Generation Configuration User Guide www xilinx com 123 UG332 v1 2 May 23 2007 Chapter 4 Master SPI Mode XILINX Serial Peripheral Interface SPI Configuration Timing Figure 4 29 provides example waveforms for Master SPI configuration The following items correspond to the numbered markers in Figure 4 29 The symbols for the FPGA timing parameters are listed in Table 4 15 The required SPI Flash PROM timing and the dependencies on FPGA timing is provided in Table 4 16 page 126 e Mode input pins M 2 0 and variant select input pins VS 2 0 are sampled when INIT B goes High After this point input values do not matter until DONE goes High at which point these pins become user l O pins INIT B New ConfigRate
92. 2 081506 Figure 9 2 Typical JTAG IEEE 1149 1 Architecture Test Access Port TAP The Spartan 3 Generation TAP contains four mandatory dedicated pins as specified by the protocol given in Table 3 1 and illustrated in Figure 3 1 a typical JTAG architecture Three input pins and one output pin control the 1149 1 Boundary Scan TAP controller Optional control pins such as TRST Test Reset and enable pins might be found on devices from other manufacturers It is important to be aware of these optional signals when interfacing Xilinx devices with parts from different vendors because they might need to be driven The TAP controller is a state machine 16 states shown in Figure 9 3 The four mandatory TAP pins are outlined in Table 9 2 186 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Boundary Scan for Spartan 3 Generation FPGAs Using IEEE Standard 1149 1 0 oCmueresrmoce GexeoroR scan SELESTI SGAN 0 0 emus omun 0 0 SHIFT DR o SHIFTIR 0 1 1 L gt exiti prR H San A 0 PAUSE DR Jo PAUSE IR 0 1 B EXIT2 DR 0 EXIT2 IR 1 1 UPDATE DR UPDATE IR 1 0 1 0 i UG332_C9_03_080906 Figure 9 3 Test Access Port TAP State Machine Table 9 2 Spartan 3 Generation TAP Controller Pins Pin Description TDI Test Data In This pin is the serial input to all JTAG
93. 2 732 640 4 Mbit A 18 0 XC3851400A AN 4 755 296 8 Mbit A 19 0 XC3SD1800A 8 197 280 8 Mbit A 19 0 Spartan 3A DSP XC3SD3400A 11 718 304 16 Mbit A 20 0 Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 137 Chapter 5 Master BPI Mode XILINX Table 5 5 Number of Bits to Program a Spartan 3A 3AN 3A DSP or Spartan 3E FPGA and Smallest Usable Parallel PROM Continued Family Spartan 3E Uncompressed Smallest Usable Minimum Required FPGA File Sizes bits Parallel Flash PROM Address Lines XC3S100E 581 344 1 Mbit A 16 0 XC3S250E 1 353 728 2 Mbit A 17 0 XC3S500E 2 270 208 4 Mbit A 18 0 XC3S1200E 3 841 184 4 Mbit A 18 0 XC3S1600E 5 969 696 8 Mbit A 19 0 A multiple FPGA daisy chained application requires a parallel Flash PROM large enough to contain the sum of the FPGA file sizes An application can also use a larger density parallel Flash PROM to hold additional data beyond just FPGA configuration data For example the parallel Flash PROM might also contain the application code for a MicroBlaze RISC processor core implemented within the Spartan 3A 3AN 3A DSP or Spartan 3E FPGA After configuration the MicroBlaze processor either executes directly from the external Flash memory or it copies the code to other faster system memory before executing the code CCLK Frequency In BPI mode the FPGA
94. 2007 XILINX Spartan 3A 3AN 3A DSP MultiBoot the default bitstream even resending the appropriate SPI Flash read command if using the SPI configuration mode Similarly a Spartan 3A 3AN 3A DSP FPGA can also recover from a MultiBoot operation to a bitstream that has a correct synchronization word but that eventually issues a CRC error for some reason One such example might be if the next MultiBoot bitstream was only partially written in Flash Set the Reset on err Yes bitstream option to cause the FPGA to automatically re initialize and retry configuration should a CRC error occur In BPI and SPI modes if reconfiguration fails three times then the FPGA halts and drives the INIT B pin Low Pulsing the PROG B pin or cycling power restarts the configuration process from the beginning These features are particularly useful when providing the FPGA with live Flash updates The counter that keeps track of the three failed configurations is reset only when PROG B is pulsed or power is cycled it is not reset after a successful configuration The FPGA will stop attempting configuration if the initial design is good but the MultiBoot bitstream is bad after the third attempt at MultiBoot Note that when configuring via SPI or BPI modes and using the Reset on err Yes bitstream option any combination of successful and failed configurations over any period of time will halt after the third failed configuration and require assertion of PROG B
95. 3 the FPGA s SPI pins are fully controlled by the FPGA application Direct In system Programming Using FPGA as Intermediary This method is typically used to update the SPI serial Flash using the FPGA as the actual programmer The advantage is that the FPGA s flexibility allows the FPGA to connect to practically any digital interface to receive the programming data The FPGA based programmer can be included as part of the application or alternatively downloaded temporarily into the FPGA using the FPGA s JTAG interface The Spartan 3E Starter Kit includes a design example that programs the attached STMicro M25P16 SPI Flash using an RS 232 connection to a PC or workstation e PicoBlaze RS 232 to STMicro SPI Flash Programmer www xilinx com products boards s3estarter reference designs htmftpicoblaze spi flash programmer The Spartan 3A Starter Kit includes a design example that programs the attached Atmel AT45DB161D DataFlash PROM using an RS 232 connection to a PC or workstation e PicoBlaze RS 232 to Atmel DataFlash Programmer www xilinx com products boards s3astarter reference designs htm atmel spi flash programmer 108 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Generating the Bitstream for a Master SPI Configuration Indirect In System Programming Using FPGA JTAG Chain The FPGA has JTAG test capabilities which include the standard PRELOAD
96. 3 FPGAs Xilinx Platform Flash PROM Chapter Madier Parallel Mode but possible in XCFxxP PROMs only Spartan 3E 3A 3AN 3A DSP FPGAs using BPI mode or Slave Parallel mode Commodity Parallel 4 Spartan 3E Spartan 3A 3AN 3A DSP NOR Flash PROM Chapter 5 Master BPI Mode FPGAs Commodity SPI Serial Flash PROM Chapter 4 Master SPI Mode Ap aee ee pes The downloaded FPGA configuration modes generically called Slave modes are also available with either a serial or byte wide data path In Slave mode an external intelligent agent such as a processor microcontroller DSP processor or tester downloads the configuration image into the FPGA as shown in Figure 1 2 The advantage of the Slave configuration modes is that the FPGA bitstream can reside just about anywhere in the overall system The bitstream could reside in Flash on board along with the host processor s code It could reside on a hard disk It could originate somewhere over a network connection The possibilities are nearly endless Sem Byte Wide Spartan 3 Spartan 3 Processor Generation Processor Generation Microcontroller FPGA Microcontroller FPGA SERIAL DATA DATA 7 0 SELECT READ WRITE CLOCK a Slave Serial mode CLOCK l l l l l l l l l l l JTAG Tester Spartan 3 Processor Generation FPGA l l l l l l l l l l l l l i Microcontroller c Slave Parallel mode SelectMAP
97. 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Authentication Design Examples Blueberry is indeed Blue The bitstream loaded from the PROM is authentic and the FPGA application is enabled for full operation The Spartan 3E Starter Kit board includes a design example demonstrating this technique This same method also applies for Spartan 3A Spartan 3AN Spartan 3A DSP FPGAs e Low Cost Design Authentication for Spartan 3E FPGAs www xilinx com products boards s3estarter reference_designs htm authenticatio n Spartan 3A 3AN 3A DSP FPGA Authenticating a Downloaded Design Authentication also works when downloading an FPGA design In Figure 15 11 an intelligent host such as a microprocessor microcontroller or JTAG tester downloads a bitstream into a Spartan 3A 3AN 3A DSP FPGA The bitstream is stored somewhere in the system either in local memory a disk drive or obtained via a network connection The downloaded FPGA application is not yet fully authenticated but is partially functional to support the authentication process meee Spartan 3A 3AN 3A DSP FPGA FPGA Bitstream FPGA Fabric Device DNA DNA UG332_c16_11_040107 Figure 15 11 Intelligent Host Downloads a Spartan 3A Bitstream In Figure 15 12 the intelligent host reads the FPGA s Device DNA identifier either through the FPGA fabric or via the FPGA s JTAG port Using the Device DNA value the host either computes an
98. 332 v1 2 May 23 2007 XILINX General Configuration Control Pins Spartan 3A 3AN 3A DSP and Spartan 3E FPGA Families On the Spartan 3A 3AN 3A DSP and Spartan 3E FPGA families the M 2 0 mode select pins are borrowed during configuration and become full user I O after configuration successfully completes The M 2 0 pins are powered by the VCCO_2 supply Spartan 3E FPGAs The Spartan 3E FPGA mode pins do not have dedicated pull up resistors during configuration However these pins have optional pull up resistors during configuration controlled by the Spartan 3E HSWAP pin If the mode pins are unconnected and if the HSWAP is Low then the Spartan 3E FPGA defaults to the Slave Serial configuration mode M 2 0 lt 1 1 1 gt Spartan 3A 3AN 3A DSP FPGAs The Spartan 3A 3AN 3A DSP FPGA mode pins have dedicated internal pull up resistors during configuration regardless of the PUDC B pin If the mode pins are unconnected then the Spartan 3A 3AN 3A DSP FPGA defaults to the Slave Serial configuration mode M 2 0 lt 1 1 1 gt Spartan 3 FPGA Family On the Spartan 3 FPGA family the M 2 0 mode select pins are dedicated inputs powered by the Vecaux supply Before and during configuration the mode pins have a relatively strong internal pull up resistor to the Vccaux supply regardless of the HSWAP EN pin If the mode pins are unconnected then the FPGA defaults to the Slave Serial configuration mode M 2 0 lt 1 1 1 gt
99. 3V The Dual Purpose configuration pins operate at other voltages by appropriately setting the voltage on the associated power rail For Spartan 3A 3A DSP and for Spartan 3AN FPGAs in modes other than Internal Master SPI and Spartan 3E FPGAs the Dual Purpose configurations pins are supplied by the VCCO 2 rail plus VCCO 1 in BPI mode In Spartan 3 the Dual Purpose configuration pins are supplied by VCCO 4 plus VCCO 5in any of the parallel configuration modes In general set the configuration voltage to either 2 5V or 3 3V The change on the Vcco supply also changes the I O drive characteristics For example with Veco 3 3V the output current when driving High Ig increases to approximately 12 to 16 mA while the current when driving Low Ior remains 8 mA At Vcco 1 8V the output current when driving High lop decreases slightly to approximately 6 to 8 mA Again the current when driving Low Io remains 8 mA Table 2 20 Supported Configuration Interface Voltages Dedicated Pins Dual Purpose Pins Dual Purpose Supported Supported VccAux Configuration Pin Configuration Supply FPGA Family Voltage Options Supply Rails Voltage Options Spartan 3A 25V Spartan 3A DSP 33V VCCO 2 2 5V Ben sometimes VCCO 1 3 3V Spartan 3AN 3 3V Spartan 3E VCCO 2 2 5V 2 5V FPGAs sometimes VCCO 1 3 3V Spartan 3 VCCO 4 2 5V 2 5V FPGAs sometimes VCCO 5 3 3V Notes 1 Spartan 3AN FPGAs in Internal Master SPI mode
100. 6 Figure 3 13 Generate PROM File 19 Click Generate File 20 The iMPACT software indicates when the PROM file is successfully created Platform Flash In System Programming via JTAG using iMPACT Both the FPGA and the Platform Flash PROM are in system programmable via the JTAG chain Download support for prototyping purposes is provided by the Xilinx iMPACT programming software and the associated Xilinx Parallel Cable IV MultiPRO or Platform Cable USB programming cables Prepare Board for Programming Before attempting to program the Platform Flash PROM complete the following steps 1 Ensure that the board is powered 2 Ensure that the programming cable is properly connected both the board and to the computer or workstation Spartan 3 Generation Configuration User Guide www xilinx com 79 UG332 v1 2 May 23 2007 Chapter 3 Master Serial Mode XILINX Programming via iMPACT The following steps describe how to program a Platform Flash PROM using the iMPACT software and a Xilinx programming cable 1 Click Configure devices using Boundary Scan JTAG from within iMPACT as shown in Figure 3 14 If the Automatically connect option is selected iMPACT will query the devices in the JTAG chain and automatically detect the chain topology iMPACT Welcome to iMPACT Please select an action from the list below vV Configure devices using Boundary Scan JTAG Automatically connect to a cable and identif
101. 73 UG332 v1 2 May 23 2007 XILINX Chapter 15 Protecting FPGA Designs Spartan 3 and Spartan 3E Security Levels Table 15 1 shows the available security levels on Spartan 3 and Spartan 3E FPGAs Spartan 3A 3AN 3A DSP FPGAs provide an extra level as shown in Table 15 2 Table 15 1 Spartan 3 and Spartan 3E Security Levels Security Level Description None Default Unrestricted access to all configuration and Readback functions Levell Disable all Readback functions from either the SelectMAP or JTAG port Disable all configuration and Readback functions from all configuration Level2 and JTAG ports Spartan 3A 3AN 3A DSP Security Levels Spartan 3A 3AN 3A DSP FPGAs provide an additional security level as shown in Table 15 2 Readback can be optionally disabled completely or disabled except for internal access from the FPGA application via the Internal Configuration Access Port ICAP Table 15 2 Spartan 3A 3AN 3A DSP BitGen Security Levels Security Level Description None Default Unrestricted access to all configuration and Readback functions Level1 Disable all Readback functions from both the SelectMAP or JTAG ports Readback via the Internal Configuration Access Port ICAP allowed Level2 Disables all Readback operations on all ports Disable all configuration and Readback functions from all configuration Level3 and JTAG ports Setting the Security Level in the Bitstream Th
102. 8 bits represent the device vendor Xilinx and device identifier The upper four bits ignored by most tools represent the revision level of the silicon mounted on the printed circuit board The Spartan 3 Generation JTAG interface provides the option to store a 32 bit User ID loaded during configuration The User ID value is specified via the UserID configuration bitstream option shown in Table 11 2 page 218 or in Step 11 Figure 1 7 page 29 from the ISE Project Navigator software The user ID provides a convenient means to store an identifier or revision code for the FPGA bitstream loaded into the FPGA This is different than the Device DNA identifier which is unique to a specific Spartan 3A 3AN 3A DSP FPGA not the bitstream and permanently factory programmed in the FPGA 184 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Using JTAG Interface to Communicate to a Configured FPGA Design Using JTAG Interface to Communicate to a Configured FPGA Design After the FPGA is configured using any of the available modes the JTAG interface offers a possible communications channel to internal FPGA logic The Boundary Scan BSCAN page 239 design primitive provides two private JTAG instructions to create an internal boundary scan chain Boundary Scan for Spartan 3 Generation FPGAs Using IEEE Standard 1149 1 Spartan 3 Generation FPGAs are fully compliant with the IEEE Standa
103. 81106 Figure 7 9 Readback Abort Sequence Spartan 3 Generation Configuration User Guide www xilinx com 175 UG332 v1 2 May 23 2007 Chapter 7 Slave Parallel SelectMAP Mode XILINX 1 Thereadback sequence begins normally The processor changes the RDWR B pin while the FPGA is still selected CSI B is Low BUSY Spartan 3 3E only goes High if CSI B remains asserted Low The FPGA drives the status word onto the data pins if RDWR B is High reading data from the FPGA The Status value is not presented by the FPGA if RDWR B is Low ABORT operations during Readback typically are not followed by a status word because the RDWR B signal will be Low causing the ABORT When RDWR B is Low the processor is writing to the FPGA and the FPGA s D 7 0 pins are inputs The FPGA cannot present the Status value ABORT Status Word During the configuration ABORT sequence the FPGA presents a status word onto the D 7 4 pins The other data pins D 3 0 are all High The key for that status word is given in Table 7 3 Table 7 3 ABORT Status Word Bit Number Status Bit Name Meaning D7 CFGERR B Configuration Error active Low 0 A configuration error has occurred 1 No configuration error D6 DALIGN Synchronization Word Received 0 2 No synchronization word received 1 Synchronization word received D5 RIP Readback In Progress 0 No readback in progress 1 A readback is in progress D4 IN_ABORT_B ABORT
104. 9 Generating the Bitstream for a Master SPI Configuration 109 ConfigRate CCLK Frequency sssesesesseeee eee 109 StartupCIK CCL iuis Rr ek RPRe RR D e Hp b dk ke rbi kd eh ed 110 DriveDone Actively Drive DONE Pin eee e 110 DONE cycle Daisy Chains with Spartan 3E Master sssssssssss 110 GTS cycle Global Three State Release Timing for Daisy Chains 110 Preparing an SPI PROM File chic aueh pP RUE R Race uae ac RR d egi E Rd ERO 110 IMPACT REEL 110 Iu avec eE 114 Direct Programming using iMPACT ssessssesseeess 115 Prepare Board for Programming ssss e 115 Programming viaiMPACT ssssseeeeeee n 116 Indirect Programming using iMPACT sese 118 Programming SCHIP is vor dear eda track doe toa Se ee aed 118 Using IMPACT eset epe e erem epe dene eee eae rad lee 119 Serial Peripheral Interface SPI Configuration Timing 124 Multi Package Layout isesesssssssssss ne 126 Saving POWEL do neni Eus r denda pofi dg d citt ua dtt akon dpi cioe 127 Deassert CSO B to Enter Standby Mode 0 00 cece eens 127 Deep Power Down Mode ssssssesseslse eee 127 Enter Deep Power Down Mode 06 00 cece nen 128 Release from Deep Power Down Mode sseeeeee nen 128 Spartan 3A 3AN 3A DSP MultiBoot Precautions isses 128 Chapter 5 Master BPI M
105. AD 0 56 an 5 57 bit bit loadable shift register DOUT m gt READ 1 x 54 55 56 55 bit unique device identifier Device DNA 0 1 Factory programmed unchangeable UGG32 c15 01 110206 Figure 15 4 DNA PORT Operation If both READ and SHIFT are Low the output shift register holds its value and DOUT remains unchanged Table 15 5 DNA PORT Operations Operation DIN READ SHIFT CLK Shift Register DOUT HOLD X 0 0 X Hold previous value Hold previous value Bit 56 of READ X 1 X T Parallel load with 57 bit ID identifier which is always 1 Shift DIN into bit 0 shift contents of Shift Bit 56 of Shift SERE BIS 1 T Register toward DOUT Register Notes X Don t care Rising clock edge The Spartan 3A Starter Kit board has a design example that demonstrates how to read the Device DNA value e Spartan 3A 3AN 3A DSP Device DNA Reader Design Example www xilinx com products boards s3astarter reference designs htmstdna reader Interface Timing Table 15 6 provides the interface timing for the DNA PORT design primitive The timing is the same regardless of the FPGA s speed grade As always please refer to the associated data sheet for official timing values Table 15 6 DNA PORT Interface Timing Symbol Description Min Max Unit tpNAssu Setup time on SHIFT before the rising edge of CLK 1 0 ns tpnasy Hold time on SHIFT after the rising ed
106. AN FPGA XC38400A AN 1 886 560 XC38S700A AN 2 732 640 XC3851400A AN 4 755 296 XC3SD1800A 8 197 280 Spartan 3A DSP XC3SD3400A 11 718 304 XC3S100E 581 344 XC3S250E 1 353 728 Spartan 3E FPGA XC3S500E 2 270 208 XC3S1200E 3 841 184 XC3S1600E 5 969 696 XC3550 439 264 XC38200 1 047 616 XC38400 1 699 136 XC3S1000 3 223 488 Spartan 3 FPGA XC3S1500 5 214 784 XC3S2000 7 673 024 XC3S4000 11 316 864 XC35S5000 13 271 936 Bitstream Format The typical FPGA user does not need a bit level understanding of the configuration stream However for the purpose of understanding configuration options and for debugging an overview of the bitstream format is helpful For more details see the chapter Sequence of Events and XAPP452 Spartan 3 Advanced Configuration Architecture 24 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX FPGA Configuration Bitstream Sizes Synchronization Word Embedded at the beginning of an FPGA configuration bitstream is a special synchronization word The synchronization word alerts the FPGA to upcoming configuration data and aligns the configuration data with the internal configuration logic Any data on the configuration input pins prior to synchronization is ignored Because the synchronization word is automatically added by the Xilinx bitstream generation software this step is transparent in most applications The length and contents of the synchroniz
107. C IDs In such an example the FPGA configures from parallel Flash PROM Then using FPGA logic after configuration a MicroBlaze processor embedded within the FPGA can either execute code directly from parallel Flash PROM or copy the code to external DDR SDRAM and execute from DDR SDRAM Similarly the FPGA application can store nonvolatile application data within the parallel Flash PROM For Spartan 3E FPGAs the configuration data is stored starting at either at location 0 BPI Up or starting at the highest address location BPI Down or at both locations for when performing MultiBoot configuration see Spartan 3E MultiBoot page 249 For Spartan 3A 3AN 3A DSP FPGAs there is always a configuration image starting at location 0 BPI Up and possibly at other higher address locations when performing Spartan 3A 3AN 3A DSP MultiBoot configuration see Spartan 3A 3AN 3A DSP MultiBoot page 257 Store any additional data beginning in other available parallel Flash PROM sectors Caution Do not mix FPGA configuration data and user data in the same sector Mixing both configuration and user data in the same sector should only be done with extreme caution Similarly the parallel Flash PROM interface can be expanded to additional parallel peripherals The address data LDC1 OE and HDC WE control signals are common to all parallel peripherals Connect the chip select input on each additional peripheral to one of the FPGA user I O pins If
108. C7 C6 C5 C4 C3 C2 C1 CO 10 SPI mode example Low A23 A22 A21 A20 A19 A18 A17 A16 12 1 Word Low 1 0 1 0 0 0 0 1 oxa1 13 Reserved High 0 0 0 0 0 0 0 0 0x00 14 MODE_REG Register Low 0 Nov BOOTMODE BOOTVSEL 16 1 Word Low 1 0 1 0 0 0 0 1 oxa1 17 High 0 0 0 0 0 0 0 0 oxoo REBOOT Command 18 Low 0 0 0 0 1 1 1 0 oxoE 19 High 0 0 1 0 0 0 0 0 0x20 No Op 20 Low 0 0 0 0 0 0 0 0 oxoo Spartan 3 Generation Configuration User Guide www xilinx com 261 UG332 v1 2 May 23 2007 Chapter 14 Reconfiguration and MultiBoot XILINX MultiBoot Registers Generally there are three ICAP registers involved in a MultiBoot application The address of the next MultiBoot bitstream is stored in registers GENERAL1 and GENERAL2 although they can be preloaded via BitGen option next_config_addr To trigger a MultiBoot event the FPGA application must issue a REBOOT command using the CMD register Next MultiBoot Start Address GENERAL1 GENERAL2 The start address of the next MultiBoot configuration image is stored in two 16 bit registers called GENERAL1 and GENERAL 2 These registers can also be preloaded using the bitstream generation BitGen option next config addr The GENERALI and GENERAL2 registers are not cleared or modified during a MultiBoot event The GENERALI register holds the lower 16 bits of the next MultiBoot address as shown in Table 14 4 Table 14 4 GENERAL1 Register Definition GENERAL
109. CINT HSWAP SPI Mode VCC Spartan oA DSP igs J cy a ST Micro Feds Mm BEER a M25Pxx se S SPI Flash CCLK C i w Spartan 3E 3A AN W Select Epartan 3A DSP Spartan 3A 3AN 47 Spartan 3A DSP 1 h ve internal pull up resistors GND VCCAUX x Cable Header JTAG Interface PROG B ilin SPI Direct Programming umper PROGRAM 4 Dedicated internal pull up resistor UG332_c4_01_040107 Figure 4 1 SPI Flash Configuration Interface for STMicro compatible Devices Although SPI is a fairly standard and ubiquitous four wire interface various available SPI Flash PROMs use different command protocols The FPGA s variant select pins VS 2 0 define how the FPGA communicates with the SPI Flash including which SPI Flash command the FPGA issues to start the read operation and the number of dummy bytes inserted before the FPGA expects to receive valid data from the SPI Flash Table 4 2 shows the available SPI Flash PROMs tested or expected to operate with Spartan 3E 3A FPGAs Other compatible devices might work but have not been hardware verified by Xilinx All other VS 2 0 values are reserved for future use Consult the data sheet for the desired SPI Flash device to determine its suitability Figure 4 1 shows the general connection diagram for SPI Flash PROMs that support the 0x0B FAST READ commands which are most modern 25 series PROMs The example shown is an STMicro M25Pxx PROM 86 www xilin
110. CLK This PROM data must be valid and setup on the FPGA s DIN serial data input before next rising edge of CCLK Table 4 15 lists the various FPGA timing parameters associated with the SPI configuration interface Table 4 15 FPGA Timing Symbols for Serial Peripheral Interface SPI Configuration Mode Symbol Description TCCLK1 Initial CCLK clock period TCCLKn CCLK clock period after FPGA loads ConfigRate setting TMINIT Setup time on the VS 2 0 variant select pins and the M 2 0 mode select pins before the rising edge of INIT_B Tccrkia Minimum CCLK Low time at the initial default ConfigRate setting TCCLKLn Minimum CCLK Low time at the ConfigRate setting specified in the FPGA bitstream TINITM Hold time on the VS 2 0 variant select pins and the M 2 0 mode select pins before the rising edge of INIT B Tcco MOSI output valid delay after CCLK falling clock edge Tpcc Setup time on the DIN data input before CCLK rising clock edge Tccp Hold time on the DIN data input after CCLK rising clock edge Spartan 3 Generation Configuration User Guide www xilinx com 125 UG332 v1 2 May 23 2007 Chapter 4 Master SPI Mode XILINX Table 4 16 shows the relationship between the SPI Flash PROM timing specifications and the FPGA s configuration timing specifications For example the SPI Flash clock to output time Ty must be less than or equal the FPGA minimum CCLK Low time and the specified Con
111. DONE pin has gone High which is distinctly different than programming the FPGA immediately after power is applied To reconfigure the FPGA pulse the PROG B pin Low which is identical to configuration or reconfigure by resynchronizing the FPGA and sending configuration data Generally the FPGA s SelectMAP pins become user 1 O pins after configuration because the Persist No bitstream option is set by default To reconfigure a device in Select MAP mode without pulsing PROG B set the bitstream option Persist Yes which reserves the Slave Parallel SelectM AP interface pins after configuration preventing them from becoming user I O pins Reconfigure the FPGA by clocking the appropriate synchronization word shown in Table 12 3 page 230 into the SelectMAP port The remainder of the operation is identical to configuration as described above SelectMAP Data Ordering On Spartan 3 Generation FPGAs by Xilinx convention data bit D0 is the most significant bit msb and bit D7 is the least significant bit Isb However this convention varies between vendors and can be especially confusing when the FPGA uses one convention and the attached processor downloading configuration data to the FPGA uses the opposite Spartan 3 Generation Configuration User Guide www xilinx com 177 UG332 v1 2 May 23 2007 Chapter 7 Slave Parallel SelectMAP Mode XILINX convention Consequently it is crucial to understand how the data ordering in the
112. DWR_B Input this input ignored on Spartan 3A 3AN 3A DSP FPGAs i ANA AA AI CANWARWRAKN Mode input pins M 2 0 are sampled when INIT B goes High After this point er QUOQUUUE o1 ANNIN YY eee input values do not matter until DONE goes High at which point the mode pins Input PPM MA l N N M M M become user l O pins Twunit Open drain NW HSWAP or PUDC B must be stable before INIT B goes High and remain constant throughout configuration Timm Pin initially pulled High by internal pull up resistor if HSWAP or PUDC_B input is Low Pin initially high impedance Hi Z if HSWAP or PUDC_B input is High LDC 2 0 HDC oui ceti cuite ete i CSO_B evinenceicctincnissetineansnes P New ConfigRate active T NITADDR Took Toctkn 8 OxFF FFFF OxFF FFFE Byte 1 eee Data Shaded values indicate timing specifications for external parallel NOR Flash PROM UG332 5 08 040107 Figure 5 14 BPI Configuration Timing Waveform Spartan 3E BPI Down mode shown The following numbered items correspond to the markers provided in Figure 5 14 1 The M 2 0 mode pins must be set for BPI mode Only the Spartan 3E FPGA supports the BPI Down mode Both Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs support BPI Up mode See Table 5 2 The mode pin must be setup with sufficient time before the rising edge of INIT_B 2 On Spartan 3E FPGAs the CSI B select input and the RDWR_B r
113. E FPGAs and may be 2 5V or 3 3V on Spartan 3A 3A DSP FPGAs Add a 68Q or larger series resistor if there is a voltage mismatch Spartan 3A 3AN 3A DSP and Configuration Watchdog Timer Spartan 3A 3AN 3A DSP FPGAs include a configuration watchdog timer CWDT which makes parallel Flash configuration more robust even when the 3 3V supply is applied last In Master BPI mode the CWDT ensures that the FPGA reads a valid synchronization word from the parallel NOR Flash PROM within the first 216 1 cycles of CCLK The synchronization word is part of the FPGA configuration bitstream If the FPGA does not find the synchronization word the CWDT forces the FPGA to automatically restart the BPI the configuration process The CWDT retries to successfully configure from parallel NOR Flash three times before failing If the FPGA fails to configure it then drives the INIT B pin Low indicating a failure Spartan 3 Generation Configuration User Guide www xilinx com 155 UG332 v1 2 May 23 2007 Chapter 5 Master BPI Mode XILINX Byte Peripheral Interface BPI Timing Figure 5 14 provides a detailed timing diagram for the BPI configuration mode The specific diagram is for the Spartan 3E FPGA family using the BPI Down mode However the timing is also similar for the Spartan 3A 3AN 3A DSP FPGA families and for the BPI Up mode PROG B Input PUDC B HSWAP Input CSI B Input NN this input ignored on Spartan 3A 3AN 3A DSP FPGAs R
114. FPGA Families The Master SPI configuration mode is available using either the Spartan 3A 3AN 3A DSP or Spartan 3E FPGA families It is not provided on the Spartan 3 FPGA family as summarized in Table 4 1 Table 4 1 Master SPI Mode Support within Spartan 3 Generation FPGAs Spartan 3A 3AN Spartan 3 Spartan 3E Spartan 3A DSP FPGA FPGA FPGA Supports multi FPGA daisy chain Step 1 only Yes configurations Supports MultiBoot configuration No Yes Watchdog Timer retry Master SPI No Yes CCLK directionality during Master Ae not Output only for SPI mode P He x po I O improved signal pas integrity FPGAs M 2 0 and VS 2 0 pins have No dedicated internal pull up resistors Optional Yes during configuration controlled by HSWAP Choosing a Compatible SPI Serial Flash The Spartan 3E and Spartan 3A 3AN 3A DSP FPGA families are designed to support a wide range of SPI serial Flash memory devices Table 4 2 page 89 lists the Xilinx tested PROMs that have in system programming support using the iMPACT software Many other SPI Flash PROMs are designed to be form fit and functionally equivalent and are listed in Table 4 5 page 91 The Xilinx ISE software generates compatible programming files but Xilinx has not tested these PROMs for complete compatibility Similarly the PROMs listed in Table 4 5 page 91 are not supported by the iMPACT in system programming software The criteria to select an SPI Flash PR
115. FPGA Part Number Frames in Bits XC3550A AN 367 1 184 XC3S200A AN 540 2 208 Spartan 3A 3AN FPGA XC3S400A AN 692 2 720 XC3S700A AN 844 3 232 XC3S1400A AN 996 4 768 XC3SD1800A 1 414 5 792 Spartan 3A DSP XC3SD3400A 1 718 6 816 XC3S100E 368 1 568 XC3S250E 577 2 336 Spartan 3E FPGA XC3S500E 729 3 104 XC3S1200E 958 4 000 XC3S1600E 1 186 5 024 Spartan 3 Generation Configuration User Guide www xilinx com 25 UG332 v1 2 May 23 2007 Chapter 1 Overview and Design Considerations XILINX Table 1 5 Spartan 3 Generation Configuration Data Frames Continued Spartan 3 Generation Number of Frame Length FPGA Family FPGA Part Number Frames in Bits XC3550 368 1 184 XC35200 615 1 696 XC35400 767 2 208 XC351000 995 3 232 Spartan 3 FPGA XC351500 1 223 4 384 XC352000 1451 5 280 XC354000 1 793 6 304 XC355000 1 945 6 816 CRC Next is the Cyclic Redundancy Check CRC value As the configuration data frames are loaded the FPGA calculates a CRC value After the configuration data frames are loaded the configuration bitstream issues a Check CRC instruction to the FPGA If the CRC value calculated by the FPGA does not match the expected CRC value in the bitstream then the FPGA pulls INIT B Low and aborts configuration Refer to CRC Checking during Configuration page 291 for additional information Bitstream Compression By default FPGA bitstreams are uncompressed However Spartan 3 Generati
116. FPGAs with different configurations then configure the FPGAs using a serial daisy chain as shown in Figure 1 3 page 18 Use Slave Serial mode M 2 0 lt 1 1 1 gt for all FPGAs in the daisy chain After the lead FPGA is filled with its configuration data the lead FPGA passes configuration data via its DOUT output pin to the next FPGA on the falling CCLK edge Table 8 1 Slave Serial Mode Connections Pin Name FPGA Direction Description During Configuration After Configuration HSWAP Input User I O Pull Up Control Drive at valid logic level User I O When Low during throughout configuration configuration enables pull up resistors in all I O pins to respective I O bank Veco input 0 Pull up during configuration 1 No pull ups M 2 0 Input Mode Select Selects the FPGA M2 1 M1 1 M0 1 User I O configuration mode See Sampled when INIT_B goes Design Considerations for the High HSWAP M 2 0 and VS 2 0 Pins page 58 DIN Input Data Input Serial data provided by host User I O FPGA captures data on rising CCLK edge CCLK Input Configuration Clock If CCLK External clock User I O PCB trace is long or has multiple connections terminate this output to maintain signal integrity See CCLK Design Considerations page 42 INIT_B Open drain Initialization Indicator Active Active during configuration If User I O If unused in bidirectional Low Goes Low at start of CRC error detected during the applicati
117. Figure 3 10 select the xcf Platform Flash PROM family from the drop list iMPACT Specify Xilinx PROM Device Auto Select PROM Enable Revisioning Number Enable Compression Select a PROM Position Part Name 0 xcfO4s Delete All Noa UG332_c3_05_111506 Figure 3 10 Select Platform Flash PROM 9 Select the desired Platform Flash part number The example in Figure 3 10 shows an XCF04 PROM which stores up to 4 Mbits or 524 288 bytes 10 Click Add This example assumes that the FPGA is connected to a single Platform Flash PROM However multiple Platform Flash PROMs can also be cascaded to create a larger memory If the application cascaded multiple PROMs then click the Add button to include additional PROMs 11 For a design that uses a single Platform Flash PROM the PROM also is located in position 0 If the application used multiple cascaded PROMs each PROM part name and position would be listed 12 Click Next Spartan 3 Generation Configuration User Guide www xilinx com 77 UG332 v1 2 May 23 2007 Chapter 3 Master Serial Mode XILINX 13 As shown in Figure 3 11 review that the settings are correct to format the Platform Flash PROM Click Finish to confirm the settings or Back to change the settings iMPACT File Generation Summary Eifel xi You have entered following information PROM Type Serial File Format mcs Fill Value FF PROM filename MyPlatformFlashPROM Nu
118. GA s DONE pin remains Low Using the Indirect Programming Method the programming cable connects to the FPGA s JTAG port The iMPACT software first programs the FPGA with a special design that performs the actual SPI PROM programming and uses the JTAG interface as a serial communications port During the process the FPGA s DONE output is High because the FPGA is configured with the programming application All pins that are not connected to the SPI Flash PROM or the JTAG interface have an internal pull up resistor to the VCCO voltage supply associated with the pin Table 4 12 Summary of SPI Flash PROM Programming Options Direct Method Indirect Method Detailed Instructions nsu wee ISE Version Required ISE 9 1i or later ee m dall Interface Cable Connection Directly to SPI PROM FPGA s JTAG Port DONE Pin Status during Low FPGA is ai with Programming special programming design Required PROG_B Control PROG B Low N A Status of non SPI Pins High impedance because Pulled en ees uds during Programming PROG B Low pull up resistor to associated a VCCO supply input Third Party Programmer Off board Programming Off board programming before board assembly using a third party programmer is likely the preferred method for high volume production Most Xilinx distributors offer programming services or can arrange for such services Check the PROM vendor s web site for a list of approved and qualified third p
119. Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Authentication Design Examples application then the FPGA application decides how to handle this unauthorized copy There are a variety of potential scenarios as described in Handling Failed Authentications page 287 In this example the PROM image fails because the FPGA application checks that a Blueberry is not Yellow Spartan 3A 3AN 3A DSP FPGA Configuration PROM FPGA Bitstream Blueberry UG332_c16_06_040107 Figure 15 8 Authentication Fails Using an Unauthorized Copy Spartan 3E FPGA Leveraging Security Features in Select Commodity Flash PROMs Only Spartan 3A 3AN 3A DSP FPGAs support the internal unique identifier feature The feature is not available on Spartan 3 or Spartan 3E FPGAs However Spartan 3E and Spartan 3 FPGAs support a similar authentication method using commodity Flash PROMs that have their own device ID values Table 15 8 provides example devices there are likely others The identifiers are only available is certain Flash PROM families and usually in the larger density members of the family The size of the identifier also varies by vendor and product family from 64 bits to 256 bytes Similarly some devices also have a user defined field that can be used to extend the size of the unique ID Table 15 8 Example Flash PROMs with Embedded Unique Identifiers Data Vendor Fami
120. Guide www xilinx com 83 UG332 v1 2 May 23 2007 Chapter 3 Master Serial Mode XILINX 84 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Chapter 4 Master SPI Mode The SPI serial Flash configuration mode is ideal for applications with the following attributes e SPI Flash PROMs are already being used in the system e The FPGA application needs to store data in nonvolatile memory or to access data from randomly accessible byte addressable nonvolatile memory e High volume consumer applications with a production run of about a few years or less For embedded applications with a five year or longer production lifetime also consider Master Serial mode using Xilinx Platform Flash which has a longer more stable supply lifetime than commodity Flash In Master SPI mode M 2 0 lt 0 0 1 gt the Spartan 3E or Spartan 3A 3AN 3A DSP FPGA configures itself from an attached industry standard SPI serial Flash PROM as illustrated in Figure 4 1 and Figure 4 2 The figure shows optional components in gray and designated NO LOAD The FPGA supplies the CCLK output clock from its internal oscillator and drives the clock input of the attached SPI Flash PROM Spartan 3 Generation Configuration User Guide www xilinx com 85 UG332 v1 2 May 23 2007 Chapter 4 Master SPI Mode XILINX Xilinx Cable Header SPI Flash Direct Programming 1 VC
121. I mode Define the M 2 0 configuration mode select setting for the next MultiBoot event Requires NEW MODE 1 001 Available options are identical to FPGA mode pin SPI settings M 2 0 shown in Table 2 1 page 34 BOOTMODE 53 Define the VS 2 0 SPI variant select setting for the next MultiBoot event This value is only used if BOOTVSEL 2 0 NEW MODE 1 and BOOTMODE 001 Available 111 options are identical to the SPI Flash variant select options VS 2 0 shown in Table 4 2 page 89 Generating a Spartan 3A 3AN 3A DSP MultiBoot PROM Image using iMPACT Note For Spartan 3AN see also Preparing an In System Flash Programming File page 205 TheiMPACT programming software provides a graphical step by step approach to create a MultiBoot PROM file Similar functionality is also available from the command line or via scripts using the PROMGen utility shown in Figure 14 10 Follow the steps outlined Spartan 3 Generation Configuration User Guide www xilinx com 263 UG332 v1 2 May 23 2007 Chapter 14 Reconfiguration and MultiBoot XILINX below to create a Spartan 3A 3AN 3A DSP MultiBoot PROM file using the iMPACT software Figure 14 11 page 264 shows the Spartan 3A 3AN 3A DSP MultiBoot design used in the following example 16Mbit SPI Flash Bitstream Spacing e Flash sector boundary alignment e Minimum spacing requirements if DCM_WAIT TRUE MultiBoot Bitstream 2
122. IEEE 1532 Configuration File Enable BitStream Compression Enable Debugging of Serial Mode BitStream Enable Cyclic Redundancy Checking CRC Other Bitgen Command Line Options Property display level Advanced Default 4 ug332_C1_05_091106 Figure 1 6 Bitstream Generator General Options 28 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Setting Bitstream Options Generating an FPGA Bitstream 3 Click General Options as shown in Figure 1 6 4 Tocompress the FPGA bitstream check Enable BitStream Compression 5 To enter specific bitstream generator command line options that are not already supported by the graphical interface enter the option strings in the space provided LX E Process Properties Category eneral f1ntian 1 Configuration Options arp Upto i Readback Options Configuration Rate Configuration Pin Program Configuration Pin Done Unused IOB Pins UserlD Code 8 Digit Hexadecimal 0x01 234567 Property display level Advanced Default 4 UG332_c1_06_091106 Figure 1 7 Bitstream Generator Configuration Options Click Configuration Options as shown in Figure 1 7 If using one of the Master configuration modes set the CCLK Configuration Rate frequency This setting is not used for Slave mode configuration The specif
123. If configuration process is complete the FPGA remains configured After configuration hold the PROG B input High Any Low going pulse on PROG B lasting 500 ns or longer restarts the configuration process The PROG B pin functionality is identical among all Spartan 3 Generation FPGAs Configuration Clock CCLK The configuration clock signal CCLK synchronizes the reading or writing of configuration data In Master modes CCLK is generated from an internal oscillator within the FPGA In Slave modes CCLK is an input driven by the external device providing the configuration data CCLK Differences between Spartan 3 Generation FPGA Families Table 2 8 summarizes the primary differences between the various Spartan 3 Generation FPGA families On Spartan 3 FPGAs the CCLK pin is a dedicated function while on the other families CCLK becomes available as a user programmable I O pin after configuration successfully completes The CCLK pin is an input only pin for the Slave Serial and Slave Parallel configuration modes 40 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX General Configuration Control Pins Table 2 8 CCLK Differences between Spartan 3 Generation FPGA Families Spartan 3A 3AN Spartan 3 Spartan 3E Spartan 3A DSP CCLK pin becomes full user I O No Yes Yes after configuration dedicated pin CCLK pin supply voltage VCCAUX VCCO 2 VCCO 2 CC
124. LK pin behavior after Pull up or pull configuration down resistor controlled by CclkPin UserI O UserI O bitstream option CCLK pin directionality during Output only for Master mode configuration I O I O improved signal integrity CCLK frequency options during 1 3 6 7 8 10 12 Master mode configuration 3 6 12 25 50 1 3 6 12 25 50 13 17 22 25 27 ConfigRate 33 44 50 100 CCLK frequency variation Fully Fully 50 of h ized h ized ConfigRate characterized characterized Fei aD Specified in Specified in data q y data sheet sheet In the Master configuration modes the FPGA internally generates the CCLK clock source As shown in Figure 2 2 there are slight differences in the CCLK circuitry between the Spartan 3 Spartan 3E FPGA families and the Spartan 3A 3AN 3A DSP families As shown inFigure 2 2a Spartan 3 3E FPGAs drive the internally generation CCLK signal to an output Like the configuration PROM connected to the FPGA the FPGA s internal configuration logic is clocked by the CCLK signal at the FPGA pin which simplifies the interface timing However any switching noise on the CCLK pin potentially also affects the FPGA Therefore treat CCLK as a full bidirectional I O pin for signal integrity analysis the FPGA uses the value at the pin to clock internal logic See CCLK Design Considerations page 42 As shown in Figure 2 2b CCLK is strictly an output on Spartan 3A 3AN 3A DSP FPGAs in the M
125. M must be ready for read operations at this time Spartan 3 Generation Configuration User Guide www xilinx com 97 UG332 v1 2 May 23 2007 Chapter 4 Master SPI Mode XILINX There are a few potential solutions if the 3 3V supply is last in the sequence and does not ramp fast enough or if the SPI Flash PROM cannot be ready when required by the FPGA e Change the power sequence order so that the 3 3V VCCO 2 is powered and valid before the FPGA s VCCINT or VCCAUX supply e Choose a different SPI Flash PROM family or vendor one with a faster power on timing specification For example while the Atmel AT45DBxxxB family has 20 ms power on requirement the compatible AT45DBxxxD family requires just 30 us e Delay the FPGA configuration process by holding either the FPGA s PROG B input or INIT B input Low Release the FPGA when the SPI Flash PROM is ready For example a simple R C delay circuit attached to the INIT B pin forces the FPGA to wait for a preselected amount of time Alternately a Power Good signal from the 3 3V supply or a system reset signal accomplishes the same purpose Use an open drain or open collector output when driving PROG B or INIT B Table 4 10 Spartan 3E and Spartan 3A 3A 3A DSP Power On Reset Timing and Thresholds Spartan 3A 3AN Symbol Description Spartan 3E Spartan 3A DSP Units VCCO 2 voltage at which Power On Reset POR circuit is released Vccoor P E Cn and Voy 0 4 to 1 0 0 8 to 2
126. May 23 2007 Chapter 4 Master SPI Mode XILINX command to force the SPI Flash into Deep Power Down mode Once the SPI Flash is in the Deep Power Down mode it ignores all commands except the Release from Deep Power Down Mode command The FPGA application must issue the Release from Deep Power Down Mode before accessing the SPI Flash Caution n a Spartan 3A 3AN 3A DSP MultiBoot application the SPI Flash memory must be released from Deep Power Down Mode before issuing the MultiBoot command Enter Deep Power Down Mode To enter Deep Power Down Mode the FPGA application must send the appropriate command to the SPI Flash Refer to the specific SPI Flash PROM data sheet for the specific command code and timing Once the SPI Flash PROM has entered Deep Power Down mode the PROM enters its lowest power state and the PROM ignores all other subsequent commands except the Release from Deep Power Down command Release from Deep Power Down Mode If the SPI Flash PROM is in Deep Power Down Mode then the FPGA application must issue a Release from Deep Power Down command before attempting any further communication Refer to the specific SPI Flash PROM data sheet for the specific command code and timing Spartan 3A 3AN 3A DSP MultiBoot Precautions Once the SPI Flash PROM is in Deep Power Down mode it remains in that state until the FPGA application issues a Release from Deep Power Down mode or until power is removed and reapplied to th
127. Multiboot Location C Data my_designs s3a_multiboot Browse Cancel UG332_c14_12_082006 C HEX J Swap Bits Checksum Fill Value 2 Hex Digits FF lt Back Figure 14 13 Select a PROM Supporting MultiBoot for Spartan 3A 3AN 3A DSP FPGAs Choose the Spartan3A MultiBoot method Select a PROM File Format The MCS format is supported by a variety of programmers but other options are available 7 Enter a PROM File Name Click Next 266 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Spartan 3A 3AN 3A DSP MultiBoot 9 As shown in Figure 14 14 choose whether to create a Spartan 3A 3AN 3A DSP MultiBoot image for SPI serial Flash or for parallel NOR Flash using BPI mode This example uses an SPI PROM iMPACT Spartan3A MultiBoot PROM C Using BPI Mode Direction UP only Downstream Daisy Chain Type Serial UG332 c14 13 082006 Figure 14 14 SPI or Parallel Flash PROMs are Supported 10 Click Next 11 Asshownin Figure 14 15 Select SPI PROM Density which is always specified in bits This example uses a 16 Mbit PROM Select SPI PROM Density bits Data Stream Enable Address Version Data Stream Hex DefaultorO v oa C Un 4 N UG332 c14 14 082006 Figure 14 15 Enter a PROM Density and Specify MultiBoot Image Start Locations 12 The initial MultiBoot image is
128. OM are listed below e Ideally the end application should use a Xilinx tested SPI PROM listed in Table 4 2 Table 4 3 page 89 lists the specific SPI Flash PROM part numbers tested and supported within iMPACT for in system programming using Xilinx programming cables 88 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Choosing a Compatible SPI Serial Flash Table 4 2 SPI Flash Memory Devices Officially Supported by Xilinx and Programmed Using iMPACT Read Command Fast Read Read Read Array 0x0B 0x03 OxE8 ilinx i SPI Flash IMPACT Unique FPGA VS 2 0 Setting Density bits Vendor Family Support ID 1 1 1 1 0 1 1 1 0 512K 1M 2M 4M 8M 16M 32M 64M 128M M25P STMicro M25PE M45PE AMDE D series Atmel ATSSDB B series Notes 1 Xilinx iMPACT Support indicates that Xilinx has physically tested compatibility for these SPI Flash memory devices and provides programming support in the iMPACT programming utility using Xilinx approved JTAG cables The iMPACT software generates programming information that is compatible with all the devices listed 2 Unique ID indicates that these SPI Flash memory device have factory programmed unique identifier bits useful for protecting FPGA applicatio
129. OM must be in x8 mode with BYTE 0 at power on or when the FPGA s PROG B pin is pulsed Low If required extend the BYTE setup time for a 3 3V PROM using an external 680 Q pull down resistor on the FPGA s LDC2 pin or by delaying assertion of the CSI B select input to the FPGA Daisy Chaining If the application requires multiple FPGAs with different configurations then configure the FPGAs using a daisy chain as shown in Figure 5 4 page 143 or Figure 5 5 page 145 e Parallel daisy chains from a BPI mode master FPGA are supported by both Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs e Serial daisy chains from a BPI mode master FPGA are only supported by Spartan 3A 3AN 3A DSP FPGAs To successfully configure a daisy chain the GTS cycle bitstream option must be set to a Startup phase after the DONE cycle setting for all FPGAs in the chain This is the software default setting Optionally set GTS cycle Done Parallel Daisy Chaining Both Spartan 3E and Spartan 3A 3AN 3A DSP FPGA families support parallel configuration daisy chains when the first device in the chain uses BPI mode As shown in Figure 5 4 all downstream FPGAs in the daisy chain use Slave Parallel mode M 2 0 lt 1 1 0 gt However if there are more than two FPGAs in the daisy chain then last FPGA in the chain can be from any recent Xilinx FPGA family that supports the Select MAP interface such as Virtex II Virtex II Pro Spartan 3 etc However all intermediate
130. OR page 226 Table 3 5 Maximum ConfigRate Settings Using Platform Flash Platform Flash Part 1 0 Voltage Spartan 3E Spartan 3A 3AN 3A DSP Number VCCO_2 Veco ConfigRate Setting ConfigRate Setting XCFO1S 3 3V or 2 5V 25 44 XCF025 XCFO04S 1 8V 12 N A XCFO08P 3 3V or 2 5V 33 XCF16P 25 XCF32P 1 8V N A Daisy Chained Configuration If the application requires multiple FPGAs each with different configurations then configure the FPGAs using a daisy chain as shown in Figure 3 4 page 71 Use Master Serial mode M 2 0 lt 0 0 0 gt for the FPGA connected to the Platform Flash PROM and Slave Serial mode M 2 0 lt 1 1 1 gt for all other FPGAs in the daisy chain After the master FPGA the FPGA on the left in the diagram finishes loading its configuration data from the Platform Flash the master device supplies data using its DOUT output pin to the next device in the daisy chain on the falling CCLK edge Also to successfully configure a daisy chain the GTS_cycle bitstream option must be set to a Startup phase after the DONE_cycle setting for all FPGAs in the chain This is the software default setting Optionally set GTS cycle Done Ganged or Broadside Configuration Daisy Chained Configuration is designed to load multiple FPGAs each with a different design and typically of different array size However some applications include multiple identical FPGAs all programmed with the same
131. P 1 8V VCCINT DO VCCO OE RESET XILINX Platform Flash XCFxx UG332 c3 16 112206 Table 3 2 Spartan 3 FPGA Connections to Platform Flash PROM Platform Flash FPGA Pin PROM Pin Comments DIN DO CCLK CLK Watch signal integrity on this trace See CCLK Design Considerations page 42 CCLK output powered by FPGA s VcCAUX supply INIT_B OE RESET FPGA resets PROM during initialization then enables the PROM s data out during configuration DONE CE FPGA enables PROM during configuration DONE output powered by FPGA s VccAux supply PROG B CF VCCO 4 Veco 1 8V 2 5V or 3 3V VCCJ PROM s JTAG output voltage If 3 3V then protect the FPGAs JTAG inputs with current limiting resistors gt 68Q 66 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Master Serial Mode Connections Master Serial Mode Connections Table 3 3 lists the various FPGA pins involved in Master Serial mode configuration Table 3 3 Master Serial Configuration Mode Connections FPGA After Pin Name Direction Description During Configuration Configuration Spartan 3E FPGA User I O Pull Up Control When Drive at valid logic level User I O HSWAP Low during configuration enables throughout configuration Spartan 3A pull up resistors in all I O pins to Spartan 3AN respective I O bank Vcco input Spartan 3A DSP 0 Pu
132. PGAs Table 2 16 shows the various Spartan 3E FPGA pins that are either borrowed or dedicated during configuration Table 2 16 Spartan 3E FPGAs Pin Behavior during Configuration Pin Behavior During Configuration Pin Name IO user I O IP input only TDI TMS TCK TDO Dedicated SPI BPI Pull Up Master Serial Parallel Slave Slave Supply Resistor Serial Flash Flash JTAG Serial Parallel I O Bank Seepinout S table Yes TDI TDI TDI TDI TDI TDI VCCAUX Yes TMS TMS TMS TMS TMS TMS VCCAUX Yes TCK TCK TCK TCK TCK TCK VCCAUX Yes TDO TDO TDO TDO TDO TDO VCCAUX Yes PROG B PROG B PROG B PROG B PROG B PROG B VCCAUX Yes DONE DONE DONE DONE DONE DONE Vecaux Yes HSWAP HSWAP HSWAP HSWAP HSWAP HSWAP 0 0 0 0 1 1 1 2 0 0 1 0 1 1 2 0 U 0 1 i CN 1 1 0 2 B CCLK CCLK CCLK CCLK CCLK 2 I O I O I O INPUT INPUT Yes INIT_B INIT_B INIT_B INIT_B INIT_B 2 CSO B CSO B CSO B 2 DOUT DOUT BUSY DOUT BUSY 2 MOSI CSI B CSI B 2 E D 7 1 D 7 1 2 DIN DIN DO DIN DO 2 RDWR B RDWR B 2 VS 2 0 Note 4 2 Note 4 A 23 17 2 A 16 0 1 LDC2 1 LDC1 1 LDCO 1 Z HDC 1 Notes 1 Gray shaded cells represent pins that are in a high impedance state Hi Z floating during configuration These pins have an optional internal pull up resistor to their respective Vcco supply pin that is active throughout configurati
133. PROM vendors use slightly different interfaces to support both x8 and x16 modes Some vendors Intel Micron some STMicroelectronics devices use a straightforward interface with pin naming that matches the FPGA connections However the PROM s A0 pin is wasted in x16 applications and a separate FPGA user I O pin is required for the D15 data line Fortunately the FPGA AO pin is still available as a user I O after configuration even though it connects to the Flash PROM Other vendors AMD Atmel Silicon Storage Technology Spansion and some STMicroelectronics devices use a pin efficient interface but change the function of one pin called IO15 A 1 depending if the PROM is in x8 or x16 mode Figure 5 3 illustrates this interface In x8 mode BYTE 0 controlled by the FPGA s LDC2 pin the Flash s IO15 A 1 pin becomes the least significant address line into the Flash memory The IO15 A 1 line selects a byte location The A0 address line which one might assume to be the least significant address line is actually the select line for word x16 locations After the FPGA configures successfully the FPGA application can optionally access the Flash memory using a 16 bit data interface The FPGA application drives BYTE 1 which switches the definition of the IO15 A 1 pin This pin then becomes the most significant data bit D15 because byte addressing is not required in x16 mode Check to see if the Flash PROM has a pin named IO15 A 1 or DQ15 A
134. Program a Spartan 3AN FPGA and Internal SPI Flash Memory Number of Configuration Bits FPGA Uncompressed In System Flash Memory XC3S50AN 437 312 1 Mbit XC3S200AN 1 196 128 4 Mbit XC3S400AN 1 886 560 4 Mbit XC3S700AN 2 732 640 8 Mbit XC3S1400AN 4 755 296 16 Mbit Mode Select Pins M 2 0 The Spartan 3AN FPGA family is generally designed to be pin and function compatible with the Spartan 3A 3A DSP FPGA families The Spartan 3AN FPGA family supports all the same configuration modes as the Spartan 3A 3A DSP FPGAs and adds the ability to configure from the internal In System Flash memory To configure from Internal Master SPI Flash mode the FPGA mode select pins must be set to M 2 0 lt 0 1 1 gt Furthermore the Vccayux supply must be 3 3V Variant Select Pins VS 2 0 For backward compatibility the Spartan 3AN FPGA monitors the variant select pins VS 2 0 to decide which read command to issue to the SPI Flash PROM Spartan 3AN FPGAs and the integrated SPI serial Flash support the variant select codes listed in Table 10 2 The choice of a variant select code potentially affects configuration performance For more details on the Spartan 3AN FPGA read commands see UG333 Spartan 3AN In System Flash User Guide Furthermore the VS 2 0 pins have dedicated pull up resistors that are active regardless of the PUDC_B pin whenever the M 2 0 mode select pins are set for Internal Master SPI mode 202
135. Programming using iMPACT Using iMPACT To program the attached and selected SPI PROM using the iMPACT software and the Indirect programming method follow the steps outlined below This specific example uses the Spartan 3A Starter Kit board which has an XC3S700A FPGA connected to an XCF04S Platform Flash PROM on the JTAG chain 1 Invoke iMPACT and select Configure devices using Boundary Scan JTAG as shown in Figure 4 21 E iMPACT Welcome to iMPACT Please select an action from the list below Automatically connect to a cable and identify Boundary Scan chain C Prepare a PROM File Prepare a System ACE File C Prepare a Boundary Scan File SVF v C Configure devices using Slave Serial mode UG332 c4 22 032807 Figure 4 21 Indirect Programming Method Uses JTAG 2 Select Finish Spartan 3 Generation Configuration User Guide www xilinx com 119 UG332 v1 2 May 23 2007 Chapter 4 Master SPI Mode XILINX 3 Select the FPGA bitstream file bit to be programmed into the FPGA as shown in Figure 4 22 This step is superfluous but required for iMPACT 9 1i This step will be eliminated starting in iMPACT 9 2i This file is not the special FPGA based SPI programming application z Assign New Configuration File Look in E C Data my designs switches leds t CX EE B File name top level bit File type All Design Files bit rbt nky ise
136. R B The RDWR B input controls whether the SelectMAP data pins are inputs or outputs e When RDWR B 0 the D 7 0 data pins are inputs writing to the FPGA e When RDWR B 1 the D 7 0 data pins are outputs reading from the FPGA 170 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Continuous SelectMAP Data Loading When writing configuration data to the FPGA the RDWR B pin must be Low When reading back configuration information from the FPGA the RDWR B pin must be High while CSI B is deasserted Changing the value of RDWR B while CSI B is Low triggers an ABORT if the FPGA receives a rising edge on CCLK see SelectMAP ABORT page 174 If Readback is not used RDWR B can be tied to ground or used for debugging with Select MAP ABORT The RDWR B signal is ignored while CSI B is High Read write control three state control of the D 7 0 data pins is asynchronous The FPGA actively drives SelectMAP data CCLK All activity on the SelectMAP data bus is synchronous to CCLK When writing configuration data to the FPGA RDWR B is Low and the FPGA samples the data on rising CCLK edges When RDWR B is set for read control RDWR B 1 Readback the FPGA updates the SelectM AP data pins on rising CCLK edges Configuration can be paused by pausing CCLK as outlined in Non Continuous SelectMAP Data Loading page 173 BUSY If the system writes data to or reads data fr
137. SPI serial Flash PROMs The SPI Flash memory devices that are tested and supported is indicated under the Xilinx iMPACT Support column in Table 4 3 page 89 Prepare Board for Programming Before attempting to program the SPI PROM complete the following steps 1 Ensure that the board is powered 2 Ensure that the FPGA pins that connect to the SPI Flash are high impedance Hi Z See Forcing FPGA SPI Bus Pins to High impedance During Programming page 107 3 Ensure that the programming cable is properly connected both the board and to the computer or workstation See Programmable Cable Connections page 106 Spartan 3 Generation Configuration User Guide www xilinx com 115 UG332 v1 2 May 23 2007 Chapter 4 Master SPI Mode XILINX Programming via iMPACT The following steps describe how to program the SPI PROM using the iMPACT software and a Xilinx programming cable 1 Click Direct SPI Configuration from within iMPACT as shown in Figure 4 16 iMPACT C Data my designs led crazy led crazy 700a ipf Direct SP s Fie Edit view Operations Options Output Debug Window Help IMPACT Modes UG332 c4 03 101006 Figure 4 16 iMPACT Supports Direct Programming for SPI Serial Flash Memories 2 Right click in the area indicated 3 Select Add SPI Device 4 Selecta previously formatted PROM file as shown in Figure 4 17 Add Device HEI Look in c led crazy e ex Fe My Recent D
138. Spartan 3 Generation Configuration User Guide Spartan 3A Spartan 3AN Spartan 3A DSP Spartan 3E and Spartan 3 FPGA Families with ISE 9 1i Design Examples UG332 v1 2 May 23 2007 XILINX XILINX Xilinx is disclosing this Document and Intellectual Property hereinafter the Design to you for use in the development of designs to operate on or interface with Xilinx FPGAs Except as stated herein none of the Design may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of the Design may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes Xilinx does not assume any liability arising out of the application or use of the Design nor does Xilinx convey any license under its patents copyrights or any rights of others You are responsible for obtaining any rights you may require for your use or implementation of the Design Xilinx reserves the right to make changes at any time to the Design as deemed desirable in the sole discretion of Xilinx Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made Xilinx will not assume any liability for the accuracy or correctness of an
139. Specifies the PROM size in kilobytes The PROM size must be a power TES of 2 and the default setting is 64 kilobytes Loads the bit file from the specified starting address in an upward u address direction This option must be specified immediately before the input bitstream file The example PROMGen command provided below generates an SPI formatted PROM file with the following characteristics 114 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Direct Programming using iMPACT Formatted for an SPI Flash PROM by specifying the spi option Formatted using the Intel MCS format by specifying the p mcs option The output filename is specified by the o lt promdata gt mcs option where promdata is a user specified file name Formatted for a 16Mbit SPI PROM by specifying the s 2048 option PROMGen specifies sizes in Kbytes The specified FPGA bitstream is loaded in the upward direction starting at address 0 by specifying the u 0 option The FPGA bitstream to be formatted for the PROM is specified as the last option lt inputfile gt bit where lt inputfile gt is the user specified file name used when generating the FPGA bitstream promgen spi p mcs o lt promdata gt mcs s 2048 u 0 lt inputfile gt bit Direct Programming using iMPACT Starting with version 8 2i the iMPACT programming software supports direct in system programming for
140. Star Topology Is Not Recommended ConfigRate Bitstream Option for CCLK For Master configuration mode the ConfigRate bitstream generator option defines the frequency of the internally generated CCLK oscillator The actual frequency is approximate due to the characteristics of the silicon oscillator and varies by up to 50 over the temperature and voltage range On Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs the resulting frequency for every ConfigRate setting is fully characterized and specified in the associated FPGA family data sheet At power on CCLK always starts operation at its lowest frequency Use the ConfigRate option to set the oscillator frequency to one of the other values shown in Table 2 8 Set this option graphically in ISE Project Navigator page 28 as shown in Step 7 in Figure 1 7 page 29 The FPGA does not start operating at the higher CCLK frequency until the ConfigRate control bits are loaded during the configuration process Persist Reserve CCLK As Part of SelectMAP Interface By default any clocks applied to CCLK after configuration are ignored unless the bitstream option Persist Yes is set which retains the configuration interface If Persist Yes then all clock edges are potentially active events depending on the other configuration control signals On Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs CCLK becomes a full featured user I O pin after configuration 44 www xilinx com Spartan 3 Generation Configurat
141. Table 11 2 Spartan 3 Generation Bitstream Generator BitGen Options Continued Pins Function Values Option Name Affected default Description Persist SelectMAP No Default All Slave mode configuration pins are available as interface pins user I O after configuration Slave mode Thi red adana al Configuration Yes is option is require or Readbac an partia reconfiguration using the SelectMAP interface The SelectMAP interface pins see SelectMAP Data Loading page 170 are reserved after configuration and are not available as user I O Security JTAG None Default Readback and limited partial reconfiguration are SelectMAP available via the JTAG port or via the SelectMAP interface if Readback Partial Persist Yes fi ti DOR QUITE Levell See Basic FPGA Hardware Level Security Options 273 Level2 page Level3 Compress FPGA bitstream No Default Bitstream is not compressed and will be the size size shown in Table 1 4 Yes Possibly compress the FPGA bitstream by finding redundant configuration frame and using multi frame write command during configuration There is no guarantee of the amount of compression Sparse designs or designs that do not use block RAM see the most benefit See Bitstream Format page 24 Spartan 3 FPGA Family Configuration Pin Controls see Table 2 9 page 47 and Table 2 11 page 48 HswapenPin Spartan 3 FPGA Pullup De
142. These resistors can be controlled after the Spartan 3 FPGA successfully configures using the bitstream generator options M2Pin M1Pin and MOPin These options define whether a pull up resistor pull down resistor or no resistor is present on its respective mode pin MO M1 or M2 By default all three pins will have an internal pull up resistor to VccAUx Defining M 2 0 after Configuration for Minimum Power Consumption During configuration the M 2 0 pin may be tied directly to power or ground tied High or Low using external resistors or actively driven by an external component To further minimize power consumption adjust the post configuration behavior of the M 2 0 pins so that they match the required configuration setting shown in Table 2 1 page 34 either by defining their value in the FPGA application or by adjusting the associated bitstream options Essentially avoid any unnecessary current paths through pull up or pull down resistors Spartan 3 Generation Configuration User Guide www xilinx com 35 UG332 v1 2 May 23 2007 Chapter 2 Configuration Pins and Behavior during Configuration XILINX Table 2 3 summarizes the default post configuration behavior on both Spartan 3 and Spartan 3E 3A 3AN FPGA families which have slightly different functionality Table 2 3 Default Post Configuration Behavior of M 2 0 Pin Spartan 3 FPGAs Spartan 3E Spartan 3A 3AN 3A DSP FPGAs After configuration the M 2 0 After configu
143. UG332 v1 2 May 23 2007 XILINX Programming an FPGA Using JTAG Mode Pin Considerations when Programming a Spartan 3AN FPGA via JTAG using iMPACT When iMPACT 9 1i configures the Spartan 3AN FPGAs it first programs the internal SPI Flash PROM After this configuration is complete a reboot is triggered and the FPGA configures itself from the internal SPI PROM When the reboot is triggered the mode pins M 2 0 are sampled For the configuration to complete successfully the FPGA mode select pins must be set to M 2 0 lt 0 1 1 gt which is the Internal Master SPI mode If you are configuring from iMPACT and your mode pins are set to JTAG mode M 2 0 lt 1 0 1 gt configuration of the FPGA will not complete To finish configuration of the FPGA you can simply change the mode pins to Internal Master SPI mode and pulse the PROG pin to trigger configuration or reconfigure through iMPACT In iMPACT 9 2i and later you have the option to either configure the FPGA directly through JTAG mode or to program the Internal SPI PROM and then configure through Internal Master SPI mode Spartan 3 Generation Configuration User Guide www xilinx com 199 UG332 v1 2 May 23 2007 Chapter 9 JTAG Configuration Mode and Boundary Scan XILINX 200 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Chapter 10 Internal Master SPI Mode The Internal Master SPI Flash mode is only a
144. UG332 v1 2 May 23 2007 Chapter 1 Overview and Design Considerations XILINX Will the FPGA load its configuration data itself from external or internal memory or will an external processor or microcontroller download the configuration data Spartan 3 Generation FPGAs are designed for maximum flexibility The FPGA either automatically loads itself with configuration data like a processor or alternatively another external intelligent device like a processor or microcontroller can download the configuration data It is your choice and Table 1 2 summarizes the available options The self loading FPGA configuration modes generically called Master modes are available with either a serial or byte wide data path as shown in Figure 1 1 The Master modes leverage various types of nonvolatile memories to store the FPGA s configuration information as shown in Table 1 1 In Master mode the FPGA s configuration bitstream typically resides in nonvolatile memory on the same board generally external to the FPGA The FPGA internally generates a configuration clock signal called CCLK and the FPGA controls the configuration process Spartan 3AN FPGAs optionally configure from internal In System Flash ISF memory as shown in Figure 1 1c In this mode the configuration memory and the control and data signals are inside the package Spartan 3AN FPGAs also optionally support all the other Spartan 3A FPGA configuration modes as well 12 www
145. VCCINT 1 2V Supply Tor VCCAUX ES 2 5V Supply 9 Vcco Bank 2 PROG_B Input INIT_B Open Drain NNNNN Z pe Ticck CCLK te Output T T MINIT INITM M 2 0 VS 2 0 Input Pins Sampled UG332 c2 13 111506 Figure 12 4 FPGA Power Up Timing Waveforms Master Modes Spartan 3 Generation Configuration User Guide www xilinx com 227 UG332 v1 2 May 23 2007 Chapter 12 Sequence of Events XILINX Table 12 2 lists and describes the power up timing specifications shown in Figure 12 4 Refer to the associated FPGA data sheet for any unlisted values Table 12 2 FPGA Power Up Timing Specifications Symbol Description Family Value Units TPOR Power On Reset delay from when all three Spartan 3 5to7 supplies reach their required threshold voltage until the FPGA completes clearing its configuration memory and INIT_B goes High Spartan 3A 18 Spartan 3E 5to7 ms Tp Delay form when PROG B is released High Spartan 3 2to3 until the FPGA completes clearing its configuration memory and INIT B goes High Spartan 3E 0 5to2 ms Spartan 3A 0 5to2 TpPROG Minimum PROG B pulse width required to Spartan 3 300 reset FPGA ns Spartan 3E 500 Spartan 3A Ticck For Master configuration modes the time from the rising edge of INIT B until CCLK output All 0 5 to 4 us begins toggling Tm n r Setup time on M 2 0 mode select pins and in Master SPI mode th
146. VS 2 0 Table 2 21 Pull up or Pull down Values for HSWAP M 2 0 and VS 2 0 1 0 Pull up Resistors Required Resistor Value to Define Logic Level on HSWAP M 2 0 or VS 2 0 HSWAP Value during Configuration High Low 0 Enabled Pulled High via an internal Pulled Low using an appropriately pull up resistor to the associated sized pull down resistor to GND as Vcco supply No external shown in Table 2 14 page 49 pull up resistor is necessary 1 Disabled Pulled High using a 3 3 to 4 7 kQ Pulled Low using a 3 3 to 4 7 kQ resistor resistor to the associated Vcco to the associated Vcco supply supply Dual Purpose Pins Become User I O All dual purpose I O pins that are borrowed during configuration become full function I O pins after configuration successfully completes Figure 2 6 shows stylized waveforms for some of the configuration control signals On Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs the M 2 0 mode pins the VS 2 0 pin in Master SPI mode the CCLK pin and the HSWAP or PUDC_B pin are borrowed during configuration After configuration completes the pins become available as user I O pins All dual purpose I O pins except for CCLK become available to the FPGA application immediately following the GTS cycle during the FPGA Startup sequence The GTS cycle timing is controlled by the GTS_cycle bitstream option The CCLK configuration clock does not become a user defined I O until after the
147. X Table 1 2 Spartan 3 Generation Configuration Options Master Master Internal Slave Serial SPI BPI Parallel Master SPI Parallel Slave Serial JTAG Spartan 3 All Spartan 3A Spartan 3A Spartan 3 Spartan 3AN All All All Generation Spartan 3AN Spartan 3AN only only F ili Spartan 3A DSP Spartan 3A DSP ammes Spartan 3E Spartan 3E lt 0 0 0 gt lt 0 0 1 gt lt 0 1 0 gt Up 0 1 1 01 1 lt 1 1 0 gt lt 1 1 1 gt lt 1 0 1 gt M 2 0 mode Spartan de in settings oniy p lt 0 1 1 gt Dow n Data width Serial Serial Byte wide Byte wide Serial Byte wide Serial Serial Xilinx Commodity Commodity Xilinx Internal In Any source Any source Any source Platform SPI serial parallel NOR parallel System via micro via micro via micro Configuration Flash Flash Flash or Xilinx Platform Flash ISF controller controller controller memory parallel Flash etc memory CPU Xilinx CPU Xilinx CPU System source Platform parallel Platform ACE CF Flash Platform Flash etc etc Flash etc Internal oscillator External clock signal External Clock source applied on CCLK pin clock on TCK pin Total I O pins borrowed 8 13 46 12 7 21 8 0 during configuration Configuration Slave Slave Serial Slave Parallel Slave Not Slave Slave Serial JTAG mode for Serial Spartan Serial Supported Parallel or downstream 3A 3AN 3A Memory daisy chai
148. XC3S400AN ASM484BGD XC3S700AN SM484BGD BPWin V4 66 0 and later ASM676BG XC381400AN SM676BG BPWin V4 66 0 and later Spartan 3 Generation Configuration User Guide www xilinx com 215 UG332 v1 2 May 23 2007 Chapter 10 Internal Master SPI Mode XILINX 216 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Chapter 11 Configuration Bitstream Generator BitGen Settings Various Spartan 3 Generation FPGA functions are controlled by individual settings in the configuration bitstream image These values are specified when creating the bitstream image with the Bitstream Generator BitGen software Table 11 2 page 218 lists the more commonly used bitstream generator options for Spartan 3 Generation FPGAs Each of these options can be specified on the command line with the following format bitgen g option value infile The option name and value are separated by a colon with no spaces For more information and a complete listing of all options see the BitGen chapter in the following document e ISE9 1i Development System Reference Guide http toolbox xilinx com docsan xilinx9 books docs dev dev pdf For a quick summary of available options for particular FPGA family type the command shown in Table 11 1 in a DOS box or command window Table 11 1 Command Line to Review Bitstream Generator Options per Family FPGA Fami
149. Yee RE Ie eis eae 35 Defining M 2 0 after Configuration for Minimum Power Consumption 35 DONE Pit eere PI ERG Ou sop gos e ce ra e eee der ra 36 Associated Bitstream Generator BitGen Options 6 6 6 6c eee eee eee 36 DONE Synchronizes Multiple FPGAs in a Daisy Chain or Broadside Ganged Configuration38 Program or Reset FPGA PROG B 6 n 39 Configuration Clock CCLK i ies shew Ue Odo oe atid aie ere ee sees 40 CCLK Differences between Spartan 3 Generation FPGA Families 40 CCLK Design Considerations eise 42 ConfigRate Bitstream Option for CCLK 2 6 tt nen 44 Persist Reserve CCLK As Part of SelectMAP Interface 0 cc cece eee eens 44 Spartan 3A 3AN 3A DSP and Spartan 3E FPGA Families esses 45 Spartan 3 FEGA Family ed ber eode enirn b PR ae be Rees 45 Initializing Configuration Memory Configuration Error INIT B 45 After Configuration 52 pase tha Vp EE bead hee beta Ooo eke als 45 Spartan 3A 3AN 3A DSP Post Configuration CRC 20 6 46 Spartan 3A 3AN 3A DSP and Spartan 3E FPGA Families lesse 46 Spartan 3 FPGA Family cese cece ei aeeie ienie Re ba aed eee uod ew ee 46 Pull Up Resistors During Configuration 0600 e cece eee 46 Pins with Dedicated Pull Up Resistors during Configuration 05 46 Pins with Optional Pull Up Resistors during Configuration 05 48 FPGA Pull Up Resistor Values
150. Yes Spartan 3E BPI Output PROM Chip Enable Connect to parallel User I O If the Spartan 3A PROM chip select FPGA does not access Spartan 3AN input CS FPGA the PROM after Spartan 3A DSP drives this signal Low configuration drive FPGA throughout this pin High to LDCO configuration deselect the PROM A 23 0 D 7 0 LDC 2 1 and HDC then become available as user I O Spartan 3E BPI Output PROM Output Enable Connect to the parallel User I O Spartan 3A PROM output enable Spartan 3AN input OE The FPGA Spartan 3A DSP drives this signal Low FPGA throughout LDC1 configuration Spartan 3E BPI Output PROM Write Enable Connect to parallel User I O Spartan 3A PROM write enable input WE FPGA drives this signal High throughout configuration 52 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Pin Description Table 2 15 Spartan 3 Generation Configuration Pins Associated Modes and Function Continued Config FPGA Pin Name Mode s Direction Description During Configuration After Configuration Spartan 3E BPI Output PROM Byte Mode This signal is not used User I O Drive this Spartan 3A for x8 PROMs For pin High after Spartan 3AN PROMs with a x8 x16 configuration to use a Spartan 3A DSP data width control x8 x16 PROM in x16 FPGA connect to PROM byte mode LDC2 mode input BYTE Spartan 3E BPI Output Parallel PROM Addres
151. a Master SPI Configuration 204 ConfigRate CCLK Frequency sseee een 204 StartupClk CCL usce RR CER niet aide ss Pu Had Eh bie rbi aged ed 204 DriveDone Actively Drive DONE Pin 0 0 06 cece e 204 Programming a Spartan 3AN FPGA Using JTAG sess 204 Preparing an In System Flash Programming File uuuuuuuue 205 IMPA CI CPPT C elec dt teas gua Kates MI 205 PROM Cp C0 5 cesses Bicester tee a uence cpap ate ear gee led hie Meas Mets ED 212 Programming Spartan 3AN FPGAs Using iMPACT 213 Third Party Programmer Suppott 0 0 000 0 cece cece eee 213 BPM Microsystems ii dde sedet eve roe ere Se bp der dx o eau eee Mee 213 Production Hardware Programming Solutions 0 0 e eee eee ee eee 213 Programming Socket Modules and Software nuun unn e ccc cece eee 215 Spartan 3 Generation Configuration User Guide www xilinx com 7 UG332 v1 2 May 23 2007 XILINX Chapter 11 Configuration Bitstream Generator BitGen Settings Chapter 12 Sequence of Events Overview solu bRPeCH Seb RE RDMPeI pde tinidesediie eee dd EN LR D decies 225 Setup for Configuration Steps 1 3 00 225 Wake from Reset cceli eese rre er eee eL HIR Ob eee eee e n 225 Power On Reset DOR eue od redet cer cech dea eee ded one aceto ir dota 226 PROG BPin 4i 69 re e ek d e a ee EP E Ie Rays 227 Power Up Timing siei ieena e me aeria
152. a back data from the FPGA then the RDWR B signal can also be removed from the interface but must remain Low during configuration After configuration all of the interface pins except DONE and PROG B are available as user I Os Alternatively the bidirectional SelectMAP configuration interface is available after configuration To continue using SelectMAP mode set the Persist Yes bitstream generator option The external host can then read and verify configuration data The Slave Parallel mode is also used with BPI mode to create multi FPGA daisy chains The lead FPGA is set for BPI mode configuration all the downstream daisy chain FPGAs are set for Slave Parallel configuration as highlighted in Figure 5 4 page 143 Spartan 3 Generation Configuration User Guide www xilinx com 163 UG332 v1 2 May 23 2007 Chapter 7 Slave Parallel SelectMAP Mode XILINX 1 2V VCCINT Slave HSWAP Parallel P PUDC_B E VCCO 0 Mode Qv Spartan 3A 3 4 Spartan 3AN and Spartan 3A DSP iwi M1 FPGAs have internal p lo Mo XILINX VCC pu kup resistors Spartan 3E 3A 3AN 3A DSP e D 2 D BUSY BUSY sec CSL B RDWR B INIT B e Internal memory CLOCK e Disk drive NOTE Over network PROG B Only Spartan 3A Over RF link DONE VCCAUX cand partan INIT B FPGAs support GND VCCAUX 3 3V e Microcontroller nq PROG B DONE e Processor Tester GND e Computer PROGRAM RE ae au 2 25V Assumes VCCAUX 2 5V Intell
153. able 2 1 The logic levels applied to the mode pins is sampled on the rising edge of INIT B immediately after the FPGA completes initializing its internal configuration memory Table 2 1 Mode Pin Settings and Associated FPGA Configuration Mode by Family FPGA Family Spartan 3A M 2 0 Spartan 3 Spartan 3E Spartan 3A DSP Spartan 3AN lt 0 0 0 gt Master Serial Platform Flash Mode lt 0 0 1 gt Reserved Master SPI Mode lt 0 1 0 gt Reserved BPI Up lt 0 1 1 gt Master Parallel BPI Down Reserved Da lt 1 0 0 gt Reserved lt 1 0 1 gt JTAG Mode lt 1 1 0 gt Slave Parallel Mode lt 1 1 1 gt Slave Serial Mode M 2 0 Functional Differences between Spartan 3 Generation Families Table 2 2 summarizes the slight differences in functionality between the Spartan 3 Generation families Table 2 2 M 2 0 Mode Pin Differences between Spartan 3 Generation FPGAs Spartan Spataw3 SpartanSE 3A 3AN 3A DSP FPGA Available as possible user I O pin after No Yes Yes configuration Dedicated internal pull up resistor Yes No Yes during configuration Mechanism to define post configuration M2Pin behavior M1Pin MOPin User I O User I O bitstream options Supply voltage VCCAUX VCCO 2 VCCO 2 Same voltage as other pins in the Only when configuration interface interface is at Yes Yes 2 5V 34 www xilinx com Spartan 3 Generation Configuration User Guide UG
154. age 46 for additional information Does the application target a specific FPGA density or should it support migrating to other FPGA densities in the same package footprint The package footprint and pinouts for Xilinx Spartan 3 Generation FPGAs are designed to allow migration between different densities within a specific family For example three different Spartan 3E FPGAs support the identical package footprint when using the 320 ball fine pitch ball grid array package FG320 As shown in Table 1 4 the smallest of devices the XC3S500E requires approximately 2 2 Mbits for configuration The largest of these devices the XC351600E requires 5 7 Mbits for configuration Likewise an FPGA application may store other nonvolatile data in the Flash memory requiring a larger storage device To support design migration between device densities allow sufficient configuration memory to cover the largest device in the targeted package In the example provided above allow up to 5 7 Mbits for configuration This allows the application to use any Spartan 3E FPGA available in the FG320 package In downloaded applications simply reserve enough space in memory for the largest anticipated uncompressed FPGA bitstream In self loaded applications use a PROM footprint and the associated FPGA configuration mode to facilitate easy migration Table 1 3 provides example migration options using different FPGA configuration modes different PROM families and
155. ailable any time the FPGA is powered and regardless of the mode pin settings However when the FPGA mode pins are set for JTAG mode M 2 0 lt 1 0 1 gt the FPGA waits to be configured via the JTAG port after a power on event or after PROG_B is pulsed Low Selecting the JTAG mode simply disables the other configuration modes No other pins are required as part of the configuration interface See Mode Pin Considerations when Programming a Spartan 3AN FPGA via JTAG using iMPACT for special mode pin requirements Figure 9 1 illustrates a JTAG only configuration interface The figure shows optional components in gray The JTAG interface is easily cascaded to any number of FPGAs by connecting the TDO output of one device to the TDI input of the next device in the chain The TDO output of the last device in the chain loops back to the port connector 1 2V 1 2V VCCO 0 VCCO 2 VCCO 2 ses o M x XILINX x XILINX Spartan 3E 3A FPGA Spartan 3E 3A FPGA VCCAUX TCK TDI PROG_B DONE GND Dedicated internal pull up resistor UG332_c9_01_120106 Figure 9 1 JTAG Configuration Interface Spartan 3 Generation Configuration User Guide www xilinx com 183 UG332 v1 2 May 23 2007 Chapter 9 JTAG Configuration Mode and Boundary Scan XILINX JTAG Cable Voltage Compatibility The FPGA s JTAG interface is powered by the Vccayx supply All of the user I Os are separately powered by their
156. ains 148 Preparing an Parallel NOR Flash PROM File 0005 148 IPAE rre rE dt E Puce euet erus eas Rutas wave ade elenco cett aeu 148 In System Programming Support 00 060 153 Power On Precautions if 3 3V Supply is Last in Sequence 154 Spartan 3A 3AN 3A DSP and Configuration Watchdog Timer 155 Byte Peripheral Interface BPI Timing ususuuusssessessse 156 Limitations when Reprogramming via JTAG if FPGA Set for BPI Configuration 158 Spartan 3E BPI Mode Interaction with Right and Bottom Edge Global Clock Inputs 158 Chapter 6 Master Parallel Mode Chapter 7 Slave Parallel SelectMAP Mode Voltage Compatibility esce Cep Ra rat ede ese rte d tcn cid p eod suena 168 Daisy Chains cien kk a Cked ICE Ae OCC e DURO AC Ec An ed er 168 Spartan 3E Spartan 3A 3AN 3A DSP Slave Parallel Daisy Chains 169 Slave Parallel Daisy Chains Using Any Modern Xilinx FPGA Family 169 Select MAP Data Loadinp i ioesshtor eb rir b dread rd P a oa eod 170 aug CU 170 RDWR B srpu ek RR RE XI X EE RE X EXE RE RES EGG eG rx ie da 170 CCLK eR ERR RESURROSUERERET ARE RU PER UC REL YR ERAR EREE EE CERE nha 171 BUSY icol ike kwe ke Re Rr ER ERAN RA ERE CERT be eR epe eria 171 Continuous SelectMAP Data Loading suuuuuussssssssesesee 171 Non Continuous SelectMAP Data Loading 0 000005 173 Deassertng CSI B irs
157. al FPGA configuration bitstream is always loaded at address 0 from the attached configuration PROM regardless of mode For MultiBoot operations there are two methods for the FPGA application to load the address of the next MultiBoot configuration image 1 Fixed Known Address If the next address is predefined and known at design time the next MultiBoot address can be preloaded within the current FPGA bitstream using the next config addr bitstream generator BitGen option The parallel NOR Flash address or the SPI serial Flash address is specified as an seven character hexadecimal string next config addr 0x0000000 Spartan 3 Generation Configuration User Guide www xilinx com 257 UG332 v1 2 May 23 2007 Chapter 14 Reconfiguration and MultiBoot XILINX 2 Variable or Calculated Address The FPGA application itself can supply the address of the next MultiBoot image by writing a command sequence to the FPGA s ICAP_SPARTANSA design primitive Required Data Spacing between MultiBoot Images Spartan 3A 3AN 3A DSP MultiBoot addressing is flexible enough to allow a bitstream to begin at any byte boundary However there are a few practical limitations based on specific application requirements Flash Sector Block or Page Boundaries Spartan 3A 3AN 3A DSP FPGAs load MultiBoot configuration images from an external Flash PROM All Flash PROMs have an internal memory architecture that arranges the memory into sectors blocks
158. al Flash Table 4 5 Other SPI Flash Memory Devices With Data Sheet Compatibility Unverified by Xilinx Unsupported in iMPACT Read Command Fast Read Read Read Array 0x0B 0x03 0xE8 Xilinx SPI Flash FPGA VS 2 0 Settin D iMPACT Unique 2 0 ing ensity bits Vendor Family Support ID 1 1 1 1 0 1 1 1 0 512K 1M 2M 4M 8M 16M 32M 64M 128M AT26 Atmel AT25 Spansion AMD S25FL Fujitsu NX25P Winbond WOSP NexFlash W25X Intel S33 SST25L SST SST25V Macronix MX25 Chingis PMC Pm25 AMIC A25L Eon EN25 Notes 1 Compatibility based on publicly available data sheets as of October 2006 2 Unique ID indicates that these SPI Flash memory device have factory programmed unique identifier bits useful for protecting FPGA applications or IP cores Spartan 3 Generation Configuration User Guide www xilinx com 91 UG332 v1 2 May 23 2007 Chapter 4 Master SPI Mode XILINX SPI Flash PROM Density Requirements Table 4 6 shows the smallest usable SPI Flash PROM to program a single Spartan 3A 3AN 3A DSP orSpartan 3E FPGA Commercially available SPI Flash PROMs range in density from 1 Mbit to 128 Mbits A multiple FPGA daisy chained application requires a SPI Flash PROM
159. al Uses of Authentication and Device ID 4 289 Protecting Intellectual Property IP sssssseessesessseeeeee 289 Spartan 3 Generation Configuration User Guide www xilinx com 9 UG332 v1 2 May 23 2007 XILINX Code and Data Security i cs esent eee be e Hee eee eren I RS RA he 289 U S Legal Protection of FPGA Configuration Bitstream Programs 289 Chapter 16 Configuration CRC CRC Checking during Configuration 0 00 e cece eee 291 Spartan 3 and Spartan 3E Configuration CRC Errors 00000 291 Configuration CRC Enabled by Default 0 0 0 66 c cece nee 291 Possible CRC Escapes a4 sveses eh Rr erem traa iandien eaa hoes rd e weed 291 Spartan 3A 3AN 3A DSP Configuration CRC Errors and Configuration Watchdog Timer292 Robust CMOS Configuration Latches CCLs 0 00 0 008 292 Post Configuration CRC Spartan 3A 3AN 3A DSP Only 292 OVERVICW sets detail Vae oa Ea EEG E bae Sade aed 293 Continuous CRC Checking Until Configuration JTAG or Suspend Event 294 Clock Source oc 1 9 4o dne eere deed e EO Cade Cae eee ew 294 CRC Checking Time isda siaii aiee eskei wine epo de ath agate katona 294 Behavior when CRC Error Occurs ssssseee en 295 Verifying CRC Error Behavior 6 0 ccc cc nnn 295 Preparing an Application to Use the Post Configuration CRC Feature 295 Example User Constraints Fil
160. al clock is available on the board it is also possible to configure the FPGA in a Slave mode while still using an attached nonvolatile memory Spartan 3 Generation Configuration User Guide www xilinx com 19 UG332 v1 2 May 23 2007 Chapter 1 Overview and Design Considerations XILINX Will the FPGA or FPGAs be loaded with a single configuration image or loaded with multiple images In most FPGA applications the FPGA is loaded only when the system is powered on However some applications reload the FPGA multiple times while the system is operating with different FPGA bitstreams for different functions For example the FPGA may be loaded with one bitstream to implement a power on self test followed by a second bitstream with the final application In many test equipment applications the FPGA is loaded with different bitstreams to execute hardware assisted tests In this way one smaller FPGA can implement the equivalent functionality of a larger ASIC or gate array device The downloaded or Slave configuration modes easily support reloading the FPGA with multiple images However this is also possible on Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs using the MultiBoot feature See Chapter 14 Reconfiguration and MultiBoot for more information What I O voltages are required in the end application The chosen FPGA configuration mode places some constraints on the FPGA application specifically the I O voltage allowed on t
161. and EXTEST commands When using these commands it is possible to drive and sample the pins of the FPGA with the JTAG chain and thereby stimulate the pins of the SPI memory via the associated FPGA pins and the traces routed on the PCB This method shown in Figure 4 8 is supported by many third party JTAG tool vendors However this method is often much slower than the Direct SPI In System Programming technique XILINX MeN SPI Flash Spartan 3 SCLK CCLK Generation Pene FPGA UG332 c4 xx 080906 Figure 4 8 Using FPGA s JTAG Test Chain to Program Attached SPI Flash The advantage to this approach is that it requires minimal wiring for in system programming and that the SPI Flash PROM can be programmed during other JTAG based board test operations For easier development Xilinx recommends including the JTAG programming cable socket shown in Figure 4 1 page 86 and Figure 4 2 page 87 The FPGA configuration can be downloaded directly into the FPGA for development purposes without requiring that the SPI Flash PROM be programmed For more information on the JTAG interface see Chapter 9 JTAG Configuration Mode and Boundary Scan especially Programming Cables and Headers page 193 Generating the Bitstream for a Master SPI Configuration To create the FPGA bitstream for a Master SPI configuration follow the steps outlined in Setting Bitstream Options Generating an FPGA Bitstream page 27 For an FPGA configure
162. and block RAM are automatically excluded from the CRC calculation Any write operations to these locations would otherwise result in a different calculated CRC value and a subsequent CRC error Similarly the look up tables LUTs within the SLICEM logic slices in each Spartan 3 Generation Configuration User Guide www xilinx com 293 UG332 v1 2 May 23 2007 Chapter 16 Configuration CRC XILINX Configurable Logic Block CLB also potentially contain writable functions such as distributed RAM or SRL16 shift registers Consequently by default all LUTs in all SLICEM logic slices are excluded from the calculated CRC value However if all the LUTs in the FPGA application are only used for logic that is there is no distributed RAM or SRL16 shift registers in the design then the SLICEM LUTSs can be included in the calculation by setting the glutmask No bitstream option See the ISE project summary report to determine if the design uses any distributed RAM or SRL16 shift registers Block RAM is excluded from the CRC calculation because a change in the RAM content would have a subsequent change in the CRC result Byte half word or word level changes are easily detected using the available parity bits provided as part of the block RAM function See Techniques to Check Distributed and Block RAM Contents page 298 for more information Continuous CRC Checking Until Configuration JTAG or Suspend Event The CRC check
163. artan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX CRC Checking during Configuration Chapter 16 Configuration CRC All Spartan 3 Generation FPGAs have an embedded 32 bit cyclic redundancy checker CRC circuit designed to flag errors when loading the configuration bitstream The configuration CRC circuit is always active during configuration unless specifically disabled in the configuration bitstream Spartan 3A 3AN 3A DSP FPGAs also optionally allow the CRC circuit to continue operating after configuration CRC Checking during Configuration As the configuration data frames are loaded the FPGA calculates a Cyclic Redundancy Check CRC value from the configuration data packets After all the configuration data frames are loaded the configuration bitstream issues a Check CRC command to the FPGA followed by an expected CRC value If the CRC check values match the FPGA continues the configuration process by progressing to the Startup phase If the CRC value does not match then there are slightly different behaviors between the various Spartan 3 Generation product families as described below Spartan 3 and Spartan 3E Configuration CRC Errors If the CRC value calculated by the FPGA does not match the expected CRC value in the bitstream the FPGA drives the INIT_B pin Low and aborts configuration When a CRC error occurs the CCLK output goes to the high impedance state Hi Z unless the HSWAP or HSWAP_EN p
164. arty device programmers See Preparing an SPI PROM File page 110 to properly format the programming file Direct SPI In System Programming For systems requiring in system programming support there are different options for production and prototyping phases For production programming some third party PROM programmers utilize a socket adapter with attached wires to program the SPI flash memory in system For prototype programming the Xilinx iMPACT software provides direct in system programming support for limited set of STMicro and Atmel SPI Flash memories Requirements for iMPACT Direct Programming Support The following are required to successfully perform in system programing on the attached SPI serial Flash PROM e A Xilinx programming cable Spartan 3 Generation Configuration User Guide www xilinx com 105 UG332 v1 2 May 23 2007 Chapter 4 Master SPI Mode XILINX Platform Cable USB www xilinx com xlnx xebiz designResources ip product details jsp key HW USB G Parallel Cable IV www xilinx com xlInx xebiz designResources ip product details jsp key HW PC4 MultiPRO Desktop Tool www xilinx com xlnx xebiz designResources ip product details jsp key HW MULTIPRO e Acompatible cable connector on board e Properly installed Xilinx ISE 8 2i software or later Programmable Cable Connections All modern Xilinx programming cables use a standard 14 pin ribbon cable and associated socket Th
165. aster configuration modes The FPGA s internal configuration logic is clocked by the internally generated CCLK signal and is not susceptible to external switching noise That said good signal integrity on the CCLK board trace is a good design practice Spartan 3 Generation Configuration User Guide www xilinx com 41 UG332 v1 2 May 23 2007 Chapter 2 Configuration Pins and Behavior during Configuration XILINX Internal Oscillator Configuration N Logic a Spartan 3 and Spartan 3E FPGAs b Ppa TASAN AA DSP s UG332_c2_03_040107 Figure 2 2 Differences between Spartan 3 3E and Spartan 3A 3AN 3A DSP FPGAs for Master Configuration Modes CCLK Design Considerations The FPGA s configuration process is controlled by the CCLK configuration clock Consequently signal integrity of CCLK is important to guarantee successful configuration Poor CCLK signal integrity caused by ringing or reflections potentially causes double clocking which might result in failed configuration Although the CCLK frequency is relatively low the FPGA s output edge rates are fast Therefore pay careful attention to the CCLK signal integrity on the printed circuit board Signal integrity simulation with IBIS is recommended For all configuration modes except JTAG the signal integrity must be considered at every CCLK trace destination including the FPGA s CCLK pin This analysis is especially important for Spartan 3E FPGAs where the FPGA
166. at provides an alternate means to create a Spartan 3AN programming file PROMGen can be invoked from within a command window or from within a script file Table 10 4 shows the relevant options for formatting a Spartan 3AN programming file Table 10 4 PROM Generator Command Options PROMGen Option Description REQUIRED Specifies the correct bit ordering required to configure ix from the SPI based In System Flash memory PROM output file format Specifies the file format required by the SPI p format programming software Refer to the third party programmer documentation for details Specifies the PROM size in kilobytes The PROM size must be a power of 2 and the default setting is 64 kilobytes s size By default the Spartan 3AN In System Flash memory uses a non binary addressing method which uses an additional address bit Use the size settings shown in Table 10 5 Loads the bit file from the specified starting address in an upward direction This option must be specified immediately before the input bitstream file See Table 10 3 page 209 for starting addresses by Spartan 3AN FPGA part type u address Table 10 5 Spartan 3AN PROMGen Size Settings In System Flash Size S size Setting by Address Mode Spartan 3AN FPGA bits Default Power of 2 XC3S50AN 1M 256 128 XC3S200AN 4M 1 024 512 XC3S400AN 4M 1 024 512 XC3S700AN 8M 2 048 1 024 XC3S1400AN 16M 4 096 2 048
167. at switches between the x8 or x16 modes During configuration Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs only support byte wide data as shown in Figure 5 3a However after configuration as shown in Figure 5 3b the FPGA supports either x8 or x16 modes because the FPGA s LDC2 pin which controls the PROM s BYTE mode input is controlled by the FPGA application In x16 mode up to eight additional user I O pins are required for the upper data bits D 15 8 Caution Different Flash memory vendors use different nomenclature when naming address pins Make sure that the FPGA connects correctly to the selected memory 140 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Precautions Using x8 x16 Flash PROMs 32Mbit Flash 32Mbit Flash FPGA 4Mx8 Mode FPGA 2Mx16 Mode LDCO CE User _CE CE LDC1 OE User OE OE HDC WE User WE WE LDC2 BYTE l T BYTE 7 XILINX D 7 0 DQ 7 0 7 XILINX D 7 0 DQ 7 0 A 21 1 A 20 0 A 21 1 A 20 0 AO DQ15 A 1 User D15 DQ15 A 1 User VO DQ 14 8 User D 14 8 DQ 14 8 a Byte wide interface during configuration b 16 bit interface after configuration UG332 c5 07 040107 Figure 5 3 FPGA Supports x8 Interface before Configuration and Optional x16 Interface after Configuration Connecting a Spartan 3E or Spartan 3A 3AN 3A DSP FPGA to a Flash PROM that supports both x8 x16 modes is simple but does require a precaution Various Flash
168. ate control GTS activating I O GWE cycle 6 ud the global write enable GWE allowing RAM and flip ops to change state N A 7 Assert EOS The FPGA automatically pulses the Global Set Reset GSR signal when entering the Startup sequence forcing all flip flops and latches in a known state The sequence and timing of how the FPGA switches over is programmable as is the clock source controlling the sequence The default start up sequence appears in Figure 12 12 where the Global Three State signal GTS is released one clock cycle after DONE goes High This sequence allows the DONE signal to enable or disable any external logic used during configuration before the user application in the FPGA starts driving output signals One clock cycle later the Global Write Enable GWE signal is released This allows signals to propagate within the FPGA before any clocked storage elements such as flip flops and block ROM are enabled The function of the dual purpose I O pins such as M 2 0 VS 2 0 HSWAP PUDC_B and A 25 0 also changes when the Global Three State GTS signal is released The dual purpose configuration pins become user I Os The exception on Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs is the CCLK pin which becomes a user I O pin at the End of Startup EOS 234 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 x XILINX Startup Default Cycles DONE m EI E GWE
169. ating that initialization i e housecleaning of the configuration memory has in progress When INIT B returns High the FPGA samples the M 2 0 mode select pins and begins the configuration process During configuration the INIT B pin is an open drain bidirectional I O pin with a dedicated internal pull up resistor required to produce a High logic level On Spartan 3A 3AN 3A DSP and Spartan 3E FPGAs the INIT B pull up resistor connects to VCCO 2 on Spartan 3 FPGAs the pull up resistor connect to VCCO 4 or VCCO BOTTOM depending on the package style In a multi FPGA daisy chain or broadside configuration connect wire AND the INIT B pins from all FPGAs together as shown in Figure 2 1 page 39 The common node ensures that all FPGAs in the design complete their respective housecleaning before any of the FPGAs is allowed to start configuring The common node transitions High only after all of the FPGAs have been successfully initialized Externally holding this pin Low beyond the initialization phase delays the start of configuration This action stalls the FPGA at the configuration step just before the M 2 0 mode select pins are sampled See Delaying Configuration page 229 During configuration the FPGA indicates the occurrence of a configuration data error i e CRC error by asserting INIT B Low See CRC Checking during Configuration page 291 After Configuration After configuration successfully completes i e when
170. ation Table 5 4 Example Compatible Parallel NOR Flash Families Flash Vendor Flash Memory Family Status STMicroelectronics M29W Hardware tested Atmel AT29 AT49 Hardware tested Spansion AMD Fujitsu Am29 S29 Data sheet compatible Intel StrataFlash J3 v D Hardware test Macronix MxX29 Data sheet compatible Required Parallel Flash PROM Densities Table 5 5 indicates the smallest usable parallel Flash PROM to program a single Spartan 3A 3AN 3A DSP or Spartan 3E FPGA Parallel Flash memory devices are typically specified by bit density but the memory is addressed as bytes or half words Spartan 3A 3AN 3A DSP FPGAs present up to 26 address lines during configuration although not all are address lines are required depending on number of bytes required to hold the FPGA bitstream s Table 5 5 shows the minimum required number of address lines between the FPGA and parallel Flash PROM The actual number of address line required depends on the density of the attached parallel Flash PROM Table 5 5 Number of Bits to Program a Spartan 3A 3AN 3A DSP or Spartan 3E FPGA and Smallest Usable Parallel PROM Uncompressed Smallest Usable Minimum Required Family FPGA File Sizes bits Parallel Flash PROM Address Lines XC3S50A AN 437 312 BPI Mode not available on XC3S50A FPGAs XC38200A AN 1 196 128 2 Mbit A 17 0 Spartan 3A 3AN XC38400A AN 1 886 560 2 Mbit A 17 0 XC38700A AN
171. ation word differ between the Spartan 3A 3AN 3A DSP FPGA families and the Spartan 3 and Spartan 3E FPGA families as outlined in Table 12 3 Array ID Next the array ID is embedded in the bitstream so that the FPGA can check that it matches its internal array ID This prevents the FPGA from mistakenly attempting to load configuration data intended for a different FPGA array For example the array ID check prevents an XC3S1000 from being configured with an XC35200 bitstream Table 12 4 shows the Spartan 3 Generation array ID codes Data Frames Next is the internal configuration memory partitioned into segments called data frames The Spartan 3 Generation configuration memory can be visualized as a rectangular array of bits The bits are grouped into vertical frames that are one bit wide and extend from the top of the array to the bottom A frame is the atomic unit of configuration It is the smallest portion of the configuration memory that can be written to or read from The number and size of frames varies with device size seeTable 1 5 The total number of configuration bits for a particular device is calculated by multiplying the number of frames by the number of bits per frame and then adding the total number of bits needed to perform the configuration register writes Table 1 5 Spartan 3 Generation Configuration Data Frames Spartan 3 Generation Number of Frame Length FPGA Family
172. ator Active Low Active during configuration User I O If unused in the drain Goes Low at start of configuration If SPI Flash PROM requires application drive INIT_B bidirectional during Initialization memory more than 2 ms to awake after High I O clearing process Released at end of powering on hold INIT B memory clearing when mode select Low until PROM is ready See pins are sampled See Initializing Power On Precautions if Configuration Memory System nod Supply is Last in Configuration Error INIT_B Sequence page 96 page 45 If CRC error detected during configuration FPGA drives INIT_B Low See CRC Checking during Configuration page 291 DONE Open FPGA Configuration Done Low Low indicates that the FPGA Pulled High via external drain during configuration Goes High is not yet configured pull up When High bidirectional when FPGA successfully completes indicates that the FPGA I O configuration See DONE Pin successfully configured Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 95 Chapter 4 Master SPI Mode EZ XILINX Table 4 8 Serial Peripheral Interface SPI Connections Continued FPGA Pin Name Direction Description During Configuration After Configuration PROG B Input Program FPGA Active Low When Must be High to allow Drive PROG B Low and asserted Low for 500 ns or longer configuration to start release to r
173. avior during and after configuration These options are summarized immediately below and described in detail on the next few pages e DriveDone defines whether the DONE pin is an active driver or an open drain output e DonePin defines whether or not the DONE pin has an internal pull up resistor e DONE cycle defines the Startup state where is DONE driven High or released to float High e DonePipe adds an extra pipelining stage before the FPGA actually completes configuration 36 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX General Configuration Control Pins DriveDone The DriveDone bitstream generator option shown in Table 2 4 defines whether the DONE pin has a totem pole output that actively drives High or acts an open drain output If configured as an open drain output which is the default behavior then a pull up resistor is required to produce a High logic level The DonePin bitstream option controls the pull up resistor Table 2 4 DriveDone Bitstream Generator Option Setting No Description Default The DONE pin is an open drain output A pull up resistor to VccAUx is required An internal pull up resistor is available using the DonePin Pullup bitstream generator option Yes The DONE pin actively drives High when the FPGA completes the configuration process Set DriveDone Yes in single FPGA applications or for the first desig
174. be considered when test vectors are being developed for testing opens and shorts The Boundary Scan mode determines whether an I O block has a pull up resistor Bit Sequence Boundary Scan Register The order of each non TAP IOB is described in this section The input is first then the output and finally the 3 state IOB control The 3 state IOB control is closest to the TDO The input only pins contribute only the input bit to the Boundary Scan I O data register The bit sequence of the device is obtainable from the Boundary Scan Description Language Files BSDL files for Spartan 3 Generation FPGAs The bit sequence always has the same bit order and the same number of bits and is independent of the design The BSDL files are provided with the Xilinx ISE Development Software or can be downloaded directly from the Xilinx web site From the Xilinx web site select BSDL Models select the FPGA family then click Search Spartan 3 Generation Configuration User Guide www xilinx com 189 UG332 v1 2 May 23 2007 Chapter 9 JTAG Configuration Mode and Boundary Scan XILINX e Xilinx Download Center http www xilinx com xlnx xil sw updates home jsp Instruction Register The Instruction Register IR for the Spartan 3 Generation FPGA is connected between TDI and TDO during an instruction scan sequence In preparation for an instruction scan sequence the instruction register is parallel loaded with a fixed instruction capture pattern
175. bitstream Instead of daisy chaining the FPGAs and storing multiple copies of the same bitstream Ganged or Broadside Configuration programs multiple identical FPGAs with the same bitstream as shown in Figure 3 5 page 71 70 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Ganged or Broadside Configuration O Koy Platform Flash XCF M2 M1 MO M2 M1 MO CCLK DIN DOUT INIT B PROG B DONE PROGRAM UG332 c3 02 111906 Figure 3 4 Multi FPGA Daisy Chain Configuration Using Xilinx Platform Flash PROM Koy o Koy Platform Flash XCFxxx M2 M1 MO CCLK INIT B PROG B DONE Master FPGA M2 M1 MO CCLK Slave FPGA UG332 c3 03 111906 Figure 3 5 Multiple Identical FPGAs Programmed with the Same Bitstream Spartan 3 Generation Configuration User Guide www xilinx com 71 UG332 v1 2 May 23 2007 Chapter 3 Master Serial Mode XILINX JTAG Interface Spartan 3 Generation FPGAs and the Platform Flash PROMs both have a four wire IEEE 1149 1 1532 JTAG port Both the FPGA and the PROM share the JTAG TCK clock input and the TMS mode select input The devices may connect in either order on theJTAG chain with the TDO output of one device feeding the TDI input of the following device in the chain The TDO output of the last device in the JTAG chain drives the JTAG connector The JTAG interface on the FPGA is powered by the VccAux supply Consequ
176. bsd Enable Programming of BPI Flash Device Attached to this FPGA UG332 c4 23 032807 Figure 4 22 Select the FPGA Bitstream File and Enable SPI Programming Select Enable Programming of SPI Flash Device Attached to this FPGA Click Open The iMPACT software warns that it changed the Startup clock source over to theJTAG clock pin TCK The SPI Flash image is not affected This warning is safely ignored B Warning xi A WARNING iMPACT 2257 Startup Clock has been changed to JtagCIk in the bitstream stored in memory but the original bitstream File remains unchanged UG332 c4 24 032807 Figure 4 23 iMPACT Uses the JTAG Clock Input TCK for Startup Clock when Programming via JTAG 120 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 Indirect Programming using iMPACT EZ XILINX 7 Asshown in Figure 4 24 select the programming file for the attached SPI Flash PROM Look in E switches_leds ex E3 Desktop File name Files of type UG332 c4 26 032907 Figure 4 24 Select the SPI PROM Programming Flle 8 Click Open 9 Selectthe part number for the attached SPI Flash PROM as shown in Figure 4 25 Select Device Part Name Select PROM Part Name M25P16 X Cancel Help UG332 c4 27 032907 Figure 4 25 Select SPI Flash PROM Type 10 Click OK Spartan 3 Generation Configuration User Guide www xilinx com UG332 v
177. bt Places Add Device Files of type FPGA dE a t lin zi IER i i You have completed the device file entry 4 Click Ok to continue UG332 c10 06 022307 Figure 10 9 Add FPGA Configuration Bitstream File s 18 Locate and select the desired Spartan 3AN FPGA bitstream 210 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Preparing an In System Flash Programming File 19 Click Open 20 If the Bitstream 1 option box was checked in Step 12 the iMPACT software will prompt for a second bitstream After selecting the last FPGA bitstream click OK 21 As shown in Figure 10 10 the iMPACT software graphically displays the selected Spartan 3AN FPGA and any associated FPGA bitstream s UG332_c10_07_022307 Figure 10 10 iMPACT View of the Spartan 3AN In System Flash Memory 22 The location of the first and second bitstreams is also highlighted 23 As shown Figure 10 11 click Generate File Erg Sources Snapsht D Libr PROM File Generation Succeeded xc3s700an top level bit UG332 c10 08 022307 Figure 10 11 Generate the Spartan 3AN In System Flash File 24 The iMPACT software indicates when the PROM file is successfully created Spartan 3 Generation Configuration User Guide www xilinx com 211 UG332 v1 2 May 23 2007 Chapter 10 Internal Master SPI Mode XILINX PROMGen PROMGen is a command line utility th
178. cation from where the first configuration image loads The initial location depends on the BPI mode pin settings Spartan 3 Generation Configuration User Guide www xilinx com 251 UG332 v1 2 May 23 2007 Chapter 14 Reconfiguration and MultiBoot XILINX iMPACT Spartan3E MultiBoot PROM Spartan 3E Spartan 3E MultiBoot PROM Using BPI Mode Initial Boot Direction uP UP DOWN Cancel UG332 c14 05 112906 Figure 14 4 Select the Configuration Direction of the First MultiBoot Image 10 Click Next 11 As shown in Figure 14 5 Select a Parallel PROM Density measured in bytes iMPACT Spartan3E BPI PROM Propeuf wv milej x YS mum Select a Parallel PROM Density Bytes Position Density 0 1M Delete All Data Stream Enable Data Addr 23 0 Version Data Stream Direction Hex Default or 0 I Up o 1 Vv Down FFFFF NIS Cancel UG332_c14_06_112906 Figure 14 5 Selecta PROM Size and Add It to the Design 12 Click Add to use the PROM density specified in Step 11 In Spartan 3E MultiBoot mode only a single PROM is allowed The PROM density also determines the highest PROM address location 13 Click Next 14 TheiMPACT software summarizes the current settings as shown in Figure 14 6 Click Finish to continue 252 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Spartan 3E MultiBoot iMPACT File Gen
179. ch as a boot block or a specific sector size The BPI interface also works equally well with other asynchronous memories that use a similar SRAM style interface such as the following many of which have faster access times e Xilinx Parallel Platform Flash PROMs XCFxxP e SRAM e NVRAM non volatile RAM e EEPROM e EPROM e Masked ROM NAND Flash memory is a different technology and is commonly used in memory cards for digital cameras Spartan 3A 3AN 3A DSP and Spartan 3E FPGAs do not configure directly from NAND Flash memories The FPGA s internal oscillator controls the interface timing and the FPGA supplies the clock on the CCLK output pin However the CCLK signal typically is not used connected in single FPGA applications Similarly the FPGA drives three pins Low during configuration LDC 2 0 and one pin High during configuration HDC to the PROM s control inputs Spartan 3 Generation Configuration User Guide www xilinx com 129 UG332 v1 2 May 23 2007 Chapter 5 Master BPI Mode XILINX 1 2V VCCINT HSWAP VCCO 0 CER x8or OE4 X8 x16 NOR WEF Flash Not available in A n 0 VQ100 package BPI Mode A 23 17 Address Control 0 D 7 0 0 BPI Up M1 1 BPI Down Mo XILINX If VCCAUX 2 5V Spartan 3E FPGA CCLK CSI B CSO B RDWR B INIT B 12 5 PROG B DONE GND Xilinx Cable Header JTAG Interface PROGRAM Figure 5 1 Sparta
180. ckage Pin 1 for the 8 pin SOIC and MLP packages is located in the top left corner However pin 1 for the 16 pin SOIC package is located in the top right corner because the package is rotated 90 The 16 pin SOIC package also has four pins at the center each side that do not connect on the board These pins must be left unconnected i e floating o a Pin 1 a F 16 pin SOIC Pin 1 8 pin SOIC Do not connect 8 lead MLP VCC HOLD C G Do not connect z o o z UG230 c15 18 030606 Figure 4 30 Multi Package Layout for the STMicroelectronics M25Pxx Family on Spartan 3E Stater Kit Board Saving Power Most SPI Flash memories support multiple power saving options e Standby Mode reduces power simply by de selecting the SPI Flash memory Within the FPGA application drive the CSO B pin High e Deep Power Down Mode requires that the FPGA issue a specific command to enter and exit this mode Deassert CSO B to Enter Standby Mode The SPI Flash memory automatically enters Standby power mode when the memory s active Low Slave Select line is deasserted High After configuration or when not accessing the SPI Flash the application must drive the CSO B pin High Deep Power Down Mode To reduce power consumption even further most SPI Flash memory devices support a Deep Power Down Mode The FPGA application must issue a separate and specific Spartan 3 Generation Configuration User Guide www xilinx com 127 UG332 v1 2
181. clock source is TCK StartupClk JtagClk JSHUTDOWN 001101 Clocks the shutdown sequence ISC ENABLE Marks the beginning of ISC configuration Full 010000 shutdown is executed ISC PROGRAM 010001 Enables in system programming 190 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Boundary Scan for Spartan 3 Generation FPGAs Using IEEE Standard 1149 1 Table 9 4 Spartan 3 Generation Boundary Scan Instructions Continued Boundary Scan Command Instruction Description ISC_NOOP 010100 No operation ISC_READ 010101 Used to read back BBR ISC_DISABLE oroia Completes ISC configuration Startup sequence is executed ISC_DNA icon Spartan 3A 3AN 3A DSP FPGAs Read Device DNA See JTAG Access to Device Identifier page 281 BYPASS 111111 Enables BYPASS RESERVED Allother Xilinx reserved instructions codes Figure 3 4 shows the instruction capture values loaded into the IR as part of an instruction scan sequence TDI IR 5 IR 4 IR 3 IR 2 IR 1 0 TDO DONE INIT 1 ISC_ENABLED ISC_DONE 01 BYPASS Register The BYPASS register which consists of a single flip flop between TDI and TDO is required in all JTAG IEEE 1149 1 compliant devices It passes data serially from the TDI pin to the TDO pin during a bypass instruction The BYPASS register initializes to zero when the TAP controller is
182. com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Boundary Scan for Spartan 3 Generation FPGAs Using IEEE Standard 1149 1 Boundary Scan operations are independent of how an individual I O block is configured By default each I O block starts as bidirectional with 3 state control Later it can be configured via JTAG operations to be an input output or 3 state pin TDI Capture Update 4 l 4 Register ia ens i INTEST IOB I PAD IOB O IOB T EXTEST SHIFT CLOCK DATA TDO UPDATE INTEST or EXTEST REGISTER UG332 c9 04 081506 Figure 9 4 Boundary Scan Logic per I O Pin When conducting a data register DR operation the DR captures data in a parallel fashion during the CAPTURE DR state The data is then shifted out and replaced by new data during the SHIFT DR state For each bit of the DR an update latch is used to hold the input data stable during the next SHIFT DR state The data is then latched during the UPDATE DR state when TCK is Low The update latch is opened each time the TAP controller enters the UPDATE DR state Care is necessary when exercising an INTEST or EXTEST to ensure that the proper data has been latched before exercising the command This is typically accomplished by using the SAMPLE PRELOAD instruction Internal pull up and pull down resistors should
183. ct Be agi VS 2 0 S9 8 Vso o M2 FPGA Mode Select Be MO MIE O o 8 MO 0 From Pins 1 From Mode Register NEW_MODE UG332_c14_02_082106 Figure 14 20 Spartan 3A 3AN 3A DSP MultiBoot Configuration Mode Control 272 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Basic FPGA Hardware Level Security Options Chapter 15 Protecting FPGA Designs Similar to a processor a Spartan 3 Generation FPGA receives its configuration information i e its application program from an external memory source The exposed external interface makes both processor code and FPGA bitstreams potentially vulnerable to copying or cloning Unlike a processor there are no simple reverse assemblers for FPGA applications Processors have a defined fixed instruction set and instruction length making a reverse assembler for a processor a straightforward task However reverse engineering an entire FPGA design and then converting it to a human understandable form is exceedingly difficult An FPGA configuration bitstream contains millions of interrelated bits Furthermore the Xilinx bitstream format is both proprietary and confidential While reverse engineering an FPGA bitstream is difficult directly copying an FPGA bitstream without understanding its underlying function is rather straightforward This chapter describes the available low cost solutions to protect a design agains
184. cy of CCLK at that ConfigRate setting The number of spacing bits required also depends on the configuration mode The SPI Flash mode receives one bit per clock while the BPI mode receives eight bits or one byte per clock Example A Spartan 3A MultiBoot application includes an FPGA bitstream that contains at least one DCM with the DCM WAIT option set TRUE The FPGA application uses a DLL output from the DCM The input clock frequency to the DCM is 33 MHz The data sheet lock time specification LOCK DLL for DCM clocks faster than 15 MHz is 600 us The FPGA bitstream has the ConfigRate option set to 25 According to D5529 Spartan 3A FPGA Family Data Sheet setting ConfigRate 25 means that CCLK will never have a period shorter than 45 ns The MultiBoot application configures from an SPI serial Flash Dividing the 600Ls lock time by the 45 ns CCLK period yields 13 334 clock cycles In SPI mode the FPGA receives one bit per clock cycle Consequently under these conditions two MultiBoot configuration images must be place more than 13 334 bit locations from each other in memory If the FPGA configured from parallel Flash then the FPGA receives 8 bits per clock cycle Consequently the application must space the two configurations apart by more than 13 334 byte locations which is equivalent to 106 672 bits The memory space between two configuration images can contain data as long as it does not contain a valid Spartan 3A configuration
185. d VCCO 2 supply voltages must also be 3 3V to match the parallel Flash PROM There are some 1 8V parallel Flash PROMs available and Spartan 3E FPGAs interface with these devices if the VCCO 1 and VCCO 2 supplies are also 1 8V Spartan 3A 3AN 3A DSP FPGAs do not support 1 8V PROMs because of the Spartan 3A FPGA s Power On Reset POR voltage threshold Vcco r shown in the appropriate Spartan 3A 3AN 3A DSP data sheet and summarized in Table 12 1 page 227 Also see Power On Precautions if 3 3V Supply is Last in Sequence page 154 See also JTAG Cable Voltage Compatibility page 184 136 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Compatible Parallel NOR Flash Families Compatible Parallel NOR Flash Families The Spartan 3E and Spartan 3A 3AN 3A DSP BPI configuration interface operates with a wide variety of x8 or x8 x16 parallel NOR Flash devices Table 5 4 provides a few example Flash memory families that operate with the BPI interface Xilinx has hardware tested various family members from some vendors Other devices appear to be compatible based on a data sheet analysis Consult the manufacturer s data sheet for the desired parallel NOR Flash device to determine the suitability of a specific device While most parallel NOR Flash have comparable memory read functions different vendors may use different programming algorithms which has no impact on FPGA configur
186. d in Master SPI mode set the following bitstream generator options ConfigRate CCLK Frequency Set the ConfigRate option as described in CCLK Frequency page 98 Using ISE Project Navigator the Configuration Rate frequency is set in Step 7 in Figure 1 7 page 29 g ConfigRate 12 Spartan 3 Generation Configuration User Guide www xilinx com 109 UG332 v1 2 May 23 2007 Chapter 4 Master SPI Mode XILINX StartupClk CCLK By default the configuration Startup clock source is the internally generated CCLK Keep the StartupClk bitstream generation option shown as Step 13 in Figure 1 8 page 30 g StartupClk Cclk DriveDone Actively Drive DONE Pin In a single FPGA design or for the Master FPGA in a multi FPGA daisy chain set the FPGA to actively drive the DONE pin after successfully completing the configuration process Using ISE Project Navigator check the Drive Done Pin High option shown as Step 16 in Figure 1 8 page 30 g DriveDone Yes DONE cycle Daisy Chains with Spartan 3E Master If a Spartan 3E FPGA is the Master FPGA in an SPI based daisy chain ensure that DONE cycle is set for cycle 5 or earlier From ISE Project Navigator the DONE cycle setting is the Done Output Events option shown as Step 14 in Figure 1 8 page 30 g DONE cycle 4 GTS cycle Global Three State Release Timing for Daisy Chains If creating a multi FPGA daisy chain set the GTS cycle option to be later than the DONE cycle setti
187. d not used on Spartan 3A 3AN 3A DSP FPGAs Unlike Spartan 3E FPGAs however Spartan 3A 3A 3A DSP FPGAs do use the DOUT pin in BPI serial daisy chains which are only supported on Spartan 3A 3AN 3A DSP FPGAs 56 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Default I O Standard During Configuration Spartan 3 FPGAs Table 2 18 shows the various Spartan 3 FPGA pins that are either borrowed or dedicated during configuration Table 2 18 Pin Behavior during Configuration for Spartan 3 FPGA Family Dedicated Pull Up Master Master Slave Supply Pin Name Resistor Serial Parallel JTAG Slave Serial Parallel I O Bank IP input only table TDI Yes TDI TDI TDI TDI TDI VCCAUX TMS Yes TMS TMS TMS TMS TMS VCCAUX TCK Yes TCK TCK TCK TCK TCK VCCAUX TDO Yes TDO TDO TDO TDO TDO VCCAUX Yes PROG B PROG B PROG B PROG B PROG B Vccaux Yes DONE DONE DONE DONE DONE VCCAUX Yes HSWAP HSWAP HSWAP HSWAP HSWAP VCccAUX Yes 0 0 1 1 1 VCCAUX Yes 0 1 0 1 1 VCCAUX Yes 0 1 1 1 0 VCcCAUX Yes CCLK CCLK CCLK CCLK VCCAUX I O I O INPUT INPUT Yes INIT_B INIT_B INIT_B INIT_B 4 CS B CS B 5 DOUT BUSY DOUT BUSY 4 D 74 D 7 4 5 D 3 1 D 3 1 4 DIN DO DIN DO 4 RDWR_B RDWR_B 5 Notes 1 Gray shaded cells represent pins that are in a high impedance state Hi Z floating during configuration The
188. d numerous times The downloaded modes are available on all Spartan 3 Generation FPGA families The Spartan 3E and Spartan 3A 3AN 3A DSP FPGA families introduce a new capability called MultiBoot that allows the FPGA to selectively reprogram and reload its bitstream from an attached external memory The MultiBoot feature allows the FPGA application to load two or more FPGA bitstreams under the control of the FPGA application The FPGA application triggers a MultiBoot operation causing the FPGA to reconfigure from a different configuration bitstream As shown in Table 14 1 there are differences between MultiBoot on Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs Once a MultiBoot operation is triggered the FPGA restarts its configuration process as usual The INIT_B pin pulses Low while the FPGA clears its configuration memory and the DONE output remains Low until the MultiBoot operation successfully completes For Spartan 3E FPGA applications see Spartan 3E MultiBoot page 249 For Spartan 3A 3AN 3A DSP FPGA applications see Spartan 3A 3AN 3A DSP MultiBoot page 257 MultiBoot Options Compared between Spartan 3 Generation FPGA Families Table 14 1 highlights the primary MultiBoot differences between Spartan 3 Generation FPGA families The MultiBoot feature is available only on the Spartan 3E and Spartan 3A FPGA families Spartan 3 Generation Configuration User Guide www xilinx com 247 UG332 v1 2 May 23 2007 Chapter 14 R
189. d out sequentially while the JTAG controller is in the RUN TEST IDLE state Authentication Design Examples Authentication can take various forms in an application as described in the examples below Some of these examples configure from an attached PROM others are downloaded into the FPGA Spartan 3A 3AN 3A DSP FPGA Imprinting or Watermarking the Configuration PROM with Device DNA page 282 Spartan 3E FPGA Leveraging Security Features in Select Commodity Flash PROMs page 283 Spartan 3A 3AN 3A DSP FPGA Authenticating a Downloaded Design page 285 Authenticating any FPGA Design Using External Secure PROM page 286 Spartan 3 Generation Configuration User Guide www xilinx com 281 UG332 v1 2 May 23 2007 Chapter 15 Protecting FPGA Designs XILINX Spartan 3A 3AN 3A DSP FPGA Imprinting or Watermarking the Configuration PROM with Device DNA The Spartan 3A 3AN 3A DSP FPGA in Figure 15 6 configures using one of the Master configuration modes from an associated configuration PROM The PROM contains both the FPGA configuration bitstream and a previously generated authentication check value The PROM itself does not require any special features just enough memory to contain both the FPGA bitstream and the authentication check value The Spartan 3A 3AN 3A DSP FPGA has an internal unique Device DNA value At power up or when PROG B is pulsed Low the FPGA configures normally Spartan 3A 3AN 3A DSP FPGA Configu
190. d used in the application See Table 2 15 page 50 for pull down resistor values After configuration the FPGA can selective enable the PROM by driving the associated I O pin High or Low See the following application notes for specific details on how to implement such an interface Spartan 3 Generation Configuration User Guide www xilinx com 73 UG332 v1 2 May 23 2007 Chapter 3 Master Serial Mode XILINX e XAPP482 MicroBlaze Platform Flash PROM Boot Loader and User Data Storage http www xilinx com bvdocs appnotes xapp482 pdf e XAPP694 Reading User Data from Configuration PROMs http www xilinx com bvdocs appnotes xapp694 pdf Generating the Bitstream for a Master Serial Configuration The create the FPGA bitstream for a Master Serial mode configuration follow the steps outlined in Setting Bitstream Options Generating an FPGA Bitstream page 27 For an FPGA configured in Master SPI mode set the following bitstream generator options ConfigRate CCLK Frequency Set the ConfigRate option as described in CCLK Frequency page 70 Using ISE Project Navigator the Configuration Rate frequency is set in Step 7 in Figure 1 7 page 29 g ConfigRate 25 StartupClk CCLK By default the configuration Startup clock source is the internally generated CCLK Keep the StartupClk bitstream generation option shown as Step 13 in Figure 1 8 page 30 g StartupClk Cclk DriveDone Actively Drive DONE Pin In a sin
191. ddress 0 if Yes MultiBoot operation fails Notes 1 See Spartan 3AN Errata regarding limitations using MultiBoot after configuration from the in system Flash 248 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Spartan 3E MultiBoot Spartan 3E MultiBoot After the FPGA configures itself using BPI mode from one end of the parallel Flash PROM then the FPGA can trigger a MultiBoot event and reconfigure itself from the opposite end of the parallel Flash PROM MultiBoot is only available when using BPI mode and only for applications using a single Spartan 3E FPGA MultiBoot does not support multi FPGA configuration daisy chains By default the MultiBoot feature is disabled To use MultiBoot in an application the FPGA design must first include a STARTUP_SPARTAN3E design primitive described in Start Up STARTUP page 241 To trigger a MultiBoot event assert a Low pulse lasting at least 300 ns on the MultiBoot Trigger MBT input to the primitive When the MBT signal returns High after the Low pulse the FPGA automatically reconfigures from the opposite end of the parallel Flash memory Figure 14 1 illustrates a simple MultiBoot design example At power up the FPGA loads itself from the attached parallel Flash PROM In this specific example the MO mode pin is Low so the FPGA configures starting at Flash address 0 and increments through the PROM memory locations A
192. different package options For example Xilinx Platform Flash provides excellent migration between 1 to 4 Mbits using the XCFxxS serial family and between 8 to 32 Mbits using the XCFxxP parallel family If an application spans between the two use two separate footprints one for each Platform Flash sub family Be aware that the XCFxxP Flash family requires a 1 8V supply input while the XCFxxS requires 3 3V Spartan 3 Generation Configuration User Guide www xilinx com 21 UG332 v1 2 May 23 2007 Chapter 1 Overview and Design Considerations EZ XILINX Table 1 3 PROM Families and Footprint Compatible Package Migration Config Serial Mode PROM Family XCExxS serial Platform Flash Package PROM Density in Bits Associated Part Numbers Option VO20 XCFxxP parallel Platform Flash VO48 XCFO1S XCF02S XCFO8P XCF16P XCF32P FS48 Master SPI Mode ST compatible SPI Flash Multi Package Footprint 8SOIC JEDEC 8SOIC EIAJ 16SOIC 8MLP Atmel AT45DBxxxD SPI Flash Multi Package Footprint 8SOIC JEDEC 8SOIC EIAJ 8CASON Master BPI Mode x8 Parallel NOR Flash 40 pin TSOP x8 x16 Parallel NOR Flash 48 pin TSOP XCFO8P XCF16P XCF32P Part number varies by vendor 011D 021D 041D 081D 161D 321D 642D Part number varies by vendor EE Part number varies by vendor
193. ding the FPGA s VCCO 2 voltage input typically 3 3V SPI Flash PROMs specify that they cannot be accessed until their Vcc supply reaches its minimum data sheet voltage followed by an additional delay For some devices this additional delay is as little as 10 us as shown in Table 4 9 For other vendors this delay is as much as 20 ms 96 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Power On Precautions if System 3 3V Supply is Last in Sequence Table 4 9 Example Minimum Power On to Select Times for Various SPI Flash PROMs SPI Flash PROM Data Sheet Minimum Time from Vcc min to Select Low Vendor Part Number Symbol Value Units STMicro M25Pxx TysL 10 us Spansion S25FLxxxA tpu 10 ms NexFlash NX25xx TysL 10 us Macronix MX25Lxxxx tvsr 10 us Silicon Storage Technology SST25LFxx TPU READ 10 us Programmable Microelectronics Pm25LVxxx Tvcs 50 us Corporation Atmel Corporation AT45DBxxxD tvcsr 50 us AT45DBxxxB 20 ms Notes 1 Memory vendors are continuously improving their products and specifications Please check with the memory vendor s data sheets for up to date values In many systems the 3 3V supply feeding the FPGA s VCCO 2 input is valid before the FPGA s other Vccmr and VccAux supplies and consequently there is no issue However if the 3 3V supply feeding the FPGA s VCCO 2 supply is last in the sequence a pote
194. e UCF 6 cece eens 296 CONFIG Constraints eee ccre err ebd e E eei eec decided es dung 296 Bitstream Generator Options 6 66 ccc ene nnn 297 Design Considerations oses tispe Sita ta eet ee eee 297 Techniques to Check Distributed and Block RAM Contents 4 298 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Design Considerations Chapter 1 Overview and Design Considerations Xilinx Spartan 3 Generation Field Programmable Gate Arrays FPGAs are highly flexible reprogrammable logic devices that leverage advanced CMOS manufacturing technologies similar to other industry leading processors and processor peripherals Like processors and peripherals Spartan 3 Generation FPGAs are fully user programmable For FPGAs the program is called a configuration bitstream which defines the FPGA s functionality The bitstream loads into the FPGA at system power up or upon demand by the system The process whereby the defining data is loaded or programmed into the FPGA is called configuration Configuration is designed to be flexible to accommodate different application needs and wherever possible to leverage existing system resources to minimize system costs Similar to microprocessors Spartan 3 Generation FPGAs optionally load or boot themselves automatically from an external nonvolatile memory device Alternatively similar to microprocessor peripherals Spar
195. e 4 11 Set Options for a 3rd Party SPI PROM Select a PROM File Format Enter a PROM File Name Click Next As shown in Figure 4 12 select the SPI PROM Density of the targeted device measured in bits Qo NL gs con iMPACT Specify SPI PROM Device Auto Select PROM Density Select SPI PROM Density bits puu eed UG332_c4_13_110206 Figure 4 12 Select SPI PROM Density 9 Click Next www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Preparing an SPI PROM File 10 As shown in Figure 4 13 review that the settings are correct to format the SPI PROM Click Finish to confirm the settings or Back to change the settings iMPACT File Generation Summary Eie Ea You have entered following information PROM Type SPI PROM File Format mcs Fill Value FF PROM filename MySPIFlashPROM Number of PROMs 1 Position PatNam 000000 0 16M Click Finish to start adding device files Figure 4 13 Review PROM Formatting Settings 11 As shown in Figure 4 14 click OK to start adding FPGA configuration bitstreams to the PROM image Add i p Adding device fie to the SPI PROM Look in o led crazy 4 My Recent Documents E OMET File name ied crazy bit Y Places i Files of type FPGA Bit Files bit UG332 c4 15 110206 Figure 4 14 Add FPGA Configuration Bitstream File s 12
196. e FPGA recognizes the synchronization word as described in Synchronization page 230 After the configuration bitstream is loaded the device enters the Startup sequence The FPGA asserts its DONE signal High in the Startup phase specified by the DONE cycle bitstream option See Startup page 233 The processor or controller must continue Spartan 3 Generation Configuration User Guide www xilinx com 171 UG332 v1 2 May 23 2007 Chapter 7 Slave Parallel SelectMAP Mode XILINX sending CCLK pulses until after the Startup sequence successfully completes which requires several CCLK pulses after DONE goes High After configuration the CSI B and RDWR B signals can be deasserted or they can remain asserted Because the SelectMAP port is inactive toggling RDWR B at this time does not cause an ABORT event Figure 7 5 summarizes the timing of SelectMAP configuration with continuous data loading PROG B wrB NASA i OS 3 5 3 RDWR B DATAL 0 77777777777777777 Kee 9X ere X Kore X NETT BUSY Honz QE 2 DONE UG332 c7 05 081006 Figure 7 5 SelectMAP Continuous Data Loading The following numbered items correspond to the markers provided in Figure 7 5 1 CSI Bsignal can be tied Low if there is only one device on the SelectMAP bus If CSI B is not tied Low it can be asserted at any time 2 RDWR B can be tied Low if readback is not needed RDWR B should not be toggled after
197. e board This is a potential complication for Spartan 3A 3AN 3A DSP FPGA applications that employ MultiBoot If using the Deep Power Down mode the FPGA must first issue the Release from Deep Power Down command before starting the MultiBoot operation 128 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Overview Chapter 5 Master BPI Mode Overview The master Byte wide Peripheral Interface BPI configuration mode is available for either the Spartan 3A 3AN 3A DSP and Spartan 3E FPGA families It is not supported on the Spartan 3 FPGA family although there is a similar mode that leverages Xilinx Parallel Platform Flash PROMs see Chapter 6 Master Parallel Mode In BPI mode a Spartan 3E or Spartan 3A 3AN 3A DSP FPGA configures itself from an standard parallel NOR Flash PROM as illustrated in Figure 5 1 page 130 for Spartan 3E FPGAs and Figure 5 2 page 131 for Spartan 3A 3AN 3A DSP FPGAs The figures show optional components in gray and designated NO LOAD The BPI configuration interface is primarily designed to support standard parallel NOR Flash PROMs and the interface supports both byte wide x8 and byte wide word wide x8 x16 PROMS In a pinch the interface also functions with word only x16 PROMs but the upper byte ina portion of the PROM remains unused For FPGA configuration the BPI interface does not require any specific Flash PROM features su
198. e bos RARE IER EE EP ead repr 173 Pausing C CL IK 2i d tad v thik ed Piceno eee eed de eee den 174 Select MAP ABORT 2 000 e044 peepetoviersetaeand dubiae adepto beer 174 Configuration Abort Sequence Description llssseseseeseeeeee 175 Readback Abort Sequence Description 175 ABORT Status Word 63 3603 sect sits ree Perse sa he ERR E E e Een 176 Resuming Configuration or Readback After an Abort 005 177 SelectMAP Reconfiguration sisse ee 177 SelectMAP Data Ordering ieeeeseve x CrRE Rr YA Er ERES UE pn 177 Chapter 8 Slave Serial Mode Voltage Compatibility iisssssssssssss ee 180 Daisy Ca reet i epum Diod Rupee e ERA nad bl o elei DR E IRR we 181 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Chapter 9 JTAG Configuration Mode and Boundary Scan JTAG Cable Voltage Compatibility isses eese 184 JIAG Device ID sicuti RR RR RREURETREEATRECKRRCCKPRECK RESCERA 184 JTAG UserID i ber RR rhe FR DR e ed eue T ped e ob EEE 184 Using JTAG Interface to Communicate to a Configured FPGA Design 185 Boundary Scan for Spartan 3 Generation FPGAs Using IEEE Standard 1149 1 185 lest Access Dort LAR creser ioy krr Rent eee oie nae CNN e x peat und 186 TAP Controller irete bte e hhI SE bebe Ree eG PE OEE QC Looe aw Pak aeg 187 Boundary Scan Architecture 6 0 cece ect nnn 188 Boundary Scan Register 000 6 bed eds oi
199. e each step in detail where the current step is highlighted at the beginning of each subsection Steps 1 l 2 l 3 4 5 6 7 8 l Wake from Clear Sample Control are Load Start Reset Configuration Pins Synchronization h Configuration CRC Check sequence power on or Memory M 2 0 VS 2 0 l Data PROG B Bitstream Setup Start Loading Finish UG332 c12 01 110406 Figure 12 1 Spartan 3 Generation FPGA Configuration Process Setup for Configuration Steps 1 3 The Setup process is similar for all configuration modes The Spartan 3 Generation FPGA first wakes from reset initializes its internal configuration memory and determines which configuration mode to use by sampling the mode pins Wake from Reset Steps 4 5 6 7 8 Clear Sample Control E Load Startu Configuration l Pins Synchronization pied Configuration CRC Check dnd Memory M 2 0 VS 2 0 Data Bitstream oadin cos Start 9 Finish UG332 c12 02 110406 Figure 12 2 FPGA Wake from Reset Spartan 3 Generation FPGAs wake from reset in several possible ways 1 The FPGA powers on and the FPGA s internal Power On Reset POR circuit holds the FPGA in reset until the required voltage supplies reach appropriate levels Spartan 3 Generation Configuration User Guide www xilinx com 225 UG332 v1 2 May 23 2007 Chapter 12 Sequence of Events XILINX The system pulses the PROG B pin Low
200. e interface between the FPGA and the source of configuration data The important steps in the bitstream loading process are as follows e Synchronization Array ID check e Loading configuration data e CRC check Each of these steps involves distinct parts of the configuration bitstream Spartan 3 Generation Configuration User Guide www xilinx com 229 UG332 v1 2 May 23 2007 Chapter 12 Sequence of Events XILINX Synchronization 6 7 8 Load Configuration Data 1 Wake from Clear 2 3 Configuration l Memory M 2 0 VS 2 0 Sample Control Startup CRC Check Sequence Reset power on or PROG_B Array ID Check Bitstream Loading Setup Finish UG332_c12_05_110406 a Start Figure 12 7 Synchronization Embedded at the beginning of an FPGA configuration bitstream is a special synchronization word The synchronization word alerts the FPGA to upcoming configuration data and aligns the configuration data with the internal configuration logic Any data on the configuration input pins prior to synchronization is ignored Because the synchronization word is automatically added by the Xilinx bitstream generation software this step is transparent in most applications The length and contents of the synchronization word differ between the Spartan 3A 3AN 3A DSP FPGA families and the Spartan 3 and Spartan 3E FPGA families as outlined in Table 12 3
201. e setup time on VS 2 0 All 50 variant select pins before the rising edge of INIT_B Notes 1 Spartan 3A represents the Spartan 3A Spartan 3AN and Spartan 3A DSP FPGA families Clear Configuration Memory Initialization Steps 1 3 4 5 l TIN Load Startu Reset Pins Synchronization Array 1D Configuration CRC Check Set mum power on or MI2 0 VS 2 0 j Shek 7 3 Data PROG B 6 7 8 Wake from Sample Control Bitstream Loading Start Finish UG332 c12 03 110406 Figure 12 5 Clear Configuration Memory Initialization Configuration memory is cleared automatically after the FPGA wakes from a reset event During this time I Os are placed in a high impedance Hi Z state except for the dedicated Configuration and JTAG pins The INIT B pin actively drives Low during initialization and then released after Tpog during a power up event or after Tp for other cases See Figure 12 4 If the INIT B pin is held Low externally the FPGA waits at this point in the initialization process until the pin is released The minimum Low pulse time for PROG B is defined by the Tppoc timing parameter The PROG B pin can be held active Low for as long as necessary 228 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Bitstream Loading Steps 4 7 Sample Control Pins Steps 1 2 4 5 6 7 8 Wake from
202. e socket connections appear in Figure 4 1 page 86 and Figure 4 2 page 87 along with a detail pinout table in Table 4 13 The mechanical dimensions are provided in Figure 9 6 page 193 and vendor part numbers provided in Table 9 5 page 193 As shown in Table 4 13 one side of the socket connects entirely to GND for better signal integrity The other side of the cable includes the Vggg voltage connection and the four SPI Flash control signals When used for SPI programming the programming cable behaves as an SPI Master controlling all transactions on the SPI bus 106 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Programming Support Table 4 13 Xilinx Download Header Signal Description for In System SPI Flash PROM Programming GND Socket Pin top view GND Direction Signal Connections to SPI PROM System Vrer Connect to 3 3V VCCO 2 which is common to the FPGA and SPI PROM The voltage reference must be regulated and must not have a current limiting series resistor Label VREF red SPI Slave Select Connect to the SPI PROM s Slave Select input Flying Lead Wire Color TMS PROG green GND GND GND SPI Clock Connect to the SPI PROM s Slave Clock input SPI Master Input Slave Output Connect to the SPI PROM s Slave Data Output SPI Master Output Slave Input Con
203. e sont uxkued cceterterd remi eR ae dac Redde edad 70 Daisy Chamed Configuration unisce eek eee PRICE EX dE do 70 Ganged or Broadside Configuration suse se eee eee 70 JTAG Interface oi oio isse e teense anes Ib E ERE RE Eder ad 72 Storing Additional User Data in Platform Flash susuusuue 72 Generating the Bitstream for a Master Serial Configuration 74 ConfigRate CCLK Frequency ssesessese Ie 74 StartupClk CCEK io ete teer eet be heii MWR edet ee etos 74 DriveDone Actively Drive DONE Pin 0 6 0 en 74 GTS_cycle Global Three State Release Timing for Daisy Chains 74 Preparing an Platform Flash PROM File s sues 75 IMPAC dienten tnt eh e dee Y eee ent ineunt dee nc A eee ig 75 Platform Flash In System Programming via JTAG using iMPACT 79 Prepare Board for Programming ss eh 79 Programming via iMPACT seseg ea mee yr eR da xx Ea Ex d Dea 80 Production Programmers 83 Additional Information i360 c isis ceed atid eis end eve ERE cede weed ea RE E V 83 Chapter 4 Master SPI Mode Master SPI Mode Differences between Spartan 3 Generation FPGA Families 88 Choosing a Compatible SPI Serial Flash 00 e eee eee 88 SPI Flash PROM Density Requirements 06666 c ccc 92 FPGA Connections to the SPIPROM sese 93 Voltage Compatibility iiss ich nb ti eed ke hc Cx ERR Ca 96 Power On P
204. e the set or reset inputs to key logic in Configurable Logic Blocks CLBs e Use a gating signal to disable key logic in Configurable Logic Blocks CLBs e Selectively disable CLB flip flops using the clock enable input e Any or all of the above The disadvantage of this approach is that it immediately tells an attacker whether an attempted breach was successful or not Limited Functionality Limited functionality provides partial or basic functionality This approach allows a 3rd party test house or contract manufacturers CM to build and test the unauthenticated systems This technique allows the CM to program the configuration PROM but does not provide them authentication capability eliminating the risk of potential overbuilding Disable key functions or special IP using one or more of the techniques described in No Functionality Optionally degrade the performance of key features For example drop to a lower communications data rate or a lower display resolution Spartan 3 Generation Configuration User Guide www xilinx com 287 UG332 v1 2 May 23 2007 Chapter 15 Protecting FPGA Designs XILINX Full Functionality with Time Out This technique allows an unauthenticated design to fully operate for a limited amount of time This approach is most useful when a 3rd party test house or contract manufacturer requires full functionality to complete system testing However this technique does not provide the contract manufac
205. e this output to maintain signal integrity See CCLK Design Considerations page 42 FPGA Pin Name Direction Description During Configuration After Configuration Spartan 3E Input User I O Pull Up Control When Drive at valid logic level User I O HSWAP Low during configuration throughout configuration Spartan 3A edm iud pte E g Spartan 3AN s pins aa ive an Spartan 3A DSP cco mput f PUDC B 0 Pull ups during configuration 1 No pull ups Spartan 3 HSWAP EN M 2 0 Input Mode Select Selects the FPGA M2 1 M1 1 M0 0 User I O configuration mode See Design Sampled when INIT_B goes Considerations for the HSWAP High M 2 0 and VS 2 0 Pins page 58 D 7 0 Input Data Input Byte wide data provided by User I O If bitstream host FPGA captures dataon option Persist Yes rising CCLK edge becomes part of SelectMap parallel peripheral interface Spartan 3 Output Busy Indicator Not required or If CCLK frequency is less than User I O If bitstream Spartan 3E used for Spartan 3A 3AN 3A 50 MEZ this pin may safely be option Persist Yes BUSY DSP FPGAs ignored When High indicates becomes part of that the FPGA is not ready to SelectMap parallel receive additional peripheral interface configuration data Host must hold data an additional clock cycle Spartan 3E Input Chip Select Input Active Low Must be Low during valid data User I O If bitstream Spartan 3A cycles option Persis
206. e unless loaded into an FPGA containing the correct key to decrypt the bitstream The encryption circuitry is typically a dedicated embedded function on the FPGA consuming valuable silicon area Applications that do not use encryption pay for the feature regardless Encryption is considered highly secure as implemented with battery back up on the Xilinx Virtex Virtex II Pro Virtex 4 and Virtex 5 FPGA families The built in encryption circuitry only protects the FPGA bitstream and is typically not available after configuration to protect application data The primary downside of encryption is key management and key distribution Authentication Authentication is another protection technique widely used in a variety of applications Authentication is distinctly different than using either security bits or encryption Here are a few examples of everyday applications using authentication e When you access an Automated Teller Machine ATM you insert your bank card and authenticate your identity by entering a Personal Identification Number PIN If someone steals your ATM card they cannot use it without also having your PIN number e When you log onto your computer network you enter your login name and your password The password authenticates your identity An imposter must have both your login name and your password to access the network from your account e Many software programs including the Xilinx ISE development software r
207. e while CSI B is asserted Low During a configuration ABORT the FPGA drives internal status information onto the D 7 4 pins over the next four CCLK cycles The other data pins D 3 0 remain High After the ABORT sequence finishes the processor that is downloading the FPGA must resynchronize the configuration logic before resuming configuration For applications that must deassert RDWR B between bytes use the method described in Pausing CCLK page 174 174 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX SelectMAP ABORT Configuration Abort Sequence Description An ABORT is signaled during configuration as shown in Figure 7 8 CSI B RDWR B para AA STATUS RK jj BUSY i i ABORT UG332 c7 08 081106 Figure 7 8 Configuration Abort Sequence The configuration sequence begins normally 2 The processor changes the value on the RDWR B pin while the FPGA is still selected CSI B is Low 3 BUSY goes High if CSI B remains asserted Low The FPGA drives the status word onto the data pins if RDWR B is High reading data from the FPGA The Status value is not presented by the FPGA if RDWR B is Low 4 The ABORT lasts for four clock cycles and Status is updated Readback Abort Sequence Description An ABORT is signaled during readback as shown in Figure 7 9 CSI B RDWR B DATAT me X i BUSY py f ABORT UG332 c7 09 0
208. ead write control input must be Low before the rising edge of INIT_B It is possible to delay the start of BPI mode configuration by controlling when CSI_B is asserted Low The CSI_B and RDWE_B pins are not used for Spartan 3A 3AN 3A DSP FPGAs 156 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Byte Peripheral Interface BPI Timing 3 The HSWAP or PUDC B pull up resistor control input must be setup and valid before the rising edge of INIT B Similarly the example in Figure 5 14 shows the pull up resistors enabled 4 The HSWAP or PUDC B control input defines the initial condition for the FPGA pins that control the Flash including LDC2 LDC1 LDC0 HDC and CSO B If HSWAP or PUDC B 1 then these pins are floating Hi Z If HSWAP or PUDC B 0 then these pins have an internal pull up resistor 5 After the FPGA completes its internal housecleaning and allows INIT B to go High the FPGA actively drives the Flash control outputs 6 TheFPGA begins driving the CCLK clock output which controls all the timing for BPI interface 7 The CCLK output begins operating at its lowest frequency option The ultimate frequency is controlled by a bitstream option called ConfigRate The FPGA generated address outputs are clocked by the falling edge of CCLK The initial address is held for five CCLK cycles in BPI Up mode and two CCLK cycles in BPI Down mode BPI Down mode is only available o
209. ecific pin Table 2 12 Pull Up Resistor during Configuration Control Input FPGA Family Pin Name Function Spartan 3A 3AN 3A DSP EPGA PUDC B 0 Pull up resistors enabled during configuration 1 No pull up resistors during configuration Pins Spartan 3E FPGA HSWAP that are not active during the configuration Spartan FPGA HSWAP EN Process float Hi Z The control pin itself has a pull up resistor enabled during configuration However the VCCO_0 supply voltage must be applied before the pull up resistor becomes active If the VCCO_0 supply ramps after the VCCO 2 power supply do not let the control input pin float tie the pin to the desired logic level externally Note that Spartan 3E step 0 silicon requires that VCCINT be applied before VCCAUX when using the internal pull up on HSWAP FPGA Pull Up Resistor Values The value of the dedicated and optional pull up resistors is specified as a current symbol Ipy in the respective Spartan 3 Generation data sheet The equivalent resistor values provided in Table 2 13 are for reference The pull up resistors on the Spartan 3 FPGA family are stronger than the other families Caution The pull up resistors in Spartan 3 FPGAs are strong especially at higher Veco voltages 48 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX General Configuration Control Pins Table 2 13 Pull Up Resistor Range
210. econfiguration and MultiBoot XILINX Table 14 1 MultiBoot Options on Spartan 3 Generation FPGA Families Spartan 3A 3AN Spartan 3A DSP Spartan 3 Spartan 3E More complex but also more capable Application complexity and flexible MultiBoot in BPI mode using parallel NOR Yes Flash MultiBoot in SPI mode using SPI serial Flash Yes MultiBoot from In System Flash memory Spartan 3AN only MultiBoot between different configuration Yes modes MultiBoot supports multi FPGA Yes configuration daisy chains How is MultiBoot triggered by FPGA Via command application sequence to ICAP MBT input on primitive JTAG STARTUP primitive interface Slave Serial or Slave Parallel SelectMAP interface Maximum number of MultiBoot Limited only by the configuration images 2 top and bottom of amount of parallel Flash configuration memory Bitstream start locations and addressing Ether at address 0 direction with incrementing Any byte location addresses or highest always with PROM address with incrementing decrementing addresses addresses Initial MultiBoot image location Controlled by MO mode pin 0 Address 0 Always at address 0 1 Highest PROM address Can FPGA application specify MultiBoot start No always top and address bottom of parallel Yes Flash Configuration watchdog timer automatically reconfigures FPGA starting at a
211. ed Low whilethe Low Error INIT B page 45 FPGA is clearing its configuration memory If a CRC error detected during configuration FPGA again drives INIT B Low DONE All Open drain FPGA Configuration Actively drives Low When High bidirec Done Low during during configuration indicates that the tionalI O configuration Goes High FPGA successfully when FPGA successfully configured completes configuration Powered by VCCAUX supply 0 FPGA not configured 1 FPGA configured See DONE Pin page 36 PROG B All Input Program FPGA Active Must be High during Drive PROG B Low Low When asserted Low configuration to allow and release to for 500 ns or longer forces configuration to start reprogram FPGA the FPGA to restart its configuration process by clearing configuration memory and resetting the DONE and INIT B pins If driving externally with a 3 3V output use an open drain or open collector driver or use a current limiting series resistor See Program or Reset FPGA PROG B page 39 Spartan 3E Master SPI Input Variant Select Instructs the Must be at the logic User I O Spartan 3A FPGA how to communicate levels shown in Spartan 3AN with the attached SPI Flash Table 4 2 page 89 Spartan 3A DSP PROM Sampled when INIT B FPGA goes High VS 2 0 Spartan 3E Master SPI Output Serial Data Output FPGA sends SPI Flash User I O Spartan 3A memory read commands and starting address to the PROM s serial data i
212. ent and with dedicated pull guarantee Vip LVCMOS15 lt 28kQ up resistors during LVCMOS12 lt 38kQ configuration B LVCMOS33 lt 32kQ lt 80kQ Pull Down LVTTL required to LVCMOS25 lt 70kQ overcome single load maximum Ij LVCMOS18 leakage current and lt 38 kQ guarantee Vg IVCMOSIS LVCMOS12 lt 59kQ Spartan 3 Generation Configuration User Guide www xilinx com 49 UG332 v1 2 May 23 2007 Chapter 2 Configuration Pins and Behavior during Configuration XILINX Pin Description Table 2 15 lists the various pins involved in the configuration process including which configuration mode the pin s direction and a summary description The table also describes how to use the pin during and after configuration Table 2 15 Spartan 3 Generation Configuration Pins Associated Modes and Function Config FPGA Pin Name Mode s Direction Description During Configuration After Configuration HSWAP All Input User I O Pull Up Control Drive at valid logic User I O or When Low during level throughout PUDC B configuration enables configuration pull up resistors in all I O d pins to respective I O bank HSWAP EN Vcco input depends on 0 Pull ups during FPGA family configuration 1 No pull ups M 2 0 All Input Mode Select Selects the Must be at the logic User I O dedicated FPGA configuration mode levels shown in on Spartan 3 FPGAs as defined in Table 2 1 Table 2 1 page 34 Sampled
213. entire configuration sequence is complete See Chapter 12 Sequence of Events for more information 60 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Design Considerations for the HSWAP M 2 0 and VS 2 0 Pins INIT B User I O I M 2 0 User I O I sea EE Master SPI i HSWAP User I O UG332 c2 04 111506 Figure 2 6 Stylized Configuration Waveforms Showing When Dual Purpose Pin Become Active Spartan 3 Generation Configuration User Guide www xilinx com 61 UG332 v1 2 May 23 2007 Chapter 2 Configuration Pins and Behavior during Configuration XILINX 62 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Chapter 3 Master Serial Mode The Master Serial configuration mode leverages the purpose designed Xilinx Platform Flash PROMs to configure Spartan 3 Generation FPGAs Master Serial mode uses the serial interface offered on XCFxxS serial PROMs and the serial interface option on XCFxxP serial parallel PROMs Xilinx Platform Flash PROMs offer the following system advantages e Simple interface Fewest number of FPGA pins used during configuration e Low cost per configuration bit e Highest bandwidth between PROM and FPGA for any serial PROM resulting in fastest configuration time e Small package footprint e In system programmable and reprogrammable via an i
214. ently the PROM s VCCJ supply input must also be 2 5V To create a 3 3V JTAG interface refer to XAPP453 The 3 3V Configuration of Spartan 3 FPGAs for additional information Storing Additional User Data in Platform Flash Typically there is some additional space leftover in the Platform Flash after storing the FPGA bitstream If desired the application can store additional data in the Platform Flash PROM and make it available to the FPGA after configuration The FPGA application does not have easy write access to the PROM but read access is relatively simple as described in the referenced application notes below For applications that also require easy write access consider using the Master SPI configuration interface described in Chapter 4 Master SPI Mode Use the available space in the Platform Flash PROM or even the next larger PROM size to hold additional nonvolatile application data such as MicroBlaze processor code or other user data such as serial numbers and Ethernet MAC IDs Using a MicroBlaze application as an example the FPGA configures from the Platform Flash PROM Then using FPGA logic after configuration the FPGA copies MicroBlaze code from Platform Flash into external DDR SDRAM for code execution providing simple and cost effective code shadowing 72 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Storing Additional User Data in Platform Flash Platform F
215. eprogram forces the FPGA to restart its FPGA Hold PROG B to configuration process by clearing force FPGA I O pins into configuration memory and resetting Hi Z allowing direct the DONE and INIT B pins once programming access to PROG B returns High SPI Flash PROM pins VCCO 2 Voltage Voltage Supply Input to I O 3 3V Ensure that either the 3 3V supply Bank 2 Supplies interface pins to VCCO 2 supply ramps input SPI Flash PROM faster than Vccqnt or VCCAUX or that the PROM wakes up sufficiently fast See Power On Precautions if System 3 3V Supply is Last in Sequence page 96 Voltage Compatibility Available SPI Flash PROMs use a single 3 3V supply voltage All of the FPGA s SPI Flash interface signals are within I O Bank 2 Consequently the FPGA s VCCO 2 supply voltage must also be 3 3V to match the SPI Flash PROM Also see Power On Precautions if System 3 3V Supply is Last in Sequence page 96 See also JTAG Cable Voltage Compatibility page 184 Power On Precautions if System 3 3V Supply is Last in Sequence Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs have a built in power on reset POR circuit The FPGA waits for its three power supplies Vccinp Vecaux and Veco to I O Bank 2 VCCO_2 to reach their respective power on thresholds before beginning the configuration process See Power On Reset POR page 226 for more information The SPI Flash PROM is powered by the same voltage supply fee
216. equire an authorization code before they operate on your computer You can freely copy the DVD but it can only be used when unlocked by the authorization code To be ideally effective authentication requires an identity or authorization code with these two essential attributes 1 Unique 2 Noteasily cloned copied or duplicated Spartan 3 Generation Configuration User Guide www xilinx com 277 UG332 v1 2 May 23 2007 Chapter 15 Protecting FPGA Designs XILINX Weaknesses in either of these elements potentially compromise security For example if someone has your ATM card and your PIN number kiss your cash goodbye The PIN number once learned is easily cloned This is one of the reasons behind the move to biometric authentication While it is easy to learn a simple PIN number it is presently quite difficult to clone a human iris or a fingerprint Spartan 3A 3AN 3A DSP Unique Device Identifier Device DNA Each Spartan 3A Spartan 3AN and Spartan 3A DSP FPGA contains an embedded unique device identifier The identifier is nonvolatile permanently programmed into the FPGA and is unchangeable making it tamper resistant This identifier is called the Device DNA The FPGA application accesses the identifier value using the Device DNA Access Port DNA PORT design primitive shown in Figure 15 3 DNA PORT UG332 C13 05 081406 Figure 15 3 Spartan 3A 3AN 3A DSP DNA PORT Design Primitive Identifier Value
217. er continues until one of the following events occurs Upon any one of these events the CRC checker stops operating e The configuration controller receives a valid synchronization word which can occur if the FPGA is being reconfigured or from a MultiBoot operation e There is an active configuration operation via the JTAG port e The FPGA enters the power saving Suspend mode If enabled in the bitstream the CRC checker will reset and restart at the end of the configuration event or when the FPGA awakens from Suspend mode Clock Source If enabled the post configuration CRC checker is clocked by one of three sources depending on the specific FPGA application ordered from least likely to most likely e Ifthe bitstream option Persist Yes is selected and the FPGA is configured using one of the Slave configuration modes then the post configuration CRC checker is clocked using the FPGA s CCLK input pin e If the Internal Configuration Access Port ICAP feature is enabled the post configuration CRC checker is clocked by the CLK input on the ICAP design primitive e Otherwise the post configuration CRC checker is clocked by the FPGA s internal oscillator Set the frequency of the internal oscillator using the POST_CRC_FREQ configuration constraint See Table 16 1 for available options CRC Checking Time The time required for each CRC calculation is similar to the serial configuration time and depends on the density and clock
218. eration Summary fel Ed You have entered following information PROM Type Parallel File Format mcs Fill Value FF PROM filename Untitled Number of PROMs 1 Cancel UG332 c14 07 112906 Figure 14 6 Confirm the PROM Settings 15 As shown in Figure 14 7 start selecting the FPGA configuration bitstream for the design that initially loads at power up or when the PROG B input is pulsed Low Initial Boot Bitstream Start adding device File to My Recent Documents Desktop L x CE File name first multiboot image bit Places Files of type FPGA Bit Files bit UG332 c14 08 081906 Figure 14 7 Select the First MultiBoot Configuration Image 16 Using the file selection mechanism for your operating system choose the initial bitstream This bitstream is loaded at the initial PROM location specified in Step 9 17 Click Open Spartan 3 Generation Configuration User Guide www xilinx com 253 UG332 v1 2 May 23 2007 Chapter 14 Reconfiguration and MultiBoot XILINX 18 As shown in Figure 14 8 the iMPACT software then prompts for the second MultiBoot configuration image p Now adding the Second Bi My Recent Documents Desktop My Network Fi Places Ci You have completed the device file entry i Click Ok to continue UG332_c14_09_082006 Figure 14 8 Select the Second MultiBoot Configuration Image 19 Select the bit file for the second i
219. ere are two ways to set the security level in the bitstream either from the ISE Project Navigator or from the BitGen command line utility ISE Project Navigator Set the security level in the FPGA bitstream as shown in Figure 15 1 274 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Basic FPGA Hardware Level Security Options Ep Generate PROM ACE iE Configure Device iMP Ep Rerun All Rerun UG332_c1_04_120306 Figure 15 1 Setting Bitstream Generator Options from ISE Project Navigator 1 Right click Generate Programming File 2 Select Properties From the Process Properties dialog box shown in Figure 15 2 set the following options E Process Properties xi Category t General Options RN Options Create ReadBack Data Files Enable Readback and Reconfiguration Allow SelectMAP Pins to Persist Disable Readback Disable Readback and ene POMA Security Enable Readback and Reconfiguration Y ana Create Logic Allocation File Create Mask File UG332_c16_07_0918 Figure 15 2 Bitstream Generator Security Options 3 Select the Readback Options category 4 Choose the Security level value that best meets the needs of the application Spartan 3 Generation Configuration User Guide www xilinx com 275 UG332 v1 2 May 23 2007 Chapter 15 Protecting FPGA Designs XILINX Table 15 3 Relation between ISE Project Navigator
220. es the bitstream instructs the FPGA to enter the Startup sequence The Startup sequence is controlled by an 8 phase phases 0 7 sequential state machine The startup sequencer performs the tasks outlined in Table 12 6 Table 12 6 User Selectable Cycle of Startup Events BitGen Startup Event Phase Control Wait for DCMs to Lock optional 1 6 LCK cycle Spartan 3 FPGA family only Wait for DCI to Match optional 1 6 Match cycle Assert Global Write Enable GWE allowing RAMs and flip flops to change state 1 6 GWE_cycle Release the Global 3 State GTS activating I O 1 6 GTS_cycle Release DONE pin 1 6 DONE cycle End Of Startup EOS 7 N A Spartan 3 Generation Configuration User Guide www xilinx com 233 UG332 v1 2 May 23 2007 Chapter 12 Sequence of Events XILINX The specific order of startup events except for the End of Startup EOS is user programmable through various bitstream generator options Table 12 7 and Figure 12 12 page 235 show the general sequence of events although the specific phase for each of these startup events is user programmable EOS is always the last phase By default startup events occur as shown in Table 12 7 Table 12 7 Default BitGen Sequence of Startup Events Default BitGen Setting Control Phase Event DONE cycle 4 Release DONE pin indicating that the FPGA successfully completed configuration GTS_cycle 5 Release the global three st
221. esent status by actively driving the AWAKE output 222 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Table 11 2 Spartan 3 Generation Bitstream Generator BitGen Options Continued Pins Function Values Option Name Affected default Description suspend filter Spartan 3A Yes Default Enables the glitch filter on the SUSPEND pin Spartan 3AN isables the elitch fi Spartan 3A DSP No Disables the glitch filter on the SUSPEND pin FPGA only Suspend mode SUSPEND pin en_sw_gsr Spartan 3A No Default The state of all clocked elements in the FPGA is Spartan 3AN preserved during Suspend mode Spartan 3A DSP FPGA only Yes During wake up from Suspend mode the FPGA pulses the GlobalSet Reset GSR signal setting or resetting all clocked Suspend mode elements as originally specified in the FPGA application All wake up timing state information prior to entering Suspend mode is lost sw clk Spartan 3A StartupClk Default Uses the clock defined by the StartupClk bitstream Spartan 3AN Spartan 3A DSP setting to control the Suspend wake up timing InternalClk Uses the internally generated 50 MHz oscillator to control FPGA only AU theSuspend wake up timing The clock frequency is the same Suspend mode as when ConfigRate 50 as described in the FPGA data sheet wake up timing sw gwe cycle Spartan 3A 1 5 1024 After the AWAKE pin i
222. face has a separate JTAG command to initiate configuration The PROG_B pin also forces a master reset on the FPGA e The configuration clock pin CCLK defines the timing for the FPGA s configuration process If the M 2 0 mode select pins define a Master mode then the FPGA internally generates CCLK If the M 2 0 mode select pins define a Slave mode then CCLK is an input to the FPGA from an external timing reference e The INIT_B pins performs multiple functions At the start of configuration INIT B goes Low indicating that the FPGA is clearing its internal configuration memory a process called housecleaning Later when the FPGA is actively loading its configuration bitstream INIT B goes Low if the bitstream fails its CRC check On Spartan 3A 3AN 3A DSP FPGAs if so enabled in the FPGA application the INIT B pin also potentially signals a post configuration CRC error e During configuration some pins have built in pull up resistors The remaining pins each have an optional pull up resistor controlled by a single control input pin This pin has different names on different architectures as shown in Table 2 12 Spartan 3 Generation Configuration User Guide www xilinx com 33 UG332 v1 2 May 23 2007 Chapter 2 Configuration Pins and Behavior during Configuration XILINX Choose a Configuration Mode M 2 0 The mode select pins M 2 0 define the configuration mode that the FPGA uses to load its bitstream as shown in T
223. fault Internally connects a pull up resistor between the only Spartan 3 HSWAP EN pin and VccAux HSWAP EN pin Pulldown Internally connects a pull down resistor between the Spartan 3 HSWAP EN pin and GND Pullnone No internal pull up resistor on the Spartan 3 HSWAP EN pin CclkPin Spartan 3 FPGA Pullup Default Internally connects a pull up resistor or between only CCLK pin and VCCAUX CCLK pin Pullnone CCLK pin is high impedance floating Define CCLK logic level externally M2Pin Spartan 3 FPGA Pullup Default Internally connects a pull up resistor or between M2 only mode select pin and VccAUx M2 pin Pulldown Internally connects a pull down resistor or between M2 mode select pin and GND Pullnone M2 pin is high impedance floating Define M2 logic level externally Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 219 Chapter 11 Configuration Bitstream Generator BitGen Settings XILINX Table 11 2 Spartan 3 Generation Bitstream Generator BitGen Options Continued Option Name M1Pin Pins Function Affected Spartan 3 FPGA only M1 pin Values default Pullup Description Default Internally connects a pull up resistor or between M1 mode select pin and VccAux Pulldown Internally connects a pull down resistor or between M1 mode select pin and GND Pullnone M1 pin is high impedance floating Define M1 logic leve
224. figRate setting TCCLKLn minus the FPGA s setup time on the DIN input TDCC See the Ty parameter highlighted in Figure 4 29 page 124 All communication from the FPGA to the SPI Flash PROM i e sending the read command address and dummy bits all occurs at the default slowest CCLK ConfigRate setting TCCLK1 which equates to approximately 1 MHz Table 4 16 Configuration Timing Requirements for Attached SPI Serial Flash Symbol Description Requirement Units T SPI serial Flash PROM chip select time ns x j Tees Twccri 7 Peco T SPI serial Flash PROM data input setup time ns iid precum TpsuS Tuccii Tcco TpH SPI serial Flash PROM data input hold time ns Tpu S Tuccm Ty SPI serial Flash PROM data clock to output time ns Tv S Twccis Tpcc fcorfg Maximum SPI serial Flash PROM clock frequency also 1 MHz depends on specific read command used c2 T CCLKn min Notes 1 These requirements are for successful FPGA configuration in SPI mode where the FPGA provides the CCLK frequency The post configuration requirements may be different depending on the application loaded into the FPGA and the resulting clock source 2 Subtract additional printed circuit board routing delay as required by the application Multi Package Layout Most of the SPI PROM vendors have a multi package migration scheme that allows a design to migrate to larger or smaller memory densities The multi package layout prov
225. fter the FPGA completes configuration this example FPGA application performs a board level or system test using FPGA logic If the test is successful the FPGA then triggers a MultiBoot event causing the FPGA to reconfigure from the opposite end of the Flash PROM memory in this case starting at address OxFFFF The FPGA actually starts at address OxF FFFF but the upper four address bits A 23 20 are not connected to the PROM in this example The FPGA addresses the second configuration image which in this example contains the FPGA application for normal operation Similarly the second FPGA application could trigger another MultiBoot event at any time to reload the diagnostics design from address 0 and so on 1Mbyte Parallel PROM 1Mbyte Parallel PROM OxFFFFF OxFFFFF General General FPGA FPGA Application STARTUP_SPARTAN3E Application MultiBoot Trigger GSR pulse from User Area application GTS User Area l MBT gt 300 ns CLK Diagnostics Diagnostics FPGA Reconfigure FPGA Application Application 0 0 First Configuration Second Configuration DS332 c14 01 082006 Figure 14 1 Example Spartan 3E MultiBoot Application using 1Mbyte Parallel Flash PROM In another potential application the initial design loaded into the FPGA image contains a golden or fail safe configuration image which then communicates with the outside world and checks for a newer FPGA configuration image If there is a new configuration revisio
226. fully supported by iMPACT the Xilinx JTAG based programming software 18 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Design Considerations Is the lowest cost solution the more important consideration For cost sensitive applications obviously the lowest cost configuration solution is best However which option is lowest cost The answer depends on your specific application e Is there spare nonvolatile memory already available in the system in which to store the FPGA configuration bitstream s The bitstream image can be stored in system memory stored on a hard drive or even downloaded remotely over a network connection If so consider one of the downloaded modes Master Parallel Mode Slave Serial Mode or JTAG Configuration Mode and Boundary Scan e Is there a way to consolidate the nonvolatile memory required in the application For example can the FPGA configuration bitstream s be stored with any processor code for the board If the processor is a MicroBlaze soft processor core embedded in the FPGA the FPGA configuration data and the MicroBlaze code can easily share the same nonvolatile memory device e Spartan 3A and Spartan 3E FPGAs optionally configure from commodity SPI serial Flash and parallel NOR Flash memories Because these memories have common footprints and multiple suppliers they may have lower pricing due to the highly competitive marketplace I
227. function If the FPGA configures in one of the Master modes and if the Reset_on_err Yes bitstream option is set then the Spartan 3A 3AN 3A DSP FPGA automatically re initializes itself and attempts to reconfigure if a CRC error occurs during configuration In BPI and SPI modes if reconfiguration fails three times then the FPGA halts and drives the INIT_B pin Low The CCLK output goes to the high impedance state Hi Z unless the HSWAP or HSWAP EN pin is Low in which case the CCLK output is pulled High Pulsing the PROG B pin or power cycling restarts the configuration process from the beginning The JTAG interface remains responsive and the device is still alive only the BPI SPI interface is inoperable The counter that keeps track of the three failed configurations is reset only when PROG B is pulsed or power is cycled it is not reset after a successful configuration Note that when configuring via SPI or BPI modes and using the Reset on err Yes bitstream option any combination of successful and failed configurations over any period of time will halt after the third failed configuration and require assertion of PROG_B or power cycling to reconfigure It is good design practice to have the ability to assert PROG B to reset configuration if necessary Robust CMOS Configuration Latches CCLs FPGA configuration data is stored in robust CMOS configuration latches CCLs Despite being readable and writable like static RAM SRAM CCLs are des
228. g FPGA Designs for additional information Spartan 3 Generation Configuration User Guide www xilinx com 245 UG332 v1 2 May 23 2007 Chapter 13 Configuration Related Design Primitives XILINX Usage The DNA PORT component must be instantiated in order to be used in a design To do so use the instantiation template found within the ISE Project Navigator HDL Templates and place this instance declaration within the code Connect all inputs and outputs to the design in order to ensure proper operation In order to access the Device DNA data the shift register must first be loaded by setting the active high READ signal for one clock cycle After the shift register is loaded the data may be synchronously shifted out by enabling the active high SHIFT input and capturing the data out the DOUT output port If desired additional data may be appended to the end of the 57 bit shift register by connecting the appropriate logic to the DIN port If DNA data rollover is desired connect the DOUT port directly to the DIN port to allow for the same data to be shifted out after completing the 57 bit shift operation If no additional data is necessary the DIN port may be tied to a logic zero The attribute SIM DNA VALUE may be optionally set to allow for simulation of a possible DNA data sequence By default the Device DNA data bits are all zeros in the simulation model See Operation page 278 for additional information Port De
229. g Timer CWDT and Fallback page 270 Spartan 3 Generation Configuration User Guide www xilinx com UG332 v1 2 May 23 2007 Table of Contents Chapter 1 Overview and Design Considerations Design Considerations c2ssesiisoetebageed DRE RERO RI er ande d 11 Where to go for debuggingsupport seseeeeee I 23 FPGA Configuration Bitstream Sizes u nusanusa nner cece eee 24 Uncompressed Bitstream Image Size 6 6 een eee 24 Bitstream Format ss scsc60 56s eo nerio pa U pere a ed eee pee te eee Hace eal 24 Synchronization Word ie ccocepigusr sees RIA eaei IAN RE eee EAS ceeds 25 Aray ID secari Emm 25 Data Eranies sorori vivid ee REVERSE Reise e hee ba eee Sd 25 CRC rcr EEA Ner E oe E E AE O EEE Ea 26 Bitstream Compression yss siesesesa etea inaia aa baaa nnn 26 Packet Format iik usa RE ERE C RR RES REPE REL RR EE 27 Setting Bitstream Options Generating an FPGA Bitstream 27 ISE Project Navigator isses rne eed er REDE ERR e i bae as 28 BitGen Command Line Utility 0 0 6 nnn eee 32 Chapter 2 Configuration Pins and Behavior during Configuration General Configuration Control Pins uuu 33 Choose a Configuration Mode M 2 0 ssssssssss nannan 34 M 2 0 Functional Differences between Spartan 3 Generation Families 34 Spartan 3A 3AN 3A DSP and Spartan 3E FPGA Families esee 35 Spartan FPGA Family i919 iouis un eee he
230. g the comparison against the precomputed CRC HALT If a CRC mismatch is detected cease CRC check 296 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Post Configuration CRC Spartan 3A 3AN 3A DSP Only Bitstream Generator Options Table 16 2 lists the bitstream generator BitGen options associated with the post configuration CRC feature The shaded fields are hidden because the CONFIG constraints are the preferred control mechanism as described in Preparing an Application to Use the Post Configuration CRC Feature page 295 The glutmask option has no associated CONFIG constraint Table 16 2 Post Configuration CRC Bitstream Generator Options Setting BitGen Option default Description glutmask Default Mask out the Look Up Table LUT bits from the SLICEM logic slices SLICEMs support writable Yes functions such as distributed RAM and SRL16 shift registers which generate CRC errors when bit locations are modified Include the Look Up Table LUT bits from SLICEM logic slices Use this option only if the application does not include any distributed RAM or SRL16 shift registers Design Considerations While all flip flop and latch values are automatically ignored the initial values for each flip flop and latch are included in the CRC calculation Consequently do not issue a Readback CAPTURE operation when the post configu
231. gRate CCLK Frequency Set the ConfigRate option as described in CCLK Frequency page 138 Using ISE Project Navigator the Configuration Rate frequency is set in Step 7 in Figure 1 7 page 29 g ConfigRate 12 StartupClk CCLK By default the configuration Startup clock source is the internally generated CCLK Keep the StartupClk bitstream generation option shown as Step 13 in Figure 1 8 page 30 g StartupClk Cclk DriveDone Actively Drive DONE Pin In a single FPGA design or for the Master FPGA in a multi FPGA daisy chain set the FPGA to actively drive the DONE pin after successfully completing the configuration process Using ISE Project Navigator check the Drive Done Pin High option shown as Step 16 in Figure 1 8 page 30 g DriveDone Yes GTS_cycle Global Three State Release Timing for Daisy Chains If creating a multi FPGA daisy chain set the GTS cycle option to be later than the DONE cycle setting which is the default setting for both Alternatively set GTS cycle Done From ISE Project Navigator the GTS cycle setting is the Enable Outputs Output Events option shown as Step 14 in Figure 1 8 page 30 Preparing an Parallel NOR Flash PROM File This section provides guidelines to create PROM files for parallel NOR Flash memories The Xilinx software tools iMPACT or PROMGen generate formatted PROM files from the FPGA bitstream or bitstreams IMPACT The following steps graphically describe how to c
232. ge of CLK 0 5 ns tpnapsu__ Setup time on DIN before the rising edge of CLK 1 0 ns tpnNapH__ Hold time on DIN after the rising edge of CLK 0 5 ns tpNAmsu Setup time on READ before the rising edge of CLK 5 0 10 000 ns tDNARH Hold time on READ after the rising edge of CLK 0 ns Spartan 3 Generation Configuration User Guide www xilinx com 279 UG332 v1 2 May 23 2007 Chapter 15 Protecting FPGA Designs XILINX Table 15 6 DNA_PORT Interface Timing Continued Symbol Description Min Max Unit dM delay on DOUT after rising edge 05 15 tpuNAcLKkr CLK frequency 0 100 MHz tDNACLKL CLK High time 1 0 oo ns tDNACLKH CLK Low time 1 0 co ns Identifier Memory Specifications Figure 15 4 presents the general characteristics of the DNA identifier memory The unique FPGA identifier value is retained for a minimum of ten years of continuous usage under worst case recommended operating conditions The identifier can be read using the READ operation defined in Table 15 5 a minimum of 30 million cycles which roughly correlates to one read operation every 11 seconds for the minimum lifetime of the Spartan 3A 3AN 3A DSP FPGA Table 15 7 dentifier Memory Characteristics Symbol Description Minimum Units DNA RETENTION Data retention continuous usage 10 Years DNA CYCLES Number of READ operations as defined in Figure 15 3 or JTAG ISC DNA read operations Unaffected by HOLD or SHIFT
233. gisters then leave the glutmask bitstream generator option at its default value Spartan 3 Generation Configuration User Guide www xilinx com 295 UG332 v1 2 May 23 2007 Chapter 16 Configuration CRC XILINX Example User Constraints File UCF Figure 16 2 provides an example user constraints file to enable the post configuration CRC checker Enable the post configuration CRC checker CONFIG POST_CRC ENABLE Set clock frequency for CRC checker circuitry CONFIG POST_CRC_FREQ 1 Define if the CRC checker continues or halts after detecting an error CONFIG POST_CRC_ACTION CONTINUE Figure 16 2 UCF Constraints for Post Configuration CRC CONFIG Constraints Table 16 1 lists the available CONFIG constraints that control the post configuration CRC feature Table 16 1 Post Configuration CRC CONFIG Constraints CONFIG Constraint Setting Description POST_CRC Default Disable the post configuration CRC PRATU checker INIT B pin is available as a user I O pin Enable the post configuration CRC checker ENABLE INIT B pin is reserved to flag CRC errors and not available as a user I O pin POST CRC FREO 1 3 6 7 8 10 12 Default value is 1 Sets the clock frequency used 18 17 22 25 27 for the post configuration CRC checker 33 44 50 100 POST CRC ACTION CONTINUE Default If a CRC mismatch is detected continue reading back the bitstream computing the comparison CRC and makin
234. gle FPGA design or for the Master FPGA in a multi FPGA daisy chain set the FPGA to actively drive the DONE pin after successfully completing the configuration process Using ISE Project Navigator check the Drive Done Pin High option shown as Step 16 in Figure 1 8 page 30 g DriveDone Yes GTS cycle Global Three State Release Timing for Daisy Chains If creating a multi FPGA daisy chain set the GTS cycle option to be later than the DONE cycle setting which is the default setting for both Alternatively set GTS cycle Done From ISE Project Navigator the GTS cycle setting is the Enable Outputs Output Events option shown as Step 14 in Figure 1 8 page 30 74 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Preparing an Platform Flash PROM File Preparing an Platform Flash PROM File This section provides guidelines to create PROM files for Platform Flash PROM memories The Xilinx software tools iMPACT or PROMGen generate PROM files from the FPGA bitstream or bitstreams IMPACT The following steps graphically describe how to create a PROM file using iMPACT from within the ISE Project Navigator 1 From within the ISE Project Navigator double click Generate PROM ACE or JTAG File from within the Process pane as shown in Figure 3 7 Processes E JC Generate Programming File P A Processes UG332_c4_10_110206 Figure 3 7 Double click Generate PROM
235. gnsS3E Simple default ipf Boundary Scan z Fie Edit View Operations Options Output Debug Window Help le El amp amp BB X as Xx zz IP H B2 Boundary Scan H Ba SlaveSerial H S9SelectMAP H Ba Desktop Configu xc3s500e xcf ds xc2c54a file file file H BS Direct SPI Config IMPACT Modes UG332_c9_xx_112006 Figure 9 9 iMPACT Automatically Detects Devices on the JTAG Chain 6 As shown in Figure 9 10 the iMPACT software automatically prompts for the FPGA bitstream Select the desired bitstream to download specifically to the FPGA 7 Click Open Spartan 3 Generation Configuration User Guide www xilinx com 195 UG332 v1 2 May 23 2007 Chapter 9 JTAG Configuration Mode and Boundary Scan XILINX Assign New Configuration File 2f x File name M yFPGA bit Open File type All Design Files bit rbt nky isc bsd Cancel Cancel All Bypass L UGS332 c9 09 112006 Figure 9 10 iMPACT Prompts for FPGA Bitstream 8 As shown in Figure 9 11 the iMPACT software automatically detects that the FPGA bitstream was generated for a non JTAG configuration method The iMPACT software automatically adjusts the Startup clock setting for successful JTAG configuration StartupClk JtagClk The original bitstream file is unaffected WARNING iMPACT 2257 Startup Clock has been changed to JtagClk in the bitstream stored
236. greed tee eatp ectetuer aes os 227 Clear Configuration Memory Initialization 0 0 228 Sample Control PINS ions esee ser testa eppen p Rer e a hne dieta 229 Delaying Configuration sssssseeessess ee 229 Bitstream Loading Steps 4 7 229 Synchronization sessi ian be ceed eee be RR ERG Sed PG ERE CER Ed aded a 230 Check Array ID 2250 zseeckeRec Rh e t ere RE ed RE Ra dU PER DRE riv 230 Load Configuration Data Frames sssssseesesee e 232 Cyclic Red ndancy Check electa RR e y e pre eds 233 Start p C 233 Startup Clock Source is csi a he etr b a ty a Ry eR Ya rr a ad Rod d 235 Waiting for DCMs to Lock DCI to Match 6 6 eee eee 235 Chapter 13 Configuration Related Design Primitives Boundary Scan BSCAN 0 00 e nee 239 Usap ras erste tate dieses eh Sa oe ole uot ee ile Ape iia ate Te tr BA hae We Ds 240 Port Descriptions 22 35 4c4S aes eced Heese h eins Hees hie Meio aa kis dias a 240 Start Up STARTUP oko Ve EE be ERE ERAS E REY ve diner RES C XR VERAS EARS 241 IUSage rie akida tyik khh aat o dnte abd Je balding debe bind sien e ae R dris 242 Port Descriptions si e Lee be es e Cl de EAD ERR eg 242 Readback Capture CAPTURE eek eet EUR ER ERR EHEREKTERSE VERE sities 242 SABC ooo bie ee ebd eddie i Fase ied cde duci aee ue d ddl 243 Port Descriptioti l i Leere ete ek ere x era he e eed qa 243 Attributes nener ees LR eene Rice get ods
237. gure 4 5 the FPGA configures from SPI Flash PROM Then using FPGA logic after configuration the FPGA copies MicroBlaze code from SPI Flash into external DDR SDRAM for code Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 101 Chapter 4 Master SPI Mode XILINX execution Similarly the FPGA application can store nonvolatile application data within the SPI Flash PROM The FPGA configuration image or initial configuration image for a Spartan 3A 3AN 3A DSP MultiBoot application is always stored at starting address 0 Store any additional data beginning in the next available SPI Flash PROM sector or page Do not mix configuration data and user data in the same sector or page After configuration the FPGA application can exploit any special features of the attached SPI serial Flash PROM For example the Atmel AT45DB series PROMs support a slightly modified serial interface called Rapid S The FPGA cannot configure using this mode but after configuration the FPGA application can use Rapid S to increase overall data throughput Similarly the NexFlash Winbond W25X series PROMs support a feature called Dual Output SPI that transmits two data bits per clock cycle but requires a special read command The FPGA does not support this command for configuration but the FPGA application can issue the command after configuration Accessing other SPl compatible Peripherals Similarly the SPI bus ca
238. h Figure 16 3 shows a block RAM example the same technique applies for distributed RAM Similarly both block RAM and distributed RAM support dual port read operations The parity checker function can be moved to the second read port so that it can continuously monitor the RAM contents without affecting normal operation Similarly if the block RAM contents are static if used to store PicoBlaze code as an example then FPGA logic can use the second block RAM port and continuously calculate a CRC signature for the block RAM contents If the signature changes between subsequent checking operations then the circuit flags an error This is similar to the method used to continuously check the FPGA configuration memory cells 298 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007
239. h the SPI Flash PROM as shown in Figure 4 5 SPI Flash PROMs offer random accessible byte addressable read write nonvolatile storage to the FPGA application Caution Allow the FPGA configuration logic to use the CCLK pin to complete configuration and startup before using it to control the SPI Flash interface Although most dual purpose pins become I O at the GTS cycle CCLK must wait until the End of Startup EOS Delay access by a couple clock cycles after configuration to avoid conflicts See Startup in Chapter 12 100 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX SPI Flash Interface after Configuration Spartan 3E 3A 3AN 3A DSP FPGA 3laze MOSI FPGA based p SPI Master DIN CCLK CSO B User I O DDR SDRAM Micrc To other SPI slave peripherals YAY SPI Serial Flash PROM FFFFF DATA IN E DATA_OUT MicroBlaze Code CLOCK SELECT FPGA Configuration SPI Peripherals A D Converter DATA IN D A Converter DATA OUT CAN Controller m Displays CLOCK Temperature Sensor SELECT ASSP ASIC UG332 c4 09 040107 Figure 4 5 Using the SPI Flash Interface After Configuration SPI Master Interface using FPGA Logic The FPGA does not contain a dedicated SPI interface except for configuration Consequently to access the SPI Flash or other SPI devices after configuration the FPGA application mu
240. hat require 8 Mbit PROMs use either a single 8 Mbit XCF08P parallel serial PROM or two cascaded XCFxxG serial Spartan 3 Generation Configuration User Guide www xilinx com 69 UG332 v1 2 May 23 2007 XILINX Chapter 3 Master Serial Mode PROMs as listed in Table 3 4 The two XCFxxS PROMs have a 3 3V Vecint supply while the XCF08P requires a 1 8V Vcc nr supply If the board does not already have a 1 8V supply available the two cascaded XCFxxS PROM solution is recommended CCLK Frequency In Master Serial mode the FPGA s internal oscillator generates the configuration clock frequency The FPGA provides this clock on its CCLK output pin driving the PROM s CLK input pin The FPGA starts configuration at its lowest frequency and increases its frequency for the remainder of the configuration process if so specified in the configuration bitstream The maximum frequency is specified using the ConfigRate bitstream generator option Table 3 5 shows the maximum ConfigRate settings approximately equal to the frequency measured in MHz for various Platform Flash PROMs and I O voltages These values are determined using the minimum CCLK period from the appropriate Spartan 3E or Spartan 3A 3AN 3A DSP data sheet The maximum ConfigRate for the serial XCFxxS PROMs is reduced at 1 8V Spartan 3A 3AN 3A DSP FPGAs do not support a 1 8V configuration interface due to their higher VCCO_2 Power On Reset voltage threshold See Power On Reset P
241. he FPGA s configuration banks For example the SPI or BPI modes leverage third party Flash memory components that are usually 3 3V only devices This then requires that the I O voltage on the bank or banks attached to the memory also be 3 3V In most applications this is not an issue However if a voltage other than 3 3V is required specifically 2 5V consider using a Xilinx Platform Flash PROM which supports a range of output voltages via a separate supply on the Platform Flash PROM Will the FPGA application need to store nonvolatile data Some FPGA applications store data in external nonvolatile memory Spartan 3E or Spartan 3A 3A DSP FPGAs provide some useful enhancements for these applications e Spartan 3E and Spartan 3A 3A DSP FPGAs can configure directly from external commodity serial or parallel Flash PROMs e The Flash PROM address data and control pins are only borrowed by the FPGA during configuration After configuration the FPGA has full read write control over these pins e The FPGA configuration bitstreams and the application s nonvolatile data can share the same PROM reducing overall system cost See Chapter 4 Master SPI Mode or Chapter 5 Master BPI Mode for additional information 20 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Design Considerations Should the FPGA I O pins be pulled High via resistors during configuration Some
242. he internal reset and the FPGA can continue with the configuration process unless the PROG_B pin is Low 226 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Setup for Configuration Steps 1 3 Table 12 1 Power On Reset Threshold Voltages Spartan 3A 3AN Spartan 3A DSP FPGA 3E FPGA 3 FPGA POR Threshold G Spartan 3 G Spartan 3 FPG Voltage Supply Specification Min Max Min Max Min Max Units VCCINT VCCINTT 0 4 1 0 0 4 1 0 0 4 1 0 V VCCAUX VCCAUXT 0 8 2 0 0 8 2 0 0 8 2 0 V VCCO 2 Vccoor 0 8 2 0 0 4 1 0 V VCCO 4 or VCCO BOTTOM Vccoar Ue n M VccrNr Should rise monotonically within the specified ramp rate If this is not possible delay configuration by holding the INIT B pin or the PROG B pin Low see Delaying Configuration page 229 while the system power supplies reach the required POR threshold After successfully configuring the POR circuit continues to monitor the VccmT and Vecaux Supply inputs Should either supply drop below the its associated threshold voltage the POR circuit again resets the FPGA PROG B Pin The PROG B resets the FPGA regardless of the current state of the FPGA For additional information see Program or Reset FPGA PROG B page 39 Power Up Timing Figure 12 4 shows the general power up timing showing the relationship between the input voltage supplies the INIT B pin and the PROG B pin
243. hen Drive at valid logic level User I O PUDC B Low during configuration enables throughout configuration P pull up resistors in all I O pins to respective I O bank Vcco input See Pull Up Resistors During Configuration page 46 0 Pull ups during configuration 1 No pull ups M 2 0 Input Mode Select Selects the FPGA M2 0 M1 0 MO 1 User I O configuration mode Spartan Sampled when INIT_B goes 3A 3AN 3A DSP FPGAs have High Spartan 3A 3AN 3A dedicated internal pull up resistors DSP FPGAs have internal on these pins See Choose a pull up resistors to VCCO_2 Configuration Mode M 2 0 page 34 VS 2 0 Input Variant Select Instructs the FPGA Must be at the logic levels User I O how to communicate with the shown in Table 4 2 Sampled attached SPI Flash PROM Spartan when INIT_B goes High 3A 3AN 3A DSP FPGAs have Spartan 3A 3AN 3A DSP dedicated internal pull up resistors FPGAs have internal pull up on these pins resistors to VCCO_2 MOSI Output Master SPI Serial Data Output FPGA sends SPI Flash User I O Connect to the SPI Flash PROM s memory read commands and Slave Data Input pin starting address to the PRONM s serial data input DIN Input Master SPI Serial Data Input FPGA receives serial data User I O Connect to the SPI Flash PROM s from PROM s serial data Slave Data Output pin output 94 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX FPGA Connectio
244. hich guarantees a logic High to the CSI B input of the next device in the chain If FPGA s HSWAP or PUDC B pin is Low no external pull up is necessary Spartan 3 Generation Configuration User Guide www xilinx com 143 UG332 v1 2 May 23 2007 Chapter 5 Master BPI Mode XILINX Serial Daisy Chaining Spartan 3A 3AN 3A DSP FPGAs Only The Spartan 3A 3AN 3A DSP FPGA family supports serial daisy chains where the first device in the chain uses BPI mode Serial daisy chains from BPI mode are not supported for Spartan 3E FPGAs As shown in Figure 5 5 page 145 all downstream FPGAs in the serial daisy chain use Slave Serial mode M 2 0 lt 1 1 1 gt and can be from any Xilinx FPGA family The CCLK output from the master device operates a 8 times the frequency of the Flash interface and CCLK synchronizes all FPGAs in the daisy chain The master FPGA access the Flash every 8 CCLK cycles but provides serial data on its DOUT output to downstream FPGAs every CCLK cycle The iMPACT programming software automatically adjusts the CCLK frequency when serial daisy chains are selected in Step 14 Figure 5 10 page 151 After the master FPGA the FPGA on the top left in Figure 5 5 finishes loading its configuration data from the parallel Flash PROM the master device continues generating addresses to the Flash PROM The master FPGA reads byte wide data from the PROM internally serializes the data and provides the data to downstream devices v
245. i ed ede die vis 188 Bit Sequence Boundary Scan Register sees 189 Instruction Register init eripe Ce Bees so e tee aces dre ed eeden ed depen 190 BYPASS Reeister sid onere pee er ere NE eie Gee EEE aie ida 191 Identification IDCODE Register ise 191 JTAG Configuration Register Boundary Scan sese 191 USBRCODE Re amp gISIer e vue eR Ving Yb dre ee dedere bete tir ddp es 191 USERI and USER2 Registers oss 000 eee me hh hme ne beens 192 Using Boundary Scan in Spartan 3 Generation FPGAS 000 192 Programming Cables and Headers 0 0 0 0 cece cece eee eee 193 Programming an FPGA Using JTAG sene 194 Mode Pin Considerations when Programming a Spartan 3AN FPGA via JTAG using iMPACT 199 Chapter 10 Internal Master SPI Mode Internal Flash Memory 000 ccc nn 202 Mode Sel ct Pins M 2 0 5 e Rer e rx a a e e 202 Variant Select Pins VS 2 0 0 0 cece n 202 Supply Voltage Requirements 0 66 nannan rnnr een eens 203 VCCAUX eines ace drea uude EC GARA PS SACR CAD Rawk Bl Ree TE qmd aa 203 VG GO 203 Sequenclmp agosto dors bte eee quee pte quts ism e ck eun beeen 203 Accessing the Internal SPI Flash PROM After Configuration 208 No Configuration Daisy Chains in Internal Master SPI Mode 204 Generating the Bitstream for
246. iMPACT FE Please select an action from the list below C Configure devices using Boundary Scan JTAG N2 Automatically connect to a cable and identify Boundary Scan chain v Prepare a PROM File C Prepare a System ACE File C Prepare a Boundary Scan File C Configure devices Cancel UG332 c14 04 112906 Figure 14 2 Prepare a MultiBoot PROM Image 3 Click Next 4 Asshownin Figure 14 3 target a PROM Supporting Multiple Design Revisions 250 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Spartan 3E MultiBoot iMPACT Prepare PROM Files File Ea want to target a C Xilins PROM Generic Parallel PROM C 3rd Party SPI PROM PROM Supporting Multiple Design Versions PROM File Format C TEK C UFP E format C Exo C BIN C SC C HEX Swap Bits Checksum Fill Value 2 Hex Digits FNY PROM File Name MyMultiBootPROM Location C Data my_designs s3e_multiboot lt Back Spartan3E MultiBoot Cancel UG332_c14_03_112906 Figure 14 3 Select a PROM Supporting MultiBoot for Spartan 3E FPGAs Choose the Spartan3E MultiBoot method Select a PROM File Format The MCS format is supported by a variety of programmers but other options are available Enter a PROM File Name Click Next As shown in Figure 14 4 select the Initial Boot Direction This is the lo
247. ia its DOUT output pin The next FPGA in the daisy chain then receives serial configuration data from the preceding FPGA in the chain The master FPGA s CCLK output synchronizes data capture 144 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Daisy Chaining Spartan 3A 3AN 3A DSP Parallel NOR FPGA Flash 0 Serialized PROM Data Hoo gt vour Lor Xe Ko X X5 5X7 LDC2 A 25 0 A 25 0 Next PROM Address D 7 0 DOUT CCLK CSI B CSO B RDWR B INIT B PROG B DONE Slave T M2 M2 Serial ak M1 M1 Mode 1 mo INIT_B MO PROG B DONE PROG B DONE Intermediate Last FPGA in FPGAs Daisy Chain Any Xilinx FPGA Any Xilinx FPGA UGS332 c5 06 052107 Figure 5 5 Serial Daisy Chains are Only Available for Spartan 3A 3AN 3A DSP BPI Mode Spartan 3 Generation Configuration User Guide www xilinx com 145 UG332 v1 2 May 23 2007 Chapter 5 Master BPI Mode XILINX Using Xilinx Platform Flash PROMs with Master BPI Mode The Master BPI mode also supports the Xilinx Parallel Platform Flash PROM XCFxxP family as shown in Figure 5 6 1 2V 1 8V VCCINT VCCINT PUDCB VCCOO x VCCO CEO Platform Flash XCFxxP REV SEL1 Not REV_SELO available on XC3S50A D 7 0 D 7 0 vo X XILINX EN EXT SEL Spartan 3A 3AN 3A DSP BUSY FPGA TDI TDO PROG B DONE GND Xilinx Cable Header JTAG Interface Dedicated i
248. ic setting depends on the specific FPGA family the attached configuration memory and the configuration mode Specific values are recommended in later chapters depending on the speed of the attached memory 8 The FPGA s DONE and PROG B Program pins each have a dedicated pull up resistor during configuration These resistors become optional after configuration The specific example is from a Spartan 3E FPGA application Spartan 3 and Spartan 3A FPGAs have additional options 9 The FPGA s JTAG pins each have a dedicated pull up resistor during configuration These resistors become optional after configuration 10 By default unused I O blocks are configured as inputs with a pull down resistor Other options are available See UnusedPin bitstream option 11 Each FPGA bitstream can include an 8 digit hexadecimal 32 bit identifier that can be read via the FPGA s JTAG port Spartan 3 Generation Configuration User Guide www xilinx com 29 UG332 v1 2 May 23 2007 Chapter 1 Overview and Design Considerations XILINX 12 13 14 15 16 E Process Properties Category Property Name Value FPGA Start Up Clock CCLK zj E Enable Internal Done Pipe Done Output Events Default 4 m Enable Outputs Output Events Release Write Enable Output Events Default 6 Release DLL Output E vents Default Now ait Drive Done Pin High Iv NI6 Property display level Advanced Defa
249. ides e Density migration between smaller and larger density SPI Flash PROMs Not all SPI Flash memory densities are available in all packages The SPI Flash migration strategy follows nicely with the pinout migration provided by Xilinx FPGAs Should the application need more nonvolatile storage there is always a convenient upward density migration path in the SPI Flash PROM up to 128Mbits e Consistent configuration PROM layout when migrating between FPGA densities Within the Spartan 3A 3AN 3A DSP FPGA family and within the Spartan 3E FPGA family a particular FPGA package option spans different density levels while maintaining footprint compatibility The SPI Flash multi package layout allows comparable flexibility in the associated configuration PROM Ship the optimally sized SPI Flash memory for the specific FPGA mounted on the board e Supply security If a certain SPI Flash density is not available in the desired package switch to a different package style or to a different density to secure availability Likewise multiple vendors support the STMicroelectronics footprint 126 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Saving Power An example package layout for the M25Pxx SPI serial Flash family from the Spartan 3E Starter Kit Board is provided in Figure 4 30 The multi package layout supports the 8 lead 8x6 mm MLP package the 8 pin SOIC package and the 16 pin SOIC pa
250. igent Download Host Configuration Memory Source READ WRITE Xilinx Cable Header JTAG Interface Dedicated internal pull up resistor UG332 c7 01 052207 Figure 7 1 Slave Parallel Mode Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs 164 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Intelligent Download Host VCC Configuration D e Memory Source SELECT READ WRITE gigmalmemeny lk l IV Over network PROG B Over RF link DONE INIT B GND e Microcontroller Processor e Tester Computer PROGRAM VCCAUX s VREF O Be tus ANN is rck og J ac g ZE E gt A nn Dedicated internal pull up resistor 1 2V VCCINT D 7 0 VCCO_4 BUSY VCCO_5 CS B RDWR B CCLK VCCAUX HSWAP EN M2 XILINX M1 Spartan 3 FPGA Mo Slave Parallel TMS Mode TCK TDI TDO PROG_B DONE GND UG332_c7_02_022607 Figure 7 2 Slave Parallel Mode Spartan 3 FPGAs Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 165 Chapter 7 Slave Parallel Select MAP Mode EZ XILINX Table 7 1 Slave Parallel SelectMAP Function Overview Inputs to FPGA D 7 0 is bidirectional FPGA Outputs PROG B CSI B RDWR B D 7 0 BUSY CCLK INIT B DONE Function 0 X X X X X X Drive PROG B Low
251. ign Specification 2 oo iets dent conrad a aa cass ir a 259 FPGA Application Run Time 0 0 0 ccc ce eh nn 260 MultiBoot from an Address Preloaded during Configuration 0 260 MultiBoot to a Address Specified by the FPGA Application 00 260 MultiBoot Registers 0 0 een 262 Next MultiBoot Start Address GENERAL1 GENERAL2 02 0000 0s eee 262 Command Register CMD er 2s0i ss20 esepis8 dee rb EE EE eu hie Fates 262 Configuration Mode Register MODE REG 0 0 cece ccc ce eee 263 Generating a Spartan 3A 3AN 3A DSP MultiBoot PROM Image using iMPACT 263 Configuration Watchdog Timer CWDT and Fallback 0000005 270 Advanced Capabilities e eee tera eee RE eR ea 271 Switching between MultiBoot Configuration Memory Types 0 0005 271 Chapter 15 Protecting FPGA Designs Basic FPGA Hardware Level Security Options 004 273 Spartan 3 and Spartan 3E Security Levels 6 6 eee eee 274 Spartan 3A 3AN 3A DSP Security Levels 2 0 66 274 Setting the Security Level in the Bitstream 0 0 6 6 c eee eee eee 274 ISE Project Navigator sic needs oi aed E RR YR RYE VICRERQA eV ote p REY oe ae 274 BitGen Command Line Utility esee e 276 Approaches to Design Security esses esee 276 Security BIS o rr necrotic Sian asd cere baleen ee bete d duca ii grades 277 ENCryYPHONs Em 277 AvithenticatiOn sce e dp Rr RR PEg ERE iL
252. igned primarily for stability resulting in improved stability over voltage and temperature CCLs also exhibit 10 to 100 times better immunity to single event upset SEU phenomenon than traditional SRAM memories Xilinx is a world leader in measuring and mitigating SEU effects on FPGAs Extensive proton beam and atmospheric data is available upon request Post Configuration CRC Spartan 3A 3AN 3A DSP Only Despite the robust stability of the CMOS configuration latches CCLs that hold the FPGA configuration data some high reliability high demand applications require continuous checking of all configuration memory locations Spartan 3A 3AN 3A DSP FPGAs offer this capability The configuration CRC checker can be enabled so that it continues to monitor the FPGA bitstream after configuration 292 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Post Configuration CRC Spartan 3A 3AN 3A DSP Only Overview Figure 16 1 page 293 provides a conceptual overview checker circuit Block RAM CMOS Configuration Latches CCLs of the post configuration CRC SLICEM LUTs All FPGA configuration bits are always checked when the C is enabled Block RAM bits are not checked by CRC checker POST_CRC Internal Oscillator ENABLE TTT TTT TTT ty yy fy SLICEM SLICEL Logic LUT LUTRAM SRL16 Logic LUT LUTRAM SRL16 Logic LUT LUTRAM
253. iguration Image 18 Select the first FPGA configuration bitstream 19 Click Open 20 Click No 21 Perform Steps 17 through 20 but this time for the second FPGA configuration bitstream 22 As shown in Figure 14 18 start adding the third FPGA configuration bitstream Start adding device file to Revision 2 22 D Would you like to add another design file to 3 Data Stream 2 My Recent Documents LO File name 34 multiboot imaae 2 bit Place Add Device x lt e You have completed the device file entry A Click Ok to continue Orn Cancel LZ UG332 c14 17 082106 Figure 14 18 Select the Third MultiBoot Configuration Image Spartan 3 Generation Configuration User Guide www xilinx com 269 UG332 v1 2 May 23 2007 Chapter 14 Reconfiguration and MultiBoot XILINX 23 Select the third FPGA configuration bitstream 24 Click Open 25 Click No 26 File selection is complete Click OK 27 As shown in Figure 14 19 the iMPACT software reports how much of the PROM is consumed by the FPGA configuration bitstream files Double click Generate File iMPACT C Data my designs s3a multiboot MySpartan 3AMultiBoot ipf PROM File Formatter g File Edit View Operations Options Output Debug Window Help lg B amp amp x a xx z2 z x 1S electMAP Data Stream fot al I a E maDesktop Configu H mal Direct SPI Config m El SystemACE
254. imitive Spartan 3 Generation Configuration User Guide www xilinx com 203 UG332 v1 2 May 23 2007 Chapter 10 Internal Master SPI Mode XILINX Details on accessing the In System Flash memory after configuration from inside the FPGA application are found in UG333 Spartan 3AN In System Flash User Guide e UG333 Spartan 3AN In System Flash User Guide www xilinx com bvdocs userguides ug333 pdf No Configuration Daisy Chains in Internal Master SPI Mode Spartan 3AN FPGAs do not support multi FPGA daisy chains when configuring from Internal Master SPI mode The FPGA does not supply the DOUT or CCLK outputs required for serial daisy chains when configuring in this mode However the Spartan 3AN FPGA supports daisy chaining when configured using any of the other modes or when configured in a Slave configuration mode Generating the Bitstream for a Master SPI Configuration To create the FPGA bitstream for a Internal Master SPI configuration follow the steps outlined in Setting Bitstream Options Generating an FPGA Bitstream page 27 For an FPGA configured in Internal Master SPI mode set the following bitstream generator options ConfigRate CCLK Frequency Set the ConfigRate option for 33 MHz Using ISE Project Navigator the Configuration Rate frequency is set in Step 7 in Figure 1 7 page 29 g ConfigRate 33 StartupClk CCLK By default the configuration Startup clock source is the internally generated CCLK Keep
255. in the chain If HSWAP or PUDC_B 1 ina multi FPGA daisy chain application connect this signal to a 4 7 kQ pull up resistor to VCCO_2 Actively drives Low when selecting a downstream device in the chain User I O Spartan 3E FPGAs BUSY Output Busy Indicator Not used in single FPGA designs BUSY is pulled up not actively driving User I O Spartan 3A Spartan 3AN Spartan 3A DSP FPGAs DOUT Output Serial Data Output Used in Spartan 3A 3AN 3A DSP serial daisy chains Not used in single FPGA designs DOUT is pulled up not actively driving In a Spartan 3A 3AN 3A DSP serial daisy chain configuration this pin connects to DIN input of the next FPGA in the chain User I O Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 135 Chapter 5 Master BPI Mode EZ XILINX Table 5 3 Byte Wide Peripheral Interface BPI Connections Continued FPGA Pin Name Direction Description During Configuration After Configuration CCLK Output Configuration Clock Generated Not used in single FPGA User I O Drive High by FPGA internal oscillator applications but actively drives In or Low if not used Frequency controlled by a daisy chain configuration drives ConfigRate bitstream generator the CCLK inputs of all other FPGAs option If CCLK PCB trace is long in the daisy chain or has multiple connections
256. in I O Bank 2 and its output voltage determined by VCCO 2 Spartan 3 FPGA Family INIT B is located in I O Bank 4 and its output voltage determined by VCCO 4 or VCCO BOTTOM depending on package style Pull Up Resistors During Configuration The FPGA s configuration control pins have a dedicated internal pull up resistor that is active during the configuration process All other I O or Input only pins have an optional pull up resistor during configuration controlled by a separate control input The name of the control input varies by Spartan 3 Generation family as shown in Table 2 12 Pins with Dedicated Pull Up Resistors during Configuration Table 2 9 shows the configuration control pins on all Spartan 3 Generation FPGAs that have a built in dedicated pull up resistor during configuration The table also indicates the supply rail to which the resistor is connected The dedicated configuration pins also have a separate bitstream generator BitGen option setting that controls the pin s behavior after configuration 46 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX General Configuration Control Pins Table 2 9 Pins with Dedicated Pull Up Resistors during Configuration All Spartan 3 Generation FPGAs Pull Up Resistor Supply see Table 2 12 Pin Name Rail Post Configuration Control PROG B VCCAUX ProgPin BitGen setting DONE VCCAUX DonePin and DriveDone Bi
257. in is Low in which case the CCLK output is pulled High Configuration CRC Enabled by Default The CRC check is included in the configuration bitstream by default CRC Enable However it is possible to disable the check which should only be done in rare circumstances and with great caution If the CRC check is disabled there is a risk of loading incorrect configuration data frames causing incorrect design behavior or damage to the FPGA Possible CRC Escapes There is a scenario where errors in transmitting the configuration bitstream can be missed by the CRC check Certain clocking errors such as double clocking can cause loss of synchronization between the bitstream packets and the configuration logic Once synchronization is lost any subsequent commands are not understood by the FPGA including the command that performs the CRC check In this situation configuration fails with the FPGA s DONE pin Low and the INIT_B pin High because the CRC was ignored In Spartan 3A 3AN 3A DSP BPI mode the address counter eventually overflows or Spartan 3 Generation Configuration User Guide www xilinx com 291 UG332 v1 2 May 23 2007 Chapter 16 Configuration CRC XILINX underflows to cause wraparound which triggers reconfiguration if the Reset_on_err Yes bitstream option is set Spartan 3A 3AN 3A DSP Configuration CRC Errors and Configuration Watchdog Timer Spartan 3A 3AN 3A DSP FPGAs include a Configuration Watchdog Timer CWDT
258. in memory but the original bitstream File remains unchanged UG332_c9_09_112006 Figure 9 11 iMPACT Automatically Adjusts FPGA Startup Clock for JTAG Configuration 9 For faster downloading and a shorter FPGA debugging cycle there is no need to program the Platform Flash PROM or CPLD unless actually desired To skip programming the Platform Flash PROM click Bypass as shown in Figure 9 12 196 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Programming an FPGA Using JTAG Assign New Configuration File i xj File name i File type All Design Files mcs exo isc bsd Cancel UG332 c9 10 112006 Figure 9 12 Click Bypass to Skip Platform Flash Programming 10 Similarly click Bypass to skip programming of the CPLD as shown in Figure 9 13 Assign New Configuration File 20x amp ck pr 8 amp File type All Design Files mcs exo isc bsd Cancel All UG332 c9 11 112006 Figure 9 13 Click Bypass to Skip CPLD Programming 11 As shown in Figure 9 14 the iMPACT software updates the display showing the files assigned to each device in the JTAG chain In this example the XCF045 Platform Flash and XC2C64A CPLD are bypassed and are not programmed Click the FPGA to highlight it on the display Spartan 3 Generation Configuration User Guide www xilinx com 197 UG332 v1 2 May 23 2007 Chapter 9 JTAG Configu
259. in progress active Low 0 Abort is in progress 1 No abort in progress D 3 0 N A 1111 all High 176 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX SelectMAP Reconfiguration The ABORT sequence lasts four CCLK cycles During those cycles the status word changes to reflect data alignment and ABORT status An example ABORT sequence appears in Table 7 4 Table 7 4 Example ABORT Sequence Disil iram D7 D6 D5 D4 D 3 0 FPGA CFGERR B DALIGN RIP IN ABORT B N A 11011111 1 1 0 1 1111 11001111 1 1 0 0 1111 10001111 1 0 0 0 1111 10011111 1 0 0 1 ILLI After the last cycle the synchronization word can be reloaded to establish data alignment Resuming Configuration or Readback After an Abort There are two ways to resume configuration or readback after an ABORT 1 The FPGA can be resynchronized after the ABORT completes by resending the configuration synchronization word See Table 12 3 page 230 2 Reset the FPGA by pulsing PROG B Low at any time To resynchronize the device CSI B must first be deasserted then reasserted To resume configuration or readback resend the last configuration or readback packet that was in progress when the ABORT occurred Alternatively restart configuration or readback from the beginning SelectMAP Reconfiguration The term reconfiguration refers to reprogramming an FPGA after its
260. ines to access an attached parallel memory There are a few exceptions as described below e Spartan 3E FPGAs available in the TQ144 package only provide 20 address lines which is more than sufficient for the smaller FPGA array sizes offered in the TQ144 package e Similarly the XC3S100E FPGA in the CP132 package only has 20 address lines while the XC3S250E and XC3S500E FPGAs in the same package have 24 address lines e The BPI address pins are not provided on Spartan 3E FPGAs offered in the VQ100 Consequently Spartan 3E FPGAs in the VQ100 package cannot configure from a parallel NOR Flash but can configure using parallel Xilinx Platform Flash XCFxxP Spartan 3A 3AN 3A DSP FPGAs generally provide up to 26 address lines to access an attached parallel memory There are a few exceptions as described below e The XC3550A FPGA does not support BPI mode As shown in Figure 5 14 page 156 the mode select pins M 2 0 are sampled when the FPGA s INIT_B output goes High and must be at defined logic levels during this time After configuration when the FPGA s DONE output goes High the mode pins are available as full featured user I O pins Similarly the FPGA s HSWAP pin must be Low to enable pull up resistors on all user 170 pins or High to disable the pull up resistor The HSWAP or PUDC_B control must remain at a constant logic level throughout FPGA configuration After configuration when the FPGA s DONE output goes High the HSWAP o
261. instruction and data registers The state of the TAP controller and the current instruction determine the register that is fed by the TDI pin for a specific operation TDI has an internal resistive pull up to provide a logic High to the system if the pin is not driven TDI is applied into the JTAG registers on the rising edge of TCK TDO Test Data Out This pin is the serial output for all JTAG instruction and data registers The state of the TAP controller and the current instruction determine the register instruction or data that feeds TDO for a specific operation TDO changes state on the falling edge of TCK and is only active during the shifting of instructions or data through the device TDO is an active driver output TMS Test Mode Select This pin determines the sequence of states through the TAP controller on the rising edge of TCK TMS has an internal resistive pull up to provide a logic High if the pin is not driven TCK Test Clock TCK sequences the TAP controller and the JTAG registers Notes 1 LAs specified by the IEEE Standard the TMS and TDI pins both have internal pull up resistors These internal pull up resistors of are active before configuration regardless of the mode selected See Table 2 13 page 49 for resistor values After configuration these resistors are controlled by the TmsPin and TdiPin bitstream generator option settings shown in Table 11 2 page 218 TAP Controller Figure 9 3 diagra
262. ion User Guide UG332 v1 2 May 23 2007 XILINX General Configuration Control Pins Spartan 3A 3AN 3A DSP and Spartan 3E FPGA Families On the Spartan 3A 3AN 3A DSP and Spartan 3E FPGA families the CCLK pin is borrowed during configuration and becomes a full user I O after configuration successfully completes The CCLK pin does not have a dedicated pull up resistor during configuration However CCLK has an optional pull up resistor to VCCO_2 during configuration controlled by the Spartan 3E HSWAP pin or the Spartan 3A 3AN 3A DSP PUDC B pin If the CCLK pin is not otherwise used by the FPGA application then drive the pin High or Low Spartan 3 FPGA Family During configuration the CCLK pin has a dedicated internal pull up resistor to VccAUx regardless of the HSWAP EN pin After configuration the CCLK pin is pulled High to VccAux by default as defined by the CcIKkPin bitstream selection although this behavior is programmable Any clocks applied to CCLK after configuration are ignored unless the bitstream option Persist Yes is set which retains the configuration interface The Persist No by default However if Persist Yes then all clock edges are potentially active events depending on the other configuration control signals Initializing Configuration Memory Configuration Error INIT B The INIT B pin serves multiple purposes during configuration Shortly after power is applied the FPGA drives the INIT B pin Low indic
263. ion and MultiBoot XILINX PROMGEN Xilinx Prom Generator I 32 Copyright c 1995 2006 Xilinx Inc All rights reserved w p mcs c FF o MyMultiBootPROM u 0 first multiboot image bit d fffff second multiboot image bit PROM MyMultiBootPROM prm Calculating PROM checksum with fill value ff Format Mcs 86 32 bit Size 1024K PROM start 0000 0000 PROM end 000 f ffff PROM checksum 07515767 Addr 1 Addr2 Date File s 0000 0000 0004 547 18 22 38 14 2006 first multiboot imag 000 f ffff 000b ab80 Aug 18 22 37 07 2006 second multiboot image bit UG332 c14 11 082006 Figure 14 10 PROMGen Report File prm The following items correspond to the markers in Figure 14 10 1 PROMGen is the command line program that generates PROM programming files using the specified format Various formats are available The Intel MCS format is one of the popular options The base output file name The extension depends on the selected format In the example shown above the first MultiBoot file is loaded for the BPI Up mode meaning that the file starts at address 0 5 The second MultiBoot file is loaded at the opposite end of memory in this case at the maximum PROM address and loaded downward 6 The PROM size is specified in kilobytes K In the example the PROM is 1Mbyte or 1024K 7 The first MultiBoot image is loaded starting at PROM address 0 and ends at hexadecimal address 0x4547F 8 Thesecond MultiBoot
264. irection Function Active upon the loading of the USER instruction It asserts SHIFT Output High when the JTAG TAP controller is in the SHIFI DR state Active upon the loading of the USER instruction Asserts CAPTURE Output High when the JTAG TAP controller is in the CAPTURE DR state Active upon the loading of the USER instruction It asserts UPDATE Output High when theJTAG TAP controller is in the UPDATE DR state Active upon the loading of the USER1 or USER2 TDO1 TDO2 Input instruction External JTAG TDO pin reflects data input to the component s TDO1 USER1 or TDO2 USER2 pin Start Up STARTUP The STARTUP primitive is used to either interface device pins and or logic to the global asynchronous set reset GSR signal or for global 3 state GTS dedicated routing This primitive can also be used to specify a different clock for the device startup sequence at the end of configuring the device STARTUP_SPARTAN3 STARTUP_SPARTAN3A STARTUP SPARTANSE UG332 C13 02 120106 Figure 13 2 STARTUP Primitive for Spartan 3A 3AN 3A DSP and Spartan 3E FPGAs As shown in Figure 13 2 the STARTUP primitive is similar between Spartan 3 Generation FPGA families although the Spartan 3E STARTUP primitive has an additional input pin to support MultiBoot functions The specific STARTUP primitive name also varies by family as indicated in Table 13 3 Table 13 3 STARTUP Primitives by FPGA Family FPGA Family Primitive S
265. is is different than conventions used elsewhere Watch out for bit reversals Table 13 8 ICAP SPARTAN3A Primitive Connections Signal Name Direction Description CLK Input ICAP interface clock CE Input Active Low select Equivalent to CS_B in the Slave Parallel pu SelectMAP interface Read Write control input Equivalent to the RDWR_B signal in the Slave Parallel SelectMAP interface WRITE Input ENR 1 READ I 0 7 Input Byte wide ICAP write data bus O 0 7 Output Byte wide ICAP read data bus Active High busy status Only used in read operations pons TIO BUSY remains Low during writes Device DNA Access Port DNA PORT The DNA PORT primitive shown in Figure 13 5 is only available on the Spartan 3A 3AN 3A DSP FPGA families DNA PORT UG332 C13 05 081406 Figure 13 5 DNA PORT Primitive only available on Spartan 3A 3AN 3A DSP FPGAs The DNA_PORT provides access to a dedicated shift register which can be loaded with the Device DNA data bits unique ID for a given Spartan 3A 3AN 3A DSP device In addition to shifting out the DNA data bits this component allows for the inclusion of supplemental data bits for additional user data or allow for the DNA data to rollover repeat DNA data after initial data has been shifted out This component is primarily used in conjunction with other circuitry to build anti cloning protection for the FPGA bitstream from possible theft See Chapter 15 Protectin
266. isc bsd Cancel Cancel All Bypass 4 UG332_c3_12_111506 Figure 3 17 Select the Platform Flash Programming File 6 Click Open Spartan 3 Generation Configuration User Guide www xilinx com 81 UG332 v1 2 May 23 2007 Chapter 3 Master Serial Mode XILINX 7 Asshownin Figure 3 18 the iMPACT software updates the screen image showing the files to be loaded to each device in the JTAG chain To program the Platform Flash PROM first click to highlight the XCF04S PROM iMPACT C Data my designs led crazy led crazy ipf Boundary Scan H3 File Edit View Operations Options Output Debug Window Help a Bx s X F H BB Boundary Scan H malSlaveSerial H a SelectMAP a Desktop Configu Ba Direct SPI Config E xc3s700a bypass xcf 4s iMPACT Modes myplatformflash m Program Succeeded UG332 c3 13 111506 Figure 3 18 Program the Platform Flash PROM 8 Double click Program 9 Click Programming Properties as shown in Figure 3 19 Programming Properties Category T IP ogramming Properties Ie n PROM CoolRunnerll Usercode 8 Hex Digits PROM Specific Properties Al I Load FPGA Parallel Mode Use D4 for CF Cancel Apply Help UG332_c3_14_111506 Figure 3 19 PROM Programming Options 82 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Pr
267. k the Programming Properties option under Category as shown in Figure 4 20 Programming Properties xi UG332_c4_07_101006 Figure 4 20 SPI PROM Programming Options 11 Check Verify Unchecking Verify reduces programming time but the iMPACT software can only guarantee correct programming for a verified PROM 12 Check Erase Before Programming Unchecking the Erase option reduces programming time However Xilinx recommends erasing the PROM when downloading a new FPGA bitstream 13 Click OK 14 The iMPACT software indicates successful programming as shown in Figure 4 19 Indirect Programming using iMPACT Indirect programming support is available starting with Xilinx ISE 9 1i Service Pack 1 and later releases In Indirect mode the iMPACT software programs the memory attached to the FPGA through the FPGA s JTAG port During the programming process the FPGA is configured with a special programming application Consequently the FPGA s DONE pin will go High during the programming process Programming Setup To program the attached and selected SPI PROM using the Indirect method configure the board as described below 1 Disconnect power to the board 2 Setthe FPGA mode select pins for Master SPI mode 3 Connect the JTAG programming cable to the FPGA s JTAG port 4 Re apply power to the board 118 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Indirect
268. l externally MOPin Spartan 3 FPGA only MO pin Pullup Default Internally connects a pull up resistor or between MO mode select pin and VccAux Pulldown Internally connects a pull down resistor or between MO mode select pin and GND Pullnone MO pin is high impedance floating Define MO logic level externally DONE Pin Options See DONE Pin page 36 DonePin DONE pin Pullup Default Internally connects a pull up resistor between DONE pin and VccAux An external 330 Q pull up resistor to Vccaux is still recommended See DONE pin ConfigRate Bitstream Option for CCLK page 44 Pullnone No internal pull up resistor on DONE pin An external 330 Q pull up resistor to Vccay x is required DriveDone DONE pin No Default When configuration completes the DONE pin stops driving Low and relies on an external 330 pull up resistor to VccAux for a valid logic High See DONE pin ConfigRate Bitstream Option for CCLK page 44 Yes When configuration completes the DONE pin actively drives High When using this option an external pull up resistor is no longer required Only one device in an FPGA daisy chain should use this setting DonePipe DONE pin Default The input path from DONE pin input back to the Startup sequencer is not pipelined See DONE pin ConfigRate Bitstream Option for CCLK page 44 Yes This option adds a pipe
269. l Configuration Control Pins Figure 2 3 shows the basic point to point topology where the CCLK output from the Master FPGA drives one clock input receiver either on the configuration PROM or on a slave FPGA Caution On Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs be sure to define a valid logic level on CCLK Otherwise the clock trace might float and cause spurious clocking to other devices in the system CCLK gt za z gt Master FPGA C PROM Clock Input N Slave FPGA CCLK Input 8 2 Voco 2 2 x Zo 1000 2 x Zy 1009 UG332_c2_05_112206 Figure 2 3 Point to Point Master CCLK Output Drives Single Clock Load Figure 2 4 shows the basic multi drop flyby topology where the CCLK output from the Master FPGA drives two or more clock input receivers Constrain the trace length on any clock stubs CCLK Clock Input 2 Master FPGA 2 x Zg 1002 ww gz gt ujue qns Clock Input 1 2 x Zo 1000 m UG332 c2 06 112206 Figure 2 4 Multi Drop Master CCLK Output Drives Two Clock Inputs Spartan 3 Generation Configuration User Guide www xilinx com 43 UG332 v1 2 May 23 2007 Chapter 2 Configuration Pins and Behavior during Configuration XILINX Figure 2 5 shows a star topology where the Master FPGA CCLK transmission line branches to the multiple clock receiver inputs The branch point creates a significant impedance discontinuity Do not use this topology UG191 c2 07 112206 Figure 2 5
270. l high impedance floating Hi Z allowing the programmer to have full and direct control over the SPI PROM There are three different methods to place the FPGA SPI signals in high impedance listed below Spartan 3 Generation Configuration User Guide www xilinx com UG332 v1 2 May 23 2007 107 Chapter 4 Master SPI Mode XILINX Option1 Hold the FPGA s PROG_B pin Low throughout the programming process The FPGA is unconfigured during the programming process and automatically loads the new SPI Flash PROM image when PROG B is released High Option2 Change the FPGA s mode pins to JTAG mode M 2 0 lt 1 0 1 gt and pulse the FPGA s PROG B pin Do not perform any JTAG operations All FPGA I O pins are forced to their high impedance state The FPGA is unconfigured during the programming process The FPGA s M 2 0 pins must be returned to the SPI Flash setting and PROG B pin must be pulsed Low before the FPGA reloads the new SPI Flash PROM image Option3 Within a functioning FPGA application use an internal control signal that three states the MOSI DIN CCLK and CSO B pins The FPGA remains configured with the current configuration Pulse the PROG B pin Low or on Spartan 3A 3AN 3A DSP FPGAs issue a MultiBoot reconfiguration operation with a start address of zero If using Option 1 or Option 2 be aware that pull up resistors to VCCO 2 are enabled on the FPGA s SPI pins if the FPGA s HSWAP or PUDC B pin is Low Using Option
271. large enough to contain the sum of the FPGA file sizes An application can also use a larger density SPI Flash PROM to hold additional data beyond just FPGA configuration data For example the SPI Flash PROM can also store application code for a MicroBlaze RISC processor core integrated in the Spartan 3A or Spartan 3E FPGA See SPI Flash Interface after Configuration Table 4 6 Number of Bits to Program a Spartan 3A 3AN 3A DSP or Spartan 3E FPGA and Smallest SPI Flash PROM Number of Configuration Bits Smallest Usable Family FPGA Uncompressed SPI Flash PROM XC3550A AN 437 312 512 Kbit XC35200A AN 1 196 128 2 Mbit Spartan 3A 3AN XC3S400A AN 1 886 560 2 Mbit XC35700A AN 2 732 640 4 Mbit XC381400A AN 4 755 296 8 Mbit XC3SD1800A 8 197 280 8 Mbit Spartan 3A DSP XC3SD3400A 11 718 304 16 Mbit XC3S100E 581 344 1 Mbit XC3S250E 1 353 728 2 Mbit Spartan 3E XC3S500E 2 270 208 4 Mbit XC3S1200E 3 841 184 4 Mbit XC351600E 5 969 696 8 Mbit 92 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX FPGA Connections to the SPI PROM FPGA Connections to the SPI PROM Table 4 7 shows the connections between the SPI Flash PROM and the FPGA s SPI configuration interface Each SPI Flash PROM vendor uses slightly different signal naming Table 4 8 page 94 provides a complete list of the FPGA pins involved in the Master SPI configu
272. lash a Standard interface Spartan 3E Spartan 3A 3AN Spartan 3A DSP Spartan 3 FPGA Platform Flash FPGA Platform Flash DO DO CLK CLK OE RESET CE OE RESET CE b PROM always enabled Spartan 3E Spartan 3A 3AN Spartan 3A DSP FPGA Platform Flash Spartan 3 FPGA Platform Flash DO CLK OE RESET CE c PROM enabled by FPGA Figure 3 6 Various Methods to Use Platform Flash PROM after Configuration UG332 c3 17 040107 A few simple modifications are required to the standard interface As shown in Figure 3 6a the FPGA uses its DONE output to enable the Platform Flash PROM CE input However once configured the FPGA cannot re enable the PROM because the DONE is a dedicated pin and the FPGA application cannot control it The simplest solution shown in Figure 3 6b is to connect the PROM s CE input to ground The PROM consumes slight more power if constantly enabled but then the FPGA has direct access On Spartan 3 FPGAs the CCLK pin is a dedicated pin To control the PROM use an FPGA I O in parallel with CCLK Also be sure to set the CcIkPin Pullnone bitstream option Figure 3 6c shown an alternative solution In this case connect the PROM s CE input to an FPGA I O pin The FPGA pin has a sufficiently large pull down resistor to guarantee that CE is Low during configuration The exact size of the pull down resistor depends on whether pull up resistors are enabled during configuration and the I O standar
273. later The Xilinx software tools iMPACT or PROMGen generate files from the Spartan 3AN FPGA bitstream or bitstreams The Spartan 3AN ISF memory is a serial SPI based memory and data bytes are stored most significant bit msb first When using PROMGen the spi option is required for proper formatting iMPACT The following steps graphically describe how to create an SPI formatted PROM file using iMPACT from within the ISE Project Navigator To create a Spartan 3AN MultiBoot image for an SPI Flash memory see Generating a Spartan 3A 3AN 3A DSP MultiBoot PROM Image using iMPACT page 263 1 From within the ISE Project Navigator double click Generate PROM ACE or JTAG File from within the Process pane as shown in Figure 10 3 Processes Gen Ol or JTAG File Configure Device IMPACT A Processes UG332_c4_10_110206 Figure 10 3 Double click Generate PROM ACE or JTAG File 2 As shown in Figure 10 4 select Prepare a PROM File Spartan 3 Generation Configuration User Guide www xilinx com 205 UG332 v1 2 May 23 2007 Chapter 10 Internal Master SPI Mode XILINX iMPACT Welcome to iMPACT Please select an action from the list below C Configure devices using Boundary Scan JTAG Ne Automatically connect to a cable and identify Boundary Scan chain v Prepare a PROM File C Prepare a System ACE File Prepare a Boundary Scan File SVF X C Configure devices using Slave Serial mode
274. lectronics Krypto Secure Parallel Flash Memories http www st com stonline products families memories fl nor emb fl m28w fs htm e Atmel Crypto and Secure Memories http www atmel com products SecureMem Handling Failed Authentications One of the strengths of the Spartan 3 authentication scheme is that the designer and the application decides how best to respond to a failed authentication A spectrum of solutions is possible including the following e No functionality e Limited functionality e Full functionality for a limited period of time e Active defense against tampering No Functionality The simplest way to respond to an unauthorized copy is for the application to stop functioning This is easily accomplished using features already on the FPGA such as the following e Assert the Global Set Reset GSR signal on the STARTUP design primitive which holds all flip flops reset See Start Up STARTUP page 241 The signal driving GSR must be either a logic based latch or from an SRL16 shift register neither of which are affected by the GSR signal e Assert the global three state control on the STARTUP design primitive which forces all output pins to high impedance Hi Z e Disable global clock signals using a BUFGCE global clock primitive that has an enable input which prevents the clock signal from being distributed within the design e Assert the reset input to a Digital Clock Manager DCM e Driv
275. line register stage between the DONE pin input and the Startup sequencer Used for high speed daisy chain configurations when DONE cannot rise in a single CCLK cycle Releases GWE and GTS signals on the first rising edge of StartupClk after the DONE pin input goes High Startup Sequencer Options See Startup page 233 DONE cycle DONE pin Configuration Startup 1 2 3 4 5 6 Selects the Configuration Startup phase that activates the FPGA s DONE pin See Startup page 233 220 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Table 11 2 Spartan 3 Generation Bitstream Generator BitGen Options Continued Option Name GWE cycle Pins Function Affected All flip flops LUT RAMs and SRL16 shift registers Block RAM Configuration Startup Values default 1 2 3 4 5 6 Description Default Selects the Configuration Startup phase that asserts the internal write enable signal to all flip flops LUT RAMs and shift registers SRL16 It also enables block RAM read and write operations See Startup page 233 Done Waits for the DONE pin input to go High before asserting the internal write enable signal to all flip flops LUT RAMs and shift registers SRL16 Block RAM read and write operations are enabled at this time Keep Retains the current GWE_cycle setting for partial reconfiguration applications
276. lity The solution requires either an external configuration clock source or the Platform Flash PROM s internal clock option The advantage of the alternate solution is that the FPGA s address pins are not active during configuration Furthermore if using an external clock source the clock frequency has little variation and likely operates at a higher average frequency which shortens configuration time ConfigRate Settings Using Platform Flash As shown in Table 5 8 parallel Platform Flash PROMs support a high ConfigRate setting The performance is even more dramatic considering that the PROM loads eight bits per clock The resulting bandwidth on a Spartan 3A 3AN 3A DSP FPGAs is between 110 to 190 Mbits per second Table 5 8 Maximum ConfigRate Settings Using Parallel Platform Flash Spartan 3A 3AN Platform Flash Part 1 0 Voltage Spartan 3E Spartan 3A DSP Number VCCO 2 VCCO ConfigRate Setting ConfigRate Setting XCF08P 3 3V or 2 5V 33 XCF16P 25 XCF22P 1 8V N A Spartan 3 Generation Configuration User Guide www xilinx com 147 UG332 v1 2 May 23 2007 Chapter 5 Master BPI Mode XILINX Generating the Bitstream for a Master BPI Configuration The create the FPGA bitstream for a Master BPI configuration follow the steps outlined in Setting Bitstream Options Generating an FPGA Bitstream page 27 For an FPGA configured in Master BPI mode set the following bitstream generator options Confi
277. ll ups during configuration FPGA Input 1 No pull ups PUDC B Spartan 3 FPGA HSWAP EN Mode Select Selects the FPGA M2 0 M1 0 MO O User I O M 2 0 Input configuration mode Sampled when INIT_B goes High Serial Data Input Receives serial data from User I O P inpar PROM s D0 output Configuration Clock Generated by Drives PROM s CLK clock Spartan 3 FPGA internal oscillator Frequency input Dedicated pin controlled by ConfigRate bitstream Spartan 3E generator option If CCLK PCB trace Spartan 3A CCLK Output is long or has multiple connections Spartan 3AN terminate this output to maintain Spartan 3A DSP signal integrity User I O Drive High or Low if not used Serial Data Output Not used in single FPGA User I O designs DOUT is pulled up not actively driving In a daisy DOUT Output chain configuration this pin connects to DIN input of the next FPGA in the chain See Figure 3 4 page 71 Initialization Indicator Active Low Connects to PROM s User I O If Goes Low at start of configuration OE RESET input FPGA clears unused in the during Initialization memory PROM s address counter at application clearing process Released at end of start of configuration enables drive INIT B Open drain memory clearing when mode select outputs during configuration High INIT B bidirectional pins are sampled PROM also holds FPGA in I O Initialization state until PROM reaches Power On Reset POR state If CRC error
278. ly Command Line Spartan 3 bitgen help spartan3 Spartan 3E bitgen help spartan3e Spartan 3A bitgen help spartan3a Spartan 3AN bitgen help spartan3an Spartan 3A DSP bitgen help spartan3adsp Some of the bitstream options can be controlled from the ISE Project Navigator as described in ISE Project Navigator page 28 Any option not specifically listed in the graphic interface can be included as Step 5 shown in Figure 1 6 page 28 Spartan 3 Generation Configuration User Guide www xilinx com 217 UG332 v1 2 May 23 2007 Chapter 11 Configuration Bitstream Generator BitGen Settings XILINX Table 11 2 Spartan 3 Generation Bitstream Generator BitGen Options Pins Function Values Option Name Affected default Description ConfigRate CCLK Spartan 3A Sets the frequency approximately in MHz of the internal Configuration Spartan 3AN oscillator used for Master configuration modes Drives out on Master Modes Spartan 3A DSP the FPGA s CCLK pin The internal oscillator powers up at its only FPGA lowest frequency and the new setting is loaded as part of the 1 3 6 7 8 10 configuration bitstream See Configuration Clock CCLK 12 13 17 22 page 40 for more information 25 27 33 44 50 100 Spartan 3E FPGA 1 3 6 12 25 50 Spartan 3 FPGA 3 6 12 25 50 StartupClk Configuration Cclk Default The CCLK signal internally or externally generated Start
279. ly Format Density Unique ID Field User Field STMicro M29W Paraet O ee 64 bits z larger i 32Mbitand 256 bytes Spansion S29A Parallel larger ESN Atmel AT45DBxxxD Serial All 64 bytes 64 bytes Atmel AT45BV Parallel Mbitand 64 bits 64 bits larger StrataFlash Intel Bv D D Parallel All 64 bits 64 bits Intel S33 Serial All 64 bits a aa 299 bits Macronix MX29 Parallel 32Mbitand 128 word or 64K SF TEES larger bytes Figure 15 9 shows an authentication example using a Spartan 3E FPGA and a commodity Flash PROM with an embedded device identifier In this example the configuration Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 283 Chapter 15 Protecting FPGA Designs XILINX PROM must contain a unique identifier The PROM also contains the FPGA configuration bitstream and the authentication check value specific to this implementation At power up or when PROG B is pulsed Low the FPGA configures normally Configuration PROM Spartan 3E FPGA with Device ID FPGA Bitstream FPGA Fabric Authentication Check Value UG332_c16_08_100406 Figure 15 9 Spartan 3E FPGA Authentication Example using Commodity Flash PROM with Identifier As shown in Figure 15 10 part of the FPGA application includes circuitry that validates that the bitstream programmed into the PROM is authorized to load The PROM s Device ID and the authentica
280. mage 20 Click Open 21 The iMPACT software then confirms that all the necessary files are entered 22 As shown in Figure 14 9 the iMPACT software reports how much of the PROM is consumed by the FPGA configuration bitstream files Double click Generate File 254 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Spartan 3E MultiBoot iMPACT C Datamy designss3e multiboot default ipf PROM File Formatter L3 File Edit View Operations Options Output Debug Window Help lg B amp B X amp ee z2 2 BPI Parallel Daisy Chain H malslaveSerial i als electMAP alDesktop Configu i malDirect SPI Config x m iMPACT Modes PROM 1M 54 13 96 Full Data Bus xce3s500e PROM File Generation Succeeded UG332_c14_10_082006 Figure 14 9 Generate the PROM File Using the Specified Parameters 23 The iMPACT software successfully generates a PROM file using the name specified in Step 7 with the format and file extension specified in Step 6 The file is created in the current directory A PROMGen Report File is also created PROMGen Report File The iMPACT software creates the PROM file using the PROMGen command line program The PROMGen software also creates a report file with an prm file extension as shown in Figure 14 10 Spartan 3 Generation Configuration User Guide www xilinx com 255 UG332 v1 2 May 23 2007 Chapter 14 Reconfigurat
281. mber of PROMs 1 UG332_c3_06_111506 Figure 3 11 Review PROM Formatting Settings 14 As shown in Figure 3 12 click OK to start adding bitstream files Ci Start adding device file to Data Stream 0 NA 9 Would you like to add another device file to Look in C3 led crazy Data Stream 0 My ne ET Documents M ec OMET File name led crazy bit Places ee Files of type Figure 3 12 Add FPGA Configuration Bitstream File s 15 Locate and select the desired FPGA bitstream 16 Click Open 78 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Platform Flash In System Programming via JTAG using iMPACT 17 Click No This example assumes that the Platform Flash PROM holds only a single FPGA bitstream If creating a multi FPGA configuration daisy chain click Yes and select additional FPGA bitstreams 18 Asshown in Figure 3 13 the iMPACT software graphically displays the Platform Flash PROM and associated FPGA bitstream s iMPACT C Datamy designs sblinky lights sdefault ipf PROM File Formatter E File Edit View Operations Options Output Debug Window Help lg Ell amp B Se 3c 22 Ge i 2 Boundary Scan B2 SlaveSerial aaSelectMAP Ba Desktop Configu xc3s1400a Ba Direct SPI Config xj led crazy bit iMPACT Modes Generate File Generate File UG332_c3_08_11150
282. ms a 16 state finite state machine The four TAP pins control how data is scanned into the various registers The state of the TMS pin at the rising edge of TCK Spartan 3 Generation Configuration User Guide www xilinx com 187 UG332 v1 2 May 23 2007 Chapter 9 JTAG Configuration Mode and Boundary Scan XILINX determines the sequence of state transitions There are two main sequences one for shifting data into the data register and the other for shifting an instruction into the instruction register Spartan 3 Generation FPGAs support the mandatory IEEE 1149 1 commands as well as several Xilinx vendor specific commands The EXTEST INTEST SAMPLE PRELOAD BYPASS IDCODE USERCODE and HIGHZ instructions are all included The TAP also supports internal user defined registers USER1 and USER2 and configuration readback of the device The Spartan 3 Generation Boundary Scan operations are independent of configuration mode selections The Boundary Scan mode overrides other mode selections For this reason Boundary Scan instructions using the Boundary Scan register SAMPLE PRELOAD INTEST and EXTEST must not be performed during configuration All instructions except the user defined instructions are available before a Spartan 3 Generation FPGA device is configured After configuration all instructions are available JSTART and JSHUTDOWN are instructions specific to the Spartan 3 Generation FPGA architecture and configuration flow I
283. n However the Startup sequencer does not proceed beyond the specified Startup cycle until the DONE pin actually sees an externallogic High The DONE pin is an open drain bidirectional signal by default By releasing the DONE pin the FPGA simply stops driving a logic Low and the pin goes into a high impedance Hi Z state A pull up resistor either internal or external is required for the DONE pin to reach a logic High in this case Table 12 8 shows signals relating to the startup sequencer Figure 1 12 shows the waveforms relating to the startup sequencer 236 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Startup Table 12 8 Signals Relating to Startup Sequencer Signal Name DONE Type Bidirectional Access DONE pin or Status Register Description Indicates configuration is complete Can be held Low externally to synchronize startup with other FPGAs Release_DONE GWE GTS EOS DCIMATCH DCM_LOCK Status Status Register Indicates whether the FPGA has stopped driving the DONE pin Low If the pin is held Low externally Release_DONE can differ from the actual value on the DONE pin Global Write Enable GWE When deasserted GWE disables the CLB and the IOB flip flops as well as other synchronous elements on the FPGA Global 3 State GTS When asserted GTS disables all the I O drivers except fo
284. n 3E FPGA Configured from Parallel NOR Flash _2 Dedicated internal pull up resistor UG332 c5 01 040107 130 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Overview 1 2V VCCINT PUDC_B VCCO 0 CE x80r ogg X8 x16 NOR wer Flash Not A n 0 available on XC3S50A 0 M2 D 7 0 POEM q M1 nly o mo XILINX Spartan 3A 3AN Y REDUX 25V Spartan 3A DSP CCLK CSO_B Xilinx Cable Header JTAG Interface PROGRAM _ Dedicated internal pull up resistor UG332_c5_02_040107 Figure 5 2 Spartan 3A 3AN 3A DSP FPGA Configured from Parallel NOR Flash Spartan 3 Generation Configuration User Guide www xilinx com 131 UG332 v1 2 May 23 2007 Chapter 5 Master BPI Mode EZ XILINX Master BPI Mode Differences between Spartan 3 Generation FPGA Families Table 5 1 summarizes the BPI configuration mode differences between various Spartan 3 Generation FPGA families BPI mode is only available on the Spartan 3E and Spartan 3A 3AN 3A DSP FPGA families The Spartan 3A 3AN 3A DSP BPI mode supports up to 26 address lines capable of addressing up to 512 Mbits 64 KBytes Table 5 1 BPI Configuration Mode Differences between Spartan 3 Generation FPGA Families Spartan 3A 3AN Spartan 3 Spartan 3E Spartan 3A DSP FPGA FPGA FPGA BPI Up mode supported start at 0 increme
285. n Spartan 3 Generation FPGAs the TAP controller is not reset by the PROG B pin and can only be reset by bringing the controller to the TLR state The TAP controller is reset on power up For details on the standard Boundary Scan instructions EXTEST INTEST and BYPASS refer to the IEEE Standard Boundary Scan Architecture Spartan 3 Generation FPGA registers include all registers required by the IEEE 1149 1 Standard In addition to the standard registers the family contains optional registers for simplified testing and verification as described in Table 9 3 Table 9 3 Spartan 3 Generation JTAG Registers Register Name Register Length Description Boundary Scan Register 3 bits perI O Controls and observes input output and output enable Instruction Register 6 bits Holds current instruction OPCODE and captures internal device status BYPASS Register 1 bit Bypasses the device Identification Register 32 bits Captures the Device ID JTAG Configuration Register 32 bits Allows access to the configuration bus when using the CFG_IN or CFG_OUT instructions USERCODE Register 32 bits Captures the user programmable code User Defined Registers Design specific Design specific USER1 and USER2 Boundary Scan Register Each user I O block IOB whether connected to a package pin or unbonded contains additional logic that forms the boundary scan data register as shown in Figure 9 4 188 www xilinx
286. n Spartan 3E FPGAs 10 In response to the address inputs provided by the FPGA the attached PROM asynchronously presents output data 11 During the first 320 bits in the bitstream the FPGA loads the ConfigRate bitstream setting that potentially increases the CCLK output frequency of in order to reduce configuration time 12 Two directly related factors control the interface timing One factor is the PROM data access time typically called Tacc tavov or Tayoy in memory data sheets The other is the maximum CCLK frequency controlled by the ConfigRate bitstream generator setting A faster PROM access time allows a higher ConfigRate setting resulting in a faster CCLK frequency and a correspondingly faster configuration time See Table 5 6 page 139 Table 5 10 shows the timing requirements of the attached parallel Flash PROM based on FPGA data sheet timing values Table 5 10 Configuration Timing Requirements for Attached Parallel NOR Flash Symbol Description Requirement Units TcE Parallel NOR Flash PROM chip select time Tce S TINITADDR ns tg ov Tog Parallel NOR Flash PROM output enable log lt TINITADDE ns tetrov time T Parallel NOR Flash PROM read access time ns r Tace S Tcerkumin Tecco T pcc PCB tavev ter Qv valid time 3 trHov Notes 1 These requirements are for successful FPGA configuration in BPI mode where the FPGA generates the CCLK clock signal The post configuration requi
287. n and the new image verifies as good the golden configuration triggers a MultiBoot event to load the new image Spartan 3 Generation Configuration User Guide www xilinx com 249 UG332 v1 2 May 23 2007 Chapter 14 Reconfiguration and MultiBoot XILINX When a MultiBoot event is triggered the FPGA then again drives its configuration pins as described in Chapter 5 Master BPI Mode However the FPGA does not assert the PROG B pin The system design must ensure that no other device drives on these same pins during the reconfiguration process The FPGA s DONE LDC 2 0 or HDC pins can can be used to temporarily disable any conflicting drivers during reconfiguration Asserting the PROG B pin Low overrides the MultiBoot feature and forces the FPGA to reconfigure starting from the end of memory defined by the mode pins shown in Table 5 2 page 133 Generating a Spartan 3E MultiBoot PROM Image using iMPACT The iMPACT programming software provides a graphical step by step approach to create a MultiBoot PROM file Similar functionality is also available from the command line or via scripts using the PROMGen utility shown in Figure 14 10 Follow the steps outlined below to create a MultiBoot PROM file using the iMPACT software The steps assume an example application like that shown in Figure 14 1 1 Invoke the iMPACT programming software 2 Asshown in Figure 14 2 choose Prepare a PROM File iMPACT Welcome to
288. n be expanded to additional SPI peripherals Because SPI is a common industry standard interface various SPI based peripherals are available such as analog to digital A D converters digital to analog D A converters CAN controllers and temperature sensors The MOSI DIN and CCLK pins are common to all SPI peripherals Connect the select input on each additional SPI peripheral to one of the FPGA user I O pins If HSWAP or PUDC B 0 during configuration the FPGA holds the select line High If HSWAP or PUDC B 1 connect the select line to 3 3V via an external 4 7 kQ pull up resistor to avoid spurious read or write operations After configuration drive the select line Low to select the desired SPI peripheral During the configuration process CCLK is controlled by the FPGA and limited to the frequencies generated by the FPGA After configuration the FPGA application can use other clock signals to drive the CCLK pin and can further optimize SPI based communication Caution Avoid excessive loading on the CCLK pin Excessive loading will degrade the signal integrity on this crucial signal Use the recommended design practices described in CCLK Design Considerations page 42 Refer to the individual SPI peripheral data sheet for specific interface and communication protocol requirements Caution Although many devices claim to have an SPI interface the timing and even signal polarity vary between devices and between vendors Check
289. n in a multi FPGA design This option is set graphically in the ISE Project Navigator page 28 by checking Drive Done Pin High during Step 16 in Figure 1 8 page 30 See Table 2 6 for the interaction between DriveDone and DonePin DonePin The DonePin bitstream generator option shown in Table 2 5 defines whether or not an internal pull up resistor is present on the DONE pin to pull the pin to Vecayx If the pull up resistor is eliminated then the DONE pin must be pulled High using an external 300 to 3 3kQ pull up resistor Table 2 5 DonePin Bitstream Generator Option Setting Description Pullu Default After configuration the DONE pin has an internal pull up P resistor to VCCAUX There is no internal pull up resistor on DONE An external 3000 to 3 3kQ Pullnone pull up resistor to Vccay x is required The pull up resistor must be strong enough to pull the DONE pin to a valid High within less than one CCLK cycle This option is set graphically in the ISE Project Navigator page 28 by selecting the Configuration Pin Done setting during Step 8 in Figure 1 7 page 29 See Table 2 6 for the interaction between DriveDone and DonePin Spartan 3 Generation Configuration User Guide www xilinx com 37 UG332 v1 2 May 23 2007 Chapter 2 Configuration Pins and Behavior during Configuration XILINX Table 2 6 Interaction between DriveDone and DonePin Bitstream Generator Options for DONE Pin
290. ndor Part Number Symbol Value Units Intel Corp J3v D tvccPH 60 us Spansion S29AL016M tvcs 50 us Macronix MX29LV004C tvcs 50 us In many systems the 3 3V supply feeding the FPGA s VCCO 2 input is valid before the FPGA s other Vecynt and VccAux supplies and consequently there is no issue However if the 3 3V supply feeding the FPGA s VCCO 2 supply is last in the sequence a potential race occurs between the FPGA and the NOR Flash PROM as shown in Figure 5 13 154 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Power On Precautions if 3 3V Supply is Last in Sequence 3 3V Supply Flash cannot be selected Flash PROM minimum voltage Flash PROM ready for read operations Flash l PROM NOR Flash PROM must FPGA VCCO_2 minimum ______ rs sel be ready for FPGA Power On Reset Voltage ves B access otherwise delay V FPGA configuration ccoz1 FPGA initializes configuration FPGA accesses V V Vecint VCCAUX memory Trop Flash PROM already valid Time UG332 c5 03 111906 Figure 5 13 Parallel NOR Flash PROM FPGA Power On Timing if 3 3V Supply is Last in Power On Sequence If the FPGA s Vccmr and VccAux supplies are already valid then the FPGA waits for VCCO 2 to reach its minimum threshold voltage before starting configuration This threshold voltage is labeled as Vcco T in Table 12 1
291. nect to the SPI PROM s gt Slave Data Input white TDI DIN GND Reserved Do not connect GND Notes D N C Do not connect Although the cable leads label this as __ INIT do not connect it to the FPGA s INIT B pin 1 The Flying Lead adapter is only required if using stake pins instead of the recommended 14 pin socket The specified surface mount cable connector requires only 0 162 square inches of board space The Xilinx iMPACT programming solution is only qualified for system prototyping so the socket can be removed from the production bill of materials to save cost Alternatively the Xilinx programming cables optionally support flying leads that push on to standard 0 1 inch stake pins However the ribbon cable and associated socket have superior signal integrity and provide fast programming speeds Also ensure that the programming cable leads are connected correctly The SPI programming capability is new for the Xilinx programming cables and existing cables may have different signal labels as indicated in Table 4 13 Forcing FPGA SPI Bus Pins to High impedance During Programming Because the programming cable acts as an SPI bus Master the FPGA s SPI pins must be floating or high impedance Hi Z This requirement also applies for third party programmers that directly program the SPI Flash PROM Ensure that the FPGA MOSI DIN CSO B and CCLK pins are al
292. ned DSP only Mapped FPGAs Slave Serial Possible Possible Stand alone using using sae Platform Platform qe atform atform EE IERI v v v v v Flash which Flash l optionally which download generates optionally host CCLK generates CCLK 16 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Design Considerations Does the application use a single FPGA or multiple FPGAs Most Spartan 3 Generation FPGA applications use a single FPGA However some applications require multiple FPGAs for increased logic density or I O Obviously each FPGA ina multi FPGA design could have its own separate configuration source However using a configuration daisy chain multiple FPGAs share a single configuration source Daisy chaining reduces system costs and simplifies programming and logistics The most common style is a serial daisy chain illustrated in Figure 1 3 page 18a Generally the first device in the chain may use any one of the configuration modes except JTAG mode When the first device finishes loading its configuration bitstream it passes data to the downstream FPGAs via its DOUT serial data output pin The JTAG interface also supports multi FPGA configuration as shown in Figure 1 3 page 18b The TDO serial data output is connected to the TDI serial data input of the next device in the chain The mode select input TMS and the clock input TCK are common to all devices in the JTAG chain
293. ng which is the default setting for both Alternatively set GTS cycle Done From ISE Project Navigator the GTS cycle setting is the Enable Outputs Output Events option shown as Step 14 in Figure 1 8 page 30 Preparing an SPI PROM File This section provides guidelines to create PROM files for SPI Flash memories The Xilinx software tools iMPACT or PROMGen generate SPI formatted PROM files from the FPGA bitstream or bitstreams SPI Flash memory devices serially output data bytes with the most significant bit msb first while Xilinx PROMs output data least significant bit Isb first Consequently a PROM file formatted for an SPI Flash memory device is bit reversed within each byte directly opposite from the bit ordering for a standard Xilinx PROM file When using PROMGen the spi option is required for proper formatting IMPACT The following steps graphically describe how to create an SPI formatted PROM file using iMPACT from within the ISE Project Navigator To create a Spartan 3A 3AN 3A DSP MultiBoot image for an SPI Flash memory see Generating a Spartan 3A 3AN 3A DSP MultiBoot PROM Image using iMPACT page 263 110 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Preparing an SPI PROM File 1 From within the ISE Project Navigator double click Generate PROM ACE or JTAG File from within the Process pane as shown in Figure 4 9 Processes gu
294. nnect All DONE Pins Connect the DONE pins for all devices in a multi FPGA daisy chain or broadside configuration For debugging purposes it is often helpful to have a way of disconnecting individual DONE pins from the common DONE signal so that devices can be individually configured through the serial or JTAG interface In Figure 2 1 the FPGAs can be disconnected by temporarily remove the 0 ohm resistors on the board Stake pin or wire jumpers also work DONE Pin Bitstream Generator Options When generating the bitstream files for each of the FPGAs in the daisy chain or broadside configuration set the DONE pin options as indicated in Table 2 6 page 38 Also to successfully configure a daisy chain the GTS cycle bitstream option must be set to a Startup phase after the DONE cycle setting for all FPGAs in the chain This is the software default setting Optionally set GTS cycle Done Cautions When Mixing Spartan 3A FPGAs with VccAux 3 3V and Other Spartan 3 Generation FPGAs in a Daisy Chain Configuration The DONE pin is powered by the FPGA s VccAux supply The Vecayx voltage on Spartan 3 and Spartan 3E FPGAs is solely 2 5V For Spartan 3A FPGAs however the VccaAux voltage can be either 2 5V or 3 3V Spartan 3AN FPGAs require VccAux at 3 3V Caution In a multi FPGA configuration that mixes Spartan 3A 3AN 3A DSP and other Xilinx FPGAs where the Spartan 3A 3AN 3A DSP Vocayx 3 3V check for voltage compatibility on the common DONE node
295. not be being secured No Pos Pra used except in an ryp authenticated system Does security method provide bitstream Yes Yes Yes design security What happens when an unauthorized or Behavior defined by unencrypted bitstream loaded into FPGA FPGA application N A Does not configure see Handling Failed Authentications Does the security method provide an option to No No Yes secure application data 276 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Approaches to Design Security Table 15 4 Programmable Logic Security Options Compared Does the security method provide an option to provide Digital Rights Management Security Bits No Encryption No Authentication Yes Technical Limitations Requires a large amount of on chip nonvolatile memory Key management Requires logic in the FPGA application to authenticate design Security Bits Complex PLD CPLD designs are programmed into on chip nonvolatile memory similar to simple microcontrollers As such CPLDs and microcontrollers typically offer a security bit or bits that locks the internal memory array preventing the array from being read Locking the array prevents the design from being easily copied Encryption Some FPGAs employ bitstream encryption Encryption essentially scrambles the external bitstream so that it is unusabl
296. nput Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 51 Chapter 2 Configuration Pins and Behavior during Configuration XILINX Table 2 15 Spartan 3 Generation Configuration Pins Associated Modes and Function Continued Spartan 3AN Spartan 3A DSP FPGA HDC Config FPGA Pin Name Mode s Direction Description During Configuration After Configuration CSO B Master SPI Output Chip Select Output Active Connects to the SPI Drive CSO B High Low Flash PROM s Slave after configuration to Select input If disable the SPI Flash HSWAP 1 connect and reclaim the this signal to a 4 7 KQ MOSI DIN and pull up resistor to 3 3V CCLK pins Optionally re use this pin and MOSI DIN and CCLK to continue communicating with SPI Flash Spartan 3E BPI Slave Input Chip Select Input Active Active Low User I O If bitstream Spartan 3A Parallel Low option Persist Yes Spartan 3AN becomes part of Spartan 3A DSP SelectMap parallel FPGA peripheral interface CSI_B Spartan 3 FPGA CS_B RDWR_B BPI Slave Input Read Write Control Active Must be Low User I O If bitstream Parallel Low write enable Read throughout option Persist Yes functionality typically only configuration Do not becomes part of used after configuration if change logic level SelectMap parallel bitstream option while CSI B is Low peripheral interface Persist
297. ns or IP cores Spartan 3 Generation Configuration User Guide Table 4 3 SPI Serial Flash PROMs Supported by iMPACT Vendor STMicro Atmel Status Recommended Supported Recommended Supported Density bits M25Pxx M25PExx M45PExx AT45DBxxxD AT45DBxxxB 512K M25P05A 1M M25P10A M25PE10 M45PE10 AT45DB011D AT45DB011B 2M M25P20 M25PE20 M45PE20 AT45DB021D AT45DB021B 4M M25P40 M25PE40 M45PE40 AT45DB041D AT45DB041B 8M M25P80 M25PE80 M45PE80 AT45DB081D AT45DB081B 16M M25P16 AT45DB161D 32M M25P32 AT45DB321D AT45DB321C 64M M25P64 AT45DB642D 128M M25P128 e The specific SPI serial memory must support a compatible read command offered by the FPGA The specific command set is selected by defining the FPGA s VS 2 0 pins before configuration Table 4 4 lists the commands supported on Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs The command setting defines which SPI Flash read command that the FPGA issues at the start of configuration followed by a 24 bit address starting at 0 followed by the number of dummy bits required for the specific command UG332 v1 2 May 23 2007 www xilinx com 89 Chapter 4 Master SPI Mode XILINX The Fast Read command command code 0x0B is supported on modern 25 series SPI serial Flash devices Set VS 2 0 lt 1 1 1 gt to use this command SPI Flash PROMs that support the Fast Read command also
298. ns to the SPI PROM Table 4 8 Serial Peripheral Interface SPI Connections Continued page 36 FPGA Pin Name Direction Description During Configuration After Configuration CSO B Output Master SPI Chip Select Output If HSWAP or PUDC B 1 Drive CSO B High after Active Low Connect to the SPI Flash connect this signal toa 4 7 kO configuration to disable PROM s Slave Select input pull up resistor to 3 3V the SPI Flash and reclaim the MOSI DIN and CCLK pins Optionally re use this pin and MOSI DIN and CCLK to continue communicating with SPI Flash See SPI Flash Interface after Configuration page 99 CCLK Output Configuration Clock Generated by Drives PROM s clock input User I O Drive High or FPGA internal oscillator Connect to Low if not used the SPI Flash PROM s Slave Clock Avoid excessive loading input Frequency controlled by HM on CCLK to maintain best ConfigRate bitstream generator signal integrity for option If CCLK PCB trace is long or has multiple connections terminate configuration this output to maintain signal integrity See Configuration Clock CCLK page 40 DOUT Output Serial Data Output Used in multi Not used in single FPGA User I O FPGA daisy chain configurations designs DOUT is pulled up not actively driving Ina daisy chain configuration this pin connects to DIN input of the next FPGA in the chain INIT_B Open Initialization Indic
299. nt addresses yes Yes BPI Down mode supported start at Yes No highest location decrement addresses Maximum number of address lines 24 26 supplied by FPGA FPGA I O Banks used for address lines Banks 1 and 2 Bank 1 only Address lines independent of Right No Yes edge Clock inputs RHCLKs Parallel daisy chains supported Yes Yes Serial daisy chains supported BPI Mode not No Yes available on Supports MultiBoot configuration Eee Yes Yes Watchdog Timer retry FPGA family No Yes Number of interface timing options 3 8 controlled by ConfigRate setting CCLK directionality during Master BPI Output only for mode I O improvedsignal integrity RDWR B and CSI B required during No Yes configuration don t care M 2 0 pins have dedicated internal No pull up resistors during configuration Optional T es controlled by HSWAP PROM Address Generation Spartan 3A 3AN 3A DSP FPGAs always start configuration from address 0 with incrementing addresses a mode called BPI Up Spartan 3A 3AN 3A DSP FPGAs always set M 2 0 lt 0 1 0 gt for BPI mode A As shown in Figure 5 1 page 130 the Spartan 3E FPGA family supports two versions of BPI configuration defined by the MO mode select pin As shown in Table 5 2 page 133 132 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX PROM Address Generation when the M0 mode select pin is Low a Spartan 3E FPGA configu
300. ntegrated JTAG interface e Fully supported by the Xilinx iMPACT programming software Multiple I O and JTAG voltage ranges for maximum system flexibility e Density migration within a common package footprint See Table 1 3 page 22 e Sold and supported by Xilinx with the long product lifetime and reliability associated with Xilinx products In Master Serial mode M 2 0 lt 0 0 0 gt the Spartan 3 Generation FPGA configures itself from an attached Xilinx Platform Flash PROM as illustrated in Figure 3 1 Figure 3 2 and Figure 3 3 The figures show optional components in gray and designated NO LOAD The FPGA supplies the CCLK output clock from its internal oscillator to the attached Platform Flash PROM In response the Platform Flash PROM supplies bit serial data to the FPGA s DIN input and the FPGA accepts this data on each rising CCLK edge All the FPGA mode select pins M 2 0 must be Low when sampled which occurs when the FPGA s INIT_B output initially goes High The FPGA s DOUT pin is used in daisy chain applications described in Daisy Chained Configuration page 70 In a single FPGA application the FPGA s DOUT pin is inactive but pulled High via an internal resistor The Master Serial interface varies slightly between Spartan 3 Generation FPGAs e Figure 3 1 page 64 illustrates the Master Serial configuration interface for Spartan 3E and Spartan 3A 3A DSP FPGAs when the FPGA s Vccayux supply is at 2
301. nternal pull up resistor UG332 c9 16 040107 Figure 5 6 Master BPI Mode Using Xilinx Parallel Platform Flash PROMs XCFxxP e The diagram in Figure 5 6 shows a Spartan 3A 3AN 3A DSP FPGA but the same approach also works with Spartan 3E FPGAs e The Xilinx Parallel Platform Flash PROM family is in system programmable using JTAG similar to the FPGA 146 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Using Xilinx Platform Flash PROMs with Master BPI Mode e The FPGA s address outputs A 25 0 or A 23 0 actively drive during configuration To use the design revisioning feature in Platform Flash PROMs for MultiBoot operations connect the FPGA s upper address lines to the PROM s REV SEL 1 0 inputs Spartan 3A 3AN 3A DSP FPGAs support up to four images Spartan 3E FPGAs support just two images e The FPGA s LDC2 LDC1 LDCO and HDC outputs actively drive during configuration Use the LDCO output to enable the Platform Flash PROM during configuration After configuration the FPGA application drives LDCO now an I O pin to enable or disable the PROM e After configuration the FPGA application can control the I O pins that connect to the PROM the application can read additional non configuration data from the PROM The FPGA can use the PROM s REV SEIL 1 0 pins to select different regions of the PROM A similar approach using Slave Parallel mode is possible minus the MultiBoot capabi
302. ntial race occurs between the FPGA and the SPI Flash PROM as shown in Figure 4 3 3 3V Supply SPI Flash cannot be selected a SPI Flash PROM ae SPI Flash available for minimum voltage i read operations SPI Flash PROM CS delay tys B gt FPGA initializes configuration memory Teog SPI Flash PROM must FPGA VCCO 2 minimum be ready for FPGA Power On Reset Voltage access otherwise delay FPGA configuration Vecoer FPGA accesses Vi V VocinT VCCAUX SPI Flash PROM already valid Time UG332 c4 08 102506 Figure 4 3 SPI Flash PROM FPGA Power On Timing if 3 3V Supply is Last in Power On Sequence If the FPGA s Vecint and VccAux supplies are already powered and valid then the FPGA waits for VCCO 2 to reach its minimum threshold voltage before starting configuration This threshold voltage is labeled as Vcco 7 in the Spartan 3E or Spartan 3A 3AN 3A DSP data sheet The range of values is listed in Table 4 10 and are substantially lower than the SPI Flash PROM s minimum voltage Once all three FPGA supplies reach their respective Power On Reset POR thresholds the FPGA starts the configuration process and begins initializing its internal configuration memory Initialization completes in a minimum of 1 ms as shown in Table 4 10 after which the FPGA deasserts INIT B selects the SPI Flash PROM and starts sending the appropriate read command The SPI Flash PRO
303. nx com 159 UG332 v1 2 May 23 2007 Chapter 5 Master BPI Mode XILINX 160 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Chapter 6 Master Parallel Mode Master Parallel Mode is only available on the Spartan 3 FPGA family See the D5099 Spartan 3 FPGA Family Data Sheet for details The Spartan 3A 3AN 3A DSP and Spartan 3E FPGA families do not support Master Parallel Mode but do support a variation described in Chapter 5 Master BPI Mode Spartan 3 Generation Configuration User Guide www xilinx com 161 UG332 v1 2 May 23 2007 Chapter 6 Master Parallel Mode XILINX 162 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Chapter 7 Slave Parallel SelectMAP Mode When using Slave Parallel mode configuration M 2 0 lt 1 1 0 gt an external host such as a microprocessor or microcontroller writes byte wide configuration data into the FPGA using a typical peripheral interface The interface for Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs appears in Figure 7 1 page 164 The interface for Spartan 3 FPGAs is similar but there a few minor differences as shown in Figure 7 2 page 165 The figures show optional components in gray and designated NO LOAD A list of Slave Parallel SelectMAP interface pins appears in Table 7 2 page 167 An overview of Slave Parallel functions is pro
304. ocuments IFlashPROM mcs F 3 XT File name MySPIFlashPROM mcs Oen Places Files of type all Design Files mcs exo Zi UG332 c4 04 101006 Figure 4 17 Select a Previously formatted PROM File 5 Click Open 116 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Direct Programming using iMPACT 6 Select the Part Name for a supported SPI serial Flash as shown in Figure 4 18 M25P16 a Cancel Help Select Device Part Name Select PROM Part Name UG332 c4 05 101006 Figure 4 18 Select a Supported SPI Flash Memory Device 7 Click OK 8 TheiMPACT software displays the selected SPI Flash PROM as shown in Figure 4 19 iMPACT C Data my designs led crazy led crazy 700a ipf Direct 4 File Edit View Operations Options Output Debug Window Help le A x X 22 z E t Gal Boundary Scan i 23 SlaveSerial Sa SelectMAP i Gal Desktop Configu GalDinect SPI Config y iMPACT Modes BE us myspiflashprom Program lI Program Succeeded mp Verify Erase Blank Check Readback UG332_c4_06_101006 Figure 4 19 Directly Program Supported SPI Flash PROM 9 Click Program Note Step 14 occurs later Spartan 3 Generation Configuration User Guide www xilinx com 117 UG332 v1 2 May 23 2007 Chapter 4 Master SPI Mode XILINX 10 Clic
305. ode OVERVIEW Loo oU eed bebe oe adeb ek eed eed ed oe vade e e Hed 129 Master BPI Mode Differences between Spartan 3 Generation FPGA Families 132 PROM Address Generation sssssssssssssse eee 132 Voltage Compatibility 242 ede tends perc be ved eee dae C ea abeo woo E Vade 136 Compatible Parallel NOR Flash Families 00 000005 137 Required Parallel Flash PROM Densities 0 000 0000 137 CCLK Frequency iiceasebeuutet etd rebate Ru aka ex edere o edi etc pua eas 138 Using the BPI Interface after Configuration 0008 139 Precautions Using x8 x16 Flash PROMs ssssessesseeeseeeeeen 140 Spartan 3 Generation Configuration User Guide www xilinx com UG332 v1 2 May 23 2007 EZ XILINX Daisy Chaining i crea exescesecceandessvszerdd x d ebd rade a xod deat 142 Parallel Daisy Chaining isse 142 Serial Daisy Chaining Spartan 3A 3AN 3A DSP FPGAs Only ssss 144 Using Xilinx Platform Flash PROMs with Master BPI Mode 146 ConfigRate Settings Using Platform Flash 6 6 6 cece cece 147 Generating the Bitstream for a Master BPI Configuration 148 ConfigRate CCLK Frequency 2 6 6 cece eee 148 StartupC Ik CELK iue sete pe ep ception diede ped cre tard EUR Dod cerdo bogies 148 DriveDone Actively Drive DONE Pin 0 0 0 0 148 GTS_cycle Global Three State Release Timing for Daisy Ch
306. oduction Programmers 10 11 12 13 14 Check Verify Unchecking Verify will reduce programming but iMPACT can only guarantee correct programming on a verified PROM Check Erase Before Programming Required for reprogramming Unchecking the Erase option reduces programming time for a blank device Check Load FPGA to force the FPGA to automatically reconfigure with the new PROM data after PROM programming is complete Click OK The iMPACT software indicates successful programming as shown in Figure 3 18 Production Programmers The Xilinx Platform Flash PROMs are supported by a variety of third party production programmers These programmers are the best option for high volume applications and many offer gang programming options Table 3 6 provides links to vendors that provide Platform Flash programming support The links indicate the specific programmer model numbers software versions and any programming adapters required Table 3 6 Xilinx Platform Flash Production Programmers Platform Flash Part Family Numbers Production Programmers XCFO1S XCExxS XCF028 www xilinx com support programr dev sup htm XCF00SP XCF04S XCFO8P XCFxxP XCF16P www xilinx com support programr dev_sup htm XCFOOSP XCF32P Additional Information DS123 Platform Flash In System Programmable Configuration PROMs www xilinx com bvdocs publications ds123 pdf Spartan 3 Generation Configuration User
307. oducts with shorter production lifetimes may benefit from the multi vendor pricing and multi sourcing of commodity memories 22 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Design Considerations Do you want to protect your FPGA bitstream against unauthorized duplication Like processor code the bitstream that defines the FPGA s functionality loads into the FPGA during power on Consequently this means that an unscrupulous company can capture the bitstream and create an unauthorized copy of the design Like processors there are multiple techniques to protect the FPGA bitstream and any intellectual property IP cores embedded in the FPGA The most powerful of these is called authentication and is more fully described in Chapter 15 Protecting FPGA Designs Do you want to load multiple FPGAs with the same configuration bitstream Generally there is one configuration bitstream image per FPGA in a system As shown in Figure 1 3 multiple different FPGA bitstream images can share a single configuration PROM by leveraging a configuration daisy chain However what if all the FPGAs in the application have the same part number and use the same bitstream Fortunately in this case only a single bitstream image is required An alternative solution called a ganged or broad side configuration loads multiple similar FPGAs with the same bitstream See Figure 3 5 page 71 or Figure
308. ogic Low or High value The HSWAP or PUDC B M 2 0 and VS 2 0 pins can be either dedicated or reused by the FPGA application Dedicating the HSWAP PUDC B M 2 0 and VS 2 0 Pins If the HSWAP or PUDC B M 2 0 and VS 2 0 pins are not required by the FPGA application after configuration simply connect these pins directly to the Veco or GND supply rail shown in the appropriate configuration schematic Optionally use external pull up or pull down resistors to define the appropriate logic level The external resistors provide the ability to temporarily change the logic level for debugging purposes Some of these pins have dedicated pull up resistors during configuration See Table 2 14 page 49 for recommended resistor values Be sure to define the post configuration behavior for these pins to avoid unnecessary current paths For example see Defining M 2 0 after Configuration for Minimum Power Consumption page 35 Reusing HSWAP PUDC B M 2 0 and VS 2 0 After Configuration To reuse the HSWAP or PUDC B M 2 0 and VS 2 0 pin after configuration use pull up or pull down resistors to define the logic values shown in the appropriate configuration schematic Some of these pins have dedicated pull up resistors during configuration See Table 2 14 page 49 for recommended resistor values Use the weakest external pull up or pull down resistor value acceptable in the application The resistor must be strong enough to define a logic L
309. ogic and STARTUP LCK cyde amp O pins Force all I Os Hi Z Hold all storage elements reset Disable write operations to storage elements EN USER CLOCK JTAG_CLOCK Internal Oscillator INTERNAL_CONFIGURATION_CLOCK ENABLE ERROR Configuration Error Detection CRC Checker These connections are available via the STARTUP SPARTANGE library primitive s uaAq Jo oouenbes z sajdey9 oXNIIIX 2 XILINX Boundary Scan BSCAN Chapter 13 Configuration Related Design Primitives The following configuration primitives provide access to FPGA configuration resources during or after FPGA configuration Boundary Scan BSCAN The BSCAN component shown in Figure 13 1 provides access to and from the JTAG Boundary Scan logic controller from internal FPGA logic allowing communication between the internal FPGA application and the dedicated JTAG pins of the FPGA The BSCAN primitive is not required for normal JTAG operations It is only required when implementing private JTAG scan chains within the FPGA logic Although the BSCAN primitive is functionally equivalent on all Spartan 3 Generation FPGAs the primitive name varies by family as shown in Table 13 1 page 240 Use for Spartan 3A 3AN 3A DSP BSCAN_SPARTAN3A TCK Use for Spartan 3 and Spartan 3E BSCAN SPARTANS3 TMS CAPTURE DRCK1 DRCK2 RESET TDO1 CAPTURE DRCK1
310. om the FPGA at less than 50 MHz then the BUSY pin can be left unconnected Spartan 3A 3AN 3A DSP FPGAs do not have a BUSY pin BUSY is an output from Spartan 3 and Spartan 3E FPGAs indicating when the device is ready to receive configuration data or drive Readback data e When BUSY 0 the FPGA is ready to receive or send data depending on the operation e When BUSY 1 the FPGA is not ready to receive or send data If writing to the FPGA hold the current data value until BUSY returns Low When CSI_B is deasserted CSI_B 1 the BUSY pin is in a high impedance Hi Z state BUSY remains in a Hi Z state until CSI_B is asserted If CSI_B is asserted before power up for example if the pin is tied to GND BUSY initially is in a Hi Z state then drives Low after the Power On Reset is released Continuous SelectMAP Data Loading Continuous data loading occurs when the external processor or controller provides an uninterrupted stream of configuration data to the FPGA After power up the controller asserts RDWR B 0 to write data to the FPGA and asserts CSI B 0 to select the FPGA This action causes the FPGA to drive BUSY Low which is an asynchronous transition Drive the FPGA s RDWR B pin Low before or coincident with asserting CSI B Low otherwise an ABORT occurs described in SelectMAP ABORT page 174 On the next rising CCLK edge the FPGA begins sampling the D 7 0 data pins Actual FPGA configuration begins after th
311. on drive I O configuration during configuration FPGA drives INIT B High Initialization memory clearing process Released at end of memory clearing when mode select pins are sampled INIT B Low Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 181 Chapter 8 Slave Serial Mode XILINX Table 8 1 Slave Serial Mode Connections Continued Pin Name FPGA Direction Description During Configuration After Configuration DONE Open drain FPGA Configuration Done Low indicates that the FPGA is Pulled High via external bidirectional Low during configuration not yet configured pull up When High I O Goes High when FPGA indicates that the FPGA successfully completes successfully configured configuration PROG B Input Program FPGA Active Low Must be High to allow Drive PROG B Low and When asserted Low for 300ns configuration to start release to reprogram or longer forces the FPGA to FPGA restart its configuration process by clearing configuration memory and resetting the DONE and INIT B pins once PROG B returns High R 182 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Chapter 9 JTAG Configuration Mode and Boundary Scan Xilinx Cable Header JTAG Interface Spartan 3 Generation FPGAs have a dedicated four wire IEEE 1149 1 1532 JTAG port that is always av
312. on FPGAs support basic bitstream compression The compression is fairly simple yet effective for some applications The ISE bitstream generator software examines the FPGA bitstream for any duplicate configuration data frames These duplicates occur often in the following situations e FPGA designs with unused block RAM or hardware multipliers e FPGA design with low logic utilization i e most of the FPGA array is empty The ISE software can then generate a compressed FPGA bitstream When the FPGA configures the internal configuration controller copies the redundant data frame to multiple locations Because of the extra processing required by the FPGA configuration controller the maximum configuration clock frequency is reduced to 20 MHz on Spartan 3 and Spartan 3E FPGAs as shown in Table 1 6 Spartan 3A 3AN 3A DSP FPGAs support the full CCLK frequency range even with compressed bitstreams Table 1 6 Maximum CCLK Frequency When Using Compressed Bitstream Spartan 3A Spartan 3AN Spartan 3 Spartan 3E Spartan 3A DSP FPGA FPGA FPGA Maximum CCLK Frequency When Using Compressed Bitstream BUE EIE PONI The amount of compression is non deterministic Changes to the source FPGA design may cause the size of the compressed bitstream to grow Sparse mostly empty FPGA designs 26 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Setting Bitstream Options Generating
313. on if the HSWAP input is Low See Pull Up Resistors During Configuration page 46 2 The Spartan 3E HSWAP pin and the Spartan 3A 3AN 3A DSP PUDC B pin have identical behavior just different names See Pull Up Resistors During Configuration page 46 3 CCLK is always in input pin in Slave configuration modes For Master modes CCLK must be treated as a bidirectional I O pin for Spartan 3E FPGAs 4 On Spartan 3E FPGAs the VS 2 0 pins used in Master SPI mode are shared with the A 19 17 address pins used in BPI mode Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 55 Chapter 2 Configuration Pins and Behavior during Configuration XILINX Spartan 3A 3AN 3A DSP FPGA Table 2 17 shows the various Spartan 3A 3AN 3A DSP FPGA pins that are either borrowed or dedicated during configuration Table 2 17 Spartan 3A 3AN 3A DSP FPGAs Pin Behavior during Configuration Dedicated SPI Internal BPI Pull Up Master Serial Master Parallel Slave Slave Supply Pin Name Resistor Serial Flash SPI Flash JTAG Serial Parallel I O Bank _ See pinout IP input only table TDI Yes TDI TDI TDI TDI TDI TDI TDI VCccAUX TMS Yes TMS TMS TMS TMS TMS TMS TMS VCCAUX TCK Yes TCK TCK TCK TCK TCK TCK TCK VccAux TDO Yes TDO TDO TDO TDO TDO TDO TDO Vccaux Yes PROG_B PROG_B PROG_B PROG B PROG B PROG B PROG B Vccaux Yes DONE DONE DONE DONE DONE DONE DONE VCCAUX Yes PUDC_B
314. onal clock input to the configuration Startup CLK Input sequencer selected using StartupClk UserClk bitstream option Readback Capture CAPTURE The CAPTURE primitive shown in Figure 13 3 provides FPGA application control over when to capture register flip flop and latch information for readback Spartan 3 Generation FPGAs provide the readback function through dedicated configuration port instructions CAPTURE_SPARTAN3A CAP gt CLK UG332_C13_03_081406 Figure 13 3 CAPTURE Primitive for Spartan 3A 3AN 3A DSP FPGAs other families are similar Caution On Spartan 3E FPGAs Readback is available on all devices except for the XC3S1200E and XC3S1600E in the 4 speed grade in the commercial temperature range Readback is supported on all Spartan 3E FPGAs available in the 5 speed grade or in the industrial temperature range 242 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Readback Capture CAPTURE Usage The CAPTURE primitive is optional within a design Without it Readback is still performed but the asynchronous capture function it provides for register states is not available Spartan 3 Generation FPGAs only capture register flip flop and latch states Although LUT RAM SRL and block RAM bit values are read back their values cannot be captured To capture the register states assert the CAP signal High The state is captured on the next
315. operations 30 000 000 Read cycles Extending Identifier Length As shown in Figure 15 5a most applications that use the DNA PORT primitive tie the DIN data input to a static value However other options are possible As shown in Figure 15 5b the length of the identifier can be extended by feeding the DOUT serial output port back into the DIN serial input port This way the identifier can be extended to any possible length However there are still only 55 unique bits with a 57 bit repeating pattern It is also possible to add additional bits to the identifier using FPGA logic resources As shown in Figure 15 5c the FPGA application can insert additional bits via the DNA PORT DIN serial input The additional bits provided by the logic resources could take the form of an additional fixed value or a variable computed from the Device DNA 280 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Authentication Design Examples DNA PORT DNA PORT c Bitstream specific code UG332 c15 02 120106 Figure 15 5 Possible Options for DIN Input JTAG Access to Device Identifier The FPGA s internal device identifier plus any values shifted in on the DIN input can be read via the JTAG port using the private ISC DNA command Bit 56 of the identifier shown in Figure 15 4 appears on the TDO JTAG output following an ISC DNA command The remaining bits are shifte
316. or power cycling to reconfigure It is good design practice to have the ability to assert PROG B to reset configuration if necessary Advanced Capabilities Switching between MultiBoot Configuration Memory Types The Spartan 3A 3AN 3A DSP MultiBoot feature also provides the advanced capability to jump between configuration modes and hence different types of external memory For example a Spartan 3A 3AN 3A DSP FPGA application could initially configure from an SPI serial PROM then MultiBoot from a specified location in a parallel NOR Flash and so on As shown in Figure 14 20 during a MultiBoot event the Spartan 3A 3AN 3A DSP internal configuration controller determines which FPGA configuration mode to execute By default the FPGA uses the mode select values physically defined on the FPGA s M 2 0 mode select pins Similarly if the FPGA mode pins specify the Master SPI Flash mode then the controller uses the variant select values VS 2 0 defined by the associated FPGA pins However by setting the control bit NEW MODE 1 in the MODE REG register the internal configuration controller uses the configuration mode specified by the BOOTMODE bits and if BOOTMODE 001 the variant select specified by the BOOTVSEL bits Spartan 3 Generation Configuration User Guide www xilinx com 271 UG332 v1 2 May 23 2007 Chapter 14 Reconfiguration and MultiBoot XILINX Internal Configuration Controller o zt VS2 SPI Variant Sele
317. ow or High during configuration However when driving the HSWAP or PUDC B M 2 0 or VS 2 0 pins after configuration an external output driver must be strong enough to overcome the pull up or pull down resistor value and generate the appropriate logic levels For example to overcome a 560 Q pull down resistor a 3 3V FPGA I O pin must use a 6 mA or stronger driver Spartan 3E HSWAP Considerations For Spartan 3E FPGAs the logic level on HSWAP dictates how to define the logic levels on M 2 0 and VS 2 0 as shown in Table 2 21 page 60 If the application requires HSWAP to be High connect the HSWAP pin to an external 3 3 to 4 7 kQ resistor to VCCO 0 If the application requires HSWAP to be Low during configuration then HSWAP is either connected to GND or pulled Low using an appropriately sized external pull down resistor to GND When HSWAP is Low the pin itself has an internal pull up resistor to VCCO 0 Note that Spartan 3E step 0 silicon requires that VCCINT be applied before VCCAUX when using the internal pull up on HSWAP The external pull down resistor must be Spartan 3 Generation Configuration User Guide www xilinx com 59 UG332 v1 2 May 23 2007 Chapter 2 Configuration Pins and Behavior during Configuration XILINX strong enough to define a logic Low on HSWAP for the I O standard used during configuration as shown in Table 2 14 page 49 Once HSWAP is defined use Table 2 21 to define the logic values for M 2 0 and
318. pScope tool for communications via the JTAG pins of the FPGA to the internal device logic When used with this IP this component is generally instantiated as a part of the IP and nothing more is needed by the user to ensure it is properly used However the BSCAN component can be instantiated in any FPGA design although only one BSCAN component can be used in any single design Port Descriptions Table 13 2 BSCAN Primitive Connections Port Name Direction Function TDI Output The value of the TDI input pin to the FPGA TCK Output The value of the TCK input pin to the FPGA TMS Output The value of the TMS input pin to the FPGA The value of the TCK input pin to the FPGA when the JTAG USER instruction is loaded and the JTAG TAP controller is in the SHIFT DR state DRCK1 applies to the USERI logic while DRCK2 applies to USER2 DRCK1 DRK2 Output Active upon the loading of the USER instruction It asserts RESET Output High when the JTAG TAP controller is in the TEST LOGICRESET state Indicates when the USER1 or USER2 instruction is loaded into the JTAG Instruction Register SEL1 or SEL2 becomes active in the UPDATE IR state and stays active until a new instruction is loaded SEL1 SEL2 Output 240 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Start Up STARTUP Table 13 2 BSCAN Primitive Connections Continued Port Name D
319. page 287 or Full Functionality with Time Out page 288 techniques described early the contract manufacturer can build and test the end product without risk of overbuilding or unauthorized cloning Additional Uses of Authentication and Device ID The authentication techniques described in this chapter primarily protect the FPGA application However these techniques serve other potential purposes in an application Protecting Intellectual Property IP FPGAs are a common deployment vehicle for intellectual property IP cores Authentication solves a key concern for IP vendors allowing them to protect the IP core from unauthorized copying The techniques described above also allow a vendor to protect key IP but still allow potential customers to try the core before purchase Furthermore the Device DNA feature in Spartan 3A 3AN 3A DSP FPGAs provides full traceability allowing an IP vendor to track unit shipments by a customer in order to determine royalty based payments for an IP core Code and Data Security The Spartan 3A 3AN 3A DSP FPGA s Device DNA identifier provides an additional level of security for embedded applications The Device DNA forms a key used to encrypt and decrypt both code and data to protect an embedded processor application Figure 15 15 shows an example MicroBlaze application The Spartan 3A 3AN 3A DSP Device DNA identifier forms a key to encrypt and decrypt both code and data MicroBlaze B 32 bit RISC
320. partan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX Startup Cyclic Redundancy Check Startup Steps 2 3 4 5 6 8 l l Load Startup Configuration Sequence Data 1 Wake from Reset power on or PROG B Clear Configuration l Sampl Control Synchronization Array ID Memory M 2 0 VS 2 0 Check Bitstream Setup Loading Finish UG332 c12 08 110406 a Start Figure 12 10 Cyclic Redundancy Check As the configuration data frames are loaded the FPGA calculates a Cyclic Redundancy Check CRC value from the configuration data packets After the configuration data frames are loaded the configuration bitstream by default CRC Enable issues a Check CRC instruction to the FPGA followed by an expected CRC value If the CRC value calculated by the FPGA does not match the expected CRC value in the bitstream then the FPGA pulls INIT_B Low and aborts configuration Refer to CRC Checking during Configuration page 291 for additional information Steps 1 2 3 4 5 6 7 Wake from Clear Sample Control irat Load Reset Configuration Pins Synchronization tor Configuration CRC Check power onor Memory M 2 0 VS 2 0 Data PROG B Bitstream Loading Finish UG332 c12 09 110406 Start Figure 12 11 Startup Sequence After successfully loading the configuration fram
321. partan 3A 3AN FPGAs Spartan 3A DSP FPGAs STARTUP_SPARTAN3A Spartan 3E FPGAs STARTUP_SPARTAN3E Spartan 3 FPGAs STARTUP SPARTANS3 Spartan 3 Generation Configuration User Guide www xilinx com 241 UG332 v1 2 May 23 2007 Chapter 13 Configuration Related Design Primitives XILINX Usage The STARTUP primitive must be instantiated into the design To use the dedicated GSR circuitry connect the sourcing pin or logic to the GSR pin However avoid using the GSR circuitry of this component unless certain precautions are taken first Since the skew of the GSR net cannot be guaranteed either use general routing for the set reset signal in which routing delays and skew can be calculated as a part of the timing analysis of the design or ensure that possible skew during the release of GSR will not interfere with proper circuit operation Similarly if the dedicated global 3 state is used connect the appropriate sourcing pin or logic to the GTS input pin of the primitive In order to specify a user clock for the startup sequence of configuration connect a clock from the design to the CLK pin of the STARTUP component Port Descriptions Table 13 4 STARTUP Primitive Connections Port Name Direction Function GSR Input Active High global set reset GSR signal GTS Input Active High global 3 state GTS signal Spartan 3E family only Active Low asynchronous Mas ENS MultiBoot trigger input Opti
322. pins are active and borrowed during configuration and how they function In JTAG configuration mode no user I O pins are borrowed for configuration The Dedicated Pull Up Resistors column indicates pins that always have a pull up resistor enabled during configuration regardless of the PUDC_B HSWAP or HSWAP EN input After configuration the behavior of these pins is either defined by specific bitstream generator options or by the FPGA application itself Table 2 16 and Table 2 18 show the FPGA pins that are either borrowed or dedicated during configuration The specific pins are listed by FPGA configuration mode along the top For each pin the table also indicates the power rail that supplies the pin during configuration A numeric value such as 2 indicates that the associated pin is located in I O Bank 2 and powered by the VCCO 2 supply inputs Spartan 3E and Spartan 3A 3AN 3A DSP FPGAs have four I O banks the Spartan 3 FPGA family has eight I O banks The pin names are color coded using the same colors used in the package pinout tables and footprint diagrams found in the respective Spartan 3 Generation data sheet Black represents the dedicated JTAG pins yellow represents the dedicated configuration pins light blue represents the dual purpose configuration pins that become user I O pins after configuration 54 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Spartan 3E F
323. r PUDC B pin is available as full featured user I O pin and is powered by the VCCO 0 supply Spartan 3 Generation Configuration User Guide www xilinx com 133 UG332 v1 2 May 23 2007 Chapter 5 Master BPI Mode XILINX On Spartan 3E FPGAs the RDWR B and CSI B pins must be Low throughout the configuration process although the start of configuration is delayed until CSI B is asserted After configuration these pins also become user I O The RDWR B and CSI B are not used and are ignored on Spartan 3A 3AN 3A DSP FPGAs In a single FPGA application the FPGA s CSO B and CCLK pins are not used but are actively driving during the configuration process The Spartan 3E BUSY pin not available on Spartan 3A 3AN 3A DSP FPGAs is not used but actively drives during configuration and is available as a user I O after configuration After configuration all of the interface pins except DONE and PROG B are available as user I Os Table 5 3 Byte Wide Peripheral Interface BPI Connections FPGA Pin Name Direction Description During Configuration After Configuration HSWAP Input User I O Pull Up Control When Drive at valid logic level User I O PUDC B Low during configuration throughout configuration B i enables pull up resistors in all I O pins to respective I O bank Veco input 0 Pull ups during configuration 1 No pull ups M 2 0 Input Mode Select Selects the FPGA M2 0 M1 1
324. r the configuration pins End of Startup EOS EOS indicates the absolute end of the configuration and startup process Spartan 3 FPGA Family only DCI MATCH indicates when all the Digitally Controlled Impedance DCI controllers have matched their internal resistor to the external reference resistor DCM_LOCK indicates when all the Digital Clock Managers DCMs have locked This signal is asserted by default It is active if the LOCK WAIT option is used on a DCM and the LCK cycle option is set in the bitstream Figure 12 13 is a generalized block diagram of the configuration logic showing the interaction of different device inputs and Bitstream Generator BitGen options Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 237 1002 ez Aen 2 L zeeon 8 c UJOO XUI DCAWWM p n JAS uoneanDiuo uonejouoes c uejieds weibeiq 901g jenide2uo 2160 uoneanBiuo v5d4J 3ce ueueds Sd vg NVeE Ve ueueds 4 Z4 einDi4 S0920L ZS Z ZLESA F Option Bitstream Generator BitGen Option Design Attribute Power On Reset POR POWER GOOD LOCKED DCM in User Application STARTUP_WAIT TRUE All DCMs INITIALIZATION ENABLE DONE ENABLE DONE Clear internal CMOS DS j Load application configuration latches data into CHOS configuration latches CLEARING MEMOR RESET WAIT DCMs LOCKED DONE Enable application l
325. rate The CRC engine is a one bit wide shift register as are the internal registers of the device So for each clock period one bit will be shifted into the CRC engine The total time then to run one CRC check will be the total number of configuration bits X clock period For example the XC3S50A has 437 312 bits running at 12 MHz the CRC check will take 0 0364 seconds The XC3S1400A has 4 755 296 bits running at 12 MHz the CRC check will take 0 39627 seconds 294 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Post Configuration CRC Spartan 3A 3AN 3A DSP Only Behavior when CRC Error Occurs As described earlier the FPGA flags a post configuration CRC error by driving the open drain INIT_B pin Low This is identical to the way that the FPGA flags a CRC error during configuration When the post configuration CRC feature is enabled the INIT_B pin is reserved as an open drain output with an internal dedicated pull up resistor to the VCCO_2 supply input The INIT_B pin cannot be used as an user I O when the CRC feature is enabled The POST_CRC_ACTION configuration constraint defines how the post configuration CRC checker behaves should it detect an error If POST CRC ACTION HALT then the CRC circuit stops calculating a new CRC value if an error occurs This allows an external device to check the CRC signature using Readback If POST_CRC_ACTION CONTINUE then the CRC circuit contin
326. ration the M 2 0 pin are available as user pins have optional pull up and I O pins If these pins are not defined in the FPGA pull down resistors controlled by application then these pins are treated as unused I O the M2Pin M1Pin and MOPin pins The behavior of unused I O pins is defined by the bitstream options Unless changed UnusedPin bitstream option Unless defined in the in the bitstream all three M 2 0 FPGA application or changed via the UnusedPin option have pull up resistors all three M 2 0 have internal pull down resistors DONE Pin The FPGA actively drives the DONE pin Low during configuration When the configuration process successfully completes the FPGA either actively drives the DONE pin High DriveDone or allows the DONE pin to float High using either an internal or external pull up resistor controlled by the DonePin bitstream generator option In a multi FPGA daisy chain or broadside configuration the open drain option permits the DONE lines of multiple FPGAs to be tied together so that the common node transitions High only after all of the FPGAs have successfully completed configuration Externally holding the open drain DONE pin Low stalls the Startup sequence The DONE pin is powered by the VccAux supply The DONE pin functionality is common to all Spartan 3 Generation FPGAs Associated Bitstream Generator BitGen Options The DONE pin has various option bits that controls this pin s beh
327. ration CRC feature is enabled The CAPTURE operation captures the current flip flop and latch values and writes them back to the memory cells that originally contained the initial values Spartan 3 Generation Configuration User Guide www xilinx com 297 UG332 v1 2 May 23 2007 Chapter 16 Configuration CRC XILINX Techniques to Check Distributed and Block RAM Contents As described earlier block RAM LUT RAM and SRL16 shift registers are not included as part of the CRC calculation Any RAM errors should they occur are not flagged on the INIT_B pin However it is possible to check RAM contents during operation using simple parity as shown in Figure 16 3 Each block RAM has additional bit locations specifically to store parity values The parity generator is a simple XOR gate implemented using FPGA logic Parity is generated for any data written to the block RAM The parity checker is also a simple XOR gate effectively with an additional input Parity is generated for any data value read from block RAM The generated parity value is compared against the parity bit also read from the RAM If the values are different then an odd number of bits changed within the RAM location between the time the value was written to the time it was read and checked RAMB16_S9 DI 7 0 DO 7 0 gt gt ERROR Parity Generator Parity Checker UG332_c17_02_092006 Figure 16 3 Checking Block RAM Contents Using Simple Parity Althoug
328. ration Mode and Boundary Scan XILINX iMPACT C Datamy designsXS3E Simple default ipf Boundary Scan cg File Edit View Operations Options Output Debug Window Help IPF E 4OBRW BRN d x0 ee xcf 4s xc2cB54a xc3s500e myfpga bit bypass bypass Program Ux Lc ic Rein UG332 c9 12 112006 Figure 9 14 Double Click Program to Configure FPGA via JTAG 12 Oncethe FPGA is highlighted the associated Available Operations are enabled on the display Double click Program 13 The Programming Properties dialog box appears as shown in Figure 9 15 Programming Properties Category Programming Properties t Advanced PRUM Programming Properties Revision Properties General CPLD And PROM Properties Erase Before Programming J Read Protect 15 aolHunnerll Usercode 8 Hex Digits jp PN Cancel Apply Help 4 UG332_c9_13_112006 Figure 9 15 FPGA Programming Options 14 The iMPACT software provides a Verify feature even for FPGA programming Typically the Verify function is not used when downloading the FPGA for debugging purposes 15 Click OK to start the programming process 16 The iMPACT software indicates when programming is complete as shown in Figure 9 14 The iMPACT software also forces the FPGA to reconfigure on the board The FPGA is downloaded with the specified FPGA bitstream 198 www xilinx com Spartan 3 Generation Configuration User Guide
329. ration PROM FPGA Fabric FPGA Bitstream Authentication Check Value Device DNA UG332_c16_03_040107 Figure 15 6 Spartan 3A 3AN 3A DSP FPGA Configures Normally As shown in Figure 15 7 part of the FPGA application includes circuitry that validates that the bitstream programmed into the PROM is authorized to operate on the associated Spartan 3A 3AN 3A DSP FPGA In reality the Device DNA and the authentication check value are both multi bit binary values However for the sake of clarity this example uses symbolic values In this example the FPGA s Device DNA is Blue and the configuration PROM is programmed with the check value Blueberry Spartan 3A 3AN 3A DSP FPGA Configuration PROM FPGA Bitstream Blueberry UG332_c16_04_040107 Figure 15 7 Spartan 3A 3AN 3A DSP FPGA Authenticates the PROM Image Against Device DNA After configuration the FPGA checks that the value contained in the PROM matches the value expected by the FPGA application In this example the FPGA validates that a Blueberry is indeed Blue The bitstream loaded from the PROM is authentic and the FPGA application is enabled for full operation What happens if an attacker copies the contents of an authenticated PROM shown in Figure 15 7 and uses it with a different similarly sized Spartan 3A 3AN 3A DSP FPGA If the check value in the PROM does not match the value expected by the FPGA 282 www xilinx com Spartan 3
330. ration mode Table 4 7 Example SPI Flash PROM Connections and Pin Naming Silicon Winbond Storage Atmel SPI Flash Pin FPGA Connection STMicro NexFlash Technology DataFlash Slave Data Input MOSI D DI SI SI Slave Data Output DIN Q DO SO SO Slave Select CSO B S CS CE CS Slave Clock CCLK C CLK SCK SCK Write Protect Notrequired for FPGA configuration Must W WP WP WP be High to program SPI Flash Optional connection to FPGA user I O after configuration Hold Not required for FPGA configuration but HOLD HOLD HOLD N A see Figure 4 1 must be High during configuration and programming Optional connection to FPGA user I O after configuration Not applicable to Atmel DataFlash Reset Only applicable to Atmel DataFlash Not N A N A N A RESET see Figure 4 2 required for FPGA configuration but must be High during configuration and programming Optional connection to FPGA user I O after configuration Do not connect to FPGA s PROG B as this potentially prevents direct programming of the DataFlash Ready Busy Only applicable to Atmel DataFlash and N A N A N A RDY BUSY see Figure 4 2 only available on certain packages Not required for FPGA configuration Output from DataFlash PROM Optional connection to FPGA user I O after configuration The mode select pins M 2 0 and the variant select pins VS 2 0 are sampled when the FPGA s INIT_B output goes High and mu
331. rd 1149 1 Test Access Port and Boundary Scan Architecture The architecture outlined in Figure 9 2 includes all mandatory elements defined in the IEEE 1149 1 Standard These elements include the Test Access Port TAP the TAP controller the Instruction register the instruction decoder the Boundary Scan register and the BYPASS register Spartan 3 Generation FPGAs also supports a 32 bit Identification register and a Configuration register in full compliance with the standard Outlined in the following sections are the details of the JTAG architecture for Spartan 3 Generation FPGAs Spartan 3 Generation Configuration User Guide www xilinx com 185 UG332 v1 2 May 23 2007 Chapter 9 JTAG Configuration Mode and Boundary Scan EZ XILINX y Select Next State z IEEE Standard 1149 1 Compliant Device TAP State Machine T Test Logic Reset Z 7 Run Test ldle 1 Hl A Shift IR Shift DR Select DR Select IR Vo io r Capture DR Capture IR i vo 0 Shift DR j4 o Shift IR Jo 4 Ww Exitt DR J 1 Exiti IR 40 0 rj Pause DR Pause IR 1 Exit2 DR JO Exit2 IR 1 lt Update DR ta i le 10 Y Cot ee Yi Instruction Decoder Boundary Scan n Register Select Data Register UG332 c9 0
332. re 7 3 Slave Parallel Daisy Chain for Spartan 3E Spartan 3A 3AN 3A DSP FPGAs Slave Parallel Daisy Chains Using Any Modern Xilinx FPGA Family Figure 7 4 page 170 describes an alternate Slave Parallel daisy chain scheme that supports any modern Xilinx FPGA family including all Spartan 3 Generation FPGAs The topology is similar to that shown in Figure 7 3 page 169 except that each FPGA has a separate CSI_B or CS_B chip select input Spartan 3 Generation Configuration User Guide www xilinx com 169 UG332 v1 2 May 23 2007 Chapter 7 Slave Parallel SelectMAP Mode XILINX D 7 0 M2 M1 M1 Mo INIT_B MO PROG B DONE PROG B DONE PROG B First Intermediate Last FPGA in FPGAs Daisy Chain Any Xilinx FPGA Any Xilinx FPGA UG332 c7 c4 120106 Figure 7 4 Slave Parallel Daisy Chain Using Any Modern Xilinx FPGA SelectMAP Data Loading The SelectMAP interface provides for either continuous or non continuous data loading Data loading is controlled by the FPGA s CSI B RDWR B CCLK and BUSY signals Spartan 3A 3AN 3A DSP FPGAs do not have a BUSY signal CSI B The active Low chip select input CSI B enables the SelectMAP interface When CSI B is High the FPGA ignores the SelectMAP interface The data port and BUSY output pin are high impedance Hi Z If only one device is being configured through the SelectM AP and readback is not required or if ganged SelectMAP configuration is used connect the CSI B signal to GND RDW
333. reate a PROM file for parallel NOR Flash using iMPACT from within the ISE Project Navigator If creating a Spartan 3A 3AN 3A DSP MultiBoot image for a parallel Flash memory see Generating a Spartan 3A 3AN 3A DSP MultiBoot PROM Image using iMPACT page 263 148 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Preparing an Parallel NOR Flash PROM File 1 From within the ISE Project Navigator double click Generate PROM ACE or JTAG File from within the Process pane as shown in Figure 5 7 Processes UG332_c4_10_110206 St Processes Figure 5 7 Double click Generate PROM ACE or JTAG File 2 As shown in Figure 5 8 select Prepare a PROM File iMPACT Welcome to iMPACT CE X Please select an action from the list below C Configure devices using Boundary Scan JT G WY Automatically connect to a cable and identify Boundary Scan chain Prepare a PROM File C Prepare a System ACE File C Prepare a Boundary Scan File SVF C Configure devices using Slave Serial mode Figure 5 8 Prepare a PROM File 3 Click Next Spartan 3 Generation Configuration User Guide www xilinx com 149 UG332 v1 2 May 23 2007 Chapter 5 Master BPI Mode XILINX 4 As shown in Figure 5 9 target a Generic Parallel PROM iMPACT Prepare PROM Files lel F3 want to target a C Xiling PROM WH Generic Parallel PROM C
334. recautions if System 3 3V Supply is Last in Sequence 96 Spartan 3A 3AN 3A DSP and Configuration Watchdog Timer 98 CCLK Frequency nc eret eevee PER bebe E s PER ER ERR RH 98 SPI Flash Interface after Configuration sssesessssses esses 99 If Not Using SPI Flash after Configuration 0 666 cece eee nee 99 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 EZ XILINX If Using SPI Flash Interface after Configuration eee 100 SPI Master Interface using FPGA Logic ceseeeeeeeee e 101 Accessing SPI Flash PROM 6 0 skede wy e DEG e hn 101 Accessing other SPI compatible Peripherals llle 102 Daisy Chained Configuration os 6 0 c vsedaviaudvus civedivesei isi eie pew iiss 102 Ganged or Broadside Configuration 0 0 c cece eee eee eee 104 Programming SUpPOtl ii2 civ ct ivi eat HRCRLCOHRRPHO PERHAPS rnr EUR Ah 104 Third Party Programmer Off board Programming ssssseluses 105 Direct SPI In System Programming ssssesseeee e 105 Requirements for iMPACT Direct Programming Support 000000 105 Programmable Cable Connections 2 0 6 6 0 ccc nen 106 Forcing FPGA SPI Bus Pins to High impedance During Programming 107 Direct In system Programming Using FPGA as Intermediary 108 Indirect In System Programming Using FPGA JTAG Chain 10
335. rements might be different depending on the application loaded into the FPGA and the resulting clock source 2 Subtract additional printed circuit board routing delay as required by the application 3 The initial BYTE timing can be extended using an external appropriately sized pull down resistor on the FPGA s LDC2 pin The resistor value also depends on whether the FPGA s HSWAP or PUDC B pin is High or Low Spartan 3 Generation Configuration User Guide www xilinx com 157 UG332 v1 2 May 23 2007 Chapter 5 Master BPI Mode XILINX Limitations when Reprogramming via JTAG if FPGA Set for BPI Configuration The FPGA can always be reprogrammed via the JTAG port regardless of the mode pin M 2 0 settings However there is a minor limitation if using BPI mode and versions of the ISE software prior to ISE 9 1i Service Pack 1 ISE 9 1 01i The issue with prior software releases exists for all Spartan 3A 3AN FPGA and all Spartan 3E FPGA FPGAs including both Stepping 0 and Stepping 1 The issue is resolved using ISE 9 1i Service Pack 1 or later The issue does not exist for Spartan 3A DSP FPGAs because support started in later software versions Using versions prior to ISE 9 1i Service Pack 1 if the FPGA is set to configure in BPI mode and the FPGA is attached to a parallel memory containing a valid FPGA configuration file then subsequent reconfigurations using the JTAG port will fail Potential workarounds include setting
336. requency used for the post configuration CRC Spartan 3AN 12 13 17 22 checker The available options are the same as for the Spartan 3A DSP 25 27 33 44 ConfigRate bitstream option FPGA only 50 100 Post configuration CRC checker post crc keep Spartan 3A No Default Stop checking when error detected Allows CRC Spartan 3AN signature to be read back Spartan 3A DSP Y 7 heck f f 4 3 FPGA only es Continue to check for CRC errors after an error was detected Post configuration CRC checker glutmask Spartan 3A Yes Default Mask out the Look Up Table LUT bits from the Spartan 3AN SLICEM logic slices SLICEMs support writable functions Spartan 3A DSP such as distributed RAM and SRL16 shift registers which FPGA only generate CRC errors when bit locations are modified Post No Include the LUT bits from SLICEM logic slices Use this configuration option only if the application does not include any CRC checker distributed RAM or SRL16 shift registers 224 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 x XILINX Overview Chapter 12 Sequence of Events Overview This chapter outlines the multi stage configuration process for Spartan 3 Generation FPGAs While each FPGA configuration mode uses a slightly different interface the basic steps involved are the same for all modes Figure 12 1 shows the Spartan 3 Generation FPGA configuration process The following subsections describ
337. res using BPI Up mode starting at address 0 and incrementing the addresses presented on the A 23 0 address pins When the M0 mode select pin is High a Spartan 3E FPGA configures using the BPI Down mode starting from the highest memory location A 23 0 OxFFFFFF and automatically decrementing the memory addresses Spartan 3A 3AN 3A DSP FPGAs do not support BPI Down mode Addresses are generally incremented or decremented for BPI Down mode on every falling CCLK edge The exception is when using Spartan 3A FPGAs are parts of a serial daisy chain see Serial Daisy Chaining Spartan 3A 3AN 3A DSP FPGAs Only page 144 Table 5 2 BPI Addressing Control M2 M1 MO Mode Supported Families Start Address Addressing BPI Up Spartan 3A 3AN 0 Incrementing 0 Spartan 3A DSP 0 1 Spartan 3E FPGAs 1 BPI Down Spartan 3E FPGAs OxFF FFFF Decrementing only The Spartan 3E addressing flexibility allows the FPGA to share the parallel Flash PROM with an external or embedded processor Depending on the specific processor architecture the processor boots either from the top or bottom of memory The FPGA is flexible and boots from the opposite end of memory from the processor Only the processor or the FPGA can boot at any given time The FPGA can configure first holding the processor in reset or the processor can boot first asserting the FPGA s PROG_B pin Spartan 3E FPGAs generally provide up to 24 address l
338. rising edge of CLK By default data is captured after every trigger transition on CLK while CAP is asserted To limit the readback operation to a single data capture add the ONESHOT attribute to CAPTURE devices Although the CAPTURE primitive functions equivalently on all Spartan 3 Generation FPGA families the required design primitive varies by family as indicated in Table 13 5 Table 13 5 CAPTURE Primitive by FPGA Family FPGA Family Primitive Spartan 3A 3AN FPGAs Spartan 3A DSP FPGAs CAPTURE SPARTAN3A Spartan 3E FPGAs CAPTURE SPARTANS3 Spartan 3 FPGAs For more information on Readback and the CAPTURE primitive see XAPP452 Spartan 3 Advanced Configuration Architecture Port Description Attributes Table 13 6 CAPTURE Primitive Connections Port Name Direction Description CLK Input Clock for sampling the CAP input Active High capture enable The CAP input is sampled by CAP Input the rising edge of CLK Table 13 7 describes the ONESHOT attribute available on the CAPTURE primitive Table 13 7 CAPTURE Attributes Allowed Attribute Type Values Default Description TRUE Specifies the procedure for performing NESEY Buglen FALSE PALE single readback operation per CAP trigger Spartan 3 Generation Configuration User Guide www xilinx com 243 UG332 v1 2 May 23 2007 Chapter 13 Configuration Related Design Primitives XILINX Inte
339. rive I O configuration during the configuration FPGA drives INIT B High Initialization memory clearing INIT B Low process Released at the end of memory clearing when mode select pins are sampled DONE Open drain FPGA Configuration Done Low Low indicates that the FPGA is When High indicates bidirectional during configuration Goes High not yet configured that the FPGA I O when FPGA successfully successfully configured completes configuration PROG_B Input Program FPGA Active Low Must be High to allow Drive PROG_B Low and When asserted Low for 500 ns or longer forces the FPGA to restart its configuration process by clearing configuration memory and resetting the DONE and INIT_B pins once PROG_B returns High configuration to start release to reprogram FPGA Voltage Compatibility Most Slave Parallel interface signals are within the FPGA s I O Bank 2 supplied by the VCCO 2 supply input The VCCO 2 voltage can be 1 8V 2 5V or 3 3V to match the requirements of the external host ideally 2 5V Using 1 8V or 3 3V requires additional design considerations as the DONE and PROG B pins are powered by the FPGA s 2 5V VccaAux supply See XAPP453 The 3 3V Configuration of Spartan 3 FPGAs for additional information Also see JTAG Cable Voltage Compatibility page 184 Daisy Chaining If the application requires multiple FPGAs with different configurations then configure the FPGAs using a daisy
340. rnal Configuration Access Port ICAP Usage The Internal Configuration Access Port ICAP shown in Figure 13 4 is only available on the Spartan 3A 3AN 3A DSP FPGA families See the Spartan 3AN Errata regarding limitations on using ICAP after configuration from the in system Flash The ICAP SPARTANS3A primitive works similar to the Slave Parallel Select MAP configuration interface except it is available to the FPGA application using internal routing connections Furthermore the ICAP primitive has separate read and write data ports as opposed to the bidirectional bus on the Slave Parallel SelectMAP interface ICAP allows the FPGA application to access configuration registers readback configuration data or to trigger a MultiBoot event after configuration successfully completes For additional information on the Slave Parallel SelectMAP interface see Chapter 7 Slave Parallel SelectMAP Mode For additional information on Spartan 3A 3AN 3A DSP MultiBoot Chapter 14 Reconfiguration and MultiBoot ICAP_SPARTAN3A 0 7 O 0 7 UG332_C13_04_111906 Figure 13 4 ICAP Primitive only available on Spartan 3A 3AN 3A DSP FPGAs 244 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Device DNA Access Port DNA_PORT Port Description Caution Xilinx convention defines I0 and OO as the most significant bits I7 and O7 are the least significant bits Th
341. rol the operation of the configuration state machine Each command consists of five bits as shown in Table 14 7 262 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Spartan 3A 3AN 3A DSP MultiBoot Table 14 7 CMD Register Definition CMD Address 00 0101 0x05 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 REBOOT Reserved Command 0 1 1 1 0 Only one command is required for MultiBoot operations the REBOOT command which is binary 01110 Configuration Mode Register MODE REG The configuration mode register MODE REG defines which configuration mode the FPGA uses upon the next MultiBoot trigger event The NEW MODE bit defines whether the FPGA uses the M 2 0 mode settings defined by the M 2 0 pins of the FPGA or whether the FPGA uses the settings defined by the BOOTMODE and BOOTVSEL bits Setting NEW MODE 1 allows the FPGA to MultiBoot to a different type of attached memory Table 14 8 describes the bit options available in the MODE REG register Table 14 8 MODE REG Bit Options MODE REG Address 01 0101 0x15 Name Bit s Description Default Reserved 15 7 Reserved 0 0 Sample M 2 0 pins and if in SPI mode the VS 2 0 pins to determine MultiBoot configuration mode NEW MODE 6 1 Use BOOTMODE value to determine MultiBoot 0 configuration mode and BOOTVSEL to determine which SPI command to issue if BOOTMODE set for SP
342. s fastest possible configuration time the more important consideration Some applications require that the logic be operational within a short time Certain FPGA configuration modes and methods are faster than others The configuration time includes the initialization time plus the configuration time Configuration time depends on the size of the device and speed of the configuration logic For example an XC3S1400A programming at 10 MHz will require 4755296 bits 10 MHz or approximately 500 ms e At the same clock frequency parallel configuration modes are inherently faster than the serial modes since they program 8 bits at a time e Configuring a single FPGA is inherently faster than configuring multiple FPGAs in a daisy chain In a multi FPGA design where configuration speed is a concern configure each FPGA separately and in parallel e In Master modes the FPGA internally generates the CCLK configuration clock signal By default the CCLK frequency starts out low but can be increased using the ConfigRate bitstream option The maximum supported CCLK frequency setting depends on the read specifications for the attached nonvolatile memory A faster memory may allow for faster configuration e Furthermore in Master modes the FPGA s CCLK output frequency varies with process voltage and temperature The fastest guaranteed configuration rate depends on the slowest guaranteed CCLK frequency as shown in the respective data sheet If an extern
343. s Connect to PROM User I O If the FPGA outputs address inputs FPGA does not access A 23 0 the PROM after 2 configuration drive rune spn igh deselect the PROM Spartan 3A DSP A 23 0 D 7 0 GA LDC 2 1 and HDC A 25 0 then become available as user I O D 7 0 Master Input Data Input Data captured by User I O If bitstream Parallel FPGA option Persist Yes BPI Slave becomes part of Parallel SelectMap parallel SelectMAP peripheral interface Spartan 3 BPI Slave Output FPGA Busy Indicator Used Not used during BPI User I O If bitstream Spartan 3E Parallel primarily in Slave Parallel mode configuration option Persist Yes FPGA SelectMAD interfaces that operate at but actively drives becomes part of BUSY 50 MHz and faster SelectMap parallel peripheral interface Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 53 Chapter 2 Configuration Pins and Behavior during Configuration XILINX Pin Behavior During Configuration Table 2 16 shows how various pins on Spartan 3E or Spartan 3A 3AN 3A DSP FPGAs behave during the configuration process The actual behavior depends on the settings applied to the M2 M1 and MO M 2 0 mode select pins and the pin that controls the optional pull up resistors called HSWAP PUDC B or HSWAP EN depending on the specific Spartan 3 Generation FPGA family The M 2 0 mode select pins determine which of the I O
344. s High indicates the number of clock Spartan 3AN cycles as defined by the sw_clk setting when the global Spartan 3A DSP write protect lock is released for writable clocked elements FPGA only flip flops block RAM etc The default value is five clock Suspend mode cycles after the AWAKE pin goes High Generally this value wake up timing is equal to or greater than the sw gts cycle setting sw gts cycle Spartan 3A 1 4 1024 After the AWAKE pin is High indicates the number of clock Spartan 3AN Spartan 3A DSP FPGA only Suspend mode wake up timing cycles as defined by the sw_clk setting when the I O pins switch from their SUSPEND Constraint settings back to their normal functions The default value is four clock cycles after the AWAKE pin goes High Generally this value is equal to or less than the sw gwe cycle setting Spartan 3A 3AN 3A DSP MultiBoot Control Options See Spartan 3A 3AN 3A DSP MultiBoot page 257 ICAP Enable Spartan 3A Auto Default The BitGen software examines the FPGA design If Spartan 3AN the ICAP primitive is instantiated in the design BitGen Spartan 3A DSP automatically sets ICAP Enable Yes enabling the ICAP port FPGA only Otherwise ICAP_Enable No ICAP MultiBoot No The ICAP port is disabled Yes The ICAP port is enabled next config addr Spartan 3A 0x0000000 Specifies the next MultiBoot start address as a 7 character Spartan 3AN Spartan 3A DSP FPGA only
345. s by Spartan 3 Generation Family Spartan 3A 3AN Spartan 3 Spartan 3E Spartan 3A DSP Voltage Range FPGA FPGA FPGA Units VCcCAUX or Veco 3 0 to 3 6V 5 1 to 23 9 Veco 3 0 to 3 45V 1 27to4 11 24 to 10 8 Q VCCAUX or Veco 2 3 to 2 7V 1 15 to 3 25 2 7 to 11 8 6 2 to 33 1 Veco 1 7 to 1 9V 245to9 10 4 3 to 20 2 8 4 to 52 6 Table 2 14 Recommended External Pull Up or Pull down Resistor Values to Define Input Values during Configuration Spartan 3A 3AN PUDC_B HSWAP or Desired Pull Spartan 3 Spartan 3E Spartan 3A DSP HSWAP_EN Direction I O Standard FPGA FPGA FPGA 0 5 No pull up required Internal pull up resistors are also applies to all Paleup AN enabled See Table 2 13 for resistor range pins that have a LVCMOS dedicated pull up pe a lt 3300 lt 6200 lt 11kQ resistor during Pull Down configuration vd required to IVCMOS25 lt 470Q lt 820 Q lt 1 8 kQ Pins with Dedicate i overcome maximum Pull Up Resistors loccicurtentand LVCMOS18 lt 510 lt 8200 lt 3 3kQ m RM guarantee Vj LVCMOSI5 lt s0Q lt 12kQ lt 54kQ Configuration page 46 LVCMOS12 lt 15kQ lt 15kQ lt 96kQ 1 LVCMOS33 lt lt optional pull up Pull Up LVTTL SED S 10042 ist disabled i cae e required to LVCMOS25 lt 60kQ auring overcome single e Does load maximum Ij LVCMOS18 37kQ not apply to pins leakage curr
346. s to another task or services an interrupt There are two methods to throttle or pause the configuration data throughput 1 Deassert the CSI B signal with a free running CCLK shown in Figure 7 6 and described in Deasserting CSI B page 173 2 Pause CCLK shown in Figure 7 7 and described in Pausing CCLK page 174 Deasserting CSI B PROG B wrB fe 29999 888 CCLK CSI B DATA XXX RDWR B BUSY N 0 a M UG332 c7 06 040207 Figure 7 6 SelectMAP Non Continuous Data Loading with Controlled CSI B The following numbered items correspond to the markers provided in Figure 7 6 1 The external processor drives RDWR B Low setting the FPGA s D 7 0 pins as inputs for configuration The RDWR B input can be tied Low if Readback is not used in the application ROWR_B should not be toggled after CSI B has been asserted because this triggers an ABORT described in SelectMAP ABORT page 174 The FPGA is ready for configuration after INIT B returns High The processor asserts CSI B Low enabling the SelectMAP interface The CSI B input can be tied Low if there is only one device on the SelectMAP bus If CSI B is not tied Low it can be asserted at any time 4 BUSY goes Low shortly after CSI B is asserted If CSI B is tied Low BUSY is driven Low before INIT B returns High A D 7 0 data byte is loaded on the rising CCLK edge A D 7 0 data byte is loaded on the rising CCLK edge
347. scriptions Table 13 9 DNA PORT Primitive Connections Port Name Direction Function DOUT Output Serial shifted output data DIN Input User data input to the shift register Synchronous load of the shift register with the Device READ Input DNA data A READ operation overrides a SHIFT operation SHIFT Input Active high shift enable input CLK Input Clock Input Attributes Table 13 10 DNA PORT Attributes Allowed Attribute Type Values Default Description Anv 57 bit Specifies a DNA value for simulation purposes SIM DNA VALUE 57 bit vector d alus All zeros the actual value will be specific to the a particular device used 246 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 x XILINX Overview Chapter 14 Reconfiguration and MultiBoot Overview Because Spartan 3 Generation FPGAs are reprogrammable in the system some applications reload the FPGA with one or more bitstream images during normal operation In this way a single smaller FPGA reprogrammed multiple times replaces a much larger and more expensive ASIC or FPGA programmed just once There are a variety of methods to reprogram the FPGA during normal operation The downloaded configuration modes see Figure 1 2 page 14 inherently provide this capability Via an external intelligent agent such as a processor microcontroller computer or tester an FPGA can be reprogramme
348. se pins have an optional internal pull up resistor to their respective Vcco supply pin that is active throughout configuration if the HSWAP input is Low 2 CCLK is always in input pin in Slave configuration modes For Master modes CCLK must be treated as a bidirectional I O pin Default I O Standard During Configuration When the FPGA first powers up or after PROG_B is pulsed Low the FPGA s I O pins are unconfigured However the FPGA pins involved in the configuration process are predefined to the settings shown in Table 2 19 Table 2 19 Default I O Standard Setting During Configuration Output Pin s I O Standard Drive Slew Rate All including CCLK LVCMOS25 8mA Slow By default the I O pins are set for LVCMOS25 operation or 2 5V low voltage CMOS The setting is the same for both the Dedicated and Dual Purpose pins However the Dual Spartan 3 Generation Configuration User Guide www xilinx com 57 UG332 v1 2 May 23 2007 Chapter 2 Configuration Pins and Behavior during Configuration XILINX Purpose pins can drive at different voltages depending on the voltage applied to the relevant I O bank The Dedicated configuration pins see Table 2 16 page 55 and Table 2 18 page 57 are always powered by VccAux On Spartan 3 and Spartan 3E FPGA families VccAUx is always 2 5V as shown in Table 2 18 On Spartan 3A 3A DSP FPGAs VccAux can be either 2 5V or 3 3V On Spartan 3AN FPGAs VccAux is always 3
349. ser Guide www xilinx com 213 UG332 v1 2 May 23 2007 Chapter 10 Internal Master SPI Mode XILINX Table 10 6 BPM Microsystems Programmers Supporting Spartan 3AN FPGAs Status Programmer Model Number Programmer Type 3610 4610 4710 3710MK2 Automated Production Recommended for new installations available for BP 2610 purchase Multi site Concurrent BP 2710 BP 1410 BP 1610 Single site Engineering BP 1710 4700 3700MK2 BP 3500 BP 3510 Automated Production BP 3600 BP 4500 Legacy model May already be installed in BP 4510 many programming BP 4600 centers BP 2500 BP 2510 Multi site Concurrent BP 2600 BP 2700 BP 1600 Single site Engineering BP 1700 214 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Third Party Programmer Support Programming Socket Modules and Software Table 10 7 lists the socket adapters and software required to program Spartan 3AN FPGAs on the programming solutions shown in Table 10 6 Check the BPM Microsystems web site for the most up to date information Table 10 7 BPM Microsystems Socket Modules and Software for Spartan 3AN FPGAs BPM Microsystems Socket Module Spartan 3AN FPGA Model Number Programming Software XC3S50AN ASM256BGT XC3S200AN SM256BCT BPWin V4 66 0 and later
350. st be at defined logic levels during this time After configuration when the FPGA s DONE output goes High these pins are all available as full featured user I O pins B Similarly the FPGA s HSWAP or PUDC B pin must be defined Set Low to enable pull up resistors on all user I O pins during configuration or High to disable the pull up resistors The HSWAP or PUDC B control must remain at a constant logic level throughout FPGA configuration After configuration when the FPGA s DONE output goes High the Spartan 3 Generation Configuration User Guide www xilinx com 93 UG332 v1 2 May 23 2007 Chapter 4 Master SPI Mode XILINX HSWAP or PUDC B pin is available as full featured user I O pin and is powered by the VCCO 0 supply The FPGA s DOUT pin is used in daisy chain applications described in Daisy Chained Configuration page 102 In a single FPGA application the FPGA s DOUT pin is in active but pulled High via an internal resistor Ww The SPI Flash PROM s Write Protect and Hold controls are not used by the FPGA during configuration although the Hold pin must be High during the configuration process The PROM s Write Protect input must be High in order to write or program the Flash memory Table 4 8 Serial Peripheral Interface SPI Connections FPGA Pin Name Direction Description During Configuration After Configuration HSWAP Input User I O Pull Up Control W
351. st contain an SPI bus master interface Xilinx provides SPI interface cores as described below e For an application that already includes a MicroBlaze processor core the Xilinx Embedded Development Kit EDK includes an SPI interface that connects to the MicroBlaze OPB bus Depending on the options used the SPI interface core uses between 147 to 203 slices OPB Serial Peripheral Interface Product Specification www xilinx com bvdocs ipcenter data sheet opb spi pdf e For general applications the 8 bit PicoBlaze controller core offers an easy to use solution that requires approximately 100 slices and a block RAM Example design solutions are available for the Spartan 3E Starter Kit board PicoBlaze STMicro SPI Flash Programmer www xilinx com products boards s3estarter reference designs htmftpicoblaze spi flas h programmer PicoBlaze SPI based D A Converter Controller www xilinx com products boards s3estarter reference designs htmftpicoblaze dac control Accessing SPI Flash PROM SPI Flash PROMs are available in densities ranging from 1 Mbit up to 128 Mbits However a single Spartan 3A 3E FPGA requires less than 6 Mbits A Spartan 3A DSP FPGA requires a little more than 11 Mbits If desired use a larger SPI Flash PROM to contain additional nonvolatile application data such as MicroBlaze processor code or other user data such as serial numbers and Ethernet MAC IDs In the example shown in Fi
352. supports programming multiple identical FPGAs with the same bitstream Koy KOM P SPI Serial Flash PROM M2 M1 MO DOUT CSOB INIT B PROG B DONE Master FPGA PROGRAM E 4 E M2 M1 MO CCLK DIN DOUT INIT B PROG B DONE Slave FPGA UG332 c4 21 111906 Figure 4 7 Multiple Identical FPGAs Programmed with the Same Bitstream Programming Support In production applications the SPI Flash PROM is usually preprogrammed before it is mounted on the printed circuit board The Xilinx ISE development software produces industry standard programming files that can be used with third party gang programmers Consult your specific SPI Flash vendor for recommended production programming solutions There are multiple programming methods for the attached SPI memory as described below Starting with ISE 9 1i Service Pack 2 and later the iMPACT programming software supports two different methods to program an attached SPI Flash PROM as summarized in Table 4 12 Using the Direct Programming Method the programming cable communicates directly to the SPI Flash PROM The FPGA is not involved in the programming process and the FPGA 104 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Programming Support I O pins that connect to the PROM must be in their high impedance state Hi Z during programming Hold the FPGA s PROG_B input Low to place the I Os in Hi Z the FP
353. synchronization word shown in Table 12 3 page 230 Alternatively leave the space between locations programmed with 0xFF which is the same state as an unprogrammed Flash location MultiBoot Command Sequence ICAP Example The following steps are required to initiate a MultiBoot reconfiguration event from within the FPGA application using the ICAP design primitive MultiBoot events can also be issued via JTAG the Slave Serial or the Slave Parallel SelectMAP interface The specific bit sequences supplied below are for the ICAP interface but the same general approach also applies for the other interfaces Caution By Xilinx convention data bit DO is the most significant bit In many other conventions data bit D7 is the most significant bit In the application ensure that the correct value is being written to the ICAP interface either by adjusting the data written to the interface or by reversing the wiring connections to the interface Design Specification Enable the ICAP interface which is required for MultiBoot functionality in the FPGA configuration bitstream using the ICAP Enable Auto or ICAP_Enable Yes bitstream generator option setting Caution The ICAP interface will not be available until the first configuration has completed startup including the End of Startup cycle Allow a few additional clock cycles after the end of configuration before beginning the ICAP MultiBoot sequence See Startup in Chapter 12 Spartan 3
354. t Yes Spartan 3AN becomes part of Spartan 3A DSP SelectMap parallel CSI B peripheral interface Spartan 3 CS B RDWR B Input Read Write Control Active Low Must be Low throughout User I O If bitstream write enable configuration Do not change option Persist Yes the state of RDWR B while becomes part of CSI B or CS B is asserted SelectMap parallel otherwise an ABORT is issued peripheral interface CCLK Input Configuration Clock If CCLK External clock User I O If bitstream option Persist Yes becomes part of SelectMap parallel peripheral interface Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 167 Chapter 7 Slave Parallel Select MAP Mode XILINX Table 7 2 Slave Parallel Mode Connections Continued FPGA Pin Name Direction Description During Configuration After Configuration Spartan 3E Output Chip Select Output Active Low Not used in single FPGA User I O Spartan 3A Not provided on Spartan 3 designs CSO_B is pulled up Spartan 3AN FPGAs not actively driving Ina Spartan 3A DSP Spartan 3E or Spartan CSO B 3A 3AN 3A DSP parallel ni daisy chain configuration this pin connects to CSI B or CS B input of the next FPGA in the chain INIT B Open drain Initialization Indicator Active Active during configuration If User I O If unused in bidirectional Low Goes Low at the start of CRC error detected during the application d
355. t cloning and even to protect an intellectual property IP core implemented within an FPGA This chapter covers the following design security topics e Basic FPGA Hardware Level Security Options page 273 e Approaches to Design Security page 276 e Spartan 3A 3AN 3A DSP Unique Device Identifier Device DNA page 278 e Authentication Design Examples page 281 e U S Legal Protection of FPGA Configuration Bitstream Programs page 289 Basic FPGA Hardware Level Security Options Spartan 3 Generation FPGAs provide advanced debugging capabilities via a function called Readback Similarly the FPGA generally allows full access to all configuration operations However for security conscious applications the Readback function and configuration operations especially via JTAG provide a potential point of attack Fortunately the FPGA bitstream optionally restricts access to configuration and readback operations By default there are no restrictions and the JTAG port is always active providing access to configuration and Readback The SelectMAP configuration interface which can also be used to perform Readback is disabled by default and is not available unless specifically enabled by setting the Persist Yes bitstream option The only way to remove a security setting in a configured FPGA is to clear the FPGA program by asserting PROG B or cycling power Spartan 3 Generation Configuration User Guide www xilinx com 2
356. t of each FPGA s INIT B and DONE pin is recommended for debugging purposes Should there be a configuration error the FPGAs can be individually isolated The jumper on the master FPGA s DONE pin is recommended for future in system programming support as well as for debugging purposes The pull up resistors shown in gray are optional but should be provided in the board design The resistors themselves do not need to be stuffed during board manufacturing As described in Table 2 13 page 49 the dedicated pull up resistors on Spartan 3 Generation FPGAs are sufficiently strong to pull up the corresponding signal pin The Thevenin termination resistors on CCLK are also optional but also recommended in the board design QO E M2 M1 MO M2 M1 MO CCLK DIN DOUT CSO B INIT B INIT B PROG B DONE Master FPGA UG332 c4 20 111906 Figure 4 6 Daisy Chaining from SPI Flash Mode Spartan 3 Generation Configuration User Guide www xilinx com 103 UG332 v1 2 May 23 2007 Chapter 4 Master SPI Mode XILINX Ganged or Broadside Configuration Daisy Chained Configuration is designed to load multiple FPGAs each with a different design and typically of different array size However some applications include multiple identical FPGAs all programmed with the same bitstream Instead of daisy chaining the FPGAs and storing multiple copies of the same bitstream Ganged or Broadside Configuration
357. tGen settings Pull up during Spartan 3E and Spartan 3A 3AN 3A DSP Configuration FPGAs User I O after configuration control input Controlled by the FPGA application HSWAP VCCO 0 Spartan 3 FPGA Controlled by HswapenPin PUDC_B or BitGen setting HSWAP_EN Spartan 3E 3A 3ANI Spartan 3A DSP FPGAs User I O after configuration Controlled by the FPGA application VCCO_2 INIT_B Spartan 3 FPGA VCCO_4 or VCCO_BOTTOM TDI Vec AUX TdiPin BitGen setting TMS VCCAUX TmsPin BitGen setting TCK VCCAUX TckPin BitGen setting TDO VCCAUX TdoPin BitGen setting As highlighted in Table 2 2 page 34 the Spartan 3A 3AN 3A DSP FPGA family adds a few more dedicated internal pull up resistors as shown in Table 2 10 On Spartan 3E FPGAs these pins do not have a dedicated internal pull up resistor but do have an optional pull up resistor controlled when HSWAP 0 Table 2 10 Pins with Dedicated Pull Up Resistors during Configuration Spartan 3A 3AN 3A DSP FPGA Family Only Pull Up Resistor Pin Name Supply Rail Post Configuration Control M 2 0 VCCO 2 User I O after configuration Controlled by the FPGA application Pull up resistors only active when M 2 0 lt 0 0 1 gt Master VS 2 0 VCCO 2 SPI mode User I O after configuration Controlled by the FPGA application Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 www xilinx com 47 Chapter 2 Configuration Pins and
358. tan 3 Generation FPGAs can be downloaded or programmed by an external smart agent such as a microprocessor DSP processor microcontroller PC or board tester In either case the configuration data path is either serial to minimize pin requirements or byte wide for maximum performance or for easier interfaces to processors or to byte wide Flash memory Similar to both processors and processor peripherals Xilinx FPGAs can be reprogrammed in system on demand an unlimited number of times After configuration the FPGA configuration bitstream is stored in highly robust CMOS configuration latches CCLs Although CCLs are reprogrammable like SRAM memory CCLs are designed primarily for data integrity not for performance The data stored in CCLs is written only during configuration and remains static unless changed by another configuration event Design Considerations Before starting a new FPGA design spend a few minutes to consider which FPGA configuration mode best matches your system requirements Each configuration mode dedicates certain FPGA pins and may borrow others Similarly the configuration mode may place voltage restrictions on some FPGA I O banks If you have already selected an FPGA configuration mode feel free to jump to the relevant section in the user guide Otherwise please evaluate the following design considerations to understand the options available Spartan 3 Generation Configuration User Guide www xilinx com 11
359. te presented first followed by the low byte Note that DO is the most significant bit msb for the ICAP interface which is the opposite direction from most processors Table 14 2 Command Sequence to Initiate MultiBoot from a Preloaded Address CLK High or Cycle Command Low Byte DO D1 D2 D3 D4 D5 D6 D7 Hex 1 High 1 0 1 0 1 0 1 0 OxAA SYNC WORD 2 Low 1 0 0 1 1 0 0 1 0x99 3 Type 1 Write CMD High 0 0 1 1 0 0 0 0 0x30 4 1 Word Low trueque vu ae fa 0 1 0xA1 5 High 0 0 0 0 0 0 0 0 0x00 REBOOT Command 6 Low 0 0 0 0 1 1 1 0 OxOE 7 High 0 0 1 0 0 0 0 0 0x20 No Op 8 Low 0 0 0 0 0 0 0 0 0x00 MultiBoot to a Address Specified by the FPGA Application Table 14 3 shows an example where the FPGA application specifies the address of the next MultiBoot image This specific example is for SPI serial Flash but parallel NOR Flash is similar with slightly different definitions of the bits written to the GENERAL2 register CLK cycles 9 and 10 260 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Spartan 3A 3AN 3A DSP MultiBoot Each 16 bit command is written as two bytes to the ICAP interface with the high byte presented first followed by the low byte Note that DO is the most significant bit msb for the ICAP interface which is the opposite direction from most processors The sequence in Table
360. te bitstream generator option The maximum frequency supported by the FPGA configuration logic depends on the timing for the SPI Flash device Without examining the timing for a specific SPI Flash PROM use ConfigRate 12 or lower SPI Flash PROMs that support the FAST READ command support higher data rates 98 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX SPI Flash Interface after Configuration Some such PROMs support up to ConfigRate 25 and beyond but require careful data sheet analysis See Serial Peripheral Interface SPI Configuration Timing page 124 for more detailed timing analysis Table 4 11 lists the various ConfigRate setting options and the corresponding clock to output requirement Ty for the SPI Flash PROM The Ty value is determined according to the equation in Table 4 16 page 126 Spartan 3A 3AN 3A DSP FPGAs have more ConfigRate settings than Spartan 3E hence the shaded cells under the Spartan 3E column Unless a ConfigRate setting is specified when generating the bitstream the FPGA always uses the default slowest setting of ConfigRate 1 which lengthens the overall configuration time Table 4 11 FPGA ConfigRate Setting and Corresponding SPI Flash PROM Clock to Output Requirements Ty SPI Flash Maximum Ty Specification Spartan 3E ConfigRate Bitstream P Spartan 3A 3AN Setting Commercial Industrial Spartan 3A DSP Uni
361. tement could be added to the PCB such as Bitstream proprietary to XYZ Company Copying or other use of the bitstream program except as expressly authorized by XYZ Company is prohibited To the extent that documentation data books or other literature accompanies the FPGA based design appropriate wording should be added to this literature providing third parties with notice of the user s claim of copyright and trade secret in the bitstream program For example this notice could read Bitstream 2006 XYZ Company All rights reserved The bitstream program is proprietary to XYZ Company and copying or other use of the bit stream program except as expressly authorized by XYZ Company is expressly prohibited To help prove unauthorized copying by a third party additional nonfunctional code should be included at the end of the bitstream program Therefore should a third party copy the bitstream program without proper authorization if the non functional code is present in the copy the copier cannot claim that the bitstream program was independently developed These are only suggestions and Xilinx makes no representations or warranties with respect to the legal effect or consequences of the above suggestions Each end user company is advised to consult legal counsel with respect to seeking protection of a bitstream program and to determine the applicability of these suggestions to the specific circumstances 290 www xilinx com Sp
362. the BPI Master Device is either a Spartan 3E or Spartan 3A FPGA 13 If the Spartan 3E option is selected then choose whether the PROM file is loaded at address 0 using incrementing addresses BPI Up or at the highest address location using decrementing addresses BPI Down This option is not available if the Spartan 3A option is the selected BPI Master Device 14 If the Spartan 3A option is selected then choose whether to create a Parallel or Serial configuration daisy chain This option is not available if the Spartan 3E option is the selected BPI Master Device although Spartan 3E FPGAs support parallel daisy chains 15 Click Next Spartan 3 Generation Configuration User Guide www xilinx com 151 UG332 v1 2 May 23 2007 Chapter 5 Master BPI Mode XILINX 16 As shown in Figure 5 11 start selecting the FPGA bitstreams to store in the PROM i 22 Would you like to add another design file to NI Data Stream 0 Look in 3 led crazy D 4 i You have completed the device file entry first fpa bk 4 Click Ok to continue E second fpqa bit Start adding device file to Data Stream 0 amp ccna File name Places i Files of type FPGA Bit Files bit x first fpga bit UG332 c5 12 111806 Figure 5 11 Select FPGA Bitstream Files 17 This example create a PROM file for a Spartan 3A serial daisy chain Select the first FPGA bitstream
363. the Platform Flash PROM Vcco supply input must be the same voltage A 2 5V only interface is easiest as all signals are the same voltage A 3 3V interface is also supported but the FPGA PROG_B and DONE pins require special attention as they are powered by the FPGA Vccaux supply nominally 2 5V See application note XAPP453 The 3 3V Configuration of Spartan 3 FPGAs for additional information Spartan 3 FPGAs The Spartan 3 FPGA s VCCO 4 supply input and the Platform Flash PROM Vcco supply input must be the same voltage A 2 5V only interface is easiest as all signals are the same voltage A 3 3V interface is also supported but the FPGA PROG B DONE and CCLK pins require special attention as they are powered by the FPGA Vccayx supply nominally 2 5V See application note XAPP453 The 3 3V Configuration of Spartan 3 FPGAs for additional information JTAG Interface If the Platform Flash PROM is the last device in the chain then the JTAG interface voltage is easily controlled by the PROM s VCCJ supply If the FPGA s VccAux supply is 2 5V and the JTAG chain is also 2 5V the interface is simple To create a 3 3V JTAG interface even when the FPGA s VccAux supply is 2 5V connect VCCJ to 3 3V and provide current limiting resistors on the FPGA s TDI TMS and TCK JTAG inputs 68 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Supported Platform Flash PROMs For Spartan 3A 3A DSP FPGA
364. the StartupClk bitstream generation option shown as Step 13 in Figure 1 8 page 30 g StartupClk Cclk DriveDone Actively Drive DONE Pin In a single FPGA design or for the Master FPGA in a multi FPGA daisy chain set the FPGA to actively drive the DONE pin after successfully completing the configuration process Using ISE Project Navigator check the Drive Done Pin High option shown as Step 16 in Figure 1 8 page 30 g DriveDone Yes Programming a Spartan 3AN FPGA Using JTAG 204 A Spartan 3AN FPGA is programmed using JTAG and iMPACT software in the same way described for other FPGA families in Programming an FPGA Using JTAG in Chapter 9 The iMPACT software only requires associating a bistream with the FPGA and will automatically generate the PROM file for the In System Flash program the Flash in the Spartan 3AN FPGA and then configure the Spartan 3AN FPGA from the In System Flash See Mode Pin Considerations when Programming a Spartan 3AN FPGA via JTAG using iMPACT in Chapter 9 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Preparing an In System Flash Programming File Preparing an In System Flash Programming File This section provides guidelines to create a programming file for the Spartan 3AN In System Flash ISF memory These steps are not needed when programming a single bitstream into the ISF using iMPACT Caution Requires ISE 9 1i Service Pack 3 or
365. the VccAux supply can be either 2 5V or 3 3V If Vecaux is 3 3V then a 3 3V JTAG interface is also easy No current limiting resistors are required See also JTAG Cable Voltage Compatibility page 184 Supported Platform Flash PROMs Table 3 4 shows the smallest available Platform Flash PROM to program one Spartan 3 Generation FPGA A multiple FPGA daisy chain application requires a Platform Flash PROM large enough to contain the sum of the various FPGA bitstream sizes Table 3 4 Number of Bits to Program a Spartan 3 Generation FPGA and Smallest Platform Flash PROM Number of Smallest Possible Family FPGA Configuration Bits Platform Flash PROM XC3S50A 437 312 XCFO01S XC3S200A 1 196 128 XCF02S Spartan 3A XC3S400A 1 886 560 XCF02S Spartan 3AN xC96700A 2 732 640 XCF04S XCF08P XC3S1400A 4 755 296 or XCF04S XCF02S XCF08P cT XC3SD1800A 8 197 280 ads role PRONE XC3SD3400A 11 718 304 XCF16P XC3S100E 581 344 XCFO01S XC3S250E 1 353 728 XCF02S Spartan 3E XC3S500E 2 270 208 XCF04S XC3S1200E 3 841 184 XCF04S XCF08P XC3S1600E 5 969 696 or XCF04S XCF02S XC3S50 439 264 XCFO01S XC3S200 1 047 616 XCFO01S XC3S400 1 699 136 XCF02S XC3S1000 3 223 488 XCF04S Spartan 3 XCFO8P ore 9 214 784 or XCF04S XCF02S XCF08P XC382000 7 673 024 or 2 x XCF04S XC384000 11 316 864 XCF16P XC3S5000 13 271 936 XCF16P There are two possible design solutions for FPGA designs t
366. the mode pins for JTAG configuration M 2 0 lt 1 0 1 gt or offsetting the bitstream start address in Flash by 0x2000 Spartan 3E BPI Mode Interaction with Right and Bottom Edge Global Clock Inputs 158 Some of the Spartan 3E BPI mode configuration pins are shared with global clock inputs along the right and bottom edges of the device Bank 1 and Bank 2 respectively These pins are not easily reclaimable for clock inputs after configuration especially if the FPGA application access the parallel NOR Flash after configuration Table 5 11 summarizes the shared pins on Spartan 3E FPGAs These pins are not shared connections on Spartan 3A 3AN 3A DSP FPGAs Table 5 11 Spartan 3E Shared BPI Configuration Pins and Global Buffer Input Pins Device Global Buffer BPI Mode Edge Input Pin Configuration Pin GCLKO RDWR B GCLK2 D2 GCLK3 D1 Bottom GCLK12 D7 GCLK13 D6 GCLK14 D4 GCLK15 D3 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Spartan 3E BPI Mode Interaction with Right and Bottom Edge Global Clock Inputs Table 5 11 Spartan 3E Shared BPI Configuration Pins and Global Buffer Input Pins Device Global Buffer BPI Mode Edge Input Pin Configuration Pin RHCLKO A10 RHCLK1 A9 RHCLK2 A8 RHCLK3 A7 Right RHCLK4 A6 RHCLK5 A5 RHCLK6 A4 RHCLK7 A3 Spartan 3 Generation Configuration User Guide www xili
367. then enables the PROM data out during configuration DONE CE FPGA enables PROM during configuration DONE output powered by FPGA VccAux supply PROG_B CF VCCO_2 Veco Spartan 3E FPGA 1 8V 2 5V or 3 3V Spartan 3A 3A DSP FPGA 2 5V or 3 3V not 1 8V VCCJ PROM JTAG output voltage If 3 3V then protect the FPGA JTAG inputs with current limiting resistors gt 68Q 64 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX 1 2V XCFxxS 3 3V VCCINT XCFxxP 1 8V Py PUbDc B vccoo Mode voco 3 3V OE RESET XILINX 7 XILINX Spartan 3A 3AN 3 3V Platform Flash Spartan 3A DSP 3 3V 3 3V 5 VREF 3 3V 88 5 rws efl obo A og 2c 8o 5 froi xi c5 N C x N C pues PROGRAM Dedicated internal pull up resistor UG332 c3 15 052107 Figure 3 2 Master Serial Mode Using Platform Flash PROM Spartan 3A 3AN 3A DSP FPGA VccAUX 3 3V Spartan 3 Generation Configuration User Guide www xilinx com 65 UG332 v1 2 May 23 2007 Chapter 3 Master Serial Mode EZ XILINX 1 2V VCCINT VCCO 4 DIN INIT B JTAG Voltage Resistors HSWAP EN CCLK m2 lt XILINX M1 Spartan 3 MO Master Serial Mode TDO PROG_B DONE GND Xilinx Cable Header JTAG Interface Dedicated internal pull up resistor Figure 3 3 Master Serial Mode Using Platform Flash PROM Spartan 3 FPGA XCFxxS 3 3V XCFxx
368. tion check value are both multi bit binary values For the sake of clarity this example uses symbolic values The PROM s Device ID is Blue and the configuration PROM is programmed with the check value Blueberry The Flash ID plus the authentication check value should be as large as practical A larger number of bits thwarts a possible spoof or middleman attack using an extra interposing device or devices that intercepts the access to the off FPGA identifier and check value The interposing device or devices mimics the response from an authentic PROM This technique requires additional components and a new printed circuit board the additional development and component costs of which act as a suitable deterrent If the FPGA authentication application accesses a large data field or check value then the interposing device or devices must be more sophisticated and consequently more expensive This potential vulnerability also highlights the advantage of the Spartan 3A 3AN 3A DSP Device DNA which is securely accessed from inside the FPGA Configuration PROM Spartan 3E FPGA with Device ID FPGA Bitstream Blue Blueberry UG332 c16 09 100406 Figure 15 10 Spartan 3E FPGA Authenticates the PROM Image Against the PRON s Device ID After configuration the FPGA checks that the value contained in the PROM matches the value expected by the FPGA application In this example the FPGA validates that a 284 www xilinx com Spartan
369. to reset FPGA FPGA initializing when INIT B is 1 X X X X 0 0 Low after a PROG B pulse or initially at power on FPGA ready for configuration l d 2 a is j when INIT_B returns High 1 1 X X X 1 0 No operation when CSI_B is High To write configuration data to D 7 0 FPGA drive RDWR B Low before 1 0 0 t FPG A 0 T 1 0 or coincident with driving CSI B S Low Each D 7 0 byte captured on each rising CCLK edge BUSY is High indicating that the FPGA not ready to receive data 1 0 0 D 7 0 1 T 1 0 Hold current D 7 0 byte until the to FPGA next CCLK cycle when BUSY returns Low BUSY not used on Spartan 3A 3AN 3A DSP FPGAs 1 0 Otol X X X X ABORT condition if RDWR B 0 ito is X X X X changes state while CSI B is Low After configuration if the Persist Yes bitstream option is set D 7 0 the Slave Parallel SelectM AP 1 0 1 from 0 T 1 1 interface can be used to Readback FPGA data from the FPGA assuming the security bits were not set in the FPGA bitstream FPGA successfully configured 1 X x X 0 8x T X 1 eight CCLK cycles after DONE goes High At the end of configuration if 1 X X X X 0 0 INIT_B is again Low then a configuration CRC error occurred Notes X don t care T rising edge 166 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Table 7 2 Slave Parallel Mode Connections PCB trace is long or has multiple connections terminat
370. tor software please refer to pages 257 through 276 in the following software manual e ISE9 1i Development System Reference Guide http toolbox xilinx com docsan xilinx9 books docs dev dev pdf 32 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX General Configuration Control Pins Chapter 2 Configuration Pins and Behavior during Configuration The FPGA s configuration flexibility means that many pins serve multiple purposes Some pins are merely borrowed during configuration only to be released back to the FPGA application as user defined I O pins Other pins are dedicated to configuration This chapter describes how these various pins behave during the configuration process General Configuration Control Pins A few pins control the overall FPGA configuration process These include the following and are similar on all Spartan 3 Generation FPGAs The four wire JTAG interface is a separate and independent configuration interface discussed primarily in Chapter 9 JTAG Configuration Mode and Boundary Scan e The mode select pins M 2 0 defines the configuration mode that the FPGA uses to load its configuration data e The DONE pin when High indicates when the FPGA successfully completed loading its configuration data e The program pin PROG B initiates the configuration process The FPGA also automatically initiates configuration on power up The JTAG inter
371. tore multiple FPGA bitstreams Add the bitstream sizes for each FPGA in the daisy chain If using the SPI PROM to store MicroBlaze code or other nonvolatile data for the FPGA application after configuration add the sizes of each of these images Add any overhead requirements to align the data to page or sector boundaries as required by the selected Flash PROM device e For possible future migration to a larger FPGA or to allow possible upward migration for additional data choose a SPI PROM family that offers larger compatible densities e For Spartan 3E FPGA applications that require anti cloning protection choose an SPI PROM that provides a unique identifier ID See Spartan 3E FPGA Leveraging Security Features in Select Commodity Flash PROMs page 283 Spartan 3A 3AN 3A DSP FPGAs provide similar protection features using an SPI PROM See Spartan 3A 3AN 3A DSP FPGA Imprinting or Watermarking the Configuration PROM with Device DNA page 282 e The Xilinx iMPACT software offers direct in system programming using Xilinx programming cables starting with ISE 8 2i However the current software version only supports the STMicro and Atmel devices indicated in Table 4 2 page 89 Many 25 series PROMs are directly compatible with the STMicro M25Pxx family and could be substituted in production 90 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Choosing a Compatible SPI Seri
372. ts 1 265 224 553 default i 12 23 5 18 3 39 13 34 17 25 ns 22 17 25 641 3 5 144 27 13 33 92 44 49 SPI Flash Interface after Configuration After the FPGA successfully completes configuration all of the pins connected to the SPI Flash PROM are available as user I O pins If Not Using SPI Flash after Configuration If not using the SPI Flash PROM after configuration drive CSO B High to disable the PROM as shown in Figure 4 4 The MOSI DIN and CCLK pins are then available as Spartan 3 Generation Configuration User Guide www xilinx com 99 UG332 v1 2 May 23 2007 Chapter 4 Master SPI Mode XILINX general purpose I O pins in the FPGA application although avoid additional loading on CCLK if possible to maintain best signal integrity User l O SPI Flash PROM 8 During configuration User I O SPI Flash PROM User I O User I O De selected yt ga Standby User I O b After successful configuration UGS332 c4 19 040107 Figure 4 4 f Not Using SPI after Configuration Drive CSO B Pin High De selecting CSO B also places the SPI PROM in the lower power Standby mode See Deassert CSO B to Enter Standby Mode page 127 If Using SPI Flash Interface after Configuration Because all the interface pins are user I O after configuration the FPGA application can continue to use the SPI Flash interface pins to communicate wit
373. turer with the ability to create authentic copies which reduces the risk of potential overbuilding In addition the time out function makes a potential attack significantly more difficult If the system functions for awhile before failing significantly more time is required to attack the system using a brute force approach Similarly using a random time out value makes it difficult for an attacker to determine if he or she cracked the system or whether there is an inherent system design problem Active Defense The final level of protection against unauthorized copying is an active defense The active defense can take many forms again depending on the application requirements For example the application can track the number of failed authentication attempts Once the number of failed attempts reaches a predefined threshold the application can take more drastic protection means such as erasing the configuration PROM or permanently locking down sectors in the PROM Authentication Algorithm The obvious question is What is the authentication algorithm The answer is It s a secret Something in the authentication process must be secret either the authentication algorithm or the authentication values In the examples using the Spartan 3A 3AN 3A DSP Device DNA or the Flash PROM with a Device ID the authentication algorithm must be kept secret Because the authentication algorithm is implemented using FPGA logic the algorithm is
374. ty boundary scan tool vendors and from some third party PROM programmers using a socket adapter with attached wires To gain direct access to the parallel Flash signals hold the FPGA s PROG B input Low throughout the programming process This action places all FPGA I O pins including those attached to the parallel Flash in high impedance Hi Z If the HSWAP or PUDC B inputis Low theI Os have pull up resistors to the Vcco input on their respective I O bank The external programming hardware then has direct access to the parallel Flash pins The FPGA itself can also be used as a parallel Flash PROM programmer during development and test phases Because parallel NOR Flash is most commonly used with the MicroBlaze processor core the Xilinx Platform Studio XPS includes Flash programming support Essentially XPS downloads a Flash programmer into the FPGA via the FPGA s JTAG port The FPGA then performs necessary the Flash PROM programming algorithms and receives programming data from the host via the FPGA s JTAG interface e Chapter 9 Flash Memory Programming in UG111 Embedded System Tools Reference Manual EDK 8 1i www xilinx com ise embedded est rm pdf Spartan 3 Generation Configuration User Guide www xilinx com 153 UG332 v1 2 May 23 2007 Chapter 5 Master BPI Mode XILINX Similarly the FPGA application can leverage an existing communication channel in the system to program or update the Flash memory The Spartan 3E
375. ues to check for additional post configuration CRC errors even after detecting an error The FPGA based system separately determines what action to take when a CRC error occurs Most applications will simply decide to reconfigure the FPGA Verifying CRC Error Behavior To verify the post configuration CRC checking function the user can force a change using the SRL16 logic Instantiate at least one SRL16 and set the glutmask Yes bitstream option Write to the SRL16 to change its state and the post configuration CRC feature should flag the CRC error Preparing an Application to Use the Post Configuration CRC Feature e Enable the post configuration CRC logic using the POST CRC ENABLE configuration constraint e The post configuration CRC checker is clocked by one of three possible clock sources as described in Clock Source Be sure that the application or system is providing the required clock input In most applications the CRC checker uses the FPGA s internal oscillator as the clock source Set the oscillator frequency using the POST CRC FREO configuration constraint By default the oscillator is set at 1 which roughly equates to a 1 MHz clock See Table 16 2 for available options e Using the POST CRC ACTION configuration constraint define whether the CRC checker will continue to check for additional CRC errors or will halt checking e If any look up tables LUTs in the FPGA application are used as distributed RAM or SRL16 shift re
376. ult UG332_c1_07_120106 Figure 1 8 Bitstream Generator Startup Options Click Startup Options as shown in Figure 1 8 After the FPGA configuration bitstream is loaded into the FPGA the FPGA enters its Startup phase The timing of each Startup cycle is controlled by a selectable clock source See Startup Clock Source page 235 The Startup phase of FPGA configuration provides six different cycles to synchronize the following startup events The event can be assigned to a specific cycle or be synchronized to the DONE signal See Startup page 233 The timing of when output drivers are enabled The timing of when the write protect lock is removed from writable clocked elements The timing of when the DONE pin goes active If the DCM_WAIT TRUE attribute is set on a Digital Clock Manager DCM within the FPGA the FPGA optionally waits for the Delay Locked Loop DLL within the DCM to lock to the incoming clock signal before finishing configuration See Waiting for DCMs to Lock DCI to Match page 235 The FPGA s DONE pin can actively drive High after configuration This option should only be set for single FPGA applications or for the last FPGA in a multi FPGA configuration daisy chain See DONE Pin page 36 30 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Setting Bitstream Options Generating an FPGA Bitstream Category
377. up controls the Startup sequencer as the FPGA transitions from configuration mode to the application loaded into the FPGA See Startup Clock Source page 235 UserClk A clock signal from within the FPGA application controls the Startup sequencer as the FPGA transitions from configuration mode to the application loaded into the FPGA See Startup Clock Source page 235 The FPGA application supplies the user clock on the CLK pin on the STARTUP primitive See Start Up STARTUP page 241 JtagClk The JTAG TCK input controls the startup sequence when the FPGA transitions from the configuration mode to the user mode See Startup page 233 ProgPin PROG B pin Pullup Default Internally connects a pull up resistor or between PROG B pin and VccAux See Program or Reset FPGA PROG B page 39 Pullnone No internal pull up resistor on PROG B pin An external 4 7 KQ pull up resistor to VccAux is required UnusedPin Unused I O Pins Pulldown Default All unused I O pins and input only pins have a pull down resistor to GND Pullup All unused I O pins and input only pins have a pull up resistor to the VCCO_ supply for its associated I O bank Pullnone All unused I O pins and input only pins are left floating Hi Z high impedance three state Use external pull up or pull down resistors or logic to apply a valid signal level 218 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX
378. vailable on the Spartan 3AN FPGA family The Spartan 3AN FPGA family has integrated In System Flash ISF memory primarily for FPGA configuration The ISF memory is sufficiently large to store two FPGA configuration bitstreams MultiBoot plus additional nonvolatile data storage for the FPGA application Spartan 3AN FPGAs also support all of the other Spartan 3A 3AN 3A DSP FPGA configuration modes shown in Table 2 1 page 34 Caution This configuration mode is only supported by the Spartan 3AN FPGA family The Vccaux Supply MUST be 3 3V Figure 10 1 shows the logic levels and signals involved during configuration 1 2V VCCINT PUDC_B VCCO 0 VCCO 0 VCCO 2 Internal SPI Mode 0 T M1 1 gt e X XILINX Variant Spartan 3AN Select J 0 Xilinx Cable Header JTAG Interface PROGRAM UG332 c10 01 112906 Figure 10 1 Spartan 3AN FPGA using Internal Master SPI Flash Mode Spartan 3 Generation Configuration User Guide www xilinx com 201 UG332 v1 2 May 23 2007 Chapter 10 Internal Master SPI Mode XILINX Internal Flash Memory The amount of ISF memory varies by Spartan 3AN FPGA logic density as shown in Table 10 1 The amount of Flash memory exceeds the amount required to configure the FPGA There is sufficient additional memory for at least two uncompressed bitstream images to support MultiBoot or for additional nonvolatile storage for the FPGA application Table 10 1 Number of Bits to
379. vided in Table 7 1 page 166 The external download host starts the configuration process by pulsing the FPGA s PROG B pin Low and monitoring that the INIT B pin returns High indicating that the FPGA is ready to receive its first data The host asserts the active Low chip select signal CSI B and the active Low Write signal RDWR B The host then continues supplying data and clock signals until either the FPGA s DONE pin goes High indicating a successful configuration or until the FPGA s INIT B pin goes Low indicating a configuration error The FPGA captures data on the rising CCLK edge On Spartan 3 and Spartan 3E FPGAs if the CCLK frequency exceeds 50 MHz then the host must also monitor the FPGA s BUSY output Spartan 3A 3AN 3A DSP FPGAs do not have a BUSY pin If the FPGA asserts BUSY High the host must hold the data for an additional clock cycle until BUSY returns Low If the CCLK frequency is 50 MHz or below the BUSY pin may be ignored but actively drives during configuration The configuration process requires more clock cycles than indicated from the configuration bitstream size alone Additional clocks are required during the FPGA s start up sequence especially if the FPGA is programmed to wait for selected Digital Clock Managers DCMs to lock to their respective clock inputs LCK cycle See Startup page 233 for additional information If the Slave Parallel interface is only used to configure the FPGA never to read dat
380. www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Accessing the Internal SPI Flash PROM After Configuration Table 10 2 Spartan 3AN FPGA Supported Variant Select VS 2 0 Options SPI Flash Read Supported by Variant Select Pins Command Spartan 3AN FPGA Maximum CLK VS 2 0 Command Code Family Frequency FAST READ 1 11 11 0x0B Yes 66 MHz READ ARRAY lt 1 1 0 gt OxE8 Yes 66 MHz READ lt 1 0 1 gt 0x03 Yes 33 MHz All Others No Supply Voltage Requirements The Spartan 3AN FPGA family imposes some minor restrictions on FPGA supply voltages VCCAUX The VCCAUX supply input must be 3 3V The VCCAUX rail supplies power to the In System Flash memory VCCO 2 The VCCO 2 supply rail which must be the same voltage as the configuration memory in other configuration modes has no such restriction on Spartan 3AN FPGAs Sequencing Due to requirements of the integrated SPI serial Flash memory the 3 3V VCCAUX supply must reach its minimum supply rail before the FPGA s 1 2V VCCINT supply reaches its minimum power on reset voltage level Accessing the Internal SPI Flash PROM After Configuration The FPGA application has full access to the internal In System Flash memory after configuration using the SPI ACCESS design primitive as shown in Figure 10 2 SPI ACCESS MOSI UG332 C13 06 081506 Figure 10 2 Spartan 3AN SPI ACCESS Design Pr
381. x com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX E Figure 4 2 shows the connection diagram for Atmel DataFlash serial PROMs which also use an SPI based protocol Xilinx recommends using C or D series DataFlash devices Figure 4 6 page 103 demonstrates how to configure multiple FPGAs with different configurations all stored in a single SPI Flash The diagram uses standard SPI Flash memories but the same general technique applies for Atmel DataFlash Xilinx Cable Header SPI Flash Direct Programming 1 2V z z 8 S S amp 3 Se erm 43 3V VCCINT P HSWAP VCCO 0 SPI Mode 3 3V VCC iy o s Atmel Spartan 3A 3AN Spartan 3A DSP 0 have internal pull up resistors i 4 a J AT45DB px D Series CS pataFlash XILINX pet ole i ACC partan 3A DSP Spartan 3A 3AN iM Spartan 3A DSP 1 VS2 have internal pull up resistors iy i4 3 b Er VER VCCAUX vo rms o 8 t illo mwm tz 2g ac Soha off ses N C PROG B DONE x N C GND e 8200 a Bn a Direct rogrammin PROGRAM umper i Dedicated internal pull up resistor UG332 c4 02 040107 Figure 4 2 SPI Flash Configuration Interface for Atmel DataFlash Devices Spartan 3 Generation Configuration User Guide www xilinx com 87 UG332 v1 2 May 23 2007 Chapter 4 Master SPI Mode XILINX Master SPI Mode Differences between Spartan 3 Generation
382. xadecimal address 0x60000 Place the second bitstream at this address or any subsequent sector boundary With an image at 0x60000 a third image starts at 0xC0000 15 Click Next 16 The iMPACT software summarizes the current settings as shown in Figure 14 16 Click Finish to continue iMPACT File Generation Summary lel XI Y ou have entered following information PROM Type SPI PROM File Format mes Fill Value FF PROM filename MyS partan 34MultiB oot Number of PROMs 1 Click Finish to start adding device files lt Back UG332_c14_15_082006 Figure 14 16 Confirm PROM Settings 17 As shown in Figure 14 17 page 269 add the initial FPGA bitstream This is the design that is loaded into the FPGA at power up or whenever the PROG B pin is pulsed Low This is also the default bitstream that is automatically loaded if the Configuration Watchdog Timer CWDT expires during a MultiBoot operation 268 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Spartan 3A 3AN 3A DSP MultiBoot i i Start adding device file to A Data Stream 0 2 would you like to add another design file to Data Stream 0 Fe My Recent T UM Emma Filename s3a_multiboot_image_0 bit Places Files of type FPGA Bit Files bit 2 bit f s3a multiboot image UG332 c14 16 082106 Figure 14 17 Select the First Default Conf
383. xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Design Considerations Seria Byte Wide Spartan 3 Xilinx Spartan 3E Generation Platform Flash Spartan 3A 3AN 3A DSP Parallel NOR FPGA PROM FPGA Flash CLK e FP LDC1 OE HDC WE a Master Serial mode LDC2 Spartan 3E D 7 0 DATA 7 0 Spartan 3A 3AN 3A DSP eria aaa Flash ADDRIn 0 ADDR n 0 DTE d Master BPI mode parallel NOR Flash DATA OUT SELECT Spartan 3 Platform Flash FPGA PROM CLOCK b Master SPI Flash mode Spartan 3AN FPGA e Master Parallel mode In System Flash ISF Memory c Internal Master SPI Flash mode Xilinx XCFxxP Notes 1 Remaining Spartan 3 Generation FPGAs support XCFxxP Platform Flash PROMs via Master BPI mode UG332_c1_01_052207 Figure 1 1 Spartan 3 Generation Self Loading Master Configuration Modes Spartan 3 Generation Configuration User Guide www xilinx com 13 UG332 v1 2 May 23 2007 Chapter 1 Overview and Design Considerations XILINX Table 1 1 Spartan 3 Generation Self Loading Configuration Modes and Memory Sources Information on Supported Spartan 3 Generation External Memory FPGA Configuration Mode Families Xilinx Platformi Mash PROM Chapter 3 Master Serial Mode All either XCFxxS or XCFxxP PROMs Primarily Spartan
384. y Boundary Scan chain C Prepare a PROM File C Prepare a System ACE File Prepare a Boundary Scan File SYF Y C Configure devices Figure 3 14 Program Platform Flash PROM using JTAG Click Finish As shown in Figure 3 15 the iMPACT software automatically detects the JTAG chain if so enabled This example application is similar to that shown in Figure 3 1 The FPGA is an XC3S700A followed in the chain by an XCF045 Platform Flash PROM xc3s700a xcf 4s bypass bypass UG332 c3 10 111506 Figure 3 15 iMPACT Automatically Detects JTAG Chain 80 www xilinx com Spartan 3 Generation Configuration User Guide UG332 v1 2 May 23 2007 XILINX Platform Flash In System Programming via JTAG using iMPACT 4 Inthis example the XC3S700A precedes the XCF04S Platform Flash PROM in the chain The FPGA does not need to be programmed in order to program the Platform Flash PROM The iMPACT software prompts for the FPGA bitstream as shown in Figure 3 16 Click Bypass to skip programming the FPGA Assign New Configuration File 21 xi Look in E C Data my desians led crazy t ex ga EE E led crazy bit File type All Design Files bit rbt nky isc bsd Cancel UG332 c3 11 111506 Figure 3 16 Bypass Programming the FPGA 5 Asshownin Figure 3 17 select the PROM data file to be programmed to the Platform Flash PROM File type All Design Files mes exo
385. y engineering or technical support or assistance provided to you in connection with the Design THE DESIGN IS PROVIDED AS IS WITH ALL FAULTS AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE WHETHER GIVEN BY XILINX OR ITS AGENTS OR EMPLOYEES XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DESIGN INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN WHETHER IN CONTRACT OR TORT OR OTHERWISE WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN YOU ACKNOWLEDGE THAT THE FEES IF ANY REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY The Design is not designed or intended for use in the development of on line control equipment in hazardous environments requiring fail safe controls such as in the operation of nuclear facilities

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