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conga-QMX6 User's Guide

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1. 41 Table 5 Edge Finger EEN 42 Table 6 PCI Express Signal Descriptions emgeiesgrgeege tege de de EN 45 Table 7 UART Signal DESCr PUONS cccacacss lt etconccccseanenrenssrtenainecutcaatsddanies 45 Table 8 Ethernet Signal Descriptions c g icsscscccrccaseaiavscdoncenvaveasmiesnpean 46 Table 9 SATA Signal Descriptions E 47 Table 10 USB Signal Descrpttons ereere eee 47 Table 11 SDIO Signal Descriptions 2 0 00 eec ccc remanet ctr nac tene 49 Table 12 HDA AC 97 Signal Descriptions esee 50 Table 143 LVDS Signal Descriptions ues ero tue dina edeede sadip nicus 50 Table 14 DisplayPort Signal Descripotions 52 Table 15 HDMI Signal Descriptions eiae rrr r trt trauen narra 52 Table 16 LPC GPIO Signal Descriptions eseeeeeessssssse 53 Table 17 SPI Interface Signal Descriptions sss 54 Table 18 CAN Bus Signal DescnplioriS usse iciatis saine apr a ipi huc 54 Table 19 Input Power Signal Descriptions eese 54 Table 20 Power Control Signal Descriptions eeeeeeeeeeeeeeeeeeeeeeeeneeeene 55 Table 24 Power Management Signal Descriptions 55 Table 22 Miscellaneous Signal Descriptions sssssss 56 Table 23 Manufacturing Signal Descriptions seeeeeeeseeeeeeeeeeeeeeeeeneene 57 Table 24 Thermal Management Signal Descriptions 58 Table
2. WDTRIG 70 Watchdog trigger signal This signal restarts the watchdog timer of the Qseven 13 3V Connected to GPIO module on the falling edge of a low active pulse WDOUT 72 Watchdog event indicator High active output used for signaling a missing watchdog O 3 3V Connected to GPIO trigger Will be deasserted by software system reset or a system power down GPO I2C CLK 66 General Purpose IC bus 0 clock line 1 0 3 3V OD PU 4k7 3 3V GPO DC DAT 68 General Purpose IC bus 0 data line 1 0 3 3V OD PU 4k7 3 3V SMB CLK 60 Clock line of System Management Bus I O 3 3VSB PU 4k7 3 3V Connected to I2C GP1 I2C CLK Multiplexed with General Purpose 1 C bus 1 clock line OD SMB DAT 62 Data line of System Management Bus I O 3 3VSB PU 4k7 3 3V Connected to I2C GP1 I2C DAT Multiplexed with General Purpose IC bus 1 data line OD SMB_ALERT 64 System Management Bus Alert input This signal may be driven low by SMB I O 3 3VSB PU 10k 3 3V Connected to GPIO devices to signal an event on the SM Bus OD SPKR 194 Primary functionality is output for audio enunciator the speaker in PC AT systems O 3 3V Not supported GP PWM OUT2 When not in use for this primary purpose it can be used as General Purpose PWM Output BIOS DISABLE 41 Pin is used to select Boot mode 1 3 3V PU 4k7 3 3V BOOT_ALT RSVD 56 132 134 144 Do not connect NC 146 154 GP 1 Wire Bus 124 General Purpose 1 Wire bus interface Can be used for consumer electr
3. to 60 C it is not designed to be used within industrial temperature ranges 40 to 85 C When using a heatspreader with conga QMX6 commercial grade variants the maximum operating temperature refers to any measurable spot on the heatspreader s surface congatec AG strongly recommends that you use the appropriate congatec module heatspreader as a thermal interface between the module and your application specific cooling solution when used in a commercial temperature range If it is not possible to use the appropriate congatec module heatspreader for conga QMX6 commercial grade variants or an industrial grade variant of conga QMX 6 is being used within industrial temperature ranges then it is the responsibility of the operator to ensure that all components found on the module operate within the component manufacturer s specified temperature range Copyright O 2013 congatec AG QMX6m03 21 63 3 Block Diagram amp congatec the rhythm of embedded computing Qseven Qseven Connector DEE Connector i i onboard Memory i i 230 pin goldfinger GE 230 pin goldfinger Power Rail DDR3 Power T Control I2C2 3 ARM Cortex A9 Core 32 KB I Cache 32 KB D Cache JTAG TRACE JI per Core per Core 7 MFG_NCO 4 Gigabit Ethernet SES 7 USB Port 0 l USB HI USB Port 2 USB Ports USB Port A HDMI Vi USB OTG 5 UARTO USB Port 1 Client 10 Enc D P SOD3O EOM LVDS single dual channel SPI s LVDS E SD
4. 156 PCIE_WAKE 157 PCIE CLK REF 158 PCIE_RST Copyright 2013 congatec AG QMX6m03 congatec the rhythm of embedded computing 43 63 159 GND 160 GND 161 PCIE3_TX 162 PCIE3_RX 163 PCIE3 TX 164 PCIE3 RX 165 GND 166 GND 167 PCIE2_TX 168 PCIE2_RX 169 PCIE2 TX 170 PCIE2 RX 171 UARTO TX 172 UARTO_RTS 173 PCIE1 TX 174 PCIE1_RX 175 PCIE1 TX 176 PCIE1 RX 177 UARTO RX 178 UARTO_CTS 179 PCIEO TX 180 PCIEO_RX 181 PCIEO TX 182 PCIEO_RX 183 GND 184 GND 185 LPC ADO GPIOO 186 LPC AD1 GPIO1 187 LPC AD2 GPIO2 188 LPC AD3 GPIO3 189 LPC_CLK GPIO4 190 LPC FRAME GPIO5 191 SERIRQ GPIO6 192 LPC_LDRQ GPIO7 193 VCC RTC 194 SPKR GP PNM OUT2 195 FAN TACHOIN GP TIMER IN 196 FAN PNMOUT GP PWM OUT 197 GND 198 GND 199 SPI MOSI 200 SPI CS 201 SPI MISO 202 SPI_CS1 203 SPI SCK 204 MFG NC4 205 VCC 5V SB 206 VCC 5V SB 207 MFG NCO 208 MFG NC2 209 MFG NC1 210 MFG NC3 211 VCC 212 vcc 213 VCC 214 vcC 215 VCC 216 VCC 217 Woo 218 VCC 219 VCC 220 VCC 221 VCC 222 VCC 223 VCC 224 VCC 225 VCC 226 VCC 227 Jee 228 VCC 229 VCC 230 VCC o gt Note The conga QMX6 does not support the signals marked with asterisk symbol Copyright O 2013 congatec AG QMX6m03 Se congatec the
5. is connected directly to the USB OTOG port of the i MX6 processor The OTG client port can drop the hosting role and act as a normal USB device when conga QMX6 is attached to another host The direction Copyright O 2013 congatec AG QMX6m03 28 63 5 6 5 7 5 8 P congatec the rhythm of embedded computing of OTG port depends on the USB control signal USB_ID If asserted high the OTG is set to client and if low the OTG port is set to host All ports are capable of supporting USB 1 1 and 2 0 compliant devices SD SDIO MMC SDIO stands for Secure Digital Input Output Devices that support SDIO can use small devices such as SD Card or MMC Card flash memories The SD SDIO MMC cards communicate with the host system via the Ultra Secured Digital Host Controller USDHC This controller acts as a bridge by sending commands and accessing data to and from the cards The Freescale i MX6 processor on the conga QMX6 provides SD SDIO MMC controllers SD1 SD4 for communicating with different SD SDIO and MMC devices The conga QMX6 offers one SDIO interface on the MXM connector via the Freescale i MX6 SD4 port Two other SDIO ports provided by the Freescale i MX6 processor are supported onboard the conga QMX6 These ports SD2 and SD3 connect the onboard 4 bit micro SD and the onboard 8 bit eMMC respectively The SDIO ports support SDIO Revision 1 1 SD Memory Card Specification Revision 3 0 and MMC Revision 4 4 HDA I2S AC 97 The co
6. 2 0 ports 4x USB 2 0 hosts and 1x USB 2 0 OTG DS Bus SPI CAN Android Buttons JTAG RS 232 Debug Port SPI Flash contains the bootloader 8x GPIOs 3x lC fast mode multi master two shared IC buses and one unshared bus 1x UART fully featured UART with control signals supported on the MXM connector 2x RS 232 interfaces supported onboard the conga QMX6 via RS232 transceiver DDR3 SDRAM memory up to 2 GB Micro SD Socket eMMC module 4GB onboard Pre installed open source bootloader U boot Did EET I uiui Yes Some of the features mentioned in the above feature summary are optional Check the article number of your module and compare it to the conga QMX6 options information list on page 12 of this user s guide to determine what options are available on your particular module Copyright O 2013 congatec AG QMX6m03 13 63 p congatec the rhythm of embedded computing 2 2 Supported Operating Systems The conga QMX6 supports the following operating systems Microsoft Windows Embedded Compact 7 Android Linux 2 3 Mechanical Dimensions 70 0 mm x 70 0 mm 2 x 2 7 The Qseven module including the heatspreader plate PCB thickness and bottom components is up to approximately 12mm thick Heatspeader Qseven Module PCB i Dimension is dependent on connector height used All dimensions without tolerance 0 2mm Dimension is dependent on connector height
7. 3 9 4 9 5 9 7 9 8 9 10 9 11 9 12 9 13 9 14 9 15 9 16 9 17 9 18 9 19 9 20 921 10 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 11 USB Port Connections cece eeeee cece eee eeeeeeeeeeeeeeeeeeeeeeeees 39 Interface Signal Descriptions and Pinout Tables 41 EGUEXDIGSS M mare EE 45 olg RE 45 Gigabit Ethernet E 46 SATA rirnori a RA E RE ARE ERTS 47 USB ee 47 IB 70 EE 49 HDA 128 JSP DIF 50 KEE 50 IR En EE 52 lp 52 Be EEN 53 E 54 CAN RTE 54 leg L 54 Power Control eee 55 Power Managements scssi ii 55 Miscellaneous 2 ccc cececeecceeceeecceeceeeceeeceeeceeeeeeeeeeeeeeeeeeteeeeeeees 56 Manufacturing JTAG Interface is tcsiscuacbencikcesasanantcnauvaiinaesnngseaien 57 Thermal WAG LE 58 Fan CON Oli E M 58 Bootstrap eege EE 59 Onboard Interfaces and Devices ccccccceeeeeeeeeeeeeeeeeeeeees 60 UART RS 232 Debug Port 60 MIPI CMOS Camera 60 RENE 61 SPUEIBSPS EE 61 Android Eu e E 61 DORS MEMON Laiiiacula cn edito stir ban eur fuente ced i sit uud 61 li ge err 62 Micro GD 62 Ind stry Specifications me RT 63 Copyright O 2013 congatec AG Se congatec the rhythm of embedded computing 9 63 P congatec the rhythm of embedded computing List of Tables Table 1 LEO 12 Table 2 Ugen EE 12 Table 3 Feature EMER af ce eege enee 13 Table 4 Signal Tables Terminology Descriptions
8. 3 OC 86 USB 0 1 OCH 87 USB P3 88 USB P2 89 USB b i 90 USB_P2 91 USB CC 92 USB ID 93 USB_P1 94 USB PO 95 USB P1 96 USB PO 97 GND 98 GND 99 eDPO TX0 LVDS A0 100 eDP1 Tv LVDS B0 101 eDPO TX0 LVDS AQ 102 eDP1 TX0 LVDS BO 103 eDPO_TX1 LVDS_A1 104 eDP1 TX1 LVDS B1 105 eDPO_TX1 LVDS_A1 106 eDP1 TX1 LVDS B1 107 eDPO_TX2 LVDS_A2 108 eDP1_TX2 LVDS_B2 109 eDPO_TX2 LVDS_A2 110 eDP1 TX2 LVDS B2 111 LVDS PPEN 112 LVDS BLEN 113 eDPO TX3 LVDS A3 114 eDP1 TX3 LVDS B3 115 eDPO TX3 LVDS A3 116 eDP1 TX3 LVDS B3 117 GND 118 GND 119 eDPO AUX LVDS A CLK 120 eDP1 AUX LVDS B CLK 121 eDPO AUX LVDS A CLK 122 eDP1 AUX LVDS B CLK 123 LVDS BLT CTRL 124 GP 1 Wire Bus IGP PNM OUTO 125 GP2 I2C DAT LVDS DID DAT 126 eDPO HPD LVDS BLC DAT 127 GP2 I2C CLK LVDS DID CLK 128 eDP1 HPD LVDS BLC CLK 129 CANO TX 130 CANO RX 131 DP LANE3 TMDS CLK 132 RSVD Differential Pair 133 DP LANE3 TMDS CLK 134 RSVD Differential Pair 135 GND 136 GND 137 DP LANE1 TMDS LANE1 138 DP AUX 139 DP LANE1 TMDS LANE1 140 DP AUX 141 GND 142 GND 143 DP_LANE2 TMDS_LANEO 144 RSVD Differential Pair 145 DP LANE2 TMDS LANEO 146 RSVD Differential Pair 147 GND 148 GND 149 DP_LANEO TMDS_LANE2 150 HDMI CTRL DAT 151 DP LANEO TMDS LANE2 152 HDMI CTRL CLK 153 DP HDMI HPD 154 RSVD 155 PCIE_CLK_REF
9. 6 3 3V CH Note The eight LPC pins are configured by default as GPIO s Additional eight GPIO pins can be achieved by configuring SDIO pins as GPIO This can be programmed in the bootloader and in the kernel The conga QMX96 does not support LPC interface Copyright O 2013 congatec AG QMX6m03 53 63 9 12 SPI Table 17 SPI Interface Signal Descriptions p congatec the rhythm of embedded computing Description HO PU PD Comment SPI_MOSI 199 Master serial output Slave serial input signal SPI serial output data from 0 3 3V Qseven module to the SPI device SPI_MISO 201 Master serial input Slave serial output signal SPI serial input data from the SPI 13 3V device to Qseven module SPI SCK 203 SPI clock output O 3 3V SPI CSO 200 SPI chip select 0 output 0 3 3V SPI_CS1 202 SPI Chip Select 1 signal is used as the second chip select when two devices are O 3 3V used Do not use when only one SPI device is used 9 13 CAN Bus Table 18 CAN Bus Signal Descriptions Pin Description UO PU PD Comment CANO_TX 129 CAN Controller Area Network TX output for CAN Bus channel 0 In order 0 3 3V to connect a CAN controller device to the Qseven module s CAN bus it is necessary to add transceiver hardware to the carrier board CANO_RX 130 RX input for CAN Bus channel 0 In order to connect a CAN controller device to 1 3 3V the Qseven module s CAN bus it is nec
10. codes faster than the software based java virtual machine The Jazelle DBX Direct Bytecode eXecution enabled cores execute the majority of Java bytecodes in hardware No modification is required in the application code to take advantage of this technology To configure and turn on the Jazelle DBX the software support code needs to be integrated into a Java Virtual Machine JVM Contact ARM for further information on how to obtain the software support code 7 3 TrustZone The ARM TrustZone technology is a security extension that provides additional dedicated security to a System on Chip SoC This technology aims to provide a framework that enables a device to counter many of the specific threats that it will experience The security of the system is achieved by partitioning all of the SoC s hardware and software resources so that they exist in one of two worlds the secure world more trusted and the normal world less trusted The memory and peripherals are then made aware of the operating world of the core and may use this to provide access control to secrets and code in the device 7 4 Floating Point Unit The Floating Point Unit FPU provides significant acceleration for both single and double precision scalar Floating Point operations It provides industry leading image processing graphics and scientific computation capabilities The FPU provides an optimized solution in performance power and area for embedded applications and high perf
11. computing 9 6 SDIO MMC Table 11 SDIO Signal Descriptions Pin Description PU PD Comment SDIO_CD 43 SDIO Card Detect This signal indicates when a SDIO MMC card is present l O 3 3V PU 10k 3 3V SDIO CLK 42 SDIO Clock With each cycle of this signal a one bit transfer on the command and each O 3 3V data line occurs This signal has maximum frequency of 48 MHz SDIO CMD 45 SDIO Command Response This signal is used for card initialization and for command l O 3 3V PU 10k transfers During initialization mode this signal is open drain During command transfer OD PP 3 3V this signal is in push pull mode SDIO LED 44 SDIO LED Used to drive an external LED to indicate when transfers occur on the bus O 3 3V PU 10k 3 3V SDIO WP 46 SDIO Write Protect This signal denotes the state of the write protect tab on SD cards l O 3 3V PU 10k 3 3V SDIO PWRZ 47 SDIO Power Enable This signal is used to enable the power being supplied to a SD O 3 3V Connected to GPIO MMC card device SDIO DATO 49 SDIO Data lines These signals operate in push pull mode 1 0 3 3V SDIO DAT1 48 PP SDIO DAT2 51 SDIO DAT3 50 SDIO DAT4 53 SDIO DAT5 52 SDIO DAT6 55 SDIO DAT7 54 Copyright O 2013 congatec AG QMX6m03 49 63 p congatec the rhythm of embedded computing 9 7 HDA I2S SPDIF Table 12 HDA AC 97 Signal Descriptions Description 1 0 PU PD Comment HDA_RST 61 HD Audio AC 97 Codec Res
12. debugging purposes May be used as JTAG TMS signal for NA NA boundary scan purposes during production May also be used via a multiplexer as vendor specific BOOT signal for firmware and boot loader implementations In this case the multiplexer must be controlled by the MFG NCA signal MFG NC4 204 This pin is reserved for manufacturing and debugging purposes May be used as JTAG_TRST signal for NA NA boundary scan purposes during production May also be used as control signal for a multiplexer circuit on the module enabling secondary function for MFG NCO 3 JTAG UART When MFG NC4A is high active it is being used for JTAG purposes When MFG NCA is low active it is being used for UART purposes o gt Note The MFG NCO2O 4 pins are reserved for manufacturing and debugging purposes It s recommended to route the signals to a connector on the carrier board The carrier board must not drive the MFG NC pins or have pull up or pull down resistors implemented for these signals MFG NCO 4 are defined to have a voltage level of 3 3V It must be ensured that the carrier board has the correct voltage levels for JTAG UART signals originating from the module For this reason a level shifting device may be required on the carrier board to guarantee that these voltage levels are correct in order to prevent damage to the module More information about implementing a carrier board multiplexer can be found in the Qseven Design G
13. factor optimized for mobile computing platforms eMMC Embedded Multi Media Card is a non volatile memory system which frees the processor from low level flash memory management SDIO card SDIO Secure Digital Input Output is a non volatile memory card format developed for use in portable devices USB Universal Serial Bus SATA Serial AT Attachment serial interface standard for hard disks HDA High Definition Audio HDMI High Definition Multimedia Interface HDMI supports standard enhanced or high definition video plus multi channel digital audio on a single cable TMDS Transition Minimized Differential Signaling TMDS is a signaling interface defined by Silicon Image that is used for DVI and HDMI DVI Digital Visual Interface is a video interface standard developed by the Digital Display Working Group DDWG lC Bus Inter Integrated Circuit Bus is a simple two wire bus with a software defined protocol that was developed to provide the communications link between integrated circuits in a system SM Bus System Management Bus is a popular derivative of the C bus SPI Bus Serial Peripheral Interface is a synchronous serial data link standard named by Motorola that operates in full duplex mode CAN Bus Controller area network is a vehicle bus standard designed to allow microcontrollers and devices to communicate with each other within a vehicle without a host computer AMBA Advanced Microcontroller Bus Architecture IOMUX Input Output Multiplex
14. for heatspreader screws is 0 3 Nm Mechanical system assembly mounting shall follow the valid DIN ISO specifications A cem When using the heatspreader in a high shock and or vibration environment congatec recommends the use of a thread locking fluid on the heatspreader screws to ensure the above mentioned torque specification is maintained Copyright O 2013 congatec AG QMX6m03 25 63 P congatec the rhythm of embedded computing 5 Connector Subsystems The conga QMX6 is based on the Qseven standard and therefore has 115 edge fingers on the top and bottom side of the module that mate with the 230 pin card edge MXM connector located on the carrier board This connector provides the ability to interface the available signals of the conga QMX6 with the carrier board peripherals 1x PCI Express Lane 1x HDMI UART GPIO onboard RS 232 SPI Gigabit Ethernet CAN Bus 1x Serial ATA JTAG 4x USB 2 0 Power Control 1x USB OTG Power Management SDIO MMC MicroSD Watchdog IS Audio lC Bus BB Copyright O 2013 congatec AG QMX6m03 26 63 P congatec the rhythm of embedded computing 5 1 PCI Express The conga QMX6 offers one PCI Express lane The PCle signals are routed from the Freescale i MX6 processor to the PCI Express port 0 of the conga QMX6 edge finger These signals support PCI Express Gen 2 0 interfaces at 5 Gb s and are backward compatible to Gen 1 1 interfaces at 2 5 Gb s Only x1 PCI Express link configuration is possibl
15. identical outputs single input sent to both output channels Two independent outputs two inputs sent each to a different output channel gt Note The LVDS interface can be used either as a single channel or as a dual channel It is also possible to use the LVDS interface as two independent single LVDS channels To do this it is recommended to configure the LVDS display in the bootloader Three independent displays are possible when connected as two single LVDS channel and one HDMI interface 5 9 HDMI High Definition Multimedia Interface HDMI is a licensable compact audio video connector interface for transmitting uncompressed digital streams HDMI encodes the video data into TMDS for digital transmission and is backward compatible with the single link Digital Visual Interface DVI carrying digital video The conga QMX6 provides HDMI connection directly from the Freescale i MX6 processor Video data is provided through three differential TMDS data pairs TMDS LANEOx to TMDS_LANE2 and one differential clock pair TMDS CLKxz In addition the conga QMX6 includes one standard I2C interface I2C2 SDA and I2C2 SCL for configuring and testing the HDMI 3D Tx PHY and a pin DP HDMI HPD for HDMI hot plug detection support 5 10 LPC GPIO The conga QMX6 does not support the Low Pin Count LPC signals instead eight GPIO pins shared with the LPC pins according to Qseven specification 2 0 are supported The General Purpose Input Output
16. on the 12C2 interface The multiplexer separates the PMIC functions from other devices camera HDMI that share the bus Due to this implementation the user needs to download the latest kernel from git congatec com public or at least ensure the congatec I2C multiplexer patches CGT000031 CGT000032 are applied to the desired kernel to achieve proper behaviour The I2C3 is also available on the SMB Bus signals pin 60 and 62 of the Qseven edge connector 34 63 p congatec the rhythm of embedded computing 6 Additional Features 6 1 High Assurance Boot HAB The High Assurance Boot is a software library executed in internal ROM on the Freescale processor at boot time which among other things authenticates software in external memory by verifying digital signatures The HAB enables the ROM to authenticate software which executes immediately after ROM by using digital signatures This software is usually a bootloader The High Assurance Boot component of the ROM protects against the potential threat of attackers modifying areas of code or data in programmable memory to make it behave in an incorrect manner 6 2 Dedicated Hardware Accelerators The Freescale i MX6 processor uses dedicated hardware accelerators to meet the targeted multimedia performance The use of hardware accelerators is a key factor in obtaining high performance at low power consumption while having the CPU core relatively free for performing other tasks The hardwa
17. pins can be configured as inputs or outputs When configured as output it is possible to write to an internal register to control the state driven on the output pin When configured as input the input state can be detected by reading the status of an internal register To select the GPIO mode configure the IOMUX Copyright O 2013 congatec AG QMX6m03 30 63 5 11 5 12 5 13 p congatec the rhythm of embedded computing SPI The Freescale i MX6 processor provides Enhanced Configurable Serial Peripheral Interfaces ECSPIs capable of up to 66 Mbps write speed and 31 Mbps read speed The ECSPI interfaces offer full duplex synchronous serial interface with maximum operation frequency up to the reference clock frequency It can be configured to support Master Slave modes and four chip selects to support multiple peripherals The conga QMX6 offers one SPI interface on the edge finger connector Another SPI interface from the Freescale i MX6 processor is connected to the 32 Mbit SPI Flash memory onboard the conga QMX6 The Freescale i MX6 processor is programmed to boot from the bootloader contained in the SPI flash memory CAN Bus The conga QMX6 supports CAN bus The CAN controller performs communication in accordance with the CAN Protocol Version 2 0B Active1 standard format and extended format The bit rate can be programmed to a maximum of 1 Mbit s based on the technology used To connect the CAN controller module to the CAN bus i
18. resistors that are located on the module No external DC loads or external pull up or pull down resistors should change the configuration of the signals listed in the above table External resistors may override the internal strap states and cause the Qseven module to malfunction and or cause irreparable damage to the module Additionally if it is necessary to have link and activity LEDs connected to GBE_LINK and GBE_ACT on the carrier board then you have to use buffers Without a buffer the strapping becomes active and this causes the PHY to be programmed with wrong address Copyright 2013 congatec AG QMX6m03 59 63 p congatec the rhythm of embedded computing 10 Onboard Interfaces and Devices 10 1 UART RS 232 Debug Port The conga QMX6 is equipped with a six pin RS232 connector onboard the conga QMX6 This RS 232 debug port is connected to the Freescale i MX6 UART1 and UART2 pins via the MAXIM 3232 transceiver The transceiver is guaranteed to run at data rates of 250kbps in normal operating mode while maintaining RS 232 output levels Refer to section 5 2 for more information about the UART interface Table 27 UART Signal Descriptions P Signal Molex Connector D SUB 1 Console Description 1 DCE1_TXT NC Pin 2 i MX6 UART 5 Serial Data Transmitter Red 2 NC NC NC Not Connected 3 GND Pin 5 Pin 5 Ground White 4 DCE2_TXT Pin 2 NC UART 2 Serial Data Transmitter Black 5 DCE2_RX Pin 3 NC UART 2 Serial Da
19. rhythm of embedded computing 44 63 p congatec the rhythm of embedded computing 9 1 PCI Express Table6 PCI Express Signal Descriptions Pin Description Comment PCIEO_RX 180 PCI Express channel 0 Receive Input differential pair PCIE Supports PCI Express Base Specification Revision 1 0a PCIEO RX 182 PCIEO TX 179 PCI Express channel 0 Transmit Output differential pair O PCIE Supports PCI Express Base Specification Revision 1 0a PCIEO TX 181 PCIE1_RX 174 PCI Express channel 1 Receive Input differential pair PCIE Not supported PCIE1 RX 176 PCIE1_TX 173 PCI Express channel 1 Transmit Output differential pair O PCIE Not supported PCIE1 TX 175 PCIE2_RX 168 PCI Express channel 2 Receive Input differential pair PCIE Not supported PCIE2 RX 170 PCIE2 TX 167 PCI Express channel 2 Transmit Output differential pair O PCIE Not supported PCIE2 TX 169 PCIE3_RX 162 PCI Express channel 3 Receive Input differential pair PCIE Not supported PCIE3 RX 164 PCIE3 TX 161 PCI Express channel 3 Transmit Output differential pair O PCIE Not supported PCIE3 TX 163 PCIE CLK REF 155 PCI Express Reference Clock Signals for Lanes 0 to 3 O PCIE PCIE CLK REF 157 PCIE WAKE 156 PCI Express Wake Event Sideband wake signal 13 3VSB PU 1k 3 3VSB connected to GPIO asserted by components requesting wakeup PCIE RST 158 Reset Signal for external devices O 3 3V 9 2 U
20. the ARM is in a low power mode 8 4 LVDS Bridge The LVDS Bridge LDB supports the flow of synchronous RGB data from the Image Processing Unit to external devices through LVDS interface This support includes synchronization and control capabilities connectivitity to relevant devices as well as proper data arrangement as required by the external display receiver and by LVDS display standards 8 5 USB Port Connections The conga QMX6 offers a total of 5 USB ports one USB OTG port and four Host only ports The four Host only ports found on the conga QMX6 are implemented by routing one Host only port USB H1 from the Freescale i MX6 processor to the conga QMX6 edge finger via a SMSC USB Hub The USB OTG port OTG client of the conga QMX6 is routed directly to the USB OTG port of the i MX6 processor This port can drop the hosting role and act as a normal USB device when conga QMX6 is attached to another host It is also used as a downstream and upstream port while the Host only cores are used as downstream ports For more information refer to the conga QMX6 USB routing diagram shown below Copyright O 2013 congatec AG QMX6m03 39 63 p congatec the rhythm of embedded computing conga QMX6 USB Routing Diagram USB Device USB 0 Host only USB 2 Host only USB Host S 3USB 3 Host only Freescale i MX6 jUSB 4 Host only ARM Cortex A9 Processor USB 1 Host Client Copyright 2013 congatec AG QMX6m0
21. 0V 3 6V DC Typical 3V DC CMOS Battery Power Consumption RTC 20 C Voltage Current RTC onboard the conga QMX6 module 3V DC 1 45 pA The CMOS battery power consumption value listed above should not be used to calculate CMOS battery lifetime You should measure the CMOS battery power consumption in your customer specific application in worst case conditions for example during high temperature and high battery voltage The self discharge of the battery must also be considered when determining CMOS battery lifetime For more information about calculating CMOS battery lifetime refer to application note AN9 RTC Battery Lifetime pdf which can be found on the congatec AG website at www congatec com gt Note To improve the lifetime of the CMOS battery congatec implemented an external real time clock onboard the conga QMX6 module Copyright 2013 congatec AG QMX6m03 20 63 p congatec the rhythm of embedded computing 2 7 Environmental Specifications Temperature Operation 0 to 60 C Storage 20 to 80 C commercial grade variants of conga QMX6 Temperature Operation 40 to 85 C Storage 40 to 85 C industrial grade variants of conga QMX6 Humidity Operation 10 to 90 Storage 5 to 95 humidity specifications are for non condensing conditions ton The above operating temperatures must be strictly adhered to at all times The congatec heatspreader is only suitable for use within commercial temperature ranges 0
22. 10Mbit sec modes transformer This signal pair is only used for 1000Mbit sec Gigabit Ethernet mode GBE CTREF 15 Reference voltage for carrier board Ethernet channel 0 magnetics center REF Not Supported tap The reference voltage is determined by the requirements of the module s PHY and may be as low as OV and as high as 3 3V The reference voltage output should be current limited on the module In a case in which the reference is shorted to ground the current must be limited to 250mA or less GBE LINK 13 Ethernet controller O link indicator active low O3 3V PP PD1k GBEO LINKZ is a bootstrap signal see note below GBE LINK1002 7 Ethernet controller 0 100Mbit sec link indicator active low O 3 3V PP PU 4k99 Not Supported Internally 2 5VSB_ connected to GBE ACT GBEO LINK100 is a bootstrap signal see note below GBE_LINK1000 8 Ethernet controller 0 1000Mbit sec link indicator active low O3 3V PP PD1k Not Supported Internally connected to GBE_LINK GBEO_LINK1000 is a bootstrap signal see note below GBE_ACT 14 Ethernet controller 0 activity indicator active low O 3 3V PP PU 4k99 GBEO_ACT is a bootstrap signal 2 5VSB see note below o gt Note congatec the rhythm of embedded computing The theoretical maximum performance of 1 Gbps Ethernet is limited to 470 Mbps total for Tx and Rx due to internal bus throughput limitations The actual measured performance in optimized environm
23. 1GB onboard Operating System Ubuntu Power State Desktop Idle 100 workload Max Power Consumption Power consumption Imeasured In AmpereslVWattsl 0 22 A 1 1 W 0 46 A 2 3 W 2 5 2 Freescale i MX6 Cortex A9 1 0 GHz Dual Lite 512kB L2 cache With 4GB onboard eMMC conga QMX6 Art No 016101 Freescale i MX6 Cortex A9 1 0 GHz 512kB L2 cache 40nm Layout Rev QMX6LB1 Bootloader Rev QMX6Rx07 Memory Size 1GB onboard Operating System Ubuntu Power State Desktop Idle 100 workload Max Power Consumption Power Consumption Imeasured mp AmperesWatte 0 26 A 1 3 W 0 44 A 2 2 W 0 66 A 3 3 W Copyright 2013 congatec AG QMX6m03 17 63 p congatec the rhythm of embedded computing 2 5 3 Freescale i MX6 Cortex A9 1 0 GHz Dual Core 1MB L2 cache With 4GB onboard eMMC conga QMX6 Art No 016102 Freescale i MX6 Cortex A9 1 0 GHz 1MB L2 cache 40nm Layout Rev QMX6LB1 Bootloader Rev QMX6Rx07 Memory Size 1GB onboard Operating System Ubuntu Power State Desktop Idle 100 workload Max Power Consumption NW de Ee Te BULLET TT BW NOT I3 EJ EU G MM 0 28 A 1 4 W 0 5A 2 5W 0 7 A 3 2 W 2 5 4 Freescale i MX6 Cortex A9 1 0 GHz Quad Core 1MB L2 cache With 4GB onboard eMMC conga QMX6 Art No 016103 Freescale i MX6 Cortex A9 1 0 GHz 1MB L2 cache 40nm Layout Rev QMX6LB1 Bootloader Rev QMX6Rx07 Memory Size 1GB onboard Operating System Ubuntu Power State De
24. 25 Fan Control Signal Descriptions esses 58 Table 26 Bootstrap Signal Deeg Gegner aunt ignotae ttti 59 Table 27 UART Signal Descriptions eeeeeeeceeenene 60 Table 28 Android Button Signal Descriptions sess 61 Copyright O 2013 congatec AG QMX6m03 10 63 p congatec the rhythm of embedded computing 1 INTRODUCTION Qseven Concept The Qseven concept is an off the shelf multi vendor Single Board Computer that integrates all the core components of a common PC and is mounted onto an application specific carrier board Qseven modules have a standardized form factor of 70mm x 70mm and a specified pinout based on the high speed MXM system connector The pinout remains the same regardless of the vendor The Qseven module provides the functional requirements for an embedded application These functions include but are not limited to graphics sound mass storage network interface and multiple USB ports A single ruggedized MXM connector provides the carrier board interface to carry all the I O signals to and from the Qseven module This MXM connector is a well known and proven high speed signal interface connector that is commonly used for high speed PCI Express graphics cards in notebooks Carrier board designers can utilize as little or as many of the I O interfaces as deemed necessary The carrier board can therefore provide all the interface conn
25. 3 40 63 p congatec the rhythm of embedded computing 9 Interface Signal Descriptions and Pinout Tables The following section describes the signals found on Qseven module s edge fingers and the interfaces implemented on the conga QMX6 Table 3 describes the terminology used in this section for the Signal Description tables The PU PD column indicates if a Qseven module pull up or pull down resistor has been used if the field entry area in this column for the signal is empty then no pull up or pull down resistor has been implemented by congatec The symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level When is not present the signal is asserted when at a high voltage level gt Note The Signal Description tables do not list internal pull ups or pull downs implemented by the chip vendors only pull ups or pull downs implemented by congatec are listed For information about the internal pull ups or pull downs implemented by the chip vendors refer to the respective chip s datasheet Not all the signals described in this section are available on all conga QMX6 variants Use the article number of the module and refer to the options table on page 8 to determine the options available on the module Table 4 Signal Tables Terminology Descriptions l Input Pin O Output Pin OC Open Collector OD Open Drain PP Push Pull UO Bi directional
26. 4 8bit SDA Resizing and Blending Inversion Rotation SD3 8bit PER Display and rf SR HDMI and PHY Dual 24 bit LVDS 12S Audio MIPI CSI2 SD2 4bit Security Cntrl Kg TrustZone Secure RTC FlexCAN CAN Bus Ciphers Gees SATA sara a NOTE The conga QMX6 BSPs do no currently F support the camera interface Copyright 2013 congatec AG QMX6m03 22 63 p congatec the rhythm of embedded computing 4 Heatspreader Thermal design is an important factor for systems This factor is critical when the power dissipation level increases in certain high performance use cases To ensure the performance and reliability of the system adequate thermal management technique such as the heatspreader is necessary The heatspreader acts as a thermal coupling device to the module It is thermally coupled to the CPU via a thermal gap filler and on some modules it may also be thermally coupled to other heat generating components with the use of additional thermal gap fillers Although the heatspreader is the thermal interface where most of the heat generated by the module is dissipated it is not to be considered as a heatsink It has been designed as a thermal interface between the module and the application specific thermal solution The application specific thermal solution may use heatsinks with fans and or heat pipes which can be attached to the heatspreader Some thermal solutions may also require that the heatspreader is attached dire
27. 62 63 p congatec the rhythm of embedded computing 11 Industry Specifications The list below provides links to industry specifications that apply to congatec AG modules Specification Link Qseven Specification Qseven Design Guide Low Pin Count Interface Specification Revision 1 0 LPC Universal Serial Bus USB Specification Revision 2 0 Serial ATA Specification Revision 1 0a PCI Express Base Specification Revision 2 0 Freescale website http www qseven standard org http www qseven standard org http developer intel com design chipsets industry Ipc htm http www usb org home http www serialata org http www pcisig com specifications http www freescale com QMX6m03 63 63 Copyright O 2013 congatec AG
28. ART Table7 UART Signal Descriptions Description Comment UARTO TX 171 Serial Data Transmitter O 3 3V UARTS3 TX signal from Processor UARTO RX 177 Serial Data Reciever 13 3V UART3_RX signal from Processor UARTO CTS 178 Handshake signal ready to send data 13 3V UART3_CTS signal from Processor UARTO_RTS 172 Handshake signal ready to receive data O 3 3V UART3_RTS signal from Processor Copyright 2013 congatec AG QMX6m03 45 63 9 3 Table 8 Gigabit Ethernet Ethernet Signal Descriptions Description PU PD E Comment GBE_MDI0 12 Media Dependent Interface MDI differential pair 0 The MDI can UO Analog Twisted pair signals for external GBE MDIO 10 operate in 1000 100 and 10Mbit sec modes transformer This signal pair is used for all modes GBE_MDI1 11 Media Dependent Interface MDI differential pair 1 The MDI can I O Analog Twisted pair signals for external GBE MDI1 9 operate in 1000 100 and 10Mbit sec modes transformer This signal pair is used for all modes GBE MDI2 6 Media Dependent Interface MDI differential pair 2 The MDI can I O Analog Twisted pair signals for external GBE MDI2 4 operate in 1000 100 and 10Mbit sec modes transformer This signal pair is only used for 1000Mbit sec Gigabit Ethernet mode GBE_MDI3 5 Media Dependent Interface MDI differential pair 3 The MDI can I O Analog Twisted pair signals for external GBE MDIS 3 operate in 1000 100 and
29. HDMI HPD 153 Hot plug detection signal that serves as an interrupt request 3 3V PD 100k HDMI interface gt Note On the conga QMX6 only the HDMI interface supports the Transition Minimized Differential Signaling TMDS Copyright 2013 congatec AG QMX6m03 52 63 p congatec the rhythm of embedded computing 9 11 LPC GPIO Table 16 LPC GPIO Signal Descriptions Pin Description UO Comment LPC_ADO 185 Multiplexed Command Address and Data LPC AD O 3 1 0 3 3V Shared with GPIOO GPIOO shared with General Purpose Input Output 0 3 LPC AD1 186 Shared with GPIO1 GPIO1 LPC AD2 187 Shared with GPIO2 GPIO2 LPC AD3 188 Shared with GPIO3 GPIO3 LPC_FRAME 190 LPC frame indicates the start of a new cycle or the termination I O 3 3V Shared with GPIO5 GPIO5 of a broken cycle Shared with General Purpose Input Output 5 LPC_LDRQ 192 LPC DMA request UO 3 3V Shared with GPIO7 GPIO7 General Purpose Input Output 7 LPC CLK 189 LPC clock shared with General Purpose Input Output 4 UO 3 3V The LPC clock output operates at 1 4th of FSB GPIO4 frequency By default the LPC clock is only active when LPC bus transfers occur Because of this behavior LPC clock must be routed directly to the bus device they cannot go through a clock buffer or other circuit that could delay the signal going to the end device SERIRQ 191 Serialized Interrupt V0 3 3V PU 10k Shared with GPIO6 GPIO6 General Purpose Input Output
30. Host Backwards compatible to USB 1 1 If USB ID is tied HIGH USB device Client If USB ID is HIGH USB 2 0 Client Backwards compatible to USB 1 1 USB P2 90 Universal Serial Bus Port 2 differential pair 1 0 USB 2 0 compliant Backwards compatible to USB 1 1 USB_P2 88 USB_P3 89 Universal Serial Bus Port 3 differential pair UO USB 2 0 compliant Backwards compatible to USB 1 1 USB P3 87 USB P4 84 Universal Serial Bus Port 4 differential pair UO USB 2 0 compliant Backwards compatible to USB 1 1 USB_P4 82 No USB 3 0 available USB_SSRX1 Multiplexed with receive signal differential pairs for the Superspeed l USB_SSRX1 USB data path USB_P5 83 Universal Serial Bus Port 5 differential pair UO Not supported USB_P5 81 USB_SSTX1 Multiplexed with transmit signal differential pairs for the Superspeed O USB SSTX1 USB data path Copyright 2013 congatec AG QMX6m03 47 63 congatec the rhythm of embedded computing Se USB_P6 78 Universal Serial Bus Port 6 differential pair UO Not supported USB_P6 76 USB_SSRX0 Multiplexed with receive signal differential pairs for the Superspeed l USB SSRXO USB data path USB Pri 77 Universal Serial Bus Port 7 differential pair IO Not supported USB_P7 75 USB_SSTX0 Multiplexed with transmit signal differential pairs for the Superspeed O USB SSTXO USB data path USB 0 1 OC 86 Over current detect input 1 This pin is used to monitor the USB power l 3 3
31. Input Output Pin 3 3VSB 3 3V tolerant active in standby state P Power Input NA Not applicable NC Not Connected PCIE PCI Express differential pair signals In compliance with the PCI Express Base Specification 1 0a GB_LAN Gigabit Ethernet Media Dependent Interface differential pair signals In compliance with IEEE 802 3ab 1000Base T Gigabit Ethernet Specification USB Universal Serial Bus differential pair signals In compliance with the Universal Serial Bus Specification 2 0 SATA Serial Advanced Technology Attachment differential pair signals In compliance with the Serial ATA High Speed Serialized AT Attachment Specification 1 0a SPI Serial Peripheral Interface bus is a synchronous serial data link that operates in full duplex mode CAN Controller Area Network bus is a vehicle bus standard that allows microcontrollers and devices to communicate with each other within a vehicle without a host computer LVDS Low Voltage Differential Signaling differential pair signals In compliance with the LVDS Owner s Manual 4 0 TMDS Transition Minimized Differential Signaling differential pair signals In compliance with the Digital Visual Interface DVI Specification 1 0 CMOS Logic input or output Copyright 2013 congatec AG QMX6m03 41 63 P congatec the rhythm of embedded computing Table 5 Edge Finger Pinout Pin Signal Pin Signa
32. LANEO DP LANEI 137 DisplayPort differential pair lines lane 1 Shared with O PCIE DisplayPort interface not supported DP LANE1 139 TMDS_LANE1 and TMDS LANE1 DP LANEO 149 DisplayPort differential pair lines lane 0 Shared with O PCIE DisplayPort interface not supported DP LANEO 151 TMDS LANE2 and TMDS LANE2 DP AUS 138 Auxiliary channel used for link management and VO PCIE DisplayPort interface not supported DP AUX 140 device control Differential pair lines DP HDMI 154 Hot plug detection signal that serves as an interrupt 13 3V DisplayPort interface not supported HPD request gt Note The conga QMX6 does not offer DisplayPort interface because the interface is not supported by the Freescale i MX6 processor 9 10 HDMI Table 15 HDMI Signal Descriptions Pin Description PU PD Comment TMDS_CLK 131 TMDS differential pair clock lines O TMDS HDMI interface TMDS CLK 133 TMDS LANEO 143 TMDS differential pair lines lane O O TMDS HDMI interface TMDS LANEO 145 TMDS_LANE1 137 TMDS differential pair lines lane 1 O TMDS HDMI interface TMDS LANE1 139 TMDS_LANE2 149 TMDS differential pair lines lane 2 O TMDS HDMI interface TMDS LANE2 151 HDMI CTRL CLK 152 DDC based control signal clock for HDMI device I O 3 3V OD PU 4k7 3 3V HDMI interface HDMI CTRL DAT 150 DDC based control signal data for HDMI device 1 0 3 3V OD PU 4k7 3 3V HDMI interface DP
33. VSB PU 10k over current of the USB Ports 0 and 1 3 3V USB 2 3 OC 85 Over current detect input 2 This pin is used to monitor the USB power l 3 3VSB PU 10k over current of the USB Ports 2 and 3 3 3V USB 4 5 OCH 80 Over current detect input 3 This pin is used to monitor the USB power l 3 3VSB PU 10k over current of the USB Ports 4 and 5 3 3V USB 6 7 OC 79 Over current detect input 4 This pin is used to monitor the USB power 3 3VSB PU 10k Not supported over current of the USB Ports 6 and 7 3 3VSB USB ID 92 USB ID pin 1 3 3VSB PU 10k Connected to GPIO Configures the mode of the USB Port 1 If the signal is detected as 3 3V being high active the chip will automatically configure USB Port 1 as USB Client and enable USB Client support This signal should be driven as OC signal by external circuitry USB CC 91 USB Client Connect pin 1 3 3VSB PD 10k If USB Port 1 is configured for client mode then an externally connected GND USB host should set this signal to high active in order to properly make the connection with the module s internal USB client controller If the external USB host is disconnected this signal should be set to low active in order to inform the USB client controller that the external host has been disconnected A level shifter protection circuitry should be implemented on the carrier board for this signal Copyright O 2013 congatec AG QMX6m03 48 63 p congatec the rhythm of embedded
34. ache18 5 17 2C EHE 34 2 5 5 Freescale i MX6 Cortex A9 1 0 GHz Quad Core 1MB L2 cache18 6 Additional FeSIUFBS uos trier depot fatali 35 ER in Rape ee ee EU nS 6 1 High Assurance Boot HA 35 cache 2GB eMMC mm 19 257 Freescale i MX6 Cortex A9 800 MHz Dual Lite 512kB L2 cache 6 2 Dedicated Hardware Accelerators AAA 35 6 3 Power Manage MOM siccsascssineccrccecvaccssanssseanunnseracdaccctenrenseevsuancent 35 2GB MMC EEN 19 64 D ic Volt dF Scali 35 258 Freescale i MX6 Cortex A9 800 MHz Dual Core 1MB L2 cache ynamic Voltage and Frequency Scaling 6 5 Smart Speed e e KEE 36 2GB ne c eg 19 259 Freescale i MX6 Cortex A9 800 MHz Quad Core 1MB L2 cache 6 6 cca eMe EERE 36 AG SIMI elm EE 20 7 ARM Technologie Sian E 37 2 6 Supply Voltage Battery POWer ssi iterare statua 20 e e 2 6 1 CMOS Battery Power Consumption ssssssssesssieseieserrnsrrereree 20 par EJIIS Sc eegen er SE i 7 3 50 E 37 3 s larei le e E EE 22 7 4 Floating Pm E eR m 37 4 Heatspreader EE 23 8 Ge 38 l 8 1 Freescale i MX6 Processor Features e 38 4 1 Heatspreader Dimensions eren 24 844 Temperature Monitor TEMPMON ae 38 5 Connector SUDSYStOMS 0 ssseeeeeeiesneseseenenssenerensnanei 26 82 Thermal Management 38 5 1 e 27 8 3 Audio E EH 20 5 2 UART RS 232 jj eene cec lus 27 8 4 LVDS Bridge SE Ee Ee 39 Copyright 2013 congatec AG QMX6m03 8 63 8 5 9 1 9 2 9
35. al bus throughput limitations The actual measured performance in optimized environment is up to 400 Mbps For more information consult Freescale s Errata ERRO04512 Some signals have special functionality during the reset process They may bootstrap some basic important functions of the module For more information refer to section 9 21 of this user s guide 5 4 SATA The Freescale i MX6 Cortex A9 processor on the conga QMX6 supports one SATA port only The supported signals are coupled with 10nF capacitors and then routed to conga QMX6 edge finger The conga QMX6 offers this SATA port on the MXM connector This port supports SATA I 1 5Gbps and SATA II 3Gbps and is compliant with SATA specification 3 0 AHCI specification 1 3 and Advanced Microcontroller Bus Architecture AMBA specification 2 0 gt Note SATA interface is only supported on conga QMX6 quad and dual core variants Solo core and dual lite variants do not support SATA 5 5 USB 2 0 The conga QMX6 offers five USB ports via USB 2 0 host controllers provided by the Freescale i MX6 Cortex A9 processor These controllers provide high performance USB functionality that complies with USB 2 0 specification and with OTG supplement The offered ports comprise of one USB OTG port and four USB hosts These four USB hosts are derived through the integration of an SMSC USB hub and are implemented by routing the USB H1 port of the processor to the SMSC Hub The USB OTG port OTG client
36. be driven active low by external circuitry to signal 1 3 3VSB Connected to GPIO that the system battery is low or may be used to signal some other external battery management event WAKE 17 External system wake event This may be driven active low by external circuitry to signal 3 3VSB an external wake up event SUS STAT 19 Suspend Status indicates that the system will be entering a low power state soon Not supported SUS_S3 18 S3 State This signal shuts off power to all runtime system components that are not O 3 3VSB Connected to PMIC maintained during S3 Suspend to Ram S4 or S5 states The signal SUS_S3 is necessary in order to support the optional S3 cold power state SUS S5 16 S5 State This signal indicates S4 or S5 Soft Off state O 3 3VSB Connected to PMIC SLP BING 21 Sleep button Low active signal used by the ACPI operating system to transition the 1 3 3VSB PU 10k Connected to GPIO system into sleep state or to wake it up again This signal is triggered on falling edge 3 3VSB LID_BTN 22 LID button Low active signal used by the ACPI operating system to detect a LID switch 3 3VSB PU 10k Connected to GPIO and to bring system into sleep state or to wake it up again 3 3VSB Copyright O 2013 congatec AG QMX6m03 55 63 9 17 Miscellaneous Table 22 Miscellaneous Signal Descriptions Description Se congatec the rhythm of embedded computing Comment
37. ck line OD 3 3V LVDS DID DAT 125 Primary functionality DisplayID DDC data line used for LVDS flat panel detection If 1 0 3 3V PU 4k7 GP2 I2C DAT primary functionality is not used it can be as General Purpose PC bus data line OD 3 3V LVDS BLC CLK 128 Control clock signal for external SSC clock chip If the primary functionality is not used 1 O 3 3V PU 4k7 Not supported eDP1 HPD it can be used as an emedded DisplayPort secondary Hotplug detection OD 3 3V LVDS BLC DAT 126 Control data signal for external SSC clock chip 1 0 3 3V PU 4k7 Not supported eDPO_HPD If the primary functionality is not used it can be used as an embedded DisplayPort OD 3 3V primary Hotplug detection gt Note The LVDS interface can be used either as a single channel or as a dual channel It is also possible to use the LVDS interface as two independent single LVDS channels To do this it is recommended to configure the LVDS display in the bootloader Copyright 2013 congatec AG QMX6m03 51 63 p congatec the rhythm of embedded computing 9 9 DisplayPort Table 14 DisplayPort Signal Descriptions Pin Description Comment DP_LANE3 131 DisplayPort differential pair lines lane 3 Shared with O PCIE DisplayPort interface not supported DP_LANE3 133 TMDS_CLK and TMDS_CLK DP_LANE2 143 DisplayPort differential pair lines lane 2 Shared with O PCIE DisplayPort interface not supported DP_LANE2 145 TMDS LANEO and TMDS
38. ctly to the systems chassis thereby using the whole chassis as a heat dissipater congatec AG offers three heatspreader variants for the conga QMX6 Each heatspreader variant is intended for specific conga QMX6 modules as shown in the table below Heatspreader Heatspreader Compatible conga QMX6 Comment EEG Part No PN Variants PN conga QMX6 HSP1 B 016160 016112 016113 For modules equipped with lidded FC PBGA CPU 1mm Gap Pad conga QMX6 HSP2 B 016161 016100 016101 016110 016111 For modules equipped with MA PBGA CPU 2mm Gap Pad conga QMX6 HSP3 B 016162 016102 016103 016104 For modules equipped with non lidded FC PBGA CPU heatstack solution o gt Note Currently only a few Freescale iMX6 on chip devices are enabled by default in the bootloader With this default configuration the conga QMX6 power consumption is low However power consumption may increase significantly depending on the application and the workload of the CPU A cm congatec Qseven heaspreaders have been specifically designed for use within commercial temperature ranges 0 to 60 C only When using industrial temperature variants of the conga QMX6 in industrial temperature ranges 40 to 85 C use of the conga QMX6 heatspreaders is not recommended by congatec furthermore its use is at the risk of the end user It is the responsibility of the end user to design an optimized thermal solution that meets the needs of their applicatio
39. d Max Power Consumption Power consumption measured in Amperes Watts TBD A W TBD AW 2 5 8 Freescale i MX6 Cortex A9 800 MHz Dual Core 1MB L2 cache 2GB eMMC With 2GB onboard eMMC conga QMX6 Art No 016112 Freescale i MX6 Cortex A9 800 MHz 1MB L2 cache 40nm Layout Rev QMX6LB1 Bootloader Rev QMX6Rx07 Memory Size 1GB onboard Operating System Ubuntu Power State Desktop Idle 100 workload Max Power Consumption DW de ELO SL Toe BULLET Te BW NATI EA Lit 0 30 A 1 5W 0 42 A 2 1 W 0 60 A 3 0 W Copyright O 2013 congatec AG QMX6m03 19 63 2 5 9 p congatec the rhythm of embedded computing Freescale i MX6 Cortex A9 800 MHz Quad Core 1MB L2 cache 2GB eMMC With 2GB onboard eMMC conga QMX6 Art No 016113 Freescale i MX6 Cortex A9 800 MHz 1MB L2 cache 40nm Layout Rev QMX6LB1 Bootloader Rev QMX6Rx07 Memory Size 1GB onboard Operating System Ubuntu Power State Desktop Idle 100 workload Max Power Consumption Power consumption measured aP EENE 0 30 A 1 5 W 0 54 A 2 7 W 0 72 A 3 6 W gt Note 2 6 2 6 1 All recorded power consumption values are approximate and only valid for the controlled environment described earlier 100 workload refers to the CPU workload and not the maximum workload of the complete module Power consumption results will vary depending on the workload of other components such as graphics engine memory etc Supply Voltage Battery Power 2
40. dules that are currently offered by congatec AG For more information about additional conga QMX6 variants offered by congatec contact your local congatec sales representative or visit the congatec website at www congatec com Table 1 Commercial variants Part No 016100 016101 016102 016103 016104 Processor Freescale i MX6 Cortex A9 Freescale i MX6 Cortex A9 Freescale i MX6 Cortex A9 Freescale i MX6 Cortex A9 Freescale i MX6 Cortex A9 1 0 GHz Single Core 1 0 GHz Dual Lite 1 0 GHz Dual Core 1 0 GHz Quad Core 1 0 GHz Quad Core L2 Cache 512 kB 512 kB 1 MB 1 MB 1 MB Onboard Memory 1GB DDR3 1GB DDR3 1GB DDR3 1GB DDR3 2GB DDR3 eMMC up to 8GB 4GB 4GB 4GB 4GB 4GB PCI Express Lane Yes Yes Yes Yes Yes CAN Bus Yes Yes Yes Yes Yes Gigabit Ethernet Yes Yes Yes Yes Yes SATA No No Yes Yes Yes Table 2 Industrial Variants Part No 016110 016111 016112 016113 Processor Freescale i MX6 Cortex A9 Freescale i MX6 Cortex A9 Freescale i MX6 Cortex AQ Freescale i MX6 Cortex A9 800 MHz Single Core 800 MHz Dual Lite 800 MHz Dual Core 800 MHz Quad Core L2 Cache 512 kB 512 kB 1 MB 1 MB Onboard Memory 1GB DDR3 1GB DDR3 1GB DDR3 1GB DDR3 eMMC up to 8GB 4GB 4GB 4GB 4GB PCI Express Lane Yes Yes Yes Yes CAN Bus Yes Yes Yes Yes Gigabit Ethernet Yes Yes Yes Yes SATA No No Yes Yes Caution Do not alter the conga QMX6 boot fuse settings These fuse settings are already programmed during production process and are not protected against alteration C
41. e For more information about the PCI Express interface on the edge finger refer to the conga QMX6 pinout table in section 9 Interface Signal Descriptions and Pinout Tables 5 2 UART RS 232 The conga QMX6 offers one UART interface on the MXM connector and two RS 232 interfaces onboard The UART offered on the MXM connector is fully featured with control signals 4 pin UART and is connected directly to UART3 port of the Freescale i MX6 Cortex A9 processor The conga QMX6 offers the two onboard RS 232 interfaces via a 6 pin Molex connector This connector is provided by routing the UART2 and UARTS pins of the Freescale i MX6 processor to the MAXIM 3232 transceiver The transceiver converts the Qseven UART CMOS level 3 3V to RS 232 voltage levels 5v and is guaranteed to run at data rates of 250 kbps in the normal operating mode while maintaining RS 232 output levels With the Molex connector you can output data to the console by using the appropriate RS 232 adapter cable The UART interfaces support speeds up to 4 0 Mbps and Non Return To Zero encording format RS 485 compatible 9 bit data format and IrDA compatible infrared slow data rate format gt Note You can realize a second UART interface on the MFG interface This implementation however requires a customized conga QMX6 variant Contact congatec support for more information To display the u boot output to console you need the RS232 adapter cable PN 48000023 See sect
42. ect to the terms and conditions set out in the respective owner s license agreements which are available at www congatec com and or upon request Beginning on the date of shipment to its direct customer and continuing for the published warranty period congatec AG represents that the products are new and warrants that each product failing to function properly under normal use due to a defect in materials or workmanship or due to non conformance to the agreed upon specifications will be repaired or exchanged at congatec s option and expense Customer will obtain a Return Material Authorization RMA number from congatec AG prior to returning the non conforming product freight prepaid congatec AG will pay for transporting the repaired or exchanged product to the customer Repaired replaced or exchanged product will be warranted for the repair warranty period in effect as of the date the repaired exchanged or replaced product is shipped by congatec or the remainder of the original warranty whichever is longer This Limited Warranty extends to congatec s direct customer only and is not assignable or transferable Except as set forth in writing in the Limited Warranty congatec makes no performance representations warranties or guarantees either express or implied oral or written with respect to the products including without limitation any implied warranty a of merchantability b of fitness for a particular purpose or c aris
43. ectors required to attach the system to the application specific peripherals This versatility allows the designer to create a dense and optimized package which results in a more reliable product while simplifying system integration The Qseven evaluation carrier board provides carrier board designers with a reference design platform and the opportunity to test all the Qseven UO interfaces available and then choose what are suitable for their application Qseven applications are scalable which means once a carrier board has been created there is the ability to diversify the product range through the use of different performance class Qseven modules Simply unplug one module and replace it with another no need to redesign the carrier board This document describes the features available on the Qseven evaluation carrier board Additionally the schematics for the Qseven evaluation carrier board can be found on the congatec website o gt Note The conga QMX6 design is based on the Qseven specification 2 0 and in revision B 0 design we took into consideration the Qseven Specification 2 0 Errata Copyright O 2013 congatec AG QMX6m03 11 63 P congatec the rhythm of embedded computing conga QMX6 Options Information The conga QMX6 is currently available in nine variants five commercial and four industrial This user s guide describes the features these variants offer Below you will find an order table showing the base configuration mo
44. ed for general audiences Copyright O 2013 congatec AG QMX6m03 3 63 P congatec the rhythm of embedded computing Symbols The following symbols are used in this user s guide ann Warnings indicate conditions that if not observed can cause personal injury om Cautions warn the user about how to prevent damage to hardware or loss of data o gt Note Notes call attention to important information that should be observed Copyright 2013 congatec AG QMX6m03 4 63 P congatec the rhythm of embedded computing Terminology Term Description PCI Express PCle Peripheral Component Interface Express next generation high speed Serialized UO bus ARM Advanced RISC Machine JTAG Joint Test Action Group eCSPI Enhanced Configurable Serial Peripheral Interface MIPI Mobile Industry CPU Interface GPIO General Purpose Input Output RGMII Reduced Gigabit Media Independent Interface PCI Express Lane One PCI Express Lane is a set of 4 signals that contains two differential lines for transmitting and two differential lines for Receiving Clocking information is embedded into the data stream X1 X2 x4 x8 x16 x1 refers to one PCI Express Lane of basic bandwidth x2 to a collection of two PCI Express Lanes etc Also referred to as x1 x2 x4 x8 or x16 link PCI Express Mini Card PCI Express Mini Card add in card is a small size unique form
45. ent is up to 400 Mbps For more information consult Freescale s Errata ERRO04512 Some signals have special functionality during the reset process They may bootstrap some basic important functions of the module For more information refer to section 9 21 of this user s guide Copyright 2013 congatec AG QMX6m03 46 63 9 4 9 5 SATA Table 9 SATA Signal Descriptions Description p congatec the rhythm of embedded computing Comment SATAO_RX 35 Serial ATA channel 0 Receive Input differential pair SATA Supports Serial ATA specification SATAO RX 37 Revision 3 0 SATAO_TX 29 Serial ATA channel 0 Transmit Output differential pair O SATA Supports Serial ATA specification SATAO TX 31 Revision 3 0 SATA1_RX 36 Serial ATA channel 1 Receive Input differential pair SATA Not supported SATA1_RX 38 SATA1_TX 30 Serial ATA channel 1 Transmit Output differential pair O SATA Not supported SATA1_TX 32 SATA_ACT 33 Serial ATA Led Open collector output pin driven during SATA command OC 3 3V Not supported activity USB 2 0 Table 10 USB Signal Descriptions Pin Description Comment USB PO 96 Universal Serial Bus Port 0 differential pair UO USB 2 0 compliant Backwards compatible to USB 1 1 USB_PO 94 USB_P1 95 Universal Serial Bus Port 1 differential pair UO If USB ID is LOW default USB 2 0 compliant Host USB P1 93 If USB ID is LOW default USB
46. er GbE Gigabit Ethernet LVDS Low Voltage Differential Signaling DDC Display Data Channel is an PC bus interface between a display and a graphics adapter N C Not connected N A Not available T B D To be determined Copyright O 2013 congatec AG QMX6m03 5 63 P congatec the rhythm of embedded computing Copyright Notice Copyright 2010 congatec AG All rights reserved All text pictures and graphics are protected by copyrights No copying is permitted without written permission from congatec AG congatec AG has made every attempt to ensure that the information in this document is accurate yet the information contained within is supplied as is Trademarks Product names logos brands and other trademarks featured or referred to within this user s guide or the congatec website are the property of their respective trademark holders These trademark holders are not affiliated with congatec AG our products or our website Warranty congatec AG makes no representation warranty or guaranty express or implied regarding the products except its standard form of limited warranty Limited Warranty per the terms and conditions of the congatec entity which the product is delivered from These terms and conditions can be downloaded from www congatec com congatec AG may in its sole discretion modify its Limited Warranty at any time and from time to time The products may include software Use of the software is subj
47. esign techniques Even with these techniques it is vital to manage the heat dissipation of the module in accordance with internal and external conditions The conga QMX6 employs basically two types of thermal management strategies Active Cooling During this cooling policy the operating system turns the fan on off Though the active thermal management technique provides better heat dissipation and lower thermal resistances the cooling solutions are however expensive and have large form factors Copyright O 2013 congatec AG QMX6m03 38 63 p congatec the rhythm of embedded computing Passive Cooling The passive cooling policy employs the technique of enhancing conduction and natural convection This passive thermal management procedure provides cost effective cooling solutions up to certain power levels without introducing reliability concerns Some of these techniques typically used are thermal gap fillers heatspreaders and heat shields 8 3 Audio Mux Audio Mux AUDMUX is one of the modules found in the audio subsystem of the Freescale i MX6 processor It provides flexible programmable routing of the on chip serial interfaces to and from off chip devices The AUDMUX includes internal port that connect to the processor serial interfaces and external ports that connect to off chip audio devices Connection is established by configuring the appropriate host and peripheral ports Though controlled by ARM the AUDMUX can route data even when
48. essary to add transceiver hardware to the carrier board 9 14 Input Power Table 19 Input Power Signal Descriptions SITE Pin Description I O Comment VCC 211 230 Power Supply 5VDC 5 P VCC_5V_SB 205 206 Standby Power Supply 5VDC 5 P VCC_RTC 193 3 V backup cell input VCC_RTC should be connected to a 3V backup cell for P power VCC_RTC 24 3 3 V RTC operation and storage register non volatility in the absence of system Copyright 2013 congatec AG QMX6m03 54 63 p congatec the rhythm of embedded computing GND 1 2 23 25 34 Power Ground P 39 40 57 58 73 74 97 98 117 118 135 136 141 142 147 148 159 160 165 166 183 184 197 198 9 15 Power Control Table 20 Power Control Signal Descriptions Signal Pin Description of Power Control signals UO PU PD Comment PWGIN 26 High active input for the Qseven module indicates that power from the power supply is I 5V PU 10k 5V ready PWRBTN 20 Power Button Low active power button input This signal is triggered on the falling edge 3 3VSB PU 10k 3 3V 9 16 Power Management Table 21 Power Management Signal Descriptions Signal Pin Description of Power Management signals PU PD Comment RSTBTN 28 Reset button input This input may be driven active low by an external circuitry to reset 3 3V the Qseven module BATLOW 27 Battery low input This signal may
49. et O 3 3V Connected to GPIO I2S_RST Multiplexed with 12S Codec Reset HDA_SYNC 59 Serial Bus Synchronization O 3 3V DS WS Multiplexed with 12S Word Select from Codec HDA BITCLK 63 HD Audio AC 97 24 MHz Serial Bit Clock from Codec O 3 3V I2S_CLK Multiplexed with I2S Serial Data Clock from Codec HDA_SDO 67 HD Audio AC 97 Serial Data Output to Codec O 3 3V I2S_SDO Multiplexed with I2S Serial Data Output from Codec HDA SDI 65 HD Audio AC 97 Serial Data Input from Codec 13 3V DS GD Multiplexed with I2S Serial Data Input from Codec gt Note The conga QMX 6 currently supports only 12S format 9 8 LVDS Table 13 LVDS Signal Descriptions Description UO PU PD Comment LVDS_PPEN 111 Controls panel power enable O 3 3V LVDS_BLEN 112 Controls panel Backlight enable O 3 3V LVDS BLT CTRL 123 Primary functionality is to control the panel backlight brightness via pulse width O 3 3V GP PWM OUTO modulation PWM When not in use for this primary purpose it can be used as General Purpose PWM Output LVDS_A0O 99 LVDS primary channel differential pair 0 O LVDS LVDS_AO 101 eDPO_TX0 Display Port primary channel differential pair 0 eDPO TXO LVDS A1 103 LVDS primary channel differential pair 1 OLVDS LVDS A1 105 eDPO_TX1 Display Port primary channel differential pair 1 eDPO_TX1 LVDS_A2 107 LVDS primary channel differential pair 2 O LVDS LVDS_A2 109 eDPO_TX2 Display Port primary channel differential pa
50. hanging the boot fuse settings will void the congatec AG warranty Copyright O 2013 congatec AG QMX6m03 12 63 p congatec the rhythm of embedded computing 2 Specifications 2 1 Feature List Table3 Feature Summary Form Factor Processor Memory Audio Ethernet Graphics Options Peripheral Interfaces Onboard Interfaces and Devices Bootloader gt Note Based on Qseven form factor specification revision 2 0 Freescale i MX6 Cortex A9 up to 2 GB onboard DDR3 memory DS format supported Gigabit Ethernet Qualcomm Atheros PHY on conga QMX6 rev B x Earlier conga QMX6 variants are equipped with Micrel KSZ9031 PHY Integrated video graphic subsystem consisting of Video Processing Unit VPU Graphic Processing Unit 3D GPU 2D GPU Open VG Image Processing Unit Display interface bridges LVDS HDMI MIPI DSI Supports three independent displays must be 2x single channel LVDS and 1x HDMI 1x HDMI 1 4 Two LVDS channels driven by the LVDS display bridge Support Single channel LVDS interface 1 x 18 bpp or 1 x 24 bpp up to 85 MHz per interface e g 1366x768 60Hz 35 blanking Dual channel LVDS interface 2 x 18 bpp OR 2 x 24 bpp up to 170 MHz pixel clock e g 1600x1200 60 Hz 35 blanking TE Video Decode Acceleration MPEG2 MP HP MPEG4 SP H 264 VC 1 DivX 1x Serial ATA Gen 2 3GB s 1x SDIO x1 PCI Express Lane Gen 2 0 offering up to 5 GB s 5x USB
51. ing from course of performance course of dealing or usage of trade Copyright 2013 congatec AG QMX6m03 6 63 P congatec the rhythm of embedded computing congatec AG shall in no event be liable to the end user for collateral or consequential damages of any kind congatec shall not otherwise be liable for loss damage or expense directly or indirectly arising from the use of the product or from any other cause The sole and exclusive remedy against congatec whether a claim sound in contract warranty tort or any other legal theory shall be repair or replacement of the product only 150 9007 Certification 77 NN 38 congatec AG is certified to DIN EN ISO 9001 2008 standard SZ Rec mm Technical Support Intertek congatec AG technicians and engineers are committed to providing the best possible technical support for our customers so that our products can be easily used and implemented We request that you first visit our website at www congatec com for the latest documentation utilities and drivers which have been made available to assist you If you still require assistance after visiting our website then contact our technical support department by email at support congatec com Lead Free Designs ROHS All congatec AG designs are created from lead free components and are completely ROHS compliant Electrostatic Sensitive Device All congatec AG products are electrostatic sensitive devices and are packaged accordingly Do no
52. ion 10 1 UART RS 232 Debug Port for more information about the RS232 adapter cable and the UART pin description A em The MFG NC4A pin is high active on the conga QMX6 module This means that the MFG interface on the edge connector functions as JTAG interface by default Therefore do not use the MFG interface for UART purposes or externally pull the MFG NCA4 pin to ground Failure to adhere to this warning may result to back driving which can damage the module If you need the UART function on the MFG interface then you require a customized conga QMX6 For more information contact congatec support Copyright O 2013 congatec AG QMX6m03 27 63 P congatec the rhythm of embedded computing 5 3 Gigabit Ethernet The conga QMX6 rev B x offers Gigabit Ethernet with the integration of Qualcomm Atheros Gigabit Transceiver This transceiver is implemented via the RGMII interface of the i MX6 processor The Ethernet interface consists of 4 pairs of low voltage differential pair signals designated from GBEO_MDI0 to GBEO_MDI3 plus control signals for link activity indicators These signals can be used to connect to a 10 100 1000 BaseT RJ45 connector with integrated or external isolation magnetics on the carrier board Earlier conga QMX6 revisions offer Gigabit Ethernet with the integration of Micrel KSZ 9031 Ethernet PHY o gt Note The theoretical maximum performance of 1 Gbps Ethernet is limited to 470 Mbps total for Tx and Rx due to intern
53. ir 2 eDPO_TX2 Copyright 2013 congatec AG QMX6m03 50 63 p congatec the rhythm of embedded computing LVDS_A3 113 LVDS primary channel differential pair 3 O LVDS LVDS_A3 115 eDPO_TX3 Display Port primary channel differential pair 3 eDPO TX3 LVDS A CLK 119 LVDS primary channel differential pair clock lines OLVDS LVDS A CLK 121 eDPO AUX Display Port primary auxiliary channel eDPO_AUX LVDS_BO 100 LVDS secondary channel differential pair 0 O LVDS LVDS_BO 102 eDP1_TX0 Display Port secondary channel differential pair 0 eDP1 TXO LVDS_B1 104 LVDS secondary channel differential pair 1 O LVDS LVDS B1 106 eDP1_TX1 Display Port secondary channel differential pair 1 eDP1_TX1 LVDS_B2 108 LVDS secondary channel differential pair 2 O LVDS LVDS_B2 110 eDP1_TX2 Display Port secondary channel differential pair 2 eDP1_TX2 LVDS_B3 114 LVDS secondary channel differential pair 3 O LVDS LVDS_B3 116 eDP1_TX3 Display Port secondary channel differential pair 3 eDP1_TX3 LVDS_B_CLK 120 LVDS secondary channel differential pair clock lines O LVDS LVDS B CLK 122 eDP1 AUX Display Port secondary auxiliary channel eDP1 AUX LVDS DID CLK 127 Primary functionality is DisplayID DDC clock line used for LVDS flat panel detection If 1 0 3 3V PU 4k7 GP2 I2C CLK primary functionality is not used it can be as General Purpose l C bus clo
54. ith integrated memory power RTC supply and additional bulk and linear regulators to power system peripherals multiple point of power supply across the PCB is drastically reduced 5 16 Watchdog The watchdog timer WDOG protects against system failures by providing a method of escaping from unexpected events or programming errors The software must periodically service the watchdog timer once the WDOG is activated Without the servicing the timer times out The Freescale i MX6 processor on the conga QMX6 offers two watchdog timers a watchdog timer integrated within the ARM Cortex A9 platform and a TrustZone watchdog timer Copyright O 2013 congatec AG QMX6m03 33 63 5 17 P congatec the rhythm of embedded computing I2C Bus The I2C bus is suitable for applications requiring occasional communications over a short distance between many devices The I2C interfaces offered by the Freescale i MX6 processor support up to 400 kbps depending on pin loading and timing characteristics The conga QMX6 offers three I2C interfaces I2C1 I2C2 and I2C3 on the Qseven edge connector The I2C2 and I2C3 buses on the edge connector are shared with some onboard devices I2C3 is shared with LVDS and RTC while I2C2 is shared with camera interface and HDMI The I2C1 bus is routed directly without sharing on the edge connector o gt Note Copyright 2013 congatec AG QMX6m03 On the conga QMX revision B x and later we implemented a multiplexer
55. l 1 GND 2 GND 3 GBE_MDI3 4 GBE_MDI2 5 GBE_MDI3 6 GBE MDI2 7 GBE LINK100 8 GBE_LINK1000 9 GBE_MDI1 10 GBE MDIO 11 GBE_MDI1 12 GBE_MDI0 13 GBE LINK 14 GBE_ACT 15 GBE CTREF 16 SUS S54 17 WAKE Z 18 SUS S3 19 SUS_STAT 20 PWRBTN Z 21 SLP_BTN 22 UD BTN 23 GND 24 GND 25 GND 26 PWGIN 27 BATLOW 28 RSTBTN 29 SATAO TX 30 SATA1 TX 31 SATAO TX 32 SATA1 TX 33 SATA_ACT 34 GND 35 SATAO RX 36 SATA1 RX 37 SATAO RX 38 SATA1 RX 39 GND 40 GND 41 BlOS_DISABLE BOOT_ALT 42 SDIO CLK 43 SDIO_CD 44 SDIO LED 45 SDIO CMD 46 SDIO WP 47 SDIO_PWR 48 SDIO DAT1 49 SDIO DATO 50 SDIO DAT 51 SDIO_DAT2 52 SDIO DAT5 53 SDIO_DAT4 54 SDIO DAT7 55 SDIO DAT6 56 RESERVED 57 GND 58 GND 59 HDA SYNC I2S WS 60 SMB CLK GP1 I2C CLK 61 HDA_RST 12S_RST 62 SMB DAT GP1 DC DAT 63 HDA BITCLK 12S CLK 64 SMB_ALERT 65 HDA_SDI 12S_ SDI 66 GPO I2C CLK 67 HDA SDO I2S SDO 68 GPO I2C DAT 69 THRM 70 WDTRIG 71 THRMTRIP 72 WDOUT 73 GND 74 GND 75 USB P7 USB SSTXO 76 USB P6 USB SSRXO 77 USB P7 USB SSTXO 78 USB P6 USB SSRXO0 Copyright O 2013 congatec AG QMX6m03 42 63 79 USB 6 7 OCH 80 USB 4 5 OC 81 USB P5 USB SSTX1 82 USB P4 USB SSRX1 83 USB P5 USB SSTX1 84 USB_P4 USB_SSRX1 85 USB 2
56. med instead of the clock speed The set of tasks determines the execution units needed to make sure the system work more efficiently This ensures that the system provides enough performance without wasting resources With the Smart Speed Technology several execution units work in parallel thereby providing higher processor speed at lower power consumption System parallelism is accomplished via the Smart Speed crossbar switch that nearly eliminates wait states This results in improved processor performance without power consumption penalty associated with higher operating frequencies By employing Smart Speed Technology portable devices can run longer retain smaller form factors and support more innovative applications without substantially increasing the battery power 6 6 Suspend Mode The Suspend Mode feature is available on the conga QMX6 Copyright 2013 congatec AG QMX6m03 36 63 P congatec the rhythm of embedded computing 7 ARM Technologies 7 1 Media Processing Engine MPE NEON The Media Processing Engine MPE NEON is a single instruction multiple data SIMD instruction set that provides flexible and powerful acceleration for media and signal processing applications Support for a wide range of multimedia codecs with fewer cycles helps in enhancing user experience NEON is used for multimedia data processing 7 2 Jazelle DBX The Jazelle is an instruction set that introduces technological infrastructure for running java
57. n within the industrial environmental conditions it operates in There are mounting holes on the heatspreader designed to attach the heatspreader to the module These mounting holes must be used to ensure that all components that are required to make contact with heatspreader do so Failure to utilize these mounting holes will result in improper contact between these components and heatspreader thereby reducing heat dissipation efficiency Copyright O 2013 congatec AG QMX6m03 23 63 p congatec the rhythm of embedded computing Attention must be given to the mounting solution used to mount the heatspreader and module into the system chassis Do not use a threaded heatspreader together with threaded carrier board standoffs The combination of the two threads may be staggered which could lead to stripping or cross threading of the threads in either the standoffs of the heatspreader or carrier board 4 1 Heatspreader Dimensions conga QMX6 HSP1 B and HSP2 B 1mm for conga QMX6 HSP1 B 2mm for conga QMX6 HSP2 B Copyright 2013 congatec AG QMX6m03 24 63 p congatec conga QMX6 HSP3 B the rhythm of embedded computing Al Heatstack BOM Position 5 ed _f nes 565 amp w L eo e e 498 70 Xi o gt Note All measurements are in millimeters Torque specification
58. nga QMX6 uses the I28 format for audio signals These signals are derived from the Synchronous Serial Interface SSI of the Freescale i MX6 processor The SSI is a full duplex serial port that allows communication with external devices using a variety of serial protocols The I2S protocol is part of the protocols supported by the Freescale i MX6 Cortex A9 processor The SSI supports up to 1 4 Mbps gt Note The conga QMX 6 currently supports only 12S format LVDS The LVDS Display Bridge LDB from the Freescale i MX6 Cortex A9 processor found on the conga QMX6 offers two LVDS channels with up to 170 Mhz pixel clock Each channel consists of one clock pair and four data pairs The LDB supports the flow of synchronous RGB data from the Image Processing Unit IPU to external display devices through LVDS interface The LVDS interface supports 18 bit and 24 bit dual channel The LVDS interface also supports various resolutions but with stipulated maximum data rates The data rates supported are as follows For single channel output Up to 85 MHz per interface e g 1366x768 60 Hz 35 blanking Copyright O 2013 congatec AG QMX6m03 29 63 p congatec the rhythm of embedded computing For dual channel output Up to 170 MHZ pixel clock e g 1600x1200 60Hz 35 blanking The LVDS ports support the following configurations One single channel output One dual channel output single input split to two output channels Two
59. nsumption value that is measured for the module The USB keyboard was detached once the module was configured within the OS All recorded values were averaged over a 30 second time period The modules were cooled by the heatspreader specific to the module variants Each module was measured while running 32 bit Linaro Ubuntu 11 10 To measure the worst case power consumption the cooling solution was removed and the CPU core temperature was allowed to run between 95 and 100 C at 100 workload The peak current value was then recorded This value should be taken into consideration when designing the system s power supply to ensure that the power supply is sufficient during worst case scenarios Power consumption values were recorded during the following stages Linaro Ubuntu 11 10 32 bit Desktop Idle 10096 CPU workload 100 CPU workload at approximately 100 C peak power consumption BCC Note With the linux stress tool we stressed the CPU to maximum frequency Copyright O 2013 congatec AG QMX6m03 16 63 congatec the rhythm of embedded computing Processor Information The tables below provide additional information about the different variants offered by the conga QMX6 2 5 1 Freescale i MX6 Cortex A9 1 0 GHz Single Core 512kB L2 cache With 4GB onboard eMMC conga QMX6 Art No 016100 Freescale i MX6 Cortex A9 1 0 GHz 512kB L2 cache 40nm Layout Rev QMX6LB1 Bootloader Rev QMX6Rx07 Memory Size
60. ntime system components that are not maintained during suspend mode This signal is an output signal and is connected to the Power Management Integrated Circuit PMIC See section 9 16 Power Management for more information PWRBTN When using ATX style power supplies PWRBTN pin 20 is used to connect to a momentary contact active low debounced push button input while the other terminal on the push button must be connected to ground This signal is internally pulled up to 3V_SB using a 10k resistor When PWRBTNH is asserted it indicates that an operator wants to turn the power on or off gt Note The conga QMX 6 boots up immediately power is applied to the modules 5v input rail To shutdown the system use the the linux command poweroff Depending on the operating system the shutdown can also be performed by pressing the power button If the system is in shutdown or standby state pressing the power button restores the system back to full on state When the chip main power supply is Off a button press greater in duration than 750 ms asserts an output signal to request power from a power IC to power up the SoC If it s desired to keep the system switched off even when the 5V input power rail is initially powered on ATX style an external logic has to be used that prevents the system from booting by means of the power good signal PWGIN It is the responsibility of the external logic to release the PWGIN signal when the desired e
61. o the ECSPI 1 interface of the i MX6 processor The Freescale i MX6 processor is programmed to boot from the SPI flash 10 5 Android Buttons Table 28 Android Button Signal Descriptions Onboard the conga QMXG6 is an eight pin connector for implementing android buttons The signals are directly connected to the Freescale i MX6 processor P Description Comment PWRBTN 1 Power button signal KEY VOL UP 2 Increases volume GPIO7 13 HOME 3 Returns to the main home screen GPIO2 4 SEARCH 4 Brings up the search function GPIO2 3 BACK 5 Takes you a level back in an app ora page GPIO2 2 back in a browser MENU 6 Displays additional options in an application GPIO2 1 KEY VOL DN 7 Decreases volume GPIO4 5 GND 8 Ground 10 6 DDR3 Memory The conga QMX6 offers a 2GB DDR3 SDRAM memory onboard The memory modules are connected directly to the DDR ports of the Freescale i MX6 processor Copyright O 2013 congatec AG QMX6m03 61 63 E the rhythm of embedded computing 10 7 eMMC The conga QMX6 offers a 4G eMMC module onboard The onboard eMMC is a nand flash device and it is routed directly to the SDIO port 3 of the Freescale i MX6 processor Eight lanes are used for data 10 8 Micro SD The conga QMX6 offers an onboard micro SD connector backside of the module It is connected to the SDIO port 2 of the Freescale i MX6 processor Four lanes are used for data Copyright O 2013 congatec AG QMX6m03
62. onics 1 0 3 3V Currently implemented control bus CEC of HDMI as HDMI Consumer Electronics Control Bus Copyright O 2013 congatec AG QMX6m03 56 63 p congatec the rhythm of embedded computing 9 18 Manufacturing JTAG Interface Table 23 Manufacturing Signal Descriptions Description Comment MFG NCO 207 This pin is reserved for manufacturing and debugging purposes May be used as JTAG TCK signal for NA NA boundary scan purposes during production or as a vendor specific control signal When used as a vendor specific control signal the multiplexer must be controlled by the MFG NCA4 signal MFG NC1 209 This pin is reserved for manufacturing and debugging purposes May be used as JTAG TDO signal for NA NA See caution statement boundary scan purposes during production May also be used via a multiplexer as a UART_TX signal to below connect a simple UART for firmware and boot loader implementations In this case the multiplexer must be controlled by the MFG NC4A signal MFG NC2 208 This pin is reserved for manufacturing and debugging purposes May be used as JTAG TDI signal for NA NA See caution statement boundary scan purposes during production May also be used via a multiplexer as a UART RX signal to below connect a simple UART for firmware and boot loader implementations In this case the multiplexer must be controlled by the MFG NCA4A signal MFG NC3 210 This pin is reserved for manufacturing and
63. ormance for general purpose applications Copyright 2013 congatec AG QMX6m03 37 63 p congatec the rhythm of embedded computing 8 conga Tech Notes The conga QMX6 has some technological features that require additional explanation The following section will give the reader a better understanding of some of these features 8 1 Freescale i MX6 Processor Features 8 1 1 Temperature Monitor TEMPMON The Freescale i MX6 Cortex A9 processors have a temperature sensor module that implements a temperature sensor conversion function based on a temperature dependent voltage to time conversion The module features an alarm function that can raise an interrupt signal if the temperature is above a specified threshold A self repeating mode can also be programmed which executes a temperature sensing operation based on a programmed delay Software can use this module to monitor the on die temperature and take appropriate actions such as throttling back the core frequency when a temperature interrupt is set During normal system operation software can use the temperature sensor counter output in conjunction with the fused temperature calibration data to determine the on die operational temperature or to set an over temperature interrupt alarm to within a couple of degree centigrade 8 2 Thermal Management To meet low power design requirement while maintaining a high performance operation the Freescale iMX6 incorporated several low power d
64. p congatec the rhythm of embedded computing Qseven conga QMX6 Freescale i MX6 ARM Cortex A9 processor with Ultra Low Power Consumption User s Guide Revision 0 3 Preliminary p congatec the rhythm of embedded computing Revision History Revision Date yyyy mm dd Author Changes 0 1 2013 03 28 AEM e Preliminary release 0 2 2013 11 05 AEM Corrected the LVDS data rates resolutions supported in sections 2 1 Feature List and 5 8 LVDS Added information about the Atheros Quadcomm Ethernet PHY for conga QMX6G revision B 0 in sections 2 1 Feature List and 5 3 Gigabit Ethernet Updated section 4 Heatspreader Added additional heatspreader variants Updated section 5 2 UART Updated section 5 13 Manufacturing Jtag Interface Added pin descriptions for the onboard UART connector and the RS 232 adapter cable in section 10 1 UART RS 232 Debug Port Added section 10 3 JTAG Interface 0 3 2014 02 28 AEM Added the new Ethernet PHY Qualcomm Atheros for conga QMX6 revision B x to relevant sections Changed the eMMC value of industrial variants from 2G to 4G e Deleted the row RSVD from table 23 Manufacturing Signal Description e Edited section 5 2 UART and added caution statement Updated the whole document Copyright O 2013 congatec AG QMX6m03 2 63 p congatec the rhythm of embedded computing Preface This user s guide provides information about
65. re accelerators available in the processor are VPU IPUv3H 3D GPU 2D GPU OpenVG 1 1 GPU and Asynchronous Sample Rate Converter ASRC 6 3 Power Management The Freescale i MX6 processor integrates power management functions to simplify system power management requirements The processor provides power management units for offering power to various Soc domains Temperature sensor for monitoring the die temperature is also provided Dynamic Voltage and Frequency Scaling techniques software state retention power gating and various levels of system power mode are supported The use of simple and low cost power regulators in place of complicated external power management ICs reduces system design cost 6 4 Dynamic Voltage and Frequency Scaling Dynamic Voltage and Frequency Scaling is a power management technique used in changing the clock frequency and or the operating voltage of a processor based on system performance requirements at any point in time This scaling is normally carried out during less demanding periods of nominal run speed In General it helps in balancing the performance demands of processor with the high amount of power needed to satisfy those demands Copyright O 2013 congatec AG QMX6m03 35 63 P congatec the rhythm of embedded computing 6 5 Smart Speed Technology The Freescale s Smart Speed Technology with enhanced Cycles Per Instruction eCPI determines the speed of the processor by the set of tasks to be perfor
66. right O 2013 congatec AG QMX6m03 32 63 p congatec the rhythm of embedded computing Inrush and Maximum Current Peaks on VCC_5V_SB and VCC The inrush current on the conga QMX6 VCC_5V_SB power rail can go up as high as 2 3A for a maximum of 100uS Sufficient decoupling capacitance must be implemented to ensure proper power up sequencing The maximum peak current on the conga QMX6 VCC 5V power rail can be as high as 3 0A This requires that the power supply be properly dimensioned o gt Note For more information about power control event signals refer to the Qseven specification 5 15 Power Management Onboard the conga QMX6 is a 14 channel configurable Power Management Integrated Circuit PMIC The PMIC provides a cost effective programmable power management solution for a wide range of applications This high efficiency configurable power management IC is designed to work seamlessly with Freescale processors The Freescale i MX6 cortex A9 processor uses advanced integration Power Management Unit PMU to reduce supply connections The PMIC complements the processor s internal regulators in providing a complete and simple way to supply voltage domain with different voltages when needed The PMIC features four bulk regulators up to six independent outputs one boost regulator six general purpose LDOs one switch LDO combination and a DDR voltage reference to supply voltages for the application processor and peripheral devices W
67. sktop Idle 100 workload Max Power Consumption Power Consumptlon Imeasured In AmperesVattsl 0 3 A 1 5 W 0 72 A 3 6 W 0 92 A 4 6 W 2 5 5 Freescale i MX6 Cortex A9 1 0 GHz Quad Core 1MB L2 cache With 4GB onboard eMMC conga QMX6 Art No 016104 Freescale i MX6 Cortex A9 1 0 GHz 1MB L2 cache 40nm Layout Rev QMX6LB1 Bootloader Rev QMX6Rx07 Memory Size 2GB onboard Operating System Ubuntu Power State Desktop Idle 100 workload Max Power Consumption Power Consumption Imeasured Im AmperesVattsl 0 3 A 1 5 W 0 74 AI 3 7 W 0 94 A 4 7 W Copyright 2013 congatec AG QMX6m03 18 63 p congatec the rhythm of embedded computing 2 5 6 Freescale i MX6 Cortex A9 800 MHz Single Core 512kB L2 cache 2GB eMMC With 2GB onboard eMMC conga QMX6 Art No 016110 Freescale i MX6 Cortex A9 800 MHz 512kB L2 cache 40nm Layout Rev QMX6LB1 Bootloader Rev QMX6Rx07 Memory Size 1GB onboard Operating System Ubuntu Power State Desktop Idle 100 workload Max Power Consumption Power Consumption Imeasured In AmperesVattel 0 24 A 1 2 W 0 30 A 1 5 W 0 48 A 2 1 W 2 5 7 Freescale i MX6 Cortex A9 800 MHz Dual Lite 512kB L2 cache 2GB eMMC With 2GB onboard eMMC conga QMX6 Art No 016111 Freescale i MX6 Cortex A9 800 MHz 512kB L2 cache 40nm Layout Rev QMX6LB1 Bootloader Rev QMX6Rx07 Memory Size 1GB onboard Operating System Ubuntu Power State Desktop Idle 100 workloa
68. t is necessary to add transceiver hardware A complete description of the CAN controller registers and functionality is beyond the scope of this user s guide Consult Freescale s i MX6 processor reference manual for additional information about this interface Manufacturing JTAG Interface The manufacturing signals defined in Qseven Specification 2 0 are reserved for either manufacturing or debugging purposes The conga QMX6 offers this interface as a 10 pin JTAG interface for debugging purposes This interface is connected to the JTAG controller of the Freescale i MX6 processor The JTAG control fuses are used to allow or disallow JTAG access to secured resources o gt Note 5 14 Copyright O 2013 congatec AG QMX6m03 31 63 For compatible JTAG adapters contact the congatec support team or order the Nit6X JTAG from Boundary Devices Power Control PWGIN pin 26 can be connected to an external power good circuit or it may also be utilized as a manual reset input To use PWGIN as a manual reset input the pin must be grounded through the use of a momentary contact push button switch When external circuitry asserts this signal it is necessary that an open drain driver drives this signal causing it to be held low for a minimum of 15ms to initiate a reset Using this input is optional For more information see the note below p congatec the rhythm of embedded computing SUS_S3 The SUS_S3 pin 18 signal shuts off power to all ru
69. t open or handle a congatec AG product except at an electrostatic free workstation Additionally do not ship or store congatec AG products near strong electrostatic electromagnetic magnetic or radioactive fields unless the device is contained within its original manufacturer s packaging Be aware that failure to comply with these guidelines will void the congatec AG Limited Warranty Copyright 2013 congatec AG QMX6m03 7 63 p congatec the rhythm of embedded computing Contents 1 INTRODUC HON EEN 11 5 3 Gigabit Gun E 28 5 4 eege 28 2 SPECIFICATIONS NEEN 13 55 USB2 dr T 28 2 1 zc dtc e EE 13 56 SD SDIO MMC een 29 22 Supported Operating Systems 14 5 7 FDA I2SIAQ EE 29 23 Mechanical Dimensions o esse 14 5 8 LVDS mA 29 24 Supply Voltage Standard Power 15 5 9 able LM 30 24 1 Electrical Characteristics 15 5 10 WE GHG IO EE 30 24 2 FTES TANG EENEG 15 5 11 elu EE 31 2 5 Power Consumpltion ceret tentent ect nd 16 5 12 CAN Bus D 31 2 5 1 Freescale i MX6 Cortex A9 1 0 GHz Single Core 512kB L2 cache 5 13 Manufacturing JTAG Interface e 31 17 5 14 Power COMO fp T 31 2 5 2 Freescale i MX6 Cortex A9 1 0 GHz Dual Lite 512kB L2 cache17 5 15 Power AACS GIN ense fees cde danse add qui unus ab M AR BOE 33 2 5 3 Freescale i MX6 Cortex A9 1 0 GHz Dual Core 1MB L2 cache18 5 16 Watchdog REC c 33 2 54 Freescale i MX6 Cortex A9 1 0 GHz Quad Core 1MB L2 c
70. ta Receiver Orange 6 DCE1_RX NC Pin 3 i MX6 UART 5 Serial Data Receiver Purple CH Note The RS232 adapter cable PN 48000023 for the onboard UART interface is included in the congatec Qseven Evaluation kit You can also order this cable separately from congatec AG For more information contact your congatec sales representative 10 2 MIPI CMOS Camera The Freescale i MX6 Image Processing Unit IPU provides connectivity to cameras via the MIPI CSI 2 transmitter and maintains image manipulation and processing with adequate synchronization and control The Camera Serial Interface CSI controls the camera port and provides interface to an image sensor or a related device The role of the camera ports is to receive input from video sources and to provide support for time sensitive signals to the camera Non time sensitive controls such as configuration reset are performed by the ARM platform through 12C interface or GPIO signals gt Note The conga QMX6 BSPs do not currently support the camera interface Copyright 2013 congatec AG QMX6m03 60 63 p congatec the rhythm of embedded computing 10 3 JTAG Interface The conga QMX6 offers an onboard 10 pin JTAG interface For compatible JTAG adapters contact congatec support team or use the Nit6X_JTAG adapter Boundary Devices 10 4 SPI Flash Onboard the conga QMX6 is a 32 Mbit SPI flash memory This flash memory contains the bootloader and is directly connected t
71. the components features connectors and signals available on the conga QMX6 It is one of four documents that you should refer to when designing an i MX6 based Qseven application The other reference documents that should be used include the following Qseven Design Guide Qseven Specification i MX6 Applications Processor Reference Manual available at www freescale com The links to these documents can be found on the congatec AG website at www congatec com Disclaimer The information contained within this user s guide including but not limited to any product specification is subject to change without notice congatec AG provides no warranty with regard to this user s guide or any other information contained herein and hereby expressly disclaims any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing congatec AG assumes no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for discrepancies between the product and the user s guide In no event shall congatec AG be liable for any incidental consequential special or exemplary damages whether based on tort contract or otherwise arising out of or in connection with this user s guide or any other information contained herein or the use thereof Intended Audience This user s guide is intended for technically qualified personnel It is not intend
72. uide Caution The MFG NCZ4A pin is high active on the conga QMX6 module This means that the MFG interface on the edge connector functions by default as JTAG interface Therefore do not use the MFG interface for UART purposes or externally pull the MFG NC4A pin to ground Failure to adhere to this warning may result to back driving which can damage the module If you need the UART function on the MFG interface then you require a customized conga QMX 6 For more information contact congatec support Copyright O 2013 congatec AG QMX6m03 57 63 9 19 Thermal Management Table 24 Thermal Management Signal Descriptions p congatec the rhythm of embedded computing Description PU PD Comment THRM 69 Thermal Alarm active low signal generated by the external hardware to indicate an 3 3V PU 10k Connected to GPIO over temperature situation This signal can be used to initiate thermal throttling 3 3V THRMTRIP 71 Thermal Trip indicates an overheating condition of the processor If THRMTRIP O 3 3V Connected to GPIO goes active the system immediately transitions to the S5 State Soft Off 9 20 Fan Control Table 25 Fan Control Signal Descriptions Pin Description PU PD Comment FAN_PWMOUT 196 Primary functionality is fan speed control Uses the Pulse Width Modulation PWM O 3 3V GP PWM OUT technique to control the Fan s RPM based on the CPU s die temperature When not in use OC for this primar
73. used All measurements are in millimeters Carrier Board PCB Rear View of Qseven Module Copyright 2013 congatec AG QMX6m03 14 63 2 4 Supply Voltage Standard Power e DV DC 59 The dynamic range shall not exceed the static range 5 25V 4 75V 2 4 1 Electrical Characteristics Characteristics p congatec the rhythm of embedded computing Absolute Maximum Dynamic Range Nominal Static Range AA Absolute Minimum Comment Current VIC 5 4 75 5 00 5 25 Vdc Ripple E S 50 mV 0 20MHz VIC 5 4 75 5 00 5 25 Vde 50 DM Ripple 2 4 2 Rise Time The input voltages shall rise from 10 of nominal to 90 of nominal at a minimum slope of 250V s The smooth turn on requires that during the 10 to 90 portion of the rise time the slope of the turn on waveform must be positive gt Note For information about the input power sequencing of the Qseven module refer to the Qseven specification Copyright 2013 congatec AG QMX6m03 15 63 P congatec the rhythm of embedded computing 2 5 Power Consumption The power consumption values listed in this document were measured under a controlled environment The hardware used for testing includes a conga QMX6 module carrier board for Qseven ARM TFT monitor micro SD card and USB keyboard The carrier board was powered externally by a power supply unit so that it does not influence the power co
74. vent e g pressing the power button occurs Power Supply Implementation Guidelines 5 volt input power is the sole operational power source for the conga QMX6 The remaining necessary voltages are internally generated on the module using onboard voltage regulators When designing a power supply for a conga QMX6 application a carrier board designer should be aware of the important information below t has been noticed that on some occasions problems occur when using a 5V power supply that produces non monotonic voltage when powered up The problem is that some internal circuits on the module e g clock generator chips will generate their own reset signals when the supply voltage exceeds a certain voltage threshold A voltage dip after passing this threshold may lead to these circuits becoming confused resulting in a malfunction It must be mentioned that this problem is quite rare but has been observed in some mobile power supply applications The best way to ensure that this problem is not encountered is to observe the power supply rise waveform through the use of an oscilloscope to determine if the rise is indeed monotonic and does not have any dips This should be done during the power supply qualification phase therefore ensuring that the above mentioned problem doesn t arise in the application For more information about this issue visit www formfactors org and view page 25 figure 7 of the document ATX12V Power Supply Design Guide V2 2 Copy
75. y purpose it can be used as General Purpose PWM Output FAN TACHOIN 195 Primary functionality is fan tachometer input When not in use for this primary purpose it can 3 3V Connected to GPIO GP TIMER IN be used as General Purpose Timer Input Copyright O 2013 congatec AG QMX6m03 58 63 9 21 Bootstrap Signals Table 26 Bootstrap Signal Descriptions Pin Description of Bootstrap Signal PU PD congatec the rhythm of embedded computing Se Comment GBE LINK Ethernet controller 0 link indicator active low O 2 5VSB PU 4k99 GBEO LINK is a bootstrap signal see note below GBE_LINK100 7 Ethernet controller 0 100Mbit sec link indicator active low O 2 5VSB PU 1k 3 3V Not Supported Internally connected to GBE_ACT GBEO_LINK100 is a bootstrap signal see note below GBE_LINK1000 8 Ethernet controller 0 1000Mbit sec link indicator active low O 2 5VSB PU 4k99 Not Supported Internally connected to GBE_LINK GBEO_LINK1000 is a bootstrap signal see note below GBE ACT 14 Ethernet controller 0 activity indicator active low O 2 5VSB PD 1k 3 3V GBEO ACT is a bootstrap signal see note below Caution The signals listed in the table above are used as chipset configuration straps during system reset In this condition during reset they are inputs that are pulled to the correct state by either Qseven internally implemented resistors or chipset internally implemented

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