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User Guide PC3-ALLEGRO • CompactPCI® PlusIO CPU Card

1. dee 35 Installing the Board pied dope pe ee op Re e Pe ORO ed 36 Removing the Board aea dau ax war de EE EA x Balal Ba Sal a 37 EMC Recommendations ka 38 Replacement of the Battery assu xxx xxx x E XX AX s 39 Technical Reference sca qux asd SETA qp d A ua 40 O EKF 2 ekf com User Guide 9 PC3 ALLEGRO e CompactPCI PluslO CPU Board e Intel i7 3xxx Processor Local PELDEVICES Em 40 Local SMB DEVICES 624645634445 dq aud diaria ERE Pw Ed Rd 41 Hardware Monitor LMS7 68 6996 4 9 44 8 66 86 64 94 8 8 4 6 9 6 8 6446669096 AN AA A 41 Board Control and Status Register 42 Write Read Control Poet A e e cere Ee Ee E EE ses 42 Read Clear Status Register O a eed eee eeu 43 Redd Clear Status Register naa ao Geek ra aa 44 Read PLD Revision Register lt 42504 a en Ee ae Aa OE Ra 44 GPIO spa e er rie rabo 45 GPIO Usage QNI 2 PEH O E ds 45 Configuration 22a nd eh hy e Ad saa 47 Configuration PCI Express Switch 05 ea em d en emn 47 Loading UEFI BIOS Setup Defaults P GP 48 Manufacturer Mode Jumper P MFG 48 te a na ep sospes eq usnu qat qp o 49 CONVO a M 50 Front Panel COnnectals oec coua steisst 44524552 24045455 P GE ad 50 Disp
2. TU ns O PC3 ALLEGRO EKF ekf com OYDATIV Dd N 2 5 D m e e o o Olsn d BDdPEdWOD DAD UJO2 IN lt EKF 13 ekf com User Guide e PC3 ALLEGRO 7 CompactPCI PluslO CPU Board e Intel i7 3xxx Processor Front Panel Connectors ETH1 2 mDP1 2 12 VGA Dual Gigabit Ethernet RJ 45 receptacles with integrated indicator LEDs Mini DisplayPort digital video output receptacle VGA connector available as alternate Universal Serial Bus 3 0 type A receptacles VGA analog video output connector Mini DisplayPort connectors available as alternate Front Panel Switches amp Indicators EB FPH GP HD PG RST EKF LED indicating Backplane Ethernet activity Front Panel Handle with integrated switch programmable function power event button by default General Purpose bicolour LED LED indicating any activity on SATA ports Power Good Board Healthy bicolour LED System Reset Button Option ekf com User Guide e PC3 ALLEGRO e CompactPCI PluslO CPU Board e Intel i7 3xxx Processor On Board Connectors amp Sockets J EXPT Utility EXPansion Interface Connector LPC USB HD Audio SMBus available either J EXPB from top T or bottom B of the board interface to optional side board J HSE High Speed Expansion Connector 4 x SATA 4 x USB interface to optional low profile mezzanine module or side board J PCIE PCI Exp
3. EKF 65 ekf com User Guide e PC3 ALLEGRO CompactPCI PluslO CPU Board e Intel i7 3xxx Processor 5 E yum PC3 ALLEGRO w PCL CAPELLA Side Card 8HP Assembly d 3 Min Uu Wm mm iui Mir Up PC3 ALLEGRO w PCL CAPELLA Side Card 8HP Assembly ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board e Intel 7 3xxx Processor Pin Headers amp Debug Front Panel Handle Microswitch Header P FPH The jumper P FPH is used for attachment of an external SPDT switch By default P FPH is connected across a short cable harness to a microswitch which is integrated into the PC3 ALLEGRO front panel handle ejector lever The switch performs a power button event e g system shutdown by short circuiting the pins 1 and 3 of P FPH when activated hold unlock button of front panel handle depressed momentarily 1 black Microswitch Pole Common Wired to PLD red Microswitch Throw F P Handle Locked Position NC 3 yellow Microswitch Throw F P Handle Unlocked Position Wired to GND PLD Programming Header P ISP The PC3 ALLEGRO is provided with a powerful PLD in System Programmable Logic Device which replaces legacy glue logic The programming header P ISP is not stuffed in use for manufacturing only Its footprint is situated at the bottom side of the board 1 SV 2 TDO 3 TDI 4 NC 5 KEY 6 TMS GND 8 TCK EKF 67 ekf com User Guide PC3 ALLEGRO Compact
4. 4 User Guide PC3 ALLEGRO CompactPCI PlusIO CPU Card Intel Core i7 3xxx Processor Quad Core Ivy Bridge Document No 7106 Edition 24 3 September 2015 User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel 7 3xxx Processor Contents Abu this Manual uru usu Suyu as LIT ROT LOO LOT LOL LOU LOL LOU TIL to a 4 RENE EE ETT TT TT TT 4 Related DOCUMENTS bg oh ee aiaa ana Ee mi ai Os 2h 2 na e a 5 ps varo Su ee ee abs ee 5 D CE CD hee 1 a TNNT 5 Legal Disclaimer Liability EXCUSI N e cick E EE ai 4 ned 5 copo Pee TC IMP 6 Roc 11 7 TeehiicalFeat res ok ded oh en Ba BE wba E 9 Feature SUMMA arara ra b Eder Euge 9 Performance Rating dogs 11 Operating Cada raras Ru DEC e REDI I ay Ry ad SVP DER Td 11 Power ch coc MC crm 11 A cb aude or do ulus di ag bal os awa dic oa us 12 Top View Component Assembly 13 PROM Panel EISEN u a saa saw b ss a saqsa kas saa sao s aaa yad 14 Front Panel Switches S Indicators _ 14 On Board Connectors amp SOCKETS u a
5. 245 092 07 Intel SpeedStep Frequence Modes LFM Low Frequency Mode HFM High Frequency Mode 2 Add 200 600mA link only active 9 1 Gbps per Ethernet Port For Intel Celeron 1047UE there is no Turbo Mode at all and no low Frequency Mode at workload O EKF 11 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel 7 3xxx Processor Block Diagram 2 Simplified Block Diagram gt Ge PC3 ALLEGRO G m PCle Gen3 PICMG CompactPCI PluslO 6 DDR3 1333 1600 Ivy Bridge ECC 1 8112 32 un Dual Channel CPU Card Y d mes E Embedded Mobile G miel CPU i EKF m 2 4 Core PCle Gen3 m ekf com O x 2014 07 O a Ta configured to SATA 3G bv default Front DMI2 ding t Panel FDI 4x5GT s Ga 890 0 specification a USB3 L L 2 PCle PCle Gen2 Gen2 8608 Ad a DP1 O E QM77 Front Panel Stuffing Alternates either Mini DisplayPort or VGA VGA USB2 l Mobile 5 gess ezzanine BRA USB2 Side Card 4 1 0 PCH DP3 S LPC Audio SMB GPIO Panther PCI PCI GbE GbE 82579 e Point 1 LM 2 SATA 6G 3G 2 2 GbE GbE PCle PCle Gen2 Intel Chief River Platform Backplane CompactPCI PlusIO ekf com 12 EKF User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board e Intel 7 3xxx Processor Top View Component Assembly
6. 100Base TX Fast Ethernet and 10Base T Classic Ethernet capability gt Half or full duplex operation gt IEEE 802 3u 802 3ab Auto Negotiation for the fastest available connection gt Jumperless configuration complete software configurable Two bicoloured LEDs integrated into the dedicated RJ 45 connector in the front panel are used to signal the LAN link the LAN connection speed and activity status A further bicoloured LED in front panel labelled EB displays the state of the backplane network ports Each device is connected by a single PCI Express lane to the PCH Their MAC addresses unique hardware number are stored in dedicated FLASH EEPROM components The Intel Ethernet software and drivers for the 82579 and 82574 is available from Intel s World Wide Web site for download When managing the board by Intel Active Management Technology iAMT the dedicated network port to do so is accessible by the RJ45 connector GbE1 the upper port within the front panel EKF 19 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel i7 3xxx Processor Serial ATA Interface SATA The PC3 ALLEGRO provides a total of eight serial ATA SATA ports derived from two independent SATA controllers Two of these ports support data transfer rates of 6Gbps 600MB s while all ports are capable to work with 3Gbps 300MB s or 1 5Gbps 150MB s The SATA controller that is located within the QM77 Platform Controller Hub h
7. 5V 1 5A max 2 USB D c USB 3 0 3 USB D ceo U lt 4 GND S e 5 SS RX EE Q 6 SS RX 7 GND 8 ESE 9 SEGESCE D 5V via 1 5A current limited electronic power switch Power rail may be switched off by software independently for each port Another two USB 3 0 connectors would be available when the PC3 ALLEGRO is combined with the PCS BALLET mezzanine side card PC3 ALLEGRO w PCS BALLET Mezzanine Side Card 8HP O EKF 56 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board e Intel 7 3xxx Processor Ethernet Connectors Gigabit Ethernet Ports 1 2 J ETH RJ 45 1 NC1_MDX0 NC1 MDXO NC1_MDX1 NC1_MDX2 Port 1 NC1 MDX2 NCI MDXI S fen e W NC1_MDX3 00 NCI MDX3 NC2_MDXO NC2_MDXO NC2_MDX1 270 02 08 5 NC2 MDX2 Port NC2 MDX2 NC2 MDX1 NC2 MDX3 69 Jey oe W NC2 MDX3 The lower green LED indicates LINK established when continuously on and data transfer activity when blinking If the lower green LED is permanently off no LINK is established The upper green yellow dual LED signals the link speed 1Gbit s when lit yellow 100Mbit s when lit green and 10Mbit s when off O EKF 57 ekf com User Guide PC3 ALLEGRO CompactPCI PlusiO CPU Board Intel i7 3xxx Processor Mezzanine Connectors EKF Mezzanine Side Card Connector Suite 58 D 68 ny x q ekf com User
8. AD4 AD15 IPMB SCL gt GND FRAME AD17 AD29 GND BRSVP1B5 GND INTB 7 5V ay This pin is pulled up with 1kQ to V I O This pin is not used on PC3 ALLEGRO but pulled up with 1kO to V I O This pin is pulled up with 3 0k to J1 pin A4 This pin is not connected This pin is connected to a decoupling capacitor only and not used on PC3 ALLEGRO This pin is connected to power sequencing logic and should pulled low for normal operation This pin can be pulled down on PC3 ALLEGRO to force 33 MHz operation on request The PC3 ALLEGRO is capable to operate with 66 MHz on the CPCI Bus by default EKF ENUM AD3 3 3V AD8 V VO AD14 3 3V IPMB SDA IRDY 7 KEY AREA AD16 3 3V AD23 V I O AD28 3 3V RST V I O INTC TMs TRST 69 3 3V ADO 5V AD6 GND M66EN AD11 GND PAR GND STOPZ 80 5 1 9 GND AD20 GND AD25 GND CLK GND INTP 5V TDO 12V 5V ACK64 AD2 AD5 8 0 AD10 AD13 8 1 PERR LOCK TRDYZ 8 2 AD19 AD22 AD24 AD27 AD31 GNT INTS INTD TDI DV ekt com User Guide e PC3 ALLEGRO 7 CompactPCI PluslO CPU Board e Intel i7 3xxx Processor CompactPCI J2 PluslO This connector is a high speed UHM connector suitable for Gigabit Serial I O Refer also to PICMG 2 30 CompactPCI amp PluslO Specification 21 20 13 10
9. RAID Configuration Level 0 1 10 9 ekf com User Guide 9 PC3 ALLEGRO 7 CompactPCI PluslO CPU Board 7 Intel i7 3xxx Processor Feature Summary gt USB 3 0 XHCI SuperSpeed amp USB 2 0 EHCI Support 2 x USB 3 0 F P Connectors 6 x USB 2 0 to Mezzanine Connectors 4 x USB 2 0 to J2 Backplane 4 Gigabit Ethernet Controllers 2 x GbE F P RJ 45 Jacks 4 2 x GbE Backplane Connector J2 4 PCI Express Based Design for Component Interconnect 4 PCI Express for System Expansion by Mezzanine and Backplane or RIO 4 4 x PCI Express Gen2 Lanes to CPCI PluslO Backplane J2 Connector 4 x PCI Express Gen2 Lanes to Mezzanine Connector Set of Mezzanine Connectors for Storage Module or Side Card gt Legacy I O Mezzanine Expansion Connector EXP USB HD Audio LPC gt High Speed I O Mezzanine Expansion Connector HSE 4 x SATA 4 x USB gt PCI Express Mezzanine Expansion Connector PCIE 4 Lanes gt Third Display Mezzanine Expansion Connector DP gt Variety of Mezzanine Expansion Boards Side Cards Available gt Most Mezzanines Optionally Equipped with 2 5 Inch Single or Dual Drive 4 Low Profile Storage Modules Maintain 4HP F P Width 4 Side Cards with Additional Front Panel I O Connectors 3HP amp 12HP Assembly 4 Phoenix UEFI Unified Extensible Firmware Interface with CSM 4 Fully Customizable by EKF 4 Secure Boot on Reguest Windows Linux and other RT OS Supported CSM Compatibility Sup
10. SDVO DisplavPort Expansion Header J SDVO J SDVO GND 1 2 GND SDVO_RED DP_LANEO 3 4 SDVO_CLK DP_LANE3 SDVO_RED DP_LANEO 5 6 SDVO_CLK DP_LANE3 A GND 7 8 GND DVO GREEN DP LANE1 9 10 SDVO INT DP AUX Re l SDVO GREEN DP LANET 11 12 SDVO INT DP AUX i GND ie a GND SDVO BLUE DP LANE2 15 16 SDVO CTR CLK DP HPD SDVO BLUE DP LANE2 17 18 SDVO CTR DATA DP CFG1 GND ie GND To use J SDVO as either an SDVO or a further DisplayPort interface some of the control lines are configurable by a multiplexer The state of this multiplexer is controlled by PCH QM77 GPIO16 and adjustable by BIOS Setting GPIO16 to LO configures the connector J SDVO to work in SDVO mode In this case pins 10 12 carry the SDVO_INT and pins 16 18 the SDVO_CTR function This option was removed with BIOS 126 With GPIO16 set to HIGH the connector behaves like a DisplayPort interface The pins 10 12 function as DP_AUX while pin 16 and 18 are connected to DP HPD and DP CFG1 respectively EKF 63 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board Intel 7 3xxx Processor PC3 ALLEGRO w PCS BALLET amp Half Slim SATA SSD 8HP PC3 ALLEGRO w PCS BALLET amp C41 CFAST 8HP O EKF 64 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board Intel 7 3xxx Processor ms Ju HIHI e Typical 8HP Assembly w PCS BALLET Side Card amp C42 SATA 50 itii i f
11. Connector J HSE High Speed Expansion J HSE si ekf com 275 90 08 068 01 EKF s9 2 81 51 510 8mm 1 00mm Pitch High Speed Female Connector H s18 a25 b25 GND SATA HSE1 TXP SATA HSE1 TXN gt GND SATA HSE1 RXN SATA 5 1 RXP gt GND SATA HSE2 TXP gt SATA HSE2 TXN gt GND SATA HSE2 RXN 9 SATA HSE2 RXP GND USB 5 1 P USB 5 1 GND USB HSE2 P USB HSE2 N GND USB HSE 1 USB HSE 2 3 3VS 3 3VS 3 3VA 7 12V Power rail switched on in state SO only Switched Power rail on with system stand by power Always Power rail switch off in state S5 This SATA channel is capable to perform up to 6Gbps All TX RX designations with respect to the SATA controller a13 814 815 816 817 818 819 820 821 822 823 824 825 b13 b14 b15 b16 b17 b18 b19 b20 b22 b23 b24 b25 GND SATA HSE3 2275 SATASHSESSIXNE 7 GND SATA HSE3 RXN SATASLISESSRXP 09 GND SATA HSE4 TXP SATA 5 4 TXN gt GND SATA HSE4 RXN SATA HSEA RXP GND USB HSE3 P USB HSE3 N GND USB 5 4 P USB HSE4 N GND USB HSE OC34 USB HSE 34 5VS 5VS 5VA 2 350123 WARNING The 4 3 3V 5V 12V power pins are not protected against a short circuit event The connector J HSE therefore should be used only for attachment of an approved expansion side card The maximum current flow through these power pins
12. EKF CFast Specification Rev 1 0 CompactPCI Specification PICMG 2 0 R3 0 Oct 1 1999 CompactPCI PluslO Specification PICMG 2 30 81 0 November 11 2009 CompactPCI Serial Specification PICMG CPCI S 0 81 0 March 2 2011 VESA DisplayPort Standard Version 1 1a January 11 2008 VESA Mini DisplayPort Connector Standard Version 1 October 26 2009 Digital Visual Interface Rev 1 0 Digital Display Working Group IEEE Std 802 3 2000 Edition Low Pin Count Interface Specification Revision 1 1 High Definition Audio Specification Rev 1 0 PCI Express Base Specification 3 0 Serial ATA 2 5 2 6 Specification Serial ATA 3 0 amp 3 1 Specification Unified Extensible Firmware Interface UEFI Specification Version 2 5 ACPI Specification Version 6 0 Universal Serial Bus 3 0 Specification Revision 1 0 November 12 2008 www compactflash org www picmg org www picmg org www picmg org WWW Vesa Oorg www ddwg org standards ieee org developer intel com design chipsets industry Ipc htm www intel com design chipsets hdaudio htm www pclsig com www sata lo org www uefi org www usb org ekf com User Guide 9 PC3 ALLEGRO e CompactPCI PluslO CPU Board e Intel i7 3xxx Processor Overview The PC3 ALLEGRO is a rich featured high performance 4HP 3U CompactPCI Plus O CPU board equipped with a 3 Generation Intel Core 7 lw Bridge ECC dual or quad core mobile processor based
13. GPIO 55 GPIO 56 GPIO 57 GPIO 58 GPIO 59 GPIO 60 GPIO 61 62 GPIO 63 GPIO 64 67 GPIO65 GPIO 66 GPIO 67 GPIO68 71 GPIO 72 GPIO 73 GPIO 74 75 EKF GE S SN 3 3V SV SENI 22 7 3 3V E 3 3V 3 3V S SN 3 3V EVI 3 3V SI S VI 3 3V 3 3V 3 3V EI SEI 3 3V 3 3V SV 3 3V SEVA N A 3 3V 3 3V 3 3V GPIO Usage QM77 PCH GAO A A a CPCI_SMB_EN SGPIO_LOAD SGPIO OUT USB 1 ENABLE NC3 ENABLE NC4 USB 4 CLKOE 4 2 CLKOE 3J2 CH PCI CLKBUF EN ENABLE NC2 CPCI INTS USB 0 N A HWREV CLK 14 EXP HWREV HWREV N A NCI CLKREQ f Connect SMBus on CPCI to local SMBus LOW CPCI Backplane disconnected from SMBus HIGH CPCI Backplane connected to SMBus Not used pulled to GND Serial GPIO Bus LOAD Backplane J2 Serial GPIO Bus DATAOUT Backplane J2 USB Front Panel Right Port Overcurrent Detect Enable Ethernet Controller NC3 Enable Ethernet Controller NC4 USB J HSE Port 1 Overcurrent Detect Not used pulled to GND J2 PCle4 clk enable pulled to 4 V3 3A Not used pulled to GND J2 PCle3 clk enable pulled to 4 V3 3A Not used pulled to GND Not used pulled to V3 3S Enable CompactPCI Clock Buffer Not used pulled to V3 3S Enable Ethernet Controller NC2 Not used pulled to GND LOW Isolate SERIRQ from CPCI INTS HIGH Connect SERIRQ to CPCI INTS Not used pulled
14. Guide PC3 ALLEGRO CompactPCI PluslO CPU Board e Intel 7 3xxx Processor Expansion Interface J EXP J EXPT J EXPB optinal GND 1 2 3 3V PCI CLK 33MHz 3 4 RST PLCZ LPC ADO 5 6 AD1 LPC AD2 7 8 LPC AD3 FRMZ 9 10 DRQ GND 11 12 3 3V E LPC SERIRQ 13 14 WAKE EXP_SMI 15 16 SIO_CLK 14 3MHz FWH_IDO 17 18 FWH KBRST 19 20 A20GATE GND 21 22 5V 7 USB EXP2 23 24 USB EXP1 USB EXP2 25 26 USB EXP1 4 40 USB EXP 27 28 DBRESETZ 1 27mm sodel DP sel 2 29 30 EXP SDA GND 31 32 5V 7 HDA SDOUT 33 34 HDA SDIN0 HDA RSTZCL RSTZ 35 36 HDA SYNC HDA CLK CL CLK 37 38 HDA SDIN1 CL DATA SPEAKER 39 40 12V Power rail switched on in state SO only Connected to SMBus via buffered switch isolated after reset Stuffing option default is the HDA option Power rail switch off in state S5 The expansion interface header footprint is available on both sides of the board top J EXPT and bottom J EXPB The bottom side connector is stuffed only on customers request WARNING The 3 3V 5V 12V power pins are not protected against a short circuit event The connector J EXP therefore should be used only for attachment of an approved expansion side card The maximum current flow across these pins should be limited to 1A per power pin O EKF 59 ekf com User Guide e PC3 ALLEGRO e CompactPCI PluslO CPU Board 7 Intel i7 3xxx Processor High Speed Expansion
15. Integrated Graphics Device 0 20 0 0x8086 Ox1E31 USB xHCI Controller 0 22 0 048086 Ox1E3A Intel ME Interface Z1 0 22 1 0x8086 0x1E3B Intel ME Interface 2 0 22 2 0x8086 0x1E3C Intel ME IDE Redirection 0 22 0x8086 0x1E3D Intel ME Keyboard Text Redirection 0 25 0 0x8086 0x1502 PCH Gigabit LAN NC1 82579LM 0 26 0 0x8086 0x1E2D USB EHCI Controller 2 0 27 0 0x8086 Ox1E20 Intel High Definition Audio Controller 0 28 0 7 0x8086 0x2448 PCH PCI Express Port 1 8 0 29 0 0x8086 Ox1E26 USB EHCI Controller Z1 0 31 0 0x8086 Ox1E55 LPC Bridge 0 ET 2 0x8086 Ox1E01 SATA Non AHCI RAID Ports 0 3 0x1E03 SATA AHCI Mode 0x282A SATA Intel Rapid Storage Tech RAID Mode Ox1E07 SATA RAID Mode Capable 0 31 3 0x8086 Ox1E22 SMBus Controller 0 31 5 0x8086 Ox1E09 SATA Non AHCI RAID Ports 4 5 0 31 6 0x8086 Ox1E24 Thermal Controller 1 00 0 0x10B5 0x8614 PCle Switch Root Port PEX8608 ne 01 05 07 09 0 0x10B5 0x8614 PCle Switch Downstream Ports PEX8608 7 gt 0 0 0x1B4B 0x9230 Marvell 9230 SATA Controller 102 00 0 0x8086 041023 Ethernet Controller NC2 8257411 112 00 0 0x8086 0x10D3 Ethernet Controller NC 82574IT 122 00 0 0x8086 0x10D3 Ethernet Controller NC4 82574IT 1 Depends on BIOS settings 2 Bus number can vary depending on the PCI enumeration schema implemented in BIOS EKF 40 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel i7 3xxx Processor Local SMB Devices The PC3 ALLEGRO contains devices that a
16. edition Text 7106 File pc3 ug wpd Error corrected on pg 44 upper and lower table Reworked section Watchdog Power Requirements updated Reworked sections Serial ATA Interface and High Speed Expansion Connector J HSE Modified block diagram RIO SATA configured to 3G by default Table Feature Summary updated Table Power Requirements updated Table CompactPCI J2 updated Added list of local pci devices SDVO option removed on J SDVO Added photos PC3 w PCL Side Card Assembly Added photo PC3 w PCL Side Card Assembly Exploded View Added Board Control and Status Registers updated links Added note on operation in systems with a 64 bit CompactPCI backplane Added additional function of HD LED Added Power Requirements Clarified resetting of UEFI BIOS settings to factory defaults Universal V I O on CPCI Interface Added power requirements Updated description of BCSR Status Registers 0 and 1 Cleaned up section Watchdog Added photos PC3 ALLEGRO with CA7 MSATA amp C48 M2 Updated LM87 Information Table Feature Summary BIOS replaced by Firmware UEFI Table Reference Documents UEFI amp ACPI specifications Removed redundant Operating Conditions mib gn mib mib mib mib gn mib mib gn 2013 09 09 2013 09 25 2013 12 06 2 01 3 1 2 111 2014 01 10 15 January 2014 17 February 2014 3 April 2014 20 June 2014 21 July 2014 31 July 2014 11 August 2014 21 August 2014 4 September 2014 18 Septe
17. is pulled up with 1kQ to V O Alternate pull up resistor values e g 2 7kQ for V I O 3 3V are available on request This pin is not connected This pin is pulled up with 10kO to 3 3V Pin positions printed italic 64 bit system slot signals for reference only Pin positions printed blue PluslO options As an exclusive stuffing option J2 C15 can be utilised as PSON7 output 70 ekf com un Val O o e Pus A e ES TO fus 45 e sa A S x O Un e me 9 Q S U aa LLI Y Lef b OLOLTZSOOSZ 383 b a lm m m mmi jim a Ej fe JoOl2auuoD DJIWA pJeH zf uo pe LOOLSZSOOSZ 11 ba d m mimm 10128UU0 31119 DIEH f Top J2 UHM J1 Bottom ekf com EAR EKF ke el Val bb e a n s e TO e aa a U pus Lo e O gt el S U LJ lt m U a Oo Ou 70 5 UM a Val 222 n iya yaya e ayan eag an aya i ie EEA Ta nur PC3 ALLEGRO Shown w Dual M 2 SATA SSD ekf com 72 EKF User Guide PC3 ALLEGRO CompactPCI Serial CPU Board Intel amp i7 3xxx Processor Industrial Computers Made in Germany boards
18. on 22nm technology The PC3 ALLEGRO front panel is provided with two Gigabit Ethernet jacks two USB 3 0 receptacles and two Mini DisplayPort connectors for attachment of high resolution digital displays configured e g as extended desktop option VGA CompactPCI amp PluslO PICMG 2 30 is a new standard for rear I O across J2 specified by the PICMG High speed signal lines PCI Express SATA Gigabit Ethernet and USB are passed from the PC3 ALLEGRO through the special UHM connector to the backplane for usage either on a PluslO rear transition module or CompactPCI6 Serial card slots The PC3 ALLEGRO is equipped with a set of local expansion interface connectors which can be optionally used to attach a mezzanine side board A variety of expansion cards is available e g providing legacy I O and additional PCI Express based I O controllers such as SATA USB 3 0 and Gigabit Ethernet or a third video output Most mezzanine side cards can accommodate in addition a 2 5 inch drive EKF The PC3 ALLEGRO is equipped with up to 16GB RAM with ECC support 8GB memory down are provided for rugged applications and another 8GB are available via the DDR3 ECC SO DIMM socket The PC3 ALLEGRO backplane connectors comply with the PICMG CompactPCI PluslO system slot specification suitable for a rear VO module or hybrid CompactPCI Serial Systems Several low profile mezzanine modules are available as mass storage s
19. previously described the green part of this LED may change its function dependent on the state of the LED PG O EKF 26 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel i7 3xxx Processor EB Ethernet Backplane LED To monitor the link status and activity on both Ethernet ports attached to the backplane via the CompactPCI Serial connector P6 a single bicoloured LED is provided in the front panel The states are decoded as follows TEETH 2_ETH LED EB no link no link OFF link no link GREEN no link link YELLOW link link GREEN YELLOW Blinking of the LED EB in the appropriate colour means that there is activity on the port Hot Swap Detection The CompactPCI amp specification added the signal ENUM to the PCI bus to allow board hot swapping This signal is routed to a GPIO GPIO3 QM77 PCH An interrupt can be requested if ENUM changes caused by insertion or removal of a peripheral board Note that the PC3 ALLEGRO itself is not a hot swap device because it makes no sense to remove the system controller from a CompactPCI amp system However it is capable to recognize the hot swap of peripheral boards and to start software that is performing any necessary system reconfiguration Power Supply Status DEG FAL Power supply failures may be detected before the system crashes down by monitoring the signals DEG or FAL These active low lines are additions to the CompactPCI amp specification and may be d
20. systems solutions EKF Elektronik GmbH Philipp Reis Str 4 Haus 1 Phone 49 0 2381 6890 0 Fax 49 0 2381 6890 90 Internet www ekf com E Mail sales ekf com Lilienthalstr 2 Haus 2 59065 HAMM Germany
21. to be pressed preventing from being inadvertently activated The ejector within the front panel contains a micro switch that is used to generate a power button event This is done by pushing the red button of the ejector until the handle unlocks Immediately after that push up the ejector back to its original position the red button jumps up as well Animated GIF www ekf com c ccpu img reset 400 gif NOTE To prevent the board to cause a power button override the handle should be closed immediately after unlocking the front panel handle A power button override is triggered by opening the front panel handle for at least 4 seconds which results in bringing the board to power state S5 In case of entering this state unlock and lock the front panel handle a 2 time to reenter normal power state SO again See also section PG Power Good LED to see how the PC3 ALLEGRO indicates the different power states WARNING The PC3 ALLEGRO will enter the power state S5 if the front panel handle is not closed properly when the system powers up An open handle is signalled by a yellow blinking PG LED The manual reset push button and the power button functionality of the front panel handle could be passivated by BIOS settings An alternative and recommended way to generate a system reset is to activate the signal PRSTZ located on CompactPCI connector J2 pin C17 Pulling this signal to GND will have the same effect as to push the tactile reset swit
22. turned off The PC3 uses a BR2032 lithium battery soldered in the board giving an autonomy of more than 5 years Under normal conditions replacement should be superfluous during lifetime of the board In applications were the use of a battery is not permitted a SuperCap can be stuffed instead of the battery SPI Flash The BIOS and iAMT firmware is stored in flash devices with Serial Peripheral Interface SPI Up to 16MByte of BIOS code firmware and user data may be stored nonvolatile in these SPI Flashes The SPI Flash contents can be updated by a DOS or Linux based tool This program and the latest PC3 ALLEGRO BIOS binary are available from the EKF website Read carefully the enclosed instructions If the programming procedure fails e g caused by a power interruption the PC3 ALLEGRO may no more be operable In this case you would possibly have to send in the board because the Flash device is directly soldered to the PCB and cannot be changed by the user EKF 22 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board e Intel i7 3xxx Processor Reset The PC3 ALLEGRO is provided with several supervisor circuits to monitor supply rails like the CPU core voltage 1 5V 3 3V or 5V This circuitry is responsible also to generate a clean power on reset signal To force a manual board reset the PC3 ALLEGRO offers a small tactile switch within the front panel This push button is indent mounted and requires a tool e g a pen
23. PCI PlusIO backplane according to the PICMG 2 30 specification Hybrid backplanes allow the configuration of systems with CompactPCI Serial slots in addition to classic CompactPCI boards CompactPCI PluslO 8 CompactPCI Serial Hybrid Backplane CompactPCI 32 Bit Peripheral Slots CPCIS 0 Peripheral Slots Removable Power Supply EKF ekf com Sample Small Systems Hybrid Backplane Warning Do not operate the PC3 ALLEGRO in systems with a 64 bit CompactPCI backplane The J2 P2 pin assignments of a 64 bit CPCI backplane differ substantially from a CompactPCl PluslO backplane which may result in a short circuit situation For use with a 64 bit CompactPCI backplane special versions are available on request 32 bit operation is supported only The use of 64 bit CompactPCI peripheral boards may cause problems EKF 30 ekf com User Guide PC3 ALLEGRO CompactPCI PlusiO CPU Board Intel i7 3xxx Processor PCI GROOVE as System Controller in a Hybrid System Sample Hybrid CompactPCI amp CompactPC Serial Backplanes EKF 31 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board Intel 7 3xxx Processor aA 4 18 IN San EU CompactPCI amp PluslO Racks Available Sample Hybrid System Rack EKF 32 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board Intel 7 3xxx Processor As an alternate the PC3 ALLEGRO can be combined w
24. PCI PluslO CPU Board 7 Intel 7 3xxx Processor Processor Debug Header XDP1 The PC3 ALLEGRO may be equipped with a 26 position processor debug header for hard and software debugging specified by Intel amp as XDP SFF 26 Pin Platform Connection The connector is suitable for installation of a flat flex cable FFC in order to attach an JTAG debugger emulator such as the Arium ECM XDP3 An adapter ITP XDP SFF 26 is required in addition to convert the 26 pin XDP SFF 26 Pin connector to the standard 60 pin XDP The header XDP1 would be mounted on the PCB bottom side but is not stuffed by default XDP Processor Debug Connector 269 1 026 902 FFC Connector O EKF ekf com EKF 1 OBSFN AO PREQ OBSFN A PRDYZ 2 3 GND OBSDATA_AO 4 5 OBSDATA A1 GND 6 7 OBSDATA A2 OBSDATA A3 8 9 GND HOOKO CPU PWRGOOD 10 11 HOOK1 PWRBTN HOOK2 CFG O 12 13 HOOK3 SYS PWROK HOOKA BCLKP 14 HOOKS BCLKN VCCOBS AB 1 05V 16 17 HOOK6 PLTRST HOOK7 DBRESET 18 19 GND TDO 20 21 TRST TDI 22 25 TMS TCK1 24 25 GND TCKO TCK 26 ekf com User Guide e PC3 ALLEGRO 7 CompactPCI PlusIO CPU Board 7 Intel i7 3xxx Processor Backplane Connectors CompactPCI J1 25 5V 1 2 3 4 5 6 7 24 23 22 21 20 ADI 3 3V AD7 3 3V AD12 3 3V SERRA 3 3V DEVSEL 3M AD18 AD21 C BE3 AD26 AD30 REQ BRSVP1A5 IPMB PWR INTA TGK 5V CEE E 2 REQ64 2 5
25. QE Processor 2 1GHz 35W TDP Standard Voltage Quad Core 17 3555LE Processor 2 5GHz 25W TDP Low Voltage Dual Core 17 3517UE Processor 1 7GHz 17W TDP Ultra Low Voltage Dual Core 15 3610ME Processor 2 7GHz 35W TDP Standard Voltage Dual Core I3 3120ME Processor 2 4GHz 35W TDP Standard Voltage Dual Core 13 3217UE Processor 1 6GHz 17W TDP Ultra Low Voltage Dual Core Intel QM77 Panther Point Platform Controller Hub PCH Integrated HD Graphics Engine 3 Independent Displays Enhanced Media Processing Up to 3 Display Configuration Front Panel Dual mDP or Single VGA Connector Option Max Resolution 2560 x 1600 DisplayPort 1920 x 1200 VGA 3rd Display via Side Card PCS BALLET Integrated Memory Controller up to 16GB DDR3 ECC 1600 DDR3 ECC Soldered Memory up to 8GB DDR3 ECC SO DIMM Memory Module Socket up to 8GB SATA 6G amp 3G for Mass Storage 2 2 SATA Channels 6Gbps 3Gbps for Mezzanine Storage Modules Connector HSE CompactFlash Card with C40 SCFA Mezzanine Module Option 4HP Maintained CFast Card with C41 CFAST Mezzanine Module Option 4HP Profile Maintained SATA 1 8 Inch Solid State Drive with C42 SATA Mezzanine Card Option 4HP Maintained Dual mSATA Modules with C47 MSATA RAID Mezzanine Card Option 4HP Maintained 4 x SATA RAID Channels to UHM Connector J2 for RIO Module or CPCI Serial Backplane Usage limited to 3G SATA by CPCI PluslO Specification Hardware RAID Enabled by Marvell 88SE9230 ARM Powered Subsystem
26. ader P MFG is not stuffed on the PC3 ALLEGRO by default P MFG P MFG Jumper Removed Normal operation Jumper Installed Entering Manufacturer Mode This setting is the factory default O EKF 48 ekf com User Guide 9 PC3 ALLEGRO e CompactPCI PluslO CPU Board e Intel i7 3xxx Processor RTC Reset P RTC The jumper P RTC may be used to reset certain register bits of the battery backed RTC core within the PCH QM77 This can be necessary under rare conditions e g battery undervoltage if the CPU fails to enter the BIOS POST after power on Note that installing of jumper P RTC will neither set UEFI BIOS Setup to EKF Factory Defaults nor resets the time and date register values of the RTC Real Time Clock To reset the RTC core the board must be removed from the system rack Short circuit the pins of P RTC for about 1 sec Thereafter reinstall the board to the system and switch on the power It is important to accomplish the RTC reset while the board has no power The pin header P RTC is not stuffed on the PC3 ALLEGRO by default P RTC P RTC Jumper Removed Normal operation Jumper Installed RTC reset performed This setting is the factory default EKF 49 ekf com User Guide e PC3 ALLEGRO 7 CompactPCI PluslO CPU Board 7 Intel i7 3xxx Processor Connectors Caution Some of the internal connectors provide operating voltage 3 3V and 5V to devices inside the system chassis such as internal peripherals Not all o
27. age for direct soldering to the PCB i e the chip cannot be removed or changed by the user The processors supported by the PC3 ALLEGRO are running at core clock speeds up to 2 1GHz for quad core and to 2 5GHz on dual core devices Due to Enhanced Intel SpeedStep and Intel Turbo Boost Technology each core can decrease or increase its nominal operating frequency The clock speed is chosen depending on the power states of the processor cores graphics engine the currently required performance and the actual core temperature Power is applied across the CompactPC connectors 41 3 3V 5V The processor core voltage is generated by a switched voltage regulator sourced from the 5V plane The processor signals its required core voltage by 7 dedicated pins according to Intels IMVP 7 voltage regulator specification Intel amp Core Processors Supported Processor Physical Core Clock Cache Junction CPU ID Stepping SPEC Number Cores nom max 11 Temp Code i7 3612QE 2 1 3 1GHz 650MHz 105 C 306A9h SROND I5 2 2 5 3 2GHz 4MB 550MHz 105 C 25W 306A9h L 1 SROT5 2 3517 2 1 7 2 8GHz 4MB 350MHz 105 C 17W 306A9h Lei SROT6 i5 3610ME H 222112 3MB 650MHz 105 357 306A9h bi SROQK O EKF 16 ekf com User Guide e PC3 ALLEGRO 7 CompactPCI PluslO CPU Board e Intel i7 3xxx Processor Thermal Considerations In order to avoid malfunctioning of the PC3 ALLEGRO take care of appropriate cooling of the processor and system e
28. cable diameter 13 0mm Metal Shielding Conec Polytronic Ordering No Caps 59557 Lippstadt CDFA 09 165 X 13129 X DB9 CDSFA 15 165 X 12979 X DB15 CDSFA 25 165 X 12989 X DB25 O EKF 38 ekf com User Guide e PC3 ALLEGRO e CompactPCI PluslO CPU Board 7 Intel i7 3xxx Processor Replacement of the Battery When your system is turned off a battery maintains the voltage to run the time of day clock and to keep the values in the CMOS RAM The battery should last during the lifetime of the PC3 ALLEGRO For replacement the old battery must be desoldered and the new one soldered We suggest that you send back the board to EKF for battery replacement Warning Danger of explosion if the battery is incorrectly replaced or shorted Replace only with the same or equivalent type Do not expose a battery to fire O EKF 39 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board e Intel i7 3xxx Processor Technical Reference Local PCI Devices The following table shows the on board PCI devices and their location within the PCI configuration space Several devices are part of the processor and platform controller hub QM77 Vendor D 0x8086 0x0154 Processor Host Bridge DRAM Controller 0 1 0 0x8086 0x0151 Processor PCI Express Controller 0 1 1 0x8086 0x0155 Processor PCI Express Controller 0 1 2 0x8086 0x0159 Processor PCI Express Controller 0 6 0 0x8086 0x015D Processor PCI Express Controller 0 2 0 0x8086 0x0166 Processor
29. ch The healthy state of the PC3 ALLEGRO is indicated by the LED PG Power Good located in the front panel This bicoloured LED signals different states of the board see section below As soon as this LED begins to lite green all power voltages are within their specifications and the reset signal has been deasserted O EKF 23 ekf com User Guide e PC3 ALLEGRO e CompactPCI PluslO CPU Board e Intel i7 3xxx Processor EKF e ekf com O EKF 24 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel 7 3xxx Processor Watchdog An important reliability feature is a software programmable watchdog function The PC3 ALLEGRO contains two of these watchdogs One is part of the QM77 PCH and also known as TCO Watchdog A detailed description is given in the QM77 data sheet Operating systems like Linux offer a driver interface to the TCO watchdog The behaviour of the 2 watchdog is defined within a PLD of the PC3 which activates deactivates the watchdog and controls its time out period The time out delay is adjustable in the steps 2 10 50 and 255 seconds After alerting the WD and programming the time out value the related software e g application program must trigger the watchdog periodically For details on programming the watchdog see section Board Control and Status Register BCSR This watchdog is in a passive state after a system reset There is no need to trigger it at boot time The watch
30. ched on in SO state only Most DisplayPort monitors come with the standard DP connector hence requiring a mDP to DP cable assembly for use with the PC3 ALLEGRO For attachment of either a classic style analog RGB monitor DVI or HDMI type display to the J DP receptacles there are both adapters and also adapter cables available EKF 51 ekf com User Guide 9 PC3 ALLEGRO e CompactPCI PluslO CPU Board e Intel i7 3xxx Processor Specified by the VESA DisplayPort connector standard is a dedicated power pin 20 3 3V 0 54 Both the GPU source side and a DP monitor sink side must provide power via this pin A VESA specified standard DisplayPort cable however must not connect the pins 20 of both cable ends in order to avoid a back driving conflict Unfortunately there are cable assemblies available with pin 20 passed through with unpredictable results on the system behaviour Before ordering DP cable assemblies verify the associated wiring diagram Sample VESA Compliant Mini DisplayPort Cable Assemblies 2 0m Mini DisplayPort mDP DisplayPort DP plug plug cable assembly VESA compliant EKF Part 270 66 2 02 0 Astron T2M2M20020 R Molex 0687850003 Roline 1045636 Wieson 9858 Option Screw Locked mDP Connectors EKF 52 ekf com User Guide PC3 ALLEGRO CompactPCI PlusiO CPU Board Intel i7 3xxx Processor A third DisplayPort video output is available when combining the PC3 ALLEGRO with the m
31. ci ac tasti ate ss S its hes A b quas a 15 PING ENEE 15 iD eem Crece 15 1 1 ta sta AA as sip a supi 16 Thermal Considerations EEN 17 Main Memo qui d oed decur ra dod ce 9 18 Graphics SUBSYSTEM s D 19 EE 19 Serial ATA Interface SATA L 20 POE Besse SHAG RNC 20 Universal Serial Bus USB aiiis wid exe ead 8 4 5 9 ehh 9 0 u ne 21 A dag he aan TA 21 Real Time Clock r i besi 22 111 ear dba ia ota tii 22 RESOU a C EN 23 Wale EE 25 enti tava bees heda haga bid jig rag 25 FGdrover Good EBD lt uus ataca uu sa susan Dawa aA aaa Sta 26 GP General Purpose EBD a RE REP RR REPRE RR A RAS 26 HD Hard Disk Attivi LED ai ai aurum icon qe e Su aa st sua dh a ll 26 EB Ethernet Backplane LED 4 iiiki OCER ORCI 27 Power Supply Status DEG FAL OE REOR RR oed 27 Mezzanine Side Board DDLIOrIS eg alan a d oe OR C o EO ER oe EC T o RR ku 28 CompactPCI PluslO P 30 Installing and Replacing Components o 35 Bee KOM Bie arara m hee AGG deny Ale
32. d high speed full speed and low speed are integrated into the QM77 PCH Utility Interfaces Besides the high speed mezzanine interface connectors J HSE and J PCIE the PC3 ALLEGRO is provided with the utility Interface expansion connector socket J EXP This connector comprises several interfaces which may be useful for system expansion on mezzanine cards as an option HD Audio LPC Low Pin Count SMBus 2 x USB Y Y Y The SMBus is controlled by the QM77 platform controller hub The SMBus signal lines on the J EXP utility expansion connector can be switched on off under software control PCH GPIO in order to isolate external components in case of an IC address conflict The HD Audio port requires an additional audio codec as provided e g on the PCS BALLET side card The LPC bus presents an easy way to add legacy interfaces to the system EKF offers a variety of mezzanine expansion boards side cards to be attached on top of the PC3 ALLEGRO featuring all classic Super I O functionality for example the PCS BALLET or the CCO CONCERT Access to the connectors PS 2 mouse keyboard COM USB and audio in out is given directly from the front panel O EKF 21 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel 7 3xxx Processor Real Time Clock The PC3 ALLEGRO has a time of day clock and 100 year calendar integrated into the QM77 PCH A battery on the board keeps the clock current when the computer is
33. d to J HSE which maintain the 4HP envelope for extremely compact systems Furthermore these small size modules may be combined with the full size expansion boards that means an assembly comprised of 3 PCBs O EKF 28 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board Intel i7 3xxx Processor PC3 ALLEGRO w PCL CAPELLA Side Card 8HP Assembly Related Documents Mezzanine Modules and Side Cards C40 C47 Series www ekf com c ccpu cAx mezz ovw pdf Mezzanine Storage Modules PCL CAPELLA Mezzanine Side Card www ekf com p pcl pcl html PCS BALLET Mezzanine Side Card www ekf com p pcs pcs html EKF 29 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel 7 3xxx Processor CompactPCI PluslO CompactPCI6 PluslO PICMG 2 30 isa standard for rear across J2 High speed signal lines PCI Express SATA Gigabit Ethernet and USB are passed from the PC3 ALLEGRO through the special UHM J2 connector to the backplane for usage either with a PluslO rear VO transition module or CompactPCI Serial card slots CompactPCI amp Serial PICMG CPCIS 0 defines a completely new card slot based on PCI Express SATA Gigabit Ethernet and USB serial data lines On a hybrid backplane both card styles can reside CompactPCl amp and CompactPCl Serial with the PC3 ALLEGRO in the middle as controller for both backplane segments The PC3 ALLEGRO can be used in any system with a Compact
34. dog is activated on the first trigger request If the duration between two trigger requests exceeds the programmed period the watchdog times out and a full system reset will be generated The watchdog remains in the active state until the next system reset There is no way to disable it once it has been put on alert whereas it is possible to reprogram its time out value at any time Front Panel LEDs The PC3 ALLEGRO is equipped with four LEDs which can be observed from the front panel Three of these LEDs are labelled according to their primary meaning but should be interpreted altogether for system diagnosis Status A GE cM Ur GREEN GREEN Sleep State S5 Soft Off OFF GREEN OFF Sleep State 4 Suspend to Disk Hibernate OFF OFF GREEN Sleep State S3 Suspend to RAM Standby GREEN RED BLINK X After Reset GREEN X X Board Healthy and in SO State YELLOW BLINK X X Front panel handle is unlocked RED X X Hardware Failure Power Fault RED BLINK X X Software Failure O EKF 25 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board e Intel i7 3xxx Processor PG Power Good LED The PC3 ALLEGRO offers a bicolour LED labelled PG located within the front panel After system reset this LED defaults to signal different power states Off Sleep state S3 S4 or S5 Green Healthy Yellow blink Front panel handle open Red steady Hardware failure Red blink Software failure Y Y Y Y To enter the PG LED state Software Failure th
35. e PC3 ALLEGRO enables mode TM2 which is the most efficient O EKF 17 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel 7 3xxx Processor Main Memory The PC3 ALLEGRO features two channels of DDR3 SDRAMs with support of ECC Error Correction Code One channel is realized with 18 memory devices soldered to the board Memory Down and delivers a capacity of up to 8GB with a clock frequency of 1600MHz PC3 12800 The 2nd channel provides a socket for installing a 204 pin ECC SODIMM module thus allowing a simple expansion of system memory max module height 1 25 inch Supported are unbuffered DDR3 ECC SODIMMs 72 bit with V 1 5V featuring on die termination ODT according the PC3 12800 specification Minimum module size is 512MB maximum module size is 8GB Please note that standard DDR3 SODIMMs without ECC feature do not work on PC3 ALLEGRO It is recommended to add a SODIMM module with same size as the Memory Down to get best performance some of the system memory is dedicated to the graphics controller This typically results in a size of 2x4GB of memory which is recommended to run the operating systems Windows Vista or Windows 7 The memory controller supports symmetric and asymmetric memory organization The maximum memory performance can be obtained by using the symmetric mode When in this mode the memory controller accesses the memory channels in an interleaved way Since Core i7 processors su
36. e bit PGLED in the board control register CTRLL REG must be set The PG LED remains in this red blinking state until this bit is cleared After that it falls back to its default function GP General Purpose LED This programmable bicolour LED can be observed from the PC3 ALLEGRO front panel The status of the red part within the LED is controlled by the GPIO18 of the PCH QM77 Setting GPIO18 to 1 will switch on the red LED Turning on or off the green LED is done by setting the bit GPLED in the board control register CTRLH REG The GP LED is not dedicated to any particular hardware or firmware function with exception of special power states of the LED PG as described above Nevertheless a red blinking GP LED is an indication that the BIOS code couldnt start While the CPU card is controlled by the BIOS firmware the GP LED is used to signal board status information during POST Power On Self Test After successful operating system boot the GP LED may be freely used by customer software For details please refer to www ekf com p pc3 firmware biosinfo txt HD Hard Disk Activity LED The PC3 ALLEGRO offers a bicoloured LED marked as HD placed within the front panel This LED when blinking green signals activity on any device attached to the SATA ports of the Intel QM77 Panther Point Platform Controller Hub PCH Blinking yellow signals activity on any device attached to the SATA ports of the Marvell 88SE9230 SATA RAID Controller As
37. em reset may be caused by a power failure of the CPU VCC SA voltage regulator 3 EPETOSIS O0 Normal operation 1 Last system reset may be caused by a power failure of the V1 05LAN voltage regulator 6801110552 0 Normal operation 1 Last system reset may be caused by a power failure of the V1 05S voltage regulator 1 PFVRG O0 Normal operation 1 Last system reset may be caused by a power failure of the CPU VCC_AXG voltage regulator O PFVRC O0 Normal operation 1 Last system reset may be caused by a power failure of the CPU VCC CPU voltage regulator The bits in this register are sticky i e their state will be kept even if a system reset occurs To clear the bits a write to the register with arbitrary data may be performed O EKF 43 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel 7 3xxx Processor Read Clear Status Register 1 Write SMBus Address OxB2 Read SMBus Address OxB3 Bit Description CMD 51411 7 RESERVED Always read as 0 6 WDGRST O0 Normal operation 1 Last system reset may be caused by a watchdog time out 5 WDGHT O0 Normal operation 1 The watchdog already has elapsed half of its time out period 4 PFI A 0 Normal operation 1 Power failure on the 12V voltage rail SEM EPEIISSS O0 Normal operation 1 Last system reset may be caused by a power failure of the V1 05S or V3 3S voltages 2 PFI33M 0 Normal operation 1 Last system reset may be caused by a
38. ess Gen 2 lanes 5GT s originating from the QM77 are available at the backplane connector J2 Another four PCI Express lanes are provided by the Intel Core i7 processor to the J PCIE connector A small DIP switch DS P located on the backside of the board are used to configure different lane widths to each of both downstream interfaces and to choose the interface transfer rate Possible settings are gt Single link x 4 lanes to J PCIE gt Four links x 1 lane to J PCIE gt 2 5GT s or 5GT s transfer speed See section Configuration PCI Express Switch DS P for details O EKF 20 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board e Intel 7 3xxx Processor Universal Serial Bus USB The PC3 ALLEGRO is provided with twelve USB ports All of them are USB 2 0 capable but two ports routed to front panel connectors are also supporting the USB 3 0 SuperSpeed standard The USB 2 0 interfaces are distributed to the front panel two ports two to the expansion board interface connectors J EXP four to the high speed expansion connector J HSE and four ports are available across the backplane connector J2 The front panel USB connectors can source a minimum of 1 5A 5V each over current protected by two electronic switches Protection for the USB ports on the expansion interfaces and on the J2 PluslO connector is located on expansion boards The USB xHCI and two EHCI controllers handling the USB port operation at SuperSpee
39. ezzanine side card PCS BALLET The standard DP connector is provided with latches which may be important for some applications PC3 ALLEGRO w PCS BALLET C32 FIO 12HP O EKF 53 ekf com User Guide PC3 ALLEGRO CompactPCI PlusiO CPU Board Intel i7 3xxx Processor ia PC3 ALLEGRO w PCS BALLET C32 FIO C20 SATA 12HP EKF 54 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board e Intel 7 3xxx Processor VGA Video Connector As an option the PC3 ALLEGRO can be equipped with a legacy VGA connector High Density D Sub 15 position female connector The connector VGA replaces the two Mini DisplayPort receptacles and the digital video interface therefore is not available concurrently with this option J VGA Option 1 RED 2 GREEN BLUE 4 NC 5 GND 6 6 GND 7 GND 8 GND 9 DDC POW 10 GND 11 NC 12 VGA DDC SDA 13 HSYNC 14 VSYNC 15 VGA DDC SCL 1 3 3V protected by a self resetting PolySwitch fuse 0 75A This voltage is switched on in SO state only O EKF 55 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel 7 3xxx Processor USB Connectors The Intel QM77 Platform Controller Hub incorporates a four port USB 3 0 xHCI host controller Two ports are directly available on the PC3 ALLEGRO front panel type A receptacle for attachment of external USB devices USB Dual USB 3 0 Receptacle USB 3 0 dual type A receptacle stacked 18 position 1 VBUS
40. f these connectors are short circuit protected Do not use these internal connectors for powering devices external to the computer chassis A fault in the load presented by the external devices could cause damage to the board the interconnecting cable and the external devices themselves Front Panel Connectors With respect to the video connector the PC3 ALLEGRO is available in two flavours either dual mDP or VGA EKF e draft do not scale ekf com PC3 ALLEGRO PC3 ALLEGRO Dual mDP VGA EKF 50 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel 7 3xxx Processor DisplayPort Connectors The Intel amp i7 processors used on PC3 ALLEGRO are equipped with an integrated graphics controller which supports DisplayPort and SDVO interfaces permitting simultaneous independent operation of up to three displays Two DP receptacles are available from the PC3 ALLEGRO front panel as mDP Mini DisplayPort connectors which is a space saving alternate to the standard DP connector and is also specified by the VESA Mini DisplayPort J DP1 2 20 PWR 19 GND 18 AUX CH N 17 LANE2 N 16 AUX CH P 15 LANE2 P O et e S 14 GND 13 GND gu 2 E 12 LANE3 N 11 LANE1 N A 10 LANE3 P 9 LANE1 P NO 8 GND 7 GND 6 CONFIG2 GND 5 LANEO N 4 CONFIG1 3 LANEO P 2 Hot Plug Detect 1 GND 1 3 3V protected by a self resetting PolySwitch fuse 0 7 This voltage is swit
41. g by a cooling fan suitable to the maximum power consumption of the CPU chip actually in use The processor contains digital thermal sensors DTS that are readable via special CPU registers DTS allows to get the temperatures of each CPU core separately Two further temperature sensors located in the system hardware monitor LM87 allows for acquisition of the boards surface temperature and the thermal state of the onboard system memory channel Beside this the LM87 also monitors most of the supply voltages A suitable software on Microsoft Windows systems to display both the temperatures as well as the supply voltages is Speedfan which can be downloaded from the web After installation both temperatures and voltages can be observed permanently from the Windows taskbar The PC3 ALLEGRO is equipped with a passive heatsink Its height takes into account the 4HP limitation in mounting space of a CompactPC board In addition a forced vertical airflow through the system enclosure e g bottom mount fan unit is strongly recommended 2 20m h or 2m s 400LFM around the CPU slot Be sure to thoroughly discuss your actual cooling needs with EKF Generally the faster the CPU speed the higher its power consumption For higher ambient temperatures consider increasing the forced airflow to 3m s 600LFM or more The table showing the supported processors above give also the maximum power consumption TDP Thermal Design Power of a particular proce
42. gs of DS P with different side boards mounted to the Side Board PCle Link Width J PCIE PC3 ALLEGRO None OFF OFF CCI RAP OFF OFF CCK ON OFF MARIMBA CCL CAPELLA ON OFF CCO CONCERT OFF ON PCS BALLET OFF OFF EKF 4 Links x 1 Lane 5GT s 4 Links x 1 Lane 5GT s 1 Link x 4 Lanes 5GT s 1 Link x 4 Lanes 5GT s 4 Links x 1 Lane 2 5GT s 4 Links x 1 Lane 5GT s 47 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board e Intel 7 3xxx Processor Loading UEFI BIOS Setup Defaults P GP The jumper P GP may be used to reset the UEFI BIOS configuration settings to a default state The UEFI BIOS on PC3 ALLEGRO stores most of its settings in an area within the BIOS flash e g the actual boot devices Using the jumper P GP is only necessary if it is not possible to enter the setup of the BIOS To reset the settings mount a jumper on P GP and perform a system reset As long as the jumper is stuffed the BIOS will use the default configuration values after any system reset To get normal operation again the jumper has to be removed Jumper Removed Normal operation Jumper Installed BIOS configuration reset performed This setting is the factory default Manufacturer Mode Jumper P MFG The jumper P MFG is used to bring the board into the manufacturer mode This is necessary only on board production time and should not used by customers For normal operation the jumper should be removed The pin he
43. ith a CompactPCI PluslO rear I O transition module such as the PR1 RIO which is provided with I O connectors on board and back panel for all high speed signals PRI RIO Rear I O Transition Module O EKF 33 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel i7 3xxx Processor Related Documents Mezzanine Modules and Side Cards CAK Series Mezzanine Storage Modules www ekf com c ccpu c4x mezz ovw pdf Mezzanine Modules Overview www ekf com c ccpu mezz ovw pdf The EKF Mezzanine Module Concept www ekf com c ccpu cpci mezzanine evolution pdf I F Type Controller LPC Low Pin Count CPU HD Audio CPU SMBus CPU buffered 2 KUSER RER I F Type Controller SATA1 3GI S SATA2 SATA3 PCH 6GT s 4 x USB 2 0 USB Hub I F Type PCI Express PE Switch Controller Related Documents CompactPCI Serial CompactPCI PluslO amp Serial Overview www ekf com s smart_solution pdf CompactPCI Serial Home www ekf com s serial html CompactPCI PluslO Home www ekf com p plus html O EKF 34 ekf com User Guide e PC3 ALLEGRO e CompactPCI PluslO CPU Board e Intel i7 3xxx Processor Installing and Replacing Components Before You Begin Warnings The procedures in this chapter assume familiarity with the general terminology associated with industrial electronics and with safety practices and regulatory compliance required for using and modifying electronic equipment Disconnect the sys
44. layPort CONMGCIONS 22224222 14 51 VGA Video Connector ia qua ca paa da tracce ba a Dario daa dr 55 US CONTEO FT PS 56 Ethernet COIIECIOIS cicer cane aa a wa Ride is 57 Mezzanine 8 17 1 16 9 2 x su s gu singh at d nidad A E AC en 58 Expansion Interface J EXP ivo e rx 59 High Speed Expansion Connector J HSE a secese ea aa 60 PCI Express Expansion Header J PCIE suas rcu kh rer n 62 SDVO DisplayPort Expansion Header J SDVO 63 DEDO lp 67 Front Panel Handle Microswitch Header P FPH 67 PLD Programming Header PJSP A s casa aaa anga aq a 67 Processor Debug Header XDP1 68 Backplane CONNECT EE ED HIE P RE 69 CompactPCI gares 45 4845 ARES GEAR MEAL EY dob d dod 69 Gormpacil ENER arg Tara ded opo CREER EE 70 EKF 3 ekf com User Guide e PC3 ALLEGRO e CompactPCI PluslO CPU Board e Intel i7 3xxx Processor About this Manual This manual describes the technical aspects of the PC3 ALLEGRO required for installation and system integration It is intended for the experienced user only Edition History fid Contents Changes SS E 2 22 25 24 EKF User Manual PC3 ALLEGRO english preliminary
45. m dme E EKF GA4 GA3 GA2 GA1 GAO CLK6 GND 2 ETH B 1 ETH D 1 ETH B RSV RSV RSV CLK5 GND 2 ETH B 1 ETH D 1 ETH B RSV GND RSV GND GND 2 ETH A 1 ETH C 1 ETH RSV RSV RSV 2 ETH D4 2 ETH 2 ETH A 1 ETH C 1 ETH A BRSVP2A18 BRSVP2B18 BRSVP2C18 GND BRSVP2E18 2 ETH D 2 ETH C PRST REQ6 GNT6 BRSVP2A17 GND 4 PE CLK 2 PE 1 DEG GND reserved BRSVP2A16 BRSVP2B16 BRSVP2E16 4 PE CLK 2 ale FAL REQS 7 GNT5 BRSVP2A15 GND PSON 9 3 PE CLK 1 PE ClK 4 PE CIKEZ SATA SCL reserved AD35 AD34 AD33 GND AD32 3 PE CLK 1 PE CIK 3 PE CLKE SATA SDO SATA SL AD38 GND V 1 O AD37 AD36 4 PE RXOO 1 PE CLKEZ 2 PE CLKE SATA SDI 4 SATA RX4 AD42 AD41 AD40 GND AD39 4 PE RXOQ 4 PE TX00 4 USB2 4 SATA TX 4 SATA RX AD45 GND 4044 4043 3_PE_RX00 4 PE TX00 4 USB2 4 SATA TX 3 SATA RX AD49 AD48 AD47 GND AD46 3 PE RXOQ 3 PE TX00 3 582 3 SATA TX 3 SATA 4052 GND V 1 O 4051 4050 2_PE_RX00 3 PE TXOD 3 USB2 3 SATA TX 2 SATA RX AD56 AD55 AD54 GND AD53 2 PE RXOQ 2 PE TX00 2 USB2 2 SATA TX 2 SATA RX AD59 GND 4058 4057 1 PE RX00 2 PE TX00 2 USB2 2 SATA TX 1 SATA RX AD63 AD62 AD61 GND AD60 1 PE RXOO 1 PE TX00 1 USB24 1 SATA TX 1 SATA RX C BE5 64EN C BE4 PAR64 1 PE TXOQ 1 USB2 1 SATA TX reserved BRSVP2B4 C BE7 GND C BE6 CLK4 GND GNT3 REQ4 GNT4 CLK2 CLK3 SYSEN GNT2 REQ3 CLK1 GND REQ1 GNT1 REQ2 This pin
46. mber 2014 12 December 2014 16 January 2015 27 January 2015 5 February 2015 7 April 2015 27 May 2015 28 May 2015 14 August 2015 3 September 2015 ekf com User Guide 9 PC3 ALLEGRO e CompactPCI PluslO CPU Board 7 Intel i7 3xxx Processor Related Documents Related Information PC3 ALLEGRO PC3 ALLEGRO Home www ekf com p pc3 pc3 html PC3 ALLEGRO Product Information www ekf com p pc3 pc3 pi pdf Nomenclature Signal names used herein with an attached designate active low lines Trade Marks Some terms used herein are property of their respective owners e g Chief River Ivy Bridge Panther Point Core i7 Intel CompactPCI CompactPCI PluslO CompactPCI Serial PICMG Windows XP Windows 7 Microsoft EKF ekf system amp EKF Y Y Y EKF does not claim this list to be complete Legal Disclaimer Liability Exclusion This manual has been edited as carefully as possible We apologize for any potential mistake Information provided herein is designated exclusively to the proficient user system integrator engineer EKF can accept no responsibility for any damage caused by the use of this manual O EKF 5 ekf com User Guide e PC3 ALLEGRO e CompactPCI PluslO CPU Board e Intel i7 3xxx Processor Standards Reference Documents CFast CompactPCI CompactPCI PluslO CompactPCI Serial DisplayPort DVI Ethernet LPC HD Audio PCI Express SATA UEFI USB
47. oard cabling assembly Activate the ejector lever Remove the card carefully be sure not to damage components mounted on the bottom side of the board by scratching neighboured front panels Store board in the original packaging do not touch any components hold the board at the front panel only Warning Do not expose the card to fire Battery cells and other components could explode A and cause personal injurv O EKF 37 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel 7 3xxx Processor EMC Recommendations C In order to comply with the CE regulations for EMC it is mandatory to observe the following rules The chassis or rack including other boards in use must comply entirely with CE Close all board slots not in use with a blind front panel Front panels must be fastened by built in screws Cover any unused front panel mounted connector with a shielding cap External communications cable assemblies must be shielded shield connected only at one end of the cable Use ferrite beads for cabling wherever appropriate Some connectors may require additional isolating parts Recommended Accessories Blind CPCI Front EKF Elektronik Widths currently available Panels HRSS OSMIM with handle 4HP 8HP without handle 2HP AHP 8HP 10HP 12HP Ferrit Bead Filters ARP Datacom Ordering No 63115 Dietzenbach 102 820 cable diameter 6 5mm 102 821 cable diameter 10 0mm 102 822
48. old two 6Gbps and two 3Gbps ports which are fed to the high speed expansion connector J HSE This connector allows the installation of low profile expansion boards like C41 CFAST or C42 SATA to attach the popular CFast cards or Micro SATA SSDs 1 8 inch respectively Another mezzanine is the C47 MSATA a carrier for two MSATA SSD modules that is connected via J HSE to the 6Gbps ports for fast data storage Four SATA interfaces are provided by a Marvell 88SE9230 Controller available on the Backplane connector J2 Hardware RAID configuration level 0 1 10 is supported Please be aware that CompactPCI PluslO Specefication does not support SATA 6G Therefore J2 SATA channels are configured as SATA 3G A LED named HD located in the front panel signals disk activity status of any of the SATA devices Additionally a variety of side cards is available suitable for mounting on the PC3 ALLEGRO in a 4HP 20 32mm distance resulting in 8HP front panel width for the assembly Some of these side boards can accommodate a SATA drive e g a 2 5 inch SSD Available for download from Intel s web site are drivers for popular operating systems e g Windows XP Windows Vista Windows 7 and Linux To manage the RAID configuration of the 88SE9230 a Windows application is provided by Marvell that can be downloaded from EKF s website PCI Express Interface The PC3 ALLEGRO is provided with several PCI Express PCle lanes for YO expansion Four PCI Expr
49. olution CompactPCI amp Serial PICMG CPCIS 0 defines a completely new card slot based on PCI Express SATA Gigabit Ethernet and USB serial data lines On a hybrid backplane both card styles can reside CompactPCI amp and CompactPCl Serial with the PC3 ALLEGRO in the middle as system slot controller for both backplane segments Typically the PC3 ALLEGRO and the related side card would come as a readily assembled 8HP unit As an alternate low profile Flash based mezzanine storage modules are available that fit on the PC3 ALLEGRO while maintaining the AHP profile The C42 SATA module e g is equipped with a very fast 1 8 inch SATA Solid State Drive SSD which installation of any popular operating system suitable for ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board e Intel i7 3xxx Processor 5 ea Sa n VV YY xf ekf com EKF User Guide e PC3 ALLEGRO e CompactPCI PluslO CPU Board 7 Intel i7 3xxx Processor Technical Features Feature Summary Feature Summary EKF CompactPCI amp PluslO PICMG CPCI 2 30 System Slot Controller J1 Connector for Full CompactPCIO Classic 32 Bit Support universal V I O 3 3V or 5V J2 Connector UHM High Speed for CompactPCI6 PluslO Support 4 x PCle 4 x SATA 4 x USB 2 x GbE Proven Intel amp Mobile CPU Technology 3rd Generation Intel amp Core Mobile ECC CPU Code Name Ivy Bridge i7 3612
50. on CMD CTRLO 7 GPLED 0 Green part of the front panel LED GP is off Default 1 Green part of the front panel LED GP is on GEM BERDIS 0 Enable the power event button within the front panel handle Default 1 Disable the power event button within the front panel handle 5 FRDIS 0 Enable the system reset button within the front panel Default 1 Disable the system reset button within the front panel 4 3 WDGTO WDGT1 Maximum Watchdog retrigger time 0 0 2 sec 1 0 10 sec 0 1 50 sec 1 1 250 sec 2 WDGTRG Retrigger Watchdog Any change of this bit will retrigger the watchdog After a system reset the watchdog is in an inactive state The watchdog is armed on the 1 edge of this bit 1 PGLED 0 Red part of the front panel LED PG is off Default 1 Red part of the front panel LED PG is blinking EKF 42 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel 7 3xxx Processor Bit Description CMD CTRLO O0 SRES O Normal operation Default 1 A full system reset is performed Read Clear Status Register O Write SMBus Address OxBO Read SMBus Address OxB1 Bit Description CMD STATO 6111 0 Normal operation 1 Last system reset may be caused by a power failure of the V1 8S voltage regulator CEEMEPEIDS O0 Normal operation 1 Last system reset may be caused by a power failure of the V1 5S voltage regulator 5 RESERVED Always read as 0 4 0 PFVSA O0 Normal operation 1 Last syst
51. port Module emulates a legacy BIOS environment which allows to boot a legacy operating system such as DOS 32 bit Windows and some RTOS Best Suited e g for Industrial Transportation amp Instrumentation Applications 4 Long Term Availability 4 Rugged Solution 4 Coating Sealing Underfilling Available on Reguest O EKF 10 ekf com User Guide e PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel i7 3xxx Processor Performance Rating Performance Rating tbd Operating Conditions Operating Conditions Thermal amp gt Operating Temperature 0 C to 70 C 40 C to 85 C on Request Environmental Storage temperature 40 C to 85 C max Gradient 5 C min Conditions 4 Humidity 596 95 RH non Condensing Altitude 300 3000m Shock 15g 0 33ms 6g 6ms 4 Vibration 19 5 2000Hz EC Regulations EN55022 EN55024 EN60950 1 UL60950 1 IEC60950 1 gt 2002 95 EC RoHS MTBF 104 x 10 11 9 years 50 C Power Requirements Power Requirements Load Current A at 3 3V 0 17V 0 1V Load Current A at 5V 4 0 25V 0 15V Maximum Performance Windows 7 Idle Maximum Performance Windows 7 Idle Board LFM HFM Turbo LFM HFM Turbo LEM HFM Turbo LFM HFM Turbo PC3 68XX 50 5 0 5 0 TE I TAE 9 Tl BT 0 8 0 8 08 PC3 48XX AN AI TS DUPUIS 4 5l 55 0 8 0 8 08 PC3 22XX WADA TBD TBD TBD 18 TBD TBD PC3 046X 2657 7 1 9 1 9 2
52. power failure of the V1 05M or V3 3M voltages 1 RESERVED Always read as 0 O RESERVED Always read as 0 Except of WDGHT the bits in this register are sticky 1 6 theire state will be kept even if a system reset occurs To clear the bits a write to the register with arbitrary data may be performed Read PLD Revision Register Write Not allowed Read SMBus Address 0xC1 Bit Description CMD_PLDREV 7 0 PLDREV Read PLD Revison Number O EKF 44 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel 7 3xxx Processor GPIO Usage GPIO Usage QM77 PCH GPIO Usage QM77 PCH E E E GPIO 0 ALERT Monitoring of processor PROCHOT GPIO 1 SSN EXP_SMI Expansion Interface SMI Request J EXP Pin 15 GPIO 2 5V INTP CompactPCI Interrupt Request Line INTP GPIO 3 5V CPCI ENUM CompactPCI System Enumeration Line ENUM GPIO 4 5V CPCI_PS_FAL_ON CompactPCI Power Failure Line FAL PS_ON GPIO 5 5 PM_MEMTS Memory Thermal Sensor GPIO 6 SM Not used pulled to GND GPIO 7 3 3V CPCI SYSEN 7 Sense CPCI System Slot Enable GPIO 8 3 3V Not used pulled to V3 3A GPIO 9 3 3V USB HSE 5 USB HSE Port 2 Overcurrent Detect GPIO 10 O SEV USB OC6Z USB HSE Port 3 or 4 Overcurrent Detect GPIO 11 SV GP_JUMP Reset UEFI BIOS Setup to Factory Defaults Jumper P GP GPIO 12 3 3V NC1 ENABLE Enable Ethernet Controller NC2 GPIO 13 SV HM INTA Hardware Monitor LM87 Inter
53. pport Intels Flex Memory Technology interleaved operation isn t limited to systems using memory channels of equal capacity In the case of unequal memory population the smaller memory channel dictates the address space of the interleaved accessible memory region The remainder of the memory is then accessed in non interleaved mode In asymmetric mode the memory always will be accessed in a non interleaved manner with the drawback of less bandwidth The only meaningful application of asymmetric mode is the special case when only one memory channel is populated i e the SODIMM socket may be left empty The contents of the SPD EEPROM on the SODIMM is used by the BIOS at POST Power on Self Test to get any necessary timing parameters to program the memory controller within the chipset ER nitri 221 e KH T M B ta ooon conos NANAS O EKF 18 ekf com User Guide e PC3 ALLEGRO e CompactPCI PluslO CPU Board e Intel i7 3xxx Processor Graphics Subsystem The graphics subsystem is part of the Intel Core i7 processor and the PCH QM77 While the graphics controller is located within the Core i7 processor the different interfaces like DisplayPort and VGA are moved to the PCH The PC3 ALLEGRO offers two Mini DisplayPort mDP interfaces in the front panel Adapters to convert Mini DisplayPort to any other popular interface standard are available A 3 DisplayPort is fed to
54. pt via the GPI13 input of the QM77 PCH which may result in a system management interrupt EKF 41 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board e Intel 7 3xxx Processor Board Control and Status Registers A set of board control and status registers allow to program special features on the PC3 ALLEGRO Assert a full reset Control activity of front panel reset and power event button Program time outs and trigger a watchdog Get access to two LEDs in the front panel Get power fail and watchdog status of last board reset The register set consists of five registers located on the SMBus at Device ID 0x5c on the following addresses CMD CTRLO WR Write to Control Register O Write Only OxA1 CMD CTRLO RD Read from Control Register O Read Only OxBO CMD STATO WR Write to Status Register O Write Clear gt 0481 CMD STATO RD Read from Status Register O Read Only 0 82 CMD STATI WR Write to Status Register 1 Write Clear 0483 CMD STATI RD Read from Status Register 1 Read Only OxC1 CMD PLDREV RD Read from PLD Revision Register Read Only To prevent misfunction accesses to the registers should be done by SMBus Byte Data commands Further writes to read only or reads to write only registers should be omitted Write Read Control Register O Write SMBus Address OxAO Default after reset 0x00 Read SMBus Address OxA1 Bit Descripti
55. rd Attach your antistatic wrist strap to a metallic part of the system Remove the board packaging be sure to touch the board only at the front panel Identify the related CompactPCI slot peripheral slot for I O boards system slot for CPU boards with the system slot typically most right or most left to the backplane Insert card carefully be sure not to damage components mounted on the bottom side of the board by scratching neighboured front panels A card with onboard connectors requires attachment of associated cabling now Lock the ejector lever fix screws at the front panel top bottom Retain original packaging in case of return EKF 36 ekf com User Guide e PC3 ALLEGRO CompactPCI PluslO CPU Board e Intel i7 3xxx Processor Removing the Board Warning This procedure should be done only by qualified technical personnel Disconnect the system from its power source before doing the procedures described here Failure to disconnect power or telecommunication links before you open the system or perform any procedures can result in personal injury or equipment damage Typically you will perform the following steps Switch off the system remove the AC power cord Attach your antistatic wrist strap to a metallic part of the system A Identify the board be sure to touch the board only at the front panel Unfasten both front panel screws top bottom unlock the ejector lever Remove any onb
56. re attached to the System Management Bus SMBus These are the SPD EEPROMs for the on board memory or the possibly plugged SODIMM a general purpose serial EEPROM a supply voltage temperature controlling device and a set of board control and status registers Additional devices may be connected to the SMBus via the CompactPCI Serial backplane signals SCL P1 B2 and lC SDA P1 B3 or pins 29 30 of the mezzanine expansion connector J EXP 0x58 Hardware Monitor Memory Down Temperature Sensor LM87 Ox5C Board Control Status OxA0 SPD of On board Memory OxA4 SPD of SODIMM OxAE General Purpose EEPROM Hardware Monitor LM87 Attached to the SMBus the PC3 ALLEGRO is provided with a hardware monitor LM87 This device is capable to observe the board and on board memorv temperatures as well as several supplv voltage rails with a resolution of 8 bit The following table shows the mapping of the voltage inputs of the LM87 to the corresponding supply voltages of the PC3 ALLEGRO Input Source Resolution Register Processor Core Voltage 0x28 AIN2 Graphics Core Voltage 9 8 0x29 VEEPI ar leon 14 1 0x21 VGCP2 D2 F SN 14 1 0x25 2 SIDA SES 12 0x20 T S SN E 0x22 5V Sem 26 0x23 LAY ON 6225 0x24 Beside the continuous measuring of temperatures and voltages the LM87 may compare these values against programmable upper and lower boundaries As soon as a measurement violates the allowed value range the LM87 can request an interru
57. ress Expansion Interface Connector interface to optional side board J SDVO Digital Display Interface Connector DisplayPort 1 2 CompactPCI Bus 32 bit universal V I O 33MHz PluslO SODM1 204 pin DDR3 ECC Memory Module SDRAM PC3 12800 Socket ECC SODIMM XDP CPU Debug Port 1 Connector populated on customers request only Pin Headers P FPH Pin header suitable for Front Panel Handle switch cable harness P ISP PLD glue logic device programming connector not populated Jumpers DS P Switches to configure link width and speed on J PCIE P GP Jumper to reset UEFI BIOS Setup to EKF Factory Defaults P MFG Jumper to enter Manufacturing Mode not populated P RTC Jumper to reset RTC circuitry part of PCH not populated EKF 15 ekf com User Guide e PC3 ALLEGRO e CompactPCI PluslO CPU Board 7 Intel i7 3xxx Processor Microprocessor The PC3 ALLEGRO is equipped with Intel amp Core i7 or i5 3 generation mobile ECC processor code name lvy Bridge These low power processors provide integrated graphics and memory controller which results in a very efficient platform design The Core processors almost can be considered as a single chip solution since all functions of a typical north bridge have been moved to the CPU The Core i7 and i5 processor family includes beside the Standard Voltage SV also several Ultra Low Voltage ULV and Low Voltage LV processors as listed below The processors are housed in a Micro FC BGA pack
58. riven by the power supply DEG signals the degrading of the supply voltages FALZ there possible failure On the PC3 ALLEGRO DEG is tied to VCC and FAL is routed to QM77 PCH GPIOA O EKF 27 ekf com User Guide e PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel i7 3xxx Processor Mezzanine Side Board Options The PC3 ALLEGRO is provided with several stacking connectors for attachment of a mezzanine expansion module aka side board suitable for a variety of readily available mezzanine cards please refer to www ekf com c ccpu mezz ovw pdf for a more comprehensive overview EKF furthermore offers custom specific development of side boads please contact sales ekf de 2 x SATA 6G LPC USB 4 x PCle 2 x SATA 3G SMBus 4 x USB HD Audio PCI Express 4 x SATA 3G x4 2xGbE 4x USB CompactPCl Serial up to 4 Slots CPCI S 0 gt Peripheral Boards or CompactPCI PluslO Rear VO Module Mezzanine PC3 ALLEGRO amp Backplane Intel Ivy Bridge Expansion Core 7 CPU Options EKF ekf com CompactPCl Classic up to 8 Slots Ely CompactPCI lt Peripheral Boards 5 SDVO DP PC3 ALLEGRO CompactPCI PlusIO ekf com Most mezzanine expansion modules require an assembly height of 8HP in total together with the CPU carrier board resulting from two cards at 4HP pitch each In addition cropped low profile mass storage mezzanine modules can be attache
59. rupt Line GPIO 14 USB OC7 USB J EXP Port 1 or 2 Overcurrent Detect GPIO 15 3 3V Not used pulled to 4 V3 3A GPIO 16 O 3 3V MODE DP SDVO Switch Mode of J SDVO Connector LOW J SDVO in SDVO Mode HIGH J SDVO in DisplayPort Mode GPIO 17 2 21 Not used pulled to GND GPIO 18 O 3 3V GP LED RED General Purpose Red LED Control via PLD GPIO 19 Not used pulled to 4 V3 3A GPIO 20 O NW SE SYS WP General Purpose Serial EEPROM Write Protection GPIO 21 3 3V Not used pulled to V3 3A GPIO 22 O SV SGPIO_CLOCK Serial GPIO Bus CLOCK GPIO 23 3 3V Not used internally pulled GPIO 24 3 3V USB POWEN17 USB Front Panel Right Port Power Enable GPIO 25 O 3 3V CLKOE_2J2 J2 PCle2 clk enable pulled to V3 3A GPIO26 O 3 3V CLKOE 1J2 2 PCle1 clk enable pulled to V3 3A GPIO 27 3 3V USB POWEN2A USB Front Panel Left Port Power Enable GPIO 28 SAN Not used pulled to 4 V3 3A GPIO 29 3 3V Fixed to chipset internal function GPIO 30 32 SM Not used pulled to 4 V3 3A GPIO 33 3 3V Not used GPIO 34 O EXP SMB EN Connect SMBus on J EXP to local SMBus EKF LOW J EXP disconnected from SMBus HIGH J EXP connected to SMBus 45 ekf com User Guide e PC3 ALLEGRO e CompactPCI PluslO CPU Board 7 Intel i7 3xxx Processor GPIO36 37 GPIO 38 GPIO 39 GPIO 40 GPIO 41 GPIO 42 GPIO 43 GPIO 44 GPIO 45 GPIO 46 GPIO 47 GPIO 48 49 GPIO 50 52 GPIO 53 GPIO 54
60. should be limited to 0 5A per pin EKF ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board Intel 7 3xxx Processor BED Kaka CZ ee FB Ce wt gt 3 E a lt DN lt lt lt lt PC3 ALLEGRO w C48 M2 Dual M 2 SATA SSD Module EKF 61 ekf com User Guide e PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel i7 3xxx Processor PCI Express Expansion Header J PCIE PE CLKP PE CLKN GND PE 1TP PE 1TN y X ssaJdx3 Dd worp 333 G 080 0b0 1 062 GND pieog Jae DN uo mala 901 40 25 63 153205 pasds U IH GND 11111 11111111 11111111 PE 2TP PE 2TN GND PE 3TP PE 3TN GND PE ATP PE 4 GND 1 Power rail switched on in state SO only 1 2 3 4 5 6 7 8 9 10 11 i 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 25 30 31 E 33 34 36 37 38 39 40 3 3V 3 3V GND PLTRST PE WAKEZ GND PE 1RP PE 1RN GND GND PE 2RP PE 2RN GND PE 3RP PE 3RN GND PE 4RP PE ARN GND WARNING The 3 3V 5V power pins are not protected against a short circuit event The connector J PCIE therefore should be used only for attachment of an approved expansion side card The maximum current flow through these power pins should be limited to 1A per pin EKF 62 ekf com User Guide 9 PC3 ALLEGRO e CompactPCI PluslO CPU Board e Intel i7 3xxx Processor
61. ssor Fortunately the power consumption is by far lower when executing typical Windows or Linux tasks The heat dissipation increases when e g rendering software like the Acrobat Distiller is executed The Core i7 processors support Intel s Enhanced SpeedStep technology This enables dynamic switching between multiple core voltages and frequencies depending on core temperature and currently required performance The processors are able to reduce their core speed and core voltage in multiple steps down to 1200MHz 800MHz for LV ULV processors Additional a reduction of the graphics core clock and voltage is possible This leads to an obvious reduction of power consumption resulting in less heating This mode of lowering the processor core temperature is called TM2 TM Thermal Monitor Another way to reduce power consumption is to modulate the processor clock This mode TM1 is achieved by actuating the Stop Clock input of the CPU A throttling of 50 e g means a duty cycle of 5096 on the stop clock input However while saving considerable power consumption the data throughput of the processor is also reduced The processor works at full speed until the core temperature reaches a critical value Then the processor is throttled by 5096 As soon as the high temperature situation disappears the throttling will be disabled and the processors runs at full speed again These features are controllable by BIOS menu entries By default the BIOS of th
62. tem from its power source and from any telecommunication links networks or modems before performing any of the procedures described in this chapter Failure to disconnect power or telecommunication links before you open the system or perform any procedures can result in personal injury or equipment damage Some parts of the system can continue to operate even though the power switch is in its off state Caution Electrostatic discharge ESD can damage components Perform the procedures described in this chapter only at an ESD workstation If such a station is not available you can provide some ESD protection by wearing an antistatic wrist strap and attaching it to a metal part of the system chassis or board front panel Store the board only in its original ESD protected packaging Retain the original packaging antistatic bag and antistatic box in case of returning the board to EKF for repair EKF 35 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board e Intel i7 3xxx Processor Installing the Board Warning This procedure should be done only by qualified technical personnel Disconnect the system from its power source before doing the procedures described here Failure to disconnect power or telecommunication links before you open the system or perform any procedures can result in personal injury or equipment damage Typically you will perform the following steps Switch off the system remove the AC power co
63. the on board connector J SDVO EKF expansion boards like PCS BALLET feature the possibility to gain access to the 3 DisplayPort interface As an option the PC3 ALLEGRO can be equipped with an ordinary HD D Sub 15 lead connector VGA style This connector is suitable for analog signals only Nevertheless also flat panel displays can be attached to the D Sub connector but with minor reduced image quality Independent from the video connector actually in use Mini DisplayPort DVI or VGA the VESA DDC standard is supported This allows to read out important parameters e g the maximum allowable resolution from the attached monitor DDC Power 3 3V or 5V on DisplayPort or VGA connector respectively is delivered via a resettable fuse to protect the board from an external short circuit condition 0 54 Graphics drivers for the Core i7 can be downloaded from the Intel web site LAN Subsystem The Ethernet LAN subsystem is composed of four Gigabit Ethernet ports One Intel 82579LM Physical Layer Transceiver PHY using the PCH QM77 internal MAC and three Intel 82574IT Gigabit Ethernet Controllers These devices provide also legacy 10Base T and 100Base TX connectivity Two of the Ethernet ports are fed to two RJA5 jacks located in the front panel the others are attached to the CompactPCI PluslO interface on 72 Each port includes the following features gt One PCI Express lane per Ethernet port 250MB s gt 1000Base Tx Gigabit Ethernet
64. to 4 V3 3A USB Front Panel Right Port Overcurrent Detect Not used pulled to 4 V3 3A Not used ultiplexed with chipset internal function PCB Revision Code HW REVI2 0 GPIO 67 66 64 000 001 DTO Wil Revision 0 1 2 4 7 Used as 14MHz Clock Used as HW REV 1 see GPIO64 Used as HW_REV 2 see GPIO64 Not used Not used pulled to V3 3A Clock Enable Ethernet Controller NC1 Not used pulled to 3 3 46 ekf com User Guide PC3 ALLEGRO CompactPCI PluslO CPU Board 7 Intel 7 3xxx Processor Configuration Jumpers Configuration PCI Express Switch DS P The link width and transfer rate of the PCI Express interfaces attached to the local expansion connector P PCIE is configurable by two DIP switches DS P located on the backside of the PC3 ALLEGRO Note that changes in PCle link configuration are honoured by the PC3 ALLEGRO not before a system reset was performed 160 15 02 0 EKF ekf com NETUS PCle Switch J PCIE Upstream 4 Lanes 5GT s ON OFF 4 Lanes 5GT s 4 Links x 1 Lane 5GT s 1 Link x 4 Lanes 5GT s OFF ON 4 Lanes 2 5GT s 4 Links x 1 Lane 2 5GT s ON ON 4 Lanes 2 5GT s 1 Link x 4 Lanes 2 5GT s Consists to the non fat pipe slots generally periphery slots 3 to 6 When the port on J PCIE is configured as single link the PCle switch may size down the link width to x2 or x1 by auto negotiation The following table shows the factory settin

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