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EV10AQ190-EB Evaluation Board User Guide

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1. 3 12 4 Uu UU Uu uQ a 4 15 42 ee 4 15 AG Getting Stared 4 16 4 4 Troubleshooting 8 4 21 45 SONWANE ns uu u uuu dns apasqa apuq ER 4 22 4 6 Operating Modes ses 4 23 46 1 4 24 ACO 4 28 405 9 2 4 29 4 6 4 Input Impedance 4 32 4 6 5 Load Save contfiguration 4 33 Section 5 51 Analog MPU uuu u u u u uu uu lll ua saint dai dois nan assado 5 37 cv MEE oo 0 0 1 uuu u mmm 5 38 SS FBO die u uuu E E E AEE ee RU 5 38 54 Output BE 5 39 5 5 and CMIRefCD Output Signals 5 39 5 6 Diode for Junction Temperature Monitoring iso 5 39 57 TEST DONC DESC IP E 5 40 Section 6 Ordering Information 6 41 EV10AQ190 EB User Guide 0964 1 2 08 2 semiconductors SAS 2008 7 7 1 EV10AQ190 EB Electrical 7 43 7 2 EV10AQ190 EB Board
2. 32 Id pF nF IDDnF MinF I pF 0 IBOpF pF IBnF IG pF 1 4 J 4 1 I L di BnF sav 2 5 50 2 EBV Bv Eili i Elia E133 7 i 2 Ciss T 134 T IB pF J lODpF IBnF IB pF 100pF LE nF moprL gear 100pF LE nF d 1 TE J 1 k J IBy BBV 2 7 44 EV10AQ190 EB User Guide 0964A BDC 1 2 08 e2v semiconductors SAS 2008 Appendices Figure 7 3 Electrical Schematics AVR 17 CE ELITE Er OL B ald x uj ar MEDO O i eH NI az WVup s V T Zr FEAT VEM E FH 20010 AGL neg OSH LOTS SS TE Hm E COE Es WOO OSE LUE SE BEI 619 yaoL 20v d vro IL eur vol 7 45 EV10AQ190 EB User Guide 0964 12 08 e2v semiconductors SAS 2008 Appendices Figure 7 4 Electrical Schematics ADC 7 46 0964 1 2 08 Mi ki ki ki 2X SA 142407 r 85 SE yid 2 3 4 3 56i 8 8 6 aaa a a a a a a g aE amp amp E al k AH ya A jd o c d al s 5 8 aa al a al aj gU 3 2 FESTU E FE WEST D g 7
3. ir 15 zm jm 22 Bock E Felt 3X SMA A QUAD ADC 1 z T del c En iX SMA 142 0707 85 pw PA mr P if 172 8d 34 Beach ten SER jo T 4 3 a DOR 099 E E am L an APS D EE Ege H Ja H E Er a JA E du x B E 58 Jd 1 g B a 5 s DEA 1 HEHEEEEEEEEE 5 bali dk M a Fa A EV10AQ190 EB User Guide e2v semiconductors SAS 2008 Appendices EV10AQ190 EB Board Layers 7 2 Figure 7 5 Top Layer Ge 5 E YY i mn gt 5 RAN HUHHHHHHH HHHHHHHHH 7 47 EV10AQ190 EB User Guide 0964A BDC 1 2 08 e2v semiconductors SAS 2008 Appendices Figure 7 6 Bottom Layer E 9001 585A 8 7 48 EV10AQ190 EB User Guide 0964 12 08 e2v semiconductors SAS 2008 Appendices Figure 7 7 Equipped Board Top eu en 37 gt FE D B 0 m FQ 0 d
4. is HE ze Os oO em er zu au 0 Of re or 0 om 0 mm e R RIO O J M B m j F5 23 Xx E ap HE Cy X eu esi m 7 rs a 68648 1 7 i B B E om J2 Ji J3 J15 na Jii E __ __ a a ES ES ES ES ES ES EV10AQ190 EB User Guide 7 49 0964A BDC 1 2 08 e2v semiconductors SAS 2008 5 Figure 7 8 Equipped Board Bottom x HCL m m L E 7 50 1040190 User Guide 0964A BDC 12 08 e2v semiconductors SAS 2008 e 2V Table of Contents Section 1 ais 1 3 1 2 WSS CIM OMA uu uuu uuu uu u u u 1 3 Section 2 2 1 Board Structure U a 2 5 2 2 Analog Inputs Clock Input 2 6 2 d E E as 2 6 2 4 Reset INPU S E 2 7 25 POWET u uuu u uyu I TM 2 9 Section 3 uu 3 11 3 2 Operating Procedure 3 11 3 3 Electrical
5. EV10AQ190 EB Evaluation Board User Guide 1 1 Scope 1 2 Description EV10AQ190 EB User Guide Section 1 Introduction The EV10AQ190 EB Evaluation Kit is designed to facilitate the evaluation and charac terization of the EV10AQ190 Quad 10 bit 1 25 Gsps ADC in AC coupled mode The EV10AQ190 EB Evaluation Kit includes m The Quad 10 bit 1 25 Gsps ADC Evaluation Board including EV10AQ190 ADC and Atmel ATMEGA128 AVR soldered m A cable for connection to the RS 232 port m Software tools necessary to use the The user guide uses the EV10AQ190 EB Evaluation Kit as an evaluation and demon stration platform and provides guidelines for its proper use The EV10AQ190 EB Evaluation Board is very straightforward as it implements e2v EV10AQ190 Quad 10 bit 1 25 Gsps ADC device Atmel ATMEGA128 AVR SMA nectors for the sampling clock analog inputs and reset inputs accesses and 2 54 mm pitch connectors compatible with high speed acquisition system probes Thanks to its user friendly interface the EV10AQ190 EB Kit enables to test all the func tions of the EV10AQ190 Quad 10 bit 1 25 Gsps ADC using the SPI connected to a PC To achieve optimal performance the EV10AQ190 EB Evaluation Board was designed in a 6 metal layer board using FR4 HTG epoxy dielectric material 200 um ISOLA IS410 featuring a resin content of 45 The board implements the following devices m The Quad 10 bit 1 25 Gsps ADC Evaluation Board w
6. 7 47 iv EV10AQ190 EB User Guide 0964A BDC 12 08 e2v semiconductors SAS 2008 C2 How to reach us Home page www e2v com Sales offices Europe Regional sales office e2v 106 Waterhouse Lane Chelmsford Essex CM1 2QU England Tel 44 0 1245 493493 Fax 44 0 1245 492492 mailto enquiries e2v com Europe Regional sales office e2v sas 16 Burospace F 91572 Bievres Cedex France Tel 33 0 16019 5500 Fax 33 0 16019 5529 mailto enquiries fr e2v com Europe Regional sales office e2v gmbh IndustriestraBe 29 82194 Gr benzell Germany Tel 49 0 8142 41057 0 Fax 49 0 8142 284547 mailto enquiries de e2v com Americas e2v inc 4 Westchester Plaza Elmsford NY 10523 1482 USA Tel 1 914 592 6050 or 1 800 342 5338 Fax 1 914 592 5148 mailto enquiries na e2v com Asia Pacific e2v ltd 11 F Onfem Tower 29 Wyndham Street Central Hong Kong Tel 852 3679 364 8 9 Fax 852 3583 1084 mailto enquiries ap e2v com Product Contact e2v Avenue de Rochepleine BP 123 38521 Saint Egr ve Cedex France Tel 33 0 4 76 58 30 00 Hotline mailto hotline bdc e2v com Whilst e2v has taken care to ensure the accuracy of the information contained herein it accepts no responsibility for the consequences of any use thereof and also reserves the right to change the specification of goods without notice e2v accepts no liability beyond that set out in its s
7. Phase White Write TT 0 01 Cancel 0 015 Cancel Internal Gain 0 00978 Send Internal Phase 1015 Send J Write EB 0 035 Channel DH z OFF 0 Cancel Channel Ready Busy wall Internal Offset 0055 Send Cancel Apply Polling on AVON EON CION DON Avr 2 0 Chip ID 414 In the following example you can see that the internal phase register is set to 0 015 that the user wants the phase to be set to 15 ps In the second picture the Write and Send buttons have been pushed and the internal register shows the new entered value for the phase rite Write se Cancel Cancel 15 Cancel Internal Phase 2 053 Send Internal Phase 15 EV10AQ190 EB User Guide 4 31 0964 12 08 e2v semiconductors SAS 2008 Software Tools 4 6 4 Input Impedance Quad ADC 10 bit x File Pork 7 me Quad ADU 10 bit Reset Input Impedance Write 60 5 50 41 7 Cancel Channel ON OFF w Channel Ready Busy Cancel Apply 2 0 Chip ID 4 1 4 AON EON CON Paling on In this window it is possible to re adjust the internal input resistor which should be matched to 50 The procedure is similar to the previous ones Select the channel where you need to adjust the input impedance Check that the chann
8. EV10AQ190 EB User Guide 4 29 0964A BDC 1 2 08 e2v semiconductors SAS 2008 Software Tools The calibration is successful if the internal gain offset phase boxes display the entered values new value for the gain offset phase has been entered by mistake it is possible to retrieve the initial value by pushing the CANCEL button frite 0 059 0 Internal Gain 0 056592 Send The general Apply and Cancel general buttons are not active in this window as soon as the Send button is pressed the gain offset phase adjustments are made active File Pork 7 Fen Quad AD Obit Channel Select Reset Gain Offset Phase r E ES Write Write O i Cancel 0 015 Internal Gain 200978 Send Internal Phase 0015 Send J rite Cancel Channel Ready Busy wd Internal Offset 1 033 Send Cancel Apply Avr 2 0 Chip ID 414 AON BON 4 30 1040190 User Guide 0964A BDC 1 2 08 e2v semiconductors SAS 2008 Software Tools In the following example channel is selected Values for the gain the offset the phase have been entered via the Write and then the Send buttons which explains why the Internal values are equal to the settings values 4 Quad ADC 10 bit File Pork ete Quad AD 10 bit Channel Select A Reset Gain Offset
9. a low phase noise high frequency generator as well as a band pass filter to optimize the analog input performance The analog input full scale is 500 mV peak to peak around zero analog input providing the Input common mode It is recommended to use the ADC with an input signal of 1 dBFS max to avoid saturation of the ADC 5 Connect the high speed acquisition system probes to the output connectors The digital data are differentially terminated on board 100Q however they can be probed either in differential or in single ended mode 6 Connect the PC s RS 232 connector to the evaluation board s serial interface 7 Switch on the ADC power supplies recommended power up sequence simulta neous in the following order Voc 3 3V Veep 1 8V Veco 1 8V and 3 3V 8 Turn on the RF clock generator 9 Turn on the signal generator 3 11 0964A BDC 12 08 e2v semiconductors SAS 2008 Operating Characteristics 10 Perform an analog reset SYNC potentiometer on the device 11 Launch Quad 10bit exe software The EV10AQ190 EB evaluation board is now ready for operation 3 3 Electrical Characteristics For more information please refer to the device datasheet Table 3 1 Recommended Conditions of Use Parameter Comments Recommended Positive supply voltage Includes pads 3 3 Positive digital supply voltage core Positive output supply voltage Output buffers Differential analog input voltage F
10. evaluation board Six cop per layers are used dedicated to the signal traces ground planes and power supply planes The board is made in FR4 HTG epoxy dielectric material ISOLA 15410 Table 2 1 gives a detailed description of the board s structure Table 2 1 Board Layer Thickness Profile Characteristics Layer 1 Copper layer Copper thickness 40 um with NiAu finish AC signals traces 500 microstrip lines DC signals traces HT G dielectric layer Layer thickness 200 um Layer 2 Copper layer Copper thickness 18 um Upper ground plane reference plane HTG dielectric layer Layer thickness 349 um Layer 3 Copper layer Copper thickness 18 um Power plane Voc HTG dielectric layer Layer thickness 350 um Layer 4 Copper layer Copper thickness 18 um Power planes Veco and 3V3 HTG dielectric layer Layer 5 Copper layer FR4 HTG dielectric layer Layer thickness 350 um Copper thickness 18 um Power planes reference plane identical to layer 3 Layer thickness 200 um Layer 6 Copper layer Copper thickness 40 with NiAu finish AC signals traces 500 microstrip lines DC signals traces EV10AQ190 EB User Guide 2 5 0964 12 08 e2v semiconductors SAS 2008 Hardware Description 2 2 Analog Inputs Clock Input 2 3 Digital Output 2 6 0964 12 08 e2v semiconduct
11. is grayed out 2 Check your connection and restart the application 3 If the serial interface is not active the LED appears in orange and the application is grayed out 4 20 EV10AQ190 EB User Guide 0964A BDC 12 08 e2v semiconductors SAS 2008 Software Tools Figure 4 9 QUAD 10 bit 1 25 Gsps User Interface Window E File Port 7 cw Quad Ibit Ename v Rest O Switch ON power supplies and launch the Quad ADC 10bit exe the application should become available and the LED turns to green Figure 4 10 QUAD 10 bit 1 25 Gsps User Interface Window x x File Port cw Quad ADC 10 bit ChannelSelect None Reset 4 4 Troubleshooting check that you own rights to write in the directory check for the available disk space check that at least one RS 232 serial port is free and properly configured check that the serial port and DB9 connector are properly connected check that all supplies are properly powered on ge eS Do The serial port configuration should be as follows B rate 19200 Data coding 8 bits B 1 start bit 1 stop bit No parity check Figure 4 11 QUAD 10 bit 1 25 Gsps User Interface Hardware Implementation PC Evaluation Board ADC Quad 10 bit Serial port 1 Use an RS 232 port to send data to the ADC 2 Connect the crossed DB9 F F cable between your PC and your evaluation board as illustrated in Figure 4 12 EV10AQ190 EB User Guide 4 21 0
12. 0 um between two differential pairs B 310 um line width B 40 um thickness EV10AQ190 EB User Guide Hardware Description Figure 2 2 Board Layout for the Differential Digital Outputs e 40 pm 325 The digital outputs are compatible with LVDS standard They are on board 1000 differ entially terminated as described in Figure 2 3 Figure 2 3 Differential Digital Outputs Implementation Connector Double row 2 54 mm pitch connectors are used for the digital output data The upper row is connected to the signal while the lower row is connected to ground as illustrated in Figure 2 4 Figure 2 4 Differential Digital Outputs 2 54 mm Pitch Connector X A C or D XDR XDRN XDO XDON XD7 XD7N XORN XOR GND GND GND GND GND GND GND GND 2 4 Reset Inputs Two hardware reset signals are provided SYNCP SYNCN corresponds to the reset of the output clock of the ADC analog reset RSTN corresponds to the reset of the SPI makes the SPI registers go to their default value The differential reset inputs SYNC SYNCN are provided by SMA connectors refer ence VITELEC 142 0701 8511 The signals are AC coupled using 10 nF capacitors and pulled up and down via 2000 resistors A variable resistor of 5000 is implemented on SYNC by adjusting this resistor value one can activate and deactivate easily the reset signal EV10AQ190 EB User Guide 2 7 0964 12 08 e2v semiconductors SAS 2008 Hardware
13. 964 12 08 e2v semiconductors SAS 2008 Software Tools Figure 4 12 Crossed Cable DB 9 Female 4 5 Installation Software At startup the application automatically checks all RS232 ports available on the com puter and tries to find the evaluation board connected to the RS232 port Quad ADC 10 bit DO File Port uad ADU 1036 Channel Select None Reset 4 channels 2channels and 2 5 per channel Output Mode Binary C Gray C channels Bandwidth Selection Nominal Standby Partial Standby channel amp channel Ful Standby Extra clock cycles before restart 5 Software reset 15 x SWRESET x Cancel App Avr 2 0 Chip ID 4 1 4 AON EON CON Polling an The Port menu shows all available ports on your computer The port currently used has a check mark on its left By clicking another port item the application will try to connect to an evaluation board via the selected port If a board is successfully detected on the new port the LED is green and the new port gets the check mark If the application is not able to find a board on this port an error message is displayed 4 22 EV10AQ190 EB User Guide 0964 12 08 e2v semiconductors SAS 2008 4 6 Operating Modes 4 6 1 Settings EV10AQ190 EB User Guide Software Tools The Quad ADC software included with the eva
14. Button installation the software is now complete 4 18 EV10AQ190 EB User Guide 0964A BDC 12 08 e2v semiconductors SAS 2008 Software Tools Figure 4 7 QUAD 10 bit 1 25 Gsps Completing Setup Wizard Window Completing the Quad ADC 10bit Setup Wizard Setup has finished installing Quad ADC 10bit on your computer The application may be launched by selecting the installed Icons Click Finish to exit Setup After the installation you can launch the interface with the following file C Program Files e2v QUAD_10bit Quad ADC 10bit exe The window shown in Figure 4 8 will be displayed EV10AQ190 EB User Guide 4 19 0964 1 2 08 e2v semiconductors SAS 2008 Software Tools Figure 4 8 QUAD 10 bit 1 25 Gsps User Interface Window Quad ADC 10 bit B x File Pork Quad ADU abit Channel Select Reset settings Vu ees 4 channels C 2 channels E and C 2 5 per channel 4 C 1 channels E Gps Output Mode Binary Gray Bandwidth Selection Nominal No Standby Partial Standby channel channel Full Standby Software reset x RESET x _ Extra clock cycles before restart 0 15 Notes 1 If the QUAD 10 bit 1 25 Gsps application board is not connected powered red LED appears on the right of the reset button and the application
15. Description m 500 lines matched to 0 1 mm in length between SYNCP and SYNCN m 909 um pitch between the differential traces m 1270 um between two differential pairs m 361 um line width 40 um thickness Figure 2 5 Board Layout for the SYNC Signal e 40 um 909 um 4 gt FR4 HTG 1270 um Figure 2 6 SYNC SYNCN Inputs Implementation 3 3V 10 nF SYNC H SYNC 11 EV10AQ190 SYNCN MM H SYNCN AD11 10 nF GND A push button is provided for the RSTN reset as described in Figure 2 7 on page 9 This reset can also be generated through the AVR via the User Interface 2 8 EV10AQ190 EB User Guide 0964 12 08 e2v semiconductors SAS 2008 Hardware Description Figure 2 7 RSTN Input Implementation 3 3V T RSTN AC15 EV10AQ190 GND 2 5 Power Supplies Layers 4 are dedicated to power supply planes Vec Vccp Veco and 3 3V The supply traces are low impedance and are surrounded by two ground planes layer 2 and 5 Each incoming power supply is bypassed at the banana jack by a 1 uF Tantalum capac itor in parallel with a 100 nF chip capacitor Each power supply is decoupled as close as possible to the EV10AQ190 device by 10 nF in parallel with 100 pF surface mount chip capacitors Note decoupling capacitors are superimposed with the 100 pF capacitor mounted first EV10AQ190 EB User Guide 2 9 0964A BDC 1 2 08 e2v
16. e the output clock frequency is half the data rate and thus hall the input clock frequency Two 2 mm banana jacks are provided for the CMIRefAB and CMIRefCD signals which provides the analog input common mode voltages 1 6V As the analog input is entered in AC coupled mode these CMIRefAB and CMIRefCD signals do not need to be used Two 2 mm banana jacks are provided for the die junction temperature monitoring of the ADC One banana jack is labeled DIODA and should be applied a current of up to 1 mA via a multimeter used in current source mode and the second one is connected to DIODC The ADC diode is protected via 2 x 3 head to tail diodes Figure 5 5 describes the setup for the die junction temperature monitoring using a multimeter Figure 5 5 Die Temperature Monitoring Test Setup To DIODA To DIODC 5 39 0964 12 08 e2v semiconductors SAS 2008 Application Information 5 7 Test Bench Description Figure 5 6 Test Bench Description Band pass filter Filter Thermal system Temperature range Input Signal Generator 80 to 163 10 MHZ synchronisation Digital Acquisition System Clock Signal Computer GPIB 5 40 EV10AQ190 EB User Guide 0964 1 2 08 2 semiconductors SAS 2008 6 1 Ordering Information Table 6 1 Ordering Information Part Number Package EV10AQ190CTPY EBGA 380 RoHS T
17. e ended mode CLKIN should be terminated to ground via 500 resistor This is physically done by shorting the SMA CLKIN with a 500 cap The jitter performance on the clock is crucial to obtain optimum performance from the ADC We thus recommend to use a very low phase noise clock and to filter the clock signal if a fixed frequency is used For a clock at 500 MHz we use our testbench Pass band filter from LORCH MICROWAVE 9BP8 500 30 S up to 8 dB attenuation 70 OB rejection up to 5000 MHz 500 14512 500 MHz SC Sprinter Crystal Oscillator from WENZEL Associates 5 3 Reset input The SYNCP SYNCN is necessary to start the ADC after power up The reset signal is implemented as illustrated in Figure 5 3 Figure 5 3 SYNCP SYNCN Inputs Implementation SYNC AC11 EV10AQ190 SYNCN AD11 By turning the potentiometer on the SYNC signal to the 3 3V you activate the reset and de activate it by turning the potentiometer back to its initial position near ground 5 38 EV10AQ190 EB User Guide 0964A BDC 1 2 08 e2v semiconductors SAS 2008 5 4 Output Data 5 5 CMIRefAB and CMIRefCD Output Signals 5 6 Diode for Junction Temperature Monitoring EV10AQ190 EB User Guide Application Information The output data are LVDS and are 1000 terminated to ground as shown in Figure 5 4 Figure 5 4 Output Data on board Implementation Connector The data are output in binary format and in double data rat
18. edance Page ww n A A A E A EC T PCC PC PC PC PC EC EC TN TIN ET Input Impedance Trimmer AAA A AA A M A CUN 15 000001 30 000004 Software Tools lo xi 4 channels No standby 1 2 Binary Nomina 300 4 35 0964A BDC 12 08 e2v semiconductors SAS 2008 Software Tools 4 36 EV10AQ190 EB User Guide 0964 12 08 e2v semiconductors SAS 2008 Section 5 Application Information 5 1 Analog Input The analog input XAI XAIN are entered in differential AC coupled mode as described In Figure 5 1 It is recommended to use a differential source to drive the analog inputs of this ADC external balun or differential amplifier Note References of differential amplifiers and external baluns B M A COM H9 balun B M A COM TP101 1 1 transformer In order to optimize the performance of the ADC it is also recommended to use a band pass filter on the analog input path Figure 5 1 Differential Analog or Clock Inputs Implementation EV10AQ190 EV10AQ190 EB User Guide 5 37 0964 12 08 e2v semiconductors SAS 2008 Application Information 5 2 Clock Input The clock input can be entered indifferently in single ended or differential mode with no performance degradation The clock is AC coupled via 10 nF capacitors as described in Figure 5 2 Figure 5 2 Clock Input Implementation 10 nF os m H 10 nF EV10AQ190 If used in singl
19. el is ON and Ready green LEDs Enter the resistor value Push the Write button to write these values to the internal registers you can retrieve the initial value of the impedance by clicking on the Cancel button This function helps to re adjust the input impedance in case of a slight mismatch due to temperature variations or process variations 4 32 EV10AQ190 EB User Guide 964 12 08 e2v semiconductors SAS 2008 Software Tools 4 6 5 Load and Save CONN The File menu shows possibility to load or save a configuration of the 10 0190 to create a data log file It is possible to save the configuration EV10AQ190 into txt file Select the File menu and click to Save Configuration Quad ADC 10 bit File Port Load Configuration i Save Configuration AD it Channel select None Reset Datalag 2 channels and 2 5 per channel Output Mode Binary Gray channels 5 Gene ESS Bandwidth Selection Nominal Standby Partial Standby channel A channel C Ful Standby Extra clack cycles before restart Software reset 0 15 SWRESET x Cancel Apply Avr 2 0 Chip ID 4 1 4 BON CON DOM Polling on Example of configuration file EV10AQ190 EB User Guide 4 33 0964 12 08 e2v semiconductors SAS 2008 Software Tools cfg txt Bloc notes xl Fichier Edit
20. emperature Range Ambient Section 6 Ordering Information Screening Level Standard Comments EV10AQ190TPY EB EBGA 380 RoHS Ambient Prototype Evaluation board EV10AQ190 EB User Guide 6 41 0964A BDC 12 08 e2v semiconductors SAS 2008 Information 6 42 EV10AQ190 EB User Guide 0964 12 08 e2v semiconductors SAS 2008 7 1 EV10AQ190 EB Electrical Schematics Figure 7 1 Power Supplies Bypassing IBBnF bi V wie EV10AQ190 EB User Guide Section 7 Appendices CCD ld nF 5B CRI 7 43 0964 12 08 e2v semiconductors SAS 2008 Appendices Figure 7 2 Power Supplies Decoupling J 5 Tolerance CC cs os 052 ces 054 cis cee ces IDOpF wr ONF 100pF de nr oF BnF 100 2I nF IDDpF nF 100pF ln F k K J K J K 5pv sgv 2 v 2 sav P 73 IB pF J X SAV 79 IB pF BBY CB5 4 Ca L88 25 CHI Cl42 45 1 IGGpF L l nF IBBpF IBnF IB pF Li L Ipo FL L BnF I pF ab 4 J T r 5 5 VCCD cos ces cor cos ca E 22 ci24 rus col
21. ion Format common Rw registers 04 0000 0l 0000 05 0000 06 0000 Common RO registers 1 Rw registers channel 2 Rw registers 0000 ood 0200 0200 0200 0000 0000 0000 This file could loaded into the 10 0190 1 Selectthe Filemenu and click to Load Configuration chose the file 2 ltis possible to save the Data log of the EV10AQ190 configuration into a txt file 3 Selectthe Filemenu and click to Datalog 4 34 EV10AQ190 EB User Guide 0964A BDC 12 08 e2v semiconductors SAS 2008 EV10AQ190 EB User Guide Example Datalog file data log txt Bloc notes Fichier Edition Format HHH Oe TIC TCR Settings Page ww HAE ADC Mode Standby DMU output Mode Bandwidth Selection Full scale Selection synchronization Extra clock cycle before restart AAA A A AM Test Page ww Bowe RNC RR TRUNG 7 Test Mode AOA AAA A AAA AA ww Channel A ww 7 RC NS TN M AE PC ww Gain offset Phase Page AE AA A A A A A M M Gain 0 010000 Internal Gain 0 009780 offset 0 039000 0 039000 Internal offset Phase 15 000001 Internal offset HHHHHHHHHHHHHHHHHHH HHH HHH PH OH Input Imp
22. ith the EV10AQ190 ADC soldered m SMA connectors for CLK CLKN AAI AAIN BAI BAIN CAI CAIN DAI DAIN SYNCP SYNCN CAL CALN signals m 2 54 mm pitch connectors for the digital outputs compatible with high speed acquisition system probes m Banana jacks for the power supply accesses the die junction temperature monitoring functions reference resistor analog input common mode voltage 2 mm An RS 232 connector for PC interface 1 3 0964A BDC 12 08 e2v semiconductors SAS 2008 Introduction The board dimensions are 170 mm x 185 mm The board comes assembled and tested with the EV10AQ190 installed Figure 1 1 EV10AQ190 EB Evaluation Board Simplified Schematic SYNCP SYNCN DiodC CALN CAL TO FW EV10AQ190 AUOT T GND DAIN DAI CAIN CAI BAIN BAI AAIN i CMIREFAB EE EE VCC shown Figure 1 1 different power supplies required E Voc 9 3V analog positive power supply includes the SPI pads B 1 8V digital positive power supply Vcco 1 8V output power supply B 3 digital interface primary power supply for the microcontroller 1 4 EV10AQ190 EB User Guide 0964A BDC 12 08 e2v semiconductors SAS 2008 Section 2 Hardware Description 2 1 Board Structure order to achieve optimum full speed operation of the EV10AQ190 Quad 10 bit 1 25 Gsps ADC a multilayer board structure was retained for the
23. luation board provides a graphical user interface to configure the ADC Push buttons popup menus and capture windows allows easy 1 Settings 2 Test mode 3 Gain Offset Phase adjustments With Setting and Test mode windows always click on Apply button to validate any command Cancel J Apply Clicking the Cancel button will restore last settings sent with Apply button With Gain Offset Phase and INL windows always click on Write then Send buttons to validate any command Reset button allows reconfiguring ADC to Default Mode Reset Or Software reset SWRESET 4 23 0964A BDC 12 08 e2v semiconductors SAS 2008 Software Tools Figure 4 14 Settings Quad ADC 10 bit 5 X File Port ae Quad ADC 10 bit EE L nes Settings C 2 channels E and 2 5 Gaps per channel Output Binary Gray channels F B Gsps Bandwidth Selection Nominal No Standby Partial Standby channel A channel Ful Standby Software reset Ty RESET Extra clock cycles before restart 0 E 0 15 Cancel Apply Avr 2 0 Chip ID 414 EON CON Polling oni In this window five functions are available ADC mode 4 channel mode the four ADCs work independently at Fclock 2 sampling rate where Fclock is the external clock signal frequency 4 channels C 2 channels n and 2 5 Gs
24. on 4 Software Tools The Quad 10 bit 1 25 Gsps ADC Evaluation user interface software is a Visual compiled graphical interface that does not require a licence to run a Windows and Windows 2000 98 XP PC The software uses intuitive push buttons and pop up menus to write data from the hardware The advised configuration for Windows 98 is B PC with Intel Pentium Microprocessor of over 100 MHz Memory of at least 24 For other versions of Windows OS use the recommended configuration from Microsoft Note Two COM ports are necessary to use two boards simultaneously 4 15 0964A BDC 12 08 e2v semiconductors SAS 2008 Software Tools 4 3 Getting Started 1 Installthe ADC Quad 10 bit application on your computer by launching the Setup_Quad 10bit exe installer please refer to the latest version available Figure 4 1 Install Window Favoris Outils S lectionnez un l ment pour obtenir une description 2 abjetrs 342 Ko Poste de travail The screen shown in Figure 4 2 is displayed Figure 4 2 QUAD 10 bit 1 25 Gsps Application Setup wizard Window Welcome to the Quad ADC 10bit Setup Wizard This will install Quad ADC 10bit 1 1 2 on your computer recommended that vou close all other applications before continuing Click Mest to continue or Cancel to exit Setup Cancel 4 16 EV10AQ190 EB User Guide 0964 12 08 e2v semiconductors SAS 2008 Sof
25. ors SAS 2008 The board is 1 6 mm thick The clock analog inputs resets digital data output signals and ADC functions occupy the top metal layer while the SPI signals and circuitry occupy the bottom layer The ground planes occupy layer 2 and 5 Layer 3 and 4 are dedicated to the power supplies The differential clock and analog inputs are provided by SMA connectors reference VITELEC 142 0701 8511 Both pairs are AC coupled using 10 nF capacitors Special care was taken for the routing of the analog and clock input signals for optimum performance in the high frequency domain E 500 lines matched to 0 1 mm in length between XAI and XAIN X A B C or D or CLK and CLKN 909 um pitch between the differential traces 1270 um between two differential pairs 361 um line width B 40 um thickness 850 um diameter hole in the ground layer below the XAI and XAIN CLK and CLKN ball footprints Figure 2 1 Board Layout for the Differential Analog and Clock Inputs e 40um 909 um FR4 HTG 1270 um Note The analog inputs and clock inputs AC coupled with 10 nF very close to the SMA connectors The digital output lines were designed with the following recommendations m 500 lines matched to 2 5 mm in length between signal of the same differential pair B 1mm line length difference between signals of two differential pairs 635 um pitch between the differential traces 65
26. ps per channel C channels Ja 5 4 24 EV10AQ190 EB User Guide 0964 12 08 e2v semiconductors SAS 2008 Software Tools Two channel mode the four ADCs are interleaved two by two and B C and D the sampling rate is equal to Fclock where Fclock is the external clock signal frequency the analog inputs can be applied to or B and respectively C or D Figure 4 15 Two channel Mode 4 channels 4 channels 2 channels and 2 5 Gaps per channel fe Zchannels and 2 5 Gkps pes channel dehannels 5 00 5 Gsps amp channels A channels fF channels A and 0 25 Gsps per channel f channels E and D 2 5 Gaps per channel channels A 5 Esp mode the four ADCs all interleaved the sampling rate is Fclock x 2 where Fclock is the external clock signal frequency the analog input can be applied to either A B C or D channel Figure 4 16 One channel Mode d channels 4 channels Z channelg 4 and 2 5 Gaps per channel channels and 0 25 Gens per channel channels A 5 channels B 5 C Achannels C 4 channels C Zchannels and D 2 5 Geos per channel C 2 channels and 0 2 5 Gens per channel 4 channels 5 Gsps 1 channels D 5 EV10AQ190 EB User Guide 4 25 0964 12 08 e2v semiconductor
27. rs SAS 2008 Software Tools 4 6 3 Gain Offset Phase File Port gt eV Quad ADU 10 bit Channel Select None Reset Gain Offset Phase _ ws Wie T 2 2 Cancel J 2 15 Cancel Cancel Internal Gain 10 Send J Internal Phase 15 Send J Wie Write Channel ON OFF Cancel Channel Ready Bus Qi Internal Offset E Send om Avr 2 0 Chip ID 414 AON EON CON DON Polling on In this window you can adjust the gain offset and phase of the channel selected via the channel select button on the top right of the user interface A LED shows if the channel is ON active green LED or OFF not active red LED and if the same channel is ready ready to receive gain offset or phase orders green LED or busy not ready to receive new calibration orders red LED Once a channel has been selected you can adjust the gain offset phase of this channel You first need to enter the desired value for the gain offset phase thanks to the cursor If you need to retrieve the old value of the gain offset phase click CANCEL Then you should WRITE this value to the internal registers by clicking on the WRITE button f several adjustments are needed gain AND offset AND phase then select each value and then click on the respective WRITE buttons Once all adjustments are made via the WRITE buttons then you can SEND the orders to the ADC SPI via the SEND button
28. s SAS 2008 Software Tools m Standby mode No standby all channels are active A ON B ON C ON D ON Standby Partial standby either A and B are in standby or C and D are in standby Standby channel channel B Full standby all four ADCs are in standby Standby e EV10AQ190 EB User Guide 4 26 0964A BDC 12 08 e2v semiconductors SAS 2008 Software Tools Full standby all 4 ADCs are in standby No Standby Partial Standby channel C channel D 2 0 Chip ID 4 1 4 OFF CORF D OFF Polling on General settings Output Mode Binary Gray Bandwidth Selection Output mode Gray coding binary coding Bandwidth selection nominal or full band at 3 dB m Synchronization programs the number of clock cycles prior to output clock restart after SYNC reset Extra clock cycles before restart EV10AQ190 EB User Guide 4 27 0964 12 08 e2v semiconductors SAS 2008 Software Tools Software reset resets the SPI by software 4 6 2 Test Quad ADC 10 bit HS Tes BEETLE wrasse Test Mode oy E Lance Apply In this window the test mode is available Either a ramp is generated within each ADC and output Or a flashing bit at 1 is output on each ADC 1 FF pattern every ten 00 patterns 4 28 EV10AQ190 EB User Guide 0964A BDC 1 2 08 2 semiconducto
29. semiconductors SAS 2008 Hardware Description 2 10 EV10AQ190 EB User Guide 0964 12 08 e2v semiconductors SAS 2008 3 1 Introduction 3 2 Operating Procedure EV10AQ190 EB User Guide Section 3 Operating Characteristics This section describes a typical configuration for operating the evaluation board of the EV10AQ190 Quad 10 bit 1 25 Gsps ADC The analog input signals and the sampling clock signal should be accessed in a differ ential fashion Band pass filters should also be used to optimize the performance of the ADC both on the analog input and on the clock It is necessary to use a very low jitter source for the clock signal recommended maxi mum jitter 50 ps Note The analog inputs and clock are coupled on the board 1 Install the software as described in section 4 Software Tools 2 Connectthe power supplies and ground accesses through the dedicated banana 3 Connect the clock input signals Use a very low phase noise high frequency generator as well as a band pass filter to optimize the clock performance The clock input level is typically dBm and should not exceed 10 dBm into 500 The clock frequency should be set to 2 5 GHz corresponding to 1 25 Gsps sam pling in 4 channel mode or 2 5 Gsps sampling in 2 channel mode or 5 Gsps sampling in 1 channel mode 4 Connect the analog input signals the board has been designed to allow only coupled analog inputs Use
30. tan dard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in accordance with informa tion contained herein e2v semiconductors SAS 2008 0834D BDC 12 08 08340 12 08 e2v semiconductors SAS 2007
31. tware Tools 2 Select Destination Directory Figure 4 3 QUAD 10 bit 1 25 Gsps Select Destination Directory Window Select Destination Location Where should Quad ADC 10bit be installed Setup will install Quad ADC 10bit into the following folder To continue click Hest IF you would like to select a different folder click Browse Browse At least 1 0 af free disk space is required Back Cancel 3 Select Start Menu Folder Figure 4 4 QUAD 10 bit 1 25 Gsps Select Start Menu Window Select Start Menu Folder Where should Setup place the program s shortcuts rm Setup will create the program s shortcuts in the following Start Menu folder To continue click Hest IF vou would like to select a different folder click Browse Browse Back Cancel EV10AQ190 EB User Guide 4 17 0964 12 08 e2v semiconductors SAS 2008 Software Tools 4 Ready to install Figure 4 5 QUAD 10 bit 1 25 Gsps Ready To Install Window Ready to Install Setup ix ready to begin installing Quad ADC 10bit on your computer Click Install to continue with the installation or click Back if you want to review change any settings Destination locator C Program Files es ADC 10bit Start Menu folder En _ Cancel If you agree with the install configuration press Install button Figure 4 6 QUAD 10 bit 1 25 Gsps Application Setup Install Push
32. ull Scale Digital CMOS input Clock input power level PcLkn For operation at 1 25 Gsps 2 5 Gsps or 5 Gsps in 4 channel 2 channel or Clock frequency 1 channel mode respectively Storage temperature 55 to 150 Typical conditions E Voc 3 3V Vccp 1 8V Vcco 1 8V E Vin Vinn 500 mVpp scale differential input digital outputs LVDS 1000 B Tomb typical 25 C unless otherwise specified 3 12 EV10AQ190 EB User Guide 0964 12 08 e2v semiconductors SAS 2008 Table 3 2 Electrical Characteristics Parameter Resolution Operating Characteristics Power Requirements Power supply voltage Analog and SPI pads Digital Output Power supply current Analog and SPI pads Digital Output Power supply current Partial standby mode AB Analog and SPI pads Digital Output Power supply current Partial standby mode CD Analog and SPI pads Digital Output Power supply current full standby mode Analog and SPI pads Digital Output Power dissipation Default mode Partial standby mode AB Partial standby mode CD Full standby mode EV10AQ190 EB User Guide 3 13 0964 12 08 e2v semiconductors SAS 2008 Operating Characteristics 3 14 EV10AQ190 EB User Guide 0964 12 08 e2v semiconductors SAS 2008 4 1 Overview 4 2 Configuration EV10AQ190 EB User Guide Secti

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