UG-9696HDDAF11 Evaluation Kit User Guide
Contents
1. IES BC DH BS n UG 9696HDDAF1 1 Evaluation Kit User Guide Writer Email Version Preliminary nivision Contents 1 REVISION HISTORY ee eoe itai ea eae ora pasa e sue sa a uu oup eu adeo aaa adu see aves 3 2 EVKSchematic ee 4 3 Symbol define 1 e cee ten aa a aaa iaaiiai esaudita 5 4 TIMMING CHARACTERISTICS ns 6 4 1 80 Series MPU parallel Interface eese Hn 6 4 2 6800 Series MPU parallel Interface pp 7 4 3 SPI 4 wire Series MPU parallel Interface eeessee esses 8 SoEVKUseintroduuction 9 6 Power down and Power up Sequence pp 11 7 How to use seps114a module nennen nennen nennen nnn 12 LA Initial Step FIOW rece eiie dace cece aana ee RR eren reese eteee 12 7 2 RD recommend Initial Code for 80 Interface sees 13 7 2 1 Sub Function for 80 Interface eese 13 fA EL AS Rr 1 REVISION HISTORY Date Page Contents Version 200X XX XX Preliminary Preliminary 0 0 Jnivision 4c Es 2 EVK Schematic pe I uE 16V k mev aannraaktasse AAARAAR AEA J2 J3 J4 J5 VDD IN VCC IN VDD VDD VDD voc C VDDIO GND VDD Donc EN PS To EN IN a DCDC GND GND VDD IN VC C VDDIO2. data at DO D7 will be transferred to the command register For detail relationship to MCU interface signals please refer to the timing characteristics diagrams at following pages and datasheet RESB Reset SEPS1 14A active low VCC External Column Driving Power Supply VDD Logic power supply GND Power supply ground EEA ERAS wd 4 TIMMING CHARACTERISTICS 4 1 80 Series MPU parallel Interface Write Timming CSB AQ twRLwW8 DB 15 0 Figure 1 80 Series MPU parallel Interface Timing Diagram VDD 2 8V Ta 250 reaa pee ff pp m Address hold timing tans Address setup timing tass System cycle timing ci Write L pulse width IRL WRB Write H pulse width 45 Data setup timing toss 30 DB 15 0 Data hold timing tons 10 ns notice All the timing reference is 10 and 90 of VDDIO Table 1 80 Series MPU parallel Interface Timing Characteristics Ea ERAS wd 4 2 6800 Series MPU parallel Interface Write Timming CSB A0 RW WRB DB 15 0 Figure 1 80 Series MPU parallel Interface Timing Diagram VDD 2 8V Ta 250 Address hold timing tane Address setup timing tase System cycle timing Write L pulse width Write H pulse width D ata setup imi B DB 15 0 Data hold timing Notice All the timing PEE is 10 and 90 d VDDIO Table 1 80 Series MPU parallel Interface Timing Characterist
3. time the driver IC power up down routine should include a delay period between high voltage and low voltage power sources during turn on off Such that panel has enough time to charge up or discharge before after operation Power up Sequence Power up Vpp Send Display off command Driver IC Initial Setting Clear Screen Power up Vppu Delay 100ms when Vpp is stable Qu At dee uas pu uem 7 Send Display on command Power down Sequence Send Display off command 2 Power down Vppg 3 Delay 100ms when VppH is reach 0 and panel is completely discharges 4 Power down Vpp Vpp on Vcc on Display on Vcc Vpp Vss Ground Display off Vec off i Vpp off Vcc Vpp Vss Ground 11 gag vision eee 7 How to use SEPS114A module 7 1 Initial Step Flow Reset Driver IC RES 0 Delay 10ms RES 1 Driver IC Initial Code Suggest all register set again Clear RAM Display on Start Dispaly Univision 7 2 RD recommend Initial Code for 80 Interface
4. PS CH DCDC IN EVK VDDIO VDD gt Kit 73 JUMP VDDIO For this edition VDDIO pin already accessed with VDD so it will cannot use external applicable function and have no bond up with J3 JUMP component for this edition and J3 JUMP have no function in this edition we will modify EVK in our next edition and recover function of external applicable for VDDIO nivision 3 Symbol define D7 D0 These pins are 8 bit bi directional data bus to be connected to the MCU s data bus The D0 D7 are for command and data inputs 8bit parallel interface CSB This pin is the chip select input The chip is enabled for MCU communication only when CS is pulled low RDB When connecting to an 8080 microprocessor this pin receives the Read RD signal Data read operation is initiated when this pin is pulled low and the chip is selected When serial interface is selected this pin RD must be connected to VSS WRB When 8080 interface mode is selected this pin will be the Write WR input Data write operation is initiated when this pin is pulled low and the chip is selected When serial interface is selected this pin R W must be connected to VSS AO This pin is Data Command control pin When the pin is pulled high the data at DO D7 is treated as display data When the pin is pulled low the
5. ics Univision 4 3 SPI 4 wire Series MPU parallel Interface CSB Ne tes y t less y AO tess ecce NECS tse WEN IIIJ SCL SDI X X TII Figure 1 SPI 4 wire Series MPU parallel Interface Timing Diagram VDD 2 8V Ta 25t ITEM SYMBOL CONDITION MIN Serial clock cycle 2 SCL H pulse width SHW 9 SCL L pulse width 9 00 0 0 5 5 5 5 5 5 Data setup timing Data hold timing imi 2 uM 2 CSB hold timing 2 RS hold timing 2 Notice All the timing reference is 10 and 90 of VDDIO Table 1 SPI 4 wire Series MPU parallel Interface Timing Characteristics IES BC PH BRS n 5 EVK use introduction We Figure 5 EVK PCB and OLED Module UG 9696HDDAF 11 is COF type module please refer to Figure 5 Figure 6 User can use leading wire to connect EVK with customer s system The example shows as Figure 7 RERED ARZA Figure 6 The combination of the module and EVK Figure 7 EVK with test platform Note 1 Itis OLED high voltage supply Note 2 It is logic voltage supply Note 3 Those are leading wire connect to control board Those are data pin DO D7 Note 4 Those are leading wire connect to control board Those are control pin RDB WRB AO RSTB CSB 10 Univision 6 Power down and Power up Sequence To protect OLED panel and extend the panel life
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