Home

CP6011 User's Guide

1. G 1 A Memory amp 1 0 Maps A 1 MEMORY MAPPING 1MB to top of DRAM System BIOS Optional ROM free LAN BIOS if activated 30KB SCSI BIOS 18KB at runtime Optional ROM Free Video BIOS 100000h See detailed map to the right XBDA USB Legacy BIOS Stack Video DRAM 0 622KB DRAM Address 00000 9B7FF 9B800 9FFFF A0000 BFFFF C0000 CBFFF CCO00 DBFFF E0000 FFFFF 100000 PCI Memory FFFFFh See Note 2 See Note 1 CC000h C0000h A0000h Note 1 LAN BIOS address may vary Note2 SCSI BIOS address may vary Size is only 2KB if no device Function 0 622 KB DRAM 622KB 640 KB XBDA USB Legacy BIOS Stack Video DRAM Video BIOS Optional ROM Free LAN BIOS around 30KB if activated address may vary External SCSI BIOS 18KB 64KB address may vary System BIOS DRAM available 2 1 0 MAPPING Address Optional Function Address 000 01F DMA Controller 1 020 03F Interrupt Controller 1 040 05F Timer 060 06F Keyboard 070 07F Real time clock 080 09F DMA Page Register 0 0 0 Interrupt Controller 2 0C0 0DF DMA Controller 2 0F0 0F1 0F8 0FF Math Coprocessor 190 1AB Kontron Control Port 1F0 1F7 3F6 Primary IDE 170 177 376 Secondary IDE 3F0 3F7 Floppy Disk 3F8 3FF COM1 2F8 2FF COM2 Serial Port 1 0 1 by default 2F8 2FF COM2 3F8 3FF COM1 Serial Port 2 COM2 by default 400 OF FF Chipset Reserv
2. 3 9 3 6 3 Installing a PMC C ard 3 9 3 6 4 Installing the IDE Mezzanine 3 9 3 6 5 Installing a CompactFlash 3 10 Building a cPCI System 4 amp 1 Building cPCLSystetm eE 4 1 4 1 4 2 4 1 3 St rage Devices 4 2 cod ripe 4 2 4 1 5 Connector Keying o 4 2 41 6 Bus 4 3 4 1 7 CompactPCI COnNeCt sua 4 4 4 2 CPCII O 4 5 4 1 J3 Signal SPCC CALOM aai 4 5 4 8 2 3 OSTA NALS PECIICAL ON sss 4 10 Software Setup 5 1 PHOENIX BIOS Setup Program 5 1 5 1 1 Accessing the BIOS setup program 5 1 5 1 2 The Men Bab la Su suls 5 3 51 3 Boot MESS S 5 20 52 Installing 5 21 Oed Plat eens 5 21 5 2 2 Eth r et RUEa 5 21 52 3
3. 0 12 0 18 amp JNB3 PMC JNA3 82 83 0 13 D 19 D 14 BIOS Setup Error Codes E 1 POST M NUR 1 E 2 POST 6 6616 E 6 E 3 Error 7 F BIOS Update amp Emergency Procedure F 1 BIOS UPDATE PROCEDURE AA TEN F 1 F 2 EMERGENCY tur ACEEA A AN EEA F 1 G Getting Help Safety Instructions Contents TOM BODIE ossis eic viii When Working Inside a ix Preventing Electrostatic Discharge x Working with BOTS vii Before You Begin Before handling the board read the instructions and safety guidelines on the following pages to prevent damage to the product and to ensure your own personal safety Refer to the Advisories section in the Preface for advisory conventions used in this user s guide including the distinction between Warnings Cautions Important Notes and Notes Always use caution when handling operating the computer Only qualified experienced authorized electronics service personnel should access the interior of the computer The power supplies produce high voltages and energy hazards which can cause bodily harm Use extreme caution when installing or
4. IDE Failure Prediction Monitoring Enabled Disabled di Floppy check Enabled Enabled verifies floppy type on boot disabled speed boot 5 8 5 1 2 5 2 PCI Configuration Feature 0ptions Description ee Additional setup menus to configure On board Ethernet Controller Controller On board PMC Expansion PCI Performance Settings Default Primary Video Adapter Delay before PCI Initialization IDE Device 31 Function 1 Legacy USB Support This is a Sub Menu This is a Sub Menu External On board Oto7 Enabled Disabled Enabled Auto Additional setup menus to configure PMC Expansion Slot Additional setup menus to configure PCI Performance settings Select External to have a PCI video card must be installed to be set as the Boot Display Device Select On board to have the On Board video controller as the Boot Display Device Delay in seconds before PCI Initialization Some external cards may require a minimum delay after reset before they can be accessed Cards with onboard CPU that emulate a PCI Controller ex RAID are more likely to require a delay Enabled or Disabled the IDE controller Enables support for Legacy Universal Serial Bus 5 1 2 5 2 1 On board Ethernet Controller Feature Options Description Onboard Ethernet Controller 1 Option ROM Onboard Ethernet Controller 2 Option ROM Onboard Ethernet Controller 3 Option
5. 2 23 29 Debugging Features 2 24 2 9 1 Bi color Debug LED BLUE USER LED 2 24 2 9 2 SenaL Post CodeS eel destin 2 25 2 10 7 Miseellaneous Features su u 2 25 2101 Sena NUmbe a u SOC 2 25 iii 3 Installing the board 31 Setting 3 1 Si Jump er D escrIpli fi 3 1 3 1 2 Setting Jumper amp locations 3 2 Se V Pra LR 3 3 3 8 aina 3 3 3 3 1 Installing ws uui ede a ul u a va 3 4 3 amp Onboard Interconnectivity 3 5 3 4 1 Onboard Connectors and Headers 3 5 3 4 2 Front Plate Connectors and Indicators 3 6 3 5 Backup Battery peo Vie bk Pe 3 7 3 5 1 Operation and Preventative Maintenance 3 7 3 6 Board Hot Swap and Installation 3 8 3 6 1 Installing the Card in the Chassis 3 8 3 6 2 REMOVING ANE Board
6. C 5 22 BMC Control eaae C 5 C13 lt O1AOhs PCL Interrupt eerte eene oi tae 6 CHA Interrupt ernable 4 u C 6 15 kae ge Ye Q C 6 C 16 O1A4h Control FWH Boot block and Mezzanine C 7 D Connector Pinouts D 1 Connectors and Headers Summary D 1 D 2 CPCT BUS 01 D 2 D 3 D 3 D 4 CPCT 1 0 93 ur D 4 D 5 CPCLI O CPIM D 5 D 6 CPCT T O SCSD awaqa D 6 D 7 CB IND D 7 D 8 Port 1 RS 232 etae eaa oo ves D 8 D 9 USB located on faceplate J11 D 8 D 10 Ethernet Management 79 ui a rra rene etn ry aane uno ex vo Ere ae aee e uo rea D 8 DAT Hot Swap Switch 113 entrer D 8 12 14 A D 9 DAS Reset Switch SW uyu l D 9 0 14 CMOS Battery Backup Connector 1 D 10 0 15 CompactFlash J12 ERI CI Sus suis s D 10 D 16 1 amp JNB1 JNA1 amp 0 1 D 11 0 17 2 2 amp JNB2 JNA2 82 02
7. STOP LOCK VCC3E IPMBO_SCL IPMBO_SDA GND PERR SERR GND VCC3E PAR CBE1 VCC3E AD15 AD14 GND AD13 AD12 GND VI O AD11 AD10 VCC3E AD9 AD8 M66EN CBEO AD7 GND VCC3E AD6 AD5 VCC3E AD4 AD3 VCCE AD2 AD1 VCCE ADO ACK64 VCCE REQ64 ENUM VCC3E VCCE N N N N m YFP FP h FP Active Low Long pins 3D 4C 5D 6C 7D 9D 10D 17D 19D 22C 23D 24C Short pins 9B 15D D 2 D 3 CPCI BUS 12 On Oo HR Ww 5 Active Low ROW B ROW C REQ1 SYSEN GNT3 V1 0 AD61 VI O AD54 VI O 047 VI O AD40 VI O AD33 DEG PRSTH RSV IMPB1_SDA RSV RSV GA2 D 3 ROW D GNT1 GNT2 REQ4 GND CBE4 GND AD58 GND AD51 GND AD44 GND AD37 GND REQ5 GND REQ6 GND SMB1_SCL GND RSV GA1 REQ2 REQ3 GNT4 CBE6 PAR64 AD60 AD57 AD53 AD50 AD46 AD43 AD39 AD36 AD32 GNT5 RSV GNT6 RSV SMB_ALERT RSV RSV GAO 4 1 0 13 1 2 3 4 5 6 7 8 9 e e m U KR WY COM1 RTS COM1 RI COM2 RTS COM2 RI VGA BLUE VGA RED VCC3 USBO DATA USB1 DATA USB1 VCC LAN3 ERX LAN3 ETX LAN2 ACT LAN2 LINK LAN1 DB LAN1 DA LAN2 DB LAN2 DA COM1 RXD COM1 DTR COM2 RXD COM2 DTR VGA HSYNC VGA GREEN 102 USBO DATA USB1 DATA USBO VCC LAN3 ERX LAN3 ETX LAN1 ACT LAN1 LINK LAN1 DB LAN1 DA LAN2 DB LAN2 DA COM1 DSR COM1 CTS
8. Address 0x1A2 SWITCH WDOG ENUM RSV Action D7 D3 D2 01 00 READ RSV NU WRITE RSV NU SWITCH SWITCH WDOG ENUM WDOG NU A one indicates a switch event has occurred Switch state can be read on 0191h bit 5 Write a one to this bit clears the interrupt A one indicates a watchdog interrupt has occurred Writing a one to this bit clears the watchdog and clears the interrupt Reset will occur 16ms after the interrupt A one indicates an ENUM has occurred on either the onboard CPCI interface or the mezzanine interface Writing a one to this register does nothing The interrupt condition must be cleared in the source PCI device Rewrite what is read 16 01 4 CONTROL FWH BOOT BLOCK AND MEZZANINE Address 0x1A3 FWH_MEZZ_BIT TBL WP MEZZ Action READ WRITE D7 D6 D5 NU NU FWH_MEZZ_BIT NU NU FWH_MEZZ_BIT Select FWH Mezzanine BIOS When this bit is 0 net fwh_mezz is sink to GND and onboard FWH have address 0 When this bit is 1 PLD float this net and onboard FWH have address 1 This bit has no effect when we don t have FWH Mezzanine TOP SECTOR LOCK When low prevents programming or sector erase to the highest addressable sector 7 in a 4 Mbit 15 in an 8 Mbit component regardless of the state of the lock registers TBL high disables hardware write protection for the top sector though register based protection still applies The status of TBL does not affect the status of sector loc
9. Ctrl F1 Esc O P F1 Esc 65 Ctrl F2 EscO Q F2 Esc 66 Ctrl F3 EscOR F3 Esc 67 Ctrl F4 EscO S F4 Esc 68 Ctrl F5 EscOw F3 Esc 69 Ctrl F6 EscO x F4 Esc 70 7 Ctrl F7 EscOt F5 Esc 71 Ctrl F8 EscOu F6 Esc 72 7 Ctrl F9 EscO q 7 Esc 73 Ctrl F10 EscOr F8 Esc 74 Ctrl F11 EscO p F10 Esc 75 Ctrl F12 5 3 3 Running Without a Terminal The board can boot up without a screen or terminal attached If the speed is set to Auto and no terminal is connected the speed is set to 115 200 bauds Furthermore you can run without any console at all by simply not enabling VT100 Mode and by disabling the onboard video Full Setup Partial Setup COM COM Connector Connector TID gt RXD ple RxD 4 4 1 TxD a OTR 4 DSR E m DSR 4 DTR a DSR 8 RTS cs 8 RTS CTS RTS cts DCD 4 DCD 22 GND __ GND GND 5 23 Appendix Contents A Memory amp 1 0 Maps A 1 B Interrupt B 1 C Kontron Extension Registers C 1 D Coniector PINOUTS L save cauto e roa rye q s oi ege uio PUE D 1 E BIOS Setup Error Codes E 1 F BIOS Update amp Emergency Procedure F 1 G
10. Analog blue video signal Description 4 2 1 11 Power Pin Assignment A19 B19 C19 D19 E19 C15 C18 4 2 1 12 ID Pin Assignment A11 A12 B11 B12 C8 C13 D8 D14 E8 E14 Description 5V Supply voltage 3 3V Supply voltage 12V Supply voltage 12V Supply voltage Ground Description Reserved for Kontron internal use 4 7 4 2 2 4 2 2 1 00 to 015 DO to D15 TERMPWR1 to TERMPWR9 10 REQ CD SEL MSG RST ACK BSY ATN DPL DPH DIFFSENS J4 Signal Specification SCSI Interface Pin Assignment 5 D5 7 D7 8 08 A10 24 024 022 025 A1 D1 2 D2 E4 B5 E5 B7 E7 B8 E8 B10 B24 E24 B25 E25 B1 E1 B2 E2 A16 B16 A15 B15 D15 E15 B11 011 E11 D22 E22 A22 B22 D21 E21 A21 B21 D19 E19 A19 B19 D18 E18 A18 B18 D16 E16 D10 E10 A4 B E23 A3 A6 A9 A17 A20 B3 B6 B9 B17 B20 C1to C25 D3 D6 D9 D17 D20 E3 E6 E9 E17 E20 A23 D23 Description SCSI data The SCSI data lines drive the ID during arbitration and selection and command and data information as well as status and messages Termination power In Out Indicates the in direction when asserted and the out direction when not asserted Request A target will assert REQ to indicate a byte is ready or is needed by the target Command Data Indicates Command or message p
11. At Kontron we take great pride in our customers successes We believe in providing full support at all stages of your product development If at any time you encounter difficulties with your application or with any of our products or if you simply need guidance on system setups and capabilities contact our Technical Support at CANADIAN HEADQUARTERS Tel 450 437 5682 Fax 450 437 8053 If you have any questions about Kontron our products or services visit our Web site at www kontron com You also can contact us by E mail at support ca kontron com Or at the following address Kontron Canada Inc 616 Cur Boivin Boisbriand Qu bec 276 2 7 Canada RETURNING DEFECTIVE MERCHANDISE Before returning any merchandise please do one of the following if your product malfunctions e Call e Fax e E mail Call our Technical Support department in Canada at 450 437 5682 Make sure you have the following on hand our Invoice your Purchase Order and the Serial Number of the defective unit Provide the serial number found on the back of the unit and explain the nature of your problem to a service technician The technician will instruct you on the return procedure if the problem cannot be solved over the telephone Make sure you receive an RMA from our Technical Support before returning any merchandise Make a copy of the request form on the following page Fill it out Fax it to us at 450 437 8053
12. Board Part Number Static information CP6011 1000123456 T6011 A_1000 Description Inventory information about the board 5 18 5 1 2 5 10 Boot Menu Feature Options Description Boot From Primary Master Boot From Primary Slave Boot From Secondary Master Boor From Secondary Slave Boot From Floppy Boot From CDROM Boot Menu Boot From CompactFlash Boot From SCSI External Boot From LAN1 Boot From LAN2 Boot From LAN3 Boot From USB CDROM Boot From USB Floppy 5 1 2 6 Exit Menu Selection Feature Description Exit Saving Changes Yes No Exit Saving Changes Setup and save your changes to CMOS Exit Discarding Changes Yes Exit Discarding Changes Exit utility without saving Setup data to CMOS Load Setup Defaults Yes No Load Setup Defaults Load default values for all SETUP items Discard Changes Yes No Discard Changes Load previous values from CMOS for all SETUP items Saves Changes Yes No Save Changes Save Setup Data to CMOS 5 19 5 1 3 Boot Utilities Phoenix Boot Utilities are Phoenix QuietBoot Phoenix MultiBoot Phoenix QuietBoot displays a graphic illustration rather than the traditional POST messages while keeping you informed of diagnostic problems Phoenix MultiBoot is a boot screen that displays a selection of boot devices from which you can boot your operating system 5 1 3 1 Phoenix Quiet Boot Right after you turn on or reset the computer Phoenix Q
13. In peripheral mode the CP6011 is universal in this respect so there 15 no color key in J1 However always key backplanes in accordance to their VIO settings Note that 5V signaling forces a 33MHz PCI bus mode When operating at 3 3V all PCI and PCI X frequencies are valid In system mode the CP6011 is 3 3V or 5V Depending on Option only due to the CPCI bus pull up values To use the board with a 3 3V or 5V VIO you have to use correct board option 4 2 Signaling Voltage Key Color 3 3V Cadmium Yellow 5V Brilliant Blue Universal board 5V and 3 3V None Keying also is defined in the J4 connector to determine its usage CP6011 supports user 1 0 on J4 so itis keyed with the nut brown key Backplanes that feed through J4 also have a brown key Other J4 usages have their key defined in PICMG2 10R1 0 J4 Usage Key Color User 1 0 Nut Brown H 110 Strawberry Red Standard switch Blue Lilac Extended switch Ocher Yellow Cavity keying within the card guide and handle is used to protect J2 J3 and J5 usage The CP6011 is keyed accordingly to PICMG2 10R1 0 and PICMG2 16R1 0 Few systems support this keying so you must take care to verify the type of slot before installing the board XL VHDS features complete keying and offers the greatest protection against pinout mismatch 4 1 6 Bus Mastering The CP6011 provides seven pairs of REQ GNT 0 6 arbitration signals through the secondary PCI bus This means that the board can driv
14. Y CP6011 User s Guide Pentium M Document Revision 1 3 kontron Ref M6011 TECH 1 February 2006 Customer Service Contact Information Kontron Canada Inc 616 Cur Boivin Boisbriand Qu bec Canada J7G 2A7 Tel 450 437 5682 800 354 4223 Fax 450 437 8053 E mail support ca kontron com Visit our site at www kontron com 2006 Kontron an International Corporation All rights reserved The information in this user s guide is provided for reference only Kontron does not assume any liability arising out of the application or use of the information or products described herein This user s guide may contain or reference information and products protected by copyrights or patents and does not convey any license under the patent rights of Kontron nor the rights of others Kontron is a registered trademark of Kontron All trademarks registered trademarks and trade names used in this user s guide are the property of their respective owners All rights reserved Printed in Canada This user s guide contains information proprietary to Kontron Customers may reprint and use this user s guide in other publications Customers may alter this user s guide and publish it only after they remove the Kontron name cover and logo Kontron reserves the right to make changes without notice in product or component design as warranted by evolution in user needs or progress in engineering or manufacturing tec
15. im Bios Settings PEE Monitoring gt IDE Activity Led 2 9 1 1 POST Code Blinker The postcode blinker circuit uses a blinking sequence to display the current POST Power On Selft Test code value on faceplate This sequence restarts every time the POST codes value changes Because POST codes changes all the time during a normal boot process the blinker does not have enough time to complete its sequence and the debug LED blinks meaninglessly If the boot process succeeds the POST code value has no interest and the BIOS will disable the post code blinker before the operating system launches Ifthe boot sequence fails or the CPU hangs the postcode blinker remains operational and repeats indefinitely the last postcode blink sequence defined below 1 Blink simultaneously RED and GREEN one time start of the sequence 2 Blink RED R times while GREEN stays off R range from 0 to 15 3 Blink GREEN G times while RED stays off G range from 0 to 15 4 Repeatthe sequence See step 1 R is the first most significant digit of the post code value in hexadecimal while G is the second digit i e post code value is RGh Some examples are shown in the following figure 2 24 e ee vcoccect ccteecccc 2 9 1 2 Application Software Use of the Debug LED A status LED can be very useful for software development and for system level troubleshooting Consult register 0x19A description for software usage Ap
16. nominally implementing the Hot Plug Service and Hot Plug System Driver An ENUMi signal which is an open collector open drain bussed signal to signal change in status for the board A switch actuated with the lower ejector handle indicating the beginning of the extraction process or end of the insertion process A LED to indicate the status of the software connection process A set of four control and status bits hot swap register in PCI configuration space on each board allows the system host s software to determine the source of the ENUM signal and control the LED 1 8 1 5 5 High Availability mechanism When using High Availability system such as XL VHDS and XL LP42 the system has more control over the hardware connection process compared with the full hot swap model When a board is inserted in the system the Hot Swap Controller HSC detects this insertion before powering up the newly inserted board When the HSC is ready to power up a card it asserts BDSEL and monitor the HEALTHY signal for that card This flexibility gives the possibility to the operator for example to cycle the power state of a problematic I 0 board or to reset only a particular slot Refer to your system manual for more details on how to use the High Availability feature of the system In addition to the resources a board present to Full Hot Swap system the following ones are usable on HA systems e A BDSEL signal controls the power sta
17. COM2 DSR COM2 CTS VGA VSYNC VGA SDA ID3 GND GND GND GND GND RSV LAN CT GND GND GND GND VCC3 D 4 COM1 DCD COM1 TXD COM2 DCD COM2 TXD VGA SCL POST CLK 4 RSV RSV RSV RSV RSV LAN3 ACT LAN3 LINK LAN1 DD LAN1 DC LAN2 DD LAN2 DC 12V 191 MOUSE CLK MOUSE DATA KB DATA KB CLK POST DATA SPEAKER RSV RSV RSV RSV RSV RSV RSV LAN1 DD LAN1 DC LAN2 DD LAN2 DC 12V 0 5 11 0 24 ROW ON OQ Ui D D D D D D D D D D D KEY AREA D 5 D 6 1 0 SCSI 14 Eo c ELI gt Nil ne PS ro TS I 5 m mjela Ui rn 5 DU KR WMH gt D12 014 GND DP1 D1 GND D3 D5 GND D7 DIFFSENS TERMPW TERMPW GND BSY RST GND SEL REQ N C D8 D10 ROW B D1 D3 D5 GND D7 TERMPW TERMPW TERMPW GND BSY RST GND SEL REQ KEY AREA D 6 D13 015 GND DO D2 GND D4 D6 GND GND DPO DPO TERMPW TERMPW TERMPW TERMPW ATN ATN GND GND ACK ACK MSG MSG GND GND CD 10 N C D9 D11 7 1 0 15 ON O O Ut HG PP PB BP BP B FP Ui KR WwW FP Active Low GND RSV GND RSV GND RSV GND RSV GND FD MSENO FD MTR
18. D17 D20 E3 E6 E9 E17 E20 Ero GND 4 2 2 3 Mezzanine Connector JN4 Pin Assignment Description P14 to P32 1 2 5 6 9 10 13 14 17 18 21 22 25 26 29 30 33 34 37 38 41 42 45 46 49 50 53 54 57 58 61 62 3 4 7 8 11 12 15 16 19 20 23 24 27 28 31132 35 36 39 40 43 44 47 48 51 52 55 56 59 60 63 64 4 9 4 2 3 45 Signal Specification 4 2 3 1 IDE Interface Pin Assignment Description IDE RESET E15 Reset signal A18 D18 A17 D17 A16 D16 A15 D15 Disk Data These signals are used to transfer data to or from IDE1 D0 D15 B15 16 B16 E17 B17 E18 B18 E19 the IDE device Disk DMA Request This signal is directly driven from the IDE IDE1 DMARQ 19 device DMARQ signal It is asserted by the IDE device to request a data transfer Disk 1 0 Write In normal IDE mode this is the command to the IDE device that it may latch data from data lines Disk 1 0 Read In normal IDE mode this is the command to the IDE1 IOR IDE device that it may drive data on SDD lines 1 0 Channel Ready This input signal is negated to extend the host transfer cycle of any host register read write access when the drive is not ready to respond to a data transfer request When not negated it is in a high impedance state IDE1 IORDY DMA Acknowledge This signal directly drives the IDE device DMACK signal It is asserted to indicate to IDE DMA slave devices t
19. Initial Prefetch 4 during reads initiated from the primary port no effect when count So Dak in PCT X mode None 4 Controls Incremental Read Prefetch Dwords count When 8 an entry s remaining Prefetch Dword count falls below 12 this value the bridge will prefetch an additional PCI PCI Sec Incremental 16 Sec Incremental Prefetch count Dwords no effect Prefetch count when in PCI X mode 20 The count must not exceed half the value in the PCI Sec 24 Maximum Prefetch count Otherwise no Incremental 28 Prefetch will be performed 32 Dwords 5 11 2 to 64 Dwords 2 Controls the maximum count of prefetcheable Dwords 3 that are allocated to one entry on the Secondary when PCI Sec Maximum 30 flow through for that entry was not achieved no effect Prefetch count 32 when in PCI X mode 34 Exception 0 256 bytes 64 Dwords maximum programmable count 63 64 5 1 2 5 3 On board Device Configuration Feature 0ptions Description Enabled ric is ii using options Serial port A Disabled Auto Enabled User configuration Auto BIOS or OS chooses configuration 3F8 Base 1 0 2F8 address 3E8 Sets the base 1 0 address for serial port A 2E8 Interrupt Sets the interrupt for serial port A Enabled Configure serial port B using options Disabl 2 Serial portB isabled Disabled No configuration Auto Enabled User configuration Auto BIOS or OS chooses configuration 3F8 Base 1 0 2F8 address 3 8
20. SMS to discover all system s components and to build a database of all management controller sensors You can find more information about the IPMI at the following Web site http www intel com design servers ipmi index html 2 14 2 8 1 1 IPMI Glossary IPMI FRU Data SAF HPI Intelligent Platform Management Interface Baseboard Management Controller In a compact PCI chassis there can be only one BMC present The BMC includes de SEL and the SDRR for the complete system The BMC is connected to the other blades in the system via a dedicated bus IPMB The CP6011 management controller can be set in BMC by selecting the option in the BIOS setup menu Satellite Management Controller In a compact PCI chassis there can be many SMC Each SMC is connected to the BMC via a dedicated bus IPMB The CP6011 management controller can be set in SMC mode by selecting the option in the BIOS setup menu System Event Log The SEL is present only in the BMC If an event occurs in any blade the sensor event is sent throught the IPMB bus if SEL 15 not local and stored in the BMC SEL Sensor Data Record This is the IPMI data structure that defines a sensor Sensor Data Record Repository The SDRR is only present witin the BMC Usually the SDRR contains all management controller SDRs of the chassis A Kontron utility named fillsf exe is provided the IPMI DOS tool package to make a full chassis discovery and fill the SDRR
21. Up to 64 bit 133MHz PCI X PMC Slot Slot B Up to 64 bit 100MHz PCI X PMC 1 0 module PIM support through 24 Up to 2GB on 2 x 200 pin latching SO DIMM sockets 1 45 inch maximum height Two DDR channels 72 bit 200 266MHz for Interleave operation PC 1600 PC 2100 DDR registered SDRAM non ECC ECC mode ECC error correction up to a nibble error detection for more than a nibble Flash Memory 1MB BIOS field upgradeable with BIOS mezzanine and with PH FLASH software System Memory 1 2 Board Specifications continued Description Front Plate Rear 1 0 Mezzanine Video USB Serial PS 2 Mouse PS 2 Keyboard Ethernet F R Hard Disk SCSI optional Compact Flash Floppy 1 0 Reset Button Various combinations of mezzanine options are possible F R Front or Rear Video PCI video controller ATI Mobility M with 4MB video memory Support CRT with resolution up to 1600 x 1200 65K colors USB USB 1 1 compliant Serial COM1 RS232 COM2 configurable as RS 232 RS 422 485 Ethernet 10 Base T 100 Base Intel82551er on faceplate and Two 10 Base T 100 Base 1000 Base T Intel 82544GC on rear 1 0 optional Gigabit Ethernet ports available on PMC Hard Disk PCI EIDE Ultra DMA 100 Rear 1 0 Channel 1 Onboard Channel 0 SCSI Dual Channel Ultra 160 320 SCSI LVD SE based on LSI 53C10XXX using PMC BP e Ul UJ 5 CompactFlash Can be installed on EIDE channel 0 through the onboard connector Clock Calenda
22. B Interrupt Lines Appendix Kontron Extension Registers Appendix D Board Diagrams Appendix E Connector Pinout Appendix F BIOS Setup Error Codes Appendix G BIOS Update amp Emergency Procedure Appendix H Getting Help Customer Comments If you have any difficulties using this user s guide discover an error or just want to provide some feedback please send a message to Tech Writer ca kontron com Detail any errors you find We will correct the errors or problems as soon as possible and post the revised user s guide in our Web site Thank you Advisory Conventions Seven types of advisories are used throughout the user guides to provide helpful information or to alert you to the potential for hardware damage or personal injury They are Note Signal Paths Related Jumpers BIOS Settings Software Usage Cautions and Warnings The following is an example of each type of advisory Use caution when servicing electrical components Note ed Indicate information that is important for you to know Signal Paths Indicate the places where you can fin the signal on the board dd Related Jumpers audi Indicate the jumpers that are related to this sections mr BIOS Settings 1101 jui Indicate where you can set this option in the BIOS lt Software Usage Indicates how can access this feature through software CAUTION A Indicate potential damage to hardware and tells you how to avoid
23. Displays a Status and 12V gt Misc limits setin other menu 1 05V Chipset amp CPU Displays a Status and Vbat gt Battery RTC limits set in other menu Vin 12V Vin 12V Vin 1 05V Displays a Status and Vhat limits set in other menu 5 15 5 1 2 5 8 3 Control Temperature Events Feature CPU Temperature Interrupt Resume Alarm oC Overheat Alarm oC On Demand TCC Duty Cycle Enabled Disabled 10 to 70 C in 4 C increment 30 to 90 C in 4 C increment Disabled 12 5 25 0 37 5 50 0 62 5 75 0 87 5 5 1 2 5 8 4 Control Voltage Events Feature Vin 1 25V Voltage Interrupt Vin 3 3V Voltage Interrupt Vin 5V Voltage Interrupt Vin 12V Voltage Interrupt Vin 12V Voltage Interrupt Vin 1 05V Voltage Interrupt Vbat Voltage Interrupt Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Description This option enables Temperature events handling Full speed Normal mode will be resumed when the temperature comes down to the selected temperature The CPU will be slowed down Doze mode when it reaches the selected temperature This is the period in which the clock is running Note that Automatic TCC has precedence if both Automatic and On Demand TCC are enabled Exemple If 12 5 is selected the clock will run 12 5 of the overall time Description This option enab
24. Other DEVIS 5 21 53 Console Redirection VT100 Mode 5 22 5 3 1 n tu 5 22 5 3 2 Setup amp Configuration eu ERE Dua ERO EUG 5 22 5 3 3 Running Without a Terminal 5 23 A Memory 1 0 Maps A 1 MEMORY MAPPING sv A 1 A 2 T O T A 2 B Interrupt Lines B 1 RO EET 1 B 2 1 C Kontron Extension Registers C 1 FPGA CPLD Registers Definition 44222 04 0 eene nennen C 1 C 2 tice eo C 2 C 3 0190h COM2 RS232 422 485 Buffer Control C 3 4 19102 Reset HITSEOTV zs C 3 C 5 0192h Bracket Switch Blue LED C 3 09109 do iy de etes C 3 C 7 0196h z Watchdog Coritrol 3 decd edo C4 C 8 0197m ed uad ve 4 C 9 0199h PCI device enable Jumper configuration 4 ee Tos n C 5 11 019Bh Backplane Information erue puo
25. PCI Performance settings gt PLX6540 HB8 related options 2 7 2 Hot Swap 2 7 2 1 Power Ramping and Overcurrent Protection This product has electrical components that control current ramp up on the board when the board is hot swapped in the chassis Current transient upon insertion follows the PICMG2 1R2 0 specification The hot swap circuit also protects from overcurrent If for any reason current requirements increase to an abnormal level the board will shut down Power cycling or board select BDSEL signal cycling restarts the board 2 7 2 2 Hardware onnection Process Ifyou would like more information please see Section 1 5 4 for technical background This section explains how to use the ENUM signal When the board is used in a system slot it is possible to detect insertion and pending extraction of a compliant peripheral cPCI card WARNING 1 Some mechanical parts of the guide rail are fragile shield contacts and clips Do not use force to insert and connect a CompactPCI module 2 If there is any mechanical resistance while you insert a module ensure there is no mechanical obstacle and verify that all parts are well aligned 2 13 2 7 3 Bus Mode The PICMG2 0R3 0 specification and PICMG2 1R2 0 specification do not dictate how to support a PCI X card This product implements a solution that is the best candidate for the next revision of this specification Bus speed negotiation is always done on a PCI reset Inse
26. ROM Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enables Disables Onboard Gigabit Ethernet Controller 182544 on Bus B Device 00 Initialize device expansion ROM Enables Disables Onboard Gigabit Ethernet Controller 182544 on Bus B Device 01 Initialize device expansion ROM Enables Disables Onboard 10 100 Ethernet Controller 182551 on Bus D Device 06 Initialize device expansion ROM 5 9 5 1 2 5 2 2 On board PMC Expansion Feature On board PMC A Expansion Slot Option ROM scan Latency Timer On board PMC B Expansion Slot Option ROM scan Latency Timer Enabled Disabled Default 0020h 0040h 0060h 0080h 00 OOCOh or OOEOh Enabled Disabled Default 0020h 0040h 0060h 0080h 00 OOCOh or OOEOh Description Initialize device expansion ROM Minimum guaranteed time slice allotted for bus master in units of PCI bus clocks Initialize device expansion ROM Minimum guaranteed time slice allotted for bus master in units of PCI bus clocks 5 10 5 1 2 5 2 3 PCI Performance settings Feature Options Description Set the Cache Line Size in DWORDS 0 1 2 4 8or 16 PCI Cache Line Size Sets the Cache Line Size Register in the Configuration Space DWORDS of PCI devices Onboard HB8 PCI X Title for next options Bridge settings Disabled Both 32 bit P
27. Send us an e mail at RMA ca kontron com In the e mail you must include your name your company name your address your city your postal zip code your phone number and your e mail You must also include the serial number of the defective product and a description of the problem When returning a unit i In the box you have to include the name and telephone number of a person whom we can contact for further explanations if necessary when returning goods Where applicable always include all duty papers and invoice s associated with the item s in question ii Ensure that the unit is properly packed Pack it in a rigid cardboard box iti Clearly write or mark the RMA number on the outside of the package you are returning iv Ship prepaid We take care of insuring incoming units Kontron Canada Inc 616 Cur Boivin Boisbriand Qu bec J7G 2A7 Canada G 2 G kontron always a Jump ahead Contact Name Company Name Street Address City Return to Manufacturer Authorization Request Province State Country Postal Zip Code Phone Number Extension Fax Number E Mail P O Serial Number Failure or Problem Description if not under warranty Kontron Canada Inc 616 Cur Boivin Boisbriand Qu bec Canada J7G 2A7 Fax this form to Kontron s Technical Support department in Canada at 450 437 8053 G 3
28. Sets the base 1 0 address for serial port 2E8 Interrupt Sets the interrupt for serial port B RS 422 Mode RS 485 Set the mode for Serial Port B RS 232 E Enabled oppy Dis 5 Controller Disabled Enables the Floppy Disk Controller Auto 5 1 2 5 4 Advanced Chipset Control Feature Description Disabled If enabled BIOS will initialize ECC ECC This will lengthen POST time execution ECC Config 5 12 5 1 2 5 5 Console Redirection Feature Options Description C Disabled If enabled Console Redirection works without the VT100 jumper to use the console Redirection Redirection Enabled This option is only used when jumper is not present If enabled it will use a port on the motherboard Com Port On board COMA s 3 ME On Board COMB Install the VT100 jumper to use the Console Redirection using the selected port 300 1200 2400 9600 Baud Rate 19 2K 38 4K 57 6K Enables the specified baud rate 115 2K Parity Fix setting No Parity Data Bits Fix setting 8 Data Bits Stop Bit s Fix setting 1 Stop Bit VT100 VT100 8bit PC ANSI 7bit Console d Enables the specified console type m PC ANSI j VT100 VT UTF8 None Flow Control XON XOFF Enables Flow Control CTS RTS Continue CR Off On Enables Console Redirection after OS has loaded after POST 5 1 2 5 6 Advanced Processor 0ptions Feature Speed Step Support POM BOM Description BOM Battery Optimiz
29. density disks Signal Paths The floppy disk controller interface is available through the J5 connector Bios Settings 01013 Main gt Legacy Diskette A Advanced gt On board Device Configuration gt Floppy Disk Controller 2 4 2 5 2 Keyboard PS 2 Mouse Interface The onboard keyboard controller is compatible with 8042 software Signal Paths un PS 2 keyboard and PS 2 mouse signals are available through the J3 CPCI 1 0 connector Keyboard J3 Row E pin 2 3 See appendix for complete pinout description of J3 Mouse J3 Row E pin 4 5 x Bios Settings Eh Advanced gt Boot Settings Configuration gt PS 2 Mouse 2 5 2 4 3 Serial Ports Two fully functional serial ports are provided on the board for asynchronous serial communications They are 16 550 high speed UART compatible and support 16 byte FIFO buffers for transfer rates from 50bps to 115Kbps Each serial port is specified as follows Designation Communication Mode Output Path Serial Port A COM1 RS 232 Front Plate 45 210 CPCI 33 Serial Port 0 2 RS 232 RS422 RS485 CPCI J3 UART registers are individually addressable and fully programmable 2 4 3 1 Serial Port 1 J10 Serial Port 1 is buffered directly for RS 232 operation Signals include the complete signal set for handshaking modem control interrupt generation and data transfer When assigned as Serial Port 1 the port is 100 compatible with the IBM AT serial port i
30. enables or disables 32 bit IDE data transfers Transfer Mode Choices are Standard Fast PIO 1 Fast PIO 2 Fast PIO 3 Fast PIO 4 FPIO 3 DMA 1 FPIO 4 DMA2 Select the method for moving data to from the drive Autotype the drive to select the optimum transfer mode Ultra DMA Mode Choices are Disabled Mode 0 to 5 Select the Ultra DMA mode used for moving data to from the drive Autotype the drive to select the optimum transfer mode SMART Monitoring IDE Failure Prediction BIOS auto detects the hard disk installed Same as Primary Master Pauses and displays SETUP entry or resumes boot prompt if error occurs on boot If disabled system always attempts to boot Displays amount of conventional memory detected during boot up Displays the amount of RAM memory detected during boot up minus the base memory 1 Mbyte 5 6 5 1 2 5 Advanced Menu Selection You can make the following selections on the Advanced Menu Use the sub menus for other selections Feature Options Description Boot Settings This is a Sub Menu Additional set to configure boot setti Configuration itional setup menus to configure boot settings Pa This is a Sub Menu Additional set to configure PCI devi Configuration itional setup menus to configure evices On Board Device This is a Sub Menu Peripheral Configuration Configuration Advanced This is Sub Menu Select options for Advanced Chipset features Chipset Control Console This
31. from the BI0S Monitoring Menu to reconfigure IDE LED activity as IPMI communication LED The meaning ofthe blink pattern is explained within the table below IPMI LED Led Color GREEN Normal status SLOW BLINKING Fast 8 x 150 msec ON 50 msec OFF Slow Fast 250 msec ON 8 x 150 msec ON 3 sec OFF 50 msec OFF Slow Blinking speed 100 msec ON 1 4 sec OFF Management Controller request attention to SMS Send The Management Send this may occur Receive data Controller is running Receive data when there is through the normally it s an through the KCS message waiting for interface heart beat interface the SMS Signification x Bios Settings Monitoring gt Activity Led 2 23 2 9 Debugging Features 2 9 1 Bi color Debug LED BLUE USER LED The board has a bi color LED that is very useful to debug Consult the quick reference sheet The significance of the LED is context dependent and is shown below Time LED usage Misconnection on PMC VIO jumper Both red LEDs will light During reset Blue LED is ON After reset during the boot process Postcode blinker blinking After the boot process while the GREEN RED is not used operating system loads GREEN and RED is not used While the application software runs Application software uses the LED to display status information ff Software Usage M See register 0x19A description in Appendix C for details
32. if you replace the battery incorrectly Replace the battery with the same or equivalent type recommended by the manufacturer Dispose of used batteries according to the manufacturer s instructions 3 5 1 Operation and Preventative Maintenance The operational battery voltage must be between 2 9 and 3 6 volts When the board is stored and is kept in it s original package the battery must be replaced when the battery voltage is below 2 9 volts For preventive operational maintenance we recommend to verify the battery voltage after 4 years After that period we recommend that the safety voltage is checked more often The normal battery life expectancy depends on the utilisation of the board e Kontron ordering MRP 100 001 e Tadiran ordering 15 51 86 420 007 TL 5186 3 7 3 6 Board Hot Swap and Installation Because of the high density pinout of the hard metric connector some precautions must be taken when connecting or disconnecting a board to from a backplane 1 2 3 4 lt A A Rail guides must be installed on the enclosure to slide the board to the backplane Do not force the board if there is mechanical resistance while inserting the board Screw the frontplate to the enclosure to firmly attach the board to its enclosure Use extractor handles to disconnect and extract the board from its enclosure Note Hot swap of the CP6011 in a system slot is not defined This results in a cold start of the syste
33. isa Sub Menu Additional setup menus to configure console Redirection Advanced Processor This is a Sub Menu Select options for Advanced Processor specific options Options 5 7 5 1 2 5 1 Boot Settings Configuration Feature 0ptions Description Other General Settings Other Win2000 Specific Settings Installed 0 S Win2000 Note An incorrect setting can cause some operating systems to display unexpected behavior Yes Enable Disable ACPI BIOS Advance Configuration and Power Interface Da ton No Select Yes if you want to clear the Extended System d Yes Configuration Data ESCD area Boot time Enabled Displays the Diagnostic Screen during Boot Diagnostic 5 Disabled Always Enabled when Console Redirection is activated Screen Extended Norma Determines which type of test will be performed on extended Just zero it Memory Testing memory above 1M None Summary Screen None Delay Delay to display the system configuration at boot time Save CMOS in Disabled Saving CMOS memory content into Flash Memory will prevent FLASH Enabled loosing CMOS options when battery fails Retry Boot Disabled Enable this option to Retry the Boot sequence until a successful Sequence Enabled boot infinite Retry Disabl Disabled prevent any installed PS 2 mouse from functioning PS 2 Mouse ce but frees up IRQ 12 Enabled forces the PS 2 mouse port to be Enabled enabled regardless if a mouse is present D
34. must be set in cable select so the onboard jumper will set the master and the slave devices CAUTION When connecting IDE devices to the Primary IDE interface Master and Slave devices must be shared in respect of the device allocation on both the compact flash connector and the mezzanine Two Master devices must not be installed on the same interface at the same time If a device is alone on an interface it shall be master 2 3 2 USB 1 1 Interfaces USB strengths include e Capability to daisy chain as many as 127 devices per interface e Fast bi directional e Isochronous asynchronous interface e 12MBPS transfer rate e Standardization of peripheral interfaces into a single format USB supports Plug and Play and hot swapping operations 05 level These features allow USB devices to be automatically attached configured and detached without reboot or running setup 2 4 Pin Signal 2 Signal Paths USBO signals are available on the faceplate from the J11 connector Both USB 1 and USB 2 signals are available through the CPCI 1 0 connector 23 roth Bios Settings tid Advanced PCI Configuration Legacy USB Support keyboard and mouse The CP6011 board supports the standard open host controller interface OHCT and uses standard software drivers that are OHCI compatible 2 4 Super 1 0 2 4 1 Floppy Disk Interface The onboard floppy disk controller is IBM PC XT AT compatible It handles 3 5 low and high
35. on this processor e Supports Intel Architecture with Dynamic Execution High performance low power core On die primary 32 kbyte instruction cache and 32 kbyte write back data cache On die up to 2 Mbyte second level cache with Advanced Transfer Cache Architecture Advanced Branch Prediction and Data Prefetch Logic Streaming SIMD Extensions 2 SSE2 400 533MHz Source Synchronous processor system bus Advanced Power Management features including Enhanced Intel SpeedStep technology Micro FCBGA packaging technologies Please call Kontron to get the available CPU speed and configuration See Intel s Web site for additional details about Pentium M architecture and instruction set 2 2 2 Chipset Feature e Processor Host Bus Support Intel Pentium processor with 1 Mbyte or 2 Mbyte of 12 cache 400 533 MHz system bus 2X address 4X data System bus Dynamic Bus Inversion DBI 36 bit system bus addressing 12 deep in order queue AGTL bus driver technology with on die termination resistors Parity protection on system bus data address request and response signals e Memory System Supports 72 bit Registered ECC DDR DIMMs Supports 256 Mb 512Mb and 1 Gb DRAM densities Cache Latency of 2 and 2 5 Dual Channel Support 144 bit wide DDR memory port with Peak memory bandwidth of 3 2 GB s Supports 2GB of double sided SODIMMs SODIMMs mu
36. order Exit Use this menu chose Exits option Use the left and right lt and gt arrows keys to make a selection 5 1 2 1 The Legend Bar Use the keys listed in the legend bar on the bottom to make your selections or exit the current menu The chart on the following page describes the legend kevs and their alternates Key Function lt F1 gt or lt Alt H gt General Help windows lt Esc gt Exit this menu lt gt arrow keys Select a different menu lt Home gt or lt End gt Move cursor to top or bottom of window lt PgUp gt or lt PgDn gt Move cursor to top or bottom of window lt F5 gt or lt gt Select the Previous Value for the field lt F6 gt or lt gt or lt Space gt Select the Next Value for the field Fo Load the Default Configuration values for all menus lt F10 gt Save and exit lt Enter gt Execute Command display possible value for this field or Select the Sub menu To select an item use the arrow keys to move the cursor to the field your want Then use the plus and minus value keys to select a value for that field To save values commands in the Exit Menu save the values currently displayed in all the menus To display a sub menu use the arrow keys to move the cursor to the sub menu your want Then press lt Enter gt A pointer gt marks all sub menus 5 1 2 2 The Field Help Window The help window on the right side of each menu displays the help text for the currently selected
37. the problem A WARNING Indicates potential for bodily harm and tells you how to avoid the problem Disclaimer We have tried to identify all situations that may pose a warning or a caution condition in this user s guide However Kontron does not claim to have covered all situations that might require the use of a Caution or a Warning Unpacking Follow these recommendations while unpacking Remove all items from the box If any items listed on the purchase order are missing notify Kontron customer service immediately Inspect the product for damage If there is damage notify Kontron customer service immediately Save the box and packing material for possible future shipment Powering Up the System Before any installation or setup ensure that the board is unplugged from power sources or subsystems If you encounter a problem verify the following items Make sure that all connectors are properly connected Verify your boot devices Ifthe system does not start properly try booting without any other 1 0 peripherals attached including Compact PCI or PMC adapters If you still cannot start your system please refer to the Emergency Procedure in the Appendix Section of this User s Guide Make sure your system provides the minimum DC voltages required at the board s slot especially if DC power is carried by cables If you are still not able to get your board running contact our Technical Support for ass
38. the supported IPMI commands within the CP6011 All these commands are compatible to IPMI v1 5 and PICMG 2 9 specification Global commands SEL Device Commands Get Device ID Get SEL Info Cold Reset Get SEL Allocation Info Get Self Test Results Get SEL Info Broadcast Get Device ID Get SEL Allocation Info Reserve SEL Get SEL Entry Set BMC Global Enables Add SEL Entry Get BMC Global Enables Delete SEL Entry Clear Message Flags Clear SEL Get Message Flags Get SEL Time Enable Message Channel Receive Set SEL Time Get Message Send Message Read Event Message Buffer Get BT Interface Capabilities Master Write Read 2 Get SDR Repository Info Get SDR Repository Allocation Info Reserve SDR Repository Reset Watchdog Timer Get SDR Set Watchdog Timer Partial Add SDR Get Watchdog Timer Delete SDR Clear SDR Repository FRU Inventory Device Run Initialization Agent OEM Command Get FRU Inventory Area Info Get Init Agent Last Error Read FRU Inventory Data Write FRU Inventory Data Event Commands Set Event Receiver Get Event Receiver Platform Event Sensor Device Get Device SDR Info Get Device SDR Reserve Device SDR Repository Set Sensor Hysteresis Get Sensor Hysteresis Set Sensor Threshold Get Sensor Threshold Set Sensor Event Enable Get Sensor Event Enable Get Sensor Reading PICMG IPMI extension Set FRU LED State Get FRU LED State Get FRU LED Properties Get LED Color Capabilities 2 8 2 3 Sensors Implement
39. which of the LEDs if any are under control of the IPM Controller The CP6011 only support control of BLUE hot swap LED NetFn Group Extension request LUN Command ID cPCI ID Extension FRU Device ID NetFn Group Extension response LUN Response command Q Command ID 05 Completion code 00 cPCI ID Extension 00 General Status LED Properties 01 Response A bit field indicating the FRU s ability to control the LEDs 7 4 reserved set to 0 3 1 unused set to 0 0 1b BLUE LED Application Specific LED Count None for CP6011 e Get LED Color Capabilities The Get LED Color Capabilities command allows SMS interrogation of the colors supported by each LED This command is used to determine the valid set of colors prior to issuing a Set FRU LED State command The CP6011 only support BLUE color for BLUE hot swap LED NetFn Group Extension request LUN Command ID cPCI ID Extension FRU Device ID LED ID 00h BLUE Hot swap LED NetFn Group Extension response LUN Command ID 06 Completion code 00 cPCI ID Extension 00 LED Color Capabilities 01 A bit field When the bit set the LED supports the color Bit LED 7 Reserved shall be set to 0 6 2 unused for CP6011 Response 1 LED supports BLUE command 0 Reserved shall be set to 0 6 Default LED Color in Local 01 Control State Bits number 7 4 Reserved shall be set to 0 3 0 Hex Value Funct
40. with the found SDRs The factory default repository contains only the local board SDRs Intelligent Platform Management Bus The dedicated 126 management bus where SMC communicate with the BMC Keyboard Controller Style This is the IPMI mandatory interface on the host system to communicate with the BMC Field Replaceable Units inventory Data A FRU inventory data is available in all management controller The FRU contains information about the product such as the part number and the serial number See PICMG Specification 2 9 for complete details on the FRU inventory data byte structure A Kontron utility named Fillsf exe is provided to update the FRU inventory data System Management Software This is the generic term for the high level software that perform all management task The SAF Hardware Platform Interface provides an industry standard interface to monitor and control highly available telecommunications system platforms The ability to monitor and control these platforms is provided through a consistent and standard set of programmatic interfaces HPI provides the interface between the SMS and IPMI allowing portability of SMS across many different hardware platforms and portability of hardware platforms across many different SMS The Platform Management Module is in charge of performing all management actions from chassis point of view From hardware perspective it is the BMC within the system that collect all events coming from
41. 0x193 WRITE NU IDCHIP NU IDCHIP ID Chip serial number control Open drain output with pin readback 7 0196H WATCHDOG CONTROL This 15 a Kontron SBC standard dual stage watchdog However the second stage time increases from 1ms to 16ms to ease the interrupt handling when using ISA interrupt So either a NMI ora legacy interrupt will generate after the specified timeout Then the watchdog must be triggered either by writing the WDD 2 0 bits or by clearing the interrupt bit in the 1A2h register Failure to trigger the watchdog within 16ms will reset the system If interrupts are disabled the watchdog reverts to a single stage one Address Action D7 D6 D5 D4 READ WDEN WDD2 WDD1 WDD0 0x196 WRITE WDEN WDD2 WDD1 WDD0 WDEN Enable Lockable with bit LOCK WDD 2 0 Timeout selection A write to this register triggers the watchdog Timeout as follow 000 0 016s 001 0 065s 010 0 262s 011 1 0485 100 4 1945 101 16 785 110 67 115 111 268 45 C 8 0197 NMI CONTROL Address Action D4 D3 D2 D1 DO READ NU SWNMIEN SWNMIEN WDNMIEN WDNMI 0x197 WRITE NU SWNMIEN NU WDNMIEN NU WDNMI Watchdog NMI occur when 1 WDNMIEN Enable NMI on watchdog timer when 1 SWNMI Front Panel Switch NMI occur when 1 SWNMIEN Enable NMI on CPCI SWITCH when 1 C 9 0199H PCI DEVICE ENABLE amp JUMPER CONFIGURATION Address Action D7 D6 D5 D4 D3 READ VGA_EN VT100 BSPD BSPD BSPD 0x197 WRITE NU NU NU NU NU VGA_EN Read jumper for V
42. 1 3 5 Phoenix Multiboot Phoenix Multiboot expands your boot options by letting you choose your boot device which could be a hard disk floppy disk CDROM Flash Disk SCSI or LAN You can select your boot device in Setup or you can choose a different device each time you boot during POST by selecting your boot device in The Boot First Menu ESC key Multiboot consists of The Setup Boot Menu The Boot First Menu 5 2 Installing Drivers 5 2 1 Video Drivers Various drivers are provided for different operating systems and software To install a driver refer to the Setup program located on the CD ROM provided with your board 5 2 2 Ethernet Drivers Various drivers are provided for different operating systems and software To install a driver use the Setup program and the ReadMe bat file located on the CD ROM provided with your board 5 2 3 Other Drivers For other operating system drivers and installation instructions or for more information visit our Web site at www kontron com or our FTP site at ftp kontron ca support or you may also contact Kontron s Technical Support department 5 21 5 3 Console Redirection VT100 Mode The VT100 operating mode allows remote setups ofthe board This configuration requires a remote terminal that must be connected to the board through a serial communication link 5 3 1 Requirements The terminal should emulate a VT100 or ANSI terminal Terminal emulation programs such as Telix or Proc
43. 1 6 qa u 1 6 dean 1 6 1 5 3 Hot swap compatibility with Kontron s systems 1 7 1 5 4 Fullhotswap mechanism 1 8 1 5 5 High Availability mechanism 1 9 16 Interfacing with the Environment 1 9 1 0 1 GPCIN 1 9 1 6 2 RTM rear transition module 1 10 aa E Se dc i E Ea ei 1 10 1 7 Compatibility with Kontron Products 1 11 2 Onboard Fedtlf 2 0 2 1 BLOCK 2 1 2 2 System eee 2 2 22 1 IPIOCBSSOPS RR 2 2 22 2 ua 2 2 2 2 3 Memory Interface onse ete 2 3 2 9 TGS AND 2 4 2 3 1 Enltanced IDE od eto vases 2 4 2 3 2 tin VO 2 4 2 4 npa 2 5 2 4 1 Floppy Disk Interface v eet t ine kh Rude 2 5 2 4 2 PS 2 Keyboar
44. 100 133MHz for interleave operation to match the bandwidth of the CPU front side bus The memory controller is optimized for applications that use huge amounts of memory and have the following high end feature 2 2 3 1 Memory scrubbing This feature allows the E7501 to automatically correct ECC errors and write back the good data into memory without the CPU intervening This is done in hardware 2 3 2 3 ICH3 S 2 3 1 Enhanced IDE Interfaces EIDE interface is part of the ICH3 S south bridge The interface conforms to the ATA specification and support ATA100 for 100MB s burst transfer The board features two channel Bus Master PCI EIDE dedicated to Primary and Secondary IDE logical interfaces Secondary Channelis available only through the Rear Transition Module Each channel supports up to two IDE devices including CD ROMs hard disks and CompactFlash with independent timings in Master Slave combination Signal Paths 0 The primary IDE Interface is available through the compact flash or through the Mezzanine connector The secondary IDE interface is only available through the CPCI I 0 connector Bios Settings iuis Main Specify disk type Advanced gt PCI Configuration gt IDE Device 31 Function 1 Enabled or disabled the IDE controller The IDE interfaces supports PIO mode 4 transfers up to 16 6MB sec and Bus Master IDE transfer up to 100MB sec Ultra DMA 100 Note Devices connected to IDE0
45. 4AD14 P64M66EN P64AD8 P64AD7 VCC3 N C N C GND P64ACK64 GND Active Low N C GND N C N C VCC3 BMODE3 BMODE4 GND P64AD29 P64AD26 VCC3 P64AD23 P64AD20 GND P64C BE2 N C VCC3 P64STOPH GND P64SERR GND P64AD13 P64AD10 VCC3 N C N C GND N C N C 0 18 JNA3 amp JNB3 JNA3 amp JNB3 GND P64C BE7 P64C BE6 6 P64C BE5 P64C BE4 GND VIO P64PAR64 P64AD63 P64AD62 P64AD61 GND GND P64AD60 P64AD59 P64AD58 P64AD57 GND VIO P64AD56 P64AD55 P64AD54 P64AD53 GND GND P64AD52 P64AD51 P64AD50 P64AD49 GND GND P64AD48 P64AD47 P64AD46 P64AD45 GND VCC3 P64AD44 P64AD43 P64AD42 P64AD41 GND GND P64AD40 P64AD39 P64AD38 P64AD37 GND GND P64AD36 P64AD35 P64AD34 P64AD33 GND VIO P64AD32 N C N C N C GND N C Active Low D 13 0 19 2 4 PIM JN4A Active Low D 14 1 1 1 BIOS Setup Error Codes POST BEEP Recoverable POST Errors Whenever a recoverable error occurs during POST Phoenix BIOS displays an error message describing the problem Phoenix BIOS also issues a beep code one long tone followed by two short tones during POST if the video configuration fails no card installed or faulty or if an external ROM module does not properly checksum to zero An external ROM module e g VGA can also issue audible errors usually consisting of one long tone followed by a series of short tones Term
46. ESET RSV Active Low D 13 RESET SWITCH SW1 Active Low Signal D 9 D 14 CMOS BATTERY BACKUP CONNECTOR 1 Battery Battery CS1 DMACK DMARQ PDIAG 015 VCC GND RESET CSEL Al AO DO D1 D2 IOCS16 Active Low Signal D 10 0 16 JNA1 amp JNB1 JNA1 amp JNB1 N C GND INTB 64 BUSMODE1 INTD_P64PMC GND CLK66_PMC GND P64REQ VIO P64AD28 P64AD25 GND P64AD22 P64AD19 VIO P64FRAME GND P64DEVSEL PCIXCAP GND RSV P64PAR VIO P64AD12 AD9 GND P64AD6 P64AD4 VIO P64AD2 P64ADO GND Active Low 12V INTA P64PMCH INTC_P64PMC vcc N C VCC3E GND P64GNT _PMC vcc P64AD31 P64AD27 GND P64C BE 3 P64AD21 vcc P64AD17 GND P64IRDY vcc P64LOCK SBO GND P64AD15 P64AD11 vcc P64C CBEOH P64AD5 GND P64AD3 P64AD1 vcc P64REQ64 0 17 JNA2 amp JNB2 PMC JNA2 amp JNB2 12V RSV RSV GND N C BMODE2 PCIRST VCC3 N C P64AD30 GND P64AD24 IDSEL PMC VCC3 P64AD18 P64AD16 GND 64 GND P64PERR VCC3 P64C BE1 P6
47. GA enable VT100 Read jumper for VT100 BSPD CPCI Maximal speed 10 019AH USER LED CONTROL Address 0x19C Action READ WRITE LB_S1 LB_S1 LB_SO LB_SO LB_G LB_G LB_R LB_R LA_S1 LA_S1 LA_SO LS_SO LA_G LA_G LA_R Control red component of user led Led is on when this bit is set to 1 LA G Control green component of user led A Led is on when this bitis setto 1 SA S 0 1 Mode selection for user led A LB R Control red component of user led B Led is on when this bit is set to 1 LB G Control green component of user led B Led is on when this bit is set to 1 SB S 0 1 Mode selection for user led B S 0 1 Led Mode 00 IDE activity 01 BMC debug LED 10 Post Code debug LED 11 User control LA R LA R C 11 019BH BACKPLANE INFORMATION Address READ ST S 019Bh WRITE NU State of hardware pins GA 4 0 ST 2 0 Action D7 2 Geographical address Segment type As defined in PICMG2 0R3 0 ECR 2 000 Nominal left 001 Nominal right 111 Backplane do not provide segment type other reserved 12 019CH BMC CONTROL Address 0x19C TEST If set the SBC is inserted in a CPCI test backplane This is used for Kontron test platform Not used by SMB BMC_2EXT When 1 The BMC com port is routed to COM2 buffer BMC_COM When 1 the SIO is connected to BMC When 0 the SIO is connected to output buffer This bit is ignored if BMC_TAKE_COM 1 BMC_RST When 1 re
48. GC controllers reside on the PCI X bus and run at 133MHz without PMC B and is 64 bit wide Each interface supports 10Base T 100Base TX 1000Base T with auto negotiation and automatic crossover cable detection in rear access The Ethernet Intel 82551er controller resides on the PCI bus D and runs at 33MHz at 32 bit wide this interface support 10Base T 100Base TX with auto negotiation in front access The 1825446 features high performance with TCP IP and UDP IP checksum offloading for IPv4 and IPv6 packet filtering and jumbo frame up to 16K The CP6011 has boot from LAN capability PXE on the 3 ports Enable the option from the BIOS Set up Program Please refer to Section 5 1 PHOENIX BIOS Set up Program See Kontron s Web site http www kontron com for the latest drivers See Intel s Web site http www intel com for the latest drivers for the 1825446 and for additional information on the Ethernet controller Pin Signal 10 100 1 2 3 4 5 6 7 8 2 8 2 4 4 1 Signal Paths The Ethernet Management RJ45 connector is on the faceplate and the two other LAN connectors are available on rear access BIOS Settings Advanced gt PCI Configuration gt On board Ethernet Controller CPCI 1 0 Configuration In rear access or 2 16 configuration the two Gig Ethernet ports are available from a RTM orina PICMG2 16 system A CAUTION 1 2 When using a PICMG 2 16 system LAN cannot be us
49. O FD DIR FD TRKO FD DSKCHG IDE1 D6 IDE1 D4 IDE1 D2 IDE1 DO IDE1 1OR RSV IDE1 A2 IDE1 ACT ROW B GND RSV GND RSV GND RSV GND RSV GND FD MSEN1 FD INDEX FD MTR1 FD WGATE FD HDSEL IDE1 D8 IDE1 D10 IDE1 D12 IDE1 D14 IDE1 10W IDE1 IRQ IDE1 A0 IDE1 CS3 ROW D 7 E S E i GN RSV FD FDEDIN FD DSELO FD WDATA FD RDATA IDE1 D7 IDE1 D5 IDE1 D3 IDE1 D1 IDE1 REQ IDE1 ACK IDE1 A1 IDE1 CSO Sole s GN RSV FD DENSEL DSEL1 FD STEPH FD WRPROT IDE1 RESET IDE1 D9 IDE1 D11 IDE1 D13 IDE1 D15 IDE1 IORDY IDE1 PDIAG BATT D 8 SERIAL PORT 1 RS 232 210 These two LEDs might be reversed 1 2 3 4 5 6 7 8 0 11 HOTSWAP SWITCH 113 VCC3E 1 m SW_OPEN 2 H N SW_CLOSE 3 Active Low Signal 0 12 IDE MEZZANINE 214 P64GNT _MEZ2 IPMBO_SDA GND IPMBO_SCL CLK66_MEZ 6 GND VCC CLK66_PMC_8HP P64REQ MEZ GND 646 MEZ INTB_P64MEZZ INT_BRDG_MEZ INTA_P64MEZZ INTD_P64MEZZ MEZZ_ENUM INTC_P64MEZZ IDEO MS SLV P64REQ MEZ2 IDEO ACT IDEO CS14 GND IDEO DA2 IDEO CSO GND IDEO DAO IDEO PDIAG GND IDEO DA1 IDEO IRQ GND IDEO DMACK IDEO IORDY GND IDEO IOR IDEO IOW BD_SEL_MEZZ IDEO DMARQ IDEO DO HEALTHY _BP IDEO D1 IDEO D15 RSV IDEO D14 IDEO D2 RSV IDEO D3 IDEO D13 RSV IDEO D12 IDEO D4 RSV IDEO D5 IDEO D11 RSV IDEO D10 IDEO D6 RSV IDEO D7 IDEO D9 RSV IDEO D8 IDE R
50. PIC and DMA Initialize Memory type Initialize Memory size Shadow Boot Block System memory test Initialize interrupt vectors Initialize Run Time Clock Initialize video Initialize System Management Mode Output one beep before boot Boot to Mini DOS Clear Huge Segment Boot to Full DOS Test SIO Clock Validity Check TEST Jumper for POST to COM see Extension Registers Reset System for Erratas Hyper Threading Early Boot Block Initialize completed E 2 POST MESSAGES During the Power On Self Test POST if the BIOS detects an error requiring you to do something to fix it will either sound a beep code or display a message If a message is displayed it will be accompanied by PRESS F1 TO CONTINUE DEL TO ENTER SETUP E 6 3 ERROR MESSAGES One or more of the following messages may be displayed if the BIOS detects an error during the POST CMOS BATTERY HAS FAILED 1 Ifitis the first boot check if the battery is installed properly 2 CMOS battery is no longer functional It should be replaced Consult the Intelligent System Monitoring in BIOS Setup to verify Vbat value CMOS CHECKSUM ERROR Checksum of CMOS is incorrect This indicates that CMOS has become corrupt This error may have been caused by a weak battery Check the battery and replace if necessary OPERATING SYSTEM NOT FOUND No boot device was found This could mean either a boot drive was not detected or the drive does not contain proper system boot fil
51. RSV RSV RX TX RSV RSV RSV 2 4 3 2 1 RS 232 Protocol When configured for RS 232 operation mode the serial port is 100 compatible with the IBM AT serial port signals 2 4 3 2 2 RS 422 Protocol The RS 422 protocol Full Duplex uses both RX and TX lines during a communication session CAUTION A In RS 422 mode install W4 and W5 jumper caps to connect the 120 Ohm A termination resistors See the Jumper Settings section 2 7 2 4 3 2 3 85 485 Protocol The RS 485 protocol Half Duplex also uses differential signals during communication session It differs from the RS 422 mode because it offers the ability to transmit and receive over the same pair of wires and allows a shared communication line by multiple stations This configuration also known as Party Line allows only one system to take control of the communication line at a time In RS 485 mode the RX lines are used as the transceiver lines and the RTS signal controls the direction of the RS 485 buffer When set for RS 485 mode in the BIOS upon power up or reset the transceiver is by default in receiver mode to prevent unwanted perturbation on the line Party line operation mode requires termination resistors to be installed at both ends of the network CAUTION A When installing the board at one end of the network connect the W4 and W5 A jumper caps at the 120 ohms termination resistors See Setting Jumpers 2 4 4 Ethernet Interfaces The 2 Ethernet Intel 82544
52. Stations Controller RNC SGSN GGSN SCP HLR VLR billing and wireless access gateway datacom applications database management routing devices medical applications diagnosis as well as industrial and military applications 1 2 What s Included This board is shipped with the following items One Quick Reference Sheet One CD ROM containing drivers One CP6011 board Cables that have been ordered If any item is missing or damaged contact the supplier 1 3 Board Specifications Single Pentium M Processor at 400 533 MHz front side bus FSB up to 2 0GHz Supported and future speeds as they become available Microprocessors Passive heatsink 1M L2 on die cache 1 6GHz 2M L2 on die cache 1 8GHz 2 0GHz Intel E7501 MCH and south bridge Intel s ICH3 S Chipset Front Side Bus 400 533 MHz 64 bit Large 1 0 bandwidth Two 64 bit 133MHz PCI X bus plus one 32 bit 33MHz bus Front side bus at 400 533 MHz 64 bit data 32 bit address Memory bus at 200 266 MHz 144 bit data 2 channel Two onboard 64 bit 133MHz PCI X bus Cache Memory Bus Interface CPCI PCI X 64 bit 133MHz with universal bridge 3 3V or 5V are available see available options One onboard 32 bit 33MHz bus for video interface and LAN management port PCI X 64 bit 133MHz with universal bridge board can operate and access the 1 system slot or peripheral slot or be isolated from the cPCI bus in any slot drone mode Slot A
53. U NU NU 0x19F NU NU NU NU NU NU NU 0 19 0x1A0 NU NU NU NU ENUM_EN 0x1A0 NU NU NU NU ENUM_EN 0 1 1 0 1 1 Ox1A2 NU NU NU NU 0x1A3 NU NU NU NU NU 0x1A3 NU NU NU NU NU 0 1 4 0 1 4 C 3 0190H COM2 RS232 422 485 BUFFER CONTROL Address Action D7 D4 D3 D2 READ NU RS485 RS232 ST1 0x190 WRITE NU RS485 RS232 ST1 RS485 RS232 Description RS232 mode default RS485 422 point to point mode RX is always enable TX enabled when 0 2 RTS is asserted RS485 party line mode RX enabled when 2 RTS is deasserted TX enabled when 0 2 RTS is asserted Illegal This puts the buffers in RS232 mode Illegal This puts the buffers in RS232 mode This is the condition on power up Value is changed by the BIOS 1 0191H RESET HISTORY Address Action D7 D6 D5 D4 D3 D2 D1 DO READ NU NU WD0 NU NU NU NU NU 0x193 WRITE NU NU NU NU NU NU NU NU X X X X X X X X WDO Board reseted by the watchdog C 5 0192H BRACKET SWITCH BLUE LED Address Action D7 D6 D5 READ BL ST BL EN SW 0 0x192 WRITE BL ST BL EN NU BL ST Blue LED state BL EN Blue LED control enable SW 0 When 1 the bracket switch is open LOCK When 1 the enable bit of the watchdog WDEN can t be modified C 6 0193H ID CHIP Address Action D4 D3 D2 READ NU IDCHIP NU
54. anine JN1A JN4A 64 Bit PCIX Mezzanine amp PIM PCI Mezzanine JN1B JN4B 64 Bit PCIX Mezzanine 3 5 3 4 2 Front Plate Connectors and Indicators 6011 Blue User LED User LED 3 6 Description Mezzanine Ethernet Management Ready to Swap HDD Activity Reset Button Serial Port A USBO Mezzanine Comments The front plate supports a PMC cutout and a cap that also acts as an EMI shield when there is no PMC device installed Ethernet RJ 45 connectors with built in activity and link indicators Lights when the board is ready to be swapped Display POST code during boot process Indicates activity on IDE Use a small tool to press the button and proceed to a hardware reset of the board Standard 8 pin RJ 45 connector 4 Pin standard USB connector The front plate supports a PMC cutout and a cap that also acts as an EMI shield when there is no PMC device installed 3 5 Backup Battery An onboard 3 6V lithium battery is provided to back up BIOS setup values and the real time clock RTC When replacing the battery must be connected as follows 1 Place your index and thumb at each side of the battery and gently pull out the battery 2 Insert a new one firmly in place with respect to the positive and negative location of the pins Negative outer pin 3 6V Lithium Battery Positive center pin Onboard Battery Connector WARNING There is a danger of explosion
55. any SMC It is also in charge to perform the slot power reset control action From management point of view the PMM includes the SAF HPI layer that gives to SMS access to all chassis sensor control The PMM is part of Kontron XL VHDS chassis 2 15 2 8 1 2 a Compact PCI Chassis Kontron IPMI implementation in cPCI environment is compliant to the PICMG2 9R1 0 specification The specification gives the pinout of J1 and J2 as well as the addressing scheme There should be only one BMC in the chassis The BMC may reside either on an SBC blade or on an external Platform Management Module PMM the specification gives full latitude over this BMC Satellite Satellite Satellite IPMB Address IPMB Address IPMB Address IPMB Address Fix 20h Boh Satellite Satellite Satellite Satellite IPMB Address IPMB Address IPMB Address IPMB Address Beh Bah BAh Bch 1 IPMB address for satellite is determined via the location of the slot in the chassis 2 8 1 3 IPMISetup To use the IPMI resources in a system some steps are needed The system operator must perform Step 1 The SMS application performs Steps 2 and 3 2 8 2 2 8 2 1 1 2 Elect a BMC by setting the management mode to BMC in the BI0S Setup Menu By default all Kontron s CPCI blades are configured in SMC mode Fill the SDRR with all the present sensors in the chassis This step may be done using the fillsf exe Kontron utility in DOS IPMI speci
56. are reserved It is strongly recommended not to modify unused bit to insure compatibility with other product Base addresses are fixed It can be changed but no option will be supported in the BIOS setup We strongly recommend using the default base address Bits marked NU are not used on this board Writing to such bit does nothing and reading is undefined either 0 or 1 may be returned Next table present 1 0 addressee for each register Legend Unchanged stay unchanged after reset Not Defined bit not used on this board Not Used C 1 C 2 OVERVIEW FPGA CPLD registers 0x190 RS485 RS232 ST1 NU NU 0x190 RS485 RS232 ST1 NU NU 0x191 NU NU NU NU NU 0x191 NU NU NU NU NU 0x192 NU NU NU NU 0x192 NU NU NU NU 0x193 NU IDCHIP NU NU NU 0x193 NU IDCHIP NU NU NU 0x194 NU NU NU NU NU 0x194 NU NU NU NU NU 0x195 NU NU NU NU NU 0x195 NU NU NU NU NU 0x196 NU NU NU NU 0x196 NU NU NU NU 0x197 NU NU NU NU NU NU NU 0x197 NU NU NU NU NU NU NU 0x198 NU NU NU NU NU NU NU 0x198 NU NU NU NU NU NU NU 0x199 100 BSPD BSPD NU NU EN_LAN 0x199 NU NU NU NU NU NU EN_LAN 0x19A LB_S1 LB_SO LB_R LA_S1 LA_SO LA_G LA_R 0x19A LB_S1 LB_SO LB_R LA_S1 LS_SO LA_G LA_R 0x19B 5 2 ST1 GA4 GA3 GA2 GA1 GAO 0x19B NU NU NU NU NU NU NU 0x19C TEST FWH_LOCK P_COM2 BMC_2EXT BMC_COM BMC_RST BMC_PRG 0x19C NU NU P_COM2 NU BMC COM BMC RST BMC PRG 0x19D NU NU NU NU NU NU NU 0x19D NU NU NU NU NU NU NU 0 19 NU NU NU NU NU 0x19E NU NU NU NU N
57. d Ground and Reserved Pins Description Ground Reserved for Kontron internal use 4 11 5 Software Setup Contents 5 1 PHOENIX BIOS Setup Program 5 1 52 5 21 5 3 Console Redirection VT100 Mode 5 22 5 0 5 1 PHOENIX BIOS Setup Program All relevant information for operating the board and connected peripherals is stored in the CMOS memory A battery backed up memory holds this information when the board is powered off the BIOS Setup program is required to make changes to the setup 5 1 1 Accessing the BIOS setup program The system BIOS Basic Input Output System provides an interface between the operating system and the hardware of the CP6011 The CP6011 uses the Phoenix Setup program a setup utility in flash memory that is accessed by pressing the lt DELETE gt key at the appropriate time during system boot This utility is used to set configuration data in CMOS RAM To run the Phoenix Setup program incorporated in the ROM BIOS e Turn on or reboot the system e When you get the following message hit lt DELETE gt key to enter SETUP 105 4 0 Release 6 0 Copyright 1985 2002 Phoenix Technologies Ltd All Rights Reserved KONTRON CP6011 BIOS Version 2 4 The main menu of the Phoenix BIOS CMOS Setup Utility appears on the screen Advanced Monitoring Boot Exit Item Specif
58. d PS 2 Mouse Interface 2 5 2 4 3 5 POTES uA Ee T 2 6 2 4 4 Ethernet Interfaces a 2 2 5 System Management Features 2 10 2 5 1 Thermal Management 2 10 2 5 2 Power Supply Monitoring 2 10 2 5 3 Programmable Dual Stage Watchdog 2 11 2 6 Vid o 2 11 2 6 1 Supported Resolutions 2 12 2 6 2 Major Features Description 2 12 2 1 XPCLEGaIUEBS 2 12 2 7 1 Universal Bridge PLX6540 2 12 27222 pa Q Qa 2 13 CBS MOUS 2 14 2 94 APME d Feb 2 14 2 8 1 TechmicalBackground cert ee 2 14 2 8 2 Implementation of CP6011 2 16 2 8 3 u iaa 2 19 28 4 Software TE CPU pr 2 22 2 8 5 IPMI Communication EED
59. de Control Primary Master Type CD ROM Ultra DMA Mode SMART Monitoring SMART Monitoring Display type of Monitoring This field is a Display Only This option can be changed in the Advanced Menu ATAPI Removable Same choices as CD ROM 5 5 Main Menu Selection continued Feature Primary Master Continued Primary Slave Secondary Master Secondary Slave POST Errors System Memory Extended Memory Options Description IDE Removable Same choices as CD ROM Other ATAPI Same choices as CD ROM Type continu ed USER Same as Primary Master Same as Primary Master Enabled Disabled N A N A Cylinders Heads Sectors Maximum Capacity Multi Sector Transfers LBA mode Control 32 Bit 1 0 Transfer Mode Ultra DMA Mode SMART Monitoring Cylinders Set the number of cylinders Heads Set the number of heads Choices are 1 to 16 Sectors Set the number of sectors per track Maximum Capacity Maximum capacity is displayed according to the cylinders heads and sectors selected Multi Sector Transfers Choices are Disabled 2 4 8 and 16 sectors Specify the number of sectors per block for multiple sector transfers MAX refers to the size the disk returns when queried LBA Mode Control Choices are Enabled Disabled Enabling LBA cause Logical Block Addressing to be used in place of Cylinders Heads and Sectors 32 BitI O Choices are Enabled Disabled This setting
60. e the two SO DIMM shall be different Insert the SO DIMM with the EEPROM on the upper side Push down the SO DIMM until the retaining clips on each side Repeat these steps to populate the other socket To remove a SO DIMM from a socket push sideway the retaining clips on each side of the socket to release the module Pull out the memory from the socket 3 4 Onboard Interconnectivity 3 4 1 Onboard Connectors and Headers Description Connector Comments J1 CPCI bus signals and power J2 64 bit extension arbitration clocks reset and power Serial Ports A and B LAN 0 and 1 PS 2 Keyboard and Mouse VGA and USB CompactPCI I 0 J4 SCSI SCSI SCSI board version CompactPCI 1 0 J4 PIM Mezzanine signals PIM board version CompactPCI I 0 25 Legacy connections IDE and Floppy POST Code J6 4 pin locking Memory Sockets SO DIMM 200 pin Registered DDR 200 266 SDRAM CompactPCI Bus CompactPCI I 0 J3 RJ 45 connector with built in activity and link indicators faceplate Serial Port 1 J10 Supports RJ 45 connector faceplate USB J11 4 pin USB connector faceplate Reset SW1 Reset Switch faceplate Ethernet Management J9 o LE son ora v Su o Compact Flash J12 Compact Flash connector for a T069 Mezzanine Hot Swap J13 Hot Swap Switch IDE J14 IDE mezzanine connector JTAG J16 JTAG connector Battery BT1 CMOS backup battery connector PCI Mezz
61. e up to seven CPCI slots with PCI bus master capabilities CPCI 1 0 Signals This section describes integrated feature signals available on rear panel CPCI 1 0 connectors J3 J4 and J5 4 3 4 1 7 CompactPCI Connectors cPCIJ5 Connector Legacy connections IDE Floppy cPCI Connector SCSI Ultra 160 connections SCSI board version or PIM connections PIM board version cPCI J3 Connector LAN2 and LAN1 Serial Ports 1 and B PS 2 Keyboard and Mouse VGA POST ID Speaker and USB cPCIJ2 Connector 64 bit extension arbitration clocks reset and power cPCIJ1 Connector Supports cPCI bus signals and power 4 4 4 2 cPCII O Signals 4 2 1 Signal Specification 4 2 1 1 LAN2 1 ACT LAN2 1 LINK LAN CT LAN2 DA LAN2 DA LAN2 DB LAN2 DB LAN2 DC LAN2 DC LAN2 DD LAN2 DD 4 2 1 2 Signal Ethernet LAN 1 and LAN2 Pin Assignment Description A13 B13 D13 Transmit receive activity LED signal A14 B14 D14 Link integrity LED signal 614 LAN1 DA LAN1 DA LAN1 DB LAN1 DB LAN1 DC LAN1 DC LAN1 DD LAN1 DD Serial Port 0 COM1 Pin Assignment Description COM1 DCD COM1 RXD COM1 DSR COM1 TXD COM1 RTS COM1 CTS COM1 RI COM1 DTR D1 Data Carrier Detect B1 Receive Data C1 Data Set Ready D2 Transmit Data 1 Ready To Send C2 Clear To Send A2 Ring Indicator B2 Data Terminal Ready 4 5 4 2 1 3 Signal Serial P
62. ections on the Main Menu itself Use the sub menus for other selections Feature Description System Time HH MM SS Setthe system time System Date MM DD YYYY Setthe system date Select the type of floppy disk drive installed in your system Note 1 25MB 3 1 2 references a 1024 byte sector Japanese media format The 1 25MB 3 1 2 diskette requires a 3 Mode floppy disk drive None No booting device installed Multi Sector Transfers Choices Disabled 2 4 8 and 16 sectors Any selection except Disabled determines the number of sectors transferred per block Standard is 16 sectors per block LBA Mode Control Choices Disabled Enabled Enabling LBA causes Logical Block Addressing to be used in place of Cylinders heads and Sectors 32 BitI O Legacy Diskette Disabled A 1 44 1 25 MB 3 1 2 Multi Sector Choices Disabled Enabled Transfers Enables 32 bit communication between CPU and IDE card Requires PCI or local bus Transfer Mode 32 BITI O Choices Standard Fast PIO 1 Fast PIO 2 Fast PIO 3 Fast PIO 4 FPIO 3 DMA 1 FPIO 4 DMA2 Transfer Mode Selects the method for transferring the data between the hard disk and system memory The Setup menu only lists those options supported by the drive and platform Ultra DMA Mode Choices Disabled Mode 0 1 2 3 4 5 Select the Ultra DMA mode used for moving data to from the drive Autotype the drive to select the optimum transfer mode LBA Mo
63. ed Interrupt Lines 1 IRQ LINES The board is fully PC compatible with interrupt steering for PCI plug and play compatibility Controller 1 IRQ 0 Timer Output 0 IRQ 1 Keyboard Output Buffer Full IRQ 2 Cascade Controller 2 IRQ 3 Serial Port 2 IRQ 4 Serial Port 1 IRQ 5 BMC_INT Available IRQ 6 Floppy Controller IRQ7 BMC_INT Available IRQ 9 IRQ 10 IRQ 12 IRQ 13 IRQ 14 IRQ 15 All functions marked with an asterisk can be disabled or reconfigured 1 Available lines service on board and external PCI devices in Legacy mode Boot interrupt B 2 PCI INTERRUPTS Interrupt ICH3 IRQ14 IRQ15 PIRQA PIRQB PIRQC PIRQD PIRQE PIRQF PIRQH IDEO IDE1 P62H2 Boot interrupt MOBILITY M LAN 10 100 Ethernet Management USB BMC SMI FPGA INT FPGA NMI B 1 Controller 2 Real Time Clock Available Available Available PS 2 Mouse Coprocessor Error Primary IDE or available Secondary IDE or available Interrupt P64H2 PCI BUS A PMCAINTA PMC AINT B PMC A INTC PMC AINT D PMC B INT A PMC B INT B PMC B INTC PMC B INT D GLAN 2 GLAN 1 CPCI INT A CPCI INT B CPCI INTC CPCI INT D CPCI MEZZ INT A CPCI MEZZ INT B CPCI MEZZ INT C CPCI MEZZ INT D BRDG MEZZ INT On request only SMR 8HP option mezzanine B 2 C Kontron Extension Registers C 1 FPGA CPLD REGISTERS DEFINITION Unused shaded bits
64. ed Mode low power low frequency POM Performance Optimized Mode high power high frequency 5 13 5 1 2 5 7 Monitoring Menu Feature Description Intelligent System This is a Sub Menu Monitoring IPMI System NOTE the sub menu is not available if the BMC Reset jumper is Management OR Tice SUD SM installed W9 The BIOS Setup willin that case show Check the BMC Device 15 BMC reset jumper and the IPMI Firmware version update not available IDE Activity LEp IPE Activity Set IDE Activity Led usage IPMI Activity Enables the Watchdog circuit after the POST sequence Watchdog After Enabled POST Disabled Application software must refresh the Watchdog to prevent System Reset Watchdog 16 seconds a mi So Duration 1 minute Select the duration time of the Watchdog timing circuitry 4 minutes IRQ 5 Select FPGA IRQ for SWITCH WATCHDOG and ENUM events FPGA IRQ IRQ7 Disabled If is shown this IRO is already used by KCS SMS IRQ This enables or disables the Intel processor Automatic Thermal Enabled Control Circuit TCC Automatic TCC Disabled When enabled the processor clock will be forced to a 5096 duty cycle if the internal temperature exceeds its limit Disabled 2 Minutes The Thermal Control Circuit TCC must be disabled just prior to 4 Minutes transferring control to the operating System This is necessary in Delay prior to order for the Operating System s timing calibration to complete 8 M
65. ed on 6011 The IPMI CP6011 management controller includes many sensors such as voltage or current monitoring and others for pass fail type signal monitoring Each sensor s definition is available from the IPMI Device SDR module witch is accessible to the SMS The following sensor are implemented on the CP6011 the sensor name prefix SXX are dynamically assigned at power up base on cPCI slot number Sensors Names SXX Watchdog SXX IPMBO Stuck SXX IPMB1 Stuck SXX IPMI info 1 SXX IPMI info 2 SXX InitAgent Err SXX Power Off SXX Board Reset SXX Power Good SXX Temp A Q1 SXX Temp B Q2 SXX CPU Temp SXX Board 12V SXX Board 12V SXX Volt Battery SXX Slot System SXX PSU status SXX Lan1 Link SXX Lan2 Link SXX Lan3 Link SXX Board 1 2V SXX Board 2 5V SXX Board 1 8V SXX IPMI IPMB 5V SXX Board 5V SXX Board 3 3V SXX Board Icc 5V SXX Board Icc 3V SXX Board NMI SXX SMI Timeout SXX PMC A SXX PMC B SXX Slot State SXX CPU status SXX CPU Throttle SXX IPMB1 Alert SXX PCI Present SXX PCI VIO Error SXX PMC VIO Error SXX Slink Error Sensor Type Reading Class Watchdog 2 Watchdog 2 specific Cable interconnect digital discrete Cable interconnect digital discrete OEM OEM specific OEM OEM specific OEM digital discrete Power Supply OEM specific OEM OEM specific Power Supply OEM specific Temperature threshold Temperature threshold Temperature threshold Voltage threshold Voltage threshold Voltage thres
66. ed on the RTM You cannot use a standard RTM with most PICMG2 16 systems See your system s manual Signal Paths 10 100 Ethernet is available on J9 in the faceplate 10 100 1000 2 Ethernet are available through CPCI J3 Bios Settings Advanced gt PCI Configuration gt On board Ethernet Controller 2 9 2 5 System Management Features 2 5 1 Thermal Management The SBC includes a user defined temperature sensor alarm function which provides thermal monitoring of the processor using the WINBOND W83627HF In addition the Pentium M includes an active thermal control circuit TCC that can automatically throttle the CPU clock when exceeding the maximum operating temperature The current CPU temperature can be read by software or by a user application Use the IPMI for increased system management If you would like more information please consult the IPMI section Board Sensor A 01 Board Sensor B Q2 x Bios Settings En Monitoring Intelligent System Monitoring Note ay Temperature values are provided for reference only they should not be used for system calibration CPU overheating may happen if the system fans fail In the advent of catastrophic overheating the SBC will power down itself Note Ifthe CPU overheats the CPU asserts the THERMTRIP signal which stops power You need to cycle BDSEL or remove and insert the board to restart the board 2 5 2 Power Supply Monitoring All onboard supplies a
67. em Please refer to the PICMG2 1R2 0 specification for additional details The following paragraphs describe some of the most important features of the hot swap system 1 5 1 Board Level You may encounter these types of boards Type of board Description Non hot swap The board has of the features required for hot swap It is not electrically safe to hot swap a board in a powered system Basic hot swap The board has the minimum feature set to allow electrically safe insertion in a live system It is up to the system operator to use and configure the board after it is inserted Full hot swap In addition to the basic hot swap feature there are additional provisions for automatic software control over the connection process This gives the broadest range of system capability Boards in this class provide the following signals ENUM BDSEL HEALTHY Full hot swap boards also provide a blue LED and a switch in the lower ejector for interaction with the operator 1 5 2 System Level At this level hot swap capability depends on the boards and on the chassis Type of board Description Non hot swap There is not any hot swap capability in this class of system live insertion of any type of board is unsafe Basic hot swap It is electrically safe to insert a basic or full hot swap board in the chassis However the operator must do the software connection process Full hot swap This adds automatic software connection process to the bas
68. en the equipment and receiver e Connect the equipment into an outlet on a circuit different from that to which the receiver is connected e Consult the dealer or an experience radio TV technician for help WARNING This is a Class product If not installed in a properly shielded enclosure and used in accordance with this User s Guide this product may cause radio interference in which case users may need to take additional measures at their own expense UL Certification This product bears the combined UL Recognized Component Mark for Canada and U S It indicates investigations to the UL Standard for Safety of US Information Technology Equipment Including Electrical Business Equipment It is destinated to be used in end product equipment where the acceptability of the combination is determined by Underwriters Laboratories Inc CE Certification The product s described in this user s guide complies with all applicable European Union CE directives if it has a CE marking The CE declaration of conformity is provided on the last page of this user s guide For computer systems to remain CE compliant only CE compliant parts may be used Maintaining CE compliance also requires proper cable and cabling techniques Although Kontron offers accessories the customer must ensure that these products are installed with proper shielding to maintain CE compliance Kontron does not offer engineering services for designing cabling sy
69. enable the Console Redirection Mode put the jumper in Reserved Use this jumper to disable the onboard video feature Reserved Use these jumpers to connect or disconnect the termination resistors on from Serial COM2 when set for RS 422 RS 485 operation mode 0 Sets the maximum speed 66 100 133 2 of the PCI bus located on the backplane To disable the BMC put the jumper in To put the CompactFlash in master mode put the jumper in To set the VIO of the PMC B to 3 3V or 5V To clear the CMOS put the jumper in 3 1 W1 1 2 W1 3 4 W1 5 6 W2 1 2 W2 3 4 W2 5 6 w3 w4 w5 W6 W7 W8 w9 W10 W11W12 W13 3 1 2 Setting Jumper amp locations Default Setting WARNING Make sure that only W1 1 2 or W1 3 4 is set Only one at the time must be installed Rage e Mobility M Wi3ClearCMOS Clear CMOS in WARNING Make sure that only W11 or W12 is set Only one at the time must be installed 3 2 3 2 Processor This product ships with the CPU installed and a thermal solution Because the thermal solution is a custom one and the thermal interface is critical for passive cooling Kontron does not guarantee thermal performance if the heat sink is removed and then reinstalled by the end user 3 3 Memory Only use validated memory with this product Currently recommended configuration and part numbers are Quantity of memory Memory Slot A J7 K
70. eo Adapter PCII O Configuration VGA interface signals are available on the J3 CPCI 1 0 connector 2 11 2 6 1 Supported Resolutions The maximum video resolution and performance depend directly on the drivers running with your software application Resolution and number of colours specification are listed below Resolution Number of Colours 640x480 800x600 1024x768 1280x1024 1600x1200 256 8 bits 640x480 800x600 1024x768 1280x1024 1600x1200 65 536 16 bits 640x480 800x600 1024x768 1280x1024 16 8 million 24 bits 640x480 800x600 1024x768 16 8 million 32 bits 2 6 2 Major Features Description VGA Compatibility The video controller includes all registers and data paths required for the VGA controller and supports extensions to VGA including resolutions up to 1600 x 1200 x 65K colours non interlaced The 24 bit images are displayed at up to 1280x1024 resolutions 2 Graphics Engine The 2D graphics engine is an advanced 32 bit three operand engine that accelerates BitBLTs as line draws polygon draw and polygon fill The 2D graphics engine also performs video and bitmap scaling and data overlay 2 7 CPCI Features 2 7 1 Universal Bridge PLX6540 This cPCI product s access to the backplane bus runs through the PLX6540 PCI X to PCI X universal bridge The feature set of this bridge is similar to the HB6 which is used on Kontron cPCI products The PLX6540 can operate in either 32 or 64 bits bus wid
71. es Insert a system disk into Floppy Drive A and press Enter If you assumed the system would boot from the hard drive make sure the controller is inserted correctly and all cables are properly attached Also be sure the disk is formatted as a boot device Then reboot the system EXPANSION ROM NOT INITIALIZED Cannot initialize the PCI expansion ROM There is not enough free conventional memory for expansion ROM C0000h to DFFFFh Expansion ROM not required to boot should be disabled F F 1 F 2 BIOS Update amp Emergency Procedure BIOS UPDATE PROCEDURE The BIOS update procedure is detailed in a ReadMe file included with the BIOS package as well as the update utility This package can be downloaded from our website www kontron com or from our FTP site ftp ftp kontron ca Support EMERGENCY PROCEDURE Symptoms e No POST code on a power up when using a POST card e Board does not boot even after usual hardware and connection verifications e At power up there is floppy disk led activity which is one sign that the BIOS as detected corrupted BIOS CRC prior POST and fallen back automatically to Emergency Recovery Mode looking for the floppy Emergency disk The Emergency Recovery procedure is detailed in a ReadMe file included with the Emergency BIOS package as well as the update utility This package can be downloaded from our website www kontron com or from our FTP site ftp ftp kontron ca Support G Getting Help
72. fication requires the SDRR to be rebuild each time there is a configuration change in the chassis For more details about Fillsf exe please refer to CP6011_IPMI_Firmware package on Kontron website Probe the BMC SEL for event or any other available information using the SMS of your choice or by sending the command directly using your own tool IPMI Implementation of CP6011 Key Features Compliant with IPMI specification 1 5 revision 1 1 Compliant with PICMG 2 9 specification Can be configured as BMC or SMC by software from the BIOS Setup Menu Firmware designed and specially made for compact PCI implementation and easy integration with SAF HPI such as the Kontron XL VHDS SAF HPI implementation KCS SMS interface with interrupt support 2 16 Dual Port IPMB configurable as two independent channels or in redundant mode via BIOS Setup Menu Out of band management and monitoring using IPMB interface permits access to sensors regardless of SBC state Sensor threshold fully configurable Sensor name prefixed with slot number Complete IPMI watchdog functionality Complete SEL SDR repository and FRU inventory data functionality Master Read Write 2 supports for external I2C devices communications additional FRU inventory data EEPROM FAN Firmware can be updated in the field e Firmware fully customizable per customer needs e Interoperable with other IPMI solution 2 8 2 2 IPMI commands set on CP6011 The next table presents
73. field It updates as you move the cursor to each field 5 1 2 3 The General Help Windows Pressing lt F1 gt or lt Alt H gt on any menu brings up the General Help window that describes the legend keys and their alternates General Help Setup changes system behavior by modifying the BIOS configuration Selecting incorrect values may cause system boot failure load Setup Default values to recover lt Up Down gt arrows select fields in current menu lt PgUp PgDn gt moves to previous next page on scrollable menus lt Home End gt moves to top bottom item of current menu Within a field lt F5 gt or lt gt selects next lower value and lt F6 gt lt gt or lt Space gt selects next higher value lt Left Right gt arrows select menus on menu bar lt Enter gt displays more options for items marked with lt F9 gt loads factory installed Setup Default values lt F10 gt saves current settings and exits Setup lt Esc gt or lt Alt X gt exits Setup in sub menus pressing these keys returns to the previous menu lt F1 gt or lt Alt H gt displays General Help this screen 5 4 5 1 2 4 Main Menu Selection The scroll bar on the right of any windows indicates that there is more than one page of information in the windows Use lt PgUp gt and lt PgDn gt to display all the pages Pressing Home and End displays the first and last page Main Menu Selection You can make the following sel
74. forms maintenance such as assigning resources to PCI devices or installing or removing a device driver and any other task Some of the above functionalities may be implemented in the OS others may need specific application software More details on Hot Swap can be found on the PICMG 2 12 specification The Hot Swap Switch is in the lower ejector It allows the operator to inform the system about the intention to extract the board A blue LED located on the board s faceplate illuminates when it is safe to extract the board This LED indicates that the system software has been placed in a state for orderly extraction of a board The hardware connection layer provides protection only for the hardware during insertions and extractions This method allows the operator to insert or to extract boards without reconfiguring the system with the console Note In order to detect handle switch activity and to signal board status with the blue LED a proper hot lt swap driver must be running on the host a End user must be aware that adding PCI device in a live system require PCI ressources allocation This is not done by the OS It has to be done by a hot swap driver Consult Kontron s technical support if you need doing that WARNING All actions are initiated by the operator and must be performed in the correct sequence for proper system operation Full Hot Swap boards present the following resources to software executing on the system host
75. hase when asserted and data phase when not asserted SCSI Select The line is driven after a successful arbitration to select as an initiator or reselect as a target and otherwise it is received SCSI Message Indicates a message phase when asserted and command or data phase when not asserted Reset Signal 15 interpreted as a hard reset and will clear all commands pending on the SCSI bus Acknowledge Indicates a byte is ready for or was received from the target Busy Handshake signal used during arbitration Attention This line is activated when a special condition occurs SCSIHigh Parity Provide odd parity for data lines SCSI Low Parity Provide odd parity for data lines Differential Sense Detects the voltage level of a SCSI signal to determine whether it is a single ended or LVD 5V 3 3 Ground Reserved for Kontron internal use 4 8 4 2 2 2 PIM Interface Pin Assignment Description PIM1 to PIM 10 A25 025 B25 E25 A24 D24 B24 E24 A22 D22 PIM11 to PIM20 B22 E22 A21 021 B21 E21 A19 019 B19 E19 PIM21 to PIM30 A18 018 B18 E18 A16 D16 B16 E16 A15 015 PIM31 to PIM40 B15 E15 11 011 B11 E11 A10 D10 B10 E10 PIM Interface PIM41 to PIM50 A8 D8 B8 E8 A7 D7 B7 E7 A5 D5 51 to 60 5 5 4 D4 B4 4 2 D2 B2 E2 PIM61 to PIM64 A1 D1 B1 E1 VCC B23 5V VCC3 E23 3 3V A3 A6 A9 A17 A20 B3 B6 B9 B17 B20 C1 to C25 D3 D6 D9
76. hat a given data transfer cycle is a DMA data transfer cycle IDE1 DMACK IDE1 ACT Activity indicator IDE1 IRQ IRQ line 1 0 Chip Select Indicates to the host that the 16 bit data port IDE1 10CS16 has been addressed and the drive is prepared to send receive a 16 bit data word Disk Address These signals indicates which byte in either the ATA command block or control block is being addressed IDE1 A0 2 B21 D21 A21 IDE1 CSO CS1 D22 B22 Chip Select For ATA control register Diagnostic Will be asserted by Drive 1 to indicate to Drive 0 that it has passed diagnostics Following a power on reset or software reset Drive 1 will negate PDIAG within 1 msec to indicate to Drive 0 that it is busy IDE1 PDIAG 4 10 4 2 3 2 4 2 3 3 Floppy Disk Interface Pin Assignment FD INDEX B11 FD MTRO 1 A11 B12 FD DSEL 0 1 012 E12 FD DIR A12 FD STEP E13 FD WDATA FD WGATE FD TRKO FD WRPROT FD RDATA FD HDSEL FD DSKCHG FD DENSEL FD MSENO FD MSEN1 FD FDEDIN Pin Assignment Row C1 C22 A1 A9 B1 B9 D1 D10 E1 E10 E22 Description Index Motor 0 1 enable Drive 0 1 select Direction Step pulse Write disk data Write gate Track 0 Write protected Read disk data Head select Disk change Also named DRVDENO Density select Indicate the drive and media selected Automatic media sense Also named DRVDEN1 Used along DENSEL Indicates the drive and media selecte
77. his type of cable press in on the locking tabs before disconnecting the cable As you pull connectors apart keep them evenly aligned to avoid bending any connector pins Also before connecting a cable make sue both connectors are correctly oriented and aligned CAUTION Do not attempt to service the system yourself except as explained in this user s A guide Follow installation and troubleshooting instructions closely Preventing Electrostatic Discharge Static electricity can harm system boards Perform service at an ESD workstation and follow proper ESD procedure to reduce the risk of damage to components Kontron strongly encourages you to follow proper ESD procedure which can include wrist straps and smocks when servicing equipment Take the following steps to prevent damage from electrostatic discharge ESD When unpacking a static sensitive component from its shipping carton do not remove the component s antistatic packing material until you are ready to install the component in a computer Just before unwrapping the antistatic packaging be sure you are at an ESD workstation or grounded This will discharge any static electricity that may have built up in your body When transporting a sensitive component first place it in an antistatic container or packaging Handle all sensitive components at an ESD workstation If possible use antistatic floor pads and workbench pads Handle components and boards with ca
78. hnology Changes that affect the operation of the unit will be documented in the next revision of this user s guide Contents Customer Service Contents Safety Instructions Before You B6edlfiiza ss viii When Working Inside a Computer ix Preventing Electrostatic Discharge x Working with Batteries ee xi Preface How to Use This GUIDE usa au Md xiv Customer COMMENES sous iae EROR C n REI Advisory CONVENTIONS xvi Powering Up the Syst m ai E xvi Adapter Cables aaa ote vo ses PE xvii SLOT Boards Debes G bed dud xvii Regulatory Compliance Statements xvii Limited rura ix tid etd xviii 1 Product Description 1 1 Product OvervieW kunu 1 1 1 2 What SIN ar ned ap 1 2 13 BoardSpecifications 1 2 1 4 Compact PCL Compliance u asas QNNM 1 6
79. hold Entity presence Ent pres specific Power Supply P Supply specific LAN LAN Specific LAN LAN Specific LAN LAN Specific Voltage threshold Voltage threshold Voltage threshold Voltage threshold Voltage threshold Voltage threshold current threshold current threshold Critical interrupt digital discrete Critical interrupt digital discrete Entity presence Ent pres Specific Entity presence Ent pres specific Slot Connector Slot Con specific Processor processor specific Processor digital discrete Cable interconnect digital discrete Entity presence Ent pres specific Power Supply digital discrete Power Supply digital discrete Management Subsystem Health specific 2 18 Description IPMI watchdog PICMG 2 9 required sensor indicates problem on IPMBO PICMG 2 9 required sensor indicates problem on IPMB1 Reserved for internal firmware usage Reserved for internal firmware usage Only present on BMC Indicates if the Init Agent has enconter a problem such as missing SMC Indicates any source holding board in power down Indicates any source holding board in reset Reflect goodness of various on board supply Upper Edge PMC site A board temperature Lower Edge PMC site B board temperature Current CPU temperature on die thermal diode Board 12V supply Board 12V supply Board RTC battery Indicated if board is in a system slot System power supply Deg Fail indication LAN1 link sta
80. ic Help System Time 13530500 lt System Date 01 01 2004 Enter gt selects Legacy Diskette Disabled field Primary Master Primary Slave Secondary Master Secondary Slave DOS Disabled System Memory 624 Extended Memory 512 Whenever you are not sure about a certain setting you may refer to the list of default values The list of defaults is provided in the event that a value has been changed and one wishes to set this option to its original value Loading the SETUP defaults will affect all parameters and will reset options previously altered The Setup Defaults values provide optimum performance settings for all devices and system features Note 22 The CMOS setup option described in this section is based on BIOS Version 2 4 The options and default settings may change in a new BIOS release CAUTION A These parameters have been provided to give control over the system However A the values for these options should be changed only if the user has a full understanding of the timing relationships involved 5 2 5 1 2 The Menu Bar The Menu Bar at the top of the window lists these selections Menu selection Description Main Use this menu for basic system configuration Advanced Use this menu to set the Advanced Features available on your system Monitoring Use this menu to configure Monitoring features Boot Use this menu to determine the booting device
81. ic hot swap model A signal ENUM is used to notify the system slot when a peripheral board is newly inserted or when a board is about to be extracted High availability This is strictly system dependent A full hot swap board already meets the electrical requirement for a High Availability system but the system itself may fall in the Full Hot Swap category if it is not controlling the hardware connection process In addition to the automatic software connection process a High Availability system adds more control over the hardware such as reset and power control of each slot of the system 1 6 The following signals are used BDSEL This is a short pin It is the last to mate or the first to break contact This signal allows the system to detect the presence of a board and also to control its power state Systems other than High Availability have this pin grounded HEALTHY This is a normal length pin Peripheral boards are required to drive this signal low when they are ready to join the PCI bus This signal will not be asserted when the current operating mode of the bus is not compatible or when the back end power is not good or for any other reason PCIRST This signal resets the PCI bus when driven low High availability can implement this signal as a radial signal from the Hot Swap Controller HSC to further control the electrical connection Platforms that do this must OR the system host s reset signal with the slot specific s
82. ignal to maintain the bused signals function M66EN On a High Availability platform compatible with R 2 0 of PICMG2 1 the signal may be radial from the HSC This allows the platform to accept 33MHz only peripheral boards that comply with R 1 of the specification Note a Hot Swap of the system slot is not defined in the PICMG2 1R2 0 specification It is electrically possible to hot swap the CP6011 in a system slot but system functionality is lost and the PCI bus will float WARNING It can be harmful for some PCI peripheral devices to remove system slots because the PCI bus floats At least PCIRST should be asserted but not all platforms detect this condition and hold the system in reset when a system board is not present Please consult your chassis manual 1 5 3 Hot swap compatibility with Kontron s systems XL VHDS XL PSB XL CXP XL LP41 XL LP42 CP6011 High availability Full hot swap CP6011 is not High High 1 supported in availability 2 availability 2 this chassis 1 When system management card used 2 No supported for radial RESET and radial M66EN 1 7 1 5 4 Full hot swap mechanism Full Hot Swap boards such as the CP6011 in peripheral mode drive the ENUM signals to the system host to indicate a service request This signal notifies the system host that either a board has been inserted or is about to be extracted and that the configuration of the system has or will change Then the system host per
83. inal POST Errors There are several POST routines that issue a POST Terminal Error and shut down the system if they fail Before shutting down the system the terminal error handler issues a beep code signifying the test point error writes the error to port 80h attempts to initialize the video and writes the error in the upper left corner of the screen using both mono and color adapters The routine drives the beep code from the test point error as follows 1 The 8 bit error code is broken down to four 2 bit groups Discard the most significant group if it is 00 2 Each group is made one based 1 through 4 by adding 1 3 Short beeps are generated for the number in each group Example Test point 01Ah 00 01 10 10 1 2 3 3 beeps Test Points and Beep Codes Atthe beginning of each POST routine the BIOS outputs the test point error code to 1 0 address 80h Use this code during troubleshooting to establish at what point the system failed and what routine was being performed If the BIOS detects a terminal error condition it halts POST after issuing a terminal error beep code See above and attempts to display the error code on upper left corner of the screen and on the port 80h LED display If the system hangs before the BIOS can process the error the value displayed at the port 80h is the last test performed In this case the screen does not display the error code Code Beeps POST Routine Description Verify Real Mode Di
84. inutes enabling the TCC accurately 16 Minutes 32 Minutes This delay is valid for both Automatic and OnDemand TCC Intelligent System Monitoring 5 1 2 5 8 Feature Interrupt Generation Hardware Monitor Temperature Hardware Monitor Voltage Inputs Control Temperature Events Control Voltage Events Enabled Disabled This is a Sub Menu This is a Sub Menu This is a Sub Menu This is a Sub Menu Description Enables disables the generation of interrupts when an event occurs This must be set to Disabled when programs such as LANDesk R are loaded onto the system 5 14 5 1 2 5 8 1 Hardware Monitor Temperature Feature Description CPU Die Temperature Display a Status The following are temperature at the various sensors present on the board Board Sensor A Q1 Display a Status Please refer to manual for location of those sensors Board Sensor B Q2 Display a Status 5 1 2 5 8 2 Hardware Monitor Voltage Inputs Feature Description Vcore Displays a Status Displays a Status and When enabled events can be triggered when a specific limits setin other menu voltage cross below the LoLimit or above the HiLimit Displays a Status and limits set in other menu Displays a Status and limits set in other menu Vin 1 25V Vin 3 3V The following is the different voltage usage on the board 1 25V Memory 3 39 gt Misc Vin 5V Displays a Status and limits setin other menu 5V Misc
85. ion 1h BLUE 7 Default LED Color in Override 01 State Bits number 7 4 Reserved shall be set to 0 3 0 Hex Value Function 1h BLUE Request command WP 2 8 4 Software Support 2 8 4 1 IPMI KCS Support in Different OS For customer that plan to design software using IPMI feature there are some tools publicly available Linux An open source KCS driver is available for Linux This driver includes all the necessary functionality and more to communicate with the IPMI management controller http openipmi sourceforge net IPMItoolis a simple command line interface to systems that support the Intelligent Platform Management Interface IPMI v1 5 specification It provides the ability to read the SDR and print sensor values display the contents of the SEL print FRU inventory data information it is also capable of using a system interface as provided by a kernel device driver such as OpenIPMI http ipmitool sourceforge net Intel provides some Linux KCS reference drivers they are available at the following address http www intel com design servers ipmi ipmi_driver htm Contact Kontron s technical support for additional tools or help with Linux IPMI tools Windows 2 8 4 2 Intel provides some Windows KCS reference drivers they are available at the following address http www intel com design servers ipmi ipmi_driver htm For Windows XP Windows Server 2003 and Windows 2000 Microsoft is pr
86. istance Adapter Cables Because adapter cables come from various manufacturers pinouts can differ The direct crimp design offered by Kontron allows the simplest cable assembly All cables are available from Kontron Sales Department Storing Boards Electronic boards are sensitive devices Do not handle or store device near strong electrostatic electromagnetic magnetic or radioactive fields Regulatory Compliance Statements This section provides the FCC compliance statement for Class B devices and describes how to keep the system CE compliant FCC Compliance Statement for Class B Devices This equipment has been tested and found to comply with the limits for a Class B digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generated uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures Reorientor relocate the receiving antenna e Increase the separation betwe
87. king registers When we lock register with fwh_lock Reg_BMCCTR TBL state comes automatically at 0 WRITE PROTECT When low prevents programming or sector erase to all but the highest addressable sectors 0 6 ina 4 Mbit 0 14 in an 8 Mbit component regardless of the state of the corresponding lock registers WP high disables hardware write protection for these sectors though register based protection still applies The status of TBL does not affect the status of sector locking registers When we lock register with fwh lock Reg_BMCCTR TBL state comes automatically at 0 Emergency Bios mezz is preset when this bit is set to 1 C 7 D Connector Pinouts D 1 CONNECTORS AND HEADERS SUMMARY CPCI Bus connector CPCI Bus connector CPCI 1 0 connector CPCI 1 0 connector CPCI 1 0 connector POST Code Memory SODIMM 1 2 J9 Ethernet Management J10 COM1 Faceplate RJ 45 J11 USB Faceplate J12 Compact Flash J13 Hot Swap Switch J14 IDE Mezzanine J16 JTAG JN1A JN4A 64 bit PCIX Mezzanine amp PIM JN1B JN3B 64 bit PCIX Mezzanine Reset Button faceplate Battery LEDs D 1 D 2 CPCI BUS 21 ROW D VCCE 12VE RSV RSV VCCE RSV INTA INTB INTC IPMB_PWR HEALTHY VI O RSV RSV RST REQO PCI PRESENT VCC3E AD30 AD29 AD28 AD26 GND VI 0 CBE3 IDSEL AD23 AD21 GND VCC3E AD18 AD17 AD16 CON Ui HR Ut FP KEY AREA VCC3E FRAME IRDY BD_SEL TRDY DEVSEL PCIXCAP
88. les Temperature events handling 5 16 5 1 2 5 9 IPMI System Management Feature Options Description IPMI Device and Firmware This is a Sub Menu Intelligent Platform Management Interface IPMI information Information FR Bomm This is a Sub Menu Field Replaceable Unit FRU information about the board Information Allow Baseboard Management Controller BMC SMI handler for the initialization or startup of certain functions in the Management Controllers such as setting the initial timestamp kcs smmsmy Fnabled time Disabled WARNING option forced to Disabled if the TEST jumper is installed Select BMC IRQ for the System Management Software SMS SMS TROS takes platform management information and links it into other aspects of systems management such as software management KCS SMS IRQ IRO7 and distribution alerting remote console access etc Disabled If is shown this IRO is already used by FPGA IRQ Intelligent Platform Management Bus IPMB Dual Port IPMB Enabled Enabled IPMB1 is hidden behind IPMBO and used as a Redundancy Disabled Redundancy channel Disabled IPMBO and IPMB1 operate as separate channels BMC the board is the central management controller Management Satellite the Board is a Satellite Management Controller g Basebord under the control of an external central Management controlar Li Controller Configuration Satellite The BMC manages the interface between system management and the pla
89. lot and therefore potentially double overall system density Combined with a high I 0 throughput chipset like Intel s E7501 and up to 2GB of DDR memory distributed over two separate channels for increased memory bandwidth this board is designed to meet the requirements of the most demanding applications The CP6011 has two SODIMM sockets with Registered ECC support for a better combination of flexibility capacity and cost efficiency Finding the product that exactly matches all application requirements can be a difficult task Kontron however made it easier by offering the CP6011 with two PMC slots that can be populated with Kontron or third party products The wide acceptance of the PMC standard and the availability of several different flavors of PMC will allow customers to easily tailor the CP6011 to their requirements in a very short amount of time The first high performance PMC slot up to 64 bit 133MHz PCI X also supports the PMC 1 0 Module PIM standard thus allowing the access of the PMC 1 0 signals on Kontron s rear transition module RTM The second PMC slot has interface that can reach up to PCI X 64 bit 100MHz The CP6011 has Dual Gigabit Ethernet 2 16 compliant ports and a third 100Base T Ethernet port on the front panel for management or other purposes Additional Gigabit Ethernet ports and Ultra160 320 SCSI can be added through Kontron PMC cards respectively PMC240 and PMC261 CP6011 also has VGA support through the use
90. m WARNING Always use a grounding wrist wrap before installing or removing the board froma chassis WARNING Removing the system host in a running system can harm some PCI 1 0 devices because the bus remains floating At least PCI reset should stay asserted but not all systems detect this condition and hold reset active when no system slot is present CAUTION In system slot the VIO must be set to 3 3V or 5V Depending on Board Options A There is no limitation in a peripheral slot 3 6 1 Installing the Card in the Chassis To install a card in a chassis 1 2 3 Remove the filler panel of the slot or see Removing the Card below Ensure the board is configured properly Carefully align the PCB edges in the bottom and top card guide Insert the board in the system until it makes contact with the backplane connectors Using both ejector handles engage the board in the backplane connectors until both ejectors are locked Fasten screws at the top and bottom of the faceplate 3 8 3 6 2 Removing the Board If you would like to remove a card from your chassis please follow carefully these steps Unscrew the top and the bottom screw of the front panel Push the red handle latch until the ejector fall free Using both ejectors disengage the board from the backplane Pull the board out of the chassis gt O 3 6 3 Installing a PMC Card To install a PMC card 1 Remove the fro
91. min with history Silicon Serial ID TAG for unique board identification accessible via software Hardware system monitor voltages temperature CPU temperature monitor alarm board temperature sensor power failure low battery detector SMBus Current monitoring using IPMI Microsoft Windows 2000 family Microsoft Windows XP Microsoft Windows Server 2003 Linux Fedora Core 3 FreeBSD 5 2 And other OSs Upgrade path for many previous Kontron s boards MXS64 MXP64 MXS64GX MXP64GX CPCI J3 J4 and J5 pinouts is the same as the DT64 and the CP6010 but has been changed from previous boards Do not use older Rear Transition Modules RTMs with this board Use only the CTM80 2 RTM or contact technical support for other RTM availability 6U 10 5 x 6 3 x 4HP Standard cPCI 6U board Supply Voltage 3 3V 5 3 5V 5 3 12 5 12V 5 2 06 2619 DDR 1 86 2619 DDR 1 66 2619 DDR 1 16 2619 DDR ICC 51 8 8 5 6 7 4 3 4 ICC 3 3V 4 2 Amax 6 1 max 5 9 Amax 5 9 Amax ICC 12V 0 3 A 0 3 A 0 3 max 0 3 ICC 12V 10 mA max 10 mA max 10 mA max 10 mA max Power 61 2 W 52W 60 W 40 W Mesured with MaxPower and Memtest 2 0 1 4 Board Specifications continued Operating 0 55 C 32 131 F Temperature Air Flow Consult table below Humidity 5 to 90 40 C 104 F non condensing Altitude 4 000 m 13 123 ft Envir
92. n RS 232 mode Pin Signal id rm RTS DTR al TXD DCD GND DSR CTS 1 2 3 4 5 6 7 8 Note The pinout is a custom one not the same as RS 232D 561 Use the Kontron provided RJ45 to DB9 adapter Signal Paths The Serial Port 1 signal is always available in front and rear access Bios Settings Advanced gt On board Device Configuration gt Serial port A 2 6 2 4 3 2 Serial Port 2 Serial Port B is buffered directly for RS 232 operations and is 16 550 PC compatible The interface includes the complete signal set for handshaking modem control interrupt generation and data transfer This port is 100 compatible with the IBM AT serial port Signal Paths Serial Port B signals are only available through the J3 CPCI 1 0 connector Related Jumpers W4 and W5 insert both jumper if Serial Port 2 is used in RS 422 or RS 485 mode and need termination resistors Termination resistors are 120 ohm I Bios Settings En Advanced gt On board Device Configuration gt Serial port B Upon a power up or reset the Serial Port 2 interface circuits is automatically configured for the operation mode setup in the BIOS This Serial Port signal assignation on the J3 CPCI 1 0 connector depends on the operation mode RS 232 RS 422 or RS 485 it has been set J3 Connector RS 232 RS 422 RS 485 RSV RX TX
93. nt bezel 2 Carefully push the PMC to mate the four connectors 3 Screw the four screws at the bottom of the PMC to fix it to the board WARNING The CompactFlash and the PMC B can not be used simultaneously IDE Mezzanine and the not be used simultaneously 3 6 4 Installing the IDE Mezzanine To install the IDE mezzanine 1 Carefully connect the IDE connector of the mezzanine to the IDE connector J14 of the board 2 Screw the four screws at the bottom of the PMC to fix it to the board 3 6 5 Installing a CompactFlash This product supports all type I and type II CompactFlash modules WARNING Never install or remove the compact flash while the board is on To install the CompactFlash 1 Remove the plastic retainer 2 Insert the CompactFlash in place 3 Reinstall the plastic retainer To remove the CompactFlash Remove the plastic retainer Pull the CompactFlash module out Install a new CompactFlash module Reinstall the plastic retainer 4 Building a cPCI System Contents 4 1 BuilingacPCISvystem 4 1 Sc SPOLIIS HIS u uu us 4 5 4 1 Building cPCI System The basic components needed to build a CompactPCI system include Chassis Backplanes Power supplies Ventilation unit System peripheral or busless boards following application requirements Other accessories such as storage modules Ethernet switches sys
94. odule 1 0 be accessed through the use of a RTM RTM use a proprietary pinout in 23 24 25 to bring out all 1 0 of the SBC Only use Kontron s RTM with the CP6011 Currently compatible RTM is the cTM80 2 RTM are not designed to be hot swapped Always make sure that either the system is shut off or that the front board of the RTM is unpowered before removing or installing the RTM Note A front 1 0 configuration the following I Os signals are available on the faceplate Serial 22 Port COM1 RJ 45 USB Port 1 Ethernet 1 other I Os are connected J3 J4 and J5 Rear 1 0 configuration all 1 0 signals are connected to 33 J4 and J5 1 6 3 Mezzanine The mezzanine is a hardware interface used to increase I 0 connectivity of the CP6011 while respecting the single slot 4HP form factor restrictions It is built around three sets of connectors e Mezzanine connector handling IDE signals e PMCA Mezzanine connectors 4 that handle an independant PCIX signal set including the REQ GNT arbitration signal pair 64bits 133MHz And the PIM interface PMCB Mezzanine connectors that handles a complete PCIX signal set including the REQ GNT arbitration signal pair This PCI channel 15 bussed with the 2 Gig Ethernet and the Bridge 64bits 100MHz CompactFlash Mezzanine connector that handle all the signals to connect a CompactFlash Module e These connectors represent an open door for future development of e
95. of ATI s Mobility M graphics chip It also features CompactFlash support ATA 100 and programmable user LED s for software use The CP6011 is capable of driving a cPCI bus segment that can scale from 32 bit 33MHz to 64 bit 133MHz PCI X Since the chipset has two independent 64 bit 133MHz PCI X buses it ensures thata board driving an external bus two PMC s and the dual Gigabit Ethernet will maintain a high level of performance In today s systems whether they are in communications medical or industrial environments serviceability is critical and the ability to manage an entire system remotely is often an obligation The groundwork for such an environment is the Intelligent Platform Management Interface IPMI The CP6011 includes a Baseboard Management Controller BMC that incorporates Kontron s IPMI firmware which allows the board to act as an IPMI BMC or as a satellite in one of Kontron s High Availability platforms Kontron s Xtreamlink family of system products includes two platforms with such management capabilities the XL VHDS 10U carrier class platform and the XL LP42 4U low profile platform As a powerful very flexible and high density CPU engine the CP6011 is intended for applications calling for distributed high processing capabilities and tremendous 1 0 throughput Those are likely to be VoIP applications Softswitch Media Gateway Signalling Gateway trunking call centers and IVR wireless infrastructure applications Base
96. om can also be used 5 3 2 Setup amp Configuration Follow these steps to set up the VT100 mode 1 Connecta monitor and a keyboard to your board and turn on the power 2 Enterinto the CMOS Setup program in the Advanced page Console Redirection menu 3 Selectthe VT100 mode and the appropriate COM port and save your setup 4 Connectthe communications cable Note If you do not require a full cable for your terminal you can set up a partial cable by using only the TXD and RXD lines To ignore control lines simply loop them back as shown in VT100 Partial Setup cable diagram NY 5 Configure your terminal to communicate using the same parameters as in CMOS Setup 6 Install the VT100 jumper Reboot the board 7 Usethe remote keyboard and display to setup the BIOS Save the setup exit and disconnect the remote computer from the board to operate in stand alone configuration Console Redirection is done by refreshing the Video address 2 B8000h at the selected BAUD rate This means that a low baud rate refreshes the screen slowly but the CPU time is maximized for the applications A high BAUD rate refreshes the screen rapidly but the CPU is frequently interrupted by the Serial Port 5 22 Console Redirection provided by Phoenix based BIOS offers various escape sequences to emulate keyboard function keys The following table lists the escape sequences available Escape sequence Escape sequence Esc Del Warm Reset Esc 64
97. onmental 30G half sine 11ms each axis Vibration 1 0G 5 500Hz each axis Storage and Transit 40 to 70 C 40 to 158 F 5 to 95 40 C 104 F non condensing 15 000 m 49 212 ft Bellcore GR 63 CORE Section 4 3 2 0G 5 50Hz 3 0G 50 500Hz each axis e MTBF gt 134 000 hours 25 C 77 F Telcordia SR 332 Issue 1 Whole board protected by active breaker Reliability e USB voltage protected by an active breaker e Mouse keyboard voltage protected by self resetting fuses Meet or exceed Safety EMC e Safety UL 60950 3 Ed CSA C22 2 60950 00 EN 60950 2000 IEC60950 1 e EMI EMC FCC 47 CFR Part 15 Class B CE Mark to EN55022 EN55024 Warranty Two year limited warranty Designed to meet or exceed Airflow Configuration Max Ambient Base board 16 24 PMC Ethernet and PMC SCSI For more configurations please call Technical Support These results are shown for reference only and might differ from your system and CPUs 1 5 1 4 Compact PCI Compliance This product conforms to the following specifications e PICMG2 0R3 0 core specification PICMG2 1R2 0 hot swap specification PICMG2 9R1 0 system management PICMG2 10R1 0 keying of CPCI boards PICMG2 16R1 0 packet switching 1 5 Hot Swap Capability The CP6011 supports Full Hot Swap capability as per PICMG2 1R2 0 The T6011 can be removed from or installed in the system while it is on without powering down the syst
98. ontron Part Number Memory Slot B J8 Kontron Part Number 512 MB 635 118 635 118 1 GB 1024 MB 635 119 635 119 2 GB 2048 MB 635 137 00 635 120 Memory should have the following characteristics DDR200 or DDR266 2 5V only Single sided or double sided 1 layer of BGA on PCB side X4 or X8 configuration supported Serial Presence Detect SPD EEPROM 64 bit and 72 bit DIMMs supported 1 45 inch maximum height Note To ensure proper operation the board must have two identical memory modules installed The EEPROM may conflict with the connector s clip In this case the two SO DIMM shall be different The EEPROM is installed on the 2 different sides Insert the SO DIMM with the EEPROM on the upper side WARNING Because static electricity can cause damage to electronic devices take the following precautions e board in its anti static package until you are ready to install memory e Wear a grounding wrist strap before removing the board from its package this will discharge any static electricity that may have built up in your body e the board by the faceplate or its edges 3 3 3 3 1 Installing Memory On an anti static plane place the board so that you are facing the SO DIMM sockets Insert the SO DIMM into any available socket aligning the notches on the module with the socket s key inserts The EEPROM may conflict with the connector s clip 1GB only In this cas
99. ort 1 COM2 Pin Assignment Description COM2 DCD COM2 RXD COM2 DSR COM2 TXD COM2 RTS COM2 CTS COM2 RI COM2 DTR 4 2 1 4 Signal D3 B3 C3 D4 A3 C4 A4 B4 USBO USB1 Pin Assignment Data Carrier Detect Receive Data Data Set Ready Transmit Data Ready To Send Clear To Send Ring Indicator Data Terminal Ready Description USBO DATA DATA USB1 DATA DATA USBO 1 VCC 4 2 1 5 Signal B8 8 9 9 10 10 Keyboard Pin Assignment USB Data USB Data USB Voltage Description KB DATA KB CLK 4 2 1 6 Signal E4 E5 Mouse Pin Assignment Keyboard Data Keyboard Clock Description MOUSE DATA MOUSE CLK 4 2 1 7 Signal 3 E2 Speaker Pin Assignment Mouse Data Mouse Clock Description SPEAKER E7 Speaker signal 4 6 Differential data path for USB 0 port Differential data path for USB 1 port Differential power level for USB 0 and 1 port 4 2 1 8 POST Pin Assignment POST DATA POST CLK 4 2 1 9 Video Description POST data POST clock Signal Pin Assignment Description VGA HSYNC B5 VGA VSYNC 65 VGA SCLK D5 VGA SDATA C6 VGA RED VGA GREEN VGA BLUE 4 2 1 10 ID Signal Pin Assignment 101 104 E1 B7 C7 07 Horizontal synchronization Vertical synchronization Video serial clock line Video serial data line Analog red video signal Analog green video signal
100. ot PCI segment one 2 16 Fabric slot CP6011 6U system board up to 7 including other Kontron cPCI SBCs CTM80 2 6Ux8HPx80mm RTM for CP6011 Third party CPCI 1 0 board with RTM as needed Up to three 3U 250W power supplies One Ethernet switche PICMG2 16 One optional CMM Chassis Management Module AC or DC power input Two PCI segments 4 slots 3 slots One 2 16 Fabric slot CP6011 6U system board up to 7 including other Kontron cPCI SBCs CTM80 2 6Ux8HPx80mm RTM for CP6011 Third party CPCI 1 0 board with RTM as needed Up to three 3U 250W power supplies One Ethernet switche PICMG2 16 One CMM Chassis Management Module AC or DC power input 1 11 2 Onboard Features Contents d CUERO 2 1 2 2 La SEI 2 4 2 5 2 5 System Management Features 2 10 26 Videolnterface 2 11 24 2 12 meer 2 14 29 Debugging Features 2 24 2 10 Miscellaneous Features 2 25 2 0 2 1 Block Diagram B g DEVELOPMENT IPMI POWER UPGRADE 2 2 System Core 2 2 1 Processors The Intel Pentium M processor is a high performance low power mobile processor with several micro architectural enhancements over existing Intel mobile processors The following list provides some of the key features
101. oviding a device driver and manageability infrastructure for developers to use to write hardware device drivers This infrastructure allows management data to be obtained from hardware interfaces that might not have direct native support in these versions of Windows By using WMI and WDM hardware interfaces such as IPMI can be supported in systems http www microsoft com whdc hwdev driver WMI WMI intro mspx Firmware Update The IPMI firmware update tool ipmifwu is available from Kontron for both Dos and Linux This utility allows you to upload a new binary file to the microcontroller Consult the ipmifwu usage display for complete utility options by running ipmifwu h Visit the Kontron Web site for package and firmware availability or call Kontron Technical Support DOS Firmware update procedure 1 Boot DOS 2 Place both firmware binary and utility ipmifwu exe on a floppy 3 Insert the floppy and run the following ipmifwu f firmware bin p r 2 22 Linux Firmware update procedure 1 Putipmifwu and firmware bin in a temporary directory i e tmp 2 Move to that directory i e cd 3 Simply run the command ipmifwu f firmware bin p r Note lt You must have super user root privileges to gain access to the hardware ports WARNING Some firmware might not be compatible with some BIOS versions Always upgrade A the BIOS and firmware as recommended 2 8 5 IPMI Communication LED Itis possible
102. pendix C 2 9 2 Serial Post Codes The 8 bit content of 1 0 address 80h is serialized into a proprietary protocol and output on J3 connector In manufacturing Kontron use a display board to deserialize and display the post code value on 7 segment LEDs modules This approach enables you to see post codes because it is not possible to see postcode with a PCI card on CP6011 the PCI to PCI bridges P64H2 also does not forward this IO 80h The display board is not offered with this product It is used for manufacturing Postcodes can be a useful tool when debugging application software If the display board is interesting you please ask your Kontron representative for it 2 10Miscellaneous Features 2 10 1 Serial Number A DS2401 silicon serial number comes standard on the CP6011 It can be read from register 0x193 See appendix C 2 25 3 Installing the board Contents 3 1 3 2 PROCES 3 3 RR 3 3 3 4 Onboard Interconnectivitv 3 5 0 0 04 SNNT 3 7 3 6 Board Hot Swap and Installation 3 8 3 0 3 1 1 3 1 Setting Jumpers Jumper Description Description PMCA VIO Settings User Jumper Console Redirection Reserved Onboard Video Reserved Serial COM2 Termination Backplane PCI Onboard BMC Compact Flash PMC B VIO Settings Clear CMOS To set the VIO of the PMC A to 3 3V or 5V This jumper is for user applications To
103. plotar si la pila no este bien reemplazada Solo reemplazca la pila con tipas equivalentes segun las instrucciones del manifacturo Vote las pilas usads segun las instrucciones del manifacturo xii gt gt P P Preface Contents How to Use This Guide xiv Customer Cone Advisory Conventions d PR us hawa xvi Powering Up the System xvi Adapter Cales xvii Storag TT xvii Regulatory Compliance Statements xvii Limited Warranty xviii xiii How to Use This Guide This user s guide is designed to be used as step by step instructions for installation and as a reference for operation troubleshooting and upgrades You can find the latest release of this User s Guide at http www kontron com or at ftp ftp kontron ca support For the circuits descriptions and tables indicated Kontron assumes no responsibility as far as patents or other rights of third parties are concerned The following is a summary of chapter contents Chapter 1 Product Description Chapter 2 Onboard Features Chapter 3 Installing the board Chapter 4 Building a CPCI System Chapter 5 Software Setup Appendix A Memory 1 0 Maps Appendix
104. ption Save the current boot type into CMOS Initialize error logging Check the requested boot type Cold or Warm Initialize error display function Initialize system error handler Install the IRQ1 vector for BIOS Hot Keys PnP NoteDock dual CMOS optional Mark the fact that we are no longer in POST Console Redirection SIO Initialize Remove Console Redirection Force Emergency Flash update check Ctrl E and bad CMOS Test Gate A20 Extended checksum optional Install Console Redirection Interrupt Handler Extended BIOS data Fail BIOS stack initialization Unknown interrupt Setup WAD reserved memory used by BIOS Get CPU string Software SMI failure during POST Memory error Their is no memory modules Memory error The two memory modules type mismatch Memory error Memory type is not supported Memory error CHL Mismatch Memory error Size Mismatch Memory error Row address bits Memory error Internal Bank Memory error Timing Error Memory error CAS 3 Memory error Non Registered and Registered memory have been mixed Memory error Case Latency not supported Memory error Size Not Supported Memory error Population order E 5 For Boot Block in Flash ROM Initialize the chipset Initialize the bridge Initialize the CPU Initialize system timer Initialize system 1 0 Check force recovery boot Checksum BIOS ROM Go to BIOS Set Huge Segment Initialize Multi Processor Initialize OEM special code Initialize
105. r Real time clock with 256 byte battery backup CMOS RAM Front Plate COM1 1 x RJ 45 Serial Port Ethernet 1 x RJ 45 Ethernet USB 1 1x4 pin USB female Optional SCSI PMC adapter with front connector Rear CPCI 1 0 Connectors 23 24 25 Rear panel transition module cTM80 2 available separately CRT Serial Ports 2 USB 2 Speaker I F Reset Switch Ethernet 2 PS 2 Mouse amp Keyboard SCSI with PMC EIDE Floppy disk 2 PCI Mezzanine Card PMC Connectors in Front configuration Interfaces on 23 24 25 Onboard Expansions CompactFlash 4HP IDE Mezzanine 1 3 Board Specifications continued BIOS Features Supervisory OS Compatibility Hardware Compatibility Mechanical Power Requirements Phoenix BIOS in Boot Block Flash with recovery code Save CMOS in Flash option Boot from LAN and from USB capability Auto configuration extended setup and VGA disable by jumper Diskless keyboard less and video less operation extensions System video and LAN BIOS shadowing Programmable memory wait states HDD S M A R T support Advanced Configuration and Power Interface ACPI 1 0 Intelligent System Monitoring advanced thermal management such as resume overheat alarm and auto slow down Setup console redirection to serial port VT100 mode with CMOS setup access Support a system management interface via an IPMI V1 5 compliant controller Two stage software programmable watchdog timer time out from 16msec to 4 5
106. re Don t touch the components or contacts on a board Hold a board by its edges or by its metal mounting bracket Do not handle or store system boards near strong electrostatic electromagnetic magnetic or radioactive fields Working with Batteries Care and Handling Precautions for Lithium Batteries Your computer board has a standard nonrechargeable lithium battery Do not short circuit Do not heat or incinerate Do not charge Do deform or disassemble not apply solder directly not mix different types or partially used batteries together Always observe proper polarities xi Replacing Lithium Batteries Exercise caution while replacing lithium batteries AN gt P gt P WARNING Danger of explosion if battery is incorrectly replaced Replace only with the same or equivalent type recommended by the manufacturer Dispose of used batteries following manufacturer s instructions ATTENTION Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du m me type ou d un type quivalent recommand par le constructeur Mettre au rebut les batteries usag es conform ment aux instructions du fabriquant ACHTUNG Explosionsgefahr bei falschem Batteriewechsel Verwenden Sie nur die empfohlenen Batterietypen des Herstellers Entsorgen Sie die verbrauchten Batterien laut Gebrauchsanweisung des Herstellers ATENCION Puede ex
107. re monitored any low power rail holds the board in reset Most power rails also can be monitored through the LPC bus by using the WINBOND W83627HF or by using the embedded IPMI controller im Bios Settings 04101 Section 5 1 2 6 1 2 Monitoring Menu Selection Intelligent System Monitoring Hardware Monitor Voltage Inputs 2 10 2 5 3 Programmable Dual Stage Watchdog A two stage digital watchdog timer with software programmable time out period is available Following a reset of any source the watchdog is disabled Software enables the watchdog Bios Settings FEES e Monitoring gt Watchdog After POST Enable watchdog automatically before OS launch ERR e Monitoring gt Watchdog Duration e Monitoring gt FPGA IRQ Software Usage lt e registers 0x190 0x191 and 0x196 description in Appendix for details e Application Note 3 for watchdog timer usage This App note gives bad info on CP6011 0x192 0x196 0x190 register 2 6 Video Interface The video controller ATI Mobility M with its integrated 4MBcapable of CRT resolutions up to 1600 x 1200 x 65K colors 4MB RAM The video interface features high performance 32 bit frame buffer PCI video Signal Paths Video signals are available through J3 CPCI connector Related Jumpers W2 5 6 enables or disables the onboard video See Section 3 1 Jumper Settings Tal Bios Settings ER Advanced PCI Configuration Default Primary Vid
108. refetchable reads or 32 bit Posted Memory Write Force 64 bit Control 9 cycles on one side will be converted to 64 bit cycles on Secondary completion to target side if target supports 64 bit transfers Primary Enabled After a prefetch command the remaining prefetched data will NOT be discarded but will be available for the next Read Disabled Command with consecutive address 32 PCICLK 64 PCICLK When Smart Prefetch is Enabled the prefetched data is only Smart Prefetch Timeout 456 pCICLK discarded upon a Timeout 256 PCICLK Controls Secondary PCI bus Prefetch behaviour no effect when in PCI X mode Tf set to By EEPROM the values shown are taken from the By EEPROM Bridge and are not available for change This happens if a valid EEPROM content is detected and were loaded by the Prefetching scheme dde ms Bridge omma The default aggressive Prefetching may affect the overall Manual performance with some PCI Masters that cannot prefetch a lot of data due to limited buffers size or other reasons Tf set to Manual the options can be changed for optimum performance which depends on the PCI device s present 1 2 Controls initial Prefetch Cache Lines count on the Primary bus PCIX Primary Initial during reads to prefetchable memory space Prefetch count 8 This value defines the cache line multiples for the initial 8 prefetch count 16 5 8 Controls initial Prefetch Dwords count the Secondary bus PCI Sec
109. removing components Refer to the installation instructions in this user s guide for precautions and procedures If you have any questions please contact Kontron Technical Support WARNING High voltages are present inside the chassis when the unit s power cord is plugged into an electrical outlet Turn off system power turn off the power supply and then disconnect the power cord from its source before removing the chassis cover Turning off the system power switch does not remove power to components viii When Working Inside a Computer Before taking covers off a computer perform the following steps Turn off the computer and any peripherals Disconnect the computer and peripherals from power sources or subsystems to prevent electric shock or systemboard damage This does not apply to when hot swapping parts Follow the guidelines provided in Preventing Electrostatic Discharge on the following page Disconnect telephone or telecommunications lines from the computer In addition take note of these safety guidelines when appropriate To help avoid possible damage to system boards wait five seconds after turning off the computer before removing a component removing a system board or disconnecting a peripheral device from the computer When you disconnect a cable pull on its connector or on its strain relief loop not on the cable itself Some cables have a connector with locking tabs If you are disconnecting t
110. rting a board in a live system will never make the bus not function with compliant hardware A peripheral card will have a problem if the bus is faster than the card s capability In other cases the card should initialize itself with the current bus mode 2 8 IPMI This product fully supports Intelligent Platform Management Interface 1 5 IPMIv1 5 and PICMG2 9R1 0 specifications All its functionalities run under an autonomous management controller even if the board is held in reset or power down by a management card within a system design for High Availability such as XL VHDS and XL LP42 While the CP6011 IPMI implementation is fully compliant to IPMI v1 5 and should work with any System Management Software that respect this specification it has been design to be easily integrate with the Service Availability Forum Hardware Platform Interface SAF HPT specification You can find more information about the SAF HPI at the following Web site http www saforum org home 2 8 1 Technical Background is an extensible and open standard that defines autonomous system monitoring It is autonomous because all management controllers within a compact PCI chassis monitor its own sensors and send critical events through a dedicated bus to a Baseboard Management Controller BMC that logs it into a non volatile System Event Log SEL The CP6011 IPMI implementation include a device SDR module that allows the user s System Management Software
111. sable Non Maskable Interrupt NMI Get CPU type Initialize system hardware De shadow BIOS code Initialize chipset with initial POST values Set IN POST flag Verify CMOS and RTC validity E 1 Code Beeps POST Routine Description Initialize CPU registers Enable CPU cache Initialize caches to initial POST values Initialize 1 0 component Initialize the local bus IDE Initialize Power Management Load alternate registers with initial POST values Restore CPU control word during warm boot Initialize PCI Bus Mastering devices Initialize keyboard controller BIOS ROM checksum Initialize cache before memory autosize 8254 timer initialization 8237 DMA controller initialization Reset Programmable Interrupt Controller Test DRAM refresh Test 8742 Keyboard Controller Set ES segment register to 4 GB Enable A20 line Autosize DRAM Initialize POST Memory Manager Clear 512 KB base RAM Enhanced CMOS init RAM failure on address line xxxx RAM failure on data bits xxxx of low byte of memory bus Enable cache before system BIOS shadow RAM failure on data bits xxxx of high byte of memory bus Test CPU bus clock frequency Initialize Phoenix Dispatch Manager CMOS test on Suspend to Disk resume Register re initialization Warm start shut down Shadow system BIOS ROM Cache re initialization Autosize cache Advanced configuration of chipset registers Load alternate registers with CMOS values Initialize interrup
112. set BMC BMC_PRG When 1 set BMC in program mode COM2 is redirected to BMC to allow bootstrapping the microcontroller BMC_LOCK When TEST 15 1 BMC_LOCK has no effect on BMC_RST bit When TEST 15 0 and BMC_LOCK is 0 BMC_RST bit is in normal operation When TEST is 0 and BMC_LOCK is 1 BMC is in Reset P_COM2 Redirected postcode on serial port when is set to 1 READ WRITE NU NU Action D7 D6 D5 D4 D3 D2 D1 BMC LOCK P COM2 TEST NU BMC 2EXT BMC LOCK P COM2 NU D6 D5 D4 D3 D2 D1 00 1 5 0 GA4 GA3 GA2 GA1 GAO NU NU NU NU NU NU NU DO BMC_COM BMC_RST BMC_PRG BMC_COM BMC_RST BMC_PRG Signal routing follow this table Address ISA 3 0 BMC_PRG TAKE_COM2_N BMC_COM Routing 0 SIO to buffers default BMC RXD 1 1 SIO to BMC Buffers TXD 1 X BMCto buffer Host RXD 1 X SIO to BMC Buffers TXD 1 0 0 0 1 Action D3 D2 01 00 READ ISA3 ISA2 ISA1 ISA1 WRITE ISA3 ISA2 ISA1 ISA1 ISA IRQ number 14 01A1H INTERRUPT ENABLE Address 0x1A0 SW_EN WD_EN ENUM_EN Action D3 D2 01 00 READ NU WRITE NU SW_EN SW_EN WD_EN WD_EN ENUM_EN ENUM_EN Set this bit to enable interrupt on switch event Enable watchdog interrupt Enable ENUM interrupt The interrupt is generated for both onboard CPCI interface and the mezzanine CPCI interface On this SBC the PLX6540 PCIX PCIX bridge can handle the ENUM event as an alternate way 15 01A2H INTERRUPT STATUS
113. st command 1 NetFn Group Extension response LUN 2 Command ID 08 3 Completion code 00 4 cPCI ID Extension 00 5 LED State XX 7 3 reserved 2 1b if Lamp Test has been enabled 1 1b if Override has been enabled 0 1b if Local Control has been enabled 6 Local Control LED Function XX 00 LED is OFF FFh LED is ON 7 Local Control On duration 00 Local control Blinking state is not supported this byte will be set to Oh 8 Local Control Color 01 Response 01h BLUE command 9 Override state LED Function XX This byte is returned if either Override state or Lamp Test is in effect 00 LED Override state is OFF 01h FAh LED Override state is BLINKING The off duration is specified by the value of this byte and the on duration is specified by the value of byte 10 Both values specify the time in tens of milliseconds 10ms 2 5s FBh FEh Reserved FFh LED Override state is ON 10 Override state On duration XX This byte is returned if either Override state or Lamp Test is in effect The LED on time in tens of milliseconds if 01h lt Byte 7 lt FAh and otherwise 11 Override State Color 01 01h BLUE 12 Lamp Test Duration XX This byte is not returned if Lamp Test is not in effect This byte contains the Lamp Test remaining time in hundreds of milliseconds 2 20 Get FRU LED Properties The Get FRU LED Properties command allows SMS to determine
114. st be populated in pairs Hub Interface_A to ICH3 S 266 MB s point to point Hub Interface 1 5 8 bit connection to ICH3 S 66 MHz base clock running 4X data transfers Isochronous support Parallel termination mode only 64 bit addressing on inbound transactions maximum 16 GB memory decode space Hub Interface_B Hub Interface_C and Hub Interface_D e RASUM 1 GB s point to point Hub Interface 2 0 66 MHz base clock running 8x 1 GB s data transfers Supports snooped and non snooped inbound accesses Parallel termination mode only 64 bit addressing on inbound transactions maximum 16 GB memory decode space 32 bit outbound addressing supported for PCI X Hub Interface_A protected by parity Hub Interface_B D protected by ECC Memory auto initialization by hardware implemented to allow main memory to be initialized with valid ECC Memory scrubbing supported Note lt gt Many errors can be monitored setting the DMI event BIOS menu such as ECC errors parity errors on all PCI PCI X buses and more See the BIOS section for details 2 2 3 Memory Interface This product supports up to two Gigabytes on 2 x 200 pin latching SO DIMM sockets Supported memory includes PC 1600 PC 2100 DDR 2 5V registered SDRAM non ECC ECC mode The MCH memory controller is capable of up to a nibble error correction and multiple nibble error detection via There are two DDR channels 72 bit
115. stems In addition Kontron will not retest or recertify systems or components that have been reconfigured by customers Limited Warranty Kontron Canada Inc The seller warrants its boards to be free from defects in material and workmanship for a period of two 2 years commencing on the date of shipment The liability of the seller shall be limited to replacing or repairing at the seller s option any defective units Equipment or parts which have been subject to abuse misuse accident alteration neglect or unauthorized repair are not covered by this warranty This warranty is in lieu of all other warranties expressed or implied xviii 1 Product Description Contents Overview 1 1 L2 tl RE Ed ad 1 2 13 BoardSpecifications 1 2 14 CompactPCI Compliance 1 6 15 HaotSwaptapaln ly isis 1 6 1 6 Interfacing with the Environment 1 9 1 7 Compatibility with Kontron Products 1 11 1 0 1 1 Product Overview The CP6011 is without a doubt the most powerful CompactPCI CPU engine you can getina single slot 4HP Its use of the Intel Pentium M and Low Voltage Pentium M processors at 1 6GHz 1 8GHz and at 2 0GHz and 1 1GHz and future speeds when they become available guarantees performance and high density The low power features of the Pentium M processor make it possible to fit in a single s
116. t swap indicator LED Response command Response command JT 00 HG NetFn Group Extension request LUN Command ID cPCI ID Extension FRU Device ID LED ID 00h BLUE Hot swap LED LED Function 00h LED OFF Override O1h FAh LED BLINKING Override The off duration is specified by the value of this byte and the on duration is specified by the value of byte 7 Both values specify the time in tens of milliseconds 10ms 2 5s FBh LAMP TEST state Turn on LED for duration specified in byte 7 in hundreds of milliseconds then return to the highest priority state LED state restored to Local Control state FDh FEh Reserved FFh LED ON Override On duration LED on time in tens of milliseconds if 1 lt Byte 6 lt FAh Lamp Test time in hundreds of milliseconds if Byte 6 FBh Lamp Test time value must be less than 128 Other values when Byte 6 FBh are reserved Otherwise this field is ignored and shall be set to Oh Color when illuminated O1h Use BLUE OEh Do not change OFh Default color NetFn Group Extension response LUN Command ID 08 Completion code cPCIID Extension 2 19 e Get FRU LED State The Get FRU LED State command returns the state of the FRU s BLUE hot swap LED including whether a Lamp Test or Override state is enabled for it NetFn Group Extension request LUN Command ID cPCI ID Extension FRU Device ID LED ID 00h BLUE Hot swap LED Reque
117. t vectors POST device initialization Check ROM copyright notice Check video configuration against CMOS E 2 Code Beeps POST Routine Description Initialize PCI bus and devices 1 0 81h PCI Bus tested Initialize all video adapters in system QuietBoot logo start Shadow video BIOS ROM Display BIOS copyright notice Multi Boot Boot menu support Initialization Display CPU type and speed Initialize EISA board Test keyboard Set key click if enabled USB initialization legacy support Enable Keyboard Test for unexpected interrupts Initialize POST display service Display prompt Press DEL to enter SETUP Disable CPU cache Test RAM between 512 and 640 KB Test extended memory Test extended memory address lines Jump to UserPatch1 Configure advanced cache registers Early Initialize of Multi Processor APIC Enable external and CPU caches Setup System Management Mode SMM area Display external L2 cache size Load custom defaults optional Display shadow area message Clear Memory Display error messages Test for configuration error detected Test RTC Check for keyboard errors Set up hardware interrupt vectors Intelligent System Monitoring initialization Initialize coprocessor if present Disable onboard Super 1 0 ports and IRQs for Auto detection Late POST device initialization Detect and install external RS232 ports Configure non Motherboard Configurable Device IDE controllers Detect and ins
118. tall external parallel ports Initialize PC compatible PnP ISA devices E 3 Code Beeps POST Routine Description Re initializes onboard 1 0 ports Configure Motherboard Configurable Devices optional Initialize BIOS Data Area Enable Non Maskable Interrupts NMIs Initialize Extended BIOS Data Area Test and initialize PS 2 mouse Initialize floppy controller Determine number of ATA drives optional Initialize hard disk controllers auto detect IDE drives Initialize local bus hard disk controllers Jump to UserPatch2 Build MPTABLE for multi processor boards Install CD ROM for boot Clear huge ES segment register Fixup Multi Processor table Search for option ROMs One long two short beeps on checksum failure Check for SMART Drive optional Set up Power Management Initialize security engine optional Enable hardware interrupts Determine number of ATA and SCSI drives optional Set time of day Initialize Typematic rate Erase DEL prompt Scan for DEL key stroke Enter SETUP Clear Boot flag Check for errors POST done prepare to boot operating system One short beep before boot Terminate QuietBoot optional Check password optional ACPI initialization Prepare Boot Initialize DMI parameters Clear parity checkers Display MultiBoot menu Clear screen optional Display Summary Screen Try to boot with INT 19 Initialize POST Error Manager PEM E 4 Code Beeps POST Routine Descri
119. te of the board e AHEALTHY signal indicates the healthiness of the board 1 5 5 1 Bus less operation When the onboard bridge is disabled the CP6011 is considered bus less In such case the SBC can be hot swapped in a CPCI bus but will not try to participate on the bus Then BDSEL and HEATHY preserve their functionality but PCIRST is ignored The blue led mechanism from the bridge is disabled since the onboard bridge and system host can t handle it However itis possible to read the handle switch and control the blue LED through the register 0x192 Note lt When bridge is disabled Stand alone operation user can read the hot swap switch and drive blue LED using register 0x192 The BMC can overwrite this register 1 6 Interfacing with the Environment 1 6 1 CPCI The CP6011 system peripheral processor board is provided for rack mounted systems to offer the highest modularity Through the J1 J2 segment the board can drive up to seven external CompactPCI slots supporting individual REQ GNT arbitration pair signals and the clock The CP6011 supports all PCI and PCI X modes for operation up to 133MHz giving a theoretical throughput of 1GB s Possible PCI modes of the CP6011 with Kontron systems XL VHDS 1 XL PSB XL LP41 XL LP42 CP6011 PCI 33 PCI 33 PCI 33 PCI 33 PCI 66 PCI 66 PCIX 66 PCIX 100 1 Using a five slot backplane Call technical support for 133MHz backplane availability 1 6 2 RTM rear transition m
120. tem management cards and RTM See your system s manual for more details 4 1 1 Backplane The CP6011 is fully compatible with the XL PSB XL LP41 XL LP42 and XL VHDS If using a third party system consult you system s manual determine the system s compatibility with the CP6011 J1 and J2 connectors must be compatible with PICMG2 0R3 0 Note J1 and J2 are de facto industry standard as defined by PICMG2 0R3 0 The J3 connector is user defined Pinouts vary from vendor to vendor Backplanes should be feed through with the exception of PICMG2 16R1 0 compliant system which routes Ethernet signals into the backplane J4 and J5 are defined by users and vary from vendor to vendor and should be feed through Systems that do not meet this requirement may permanently damage the CP6011 Contact Kontron Technical Support to verify pinout compatibility with other chassis backplanes 4 1 4 1 2 Rear Panel 1 0 This feature is intended to issue the 1 0 capabilities of the CP6011 to the rear of the enclosure using 1 0 80 2 1 0 module gathers all the 1 0 signals of the CPU board and makes them easily accessible through standard headers and connectors located at the rear of enclosure For more information about the 80 2 transition module please consult our web site at www kontron com Note The 6011 detect older RTMs such as the 80 2 which forces the CP6011 to remain off This protection onl
121. tform management hardware Clear SEL No Select YES if you want to clear all contents of the IPMI Yes System Event Log on next boot only Indicates the current use assigned to the Watchdog Timer None IPMI Watchdog BIOS POST BIOS POST Watchdog Timer used by the BIOS POST Timer Use OS Load Both OS Load OS Load Timeout This mode requires SMS or OS support ae SEC Initial BIOS Timer Countdown Value Countdown min OS Load Ti 30 sec 1 min 2 min 4 min 8 min 16 min or 32 Initial OS Load Timer Countdown Value Countdown kn Initial OS Load timeout action None OS Load Timer Hard Rst None no action Action Pwr Down Hard Reset Pwr Cycle Power Down Power cycle 5 17 5 1 2 5 9 1 Device and Firmware Information Feature Static information Description Kontron board identifier Product ID 6011 Provide a numeric value that identifies a particular System or board type IPMI specification version IPMI Version 115 E This field holds the version of the IPMI specification that the controller is compatible with Device ID 3 IPMIimplementation ID used with this product ID SE Provide a numeric value that identifies a particular controller type Device Revision 0 3 02 IPMI firmware revision Revision SDR Revision 7 Sensor Data Records package revision CPCI Slot 8 Number 5 1 2 5 9 2 FRU Board Information Feature Board Product Number Board Serial Number
122. th and with any PCI or PCI X frequency up to 133MHz 2 7 1 1 Transparent Mode When the CP6011 is inserted in the system slot of a backplane the bridge is configured in transparent mode and performs like any other bridge You can configure important registers from the BIOS setup The board will power up depending on board options system slot 3 3V or 5V 2 7 1 2 Nontransparent Mode If the SBC is inserted in a peripheral slot the PLX6540 will be configured in nontransparent mode and will be seen as an 1 0 device By default it will appear with vendor ID 3388h and device ID 0029h The PLX6540 will always claim a 16MB window unless the default is changed in the EEPROM settings The board will work in either a 3 3V or 5V backplane 2 12 2 7 1 3 Busless Operation When used in a busless slot as in some PICMG2 16 systems the bridge will be disabled and will disappear from the PCI device list 2 7 1 4 Using the EEPROM If you use this product as 1 0 board you can assign different vendor ID and device ID to the PLX6540 and can configure the PCI resources that will be claimed at boot up This allows the CP6011 to act as an 1 0 board like any other peripheral device SCSI Ethernet and to load proper drivers Please contact Kontron s technical support if you need to configure the EEPROM Related Jumpers W6 W7 W8 allow you to set maximum bus speed or disable the bridge mm Bios Settings PETS Advanced gt PCI Configuration gt
123. tus PCI bus X device 0 function 3 LAN link status PCI bus X device 0 function 2 LAN3 link status PCI bus X device 1 function 0 Board 1 2V supply On board DC DC converter from 3 3V Mainly used for memory Board 1 8V supply Voltage provided for external IPMB bus Board 5 Volts supply Board 3 3 Volts supply Total current from baseboard and mezzanine on 5V supply Total current from baseboard and mezzanine on 3 3V supply CPU NMIinterrupt has occur CPU remain in SMI interrupt state for to much time Indicated if upper mezzanine PMC Site A is installed Indicated if bottom mezzanine PMC Site B is installed Information about board ejector power off fault status CPU Thermal trip alarm Thermal over heat indication CPU throttling in action PICMG 2 9 required sensor device on IPMB1 require attention Indicates if the backplane is PCI enabled otherwise PICMG 2 16 might be present System slot in VIO 5V CPCI backplane PMC VIO Error check VIO jumpers Indicates if the management Slink is recognized 2 8 3 2 8 3 1 High Availability Facilities IPMI extension for control You will find below the standard IPMI formatted commands that may be used within a High Available System that use abstraction layer such as SAF HPI Set FRU LED State The Set FRU LED State command allows the state of the FRU LEDs to be controlled by the SMS On the CP6011 the command provides facilities to control the BLUE ho
124. uietBoot displays the QuietBoot Screen a graphic illustration created by the computer manufacturer instead of the text based POST screen which displays a number of PC diagnostic messages To exit the QuietBoot screen and run Setup display the Multiboot menu or simply display the PC diagnostic messages you can simply press one of the hot keys described below The QuietBoot Screen stays up until just before the operating system loads unless e You press lt ESC gt to display the POST screen e You press Del to enter Setup e POSTissues an error message e The BIOS or an option ROM requests keyboard input The following explains each of these situations 5 1 3 2 Press lt 5 gt 1 Pressing lt ESC gt switches the POST screen and The boot process continues with the text based POST screen until the end of POST and then displays the BootFirst Menu with these options 1 Loadthe operating system from a boot device of your choice 2 Enter Setup 3 Exit the Boot First Menu with lt ESC gt and load the operating system from the boot devices in the order specified in Setup 5 1 3 3 Press Del Pressing lt Del gt at any time during POST enter Setup 5 1 3 4 Keyboard Input Request If the BIOS or an Option ROM add on card requests keyboard input QuietBoot switches over to the POST screen and the Option ROM displays prompts for entering the information POST continues from there with the regular POST screen 5
125. xpansion and 1 0 mezzanine cards The IDE support is used with the T6508 mezzanine See Kontron s mezzanine offering for additional I O capabilities 1 6 3 1 PMC Expansion The mezzanine increases the 1 0 capability of the CP6011 by providing two PMC slots Up to 133MHZ 64 bits are supported for up to 1GB of I O bandwidth The capability of the CP6011 to connect with other devices is enforced by PCI Mezzanine Cards PMC CP6011 equipped with a SCSI PMC and T6508 mezzanine board may appear as follows 1 10 1 7 Compatibility with Kontron Products The CP6011 system processor is a member of Kontron s CompactPCI product family When building a basic environment around the CP6011 the platform can be composed of any of the following devices XL VHDS XL LP41 CP6011 6U system board up to 17 including other Kontron cPCI SBCs CTM80 2 6Ux8HPx80mm RTM for CP6011 Third party CPCI 1 0 board with RTM as needed Storage module with 2 5 inch hard disk and DVD or floppy Up to 12 hot swappable SCSI drives Up to six 3U 250W power supply Up to two Ethernet switches PICMG2 16 Up to two PMM Platform management module AC or DC redundant 48 volts power input CP6011 6U system board up to 12 including other Kontron cPCI SBC CTM80 2 6Ux8HPx80mm Rear Transition Module for CP6011 Third party CPCI 1 0 board with RTM as needed Up to two 6U 350W power supplies Two Ethernet switches PICMG2 16 AC power input One 7 sl
126. y works with older RTMs from Kontron Canada aA WARNING Always used the right RTM with your front board or permanent damage could occur Note For most PICMG2 16 systems XL PSB and XL LP42 you need to use a special RTM The limitation does not apply to the XL VHDS 4 1 3 Storage Devices CP6011 can support a CompactFlash connected to the system processor through T069 If more storage devices or DVD floppy drives are needed 6U form factor storage modules are supported with the XL VHDS system 3U SCSI trays also are supported in VHDS for very high storage capacity and very high MTBF This requires a SCSI PMC Consult you system s manual for available storage device 4 1 4 Power Supply Use of 3U or 6U Compact PCI power supplies is strongly recommended with the CP6011 Although you can use other power supply types make sure they can handle the power requirement current transient and voltage tolerance Use of an ATX power supply is not recommended 3U and 6U CompactPCI power supply modules feature load sharing redundant mode and hot swap capabilities which allow on site replacements of defective modules while the system remains on 4 1 5 Connector Keying CompactPCI connectors support guide lugs to ensure a correct polarized mating A proper mating is enhanced by the use of color coded keys for 3 3V and 5V operation Color coded keys prevent inadvertent installation of a 5V peripheral system board in a 3 3V slot

CP6011 User's Guide

Contents

Download Pdf Manuals

Related Search

Related Contents