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RocketIO™ Transceiver User Guide

1. Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj D17 4 100 10001 100011 1101 100011 0010 D18 4 100 10010 010011 1101 010011 0010 D19 4 100 10011 110010 1101 110010 0010 D20 4 100 10100 001011 1101 001011 0010 D21 4 100 10101 101010 1101 101010 0010 D22 4 100 10110 011010 1101 011010 0010 D23 4 100 10111 111010 0010 000101 1101 D24 4 100 11000 110011 0010 001100 1101 D25 4 100 11001 100110 1101 100110 0010 D26 4 100 11010 010110 1101 010110 0010 D27 4 100 11011 110110 0010 001001 1101 D28 4 100 11100 001110 1101 001110 0010 D29 4 100 11101 101110 0010 010001 1101 D30 4 100 11110 011110 0010 100001 1101 D31 4 100 11111 101011 0010 010100 1101 D0 5 101 00000 100111 1010 011000 1010 DI 5 101 00001 011101 1010 100010 1010 D2 5 101 00010 101101 1010 010010 1010 D3 5 101 00011 110001 1010 110001 1010 D4 5 101 00100 110101 1010 001010 1010 D5 5 101 00101 101001 1010 101001 1010 D6 5 101 00110 011001 1010 011001 1010 D7 5 101 00111 111000 1010 000111 1010 D8 5 101 01000 111001 1010 000110 1010 D9 5 101 01001 100101 1010 100101 1010 D10 5 101 01010 010101 1010 010101 1010 D11 5 101 01011 110100 1010 110100 1010 D12 5 101 01100 001101 1010 00
2. Attribute Default Default Default GT AURORA GT CUSTOM GT ETHERNET ALIGN COMMA MSB FALSE FALSE FALSE CHAN BOND LIMIT 16 16 1 CHAN BOND MODE OFFO OFF OFF CHAN BOND OFFSET 8 8 0 CHAN BOND ONE SHOT FALSE FALSE TRUE CHAN BOND SEQ 1 1 00101111100 00000000000 00000000000 CHAN BOND SEQ 1 2 00000000000 00000000000 00000000000 CHAN BOND SEQ 1 3 00000000000 00000000000 00000000000 CHAN BOND SEQ 1 4 00000000000 00000000000 00000000000 CHAN BOND SEQ 2 1 00000000000 00000000000 00000000000 CHAN BOND SEQ 2 2 00000000000 00000000000 00000000000 CHAN BOND SEQ 2 3 00000000000 00000000000 00000000000 CHAN BOND SEQ 2 4 00000000000 00000000000 00000000000 CHAN BOND SEQ 2 USE FALSE FALSE FALSE CHAN BOND SEQ LEN 1 1 1 CHAN BOND WAIT 8 8 7 CLK COR INSERT IDLE FLAG FALSE FALSE FALSE CLK COR KEEP IDLE FALSEO FALSE FALSEO CLK COR REPEAT WAIT 12 1 12 COR SEQ 1 1 00111110111 00000000000 00110111100 CLK COR SEQ 1 2 00111110111 00000000000 00001010000 CLK COR SEQ 1 3 001111101110 00000000000 00000000000 CLK COR SEQ 1 4 001111101110 00000000000 00000000000 CLK COR SEQ 2 1 00000000000 00000000000 00000000000 CLK COR SEQ 2 2 00000000000 00000000000 00000000000 RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 33 XILINX Chapter 1 RocketlO Transceiver Overview Table 1 7 Default Attribute Values GT
3. 21 RocketIO Transceiver 24 HDL Code Exar ples ci sind a hee hd wee ee Ree USA RU Ie a 24 List of Available 25 Primitive Attributes 30 Modifiable 35 Byte 39 Chapter 2 Digital Design Considerations IRE EIAS e es Leen Ee Ce ee 41 lok PER E 41 diesque UU 43 Clock Paule rep da igna Up REE org Poe ope ep 45 Digital Clock Manager DCM Examples 45 Example 1 Two Byte Clock with DCH 46 Example 1b Two Byte Clock without DCM eh 49 Example 2 Four Byte Clock 0 1 49 Example 3 One Byte 2 53 Half Rate Clocking 57 Multiplexed Clocking Scheme with 58 Multiplexed Clocking Scheme without 58 RXRECCLK EE 59 Clock Dependency SEET EE
4. FG676 FF896 FF1152 LOC Constraints 2VP20 2VP7 2VP20 2VP30 2VP40 2VP20 2VP30 2VP30 2VP40 2VP50 GT XO YO AF7 AF6 AK27 AK26 AK27 26 AP29 AP28 AP33 AP32 AP33 AP32 AF5 AF4 AK25 AK24 AK25 AK24 AP27 AP26 AP31AP30 AP31AP30 GT X0 7 A6 5 27 26 27 26 29 28 A33 A32 A33 A32 4 25 24 25 24 27 26 A31 A30 A31 A30 GT YO AF12 AF11 AF7 AF6 AK20 AK19 20 19 AP21 AP20 AP29 AP28 AP29 28 10 AF9 AF5 4 AK18 AK17 AK18 AK17 AP19 AP18 AP27 AP26 AP27 AP26 GT A12 All 7 A6 A5 A20 19 A20 A19 A21 A20 A29 A28 A29 A28 A10 A9 4 18 17 18 17 19 18 27 26 27 26 GT X2 YO AF18 AF17 12 11 4 AKI3 AK14 AK13 API7 16 21 20 AP25 AP24 AF16 AF15 AF10 AF9 AK12 AK11 AKI2 AK1 AP15 AP14 AP19 APIS AP23 AP22 GT X2 A18 17 A12 All A14 A13 A14 A13 A17 A16 A21 A20 A25 A24 A16 A15 A10 A9 A12 11 A12 11 15 14 19 18 23 22 GT X3 YO AF23 AF22 8 AF17 AK7 AK6 AK7 AK6 AP9 AP8 AP17 AP16 21 AP20 AF21 AF20 AF16 AF15 AK5 AK4 AK5 AK4 AP7 AP6 AP15 AP14 AP19 AP18 YI 23 22 18 17 7 A6 5 7 6 5 9 8 A7 6 A17 A16 A21 A20 A21 A20 A16 A15 4 4 A15 A14 A19 A18 GT X4 YO AF23 AF22 9 AP8 AP17 AP16
5. 91 Receiver Ue oe E iboats a wae eo 92 Ports and Attributes aw o Ros ge ge oe eae eke arb ides 92 TXBUPFERR m UA a E ERU RR 92 DX USES ee UR baw ma e ER EAR 92 RXBUPSTATUS mE 92 EE 92 Miscellaneous 92 Ports and Attribute Seese Pueri oer ee deg 92 RocketlO Transceiver User Guide www xilinx com 9 06024 v2 4 August 25 2004 3 XILINX RX DATA WIDTH TX_DATA TEEN 92 SERDES LOB EE 93 TERMINATION IMP a m mmm ERR te ee ae AEN 93 TXPOLARITY RXPOLARITY H e E deeg Sup Rete vro aoc Oro Oise 93 TX_DIFF_CTRL PRE EMPHASIS ba karin estate eel ee xe dE eebe dei ai ee toe 93 LOOPBACK oeren eei hp c SE RR eee Roue EE eink a pions a lesa Tig aa nes Eus ea ae 94 Other Important Design Notes 95 Receive Data Path 32 bit Alignment 95 32 bit Alignment 2 97 deeds bano tpe nbn EUER paries 97 AAR 100
6. 116 Figure 3 11 Example Power Filtering PCB Layout for Four MGTs in Device with External Capacitors Bottom 117 Figure 3 12 Single Ended Trace 118 Figure 3 13 Microstrip Edge Coupled Differential 119 Figure 3 14 Stripline Edge Coupled Differential 119 Figure 3 15 AC Coupled Serial 119 Figure 3 16 DC Coupled Serial 120 Figure 3 17 LVPECL Reference Clock Oscillator 121 Figure 3 18 LVPECL Reference Clock Oscillator Interface On Chip Termination 121 Figure 3 19 LVDS Reference Clock Oscillator 121 Figure 3 20 LVDS Reference Clock Oscillator Interface On Chip Termination 121 Chapter 4 Simulation and Implementation Figure 4 1 XC2VP2 Implementation 124 Figure 4 2 XC2VP50 Implementation 124 Appendix A RocketlO Transceiver Timing Model Figure 1 RocketIO Transceiver Block Diagram 130 Figure 2 RocketIO Transceiver Timing Relative to Clock Edge 135 Appendix B 8B 10B Valid Characters
7. Clk2x 180 1 1 DCM LOCKED 1 clk2x 180 USRCLK2 M elk i USRCLK M REFCLKIN REFCLKINBUF 56 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Clocking A UNN Halt Hate Clocking Scheme Some applications require serial speeds between 600 Mb s and 1 Gb s The transceiver attribute SERDES 10B which sets the REFCLK multiplier to 10 instead of 20 enables the half rate speed range when set to TRUE With this configuration the clocking scheme also changes The figures below illustrate the three clocking scheme waveforms when SERDES 10B TRUE Clocks for 1 Byte Data Path SERDES 10B TRUE GT std 1 CLKDV divide by 2 REFCLKSEL REFCLK IBUFGDS DCM REFCLK REFCLK_P CLKIN CLKDV TXUSRCLK TXUSRCLK CLKFB RXUSRCLK RXUSRCLK TXUSRCLK2 RST CLKO RXUSRCLK2 LILILS TXUSRCLK2 RXUSRCLK2 MGT clock input invert Figure 2 6 One Byte Data Path Clocks SERDES 10B TRUE ers acceptable skew UG024_29_013103 Clocks for 2 Byte Data Path 0 REFCLKSEL SERDES 10B TRUE IBUFGDS REFCLK P dE TXUSRCLK REFCLK REFCLK N TXUSRCLK2 RXUSRCLK2 RXUSRCLK RXUSRCLK2 Figure 2 7 Two Byte Data Path Clocks SERDES 10B TRUE CLKDV divide by 2 06024 30 013103
8. a pape e ee wile epe Ex WEE PA 76 1 _ _ EORR 76 EX BUFFER USE S etos ead 77 ULE COR SED E o eer Le 77 CLE COR SEQ e EE 77 CLK COR INSERT IDLE FLAG CLK COR KEEP IDLE CLK COR REPEAT WAIT o eres prx Spr vr PESE EDO e 78 Synchronization 79 Jal PATH EE 79 8 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 XILINX Poits and Attributes Eege Zoe ed ess ee e doe RU aria desk 79 RXCLKCORQNT rb dak EE cs US e Rt oae 79 RX LOS INVALID INCR RX LOS THBRSHOEDS Causae aoi ae ah c RERO 80 RX LOSS OP SYNC PSM 255224495 bh ote o tme e Ue e UR ede E ae 80 RXLOSSOESYNG EE us UPC ING que REUS us 80 Channel Bonding Channel Alignment 81 ee roti die Mone E 81 Channel Bonding Alignment 82 Ports and Attributes iesu esser aer hr RR 83 CHAN BOND 83 and ore r a bx RESERVE VENAE NEN 83
9. Table A 4 Parameters Relative to the TX User Clock2 TXUSRCLK2 Parameter Setup Hold Function Signals CFGEN Control inputs CONFIGENABLE Control inputs TXBYPASSSBIOB 3 0 TCRCE TGcgc Control inputs TXFORCECRCERR GC kc TP OL Control inputs TXPOLARITY TINH Control inputs TXINHIBIT LBK Control inputs LOOPBACK 1 0 RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 133 XILINX Appendix A RocketlO Transceiver Timing Model Table A 4 Parameters Relative to the TX User Clock2 TXUSRCLK2 Continued Parameter Toccx_TRST Tecxc_TRST Toccx_TKCH TgcKc_TKCH Toccx_TCDM Tgcxc_TCDM Function Control inputs Control inputs Control inputs Signals TXRESET TXCHARISK 3 0 TXCHARDISPMODE 3 0 Tacck TCDV Control inputs TXCHARDISPVAL 3 0 Tapck Data inputs CONFIGIN Tenge TOAT Tace Data inputs TXDATA 31 0 Clock to Out lt TBERR TKERR TGckpo TRDIS Status outputs Status outputs Data outputs TXBUFERR TXKERR 3 0 TXRUNDISP 3 0 TGckpo CFGOUT Data outputs CO
10. 3 XILINX 84 Chapter 2 Digital Design Considerations These CBSs should be unique from other delimiters in the data stream including Clock Correction Sequence IDLE Start of Frame and End of Frame As with clock correction there are multiple sequences that can be defined GT CUSTOM only The primary CBS is defined by CHAN BOND SEQ 1 where a number from 1 to 4 If a second CBS is required CHAN BOND SEQ 2 USE must be set to TRUE and CHAN BOND SEQ 2 usedto definethe second CBS otherwise CHAN BOND SEQ 2 USE should be left at its default value FALSE See Receiving Vitesse Channel Bonding Sequence page 68 for the bit breakdown of the sequence definition Finally CHAN BOND SEQ LEN defines the CBS length as 1 to 4 bytes When set to anything other than 4 only those sequences are defined For example if CHAN BOND SEQ LEN is set to 2 only CHAN BOND SEQ 1 1 and CHAN BOND SEQ 1 2 need to be defined CHAN BOND WAIT CHAN BOND OFFSET CHAN BOND LIMIT These three attributes define how the Master performs channel alignment of the RX buffer The typical values of these attributes are CHAN BOND WAIT 8 CHAN BOND WAIT roughly defines the maximum number of bytes by which the Slave can lag the Master Due to internal pipelining the equation should be CHAN BOND WAIT 3 5 bytes of bytes Slave may lag Master For example if CHAN BOND WAIT 8 the Slave may lag the Master by 4 5 bytes W
11. Clocks for 4 Byte Data Path 1 Rn 0 REFCLKSEL SERDES 10B TRUE ELE REFCLK P REFCLK REFCLK REFCLK CLKIN CLK FX180 TXUSRCLK RXUSRCLK TXUSRCLK2 TXUSRCLK RXUSRCLK2 RXUSRCLK TXUSRCLK2 RXUSRCLK2 GT std 4 06024 31 013103 Figure 2 8 Four Byte Data Path Clocks SERDES 10B TRUE RocketlO Transceiver User Guide www xilinx com 57 06024 v2 4 August 25 2004 A XILINX Chapter 2 Digital Design Considerations Multiplexed Clocking Scheme with DCM Following configuration of the FPGA some applications might need to change the frequency of its REFCLK depending on the protocol used Figure 2 9 shows how the design can use two different reference clocks connected to two different DCMs The clocks are then multiplexed before input into the RocketIO transceiver User logic can be designed to determine during auto negotiation 1f the reference clock used for the transceiver is incorrect If so the transceiver must then be reset and another reference clock selected IBUFGDS REFCLK P GT std 2 REFCLK N REFCLK2 P REFCIK z REFCLK2 REFCLK2_N REFCLKSEL TXUSRCLK2 RXUSRCLK2 TXUSRCLK RXUSRCLK REFCLKSEL Use of 2 5 is required to maintain correct IBUFG DCM BUFGMUX topology for clock skew compensation 06024 05a 112202 Figure 2 9 Multiplexed REFCLK with DCH Multiplexed Clocking Scheme without DCM As with
12. bob EH wees 53 One Byte Data Path Clocks SERDES 10B TRUE 57 Two Byte Data Path Clocks SERDES 10B 57 Four Byte Data Path Clocks SERDES 10 57 Multiplexed REFCLK with 58 Multiplexed REFCLK without DCM 58 Using RXRECCLK to Generate RKUSRCLK and RXUSRCLK2 59 8B 10B Data BOW ER ERR CS hx Rea cepe ex Re e E 64 10 Bit TX Data Map with 8 10 68 10 Bit RX Data Map with 8 10 68 8B 10B Parallel to Serial Conversion 69 4 Byte Serial 69 Synchronizing Comma Align Signals to RKRECCLK 71 MGT Comma Control Flip Flop Ideal Locations 72 Bottom MGT Comma Control Flip Flop Ideal 72 Clock Correction in 75 RXLOSSOFSYNC FSM States 80 Channel Bonding 81 CRC Packet Format MERE Eee V 86 USER MODE FIBRE CHAN Mode 88 Ethernet Losses eret p eade p OE M ER me 89 Infini
13. 1 THEN sync hold 0 ELSE IF wait to sync 0000 THEN IF rxchariscomma3 OR rxchariscommal 1 THEN sync hold lt 1 END IF END IF END IF END IF END PROCESS This process generates aligned data with commas aligned in 31 24 assuming that incoming commas are aligned to 31 24 or 15 8 Here you could add code to use ENPCOMMAALIGN and ENMCOMMAALIGN to enable a move back into the byte 0 state PROCESS usrclk2 rxreset BEGIN IF rxreset 1 THEN rxdata reg lt 0000000000000000 rxdata hold 00000000000000000000000000000000 rxisk reg 00 rxisk hold 0000 byte sync 0 ELSIF usrclk2 EVENT AND usrclk2 1 THEN rxdata reg 15 DOWNTO 0 rxdata 15 DOWNTO 0 rxisk reg 1 DOWNTO 0 rxisk 1 DOWNTO 0 IF rxchariscomma3 1 THEN rxdata hold 31 DOWNTO 0 rxdata 31 DOWNTO 0 rxisk hold 3 DOWNTO 0 lt rxisk 3 DOWNTO 0 byte sync 0 ELSE IF rxchariscommal OR byte sync 1 THEN rxdata hold 31 DOWNTO 0 rxdata reg 15 DOWNTO 0 amp rxdata 31 DOWNTO 16 rxisk hold 3 DOWNTO 0 lt rxisk reg 1 DOWNTO 0 amp rxisk 3 DOWNTO 2 byte sync 1 ELSE rxdata hold 31 DOWNTO 0 lt rxdata 31 DOWNTO 0 rxisk hold 3 DOWNTO 0 rxisk 3 DOWNTO 0 END IF END IF END IF END PROCESS END ARCHITECTURE translated 102 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25
14. ENMCOMMAALIGN to enable a move back into the byte 0 state always 9 posedge usrclk2 or posedge rxreset begin if rxreset begin rxdata reg 16 h0000 aligned data 32 h0000 0000 rxisk reg lt 2 b00 aligned rxisk lt 4 b0000 byte sync lt 1 b0 end else begin rxdata reg 15 0 rxdata 15 0 rxisk reg 1 0 rxisk 1 0 if rxchariscomma3 begin aligned data 31 0 lt rxdata 31 0 aligned rxisk 3 0 rxisk 3 0 byte sync m 17502 end else if rxchariscommal byte sync begin aligned data 31 0 lt rxdata reg 15 0 rxdata 31 16 aligned rxisk 3 0 lt rxisk reg 1 0 rxisk 3 2 byte sync lt else begin aligned data 31 0 rxdata 31 0 aligned rxisk rxisk end end end endmodule align comma 32 VHDL kkkkxkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkk kkkkkkkkkx k ck ck ce ck ck ce ck ck ke ck ck ck ck ck XILINX IS PROVIDING THIS DESIGN CODE OR INFORMATION AS IS AS A COURTESY TO YOU SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES BY PROVIDING THIS DESIGN CODE OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE APPLICATION OR STANDARD XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
15. 3 125b s Diff TX 1 800 25 VSEL 11 RDIV 1 SPEED 1 TESTEN 1EMN 3x PEENE a ara 2 TXP Channel 1 90 e pooma DATAN Bu NE BE Meet oe breed Ped Loge Lon 090024 18 020802 Figure 3 3 K28 5 with Pre Emphasis RocketlO Transceiver User Guide www xilinx com 107 06024 v2 4 August 25 2004 A XILINX Chapter 3 Analog Design Considerations ug024 36 031803 Figure 3 4 Eye Diagram 10 Pre Emphasis 20 FR4 Worst Case Conditions 2vpT 3 2Gbps Differential 100 Avccaux2 36V Vix 1 8V Vcore 11 Emp 11 Data PRES 277 1 FF672 Rev C Board 1 ug024_37_031803 Figure 3 5 Eye Diagram 33 Pre Emphasis 20 FR4 Worst Case Conditions 108 www xilinx com RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 Differential Receiver Differential Receiver XILINX The differential receiver accepts the Vp Vy signals carrying out the difference calculation Vp Vy electronically input data must be differential and nominally biased to a common mode voltage of 0 5 V 2 5 V or AC coupled Internal terminations provide for simple 50Q or 75Q transmission line connection See Figure 3 6 RXP Pin 500r 75o VTRX AVCCAUXRX Ba Pullup Network 4 PMA RXP e RXN 50 or 75o RXN Pin Figure 3 6 GNDA Ver 47 Receiver The differential receiver parameters are sho
16. 69 HDL Code Examples Transceiver Bypassing of 8B 10B 69 SERDES 70 OVervIeW D E Hebd eed REDE PER PEG Ead prx eee 70 Eelere IG ae A pa eee EE AE EE 70 Deserializer RR ek IERI RE REG RR Re CER 70 Ports and Attributes CREE CER ER 70 ALIGN COMMA MSB RUA PR ARR X etapa RU FCR YS 70 ENPCOMMAALIGN BENMCOMMAALIGN e EE CC RE Pe ER OR E ERR EP ERR Ren 71 PCOMMA DETECT MCOMMA DETEGCT hk erh 73 COMMA 10B MASK PCOMMA 10B VALUE MCOMMA e EE 73 DEC PCOMMA DETECT DEC MCOMMA DETECT DEC VALID COMMA ONLY 73 5 we DMRS SEE EASE Ee SRY Sd Oe EU VERD 73 RXCHARISCOMMA bee Re eee ee 74 RXCOMMADET 6 ees Pw X send ceed Ee seen 74 Clock 74 quoe d ddp eee 74 Clock 4 74 Clock and Data Recovery ee ee a Hee ades a 75 Clock Correction Ped eT ERO Per o eR eed 75 Ports and Attributes sis
17. CHAN BOND WAIT 8 CHAN BOND OFFSET CHAN BOND WAIT CHAN BOND LIMIT 2 x CHAN BOND WAIT Lower values are not recommended Use higher values only if channel bonding sequences are farther apart than 17 bytes 82 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Channel Bonding Channel Alignment A XILINX Table 2 19 shows different settings for CH AN BOND ONE SHOT and ENCHANSYNC in Master and Slave applications Table 2 19 Master Slave Channel Bonding Attribute Settings Master Slave CHAN BOND ONE SHOT TRUE or FALSE as desired FALSE ENCHANSYNC Dynamic control as desired Tie High Ports and Attributes CHAN BOND MODE An MGT can be designated as one of three types when used in a channel bonding scheme The type is designated by HAN BOND MODE the three values of which are MASTER SLAVE 1 HOP and SLAVE 2 HOPS A fourth mode OFF is used when channel bonding is not being performed The Master always controls for itself and for Slaves of either type when channel bonding and clock correction will occur Masters are always connected directly to a SLAVE 1 HOP and indirectly to a SLAVE 2 HOPS via daisy chain through SLAVE 1 HOP This topology improves the timing characteristics of the CHBONDO and CHBONDI buses ENCHANSYNC ENCHANSYNC controls when channel bonding is enabled Table 2 19 shows the recommended settings for Master and Slaves To counter the possibility of a bit erro
18. RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Timing Parameters A UNN Timing Parameters Parameter designations are constructed to reflect the functions they perform as well as the I O signals to which they are synchronous The following subsections explain the meaning of each of the basic timing parameter designations used in the tables Setup Hold Times of Inputs Relative to Clock Basic Format ParameterName SIGNAL where ParameterName with subscript string defining the timing relationship SIGNAL of RocketIO signal synchronous to the clock ParameterName Format Tauck Setup time before clock edge Tgcxx Hold time after clock edge where x C Control inputs D Data inputs Setup Hold Time Examples 5 RRST Setup hold times of RX Reset input relative to rising edge of RXUSRCLK2 Setup hold times of TX Data inputs relative to rising edge of TXUSRCLK2 Clock to Output Delays Basic Format ParameterName SIGNAL where ParameterName with subscript string defining the timing relationship SIGNAL of RocketIO signal synchronous to the clock ParameterName Format Tack Delay time from clock edge to output where x CO Control outputs DO Data outputs ST Status outputs Output Delay Time Examples TaGckco CHBO Rising edge of RXUSRCLK to Channel Bond outputs TGckpo RDAT Rising e
19. Version 1 0 Revision Initial Xilinx release 01 23 02 1 1 Updated for typographical and other errors found during review 02 25 02 1 2 Part of Virtex II Pro Developer s Kit March 2002 Release 07 11 02 1 3 Updated PCB Design Requirements Added Appendix A RocketIO Transceiver Timing Model Changed Cell Models to Appendix B 09 27 02 1 4 Added additional IMPORTANT NOTE regarding ISE revisions at the beginning of Chapter 1 Added material in section Cyclic Redundancy Check Added section Other Important Design Notes New pre emphasis eye diagrams in section Pre emphasis Techniques Numerous parameter additions previously shown as TBD in MGT Package Pins 10 16 02 1 5 Corrected pinouts for FF1152 package device column 2VP20 30 LOC Constraints rows GT_X0_Y0 and Corrected section Latency and Table 2 20 to express latency in terms of TXUSRCLK and RXUSRCLK cycles Corrected sequence of packet elements in Figure 2 30 11 20 02 1 6 Table 1 2 Added support for XAUI Fibre Channel Corrected max PCB drive distance to 40 inches Reorganized content sequence in Chapter 2 Digital Design Considerations Table 1 5 Additional information in RKCOMMADET definition Code corrections in VHDL Clock templates Data Path Latency section expanded and reformatted Corrections in clocking scheme drawings Addit
20. XAPP652 Word Alignment and SONET SDH XAPP660 Partial Reconfiguration of RocketIO Pre emphasis and Differential Swing Control Attributes 20 0 0 eee XAPP661 RocketIO Transceiver Bit Error Rate Tester XAPP662 In Circuit Partial Reconfiguration of RocketIO Attributes XAPP669 PPC405 PPE Reference System Using Virtex II Pro RocketlO Transeivers ENEE eee ers Rue DRE PUES XAPP670 Minimizing Receiver Elastic Buffer Delay in the Virtex II Pro RocketlO TransCetver sees pymes eee dew eee XAPP680 HD SDI Transmitter Using Virtex II Pro RocketIO Multi Gigabit TANSCCIV EIS eege d late eta et ee uie s D eco e Ee DE ae ee XAPP681 HD SDI Receiver Using Virtex II Pro RocketIO Multi Gigabit ECH XAPP683 Multi Rate HD SD SDI Transmitter Using Virtex II Pro RocketIO Multi Gigabit Transceivers XAPP684 Multi Rate HD SD SDI Receiver Using Virtex II Pro RocketIO Multi Gigabit Transceivers XAPP687 64 66 Encoder Decoder eese XAPP763 Local Clocking for MGT RXRECCLK in Virtex II Pro Devices Characterization Virtex II Pro RocketIO Multi Gigabit Transceiver Characterization Virtex II Pro RocketlO MGT HSSDC
21. e RocketIO CRC support is implementable for single channel use only Computation and byte striping of CRC across multiple bonded channels is not supported For that usage the CRC logic can be implemented in the FPGA fabric www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Fabric Interface Buffers A UNN e The RocketIO transceiver does not compute the 16 bit variant CRC used for Infiniband and thus does not fulfill the Infiniband CRC requirement Infiniband CRC can be computed in the FPGA fabric e AIL CRC formats have minimum allowable packet sizes These limits are larger than those set by the user mode and are defined by the specific protocol Fabric Interface Buffers Overview Transmitter and Elastic Receiver Buffers Both the transmitter and the receiver include buffers FIFOs in the data path This section gives the reasons for including the buffers and outlines their operation Transmitter Buffer FIFO The transmitter buffer s write pointer TXUSRCLK is frequency locked to its read pointer REFCLK Therefore clock correction and channel bonding are not required The purpose of the transmitter s buffer is to accommodate a phase difference between TXUSRCLK and REFCLK Proper operation of the circuit is only possible if the FPGA clock TXUSRCLK is frequency locked to the reference clock REFCLK Phase variations of up to one clock cycle are allowable A simple FIFO suffices for this
22. If RX LOSS OF SYNC FSM TRUE RXLOSSOFSYNC indicates the state of the FSM Bit 1 Loss of sync High Bit 0 Resync state High If RX LOSS OF SYNC FSM FALSE RXLOSSOFSYNC indicates Bit 1 Received data invalid High Bit 0 Channel bonding sequence recognized High Serial differential port FPGA external RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 25 XILINX Chapter 1 RocketlO Transceiver Overview Table 1 5 5 GT AURORA GT FIBRE CHANO GT ETHERNET GT INFINIBAND and GT XAUI Primitive Ports Continued Port RXNOTINTABLE Port Size 1 2 4 Definition Status of encoded data when the data is not a valid character when asserted High Applies to the byte mapping scheme Serial differential port FPGA external RXPOLARITY Similar to TXPOLARITY but for and RXP When de asserted assumes regular polarity When asserted reverses polarity RXREALIGN Signal from the PMA denoting that the byte alignment with the serial data stream changed due to a comma detection Asserted High when alignment Occurs RXRECCLK Clock recovered from the data stream by dividing its speed by 20 RXRESET Synchronous RX system reset that recenters the receive elastic buffer It also resets 8B 10B decoder comma detect channel bonding clock correction logi
23. Input Value Mode Description Normal Mode is selected during normal operation The transmitted data is sent out the differential transmit ports TXN 00 Normal Mode TXP and are sent to another transceiver without being sent to its own receiver logic During normal operation LOOPBACK should be set to 00 RocketlO Transceiver User Guide www xilinx com 93 06024 v2 4 August 25 2004 7 XILINX Chapter 2 Digital Design Considerations Table 2 23 LOOPBACK Modes Input Value Mode Description Internal Parallel Internal Parallel Mode allows testing the transmit and receive 01 M i interface logic PCS without having to go into the PMA section of the transceiver or to another transceiver See Figure 2 28 Internal Serial Mode is used to check that the entire transceiver is working properly including testing of 8B 10B encoding decoding This emulates what another transceiver would receive as data from this specific transceiver design Since the TXP TXN pins are still being driven during this loopback mode PCB traces on these pins should be terminated to remove reflections otherwise loopback bit errors could result Internal Serial mm 10 Mod Termination can be accomplished by any of a variety of methods Two examples Connect SMA terminators the TXP TXN SMA connectors if applicable or simply use 50Q resistors on the transmitter backplane pins Connect the u
24. The POWERDOWN 4 122 Chapter 4 Simulation and Implementation Simulation Models 123 123 LSV Le ER EE 123 Implementation 18 123 Par T ee T RE 123 MGT Package 125 Appendix A RocketlO Transceiver Timing Model Timing Parameters ened 131 Setup Hold Times of Inputs Relative to 131 10 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 XILINX Clock to Output Del ys en Phe eiie bea Rien Clock Pulse Width 2 Timing Parameter Tables and Appendix B 8B 10B Valid Characters Valid Data Character Valid Control Characters Appendix C Related Online Documents Application 65 OEE Eee CURES ERR XAPP648 Serial Backplane Interface to a Shared Memory XAPP649 SONET Rate Conversion in Virtex II Pro Devices XAPP651 SONET and OTN
25. they can be connected with vias close to where the signals change layers To control crosstalk serial differential traces should be spaced at least five trace separation widths from all other PCB routes including other serial pairs A larger spacing is required if the other PCB routes carry especially noisy signals such as TTL and other similarly noisy standards The RocketIO transceiver is designed to function at 3 125 Gb s through 40 inches of PCB with two high bandwidth connectors Longer trace lengths require either a low loss dielectric or considerably wider serial traces Differential Trace Design The characteristic impedance of a pair of differential traces depends not only on the individual trace dimensions but also on the spacing between them The RocketIO transceivers require either a 1000 or 1500 differential trace impedance depending on whether the 50 2 or 750 termination option is selected To achieve this differential impedance requirement the characteristic impedance of each individual trace must be slightly higher than half of the target differential impedance A field solver should be used to determine the exact trace geometry suited to the specific application Figure 3 12 This task should not be left up to the PCB vendor W W 7 9 mil 0 201 mm H 5 0 mil 0 127 mm 20 500 Reference Plane 00024 21 042903 Figure 3 12 Single Ended Trace Geometry Trace lengths up to 20 in 4 may be of
26. 2004 A XILINX Appendix B 8 10 Valid Characters Table B 1 Valid Data Characters Continued Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj D19 0 000 10011 110010 1011 110010 0100 D20 0 000 10100 001011 1011 001011 0100 D21 0 000 10101 101010 1011 101010 0100 D22 0 000 10110 011010 1011 011010 0100 D23 0 000 10111 111010 0100 000101 1011 D24 0 000 11000 110011 0100 001100 1011 D25 0 000 11001 100110 1011 100110 0100 D26 0 000 11010 010110 1011 010110 0100 D27 0 000 11011 110110 0100 001001 1011 D28 0 000 11100 001110 1011 001110 0100 D29 0 000 11101 101110 0100 010001 1011 D30 0 000 11110 011110 0100 100001 1011 D31 0 000 11111 101011 0100 010100 1011 1 001 00000 100111 1001 011000 1001 DI 1 001 00001 011101 1001 100010 1001 D2 1 001 00010 101101 1001 010010 1001 D3 1 001 00011 110001 1001 110001 1001 D4 1 001 00100 110101 1001 001010 1001 05 1 001 00101 101001 1001 101001 1001 D6 1 001 00110 011001 1001 011001 1001 D7 1 001 00111 111000 1001 000111 1001 D8 1 001 01000 111001 1001 000110 1001 D9 1 001 01001 100101 1001 100101 1001 D10 1 001 01010 010101 1001 010101 1001 D11 1 001 01011 110100 1001 1
27. 2004 SC XILINX Chapter 3 Analog Design Considerations Serial UO Description The RocketIO transceiver transmits and receives serial differential signals This feature operates at a nominal supply voltage of 2 5 VDC A serial differential pair consists of a true Vp and a complement Vj set of signals The voltage difference represents the transferred data Thus Vp VparA Differential switching is performed at the crossing of the two complementary signals Therefore no separate reference level is needed A graphical representation of this concept is shown in Figure 3 1 AVCCAUXTX Pullup Network 50Q or 75Q TXP pin PMA TXP PMA TXN VTTX 500 or 750 gt pin GNDA Ve 46 021704 Figure 3 1 Differential Amplifier The RocketIO transceiver is implemented in Current Mode Logic CML A CML output consists of transistors configured as shown in Figure 3 1 CML uses a positive supply and offers easy interface requirements In this configuration both legs of the driver Vp and Vy sink current with one leg always sinking more current than its complement The CML output consists of a differential pair with 500 or optionally 75 2 source resistors The signal swing is created by switching the current in a common drain differential pair The differential transmitter specification is shown in Table 3 1 page 105 Table 3 1 Differential Transmitter Para
28. AF21 AF20 AP7 AP6 AP15 AP14 GT X4 YI 23 A22 9 8 7 A17 A16 A21 A20 A6 15 14 GT X5 YO 5 APA AP13 AP12 AP3 AP2 AP10 GT X5 YI A5 A4 A3 A13 A12 A2 All A10 GT X6 YO AP9 8 AP7 AP6 GT X6 YI 9 8 A7 6 7 0 5 4 AP3 AP2 GT X7 5 4 2 GT X8 YO GT X8 YI GT X9 YO GT X9 YI 126 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 lt XILINX Table 4 3 LOC Grid amp Package Pins Correlation for FF1517 and FF1704 LOC FF1517 FF1704 Constraints 2VP40 2VP50 2VP70 2VP70 2VP100 GT X0 YO AW36 AW35 AW36 AW35 36 AW35 BB41 BB40 BB39 AW34 AW33 AW34 AW33 AW34 AW33 BB38 GT A36 A35 A34 A33 A36 A35 A34 A33 36 A35 A34 A33 41 A40 A39 A38 GT XI YO AW32 AW31 AW32 AW31 BB37 BB36 BB35 AW30 AW29 AW30 AW29 BB34 GT A32 A31 A30 29 A32 A31 A30 29 A37 A36 A35 A34 GT XO YO AW24 AW23 AW28 AW27 AW32 31 BB33 BB32 BB31 AW22 AW21 AW26 AW25 AW30 AW29 BB30 GI X2 Yi A24 A23 A22 A21 A28 A27 A26 A25 A32 A31 A30 A29 A33 A32 A31 A30 GT X3 YO 19 AWI8 AW24 AW23 AW28 AW27 BB29 BB28 BB27 AWI17 AW16 AW22 AW21 AW26 AW25 BB26 GT X3 A19 A18 A17 A16 A24 A23 A22 A21 A28 A27 A26 A25 A29 A28 A27 A26 GT X4 Y
29. Appendix C Related Online Documents 14 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Schedule Chapter 1 of Tables RocketlO Transceiver Overview Table 1 1 Number of RocketIO Cores per Device 21 Table 1 2 Communications Standards Supported by RocketIO Transceiver 21 Table 1 3 Serial Baud Rates and the SERDES 10B Attribute 22 Table 1 4 Supported RocketIO Transceiver 24 Table 1 5 CUSTOM D GT AURORA GT FIBRE CHANO GT ETHERNET 0 GT INFINIBAND and GT XAUI Primitive 25 Table 1 6 RocketIO Transceiver Attributes 30 Table 1 7 Default Attribute Values AURORA GT CUSTOM GT ETHERNET 35 Table 1 8 Default Attribute Values GT FIBRE CHAN GT INFINIBAND and GI coti de puc RUPPEPLPb ERE PRESS 37 Table 1 9 Control Status Bus Association to Data Bus Byte Paths 39 Chapter 2 Digital Design Considerations Table 2 1 Clock 42 Table 2 2 Reference Clock 42 Table 2 3 BREFCLK Pin Numbers 43 Table 2 4 Data Width Clock 4
30. CHAN BOND ONE SHOT ENN ba vas AEN 83 CHAN BOND SEQ CHAN BOND SEQ LEN CHAN BOND SEQ EE 84 CHAN_BOND WAIT CHAN BOND OFFSET CHAN BOND LIMIT 84 CHBONDDONE x2pRbXEEXUadg 2854 24 os DAS OS WAM OS EEN OE DEY SEE SENSU 85 CHBONDI CHBONDO Rex ONE OM BaP a SAE Os AE ee qued pace 85 RXCLKCORCNT RXLOSSOFSYING be OSES Swans SENE DENS PES DEE SE NER 85 Troubleshooting Rer eee RIEN HERI eer ed 85 CRC Cyclic Redundancy 86 OVerVIeW ee 86 CRE Opetaliotn 5 ee deben Ri pp ueber eoe usi bet 86 CRG Generation EE 86 ee 87 Ports and Attributes isses ERRARE 4 GA EIER RE E da 87 TX CRC USE RX Led e vobi Mkt denen 87 CRE 25 aud e n Rae GR ee um 87 CRC START OF PACKET CRC END OF PACKET ENEE dE AEN 90 RXCHECKINGCRC 4 diee pe drained e ceed dies baeo eiae a 91 TXFORCECRCERR TX CRC FORCE VALUE E Tor bio Se eg 91 RocketIO CRC Support Limitations e 91 Fabric Interface 91 Overview Transmitter and Elastic Receiver Buffers 91 Transmitter Buffer
31. DCM demi CLKFB USRCLK M CLKIN REFCLKINBUF DSSEN 1 bO PSCLK 1 bo PSEN 1 bo PSINCDEC 1 bo RST 1 bo CLKO i CLK90 C CLK180 CLK270 CLK2X 2 CLK2X180 CLKDV clkdv2 CLKFX C CLKFX180 LOCKED DCM LOCKED PSDONE STATUS LI jee BUFG bufi I clkdv2 O USRCLK2 M ye BUFG buf2 I clk i 0 USRCLK IBUFG buf3 I REFCLKIN 52 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Clocking XILINX 0 REFCLKINBUF endmodule Example 3 One Byte Clock This is the 1 byte data path width clocking scheme example USRCLK2 M is twice as fast as USRCLK M It is also phase shifted 180 for falling edge alignment Clocks for 1 Byte Data Path for 1 Byte Data Path REFCLK REFCLKSEL GT std 1 TXUSRCLK erc DCM REFCLK RXUSROLK N CLKIN CLK2X180 TXUSRCLK2 CLKFB RXUSRCLK2 LI LJ LJ LJ RXUSRCLK2 RST RXUSRCLK 06024 04 112202 Figure 2 5 One Byte Clock VHDL Template Module ONE BYTE CLK Description VHDL submodule DCM for 1 byte GT Device Virtex II Pro Family library IEEE use IEEE std logic 1164 all pragma translate off library UNISIM use UNISIM VCOMPONENTS ALL pragma translate on entity ONE BYTE CLK is port REFCLKIN in std logic RST in std
32. These attributes help control how clock correction is implemented RocketlO Transceiver User Guide www xilinx com 77 06024 v2 4 August 25 2004 3 XILINX Chapter 2 Digital Design Considerations CLK COR INSERT IDLE FLAG is a TRUE FALSE attribute that defines the output of the RXRUNDISP port When set to TRUE RXRUNDISP is raised for the first byte of each inserted repeated clock correction sequence 8B 10B decoding enabled When set to FALSE default RXRUNDISP denotes the running disparity of RXDATA 8B 10B decoding enabled CLK COR KEEP IDLE is a TRUE FALSE attribute that controls whether or not the final byte stream must retain at least one clock correction sequence When set to FALSE default the clock correction logic is allowed to remove all clock correction sequences if needed to recenter the elastic buffer When set to TRUE it forces the clock correction logic to retain at least one clock correction sequence per continuous stream of clock correction sequences Example Elastic buffer is 75 full and clock correction is needed is the defined clock correction sequence Data stream written into elastic buffer DO IDLE IDLE IDLE IDLE D1 D2 Data stream read out of elastic buffer COR KEEP IDLE FALSE DO D1 D2 Data stream read out of elastic buffer CLK_COR_KEEP IDLE TRUE 0 D1 D2 CLK COR REPEAT WAIT is an integer attribute 0 31 that contro
33. and FF1152 126 Table 4 3 LOC Grid amp Package Pins Correlation for FF1517 and 1704 127 Appendix A RocketlO Transceiver Timing Model Table A 1 RocketIO Clock Descriptions 129 Table A 2 Parameters Relative to the RX User Clock RXUSRCLK 132 Table A 3 Parameters Relative to the RX User Clock2 RXUSRCLK2 133 Table A 4 Parameters Relative to the TX User Clock2 TXUSRCLK2 133 Table 5 Miscellaneous Clock 134 Appendix B 8B 10B Valid Characters Table B 1 Valid Data Characters 137 Table B 2 Valid Control Characters 145 Appendix C Related Online Documents www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 SC XILINX Preface About This Guide The RocketIO Transceiver User Guide provides the product designer with the detailed technical information needed to successfully implement the RocketIOTM multi gigabit transceiver in Virtex II Pro Platform FPGA designs RocketlO Features The RocketIO transceiver s flexible programmable features allow a multi gigabit serial transceiver to be easily integrated into any Virtex II Pro design Guide Contents Variable speed full duplex transceiver allowing 600 Mb
34. 0 mil 0 127 mm 201 55 30 20 55 30 Zopirr 1002 Reference Plane 06024 22 042903 Figure 3 13 Microstrip Edge Coupled Differential Pair Reference Plane 1 7 Y 7 W4 3 0 mil 0 076 mm 2 Wa 3 0 mil 0 076 mm 2 P 1 2 10 0 mil 0 254 mm 2 201 64 80 7 E Dielectric Reference Plane TRUE Figure 3 14 Stripline Edge Coupled Differential Pair AC and DC Coupling AC coupling use of DC blocking capacitors in the signal path should be used in cases where transceiver differential voltages are compatible but common mode voltages are not Some designs require AC coupling to accommodate hot plug in and or differing power supply voltages at different transceivers This is illustrated in Figure 3 15 Capacitors of value 0 01 uF in a 0402 EIA package are suitable for AC coupling at 3 125 Gb s when 8B 10B encoding is used Different data rates and different encoding schemes may require a different value M 06024 23 042503 Figure 3 15 AC Coupled Serial Link DC coupling direct connection is preferable in cases where RocketIO transceivers are interfaced with other RocketIO transceivers or other Mindspeed transceivers that have compatible differential and common mode voltage specifications Passive components are not required when DC coupling is used This is illustrated in Figure 3 16 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004
35. 4 August 25 2004 SC XILINX Chapter 4 Simulation and Implementation Simulation Models SmartModels HSPICE SmartModels are encrypted versions of the actual HDL code These models allow the user to simulate the actual functionality of the design without having access to the code itself A simulator with SmartModel capability is required to use SmartModels The models must be extracted before they can be used For information on how to extract the SmartModels under ISE 5 1i see Solution Record 15501 HSPICE is an analog design model that allows simulation of the RX and TX high speed transceiver To obtain these HSPICE models go to the SPICE Suite Access web page at http support xilinx com support software spice spice request htm Implementation Tools Par For place and route the transceiver has one restriction This is required when channel bonding is implemented Because of the delay limitations on the CHBONDO to CHBONDI ports linking of the Master to a Slave 1 hop must run either in the X or Y direction but not both In Figure 4 1 the two Slave 1 hops are linked to the master in only one direction To navigate to the other slave a Slave 2 hops both X and Y displacement is needed This slave needs one level of daisy chaining which is the basis of the Slave 2 hops setting Figure 4 2 shows the channel bonding mode and linking for a 2VP50 which optionally contains more transceivers 16 per chip Rocke
36. 4 August 25 2004 SC XILINX Preface About This Guide e Appendix A RocketIO Transceiver Timing Model Timing parameters associated with the RocketIO transceiver core Appendix B 8B 10B Valid Characters Valid data and K characters e Appendix C Related Online Documents Bibliography of online Application Notes Characterization Reports and White Papers For More Information For a complete menu of online information resources available on the Xilinx website visit http www xilinx com virtex2pro or refer to Appendix C Related Online Documents For a comprehensive listing of available tutorials and resources on network technologies and communications protocols visit http www iol unh edu training Additional Resources For additional information go to http support xilinx com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Tutorials Description URL Tutorials covering Xilinx design flows from design entry to verification and debugging http support xilinx com support techsup tutorials index htm Answer Browser Database of Xilinx solution records http support xilinx com xInx xil_ans_browser jsp Application Notes Descriptions of device specific design techniques and approaches http support xilinx com apps appsweb htm Data She
37. 4 RXRECCLK cycles invalid data no comma received RESYNC LOSS OF SYNC comma received 06024 40 031803 Figure 2 21 RXLOSSOFSYNC FSM States SYNC ACQUIRED RXLOSSOFSYNC 00 In this state a counter is decremented by 1 but not past 0 for a valid received symbol and incremented by RX LOS INVALID INCR for an invalid symbol If the count reaches or exceeds RX LOS THRESHOLD the FSM moves to state LOSS OF SYNC Otherwise if a channel bonding alignment sequence has just been written into the elastic buffer or if a comma realignment has just occurred the FSM moves to state RESYNC Otherwise the FSM remains in state SYNC ACQUIRED RESYNC RXLOSSOFSYNC 01 The FSM waits in this state for four RXRECCLK cycles and then goes to state SYNC ACQUIRED unless an invalid symbol is received in which case the FSM goes to state LOSS OF SYNC LOSS OF SYNC RXLOSSOFSYNC 10 The FSM remains in this state until a comma is received at which time it goes to state RESYNC 80 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Channel Bonding Channel Alignment A UNN Channel Bonding Channel Alignment Overview Some gigabit I O standards such as XAUI specify the use of multiple transceivers in parallel for even higher data rates Words of data are split into bytes with each byte sent over a separate channel transceiver See Figure 2 22 In Transmitters Full word SSSS sent over four channels one byte
38. 9 10 Valid Characters 8B 10B encoding includes a set of Data characters and K characters Eight bit values are coded into 10 bit values keeping the serial line DC balanced K characters are special Data characters designated with a CHARISK K characters are used for specific informative designations Table B 1 and Table B 2 show the Data and K tables of valid characters Valid Data Characters Table B 1 Valid Data Characters Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj 0 0 000 00000 100111 0100 011000 1011 D1 0 000 00001 011101 0100 100010 1011 D2 0 000 00010 101101 0100 010010 1011 D3 0 000 00011 110001 1011 110001 0100 D4 0 000 00100 110101 0100 001010 1011 D5 0 000 00101 101001 1011 101001 0100 D6 0 000 00110 011001 1011 011001 0100 D7 0 000 00111 111000 1011 000111 0100 D8 0 000 01000 111001 0100 000110 1011 D9 0 000 01001 100101 1011 100101 0100 D10 0 000 01010 10101 1011 010101 0100 D11 0 000 01011 110100 1011 110100 0100 D12 0 000 01100 001101 1011 001101 0100 D13 0 000 01101 101100 1011 101100 0100 D14 0 000 01110 011100 1011 011100 0100 D15 0 000 01111 010111 0100 101000 1011 D16 0 000 10000 011011 0100 100100 1011 D17 0 000 10001 100011 1011 100011 0100 D18 0 000 10010 010011 1011 010011 0100 RocketlO Transceiver User Guide www xilinx com 137 06024 v2 4 August 25
39. AURORA GT CUSTOM GT ETHERNET Continued Attribute Default Default Default GT AURORA GT CUSTOM GT ETHERNET CLK COR SEQ 2 3 00000000000 00000000000 00000000000 CLK COR SEQ 2 4 00000000000 00000000000 00000000000 CLK COR SEQ 2 USE FALSE FALSE FALSE CLK COR SEQ LEN 40 1 2 CLK CORRECT USE TRUE TRUE TRUE COMMA 10B MASK 1111111111 1111111000 1111111000 CRC END OF PKT K29 7 K29 7 Note 6 CRC FORMAT USER MODE USER MODE ETHERNET CRC START OF PKT K27 7 27_7 Note 6 DEC MCOMMA DETECT TRUE TRUE TRUE DEC PCOMMA DETECT TRUE TRUE TRUE DEC VALID COMMA ONLY TRUE TRUE TRUE MCOMMA 10B VALUE 1100000101 1100000000 1100000000 MCOMMA DETECT TRUE TRUE TRUE PCOMMA 10B VALUE 0011111010 0011111000 0011111000 PCOMMA DETECT TRUE TRUE TRUE REF CLK V SEL 0 0 0 RX BUFFER USE TRUE TRUE TRUE RX CRC USE FALSE FALSE FALSE RX_DATA_WIDTH NO 2 NO RX DECODE USE TRUE TRUE TRUE RX LOS INVALID INCR 12 1 12 RX_LOS_THRESHOLD 4 2 4 4 2 RX LOSS OF SYNC FSM TRUEO TRUE TRUEO SERDES 10B FALSE FALSE FALSE TERMINATION_IMP 500 50 500 TX BUFFER USE TRUE TRUE TRUE TX CRC FORCE VALUE 110101100 11010110 110101100 TX USE FALSE FALSE FALSE TX_DATA_WIDTH NO 2 NO 34 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Modifiable Primitives XILINX Table 1 7 Default Attribute Values GT AURORA GT
40. Clock without DCM If TXDATA and RXDATA are not clocked off the FPGA using the respective USRCLK2s then the DCM may be removed from the two byte clocking scheme as shown in Figure 2 3 MGT for 2 Byte Data Path no DCM GT std 2 REFCLKSEL REFCLK TXUSRCLK2 RXUSRCLK2 TXUSRCLK RXUSRCLK Note Implementation tools automatically instantiate the BUFG There is no need to explicitly instantiate in HDL code ug024 02b 062404 Figure 2 3 Two Byte Clock without DCM Example 2 Four Byte Clock If a 4 byte or 1 byte data path is chosen the ratio between USRCLK and USRCLK2 changes The time it take for the SERDES to serialize the parallel data requires the change in ratios The DCM example Figure 2 4 is detailed for a 4 byte data path If 3 125 is required REFCLK is 156 MHz and USRCLK2 M runs at only 78 MHz including the clocking for any interface logic Both USRCLK and USRCLK2 are aligned on the falling edge since USRCLK M is 180 out of phase when using local inverters with the transceiver Note These local MGT clock input inverters shown and noted in Figure 2 4 are not included in the FOUR BYTE CLK templates Clocks for 4 Byte Data Path MGT for 4 Byte Data Path T _std_ CLKDV DIVIDE 2 REFCLK REFCLKSEL IBUFGDS DCM BUFG REFCLK TXUSRCLK REFCLK N CLKIN CLKDV TXUSRCLK2 RXUSRCLK RXUSRCLK2 TXUSRCLK TXUSRCLK2 RST CLKO o RXUSRCLK RXUSRCLK2 MGT cl
41. D10 4 to the value required to invert the running disparity D21 5 or D10 5 Note that CRC generation for EOP requires that the transmitted K28 5 be left justified in the MGT s internal two byte data path Observing the following restrictions assures correct alignment of the packet delimiters 4 byte data path K28 5 must appear in TXDATA 31 24 or TXDATA 15 8 e 2 byte data path K28 5 must appear in TXDATA 15 8 e byte data path K28 5 must be strobed into the MGT on rising TXUSRCLK2 only when TXUSRCLK is High Note Minimum data length for this mode is 24 bytes not including the CRC placeholder Note When CRC FORMAT FIBRE CHAN TX CRC USE must be set to TRUE Otherwise occasional errors will occur in the transmitted data stream HX CRC USE can be either TRUE or FALSE in this usage ETHERNET The Ethernet CRC is more complex Figure 2 25 The SOP EOP and Preamble are neglected by the CRC The extension bytes are special characters in special cases The extension bytes are untouched by the CRC as are the Trail bits which are added to maintain packet length sor Pantie sor recs Ro ss EOP n Bytes 2 to 3 Bytes 06024 13 101602 Figure 2 25 Ethernet Mode Designs should generate only the K28 5 D16 2 IDLE sequence for transmission never K28 5 D5 6 When the RocketIO CRC determines that the running disparity must be inverted to satisfy Gigabit Ethernet requirements it
42. Example 1b Two Byte Clock without DCM the DCMs shown in Figure 2 9 may be removed if TXDATA and RXDATA are not clocked off the FPGA See Figure 2 10 However the transceiver must still be reset when clocks are switched IBUFGDS REFCLK P GT std 2 REFCLK N REFCLK2 P REFUS REFCLK2 REFCLK2 N REFCLKSEL TXUSRCLK2 RXUSRCLK2 TXUSRCLK RXUSRCLK REFCLKSEL BUFGMUX 00024 05b 021503 Figure 2 10 Multiplexed REFCLK without www xilinx com RocketlO Transceiver User Guide 58 UG024 v2 4 August 25 2004 Clocking A XILINX RXRECCLK RXRECCLK is a recovered clock derived by dividing by 20 the received data stream bit rate whether full rate or half rate If clock correction is bypassed it is not possible to compensate for differences in the clock embedded in the received data and the REFCLK created USRCLKs In this case RXRECCLK is used to generate the RXUSRCLKSs as shown in Figure 2 11 RXRECCLK changes monotonically when it changes from being locked to the reference clock to being locked to data and vice versa The recovered bit clock jumps by a maximum of 1 16th of a bit period every eight RXRECCLK cycles 20 ps for a data rate of 3 125 Gb s with a 320 ps bit period in the interpolator RXRECCLK 15 derived from this bit clock through a divide by 20 process When the data input is kept static however the recovered clock does not frequency lock to the reference clock exactly but can deviate f
43. For use with RocketIO transceivers Xilinx requires that this be modified according to the capacitor topology shown in Figure 3 7 The 10 uF capacitor on the input is not changed However the 10 uF output capacitor is replaced with one 330 uF capacitor and eight 1 0 capacitors In cases where more than 16 are powered from a single regulator additional 1 0 capacitor is required for every two additional MGTs Tantalum is the recommended capacitor type for the 330 uF capacitor though the low ESR electrolytic type is also acceptable X7R or X5R ceramic is the recommended capacitor type for the 1 0 UF and 10 uF capacitors These capacitors can be placed anywhere on the board but preferably in close proximity to the regulator T Cm 06024 026 080404 Figure 3 7 Power Supply Circuit Using Approved Regulator Termination Voltage Termination voltages VTTX and VTRX can be of any value in the range of 1 8V to 2 625V VTTX or 1 6V to 2 525 V VTRX In cases where the RocketIO transceiver is interfacing with a transceiver from another vendor termination voltage can be dictated by the specifications of the other transceiver In cases where the RocketIO transceiver is interfacing with another RocketIO transceiver any termination voltage can be used With AVCCAUXTX and AVCCAUXRX already powered with 2 5V an obvious choice for VTTX and VTRX is 2 5V However it should be noted that when AC coupling is used the optimum v
44. Matching the differential traces to within 50 mils 1 27 mm produces a robust design Since signals propagate in PCB traces at approximately 180 ps per inch a difference of 50 mils produces a timing skew of roughly 9 ps Use SI CAD tools to confirm these assumptions on specific board designs signal traces must have an intact reference plane beneath them Stripline and microstrip geometries may be used The reference plane should extend no less than five trace widths to either side of the trace to ensure predictable transmission line behavior Routing of a differential pair is optimally done in a point to point fashion ideally remaining on the same PCB routing layer As vias represent an impedance discontinuity layer to layer changes should be avoided wherever possible It is acceptable to traverse the PCB stackup to reach the transmitter and receiver package pins If serial traces must change layers care must be taken to ensure an intact current return path For this reason routing of high speed serial traces should be on signal layers that share a reference plane If the signal layers do not share a reference plane a 116 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 PCB Design Requirements A UNN capacitor of value 0 01 uF should be connected across the two reference layers close to the vias where the signals change layers If both of the reference layers are DC coupled if they are both ground
45. PCB Design Requirements A UNN UGO24 24 042503 Figure 3 16 DC Coupled Serial Link The RocketIO differential receiver produces the best bit error rates when its common mode voltage falls between 1 6V and 1 8V When the receiver is AC coupled to the line is the sole determinant of the receiver common mode voltage and therefore must be set to a value within this range When two transceivers both terminated with 2 5V are DC coupled the common mode voltage will establish itself at around 1 7V to 1 8V The and voltages for different coupling environments are summarized in Table 3 8 Table 3 8 Recommended and for AC and DC Coupled Environments Coupling VrRX 1 6V to 1 8V 2 5V 5 DC 2 5V 5 1 2 5V 5 1 Notes 1 The recommended voltage for DC coupled implementations is 2 5 V However any voltage is valid as long as both and are the same voltage and within the specifications shown in Table 3 5 page 111 RocketlO Transceiver User Guide www xilinx com 119 UG024 v2 4 August 25 2004 A XILINX Chapter 3 Analog Design Considerations Reference Clock A high degree of accuracy 15 required from the reference clock For this reason it is required that one of the oscillators listed in this section be used Epson EG 2121CA 2 5V LVPECL Outputs See the Epson Electronics America website for detailed info
46. Virtex II Pro internal configuration access port ICAP The solution uses a Virtex II Pro device with an IBM PowerPC 405 PPC405 processor to perform a partial reconfiguration of the RocketIO multi gigabit transceivers MGTs pre emphasis and differential swing control attributes These attributes must be modified to optimize the MGT signal transmission prior to and after a system has been deployed in the field This solution is also ideal for characterization calibration and system testing The hardware and software elements of this solution can be easily integrated into any Virtex II Pro design already utilizing the PLB or OPB bus structures The reference design uses a Xilinx www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Application Notes A UNN intellectual property interface IPIF connecting to either the PLB or OPB buses This design also provides for a terminal interface using a serial port connection allowing MGT attribute settings to be changed through command line entries Design modules are also included to facilitate bit error rate tests BERT and pseudo random binary sequence PRBS diagnostics XAPP669 PPC405 PPE Reference System Using Virtex Il Pro RocketlO Transceivers The PPC405 Packet Processing Engine PPE Reference System using Virtex II Pro RocketIOTM transceivers addresses the need in the digital communications market for high speed data transfer Serial protocols can be cont
47. any width provided that the differential impedance is 1000 or 1500 Trace lengths between 20 and 40 in 4 must be at least 8 mils wide and have a differential impedance of 1000 or 1500 For information on other dielectric materials please contact your Xilinx representative or the Xilinx Hotline Differential impedance of traces on the finished PCB should be verified with Time Domain Reflectometry TDR measurements Tight coupling of differential traces is recommended Tightly coupled traces as opposed to loosely coupled maintain a very close proximity to one another along their full length Since the differential impedance of tightly coupled traces depends heavily on their proximity to each other it 1s imperative that they maintain constant spacing along their full length without deviation If it is necessary to separate the traces in order to route through a pin field or other PCB obstacle it can be helpful to modify the trace geometry in the vicinity of the obstacle to correct for the impedance discontinuity increase the individual trace width where trace separation occurs Figure 3 13 and Figure 3 14 show examples of PCB geometries that result in 100Q differential impedance RocketlO Transceiver User Guide www xilinx com 117 06024 v2 4 August 25 2004 7 XILINX 118 Chapter 3 Analog Design Considerations e Wu sche S H Wo gt W4 6 29 mil 0 160 mm Wo 6 29 mil 0 160 mm S 10 mil 0 254 mm H 5
48. asserted the resets can be asserted The resets must be asserted for two USRCLK2 cycles to ensure correct initialization of the FIFOs Although both the transmit and receive resets can be attached to the same signal separate signals are preferred This allows the elastic buffer to be cleared in case of an over underflow without affecting the ongoing TX transmission The following example is an implementation that resets all three data width transceivers Additional reset and power control descriptions are given in Table 2 8 and Table 2 9 Table 2 8 Reset and Power Control Descriptions Ports Description RXRESET Synchronous receive system reset recenters the receiver elastic buffer and resets the 8B 10B decoder comma detect channel bonding clock correction logic and other receiver registers The PLL is unaffected TXRESET Synchronous transmit system reset recenters the transmission FIFO and resets the 8B 10B encoder and other transmission registers The PLL is unaffected POWERDOWN Shuts down the transceiver both RX and TX sides In POWERDOWN mode transmit output pins TXP TXN are not driven but biased by the state of transmit termination supply VTTX If VTTX is not powered TXP TXN float to a high impedance state Receive input pins RXP RXN respond similarly to the state of receive termination supply VTRX www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Reset Power Down A
49. boundary when plus comma is detected LOOPBACK I 2 Selects the two loopback test modes Bit 1 is for serial loopback and bit 0 is for internal parallel loopback POWERDOWN I 1 Shuts down both the receiver and transmitter sides of the transceiver when asserted High This decreases the power consumption while the transceiver is shut down This input is asynchronous REFCLK I 1 High quality reference clock driving transmission reading TX FIFO and multiplied for parallel serial conversion and clock recovery REFCLK frequency is accurate to 100 ppm This clock originates off the device is routed through fabric interconnect and is selected by REFCLKSEL REFCLK2 I 1 An alternative to REFCLK Can be selected by REFCLKSEL 24 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 List of Available Ports XILINX Table 1 5 5 AURORA GT FIBRE CHANO GT_ETHERNET GT INFINIBAND and GT XAUI Primitive Ports Continued Port REFCLKSEL Port Size 1 Definition Selects the reference clock to use Low selects REFCLK if REF CLK V SEL 0 selects BREFCLK if REF CLK V SEL 1 High selects REFCLK2 if REF CLK V SEL 0 selects BREFCLK2 if REF CLK V SEL 1 See REF CLK V SEL page 31 RXBUFSTATUS Receiver elastic buffer status Bit 1 indicates if an overflow underflow error has occurred when asserted High Bit 0 indicates that the buffer is at least half fu
50. define when RXCOMMADET signals that a comma has been received When only PCOMMA DETECT is TRUE RXCOMMADET signals when a plus comma is received but not a minus comma When only MCOMMA DET is TRUE RXCOMMADET signals when a minus comma is received but not a plus comma If both attributes are TRUE RXCOMMADET will signal when either comma character is received COMMA 10B MASK PCOMMA 10B VALUE MCOMMA 10B VALUE The RocketIO transceiver allows the user to define a comma character using these three attributes The COMMA 10B MASK bits are used in conjunction with PCOMMA 10B VALUE to define a plus comma or MCOMMA 10B VALUE to define a minus comma to define some number of recognized comma characters High bits in the mask condition the corresponding bits in PCOMMA 10B VALUE or MCOMMA 10B VALUE to matter while Low bits in the mask function as a don t care conditioner For example with COMMA 10B MASK setto 1111111000 meaning the three least significant bits don t matter and PCOMMA 10B VALUE is 0011111000 the comma detection unit will recognize the following characters as plus commas 0011111000 K28 7 0011111001 K28 1 0011111010 K28 5 0011111011 through 0011111111 not valid comma characters Using the same value in PCOMMA 10B VALUE but setting COMMA 10B MASK to 1111111111 meaning all the bits in PCOMMA 10B VALUE matter the comma detection unit will recognize only the 0011111000 K28 7 sequence which matches the value of P
51. design or not must be connected to power and ground Unused transceivers may be powered by any 2 5 V source and passive filtering is not required The maximum power consumption per port is 350 mW at 3 125 Gb s operation The POWERDOWN Port POWERDOWN is a single bit primitive port see Table 2 5 page 45 that allows shutting off the transceiver in case it is not needed for the design or will not be transmitting or receiving for a long period of time When POWERDOWN is asserted the transceiver does not use any power The clocks are disabled and do not propagate through the core The 3 state TXP and TXN pins are set High Z while the outputs to the fabric are frozen but not set High Z Any given transceiver that is not instantiated in the design will automatically be set to the POWERDOWN state by the Xilinx ISE development software and will consume no power An instantiated transceiver however will consume some power even if it is not engaged in transmitting or receiving Therefore when a transceiver is not to be used for an extended period of time the POWERDOWN port should be asserted High to reduce overall power consumption by the Virtex II Pro FPGA Deasserting the POWERDOWN port restores the transceiver to normal functional status RocketlO Transceiver User Guide www xilinx com 121 UG024 v2 4 August 25 2004 A XILINX Chapter 3 Analog Design Considerations 122 www xilinx com RocketlO Transceiver User Guide UG024 v2
52. for each byte specified by the byte mapping TXCHARDISPVAL 1 2 4 If 8B 10B encoding is enabled this bus determines what type of disparity is to be sent When 8B 10B is bypassed this becomes the second bit transmitted Bit b of the 10 bit encoded TXDATA bus section see Figure 2 13 page 68 for each byte specified by the byte mapping section TXCHARISK 1 2 4 If 8B 10B encoding is enabled this control bus determines if the transmitted data is a K character or a Data character A logic High indicates a K character 26 RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 www xilinx com List of Available Ports A XILINX Table 1 5 5 AURORA GT FIBRE CHANO GT_ETHERNET GT INFINIBAND and GT XAUI Primitive Ports Continued Port uo Pert Definition Size TXDATAO 8 16 32 Transmit data that can be 1 2 or 4 bytes wide depending on the primitive used TXDATA 7 0 is always the last byte transmitted The position of the first byte depends on selected TX data path width TXFORCECRCERR I 1 Specifies whether to insert error in computed When TXFORCECRCERR TRUE the transmitter corrupts the correctly computed CRC value by XORing with the bits specified in attribute TX CRC FORCE VALUE This input can be used to test detection of CRC errors at the receiver TXINHIBIT I 1 If a logic High the TX differential
53. intended sequence instead of the one after or the one before There are several possibilities that could cause unsuccessful channel bonding e Slaves CBS lagging the master by too much Essentially the Slave does not see a CBS when CHBONDO is asserted e Master CBS lags the slave by too much In this case the slave s CBS sequence has exceeded CHAN BOND LIMIT and has expired CBS sequences appear more frequently than CHAN BOND LIMIT allows causing the Slave to align to a CBS before or after the expected one CRC Cyclic Redundancy Check Overview Cyclic Redundancy Check is a procedure to detect errors in the received data The RocketIO transceiver CRC logic supports the 32 bit invariant CRC calculation used by Infiniband Fibre Channel and Gigabit Ethernet CRC Operation On the transmitter side the CRC logic recognizes where the CRC bytes should be inserted and replaces four placeholder bytes at the tail of a data packet with the computed CRC For Gigabit RocketlO Transceiver User Guide www xilinx com 85 06024 v2 4 August 25 2004 XILINX Chapter 2 Digital Design Considerations Ethernet and Fibre Channel transmitter CRC can adjust certain trailing bytes to generate the required running disparity at the end of the packet This is discussed further in the FIBRE and ETHERNET sections under FORMAT page 87 On the receiver side the CRC logic verifies the received CRC va
54. is forgotten in the presence of subsequent valid characters For example RX LOS INVALID INCR 4 means that four consecutive valid characters after an invalid character will reset the counter RX LOS THRESHOLD determines when the counter has reached the point where the link is considered to be of sync RX LOSS OF SYNC FSM The transceiver s FSM is driven by RXRECCLK and uses status from the data stream prior to the elastic buffer This is intended to give early warning of possible problems well before corrupt data appears on RXDATA RX LOSS OF SYNC FSM a TRUE FALSE attribute indicates what the output of the RXLOSSOFSYNC port see below means RocketlO Transceiver User Guide www xilinx com 79 06024 v2 4 August 25 2004 A XILINX Chapter 2 Digital Design Considerations RXLOSSOFSYNC If RX LOSS OF SYNC FALSE then RXLOSSOFSYNCT I1 High indicates that the transceiver has received an invalid character and RXLOSSOFSYNC 0 High indicates that a channel bonding sequence has been recognized If RX LOSS OF SYNC FSM TRUE then the two bits of RXLOSSOFSYNC reflect the state of the RXLOSSOFSYNC FSM The state machine diagram in Figure 2 21 and the three subsections following describe the three states of the RXLOSSOFSYNC FSM SYNC ACQUIRED count RX LOS THRESHOLD count RX LOS THRESHOLD valid data 4 RXRECCLK cycles channel alignment or comma realignment valid data
55. of data along with a K character signal for a total of 9 bits per character applied If the K character signal is High the data 15 encoded into one of the twelve possible K characters available in the 8B 10B code See Table B 2 page 145 If the K character input is Low the 8 bits are encoded as standard data If the K character input 1s High and a user applies other than one of the twelve possible combinations TXKERR indicates the error 8B 10B Decoder An optional 8B 10B decoder is included in the receiver A programmable option allows the decoder to be bypassed When it is bypassed the 10 bit character order is as shown in Figure 2 14 page 68 The decoder uses the same table that is used for Gigabit Ethernet Fibre Channel and InfiniBand The decoder separately detects both disparity errors and out of band errors A disparity error occurs when a 10 bit character 15 received that exists within the 8B 10B table Table B 1 page 137 but has an incorrect disparity An out of band error occurs when a 10 bit character is received that does not exist within the 8B 10B table It is possible to obtain an out of band error without having a disparity error The proper disparity is always computed for both legal and illegal characters The current running disparity 1s available at the RXRUNDISP signal The 8B 10B decoder performs a unique operation if out of band data is detected Should this occur the decoder signals the error passes th
56. only 60 MHz for half rate operation with a duty cycle between 45 and 55 and should have a frequency stability of RocketlO Transceiver User Guide www xilinx com 41 06024 v2 4 August 25 2004 A XILINX Chapter 2 Digital Design Considerations 100 ppm or better with jitter as low as possible Module of the Virtex Il Pro data sheet gives further details Table 2 1 Clock Ports Clock I Os Description BREFCLK Input Reference clock used to read the TX FIFO and multiplied by 20 for parallel to serial conversion 20X BREFCLK2 Input Alternative to BREFCLK RXRECCLK Output Recovered clock from serial data stream divided by 20 Clocks data into the elastic buffer REFCLK Input Reference clock used to read the TX FIFO and multiplied by 20 for parallel to serial conversion 20X REFCLK2 Input Alternative to REFCLK REFCLKSEL Input Selects which reference clock is used 0 selects REFCLK 1 selects REFCLK2 RXUSRCLK Input Clock from FPGA used for reading the RX Elastic Buffer Clock signals CHBONDI and CHBONDO into and out ofthe transceiver This clock is typically the same as TXUSRCLK TXUSRCLK Input Clock from FPGA used for writing the TX Buffer This clock must be frequency locked to REFCLK for proper operation RXUSRCLK2 Input Clock from FPGA used to clock RX data and status between the transceiver and FPGA fabric The relationship between RXUSRCLK2 and RXUSRCLK depend
57. per channel L Trek 3 Channel lane 0 ri Channel lane 1 Channel lane 2 Channel lane 3 In Receivers Rea Read RXUSRCLK RXUSRCLK 5 RER Palais n d Ell _ Janis Before channel bonding After channel bonding DS083 2 16 010202 Figure 2 22 Channel Bonding Alignment The top half ofthe figure shows the transmission of words split across four transceivers channels or lanes PPPP QQQQ RRRR SSSS and TTTT represent words sent over the four channels The bottom left portion of the figure shows the initial situation in the FPGA s receivers at the other end of the four channels Due to variations in transmission delay especially if the channels are routed through repeaters the FPGA core might not correctly assemble the bytes into complete words The bottom left illustration shows the incorrect assembly of data words QRQQ RSRR etc To support correction of this misalignment the data stream includes special byte sequences that define corresponding points in the several channels In the bottom half of Figure 2 22 the shaded bytes represent these special characters Each receiver recognizes the channel bonding character and remembers its location in the buffer At some point one transceiver designated as the Master instructs all the transceivers to align to the channel bondin
58. the other for when 8B 10B encoding is bypassed The most significant bit of the CCS determines whether it is applicable to an 8 bit encoded or a 10 bit unencoded sequence These sequences require that the encoding scheme allows the comma detection and alignment circuitry to properly align data in the elastic buffer See CORRECT USE above The bit definitions are the same as shown earlier in the Vitesse channel bonding example See Receiving Vitesse Channel Bonding Sequence Table 2 15 Clock Correction Sequence Data Correlation for 16 Bit Data Port Attribute Settings CLK COR SEQ 8 Bit Data Mode 10 BitData Mode Character CHARISK wen 8B 10B Bypass COR SEQ 1 1 00110111100 10011111010 K28 5 1 BC CLK COR SEQ 12 00010010101 11010100010 D21 4 0 95 CLK COR SEQ 13 00010110101 11010101010 D21 5 0 B5 CLK COR SEQ 14 00010110101 11010101010 D21 5 0 B5 COR SEQ LEN To define the CCS length this attribute takes the integer value 1 2 3 or 4 Table 2 16 shows which sequences are used for the four possible settings of CLK COR SEQ LEN Table 2 16 Applicable Clock Correction Sequences CUK COR SEA LEN dree Shat Are Applicable 1 11 21 2 11 12 21 22 3 11 12 13 21 22 23 4 11 12 13 14 21 22 23 24 Notes 1 Applicable only COR SEQ 2 USE is set to TRUE CLK COR INSERT IDLE FLAG CLK COR KEEP IDLE CLK COR REPEAT WAIT
59. width of receiver data path RocketlO Transceiver User Guide www xilinx com 129 06024 v2 4 August 25 2004 XILINX Appendix A RocketlO Transceiver Timing Model PACKAGE PINS MULTI GIGABIT TRANSCEIVER CORE FPGA FABRIC POWERDOWN VTBX Termination Supply RX gt RXRECCLK RXPOLARITY gt RXREALIGN RXCOMMADET ENPCOMMAALIGN ENMCOMMAALIGN RXCHECKINGCRC RXCRCERR RXDATA 15 0 RXDATA 31 16 RXNOTINTABLE 3 0 UU RXP RXN Comma Deserializer Detect Realign A Channel Bonding and Clock Correction gt RXDISPERR 3 0 RXCHARISK 3 0 RXCHARISCOMMA 3 0 RXRUNDISP 3 0 RXBUFSTATUST 1 0 ENCHANSYNC CHBONDDONE CHBONDI 3 0 CHBONDO 3 0 RXLOSSOFSYNC RXCLKCORCNT Serial Loopback Path Parallel Loopback Path M TXP TXN Serializer Output Polarity TXBUFERR TXFORCECRCERR TXDATA 15 0 TXDATA 31 16 TXBYPASS8B10B 3 0 TXCHARISK 3 0 TXCHARDISPMODE 3 0 TXCHARDISPVAL 3 0 TXKERR 3 0 TXRUNDISP 3 0 TXPOLARITY GNDA rx Rx GND AVCCAUXTX 25V TX VTTX Termination Supply TX Figure 1 RocketlO Transceiver Block Diagram m TXINHIBIT LOOPBACK 1 0 TXRESET RXRESET REFCLK REFCLK2 REFCLKSEL BREFCLK BREFCLK2 RXUSRCLK RXUSRCLK2 TXUSRCLK TXUSRCLK2 DS083 2_04_090402 130 www xilinx com
60. 0 0101 100110 0101 D26 2 010 11010 010110 0101 010110 0101 D27 2 010 11011 110110 0101 001001 0101 D28 2 010 11100 001110 0101 001110 0101 D29 2 010 11101 101110 0101 010001 0101 D30 2 010 11110 011110 0101 100001 0101 D31 2 010 11111 101011 0101 010100 0101 D0 3 011 00000 100111 0011 011000 1100 DI 011 00001 011101 0011 100010 1100 D2 3 011 00010 101101 0011 010010 1100 D3 3 011 00011 110001 1100 110001 0011 D4 3 011 00100 110101 0011 001010 1100 D5 3 011 00101 101001 1100 101001 0011 D6 3 011 00110 011001 1100 011001 0011 D7 3 011 00111 111000 1100 000111 0011 D8 3 011 01000 111001 0011 000110 1100 D9 3 011 01001 100101 1100 011010 0011 D10 3 011 01010 010101 1100 100101 0011 D11 3 011 01011 110100 1100 110100 0011 D12 3 011 01100 001101 1100 001101 0011 D13 3 011 01101 101100 1100 101100 0011 D14 3 011 01110 011100 1100 011100 0011 D15 3 011 01111 010111 0011 101000 1100 140 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Valid Data Characters A UNN Table B 1 Valid Data Characters Continued Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj D16 3 011 10000 011011 0011 100100 1
61. 00 1100000000 1100000000 MCOMMA DETECT TRUE TRUE TRUE PCOMMA 10B VALUE 0011111000 0011111000 0011111000 PCOMMA DETECT TRUE TRUE TRUE REF CLK V SEL 0 0 0 RX BUFFER USE TRUE TRUE TRUE RX CRC USE FALSE FALSE FALSE RX_DATA_WIDTH NO NO NO RX DECODE USE TRUE TRUE TRUE 36 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Byte Mapping Table 1 8 Default Attribute Values and GT XAUI Continued GT FIBRE CHAN GT INFINIBAND XILINX Attribute Default Default Default GT FIBRE CHAN GT INFINIBAND GT XAUI RX LOS INVALID INCR 10 10 10 RX LOS THRESHOLD 40 40 40 RX LOSS OF SYNC FSM TRUE D TRUE TRUE SERDES 10B FALSE FALSE FALSE TERMINATION_IMP 500 500 500 TX BUFFER USE TRUE TRUE TRUE TX CRC FORCE VALUE 11010110 11010110 11010110 TX_CRC_USE FALSE FALSE FALSE TX_DATA_WIDTH NO NO NO TX DIFF CTRL 5000 5000 5000 TX PREEMPHASIS 04 00 04 Notes 1 Modifiable attribute for specific primitives 2 Depends on primitive used either 1 2 or 4 3 CRC_EOP and CRC_SOP are not applicable for this primitive Byte Mapping Most of the 4 bit wide status and control buses correlate to a specific byte of TXDATA or RXDATA This scheme is shown in Table 1 9 This creates a way to tie all the signals together regardless of the data path width needed for the CUSTOM other primitives with specific data widt
62. 01001 0110 101001 0110 D6 6 110 00110 011001 0110 011001 0110 D7 6 110 00111 111000 0110 000111 0110 D8 6 110 01000 111001 0110 000110 0110 D9 6 110 01001 100101 0110 100101 0110 D10 6 110 01010 010101 0110 010101 0110 D11 6 110 01011 110100 0110 110100 0110 D12 6 110 01100 001101 0110 001101 0110 D13 6 110 01101 101100 0110 101100 0110 D14 6 110 01110 011100 0110 011100 0110 D15 6 110 01111 010111 0110 101000 0110 D16 6 110 10000 011011 0110 100100 0110 D17 6 110 10001 100011 0110 100011 0110 D18 6 110 01010 010011 0110 010011 0110 RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 143 A XILINX Appendix B 8 10 Valid Characters Table B 1 Valid Data Characters Continued Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj D19 6 110 10011 110010 0110 110010 0110 D20 6 110 10100 001011 0110 001011 0110 D21 6 110 10101 101010 0110 101010 0110 D22 6 110 10110 011010 0110 011010 0110 D23 6 110 10111 111010 0110 000101 0110 D24 6 110 11000 110011 0110 001100 0110 D25 6 110 11001 100110 0110 100110 0110 D26 6 110 11010 0101
63. 1 D3 2 010 00011 110001 0101 110001 0101 D4 2 010 00100 110101 0101 001010 0101 5 2 010 00101 101001 0101 101001 0101 6 2 010 00110 011001 0101 011001 0101 7 2 010 00111 111000 0101 000111 0101 08 2 010 01000 111001 0101 000110 0101 D9 2 010 01001 100101 0101 100101 0101 D10 2 010 01010 010101 0101 010101 0101 D11 2 010 01011 110100 0101 110100 0101 D12 2 010 01100 001101 0101 001101 0101 D13 2 010 01101 101100 0101 101100 0101 D14 2 010 01110 011100 0101 011100 0101 D15 2 010 01111 010111 0101 101000 0101 D16 2 010 10000 011011 0101 100100 0101 RocketlO Transceiver User Guide www xilinx com 139 06024 v2 4 August 25 2004 A XILINX Appendix B 8 10 Valid Characters Table B 1 Valid Data Characters Continued Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj D17 2 010 10001 100011 0101 100011 0101 D18 2 010 01010 010011 0101 010011 0101 D19 2 010 10011 110010 0101 110010 0101 D20 2 010 10100 001011 0101 001011 0101 D21 2 010 10101 101010 0101 101010 0101 D22 2 010 10110 011010 0101 011010 0101 D23 2 010 10111 111010 0101 000101 0101 D24 2 010 11000 110011 0101 001100 0101 D25 2 010 11001 10011
64. 10 0110 010110 0110 D27 6 110 11011 110110 0110 001001 0110 D28 6 110 11100 001110 0110 001110 0110 D29 6 110 11101 101110 0110 010001 0110 D30 6 110 11110 011110 0110 100001 0110 D31 6 110 11111 101011 0110 010100 0110 D0 7 111 00000 100111 0001 011000 1110 D1 7 111 00001 011101 0001 100010 1110 D2 7 111 00010 101101 0001 010010 1110 D3 7 111 00011 110001 1110 110001 0001 D4 7 111 00100 110101 0001 001010 1110 05 7 111 00101 101001 1110 101001 0001 D6 7 111 00110 011001 1110 011001 0001 D7 7 111 00111 111000 1110 000111 0001 D8 7 111 01000 111001 0001 000110 1110 D9 7 111 01001 100101 1110 100101 0001 D10 7 111 01010 010101 1110 010101 0001 D11 7 111 01011 110100 1110 110100 1000 D12 7 111 01100 001101 1110 001101 0001 D13 7 111 01101 101100 1110 101100 1000 D14 7 111 01110 011100 1110 011100 1000 D15 7 111 01111 010111 0001 101000 1110 D16 7 111 10000 011011 0001 100100 1110 D17 7 111 10001 100011 0111 100011 0001 D18 7 111 10010 010011 0111 010011 0001 D19 7 111 10011 110010 1110 110010 0001 144 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Valid Control Characters K Characters XILINX Table B 1 Valid Data Characters Continued Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj D20 7 111 10100 001011 0111 001011 0001 D21 7 111 10101 101010 1110 101010 0001
65. 100 28 5 or K28 5 010010111100 K28 5 or K28 5 010110111100 K28 5 or K28 5 The RocketIO core receives this data but for cases where TXCHARDISPVAL is set High during data transmission the disp err bit in CHAN BOND SEQ must also be set High RocketlO Transceiver User Guide www xilinx com 67 06024 v2 4 August 25 2004 A XILINX Chapter 2 Digital Design Considerations Receiving Vitesse Channel Bonding Sequence On the RX side the definition of the channel bonding sequence uses the disp err bit to specify the flipped disparity 10 bit literal value disp err char is k 8 bit byte value CHAN BOND SEQ 1 1 1 10111100 matches K28 5 or K28 5 CHAN BOND SEQ 1 2 1 10111100 matches K28 5 or K28 5 CHAN BOND SEQ 1 3 1 10111100 matches K28 5 or K28 54 CHAN BOND SEQ 1 4 1 10111100 matches K28 5 or K28 54 CHAN BOND SEQ LEN 0 0 0 0 4 CHAN BOND SEQ 2 USE FALSE 8B 10B Bypass Serial Output When 8B 10B encoding is bypassed the TXCHARDISPVAL and TXCHARDISPMODE bits become bits b and respectively of the 10 bit encoded data that the transceiver must transmit to the receiving terminal Figure 2 13 illustrates the TX data map during 8B 10B bypass TXCHARDISPMODE 0 TXCHARDISPVAL 0 TXDATA 7 TXDATA O a lb lc d e i f g h lj E pos pope pepe e First transmitted Last transmitted 06024 10a 051602 Figure 2 13 10 Bit T
66. 100 D17 3 011 10001 100011 1100 100011 0011 D18 3 011 10010 010011 1100 010011 0011 D19 3 011 10011 110010 1100 110010 0011 D20 3 011 10100 001011 1100 001011 0011 D21 3 011 10101 101010 1100 101010 0011 D22 3 011 10110 011010 1100 011010 0011 D23 3 011 10111 111010 0011 000101 1100 D24 3 011 11000 110011 0011 001100 1100 D25 3 011 11001 100110 1100 100110 0011 D26 3 011 11010 010110 1100 010110 0011 D27 3 011 11011 110110 0011 001001 1100 D28 3 011 11100 001110 1100 001110 0011 D29 3 011 11101 101110 0011 010001 1100 D30 3 011 11110 011110 0011 100001 1100 D31 3 011 11111 101011 0011 010100 1100 D0 4 100 00000 100111 0010 011000 1101 D1 4 100 00001 011101 0010 100010 1101 D2 4 100 00010 101101 0010 010010 1101 D3 4 100 00011 110001 1101 110001 0010 D4 4 100 00100 110101 0010 001010 1101 D5 4 100 00101 101001 1101 101001 0010 D6 4 100 00110 011001 1101 011001 0010 D7 4 100 00111 111000 1101 000111 0010 D8 4 100 01000 111001 0010 000110 1101 D9 4 100 01001 100101 1101 100101 0010 D10 4 100 01010 010101 1101 010101 0010 D11 4 100 01011 110100 1101 110100 0010 D12 4 100 01100 001101 1101 001101 0010 D13 4 100 01101 101100 1101 101100 0010 D14 4 100 01110 011100 1101 011100 0010 D15 4 100 01111 010111 0010 101000 1101 D16 4 100 10000 011011 0010 100100 1101 RocketlO Transceiver User Guide www xilinx com 141 06024 v2 4 August 25 2004 A XILINX Appendix B 8 10 Valid Characters Table B 1 Valid Data Characters Continued
67. 10100 1001 D12 1 001 01100 001101 1001 001101 1001 D13 1 001 01101 101100 1001 101100 1001 D14 1 001 01110 011100 1001 011100 1001 D15 1 001 01111 010111 1001 101000 1001 D16 1 001 10000 011011 1001 100100 1001 D17 1 001 10001 100011 1001 100011 1001 138 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Valid Data Characters A UNN Table B 1 Valid Data Characters Continued Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj D18 1 001 10010 010011 1001 010011 1001 D19 1 001 10011 110010 1001 110010 1001 D20 1 001 10100 001011 1001 001011 1001 D21 1 001 10101 101010 1001 101010 1001 D22 1 001 10110 011010 1001 011010 1001 D23 1 001 10111 111010 1001 000101 1001 D24 1 001 11000 110011 1001 001100 1001 D25 1 001 11001 100110 1001 100110 1001 D26 1 001 11010 010110 1001 010110 1001 D27 1 001 11011 110110 1001 001001 1001 D28 1 001 11100 001110 1001 001110 1001 D29 1 001 11101 101110 1001 010001 1001 D30 1 001 11110 011110 1001 100001 1001 D31 1 001 11111 101011 1001 010100 1001 D0 2 010 00000 100111 0101 011000 0101 D1 2 010 00001 011101 0101 100010 0101 D2 2 010 00010 101101 0101 010010 010
68. 1101 1010 D13 5 101 01101 101100 1010 101100 1010 D14 5 101 01110 011100 1010 011100 1010 D15 5 101 01111 010111 1010 101000 1010 D16 5 101 10000 011011 1010 100100 1010 D17 5 101 10001 100011 1010 100011 1010 142 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Valid Data Characters XILINX Table B 1 Valid Data Characters Continued Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj D18 5 101 01010 010011 1010 010011 1010 D19 5 101 10011 110010 1010 110010 1010 D20 5 101 10100 001011 1010 001011 1010 D21 5 101 10101 101010 1010 101010 1010 D22 5 101 10110 011010 1010 011010 1010 D23 5 101 10111 111010 1010 000101 1010 D24 5 101 11000 110011 1010 001100 1010 D25 5 101 11001 100110 1010 100110 1010 D26 5 101 11010 010110 1010 010110 1010 D27 5 101 11011 110110 1010 001001 1010 D28 5 101 11100 001110 1010 001110 1010 D29 5 101 11101 101110 1010 010001 1010 D30 5 101 11110 011110 1010 100001 1010 D31 5 101 11111 101011 1010 010100 1010 D0 6 110 00000 100111 0110 011000 0110 D1 6 110 00001 011101 0110 100010 0110 D2 6 110 00010 101101 0110 010010 0110 D3 6 110 00011 110001 0110 110001 0110 D4 6 110 00100 110101 0110 001010 0110 D5 6 110 00101 1
69. 2 Cable Characterization White Papers MM HR WP157 Usage Models for Multi Gigabit Serial WP160 Emulating External SERDES Devices with Embedded RocketIO RocketlO Transceiver User Guide www xilinx com 06024 v2 4 August 25 2004 11 7 XILINX 12 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Figure 1 1 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 2 7 Figure 2 6 Figure 2 9 Figure 2 10 Figure 2 11 Figure 2 12 Figure 2 13 Figure 2 14 Figure 2 15 Figure 2 16 Figure 2 17 Figure 2 18 Figure 2 19 Figure 2 20 Figure 2 21 Figure 2 22 Figure 2 23 Figure 2 24 Figure 2 25 Figure 2 26 Figure 2 27 Figure 2 28 Figure 2 29 Figure 2 30 Figure 3 1 Schedule of Figures Chapter 1 RocketlO Transceiver Overview RocketIO Transceiver Block Diagram 23 Chapter 2 Digital Design Considerations REFCLK BREFCLK Selection 43 Two Byte Clock with 46 Two Byte Clock without 49 Four Byte 49 One Byte Clock eol ERR RR UR de
70. 4 August 25 2004 XILINX Related Online Documents The documents described in this Appendix are accessible on the Xilinx website at www xilinx com Document links shown in blue are clickable in this PDF file providing easy access to the most current revision of each document Application Notes XAPP648 Serial Backplane Interface to a Shared Memory This application note utilizes the Virtex II Pro RocketIO transceivers and the Xilinx Aurora Protocol Engine to provide a multi ported interface to a shared memory system in a backplane environment Multiprocessor systems are often encountered in backplane systems and distributed processing applications require access to a shared memory across a backplane bus Utilization of a hardware test and set lock mechanism along with a software protocol to test for a semaphore grant prior to accessing the shared memory guarantees atomic access to the shared memory 649 SONET Rate Conversion in Virtex Il Pro Devices The RocketIO transceivers have several modes of operation but all modes rely on the internal transmitter clock being multiplied by 20 for data transmission For example a 20 bit data stream passed to the unit at 125 MHz is serialized and retransmitted at 2 5 Gb s At a 156 25 MHz input the output is at its maximum speed of 3 125 Gb s The parallel data stream applied to the RocketIO transceiver can either be 20 bits direct or it can be written as 1
71. 5 Table 2 5 DCM Outputs for Different 8 45 Table 2 6 Latency through Various Transmitter Components Processes 59 Table 2 7 Latency through Various Receiver Components Processes 60 Table 2 8 Reset and Power Control amp 60 Table 2 9 Power Control 61 Table 2 10 8B 10B Bypassed Signal Significance 65 Table 2 11 Running Disparity Control 66 Table 2 12 Possible Locations of Comma Character 71 Table 2 13 Effects of Comma Related Ports and 74 Table 2 14 Data Bytes Allowed Between Clock Corrections as a Function of REFCLK Stability and IDLE Sequences 76 Table 2 15 Clock Correction Sequence Data Correlation for 16 Bit Data Port 77 Table 2 16 Applicable Clock Correction TI Table 2 17 RXCLKCORCNT 79 Table 2 18 Bonded Channel Connections 82 Table 2 19 Master Slave Channel Bonding Attribute Settings 83 Table 2 20 Effects of CRC on Transceiver 87 Table 2 21 Global
72. 5 20 04 2 3 1 Changed the value of TRCLK RFCLK in Table 3 4 06 24 04 2 3 2 Modified Figure 2 3 08 25 04 2 4 Fixed error in Hex value in Table 2 15 page 77 Add application notes to Appendix C Related Online Documents Replaced Voltage Regulation section with Voltage Regulator Selection and Use in Chapter 3 Removed all references to the XCVP125 device Modified Note 4 in Table 3 5 06024 v2 4 August 25 2004 www xilinx com RocketlO Transceiver User Guide RocketlO Transceiver User Guide www xilinx com UG024 v2 4 August 25 2004 Table of Contents Schedule of 13 Schedule of Tables s 15 Preface About This Guide RocketlO Features sss omes here P Wer E AEN RENE ERAN dE 17 Guide Contents 17 For More 18 Additional 18 C onventlons e esche UR De b exe RE EE EA 19 Port and Attribute 19 Typographical i ccce kr RR e SOR RE wee erac cs 19 Online Document 522 2 voz giae RE BEd os Meo bE OM alee 20 Chapter 1 RocketlO Transceiver Overview Basic Architecture and
73. 6 bits to which 8b 10b coding is applied to generate the 20 bits required However there is a class of applications typically in SONET processing systems where the data path is 16 bits wide running at 155 52 MHz The designer would ideally apply the data directly to the RocketIO transceiver for onward transmission at 155 52 x 16 2 48832 Gb s Since this cannot be done in Virtex II Pro devices this application note describes the logic necessary to perform this function This application note is divided into two sections the first is the logic necessary for the data width conversion and the second describes the clocking characteristics required by the RocketIO transceiver XAPP651 SONET and OTN Scramblers Descramblers Both SONET and OTN are standards for data transmission over fibre optic links This implies a need for clock recovery at the receiver which in turn requires a guaranteed minimum number of transitions in the incoming serial data stream The mechanism to achieve this transition density similar for both SONET and OTN is known as scrambling The scrambling and descrambling function is independent of the serial data rate used Serial data for transmission is added to the output RocketlO Transceiver User Guide www xilinx com 147 UG024 v2 4 August 25 2004 7 XILINX Appendix C Related Online Documents of a pseudo random number generator running at the same clock frequency The same circuit is used in the rece
74. B Notes 1 BREFCLK for speeds of 2 5 Gb s or greater 2 Jitter measured at BGA ball 3 Tr depends on serial speed and length type of sequence used An additional feature of CDR is its ability to accept an external precision clock REFCLK which either acts to clock incoming data or to assist in synchronizing the derived RXRECCLK 110 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 PCB Design Requirements XILINX For further clarity TXUSRCLK is used to clock data from the FPGA core to the TX FIFO The FIFO depth accounts for the slight phase difference between these two clocks If the clocks are locked in frequency then the FIFO acts much like a pass through buffer PCB Design Requirements To ensure reliable operation of the RocketIO transceivers certain requirements must be met by the designer This section outlines these requirements governing power filtering networks high speed differential signal traces and reference clocks Any designs that do not adhere to these requirements will not be supported by Xilinx Inc Power Conditioning Each RocketIO transceiver has five power supply pins all of which are sensitive to noise Table 3 5 summarizes the power supply pins their names associated voltages and power requirements To operate properly the RocketIO transceiver requires a certain level of noise isolation from surrounding noise sour
75. BD 1 Indicates running disparity is POSITIVE RXDATA 7 0 or 15 8 23 16 31 24 RXDISPERR Disparity error occurred on current byte Unused TXCHARISK Transmitted byte is a K character Unused RXCHARISCOMMA Received byte is a comma Unused TXCHARDISPVAL TXCHARDISPMODE TXCHARDISPVAL and TXCHARDISPMODE are dual purpose ports for the transmitter depending upon whether 8B 10B encoding is enabled Table 2 10 shows this dual functionality When encoding is enabled these ports function as byte mapped control ports controlling the running disparity of the transmitted serial data RocketlO Transceiver User Guide In the encoding configuration the disparity of the serial transmission can be controlled with the TXCHARDISPVAL and TXCHARDISPMODE ports When TXCHARDISPMODE is set High the running disparity is set before encoding the specific byte TXCHARDISPVAL determines if the disparity is negative set Low or positive set High Table 2 11 illustrates this 06024 v2 4 August 25 2004 www xilinx com 65 X XILINX 66 Chapter 2 Digital Design Considerations Table 2 11 Running Disparity Control TXCHARDISPMODE Function TXCHARDISPVAL 00 Maintain running disparity normally Invert normally generated running disparity before encoding this byte 10 Set negative running disparity before encoding this byte 11 Set positive running disparity before encoding this byte When TXCHARDISPMO
76. C gt GND PSEN gt GND PSCLK gt GND RST RST 54 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Clocking XILINX CLKO gt CLKO CLK2X180 gt CLK2X180 W LOCKED gt LOCK 3 BUFG Instant U BUFG IBUFG port map I gt Q U2 BUFG BUFG port map OH oll U4 BUFG BUFG port map I gt gt iation REFCLKIN REFCLK CLKO W USRCLK M W CLK2X180 W USRCLK2 M W end ONE BYTE CLK arch Verilog Template Module Description Device ONE BYTE CLK Verilog Submodule DCM for 1 byte GT Virtex II Pro Family module ONE BYTE CLK REFCLKIN REFCLK USRCLK M USRCLK2 M DCM LOCKED L input REFCLKIN output REFCLK output USRCLK M output USRCLK2 output DCM LOCKED wire REFCLKIN wire REFCLK wire USRCLK M wire USRCLK2 wire DCM LOCKED wire REFCLKINBUF wire i wire clk 2x 180 DCM demi CLKFB USRCLK CLKIN REFCLKINBUF RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 www xilinx com 55 3 XILINX Chapter 2 Digital Design Considerations endmodule DSSEN PSCLK PSEN PSINCDEC RST CLKO CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 LOCKED PSDONE STATUS E BUFG buf1 BUFG buf2 IBUFGbuf3 1 bo 1 bo 1 bo 1 bo 1 bo clk i
77. CHANSYNC ports 3 The port size changes with relation to the primitive selected and also correlates to the byte mapping 4 External ports only accessible from package pins RocketlO Transceiver User Guide www xilinx com 27 06024 v2 4 August 25 2004 3 XILINX Chapter 1 RocketlO Transceiver Overview Primitive Attributes The primitives also contain attributes set by default to specific values controlling each specific primitive s protocol parameters Included are channel bonding settings for primitives supporting channel bonding clock correction sequences and CRC Table 1 6 shows a brief description of each attribute Table 1 7 and Table 1 8 have the default values of each primitive Table 1 6 RocketlO Transceiver Attributes Attribute ALIGN COMMA MSB Description TRUE FALSE controls the alignment of detected commas within the transceiver s 2 byte wide data path FALSE Align commas within a 10 bit alignment range As a result the comma is aligned to either RXDATA 15 8 byte or RXDATA 7 0 byte in the transceivers internal data path TRUE Aligns comma with 20 bit alignment range As a result aligns on the RXDATA 15 8 byte Notes 1 If protocols like Gigabit Ethernet are oriented in byte pairs with commas always in even first byte formation this can be set to TRUE Otherwise it should be set to FALSE 2 For 32 bit data path primitives see 32 bit Alignment Design page 97 3 This attribute is o
78. CLK2 etc in the FPGA core and REFCLK at the pad NOTE The reference clock may be any of the four MGT clocks including the BREFCLKs Table 2 5 DCM Outputs for Different DATA WIDTHs SERDES 108 gy Get wm PEFCLK RXUSRCLK RXUSRCLK2 FALSE 1 CLKIN CLKO CLK2X180 FALSE 2 CLKIN CLKO CLKO FALSE 4 CLKIN CLK 1800 CLKDV divide by 2 TRUE 1 CLKIN CLKDV divide by 2 CLK180 TRUE 2 CLKIN CLKDV divide by 2 CLKDV divide by 2 TRUE 4 CLKIN CLKFX180 divide by 2 CLKDV divide by 4 Notes 1 Since CLKO is needed for feedback it can be used instead of CLK180 to clock USRCLK or USRCLK2 of the transceiver with the use of the transceiver s local inverter saving a global buffer BUFG RocketlO Transceiver User Guide www xilinx com 45 06024 v2 4 August 25 2004 A XILINX Chapter 2 Digital Design Considerations Example 1a Two Byte Clock with DCM The following HDL codes are examples of a simple clock scheme using 2 byte data with both USRCLK and USRCLK2 at the same frequency USRCLK M is the input for both USRCLK and USRCLK2 Clocks for 2 Byte Data Path for 2 Byte Data Path GT std 2 JLU LI LI LI IBUFGDS REFCLKSEL REFCLK_P REFUS TXUSRCLK REFCLK N TXUSRCLK2 RXUSRCLK 7 RXUSRCLK2 TXUSRCLK RXUSRCLK RXUSRCLK2 ug024 02a 112202 Figure 2 2 Two Byte Clock with DCM VHDL Template Module TWO BYTE CLK Descripti
79. CLKIN input of the DCM for creation of USRCLKs If all the transceivers on a Virtex II Pro FPGA are to be used two BREFCLKs must be created one for the top of the chip and one for the bottom These dedicated clocks use the same clock inputs for all packages P GCLK4S GCLK6P BREFCLK BREFCLK N GCLKSP N GCLK7S Top Bottom P GCLK2S P GCLKOP BREFCLK2 BREFCLK2 N GCLK3P N GCLKIS An attribute REF CLK V SEL and a port REFCLKSEL determine which reference clock is used for the MGT PMA block Figure 2 1 shows how REFCLK and BREFCLK are selected through use of REFCLKSEL and REF CLK V SEL refclk refclk2 brefclk brefclk2 REFCLKSEL REF CLK V SEL refclk out to PCS and PMA ug024 35 091802 Figure 2 1 REFCLK BREFCLK Selection Logic Table 2 3 shows the BREFCLK pin numbers for all packages Note that these pads must be used for BREFCLK operations Table 2 3 BREFCLK Pin Numbers Top Bottom Package BREFCLK BREFCLK2 BREFCLK BREFCLK2 Pin Number Pin Number Pin Number Pin Number FG256 A8 B8 B9 A9 R8 T8 T9 R9 FG456 C11 D11 D12 C12 W11 Y11 Y12 W12 FG676 B13 C13 C14 B14 AD13 AE13 AE14 AD14 FF672 B14 C14 C13 B13 AD14 AE14 AE13 AD13 RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 43 3 XILINX A4 Chapter 2 Digital Design Considerations Table 2 3 BREFCLK Pin Numbe
80. COMMA 10B VALUE exactly DEC PCOMMA DETECT DEC MCOMMA DETECT DEC VALID COMMA ONLY These signals only pertain to the 8B 10B decoder not the comma alignment circuitry The DEC PCOMMA DETECT and DEC MCOMMA DETECT control the 8B 10B decoder to signal the RXCHARISCOMMA port if a plus comma or minus comma is received This is described in the table below DEC VALID COMMA ONLY for most applications should be set to TRUE If valid data is being transmitted and hence received then an invalid comma would arise only in the case of a bit error in which case RXCHARISCOMMA would not be asserted in the presence of bit errors If set to FALSE then RXCHARISCOMMA will be asserted for invalid K characters RXREALIGN This status signal indicates whenever the serial data is realigned from a comma character in the data stream This signal will not necessarily go High after the transceiver is reset If ENPCOMMAALIGN and ENMCOMMAALIGN are both set to zero then this signal should not go High See Table 2 13 RocketlO Transceiver User Guide www xilinx com 73 06024 v2 4 August 25 2004 Chapter 2 Digital Design Considerations RXCHARISCOMMA This signal is similar to RXCHARISK except that it signals that a specific byte of RXDATA is a comma character However this definition only holds true for when 8B 10B encoding decoding is enabled This port is controlled by the DEC attributes and is shown in Table 2 13 If the 8B 10B decoder is bypassed t
81. CRC is bypassed and must be implemented in the FPGA fabric CRC FORMAT There are four possible CRC modes USER MODE FIBRE CHAN ETHERNET and INFINIBAND This attribute is modifiable only for the XAUI and CUSTOM primitives Each mode has a Start of Packet SOP and End of Packet EOP setting to determine where to start and end the CRC monitoring USER MODE allows the user to define the SOP and EOP by setting the CRC START OF PKT and CRC END OF PKT to one of the valid K characters Table B 2 page 145 The CRC is controlled by RX USE and TX USE Whenever these attributes are set to TRUE CRC is used The four modes are defined in the subsections following USER MODE USER MODE is the simplest CRC methodology The CRC checks for the SOP and EOP calculates CRC on the data and leaves the four remainders directly before the EOP The CRC form for the user defined mode is shown in Figure 2 24 along with the timing for when RKCHECKINGCRC and RXCRCERR are asserted High with respect to the incoming data To check the CRC error detection logic in a testing mode such as serial loopback a CRC error can be forced by setting TXFORCECRCERR to High which incorporates an error into the transmitted data When that data is received it appears corrupted and the receiver signals an error by asserting RXCRCERR High at the same time RXCHECKINGCRC goes High User logic determines the procedure that is invoked when a CRC error occ
82. CUSTOM GT ETHERNET Continued Attribute Default Default Default GT AURORA GT CUSTOM GT ETHERNET TX DIFF CTRL 5000 500 5000 TX PREEMPHASIS 02 0 00 Notes 1 All GT CUSTOM attributes are modifiable 2 Modifiable attribute for specific primitives 3 Depends on primitive used either 1 2 or 4 4 Attribute value only when RX DATA WIDTH is 4 When RX DATA WIDTH is 1 or 2 attribute value is 2 5 Attribute value only when RX DATA WIDTH is 4 When RX DATA WIDTH is 1 or 2 attribute value is 0 6 CRC EOP and CRC SOP are not applicable for this primitive Table 1 8 Default Attribute Values GT FIBRE CHAN GT INFINIBAND and GT XAUI Attribute Default Default Default GT FIBRE CHAN GT INFINIBAND GT XAUI ALIGN COMMA MSB FALSE FALSE FALSE CHAN BOND LIMIT 1 16 16 CHAN BOND MODE OFF OFF OFF D CHAN BOND OFFSET 0 8 8 CHAN BOND ONE SHOT TRUE FALSE FALSE CHAN BOND SEQ 1 1 00000000000 00110111100 00101111100 CHAN BOND SEQ 1 2 00000000000 Lane ID Modify with 00000000000 Lane ID CHAN BOND SEQ 1 3 00000000000 00001001010 00000000000 CHAN BOND SEQ 1 4 00000000000 00001001010 00000000000 CHAN BOND SEQ 2 1 00000000000 00110111100 00000000000 CHAN BOND SEQ 2 2 00000000000 Lane ID Modify with 00000000000 Lane ID CHAN BOND SEQ 2 3 00000000000 00001000101 00000000000 CHAN BOND SEQ 2 4 00000000000 00001000101 00000000000 CHAN BOND SEQ 2 USE FALSE TRUE FALS
83. Chapter 3 Analog Design Considerations Serial I O Description 105 Pre emphasis 106 Differential Receiver 109 Np pc UEM 109 Clock and Data 110 PCB Design 111 Power Conditioning cued AE EEN AE Re ees 111 Voltage Regulator Selection and 111 Termination Voltage WERE EUER 113 Passive EE 113 High Speed Serial Trace Designs NEEN chee eek ase ease ee asa eee DX EE IAM 117 Routing Serial 117 Differential Trace Design vua e Oe BEN SS POS OEE EES 118 AC and DC 1 119 Reference Clock Se ES ee AR 121 Epson EG 2121CA 2 5V LVPECL 121 Pletronics LV1145B LVDS 121 Other Important Design Notes 122 Powering the RocketIO Transceivers 122
84. D WAIT 84 CLK COR INSERT IDLE FLAG 78 CLK COR KEEP IDLE 78 CLK COR REPEAT WAIT 78 CLK COR SEQ 77 CLK COR SEQ LEN 77 CLK CORRECT USE 76 COMMA 10 MASK 73 CRC END OF PACKET 90 CRC FORMAT 87 CRC START OF PACKET 90 DEC MCOMMA DETECT 73 DEC PCOMMA DETECT 73 DEC VALID COMMA ONLY 73 MCOMMA 10 VALUE 73 MCOMMA DETECT 73 PCOMMA 10B VALUE 73 PCOMMA DETECT 73 PRE EMPHASIS 93 RX BUFFER USE 77 92 RX CRC USE 87 RX DATA WIDTH 92 RX DECODE USE 64 RX LOS INVALID INCR 80 RX LOS THRESHOLD 80 RX LOSS OF SYNC FSM 80 SERDES 10 93 TERMINATION IMP 93 TX BUFFER USE 92 TX CRC FORCE VALUE 91 TX CRC USE 87 TX DATA WIDTH 92 TX DIFF CTRL 93 Attributes table 30 BREFCLK and REF CLK V SEL 33 43 and REFCLKSEL 26 43 and serial speed 41 pin numbers 43 when amp how to use 43 Buffers Fabric Interface 91 ports and attributes 92 transmitter and elastic receiver 91 Byte Mapping 39 C Channel Bonding Alignment 81 operation 82 ports and attributes 83 troubleshooting 85 Vitesse channel bonding sequence receive 68 transmit 67 Characters valid tables 137 Clock Correction Recovery clock recovery 75 overview 74 ports and attributes 76 Clock Data Recovery CDR parameters 110 Clocking 41 clock and data recovery 75 clock correction recovery 74 clock dependency 59 clock descriptions 129 clock pulse width 132 clock ratio 45 clock recovery 75 clock signals 41 clock synthesizer 74 clock to out
85. D22 7 111 10110 011010 1110 011010 0001 D23 7 111 10111 111010 0001 000101 1110 D24 7 111 11000 110011 0001 001100 1110 D25 7 111 11001 100110 1110 100110 0001 D26 7 111 11010 010110 1110 010110 0001 D27 7 111 11011 110110 0001 001001 1110 D28 7 111 11100 001110 1110 001110 0001 D29 7 111 11101 101110 0001 010001 1110 D30 7 111 11110 011110 0001 100001 1110 D31 7 111 11111 101011 0001 010100 1110 Valid Control Characters K Characters Table B 2 Valid Control Characters K Characters Special Bits Current RD Current RD Code Name HGF EDCBA abcdei fghj abcdei fghj K28 0 000 11100 001111 0100 110000 1011 K28 1 001 11100 001111 1001 110000 0110 K28 2 010 11100 001111 0101 110000 1010 K28 3 011 11100 001111 0011 110000 1100 K28 4 100 11100 001111 0010 110000 1101 K28 5 101 11100 001111 1010 110000 0101 K28 6 110 11100 001111 0110 110000 1001 K28 7 0 111 11100 001111 1000 110000 0111 K23 7 111 10111 111010 1000 000101 0111 K27 7 111 11011 110110 1000 001001 0111 K29 7 111 11101 101110 1000 010001 0111 K30 7 111 11110 011110 1000 100001 0111 Notes 1 Used for testing and characterization only Do not use in protocols RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 145 A XILINX Appendix B 8 10 Valid Characters 146 www xilinx com RocketlO Transceiver User Guide UG024 v2
86. DC converter is not acceptable Must be used in the circuit given in Figure 3 7 Must either be a qualified linear regulator listed in Table 3 6 or meet the following criteria Output noise no greater than 40 RMS from 10 Hz to 100 kHz Regulation to within 2 of nominal output voltage 50 mV for 2 5V supply RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 111 A XILINX Chapter 3 Analog Design Considerations Table 3 6 Qualified Linear Regulators Vendor Part Number Current Rating Description Linear Technology LT1963 154 Low NoiseLDO Regulator Linear Technology LT1764 3 0A Low Noise LDO Regulator Texas Instruments TPS795xx 0 5A RF LDO Regulator Texas Instruments TPS796xx 1 0A RF LDO Regulator Texas Instruments TPS786xx 1 5A RF LDO Regulator National LP3875 1 5A Ultra LDO Regulator Semiconductor Voltage regulators in this category typically are available in both fixed and adjustable output varieties Those with fixed output voltage require no output adjustment resistors whereas adjustable versions require a two resistor voltage divider to determine the output voltage See vendor data to select these resistors and for information on connection of all other regulator pins Sense Shutdown etc Vendor application examples typically recommend a 10 uF capacitor on the input and a 10 UF capacitor on the output of the regulator
87. DE is set Low the running disparity is maintained if TX CHARDISPVAL is also set Low but the disparity is inverted before encoding the byte when TXCAHRDISPVAL is set High Most applications will use the mode where both TXCHARDISPMODE and TXCHARDISPVAL are set Low Some applications may use other settings if special running disparity configurations are required such as in the Vitesse Disparity Example below In the bypassed configuration TXCHARDISPMODE 0 becomes bit 9 of the 10 bits of encoded data TXCHARDISPMODE 1 3 are bits 19 29 and 39 in the 20 and 40 bit wide buses TXCHARDISPVAL becomes bits 8 18 28 and 38 of the transmit data See Figure 2 13 TXCHARISK TXCHARISK is a byte mapped control port that is used only when the 8B 10B encoder is implemented This port controls whether the byte of TXDATA is to be encoded as a control K character when asserted High or as a data character when de asserted When 8B 10B encoding is bypassed this port is undefined TXRUNDISP TXRUNDISP is a status port that is byte mapped to TXDATA This port indicates the running disparity after the byte of TXDATA is encoded When High the disparity is positive When Low the disparity is negative TXKERR TXKERR is a status port that is byte mapped to TXDATA This port is defined only if 8B 10B encoding is enabled If a bit is asserted High it means that TXDATA and TXCHARISK have combined to create an invalid control K character The
88. E CHAN BOND SEQ LEN 1 4 1 CHAN BOND WAIT 7 8 8 CLK COR INSERT IDLE FLAG FALSE FALSE FALSE CLK COR KEEP IDLE FALSE FALSE FALSE RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 35 XILINX Chapter 1 RocketlO Transceiver Overview Table 1 8 Default Attribute Values GT FIBRE CHAN GT INFINIBAND and GT XAUI Continued Attribute Default Default Default GT FIBRE CHAN GT INFINIBAND GT XAUI CLK COR REPEAT WAIT 20 10 10 CLK COR SEQ 11 00110111100 00100011100 00100011100 CLK COR SEQ 1 2 00010010101 00000000000 00000000000 CLK COR SEQ 1 3 00010110101 00000000000 00000000000 CLK COR SEQ 1 4 00010110101 00000000000 00000000000 CLK COR SEQ 2 1 00000000000 00000000000 00000000000 CLK COR SEQ 2 2 00000000000 00000000000 00000000000 CLK COR SEQ 2 3 00000000000 00000000000 00000000000 CLK COR SEQ 2 4 00000000000 00000000000 00000000000 CLK COR SEQ 2 USE FALSE FALSE FALSE CLK COR SEQ LEN 4 1 1 CLK CORRECT USE TRUE TRUE TRUE COMMA 10B MASK 1111111000 1111111000 1111111000 CRC END OF PKT Note 3 Note 3 K29 70 CRC FORMAT FIBRE CHAN INFINIBAND USER MODE D CRC START OF PKT Note 3 Note 3 K27 70 DEC MCOMMA DETECT TRUE TRUE TRUE DEC PCOMMA DETECT TRUE TRUE TRUE DEC VALID COMMA ONLY TRUE TRUE TRUE Lane ID INFINBAND ONLY NA 00000000000 D NA 10 VALUE 11000000
89. FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES BY PROVIDING THIS DESIGN CODE OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE APPLICATION OR STANDARD XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS INFRINGEMENT IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE c Copyright 2002 Xilinx Inc All rights reserved KK k k RK RR RR RR 7 96 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Other Important Design Notes XILINX Virtex II Pro RocketIO comma alignment module This module reads RXDATA 31 0 from a RocketIO transceiver and copies it to its output realigning it if necessary so that commas are aligned to the MSB position 31 24 The module assumes ALIGN COMMA MSB is TRUE that the comma is already aligned to 31 24 or 15 8 Outputs aligned data 31 0 Properly aligned 32 bit ALIGNED DATA sync Indicator that aligned data is properly aligned aligned rxisk 3 0 properly ali
90. FOR YOUR IMPLEMENTATION XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF 1 1 KF HF zt ox RocketlO Transceiver User Guide www xilinx com 99 06024 v2 4 August 25 2004 7 XILINX Chapter 2 Digital Design Considerations ET i LIB USE use use use ENT INFRINGEMENT IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE c Copyright 2002 Xilinx Inc All rights reserved kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk kkkkkkkkkk Virtex II Pro RocketIO comma alignment module This module reads RXDATA 31 0 from a RocketIO transceiver and copies it to its output realigning it if necessary so that commas are aligned to the MSB position 31 24 The module assumes ALIGN COMMA MSB is TRUE that the comma is already aligned to 31 24 or 15 8 Outputs aligned data 31 0 Properly aligned 32 std logic ALIGNED DATA sync Indicator that aligned data is properly aligned aligned rxisk 3 0 properly aligned 4 std logic RXCHARISK Inputs These are all RocketIO inputs or outputs as indicated usrclk2 RXUSRCLK2 rxreset RXRESET rxdata 31 0 RXDATA 31 0 commas aligned to 31 24 or 15 8 rxisk 3 0 RXCHARISK 3 0 rxrealign RXREALIGN rxcommadet RXCOMMADE
91. FORCE VALUE 8 bit vector Value to corrupt TX CRC computation when input TXFORCECRCERR is High This value is XORed with the correctly computed CRC value corrupting the CRCif TX CRC FORCE VALUE is nonzero This can be used to test CRC error detection in the receiver downstream TX DIFF CTRL An integer value 400 500 600 700 or 800 representing 400 mV 500 mV 600 mV 700 mV or 800 mV of voltage difference between the differential lines Twice this value is the peak peak voltage TX PREEMPHASIS An integer value 0 3 that sets the output driver pre emphasis to improve output waveform shaping for various load conditions Larger value denotes stronger pre emphasis See pre emphasis values in Table 3 2 page 106 32 RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 www xilinx com Modifiable Primitives Modifiable Primitives XILINX As shown in Table 1 7 and Table 1 8 only certain attributes are modifiable for any primitive These attributes help to define the protocol used by the primitive Only the CUSTOM primitive allows the user to modify all of the attributes to a protocol not supported by another transceiver primitive This allows for complete flexibility The other primitives allow modification of the analog attributes of the serial data lines and several channel bonding values Table 1 7 Default Attribute Values GT AURORA GT CUSTOM GT ETHERNET
92. Guide UG024 v2 4 August 25 2004 Clocking XILINX PSDONE STATUS end component out std logic out std logic vector 7 downto O0 Signal Declarations signal GND signal CLKO W Signal CLKDV W std logic std logic std logic Signal USRCLK2 M W std logic begin USRCLK2 M USRCLK2 M W GND ss FOI Instantiation U DCM DCM port map CLKIN gt REFCLK CLKFB gt USRCLK2 M W DSSEN gt GND PSINCDEC gt GND PSEN gt GND PSCLK gt GND RST gt RST CLKO gt CLKO W CLKDV gt CLKDV W LOCKED gt LOCK E BUFG Instant U BUFG IBUFG port map c Qe IS U2 BUFG BUFG port map OH oll U3 BUFG BUFG port map 1 gt gt iation REFCLKIN REFCLK CLKO W USRCLK M CLKDV W USRCLK2 M W end FOUR BYTE CLK arch Verilog Template Module Description FOUR BYTE CLK Verilog Submodule DCM for 4 byte GT RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 www xilinx com 51 A XILINX Chapter 2 Digital Design Considerations Device Virtex II Pro Family module FOUR BYTE CLK REFCLKIN REFCLK USRCLK M USRCLK2 M DCM LOCKED input REFCLKIN output REFCLK output USRCLK M output USRCLK2 M output DCM LOCKED wire REFCLKIN wire REFCLK wire USRCLK M wire USRCLK2 M wire DCM LOCKED wire REFCLKINBUF wire clkdv2 wire i
93. LAVE 1 HOP and its CHBONDO does not connect to another transceiver To designate a transceiver as a Master or a Slave the attribute CHAN BOND MODE must be set to one of three designations Master SLAVE 1 HOP or SLAVE 2 HOPS To shut off channel bonding set the transceiver attribute to off The possible values that can be used are shown in Table 2 18 Table 2 18 Bonded Channel Connections Mode CHBONDI CHBONDO OFF NA NA MASTER NA Slave 1 CHBONDI SLAVE 1 Master CHBONDO Slave 2 CHBONDI SLAVE 2 HOPS Slave 1 CHBONDO NA Note All standards that use both clock correction and channel bonding require a gap greater than or equal to 4 bytes between clock correction and channel bonding sequences If a user creates his her own protocol that uses clock correction and channel bonding the user must ensure that there is at least a 4 byte gap between the sequences The channel bonding sequence is similar in format to the clock correction sequence This sequence is set to the appropriate sequence for the primitives supporting channel bonding The CUSTOM is the only primitive allowing modification to the sequence These sequences are comprised of one or two sequences of length up to 4 bytes each as set by CHAN BOND SEQ LEN and CHAN BOND SEQ 2 USE Other control signals include the attributes e CHAN BOND WAIT e CHAN BOND OFFSET e CHAN BOND LIMIT e CHAN BOND ONE SHOT Typical values for these attributes are
94. LER Gee es eed Sw Ra ee 59 Data Path Latency sg ok eae aee E 59 Reset Power Down 60 8B 10B Encoding Decoding 63 RA LL 63 8 10 63 RocketlO Transceiver User Guide www xilinx com 06024 v2 4 August 25 2004 3 XILINX SB LOB Decoder eege dr kee noe re ps eed 63 Ports and Attributes eer 64 TXBYPASSSBIOB RX DECODE SE eor do ies au Eit ti cot 64 TXCHARDISPVAL 65 TXCHARISK ars 66 TXRUNDIS P rr 66 EE 66 RXCHARISK RXRUNDISP ead ed Rae Gee tenes deere Gee Roe 66 RXDISPEBRR 55 ret ah ath ake rece ee esee 67 RXNOTINTABLE E Aug ege ani ee I PUR Rue fn 67 Vitesse Disparity Example 67 Transmitting Vitesse Channel Bonding 67 Receiving Vitesse Channel Bonding 68 8B 10B Bypass Serial Output en 68 8B 10B Serial Output
95. Multiplier Si Clock Correction 2 2 Receiver RX Clock Recovery 32 16 8 bits Deserializer Receive Buffer Comma Detect RXDATA Elastic 8B 10B Buffer Decode 4 64 UG024_09_031203 Figure 2 12 8B 10B Data Flow www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 8B 10B Encoding Decoding Table 2 10 8B 10B Bypassed Signal Significance XILINX Function TXBYPASS8B10B 8B 10B encoding is enabled not bypassed 1 2 or 4 bits mapped to number of bytes of data path width 8B 10B encoding bypassed disabled 1 2 or 4 bits mapped to number of bytes of data path width Function 8B 10B Enabled Function 8B 10B Bypassed TXCHARDISPMODE 00 Maintain running disparity normally Part of 10 bit encoded byte TXCHARDISPVAL see Figure 2 13 T Invert the normally generated running TXCHARDISPMODE 0 disparity before encoding this byte or 1 2 BD 2 Set negative running disparity before TXCHARDISPVAL 0 encoding this byte or 1 2 3 T Set positive running disparity before TAARAT O encoding this byte or 15 8 23 16 31 24 RXCHARISK Received byte is a K character Part of 10 bit encoded byte Fi 2 14 RXRUNDISP 0 Indicates running disparity is NEGATIVE RXCHARISK 0 or 1 2 3 RXRUNDISP 0 EE or 11 2
96. N RX LOSS OF SYNC FSM does this It can be programmed to lose sync after a specified number of invalid data characters are received Ports and Attributes RXCLKCORCNT Clock correction count RXCLKCORCNT is a three bit signal It signals if clock correction has occurred and whether the elastic buffer realigned the data by skipping or repeating data in the buffer It also signals if channel bonding has occurred Table 2 17 defines the eight binary states of RXCLKCORCNT Table 2 17 RXCLKCORCNT Definition RXCLKCORCNT 2 0 Significance ane No channel bonding or clock correction occurred for current RXDATA won Elastic buffer skipped one clock correction sequence for current RXDATA n Elastic buffer skipped two clock correction sequence for current RXDATA Te Elastic buffer skipped three clock correction sequence for current RXDATA xad Elastic buffer skipped four clock correction sequence for current E RXDATA 101 Elastic buffer executed channel bonding for current RXDATA iTO Elastic buffer repeated two clock correction sequences for current RXDATA Elastic buffer repeated one clock correction sequences for current RXDATA RX_LOS_INVALID_INCR RX_LOS_THRESHOLD These two signals determine how fast an invalid character advances the RXLOSSOFSYNC FSM counter before loss of sync is considered to have occurred RX LOS INVALID INCR determines how quickly the occurrence of invalid characters
97. ND IQ 3 0 Clock to Out CHBO Control outputs CHBONDOJ 3 0 Clock TRXPWH Clock pulse width High state RXUSRCLK TRXPWL Clock pulse width Low state RXUSRCLK 132 www Xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Timing Parameter Tables and Diagram XILINX Table A 3 Parameters Relative to the RX User Clock2 RXUSRCLK2 Parameter Function Signals Setup Hold RRST Tgckc RRST Control input RXRESET Toccx_RPOL TgcKc_RPOL Control input RXPOLARITY Toccx_ECSY TgcKc_ECSY Control input ENCHANSYNC Clock to Out Tgcxst_RNIT Status outputs RXNOTINTABLE 3 0 TaGcksr RDERR Status outputs RXDISPERR 3 0 Tacksr RCMCH Status outputs 3 0 TaGcksr ALIGN Status output RXREALIGN TaGcksr CMDT Status output RXCOMMADET Tgcxst_RLOS Status outputs RXLOSSOFSYNC 1 0 Toce ROCUNT Status outputs RXCLKCORCNT 2 0 TaGcksr RBSTA Status outputs RXBUFSTATUS 1 0 RCCRC Status output RXCHECKINGCRC TaGcksr RCRCE Status output RXCRCERR Tockert CHBD Status output CHBONDDONE Tacksr RKCH Status outputs RXCHARISK 3 0 TGcksr RRDIS Status outputs RXRUNDISP 3 0 RDAT Data outputs RXDATA 31 0 Clock TRX2PWH Clock pulse width High state RXUSRCLK2 TpxorwH Clock pulse width Low state RXUSRCLK2
98. NFIGOUT Clock TTX2PWH Clock pulse width High state TXUSRCLK2 TTX2PWH Clock pulse width Low state TXUSRCLK2 Table A 5 Miscellaneous Clock Parameters Parameter Function Signals Clock TREFPWH Clock pulse width High state REFCLK TREFPWL Clock pulse width Low state REFCLK TBREFPWH Clock pulse width High state BREFCLK 0 TBREFPWL Clock pulse width Low state BREFCLK O TTX2PWH Clock pulse width High state TXUSRCLK 0 TTX2PWL Clock pulse width Low state TXUSRCLK 0 Notes 1 REFCLK is not synchronous to any RocketIO signals 2 BREFCLK is not synchronous to any RocketIO signals 3 TXUSRCLK is not synchronous to any RocketIO signals 134 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Timing Parameter Tables and Diagram 1 2 LG vw gt CLOCK BS Noy Tacck Taecke CONTROL f N INPUTS Tackco CONTROL OUTPUTS Lo DATA OUTPUTS DATA N INPUTS l 06012 106 02 100101 Figure A 2 RocketlO Transceiver Timing Relative to Clock Edge RocketlO Transceiver User Guide www xilinx com UG024 v2 4 August 25 2004 XILINX 135 A XILINX Appendix A RocketlO Transceiver Timing Model 136 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 XILINX Appendix
99. O AW11 AW10 AW9 AW19 AWI8 AW24 AW23 BB25 BB24 BB23 AWS AWI7 16 AW22 AW21 BB22 GT X4 A10 A9 A8 A19 A18 A17 A16 A24 A23 A22 A21 A25 A24 A23 A22 GT X5 YO AW7 AW6 AWS 15 AW14 19 18 21 20 19 AWA AW13 AW12 AWI17 AW16 BB18 GT X5 7 A6 5 4 A15 A14 A13 12 A19 A18 A17 A16 21 A20 A19 18 GT X6 YO AWII AW10 AW15 AW14 BB17 BB16 15 AWS AW13 AW12 14 GT X6 All A10 A9 A8 AIS A14 A12 Al2 A17 A16 A15 14 GT X7 YO 7 AW6 AWS AW11 AW10 AW9 BB13 BB12 BB11 AW4 AWS 10 GT X7 A7 A6 5 4 A10 9 8 A13 A12 A11 AIO GT X8 YO 8 BB7 BB6 GT X8 9 A8 A7 A6 GT X9 YO AW7 AW6 AWS 5 BB3 AWA BB2 GT X9 AT A6 5 4 AS A4 A3 A2 GT X10 YO GT X10 GT YO GT YI RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 127 A XILINX Chapter 4 Simulation and Implementation 128 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 XILINX Appendix A RocketIO Transceiver Timing Model This appendix explains all of the timing parameters associated with the RocketIOTM transceiver core It is intended to be used in conjunction with Module 3 of the Virtex II Pro Data Sheet and the Timing Analyzer TRCE report from Xilinx software For specific timing parameter va
100. OMMA MSB is TRUE the PCS places the comma into the most significant byte MSB of RXDATA in the 2 byte mode Because the PCS is optimized for the 2 byte mode some 70 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 SERDES Alignment A UNN uncertainty exists in the 4 byte mode as to which byte will contain the comma as shown in Table 2 12 See Receive Data Path 32 bit Alignment for more details on this case Table 2 12 Possible Locations of Comma Character Data Path Width ALIGN COMMA MSB 1 byte 2 bytes 4 bytes 7 0 15 8 7 0 31 24 23 16 15 8 7 0 TRUE V V V V FALSE V V V V V V V ENPCOMMAALIGN ENMCOMMAALIGN These two alignment ports control how the PMA aligns incoming serial data It can align on a minus comma negative disparity a plus comma positive disparity both or neither if comma alignment is not desired These signals are latched inside the transceiver with Care must be taken not to de assert these signals at the improper time Comma detection may be vulnerable to spurious realignment if RXRECCLK occurs at the wrong time To avoid this problem ENPCOMMAALIGN and ENMCOMMAALIGN should be passed through a flip flop that is clocked with RXRECCLK These flip flops should be located near the MGT and RXRECCLK should use local interconnect not global clock resources to reduce skew For both top and bottom edges the best s
101. RECCLK RXPOLARITY RXREALIGN RXCOMMADET ENPCOMMAALIGN ENMCOMMAALIGN RXCHECKINGCRC RXCRCERR RXDATA 15 0 RXDATA 31 16 RXP RXNOTINTABLE 3 0 RXN Comma i RXDISPERR 3 0 Deserializer Detect RXCHARISK 3 0 Realign Decoder RXCHARISCOMMA 3 0 RXRUNDISP 3 0 RXBUFSTATUS 1 0 ENCHANSYNC CHBONDDONE CHBONDI 3 0 CHBONDOJ 3 0 RXLOSSOFSYNC gt TXBUFERR TXFORCECRCERR TXDATA 15 0 TXDATA 31 16 i TXBYPASS8B10B 3 0 TXCHARISK 3 0 dd TXCHARDISPMODE 3 0 TXN Serializer Output Polarity XCHARDISPVAL 3 0 TXKERR 3 0 TXRUNDISP 3 0 TXPOLARITY TXINHIBIT LOOPBACK 1 0 TXRESET RXRESET REFCLK REFCLK2 REFCLKSEL BREFCLK 2 5V TX BREFCLK2 RXUSRCLK Termination Supply TX RXUSRCLK2 TXUSRCLK TXUSRCLK2 VTBX Termination Supply RX Channel Bonding and Clock Correction Serial Loopback Path Parallel Loopback Path f GNDA rx Rx GND AVCCAUXTX VTTX DS083 2 04 090402 Figure 1 1 RocketlO Transceiver Block Diagram 22 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 RocketlO Transceiver Instantiations XILINX Table 1 4 lists the sixteen gigabit transceiver primitives provided These primitives carry attributes set to default values for the communications protocols listed in Table 1 2 Data widths of one two and four
102. RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 XILINX XILINX Xilinx and the Xilinx logo shown above are registered trademarks of Xilinx Inc Any rights not expressly granted herein are reserved CoolRunner RocketChips Rocket IP Spartan StateBENCH StateCAD Virtex XACT XC2064 XC3090 XC4005 and XC5210 are registered trademarks of Xilinx Inc The shadow X shown above is a trademark of Xilinx Inc ACE Controller ACE Flash A K A Speed Alliance Series AllianceCORE Bencher ChipScope Configurable Logic Cell CORE Generator CoreLINX Dual Block EZTag Fast CLK Fast CONNECT Fast FLASH FastMap Fast Zero Power Foundation Gigabit Speeds and Beyond HardWire HDL Bencher IRL J Drive JBits LCA LogiBLOX Logic Cell LogiCORE LogicProfessor MicroBlaze MicroVia MultiLINX NanoBlaze PicoBlaze PLUSASM PowerGuide PowerMaze QPro RocketlO SelectlO SelectRAM SelectRAM Silicon Xpresso Smartguide Smart IP SmartSearch SMARTswitch System ACE Testbench In A Minute TrueMap UIM VectorMaze VersaBlock VersaRing Virtex Il Pro Virtex ll EasyPath Wave Table WebFITTER WebPACK WebPOWERED XABEL XACT Floorplanner XACT Performance XACTstep Advanced XACTstep Foundry XAPP X BLOX XC designated products XChecker XDM XEPLD Xilinx Foundation Series Xilinx Xinfo XSI XtremeDSP and ZERO are trademarks of Xilinx Inc The Programmable Log
103. T rxchariscomma3 RXCHARISCOMMA 3 rxchariscommal RXCHARISCOMMA 1 RARY IEEE IEEE std logic 1164 11 IEEE STD LOGIC ARITH ALL IEEE Numeric STD all IEEE STD LOGIC UNSIGNED ALL ITY align comma 32 IS PORT aligned data OUT std logic vector 31 DOWNTO 0 aligned rxisk OUT std logic vector 3 DOWNTO 0 sync OUT std logic usrclk2a IN std logic rxreset IN std logic rxdata IN std logic vector 31 DOWNTO 0 rxisk IN std logic vector 3 DOWNTO 0 rxrealign IN std logic rxcommadet IN std logic rxchariscomma3 IN std logic rxchariscommal IN std logic END ENTITY align comma 32 ARCHITECTURE translated OF align comma 32 IS 100 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Other Important Design Notes XILINX SIGNAL rxdata reg Std logic vector 15 DOWNTO 0 SIGNAL rxisk reg Std logic vector 1 DOWNTO 0 SIGNAL byte sync std logic SIGNAL wait to sync std logic vector 3 DOWNTO 0 SIGNAL count std logic SIGNAL rxdata hold Std logic vector 31 DOWNTO 0 SIGNAL rxisk hold std logic vector 3 DOWNTO 0 SIGNAL sync hold std logic BEGIN aligned data rxdata hold aligned rxisk rxisk hold sync lt sync hold PROCESS This process maintains wait to sync which are used only to maintain output sync this provides of when the output is properly aligned with the comma in aligned data 31 24 The counter is set to a high value
104. T will go to 101 regardless of whether the channel bonding was successful or not To determine if channel bonding was successful check both this signal and RXCLKCORONT CHBONDI CHBONDO These two 4 bit ports are used by the Master MGT to control its clock correction and channel bonding as well as those of any Slaves bonded to it CHBONDO of the Master is connected to CHBONDI ofa SLAVE 1 HOP The signal is then daisy chained from SLAVE 1 HOP CHBONDO to a SLAVE 2 HOPS CHBONDI See Figure 4 1 and Figure 4 2 page 124 and Table 2 18 page 82 for examples The three least significant bits correlate to the value of the RXCLKCORCNT port These four bits allow the Master to control when the Slaves perform clock correction This keeps channels from going out of sync if for instance one Slave repeated a CCS while another skipped RXCLKCORONT RXLOSSOFSYNC These signals are mainly used for clock correction However they can convey some information relevant to channel bonding as well Refer to RXCLKCORCNT and RXLOSSOFSYNC page 80 Troubleshooting Factors that influence channel bonding include e Skew between Master and Slave CBS arrival time both Master lags Slave and Slave lags Master cases The larger the separation the larger CHAN BOND WAIT needs to be e Arrival time between consecutive CBSs The smaller the separation is between consecutive CBSs the smaller HAN BOND WAIT needs to be set to ensure that the Master aligns to the
105. TH Integer 1 2 or 4 Relates to the data width of the FPGA fabric interface RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 31 XILINX Chapter 1 RocketlO Transceiver Overview Table 1 6 RocketlO Transceiver Attributes Continued Attribute RX DECODE USE Description This determines if the 8B 10B decoding is bypassed FALSE denotes that it is bypassed RX LOS INVALID INCR Power of two in a range of 1 to 128 that denotes the number of valid characters required to cancel out appearance of one invalid character for loss of sync determination RX LOS THRESHOLD Power of two in a range of 4 to 512 When divided by LOS INVALID INCR denotes the number of invalid characters required to cause FSM transition to sync lost state RX LOSS OF SYNC FSM TRUE FALSE denotes the nature of RXLOSSOFSYNC output TRUE RXLOSSOFSYNC outputs the state of the FSM bits See RXLOSSOFSYNC page 25 for details SERDES 10 Denotes whether the reference clock is 1 10 or 1 20 the serial bit rate TRUE 1 10 FALSE 1 20 FALSE supports a serial bitstream range of 1 0 Gb s to 3 125 Gb s TRUE supports a range of 600 Mb s to 1 0 Gb s See Halt Rate Clocking Scheme page 57 TERMINATION IMP Integer 50 or 75 Termination impedance of either 50Q or 75Q Refers to both the RX and TX TX BUFFER USE Always set to TRUE TX CRC
106. USRCLK and RXUSRCLK2 have different frequencies 1 2 and each edge of the slower clock is aligned to a falling edge of the faster clock The same relationships apply to TXUSRCLK and TXUSRCLK2 See Table 2 5 page 45 for details Clock and Data Recovery The clock data recovery CDR circuits lock to the reference clock automatically if the data is not present For proper operation TXUSRCLK must have the exact same frequency as REFCLK RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 www xilinx com Clock Recovery XILINX REFCLK RXUSRCLK and the incoming stream RXRECCLK must not exceed 100 ppm of frequency variation It is critical to keep power supply noise low in order to minimize common and differential noise modes into the clock data recovery circuitry See PCB Design Requirements page 111 for more details Clock Correction Clock RXRECCLK the recovered clock reflects the data rate of the incoming data Clock RXUSRCLK defines the rate at which the FPGA core consumes the data Ideally these rates are identical However since the clocks typically have different sources one of the clocks is faster than the other The receiver buffer accommodates this difference between the clock rates See Figure 2 20 Read Write RXUSRCLK RXRECCLK Nominal condition buffer half full Read Write Buffer less than half full emptying Repeatable sequence Read Write EN OE Buff
107. X Data Map with 8B 10B Bypassed During receive when 8B 10B decoding is enabled the running disparity of the serial transmission can be read by the transceiver from the RXRUNDISP port while the RXCHARISK port indicates presence of a K character When 8B 10B decoding is bypassed these bits remain as Bits b and respectively of the 10 bit encoded data that the transceiver passes on to the user logic Figure 2 14 illustrates the RX data map during 8B 10B bypass RXCHARISK 0 RXRUNDISP O0 RXDATA T RXDATA 0 a b d i f g h j EC First received Last received 06024 10b 051602 Figure 2 14 10 Bit RX Data Map with 8B 10B Bypassed 68 www xilinx com RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 8 10 Encoding Decoding A UNN 8B 10B Serial Output Format The 8B 10B encoding translates a 8 bit parallel data byte to be transmitted into a 10 bit serial data stream This conversion and data alignment are shown in Figure 2 15 The serial port transmits the least significant bit of the 10 bit data first and proceeds to j This allows data to be read and matched to the form shown in Appendix B 8B 10B Valid Characters D C B Parallel 8B 10B a b d i f g h j aaa Ea EE ERES First transmitted Last transmitted 00024 10 021102 Figure 2 15 8B 10B Parallel to Serial Conversion The serial data bit sequence is dependent
108. XILINX Table 2 9 Power Control Descriptions POWERDOWN Transceiver Status 0 Transceiver in operation 1 Transceiver temporarily powered down Notes 1 Unused transceivers are automatically configured as powered down by the implementation tools VHDL Template Module gt reset Description VHDL submodule reset for GT Device Virtex II Pro Family LIBRARY IEEE USE IEEE std logic 1164 all use IEEE STD LOGIC ARITH ALL use IEEE Numeric STD all use IEEE STD LOGIC UNSIGNED ALL pragma translate off library UNISIM use UNISIM VCOMPONENTS ALL pragma translate on entity gt reset is port USRCLK2 M in std logic LOCK in std logic REFCLK out std logic DCM LOCKED in std logic RST out std logic end gt reset architecture RTL of gt reset is signal startup count std logic vector 7 downto 0 begin process USRCLK2 M DCM LOCKED begin if USRCLK2 event and USRCLK2 M 1 then if DCM LOCKED 0 then startup count lt 00000000 elsif DCM LOCKED 1 then Startup count lt startup count 00000001 end if end if if USRCLK2 event and USRCLK2 M 1 then if DCM LOCKED 0 then RST 1 elsif startup count 00000010 then RST lt 0 end if RocketlO Transceiver User Guide www xilinx com 61 UG024 v2 4 August 25 2004 A XILINX Chapter 2 Digital Design Considerations end if end process
109. a is correctly decoded into parallel data Typographical The following typographical conventions are used in this document Convention Meaning or Use Example Messages prompts and program files that the system displays Speed grade 100 Literal commands that you enter Courier bold 4 in a syntactical statement ngdbuild design name Commands that you select from a Helvetica bold menu Keyboard shortcuts Ctrl C File Open Variables in a syntax statement il for which you must supply values nacht te design name See the Development System References to other manuals Reference Guide for more Italic font f information Ifa wire is drawn so that it Emphasis in text overlaps the pin of a symbol the two nets are not connected An optional entry or parameter Sonare bace A However in bus specifications ngdbuild option_name q such as bus 7 0 they are design name required A list of items from which you B 1 ff DES Je must choose one or more BEER i Verticalbar Separates items ina list of choices lowpwr RocketlO Transceiver User Guide www xilinx com 19 06024 v2 4 August 25 2004 7 XILINX 20 Preface About This Guide Convention Vertical ellipsis Meaning or Use Repetitive material that has been omitted Example 1 Name QOUT 2 Name CLKIN Horizontal ellips
110. ally with Infiniband a more in depth discussion 1s beyond the scope of this manual CRC START OF PACKET CRC END OF PACKET When implementing USER MODE CRC Start of Packet SOP and End of Packet EOP must be defined for the CRC logic These delimiters must be one of the defined K characters see Table B 2 page 145 These must be different than a clock correction sequence CCS or IDLE sequence otherwise the CRC will mistake the CCS or IDLE for SOP EOP Note These attribute are not applicable to the other CRC formats RXCHECKINGCRC RXCRCERR These two signals are status ports for the CRC circuitry RXCHECKINGCRC is asserted within several USRCLKs of the EOF being received from RXDATA This signals that the CRC circuitry has identified the SOF and the EOF If a CRC error occurred RXCRCERR will be asserted at the same time that goes High TXFORCECRCERR TX_CRC_FORCE_VALUE To test the CRC logic in either the MGT or the FPGA fabric TXFORCECRCERR and TX_CRC_FORCE_VALUE may be used to invoke a CRC error When TXFORCECRCERR is asserted High for at least one USRCLK2 cycle during data transmission between SOP and EOP the CRC circuitry is forced to TXDATA with TX CRC FORCE VALUE creating a bit error This should cause the receiver to register that a CRC error has occurred RocketlO CRC Support Limitations 90 There are limitations to the CRC support provided by the RocketIO transceiver core
111. also determines which package pins are used Table 4 1 shows the correlation between the LOC grid and the package pins themselves The pin numbers are TXNPAD TXPPAD RXPPAD and RXNPAD respectively The power pins are adjacent to these pins in the package pin diagrams of the User Guide Table 4 1 LOC Grid amp Package Pins Correlation for FG256 456 amp FF672 LOC FG256 FG456 FF672 Constraints 2 2 2 2VP2 2VP4 2VP7 2VP2 2VP4 2VP7 GT YO T4 T5 T6 7 AB7 ABS AB3 ABA AF18 AF17 AF23 AF22 AB9 AB10 AB5 AB6 AF16 AF15 AF21 AF20 GT A4 A5 A6 A7 7 9 A3 A4 A5 A6 A18 A17 A16 A23 A22 A21 A10 A15 A20 GT YO T10 T11 T12 AB13 AB14 ABS AF12 AF11 AF18 AF17 T13 AB15 AB16 AB9 AB10 AF10 AF9 AF16 AF15 GT A10 A11 A12 A13 A14 A15 A7 A8 A9 A12 A11 A10 18 17 16 A13 A16 A10 A9 A15 GT X2 YO AB13 14 AF12 AF11 AB15 AB16 AF10 AF9 GT X2 Y1 A13 A14 A15 A12 A11 A10 16 9 GT X3 YO 17 18 AF7 AF6 AB19 AB20 AF5 AF4 GT X3 Y1 17 18 19 5 4 20 RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 125 3 XILINX Table 4 2 LOC Grid amp Package Pins Correlation for FG676 FF896 and FF1152 Chapter 4 Simulation and Implementation
112. alue for VTRX is 1 7V See and DC Coupling section for more information 112 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 PCB Design Requirements Passive Filtering XILINX To achieve the necessary isolation from high frequency power supply noise passive filter networks are required on the power supply pins Figure 3 8 illustrates the difference in power filtering networks between a device that does contain capacitors Internal and a device that does not contain capacitors External Device with in package capacitors oa lt AVCCAUXTX AVCCAUXRX VTTX VTRX GNDA lt Device without in package capacitors HH EH AVCCAUXTX AVCCAUXRX VTTX VTRX 00024 48 021704 Figure 3 8 Power Filtering Network on Devices with Internal and External Capacitors Each transceiver power pin requires one capacitor and one ferrite bead The capacitors must be of value 0 22 uF in an 0603 EIA SMT package of X7R or X5R dielectric material at 15 tolerance rated to at least 5 V The ferrite bead is either the Murata BLM18AGIO2SNI or the Murata BLM15A6102SNID These components may not be shared among multiple RocketIO power supply pins under any circumstances Many of the Virtex II Pro devices have power filtering capacitors incorporated into the package to reduce component count on the PCB and improve the effectiv
113. and Local Headers 90 Table 2 22 Serial Speed Ranges as a Function of SERDES 10 93 Table 2 23 LOOPBACK 94 Table 2 24 32 bit RXDATA Aligned versus 96 RocketlO Transceiver User Guide www xilinx com 06024 v2 4 August 25 2004 15 XILINX 16 Chapter 3 Analog Design Considerations Table 3 1 Differential Transmitter Parameters 105 Table 3 2 Pre emphasis 106 Table 3 3 Differential Receiver Parameters 109 Table 3 4 CDR 110 Table 3 5 Transceiver Power Supply Ranges 111 Table 3 6 Qualified Linear 112 Table 3 7 Device and Package Combinations showing Devices with RocketIO Power Filtering Capacitors Internal to the Package and Externally Mounted on the PCB 114 Table 3 8 Recommended V rgy and V rry for AC and DC Coupled Environments 120 Chapter 4 Simulation and Implementation Table 4 1 LOC Grid amp Package Pins Correlation for FG256 456 amp 672 125 Table 4 2 LOC Grid amp Package Pins Correlation for FG676 FF896
114. ansceiver multiplies the reference frequency provided on the reference clock input REFCLK by 20 or by 10 if half rate operation is selected Data is converted from parallel to serial format and transmitted on the TXP and TXN differential outputs The electrical polarity of TXP and TXN can be interchanged through the TXPOLARITY port This option can either be programmed or controlled by an input at the FPGA core TX interface This facilitates recovery from situations where printed circuit board traces have been reversed Deserializer The RocketIO transceiver core accepts serial differential data on its RXP and RXN inputs The clock data recovery circuit extracts clock phase and frequency from the incoming data stream and re times incoming data to this clock The recovered clock is presented on output RXRECCLK at 1 20 of the received serial data rate The receiver is capable of handling either transition rich 8B 10B streams or scrambled streams and can withstand a string of up to 75 non transitioning bits without an error Word alignment is dependent on the state of comma detect bits If comma detect is enabled the transceiver recognizes up to two 10 bit preprogrammed characters Upon detection of the character or characters RK COMMADET is driven High and the data is synchronously aligned If a comma is detected and the data is aligned no further alignment alteration takes place If a comma 15 received and realignment is necessary the data is
115. atching Clock RXUSRCLK must be frequency locked with RXRECCLK in this case TRUE Enable clock correction normal mode COMMA 10B MASK This 10 bit vector defines the mask that is ANDed with the incoming serial bit stream before comparison against PCOMMA 10B VALUE and MCOMMA 10B VALUE CRC END OF PKT NOTE This attribute is only valid when CRC FORMAT USER MODE K28 0 K28 1 K28 2 K28 3 K28 4 K28 5 K28 6 K28 7 K23 7 K27 7 K29 7 K30 7 End of packet EOP K character for USER MODE CRC Must be one of the 12 legal K character values 30 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Primitive Attributes XILINX Table 1 6 RocketlO Transceiver Attributes Continued Attribute CRC FORMAT Description ETHERNET INFINIBAND FIBRE CHAN USER MODE CRC algorithm selection Modifiable only for AURORA n XAUI GT CUSTOM USER MODE allows user definition of Start of Packet SOP and End of Packet EOP K characters CRC START OF PKT NOTE This attribute is only valid when CRC FORMAT USER MODE K28 0 K28 1 K28 2 K28 3 K28 4 K28 5 K28 6 K28 7 K23 7 K27 7 K29 7 K30 7 Start of packet SOP K character for USER MODE CRC Must be one of the twelve legal K character values DEC MCOMMA DETECT TRUE FALSE controls the raising of per byte flag RXCHARISCOMMA on minus comma DEC PCOMMA DETECT TRUE FALSE contro
116. band 90 Local Route 90 Serial and Parallel Loopback 95 RXDATA Aligned Correctly 96 Realignment of RXDATA I I 96 Chapter 3 Analog Design Considerations Differential 105 Figure 3 2 Alternating K28 5 with No 107 RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 13 3 XILINX Figure 3 3 K28 5 with 107 Figure 3 4 Eye Diagram 10 Pre Emphasis 20 4 Worst Case Conditions 108 Figure 3 5 Eye Diagram 33 Pre Emphasis 20 4 Worst Case Conditions 108 Figure3 0 MGT Receiver e ooo De ee TX EE AER 109 Figure 3 7 Power Supply Circuit Using Approved Regulator 112 Figure 3 6 Power Filtering Network on Devices with Internal and External Capacitors 113 Figure 3 9 Example Power Filtering PCB Layout for Four MGTs in Device with Internal Capacitors Bottom 115 Figure 3 10 Example Power Filtering PCB Layout for Four MGTs In Device with External Capacitors Top
117. bled When clock correction is disabled RKXRECCLK must drive the receive logic in the fabric Otherwise the elastic buffer may over underflow Clock correction may be used with other encoding protocols but they must have a 10 bit alignment scheme This is required so the comma detection logic can properly align the data in the elastic buffer allowing the clock correction logic to properly read out data to the FPGA fabric RX BUFFER USE The RX BUFFER USE attribute controls if the elastic buffer is bypassed or not Most applications use this buffer for clock correction and channel bonding See Channel Bonding Channel Alignment page 81 It is recommended that this attribute always be set to TRUE since this RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 www xilinx com Clock Recovery XILINX buffer allows a way to cross the clock domains of RXRECCLK and the fabric RXUSRCLK RXUSRCLK2 CLK COR SEQ CLK To accommodate many different protocols the MGT features programmability that allows it to detect a 1 2 or 4 byte clock correction sequence CCS such as may be used in Gigabit Ethernet 2 byte or Fibre Channel 4 byte The attributes CLK COR SEQ and CLK COR SEQ LEN below define the CCS that the PCS recognizes Both SEQ 1 and SEQ 2 can be used at the same time if multiple CCSs are required As shown in Table 2 15 the example CCS has two possible modes one for when 8B 10B encoding is used
118. buffer during clock correction TRUE In the final RXDATA stream the transceiver must leave at least one clock correction sequence per continuous stream of clock correction sequences CLK COR REPEAT WAIT Integer 0 31 controls frequency of repetition of clock correction operations This attribute specifies the minimum number of RXUSRCLK cycles without clock correction that must occur between successive clock corrections If this attribute 1s zero no limit is placed on how frequently clock correction can occur CLK COR SEQ 11 bit vectors that define the sequence for clock correction The attribute used depends on the CLK COR SEQ LEN and CLK_COR_SEQ 2 USE CLK COR SEQ 2 USE TRUE FALSE controls use of second clock correction sequence FALSE Clock correction uses only one clock correction sequence defined by CLK COR SEQ 1 1 4 TRUE Clock correction uses two clock correction sequences defined by CLK COR SEQ 1 1 4 and CLK COR SEQ 2 1 4 as further constrained by CLK SEQ LEN CLK COR SEQ LEN Integer that defines the length of the sequence the transceiver matches to detect opportunities for clock correction It also defines the size ofthe correction since the transceiver executes clock correction by repeating or skipping entire clock correction sequences CLK CORRECT USE TRUE FALSE controls the use of clock correction logic FALSE Permanently disable execution of clock correction rate m
119. bytes are selectable for each protocol Table 1 4 Supported RocketlO Transceiver Primitives Primitives Description Primitive Description GT CUSTOM Fully customizable GT XAUI 2 10 Gb Ethernet T 2 byte data path GT FIBRE CHAN 1 Fibre Channel GT XAUI 4 10 Gb Ethernet 1 byte data path 4 byte data path Fibre Channel 2 byte data path Infiniband 1 byte GT FIBRE CHAN 2 data path GT INFINIBAND 1 Fibre Channel 4 byte data path Infiniband 2 byte GT FIBRE CHAN 4 data path GT INFINIBAND 2 Gigabit Ethernet 1 byte data path Infiniband 4 byte GT_ETHERNET 1 data path GT_INFINIBAND 4 Gigabit Ethernet Xilinx protocol 2 byte data path 1 byte data path Gigabit Ethernet Xilinx protocol PETERS 4 byte data path 2 byte data path GT XAUI 1 10 Gb Ethernet GT AURORA 4 Xilinx protocol 1 byte data path 4 byte data path There are two ways to modify the RocketIO transceiver e Static properties can be set through attributes in HDL code Use of attributes are covered in detail in Primitive Attributes page 28 e Dynamic changes can be made by the ports of the primitives The RocketIO transceiver consists of the Physical Media Attachment PMA and Physical Coding Sublayer PCS The PMA contains the serializer deserializer SERDES TX and RX buffers clock generator and clock recovery circuitry The PCS contains the 8B 10B encoder d
120. c and other internal receive registers It does not reset the receiver PLL RXRUNDISP 1 2 4 Signals the running disparity 0 negative 1 positive in the received serial data If 8B 10B encoding is bypassed it remains as the second bit received Bit b of the 10 bit encoded data see Figure 2 14 page 68 RXUSRCLK Clock from a DCM or a BUFG that is used for reading the RX elastic buffer It also clocks CHBONDI and CHBONDO in and out of the transceiver Typically the same as TXUSRCLK RXUSRCLK2 Clock output from a DCM that clocks the receiver data and status between the transceiver and the FPGA core Typically the same as TXUSRCLK2 The relationship between RXUSRCLK and RXUSRCLK2 depends on the width of RXDATA TXBUFERR Provides status of the transmission FIFO If asserted High an overflow underflow has occurred When this bit becomes set it can only be reset by asserting TXRESET TXBYPASS8B10BO 1 2 4 This control signal determines whether the 8B 10B encoding is enabled or bypassed If the signal is asserted High the encoding 15 bypassed This creates a 10 bit interface to the FPGA core See the 8B 10B section for more details TXCHARDISPMODEO 1 2 4 If 8B 10B encoding is enabled this bus determines what mode of disparity is to be sent When 8B 10B 15 bypassed this becomes the first bit transmitted Bit a of the 10 bit encoded TXDATA bus section see Figure 2 13 page 68
121. ces For this reason it is required that both dedicated voltage regulators and passive high frequency filtering be used to power the RocketIO circuitry Table 3 5 Transceiver Power Supply Ranges mW M PEDE Me me Coupled Coupled AVCCAUXRX 90 90 Analog RX supply AVCCAUXTX 130 130 Analog TX supply VTRXO 37 500 00 RX termination supply VTTX 37 5 750 TX termination supply GNDA N A N A E for transmit and receive Notes 1 Power at max data rate Power figures shown do not include power requirements of 28 mW and Vocayx 48 mW which power the PCS and PMA respectively 2 See section and DC Coupling page 118 and Table 3 8 for VTRX supply restrictions in AC and DC coupled cases 3 These numbers are based on VTTX at 2 5V for the DC and AC coupled cases VTRX at 2 5V for the DC coupled case and 1 8V for the AC coupled case 4 Pre emphasis and swing settings are optimal at VTTX 2 5V 4 5 VTTX can be powered with as low as 1 8V in applications with data rates below 1 25 Gb s LVDS interfacing Contact your Xilinx FAE for more information on such interfaces Voltage Regulator Selection and Use Xilinx has qualified a number of linear regulators for use with RocketIO transceivers RocketIO supplies must be powered by voltage regulators meeting the following criteria Must be a linear or LDO regulator switching or DC
122. dge of RXUSRCLK2 to RX Data outputs Iecker TBERR Rising edge of TXUSRCLK2 to TX Buffer Err output RocketlO Transceiver User Guide www xilinx com 131 UG024 v2 4 August 25 2004 A XILINX Appendix A RocketlO Transceiver Timing Model Clock Pulse Width ParameterName Format Minimum pulse width High state Minimum pulse width Low state where x REF REFCLK TX TXUSRCLK TX2 TXUSRCLK2 RX RXUSRCLK RX2 RXUSRCLK2 Pulse Width Examples TrxopwL Minimum pulse width TX2 clock Low state TrerpwH Minimum pulse width Reference clock High state Timing Parameter Tables and Diagram The following four tables list the timing parameters as reported by the implementation tools relative to the clocks given in Table A 1 along with the RocketIO signals that are synchronous to each clock No signals are synchronous to REFCLK or TXUSRCLK A timing diagram Figure A 2 illustrates the timing relationships e Table A 2 Parameters Relative to the RX User Clock RXUSRCLK page 132 Table A 3 Parameters Relative to the RX User Clock2 RXUSRCLK2 page 133 e Table A 4 Parameters Relative to the TX User Clock2 TXUSRCLK2 page 133 e A 5 Miscellaneous Clock Parameters page 134 Table A 2 Parameters Relative to the RX User Clock RXUSRCLK Parameter Function Signals Setup Hold Tacck CHBI Control inputs CHBO
123. e emphasis A second characteristic of RocketIO transceiver pre emphasis is that the STRONG level is reduced after some time to the LOGIC level thereby minimizing the voltage swing necessary to switch the differential pair into the opposite state Lossy transmission lines cause the dissipation of electrical energy This pre emphasis technique extends the distance that signals can be driven down lossy line media and increases the signal to noise ratio at the receiver It should be noted that high pre emphasis settings are not appropriate for short links a fraction of the maximum length of 40 inches of 4 Excessive pre emphasis can actually degrade the bit error rate BER of a multi gigabit link Careful simulation and or lab testing of the system should always be used to verify that the optimal pre emphasis setting is in use Consult the Virtex 1I Pro RocketIOTM Multi Gigabit Transceiver Characterization Summary for more detailed information on the waveforms to be expected at the various pre emphasis levels The four levels of pre emphasis are shown in Table 3 2 Table 3 2 Pre emphasis Values Attribute Values Emphasis 0 10 1 20 2 25 3 33 www Xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Pre emphasis Techniques A XILINX m i i i H S DE qub did 1 x 00024 17 020802 Figure 8 2 Alternating K28 5 with Pre Emphasis
124. e illegal 10 bits through and places them on the outputs This can be used for debugging purposes if desired The decoder also signals reception of one ofthe twelve valid K characters Table B 2 page 145 by way of the RXCHARISK port In addition a programmable comma detect is included The comma detect signal RXCOMMADET registers a comma on the receipt of any plus comma minus comma or both Since the comma is defined as a 7 bit character this includes several out of band characters RKCHARISCOMMA allows the decoder to detect only the three defined commas K28 1 K28 5 and K28 7 as plus comma minus comma or both In total there are six possible options three for valid commas and three for any comma Note that all bytes 1 2 or 4 at the RX FPGA interface each have their own individual 8B 10B indicators K character disparity error out of band error current running disparity and comma detect RocketlO Transceiver User Guide www xilinx com 63 06024 v2 4 August 25 2004 3 XILINX Chapter 2 Digital Design Considerations Ports and Attributes TXBYPASS8B10B RX_DECODE_USE One port and one attribute enable 8B 10B encoding decoding in the transceiver TXBYPASS8B10B is a byte mapped port that is 1 2 or 4 bits wide depending on the data width of the transceiver primitive being used These bits correlate to each byte of the data path To enable 8B 10B encoding in the transmitter these bits must be set Low In t
125. ecoder and the elastic buffer supporting channel bonding and clock correction The PCS also handles Cyclic Redundancy Check CRC Refer again to Figure 1 1 showing the RocketIO transceiver top level block diagram and FPGA interface signals RocketlO Transceiver Instantiations For the different clocking schemes several things must change including the clock frequency for USRCLK and USRCLK2 discussed in Digital Clock Manager DCM Examples in Chapter 2 The data and control ports for GT CUSTOM must also reflect this change in data width by concatenating zeros onto inputs and wires for outputs for Verilog designs and by setting outputs to open and concatenating zeros on unused input bits for VHDL designs HDL Code Examples Please use the Architecture Wizard to create instantiation templates This wizard creates code and instantiation templates that define the attributes for a specific application RocketlO Transceiver User Guide www xilinx com 23 06024 v2 4 August 25 2004 X XILINX List of Available Ports The RocketIO transceiver primitives contain 50 ports with the exception of the 46 port GT_ETHERNET and GT_FIBRE_CHAN primitives The differential serial data ports RXN RXP TXN and TXP are connected directly to external pads the remaining 46 ports are all accessible from the FPGA logic 42 ports for GT_ETHERNET and GT FIBRE CHAN Chapter 1 RocketlO Transceiver Overview Table 1 5 contains the port descript
126. end RTL Verilog Template Module gt reset Description Verilog Submodule reset for4 byte GT Device Virtex II Pro Family module gt_reset USRCLK2 M DCM LOCKED RST input USRCLK2 M input DCM LOCKED output RST wire USRCLK2 wire DCM LOCKED reg RST reg 7 0 startup counter always 9 posedge USRCLK2 M if DCM LOCKED startup counter lt 8 h0 else if startup counter 8 h02 Startup counter lt startup counter 1 always posedge USRCLK2 M or negedge DCM LOCKED if DCM LOCKED RST 1 b1 else RST startup counter 8 h02 endmodule 62 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 8 10 Encoding Decoding A XILINX 8B 10B Encoding Decoding Overview The RocketIO transceiver has the ability to encode eight bits into a 10 bit serial stream using standard 8B 10B encoding This guarantees a DC balanced edge rich serial stream facilitating DC or AC coupling and clock recovery Table 2 10 page 65 shows the significance of 8B 10B ports that change purpose depending on whether 8B 10B is bypassed or enabled 8B 10B Encoder A bypassable 8B 10B encoder is included in the transmitter The encoder uses the same 256 data characters and 12 control characters shown in Appendix B 8B 10B Valid Characters that are used for Gigabit Ethernet XAUI Fibre Channel and InfiniBand The encoder accepts 8 bits
127. eness of these capacitors Table 3 7 outlines which device package combinations have 0 22 UF capacitors internal to the package and which devices do not External ferrite beads must be used in all cases as ferrite beads are not included inside the package in any device Table boxes labeled External denote a device for which the user must provide power filtering capacitors externally on the PCB those labeled Internal denote a device that contains all necessary 0 22 UF capacitors for RocketIO power pins Table boxes that say MGTs denote a device that does not have any RocketIO transceivers RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 113 X XILINX Chapter 3 Analog Design Considerations Table 3 7 Device and Package Combinations showing Devices with RocketlO Power Filtering Capacitors Internal to the Package and Externally Mounted on the PCB XC2VP2 XC2VP4 XC2VP7 XC2VP20 XC2VP30 XC2VP40 XC2VP50 XC2VP70 XC2VP100 FG256 External External FG456 External External External FF672 Internal Internal Internal FG676 External External External FF896 Internal Internal Internal FF1152 Internal Internal Internal Internal FF1148 No MGIS No MGIS FF1517 Internal Internal Internal FF1704 Internal Internal FF1696 No MGIS For devices that do not contain filtering capacitors in their package the 0 22 UF capacitors
128. ent that devices shown or products described herein are free from patent infringement or from any other third party right Xilinx Inc assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made Xilinx Inc will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user Xilinx products are not intended for use in life support appliances devices or systems Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited The contents of this manual are owned and copyrighted by Xilinx Copyright 1994 2003 Xilinx Inc All Rights Reserved Except as stated herein none of the material may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of any material contained in this manual may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes RocketlO Transceiver User Guide www xilinx com UG024 v2 4 August 25 2004 RocketiO Transceiver User Guide 00024 v2 4 August 25 2004 The following table shows the revision history for this document Date 11 20 01
129. er more than half full filling up Removable sequence 5083 2 15 100901 Figure 2 20 Clock Correction Receiver Nominally the buffer is always half full This is shown in the top buffer where the shaded area represents buffered data not yet read Received data is inserted via the write pointer under control of RXRECCLK The FPGA core reads data via the read pointer under control of RXUSRCLK The half full half empty condition of the buffer gives a cushion for the differing clock rates This operation continues indefinitely regardless of whether or not meaningful data is being received When there is no meaningful data to be received the incoming data consists of IDLE characters or other padding If RXUSRCLK is faster than RXRECCLK the buffer becomes more empty over time The clock correction logic corrects for this by decrementing the read pointer to reread a repeatable byte sequence This is shown in the middle buffer Figure 2 20 where the solid read pointer decrements to the value represented by the dashed pointer By decrementing the read pointer instead of incrementing it in the usual fashion the buffer is partially refilled The transceiver inserts a single repeatable byte sequence when necessary to refill a buffer If the byte sequence length is greater than one and if attribute COR REPEAT WAIT is 0 then the transceiver can repeat the same sequence multiple times until the buffer is refilled to the half full conditio
130. esign Considerations RXREALIGN clears this bit RXBUFSTATUS 0 High indicates that the elastic buffer is at least half full RX BUFFER USE When set to FALSE this attribute causes the receive buffer to be bypassed It should normally be set to TRUE since channel bonding and clock correction use the receive buffer for realignment When the buffer 1s bypassed the user logic must be clocked with RXRECCLK Miscellaneous Signals Ports and Attributes 92 Several ports and attributes of the MGT have very unique functionality The following do not have large roles in the other functionality discussed so far RX DATA WIDTH TX DATA WIDTH These two attributes define the data width in bytes of RXDATA and TXDATA respectively The possible values of each attribute are 1 2 and 4 which correspond to 8 16 and 32 bit data buses when 8B 10B encoding decoding is used See 8B 10B Encoding Decoding page 63 The bus widths are 10 20 and 40 bits when 8B 10B encoding decoding is bypassed SERDES 10B This attribute allows the MGT to expand its serial speed range The normal operational speed range of 1 0 Gb s to 3 125 Gb s 20 times the reference clock rate is obtained when this attribute is set to FALSE When set to TRUE the MGT serial data will run at 10 times the reference clock rate producing a speed range of 600 Mb s to 1 Gb s Table 2 22 Serial Speed Ranges as a Function of SERDES 10 SERDES 10B Reference Clock Ran
131. ets Device specific information on Xilinx device characteristics including readback boundary scan configuration length count and debugging http support xilinx com xInx xweb xil_publications_index jsp Problem Solvers Interactive tools that allow you to troubleshoot your design issues http support xilinx com support troubleshoot psolvers htm Tech Tips Latest news design tips and patch information for the Xilinx design environment http www support xilinx com xInx xil_tt_home jsp 18 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Conventions A UNN Conventions This document uses the following conventions An example illustrates each typographical and online convention Port and Attribute Names Input and output ports of the RocketIO transceiver primitives are denoted in upper case letters Attributes of the RocketIO transceiver are denoted in upper case letters with underscores Trailing numbers in primitive names denote the byte width of the data path These values are preset and not modifiable When assumed to be the same frequency RKUSRCLK and TXUSRCLK are referred to as USRCLK and can be used interchangeably This also holds true for RKUSRCLK2 TXUSRCLK2 and USRCLK2 Comma Definition is a K character used by the transceiver to align the serial data on a byte half word boundary depending on the protocol used so that the serial dat
132. for the capacitors and ferrite beads of AVCCAUXTX and AVCCAUXRX supplies The ferrite beads are mounted at the eight L n locations the capacitors are mounted at the eight C n locations gt d gt X S Hes X s Ke x 2 Figure 3 10 Example Power Filtering Layout for Four MGTs In Device with External Capacitors Top Layer RocketlO Transceiver User Guide www xilinx com 115 UG024 v2 4 August 25 2004 A XILINX Chapter 3 Analog Design Considerations Figure 3 11 Example Power Filtering PCB Layout for Four MGTs in Device with External Capacitors Bottom Layer High Speed Serial Trace Design Routing Serial Traces RocketIO transceiver I Os are placed on the periphery of the package to facilitate routing and inspection since JTAG is not available on serial I O pins Two output input impedance options are available in the RocketIO transceivers 50Q and 75 2 Controlled impedance traces with a corresponding impedance should be used to connect the RocketIO transceiver to other compatible transceivers In chip to chip PCB applications 50Q termination and 100Q differential transmission lines are recommended When routing a differential pair the complementary traces must be matched in length to as close a tolerance as is feasible Length mismatches produce common mode noise and radiation Severe length mismatches produce jitter and unpredictable timing problems at the receiver
133. for the receiver that is byte mapped to RXDATA When a bit in RXDISPERR is asserted High it means that a disparity error has occurred in the received data This usually indicates data corruption bit errors or transmission of an invalid control character It can also occur in cases where normal disparity is not required such as in the Vitesse Disparity Example RXNOTINTABLE RXNOTINTABLE is a status port for the receiver that is byte mapped to RXDATA When it is asserted High it means that the received data is not in the 8B 10B tables This port is only used when the 8B 10B decoder is enabled Vitesse Disparity Example To support other protocols the transceiver can affect the disparity mode of the serial data transmitted For example Vitesse channel to channel alignment protocol sends out K28 5 28 5 K28 5 K28 5 or K28 5 K28 5 K28 5 K28 5 instead of K28 5 K28 5 28 5 K28 5 or K28 5 K28 5 K28 5 28 5 The logic must assert TXCHARDISPVAL to cause the serial data to send out two negative running disparity characters Note If bypassing 8B 10B encoding decoding the remaining 10 bits will be the 10 bit encoded version of the channel bonding sequence This is the same as the clock correction sequence shown in Table 2 15 page 77 Transmitting Vitesse Channel Bonding Sequence TXBYPASS8B10B TXCHARISK TXCHARDISPMODE TXCHARDISPVAL TXDATA ll ld 010010111100 28 5 or K28 5 010110111
134. g character P or to some location relative to the channel bonding character After this operation the words transmitted to the FPGA core are properly aligned RRRR SSSS TTTT etc as shown in the bottom right portion of Figure 2 22 To ensure that the channels remain properly aligned following the channel bonding operation the Master transceiver must also control the clock correction operations described in the previous section for all channel bonded transceivers RocketlO Transceiver User Guide www xilinx com 81 06024 v2 4 August 25 2004 A XILINX Chapter 2 Digital Design Considerations Channel Bonding Alignment Operation Channel bonding is the technique of tying several serial channels together to create one aggregate channel Several channels are fed on the transmit side by one parallel bus and reproduced on the receive side as the identical parallel bus The maximum number of serial differential pairs that can be bonded is 24 For implementation guidelines see Implementation Tools page 123 Channel bonding allows those primitives that support it to send data over multiple channels Among these primitives are CUSTOM GT INFINIBAND XAUI and GT AURORA To bond channels together there is always one Master The other channels can either be a SLAVE 1 or SLAVE 2 HOPS SLAVE 1 HOP is a Slave to a Master that can also be daisy chained toa SLAVE 2 HOPS ASLAVE 2 HOPS can only bea Slavetoa S
135. ge Serial Speed Range TRUE 60 100 MHz 600 Mb s 1 0 Gb s FALSE 50 156 25 MHz 1 0 Gb s 3 125 Gb s TERMINATION IMP Receive Termination On chip termination is provided at the receiver eliminating the need for external termination The receiver includes programmable on chip termination circuitry for 50 2 default or 759 impedance Transmit Termination On chip termination is provided at the transmitter eliminating the need for external termination Programmable options exist for 500 default and 75Q termination www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Miscellaneous Signals A XILINX TXPOLARIT Y RXPOLARIT Y TXINHIBIT A differential pair has a positive designated and a negative designated component If for some reason the polarity of these components is switched between two transceivers the data will not be passed properly If this occurs TXPOLARITY will invert the definition of the TXN and TXP pins On the receiver side of the MGT the RXPOLARITY port can invert the definition of RXN and RXP For some protocols the MGT must turn off the TXN TXP pins The TXINHIBT port shuts off the transmit pins and forces them to a constant value TXN 0 TXP 1 Asserting TXINHIBIT also disables internal serial loopback TX DIFF CTRL PRE EMPHASIS These two attributes control analog functionality of the MGT The TX DIFF CTRL attribute is used to compensate for signa
136. gned 4 bit RXCHARISK Inputs These are all RocketIO inputs or outputs as indicated usrclk2 RXUSRCLK2 rxreset RXRESET rxisk 3 0 RXCHARISK 3 0 rxdata 31 0 RXDATA 31 0 commas aligned to 31 24 or 15 8 rxrealign RXREALIGN rxcommadet RXCOMMADET rxchariscomma3 RXCHARISCOMMA 3 rxchariscommal RXCHARISCOMMA 1 module align comma 32 aligned data aligned rxisk sync usrclk2 rxreset rxdata rxisk rxrealign rxcommadet rxchariscomma3 rxchariscommal output 31 0 aligned data output 3 0 aligned rxisk output sync reg 31 0 aligned data reg Sync input usrclk2 input rxreset input 31 0 rxdata input 3 0 rxisk input rxrealign input rxcommadet input rxchariscomma3 input rxchariscommal reg 15 0 rxdata reg reg 1 30 rxisk reg reg 3 0 aligned rxisk reg byte sync reg 3 0 wait to sync reg count RocketlO Transceiver User Guide www xilinx com 97 06024 v2 4 August 25 2004 A XILINX Chapter 2 Digital Design Considerations This process maintains wait to sync and count which are used only to maintain output sync this provides some idea of when the output is properly aligned with the comma in aligned data 31 24 The counter is set to a high value whenever the elastic buffer is reinitialized that is upon asserted RXRESET or RXREALIGN Count down is enabled whenever a comma is known t
137. h paths and all byte mapped ports are affected by this situation For example 1 byte wide data path has only 1 bit control and status bits TXKERR 0 correlating to the data bits TXDATA 7 0 Footnote 3 in Table 1 5 shows the ports that use byte mapping Table 1 9 Control Status Bus Association to Data Bus Byte Paths Control Status Bit Data Bits 0 7 0 1 15 8 2 23 16 3 31 24 RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 37 A XILINX Chapter 1 RocketlO Transceiver Overview 38 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 XILINX Chapter 2 Digital Design Considerations Clocking Clock Signals There are eight clock inputs into each RocketIO transceiver instantiation Table 2 1 REFCLK and BREFCLK are reference clocks generated from an external source and presented to the FPGA as differential inputs The reference clocks connect to the REFCLK or BREFCLK ports of the RocketIO multi gigabit transceiver MGT While only one of these reference clocks is needed to drive the BREFCLK or BREFCLK2 must be used for serial speeds of 2 5 Gb s or greater See BREFCLK page 43 To clock the serial data the PLL architecture for the transceiver uses the reference clock as the interpolation source Removing the reference clock stops the RX and TX PLLs from working Therefore a reference clock must be pr
138. hile this type of lag is equivalent to approximately 14 ns at 3 125 Gb s it is recommended that channel links be matched as closely as possible The equation that produces this maximum lag time result is lag time ns 1 serial speed Gb s e number of lag bytes 10 bits byte or for schemes that do not use 8B 10B encoding 1 serial speed Gb s e number of 10 bit lag characters 10 bits character In the example above 1 3 125 Gb s 4 5 bytes 10 bits byte 14 4 ns The recommended setting of 8 is set for protocols such as Infiniband and XAUI which can repeat the CBS every 16 and 17 bytes respectively However CHAN BOND WAIT can grow accordingly 1f CBSs are spaced farther apart BOND OFFSET CHAN BOND WAIT CHAN BOND OFFSET measures the number of bytes past the beginning of the channel bonding sequence However this value must always equal CHAN BOND WAIT CHAN BOND LIMIT 2X CHAN BOND WAIT CHAN BOND LIMIT defines the expiration time after which the Slave will invalidate the most recently seen CBS location in the RX buffer For proper alignment this value must always be set to two times CHAN BOND WAIT CHBONDDONE This port indicates when a channel alignment has occurred in the MGT When it is asserted RXDATA is valid after RXCLKCORCNT goes to a 101 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 CRC Cyclic Redundancy Check A UNN Note The Slave s RXCLKCORCN
139. his mode the transmit data input to the TXDATA port is non encoded data of either 8 16 or 32 bits wide However if other encoding schemes are preferred the encoder capabilities can be bypassed by setting all bits High In this mode the data input to TXDATA is either 10 20 or 40 bits wide The extra bits are fed through the TXCHARDISPMODE and TXCHARDISPVAL buses shown in Table 2 10 The decoder is controlled by the attribute RX_DECODE_USE When this attribute is set to TRUE the decoder is enabled and should coincide with TXB YPASS8B10B being set Low In this mode the received data output from the RXDATA port is decoded data either 8 16 or 32 bits wide However when the attribute is set to FALSE the decoder is disabled In this mode the received data is 10 20 or 40 bits wide and the extra bits are provided by RXCHARISK and RXRUNDISP shown in Table 2 10 If this pair is not matched the data is not received correctly Figure 2 12 shows the encoding decoding blocks of the transceiver and how the data passes through these blocks Table 2 10 shows the significance of 8B 10B ports that change purpose depending on whether 8B 10B is bypassed or enabled Transceiver Module Physical Coding Sublayer Physical Media Attachment Mindspeed IP 32 16 8 bits F 8B 10B Transmit Py Xt TXDATA ALY wee _ Encode Serializer Buffer TX TX Clock Generator E Channel Bondin S 9 S S 20X
140. his port is undefined RXCOMMADET This signal indicates if a comma character has been detected in the serial data The definition of this port is defined by the PCOMMA DETECT and MCOMMA DETECT attributes This signal is clocked off RXRECCLK and to reliably have the signal pulse for all the data width configurations this pulse may change with respect to the USRCLKs Table 2 13 Effects of Comma Related Ports and Attributes Affects Character X Affects Affects Port or Attribute Alignment and RXCHARISCOMMA RXCOMMADET RXREALIGN DEC VALID COMMA ONLY DEC PCOMMA DETECT y DEC MCOMMA DETECT PCOMMA 10B VALUE J MCOMMA 10B VALUE PCOMMA DETECT gd MCOMMA DETECT ENPCOMMAALIGN ENMCOMMAALIGN Clock Recovery Overview Clock Synthesizer Synchronous serial data reception is facilitated by a clock data recovery circuit This circuit uses a fully monolithic Phase Locked Loop PLL which does not require any external components The clock data recovery circuit extracts both phase and frequency from the incoming data stream The recovered clock is presented on output RXRECCLK at 1 20 of the serial received data rate The gigabit transceiver multiplies the reference frequency provided on the reference clock input REFCLK by 20 No fixed phase relationship is assumed between REFCLK RXRECCLK and or any other clock that is not tied to either of these clocks When the 4 byte or 1 byte receiver data path is used RX
141. ic Company is a service mark of Xilinx Inc All other trademarks are the property of their respective owners Xilinx Inc does not assume any liability arising out of the application or use of any product described or shown herein nor does it convey any license under its patents copyrights or maskwork rights or any rights of others Xilinx Inc reserves the right to make changes at any time in order to improve reliability function or design and to supply the best product possible Xilinx Inc will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products Xilinx provides any design code or information shown or described herein as is By providing the design code or information as one possible implementation of a feature application or standard Xilinx makes no representation that such implementation is free from any claims of infringement You are responsible for obtaining any rights you may require for your implementation Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation including but not limited to any warranties or representations that the implementation is free from claims of infringement as well as any implied warranties of merchantability or fitness for a particular purpose Xilinx Inc devices and products are protected under U S Patents Other U S and foreign patents pending Xilinx Inc does not repres
142. ices combined with the programmable logic of the Virtex II Pro FPGAs makes it possible to implement HD SDI interfaces Because every Virtex II Pro FPGA has multiple RocketIO transceivers multiple HD SDI interfaces can be integrated into one Virtex II Pro device along with other video processing functions This application note describes how to implement HD SDI receivers An HD SDI receiver built in a Virtex II Pro FPGA is presented as a reference design XAPP683 Multi Rate HD SD SDI Transmitter Using Virtex Il Pro RocketlO Multi Gigabit Transceivers The SD SDI standard is widely used in broadcast studios and video production centers to transport standard definition SD digital video serially over video coax cable The HD SDI standard is similar but transports high definition HD digital video The SD SDI and HD SDI standards are similar enough that it is possible to implement interfaces for video equipment that support both standards through the same connector This application note describes how to use the RocketIO multi gigabit transceivers available in the Virtex II Pro family of FPGA devices to implement a transmitter that can support both SD SDI and HD SDI The flexibility ofthe RocketIO transceivers combined with the programmable logic of the Virtex II Pro devices makes it possible to implement multi rate SDI interfaces Since all Virtex II Pro devices have four or more RocketIO transceivers it is possible to implement multiple HD SDI a
143. ing 83 clock correction 76 CRC 87 SERDES alignment 70 synchronization logic 79 Ports defined CHBONDDONE 85 ENCHANSYNC 83 ENMCOMMAALIGN 71 ENPCOMMAALIGN 71 LOOPBACK 94 POWERDOWN 122 RXBUFSTATUS 92 RXCHARISCOMMA 74 RXCHARISK 66 RXCHECKINGCRC 91 RXCLKCORCNT 79 85 RXCOMMADET 74 RXCRCERR 91 RXDISPERR 67 RXLOSSOFSYNC 80 85 RXNOTINTABLE 67 RXPOLARITY 93 RXREALIGN 73 RXRECCLK 59 RXRUNDISP 66 TXBUFERR 92 TXBYPASSSBIOB 64 TXCHARDISPMODE 65 TXCHARDISPVAL 65 TXCHARISK 66 TXFORCECRCERR 91 TXINHIBIT 93 TXKERR 66 TXPOLARITY 93 TXRUNDISP 66 Ports table 25 Power Supply passive filtering 113 power conditioning 111 Power Supply Circuit Using Approved Regu lator figure 112 Pre emphasis available values 106 overview 106 scope screen captures 107 108 Q Qualified Linear Regulators table 112 R Random Jitter RJ 110 Receive Data Path 32 bit Alignment 95 Receiver Buffer 92 Reference Clock oscillator Pletronics for LVDS 121 Reset Power Down 60 RocketIO transceiver additional resources 18 analog design considerations 105 application notes 147 attributes table 30 basic architecture and capabilities 21 block diagram 23 130 channel bonding channel alignment 81 characterization reports 151 clocking 41 communications standards supported 21 CRC Cyclic Redundancy Check 86 default attribute values tables 35 design notes analog 122 digital 95 digital design considerations 41 modifiable
144. ion of drawings showing clocking schemes without using DCM Table B 1 Corrections in Valid Data Characters Table 3 4 Data added Corrections made to power regulator schematic Figure 3 7 Table 2 23 Data added corrected 12 12 02 1 6 1 Added clarifying text regarding trace length vs width 03 25 03 2 0 Reorganized existing content Added new content Added Appendix C Related Online Documents Added Index 06024 v2 4 August 25 2004 www xilinx com RocketlO Transceiver User Guide Date 06 12 03 Version 2 1 Revision Table 1 2 Added qualifying footnote to XAUI 10 Table 1 5 Corrected definition of RXRECCLK Section RocketIO Transceiver Instantiations in Chapter 1 added text briefly explaining what the Instantiation Wizard does Table 2 14 Changed numerics from exact values to rounded off approximations nearest 5 000 and added footnote calling attention to this Section Clocking in Chapter 2 added text recommending use of an IBUFGDS for reference clock input to FPGA fabric Section RXRECCLK in Chapter 2 Deleted references to SERDES 10B attribute and to divide by 10 RXRECCLK is always 1 20th the data rate Section FORMAT in Chapter 2 Corrected minimum data length for USER MODE to greater than 20 Table 3 5 Clarified the significance of the voltages shown in this table Section AC and DC Coup
145. ions of all primitives Table 1 5 GT CUSTOMO GT AURORA GT FIBRE CHANO GT ETHERNET GT INFINIBAND and GT XAUI Primitive Ports Port uo Pert Definition Size BREFCLK I 1 This high quality reference clock uses dedicated routing to improve jitter for serial speeds of 2 5 Gb s or greater See Table 2 2 page 42 for usage cases BREFCLK2 I 1 Alternative to BREFCLK be selected by REFCLKSEL CHBONDDONEO 1 Indicates a receiver has successfully completed channel bonding when asserted High CHBONDIO I 4 The channel bonding control that is used only by slaves which is driven by a transceiver s CHBONDO port CHBONDOO 4 Channel bonding control that passes channel bonding and clock correction control to other transceivers CONFIGENABLE I 1 Reconfiguration enable input unused Should be set to logic 0 CONFIGIN I 1 Data input for reconfiguring transceiver unused Should be set to logic 0 CONFIGOUT 1 Data output for configuration readback unused Should be left unconnected ENCHANSYNCO I 1 Comes from the core to the transceiver and enables the transceiver to perform channel bonding ENMCOMMAALIGN I 1 Selects realignment of incoming serial bitstream on minus comma High realigns serial bitstream byte boundary when minus comma is detected ENPCOMMAALIGN I 1 Selects realignment of incoming serial bitstream on plus comma High realigns serial bitstream byte
146. is Repetitive material that has been allow block block name omitted loci loc2 locn Online Document The following conventions are used in this document Convention Meaning or Use Example See the section Additional Cross reference link to a location Resources for details Blue text i in the current document Refer to Title Formats in Chapter 1 for details Red text Cross reference link to a location See Figure 2 5 in the Virtex IT in another document Handbook Go to http www xilinx com for Blue underlined text Hyperlink to a website URL the latest speed files www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 SC XILINX RocketIO Transceiver Overview Chapter 1 Basic Architecture and Capabilities The RocketIO transceiver is based on Mindspeed s SkyRail technology Figure 1 1 page 22 depicts an overall block diagram of the transceiver Up to 20 transceiver modules are available on a single Virtex II Pro FPGA depending on the part being used Table 1 1 shows the RocketIO cores available by device Table 1 1 Number of RocketlO Cores per Device Type Device RocketlO Cores Device RocketlO Cores XC2VP2 4 XC2VP40 0 or 12 XC2VP4 4 XC2VP50 0 or 16 XC2VP7 8 XC2VP70 16 or 20 XC2VP20 8 XC2VP100 0 or 20 XC2VP30 8 The transceiver module is designed to operate at any se
147. ising and falling edges of incoming data and derives a clock that is representative of the incoming data rate The derived clock RXRECCLK is presented to the FPGA fabric at 1 20th the incoming data rate whether full rate or half rate This clock is generated and remains locked as long as it remains within the specified component range This range is shown in Table 3 4 A sufficient number of transitions must be present in the data stream for CDR to work properly The CDR circuit is guaranteed to work with 8B 10B encoding Further CDR requires approximately 5 000 transitions upon power up to guarantee locking to the incoming data rate Once lock 15 achieved up to 75 missing transitions can be tolerated before lock to the incoming data stream is lost Table 3 4 CDR Parameters Parameter Min Typ Max Units Conditions Frequency Range Serial input diff 300 1 562 5 MHz RXP RXN TDCREF duty cycle 45 50 55 TRCLK TFCLK REFCLK rise and fall 400 1000 ps Between 20 and time see Virtex II Pro 80 voltage levels Data Sheet Module 3 TGJTT REFCLK total 40 ps 3 125 Gb s jitter 2 to jitter peak to peak 50 ps 2 5 Gb s 120 ps 1 06 Gb s TLOCK Clock recovery 10 us From system reset frequency acquisition Much less time is time needed to lock if loss of sync occurs Tpnase Which is described in Module 3 TUNLOCK cycles PLL length 75 non Requirement when transitions bypassing 8B 10
148. it primitives when implementing certain protocols Note that FPGA logic is not required for 1 byte and 2 byte configurations One such protocol is Fibre Channel Delimiters such as IDLES SOF and EOF are four bytes long and are assumed by the protocol logic to be aligned on a 32 bit boundary The Fibre Channel IDLE delimiter is four bytes long and is composed of characters K28 5 D21 4 D21 5 and D21 5 The comma 28 5 is transmitted in TXDATA 31 24 which the protocol logic expects to be received in RXDATA 31 24 Using Table B 1 page 137 and Table B 2 page 145 the IDLE delimiter can be translated into a hexadecimal value 0x BC95B5B5 that represents the 32 bit RXDATA word On the 32 bit RXDATA interface the received word is either 32 bit aligned or misaligned as shown in Table 2 24 In the table indicates a byte from a previous word of data Table 2 24 32 bit RXDATA Aligned versus Misaligned RXDATA RXDATA RXDATA RXDATA 31 24 23 16 15 8 7 0 32 bit aligned BC 95 B5 B5 CHARISCOMMA 1 0 0 0 32 bit misaligned BC 95 CHARISCOMMA 0 0 1 0 When RXDATA is 32 bit aligned the logic should pass RXDATA though to the protocol logic without modification properly aligned data flow is shown in Figure 2 29 TXDATA BC95B5B5 X FDB53737 X 45674893 BC95B5B5 A FDB53737 4 45674893 A BC95B5B5 FDB53737 45674893 ug024 33 091602 RXDATA ALIGNED DATA Fig
149. iver to recover the original data transmitted Obviously the pseudo random number generators at each end of the link must be in phase This is achieved using a known pattern of framing information which is actually transmitted unscrambled This 1s covered in more detail in 652 XAPP652 Word Alignment and SONET SDH Deframing This application note describes the logic to perform basic word alignment and deframing specifically for SONET SDH systems where data is being processed at 16 bits or 64 bits per clock cycle XAPP660 Partial Reconfiguration of RocketlO Pre emphasis and Differential Swing Control Attributes This application note describes a pre engineered solution for Virtex II Pro devices using the IBM PowerPC 405 core to perform a partial reconfiguration of the RocketIOTM multi gigabit transceivers MGTs pre emphasis and differential swing control attributes This solution is ideal for applications where these attributes must be modified to optimize the MGT signal transmission for various system environments while leaving the rest of the FPGA design unchanged The hardware and software elements of this solution can be easily integrated into any Virtex II Pro design The associated reference design supports the following devices XC2VP4 XC2VP7 XC2VP20 and XC2VP50 The design discussed in this document uses the PPC405 core device control register DCR bus interface to implement a simple solution with a minimum of FPGA resource
150. l e Gigabit Ethernet e Aurora Xilinx proprietary link layer protocol This document presents characterization data taken on Virtex II Pro devices to verify the performance of the MGTs with respect to these standards and the product specification Virtex Il Pro RocketlO MGT HSSDC2 Cable Characterization White Papers RocketIO multi gigabit transceivers MGTs in Virtex II Pro Platform FPGAs are capable of sending serial data at rates from 600 Mb s to 3 125 Gb s Many links taking advantage of this technology involve some length of cable through which these signals travel At these speeds cable has the effect of degrading the quality of the signals both distorting the waveforms and reducing their amplitude This report illustrates the effects that an industry standard cable the HSSDC2 has on waveforms transmitted from a Virtex II Pro device WP157 Usage Models for Multi Gigabit Serial Transceivers This document provides an overview of the various usage models for high speed point to point serial transceiver technology While not intending to represent all the applications of this technology it provides a basic categorization and description of some of the most common uses RocketlO Transceiver User Guide www xilinx com 151 UG024 v2 4 August 25 2004 A XILINX Appendix C Related Online Documents WP160 Emulating External SERDES Devices with Embedded RocketlO Transceivers The Virtex II Pro Platform FPGA provides an at
151. l attenuation in the link between transceivers It has five possible values of 400 500 600 700 and 800 mV These values represent the peak to peak amplitude of one component of the differential pair the full differential peak to peak amplitude is two times these values The PRE EMPHASIS attribute has four values 10 20 25 and 33 which are designated by 0 1 2 and 3 respectively Pre emphasis is discussed in greater detail in Chapter 3 Analog Design Considerations LOOPBACK To facilitate testing without the requirement to apply patterns or measure data at gigahertz rates two programmable loopback features are available One option serial loopback places the gigabit transceiver into a state where transmit data 1s directly fed back to the receiver An important point to note is that the feedback path is at the output pads of the transmitter This tests the entirety of the transmitter and receiver The second loopback path is a parallel path that checks only the digital circuitry When the parallel option is enabled the serial loopback path is disabled However the transmitter outputs remain active and data is transmitted over the serial link If TXINHIBIT is asserted TXN is forced High and TXP is forced Low until TXINHIBIT is de asserted LOOPBACK allows the user to send the data that is being transmitted directly to the receiver of the transceiver Table 2 23 shows the three loopback modes Table 2 23 LOOPBACK Modes
152. lator requirements when a device other than the LT1963 is used Section AC and DC Coupling in Chapter 3 Added footnote to Table 3 8 clarifying voltage compliance Figure 3 17 and section Epson EG 2121CA 2 5V LVPECL Outputs in Chapter 3 Added material specifying the optional use of an LVPECL buffer as an alternative to the LVDS buffer previously specified Table 4 2 Added pinouts for FG676 package XC2VP20 and XC2VP30 Table 5 Added BREFCLK parameters Toprrpwu and TBREFPWL Section Application Notes in Appendix C Included new Xilinx Application Notes XAPP648 XAPP669 and XAPP670 Various non technical edits and corrections RocketlO Transceiver User Guide www xilinx com UG024 v2 4 August 25 2004 Date 02 24 04 Version 2 3 Revision Table 2 3 page 43 Added FG676 row to BREFCLK Pin Numbers Figure 2 4 page 49 Added note above Figure 2 4 stating These local MGT clock input inverters shown and noted in Figure 2 4 are not included in the FOUR BYTE CLK templates Section RXRECCLK in Chapter 2 Added paragraph to section explaining how RXRECCLK changes monotonically and how the recovered bit clock is derived Section Data Path Latency in Chapter 2 Revised first sentence to read With the many configurations of the MGT both the transmit and receive data path latencies vary Section RXBUFSTATUS in Chapter 2 Revised the description of RXBUFSTATUS Figu
153. lices to use are in the CLB immediately to the left of the transceiver next to the bottom of the transceiver For the top side of the chip this is the fourth CLB row for the bottom side the bottom CLB row For example for the XC2VP7 here are the best slices to use for two of the transceivers e ForGT top edge the best slices are SLICE X15Y72 and SLICE X15Y73 For OT 0 0 bottom edge the best slices are SLICE X14Y0 and SLICE 4 This must be done for each MGT Figure 2 17 shows this recommendation GT std PCOMMA CONTROL ENPCOMMAALIGN RXRECCLK MCOMMA CONTROL ENMCOMMAALIGN UGO024 39 013103 Figure 2 17 Synchronizing Comma Align Signals to RXRECCLK RocketlO Transceiver User Guide www xilinx com 71 06024 v2 4 August 25 2004 XILINX Chapter 2 Digital Design Considerations Figure 2 18 and Figure 2 19 show floorplanner layouts for the two examples given above 3H FF EDGG EDFEDO HH GF 1 11 13 351 LEI 11 11 5 76 7765 665555 54 4 4 e ug024 43 031303 Figure 2 18 Top MGT Comma Control Flip Flop Ideal Locations WYAAAA YYAAAA A AA A 11DOAA 11CBCB 1 671111 561111 111145 8867 7766 5555 ugo24 44 031303 Figure 2 19 Bottom MGT Comma Control Flip Flop Ideal Locations 72 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 SERDES Alignment A UNN PCOMMA DETECT MCOMMA DETECT These two control attributes
154. ling in Chapter 3 Explanatory material added regarding V Rx V Try settings when AC or DC coupling is used Table 4 1 Corrected pinouts for FG256 and FG456 Table 4 3 Corrected pinouts for FF1517 XC2VP70 11 07 03 2 2 Section Clock Signals in Chapter 2 Added material that states the reference clock must be provided at all times any added jitter on the reference clock will be reflected on the RX TX I O Figure 2 3 Added a BUFG after the IBUFGDS reference clock buffer Section RX BUFFER USE in Chapter 2 Corrected erroneous USRCLK2 to RXUSRCLK RXUSRCLK2 Table 2 20 Added footnotes qualifying the maximum receive side latency parameters given in the table Section FIBRE CHAN in Chapter 2 Added specification for minimum data length 24 bytes not including CRC placeholder Section ETHERNET in Chapter 2 Added note indicating that Gigabit Ethernet 802 3 frame specifications must be adhered to Table 2 23 Corrected External to Internal loopback Improved explanation of Parallel Mode loopback Added Figure 2 28 Serial and Parallel Loopback Logic Section Clock and Data Recovery in Chapter 3 Corrected text to make clear that RXRECCLK is always 1 20th the incoming data rate and that CDR requires a minimum number of transitions to achieve and maintain a lock on the received data Section Voltage Regulation in Chapter 3 Added material defining voltage regu
155. ll when asserted High RXCHARISCOMMA O 1 2 4 Similar to RXCHARISK except that the data is a comma RXCHARISK 0 1 2 4 If 8B 10B decoding is enabled it indicates that the received data is a K character when asserted High Included in Byte mapping If 8B 10B decoding is bypassed it remains as the first bit received Bit of the 10 bit encoded data see Figure 2 14 page 68 RXCHECKINGCRC CRC status for the receiver Asserts High to indicate that the receiver has recognized the end of a data packet Only meaningful if RX USE TRUE RXCLKCORCNT Status that denotes occurrence of clock correction or channel bonding This status is synchronized on the incoming RXDATA See RXCLKCORCNT page 79 RXCOMMADET Signals that a comma has been detected in the data stream To assure signal is reliably brought out to the fabric for different data paths this signal may remain High for more than one USRCLK USRCLK2 cycle RXCRCERR Indicates if the CRC code is incorrect when asserted High Only meaningful if RX CRC USE TRUE RXDATA 8 16 32 Up to four bytes of decoded 8B 10B encoding or encoded 8B 10B bypassed receive data RXDISPERR 1 2 4 If 8B 10B encoding is enabled it indicates whether a disparity error has occurred on the serial line Included in Byte mapping scheme RXLOSSOFS YNC Status related to byte stream synchronization RX LOSS OF SYNC FSM
156. logic USRCLK M out std logic USRCLK2 M out std logic REFCLK out std logic LOCK out std logic 3 end ONE BYTE CLK architecture ONE BYTE CLK arch of ONE BYTE CLK is Components Declarations component BUFG port I in std logic O out std logic RocketlO Transceiver User Guide www xilinx com 53 06024 v2 4 August 25 2004 7 XILINX Chapter 2 Digital Design Considerations a end component component IBUFG port I in std logic O out std logic A end component component DCM port CLKIN CLKFB DSSEN PSINCDEC PSEN PSCLK RST CLKO CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CLKFX CLKFX180 LOCKED PSDONE STATUS end component in in in in in in in out out out out out out out out out out out out Signal Declarations signal signal signal signal signal begin GND USRCLK2 M std logic std logic std logic std logic std logic std logic std logic std logic std logic std logic std logic std logic std logic std logic std logic std logic std logic std logic std logic vector 7 downto 0 GND std logic CLKO W std logic CLK2X180 W std logic USRCLK2 M W std logic USRCLK M W std logic lt 0 USRCLK2 M W USRCLK lt USRCLK M W DCM Instantiation U DCM DCM port map CLKIN gt REFCLK CLKFB gt USRCLK M DSSEN gt GND PSINCDE
157. ls frequency of repetition of clock correction operations This attribute specifies the minimum number of RXUSRCLK cycles without clock correction that must occur between successive clock corrections For example if this attribute is 3 then at least three RXUSRCLK cycles without clock correction must occur before another clock correction sequence can occur If this attribute is 0 no limit is placed on how frequently clock correction can occur Example Elastic buffer is 25 full clock correction 1s needed and one sequence is repeated per clock correction IDLE is the defined clock correction sequence Data stream written into elastic buffer DO IDLE IDLE IDLE D1 D2 Data stream read out of elastic buffer CLK REPEAT WAIT 0 DO IDLE IDLE IDLE IDLE IDLE IDLE D1 D2 Data stream read out of elastic buffer CLK_COR REPEAT WAIT 1 DO IDLE IDLE IDLE IDLE IDLE D1 D2 The percent that the buffer is full together with the value of CLK_COR_REPEAT_WAIT determines how many times the clock correction sequence is repeated during each clock correction Synchronization Logic Overview 78 For some applications it is beneficial to know if incoming data is valid or not and if the MGT is synchronized on the data For applications using the 8B 10B encoding scheme the www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Synchronization Logic A UN
158. ls the raising of per byte flag RXCHARISCOMMA on plus comma DEC VALID COMMA ONLY TRUE FALSE controls the raising of RXCHARISCOMMA on an invalid comma FALSE Raise RXCHARISCOMMA 0011111xxx Gf DEC PCOMMA DETECT is TRUE and or on 1100000xxx if DEC MCOMMA DETECT is TRUE regardless of the settings of the xxx bits TRUE Raise RXCHARISCOMMA only on valid characters that are in the 8B 10B translation MCOMMA 10B VALUE This 10 bit vector defines minus comma for the purpose of raising RXCOMMADET and realigning the serial bit stream byte boundary This definition does not affect 8B 10B encoding or decoding Also see COMMA 10B MASK MCOMMA DETECT TRUE FALSE indicates whether to raise or not raise when minus comma is detected PCOMMA 10B VALUE This 10 bit vector defines plus comma for the purpose of raising and realigning the serial bit stream byte boundary This definition does not affect 8B 10B encoding or decoding Also see COMMA 10B MASK PCOMMA DETECT TRUE FALSE indicates whether to raise or not raise when plus comma is detected REF CLK V SEL 1 0 1 Selects BREFCLK BREFCLK2 for 2 5 Gb s or greater serial speeds 0 Selects REFCLK REFCLK2 for serial speeds under 2 5 Gb s RX BUFFER USE Always set to TRUE RX CRC USE TX CRC USE TRUE FALSE determines if CRC is used or not RX DATA WIDTH TX DATA WID
159. lue supporting the same standards as above CRC Generation RocketIO transceivers support a 32 bit invariant CRC fixed 32 bit polynomial shown below for Gigabit Ethernet Fibre Channel Infiniband and user defined modes 32 26 23 22 16 12 11 10 8 7 5 4 2 1 X tx x x x x x tx x tx x tx tx x 1 The CRC recognizes the SOP Start of Packet EOP End of Packet and other packet features to identify the beginning and end of data These SOP and EOP are defined by CRC_FORMAT for ETHERNET INFINIBAND and FIBRE CHAN and in these cases the user does not need to set CRC START OF PKT and CRC END OF PKT Where CRC FORMAT is USER MODE user defined CRC START OF PKT and CRC END OF PKT are used to define SOP and EOP 4 Bytes 00024 07 021102 Figure 2 29 CRC Packet Format The transmitter computes 4 byte CRC on the packet data between the SOP and EOP excluding the CRC placeholder bytes The transmitter inserts the computed CRC just before the EOP The transmitter modifies trailing Idles or EOP if necessary to generate correct running disparity for Gigabit Ethernet and Fibre Channel The receiver recomputes CRC and verifies it against the inserted CRC Figure 2 23 shows the packet format for CRC generation The empty boxes are only used in certain protocols Ethernet The user logic must create a four byte placeholder for the CRC by placing it in TXDATA Otherwise data is overwritten CRC Latency Enabling CRC increases the tran
160. lues refer to the data sheet There are many signals entering and exiting the RocketIO core Refer to Figure A 1 The model presented in this section treats the RocketIO core as a black box Propagation delays internal to the RocketIO core logic are ignored Signals are characterized with setup and hold times for inputs and with clock to valid output times for outputs There are five clocks associated with the RocketIO core but only three of these clocks RXUSRCLK RXUSRCLK2 and TXUSRCLK2 have I Os that are synchronous to them The following table gives a brief description of all of these clocks For an in depth discussion of clocking the RocketIO core refer to Chapter 2 Digital Design Considerations Table 1 RocketlO Clock Descriptions CLOCK SIGNAL DESCRIPTION REFCLK Main reference clock for RocketIO transceiver TXUSRCLK Clock used for writing the TX buffer Frequency locked to REFCLK TXUSRCLK2 Clocks transmission data and status and reconfiguration data between the transceiver and the FPGA core Relationship between TXUSRCLK2 and TXUSRCLK depends on width of transmission data path RXUSRCLK Clock used for reading the RX elastic buffer Clocks CHBONDI and CHBONO into and out of the transceiver Typically the same as TXUSRCLK RXUSRCLK2 Clocks receiver data and status between the transceiver and the FPGA core Typically the same as TXUSRCLK2 Relationship between RXUSRCLK2 and RXUSRCLK depends on
161. meters Parameter Min Typ Max Units Conditions Vout Serial output differential 800 1600 mV Output differential voltage peak to peak TXP TXN is programmable Output termination voltage 1 8 2 625 V supply RocketlO Transceiver User Guide www xilinx com 105 06024 v2 4 August 25 2004 XILINX Chapter 3 Analog Design Considerations Table 3 1 Differential Transmitter Parameters Parameter Min Typ Max Units Conditions mode 1 1 1 5 V voltage range no transmission line connected VTCM Common mode output 1 1 2 0 V The common mode depends voltage range transmission on coupling DC or AC line connected VTTX VTRX and differential swing Spice simulation gives the exact common mode voltage for any given system Viskgw Differential output skew 15 ps Pre emphasis Techniques 106 In pre emphasis the initial differential voltage swing is boosted to create a stronger rising or falling waveform This method compensates for high frequency loss in the transmission media that would otherwise limit the magnitude of this waveform The effects of pre emphasis are shown in four Scope screen captures Figure 3 2 through Figure 3 5 on the pages following The STRONG notation in Figure 3 3 is used to show that the waveform is greater in voltage magnitude at this point than the LOGIC or normal level i e no pr
162. must be placed within 1 cm of the pins they are connected to Figure 3 9 Figure 3 10 and Figure 3 11 show example layouts of the power filtering network for four transceivers in one case in a package with internal capacitors in another case in a package with external capacitors The device in Figure 3 9 is in an FF672 package which has eight transceivers total four on the top edge rows A B and four on the bottom edge rows AE AF This device contains internal capacitors so it is only necessary to have ferrite beads on the PCB Figure 3 9 shows the bottom PCB layer with lands for ferrite beads of the VTTX VTRX AVCCAUXTX and AVCCAUXRX supplies The ferrite beads are mounted at the sixteen L n locations v 1 1 _ RI l Figure 3 9 Example Power Filtering PCB Layout for Four MGTs in Device with Internal Capacitors Bottom Layer The device in Figure 3 10 and Figure 3 11 is an FG456 package which also has eight transceivers total four on the top edge and four on the bottom edge This device does not have capacitors inside 114 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 PCB Design Requirements A XILINX the package so it is necessary to have both capacitors and ferrite beads mounted on the PCB Figure 3 10 shows the top PCB layer with lands for the capacitors and ferrite beads of the VTTX and VTRX supplies Figure 3 11 shows the bottom PCB layer with lands
163. n Similarly if RXUSRCLK is slower than RXRECCLK the buffer fills up over time The clock correction logic corrects for this by incrementing the read pointer to skip over a removable byte sequence that need not appear in the final FPGA core byte stream This is shown in the bottom buffer Figure 2 20 where the solid read pointer increments to the value represented by the dashed pointer This accelerates the emptying of the buffer preventing its overflow The transceiver design skips a single byte sequence when necessary to partially empty a buffer If attribute RocketlO Transceiver User Guide www xilinx com 75 06024 v2 4 August 25 2004 XILINX Chapter 2 Digital Design Considerations CLK COR REPEAT WAIT is 0 the transceiver can also skip four consecutive removable byte sequences in one step to further empty the buffer when necessary These operations require the clock correction logic to recognize a byte sequence that can be freely repeated or omitted in the incoming data stream This sequence is generally an IDLE sequence or other sequence comprised of special values that occur in the gaps separating packets of meaningful data These gaps are required to occur sufficiently often to facilitate the timely execution of clock correction The clock correction logic has the ability to remove up to four IDLE sequences during a clock correction How many IDLEs are removed depends on several factors including how many IDLEs are
164. nd SDI SDI interfaces in a single FPGA XAPP684 Multi Rate HD SD SDI Receiver Using Virtex Il Pro RocketlO Multi Gigabit Transceivers The SD SDI standard is widely used in broadcast studios and video production centers to transport standard definition SD digital video serially over video coax cable The HD SDI standard is similar but transports high definition HD digital video The SD SDI and HD SDI standards are similar enough that it is possible to implement interfaces for video equipment that support both standards through the same connector This application note describes how to use the RocketIO multi gigabit transceivers available in the Virtex II Pro family of FPGA devices to implement a receiver that can support both SD SDI and HD SDI The flexibility ofthe RocketIO transceivers combined with the programmable logic of the Virtex II Pro devices makes it possible to implement multi rate SDI interfaces XAPP687 64B 66B Encoder Decoder This application note describes the encoding and decoding blocks of the 64B 66B encoding scheme This application allows designs to use the RocketlO transceiver of the Virtex II Pro device or an external SerDes with either Virtex II or Virtex II Pro devices XAPP763 Local Clocking for MGT RXRECCLK in Virtex II Pro Devices 150 This application note describes the local clocking resources available in the Virtex II Pro architecture for the RXRECCLK of the 3 125 Gb s RocketIO multi gigabit
165. niband CRC must be implemented entirely in the FPGA fabric There are also two Infiniband Architecture IBA packets a local and a global Both of these IBA packets are shown in Figure 2 26 Local IBA Packet R1 Ro Ra Variant RC EOP Payload Global IBA sop LRH GRH pm Packet Ri Ro Variant CRC EOP Payload 06024 14 020802 Figure 2 26 nfiniband Mode The CRC is calculated with certain bits masked in LRH and GRH depending on whether the packet is local or global The size of these headers is shown in Table 2 21 Table 2 21 Global and Local Headers Packet Description Size LRH Local Routing Header 8 Bytes GRH Global Routing Header 40 Bytes BTH IBA Transport Header 12 Bytes RocketlO Transceiver User Guide www xilinx com 89 06024 v2 4 August 25 2004 XILINX Chapter 2 Digital Design Considerations The checks the LNH Link Next Header of the LRH LRH 15 shown in Figure 2 27 along with the bits the CRC uses to evaluate the next packet 8 Ba a Bs Bo ev B11 Bin 1 1 IBA Global Packet 1 0 IBA Local Packet 0 1 Raw Packet CRC does not insert remainder 0 0 Raw Packet CRC does not insert remainder 00024 15 020802 2 27 Local Route Header Note Minimum data length for this mode is defined by the protocol requirements Because of the complexity of the CRC algorithms and implementations especi
166. nly modifiable in the CUSTOM primitive CHAN BOND LIMIT Integer 1 31 that defines maximum number of bytes a slave receiver can read following a channel bonding sequence and still successfully align to that sequence CHAN BOND MODE STRING OFF MASTER SLAVE 1 HOP SLAVE 2 HOPS OFF No channel bonding involving this transceiver MASTER This transceiver is master for channel bonding Its CHBONDO port directly drives CHBONDI ports on one or more SLAVE 1 HOP transceivers SLAVE 1 This transceiver is a slave for channel bonding SLAVE 1 HOP s CHBONDI is directly driven by a MASTER transceiver CHBONDO port SLAVE 1 HOP s CHBONDO port can directly drive CHBONDI ports on one or more SLAVE 2 HOPS transceivers SLAVE 2 HOPS This transceiver is a slave for channel bonding SLAVE 2 HOPS CHBONDI is directly driven by a SLAVE 1 HOP CHBONDO port 28 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Primitive Attributes XILINX Table 1 6 RocketlO Transceiver Attributes Continued Attribute CHAN BOND OFFSET Description Integer 0 15 that defines offset in bytes from channel bonding sequence for realignment It specifies the first elastic buffer read address that all channel bonded transceivers have immediately after channel bonding CHAN BOND WAIT specifies the number of bytes that the master transceiver passes to RXDATA starting with the channel bonding seq
167. nterminated TXP TXN to the RXP RXN of another instantiated transceiver allowing its receiver inputs to terminate the transmitter outputs TXP TXN TXDATA TX PCS TX SERIALIZER PARALLEL LOOPBACK 01 SERIAL LOOPBACK 10 RXDATA RX PCS RX DESERIALIZER RXP RXN 00024 25 110503 Figure 2 28 Serial and Parallel Loopback Logic Other Important Design Notes Receive Data Path 32 bit Alignment 94 The RocketIO transceiver uses the attribute ALIGN COMMA MSB to align protocol delimiters with the use of comma characters special K characters K28 5 K28 1 and K28 7 for most protocols Setting ALIGN COMMA MSB to TRUE FALSE determines where the comma characters appear on the RXDATA bus When ALIGN COMMA MSB issetto FALSE the comma can appear in any byte lane of RXDATA 1n the 2 and 4 byte primitives When www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 XILINX Other Important Design Notes ALIGN COMMA MSB is set to TRUE the comma appears in RXDATA 15 8 for the 2 byte primitives and in either RXDATA 15 8 or RXDATA 31 24 for the 4 byte primitives See ALIGN COMMA page 70 In the case of a 4 byte primitive the transceiver sets comma alignment with respect to its 2 byte internal data path but it does not constrain the comma to appear only in RXDATA 31 24 Logic must be designed in the FPGA fabric to handle comma alignment for the 32 b
168. o have come through the comma detection circuit that is upon an asserted RXREALIGN or RXCOMMADET always 9 posedge usrclk2 begin if rxreset begin wait to sync lt 4 b1111 count lt 1 b0 end else if rxrealign begin wait to sync lt 4 b1111 count lt 1 61 end else begin if count amp amp wait to sync 4 0000 wait to sync wait to sync 4 b0001 if rxcommadet count lt 1 b1 end end This process maintains output sync which indicates when outgoing aligned data should be properly aligned with the comma in aligned data 31 24 Output aligned data is considered to be in sync when a comma is seen on rxdata as indicated by rxchariscomma3 or 1 after the counter wait to sync has reached 0 indicating that commas seen by the comma detection circuit have had time to propagate to aligned data after initialization of the elastic buffer always posedge usrclk2 begin if rxreset rxrealign Sync 1 b0 else if wait to sync 4 b0000 amp rxchariscomma3 rxchariscommal Sync lt 1 bl end This process generates aligned data with commas aligned in 31 24 assuming that incoming commas are aligned to 31 24 or 15 8 98 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Other Important Design Notes A UNN Here you could add code to use ENPCOMMAALIGN and
169. ock input invert ers acceptable skew 00024 03 112202 Figure 2 4 Four Byte Clock VHDL Template Module FOUR BYTE CLK Description VHDL submodule RocketlO Transceiver User Guide www xilinx com 49 06024 v2 4 August 25 2004 3 XILINX Chapter 2 Digital Design Considerations DCM for 4 byte GT Device Virtex II Pro Family library IEEE use IEEE std logic 1164 all pragma translate off library UNISIM use UNISIM VCOMPONENTS ALL pragma translate on entity FOUR BYTE CLK is port REFCLKIN in std logic RST in std logic USRCLK M out std logic USRCLK2 M out std logic REFCLK out std logic LOCK out std logic end FOUR BYTE CLK architecture FOUR BYTE CLK arch of Components Declarations component BUFG port in std logic O out std logic end component component IBUFG port I in std logic O out std logic end component component DCM port CLKIN in std logic CLKFB in std logic DSSEN in std logic PSINCDEC in std logic PSEN in std logic PSCLK in std logic RST in std logic CLKO out std logic CLK90 out std logic CLK180 out std logic CLK270 out std logic CLK2X out std logic CLK2X180 out std logic CLKDV out std logic CLKFX out std logic CLKFX180 out std logic LOCKED out std logic FOUR BYTE CLK is 50 www xilinx com RocketlO Transceiver User
170. on VHDL submodule os DCM for 2 byte GT Device Virtex II Pro Family library IEEE use IEEE std logic 1164 11 pragma translate off library UNISIM use UNISIM VCOMPONENTS ALL pragma translate on entity TWO BYTE CLK is port REFCLKIN in std logic RST in std logic USRCLK M out std logic REFCLK out std logic LOCK out std logic Le end TWO BYTE CLK architecture TWO BYTE CLK arch of TWO BYTE CLK is Components Declarations component BUFG port I in std logic O out std logic end component component IBUFG port I in std logic 46 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Clocking XILINX O out std logic end component component DCM port CLKIN in std logic CLKFB in std logic DSSEN in std logic PSINCDEC in std logic PSEN in std logic PSCLK in std logic RST in std logic CLKO out std logic CLK90 out std logic CLK180 out std logic CLK270 out std logic CLK2X out std logic CLK2X180 out std logic CLKDV out std logic CLKFX out std_logic CLKFX180 out std logic LOCKED out std logic PSDONE out std logic STATUS out E end component 1 Signal Declarations signal GND signal CLKO W begin std std GND 107 Instantiation std logic vector 7 downto 0 logic logic U DCM DCM port map CLKIN gt REFCLK CLKFB gt USRCLK M DSSEN g
171. on the width of the parallel data The most significant byte is always sent first regardless of the whether 1 byte 2 byte or 4 byte paths are used The least significant byte is always last Figure 2 16 shows a case when the serial data corresponds to each byte of the parallel data TXDATA 31 24 is serialized and sent out first followed by TXDATA 23 16 TXDATA 15 8 and finally TXDATA 7 0 The 2 byte path transmits TXDATA 15 8 and then TXDATA 7 0 H3 A3 Ho A2 H4 Au Ho Ao TXDATA 31 24 TXDATA 23 16 TXDATA 15 8 TXDATA 7 0 8B 10B 83 j3 a1 j1 ao jo LSB3 LSBo LSB LSBo 18t Sent 2nd Sent 3rd Sent 4th Sent Encoded Encoded Encoded Encoded 0024 11 020802 Figure 2 16 4 Byte Serial Structure HDL Code Examples Transceiver Bypassing of 8B 10B Encoding 8B 10B encoding can be bypassed by the transceiver The TXBYPASSS8BIOB is set to 1111 the RXDECODE attribute is set to FALSE to create the extra two bits needed for a 10 bit data bus and TXCHARDISPMODE TXCHARDISPVAL RXCHARISK and RXRUNDISP are added to the 8 bit data bus Please use the Architecture Wizard to create instantiation templates This wizard creates code and instantiation templates that define the attributes for a specific application RocketlO Transceiver User Guide www xilinx com 69 06024 v2 4 August 25 2004 A XILINX Chapter 2 Digital Design Considerations SERDES Alignment Overview Serializer The multi gigabit tr
172. ovided at all times This is especially important at the end of configuration when the PMA portion of the MGT requires a reference clock in order to properly initialize If a reference clock is not available at this point the user should toggle the POWERDOWN pin when the reference clock becomes available to ensure the PMA is properly initialized The reference clock also clocks a Digital Clock Manager DCM or a BUFG to generate all of the other clocks for the MGT Never run a reference clock through a DCM since unwanted jitter will be introduced Any additional jitter on the reference clock will be transferred to the transceiver s RX and TX serial I O It is recommended that all reference clock sources into the FPGA be LVDS or LVPECL IBUFGDS The DCI or DT attributes of LVDS are optional Refer to the Virtex II Pro Platform FPGA User Guide Chapter 3 Design Considerations for a complete listing and discussion of IBUFGDS and other available I O primitives Also see section Reference Clock in Chapter 3 of this Guide Typically TXUSRCLK RXUSRCLK and TXUSRCLK2 RXUSRCLK2 The transceiver uses one or two clocks generated by the DCM As an example USRCLK and USRCLK2 clocks run at the same speed if the 2 byte data path 15 used The USRCLK must always be frequency locked to the reference clock of the RocketIO transceiver when SERDES_10B FALSE full rate operation Note The reference clock must be at least 50 MHz for full rate operation
173. pairs are forced to be a constant 1 0 1 0 TXKERR O 1 2 4 If 8B 10B encoding is enabled this signal indicates High when the K character to be transmitted is not a valid K character Bits correspond to the byte mapping scheme TXN 1 Transmit differential port FPGA external TXP 1 Transmit differential port FPGA external TXPOLARITY I 1 Specifies whether or not to invert the final transmitter output Able to reverse the polarity on the TXN and TXP lines Deasserted sets regular polarity Asserted reverses polarity TXRESET I 1 Synchronous TX system reset that recenters the transmit elastic buffer It also resets 8B 10B encoder and other internal transmission registers It does not reset the transmission PLL TXRUNDISPO O L2 4 Signalsthe running disparity after this byte is encoded Low indicates negative disparity High indicates positive disparity TXUSRCLK I 1 Clock output from DCM or a BUFG that is clocked with a reference clock This clock is used for writing the TX buffer and 15 frequency locked to the reference clock TXUSRCLK2 I 1 Clock output from DCM that clocks transmission data and status and reconfiguration data between the transceiver an the FPGA core The ratio between TXUSRCLK and TXUSRCLK2 depends on the width of TXDATA Notes 1 The GT CUSTOM ports are always the maximum port size 2 GT FIBRE CHAN and GT ETHERNET ports do not have the three CHBOND or EN
174. primitives 35 number of MGTs per device type 21 PCB design requirements 111 ports table 25 powering 122 related online documents 147 reset power down 60 simulation and implementation 123 valid control characters K characters 145 valid data characters 137 white papers 152 Routing Serial Traces 117 SERDES Alignment overview 70 ports and attributes 70 Serial I O Description 105 Serializer 70 Setup Hold Times of Inputs Relative to Clock 131 Simulation Models 123 SmartModels 123 Synchronization Logic overview 79 ports and attributes 79 T CHBONDI 85 generating 121 Termination Voltage 113 CHBONDO 85 oscillator Epson for LVPECL 121 Timing Parameters 131 154 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 XILINX Total Jitter DJ RJ 109 Transmitter and Elastic Receiver Buffers 91 Transmitter Buffer FIFO 91 U User Guide conventions online references 20 port and attribute names 19 typographical 19 V Vitesse Disparity Example 67 Voltage Regulator Selection and Use 111 RocketlO Transceiver User Guide www xilinx com 155 06024 v2 4 August 25 2004 7 XILINX 156 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004
175. purpose A FIFO depth of four permits reliable operation with simple detection of overflow or underflow which might occur if the clocks are not frequency locked Overflow or underflow conditions are detected and signaled at the interface Receiver Buffer The receiver buffer is required for two reasons e accommodate the slight difference in frequency between the recovered clock RKXRECCLK and the internal FPGA core clock RXUSRCLK clock correction e allow realignment of the input stream to ensure proper alignment of data being read through multiple transceivers channel bonding The receiver uses an elastic buffer where elastic refers to the ability to modify the read pointer for clock correction and channel bonding Ports and Attributes TXBUFERR When High this port indicates that a transmit buffer underflow or overflow has occurred Once set High TXRESET must be asserted to clear this bit TX_BUFFER_USE This attribute allows the user to bypass the transmit buffer A value of FALSE bypasses the buffer while a TRUE keeps the buffer in the data path This attribute should always be set to TRUE RXBUFSTATUS This 2 bit port indicates the status of the receiver elastic buffer RXBUFSTATUS 1 High indicates if an overflow underflow error has occurred Once set High the assertion of RXRESET or RocketlO Transceiver User Guide www xilinx com 91 06024 v2 4 August 25 2004 3 XILINX Chapter 2 Digital D
176. put delays 131 code examples I byte clock 53 2 byte clock 46 4 byte clock 49 half rate clocking scheme 57 multiplexed clocking scheme with DCM 58 without DCM 58 Control Characters valid table 145 Coupling AC and DC 119 CRC Cyclic Redundancy Check 86 generation 86 latency 87 operation 86 ports and attributes 87 support limitations 91 D Data Characters valid table 137 Data Path Latency 59 Deserializer 70 Deterministic Jitter DJ 110 Differential Receiver 109 Differential Trace Design 118 H Half Rate Clocking Scheme 57 HDL Code Examples Verilog I byte clock 55 2 byte clock 48 32 bit alignment design 97 4 byte clock 52 VHDL 1 byte clock 53 2 byte clock 46 32 bit alignment design 100 RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 153 XILINX 4 byte clock 50 High Speed Serial Trace Design 117 HSPICE 123 Implementation Tools 123 J Jitter and BREFCLK 43 and use of DCM with REFCLK 41 deterministic and random defined 109 parameters 109 110 PCB trace length mismatch 117 K K Characters valid table 145 L Latency Data Path 59 M MGT Package Pins 125 Miscellaneous Signals 92 Modifiable Primitives table 35 Multiplexed Clocking Scheme with DCM 58 without DCM 58 P Par 123 Passive Filtering 113 PCB Design Requirements 111 Ports amp Attributes by function 8B 10B encoding decoding 64 buffers fabric interface 92 channel bond
177. r causing a false channel bonding sequence to occur this port is usually de asserted once a group of channels have been successfully aligned CHAN BOND ONE SHOT As with ENCHANSYNC many applications will require that the channels be aligned only once CHAN BOND ONE SHOT TRUE allows the Master to initiate a channel bonding only once This remains true even if more channel bonding sequences are received The channels may be aligned again if RXRESET is asserted and then deasserted and ENCHANSYNC is deasserted and then reasserted CHAN BOND ONE SHOT may be set to FALSE when very few channel bonding sequences appear in the data stream For Slave instantiations this attribute should always be set to FALSE See Table 2 19 When the channel bonding sequence appears frequently in the data stream however it is recommended that this attribute be set to TRUE in order to prevent the RX buffer from over or underflowing CHAN BOND SEQ xx CHAN BOND GEO LEN CHAN BOND SEQ 2 USE The channel bonding sequence CBS is similar in format to the clock correction sequence The CBS is set to the appropriate sequence for the primitives supporting channel bonding GT CUSTOM is the only primitive allowing modification to the sequence These sequences are comprised of one or two sequences of length up to 4 bytes each as set by CHAN BOND SEQ LEN and CHAN BOND SEQ 2 USE RocketlO Transceiver User Guide www xilinx com 83 06024 v2 4 August 25 2004
178. re 3 1 page 105 Replaced old Figure 3 1 page 101 with new Figure 3 1 showing Differential Amplifier Figure 3 6 page 109 Added new Figure 3 6 page 105 showing MGT Receiver Table 3 4 page 110 Added text to CDR Parameters TLOCK parameter in Conditions column and edited Note 3 Section Voltage Regulation in Chapter 3 Added Linear Technology part numbers LT1963A LT1964 Section Passive Filtering in Chapter 3 Added new cap rules for RocketIO transceiver Figure 3 8 page 113 Replaced old Figure 3 8 with new figure showing Power Filtering Network on Devices with Internal and External Capacitors Table 3 7 page 114 Added Device and Package combinations table Figure 3 9 page 115 Added new Figure 3 10 page 110 showing Example Power Filtering PCB Layout for Four MGTs in Device with Internal Capacitors Bottom Layer Modified the text describing Figure 3 9 page 115 Figure 3 10 page 116 Replaced old Figure 3 10 with new figure showing Example Power Filtering PCB Layout for Four MGTs in Device with External Capacitors Top Layer Removed the text describing old Figure 3 10 Figure 3 11 page 117 Replaced old Figure 3 11 with new figure showing Example Power Filtering PCB Layout for Four MGTs in Device with External Capacitors Bottom Layer Removed the text describing old Figure 3 11 Table 3 8 page 120 Added and voltages for different coupling environments 0
179. realigned and RXREALIGN is asserted The realignment indicator is a distinct output The transceiver continuously monitors the data for the presence of the 10 bit character s Upon each occurrence of the 10 bit character the data is checked for word alignment If comma detect is disabled the data is not aligned to any particular pattern The programmable option allows a user to align data on plus comma minus comma both or a unique user defined and programmed sequence The electrical polarity of RXP and RXN can be interchanged through the RXPOLARITY port This can be useful in the event that printed circuit board traces have been reversed Ports and Attributes Comma definition can be accomplished using the attributes discussed below This method of definition makes the MGT extremely flexible in implementing different protocols ALIGN_COMMA_MSB This attribute determines where the commas will reside in the parallel received data The comma indicates to the deserializer how to parallelize the data However with the multiple data path widths available the PCS portion must determine where to place the comma in the parallel data bytes When ALIGN COMMA MSB is FALSE the PCS may place the comma in any of the RXDATA bytes In the 1 byte mode of course there is only one location in which the comma can be placed In the 2 byte and 4 byte paths some uncertainty exists as to which byte will contain the comma as shown in Table 2 12 When ALIGN C
180. received and whether CLK amp COR KEEP IDLE is TRUE or FALSE For example if three IDLEs are received and COR KEEP IDLE is set to TRUE at least one IDLE sequence must remain after clock correction has been completed This limits the clock correction logic to remove only two of the three IDLE sequences If CLK COR KEEP IDLE is FALSE then all three IDLEs can be removed Table 2 14 illustrates the relationship between the number of IDLE sequences removed the inherent stability of REFCLK and the number of bytes allowed between clock correction sequences Table 2 14 Data Bytes Allowed Between Clock Corrections as a Function of REFCLK Stability and IDLE Sequences Removed Bytes Allowed Between Clock Correction Sequences REFCLK Remove1IDLE 2 Remove 2IDLE Remove 3 IDLE Remove 4 IDLE Stability Sequence Sequences Sequences Sequences 100 ppm 5 000 10 000 15 000 20 000 50 ppm 10 000 20 000 30 000 40 000 20 ppm 25 000 50 000 75 000 100 000 Notes 1 All numbers are approximate 2 IDLE the defined clock correction sequence Ports and Attributes 76 CLK CORRECT USE This attribute controls whether the PCS will repeat skip the clock correction sequences CCS from the elastic buffer to compensate for differences between the clock recovered from serial data and the reference clocks When this attribute is set to TRUE the clock correction is enabled If set to FALSE clock correction is disa
181. rial bit rate in the range of 600 Mb s to 3 125 Gb s per channel including the specific bit rates used by the communications standards listed in Table 1 2 The serial bit rate need not be configured in the transceiver as the operating frequency is implied by the received data the reference clock applied and the SERDES 10B attribute see Table 1 3 Table 1 2 Communications Standards Supported by RocketlO Transceiver iid Fibre Channel 1 2 12 Gbit Ethernet 1 1 25 XAUI 10 Gbit Ethernet 4 3 125 XAUI 10 Gbit Fibre Channel 2 4 3 1875 Infiniband 1 4 12 2 5 Aurora Xilinx protocol 1 2 3 4 0 600 3 125 Custom Mode 1 2 3 4 0 600 3 125 Notes 1 One channel is considered to be one transceiver 2 Supported with the GT CUSTOM primitive Certain attributes must be modified to comply with the XAUI 10GFC specifications including but not limited to COR SEQ and CHAN BOND SEQ 3 Bitrate is possible with the following topology specification maximum 6 FR4 and one Molex 74441 connector RocketlO Transceiver User Guide www xilinx com 21 UG024 v2 4 August 25 2004 A XILINX Chapter 1 RocketlO Transceiver Overview Table 1 3 Serial Baud Rates and the SERDES 10B Attribute SERDES 10B Serial Baud Rate FALSE 1 0 Gb s 3 125 Gb s TRUE 600 Mb s 1 0 Gb s PACKAGE PINS MULTI GIGABIT TRANSCEIVER CORE FPGA FABRIC RX
182. rmation The power supply circuit specified by the manufacturer must be used The circuit shown in Figure 3 17 must be used to interface the oscillator s LVPECL outputs to the LVDS or LVPECL inputs of the transceiver reference clock Alternatively LVDS 25 DT input buffers may be used to terminate the signals on chip as shown in Figure 3 18 EG2121CA 2 5V PECL 1000 777 06024 025a 110603 Figure 3 17 LVPECL Reference Clock Oscillator Interface EG2121CA 2 5V PECL 1000 777 06024 025c 071504 Figure 3 18 LVPECL Reference Clock Oscillator Interface On Chip Termination Pletronics LV1145B LVDS Outputs See the Pletronics website for detailed information The circuit shown in Figure 3 19 must be used to interface the oscillator s LVDS outputs to the LVDS inputs of the transceiver reference clock Alternatively the LVDS 25 DCI input buffer may be used to terminate the signals on chip as shown in Figure 3 20 LV1145B 2 5V LVDS 06024 025b 050102 Figure 3 19 LVDS Reference Clock Oscillator Interface LV1145B 2 5V LVDS 06024 0254 071504 Figure 3 20 LVDS Reference Clock Oscillator Interface On Chip Termination 120 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Other Important Design Notes A UNN Other Important Design Notes Powering the RocketlO Transceivers IMPORTANT RocketIO transceivers in the FPGA whether instantiated in the
183. rolled by complex logic but are more simply handled by a microprocessor in this case the IBM amp PowerPC 405 PPC405 processors embedded in the Virtex II ProTM FPGA This reference system is an example of a high speed serial link packet processing engine implemented in Virtex II Pro FPGAs The Embedded Development Kit EDK is used exclusively in the design and implementation of both hardware and software in this reference system This reference design has been verified on the Memec Design Virtex II Pro P4 Development Board Instructions are included to allow the reader to reproduce the design on this board XAPP670 Minimizing Receiver Elastic Buffer Delay in the Virtex Il Pro RocketlO Transceiver This application note describes a design that reduces latency through the receive elastic buffer of the Virtex II Pro RocketIO transceiver This note is only applicable for designs that do not use the clock correction or channel bonding features ofthe RocketIO transceiver These operations can still be done in the fabric if needed XAPP680 HD SDI Transmitter Using Virtex Il Pro RocketlO Multi Gigabit Transceivers The High Definition Serial Digital Interface HD SDI standard describes how to transport high definition HD digital video serially over video coax cable HD SDI is used to connect HD video equipment in broadcast studios and video production centers It is an evolution of the popular SDI standard that is widely used to transpo
184. rom it by up to 400 ppm DCM 0 1 REFCLKSEL IBUFGDS BUFG REFCLK TXUSRCLK TXUSRCLK2 RXUSRCLK RXUSRCLK2 RXRECCLK 06024 38 112202 Figure 2 11 Using to Generate RXUSRCLK RXUSRCLK2 Note Bypassing the RX elastic buffer is not recommended as the skew created by the DCM and routing to global clock resources is uncertain and may cause unreliable performance Clock Dependency signals used by the FPGA fabric to interact between user logic and the transceiver depend on an edge of USRCLK2 These signals all have setup and hold times with respect to this clock For specific timing values see Module 3 of the Virtex II Pro data sheet The timing relationships are further discussed and illustrated in Appendix A Transceiver Timing Model Data Path Latency With the many configurations of the MGT the both transmit and receive data path latencies vary Below are several tables that provide approximate latencies for common configurations Table 2 6 Latency through Various Transmitter Components Processes Component Process Latency 1 Byte Data Path 2 Byte Data Path 4 Byte Data Path TX Fabric GT Interface 2 5 TXUSRCLK2 cycles I TXUSRCLK2 cycle 1 25 TXUSRCLK2 cycles 1 25 TXUSRCLK cycles TXUSRCLK cycle 2 5 TXUSRCLK cycles included 7 TXUSRCLK cycles TX CRC bypassed TXUSRCLK cycle included TXUSRCLK cycle 8B 10B Encoder bypa
185. rs Top Bottom Package BREFCLK BREFCLK2 BREFCLK BREFCLK2 Pin Number Pin Number Pin Number Pin Number FF896 F16 G16 G15 F15 AHI6 AJ16 5 15 FF1152 H18 J18 J17 H17 AKI8 AL18 ALI7 AK17 FF1148 N A N A N A N A FF1517 E20 D20 J20 K20 AR20 AT20 AL20 AK20 FF1704 G22 F22 F21 G21 AU22 AT22 AT21 AU21 FF1696 N A N A N A N A www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Clocking XILINX Clock Ratio USRCLK2 clocks the data buffers The ability to send receive parallel data to from the transceiver at three different widths requires the user to change the frequency of USRCLK2 This creates a frequency ratio between USRCLK and USRCLK2 The falling edges of the clocks must align Table 2 4 shows the ratios for each of the three data widths Table 2 4 Data Width Clock Ratios Data Width Frequency Ratio of USRCLK USRCLK2 1 byte 120 2 byte 1 1 4 byte 210 Notes 1 Each edge of the slower clock must align with the falling edge of the faster clock Digital Clock Manager DCM Examples With at least three different clocking schemes possible on the transceiver a DCM is the best way to create these schemes Table 2 5 shows typical DCM connections for several transceiver clocks REFCLK is the input reference clock for the DCM The other clocks are generated by the DCM The DCM establishes a desired phase relationship between TXUSRCLK TXUSR
186. rt standard definition SD digital video in the broadcast industry The flexibility of RocketIOTM multi gigabit transceivers available in the Virtex II ProTM family devices combined with the programmable logic of Virtex II Pro FPGAs makes it possible to implement HD SDI interfaces Because every Virtex II Pro FPGA has multiple RocketIO transceivers it is possible to integrate multiple HD SDI interfaces into one Virtex II Pro device along with other video processing functions This application note describes the electrical specifications for HD SDI transmitters and the HD SDI data format It also presents several implementation examples and reference designs for an HD SDI transmitter implemented using the Virtex II Pro FPGA 681 HD SDI Receiver Using Virtex Il Pro RocketlO Multi Gigabit Transceivers The High Definition Serial Digital Interface HD SDI standard describes how to transport high definition HD digital video serially over video coax cable HD SDI is used to connect HD video equipment in broadcast studios and video production centers It is an evolution of the popular SDI RocketlO Transceiver User Guide www xilinx com 149 UG024 v2 4 August 25 2004 7 XILINX Appendix C Related Online Documents standard that is widely used to transport standard definition SD digital video in the broadcast industry The flexibility of the RocketIOTM multi gigabit transceivers available in the Virtex II Pro family dev
187. s XAPP661 RocketlO Transceiver Bit Error Rate Tester This application note describes the implementation of a RocketIO transceiver bit error rate tester BERT reference design demonstrating a serial link 1 0 Gb s to 3 125 Gb s between two RocketIO multi gigabit transceivers MGT embedded in a single Virtex II Pro FPGA To build a system an IBM CoreConnect infrastructure connects the PowerPC 405 processor PPC405 to external memory and other peripherals using the processor local bus PLB and device control register DCR buses The reference design uses a two channel Xilinx bit error rate tester XBERT module for generating and verifying high speed serial data transmitted and received by the RocketIO transceivers The data to be transmitted 1s constructed using pseudorandom bit sequence PRBS patterns The receiver in XBERT module compares the incoming data with the expected data to analyze for errors The XBERT supports several different types of user selectable PRBS patterns Frame counters in the receiver are used to track the total number of data words frames received and total number of data words with bit errors The processor reads the status and counter values from the XBERT through the PLB Interface then sends out the information to the UART XAPP662 In Circuit Partial Reconfiguration of RocketlO Attributes 148 This application note describes in circuit partial reconfiguration of RocketIO transceiver attributes using the
188. s on the width of the receiver data path 2 is typically the same as TXUSRCLK2 TXUSRCLK2 Input Clock from FPGA used to clock TX data and status between the transceiver and FPGA fabric The relationship between TXUSRCLK2 and TXUSRCLK depends on the width of the transmission data path Notes 1 TXUSRCLK and TXUSRCLK2 must be driven by clock sources even if only the receiver of the is being used Table 2 2 Reference Clock Usage Data Rate Routing 600 Mb s 2 500 Gb s Can Route Can Route 2 499 Gb s 3 125 Gb s Across Chip Through BUFG REFCLK y 2 AJ BREFCLK Note 1 Note 1 Notes 1 Because of dedicated routing to reduce jitter BREFCLK cannot be routed through the fabric 2 While this option is available in the silicon this topography adds extra jitter to the reference clock which can affect the overall performance of the transceiver 42 www xilinx com RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 XILINX BREFCLK At speeds of 2 5 Gb s or greater REFCLK configuration introduces more than the maximum allowable jitter to the RocketIO transceiver For these higher speeds BREFCLK configuration is required The BREFCLK configuration uses dedicated routing resources that reduce jitter BREFCLK must enter the FPGA through dedicated clock I O BREFCLK can connect to the BREFCLK inputs of the transceiver and the
189. s to 3 125 Gb s baud transfer rates Monolithic clock synthesis and clock recovery system eliminating the need for external components Automatic lock to reference function Five levels of programmable serial output differential swing 800 mV to 1600 mV peak peak allowing compatibility with other serial system voltage levels Four levels of programmable pre emphasis AC and DC coupling Programmable 509 759 on chip termination eliminating the need for external termination resistors Serial and parallel TX to RX internal loopback modes for testing operability Programmable comma detection to allow for any protocol and detection of any 10 bit character The RocketIO Transceiver User Guide contains these sections Preface About This Guide This section Chapter 1 RocketIO Transceiver Overview An overview of the transceiver s capabilities and how it works Chapter 2 Digital Design Considerations Ports and attributes for the six provided communications protocol primitives VHDL Verilog code examples for clocking and reset schemes transceiver instantiation 8B 10B encoding CRC channel bonding Chapter 3 Analog Design Considerations RocketIO serial overview pre emphasis jitter clock data recovery PCB design requirements Chapter 4 Simulation and Implementation Simulation models implementation tools debugging and diagnostics RocketlO Transceiver User Guide www xilinx com 17 UG024 v2
190. second channel bonding sequence FALSE Channel bonding uses only one channel bonding sequence defined by CHAN BOND SEQ 1 1 4 TRUE Channel bonding uses two channel bonding sequences defined by CHAN BOND SEQ 1 1 4 and CHAN BOND SEQ 2 1 4 as further constrained by CHAN BOND SEQ LEN CHAN BOND SEQ LEN Integer 1 4 defines length in bytes of channel bonding sequence This defines the length of the sequence the transceiver matches to detect opportunities for channel bonding CHAN BOND WAIT Integer 1 15 that defines the length of wait in bytes after seeing channel bonding sequence before executing channel bonding RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 29 XILINX Chapter 1 RocketlO Transceiver Overview Table 1 6 RocketlO Transceiver Attributes Continued Attribute CLK COR INSERT IDLE FLAG Description TRUE FALSE controls whether RXRUNDISP input status denotes running disparity or inserted idle flag FALSE RXRUNDISP denotes running disparity when RXDATA is decoded data TRUE RXRUNDISP is raised for the first byte of each inserted repeated clock correction Idle sequence when RXDATA is decoded data CLK COR KEEP IDLE TRUE FALSE controls whether or not the final byte stream must retain at least one clock correction sequence FALSE Transceiver can remove all clock correction sequences to further recenter the elastic
191. smission latency from TXDATA to TXP and TXN The enabling of CRC does not affect the latency from RXP and RXN to RXDATA The typical and maximum latencies expressed in TXUSRCLK RXUSRCLK cycles are shown in Table 2 20 For timing diagrams expressing these relationships please see Module 3 of the Virtex II Pro Data Sheet Table 2 20 Effects of CRC on Transceiver Latency TXDATA to TXP and TXN RXP and RXN to RXDATA in TXUSRCLK Cycles in RXUSRCLK Cycles Typical Maximum Typical Maximum CRC Disabled 8 11 25 420 86 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 CRC Cyclic Redundancy Check A UNN Table 2 20 Effects of CRC on Transceiver Latency TXDATA to TXP and TXN RXP and RXN to RXDATA in TXUSRCLK Cycles in RXUSRCLK 3 Typical Maximum Typical Maximum CRC Enabled 14 17 25 420 Notes 1 See Table 2 6 and Table 2 7 for all MGT block latency parameters 2 This maximum may occur when certain conditions are present and clock correction and channel bonding are enabled If these functions are both disabled the maximum will be near the typical values 3 To further reduce receive side latency refer to Appendix C Related Online Documents Ports and Attributes TX CRC USE RX CRC USE These two attributes control whether the MGT CRC circuitry is enabled or bypassed When set to TRUE CRC is enabled When set to FALSE
192. ssed TXUSRCLK cycle RocketlO Transceiver User Guide www xilinx com 59 06024 v2 4 August 25 2004 3 XILINX Chapter 2 Digital Design Considerations Table 2 6 Latency through Various Transmitter Components Processes Continued Component Process Latency TX FIFO 4 TXUSRCLK cycles 0 5 TX SERDES SERDES 10B FALSE SERDES 10B TRUE 1 5 TXUSRCLK cycles 0 5 TXUSRCLK cycles approx Table 2 7 Latency through Various Receiver Components Processes Component Process Latency RX SERDES 1 5 recovered clock RXRECCLK cycles Comma Detect Realignment 2 5 or 3 5 recovered clock cycles some bits bypass one register depending on comma alignment included 1 recovered clock cycle 8B 10B Decoder bypassed recovered clock cycle RX FIFO 18 RXUSRCLK cycles 0 5 1 Byte Data Path 2 Byte Data Path 4 Byte Data Path RX GT Fabric Interface 2 5 RXUSRCLK2 cycles 1 RXUSRCLK2 cycle 1 25 RXUSRCLK2 cycles 1 25 RXUSRCLK cycles 1 RXUSRCLK cycle 2 5 RXUSRCLK cycles Reset Power Down 60 The receiver and transmitter have their own synchronous reset inputs The transmitter reset recenters the transmission FIFO and resets all transmitter registers and the 8B 10B encoder The receiver reset recenters the receiver elastic buffer and resets all receiver registers and the 8B 10B decoder Neither reset signal has any effect on the PLLs After the DCM locked signal is
193. t GND PSINCDEC gt GND PSEN gt GND PSCLK gt GND RST RST CLKO CLKO W LOCKED gt LOCK BUFG Instantiation U BUFG IBUFG port map I E REFCLK gt REFCLK IN RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 www xilinx com 47 3 XILINX Chapter 2 Digital Design Considerations U2 BUFG BUFG port map I gt CLKO gt USRCLK_M H end TWO BYTE CLK arch Verilog Template Module TWO BYTE CLK Description Verilog Submodule for 2 byte GT Device Virtex II Pro Family module TWO BYTE CLK input output output output wire wire wire wire wire wire DCM demi REFCLKIN REFCLK USRCLK M DCM LOCKED REFCLKIN REFCLK USRCLK M DCM LOCKED REFCLKIN REFCLK USRCLK M DCM LOCKED REFCLKINBUF 4 CLKFB USRCLK M CLKIN REFCLKINBUF DSSEN 1 bo PSCLK 1 bo PSEN 1 bo PSINCDEC 1150 RST 1 bo CLKO clk i CLK90 CLK180 yu CLK270 CLK2X CLK2X180 EA CLKDV H D D CLKFX CLKFX180 LOCKED DCM LOCKED PSDONE STATUS BUFG buf1 b 48 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Clocking A UNN I clki 0 USRCLK IBUFG buf2 I REFCLKIN REFCLKINBUF E endmodule Example 1b Two Byte
194. tlO Transceiver User Guide www xilinx com 123 UG024 v2 4 August 25 2004 A XILINX Chapter 4 Simulation and Implementation MASTER SLAVE 1 HOP CHBONDI CHBONDO CHBONDI CHBONDO Top of device Bottom of device CHBONDI CHBONDO CHBONDI CHBONDO SLAVE 1 HOP SLAVE 2 HOPS 06024 08 020802 Figure 4 1 XC2VP2 Implementation SLAVE 1 HOP SLAVE 1 HOP SLAVE 1 HOP MASTER SLAVE 1 HOP SLAVE 1 HOP SLAVE 1 HOP CHBONDI CHBONDO CHBOND CHBONDO CHBOND CHBONDO CHBOND CHBONDO CHBOND CHBONDO CHBOND CHBONDO CHBONDO SLAVE 1 HOP CHBONDI CHBONDO Top of device Bottom of device CHBONDO CHBONDI CHBONDO CHBONDO CHBOND CHBONDO CHBONDO CHBOND CHBONDO CHBOND CHBONDO CHBONDI SLAVE 2 HOPS SLAVE 2 HOPS SLAVE 2 HOPS SLAVE 1 HOP SLAVE 2 HOPS SLAVE 2 HOPS SLAVE 2 HOPS SLAVE 2 HOPS 06024 08 020802 Figure 4 2 XC2VP50 Implementation 124 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Package Pins MGT Package Pins XILINX The MGT is a hard core placed in the FPGA fabric all package pins for the MGTs are dedicated on the Virtex II Pro device This is shown in the package pin diagrams in the Virtex II Pro Platform FPGA User Guide When creating a design LOC constraints must be used to implement a specific on the die This LOC constraint
195. tractive single chip solution to serial transceiver design problems that previously required multiple devices This white paper describes several different dedicated external SERDES devices and presents alternative design solutions using the Virtex II Pro Platform FPGA with RocketIO transceivers The four external devices discussed here are the Vitesse single channel VSC7123 the Vitesse quadchannelVSC7216 01 the Texas Instruments TLK3101 and the Mindspeed CX27201 The features offered by each of these devices are presented along with a discussion of how the RocketIO transceiver can afford an alternative to each multi chip solution Links to Xilinx information resources for the Virtex II Pro Platform FPGA and embedded RocketIO transceiver are presented in the final section 152 www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Index Numerics 8B 10B Encoding Decoding bypassing 69 decoder 63 encoder 63 overview 63 ports and attributes 64 serial output format 69 8B 10B Valid Characters 137 A AC and DC Coupling 119 Attributes amp Ports by function 8B 10B encoding decoding 64 buffers fabric interface 92 channel bonding 83 clock correction 76 CRC 87 SERDES alignment 70 synchronization logic 79 Attributes defined ALIGN COMMA MSB 70 CHAN BOND SEQ LEN 84 CHAN BOND LIMIT 84 CHAN BOND MODE 83 CHAN BOND OFFSET 84 CHAN BOND ONE SHOT 83 CHAN BOND SEQ 84 CHAN BOND SEQ 2 USE 84 CHAN BON
196. transceivers MGTs Using RXRECCLK with local clock routing can enable applications to bypass the MGT s elastic www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 Characterization Reports A XILINX buffer thus reducing latency without consuming global clock resources Along with a reference design this application note explains how to use the local clocking resources Characterization Reports Characterization Reports and SPICE models can be accessed from the Xilinx SPICE Suite http www xilinx com xInx xil prodcat product sp title spice models Online registration required Follow the instructions on the web page to register Virtex Il Pro RocketlO Multi Gigabit Transceiver Characterization Summary Virtex II Pro devices contain up to twenty four embedded RocketIO multi gigabit transceivers MGTs for the creation of high speed serial links from chip to chip across a backplane or from system to system Each MGT has separate transmit and receive functions full duplex and can be operated at baud rates from 600 Mb s to 3 125 Gb s Additionally every RocketIO MGT block is fully independent and contains a complete set of common SerDes serializer deserializer functions This allows Virtex II Pro devices to support many existing and emerging serial I O standards at data rates up to 10 Gb s including e XAUI 10 Gigabit Attachment Unit Interface PCI Express e Serial RapidIOTM e Fibre Channe
197. transmission reception and decode of this invalid character will create unexpected RXDATA results in the RocketIO receiver or in other transceivers RXCHARISK RXRUNDISP RXCHARISK and RXRUNDISP are dual purpose ports for the receiver depending whether 8B 10B decoding 15 enabled Table 2 10 shows this dual functionality When decoding 15 enabled the ports function as byte mapped status ports for the received data In the 8B 10B decoding configuration RXCHARISK asserted High indicates the received byte of data 1s a control character Otherwise the received byte of data 15 a data character See Appendix B 8B 10B Valid Characters www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 8 10 Encoding Decoding A XILINX The RXRUNDISP port indicates the disparity of the received byte is either negative or positive RXRUNDISP asserted High indicates positive disparity This is used in cases like the Vitesse Disparity Example below When CLK COR INSERT IDLE FLAG TRUE RXRUNDISP is asserted to flag the presence of an inserted clock correction sequence In the bypassed configuration and RXRUNDISP are additional data bits for the 10 20 or 40 bit buses similar to the configuration on the transmit side RXCHARISK 0 3 relates to bits 9 19 29 and 39 while RXRUNDISP pertains to bits 8 18 28 and 38 of the data bus See Figure 2 14 RXDISPERR RXDISPERR is a status port
198. uence before the transceiver executes channel bonding alignment across all channel bonded transceivers CHAN BOND OFFSET specifies the first elastic buffer read address that all channel bonded transceivers have immediately after channel bonding alignment as a positive offset from the beginning of the matched channel bonding sequence in each transceiver For optimal performance of the elastic buffer CHAN BOND WAIT and CHAN BOND OFFSET should be set to the same value typically 8 CHAN BOND ONE SHOT TRUE FALSE that controls repeated execution of channel bonding FALSE Master transceiver initiates channel bonding whenever possible whenever channel bonding sequence is detected in the input as long as input ENCHANSYNC 1s High and RXRESET 15 Low TRUE Master transceiver initiates channel bonding only the first time it is possible channel bonding sequence is detected in input following negated RXRESET and asserted ENCHANSYNC After channel bonding alignment is done it does not occur again until RXRESET is asserted and negated or until ENCHANSYNC is negated and reasserted Always set Slave transceivers CHAN BOND ONE SHOT to FALSE CHAN BOND SEQ 11 bit vectors that define the channel bonding sequence The usage of these vectors also depends on CHAN BOND SEQ LEN BOND SEQ 2 USE See Receiving Vitesse Channel Bonding Sequence page 68 for format CHAN BOND SEQ 2 USE Controls use of
199. ure 2 29 RXDATA Aligned Correctly RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 95 A XILINX Chapter 2 Digital Design Considerations When RXDATA is 32 bit misaligned the word requiring alignment is split between consecutive RXDATA words in the data stream as shown in Figure 2 30 RXDATA REG in the figure refers to the design example code in 32 bit Alignment Design page 96 ug024 34 091602 Figure 2 30 Realignment of RXDATA This conditional shift delay operation on RXDATA also must be performed on the status outputs RXNOTINTABLE RXDISPERR RXCHARISK RXCHARISCOMMA and RXRUNDISP in order to keep them properly synchronized with RXDATA It is not possible to adjust RXCLKCORCNT appropriately for shifted delayed RXDATA because RXCLKCORCNT is summary data and the summary for the shifted case cannot be recalculated 32 bit Alignment Design The following example code illustrates one way to create the logic to properly align 32 bit wide data with a comma in bits 31 24 For brevity most status bits are not included in this example design however these should be shifted in the same manner as RXDATA and RXCHARISK Note that when using a 40 bit data path 8B 10B bypassed a similar realignment scheme may be used but it cannot rely on RXCHARISCOMMA for comma detection Verilog IK XILINX IS PROVIDING THIS DESIGN CODE OR INFORMATION AS IS AS A COURTESY TO YOU SOLELY
200. urs Note Data length must be greater than 20 bytes for USER MODE CRC generation For CRC to operate correctly at least four gap bytes are required between EOP of one packet and SOP of the next packet The gap may contain clock correction sequences provided that at least 4 bytes of gap remain after all clock corrections FIBRE CHAN The FIBRE CHAN CRC is similar to USER MODE CRC Figure 2 24 with one exception In FIBRE CHAN SOP and EOP are predefined protocol delimiters Unlike USER MODE RocketlO Transceiver User Guide www xilinx com 87 06024 v2 4 August 25 2004 3 XILINX 88 Chapter 2 Digital Design Considerations FIBRE CHAN does not need to define the attributes CRC START OF PKT and CRC END OF PKT Both USER MODE and FIBRE CHAN however disregard SOP and EOP in CRC computation ol s s T 9 RXCHECKINGCRC 14 RXCRCERR 06024 12 022803 Figure 2 24 USER MODE FIBRE Mode Designs should generate only the EOP frame delimiter for a beginning running disparity RD that is negative These are the frame delimiters that begin with K28 5 D21 4 or K28 5 D10 4 Never generate the EOP frame delimiter for a beginning RD that is positive These are the frame delimiters that begin with K28 5 D21 5 or K28 5 D10 5 When the RocketIO CRC determines that the running disparity must be inverted to satisfy Fibre Channel requirements it will convert the second byte of the EOP frame delimiter D21 4 or
201. whenever the elastic buffer is reinitialized that is upon asserted RXRESET or RXREALIGN Count down is enabled whenever a comma is known to have come through the comma detection circuit is upon an asserted RXREALIGN or RXCOMMADET and count some idea that usrclk2 BEGIN IF usrclk2 EVENT AND IF rxreset 1 wait to sync count lt 0 ELSE IF usrclk2 THEN THEN 33145 11 11 1111 rxrealign wait to sync count lt 1 ELSE IF lt THEN 0000 THEN wait to sync 0001 count 1 IF wait to sync wait to sync END IF END IF IF rxcommadet count lt 1 END IF END IF END IF END IF 1 THEN END PROCESS This process maintains output sync which indicates when outgoing aligned data should be properly aligned with the comma in aligned data 31 24 Output aligned data is considered to be in sync when a comma is seen on rxdata as indicated RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 101 A XILINX Chapter 2 Digital Design Considerations by rxchariscomma3 or 1 after the counter wait to sync has reached 0 indicating that commas seen by the comma detection circuit have had time to propagate to aligned data after initialization of the elastic buffer PROCESS usrclk2 BEGIN IF usrclk2 EVENT AND usrclk2 1 THEN IF rxreset OR rxrealign
202. will convert the first K28 5 D16 2 IDLE following a packet to K28 5 D5 6 performing the necessary conversion www xilinx com RocketlO Transceiver User Guide UG024 v2 4 August 25 2004 CRC Cyclic Redundancy Check A UNN Note As noted in Figure 2 25 pad bits are used to assure that the header data and CRC total to the 64 byte minimum packet length For packets that are already 64 bytes or longer pad bits are not used Note that CRC generation for IDLE requires that the transmitted K28 5 be left justified in the MGT s internal two byte data path Observing the following restrictions assures correct alignment of the packet delimiters 4 byte data path K28 5 must appear in TXDATA 31 24 or TXDATA 15 8 e 2 byte data path K28 5 must appear in TXDATA 15 8 e byte data path K28 5 must be strobed into the MGT on rising TXUSRCLK2 only when TXUSRCLK is High Note Minimum data length for this mode is defined by the protocol requirements Note For correct operation of the Gigabit Ethernet CRC function transmitted and received frames must comply with the 802 3 specification regarding Gigabit Ethernet This includes the preamble maximum length INFINIBAND The Infiniband CRC is the most complex mode and is not supported in the CRC generator Infiniband CRC contains two computation types an invariant 32 bit CRC the same as in Ethernet protocol and a variant 16 bit CRC which is not supported in the hard core Infi
203. wn in Table 3 3 Table 3 3 Differential Receiver Parameters Parameter Min Typ Max Units Conditions Serial input differential peak to VIN peak RXP RXN x 2000 SR Vim Common mode input voltage 300 2500 mV range Tiskgw Differential input skew 75 ps Receive data total jitter tolerance 1 TTo penk to peak 0 65 UI Receive data deterministic jitter tolerance peak to peak on ul Notes 1 Unit Interval Jitter Jitter is defined as the short term variations of significant instants of a signal from their ideal positions in time ITU Jitter is typically expressed in a decimal fraction of Unit Interval UI e g 0 3 UI Total Jitter Deterministic Jitter DJ Random Jitter RJ RocketlO Transceiver User Guide 06024 v2 4 August 25 2004 www xilinx com 109 3 XILINX Chapter 3 Analog Design Considerations Deterministic Jitter DJ is data pattern dependant jitter attributed to a unique source e g Inter Symbol Interference IST due to loss effects of the media DJ is linearly additive Random Jitter RJ is due to stochastic sources such as substrate power supply etc RJ is additive as the sum of squares and follows a bell curve Clock and Data Recovery The serial transceiver input is locked to the input data stream through Clock and Data Recovery CDR a built in feature of the RocketIO transceiver CDR keys off the r

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RocketIO™ Transceiver User Guide