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PSpice A/D User's Guide

1. Analysis type Sweep variable foc Sweep Voltage source Name RD C Current source Pere tne Set C Global parameter W Primary Sweep Pern Model name Monte Carlo Worst Case Temperature pall Parametric Sweep Temperature Sweep j Sweep type Save Bias Point nest Start value fio OLoad Bias Point Endivale fo Logarithmic Decade Increment fio Value list l To set up a nested sw eep 1 Under Options select the Secondary Sweep box for the DC Sweep Analysis type DC Sweep 311 Chapter9 DC analyses 2 Enter the necessary parameter values and select the appropriate check boxes to complete the analysis specifications 312 Curve families for DC sweeps When a nested DC sweep is performed the entire curve family is displayed That is the nested DC sweep is treated as a single data section or you can think of it as a single PSpice A D run For the circuit shown in Figure 59 you can set up a DC sweep analysis with an outer sweep of the voltage source VD and an inner sweep of the voltage source VG as listed in Table 1 Tablel Curve family example setup Outer sweep Nested sweep Swept Var Type voltage source voltage source Sweep Type linear linear Name VD VG Start Value 0 0 End Value 5 2 Increment 0 1 0 5 When the DC sweep analysis is run add a current marker at the drain pin of M1 and display the simulation results in PSpice A D The re
2. UU E clipper sth I Smmuaton Profle SEMATI DC Sweep x F oi C Sweep E ae TE i Stat 10 VVin 15 End 15 oc hed Simulation complete 4 Analysis Wach A Devices For Help press Fi VVin 15 100 ee Figure 7 Probe window To plot voltages at nets In and Mid 1 From PSpice s Trace menu choose Add Trace 2 Inthe Add Traces dialog box select V In and V Mid 3 Click OK To display a trace using a marker 1 From Capture s PSpice menu point to Markers and choose Voltage Level 2 Click to place a marker on net Out as shown in Figure 8 Veco A R2 ZA Di 3 3k D1N3940 R1 c1 Ne AAA 4 Mid 4 4H out 1k 0 47u v R3 ZS D R4 3 3k D1N3940 5 6k 4 o Veco A N fi y7 ka Vin ov 2a 1 1 o o Figure 8 Clipper circuit with voltage marker on net Out 3 Right click and choose End Mode to stop placing markers 4 From the File menu choose Save 5 Switch to PSpice The V Out waveform trace appears as shown in Figure 9 IE SCHEMATIC1 DC Sweep OrCAD PSpice A D clipper SCHEMATIC1 DC Sweep dat Fle Edt View Simulation Trace Plot Took Window Help alaj a o ge seml gt 4 Me ScHEVATIC OC vee gt at hega OieS SAP id KV FMA Bae 160 100 5u w 5U 10 45u U IN Y U MID U OUT u_Vin BB clipper SCH 4 Simulation
3. 004 372 Example schematic EXAMPLELOP has oe wee Rw ee Oo 374 Figure 76 Figure 77 Figure 78 Figure 79 Figure 80 Figure 81 Figure 82 Figure 83 Figure 84 Figure 85 Figure 86 Figure 87 Figure 88 Figure 89 Figure 90 Figure 91 Figure 92 Figure 93 Figure 94 Figure 95 Figure 96 Figure 97 Figure 98 Figure 99 Figure 100 Figure 101 Figure 102 Figure 103 Figure 104 Figure 105 Figure 106 Figure 107 Figure 108 Figure 109 Figure 110 Figure 111 Figure 112 Figure 113 Figure 114 Figure 115 Figure 116 Figure 117 Figures Example schematic EXAMPLE DSN 00000 380 Monte Carlo analysis setup for EXAMPLE DSN 382 Summary of Monte Carlo runs for EXAMPLE OPJ 383 Parameter values for Monte Carlo pass three 384 Pressure sensor circuit 2 ee 385 Model definition for RMontel 0 0 0 0 000000048 390 Pressure sensor circuit with RMontel and RTherm model definitions 391 Chebyshey filt r lt o ea 669 deh ete OS ba GS Se HES EASES s 394 1 dB bandwidth histogram sh ek ee ae ke ee eR ew 397 Center frequency histogram oases ees oe Reade ee eee RS 398 Simple biased BJT amplifier 6 6 2x4 eS ee eee Rd ee 401 Amplifier netlist and circuit file 24 424 424 eH e ban Se ees 402 YatX Goal Function 2 a a a 403 Correct worst case results o oo oo e 404 Incorrect worst case results 2 o oo 404 Schematic using VARY BOTH
4. five runs Simulation Settings Monte Carlo xj General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window Analysis lype Monte Carlo Joc Sweep a Worst case Sensitivity Output variable Options m Monte Carlo options Primary Sweep Number of runs fs 1 400 Secondary Sweep Use distribution gt Distributions Monte Carlo worst Case Parametric Sweep Temperature Sweep Save Bias Point OLoad Bias Point Random number seed 1 32767 lt none gt gt runs Senstviyoptians that have fboth DEY and LOT Limit devices to ypes ja Gave dete from each sensitivity ran More Settings Save data from ioerances Figure 77 Monte Carlo analysis setup for EXAMPLE DSN PSpice A D starts by running all of the analyses enabled in the Simulation Settings dialog box with all parameters set to their nominal values However with Monte Carlo enabled PSpice A D saves the DC sweep analysis results for later reference and comparison After the nominal analyses are finished PSpice A D performs the additional specified analysis runs in this example DC sweep Subsequent runs use the same analysis specification as the nominal run with one major exception instead of using the nominal parameter values the tolerances are applied to set new parameter values and thus new part values There is a trade off in choosing the num
5. 8 O U ONDISE o RMSSUH 20f 22 2 22 22 22 22222222 222222 nnn 22222 Wicdesnencnssese doses oo oceee een ste E AA ERE es See ie o SEL gt gt 6 0 V A0 0O O y ad so O V 4 o Y ho 0 Aoi 4 0GHz 106Hz J A o 1661 requency Figure 64 Device and total noise traces for EXAMPLE DSN Frequency is swept from 100 kHz to 10 GHz by decades with 10 points per decade The V1 independent voltage source is the only input to an amplifier so it is the only AC stimulus to this circuit Magnitude equals 1 V and relative phase is left at zero degrees the default All other voltage sources have zero AC value Noise analysis To find out more about PSpice macros refer to PSpice A D online Help Note The source V1 is a VSIN source that is normally used for setting up sine wave signals for a transient analysis It also has an AC property so that you can use it for an AC analysis To find out more about VSIN and other source symbols that you can use for AC analysis see Using time based stimulus parts with AC and DC properties on page 3 118 339 Chapter 10 AC analyses 340 Transient analysis 11 Chapter overview This chapter describes how to set up a transient analysis and includes the following sections Overview of transient analysis on page 11 342 Defining a time based stimulus on page 11 344 Transi
6. Figure 72 shows how the overshoot increases with increasing resistance Parametric analysis SCHEMATIC1 Parametric OrCAD PSpice A D_ ricfilt SCHEMATIC1 Test dat Fie Edt View Simulation Trace Plot Tools Window Help zlajxi Desaignes 8 a amp 9 m e E Smet A a a y a a e e 0 4 0 6 6 8 GD o GenRise 1 L1 Z v Overshoot 1 L1 Is 1 L1 9 E ricfit SCHEM For Help press F1 J I m Figure 72 Rise time and overshoot vs damping resistance 369 Chapter 12 Parametric and temperature analysis This technique for measuring branch capacitances works well in both simple and complex circuits PARAMETERS Vbias 10 1 ci Vin Al Cnn DO Vbias ik iuF AC 1 Figure 73 RLC filter example circuit 370 Example frequency response vs arbitrary parameter You can view a plot of the linear response of a circuit at a specific frequency as one of the circuit parameters varies such as the output of a band pass filter at its center frequency vs an inductor value In this example the value of a nonlinear capacitance is measured using a 10 kHz AC signal and plotted versus its bias voltage The capacitance is in parallel with a resistor so a trace expression is used to calculate the capacitance from the complex admittance of the R C pair Setting up the druit Ent
7. Table 2 For voltage input Use this When you are running VAC An AC sweep analysis only VSRC Multiple analysis types including AC sweep Table 3 For current input Use this When you are running IAC An AC sweep analysis only ISRC Multiple analysis types including AC sweep AC sweep analysis Note Unlike DC sweep the AC Sweep Noise dialog box not indude an input source option Instead each independent source in your circuit contains its own AC specification for magnitude and phase If you are planning to run a DC or transient analysis in addition to an AC analysis see If you want to specify multiple stimulus types on page 3 118 for additional information and source symbols that you can use 325 Chapter 10 AC analyses 2 Double click the symbol instance to display the Parts spreadsheet 3 Click in the cell under the appropriate property column to edit its value Depending on the source symbol that you placed define the AC specification as follows Table 4 For VAC or IAC Set this property To this value ACMAG AC magnitude in volts for VAC or amps for IAC units are optional ACPHASE Optional AC phase in degrees Table 5 For VSRC or ISRC Set this property To this value If you are also planning to run a transient AC Magnitude_value phase_value analysis see Using VSRC or ISRC where magnitude_value is in volts or parts on page 3 119 t
8. dien biped To edit display and print colors in the PSPICE INI file brightmagenta Note After editing PSPICE INI you must restart PSpice A D before your brightwhite changes will take effect brightyellow darkblue 1 Ina standard text editor such as Notepad open PSPICE INI This file is normally located in the darkcyan darkgray darkgreen P a C Windows directory darkmagenta darkred r Scroll to the PROBE DISPLAY COLORS or oe PROBE PRINTER COLORS section of the file lightgreen 3 Add or modify a color entry See Table 19 on lightblue lightgray green page 17 481 for a description of color entries and their magenta mustard orange default values Valid item names include pink purple red e BACKGROUND brown blue cyan e FOREGROUND white black yellow 480 Setting up waveform analysis e TRACE_1 through TRACE_12 4 If you added or deleted trace number entries set NUMTRACECOLORS n to the new number of traces where n is between 1 and 12 This item represents the number of trace colors displayed on the screen or printed before the color order repeats 5 Save the file Table19 Default waveform viewing colors Item Name Description Default BACKGROUND specifies the color of BLACK When you want to copy Probe plots to the window background dipboard and then paste them into a black FOREGROUND specifies the default WHITE and white document choose the Change All color for items not Colors to Black option under Foregr
9. 156 Example editing a Q2N2222 instance model Suppose you have a design named MY OP J that contains several instances of a Q2N2222 bipolar transistor Suppose also that you are interested in the effect of base resistance variation on one specific device Q6 To do this you need to do the following e Define a tolerance in this example 5 on the Rb model parameter e Set up and run a Monte Carlo analysis The following example demonstrates how to set up the instance model for Q6 Starting the Model Editor To start the Model Editor you need to 1 Inthe schematic page editor select Q6 on the schematic page 2 From the Edit menu choose PSpice Model The Model Editor automatically creates a copy of the Q2N2222 base model definition 3 Inthe Model Editor from the View menu choose Model Text The Model Editor displays the PSpice syntax for the copied model in the text editing area Editing the Q2N2222 X model instance Text edits appropriate to this example are as follows e Add the DEV 5 clause to the Rb statement required e Change the model name to 92N2222 mc optional for descriptive purposes only Saving the edits and updating the schematic When you choose Save from the File menu two things happen e The Model Editor saves the model definition to the model library e The schematic page editor updates the Implementation property value to Q2N2222 MC for the Q6 part instance In this e
10. Chapter 6 Analog behavioral modeling 226 TABLE 15 15 15 15 EXPR V IN IN First EXPR is evaluated and that value is used to look up an entry in the table EXPR is a function of the input current or voltage and follows the same rules as for VALUE expressions The table consists of pairs of values the first of which is an input and the second of which is the corresponding output Linear interpolation is performed between entries For values of EXPR outside the table s range the device s output is a constant with a value equal to the entry with the smallest or largest input This characteristic can be used to impose an upper and lower limit on the output An example of a table declaration using the TABLE property would be the following TABLE 0 0 02 2 690E 03 04 4 102E 03 06 4 621E 03 08 4 460E 03 10 3 860E 03 12 3 079E 03 14 327E 03 16 1 726E 03 18 1 308E 03 20 1 042E 03 22 734E 04 24 7 544E 04 26 6 566E 04 28 5 718E 04 30 013E 04 32 4 464E 04 34 4 053E 04 36 3 781E 04 38 744E 04 40 4 127E 04 42 5 053E 04 44 6 380E 04 46 935E 04 48 1 139E 03 50 2 605E 03 52 8 259E 03 54 2 609E 02 56 7 418E 02 58 1 895E 01 60 4 426E 01 jo a K a fi Ga kog iP ot ieee IP oot Hot wa AR oa NA E a ja Frequency domain device models Frequency domain models
11. Concepts you need to understand on page 14 411 Defining a digital stimulus on page 14 413 Defining simulation time on page 14 426 Adjusting simulation parameters on page 14 427 Starting the simulation on page 14 429 Analyzing results on page 14 430 Chapter 14 Digital simulation See Tracking timing violations and hazards on page 14 435 for information about persistent hazards and for descriptions of the warning messages For more information on drawing designs see your OrCAD Capture User s Guide Steps 2 through 6 of this process are covered in this chapter 410 What is digital simulation Digital simulation is the analysis of logic and timing behavior of digital devices over time PSpice A D simulates this behavior during transient analysis When computing the bias point PSpice A D considers the digital devices in addition to any analog devices in the circuit PSpice A D performs detailed timing analysis subject to the constraints specified for the devices For example flip flops perform setup checks on the incoming clock and data signals PSpice A D reports any timing violations or hazards as messages written to the simulation output file and the waveform data file Steps for simulating digital circuits There are six steps in the development and simulation of digital circuits 1 Drawing the design Defining the stimuli Setting the simulation time Adjusting the simulation parameters Starting t
12. GMIN stepping attempts to find a solution by starting the repeating cycle with a large value of GMIN initially 1 0e10 times the nominal value If a solution is found at this setting it then reduces GMIN by a factor of 10 and tries again This continues until either GMIN is back to the nominal value or a repeating cycle fails to converge In the latter case GMIN is restored to the nominal value and the power supplies are stepped Bias point and DC sweep Bias point and DC sweep Power supply stepping As previously discussed PSpice uses a proprietary algorithm which finds a continuous path from zero power supplies levels to 100 It starts at almost zero 001 power supplies levels and works its way back up to the 100 levels The minimum step size is 1e 6 0001 The first repeating series of the first step starts at zero for all voltages Semiconductors Model parameters The first consideration for semiconductors is to avoid physically unrealistic model parameters Remember that as PSpice steps the power supplies up it has to step carefully through the turn on transition for each device In the diode example above for the setting N 1e 6 the knee of the I V curve would be too sharp for PSpice to maintain its continuity within the power supply step size limit of le 6 Unguarded p n junctions A second consideration is to avoid unguarded p n junctions no series resistance The above diode example also applies to
13. Generic Mfg Device Type Name Name Symbol Name Library Tech Type Model Operational Amplifier OP 249 Analog OP 249G AD ANLG_DEV SL amp Devices Inc Operational Amplifier OP 260 Analog OP 260 AD ANLG_DEV SLB Devices Inc Operational Amplifier Analog OP 27 AD ANLG_DEVSLB amp Davices Inc Operational Amplifier OP 27 Analog OP 27VAD ANLG_DEV SL8S Devices Inc Operational Amplifier OP 27 Analog OP 27B AD ANLG_DEV SL8 Devices Inc Operational Amplifier OP 27 Analog OP 27C AD ANLG_DEV SLB Devices Inc Operational Amplifiers OP 27 Analog OP 27E AD ANLG_DEV SL8 Devices Inc Operational Amplifier OP 27 Analog OP 27F AD ANLG_DEVSL amp Devices Ing Operational Amplifier OP 27 Analog OP 27G AD ANLG_DEV SLE Devices Inc Operational Amplifiers OP 27 Linear OP 27 LT LIN_TECH SLB Technology Corp Operational Amplifier OP 27 OP 27 OPAMP SLB Operational Amplifier OP 275 Analog OP 275 AD ANLG_DEV SLB Davices Inc Operational Amplifier OP 275 Analog OP 275G AD ANLG_DEV SL8S Devices Ing Operational Amplifier OP 27A Linear OP 27AAT LIN_TECH SLB Technology Corp Operational Amplifier OP 27C Linear OP 27C LT UN_TECH SLB Technology Corp Using parts that you can simulate For a listing of vendor supplied parts contained in the OrCAD libraries refer to the online Library List To find out more about each model library read the comments in the LIB file header New for Package 8 0 101 Chapter 3 Preparing a de
14. LOAD F 2C LOAD amp C JC I1C amp LOAD amp 12C kC TIC amp 12C 1D QC amp QB amp QA amp EN EN amp QA amp QD LOAD a 2D LOAD amp D JD I1D amp LOAD amp 12D 281 Chapter 7 Digital device modeling 282 D ID amp 12D RCO QD amp QA amp ENT UJKFF JKFF 4 DPWR DGND D_HI CLRBAR CLKBAR JA JB JC JD KA KB KC KD QA QB QC QD QABAR QBBAR QCBAR QDBAR DO_EFF 10_STD U160DLY PINDLY 5 0 10 DPWR DGND RCO QA QB QC QD CLK LOADBAR ENT CLRBAR ENP ABCDE RCO_O QA_O QB_0 QC_O QD_O IO STD MNTYMXDLY MNTYMXDLY TO_LEVEL IO_LEVEL BOOLEAN CLOCK CHANGED_LH CLK 0 CNTENT CHANGED ENT O PINDLY QAO QB_O QC_O QD_O CASE CHANGED_HL CLRBAR O DELAY 1 26NS 38NS DELAY 1 26NS 38NS a a F RCO_O a CASE CNTENT DELAY 1 11NS 16NS CLOCK DELAY 1 23NS 35NS DELAY 1 23NS 35NS E T FREQ F ODE CLK AXFREQ 25MEG WIDTH ODE CLK LO 25NS HI 25NS WIDTH F ODE CLRBAR LO 20NS TUP_HOLD DATA 4 A BC D CLOCK LH CL 5 W ETUPTIME 20NS HEN LOADBAR 1 CHANGED LOADBAR O amp ite CLRBAR 0 SETUP_HOLD DATA 2 ENP ENT CLOCK LH CL SETUPTIME 20NS WHEN CLRBAR 0 amp LOADBAR 0 CHANGED LOADBAR 0 amp CHANGED EN
15. Note The model parameter defaults used by the Model Editor are different from those used by the models built into PSpice A D 137 Chapter 4 Creating and editing models Testing and verifying models created with the Model Editor Each curve in the Model Editor is defined only by the parameters being adjusted For the diode the forward current curve only shows the part of the current equation that is associated with the forward characteristic parameters such as IS N Rs However PSpice uses the full equation for the diode model which includes a term involving the reverse characteristic parameters such as ISR NR These parameters could have a significant effect at low current This means that the curve displayed in the Model Editor does not exactly match whatis displayed in PSpice after a simulation Be sure to test and verify models using PSpice If needed fine tune the models Note When specifying operating characteristics for a model you can use typical values found on data sheets effectively for most simulations To verify your design you may also want to use best and worst case values to create separate models and then swap them into the circuit design 138 Ways To Characterize Models Figure 28 shows two ways to characterize models using the Model Editor device data from data sheets parts estimation PSpice A D model simplified graph of device parameters equation characterist
16. Once you have defined a parameter declared its name f a values for what if analyses and given it a value you can use it to represent circuit values anywhere in the design this applies to any Example If two independent sources have hierarchical level a value defined by the parameter VSUPPLY then you can change both sources to 10 volts by assigning the value e Apply the same value to multiple part instances once to VSUPPLY Some ways that you can use parameters are as follows e Set up an analysis that sweeps a variable through a range of values for example DC sweep or parametric analysis Dedaring and using a global parameter To use a global parameter in your design you need to e define the parameter using a PARAM part and e use the parameter in place of a literal value somewhere in your design 107 Chapter 3 Preparing a design for simulation Note For more information about using the Parts spreadsheet see the OrCAD Capture User s Guide Example To declare the global parameter VSUPPLY that will set the value of an independent voltage source to 14 volts place the PARAM part and then create a new property named VSUPPLY with a value of 14v Example To set the independent voltage source VCC to the value of the VSUPPLY parameter set its DC property to VSUPPLY PARAMETERS Al VSUPPLY 14V ik F a i vee in DO VSUPPLY So o 108 To declare a global parameter
17. The FTABLE part is described by a table of frequency responses in either the magnitude phase domain R_I or complex number domain R_I YES The entire table is read in and converted to magnitude in dB and phase in degrees Interpolation is performed between entries Magnitude is interpolated logarithmically phase is interpolated linearly For frequencies outside the table s range 0 zero magnitude is used This characteristic can be used to impose an upper and lower limit on the output The DELAY property increases the group delay of the frequency table by the specified amount The delay term is particularly useful when a frequency table device generates a non causality warning message during a transient analysis The warning message issues a delay Control system parts If more than five values are required the part can be customized through the part editor Insert additional row variables into the template using the same form as the first five and add ROWn properties as needed to the list of properties 207 Chapter 6 Analog behavioral modeling FTABLE Freq dB Deg OHz 0 0 5kHz 0 5760 BkHz 60 8912 DELAY 0 Figure 39 FTABLE part example 208 value that can be assigned to the part s DELAY property for subsequent runs without otherwise altering the table The output of the part depends on the analysis being done For DC and bias point the output is the zero frequency magnit
18. global parameter global parameter defined with a parameter block PARAM Minimum program setup requirements 1 Inthe Simulation Settings dialog box from the Analysis type list box select Time Domain Transient 2 Under Options select Parametric Sweep if it is not already enabled 3 Specify the required parameters for the sweep Simulation Settings Parametric Analysis x General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window Analysis type r Sweep variable Time Domain Transient z Voltage source Nene C Current source ere EEE Jodel type p Options Global parameter z General Settings c Modellname Model et Monte Carlo Worst Case eee lhe Parametric Sweep Temperature Paremata nane E Temperature Sweep OSave Bias Point 7 Sweep type Load Bias Point ali Start value fos Ae End value fis C Logarithmic Decade Increment fo C Value list 4 Click OK to save the simulation profile 5 From the PSpice menu choose Run to start the simulation Note Do not specify a DC sweep and a parametric analysis for the same variable Overview of parametric analysis Parametric analysis performs multiple iterations of a specified standard analysis while varying a global parameter model parameter component value or operational temperature The effect is the same as running the circuit several times once f
19. i i 8 A i When you finish creating transitions right click Click the transition at the start far left of the interval A small diamond appears over the transition From the Edit menu choose Properties In the Transition Type frame choose Set Value Increment or Decrement Do one of the following to specify the bus value Defining a digital stimulus e Inthe Value text box type a value e Select one of these defaults from the list 0 All bits 1 X Unknown or Z High impedance 8 Click OK 9 Repeat steps 4 through 8 for each transition To set the default bus radix 1 From the Tools menu choose Options 2 Inthe Bus Display Defaults frame from the Radix list select the radix you want as default Table 5 Select this radix To show values in this notation Binary base 2 Octal base 8 Decimal base 10 Hexadecimal base 16 3 Click OK 419 Chapter 14 Digital simulation Adding loops Suppose you have a stimulus that looks like this and you want to create a stimulus that consists of three consecutive occurrences of the sequence that starts at A and ends at B To find out more about the syntax of the fi gf A Gi th th s in bold Repeat 0s 000 250us I 500us 0 750us I Ims 000 Endrepe 420 mulus commands used in the stimulus e refer to the online OrCA D PSpice D Reference Manual ven the example shown o
20. 1 From the File menu choose Save Finding out more about setting up your design About setting up a design for simulation For a checklist of all of the things you need to do to set up your design for simulation and how to avoid common problems see Chapter 3 Preparing a design for simulation Example circuit creation 61 Chapter 2 Simulation examples You can set up a simulation profile to run one analysis at a time To run multiple analyses for example both DC sweep and transient analyses set up a batch simulation For more information see Chapter 8 Setting up analyses and starting simulation The root schematic listed is the schematic page associated with the simulation profile you are creating 62 Running PSpice A D When you perform a simulation PSpice A D generates an output file OUT While PSpice A D is running the progress of the simulation appears and is updated in the PSpice A D simulation output window see Figure 4 vm Simulation Profle SCHEMATIC Biag m MN Simulation running circuit file for profile Bias Reading and checking circuit Circuit read in and checked no errors Calculating bias point Bias point calculated Simulation complete Figure 4 PSpice A D simulation output window Performing a bias point analysis To set up a bias point analysis in Capture 1 In Capture switch to CLIPPER OP in the schematic page editor 2 From the PSpice menu
21. 152 Editing model text For any model you can edit model text in the Model Editor instead of using the Spec Entry and Parameter frames However there are two cases where you must edit the model text e When you want to edit models of device types not supported by the Model Editor The model text is displayed automatically when you load one of these models e When you want to add DEV and LOT tolerances to a model for Monte Carlo or sensitivity worst case analysis By typing PSpice commands and netlist entries you can do the following e change definitions and e create new definitions When you are finished the Model Editor automatically configures the model definitions into the model libraries To display the model text 1 From the View menu choose Model Text The Model Editor displays the PSpice syntax for model definitions e MODEL syntax for models defined as parameter sets e SUBCKT syntax for models defined as netlist subcircuits You can edit the definition just as you would in any standard text editor Editing MODEL definitions For definitions implemented as model parameter sets using PSpice MODEL syntax the Model Editor lists one parameter per line This makes it easier to add DEV LOT tolerances to model parameters for Monte Carlo or sensitivity worst case analysis Editing SUBCKT definitions For definitions implemented as subcircuit netlists using PSpice SUBCKT syntax the model e
22. 453 Interface generation and node names 00050 454 Digital worst case timing analysis 457 Chapter OVEIVIOW fate dd ke ewe oe pa E Se eS CaSO 457 Digital worst case timing 2666 bbe RR EERO OH 458 Starting worst case timing analysis 2 05 459 Simulator representation of timing ambiguity 459 Propagation of timing ambiguity 00 0048 461 Identification of timing hazards 2 4424025 sein eedu es 462 Convergence hazard o1 eS ee a ae ae ee Ge eee PH 462 Critical hazard 1 0 surs rs n EE ErEISAA REESS A D 463 Contents Cumulative ambiguity hazard 2 2436 be een de eo ewe ws 464 Reconversence hazard saw e s hack a ee OS Ee Banke 466 Glitch suppression due to inertial delay 468 Me thod logy s si se a ha kat eo ee eee Pa ORS Gee oe Ss 469 Partfour Viewing results Chapter 17 Analyzing waveforms 475 Chapter overview oonan a 475 Overview of waveform analysis ooo a 476 Elements of a plot aoaaa ENE ESS SEH Se 477 Elements of a Probe window oaaao a a ee 478 Managing multiple Probe windows a na 479 Printing multiple windows aaao eebe eV Gwe wes 479 Setting up waveform analysis ea pas od ee a 480 Setting up colors ooo EEEES OH EEE EREA SS 480 Editing display and print colors in the PSPICE INI file 480 Configuring trace color schemes 2 4 482 Viewing waveforms ocak ow A Sah Ee oe
23. 8 8 Text between the first s s separators if lt id gt is defined else the second s s clause lt id gt s s Text between s s separators if lt id gt is undefined lt id gt S 8S S Text between the first s s separators if lt id gt is undefined else the second S 5 clause lt id gt s s Text between s s separators if lt id gt is defined but delete rest of template if lt id gt is undefined is a separator character Separator characters include commas periods semi colons forward slashes and vertical bars You must always use the same character to specify an opening closing pair of separators Note You can use different separator characters to nest conditional property clauses Defining part properties needed for simulation Example The template fragment 2G bar if th If G tran G G G 1000 usesthe vertical as the separator between the en else parts of this conditional clause has a value then this fragment slates to G lt G property value gt Otherwise this fragment translates to G 000 183 Chapter 5 Creating parts for models Caution Recommended scheme for netlist templates Templates for devices in the part library start with a PSpice A D device letter followed by the hierarchical path and then the reference designator REFDES property OrCAD recommends that you adopt this scheme when defining your own netlist te
24. Chapter 6 Analog behavioral modeling 222 lt ABM specifies the form of the transfer keyword gt function to be used as one of VALUE arithmetic expression TABLE lookup table LAPLACE Laplace transform FREQ frequency response table CHEBYSHEV Chebyshev filter characteristics lt ABM specifies the transfer function as a function gt formula or lookup table as required by the specified lt ABM keyword gt Refer to the online OrCA D PSpice A D Reference Manual for detailed information Modeling mathematical or instantaneous relationships The instantaneous models using VALUE and TABLE extensions to PSpice A D E and G devices in the part templates enforce a direct response to the input at each moment in time For example the output might be equal to the square root of the input at every point in time Such a device has no memory or a flat frequency response These techniques can be used to model both linear and nonlinear responses Note For AC analysis a nonlinear device is first linearized around the bias point and then the linear equivalent is used EVALUE and GVALUE parts The EVALUE and GVALUE parts allow an instantaneous transfer function to be written as a mathematical expression in standard notation These parts take the input signal perform the function specified by the EXPR property on the signal and output the result on the output pins In controlled sources EXPR may contain constants and param
25. e modify the behavior of a Model Editor supported model e edit the PSpice command syntax text for MODEL and SUBCKT definitions e Create Subcircuit command in the schematic page editor when you have a hierarchical level in your design that you want to set up as an equivalent part with behavior described as a subcircuit netlist SUBCKT syntax Note Ifyou created a subcircuit definition using the Create Subcircuit command and want to alter it use the Model Editor to edit the definition or modify the original hierarchical schematic and run Create Subcircuit again to replace the definition Tools to create and edit models Note A limited version VAN of he Model Editor is L supplied with PSpice A D Basics For a description of models supported by the Model Editor see Model Editor supported device types on page 4 137 Note The Create Subcircuit command does not help you create a hierarchical design You need to create this yourself before using the Create Subcircuit command For information on hierarchical designs and how to create them refer to the OrCA D Capture User s Guide 133 Chapter 4 Creating and editing models Ways to create and edit models This section is a roadmap to other information in this chapter Find the task that you want to complete then go to the referenced sections for more information If you want to Then do this To find out more see this Create or edi
26. not supported in PSpice A D Basics 428 la Selecting propagation delays All digital devices including primitives and library models perform simulations using either minimum typical maximum or worst case min max timing characteristics You can set the delay circuit wide or on individual device instances Cirqit wide propagation delays You can set these to minimum typical maximum or variable within the min max range for digital worst case timing simulation on the Options tab of the Simulation Settings dialog box To specify the delay level circuit w ide 1 From Capture s PSpice menu choose Edit Simulation Settings 2 Click the Options tab 3 In the Category list box select Gate level simulation Part instance propagation delays You can set the propagation delay mode on an individual device thereby overriding the circuit wide delay mode To override the circuit w ide default on an individual part 1 Set the part s MNTYMXDLY property from 1 to 4 where 1 minimum 2 typical 3 maximum 4 worst case min max By default MNTYMXDLY is set to 0 which tells PSpice A D to use the circuit wide value defined in the Options tab Initializing flip flops To initialize all flip flops and latches Select one of the three Flip flop Initialization choices on the Options tab e Ifset to X all flip flops and latches produce an X unknown state until explicitly set or cleared or until a known st
27. x axis variable AVG x running average of x over the range of NO the x axis variable AVGX x d running average of x from NO X_axis_value x d to X_axis_value x RMS x running RMS average of x over the NO range of the x axis variable Table 12 Analog arithmetic functions for trace expressions Probe Description Available in function PSpice A D DB x magnitude in decibels of x NO MIN x minimum of the real part of x NO MAX x maximum of the real part of x NO In PSpice A D this function is called DDT x In PSpice A D this function is called SDT x Note For AC analysis PSpice A D uses complex arithmetic to evaluate trace expressions If the result of the expression is complex then its magnitude is displayed Rules for numeric values suffixes Explicit numeric values are entered in trace expressions in the same form as in simulation analyses by means of part properties in Capture with the following exceptions e Suffixes M and MEG are replaced with m milli 1E 3 and M mega 1E 6 respectively e MIL and mil are not supported e With the exception of the m and M scale suffixes PSpice is not case sensitive therefore upper and lower case characters are equivalent Unit suffixes are only used to label the axis they never affect the numerical results Therefore it is always safe to leave off a unit suffix The units to use for trace expressions are shown in Table 13 Table 13 Output units
28. 0 VEE Figure 117 Example schematic EXAMPLE OP Running the simulation The simulation is run with the Bias Point Detail Temperature and Transient analyses enabled The temperature analysis is set to analysis is setup as follows Print Step Final Time Enable Fourier Center Frequency Output Vars To start the simulation 35 degrees The transient 20ns 1000ns selected 1Meg V OUT2 1 From Capture s File menu point to Open and choose Project 2 Open the following project in your OrCAD program installation directory Analog example The example project EXAMPLE OP is provided with your OrCAD programs When shipped EXAMPLE OP is set up with multiple analyses For this example the AC sweep DC sweep Monte Carlo worst case and small signal transfer function analyses have been disabled The specification for each of these disabled analyses remains intact To run them from Capture in the future from the PSpice menu choose Edit Simulation Settings and enable the analyses Note When you run a Fourier analysis using PSpice A D as specified in this example PSpice A D writes the results to the PSpice output file 0UT You can also use Probe windows to display the Fourier transform of any trace expression by using the FFT capability in PSpice To find out more refer to PSpice A D online Help 497 Chapter 17 Analyzing waveforms If PSpice is set
29. 1 2 3 Note Click the transition you want to move If needed use Shift click to select additional transitions on the same signal or different signals Reposition the transition or transitions by dragging If you press Shift while dragging then all selected transitions move by the same amount To edit a transition 1 Do one of the following e Select the transition you want to edit and from the Edit menu choose Properties e Double click the transition you want to edit In the Stimulus propertiesdialog box edit the timing and value of the transition Click OK Defining a digital stimulus To delete a transition 1 Click the transition you want to delete 2 If needed press Shift click to select additional transitions on the same signal or different signals 3 From the Edit menu choose Delete Defining bus transitions There are three steps for creating a bus 1 Creating the digital bus stimulus 2 Introducing transitions 3 Optionally defining the radix for bus values These steps are described in detail in the following procedures To create a digital bus stimulus 1 From the Stimulus menu choose New 2 In the Digital frame choose Bus 3 Ifneeded change the bus width from its default value of 8 bits To do this in the Width text box type a different integer 4 Click OK During any interval the bits on the bus lines represent a value from zero through 2 1 where n is t
30. 106 breakout 105 C capacitor 104 CBREAK capacitor 105 CD4000_PWR digital power 115 creating for models custom parts 175 using the Model Editor 173 CVAR capacitor 104 D diode 104 DBREAK diode 105 DIGCLOCK digital stimulus 119 DIGIFPWR digital power 115 Index DIGSTIM digital stimulus 119 ECL_100K_PWR digital power 115 ECL_10K_PWR digital power 115 EGND ground 124 FILESTIM digital stimulus 119 finding 102 IAC AC stimulus 325 ICn initial conditions 544 IDC DC stimulus 114 310 IO_LEVEL property 189 ISRC analog stimulus 114 310 325 ISTIM transient stimulus 117 JBREAK JFET 105 K_LINEAR transformer 104 KBREAK inductor coupling 105 KCOUPLEn coupled transmission line 104 LBREAK inductor 105 MBREAK MOSFET 105 MNTYMXDLY property 190 MODEL property 180 NODESETn 544 PARAM global parameter 107 passive 104 PSPICEDEFAULTNET properties 191 QBREAK bipolar transistor 105 R resistor 104 RBREAK resistor 105 RVAR resistor 104 SBREAK voltage controlled switch 105 STIMn digital stimulus 119 T ideal transmission line 104 TBREAK transmission line 105 TEMPLATE property 182 TLOSSY Lossy transmission line 104 TnCOUPLEDx coupled transmission line 104 unmodeled 120 VAC AC stimulus 116 325 VDC DC stimulus 114 116 vendor supplied 101 VEXP transient stimulus 116 VPULSE transient st
31. 154 1 n 1 1 to i i 1 1 i 1 o i i 1 F ag i 1 1 5 oi i a i i mo 4 i p fi 1 1 a4 i I 1 e 1 1 s i 1 i ji i fi 1 r r l 8 4K 8 8K 9 2K 9 6K 16 6K 10 4K 10 8K CenterFreq YDBCOUT 13 n samples 166 sigma 265 376 median 9987 8 n divisions 20 minimum 9109 8 96th gile 180242 5 mean 9955 4 16th Zile 9537 52 maximun 180354 9 Figure 85 Center frequency histogram Worst case analysis This section discusses the analog worst case analysis feature of PSpice A D The information provided in this section explains how to use worst case analysis properly and with realistic expectations Overview of worst case analysis Worst case analysis is used to find the worst probable output of a circuit or system given the restricted variance of its parameters For instance if the values of R1 R2 and R3 can vary by 10 then the worst case analysis attempts to find the combination of possible resistor values which result in the worst simulated output As with any other analysis there are three important parts inputs procedure and outputs Inputs In addition to the circuit description you need to provide two pieces of information e the parameter tolerances e a definition of what worst means You can set tolerances on any number of the parameters that characterize a model The criterion for determining the worst values for the relevant model parameters is defi
32. Analyses you can run with PSpice A D on page 1 43 introduces the different kinds of basic and advanced analyses that PSpice A D supports Using PSpice A D with other OrCAD programs on page 1 49 presents the high level simulation design flow Files needed for simulation on page 1 50 describes the files used to pass information between OrCAD programs This section also introduces the things you can do to customize where and how PSpice A D finds simulation information Files that PSpice A D generates on page 1 54 describes the files that contain simulation results Chapter 1 Things you need to know Because the analog and digital simulation algorithms are built into the same program PSpice A D simulates mixed signal circuits with no performance degradation because of tightly coupled feedback loops between the analog and digital sections The range of models built into PSpice A D indude not only those for resistors inductors capacitors and bipolar transistors but also these e transmission line models including delay reflection loss dispersion and crosstalk e nonlinear magnetic core models including saturation and hysteresis e six MOSFET models including BSIM3 version 3 1 and EKV version 2 6 e five GaAsFET models including Parker Skellern and TriQuint s TOM2 model e IGBTs e digital components with analog 0 models 42 What is PSpice A D OrCAD PSpice A D is a simulation program that mo
33. Claude S Active Network Design with Signal Filtering Applications Steward amp Sons 1977 Stephenson F W ed RC Active Filter Design Handbook Wiley 1985 Van Valkenburg M E Analog Filter Design Holt Rinehart amp Winston 1982 Williams A B Electronic Filter Design Handbook McGraw Hill 1981 1 2kHz 2 les Booz 0 1dE 50dB Figure 35 LOPASS filter example 203 Chapter 6 Analog behavioral modeling band cutoff of 1 2 kHz The pass band ripple is 0 1 dB and the minimum stop band attenuation is 50 dB Assuming that the input to the filter is the voltage at net 10 and output is a voltage between nets 5 and 0 this will produce a PSpice A D netlist declaration like this ELOWPASS 5 0 CHEBYSHEV V 10 LP 800 1 2K 1dB 50dB HIPASS FS stop band frequency FP pass band frequency RIPPLE pass band ripple in dB STOP stop band attenuation in dB The HIPASS part is characterized by two cutoff frequencies that delineate the boundaries of the filter pass band and stop band The attenuation values RIPPLE and STOP define the maximum allowable attenuation in the pass band and the minimum required attenuation in the stop band respectively The HIPASS part provides one input and one output Figure 36 shows an example of a HIPASS filter device Then This is a high pass filter with the pass band above 1 2 kHz D 1AE Oe and the stop band below 800 Hz Again the pass band Figure 36 HIPAS
34. D_HI QA_BUF D_NC D_393_1 IO_STD MNTYMXDLY MNTYMXDLY IOQ_LEVEL IO_LEVEL U2 jkff 1 DPWR DGND D_HI CLRBAR QA_BUF D_HI D_HI QB_BUF D_NC D_393_2 IO_STD MNTYMXDLY MNTYMXDLY U3 jkff 1 DPWR DGND D_HI CLRBAR QB_BUF D_HI D_HI QC_BUF D_NC D_393_2 IO_STD MNTYMXDLY MNTYMXDLY U4 jkff 1 DPWR DGND D_HI CLRBAR QC_BUF D_HI D_HI QD_BUF D_NC D_393_3 IO_STD MNTYMXDLY MNTYMXDLY 249 Chapter 7 Digital device modeling 250 UBUFF bufa 4 DPWR DGND QA BUF QB_BUF QC_BUF QD_BUF QA QB QC QD D_393_4 IO0_STD MNTYMXDLY MNTYMXDLY JO_LEVEL IO_LEVEL ends When adding digital parts to the part libraries you must create corresponding digital device models by connecting U devices in a subcircuit definition similar to the one shown above OrCAD recommends you save these in your own custom model library which you can then configure for use with a given design Timing characteristics Timing characteristics A digital device model s timing behavior can be defined in one of two ways e Most primitives have an associated Timing model in which propagation delays and timing constraints such as setup hold times are specified This method is used when it is easy to partition delays among individual primitives typically when the number of primitives is small e Use the PINDLY and CONSTRAINT primitives which can directly model pin to pin delays and timing constraints fo
35. Drain terminal V B11 D G Gate terminal ID B11 S Source terminal Junction FET J D Drain terminal VG FET G Gate terminal I JFET G S Source terminal 296 Setting up analyses Table8 Element definitions for 3 or 4 terminal devices lt out id gt or lt out snd Output variable Device type device lt P id gt examples device indicator MOSFET M B Bulk substrate VDG M1 terminal ID M1 D Drain terminal G Gate terminal S Source terminal bipolar Q B Base terminal V Q1 B transistor C Collector terminal I Q1 C E Emitter terminal S Source terminal IGBT Z C Collector terminal V Z1 C Note The IGBT device type is RAIA E Emitter terminal I Z1 C not supported in PSpice A D f G Gate terminal Basics L Table9 Element definitions for transmission line devices lt out id gt or i i Output variable Device type lt out device gt lt z gt bee ates examples device indicator transmission T A Port A V T32 A line B PortB 1 T32 B 297 Chapter 8 Setting up analyses and starting simulation Table 10 Element definitions for AC analysis specific elements lt ac suffix gt Output variable device symbol Meaning examples none magnitude default V V1 I V1 M magnitude VM CAP1 1 IM CAP1 1 DB magnitude in decibels VDB R1 phase IP R1 R real part VR R1 I imaginary part VI R1 The INOISE ONOISE DB INOISE and DB ONOISE output variables are
36. Esqroot H OJT H OJT 5y SO Figure 49 EVA Evalue AT VES6ING S6IN 3 LUE part example Gpsk H OUT N OUT Gvalue 15ma SIN 6 28 1 0KHz TIME 96 IN IN Figure 50 GVALUE part example 223 Chapter 6 Analog behavioral modeling expression This is the PSpice A D internal sweep variable used in transient analyses For any analysis other than transient TIME 0 The relevant property settings for this device are shown below EXPR 15ma SIN 6 28 10kHz T IME V ZIN ZIN EMULT GMULT ESUM and GSUM The EMULT and GMULT parts provide output which is based on the product of two input sources The ESUM and GSUM parts provide output which is based on the sum of two input sources The complete transfer function may also include other mathematical expressions Example 1 i Epwr Consider the device in Figure 51 This device computes ECON um the instantaneous power by multiplying the voltage across pins IN and IN by the current through a a VSENSE This device s behavior is built in to the Sun o property as follows appears on one ine TEMPLATE E REFDES OUT ZOUT VALUE V IN1 IN1 V IN2 IN2 Figure 51 EMULT part example You can use the part editor to change the characteristics of the template to accommodate additional mathematical functions or to change the nature of the transfer function itself Fo
37. The message PSpice puts into the output file specifies which condition occurred Skipping the bias point The SKIPBP option for the transient analysis skips the bias point calculation In this case the transient analysis has no known solution to start from and therefore is not assured of converging at the first time point Because of this its use is not recommended It inclusion in PSpice is to maintain compatibility with UC Berkeley SPICE SKIPBP has the same meaning as UIC in Berkeley SPICE UIC is not needed in order to specify initial conditions The dynamic range of TIME TIME the simulation time during transient analysis is a double precision variable which gives it about 15 digits of accuracy The dynamic range is set to be 15 digits minus the number of digits of accuracy required by RELTOL For a default value of RELTOL 001 1 or 3 digits this gives 15 3 12 digits This means that the minimum time step is the overall run time TSTOP divided by 1e12 The dynamic range is large but finite It is possible to exceed this dynamic range in some circuits Consider for example a timer circuit which charges up a 100uF capacitor to provide a delay of 100 seconds At a certain threshold a comparator turns on a power MOSFET The overall simulation time is 100 seconds For default RELTOL this gives us a minimum time step of 100 picoseconds If the comparator and other circuitry has portions that switch in a nanosecond then PSpi
38. The strongest driver determines the resulting level of the node If outputs of the same strength but different levels drive a node the node s level becomes X PSpice A D supports 64 strengths The lowest weakest strength is called Z The highest strongest strength is called the forcing strength The Z strength called high impedance is typically output by disabled tristate gates or open collector output devices PSpice A D reports any nodes of Z strength at any level as Z and reports all other nodes by the designations shown in Digital states on page 14 411 Defining a digital stimulus Defining a digital stimulus A digital stimulus defines input to the digital portions of your circuit playing a role similar to that played by the independent voltage and current sources for the analog portion of your circuit The following table summarizes the digital stimuli provided in the part libraries Table 2 If you want to specify Then use this For this type of digital the input signal by part input Using the DIGSTIM signal or bus AWA Note The Stimulus Editor is Stimulus Editor stimulus AA not induded in PSpice A D Defining part DIGCLOCK clock signal J tass properties STIM1 one bit stimulus STIM4 four bit stimulus STIM8 eight bit stimulus STIM16 sixteen bit stimulus FILESTIM1 one bit file based stimulus FILESTIM2 two bit file based stimulus FILESTIM4 four bit file based stimulus FILESTIM8 eight bit file bas
39. boolean variable boolean expression The curly braces are required In the 74160 model the boolean expressions are actually reference functions There are three reference functions available CHANGED CHANGED_LH and CHANGED_HL The format is function name node delta time For our example we define the variable CLOCK as a logical TRUE if there has been a LO to HI transition of the CLK signal at simulation time We define CNTENT as TRUE if there has been any transition of the ENT signal at the simulation time Boolean operators take the following boolean values as operands e reference functions e transition functions e previously assigned boolean variables e boolean constants TRUE and FALSE Transition functions have the general form of TRN_pn For a complete list of reference functions and transition functions see the Digital Devices chapter in the online OrCAD PSpice A D Reference Manual Creating a digital model using the PINDLY and LOGICEXP primitives PINDLY PINDLY contains the actual delay and constraint expressions for each of the outputs The CASE function defines a more complex rule based lt delay expression gt and works as a rule section mechanism for establishing path delays Each boolean expression in the CASE function is evaluated in order until one is encountered that produces a TRUE result Once a TRUE expression is found the delay expression portion of the rule is associated with the output
40. choose Save to save the design AC sweep analysis results PSpice displays the dB magnitude 20log10 of the voltage at the marked nets Out and Mid in a Probe window as shown in Figure 20 below VDB Mid has a lowpass response due to the diode capacitances to ground The output capacitance and load resistor act as a highpass filter so the overall response illustrated by VDB out is a bandpass response Because AC is a linear analysis and the input voltage was set to 1V the output voltage is the same as the gain or attenuation of the circuit 79 Chapter 2 Simulation examples 1 OKHZ 16KHZ 100KHZ 1 6MHZ 10MHz 100HHz Frequency fi Bisioper SCHE gure 20 dB magnitude curves for gain at Mid and Out To display a Bode plot of the output voltage including phase Note Depending upon where the Vphase 1l marker was placed the trace name may be different such as VP Cout 2 VP R4 1 or gt VP R4 2 For more information on Probe windows and trace expressions see Chapter 17 Analyzing waveforms 5 press Ctrl X ra 6 7 8 press Ctrl V 80 From Capture s PSpice menu point to Markers point to Advanced and choose Phase of Voltage Place a Vphase marker on the output next to the Vdb marker Delete the Vdb marker on Mid Switch to PSpice In the Probe window the gain and phase plots both appear on the same graph with the same s
41. device letter BBREAK GaAsFET B CBREAK capacitor C DBREAKx diode D JBREAKx JFET J KBREAK inductor coupling K LBREAK inductor L MBREAKx MOSFET M QBREAKx bipolar transistor Q RBREAK resistor R SBREAK voltage controlled S switch TBREAK transmission line T WBREAK current controlled W switch XFRM_NONLINEAR transformer Kand L ZBREAKN IGBT Z For this device type the OrCAD libraries supply several breakout parts Refer to the online OrCA D PSpice A D Reference Manual for the available parts Using parts that you can simulate To find out more about models see What are models on page 4 129 To find out more about Monte Carlo and sensitivity worst case analyses see Chapter 13 Monte Carlo and sensitivity worst case analyses To find out more about setting temperature parameters see the A nalog Devices chapter in the online OrCA D PS pice A D Reference Manual andfind the device type that you are interested in To find out more about how to use these parts and define their properties look up the corresponding PSpice device letter in the Analog Devices chapter of the online OrCA D PSpice A D Reference Manual and then look in the Capture Parts section 105 Chapter 3 Preparing a design for simulation For more information see Chapter 6 Analog behavioral modeling For more information see e Chapter 7 Digital device modeling e the Digital Devices chapter in the online OrCA D PSpice A D Re
42. e Dbreak D1 diode e C C1 capacitor e R R1 resistor e VSIN V1 sine wave source Click the Ground button and place the analog ground From the Place menu choose Wire and draw the connections between parts as shown in Figure 30 From the File menu choose Save If you were to simulate this design using a transient analysis you would also need to set up a transient specification for V1 most likely this would mean defining the VOFF offset voltage VAMPL amplitude and FREQ frequency properties for V1 For this tutorial however you will not perform a simulation so you can skip this step Using the Model Editor to edit the D1 diode model To create a new model and model library 1 Inthe Model Editor from the Model menu choose New 2 Inthe New dialog box do the following a Inthe Model text box type Dbreakx b From the From Model list select Diode Click OK 3 From the File menu choose Save As 4 Inthe File name text box type rect fr 1ib to save the library as RECTFR LIB Entering data sheet information As shown in Figure 31 the Model Editor initially displays e diode model characteristics listed in the Models List frame and e DbreakX model parameter values listed in the Parameters frame 24 ModelLib1 lib Dbreakx OrCAD Model Editor Forward Current Gi Fie Edt View Model Plot Tools Window Help 218 x olsjalsja me eee WE ef ef Model Name Type Forward C
43. parameters You can define the behavior for a device that is based on a built in model by setting all or any of the corresponding model parameters to new values using the PSpice MODEL syntax For example MODEL MLOAD NMOS LEVEL 1 VT0 0 7 CJ 0 02pF Models defined as subdrauit netlists For some devices there are no PSpice A D built in models that can describe their behavior fully These types of devices are defined using the PSpice SUBCKT ENDS or subcircuit syntax instead Subcircuit syntax includes e Netlists to describe the structure and function of the part e Variable input parameters to fine tune the model For example What are models In addition to the analog models built in to PSpice A D the MODEL syntax applies to the timing and I O characteristics of digital parts To find out more about PSpice A D command and netlist syntax refer to the online OrCA D PSpice A D Reference Manual 129 Chapter 4 Creating and editing models You can use the OrCAD Model Editor or any standard text editor to view model definitions in the libraries For example MOTOR_ RF LIB contains models for Motorola made RF bipolar transistors 130 FIRST ORDER RC STAGE SUBCKT LIN STG IN OUT AGND PARAMS CIVAL 1 C2VAL 1 RIVAL 1 R2VAL 1 GAIN 10000 C1 I N1 CIVAL C2 N1 OUT C2VAL R1 I N1 RIVAL R2 N1 OUT R2VAL EAMP1 OUT AGND VALUE V AGND N1 GAIN ENDS Sa aS How are models organi
44. real part of x IMG x imaginary part which is applicable to of x AC analysis only Using global parameters and expressions for values 111 Chapter 3 Preparing a design for simulation Note In waveform analysis this function is D x Note In waveform analysis this function is s x Example v 1 STP TIME 10ns gives a value of 0 0 until 10 nsec has elapsed then gives v 1 112 Table 10 Functions in arithmetic expressions continued This function Means this DDT x time derivative which is applicable to of x transient analysis only SDT x time integral of x which is applicable to TABLE x x1 y1 y value as a function of x MIN x y minimum of x and y MAX x y maximum of x and y LIMIT x min max min if x lt min max if x gt max else x SGN x 1ifx gt 0 Oifx 0 lifx lt 0 STP x lifx gt 0 0 otherwise IF t x y x if tis true y otherwise transient analysis only where X Yp point pairs are plotted and connected by straight lines which is used to suppress a value until a given amount of time has passed where t is a relational expression using the relational operators shown in Table 9 M x P x R x and IMG x apply to Laplace expressions only Table1l System variables This variable Evaluates to this TEMP TIME Temperature values resulting from a temperature parametric temperature or DC temperature sweep analysis The def
45. sitsw 5 5ns sirlo 467 sirhi 200 s2name R s2vlo 0 8 s2vhi 1 4 s2name X s2tsw 3 5ns_ s2rlo 42 9 s2rhi 116 s8name R s3vlo 1 3 s3vhi 2 0 s3name R s3tsw 3 5ns srlo 42 9 s3rhi 116 s4name X s4vlo 0 8 s4vhi 2 0 s4name F s4tsw 3 5ns s4rlo 42 9 s4rhi 116 sSname 1 s5vlo 2 0 s5vhi 7 0 s5name Z sStsw 3 5ns s5Srlo 200K s5rhi 200K s6name F s6vlo 1 3 s6vhi 2 0 s7name F s7vlo 0 8 s7vhi 1 4 Figure 55 Elements of a digital device definition Functional behavior 247 Chapter 7 Digital device modeling This type of Timing model and its parameters are specific to each primitive type and are discussed in the online OrCA D PSpice A D Reference Manual See Input Output model on page 7 257 for more information 248 automatically inserts an interface subcircuit to translate between digital output states and voltages lt Timing model name gt is the name of a timing model that describes the device s timing characteristics such as propagation delay and setup and hold times Each timing parameter has a minimum typical and maximum value which may be selected during analysis setup lt I O model name gt is the name of anI O model that describes the device s loading and driving characteristics I O models also contain the names of up to four DtoA and AtoD interface subcircuits which are automatically called by PSpice A D to handle analog digital interface nodes MNTYMXDLY is an optio
46. standard method of using Laplace transforms We recommend looking at one or more of the references cited in Frequency domain device models on page 6 227 for more information Example The input to the Laplace transform is the voltage across the input pins or V IN IN The EXPR property may be edited to include constants or functions as with other parts The transform 1 1 001 s describes a simple lossy integrator with a time constant of 1 millisecond This can be implemented with an RC pair that has a time constant of 1 millisecond Using the part editor you would define the XFORM and EXPR properties as follows XFORM 1 1 001 s EXPR V ZIN IN The default template remains appears on one line TEMPLATE E REFDES ZOUT 0UT LAPLACE EXPR XFORM After netlist substitution of the template the resulting transfer function would become V OUT BOUT LAPLACE V IN IN 1 1 001 s The output is a voltage and is applied between pins OUT and OUT For DC the output is simply equal to the input since the gain at s O is 1 For AC analysis the gain is found by substituting j for s This gives a flat response out to a corner frequency of 1000 27 159 Hz and a roll off of 6 dB per octave after 159 Hz There is also a phase shift centered around 159 Hz In other words the gain has both a real and an imaginary component The gain and phase characteristic is the same as that shown fo
47. traretet Dg 3 tererter a circuit file for profile Bias iid SMALL SIGNAL BIAS SOLUTION TEMPERATURE 27 000 DEG C TELELELLLLLLLLLLLLLLLLLLEELLLLLE LLL ELLE EEL NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE IN 0 0000 OUT 0 0000 YCC 5 0000 NW00744 9434 VOLTAGE SOURCE CURRENTS NAE CURRENT vyl 1 229E 03 Vin 9 434 04 TOTAL POWER DISSIPATION 6 15E 03 WATTS v al E clpper SCH Figure Simulation output file 2 When finished close the window Running PSpice A D PSpice A D measures the current through a two terminal device into the first terminal and out of the second terminal For voltage sources current is measured from the positive terminal to the negative terminal this is opposite to the positive current flow convention and results in a negative value in the output file Finding out more about bias point calculations Table 2 1 To find out more about this See this bias point calculations Bias point on page 9 315 65 Chapter 2 Simulation examples Note The default settings for DC Sweep simulation are Voltage Source as the swept variable type and Linear as the sweep type To use a different swept variable type or sweep type choose different options under Sweep variable and Sweep type 66 DC sweep analysis You can visually verify the DC response of the clipper by performing a DC sweep of the input voltage source and displaying the waveform results in the Probe window in PS
48. 1 2 Note 4 5 Place a PARAM part in your design Double click the PARAM part to display the Parts spreadsheet then click New Declare up to three global parameters by doing the following for each global parameter a Click New 0 Inthe Property Name text box enter NAMEN then click OK This creates a new property for the PARAM part NAME in the spreadsheet Click in the cell below the NAMEn column and enter a default value for the parameter d While this cell is still selected click Display e Inthe Display Format frame select Name and Value then click OK The system variables in Table 11 on page 3 113 have reserved parameter names Do not use these parameter names when defining your own parameters Click Apply to update all the changes to the PARAM part Close the Parts spreadsheet To use the global parameter in your circuit 1 Find the numeric value that you want to replace a component value model parameter value or other property value Replace the value with the name of the global parameter using the following syntax global_parameter_name The curly braces tell PSpice A D to evaluate the parameter and use its value Expressions An expression is a mathematical relationship that you can use to define a numeric or boolean TRUE FALSE value PSpice A D evaluates the expression to a single value every time e itreads in anew circuit and e a parameter value used within
49. 162 The Libraries and Include Filestabs 0 162 How PSpice A D uses model libraries 163 Search ordet 2 og eo ae oe ae oe Ee ee ER 163 Handling duplicate modelnames 164 Adding model libraries to the configuration 164 Changing design and global scope 0 456 165 Changing model library search order 4 166 Changing the library search path 1 0040 167 Chapter 5 Creating parts for models 169 Chapter overview tio acts secot berie Reed ga Hee Ea e eA 169 What s different about parts used for simulation 171 Ways to create parts f r models oie arsa m e ae a a ee ed aed ee ee 171 Preparing your models for part creation 172 Using the Model Editor to create parts 2 173 Starting the Model Editor sate soe e eee eee eS 173 Setting up automatic part creation 004 174 Basing new parts on a custom set of parts 175 Editing part graphics aoaaa a 177 vii Contents Chapter 6 viii How Capture places parts si 66 8 sees ese wee eee eH E 177 Defining grid spacing ae sacks ee a Re OA Ee 178 Grid spacing for graphics 44 24 4 24 ee Oe ee os 178 Grid spacing for pins 4 4 aa A 44 se RAS Re bee ee eS 178 Attaching models to parts 4 4 0622244944202 2244 ER4 dees 180 MODEL srs eons oS o e Bee Bois Ph oa Oe ee a 180 Defining part properties
50. 20NS CLOCK amp LOADBAR 1 amp TRN_LH DELAY 1 13NS 20NS CLOCK amp LOADBAR 1 amp TRN_HL DELAY 1 15NS 23NS CLOCK amp LOADBAR 0 amp TRN_LH DELAY 1 17NS 25NS CLOCK amp LOADBAR 0 amp TRN_HL DELAY 1 19NS 29NS UP_HOLD LOADBAR CLK 25NS LRBAR 0 CLRBAR CLK E_LH 20NS Creating a digital model using the PINDLY and LOGICEXP primitives 283 Chapter 7 Digital device modeling 284 Part three Setting Up and Running Analyses Part Three describes how to set up and run analyses and provides setup information specific to each analysis type e Chapter 8 Setting up analyses and starting simulation explains the procedures general to all analysis types to set up and start the simulation e Chapter 9 DC analyses describes how to set up DC analyses including DC sweep bias point detail small signal DC transfer and DC sensitivity e Chapter 10 AC analyses describes how to set up AC sweep and noise analyses e Chapter 11 Transient analysis describes how to set up transient analysis and optionally Fourier components This chapter also explains how to use the Stimulus Editor to create time based input e Chapter 12 Parametric and temperature analysis describes how to set up parametric and temperature analyses and how to run post simulation performance analysis in Probe on the results of these analyses Chapt
51. 39 analog and 134 digital parts displays only simulation data created using the demo version of the simulator PSpice Optimizer limited to one goal one parameter and one constraint designs created in Capture can be saved if they have no more than 30 part instances XXXV Before you begin To find out more see Analyzing waveforms on page 475 xxxvi What s New New PSpice interface with integrated waveform analysis functionality Release 9 of PSpice A D includes all of Probe s features and adds to them Included in one screen are tabbed windows for viewing plots text windows for viewing output files or other text files and a simulation status and message window Also included is anew self documenting analysis setup dialog for creating simulation profiles see below PSpice A D now provides an editable simulation queue which shows you how many files are currently in line to be simulated You can edit or re order the list as needed And the plotting features have been improved by providing user controlled grid settings grid and trace properties style and color and metafile format copy and paste functions Simulation profiles PSpice A D Release 9 introduces the concept of simulation profiles Each simulation profile refers to one schematic in a design and includes one analysis type AC DC or Transient with any options sensitivity temperature parametric Monte Carlo etc You can define as many profiles as you ne
52. 49 viewing in progress output values 534 waveform data file DAT 54 PSPICE INI file editing 480 PSPICEDEFAULTNET properties 191 R real part 524 regulator 137 RELTOL simulation option 238 resistors 296 527 S schematic page editor starting other tools from Model Editor 143 153 154 scrolling Probe windows 507 semiconductor problems 553 shot noise 337 simulation about 42 analysis execution order 291 setup 289 types 288 batch jobs 300 bias point 542 failure to start 98 initial conditions 542 546 messages 437 output file OUT 64 setup checklist 96 starting 299 status window 301 troubleshooting checklist 98 simulation control parts 100 ICn 544 NODESETn initial conditions 544 PARAM 107 small signal DC transfer analysis 288 317 introduction 43 STARTVAL stimulus property digital 422 states digital 262 411 Index STIMn digital stimulus parts 119 422 Stimulus Editor 73 346 about 49 creating new stimulus parts 352 defining analog stimuli 117 defining digital inputs 414 defining stimuli 349 editing a stimulus 353 manual stimulus configuration 354 starting 347 stimulus files 346 347 stimulus files 51 configuring 53 162 stimulus generation 344 manually configuring 354 stimulus adding 73 AC sweep 325 bus transitions digital 417 clock transitions digital 414 DC sweep 310 for multiple analysis types 118 loops digital 420 signal tra
53. An AC Sweep analysis is a linear or small signal analysis This means that nonlinear devices must be linearized to run the analysis What s required to transform a device into a linear drait In order to transform a device such as a transistor amplifier into a linear circuit you must do the following 1 Compute the DC bias point for the circuit 2 Compute the complex impedance and or transconductance values for each device at this bias point 3 Perform the linear circuit analysis at the frequencies of interest by using simplifying approximations What PSpice A D does PSpice A D automates this process for you PSpice A D computes the partial derivatives for nonlinear devices at the bias point and uses these to perform small signal analysis Example nonlinear behavioral modeling block Suppose you have an analog behavioral modeling block that multiplies V 1 by V 2 Multiplication is a nonlinear operation To run an AC sweep analysis on this block the block needs to be replaced with its linear equivalent To determine the linear equivalent block PSpice A D needs a known bias point AC sweep analysis Example Replace a bipolar transistor in common emitter mode with a constant transconductance collector current proportional to base emitter voltage and a number of constant impedances 331 Chapter 10 AC analyses Int of Out In2 V1 FN V2 DC 0V pc 2v ACMAG 1V A Th
54. Close the opened model library 2 Open a new model library 3 Load a device model or create a new one 173 Chapter 5 Creating parts for models Instead of using the OrCAD default part set you can use your own set of standard parts To find out more see Basing new parts on a custom set of parts on page 5 175 For example if the model library is named MYPARTS LIB then the Model Editor creates the part library named MYPARTS OLB 174 Setting up automatic part creation Part creation from the Model Editor is optional By default automatic part creation is enabled However if you previously disabled part creation you need to enable it before creating a new model and part To automatically create parts for new models 1 Inthe Model Editor from the Tools menu choose Options 2 Inthe Part Creation Setup frame select Create Parts for Models if it is not already enabled 3 In the Save Part To frame define the name of the part library for the new part Choose one of the following e Part library path same as model library to create or open the OLB file that has the same filename as the open model library LIB e User defined part library and then enter a library name in the part Library Name text box Basing new parts on a custom set of parts Basing new parts ona custom set of parts If you are using the the Model Editor to automatically generate parts for model definitions and you want to base t
55. Current at a different temperature 1 Inthe Spec Entry frame click the Forward Current tab 2 From the Plot menu choose Add Trace 3 Type 100 in C 4 Click OK The Forward Current plot should appear as shown in Figure 33 below Using the Model Editor to edit models 6 2U 6 5U 1 6U 1 4U o Ifwd 27 C Ifwd 166 C Forward Voltage Figure 33 Forward Current device curve at two temperatures Completing the model definition You can refine the model definition by e modifying the entered data as described before or e editing model parameters directly You can update individual model parameters by editing them in the Parameters frame of the Model Editor workspace When you save the model library the Model Editor automatically updates the device curves For this tutorial leave the model parameters at their current settings To save the model definition with the current parameter values and to make the model available to your design 1 From the File menu select Save to update RECTFR LIB and save the library to disk Your design is ready to simulate with the model definition you just created 151 Chapter 4 Creating and editing models Caution If you edit the text of a model that was created by entering data sheet values you may not be able to edit the model in Normal view again To find out more about PSpice A D command and netlist syntax refer to the online OrCA D PSpice A D Reference Manual
56. D Basics N A subcircuit sometimes called a macromodel is analogous to a procedure call in a software programming language See What is the Model Editor on page 1 50 for a description 52 You can create these files using OrCAD programs like the Stimulus Editor and the Model Editor These programs automate file generation and provide graphical ways to verify the data You can also use the Model Text view in the Model Editor or another text editor like Notepad to enter the data manually Model library A model library is a file that contains the electrical definition of one or more parts PSpice A D uses this information to determine how a part will respond to different electrical inputs These definitions take the form of either a e model parameter set which defines the behavior of a part by fine tuning the underlying model built into PSpice A D or e subcircuit netlist which describes the structure and function of the part by interconnecting other parts and primitives The most commonly used models are available in the OrCAD model libraries shipped with your programs The model library names have a LIB extension If needed however you can create your own models and libraries either e manually using the Model Text view in the Model Editor or another text editor like Notepad or e automatically using the Model Editor Stimulus file A stimulus file contains time based definitions for analog and
57. D Capture User s Guide 122 Check for this if the part in question is custom built Are there blank or inappropriate values for the part s Implementation and PSPICETEMPLATE properties If so load this part into the part editor and set these properties appropriately One way to approach this is to edit the part that appears in your design To edit the properties for the part in question 1 Inthe schematic page editor select the part 2 From the Edit menu choose Part The part editor window appears with the part already loaded 3 From the Edit menu choose Properties and proceed to change the property values Unconfigured model stimulus or include files If you see messages like these in the PSpice Simulation Output window design_name Floating pin refdes pin pin_name Floating pin pin_id File not found Can t open stimulus file or messages like these in the PSpice output file Model model_name used by device_name is Subcircuit subckt_name used by device_name is undefined Can t find STIMULUS refdes definition then you may be missing a model library stimulus file or include file from the configuration list or the configured file is not on the library path Things to watch for Check for this e Does the relevant model library stimulus file or include file appear in the configuration list e If the file is configured does the default library search path include the directory
58. DIGDRVF is 2 ohms The larger the range between DIGDRVZ and DIGDRVF the larger the range of impedance values in each of the 64 strengths Determining the strength of a device output The simulator uses the value of the DRVH high level driving resistance or DRVL low level driving resistance parameters from the device s I O model If the level of the output is a 1 the simulator obtains the strength by finding the bin which contains the value of the DRVH parameter Likewise if the level is a 0 the simulator uses the value of the DRVL parameter to obtain the strength Input Output characteristics You can set these options in the Simulation Settings dialog box in PSpice A D See Input Output model on page 7 257 for more information Output Output Output Output Drive Strength Drive Strength DIGDRVF 63 DIGDRVF 63 Higher Level 1 Level0 Higher Strength DRVH Strength DRVL Strength Impedance DIGDRVZ 0 DIGDRVZ 0 Figure 56 Level 1 and 0 strength determination 263 Chapter 7 Digital device modeling You can set these options in the Simulation Settings dialog box in PSpice A D 264 Note that if the values of DRVH and DRVL in the I O model are different it is possible for the 1 and 0 levels to have different strengths This is useful for open collector devices where the 0 level is at a higher strength than the 1 level which drives at the Z strength Drive impedances w
59. ELAPLACE GLAPLACE EFREQ and GFREQ are characterized by output that depends on the current input as well as the input history The relationship is therefore non instantaneous For example the output may be equal to the integral of the input over time In other words the response depends upon frequency During AC analysis the frequency response determines the complex gain at each frequency During DC analysis and bias point calculation the gain is the zero frequency response During transient analysis the output of the device is the convolution of the input and the impulse response of the device Laplace transforms LAPLACE The ELAPLACE and GLAPLACE parts allow a transfer function to be described by a Laplace transform function The ELAPLACE and GLAPLACE parts are defined in part by the following properties default values are shown ELAPLACE EXPR V IN IN XFORM 1 s GLAPLACE EXPR V IN IN XFORM 1 s The LAPLACE parts use a Laplace transform description The input to the transform is the value of EXPR where EXPR follows the same rules as for VALUE expressions see EVALUE and GVALUE parts on page 6 222 XFORM is an expression in the Laplace variable s It follows the rules for standard expressions as described for VALUE expressions with the addition of the s variable PSpice A D equivalent parts Moving back and forth between the time and frequency domains can cause surprising results Often the results ar
60. EMULT partexample gt s 2 kc deh keke EE SEARS Re hw oE 224 GMULT part example so sev dan eset ooo eee gee oe 225 EFREQ patlexample se 0 4c 8 oe ee dS See ee eee kEi 231 Voltage multiplier circuit mixer 2646 8in decd be edew wees 232 Elements of a digital device definition 247 Level 1 and 0 strength determination 0 263 Popice A D simulation window lt 4 4 on 4 oes ek Le ee 303 Example schematic EXAMPLE OP 246 40 402444404 eee 4u 309 Curve family example schematic lt cices 6 u Vg Hee kd Bee ee RD 313 Device curve family oh 25 ASS EDeas Ree Hae ES See Ee Se 314 Operating point determination for each member of the curve family 314 Circuit diagram tor EXAMPLE OP 425 eae SAREE MASE 329 AC analysis setup for EXAMPLE OPJ 04 330 Device and total noise traces for EXAMPLE DSN 339 Transient analysis setup for EXAMPLE OPJ 356 Example schematic EXAMPLE OPJ 0 0 40 44 4452 8 oe whee o 357 ECL compatible Schmitt trigger 2 ee 359 Netlist for Schmitt trigger circuit ew a Ok ee eR 360 Hysteresis curve example Schmitt trigger 361 Passive filter schematic 0 a 366 Current of L1 when R1 is 1 5 ohms 0 000048 368 Rise time and overshoot vs damping resistance 369 RLC filter cxaMplecethes okato Saree setae oe be 4 370 Plot of capacitance versus bias voltage
61. GFREQ and are based on extensions to traditional PSpice A D E and G device types Implement ABM components by using PSpice A D primitives there is no corresponding abm 1ib model library A few components generate multi line netlist entries but most are implemented as single PSpice A D E or G device declarations See ABM part templates on page 6 198 for a description of PSPICETEMPLATE properties and their role in generating netlist declarations See Implementation of PSpice A D equivalent parts on page 6 221 for more information about PSpice A D E and G syntax The ABM OLB part library file 195 Chapter 6 Analog behavioral modeling The name of an interface port does not extend to any connected nets To refer to a signal originating at an interface port connect the port to an offpage connector of the desired name 196 Placing and specifying ABM parts Place and connect ABM parts the same way you place other parts After you place an ABM part you can edit the instance properties to customize the operational behavior of the part This is equivalent to defining an ABM expression describing how inputs are transformed into outputs The following sections describe the rules for specifying ABM expressions Net names and device names in ABM expressions In ABM expressions refer to signals by name This is also considerably more convenient than having to connect a wire froma pin on an ABM component to a point carrying the vol
62. Global buttons respectively The Stimulus tab contains stimulus files See Configuring stimulus files on page 11 347 for more information 162 Configuring model libraries Although model libraries are usually configured for you there are things that you sometimes must do yourself These are e adding new model libraries that were created outside of Capture or the Model Editor e changing the global or design scope of a model library e changing the library search order e changing or adding directory search paths The Libraries and Include Files tabs The Libraries and Include Files tabs of the Simulation Settings dialog box are where you can add change and remove model libraries and include files from the configuration or resequence the search order Note Removing a library in this dialog box means that you are removing the model library from the configured list The library still exists on your computer and you can add it back to the configuration later To display the Libraries tab 1 In PSpice A D from the Simulation menu choose Edit Simulation Settings 2 Click the Libraries tab The Library Files list shows the model libraries that PSpice A D searches for definitions matching the parts in your design Files showing an asterisk after their name have global scope files with names left unmarked have design scope The buttons for adding model libraries to the configuration follow the same local global s
63. IGBT 137 297 525 imaginary part 524 include files 51 configuring 53 162 with model definitions 163 inductors 295 problems 559 inertial delay 255 initial conditions 542 546 INLD I O model 258 input noise total 337 INR I O model 258 instance models and the Model Editor 143 154 changing model references 159 editing 145 reusing 160 saving for global use instead using the Model Editor 155 integrators ABM 199 206 interface subcircuits 266 444 456 and I O models 248 445 and power supplies 444 CAPACITANCE 266 customized 266 DRVH 266 DRVL 266 IO_LEVEL 246 N device digital input 266 O device digital output 266 syntax 266 IO_LEVEL interface subcircuit parameter 246 part property 189 stimulus property digital 423 IO_LEVEL property 189 IO_MODEL stimulus property digital 423 IPLOT write current plot part 535 IPRINT write current table part 536 ISRC stimulus part 114 310 325 ISTIM stimulus part 117 J JFET 137 296 525 526 L Laplace transform parts ABM 200 210 220 227 233 235 libraries configuring 162 footprint 53 model 130 package 53 part OLB 53 searching for models 163 see also model libraries Library List using the 103 limiters ABM 199 202 loading delay 254 LOGICEXP primitive 106 271 M magnetic core nonlinear 137 magnitude 524 markers 490 displaying traces 68 for limiting waveform data file s
64. O CAD Model Editor Eie Edt View Model Plot Tools Window Help Ofer Ba e Ree Mf elie Modeinane Type T Cieaion Date Craenen RAE Dbreak Diode 07 31 98 at ee Q2N22224 Z Forward Current f Reverse Leakage QANSISZTK BIT 4 Q2NE727 2TX BJT Toinclude this spec in the model To include this spec in the model M2N7000 2TX SUBCKT extraction please enter two or mote extraction please enter two of more M2N7002 2TX SUBCKT data points in the following table data points in the following table palzarany Diode e wwa mijd ea BASIGZTX Diode BAS19 ZTX Diode Junction Capacitance BASZNZTX Diode BAS2I ZTX Diode Toinclude this spec in the model BAVZO ZTX Diode E Reverse Breakdown extraction please enter two of more BAV 4 ZTX Diode data ponts in the folowing table BAVOIZTX BAWSEZZTX Diode WA BY31 ZTX BBYAUZTX Diod BCIOTBP ZTX BIT Reverse Recovery ol ina r i pea oll ion Ca Reverse Br fa Reverse Re Parameters A tive i 4 d A E E E i Ready T NONI Figure 32 Assorted device characteristic curves for a diode Adding aurves for more than one temperature By default the Model Editor computes device curves at 27 C For any characteristic you can add curves to the plot at other temperatures To add curves for Forward
65. Output variable formats Format Meaning Voltage variables V ac lt analog net gt lt analog net Voltage between gt and analog net ids V lt pin name gt ac lt device gt Voltage at pin name of a device 521 Chapter 17 Analyzing waveforms 522 Table6 Output variable formats continued Format Meaning V lt x gt ac lt 3 or 4 terminal device gt V lt z gt ac lt transmission line device gt Current variables I ac lt device gt I lt x gt ac lt 3 or 4 terminal device gt I lt z gt ac lt transmission line device gt Digital signal and bus variables lt digital net gt lt display name gt lt digital net gt lt display name gt lt radix gt Sweep variables lt DC sweep variable gt FREQUENCY TIME Voltage at non grounded terminal x of a 3 or 4 terminal device Voltage at end z of a transmission line device z is either A orB Current into a device Current into terminal x of a3 or 4 terminal device Current into end z of a transmission line device z is either A orB Digital state at digital net labeled as display name Digital bus labeled as display name and of specified radix name of any variable used in the DC sweep analysis AC analysis sweep variable transient analysis sweep variable Trace expressions Table6 Output variable formats continued Form
66. PARAM include most valid and FUNC definitions before the circuit They can Cancel Apply Help 347 Chapter 11 Transient analysis smallest usable increment example if it is set to 1 msec then you cannot add a data point at 1 5 msec 348 The Stimulus Editor utility Defining stimull See Chapter 14 Digital 1 simulation for detailed information Place stimulus part instances from the symbol set about creating digital stimuli VSTIM ISTIM and DIGSTIMn Click the source instance to select it From the Edit menu choose PSpice Stimulus to start the Stimulus Editor Fill in the transient specification according to the dialogs and prompts Piecewise linear and digital stimuli can be specified by direct manipulation of the input waveform display From the File menu choose Save to save the edits Example piecewise linear stimulus 1 2 Open an existing schematic or start a new one From the Place menu choose Part and browse the SOURCE OLB part library file for VSTIM and select it Place the part It looks like a regular voltage source with an implementation property displayed Click the implementation label and type vfirst This names the stimulus that you are going to create If you are working in a new schematic use Save from the File menu to save it This is necessary since the schematic name is used to create the default stimulus file name Click the VSTIM
67. PINDLY and LOGICEXP primitives taken directly from the actual data sheet This makes the delay modeling both easy and accurate Allof the above primitives and modeling methods as well as a few special cases that are not covered here can be found in the Digital Devices chapter of the online OrCA D PSpice A D Reference Manual 74160 Synchronous 4 bit Decade Counters with asynchronous clear Modeled using LOGICEXP SUBCKT 74160 CLK_I ENP_I C_I DI QA_O QB_O QC_O QD_O RCO PINDLY amp CONSTRAINT devices ENT_I CLRBAR_I LOADBAR_I A_I B_I 0 OPTIONAL DPWR G_DPWR PARAMS MNTYMXDLY 0 I0_ U160L0G LOGICEXP 14 20 D CLK_I ENP_I ENT_I CLRBA QDBAR QA QB QC QD CLK ENP ENT CLRBAR LOAD CLKBAR RCO JA JB JC JD DGND G_DGND LEVEL 0 PWR DGND R_I LOADBAR_I A_I B_I C_I D_I BAR A BC D A KB KC KD EN DO_GATE IO_STD IO_LEVEL TO_LEVEL LOGIC CLK _ CLRI Buffering ENP ENP_I ENT ENT_I CLRBAR CLRBAR_I LOADBAR LOADBAR_I A AT B BI Ao Gee Ca te D DEP F CLKBAR CLK Logic expressions LOAD LOADBAR EN ENP amp ENT 1A LOAD EN 2A LOAD amp A JA TIA amp LOAD amp I2A A I1A amp I2A F 1B QA amp EN amp QDBAR LOAD 2B LOAD amp B JB I1B amp LOAD amp 2B KB I1B amp 2B 1C QA amp EN amp QB
68. PSpice A D calaulates total output and input noise To calculate total noise at an output net PSpice A D computes the RMS sum of the noise propagated to the net by all noise generating devices in the circuit To calculate the equivalent input noise PSpice A D then divides total output noise by the gain from the input source to the output net This results in the amount of noise which if injected at the input source into a noiseless circuit would produce the total noise originally calculated for the output net Setting up a noise analysis To set up the noise analysis 1 From the PSpice menu choose New Simulation Profile or Edit Simulation Settings If this is a new simulation enter the name of the profile and click OK The Simulation Settings dialog box appears Simulation Settings AC Sweep General Analysis Include Files Libraries Stimulus Options Data Collection Probe window Analysis type fac Sweep Noise gt Options General Settings Monte Carlo worst Case Parametric Sweep Temperature Sweep Choose AC Sweep Noise in the Analysis type list box Under Options select General Settings if it is not already enabled AC Sweep Type Linear Start Frequency fi 00K Logarithmic End Frequency fi 0G Decade z Points Decade fi 0 r Noise Analysis V Enabled Dutput Voltage vOut IZY Source ir Interval fo x Cancel Apply Help
69. Stimulus Editor with the DIGSTIMn part see Defining clock transitions on page 14 414 422 Using the DIGCLOCK part The DIGCLOCK part allows you to define a clock signal by using the part s properties To define a clock signal using DIGCLOCK 1 From Capture s Place menu choose Part 2 Place and connect a DIGCLOCK part 3 Double click the part instance 4 Define the properties as described below Table 6 For this property Specify this DELAY Time before the first transition of the clock ONTIME Time in high state for each period OFFTIME Time in low state for each period STARTVAL Low state of clock default 0 OPPVAL High state of clock default 1 Using STIM1 STIM4 STIM8 and STIM16 parts The STIMzn parts have a single pin for connection STIM1 is used for driving a single net STIM4 STIM8 and STIM16 drive buses that are 4 8 and 16 bits wide respectively The properties for all of these parts are the same as those shown in Table 7 below Defining a digital stimulus Table STIMn part properties Property Description WIDTH Number of output signals nodes FORMAT Sequence of digits defining the number of signals corresponding to a digit in any lt value gt term appearing ina COMMANDnz property definition Each digit must be either 1 3 or 4 binary octal hexadecimal respectively the sum of all digits in FORMAT must equal WIDTH IO_MODEL I O model describing the stimulus drivin
70. The result in Figure 109 does not represent what is actually propagated at U2 and U3 but is a computation to determine that U2 must be stable at the earliest time U3 might change This is why an X level should not be latched In the event that discounting the common ambiguity does not preclude latching the X or in the case of simple gates predicting a glitch the situation is called a reconvergence hazard This is the same as a convergence hazard with the conflicting signal ambiguities having a common origin To use digital worst case simulation effectively find the areas of the circuit where signal timing is most critical and use constraint checkers where appropriate These devices identify specific timing violations taking into account the actual signal ambiguities resulting from the elements MIN MAX delay characteristics The most common areas of concern include e data clock signal relationships e clock pulse widths e bus arbitration timing Signal ambiguities that converge or reconverge on wired nets or buses with multiple drivers may also produce hazards in a manner similar to the behavior of logic gates In such cases PSpice A D factors out any common ambiguity before reporting the existence of a hazard condition The use of constraint checkers to validate signal behavior and interaction in these areas of your design identifies timing problems early in the design process Otherwise a timing related failure is only
71. Waveforms for the selected output variables appear Adding digital signals to a plot When defining digital trace expressions you can include any combination of digital signals buses signal constants bus constants digital operators macros and the Time sweep variable The following rules apply e An arithmetic or logical operation between two bus operands results in a bus value that is wide enough to contain the result e An arithmetic or logical operation between a bus operand and a signal operand results in a bus value The syntax for expressing a digital output variable or expression is digital_output_variable display_name or digital_expression display_name Analyzing results Use spaces or commas to separate the output variables you place in the Trace Expressions list 431 Chapter 14 Digital simulation Example U2 Y OUT1 where U2 Y is the output variable On the plot the signal is labeled OUTL 432 Table 9 This placeholder Means this digital_output_ output variable from the Simulation variable Output Variable list Digital check box selected digital_expression expression using digital output variables and operators display_name text string name to label the signal on optional the plot instead of using the default output variable notation To add a digital trace expression 1 In the Add Traces dialog box make sure you select the Digital check box Do
72. a nonzero MIN MAX delay spread Consider the following example that uses the delay values of the previous BUF model Oe P s 35 85 5 20 45 Figure 99 Timing ambiguity example two This accumulation of ambiguity may have adverse effects on proper circuit operation In the following example consider ambiguity on the data input to a flip flop a 7 De ee fbr Figure 100 Timing ambiguity example three The simulator must predict an X output because it is not known with any certainty when the data input actually made the 0 1 transition If the cumulative ambiguity present in the data signal had been less the 1 state would be latched up correctly Figure 101 illustrates the case of unambiguous data change settled before the clock could transition being latched up by a clock signal with some ambiguity The Q output will change but the time of its transition is a function of both the clock s ambiguity and that contributed by the flip flop MIN MAX delays D Q 7 pe Figure 101 Timing ambiguity example four Propagation of timing ambiguity 461 Chapter 16 Digital worst case timing analysis 462 Identification of timing hazards Timing hazard is the term applied to situations where the response of a device cannot be properly predicted because of uncertainty in the arrival times of signals applied to its inputs For example Figure 102 below shows the following signal transitions 0 1 1 0 being a
73. accumulation of ambiguity Figure 106 shows the effects of additional cumulative ambiguity 2 5 9 12 3 LO 19 H gt _L rn 12 TPxxMN 1 TPxxMX 7 Figure 106 Cumulative ambiguity hazard example two The X result is predicted here because the ambiguity of the rising edge propagating through the device has increased to the point where it will overlap the later falling edge ambiguity Specifically the rising edge should occur between 3nsec and 12nsec but the subsequent falling edge applied to the input predicts that the output starts to fall at 10nsec This situation is called a cumulative ambiguity hazard Another cause of cumulative ambiguity hazard involves circuits with asynchronous feedback The simulation of such circuits under worst case timing constraints yields an overly pessimistic result due to the unbounded accumulation of ambiguity in the feedback path A simple example of this effect is shown in Figure 107 SA OSC OSC aA Aa E7 N Figure 107 Cumulative ambiguity hazard example three Due to the accumulation of ambiguity in the loop the output signal will eventually become X because the ambiguities of the rising and falling edges overlap However in the hardware implementation of this circuit a continuous phase shift with respect to absolute time is what will actually occur assuming normal deviations of the rise and fall delays from the nominal values Iden
74. additional possibility of being unable to continue because the time step required becomes too small from something in the circuit moving too fast This is also discussed below Newton Raphson requirements The Newton Raphson algorithm is guaranteed to converge to a solution However this guarantee has some conditions 1 The nonlinear equations must have a solution 2 The equations must be continuous 3 The algorithm needs the equations derivatives 4 The initial approximation must be close enough to the solution Each of these can be taken in order Remember that the PSpice algorithms are used in computer hardware that Introduction has finite precision and finite dynamic range that produce these limits e Voltages and currents in PSpice are limited to 1e10 volts and amps e Derivatives in PSpice are limited to 1e14 e The arithmetic used in PSpice is double precision and has 15 digits of accuracy Is there a solution Yes for any physically realistic circuit However it is not difficult to set up a circuit that has no solution within the limits of PSpice numerics Consider for example a voltage source of one megavolt connected to a resistor of one micro ohm This circuit does not have a solution within the dynamic range of currents 1e10 amps Here is another example V1 l 0 5v D1 1s 0 DMOD MODEL DMOD IS le 16 The problem here is that the diode model has no series resistance It can be shown th
75. also automatically configures the library for local use To have resistors R2 and R4 use the same tolerances as R1 1 In Capture s schematic page editor select R2 and R4 2 From the Edit menu select Properties 3 In the R2 row click in the cell under the Implementation column and type RMontel 4 In the R4 row click in the cell under the Implementation column and type RMontel To assign 5 device tolerance to the resistance multiplier for R3 1 Select R3 2 From the Edit menu select PSpice Model 3 Inthe Model Text frame change the MODEL statement to model RTherm RES R 1 DEV 5 4 From the File menu choose Save Your schematic page should look like Figure 82 Setting up the analyses This section shows how to define and enable a DC analysis that sweeps the pressure value and a Monte Carlo analysis that runs the DC sweep with each change to the resistance multipliers To set up the DC sweep 1 Inthe PSpice menu choose New Simulation Profile or Edit Simulation Settings If this is a new simulation enter the name of the profile and click OK The Simulation Settings dialog box appears R4 RAMonte ak Meter 2 Zak R RMonte1 R5 vt k R RTherm Zz ial Pressure Sensor PARAMETERS Pepet 0 06 Fnom 1 0 3 1k 14 P Pooeff Pnom f Figure 82 Pressure sensor circuit with RMontel and RTherm model definitions 2 Select DC Sweep in the Analy
76. an expression changes during an analysis Spedfying expressions To use an expression in your circuit 1 Find the numeric or boolean value you want to replace a component value model parameter value other property value or logic in an IF function test see page 3 112 for a description of the IF function 2 Replace the value with an expression using the following syntax expression where expression can contain any of the following e standard operators listed in Table 9 e built in functions listed in Table 10 e user defined functions e system variables listed in Table 11 e user defined global parameters e literal operands The curly braces tell PSpice A D to evaluate the expression and use its value Using global parameters and expressions for values Example A parameter that changes with each step of a DC sweep or parametric analysis Example Suppose you have declared a parameter named FACTOR with a value of 1 2 and want to scale a 10 V independent voltage source VEE by the value of FACTOR To do this set the DC property of VEE to 10 FACTOR PSpice A D evaluates this expression to 10 1 2 or 12 volts For more information on user defined functions see the FUNC command in the Commands chapter in the online OrCA D PSpice A D Reference Manual For more information on user defined parameters see Using global parameters and expressions for values on page 3 107 109 Chapt
77. analyses and starting simulation 287 Chapter overview i626 enieg ei Use Geb Oo ROe bea w ad OS 287 Analysis TY OES aa en Bees Be EE ke ee oe EEO A EA 288 Setting up analyses ae Sa Seba Cee eR ER EAS SER SS 289 Execution order for standard analyses 290 Output variables 4 2 gee so om amp oe Ro ona ia tenema mamaaa 292 Modillers esre eee is ad be Re ee BG ee eS i 293 Starting a simulation ios aa eee ee KS Me a a a eee ae 299 Starting a simulation from Capture 04 299 Starting a simulation outside of Capture 300 Setting up batch simulations 60 6 6s eave de wesw eens 300 Multiple simulation setups within one circuit fille 300 Running simulations with multiple circuit files 301 The PSpice A D simulation window 04 301 DC analyses 305 Chapter OVEIVIOW tas me mea pate oO po ERS EY Se RAO 305 INOS Weep sirra resa eee et eed ete ete eee bh eS eae ed 306 Minimum requirements to run a DC sweep analysis 306 Overview of DC sweep 4 3deseGe hoe 22 eo Ras eRe Se Be eS 308 Setting up a DC stimulus 4 os ae wee Kad ald Soe ee 310 Nested DC sweeps o42 4 to hie dee 4 Se ede ete ee de Sa 311 Curve families for DC sweeps 2 44 ss es vee bun eee ee eas 313 Bias DOME s oq eke oe SG e DAR ESE LAER S CEO RRS A aS 315 Minimum requirements to run a bias point analysis 315 Overview of bias point 4 as 42 42 4 4 ode eS eee a ee pote 4 315 omall si
78. and reported The digital devices themselves are not included in the small signal analysis A gate for example does not have a frequency response Instead all the digital devices hold the states that were calculated when solving for the bias point However for N and O devices in the analog digital interface subcircuits the analog side has a well defined linear equivalent To calculate the small signal gain input resistance and output resistance Simulation Settings Small Signal x General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window Analysis type M Output File Options Bias Point z r PESA F z T Include detailed bias point information for nonlinear controlled N sources and semiconductors OP Options General Settings T Perform Sensitivity analysis SENS Temperature Sweep muput yananiels l Load Bias Point Save Bias Point IM Calculate small signal DC gain TF From Input source name fi To Output variable Ou 1 In the Bias Point dialog box select Calculate small signal DC gain TF 2 Specify the value for either an output voltage or the current through a voltage source in the To Output variable box For example entering V a b as the output variable specifies that the output variable is the output voltage between two nets a and b Entering I VDRIV as the output variable specifies that the output variable is
79. aoaaa aaa a 405 Circuit file using VARY BOTH 24 5 4 eee aaa a 405 FILESTIM1 used on a schematic page ooa 425 Circuit with a timing error oaaao a 436 Circuit with a timing ambiguity hazard 436 Mixed analog digital circuit before and after interface generation 455 Simulation output for mixed analog digital circuit 456 Timing ambiguity example one aooaa a 460 Timing ambiguity example tw0 aaoo ee ee ee 461 Timing ambiguity example three aoaaa ee ee ee 461 Timing ambiguity example four aaou a 461 Timing hazard example ooa a 462 Convergence hazard example onoo a 463 Critical hazard example oaoa be RES ERR LEYS SSS 463 Cumulative ambiguity hazard example one 464 Cumulative ambiguity hazard example two 464 Cumulative ambiguity hazard example three 465 Reconvergence hazard example one v4 40e40ieewe bbe eee a 466 Reconvergence hazard exampletwo 2 20 05 0000s 466 Glitch suppression example one n nooo 468 Glitch suppression example two 2 2 2 0020000020 G 468 Glitch suppression example three one aig ecee me Oo KOS Bo es 469 Analog and digital areas ofaplot 00040 477 Two Probe windows 0 0 0 00 a a a a 478 Trace legend symbols 4 9 eek oe Ree ee ee SS ERO YESH Ae 494 Section information message box 2 666604 ee ee eee ee eee 495 Example schematic EXAMPLE OPJ
80. array Bidirectional transfer gates NBTG N channel transfer gate PBTG P channel transfer gate Flip flops and latches JKFF J K negative edge triggered DFF D type positive edge triggered SRFF S R gated latch DLTCH D gated latch Pullup pulldow n resistors PULLUP pullup resistor array PULLDN pulldown resistor array Delay lines DLYLINE delay line 244 Table2 Digital primitives summary continued Type Description Programmable logic arrays PLAND AND array PLOR OR array PLXOR exclusive OR array PLNAND NAND array PLNOR NOR array PLNXOR exclusive NOR array PLANDC AND array true and complement PLORC OR array true and complement PLXORC exclusive OR array true and complement PLNANDC NAND array true and complement PLNORC NOR array true and complement PLNXORC exclusive NOR array true and complement Memory ROM read only memory RAM random access read write memory Multi Bit A D amp D A Converters ADC multi bit A D converter DAC multi bit D A converter Behavioral LOGICEXP logic expression PINDLY pin to pin delay CONSTRAINT constraint checking The format for digital primitives is similar to that for analog devices One difference is that most digital primitives require two models instead of one e The timing model which specifies propagation delays and timing constraints such as setup and hold times Functional behavior 245 Chapter 7 Digital device modeling For specif
81. as the simulation progresses marching waveforms Waveforms are displayed only after the full simulation has completed and all data has been calculated Waveforms are displayed for those nets that have markers attached in the schematic Waveforms are displayed according to the last display configuration that was used in the Probe window Viewing waveforms while simulating While a simulation is in progress you can monitor the results for the data section being written by PSpice A D This function is only available when the Display Probe window during simulation option is enabled in the Probe Window tab of the Simulation Settings dialog box To monitor results during a simulation 1 From Capture s PSpice menu choose Edit Simulation Settings to display the Simulation Settings dialog box 2 Click the Probe Window tab Select Display Probe window and then click during simulation 4 Click OK to close the Simulation Settings dialog box 5 From the PSpice menu choose Run to start the simulation One Probe window is displayed in monitor mode 6 Doone of the following to select the waveforms to be monitored e From PSpice s Trace menu choose Add and enter one or more trace expressions e From Capture s PSpice menu point to Markers then choose and place one or more markers The Probe window monitors the waveforms for as long as the most recent data section is being written After that data secti
82. behavior of digital devices within a standard transient analysis including worst case min max timing For mixed analog digital circuits all of the above mentioned analyses can be run If the circuit is digital only only the transient analysis can be run Table 4 provides a summary of the available PSpice A D analyses and the corresponding Analysis type options where the analysis parameters are specified In Capture switch to the PSpice view then from the PSpice menu choose New Simulation Profile Table4 Classes of PSpice A D analyses Analysis Analysis type or Option Swept variable Standard analyses DC sweep DC Sweep source parameter temperature Bias point Bias Point Small signal DC transfer Bias Point DC sensitivity Bias Point Frequency response AC Sweep Noise frequency Noise requires a frequency AC Sweep Noise frequency response analysis Transient response Time Domain time Transient Fourier requires transient Time Domain time response analysis Transient Simple multi run analyses Parametric Parametric Sweep Table4 Classes of PSpice A D analyses continued Analysis Analysis type or Option Swept variable Temperature Temperature Sweep Statistical analyses Monte Carlo Monte Carlo Worst Case Sensitivity worst case Monte Carlo Worst Case The waveform analyzer calculates and displays the results of PSpice A D simulations for swept analyses The waveform analyzer also genera
83. digital modeling and includes the following sections e Introduction on page 7 242 e Functional behavior on page 7 243 e Timing characteristics on page 7 251 e Input Output characteristics on page 7 257 Chapter 7 Digital device modeling 242 Introduction The standard part libraries contain a comprehensive set of digital parts in many different technologies Each digital part is described electrically by a digital device model in the form of a subcircuit definition stored in a model library The corresponding subcircuit name is defined by the part s MODEL attribute value Other attributes MNTYMXDLY IO_LEVEL and the PSPICEDEFAULTNET set are passed to the subcircuit thus providing a high level means for influencing the behavior of the digital device model Generally the digital parts provided in the part libraries are satisfactory for most circuit designs However if your design requires digital parts that are not already provided in OrCAD s part and model libraries you need to define digital device models corresponding to the new digital parts A complete digital device model has three main characteristics e Functional behavior described by the gate level and behavioral digital primitives comprising the subcircuit e I O behavior described by the I O model interface subcircuits and power supplies related to a logic family e Timing behavior described by one or more timing models pin to pin delay p
84. either design or global application to your designs Design models Design models apply to one design The schematic page editor automatically creates a design model whenever you modify the model definition for a part instance on your schematic page You can also create models externally and then manually configure the new libraries for a specific design Global models Global models are available to all designs you create The part editor automatically creates a global model whenever you create a part with a new model definition The Model Editor also creates global models You can also create models externally and then manually configure the new libraries for use in all designs How are models organized To optimize the search PSpice A D uses indexes To find out more about this and how to add delete and rearrange configured libraries see Configuring model libraries on page 4 162 To find out how to change the design and global configuration of model libraries see Changing design and global scope on page 4 165 Example usage To set up device and lot tolerances on the model parameters for a particular part instance when running a Monte Carlo or sensitivity worst case analysis PSpice A D searches design libraries before global libraries To find out more see Changing model library search order on page 4 166 131 Chapter 4 Creating and editing models For a list of device models provided by OrCAD refer t
85. frequency response vs arbitrary parameter 370 mixed analog digital waveform analysis 500 modeling a triode ABM 217 Monte Carlo analysis 385 parametric analysis 82 performance analysis 89 366 transient analysis 72 using the Model Editor 146 156 worst case analysis 401 expression parts ABM 200 214 expressions 109 110 see also parameters ABM 220 functions 111 specifying 109 system variables 113 waveform analysis 527 F files generated by Capture 50 user configurable 51 with simulation results 54 FILESTIM digital stimulus part 119 424 flicker noise 337 FORMAT stimulus property digital 423 Fourier analysis 288 introduction 45 FREQUENCY output variable 522 frequency response vs arbitrary parameter 370 frequency table parts ABM 220 229 237 functions PSpice A D 111 waveform analysis 528 G GaAsFET 296 525 526 glitch suppression 439 goal functions 367 in performance analysis 368 single data point 368 grid spacing part graphics 178 part pins 178 ground missing 124 missing DC path to 125 566 parts 100 group delay 524 H histograms 393 hysteresis curves 359 I O model 245 248 257 445 and switching times TSW 259 DIGPOWER 258 DRVH 258 DRVL 258 DRVZ 258 INLD 258 INR 258 OUTLD 258 parameter summary 260 TPWRT 255 258 TSTOREMN 258 IAC stimulus part 325 IC property 546 ICn initial conditions parts 544 IDC stimulus part 114 310
86. is the only AC stimulus to this circuit Magnitude equals 1 V and relative phase is left at zero degrees the default All other voltage sources have zero AC value 329 Chapter 10 AC analyses Note The source V1 is a VSIN source that iS normally used for setting up sine wave signals for a transient analysis It also has an AC property so that you can use it for an AC analysis To find out more about VSIN and other source symbols that you can use for AC analysis see Using time based stimulus parts with AC and DC properties on page 3 118 330 Simulation Settings AC Sweep ix General Analysis include Files Libraries Stimulus Options Data Collection Probe Window Analysis type r AC Sweep Type Jac Sweep Noise zl Linear Start Frequency 100K Options Logarithmic End Frequency fi 0G Bl General Settings Decade z PAren mp CMonte Carlo Worst Case z i Parametric Sweep Temperature Sweep r Noise Analysis M Enabled Output Voltage fv 0ut2 lA Source fui Interval fo Figure 63 AC analysis setup for EXAMPLE OP Frequency is swept from 100 kHz to 10 GHz by decades with 10 points per decade The V1 independent voltage source is the only input to an amplifier so it is the only AC stimulus to this circuit Magnitude equals 1 V and relative phase is left at zero degrees the default All other voltage sources have zero AC value How PSpice A D treats nonlinear devices
87. larger Large data files may be slow to open and slow to draw traces One way to work around thisis to set up an overnight batch job to run the simulation and execute commands You can even set up the batch job to produce a series of plots on paper to be ready for you in the morning 376 Statistical analyses Monte Carlo and sensitivity worst case are statistical analyses This section describes information common to both types of analyses See Monte Carlo analysis on page 13 381 for information specific to Monte Carlo analyses and see Worst case analysis on page 13 398 for information specific to sensitivity worst case analyses Overview of statistical analyses The Monte Carlo and worst case analyses vary the lot or device tolerances of devices between multiple runs of an analysis DC AC or transient Before running the analysis you must set up the model and or lot tolerances of the model parameter to be investigated A Monte Carlo analysis performs a Monte Carlo statistical analysis of the circuit A worst case analysis performs a sensitivity and worst case analysis of the circuit Sensitivity worst case analyses are different from Monte Carlo analyses in that they compute the parameters using the sensitivity data rather than using random numbers You can run either a Monte Carlo or a worst case analysis but you cannot run both at the same time Multiple runs of the selected analysis are done while par
88. macromodel to implement differentiation Here are some guidelines e Inthe case of a Laplace device ELAPLACE multiply the Laplace expression by e to the s lt the suggested delay gt e Inthe case of a frequency table EFREQ or GFREQ do either of the following e Specify the table with DELAY lt the suggested delay gt e Compute the delay by adding a phase shift Cautions and recommendations for simulation and analysis Chebyshev filters All of the considerations given above for Laplace parts also apply to Chebyshev filter parts However PSpice A D also attempts to deal directly with inaccuracies due to sampling by applying Nyquist criteria based on the highest filter cutoff frequency This is done by checking the value of TMAX If TMAX is not specified it is assigned a value or if it is specified it may be reduced For low pass and band pass filters TMAX is set to 0 5 FS where FS is the stop band cutoff in the case of a low pass filter or the upper stop band cutoff in the case of a band pass filter For high pass and band reject filters there is no clear way to apply the Nyquist criterion directly so an additional factor of two is thrown in as a safety margin Thus TMAX is set to 0 25 FP where FP is the pass band cutoff for the high pass case or the upper pass band cutoff for the band reject case It may be necessary to set TMAX to something smaller if the filter input has significant frequency c
89. model parameter sets 129 Models defined as subcircuit netlists 0 129 Flow are models organized 4 0 ee aha we eo Mee 130 Model libraries 6 wae week oe oy poke oO eR SO 130 Model library configuration 226 64 665644068 deb ewes 131 Global vs design models and libraries 131 Nested model libraries 24 24 a lt 6e e oheaewi de ee econ 132 OrCAD provided models eee ees dw eee eae ee ee we 132 Tools to create and edit models 2 45sec es tee eed eae wee 133 Ways to create and edit models 04 263444 Paw d wee eee 134 Using the Model Editor to Ode MOCO ose Sh el ee a Ble EAE we oO ZA 135 Ways to use the Model Editor 2 sa4 doe eve Gees aw Ss 136 Model Editor supported device types 0 137 Ways To Characterize Models 2 42 4 24458 20402 Os Bx en 138 Creating models from data sheet information 138 Analyzing the effect of model parameters on device characteristics 0000 139 How to fit models eke ee we me Ge a 139 Running the Model Editor alone aaou 141 Starting the Model Editor aoaaa a 141 Enabling and disabling automatic part creation 142 Saving global models and parts oaoa 142 Running the Model Editor from the schematic page editor 143 What is an instance model cee se aaa 143 Starting the Model Editor e064 6 4 a 144 Saving design models aoaaa a 144 What happens if you don
90. models see e Running the Model Editor from the schematic page editor on page 4 143 e Starting the Model Editor from the schematic page editor in Capture on page 4 153 160 To change the model reference for a part in the part library 1 Find the name of the model that you want to use 2 Inthe schematic page editor select the part you want to change 3 From the Edit menu choose Part to start the part editor with that part loaded for editing 4 From the Options menu choose Part Properties to display the User Properties dialog box Select Implementation Type 6 From the Implementation list select PSpice Model 7 Inthe Implementation text box type the name of the existing model that you want to use if it is not already listed 8 Click OK to close the Edit Part dialog box Reusing instance models If you created instance models in your design and want to reuse them there are two things you can do e Attach the instance model implementation to other part instances in the same design e Change the instance model to a global model and create a part that corresponds to it Reusing instance models in the same schematic There are two ways to use the instance model elsewhere in the same design To use the instance model elsew here in your design 1 Do one of the following Reusing instance models e Change the model reference for other part See Changing the model instances to the name of t
91. more about AC sweep and noise analysis 81 Parametric analysis lt 4 Ho ee ae Oe Oe OH BLE RR 82 Setting up and running the parametric analysis 83 Analyzing waveform families 0 00 000000 4 85 Finding out more about parametric analysis 88 Performance analysis i 24 ite dees de Gow e e Awd Dw eA 89 Finding out more about performance analysis 91 Part two Chapter 3 Design entry Preparing a design for simulation 95 Chapter overview 2 434046 6 60en di tetas be ees Checklist for simulation setup 4 4 4 4 04 eek awk owes Typical simulation setup steps 1 0 2000 Advanced design entry and simulation setup steps When netlisting fails or the simulation does not start ce sh eee ced ee ead ee es des Things to check in your design Things to check in your system configuration Using parts that you can simulate oe oe cee xe eS Vendor supplied parts 2 544 440864404 4du eu 4 Part naming conventions 4 0 0 4 a 5 ea4 ea ooo es Finding the part that you want 0 Passive parts 2 64 o teve deck Do ee ee Oe aoe es Breakout Pate 0 246 face does tae ee bho ke dd ee Behavioral parts 24 045 4 24686 bb e0oe we eG sew ees Using global parameters and expressions for values Global parameters lt 2a er Gd che es ER SRD Swe BE ee Declaring and using a global parameter EXPICSSIO
92. needed for simulation 181 PSPICETEMPLATE 0 0 000000000 eee ee 182 PSPICE TEMPLATE syntax aie 5 4 ka ke se ee RR BE Ro 182 PSPICETEMPLATE examples 4k eo Hob be a 185 IO LEVEL s008 ack hE we ung e aoee a oe eee BL ah oO te Bae 189 MINTY MXDLY se oo ode Bog be oe Been d ge ea SA deed 190 PSPICEDEFAULTNET 0 0 0 0 00000000004 191 Analog behavioral modeling 193 Chapter ovefvieW so seos seoan a eke ee ee eS a 193 Overview of analog behavioral modeling 194 The ABMLOLE part library file ve Ose eee ok Re eee SE 195 Placing and specifying ABM parts 6 piece 2 eee Sea he ee 196 Net names and device names in ABM expressions 196 Forcing the use of a global definition 197 ABM part templates 4 ae Ga ae ee a eS be er eee 198 Control system parts 24644224265 e2F h Pe hee has Pe 85 199 Basic COMPONEINS cs sose oe 2 Sek OHS Sere G6 D OHS Oe Es 201 Limiters 2 a 202 Chebyshev filters 5 24620 dae 2 oS 6 eee Se OS dew ele ees 203 Integrator and differentiator 426135 44k ees RAR ee we So 206 Table look up parts ecb es eS Ue ee ee ee Soe ees ee es 206 Laplace transform part 3 54 de eer ed he eke ee PRs 210 Math functions es seri eneen kaes neka eea 213 ABM expression parts aaau aaa me Pea ee es 214 An instantaneous device example modeling atriode 217 PSpice A D equivalent parts ooa a RS 4 ee 220 Implementation of PSpice A D equiva
93. of your simulation Basic controlled sources Basic controlled sources As with basic SPICE PSpice A D has basic controlled sources derived from the standard SPICE E F G and H devices Table 1 summarizes the linear controlled source types provided in the standard part library Table1 Basic controlled sources in ANALOG OLB Device type Part name Controlled Voltage Source E PSpice A D E device Current Controlled Current Source F PSpice A D F device Controlled Current Source G PSpice A D G device Current Controlled Voltage Source H PSpice A D H device Creating custom ABM parts Create a custom part when you need a controlled source Refer to your OrCA D Capture that is not provided in the special purpose set or that is User s Guide for a description of how more elaborate than you can build with the general to create a custom part purpose parts with multiple controlling inputs for example The transfer function can be built into the part two different ways e directly in the PSPICETEMPLATE definition e by defining the part s EXPR and related properties if any The PSpice A D syntax for declaring E and Gdevicescan Refer to the online OrCA D PSpice help you form a PSPICETEMPLATE definition A D Reference Manual for more information about E and G devices 239 Chapter 6 Analog behavioral modeling 240 Digital device modeling Chapter overview This chapter provides information about
94. on page 4 166 e If found the schematic page editor starts the Model Editor which opens the model library that contains the instance model and loads the instance model e If not found the schematic page editor assumes that this is a new instance model and does the following makes a copy of the original model definition names it original_model_name Xn and starts the Model Editor with the new model loaded Saving design models When you save your edits the Model Editor saves the model definition to DESIGN_NAME LIB which is already configured for local use see What happens if you don t save the instance model on page 4 145 To save instance models 1 From the File menu choose Save to update DESIGN_NAME LIB and save it to disk 144 Using the Model Editor to edit models What happens if you don t save the instance model Before the schematic page editor starts the Model Editor it does these things e Makes a copy of the original model and saves it as an instance model in SCHEMATIC_NAME LIB e Configures SCHEMATIC_NAME LIB for design use if not already done e Attaches the new instance model name to the Implementation property for the selected part instance This means that if you e quit the Model Editor or e return to Capture to simulate the design without first saving the model you are editing the part instance on your schematic page is still attached to the instance model implementation In
95. one of the following In the Simulation Output Variables list click the signal you want to display In the Trace Expression text box create a digital expression by either typing the expression or by selecting digital output variables from the Simulation Output Variables list and digital operators from the Digital Operators and Functions list If you want to label a signal with a name that is different from the output variable a Click in the Trace Expression text box after the last character in the signal name Type display_name where display_name is the name of the label Adding buses to a waveform plot You can evaluate and display a set of up to 32 signals asa bus even if the selected signals were not originally a bus This is done by following the same procedure already given for adding digital signals to the plot However when adding a bus be sure to enclose the list of signals in braces Q3 Q2 Q1 Q2 4 The complete syntax is as follows signal_list L display_name radix 1 or bus_prefixi msb lsb display_name L radix1 Table 10 This placeholder Means this signal list comma or space separated list of up to 32 digital node names in sequence from high order to low order bus_prefix msb lsb alternate way to express up to 32 signals in the bus display_name text string name to label the bus on the optional plot instead of using the default output variable notation rad
96. or the node name automatically generated for an unlabeled wire appended with AtoD or DtoA If the node is attached to more than one digital part the second digital node is appended with AtoD2 or DtoA2 and so on Figure 96 below shows a fragment of a mixed analog digital circuit before and after the interface subcircuits have been added The wires labeled 1 and 2 in the schematic representation are the interface nets connecting analog and digital parts These translate to interface nodes which are processed by PSpice A D to create the circuit fragment shown in the PSpice A D representation schematic representation ui Ra Ay 7404 uz 7404 PSpice A D representation ui RA 1 1 2 Tbten 2 0ie4 1 2 AoD Dios EEA 7404 on 1 2 1 4t002 ue Aled 7404 Figure 96 Mixed analog digital circuit before and after interface generation After interface generation node 1 is a purely analog node connecting the resistor transistor and the analog inputs of both AtoD subcircuits Node 2 is also a purely analog node connecting the resistor and the analog output of the DtoA interface You can see that PSpice A D inserted two new digital nodes 1 AtoD and 1 AtoD2 which connect the outputs of the AtoD interfaces to the inverter inputs It also created one digital node 2 DtoA to connect the output of U1 to the digital input of the DtoA interface The interface subcircuits PSpice A D a
97. parameters named CD4000_VDD and CD4000_VSS that are referenced by the CD4000_PWR subcircuit definition To change the CD4000_ PWR power supply to 12 volts referenced to ground 1 Place an instance of the PARAM pseudopart from SPECIAL OLB 2 Create anew PARAM property as follows CD4000_VDD 12 0V DC4000_VSS is left at its default of 0 volts If the reference voltage also needs to be reset the same method can be used to define the CD4000_VSS parameter by setting this property of the same PARAM instance For example if you want the supplies to go between 5 volts and 5 volts a difference of 10 volts set CD4000_VSS to 5V and CD4000_VDD to 10V as a result CD4000_VDD is 10 volts above CD4000_VSS or 5 volts Creating a secondary CD4000 TTL or ECL power supply Designs using CD4000 TTL or ECL parts may require power supply voltages in addition to the default 5 0 volts supplied by the standard CD4000_PWR power supply part To create a secondary power supply for any one of the CD4000 TTL or ECL technologies you must place the appropriate power supply part and create user defined nodes with a new voltage value To create and use a secondary CD4000 power supply with nodes MY_VDD and MY_VSS and a voltage of 3 5 volts 1 Place the CD4000_PWR power supply and modify the appropriate pin properties as follows VOLTAGE 3 5V PSPICEDEFAULTNET MY_VDD PSPICEDEFAULTNET MY_VSS 2 Selecta CD4000 part in the schematic t
98. part is characterized by the following properties ROW1 OHz 0 0 ROW2 5kHz 0 5760 ROW3 6kHz 60 6912 DELAY R_I MAGUNITS PHASEUNITS Since R_I MAGUNITS and PHASEUNITS are undefined each table entry is interpreted as containing frequency magnitude value in dB and phase values in degrees Delay defaults to 0 This produces a PSpice A D netlist declaration like this ELOFILT 5 0 FREQ V 10 0 0 0 5kHz 0 5760 6kHz 60 6912 Since constant group delay is calculated from the values for a given table entry as group delay phase 360 frequency An equivalent FTABLE instance could be defined using the DELAY property For this example the group delay is 3 2 msec 6912 360 6k 5760 360 6k 3 2m Equivalent property assignments are ROW OHz 0 0 ROW2 5kHz 0 0 ROW3 6kHz 60 0 DELAY 3 2ms RI MAGUNITS PHASEUNITS This produces a PSpice A D netlist declaration like this ELOFILT 5 0 FREQ V 10 0 0 0 5kHz 0 0 6kHz 60 0 DELAY 3 2ms 209 Chapter 6 Analog behavioral modeling 210 Laplace transform part The LAPLACE part specifies a Laplace transform which is used to determine an output for each input value LAPLACE NUM numerator of the Laplace expression DENOM denominator of the Laplace expression The LAPLACE part uses a Laplace transform description The input to the transform is a voltage The numerator and denominator of the Laplace transform
99. seconds Parametric Sweep Temperature Sweep J Skip the initial transient bias point calculation SKIPBP Save Bias Point _JLoad Bias Point Output File Options Transient Output File Options E Start saving data after seconds Gi IV Perform Fourier Analysis ema Center Frequency 1Meg Number of Harmonics Output Variables Out2 hz IV Include detailed bias point information for nonlinear controlled sources and semiconductors OP Figure 65 Transient analysis setup for EXAMPLE OP Transient time response During a transient analysis any or all of the independent sources may have time varying values In EXAMPLE OP J the only source which has a time varying value is V1 VSIN part with attributes VOFF Ov VAMPL 0 1v FREQ 5Meg V1 s value varies as a 5 MHz sine wave with an offset voltage of 0 volts and a peak amplitude of 0 1 volts In general more than one source has time varying values for instance two or more clocks in a digital circuit VOU ieee readme RalaS RCI RC2 example rdm ak Z ik z ik CLOAD OUTI d ouT2 RS RSI y o wif Fy 202222 a2 tk The example circuit EXAMPLE OP is amp l provided with the OrCAD program Iles des ey installation a ae 4202222 4d bs 212222 CO VEE o VEE Figure 66 Example schematic EXAMPLE OPJ The transie
100. that will go to the PINDLY primitive In this case LOGICEXP buffers the ENP_I ENT_I CLK_I CLRBAR_I LOADBAR_I and four data signals See the Digital Devices chapter in the online OrCAD PSpice A D Reference Manual for more information For our 74160 example the logic expression LOGICEXP has fourteen inputs and twenty outputs The inputs are the nine interface input pins in the subcircuit plus five feedback signals that come from the flip flops QA QB QC QD and QDBAR The flip flops are primitive devices themselves and are not part of the logic expression The outputs are the eight J K data inputs to the flip flops RCO the four data lines used internal to the logic expression A B C D and the seven control lines CLK CLKBAR EN ENT ENP CLRBAR and LOADBAR The schematic representation of the device shows buffers on every input signal of the model while the logic diagram of the device in the data book shows buffers or inverters on only the CLRBAR_I CLK_I and LOADBAR Isignals We have added buffers to the inputs to minimize the insertion of A to D interfaces when the device is driven by analog circuitry The best example is the CLK signal With the buffer in place if the CLK signal is analog one A to D interface device will be inserted into the circuit by the simulator If the buffer was not present then an interface device would be inserted at the CLK pin of each of the flip flops The buffers have no delay assoc
101. the current through a voltage source VDRIV Specify the input source name in the Calculate small signal DC gain TF portion of the Bias Point dialog box The gain from the input source to the output variable is calculated along with the input and output resistances For example if you enter V OUT2 as the output variable and v1 as the input source the input resistance for V1 is calculated the output resistance for V OUT2 is calculated and the gain from V1 to V OUT2 is calculated All calculations are reported to the simulation output file Small signal DC transfer 319 Chapter9 DC analyses 320 DC sensitivity Minimum requirements to run a DC sensitivity analysis Minimum circuit design requirements None Minimum program setup requirements 1 Inthe Bias Point dialog box select Perform Sensitivity analysis SENS 2 Enter the required value s in the Output variable s box 3 Click OK to save the simulation profile Be sure you give the new profile an appropriate name under the General tab prior to saving 4 In Capture from the PSpice menu select Run to start the simulation DC sensitivity Overview of DC sensitivity DC sensitivity analysis calculates and reports the sensitivity of one node voltage to each device parameter for the following device types resistors independent voltage and current sources voltage and current controlled switches diodes bipolar transistors The sensitivi
102. the tolerance range thus producing incorrect worst case results 404 The second MODEL statement scales the nominal value of Rb2 by 1 1 to approximately 800 ohms The gain still increases with a small increase in R but a larger increase in R increases the base voltage so much that it drives the BJT into saturation and nearly eliminates the gain The worst case analysis is fooled by the sensitivity analysis into assuming that Rb2 must be minimized to degrade the gain but maximizing Rb2 is much worse see Figure 90 Note that even an optimizer which checks the local gradients to determine how the parameters should be varied is fooled by this circuit QOD oS se ae Se Sn ee 1 q 1504 max 5 i 1 0500 84 829 1 q 1 g q 1085 i Nominal 725 Ohm i 1 0000 40 246 i q 5g HC analysis result i min 5 f 950 000m 15 169 1 q 1 i a E E PPaSe Resa SS asSesse PoSSS RP sSSs seers POSR Rr SsS sSRncsse 4 8 4 9 1 6 1 1 1 2 o YatXx U 0ut 1090k Rbmod R Figure 89 Correct worst case results Nominal 800 Ohm 1 1000 140 772 1504 1 i WC analysis result woot LOS TT True worst case hae 24 3532 8 B 9 1 8 1 1 1 2 o atkX U Out 180k Rbmod R Figure 90 Incorrect worst case results Worst case analysis Tips and other useful information VARY BOTH VARY DEV and VARY LOT When VARY BOTH is specified in the WC statement and a mo
103. the DIGSTIM part to define both 1 bit signal or bus any width input signals using the Stimulus Editor See Defining a digital stimulus on page 14 413 to find out more about e all of these source parts and e how to use the Stimulus Editor to specify DIGSTIMn DIGSTIM1 DIGSTIM4 etc part 119 Chapter 3 Preparing a design for simulation For a roadmap to other commonly encountered problems and solutions see When netlisting fails or the simulation does not start on page 3 98 The libraries listed in the tables that follow all contain parts that you can simulate Some files also contain parts that you can only use for board layout That s why you need to check the Pspice TEMPLATE property if you are unsure or still getting warnings when you try to simulate your druit 120 Things to watch for This section includes troubleshooting tips for some of the most common reasons your circuit design may not netlist or simulate Unmodeled parts If you see messages like this in the PSpice Simulation Output window Warning Part part_name has no simulation model then you may have done one of the following things e Placed a part from the OrCAD libraries that is not available for simulation used only for board layout e Placed a custom part that has been incompletely defined for simulation Do this if the part in question is from the OrCAD libraries e Replace the part with an equivalent part from one of th
104. the Stimulus Editor 76 AC sweep analysis AC sweep analysis The AC sweep analysis in PSpice A D is a linear or small signal frequency domain analysis that can be used to observe the frequency response of any circuit at its bias point Setting up and running an AC sweep analysis In this example you will set up the clipper circuit for AC analysis by adding an AC voltage source for a stimulus signal see Figure 18 and by setting up AC sweep parameters om D1N3940 c1 O47u D2 R4 D1N3940 5 6k lt o F vin 2s lt H u Z m KOO Figure 18 Clipper circuit with AC stimulus To change Vin to include the AC stimulus signal 1 In Capture open CLIPPER OPJ 2 Select the DC voltage source Vin and press to remove the part from the schematic page 77 Chapter 2 Simulation examples Note PSpice simulation is not case sensitive so both M and m can be used as milli and MEG Meg and meg can all be used for mega However waveform analysis treats M and m as mega and milli respectively 78 From the Place menu choose Part In the Part text box type vac from the PSpice library SOURCE OLB and click OK Place the AC voltage source on the schematic page as shown in Figure 17 Double click the VAC part OV to display the Parts spreadsheet Change the Reference cell to Vin and change the ACMAG cell to 1V Click Apply to update the changes and
105. the inputs hazard Critical hazard It is important to note that the glitch predicted could propagate through the circuit and may cause incorrect operation If the glitch from a timing hazard becomes latched up in an internal state such as flip flop or ram or if it causes an incorrect state to be latched up it is called a critical hazard because it definitely causes incorrect operation Otherwise the hazard may pose no problem Figure 104 below shows the same case as above driving the data input to a latch ee 2 e o p pc Figure 104 Critical hazard example As long as the glitch always occurs well before the leading edge of the clock input it will not cause a problem 463 Chapter 16 Digital worst case timing analysis See Glitch suppression due to inertial delay on page 16 468 464 Cumulative ambiguity hazard In worst case mode simple signal propagation through the network will result in a buildup of ambiguity along the paths between synchronization points The cumulative ambiguity is illustrated in Figure 105 TPxxMN 1 TPxxMX 3 Figure 105 Cumulative ambiguity hazard example one The rising and falling transitions applied to the input of the buffer have a Insec ambiguity The delay specifications of the buffer indicate that an additional 2nsec of ambiguity is added to each edge as they propagate through the device Notice that the duration of the stable state 1 has diminished due to the
106. the p n junctions inside bipolar transistors MOSFETs drain bulk and source bulk JFETs and GaAsFETs 553 Chapter B Convergence and time step too small errors 554 No leakage resistance A third consideration is to avoid situations which could have an ideal current source pushing current into a reverse biased p n junction without a shunt resistance Since p n junctions in PSpice have almost no leakage resistance and would cause the junction s voltage to go beyond 1e10 volts The model libraries which are part of PSpice follow these guidelines Typos can cause unrealistic device parameters The following MOSFET M1 3 2 1 0 MMOD L 5 W 3 has a length of five meters and a width of three meters instead of micrometers It should have been M1 3 2 1 0 MMOD L 5u W 3u PSpice flags an error for L too large but cannot for W because power MOSFETs are so interdigitated a zipper like trace that their effective W can be very high The LIST option can show this kind of problem When the devices are listed in the output file their values are shown in scientific notation making it easy to spot unusual values Switches PSpice switches have gain in their transition region If several are cascaded then the cumulative gain can easily exceed the derivative limit of 1e14 This can happen when modeling simple logic gates using totem pole switches and there are several gates in cascaded in series Usually a cascade of two sw
107. their extreme values If this is not true the Monte Carlo analysis may find a point at which the results are worse To try this replace WC in the circuit file with MC lt runs gt where lt runs gt is the number of simulations you want to perform More runs provide higher confidence results The Monte Carlo summary in the output file lists the runs in decreasing order of collating function value Next add the following option to the MC statement and simulate again OUTPUT LIST RUNS lt worst_run gt This performs only two simulations the nominal and the worst Monte Carlo run The parameter values used during the worst run are written to the output file and the results of both simulations are saved Using Monte Carlo analysis with YMAX is a good way to obtain a conservative guess at the maximum possible deviation from nominal since worst case analysis usually cannot provide this information Worst case analysis Parametric sweeps STEP like the one performed in the circuit file shown in Figure 87 can be used to augment this procedure To save disk space do not specify any OUTPUT options 407 Chapter 13 Monte Carlo and sensitivity worst case analyses 408 Digital simulation 14 Chapter overview This chapter describes how to set up a digital simulation analysis and includes the following sections What is digital simulation on page 14 410 Steps for simulating digital circuits on page 14 410
108. to ground so that each controlling input and output are represented by a single pin in the part These are described in Control system parts on page 6 199 PSpice A D equivalent parts reflect the structure of the PSpice A D E and G device types which respond to a differential input and have double ended output These are described in PSpice A D equivalent parts on page 6 220 You can also use the Device Equations option described in the online OrCA D PSpice A D Reference Manual for modeling of this type but OrCAD recommends using the ABM feature wherever possible With Device Equations the PSpice A D source code is actually modified While this is more flexible and produces faster results it is also much more difficult to use and to troubleshoot Also any changes you make using Device Equations must be made to all new PSpice A D updates you install Device models made with ABM can be used for most cases are much easier to create and are compatible with PSpice A D updates The ABM OLB part library file The part library ABM OLB contains the ABM components This library contains two sections The first section has parts that you can quickly connect to form control system types of circuits These components have names like SUM GAIN LAPLACE and HIPASS The second section contains parts that are useful for more traditional controlled source forms of schematic parts These PSpice A D equivalent parts have names like EVALUE and
109. to show traces for all markers on startup you will see the V OUTL and V OUT2 traces when the Probe window displays To clear these traces from the plot from the Trace menu choose Delete All Traces 498 PSPICE SAMPLES ANASIM EXAMPLE EXAMPLE OPJ 3 From the PSpice menu choose Run to start the simulation PSpice A D generates a binary waveform data file containing the results of the simulation A new Probe window appears with the waveform data file EXAMPLE DAT already loaded Figure 118 IE Example TRAN OrCAD PSpice A D _ Example dat active Bi File Edt View Simulation Trace Plot Tools Window Help 18 x 2879 09 Time 1 000E 06 End 1 000 06 i AE Analysis A Watch A Devices OOOO Oee For Help press F1 100 ENERO ZAS Figure 118 Waveform display for EXAMPLE DAT Because this sample project was set up as a transient analysis type the data currently loaded are the results of the transient analysis Note In this sample the voltage markers for OUTI and OUT2 are already placed in the design If the markers are not placed prior to simulating you can display the waveforms later as explained below in Displaying voltages on nets Displaying voltages on nets After selected an analysis voltages on nets and currents into device pins can be displayed in the Probe windows using either schematic markers or output variables as
110. used in simulation analyses because analog net values can be specified by lt output variable gt display name as opposed to the lt output variable gt format used in analyses With this format the analog trace expression can be displayed in the analog legend with an optional alias Arithmetic functions Arithmetic expressions of analog output variables use the same operators as those used in simulation analyses by means of part property definitions in Capture You can also include intrinsic functions in expressions The intrinsic functions available for trace expressions are similar to those available for PSpice A D math 527 Chapter 17 Analyzing waveforms 528 expressions but with some differences as shown in Table 12 A complete list of PSpice A D arithmetic functions can be found in Table 10 on page 3 111 Table12 Analog arithmetic functions for trace expressions Probe Description Available in function PSpice A D ABS x Ix YES SGN x 1 if x gt 0 0 if x 0 1 if x lt 0 YES SQRT x xl 2 YES EXP x ex YES LOG x In x YES LOG10 x log x YES M x magnitude of x YES P x phase of x degrees YES R x real part of x YES IMG x imaginary part of x YES G x group delay of x seconds NO PWR x y Ixly YES SIN x sin x YES COS x cos x YES TAN x tan x YES ATAN x tan x YES ARCTAN x d x derivative of x with respect to the YES x axis variable s x integral of x over the range of the YES
111. where the x axis value is 100 86 From the Tools menu point to Cursor and choose Display Right click then left click the trace part triangle for Vdb Out 1 Vdb Out 21 Make sure that you left click last to make cursor 1 the active cursor From the Trace menu point to Cursor and choose Max From the Trace menu point to Cursor and choose Search Commands In the Search Command text box type the following search forward x value 100 Select 2 as the Cursor to Move option Parametric analysis g Click OK Figure 25 shows the Probe window with cursors aa aaa aaa ea fen J da A F A Probe Curse i A1 100 000 35 776 i A2 100 0909 17 874 N i dif 180 090H 17 902 EE EE EEEE a 18Hz 168KHZ 1 OMHZ 1OMHZ 168MHZ 100Hz 1 OKHZ 1OKHZ a udb out 1 vdb out 21 vjudb out 1 vdb out 21 Frequency Figure 25 Small signal frequency response at 100 and 10 kQ input resistance Note that the Y value for cursor 2 in the cursor box is about 17 87 This indicates that when R1 is set to 10 kQ the small signal attenuation of the circuit at 100Hz is 17 87dB greater than when R1 is 100 From the Trace menu point to Cursor and choose Display to turn off the display of the cursors Delete the trace 87 Chapter 2 Simulation examples Finding out more about parametric analysis Table 2 3 To find out more about this See this parametric analysis Parametric analys
112. will be demonstrated in this example To display the voltages at the OUT1 and OUT2 nets using output variables 1 From the Trace menu choose Add Trace to display the Add Traces dialog box The Simulation Output Variables frame displays a list of valid output variables 2 Click V OUT1 and V OUTZ2 then click OK The Probe window should look similar to Figure 118 Analog example press 499 Chapter 17 Analyzing waveforms 500 Mixed analog digital tutorial In this tutorial you will use PSpice A D to simulate a simple mixed analog digital circuit You will then analyze the output by e simultaneously displaying analog and digital traces along a common time axis and e displaying digital data values and features unique to mixed analog digital circuit analysis such as identification of digital nets inserted by PSpice A D About digital states All digital states are supported in PSpice A D Logic levels appear as shown below displays and prints yellow a displays and prints ee 0 1 R F X Nets with the Z strength at any level are displayed as a triple line as shown below Z i3 displays and prints blue Mixed analog digital tutorial About the oscillator circuit The circuit you will simulate and analyze is a mixed analog digital oscillator using Schmitt trigger inverters an open collector output inverter a standard inverter a JK flip flop a resi
113. with optional AC and DC specifications VAC template The VAC part has e two properties AC and DC e two pins and Template V REFDES DC DC DC AC AC AC Sample translation V_V6 vp vm DC 5v where REFDES equals V6 VSRC is connected to nodes vp and vm DC is set to 5v and AC is undefined Sample translation V_V6 vp vm DC 5v AC 1v where in addition to the settings for the previous translation AC is set to lv 185 Chapter 5 Creating parts for models Note For clarity the PSPICETEMPLATE property value is shown here in multiple lines in a part definition it is specified in one line no line breaks 186 Parameterized subcircuit call X template Suppose you have a subcircuit Z that has e two pins a and b e asubcircuit parameter G where G defaults to 1000 when no value is supplied To allow the parameter to be changed on the schematic page treat G as an property in the template Template X REFDES a b Z PARAMS G G G G G 1000 Equivalent template using the if else form X REFDES a b Z PARAMS G G G G 1000 Sample translation X_U33 101 102 Z PARAMS G 1024 where REFDES equals U33 G is set to 1024 and the subcircuit connects to nets 101 and 102 Sample translation X_U33 101 102 Z PARAMS G 1000 where the settings of the previous translation apply except that G is undefined Defining part properties needed for simulation Digital stimulus parts
114. you configure a model library LIB extension as an indude file using the Add to Design or Add as Global button PSpice A D loads every model definition contained in that file If the model library is large you may overload the memory capacity of your system However when developing models you can do the following 1 Initially configure the model library as an include file this avoids rebuilding the index files every time the model library changes 2 When your models are stable reconfigure the include file containing the model definitions as a library file To reconfigure an include file as a library file 1 From the Simulation menu choose Edit Simulation Settings then click the Include Files tab 2 Select the include file that you want to change 3 Click either the Add as Global or the Add to Design button 4 Click Remove to remove the include file entry 163 Chapter 4 Creating and editing models 164 Handling duplicate model names If your model libraries contain duplicate model names PSpice A D always uses the first model it finds This means you might need to resequence the search order to make sure PSpice A D uses the model that you want See Changing model library search order on page 4 166 Note PSpice A D searches design libraries before global libraries so if the new model you want to use is specific to your design and the duplicate definition is global you do not need to make any
115. 1 Time 1 0006 05 oe eV Figure 57 PSpice A D simulation window Main window section The top central portion by default of the simulation window is the main window section where documents such as waveforms circuit description output information etc are displayed within child windows These windows are tabbed by default The tabs at the bottom left show the names of the documents that each child window contains Clicking on a tab brings that child window to the foreground Figure 56 shows the tabbed document windows for Example Example TRAN DAT and Example Example TRAN OUT You can configure the display of these windows to suit your preferences and to make the analysis of the circuit quick and readily understandable These windows can also be resized moved and reordered to suit your needs Output window section The lower left portion of the simulation window provides a listing of the output from the simulation It shows informational warning and error messages from the simulation You can resize and relocate this window to make it easier to read Starting a simulation 303 Chapter 8 Setting up analyses and starting simulation 304 Simulation status window section The lower right portion of the simulation window presents a set of tabbed windows that show detailed status about the simulation There are three tabbed windows in this section the Analysis window the Watch Variable window and the Devices window
116. 110 Functions in arithmetic expressions 466 44 4066 tee deans 111 Syste VANARICS s so eaae kae eh READ EE Ae eee ee eM 113 114 115 116 118 119 119 121 Models supported in the Model Editor 137 Sample diode datasheet values 64 445 66244 8S Ae eee De 148 Part names for custom part generation 00 175 181 183 Tables Table 6 Table 7 Table 8 Table 9 Table 1 Table 2 Table 1 Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 1 Table 1 Table 1 Table 2 Table 3 Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 XXiV 188 189 190 Control system parts s 4 4 40 4 4 Boe ep Coe Oe oe Ro ee Be 199 ABM math function parts 42 2 4 Phe See REGAL ASE RS 213 ABM expression parts s aot4 624 taw ale hee Shaw eh eee Ex 214 PSpice A D equivalent parts nu 4 442 oe8 eee be een RE EO 220 Basic controlled sources in ANALOG OLB 239 Digital primitives summary 46k ee ee ee 243 Digital I O model parameters lt 2 5 2004500 be eRe ee ERE HS 260 Classes of PSpice A D analyses sci s ba bea ek we Yew ee eA 2 288 Execution order for standard analyses 0000 291 PSpice A D output variable formats 04 294 Element definitions for 2 terminal devices 00 295 Element de
117. 16 and 32 bits wide respectively You must define the digital stimulus specification in an external file Using this technique stimulus definitions can be created from scratch or extracted with little modification from another simulation s output file Table 8 lists the properties of the FILESTIMn parts The IO_MODEL IO_LEVEL and PSPICEDEFAULTNET properties describing this part s I O characteristics are provided with default values that rarely need modification However you must define the FILENAME property with the name of the external file containing the digital stimulus specification The SIGNAME property specifies the name of the signal inside the stimulus file which becomes the output from the FILESTIMn part If left undefined the name of the connected net generally a labeled wire determines which signal is used Table8 FILESTIMn part properties Property Description FILENAME Nname of file containing the stimulus specification SIGNAME Name of output signal Defining a digital stimulus Table8 FILESTIMn part properties Property Description IO_MODEL I O model describing the stimulus driving characteristics IO_LEVEL Interface subcircuit selection from one of the four AtoD or DtoA subcircuits provided with the part s I O model PSPICEDEFAULTNET Hidden digital power and ground pins used by the interface subcircuit Name of the default net to use For example a FILESTIMn part can be use
118. 219 T Vbe sat Voltage To include this spec in the model extraction please enter two or more data points in the following table Ie Vbe A g2n2282 Q2N2369 BIT Q2N2369 55C BJT Q2N2369 125C BJT 6 5U 466uA Ube 27 C 1 0mA 18mA Collector Current A en E Vbetsat Vol E Output Adm feb Forward DC EVceta val CB Capacit EEE Capact J E Storage Time E Gain Band Param Value Minimum Maximum Default Active Fixed S 1 434e 014 12 020 1e 006 Tema E m BF 2553 1 1500 joo m NF 1 os 12 m m VAF 74 03 a 1000 wo m mi KF 02847 o0 20 o r m SE 14340 04 a 1 o E o NE 1 307 1 2 is m m BR 6 092 a4 500 i E mi Ready Figure 29 Model Editor workspace with data for a bipolar transistor Using the Model Editor to edit models For more information about the characteristics of devices supported by the Model Editor refer to the online OrCA D PSpice A D Reference Manual 139 Chapter 4 Creating and editing models 140 g To fit the model 1 For each device characteristic that you want to set up a Inthe Spec Entry frame click the tab of the device characteristic b Enter the device information from the data sheet 2 From the Tools menu choose Extract Parameters to extract all relevant model parameters for the current specification A check mark appears in the Active column of t
119. 249 and that the IOLLEVEL is set to 1 PSpice A D determines that IO_STD is the I O model used by U1 Notice how IO_STD identifies the interface subcircuit names AtoD_STD and DtoA_STD to be used for level 1 subcircuit selection If the connection with U1 is an input such as a clock line PSpice A D creates an instance of the subcircuit AtoD_STD X AD_NODE_AtoD1 AD_NODE AD_NODES AtoD G_DPWR G_DGND AtoD_STD PARAMS CAPACITANCE 0 The AtoD_STD interface subcircuit references the DO74 model in its PSpice A D O device declaration This model stated elsewhere in the model libraries describes how to translate an analog signal on the analog side of an interface node to a digital state on the digital side of an interface node Input Output characteristics model D074 doutput sOname X sOvlo 0 8 sOvhi 2 0 siname 0 slvlo 1 5 slvhi 0 8 s2name R s2vlo 0 8 s2vhi 1 4 s3name R s3vlo 1 3 s3vhi 2 0 s4name X s4vlo 0 8 s4vhi 2 0 s5name 1 s5vlo 2 0 sovhi 0 s6name F s6vlo 1 3 s6vhi 2 0 s name F s vlo 0 8 s vhi 1 4 Supposing the output of the 74393 is connected to an analog part via the digital primitive UBUFF At IO_LEVEL set to 1 PSpice A D determines that the DtoA_STD interface subcircuit identified in the IO_STD model should be used subckt DtoA_STD D A DPWR DGND params DRVL 0 DRVH 0 CAPACITANCE 0 N1 A DGND DPWR DIN74 DGTLNET D IO_STD C1 A DGND CAPACI
120. 28 e Tools to create and edit models on page 4 133 Task roadmap This section helps you find other sections in this chapter that are relevant to the model editing task that you want to complete e Ways to create and edit models on page 4 134 How to use the tools These sections explain how to use different tools to create and edit models on their own and when editing schematic pages or parts e Using the Model Editor to edit models on page 4 135 e Editing model text on page 4 152 e Using the Create Subcircuit command on page 4 157 Other useful information These sections explain how to configure and reuse models after you have created or edited them e Changing the model reference to an existing model definition on page 4 159 e Reusing instance models on page 4 160 e Configuring model libraries on page 4 162 What are models A model defines the electrical behavior of a part On a schematic page this correspondence is defined by a part s Implementation property which is assigned the model name Depending on the device type that it describes a model is defined as on of the following e amodel parameter set e asubcircuit netlist Both ways of defining a model are text based with specific rules of syntax Models defined as model parameter sets PSpice A D has built in algorithms or models that describe the behavior of many device types The behavior of these built in models is described by a set of model
121. 4 157 For a list of device types that the Model Editor supports see Model Editor supported device types on page 4 137 If the Model Editor does not support the device type for the model definition that you want to create then you can edit the text using the Model Editor to create a model definition using the PSpice MODEL and SUBCKT command syntax Remember to configure the new model library 134 Using the Model Editor to edit models The Model Editor converts information that you enter from the device manufacturer s data sheet into either e model parameter sets using PSpice MODEL syntax or e subcircuit netlists using PSpice SUBCKT syntax and saves these definitions to model libraries that PSpice A D can search when looking for simulation models model libraries OrCAD Capture OrCAD PSpice A D OrCAD Model Editor exported model file Figure 27 Relationship of the Model Editor to Capture and PSpice A D Note By default the Model Editor creates or updates model libraries To create an exported model file choose the Export command from the Model menu and configure it as an include file For more information see How PSpice A D uses model libraries and the companion sidebar on page 4 163 Using the Model Editor to edit models AA Note A limited version P of the Model Editor is bey not supplied with PSpice A D Basics The Normal view in the Model Editor d
122. 4 and DtoA4 2 Use this property in the PSPICETEMPLATE property definition IO_LEVEL is also a subcircuit parameter used in calls for digital subcircuits Example PSPICETEMPLATE X REFDES A B C D PWR GND MODEL PARAMS n TO_LEVEL I0_LEVEL MNTYMXDLY MNTYMXDLY Defining part properties needed for simulation All digital parts provided in the OrCAD libraries have an 1O_ LEVEL property To find out more about interface subcircuits see Interface subcircuit_ selection by PSpice A D on page 15 445 Note For clarity the PSPICETEMPLATE property value is shown here in multiple lines in a part definition it is specified in one line no line breaks 189 Chapter 5 Creating parts for models All digital parts provided in the OrCAD libraries have a MNTYMXDLY property To find out more about propagation delays see Timing characteristics on page 7 251 and Selecting propagation delays on page 14 428 Note For clarity the PSPICETEMPLATE property value is shown here in multiple lines in a part definition it is specified in one line no line breaks 190 MNTYMXDLY The MNTYMXDLY property defines the digital propagation delay level that PSpice A D must use for a digital part To use the MNTYMXDLY property with a digital part 1 Add the MNTYMXDLY property to the part and assign a value shown in the table below Table 8 Assign this value To use this propagation delay 0 circuit wide defau
123. 476 about 48 adding traces 68 cursors 513 digital display name 531 digital signals and buses 530 displaying simulation results 68 79 expressions 527 functions 528 hysteresis curves 359 limiting waveform data file size 490 logic arithmetic operators 531 messages 437 multiple y axes 368 502 output variables 519 530 for noise 337 526 performance analysis 89 366 placing a cursor on a trace 70 plot 477 printing Probe windows 479 setting colors 480 trace data tables 512 traces 490 traces displaying 505 traces using output variables 519 using markers 487 waveform data file DAT 54 waveform data file formats 495 waveform families 85 313 waveform data file formats 495 waveform families displaying 85 wavform analysis arithmetic expressions 527 output variables 530 WIDTH stimulus property digital 423 worst case analysis 289 398 collating functions 379 example 401 hints 405 introduction 47 model parameter values reports 377 output control 377 overview 398 waveform reports 378 with temperature analysis 380 Z zoom regions Probe windows 505 Index 573 Index 574
124. 53 Chapter 7 Digital device modeling See Input Output characteristics on page 7 257 for more information 254 e If the maximum value is omitted it takes on the typical value if one was specified otherwise it takes on the minimum value e If the typical value is omitted it is computed as the average of the minimum and maximum values Propagation delay calculation The timing characteristics of digital primitives are determined by both the timing models and the I O models Timing models specify propagation delays and timing constraints such as setup and hold times I O models specify input and output loading driving resistances and switching times When a device s output connects to another digital device the total propagation delay through a device is determined by adding the loading delay on the output terminal to the delay specified in the device s timing model Loading delay is calculated from the total load on the output and the device s driving resistances The total load on an output is found by summing the output and input loads OUTLD and INLD in the I O model of all devices connected to that output This total load combined with the device s driving resistances DRVL and DRVH in the I O model allows the loading delay to be calculated Loading delay Roxive Crora In 2 The loading delay is calculated for each output terminal of every device before the simulation begins The total propagation d
125. 55 4046 5 te ee OK ee 497 xxi Figures Figure 118 Figure 119 Figure 120 Figure 121 Figure 122 Figure 123 Figure A 1 xxii Waveform display for EXAMPLE DAT aooaa aaaea aaa 498 Mixed analog digital oscillator design aoaaa 501 Voltage at net 1 with y axis added o aaa a 503 Mixed analog digital oscillator results o a 504 Cursors positioned on a trough and peak of V 1 515 Waveform display for a persistent hazard 518 SETPOINTS gt 246 kh eee ee eh ee ee ee ee ele E f 544 Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 2 1 Table 10 Table 2 1 Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 1 Table 2 Table 3 Table 4 Table 5 DC analysis types ea eb RAK ee GES eR Ome Eee ES eee Oo 43 ACa alysistyp s 624 4 pee SG EEE Oe BEES KER Re ESE 44 Time based analysis types 4 24 00 ke ies teed ed Eee OS 45 Parametric and temperature analysis types 4 46 Statistical analysis types ds4 24 he Oe KOE REE Re OE OLD 47 65 Association of cursors with mouse buttons 70 71 76 81 88 91 98 99 Passive patis sos s oi da e ee RRA ERD ORR Bee ERE Se eS 104 Breakout parts oos se sa so eg Sep e eee eee Sew we hd oe ew ews 105 Operators in expressions 220250484 oe eee he ee Oe
126. 6 e Transient analysis on page 2 72 e AC sweep analysis on page 2 77 e Parametric analysis on page 2 82 e Performance analysis on page 2 89 Chapter 2 Simulation examples Example circuit creation This section describes how to use OrCAD Capture to create the simple diode clipper circuit shown in Figure 2 Vcc R2 ZA D 3 3k D1N3940 R1 c1 A n AAA Mid 4 JH sout 1k 0 47u R3 Z D2 R4 3 3k D1N3940 5 6k a lt salt HR Figure 2 Diode clipper circuit To create a new PSpice project 1 From the Windows Start menu choose the OrCAD Release 9 program folder and then the Capture shortcut to start Capture 2 Inthe Project Manager from the File menu point to New and choose Project 3 Select Analog or Mixed Signal Circuit Wizard 4 Inthe Name text box enter the name of the project CLIPPER 5 Click OK then click Finish No special libraries need to be configured at this time A new page will be displayed in Capture and the new project will be configured in the Project Manager To place the voltage sources 1 In Capture switch to the schematic page editor 56 From the Place menu choose Part to display the Place Part dialog box Add the library for the parts you need to place a Click the Add Library button b Select SOURCE OLB from the PSpice library and click Open In the Part text box type VDC Click OK Move the pointer to the correct position on the
127. 88 320 DC sweep 66 288 306 execution order 291 Fourier 288 frequency response 288 Monte Carlo 289 381 noise 288 333 overview 43 parametric 82 288 364 performance analysis 89 sensitivity worst case 289 398 setup 289 small signal DC transfer 288 317 temperature 289 373 transient 72 288 types 288 approximation problems 551 AtoD interface see mixed analog digital circuits basic components ABM 199 201 basic controlled sources ABM 239 behavioral modeling expressions 555 behavorial parts 106 bias point convergence analysis 557 564 save restore 542 skipping 557 bias point detail analysis 288 example 62 introduction 43 bipolar transistors 137 297 525 527 problems 560 Bode plot 44 80 C CAPACITANCE I O model parameter 456 capacitors 295 CD4000_PWR digital power part 115 CD4000_PWR parts power supply 451 charge storage nets 258 Chebyshev filters 199 203 237 393 circuit file CIR 50 simulating multiple circuits 300 color settings for waveform analysis 480 COMMANDn stimulus property digital 423 comparator 137 CONSTRAINT primitive 106 278 continuous equations problems 550 control system parts ABM 199 controlled sources 220 239 convergence analysis bias point 557 convergence hazard 439 convergence problems 547 approximations 551 behavioral modeling expressions 555 bias point 553 bipolar transistors 560 continuous equations 550 DC s
128. 88 example 72 Fourier analysis 288 hysteresis curves 359 internal time steps 358 introduction 45 overview 342 problems 556 setting up 74 Stimulus Editor 346 stimulus generation 344 switching circuits 359 transient response 356 transistors Darlington model 137 572 transmission lines 525 transport delay 256 triode 217 troubleshooting checklist 98 missing DC path to ground 125 missing ground 124 unconfigured libraries and files 122 unmodeled parts 120 unmodeled pins 123 TSTOREMN I O model 258 TTL 456 tutorials see examples and tutorials U unmodeled parts 120 pins 123 updating plots 509 V VAC stimulus part 116 325 variables in expressions 113 VDC DC stimulus 310 VDC stimulus part 114 116 VECTOR write digital vector file part 538 vector file 538 vendor supplied parts 101 VEXP stimulus part 116 voltage comparator 137 voltage reference 137 voltage regulator 137 voltage source controlled 220 239 VPLOTn write voltage plot part 535 VPRINTn write voltage table part 536 VPULSE stimulus part 116 VPWL stimulus part 116 VPWL_F_N_TIMES stimulus part 117 VPWL_F_RE_FOREVER stimulus part 116 VPWL_N_TIMES stimulus part 117 VPWL_RE_FOREVER stimulus part 116 VSFEM stimulus part 117 VSIN stimulus part 117 VSRC stimulus part 114 116 119 310 325 VSTIM stimulus part 73 116 117 W WATCH view output variable part 534 waveform analysis
129. AL stimulus property digital 422 options DIGERRDEFAULT 440 DIGERRLIMIT 440 DIGIOLVL 249 DIGMNTYMx 459 DIGMNTYSCALE 252 DIGOVRDRYV 264 DIGTYMXSCALE 252 NOOUTMSG 440 NOPRBMSG 440 RELTOL 238 OUTLD I O model 258 output control parts 100 535 output file OUT 64 control parts 535 messages 437 tables and plots 535 output noise total 337 output variables arithmetic expressions 527 digital signals and buses 530 digital trace expression 530 logic arithmetic operators 531 noise waveform analysis 337 526 PSpice A D 292 waveform analysis 519 530 531 waveform analysis functions 528 P PARAM global parameter part 107 parameters 107 parametric analysis 288 364 analyzing waveform families 85 example 82 frequency response vs arbitrary parameter 370 introduction 46 performance analysis 366 setting up 83 temperature analysis 289 373 parasitic capacitance 559 part wizard using custom parts 175 parts creating for models using the Model Editor 142 173 creating new stimulus parts 352 editing graphics 177 grid spacing graphics 178 pins 178 ground 100 non simulation 182 output control 100 pins 123 178 preparing model libraries for part creation 172 properties for simulation 181 saving as global using the Model Editor 142 173 simulation control 100 simulation properties 171 stimulus 100 ways to create for models 171 AGND ground 124 BBREAK GaAsFET 105 behavioral
130. AtoD_STD and DtoA_STD are obtained from the I O model that is referenced by the inverter primitive inside the subcircuit describing the 7404 part The CAPACITANCE DRVL low level driving resistance and DRVH high level driving resistance subcircuit parameter values come from the same I O model After the interface subcircuit calls Pspice A D inserts one or more interface power supply subcircuits The subcircuit name is specified in the I O model for the digital primitive at the interface In this example PSpice A D inserted DIGIFPWR which is the power supply subcircuit used by all TTL models in the model library Digital worst case timing analysis 16 Chapter overview This chapter deals with worst case timing analysis and includes the following sections e Digital worst case timing on page 16 458 e Starting worst case timing analysis on page 16 459 e Simulator representation of timing ambiguity on page 16 459 e Propagation of timing ambiguity on page 16 461 e Identification of timing hazards on page 16 462 e Convergence hazard on page 16 462 e Critical hazard on page 16 463 e Cumulative ambiguity hazard on page 16 464 e Reconvergence hazard on page 16 466 e Glitch suppression due to inertial delay on page 16 468 e Methodology on page 16 469 Chapter 16 Digital worst case timing analysis Note Digital worst case timing is not supported in NAN PSpice A D Basics led Compared to analog worst cas
131. B then C MYLIBS for model libraries type Cr ORCAD LIB Cs MYLIBS in the Library Path text box e Use a semi colon character to separate two path names e Do not follow the last path name with a semi colon 167 Chapter 4 Creating and editing models 168 Creating parts for models Chapter overview This chapter provides information about creating parts for For general information about creating model definitions so you can simulate the model from parts refer to the OrCA D Capture your design using OrCAD Capture User s Guide Topics are grouped into four areas introduced later in this overview If you want to find out quickly which tools to use to complete a given task and how to start then 1 Goto the roadmap in Ways to create parts for models on age 5 171 2 Find the task you want to complete 3 Go to the sections referenced for that task for more information about how to proceed Chapter 5 Creating parts for models 170 Background information These sections provide background on the things you need to know and do to prepare for creating parts e What s different about parts used for simulation on page 5 171 e Preparing your models for part creation on page 5 172 Task roadmap This section helps you find the sections in this chapter that are relevant to the part creation task that you want to complete e Ways to create parts for models on page 5 171 How to use the tools The
132. B and EDIODES LIB European manufactured diodes shipped with your OrCAD programs have identically named device definitions If your design uses a device out of one of these libraries you need to position the model library containing the definition of choice earlier in the list If your system is configured as originally shipped this means you need to add the specific library to the list before NOM LIB Configuring model libraries Changing the library search path For model libraries that are configured without explicit path names PSpice A D first searches the directory where the current design resides then steps down the list of directories specified in the Library Path text box on the Libraries tab of the Simulation Settings dialog box Simulation Settings TRAN Eg General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window Filename Browse Library files x 4 Add as Global nom lib Add to Design Edit Library Path C Program Files OrCAD Capture LibrarySPS pice Browse To change the library search path 1 From the Simulation menu choose Edit Simulation Settings to display the Simulation Settings dialog box 2 Click the Libraries tab 3 In the Library Path text box position the pointer after the directory path that PSpice A D should search before the new path 4 Type in the new path name following these rules Example To search first C ORCAD LI
133. Carlo analysis to view just the output of the filter you place a voltage probe at the output of the filter To collect data for the marked node only 1 3 From the PSpice menu choose New Simulation Profile or Edit Simulation Settings from the PSpice menu If this is a new simulation enter the name of the profile and click OK The Simulation Settings dialog box appears On the Data Collection tab choose the At Probes only option Click OK To run the simulation and load Probe with data 1 From Capture s PSpice menu choose Run to start the simulation When the simulation is complete PSpice A D automatically displays the selected waveform Because PSpice A D ran a Monte Carlo analysis it saved multiple runs or sections of data These are listed in the Available Sections dialog box From PSpice A D s Trace menu choose Performance Analysis Click the Select sections button In the Available Sections dialog box click All 395 Chapter 13 Monte Carlo and sensitivity worst case analyses 5 Click OK To display a histogram for the 1 dB bandwidth 1 From PSpice A D s Plot menu choose Axis Settings 2 Select the X Axis tab For information about performance 3 Inthe Processing Options frame select the analysis see RLC filter example on Performance Analysis check box age 1226 4 Click OK The histogram display appears The Y axis is the percent of samples You can also display this histogr
134. DtoA interface subcircuit AtoD3 Level 3 name of AtoD interface subcircuit DtoA3 Level 3 name of DtoA interface subcircuit AtoD4 Level 4 name of AtoD interface subcircuit DtoA4 Level 4 name of DtoA interface subcircuit DIGPOWER name of power supply subcircuit TSWLH1 switching time low to high for DtoA1 TSWLH2 switching time low to high for DtoA2 TSWLH3 switching time low to high for DtoA3 TSWLH4 switching time low to high for DtoA4 TSWHL1 switching time high to low for DtoA1 260 Input Output characteristics Table3 Digital I O model parameters continued UIO model parameter TSWHL2 TSWHL3 TSWHL4 Description switching time high to low for DtoA2 switching time high to low for DtoA3 switching time high to low for DtoA4 261 Chapter 7 Digital device modeling Node strength calculations are described in Chapter 14 Digital simulation 262 The digital primitives comprising the 74393 part reference the IO_STD I O model in the model libraries as shown model IO STD uio drvh 96 4 drvl 104 AtoDl AtoD_STD AtoD2 AtoD_STD_NX AtoD3 AtoD_STD AtoD4 AtoD_STD_NX DtoAl DtoA_STD DtoA2 DtoA_STD DtoA3 DtoA_STD DtoA4 DtoA_STD tswhll 1 373ns tswlhl 3 382ns tswhl2 1 346ns tswlh2 3 424ns tswhl3 1 5lins tswlh3 3 517ns tswhl4 1 487ns tswlh4 3 564ns Defining Output Strengths The goal of running simulations is to calculate values for each node in the circuit For an
135. ES ee Oe eee ES 505 Scrolling traces 2b ee GES OS MASSER SPAS CREE Hea 507 Sizing digital plots ss id owwk eee Coe oe hw OOS OE ES 508 Modifying trace expressions and labels 509 Moving and copying trace names and expressions 510 Copying and moving labels 2 2 0 0 0 2 0000000 511 Tabulating trace data values 2 6 4 56460 e see bee we ee es 512 Ste CUISOIS ess a a oad a eee Bele eS eS ee a 513 Displaying CUrSOrS eo Bo ah eee Sawa Meh eae Ss 513 Moving CUPSOIS 5 dow ge ee me Sees ae ee St 514 Example using Cursors s2 25 42e44 hes Hetek ie Peas 515 Tracking digital simulation messages 20000 517 Message tracking from the message summary 517 The Simulation Message Summary dialog box 517 Persistent hazards oaoa a a a 518 Message tracking from the waveform aaau oaa 519 Trace expre SSioNS mos ens eoio a a Ke kokoa moa we e 519 Basic output variable form aoao 520 Output variable form for device terminals 521 Analog trace expressions o oo eS bw RR ee EO 527 Trace expression aliases o oo a 527 Arithmetic functions aoaaa e eee 527 Rules for numeric values suffixes oaoa a 529 Digital trace expressions ooa e 24 244 28 Se 2H 530 Chapter 18 Other output options 533 Ghapter overview 242560252629 2444024 doe ERR HEE HO 533 Viewing analog results in the PSpice window 534 Writing additional re
136. I ABM1 I 1 I ABM2 I 2 I ABM3 I 3 I The following examples illustrate a variety of ABM expression part applications Example one Suppose you want to set an output voltage on net 4 to 5 volts times the square root of the voltage between nets 3 and 2 You could use an ABM2 part which takes two inputs and provides a voltage output to define a part like the one shown in Figure 43 In this example of an ABM device the output voltage is set to 5 volts times the square root of the voltage between net 3 and net 2 The property settings for this part are as follows EXP 1 BY EXP2 SQRT V IN2 IN1 This will produce a PSpice A D netlist declaration like this ESQROOT 4 O VALUE 5V SQRT V 3 2 Example two GPSK is an oscillator for a PSK Phase Shift Keyed modulator Current is pumped from net 11 through the source to net 6 Its value is a sine wave with an amplitude of 15 mA and a frequency of 10 kHz The voltage at net 3 can shift the phase of GPSK by 1 radian volt Note the use of the TIME parameter in the EXP2 expression This is the PSpice A D internal sweep variable used in transient analyses For any analysis other than transient TIME 0 This could be represented with an ABM1 I part single input current output like the one shown in Figure 44 This part is characterized by the following properties EXP1 15ma SIN EXP2 6 28 10kKHzZ TIME EXP3 V ZIN This produces a PSpice A D netlist declaration
137. ICEDEFAULTNET CD4000 series CMOS hidden power supply pins for VDD and VSS DIGIFPWR VOLTAGE TTL power supply voltage PSPICEDEFAULTNET TTL hidden power PWR and ground GND pins ECL_10K_ PWR VEE ECL power supply voltages ECL_100K_PWR VCC1 VCC2 PSPICEDEFAULTNET ECL hidden power supply pins for VEE VCC1 and VCC2 451 Chapter 15 Mixed analog digital simulation Note This procedure applies to all logic families 452 To create a custom digital power supply 1 Place the appropriate power supply part listed in Table 17 in your design by logic family 2 Rename the power supply power and ground pins PSPICEDEFAULTNET properties 3 Reset the power supply power and ground voltages as required 4 For any digital part instance that uses the power supply set its appropriate PSPICEDEFAULTNET pin properties to the power and ground pins created by the secondary power supply Overriding CD4000 power supply voltage throughout a design Designs using CD4000 parts often require power supply voltages other than the default 5 0 volts supplied by the standard CD4000_PWR power supply part If needed you can override the power supply voltage for all CD4000 parts in a design The default power supply nodes used by CD4000 parts are named G_CD4000_VDD and G_CD4000_VSS as created by the power supply subcircuit CD4000_PWR This supply defaults to 5 0 volts You can override the voltage across these two nodes by defining values for the
138. ICETEMPLATE property must match the pin names on the part e The number and order of the pins listed in the PSPICETEMPLATE property must match those for the associated MODEL or SUBCKT definition referenced for simulation e The first character in a PSPICETEMPLATE must be a PSpice A D device letter appropriate for the part such as Q for a bipolar transistor PSPICETEMPLATE syntax The PSPICETEMPLATE contains e regular characters that the schematic page editor interprets verbatim e property names and control characters that the schematic page editor translates Regular characters in templates Regular characters include the following e alphanumerics e any keyboard part except the special syntactical parts used with properties amp e white space An identifier is a collection of regular characters of the form alphabetic character any other regular character Property names in templates Property names are preceded by a special character as follows 1 1 1 1 1 amp lt identifier gt The schematic page editor processes the property according to the special character as shown in the following table Table 4 This syntax Is replaced with this lt id gt Value of lt id gt Error if no lt id gt attribute or if no value assigned amp lt id gt Value of lt id gt if lt id gt is defined lt id gt s s Text between s s separators if lt id gt is defined lt id gt s
139. INTEG ABM 199 206 LAPLACE ABM 200 210 LIMIT ABM 199 202 LOG ABM 200 213 LOG10 ABM 200 213 LOPASS ABM 199 203 MULT ABM 199 201 NODESETn initial bias point 544 PWR ABM 200 213 570 PWRS ABM 200 213 SIN ABM 200 213 SOFTLIM ABM 199 202 SQRT ABM 200 213 SUM ABM 199 201 TABLE ABM 199 206 TAN ABM 200 213 performance analysis 366 example 89 goal functions 367 phase 524 PINDLY primitive 106 271 plots sizing 508 plots in waveform analysis 477 power supplies 456 G_DGND 456 G_DPWR 456 A D interfaces 114 analog 114 default digital power supply selection by PSpice A D 449 DIGIFPWR 456 digital custom CD4000 TTL or ECL 450 453 primitives digital 272 PRNTDGTLCHG write digital state changes part 537 Probe windows plot update methods 509 plots 477 478 printing Probe windows 479 scrolling 507 setting colors 480 sizing plots 508 trace data tables 512 traces displaying 68 zoom regions 505 propagation delay see timing model properties part for simulation 181 PSpice default shortcut keys 505 waveform analysis 476 multiple y axes 368 PSpice A D about 42 default power supply selection 449 expressions 109 functions 111 output file OUT 64 535 output variables 292 PSpice A D equivalent parts 220 221 simulation status window 301 534 starting 299 using with other programs
140. NG 24 0 25 6 Sy ae RE SOE OA ORE eww es Specifying expressions eG ok ge Ree RS RS Defining power supplies 2246224444 8026845 24 For the analog portion of your circuit For A D interfaces in mixed signal circuits Default digital power supplies Custom digital power supplies Denning stimuli s cs 2s eue a kog g Bee Ie ee ook ER SS Analog Stal 2 cg ete e e Kee ee aa a a S Using VSTIM and ISTIM lt 446 s2r4vsao eee kh ban If you want to specify multiple stimulus types Digital stimuli sca e e Bowl SS ee we BE HS Bw RO Things to watch fot cy hike ane eee ERA He Se Unmodeled parts 2 44 0444 6d EGS ode Poe aH Do this if the part in question is from the OrCAD libraries Check for this if the part in question is custom built Unconfigured model stimulus or include files Check for this 20 000000 0 ee rA erk Unmodeled pins 4 amp amp lt eS 4 pak eee ee Ewe ee A Check for this 0 0 00 00 AREAN N Contents Contents Chapter 4 vi Missing ground 4 i6 lt i seme hos ew wee bee ew Re ee SS 124 Checkfor is 2 2 6 66 bbb eee ee ae 124 Missing DC path to ground 2 a cee he eee aS CMe eee RS 125 Check forthis 2 0 0 0 0 00002 ee ey ea 125 Creating and editing models 127 Chapter Overview s 44464 smaa aatre dio sa e k OR EY Se Ra 127 What are models 4 5 anaa 408 8e e eRe Bee ea we HeS ea Sus 129 Models defined as
141. ORE ae Bes 483 Setting up waveform display from Capture 483 Viewing waveforms while simulating 484 Configuring update intervals 00 0 485 Interacting with waveform analysis during simulation 485 Pausing a simulation and viewing waveforms 486 Using schematic page markers to add traces 487 Limiting waveform data filesize 25 5 8465 08 bee ewes 490 Limiting file size using markers 0 490 Limiting file size by excluding internal subcircuit data 492 Limiting file size by suppressing the first part of simulation output ise aw he ah Se amp dow Ew 492 Using simulation data from multiple files 493 Appending waveform datafiles 0 493 Adding traces from specific loaded waveform data files 494 Saving simulation results in ASCII format 495 A alog example enige rue s e ee Phe ESE ELE ESAS 497 Running the simulation a aaa 497 Displaying voltages on nets oaoa aa a 499 Mixed analog digital tutorial aoaaa a 500 About digital states ne aoaaa a 500 About the oscillator circuit o oo ee 501 Setting p Thedesign ss s osaa sorae ONE ee aoak ES 501 Contents Running the simulation 2 26444 e686 ee ees poe ee we 502 Analyzing simulation results ss 40 460 e 2 Pa wk ee ERS 502 User interface features for waveform analysis 505 ZOOM TEgIONS ose taa pe hee eS tk
142. OrCAD PSpice A D User s Guide Copyright 1998 OrCAD Inc All rights reserved Trademarks OrCAD OrCAD Layout OrCAD Express OrCAD Capture OrCAD PSpice and OrCAD PSpice A D are registered trademarks of OrCAD Inc OrCAD Capture CIS and OrCAD Express CIS are trademarks of OrCAD Inc Microsoft Visual Basic Windows Windows NT and other names of Microsoft products referenced herein are trademarks or registered trademarks of Microsoft Corporation All other brand and product names mentioned herein are used for identification purposes only and are trademarks or registered trademarks of their respective holders Part Number 60 30 632 First edition 30 November 1998 Technical Support 503 671 9400 Corporate offices 503 671 9500 OrCAD Japan K K 81 45 621 1911 OrCAD UK Ltd 44 1256 381 400 Fax 503 671 9501 General email info orcad com Technical Support email techsupport orcad com World Wide Web http www orcad com OrCAD Design Network ODN http www orcad com odn 9300 SW Nimbus Ave Beaverton OR 97008 USA Contents Part one Chapter 1 Before you begin xxvii Welcome to OrCAD 2 0 0 000 ee xxvii OrCAD PSpice A D overview aaaea bbw ewe See xxviii How to use this guide aaa aa a xxix Typographical conventions aooo e eee xxix Related documentation 0 0 0 0 ee ee XXX Online Help 2 6 249264 6 646824 GEG bE EREH Bt LH XXXi If you don t have the standard PSpice A D p
143. Other files that you can configure for simulation 51 Model library oie 212624 2486004 344 26854 eo 52 Stimulus file 0 0 000 53 melude file shu ov Shee ee ie ee BO ee HB wd 53 Configuring model library stimulus and include files 0 0 0 0 ee dka 53 Files that PSpice A D generates dee esa 4 eg ee Pe ee ee 54 Waveform datafile 0 0 0 0000000000004 54 PSpice output file 24 es sta os tok ven eer ad BK Se 54 Chapter 2 Simulation examples 55 Chapter overview Mak A aS REE CES EASS Se eRe 55 Example circuit creation s aoaaa Bax des cd G40 R824 56 Finding out more about setting up your design 61 Running PSpice A D 2 8 e4 46 She Seed dha hee eae Ss 62 Performing a bias point analysis lt 0 es eaves es ees 62 Using the simulation output file 4 eau eee Bo ed aes oes 64 Finding out more about bias point calculations 65 DC sweep a alysis sot saci ee ke ee ea RP eee 2 ee 66 Setting up and running a DC sweep analysis 66 Displaying DC analysis results 2 2 0 0 02 000 68 Finding out more about DC sweep analysis 71 Transi ntanalysis o soe oes ko ea ea ba eee ee REE ERS BRO 72 Finding out more about transient analysis 76 BC sweep analysis s s tde opus ee amp ere RH posp k EE OA eae Be 77 Setting up and running an AC sweep analysis 77 AC sweep analysis results oo a ak ee HS Sk Se Ka 79 Finding out
144. Out qu Cin In B Qi ki Q2N2222 du Vin E T AC 1 v RAb2 7 Abmod 720 k Figure 86 Simple biased BJT amplifier Figure 87 is the circuit file used to run one of the following e a parametric analysis STEP shown enabled in the circuit file that sets the value of resistor Rb2 by stepping model parameter R through values spanning the specified DEV tolerance range or e a worst case analysis shown disabled in the circuit file that allows PSpice A D to determine the worst case value for parameter R based upon a sensitivity analysis 401 Chapter 13 Monte Carlo and sensitivity worst case analyses 402 Only one of these analyses can run in any given simulation Note The AC and worst case analysis specifications AC and WC statements are written so that the worst case analysis tries to minimize Vm OUT at 100 kHz The netlist and circuit file in Figure 87 are set up to run either a parametric STEP or worst case WC analysis of the specified AC analysis These simulations demonstrate the conditions under which worst case analysis works well and those that can produce misleading results when Worst case analysis comparing monotonic and non monotonic output with a variable parameter lib xxxx x Tnput signal and blocking capacitor Vin In 0 ac 1 Cin In B lu kkk k Amp1 ifi er KKKKK gain increases with small increase in Rb2 but device saturates if Rb2 is maximized Vcc V
145. P1 EXP4 ABM1 I 1 input I out EXP1 EXP4 ABM2 I 2 inputs I out EXP1 EXP4 ABM3 I 3 inputs I out EXP1 EXP4 Control system parts Basic components The basic components provide fundamental functions and in many cases do not require specifying property values These parts are described below CONST VALUE constant value The CONST part outputs the voltage specified by the VALUE property This part provides no inputs and one output SUM The SUM part evaluates the voltages of the two input sources adds the two inputs together then outputs the sum This part provides two inputs and one output MULT The MULT part evaluates the voltages of the two input sources multiplies the two together then outputs the product This part provides two inputs and one output GAIN GAIN constant gain value The GAIN part multiplies the input by the constant specified by the GAIN property then outputs the result This part provides one input and one output DIFF The DIFF part evaluates the voltage difference between two inputs then outputs the result This part provides two inputs and one output 201 Chapter 6 Analog behavioral modeling 202 Limiters The Limiters can be used to restrict an output to values between a set of specified ranges These parts are described below LIMIT HI upper limit value LO lower limit value The LIMIT part constrains the output voltage to a value between an upper limit set wit
146. PICEDEFAULTNET VSS G_CD4000_VSS 0 volts ECL10K PSPICEDEFAULTNET VEE G_ECL_10K_VEE 5 2 volts PSPICEDEFAULTNET VCC1 Se cree naar 0 ee PSPICEDEFAULTNET VCC2 8C BCL 10K_VCC2 0 volts ECL 100K PSPICEDEFAULTNET VEE G_ECL_100K_VEE 4 5 volts PSPICEDEFAULTNET VCC1 gee hoe PSPICEDEFAULTNET vcc2 G ECL 100K_ Peas The PSPICEDEFAULTNET pin properties have the same default values as the digital power and ground nodes created by the default power supply These node assignments are passed from the part instance to the digital primitives describing its behavior connecting any digital primitive affected by an analog connection to the correct power supply Creating custom digital power supplies Each digital part model has optional digital power and ground nodes that you can use to specify custom power supplies To do this use one of the digital power supplies listed in Table 17 below in your design and redefine the digital power supply nodes Specifying digital power supplies Table17 Digital power supply parts in SPECIAL OLB fl D X model Part name CD4000 power supply CD4000_PWR TTL power supply DIGIFPWR ECL 10K power supply ECL_10K_PWR ECL 100K power supply ECL_100K_PWR The properties relevant to creating custom power supplies are shown in Table 18 Table 18 Digital power supply properties Part name Property Description CD4000_PWR VOLTAGE CD4000 series CMOS power supply voltage PSP
147. PSpice A D with Probe the Stimulus Editor and the Model Editor which are circuit analysis programs that let you create simulate and test analog and digital circuit designs This manual provides examples on how to specify simulation parameters analyze simulation results edit input signals and create models PSpice A D Basics is a limited version that does not include the Stimulus Editor OrCAD PSpice with Probe is a circuit analysis program that lets you create simulate and test analog only circuit designs OrCAD PSpice Optimizer which is an analog performance optimization program that lets you fine tune your analog circuit designs XXX Related documentation The following table provides a brief description of those manuals available online only This online manual Provides this OrCAD PSpice A D Online Reference Manual OrCAD Application Notes Online Manual OrCAD PSpice Library List Reference material for PSpice A D Also included detailed descriptions of the simulation controls and analysis specifications start up option definitions and a list of device types in the analog and digital model libraries User interface commands are provided to instruct you on each of the screen commands A variety of articles that show you how a particular task can be accomplished using OrCAD s products and examples that demonstrate a new or different approach to solving an engineering problem A complete li
148. Profile SCHEMATICT DC Sweep p Simulation n running circuit fle for profle DC Sweep Reading and checking circuit Circuit read in and checked no eors Stat 10 Vyn 15 manie DC Analysis DC Analysis finished Sradsion corgets ETE Anasi A Watch Devices 7 For Help press F1 VVin 15 100 ERNE Oe Figure9 Voltage at In Mid and Out DC sweep analysis 69 Chapter 2 Simulation examples This example uses the cursors feature to view the numeric values for two traces and the difference between them by placing a cursor on each trace Table 10 Association of cursors with mouse buttons cursor 1 left mouse button cursor 2 right mouse button ioiU In U Mid v U Out Figure 11 Trace legend with cursors activated Your ability to get as close to 4 0 as possible depends on screen resolution and window size Figure 12 Trace legend with V Mid symbol outlined 70 1 To place cursors on V In and V Mid From PSpice s Trace menu point to Cursor and choose Display Two cursors appear for the first trace defined in the legend below the x axis V In in this example The Probe Cursor window also appears To display the cursor crosshairs a Position the mouse anywhere inside the Probe window b Click to display the crosshairs for the first cursor C Right click to display the crosshairs for the second cursor In the trace legend the part for
149. Right click to end adding new points To select a time and value scale factor for PWL stimuli 1 Select the PWL trace by clicking on its name 2 Select Attributes from the Edit menu or click the corresponding toolbar button The Stimulus Editor utility PWL stimuli are a little different since they are a series of time value pairs This provides a fast way to scale a PWL stimulus 355 Chapter 11 Transient analysis 354 Deleting and removing traces To delete a trace from the displayed screen select the trace name by clicking on its name then press Del This will only erase the display of the trace not delete it from your file The trace is still available by selecting Get from the Stimulus menu To remove a trace from a file select Remove from the Stimulus menu Note Once a trace is removed it is no longer retrievable Delete traces with caution Manual stimulus configuration Stimuli can be characterized by manually starting the Stimulus Editor and saving their specifications to a file These stimulus specifications can then be associated to stimulus instances in your schematic or to stimulus symbols in the symbol library To manually configure a stimulus 1 Start the Stimulus Editor by double clicking on the Stimulus Editor icon in the OrCAD program group 2 Open a stimulus file by selecting Open from the File menu If the file is not found in your current library search path you are prompted for a new
150. S 557 The dynamic range of TIME 23 00 5 eee BY Pew RRS Ret 557 Failure at the first time step 46s 4 ok 2 ee hee ook eR eS 558 Parasitic capacitances Gon cdace PE REE SEES EAR ees 559 Inductors and transformers 0 0 00 eee eee 559 Bipolar transistors substrate junction 0 560 Diagnostics s se east feet She ag he one Gee wes Oe eee 561 Index 563 xvii Contents xviii Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 User configurable data files that PSpice A D reads 51 Diode clipper circuit ee eee Oe Roe eed PR Re ee OSES 56 C nnect n PONS s cr oe sae a oe bode ew dees bee ew 59 PSpice A D simulation output window 05 62 Simulation output file bik ee ee PR KR ROEDER ew ew Es 64 DC sweep analysis settings oh db Eade SE RES RRO ES 67 Probe window 6 bw sk ek 4 Ree RS Rw RD ERE BR ORO Dee BRS 68 Clipper circuit with voltage marker on net Out 69 Voltage at In Mid and Out 8 264 4 2422 4h 42 Fae Eads 4 69 Trace legend with cursors activated 0 s 444 ei oe ee ee eda wea 70 Trace legend with V Mid symbol outlined 0 70 Voltage d
151. S filter part example ripple is 0 1 dB and the minimum stop band attenuation is 50 dB This will produce a PSpice A D netlist declaration like this EHIGHPASS 5 O CHEBYSHEV V 10 HP 1 2K 800 1dB 50dB BANDPASS RIPPLE pass band ripple in dB STOP stop band attenuation in dB FO F1 cutoff frequencies F2 F3 The BANDPASS part is characterized by four cutoff frequencies The attenuation values RIPPLE and STOP define the maximum allowable attenuation in the pass band and the minimum required attenuation in the stop 204 band respectively The BANDPASS part provides one input and one output Figure 37 shows an example of a BANDPASS filter device This is a band pass filter with the pass band between 1 2 kHz and 2 kHz and stop bands below 800 Hz and above 3 kHz The pass band ripple is 0 1 dB and the minimum stop band attenuation is 50 dB This will produce a PSpice A D netlist declaration like this EBANDPASS 5 0 CHEBYSHEV V 10 BP 800 1 2K 2K 3K 1dB 50dB BAN DRE RIPPLE _ is the pass band ripple in dB STOP is the stop band attenuation in dB FO F1 are the cutoff frequencies F2 F3 The BANDRE part is characterized by four cutoff frequencies The attenuation values RIPPLE and STOP define the maximum allowable attenuation in the pass band and the minimum required attenuation in the stop band respectively The BANDRE J part provides one input and one output Figure 38 shows an example of a BANDRE fil
152. Simulation Error Message x PERSISTENT Hazard at time 73ns On OUTPUT Port p15 Caused By unio Violation at time 21ns peace B1 26 008n 8 Minimum nal MDM 5ns B2 25 000n 1 NODE clock1 measured WIDTH ins dif 5 Fere clock1 width too short E Moot_ddst Figure 123 Waveform display for a persistent hazard Trace expressions Message tracking from the waveform Trace segments with associated diagnostics are displayed in the foreground color specified in your PSPICE INI file This color is different from those used for standard state transitions To display explanatory message text 1 Double click within the tagged region of a trace Trace expressions Traces are referred to by output variable names Output variables are similar to the PSpice A D output variables specified in the Simulation Settings dialog box for noise Monte Carlo worst case transfer function and Fourier analyses However there are additional alias forms that are valid for trace expressions Both forms are discussed here To add traces using output variables 1 From the Trace menu choose Add Trace to display the Add Traces dialog box 2 Construct a trace expression using any combination of these controls e Inthe Simulation Output Variables frame click You can display a subset of the available output variables simulation output variables by selecting or clearing the variable type check boxes in the Simulation Output
153. Specify the AC sweep analysis parameters as described on page 10 327 Enable the Noise Analysis check box Enter the noise analysis parameters as follows Noise analysis 335 Chapter 10 AC analyses Table 8 In this text box Type this To find out more about valid syntax see Output Voltage Output variables on page 8 292 I V Source Example U1 V2 Note In the Probe window you can view Interval the device noise contributions at every frequency specified in the AC sweep The Interval parameter has no effect on what PSpice A D writes to the Probe data file A voltage output variable of the form V node node where you want the total output noise calculated The name of an independent current or voltage source where you want the equivalent input noise calculated Note f the source is in a lower level of a hierarchical schematic separate the names of the hierarchical devices with periods An integer n designating that at every n frequency you want to see a table printed in the PSpice output file out showing the individual contributions of all of the circuit s noise generators to the total noise 7 Click OK to save the simulation profile 336 Analyzing Noise in the Probe window You can use these output variable formats to view traces for device noise contributions and total input or output noise at every frequency in the analysis Noise analysis For a break do
154. Switching Regulator Analysis Electronic Design March 5 1981 359 Chapter 11 Transient analysis 360 Capture Netlist R_RIN 1 2 50 R_RC1 0 3 50 R_R 3 5 185 R_R2 5 8 760 R_RC2 0 6 100 R_RE 4 8 260 R_RTH2 7 0 85 C_CLOAD 0 7 SPF V_VEE 8 0 de 5 V_VIN 10 PWL O 8 IMS 1 0V 2MS 1 8V R_RTH1 8 7 125 Q_Q 3 2 4 QSTD Q_Q2 6 5 4 QSTD Q_Q3 0 6 7 QSTD Q_04 0 6 7 QSTD Figure 68 Netlist for Schmitt trigger circuit The QSTD model is defined as MODEL OSTD NPN is 1e 16 bf 50 br 0 1 rb 50 rc 10 tf 12ns tr 5ns cje 4pF pe 8 me 4 cjc 5pF pc 8 mc 333 ccs 1pF va 50 Instead of using the DC sweep to look at the hysteresis use the transient analysis Print Step 01ms and Final Time 2ms sweeping VIN from 1 8 volts to 1 0 volts and back down to 1 8 volts very slowly This has two advantages e it avoids convergence problems e it covers both the upward and downward transitions in one analysis After the simulation in the Probe window in PSpice A D the X axis variable is initially set to be Time By selecting X Axis Settings from the Plot menu and clicking on the Axis Variable button you can set the X axis variable to be V 1 Then use Add on the Trace menu to display V 7 and change the X axis to a user defined data range from 1 8V to 1 0V Axis Settings on the Plot menu This plots the output of the Schmitt trigger against its input which is the desired outcome The result looks sim
155. TANCE 0 1pF ends For this subcircuit the DRVH and DRVL parameters values specified in the IO_STD model would be passed to it The interface subcircuits in the model libraries do not currently use these values 269 Chapter 7 Digital device modeling The DtoA_STD interface subcircuit references the DIN74 model in its PSpice A D N device declaration This model stated elsewhere in the libraries describes how to The DINPUT model parameters are translate a digital state into a voltage and impedance described under PSpice A DN devices in model DIN74 dinput the online OrCA D PSpice A D sOname 0 sOtsw 3 5ns sOrlo 7 13 Reference Manual sOrhi 389 7ohm 0 09v slname 1 sltsw 5 5ns slrlo 46 sirhi 200 1400hm 3 5v s2name X s2tsw 3 5ns s2rlo 42 9 s2rhi ll6 31 30hm 1 35v s3name R s3tsw 3 5ns s3rlo 42 9 s3rhi ll6 31 30hm 1 35v s4name F s4tsw 3 5ns s4rlo 42 9 s4rhi ll6 31 30hm 1 35v sSname Z s5tsw 3 5ns s5rlo 200K s5rhi 200K Each state is turned into a pullup and pulldown resistor pair to provide the correct voltage and impedance The Z state is accounted for as well as the 0 1 and X logic levels You can create your own interface subcircuits DINPUT models DOUTPUT models and I O models like these for technologies not currently supported in the model libraries OrCAD recommends that you save these in your own custom model library which you can
156. The Analysis window provides a running log of values of simulation variables parameters such as Temperature Time Step and Time The Watch Variable window displays watch variables and their values These are the variables setup to be monitored during simulation The Devices window displays the devices that are being simulated DC analyses Chapter overview This chapter describes how to set up DC analyses and includes the following sections e DC Sweep on page 9 306 e Bias point on page 9 315 e Small signal DC transfer on page 9 317 e DC sensitivity on page 9 320 Chapter9 DC analyses 306 DC Sweep Minimum requirements to run a DC sweep analysis Minimum circuit design requirements Table1l DC sweep circuit design requirements Swept variable type Requirement voltage source temperature current source model parameter global parameter voltage source with a DC specification VDC for example none current source with a DC specification IDC for example PSpice A D model MODEL global parameter defined with a parameter block PARAM DC Sweep Minimum program setup requirements Simulation Settings Example ix General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window Analysis type r Sweep variable C Voltage source Name fv a Current source AGE tone ro pipet C Global parameter Prima
157. These power supply subcircuits create the digital power and ground nodes that are the defaults for all parts in that family If multiple digital primitives from the same logic family are involved with analog digital interfaces one instance of the power supply subcircuit is created with all primitives connected to the power supply nodes Specifying digital power supplies If you use custom digital parts created in technologies other than those provided in the standard model library you may need to create your own digital power supplies 449 Chapter 15 Mixed analog digital simulation The default I O models and power supply subcircuits are found in DIG_IO LIB The four default power supplies provided in the model library are DIGIFPWR TTL CD4000_ PWR CD4000 series CMOS ECL 10K_PWR ECL 10K and ECL 100K_PWR ECL 100K When creating custom power supplies you can refer to the power supply definitions in DIG_10 LIB for examples of power supply subcircuit definitions 450 Table 16 summarizes the default node names and values For instance TTL power supplies have a default value of 5 0 volts at analog digital interfaces Table16 Default digital power ground pin connections Digital pow er Logic family ground pin properties Default digital power ground nodes TTL PSPICEDEFAULTNET PWR G_DPWR 5 0 volts PSPICEDEFAULTNET GND G_DGND 0 volts CD4000 PSPICEDEFAULTNET VDD G_CD4000_VDD 5 volts PS
158. Things you need to know Note The Model Editor is not induded in PSpice A D Basics A 50 What is the Model Editor The Model Editor is a model extractor that generates model definitions for PSpice A D to use during simulation All the Model Editor needs is information about the device found in standard data sheets As you enter the data sheet information the Model Editor displays device characteristic curves so you can verify the model based behavior of the device When you are finished the Model Editor automatically creates a part for the model so you can use the modeled part in your design immediately Files needed for simulation To simulate your design PSpice A D needs to know about e the parts in your circuit and how they are connected e what analyses to run e the simulation models that correspond to the parts in your circuit and e the stimulus definitions to test with This information is provided in various data files Some of these are generated by Capture others come from libraries which can also be generated by other programs like the Stimulus Editor and the Model Editor and still others are user defined Files that Capture generates When you begin the simulation process Capture first generates files describing the parts and connections in your circuit These files are the netlist file and the circuit file that PSpice A D reads before doing anythin
159. To add a trace from a specific loaded waveform data file 1 3 In PSpice A D from the Trace menu choose Add Trace to display the Add Traces dialog box In the Trace Expression text box type an expression using the following syntax trace_expression fn where n is the numerical order from left to right of the waveform data file as it appears in the PSpice title bar or trace_expression s fn where s is a specific data section of a specific waveform data file Click OK To identify the source file for an individual trace 1 In the trace legend double click the symbol for the trace you want to identify Figure 115 The Section Information dialog box appears containing the trace name and if there is more than Viewing waveforms one waveform data file loaded in the plot the full path for the file from which the trace was generated Also listed is information about the simulation that generated the waveform data file and the number of data points used Figure 116 Section Information G V C1 1 This trace came from one simulation run from the data file one C OrCAD Projects Copy of clipper SCHEMATIC1 Pa dat Step param Aval 100 Temperature 27 0 Deg Simulation at 10 08 13 on 10 27 98 The simulator created 14 data points This trace is being displayed using 73 data points Figure 116 Section information message box Saving simulation results in ASCII format The default waveform data f
160. V In is outlined in the crosshair pattern for each cursor resulting in a dashed line as shown in Figure 11 Place the first cursor on the V In waveform a Click the portion of the V In trace in the proximity of 4 volts on the x axis The cursor crosshair appears and the current X and Y values for the first cursor appear in the cursor window b To fine tune the cursor location to 4 volts on the x axis drag the crosshairs until the x axis value of the Al cursor in the cursor window is approximately 4 0 You can also press 3 and for tighter control Place the second cursor on the V Mid waveform a Right click the trace legend part diamond for V Mid to associate the second cursor with the Mid waveform The crosshair pattern for the second cursor outlines the V Mid trace part as shown in Figure 12 0 Right click the portion on the V Mid trace that is in the proximity of 4 volts on the x axis The X and Y values for the second cursor appear in the cursor window along with the difference dif between the two cursors X and Y values DC sweep analysis C To fine tune the location of the second cursor to 4 volts on the x axis drag the crosshairs until the x axis value of the A2 cursor in the cursor window is approximately 4 0 You can also press shif gt and Shift for tighter control Figure 13 shows the Probe window wi
161. Variables frame Variable types not generated by the circuit e Inthe Functions or Macros frame select operators functions constants or macros e Inthe Trace Expression text box type in or edit simulation are dimmed output variables operators functions constants l l or macros For more information about trace expressions see Analog trace expressions on page 17 527 and Digital trace expressions on page 17 530 3 Ifyou want to change the name of the trace expression as it displays in the Probe window use the following syntax 519 Chapter 17 Analyzing waveforms trace expression display name 4 Click OK Basic output variable form This form is representative of those used for specifying some PSpice A D analyses lt output gt A C suffix lt name gt name Table 4 This placeholder Means this lt output gt type of output quantity V for voltage or I for current digital values do not require a prefix A C suffix quantity to be reported for an AC analysis For a list of valid AC suffixes see Table 8 on page 17 524 lt name gt name specifies either the net or net net pair for which the voltage is to be reported or the device for which a current is reported where e net specifies either the net or pin id lt fully qualified device name gt lt pin name gt A fully qualified device name consists of the e device name specifies the fully full hierarchical path follow
162. a general purpose ABM part used to take the input voltages from anode grid and cathode Assume the following associations e V anode is associated with V IN1 e V grid is associated with V IN2 e V cathode is associated with V IN3 The expression property EXP1 then represents V grid cathode and the expression property EXP2 represents 0 12 V anode cathode When the template substitution is performed the resulting VALUE is equivalent to the following V V grid cathode 0 12 V anode cathode 217 Chapter 6 Analog behavioral modeling 218 The part would be defined with the following characteristics EXP1 V IN2 IN3 EXP2 0 12 V IN1 IN3 This works for the main operating region but does not model the case in which the current stays 0 when combined grid and anode voltages go negative We can accommodate that situation as follows by adding the LIMIT part with the following characteristics HI 1E3 LO 0 This part instance LIMIT1 converts all negative values of V 12 v to 0 and leaves all positive values up to 1 kV alone For a more realistic model we could have used TABLE to correctly model how the tube turns off at 0 or at small negative grid voltages We also need to make sure that the current becomes zero when the anode alone goes negative To do this we can use a DIFF device immediately below the ABM3 device to monitor the difference between V anode and V cathode and output the d
163. a transient analysis PSpice automatically selects the transient analysis data section from the waveform data file This means that the Available Selection dialog box is skipped and a Probe window appears immediately Analyzing simulation results To view the clock input to the inverter voltage at net 1 1 3 From PSpice s Trace menu choose Add Trace to display the Add Traces dialog box In the Simulation Output Variables list click V 1 to plot the voltage at net 1 Click OK To add a second y axis to avoid analog trace overlap 1 From the Plot menu choose Axis Settings to display the Axis Settings dialog box The X Axis tab is active by default a Inthe Data Range frame choose User Defined and set the range from Ous to 10us if this is not already set b Inthe Scale frame select Linear if this is not already set Click the Y Axis tab a Inthe Data Range frame choose User Defined and set the range from 5 to 5 This will change the range for the current y axis 3 b Click OK From the Plot menu choose Add Y Axis The Probe window display should now look like Figure 120 below 5 094 Time Figure 120 Voltage at net 1 with y axis added To view traces for V 3 RESET and OUT 1 From the Trace menu choose Add Trace to display the Add Traces dialog box In the Simulation Output Variables list click V 3 RESET and OUT The trace names appear in the Trace Expressi
164. a using the mouse 1 Inthe digital area drag the mouse pointer left or right to produce two vertical bars Pra zoom bars digital qa op S QB u ac comp_out J F J J J q J 2 From the View menu point to Zoom then choose Area PSpice changes the plot display to the area in between the selection bars If the plot includes an analog area it is Zoomed in as well User interface features for waveform analysis Shortcut keys Many of the menu commands in PSpice A D have equivalent keyboard shortcuts For instance after placing a selection rectangle in the analog portion of the plot you can type Ctrl A instead of choosing Area from the View menu For a list of shortcut keys search on Keyboard Shortcuts in PSpice A D Help J Ql Click the mouse anywhere on the plot to remove the vertical bars without zooming 505 Chapter 17 Analyzing waveforms Click anywhere on the plot to remove the selection rectangle without zooming 506 To zoom in the analog area using the mouse 1 Drag the mouse pointer to make a selection rectangle as shown below election rectangle analog 8 QU o UGS UCS v UCcomp_out 2 From the View menu point to Zoom then choose Area PSpice A D changes the plot to display the region within the selection rectangle The digital portion of the display if present is als
165. able for controlling where and how many of these messages are generated as summarized later in this section Table 12 below summarizes the simulation message types with a brief description of their meaning Currently the messages supported are specific to digital device timing violations and hazards 437 Chapter 14 Digital simulation Table 12 Simulation condition messages timing violations Message type Severity level Meaning SETUP WARNING Minimum time required for a data signal to be stable prior to the assertion of a clock was not met HOLD WARNING Minimum time required for a data signal to be stable after the assertion of a clock was not met RELEASE WARNING Minimum time required for a signal that has gone inactive usually a control such as CLEAR to remain inactive before the asserting clock edge was not met WIDTH WARNING Minimum pulse width specification for a signal was not satisfied that is a pulse that was too narrow was observed on the node FREQUENCY WARNING Minimum or maximum frequency specification for a signal was not satisfied Minimum frequency violations indicate that the period of the measured signal is too long while maximum frequency violations describe signals changing too rapidly GENERAL INFO Boolean expression described within the GENERAL constraint checker was evaluated and produced a true result 438 Analyzing results Table 13 Simulation condition messages hazards Mes
166. ace to search text box and type Click El then double click V Out V Out 7 Click in the db level down for bandwidth calc text box and type 3 8 Click the Next gt button The wizard displays the gain trace for the first run R 100 and shows how the bandwidth is measured This is done to test the goal function Chapter 2 Simulation examples Double click the x axis or press The Trace list includes goal functions only in performance analysis mode when the x axis variable is the swept parameter 90 10 Click the Next gt button or the Finish button A plot of the 3dB bandwidth vs Rval appears Change the x axis to log scale a From the Plot menu choose Axis Settings b Click the X Axis tab Under Scale choose Log d Click OK To plot gain vs Rval manually 1 2 From the Plot menu choose Add Y Axis From the Trace menu choose Add to display the Add Traces dialog box In the Functions or Macros frame select the Goal Functions list and then click the Max 1 goal function In the Simulation Output Variables list click V out In the Trace Expression text box edit the text to be Max Vdb out then click OK PSpice displays gain on the second y axis vs Rval Figure 26 shows the final performance analysis plot of 3dB bandwidth and gain in dB vs the swept input resistance s 368 1 6K 41 o Bandwidth u Out 3 Z m Max Udb Out Ruval Figure 26 Perfo
167. ackage xxxii If you have PSpice A D Basics 4 3 bee ee ES Ree ER S xxxii If you have the demo CD ROM 2 co e sd eee en ee a wees XXXV OrCAD demo CD ROM 0 0 0 0 00 000084 XXXV What sNew 2 0 0 0 000 skita ee ee tai aea xxxvi Simulation primer Things you need to know 41 Chapter overview oaaao od SS REE ES SERED Ey 41 Whatis PSpice A D esise geo doene OAc bee ek hoe a ee ee Anes 42 Analyses you can run with PSpice A D 00 004 43 Basic analyses o seo wh ee Races eae ae 8 aw Be 8 OS 43 DC sweep amp other DC calculations 43 AC sweep and noise 2 oon kee Oi Sew a Eee Se ee 44 Transient and Fourier 0 0 00 00 eee eee eee 45 Advanced multi run analyses 2 66 bes eee eee ewe ees 46 Parametric and temperature 6 42 624642 666 RAGE e REG 46 Monte Carlo and sensitivity worst case 47 Analyzing waveforms with PSpice A D 00 4 48 What is waveform analysis 266 d 26 eee dea ee dees 48 Using PSpice A D with other OrCAD programs 49 Using Capture to prepare for simulation 49 Contents What is the Stimulus Editor 0 0 0 0 0 000 0 000084 49 What is the Model Editor a 50 Files needed for simulation 0 0 0 0 00000 a 50 Files that Capture generates 44 60 45 ea ae he be a eae 50 Netlist ile es predea Boe ey e BERR SE RE 51 Circuithle amp 4 40 cane b BRAS EES EE eda OR ee BS 51
168. age 1 49 for a description Example An include file that contains definitions using the PSpice FUNC command for functions that you want to use in numeric expressions elsewhere in your design More on libraries Configuration for model libraries is similar to that for other libraries that Capture uses including part libraries To find out more refer to your Capture user s guide 53 Chapter 1 Things you need to know For a description of how to display simulation results see Part four Viewing results For a description of the waveform analyzer program see What is waveform analysis on page 1 48 There are two ways to add waveforms to the display e From within PSpice A D by specifying trace expressions e From within Capture by cross probing Example Each instance of a VPRINTL symbol placed in your schematic causes PSpice A D to generate a table of voltage values for the connecting net and to write the table to the PSpice output file 54 Files that PSpice A D generates After reading the circuit file netlist file model libraries and any other required inputs PSpice A D starts the simulation As simulation progresses PSpice A D saves results to two files the data file and the PSpice output file Waveform data file The data file contains simulation results that that can be displayed graphically PSpice A D reads this file automatically and displays waveforms reflecting circuit respo
169. ain HI LOW The value must be a nonnegative constant or expression A value of 0 means that any pulse width is allowed At least one of MIN_HI or MIN_LO must be used within a WIDTH section Freq FREQ checks the frequency MINFREQ MAXFREQ is the minimum maximum frequency that is allowed on the node in question The value must be a nonnegative floating point constant or expression measured in hertz At least one of MINFREO or MAXFREO must be used within a FREQ section AFFECTS clauses not used in this example can be included in constraints to describe how the simulator should associate the failure of a constraint check with the outputs paths through the device of the PINDLY This information does not affect the logic state of the outputs but provides causality detail used by the error tracking mechanism in PSpice A D waveform analysis 74160 example In the 74160 example we are checking that the maximum clock frequency CLK is not more than 25 MHz and the pulse width is 25 ns We are also checking that the CLRBAR signal has a minimum LO pulse width of 20 ns and that the 4 data inputs A B C D have a setup hold time of 20 ns in reference to the CLK signal We are also checking that ENP and ENT have a setup hold time of 20 ns with respect to the 0 to 1 transition of the CLK signal but only when the conditions in the WHEN statement are met All of the delay and constraint checking values were Creating a digital model using the
170. alog nodes the values are voltages For digital nodes these values are states The state of a digital node is calculated from the output strengths of the devices driving the node and the logic level of the node The purpose of strengths is to allow the simulator to find the value of a node when more than one output is driving it A common example is a bus line which is driven by more than one tristate driver Under normal circumstances all drivers except one are driving at the Z high impedance strength Thus the bus line will take on the value of the one gate that is driving at a higher strength lower impedance Another example is a bus line connected to several open collector output devices and a digital pullup resistor The pullup resistor outputs a 1 level at a weak but non Z strength If all of the open collector devices are outputting at Z strength then the node will have a 1 level because of the pullup resistor If any of the open collectors output a 0 at a higher strength than the pullup resistor then the 0 will overpower the weak 1 from the pullup and the node will be a 0 level Configuring the strength scale The 64 strengths are determined by two configurable options DIGDRVZ and DIGDRVF DIGDRVZ defines the impedance of the Z strength and DIGDRVF defines the impedance of the forcing strength These two values define a logarithmic scale consisting of 64 ranges of impedance values By default DIGDRVZ is 20 kohms and
171. alog only and mixed signal circuits 124 The OrCAD libraries include parts that are suitable for both simulation and board layout The unmodeled pins map into packages but have no electrical significance PSpice A D ignores unmodeled pins during simulation Check for this Are there connections to unmodeled pins If so do one of the following e Remove wires connected to unmodeled pins e If you expect the connection to affect simulation results find an equivalent part that models the pins in question and draw the connections Missing ground If for every net in your circuit you see this message in the PSpice output file ERROR Node node_name is floating then your circuit may not be tied to ground Check for this Are there ground parts named 0 zero connected appropriately in your design If not place and connect one or more as needed in your design You can use the 0 zero ground part in SOURCE OLB or any other ground part as long as you change its name to 0 Missing DC path to ground If for selected nets in your circuit you see this message in the PSpice output file ERROR Node node_name is floating then you may be missing a DC path to ground Check for this Are there any nets that are isolated from ground by either open circuits or capacitors If so then add a very large for example 1 Gohm resistor either e in parallel with the capacitor or open circuit or e from the isolated net t
172. alue for a delay parameter is known but the minimum is not the simulator uses the formula TPxxMN DIGMNTYSCALE X TPxxTY where the value of DIGMNTYSCALE is between 0 1 and 1 0 with the default value being 0 4 If the typical is known and the maximum is not then the simulator uses the formula TPxxMX DIGTYMXSCALE X TPxxTY where the value of DIGTYMXSCALE is greater than 1 0 with the default being 1 6 If the typical value is not known and both the minimum and maximum are then the typical value used by the simulator will be the average of the minimum and maximum propagation delays If only one of min or max is known then the typical delay is calculated using the appropriate formula as listed above If all three are unknown then they all default to a value of 0 Constraint checker CONSTRAINT primitive The CONSTRAINT primitive provides a general constraint checking mechanism to the digital device modeler It performs setup and hold time checks pulse width checks frequency checks and includes a general mechanism to allow user defined conditions to be reported See the Digital Devices chapter in the online OrCA D PSpice A D Reference Manual for more information Creating a digital model using the PINDLY and LOGICEXP primitives Setup_Hold The expressions in the SETUP_HOLD specification may be listed in any order CLOCK defines the node that is to be used as the reference for the setup hold release specification The ass
173. alysis such as M magnitude P phase G group delay out id specifies either the lt net id gt or lt pin id gt lt fully qualified device name gt lt pin name gt out device specifies the lt fully qualified device name gt These building blocks can be used for specifying output variables as shown in Table 6 which summarizes the accepted output variable formats and Tables 7 through 10 which list valid elements for two terminal three or four terminal devices transmission line devices and AC specifications Table6 PSpice A D output variable formats Format Meaning V ac lt out id gt V ac lt out id gt lt out id gt V ac lt 2 terminal device out id gt V ac lt 3 or 4 terminal device out id gt or V lt x gt ac lt 3 or 4 terminal out device gt V lt x gt lt y gt ac lt 3 or 4 terminal out device gt V ac lt transmission line out id gt or V lt z gt ac lt transmission line out device gt voltage at out id voltage across and out id s voltage at a 2 terminal device out id voltage at non grounded terminal x of a3 or 4 terminal device voltage across terminals x and y ofa 3 or 4 terminal device voltage at one end Z of a transmission line device Setting up analyses Table6 PSpice A D output variable formats continued Format Meaning I ac lt 3 or 4 terminal out device gt lt X gt or I lt x gt ac l
174. am by 5 From the Trace menu choose Goal Functions using the performance analysis wizard to h B ih display Bandwidth VDB OUT 1 P Choose Banavath 7 Click Eval 8 Enter VDB OUT in the Name of trace to search text box 9 Enter 1 in the db level down for bandwidth calc text box 10 Click OK then click Close to view the histogram To change the number of histogram divisions 1 From the Tools menu choose Options 2 Inthe Number of Histogram Divisions text box replace 10 with 20 3 Click OK The histogram for 1 dB bandwidth is shown in Figure 84 396 rata te m neran ne B 8 5K 1 8K i ea eee SK 2 8K 2 5K 1 Bandwidth UDBCOUT 1 n samples 100 sigma 404 553 median 1557 04 n divisions 28 minimum 44 042 98th ile 1937 74 mean 1440 71 1th Zile 766 895 maxinum 2049 8 Figure 84 1 dB bandwidth histogram The statistics for the histogram are shown along the bottom of the display The statistics show the number of Monte Carlo runs the number of divisions or vertical bars that make up the histogram mean sigma minimum maximum 10th percentile median and 90th percentile You can also show the distribution of the center frequency of the filter To display the center frequency From the Trace menu choose Goal Functions Choose CenterFreq Click Eval Enter VDB OUT in the Name of tra
175. ame click the Forward Current tab This tab requires curve data 2 Inthe Vfwd text box type 1 3 3 Press to move to the Ifwd text box and then type 0 2 To change the values for J unction Capacitance and Reverse Leakage 1 Follow the same steps as for Forward Current entering the data sheet information listed in Table 1 that corresponds to the current model characteristic To change the Reverse Breakdown characteristic 1 Inthe Spec Editing frame click the Reverse Breakdown tab This tab requires single valued data 2 Inthe Vz text box type 7 5 3 Press Tab to move to the Iz text box and then type 20m 4 Press Tab to move to the Zz text box and then type 5 Extracting model parameters To generate new model parameter values 1 From the Tools menu choose Extract Parameters A check mark appears in the Active column of the Parameters frame for each extracted model parameter To display the curves for the five diode characteristics 1 From the Window menu choose Tile Some of the plots are shown in Figure 32 below Using the Model Editor to edit models The Model Editor accepts the same scale factors normally accepted by PSpice A D You can also do the following with an active plot window e Pan and zoom within the plot using commands on the View menu e Rescale axes using the Axis Settings command on the Plot menu 149 Chapter 4 Creating and editing models 150 BF rect ib Dbreak x
176. ameters are varied You can select only one analysis type AC DC or transient per run The selected analysis is repeated in subsequent passes of the analysis Statistical analyses Output control for statistical analyses Monte Carlo and sensitivity worst case analyses generate the following types of reports e Model parameter values used for each run that is the values with tolerances applied e Waveforms from each run as a function of specifying data collection or by specifying output variables in the analysis set up e Summary of all the runs using a collating function Output is saved to the data file for use by the waveform For information about performance analyzer For Monte Carlo analyses you can use the analysis see RLC filter example on performance analysis feature to produce histograms of page 12 366 derived data For information about histograms see Creating histograms on page 13 395 Model parameter values reports To produce a list of the model parameters actually used for each run 1 Inthe Simulation Settings dialog box click the Analysis tab From the Analysis type list select an analysis type Under Options select Monte Carlo Worst Case Click the More Settings button ua A WwW N Select List model parameter values 6 Click OK to close the Simulation Settings dialog box This list is written to the simulation output file at the beginning of the run and contains the parameters for eac
177. analog nets The I O model parameters INR DRVZ and TSTOREMN see Table 3 on page 7 260 are used by the simulator to determine which nets should be simulated as charge storage nets The simulator will simulate charge storage only for a net which has some devices attached to it which can be high impedance Z and which has a storage time greater than or equal to the smallest TSTOREMN of all Input Output characteristics 265 Chapter 7 Digital device modeling 266 inputs attached to the net The storage time is calculated as the total capacitance sum of all INLD and OUTLD values for attached inputs and outputs multiplied by the total leakage resistance for the net the parallel combination of all INR and DRVZ values for attached inputs and outputs Note The default values provided by the UIO model will not allow the use of charge storage simulation techniques even with circuits using non OrCAD libraries of digital devices This is appropriate since these libraries are usually for PCB based designs Creating your own interface subcircuits for additional technologies If you are creating custom digital parts for a technology which is not in the model libraries you may also need to create AtoD and DtoA subcircuits The new subcircuits need to be referenced by the I O models for that technology The AtoD and DtoA interfaces have specific formats such as node order and parameters which are expected by PSpice A D for mixed si
178. analyses 380 Monte Carlo analysis ad 6 0a bse Ge 6 OE OS ERK OHS H 381 Reading the summary report ace aba ede ee Sew 383 Example Monte Carlo analysis of a pressure sensor 385 Drawing the schematic 2 4 4ie 4 6 ae Hah se ee Ge ee 385 Defining part values 222454 424 4 284 tea dee 4 ie es 386 Setting up the parameters 4 4 44 wd eo kee Oe eee 387 Using resistors with models 664 646 ype eee eR 388 xii Chapter 14 Contents Saving the design i ss ves ee ee BE e Re PHEW es 389 Defining tolerances for the resistor models 389 Setting up the analyses eS Cae ew eS Meee Seka S 391 Running the analysis and viewing the results 392 Monte Carlo Histograms 0444 244 42 24 4 baw weed Ea 393 Chebyshev filter example oaaae 393 Creating models for Monte Carlo analysis 394 Setting up the analysis aoaaa 394 Creating histograms aooaa ewe ee ER 395 Worst case analysis ooo a 398 Overview of worst case analysis o oo ee ee eee 398 Mpu 2 24 2 bia e Seeder ee eee eee dat ees s 399 Procedure so seade ee ee ee a EEES EEN Ea doe ad 399 OUPS lt 4 2s 2h Re ee ewes wees Deke ese Phe Se os 400 Caution An important condition for correct worst case analysis 24 400 Worst case analysis example 1 6 ee a ee a ee ee 401 Tips and other useful information 04 405 VARY BOTH VARY DEV and VARY LOT 405 Gaussian
179. analysis Also you cannot sweep the temperature in a DC sweep analysis or put tolerances on temperature coefficients while performing one of these statistical analyses In EXAMPLE DSN the temperature value is fixed at 35 C VOU aera readme RalaS RCI RC2 example rdm Z ik ok a CLOAD OUT d Jour RS2 ga a2 N 93 mmm y k q212222 q212222 k 4 1 oi at d R 4202222 ad Ha q212222 o E o VEE Figure 76 Example schematic EXAMPLE DSN Monte Carlo analysis The Monte Carlo analysis calculates the circuit response to changes in part values by randomly varying all of the model parameters for which a tolerance is specified This provides statistical data on the impact of a device parameter s variance With Monte Carlo analysis model parameters are given tolerances and multiple analyses DC AC or transient are run using these tolerances For EXAMPLE DSN in Figure 76 on page 13 380 you can analyze the effects of variances in the values of resistors RC1 and RC2 by assigning a model description to these resistors that includes a 5 device tolerance on the multiplier parameter R Then you can perform a Monte Carlo analysis First the simulator performs a DC analysis with the nominal R multiplier value for RC1 and RC2 Then it performs a set number of additional runs with the R multiplier varied independently for RC1 and RC2 w
180. and twice the input frequency but these are not included in a linear analysis Cautions and recommendations for simulation and analysis If you need to analyze nonlinear functions such as a mixer use transient analysis Transient analysis solves the full nonlinear circuit equations It also allows you to use input waveforms with different frequencies for example VIN1 could be 90 MHz and VIN2 could be 89 8 MHz AC analysis does not have this flexibility but in return it uses much less computer time Frequency domain parts Some caution is in order when moving between frequency and time domains This section discusses several points that are involved in the implementation of frequency domain parts These discussions all involve the transient analysis since both the DC and AC analyses are straightforward The first point is that there are limits on the maximum values and on the resolution of both time and frequency These are related the frequency resolution is the inverse of the maximum time and vice versa The maximum time is the length of the transient analysis TSTOP Therefore the frequency resolution is 1 TSTOP Laplace transforms For Laplace transforms PSpice A D starts off with initial bounds on the frequency resolution and the maximum frequency determined by the transient analysis parameters as follows The frequency resolution is initially set below the theoretical limit to 25 TSTOP and is then made as large as p
181. ans that the convolution must be applied to both past and future samples of the input in order to properly represent the inverse of the Laplace expression For example the expression S corresponds to differentiation in the time domain The impulse response for S is an impulse pair separated by an infinitesimal distance in time The impulses have opposite signs and are situated one in the infinitesimal past the other in the infinitesimal future In other words convolution with this corresponds to applying a finite divided difference in the time domain The problem with this for PSpice A D is that the simulator only has the present and past values of the simulated input so it can only apply half of the impulse pair during convolution This will obviously not result in time domain differentiation PSpice A D can detect but not fix this condition and issues a non causality warning message when it occurs The message tells what percentage of the impulse response is non causal and how much delay would need to be added to slide the non causal part into a causal region S is theoretically 50 non causal Non causality on the order of 1 or less is usually not critical to the simulation results You can delay S to keep it causal but the separation between the impulses is infinitesimal This means that a 235 Chapter 6 Analog behavioral modeling 236 very small time step is needed For this reason it is usually better to use a
182. as no DC current If this happens it usually shows up at the first time step It can be spotted turning on the detailed operating point information TRAN OP and looking at the calculated value of CJS for bipolar transistors The whole problem can be prevented by using the PSpice model parameter ISS This parameter turns on DC current for the substrate junction Diagnostics Diagnostics If PSpice encounters a convergence problem it inserts into the output file a message that looks like the following ERROR Convergence problem in transient analysis at Time 7 920E 03 Time step 47 69E 15 minimum allowable step size 300 0E 15 These voltages failed to converge V x2 23 1230 23 68 4137 V x2 25 1211 94 86 6888 These supply currents failed to converge 1 X2 L1 36 6259 2 25682 I X2 L2 36 5838 2 29898 These devices failed to converge X2 DCR3 X2 DCR4 x2 ktr X2 Q1 X2 02 Last node voltages tried were NODE VOLTAGE NODE VOLTAG NODE VOLTAGE NODE VOLTAGE E 1 25 2000 3 4 0000 4 0 0000 6 25 2030 X2 23 1230 200 X2 24 9 1441 x2 25 1211 900 X2 26 256 970 0 0 0 X2 28 206 610 X2 29 75 487 X2 30 25 0780 X2 31 26 2810 0 0 X3 34 1 771E 0 X3 35 1 0881 X3 36 4279 X2 XU1 6 1 2636 6 The message always includes the banner ERROR convergence problem and the trailer Last node voltages tried were Itcannot include all three of the middle bloc
183. aster than 1 microseconds In general the time resolution will be limited to RELTOL TSTOP 10 A final computational consideration for Laplace parts is that the impulse response is determined by means of an FFT on the Laplace expression The FFT is limited to 8192 points to keep it tractable and this places an additional limit on the maximum frequency which may not be greater than 8192 times the frequency resolution If your circuit contains many Laplace parts which can be combined into a more complex single device it is generally preferable to do this This saves computation and memory since there are fewer impulse responses It also reduces the number of opportunities for numerical artifacts that might reduce the accuracy of your transient analyses Cautions and recommendations for simulation and analysis Laplace transforms can contain poles in the left half plane Such poles will cause an impulse response that increases with time instead of decaying Since the transient analysis is always for a finite time span PSpice A D does not have a problem calculating the transient or DC response However such poles will make the actual device oscillate Non causality and Laplace transforms PSpice A D applies an inverse FFT to the Laplace expression to obtain an impulse response and then convolves the impulse response with the dependent source input to obtain the output Some common impulse responses are inherently non causal This me
184. at Meaning Noise variables V db ONOISE V db INOISE NTOT ONOISE N lt noise type gt lt device name gt total RMS summed noise at output net total equivalent noise at input source sum of all noise contributors in the circuit contribution from noise type of device name to the total output noise See Table 11 on page 17 526 for a complete list of noise types by device type For information about noise output variable equations the units used to represent noise quantities in trace expressions and a noise analysis example see Analyzing Noise in the Probe window on page 10 337 Table Examples of output variable formats A basic form An alias equivalent V NET3 NET2 same V C1 1 V1 C1 VP Q2 B VBP Q2 V T32 A VA T32 I M1 D ID M1 QA same IN1 IN2 IN3 same MYBUS X VIN same FREQUENCY same NFID M1 same Meaning voltage between analog nets labeled NET3 and NET2 voltage at pin1 of capacitor C1 phase of voltage at base of bipolar transistor Q2 voltage at port A of transmission line T32 current through drain of MOSFET device M1 digital state at net QA digital bus made of 3 digital nets IN1 IN2 IN3 named MYBUS displayed in hexadecimal voltage source named VIN AC analysis sweep variable flicker noise from MOSFET M1 523 Chapter 17 Analyzing waveforms Table8 Output variable AC suffixes Suffix Meaning of output variables non
185. at change the x axis domain Table 22 Enable this function By doing this Fast Fourier 1 From the Plot menu choose Axis transforms Settings 2 Inthe Processing Options frame select Fourier Performance 1 From the Plot menu choose Axis analysis Settings 2 Inthe Processing Options frame select Performance Analysis New x axis variable 1 From the Plot menu choose Axis Settings then click the X Axis tab 2 Click the Axis Variable button 3 Inthe X Axis Variable dialog box specify a new x axis variable Goal function 1 From the Trace menu select Eval Goal evaluation Function 2 In the Evaluate Goal Function s dialog box specify a goal function Load a completed 1 From the File menu choose data section Append Waveform DAT 2 Select a DAT file to append Pausing a simulation and viewing waveforms You can pause a simulation to analyze waveforms before the simulation is finished After you pause the simulation you can either resume the simulation or end it To pause a simulation 1 From PSpice s Simulation menu choose Pause 2 Inthe Probe window view the waveforms generated before you paused the simulation Viewing waveforms 3 Do one of the following e From the Simulation menu choose Run to resume the simulation e From the Simulation menu choose Stop to stop the simulation Using schematic page markers to add traces You can place markers on a schematic page to identify the See Trace exp
186. at the current through a To find out more about the diode equations diode is refer to the A nalog Devices chapter in T ISteveres the online OrCAD PSpice A D Reference Manual N defaults to one and k T at room temperature is about 025 volts So in this example the current through the diode would be I 1e 16 e 7 22e70 amps This circuit also does not have a solution within the limits of the dynamic range of PSpice In general be careful of components without limits built into them Extra care is needed when using the expressions for controlled sources such as for behavioral modeling It is easy to write expressions with very large values 549 Chapter B Convergence and time step too small errors Avoid unrealistic model parameters Behavioral modeling expressions need extra care 550 Are the Equations Continuous The device equations built into PSpice are continuous The functions available for behavioral modeling are also continuous there are several functions such as int x which cannot be added because of this So for physically realistic circuits the equations can also be continuous Exceptions that come are usually from exceeding the limits of the numerics in PSpice This example tries to approximate an ideal switch using the diode model MODEL DMOD IS le 16 N le 6 The current through this diode is 1e 16 ev 025 1e 16 ev 25e9 Because the denominator in the exponential is so small the cu
187. ate is clocked in e If set to 0 all such devices are cleared e If set to 1 all such devices are preset Starting the simulation To start the simulation From the PSpice menu choose Run After PSpice A D completes the simulation the graphical waveform analyzer starts automatically Starting the simulation Refer to the online OrCA D PSpice A D Reference Manual for more information about flip flops and latches Note The X initialization is the safest setting since many devices do not power up to a known state However the 0 and 1 settings are useful in situations where the initial state of the flip flop is unimportant to the function of the circuit such as a toggle flip flop in a frequency divider gt 429 Chapter 14 Digital simulation In effect the waveform viewer in PSpice A D is a software oscilloscope Running PSpice A D corresponds to building or changing a breadboard andthe waveform viewer corresponds to looking at the breadboard with an oscilloscope For a full discussion of how the waveform viewer is used to analyze results see Chapter 17 Analyzing waveforms For detailed information on how to add digital traces see Digital trace expressions on page 17 530 430 Analyzing results PSpice A D includes a graphical waveform analyzer for simulation results You can observe and interactively manipulate the waveform data produced by circuit simulation For mixed analog digital simul
188. ations the waveform analyzer can display analog and digital waveforms simultaneously with a common time base PSpice A D generates two forms of output the simulation output file and the waveform data file The calculations and results reported in the simulation output file are like an audit trail of the simulation However the graphical analysis of information stored in the data file is a more informative and flexible method for evaluating simulation results To display waveforms 1 From the Trace menu choose Add Trace Add Traces f Simulation Output Variables gt Functions or Macros ii Digital Operators and Constants z V Analog s c2 U Didi I 3 M Digital CLEAR CYCLE M Voltages amp DONE ERROR M Currents FAST i FTEST IV Alias Names 0 INIT E p0 INIT2 I Subcircuit Nodes 4 Mode ITF NO R N1 X N2 Z N3 OK REFH REFL RUN RUNL i SLOW 543 names listed SYSCLK x Full List Trace Expression Cancel Help 2 Select traces for display e Inthe Simulation Output Variables list click any waveforms you want to display Each appears in the Trace Expressions box at the bottom e Construct expressions by selecting operators functions and or macros from the Functions or Macros list and output variables in the Simulation Output Variables list e Youcanalso type trace expression directly into the Trace Expression text box A typical set of entries might be IN1 IN2 Q1 Q2 3 Click OK
189. ault temperature TNOM is set in the Options dialog box from the Simulation Settings dialog box choose the Options tab TNOM defaults to 27 C Note TEMP can only be used in expressions pertaining to analog behavioral modeling and the propagation delay of digital models Time values resulting from a transient analysis If no transient analysis is run this variable is undefined Note TIME can only be used in analog behavioral modeling expressions Using global parameters and expressions for values Note If a passive or semiconductor device has an independent temperature assignment then TEMP does not represent that device s temperature To find out more about customizing temperatures for passive or semiconductor devices refer to the MODEL command in the Commands chapter in the online OrCA D PSpice A D Reference Manual 113 Chapter 3 Preparing a design for simulation To find out how to use these parts and specify their properties see the following e Setting up a DC stimulus on page 9 310 e Using VSRC or ISRC parts on page 3 119 114 Defining power supplies For the analog portion of your circuit If the analog portion of your circuit requires DC power then you need to include a DC source in your design To specify a DC source use one of the following parts Table 12 For this source type Use this part voltage VDC or VSRC current IDC or ISRC For A D interfaces in mixed signal circui
190. ber of Monte Carlo runs More runs provide better statistics but they require more time The amount of time scales directly with the number of runs 20 transient analyses take 20 times as long as one transient analysis During Monte Carlo runs the PSpice A D status display includes the current run number and the total number of runs left Monte Carlo analysis Reading the summary report The summary report generated in this example see Figure 78 specifies that the waveform generated from V OUT1 OUT2 should be the subject of the collating function YMAX In each of the last four runs the new V OUT1 OUT2 waveform is compared to the nominal V OUT1 OUT2 waveform for the first run calculating the maximum deviation in the Y direction YMAX collating function The deviations are printed in order of size along with their run number HERE SORTED DEVIATIONS OF UCOUT1 0OUT2 TEMPERATURE 35 000 DEG C MONTE CARLO SUMMARY HHA JE E JE KH FE JE FE JE E KE KR KKK JE JE JE JE E PE JE DE JE JE JE JE JE JE JE JE JEJE JE PEJE JE JE JE JE DE FE JE JE JE JE JE ME IE JE JE KE KAA E JE E FE IE JE FE JE FE JE FEIE FE Hean Deviation 2477 Sigma 3035 RUN MAS DEVIATION FROM NOMINAL Pass 3 5729 1 89 sigma lower at UW 82 94 885 of Nominal Pass 4 3549 1 17 sigma lower at U_U 82 i 96 832 of Nominal Pass 2 3122 1 63 sigma lower at UW 82 i 97 212 of Nominal Pass 5 2493 82 sigma higher at U_U 02 i 102 23 o
191. ber of condition messages that may be generated by any digital device If this limit is exceeded PSpice A D aborts the run By default the total number of messages is 20 Severity levels PSpice A D assigns one of four severity levels to the messages e FATAL e SERIOUS e WARNING e INFO informational FATAL conditions cause PSpice A D to cancel the simulation Under all other severity levels PSpice A D continues to run The severity levels are used to filter the classes of messages that are displayed when loading a data file Analyzing results 441 Chapter 14 Digital simulation 442 Mixed analog digital simulation 15 Chapter overview This chapter describes how PSpice A D runs mixed analog digital simulations and includes the following sections e Interconnecting analog and digital parts on page 15 444 e Interface subcircuit selection by PSpice A D on page 15 445 e Specifying digital power supplies on page 15 449 e Interface generation and node names on page 15 454 Chapter 15 Mixed analog digital simulation To find out more see Interface generation and node names on page 15 454 444 Interconnecting analog and digital parts Prior to simulation netlisting translates the part instances and nets defined in your schematic into parts connected by nodes The netlist contains a flat view of the circuit no hierarchy PSpice A D extracts the definitions for all parts modeled as subcirc
192. build better products faster and at lower cost Before you begin xxviii OrCAD PSpice A D overview OrCAD PSpice A D simulates analog only mixed analog digital and digital only circuits PSpice A D s analog and digital algorithms are built into the same program so that mixed analog digital circuits can be simulated with tightly coupled feedback loops between the analog and digital sections without any performance degradation After you prepare a design for simulation OrCAD Capture generates a circuit file set The circuit file set containing the circuit netlist and analysis commands is read by PSpice A D for simulation PSpice A D formulates these into meaningful graphical plots which you can mark for display directly from your schematic page using markers How to use this guide How to use this guide This guide is designed so you can quickly find the information you need to use PSpice A D This guide assumes that you are familiar with Microsoft Windows NT or 95 including how to use icons menus and dialog boxes It also assumes you have a basic understanding about how Windows manages applications and files to perform routine tasks such as starting applications and opening and saving your work If you are new to Windows please review your Microsoft Windows User s Guide Typographical conventions Before using PSpice A D it is important to understand the terms and typographical conventions used in this doc
193. cale Click the trace name VP Out to select the trace From the Edit menu choose Cut From the Plot menu choose Add Y Axis From the Edit menu choose Paste The Bode plot appears as shown in Figure 21 154 GHz 166Hz 41 OKHZ 16KHZ 1 o VDB OUT 2 a UP OUT E ciooer SCHE 1G6KHZ 1 6NHZ 10HHz 100HHz Frequency Figure 21 Bode plot of clipper s frequency response Finding out more about AC sweep and noise analysis Table 2 2 To find out more about this AC sweep analysis noise analysis based on an AC sweep analysis See this AC sweep analysis on page 10 324 Noise analysis on_ page 10 333 AC sweep analysis 81 Chapter 2 Simulation examples i 82 Note Parametric Analysis is not supported in PSpice A D Basics Parametric analysis This example shows the effect of varying input resistance on the bandwidth and gain of the clipper circuit by e Changing the value of R1 to the expression Rval e Placing a PARAM part to declare the parameter Rval e Setting up and running a parametric analysis to step the value of R1 using Rval R1 lt WAY oO D1N3940 c1 Rval 3 Vin 1 Qs ite ae Iili m V3 SINE I 60 m 0 47u D2 D1 N3940 PARAMETERS Rval 1k l Figure 22 Clipper circuit with global parameter Rval This example produc
194. case result in a series of DC sweep AC sweep or transient analyses depending on which basic analyses you enabled Parametric and temperature For parametric and temperature analyses PSpice A D steps a circuit value in a sequence that you specify and runs a simulation for each value Table 4 shows the circuit values that you can step for each kind of analysis Table4 Parametric and temperature analysis types For this analysis You can step one of these Parametric global parameter model parameter component value DC source operational temperature Temperature operational temperature Analyses you can run with PSpice A D Monte Carlo and sensitivity worst case Monte Carlo and sensitivity worst case analyses are statistical PSpice A D changes device model parameter values with respect to device and lot tolerances that you specify and runs a simulation for each value Table 5 summarizes how PSpice A D runs each statistical analysis type Table5 Statistical analysis types For this statistical analysis PSpice A D does this Monte Carlo For each simulation randomly varies all Vea Note Monte Carlo Worst device model parameters for which you Case Analysis is not supported have defined a tolerance in PSpice A D Basics Sensitivity Computes the probable worst case worst case response of the circuit in two steps 1 Computes component sensitivity to changes in the device model pa
195. case runs are saved for viewing in the Probe window Caution An important condition for correct worst case analysis Worst case analysis is not an optimization process it does not search for the set of parameter values that result in the worst result It assumes that the worst case occurs when each parameter has been either pushed to one of its limits or left at its nominal value as indicated by the sensitivity analysis It shows the true worst case results when the collating function is monotonic within all tolerance combinations Otherwise there is no guarantee Usually you cannot be certain whether this condition is true but insight into the operation of the circuit may alert you to possible anomalies Worst case analysis Worst case analysis example The schematic shown in Figure 86 is for an amplifier circuit that is a biased BJT This circuit is used to demonstrate how a simple worst case analysis works It also shows how non monotonic dependence of the output on a single parameter can adversely affect the worst case analysis Because an AC small signal analysis is being performed setting the input to unity means that the output Vm OUT is the magnitude of the gain of the amplifier The only variable declared in this circuit is the resistance of Rb2 Because the value of Rb2 determines the bias on the BJT it also affects the amplifier s gain z CG Yee 10V e Ra Gout L ce
196. cc 0 10 Rc Vcc G 1k Ql C B 0 Q2N2222 Rb1 Vcc B 10k Rb2 B 0 Rbmod 720 model Rbmod res R 1 dev 5 WC analysis results are correct model Rbmod res R 1 1 dev 5 WC analysis misled by sensitivity xxxx x Load and blocking capacitor CoutC Out lu RI Out 0 1k Run with either the STEP or the WC but not both This circuit file is currently set up to run the STEP WC is commented out kkk Parametric Sweep providing plot of Vm LOUT vs Rb2 STEP Res Rbmod R 0 8 1 2 10m xxxx x Worst case analysis run once for each of the model definitions stated above WC AC Vm CLOut min range 99k 101k list output all AC Lin 3 90k 110k probe end Figure 87 Amplifier netlist and circuit file output is not monotonic with a variable parameter see Figure 89 and Figure 90 For demonstration the parametric analysis is run first generating the curve shown in Figure 89 and Figure 90 This curve derived using the YatX goal function shown in Figure 88 illustrates the non monotonic dependence of gain on Rb2 YatX 1 X_value yl 1 sfxv X_value 1 Figure 88 YatX Goal Function To do this yourself place the goal function definition in a PROBE GF file in the circuit directory Then start PSpice A D load all of the AC sweeps set up the X axis for performance analysis and add the following trace YatxX Vm CLOUT 100k Next the parametric analysis is commented out and the w
197. ce a generic voltage source using the VSRC part When you place the source for the meter change its name by double clicking the part and typing Meter in the Reference cell in the Parts Spreadsheet e For R1 R7 place a resistor using the R part e Place the analog ground using the 0 ground symbol 385 Chapter 13 Monte Carlo and sensitivity worst case analyses lt gt Shift w Note Because the Meter source is used to measure current it has no DC value and can be left unchanged Note The value for R3 1k 1 P Pcoeff Pnom is an expression that represents linear dependence of resistance on pressure To complete the definition for R3 you will create and define global parameters for Pcoeff P and Pnom later on in this example 386 e To connect the parts from the Place menu choose Wire e To move values or reference designators click the value or reference designator to select it then drag it to the new location Defining part values Define the part values as shown in Figure 80 For the pressure sensor you need to do the following e Change the resistor values for R3 R5 R6 and R7 from their default value of 1 k e Set the DC value for the V1 voltage source To change resistor values 1 Double click the value for a resistor 2 Type the new value Depending on the resistor you are changing set its value to one of the following refer to Figure 80 Table 1 If you are changing th
198. ce needs steps of less than 100 picoseconds to calculate the transition accurately Transient analysis 557 Chapter B Convergence and time step too small errors 558 Failure at the first time step If the transient analysis fails at the first time point then usually there is an unreasonably large capacitor or inductor Usually this is due to a typographical error Consider the following capacitor C 1 3 0 10uft 10 has the letter O should have been 10 This capacitor has a value of one farad not 10 microfarads An easy way to catch these is to use the LIST option on the OPTIONS command LIST The LIST option can echo back all the devices into the output file that have their values in scientific notation That makes it easy to spot any unusual values This kind of problem does not show up during the bias point calculation because capacitors and inductors do not participate in the bias point Similar comments apply to the parasitic capacitance parameters in transistor and diode models These are normally echoed to the output file the NOMOD option suppresses the echo but the default is to echo As in the LIST output the model parameters are echoed in scientific notation making it easy to spot unusual values A further diagnostic is to ask for the detailed operating bias point TRAN OP information TRAN OP This lists the small signal parameters for each semiconductor device including the calc
199. ce to search text box a Ww N e 5 Enter 1 in the db level down for measurement text box 6 Click OK then click Close to view the histogram The new histogram replaces the previous histogram To display both histograms at once choose Add Plot to Window on the Plot menu before choosing Add from the Trace menu The histogram of the center frequency is as shown in Figure 85 Monte Carlo analysis If needed you can turn off the statistical data display as follows 1 From the Tools menu choose Options 2 Clear the Display Statistics check box 3 Click Save and then OK Ten percent of the goal function values is less than or equal to the 10th percentile number and 90 of the goal function values is greater than or equal to that number If there is more than one goal function value that satisfies this criteria then the 10th percentile is the midpoint of the interval between the goal function values that satisfy the criteria Similarly the median and 90th percentile numbers represent goal function values such that 50 and 90 respectively of the goal function values are less than or equal to those numbers Sigma is the standard deviation of the goal function values 397 Chapter 13 Monte Carlo and sensitivity worst case analyses Note Worst case analysis is not supported in PSpice A D Basics 398 N a e a da te ari a e i rooi i c i i e i 1
200. cell and type its value Click the AC cell type its value and then click Apply f Close the property editor spreadsheet To change stimulus references globally for a part a Select the part you want to edit a From the Edit menu choose Part to start the part editor 355 Chapter 11 Transient analysis See Chapter 5 Creating parts for b Create or change the part definition making sure models fora description of how to create to define the following properties and edit parts Note Transient time response analysis is not supported in PSpice A D Basics 356 Implementation stimulus name as defined in the Stimulus Editor Transient time response The Transient response analysis causes the response of the a circuit to be calculated from TIME 0 to a specified time ve L A transient analysis specification is shown for the circuit EXAMPLE OPJ in Figure 65 EXAMPLE OPJ is shown in Figure 66 The analysis is to span the time interval from 0 to 1000 nanoseconds and values should be reported to the simulation output file every 20 nanoseconds Simulation Settings Transient Analysis x General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window Analysis type Time Domain Transient Bun to time fi 000ns seconds TSTOP Options Print values in the output file every fi Ons seconds General Settings Transient options Monte Carlo Worst Case Maximum step size
201. ch means PSpice A D VOLTAGE used the state with a voltage range closest to the input voltage and continued the simulation PERSISTENT SERIOUS Effects of any of the aforementioned logic hazards were able to HAZARD propagate to either an external port or to any storage device in the circuit See Persistent hazards on page 14 435 for more information 439 Chapter 14 Digital simulation 440 Output control options Four control options are available for managing the generation of simulation condition messages These are described in Table 14 To access these commands select the Options tab in the Simulation Settings dialog box You can set NOOUTMSG and NOPRBMSG by selecting the Output file Category You can set DIGERRDEFAULT and DIGERRLIMIT by selecting the Gate level simulation Category and clicking Advanced Options Table 14 Simulation message output control options This option Means this NOOUTMSG Suppresses the recording of simulation condition messages in the simulation output file NOPRBMSG Suppresses the recording of simulation condition messages in the waveform data file DIGERRDEFAULT lt n gt _ Establishes a default limit n to the number of condition messages that may be generated by any digital device that has a constraint checker primitive without a local default If global or local defaults are unspecified there is no limit DIGERRLIMIT lt n gt Establishes an upper limit n for the total num
202. changes Adding model libraries to the configuration New libraries are added above the selected library name in the Library Files list box To add model libraries to the configuration 1 From the Simulation menu choose Edit Simulation Settings then click the Libraries tab Click the library name positioned one entry below where you want to add the new library In the Filename text box either e type the name of the model library or e click Browse to locate and select the library Do one of the following e If the model definitions are for use in the current design only click the Add to Design button e If the model definitions are for global use in any schematic click the Add as Global button instead Click OK Configuring model libraries Note If the model libraries reside in a directory that is not on the library search path and you use the Browse button in step 3 to select the libraries you want to add then the schematic editor automatically updates the library search path Otherwise you need to add the directory path yourself See Changing the library search path on page 4 167 Changing design and global scope There are times when you might need to change the scope Example If you have an instance model of a model library from design to global or vice versa that you now want to make available to any design then you need to change the To change the scope of a design model to global local model lib
203. choose New Simulation Profile to display the New Simulation dialog box 3 Inthe Name text box type Bias 4 From the Inherit From list select None then click Create The Simulation Settings dialog box appears 5 From the Analysis type list select Bias Point 6 Click OK to close the Simulation Settings dialog box Running PSpice A D To simulate the circuit from within Capture 1 From the PSpice menu choose Run gt PSpice A D simulates the circuit and calculates the bias point information Note Because waveform data is not calculated during a bias point analysis you will not see any plots displayed in the Probe window for this simulation To find out how to view the results of this simulation see Using the simulation output file below 63 Chapter 2 Simulation examples 64 Using the simulation output file The simulation output file acts as an audit trail of the simulation This file optionally echoes the contents of the circuit file as well as the results of the bias point calculation If there are any syntax errors in the netlist declarations or simulation commands or anomalies while performing the calculation PSpice A D writes error or warning messages to the output file To view the simulation output file 1 From PSpice s View menu choose Output File Figure 5 shows the results of the bias point calculation as written in the simulation output file tant 10 05 98 12 06 18 t PSpice 9 0 Aug 1998
204. cify the correct number of pins nodes V Are the pins nodes in the PSPICETEMPLATE specified in the proper order f Do the pin node names in the PSPICETEMPLATE match the pin names on the part To edit a property needed for simulation 1 Inthe schematic page editor select the part to edit 2 From the Edit menu choose Properties to display the Parts spreadsheet of the Property Editor 3 Click in the cell of the column you want to change for example PSPICETEMPLATE or click the New button to add a property and type the property name in the Name text box 4 f needed type a value in the Value text box 5 Click Apply to update the design then close the spreadsheet 181 Chapter 5 Creating parts for models Caution Creating parts not intended for simulation Some part libraries contain parts designed only for board layout PSpice A D cannot simulate these parts This means they do not have PSPICETEMPLATE properties or that the PSPICETEMPLATE property value is blank 182 PSPICETEM PLATE The PSPICETEMPLATE property defines the PSpice A D syntax for the part s netlist entry When creating a netlist Capture substitutes actual values from the circuit into the appropriate places in the PSPICETEMPLATE syntax then saves the translated statement to the netlist file Any part that you want to simulate must have a defined PSPICETEMPLATE property These rules apply e The pin names specified in the PSP
205. city saturation e short channel effects such as channel length modulation source and drain charge sharing and the reverse short channel effect e thermal and flicker noise modeling e short distance geometry and bias dependent device matching for Monte Carlo analysis Enhanced model libraries The model libraries supplied with PSpice A D Release 9 have been enhanced to include the latest models from various vendors as well as models for popular optocouplers Darlingtons and DAC and ADC devices What s New To find out more see Creating and editing models on page 127 To find out more refer to MOSFET devices in the A nalog Devices chapter of the online OrCA D PSpice A D Reference Manual xxxvii Before you begin XXX Vili Part one Simulation primer Part one provides basic information about circuit simulation including examples of common analyses e Chapter 1 Things you need to know provides an overview of the circuit simulation process including what PSpice A D does descriptions of analysis types and descriptions of important files e Chapter 2 Simulation examples presents examples of common analyses to introduce the methods and tools you ll need to enter simulate and analyze your design Things you need to know Chapter overview This chapter introduces the purpose and function of the OrCAD PSpice A D circuit simulator What is PSpice A D on page 1 42 describes PSpice A D capabilities
206. d an imaginary component For transient analysis the output is the convolution of the input waveform with the impulse response of 1 1 001 s The impulse response is a decaying exponential with a time constant of 1 millisecond This means that the output is the lossy integral of the input where the loss has a time constant of 1 millisecond The LAPLACE part shown in Figure 40 could be used for this purpose The transfer function is the Laplace transform 1 1 001 s This LAPLACE part is characterized by the following properties NUM 1 DENOM 1 001 s The gain and phase characteristics are shown in Figure 41 o UMi Frequency Figure 41 Viewing gain and phase characteristics of a lossy integrator This produces a PSpice A D netlist declaration like this ERC 5 O LAPLACE V 10 1 1 001 s Example two The input is V 10 The output is a current applied between nets 5 and 0 The Laplace transform describes a Control system parts 1 1 001 3 Figure 40 LAPLACE part example one XP SORT C s RL 1 Figure 42 LAPLACE part example two 211 Chapter 6 Analog behavioral modeling 212 lossy transmission line R L and C are the resistance inductance and capacitance of the line per unit length If Ris small the characteristic impedance of such a line is Z R j a L j a C the delay per unit length is L C and the loss in dB per unit len
207. d to reset a counter which could appear as shown in Figure 93 below iv sis JA QA QA QB QB ac ae QC CLR QD 74393 U2 Figure 93 FILESTIM1 used on a schematic page In this case the FILESTIM1 part instance U2 generates a reset signal to the CLR pin of the 74393 counter To set up the U2 stimulus The following steps set up the U2 stimulus so that the 74393 counter is cleared after 40 nsec have elapsed in a transient analysis 1 Create a stimulus file named RESET STM that contains the following lines Reset A blank line is required between the signal name list and the first transition 425 Chapter 14 Digital simulation 426 Ons 1 40ns 0 The header line contains the names of all signals described in the file In this case there is only one Reset The remaining lines are the state transitions output for the signals named in the header In this case the Reset signal remains at state 1 until 40nsec have elapsed at which time it drops to state 0 Associate this file with the digital stimulus instance U2 by setting U2 s FILENAME property to RESET STM Define the signal named Reset in RESET STM as the output of U2 by setting U2 s SIGNAME property to Reset Since the labeled wire connecting U2 with the 74393 counter is also named Reset it is also acceptable to leave SIGNAME undefined From the PSpice menu choose Edit Simulation Settings Click the Include Files
208. del parameter is specified with both DEV and LOT tolerances defined the worst case analysis may produce unexpected results The sensitivity of the collating function is only tested with respect to LOT variations of such a parameter For example during the sensitivity analysis the parameter is varied once affecting all devices referring to it and its effect on the collating function is recorded For the worst case analysis the parameter is changed for all devices by LOT DEV in the determined direction See the example schematic in Figure 91 and circuit file in Figure 92 WCASE VARY BOTH Test Vin 1 0 10V Rs 1 2 1K Rwc1 2 3 Rmod 100 Rwc2 3 0 Rmod 100 MODEL Rmod RES R 1 LOT 10 DEV 5 DC Vin LIST 10 WC DC V 3 MAX VARY BOTH LIST OUTPUT ALL ENDS Figure 92 Circuit file using VARY BOTH In this case V 3 is maximized if e Rwcel and Rwc2 are both increased by 10 per the LOT tolerance specification and e Rwel is decreased by 5 and Rwe2 is increased by 5 per the DEV tolerance specification The final values for Rwc and Rwc2 should be 105 and 115 respectively However because Rwc1 and Rwc2 are varied together during the sensitivity analysis it is assumed that both must be increased to their maximum for a maximum V 3 Therefore both are increased by 15 Rwe1 Rmod 100 Vin zO Rwc2 Rmod 100 t Figure 91 Schematic using VARY BOTH The purpose of the technique is to r
209. delay when a typical delay is known using the formula TPxxMN DIGMNTYSCALE TPxxTY DIGMNTYSCALE defaults to the value 0 4 or 40 of the typical delay Its value must be between 0 0 and 1 0 DIGTYMXSCALE This option computes the maximum delay from a typical delay using the formula TPxxMX DIGTYMXSCALE TPxxTY DIGTYMXSCALE defaults to the value 1 6 Its value must be greater than 1 0 When a typical delay is unspecified its value is derived from the minimum and or maximum delays in one of the following ways If both the minimum and maximum delays are known the typical delay is the average of these two values If only the minimum delay is known the typical delay is derived using the value of the DIGMNTYSCALE option Likewise if only the maximum delay is specified the typical delay is derived using DIGTYMXSCALE Obviously if no values are specified all three delays will default to zero Treatment of unspedfied timing constraints The remaining timing constraint parameters are handled differently than the propagation delays Often data books state pulse widths setup times and hold times as a minimum value These parameters do not lend themselves to the extrapolation method used for propagation delays Instead when one or more timing constraints are omitted the simulator uses the following steps to fill in the missing values e Ifthe minimum value is omitted it defaults to zero Timing characteristics 2
210. dels the behavior of a circuit containing any mix of analog and digital devices Used with OrCAD Capture for design entry you can think of PSpice A D as a software based breadboard of your circuit that you can use to test and refine your design before ever touching a piece of hardware Run basic and advanced analyses PSpice A D can perform e DC AC and transient analyses so you can test the response of your circuit to different inputs e Parametric Monte Carlo and sensitivity worst case analyses so you can see how your circuit s behavior varies with changing component values e Digital worst case timing analysis to help you find timing problems that occur with only certain combinations of slow and fast signal transmissions Use parts from OrCAD s extensive set of libraries The model libraries feature over 11 300 analog and 1 600 digital models of devices manufactured in North America Japan and Europe Vary device characteristics without creating new parts PSpice A D has numerous built in models with parameters that you can tweak for a given device These include independent temperature effects Model behavior PSpice A D supports analog and digital behavioral modeling so you can describe functional blocks of circuitry using mathematical expressions and functions Analyses you can run with PSpice A D Basic analyses DC sweep amp other DC calculations These DC analyses evaluate circuit performance in
211. dialog box edit the trace expression just as you would when adding a trace To modify text and ellipse labels 1 Click the text or ellipse to select it selection is indicated by a color change 2 From the Edit menu choose Modify Object 3 Edit the label by doing one of the following e Inthe Ellipse Label dialog box change the inclination angle e Inthe Text Label dialog box change the text label User interface features for waveform analysis To place a label click Plot point to Label and then choose the desired type of object you want to place For information about adding labels including text line poly line arrow box circle ellipse and mark refer to the online Help in PSpice A D You can also double click the trace name to modify the trace expression For more information on adding traces see Adding traces from specific loaded waveform data files on page 17 494 and To add traces using output variables on page 17 519 You can also double click a text or ellipse label to modify it 509 Chapter 17 Analyzing waveforms or press Ctrl V When adding a trace to a Probe window you can make the trace display name different from the trace expression 1 From the Trace menu choose Add Trace 2 Inthe Trace Expression text box enter a trace expression using the syntax trace_ expression display_ name 3 Click OK 510 Moving and copying trace names and expressions Trace names a
212. distributions 000542 e ee 406 YMAX collating function 66 54 se eed wee eee ee 406 RECTO o wea sek Ae ate eee ae ie amp Ao pecs ate Ge Bee de amp 406 Sensitivity analysis cw sd Ge ee Be Ree Ee eS ee RS 406 Manual optimization 5 4 60h lt ahs hae oe ee BS 406 Monte Carlo analysis eis fae de Shen the eie es 407 Digital simulation 409 Chapter overview a lt a bee a oa belek Kee ew eed BE OS 409 What is digital simulation 254445440 054 644 amp eee Re do 410 Steps for simulating digital circuits 00 0 410 Concepts you need to understand 0040 411 Slates 44 2s a4 ee Bes ee ee ele he a Bee es ee 411 Strengths eop 2 eaan Sing ae Seay eee 2 WAL eo Ope E BAe eee 412 Defining a digital stimulus 22a CRE REAR ERE PLES ORES 413 Using the DIGSTIMn part aaua aa a 414 Defining input signals using the Stimulus Editor 414 Defining clock transitions 6 be aoa 414 Defining signal transitions ooo 415 Defining bus transitions aaao ee eed wes 417 Adding loops lt 6 a seos ES kt i aa a e a aa a E i 420 Using the DIGCLOCK part aoaaa a 422 Contents Chapter 15 Chapter 16 Xiv Using STIM1 STIM4 STIM8 and STIM16 parts 422 Using the PILES TIM parts sa 8 oe A pee eRe ee KEE 424 Defining simulation time 2 44 bo ova ee te Res Se eee ES 426 Adjusting simulation parameters 2 2 2 0 0 2 0 000000048 427 Selecting pro
213. ditor displays the subcircuit syntax exactly as it appears in the model library The Model Editor also includes all of the comments immediately before or after the subcircuit definition Changing the model name You can change the model name directly in the PSpice MODEL or SUBCKT syntax but double check that the new name does not conflict with models already contained in the libraries Note Ifyou do create a model with the same name as another model and want PSpice A D to always use your model make sure the configured model libraries are ordered so your definition precedes any other definitions Starting the Model Editor from the schematic page editor in Capture Start the model editor from the schematic page editor in Capture when you want to e define tolerances on model parameters for statistical analyses e test behavior variations on a part or e refine a model before making it available to all designs This means editing models for part instances in your design When you select a part instance and edit its model the schematic page editor automatically creates an instance model that you can then change Editing model text To find out more about instance model naming conventions see What is an instance model on page 4 154 To find out more about search order in the model library see Changing model library search order on page 4 166 You can also use the model editor to view the syntax for a mod
214. e analysis Digital worst case timing simulation is different from analog worst case analysis in several ways Analog worst case analysis s implemented as a sensitivity analysis for each parameter which has a tolerance followed by a projected worst case mulation with each parameter set to its minimum or maximum value This type of analysis is general since any type of variation caused by any type of parameter olerance can be studied But it is time consuming since a separate simulation is required for each parameter This does not always produce true worst case results since the algorithm assumes that the sensitivity is monotonic over the tolerance range n or The techniques used for digital worst case timing simulation are not compatible with analog worst case analysis It is therefore not possible to do combined analog digital worst case analysis and simulation and get the correct results PSpice A D allows digital worst case simulation of mixed signal and all digital circuits any analog sections are simulated with nominal values Systems containing embedded analog within digital sections do not give accurate worst case results they may be optimistic or pessimistic This is because analog simulation can not model a signal that will change voltage at an unknown point within some time interval 458 Digital worst case timing Manufacturers of electronic components generally specify component parameters such a
215. e quite different than what one would intuitively expect For this reason we strongly recommend familiarity with a reference on Fourier and Laplace transforms A good one is 1 R Bracewell The Fourier Transform and Its Applications McGraw Hill Revised Second Edition 1986 We also recommend familiarity with the use of transforms in analyzing linear systems Some references on this subject 2 W H Chen The Analysis of Linear Systems McGraw Hill 1962 3 J A Aseltine Transform Method in Linear System Analysis McGraw Hill 1958 4 GR Cooper and C D McGillen Methods of Signal and System Analysis Holt Rinehart and Winston 1967 Voltages currents and TIME cannot appear in a Laplace transform 227 Chapter 6 Analog behavioral modeling 228 The output of the device depends on the type of analysis being done For DC and bias point the output is simply the zero frequency gain times the value of EXPR The zero frequency gain is the value of XFORM with s 0 For AC analysis EXPR is linearized around the bias point similar to the VALUE parts The output is then the input times the gain of EXPR times the value of XFORM The value of XFORM at a frequency is calculated by substituting j w for s where w is 2p frequency For transient analysis the value of EXPR is evaluated at each time point The output is then the convolution of the past values of EXPR with the impulse response of XFORM These rules follow the
216. e appears along with corresponding waveforms PSpice A D also helps you locate the problem in your design 48 Using PSpice A D with other OrCAD programs Using Capture to prepare for simulation Capture is a design entry program you need to prepare your circuit for simulation This means e placing and connecting part symbols e defining component values and other attributes e defining input waveforms e enabling one or more analyses and e marking the points in the circuit where you want to see results Capture is also the control point for running other programs used in the simulation design flow What is the Stimulus Editor The Stimulus Editor is a graphical input waveform editor that lets you define the shape of time based signals used to test your circuit s response during simulation Using the Stimulus Editor you can define e analog stimuli with sine wave pulse piecewise linear exponential pulse single frequency FM shapes and e digital stimuli that range from simple clocks to complex pulse patterns and bus sequences The Stimulus Editor lets you draw analog piecewise linear and all digital stimuli by clicking at the points along the timeline that correspond to the input values that you want at transitions Using PSpice A D with other OrCAD programs Note The Stimulus Editor is N not induded in PSpice A D Basics 49 Chapter 1
217. e are used to determine the strength of the output Strengths are discussed on Defining Output Strengths on page 7 262 DRVZ INR and TSTOREMN These are used to determine which nets should be simulated as charge storage nets These are discussed in Charge storage nets on page 7 264 TPWRT This is used to specify the pulse width above which the noise immunity behavior of a device is to be considered See Inertial delay on page 7 255 on inertial delay for detail The following UIO model parameters are needed only when creating models for use in mixed signal simulations and therefore only apply to PSpice A D simulations AtoD1 through AtoD4 and DtoA1 through DtoA4 These are used to hold the names of interface subcircuits Note that AtoD1 through AtoD4 do not apply to stimulus generators because digital stimuli have no input nodes DIGPOWER This is used to specify the name of the digital power supply PSpice A D should call if one of the AtoD or DtoA interface subcircuits is called TSWLHn and TSWHLn These switching times are subtracted from a device s propagation delay on the outputs which connect to interface nodes This compensates for the time it takes the DtoA device to change its output voltage from its current level to that of the switching threshold By subtracting the switching time from the propagation delay the analog signal reaches the switching threshold at the correct time that is at the exact time of
218. e associated with RS SID shot noise TOT total noise D diode FID flicker noise RS thermal noise associated with RS SID shot noise TOT total noise Digital Input RHI thermal noise associated with RHI RLO thermal noise associated with RLO TOT total noise Digital Output TOT total noise J FET FID flicker noise RD thermal noise associated with RD RG thermal noise associated with RG RS thermal noise associated with RS SID shot noise TOT total noise M MOSFET FID flicker noise RB thermal noise associated with RB RD thermal noise associated with RD RG thermal noise associated with RG RS thermal noise associated with RS SID shot noise TOT total noise 526 Trace expressions Table 11 Noise types by device type continued Device type Noise types Meaning Q BJT FIB flicker noise RB thermal noise associated with RB RC thermal noise associated with RC RE thermal noise associated with RE SIB shot noise associated with base current SIC shot noise associated with collector current TOT total noise R resistor TOT total noise Iswitch TOT total noise Vswitch TOT total noise These variables report the contribution of the specified device s noise to the total output noise in units of V Hz This means that the sum of all device noise contributions is equal to the total output noise in V Hz NTOT ONOISE Analog trace expressions Trace expression aliases Analog trace expressions vary from the output variables
219. e libraries listed in the tables below e Make sure that you can simulate the part by checking the following e ThatithasaPSPICETEMPLATE property and that its value is non blank e That it has an Implementation Type PSpice MODEL property and that its Implementation property is non blank Table 18 Analog libraries with modeled parts installed in Capture Library PSpice 1_SHOT EPWRBJT MOTOR_RF ABM FILTSUB NAT_SEMI ADV_LIN FWBELL OPAMP AMP HARRIS OPTO ANALOG IGBT PHIL_BJT ANA_SWIT JBIPOLAR PHIL_FET ANLG_DEV JDIODE PHIL_RF ANL_MISC JFET POLYFET APEX JJFET PWRBJT BIPOLAR JOPAMP PWRMOS BREAKOUT JPWRBJT SIEMENS BUFFER JPWRMOS SWIT_RAV BURR_BRN LIN_TECH SWIT_REG CD4000 MAGNETIC TEX_INST COMLINR MAXIM THYRISTR DIODE MIX_MISC TLINE EBIPOLAR MOTORAMP XTAL EDIODE MOTORMOS ZETEX ELANTEC MOTORSEN Not included in Basics Contains mixed signal parts Digital libraries with modeled parts 7400 74H DIG_ECL 74AC 74HC DIG_GAL 74ACT 74HCT DIG_MISC 74ALS 74L DIG_PAL 74AS 74LS DIG_PRIM 74F 74S Things to watch for To find out more about a particular library refer to the online Library List or read the header of the model library file itself 121 Chapter 3 Preparing a design for simulation To find out more about setting the simulation properties for parts see Defining part properties needed for simulation on page 5 181 To find out more about using the part editor refer to your OrCA
220. e magnitude DB magnitude in decibels G group delay dPHASE dFREQUENCY I imaginary part M magnitude P phase in degrees R real part Table9 Device names for two terminal device types Two terminal device type Device type letter capacitor C diode D voltage controlled voltage source E current controlled current source F voltage controlled current source G current controlled voltage source H independent current source I inductor L resistor R voltage controlled switch S independent voltage source V current controlled switch W The pin name for two terminal devices is either 1 or 2 The controlling inputs for these devices are not considered terminals 524 Trace expressions Table 10 Terminal IDs by three amp four terminal device type Three amp four terminal device type Device type letter Terminal IDs GaAs MOSFET Junction FET MOSFET Bipolar transistor transmission line IGBT B D drain G gate S source J D drain G gate S source M D drain G gate S source B bulk substrate Q C collector B base E emitter S substrate T A near side B far side Z C collector G gate E emitter 525 Chapter 17 Analyzing waveforms Table 11 Noise types by device type Device type Noise types Meaning B GaAsFET FID flicker noise RD thermal noise associated with RD RG thermal noise associated with RG RS thermal nois
221. e or current to the output file 1 Place and connect any of the following parts from the PSpice library SPECIAL OLB Table 18 Use this part To plot this VPLOT1 Voltage on the net that the part terminal is connected to VPLOT2 Voltage differential between the two nets that the part terminals are connected to IPLOT Current through a net Insert this part in series like a current meter 2 Double click the part instance to display the Parts spreadsheet 3 Click the property name for the analysis type that you want plotted DC AC or TRAN 4 In the columns for the analysis type that you want plotted DC AC or TRAN type any non blank value such as y YES or 1 Writing additional results to the PSpice output file To view the PSpice output file after having run a simulation 1 From the Simulation menu choose Examine Output JEL IPLOT 535 Chapter 18 Other output options If you do not enable a format PSpice A D defaults to MAG 536 to IPRINT 5 Ifyou selected the AC analysis type enable an output format a Click the property name for one of the following output formats MAG magnitude PHASE REAL IMAG imaginary or DB b Type any non blank value such as Y YES or 1 C Repeat the previous steps a and b for as many AC output formats as you want to see plotted 6 Repeat steps 2 through 5 for any add
222. e parameter TPLHTY The minimum data to clock setup time on a flip flop is specified as the parameter TSUDCLKMN Several timing models are used by digital device 74393 from the model libraries One of them D_393_1 is shown below for an edge triggered flip flop model D_393_1 ueff tppcqhl ty 18ns tpclkqlhty 6ns tpclkqhIty ns twclkhmn 20ns twpclmn 20ns When creating your own digital device models you can create Timing models like these for the primitives you are using OrCAD recommends that you save these in your own custom model library which you can then configure for use with a given design tppcqh Imx 33ns tpclkql hmx 14ns tpclkqhImx 14ns twclklmn 20ns tsudclkmn 25ns One or more parameters may be missing from the Timing model definition Data books do not always provide all three minimum typical and maximum timing specifications The way the simulator handles missing parameters depends on the type of parameter Treatment of unspedfied propagation delays Often only the typical and maximum delays are specified in data books If in this case the simulator were to assume that the unspecified minimum delay defaults to zero the logic in certain circuits could break down For this reason the simulator provides two configurable options DIGMNTYSCALE and DIGTYMXSCALE which are used to extrapolate unspecified propagation delays in the Timing models DIGMNTYSCALE This option computes the minimum
223. e part graphic 3 After you have finished editing the part from the File menu choose Save to save the part to its library Grid spacing for pins The part editor always places pins on the grid even when the snap to grid option is turned off The size of the part is relative to the pin to pin spacing for that part That means that pins placed one grid space apart in the part editor are displayed as one grid space apart in the schematic page editor Editing part graphics Pins must be placed on the grid at integer multiples of the grid spacing Because the default grid spacing for the Schematic Page Grid is set at 0 10 OrCAD recommends setting pin spacing in the Part and Symbol Grid at 0 10 intervals from the origin of the part and at least 0 10 from any adjacent pins For more information about grid spacing and pin placement refer to the OrCA D The part edit id ins that t placed at part editor considers pins that are not placed a Capture User Gilde integer multiples of the grid spacing from the origin as off grid and a warning appears when you try to save the part Here are two guidelines e Make sure Pointer Snap to Grid is enabled when editing part pins and editing schematic pages so you can easily make connections e Make sure the Part and Symbol Grid spacing matches the Schematic Page Grid spacing 179 Chapter 5 Creating parts for models For more information on model editing in general see Chapter 4 C
224. e provides a special WATCH 1 part that lets you monitor voltage values for up to three nets in your schematic as a DC sweep AC sweep or transient analysis proceeds Results are displayed in PSpice A D To display voltage values in the PSpice window 1 Place and connect a WATCH 1 part from the PSpice library SPECIAL OLB on an analog net 2 Double click the WATCH 1 part instance to display the Parts spreadsheet 3 Inthe ANALYSIS property column type DC AC or TRAN transient for the type of analysis results you want to see 4 Enter values in the LO and HI properties columns to define the lower and upper bounds respectively on the values you expect to see on this net 5 Repeat steps 1 through 4 for up to two more WATCH1 instances 6 Start the simulation For example in the schematic fragment shown below WATCH 1 parts are connected to the Mid and Vcc nets After starting the simulation PSpice A D displays voltages on the Mid and Vcc nets yec D eH gt R2 Z ie D1 3 3k e D1N3940 ___ pi Mid pi Writing additional results to the PSpice output file Capture provides special parts that let you save additional simulation results to the PSpice output file as either line printer plots or tables Generating plots of voltage and current values You can generate voltage and current line printer plots for any DC sweep AC sweep or transient analysis To generate plots of voltag
225. e simulation profile filename SIM in the list box e Enter the simulation profile filename SIM in the File name text box and click Open 4 From the Simulation menu choose Edit Settings to modify any of the analysis setup parameters 5 From the Simulation menu choose Run or click the Run toolbar button to begin the simulation Setting up batch simulations Multiple simulations can be run in batch mode when starting PSpice A D directly with circuit file input You can use batch mode for example to run a number of simulations overnight There are two ways to do this as described below Multiple simulation setups within one circuit file Multiple circuit simulation descriptions can be concatenated into a single circuit file and simulated all at once with PSpice A D Each circuit simulation description in the file must begin with a title line and end with a END statement The simulator reads all the circuits in the circuit file and then processes each one in sequence The data file and simulation output file contain the outputs from each circuit in the same order as they appeared in the circuit Starting a simulation file The effect is the same as if you had run each circuit separately and then concatenated all of the outputs Running simulations with multiple drauit files You can direct PSpice A D to simulate multiple circuit files using either of the following methods Method 1 1 From the Start menu poin
226. e subcircuit selection by PSpice A D Analog to digital AtoD and digital to analog DtoA interface subcircuits handle the translation between analog voltages impedances and digital states or vice versa The main component of an interface subcircuit is either a PSpice A D N part digital input digital to analog or a PSpice A D O part digital output analog to digital PSpice A D N and O parts are neatly packaged into interface subcircuits in the model library The standard model library shipped with your OrCAD software installation includes interface subcircuits for each of the supported logic families TTL CD4000 series CMOS and high speed CMOS HC HCT ECL 10K and ECL 100K This frees you from ever having to define them yourself when using parts in the standard library Every digital primitive comprising the subcircuit description of a digital part has an I O model describing its loading and driving characteristics The name of the interface subcircuit actually inserted by PSpice A D is specified by the I O model of the digital primitive at the interface The I O model has parameters for up to four analog to digital AtoD and four digital to analog DtoA subcircuit names You can choose among four interface levels of subcircuit models depending on the simulation accuracy you need In some cases you may need more accurate simulations of the input output stages of a digital part while in other cases a simpler smaller mode
227. e them refer to the OrCA D Capture User s Guide 157 Chapter 4 Creating and editing models Refinements can include extending the subcircuit definition using the optional nodes construct OPTIONAL the variable parameters construct PARAMS and the FUNC and local PARAM commands 158 Before you can use the subcircuit definition in your design you need to Create a part for the subcircuit Configure the DESIGN_NAME SUB file so PSpice A D knows where to find it To create a subcircuit definition for a portion of your design To create a part for the subcircuit 1 In the schematic page editor move to the level of hierarchy for which you want to create a subcircuit SSUBCKT definition From the Place menu choose Hierarchical Port From the File menu choose Save In the Project Manager from the Tools menu choose Create Netlist Select the PSpice tab In the Options frame select Create SubCircuit Format Netlist Click OK to generate the subcircuit definition and save it to DESIGN_NAME SUB To configure the subcircuit file 1 In the schematic page editor from the PSpice menu choose Edit Simulation Settings to display the Simulation Settings dialog box Click either the Libraries tab or the Include Files tab then configure DESIGN_NAME SUB as either a model library or an include file see Configuring model libraries on page 4 162 If necessary refine the subcircuit definition for the new pa
228. easured are given The parameters are listed in worst output order for example the collating function was its worst when the first parameter printed in the list was varied When you use the YMAX collating function the output file also lists mean deviation and sigma values These are based on the changes in the output variable from nominal at every sweep point in every sensitivity run Manual optimization You can use worst case analysis to perform manual optimization with PSpice A D The monotonicity condition is usually met if the parameters have a very limited range Performing worst case analysis with tight tolerances on the parameters produces sensitivity and worst case results in the output file You can use these to decide how the parameters should be varied to achieve the desired response You can then make adjustments to the nominal values in the circuit file and perform the worst case analysis again for a new set of gradients Monte Carlo analysis Monte Carlo MC analysis may be helpful when worst case analysis cannot be used Monte Carlo analysis can often be used to verify or improve on worst case analysis results Monte Carlo analysis randomly selects possible parameter values which can be thought of as randomly selecting points in the parameter space The worst case analysis assumes that the worst results occur somewhere on the surface of this space where parameters to which the output is sensitive are at one of
229. eate parts If you want to run the Model Editor and enable automatic creation of parts for any model that you create or change then run the Model Editor alone This means any models you create are not tied to the current design or to a part editing session Note If you open an existing model library the Model Editor creates parts for only the models that you change or add to it Starting the Model Editor To start the Model Editor alone 1 From the Windows Start menu point to the OrCAD Release 9 program folder then choose PSpice Model Editor 2 From the File menu choose Open or New and enter an existing or new model library name 3 Inthe Models List frame select the name of a model to display it for editing in the Spec Entry frame To start the Model Editor from within Capture 1 Inthe schematic page editor select the part whose model you want to edit 2 From the Edit menu choose PSpice Model The Model Editor starts with the model loaded for editing Using the Model Editor to create parts AWA Note The Model Editor is not bey included in PSpice A D Basics To find out how to use the Model Editor to create models see Using the Model Editor to edit models on page 4 135 To find out which device types the Model Editor supports see Model Editor supported device types on page 4 137 If you have already started the Model Editor from Capture and want to continue working on new models and parts then 1
230. ect PSpice Model 3 Inthe Implementation column type the name of the model to attach to the part 4 Click Apply to update the design then close the Parts spreadsheet Defining part properties needed for simulation If you created your parts using any of the methods discussed in this chapter then your part will have these properties already defined for it e PSpice PSPICETEMPLATE for simulation e PART and REFDES for identification You can also add other simulation specific properties for digital parts IOLLEVEL MNTYMXDLY and PSPICEDEFAULTNET for pins For example if you create a part that has electrical behavior described by the subcircuit definition that starts with SUBCKT 7400 A B Y optional DPWR G_DPWR DGND G_DGND params MNTYMXDLY 0 IO_LEVEL 0 then the appropriate part properties are IMPLEMENTATION 7400 MNTYMXDLY 0 IO_LEVEL 0 PSPICETEMPLATE X REFDES ZA B ZY PWR GND MODEL PARAMS IO_LEVEL IO_LEVEL MNTYMXDLY MNTYMXDLY Note For clarity the PSPICETEMPLATE property value is shown here in multiple lines in a part definition it is specified in one line no line breaks Table 3 To find out more about this property See this PSPICETEMPLATE page 5 182 IO_LEVEL page 5 189 MNTYMXDLY page 5 190 PSPICEDEFAULTNET page 5 191 Defining part properties needed for simulation Here are the things to check when editing part properties f Does the PSPICETEMPLATE spe
231. ed stimulus FILESTIM16 sixteen bit file based stimulus FILESTIM32 thirty two bit file based stimulus 413 Chapter 14 Digital simulation Note The DIGSTIMn part is A not included in PSpice A D va Basics VE Note The Stimulus Editor is not included in PSpice A D A Basics If you have the Basics package you can define clock signals using DIGCLOCK To find out more see Using the DIGCLOCK part on page 14 422 414 Using the DIGSTIMn part Use the DIGSTIMn stimulus parts to define a stimulus for a net or bus using the Stimulus Editor To use the DIGSTIM part 1 2 From Capture s Place menu choose Part Place and connect the DIGSTIMn stimulus part from SOURCSTM OLB to a wire or bus in your design Click the stimulus instance to select it From the Edit menu choose PSpice Stimulus This starts the Stimulus Editor A dialog box appears asking you whether you want to edit the named stimulus Click OK Define stimulus transitions see Defining input signals using the Stimulus Editor below Defining input signals using the Stimulus Editor Defining dock transitions To create a clock stimulus 1 In the Stimulus Editor select the stimulus that you want to use as a clock From the Stimulus menu choose Change Type Under Type choose Clock Click OK Defining a digital stimulus 5 Enter values for the clock signal properties as Example To create a clock signal with described b
232. ed by the qualified device name for a list of device s reference designator For device types see Table 9 on information about syntax see the voltage page 17 524 and Table 10 on output variable naming rules on page 17 525 page 8 292 520 Trace expressions Output variable form for device terminals This form can only be specified for trace expressions The primary difference between this and the basic form is that the terminal symbol appears before the net or device name specification whereas the basic form treats this as the pin name within the pin id lt output gt terminal A C suffix lt name gt name Table 5 This placeholder Means this lt output gt type of output quantity V for voltage I for current or N for noise digital values do not require a prefix terminal one or more terminals for devices with more than two terminals for a list of terminal IDs see Table 10 on age 17 525 AC suffix quantity to be reported for an AC analysis for a list of valid AC suffixes see Table 8 on page 17 524 lt name gt lt name gt net net pair or fully qualified device name for a list of device types see Table 9 on page 17 524 and Table 10 on page 17 525 Table 6 on page 17 521 summarizes the valid output formats Table 7 on page 17 523 provides examples of equivalent output variables Note that some of the output variable formats are unique to trace expressions Table6
233. ed for your design and you can set up multiple analyses of the same type Simulation profiles help you keep your analysis results separate so you can delete one without losing the rest New OrCAD Capture front end Release 9 integrates OrCAD Capture as the front end schematic entry tool for PSpice A D Capture provides a professional design entry environment with many advanced capabilities that now work hand in hand with PSpice A D These include a project manager a new property editor spreadsheet right mouse button support and many other time saving features New Model Editor interface The Model Editor formerly known as Parts has been improved and modernized for Release 9 It now provides a unified application for editing models either in text form or by modifying their specifications The Model Editor now also supports Darlington modeling EKV version 2 6 MOSFET model The EKV model isa scalable and compact model built on fundamental physical properties of the device Use this model to design low voltage low current analog and mixed analog digital circuits that use sub micron technologies Version 2 6 models the following e geometrical and process related aspects of the device oxide thickness junction depth effective channel length and width and so on e effects of doping profile and substrate effects e weak moderate and strong inversion behavior e mobility effects due to vertical and lateral fields and carrier velo
234. educe the number of simulations For a more accurate worst case analysis you should first perform a worst case analysis with VARY LOT manually adjust the nominal model parameter values according to the results then perform another analysis with VARY DEV specified 405 Chapter 13 Monte Carlo and sensitivity worst case analyses This may result in maximizing or minimizing the output variable value over the entire range of the sweep This collating function is useful when you know the direction in which the maximum deviation occurs 406 Gaussian distributions Parameters using Gaussian distributions are changed by 30 three times sigma for the worst case analysis YMAX collating function The purpose of the YMAX collating function is often misunderstood This function does not try to maximize the deviation of the output variable value from nominal Depending on whether HI or LO is specified it tries to maximize or minimize the output variable value itself at the point where maximum deviation occurred during sensitivity analysis RELTOL During the sensitivity analysis each parameter is varied multiplied by 1 RELTOL where RELTOL is specified in a OPTIONS statement or defaults to 0 001 Sensitivity analysis The sensitivity analysis results are printed in the output file OUT For each varied parameter the percent change in the collating function and the sweep variable value at which the collating function was m
235. el definition When you are finished viewing be sure to quit the Model Editor without saving the library so the schematic page editor does not create an instance model 153 Chapter 4 Creating and editing models For more information on instance models see Reusing instance models on page 4 160 After you start the Model Editor you can proceed to change the text as described in To display the model text on page 4 152 To find out how Capture searches the library see Changing model library search order on page 4 166 154 What is an instance model An instance model is a copy of the part s original model The copied model is limited to use in the current design You can customize the instance model without impacting any other design that uses the original part from the library When the schematic page editor creates the copy it assigns a unique name that is by default original_model_name Xn where nis lt blank 1 2 gt depending on the number of different instance models derived from the original model for the current design Starting the Model Editor To start editing an instance model 1 Inthe schematic page editor select the part on the schematic page 2 From the Edit menu choose PSpice Model The schematic page editor searches the configured libraries for the instance model e If found the schematic page editor starts the Model Editor which opens the library containing the instance
236. elay is easily calculated during the simulation by adding the pre calculated loading delay to the device s timing delay However for any individual timing delay specification e g TPLH having a value of 0 the loading delay is not used When outputs connect to analog devices the propagation delay is reduced by the switching times specified in the I O model Timing characteristics Inertial and transport delay The simulator uses two different types of internal delay functions when simulating the digital portion of the circuit inertial delay and transport delay The application of these concepts is embodied within the implementation of the digital primitives within the simulator Therefore they are not user selectable Inertial delay The simulation of a device may be described as the application of some stimulus S to a function F and 5 F gt R predicting the response R If this device is electrical in nature application of the stimulus implies that energy will be imparted to the device to cause it to change state The amount of such energy is a function of the signal s amplitude and duration If the stimulus is applied to the device for a length of time that is too short the device will not switch The minimum duration required for an input change to have an effect on a device s output state is called the inertial delay of the device For digital simulation all delay parameters specified in tim
237. elds on production runs of a circuit For more information about performance analysis see RLC filter example on page 12 366 393 Chapter 13 Monte Carlo and sensitivity worst case analyses 394 bandwidth and the center frequency vary when 1 resistors and 5 capacitors are used in the circuit uz L11013 411 Wh Figure 83 Chebyshev filter Creating models for Monte Carlo analysis To vary the resistors and capacitors in the filter circuit create models for these parts on which you can set device tolerances for Monte Carlo analysis The BREAKOUT OLB library contains generic devices for this purpose The resistors and capacitors in this schematic are the Rbreak and Cbreak parts from BREAKOUT OLB Using the Model Editor modify the models for these parts as follows model RMOD RES R 1 DEV 12 model CMOD CAP C 1 DEV 52 Setting up the analysis To analyze the filter set up both an AC analysis and a Monte Carlo analysis The AC analysis sweeps 50 points per decade from 100 Hz to 1 MHz The Monte Carlo analysis is set to take 100 runs The analysis type is AC and the output variable is V OUT Monte Carlo analysis To set up the analysis 1 From PSpice A D s Trace menu choose Performance Analysis In the Save data from list box choose All Click OK Creating histograms Because the data file can become quite large when running a Monte
238. elow a clock rate of 20 MHz 50 duty cycle a starting value of 1 and time delay of Table 3 h 5 nsec set the signal properties as follows For this property Enter this Frequency 20Meg Frequency clock rate Duty Cycle 0 50 or 50 Duty Cycle oe a ma versus low in decimal Initial Value i Initial Value starting value 0 or 1 Time Delay Sns Time Delay time after simulation begins when the clock stimulus takes effect 6 From the File menu choose Save To change clock properties 1 In the Stimulus Editor do one of the following e Double click the clock name to the left of the axis e Click the clock name and from the Edit menu choose properties Modify the clock properties as needed Click OK Defining signal transitions You can do any of the following when defining digital signal transitions Add a transition Move a transition Edit a transition Delete a transition Note These operations cannot be applied to a stimulus defined as a dock signal 415 Chapter 14 Digital simulation When you select a transition to edit a red handle appears 416 To add a transition 1 2 3 5 From the Stimulus Editor s Edit menu choose Add Select the digital stimulus you want to edit Drag the new transition to its proper location on the waveform If you want to add more transitions repeat steps 2 and 3 When you finish right click to exit the edit mode To move a transition
239. enal DC teansief a i 0 Gods bee ee Ph SKS EREE EEE 317 Minimum requirements to run a small signal DC transfer analysis 317 Overview of small signal DC transfer 4 318 DC Sensitivity s sarerea eho bine ooh ae eee Eh oh ee So ee 320 Minimum requirements to run a DC sensitivity analysis 320 Overview of DC sensitivity 4 2 ee ae he Qe ee ES 321 Chapter 10 AC analyses 323 Chapter overview oaao Eb RS SHS ER hed BHD AC sweep analysis o oo oos ss Ee AE RES OR OR A Setting up and running an AC sweep a aoao Whats AC SWeCp o e o emot tacsi ee ed ee eee ee Setting up an AC stimulus 008 0 Setting up an AC analysis 2 cs ee we eta Pee ead eee s AC sweep setup in example opj ace ee eke Ge Di dees How PSpice A D treats nonlinear devices What s required to transform a device into a linear circuit What PSpice A D does coe oe tA eGo Rae ee eo Example nonlinear behavioral modeling block Noise ANALYSIS oc ev gles ew eM 4 Bas GO ee a eee Setting up and running a noise analysis What is noise analysis 245 0524 346 5Ge HA bw ees ees How PSpice A D calculates total output and input noise t 0ca se oe he Bete ee 6 Be Eas Setting up a noise analysis 4 240 40k we Gok ewe EES Analyzing Noise in the Probe window About noise units 2 0 Example sad toes goo wae eee Ee Ea eR Re Chapter 11 Transient analysis 341 Chapter over
240. ent time response on page 11 356 Internal time steps in transient analyses on page 11 358 Switching circuits in transient analyses on page 11 359 Plotting hysteresis curves on page 11 359 Fourier components on page 11 361 Chapter 11 Transient analysis See Setting up analyses on page 8 289 for a description of the Analysis Setup dialog box 342 Overview of transient analysis Minimum requirements to run a transient analysis Minimum cdrait design requirements Circuit should contain one of the following An independent source with a transient specification see Table 10 An initial condition on a reactive element A controlled source that is a function of time Minimum program setup requirements 1 From the PSpice menu choose New Simulation Profile or Edit Simulation Settings If this is a new simulation enter the name of the profile and click OK The Simulation Settings dialog box appears From the Analysis type list box select Time Domain Transient Specify the required parameters for the transient analysis you want to run Click OK to save the simulation profile From the PSpice menu choose Run to start the simulation Overview of transient analysis Simulation Settings Transient Analysis General Setting Load Bias Point 343 Chapter 11 Transient analysis Defining a time based stimulus Overview of stimulus generation Symbols that generate input signals for you
241. ents with magnitude and phase you can use this information to obtain Bode plots Noise For each frequency specified in the AC analysis e Propagated noise contributions at an output net from every noise generator in the circuit e RMS sum of the noise contributions at the output e Equivalent input noise Note To run a noise analysis you must also run an AC sweep analysis Analyses you can run with PSpice A D Transient and Fourier These time based analyses evaluate circuit performance in response to time varying sources Table 3 summarizes what PSpice A D calculates for each time based analysis type Table3 Time based analysis types For this time based analysis PSpice A D computes this Transient Fourier Voltages currents and digital states tracked over time For digital devices you can set the propagation delays to minimum typical and maximum If you have enabled digital worst case timing analysis then PSpice A D considers all possible combinations of propagation delays within the minimum and maximum range DC and Fourier components of the transient analysis results Note To run a Fourier analysis you must also run a transient analysis 45 Chapter 1 Things you need to know Note Parametric analysis is not supported in PSpice A D Basics 46 la Advanced multi run analyses The multi run analyses parametric temperature Monte Carlo and sensitivity worst
242. ep 1 Open an existing schematic or start a new one 2 Place a VSTIM part on your schematic 3 Toname the stimulus double click the implementation property and type Vsin 4 Click the VSTIM part to select it 5 From the PSpice menu choose Edit Stimulus to start the Stimulus Editor 6 Define the stimulus parameter for amplitude a From the New Stimulus dialog box choose Cancel b From the Tools menu choose Parameters c Enter amp 1 in the Definition text box and click OK 10 11 d From the Stimulus menu choose New or click the New Stimulus button in the toolbar e Give the stimulus the name of Vsin f Select SIN as the type of stimulus to be created and click OK Define the other stimulus properties a Enter 0 for Offset Value b Enter Amp for Amplitude The curly braces are required They indicate that the expression needs to be evaluated at simulation time Enter 10k for Frequency and click OK d From the File menu choose Save Within Capture place and define the PARAM symbol a From the Place menu choose Part 0 Either browse SPECIAL OLB for the PARAM part or type in the name c Place the part on your schematic and double click it d Click New to add a new user property e Set the value property name to AMP no curly braces f Set the value of the VALUE1 property to 1 Set up the parametric sweep and other analyses a From the PSpice menu choose Stimulus Editor and click the Parametr
243. er 13 Monte Carlo and sensitivity worst case analyses describes how to set up Monte Carlo and sensitivity worst case analyses for statistical interpretation of your circuit s behavior Chapter 14 Digital simulation describes how to set up a digital simulation analysis on either a digital only or mixed signal circuit Chapter 15 Mixed analog digital simulation explains how PSpice A D processes the analog and digital interfaces in mixed signal circuits Chapter 16 Digital worst case timing analysis describes how PSpice A D performs digital worst case timing analysis and the kinds of hazards that this analysis can help you detect Setting up analyses and starting simulation Chapter overview This chapter provides an overview of setting up analyses and starting simulation that applies to any analysis type The other chapters in Part three Setting Up and Running Analyses provide specific analysis setup information for each analysis type This chapter includes the following sections e Analysis types on page 8 288 e Setting up analyses on page 8 289 e Starting a simulation on page 8 299 Chapter 8 Setting up analyses and starting simulation Note Parametric Analysis is Vea not supported in PSpice A D VE 4 Basics 288 Analysis types PSpice A D supports analyses that can simulate analog only mixed signal and digital only circuits PSpice A D fully supports digital analysis by simulating the timing
244. er 3 Preparing a design for simulation Table9 Operators in expressions This operator Includes this dass operator Which means arithmetic addition or string concatenation 7 subtraction 7 multiplication division s exponentiation logical unary NOT boolean OR A boolean XOR amp boolean AND relational equality test l non equality test gt greater than test gt greater than or equal to test lt less than test lt less than or equal to test Logical and relational operators are used within the IF function for digital parts logical operators are used in Boolean expressions 110 Table 10 Functions in arithmetic expressions This function Means this ABS x Ixl SQRT x x1 2 EXP x ex LOG x In x which is log base e LOG10 x log x which is log base 10 PWR x y Ixly PWRS x y 1xI if x gt 0 Ixl Gfx lt 0 SIN x sin x where x is in radians ASIN x sin x where the result is in radians SINH x sinh x where x is in radians COS x cos x where x is in radians ACOS x cos x where the result is in radians COSH x cosh x where x is in radians TAN x tan x where x is in radians ATAN x tan x where the result is in ARCTAN x radians ATAN2 y x tan y x where the result is in radians TANH x tanh x where x is in radians M x magnitude of x which is the same as ABS x P x phase of x in degrees returns 0 0 for real numbers R x
245. er object 1 Click the text to select it then drag the text to a new location To place the other parts 1 From the Place menu choose Part to display the Place Part dialog box 2 Add the library for the parts you need to place a Click the Add Library button 0 Select ANALOG OLB from the PSpice library and click Open 3 Follow similar steps as described for the diodes to place the parts listed below according to Figure 2 The part names you need to type in the Part name text box of the Place Part dialog box are shown in parentheses e resistors R e capacitor C To place the off page connector parts OFFPAGELEFT R click the Place Off Page Connector button on the tool palette Add the library for the parts you need to place a Click the Add Library button b Select CAPSYM OLB from the Capture library and click Open Place the off page connector parts according to Figure 2 To place the ground parts 0 click the GND button on the tool palette Add the library for the parts you need to place a Click the Add Library button b Select SOURCE OLB from the PSpice library and click Open Place the ground parts according to Figure 2 To connect the parts 1 From the Place menu choose Wire to begin wiring parts The pointer changes to a crosshair Click the connection point the very end of the pin on the off page connector at the input of the circuit Click the nearest connection point of the i
246. er the circuit in Capture as shown in Figure 73 To create the capacitor model in the schematic editor 1 Place a CBREAK part 2 Select it so that it is highlighted 3 From the Edit menu choose PSpice Model 4 In the Model Text frame enter the following model Cnin CAP C 1 VC1 0 01 VC2 0 05 5 From the File menu choose Save Set up the circuit for a parametric AC analysis sweep Vbias and run PSpice A D Include only the frequency of interest in the AC sweep Parametric analysis To display the results Use PSpice to display the capacitance calculated at the frequency of interest versus the stepped parameter 1 2 3 Simulate the circuit Load all AC analysis sections From the Trace menu choose Add Trace or click the Add Trace toolbar button Add the following trace expression IMG I Vin V 1 0 2 3 1416 Frequency Or add the expression CvF I Vin V 1 0 Where CvF is a macro which measures the effective capacitance in a complex conductance Macros are defined using the Macros command on the Trace menu The CvF macro should be defined as Note CvF G IMG G 2 3 1416 Frequency I Vin V 1 is the complex admittance of the R C branch the minus sign is required for correct polarity To use performance analysis to plot capacitance vs bias voltage 1 2 3 4 From the Trace menu choose Performance Analysis Click Wizard Click Next gt Click YatX in the Choose a Goal Function list and t
247. eral Settings Monte Carlo Worst Case Enter a list of temperatures separated by spaces For example 0 27 125 Parametric Sweep Temperature Sweep Save Bias Point Load Bias Point WKS Click OK to save the simulation profile From the PSpice menu choose Run to start the simulation Temperature analysis See Setting up analyses on page 8 289 for a description of the Simulation Settings dialog box 373 Chapter 12 Parametric and temperature analysis Running multiple analyses for different temperatures can also be achieved using parametric analysis see Parametric analysis on page 12 364 With parametric analysis the temperatures can be specified either by list or by range and increments within the range The example circuit EXAMPLE OP is provided with the OrCAD program installation 374 Overview of temperature analysis For a temperature analysis PSpice A D reruns standard analyses set in the Simulation Settings dialog box at different temperatures You can specify zero or more temperatures If no temperature is specified the circuit is run at 27 C If more than one temperature is listed the simulation runs once for each temperature in the list Setting the temperature to a value other than the default results in recalculating the values of temperature dependent devices In EXAMPLE OP see Figure 75 the temperature for all of the anal
248. ertion edge must be LH or HL for example a transition from logic state 0 to 1 or from 1 to 0 DATA specifies which node s is to have its setup hold time measured SETUPTIME defines the minimum time that all DATA nodes must be stable prior to the assertion edge of the clock The time value must be a nonnegative constant or expression and is measured in seconds If the device has different setup hold times depending on whether the data is HI or LOW at the clock change you can use either or both of the following forms SETUPTIME_LO lt time value gt SETUPTIME_ HI lt time value gt If either of the time values is 0 then no check is done for that case HOLDTIME is used in the same way as SETUPTIME and also has the alternate _LH and _HL formats and 0 value condition RELEASETIME causes the simulator to perform a special purpose setup check Release time also referred to as recovery time in some data sheets refers to the minimum time that a signal can go inactive before the active clock edge Again the _LH and _HL forms are available The difference between RELEASETIME and SETUPTIME checking is that simultaneous CLOCK DATA transitions are never allowed this assumes a nonzero hold time RELEASETIME is usually not used in conjunction with SETUPTIME or HOLDTIME 279 Chapter 7 Digital device modeling 280 Width WIDTH does the minimum pulse width checking MIN_HI MIN_LO is the minimum time that the node can rem
249. es Collating functions You can further compress the results of Monte Carlo and worst case analyses If you use the collating function a single number represents each run Click the Output File Options button and select a function from the Find list A table of deviations per run is reported in the simulation output file Collating functions are listed in Table 1 Tablel Collating functions used in statistical analyses Function Description YMAX Find the greatest difference in each waveform from the nominal MAX Find the maximum value of each waveform MIN Find the minimum value of each waveform RISE_EDGE Find the first occurrence of the waveform crossing above a specified threshold value FALL EDGE Find the first occurrence of the waveform crossing below a specified threshold value 379 Chapter 13 Monte Carlo and sensitivity worst case analyses Refer to Temperature Effects on Monte Carlo Analysis in the Application Notes manual for more information The example schematic EXAMPLE DSN is provided on the OrCAD installation CD 380 Temperature considerations in statistical analyses The statistical analyses perform multiple runs as does the temperature analysis Conceptually the Monte Carlo and worst case loops are inside the temperature loop However since both temperature and tolerances affect the model parameters OrCAD recommends not using temperature analysis when using Monte Carlo or worst case
250. es multiple analysis runs each with a different value of R1 After the analysis is complete you can analyze curve families for the analysis runs using PSpice A D Setting up and running the parametric analysis To change the value of R1 to the expression Rval 1 2 3 4 In Capture open CLIPPER OPJ Double click the value 1k of part R1 to display the Display Properties dialog box In the Value text box replace 1k with Rva1 Click OK To add a PARAM part to declare the parameter Rval 1 2 10 11 12 From Capture s Place menu choose Part In the Part text box type PARAM from the PSpice library SPECIAL OLB then click OK Place one PARAM part in any open area on the schematic page Double click the PARAM part to display the Parts spreadsheet then click New In the Property Name text box enter Rval no curly braces then click OK This creates a new property for the PARAM part as shown by the new column labeled Rval in the spreadsheet Click in the cell below the Rval column and enter 1k as the initial value of the parametric sweep While this cell is still selected click Display In the Display Format frame select Name and Value then click OK Click Apply to update all the changes to the PARAM part Close the Parts spreadsheet Select the VP marker and press to remove the marker from the schematic page From the File menu choose Save to save the design Parametric anal
251. eset for a flip flop for example To use load bias point 1 Runa simulation using the Save Bias Point option in See Setting up analyses on the Simulation Settings dialog box page 8 289 for a description of the 2 Before running another simulation click the Analysis Se DO tab in the Simulation Settings dialog box 3 Under Options select Load Bias Point 4 Specify a bias point file to load Include the path if the file is not located in your working directory or use the Browse button to find the file 5 Click OK 543 Chapter A Setting initial state 544 Setpoints Pseudocomponents that specify initial conditions are called setpoints These apply to the analog portion of your circuit NODESET 3 4 NODESET 5 Ic Ic2 NODESETI NODESET2 Figure A 1 Setpoints The example in Figure A 1 includes the following IC1 a one pin symbol that allows you to set the initial condition on a net for both small signal and transient bias points IC2 a two pin symbol that allows you to set initial condition between two nets Using IC symbols sets the initial conditions for the bias point only It does not affect the DC sweep If your circuit design contains both an IC symbol and a NODESET symbol for the same net the NODESET symbol is ignored To specify the initial condition edit the value of the VALUE property to the desired initial condition PSpice A D attaches a voltage source with a 0 0002 ohm series resistance to each ne
252. eshold voltage Interface subcircuit selection by PSpice A D This behavior may not be appropriate when the input rise and fall times are long or when the input voltage never leaves the threshold region If this is the case you may want to use the level 2 interface You can avoid simulations that get bogged down with the greater detail of R F and X states around these oscillations You may want to specify level 2 on only those parts for which this behavior is critical to a successful simulation This is described in Setting the default A D interface below 447 Chapter 15 Mixed analog digital simulation 448 Setting the default A D interface For mixed signal simulation you can select the AtoD and DtoA interface level circuit wide and on individual part instances e To select the default interface level circuit wide select one of the four Default A D interfaces in the Digital Setup dialog Part instances whose IO_LLEVEL property is set to 0 will use this value e You can override the circuit wide default on an individual part by specifying an IO_LEVEL property from 1 to 4 where 1 AtoD1 and DtoA1 default 2 AtoD2 and DtoA2 3 AtoD3 and DtoA3 4 AtoD4 and DtoA4 For example you can tell the simulator to use the level 2 interface subcircuits for a 7400 part by setting the IO_LEVEL property to 2 All other part instances continue to use the circuit wide setting By default O_LEVEL is set to 0 which tells
253. essages for errors that occur during a digital simulation with their corresponding waveforms You can view messages from e the Simulation Message Summary dialog box or e the waveform display Message tracking from the message summary A message summary is available for simulations where diagnostics have been logged to the waveform data file You can display the message summary e When loading a waveform data file click OK when the Simulation Errors dialog box appears e Anytime by choosing Simulation Messages from the View menu The Simulation Message Summary dialog box The Simulation Message Summary dialog box lists message header information You can filter the messages displayed in the list by selecting a severity level from the Minimum Severity Level drop down menu Messages are categorized in decreasing order of severity as FATAL SERIOUS WARNING or INFO informational When you select a severity level the Message Summary displays only those messages with the chosen severity or higher By default the minimum severity level displayed is SERIOUS Tracking digital simulation messages See Simulation condition messages on page 14 437 for information on the message types that can be displayed by PSpice A D Time Message Type Device 47 000ns PERSISTENT On OUTPUT Port p4 52 000ns PERSISTENT On OUTPUT Port p12 52 000ns PERSISTENT On OUTPUT Port pS 1 000ns PERSISTENT On OUTPUT Port p15 73 000n
254. et glee sec eset ees specs ecesssesse i 10Hz 109Hz 1 0KHZ 1OKHZ 180KHZ 1 0MHz 10MHz 100MHz 1 0GHz novAo xAY REDO vVAOHXAY 8 UDB Out Fi Figure 24 Small signal response as R1 is varied from 100Q to 10 kQ 2 Click the trace name to select it then press to You can also remove the traces by remove the traces shown removing the VDB marker from your schematic page in Capture 85 Chapter 2 Simulation examples To compare the last run to the first run press 1 From the Trace menu choose Add Trace to display the Add Traces dialog box 2 Inthe Trace Expression text box type the following You can avoid some of the typing for the Vdb Out 1 Vdb Out 21 Trace Expression text box by selecting lick OK V OUT twice in the trace list and inserting CCK OK B text where appropriate in the resulting Note The difference in gain is apparent You can also plot the difference Trace Expression of the waveforms for runs 21 and 1 then use the search commands to find certain characteristics of the difference 4 Plot the new trace by specifying a waveform expression press Insert 5 b C From the Trace menu choose Add Trace In the Trace Expression text box type the following waveform expression Vdb Out 1 Vdb OUT 21 Click OK 5 Use the search commands to find the value of the difference trace at its maximum and at a specific frequency a C d The search command tells PSpice to search for the point on the trace
255. et its value to 0 5 Place an inductor and set its value to 1H place a capacitor and set its value to 1 and place an analog ground symbol 0 from SOURCE OLB Wire the schematic symbols together as shown in Figure 70 Running the simulation Run PSpice A D with the following analyses enabled transient print step 100ms final time 20s parametric swept var type global parameter sweep type linear name R start value 0 5 end value 1 5 increment 0 1 After setting up the analyses start the simulation by choosing Run from the PSpice menu Using performance analysis to plot overshoot and rise time After performing the simulation that creates the data file RLCFILT DAT you can calcualte the specified performance analysis goal functions When the simulation is finished a list appears containing all of the sections runs in the data file produced by PSpice A D To use the data from every run select All and click OK in the Available Selections dialog box In the case of Figure 71 the trace I L1 from the ninth section was added by specifying the following in the Add Traces dialog box I L1 9 Parametric analysis To display the Add Traces dialog box from the Trace menu choose Add Trace or click the Add Trace toolbar button E 367 Chapter 12 Parametric and temperature analysis Troubleshooting tip More than one PSpice A D run or data section is required for performance analysis Because one data value is de
256. eters as well as voltages currents or time Voltages may be either the voltage at a net such as V 5 or the voltage across two nets such as V 4 5 Currents must be the current through a voltage source V device for example I VSENSE Voltage sources with a value of 0 are handy for sensing current for use in these expressions Functions may be used in expressions along with arithmetic operators and and parentheses Available built in functions are summarized in Table 10 on page 3 111 The EVALUE and GVALUE parts are defined in part by the following properties default values are shown EVALUE EXPR V IN IN GVALUE EXPR V IN IN Sources are controlled by expressions which may contain voltages currents or both The following examples illustrate customized EVALUE and GVALUE parts Example 1 In the example of an EVALUE device shown in Figure 49 the output voltage is set to 5 volts times the square root of the voltage between pins IN and IN The property settings for this device are as follows EXPR 5v SQRT V IN IN Example 2 Consider the device in Figure 50 This device could be used as an oscillator for a PSK Phase Shift Keyed modulator A current through a source is a sine wave with an amplitude of 15 mA and a frequency of 10 kHz The voltage at the input pin can shift the phase by 1 radian volt Note the use of the TIME parameter in this PSpice A D equivalent parts
257. f Nominal Figure 78 Summary of Monte Carlo runs for EXAMPLE OP With the List option enabled a report is also generated showing the parameter value used for each device in each run In this case see Figure 79 run three shows the highest deviation 383 Chapter 13 Monte Carlo and sensitivity worst case analyses C ORCADXEXS EXAMPLE SCH HERE UPDATED MODEL PARAMETERS TEMPERATURE 35 000 DEG C MONTE CARLO PASS 3 HEEL JE E JE KEELE LK JE JE KEE KEE EEL EEE EE EEE JE ME AE JE JE JE JE JE EE EEE ELE JE JE E JE JE EE REL EEEERELEREREER xxx CURRENT MODEL PARAMETERS FOR DEVICES REFERENCING cres R_RC1 R_RC2 R 1 03004E 00 9 5053F 0 Figure 79 Parameter values for Monte Carlo pass three 384 Monte Carlo analysis Example Monte Carlo analysis of a pressure sensor This example shows how the performance of a pressure sensor circuit with a pressure dependent resistor bridge is affected by manufacturing tolerances using Monte Carlo analysis to explore these effects Drawing the schematic To begin construct the bridge as shown in Figure 80 oe SGNF 1k PARAMETERS Peoeff 0 06 F a Pron 1 0 Rd R3 Hk 1 P Peget Prigen y Rbreak Por edk Figure 80 Pressure sensor circuit Here are a few things to know when placing and connecting the part e To get the part you want to place from the Place menu choose Part e To rotate a part before placing it press R e For V1and Meter pla
258. ference Manual 106 Behavioral parts Behavioral parts allow you to define how a block of circuitry should work without having to define each discrete component Analog behavioral parts These parts use analog behavioral modeling ABM to define each part s behavior as a mathematical expression or lookup table The OrCAD libraries provide ABM parts that operate as math functions limiters Chebyshev filters integrators differentiators and others that you can customize for specific expressions and lookup tables You can also create your own ABM parts Digital behavioral parts These parts use special behavioral primitives to define each part s functional and timing behavior These primitives are LOGICEXP to define logic expressions PINDLY to define pin to pin delays CONSTRAINT to define constraint checks Many of the digital parts provided in the OrCAD libraries are modeled using these primitives You can also create your own digital behavioral parts using these primitives Using global parameters and expressions for values Using global parameters and expressions for values In addition to literal values you can use global parameters and expressions to represent numeric values in your circuit design Global parameters A global parameter is like a programming variable that When multiple parts are set to the same represents a numeric value by name value global parameters provide a convenient way to change all of their
259. file name 3 Create one or more stimuli to be used in your schematic For each stimulus a Name it whatever you want This name will be used to associate the stimulus specification to the stimulus instance in your schematic or to the symbol in the symbol library bD Provide the transient specification C From the File menu choose Save The Stimulus Editor utility In the schematic page editor configure the Stimulus Editor s output file into your schematic a From the Pspice menu choose Edit Simulation Settings a Inthe Simulation Settings dialog box select the Include Files tab Enter the file name specified in step 2 C Ifthe stimulus specifications are for local use in the current design click the Add to design button For global use by any design use Add as global instead d Click OK Modify either the stimulus instances in the schematic or symbols in the symbol library to reference the new stimulus specification Associate the transient stimulus specification to a stimulus instance a Place a stimulus part in your schematic from the part set VSTIM ISTIM and DIGSTIMn b Click the VSTIM ISTIM or DIGSTIMn instance From the Edit menu choose Properties d Click the Implementation cell type in the name of the stimulus and click Apply e Complete specification of any VSTIM or ISTIM instances by selecting Properties from the Edit menu and editing their DC and AC attributes Click the DC
260. finitions for 3 or 4 terminal devices 296 Element definitions for transmission line devices 297 Element definitions for AC analysis specific elements 298 DC sweep circuit design requirements 0 0 306 310 310 311 Curve family example sete 4 4 54 20 2b eee dae ee ee BAGS 313 325 325 326 326 328 334 336 338 Stimulus symbols for time based input signals 344 Parametric analysis circuit design requirements 364 Collating functions used in statistical analyses 379 386 387 392 Digital stales 4c ob oe REE Bee a a Ro a Pee Oe Ex 411 413 415 418 419 422 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 STIMn part properties 2 6 44 8 2 eae s FILESTIMn part properties Simulation condition messages timing violations Simulation condition messages hazards_ Simulation message output control options Interface subcircuit models Default digital power ground pin connections Digital power supply parts in SPECIAL OLB Digital power supply properties Default waveform viewing c
261. for trace expressions Symbol Unit V volt A amps W watt Trace expressions Example V 5 and v 5 are equivalent in trace expressions Example The quantities 2e 3 2mV and 002v all have the same numerical value For axis labeling purposes PSpice A D recognizes that the second and third forms are in volts whereas the first is dimensionless PSpice also knows that W V A V W A and A W V So if you add this trace V 5 1D M13 the axis values are labeled with W For a demonstration of analog trace presentation see Analog example on page 17 497 529 Chapter 17 Analyzing waveforms For a procedural discussion of digital trace expressions see Analyzing results on page 14 430 in the Digital simulation chapter Example You can request that four bus lines be displayed together as one hexadecimal digit You can combine up to 32 digital signals into a bus Example Q2 Q1 Q0 specifies a 3 bit bus whose high order bit is the digital value at net Q2 Exception You can display your radix designation option with the digital trace expression by leaving the display name blank and using the following syntax digital trace expression radix 530 Table 13 Output units for trace expressions continued Symbol Unit d degree of phase S second Hz hertz Digital trace expressions Digital output variables in trace expressions vary from those used in simulation analyses as f
262. formation to help Refer to your OrCA D Capture you enter circuit designs that simulate properly If you User s Guide for general schematic want an overview use the checklist on page 3 96 to guide entry information you to specific topics Topics include e Checklist for simulation setup on page 3 96 e Using parts that you can simulate on page 3 100 e Using global parameters and expressions for values on page 3 107 e Defining power supplies on page 3 114 e Defining stimuli on page 3 116 e Things to watch for on page 3 120 Chapter 3 Preparing a design for simulation Checklist for simulation setup This section describes what you need to do to set up your circuit for simulation 1 Find the topic that is of interest in the first column of any of these tables 2 Go to the referenced section For those sections that provide overviews you will find references to more detailed discussions Typical simulation setup steps For more information on this step See this To find out this VU Setcomponent values Using parts that you can An overview of vendor passive and other properties simulate on page 3 100 breakout and behavioral parts Using global parameters and How to define values using variable expressions for values on parameters functional calls and page 3 107 mathematical expressions UV Define power supplies UV Define input waveforms UY Set up one or more analyses Defini
263. ft blank RI table type if left blank the frequency table is interpreted in the input frequency magnitude phase format if defined with any value such as YES the table is interpreted in the input frequency real part imaginary part format MAGUNITS units for magnitude where the value can be DB decibels or MAG raw magnitude defaults to DB if left blank PHASEUNITS units for phase where the value can be DEG degrees or RAD radians defaults to DEG if left blank The DELAY property increases the group delay of the frequency table by the specified amount The delay term is particularly useful when an EFREQ or GFREQ device generates a non causality warning message during a transient analysis The warning message issues a delay value that can be assigned to the part s DELAY property for subsequent runs without otherwise altering the table The output of the device depends on the analysis being done For DC and bias point the output is simply the zero frequency magnitude times the value of EXPR For AC analysis EXPR is linearized around the bias point similar to EVALUE and GVALUE parts The output for each frequency is then the input times the gain of EXPR times the value of the table at that frequency For transient PSpice A D equivalent parts analysis the value of EXPR is evaluated at each time point The output is then the convolution of the past values of EXPR with the impulse response of the frequency
264. function are specified as properties for the part Note Voltages currents and TIME may not appear in a Laplace transform specification The output of the part depends on the type of analysis being done For DC and bias point the output is the zero frequency gain times the value of the input The zero frequency gain is the value of the Laplace transform with s 0 For AC analysis the output is then the input times the gain times the value of the Laplace transform The value of the Laplace transform at a frequency is calculated by substituting j o for s where o is 2x frequency For transient analysis the output is the convolution of the input waveform with the impulse response of the transform These rules follow the standard method of using Laplace transforms Example one The input to the Laplace transform is the voltage at net 10 The output is a voltage and is applied between nets 5 and 0 For DC the output is simply equal to the input since the gain at s 0 is 1 The transform 1 1 001 s describes a simple lossy integrator with a time constant of 1 millisecond This can be implemented with an RC pair that has a time constant of 1 millisecond For AC analysis the gain is found by substituting j for s This gives a flat response out to a corner frequency of 1000 27 159 hertz and a roll off of 6 dB per octave after 159 Hz There is also a phase shift centered around 159 Hz In other words the gain has both a real an
265. g characteristics IO_LEVEL Interface subcircuit selection from one of the four analog digital subcircuits provided with the part s I O model DIG_PWR Digital power pin used by the interface subcircuit DIG_GND Digital ground pin used by the interface subcircuit TIMESTEP Number of seconds per clock cycle or step COMMAND1 Stimulus transition specification COMMAND16 statements including time value pairs labels and conditional constructs When placed you must connect each part to the wire or bus of the corresponding radix Generally you only need to modify the FORMAT TIMESTEP and COMMANDn properties Typically each COMMAND property contains only one Refer to the online OrCA D PSpice command line It is possible to enter more than one A D Reference Manual for command line per property by placing n between information about command line syntax command lines in a given definition The n must be lower case and no spaces between characters spaces may precede or follow the entire key sequence 423 Chapter 14 Digital simulation Refer to the online OrCA D PS pice A D Reference Manual for more information about creating digital stimulus specifications and files 424 Using the FILESTIMn parts The FILESTIMn parts have a single pin for connection to the rest of the circuit FILESTIM1 is used for driving a single net FILESTIM2 FILESTIM4 FILESTIM8 FILESTIM16 and FILESTIM32 drive buses that are 2 4 8
266. g else Netlist file The netlist file contains a list of device names values and how they are connected with other devices The name that Capture generates for this file is DESIGN_NAME NET Cirquit file The circuit file contains commands describing how to run the simulation This file also refers to other files that contain netlist model stimulus and any other user defined information that apply to the simulation The name that Capture generates for this file is DESIGN_NAME CIR Other files that you can configure for simulation OrCAD Stimulus Editor ru global model P D l ibraries OrCAD Model Editor model input definitions waveforms a stimulus file simulation primitives ocal model ibraries ustom OrCAD include file PSpice A D Figure 1 User configurable data files that PSpice A D reads Before starting simulation PSpice A D needs to read other files that contain simulation information for your circuit These are model files and if required stimulus files and include files Files needed for simulation Refer to the online OrCA D PSpice A D Reference Manual for the syntax of the statements in the netlist file and the circuit file The circuit file QR that Capture generates contains references to the other user configurable files that PSpice A D needs to read 51 Chapter 1 Things you need to know Note The Stimulus Editor is not included in PSpice A
267. gnal simulations If you are creating parts in one of the logic families already in the model libraries you should reference the existing I O models appropriate to that family The I O models in turn automatically reference the correct interface subcircuits for that family These too are already contained in the model libraries The AtoD interface subcircuit format is shown here SUBCKT ATOD lt name suffix gt lt analog input node gt lt digital output node gt lt digital power supply node gt lt digital ground node gt PARAMS CAPACITANCE lt input load value gt 0 device loading capacitor and other declarations ENDS Input Output characteristics It has four nodes as described The AtoD subcircuit has one parameter CAPACITANCE which corresponds to the input load PSpice A D passes the value of the I O model parameter INLD to this parameter when the interface subcircuit is called The DtoA interface subcircuit format is shown here SUBCKT DIOA lt name suffix gt lt digital input node gt lt analog output node gt lt digital power supply node gt lt digital ground node gt PARAMS DRVL lt 0 level driving resistance gt DRVH lt 1 level driving resistance gt CAPACITANCE lt output load value gt N device loading capacitor and other declarations ENDS It also has four nodes Unlike the AtoD subcircuit the DtoA subcircuit has three parameters PSpice A D will pass the values
268. gth is 23 R Z This could be represented by the device in Figure 42 The parameters R L and C can be defined in a PARAM statement contained in a model file Refer to the online OrCA D PSpice A D Reference Manual for more information about using PARAM statements More useful however is for R L and C to be arguments passed into a subcircuit This part has the following characteristics NUM EXP SQRT C s R L s DENOM 1 This produces a PSpice A D netlist declaration like this GLOSSY 5 O LAPLACE V 10 exp sqrt C s R L s The Laplace transform parts are however an inefficient way in both computer time and memory to implement a delay For ideal delays we recommend using the transmission line part instead Control system parts Math functions The ABM math function parts are shown in Table 1 For each device the corresponding template is shown indicating the order in which the inputs are processed if applicable Tablel ABM math function parts For this device Output is the ABS SORT PWR PWRS LOG LOG10 EXP SIN COS TAN ATAN ARCTAN absolute value of the input square root of the input result of raising the absolute value of the input to the power specified by EXP result of raising the signed input value to the power specified by EXP LOG of the input LOG 9 of the input result of e raised to the power specified by the input value e where x is the in
269. h device as opposed to the parameters for each MODEL statement This is because devices can have different parameter values when using a model statement containing a DEV tolerance Note that for midsize and large circuits the List option can produce a large output file 377 Chapter 13 Monte Carlo and sensitivity worst case analyses In excess of about 10 runs the waveform display can look more like a band than a set of individual waveforms This can be useful for seeing the typical spread for a particular output variable As the number of runs increases the spread more closely approximates the actual worst case limits for the circuit 378 Waveform reports For Monte Carlo analyses there are five variations of the output that you can specify in the Save data from text box on the Monte Carlo dialog box Options lt none gt No output is generated All Forces all output to be generated including nominal run First Generates output only during the first n runs Every Generates output for every nth run Runs list Does specified analysis and generates outputs only for the listed runs up to 25 values can be specified in the list The indicates that you can set the number of runs in the runs text box Values for the output variables specified in the selected analyses are saved to the simulation output file and data file Note Even a modest number of runs can produce large output files Statistical analys
270. h the HI property and a lower limit set with the LO property This part takes one input and provides one output GLIMIT HI upper limit value LO lower limit value GAIN constant gain value The GLIMIT part functions as a one line opamp The gain is applied to the input voltage then the output is constrained to the limits set by the LO and HI properties This part takes one input and provides one output SOFTLIM IT HI upper limit value LO lower limit value GAIN constant gain value A B V internal variables used to define the TANH limiting function The SOFTLIMIT part provides a limiting function much like the LIMIT device except that it uses a continuous curve limiting function rather than a discontinuous limiting function This part takes one input and provides One output Chebyshev filters The Chebyshev filters allow filtering of the signal based on a set of frequency characteristics The output of a Chebyshev filter depends upon the analysis being performed Note PSpice A D computes the impulse response of each Chebyshev filter used in a transient analysis during drcuit read in This may require considerable computing time A message is displayed on your screen indicating that the computation is in progress For DC and bias point the output is simply the DC response of the filter For AC analysis the output for each frequency is the filter response at that frequency For transient analysis the output is then the co
271. hapter A Setting initial state See Setpoints on page A 544 for more information about IC1 and IC2 546 Setting initial conditions The IC property allows initial conditions to be set on capacitors and inductors These conditions are applied during all bias point calculations However if you select the Skip Initial Transient Solution check box in the Transient Analysis Setup dialog box the bias point calculation is skipped and the simulation proceeds directly with transient analysis at TIME 0 Devices with the IC property defined start with the specified voltage or current value however all other such devices have an initial voltage or current of 0 Note Skipping the bias point calculation can make the transient analysis subject to convergence problems Applying an IC property for a capacitor has the same effect as applying one of the pseudocomponents IC1 or IC2 across its nodes PSpice A D attaches a voltage source with a 0 002 ohm series resistance in parallel with the capacitor The IC property allows the user to associate the initial condition with a device while the IC1 and IC2 pseudocomponents allow the association to be with a node or node pair In the case of initial currents through inductors the association is only with a device and so there are no corresponding pseudocomponents The internal implementation is analogous to the capacitor PSpice A D attaches a current source with a 1 Gohm parallel resistance in series
272. hapter in the online OrCAD PSpice A D Reference Manual for more information For the 74160 we have five delay paths the four flip flop outputs to subcircuit outputs QA QD to QA_O QD_O and RCO to RCO_O The five paths are seen in the Delay amp Constraint section of the design For delay paths the number of inputs must equal the number of outputs Since the 74160 does not have TRI STATE outputs there are no enable signals for this example but there are ten reference nodes The first four CLK LOADBAR ENT and CLRBAR are used for both the pin to pin delay specification and the constraint checking The last six ENP A B C D and EN are used only for the constraint checking The PINDLY primitive also allows constraint checking of the model It can verify the setup hold times pulse width and frequency It also has a general mechanism to allow for user defined conditions to be reported The constraint checking only reports timing violations it does not affect the propagation delay or the logic state of the device Since the timing parameters are generally specified at the pin level of the actual device the checking is normally done at 275 Chapter 7 Digital device modeling 276 the interface pins of the subcircuit after the appropriate buffering has been done BOOLEAN The keyword BOOLEAN begins the boolean assignments which define temporary variables that can be used later in the PINDLY primitive The form is
273. he Parameters frame for each extracted model parameter 3 Repeat steps 1 2 until the model meets target behaviors To view updated performance curves 1 On the toolbar click the Update Graph button Note If you view performance curves before fitting then your data points and the curve for the current model specification may not match Using the Model Editor to edit models Running the Model Editor alone After you have selected the part that you want to model you can proceed with Run the Model Editor alone if you want to do any of the entering data sheet information and model following fitting as described in How to fit e create a model and use the model in any design and models on page 4 139 automatically create a part e create a model and have the model definition available to any design without creating a part or e examine or verify the characteristics of a given model without using PSpice A D Running the Model Editor alone means that the model you are creating or examining is not currently tied to a part instance on your schematic page or to a part editing session Note You can only edit models for device types that the Model Editor Supports See Model Editor supported device types on page 4 137 for details Starting the Model Editor To start the Model Editor alone If you have already started the Model Editor from Capture and want to continue 1 From the Start menu point to the OrCAD program working on ne
274. he appropriate paths and know the relative timing of the paths you can do either of the following Modify the stimulus in the case of a simple convergence hazard to rearrange the relative timing of the signals involved Change one or both of the path delays to rearrange the relative timing by adding or removing logic or by substituting component types with components that have different delay characteristics In the case of the cumulative ambiguity hazard the most likely solution is to shorten the path involved You can do this in either of two ways Add a synchronization point to the logic such as a flip flop or gating the questionable signal with a clock having well controlled ambiguity before its ambiguity can grow to unmanageable duration Substitute faster components in the path so that the buildup of ambiguity happens more slowly Methodology Modifying the stimulus is not generally effective for reconvergent hazards because the problem is between the source of the reconvergent fanout and the location of the hazard In this case discounting the common ambiguity did not preclude the hazard 471 Chapter 16 Digital worst case timing analysis 472 Part four Viewing results Part four describes the ways to view simulation results Chapter 17 Analyzing waveforms describes how to perform graphical waveform analysis of simulation results Chapter 18 Other output options describes the special s
275. he appropriate voltage and then turning off the drive The charge which is trapped on the net causes the net s voltage to remain unchanged for some time after the net is no longer driven The technique is not normally used on PCB nets because sub nanoampere input and output leakage currents would be required as well as low coupling from adjacent signals The simulator models the stored charge nets using a simplified switch level simulation technique A normalized with respect to power supply charge or discharge current is calculated for each output or transfer gate attached to the net This current divided by the net s total capacitance is integrated and recalculated at intervals which are appropriate for the particular net The net s digital level is determined by the normalized voltage on the net Only the digital level 1 0 R F X on the net is used by device inputs attached to the net This technique allows accurate simulation of networks of transfer gates and capacitive loads The sharing of charge among several nets which are connected by transfer gates is handled properly because the simulation method calculates the charge transferred between the nets and maintains a floating point value for the charge on the net not just a one or zero Because of the increased computation it takes the simulator longer to simulate charge storage nets than normal digital nets However charge storage nets are simulated much faster than
276. he group delay is 3 2 msec 6912 360 6k 5760 360 6k 3 2m An alternative specification for this table could be TABLE 0 0 0 5kHz 0 0 6kHz 60 0 DELAY 3 2ms 231 Chapter 6 Analog behavioral modeling Figure 54 Voltage multiplier circuit mixer 232 RI MAGUNITS PHASEUNITS This produces a PSpice A D netlist declaration like this ELOWPASS 5 O FREQ V 10 0 0 0 5kHz 0 0 6kHz 60 0 DELAY 3 2ms Cautions and recommendations for simulation and analysis Instantaneous device modeling During AC analysis nonlinear transfer functions are handled the same way as other nonlinear parts each function is linearized around the bias point and the resulting small signal equivalent is used Consider the voltage multiplier mixer shown in Figure 54 This circuit has the following characteristics Vin1 DC 0v AC 1v Vin2 DC 0v AC 1v where the output on net 3 is V 1 V 2 During AC analysis V 3 0 due to the 0 volts bias point voltage on nets 1 2 and 3 The small signal equivalent therefore has 0 gain the derivative of V 1 V 2 with respect to both V 1 and V 2 is 0 when V 1 V 2 0 So the output of the mixer during AC analysis will be 0 regardless of the AC values of V 1 and V 2 Another way of looking at this is that a mixer is a nonlinear device and AC analysis is a linear analysis The output of the mixer has 0 amplitude at the fundamental Output is nonzero at DC
277. he new model instance reference to an existing model e From the Edit menu use the Copy and Paste definition on page 4 159 commands to place more part instances Making instance models available to all designs If you are refining model behavior specific to your design and are ready to make it available to any design then you need to link the model definition to a part and configure it for global use To make your instance model available to any design 1 Create a part and assign the instance model name to See Chapter 5 Creating parts for the Implementation property models for more information 2 Ifneeded move the instance model definition to an appropriate model library and make sure the library is configured for global use See Configuring model libraries on page 4 162 for more information Note If you use the part wizard to create the part automatically from the model definition then this step is completed for you 161 Chapter 4 Creating and editing models General Analysis Include Files Libraries Stimulus Options Data Colection Probe Window Filename Browse Library fies xiti Tachi ib ri Add as Global Add to Design Edit Library Path C Program Files OrCAD Capture Libramy PSpice Browse The Include Files tab contains include files You can manually add design and global indude files to your configuration using the Add to Design and Add as
278. he new parts on a custom graphic standard rather than the OrCAD default parts then you can change which underlying parts either application uses by setting up your own set of parts To create a custom set of parts for automatic part generation 1 Create a part library with the custom parts Be sure to name these parts by their device type as shown in Table 2 this is how the Model Editor Guide determines which part to use for a model definition Table2 Part names for custom part generation Note If you use a custom part set the Model Editor always checks the custom part library first for a part that matches the model definition If none can be found they use the OrCAD default part instead For more information on creating parts refer to the OrCA D Capture User s For this device type Use this part name For this device type Use this part name Bipolar transistor LPNP Bipolar transistor NPN Bipolar transistor PNP Capacitor Diode GaAsFET IGBT N channel Inductor JFET N channel JFET P channel Magnetic core LPNP NPN PNP CAP DIODE GASFET NIGBT IND NJF PIF CORE MOSFET N channel MOSFET P channel OPAMP 5 pin OPAMP 7 pin Resistor Switch voltage controlled Transmission line Voltage comparator Voltage comparator 6 pin Voltage reference Voltage regulator NMOS PMOS OPAMP5 OPAMP7 RES VSWITCH TRN VCOMP VCOMP6 VREF VREG Does not apply
279. he number of bus lines To set bus values introduce transitions using either of the two methods described below 417 Chapter 14 Digital simulation e a Window Help Example 12 Example 12 H Example 12 0 To find out about valid radix values see page 14 433 i Kl Here are some other things that you can do e Move a transition left or right by dicking and dragging e Delete a transition by selecting it and then from the Edit menu choosing Delete or by pressing Delete e Select more than one transition by holding down while clicking 418 To introduce transitions method one 1 2 From the Stimulus Editor s Edit menu choose Add In the digital value field on the toolbar just right of the Add button type a bus value in any of the following ways Table 4 To get this effect Type this A literal value lt unsigned_number gt radix An increment lt unsigned_number gt radix A decrement lt unsigned_number gt radix If you do not enter a radix value the Stimulus Editor appends the default bus radix Click the waveform where you want the transition added Repeat steps 2 and 3 as needed When you finish right click to exit the editing mode To introduce transitions method two From the Stimulus Editor s Edit menu choose Add Place the tip of the pencil shaped pointer on the waveform and click to create transitions as shown here i
280. he simulation na wo A WW N Analyzing the results Concepts you need to understand States When the circuit is in operation digital nodes take on values or output states shown in Table 1 Each digital state has a strength component as well Tablel Digital states Ths Means this state 0 Low false no off 1 High true yes on R Rising changes from 0 to 1 sometime during the R interval F Falling changes from 1 to 0 sometime during the F interval X Unknown may be high low intermediate or unstable Z High impedance may be high low intermediate or unstable Note States do not necessarily correspond to a specific or even stable voltage A logical 1 level means only that the voltage is somewhere within the high range for the particular device family The rising and falling levels only indicate that the voltage crosses the 0 1 threshold at some time during the R or F interval not that the voltage change follows a particular slope Concepts you need to understand Strengths are described in the next section 411 Chapter 14 Digital simulation For additional information on this topic see Defining Output Strengths on page 7 262 of Chapter 7 Digital device modeling 412 Strengths When a digital node is driven by more than one device PSpice A D determines the correct level of the node Each output has a strength value and PSpice A D compares the strengths of the outputs driving the node
281. hen click Next gt In the Name of Trace text box type the following CvF I Vin V 1 In the X value to get Y value at text box type 10K Click Next gt The wizard displays the gain trace for the first run to text the goal function YatX Click Finish 371 Chapter 12 Parametric and temperature analysis The resultant plot is shown in Figure 74 SCHEMATICT P OrCAD PSpice A D_ rlc SCHEMATIC1 Parameti Edt Vi E jew Trace Plt Tools Window Help zF OF ja steage I M 22 4 an ll SCHEMATICT Parametric pn 8 amp a m foe E P E Si E a a a 30u 8 5 o YatX CuF I Uin U 1 16K BB tic SCHEMA For Help press F1 ME Figure 74 Plot of capacitance versus bias voltage 372 Temperature analysis Minimum requirements to run a temperature analysis Minimum circuit design requirements None Minimum program setup requirements 1 In the Simulation Settings dialog box from the Analysis type list box select Time Domain Transient Under Options select Temperature Sweep if it is not already enabled Specify the required parameters for the sweep General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window Analysis type Time Domain Transient gt Run the simulation at temperature 35 9 C Repeat the simulation for each of the temperatures Options a T Gen
282. hich are higher than the value of DIGDRVZ are assigned the Z strength 0 Likewise drive impedances lower than the value of DIGDRVF are assigned the forcing strength 63 Controlling overdrive During a simulation the simulator uses only the strength range number 0 63 to compare the driving strength of outputs The simulator allows you to control how much stronger an output must be before it overdrives the other outputs driving the same node This is controlled with the configurable DIGOVRDRV option By default DIGOVRDRYV is 3 meaning that the strength value assigned to an output must be at least 3 greater than all other drivers before it determines the level of the node The accuracy of the DIGOVRDRYV strength comparison is limited by the size of the strength range DIGDRVZ through DIGDRVF The default drive range of 2 ohms to 20 000 ohms gives strength ranges of 7 5 The accuracy of the strength comparison is 15 In other words depending on the particular values of DRVH and DRVL it might take as much as a factor of 3 45 to overdrive a signal or as little as a factor of 2 55 The accuracy of the comparison increases as the ratio between DIGDRVF and DIGDRVZ decreases Charge storage nets The ability to model charge storage on digital nets is useful for engineers who are designing dynamic MOS integrated circuits In such circuits it is common for the designer to temporarily store a one or zero on a net by driving the net to t
283. iated with them but by minimizing the number of A to D interfaces we speed up the mixed signal 273 Chapter 7 Digital device modeling 274 simulation by reducing the number of necessary calculations For situations where the device is only connected to other digital nodes the buffers have no effect on the simulation The DO_GATE shown in the listing is a zero delay primitive gate timing model For most TTL modeling applications this only serves as a place holder and is not an active part of the model Its function has been replaced by the PINDLY primitive The DO_GATE model can be found in the library file DIG_IO LIB For a more detailed description of digital primitives see the Digital Devices chapter in the online OrCAD PSpice A D Reference Manual IO_STD shown in the listing is the standard I O model This determines the A to D and D to A interface characteristics for the subcircuit The device contains family specific information but the models have been created for nearly all of the stock families The various I O models can be found in the library file DIG_IO LIB The logic expressions themselves are straightforward The first nine are buffering the input signals from outside the subcircuit The rest describe the logic of the actual device up to the flip flops By tracing the various paths in the design you can derive each of the logic equations The DO_EFF timing model shown in the listing is a zero delay default
284. ic t evaluation user data entry what if model data Figure 28 Process and data flow for the Model Editor Creating models from data sheet information The most common way to characterize models is to enter data sheet information for each device characteristic After you are satisfied with the behavior of each characteristic you can have the Model Editor estimate or extract the corresponding model parameters and generate a graph showing the behavior of the characteristic This is called the fitting process You can repeat this process and when you are satisfied with the results save them the Model Editor creates model libraries containing appropriate model and subcircuit definitions Analyzing the effect of model parameters on device characteristics You can also edit model parameters directly and see how changing their values affects a device characteristic As you change model parameters the Model Editor recalculates the behavior of the device characteristics and displays a new curve for each of the affected ones How to fit models For a given model the Model Editor displays a list of the device characteristics and a list of all model parameters and performance curves see Figure 29 24 bipolar lib Q2N2222 OrCAD Model Editor Ybe sat Voltage BEE la x Eie Edt View Model Plot Tools Window Help Dest S mme A Ble efile ModelName Type Creation Date 02N2
285. ic Sweep button 0 Select Global Parameter in the Swept Var Type frame C Select Linear in the Sweep type frame Enter amp in the Name text box Specify values for the Start Value End Value and Increment text boxes The Stimulus Editor utility Chapter 11 Transient analysis 352 You can now set up your usual Transient AC or DC analysis and run the simulation Creating new stimulus symbols 1 Use the Capture part editor to edit or create a part with the following properties Implementation Type PSpice Stimulus Implementation name of the stimulus model STIMTYPE type of stimulus valid values are ANALOG or DIGITAL if this property is nonexistent the stimulus is assumed to be ANALOG Editing a stimulus To edit an existing stimulus 1 Start the Stimulus Editor and select Get from the Stimulus menu 2 Double click the trace name at the bottom of the X axis for analog and to the left of the Y axis for digital traces This opens the Stimulus Attributes dialog box where you can modify the attributes of the stimulus directly and immediately see the effect of the changes To edit a PWL stimulus 1 Double click the trace name This displays the handles for each defined data point 2 Click any handle to select it To reshape the trace drag it to a new location To delete the data point press Del 3 To add additional data points either select Add from the Edit menu or click the Add Point button 4
286. ic information on each primitive type see the online OrCA D PSpice A D Reference Manual Note that some digital primitives such as pullups do not have Timing models See Timing model on page 7 251 for more information 246 e The I O model which specifies information specific to the device s input output characteristics The reason for having two models is that while timing information is specific to a device the input output characteristics are specific to a whole logic family Thus many devices in the same family reference the same I O model but each device has its own timing model Figure 55 presents an overview of a digital device definition in terms of its primitives and underlying model attributes These models are discussed further on Timing model on page 7 251 and Input Output model on page 7 257 Digital primitive syntax The general digital primitive format is shown below U lt name gt lt primitive type gt lt parameter value gt lt digital power node gt lt digital ground node gt lt node gt lt Timing Model name gt lt I O Model name gt MNTYMXDLY lt delay select value gt IO_LEVEL lt interface subckt select value gt where lt primitive type gt lt parameter value gt is the type of digital device such as NAND JKFF or INV It is followed by zero or more parameters specific to the primitive type such as number of inputs The number and meaning of the parame
287. ically create parts for new models 1 2 Note From the Tools menu choose Options If not already checked select Always Create Part to enable automatic part creation Under Save Part To enter the name of the part library for the new part Choose either e Part Library Path Same As Model Library to create or open the OLB file that has the same name prefix as the currently open model library LIB e User Defined Part Library and then enter a file name in the Part Library Name text box If you select a user defined Part library the Model Editor saves all new parts to the specified file until you change it Saving global models and parts Wh en you save your changes the Model Editor does the following for you Tos 1 Saves the model definition to the model library that you originally opened If you had the automatic part creation option enabled saves the part definition to MODEL_LIBRARY_NAME OLB ave the new model and part From the File menu choose Save to update MODEL_LIBRARY_NAME LIB and if you enabled part creation MODEL_LIBRARY_NAME OLB and save them to disk Using the Model Editor to edit models Running the Model Editor from the schematic page editor If you want to Once you have started the Model Editor you can proceed with entering data sheet e test behavior variations on a part or S i information and model fitting as described e refine a model before making it availab
288. ice menu choose Run to perform the analysis PSpice A D uses its own internal time steps for computation The internal time step is adjusted according to the requirements of the transient analysis as it proceeds PSpice A D saves data to the waveform data file for each internal time step To display the input sine wave and clipped wave at V Out 1 From PSpice s Trace menu choose Add Trace 2 In the trace list select V In and V Out by clicking them 3 Click OK to display the traces 4 From the Tools menu choose Options to display the Probe Options dialog box 5 Inthe Use Symbols frame click Always if it is not already enabled 6 Click OK 6 5ms 1 6ns 1 5ms 2 8ns Os o UCIN UCOUT B lt lt Figure 17 Sinusoidal input and clipped output waveforms gt Note The internal time step is different from the Print Step value Print Step controls how often optional text format data is written to the simulation output file 0UT or press Insert These waveforms illustrate the clipping of the input signal 75 Chapter 2 Simulation examples Finding out more about transient analysis Table 2 1 To find out more about this See this transient analysis for analog Chapter 11 Transient and mixed signal designs analysis transient analysis for digital Chapter 14 Digital designs simulation Includes how to set up time based stimuli using
289. identifiable when the circuit does not produce the expected simulation results Identification of timing hazards See the online OrCA D PSpice A D Reference Manual for more information about digital primitives See Methodology on page 16 469 for information on digital worst case timing simulation methodology 467 Chapter 16 Digital worst case timing analysis 468 Glitch suppression due to inertial delay Signal propagation through digital primitives is performed by the simulator subject to constraints such as the primitive s function delay parameter values and the frequency of the applied stimulus These constraints are applied both in the context of a normal well behaved stimulus and a stimulus that represents timing hazards Timing hazards may not necessarily result in the prediction of an X or glitch output from a primitive these are due to the delay characteristics of the primitive which PSpice A D models using the concept of inertial delay A device presented with a combination of rising and falling input transitions assuming no other dominant inputs produces a glitch due to the uncertainty of the arrival times of the transitions see Figure 110 Pee n n TPLHMX TPLHMN Figure 110 Glitch suppression example one However when the duration of the conflicting input stimulus is less than the inertial delay of the device the X result is automatically suppressed by the simulator because it w
290. ied stimulus PSpice A D does not provide this type of static timing verification Worst case timing simulation as provided by PSpice A D is a pattern dependent mechanism that allows a designer to locate timing problems subject to the constraints of a specific applied stimulus Starting worst case timing analysis Starting worst case timing analysis To set up a worst case timing analysis 1 Inthe Simulation Settings dialog box click the See Setting up analyses on Options tab page 8 289 for a description of the 2 Under Category select Gate level Simulation Simulation Settings dialog box Go In the Timing Mode frame check Worst case min max In the Initialize all flip flops drop down list select X Set the Default I O level for A D interfaces to 1 Click OK Start the simulation as described in Starting a simulation on page 8 299 xy Oo wo A Simulator representation of timing ambiguity PSpice A D uses the five valued state representation 0 1 R F X where R and F represent rising and falling transitions respectively Any R or F transitions can be thought of as ambiguity regions Although the starting and final states are known example R is a0 gt 1 transition the exact time of the transition is not known except to say that it occurs somewhere within the ambiguity region The ambiguity region is the time interval between the earliest and the latest time Timing ambiguities propagate through dig
291. ies of several parts in your design is to use the Property Editor as follows 1 Select all of the parts to be modified by pressing and clicking each part 2 From the Edit menu choose Properties The Parts Spreadsheet appears Change the entries in as many of the cells as needed and then click Apply to update all of the changes at once 60 To assign names labels to the off page connectors Label the off page connectors as shown in Figure 2 on page 2 56 1 Double click the name of an off page connector to display the Display Properties dialog box In the Name text box type the new name Click OK Select and relocate the new name as desired To assign names to the parts 1 Double click the second VDC part to display the Parts spreadsheet Click in the first cell under the Reference column Type in the new name Vin Click Apply to update the changes to the part then close the spreadsheet Continue naming the remaining parts until your schematic looks like Figure 2 on page 2 56 To change the values of the parts 1 Double click the voltage label 0V on V1 to display the Display Properties dialog box In the Value text box type 5v Click OK Continue changing the Part Value properties of the parts until all the parts are defined as in Figure 2 on page 2 56 Your schematic page should now have the same parts wiring labels and properties as Figure 2 on page 2 56 To save your design
292. ifference at V In 4 volts 0 0006 71 Diode clipper circuit with a voltage stimulus 72 Stimulus Editor window 64d oe ee dK Re PS a ES EY BS 74 Transient analysis simulation settings 22000 74 Sinusoidal input and clipped output waveforms 75 Clipper circuit with AC stimulus as esas e ee FAP Rae wR 77 AC sweep and noise analysis simulation settings 78 dB magnitude curves for gain at Mid and Out 80 Bode plot of clipper s frequency response ooo a 81 Clipper circuit with global parameter Rval a uaaa aaa 82 Parametric simulation settings o cada aids 84 Small signal response as R1 is varied from 1002 to10kQ 85 Small signal frequency response at 100 and 10 KQ input resistance 87 Performance analysis plots of bandwidth and gain vs Rval 90 Relationship of the Model Editor to Capture and PSpice A D 135 Process and data flow for the Model Editor 138 Model Editor workspace with data for a bipolar transistor 139 Design for a half wave rectifier 2 0 ee ee ee 146 Model characteristics and parameter values for DbreakX 147 Assorted device characteristic curves foradiode 150 Forward Current device curve at two temperatures 151 Figures Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 F
293. ifference to the TABLE part The table translates all values at or below zero to zero and all values greater than or equal to 30 to one All values between 0 and 30 are linearly interpolated The properties for the TABLE part are as follows ROWL 00 ROW2 301 The TABLE part is a simple one and ensures that only a zero value is output to the multiplier for negative anode voltages The output from the TABLE part and the LIMIT part are combined at the MULT multiplier part The output of the MULT part is the product of the two input voltages This value is then raised to the 3 2 or 1 5 power using the PWR part The exponential property of the PWR part is defined as follows EXP 1 5 The last major component is an ABM expression component to take an input voltage and convert it into a current The relevant ABM1 I part property looks like this EXP1 200E 6 V IN A final step in the model is to add device parasitics For example a resistor can be used to give a finite output impedance Capacitances between the grid cathode and anode are also needed The lower part of the schematic in Figure 47 shows a possible method for incorporating these effects To complete the example one could add a circuit which produces the family of I V curves shown in Figure 48 0 OU Z200U 400 o I Cuanode vanode Figure 48 Triode subcircuit producing a family of I V curves Control system parts 219 Chapter 6 Analog beha
294. igure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 XX Rules for pin callout in subcircuit templates 188 LOPASS filter xample 224464 4b 4 ee HES OS Cw EES a C 203 HIPASS filter patlexample 2 lt 6c 4 404 oe tte etene Gees 204 BANDPASS filter part example e404 c 46 eee Gawd Rie ole es 205 BAN DEE filter part example 2 24t40 224 eG EG ESR OYE RS 205 FTABLE part example ca oe ee oS eee eee OER Se ea See x 208 LAPLACE patt exaniple ONG ss s a acs aye ded Sos Kaw es eeo 211 Viewing gain and phase characteristics of a lossy integrator 211 LAPLACE part example WO ae awe eek ASHE EAL SE REE ESS 211 ABM expression part example one 0 0 00 0000048 215 ABM expression part example two 2 2 02 00 eee eee 215 ABM expression part example three 2 2 0 0 0 0 00 00000 4 216 ABM expression part example four 1 65 ce ee ee ee eee 216 Triode Circuit 22 4 c5 62 24 262222 24545 dea Sea e te Bees 217 Triode subcircuit producing a family of I V curves 219 EVALUE part example 66746 2468 OORG BARRE OE TES 223 CVALUE part example 24 4 eee Oe 4 wee eo Ra PRE ERE BO 223
295. ilar to Figure 69 Fourier components Wg SU os as a a eS SS he I I 4 204 4 I I I I I i I I I I I I 1 6U4 I I sf I I i eee I I 2 80 a qr enn eee n l 1 8U 1 6U 1 40 1 2U 1 8U UC u t Figure 69 Hysteresis curve example Schmitt trigger Fourier components Fourier analysis is enabled through the Output File Options dialog box under the Time Domain Transient Analysis type Fourier analysis calculates the DC and Fourier components of the result of a transient analysis By default the first through ninth components are computed however more can be specified Note You must do a transient analysis in order to do a Fourier analysis The sampling interval used during the Fourier transform is equal to the print step specified for the transient analysis When selecting Fourier to run a harmonic decomposition analysis on a transient waveform only a portion of the waveform is used Using the Probe window in PSpice A D a Fast Fourier Transform FFT of the complete waveform can be calculated and its spectrum displayed In the example shown in Figure 65 on page 11 356 the voltage waveform at node OUT2 from the transient analysis is to be used and the fundamental frequency is to be one megahertz for the harmonic decomposition The period of fundamental frequency is one microsecond inverse of the fundamental frequency Only the last one micro
296. ile format is binary However you can save the waveform data file in the Common Simulation Data Format CSDF instead Warning Data files saved in the CSDF format are two or more times the size of binary files When you first open a CSDF data file PSpice A D converts it back to the DAT format This conversion takes two or more times as long as opening a DAT file PSpice A D saves the new DAT file for future use 495 Chapter 17 Analyzing waveforms To save simulation results in ASCII format 1 From PSpice s Simulation menu choose Edit Profile to display the Simulation Settings dialog box General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window Schematic Circuit Data All voltages currents and digital states C All but intemal subcircuit data C At Markers only C None Cancel Apply Help 2 Click the Data Collection tab 3 Select Save data in the CSDF format CSD 4 Click OK PSpice A D writes simulation results to the waveform data file in ASCII format as CSD instead of DAT following the CSDF convention 496 Analog example In this section basic techniques for performing waveform analysis are demonstrated using the analog circuit EXAMPLE OPJ VOU moa readme RAIAS RCI RC2 example rdm ax n cloap zn our 4 dt our ast Ne o RS y y k q212222 4212222 th l at ot 212222 ts _p 3
297. ility to model digital components using logic expressions LOGICEXP and pin to pin delays PINDLY has been added to the simulator Using the LOGICEXP and PINDLY digital primitives you can describe the logic of the device with zero delay and then enter the timing parameters for the pin to pin delays directly from the manufacturer s data sheet Digital primitives still must reference a standard timing model but when the PINDLY device is used the timing models are simply zero delay models that are supplied in DIG_IO LIB The default timing models can be 271 Chapter 7 Digital device modeling 272 found in the same manner as the standard I O models The PINDLY primitive also incorporates constraint checking which allows you to enter device data such as pulse width and setup hold timing from the data sheet Then the simulator can verify that these conditions are met during the simulation Digital primitives Primitives in the simulator are devices or functions which are compiled directly into the code The primitives serve as fundamental building blocks for more complex macro models There are two types of primitives in the simulator gate level and behavioral A gate level primitive normally refers to an actual physical device such as buffers AND gates inverters A behavioral primitive is not an actual physical device but rather helps to define parameters of a higher level model Just like gate level primitives behavioral pr
298. imitives are intrinsic functions in the simulator and are treated in much the same manner They are included in the gate count for circuit size and cannot be described by any lower level model In our 74160 example see The TTL Data Book from Texas Instruments for schematic and description the four J K flip flops are the four digital gate level primitives While flip flops are physically more complex than gates in terms of modeling they are defined on the same level as a gate for example flip flops are a basic device in the simulator Since all four share a common Reset Clear and Clock signal they can be combined into one statement as an array of flip flops They could just as easily have been written separately but the array method is more compact See the Digital Devices chapter in the online OrCA D PSpice A D Reference Manual for more information Creating a digital model using the PINDLY and LOGICEXP primitives Logic expression LOGICEXP primitive Looking at the listing in 74160 example on page 7 280 and at the schematic representation of the 74160 subcircuit you can see that there are three main parts to the subcircuit Following the usual header information SUBCKT keyword subcircuit name interface pin list and parameter list is the LOGICEXP primitive It contains everything in the component that can be expressed in terms of simple combinational logic The logic expression device also serves to buffer other input signals
299. imulus 116 VPWL transient stimulus 116 VPWL_F_N_TIMES transient stimulus 117 VPWL_F_RE_FOREVER transient stimulus 116 VPWL_N_TIMES transient stimulus 117 VPWL_RE_FOREVER transient stimulus 116 VSFFM transient stimulus 117 VSIN transient stimulus 117 VSRC analog stimulus 114 116 325 569 Index VSTIM analog stimulus 116 VSTIM transient stimulus 117 WBREAK current controlled switch 105 XFRM_LINEAR transformer 104 XFRM_NONLINEAR transformer 105 ZBREAK IGBT 105 ABMn and ABMn I ABM 200 214 ABS ABM 200 213 ARCTAN ABM 200 213 ATAN ABM 200 213 BANDPASS ABM 199 204 BANDRE ABM 199 205 CONST ABM 199 201 COS ABM 200 213 DIFF ABM 199 201 DIFFER ABM 199 206 DIGIFPWR power supply 451 E ABM controlled analog source 239 ECL_100K_PWR power supply 451 ECL_10K_PWR power supply 451 EFREQ ABM 220 229 ELAPLACE ABM 220 227 EMULT ABM 220 224 ESUM ABM 220 224 ETABLE ABM 220 225 EVALUE ABM 220 222 223 EXP ABM 200 213 F ABM controlled analog source 239 FTABLE ABM 199 207 G ABM controlled analog source 239 GAIN ABM 199 201 GFREQ ABM 220 229 GLAPLACE ABM 220 227 GLIMIT ABM 199 202 GMULT ABM 220 224 GSUM ABM 220 224 GTABLE ABM 220 225 GVALUE ABM 220 222 223 H ABM controlled analog source 239 HIPASS ABM 199 204 ICn initial condition 544
300. in multiple Probe windows e Compare simulation results from multiple circuit designs in a single Probe window e Display simple voltages currents and noise data e Display complex arithmetic expressions that use the basic measurements e Display Fourier transforms of voltages and currents or of arithmetic expressions involving voltages and currents e For mixed analog digital simulations display analog and digital waveforms simultaneously with a common time base e Add text labels and other annotation symbols for clarification PSpice A D generates two forms of output the simulation output file and the waveform data file The calculations and results reported in the simulation output file act as an audit trail of the simulation However the graphical analysis of information in the waveform data Overview of waveform analysis file is the most informative and flexible method for evaluating simulation results Elements of a plot A single plot consists of the analog lower area and the digital upper area digital area 5 OU panne nen sone nee ena n ee ne eae nan EES nS HESS HEE SEES NESTED EH SENS DEE aenean i i i analog area 2us a U U1 UCU2 Figure 113 Analog and digital areas of a plot You can display multiple plots at a time If you display only analog waveforms the entire plot will be an analog area Likewise if you display only digital waveforms the enti
301. indows You can print all or selected Probe windows with up to nine windows on a single page When you choose Print from the File menu a list of all open Probe windows appears Each Probe window is identified by the unique identifier in parentheses in its title bar The arrangement of Probe windows on the page can be customized using the Page Setup dialog box You can print in either portrait vertical or landscape horizontal orientation You can also use Print Preview to view all of the Probe windows as they will appear when printed 479 Chapter 17 Analyzing waveforms Setting up waveform analysis Setting up colors You can configure Probe display and print colors in e The configuration file PSPICE INI For information on how to use the available e The Probe Options dialog box colors and color order in a Probe window see Configuring trace color ee s i schetmes on pape 17 483 i display and print colors in the PSPICE INI In the PSPICE INI file you can control the following print and display color settings for Probe windows e The colors used to display tra Colors for all items are spedfied as P lt item name gt lt color gt The item names e The colors used for the Probe window foreground and and what they represent are listed in background Table 19 e The order colors are used to display traces Here are the color names you can specify The number of colors used to display traces brightcyan brightblue a
302. ing models are considered inertial with the exception of the delay line primitive DLYLINE To model the noise immunity behavior of digital devices correctly the TPWRT pulse width rejection threshold parameter can be set in the digital device s I O model When pulse width gt TPWRT and pulse width lt propagation delay then the device generates either a 0 R 0 1 F 1 or an X pulse This example shows normal operation in which a pulse of 20 nsec width is applied to a BUF primitive having propagation delays of 10 nsec TPWRT is not set 255 Chapter 7 Digital device modeling See the DLYLINE digital primitive in the online OrCA D PSpice A D Reference Manual 20 40 gt 30 50 PLHTY 10 PHLTY 10 TPWRT not set The same device with a short pulse applied produces no output change p I as 20 22 PLH PHL PWR Y 10 Y 10 not set However if TPWRT is assigned a numerical value 1 or 2 for this example then the device outputs a glitch 20 22 PLHTY PHLTY PWRT Transport delay The delay line primitive is the only simulator model that can propagate any width pulse applied to its input Its function is to skew the applied stimulus by some constant time value For example 256 12 14 DLYTY 4 4 6 10 12 16 18 Input Output characteristics Input Output characteris
303. ing the Stimulus Editor using a file specification or by defining part property values Analog stimuli Analog stimuli include both voltage and current sources The following table shows the part names for voltage sources Table 14 If you want this kind of input Use this part for voltage For DC analyses DC bias For AC analyses AC magnitude and phase For transient analyses exponential periodic pulse piecewise linear piecewise linear that repeats forever VDC or VSRC VAC or VSRC VEXP or VSTIM VPULSE or VSTIM VPWL or VSTIM VPWL_RE_FOREVER or VPWL_F_RE_FOREVER Defining stimuli Table 14 If you want this kind of input Use this part for voltage piecewise linear that repeats n VPWL_N_TIMES or times VPWL_F_N_TIMES frequency modulated sine wave VSFFM or VSTIM sine wave VSIN or VSTIM VSTIM and ISTIM parts require the Stimulus Editor to define the input signal these parts are not available in Basics VPWL_F_RE_FOREVER and VPWL_F_N_TIMES are file based parts the stimulus specification is saved in a file and adheres to PSpice netlist syntax To determine the part name for an equivalent current source Example The current source equivalent to VDC is IDC to VAC is IAC to VEXP is IEXP 1 Inthe table of voltage source parts replace the first V doon in the part name with I Using VSTIM and ISTIM You can use VSTIM and ISTIM parts to define any kind of
304. ing the LIMIT function to keep results within physically realistic bounds 555 Chapter B Convergence and time step too small errors 556 Example A first approximation to an opamp that has an open loop gain of 100 000 is VOPAMP 3 5 VALUE V Cint in 1le5 This has the undesirable property that there is no limit on the output A better expression is VOPAMP 3 5 VALUE LIMIT VCint in 1le5 15v 15v where the output is limited to 15 volts Transient analysis The transient analysis starts using a known solution the bias point It then uses the most recent solution as the first guess for each new time point If necessary the time step is cut back to keep the new time point close enough that the first guess allows the Newton Raphson repeating series to converge The time step is also adjusted to keep the integration of charges and fluxes accurate enough In theory the same considerations which were noted for the bias point calculation apply to the transient analysis However in practice they show up during the bias point calculation first and hence are corrected before a transient analysis is run The transient analysis can fail to complete if the time step gets too small This can have two different effects 1 The Newton Raphson iterations would not converge even for the smallest time step size or 2 Something in the circuit is moving faster than can be accommodated by the minimum step size
305. int to markers and choose Current into Pin b Place a current probe on the left hand pin of the Meter source 7 Switch to the Probe window to see the family of curves for I Meter as a function of P Note For more on analyzing Monte Carlo results in PSpice A D see the next section on Monte Carlo histograms Monte Carlo Histograms You can display data derived from Monte Carlo waveform families as histograms This is part of the performance analysis feature In this example you simulate a fourth order Chebyshev active filter running a series of 100 AC analyses while randomly varying resistor and capacitor values for each run Then having defined performance analysis goal functions for bandwidth and center frequency you observe the statistical distribution of these quantities for the 100 runs Chebyshev filter example The Chebyshev filter is designed to have a 10 kHz center frequency and a 1 5 kHz bandwidth The schematic page for the filter is shown in Figure 83 The stimulus specifications for V1 V2 and V3 are V1 DC 15 V2 DC 15 V3 AC 1 The parts are rounded to the nearest available 1 resistor and 5 capacitor value In this example note how the Another way to view the family of curves without using schematic markers is as follows 1 From PSpice A D s Trace menu choose Add Trace 2 Inthe Simulation Output Variables list double click I Meter Monte Carlo analysis is frequently used to predict yi
306. is is exactly how a double balanced mixer behaves In practice this is a simple multiplier Note A double balanced mixer with inputs at the same frequency would produce outputs at DC at twice the input frequency but these terms cannot be seen with a linear small signal analysis 332 Using a DC source Consider the circuit shown here At the DC bias point PSpice A D calculates the partial derivatives which determine the linear response of the multiplier as follows V Out 9V Out avant V2 Wna V In1 V In2 V In2 V In1 V Out V In1 For this circuit this equation reduces to V Out V In1 2 V In2 0 This means that the multiplier acts as an amplifier of the AC input with a gain that is set by the DC input Caution multiplying AC sources Suppose that you replace the 2 volt DC source in this example with an AC source with amplitude 1 and no DC value DC 0 When PSpice A D computes the bias point there are no DC sources in the circuit so all nodes are at 0 volts at the bias point The linear equivalent of the multiplier block is a block with gain 0 which means that there is no output voltage at the fundamental frequency Noise analysis Setting up and running a noise analysis The following procedure describes the minimum setup requirements for running a noise analysis For more detail on any step go to the pages referenced in the sidebars To set up and run an AC sweep 1 Place and c
307. is on page 12 364 using global parameters Using global parameters and expressions for values on page 3 107 Performance analysis Performance analysis Note Perfomance Analys ww is not supported in PSpice Performance analysis is an advanced feature in VE A D Basics PSpice A D that you can use to compare the characteristics of a family of waveforms Performance analysis uses the principle of search commands introduced earlier in this chapter to define functions that detect points on each curve in the family After you define these functions you can apply them to a family of waveforms and produce traces that are a function of the variable that changed within the family This example shows how to use performance analysis to view the dependence of circuit characteristics on a swept parameter In this case the small signal bandwidth and gain of the clipper circuit are plotted against the swept input resistance value To plot bandwidth vs Rval using the performance analysis wizard 1 In Capture open CLIPPER OPJ 2 From PSpice s Trace menu choose Performance Analysis The Performance Analysis dialog box appears with information about the currently loaded data and performance analysis in general 3 Click the Wizard button At each step the wizard provides i Cliches button information and guidelines 5 In the Choose a Goal Function list click Bandwidth then click the Next gt button 6 Click in the Name of Tr
308. is resistor Type this R3 1k 1 P Pcoeff Pnom R5 2k R6 470 R7 25 3 Repeat steps 1 2 for each resistor on your schematic page To set the DC value for the V1 source and make it visible 1 Double click the V1 source part 2 Inthe Parts Spreadsheet click in the cell under the DC column 3 Type1 35v Monte Carlo analysis Click the Display button In the Display Format frame choose the Value Only option to make the DC value 1 35v visible on the schematic Click OK then click Apply to apply the changes you have made to the part Close the Parts Spreadsheet Setting up the parameters To complete the value specification for R3 define the global parameters Pcoeff P and Pnom To define and initialize Pcoeff P and Pnom 1 2 Place a PARAM part on the schematic page Double click the PARAM part to display the Parts Spreadsheet For each parameter create a new property by clicking New and typing its name Enter its corresponding value by clicking in the cell under the new property name and typing its value Specify the parameter name and corresponding value as follows Table 2 Property Value Pcoeff 0 06 0 Pnom 1 0 4 Click Apply to save the changes you have made then close the Parts Spreadsheet 387 Chapter 13 Monte Carlo and sensitivity worst case analyses When PSpice A D runs a Monte Carlo analysis it uses tolerance values to determine how to vary model pa
309. ital devices via thata transition could ocur whatever paths are sensitized to the specific transitions involved This is normal logic behavior The delay values MIN TYP or MAX skew the propagation of such signals by whatever amount of propagation delay is associated with each primitive instance 459 Chapter 16 Digital worst case timing analysis 460 When worst case MIN MAX timing operation is selected both the MIN and the MAX delay values are used to compute the duration of the timing ambiguity result that represents a primitive s output change For example consider the model of a BUF device in the following figure U5 BUF G_DPWR G_DGND IN1 OUT1 BUFFER model T_BUF I0_ STD MODEL T_BUF UGATE BUF timing model TPLHMN 15ns TPLHTY 25ns TPLHMX 40ns TPHLMN 12ns TPHLTY 20ns TPHLMX 35ns op DS 5 20 45 Figure 98 Timing ambiguity example one The application of the instantaneous 0 1 transition at 5nsec in this example produces a corresponding output result Given the delay specifications in the timing model the output edge occurs at a MIN of 15nsec later and a MAX of 40nsec later The region of ambiguity for the output response is from 20 to 45nsec from TPLHMN and TPLHMxX values Similar calculations apply to a 1 0 transition at the input using TPHLMN and TPHLMX values Propagation of timing ambiguity As signals propagate through the circuit ambiguity is contributed by each primitive having
310. itches works but three or more can cause trouble Bias point and DC sweep Behavioral modeling expressions Range limits Voltages and currents in PSpice are limited to the range 1e10 Care must be taken that the output of expressions fall within this range This is especially important when one is building an electrical analog of a mechanical hydraulic or other type of system Source limits Another consideration is that the controlled sources must turn off when the supplies are almost 0 001 There is special code in PSpice which squelches the controlled sources in a continuous way near 0 supplies However care should still be taken using expressions that have denominators Take for example a constant power load GLOAD 3 5 VALUE 2Watts V 3 5 The first repeating series starts with V 3 5 0 and the current through GLOAD would be infinite actually the code in PSpice which does the division clips the result to a finite value The squelching code is required to be a smooth and well behaved function Note The squelching code cannot be strong enough to suppress dividing by 0 The result is that GLOAD does not turn off near 0 power supplies A better way is described in the application note Modeling Constant Power Loads The squelching code is sufficient for turning off all expressions except those having denominators In general though it is good practice to constrain expressions hav
311. ithin a 5 tolerance To modify example dsn and set up simulation 1 Replace RC1 and RC2 with RBREAK parts setting property values to match the resistors that are being replaced VALUE 10k and reference designators to match previous names 2 Select PSpice Model from the Edit menu Create the model CRES as follows MODEL CRES RES R 1 DEV 5 TC1 0 02 TC2 0 0045 From the File menu choose Save By default Capture saves the definition to the model library EXAMPLE LIB and automatically configures the file for local use with the current schematic 3 In Capture set up a new Monte Carlo analysis as shown in Figure 77 The analysis specification tells PSpice A D to do one nominal run and four Monte Monte Carlo analysis Note Monte Carlo analysis is XNA not supported in PSpice A D led Basics Monte Carlo analysis is frequently used to predict yields on production runs of a circuit TC1 is the linear temperature coefficient TC2 is the quadratic temperature coefficient 381 Chapter 13 Monte Carlo and sensitivity worst case analyses PSpice A D offers a facility to generate histograms of data derived from Monte Carlo waveform families through the performance analysis feature For information about performance analysis see RLC filter example on page 12 366 For information about histograms see Creating histograms on page 13 395 382 Carlo runs saving the DC analysis output from those
312. itional analysis types you want plotted Note Ifyou do not enable an analysis type PSpice A D reports the transient results Generating tables of voltage and current values You can generate tables of voltage and current values on nets for any DC sweep AC sweep or transient analysis To generate tables of voltage or current to the output file 1 Place and connect any of the following parts from the PSpice library SPECIAL OLB Table 19 Use this part To tabulate this VPRINT1 Voltage on the net that the part terminal is connected to VPRINT2 Voltage differential between the two nets that the part terminals are connected to IPRINT Current through a cut in the net Insert this part in series like a current meter 2 Double click the part instance to display the Parts spreadsheet Writing additional results to the PSpice output file 3 Click the property name for the analysis type that you want tabulated DC AC or TRAN 4 In the columns for the analysis type that you want plotted DC AC or TRAN type any non blank value such as Y YES or 1 5 Ifyou selected the AC analysis type enable an output If you do not enable a format PSpice A D format defaults to MAG a Click the property name for one of the following output formats MAG magnitude PHASE REAL IMAG imaginary or DB Type any non blank value such as Y YES or 1 C Repeat the previous steps a and b for as many AC outpu
313. itions radix applies only to bus expressions and denotes the radix in which the bus value is to be displayed the radix is specified as Hor X hexadecimal default D decimal O octal B binary Table 15 presents the operators available for digital signal and bus expressions listed in order of precedence high to low Table 15 Digital logical and arithmetic operators Operator Meaning grouping logical complement multiplication bus values only division bus values only addition bus values only subtraction bus values only amp and A exclusive or or An arithmetic or logical operation between two bus operands results in a bus value that is as wide as is Trace expressions 531 Chapter 17 Analyzing waveforms Example notations for bus constants This notation Has this radix x 3FFFF h 5a a 79 01177400 b 100110 hexadecimal hexadecimal decimal octal binary necessary to contain the result Prior to the operation if necessary the shorter operand is extended to the width of the longer operand by zero filling on the high order end An arithmetic or logical operation between a bus operand and a signal operand results in a bus value Prior to the operation the signal is converted to a bus of width one then extended if necessary You can use signal constants in signal expressions Specify them as shown in Table 16 Table 16 Signal constants for digita
314. itor from Capture stimulus files are automatically configured added to the list as local to the current design Otherwise new stimulus files can be added to the list by entering the file name in the Filename text box and then clicking the Add to design local configuration or Add as global global configuration button Starting the Stimulus Editor The Stimulus Editor is fully integrated with Capture and can be run from either the schematic editor or symbol editor You can start the Stimulus Editor by doing the following 6 Select one or more stimulus instances in the schematic 7 From the Edit menu choose PSpice Stimulus When you first start the Stimulus Editor you may need to adjust the scale settings to fit the trace you are going to add You can use Axis Settings on the Plot menu or the corresponding toolbar button to change the displayed data the extent of the scrolling region and the minimum resolution for each of the axes Displayed Data Range parameters determine what portion of the stimulus data set will be presented on the screen Extent of Scrolling Region parameters set the absolute limits on the viewable range Minimum Resolution parameters determine the tings Transient n General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window Filename The Stimulus Editor utility Analysis Include Files Include files are loaded t valid PSpice commands such as
315. ivalent parts Each E or G part type in the ABM OLB part file is defined by a template that provides the specifics of the transfer function Other properties in the model definition can be edited to customize the transfer function By default the template cannot be modified directly choosing Properties from the Edit menu in Capture Rather the values for other properties such as the expressions used in the template are usually edited then these values are substituted into the template However the part editor can be used to modify the template or designate the template as modifiable from within Capture This way custom parts can be created for special purpose application Implementation of PSpice A D equivalent parts Although you generally use Capture to place and specify PSpice A D equivalent ABM parts it is useful to know the PSpice A D command syntax for E and G devices This is especially true when creating custom ABM parts since part templates must adhere to PSpice A D syntax The general forms for PSpice A D E and G extensions are E lt name gt lt connecting nodes gt lt ABM keyword gt lt ABM function gt G lt name gt lt connecting nodes gt lt ABM keyword gt lt ABM function gt where lt name gt is the device name appended to the E or G device type character lt connecting specifies the lt node name node nodes gt name gt pair between which the device is connected 221
316. ix numbering system in which to display optional bus values Valid entries for radix are shown in the following table Table 11 For this numbering system Use this notation Binary base 2 B Decimal base 10 D Hexadecimal base 16 HorX Octal base 8 O the letter Analyzing results To change the radix without changing the display name be sure to include two consecutive semicolons Example A3 A2 A1 A0 radix 433 Chapter 14 Digital simulation Examples Q2 Q1 Q0 A 0 specifies a 3 bit bus whose most significant bit is Q2 PSpice AJ D labels the plot A and values appear in octal notation a3 a2 al a0 d specifiesa 4 bit bus On the plot values appear in decimal notation Since no display name is specified PSpice A D uses the signal list as a label a 3 0 iS equivalent to a3 a2 al a0 434 To add a bus expression 1 In the Add Traces dialog box in the Functions and Macros list choose Digital Operators and Constants Click the entry In the Simulation Output Variables list select the signals in high order to low order sequence If you want to label the bus with a name that is different from the default a Click in the Trace Expression text box after the last character in the bus name 0 Type display_name where display_name is the name of the label If you want to set the radix to something different from the default a Click in the Trace Expression
317. ize 490 for waveform display 487 Index math function parts ABM 200 213 mathematical expressions ABM 220 messages simulation 437 mixed analog digital circuits 271 288 I O models 445 interface subcircuits 444 power supplies 444 456 waveform display 500 527 530 MNTYMXDLY part property 190 timing model parameter 246 Model Editor about 50 152 analyzing model parameter effects 139 changing MODEL definitions 152 SUBCKT definitions 153 model names 153 creating parts for models 142 173 custom 175 example 156 fitting models 139 starting stand alone 141 startng from the schematic page editor 143 supported device types 137 testing and verifying models 138 tutorial 146 using data sheet information 138 viewing performance curves 140 ways to use 136 model editor running from the schematic page editor 153 model libraries 51 130 adding to the configuration 164 analog list of 121 and duplicate model names 164 configuration 131 configured as include files 163 configuring 53 122 162 digital list of 121 directory search path 167 global vs design 131 165 how PSpice searches them 163 nested 132 OrCAD provided 132 preparing for part creation 172 search order 163 166 MODEL property 129 180 models 567 Index built in 42 changing associations to parts 159 creating parts for custom 175 using the Model Editor 142 173 creating with the Model Editor 152 defined as
318. k ap TR 1T 4 Figure 95 Circuit with a timing ambiguity hazard Note that the output fans out to two devices G2 and L1 The effects of a glitch on G1 in this case do not reach the 436 Analyzing results circuit output P1 because that path is not sensitized since the other input to G2 is held LO and thus blocks the symptom However because G1 s output is also used to clock latch L1 the effects of a glitch could result in visibly incorrect behavior on output P2 This is an example of a persistent hazard A persistent hazard is a timing violation or hazard that has a potential effect on a primary external circuit output or on the internal state stored state or memory elements of the design For the design to be considered reliable you must correct such timing hazards PSpice A D fully distinguishes between state uncertainty and time uncertainty When a hazard occurs PSpice A D propagates hazard origin information along with the machine state through all digital devices When a hazard propagates to a state storage device primitive JKFF DFF SRFF DLTCH RAM PSpice A D reports a PERSISTENT HAZARD Simulation condition messages PSpice A D produces warning messages in various situations such as those that originate from the digital CONSTRAINT devices monitoring timing relationships of digital nodes These messages are directed to the simulation output file and or to the waveform data file Options are avail
319. ks 191 Chapter 5 Creating parts for models 192 Analog behavioral modeling Chapter overview This chapter describes how to use the Analog Behavioral Modeling ABM feature of PSpice A D This chapter includes the following sections e Overview of analog behavioral modeling on page 6 194 e The ABM OLB part library file on page 6 195 e Placing and specifying ABM parts on page 6 196 e ABM part templates on page 6 198 e Control system parts on page 6 199 e PSpice A D equivalent parts on page 6 220 e Cautions and recommendations for simulation and analysis on page 6 232 e Basic controlled sources on page 6 239 Chapter 6 Analog behavioral modeling 194 Overview of analog behavioral modeling You can use the Analog Behavioral Modeling ABM feature of PSpice A D to make flexible descriptions of electronic components in terms of a transfer function or lookup table In other words a mathematical relationship is used to model a circuit segment so you do not need to design the segment component by component The part library contains several ABM parts that are classified as either control system parts or as PSpice A D equivalent parts See Basic controlled sources on page 6 239 for an introduction to these parts how to use them and the difference between parts with general purpose application and parts with special purpose application Control system parts are defined with the reference voltage preset
320. ks 561 Chapter B Convergence and time step too small errors 562 The Last node voltages tried trailer shows the voltages tried at the last Newton Raphson iteration If any of the nodes have unreasonable large values this is a clue that these nodes are related to the problem These voltages failed to converge lists the specific nodes which did not settle onto consistent values It also shows their values for the last two iterations These supply currents failed converge does the same for currents through voltage sources and inductors If any of the listed numbers are 1e10 then that is an indication that the value is being clipped from an unreasonable value Finally These devices failed to converge shows devices whose terminal currents or core fluxes did not settle onto consistent values The message gives a clue as to the part of the circuit which is causing the problem Looking at those devices and or nodes for the problems discussed above is recommended Index ABM ABM part templates 198 ABM OLB 195 basic controlled sources 239 cautions and recommendations for simulation 232 control system parts 199 custom parts 239 frequency domain device models 227 frequency domain parts 227 233 instantaneous models 222 232 overview 194 placing and specifying ABM parts 196 PSpice A D equivalent parts 220 221 signal names 193 simulation accuracy 238 syntax 221 triode modeli
321. l but internal subcircuit data then click OK 4 From the PSpice menu choose Run to start the simulation Limiting file size by suppressing the first part of simulation output Long transient simulations create large waveform data files because PSpice A D stores many data points You can suppress a part of the data from a transient run by setting the simulation analysis to start the output at a time later than 0 This does not affect the transient calculations Viewing waveforms themselves these always start at time 0 This delay only suppresses the output for the first part of the simulation To limit file size by suppressing the first part of transient simulation output 1 From Capture s PSpice menu choose Edit Simulation Settings to display the Simulation Settings dialog box 2 Click the Analysis tab 3 From the Analysis type list select the Time Domain Transient option 4 In the Start saving data after text box type a delay time 5 Click OK to close the Simulation Settings dialog box 6 From the PSpice menu choose Run to start the simulation The simulation begins but no data is stored until after the delay has elapsed Using simulation data from multiple files You can load simulation data from multiple files into the same Probe window by appending waveform data files When more than one waveform data file is loaded you can add traces using all loaded data data from only one file or individual da
322. l is enough Digital parts provided in the standard libraries only use interface levels 1 and 2 With the exception of the HC HCT series described below levels 3 and 4 reference the same subcircuits as levels 1 and 2 Table 15 below summarizes the four interface levels Interface subcircuit selection by PSpice A D That s the letter o not the numeral zero If you are creating custom digital parts in technologies other than those provided in the standard model library you may need to create your own interface subcircuits 445 Chapter 15 Mixed analog digital simulation The elaborate model is noticeably slower than the simple model so you should only use it if you are using a power supply level other than 5 0 volts 446 The difference between levels 1 and 2 only occurs in the AtoD interfaces described below In all cases the level 1 DtoA interface is the same as the level 2 DtoA interface Table 15 Interface subcircuit models Level Subcircuits Definition 1 AtoD1 DtoAl AtoD generates intermediate R F and X levels 2 AtoD2 DtoA2 AtoD does not generate intermediate R F and X levels 3 AtoD3 DtoA3 same as level 1 4 AtoD4 DtoA4 same as level 2 The OrCAD libraries provide two different DtoA models in the HC HCT series the simple model and the elaborate model You can use the simple model by specifying level 1 or 2 the elaborate model by specifying level 3 or 4 The HC HCT level 1 and 2 DtoA mode
323. l small enough that all nonlinearities are turned off When the circuit is linear a solution can be found very near zero of course Then PSpice works its way back up to 100 power supplies using a variable step size Once a bias point is found the transient analysis can be run It starts from a known solution the bias point and steps forward in time The step size is variable and is reduced as needed to find further solutions DC sweep The DC sweep uses a hybrid approach It uses the bias point algorithm varying the power supplies to get started For subsequent steps it uses the previous solution as the initial approximation The sweep step is not variable however If a solution cannot be found at a step then the bias point algorithm is used for that step The whole process relies heavily on continuity It also requires that the circuit be linear when the supplies are turned off 551 Chapter B Convergence and time step too small errors 552 STEPGMIN An alterative algorithm is GMIN stepping This is not obtained by default and is enabled by specifying the circuit analysis option STEPGMIN either using OPTION STEPGMIN in the netlist or by making the appropriate choice from the Analysis Setup Options menu When enabled the GMIN stepping algorithm is applied after the circuit fails to converge with the power supplies at 100 percent and if GMIN stepping also fails the supplies are then cut back to almost zero
324. l trace expressions Signal Constant Meaning 0 low 1 high F falling R rising xX unknown Z high impedance You can use bus constants in bus expressions Specify them as strings of the form r ddd Table 17 This placeholder Means this r case insensitive radix specifier x h d o or b ddd string of digits appropriate to the specified radix 532 For a discussion and demonstration of digital trace presentation complete the Mixed analog digital tutorial on page 17 500 Other output options 18 Chapter overview This chapter describes how to output results in addition to those normally written to the data file or output file e Viewing analog results in the PSpice window on page 18 534 explains how to monitor the numerical values for voltages or currents on up to three nets in your circuit as the simulation proceeds e Writing additional results to the PSpice output file on page 18 535 explains how to generate additional line plots and tables of voltage and current values to the PSpice output file e Creating test vector files on page 18 538 explains how to save digital output states to a file that you can use later as input to another circuit Chapter 18 Other output options If the results move outside of the specified bounds PSpice A D pauses the simulation so that you can investigate the behavior 534 View ing analog results in the PSpice window Captur
325. laced on a top level Setting up analyses schematic page is referred to as Y1 R34 when used in an output variable A lt pin id gt from line 4 is uniquely distinguished by specifying the full part name as described above followed by a colon and the pin name For example the pins on a capacitor with reference designator C31 placed on a top level page and pin names 1 and 2 would be identified as C31 1 and C31 2 respectively Current Specify current in the following format i modifiers lt out device gt modifiers where lt out device gt is a fully qualified device name Modifiers The basic syntax for output variables can be modified to indicate terminals of semiconductors and AC specifications The modifiers come before lt out id gt or lt out device gt Or when specifying terminals such as source or drain the modifier is the pin name contained in lt out id gt or is appended to lt out device gt separated by a colon Modifiers can be specified as follows e For voltage v AC suffix lt out id gt out id v terminal lt out device gt e For current iL AC suffix lt out device gt terminal i terminal AC suffix lt out device gt where terminal specifies one or two terminals for devices with more than two terminals such as D drain G gate S source 293 Chapter 8 Setting up analyses and starting simulation 294 AC suffix specifies the quantity to be reported for an AC an
326. lation ooo 254 Inertial and transport delay aaa aaa des Ox 4 255 Inertial delay corn tule ee Roe e Re AS ES a PRESS s 255 Transport delay 6 w ics Oe we REE ROE we Rw ee wes 256 Input Output characteristics fa bo eke OR Se eR eS 257 Input Output model 052 aa 4 84 o ebb ee GE Awe Slee ee wee 257 Defining Output Strengths 4 4 5 444 255 hea Be ee Oa 262 Configuring the strength scale 004 263 Determining the strength of a device output 263 Controlling overdrive boy 424 4 RSG had eee She es 264 Charge storage nets vse s eee Oey Beate ae GEE Ree Cee 264 Creating your own interface subcircuits for additional technologies 4 1 4 64456 ss aed ee dae 266 Creating a digital model using the PINDLY and LOGICEXP pP MUUVES saos eWay ae ea De YS Eee ee a Ce 271 Digital primitives 9 Se ee ee Geek eS a eh BR RE RS 272 Logic expression LOGICEXP primitive 273 Pin to pin delay PINDLY primitive 4 275 BOOLEAN o rioa pn bhi h HRS tbe ASPET S SS 276 PINDEY ee eee oe A Su ee ee a Oe ee 277 Constraint checker CONSTRAINT primitive 278 Contents Part three Chapter 8 Chapter 9 Setup Old as sc se ee eee eee eV Ewe bee eee Oe eH 279 Widths s 40 0 ose E eee s eA ee ee we ee ie Be ae ee Ss 280 Freg 22124 4342 oos beds Cat eee eeae hace dom amp 280 TATOO EXAMPle 1 s pure a Oo ea ee ee ee ake eee ee 280 Setting Up and Running Analyses Setting up
327. le are used to display the traces in a Probe window You can use e a different color for each trace e the same color for all the traces that belong to the same y axis e the available colors in sequence for each y axis e the same color for all the traces that belong to the same waveform data file To configure trace color schemes in the Probe Options dialog box 1 From the Tools menu choose Options to display the Probe Options dialog box 2 Under Trace Color Scheme choose one of the following options Table 20 Choose this option To do this Normal Match Axis Sequential Per Axis Unique by File Use a different color for each trace for up to 12 traces depending on the number of colors set in the PSPICE INI file Use the same color for all the traces that belong to the same y axis The title of the axis by default 1 2 etc is the same color as its traces Use the available colors in sequence for each y axis Use the same color for all the traces in one Probe window that belong to the same waveform data file 3 Click OK Viewing waveforms View ing waveforms If you are using Capture you can either view waveforms automatically after you run a simulation or you can monitor the progress of the simulation as it is running Setting up waveform display from Capture You can configure the way you want to view the waveforms in PSpice A D by defining display settings in the Pr
328. le to all indiowto fi modeleoa designs page 4 139 then run the Model Editor from the schematic page editor in Capture This means editing models for part instances on your schematic page When you select a part instance and edit its model the schematic page editor automatically creates an instance model that you can then change Note You can only edit models for device types that the Model Editor Supports See Model Editor supported device types on page 4 137 for details What is an instance model For more information on instance models see Reusing instance models on An instance model is a copy of the part s original model The copied model is local to the design You can page 4 160 customize the instance model without impacting any other design that uses the original part from the library When the schematic editor creates the copy it assigns a unique name that is by default original_model_name Xn where nis lt blank 1 2 gt depending on the number of different instance models derived from the original model for the current design 143 Chapter 4 Creating and editing models Starting the Model Editor To start editing an instance model 1 In Capture select one part on your schematic page 2 From the Edit menu choose PSpice Model To find out how Capture searches the The schematic page editor searches the model libraries library see Changing model library for the instance model search order
329. lent parts 221 Modeling mathematical or instantaneous relationships 222 EVALUE and GVALUE parts aaa aaa we 2 ee RS 222 EMULT GMULT ESUM and GSUM 224 Lookup tables ETABLE and GTABLE 225 Frequency domain device models aoaaa a 227 Laplace transforms LAPLACE 6 anaa aaa a 227 Frequency response tables EFREQ and GFREQ 229 Chapter 7 Contents Cautions and recommendations for simulation and analysis 232 Instantaneous device modeling 2 0000 232 Frequency domain parts 22 464 4 dane eS TE ER a 233 Laplace transforms ese Oe ee CH ee BS 233 Non causality and Laplace transforms 235 Chebyshev filters 56a eb bea tov bw eh eee duces 237 Frequency tables socs s sorgos webs ee dome oe Oe a 237 Trading off computer resources for accuracy 238 Basic controlled sources lt 6 4 6 ow ok Bae ee kk ORE Se ee Wy OR 239 Creating custom ABM parts a en de mews Be ER 239 Digital device modeling 241 Chapter Ovefvi Ww gt os 4 b 6 crcr risista Ne Bald ee rti 241 Introduction aoaaa ee 242 Functional behavior aaa aaa a 243 Digital primitive syntax oaoa a 246 Timing characteristics i ooo a 251 Timing model s sswecce s oe p eain are a ee puka ee es d 251 Treatment of unspecified propagation delays 252 Treatment of unspecified timing constraints 253 Propagation delay calcu
330. like this GPSK 11 6 VALUE 15MA SIN 6 28 10kHz TIME V 3 Control system parts 2 BVT SQAT V IN2 IN1 Figure 43 ABM expression part example one Tama SIN 3 Bae TH TIRE VAIN Figure 44 ABM expression part example two 215 Chapter 6 Analog behavioral modeling 4 5 IV SENSE VW S6IN2 SoIN 1 Figure 45 ABM expression part example three 2 13 VINZI EINT ab Figure 46 ABM expression part example four 216 Example three A device EPWR computes the instantaneous power by multiplying the voltage across nets 5 and 4 by the current through VSENSE Sources are controlled by expressions which may contain voltages or currents or both The ABM2 part two inputs current output in Figure 45 could represent this This part is characterized by the following properties EXP1 V amp IN2 4IN1 EXP2 I VSENSE This produces a PSpice A D netlist declaration like this EPWR 3 0 VALUE V 5 4 I VSENSE Example four The output of a component GRATIO is a current whose value in amps is equal to the ratio of the voltages at nets 13 and 2 If V 2 0 the output depends upon V 13 as follows if V 13 0 output 0 if V 13 gt 0 output MAXREAL if V 13 lt 0 output MAXREAL where MAXREAL is a PSpice A D internal constant representing a very large number on the order of 1e30 In general the result of evaluating an expression i
331. ls produce accurate I V curves given a fixed power supply of 5 0 volts and a temperature of 25 C The level 3 and 4 DtoA models produce accurate I V curves over the acceptable range of power supply voltages 2 6 volts and they include temperature derating Level 1 interface The level 1 AtoD interface generates intermediate logic levels R F X between the voltage ranges VILMAX and VIHMIN specific voltages depend on the technology you are using A steadily rising voltage on the input of the AtoD will transition from 0 to Rat VILMAX and from R to 1 at VIHMIN The F level is output for steadily falling voltages in a similar manner The X level is produced if the input voltage starts in the threshold region or doubles back into a previously crossed threshold Level 1 the default strictly maps logic levels onto the changing input voltage The exact switching voltage is assumed to be anywhere between VILMAX and VIHMIN due to temperature or power supply variations Thus it provides more accurate less optimistic results Level 2 interface The level 2 AtoD interface transitions directly from 0 to 1 and 1 to 0 without passing through intermediate R F or X levels An exact switching voltage is assumed again the specific voltage depends on the technology you are using It provides a more optimistic and therefore less accurate response than level 1 Level 2 s behavior is appropriate when the input voltage oscillates around the thr
332. lt 1 minimum 2 typical 3 maximum 4 worst case min max 2 Use this property in the PSPICETEMPLATE property definition MNTYMXDLY is also a subcircuit parameter used in calls for digital subcircuits Example PSPICETEMPLATE X REFDES A B C D PWR GND MODEL PARAMS n TO_LEVEL I0_LEVEL MNTYMXDLY MNTYMXDLY PSPICEDEFAULTNET The PSPICEDEFAULTNET pin property defines the net name to which a hidden invisible pin is connected To use the PSPICEDEFAULTNET property with a digital part 1 For each PSPICEDEFAULTNET property assign the name of the digital net to which the pin is connected Example If power PWR and ground GND pins of a digital part connect to the digital nets G_DPWR and G_DGND respectively then the PSPICEDEFAULTNET properties for these pins are PSPICEDEFAULTNET G_DPWR PSPICEDEFAULTNET G_DGND 2 Use the appropriate hidden pin name in the PSPICETEMPLATE property definition Example If the name of the hidden power pin is PWR and the name of the hidden ground pin is GND then the template might look like this PSPICETEMPLATE X REFDES A B C D PWR GND MODEL PARAMS n TO_LEVEL I0_LEVEL MNTYMXDLY MNTYMXDLY Defining part properties needed for simulation Hidden pins are typically used for power and ground on digital parts Note For clarity the PSPICETEMPLATE property value is shown here in multiple lines in a part definition it is specified in one line no line brea
333. ltage stimulus Transient analysis To add a time domain voltage stimulus 1 8 9 From Capture s PSpice menu point to Markers and choose Delete All Select the ground part beneath the VIN source From the Edit menu choose Cut Scroll down or from the View menu point to Zoom then choose Out Place a VSTIM part from the PSpice library SOURCESTM OLB as shown in Figure 14 From the Edit menu choose Paste Place the ground part under the VSTIM part as shown in Figure 14 From the View menu point to Zoom then choose All From the File menu choose Save to save the design To set up the stimulus 1 2 Select the VSTIM part V3 From the Edit menu choose PSpice Stimulus The New Stimulus dialog box appears In the New Stimulus dialog box type SINI Click SIN sinusoidal then click OK In the SIN Attributes dialog box set the first three properties as follows Offset Voltage 0 Amplitude 10 Frequency 1kHz BI Click Apply to view the waveform The Stimulus Editor window should look like Figure 15 or press Ctri V Note The Stimulus Editor is not included in PSpice A D vy Basics If you do not have the Stimulus Editor 1 Place a VSIN partinstead of VSTIM and double click it 2 In the Edit Part dialog box click User Properties 3 Set values for the VOFF VAMPL and FREQ properties as defined in step 5 When finished click OK 73 Chapter 2 Simulatio
334. model already defined in DIG_IO LIB for use with flip flops All of the delays for the device are defined in the PINDLY section The I O model is IO_STD as identified previously We have not specified a MNTYMXDLY or IO_LEVEL parameter so the default values are used For a more detailed description of the general digital primitives MNTYMXDLY and IO_LEVEL see the Digital Devices chapter in the online OrCA D PSpice A D Reference Manual The primitive MNTYMXDLY specifies whether to use the minimum typical maximum or digital worst case timing values from the device s timing model in this case the PINDLY device For the 74160 MNTYMXDLY is set to 0 This means that it takes on the current value of the DIGMNTYMxX parameter DIGMNTYMx defaults to 2 Creating a digital model using the PINDLY and LOGICEXP primitives typical timing unless specifically changed using the OPTIONS command The primitive IO_LLEVEL selects one of four possible A to D and D to A interface subcircuits from the device s I O model In the header of this subcircuit IO_LEVEL is set to 0 This means that it takes on the value of the DIGIOLVL parameter DIGIOLVL defaults to 1 unless specifically changed using the OPTIONS command Pin to pin delay PINDLY primitive The delay and constraint specifications for the model are specified using the PINDLY primitive The PINDLY primitive is evaluated every time any of its inputs or outputs change See the Digital Devices c
335. model and displays the model for editing e If not found the schematic page editor assumes that this is a new instance model and starts the Model Editor which does the following makes a copy of the original model definition names it original_model_name Xn and displays the new model text for editing Editing model text Saving design models Actions that automatically configure the instance model library for global use instead When you save your edits the following is done for you to make sure the instance model is linked to the selected part instances in your design e The Model Editor saves the model definition to DESIGN_NAME LIB Instance model libraries are normally configured for design use However if you perform the following action the model e If the library is new the Model Editor configures editor configures the library for global use DESIGN_NAME LIB for local use instead e The schematic page editor assigns the new model e Save the model to a different library name to the Implementation property for each of the by typing a new file name in the selected part instances Library text box in the Save To frame To save instance models 1 Inthe Model Editor from the File menu choose Save 2 From the File menu choose Exit to quit the Model Editor 155 Chapter 4 Creating and editing models To find out more about PSpice A D command and netlist syntax refer to the online OrCA D PSpice A D Reference Manual
336. mplates Example R REFDES for a resistor 184 The character in templates The schematic page editor replaces the character with the complete hierarchical path to the device being netlisted The n character sequence in templates The part editor replaces the character sequence n with a new line Using n you can specify a multi line netlist entry from a one line template The character and pin names in templates Pin names are denoted as follows o lt pin name gt where pin name is one or more regular characters The schematic page editor replaces the lt pin name gt clause in the template with the name of the net connected to that pin The end of the pin name is marked with a separator see Property names in templates on page 5 183 To avoid name conflicts in PSpice the schematic page editor translates the following characters contained in pin names Table 5 This pin name character Is replaced with this lt 1 L 8 e XXX XXXbar Note To include a literal character in the netlist type ss in the template Defining part properties needed for simulation PSPICETEMPLATE examples Simple resistor R template The R part has e two pins 1 and 2 e two required properties REFDES and VALUE Template R REFDES 1 2 VALUE Sample translation R_R23 abc def 1k where REFDES equals R23 VALUE equals 1k and R is connected to nets abc and def Voltage source
337. mple consider an asynchronous data change on the input to flip flop FF1 in Figure 94 below The data change is too close to the clock edge e1 resulting in a SETUP violation In a hardware implementation the output of FF1 may or may not change However some designs are not sensitive to this individual missed data because the next clock edge e2 in this example latches the data The designer must judge the significance of timing errors accounting for the overall behavior of the design 435 Chapter 14 Digital simulation 01 od D QD Q Fl FF 02 E c o Heg A A 03 el e2 Figure 94 Circuit with a timing error Timing hazards are most easily identified by simulating a design in worst case timing mode usually close to its critical timing limits Under such conditions PSpice A D reports conditions such as AMBIGUITY CONVERGENCE hazards Again these may or may not pose a problem to the operation of the design However there are identifiable cases that cause major problems An example of a major problem is shown in Figure 95 below Due to the simultaneous arrival of two timing ambiguities having unrelated origins therefore nothing in common at the inputs to gate G1 PSpice A D reports the occurrence as an AMBIGUITY CONVERGENCE hazard This means that the output of G1 may glitch Ge 1 2 04 3 ONA 2 a jy f JA 7408 44 Li PRE ao a a Fe ow
338. n page 14 420 if you wanted to repeat e sequence shown from point A to point B ree times then you would modify the imulus file as shown here added lines are for 3 000000 NCR BY 000000001 00000010 NCR BY 000000001 000000 at You can do this by using a standard text editor to edit a stimulus library file Within this file is a sequence of transitions that produces the original waveform With a text editor you can modify the stimulus definition so it repeats itself To add a loop 1 Inthe Stimulus Editor save and close the stimulus file 2 Ina standard text editor such as Notepad open the stimulus file Enter the path for the stimulus file and click OK For example c lt path gt mydesign STL 4 Find the set of consecutive lines comprising the sequence that you want to repeat Each relevant line begins with the time of the transition and ends with a value or change in value 5 Before these lines insert a line that uses this syntax Repeat for n_times where n_times is one of the following e A positive integer representing the number of repetitions e The keyword FOREVER which means repeat this sequence for an unlimited number of times like a clock signal Defining a digital stimulus 6 Below these lines insert a line that uses this syntax Endrepeat 7 From the File menu choose Save 421 Chapter 14 Digital simulation For information on how to define a clock signal using the
339. n These include e vendor supplied parts e passive parts e breakout parts behavioral parts At minimum a part that you can simulate has these properties e A simulation model to describe the part s electrical behavior the model can be e explicitly defined in a model library e built into PSpice A D or e built into the part for some kinds of analog behavioral parts e A part with modeled pins to form electrical connections in your design e A translation from design part to netlist statement so that PSpice A D can read it in Note Notall parts in the libraries are set up for simulation For example connectors are parts destined for board layout only and do not have these simulation properties Vendor supplied parts The OrCAD libraries provide an extensive selection of manufacturers analog and digital parts Typically the library name reflects the kind of parts contained in the library and the vendor that provided the models Example MOTOR_RF OLB and MOTOR_RF LIB contain parts and models respectively for Motorola made RF bipolar transistors Part naming conventions The part names in the OrCAD libraries usually reflect the manufacturers part names If multiple vendors supply the same part each part name includes a suffix that indicates the vendor that supplied the model Example The OrCAD libraries include several models for the OP 27 opamp as shown by these entries in the online Library List
340. n V 2 is copied from window A to window B the trace looks different because it is determined by data from YOURSIM DAT instead of MYSIM DAT Copying and moving labels Labels can be selected and moved or copied either within For information about adding labels the same Probe window or to another Probe window including text line poly line arrow box circle ellipse and mark refer to the To copy labels online Help in PSpice A D 1 Select one or more hif click labels or select multiple 4 labels by drawing a selection rectangle Selected labels are highlighted From the Edit menu choose Copy or Cut to save the ES labels to the clipboard or Cut removes labels from the Probe window Switch to the Probe window where labels are to be press Ctrl v ie added and from the Edit menu choose Paste Click on the new location to place the labels To move labels 1 Select one or more hift click labels or select multiple labels by drawing a selection rectangle Selected labels are highlighted Move the labels by dragging them to a new location 511 Chapter 17 Analyzing waveforms or Saving the data directly to a file from Clipboard Viewer can create superfluous data at the beginning of the file E oy A 512 Tabulating trace data values You can generate a table of data points reflecting one or more traces in the Probe window and use this information in a document or spreadsheet To
341. n examples press nif F12 Transient optione Buntotime ams seconds TSTOP Pint values in the output fle every 20ns seconds Maximum step size seconds T Skip the initial transient bias point calculation SKIPBP Cees e e Output File Options Figure 16 Transient analysis simulation settings 74 Stimulus Editor chppert stl l lojx 2 Ele Edit Stimulus Plot View Tools Window Help lajxi 1 Bg Stimulus Attributes ES Name SINE Type SIN Otfsetvaue 0 i Amplitude 10 Frequency fm Time Delay pooo Damping Factor pooo Phase Angle ct Cancel Figure 15 Stimulus Editor window 7 Click OK 8 From the File menu choose Save to save the stimulus information Click Yes to update the schematic 9 From the File menu choose Exit to exit the Stimulus Editor To set up and run the transient analysis 1 From Capture s PSpice menu choose New Simulation Profile The New Simulation dialog box appears 2 Inthe Name text box type Transient 3 From the Inherit From list select Schematicl DC Sweep then click Create The Simulation Settings dialog box appears 4 Click the Analysis tab 5 From the Analysis list select Time Domain Transient and enter the settings shown in Figure 16 TSTOP 2ms Start saving data after 20ns Transient analysis 6 Click OK to close the Simulation Settings dialog box 7 From the PSp
342. n input and an output based on a set of data points These parts are described below and on the following pages TABLE ROWn is an input output pair by default up to five triplets are allowed where n 1 2 3 4 or 5 The TABLE part allows the response to be defined by a table of one to five values Each row contains an input and a corresponding output value Linear interpolation is performed between entries For values outside the table s range the device s output is a constant with a value equal to the entry with the smallest or largest input This characteristic can be used to impose an upper and lower limit on the output The TABLE part provides one input and one output FTABLE ROWn either an input frequency magnitude phase triplet or an input frequency real part imaginary part triplet describing a complex value by default up to five triplets are allowed where n 1 2 3 4 or 5 DELAY group delay increment defaults to 0 if left blank RI table type if left blank the frequency table is interpreted in the input frequency magnitude phase format if defined with any value such as YES the table is interpreted in the input frequency real part imaginary part format MAGUNITS units for magnitude where the value can be DB decibels or MAG raw magnitude defaults to DB if left blank PHASEUNITS units for phase where the value can be DEG degrees or RAD radians defaults to DEG if left blank
343. n page 5 173 extract a new model of parts Using the Model Editor to edit models on page 4 135 Basing new parts on a custom set of parts on page 5 175 For a list of device types that the Model Editor supports see Model Editor supported device types on page 4 137 171 Chapter 5 Creating parts for models Model libraries typically have a LIB extension However you can use a different file extension as long as the file format conforms to the standard model library file format For information on managing model libraries induding the search order PSpice A D uses see Configuring model libraries on page 4 162 172 Preparing your models for part creation If you already have model definitions and want to create parts for them you should organize the definitions into libraries containing similar device types To set up a model library for part creation 1 If all of your models are in one file and you wish to keep them that way rename the file to e Reflect the kinds of models contained in the file e Have the LIB extension If each model is in its own file and you want to concatenate them into one file use the DOS copy command Example You can append a set of files with MMOD extensions into a single LIB file using the DOS command copy MOD MYLIB LIB Make sure the model names in your new library do not conflict with model names in any other model library Using the Model Editor to cr
344. n with a practical set of data Your timing simulation methodology should include these key steps e Accurate specification of device delay characteristics e Functional specification of circuit behavior including all don t care states or conditions e Aset of stimuli designed to verify the operation of all functions of the design One common design verification strategy is stepwise identification of the sections of the design that are to be exercised by particular subsets of the stimulus followed by verification of the response against the functional specification Complete this phase using normal not worst case simulation with typical delays selected for the elements The crucial metric here is the state response of the design Note that with rare exception this response consists of defined states and does not include X s The second phase of design verification is to use digital worst case simulation reapplying the functionally correct stimulus and comparing the resulting state response to that obtained during normal simulation Investigate differences at primary observation points such as circuit outputs and internal state variables particularly those due to X states such as critical hazards to determine their cause Starting at those points use the waveform analyzer and the circuit schematic to trace back through the network Continue until you find the reason for the hazard After you identify t
345. nal device parameter that selects either the minimum typical or maximum delay values from the device s timing model If not specified MNTYMXDLY defaults to 0 Valid values are O0 the current value of the circuit wide DIGMNTYMxX option default 2 1 minimum 2 typical 3 maximum 4 worst case timing min max IO_LEVEL is an optional device parameter that selects one of the four AtoD or DtoA interface subcircuits from the device s I O model PSpice A D calls the selected subcircuit automatically in the event a node connecting to the primitive also connects to an analog device If not specified IO_LEVEL defaults to 0 Valid values are Functional behavior 0 the current value of the circuit wide DIGIOLVL option default 1 AtoD1 DtoA1 AtoD2 DtoA2 AtoD3 DtoA3 AtoD4 DtoA4 Ae WN e ll Following are some simple examples of U device declarations U1 NAND 2 G_DPWR G_DGND 1 2 10 DO_GATE I0_DFT U2 JKFF 1 G_DPWR G_DGND 3 5 200 3 3 10 2 D_293ASTD I0_STD U3 INV S G_DPWR G_DGND IN OUT D_INV IO_INV MNTYMXDLY 3 IO_LEVEL 2 For example the 74393 part could be defined as a subcircuit composed of U devices as shown below subckt 74393 A CLR QA QB QC QD optional DPWR G_DPWR DGND G_DGND params MNTYMXDLY 0 IO_LEVEL 0 UINV inv DPWR DGND CLR CLRBAR DO_GATE IO_STD IOQ_LEVEL IO_LEVEL Ul gkff 1 DPWR DGND D_HI CLRBAR A D_HI
346. nd expressions can be selected and moved or copied either within the same Probe window or to another Probe window To copy or move trace names and expressions 1 Click one or more hift click trace names Selected trace names are highlighted From the Edit menu choose Copy or Cut to save the trace names and expressions to the clipboard Cut removes trace names and traces from the Probe window In the Probe window where traces are to be added do one of the following e To add trace names to the end of the currently displayed set choose Paste from the Edit menu e To add traces before a currently displayed trace name select the trace name and then choose Paste from the Edit menu Here are some considerations when copying or moving trace names and expressions into a different Probe window If the new Probe window is reading the same waveform data file the copied or moved trace names and expressions display traces that are identical to the original selection set If the new Probe window is reading a different waveform data file the copied or moved names and expressions display different traces generated from the new data For example suppose two waveform data files MYSIM DAT and YOURSIM DAT each contain a V 2 waveform Suppose also that two Probe windows are currently displayed where window A is loaded with MYSIM DAT and window B is loaded with YOURSIM DAT User interface features for waveform analysis Whe
347. ned in the WC statement as a function of any standard output variable in a specified range of the sweep Ina given range reduce the measurement to a single value by one of these five collating functions MAX Maximum output variable value MIN Minimum output variable value YMAX Output variable value at the point where it differs the most with the nominal run RISE_EDGE Sweep value where the output value variable value crosses above a given threshold value FALL_EDGE Sweep value where the output value variable value crosses below a given threshold value You can define Worst as the highest HI or lowest LO possible collating function relative to the nominal run Procedure To establish the initial value of the collating function worst case analysis begins with a nominal run using all model parameters at their nominal values Next multiple sensitivity analyses determine the individual effect of each model parameter on the collating function This is accomplished by varying model parameters one at a time in consecutive simulations The Worst case analysis You can define models for nearly all primitive analog circuit parts such as resistors capacitors inductors and semiconductor devices PSpice A D reads the standard model parameter tolerance syntax specified in the MODEL statement For each model parameter PSpice A D uses the nominal minimum and maximum probable values and the DEV and or LOT specifier
348. nformation Subcircuit expansion and Load Bias files Statements included from libraries Device summary Ss ke ord Node summary connections Circuit file statements Model parameter values Digital timing and hazard messages Page breaks and banners for each section Value of each PSpice option Number of digits in printed values js Output file with 80 characters OPTION ACCT EXPAND LIBRARY LIST NOBIAS NODE NOECHO NOMOD NOOUTMSG NOPAGE OPTS NUMDG Reset Cancel Apply Help Small signal DC transfer Small signal DC transfer Minimum requirements to run a small signal DC transfer analysis Minimum circuit design requirements e The circuit should contain an input source such as VSRC Minimum program setup requirements 1 Under Analysis type in the Simulation Settings dialog box select Bias Point 2 Specify the name of the input source desired See Output variables on page 8 292 for a description of output variable formats 3 Click OK to save the simulation profile 4 In Capture from the PSpice menu select Run to start the simulation 317 Chapter9 DC analyses 318 Overview of small signal DC transfer The small signal DC transfer analysis calculates the small signal transfer function by transforming the circuit around the bias point and treating it as a linear circuit The small signal gain input resistance and output resistance are calculated
349. ng example 217 AC stimulus property 326 AC sweep analysis 288 323 324 about 324 displaying simulation results 79 example 77 329 introduction 44 noise analysis 288 333 setup 77 324 327 stimulus 325 treatment of nonlinear devices 331 ACMAG stimulus property 326 ACPHASE stimulus property 326 adding a stimulus 73 AGND ground part 124 ambiguity cumulative hazard 439 analog behavioral modeling see ABM analog parts basic components ABM 199 201 basic controlled sources ABM 239 behavioral 106 bipolar transistors 137 297 525 527 breakout 105 capacitors 295 Chebyshev filters 199 203 237 393 Darlington model transistors 137 diodes 137 295 526 expression parts ABM 200 214 frequency table parts ABM 220 229 237 GaAsFET 296 525 526 IGBT 137 297 525 inductors 295 Index integrators and differentiators ABM 199 206 JFET 137 296 525 526 Laplace transform ABM 200 210 220 227 233 limiters ABM 199 202 math functions ABM 200 213 mathematical expressions ABM 220 MOSFET 137 297 525 526 nonlinear magnetic core 137 opamp 137 passive 104 PSpice A D equivalent parts ABM 220 resistors 296 527 switch 527 table look up ABM 199 206 220 225 transmission lines 297 525 vendor supplied 101 voltage comparator 137 voltage reference 137 voltage regulator 137 analyses AC sweep 11 288 323 324 bias point detail 62 288 DC sensitivity 2
350. ng power supplies on Anoverview of DC power for age 3 114 analog circuits and digital power for mixed signal circuits Defining stimuli on An overview of DC AC and page 3 116 time based stimulus parts Chapter 8 Setting up Procedures general to all analysis analyses and starting types to set up and start the simulation simulation Chapter 9 through Detailed information about DC AC Chapter 14 see the table of transient parametric temperature contents Monte Carlo sensitivity worst case and digital analyses 96 For more information on this step Checklist for simulation setup See this WY Place markers Using schematic page markers to add traces on page 17 487 Limiting waveform data file size on page 17 490 How to display results in PSpice by picking design nets How to limit the data file size Advanced design entry and simulation setup steps For more information on this step See this To find out how to WY Create new models VY Create new parts Chapter 4 Creating and editing models Chapter 6 Analo behavioral modeling Chapter 7 Digital device modeling Chapter 5 Creating parts for models The OrCAD Capture User s Guide Define models using the Model Editor or Create Subcircuit command Define the behavior of a block of analog circuitry as a mathematical function or lookup table Define the functional timing and I O charac
351. node being evaluated and the remainder of the CASE function is ignored If none of the expressions evaluate to TRUE then the DEFAULT delay is used Since it is possible for none of the expressions to yield a TRUE result you must include a default delay in every CASE function Also note that the expressions must be separated by a comma In the PINDLY section of the PINDLY primitive in the model listing the four output nodes QA_O through QD_O all use the same delay rules The CASE function is evaluated independently for each of the outputs in turn The first delay expression is CLOCK amp LOADBAR 1 amp TRN_LH DELAY 1 13NS 20NS This means that if CLOCK is TRUE and LOADBAR is equal to 1 and QA_O is transitioning from 0 to 1 then the values of 1 13ns and 20ns are used for the MINIMUM TYPICAL and MAXIMUM propagation delay for the CLK to QA data output of the chip In this case the manufacturer did not supply a minimum prop delay so we used the value 1 to tell the simulator to derive a value from what was given If this statement is TRUE then the simulator assigns the values and move on to the CASE function for QB_O and eventually RCO_O For instances where one or more propagation delay parameters are not supplied by the data sheet the simulator derives a value from what is known and the values specified for the OPTION DIGMNTYSCALE and DIGTYMXSCALE 277 Chapter 7 Digital device modeling 278 When the typical v
352. nput resistor R1 Connect the other end of R1 to the output capacitor Connect the diodes to each other and to the wire between them a Click the connection point of the cathode for the lower diode Move the cursor straight up and click the wire between the diodes The wire ends and the junction of the wire segments becomes visible Click again on the junction to continue wiring d Click the end of the upper diode s anode pin Continue connecting parts until the circuit is wired as shown in Figure 2 on page 2 56 To assign names labels to the nets 1 From the Place menu choose Net Alias to display the Place Net Alias dialog box In the Name text box type Mid Click OK Place the net alias on any segment of the wire that connects R1 R2 R3 the diodes and the capacitor The lower left corner of the net alias must touch the wire Right click and choose End Mode to quit the Net Alias function Example circuit creation lt To stop wiring right dick and choose End Wire The pointer changes to the default arrow Clicking on any valid connection point ends a wire A valid connection point is shown as a box see Figure 3 R1 BVA 1k Figure 3 Connection points If you make a mistake when placing or connecting components 1 From the Edit menu choose Undo or dick o 59 Chapter 2 Simulation examples A more efficient way to change the names values and other propert
353. ns Editing part graphics When changing part graphics check to see that all pins are on the grid For more information about specific part editing tasks refer to the OrCA D Capture User s Guide 177 Chapter 5 Creating parts for models Note Pin changes that alter the part template can occur if you either e change pin names or e delete pins In these cases you must adjust the value of the part s PSPICETEMPLATE property to reflect these changes To find out how see Pin callout in subcircuit templates on page 5 187 178 5 After you have finished editing the part from the File menu choose Save to save the part to its library Defining grid spacing Grid spacing for graphics The grid denoted by evenly spaced grid points regulates the sizing and positioning of graphic objects and the positioning of pins The default grid spacing with snap to grid enabled is 0 10 and the grid spacing is 0 01 You can turn off the grid spacing when you need to draw graphics in a tighter space To edit the part graphics 1 In Capture s part editor display the part you want to edit 2 Select the line arc circle or other graphic object you want to change and do any of the following e To stretch or shrink the graphic object click and drag one of the size handles e Tomove the entire part graphic click and drag the edge of the part The part body border automatically changes to fit the size of th
354. nse at nets pins and parts that you marked in your schematic cross probing You can set up your design so PSpice A D displays the results as the simulation progresses or after the simulation completes After PSpice A D has read the data file and displays the initial set of results you can add more waveforms and to perform post simulation analysis of the data PSpice output file The PSpice output file is an ASCII text file that contains e the netlist representation of the circuit e the PSpice command syntax for simulation commands and options like the enabled analyses e simulation results and e warning and error messages for problems encountered during read in or simulation Its content is determined by e the types of analyses you run e the options you select for running PSpice A D and e the simulation control symbols like VPRINT1 and VPLOT1 that you place and connect to nets in your design Simulation examples Chapter overview The examples in this chapter provide an introduction to the methods and tools for creating circuit designs running simulations and analyzing simulation results All analyses are performed on the same example circuit to clearly illustrate analysis setup simulation and result analysis procedures for each analysis type This chapter includes the following sections e Example circuit creation on page 2 56 e Performing a bias point analysis on page 2 62 e DC sweep analysis on page 2 6
355. nsitions digital 415 transient analog mixed signal 344 transient digital 413 subcircuits 129 analog digital interface 444 creating SUBCKT definitions from designs 133 creating SUBCKT definitions from schematics 157 tools to create 133 ways to create edit 134 see also models switch 527 problems 554 system variables in expressions 113 T table look up parts ABM 199 206 220 225 temperature analysis 289 373 introduction 46 with statistical analyses 380 TEMPLATE property 182 and non simulation parts 182 examples 185 naming conventions 183 regular characters 182 special characters 184 571 Index test vector file 538 thermal noise 337 TIME Probe output variable 522 TIMESTEP stimulus property digital 423 timing model 245 248 251 hold times TH 251 inertial delay 255 loading delay 254 propagation delays 251 428 calculation 254 DIGMNTYSCALE 252 DIGTYMXSCALE 252 MNTYMXDLY 246 unspecified 252 pulse widths TW 251 setup times TSU 251 switching times TSW 251 transport delay 256 unspecified timing constraints 253 timing violations and hazards convergence 439 cumulative ambiguity 439 persistent hazards 435 total noise 334 circuit 337 per device 337 TPWRT I O model 255 258 traces adding 68 direct manipulation 505 displaying 68 75 markers 490 output variables 519 placing a cursor on 70 transformer problems 559 transient analysis 2
356. nt analysis does its own calculation of a bias point to start with using the same technique as described for DC sweep This is necessary because the initial values of the sources can be different from their DC values To report the small signal parameters for the transient bias point use the Transient command and enable Detailed Bias Point Otherwise if you simply want the result of the transient run itself you should only enable the Transient command In the simulation output file EXAMPLE OUT the bias point report for the transient bias point is labeled INITIAL TRANSIENT SOLUTION 357 Chapter 11 Transient analysis See Chapter 14 Digital simulation for more information on the digital timing analysis of PSpice A D 358 Internal time steps in transient analyses During analog analysis PSpice A D maintains an internal time step which is continuously adjusted to maintain accuracy while not performing unnecessary steps During periods of inactivity the internal time step is increased During active regions it is decreased The maximum internal step size can be controlled by specifying it in the Step Ceiling text box in the Transient dialog box PSpice A D will never exceed either the step ceiling value or two percent of the total transient run time whichever is less The internal time steps used may not correspond to the time steps at which information has been requested to be reported The values at the print time ste
357. ntax DC DC_value units AC magnitude_value units phase_value Using VSRC or ISRC parts The VSRC and ISRC parts have one property for each analysis type DC AC and TRAN You can set any or all of them using PSpice netlist syntax When you give them a value the syntax you need to use is as follows Table 16 This property Has this syntax DC DC_value units AC magnitude_value units phase_value TRAN time based_ty pe parameters where time based_type is EXP PULSE PWL SFFM or SIN and the parameters depend on the time based_type Note OrCAD recommends that if you are running only a transient analysis use a VSTIM or ISTIM part if you have the standard package or one of the other time based source parts that has properties specific for a waveform shape Digital stimuli Table 17 If you want this kind of input Use this part For transient analyses signal or bus any width DIGSTIMn clock signal DIGCLOCK 1 bit signal STIM1 4 bit bus STIM4 8 bit bus STIM8 16 bit bus STIM16 file based signal or bus any width FILESTIMn The DIGSTIM part requires the Stimulus Editor to define the input signal these parts are not available in Basics Defining stimuli For the syntax and meaning of transient source specifications refer to the V independent current and voltage source device type in the A nalog Devices chapter in the online OrCA D PSpice A D Reference Manual You can use
358. ntrol system parts grouped by function Also listed are characteristic properties that may be set In the sections that follow each part and its properties are described in more detail Table9 Control system parts Category Part Description Properties Basic CONST constant VALUE components SUM adder MULT multiplier GAIN gain block GAIN DIFF subtracter Limiters LIMIT hard limiter LO HI GLIMIT limiter with gain LO HI GAIN SOFTLIM soft tanh limiter LO HI GAIN Chebyshev LOPASS lowpass filter FP FS RIPPLE filters STOP HIPASS highpass filter FP FS RIPPLE STOP BANDPASS bandpass filter FO F1 F2 F3 RIPPLE STOP BANDREJ band reject FO F1 F2 F3 notch filter RIPPLE STOP Integrator and INTEG integrator GAIN IC differentiator DeFER differentiator GAIN Table look ups TABLE lookup table ROW1 ROW5 FTABLE frequency lookup ROW1 ROW5 table Control system parts 199 Chapter 6 Analog behavioral modeling 200 Table9 Control system parts continued Category Part Description Properties Laplace LAPLACE Laplace NUM DENOM transform expression Math functions ABS Ixl o x is the SORT 1 2 PWR x EXP EXP PWRS xEXP EXP LOG In x LOG10 log x EXP ex SIN sin x COS cos x TAN tan x ATAN tan x ARCTAN tan x Expression ABM no inputs Vout EXP1 EXP4 neice ABM1 linput Vout EXP1 EXP4 ABM2 2 inputs V out EXP1 EXP4 ABM3 3 inputs V out EXP1 EXP4 ABM I no input I out EX
359. nvolution of the past values of the input with the impulse response of the filter These rules follow the standard method of using Fourier transforms Note To obtain a listing of the filter Laplace coefficients for each stage choose Setup from the Analysis menu click on Options and enable LIST in the Options dialog box Each of the Chebyshev filter parts is described in the following pages LOPASS FS stop band frequency FP pass band frequency RIPPLE pass band ripple in dB STOP stop band attenuation in dB The LOPASS part is characterized by two cutoff frequencies that delineate the boundaries of the filter pass band and stop band The attenuation values RIPPLE and STOP define the maximum allowable attenuation in the pass band and the minimum required attenuation in the stop band respectively The LOPASS part provides one input and one output Figure 35 shows an example of a LOPASS filter device The filter provides a pass band cutoff of 800 Hz and a stop Control system parts OrCAD Capture recommends looking at one or more of the references cited in Frequency domain device models on page 6 227 as well as some of the following references on analog filter design 1 Ghavsi M S amp Laker K R Modern Filter Design Prentice Hall 1981 Gregorian R amp Temes G Analog MOS Integrated Circuits Wiley Interscience 1986 Johnson David E Introduction to Filter Theory Prentice Hall 1976 Lindquist
360. o find out how amps units are optional and the to specify the TRAN property optional phase_value is in degrees 326 AC sweep analysis Setting up an AC analysis To set up the AC analysis 1 From the PSpice menu choose New Simulation Profile or Edit Simulation Settings If this is a new simulation enter the name of the profile and click OK The Simulation Settings dialog box appears Simulation Settings AC Sweep ix General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window Analysis type AC Sweep Type ACS Noise Linear Start Frequency fi 0 Options Logarithmic End Frequency f1 00K General Settings Monte Carlo Wworst Case Parametric Sweep CTemperature Sweep Noise Analysis I Enabled Total Points fi 0 Cancel Apply Help 2 Choose AC Sweep Noise in the Analysis type list box 3 Under Options select General Settings if it is not already enabled 4 Set the number of sweep points as follows 327 Chapter 10 AC analyses If you also want to run a noise analysis then before clicking OK complete the Noise Analysis frame in this dialog box as described in Setting up a noise analysis on page 10 335 328 Table 6 To sweep frequency Do this linearly logarithmically by decades logarithmically by octaves Under AC Sweep Type click Linear and enter the
361. o ground Example The circuit shown below connects capacitors DC open circuits such that both ends of inductor L2 are isolated from ground L1 C1 L2 c3 1 3 4 4 10uH in 10uH in 1k When simulated PSpice A D flags nets 2 and 3 as floating The following topology solves this problem ii C1 5 L2 c3 1 3 E o 10uH in 10uH in Vi Things to watch for This applies to analog only and mixed signal circuits Note When calculating the bias point solution PSpice A D treats capacitors as open circuits and inductors as short circuits 125 Chapter 3 Preparing a design for simulation 126 Creating and editing models Chapter overview This chapter provides information about creating and editing models for parts that you want to simulate Topics are grouped into four areas introduced later in this overview If you want to find out quickly which tools to use to complete a given task and how to start then 1 Go to the roadmap in Ways to create and edit models on page 4 134 2 Find the task you want to complete 3 Go to the sections referenced for that task for more information about how to proceed Background information These sections present model library concepts and an overview of the tools that you can use to create and edit models e What are models on page 4 129 e How are models organized on page 4 130 Chapter 4 Creating and editing models 1
362. o the online Library List 132 Nested model libraries Besides model and subcircuit definitions model libraries can also contain references to other model libraries using the PSpice LIB syntax When searching model libraries for matches PSpice A D also scans these referenced libraries Example Suppose you have two custom model libraries MYDIODES LIB and MYOPAMPS LIB that you want PSpice A D to search any time you simulate a design Then you can create a third model library MYMODELS LIB that contains these two statements LIB mydiodes lib LIB myopamps 1ib and configure MYMODELS LIB for global use Because MYDIODES LIB and MYOPAMPS LIB are referenced from MYMODELS LIB they are automatically configured for global use as well OrCAD provided models The model libraries that you initially install with your OrCAD programs are listed in NOM LIB This file demonstrates how you can nest references to other libraries and models If you click the Libraries tab in the Simulation Settings dialog box immediately after installation you see the NOM LIB entry in the Library Files list The asterisk means that this model library and any of the model libraries it references contain global model definitions Tools to create and edit models There are three tools that you can use to create and edit model definitions Use the e Model Editor when you want to e derive models from data sheet curves provided by manufacturers or
363. o which the new power supply should apply then change the appropriate pin properties as follows PSPICEDEFAULTNET MY_VDD PSPICEDEFAULTNET MY_VSS Specifying digital power supplies Designs with TTL and ECL parts rarely require secondary power supplies If needed however you can use this procedure to add a secondary power supply for TTL and ECL parts 453 Chapter 15 Mixed analog digital simulation These node names are used in the output variables in the list of viewable traces when you choose Add Trace from the Trace menu 454 Interface generation and node names The majority of the interface generation process involves PSpice A D determining whether analog and digital primitives are connected and if so inserting an interface subcircuit for each digital connection This turns the interface node into a purely analog node which now connects to the analog terminal of the interface subcircuit To complete the original connection PSpice A D creates a new digital node between the digital terminal of the interface subcircuit and the digital primitive Because PSpice A D must create new digital nodes it must give them unique names Name generation follows these rules e The analog node retains the name of the original interface node either the labeled wire name in the design or the node name automatically generated for an unlabeled wire e Each new digital node name consists of the labeled wire name in the design
364. o zoomed User interface features for waveform analysis Scrolling traces By default when a plot is zoomed or when a digital plot contains more traces than can be displayed in the visible area standard scroll bars appear to the right or at the bottom of the plot area as necessary These can be used to pan through the data You can configure scroll bars so they are always present or are never displayed To configure scroll bars 1 InPSpice A D from the Tools menu choose Options 2 Inthe Use Scroll Bars frame choose one of the scroll bars options as described below Table 1 Choose this option To do this Auto Have scroll bars appear when a plot is zoomed or when additional traces are displayed in the plot but are not visible default Never Never display scroll bars This mode provides maximum plot size and is useful on VGA and other low resolution displays Always Display scroll bars at all times However they are disabled if the corresponding axis is full scale 507 Chapter 17 Analyzing waveforms 508 Sizing digital plots Sizing bars can be used to change the digital plot size instead of choosing Digital Size from the Plot menu The digital trace name sizing bar is at the left vertical boundary of the digital plot If an analog plot area is displayed simultaneously with the digital plot there is an additional plot sizing bar at the bottom horizontal boundary of the digital plot To set
365. obe Window tab in the Simulation Settings dialog box Simulation Settings Parametric x General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window M Display Probe window during simulation after simulation has completed Show All markers on open schematics C Last plot The display settings in the Probe Window tab are explained in the following table You do not need to exit PSpice if you are finished examining the simulation results for one circuit and want to begin a new simulation from within Capture However PSpice A D unloads the old waveform data file for a circuit each time that you run a new simulation of the circuit After the simulation is complete the new or updated waveform data file is loaded for viewing 483 Chapter 17 Analyzing waveforms If you open a new Probe window from the Window menu choose New Window while monitoring the data the new window also starts in monitor mode because it is associated with the same waveform data file 484 Table 21 This setting Enables this type of waveform display Display Probe Waveforms are displayed only when a window when profile is opened Display Probe window during simulation Display Probe window after simulation has completed Show all markers on open schematics Show last plot DAT file is opened from within PSpice A D Waveforms are displayed
366. odelnam Because the value of R1 is defined as went Carowost caso MA Rval the analysis is run for each value of EETA ne E i R1 as it logarithmically increases from Save Bias Point Sweep ype OLoad Bias Poin h tart 1002 to 10 ka in 20 steps resulting in a R Linear B total of 21 runs C Logarithmic Decade SEA Increment fi 0 C Value list Cancel Apply Help Figure 23 Parametric simulation settings 6 Click OK gt 7 From the PSpice menu choose Run to start the analysis 84 Parametric analysis Analyzing waveform families Continuing from the example above there are 21 analysis runs each with a different value of R1 After PSpice A D completes the simulation the Available Sections dialog box appears listing all 21 runs and the Rval parameter value for each You can select one or more runs to display To display all 21 traces 1 Inthe Available Sections dialog box click OK To select individual runs click each one separately All 21 traces the entire family of curves for VDB Out appear in the Probe window as shown in Figure 24 To see more information about the section that produced a specific trace double click the corresponding symbol in the legend below the x axis PBB 4 522 sos e ta sae poe cate c scat age tee e ee Ses esdape sen ces S acc ce pe cceescs asset gene sss eS ce
367. oes not support the following subcircuit constructs e optional nodes construct OPTIONAL e variable parameters construct PARAMS e local PARAM command e local FUNC command To refine the subcircuit definition for these constructs use the Model Text view in Model Editor described in Editing model text on page 4 152 135 Chapter 4 Creating and editing models To find out more see Running the Model Editor alone on page 4 141 To find out more see Running the Model Editor alone on page 4 141 To find out more see Running the Model Editor from the schematic page editor on page 4 143 To find out more see Running the Model Editor alone on page 4 141 136 Ways to use the Model Editor You can use the Model Editor five ways To define a new model and then automatically create a part Any new models and parts are automatically available to any design To define a new model only no part You can optionally turn off the part creation feature for new models The model definition is available to any design for example by changing the model implementation for a part instance To edit a model definition for a part instance on your schematic This means you need to start the Model Editor from the schematic page editor after selecting a part instance on your schematic The schematic editor automatically attaches the new model implementation that the Model Editor creates to the selected pa
368. of the I O model parameters DRVL DRVH and OUTLD to the interface subcircuit s DRVL DRVH and CAPACITANCE parameters when itis called The library file DIG_IO LIB contains the 1 O models and interface subcircuits for all logic families supported in the model libraries You should refer to this file for examples of the I O models interface subcircuits and the proper use of N and O devices 267 Chapter 7 Digital device modeling The DOUTPUT model parameters are described under O devices in the online OrCA D PSpice A D Reference Manual 268 Shown below are the I O model and AtoD interface subcircuit definition used by the primitives describing the 74393 part model IO _STD uio drvh 96 4 drvl 104 AtoDl AtoD_STD AtoD2 AtoD_STD_NX AtoD3 AtoD_STD AtoD4 AtoD_STD_NX DtoAl DtoA_STD DtoA2 DtoA_STD DtoA3 DtoA_STD DtoA4 DtoA_STD tswhll 1 373ns tswlhl 3 382ns tswhl2 1 346ns tswlh2 3 424ns tswhl3 1 5lins tswlh3 3 517ns tswhl4 1 487ns tswlh4 3 564ns subckt AtoD_STD A D DPWR DGND params CAPACITANCE 0 00 A DGND D074 DGTLNET D I0_STD C1 A 0 CAPACITANCE 0 1pF ends If an instance of the 74393 part is connected to an analog part via node AD_NODE PSpice A D generates an interface block using the I O model specified by the digital primitive actually at the interface Suppose that U1 is the primitive connected at AD_NODE see the 74393 subcircuit definition on page
369. ollows e Digital net values are specified by lt digital net gt display name as opposed to the lt digital net gt format used for analyses With this format the digital signal can be displayed on the digital plot with an optional alias e The output from several digital nets can be collected into a single output of higher radix known as a bus A bus is formed by enclosing a list of digital net names separated by blanks or commas within braces according to the format lt high order net gt mid order net lt low order net gt The elements of the bus definition taken left to right specify the output values of the bus from high order to low order By definition a digital signal is any digital net value or a logical expression involving digital nets For the digital output variable formats described earlier you can use a digital signal expression everywhere a net name is expected You can also form buses into expressions using both logical and arithmetic operators As a result the generalized form for defining a digital trace is lt digital trace expression gt display name radix Table 14 This placeholder Means this digital trace expression of digital buses or digital expression signals display name name that will be displayed on the screen if no display name is specified the actual trace expression is used if a display name is given it is available for use in subsequent trace defin
370. olors Mouse actions for cursor control Key combinations for cursor control Output variable formats Examples of output variable formats Output variable AC suffixes Device names for two terminal device types Terminal IDs by three amp four terminal device type Noise types by device type Analog arithmetic functions for trace expressions Output units for trace expressions Digital logical and arithmetic operators Signal constants for digital trace expressions Tables 423 424 432 433 433 438 439 440 446 450 451 451 481 482 484 486 488 489 507 514 514 520 521 521 523 524 524 525 526 528 529 531 531 532 532 535 536 538 XXV Tables xxvi Before you begin Welcome to OrCAD OrCAD offers a total solution for your core design tasks schematic and VHDL based design entry FPGA and CPLD design synthesis digital analog and mixed signal simulation and printed circuit board layout What s more OrCAD s products are a suite of applications built around an engineer s design flow not just a collection of independently developed point tools PSpice A D is just one element in OrCAD s total solution design flow With OrCAD s products you ll spend less time dealing with the details of tool integration devising workarounds and manually entering data to keep files in sync Our products will help you
371. on is finished the window changes to manual mode To see the full set of runs you must update the display by using the Add Trace command under the Trace menu Configuring update intervals You can define the frequency at which PSpice updates the waveform display as follows e At fixed time intervals every n sec e According to the percentage of simulation completed every n where n is user defined The default setting Auto updates traces each time PSpice gets new data from a simulation To change the update interval 1 From the Tools menu choose Options 2 Inthe Auto Update Interval frame choose the interval type sec or then type the interval in the text box Interacting with waveform analysis during simulation The functions that change the x axis domain that set a new x axis variable can not be accessed while the simulation is running If you have enabled the display of Viewing waveforms During a multi run simulation such as Monte Carlo parametric or temperature PSpice displays only the data for the most recent run in the Probe window E or press insert For more information see Using schematic page markers to add traces on page 17 487 485 Chapter 17 Analyzing waveforms 486 waveforms during simulation and wish to reconfigure the x axis settings as explained below you must wait until the simulation run has finished The following table shows how to enable the functions th
372. on text box Click OK to plot the traces The plot displays a digital area above the analog area as shown in Figure 121 below Mixed analog digital tutorial press Ctrl Y Note that the V 1 label at the bottom of the plot is preceded by a boxed 1 This indicates that the far left y axis applies to the V 1 waveform You can add up to 75 digital traces to the digital portion of the plot If you add more traces than can be displayed PSpice A D scrolls the traces upwards so you can see the last trace added A character in front of the highest or lowest trace name indicates that there are more traces above or below the marked traces 503 Chapter 17 Analyzing waveforms RESET I OUT 5 84 9 5 84 Time Figure 121 Mixed analog digital oscillator results 504 User interface features for waveform analysis PSpice A D provides direct manipulation techniques and shortcuts for analyzing waveform data These techniques are described below Zoom regions PSpice provides a direct manipulation method for marking the zoom region in either the digital or the analog area of the plot To zoom in or out 1 Do one of the following on the toolbar e Click the View In toolbar button to zoom in by a factor of 2 around the point you specify e Click the View Out toolbar button to zoom out by a factor of 2 around the point you specify To zoom in the digital are
373. onnect a voltage or current source with an AC input signal Set up the AC sweep simulation specifications Set up the noise simulation specifications and enable the analysis in the AC Sweep Noise portion of the Simulation Settings dialog box Click OK to save the simulation profile From the PSpice menu choose Run to start the simulation Noise analysis To find out how see Setting up an AC stimulus on page 10 325 To find out how see Setting up an AC analysis on page 10 327 To find out how see Setting up a noise analysis on page 10 335 333 Chapter 10 AC analyses Example Diodes have separate noise contributions from thermal shot and flicker noise 334 What is noise analysis When running a noise analysis PSpice A D calculates and reports the following for each frequency specified for the AC Sweep Noise analysis e Device noise which is the noise contribution propagated to the specified output net from every resistor and semiconductor device in the circuit for semiconductor devices the device noise is also broken down into constituent noise contributions where applicable e Total output and equivalent input noise Table 7 This value Means this Output noise RMS sum of all the device contributions propagated to a specified output net Input noise equivalent noise that would be needed at the input source to generate the calculated output noise in an ideal noiseless circuit How
374. ontent above these limits Frequengy tables For frequency response tables the maximum frequency is twice the highest value It will be reduced to 10 RELTOL TSTOP or 8192 times the frequency resolution if either value is smaller The frequency resolution for frequency response tables is taken to be either the smallest frequency increment in the table or the fastest rate of phase change whichever is least PSpice A D then checks to see if it can be loosened without inducing sampling errors 237 Chapter 6 Analog behavioral modeling 238 Trading off computer resources for accuracy There is a significant trade off between accuracy and computation time for parts modeled in the frequency domain The amount of computer time and memory scale approximately inversely to RELTOL Therefore if you can use RELTOL 01 instead of the default 001 you will be ahead However this will not adversely affect the impulse response You may also wish to vary TMAX and TSTOP since these also come into play Since the trade off issues are fairly complex it is advisable to first simulate a small test circuit containing only the frequency domain device and then after proper validation proceed to incorporate it in your larger design The PSpice A D defaults will be appropriate most of the time if accuracy is your main concern but it is still worth checking Note Do not set RELTOL to a value above 0 01 This can seriously compromise the accuracy
375. or and inductor MODEL yes yes support ideal non ideal lossy transmission lines all ideal coupled inductors yes yes coupled transmission lines yes no nonlinear magnetics yes no voltage and current controlled switches yes yes analog model library 10 200 10 200 Notable PSpice devices and library models continued digital primitives digital model library all 1600 most 1600 xxxiii Before you begin PSpice A D PSpice A D Feature standard Basics Purchase options OrCAD Layout yes yes OrCAD PSpice Optimizer yes no Device Equations yes no network licensing yes no Miscellaneous specifications unlimited circuit size yes yes PSpice A D Basics package includes all libraries except IGBTS SCRs thyristors PWMs magnetic cores and transmission lines PSpice A D Basics does not include bidirectional transfer gates xxxiv If you don t have the standard PSpice A D package If you have the demo CD ROM OrCAD demo CD ROM The OrCAD demo CD ROM has the following limitations for PSpice A D circuit simulation limited to circuits with up to 64 nodes 10 transistors two operational amplifiers or 65 digital primitive devices and 10 transmission lines ideal or non ideal with not more than 4 pairwise coupled lines device characterization using the Model Editor limited to diodes stimulus generation limited to sine waves analog and clocks digital sample library of approximately
376. or digital input waveforms You can create a stimulus file either e manually using the Model Text View of the Model Editor or a standard text editor to create the definition a typical file extension is STM or e automatically using the Stimulus Editor which generates a STL file extension Indude file An include file is a user defined file that contains e PSpice commands or e supplemental text comments that you want to appear in the PSpice output file see page 1 54 You can create an include file using any text editor such as Notepad Typically include file names have a INC extension Configuring model library stimulus and indude files PSpice A D searches model libraries stimulus files and include files for any information it needs to complete the definition of a part or to run a simulation The files that PSpice A D searches depend on how you configure your model libraries and other files Much of the configuration is set up for you automatically however you can do the following yourself e Add and delete files from the configuration e Change the scope of a file that is whether the file applies to one design only local or to any design global e Change the search order Files needed for simulation Note Not all stimulus definitions require a stimulus file In some cases like DC and AC sources you must use a schematic symbol and set its attributes See What is the Stimulus Editor on p
377. or each value of the swept variable See Parametric analysis on page 2 82 for a description of how to set up a parametric analysis Parametric analysis 365 Chapter 12 Parametric and temperature analysis 366 RLC filter example This example shows how to perform a parametric sweep and analyze the results with performance analysis Use performance analysis to derive values from a series of simulator runs and plot these values versus a parameter that varies between the simulator runs For this example the derived values are the overshoot and the rise time versus the damping resistance of the filter Entering the design The schematic representation for the RLC filter RLCFILT OPJ is shown in Figure 70 PARAMETERS r 0 5 Figure 70 Passive filter schematic This series of PSpice A D runs varies the value of resistor R1 from 0 5 to 1 5 ohms in 0 1 ohm steps Since the time constant of the circuit is about one second perform a transient analysis of approximately 20 seconds Create the circuit in OrCAD Capture by placing a piecewise linear independent current source IPWL from SOURCE OLB Set the current source properties as follows AC 1a Tl Os I1 Oa T2 10ms I2 Oa T3 10 1ms I3 la Place an instance of a resistor and set its VALUE property to the expression R To define R as a global parameter place a PARAM pseudocomponent and use the Property Editor to create a new property R and s
378. order to solve the circuit equations PSpice A D uses an iterative algorithm For analog devices the equations are continuous and for digital devices the equations are Boolean If PSpice A D cannot get a self consistent result after a certain number of iterations the analog digital devices are forced to the X value and more iterations are done Since X as input to a digital component gives X as output the Boolean equations can always be solved this way If a digital node cannot be driven by known values during the DC iterations for instance the output of a flip flop with the clock line held low then its DC state will be X Depending on the circuit some none or all of the digital nodes may have the state X when the bias point is calculated DC Sweep The example circuit EXAMPLE OP is provided with the OrCAD program installation 309 Chapter9 DC analyses If you are planning to run an AC or transient analysis in addition to a DC analysis see the following e Using time based stimulus parts with AC and DC properties on page 3 118 for other source symbols that you can use e Using VSRC or ISRC parts on page 3 119 to find out how to specify the TRAN attribute for a time based input signal when using VSRC or ISRC symbols 310 Setting up a DC stimulus To run a DC sweep or small signal DC transfer analysis you need to place and connect one or more independent sources and then set the DC voltage or cur
379. orst case analysis is enabled Two runs are made using the two versions of the Rbmod MODEL statement shown in the circuit file The model parameter R is a multiplier which is used to scale the nominal value of any resistor referencing the Rbmod model Rb2 in this case The first MODEL statement leaves the nominal value of Rb2 at 720 ohms The sensitivity analysis increments R by a small amount and checks its effect on Vm OUT This slight increase in R causes an increase in the base bias voltage of the BJT and increases the amplifier s gain Vm OUT The worst case analysis correctly sets R to its minimum value for the lowest possible Vm OUT see Figure 89 Worst case analysis Note The YatX goal function is used on the simulation results for the parametric sweep STEP defined in Figure 87 The resulting curves are shown in Figure 89 and Figure 90 403 Chapter 13 Monte Carlo and sensitivity worst case analyses Consider a slightly different scenario Rb2 is set to 720 ohms so that maximizing it is not enough to saturate the BJT but Rb1 is variable also The true worst case occurs when Rb2 is maximized and Rb1 is minimized Checking their individual effects is not sufficent even if the circuit were simulated four times with each resistor in turn set to its extreme values Output is monotonic within the tolerance range Sensitivity analysis correctly points to the minimum value Output is non monotonic within
380. ossible without inducing sampling errors The maximum frequency has an initial upper bound of 1 RELTOL TMAX where TMAX is the transient analysis Step Ceiling value and RELTOL is the relative accuracy of all calculated voltages and currents If a Step Ceiling value is not specified 233 Chapter 6 Analog behavioral modeling Note TSTOP TMAX and TSTEP values are configured using Transient on the Setup menu The RELTOL property is set using Options on the Setup menu 234 PSpice A D uses the Transient Analysis Print Step TSTEP instead PSpice A D then attempts to reduce the maximum frequency by searching for the frequency at which the response has fallen to RELTOL times the maximum response For instance for the transform 1 1 s the maximum response 1 0 is at s j 0 DC The cutoff frequency used when RELTOL 001 is approximately 1000 27 159 Hz At 159 Hz the response is down to 001 down by 60 db Since some transforms do not have such a limit there is also a limit of 10 RELTOL times the frequency resolution or 10 RELTOL TSTOP For example consider the transform e79 001 s This is an ideal delay of 1 millisecond and has no frequency cutoff If TSTOP 10 milliseconds and RELTOL 001 then PSpice A D imposes a frequency cutoff of 10 MHz Since the time resolution is the inverse of the maximum frequency this is equivalent to saying that the delay cannot resolve changes in the input at a rate f
381. otting hysteresis curves 4 644545 646 6 wR KREWE DORR A 359 Fourier components co 4544 4 Raed ds ORE ERRE SR SR HSS 361 Chapter 12 Parametric and temperature analysis 363 Chapter overview 4 2 6 402485 42ee26 BS Ree Ene ee te Se 363 Parametric analysis 6464424 Gadee ease caw OS CORES H 364 Minimum requirements to run a parametric analysis 364 Overview of parametric analysis 000 365 REC filtet example aw skate eae eee she Pee ee mee a 366 Entering the design 44404 2i0 6 eos edeed wee ee eGo 366 Running the simulation ae ee ae ee ee ee ee SE 367 Using performance analysis to plot overshoot and rise time 367 Example frequency response vs arbitrary parameter 370 Setting up the circuit 6 bog ehh G CES AMER a oe 370 Temperature analysis s ee se 42k s 6nd wee EEE eee ee 373 Minimum requirements to run a temperature analysis 373 Overview of temperature analysis 04 374 Chapter 13 Monte Carlo and sensitivity worst case analyses 375 ChapterOvenvieW Ja s eas pasoi gne Oe OE ee eee ee ee 375 Statistical analyses 2g ee ho Gt ER a ee OES SERGE ES 376 Overview of statistical analyses 0 0 0 02000000 376 Output control for statistical analyses 4 377 Model parameter values reports ooo a 377 Waveform reports px Ge Ree RS OR RR 378 Collating functions 6 220046 5 2 Red ede SOR WWE BESS 379 Temperature considerations in statistical
382. ould be overly pessimistic see Figure 111 Eo no n lt TPLHMX TPLHMN Figure 111 Glitch suppression example two In the analysis of reconvergent fanout cases where common ambiguity is recognized it is possible that conflicting signal ambiguities may still overlap at the inputs to a primitive even after factoring out the commonality In such cases where the amount of overlap is less than the inertial delay of the device the prediction of a glitch is also suppressed by the simulator see Figure 112 U TPLHMN 40 O i 7 TPLHMX 60 p 55 90 EI 15 30 B TPLHMN 4 PLHMX 10 haan TPLHMN 10 TPLHMX 45 25 75 Figure 112 Glitch suppression example three U In this case factoring out the 15nsec common ambiguity still results in a 5nsec overlap of conflicting states The glitch is suppressed however because 5nsec is less than TPLHMX TPLHMN the computed inertial delay value of the AND gate 6nsec Methodology Combining component tolerances and the circuit design s functional response to a specific stimulus presents a challenge You must make sure that all the finished circuits will operate properly Well designed systems have a high degree of immunity from the effects of varying combinations of individual component tolerances Digital worst case timing simulation can help identify design problems depending upon the nature of the stimulus applied to the design You can
383. ound in explicitly specified the Copy to Clipboard Color Filter dialog TRACE 1 specifies the first color BRIGHTGREEN ae Window menu choose Copy used for trace display 0 Ulpboar TRACE 2 specifies the second BRIGHTRED color used for trace display TRACE 3 specifies the third color BRIGHTBLUE used for trace display TRACE 4 specifies the fourth BRIGHTYELLOW color used for trace display TRACE _5 specifies the fifth color BRIGHTMAGENTA used for trace display TRACE 6 specifies the sixth color BRIGHTCYAN used for trace display 481 Chapter 17 Analyzing waveforms For information on what the default available colors and color order are and how to change them see Editing display and print colors in the PSPICE INI file on page 17 480 Probe Options x p Use Symbols p Trace Color Scheme Mark Data Points C Auto Normal s a Displ luati C Never C Match Axis isplay Evaluation G Always f Sequential Per Asse Display Statistics C Unique By File r Use ScrollBars gt Auto C Never C Always r Auto Update Interval Auto C Every fi sec I Highlight Error States C Eveyjo z 10 Number of Histogram Divisions 5 Number of Cursor Digits PSpice A D saves the selected color scheme for future waveform analyses 482 Configuring trace color shemes In the Probe Options dialog box you can set options for how the available colors and the color order specified in the PSPICE INI fi
384. pagation delays 22 ai 4 52 lt 4 840 Rhee eee S54 428 Circuit wide propagation delays 428 Part instance propagation delays 428 Initializing flip flops 4234 44 bee 2 ee dee wwe ee EO 429 Starting the simulation s i4 4 eo eae ke REO ORY RAE SS 429 Analyzing results hc eR ORS ERED REE ES ERE ROR Ee G 430 Adding digital signals toa plot 34 5222425 see eee ew es 431 Adding buses toa waveform plot 205 433 Tracking timing violations and hazards 435 Persistent hazards 0 0 0 0 0000p ee 435 Simulation condition messages 000000 437 Output control options 42s hens ee aw ee ES 440 Severity IEVEIS enes 4 a Se tee ee eee Ka ee eA 440 Mixed analog digital simulation 443 Ghapter overview 4 5 s 64 mie sigon ak SEN Aled OW ee ORE 443 Interconnecting analog and digital parts 444 Interface subcircuit selection by PSpice A D 445 Level 1 interface ac ov4s 22 24 Me Gee SO eee eR oe Boers 446 Level 2 interface ecaa ce eB esae Oe ee ee Re SE 447 Setting the default A D interface 4 2c eae eM a ee eS 448 Specifying digital power supplies 0 2 00048 449 Default power supply selection by PSpice A D 449 Creating custom digital power supplies 450 Overriding CD4000 power supply voltage throughout a design 452 Creating a secondary CD4000 TTL or ECL power supply
385. parameter sets 129 subcircuits 129 157 digital models 271 global vs design 131 instance 143 154 159 160 organization 130 preparing for part creation 172 saving as design using the Model Editor 143 saving as local using the Model Editor 153 testing verifying Model Editor created 138 tools to create 133 ways to create edit 134 Monte Carlo analysis 289 381 collating functions 379 histograms 393 introduction 47 model parameter values reports 377 output control 377 tutorial 385 using the Model Editor 156 waveform reports 378 with temperature analysis 380 MOSFET 137 297 525 526 multiple y axes waveform analysis 368 502 N netlist failure to netlist 98 file NET 50 Newton Raphson requirements 548 nodes interface 444 NODESETn initial conditions parts 544 noise analysis 288 333 about 44 334 device noise 334 flicker noise 337 noise equations 337 setup 333 335 shot noise 337 568 thermal noise 337 total output and input noise 334 units of measure 338 viewing results 338 viewing simulation results 337 526 waveform analysis output variables 337 526 noise units 338 non causality 235 nonlinear magnetic core 137 nonlinear devices in AC sweep analysis 331 NOOUTMSG simulation option 440 NOPRBMSG simulation option 440 0 OFFTIME stimulus property digital 422 ONTIME stimulus property digital 422 opamp 137 operators in expressions 110 OPPV
386. part to select it From the Edit menu choose PSpice Stimulus This starts the Stimulus Editor and displays the New Stimulus dialog box You can see that the stimulus already has the name of Vfirst Select PWL in the dialog box and click OK The cursor looks like a pencil The message in the status bar at the bottom of the screen lets you know that you are in the process of adding new data points to the stimulus The 349 Chapter 11 Transient analysis This example creates a 10 k sine wave with the amplitude parameterized so that it can be swept during a simulation 350 left end of the bottom status bar displays the current coordinates of the cursor 9 Move the cursor to 200ns 1 and click the left mouse button This adds the point Notice that there is automatically a point at 0 0 Ignore it for now and continue to add a couple more points to the right of the current one 10 Click right to stop adding points 11 From the File menu choose Save If you make a mistake or want to make any changes reshape the trace by dragging any of the handles to a new location The dragged handle cannot pass any other defined data point To delete a point click its handle and press Del To add additional points either choose Add Point from the Edit menu press At JHA or click the Add Point toolbar button At this point you can return to Capture edit the current stimulus or go on to create another Example sine wave swe
387. path where the file resides or explicitly define the directory path in the configuration list If the file is not configured add it to the list and make sure To find out more about how to configure that it appears before any other library or file thathas an these files and about search order see identically named definition Configuring model libraries on page 4 162 To find out more about the default 1 Inthe Simulation Settings dialog box click the Include configuration see How are models Files tab organized on page 4 130 To view the configuration list If the directory path is not specified update the default library search path or change the file entry in the configuration list to include the full path specification To view the default library search path To find out more about the library search path see Changing the library search path on page 4 167 1 Inthe Simulation Settings dialog box click the Libraries tab Unmodeled pins If you see messages like these in the PSpice Simulation Output window Warning Part part_name pin pin_name is unmodeled Warning Less than 2 connections at node node_name or messages like this in the PSpice output file Floating unmodeled pin fixups then you may have drawn a wire to an unmodeled pin 123 Chapter 3 Preparing a design for simulation To find out more about searching for parts see Finding the part that you want on page 3 102 This applies to an
388. pice This example sets up DC sweep analysis parameters to sweep Vin from 10 to 15 volts in 1 volt increments Setting up and running a DC sweep analysis To set up and run a DC sweep analysis 1 In Capture from the PSpice menu choose New Simulation Profile The New Simulation dialog box appears In the Name text box type DC Sweep From the Inherit From list select Schematic1 Bias then click Create The Simulation Settings dialog box appears Click the Analysis tab From the Analysis type list select DC Sweep and enter the values shown in Figure 6 DC sweep analysis Simulation Settings Example Primary Sweep _ Secondary Sweep Monte CarloAworst Case Parametric Sweep Temperature Sweep Save Bias Point Load Bias Point Figure6 DC sweep analysis settings 6 Click OK to close the Simulation Settings dialog box 7 From the File menu choose Save 8 From the PSpice menu choose Run to run the analysis 67 Chapter 2 Simulation examples 68 press Insert press Ctri M Displaying DC analysis results Probe windows can appear during or after the simulation is finished Z SCHEMATIC1 DC Sweep OrCAD PSpice A D clipper SCHEMATIC1 DC Sweep dat Bi Fie Edt View Simulation Trace Plot Tools Window Help 18 x a gt S ren Eea 4 fsouwancrocsnees y u 8 3 amp h OM Fer 96 FS KEE ot Sh a E 2 100 5u ou SU 10u 15u
389. pplied to the AND gate D Figure 102 Timing hazard example The state of the output does not and should not change since at no time do both input states qualify the gate and the arrival times of the transitions are known Convergence hazard In cases where there are ambiguities associated with the signal transitions 0 R 1 and 1 F O which have a certain amount of overlap it is no longer certain which of the transitions happens first The output could pulse 0 1 0 at some point because the input states may qualify the gate On the other hand the output could remain stable at the 0 state This is called a convergence hazard because the reason for the glitch occurrence is the convergence of the conflicting ambiguities at two primitive inputs Gate primitives including LOGICEXP primitives that are presented with simultaneous opposing R and F levels may produce a pulse of the form 0 R 0 or 1 F 1 Identification of timing hazards For example a two input AND gate with the inputs shown in Figure 103 below produces the output shown sr ee ee Figure 103 Convergence hazard example This output 0 R 0 should be interpreted as a possible Note that other types of primitives such as single pulse no longer than the duration of the R level The flip flops may produce an X instead of an actual device s output may or may not change depending _R 0 or F 1 in response to a convergence on the transition times of
390. predefined for use with noise AC sweep analysis 298 Lp Starting a simulation Starting a simulation After you have used Capture to enter your circuit design and have set up the analyses to be performed you can start a simulation by choosing Run from the PSpice menu When you enter and set up your circuit this way Capture automatically generates the simulation files and starts PSpice A D There may be situations however when you want to run PSpice A D outside of Capture You may want to simulate a circuit that was not created in Capture for example or you may want to run simulations of multiple circuits in batch mode This section includes the following Starting a simulation from Capture below Starting a simulation outside of Capture on page 8 300 Setting up batch simulations on page 8 300 The PSpice A D simulation window on page 8 301 Starting a simulation from Capture After you have set up the analyses for the circuit you can start a simulation from Capture in either of the following ways From the PSpice menu select Run Click the Simulate button on the PSpice toolbar 299 Chapter 8 Setting up analyses and starting simulation 300 Starting a simulation outside of Capture To start PSpice A D outside of Capture 1 From the Start menu point to the OrCAD program group then choose PSpice A D 2 From the File menu choose Open Simulation 3 Do one of the following e Double click on th
391. profile and click OK The Simulation Settings dialog box appears 3 Choose AC Sweep Noise in the Analysis type list box 4 Specify the required parameters for the AC sweep or noise analysis you want to run Click OK to save the simulation profile 6 From the PSpice menu select Run to start the simulation What is AC sweep AC sweep is a frequency response analysis PSpice A D calculates the small signal response of the circuit to a combination of inputs by transforming it around the bias point and treating it as a linear circuit Here are a few things to note e Nonlinear devices such as voltage or current controlled switches are transformed to linear circuits about their bias point value before PSpice A D runs the linear small signal analysis e Digital devices hold the states that PSpice A D calculated when solving for the bias point e Because AC sweep analysis is a linear analysis it only considers the gain and phase response of the circuit it does not limit voltages or currents The best way to use AC sweep analysis is to set the source magnitude to one This way the measured output equals the gain relative to the input source at that output Setting up an AC stimulus To run an AC sweep analysis you need to place and connect one or more independent sources and then set the AC magnitude and phase for each source To set up an AC stimulus 1 Place and connect one of these symbols in your schematic
392. ps are obtained by second order polynomial interpolation from values at the internal steps When simulating mixed analog digital circuits there are actually two time steps one analog and one digital This is necessary for efficiency Since the analog and digital circuitry usually have very different time constants any attempt to lock them together would greatly slow down the simulation The time step shown on the PSpice A D display during a transient analysis is that of the analog section Switching circuits in transient analyses Running transient analysis on switching circuits can lead to long run times PSpice A D must keep the internal time step short compared to the switching period but the circuit s response extends over many switching cycles One method of avoiding this problem is to transform the switching circuit into an equivalent circuit without switching The equivalent circuit represents a sort of quasi steady state of the actual circuit and can correctly model the actual circuit s response as long as the inputs do not change too fast Plotting hysteresis curves Transient analysis can be used to look at a circuit s hysteresis Consider for instance the circuit shown in Figure 67 netlist in Figure 68 Figure 67 ECL compatible Schmitt trigger Switching circuits in transient analyses This technique is described in V Bello Computer Program Adds SPICE to
393. put sin of the input where the input is in radians cos of the input where the input is in radians tan of the input where the input is in radians tan of the input where the output is in radians Math function parts are based on the PSpice A D E device type Each provides one or more inputs and a mathematical function which is applied to the input The result is output on the output net 213 Chapter 6 Analog behavioral modeling 214 ABM expression parts The expression parts are shown in Table 2 These parts can be customized to perform a variety of functions depending on your requirements Each of these parts has a set of four expression building block properties of the form EXPn where n 1 2 3 or 4 During netlist generation the complete expression is formed by concatenating the building block expressions in numeric order thus defining the transfer function Hence the first expression fragment should be assigned to the EXP1 property the second fragment to EXP2 and so on Expression properties can be defined using a combination of arithmetic operators and input designators You may use any of the standard PSpice A D arithmetic operators see Table 9 on page 3 110 within an expression statement You may also use the EXPn properties as variables to represent nets or constants Table2 ABM expression parts Part Inputs Output ABM none V ABM1 1 V ABM2 2 V ABM3 3 V ABM I none
394. put and output pins respectively VALUE is the keyword specifying the type of ABM device and the expression inside the curly braces defines the logarithm of the input voltage Several ABM parts produce more than one primitive PSpice A D device per part instance In this case the PSPICETEMPLATE property may be quite complicated An example is the DIFFER differentiator part This is implemented as a capacitor in series with a current sensor together with an E device which outputs a voltage proportional to the current through the capacitor The template has several unusual features it gives rise to three primitives in the PSpice A D netlist and it creates a local node for the connection of the capacitor and its current sensing V device C REFDES in U REFDES 1 n V REFDES U REFDES 0 Ov n E REFDES Sout 0 VALUE GAIN I V REFDES The fragments C REFDES V REFDES and E REFDES create a uniquely named capacitor current sensing V device and E device respectively The fragment U REFDES creates a name suitable for use as a local node The E device generates an output proportional to the current through the local V device Control system parts Control system parts have single pin inputs and outputs The reference for input and output voltages is analog ground 0 An enhancement to PSpice A D means these components can be connected together with no need for dummy load or input resistors Table 9 lists the co
395. r circuit can be divided into two categories e those whose transient behavior is characterized Note The Stimulus Editor is Basics eae AW graphically using the Stimulus Editor not included in PSpice A D ee f e those whose transient behavior is characterized by manually defining their properties within Capture Their symbols are summarized in Table 10 Table 10 Stimulus symbols for time based input signals Specified by Symbol name Description Using the Stimulus Editor VSTIM ISTIM DIGSTIM1 DIGSTIM2 DIGSTIM4 DIGSTIM8 DIGSTIM16 DIGSTIM32 voltage source current source digital stimuli Defining symbol attribute VSRC VEXP VPULSE VPWL VPWL_RE_FOREVER VPWL_F_RE_FOREVER VPWL_N_TIMES VPWL_F_N_TIMES VSFFM VSIN voltage sources 344 Table 10 Stimulus symbols for time based input signals Specified by Symbol name Description ISRC current sources IEXP IPULSE IPWL IPWL_RE_FOREVER IPWL_F_RE FOREVER IPWL_N_TIMES IPWL_F_N_TIMES ISFFM ISIN DIGCLOCK STIM1 STIM4 STIM8 STIM16 FILESTIM1 FILESTIM2 FILESTIM4 FILESTIM8 FILESTIM16 FILESTIM32 digital clock signal digital stimuli digital file stimuli To use any of these source types you must place the symbol in your schematic and then define its transient behavior Each property characterized stimulus has a distinct set of attributes depending upon the kind of transient behavior it rep
396. r example you may want to create a voltage divider rather than a multiplier This is illustrated in the following example Example 2 Consider the device in Figure 52 224 PSpice A D equivalent parts Gratio H2 AT div G REFDES OUT SOQUT VALU Figure 52 GMULT part example With this device the output is a current is equal to the ratio of the voltages at input pins 1 and input pins 2 If V IN2 IN2 0 the output depends upon V IN1 IN1 as follows if V IN1 IN1 0 output 0 if V IN1 IN1 gt 0 output MAXREAL if V IN1 IN1 lt 0 output MAXREAL where MAXREAL is a PSpice A D internal constant representing a very large number on the order of 1e30 In general the result of evaluating an expression is limited to MAXREAL Note that the output of the part can also be used as part of the controlling function PESIN T S6IN1 JAVE6IN2 96IN2 To create this device you would first make a new part GDIV based on the GMULT part Edit the GDIV template to divide the two input values rather than multiply them Lookup tables ETABLE and GTABLE The ETABLE and GTABLE parts use a transfer function described by a table These device models are well suited for use with measured data The ETABLE and GTABLE parts are defined in part by the following properties default values are shown ETABLE TABLE 15 15 15 15 EXPR V IN IN GTABLE 225
397. r other analysis types is about 2 5 times smaller For long runs especially transient runs this can generate waveform data files that are several megabytes in size Even if this does not cause a problem with disk space large waveform data files take longer to read in and take longer to display traces on the screen You can limit waveform data file size by e placing markers on your schematic before simulation and having PSpice A D restrict the saved data to these markers only e excluding data for internal subcircuits e suppressing simulation output Limiting file size using markers One reason that waveform data files are large is that by default PSpice A D stores all net voltages and device currents for each step for example time or frequency points However if you have placed markers on your schematic prior to simulation PSpice A D saves only the results for the marked wires and pins Viewing waveforms To limit file size using markers 1 From Capture s PSpice menu choose Edit Simulation Settings to display the Simulation Settings dialog box Simulation Settings Parametric x General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window r Schematic Circuit Data C All voltages currents and digital states All but internal subcircuit data T Save data in the CSDF format CSD Cancel Apply Help 2 Click the Data Collection tab 3 In the Schematic Circ
398. r the equivalent control system part example using the LAPLACE part see Figure 41 on page 6 211 For transient analysis the output is the convolution of the input waveform with the impulse response of 1 1 001 s The impulse response is a decaying exponential with a time constant of 1 millisecond This means that the output is the lossy integral of the input where the loss has a time constant of 1 millisecond This will produce a PSpice A D netlist declaration similar to ERC 5 0 LAPLACE V 10 1 1 001 s Frequency response tables EFREQ and GFREQ The EFREQ and GFREQ parts are described by a table of frequency responses in either the magnitude phase domain or complex number domain The entire table is read in and converted to magnitude in dB and phase in degrees Interpolation is performed between entries Phase is interpolated linearly magnitude is interpolated logarithmically For frequencies outside the table s range 0 zero magnitude is used PSpice A D equivalent parts 229 Chapter 6 Analog behavioral modeling 230 EFREQ and GFREQ properties are defined as follows EXPR value used for table lookup defaults to V IN IN if left blank TABLE series of either input frequency magnitude phase triplets or input frequency real part imaginary part triplets describing a complex value defaults to 0 0 0 1Meg 10 90 if left blank DELAY group delay increment defaults to 0 if le
399. r the whole device model With this method all other functional primitives operate in zero delay Refer to the online OrCA D PS pice A D Reference Manual for a n addition to explicit propagation delays other factors detailed discussion on these two primitives such as output loads can affect the total propagation delay through a device Timing model With the exception of the PULLUP PULLDN and PINDLY devices all digital primitives have a Timing model which provides timing parameters to the simulator The Timing model for each primitive type is unique That is the model name and the parameters that can be defined for that model vary with the primitive type Within a Timing model there may be one or more types of parameters e Propagation delays TP e Setup times TSU e Hold times TH e Pulse widths TW e Switching times TSW 251 Chapter 7 Digital device modeling For a description of Timing model parameters see the specific primitive type under U devices in the online OrCA D PSpice A D Reference Manual Note This discussion applies only to propagation delay parameters TP All other timing parameters such as setup hold times and pulse widths are handled differently and are discussed in the following section 252 Each parameter is further divided into three values minimum MN typical TY and maximum MX For example the typical low to high propagation delay on a gate is specified as th
400. rameters This means PSpice A D nonrandomly varies device model parameters for which you have defined a tolerance one at a time for each device and runs a simulation with each change 2 Sets all model parameters for all devices to their worst case values assumed to be at one of the tolerance limits and runs a final simulation 47 Chapter 1 Things you need to know Analyzing waveforms with PSpice A D What is waveform analysis After completing the simulation PSpice A D plots the waveform results so you can visualize the circuit s Taken together simulation and waveform behavior and determine the validity of your design analysis is an iterative process After analyzing simulation results you can refine your design and simulation settings and then perform a new simulation and waveform analysis Perform post simulation analysis of the results This means you can plot additional information derived from the waveforms What you can plot depends on the types of analyses you run Bode plots phase margin derivatives for small signal characteristics waveform families and histograms are only a few of the possibilities You can also plot other waveform characteristics such as rise time versus temperature or percent overshoot versus component value v Pinpoint design errors in digital draits When PSpice A D detects setup and hold violations race conditions or timing hazards a detailed messag
401. rameters during the simulation 388 Using resistors with models To explore the effects of manufacturing tolerances on the behavior of this circuit you set device DEV and LOT tolerances on the model parameters for resistors R1 R2 R3 and R4 in a later step see page 13 389 This means you need to use resistor parts that have model associations Because R parts do not have associated models and therefore no model parameters change the resistor parts to Rbreak parts that do have models To replace R1 R2 R3 and R4 with the RBREAK part 1 Click R1 to select it 2 Hold down the key and click R2 R3 and R4 to add them to the selection set 3 Press to delete the selection set 4 From the Place menu choose Part 5 Type RBREAK in the Part text box If RBREAK is not available click the Add Library button and select BREAKOUT OLB to configure it for use in Capture 6 Click OK 7 Manually place the RBREAK part in the circuit diagram where R1 R2 R3 and R4 were located 8 Double click on each RBREAK part and change the reference designators as desired Saving the design Before editing the models for the Rbreak resistors save the schematic To save the design 1 From Capture s File menu choose Save Defining tolerances for the resistor models This section shows how to assign device DEV and lot LOT tolerances to the model parameters for resistors R1 R2 R3 and R4 using the model editor To as
402. rary that contains it to have 1 From the Simulation menu choose Edit Simulation atone ka Settings then click the Libraries tab For more information see Global vs i design models and libraries on 2 Select the model library that you want to change nage 4 131 3 Do one of the following e Click the Add as Global button to add a global entry e Click the Add to Design button to add a design entry 4 Click the Delete toolbar button to remove the local entry 165 Chapter 4 Creating and editing models See Handling duplicate model names on page 4 164 for more information Caution Donotedit NOM LIB If you do PSpice will recreate the indexes for every model library referenced in NOM LIB This can take some time 166 Changing model library search order Two reasons why you might want to change the search order are to e reduce the search time e avoid using the wrong model when there are model names duplicated across libraries PSpice A D always uses the first instance To change the order of libraries 1 On the Libraries tab of the Simulation Settings dialog box a Select the library name you wish to move b Use either the Up Arrow or Down Arrow toolbar button to move the library name to a different place in the list 2 If you have listed multiple LIB commands within a single library like NOM LIB then edit the library using a text editor to change the order Example The model libraries DIODES LI
403. re plot will be a digital area 477 Chapter 17 Analyzing waveforms From the View menu choose Toolbar to display orhide the toolbar 478 Elements of a Probe window A Probe window is a separately managed waveform display area A Probe window can include multiple analog and digital plots Figure 114 shows two plots displayed together Because a Probe window is a window object you can minimize and maximize windows or move and scale the windows within the PSpice A D workspace A toolbar can be displayed in the Probe window and applies to the active Probe window E window A window B active Figure 114 Two Probe windows You can display information from one or more waveform data files in one Probe window After the first file is loaded load other files into the same Probe window by appending them in PSpice A D Overview of waveform analysis Managing multiple Probe windows You can open any number of Probe windows Each Probe window is a tab on the worksheet displayed in the middle of the workspace The same waveform data file can be displayed in more than one Probe window You can tile the windows to compare data Only one Probe window is active at any given time identified by a highlighted title bar or a topmost tab Menu keyboard and mouse operations affect only the active Probe window You can switch to another Probe window by clicking another tab or title bar Printing multiple w
404. reating and editing models For specific information on changing model references see Changing the model reference to_an existing model definition on page 4 159 You do not need to enter an Implementation Path because PSpice searches for the model in the list of model libraries you configure for this project 180 Attaching models to parts If you create parts and want to simulate them you need to attach model implementations to them If you created your parts using any of the methods discussed in this chapter then your part will have a model implementation already attached to it MODEL The Implementation property defines the name of the model that PSpice must use for simulation When attaching this implementation this rule applies e The Implementation name should match the name of the MODEL or SSUBCKT definition of the simulation model as it appears in the model library LIB Example If your design includes a 2N2222 bipolar transistor with a MODEL name of Q2N2222 then the Implementation name for that part should be Q2N2222 Note Make sure that the model library containing the definition for the attached model is configured in the list of libraries for your project See Configuring model libraries on page 4 162 for more information To attach a model implementation 1 Inthe schematic page editor double click a part to display the Parts spreadsheet of the Property Editor 2 From the Implementation list sel
405. rent level for each source To set up a DC stimulus 1 Place and connect one of these symbols in your schematic Table 12 For voltage input Use this When you are running VDC A DC Sweep and or Bias Point transfer function analysis only VSRC Multiple analysis types including DC Sweep and or Bias Point transfer function Table 13 For current input Use this When you are running IDC A DC Sweep and or Bias Point transfer function analysis only ISRC Multiple analysis types including DC Sweep and or Bias Point transfer function 2 Double click the symbol instance to display the Parts spreadsheet appears 3 Click in the cell under the DC column to edit its value 4 Define the DC specification as follows Table 14 Set this attribute To this value DC DC _level where DC_level is in volts or amps units are optional 5 Click OK twice to exit the dialog boxes Nested DC sweeps A second sweep variable can be selected after a primary sweep value has been specified in the DC Sweep dialog box When you specify a secondary sweep variable it forms the outer loop for the analysis That is for every increment of the second sweep variable the first sweep variable is stepped through its entire range of values Simulation Settings Example DC Nested Sweep ix General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window
406. resents For VPWL_F_xxx IPWL_F_xxx and FSTIM a separate file contains the stimulus specification As an alternative the Stimulus Editor utility automates the process of defining the transient behavior of stimulus devices The Stimulus Editor allows you to create analog stimuli which generate sine wave repeating pulse exponential pulse single frequency FM and piecewise linear waveforms It also facilitates creating digital stimuli with complex timing relations This applies to both stimulus symbols placed in your schematic as well as new ones that you might create Defining a time based stimulus For information on digital stimuli characterized by property see Chapter 14 Digital simulation 345 Chapter 11 Transient analysis Note The Stimulus Editor is not included in PSpice A D wy Basics OrCAD program versions without the Stimulus Editor must use the characterized by property sources listed in Table 10 on page 11 344 346 The stimulus specification created using the Stimulus Editor is saved to a file automatically configured into the schematic and associated with the corresponding VSTIM ISTIM or DIGSTIM part instance or symbol definition The Stimulus Editor utility The Stimulus Editor is a utility that allows you to quickly set up and verify the input waveforms for a transient analysis You can create and edit voltage sources current sources and digital stimuli for your circuit Menu prompts guide
407. response These rules follow the standard method of using Fourier transforms We recommend looking at one or more of the references cited in Frequency domain device models on page 6 227 for more information Note The table s frequencies must be in order from lowest to highest Figure 53 shows an EFREQ device used as a low pass Lowpass filter The input to the frequency response is the voltage ie oe across the input pins The table describes a low pass filter ee with a response of 1 0 dB for frequencies below 5 y i eT kilohertz and a response of 001 60 dB for frequencies DELAY 0 above 6 kilohertz The output is a voltage across the l output pins Figure 53 EFREQ part example This part is defined by the following properties TABLE 0 0 0 5kHz 0 5760 6kHz 60 6912 DELAY RI MAGUNITS PHASEUNITS Since R_I MAGUNITS and PHASEUNITS are undefined each table entry is interpreted as containing frequency magnitude value in dB and phase values in degrees Delay defaults to 0 The phase lags linearly with frequency meaning that this table exhibits a constant time group delay The delay is necessary so that the impulse response is causal That is so that the impulse response does not have any significant components before time zero The constant group delay is calculated from the values for a given table entry as follows group delay phase 360 frequency For this example t
408. response to a direct current source Table 1 summarizes what PSpice A D calculates for each DC analysis type Analyses you can run with PSpice A D See Chapter 2 Simulation examples for introductory examples showing how to run each type of analysis See Part three Setting Up and Running Analyses for a more detailed discussion of each type of analysis and how to set it up Tablel DC analysis types For this DC analysis PSpice A D computes this DC sweep Bias point detail DC sensitivity Small signal DC transfer Steady state voltages currents and digital states when sweeping a source a model parameter or temperature over a range of values Bias point data in addition to what is automatically computed in any simulation Sensitivity of a net or part voltage as a function of bias point Small signal DC gain input resistance and output resistance as a function of bias point 43 Chapter 1 Things you need to know 44 AC sweep and noise These AC analyses evaluate circuit performance in response to a small signal alternating current source Table 2 summarizes what PSpice A D calculates for each AC analysis type Table2 AC analysis types For this AC analysis PSpice A D computes this AC sweep Small signal response of the circuit linearized around the bias point when sweeping one or more sources over a range of frequencies Outputs include voltages and curr
409. ressions on points where you want to see waveform results displayed page 17 519 for ways to add traces You can place markers within PSpice A D e Before simulation to limit results written to the waveform data file and automatically display those traces in PSpice e During or after simulation with PSpice A D running to automatically display traces in the active Probe window The color of the marker you place is the same as its corresponding waveform analysis trace If you change the color of the trace the color of the marker on the schematic page changes accordingly The Markers submenu also provides options for controlling the display of marked results in PSpice after initial marker placement and during or after simulation To place markers on a schematic page 1 From Capture s PSpice menu point to Markers then choose the marker type you want to place Some of the markers are from the Advanced submenu 487 Chapter 17 Analyzing waveforms B X The color of the marker is the same as its corresponding waveform analysis trace If you change the color of the trace the color of the marker changes accordingly 488 Table 23 Waveform Markers menu command Advanced submenu command voltage Voltage Level not required voltage Voltage Differential not required differential current Current Into Pin not required digital signal Voltage Level not required dB Advanced db Magnitude of Voltage db Magnitude of Curren
410. rimitives or constraint checker primitives These characteristics are described in this chapter with a running example demonstrating the use of gate level primitives Functional behavior Functional behavior A digital device model s functional behavior is defined by one or more interconnected digital primitives Typically a logic diagram in a data book can be implemented directly using the primitives provided by PSpice A D The table below provides a summary of the digital primitives Table2 Digital primitives summary Type Description Standard gates BUF buffer INV inverter AND AND gate NAND NAND gate OR OR gate NOR NOR gate XOR exclusive OR gate NXOR exclusive NOR gate BUFA buffer array INVA inverter array ANDA AND gate array NANDA NAND gate array ORA OR gate array NORA NOR gate array XORA exclusive OR gate array NXORA exclusive NOR gate array AO AND OR compound gate OA OR AND compound gate AOI AND NOR compound gate OA OR NAND compound gate 243 Chapter 7 Digital device modeling Table2 Digital primitives summary continued Type Description Tristate gates BUF3 buffer INV3 inverter AND3 AND gate NAND3 NAND gate OR3 OR gate NOR3 NOR gate XOR3 exclusive OR gate NXOR3 exclusive NOR gate BUF3A buffer array INV3A inverter array AND3A AND gate array NAND3A NAND gate array OR3A OR gate array NOR3A NOR gate array XOR3A exclusive OR gate array NXOR3A exclusive NOR gate
411. rived for each waveform in a related set of waveforms at least two data points are required to produce a trace Use Eval Goal Function from the Trace menu to evaluate a goal function on a single waveform and produce a single data point result amp The genrise and overshoot goal functions are contained in the file PSPICE PRB in the OrCAD directory 368 IE SCHEMATIC1 Parametric OrCAD PSpice A D _ rlcfilt SCHEMATIC1 Test dat Bi Eie Edt View Simdation Trace Plot Tools Window Help alaj l I SCHEMATICI Parametic p R IEDC AAEE R89 Oe SHB gH Y 4 58 oat i Os 1 L1 9 Bi ictit SCHEM Figure 71 Current of L1 when R1 is 1 5 ohms To run performance analysis 1 From the Trace menu choose Performance Analysis 2 Click OK PSpice resets the X axis variable for the graph to be the parameter that changed between PSpice A D runs In the example this is the R parameter To see the rise time for the current through the inductor L1 click the Add Trace toolbar button and then enter genrise I L1 Figure 72 shows how the rise time decreases as the damping resistance increases for the filter Another Y axis can be added to the plot for the overshoot of the current through L1 by selecting Add Y Axis from the Plot menu The Y axis is immediately added Now click the Add Trace toolbar button and enter overshoot I L1
412. rmance analysis plots of bandwidth and gain vs Reval Performance analysis Finding out more about performance analysis Table 2 4 To find out more about this See this how to use performance RLC filter example on analysis page 12 366 Example Monte Carlo analysis of a pressure sensor on page 13 385 how to use search PSpice A D online Help commands and create goal functions 91 Chapter 2 Simulation examples 92 Part two Design entry Part two provides information about how to enter circuit designs in OrCAD Capture that you want to simulate Chapter 3 Preparing a design for simulation outlines the things you need to do to successfully simulate your schematic including troubleshooting tips for the most frequently asked questions Chapter 4 Creating and editing models describes how to use the tools to create and edit model definitions and how to configure the models for use Chapter 5 Creating parts for models explains how to create symbols for existing or new model definitions so you can use the models when simulating from your schematic Chapter 6 Analog behavioral modeling describes how to model analog behavior mathematically or using table lookups Chapter 7 Digital device modeling explains the structure of digital subcircuits and how to create your own from primitives Preparing a design for simulation Chapter overview This chapter provides introductory in
413. rrent I is essentially zero for V lt 0 and almost infinite for V gt 0 Even if there are external components that limit the current the knee of the diode s I V curve is so sharp that it is almost a discontinuity Are the derivatives correct The device equations built into PSpice include the derivatives and these are correct Depending on the device the physical meaning of the derivatives is small signal conductance transconductance or gain Unrealistic model parameters can exceed the limit of 1e14 but it requires some effort The main thing to look at is the behavioral modeling expressions especially those having denominators Introduction Is the initial approximation close enough Newton Raphson is guaranteed to converge only if the analysis is started close to the answer Also there is no measurement that can tell how close is close enough PSpice gets around this by making heavy use of continuity Each analysis starts from a known solution and uses a variable step size to find the next solution If the next solution does not converge PSpice reduces the step size falls back and tries again Bias point The hardest part of the whole process is getting started that is finding the bias point PSpice first tries with the power supplies set to 100 A solution is not guaranteed but most of the time the PSpice algorithm finds one If not then the power supplies are cut back to almost zero They are cut to a leve
414. rt instance To examine or verify the electrical characteristics of a model without running PSpice A D This means you can use the Model Editor alone to e check characteristics of a model quickly given a set of model parameter values or e compare characteristic curves to data sheet information or measured data Model Editor supported device types Table 19 summarizes the device types supported in the Model Editor Table 19 Models supported in the Model Editor Uses this And this This part type definition form name prefix diode MODEL D bipolar transistor MODEL Q bipolar transistor SUBCKT X Darlington model IGBT MODEL Z JFET MODEL J power MOSFET MODEL M operational amplifier SSUBCKT X voltage comparator SUBCKT X nonlinear magnetic core MODEL K voltage regulator SUBCKT X voltage reference SUBCKT X This is the standard PSpice A D device letter notation Refer to the online OrCAD PSpice A D Reference Manual The Model Editor only supports SUBCKT models that were generated by the Model Editor However you can edit the text of a SUBCKT model created manually or by another tool using the Model Editor When you load a SSUBCKT model that the Model Editor did not create the Model Editor displays the text of the model for editing Using the Model Editor to edit models Device types that the Model Editor models using the MODEL statement are based on the models built into PSpice A D
415. rt or for a part instance on your schematic page using the Model Editor see Editing model text on page 4 152 From Capture s Edit menu choose Part to start the part editor Changing the model reference to an existing model definition 5 Create a new part for the subcircuit definition One way to do this is to use the part wizard See Chapter 5 Creating parts for models for a complete discussion Changing the model reference to an existing model definition Parts are linked to models by the model name assigned to the parts Implementation property You can change this assignment by replacing the Implementation property value with the name of a different model that already exists in the library You can do this for e Apart instance in your design e A part in the part library To change model references for part instances on your design 1 Find the name of the model that you want to use 2 Inthe schematic page editor select one or more parts on your schematic page 3 From the Edit menu choose Properties The Parts spreadsheet appears 4 Click the cell under the column Implementation Type 5 From the Implementation list select PSpice Model 6 Inthe Implementation column type the name of the existing model that you want to use if it is not already listed 7 Click Apply to update the changes then close the spreadsheet 159 Chapter 4 Creating and editing models For information on how to create instance
416. ry Sweep C Model REESI AG celtics _ Secondary Sweep c a eee eee Ly Monte Carlo Aworst Case Temperature STEM EU MBME Parametric Sweep Temperature Sweep p Sweep type Save Bias Point linear Start value 0 125 Load Bias Point Leaeithme I Brigez jars ogarithmic Decade Increment fo 005 C Value list Cancel Apply Help 1 In Capture select New Simulation Profile or Edit Simulation Settings from the PSpice menu If this is a new simulation enter the name of the profile and click OK The Simulation Settings dialog box appears 2 Under Analysis type select DC Sweep 3 For the Primary Sweep option enter the necessary parameter values and select the appropriate check boxes to complete the analysis specifications 4 Click OK to save the simulation profile 5 Select Run under the PSpice menu to start the simulation Note Do not specify a DC sweep and a parametric analysis for the same variable 307 Chapter9 DC analyses 308 Overview of DC sweep The DC sweep analysis causes a DC sweep to be performed on the circuit DC sweep allows you to sweep a source voltage or current a global parameter a model parameter or the temperature through a range of values The bias point of the circuit is calculated for each value of the sweep This is useful for finding the transfer function of an amplifier the high and low thresholds of a logic gate and so on For the DC sweep analysis specified in Fig
417. ry analog net has a DC path to ground Missing DC path to ground on page 3 125 The part template is correct Defining part properties needed for simulation on page 5 181 Hierarchical parts if used are properly The OrCA D Capture User s Guide defined Ports that connect to the same net have the The OrCAD Capture User s Guide same name 98 Checklist for simulation setup Things to check in your system configuration Table 6 Make sure that To find out more see this Y Y Path to the PSpice A D programs is correct Directory containing your design has write Your operating system manual permission Your system has sufficient free memory Your operating system manual and disk space 99 Chapter 3 Preparing a design for simulation The OrCAD part libraries also include special parts that you can use for simulation only These include stimulus parts to generate input signals to the circuit see Defining stimuli on page 3 116 ground parts required by all analog and mixed signal circuits which need reference to ground simulation control parts to do things like set bias values see Appendix A Setting initial state output control parts to do things like generate tables and line printer plots to the PSpice output file see Chapter 18 Other output options 100 Using parts that you can simulate The OrCAD part libraries supply numerous parts designed for simulatio
418. s the probability distribution type such as UNIFORM or GAUSS is ignored You can use analog behavioral models to measure waveform characteristics other than those detected by the available collating functions such as rise time or slope You can also use analog behavioral models to incorporate several voltages and currents into one output variable to which a collating function may be applied See Chapter 6 Analog behavioral modeling for more information This procedure saves time by performing the minimum number of simulations required to make an educated guess at the parameter values that produce the worst results It also has some limitations which are described in the following sections 399 Chapter 13 Monte Carlo and sensitivity worst case analyses 400 direction better or worse in which the collating function changes with a small increase in each model parameter is recorded Finally for the worst case run each parameter value is taken as far from its nominal as allowed by its tolerance in the direction which should cause the collating function to be its worst given by the HI or LO specification Outputs A summary of the sensitivity analysis is printed in the PSpice A D output file OUT This summary shows the percent change in the collating function corresponding to a small change in each model parameter If a PROBE statement is included in the circuit file then the results of the nominal and worst
419. s WIDTH MIN LOW x0 uval 80 000ns PERSISTENT On OUTPUT Port pt 80 000ns PERSISTENT On OUTPUT Port p16 z Sort B Minimum Severity Level Section WARNING Time C Type Close A Ee a Example If you select WARNING as the minimum severity level the Simulation Message Summary dialog box will display WARNING SERIOUS and FATAL messages 517 Chapter 17 Analyzing waveforms 518 To display waveforms associated with messages 1 Inthe Simulation Message Summary dialog box double click a message For most message conditions a Probe window appears that contains the waveforms associated with the simulation condition along with detailed message text Persistent hazards If a PERSISTENT HAZARD message is displayed two plots appear see Figure 123 containing the following e the waveforms that initially caused the timing violation or hazard lower plot e the primary outputs or internal state devices to which the condition has propagated upper plot NS OrCAD PSpice A D Msg1_d dat IB Fle Edt Vew Sinuiaion Trece Plt Tool Widow Hep la Ja e ts 2 el 2 4444 pu 88 aQ OiealKxe la ikra my tir Lr EAE eR p a a e P O S tt i bi ioi si i 40 ns 50 815 80 8ns 90 8ns 100 6ns 109 5ns me I a elockt t o SEL gt gt P 1 P 1 a 1 __ 11 __ Lo fai 16ns 12ns 16ns 26ns __ 24ns 28ns 32ns 36ns Tine m
420. s limited to MAXREAL This is modeled with an ABM2 I two input current output part like this one in Figure 46 This part is characterized by the following properties EXPL V ZIN2 V IN1 Note that output of GRATIO can be used as part of the controlling function This produces a PSpice A D netlist declaration like this GRATIO 2 3 VALUE V 13 V 2 Note Letting a current approach 1 30 will almost certainly cause convergence problems To avoid this use the limit function on the ratio to keep the current within reasonable limits Control system parts An instantaneous device example modeling a triode This section provides an example of using various ABM parts to model a triode vacuum tube The schematic of the triode subcircuit is shown in Figure 47 lt ame VENEEN Tr m DASWIN IINE a amde gt lt tathode GOES VEIN lt E Q able per 1 5 lt a ct a 1 cathode gt ande erode gt Ca apr c Rout Ce a E SPS Meg T pF ji gathod cathode gt Figure 47 Triode circuit Assumptions In its main operating region the triode s current is proportional to the 3 2 power of a linear combination of the grid and anode voltages ianode ko vg ky va For a typical triode kg 200e 6 and k4 0 12 Looking at the upper left hand portion of the schematic notice the
421. s point is not supported in PSpice A D ww Basics If the circuit uses high gain components or if the circuit s behavior is nonlinear around the bias point this feature is not useful See Setting up analyses on page 8 289 for a description of the Analysis Setup dialog box 542 Save and load bias point Save Bias Point and Load Bias Point are used to save and restore bias point calculations in successive PSpice A D simulations Saving and restoring bias point calculations can decrease simulation times when large circuits are run multiple times and can aid convergence Save Load Bias Point affect the following types of analyses e transient e DC e AC Save bias point Save bias point is a simulation control function that allows you to save the bias point data from one simulation for use as initial conditions in subsequent simulations Once bias point data is saved toa file you can use the load bias point function to use the data for another simulation To use save bias point 1 Inthe Simulation Settings dialog box click the Analysis tab 2 Under Options select Save Bias Point 3 Complete the Save Bias Point dialog box 4 Click OK Save and load bias point Load bias point Load bias point is a simulation control function that allows you to set the bias point as an initial condition A common reason for giving PSpice A D initial conditions is to select one out of two or more stable operating points set or r
422. s propagation delays in the case of logic devices as having tolerances These are expressed as either an operating range or as a spread around a typical operating point The designer then has some indication of how much deviation from typical one might expect for any of these particular component delay values Realizing that any two or more instances of a particular type of component may have propagation delay values anywhere within the published range designers are faced with the problem of ensuring that their products are fully functional when they are built with combinations of components having delay specifications that fall perhaps randomly anywhere within this range Historically this has been done by making simulation runs using minimum MIN typical TYP and maximum MAX delays and verifying that the product design is functional at these extremes But while this is useful to some extent it does not uncover circuit design problems that occur only with certain combinations of slow and fast parts True worst case simulation as provided by PSpice A D does just that Other tools called timing verifiers are sometimes used in the design process to identify problems that are indigenous to circuit definition They yield analyses that are inherently pattern independent and often pessimistic in that they tend to find more problems than will truly exist In fact they do not consider the actual usage of the circuit under an appl
423. sage type Severity level Meaning AMBIGUITY WARNING Convergence of conflicting rising and falling states timing CONVERGENCE ambiguities arrived at the inputs of a primitive and produced a pulse glitch on the output See Chapter 16 Digital worst case timing analysis for more information CUMULATIVE WARNING Signal ambiguities are additive increased by propagation through AMBIGUITY each level of logic in the circuit The ambiguities associated with both edges of a pulse increased to the point where they overlapped which PSpice A D reports as a cumulative ambiguity hazard See Chapter 16 Digital worst case timing analysis for more information SUPPRESSED WARNING Pulse applied to the input of a primitive that is shorter than the active GLITCH propagation delay was ignored by PSpice A D significance depends on the nature of the circuit There might be a problem either with the stimulus or with the path delay configuration of the circuit See Chapter 16 Digital worst case timing analysis for more information NET STATE WARNING Two or more outputs attempted to drive a net to different states CONFLICT which PSpice A D reports as an X unknown state This usually results from improper selection of a bus driver s enable inputs ZERO DELAY FATAL Output of a primitive changed more than 50 times within a single OSCILLATION digital time step PSpice A D aborted the run DIGITAL INPUT SERIOUS Voltage on a digital pin was out of range whi
424. schematic page see Figure 2 and click to place the first part Move the cursor and click again to place the second part Right click and choose End Mode to stop placing parts To place the diodes 1 From the Place menu choose Part to display the Place Part dialog box Add the library for the parts you need to place a Click the Add Library button 0 Select DIODE OLB from the PSpice library and click Open In the Part text box type D1N39 to display a list of diodes Select DIN3940 and click OK Press R to rotate the diode to the correct orientation Click to place the first diode D1 then click to place the second diode D2 Right click and choose End Mode to stop placing parts Example circuit creation ES eS Note There are two sets of library files supplied with Capture and PSpice A D The standard schematic part libraries are found in the directory Capture Library The part libraries that are designed for simulation with PSpice A D are found in the sub directory Capture Library PSpice In order to have access to specific parts you must first configure the library in Capture using the Add Library function pE o When placing parts e Leave space to connect the parts with wires e You will change part names and values that do not match those shown in Figure 2 later in this section 57 Chapter 2 Simulation examples 58 KC To move the text associated w ith the diodes or any oth
425. se Monte Carlo sensitivity worst case DC sensitivity Fourier and small signal DC transfer function require you to specify output variables for voltages and currents at specific points on the schematic Depending upon the analysis type you may need to specify the following e Voltage ona net a pin or at a terminal of a semiconductor device e Current through a part or into a terminal of a semiconductor device e Adevice name If output variables or other information are required select Output File Options in the Monte Carlo Worst Case dialog box and enter the required parameters Voltage Specify voltage in the following format v modifiers lt out id gt lt out id gt 1 where lt out id gt is lt net id gt or lt pin id gt 2 lt net id gt is a fully qualified net name 3 lt pin id gt is lt fully qualified device name gt lt pin name gt 4 A fully qualified net name as referred to in line 3 above is formed by prefixing the visible net name from a label applied to one of the segments of a wire or bus or an offpage port connected to the net with the full hierarchical path separated by periods At the top level of hierarchy this is just the visible name A fully qualified device name from line 4 above is distinguished by specifying the full hierarchical path followed by the device s part reference separated by period characters For example a resistor with part reference R34 inside part Y1 p
426. se sections explain how to use different tools to create parts for model definitions e Using the Model Editor to create parts on page 5 173 e Using the Model Editor to create parts on page 5 173 e Basing new parts on a custom set of parts on page 5 175 Other useful information These sections explain how to refine part graphics and properties e Editing part graphics on page 5 177 e Defining part properties needed for simulation on page 5 181 What s different about parts used for simulation What s different about parts used for simulation A part used for simulation has these special characteristics e a link toa simulation model For information on adding simulation models to a model library see Chapter tlist translati x a 4 Creating and editing models e modeled pins e other simulation properties specific to the part which can include hidden pin connections or propagation delay level for digital parts Ways to create parts for models If you want to Then do this To find out more see this Create parts for a setof Use the Model Editor to Basing new parts on a custom set vendor or user defined create parts from a model of parts on page 5 175 models saved in a model library library Change the graphic standard for an existing model library Automatically create Use the Model Editor and Using the Model Editor to create one part each time you enable automatic creation parts o
427. second of the transient analysis is used and that 361 Chapter 11 Transient analysis 362 portion is assumed to repeat indefinitely Since V1 s sine wave does indeed repeat every one microsecond this is sufficient In general however you must make sure that the fundamental Fourier period fits the waveform in the transient analysis Parametric and temperature analysis 12 Chapter overview This chapter describes how to set up parametric and temperature analyses Parametric and temperature are both simple multi run analysis types This chapter includes the following sections e Parametric analysis on page 12 364 e Temperature analysis on page 12 373 Chapter 12 Parametric and temperature analysis Note Parametric analysis is not supported in PSpice A D ww Basics See Setting up analyses on page 8 289 for a description of the Simulation Settings dialog box 364 Parametric analysis Minimum requirements to run a parametric analysis Minimum circuit design requirements e Set up the circuit according to the swept variable type as listed in Table 1 e Setup a DC sweep AC sweep or transient analysis Tabel Parametric analysis circuit design requirements Sw ept variable type Requirement voltage source voltage source with a DC specification VDC for example temperature none current source current source with a DC specification IDC for example model parameter PSpice A D model
428. ser displays only the matching part names To find parts using the online OrCAD Library List i Note In Windows Explorer double click LIBLIST PDF located in the directory where PSpice A D is installed Acrobat Reader starts and displays the OrCAD Library List From the Tools menu choose Find In the Find What text box type the generic part name Enter any other search criteria and then click Find The Acrobat Reader displays the first page where it finds a match Each page maps the generic part name to the parts and corresponding vendor and part library name in the OrCAD libraries If you want to repeat the search from the Tools menu choose Find Again If you are unsure of the device type you can scan all of the device type lists using the Acrobat search capability The first time you do this you need to set up the across list index To find out more refer to the online Adobe Acrobat manuals Using parts that you can simulate Note This method finds only parts that OrCAD supplies that have models If you want to include user defined parts in the search use the parts browser in Capture see page 3 102 or press Ctrl F Instead of the generic part name you can enter other kinds of search information such as device type or manufacturer press Ctrl G 103 Chapter 3 Preparing a design for simulation To find out more about how to use these parts and define their properties look up
429. sign 2 device and 10 lot tolerances to the resistance multiplier for R1 1 Select R1 2 From the Edit menu choose PSpice Model Capture searches the libraries for the Rbreak model definition and makes a copy to create an instance model 3 To change the instance model name from Rbreak to Rmontel1 do the following a Inthe Model Text frame double click Rbreak b Type RMontel 4 To add a 2 device tolerance and a 10 lot tolerance to the resistance multiplier do the following a Add the following to the MODEL statement after R 1 DEV 2 LOT 10 The model editing window should look something like Figure 81 5 From the File menu choose Save By default Capture saves the RMontel MODEL definition to the design_name lib library which is Monte Carlo analysis You can use the model editor to change the MODEL or SUBCKT syntax for a model definition To find out more about the model editor see Editing model text on page 4 152 or refer to the online PSpice Reference Manual To find out more about adding model libraries to the configuration see Configuring model libraries on page 4 162 389 Chapter 13 Monte Carlo and sensitivity worst case analyses 390 E PSENSOR lib OrCAD Model Editor Rbreak BEE File Edit View Model Plot Tools Window Help 18 x SCI ile JARRI A mE cE model RMontel RES R 1 DEV 2 LOT 10 a Figure 81 Model definition for RMontel1 PSENSOR LIB Capture
430. sign for simulation Note This method finds any part contained in the current part libraries configuration including parts for user defined models If you want to find out more about a part supplied in the OrCAD libraries such as manufacturer or whether you can simulate it then search the online Library List see page 3 103 102 Notice the following There is a generic OP 27 part provided by OrCAD the OP 27 AD from Analog Devices Inc and the OP 27 LT from Linear Technology Corporation The Model column for all of these parts contains an asterisk This indicates that this part is modeled and that you can simulate it Finding the part that you want If you are having trouble finding a part you can search the libraries for parts with similar names by using either the parts browser in Capture and restricting the parts list to those names that match a specified wildcard text string or the online Library List and searching for the generic part name using capabilities of the Adobe Acrobat Reader To find parts using the parts brow ser 1 2 In Capture from the Place menu choose Part In the Part Name text box type a text string with wildcards that approximates the part name that you want to find Use this syntax lt wildcard gt lt part_name_fragment gt lt wildcard gt where lt wildcard gt is one of the following to match zero or more characters to match exactly one character The parts brow
431. sis type list box 3 In the Sweep Variable frame select Global Parameter 4 Enter the following values Monte Carlo analysis See Setting up analyses on page 8 289 for a description of the Simulation Settings dialog box 391 Chapter 13 Monte Carlo and sensitivity worst case analyses 392 Table 3 In this text box Type this Parameter name P Start value 0 End value 53 0 Increment Oel To set up the Monte Carlo analysis Hn wo A WS N FF Select the Monte Carlo Worst Case option Check Monte Carlo if it is not already selected In the Number of runs text box type 10 In the Save data from list box select All Type I Meter in the Output variable text box Click OK to save the simulation profile Running the analysis and viewing the results To complete setup simulate and view results 1 From Capture s PSpice menu choose Run to start the simulation When the simulation is complete PSpice A D automatically displays the selected waveform Because PSpice A D ran a Monte Carlo analysis it saved multiple runs or sections of data These are listed in the Available Sections dialog box From PSpice A D s Trace menu choose Performance Analysis Click the Select sections button In the Available Sections dialog box click the All button Click OK Monte Carlo analysis 6 To display current through the Meter voltage source do the following a From Capture s PSpice menu po
432. sors positioned on a trough and peak of V 1 To position a cursor on the next trough of a waveform from the Trace menu point to Cursor then choose Trough Cursor 1 is positioned on the first trough dip of the V 1 waveform Cursor 2 is positioned on the second peak of the same waveform In the Probe Cursor window cursor 1 and cursor 2 coordinates are displayed A1 and A2 To position a cursor on the next peak of a respectively with their difference shown in the bottom waveform from the Trace menu point to line dif The logic state of the Out signal is also displayed Cursor then choose Peak to the right of the cursor coordinates For more information about cursors refer to the online Help in PSpice A D 515 Chapter 17 Analyzing waveforms 516 The mouse buttons are also used to associate each cursor with a different trace by clicking appropriately on either the analog trace symbol in the legend or on the digital trace name see Table 2 on page 17 514 These are outlined in the pattern corresponding to the associated cursor s crosshair pattern Given the example in Figure 122 right clicking the V 2 symbol will associate cursor 2 with the V 2 waveform The analog legend now appears as shown below cursor 1 cursor 2 The Probe Cursor window also updates the A2 coordinates to reflect the X and Y values corresponding to the V 2 waveform Tracking digital simulation messages PSpice A D provides explanatory m
433. sponding trace symbol is outlined with a dashed line In the digital area of the plot if any both cursors are initially placed on the trace named first along the y axis The corresponding trace name is outlined with a dashed line User interface features for waveform analysis press Ctrl lt gt Shift C You can move the cursor box any where over the Probe window by dragging the box to another location 513 Chapter 17 Analyzing waveforms For more information about the cursor commands refer to the online Help in PSpice A D For a family of curves such as from a nested DC sweep you can use the mouse or the arrow keys to move the cursor to one of the other curves in the family You can also click the desired curve 514 Moving cursors To move cursors along a trace using menu commands 1 From the Trace menu point to Cursor then choose Peak Trough Slope Min Max Point or Search To move cursors along a trace using the mouse 1 Use the right and left mouse buttons as described in Table 2 below Table2 Mouse actions for cursor control Click this To do this with the cursors cursor assignment Left click the analog trace Associate the first cursor with symbol or digital trace name the selected trace Right click the analog trace Associate the second cursor symbol or digital trace name with the selected trace cursor movement Left click in the display area Move the first c
434. st of the analog and digital parts in the model and part libraries Online Help Choosing Search for Help On from the Help menu displays an extensive online help system The online help includes e step by step instructions on how to set up PSpice A D simulations and analyze simulation results e reference information about PSpice A D e Technical Support information If you are not familiar with Windows NT or 95 Help system choose How to Use Help from the Help menu xxxi Before you begin Note Not supported in PSpice 7 NW A D Basics baa Note For expert PSpice A D users these are the PSpice circuit file commands that are not available in the Basics package e STIMULUS e STIMLIB e SAVEBIAS e LOADBIAS xxxii If you don t have the standard PSpice A D package If you have PSpice A D Basics PSpice A D Basics provides the basic functionality needed for analog and mixed signal design without the advanced features in the full PSpice A D package Because this guide is for both PSpice A D Basics and PSpice A D users there are some features described here that are not available to PSpice A D Basics users The Basics icon shown in the sidebar is used throughout this user s guide to mark each section or paragraph which describes a feature not available to PSpice A D Basics users If an entire section describes a non Basics feature the icon is placed next to the section title If an individ
435. steps Note OrCAD recommends that all inductors have a parallel resistor series resistance is good for modeling DC effects but does not limit the inductor s bandwidth The parallel resistor gives a good model for eddy current loss and limits the bandwidth of the inductor The size of 559 Chapter B Convergence and time step too small errors 560 resistor should be set to be equal to the inductor s impedance at the frequency at which its Q begins to roll off Example A common one millihenry iron core inductor begins to roll off at no less than 100KHz A good resistor value to use in parallel is then R 2 2 100e3 001 628 ohms Below the roll off frequency the inductor dominates above it the resistor does This keeps the width of spikes from becoming unreasonably narrow Bipolar transistors substrate junction The UC Berkeley SPICE contains an unfortunate convention for the substrate node of bipolar transistors The collector substrate p n junction has no DC component If the capacitance model parameters are specified e g CJS then the junction has voltage dependent capacitance but no DC current This can lead to a sneaky problem if the junction is inadvertently forward biased it can create a very large capacitance The capacitance goes as a power of the junction voltage Normal junctions cannot sustain much forward voltage because a large current flows The collector substrate junction is an exception because it h
436. stor and a capacitor The design is shown in Figure 119 T1 IF 1 ey 400pF r 750 1 u2 Us H al our es 2i 3 zek p Of j a 7414 7414 Ali OUTBAR u1 CLR 7405 i 74107 u3 a ji RESET 1 D STIMULUS Reset 7404 Figure 119 Mixed analog digital oscillator design The circuit uses a one bit digital stimulus device DSTIM1 The device is connected to the rest of the circuit by a single pin and creates a reset pulse which resets the flip flop Setting up the design Set up and simulate the oscillator circuit using Capture To open the design file 1 From Capture s File menu point to Open and choose Project 2 Open the following project in your OrCAD program installation directory PSPICE SAMPLES MIXSIM OSC OSC OPJ To clear markers 1 From Capture s PSpice menu point to Markers and choose Delete All 501 Chapter 17 Analyzing waveforms gt E or press You can also use aliasesto refer to nets For example V U2 A refers to the same net as 1 In the Probe window double click the y axis In the Y Axis Settings dialog box you can change the settings for another y axis by selecting it from the Y axis Number box 502 Running the simulation To run the simulation 1 From Capture s PSpice menu choose Run Because the oscillator circuit used here has been run with only
437. sult will look like Figure 60 To adda load line for a resistor add a trace that computes the load line from the sweep voltage Assume that the X axis variable is the sweep voltage V_VD which runs from 0 to 5 volts The expression which will add a trace that is the load line for a 50 kohm resistor is 5V V_VD 50K This can be useful for determining the bias point for each member of a curve family as shown in Figure 61 DC Sweep M Mbreakh m Figure 59 Curve family example schematic In Capture from the PSpice menu point to Markers then choose Mark Current Into Pin to add a current marker V_VD is the hierarchical name for VD created by netlisting the schematic 313 Chapter9 DC analyses 150uA 168uA 5 uA au 1 60 2 0U 3 00 4 0u 5 8U a ID M1 Figure 60 Device curve family SOK Resistor Load Line 166u Se hess Sea i te 2 AE ee Bu 1 00 2 00 3 00 4 o 5 Buu o ID HM1 5U U_UD 50K u uD Figure 61 Operating point determination for each member of the curve family 314 Bias point Bias point Minimum requirements to run a bias point analysis Minimum circuit design requirements None Minimum program setup requirements 1 Under Analysis type in the Simulation Settings dialog box select Bias Point 2 For the General Settings option enter the necessary parameter values and select the appropriate check boxes to complete the anal
438. sults to the PSpice output file 535 Generating plots of voltage and current values 535 Generating tables of voltage and current values 536 Generating tables of digital state changes 537 Creating test vector files ease eR kk A Sk RW we BR 538 Appendix A Setting initial state 541 Appendix overview 4 eo ete ea eS ERE SS ChE RRS ER ER SEES 541 Save and load bias point es a a Oe oe ee OES Ree Ee 542 DAVE Dias POWIE s ssa ached See oe RE eA ARE EEE SR Ow EH 542 Xvi Appendix B Contents Load bias point s dd ea eS oe he ew ee eS eS 543 SETPOIIS 2 Save 4 oid 6 4 44 does eR 6 Oe Ee Bee eA ee Bees A 544 Setting initial conditions ooa a 546 Convergence and time step too small errors 547 Appendix overview ooa a 547 Introduction 2 6 an e ee eee eee a e ae ees 548 Newton Raphson requirements 0 00000005 548 Is there a solution 2 0 0 0 00000 0c L 549 Are the Equations Continuous a aoao 550 Are the derivatives correct oaoa a 550 Is the initial approximation close enough 551 Bias point and DC sweep 246 lt 425 5 see esd Shae eR a RS 553 Semiconductors 0 0 ea e a e a 553 SWitCh s 4 iw oo eewe Me bbe eee bd ee eee eb ew dow ES 554 Behavioral modeling expressions 0 0004 555 Transient analysis 2 4 lt 65 dhs bee bee btw ew Pe ew ba oO Ss 556 Skipping the bias point oa ox tae ee he ee eee e
439. t 3 or 4 terminal out device gt I ac lt transmission line out device gt lt Z gt or I lt z gt ac lt 3 or 4 terminal out device gt lt DC sweep variable gt current through non grounded terminal x of a3 or 4 terminal out device current through one end z of a transmission line out device voltage or current source name Table Element definitions for 2 terminal devices Output variable examples lt out id gt or Device type lt out device gt device indicator capacitor C diode D voltage controlled E voltage source current controlled F current source voltage controlled G current source current controlled H voltage source independent current I source inductor L V CAP 1 I CAP V D23 1 1 D23 V E14 1 1 E14 V F1 1 I F1 V G2 1 1 G2 V HSOURCE 1 I HSOURCE V IDRIV I IDRIV V L1 1 L1 295 Chapter 8 Setting up analyses and starting simulation Table Element definitions for 2 terminal devices sou ane Output variable Device type lt out device gt p a examples device indicator resistor R V RC1 1 I RC1 voltage controlled S V SWITCH switch I SWITCH independent voltage V V VSRC source I VSRC current controlled W V W22 switch I W22 Table8 Element definitions for 3 or 4 terminal devices lt out id gt or lt out TE Output variable Device type device gt lt P id gt examples device indicator GaAs MESFET B D
440. t phase Advanced Phase of Voltage Phase of Current group delay Advanced Group Delay of Voltage Group Delay of Current real Advanced Real Part of Voltage Real Part of Current imaginary Advanced Imaginary Part of Voltage Imaginary Part of Current You can use these markers instead of the built in functions provided in output variable expressions see Table 12 on page 17 528 However these markers are only available after defining a simulation profile for an AC Sweep Noise analysis 2 Point to the wires or pins you wish to mark and click to place the chosen markers 3 Right click and select End Mode to stop placing markers 4 If you have not simulated the circuit yet from the PSpice menu choose Run To hide or delete marked results 1 From Capture s PSpice menu point to Markers then choose one of the following Table 24 Viewing waveforms Choose this option To do this Hide All Delete All Hide traces in the waveform analysis display for all markers placed on any page or level of the schematic Remove all markers from the schematic and all corresponding traces from the waveform analysis display 489 Chapter 17 Analyzing waveforms 490 Limiting waveform data file size When PSpice A D performs a simulation it creates a waveform data file The size of this file for a transient analysis is roughly equal to transistors simulation time points 24 bytes The size fo
441. t equals the number of nodes in the subcircuit definition 187 Chapter 5 Creating parts for models If the correspondence between pin names and nodes is as follows Table 6 This node name Corresponds to this pin name 10 IN 3 IN 27 OUT 2 OUT then the template looks like this X REFDES SIN SIN SOUT OUT MODEL The rules of agreement are outlined in Figure 34 Number of pins called out must equal in template Sequence of pins called out in template Names of pins called out must match Names of modeled pins in template shown in part Unmodeled pins may appear on a part like the two voltage offset pins on a 741 opamp part These pins are not netlisted and do not appear on the template must equal Number of modeled pins shown in part Number of nodes in first line of subcircuit definition Sequence of nodes in first line m of subcircuit definition Figure 34 Rules for pin callout in subcircuit templates 188 10_ LEVEL The IO_LEVEL property defines what level of interface subcircuit model PSpice A D must use for a digital part that is connected to an analog part To use the 10_LEVEL property with a digital part 1 Add the IO_LEVEL property to the part and assign a value shown in the table below Table 7 Assign this value To use this interface subcircuit level 0 circuit wide default 1 AtoD1 and DtoA1 2 AtoD2 and DtoA2 3 AtoD3 and DtoA3 4 AtoD
442. t formats as you want to see tabulated 6 Repeat steps 2 through 5 for any additional analysis types you want plotted Note If you do not enable an analysis type PSpice A D reports the transient results Generating tables of digital state changes You can generate a table of digital state changes during a transient analysis for any net To generate a table of digital state changes to the output file 1 Place a PRINTDGTLCHG part from the PSpice library SPECIAL OLB and connect it to the net that you are interested in Sal 537 Chapter 18 Other output options To find out about vector file syntax refer to the online OrCA D PSpice A D Reference Manual To find out about setting up digital stimuli see Defining a digital stimulus on page 14 413 double click here to edit the POS property VECTO double click here to edit all properties Note You can group separate signal values to form a hex or octal value by specifying the same POS property and defining RADIX as Hex or Octal Define the bit position within the value using the BIT property 538 Creating test vector files Capture provides a special VECTOR part that lets you save digital simulation results to a vector file Whenever any net with an attached VECTOR part changes state PSpice A D writes a line of time value data to the vector file using the same format as the file stimulus device This means that you can use the vector file to drive inpu
443. t save the instance model 145 The Model Editor tutorial a oa aaa weed Rew OH 146 Creating the half wave rectifier design 146 Using the Model Editor to edit the D1 diode model 147 Entering data sheet information 0 147 Extracting model parameters cau ss2a Bei ease en 149 Contents Adding curves for more than one temperature 150 Completing the model definition 151 Editing model text tie Keo eRe ee ee eee a 152 Editing MODEL definitions aaa 152 Editing SUBCKT definitions aoaaa a 153 Changing the model name a es aaa 153 Starting the Model Editor from the schematic page editor in Capture 153 What is an instance model aaan 154 Starting the Model Editor naaa 154 Saving design models cic bs aaa eee Pe Ra 155 Example editing a Q2N2222 instance model 156 Starting the Model Editor lt a eb0c e reeds tees 156 Editing the Q2N2222 X model instance 156 Saving the edits and updating the schematic 157 Using the Create Subcircuitcommand 04 157 Changing the model reference to an existing model definition 159 Reusing instance models 2 5 G44 6 beng db eR Rae ERE RRO 160 Reusing instance models in the same schematic 160 Making instance models available to all designs 161 Configuring model libraries 3s cee odode beds ede ewe Ss
444. t the model for an existing part and have it affect all designs that use that part Create a model from scratch and automatically create a part for it to use in any design Create a model from scratch without a part and have the model definition available to any design View model characteristics for a part Define tolerances on model parameters for statistical analyses Test behavior variations on a part Refine a model before making it available to all designs Derive subcircuit definitions from a hierarchical design Create or load the part first in the part editor then edit the model using the Model Editor Start the Model Editor and enable disable automatic part creation as needed then create or view the model Select the part instance on your schematic then edit the model using the Model Editor Select the part instance on your schematic page then edit the model using the Model Editor Use the Create Subcircuit command in the schematic page editor Running the Model Editor from the schematic page editor on page 4 143 Running the Model Editor alone on page 4 141 Starting the Model Editor from the schematic page editor in Capture on page 4 153 Running the Model Editor from the schematic page editor on page 4 143 Starting the Model Editor from the schematic page editor in Capture on page 4 153 Using the Create Subcircuit command on page
445. t to the OrCAD program group then choose PSpice A D 2 Select Open Simulation from the File menu from the PSpice A D window 3 Do one of the following e Type each file name in the File Name text box separated by a space e Use the combination keystrokes and mouse clicks in the list box as follows Ctrl click to select file names one at a time and Shift click to select groups of files Method 2 1 From the Start menu point to the OrCAD program group then choose PSpice A D 2 Update the command line in the following way e Include a list of circuit file names separated by spaces Circuit file names can be fully qualified or can contain the wild card characters and The PSpice A D simulation window The PSpice A D Simulation Window is an MDI Multiple Document Interface application This implies that you can open and display multiple files at the same time in this 301 Chapter 8 Setting up analyses and starting simulation 302 window For instance you can have a waveform file DAT a circuit file CIR and a simulation output file OUT open and displayed in different child windows within this one window The PSpice A D Simulation Window consists of three sections the main window section where the open files are displayed the output window section where output information such as informational warning and error messages from the simulator are shown and the simulation status window section
446. t to which an IC symbol is connected The voltages are clamped this way for the entire bias point calculation NODESET1 is a one pin symbol which helps calculate the bias point by providing a initial guess for some net NODESET2 is a two pin symbol which helps calculate the bias point between two nets Some or all of the circuit s nets may be given an initial guess NODESET symbols are effective for the bias point both small signal and transient bias points and for the first step of the DC sweep It has no effect during the rest of the DC sweep or during the transient analysis itself Setpoints Unlike the IC pseudocomponents NODESET provides only an initial guess for some net voltages It does not clamp those nodes to the specified voltages However by providing an initial guess NODESET symbols may be used to break the tie in a flip flop for instance and make it come up ina desired state To guess at the bias point enter the initial guess in the Value text box for the VALUE property PSpice A D attaches a voltage source with a 0 0002 ohm series resistance to each net to which an IC symbol is connected These pseudocomponents are netlisted as PSpice A D IC and NODESET commands Refer to these commands in the online OrCA D PSpice A D Reference Manual for more information Setpoints can be created for inductor currents and capacitor voltages using the IC property described in Setting initial conditions on page A 546 545 C
447. ta sections from one or more files Appending waveform data files To append a waveform data file 1 InPSpice A D from the File menu choose Append Waveform DAT 2 Select a DAT file to append and click OK 493 Chapter 17 Analyzing waveforms or press The Simulation Output Variables list in the Add Traces dialog box contains the output variables for all loaded waveform data files Example To plot the V 1 output for data section 1 from the second data file loaded type the following trace expression V 1 1 f2 You can also use the name of the loaded data file to specify it For example to plot the V 1 output for all data sections of a loaded data file MYFILE DAT type the following trace expression V 1 MYFILE DAT jo w a o UCOuC trace symbols Figure 115 Trace legend symbols 494 If the file has multiple sections of data for the selected analysis type the Available Sections dialog box appears Do one of the following e Click the sections you want to use e Click the All button to use all sections Click OK Adding traces from spedfic loaded waveform data files If two or more waveform data files have identical simulation output variables trace expressions that include those variables generate traces for each file However you can specify which waveform data file to use in the trace expression You can also determine which waveform data file was used to generate a specific trace
448. tab and configure RESET STM as an include file Use the Browse button if necessary to locate the file Defining simulation time To set up the transient analysis 1 From Capture s PSpice menu choose New Simulation Profile Enter a name for the new simulation profile Click OK In the Analysis Type list box on the Analysis tab select Time Domain Transient 5 Inthe Run to Time text box type the duration of the transient analysis 6 Click OK Adjusting simulation parameters Use the Options tab of the Simulation Settings dialog box to adjust the simulation behavior of your circuit s digital devices General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window Category Timing Mode C Minimum Typical Magimum C Worst case min max I Suppress simulation error messages in waveform data file Initialize all flip flops to fx z Default 1 0 level for 4 D interfaces EE Advanced Options Reset To access the digital settings in the Options tab 1 From Capture s PSpice menu choose Edit Simulation Settings 2 Click the Options tab 3 In the Category list box select Gate level simulation Each of the dialog box settings is described in the following sections Adjusting simulation parameters For additional options see Output control options on page 14 440 427 Chapter 14 Digital simulation Note Propagation delays are AA
449. tage of interest If you used an expression such as V 2 then the referenced net 2 in this case is interpreted as the name of a local or global net A local net is a labeled wire or bus segment in a hierarchical schematic or a labeled offpage connector A global net is a labeled wire or bus segment at the top level or a global connector OrCAD Capture recognizes these constructs in ABM expressions V lt net name gt V lt net name gt lt net name gt I lt vdevice gt When one of these is recognized Capture searches for lt net name gt or lt vdevice gt in the net name space or the device name space respectively Names are searched for first at the hierarchical level of the part being netlisted If not found there then the set of global names is searched If the fragment is not found then a warning is issued but Capture still outputs the resulting netlist When a match is found the original fragment is replaced by the fully qualified name of the net or device For example suppose we have a hierarchical part U1 Inside the schematic representing U1 we have an ABM expression including the term V Reference If Reference is the name of a local net then the fragment written to the netlist will be translated to V U1_Reference If Reference is the name of a global net the corresponding netlist fragment will be V Reference Names of voltage sources are treated similarly For example an expression incl
450. ter device This is a band reject or notch filter with the stop band between 1 2 kHz and 2 kHz and pass bands below 800 Hz and above 3 kHz The pass band ripple is 0 1 dB and the minimum stop band attenuation is 50 dB This will produce a PSpice A D netlist declaration like this ENOTCH 5 0 CHEBYSHEV V 10 BR 1 2K 800 3K 2K 1dB 50dB Control system parts Aw 1 2kHz 0 1dE50gp500Hz 3kHz RT te Figure 37 BANDPASS filter part example 4 RS Tiiz 0 1dE50gp500Hz AkHz Az 2kHz Figure 38 BANDREJ filter part example 205 Chapter 6 Analog behavioral modeling If more than five values are required the part can be customized through the part editor Insert additional row variables into the template using the same form as the first five and add ROWn properties as needed to the list of properties 206 Integrator and differentiator The integrator and differentiator parts are described below INTEG IC initial condition of the integrator output GAIN gain value The INTEG part implements a simple integrator A current source capacitor implementation is used to provide support for setting the initial condition DIFFER GAIN gain value The DIFFER part implements a simple differentiator A voltage source capacitor implementation is used The DIFFER part provides one input and one output Table look up parts TABLE and FTABLE parts provide a lookup table that is used to correlate a
451. teristics of a digital part Create parts either automatically for models using the part wizard or the Parts utility or by manually defining AKO parts define simulation specific properties Create and edit part graphics pins and properties in general 97 Chapter 3 Preparing a design for simulation When netlisting fails or the simulation does not start If you have problems starting the simulation there may be problems with the design or with system resources If there are problems with the design PSpice A D displays errors and warnings in the Simulation Output window You can use the Simulation Output window to get more information quickly about the specific problem To get online information about an error or warning shown in the Simulation Output window 1 Select the error or warning message 2 Press F1 The following tables list the most commonly encountered problems and where to find out more about what to do Things to check in your design Table 5 Make sure that To find out more see this Y XY SNS ARASAN The model libraries stimulus files and Configuring model libraries on page 4 162 include files are configured The parts you are using have models Unmodeled parts on page 3 120 and Defining part properties needed for simulation on page 5 181 You are not using unmodeled pins Unmodeled pins on page 3 123 You have defined the grounds Missing ground on page 3 124 Eve
452. ters depends on the primitive type lt digital power node gt lt digital ground node gt are the nodes used by the interface subcircuits which connect analog nodes to digital nodes or vice versa lt node gt is one or more input and output nodes The number of nodes depends on the primitive type and its parameters Analog devices digital devices or both may be connected to a node If a node has both analog and digital connections then PSpice A D Digital device params MNTYMXDLY 0 IO_LEVEL 0 optional DPWR G_DPWR DGND G_DGND U1 NAND 2 DPWR DGND AB Y D_7400 IO_STD DLY MNTYMXD O_LEVEL IO_LEVEL Timing model 1 O model model IO_STD uio drvh 96 4 drvl 104 AtoBT AtoD_STD AtoD2 AtoD_STD_NX AtoD4 AtoD_STD_NX DtoA2 DtoA_STD DtoA4 DtoA_STD tswhl1 1 373ns tswiht 3 382ns model D_7400 ugate tplhty 11ns tplhmx 22ns tphlty 7ns tphlmx 15ns ROWER DIGIFPWR AtoD interface subcircuit DtoA interface subcircuit subckt AtoD_STD A D DPWR DGND subckt DotA_STD D A DPWR DGND params CAPACITANCE 0 params DRVL 0 DRVH 0 CAPACITANCE 0 O0 A DGND DO74 DGTLNET D IO_STD N1 A DGND DPWR DIN74 DGTLNET D IO_STD C1 A DGN CAPACKTANCE 0 1pF C1 A DGND CAPACITANC Digital output AtoD mode Digital input DtoA model model DO74 doutput model DIN74 dinput sOname X sOvlo 0 8 sOvhi 2 0 sOname 0 sOtsw 3 5ns sOrlo 7 13 sOrhi 389 s1iname 0 sivlo 0 0 sivhi 0 8 siname 1
453. tes supplementary analysis information in the form of lists and tables and saves this in the simulation output file Setting up analyses To set up one or more analyses 3 From the PSpice menu choose New Simulation Profile 4 Enter the name of the profile and click OK 5 Click the Analysis tab if it is not already the active tab in the dialog box Setting up analyses Note Monte Carlo Worst Vea Case Analysis is not supported VE 4 in PSpice A D Basics See Part four Viewing results for information about using waveform analysis in PSpice A D Specitic information for setting up each type of analysis is discussed in the following chapters 289 Chapter 8 Setting up analyses and starting simulation See Output variables on page 8 292 for a description of the output variables that can be entered in the Simulation Settings dialog box displayed for an analysis type Specific information for setting up each type of analysis is discussed in the following chapters 290 Simulation Settings New xj General Analysis Include Files Libraries Stimulus Options Data Collection Probe window Analysis type Run to time 1000ns seconds TSTOP Print values in the output file every fi Ons seconds Time Domain Transient Options General Settings Transient options Monte Carlo worst Case Maximum step size seconds OParametric Sweep t A B Temperature Sweep T Skip the ini
454. text box after the last character in the expression 0 Type one of the following where radix is a value from the table on page 14 433 e If you specified a display_name then type radix e Ifyou did not specify a display_name then type radix two semicolons preceding the radix value Analyzing results Tracking timing violations and hazards When there are problems with your design such as A Note Timing violations and setup hold violations pulse width violations or ter hazards are not supported in worst case timing hazards PSpice A D saves messages to VE PSpice A D Basics the simulation output file or data file You can select messages and have the associated waveforms and The messaging feature is discussed further detailed message text automatically appear i Tra kine dicita simulation PSpice A D can also detect persistent hazards that may messages 0n page 17 517 of have a potential effect on a primary circuit output or on Chapter 17 Analyzing the internal state of the design waveforms Persistent hazards Digital problems are usually either timing violations or timing hazards Timing violations include SETUP HOLD and minimum pulse WIDTH violations of component specifications This type of violation may produce a change in the state behavior of the design and potentially in the answer However the effects of many of these errors are short lived and do not influence the final circuit results For exa
455. th both cursors There are also ways to display the placed difference between two voltages as a trace TS cee e In PSpice add the trace expression a gt S mS e mmm V In V Mid 88a 9 M e E A met Pees 2 e In Capture from the PSpice menu point to Markers and choose Voltage Differential Place the two markers on different pins or wires For Help press FT a V in 15 100 SRR ZIS Figure 13 Voltage difference at V In 4 volts To delete all of the traces You can also delete an individual trace by selecting its name in the trace legend and h Delete All T i 1 From the Trace menu choose Delete races then pressing Delt At this point the design has been saved Ifneeded E ample To delete the V In trac dick the OAE i PSN we ae eae as lt text V In located under the plot s eee ana YSIS exercises later using e Save x axis and then press Delete Finding out more about DC sweep analysis Table 2 1 To find out more about this See this DC sweep analysis DC Sweep on page 9 306 71 72 Chapter 2 Simulation examples Transient analysis This example shows how to run a transient analysis on the clipper circuit This requires adding a time domain voltage stimulus as shown in Figure 14 Di D1N3940 RI ci Ing syOut lt AAN H gt 1k 0 47u D2 Re D1N3940 5 5k lt S o EJ Jml l s 3 as Ol 2 SINE dl Figure 14 Diode clipper circuit with a vo
456. the corresponding PSpice device letter in the A nalog Devices chapter in the online OrCA D PSpice A D Reference Manual and then see the Capture Parts sections 104 Passive parts The OrCAD libraries supply several basic parts based on the passive device models built into PSpice A D These are summarized in the following table Table7 Passive parts These parts are Which is this PSpice available For this device type device letter C capacitor C C_VAR L inductor L R resistor R_VAR XFRM_LINEAR transformer Kand L K_LINEAR T ideal transmission line T TLOSSY Lossy transmission line T TnCOUPLED coupled transmission line T and K TnCOUPLEDX KCOUPLEn TLOSSY is not available in Basics packages For these device types the OrCAD libraries supply several parts Refer to the online OrCA D PSpice A D Reference Manual for the available parts Breakout parts The OrCAD libraries supply passive and semiconductor parts with default model definitions that define a basic set of model parameters This way you can easily e assign device and lot tolerances to model parameters for Monte Carlo and sensitivity worst case analyses e define temperature coefficients and e define device specific operating temperatures These are called breakout parts and are summarized in the following table Table8 Breakout parts Use this Which is this PSpice breakout part For this device type
457. the digital plot size using the mouse 1 Display at least one digital trace and one analog trace in the Probe window for which you want to set the digital size To change the bottom position of the digital Probe window do the following a Place the mouse pointer between the analog and digital parts of the plot Click the plot separator Drag the plot separator until you have the digital size you want To change the left side of the digital Probe window do the following a Place the mouse pointer at the left edge of the digital Probe window you want to resize Click the left edge Drag the left edge of the digital Probe window to adjust the space available for displaying digital trace names To set the digital plot size using menu options 1 Display at least one digital trace in the plot for which you want to set the digital size 2 From the Plot menu choose Digital Size 3 Inthe Digital Size dialog box set the following e Percentage of Plot to be Digital e Length of Digital Trace Name 4 Click OK Modifying trace expressions and labels You can modify trace expressions text labels and ellipse labels that are currently displayed within the Probe window thus eliminating the need to delete and recreate any of these objects To modify trace expressions 1 Click the trace name to select it selection is indicated by a color change 2 From the Edit menu choose Modify Object 3 In the Modify Trace
458. the digital transition The values for these model parameters should be obtained by measuring the time it takes the analog output of the DtoA with a nominal analog load attached to change to the switching threshold after its digital input changes If the switching time is larger than the propagation delay for an output no warning is issued and a delay of zero is used When creating your own digital device models you can create I O models like these for the primitives you are using OrCAD recommends that you save these in your own custom model library which you can then configure for use with a given design Note The switching time parameters are not used when the output drives a digital node Input Output characteristics See the online OrCA D PSpice A D Reference Manual for more informaiton on units and defaults for these parameters 259 Chapter 7 Digital device modeling Table3 Digital I O model parameters UIO model sai Description parameter INLD input load capacitance OUTLD output load capacitance DRVH output high level resistance DRVL output low level resistance DRVZ output Z state leakage resistance INR input leakage resistance TSTOREMN minimum storage time for net to be simulated as a charge TPWRT pulse width rejection threshold AtoD1 Level1 name of AtoD interface subcircuit DtoA1 Level 1 name of DtoA interface subcircuit AtoD2 Level 2 name of AtoD interface subcircuit DtoA2 Level 2 name of
459. the simulator to use the circuit wide level defined in the digital portion DC Sweep analysis of the Simulation Settings dialog box Specifying digital pow er supplies Digital power supplies are used to power interface subcircuits that are automatically created by PSpice A D when simulating analog digital interfaces They are specified as follows e PSpice A D can instantiate them automatically e You can create your own digital power supplies and place them in your design When using parts from the standard libraries in your design you can usually have PSpice A D automatically create the necessary digital power supply Because digital power supplies are used only by analog digital interface subcircuits digital power supplies are not needed for digital only designs OrCAD recommends avoiding placing a power supply to a digital only design because it may increase simulation time and memory usage Default power supply selection by PSpice A D When PSpice A D encounters an analog digital interface it creates the appropriate interface subcircuit and power supply according to the I O model referenced by the digital part The I O model is specific to the digital part s logic family The power supply provides reference or drive voltage for the analog side of the interface By default PSpice A D inserts one power supply subcircuit for every logic family in which a digital primitive is involved with an analog digital interface
460. then close the spreadsheet To set up and run the AC sweep simulation 1 From Capture s PSpice menu choose New Simulation Profile In the Name text box enter AC Sweep then click create The Simulation Settings dialog box appears Click the Analysis tab From the Analysis type list select AC Sweep Noise and enter the settings shown in Figure 19 Simulation Settings Example x General Analysis Include Files Libraries Stimulus Options Data Collection Probe Windows Analysis type AC Sweep Type AC Sweep Noise i C Linear Start Frequency fo Options Logarithmic End Frequency ficoMes General Settings E Mania Carnot Css Decade Point Decade T Parametric Sweep Temperature Sweep m Noise Analysis I Enabled Gutsut yolteoe lV Source a Interval al Cancel Apply Help Figure 19 AC sweep and noise analysis simulation settings AC sweep analysis 5 Click OK to close the Simulation Settings dialog box 6 From the PSpice menu choose Run to start the gt simulation PSpice A D performs the AC analysis To add markers for waveform analysis 1 From Capture s PSpice menu point to Markers point Note You must tirst detine a simulation to Advanced then choose db Magnitude of Voltage profile for the AC Sweep Noise analysis 2 Place one Vdb marker on the Out net then place in order to use advanced markers another on the Mid net 3 From the File menu
461. then configure for use with a given design 270 Creating a digital model using the PINDLY and LOGICEXP primitives Creating a digital model using the PINDLY and LOGICEXP nine F pri m itiv QS supported in PSpice A D bay Basics Unlike the majority of analog device types the bulk of digital devices are not primitives that are compiled into the simulator Instead most digital models are macro models or subcircuits that are built from a few primitive devices These subcircuits reference interface and timing models to handle the D to A and A to D interfaces and the overall timing parameters of the physical device For most families of digital components the interface models are already defined and available in the DIG_IO LIB library which is supplied with all digital and mixed signal packages If you are unsure of the exact name of the interface model you need to use use a text editor to look in DIG_IO LIB For instance if you are trying to model a 74LS component that is not already in a library open DIG_IO LIB with your text editor and search for 74LS to get the interface models for the 74LS family You can also read the information at the beginning of the file which explains many of the terms and uses for the I O models In the past the timing model has presented the greatest challenge when trying to model a digital component This was due to the delays of a component being distributed among the various gates Recently the ab
462. this case the instance model is identical to the original model If you decide to edit this model later be sure to do one of the following e Ifyou want the changes to remain specific to the current design edit the instance model in the design library using the Model Editor e Ifyou want the change to be global change the model To find out how to change model implementation for the part instance in your design references see Changing the model back to the original model name in the global library reference to an existing model and then edit the original model from within the part definition on page 4 159 editor 145 Chapter 4 Creating and editing models press P Di lt Dbreak v1 cot M G9 in ik YW 0 Figure 30 Design for a half wave rectifier 146 press The Model Editor tutorial In this tutorial you will model a simple diode device as follows Create the schematic for a simple half wave rectifier Run the Model Editor from the schematic editor to create an instance model for the diode in your schematic Creating the half wave rectifier design To draw the design 1 Note From the Project Manager from the File menu point to New then choose Project Enter the name of the new project RECTFR and click Create From Capture s Place menu choose Part Place one each of the following parts reference designator shown in parentheses as shown in Figure 30
463. tial transient bias point calculation SKIPBP Save Bias Point Load Bias Point Output File Options 6 Enter the necessary parameter values and select the appropriate check boxes to complete the analysis specifications Set up any other analyses you want to perform for the circuit by selecting any of the remaining analysis types and options then complete their setup dialog boxes Execution order for standard analyses For normal simulations that are run from a simulation profile or in batch mode only the particular analysis type that is specified will be executed During simulation of a circuit file the analysis types are performed in the order shown in Table 5 Each type of analysis is conducted only once per run Several of the analyses small signal transfer DC sensitivity and frequency response depend upon the bias point calculation Because so many analyses use the bias point PSpice A D calculates this automatically PSpice A D s bias point calculation computes initial states of digital components as well as the analog components Jable5 Execution order for standard analyses 1 o N ODO oF Q N DC sweep Bias point Frequency response Noise DC sensitivity Small signal DC transfer Transient response Fourier components Setting up analyses 291 Chapter 8 Setting up analyses and starting simulation 292 Output variables Certain analyses such as noi
464. tics A digital device model s input output characteristics are defined by the I O model that it references Some characteristics such as output drive resistance and loading capacitances apply to digital simulation Others such as the interface subcircuits and the power supplies apply only to mixed analog digital simulation This section describes in detail e theI O model e the relationship between drive resistances and output strengths e charge storage on digital nets e the format of the interface subcircuits Input Output model I O models are common to entire logic families For example in the model libraries there are only four I O models for the entire 74LS family IO_LS for standard inputs and outputs IO_LS_OC for standard inputs and open collector outputs IO_LS_ST for Schmitt trigger inputs and standard outputs and IO_LS_OC_ST for Schmitt trigger inputs and open collector outputs In contrast timing models are unique to each device I O models are specified as MODEL lt I O model name gt UIO model parameters where valid model parameters are described in Table 3 257 Chapter 7 Digital device modeling 258 INLD and OUTLD These are used in the calculation of loading capacitance which factors into the propagation delay discussed under timing models on Timing model on page 7 251 Note that INLD does not apply to stimulus generators because they have no input nodes DRVH and DRVL Thes
465. tification of timing hazards f this signal were used to clock another circuit it would become the reference and the effects of the phase shift could be ignored You can do this by setting the NAND gate s model parameter MNTYMXDLY 2 to utilize typical delay values for that one gate only all other devices continue to operate in worst case mode 465 Chapter 16 Digital worst case timing analysis 466 Reconvergence hazard PSpice A D recognizes situations where signals having a common origin reconverge on the inputs of a single device In Figure 108 the relative timing relationship between the two paths U2 U3 is important 25 60 TPLHMN 10 TPLHMX 30 DQ t 0 a a U4 gt 15 30 gt A TPLHMN 15 TPLHMN 40 TPLHMX 30 TPLH o a 55 90 Figure 108 Reconvergence hazard example one Given the delay values shown it is impossible for the clock to change before the data input since the MAX delay of the U2 path is smaller than the MIN delay of the U3 path In other words the overlap of the two ambiguity regions could not actually occur PSpice A D recognizes this type of situation and does not produce the overly pessimistic result of latching an X state into the Q output of U4 This factors out the 15 nsec of common ambiguity attributed to U1 from the U2 and U3 signals see Figure 109 U2 LZ 7 25 45 U3 A 55 75 Figure 109 Reconvergence hazard example two
466. time based input signal To specify the input signal itself Note The Stimulus Editor is AWA you need to use the Stimulus Editor See The Stimulus not included in PSpice A D ter Editor utility on page 11 346 Basics LX 117 Chapter 3 Preparing a design for simulation For the meaning of transient source properties refer to the I V independent current and voltage source device type syntax in the A nalog Devices chapter in the online OrCA D PSpice A D Reference Manual 118 If you want to spedfy multiple stimulus types If you want to run more than one analysis type including a transient analysis then you need to use either of the following e time based stimulus parts with AC and DC properties e VSRC or ISRC parts Using time based stimulus parts with AC and DC properties The time based stimulus parts that you can use to define a transient DC and or AC input signal are listed below VEXP TEXP VPULSE IPULSE VPWL IPWL VPWL_F_RE_FOREVER IPWL_F_RE_FOREVER VPWL_F_N_TIMES IPWL_F_N_TIMES VPWL_RE_FOREVER IPWL_RE_FOREVER VPWL_RE_N_TIMES IPWL_RE_N_TIMES VSFFM ISFFM VSIN ISIN In addition to the transient properties each of these parts also has a DC and AC property When you use one of these parts you must define all of the transient properties However it is common to leave DC and or AC undefined blank When you give them a value the syntax you need to use is as follows Table 15 This property Has this sy
467. to the Model Editor 2 For each custom part set its MODEL property to M where is a back single quote or grave character 175 Chapter 5 Creating parts for models This tells the Model Editor to substitute the correct model name To base new parts on custom parts using the Model Editor 1 Inthe Model Editor from the Options menu choose Part Creation Setup and enable automatic part creation as described in To automatically create parts for new models on page 5 174 2 Inthe Base Parts On frame enter the name of the existing part library OLB that contains your custom parts 3 Click OK 176 Editing part graphics If you created parts using the Model Editor and you want to make further changes the following sections explain a few important things to remember when you edit the parts How Capture places parts When placing parts on the schematic page the schematic page editor uses the grid as a point of reference for different editing activities The part s pin ends are positioned on the grid points Q S grid point S part body border 1 From Capture s File menu point to Open then choose Library To edit a part in a library 2 Select the library that has the part you want to edit The library opens and displays all its parts 3 Double click the part you want to edit The part appears in the part editor 4 Edit the part You can resize it add or delete graphics and add or delete pi
468. total number of points in the sweep in the Total Points box Under AC Sweep Type click Logarithmic select Decade default and enter the total number of points per decade in the Total Points box Under AC Sweep Type click Logarithmic select Octave and enter the total number of points per octave in the Total Points box 5 Inthe Start Frequency and End Frequency text boxes enter the starting and ending frequencies respectively for the sweep 6 Click OK to save the simulation profile AC sweep analysis AC sweep setup in example op If you look at the example circuit EXAMPLE OP provided with your OrCAD programs you ll find that its AC analysis is set up as shown in Figure 63 TERE RENAS 2 RCI 2 RC2 paca Note The source V1 is a VSIN source that i a le is normally used for setting up sine wave so JON 03 ws signals for a transient analysis It also has Ey YK cen wm an AC property so that you can use it for an ___ AC analysis rd ice Bee 3 To find out more about VSIN and other qm ff rian Sonn source symbols that you can use for AC analysis see Using time based O stimulus parts with AC and DC vE properties on page 3 118 Figure 62 Circuit diagram for EXAMPLE OPJ Frequency is swept from 100 kHz to 10 GHz by decades with 10 points per decade The V1 independent voltage source is the only input to an amplifier so it
469. ts Default digital power supplies Every digital part supplied in the OrCAD libraries has a default digital power supply defined for its A to D or D to A interface subcircuit This means that if you are designing a mixed signal circuit then you have a default 5 volt digital power supply built in to the circuit at every interface Custom digital power supplies If needed you can customize the power supply for different logic families Table 13 For this logic family Use this part CD4000 CD4000_PWR TTL DIGIFPWR ECL 10K ECL_10K_PWR ECL 100K ECL_100K_PWR Defining power supplies To find out how to use these parts and specify their digital power and ground pins see Specifying digital power supplies on page 15 449 115 Chapter 3 Preparing a design for simulation See Setting up a DC stimulus on page 9 310 for more details See Setting up an AC stimulus on page 10 325 for more details See Defining a time based stimulus on page 11 344 for more details 116 Defining stimuli To simulate your circuit you need to connect one or more source parts that describe the input signal that the circuit must respond to The OrCAD libraries supply several source parts that are described in the tables that follow These parts depend on e the kind of analysis you are running e whether you are connecting to the analog or digital portion of your circuit and e how you want to define the stimulus us
470. ts for another simulation To generate a test vector file from your circuit 1 Place a VECTORn part from the PSpice library SPECIAL OLB and connect it to a wire or bus at the output of a digital part instance 2 Double click the VECTORn part instance to display the Parts spreadsheet 3 Set the part properties as described below Table 20 For this property Define this POS Column position in the file Valid values range from 1 to 255 FILE Name of the vector file If left blank PSpice A D creates a file named SCHEMATIC _NAME VEC RADIX If the VECTOR part is attached to a bus the numerical notation for a bus Valid values are B inary O ctal and H ex BIT If the VECTOR part is attached to a wire the bit position within a single hex or octal digit SIGNAMES Names of the signals that appear in the header of the file If left blank PSpice A D defaults to the following e Fora wire the label name on the wire e Fora bus a name derived from the position of each signal in the bus from MSB to LSB Creating test vector files 4 Repeat steps 1 through 3 for as many test vectors as you want to create 539 Chapter 18 Other output options 540 Setting initial state Appendix overview This appendix includes the following sections e Save and load bias point on page A 542 e Setpoints on page A 544 e Setting initial conditions on page A 546 Chapter A Setting initial state Note Bia
471. ty is calculated by linearizing all devices around the bias point Purely digital devices hold the states calculated when solving for the bias point as discussed in Small signal DC transfer on page 9 317 321 Chapter9 DC analyses 322 AC analyses 10 Chapter overview This chapter describes how to set up AC sweep and noise analyses e AC sweep analysis on page 10 324 describes how to set up an analysis to calculate the frequency response of your circuit This section also discusses how to define an AC stimulus and how PSpice A D treats nonlinear devices in an AC sweep e Noise analysis on page 10 333 describes how to set up an analysis to calculate device noise contributions and total input and output noise Chapter 10 AC analyses To find out how see Setting up an AC stimulus on page 10 325 To find out how see Setting up an AC analysis on page 10 327 To find out more see How PSpice A D treats nonlinear devices on page 10 331 324 AC sweep analysis Setting up and running an AC sweep The following procedure describes the minimum setup requirements for running an AC sweep analysis For more detail on any step go to the pages referenced in the sidebars To set up and run an AC sweep 1 Place and connect a voltage or current source with an AC input signal 2 From the PSpice menu select New Simulation Profile or Edit Simulation Settings If this is a new simulation enter the name of the
472. ual paragraph describes a non Basics feature the icon is placed next to the paragraph The following table identifies which features are included with PSpice A D and PSpice A D Basics PSpice A D PSpice A D Feature standard Basics Benefits of integration with OrCAD Capture graphical design entry schematic capture yes yes simulation setup using dialog boxes yes yes cross probing yes yes multi window analysis of PSpice datasets yes yes marching waveforms in PSpice yes yes board layout package interfaces yes yes Notable PSpice analysis and simulation features DC sweep AC sweep transient analysis yes yes noise Fourier temperature analysis yes yes parametric analysis yes no If you don t have the standard PSpice A D package PSpice A D PSpice A D Feature standard Basics Monte Carlo sensitivity worst case yes no analysis analog behavioral modeling ABM yes yes propagation delay modeling yes no constraint checking such as setup and yes no hold timing digital worst case timing yes no charge storage on digital nets yes no Stimulus Editor yes no Parts utility yes no performance analysis goal functions yes no save load bias point yes no Notable PSpice devices and library models GaAsFETs Curtice Statz TriQuint all Statz Parker Skellern MOSFETs SPICE3 1 3 with charge yes yes conservation BSIM1 BSIM3 1 version 3 EKV version 2 6 IGBTs yes no JFETs BJTs yes yes resistor capacit
473. ude times the input voltage For AC analysis the input voltage is linearized around the bias point similar to EVALUE and GVALUE parts Modeling mathematical or instantaneous relationships on page 6 222 The output for each frequency is then the input times the gain times the value of the table at that frequency For transient analysis the voltage is evaluated at each time point The output is then the convolution of the past values with the impulse response of the frequency response These rules follow the standard method of using Fourier transforms We recommend looking at one or more of the references cited in Frequency domain device models on page 6 227 for more information Note The table s frequencies must be in order from lowest to highest The TABLE part provides one input and one output Example A device ELOFILT is used as a frequency filter The input to the frequency response is the voltage at net 10 The output is a voltage across nets 5 and 0 The table describes a low pass filter with a response of 1 0 dB for frequencies below 5 kilohertz and a response of 0 001 60 dB for frequencies above 6 kilohertz The phase lags linearly with frequency This is the same as a constant time delay The delay is necessary so that the impulse response is causal That is so that the impulse response does not have any significant components before time zero The FTABLE part in Figure 39 could be used Control system parts This
474. uding the term I Vsense will be output as I V_U1_Vsense if the voltage source exists locally and as I V_Vsense if the voltage source exists at the top level Forcing the use of a global definition If a net name exists both at the local hierarchical level and at the top level the search mechanism used by Capture will find the local definition You can override this and force Capture to use the global definition by prefixing the name with a single quote character For example suppose there is a net called Reference both inside hierarchical part U1 and at the top level Then the ABM fragment V Reference will result in V U1_Reference in the netlist while the fragment V Reference will produce V Reference Placing and specifying ABM parts 197 Chapter 6 Analog behavioral modeling For clarity the template is shown on three lines although the actual template is a single line 198 ABM part templates For most ABM parts a single PSpice A D E or G device declaration is output to the netlist per part instance The PSPICETEMPLATE property in these cases is straightforward For example the LOG part defines an expression variant of the E device with its output being the natural logarithm of the voltage between the input pin and ground E REFDES out 0 VALUE LOG V in The fragment EX REFDES is standard The E specifies a PSpice A D controlled voltage source E device in and out are the in
475. uit Data frame choose At Markers only and click OK 4 From the PSpice menu point to Markers then choose The color of the marker on the schematic the marker type you want to place page is the same as its corresponding waveform analysis trace If you change the color of the trace the color of the marker changes accordingly 5 Point to the wires or pins you wish to mark and click to place the chosen markers 6 Right click and select End Mode to stop placing markers 7 From the PSpice menu choose Run to start the simulation 491 Chapter 17 Analyzing waveforms Suppressing part of the data run also limits the size of the PSpice A D output file 492 Limiting file size by exduding internal subdrauit data By default PSpice A D saves data for all internal nodes and devices in subcircuit models in a design You can exclude data for internal subcircuit nodes and devices To limit file size by excluding data for internal subcircuits 1 From PSpice s Simulation menu choose Edit Simulation Settings to display the Simulation Settings dialog box General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window gt Schematic Circuit Data C All voltages currents and digital states C At Markers only C None I Save data in the CSDF format CSD Cancel Apply Help 2 Click the Data Collection tab 3 Inthe Schematic Circuit Data frame choose Al
476. uits viewing parts as a collection of primitive parts and node connections The digital primitives that make up a digital part determine the way that PSpice A D processes an analog digital interface to that part Specifically the I O model for each digital primitive connected at the interface gives PSpice A D the necessary information PSpice A D recognizes three types of nodes analog nodes digital nodes and interface nodes The node type is determined by the types of parts connected to it If all of the parts connected to a node are analog then it is an analog node If all of the parts are digital then it is a digital node If there is a combination of analog and digital parts then it is an interface node PSpice A D automatically breaks interface nodes into one purely analog and one or more digital nodes by inserting one or more analog digital interface subcircuits PSpice A D also automatically connects a power supply to the interface subcircuit to complete the generation of the interface To view simulation results at an analog digital interface in your schematic using the graphical waveform analyzer e Place a marker on the appropriate interface net The additional nodes created by PSpice A D remain transparent e View results in PSpice A D by selecting traces from the output variable list from the Trace menu choose Add Trace If you use this approach note the names PSpice A D generates for the new nodes Interfac
477. ulated parasitic capacitances Transient analysis Parasitic capacitances It is important that switching times be nonzero This is assured if devices have parasitic capacitances The semiconductor model libraries in PSpice have such capacitances If switches and or controlled sources are used then care should be taken to assure that no sections of circuitry can try to switch in zero time In practice this means that if any positive feedback loops exist such as a Schmidt trigger built out of switches then such loops should include capacitances Another way of saying all this is that during transient analysis the circuit equations must be continuous over time just as during the bias point calculation the equations must be continuous with the power supply level Inductors and transformers While the impedance of capacitors gets lower at high frequencies and small time steps the impedance of inductors gets higher Note The inductors in PSpice have an infinite bandwidth Real inductors have a finite bandwidth due to eddy current losses and or skin effect At high frequencies the effective inductance drops Another way to say this is that physical inductors have a frequency at which their Q begins to roll off The inductors in PSpice have no such limit This can lead to very fast spikes as transistors and diodes connected to inductors turn on and off The fast spikes in turn can force PSpice to take unrealistically small time
478. umentation This guide generally follows the conventions used in the Microsoft Windows User s Guide Procedures for performing an operation are generally numbered with the following typographical conventions Notation Examples Description Ctrl R Press Ctrl R A specific key or key stroke on the keyboard monospace Type VAC Commands text entered font from the keyborad Xxix Before you begin Related documentation Documentation for OrCAD products is available in both printed and online forms To access an online manual instantly you can select it from the Help menu in its respective program for example access the Capture User s Guide from the Help menu in Capture Note The documentation you receive depends on the software configuration you have purchased The following table provides a brief description of those manuals available in both printed and online forms This manual Provides information about how to use OrCAD Capture User s Guide OrCAD Layout User s Guide OrCAD PSpice A D amp Basics User s Guide OrCAD PSpice User s Guide OrCAD PSpice Optimizer User s Guide OrCAD Capture which is a schematic capture front end program with a direct interface to other OrCAD programs and options OrCAD Layout which is a PCB layout editor that lets you specify printed circuit board sturcture as well as the components metal and graphics required for fabrication
479. ure 58 the voltage source V1 is swept from 0 125 volts to 0 125 volts by steps of 0 005 This means that the output has 0 125 0 125 0 005 1 51 steps or simulation points A source with a DC specification such as VDC or IDC must be used if the swept variable is to be a voltage type or current source To set the DC value select Properties from the Edit menu then click on the cell under the DC column and type in its value The default DC value of V1 is overridden during the DC sweep analysis and is made to be the swept value All of the other sources retain their values After running the analysis the simulation output file EXAMPLE OUT for the EXAMPLE OPJ circuit in Figure 58 contains a table of voltages relating V1 node OUT1 and node OUT2 VOU Pe readme REIAS RCI RC2 example rdm ik Z ik a CLOAD OUTI 4 Jourz RS2 saat gee eens dee anma k e af A Qi at O O q212222 ad Fa q212222 moo VEE d VEE Figure 58 Example schematic EXAMPLE OPJ To calculate the DC response of an analog circuit PSpice A D removes time from the circuit This is done by treating all capacitors as open circuits all inductors as shorts and using only the DC values of voltage and current sources A similar approach is used for digital devices all propagation delays are set to zero and all stimulus generators are set to their time zero values In
480. urrent GEESE Diode a wiwa wwa l Foward Cur JE Junction Ca G Reverse Le fE Reverse Br E Reverse Re OAAAAAAAAAAAN AN FERRERS EB 0 3333 manmanan Tn TRA z FREESFS z Figure 31 Model characteristics and parameter values for Dbreakx Using the Model Editor to edit models 147 Chapter 4 Creating and editing models 148 You can modify each model characteristic shown in the Model Spec frame with new values from the data sheets The Model Editor takes the new information and fits new model parameter values When updating the entered data the Model Editor expects either e device curve data point pairs or e single valued data depending on the device characteristic For the diode Forward Current Junction Capacitance and Reverse Leakage require device curve data Reverse Breakdown and Reverse Recovery require single valued data Table 1 lists the data sheet information for the Dbreak X model Table1 Sample diode data sheet values For this model characteristic Enter this forward current 1 3 0 2 junction capacitance 1m 120p 1 73p 3 75 45p reverse leakage 6 20n reverse breakdown Vz 7 5 Iz 20m Zz 5 reverse recovery no changes To change the Forward Current characteristic 1 Inthe Spec Entry fr
481. ursor to the closest trace segment at the X position Right click in the display Move the second cursor to area the closest trace segment at the X position To move cursors along a trace using the keyboard 1 Use key combinations as described in Table 3 below Table3 Key combinations for cursor control Us this key combination To do this with the cursors Ctri He and Ctri gt Change the trace associated with the first cursor Shift Ctrl and Change the trace associated with the Shift Ctrl gt second cursor lt and Move the first cursor along the trace Shift lt and Shift gt Move the second cursor along the trace User interface features for waveform analysis Table3 Key combinations for cursor control continued Us this key combination To do this with the cursors Home Move the first cursor to the beginning of the trace Shift Home Move the second cursor to the beginning of the trace End Move the first cursor to the end of the trace Shift End Move the second cursor to the end of the trace Example using cursors Figure 122 shows both cursors positioned on the Out signal in the digital area of a plot and both cursors on the V 1 waveform in the analog area of the plot digital signal w cursors cursor 1 results cursor 2 results analog waveform w cursors Figure 122 Cur
482. use the simulation of signal propagation through the network to observe the timing relationships among various devices and make adjustments to the design Digital worst case timing simulation does not yield such results without an applied stimulus it is not a static timing analysis tool The level of confidence that you Methodology Note Glitch suppression can be overridden by setting the pulse width rejection threshold parameter TPWRT in the device s I O Model This is not intended to be a comprehensive discussion of the application of digital worst case timing simulation in the design process Rather it is a suggested starting point for understanding the results of your simulation 469 Chapter 16 Digital worst case timing analysis For example if you were designing a digital ADDER circuit you would probably want to ensure that no timing race conditions existed in the carry logic For example in the case of a convergence or reconvergence hazard look for conflicting rise fall inputs In the case of cumulative ambiguity look for successive ambiguity regions merging within two edges forming a pulse 470 establish for your design s timing dependent characteristics is directly a function of the applied stimulus Generally the most productive way to define a stimulus is to use functional testing a stimulus designed to operate the design in a normal manner exercising all of the important features in combinatio
483. ut noise units Table 9 This type of noise output variable Is reported in these units Device contribution of the form 2 Nxxx volts Hz Total input or output noise of the form V ONOISE or V INOISE volts JHz Example You can run a noise analysis on the circuit shown in Figure 62 on page 10 329 To run a noise analysis on the example In Capture open the EXAMPLE DSN circuit provided with your OrCAD programs in the ORCAD CAPTURE SAMPLES subdirectory 1 From the PSpice menu choose New Simulation Profile or Edit Simulation Settings If this is a new simulation enter the name of the profile and click OK The Simulation Settings dialog box appears 2 Choose AC Sweep Noise in the Analysis type list box 3 Under Options select General Settings if it is not already enabled 4 Enable the Noise Analysis check box 5 Enter the following parameters for the noise analysis Output Voltage V OUT2 I V Source V1 Interval 30 These settings mean that PSpice A D will calculate noise contributions and total output noise at net OUT2 and equivalent input noise from V1 Figure 63 shows Probe traces for Q1 s constituent noise sources as well as total nose for the circuit after simulating Notice that the trace for RMSSUM at the top of the plot which is a macro for the trace expression SQORT NTOT Q1 NTOT Q2 NTOT Q3 exactly matches the total output noise V ONOISE calculated by PSpice A D
484. utomatically generates are listed in the simulation output file under the section named Generated AtoD and DtoA Interfaces For the example in Figure 96 this section would appear in the simulation output file as shown in Figure 97 below Interface generation and node names 455 Chapter 15 Mixed analog digital simulation DIGIFPWR creates the global nodes G_DPWR and G_DGND which are the default nodes used by each TTL part 456 k Generated AtoD and DtoA Interfaces Analog Digital interface for node 1 Moving X1 U1 A from analog node 1 to new digital node 1 AtoD X 1_AtoD1 1 1 AtoD G_DPWR G_DGND AtoD_STD PARAMS CAPACITANCE 0 Moving X2 U1 A from analog node 1 to new digital node 1 AtoD2 X 1_AtoD2 1 1 AtoD G_DPWR G_DGND AtoD_STD PARAMS CAPACITANCE 0 Analog Digital interface for node 2 Moving X1 U1 Y from analog node 2 to new digital node 2 DtoA X 2_DtoAl 2 DtoA 2 G_DPWR G_DGND DtoA_STD PARAMS DRVL 0 DRVH 0 CAPACITANCE 0 Analog Digital interface power supply subcircuit X DIGIFPWR O DIGIFPWR END end of AtoD and DtoA interfaces Figure 97 Simulation output for mixed analog digital circuit The lines that begin with Moving from analog node indicate the new digital node names that were generated Below each of these are the interface subcircuit calls inserted by PSpice A D In this example the subcircuits named
485. ve 106 DIGIFPWR power supply 456 logic propagation delay selection 428 LOGICEXP primitive 106 PINDLY primitive 106 Index vendor supplied 101 digital primitives 243 272 input N device 266 output O device 266 propagation delays see timing model syntax 246 timing model see timing model digital simulation messages 437 propagation delays see timing model states 262 411 strengths 262 timing model see timing model vector file 538 waveform display 500 527 530 worst case timing 458 digital values 411 digital worst case timing 458 compared to analog worst case 458 convergence hazard 439 cumulative ambiguity hazard 439 glitch suppression 439 DIGMNTYMxX simulation option 459 DIGMNTYSCALE simulation option 252 DIGOVRDRV simulation option 264 DIGPOWER I O model 258 DIGSTIM digital stimulus part 119 414 DIGTYMXSCALE simulation option 252 diodes 137 295 526 DRVH I O model parameter 456 DRVH I O model 258 263 DRVL I O model parameter 456 DRVL I O model 258 263 DRVZ I O model 258 DtoA interface see mixed analog digital circuits dynamic range of time 557 E ECL_100K_PWR digital power part 115 ECL_10K_PWR digital power part 115 EGND ground part 124 examples and tutorials AC sweep analysis 77 329 analog waveform analysis 495 bias point detail analysis 62 creating a digital model 280 DC sweep analysis 66 example circuit creation 56 565 Index
486. view 2645248 Cs ee te Soh eRe REE ESE EES Overview of transient analysis 6 2 eee eee Minimum requirements to run a transient analysis Minimum circuit design requirements Minimum program setup requirements Defining a time based stimulus 00 4 Overview of stimulus generation 4 The Stimulus Editor utility 4 hs eo 6 ow bw eed oe ew Stimulus files 0 kE ER EES RER Configuring stimulus files aoaaa Starting the Stimulus Editor aoaaa a Defining stimuli hee Peewee eee RES Pe eR aS Example piecewise linear stimulus Example sine wave sweep 644 e42446 hee ee een Creating new stimulus symbols Editing a stimulus pie ete Pha Pe Saree ae Be Be 2S To edit an existing stimulus 264 4214 0s ee ws eee es ToeditaPWLstimulus 04 Contents 334 341 342 342 342 342 344 344 346 346 347 347 349 349 350 352 353 353 353 xi Contents To select a time and value scale factor for PWL stimuli 353 Deleting and removing traces 2 cs aes 4aw Ge 4d eee a ee 354 Manual stimulus configuration 00 000004 354 To manually configure astimulus 354 Transient time response 4 oa ne yc wee 6 See RASS SE a Pe ES 356 Internal time steps in transient analyses 000 358 Switching circuits in transient analyses 0 359 Pl
487. view the trace data values table 1 Select one or more Ghift click trace names Selected trace names are highlighted From the Edit menu choose Copy or Cut to save the trace data point values to the Clipboard Cut removes traces from the Probe window In Clipboard Viewer from the Display menu choose either Text or OEM Text To export the data points to other applications 1 4 Select one or more Ghift click trace names Selected trace names are highlighted From the Edit menu choose Copy or Cut to save the trace data point values to the Clipboard Cut removes traces from the Probe window Paste the data from the Clipboard into a text editor a spreadsheet program or a technical computing program such as Mathcad Save the file Using cursors When one or more traces are displayed you can use cursors to display the exact coordinates of two points on the same trace or points on two different traces In addition differences are shown between the corresponding coordinate values for the two cursors Displaying cursors To display both cursors 1 From the Trace menu point to Cursor then choose Display The Probe Cursor window appears showing the current position of the cursor on the x axis and y axis As you move the cursors the values in the cursor box change In the analog area of the plot if any both cursors are initially placed on the trace listed first in the trace legend The corre
488. vioral modeling There are no equivalent F or H part types in the part library becayse PSpice A D F and H devices do not support the ABM extensions 220 PSpice A D equivalent parts PSpice A D equivalent parts respond to a differential input and have double ended output These parts reflect the structure of PSpice A D E and G devices thus having two pins for each controlling input and the output in the part Table 1 summarizes the PSpice A D equivalent parts available in the part library Tablel PSpice A D equivalent parts Category Part Description Properties Mathematical EVALUE general purpose EXPR expression GVALUE ESUM special purpose none GSUM EMULT GMULT Table look up ETABLE general purpose EXPR GTABLE TABLE Frequency EFREQ general purpose EXPR table look up GFREQ TABLE Laplace ELAPLACE general purpose EXPR transform GLAPLACE XFORM PSpice A D equivalent ABM parts can be classified as either E or G device types The E part type provides a voltage output and the G device type provides a current output The device s transfer function can contain any mixture of voltages and currents as inputs Hence there is no longer a division between voltage controlled and current controlled parts Rather the part type is dictated only by the output requirements If a voltage output is required use an E part type If a current output is necessary use a G part type PSpice A D equ
489. w models then folder then choose Model Editor 1 Save the opened model library 2 From the File menu choose New or Open and enter an existing or new model library name 2 Open or create a different model library 3 From the Part menu choose New Copy From or Import to load a model 3 Get a model or create a new one 141 Chapter 4 Creating and editing models Instead of using the OrCAD default part set for new models you can have the Model Editor use your own set of standard parts To find out more see Basing new parts on a custom set of parts on page 5 175 Example If the model library is MYPARTS LIB then the Model Editor creates the part library MYPARTS OLB If you want to save the open model library to a new library then 1 From the File menu choose Save As 2 Enter the name of the new model library If you want to save only the model definition that you are currently editing to a different library then 1 From the Part menu select Export 2 Enter the name of the new file 3 If you want PSpice A D to search this file automatically configure it in Capture using the Libraries tab on the Simulation Settings dialog box 142 Enabling and disabling automatic part ceation Part creation in the Model Editor is optional By default automatic part creation is enabled However if you previously disabled part creation you will need to enable it before creating a new model and part To automat
490. weep 553 derivatives 550 diagnostics 561 dynamic range of time 557 inductors and transformers 559 Newton Raphson requirements 548 parasitic capacitances 559 semiconductors 553 switches 554 transient analysis 556 Create Subcircuit command 133 157 current source controlled 220 239 cursors waveform analysis 513 custom part creation for models 175 using the Model Editor 142 173 D Darlington model transistors 137 DC analyses displaying simulation results 68 see also DC sweep analysis bias point detail analysis small signal DC transfer analysis DC sensitivity analysis DC sensitivity analysis 288 320 introduction 43 DC stimulus property 311 DC sweep analysis 288 306 about 308 curve families 313 example 66 introduction 43 nested 311 setting up 66 stimulus 310 DELAY stimulus property digital 422 derivative problems 550 design preparing for simulation 49 96 device noise 334 337 total 337 diagnostic problems 561 differentiators ABM 199 206 DIG_GND stimulus property digital 423 DIG_PWR stimulus property digital 423 DIGCLOCK digital stimulus parts 119 413 422 DIGDRVF strengths 264 DIGDRVZ strengths 264 DIGERRDEFAULT simulation option 440 DIGERRLIMIT simulation option 440 DIGIFPWR digital power part 115 DIGIOLVL simulation option 249 digital models 271 digital parts G_DGND reserved global net 456 G_DPWR reserved global net 456 CONSTRAINT primiti
491. where detailed status information about the simulation are shown These three sections are shown in Figure 56 The windows in these sections may be resized moved and reordered as needed The simulation window also includes a menu bar and toolbars for controlling the simulation and the waveform display Title bar The title bar of the simulation window the area at the top of the window identifies the name of the currently open simulation either simulation profile or circuit file and the name of the currently active document displayed in the main window area For example the simulation window shown in Figure 56 indicates that simulation profile Example TRAN is currently open and the active document displayed is Example Example TRAN DAT Menus and Toolbars The menus accessed from the menu bar include commands to set up and control the simulator customize the window display characteristics and configure the way the waveforms are displayed The toolbar buttons duplicate many of the more frequently used commands Example TRAN OrCAD PSpice A D _ example E xample TRAN dat active B File Edit View Simulation Trace Plot Tools Window Help sje x Besra PS eles 4447 rout gt ai amp a amp Q t s E m E S t lAM eae ee e 6 5U 7 7 Time step 19 25E 09 Time 1 000 06 End 1 000E 06 Analysis A WATER Devices For Help press F
492. with the inductor Convergence and time step too small errors Appendix overview This appendix discusses common errors and convergence problems in PSpice e Introduction on page B 548 e Bias point and DC sweep on page B 553 e Transient analysis on page B 556 e Diagnostics on page B 561 Chapter B Convergence and time step too small errors The ACand noise analyses are linear and do not use an iterative algorithm so the following discussion does not apply to them Digital devices are evaluated using boolean algebra this discussion does not apply to them either 548 Introduction In order to calculate the bias point DC sweep and transient analysis for analog devices PSpice must solve a set of nonlinear equations which describe the circuit s behavior This is accomplished by using an iterative technique the Newton Raphson algorithm which starts by having an initial approximation to the solution and iteratively improves it until successive voltages and currents converge to the same result In a few cases PSpice cannot find a solution to the nonlinear circuit equations This is generally called a convergence problem because the symptom is that the Newton Raphson repeating series cannot converge onto a consistent set of voltages and currents The following discussion gives some background on the algorithms in PSpice and some guidelines for avoiding convergence problems The transient analysis has the
493. with variable width pins template For a digital stimulus device template such as that for a DIGSTIM part a pin name can be preceded by a character This signifies that the pin can be connected to a bus and the width of the pin is set to be equal to the width of the bus Template Note For clarity the PSPICETEMPLATE property value is shown here in multiple lines in a part definition it is specified in one line no line breaks U REFDES STIM S PIN 0 PIN n STIMULUS STIMULUS where PIN refers to a variable width pin Sample translation U_U1 STIM 4 0 5PIN1 SPIN2 SPIN3 PIN4 STIMULUS mystim where the stimulus is connected to a four input bus a 0 3 Pin callout in subcircuit templates The number and sequence of pins named in a template for To find out how to define subdrcuits refer a subcircuit must agree with the definition of the to the SUBCKT command in the online subcircuit itself that is the node names listed in the OrCA D PSpice A D Reference SUBCKT statement which heads the definition of a Manual subcircuit These are the pinouts of the subcircuit Example Consider the following first line of a hypothetical subcircuit definition SUBCKT SAMPLE 10 3 27 2 The four numbers following the name SAMPLE 10 3 27 and 2 are the node names for this subcircuit s pinouts Now suppose that the part definition shows four pins IN OUT IN OU T The number of pins on the par
494. wn of noise output variables by supported device type see Table 11 on page 17 526 To view this Use this output variable Which is represented by this equation Flicker noise for a device Shot noise for a device Thermal noise for the RB RC RD RE RG or RS constituent of a device respectively Thermal noise generated by equivalent resistances in the output of a digital device Total noise for a device Total output noise for the circuit RMS summed output noise for the circuit Equivalent input noise for the circuit NFID device_name NFIB device_name NSID device_name NSIB device_name NSIC device_name NRB device_name NRC device_name NRD device_name NRE device_name NRG device_name NRS device_name NRLO device_name NRHI device_name NTOT device_name NTOT ONOISE V ONOISE V INOISE a I H For diodes and BJTs noise 2q For GaAsFETs JFETs and MOSFETs noise kp dI 2 noise 4kT W 3 noise des R noise 4kT R Sum of all contributors in device_name y NTOT device device RMS sum of all contributors JNTOT ONOISE V ONOISE gain To find out more about the equations that describe noise behavior refer to the appropriate device type in the A nalog Devices chapter in the OrCAD PSpice Reference Manual 337 Chapter 10 AC analyses For a description of the Interval parameter see page 10 336 338 Abo
495. xample the default model library is MY LIB If MY LIB does not already exist the Model Editor creates and saves it in the current working directory The schematic page editor then automatically configures it as a design model library for use with the current design only Now you are ready to set up and run the Monte Carlo analysis Using the Create Subcircuit command The Create Subcircuit command creates a subcircuit netlist definition for the displayed level of hierarchy and all lower levels in your design The schematic page editor does the following things for you e Maps any named interface ports at the active level of hierarchy to terminal nodes in the PSpice SUBCKT statement e Saves the subcircuit definition to a file named DESIGN_NAME SUB Using the Create Subcircuit command If you verify the model library configuration in the Simulation Settings dialog box click the Libraries tab you see entries for NOM LIB for global use as denoted by the asterisk and MY LIB for design use no asterisk in the Library files list You can change the model reference for this part back to the original Q2N2222 by following the procedure To change model references for part instances on your design on page 4 159 The Create Subcircuit command does not help you create a hierarchical design You need to do this yourself before using the Create Subcircuit command For information on hierarchical designs and how to creat
496. ymbols you can place on your schematic to generate additional information to the PSpice output file PSpice window and to digital test vector files Analyzing waveforms 17 Chapter overview This chapter describes how to perform graphical waveform analysis of simulation results in PSpice A D This chapter includes the following Overview of waveform analysis on page 17 476 Setting up waveform analysis on page 17 480 Viewing waveforms on page 17 483 Analog example on page 17 497 Mixed analog digital tutorial on page 17 500 User interface features for waveform analysis on page 17 505 Tracking digital simulation messages on page 17 517 Trace expressions on page 17 519 Chapter 17 Analyzing waveforms 476 Overview of waveform analysis You can use the waveform analysis features of PSpice A D to visually analyze and interactively manipulate the waveform data produced by circuit simulation PSpice A D uses high resolution graphics so you can view the results of a simulation both on the screen and in printed form On the screen waveforms appear as plots displayed in Probe windows within the PSpice A D workspace In effect waveform analysis is a software oscilloscope Performing a PSpice A D simulation corresponds to building or changing a breadboard and performing waveform analysis corresponds to looking at the breadboard with an oscilloscope With waveform analysis you can e View simulation results
497. yntax convention Click one of the following e Add to Design for design models e Add as Global for global models How PSpice A D uses model libraries PSpice A D searches libraries for any information it needs to complete the definition of a part or to run a simulation If an up to date index does not already exist PSpice A D automatically generates an index file and uses the index to access only the model definitions relevant to the simulation This means Disk space is not used up with definitions that your design does not use There is no memory penalty for having large model libraries Loading time is kept to a minimum Search order When searching for model definitions PSpice A D scans the model libraries using these criteria design model libraries before global model libraries model library sequence as listed in the Libraries tab of the Simulation Settings dialog box local directory where the current design resides first then the list of directories specified in the library search path in the order given see Changing the library search path on page 4 167 Configuring model libraries Caution When you use include files instead PSpice A D treats model library and include files differently as follows e For model library files PSpice A D reads in only the definitions it needs to run the current simulation e For include files PSpice A D reads in the file in its entirety This meansif
498. you to provide the necessary parameters such as the rise time fall time and period of an analog repeating pulse or the complex timing relations with repeating segments of a digital stimulus Graphical feedback allows you quickly verify the waveform Stimulus files The Stimulus Editor produces a file containing the stimuli with their transient specification These stimuli are defined as simulator device declarations using the V voltage source I current source and U STIM digital stimulus generator forms Since the Stimulus Editor produces these statements automatically you will never have to be concerned with their syntax However if you are interested in a detailed description of their syntax see the descriptions of V and I devices in the Analog Devices chapter and stimulus generator in the Digital Devices chapter of the the online OrCAD PSpice A D Reference Manual Configuring stimulus files The Include Files tab in the Simulation Settings dialog box allows you to view the list of stimulus files pertaining to your current schematic You can also manually add delete or change the stimulus file configuration in this tab dialog box The list box displays all of the currently configured stimulus files One file is specified per line Files can be configured as either global to the Capture environment or local to the current design Global files are marked with an asterisk after the file name When starting the Stimulus Ed
499. yses is set to 35 C The values for resistors RC1 and RC2 are recomputed based upon the CRES model which has parameters TC1 and TC2 reflecting linear and quadratic temperature dependencies Likewise the Q3 and Q4 device values are recomputed using the Q2N2222 model which also has temperature dependent parameters In the simulation output file these recomputed device values are reported in the section labeled TEMPERATURE ADJUSTED VALUES readme Raids RCH RC2 example rdm 2 ik ik a CLOAD oun d Jout RSI YN RS2 S o2 03 y Gee 4212222 tk T q J ba d a4 at 2 SERS 202222 ad 4212222 CS m E o VEE Figure 75 Example schematic EXAMPLE OPJ Monte Carlo and sensitivity worst case analyses 13 Chapter overview This chapter describes how to set up Monte Carlo and AWA Note This entire chapter sensitivity worst case analyses and includes the bea describes features that are following sections VE not induded in PSpice A D e Statistical analyses on page 13 376 Basics e Monte Carlo analysis on page 13 381 e Worst case analysis on page 13 398 Chapter 13 Monte Carlo and sensitivity worst case analyses Note Statistical analyses are not supported in PSpice A D Basics N Generating statistical results Asthe number of Monte Carlo or worst case runs increases simulation takes longer and the data file gets
500. ysis PSpice A D interprets text in curly braces as an expression that evaluates to a numerical value This example uses the simplest form of an expression a constant The value of R1 will take on the value of the Rval parameter whatever it may be Note For more information about using the Parts spreadsheet see the OrCAD Capture User s Guide This example is only interested in the magnitude of the response 83 Chapter 2 Simulation examples To set up and run a parametric analysis to step the value of R1 using Rval 1 From Capture s PSpice menu choose New Simulation Profile The New Simulation dialog box appears 2 Inthe Name text box type Parametric The root schematic listed is the schematic 3 From the Inherit From list select AC Sweep then click page associated with the simulation profile Create JO areen The Simulation Settings dialog box appears 4 Click the Analysis tab 5 Under Options select Parametric Sweep and enter the settings as shown below This profile specifies that the parameter Rval is to be stepped from 100 to 10k logarithmically with a resolution of 10 General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window Analysis type r Sweep variable 7 points per decade Time Domain Transient C Voltage source Hame or Current source a ree The analysis is run for each value of Rval 2 a ommpop Coe I z General Settings M
501. ysis specifications 3 Click OK to save the simulation profile 4 In Capture from the PSpice menu select Run to start the simulation Overview of bias point The bias point is calculated for any analysis whether or Also see Save and load bias point not the Bias Point analysis is enabled in the Simulation on page A 542 Settings dialog box However additional information is reported when the Bias Point analysis is enabled When Bias Point analysis is not enabled only analog node voltages and digital node states are reported to the output file 315 Chapter9 DC analyses 316 When the Bias Point analysis is enabled the following information is reported to the output file a list of all analog node voltages a list of all digital node states the currents of all voltage sources and their total power a list of the small signal parameters for all devices If Bias Point is enabled you can suppress the reporting of the bias point analog and digital node values as follows 1 Under the Options tab in the Simulation Settings dialog box select Output file in the Category box Uncheck the box for Bias point node voltages NOBIAS Simulation Settings Bias Point x General Analysis Include Files Libraries Stimulus Options Data Collection Probe Window Category Analog Simulation Gate level Simulation Include the following in the output OUT file Detailed summary and accounting i
502. zed The key concepts behind model organization are as follows e Model definitions are saved in files called model libraries e Model libraries must be configured so that PSpice A D searches them for definitions e Depending on the configuration model libraries are available either to a specific design or to all global designs Model libraries Device model and subcircuit definitions are organized into model libraries Model libraries are text files that contain one or more model definitions Typically model library names have a LIB extension Most model libraries contain models of similar type For vendor supplied models libraries are also partitioned by manufacturer To find out more about the models contained in a model library read the comments in the file header Model library configuration PSpice A D searches model libraries for the model names specified by the MODEL implementation for parts in your design These are the model definitions that PSpice A D uses to simulate your circuit For PSpice A D to know where to look for these model definitions you must configure the libraries This means e Specifying the directory path or paths to the model libraries e Naming each model library that PSpice A D should search and listing them in the needed search order e Assigning global or design scope to the model library Global vs design models and libraries Model libraries and the models they contain have

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