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Open On-Chip Debugger: OpenOCD User's Guide

1. 065 65 124 3 strOxpec dEIVer cuo eraa Di Sees hoes E See Paks 12 12 9 AME EE 73 12 5 1 mFlash Configuration 0 00 cece eee eee 73 12 5 2 mFlash commande 74 13 NAND Flash Commands 75 13 1 NAND Configuration Commandes 75 13 2 Erasing Reading Writing to NAND Flash 76 13 8 Other NAND commande 78 13 4 NAND Driver List 79 14 PLD FPGA Commaands 81 14 1 PLD FPGA Configuration and Commands 81 14 2 PLD FPGA Drivers Options and Commands 81 15 General Commands 82 15 1 Daemon Commandes 82 15 2 Target State handling 0 0 cece eens 83 15 3 I O DOllies ebbe ERE pE a Red 84 15 4 Memory access Commande 85 15 5 Image loading commande 86 15 6 Breakpoint and Watchpoint commande 87 15 7 Mise Commands lt lt eR Ga bie ieee nads ERG 87 16 Architecture and Core Commands 88 16 1 ARM Hardware Iracmng eee eee eens 88 16 1 1 ETM Configuration 0 0 c eee eee eee 88 16 1 2 ETM Trace Operation 90 16 1 3 Trace Port Drivers 0 cee 91 16 22 Generic ARM uua cages bes span Ra GGG i ANE Ra Gd 92 16 3 ARMv4 and ARMv5 Architecture 92 16 3 1 ARM7 and ARMO specific commands 93 16 3 2 ARM720T specific commande 93 16 8 3 ARMSO specific commande 93 16 3 4 ARM920T specific commande 94 16 3 5 ARM926ej s specif
2. 100 targetsogole seii e 9 kp hp peer E REPE 53 Dol POLE vidi 06e de Saleen ane eee sea ae 30 telnet POL sv eb dup ee dr quier e dewalt airy 30 test EE 86 SATO sci eem ek x tc ue Pp e E n 71 tms470 Tlasebh kerser TL tms470 oscmbhz eee eee AE tms4 Oplldis e Rene lee eoe 71 trace history e Ae sarees 100 Command and Driver Index trace polnt i REENERT transport iSt e gg Sgr EEN transport select ege ceca ct ketene anes USD blaster ize ar ee eae eed ad usb blaster device desc usb blaster vid pid e ENEE ss sbprog sosveisge a ache EE ERR ae reser e o eda v Verify image sva aee ee RE CA deer E verify ircapbure i eege Se verify Jt ag ic ies ep bRpeY aae d petu Ped d s VETS VOD jo 5 cb C VIFC2PDY Sits stots a he dente bake dashes dae ihe Dreeqdusts VILTUCK2 EEN virtex2 read stat cce virt dl ijoseessessr eeur eU See e Ge Vd E EECH 135 W wait halt rttr EENEN EEEE YU REIS 83 vp MEOm 87 X xscale analyze tLrace esses 96 xscale cache clean address 96 xscale cache info esses 96 Cake pg geg de Seege gr rp ned 96 xscale dcach itenei Meenas aaa tt ea E 96 xscale debug handler sssess 96 xscale dump trace e e atiro nrs 96 xscale Gcache ij2o 62vpoe ipee p DR 96 xScal MMU Soc pee db ubeaiescza xe dae yu dades 96 xscale trace buffer e ee eee 96 xscale trace i
3. xscale icache enable disable Command Enables or disable the CPU s instruction cache xscale mmu enable disable Command Enables or disable the CPU s memory management unit xscale trace buffer enable disable fill n wrap Command Displays the trace buffer status after optionally enabling or disabling the trace buffer and modifying how it is emptied Chapter 16 Architecture and Core Commands 97 xscale trace image filename offset type Command Opens a trace image from filename optionally rebasing its segment addresses by offset The image type may be one of bin binary ihex Intel hex elf ELF file s19 Motorola s19 mem or builder xscale vector catch mask Command Display a bitmask showing the hardware vectors to catch If the optional parameter is provided first set the bitmask to that value The mask bits correspond with bit 16 23 in the DCSR 0x01 Trap Reset 0x02 Trap Undefined Instructions 0x04 Trap Software Interrupt 0x08 Trap Prefetch Abort 0x10 Trap Data Abort 0x20 reserved 0x40 Trap IRQ 0x80 Trap FIQ xscale vector table low high index value Command Set an entry in the mini IC vector table There are two tables one for low vectors at 0x00000000 and one for high vectors OxFFFF0000 each holding the 8 exception vectors index can be 1 7 because vector 0 points to the debug handler entr
4. M 85 e ww e up Pes hace Fade Pe e ndn Prades 64 cortex m3 maskisr cesses 98 cortex m3 reset config 99 cortex m3 vector catch 99 CD attest onl tia timidi aap Astana 85 D dap apid oce ei mt EPI Re gee eel ees 98 dap apsal Lee t ee6ePeeteierTqqer de 98 dap baseaddr o occorre IQ E i 98 dap Int o suds i laden ee ee I e e RP T EETS 98 dap imemaccess wercci pericu ecem Peepewute 98 CAVING 56 b 9 0 9 QiUP Ie e Od EPA CPP PEE ed 80 debug level uen eR RI PR er iEn 82 OLS CAM hs densa gta auth arate eter lee eS 101 EE 34 91 dump image 2elessheenefeerbbessbeete pIves 86 E echO s nsexkaeaeersrmi eh doe RE bela EG EE UR 83 ecosflash e rr RERERRDE RE mee ERU 67 GpOSXXo lib b idee eke EE 34 OED EET 91 etD CODf Ig ess ee ae 91 etb trigger Dercent esses 91 etm analyze snb mid b peWe SEES tees 90 etm COnfig iccensess be ries ehd bra isinira Red 88 etm dump EE 90 Command and Driver Index etm Image oae sep Hie a Ad dae da Rue 90 etm infO essereiederweasd pea qoe rand a RES 89 etm Load oor tatus SE nie qu NE e iae 90 eim Sb aD ved pue Ded pred epe 2 90 etm Statussicoceleewes ni ERR Ex Fen RE 89 etm SLOp bewece Rer a b ue ce P PPP ES 90 etm tracemode i eise uad ed v E EY ee 89 etm trigger deiug 0 cece eee eee 89 etm dummy COnfYE 9 re res 91 SXIU o El Eet ties duae 82 F EE KEE 86 fast load image e eene ise 86 flash bark 2
5. run Let the target run halt Immediately halt the target init Immediately halt the target and execute the reset init script soft_reset_halt Command Requesting target halt and executing a soft reset This is often used when a target cannot be reset and halted The target after reset is released begins to execute code OpenOCD attempts to stop the CPU and then sets the program counter back to the reset vector Unfortunately the code that was executed may have left the hardware in an unknown state 15 3 I O Utilities These commands are available when OpenOCD is built with enable ioutil They are mainly useful on embedded targets notably the ZY1000 Hosts with operating systems have complementary tools Note there are several more such commands Chapter 15 General Commands 85 append file filename string Command Appends the string parameters to the text file filename Each string except the last one is followed by one space The last string is followed by a newline cat filename Command Reads and displays the text file filename cp src_filename dest filename Command Copies contents from the file src filename into dest filename ip Command No description provided ls Command No description provided mac Command No description provided meminfo Command Display available RAM memory on OpenOCD host Used in OpenOCD regression testing scripts peek Command No descriptio
6. Using this method has the advantage of GDB starting stopping OpenOCD for the debug session log output sends the log output to a file to ensure that the pipe is not saturated when using higher debug level outputs To list the available OpenOCD commands type monitor help on the GDB command line 20 2 Sample GDB session startup With the remote protocol GDB sessions start a little differently than they do when you re debugging locally Here s an examples showing how to start a debug session with a small ARM program In this case the program was linked to be loaded into SRAM on a Cortex M3 Most programs would be written into flash address 0 and run from there arm none eabi gdb example elf gdb target remote localhost 3333 Remote debugging using localhost 3333 gdb monitor reset halt Chapter 20 GDB and OpenOCD 107 gdb load Loading section vectors size 0x100 lma 0x20000000 Loading section tert size 0x5a0 lma 0x20000100 Loading section data size 0x18 lma 0x200006a0 Start address 0x2000061c load size 1720 Transfer rate 22 KB sec 573 bytes write gdb continue Continuing You could then interrupt the GDB session to make the program break type where to show the stack list to show the code around the program counter step through code set breakpoints or watchpoints and so on 20 3 Configuring GDB for OpenOCD OpenOCD supports the gdb qSupported packet this enables information to be sent by the GDB
7. e j smp status request e J smp set request OpenOCD implements e jc packet for reading core id displayed by GDB connection Reply is XXXXXXXX 8 hex digits giving core id or E01 for target not smp e JcXXXXXXXX 8 hex digits packet for setting core id displayed at next GDB continue core id 1 is reserved for returning to normal resume mode Reply E01 for target not smp or OK on success Handling of this packet within GDB can be done e by the creation of an internal variable ie core by mean of function allocate computed value allowing following GDB command set _core 1 Jc01 packet is sent print _core jc packet is sent and result is affected in e by the usage of GDB maintenance command as described in following example 2 cpus in SMP with core id 0 and 1 see Define CPU targets working in SMP page 25 toggleO force display of coreid 0 define toggleO Chapter 20 GDB and OpenOCD 109 maint packet JcO continue main packet Jc 1 end togglel force display of coreid 1 define togglel maint packet Jc1 continue main packet Jc 1 end Chapter 21 Tcl Scripting API 110 21 Tcl Scripting API 21 1 API rules The commands are stateless E g the telnet command line has a concept of currently active target the Tcl API proc s take this sort of state information as an argument to each proc There are three main types of return values single value
8. 15 93 97 98 99 Vector table eei ure rre EUER ep arenes 3 97 WAtCH EEN 87 WIEElers regeert be ed REPE ee 5 X Xilinx Serial Vector Format 104 KEE 95 KEE 104 Command and Driver Index Command and Driver Index target name arp examine 56 target name arp halt s s 56 target name arp poll 56 target name arp reset 56 target name arp waitstate 56 target name array2mem 56 target name get ENEE SEENEN pee een 57 target name Configure 55 target name curstate s srrerrrres OL target name eventliert sss of target name invoke event 57 target name mdb 02 oT target name mdb 0008 57 target name md or target name mem2array sss 56 target name mb 57 target name mb 57 target name mu 5T A adapter khz e e Re he mer ena 40 adapter name rlw dk br EEG Ub ER Eo 33 adapter nsrst assert width 42 adapter nsrst delag sss 42 add script search dir s ss 83 aducf 023 io bees ERRORI IEEE du c 65 amt jtagaccel ii co su uaed deri iE EA 34 append f1186 5 0 henb eoe ble RED Ee 85 arm core state eee 92 arm disassemble cece eee e eee 92 arm T r osrziaoage 49e xr erac ewe ean dss 92 E ME Cech evade eae pein ee qw XE y adus 92 AFM TOR ewicsal ge HRXG Y Ka X HY ieee
9. Checks for manufacturer bad block markers on the specified NAND device If no parameters are provided checks the whole device otherwise starts at the specified offset and continues for length bytes Both of those values must be exact multiples of the device s block size and the region they specify must fit entirely in the chip The num parameter is the value shown by nand list NOTE Before using this command you should force raw access with nand raw access enable to ensure that the underlying driver will not try to apply hardware ECC nand info num Command The num parameter is the value shown by nand list This prints the one line sum mary from nand list plus for devices which have been probed this also prints any known status for each block Chapter 13 NAND Flash Commands 79 nand raw access num enable disable Command Sets or clears an flag affecting how page I O is done The num parameter is the value shown by nand list This flag is cleared disabled by default but changing that value won t affect all NAND devices The key factor is whether the underlying driver provides read_page or write_page methods If it doesn t provide those methods the setting of this flag is irrelevant all access is effectively raw When those methods exist they are normally used when reading data nand dump or reading bad block markers or writing it nand write However enabling raw access setting the flag preven
10. Declares a NAND device which can be read and written to after it has been configured through nand probe In OpenOCD devices are single chips this is unlike some operating systems which may manage multiple chips as if they were a single larger device In some cases configuring a device will activate extra commands see the controller specific documentation NOTE This command is not available after OpenOCD initialization has completed Use it in board specific configuration files not interactively e name may be used to reference the NAND bank in most other NAND com mands A number is also available e driver identifies the NAND controller driver associated with the NAND device being declared See NAND Driver List page 79 e target names the target used when issuing commands to the NAND controller e configparams controllers may support or require additional parameters See the controller specific documentation for more information nand list Command Prints a summary of each device declared using nand device numbered from zero Note that un probed devices show no details gt nand list 0 NAND 1GiB 3 3V 8 bit Micron pagesize 2048 buswidth 8 blocksize 131072 blocks 8192 1 NAND 1GiB 3 3V 8 bit Micron pagesize 2048 buswidth 8 blocksize 131072 blocks 8192 gt nand probe num Command Probes the specified device to determine key characteristics like its page and block sizes and how ma
11. 1 2 Doxygen Developer Manual During the 0 2 x release cycle the OpenOCD project began providing a Doxygen reference manual This document contains more technical information about the software internals development processes and similar documentation http openocd berlios de doc doxygen index html This document is a work in progress but contributions would be welcome to fill in the gaps All of the source files are provided in tree listed in the Doxyfile configuration in the top of the source tree 1 3 OpenOCD Developer Mailing List The OpenOCD Developer Mailing List provides the primary means of communication be tween developers https lists berlios de mailman listinfo openocd development Discuss and submit patches to this list The PATCHES txt file contains basic information about how to prepare patches Chapter 1 OpenOCD Developer Resources 4 1 4 OpenOCD Bug Database During the 0 4 x release cycle the OpenOCD project team began using Trac for its bug database https sourceforge net apps trac openocd Chapter 2 Debug Adapter Hardware 5 2 Debug Adapter Hardware Defined dongle A small device that plugins into a computer and serves as an adapter snip In the OpenOCD case this generally refers to a small adapter that attaches to your com puter via USB or the Parallel Printer Port One exception is the Zylin ZY1000 packaged as a small box you attach via an ethernet cable The Zylin ZY1000 has the
12. 2 The double nested EXPR command performs math The EXPR command produces numerical result as a string Refer to Rule 1 3 The format command is executed producing a single string Refer to Rule 1 4 The PUTS command outputs the text 23 6 3 Body or Inlined Text Where Various TARGET scripts 1 1 Good proc someproc multiple lines of stuff _TARGETNAME configure event F00 someproc 2 Good no variables _TARGETNAME confgure event foo this that 3 Good Curly Braces _TARGETNAME configure event FOO puts Time date 4 DANGER DANGER DANGER _TARGETNAME configure event foo puts Time date The TARGETNAME is an OpenOCD variable convention TARGETNAME represents the last target created the value changes each time a new target is created Remember the parsing rules When the ascii text is parsed the TARGETNAME becomes a simple string the name of the target which happens to be a TARGET object command The 2nd parameter to the event parameter is a TCBODY There are 4 examples Chapter 23 Tcl Crash Course 122 1 The TCLBODY is a simple string that happens to be a proc name 2 The TCLBODY is several simple commands seperated by semicolons 3 The TCLBODY is a multi line curly brace quoted string 4 The TCLBODY is a string with variables that get expanded In the end when the target event FOO occurs the TCLBODY is evaluated Method 1 and 2 are functionally ide
13. CPU Configuration page 52 For the at91sam7 example above the command can look like this note that _ENDIAN is not needed since OpenOCD defaults to little endian and this chip doesn t support changing that set TARGETNAME _CHIPNAME cpu target create TARGETNAME arm7tdmi chain position TARGETNAME Work areas are small RAM areas associated with CPU targets They are used by OpenOCD to speed up downloads and to download small snippets of code to program flash chips If the chip includes a form of on chip ram and many do define a work area if you can Again using the at91sam7 as an example this can look like TARGETNAME configure work area phys 0x00200000 work area size 0x4000 work area backup 0 see Define CPU targets working in SMP page 25 Chapter 6 Config File Guidelines 26 6 3 4 Define CPU targets working in SMP After setting targets you can define a list of targets working in SMP set TARGETNAME 1 _CHIPNAME cpul set TARGETNAME 2 CHIPNAME cpu2 target create TARGETNAME 1 cortex a8 chain position CHIPNAME dap coreid 0 dbgbase DAP DBG1 target create TARGETNAME 2 cortex a8 chain position CHIPNAME dap coreid 1 dbgbase SZ DAP DBG2 define 2 targets working in smp target smp CHIPNAME cpu2 CHIPNAME cpui In the above example on cortex a8 2 cpus are working in SMP In SMP only one GDB instance is created and a set of hardware breakpoint sets the same breakpoint on all t
14. Command Displays the value of the flag controlling use of the debug communications channel DCC to write larger gt 128 byte amounts of memory If a boolean parameter is provided first assigns that flag DCC downloads offer a huge speed increase but might be unsafe especially with targets running at very low speeds This command was introduced with OpenOCD rev 60 and requires a few bytes of working area arm7_9 fast_memory_access enable disable Command Displays the value of the flag controlling use of memory writes and reads that don t check completion of the operation If a boolean parameter is provided first assigns that flag This provides a huge speed increase especially with USB JTAG cables FT2232 but might be unsafe if used with targets running at very low speeds like the 32kHz startup clock of an AT91RM9200 16 3 2 ARM720T specific commands These commands are available to ARM720T based CPUs which are implementations of the ARMv4T architecture based on the ARM7TDML S integer core They are available in addition to the ARM and ARM7 ARM9 commands arm720t cp15 opcode value Command DEPRECATED avoid using this Use the arm mrc or arm mcr commands instead Display cp15 register returned by the ARM instruction opcode else if a value is provided that value is written to that register The opcode should be the value of either an MRC or MCR instruction 16 3 3 ARMO specific commands ARM9O family cores a
15. JTAG adapter e Possible srst_type driver modes for the system reset signal SRST are the default srst open drain and erst push pull Most boards connect this signal to a pullup and allow the signal to be pulled low by various events including system powerup and pressing a reset button 9 4 Custom Reset Handling OpenOCD has several ways to help support the various reset mechanisms provided by chip and board vendors The commands shown in the previous section give standard parameters There are also event handlers associated with TAPs or Targets Those handlers are Tcl procedures you can provide which are invoked at particular points in the reset sequence When SRST is not an option you must set up a reset assert event handler for your target For example some JTAG adapters don t include the SRST signal and some boards have multiple targets and you won t always want to reset everything at once After configuring those mechanisms you might still find your board doesn t start up or reset correctly For example maybe it needs a slightly different sequence of SRST and or TRST manipulations because of quirks that the reset config mechanism doesn t address or asserting both might trigger a stronger reset which needs special attention Experiment with lower level operations such as jtag reset and the jtag arp operations shown here to find a sequence of operations that works See Chapter 17 JTAG Commands page 101 When you fi
16. With no parameters show or show all shows the status of all GPNVM bits With show number displays that bit With set number or clear number modifies that GPNVM bit at91sam3 info Command This command attempts to display information about the AT91SAMS chip First it read the CHIPID_CIDR address 0x400e0740 see Section 28 2 1 page 505 of the AT9ISAM3U 29 may 2009 datasheet document id doc6430A and decodes the values Second it reads the various clock configuration registers and attempts to display how it believes the chip is configured By default the SLOWCLK is assumed to be 32768 Hz see the command at91sam3 slowclk at91sam3 slowclk value Command This command shows sets the slow clock frequency used in the at91sam3 info command calculations above at91sam Flash Driver All members of the AT91SAM7 microcontroller family from Atmel include internal flash and use ARM7TDMI cores The driver automatically recognizes a number of these chips using the chip identification register and autoconfigures itself flash bank FLASHNAME at91sam7 O O O O TARGETNAME For chips which are not recognized by the controller driver you must provide addi tional parameters in the following order e chip model label used with flash info e banks e sectors per bank e pages per sector e pages size e num nvm bits e freq_khz required if an external clock is provided optional but recommended when the oscillator frequency is k
17. e STM32 BS TDO output STM32 Cortex M3 TDI input e STM32 Cortex M3 TDO output SM32 TDO Pin e STM32 TDO Pin output gt Xilinx TDI Pin input e Xilinx TDO Pin OpenOCD TDO input The jtag device commands would thus be in the order shown below Note e jtag newtap Xilinx tap irlen e jtag newtap stm32 cpu irlen e jtag newtap stm32 bs irlen e Create the debug target and say where it is e target create stm32 cpu chain position stm32 cpu SYSCOMP Sometimes my debugging session terminates with an error When I look into the log file I can see these error messages Error arm7 9 common c 561 arm7_9_execute_sys_speed timeout waiting for SYSCOMP TODO Chapter 23 Tcl Crash Course 117 23 Tcl Crash Course Not everyone knows Tcl this is not intended to be a replacement for learning Tcl the intent of this chapter is to give you some idea of how the Tcl scripts work This chapter is written with two audiences in mind 1 OpenOCD users who need to understand a bit more of how Jim Tcl works so they can do something useful and 2 those that want to add a new command to OpenOCD 23 1 Tcl Rule 1 There is a famous joke it goes like this 1 Rule 1 The wife is always correct 2 Rule 2 If you think otherwise See Rule 1 The Tcl equal is this 1 Rule 1 Everything is a string 2 Rule 2 If you think otherwise See Rule 1 As in the famous joke the consequences of Rule 1 are profo
18. each supported by a command e History A circular buffer of trace points can be set up and then displayed at any time This tracks where code has been which can be invaluable in finding out how some fault was triggered The buffer may overflow since it collects records continuously It may be useful to use some of the 24 bits to represent a particular event and other bits to hold data e Counting An array of counters can be set up and then displayed at any time This can help establish code coverage and identify hot spots The array of counters is directly indexed by the trace point number so trace points with higher numbers are not counted Chapter 16 Architecture and Core Commands 100 Linux ARM kernels have a Kernel low level debugging via EmbeddedICE DCC channel option CONFIG_DEBUG_ICEDCC depends on CONFIG_DEBUG_LL which uses this mechanism to deliver messages before a serial console can be activated This is not the same format used by libdcc Other software such as the U Boot boot loader sometimes does the same thing target request debugmsgs enable disable charmsg Command Displays current handling of target DCC message requests These messages may be sent to the debugger while the target is running The optional enable and charmsg parameters both enable the messages while disable disables them With charmsg the DCC words each contain one character as used by
19. long real_reset_vector long real_ui_handler long real_swi_handler long real_pf_abort long real_data_abort Long O unused long real irq handler Long real fiq handler Alternatively you may choose to keep some or all of the mini IC vector table entries synced with those written to memory by your system software The mini IC can not be modified while the processor is executing but for each vector table entry not previously defined using the xscale vector table command OpenOCD will copy the value from memory to the mini IC every time execution resumes from a halt This is done for both high and low vector tables although the table not in use may not be mapped to valid memory and in this case that copy operation will silently fail This means that you will need to briefly halt execution at some strategic point during system start up e g after the software has Chapter 16 Architecture and Core Commands 96 initialized the vector table but before exceptions are enabled A breakpoint can be used to accomplish this once the appropriate location in the start up code has been identified A watchpoint over the vector table region is helpful in finding the location if you re not sure Note that the same situation exists any time the vector table is modified by the system software The debug handler must be placed somewhere in the address space using the xscale debug handler command The allowed locations for the debug handler are either
20. or ETB The width must be either 4 8 or 16 except with ETMv3 0 and newer modules which may also support 1 2 24 32 48 and 64 bit widths With those versions etm info also shows whether the selected port width and mode are supported The mode must be normal multiplexed or demultiplexed The clocking must be half or full Warning With ETMvs3 0 and newer the bits set with the mode and clocking parameters both control the mode This modified mode does not map to the values supported by previous ETM modules so this syntax is subject to change Note You can see the ETM registers using the reg command Not all possible registers are present in every ETM Most of the registers are write only and are used to configure what CPU activities are traced etm info Command Displays information about the current target s ETM This includes resource counts from the ETM_CONFIG register as well as silicon capabilities except on rather old modules from the ETM_SYS_CONFIG register etm status Command Displays status of the current target s ETM and trace port driver is the ETM idle or is it collecting data Did trace data overflow Was it triggered etm tracemode type context id bits cycle accurate branch output Command Displays what data that ETM will collect If arguments are provided first configures that data When the configuration changes tracing is stopped and any buffered trace data is in
21. two byte wide parts wired in parallel to create a thirty two bit four byte bus with doubled throughput flash bank FLASHNAME cfi 0x00000000 0x02000000 2 4 TARGETNAME stmsmi Flash Driver Some devices form STMicroelectronics e g STR75x MCU family SPEAr MPU family include a proprietary Serial Memory Interface SMI controller able to drive Chapter 12 Flash Commands 65 external SPI flash devices Depending on specific device and board configuration up to 4 external flash devices can be connected SMI makes the flash content directly accessible in the CPU address space each exter nal device is mapped in a memory bank CPU can directly read data execute code and boot from SMI banks Normal OpenOCD commands like mdw can be used to display the flash content The setup command only requires the base parameter in order to identify the memory bank All other parameters are ignored Additional information like flash size are detected automatically flash bank FLASHNAME stmsmi 0xf8000000 0 O O TARGETNAME 12 4 2 Internal Flash Microcontrollers aduc702x Flash Driver The ADUC702x analog microcontrollers from Analog Devices include internal flash and use ARM7TDMI cores The aduc702x flash driver works with models ADUC7019 through ADUC7028 The setup command only requires the target argument since all devices in this family have the same memory layout flash bank FLASHNAME aduc702x 0 O O O _TARGETNAME at91sam3 Fla
22. value and cache status For valid entries a value is shown valid entries which are also dirty and will be written back later are flagged as such With number name display that register s value With both number name and value set register s value Writes may be held in a writeback cache internal to OpenOCD so that setting the value marks the register as dirty instead of immediately flushing that value Resuming CPU execution including by single stepping or otherwise activating the relevant module will flush such values Cores may have surprisingly many registers in their Debug and trace infrastructure ARM registers 0 rO 32 Ox0000D3C2 dirty 1 ri 32 OxFD61F31C 2 r2 32 164 ETM_contextid_comparator_mask 32 gt halt ms Command wait_halt ms Command The halt command first sends a halt request to the target which wait_halt doesn t Otherwise these behave the same wait up to ms milliseconds or 5 seconds if there is no parameter for the target to halt and enter debug mode Using 0 as the ms parameter prevents OpenOCD from waiting Warning On ARM cores software using the wait for interrupt operation often blocks the J TAG access needed by a halt command This is because Chapter 15 General Commands 84 that operation also puts the core into a low power mode by gating the core clock but the core clock is needed to detect JTAG clock transitions One partial workaround uses adaptive c
23. 23 5 2 Command section 118 23 5 8 The FOR commande 119 23 5 4 FOR command implementation 000 119 23 6 OpenOCD Tcl Usage 120 23 6 1 source and find commande 120 23 6 2 format commande 121 23 6 3 Body or Inlined Test 121 23 6 4 Global Variables 0 00 122 23 1 Other Tcl Hacks iubeo bad Sg Seege gg 122 Appendix A The GNU Free Documentation ere 123 ADDENDUM How to use this License for your documents 129 OpenOCD Concept Index 130 Command and Driver Indez 132 vi About 1 About OpenOCD was created by Dominic Rath as part of a diploma thesis written at the University of Applied Sciences Augsburg http www fh augsburg de Since that time the project has grown into an active open source project supported by a diverse community of software and hardware developers from around the world What is OpenOCD The Open On Chip Debugger OpenOCD aims to provide debugging in system program ming and boundary scan testing for embedded target devices It does so with the assistance of a debug adapter which is a small hardware module which helps provide the right kind of electrical signaling to the target being debugged These are required since the debug host on which OpenOCD runs won t usually have native support for such signaling or the connector needed to hook up to the target Such debug adapters support one or more transport protocols each of which in
24. Commands 88 ATIUM erp Rep enc uere rA RP TP iR pee 92 ARM semihosting s ssssssirerrrrrerrea 16 92 H CR RE 97 ARMT 1 iex REIS I eb erI ee er quen 93 ARMT20T EE 93 ARMY ojos hs p be LQUAPRRUEN ESQ IE ERA EAS 93 ARMO20 KEE 94 ARMO9266 H8 re REENEN NEE EE RENE AN 94 ARMO966E exime retener EIE XU EO PESE 94 KEE 92 ARMY5 u ree Rad risa EARTE ESEE PARAR 92 ATUM YO eee harc Ua erbe SA oyna Pep Re ES 97 ATUM EA hes aang vende be tpe ERE eA UP IUE uM E haps 98 ato 18813 Leoben boe tete tubas Beate arant 65 AlitOprObe wu od eed bade eee eda ee beet e Y vg 51 B board config De 21 breakpolnt 2 222216 Rr pex eere 87 C CEL AE AE AER BEE AE dae 64 command line options ee eee ee 10 COMMANAS 2c hides awe sea heme gaat gag ER aes 82 Common Flash Interface 64 config commande 29 config file board erre peas Saree 21 config file interface sees 33 config file Overview eese 13 config file target Sud Ef Ire erp 24 config file user iit eisi priini E 13 configuration stage 29 Connecting to GD 106 Core Specific Commandes 88 Cortex M3 rM 98 E DR EE ea 53 CPU variant eege e y eene xe ER 53 D EE 98 DCC esses Nude ns tar imp DRE SR UTER EP here 93 99 Debug Access Port 98 developers innimledolvqperk NEE NEEN d ESG 3 directory Search c sss er Ru 10 disassemble si ia cece se eem ENEE e 92 le 5 dotted name AT 130 E HB EE 88 E KEEN 88 event reset m1t cc eee
25. Display cp15 register regnum else if a value is provided that value is written to that register The six bit regnum values are bits 37 32 from table 7 2 of the ARM966E S TRM There is no current control over bits 31 30 from that table as required for BIST support 16 3 7 XScale specific commands Some notes about the debug implementation on the XScale CPUs The XScale CPU provides a special debug only mini instruction cache mini IC in which exception vectors and target resident debug handler code are placed by OpenOCD In order to get access to the CPU OpenOCD must point vector 0 the reset vector to the entry of the debug handler However this means that the complete first cacheline in the mini IC is marked valid which makes the CPU fetch all exception handlers from the mini IC ignoring the code in RAM To address this situation OpenOCD provides the xscale vector table command which allows the user to explicity write individual entries to either the high or low vector table stored in the mini IC It is recommended to place a pc relative indirect branch in the vector table and put the branch destination somewhere in memory Doing so makes sure the code in the vector table stays constant regardless of code layout in memory _vectors ldr pc pc 0x100 8 ldr pc pc 0x100 8 ldr pc pc st0x100 8 ldr pc pc st0x100 8 ldr pc pc s0x100 8 ldr pc pc s0x100 8 ldr pc pc st0x100 8 ldr pc pc 0x100 8 org 0x100
26. In general whenever objects of the same type exist which require an index number then these objects must be given in the right order jtag newtap targets and flash banks a target references a jtag newtap and a flash bank references a target You can use the scan_chain command to verify and display the tap order Also some commands can t execute until after init has been processed Such com mands include nand probe and everything else that needs to write to controller regis ters perhaps for setting up DRAM and loading it with code JTAG TAP Order Do I have to declare the TAPS in some particular order Yes whenever you have more than one you must declare them in the same order used by the hardware Chapter 22 FAQ 116 15 Many newer devices have multiple JTAG TAPs For example ST Microsystems STM32 chips have two TAPs a boundary scan TAP and Cortex M3 TAP Ex ample The STM32 reference manual Document ID RM0008 Section 26 5 Figure 259 page 651 681 the TDI pin is connected to the boundary scan TAP which then connects to the Cortex M3 TAP which then connects to the TDO pin Thus the proper order for the STM32 chip is 1 The Cortex M3 then 2 The boundary scan TAP If your board includes an additional JTAG chip in the scan chain for example a Xilinx CPLD or FPGA you could place it before or after the STM32 chip in the chain For example e OpenOCD TDl output gt STM32 TDI Pin BS Input
27. Info arm7 9 common c 213 arm7_9_add_breakpoint sw breakpoint requested but software breakpoints not enabled Chapter 22 FAQ 114 GDB issues software breakpoints when a normal breakpoint is requested or to imple ment source line single stepping On ARMvAT systems like ARM7TDMI ARM720T or ARM920T software breakpoints consume one of the two available hardware break points 5 LPC2000 Flash When erasing or writing LPC2000 on chip flash the operation fails at random Make sure the core frequency specified in the flash 1pc2000 line matches the clock at the time you re programming the flash If you ve specified the crystal s frequency make sure the PLL is disabled If you ve specified the full core speed e g 60MHz make sure the PLL is enabled 6 Amontec Chameleon When debugging using an Amontec Chameleon in its J TAG Accel erator configuration I keep getting Error amt jtagaccel c 184 amt wait scan busy amt jtagaccel timed out while waiting for end of scan rtck was disabled Make sure your PC s parallel port operates in EPP mode You might have to try several settings in your PC BIOS ECP EPP and different versions of those 7 Data Aborts When debugging with OpenOCD and GDB plain GDB Insight or Eclipse I get lots of Error arm7 9 common c 1771 arm7 9 read memory memory read caused data abort The errors are non fatal and are the result of GDB trying to trace stack frames beyond the last va
28. J TAG Accelerator configuration connected to a PC s EPP mode parallel port This defines some driver specific commands parport port number Config Command Specifies either the address of the I O port default 0x378 for LPT1 or the number of the dev parport device rtck enable disable Config Command Displays status of RT CK option Optionally sets that option first arm jtag ew Interface Driver Olimex ARM JTAG EW USB adapter This has one driver specific command armjtagew info Command Logs some status at91rm9200 Interface Driver Supports bitbanged J TAG from the local system presuming that system is an Atmel A T91rm9200 and a specific set of GPIOs is used dummy Interface Driver A dummy software only driver for debugging ep93xx Interface Driver Cirrus Logic EP93xx based single board computer bit banging in development ft2232 Interface Driver FTDI FT2232 USB based devices over one of the userspace libraries These in terfaces have several commands used to configure the driver before initializing the JTAG scan chain ft2232 device desc description Config Command Provides the USB device description the Product string of the FTDI FT2232 device If not specified the FTDI default value is used This setting is only valid if compiled with FTD2XX support ft2232 serial serial number Config Command Specifies the serial number of the FTDI FT2232 device to use in case the vendor provi
29. Linux with CONFIG_DEBUG_ICEDCC otherwise the libdcc format is used trace history clear count Command With no parameter displays all the trace points that have triggered in the order they triggered With the parameter clear erases all current trace history records With a count parameter allocates space for that many history records trace point clear identifier Command With no parameter displays all trace point identifiers and how many times they have been triggered With the parameter clear erases all current trace point coun ters With a numeric identifier parameter creates a new a trace point counter and associates it with that identifier Important The identifier and the trace point number are not related except by this command These trace point numbers always start at zero from server startup or after trace point clear and count up from there Chapter 17 JTAG Commands 101 17 JTAG Commands Most general purpose JTAG commands have been presented earlier See J TAG Speed page 39 Chapter 9 Reset Configuration page 41 and Chapter 10 TAP Declaration page 46 Lower level JTAG commands as presented here may be needed to work with targets which require special attention during operations such as reset or initialization To use these commands you will need to understand some of the basics of JTAG including e JTAG scan chain consists of a sequence of individual TAP devices such as
30. Shell back ticks The result of a square bracket operation is exactly 1 string Remember Rule 1 Everything is a string These two statements are roughly identical bash example X date echo The Date is X Tcl example set X date puts The Date is X e double quoted things double quoted things are just simply quoted text VARIABLES and square brackets are expanded in place the result however is exactly 1 string Remember Rule 1 Everything is a string set x Dinner puts It is now date x is in 1 hour e Curly Braces Curly Braces are magic VARIABLES and square brackets are parsed but are NOT expanded or executed Curly Braces are like single quote operators in BASH shell scripts with the added feature curly braces can be nested single quotes can not this is nested 3 times NOTE date is a bad example at this writing Jim OpenOCD does not have a date command 23 5 Consequences of Rule 1 2 3 4 The consequences of Rule 1 are profound 23 5 1 Tokenisation amp Execution Of course whitespace blank lines and comment lines are handled in the normal way As a script is parsed each multi line in the script file is tokenised and according to the quoting rules After tokenisation that line is immedatly executed Multi line statements end with one or more still open curly braces which eventually closes a few lines later 23 5 2 Command Executio
31. a CPUs e Control operations involve moving each TAP through the same standard state machine in parallel using their shared TMS and clock signals e Data transfer involves shifting data through the chain of instruction or data registers of each TAP writing new register values while the reading previous ones e Data register sizes are a function of the instruction active in a given TAP while in struction register sizes are fixed for each TAP All T APs support a BYPASS instruction with a single bit data register e The way OpenOCD differentiates between TAP devices is by shifting different instruc tions into and out of their instruction registers 17 1 Low Level JTAG Commands These commands are used by developers who need to access J TAG instruction or data registers possibly controlling the order of TAP state transitions If you re not debugging OpenOCD internals or bringing up a new JTAG adapter or a new type of TAP device like a CPU or JTAG router you probably won t need to use these commands In a debug session that doesn t use JTAG for its transport protocol these commands are not available drscan tap numbits value endstate tap_state Command Loads the data register of tap with a series of bit fields that specify the entire register Each field is numbits bits long with a numeric value hexadecimal encouraged The return value holds the original value of each of those fields For example a 38 bit number
32. advantage that it does not require any drivers to be installed on the developer PC It also has a built in web interface It supports RTCK RCLK or adaptive clocking and has a built in relay to power cycle targets remotely 2 1 Choosing a Dongle There are several things you should keep in mind when choosing a dongle 1 Transport Does it support the kind of communication that you need OpenOCD focusses mostly on JTAG Your version may also support other ways to communicate with target devices 2 Voltage What voltage is your target 1 8 2 8 3 3 or 5V Does your dongle support it You might need a level converter 3 Pinout What pinout does your target board use Does your dongle support it You may be able to use jumper wires or an octopus connector to convert pinouts 4 Connection Does your computer have the USB printer or Ethernet port needed 5 RTCK Do you expect to use it with ARM chips and boards with RTCK support Also known as adaptive clocking 2 2 Stand alone Systems ZY1000 See http www zylin com zy1000 html Technically not a dongle but a stand alone box The ZY1000 has the advantage that it does not require any drivers installed on the developer PC It also has a built in web interface It supports RTCK RCLK or adaptive clocking and has a built in relay to power cycle targets remotely 2 3 USB F T2232 Based There are many USB JTAG dongles on the market many of them are based on a chip from Future Tech
33. all boards using that chip And when the JTAG adapter doesn t support everything the user configuration file will need to override parts of the reset configuration provided by other files 9 1 Types of Reset There are many kinds of reset possible through JTAG but they may not all work with a given board and adapter That s part of why reset configuration can be error prone e System Reset the SRST hardware signal resets all chips connected to the JTAG adapter such as processors power management chips and I O controllers Normally resets triggered with this signal behave exactly like pressing a RESET button e JTAG TAP Reset the TRST hardware signal resets just the TAP controllers con nected to the JTAG adapter Such resets should not be visible to the rest of the system resetting a device s TAP controller just puts that controller into a known state e Emulation Reset many devices can be reset through JTAG commands These resets are often distinguishable from system resets either explicitly a reset reason register says so or implicitly not all parts of the chip get reset e Other Resets system on chip devices often support several other types of reset You may need to arrange that a watchdog timer stops while debugging preventing a watchdog reset There may be individual module resets In the best case OpenOCD can hold SRST then reset the TAPs via TRST and send commands through JTAG to halt the CPU at the
34. an efficient script oriented interface to memory The array2mem prim itive writes bytes halfwords or words while mem2array reads them In both cases the TCL side uses an array and the target side uses raw memory The efficiency comes from enabling the use of bulk JTAG data transfer operations The script orientation comes from working with data values that are packaged for use by TCL scripts mdw type primitives only print data they retrieve and neither store nor return those values e arrayname is the name of an array variable Chapter 11 CPU Configuration 57 e width is 8 16 32 indicating the memory access size e address is the target memory address e count is the number of elements to process target_name cget queryparm Command Each configuration parameter accepted by target_name configure can be individu ally queried to return its current value The queryparm is a parameter name accepted by that command such as work area phys There are a few special cases e event event name returns the handler for the event named event name This is a special case because setting a handler requires two parameters e type returns the target type This is a special case because this is set using target create and can t be changed using target name configure For example if you wanted to summarize information about all the targets you might use something like this foreach name target names set y
35. are in curly braces thus the variables inside are not expanded or replaced until later Remember that every Tcl command looks like the classic main argc argv function in C In JimTCL they actually look like this int MyCommand Jim Interp interp int argc Jim O0bj const argvs Real Tcl is nearly identical Although the newer versions have introduced a byte code parser and intepreter but at the core it still operates in the same basic way 23 5 4 FOR command implementation To understand Tcl it is perhaps most helpful to see the FOR command Remember it is a COMMAND not a control flow structure In Tcl there are two underlying C helper functions Remember Rule 1 You are a string The first helper parses and executes commands found in an ascii string Commands can be seperated by semicolons or newlines While parsing variables are expanded via the quoting rules The second helper evaluates an ascii string as a numerical expression and returns a value Here is an example of how the FOR command could be implemented The pseudo code below does not show error handling Chapter 23 Tcl Crash Course 120 void Execute AsciiString void interp const char string int Evaluate AsciiExpression void interp const char string int MyForCommand void interp int argc char argv if argc bit SetResult interp WRONG number of parameters return ERROR argv 0 the ascii s
36. bit value at the specified address addr When the current target has an MMU which is present and active addr is interpreted as a virtual address Otherwise or if the optional phys flag is specified addr is interpreted as a physical address 15 5 Image loading commands dump image filename address size Command Dump size bytes of target memory starting at address to the binary file named file name fast load Command Loads an image stored in memory by fast load image to the current target Must be preceeded by fast load image fast load image filename address bin ihex elf s19 Command Normally you should be using load image or GDB load However for testing pur poses or when I O overhead is significant OpenOCD running on an embedded host storing the image in memory and uploading the image to the target can be a way to upload e g multiple debug sessions when the binary does not change Arguments are the same as load image but the image is stored in OpenOCD host memory i e does not affect target This approach is also useful when profiling target programming performance as I O and target programming can easily be profiled separately load image filename address bin ihex elf s19 min addr Command max length Load image from file filename to target memory offset by address from its load address The file format may optionally be specified bin ihex elf or s
37. configuration stage but systems with a JTAG router can enable or disable TAPs dynamically 10 2 TAP Names When TAP objects are declared with jtag newtap a dotted name is created for the T AP combining the name of a module usually a chip and a label for the TAP For exam ple xilinx tap str912 flash omap3530 jrc dm6446 dsp or stm32 cpu Many other commands use that dotted name to manipulate or refer to the TAP For example CPU configuration uses the name as does declaration of NAND or NOR flash banks The components of a dotted name should follow C symbol name rules start with an alphabetic character then numbers and underscores are OK while others including dots are not Tip In older code JTAG TAPs were numbered from 0 N This feature is still present However its use is highly discouraged and should not be relied on it will be removed by mid 2010 Update all of your scripts to use TAP names rather than numbers by paying attention to the runtime warnings they trigger Using TAP numbers in target configuration scripts prevents reusing those scripts on boards with multiple targets 10 3 TAP Declaration Commands jtag newtap chipname tapname configparams Command Declares a new TAP with the dotted name chipname tapname and configured ac cording to the various configparams The chipname is a symbolic name for the chip Conventionally target config files use CHIPNAME defaulting to the model name given by the chi
38. create it then configure optional parts All operations on the target after it s created will use a new command created as part of target creation The two main things to configure after target creation are a work area which usually has target specific defaults even if the board setup code overrides them later and event handlers see Target Events page 57 which tend to be much more board specific The key steps you use might look something like this target create MyTarget cortex m3 chain position mychip cpu MyTarget configure work area phys 0x08000 work area size 8096 MyTarget configure event reset deassert pre jtag rclk 5 MyTarget configure event reset init myboard reinit You should specify a working area if you can typically it uses some on chip SRAM Such a working area can speed up many things including bulk writes to target memory flash operations like checking to see if memory needs to be erased GDB memory checksumming and more Warning On more complex chips the work area can become inaccessible when application code such as an operating system enables or disables the MMU For example the particular MMU context used to acess the virtual address will probably matter and that context might not have easy access to other Chapter 11 CPU Configuration 55 addresses needed At this writing OpenOCD doesn t have much MMU intelli gence It s often very useful to define a reset init event handler For syst
39. currently supported by OpenOCD requires explicit configu ration of all TAP devices using jtag newtap commands as detailed later in this chapter A command like this would declare one tap and name it chip1 cpu jtag newtap chipi cpu irlen 4 expected id 0x3ba00477 Each target configuration file lists the TAPs provided by a given chip Board configuration files combine all the targets on a board and so forth Note that the order in which TAPs are declared is very important It must match the order in the JTAG scan chain both inside a single chip and between them See FAQ TAP Order page 115 HG Chapter 10 TAP Declaration 4T For example the ST Microsystems STR912 chip has three separate TAPs To configure those taps target str912 cfg includes commands something like this jtag newtap str912 flash params jtag newtap str912 cpu params jtag newtap str912 bs params Actual config files use a variable instead of literals like str912 to support more than one chip of each type See Chapter 6 Config File Guidelines page 19 jtag names Command Returns the names of all current TAPs in the scan chain Use jtag cget or jtag tapisenabled to examine attributes and state of each TAP foreach t jtag names 1 puts format TAP s n t scan_chain Command Displays the T APs in the scan chain configuration and their status The set of TAPs listed by this command is fixed by exiting the OpenOCD
40. format LaTEX input format SGML or XML using a publicly available DTD and standard conforming simple HTML PostScript or PDF designed for human modification Examples of transparent image formats include PNG XCF and JPG Opaque formats include proprietary formats that can be read and edited only by proprietary word processors SGML or XML for which the DTD and or processing tools are not generally available and the machine generated HTML PostScript or PDF produced by some word processors for output purposes only The Title Page means for a printed book the title page itself plus such following pages as are needed to hold legibly the material this License requires to appear in the title page For works in formats which do not have any title page as such Title Page means the text near the most prominent appearance of the work s title preceding the beginning of the body of the text A section Entitled XYZ means a named subunit of the Document whose title either is precisely XYZ or contains XYZ in parentheses following text that translates XYZ in another language Here XYZ stands for a specific section name mentioned below such as Acknowledgements Dedications Endorsements or History To Preserve the Title of such a section when you modify the Document means that it remains a section Entitled XYZ according to this definition The Document may include Warranty Disclaimers next to the notice
41. less common so if you have the choice you should probably avoid these adapters in favor of USB based ones Wiggler There are many clones of this Link http www macraigor com wiggler htm DLC5 From XILINX There are many clones of this Link Search the web for XILINX DLC5 it is no longer produced PDF schematics are easily found and it is easy to make Amontec JTAG Accelerator Link http www amontec com jtag accelerator shtml GW16402 Link http www gateworks com products avila accessories gw16042 php Wiggler2 Improved parallel port wiggler style J TAG adapter Wiggler ntrst inverted Yet another variation See the source code src jtag parport c old amt wiggler Unknown probably not on the market today arm jtag Link Most likely http www olimex com dev arm jtag html another wiggler clone chameleon Link http www amontec com chameleon shtml Triton Unknown Lattice ispDownload from Lattice Semiconductor http www latticesemi com lit docs devtools dlcable pdf flashlink From ST Microsystems FlashLINK JTAG programing cable for PSD and uPSD 2 9 Other ep93xx An EP93xx based Linux machine using the GPIO pins directly at91rm9200 Like the EP93xx but an ATMEL AT91RM9200 based solution using the GPIO pins on the chip Chapter 3 About Jim Tcl 9 3 About Jim Tcl OpenOCD uses a small Tcl Interpreter known as Jim Tcl This programming language provides a simple and ext
42. name prefixes to help avoid naming collisions Board files could also accept input variables from user config files For example there might be a J4_JUMPER setting used to identify what kind of flash memory a development board is using or how to set up other clocks and peripherals 6 2 2 Variable Naming Convention Most boards have only one instance of a chip However it should be easy to create a board with more than one such chip as shown above Accordingly we encourage these conventions for naming variables associated with different target cfg files to promote consistency and so that board files can override target defaults Inputs to target config files include e CHIPNAME This gives a name to the overall chip and is used as part of tap identifier dotted names While the default is normally provided by the chip manufacturer board files may need to distinguish between instances of a chip e ENDIAN By default Little although chips may hard wire big Chips that can t change endianness don t need to use this variable e CPUTAPID When OpenOCD examines the JTAG chain it can be told verify the chips against the J TAG IDCODE register The target file will hold one or more defaults but sometimes the chip in a board will use a different ID perhaps a newer revision Outputs from target config files include e _TARGETNAME By convention this variable is created by the target configuration script
43. not specify a value for this except on targets with an MMU The value should normally correspond to a static mapping for the work area phys address set up by the current operating system 11 4 Other Starget name Commands The Tcl Tk language has the concept of object commands and OpenOCD adopts that same model for targets A good Tk example is a on screen button Once a button is created a button has a name a path in Tk terms and that name is useable as a first class command For example in Tk one can create a button and later configure it like this Create button foobar background red command foo Modify foobar configure foreground blue Query set x foobar cget background Report puts format The button is s x In OpenOCD s terms the target is an object just like a Tcl Tk button and its object commands are invoked the same way str912 cpu mww 0x1234 0x42 omap3530 cpu mww Ox5555 123 The commands supported by OpenOCD target objects are target name arp examine Command target name arp halt Command target name arp poll Command target_name arp_reset target name arp waitstate Command Internal OpenOCD scripts most notably startup tcl use these to deal with spe cific reset cases They are not otherwise documented here target name array2mem arrayname width address count Command target_name mem2array arrayname width address count Command These provide
44. on Reboot from scratch using that new boot loader reset run You may need more complicated utility procedures when booting from NAND That often involves an extra bootloader stage running from on chip SRAM to perform DDR RAM setup so it can load the main bootloader code which won t fit into that SRAM Other helper scripts might be used to write production system images involving consider ably more than just a three stage bootloader 5 6 Target Software Changes Sometimes you may want to make some small changes to the software you re developing to help make JTAG debugging work better For example in C or assembly language code you might use ifdef JTAG DEBUG or its converse around code handling issues like e Watchdog Timers Watchog timers are typically used to automatically reset systems if some application task doesn t periodically reset the timer The assumption is that the system has locked up if the task can t run When a JTAG debugger halts the system that task won t be able to run and reset the timer potentially causing resets in the middle of your debug sessions It s rarely a good idea to disable such watchdogs since their usage needs to be debugged just like all other parts of your firmware That might however be your only option Look instead for chip specific ways to stop the watchdog from counting while the sys tem is in a debug halt state It may be simplest to set that non counting mode in
45. or finds TAPs that aren t supposed to be there You should see no errors at this point If you see errors resolve them by correcting the commands you used to configure the server Common errors include using an initial JTAG speed that s too fast and not providing the right IDCODE values for the TAPs on the scan chain Once OpenOCD has entered the run stage a number of commands become available A number of these relate to the debug targets you may have declared For example the mww command will not be available until a target has been successfuly instantiated If you want to use those commands you may need to force entry to the run stage init Config Command This command terminates the configuration stage and enters the run stage This helps when you need to have the startup scripts manage tasks such as resetting the target programming flash etc To reset the CPU upon startup add init and reset at the end of the config script or at the end of the OpenOCD command line using the c command line switch If this command does not appear in any startup configuration file OpenOCD executes the command for you after processing all configuration files and or command line options NOTE This command normally occurs at or near the end of your openocd cfg file to force OpenOCD to initialize and make the targets ready For example If your openocd cfg file needs to read write memory on your target init must occur before the memory read wri
46. out of reset everything else should work fine 9 USB Power When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto toolchain Eclipse arm elf gcc arm elf gdb the debugging seems to be un stable When single stepping over large blocks of code GDB and OpenOCD quit with an error message Is there a stability issue with OpenOCD Chapter 22 FAQ 115 10 11 12 13 14 No this is not a stability issue concerning OpenOCD Most users have solved this issue by simply using a self powered USB hub which they connect their Amontec JTAGkey to Apparently some computers do not provide a USB power supply stable enough for the Amontec JTAGkey to be operated Laptops running on battery have this problem too USB Power When using the Amontec JTAGkey sometimes OpenOCD crashes with the following error messages Error ft2232 c 201 ft2232 read FT Read returned 4 and Error ft2232 c 365 ft2232 send and recv couldn t read from FT2232 What does that mean and what might be the reason for this First of all the reason might be the USB power supply Iry using a self powered hub instead of a direct connection to your computer Secondly the error code 4 corresponds to an FT IO ERROR which means that the driver for the FTDI USB chip ran into some sort of error this points us to a USB problem GDB Disconnects When using the Amontec JTAGkey sometimes OpenOCD crashes with the following error message Error gdb s
47. parameter is the value shown by nand list pio_base_addr is the base address of the PIO controller and pin is the pin number at91sam9 ce num pio_base_addr pin Command Configure the chip enable input to the NAND device The num parameter is the value shown by nand list pio base addr is the base address of the PIO controller and pin is the pin number Chapter 13 NAND Flash Commands 80 davinci NAND Driver This driver handles the NAND controllers found on DaVinci family chips from Texas Instruments It takes three extra parameters address of the NAND chip hardware ECC mode to use hwecct hwecc4 hwecc4_infix address of the AEMIF con troller on this processor nand device davinci dm355 arm 0x02000000 hwecc4 0x01e10000 All DaVinci processors support the single bit ECC hardware and newer ones also support the four bit ECC hardware The write page and read page methods are used to implement those ECC modes unless they are disabled using the nand raw_ access command 1pc3180 NAND Driver These controllers require an extra nand device parameter the clock rate used by the controller 1pc3180 select num mlc slc Command Configures use of the MLC or SLC controller mode MLC implies use of hard ware ECC The num parameter is the value shown by nand list At this writing this driver includes write page and read page methods Using nand raw access to disable those methods will prevent use of hardware ECC in the
48. passing the oob_softecc flag when writing NAND data or ensuring that the correct hardware ECC mode is used The basic steps for using NAND devices include 1 Declare via the command nand device Do this in a board specific configuration file passing parameters as needed by the controller 2 Configure each device using nand probe Do this only after the associated target is set up such as in its reset init script or in procures defined to access that device 3 Operate on the flash via nand subcommand Often commands to manipulate the flash are typed by a human or run via a script in some automated way Common task include writing a boot loader operating system or other data needed to initialize or de brick a board NOTE At the time this text was written the largest NAND flash fully supported by OpenOCD is 2 GiBytes 16 GiBits This is because the variables used to hold offsets and lengths are only 32 bits wide Larger chips may work in some cases unless an offset or length is larger than Oxffffffff the largest 32 bit unsigned integer Some larger devices will work since they are actually multi chip modules with two smaller chips and individual chipselect lines 13 1 NAND Configuration Commands NAND chips must be declared in configuration scripts plus some additional configuration that s done after OpenOCD has initialized Chapter 13 NAND Flash Commands 76 nand device name driver target configparams Config Command
49. reset vector before the 1st instruction is executed Then when it finally releases the SRST signal the system is halted under debugger control before any code has executed This is the behavior required to support the reset halt and reset init commands after reset init a board specific script might do things like setting up DRAM See Reset Command page 84 9 2 SRST and TRST Issues Because SRST and TRST are hardware signals they can have a variety of system specific constraints Some of the most common issues are e Signal not available Some boards don t wire SRST or TRST to the J TAG connector Some JTAG adapters don t support such signals even if they are wired up Use the reset config signals options to say when either of those signals is not connected Chapter 9 Reset Configuration 42 When SRST is not available your code might not be able to rely on controllers having been fully reset during code startup Missing TRST is not a problem since JTAG level resets can be triggered using with TMS signaling e Signals shorted Sometimes a chip board or adapter will connect SRST to TRST instead of keeping them separate Use the reset config combination options to say when those signals aren t properly independent e Timing Reset circuitry like a resistor capacitor delay circuit reset supervisor or on chip features can extend the effect of a J TAG adapter s reset for some time after the adapter stops issuing the reset For
50. specified Some tms470 specific commands are defined tms470 flash keyset key0 keyl key2 key3 Command Saves programming keys in a register to enable flash erase and write commands tms470 osc mhz clock mhz Command Reports the clock speed which is used to calculate timings tms470 plldis 0 1 Command Disables 1 or enables 0 use of the PLL to speed up the flash clock virtual Flash Driver This is a special driver that maps a previously defined bank to another address All bank settings will be copied from the master physical bank The virtual driver defines one mandatory parameters Chapter 12 Flash Commands 72 e master_bank The bank that this virtual address refers to So in the following example addresses Oxbfc00000 and 0x9fc00000 refer to the flash bank defined at address Ox1fc00000 Any cmds executed on the virtual banks are actually performed on the physical banks flash bank FLASHNAME pic32mx Ox1fc00000 O O O _TARGETNAME flash bank vbankO virtual Oxbfc00000 O O 0 TARGETNAME FLASHNAME flash bank vbank1 virtual 0x9fc00000 O O 0 TARGETNAME FLASHNAME fm3 Flash Driver All members of the FM3 microcontroller family from Fujitsu include internal flash and use ARM Cortex M3 cores The fm3 driver uses the target parameter to select the correct bank config it can currently be one of the following mb9bfxx1 cpu mb9bfxx2 cpu mb9bfxx3 cpu mb9bfxx4 cpu mb9bfxx5 cpu or mb9bfxx6 cpu flash bank FLASHNA
51. t need more than the target config file as in the AT91SAM7X256 example That s because there is no external memory flash DDR RAM and the board differences are encapsulated by application code e Maybe you don t know yet what your board looks like to JTAG Once you know the interface cfg file to use you may need help from OpenOCD to discover what s on the board Once you find the JTAG TAPs you can just search for appropriate target and board configuration files or write your own from the bottom up See Autoprobing page 50 e You can often reuse some standard config files but need to write a few new ones probably a board cfg file You will be using commands described later in this User s Guide and working with the guidelines in the next chapter For example there may be configuration files for your JTAG adapter and target chip but you need a new board specific config file giving access to your particular flash chips Or you might need to write another target chip configuration file for a new chip built around the Cortex M3 core Note When you write new configuration files please submit them for inclu sion in the next OpenOCD release For example a board newboard cfg file will help the next users of that board and a target newcpu cfg will help support users of any board using that chip e You may may need to write some C code It may be as simple as a supporting a new ft2232 or parport based adapte
52. that include an ARM core for operating system use a DSP another ARM core embedded in an image processing engine and other processing engines 6 3 1 Default Value Boiler Plate Code All target configuration files should start with code like this letting board config files express environment specific differences in how things should be set up Boards may override chip names perhaps based on role but the default should match what the vendor uses if info exists CHIPNAME 1 set _CHIPNAME CHIPNAME else set _CHIPNAME sam7x256 ONLY use ENDIAN with targets that can change it if info exists ENDIAN 1 set _ENDIAN ENDIAN else 1 set _ENDIAN little TAP identifiers may change as chips mature for example with new revision fields the 3 here Pick a good default you can pass several such identifiers to the jtag newtap command if info exists CPUTAPID set _CPUTAPID CPUTAPID else set _CPUTAPID Ox3fOfOfOf Chapter 6 Config File Guidelines 25 Remember Board config files may include multiple target config files or the same target file multiple times changing at least CHIPNAME Likewise the target configuration file should define TARGETNAME or _TARGETNAMEO etc and use it later on when defining debug targets set TARGETNAME CHIPNAME cpu target create TARGETNAME arm7tdmi chain position _TARGETNAME 6 3 2 Adding TAPs to the Scan Chain After the defaults are set
53. to execute then disables interrupts and steps over the next instruction where the core was halted After the step interrupts are enabled again If the interrupt handlers don t complete within 500ms the step command leaves with the core running Note that a free breakpoint is required for the auto option If no breakpoint is available at the time of the step then the step is taken with interrupts enabled i e the same way the off option does Default is auto Chapter 16 Architecture and Core Commands 99 cortex m3 vector catch all none Iist Command Vector Catch hardware provides dedicated breakpoints for certain hardware events Parameters request interception of all of these hardware event vectors none of them or one or more of the following hard err for a HardFault exception mm ert for a MemManage exception bus_err for a BusFault exception irg_err state_err chk_err or nocp_err for various UsageFault exceptions or reset If NVIC setup code does not enable them MemManage BusFault and UsageFault exceptions are mapped to HardFault UsageFault checks for divide by zero and un aligned access must also be explicitly enabled This finishes by listing the current vector catch configuration cortex_m3 reset_config srst sysresetreq vectreset Command Control reset handling The default srst is to use srst if fitted otherw
54. up the target so it is possible to probe flash Probing flash is necessary during gdb connect if gdb load is to write the image to flash Another use of the flash memory map is for GDB to automatically hardware software breakpoints depending on whether the breakpoint is in RAM or read only memory gdb detach When GDB disconnects gdb end When the target has halted and GDB is not doing anything see early halt Chapter 11 CPU Configuration 59 e gdb flash erase start Before the GDB flash process tries to erase the flash e gdb flash erase end After the GDB flash process has finished erasing the flash e gdb flash write start Before GDB writes to the flash e gdb flash write end After GDB writes to the flash e gdb start Before the target steps gdb is trying to start resume the target e halted The target has halted e reset assert pre Issued as part of reset processing after reset init was triggered but before either SRST alone is re asserted on the scan chain or reset assert is triggered e reset assert Issued as part of reset processing after reset assert pre was triggered When such a handler is present cores which support this event will use it instead of asserting SRST This support is essential for debugging with JTAG interfaces which don t include an SRST line JTAG doesn t require SRST and for selective reset on scan chains that have multiple targets e reset assert post Issued as part of reset processing after reset
55. users beyond what the individual works permit When the Document is included in an aggregate this License does not apply to the other works in the aggregate which are not themselves derivative works of the Document If the Cover Text requirement of section 3 is applicable to these copies of the Document then if the Document is less than one half of the entire aggregate the Document s Cover Texts may be placed on covers that bracket the Document within the aggregate or the electronic equivalent of covers if the Document is in electronic form Otherwise they must appear on printed covers that bracket the whole aggregate TRANSLATION Iranslation is considered a kind of modification so you may distribute translations of the Document under the terms of section 4 Replacing Invariant Sections with translations requires special permission from their copyright holders but you may include translations of some or all Invariant Sections in addition to the original versions of these Invariant Sections You may include a translation of this License and all the license notices in the Document and any Warranty Disclaimers provided that you also include the original English version of this License and the original versions of those notices and disclaimers In case of a disagreement between the translation and the original version of this License or a notice or disclaimer the original version will prevail If a section in the Document is Entitled Ackn
56. which states that this License applies to the Document These Warranty Disclaimers are considered to be included by reference in this License but only as regards disclaiming warranties any other implication that these Warranty Disclaimers may have is void and has no effect on the meaning of this License 2 VERBATIM COPYING You may copy and distribute the Document in any medium either commercially or noncommercially provided that this License the copyright notices and the license notice saying this License applies to the Document are reproduced in all copies and Appendix A The GNU Free Documentation License 125 that you add no other conditions whatsoever to those of this License You may not use technical measures to obstruct or control the reading or further copying of the copies you make or distribute However you may accept compensation in exchange for copies If you distribute a large enough number of copies you must also follow the conditions in section 3 You may also lend copies under the same conditions stated above and you may publicly display copies 3 COPYING IN QUANTITY If you publish printed copies or copies in media that commonly have printed covers of the Document numbering more than 100 and the Document s license notice requires Cover Texts you must enclose the copies in covers that carry clearly and legibly all these Cover Texts Front Cover Texts on the front cover and Back Cover Texts on the back cov
57. www luminarymicro com Luminary In Circuit Debug Interface ICDI Boards are included in Stellaris LM3S9B9x Evaluation Kits Like the non detachable FT2232 support on the other Stellaris eval boards they can be used to debug other target boards e olimex jtag See http www olimex com e flyswatter See http www tincantools com e turtelizer2 See Turtelizer 2 or http www ethernut de e comstick Link http www hitex com index php id 383 e stm32stick Link http www hitex com stm32 stick e axm0432 jtag Axiom AXM 0432 Link http www axman com e cortino Link http www hitex com index php id cortino 2 4 USB JTAG Altera USB Blaster compatibles These devices also show up as FTDI devices but are not protocol compatible with the FT2232 devices They are however protocol compatible among themselves USB JTAG devices typically consist of a FT245 followed by a CPLD that understands a particular protocol or emulate this protocol using some other hardware They may appear under different USB VID PID depending on the particular product The driver can be configured to search for any VID PID pair see the section on driver commands Chapter 2 Debug Adapter Hardware 7 USB JTAG Kolja Waschk s USB Blaster compatible adapter Link http www ixo de info usb_jtag Altera USB Blaster Link http www altera com literature ug ug_usb_blstr pdf 2 5 USB JLINK based There are several OEM versions of the Segger JLINK ad
58. 0x800 Ox1fef800 or 0xfe000800 Oxfffff800 The default value is 0xfe000800 XScale has resources to support two hardware breakpoints and two watchpoints However the following restrictions on watchpoint functionality apply 1 the value and mask argu ments to the wp command are not supported 2 the watchpoint length must be a power of two and not less than four and can not be greater than the watchpoint address and 3 a watchpoint with a length greater than four consumes all the watchpoint hardware resources This means that at any one time you can have enabled either two watchpoints with a length of four or one watchpoint with a length greater than four These commands are available to XScale based CPUs which are implementations of the ARMVv5TE architecture xscale analyze trace Command Displays the contents of the trace buffer xscale cache clean address address Command Changes the address used when cleaning the data cache xscale cache info Command Displays information about the CPU caches xscale cp15 regnum value Command Display cp15 register regnum else if a value is provided that value is written to that register xscale debug handler target address Command Changes the address used for the specified target s debug handler xscale dcache enable disable Command Enables or disable the CPU s data cache xscale dump trace filename Command Dumps the raw contents of the trace buffer to filename
59. 19 In addition the following arguments may be specifed min_addr ignore data below min_addr this is w r t to the target s load address address max_length maximum number of bytes to load proc load image bin fname foffset address length Load data from fname filename at foffset offset to target at address Load at most length bytes load image fname expr address foffset bin address length J test image filename address bin ihex elf Command Displays image section sizes and addresses as if filename were loaded into target memory starting at address defaults to zero The file format may optionally be specified bin ihex or elf Chapter 15 General Commands 87 verify image filename address bin ihex elf Command Verify filename against target memory starting at address The file format may optionally be specified bin ihex or elf This will first attempt a comparison using a CRC checksum if this fails it will try a binary compare 15 6 Breakpoint and Watchpoint commands CPUs often make debug modules accessible through JTAG with hardware support for a handful of code breakpoints and data watchpoints In addition CPUs almost always support software breakpoints bp address len hw Command With no parameters lists all active breakpoints Else sets a breakpoint on code execution starting at address for length bytes
60. 2 11 CPU Configuration This chapter discusses how to set up GDB debug targets for CPUs You can also access these targets without GDB see Chapter 16 Architecture and Core Commands page 88 and Target State handling page 83 and through various kinds of NAND and NOR flash commands If you have multiple CPUs you can have multiple such targets We ll start by looking at how to examine the targets you have then look at how to add one more target and how to configure it 11 1 Target List All targets that have been set up are part of a list where each member has a name That name should normally be the same as the TAP name You can display the list with the targets plural command This display often has only one CPU here s what it might look like with more than one TargetName Type Endian TapName State O at91rm9200 cpu arm920t little at91rm9200 cpu running 1 MyTarget cortex m3 little mychip foo tap disabled One member of that list is the current target which is implicitly referenced by many commands It s the one marked with a near the target name In particular memory addresses often refer to the address space seen by that current target Commands like mdw memory display words and flash erase address erase NOR flash blocks are examples and there are many more Several commands let you examine the list of targets target count Command Note target numbers are deprecated don t use them They will be removed sho
61. 24 eene eade a dor WR 61 flash banks jcc a cenin anna chased RR REY RR 62 flash erase address esse 63 flash erase check elles 64 flash erase sector cele 62 flash fillb i da dows Gs wees ERU RU ER 63 flasb E a E iben ewe RUE Iun eas 63 flash fillw osa ERE Ra re 63 flash info EE 64 flash IiSt2oi l 06e hee EE 62 flash probes ees eos dea aleenhe 4 SE di Res 62 flash protect iiiri S CURAR aah eed LIS 64 flash write bank eee eee 63 flash write 1Iuage is oici eiorsitearsoi isesi 63 ka WE eh EE 102 d E E N E A E ER 72 EE esn snr arsed eu EE 34 t2232_device_desc cece eee 34 2232 latency s c re x ee beo eH daa 35 ft2232 layout ive desta ae Seeded 34 ft2232 Serial t p e e EE EY ee 34 f12232 vid pad otl pleb I re 35 G gdb breakpoint override al gdb flash program ii edes dee oU gdb menory DEE e js er Nee esa vans 3L POD portals piece chit oe m E NA reed 30 gdb report data abort sess 31 CEET 36 H Lh Em 83 Nk EE 82 I pn rM 29 init reset e E ERE padres 44 3nterfdce itisien ni lcge RUIN D EARS aceon 33 interface transports sess 33 133 interface IISt i11 a Ree dep E Rx Ra pP 33 AP ia igang seed hehe Gene er hpernriid EEN RNE E ERA Ea 85 SE 102 J ides LM E 36 Jtag arp init deg edad ow Ree Een eer ees 45 jtag arp Lnit reset cc cece eee 45 Jtag Cgetiilis seul ena d bles Qiiid 49 jtag
62. 440 EE 80 S3c2443 coole ore rber PEPPER PE PEVCE PU 80 S9c6400 EE 80 GI Ch UE stad pedo doi Diese AT GT EE 82 CR EE 82 Soft reset halt pagg d e de tS es 84 Ste llariSi oo xe ge tan eese REVPPPPRERY OQ 70 stellaris recover bank id 70 SLOD rei e pae beerporipRircauceezerhigepei ig 84 Stm32f1xXx cd x pe Cos rx EUH den RR 70 stm32fix LOCK oi ches segs eter ennnen aaa FERMER ER 70 stm32f1x options_read 0 00 70 stm32f1x options vrite sess 70 stm32f1x unlock Asa riet Enio rI aes 70 Stmn32f2x oce kbes eb E E sade PHP Rn REPE ni Stnsmi debba e pacte ve he RU DH APER Yong 64 inge qe EET cal str7x diesable jtag ccc eee eee T1 EE T1 str9r flash conflg ch pec peer TL ciaee hao e nine ite esd hh abe iad venkat adene ae 73 str9xpec disable turbo 73 str9xpec enable turbo sess 73 E LOCk occimeseceetneb leve mede uet 73 str9xpec options map 73 str9xpec options Ludeel 73 str9xpec options Lvdtbhd es 73 str9xpec options_lvdwarn T3 str9xpec options read 73 str9xpec options vrite sss 13 StrOxpec part E DEE 73 StrOxpec UNLOCK ivan lee peer uen RE Id 13 GE 104 GE 39 swd wer trn prescale esee eee 39 T target counb sees heb kb ARR Ra n nants E 52 target EE 55 target current Leder dica lp e ques 52 target names eet dd Neie E ueber ig 52 target number esci eii de ee err ed tsk 53 target EE 53 target request debugmsgs
63. B Blaster compatibles over one of the userspace libraries for FTDI chips These interfaces have several commands used to configure the driver before initializing the JTAG scan chain usb_blaster_device_desc description Config Command Provides the USB device description the Product string of the FTDI FT245 device If not specified the FTDI default value is used This setting is only valid if compiled with FTD2XX support usb_blaster_vid_pid vid pid Config Command The vendor ID and product ID of the FTDI FT245 device If not specified default values are used Currently only one vid pid pair may be given e g for Altera USB Blaster default usb blaster vid pid OxO9FB 0x6001 The following VID PID is for Kolja Waschk s USB JTAG usb blaster vid pid 0x16CO Ox06AD usb blaster pin6 pin8 0 1 Command Sets the state of the unused GPIO pins on USB Blasters pins 6 and 8 on the female JTAG header These pins can be used as SRST and or TRST provided the appropriate connections are made on the target board For example to use pin 6 as SRST as with an AVR board TARGETNAME configure event reset assert usb blaster pin6 1 wait 1 usb blaster pin6 0 gw16012 Interface Driver Gateworks GW16012 JTAG programmer This has one driver specific command parport port port number Config Command Display either the address of the I O port default 0x378 for LPT1 or the number of the dev parport devi
64. ESET state You may use enable to highlight the default state the TAP is linked in See Enabling and Disabling TAPs page 49 e expected id number A non zero number represents a 32 bit IDCODE which you expect to find when the scan chain is examined These codes are not required by all JTAG devices Repeat the option as many times as required if more than one ID code could appear for example multiple versions Specify number as zero to suppress warnings about IDCODE values that were found but not included in the list Provide this value if at all possible since it lets OpenOCD tell when the scan chain it sees isn t right These values are provided in vendors chip documentation usually a technical reference manual Sometimes you may need to probe the JTAG hardware to find these values See Autoprobing page 50 e ignore version Specify this to ignore the J TAG version field in the expected id option When vendors put out multiple versions of a chip or use the same JTAG level ID for several largely compatible chips it may be more practical to ignore the version field than to update config files to handle all of the various chip IDs e ircapture NUMBER The bit pattern loaded by the TAP into the JTAG shift register on entry to the IRCAPTURE state such as 0x01 JTAG requires the two LSBs of this value to be 01 By default ircapture and irmask are set up to verify that two bit value You may provide additional bits if you know t
65. If JTAG communication is working OpenOCD will see each TAP and report what expected id to use with it 2 IR Length discovery Unfortunately J TAG does not provide a reliable way to find out the value of the irlen parameter to use with a TAP that is discovered If OpenOCD can discover the length of a T AP s instruction register it will report it Otherwise you may need to consult vendor documentation such as chip data sheets or BSDL files In many cases your board will have a simple scan chain with just a single device Here s what OpenOCD reported with one board that s a bit more complex clock speed 8 kHz There are no enabled taps AUTO PROBING MIGHT NOT WORK AUTO autoO tap use jtag newtap auto tap expected id Ox2b900f0f AUTO autoi tap use jtag newtap autol tap expected id 0x07926001 AUTO auto2 tap use jtag newtap auto2 tap expected id OxOb73bO2f AUTO autoO tap use irlen 4 AUTO autoi tap use irlen 4 AUTO auto2 tap use irlen 6 no gdb ports allocated as no target has been specified Given that information you should be able to either find some existing config files to use or create your own If you create your own you would configure from the bottom up first a target cfg file with these TAPs any targets associated with them and any on chip resources then a board cfg with off chip resources clocking and so forth Chapter 11 CPU Configuration 5
66. Info JTAG tap 1m3s cpu tap device found 0x3ba00477 mfg Ox23b part Oxba00 ver 0x3 Seeing that tap device found message and no warnings means the JTAG communication is working That s a key milestone but you ll probably need more project specific setup 4 2 What OpenOCD does as it starts OpenOCD starts by processing the configuration commands provided on the command line or if there were no c command or f file cfg options given in openocd cfg See Configuration Stage page 29 At the end of the configuration stage it verifies the JTAG scan chain defined using those commands your configuration should ensure that this always succeeds Normally OpenOCD then starts running as a daemon Alternatively commands may be used to terminate the configuration stage early perform work such as updating some flash memory and then shut down without acting as a daemon Once OpenOCD starts running as a daemon it waits for connections from clients Telnet GDB Other and processes the commands issued through those channels If you are having problems you can enable internal debug messages via the d option Also it is possible to interleave Jim Tcl commands w config scripts using the c command line switch To enable debug output when reporting problems or working on OpenOCD itself use the d command line switch This sets the debug Level to 3 outputting the most information including debu
67. ME fm3 O O O O TARGETNAME 12 4 3 str9xpec driver Here is some background info to help you better understand how this driver works OpenOCD has two flash drivers for the str9 1 Standard driver str9x programmed via the str9 core Normally used for flash pro gramming as it is faster than the str9xpec driver 2 Direct programming str9xpec using the flash controller This is an ISC compilant IEEE 1532 tap connected in series with the str9 core The str9 core does not need to be running to program using this flash driver Typical use for this driver is lock ing unlocking the target and programming the option bytes Before we run any commands using the str9xpec driver we must first disable the str9 core This example assumes the str9xpec driver has been configured for flash bank 0 assert srst we do not want core running while accessing str9xpec flash driver jtag_reset 0 1 turn off target polling poll off disable str9 core strOxpec enable turbo 0 read option bytes strOxpec options read 0 re enable str9 core str9xpec disable turbo 0 poll on reset halt The above example will read the str9 option bytes When performing a unlock remember that you will not be able to halt the str9 it has been locked Halting the core is not required for the str9xpec driver as mentioned above just issue the commands above manually or from a telnet prompt Chapter 12 Flash Commands T3 st
68. MLC controller mode but won t change SLC behavior orion NAND Driver These controllers require an extra nand device parameter the address of the con troller nand device orion 0xd8000000 These controllers don t define any specialized commands At this writing their drivers don t include write page or read page methods so nand raw access won t change any behavior 3c2410 NAND Driver 3c2412 NAND Driver s3c2440 NAND Driver s3c2443 NAND Driver s3c6400 NAND Driver These S3C family controllers don t have any special nand device options and don t define any specialized commands At this writing their drivers don t include write_ page or read_page methods so nand raw_access won t change any behavior Chapter 14 PLD FPGA Commands 81 14 PLD FPGA Commands Programmable Logic Devices PLDs and the more flexible Field Programmable Gate Ar rays FPGAs are both types of programmable hardware OpenOCD can support program ming them Although PLDs are generally restrictive cells are less functional and there are no special purpose cells for memory or computational tasks they share the same OpenOCD infrastructure Accordingly both are called PLDs here 14 1 PLD FPGA Configuration and Commands As it does for JTAG TAPs debug targets and flash chips both NOR and NAND OpenOCD maintains a list of PLDs available for use in various commands Also each such PLD requires a driver They are referenced by the nu
69. Non Disclosure Agreement NDA Sometimes there are chip specific extensions like a requirement to use the normally optional TRST signal precluding use of JTAG adapters which don t pass TRST through or needing extra steps to complete a TAP reset In short SRST and especially TRST handling may be very finicky needing to cope with both architecture and board specific constraints 9 3 Commands for Handling Resets adapter nsrst assert width milliseconds Command Minimum amount of time in milliseconds OpenOCD should wait after asserting nSRST active low system reset before allowing it to be deasserted adapter nsrst delay milliseconds Command How long in milliseconds OpenOCD should wait after deasserting nSRST active low system reset before starting new JTAG operations When a board has a reset button connected to SRST line it will probably have hardware debouncing implying you should use this Chapter 9 Reset Configuration 43 jtag ntrst assert width milliseconds Command Minimum amount of time in milliseconds OpenOCD should wait after asserting nTRST active low JTAG TAP reset before allowing it to be deasserted jtag ntrst delay milliseconds Command How long in milliseconds OpenOCD should wait after deasserting nTRST active low JTAG TAP reset before starting new JTAG operations reset config mode_flag Command This command displays or modifies the reset configuration of your combination of JTAG board
70. OR d 18 14 PLD FPGA Commands eet EL CER ot e 81 15 General Commands se 4 and Peowaad aie EARS eR das 82 16 Architecture and Core Commandes 88 KOENEN 101 18 Boundary Scan Commands e 2722 dur gn de rud 104 19 DEED dig a nae ae dala ane Rd ae calpain tai hae ae s 105 20 GDB and eet EE 228226 svcese REED eve Mee taxis eee 106 21 TpglocHnpongPL 22a hee we Seek oe ee a ee o 110 DO TG EMT 112 Zu Wel rash Cours rere sace thane ea de ob be were woes oa 117 A The GNU Free Documentation License 64 123 OpenOCD Concept Index 222ssoese goo ks 130 Command and Driver Inder 132 Table of Contents Pun M m 1 What is Open 1 OpenOCD Web te 2 Latest User s Guide 2 OpenOCD User s komm 2 1 OpenOCD Developer Resources 3 1 1 OpenOCD GIT Repnoaitorg 0 eee eee 3 1 2 Doxygen Developer Manual 3 1 8 OpenOCD Developer Mailing List 3 1 4 OpenOCD Bug Database 00 ne eens 4 2 Debug Adapter Hardware 5 2 1 Choosing a Dongle eh 5 2 2 Stand alone Systems crani ipene ipi penik EES 5 2 3 USB ET2232 Based tie tuned aee tombe ake eae 5 2 4 USB JTAG Altera USB Blaster compatibles 6 2 5 USB JLINK based per did usage E RIS madame 7 2 6 USB RLINK baseg sua ERNEIEREN NEE dE 7 2 7 USB Other de ER ey sae es ded deena E ERE RR 7 2 8 IBM PC Parallel Printer Port Base d KENE TEE 8 3 About Jm Pol o deir ti e e POR et 9 A a rc
71. Open On Chip Debugger OpenOCD User s Guide for release 0 5 0 9 August 2011 This User s Guide documents release 0 5 0 dated 9 August 2011 of the Open On Chip Debugger OpenOCD Copyright 2008 The OpenOCD Project Copyright 2007 2008 Spencer Oliver spen spen soft co uk Copyright 2008 2010 Oyvind Harboe oyvind harboe zylin com Copyright c 2008 Duane Ellis openocd duaneellis com Copyright 2009 2010 David Brownell Permission is granted to copy distribute and or modify this document under the terms of the GNU Free Documentation License Version 1 2 or any later version published by the Free Software Foundation with no Invariant Sections with no Front Cover Texts and with no Back Cover Texts A copy of the license is included in the section entitled GNU Free Documentation License Short Contents EE 1 1 OpenOCD Developer Resource 3 2 Debug Adapter Hardware 5 s About time Wl selene Rr ERE e eye Ee tac 9 GE ors e pu aews wa EE 10 5 OpenOCD Project Setup 0 cece eee eee ee eee 12 6 Config File Guidelines ee Edge Ke e Eed 19 7 Daemon Configuration zo 22b eaa er rem 29 8 Debug Adapter Configuration llle 33 9 Reset Configuration S as od aru V Pd bed wee Ee ruoli ERR 41 ID TAP Declaration s s schade Sp Nee tae ee RU EO ete 46 11 CPU Conbmiratlol cos Rem RE EE SE A 52 12 Flash Commands uh aca ayaa dior dex i Rad Cd d di d o d id ad 61 13 NAND Flash Commands Vert 4 2 wet Sox ORA RC RACE
72. The board configuration file may make use of this variable to configure things like a reset init script or other things specific to that board and that target If the chip has 2 targets the names are TARGETNAMEO _TARGETNAME1 etc Chapter 6 Config File Guidelines 23 6 2 3 The reset init Event Handler Board config files run in the OpenOCD configuration stage they can t use TAPs or targets since they haven t been fully set up yet This means you can t write memory or access chip registers you can t even verify that a flash chip is present That s done later in event handlers of which the target reset init handler is one of the most important Except on microcontrollers the basic job of reset init event handlers is setting up flash and DRAM as normally handled by boot loaders Microcontrollers rarely use boot loaders they run right out of their on chip flash and SRAM memory But they may want to use one of these handlers too if just for developer convenience Note Because this is so very board specific and chip specific no examples are included here Instead look at the board config files distributed with OpenOCD If you have a boot loader its source code will help so will configura tion files for other J TAG tools see Translating Configuration Files page 28 Some of this code could probably be shared between different boards For example setting up a DRAM controller often doesn t differ by much except the bus wi
73. This is a software breakpoint unless hw is specified in which case it will be a hardware breakpoint See arm9 vector_catch page 93 or see xscale vector_catch page 97 for similar mechanisms that do not consume hardware breakpoints rbp address Command Remove the breakpoint at address rwp address Command Remove data watchpoint on address wp address len r w a value mask Command With no parameters lists all active watchpoints Else sets a data watchpoint on data from address for length bytes The watch point is an access watchpoint unless the r or w parameter is provided defining it as respectively a read or write watchpoint If a value is provided that value is used when determining if the watchpoint should trigger The value may be first be masked using mask to mark don t care fields 15 7 Misc Commands profile seconds filename Command Profiling samples the CPU s program counter as quickly as possible which is useful for non intrusive stochastic profiling Saves up to 10000 sampines in filename using emon out format version Command Displays a string identifying the version of this OpenOCD server virt2phys virtual address Command Requests the current target to map the specified virtual_address to its corresponding physical address and displays the result Chapter 16 Architecture and Core Commands 88 16 Architecture and Core Commands Mos
74. and target in target configuration scripts Information earlier in this section describes the kind of problems the command is intended to address see SRST and TRST Issues page 41 As a rule this command belongs only in board config files describing issues like board doesn t connect TRST or in user config files addressing limitations derived from a particular combination of interface and board An unlikely example would be using a TRST only adapter with a board that only wires up SRST The mode flag options can be specified in any order but only one of each type signals combination gates trst type and srst type may be specified at a time If you don t provide a new value for a given type its previous value perhaps the default is unchanged For example this means that you don t need to say anything at all about TRST just to declare that if the JTAG adapter should want to drive SRST it must explicitly be driven high erst push pull e signals can specify which of the reset signals are connected For example If the J TAG interface provides SRST but the board doesn t connect that signal properly then OpenOCD can t use it Possible values are none the default trst_only srst_only and trst_and_srst Tip If your board provides SRST and or TRST through the JTAG connector you must declare that so those signals can be used e The combination is an optional value specifying broken reset signal impl
75. apter It is an example of a micro controller based JTAG adapter it uses an AT91SAM 764 internally ATMEL SAMICE Only works with ATMEL chips Link http www atmel com dyn products tools_card asp tool_id 3892 SEGGER JLINK Link http www segger com jlink html IAR J Link Link http www iar com website1 1 0 1 0 369 1 index php 2 6 USB RLINK based Raisonance has an adapter called RLink It exists in a stripped down form on the STM32 Primer permanently attached to the JTAG lines It also exists on the STM32 Primer2 but that is wired for SWD and not JTAG thus not supported Raisonance RLink Link http www raisonance com products RLink php STM32 Primer Link http www stm32circle com resources stm32primer php STM32 Primer2 Link http www stm32circle com resources stm32primer2 php 2 7 USB Other USBprog Link http www embedded projects net usbprog which uses an Atmel MEGA32 and a UBN9604 USB Presto Link http tools asix net prg presto htm Versaloon Link Link http www simonqian com en Versaloon ARM JTAG EW Link http www olimex com dev arm jtag ew html Buspirate Link http dangerousprototypes com bus pirate manual 2 8 IBM PC Parallel Printer Port Based The two well known JTAG Parallel Ports cables are the Xilnx DLC5 and the MacGraigor Wiggler There are many clones and variations of these on the market Chapter 2 Debug Adapter Hardware 8 Note that parallel ports are becoming much
76. are You may find them useful e suf2xsuf converts SVF files into the extended XSVF syntax understood by the xsvf command see notes below e xzsufdump converts XSVF files into a text output format understands the OpenOCD extensions The input format accepts a handful of non standard extensions These include three op codes corresponding to SVF extensions from Lattice Semiconductor LCOUNT LDELAY LDSR and two opcodes supporting a more accurate translation of SVF XTRST XWAIT STATE If zsufdump shows a file is using those opcodes it probably will not be usable with other XSVF tools Chapter 19 TFTP 105 19 TFTP If OpenOCD runs on an embedded host as ZY 1000 does then TFTP can be used to access files on PCs either the developer s PC or some other PC The way this works on the ZY1000 is to prefix a filename by tftp ip and append the TFTP path on the TFTP server tftpd For example load image tftp 10 0 0 96 c NtempNabc elf will load c temp abc elf from the developer pc 10 0 0 96 into memory as if the file was hosted on the embedded host In order to achieve decent performance you must choose a TFTP server that supports a packet size bigger than the default packet size 512 bytes There are numerous TFTP servers out there free and commercial and you will have to do a bit of googling to find something that fits your requirements Chapter 20 GDB and OpenOCD 106 20 GDB and OpenOCD OpenOCD complies with t
77. are provides dedicated breakpoints for certain hardware events The specific bit values are core specific as in fact is using coprocessor 14 register 7 itself but all current ARM11 cores except the ARM1176 use the same six bits 16 5 ARMv7 Architecture 16 5 1 ARMv7 Debug Access Port DAP specific commands These commands are specific to ARM architecture v7 Debug Access Port DAP included on Cortex M3 and Cortex A8 systems They are available in addition to other core specific commands that may be available dap apid num Command Displays ID register from AP num defaulting to the currently selected AP dap apsel num Command Select AP num defaulting to 0 dap baseaddr num Command Displays debug base address from MEM AP num defaulting to the currently selected AP dap info num Command Displays the ROM table for MEM AP num defaulting to the currently selected AP dap memaccess value Command Displays the number of extra tck cycles in the J TAG idle to use for MEM AP memory bus access 0 255 giving additional time to respond to reads If value is defined first assigns that 16 5 2 Cortex M3 specific commands cortex m3 maskisr auto on off Command Control masking disabling interrupts during target step resume The auto option handles interrupts during stepping a way they get served but don t disturb the program flow The step command first allows pending interrupt handlers
78. are technologies NOR flash usually supports direct CPU instruction and data bus access while data from a NAND flash must be copied to memory before it can be used SPI flash must also be copied to memory before use However the documentation also uses flash as a generic term for example Put flash configuration in board specific files Flash Steps 1 Configure via the command flash bank Do this in a board specific configuration file passing parameters as needed by the driver 2 Operate on the flash via flash subcommand Often commands to manipulate the flash are typed by a human or run via a script in some automated way Common tasks include writing a boot loader operating system or other data 3 GDB Flashing Flashing via GDB requires the flash be configured via flash bank and the GDB flash features be enabled See GDB Configuration page 30 Many CPUs have the ablity to boot from the first flash bank This means that mis programming that bank can brick a system so that it can t boot JTAG tools like OpenOCD are often then used to de brick the board by re installing working boot firmware 12 1 Flash Configuration Commands flash bank name driver base size chip_width bus_width target Config Command driver options Configures a flash bank which provides persistent storage for addresses from base to base size 1 These banks will often be visible to GDB through the target s memory map In s
79. argets in the list halt command triggers the halt of all targets in the list resume command triggers the write context and the restart of all targets in the list following a breakpoint the target stopped by the breakpoint is displayed to the GDB session dedicated GDB serial protocol packets are implemented for switching retrieving the target displayed by the GDB session see Using openocd SMP with GDB page 108 The SMP behaviour can be disabled enabled dynamically On cortex_a8 following command have been implemented cortex a8 smp on enable SMP mode behaviour is as described above cortex_a8 smp off disable SMP mode the current target is the one displayed in the GDB session only this target is now controlled by GDB session This behaviour is useful during system boot up cortex a8 smp_gdb display fix the core id displayed in GDB session see following example gt cortex_a8 smp_gdb gdb coreid 0 gt 1 0 coreid O is displayed to GDB gt 1 next resume triggers a real resume gt cortex a8 emp gdb 1 gdb coreid 0 gt 1 0 coreid D is displayed to GDB gt 1 next resume displays coreid 1 to GDB gt resume gt cortex_a8 smp_gdb gdb coreid 1 gt 1 1 coreid 1 is displayed to GDB gt 1 next resume displays coreid 1 to GDB gt cortex a8 smp gdb 1 gdb coreid 1 gt 1 1 coreid 1 is displayed to GDB gt 1 next resume triggers a real resume Chapter 6 Config File Guid
80. assert has been triggered or the target asserted SRST on the entire scan chain e reset deassert pre Issued as part of reset processing after reset assert post has been triggered e reset deassert post Issued as part of reset processing after reset deassert pre has been triggered and if the target is using it after SRST has been released on the scan chain e reset end Issued as the final step in reset processing e reset init Used by reset init command for board specific initialization This event fires after reset deassert post This is where you would configure PLLs and clocking set up DRAM so you can down load programs that don t fit in on chip SRAM set up pin multiplexing and so on You may be able to switch to a fast JTAG clock rate here after the target clocks are fully set up e reset start Issued as part of reset processing before reset init is called This is the most robust place to use jtag rclk or adapter khz to switch to a low JTAG clock rate when reset disables PLLs needed to use a fast clock e resume start Before any target is resumed Chapter 11 CPU Configuration e resume end After all targets have resumed e resume ok Success e resumed Target has resumed 60 Chapter 12 Flash Commands 61 12 Flash Commands OpenOCD has different commands for NOR and NAND flash the flash command works with NOR flash while the nand command works with NAND flash This partially reflects different hardw
81. ate Also see target curstate page 57 If that target is in debug mode architecture specific information about the current state is printed An optional parameter allows background polling to be enabled and disabled You could use this from the TCL command shell or from GDB using monitor poll command Leave background polling enabled while you re using GDB gt poll background polling on target state halted target halted in ARM state due to debug request current mode Supervisor cpsr 0x800000d3 pc 0x11081bfc MMU disabled D Cache disabled I Cache enabled gt Chapter 8 Debug Adapter Configuration 33 8 Debug Adapter Configuration Correctly installing OpenOCD includes making your operating system give OpenOCD ac cess to debug adapters Once that has been done Tcl commands are used to select which one is used and to configure how it is used Note Because OpenOCD started out with a focus purely on JTAG you may find places where it wrongly presumes JTAG is the only transport protocol in use Be aware that recent versions of OpenOCD are removing that limitation JTAG remains more functional than most other transports Other transports do not support boundary scan operations or may be specific to a given chip vendor Some might be usable only for programming flash memory instead of also for debugging Debug Adapters Interfaces Dongles are normally configured through commands in an in terface configuration fi
82. ce If a parameter is provided first switch to use that port This is a write once setting jlink Interface Driver Segger jlink USB adapter parport Interface Driver Supports PC parallel port bit banging cables Wigglers PLD download cable and more These interfaces have several commands used to configure the driver before initializing the JTAG scan chain Chapter 8 Debug Adapter Configuration 37 parport_cable name Config Command Set the layout of the parallel port cable used to connect to the target This is a write once setting Currently valid cable name values include altium Altium Universal JTAG cable arm jtag Same as original wiggler except SRST and TRST connections reversed and TRST is also inverted chameleon The Amontec Chameleon s CPLD when operated in configu ration mode This is only used to program the Chameleon itself not a connected target dlc5 The Xilinx Parallel cable III flashlink The ST Parallel cable lattice Lattice ispDOWNLOAD Cable old_amt_wiggler The Wiggler configuration that comes with some versions of Amontec s Chameleon Programmer The new version available from the website uses the original Wiggler layout wiggler triton The parallel port adapter found on the Karo Triton 1 Develop ment Board This is also the layout used by the HollyGates design see http www lartmaker nl projects jtag wiggler The original Wiggler layout also supported by several clones such a
83. cfg axm0432 cfg jtagkey2 cfg parport dlcb5 cfg calao usb a9260 cOi cfg jtagkey cfg rlink cfg calao usb a9260 c02 cfg jtagkey tiny cfg sheevaplug cfg calao usb a9260 cfg luminary cfg signalyzer cfg chameleon cfg luminary icdi cfg stm32 stick cfg cortino cfg luminary 1m3s811 cfg turtelizer2 cfg dummy cfg olimex arm usb ocd cfg usbprog cfg flyswatter cfg olimex jtag tiny cfg vsllink cfg e board think Circuit Board PWA PCB they go by many names Board files contain initialization items that are specific to a board They reuse target configuration files since the same microprocessor chips are used on many boards but support for external parts varies widely For example the SDRAM initialization sequence for the board or the type of external flash and what address it uses Any initialization sequence to enable that external flash or SDRAM should be found in the board file Boards may also contain multiple targets two CPUs or a CPU and an FPGA 1s board arm evaluatorT7t cfg at91rm9200 dk cfg at91sam9g20 ek cfg atmel at91sam7s ek cfg atmel at91sam9260 ek cfg atmel sam3u ek cfg crossbow tech imote2 cfg csb337 cfg csb732 cfg digi_connectcore_wi 9c cfg dm355evm cfg dm365evm cfg dm6446evm cfg eir cfg ek 1m3s1968 cfg ek 1m3s3748 cfg keil mcbi700 cfg keil_mcb2140 cfg linksys_nslu2 cfg logicpd_imx27 cfg mini2440 cfg olimex_LPC2378STK cfg olimex_lpc_h2148 cfg olimex_sam7_ex256 cfg olimex_sam9_19260 cfg olimex_s
84. citly declared SWD uses fewer signal wires than JTAG SWD is debug oriented and does not support boundary scan testing Flash programming support is built on top of debug support Some processors support both J TAG and SWD swd newdap Command Declares a single DAP which uses SWD transport Parameters are currently the same as jtag newtap but this is expected to change swd wcr trn prescale Command Updates TRN turnaraound delay and prescaling fields of the Wire Control Register WCR No parameters displays current settings 8 3 3 SPI Transport The Serial Peripheral Interface SPI is a general purpose transport which uses four wire signaling Some processors use it as part of a solution for flash programming 8 4 JTAG Speed JTAG clock setup is part of system setup It does not belong with interface setup since any interface only knows a few of the constraints for the JTAG clock speed Sometimes the JTAG speed is changed during the target initialization process 1 slow at reset 2 program the CPU clocks 3 run fast Both the slow and fast clock rates are functions of the oscillators used the chip the board design and sometimes power management software that may be active The speed used during reset and the scan chain verification which follows reset can be adjusted using a reset start target event handler It can then be reconfigured to a Chapter 8 Debug Adapter Configuration 40 faster speed by a reset
85. configure 222cide a p I LA nid 49 Jtag names lex m Gur v uer HORT aie 4T jtag newLap o s erelecdebee tp de p9bedg denies EU 47 jtag tapdisabl cssc tage ERES 50 jtag tapenable 2 5 26 ooiesosasi ces ee err gas 50 jtag tapisensbled 6 cece eae 50 jtag EE Serge heten Ree PRPPREEG E 29 jtag_ntrst_assert_width 43 jtag ntrst delay e Ree ie 43 Jtag rClk i iiia ede epeRESEPERR IE Y eee 40 jtag reset i secnndo d eredi Ese ded 102 L load image oe IER DAR I DIS IDEAE 86 log o tputi i2e6 rts irarri ine IP IAE 83 RL ere RD I LHPPIe T EET 67 lpc2000 part id eoi RR bats 67 Bh hehe Gee goa eas 67 PODS o NER PME 67 Ipc2900 password vile b RES 68 1pc2900 read custom 68 lpc2900 secure_jtag cece cece cence eee 69 1pc2900 secure seckor esses 69 lpc2900 eiensature 68 lpc2900 write custom 68 EE 80 Ipc3180 select isi Ree iit Rates 80 EE 85 M MAC ko EET 85 MD EE 85 EE 85 MO Wise I keds ce clita dade ruere ed dut 85 EE 85 nflash bank e ele ety eque Tim brin 73 mflash config boot 74 nflash config pll sessie 24 eek hn rans 74 mflash config etorage eee aan 74 nflash domm 252s ee rre eve rr EROR ng 74 nflash probe dE dech oe cae PER 74 nflash write oicsicesne E sei eI DEREN 74 UL EE 86 nva D 86 ip P M 86 Command and Driver Index N nand check bad blocks nnno 78 NANG device sae awe peri eed 76 nand Op ee SE aA Nee cee wee
86. data in filename etm image filename base address type Command Opens an image file etm load filename Command Loads captured trace data from filename etm start Command Starts trace data collection etm stop Command Stops trace data collection Chapter 16 Architecture and Core Commands 91 16 1 3 Trace Port Drivers To use an ETM trace port it must be associated with a driver dummy Trace Port Driver Use the dummy driver if you are configuring an ETM that s not connected to anything on chip ETB or off chip trace connector This driver lets OpenOCD talk to the ETM but it does not expose any trace data collection etm_dummy config target Config Command Associates the ETM for target with a dummy driver etb Trace Port Driver Use the etb driver if you are configuring an ETM to use on chip ETB memory etb config target etb_tap Config Command Associates the ETM for target with the ETB at etb_tap You can see the ETB registers using the reg command etb trigger_percent percent Command This displays or optionally changes ETB behavior after the ETM s configured trigger event fires It controls how much more trace data is saved after the single trace trigger becomes active e The default corresponds to trace around usage recording 50 percent data before the event and the rest afterwards e The minimum value of percent is 2 percent recording almost exclusively data b
87. des unique IDs and more than one F T2232 device is connected to the host If not specified serial numbers are not considered Note that USB serial numbers can be arbitrary Unicode strings and are not restricted to containing only decimal digits ft2232 layout name Config Command Each vendor s FT2232 device can use different GPIO signals to control output enables reset signals and LEDs Currently valid layout name values include Chapter 8 Debug Adapter Configuration 35 axm0432_jtag Axiom AXM 0432 comstick Hitex STR9 comstick cortino Hitex Cortino JTAG interface evb_lm3s811 Luminary Micro EVB_LM38811 as a JTAG interface either for the local Cortex M3 SRST only or in a passthrough mode neither SRST nor TRST This layout can not support the SWO trace mechanism and should be used only for older boards before rev C luminary_icdi This layout should be used with most Luminary eval boards including Rev C LM3S811 eval boards and the eponymous ICDI boards to debug either the local Cortex M3 or in passthrough mode to debug some other target It can support the SWO trace mechanism flyswatter Tin Can Tools Flyswatter icebear ICEbear JTAG adapter from Section 5 jtagkey Amontec JTAGkey and JTAGkey Tiny and compatibles jtagkey2 Amontec JTAGkey2 and compatibles m5960 American Microsystems M5960 olimex jtag Olimex ARM USB OCD and ARM USB Tiny oocdlink OOCDLink redbee econ
88. dsp563xx implements Freescale s 24 bit DSP Support for this is still incom plete e fa526 resembles arm920 w o Thumb e feroceon resembles arm926 e mips m4k a MIPS core This supports one variant e xscale this is actually an architecture not a CPU type It is based on the ARMv5 architecture There are several variants defined ixp42x ixp45x ixp46x pxa27x instruction register length is 7 bits pxa250 pxa255 pxa26x instruction register length is 5 bits pxa3xx instruction register length is 11 bits To avoid being confused by the variety of ARM based cores remember this key point ARM is a technology licencing company See http www arm com The CPU name used by OpenOCD will reflect the CPU design that was licenced not a vendor brand which incorporates that design Name prefixes like arm7 arm9 arm11 and cortex reflect design generations while names like ARMv4 ARMv5 ARMv6 and ARMv7 reflect an architecture version implemented by a CPU design 11 3 Target Configuration Before creating a target you must have added its TAP to the scan chain When you ve added that TAP you will have a dotted name which is used to set up the CPU support The chip specific configuration file will normally configure its CPU s right after it adds all of the chip s TAPs to the scan chain Although you can set up a target in one step it s often clearer if you use shorter commands and do it in two steps
89. dth 16 bits or 327 and memory timings so a reusable TCL procedure loaded by the target cfg file might take those as parameters Similarly with oscillator PLL and clock setup and disabling the watchdog Structure the code cleanly and provide comments to help the next developer doing such work You might be that next person trying to reuse init code The last thing normally done in a reset init handler is probing whatever flash memory was configured For most chips that needs to be done while the associated target is halted either because JTAG memory access uses the CPU or to prevent conflicting CPU access 6 2 4 JTAG Clock Rate Before your reset init handler has set up the PLLs and clocking you may need to run with a low JTAG clock rate See JTAG Speed page 39 Then you d increase that rate after your handler has made it possible to use the faster JTAG clock When the initial low speed is board specific for example because it depends on a board specific oscillator speed then you should probably set it up in the board config file if it s target specific it belongs in the target config file For most ARM based processors the fastest J TAG clock is one sixth of the CPU clock or one eighth for ARM11 cores Consult chip documentation to determine the peak JTAG clock rate which might be less than that Warning On most ARMs JTAG clock detection is coupled to the core clock so software using a wait for interrupt operatio
90. e able to source one of these files with a command like this source find board FOOBAR cfg The point of a board config file is to package everything about a given board that user config files need to know In summary the board files should contain if present 1 One or more source target cfg statements NOR flash configuration see NOR Configuration page 61 NAND flash configuration see NAND Configuration page 75 Target reset handlers for SDRAM and I O configuration JTAG adapter reset configuration see Chapter 9 Reset Configuration page 41 Props dee sg 6 All things that are not inside a chip Generic things inside target chips belong in target config files not board config files So for example a reset init event handler should know board specific oscillator and PLL parameters which it passes to target specific utility code The most complex task of a board config file is creating such a reset init event handler Define those handlers last after you verify the rest of the board configuration works 6 2 1 Communication Between Config files In addition to target specific utility code another way that board and target config files communicate is by following a convention on how to use certain variables The full Tcl Tk language supports namespaces but Jim Tcl does not Thus the rule we follow in OpenOCD is this Variables that begin with a leading underscore are temporary in nature and can be modifi
91. e than just the instruction set It also indicates how that instruction set is implemented what kind of debug support it integrates whether it has an MMU and if so what kind what core specific commands may be available see Chapter 16 Architecture and Core Commands page 88 and more For some CPU types OpenOCD also defines variants which indicate differences that affect their handling For example a particular implementation bug might need to be worked around in some chip versions It s easy to see what target types are supported since there s a command to list them However there is currently no way to list what target variants are supported other than by reading the OpenOCD source code target types Command Lists all supported target types At this writing the supported CPU types and variants are e armii this is a generation of ARMv6 cores e arm720t this is an ARMv4 core with an MMU e arm7tdmi this is an ARMv4 core e arm920t this is an ARMv4 core with an MMU e arm926ejs this is an ARMv5 core with an MMU e arm966e this is an ARMv5 core e arm9tdmi this is an ARMv4 core e avr implements Atmel s 8 bit AVR instruction set Support for this is prelim inary and incomplete e cortex a8 this is an ARMv7 core with an MMU e cortex m3 this is an ARMv7 core supporting only the compact Thumb2 in struction set Chapter 11 CPU Configuration 54 e dragonite resembles arm966e e
92. e the JTAG clock using the core clock Low power states which stop that core clock thus prevent JTAG access Idle loops in tasking environments often enter those low power states via the WFI instruction or its coprocessor equivalent before ARMv7 You may want to disable that instruction in source code or otherwise prevent using that state to ensure you can get JTAG access at any time For example the OpenOCD halt command may not work for an idle processor otherwise e Delay after reset Not all chips have good support for debugger access right after reset many LPC2xxx chips have issues here Similarly applications that reconfigure pins used for J TAG access as they start will also block debugger access To work with boards like this enable a short delay loop the first thing after reset before real startup activities For example one second s delay is usually more than enough time for a JTAG debugger to attach so that early code execution can be debugged or firmware can be replaced e Debug Communications Channel DCC Some processors include mechanisms to send messages over JTAG Many ARM cores support these as do some cores from other vendors OpenOCD may be able to use this DCC internally speeding up some operations like writing to memory Your application may want to deliver various debugging messages over J TAG by linking with a small library of code provided with OpenOCD and using the utilities there to send various
93. e used to change various features including how the low power states are clocked while debugging The STM32 DBGMCU_CR register is an example at the cost of extra power consumption JTAG can be used during low power states Chapter 5 OpenOCD Project Setup 18 e Memory Addressing Boards which support multiple boot modes may also have jumpers to configure memory addressing One board for example jumpers external chipselect 0 used for booting to address either a large SRAM which must be pre loaded via JTAG NOR flash or NAND flash When it s jumpered to address NAND flash that board must also be told to start booting from on chip ROM Your board cfg file may also need to be told this jumper configuration so that it can know whether to declare NOR flash using flash bank or instead declare NAND flash with nand device and likewise which probe to perform in its reset init handler A closely related issue is bus width Jumpers might need to distinguish between 8 bit or 16 bit bus access for the flash used to start booting e Peripheral Access Development boards generally provide access to every periph eral on the chip sometimes in multiple modes such as by providing multiple audio codec chips This interacts with software configuration of pin multiplexing where for example a given pin may be routed either to the MMC SD controller or the GPIO controller It also often interacts with configuration jumpers One jumper may be us
94. ect command Example for a 125 MHz clock frequency flash bank _FLASHNAME 1pc29000 00 O TARGETNAME 125000 Some lpc2900 specific commands are defined In the following command list the bank parameter is the bank number as obtained by the flash banks command 1pc2900 signature bank Command Calculates a 128 bit hash value the signature from the whole flash content This is a hardware feature of the flash block hence the calculation is very fast You may use this to verify the content of a programmed device against a known signature Example lpc2900 signature 0 signature Ox5f40cdc8 0xc64e592e 0x10490f89 0x32a0f317 1pc2900 read custom bank filename Command Reads the 912 bytes of customer information from the flash index sector and saves it to a file in binary format Example 1pc2900 read custom 0 path to customer info bin The index sector of the flash is a write only sector It cannot be erased In order to guard against unintentional write access all following commands need to be preceeded by a successful call to the password command 1pc2900 password bank password Command You need to use this command right before each of the following commands lpc2900 write_custom lpc2900 secure sector lpc2900 secure_jtag The password string is fixed to I know what I am doing Example lpc2900 password O I know what I am doing Potentially dangerous operation allowed in next command lpc2900 write custom bank file
95. ed Version Only one passage of Front Cover Text and one of Back Cover Text may be added by or through arrangements made by any one entity If the Document already includes a cover text for the same cover previously added by you or by arrangement made by the same entity you are acting on behalf of you may not add another but you may replace the old one on explicit permission from the previous publisher that added the old one The author s and publisher s of the Document do not by this License give permission to use their names for publicity for or to assert or imply endorsement of any Modified Version 5 COMBINING DOCUMENTS You may combine the Document with other documents released under this License under the terms defined in section 4 above for modified versions provided that you include in the combination all of the Invariant Sections of all of the original documents unmodified and list them all as Invariant Sections of your combined work in its license notice and that you preserve all their Warranty Disclaimers The combined work need only contain one copy of this License and multiple identical Invariant Sections may be replaced with a single copy If there are multiple Invariant Sections with the same name but different contents make the title of each such section unique by adding at the end of it in parentheses the name of the original author or publisher of that section if known or else a unique number Make the same adjust
96. ed to route signals to an MMC SD card slot or an expansion bus which might in turn affect booting others might control which audio or video codecs are used Plus you should of course have reset init event handlers which set up the hardware to match that jumper configuration That includes in particular any oscillator or PLL used to clock the CPU and any memory controllers needed to access external memory and peripherals Without such handlers you won t be able to access those resources without working target firmware which can do that setup this can be awkward when you re trying to debug that target firmware Even if there s a ROM bootloader which handles a few issues it rarely provides full access to all board specific capabilities Chapter 6 Config File Guidelines 6 Config File Guidelines 19 This chapter is aimed at any user who needs to write a config file including developers and integrators of OpenOCD and any user who needs to get a new board working smoothly It provides guidelines for creating those files You should find the following directories under INSTALLDIR scripts with files includ ing the ones listed here Use them as is where you can or as models for new files e interface These are for debug adapters Files that configure JTAG adapters go here ls interface arm jtag ew cfg hitex str9 comstick cfg oocdlink cfg arm usb ocd cfg icebear cfg openocd usb cfg at91rm9200 cfg jlink cfg parport
97. ed and used at will within a target configuration file Complex board config files can do the things like this for a board with three chips Chip 1 PXA270 for network side big endian set CHIPNAME network set ENDIAN big source find target pxa270 cfg on return _TARGETNAME network cpu other commands can refer to the network cpu target _TARGETNAME configure events for this CPU Chapter 6 Config File Guidelines 22 Chip 2 PXA270 for video side little endian set CHIPNAME video set ENDIAN little source find target pxa270 cfg on return _TARGETNAME video cpu other commands can refer to the video cpu target _TARGETNAME configure events for this CPU Chip 3 Xilinx FPGA for glue logic set CHIPNAME xilinx unset ENDIAN source find target spartan3 cfg That example is oversimplified because it doesn t show any flash memory or the reset init event handlers to initialize external DRAM or assuming it needs it load a configuration into the FPGA Such features are usually needed for low level work with many boards where low level implies that the board initialization software may not be working That s a common reason to need JTAG tools Another is to enable working with microcontroller based systems which often have no debugging support except a JTAG connector Target config files may also export utility functions to board and user config files Such functions should use
98. ee eee ee eens 23 eVei ou tired idan tay ebbe p eno EE eS 44 49 58 F Em C ME 112 flash configuration 0000000 61 flash rasing scissa REESEN Ra rex ER RE PERS 62 flash programming 00200 62 flash protection 4 NES llic eens 64 flash reading sa essa rexes eh etna rer hr RES 62 flash Writing ecce ee member eme 62 gie 81 NS LEE 5 EB EE EE 30 106 GDB configuration 0 200005 30 GDB Server cesses Rer hb pare IER 30 GDB largel ihe eR RT REPRE ERRARE ENS 52 H ti eC 83 I image d nmplng 2j I v vu ue m E dene ered 86 image loading 2 eere eet ee ewe nee 86 imitialization 2 22ll122f05 m plc irt E dE 29 interface config De 33 J dml Eege ER E Ode 9 jn 50 IMAG Aen e pne xD Eee repite eios 1 39 JTAG autoprobe sssssssssssseeseee Bt JTAG Commande 101 JTAG Route Controller 0 eee 50 L libdeG oii eere pip eR eI RE EORR 99 Linux ARM DCC support 99 EE 10 OpenOCD Concept Index M Memory ACCESS esc c cei Sees eee es Ev un 85 message level eioieelea eer Re ems 82 mFlash commande 74 mFlash Conbeuration 73 N NAND oe sis ta pee deseo ee ap matin LET RP 75 NAND confeuration 0 cee eee 75 KEREN CT NAND other commande 78 NAND programming eese Ta TS NAND reading eene 76 NAND verification lesse 78 NAND wig uerceietrerte see pe TER A O Er KEE EN EE e gra 30 printer e 5 DPE ett de EE sea
99. eee 92 arm semihoSting e c irlseg eee nre ter 92 arm Jtag eWicslkesssus ka reda ueber pa RA RA 34 armii memwrite burst esee 97 armii memwrite error fatal 97 armii step irq enable 97 armii Eege ee 98 arm 9 dbgrds cece teeter aan eve EE 93 arm7_9 dcc downloads sess 93 arm7_9 fast memory accees 93 armi20t cplb go ned ase yee eee EUIS 93 arm9 vector catch eese 93 arm920t cache info esses 94 arm920t EE 94 arm920t cpibi e n pe e weed cages ea 94 arm920t read cache esses 94 arm920t read mmu sees 94 arm926ejs cache info ess 94 arm966e E EEN 95 armjtagew infO i ede EE eee Per i 34 132 at91rm9200 em ha REC RARE pie Hebe DES 34 at91sam3 v c iine mer REG Geb IR ee es 65 at91sam3 gpnvm ccc cece eens 65 at91sam3 gpnvm clear cece eee eee 65 at91sam3 gpnvm Set cece eee eee eee 65 at91sam3 gpnvm eboy 0c eee eens 66 at91sam3 INFO EE 66 at91sam3 SIOWCLK 22 seed wise coe RA t aineet 66 at91samT cv acees etes hok Roe eire pde pikes 66 atOisam gpnwvil l liikde e dee ex siressa iias 66 CN NEE 79 at91samD ale ego recesso PP P eee mate ae 79 at91samD Ce see a ee Soe ayes ex e don CORR 79 at91samDO Cl eis isis caved baa ri Enpa TRE e 79 atQlsamO rdy busy phe tinay pee 79 AVY Ioan pao X CRPSPPNREIHPEMDCN PEE UE E PE 67 B e EE 87 C e
100. efore the trigger Such extreme trace before usage can help figure out what caused that event to happen e The maximum value of percent is 100 percent recording data almost ex clusively after the event This extreme trace after usage might help sort out how the event caused trouble oocd_trace Trace Port Driver This driver isn t available unless OpenOCD was explicitly configured with the enable oocd_trace option You probably don t want to configure it unless you ve built the appropriate prototype hardware it s proof of concept software Use the oocd_trace driver if you are configuring an ETM that s connected to an off chip trace connector oocd_trace config target tty Config Command Associates the ETM for target with a trace driver which collects data through the serial port tty oocd_trace resync Command Re synchronizes with the capture clock oocd trace status Command Reports whether the capture clock is locked or not Chapter 16 Architecture and Core Commands 92 16 2 Generic ARM These commands should be available on all ARM processors They are available in addition to other core specific commands that may be available arm core state arm thumb Command Displays the core state optionally changing it to process either arm or thumb in structions The target may later be resumed in the currently set core state Pro cessors may also support the Jazelle state but that
101. eld device example the adaptiveness works perfectly all the time One can set a break point or halt the system in the deep power down code slow step out until the system speeds up Note that adaptive clocking may also need to work at the board level when a board level scan chain has multiple chips Parallel clock voting schemes are good way to implement this both within and between chips and can easily be implemented with a CPLD It s not difficult to have logic fan a module s input TCK signal out to each TAP in the scan chain and then wait until each TAP s RTCK comes back with the right polarity before changing the output RTCK signal Texas Instruments Chapter 22 FAQ 113 makes some clock voting logic available for free with no support in VHDL form see http tiexpressdsp com index php Adaptive_Clocking Solution 2 Always works but may be slower Often this is a perfectly acceptable solution In most simple terms Often the JTAG clock must be 1 10 to 1 12 of the target clock speed But what that magic division is varies depending on the chips on your board ARM rule of thumb Most ARM based systems require an 6 1 division ARM11 cores use an 8 1 division Xilinx rule of thumb is 1 12 the clock speed Note most full speed FT2232 based JTAG adapters are limited to a maximum of 6MHz The ones using USB high speed chips FT2232H often support faster clock rates and adaptive clocking You can still debug the lo
102. elines 27 6 3 5 Chip Reset Setup As arule you should put the reset_config command into the board file Most things you think you know about a chip can be tweaked by the board Some chips have specific ways the TRST and SRST signals are managed In the unusual case that these are chip specific and can never be changed by board wiring they could go here For example some chips can t support JTAG debugging without both signals Provide a reset assert event handler if you can Such a handler uses JTAG operations to reset the target letting this target config be used in systems which don t provide the optional SRST signal or on systems where you don t want to reset all targets at once Such a handler might write to chip registers to force a reset use a JRC to do that preferable the target may be wedged or force a watchdog timer to trigger For Cortex M3 targets this is not necessary The target driver knows how to use trigger an NVIC reset when SRST is not available Some chips need special attention during reset handling if they re going to be used with JTAG An example might be needing to send some commands right after the target s TAP has been reset providing a reset deassert post event handler that writes a chip register to report that J TAG debugging is being done Another would be reconfiguring the watchdog so that it stops counting while the core is halted in the debugger JTAG clocking constraints often change duri
103. em into larger operations irscan tap instruction endstate tap_state Command For each tap listed loads the instruction register with its associated numeric instruc tion The number of bits in that instruction may be displayed using the scan_chain command For other TAPs a BYPASS instruction is loaded When tap_state is specified the JTAG state machine is left in that state For example IRPAUSE might be specified so the data register can be loaded before re entering the RUN IDLE state If the end state is not specified the RUN IDLE state is entered Note OpenOCD currently supports only a single field for instruction reg ister values unlike data register values For TAPs where the instruction register length is more than 32 bits portable scripts currently must issue only BYPASS instructions jtag_reset trst srst Command Set values of reset signals The trst and srst parameter values may be 0 indicating that reset is inactive pulled or driven high or 1 indicating it is active pulled or driven low The reset_config command should already have been used to configure how the board and JTAG adapter treat these two signals and to say if either signal is even present See Chapter 9 Reset Configuration page 41 Note that TRST is specially handled It actually signifies JTAG s RESET state So if the board doesn t support the optional TRST signal or it doesn t support it along with the specified SRST
104. emen tations The default behaviour if no option given is separate indicating ev erything behaves normally srst_pulls_trst states that the test logic is reset together with the reset of the system e g NXP LPC2000 broken board lay out trst_pulls_srst says that the system is reset together with the test logic only hypothetical I haven t seen hardware with such a bug and can be worked around combined implies both srst_pulls_trst and trst_pulls_srst e The gates tokens control flags that describe some cases where JTAG may be unvailable during reset srst_gates_jtag default indicates that asserting SRST gates the JTAG clock This means that no communication can happen on JTAG while SRST is asserted Its converse is srst_nogate indicating that JTAG commands can safely be issued while SRST is active The optional trst_type and srst_type parameters allow the driver mode of each reset line to be specified These values only affect J TAG interfaces with support for different driver modes like the Amontec JTAGkey and JTAG Accelerator Also they are necessarily ignored if the relevant signal TRST or SRST is not connected Chapter 9 Reset Configuration 44 e Possible trst type driver modes for the test reset signal TRST are the default trst push pull and trst open drain Most boards connect this signal to a pulldown so the JTAG TAPs never leave reset unless they are hooked up to a
105. ems that are normally used with a boot loader common tasks include updating clocks and initializing memory controllers That may be needed to let you write the boot loader into flash in order to de brick your board or to load programs into external DDR memory without having run the boot loader target create target name type configparams Command This command creates a GDB debug target that refers to a specific JTAG tap It enters that target into a list and creates a new command target name which is used for various purposes including additional configuration e target name is the name of the debug target By convention this should be the same as the dotted name of the TAP associated with this target which must be specified here using the chain position dotted name configparam This name is also used to create the target object command referred to here as target name and in other places the target needs to be identified e type specifies the target type See target types page 53 e configparams all parameters accepted by target name configure are per mitted If the target is big endian set it here with endian big If the variant matters set it here with variant You must set the chain position dotted name here target name configure configparams Command The options accepted by this command may also be specified as parameters to target create Their values can later be queried one at a time by u
106. enOCD Developer Resources 3 1 OpenOCD Developer Resources If you are interested in improving the state of OpenOCD s debugging and testing support new contributions will be welcome Motivated developers can produce new target flash or interface drivers improve the documentation as well as more conventional bug fixes and enhancements The resources in this chapter are available for developers wishing to explore or expand the OpenOCD source code 1 1 OpenOCD GIT Repository During the 0 3 x release cycle OpenOCD switched from Subversion to a GIT repository hosted at SourceForge The repository URL is git openocd git sourceforge net gitroot openocd openocd You may prefer to use a mirror and the HTTP protocol http repo or cz r openocd git With standard GIT tools use git clone to initialize a local repository and git pull to update it There are also gitweb pages letting you browse the repository with a web browser or download arbitrary snapshots without needing a GIT client http openocd git sourceforge net git gitweb cgi p openocd openocd http repo or cz w openocd git The README file contains the instructions for building the project from the repository or a snapshot Developers that want to contribute patches to the OpenOCD system are strongly encour aged to work against mainline Patches created against older versions may require additional work from their submitter in order to be updated for newer releases
107. ensible command interpreter All commands presented in this Guide are extensions to Jim Tcl You can use them as simple commands without needing to learn much of anything about Tcl Alternatively can write Tcl programs with them You can learn more about Jim at its website http jim berlios de There is an active and responsive community get on the mailing list if you have any questions Jim Tcl maintainers also lurk on the OpenOCD mailing list Jim vs Tcl Jim Tcl is a stripped down version of the well known Tcl language which can be found here http www tcl tk Jim Tcl has far fewer features Jim Tcl is several dozens of C files and H files and implements the basic Tcl command set In contrast Tcl 8 6 is a 4 2 MB zip file containing 1540 files Missing Features Our practice has been Add clone the real Tcl feature if when needed We welcome Jim Tcl improvements not bloat Also there are a large number of optional Jim Tcl features that are not enabled in OpenOCD Scripts OpenOCD configuration scripts are Jim Tcl Scripts OpenOCD s command interpreter today is a mixture of newer Jim Tcl commands and older the orginal command interpreter Commands At the OpenOCD telnet command line or via the GDB monitor command one can type a Tcl for loop set variables etc Some of the commands documented in this guide are implemented as Tcl scripts from a startup tcl file internal to the server Historical Note Jim Tcl
108. er Both covers must also clearly and legibly identify you as the publisher of these copies The front cover must present the full title with all words of the title equally prominent and visible You may add other material on the covers in addition Copying with changes limited to the covers as long as they preserve the title of the Document and satisfy these conditions can be treated as verbatim copying in other respects If the required texts for either cover are too voluminous to fit legibly you should put the first ones listed as many as fit reasonably on the actual cover and continue the rest onto adjacent pages If you publish or distribute Opaque copies of the Document numbering more than 100 you must either include a machine readable Transparent copy along with each Opaque copy or state in or with each Opaque copy a computer network location from which the general network using public has access to download using public standard network protocols a complete Transparent copy of the Document free of added material If you use the latter option you must take reasonably prudent steps when you begin distribution of Opaque copies in quantity to ensure that this Transparent copy will remain thus accessible at the stated location until at least one year after the last time you distribute an Opaque copy directly or through your agents or retailers of that edition to the public It is requested but not required that you contact the autho
109. erations and more 10 1 Scan Chains TAPs are part of a hardware scan chain which is daisy chain of TAPs They also need to be added to OpenOCD s software mirror of that hardware list giving each member a name and associating other data with it Simple scan chains with a single TAP are common in systems with a single microcontroller or microprocessor More complex chips may have several TAPs internally Very complex scan chains might have a dozen or more TAPs several in one chip more in the next and connecting to other boards with their own chips and TAPs You can display the list with the scan_chain command Don t confuse this with the list displayed by the targets command presented in the next chapter That only displays TAPs for CPUs which are configured as debugging targets Here s what the scan chain might look like for a chip more than one TAP TapName Enabled IdCode Expected MIrLen IrCap IrMask O omap5912 dsp Y Ox03df1d81 Ox03df1d81 38 0x01 0x03 1 omap5912 arm Y 0x0692602f 0x0692602f 4 0x01 OxOf 2 omap5912 unknown Y 0x00000000 0x00000000 8 0x01 0x03 OpenOCD can detect some of that information but not all of it See Autoprobing page 50 Unfortunately those TAPs can t always be autoconfigured because not all devices provide good support for that JTAG doesn t require supporting IDCODE instructions and chips with JTAG routers may not link TAPs into the chain until they are told to do so The configuration mechanism
110. erver c 101 gdb get char read 10054 What does that mean and what might be the reason for this Error code 10054 corresponds to WSAECONNRESET which means that the debugger GDB has closed the connection to OpenOCD This might be a GDB issue LPC2000 Flash In the configuration file in the section where flash device configu rations are described there is a parameter for specifying the clock frequency for LPC2000 internal flash devices e g flash bank _FLASHNAME 1pc2000 0x0 0x40000 O 0 TARGETNAME 1pc2000 vi 14746 calc checksum which must be specified in kilohertz However I do have a quartz crystal of a frequency that contains fractions of kilohertz e g 14 745 600 Hz i e 14 745 600 kHz Is it possible to specify real numbers for the clock frequency No The clock frequency specified here must be given as an integral number However this clock frequency is used by the In Application Programming IAP routines of the LPC2000 family only which seems to be very tolerant concerning the given clock frequency so a slight difference between the specified clock frequency and the actual clock frequency will not cause any trouble Command Order Do I have to keep a specific order for the commands in the configu ration file Well yes and no Commands can be given in arbitrary order yet the devices listed for the J TAG scan chain must be given in the right order jtag newdevice with the device closest to the TDO Pin being listed first
111. evice that was declared using flash bank numbered from zero This returned list can be manipulated easily from within scripts flash probe num Command Identify the flash or validate the parameters of the configured flash Operation depends on the flash type The num parameter is a value shown by flash banks Most flash commands will implicitly autoprobe the bank flash drivers can distinguish between probing and autoprobing but most don t bother 12 2 Erasing Reading Writing to Flash One feature distinguishing NOR flash from NAND or serial flash technologies is that for read access it acts exactly like any other addressible memory This means you can use normal memory read commands like mdw or dump image with it with no special flash subcommands See Memory access page 85 and Image access page 86 Write access works differently Flash memory normally needs to be erased before it s written Erasing a sector turns all of its bits to ones and writing can turn ones into zeroes This is why there are special commands for interactive erasing and writing and why GDB needs to know which parts of the address space hold NOR flash memory Note Most of these erase and write commands leverage the fact that NOR flash chips consume target address space They implicitly refer to the current JTAG target and map from an address in that target s address space back to a flash bank A few commands use abstract addressing based on bank and sec
112. example there may be chip or board re quirements that all reset pulses last for at least a certain amount of time and reset buttons commonly have hardware debouncing Use the adapter nsrst delay and jtag ntrst delay commands to say when extra delays are needed e Drive type Reset lines often have a pullup resistor letting the JTAG interface treat them as open drain signals But that s not a requirement so the adapter may need to use push pull output drivers Also with weak pullups it may be advisable to drive signals to both levels push pull to minimize rise times Use the reset config trst type and art type parameters to say how to drive reset signals e Special initialization Targets sometimes need special JTAG initialization sequences to handle chip specific issues not limited to errata For example certain JTAG com mands might need to be issued while the system as a whole is in a reset state SRST active but the JTAG scan chain is usable TRST inactive Many systems treat com bined assertion of SRST and TRST as a trigger for a harder reset than SRST alone Such custom reset handling is discussed later in this chapter There can also be other issues Some devices don t fully conform to the JTAG specifications Trivial system specific differences are common such as SRST and TRST using slightly different names There are also vendors who distribute key JTAG documentation for their chips only to developers who have signed a
113. format set p15 0x 04x 0x 08x regs value arm mcr 15 expr regs gt gt 12 amp 0x7 expr regs gt gt 0 amp 0xf expr regs gt gt 4 amp 0xf expr regs gt gt 8 amp 0x7 value Chapter 7 Daemon Configuration 29 7 Daemon Configuration The commands here are commonly found in the openocd cfg file and are used to specify what TCP IP ports are used and how GDB should be supported 7 1 Configuration Stage When the OpenOCD server process starts up it enters a configuration stage which is the only time that certain commands configuration commands may be issued Normally con figuration commands are only available inside startup scripts In this manual the definition of a configuration command is presented as a Config Com mand not as a Command which may be issued interactively The runtime help command also highlights configuration commands and those which may be issued at any time Those configuration commands include declaration of TAPs flash banks the interface used for JTAG communication and other basic setup The server must leave the configura tion stage before it may access or activate TAPs After it leaves this stage configuration commands may no longer be issued 7 2 Entering the Run Stage The first thing OpenOCD does after leaving the configuration stage is to verify that it can talk to the scan chain list of TAPs which has been configured It will warn if it doesn t find TAPs it expects to find
114. g megai28 cfg netx500 cfg omap2420 cfg omap3530 cfg omap5912 cfg pic32mx cfg pxa255 cfg pxa270 cfg readme txt sam se512 cfg sam7x256 cfg samsung_s3c2410 cfg samsung_s3c2440 cfg samsung_s3c2450 cfg samsung_s3c4510 cfg samsung_s3c6410 cfg sharp_1h79532 cfg smdk6410 cfg smp8634 cfg stm32fix cfg str710 cfg str730 cfg str750 cfg str912 cfg telo cfg ti dm355 cfg ti dm365 cfg ti dm6446 cfg tmpa900 cfg tmpa910 cfg xba revA3 cfg browse for other library files which may be useful For example there are various generic and CPU specific utilities The openocd cfg user config file may override features in any of the above files by setting variables before sourcing the target file or by adding commands specific to their situation Chapter 6 Config File Guidelines 21 6 1 Interface Config Files The user config file should be able to source one of these files with a command like this source find interface FOOBAR cfg A preconfigured interface file should exist for every debug adapter in use today with OpenOCD That said perhaps some of these config files have only been used by the devel oper who created it A separate chapter gives information about how to set these up See Chapter 8 Debug Adapter Configuration page 33 Read the OpenOCD source code and Developer s GUide if you have a new kind of hardware interface and need to provide a driver for it 6 2 Board Config Files The user config file should b
115. g last Providing a last sector of last specifies to the end of the flash bank The num parameter is a value shown by flash banks 12 4 Flash Driver List As noted above the flash bank command requires a driver name and allows driver specific options and behaviors Some drivers also activate driver specific commands 12 4 1 External Flash efi Flash Driver The Common Flash Interface CFI is the main standard for external NOR flash chips each of which connects to a specific external chip select on the CPU Frequently the first such chip is used to boot the system Your board s reset init handler might need to configure additional chip selects using other commands like mww to configure a bus and its timings or perhaps configure a GPIO pin that controls the write protect pin on the flash chip The CFI driver can use a target specific working area to significantly speed up operation The CFI driver can accept the following optional parameters in any order e jedec probe is used to detect certain non CFI flash ROMs like AM29LV010 and similar types e xl6 as x8 when a 16 bit flash is hooked up to an 8 bit bus To configure two adjacent banks of 16 MBytes each both sixteen bits two bytes wide on a sixteen bit bus flash bank FLASHNAME cfi 0x00000000 0x01000000 2 2 TARGETNAME flash bank FLASHNAME cfi 0x01000000 0x01000000 2 2 TARGETNAME To configure one bank of 32 MBytes built from two sixteen bit
116. g messages The default setting is 2 outputting only infor mational messages warnings and errors You can also change this setting from within a telnet or gdb session using debug level n see debug level page 82 You can redirect all output from the daemon to a file using the 1 lt logfile gt switch Note OpenOCD will launch the GDB amp telnet server even if it can not establish a connec tion with the target In general it is possible for the JTAG controller to be unresponsive until the target is set up correctly via e g GDB monitor commands in a GDB init script Chapter 5 OpenOCD Project Setup 12 5 OpenOCD Project Setup To use OpenOCD with your development projects you need to do more than just connecting the JTAG adapter hardware dongle to your development board and then starting the OpenOCD server You also need to configure that server so that it knows about that adapter and board and helps your work You may also want to connect OpenOCD to GDB possibly using Eclipse or some other GUI 5 1 Hooking up the JTAG Adapter Today s most common case is a dongle with a JTAG cable on one side such as a ribbon cable with a 10 pin or 20 pin IDC connector and a USB cable on the other Instead of USB some cables use Ethernet older ones may use a PC parallel port or even a serial port l Start with power to your target board turned off and nothing connected to your JTAG adapter If you re particularly paranoid
117. gth Command flash fillh address halfword length Command flash fillb address byte length Command Fills flash memory with the specified word 32 bits halfword 16 bits or byte 8 bit pattern starting at address and continuing for length units word halfword byte No erasure is done before writing when needed that must be done before issuing this command Writes are done in blocks of up to 1024 bytes and each write is verified by reading back the data and comparing it to what was written The flash bank to use is inferred from the address of each block and the specified length must stay within that bank flash write bank num filename offset Command Write the binary filename to flash bank num starting at offset bytes from the beginning of the bank The num parameter is a value shown by flash banks flash write image erase unlock filename offset type Command Write the image filename to the current target s flash bank s A relocation offset may be specified in which case it is added to the base address for each section in the image The file type can be specified explicitly as bin binary ihex Intel hex elf ELF file s19 Motorola s19 mem or builder The relevant flash sectors will be erased prior to programming if the erase parameter is given If unlock is provided then the flash banks are unlocked before erase and program The flash bank to use is i
118. h and use ARM Cortex M3 cores The driver automatically recog nizes a number of these chips using the chip identification register and autoconfigures itself str7x Flash Driver All members of the STR7 microcontroller family from ST Microelectronics include internal flash and use ARM7TDMI cores The str7x driver defines one mandatory parameter variant which is either STR71x STR73x or STR75x flash bank FLASHNAME str7x 0x40000000 0x00040000 O O TARGETNAME STR71xii str7x disable jtag bank Command Activate the Debug Readout protection mechanism for the specified flash bank str9x Flash Driver Most members of the STR9 microcontroller family from ST Microelectronics include internal flash and use ARM966E cores The str9 needs the flash controller to be configured using the str9x flash config command prior to Flash programming flash bank FLASHNAME str9x 0x40000000 0x00040000 0 O TARGETNAME str9x flash config O 4 2 0 0x80000 str9x flash config num bbsr nbbsr bbadr nbbadr Command Configures the str9 flash controller The num parameter is a value shown by flash banks e bbsr Boot Bank Size register e nbbsr Non Boot Bank Size register e bbadr Boot Bank Start Address register e nbbadr Boot Bank Start Address register tms470 Flash Driver Most members of the TMS470 microcontroller family from Texas Instruments include internal flash and use ARM7TDMI cores This driver doesn t require the chip and bus width to be
119. he remote gdbserver protocol and as such can be used to debug remote targets Setting up GDB to work with OpenOCD can involve several components e The OpenOCD server support for GDB may need to be configured See GDB Config uration page 30 e GDB s support for OpenOCD may need configuration as shown in this chapter e If you have a GUI environment like Eclipse that also will probably need to be config ured Of course the version of GDB you use will need to be one which has been built to know about the target CPU you re using It s probably part of the tool chain you re using For example if you are doing cross development for ARM on an x86 PC instead of using the native x86 gdb command you might use arm none eabi gdb if that s the tool chain used to compile your code 20 1 Connecting to GDB Use GDB 6 7 or newer with OpenOCD if you run into trouble For instance GDB 6 3 has a known bug that produces bogus memory access errors which has since been fixed see http osdir com ml gdb bugs discuss 2004 12 msg00018 html OpenOCD can communicate with GDB in two ways 1 A socket TCP IP connection is typically started as follows target remote localhost 3333 This would cause GDB to connect to the gdbserver on the local pc using port 3333 2 A pipe connection is typically started as follows target remote openocd c gdb port pipe log output openocd log This would cause GDB to run OpenOCD and communicate using pipes stdin stdout
120. he simpler solution one user config file including basic configuration plus any TCL procedures to simplify your work 5 4 User Config Files A user configuration file ties together all the parts of a project in one place One of the following will match your situation best Chapter 5 OpenOCD Project Setup 14 e Ideally almost everything comes from configuration files provided by someone else For example OpenOCD distributes a scripts directory probably in usr share openocd scripts on Linux Board and tool vendors can provide these too as can individual user sites the s command line option lets you say where to find these files See Chapter 4 Running page 10 The AT91SAM7X256 example above works this way Three main types of non user configuration file each have their own subdirectory in the scripts directory 1 interface one for each different debug adapter 2 board one for each different board 3 target the chips which integrate CPUs and other JTAG TAPs Best case include just two files and they handle everything else The first is an interface config file The second is board specific and it sets up the J TAG TAPs and their GDB targets by deferring to some target cfg file declares all flash memory and leaves you nothing to do except meet your deadline source find interface olimex jtag tiny cfg source find board csb337 cfg Boards with a single microcontroller often won
121. he string 1 if the tap specified by dotted name is enabled and 0 if it is disabled jtag tapisenabled dotted name Command Returns the string 1 if the tap specified by dotted name is enabled and 0 if it is disabled Note Humans will find the scan_chain command more helpful for query ing the state of the JTAG taps Chapter 10 TAP Declaration 51 10 7 Autoprobing TAP configuration is the first thing that needs to be done after interface and reset con figuration Sometimes it s hard finding out what TAPs exist or how they are identified Vendor documentation is not always easy to find and use To help you get past such problems OpenOCD has a limited autoprobing ability to look at the scan chain doing a blind interrogation and then reporting the TAPs it finds To use this mechanism start the OpenOCD server with only data that configures your JTAG interface and arranges to come up with a slow clock many devices don t support fast J TAG clocks right when they come out of reset For example your openocd cfg file might have source find interface olimex arm usb tiny h cfg reset config trst and srst jtag_rclk 8 When you start the server without any TAPs configured it will attempt to autoconfigure the TAPs There are two parts to this 1 TAP discovery After a JTAG reset sometimes a system reset may be needed too each TAP s data registers will hold the contents of either the IDCODE or BYPASS register
122. hem or indicate that a TAP doesn t conform to the J TAG specification Chapter 10 TAP Declaration 49 e irmask NUMBER A mask used with ircapture to verify that instruction scans work correctly Such scans are not used by OpenOCD except to verify that there seems to be no problems with JTAG scan chain operations 10 4 Other TAP commands jtag cget dotted name event name Command jtag configure dotted name event name string Command At this writing this TAP attribute mechanism is used only for event handling It is not a direct analogue of the cget configure mechanism for debugger targets See the next section for information about the available events The configure subcommand assigns an event handler a TCL string which is evalu ated when the event is triggered The cget subcommand returns that handler 10 5 TAP Events OpenOCD includes two event mechanisms The one presented here applies to all JTAG TAPs The other applies to debugger targets which are associated with certain TAPs The TAP events currently defined are e post reset The TAP has just completed a JTAG reset The tap may still be in the JTAG RESET state Handlers for these events might perform initialization sequences such as issuing TCK cycles TMS sequences to ensure exit from the ARM SWD mode and more Because the scan chain has not yet been verified handlers for these events should not issue commands which scan the JTAG IR or DR registers of any
123. holder saying it can be distributed under the terms of this License Such a notice grants a world wide royalty free license unlimited in duration to use that work under the conditions stated herein The Document below refers to any such manual or work Any member of the public is a licensee and is addressed as you You accept the license if you copy modify or distribute the work in a way requiring permission under copyright law A Modified Version of the Document means any work containing the Document or a portion of it either copied verbatim or with modifications and or translated into another language A Secondary Section is a named appendix or a front matter section of the Document that deals exclusively with the relationship of the publishers or authors of the Document to the Document s overall subject or to related matters and contains nothing that could fall directly within that overall subject Thus if the Document is in part a textbook of mathematics a Secondary Section may not explain any mathematics The relationship could be a matter of historical connection with the subject or with related matters or of legal commercial philosophical ethical or political position regarding them The Invariant Sections are certain Secondary Sections whose titles are designated as being those of Invariant Sections in the notice that says that the Document is released Appendix A The GNU Free Documentation Licen
124. ic commande 94 16 3 6 V ARMO966E specific commande 94 16 3 7 XScale specific commande 95 16 4 ARMv6 Architecture 97 16 4 1 ARM11 specific commande 97 16 5 ARMv7 Architecture 98 16 5 1 ARMv7 Debug Access Port DAP specific commands 98 16 5 2 Cortex M3 specific commande 98 16 6 Software Debug Messages and Iracmg 99 17 JTAG Commands 101 17 1 Low Level JTAG Commande 101 17 2 TAP state names iooeotileseeeker d EE E E Fees 103 18 Boundary Scan Commands 104 18 1 SVF Serial Vector Format 104 18 2 XSVF Xilinx Serial Vector Format 104 19 TETP uda meu Re ER kantsi dase ae en 105 20 GDB and OpenOCD 106 20 1 Connecting toGDb eh 106 20 2 Sample GDB session startup 0 cece eee eee e ee 106 20 8 Configuring GDB for Open 107 20 4 Programming using OD 107 20 5 Using openocd SMP with GD 108 21 Tel Scripting APT dese ENER 110 21 1 API T l S i sseekereste dates ERR RE UR ERR RUE Rr bene ke 110 21 2 Internal low level Commandes 110 21 3 OpenOCD specific Global Vanableg 111 23 Tcl Crash Course s 117 23 1 Tel R le SAL 2c cise enr Ear een c ORAE Era dca LET 23 2 Tcl Rule Fl Diiss uaea aa e eE 117 23 3 Per Rule 1 All Results are sting ird 23 4 Tcl Quoting Operators e DI 23 5 Consequences of Rule 1 2 3 4 eee esee 118 23 5 1 Tokenisation amp Execution 0 0 00 cece cee 118
125. iguration files and scripts are searched for in 1 the current directory any search dir specified on the command line using the s option any search dir specified using the add script search dir command HOME openocd not on Windows the site wide script library pkgdatadir site and EE ME 6 the OpenOCD supplied script library pkgdatadir scripts The first found file with a matching file name will be used Note Don t try to use configuration script names or paths which include the 4 character That character begins Tcl comments 4 1 Simple setup no customization In the best case you can use two scripts from one of the script libraries hook up your JTAG adapter and start the server and your JTAG setup will just work out of the box Always try to start by reusing those scripts but assume you ll need more customization even if this works See Chapter 5 OpenOCD Project Setup page 12 If you find a script for your JTAG adapter and for your board or target you may be able to hook up your JTAG adapter then start the server like openocd f interface ADAPTER cfg f board MYBOARD cfg You might also need to configure which reset signals are present using c reset config trst and srst or something similar If all goes well you ll see output something like Chapter 4 Running 11 Open On Chip Debugger 0 4 0 2010 01 14 15 06 For bug reports read http openocd berlios de doc doxygen bugs html
126. includes OOB data if that s being written NOTE At the time this text was written bad blocks are ignored That is this routine will not skip bad blocks but will instead try to write them This can cause problems Provide at most one option parameter With some NAND drivers the meanings of these parameters may change if nand raw access was used to disable hardware ECC e no oob_ parameter File has only page data which is written If raw acccess is in use the OOB area will not be written Otherwise if the underlying NAND controller driver has a write page routine that routine may write the OOB with hardware computed ECC data e oob only File has only raw OOB data which is written to the OOB area Each page s data area stays untouched This can be a dangerous option since it can invalidate the ECC data You may need to force raw access to use this mode e oob raw File interleaves data and OOB data both of which are written If raw access is Chapter 13 NAND Flash Commands 78 enabled the data is written first then the un altered OOB Otherwise if the underlying NAND controller driver has a write_page routine that routine may modify the OOB before it s written to include hardware computed ECC data e oob_softecc File has only page data which is written The OOB area is filled with Oxff except for a standard 1 bit software ECC code stored in conventional locations You might need to force raw access to use this mode to p
127. init target event handler after it reprograms those CPU clocks or manually if something else such as a boot loader sets up those clocks See Target Events page 57 When the initial low JTAG speed is a chip characteristic perhaps because of a required oscillator speed provide such a handler in the target config file When that speed is a function of a board specific characteristic such as which speed oscillator is used it belongs in the board config file instead In both cases it s safest to also set the initial J TAG clock rate to that same slow speed so that OpenOCD never starts up using a clock speed that s faster than the scan chain can support jtag_rclk 3000 _TARGET cpu configure event reset start jtag_rclk 3000 If your system supports adaptive clocking RTCK configuring JTAG to use that is probably the most robust approach However it introduces delays to synchronize clocks so it may not be the fastest solution NOTE Script writers should consider using jtag_rclk instead of adapter_khz but only for ARM cores and boards which support adaptive clocking adapter_khz max_speed_kHz Command A non zero speed is in KHZ Hence 3000 is 3mhz JTAG interfaces usually support a limited number of speeds The speed actually used won t be faster than the speed specified Chip data sheets generally include a top JTAG clock rate The actual rate is often a function of a CPU core clock and is normally less than that peak rate Fo
128. ion Appendix A The GNU Free Documentation License 129 ADDENDUM How to use this License for your documents To use this License in a document you have written include a copy of the License in the document and put the following copyright and license notices just after the title page Copyright C year your name Permission is granted to copy distribute and or modify this document under the terms of the GNU Free Documentation License Version 1 2 or any later version published by the Free Software Foundation with no Invariant Sections no Front Cover Texts and no Back Cover Texts A copy of the license is included in the section entitled GNU Free Documentation License If you have Invariant Sections Front Cover Texts and Back Cover Texts replace the with Texts line with this with the Invariant Sections being list their titles with the Front Cover Texts being list and with the Back Cover Texts being list If you have Invariant Sections without Cover Texts or some other combination of the three merge those two alternatives to suit the situation If your document contains nontrivial examples of program code we recommend releasing these examples in parallel under your choice of free software license such as the GNU General Public License to permit their use in free software OpenOCD Concept Index OpenOCD Concept Index A ee EE 1 adaptive clocking seseessesees 40 112 Architecture Specific
129. is error messages only level 1 adds warnings level 2 adds informational messages and level 3 adds debugging messages The default is level 2 but that can be overridden on the command line along with the location of that log file which is normally the server s standard output See Chapter 4 Running page 10 Chapter 15 General Commands 83 echo n message Command Logs a message at user priority Output message to stdout Option n suppresses trailing newline echo Downloading kernel please wait log_output filename Command Redirect logging to filename the initial log output channel is stderr add_script_search_dir directory Command Add directory to the file script search path 15 2 Target State handling In this section target refers to a CPU configured as shown earlier see Chapter 11 CPU Configuration page 52 These commands like many implicitly refer to a current target which is used to perform the various operations The current target may be changed by using targets command with the name of the target which should become current reg number name value Command Access a single register by number or by its name The target must generally be halted before access to CPU core registers is allowed Depending on the hardware some other registers may be accessible while the target is running With no arguments list all available registers for the current target showing number name size
130. is not currently supported in OpenOCD arm disassemble address count thumb Command Disassembles count instructions starting at address If count is not specified a single instruction is disassembled If thumb is specified or the low bit of the address is set Thumb2 mixed 16 32 bit instructions are used else ARM 32 bit instructions are used Processors may also support the Jazelle state but those instructions are not currently understood by OpenOCD Note that all Thumb instructions are Thumb2 instructions so older processors with out Thumb2 support will still see correct disassembly of Thumb code Also Thum bEE opcodes are the same as Thumb2 with a handful of exceptions ThumbEE disassembly currently has no explicit support arm mcr pX opl CRn CRm op2 value Command Write value to a coprocessor pX register passing parameters CRn CRm opcodes opcl and opc2 and using the MCR instruction Parameter sequence matches the ARM instruction but omits an ARM register arm mrc pX coproc opl CRn CRm op2 Command Read a coprocessor pX register passing parameters CRn CRm opcodes opcl and opc2 and the MRC instruction Returns the result so it can be manipulated by Jim scripts Parameter sequence matches the ARM instruction but omits an ARM register arm reg Command Display a table of all banked core registers fetching the current value from every core mode if necessary arm semihosting enable disab
131. is used e oob only Output file has only raw OOB data and will be smaller than length since it will contain only the spare areas associated with each data page erase num offset length Command Erases blocks on the specified NAND device starting at the specified offset and con tinuing for length bytes Both of those values must be exact multiples of the device s block size and the region they specify must fit entirely in the chip If those param eters are not specified the whole NAND chip will be erased The num parameter is the value shown by nand list NOTE This command will try to erase bad blocks when told to do so which will probably invalidate the manufacturer s bad block marker For the remainder of the current server session nand info will still report that the block is bad write num filename offset option Command Writes binary data from the file into the specified NAND device starting at the specified offset Those pages should already have been erased you can t change zero bits to one bits The num parameter is the value shown by nand list Use a complete path name for filename so you don t depend on the directory used to start the OpenOCD server The offset must be an exact multiple of the device s page size All data in the file will be written assuming it doesn t run past the end of the device Only full pages are written and any extra space in the last page will be filled with Oxff bytes That
132. ise fallback to vectreset srst use hardware srst if fitted otherwise fallback to vectreset sysresetreq use NVIC SYSRESETREQ to reset system vectreset use NVIC VECTRESET to reset system Using vectreset is a safe option for all current Cortex M3 cores This however has the disadvantage of only resetting the core all peripherals are uneffected A solution would be to use a reset init event handler to manually reset the peripherals See Target Events page 57 16 6 Software Debug Messages and Tracing OpenOCD can process certain requests from target software when the target uses appro priate libraries The most powerful mechanism is semihosting but there is also a lighter weight mechanism using only the DCC channel Currently target_request debugmsgs is supported only for arm7_9 and cortex_m3 cores These messages are received as part of target polling so you need to have poll on active to receive them They are intrusive in that they will affect program execution times If that is a problem see ARM Hardware Tracing page 88 See libdcc in the contrib dir for more details In addition to sending strings characters and arrays of various size integers from the target libdcc also exports a software trace point mechanism The target being debugged may issue trace messages which include a 24 bit trace point number Trace point support includes two distinct mechanisms
133. kinds of message See Software Debug Messages and Tracing page 99 5 7 Target Hardware Setup Chip vendors often provide software development boards which are highly configurable so that they can support all options that product boards may require Make sure that any jumpers or switches match the system configuration you are working with Common issues include e JTAG setup Boards may support more than one JTAG configuration Examples include jumpers controlling pullups versus pulldowns on the nTRST and or nSRST signals and choice of connectors e g which of two headers on the base board or one from a daughtercard For some Texas Instruments boards you may need to jumper the EMUO and EMUI signals which OpenOCD won t currently control e Boot Modes Complex chips often support multiple boot modes controlled by exter nal jumpers Make sure this is set up correctly For example many i MX boards from NXP need to be jumpered to ATX mode to start booting using the on chip ROM when using second stage bootloader code stored in a NAND flash chip Such explicit configuration is common and not limited to booting from NAND You might also need to set jumpers to start booting using code loaded from an MMC SD card external SPI flash Ethernet UART or USB links NOR flash OneNAND flash some external host or various other sources 3 As a more polite alternative some processors have special debug oriented registers which can b
134. lash the target do you need to enable the flash via a special command Is using SRST appropriate and possible on your system Or instead of that do you need to issue JTAG commands to trigger reset SRST usually resets everything on the scan chain which can be inappropriate During reset do you need to write to certain memory locations to set up system clocks or to reconfigure the SDRAM How about configuring the watchdog timer or other peripherals to stop running while you hold the core stopped for debugging All of the above items can be addressed by target event handlers These are set up by target name configure event or target create event The programmer s model matches the command option used in Tcl Tk buttons and events The two examples below act the same but one creates and invokes a small procedure while the other inlines it proc my attach proc 1 echo Reset reset halt mychip cpu configure event gdb attach my_attach_proc mychip cpu configure event gdb attach echo Reset To make flash probe and gdb load to flash work we need a reset init reset init The following target events are defined debug halted The target has halted for debug reasons i e breakpoint debug resumed The target has resumed i e gdb said run early halted Occurs early in the halt process gdb attach When GDB connects This is before any communication with the target so this can be used to set
135. le Command Display status of semihosting after optionally changing that status Semihosting allows for code executing on an ARM target to use the I O facilities on the host computer i e the system where OpenOCD is running The target application must be linked against a library implementing the ARM semihosting convention that forwards operation requests by using a special SVC instruction that is trapped at the Supervisor Call vector by OpenOCD 16 3 ARMv4 and ARMv5 Architecture The ARMv4 and ARMv5 architectures are widely used in embedded systems and intro duced core parts of the instruction set in use today That includes the Thumb instruction set introduced in the ARMv4T variant Chapter 16 Architecture and Core Commands 93 16 3 1 ARM 7 and ARMO specific commands These commands are specific to ARM7 and ARMO cores like ARM7TDMI ARM720T ARM9TDMI ARM920T or ARM926EJ S They are available in addition to the ARM commands and any other core specific commands that may be available arm7_9 dbgrq enable disable Command Displays the value of the flag controlling use of the the EmbeddedIce DBGRQ signal to force entry into debug mode instead of breakpoints If a boolean parameter is provided first assigns that flag This should be safe for all but ARM7TDMI S cores like NXP LPC This feature is enabled by default on most ARM9 cores including ARM9TDMI ARM920T and ARM926EJ S arm7_9 dcc_downloads enable disable
136. le 9 9 in the ARM920T TRM Not all registers can be written arm920t cp15i opcode value address Command DEPRECATED avoid using this Use the arm mrc or arm mcr commands instead Interpreted access using ARM instruction opcode which should be the value of either an MRC or MCR instruction as shown tables 9 11 9 12 and 9 13 in the ARM920T TRM If no value is provided the result is displayed Else if that value is written using the specified address or using zero if no other address is provided arm920t read cache filename Command Dump the content of ICache and DCache to a file named filename arm920t read mmu filename Command Dump the content of the ITLB and DTLB to a file named filename 16 3 5 ARM926ej s specific commands These commands are available to ARM926ej s based CPUs which are implementations of the ARMv5TEJ architecture based on the ARM9EJ S integer core They are available in addition to the ARM ARM7 ARM9 and ARM9 commands The Feroceon cores also support these commands although they are not built from ARM926ej s designs arm926ejs cache info Command Print information about the caches found 16 3 6 ARMO966E specific commands These commands are available to ARM966 based CPUs which are implementations of the ARMvSTE architecture They are available in addition to the ARM ARM7 ARM9 and ARM9 commands Chapter 16 Architecture and Core Commands 95 arm966e cp15 regnum value Command
137. le which is sourced by your openocd cfg file or through a command line f interface cfg option source find interface olimex jtag tiny cfg These commands tell OpenOCD what type of JTAG adapter you have and how to talk to it few cases are so simple that you only need to say what driver to use jlink interface interface jlink Most adapters need a bit more configuration than that 8 1 Interface Configuration The interface command tells OpenOCD what type of debug adapter you are using De pending on the type of adapter you may need to use one or more additional commands to further identify or configure the adapter interface name Config Command Use the interface driver name to connect to the target interface list Command List the debug adapter drivers that have been built into the running copy of OpenOCD interface transports transport_namet Command Specifies the transports supported by this debug adapter The adapter driver builds in similar knowledge use this only when external configuration such as jumpering changes what the hardware can support adapter name Command Returns the name of the debug adapter driver being used Chapter 8 Debug Adapter Configuration 34 8 2 Interface Drivers Each of the interface drivers listed here must be explicitly enabled when OpenOCD is configured in order to be made available at run time amt jtagaccel Interface Driver Amontec Chameleon in its
138. lid frame It might be possible to prevent this by setting up a proper initial stack frame if you happen to know what exactly has to be done feel free to add this here Simple In your startup code push 8 registers of zeros onto the stack before calling main What GDB is doing is climbing the run time stack by reading various values on the stack using the standard call frame for the target GDB keeps going until one of 2 things happen 1 an invalid frame is found or 2 some huge number of stackframes have been processed By pushing zeros on the stack GDB gracefully stops Debugging Interrupt Service Routines In your ISR before you call your C code do the same artifically push some zeros onto the stack remember to pop them off when the ISR is done Also note If you have a multi threaded operating system they often do not in the intrest of saving memory waste these few bytes Painful 8 JTAG Reset Config I get the following message in the OpenOCD console or log file Warning arm7 9 common c 679 arm7_9_assert_reset srst resets test logic too This warning doesn t indicate any serious problem as long as you don t want to de bug your core right out of reset Your cfg file specified jtag reset trst and srst srst pulls trst to tell OpenOCD that either your board your debugger or your target uC e g LPC2000 can t assert the two reset signals independently With this setup it s not possible to halt the core right
139. locking when the core is inter rupted the operation completes then J TAG clocks are accepted at least until the interrupt handler completes However this workaround is often unusable since the processor board and JTAG adapter must all support adaptive J TAG clocking Also it can t work until an interrupt is issued A more complete workaround is to not use that operation while you work with a JTAG debugger Tasking environments generaly have idle loops where the body is the wait for interrupt operation On older cores it is a coprocessor action newer cores have a wfi instruction Such loops can just remove that operation at the cost of higher power consumption because the CPU is needlessly clocked resume address Command Resume the target at its current code position or the optional address if it is provided OpenOCD will wait 5 seconds for the target to resume step address Command Single step the target at its current code position or the optional address if it is provided reset Command reset run Command reset halt Command l reset init Command Perform as hard a reset as possible using SRST if possible All defined targets will be reset and target events will fire during the reset sequence The optional parameter specifies what should happen after the reset If there is no parameter a reset run is executed The other options will not work on all systems See Chapter 9 Reset Configuration page 41
140. lso use log output to redirect the log output to a file so as not to flood the stdin out pipes The p pipe option is deprecated and a warning is printed as it is equivalent to passing in c gdb port pipe log output openocd log Any other string is interpreted as named pipe to listen to Output pipe is the same name as input pipe but with o appended e g var gdb var gdbo The GDB port for the first target will be the base port the second target will listen on gdb_port 1 and so on When not specified during the configuration stage the port number defaults to 3333 tcl port number Command Specify or query the port used for a simplified RPC connection that can be used by clients to issue TCL commands and get the output from the Tcl engine Intended as a machine interface When not specified during the configuration stage the port number defaults to 6666 telnet port number Command Specify or query the port on which to listen for incoming telnet connections This port is intended for interaction with one human through TCL commands When not specified during the configuration stage the port number defaults to 4444 When specified as zero this port is not activated 7 4 GDB Configuration You can reconfigure some GDB behaviors if needed The ones listed here are static and global See Target Configuration page 54 about configuring individual targets See Target Events page 57 about configuring target specific e
141. m and platform identify and many other variables JimTCL as implemented in OpenOCD creates 0cd_ HOSTOS which holds one of the following values cygwin Running under Cygwin darwin Darwin Mac OS is the underlying operating sytem freebsd Running under FreeBSD linux Linux is the underlying operating sytem mingw32 Running under MingW32 winxx Built using Microsoft Visual Studio other Unknown none of the above Note winxx was choosen because today March 2009 no distinction is made between Win32 and Win64 Note We should add support for a variable like Tcl variable tcl platform platform it should be called jim platform because it is jim not real tcl Chapter 22 FAQ 112 22 FAQ 1 RTCK also known as Adaptive Clocking What is it In digital circuit design it is often refered to as clock synchronisation the JTAG interface uses one clock TCK or TCLK operating at some speed your CPU target is operating at another The two clocks are not synchronised they are asynchronous In order for the two to work together they must be synchronised well enough to work JTAG can t go ten times faster than the CPU for example There are 2 basic options 1 Use a special adaptive clocking circuit to change the JTAG clock rate to match what the CPU currently supports 2 The JTAG clock must be fixed at some speed that s enough slower than the CPU clock that all TMS and TDI transitions can be detected Does
142. mage eee 97 xscale vector_catch cece cece eee eee 97 xscale vector table Lees 97 SV EE 104
143. mber shown by the pld devices command and new PLDs are defined by pld device driver name pld device driver name tap name driver options Config Command Defines a new PLD device supported by driver driver name using the TAP named tap name The driver may make use of any driver_options to configure its behavior pld devices Command Lists the PLDs and their numbers pld load num filename Command Loads the file filename into the PLD identified by num The file format must be inferred by the driver 14 2 PLD FPGA Drivers Options and Commands Drivers may support PLD specific options to the pld device definition command and may also define commands usable only with that particular type of PLD virtex2 FPGA Driver Virtex II is a family of FPGAs sold by Xilinx It supports the IEEE 1532 standard for In System Configuration ISC No driver specific PLD definition options are used and one driver specific command is defined virtex2 read stat num Command Reads and displays the Virtex II status register STAT for FPGA num Chapter 15 General Commands 82 15 General Commands The commands documented in this chapter here are common commands that you as a human may want to type and see the output of Configuration type commands are docu mented elsewhere Intent e Source Of Commands OpenOCD commands can occur in a configuration script discussed elsewhere or typed manually by a human or supplied programaticall
144. mbers of the STM32f1x microcontroller family from ST Microelectronics in clude internal flash and use ARM Cortex M3 cores The driver automatically recog nizes a number of these chips using the chip identification register and autoconfigures itself flash bank FLASHNAME stm32fix O O O O TARGETNAME Some stm32f1x specific commands are defined stm32f1x lock num Command Locks the entire stm32 device The num parameter is a value shown by flash banks stm32f1x unlock num Command Unlocks the entire stm32 device The num parameter is a value shown by flash banks stm32fix options read num Command Read and display the stm32 option bytes written by the stm32f1x options write command The num parameter is a value shown by flash banks stm32f1x options write num SWWDG HWWDG Command RSTSTNDBY NORSTSTNDBY RSTSTOP NORSTSTOP Writes the stm32 option byte with the specified values The num parameter is a value shown by flash banks n Currently there is a stellaris mass erase command That seems pointless since the same effect can be had using the standard flash erase address command 2 Currently there is a stm32f1x mass erase command That seems pointless since the same effect can be had using the standard flash erase address command Chapter 12 Flash Commands 71 stm32f2x Flash Driver All members of the STM32f2x microcontroller family from ST Microelectronics in clude internal flas
145. ment to the section titles in the list of Invariant Sections in the license notice of the combined work In the combination you must combine any sections Entitled History in the vari ous original documents forming one section Entitled History likewise combine any sections Entitled Acknowledgements and any sections Entitled Dedications You must delete all sections Entitled Endorsements 6 COLLECTIONS OF DOCUMENTS You may make a collection consisting of the Document and other documents released under this License and replace the individual copies of this License in the various documents with a single copy that is included in the collection provided that you follow the rules of this License for verbatim copying of each of the documents in all other respects You may extract a single document from such a collection and distribute it individu ally under this License provided you insert a copy of this License into the extracted document and follow this License in all other respects regarding verbatim copying of that document 7 AGGREGATION WITH INDEPENDENT WORKS A compilation of the Document or its derivatives with other separate and independent documents or works in or on a volume of a storage or distribution medium is called Appendix A The GNU Free Documentation License 128 10 an aggregate if the copyright resulting from the compilation is not used to limit the legal rights of the compilation s
146. might be specified as one field of 32 bits then one of 6 bits For portability never pass fields which are more than 32 bits long Many OpenOCD implementations do not support 64 bit or larger integer values All TAPs other than tap must be in BYPASS mode The single bit in their data registers does not matter When tap state is specified the JTAG state machine is left in that state For example DRPAUSE might be specified so that more instructions can be issued before re entering the RUN IDLE state If the end state is not specified the RUN IDLE state is entered Warning OpenOCD does not record information about data register lengths so it is important that you get the bit field lengths right Re member that different J TAG instructions refer to different data registers which may have different lengths Moreover those lengths may not be fixed the SCAN N instruction can change the length of the register ac cessed by the INTEST instruction by connecting a different scan chain Chapter 17 JTAG Commands 102 flush count Command Returns the number of times the JTAG queue has been flushed This may be used for performance tuning For example flushing a queue over USB involves a minimum latency often several milliseconds which does not change with the amount of data which is written You may be able to identify performance problems by finding tasks which waste bandwidth by flushing small transfers too often instead of batching th
147. n Remember earlier There are no control flow statements in Tcl Instead there are COM MANDS that simply act like control flow operators Commands are executed like this 1 Parse the next line into argc and argv 2 Look up argv 0 in a table and call its function 3 Repeat until End Of File It sort of works like this for ReadAndParse amp argc amp argv Chapter 23 Tcl Crash Course 119 cmdPtr LookupCommand argv 0 cmdPtr gt Execute argc argv When the command proc is parsed which creates a procedure function it gets 3 parame ters on the command line 1 the name of the proc function 2 the list of parameters and 3 the body of the function Not the choice of words LIST and BODY The PROC command stores these items in a table somewhere so it can be found by LookupCommand 23 5 3 The FOR command The most interesting command to look at is the FOR command In Tcl the FOR command is normally implemented in C Remember FOR is a command just like any other command When the ascii text containing the FOR command is parsed the parser produces 5 param eter strings If in doubt Refer to Rule 1 they are 0 The ascii text for 1 The start text 2 The test expression 3 The next text 4 The body text Sort of reminds you of main int argc char argv does it not Remember Rule 1 Everything is a string The key point is this Often many of those parameters
148. n blocks JTAG access Adap tive clocking provides a partial workaround but a more complete solution just avoids using that instruction with JTAG debuggers If both the chip and the board support adaptive clocking use the jtag rclk command in case your board is used with JTAG adapter which also supports it Otherwise use adapter_ khz Set the slow rate at the beginning of the reset sequence and the faster rate as soon as the clocks are at full speed 1 A FAQ http www arm com support faqdev 4170 htm1 gives details Chapter 6 Config File Guidelines 24 6 3 Target Config Files Board config files communicate with target config files using naming conventions as de scribed above and may source one or more target config files like this source find target FOOBAR cfg The point of a target config file is to package everything about a given chip that board config files need to know In summary the target files should contain 1 Set defaults 2 Add TAPs to the scan chain 3 Add CPU targets includes GDB support 4 CPU Chip CPU Core specific features 5 On Chip flash As a rule of thumb a target file sets up only one chip For a microcontroller that will often include a single TAP which is a CPU needing a GDB target and its on chip flash More complex chips may include multiple TAPs and the target config file may need to define them all before OpenOCD can talk to the chip For example some phone chips have JTAG scan chains
149. n provided poke Command No description provided rm filename Command Unlinks the file filename trunc filename Command Removes all data in the file filename 15 4 Memory access commands These commands allow accesses of a specific size to the memory system Often these are used to configure the current target in some special way For example one may need to write certain values to the SDRAM controller to enable SDRAM 1 Use the targets plural command to change the current target 2 In system level scripts these commands are deprecated Please use their TARGET object siblings to avoid making assumptions about what TAP is the current target or about MMU configuration mdw phys addr count Command mdh phys addr count Command mdb phys addr count Command Display contents of address addr as 32 bit words mdw 16 bit halfwords mdh or 8 bit bytes ndb When the current target has an MMU which is present and active Chapter 15 General Commands 86 addr is interpreted as a virtual address Otherwise or if the optional phys flag is specified addr is interpreted as a physical address If count is specified displays that many units If you want to manipulate the data instead of displaying it see the mem2array primitives mww phys addr word Command mwh phys addr halfword Command mwb phys addr byte Command Writes the specified word 32 bits halfword 16 bits or byte 8
150. name cget endian set z name cget typel puts format Chip Ad is s Endian As type AS x name y z target_name curstate Command Displays the current target state debug running halted reset running or unknown Also see Event Polling page 31 target_name eventlist Command Displays a table listing all event handlers currently associated with this target See Target Events page 57 target name invoke event event name Command Invokes the handler for the event named event name This is primarily intended for use by OpenOCD framework code for example by the reset code in startup tcl target name mdw addr count Command target name mdh addr count Command target name mdb addr count Command Display contents of address addr as 32 bit words mdw 16 bit halfwords mdh or 8 bit bytes mdb If count is specified displays that many units If you want to manipulate the data instead of displaying it see the mem2array primitives target name mww addr word Command target name mwh addr halfword Command target name mwb addr byte Command Writes the specified word 32 bits halfword 16 bits or byte 8 bit pattern at the specified address addr Chapter 11 CPU Configuration 58 11 5 Target Events At various times certain things can happen or you want them to happen For example What should happen when GDB connects Should your target reset When GDB tries to f
151. name type Command Writes the content of the file into the customer info space of the flash index sector T he filetype can be specified with the type field Possible values for type Chapter 12 Flash Commands 69 are bin binary ihex Intel hex format elf ELF binary or s19 Motorola S records The file must contain a single section and the contained data length must be exactly 912 bytes Attention This cannot be reverted Be careful Example 1pc2900 write custom 0 path to customer info bin bin 1lpc2900 secure sector bank first last Command Secures the sector range from first to last including against further program and erase operations The sector security will be effective after the next power cycle Attention This cannot be reverted Be careful Secured sectors appear as protected in the flash info command Example lpc2900 secure sector O 1 1 flash info 0 0 l1pc2900 at 0x20000000 size 0x000c0000 0 0x00000000 0x2000 8kB not protected 1 0x00002000 0x2000 8kB protected 2 0x00004000 0x2000 8kB not protected 1pc2900 secure_jtag bank Command Irreversibly disable the JTAG port The new JTAG security setting will be effective after the next power cycle Attention This cannot be reverted Be careful Examples lpc2900 secure jtag 0 oci Flash Driver No idea what this is other than using some arm7 arm9 core flash bank FLASHNAME ocl O O O O TARGETNAME pic32mx Flash Dri
152. name value pair list and lists Name value pair The proc foo below returns a name value pair list set foo me Duane set foo you Oyvind set foo mouse Micky gt gt gt set foo duck Donald If one does this gt set foo The result is me Duane you Oyvind mouse Micky duck Donald Thus to get the names of the associative array is easy foreach name value set foo 1 puts Name name Value value Lists returned must be relatively small Otherwise a range should be passed in to the proc in question 21 2 Internal low level Commands By low level the intent is a human would not directly use these commands Low level commands are should be prefixed with ocd e g ocd flash banks is the low level API upon which flash banks is implemented e mem2array lt varname gt width lt addr gt lt nelems gt Read memory and return as a Tcl array for script processing e array2mem lt varname gt width lt addr gt lt nelems gt Convert a Tcl array to memory locations and write the values e ocd flash banks driver base size chip width bus width target driver options Return information about the flash banks OpenOCD commands can consist of two words e g flash banks The startup tcl unknown proc will translate this into a Tcl proc called flash banks Chapter 21 Tcl Scripting API 111 21 3 OpenOCD specific Global Variables Real Tcl has tcl_platfor
153. nd a working sequence it can be used to override jtag init which fires during OpenOCD startup see Configuration Stage page 29 or init reset which fires during reset processing You might also want to provide some project specific reset schemes For example on a multi target board the standard reset command would reset all targets but you may need the ability to reset only one target at time and thus want to avoid using the board wide SRST signal init reset mode Overridable Procedure This is invoked near the beginning of the reset command usually to provide as much of a cold power up reset as practical By default it is also invoked from jtag init if the scan chain does not respond to pure JTAG operations The mode parameter is the parameter given to the low level reset command halt init or run setup or potentially some other value The default implementation just invokes jtag arp init reset Replacements will normally build on low level JTAG operations such as jtag reset Operations here must not address individual TAPs or their associated targets until the JTAG scan chain has first been verified to work Implementations must have verified the JTAG scan chain before they return This is done by calling jtag arp init or jtag arp init reset Chapter 9 Reset Configuration 45 jtag arp init Command This validates the scan chain using just the four standard JTAG signals TMS TCK TDI TDO It
154. nds on the host GPIO naming convention Currently the mflash driver supports s3c2440 and pxa270 Example for s3c2440 mflash where RST pin is GPIO B1 Chapter 12 Flash Commands T4 mflash bank FLASHNAME s3c2440 0x10000000 1b O Example for pxa270 mflash where RST pin is GPIO 43 mflash bank FLASHNAME pxa270 0x08000000 43 0 12 5 2 mFlash commands mflash config pll frequency Command Configure mflash PLL The frequency is the mflash input frequency in Hz Issu ing this command will erase mflash s whole internal nand and write new pll After this command mflash needs power on reset for normal operation If pll was newly configured storage and boot optional info also need to be update mflash config boot Command Configure bootable option If bootable option is set mflash offer the first 8 sectors 4kB for boot mflash config storage Command Configure storage information For the normal storage operation this information must be written mflash dump num filename offset size Command Dump size bytes starting at offset bytes from the beginning of the bank num to the file named filename mflash probe Command Probe mflash mflash write num filename offset Command Write the binary file filename to mflash bank num starting at offset bytes from the beginning of the bank Chapter 13 NAND Flash Commands 75 13 NAND Flash Commands Compared to NOR or SPI flash NAND devices are inexpensive and high density Toda
155. ned Sege ade Seba etica 31 8 Debug Adapter Configuration 33 8 1 Interface Configuration eee 33 8 2 Interface Divers 34 8 3 Transport Configuration eee ee 39 8 89 4 JTAG Transport 0 00 ccc eee eee nes 39 8 3 2 SWD Transports se ose m xr seen ae eee nana ES 39 8 8 8 SPI Iransport 0 0 cece enne 39 BA JTAG Speed osc ccs duse NEE EN wines sia EAD 39 9 Reset Conbeuration ss 41 HI Types ot Reset noi he oen eR NEEN Nerds Al 9 2 SRST and TRST Joes Al 9 3 Commands for Handling Resets cece eee eee eee 42 9 4 Custom Reset Handi 44 10 TAP Declaration eed cet hte es 46 10 1 Scan Chains IR n hei d RR EE 46 10 2 TAP N am s lege Y etes sieeve RW AT 10 3 TAP Declaration Commandes 47 10 4 Other TAP commande 49 10 5 TAP Events ve te eae aa ee T EIE nan e Edge 49 10 6 Enabling and Disabling DAP 50 10 7 Autoprobung 6 cece se 51 11 CPU Conbeuraton 52 LL Target DEE 52 11 2 Target CPU Types and VManants rn rrre en 53 11 3 Target Configuration 0 00 cece eee n 54 11 4 Other target name Commande 56 11 5 Target Events ke e RR EE dau xa 58 12 Flash Commede mg eng iue or hes 61 12 1 Flash Configuration Commandes 61 12 2 Erasing Reading Writing to lach 62 12 3 Other Flash commande 64 12 4 Flash Driver bist cere me nee decade ae ew eee SER 64 12 4 1 External Hiash 0 00 c cece eens 64 12 4 2 Internal Flash Microcontrollers
156. nferred from the address of each image section Warning Be careful using the erase flag when the flash is holding data you want to preserve Portions of the flash outside those described in the image s sections might be erased with no notice e When a section of the image being written does not fill out all the sectors it uses the unwritten parts of those sectors are necessarily also erased because sectors can t be partially erased e Data stored in sector holes between image sections are also af fected For example flash write_image erase of an image with one byte at the beginning of a flash bank and one byte at the end erases the entire bank not just the two sectors being written Also when flash protection is important you must re apply it after it has been removed by the unlock flag Chapter 12 Flash Commands 64 12 3 Other Flash commands flash erase check num Command Check erase state of sectors in flash bank num and display that status The num parameter is a value shown by flash banks flash info num Command Print info about flash bank num The num parameter is a value shown by flash banks This command will first query the hardware it does not print cached and possibly stale information flash protect num first last on off Command Enable on or disable off protection of flash sectors in flash bank num starting at sector first and continuing up to and includin
157. ng reset and in some cases target config files rather than board config files are the right places to handle some of those issues For example immediately after reset most chips run using a slower clock than they will use later That means that after reset and potentially as OpenOCD first starts up they must use a slower JTAG clock rate than they will use later See JTAG Speed page 39 Important When you are debugging code that runs right after chip reset getting these issues right is critical In particular if you see intermittent failures when OpenOCD verifies the scan chain after reset look at how you are setting up JTAG clocking 6 3 6 ARM Core Specific Hacks If the chip has a DCC enable it If the chip is an ARM9 with some special high speed download features enable it If present the MMU the MPU and the CACHE should be disabled Some ARM cores are equipped with trace support which permits examination of the in struction and data bus activity Trace activity is controlled through an Embedded Trace Module ETM on one of the core s scan chains The ETM emits voluminous data through a trace port See ARM Hardware Tracing page 88 If you are using an external trace port configure it in your board config file If you are using an on chip Embedded Trace Buffer ETB configure it in your target config file etm config _TARGETNAME 16 normal full etb etb config _TARGETNAME _CHIPNAME etb 6 3 7 I
158. ngles USB based par allel port based and other standalone boxes that run OpenOCD internally See Chapter 2 Debug Adapter Hardware page 5 GDB Debug It allow ARM7 ARM7TDMI and ARM720t ARM9 ARM920T ARM922T ARM926EJ S ARM966E S XScale PXA25x IXP42x and Cortex M3 Stellaris LM3 and ST STM32 based cores to be debugged via the GDB protocol Flash Programing Flash writing is supported for external CFI compatible NOR flashes Intel and AMD Spansion command set and several internal flashes LPC1700 LPC2000 AT91SAM7 AT91SAMS3U STR7x STR9x LM3 and STM32x Preliminary support for various NAND flash controllers LPC3180 Orion S3C24xx more controller is included About 2 OpenOCD Web Site The OpenOCD web site provides the latest public news from the community http openocd berlios de web Latest User s Guide The user s guide you are now reading may not be the latest one available A version for more recent code may be available Its HTML form is published irregularly at http openocd berlios de doc html index html PDF form is likewise published at http openocd berlios de doc pdf openocd pdf OpenOCD User s Forum There is an OpenOCD forum phpBB hosted by SparkFun which might be helpful to you Note that if you want anything to come to the attention of developers you should post it to the OpenOCD Developer Mailing List instead of this forum http forum sparkfun com viewforum php f 18 Chapter 1 Op
159. nology Devices International FTDI known as the FTDI FT2232 this is a USB full speed 12 Mbps chip See http www ftdichip com for more information In summer 2009 USB high speed 480 Mbps versions of these FTDI chips are starting to become available in JTAG adapters Adapters using those high speed FT2232H chips may support adaptive clocking The FT2232 chips are flexible enough to support some other transport options such as SWD or the SPI variants used to program some chips They have two communications channels and one can be used for a UART adapter at the same time the other one is used to provide a debug adapter Also some development boards integrate an F T2232 chip to serve as a built in low cost debug adapter and usb to serial solution Chapter 2 Debug Adapter Hardware 6 e usbjtag Link http www hs augsburg de hhoegl proj usbjtag usbjtag html e jtagkey See http www amontec com jtagkey shtml e jtagkey2 See http www amontec com jtagkey2 shtml e oocdlink See http www oocdlink com By Joern Kaipf e signalyzer See http www signalyzer com e Stellaris Eval Boards See http www luminarymicro com The Stellaris eval boards bundle FT2232 based JTAG and SWD support which can be used to debug the Stellaris chips Using separate JTAG adapters is optional These boards can also be used in a pass through mode as JTAG adapters to other target boards disabling the Stellaris chip e Luminary ICDI See http
160. nown It is recommended that you provide zeroes for all of those values except the clock frequency so that everything except that frequency will be autoconfigured Knowing the frequency helps ensure correct timings for flash access The flash controller handles erases automatically on a page 128 256 byte basis so explicit erase commands are not necessary for flash programming However there is an EraseAll command that can erase an entire flash plane of up to 256KB and it will be used automatically when you issue flash erase sector or flash erase address commands at91sam 7 gpnvm bitnum set clear Command Set or clear a General Purpose Non Volatile Memory GPNVM bit for the processor Each processor has a number of such bits used for controlling fea tures such as brownout detection so they are not truly general purpose Chapter 12 Flash Commands 67 Note This assumes that the first flash bank number 0 is associ ated with the appropriate at91sam7 target avr Flash Driver The AVR 8 bit microcontrollers from Atmel integrate flash memory The current implementation is incomplete ecosflash Flash Driver No idea what this is l he ecosflash driver defines one mandatory parameter the name of a modules of target code which is downloaded and executed 1pc2000 Flash Driver Most members of the LPC1700 and LPC2000 microcontroller families from NXP in clude internal flash and use Cortex M3 LPC1700
161. nted here ZY1000 Interface Driver This is the Zylin ZY1000 JTAG debugger Note This defines some driver specific commands which are not currently documented here power on off Command Turn power switch to target on off No arguments print status Chapter 8 Debug Adapter Configuration 39 8 3 Transport Configuration As noted earlier depending on the version of OpenOCD you use and the debug adapter you are using several transports may be available to communicate with debug targets or perhaps to program flash memory transport list Command displays the names of the transports supported by this version of OpenOCD transport select ransport name Command Select which of the supported transports to use in this OpenOCD session The transport must be supported by the debug adapter hardware and by the version of OPenOCD you are using including the adapter s driver No arguments returns name of session s selected transport 8 3 1 JTAG Transport JTAG is the original transport supported by OpenOCD and most of the OpenOCD com mands support it JTAG transports expose a chain of one or more Test Access Points TAPs each of which must be explicitly declared JTAG supports both debugging and boundary scan testing Flash programming support is built on top of debug support 8 3 2 SWD Transport SWD Serial Wire Debug is an ARM specific transport which exposes one Debug Access Point DAP which must be expli
162. nternal Flash Configuration This applies ONLY TO MICROCONTROLLERS that have flash built in Chapter 6 Config File Guidelines 28 Never ever in the target configuration file define any type of flash that is external to the chip For example a BOOT flash on Chip Select 0 Such flash information goes in a board file not the TARGET chip file Examples e at91sam7x256 has 256K flash YES enable it e str912 has flash internal YES enable it e imx27 uses boot flash on CSO it goes in the board file e pxa270 again CSO flash it goes in the board file 6 4 Translating Configuration Files If you have a configuration file for another hardware debugger or toolset Abatron BDI2000 BDI3000 CCS Lauterbach Segger Macraigor etc translating it into OpenOCD syntax is often quite straightforward The most tricky part of creating a configuration script is oftentimes the reset init sequence where e g PLLs DRAM and the like is set up One trick that you can use when translating is to write small Tcl procedures to translate the syntax into OpenOCD syntax This can avoid manual translation errors and make it easier to convert other scripts later on Example of transforming quirky arguments to a simple search and replace job Lauterbach syntax Data Set c15 0x042f long 0x40000015 OpenOCD syntax when using procedure below dk dk dk E E Gt setci5 0x01 0x00050078 proc setc15 regs value global TARGETNAME echo
163. ntical For Method 3 and 4 it is more interesting What is the TCLBODY Remember the parsing rules In case 3 curly braces mean the VARS and square brackets are expanded later when the EVENT occurs and the text is evaluated In case 4 they are replaced before the Target Object Command is executed This occurs at the same time TARGETNAME is replaced In case 4 the date will never change BTW date is a bad example at this writing Jim OpenOCD does not have a date command 23 6 4 Global Variables Where You might discover this when writing your own procs In simple terms Inside a PROC if you need to access a global variable you must say so See also upvar Example proc myproc 1 set y 0 Local variable Y global x Global variable X puts format X d Y A4d x y 23 7 Other Tcl Hacks Dynamic variable creation Dynamically create a bunch of variables for set x 0 x lt 32 set x expr x 1 1 Create var name set vn format BIT d x Make it a global global vn Set it set vn expr 1 lt lt x Dynamic proc command creation One X function 5 uart functions foreach who A B C D E proc format show uart c who show UARTx who Appendix A The GNU Free Documentation License 123 Appendix A The GNU Free Documentation License Version 1 2 November 2002 Copyright c 2000 2001 2002 Free Software Foundation Inc 51 Franklin St Fifth Floo
164. ny blocks it has The num parameter is the value shown by nand list You must successfully probe a device before you can use it with most other NAND commands 13 2 Erasing Reading Writing to NAND Flash nand dump num filename offset length oob option Command Reads binary data from the NAND device and writes it to the file starting at the specified offset The num parameter is the value shown by nand list Use a complete path name for filename so you don t depend on the directory used to start the OpenOCD server The offset and length must be exact multiples of the device s page size They describe a data region the OOB data associated with each such page may also be accessed NOTE At the time this text was written no error correction was done on the data that s read unless raw access was disabled and the underlying NAND controller driver had a read page method which handled that error correction By default only page data is saved to the specified file Use an oob option parameter to save OOB data Chapter 13 NAND Flash Commands 77 nand nand e no oob_ parameter Output file holds only page data OOB is discarded e oob raw Output file interleaves page data and OOB data the file will be longer than length by the size of the spare areas associated with each data page Note that this kind of raw access is different from what s implied by nand raw access which just controls whether a hardware aware access method
165. ome cases configuring a flash bank will activate extra commands see the driver specific documentation e name may be used to reference the flash bank in other flash commands A number is also available e driver identifies the controller driver associated with the flash bank being de clared This is usually cfi for external flash or else the name of a microcontroller with embedded flash memory See Flash Driver List page 64 e base Base address of the flash chip e size Size of the chip in bytes For some drivers this value is detected from the hardware e chip width Width of the flash chip in bytes ignored for most microcontroller drivers e bus width Width of the data bus used to access the chip in bytes ignored for most microcontroller drivers Chapter 12 Flash Commands 62 e target Names the target used to issue commands to the flash controller e driver options drivers may support or require additional parameters See the driver specific documentation for more information Note This command is not available after OpenOCD initialization has completed Use it in board specific configuration files not interactively flash banks Command Prints a one line summary of each device that was declared using flash bank num bered from zero Note that this is the plural form the singular form is a very different command flash list Command Retrieves a list of associative arrays for each d
166. ommand line or to GDB Examples of such events include e One of the targets can stop running maybe it triggers a code breakpoint or data watchpoint or halts itself e Messages may be sent over debug message channels many targets support such messages sent over JTAG for receipt by the person debugging or tools e Loss of power some adapters can detect these events e Resets not issued through JTAG such reset sources can include button presses or other system hardware sometimes including the target itself perhaps through a watchdog e Debug instrumentation sometimes supports event triggering such as trace buffer full so it can quickly be emptied or other signals to correlate with code behavior None of those events are signaled through standard JTAG signals However most conven tions for JTAG connectors include voltage level and system reset SRST signal detection Some connectors also include instrumentation signals which can imply events when those signals are inputs In general OpenOCD needs to periodically check for those events either by looking at the status of signals on the JTAG connector or by sending synchronous tell me your status JTAG requests to the various active targets There is a command to manage and monitor that polling which is normally done in the background Chapter 7 Daemon Configuration 32 poll on off Command Poll the current target for its current st
167. onfiguration option Chapter 20 GDB and OpenOCD 108 gdb memory map disable For this to function correctly a valid flash configuration must also be set in OpenOCD For faster performance you should also configure a valid working area Informing GDB of the memory map of the target will enable GDB to protect any flash areas of the target and use hardware breakpoints by default This means that the OpenOCD option gdb breakpoint override is not required when using a memory map See gdb breakpoint override page 30 To view the configured memory map in GDB use the GDB command info mem All other unassigned addresses within GDB are treated as RAM GDB 6 8 and higher set any memory area not in the memory map as inaccessible This can be changed to the old behaviour by using the following GDB command set mem inaccessible by default off If gdb_flash_program enable is also used GDB will be able to program any flash memory using the vFlash interface GDB will look at the target memory map when a load command is given if any areas to be programmed lie within the target flash area the vFlash packets will be used If the target needs configuring before GDB programming an event script can be executed _TARGETNAME configure event EVENTNAME BODY To verify any flash programming the GDB command compare sections can be used 20 5 Using openocd SMP with GDB For SMP support following GDB serial protocol packet have been defined
168. or ARM7TDMI LPC2000 cores Note There are LPC2000 devices which are not supported by the Ipc2000 driver The LPC2888 is supported by the Ipc288x driver The LPC29xx family is supported by the Ipc2900 driver The Ipc2000 driver defines two mandatory and one optional parameters which must appear in the following order e variant required may be 1pc2000 vi older LPC21xx and LPC22xx 1pc2000 v2 LPC213x LPC214x LPC210 123 LPC23xx and LPC24xx or 1pc1700 LPC175x and LPC176x e clock kHz the frequency in kiloHertz at which the core is running e calc_checksum optional but you probably want to provide this telling the driver to calculate a valid checksum for the exception vector table Note If you don t provide calc_checksum when you re writing the vector table the boot ROM will almost certainly ignore your flash image However if you do provide it with most tool chains verify image will fail LPC flashes don t require the chip and bus width to be specified flash bank FLASHNAME lpc2000 OxO Ox7d000 O O TARGETNAME lpc2000 v2 14765 calc checksum lpc2000 part id bank Command Displays the four byte part identifier associated with the specified flash bank lpc288x Flash Driver The LPC2888 microcontroller from NXP needs slightly different flash support from its Ipc2000 siblings The Ipc288x driver defines one mandatory parameter the pro gramming clock rate in Hz LPC flashes don t require
169. otag Integrated with a Redbee development board redbee usb Integrated with a Redbee USB stick development board sheevaplug Marvell Sheevaplug development kit signalyzer Xverve Signalyzer stm32stick Hitex STM32 Performance Stick turtelizer2 egnite Software turtelizer2 usbjtag USBJTAG 1 layout described in the OpenOCD diploma thesis ft2232 vid pid vid pid Config Command The vendor ID and product ID of the FTDI FT2232 device If not specified the FTDI default values are used Currently up to eight vid pid pairs may be given e g ft2232 vid pid 0x0403 Oxcff8 Oxib5bba 0x0003 ft2232 latency ms Config Command On some systems using F T2232 based JTAG interfaces the FT Read function call in ft2232 read fails to return the expected number of bytes This can be caused by USB communication delays and has proved hard to reproduce and debug Setting the FT2232 latency timer to a larger value increases delays for short USB packets but it also reduces the risk of timeouts before receiving the expected number of bytes The OpenOCD default value is 2 and for some systems a value of 10 has proved useful For example the interface config file for a Turtelizer J TAG Adapter looks something like this Chapter 8 Debug Adapter Configuration 36 interface ft2232 ft2232 device desc Turtelizer JTAG RS232 Adapter ft2232 layout turtelizer2 ft2232 vid pid 0x0403 Oxbdc8 usb blaster Interface Driver USB JTAG US
170. owledgements Dedications or His tory the requirement section 4 to Preserve its Title section 1 will typically require changing the actual title TERMINATION You may not copy modify sublicense or distribute the Document except as expressly provided for under this License Any other attempt to copy modify sublicense or distribute the Document is void and will automatically terminate your rights under this License However parties who have received copies or rights from you under this License will not have their licenses terminated so long as such parties remain in full compliance FUTURE REVISIONS OF THIS LICENSE The Free Software Foundation may publish new revised versions of the GNU Free Documentation License from time to time Such new versions will be similar in spirit to the present version but may differ in detail to address new problems or concerns See http www gnu org copyleft Each version of the License is given a distinguishing version number If the Document specifies that a particular numbered version of this License or any later version applies to it you have the option of following the terms and conditions either of that specified version or of any later version that has been published not as a draft by the Free Software Foundation If the Document does not specify a version number of this License you may choose any version ever published not as a draft by the Free Software Foundat
171. p vendor but overridable The tapname reflects the role of that TAP and should follow this convention See the ST document titled STR91xFAzzz Section 3 15 Jtag Interface Page 28 102 Figure 3 JTAG chaining inside the STR91xFA http eu st com stonline products literature ds 13495 pdf Chapter 10 TAP Declaration 48 e bs For boundary scan if this is a seperate TAP e cpu The main CPU of the chip alternatively arm and dsp on chips with both ARM and DSP CPUs armi and arm2 on chips two ARMs and so forth e etb For an embedded trace buffer example an ARM ETB11 e flash If the chip has a flash TAP like the str912 e jrc For JTAG route controller example the ICEpick modules on many Texas Instruments chips like the OMAP3530 on Beagleboards e tap Should be used only FPGA or CPLD like devices with a single TAP e unknownN If you have no idea what the TAP is for N is a number e when in doubt Use the chip maker s name in their data sheet For example the Freescale IMX31 has a SDMA Smart DMA with a JTAG TAP that TAP should be named sdma Every TAP requires at least the following configparams e irlen NUMBER The length in bits of the instruction register such as 4 or 5 bits A TAP may also provide optional configparams e disable or enable Use the disable parameter to flag a TAP which is not linked in to the scan chain after a reset using either TRST or the JTAG state machine s R
172. particular target NOTE As this is written September 2009 nothing prevents such access e setup The scan chain has been reset and verified This handler may enable TAPs as needed e tap disable The TAP needs to be disabled This handler should implement jtag tapdisable by issuing the relevant JTAG commands e tap enable The TAP needs to be enabled This handler should implement jtag tapenable by issuing the relevant JTAG commands If you need some action after each J AG reset which isn t actually specific to any TAP since you can t yet trust the scan chain s contents to be accurate you might jtag configure CHIP jrc event post reset echo JTAG Reset done non scan jtag operations to be done after reset Chapter 10 TAP Declaration 50 10 6 Enabling and Disabling TAPs In some systems a JTAG Route Controller JRC is used to enable and or disable spe cific JTAG TAPs Many ARM based chips from Texas Instruments include an ICEpick module which is a JRC Such chips include DaVinci and OMAPS processors A given TAP may not be visible until the JRC has been told to link it into the scan chain and if the JRC has been told to unlink that TAP it will no longer be visible Such routers address problems that JTAG bypass mode ignores such as e The scan chain can only go as fast as its slowest TAP e Having many TAPs slows instruction scans since all TAPs receive new instructions e TAPs in the scan chain must be
173. powered up which wastes power and prevents debug ging some power management mechanisms The IEEE 1149 1 JTAG standard has no concept of a disabled tap as implied by the existence of JTAG routers However the upcoming IEEE 1149 7 framework layered on top of JTAG does include a kind of JTAG router functionality In OpenOCD tap enabling disabling is invoked by the Tcl commands shown below and is implemented using TAP event handlers So for example when defining a TAP for a CPU connected to a JTAG router your target cfg file should define TAP event handlers using code that looks something like this jtag configure CHIP cpu event tap enable 1 jtag operations using CHIP jrc jtag configure CHIP cpu event tap disable jtag operations using CHIP jrc Then you might want that CPU s TAP enabled almost all the time jtag configure CHIP jrc event setup jtag tapenable CHIP cpu Note how that particular setup event handler declaration uses quotes to evaluate CHIP when the event is configured Using brackets would cause it to be evaluated later at runtime when it might have a different value jtag tapdisable dotted name Command If necessary disables the tap by sending it a tap disable event Returns the string 1 if the tap specified by dotted name is enabled and 0 if it is disabled jtag tapenable dotted name Command If necessary enables the tap by sending it a tap enable event Returns t
174. r Boston MA 02110 1301 USA Everyone is permitted to copy and distribute verbatim copies of this license document but changing it is not allowed 0 PREAMBLE The purpose of this License is to make a manual textbook or other functional and useful document free in the sense of freedom to assure everyone the effective freedom to copy and redistribute it with or without modifying it either commercially or non commercially Secondarily this License preserves for the author and publisher a way to get credit for their work while not being considered responsible for modifications made by others This License is a kind of copyleft which means that derivative works of the document must themselves be free in the same sense It complements the GNU General Public License which is a copyleft license designed for free software We have designed this License in order to use it for manuals for free software because free software needs free documentation a free program should come with manuals providing the same freedoms that the software does But this License is not limited to software manuals it can be used for any textual work regardless of subject matter or whether it is published as a printed book We recommend this License principally for works whose purpose is instruction or reference 1 APPLICABILITY AND DEFINITIONS This License applies to any manual or other work in any medium that contains a notice placed by the copyright
175. r a bit more involved like a NAND or NOR flash controller driver or a big piece of work like supporting a new chip architecture Reuse the existing config files when you can Look first in the scripts boards area then scripts targets You may find a board configuration that s a good example to follow When you write config files separate the reusable parts things every user of that interface chip or board needs from ones specific to your environment and debugging approach Chapter 5 OpenOCD Project Setup 15 e lor example a gdb attach event handler that invokes the reset init command will interfere with debugging early boot code which performs some of the same actions that the reset init event handler does e Likewise the arm9 vector catch command or its siblings xscale vector catch and cortex m3 vector catch can be a timesaver during some debug sessions but don t make everyone use that either Keep those kinds of debugging aids in your user config file along with messaging and tracing setup See Software Debug Messages and Tracing page 99 e You might need to override some defaults For example you might need to move shrink or back up the target s work area if your application needs much SRAM e TCP IP port configuration is another example of something which is environment specific and should only appear in a user config file See TCP IP Ports page 30 5 5 Project Specific Utilities A few project
176. r example most ARM cores accept at most one sixth of the CPU clock Speed 0 khz selects RTCK method See FAQ RTCK page 112 If your system uses RICK you won t need to change the JTAG clocking after setup Not all interfaces boards or targets support rtck If the interface device can not support it an error is returned when you try to use RTCK jtag_rclk fallback speed kHz Function This Tcl proc defined in startup tcl attempts to enable RTCK RCLK If that fails maybe the interface board or target doesn t support it falls back to the specified frequency Fall back to 3mhz if RTCK is not supported jtag_rclk 3000 Chapter 9 Reset Configuration 41 9 Reset Configuration Every system configuration may require a different reset configuration This can also be quite confusing Resets also interact with reset init event handlers which do things like setting up clocks and DRAM and JTAG clock rates See JTAG Speed page 39 They can also interact with JTAG routers Please see the various board files for examples Note To maintainers and integrators Reset configuration touches several things at once Normally the board configuration file should define it and as sume that the JTAG adapter supports everything that s wired up to the board s JTAG connector However the target configuration file could also make note of something the sil icon vendor has done inside the chip which will be true for most or
177. r the definitions of these registers read ARM publication HI 0014 Embedded Trace Macrocell Architecture Specification Be aware that most of the relevant registers are write only and that ETM resources are limited There are only a handful of address comparators data comparators counters and so on Examples of scenarios you might arrange to trace include e Code flow within a function excluding subroutines it calls Use address range com parators to enable tracing for instruction access within that function s body e Code flow within a function including subroutines it calls Use the sequencer and address comparators to activate tracing on an entered function state then deactivate it by exiting that state when the function s exit code is invoked e Code flow starting at the fifth invocation of a function combining one of the above models with a counter e CPU data accesses to the registers for a particular device using address range com parators and the ViewData logic e Such data accesses only during IRQ handling combining the above model with se quencer triggers which on entry and exit to the IRQ handler e more At this writing September 2009 there are no Tcl utility procedures to help set up any common tracing scenarios etm analyze Command Reads trace data into memory if it wasn t already present Decodes and prints the data that was collected etm dump filename Command Stores the captured trace
178. r9xpec Flash Driver Only use this driver for locking unlocking the device or configuring the option bytes Use the standard str9 driver for programming Before using the flash commands the turbo mode must be enabled using the str9xpec enable_turbo command Several str9xpec specific commands are defined str9xpec disable turbo num Command Restore the str9 into JTAG chain str9xpec enable turbo num Command Enable turbo mode will simply remove the str9 from the chain and talk directly to the embedded flash controller str9xpec lock num Command Lock str9 device The str9 will only respond to an unlock command that will erase the device str9xpec part id num Command Prints the part identifier for bank num str9xpec options cmap num bankO bank1 Command Configure str9 boot bank str9xpec options lvdsel num vdd vdd_vddq Command Configure str9 lvd source str9xpec options lvdthd num 2 4v 2 7v Command Configure str9 bd threshold str9xpec options lvdwarn bank vdd vdd_vddq Command Configure str9 lvd reset warning source str9xpec options read num Command Read str9 option bytes str9xpec options write num Command Write str9 option bytes str9xpec unlock num Command unlock str9 device 12 5 mFlash 12 5 1 mFlash Configuration mflash bank soc base RST_pin target Config Command Configures a mflash for soc host bank at address base The pin number format depe
179. re built around ARM9TDMI or ARMO9E including ARM9EJS integer processors Such cores include the ARM920T ARM926EJ S and ARM966 arm9 vector catch all none Iist Command Vector Catch hardware provides a sort of dedicated breakpoint for hardware events such as reset interrupt and abort You can use this to conserve normal breakpoint Chapter 16 Architecture and Core Commands 94 resources so long as you re not concerned with code that branches directly to those hardware vectors This always finishes by listing the current configuration If parameters are provided it first reconfigures the vector catch hardware to intercept all of the hardware vectors none of them or a list with one or more of the following reset undef swi pabt dabt irq fiq 16 3 4 ARM920T specific commands These commands are available to ARM920T based CPUs which are implementations of the ARMv4T architecture built using the ARM9TDMI integer core They are available in addition to the ARM ARM7 ARM9 and ARM9 commands arm920t cache_info Command Print information about the caches found This allows to see whether your target is an ARM920T 2x16kByte cache or ARM922T 2x8kByte cache arm920t cp15 regnum value Command Display cp15 register regnum else if a value is provided that value is written to that register This uses physical access and the register number is as shown in bits 38 33 of tab
180. remote server i e OpenOCD to GDB Typical information includes packet size and the device s memory map You do not need to configure the packet size by hand and the relevant parts of the memory map should be automatically set up when you declare NOR flash banks However there are other things which GDB can t currently query You may need to set those up by hand As OpenOCD starts up you will often see a line reporting something like Info lm3s cpu hardware has 6 breakpoints 4 watchpoints You can pass that information to GDB with these commands set remote hardware breakpoint limit 6 set remote hardware watchpoint limit 4 With that particular hardware Cortex M3 the hardware breakpoints only work for code running from flash memory Most other ARM systems do not have such restrictions Another example of useful GDB configuration came from a user who found that single stepping his Cortex M3 didn t work well with IRQs and an RTOS until he told GDB to disable the IRQs while stepping define hook step mon cortex m3 maskisr on end define hookpost step mon cortex m3 maskisr off end Rather than typing such commands interactively you may prefer to save them in a file and have GDB execute them as it starts perhaps using a gdbinit in your project directory or starting GDB using gdb x filename 20 4 Programming using GDB By default the target memory map is sent to GDB This can be disabled by the following OpenOCD c
181. revent the underlying driver from applying hardware ECC e oob_softecc_kw File has only page data which is written The OOB area is filled with Oxff except for a 4 bit software ECC specific to the boot ROM in Marvell Kirkwood SoCs You might need to force raw access to use this mode to prevent the underlying driver from applying hardware ECC nand verify num filename offset option Command Verify the binary data in the file has been programmed to the specified NAND device starting at the specified offset The num parameter is the value shown by nand list Use a complete path name for filename so you don t depend on the directory used to start the OpenOCD server The offset must be an exact multiple of the device s page size All data in the file will be read and compared to the contents of the flash assuming it doesn t run past the end of the device As with nand write only full pages are verified so any extra space in the last page will be filled with Oxff bytes The same options accepted by nand write and the file will be processed similarly to produce the buffers that can be compared against the contents produced from nand dump NOTE This will not work when the underlying NAND controller driver s write page routine must update the OOB with a hardward computed ECC before the data is written This limitation may be removed in a future release 13 3 Other NAND commands nand check bad blocks num offset length Command
182. rs should be detected by asking the ETM for them ETM trigger events could also implement a kind of complex hardware break point much more powerful than the simple watchpoint hardware exported by EmbeddedICE modules Such breakpoints can be triggered even when using the dummy trace port driver It seems like a GDB hookup should be possible as well as tracing only during specific states perhaps handling IRQ 23 or calls foo There should be GUI tools to manipulate saved trace data and help analyse it in conjunction with the source code It s unclear how much of a common interface is shared with the current XScale trace support or should be shared with eventual Nexus style trace module support At this writing November 2009 only ARM7 ARM9 and ARM11 support for ETM modules is available The code should be able to work with some newer cores but not all of them support this original style of JTAG access 16 1 1 ETM Configuration ETM setup is coupled with the trace port driver configuration etm config target width mode clocking driver Config Command Declares the ETM associated with target and associates it with a given trace port driver See Trace Port Drivers page 90 Chapter 16 Architecture and Core Commands 89 Several of the parameters must reflect the trace port capabilities which are a func tion of silicon capabilties exposed later using etm info and of what hardware is connected to that port such as an external pod
183. rs of the Document well before redistributing any large number of copies to give them a chance to provide you with an updated version of the Document 4 MODIFICATIONS You may copy and distribute a Modified Version of the Document under the conditions of sections 2 and 3 above provided that you release the Modified Version under precisely this License with the Modified Version filling the role of the Document thus licensing distribution and modification of the Modified Version to whoever possesses a copy of it In addition you must do these things in the Modified Version A Use in the Title Page and on the covers if any a title distinct from that of the Document and from those of previous versions which should if there were any be listed in the History section of the Document You may use the same title as a previous version if the original publisher of that version gives permission Appendix A The GNU Free Documentation License 126 N O List on the Title Page as authors one or more persons or entities responsible for authorship of the modifications in the Modified Version together with at least five of the principal authors of the Document all of its principal authors if it has fewer than five unless they release you from this requirement State on the Title page the name of the publisher of the Modified Version as the publisher Preserve all the copyright notices of the Document Add an appropriate copyrigh
184. rtly after August 2010 including this command Iterate target using target names not by counting Returns the number of targets N The highest numbered target is N 1 set c target count for set x 0 x lt c incr x Assuming you have created this function print_target_details x l target current Command Returns the name of the current target target names Command Lists the names of all current targets in the list foreach t target names puts format Target s n t A Chapter 11 CPU Configuration 53 target number number Command Note target numbers are deprecated don t use them They will be removed shortly after August 2010 including this command The list of targets is numbered starting at zero This command returns the name of the target at index number set thename target number x puts format Target d is s n x thename targets name Command Note the name of this command is plural Other target command names are singular With no parameter this command displays a table of all known targets in a user friendly form With a parameter this command sets the current target to the given target with the given name this is only relevant on boards which have more than one target 11 2 Target CPU Types and Variants Each target has a CPU type as shown in the output of the targets command You need to specify that type when calling target create The CPU type indicates mor
185. s IEEE IIR A ERU HS Roe eee a 10 4 1 Simple setup no customization 0 cece eee eee ees 10 4 2 What OpenOCD does as it starte 11 5 OpenOCD Project Setup 12 5 1 Hooking up the JTAG Adapter renerne 12 5 2 Project Directory eg eere pr cea eE REA E Heri 13 5 3 Configuration Baies 13 5 4 User Config les 13 5 5 Project Specific Utilities 0 0 15 5 6 Target Software Change 16 5 7 Target Hardware Setup Lf 6 Config File Guidelines 19 6 1 Interface Config les 21 6 2 Board Config Piles 12e KEE ener 21 6 2 1 Communication Between Config Des 21 6 2 2 Variable Naming Convention 22 6 2 3 The reset init Event Handler 23 6 2 4 JTAG Clock Rate 23 6 3 Target Config les 24 6 3 1 Default Value Boiler Plate Code 24 6 3 2 Adding TAPs to the Scan Oham 000s cece eee 25 6 3 3 Add CPU targets 0 0 c cece eee ee eee eee 25 6 3 4 Define CPU targets working in SMP 26 6 3 5 Chip Reset Getup cece eee cece eee eee eee 27 6 3 6 ARM Core Specific Hack 27 6 3 7 Internal Flash Configuration 000 e eee eee 27 6 4 Translating Configuration Hie 28 7 Daemon Configuration 29 7 1 Configuration Btage 6 cece eee eee eee eens 29 7 2 Entering the Run Stage 0 0 eee eee eee ees 29 73 TOP IP POme ce tetee ceca teen teat abel stdin eed eae ees 30 7 4 GDB Configuration 0 0 eem 30 To Event Polling oec va wide
186. s SEES 76 nand EE ge EIER EES DE ETATE Re Ek EE 78 nand list ENEE 76 nand probe ene bn RR Ger pi gece 76 NANG raw acCce8Ss jb vd Med eased bare wu 79 Nand Verity EE 78 Nand Wrlt6 iiI 9 ueber by sorta tues Ti O e DEENEN 69 ocd traco acne Sed aha edaccwe PRINS 91 oocd trace config cece 91 oocd trace FeSyhC seve e e er riris PER Rd 91 oocd trace status 91 he 80 P parport zi eceeeke ep ead acess ede bec stes 36 parport cable be b eret eeu 37 Par port port c x ARIS LE Sees 34 36 37 parport toggling time 37 parport write on elt 38 pathmove 2 3e gae sbRe3 Rr Ra genic s 102 peek ol Re a EELER 85 UE eege baa Ce Bees 69 pic32mx pgm wOIQd o2 sed rE ROEDER 69 pic32mx Unlock Lilo d epe rida epe 69 Pld device xene ner rp beet benRPT Ex e 81 Pld devices bie press SE 81 pid Tea ierg E E d 81 poc Pr 85 LEE 32 pOWOr zsinessis e a Re Sadia deanna RE EE REP 38 presto i exa eet br UPEERECSPIVR REG 38 presto Serial tb E Er ade dna A 38 Profile css sees Madan arog a Pete bed 87 R PDP it vera M M 87 IepgcolibesebbRU ash Enea eee t EEE 83 EES EE 84 reset halt c2lxl erase APR EY a x aie 84 reset init sid wcesae a n e Oa a ER 84 peset IUH ces kei eg RE Rau eva es 84 reset config ocbellcegcue dude hii gs 43 EE 84 EE 38 EEN 85 gud EE 34 EELER teste Gerd pne 102 PWD EE 87 134 S S3c2410 v ole ue E violates wae pan Re ERIT 80 S362412 EE 80 S3C2
187. s UREESU RIED 87 Programming using GDB 107 R EES 83 Reset Configuration 0 0000 41 reset init handler 0 cece eee eee 23 EE 5 40 112 Scan chain seed EE remos RARE 46 SQCULILY seu E ee cede nicum AER ehe 30 Serial Peripheral Interface 39 Serial Vector Format 104 Serial Wire Debug snusnusrenrrrrrrrre 39 SETVE cotre REDUCE RIP DEO T RR EP SUE Pars 30 e WEE 64 ME e er RRPITEEIEREUPPSPRPP PEE ed 26 108 DPI e Em 39 STMicroelectronics Serial Memory Interface 64 GELEET RTT 64 jnaq IER 72 DM LL RV on requ bak earige Ie E PERI E PET 104 131 nip 39 T TRAP 1 TAP configuration leen 46 TAP declaration 0c ce eee eee eee 46 TAP events a ae SE eier TEE 49 TAP naming convention AT TAP state namen 103 target config ble cessere Ree EN 24 target EVENS lt i oc bees e usen bert dba 58 target initialization 008 83 Larget TEE 53 target current ell eee rm dere Eg 52 targets ER 52 p P 9 ek tute dE perieefem 117 Tcl Scripting AT 110 Tol script Sic ciere RERO EPIS RI ES 110 TOP port 2e Re umi E be beta d 30 CR NEE 105 AT ACMI eo QUod c ceres pide odes eu eden 88 99 translatlOB resi 3e beROret qu RE D 28 TESHSDOEU c ooi ripe Peg unes pibus 39 U USB Adanter eee eee 5 User Config fil lel ee RE 13 V variable names seesseseeeeee eese 22 vector catch
188. s the Olimex ARM JTAG wiggler2 Same as original wiggler except an led is fitted on D5 wiggler ntrst inverted Same as original wiggler except T RST is inverted parport port port number Config Command Display either the address of the I O port default 0x378 for LPT1 or the number of the dev parport device If a parameter is provided first switch to use that port This is a write once setting When using PPDEV to access the parallel port use the number of the parallel port parport_port 0 the default If parport port 0x378 is specified you may encounter a problem parport toggling time nanoseconds Command Displays how many nanoseconds the hardware needs to toggle T CK the parport driver uses this value to obey the adapter khz configuration When the op tional nanoseconds parameter is given that setting is changed before displaying the current value The default setting should work reasonably well on commodity PC hardware However you may want to calibrate for your specific hardware Tip To measure the toggling time with a logic analyzer or a digital storage oscilloscope follow the procedure below gt parport toggling time 1000 gt adapter khz 500 This sets the maximum JTAG clock speed of the hardware but the actual speed probably deviates from the requested 500 kHz Now Chapter 8 Debug Adapter Configuration 38 measure the time between the two closest spaced TCK transitions You can use r
189. se 124 under this License If a section does not fit the above definition of Secondary then it is not allowed to be designated as Invariant The Document may contain zero Invariant Sections If the Document does not identify any Invariant Sections then there are none The Cover Texts are certain short passages of text that are listed as Front Cover Texts or Back Cover Texts in the notice that says that the Document is released under this License A Front Cover Text may be at most 5 words and a Back Cover Text may be at most 25 words A Transparent copy of the Document means a machine readable copy represented in format whose specification is available to the general public that is suitable for revising the document straightforwardly with generic text editors or for images com posed of pixels generic paint programs or for drawings some widely available drawing editor and that is suitable for input to text formatters or for automatic translation to a variety of formats suitable for input to text formatters copy made in an otherwise Transparent file format whose markup or absence of markup has been arranged to thwart or discourage subsequent modification by readers is not Transparent An image format is not Transparent if used for any substantial amount of text A copy that is not Transparent is called Opaque Examples of suitable formats for Transparent copies include plain ASCII without markup Texinfo input
190. sed in SVF boundary scan documents except that SVF uses IDLE instead of RUN IDLE e RESET stable with TMS high acts as if TRST were pulsed e RUN IDLE stable don t assume this always means IDLE e DRSELECT e DRCAPTURE e DRSHIFT stable TDI TDO shifting through the data register e DREXIT1 e DRPAUSE stable data register ready for update or more shifting e DREXIT2 e DRUPDATE e IRSELECT e IRCAPTURE e IRSHIFT stable TDI TDO shifting through the instruction register e IREXITI e IRPAUSE stable instruction register ready for update or more shifting e IREXIT2 e IRUPDATE Note that only six of those states are fully stable in the face of TMS fixed low except for RESET and a free running JTAG clock For all the others the next TCK transition changes to a new state e From DRSHIFT and IRSHIFT clock transitions will produce side effects by changing register contents The values to be latched in upcoming DRUPDATE or IRUPDATE states may not be as expected e RUN IDLE DRPAUSE and IRPAUSE are reasonable choices after drscan or irscan com mands since they are free of JTAG side effects e RUN IDLE may have side effects that appear at non JTAG levels such as advancing the ARMO9E S instruction pipeline Consult the documentation for the TAP s you are working with Chapter 18 Boundary Scan Commands 104 18 Boundary Scan Commands One of the original purposes of J TAG was to support boundary scan based hardware te
191. sh Driver All members of the AT91SAM3 microcontroller family from Atmel include internal flash and use ARM s Cortex M3 core The driver currently 6 22 09 recognizes the AT91SAMS3U 1 2 4 C E chips Note that the driver was orginaly developed and tested using the AT91SAM3U4E using a SAM3U EK eval board Support for other chips in the family was cribbed from the data sheet Note to future readers updaters Please remove this worrysome comment after other chips are confirmed The AT91SAM3U4 E C 256K chips have two flash banks most other chips have one flash bank In all cases the flash banks are at the following fixed locations Flash bank O all chips flash bank FLASHNAME at91sam3 0x00080000 O 1 1 TARGETNAME Flash bank 1 only 256K chips flash bank FLASHNAME at91sam3 0x00100000 O 1 1 TARGETNAME Internally the AT91SAMS3 flash memory is organized as follows Unlike the AT91SAM7 chips these are not used as parameters to the flash bank command e N Banks 256K chips have 2 banks others have 1 bank e Bank Size 128K 64K Per flash bank e Sectors 16 or 8 per bank e SectorSize 8K Per Sector e PageSize 256 bytes per page Note that OpenOCD operates on sector sizes not page sizes The AT91SAM3 driver adds some additional commands at91sam3 gpnvm Command at91sam3 gpnvm clear number Command Chapter 12 Flash Commands 66 at91sam3 gpnvm set number Command at91sam3 gpnvm show al1 number Command
192. sing the target name cget command Warning changing some of these after setup is dangerous For example moving a target from one TAP to another and changing its endianness or variant e chain position dotted name names the TAP used to access this target e endian big little specifies whether the CPU uses big or little endian conventions e event event name event body See Target Events page 57 Note that this updates a list of named event handlers Calling this twice with two different event names assigns two different handlers but calling it twice with the same event name assigns only one handler e variant name specifies a variant of the target which OpenOCD needs to know about e work area backup 0 1 says whether the work area gets backed up by default it is not backed up When possible use a working_area that doesn t need to be backed up since performing a backup slows down operations For example the beginning of an SRAM block is likely to be used by most build systems but the end is often unused e work area size size specify work are size in bytes The same size applies regardless of whether its physical or virtual address is being used Chapter 11 CPU Configuration 56 e work area phys address set the work area base address to be used when no MMU is active e work area virt address set the work area base address to be used when an MMU is active Do
193. specific utility routines may well speed up your work Write them and keep them in your project s user config file For example if you are making a boot loader work on a board it s nice to be able to debug the after it s loaded to RAM parts separately from the finicky early code which sets up the DDR RAM controller and clocks A script like this one or a more GDB aware sibling may help proc ramboot Reset running the target s reset init scripts to initialize clocks and the DDR RAM controller Leave the CPU halted reset init Load CONFIG_SKIP_LOWLEVEL_INIT version into DDR RAM load_image u boot bin 0x20000000 Start running resume 0x20000000 Then once that code is working you will need to make it boot from NOR flash a different utility would help Alternatively some developers write to flash using GDB You might use a similar script if you re working with a flash based microcontroller application instead of a boot loader proc newboot 1 Reset leaving the CPU halted The reset init event proc gives faster access to the CPU and to NOR flash reset halt would be slower reset init Write standard version of U Boot into the first two sectors of NOR flash the standard version should 4 do the same lowlevel init as reset init Chapter 5 OpenOCD Project Setup 16 flash protect O O 1 off flash erase sector 0 0 1 flash write bank O u boot bin OxO flash protect O O 1
194. starts by issuing a JTAG only reset Then it performs checks to verify that the scan chain configuration matches the TAPs it can observe Those checks include checking IDCODE values for each active TAP and verifying the length of their instruction registers using TAP ircapture and irmask values If these tests all pass TAP setup events are issued to all TAPs with handlers for that event jtag arp init reset Command This uses TRST and SRST to try resetting everything on the JTAG scan chain and anything else connected to SRST It then invokes the logic of jtag arp_init Chapter 10 TAP Declaration 46 10 TAP Declaration Test Access Ports TAPs are the core of JTAG TAPs serve many roles including e Debug Target A CPU TAP can be used as a GDB debug target e Flash Programing Some chips program the flash directly via J AG Others do it indi rectly making a CPU do it e Program Download Using the same CPU support GDB uses you can initialize a DRAM controller download code to DRAM and then start running that code e Boundary Scan Most chips support boundary scan which helps test for board assembly problems like solder bridges and missing connections OpenOCD must know about the active TAPs on your board s Setting up the TAPs is the core task of your configuration files Once those TAPs are set up you can pass their names to code which sets up CPUs and exports them as GDB targets probes flash memory performs low level J TAG op
195. sting Although its primary focus is to support On Chip Debugging OpenOCD also includes some boundary scan commands 18 1 SVF Serial Vector Format The Serial Vector Format better known as SVF is a way to represent JTAG test patterns in text files In a debug session using J TAG for its transport protocol OpenOCD supports running such test files svf filename quiet Command This issues a JTAG reset Test Logic Reset and then runs the SVF script from filename Unless the quiet option is specified each command is logged before it is executed 18 2 XSVF Xilinx Serial Vector Format The Xilinx Serial Vector Format better known as XSVF is a binary representation of SVF which is optimized for use with Xilinx devices In a debug session using JTAG for its transport protocol OpenOCD supports running such test files Important Not all XSVF commands are supported xsvf tapname plain filename virt2 quiet Command This issues a JTAG reset Test Logic Reset and then runs the XSVF script from filename When a tapname is specified the commands are directed at that TAP When virt2 is specified the XRUNTEST command counts are interpreted as TCK cycles instead of microseconds Unless the quiet option is specified messages are logged for comments and some retries The OpenOCD sources also include two utility scripts for working with XSVF they are not currently installed after building the softw
196. t CPUs have specialized J TAG operations to support debugging OpenOCD packages most such operations in its standard command framework Some of those operations don t fit well in that framework so they are exposed here as architecture or implementation core specific commands 16 1 ARM Hardware Tracing CPUs based on ARM cores may include standard tracing interfaces based on an Embedded Trace Module ETM which sends voluminous address and data bus trace records to a Trace Port e Development oriented boards will sometimes provide a high speed trace connector for collecting that data when the particular CPU supports such an interface The stan dard connector is a 38 pin Mictor with both JTAG and trace port support Those trace connectors are supported by higher end JTAG adapters and some logic analyzer modules frequently those modules can buffer several megabytes of trace data Con figuring an ETM coupled to such an external trace port belongs in the board specific configuration file e Ifthe CPU doesn t provide an external interface it probably has an Embedded Trace Buffer ETB on the chip which is a dedicated SRAM 4KBytes is one common ETB size Configuring an ETM coupled only to an ETB belongs in the CPU specific target configuration file since it works the same on all boards ETM support in OpenOCD doesn t seem to be widely used yet Issues ETM support may be buggy and at least some etm config paramete
197. t notice for your modifications adjacent to the other copyright notices Include immediately after the copyright notices a license notice giving the public permission to use the Modified Version under the terms of this License in the form shown in the Addendum below Preserve in that license notice the full lists of Invariant Sections and required Cover Texts given in the Document s license notice Include an unaltered copy of this License Preserve the section Entitled History Preserve its Title and add to it an item stating at least the title year new authors and publisher of the Modified Version as given on the Title Page If there is no section Entitled History in the Docu ment create one stating the title year authors and publisher of the Document as given on its Title Page then add an item describing the Modified Version as stated in the previous sentence Preserve the network location if any given in the Document for public access to a Transparent copy of the Document and likewise the network locations given in the Document for previous versions it was based on These may be placed in the History section You may omit a network location for a work that was published at least four years before the Document itself or if the original publisher of the version it refers to gives permission For any section Entitled Acknowledgements or Dedications Preserve the Title of the section and preserve in
198. te commands This includes nand probe jtag_init Overridable Procedure This is invoked at server startup to verify that it can talk to the scan chain list of TAPs which has been configured Chapter 7 Daemon Configuration 30 The default implementation first tries jtag arp init which uses only a lightweight JTAG reset before examining the scan chain If that fails it tries again using a harder reset from the overridable procedure init reset Implementations must have verified the J TAG scan chain before they return This is done by calling jtag arp init or jtag arp init reset 7 3 TCP IP Ports The OpenOCD server accepts remote commands in several syntaxes Each syntax uses a different TCP IP port which you may specify only during configuration before those ports are opened For reasons including security you may wish to prevent remote access using one or more of these ports In such cases just specify the relevant port number as zero If you disable all access through TCP IP you will need to use the command line pipe option gdb port number Command Normally gdb listens to a TCP IP port but GDB can also communicate via pipes stdin out or named pipes The name gdb_port stuck because it covers probably more than 9096 of the normal use cases No arguments reports GDB port pipe means listen to stdin output to stdout an integer is base port number disable disables the gdb server When using pipe a
199. the chip and bus width to be specified flash bank FLASHNAME lpc288x O O O O TARGETNAME 12000000 1pc2900 Flash Driver This driver supports the LPC29xx ARM968E based microcontroller family from NXP The predefined parameters base size chip width and bus width of the flash bank command are ignored Flash size and sector layout are auto configured by the driver Chapter 12 Flash Commands 68 The driver has one additional mandatory parameter The CPU clock rate in kHz at the time the flash operations will take place Most of the time this will not be the crystal frequency but a higher PLL frequency The reset init event handler in the board script is usually the place where you start the PLL The driver rejects flashless devices currently the LPC2930 The EEPROM in LPC2900 devices is not mapped directly into the address space It must be handled much more like NAND flash memory and will therefore be handled by a separate 1pc2900_eeprom driver not yet available Sector protection in terms of the LPC2900 is handled transparently Every time a sector needs to be erased or programmed it is automatically unprotected What is shown as protection status in the flash info command is actually the LPC2900 sector security This is a mechanism to prevent a sector from ever being erased or programmed again As this is an irreversible mechanism it is handled by a spe cial command 1pc2900 secure sector and not by the standard flash prot
200. the section all the substance and tone of each of the contributor acknowledgements and or dedications given therein Preserve all the Invariant Sections of the Document unaltered in their text and in their titles Section numbers or the equivalent are not considered part of the section titles Delete any section Entitled Endorsements Such a section may not be included in the Modified Version Do not retitle any existing section to be Entitled Endorsements or to conflict in title with any Invariant Section Preserve any Warranty Disclaimers If the Modified Version includes new front matter sections or appendices that qualify as Secondary Sections and contain no material copied from the Document you may at your option designate some or all of these sections as invariant To do this add their titles to the list of Invariant Sections in the Modified Version s license notice These titles must be distinct from any other section titles Appendix A The GNU Free Documentation License 127 You may add a section Entitled Endorsements provided it contains nothing but endorsements of your Modified Version by various parties for example statements of peer review or that the text has been approved by an organization as the authoritative definition of a standard You may add a passage of up to five words as a Front Cover Text and a passage of up to 25 words as a Back Cover Text to the end of the list of Cover Texts in the Modifi
201. the target board It is also the natural place to write files such as log files and data you download from the board 5 3 Configuration Basics There are two basic ways of configuring OpenOCD and a variety of ways you can mix them Think of the difference as just being how you start the server e Many f file or c command options on the command line e No options but a user config file in the current directory named openocd cfg Here is an example openocd cfg file for a setup using a Signalyzer FT2232 based JTAG adapter to talk to a board with an Atmel AT91SAM7X256 microcontroller source find interface signalyzer cfg GDB can also flash my flash gdb_memory_map enable gdb_flash_program enable source find target sam7x256 cfg Here is the command line equivalent of that configuration openocd f interface signalyzer cfg c gdb memory map enable c gdb flash program enable f target sam7x256 cfg You could wrap such long command lines in shell scripts each supporting a different devel opment task One might re flash the board with a specific firmware version Another might set up a particular debugging or run time environment Important At this writing October 2009 the command line method has prob lems with how it treats variables For example after c set VAR value or doing the same in a script the variable VAR will have no value that can be tested in a later script Here we will focus on t
202. this really matter For some chips and some situations this is a non issue like a 500MHz ARM926 with a 5 MHz JTAG link the CPU has no difficulty keeping up with JTAG Startup sequences are often problematic though as are other situations where the CPU clock rate changes perhaps to save power For example Atmel AT91SAM chips start operation from reset with a 32kHz system clock Boot firmware may activate the main oscillator and PLL before switching to a faster clock perhaps that 500 MHz ARM926 scenario If you re using JTAG to debug that startup sequence you must slow the JTAG clock to sometimes 1 to 4kHz After startup completes JTAG can use a faster clock Consider also debugging a 500MHz ARM926 hand held battery powered device that enters a low power deep sleep mode at 32kHz CPU clock between keystrokes unless it has work to do When would that 5 MHz JTAG clock be usable Solution 1 A special circuit In order to make use of this your CPU board and JTAG adapter must all support the RTCK feature Not all of them support this keep reading The RTCK Return TCK signal in some ARM chips is used to help with this problem ARM has a good description of the problem described at this link http www arm com support fagdev 4170 html checked 28 nov 2008 Link title How does the JTAG synchronisation logic work how does adaptive clocking work The nice thing about adaptive clocking is that battery powered hand h
203. tm32_h103 cfg omap2420_h4 cfg osk5912 cfg pic p32mx cfg propox_mmnet1001 cfg pxa255_sst cfg sheevaplug cfg Chapter 6 Config File Guidelines ek 1m3s811 cfg ek 1m3s9b9x cfg hammer cfg hitex_lpc2929 cfg hitex_stm32 performancestick cfg hitex_str9 comstick cfg iar str912 sk cfg imx27ads cfg imx27l1nst cfg imx3ipdk cfg e target 20 stm3210e_eval cfg stm32f10x_128k_eval cfg str910 eval cfg telo cfg ti_beagleboard cfg topas910 cfg topasa900 cfg unknown_at91sam9260 cfg x300t cfg zy1000 cfg think chip The target directory represents the JTAG TAPs on a chip which OpenOCD should control not a board Two common types of targets are ARM chips and FPGA or CPLD chips When a chip has multiple TAPs maybe it has both ARM and DSP cores the target config file defines all of them 1s target aduc 702x cfg arlixx cfg at91eb40a cfg at91r40008 cfg at91rm9200 cfg atQlsam3ulc cfg atQlsam3ule cfg at91sam3u2c cfg at91sam3u2e cfg atQlsam3u4c cfg atQlsam3u4e cfg atQlsam3uXX cfg at91sam7sx cfg at91sam9260 cfg c100 cfg c100config tcl ciO0helper tcl c100regs tcl cs351x cfg davinci cfg dragonite cfg epc9301 cfg feroceon cfg icepick cfg imx21 cfg e ore imx27 cfg imx31 cfg imx35 cfg is5b114 cfg ixp42x cfg 1m3s1968 cfg 1m3s3748 cfg 1m3s6965 cfg 1m3s811 cfg l1m3s9b9x cfg lpci768 cfg lpc2103 cfg lpc2124 cfg lpc2129 cfg lpc2148 cfg lpc2294 cfg lpc2378 cfg lpc2478 cfg lpc2900 cf
204. tor numbers and don t depend on searching the current target and its address space Avoid confusing the two command models Some flash chips implement software protection against accidental writes since such buggy writes could in some cases brick a system For such systems erasing and writing may require sector protection to be disabled first Examples include CFI flash such as Intel Advanced Bootblock flash and AT91SAMT on chip flash See flash protect page 64 flash erase sector num first last Command Erase sectors in bank num starting at sector first up to and including last Sector numbering starts at 0 Providing a last sector of last specifies to the end of the flash bank The num parameter is a value shown by flash banks Chapter 12 Flash Commands 63 flash erase address pad unlock address length Command Erase sectors starting at address for length bytes Unless pad is specified address must begin a flash sector and address length 1 must end a sector Specifying pad erases extra data at the beginning and or end of the specified region as needed to erase only full sectors The flash bank to use is inferred from the address and the specified length must stay within that bank As a special case when length is zero and address is the start of the bank the whole flash is erased If unlock is specified then the flash is unprotected before erase starts flash fillw address word len
205. tring just like C Execute the start statement Execute_AsciiString interp argv 1 Top of loop test for i Evaluate_AsciiExpression interp argv 2 if i 0 break Execute the body Execute_AsciiString interp argv 3 Execute the LOOP part Execute AsciiString interp argv 4 Return no error SetResult interp return SUCCESS Every other command IF WHILE FORMAT PUTS EXPR everything works in the same basic way 23 6 OpenOCD Tcl Usage 23 6 1 source and find commands Where In many configuration files Example source find FILENAME Remember the parsing rules 1 The find command is in square brackets and is executed with the parameter FILE Chapter 23 Tcl Crash Course 121 NAME It should find and return the full path to a file with that name it uses an internal search path The RESULT is a string which is substituted into the command line in place of the bracketed find command Don t try to use a FILENAME which includes the character That character begins Tcl comments The source command is executed with the resulting filename it reads a file and exe cutes as a script 23 6 2 format command Where Generally occurs in numerous places Tcl has no command like printf instead it has format which is really more like sprintf Example set x 6 set y 7 puts format The answer d expr x y 1 The SET command creates 2 variables X and Y
206. ts use of those methods bypassing hardware ECC logic This can be a dangerous option since writing blocks with the wrong ECC data can cause them to be marked as bad 13 4 NAND Driver List As noted above the nand device command allows driver specific options and behaviors Some controllers also activate controller specific commands at91sam9 NAND Driver This driver handles the NAND controllers found on AT91SAM9 family chips from Atmel It takes two extra parameters address of the NAND chip address of the ECC controller nand device NANDFLASH at91sam9 CHIPNAME 0x40000000 Oxfffffe800 AT91SAM9 chips support single bit ECC hardware The write page and read page methods are used to utilize the ECC hardware unless they are disabled by using the nand raw access command There are four additional commands that are needed to fully configure the AT91SAM9 NAND controller Two are optional most boards use the same wiring for ALE CLE at91sam9 cle num addr line Command Configure the address line used for latching commands The num parameter is the value shown by nand list at91sam9 ale num addr line Command Configure the address line used for latching addresses The num parameter is the value shown by nand list For the next two commands it is assumed that the pins have already been properly configured for input or output at91sam9 rd busy num pio_base_addr pin Command Configure the RDY nBUSY input from the NAND device The num
207. und Once you understand Rule 1 you will understand Tcl 23 2 Tcl Rule 1b There is a second pair of rules 1 Rule 1 Control flow does not exist Only commands For example the classic FOR loop or IF statement is not a control flow item they are commands there is no such thing as control flow in Tcl 2 Rule 2 If you think otherwise See Rule 1 Actually what happens is this There are commands that by convention act like control flow key words in other languages One of those commands is the word for another command is if 23 3 Per Rule 771 All Results are strings Every Tcl command results in a string The word result is used deliberatly No result is just an empty string Remember Rule 1 Everything is a string 23 4 Tcl Quoting Operators In life of a Tcl script there are two important periods of time the difference is subtle 1 Parse Time 2 Evaluation Time The two key items here are how quoted things work in Tcl Tcl has three primary quoting constructs the square brackets the curly braces and double quotes By now you should know VARIABLES always start with a DOLLAR sign BTW To set a variable you actually use the command set as in set VARNAME VALUE much like the ancient BASIC langauge let x 1 statement but without the equal sign Chapter 23 Tcl Crash Course 118 e square brackets square brackets are command substitutions It operates much like Unix
208. unplug power to the board It s important to have the ground signal properly set up unless you are using a JTAG adapter which provides galvanic isolation between the target board and the debugging host 2 Be sure it s the right kind of JTAG connector If your dongle has a 20 pin ARM connector you need some kind of adapter or octopus see below to hook it up to boards using 14 pin or 10 pin connectors or to 20 pin connectors which don t use ARM s pinout In the same vein make sure the voltage levels are compatible Not all JTAG adapters have the level shifters needed to work with 1 2 Volt boards 3 Be certain the cable is properly oriented or you might damage your board In most cases there are only two possible ways to connect the cable Connect the JTAG cable from your adapter to the board Be sure it s firmly connected In the best case the connector is keyed to physically prevent you from inserting it wrong This is most often done using a slot on the board s male connector housing which must match a key on the JTAG cable s female connector If there s no housing then you must look carefully and make sure pin 1 on the cable hooks up to pin 1 on the board Ribbon cables are frequently all grey except for a wire on one edge which is red The red wire is pin 1 Sometimes dongles provide cables where one end is an octopus of color coded single wire connectors instead of a connector block These are great when con
209. untest 1000 or something similar to generate a large set of samples Update the setting to match your measurement gt parport toggling time measured nanoseconds gt Now the clock speed will be a better match for adapter khz rate commands given in OpenOCD scripts and event handlers You can do something similar with many digital multimeters but note that you ll probably need to run the clock continuously for several seconds before it decides what clock rate to show Adjust the toggling time up or down until the measured clock rate is a good match for the adapter khz rate you specified be conservative parport write on exit on off Config Command This will configure the parallel driver to write a known cable specific value to the parallel interface on exiting OpenOCD For example the interface configuration file for a classic Wiggler cable on LPT2 might look something like this interface parport parport port 0x278 parport cable wiggler presto Interface Driver ASIX PRESTO USB JTAG programmer presto serial serial string Config Command Configures the USB serial number of the Presto device to use rlink Interface Driver Raisonance RLink USB adapter usbprog Interface Driver usbprog is a freely programmable USB adapter vsllink Interface Driver vsllink is part of Versaloon which is a versatile USB programmer Note This defines quite a few driver specific commands which are not currently docume
210. up add the TAPs on each chip to the JTAG scan chain See Chapter 10 TAP Declaration page 46 and the naming convention for taps In the simplest case the chip has only one TAP probably for a CPU or FPGA The config file for the Atmel AT91SAM7X256 looks in part like this jtag newtap CHIPNAME cpu irlen 4 expected id CPUTAPID A board with two such at91sam7 chips would be able to source such a config file twice with different values for CHIPNAME so it adds a different TAP each time If there are nonzero expected id values OpenOCD attempts to verify the actual tap id against those values It will issue error messages if there is mismatch which can help to pinpoint problems in OpenOCD configurations JTAG tap sam7x256 cpu tap device found Ox3fOfOfOf Manufacturer 0x787 Part OxfOf0O Version 0x3 ERROR Tap sam7x256 cpu Expected id 0x12345678 Got Ox3fOfOfOf ERROR expected mfg Ox33c part Ox2345 ver Oxi ERROR got mfg 0x787 part OxfOf0O ver 0x3 There are more complex examples too with chips that have multiple TAPs Ones worth looking at include e target omap3530 cfg with disabled ARM and DSP plus a JRC to enable them e target str912 cfg with flash CPU and boundary scan e target ti_dm355 cfg with ETM ARM and JRC this JRC is not currently used 6 3 3 Add CPU targets After adding a TAP for a CPU you should set it up so that GDB and other commands can use it See Chapter 11
211. validated e type describing how data accesses are traced when they pass any ViewData filtering that that was set up The value is one of none save nothing data save data address save addresses all save data and addresses e context id bits 0 8 16 or 32 e cycle_accurate enable or disable cycle accurate instruction tracing Be fore ETMv3 enabling this causes much extra data to be recorded e branch_output enable or disable Disable this unless you need to try reconstructing the instruction trace stream without an image of the code etm trigger debug enable disable Command Displays whether ETM triggering debug entry like a breakpoint is enabled or disabled after optionally modifying that configuration The default behaviour is disable Any change takes effect after the next etm start By using script commands to configure ETM registers you can make the processor en ter debug state automatically when certain conditions more complex than supported by the breakpoint hardware happen Chapter 16 Architecture and Core Commands 90 16 1 2 ETM Trace Operation After setting up the ETM you can use it to collect data That data can be exported to files for later analysis It can also be parsed with OpenOCD for basic sanity checking To configure what is being traced you will need to write various trace registers using reg ETM commands Fo
212. value JTAG reset is triggered with TMS and TCK signals instead of the TRST signal And no matter how that JTAG reset is triggered once the scan chain enters RESET with TRST inactive TAP post reset events are delivered to all TAPs with handlers for that event pathmove start_state next_state Command Start by moving to start_state which must be one of the stable states Unless it is the only state given this will often be the current state so that no TCK transitions are needed Then in a series of single state transitions conforming to the JTAG state machine shift to each next_state in sequence one per TCK cycle The final state must also be stable runtest num_cycles Command Move to the RUN IDLE state and execute at least num cycles of the JTAG clock TCK Instructions often need some time to execute before they take effect verify ircapture enable disable Command Verify values captured during IRCAPTURE and returned during IR scans Default is enabled but this can be overridden by verify_jtag This flag is ignored when validating JTAG chain configuration Chapter 17 JTAG Commands 103 verify jtag enable disable Command Enables verification of DR and IR scans to help detect programming errors For IR scans verify_ircapture must also be enabled Default is enabled 17 2 TAP state names The tap_state names used by OpenOCD in the drscan irscan and pathmove commands are the same as those u
213. vent handling Chapter 7 Daemon Configuration 31 gdb breakpoint override hard soft disable Command Force breakpoint type for gdb break commands This option supports GDB GUIs which don t distinguish hard versus soft breakpoints if the default OpenOCD and GDB behaviour is not sufficient GDB normally uses hardware breakpoints if the memory map has been set up for flash regions gdb_flash_program enable disable Config Command Set to enable to cause OpenOCD to program the flash memory when a vFlash packet is received The default behaviour is enable gdb_memory_map enable disable Config Command Set to enable to cause OpenOCD to send the memory configuration to GDB when requested GDB will then know when to set hardware breakpoints and program flash using the GDB load command gdb_flash_program enable must also be enabled for flash programming to work Default behaviour is enable See Jodi flash program page 31 gdb_report_data_abort enable disable Config Command Specifies whether data aborts cause an error to be reported by GDB memory read packets The default behaviour is disable use enable see these errors reported 7 5 Event Polling Hardware debuggers are parts of asynchronous systems where significant events can happen at any time The OpenOCD server needs to detect some of these events so it can report them to through TCL c
214. ver The PIC32MX microcontrollers are based on the MIPS 4K cores and integrate flash memory flash bank FLASHNAME pix32mx 0x1fc0000 flash bank FLASHNAME pix32mx 0x1d00000 ARGETNAME 0000 _T O 0 0 0 TARGETNAME Some pic32mx specific commands are defined pic32mx pgm_word address value bank Command Programs the specified 32 bit value at the given address in the specified chip bank pic32mx unlock bank Command Unlock and erase specified chip bank This will remove any Code Protection Chapter 12 Flash Commands 70 stellaris Flash Driver All members of the Stellaris LM3Sxxx microcontroller family from Texas Instruments include internal flash and use ARM Cortex M3 cores The driver automatically recog nizes a number of these chips using the chip identification register and autoconfigures itself flash bank FLASHNAME stellaris O O O O TARGETNAME stellaris recover bank id Command Performs the Recovering a Locked Device procedure to restore the flash specified by bank_id and its associated nonvolatile registers to their factory default values erased This is the only way to remove flash protection or re enable debugging if that capability has been disabled Note that the final power cycle the chip step in this procedure must be performed by hand since OpenOCD can t do it Warning if more than one Stellaris chip is connected the procedure is applied to all of them stm32fix Flash Driver All me
215. verting from one JTAG pinout to another but are tedious to set up Use these with connector pinout diagrams to help you match up the adapter signals to the right board pins 4 Connect the adapter s other end once the JTAG cable is connected A USB parallel or serial port connector will go to the host which you are using to run OpenOCD For Ethernet consult the documentation and your network administrator For USB based JTAG adapters you have an easy sanity check at this point does the host operating system see the J TAG adapter If that host is an MS Windows host you ll need to install a driver before OpenOCD works 5 Connect the adapter s power supply if needed This step is primarily for non USB adapters but sometimes USB adapters need extra power 6 Power up the target board Unless you just let the magic smoke escape you re now ready to set up the OpenOCD server so you can use JTAG to work with that board Chapter 5 OpenOCD Project Setup 13 Talk with the OpenOCD server using telnet telnet localhost 4444 on many systems or GDB See Chapter 20 GDB and OpenOCD page 106 5 2 Project Directory There are many ways you can configure OpenOCD and start it up A simple way to organize them all involves keeping a single directory for your work with a given board When you start OpenOCD from that directory it searches there first for configuration files scripts files accessed through semihosting and for code you upload to
216. volves dif ferent electrical signaling and uses different messaging protocols on top of that signaling There are many types of debug adapter and little uniformity in what they are called There are also product naming differences These adapters are sometimes packaged as discrete dongles which may generically be called hardware interface dongles Some development boards also integrate them directly which may let the development board can be directly connected to the debug host over USB and sometimes also to power it over USB For example a JTAG Adapter supports JTAG signaling and is used to communicate with JTAG IEEE 1149 1 compliant TAPs on your target board A TAP is a Test Access Port a module which processes special instructions and data TAPs are daisy chained within and between chips and boards JTAG supports debugging and boundary scan operations There are also SWD Adapters that support Serial Wire Debug SWD signaling to commu nicate with some newer ARM cores as well as debug adapters which support both J TAG and SWD transports SWD only supports debugging whereas JTAG also supports bound ary scan operations For some chips there are also Programming Adapters supporting special transports used only to write code to flash memory without support for on chip debugging or boundary scan At this writing OpenOCD does not support such non debug adapters Dongles OpenOCD currently supports many types of hardware do
217. w power situations you just need to either use a fixed and very slow JTAG clock rate or else manually adjust the clock speed at every step Adjusting is painful and tedious and is not always practical It is however easy to code your way around it i e Cheat a little have a special debug mode in your application that does a high power sleep If you are careful 98 of your problems can be debugged this way Note that on ARM you may need to avoid using the wait for interrupt operation in your idle loops even if you don t otherwise change the CPU clock rate That operation gates the CPU clock and thus the JTAG clock which prevents JTAG access One consequence is not being able to halt cores which are executing that wait for interrupt operation To set the JTAG frequency use the command Example 1 234MHz adapter_khz 1234 2 Win32 Pathnames Why don t backslashes work in Windows paths OpenOCD uses Tcl and a backslash is an escape char Use and around Windows filenames gt echo a gt echo a a gt echo Na gt 3 Missing cygwinl dll OpenOCD complains about a missing cygwinl dll Make sure you have Cygwin installed or at least a version of OpenOCD that claims to come with all the necessary DLLs When using Cygwin try launching OpenOCD from the Cygwin shell 4 Breakpoint Issue I m trying to set a breakpoint using GDB or a frontend like Insight or Eclipse but OpenOCD complains that
218. was introduced to OpenOCD in spring 2008 Fall 2010 before OpenOCD 0 5 release OpenOCD switched to using Jim Tcl as a git submodule which greatly simplified upgrading Jim Tcl to benefit from new features and bugfixes in Jim Tcl Need a crash course in Tcl See Chapter 23 Tcl Crash Course page 117 Chapter 4 Running 10 4 Running Properly installing OpenOCD sets up your operating system to grant it access to the debug adapters On Linux this usually involves installing a file in etc udev rules d so OpenOCD has permissions MS Windows needs complex and confusing driver configuration for every peripheral Such issues are unique to each operating system and are not detailed in this User s Guide Then later you will invoke the OpenOCD server with various options to tell it how each debug session should work The help option shows bash openocd help help h display this help version v display OpenOCD version file f use configuration file name search s dir to search for config files and scripts debug d set debug level lt 0 3 gt log output 1 redirect log output to file name command run lt command gt H If you don t give any f or c options OpenOCD tries to read the configuration file openocd cfg To specify one or more different configuration files use f options For example openocd f configi cfg f config2 cfg f config3 cfg Conf
219. y s NAND chips and multi chip modules commonly hold multiple GigaBytes of data NAND chips consist of a number of erase blocks of a given size such as 128 KBytes each of which is divided into a number of pages of perhaps 512 or 2048 bytes each Each page of a NAND flash has an out of band OOB area to hold Error Correcting Code ECC and other metadata usually 16 bytes of OOB for every 512 bytes of page data One key characteristic of NAND flash is that its error rate is higher than that of NOR flash In normal operation that ECC is used to correct and detect errors However NAND blocks can also wear out and become unusable those blocks are then marked bad NAND chips are even shipped from the manufacturer with a few bad blocks The highest density chips use a technology MLC that wears out more quickly so ECC support is increasingly important as a way to detect blocks that have begun to fail and help to preserve data integrity with techniques such as wear leveling Software is used to manage the ECC Some controllers don t support ECC directly in those cases software ECC is used Other controllers speed up the ECC calculations with hardware Single bit error correction hardware is routine Controllers geared for newer MLC chips may correct 4 or more errors for every 512 bytes of data You will need to make sure that any data you write using OpenOCD includes the app propriate kind of ECC For example that may mean
220. y or via one of several TCP IP Ports e From the human A human should interact with the telnet interface default port 4444 or via GDB default port 3333 To issue commands from within a GDB session use the monitor command e g use monitor poll to issue the poll command All output is relayed through the GDB session e Machine Interface The Tcl interface s intent is to be a machine interface The default Tcl port is 5555 15 1 Daemon Commands exit Command Exits the current telnet session help string Command With no parameters prints help text for all commands Otherwise prints each help text containing string Not every command provides helptext Configuration commands and commands valid at any time are explicitly noted in parenthesis In most cases no such restriction is listed this indicates commands which are only available after the configuration stage has completed sleep msec busy Command Wait for at least msec milliseconds before resuming If busy is passed busy wait instead of sleeping This option is strongly discouraged Useful in connection with script files script command and target_name configuration shutdown Command Close the OpenOCD daemon disconnecting all clients GDB telnet other debug level n Command Display debug level If n from 0 3 is provided then set it to that level This affects the kind of messages sent to the server log Level 0
221. y and can not be overwritten value holds the 32 bit opcode that is placed in the mini IC Without arguments the current settings are displayed 16 4 ARMv6 Architecture 16 4 1 ARM11 specific commands armii memwrite burst enable disable Command Displays the value of the memwrite burst enable flag which is enabled by default If a boolean parameter is provided first assigns that flag Burst writes are only used for memory writes larger than 1 word They improve performance by assuming that the CPU has read each data word over JTAG and completed its write before the next word arrives instead of polling for a status flag to verify that completion This is usually safe because JTAG runs much slower than the CPU armii memwrite error fatal enable disable Command Displays the value of the memwrite error fatal flag which is enabled by default If a boolean parameter is provided first assigns that flag When set certain memory write errors cause earlier transfer termination armii step irq enable enable disable Command Displays the value of the flag controlling whether IRQs are enabled during single stepping they are disabled by default If a boolean parameter is provided first assigns that Chapter 16 Architecture and Core Commands 98 armii vcr value Command Displays the value of the Vector Catch Register VCR coprocessor 14 register 7 If value is defined first assigns that Vector Catch hardw
222. your debugger startup scripts You may however need a different approach when for exam ple a motor could be physically damaged by firmware remaining inactive in a debug halt state That might involve a type of firmware mode where that non counting mode is disabled at the beginning then re enabled at the end a watchdog reset might fire and complicate the debug session but hardware or people would be protected e ARM Semihosting When linked with a special runtime library provided with many toolchains your target code can use I O facilities on the debug host That library provides a small set of system calls which are handled by OpenOCD It can let the debugger provide your system console and a file system helping with early debugging or providing a more capable environment for sometimes complex tasks like installing system firmware onto NAND or SPI flash Note that many systems support a monitor mode debug that is a somewhat cleaner way to address such issues You can think of it as only halting part of the system maybe just one task instead of the whole thing At this writing January 2010 OpenOCD based debugging does not support monitor mode debug only halt mode debug See chapter 8 Semihosting in ARM DUI 02031 the RealView Compilation Tools Developer Guide The CodeSourcery EABI toolchain also includes a semihosting library Chapter 5 OpenOCD Project Setup 17 e ARM Wait For Interrupt Many ARM chips synchroniz

Open On-Chip Debugger: OpenOCD User's Guide

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