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PSoC™ Designer: User Guide Assembly Language

1. Arguments JMP expr Conditional Flags Example JMP Jump unconditionally to the address indicated by the sum of the argument and the current PC 1 The current PC value is defined as the PC value that corresponds to the ROM address of the first byte of the JMP instruction The JMP instruction uses a two byte instruction format where the lower nibble of the first byte is used for the upper 4 bits of the 12 bit relative address This causes an effective 4 bit opcode Therefore the following are all valid opcode bytes for the JMP instruction 0x80 0x81 0x82 0x8F Operation Opcode Cycles Bytes PC lt PC 1 k 2048 lt k 2047 Ox8x 5 2 CF Carry Flag unaffected ZF Zero Flag unaffected 0000 main 0000 80 01 05 jmp SubFun Jump is forward relative to PC therefore offset is positive 0x01 0002 SubFun 0002 8F FD 05 jmp main Jump is backwards relative to PC therefore offset is negative OxFD Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 4 16 Jump if No Carry Description Arguments JNC expr Example December 8 2003 Section 4 M8C Instruction Set JNC If the Carry Flag is not set jump to the sum of the relative address argument and the current PC 1 The current PC value is defined as the PC value that corresponds to the ROM address of the first byte ofthe JNC instruction The JNC instruction uses a two byte instruction format where the lower nibble
2. December 8 2003 Push Register onto Stack Section 4 M8C Instruction Set PUSH Transfer the value from the specified M8C register to the top of the stack as indicated by the value of the SP at the start of the instruc tion After placing the value on the stack the SP is incremented The Zero Flag is set if the pushed value is zero else the Zero Flag is cleared The Carry Flag is not affected by this instruction For PSoC microcontrollers with more than 256 bytes of RAM the stack is confined to a single designated stack page defined in the device data sheet The M8C automatically selects the stack page as the source for the memory write during the PUSH instruction Therefore a PUSH instruction may be issued in any PUSH page After the PUSH has completed user code will be operating from the same RAM page as before the PUSH instruction was executed Operation Opcode Cycles Bytes ram SP lt A 0x08 1 SP amp SP 1 ram SP X 0x10 4 1 SP lt SP 1 CF Carry Flag unaffected ZF Zero Flag unaffected mov A Ox3E push A top value of stack is now 0x3E SP 1 mov X Ox3F push X top value of stack is now Ox3F SP 1 Document 38 12004 CY Rev A CMS Rev 2 1 63 PSoC Designer Assembly Language User Guide 4 27 64 Return Description Arguments RET Conditional Flags Example RET The last two bytes placed on the stack are used to change the PC The lower 8 bits of the Pc are pop
3. A M8C Microcontroller X PC SP F IOW IOR XlO MW MR DA 7 0 ID 7 0 PC 15 0 Vv Vv Registers RAM ROM Bank 0 Page 0 SROM 256 bytes 256 bytes Bank 1 Page 1 256 bytes 256 bytes Flash m total number of flash blocks in device mx64 n total number of RAM pages minus 1 in the device byte IOR register read blocks IOW register write Page n MR memory read 256 bytes MW memory write Figure 1 M8C Microcontroller Address Spaces Instruction Format The M8C has a total of seven instruction formats which use instruction lengths of one two and three bytes All instruction bytes are fetched from the program memory Flash using an address and data bus that are independent from the address and data buses used for register and RAM access While examples of instructions will be given in this section refer to Section 4 M8C Instruction Set for detailed information on individual instructions December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 15 PSoC Designer Assembly Language User Guide 2 4 1 2 4 2 One Byte Instructions Many instructions such as some of the mov instructions have single byte forms because they do not use an address or data as an operand As shown in Table 3 one byte instructions use an 8 bit opcode The set of one byte instruc tions can be divided into four categories according to where their results are stored Table 3 One Byte Instruction Format Byte 0 8 bit op
4. s value is incremented after the source value is read For PSoC microcontrollers with more than 256 bytes of RAM the Data Page Read ppr_pr register is used to determine which RAM page to use with the source address Therefore values from pages other than the cur rent page may be retrieved without changing the Current Page Pointer Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 2 5 10 Section 2 The M8C Microprocessor ceP DR The pointer is always read from the current RAM page For informa tion on the pP amp p amp and cr ps registers please see the device data sheet Table 14 Source Indirect Post Increment Opcode Operand 1 Instruction Source Address Pointer Source Indirect Post Increment example Source Code Machine Comments Code MVI A 8 3E 08 The value in memory at address 8 the indirect address points to a memory location in RAM The value at the memory location pointed to by the indi rect address is moved into the Accumulator The indirect address at address 8 in memory is then incremented Destination Indirect Post Increment Only one instruction uses this addressing mode The destination address stored in operand 1 is actually the address of a pointer During instruction exe cution the pointer s current value is read to determine the destination address in RAM where the Accumulator s value will be stored The pointer s value is incremented after the value is written to the destinat
5. 0000 55 3C 02 08 mov 3Ch 2 0003 16 3C 01 09 sub 3Ch 1 2 1 1 CF 0 ZF 0 0006 BO 02 05 jnz SubFun jump to SubFun 0008 30 04 halt 0009 0009 SubFun 0009 40 04 nop 54 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 4 18 Jump if Zero Description Arguments JZ expr Conditional Flags Example Section 4 M8C Instruction Set JZ If the Zero Flag is set jump to the address indicated by the sum of the argument and the current Pc 1 The current Pc value is defined as the Pc value that corresponds to the ROM address of the first byte of the JZ instruction The JZ instruction uses a two byte instruction format where the lower nibble of the first byte is used for the upper 4 bits of the 12 bit relative address This causes an effective 4 bit opcode Therefore the following are all valid opcode bytes for the JZ instruction OxAO OxA1 0xA2 0xAF Operation Opcode Cycles Bytes PC lt PC 1 k 2048 lt k lt 2047 OxAx 5 5 CF Carry Flag unaffected ZF Zero Flag unaffected 0000 main 0000 55 3C 02 08 mov 3Ch 2 0003 16 3C 02 09 sub 3Ch 2 72 2 0 CF 0 ZF 1 0006 AO 02 05 jz SubFun jump to SubFun 0008 30 04 halt 0009 0009 SubFun 0009 40 04 nop December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 55 PSoC Designer Assembly Language User Guide 4 19 56 Long Call Description Arguments LCALL expr Conditional Flags Example
6. swapping the order of the upper and lower bytes The arguments may be constants or labels The length of the source line limits the number of arguments in a DWL statement Directive Arguments DWL lt value gt value2 valuen 5 9 1 Example 6 bytes are defined starting at address 2000 MyNum EQU 6655h ORG 2000h MyTable DWL 2211h 4433h MyNum December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 81 PSoC Designer Assembly Language User Guide 5 10 Equate Label EQU Description Assign an integer value to a label The label and operand are required for an Directive EQU 5 10 1 Example BITMASK i EQU directive The argument must be a constant or label or the current PC Each EQU directive may have only one argument and if a label is defined more than once an assembly error will occur To use the same equate in more than one assembly source file place the equate in an inc file and include that file in the referencing source files Do not export equates from assembly source files or the PSoC Designer Linker will resolve the directive in unpredictable ways Syntax label EQU lt value address gt s equated to 1Fh BITMASK EQU 1Fh 5 11 Export Description Directive EXPORT 5 11 1 Example MyVariable Export MyV AR BL 82 MyVariable EXPORT Designate that a label is global and can be referenced in another file Other wise th
7. the Flag register otherwise the Zero Flag is cleared Arguments Operation Opcode Cycles Bytes SBB A expr A A K CF 0x19 4 2 SBB A expr A lt A ram k CF Ox1A 6 2 SBB A X expr A A ram X k CF Ox1B 7 2 SBB expr A ram k lt ram k A CF Ox1C 7 2 SBB Xtexpr A ram X k lt ram X k A CF Ox1D 8 2 SBB expr expr ram k lt ram k k CF Ox1E 9 3 SBB X expr expr ram X k lt ram X k ky CF Ox1F 10 3 Conditional Flags Example 1 Example 2 December 8 2003 CF Set if treating the numbers as unsigned the result lt 0 cleared otherwise ZF Set if the result is zero cleared otherwise mov A 0 Set accumulator to zero or F 0x02 set carry flag sbb A 12 accumulator value is now 0xF3 mov 0x39 2 initialize ram 0x39 0x02 inc 0x40 ram 0x40 20x00 CF 1 mov 0x40 FFh initialize ram 0x40 0xff sbb 0x39 0 ram 0x39 0x01 Document 38 12004 CY Rev A CMS Rev 2 1 69 PSoC Designer Assembly Language User Guide 4 33 70 Subtract without Borrow SUB Description Arguments SUB A expr SUB A expr SUB A X expr SUB expr A SUB X expr A SUB expr expr SUB X expr expr Conditional Flags Example 1 Example 2 Computes the difference of the two operands The first operand s value is replaced by the computed difference If the difference is less than 0 the Carry Flag is set in the Flag regis
8. 2003 Section 5 Assembler Directives OV reg Counter8 1 COMPARE REG A ENDSECTION 5 18 Suspend and Resume Code Compressor Suspend OR F 0 Resume ADD SP 0 Description Used to prevent code compression of the code between the OR F 0 and ADD SP 0 instructions The code compressor may need to be suspended for timing loops and jump tables If the JACC instruction is used to access fixed offset boundaries in a jump table any LJMP and or LCALL entries in the table may be optimized to relative jumps or calls changing the proper offset value for the JACC An RET or RETT instruction will resume code com pression if it is encountered before an ADD SP 0 instruction These instruc tions are defined as the macros Suspend CodeCompressor and Resume CodeCompressor in m c inc Directive Arguments OR F 0 lt none gt ADD SP 0 5 18 1 Example Code compression is suspended for the jump table OR F 0 OV A State JACC StateTable StateTable LJMP Statel LJMP State2 LJMP State3 ADD SP 0 December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 87 PSoC Designer Assembly Language User Guide 88 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 ee Section 6 Compile Assemble Error Messages Section 6 Compile Assemble Error Messages This section describes the PSoC Designer Linker as well as C Compiler and Assembler errors and warnings Once you have add
9. 7 2 ADD expr A C Z 31 4 2 XORA expr Z 5E 7 2 MOVA reg Xtexpr Z 05 8 2 ADD X expr A C Z 32 6 2 XORA expr Z 5F 10 3 MOV expr expr 06 9 3 ADD expr expr C Z 33 7 2 XORA X expr Z 60 5 2 MOV reg expr A 07 10 3 ADD X expr expr C Z 34 7 2 XOR expr A Z 61 6 2 MOV reg X expr A 08 4 1 PUSHA 35 8 2 XOR X expr A Z 62 8 3 MOV reg expr expr 09 4 2 ADCA expr C Z 36 9 3 XOR expr expr Z 63 9 3 MOV reg X expr expr 0A 6 2 ADCA expr C Z 37 10 3 XOR Xtexpr expr Z 64 4 1 ASLA C Z 0B 7 2 ADCA Xtexpr C Z 38 5 2 ADD SP expr 65 7 2 ASL expr 7 0C 7 2 ADC expr A C Z 39 5 2 CMPA expr if A B Z 1 66 8 2 ASL X expr Cr 0D 8 2 ADC Xtexpr A C Z 3A 7 2 CMPA expr if A lt B C 1 67 4 1 ASRA C Z 0E 9 3 ADC expr expr C Z 3B 8 2 CMPA Xtexpr 68 7 2 ASR expr C Z OF 10 3 ADC X expr expr C Z 3C 8 3 CMP expr expr 69 8 2 ASR Xtexpr 97 10 4 1 PUSHX 3D 9 3 CMP Xtexpr expr 6A 4 1 RLCA 097 11 4 2 SUBA expr C Z 3E 10 2 MVIA expr Z 6B 7 2 RLC expr C97 12 6 2 SUBA expr C Z 3F 10 2 MVI expr A 60 8 2 RLC Xtexpr C Z 13 7 2 SUBA Xtexpr C Z 40 4 1 NOP 6D 4 1 RRCA C Z 14 7 2 SUB expr A C Z 41 9 3 AND reg expr expr Z 6E 7 2 RRC expr C Z 15 8 2 SUB Xtexpr A C Z 42 10 3 ANDreg Xtexpr expr Z 6F 8 2 RRC Xtexpr 77 16 9 3 SUB expr expr C Z 43 9 3 OR reg expr expr Z 70 4 2 ANDF expr 74 17 10 3 SUB Xtexpr expr C Z 44 10 3 OR reg Xtexpr expr Z 71 4 2 ORF expr C Z 18 5 1 POPA Z 45
10. 7 2 MOVA reg X expr Z 66 8 2 ASL Xtexpr Gz 5F 10 3 MOV expr expr 67 4 1 ASRA Gz 60 5 2 MOV regfexpr A 68 7 2 ASR expr C Z 61 6 2 MOV reg Xtexpr A 69 8 2 ASR Xtexpr C Z 62 8 3 MOV reg expr expr 9x 11 2 CALL 63 9 3 MOV reg Xtexpr expr 39 5 2 CMPA expr if A B Z 1 3E 10 2 MVIA expr Z 3A 7 2 CMPA expr if A lt B C 1 3F 10 2 MVI expr A 3B 8 2 CMPA Xtexpr 40 4 1 NOP 3C 8 3 CMP expr expr 29 4 2 ORA expr Z 3D 9 3 CMP X expr expr 2A 6 2 ORA expr Z 73 4 1 CPLA 2B 7 2 ORA Xtexpr Z 78 4 1 DECA C Z 2C 7 2 OR expr A Z 79 4 1 DECX C Z 2D 8 2 OR Xtexpr A Z 7A 7 2 DEC expr C Z 2E 9 3 OR expr expr Z 7B 8 2 DEC X expr C Z 2F 10 3 OR Xtexpr expr Z 30 9 1 HALT 43 9 3 OR reg expr expr Z 74 4 1 INCA C Z 44 10 3 OR reg Xtexpr expr Z 75 4 1 INCX C Z 71 4 2 ORF expr C Z Note Interrupt acknowledge to Interrupt Vector table 13 cycles Table A 3 Assembly Syntax Expressions Precedence Expression Symbol Form 1 Bitwise Complement e a 2 Multiplication Division Modulo a b a b a b 3 Addition Subtraction a b a b 4 Bitwise AND amp a amp b 5 Bitwise XOR A a b 6 Bitwise OR alb 7 High Byte of an Address gt gt a 8 Low Byte of an Address lt lt a 96 Document 38 12004 CY Rev A CMS Rev 2 1 sak OoN OSZ AAAA Ce 4 O 4 0o TD e 5 oduooc ococo 5c doco o cg 5c c 200 1 90o407 e Instruction Format seg x PO
11. BLKW lt size gt 5 4 1 Example A 4 byte variable called MyVariable is allocated AREA bss MyVariable BLKW 2 5 5 Define Byte DB Description Reserves bytes of ROM and assigns the specified values to the reserved bytes This directive is useful for creating data tables in ROM Arguments may be constants or labels The length of the source line limits the number of arguments in a DB statement Directive Arguments DB lt value1 gt value2 valuen 5 5 1 Example 3 bytes are defined starting at address 3000 MyNum EQU 77h ORG 3000h MyTable DB 55h 66h MyNum December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 79 PSoC Designer Assembly Language User Guide 5 6 Define ASCII String DS Description Stores a string of characters as ASCII values The string must start and end with quotation marks The string is stored character by character in ASCII hex format The back slash character is used in the string as an escape character Non printing characters such as n and r can be used A quotation mark can be entered into a string using the backslash a single quote as V anda backslash as V The string is not null terminated To create a null terminated string follow the DS with a DB 00h oruse ASCIZ Directive Arguments DS lt character string gt 5 6 1 Example My String is defined MyString DS My String 5 7 Define UNICODE String DSU De
12. December 8 2003 Internal Registers Notation Document 38 12004 CY Rev A CMS Rev 2 1 Description Accumulator Carry Flag Expression Flags ZF CF and Others Operand 1 Value First Operand of 2 Operands Second Operand of 2 Operands Program Counter Stack Pointer X Register Zero Flag Register Space o PSoC Designer Assembly Language User Guide 10 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 ein eS Section 1 Introduction Section 1 Introduction 1 1 Purpose The PSoC Designer Assembly Language User Guide documents the assem bly language instruction set for the M8C microprocessor as well as other com patible assembly practices The PSoC Designer Integrated Development Environment software is avail able free of charge and supports development in assembly language For cus tomers interested in developing in C a low cost compiler is available Please contact your local distributor if you are interested in purchasing the C compiler for PSoC Designer For more information about developing in C for the PSoC device please read the PSoC Designer C Language Compiler User Guide available at the Cypress web site 1 2 Section Overview Following is a brief description of each section in this user guide Section 2 The M8C Microprocessor Discusses the microprocessor and explains address spaces instruction for mat and destination of instruction results It also lists all addressing modes
13. Destination Indexed addressing mode are two bytes in length Table 10 Destination Indexed Opcode Operand 1 Instruction Destination Index Destination Indexed Example Source Code Machine Comments Code ADD X47 A 05 07 The value in memory at address X 7 is added to the Accumulator The result is placed in memory at address X 7 The Accumulator is unchanged 2 5 6 Destination Direct Source Immediate For these instructions the destination address is stored in operand 1 of the instruction The source value is stored in operand 2 of the instruction All instructions using the Destination Direct Source Immediate addressing mode are three bytes in length Table 11 Destination Direct Source Immediate Opcode Operand 1 Operand 2 Instruction Destination Address Immediate Value Destination Direct Source Immediate examples Source Code Machine Comments Code ADD 7 5 06 07 05 The value in memory at address 7 is added to the immediate value 5 The result is placed in memory at address 7 MOV REG 8 6 62 08 06 The immediate value 6 is moved into register space at address 8 2 5 7 Destination Indexed Source Immediate For these instructions the destination offset from the x register is stored in operand 1 of the instruction The source value is stored in operand 2 of the December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 21 PSoC Designer Assembly Language User Guide 2 5 8 2 5 9 22 instruction A
14. Formats Radix Name Formats Example 127 ASCII Character J mov A J character constant Mov iN WU use NX to escape W mov A NN usce to escanea M 16 Hexadecimal 0x4A mov A 0x4A hex Ox prefix 4Ah mov A 4Ah hex append h mov A 4A phex S prefix 4A 10 Decimal 74 mov A 74 decimal no prefix 8 Octal 0112 mov A 0112 octal zero prefix Binary 0b01001010 mov A 0b01001010 bin 0b prefix 9501001010 mov A 01001010 bin prefix Labels as described on page 26 may be used as an operand for an instruc tion Labels are most often used as the operands for jump and cali instruc tions to specify the destination address However labels may be used as an argument for any instruction Dot Operator is used to indicate that the ROM address of the first byte of the instruction should be used as an argument to the instruction Example 1 mov A lt moves low byte of the PC to A Example 2 mov A moves high byte of the PC to A Example 3 jmp gt 3 nop nop jumped to this instruction nop Registers have two forms in PSoC microcontrollers The first type are those that exist in the two banks of user accessible registers The second type are Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 3 The PSoC Designer Assembler those that exist in the microprocessor Table 18 contains examples for all types of register operands Table 18 Register Formats Typ
15. LCALL Replaces the Pc value with the LCALL instruction s argument The new PC value determines the address of the first byte of the next instruction Two pushes are used to store the Program Counter current PC 2 on the stack The current PC value is defined as the PC value that corresponds to the ROM address of the first byte of the instruction First the upper 8 bits of the PC are placed on the stack followed by the lower 8 bits The Stack Pointer is post incremented for each push For PSoC microcontrollers with more than 256 bytes of RAM the stack is confined to a single designated stack page defined in the device data sheet The M8C automatically selects the stack page as the destination for the push during the LCALL instruction Therefore a LCALL instruction may be issued in any RAM page After the LCALL has completed user code will be oper ating from the same RAM page as before the LCALL instruction was executed This instruction has a 16 bit unsigned address A three byte instruction format is used where the first byte is a full 8 bit opcode Operation Opcode Cycles Bytes ram SP lt PC 153 ae 13 3 SP SP 1 ram SP lt PC 7 0 SP SP 1 PC lt k 0 lt k lt 65535 CF Unaffected ZF Unaffected 0000 main 0000 7C 00 05 13 lcall SubFun 0003 8F FC 05 jmp main Although in this example a full 16 bit address is not needed for the call to SubFun the listing above shows that the 1ca11 instruction is
16. PC 2 value resulting in a new PC that determines the address of the first byte of the next instruction The current PC value is defined as the PC value that corresponds to the ROM address of the first byte of the next instruction Two pushes are used to store the Program Counter PC 2 on the stack First the upper 8 bits of the PC are placed on the stack fol lowed by the lower 8 bits The Stack Pointer is post incremented for each push For devices with more than 256 bytes of RAM the stack is confined to a single designated stack page defined in the device data sheet The M8C automatically selects the stack page as the destination for the push during the CALL instruction There fore a CALL instruction may be issued in any RAM page After the CALL has completed user code will be operating from the same RAM page as before the CALL instruction was executed This instruction has a 12 bit twos complement relative address that is added to the PC The 12 bits are packed into the two byte instruction format by using the lower nibble of the opcode and the second byte of the instruction format Therefore all opcodes with an upper nibble of 9 are ca11 instructions The x character is used in the table below to indicate that the first byte of a call instruction can have one of 16 values i e 0x90 0x91 0x92 0x9F Operation Opcode Cycles Bytes C PC 2 k C2048 lt k lt 2047 0x9x 11 2 CF Unaffected ZF Unaffected
17. The substitution list comes from the second oreach argument In this second argument we see another MAKE keyword function called fil ter out The filter out function removes obj main o from the list of all targets being built e g ob 3 2 0 As you remember this was one of the goals for this example You can filter out additional files by adding those files to the first argument of ilter out suchas filter out obj main o Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 3 The PSoC Designer Assembler obj excludeme o The MAKE symbol combination is a shortcut syntax that refers to the list of all the targets e 9 obj 0 The third argument in the foreach function is expanded into a sequence of commands for each substitution to update or add the object file to the library This local dep example is prepared to handle both C and assembly source files and put them in the library PSoC ToolsLib a The library is created updated in the project root folder in this example However you can provide a full path to another folder e g LIBCMD a c temp PSoC ToolsLib a library file Another goal was to not include the boot asm file in the library This is easy given that the master Makefile contains a separate rule for the boot asm source file which we will not redefine in ocal dep You can cut and paste this example and place it in a ocal dep file in the root folder of any proje
18. The Carry Flag is not affected Operation Opcode Cycles Bytes A lt A k 0x31 4 2 A lt A eram k 0x32 6 2 A lt A ram X k 0x33 7 2 ram k lt ram k A 0x34 T 2 ram X k lt ram X k A 0x35 8 2 ram k ram k k 0x36 9 3 ram X k ram X k k 0x37 10 3 reg k4 reg k 9 k 0x45 9 3 reg X k lt reg X k k 0x46 10 3 E 3k 0x72 4 2 CF Unaffected unless F is destination ZF Set if the result is zero cleared otherwise unless F is desti nation mov A 0x00 xor A OxAA A O0xAA CF unchanged ZF 0 and F 0x00 F 0 xor F 0x01 F 1 therefore CF 0 ZF 0 mov A 0x5A xor A OxAA A O0xF0 CF unchanged ZF 0 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 eee Section 5 Assembler Directives Section 5 Assembler Directives Assembler directives are used to communicate with the assembler and do not generate code The directives allow a firmware developer to conditionally assemble source files equate character strings to values locate code or data at specific addresses etc While the directives are often shown in all capital letters the PSoC Designer Assembler ignores case for directives and instructions mnemonics However the assembler does consider case for user defined symbols i e labels This section will cover all of the assembler directives currently supported by the PSoC Designer Assembler A description of each directive and its syntax will be given
19. be an integer constant a label or the current PC The assembler does not keep track of areas previously defined and will not flag overlapping areas in a single source file Directive Arguments ORG address gt 5 16 1 Example The bytes defined after the ORG statement are at address 1000 ORG 1000h DB 55h 66h 77h 5 17 Section for Dead Code Elimination SECTION ENDSECTION Description Allows the removal of code specified between the SECTION and END SECTION directives The SECTION directive must be followed by an exported global label If there is no call to the global label the code will be eliminated and call offsets will be adjusted appropriately The ENDSECTION directive ends the dead code section Note that use of this directive is not limited to removing dead code PSoC Designer takes care of dead code if you check the Enable Elimination of un used User Modules area APIs field This feature can be accessed under Project gt gt Settings Compiler tab If you check this field upon a build the system will go in and remove all dead code from the APIs in effort to free up space Directive Arguments SECTION lt none gt ENDSECTION 5 17 1 Example The section of code is designated as possible dead code Export Counter8 1 WriteCompareValue SECTION Counter8 1 WriteCompareValue 86 Document 38 12004 CY Rev A CMS Rev 2 1 December 8
20. file the linker resolves any references between the input files In some detail the linking steps involve 1 Making the startup file boot asm the first file to be linked The startup file initializes the execution environment for the C program to run December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 89 PSoC Designer Assembly Language User Guide 6 2 90 2 Appending any libraries that you explicitly request or in most cases as are requested by the IDE to the list of files to be linked Library modules that are directly or indirectly referenced will be linked All user specified object files e g your program files are linked 3 Scanning the object files to find unresolved references The linker marks the object file possibly in the library that satisfies the references and adds it to its list of unresolved references It repeats the process until there are no outstanding unresolved references 4 Combining all marked object files into an output file and generating map and listing files as needed For additional information about Linker and specifying Linker settings refer to the PSoC Designer Integrated Development Environment User Guide Project Settings Preprocessor Errors Note that these errors and warnings are also associated with C Compiler errors and warnings Table 23 Preprocessor Errors Warnings Error Warning not followed by macro parameter occurs at border of replacement d
21. is decremented after the first byte is removed The lower 8 bits of the PC are popped off the stack next followed by the SP being decremented by one again Finally the upper 8 bits of the PC are popped off the stack followed by a last decrement of the SP The Carry and Zero Flags are updated with the values from the first byte popped off the stack For PSoC devices with more than 256 bytes of RAM the stack is confined to a single designated stack page defined in the device data sheet The M8C automatically selects the stack page as the source for the pop during the RETI instruction Therefore an RETI instruction may be issued in any RAM page After the RETI has completed user code will be operating from the same RAM page as before the RETI instruction was executed Operation Opcode Cycles Bytes F lt ram SP SP amp sp 1 PC 7 0 lt ram SP SP amp SP 1 PC 15 8 lt ram SP CF All Flag bits are restored to the value pushed during an interrupt call ZF All Flag bits are restored to the value pushed during an interrupt call December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 65 PSoC Designer Assembly Language User Guide 4 29 Rotate Left through Carry RLC Description Shifts all bits of the instruction s argument one bit to the left Bit 0 is loaded with the Carry Flag The most significant bit of the specified location is loaded into the Carry Flag lt lt lt lt lt 7 6 5 4 3 2
22. is usually used to explain the assembly code and may be December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 29 PSoC Designer Assembly Language User Guide 3 2 3 3 30 placed anywhere in the source file The PSoC Designer Assembler ignores comments however they are written to the listing file for reference Directives An assembler directive is used to tell the assembler to take some action during the assembly process Directives are not understood by the M8C microproces sor As such directives allow the firmware writer to create code that is easier to maintain See Section 5 Assembler Directives on page 75 for more informa tion on directives Listing File Format A project name gt 1st file is created each time the assembler completes with out errors or warnings The list file may be used to understand how the assem bler has converted the source code into machine code The two lines below represent typical lines found in a listing file Lines that begin with a four digit number in parentheses are source file lines The number in parentheses is source file line number The text following the right parenthesis is the exact text from the source file The second line in the exam ple below begins with a four digit number followed by a colon This four digit number indicates the ROM address for the first machine code byte that follows the colon In this example the two hexidecimal numbers that fol
23. k 0x06 9 3 RAM X k RAM X k4 k 0x07 10 3 SP SP k 0x38 5 2 CF Set if the result 2255 cleared otherwise ADD SP expr does not affect the Carry Flag ZF Set if the result is zero cleared otherwise ADD SP expr does not affect the Zero Flag mov A 10 initialize A to 10 decimal add A 240 result is A 250 decimal add A 6 result is A 0 CF 1 ZF 1 mov A 10 initialize A to 10 decimal add A 240 result is A 250 decimal add A 7 result is A 1 CF 1 ZF 0 add A 5 result is A 6 CF 0 ZF 0 mov A 10 initialize A to 10 decimal Swap A SP put 10 in SP add SP 240 result is SP 250 decimal add SP 6 SP 0 CF unchanged ZF unchanged Document 38 12004 CY Rev A CMS Rev 2 1 41 PSoC Designer Assembly Language User Guide 4 3 Bitwise AND Description Arguments AND A expr AND A expr AND A Xtexpr AND expr A AND X expr A AND expr expr AND X expr expr AND REG expr expr AND REG X expr expr AND F expr Conditional Flags Example 1 Example 2 42 AND Computes the logical AND for each bit position using both argu ments The result of the logical AND is placed in the corresponding bit position for the first argument The Carry Flag is only changed when the AND F expr instruc tion is used The Carry Flag will be set to the result of the logical AND of the Carry Flag at the beginning of instruction execution and the second argument s
24. line including lines with source code as long as the label appears first The PSoC Designer Assembler supports three types of labels local global and re usable local Local Labels consist of a character string followed by a colon Local labels cannot be referenced by other source files in the same project they can only be used within the file in which they are defined Local labels become global labels if they are exported The following example has a single local label named subFun Local labels are case sensitive Local Labels mov X 10 SubFun xor reg 00h FFh dec X jnz SubFun Global Labels are defined by the export assembler directive or by ending the label with two colons rather than one Global labels may be referenced from any source file in a project The following example has two global labels Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 3 The PSoC Designer Assembler The export directive is used to make the subFun label global while two colons are used to make the vorerun label global Global labels are case sensitive Global Labels EXPORT SubFun mov X 10 SubFun xor reg 00h FFh dec X jnz SubFun mov X 5 MoreFun xor reg 00h FFh dec X jnz MoreFun Re usable Local Labels have multiple independent definitions within a single source file They are defined by preceding the label string with a period The scope of a local label is boun
25. lt ram k 3 ram k lt ram k 3 lt ram k 4 ram k 4 lt ram k 5 ram k 5 lt ram k 6 ram k 6 lt ram k 7 ram k 7 lt CF RRC X expr r z Ox6F 8 2 CF lt ram X k 0 ram X k 0 lt ram X k 1 ram X k 1 lt ram X k 2 ram X k 2 lt ram X k 3 ram X k lt ram X k 3 e ram X k 4 1 5 1 6 17 ram X k 4 ram X k ram X k 5 lt ram X k ram X k 6 ram X k ram X k 7 lt CF 68 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Conditional Flags Section 4 M8C Instruction Set CF Set if LSB of the specified Accumulator was set before the shift cleared otherwise ZF Set if the result is zero cleared otherwise Example 1 or F 0x04 set carry flag and A 0x00 clear the accumulator rro A A 0x80 CF 0 ZF 0 Example 2 and F OxFB clear carry flag mov A OxFF Pinitialize A to 255 and A 0x00 make sure all flags are cleared rrc A A O0Ox7F CF 1 ZF 0 Example3 or F 0x04 set carry flag mov OxEB OxAA initialize A to 170 rre OxEB ram OxEB 0xD5 CF 1 ZF 0 4 32 Subtract with Borrow SBB Description Computes the difference of the two operands plus the carry value from the Flag register The first operand s value is replaced by the computed difference If the difference is less than 0 the Carry Flag is set in the Flag register If the sum is zero the Zero Flag is set in
26. of the address The Zero Flag is set if the retrieved byte is zero otherwise the Zero Flag is cleared The Carry Flag is not affected by this instruction Arguments Operation Opcode Bytes PC 7 0 lt X t2 lt PC 158 PC 15 8 A A lt rom PC PC 7 0 lt t1 Conditional Flags Example December 8 2003 PC 15 8 lt t2 CF Unaffected ZF Set if A is zero cleared otherwise 0000 main 0000 50 00 04 mov A 00h 0002 57 08 04 mov X 08h 0004 28 11 romx 0005 060 00 05 mov reg 00h A 0007 40 04 nop 0008 30 04 halt The romx instruction will read a byte from Flash at address 0x0008 The halt opcode is at address 0x0008 therefore reg ister 0x00 will receive the value 0x30 Document 38 12004 CY Rev A CMS Rev 2 1 67 PSoC Designer Assembly Language User Guide 4 31 Rotate Right through Carry RRC Description Shifts all bits of the instruction s argument one bit to the right The Carry Flag is loaded into the most significant bit of the argument Bit 0 of the argument is loaded into the Carry Flag gt gt gt gt gt gt gt CF gt 7 6 5 4 3 2 1 0 Arguments Operation Opcode Cycle Bytes s RRC A 0x6D 4 1 CF A 0 A 0 lt A 1 A 1 A2 A A2 amp A3 A3 lt A4 A4 AS A 5 A 6 A A7 A 7 CF RRC expr Ox6E 7 2 CF lt ram k 0 ram k 0 lt ram k 1 ram k 1 lt ram k 2 ram k 2
27. the following characters in path and file names they are prob lematic lt gt amp December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 25 PSoC Designer Assembly Language User Guide 26 From the components listed in Table 16 all user code is built and complex con ditional assembly constraints can be placed on a collection of source files The text below has an example of each of the six basic components that will be dis cussed in detail in the following sub sections Line 1 is a comment line as indi cated by the character string Lines 5 6 and 7 also have comments starting with the character and continuing to the end of the line Lines 2 and 3 are examples of assembler directives The character strings before the character in lines 3 and 4 are labels Lines 5 6 and 7 have instruction mne monics and operands Source File 1 My Project Source Code Components 2 include project inc 3 BASE equ 0x10 4 main 5 mov reg 0x00 0x34 write 0x34 to Port O0 6 mov A reg 0x04 read Port 1 7 and BASE 2 A store Port 1 value in RAM Labels A label is a case sensitive string of alphanumeric characters and underscores _ followed by a colon A label is assigned the address of the current Program Counter by the assembler unless the label is defined on a line with an zou directive See 5 10 Equate Label EQU on page 82 for more information Labels can be placed on any
28. using a three byte format which accommodates the 16 bit abso lute jump address of 0x0005 0005 0005 SubFun 0005 7F 08 ret Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 4 20 Long Jump Description Arguments LJMP expr Conditional Flags Example Section 4 M8C Instruction Set LJMP Jump unconditionally to the unsigned address indicated by the instruction s argument The LUMP instruction uses a three byte instruction format to accommodate a full 16 bit argument The first byte of the instruction is a full 8 bit opcode Operation Opcode Cycles Bytes PC lt K 0 lt k lt 65535 0x7D 7 3 CF Unaffected ZF Unaffected 0000 main 0000 7D 00 03 07 1jmp SubFun Although in this example a full 16 bit address is not needed for the jump to SubFun the listing above shows that the 1jmp instruction is using a three byte format which accommodates the 16 bit abso lute jump address of 0x0003 0003 0003 SubFun 0003 7D 00 00 07 l1jmp main Note that this instruction is jumping backwards relative to the cur rent PC value and the address in the instruction is a positive num ber 0x0000 This is because the 1jmp instruction uses an absolute address December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 57 PSoC Designer Assembly Language User Guide 4 21 58 MOV This instruction allows for a number of combinations of moves Immediate direct and indexed addressing are su
29. 0000 main 0000 40 nop 0001 90 E8 call SubFun 0003 40 nop Note that the relative address for the CALL above is positive 0xE8 and that the sum of that address and the Pc value for the first byte of the next instruction 0x0003 equals the address of the SubFun label 0xE8 0x0003 OxOOEB 0004 9F FA call main Note that the call to Main uses a negative address 0xFA 0006 OOEB org Ox00EB OOEB SubFun OOEB 40 nop OOEC 7F ret Document 38 12004 CY Rev A CMS Rev 2 1 45 PSoC Designer Assembly Language User Guide 4 7 Non destructive Compare CMP Description Arguments CMP A expr CMP A expr CMP A Xtexpr CMP expr expr CMP X expr expr Conditional Flags Example Subtracts the second argument from the first If the difference is less than zero the Carry Flag is set If the difference is 0 the Zero Flag is set Neither operand s value is destroyed by this instruction Operation Opcode Cycles Bytes A k 0x39 5 2 A ram k Ox3A 7 2 A ram X k 0x3B 8 2 ram k k 0x3C 8 3 ram X k k Ox3D 9 3 CF Set if Operand 1 lt Operand 2 cleared otherwise ZF Set if the operands are equal cleared otherwise 34 initialize the accumulator to 34 33 A gt 34 CF cleared A 33 ZF cleared 34 A 34 CF cleared ZF set r 35 A lt 35 CF set A 35 ZF cleared mov cmp cmp cmp pop 4 8 Complement Accumulator CPL Description Arguments CPL A Conditional Fla
30. 01 Con20 cUnmgpouu do nmuocqcU 2 nme oco x Ses ese x x o4 00 Q9 Q0 Q C2 CO CO f 4 od oqodod qod O Oi X Oi amp O amp O m m xdi 0 A in O O U Table A 2 Instruction Set Summary Sorted by Mnemonic g 9 g Instruction Format Flags g g S Instruction Format Flags amp 9 E 20 D D g g 09 4 2 ADCA expr C Z 76 7 2 INC expr C Z 0A 6 2 ADCA expr Gz 77 8 2 INC X expr C Z 0B 7 2 ADCA Xtexpr C Z Fx 13 2 INDEX Z 0C 7 2 ADC expr A C Z Ex 7 BE JACC 0D 8 2 ADC X expr A Gz a5 PEJC 0E 9 3 ADC expr expr C Z 8x 5 2 JMP OF 10 3 ADC X expr expr C Z Dx 5 2 JNC 01 4 2 ADDA expr C Z Exe 5 PH JV 02 6 2 ADDA expr C Z Ax 5 2 JZ 03 7 2 ADDA Xtexpr C Z TC 13 3 LCALL 04 7 2 ADD expr A C Z TD 7 3 LJMP 05 8 2 ADD X expr A 37 4F 4 1 MOVX SP 06 9 3 ADD expr expr CZ 50 4 2 MOVA expr Z 07 10 3 ADD X expr expr C Z 51 5 2 MOVA expr Z 38 5 2 ADD SP expr 52 6 2 MOVA X expr Z 21 4 2 ANDA expr Z 53 5 2 MOV expr A 22 6 2 ANDA expr Z 54 6 2 MOV X expr A 23 7 2 ANDA Xtexpr Z 55 8 3 MOV expr expr 24 7 2 AND expr A Z 56 9 3 MOV X expr expr 25 8 2 AND X expr A Z 57 4 2 MOVX expr 26 9 3 AND expr expr Z 58 6 2 MOVX expr 27 10 3 AND X expr expr Z 59 7 2 MOVX X texpr 70 4 2 ANDF expr C Z 5A 5 2 MOV expr X 41 9 3 AND reg expr expr Z 5B 4 1 MOVA X Z 42 10 3 ANDreg Xtexpr expr Z 5C 4 1 MOVX A 64 4 1 ASLA C Z 5D 6 2 MOVA reg expr Z 65 7 2 ASL expr C Z 5E
31. 1 tst 0x00 0x03 CF 20 ZF 0 i e bit 0 and 1 are 1 tst 0x00 0x04 CF 0 ZF 1 i e bit 2 is 0 Document 38 12004 CY Rev A CMS Rev 2 1 73 PSoC Designer Assembly Language User Guide 4 37 74 Bitwise XOR Description Arguments XOR A expr XOR A expr XOR A Xtexpr XOR expr A XOR X expr A XOR expr expr XOR X expr expr XOR REG expr expr XOR REG X expr expr XOR F expr Conditional Flags Example 1 Example 2 Example 3 XOR Computes the logical XOR for each bit position using both argu ments The result of the logical XOR is placed in the corresponding bit position for the argument The Carry Flag is only changed when the XOR F expr instruc tion is used The Carry Flag will be set to the result of the logical XOR of the Carry Flag at the beginning of instruction execution and the second argument s value at bit position 2 i e F 2 and expr 2 Forthe XOR F expr instruction the Zero Flag is handled the same as the Carry Flag in that it is changed as a result of the logi cal XOR of the Zero Flag s value at the beginning of instruction execution and the value of the second argument s value at bit posi tion 1 i e F 1 and expr 1 However for all other XOR instructions the Zero Flag will be set or cleared based on the result of the logical XOR operation If the result of the xon is that all bits are zero the Zero Flag will be set otherwise the Zero Flag is cleared
32. 1 0 k CF Arguments Operation Opcode Cycles Bytes RLC A J 0x6A 4 1 CF A7 A 1 A 6 A 6 A 5 Ab A4 ASS A 4 lt A 3 A33 A 2 A 2 Ail A 1 A 0 A 0 lt CF RLC expr r 7 0x6B T 2 CF lt IST 7 k 6 5 4 ram k st T lt ram k 3 2 4 PE RLC X expr if 7 0x6C 8 2 CF lt ram X k 7 ram X k 7 lt ram X k 6 ram X k 6 lt ram X k 5 am X k 5 ram X k 4 ram X k lram X k 4 lt ram X k 3 1 2 1 0 3 E 3 X k 3 e ram X k ram X k 2 lt ram X k ram X k 1 lt ram X k ram X k 0 lt CF id SS ES ES Conditional Flags CF Set if the MSB of the specified Accumulator was set before the shift otherwise cleared ZF Set if the result is zero cleared otherwise Example 1 and F OxFB clear carry flag mov A Ox7F initialize A with 127 ric A A OxFE CF 0 ZF 0 66 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 4 M8C Instruction Set 4 30 Absolute Table Read ROMX Description Moves any byte from ROM Flash into the Accumulator The address of the byte to be retrieved is determined by the 16 bit value formed by the concatenation of the A and x registers The A register is the most significant byte and the x register is the least significant byte
33. 15 CR 45 2D 055 TT 4D 115 M 109 6D 155 m 14 0E 016 SO 46 2E 056 78 4E 116 N 110 6E 156 n 15 OF 017 SI 47 2F 057 79 4F Wy 111 6F 157 o 16 10 020 DLE 48 30 060 0 80 50 120 P 112 70 160 p 17 11 021 DC1 49 31 061 1 81 51 121 Q 113 71 161 q 18 12 022 DC2 50 32 062 2 82 52 122 R 114 72 162 r 19 13 023 DC3 51 33 063 3 83 53 123 S 115 73 163 s 20 14 024 DC4 52 34 064 4 84 54 124 T 116 74 164 t 21 15 025 NAK 53 35 065 5 85 55 125 U 117 75 165 u 22 16 026 SYN 54 36 066 6 86 56 126 V 118 76 166 v 23 17 027 ETB 55 37 067 7 87 57 127 W 119 77 167 w 24 18 030 CAN 56 38 070 8 88 58 130 X 120 78 170 x 25 19 031 EM 57 39 071 9 89 59 131 Y 121 79 171 y 26 1A 032 SUB 58 3A 072 90 5A 132 Z 122 7A 172 Zz 27 1B 033 ESC 59 3B 073 91 5B 133 123 7B 173 1 28 1C 034 FS 60 3C 074 lt 92 5C 134 124 7C 174 29 1D 035 GS 61 3D 075 93 5D 135 125 7D 175 30 1E 036 RS 62 3E 076 gt 94 5E 136 amp 126 7E 176 amp 31 1F 037 US 63 3F 077 2 95 5F 137 127 TF 177 DEL 98 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 A ADC 40 ADD 41 Address Spaces 14 14 Addressing Modes 18 Destination Direct 20 Destination Direct Source Direct 22 Destination Direct Source Immediate 21 Destination Indexed 21 Destination Indexed Source Immediate 21 Destination Indirect Post Increment 23 Source Direct 19 Source Immediate 19 Source Indexed 20 Source Indirect Post Increment 22 AND 42 ASL 43 ASR 44 C CALL 45 CMP 46 Code Compression 7
34. 2003 Document 38 12004 CY Rev A CMS Rev 2 1 91 PSoC Designer Assembly Language User Guide 6 3 92 Assembler Errors Table 25 Assembler Errors Warnings Error Warning l addressing mode must end with expected if else endif mismatched lt character gt expected EOF encountered before end of macro defini tion No preceding global symbol absolute expression expected badly formed argument without a matching branch out of range cannot add two relocatable items cannot perform subtract relocation cannot subtract two relocatable items cannot use org in relocatable area character expected comma expected equ statement must have a label identifier expected but got character lt c gt illegal addressing mode illegal operand input expected label must start with an alphabet or letter expected but got c macro name already entered macro definition cannot be nested maximum lt gt macro arguments exceeded missing macro argument number multiple definitions name no such mnemonic lt name gt relocation error target too far for instruction too many include files too many nested if undefined mnemonic word undefined symbol unknown operator unmatched else unmatched endif Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 6 Compile Assemble Error Messages Table 26 Assembler Command Line Errors Warnings Error Warning cannot create output file s n To
35. 8 Code Compressor and Dead Code Elimination Er ror Messages 93 Compiling a File into a Library Module 34 Convention for Restoring Internal Registers 34 CPL 46 D DEC 47 Directive LITERAL ENDLITERAL 84 SECTION ENDSECTION 86 AREA 76 BLK 78 BLKW 79 DB 79 DS 80 DSU 80 December 8 2003 DW 81 DWL 81 EQU 82 EXPORT 82 IF ELSE ENDIF 83 INCLUDE 84 MACRO ENDM 85 ORG 86 Suspend Resume 87 F Five Basic Components of an Assembly Source File 25 H HALT 47 INC 48 INDEX 49 Instruction Format 15 One Byte Instructions 16 Three Byte Instructions 17 Two Byte Instructions 16 Internal Registers Accumulator 13 Flags 13 Index 13 Program Counter 13 Stack Pointer 13 Table 9 J JACC 50 JC 51 JMP 52 JNC 53 JNZ 54 JZ 55 Document 38 12004 CY Rev A CMS Rev 2 1 99 PSoC Designer Assembly Language User Guide L LCALL 56 Linker Operations 89 LJMP 57 MOV 58 MVI 59 N NOP 60 Notation Standards 9 O One Byte Instructions 16 OR 61 P POP 62 Product Updates 12 Purpose 11 PUSH 63 R RET 64 RETI 65 RLC 66 ROMX 67 RRC 68 S SBB 69 Section Overview 11 Source File Components Comments 29 Directives 30 Labels 26 Mnemonics 27 Operands 28 Source File Format 25 Source Immediate 19 SSC 72 SUB 70 Support 12 SWAP 71 T TST 73 100 XOR 74 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Document Revision History Docum
36. 9 3 XOR reg expr expr Z 72 4 2 XORF expr C Z 19 4 2 SBBA expr C Z 46 10 3 XOR reg X expr expr Z T3 4 1 CPLA Z 1A 6 2 SBBA expr C Z 47 8 3 TST expr expr Z 74 4 1 INCA C Z 1B 7 2 SBBA Xtexpr C Z 48 9 3 TST Xtexpr expr Z 75 4 1 INCX C Z 1C 7 2 SBB expr A C Z 49 9 3 TST reg expr expr Z 76 7 2 INC expr C Z 1D 8 2 SBB Xtexpr A C Z 4A 10 3 TST reg Xtexpr expr Z 77 8 2 INC X expr C Z 1E 9 3 SBB expr expr C Z 4B 5 1 SWAPA X Z 78 4 1 DECA 7 1F 10 3 SBB X expr expr C Z 4C 7 2 SWAPA expr Z 79 4 1 DECX C Z 205 5 MN POPX 4D 7 2 SWAPX expr 7TA 7 2 DEC expr C Z 21 4 2 ANDA expr Z 4E 5 1 SWAPA SP Z 7B 8 2 DEC Xtexpr C Z 22 6 2 ANDA expr Z 4F 4 1 MOVX SP 7C 13 3 LCALL 23 7 2 ANDA Xtexpr Z 50 4 2 MOVA expr Z TD 7 3 LJMP 24 7 2 AND expr A Z 51 5 2 MOVA expr Z TE 10 1 RETI o 25 8 2 AND Xtexpr A Z 52 6 2 MOVA Xtexpr Z TF 8 1 RET 26 9 3 AND expr expr Z 53 5 2 MOV expr A 8x 5 2 JMP 27 10 3 AND X expr expr Z 54 6 2 MOV X expr A 9x 11 2 CALL 28 11 1 ROMX Z 55 8 3 MOV expr expr Ax 5 2 JZ 29 4 2 ORA expr Z 56 9 3 MOV Xtexpr expr Bx 5 2 JNZ 2A 6 2 ORA expr Z 57 4 2 MOVX expr a5 PE JC 2B 7 2 ORA Xtexpr Z 58 6 2 MOVX expr Dx 5 2 JNC 2C 7 2 OR expr A Z 59 7 2 MOVX Xtexpr Ex 7 2 JACC Note Interrupt acknowledge to Interrupt Vector table 13 cycles Fx 13 2 INDEX Z December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 PSoC Designer Assembly Language
37. AA A O0xAA CF unchanged ZF 0 mov A or A and F 0x00 or F 0x01 F 1 therefore CF 0 ZF 0 4 25 Pop Stack into Register POP Description Arguments POP A POP X Conditional Flags Example 1 Example 2 Remove the last byte placed on the stack and put it in the specified M8C register The Stack Pointer is automatically decremented The Zero Flag is set if the popped value is zero otherwise the Zero Flag is cleared The Carry Flag is not affected by this instruction For PSoC devices with more than 256 bytes of RAM the stack is confined to a single designated stack page defined in the device data sheet The M8C automatically selects the stack page as the source for the memory read during the POP instruction Therefore a POP instruction may be issued in any RAM page After the POP has completed user code will be operating from the same RAM page as before the POP instruction was executed Operation Opcode Cycles Bytes A lt ram SP 1 0x18 5 1 SP lt SP 1 X lt ram SP 1 0x20 5 1 SP lt SP 1 CF Carry Flag unaffected ZF Set if A is updated to zero mov A 34 push A top value of stack is now 34 SP 1 mov A O0 clear the Accumulator pop A A 34 SP 1 mov A 34 push A top value of stack is now 34 SP 1 pop X 7X 34 SP 1 62 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 4 26 Description Arguments PUSH A PUSH X Conditional Flags Example 1 Example 2
38. BS REL CON OVR 5 1 1 Example A code area is defined at address 2000 AREA MyArea ROM MyArea start ORG 200 ABS CON Oh 5 1 2 Code Compressor and the AREA Directive The Code Compressor looks for duplicate code within the text Area The text Area is the 76 default area in which all C code is placed Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 5 Assembler Directives Not Allowed Function A Function B Function X text Area not text Area The above diagram shows a scenario that is not allowed or potentially prob lematic Code areas created with the AREA directive using a name other than text are not compressed or fixed up following compression Therefore if Function A in the text Area calls Function X in the non text Area then Function X calls Function B where there would be thepotential that the loca tion of Function B changed The call or jump generated in the code for Func tion X would go to the wrong location It is allowable for Function A to call a function in a non text Area and simply return For example if Function A in the text Area calls Function X in the non text Area then Function X calls to Function B could be invalid The location for Function B can change because it is in the text Area Calls and jumps are fixed up in the text Area only Following code compression the call location to Fu
39. CPP DR 0 set Current Page Pointer back to 0 mov reg DPR DR 2 set MVI write RAM page pointer mov EBh 10h initialize MVI read pointer to 10h mvi A EBh A 4 ram O EBh 1l1h mvi A EBh A 3 ram O EBh 12h Multi Page Example 4 mov reg CPP DR 0 set Current Page Pointer to 0 mov reg DPW DR 3 set MVI read RAM page pointer mov EBh 10h initialize MVI write pointer to 10h mov A 8 mvi EBh A ram 3 10h 8 ram O EBh 11h mov A 1 mvi EBh A ram 3 11h 1 ram O EBh 12h 4 23 No Operation NOP Description This one byte instruction performs no operation but consumes 4 CPU clock cycles Arguments Operation Opcode Cycles Bytes NOP None 0x40 4 1 Conditional Flags CF Carry Flag unaffected ZF Zero Flag unaffected 60 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 4 24 Bitwise OR Description Arguments OR A expr OR A expr OR A X expr OR expr A OR X expr A OR expr expr OR X expr expr OR REG expr expr OR REG X expr expr OR F expr December 8 2003 Section 4 M8C Instruction Set OR Computes the logical OR for each bit position using both argu ments The result of the logical OR is placed in the corresponding bit position for the first argument The Carry Flag is only changed when the OR F expr instruction is used The Carry Flag will be set to the result of the logical OR of the Carry Flag at the beginning of inst
40. F Ox0A 6 2 A lt A RAM X k CF 0x0B 7 2 RAM k RAM k A CF 0x0C 7 2 RAM X k lt RAM X k A CF 0x0D 8 2 RAM k RAM k k CF Ox0E 9 3 RAM X k RAM X ky k CF Ox0F 10 3 CF Set if the result gt 255 cleared otherwise ZF Set if the result is zero cleared otherwise mov A O0 Set accumulator to zero or F 0x02 set carry flag adc A 12 accumulator value is now 13 mov 0x39 0 initialize ram 0x39 0x00 mov 0x40 FFh initialize ram 0x40 0xFF inc 0x40 ram 0x40 20x00 CF 1 ZF 1 adc 0x39 0 ram 0x39 0x01 CF 0 ZF 0 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 4 M8C Instruction Set 4 2 Add without Carry ADD Description ADD ADD ADD ADD ADD ADD ADD ADD Arguments A expr A expr A X expr expr A X expr A expr expr X expr expr SP expr Conditional Flags Example 1 Example 2 Example 3 December 8 2003 Computes the sum of the two operands The first operand s value is replaced by the computed sum If the sum is greater than 255 the Carry Flag is set in the Flag register If the sum is zero the Zero Flag is set in the Flag register The ADD SP expr instruc tion does not affect the flags in any way Operation Opcode Cycles Bytes A A k 0x01 4 2 A A RAM k 0x02 6 2 A A RAM X k 0x03 7 2 RAM k lt RAM k A 0x04 7 2 RAM X k RAM X k A 0x05 8 2 RAM k RAM k
41. ION ENDLITERAL has no matching LITERAL SECTION has no ENDSECTION Unmatched LITERAL directive directive creating data may not be compatible with Code Com pression and other advanced technologies Possible Causes 1 Data defined in ROM does not have the LITERAL and ENDLITERAL direc tives 94 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Appendix A Assembly Language Reference Tables The tables in this appendix are intended to serve as a quick reference to the M8C instruction set and assembler directives For detailed information on the instruction set and the assembler directives see M8C Instruction Set on page 39 and Assembler Directives on page 75 Table A 1 Documentation Conventions Convention Courier New Size 10 bracketed bold Courier New Size 10 italics Usage Displays input and output Created by PSoC Designer rom template BOOT ASM Boot Code from Reset 000AREA TOP ABS ey c C 0000 8033 jmp start 0002 8031 jmp _ start 0004 801F jmp InterruptO 0006 801E jmp Interruptl Displays keyboard commands Enter or Ctrl C Displays file names and extensions lt Project Name gt rom December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 95 PSoC Designer Assembly Language User Guide xen epoodo 0 3 0 0 c 21 3 OO 0o NO O0 g o coc J c n O
42. LL 56 pEalgE sop mE LJMP 57 2x T MOV 58 4 22 Move Indirect Post Increment to Memory sss MVI 59 zbegi chou m o D EET NOP 60 74 Bits Za araa A AE OR 61 22 5 POD SACK MO BONS IGS sicceisasineaisnaconieiee eee POP 62 2 20 Fush Register OO SIR tnr d assk kr d SERM dba gati eor a caa baa PUSH 63 EST UU s o tuit te RR Id MN eo ER eti iMd c Mtm idee tidie iu RET 64 2228 Rebum mom WFO iet hn eens bote a e o attt RETI 65 4 29 ROE Ler Mougn Cay Ac E RLC 66 2 30 Absolute Table Road 1e tet ett REL a aaa E A4 ROMX 67 431 Rotate Right through Cany STE m o o o RRC 68 A2 ACL WINE BOTON Hec E SBB 69 A 33 SUbICacl WHO rie e ET SUB 70 AA SOA anise Ans Ase SWAP 71 SR Eres EP Me SSC 72 Sb Test WII BIEN Quei o reset bos E Delon iita Map o p ORE ERR TST 73 4T BSS XLI aistusasasctesdrisretui rs ERN SEED HRS IMDIR MMMME XOR 74 Section 5 Assembler Directives ccccccceeeeeeeeeeeeeeeeeeseneeeeeeeeeeeeeeeeeeeees 75 D DA ort pb asta Rote oan a ain D rs prO o GL s AREA 76 Tk EXIDE incen E RE E In MN dd EE D reer rnc HE MM E 76 5 1 2 Code Compressor and the AREA Directive sssssssssseees 76 5 2 NULL T rnninated ASCII SHING scan ccacs Secr RUE EPEoDc ue ER PU DU I m EPI IEEE PCR E UE REPE UNE ASCIZ 78 pal EGI NON m P 78 Do PRAN BIG M I IG ocssiriis ss oup SE RaN NE ON ee Terre rr cer ertrrrerrercy reernenrrt ts BLK 78 Sal EMDE saranta 78 PARAM Block in VIORIB a prepa onana a A BLKW 79 SE NICA o
43. PSoC Designer Assembly Language User Guide Revision 2 1 Cypress Revision A Spec 38 12004 Last Revised December 8 2003 Cypress MicroSystems Inc j M s CYPRESS MICROSYSTEMS il Cypress MicroSystems Inc 2700 162nd St SW Building D Lynnwood WA 98037 Phone 800 669 0557 Fax 425 787 4641 http www cypress com http www cypress com aboutus sales locations cfm support cypressmicro com Copyright 2001 2003 Cypress MicroSystems Inc All rights reserved PSoC Programmable System on Chip is a trademark of Cypress MicroSystems Inc Copyright 1999 2000 iMAGEcraft Creations Inc All rights reserved The information contained herein is subject to change without notice Table of Contents B e 7 Notation Standards ee oe ee ee edie 9 becpen T BIFOHOOBRO aiiin RED QUENREAM M XD LOK M Fav MU ONE 11 Re E T ET NN T1 eel eda I RUIT I D I m piis d 1 3 Product pus mne ten PTT RN TR HT ANT RC 12 1 4 Support REAA E TAT PETISE edu A SEAE DU spp MEINT N I La Section 2 The M8C Microprocessor eeeeeeeeeeeeeeeeeeen nnne 13 PAME E E CE a PETETA rib E op AEA RUBER cat EPA Fr FERRO EU KE ode IAE IAT EN 13 2 2 intemal Registers 1 conicere r eode ree ice riso T ien ded PASS PES ie oiii MNT DT a DUM 14 2 4 Instruction Format VER AATA TE eai eben DUE AEEA R Reife bu tek d E ET aeu d 2 4 1 One Byte Instru
44. PX 1 POPA 1 PUSHX 1 PUSHA 1 RETI 1 RET RLC A RLC expr RLC X expr ROMX RRC A RRC expr RRC X expr SBB A expr SBB A expr SBB A X expr SBB expr A SBB X expr A SBB expr expr SBB X expr expr SSC SUB A expr SUB A expr SUB A X expr SUB expr A SUB X expr A SUB expr expr SUB X expr expr SWAP A X SWAP A expr SWAP X expr SWAP A SP TST expr expr TST X expr expr TST reg expr expr TST reg X expr expr XOR F expr XOR A expr XOR A expr XOR A X expr XOR expr A XOR X expr A XOR expr expr XOR X expr expr XOR reg expr expr XOR reg X expr expr E NND x Q5 Co CO CO h h h O h h h CO CO CO CO NN CO CO hO h h h h CO CO hO h h2 h2 h2 KM PY December 8 2003 Flags GZ rz C Z C Z C Z 007 C Z C Z C Z C Z 097 CZ C Z CZ C Z 047 047 C Z rz C Z C Z N NNNNNNNNNONNNNWN Table A 4 Instruction Set Summary Sorted by Opcode m Instruction Format Flags Instruction Format Flags Oo m Instruction Format Flags g sg 388 BE e 9 B or go 2 o 6 oO D D E Ei x lt x lt x lt 00 15 1 SSC 2D 8 2 OR X expr A Z 5A 5 2 MOV expr X 01 4 2 ADDA expr C Z 2E 9 3 OR expr expr Z 5B 4 1 MOVA X Z 02 6 2 ADDA expr C Z 2F 10 3 OR X expr expr Z 5C 4 1 MOVX A 03 7 2 ADDA Xtexpr C Z 30 9 1 HALT 5D 6 2 MOVA reg expr Z 04
45. UT REG A Note that the 12 bit address for the INDEX instruction is positive and that the sum of the address 0x0E6 and the next instruction s address 0x0005 are equal to the first address of the ASClInum bers table 0x00EB Because the accumulator has been set to 3 before executing the INDEX instruction the fourth byte in the ASCI Inumbers table will be returned to A Therefore A will be 0x33 at the end of the INDEX instruction 0007 OOEB org OxOOEB OOEB ASCIInumbers OOEB 30 31 ds 0123456789 32 33 34 35 36 37 38 39 December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 49 PSoC Designer Assembly Language User Guide 4 13 50 Jump Accumulator JACC Description Arguments JACC expr Conditional Flags Example Jump unconditionally to the address computed by the sum of the Accumulator the 12 bit twos compliment argument and the cur rent PC 1 The current PC value is defined as the Pc value that cor responds to the ROM address of the first byte of the JACC instruction The Accumulator is not affected by this instruction The JACC instruction uses a two byte instruction format where the lower nib ble of the first byte is used for the upper 4 bits of the 12 bit relative address This causes an effective 4 bit opcode Therefore the fol lowing are all valid opcode bytes for the JACC instruction OxEO OxE1 OxE2 0xEF Operation Opcode Cycle
46. User Guide Table A 5 Assembler Directives Summary Symbol Directive Symbol Directive AREA Area ENDM End Macro ASCIZ NULL Terminated ASCII String EQU Equate Label to Variable Value BLK RAM Byte Block EXPORT Export BLKW RAM Word Block IF Start Conditional Assembly DB Define Byte INCLUDE Include Source File DS Define ASCII String LITERAL ENDLITERAL Prevent Code Compression of Data DSU Define UNICODE String MACRO Start Macro Definition DW Define Word ORG Area Origin DWL Define Word With Little Endian Ordering SECTION ENDSECTION Section for Dead Code Elimination ELSE Alternative Result of IF Directive Suspend OR F 0 Suspend and Resume Code Compressor Resume ADD SP 0 ENDIF End Conditional Assembly Table A 6 ASCII Code Table Dec Hex Oct Char Dec Hex Oct Char Dec Hex Oct Char Dec Hex Oct Char 0 00 000 NULL 32 20 040 space 64 40 100 96 60 140 1 01 001 SOH 33 21 041 65 41 101 A 97 61 141 a 2 02 002 STX 34 22 042 7 66 42 102 B 98 62 142 b 3 03 003 ETX 35 23 043 67 43 103 C 99 63 143 c 4 04 004 EOT 36 24 044 68 44 104 D 100 64 144 d 5 05 005 ENQ 37 25 045 69 45 105 E 101 65 145 e 6 06 006 ACK 38 26 046 amp 70 46 106 F 102 66 146 f 7 07 007 BEL 39 27 047 i 71 47 107 G 103 67 147 g 8 08 010 BS 40 28 050 72 48 110 H 104 68 150 h 9 09 011 HT 41 29 051 73 49 111 l 105 69 151 i 10 0A 012 LF 42 2A 052 74 4A 112 J 106 6A 152 j 11 0B 013 VT 43 2B 053 75 4B 113 K 107 6B 153 k 12 0C 014 FF 44 2C 054 76 4C 114 L 108 6C 154 13 oD 0
47. a RUD TERRE T E T ORG 86 5 15 1 EXaFTIDIS aapna Re eee E T ups E E 86 5 17 Section for Dead Code Elimination lontana esta id SECTION ENDSECTION 86 5 17 1 Example NU RA RUN eem TuS 86 5 18 Suspend and Resume Code Compressor Suspend Resume 87 m qa TEXT sisti esa citada discos eor o Ede pid EE iei de EL A 87 Section 6 Compile Assemble Error Mex 89 AB TES UI RII D UU 89 6 2 Preprocessor Errors UT E E 90 6 3 Assembler ETO as oec oi b oe RO Rte eae ba e e scita asi Ea dde 92 6 4 Linker Errors ERR E E Dres 93 6 5 Code Compressor and Dead Code Elimination Error Messages 93 Appendix A Assembly Language Reference Tables 95 l 99 December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 5 PSoC Designer Assembly Language User Guide 6 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 List of Tables Table 1 Internal Registers Table 2 Flag F Register Red LL uL MS E uc dE Table 3 One Byte Instruction Format m PP AQ Table 4 Two Byte Instruction Formats mud uS UE LE e ELT Table 5 Three ber dart died Formats aa xui UMS M DH E C RD ie 18 Table 6 Table 7 Table 8 Table 9 TENURE T Table 10 Desti
48. a ee a al ia et A 79 So DENO BI E ei ay cer rtrene rere rer se trrerrreyerttcrrer yer Tre DB 79 SAEI MC 79 4 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 56 Deine ASG SENG uicti ttt setti vases End Lane i LER LL ELLAS A ERU HR ELA uda DS 80 2 8 1 EXSll ple 1 isse REP p PRI ERE T HO sedan 5 7 Define UNICODE String 5 7 1 Example EE Bide E REE ere rere E RI MEE LE UE 5 9 Dali VIDE ai sciri n to ER HIR TRREV RE RERU AGO ERU AAA EB REV XEYA FER RURAL e ER d 2 8 1 EXGBIS 15 esas con en e edF med jd c E t 5 9 Define Word Little Endian Ordering RT RE DWL 81 5 9 1 Exaile i i erri edes Gaps Made sem T eee errs 5 W Eguate AN eaaa Ea a aaa EQU 82 5 10 1 Example M m icq kcu us d dU 82 SII EO depre EXPORT 82 5 11 1 Example pisces PEA ATRE iude Sie eee ee rere CEP MEMINI 82 5 12 CONC SOMOS Lie ep nb bebo a e ERR re LR ap i iln iF ELSE ENDIF 83 5 12 1 Example errs inion mE eee uuu dun E mci E 83 5053 TROU G Source FP Ie i op pete re Ll AR Rcx Eat d eps rere teers Sette INCLUDE 84 5 13 1 Example e REM iE E ere Tre ree UM 84 5 14 Prevent Code Compression of Data n E ETE LITERAL ENDLITERAL 84 5 TE EXAMS i2 rc e tas ndi TTA E 84 5 15 Macro Defirillorte iiec bodie sx re p ob EE ox ne od ES MACRO ENDM 85 5 15 1 Example maui EEA P TEN EEEE PRENNE M 85 NG Are
49. a value in the X and or A register that must be main tained after the API call then the caller must save push on the stack and then restore pop off the stack them after the call has returned Even though some of the APIs do preserve the X and A register Cypress MicroSystems reserves the right to modify the API in future releases in such a manner as to modify the contents of the X and A registers Therefore it is very important to observe the convention when calling from assembly The C com piler observes this convention Compiling a File into a Library Module Each library module is simply an object file Therefore to create a library mod ule you need to compile a source file into an object file There are several ways that you can create a library Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 3 The PSoC Designer Assembler One method is to create a brand new project Add all the necessary source files that you wish to be added to your custom library to this project You then add a project specific MAKE file action to add those project files to a custom library Let s take a closer look at this method using an example A blank project is created for any type of part since we are only interested in using C and or assembly the Application Editor and the Debugger The goal for creating a custom library is to centralize a set of common functions that can be shared between projects These common fun
50. aded with a zero lt lt lt lt lt CF k 7 6 5 4 3 2 1 0 amp 0 Arguments Operation Opcode Cycles Bytes ASL A r J 0x64 4 1 CF lt A7 A 1 A 6 A 6 A 5 A 5 A4 AA A 3 A3 lt A 2 A 2 Ail A 1 lt A 0 A0 0 ASL expr r 7 0x65 T 2 CF lt ram k 7 ram k ram ASL X expr r 3 0x66 8 2 CF lt ram X k 7 ram X k 7 ram X k 6 ram X k 6 lt ram X k 5 ram X k 5 ram X k 4 ram X k ram X k 4 lt ram X k 3 ram X k 3 lt ram X k 2 ram X k 2 lt ram X k 1 ram X k 1 lt ram X k 0 ram X k 0 lt 0 Conditional Flags CF Set equal to the initial argument s bit 7 value ZF Set if the result is zero cleared otherwise Example 1 mov A Ox7F initialize A with 127 asl A A OxFE CF 0 ZF 0 Example 2 mov OxEB AA initialize RAM OxEB with 0 asl OxEB ram 0xEB 54 CF 1 ZF 0 December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 43 PSoC Designer Assembly Language User Guide 4 5 44 Description Arguments ASR A ASR expr ASR X expr Conditional Flags Example 1 Example 2 Example 3 Arithmetic Shift Right ASR Shifts all bits of the instruction s argument one bit to the right Bit 7 remains the same while bit 0 is shifted into the Ca
51. ble Flash space in bytes by 64 Therefore a 16 KB part would have a hex file with 256 Flash data records 020000040010ea The first two characters 02 indicate that this record has a length of two bytes 4 ASCII charac ters The next four characters 0000 specify the starting address The next two characters 04 indicate that this is an extended linear address The four characters following 04 are the data for this record Because this is an extended linear address record the four characters indicate the value for the upper 16 bits of a 32 bit address Therefore the value of 0x0010 is a 1 MB offset For PSoC microcontroller hex files the extended linear address is used to offset Flash protection data from the Flash data The Flash protection bits start at the 1 MB address data record 1 protection bits For PSoC devices with 16 KB of Flash or less this is the only data record for protection bits data record m protection bits For PSoC devices with more than 16 KB of Flash there will be an additional data record with protec tion bits for each 16 KB of additional Flash 020000040020da This is another extended linear address record This record provides a 1 MB offset from the Flash protection bits absolute address of 2 MB data record checksum This is a two byte data record that stores a check sum for all of the Flash data stored in the hex file The record will always start with 0200000000 and end with the fo
52. ble at http www cypress com Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 See Section 2 The M8C Microprocessor Section 2 The M8C Microprocessor 2 1 Introduction The M8C is a 4 MIPS 8 bit Harvard architecture microprocessor Code select able processor clock speeds from 93 7 kHz to 24 MHz allow the M8C to be tuned to a particular application s performance and power requirements The M8C supports a rich instruction set which allows for efficient low level lan guage support This section covers Internal M8C Registers Address Spaces Instruction Formats Addressing Modes 2 2 Internal Registers The M8C has five internal registers that are used in program execution Fol lowing is a list of the registers Accumulator a Index x Program Counter ec Stack Pointer s Flags F All of the internal M8C registers are 8 bits in width except for the pc which is 16 bits wide Upon reset a x Pc and sp are reset to 0x00 The Flag register F is reset to 0x02 indicating that the z flag is set With each stack operation the sp is automatically incremented or decre mented so that it always points at the next stack byte in RAM If the last byte in the stack is at address oxrr in RAM the Stack Pointer will wrap to RAM December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 13 PSoC Designer Assembly Language User Guide 2 3 address 0x00 It is the firmware developer s responsibility to
53. code The first category of one byte instructions are those that do not update any registers or RAM Only the one byte nop and ssc instructions fit this category While the Program Counter is incremented as these instructions execute they do not cause any other internal M8C registers to be updated nor do these instructions directly affect the register space or the RAM address space The ssc Instruction will cause SROM code to run which will modify RAM and M8C internal registers The second category has only the two puss instructions in it The pusu instruc tions are unique because they are the only one byte instructions that cause a RAM address to be modified This instruction automatically increments the sp The third category has only the Hatt instruction in it The Hat instruction is unique because it is the only single byte instruction that causes a user register to be modified The sar instruction modifies user register space address 0xFF cPU_SCR The final category for single byte instructions are those that cause internal M8C registers to be updated This category holds the largest number of instructions ASL ASR CPL DEC INC MOV POP RET RETI RLC ROMX RRC SWAP These instructions can cause the a x and sp registers or SRAM to be updated Two Byte Instructions The majority of M8C instructions are two bytes in length While these instruc tions can be divided into categories identical to the one byte instruct
54. cremented to 0x00 HALT Halts the execution of the processor The processor will remain halted until a Power On Reset POR Watchdog Timer Reset WDR or external reset XRES event occurs The POR WDR and XRES are all hardware resets which will cause a complete system reset including the resetting of registers to their power on state Watchdog reset will not cause the Watchdog Timer to be dis abled while all other resets will disable the Watchdog Timer Operation Opcode Cycles Bytes reg CPU SCR reg CPU_SCR 1 0x30 9 1 CF Carry Flag unaffected ZF Zero Flag unaffected halt sets STOP bit in CPU SCR register December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 47 PSoC Designer Assembly Language User Guide 4 11 48 Increment INC Description Adds one to the argument The argument s original value is replaced by the new value If the value after the increment is 0x00 the Carry Flag and the Zero Flag will be set original value must have been OxFF Arguments Operation Opcode Cycles Bytes INC A A lt A 1 0x74 4 1 INC X XeX 1 0x75 4 1 INC expr ram k lt ram k 1 0x76 7 2 INC Xtexpr ram X k lt ram X k 0x77 8 2 Conditional Flags CF Set if value after the increment is 0 cleared otherwise ZF Set if the result is zero cleared otherwise Example 1 mov A 0x00 initialize A to 0 or F 0x06 make sure CF and ZF are set 1 inc A A 0x01 CF 0 ZF 0 Example 2 mov A OxFF init
55. ct To view messages in the Build tab of the Output Status window regarding the behavior of your custom process go to Tools gt gt Options gt gt Builder tab and click a check at Use verbose build messages Use the Project gt gt Settings Linker tab fields to add the library modules library path if you want other PSoC Designer projects to link in your custom library December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 37 PSoC Designer Assembly Language User Guide 38 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 4 M8C Instruction Set Section 4 M8C Instruction Set This section of the Assembly Language User Guide describes all M8C instruc tions in detail The M8C supports a total of 256 instructions which are divided into 37 instruction types For each instruction the assembly code format will be illustrated as well as the operation performed by the instruction The microprocessor cycles that are listed for each instruction are for instructions that are not on a ROM Flash page boundary execution If the instruction is located on a 256 byte ROM page boundary an additional microprocessor clock cycle will be needed by the instruction The expr string that is used to explain the assembly code format represents the use of assembler directives which tell the assembler how to cal culate the constant used in the final machine code Note that in the operation equations the machine code constant is
56. ctions or primitives have deterministic inputs and outputs Another goal for creating this custom library is to be able to debug the primitives using a sequence of test instructions e g a regression test in a source file that should not be included in the library No User Modules are involved in this example PSoC Designer automatically generates a certain amount of code for each new project In this example use the generated _main source file to hold regression tests but do not add this file to the custom library Also do not add the generated boot asm source file to the library Essentially all the files under the Source Files branch of the project view source tree go into a custom library except main asm or main c and boot asm Create a file called ocal dep in the root folder of the project The ocal dep file is included by the master Makefile found in the PSoC Designer tools folder The following shows how the Makefile includes local dep found at the bottom of Makefile fthis include is the dependencies include project dep if you don t like project dep use your own include local dep The nice thing about having ocal dep included at the end of the master Make file is that the rules used in the Makefile can be redefined see the Help gt gt Documentation Supporting Documents make pdf_ for detailed informa tion In this example we use this to our advantage The following shows informa
57. ctions ATAL OAOE E Cre pd teh hs Sad Cbr E atria Kn cal 16 2 4 2 TWO Byle INSTUGCHONG qe M skesiasescc IO 24 3 Throe Byte INSIUCtOnS ax ctsisseteceis RI ankenn Latanis EAA EERE Eai 17 2 5 Addressing Modes jor eh E P AET OT PIX Ou ORO SOL OL dI ob T d 20 1 Source NSS siirat ensidnireins Ear CIR dd te EEG bd aia tk P RE ea Kn E 19 s Pc DESI gerina EOM emREhrERI SPUR Shed Eau CRI e DO hPbRDE Sep EpL RCPLODU eer ded 2 0 gd OUNCE indexed ariiraa E vetas cita CO PX ped ah dard n pod QU pd cua uw rl 20 230 Deseo DIECI in ecvid od ci EXE aa dad bed Fond FAC FoU E PRO E OM EbeM EE 20 299 cus iiti TOT TE TET 21 2 5 6 Destination Direct Source Immediate eeesssssssseeeenenneee 21 2 5 7 Destination Indexed Source immediate ene EE EEEE EEE T E Dd 21 25 0 Destination Direct Source DNFOGE iu ipods ii cix a ert ie Feb ree LR RE CO bb ce YE E dE 22 2 9 9 Source Indirect POSE Increment 2ussiso uncta er c etna er Sia etc dic 22 2 5 10 Destination Indirect Post Increment 0 2 ceccceseecececeecesseeceeeceaeeeseeeeeseaaeeeees 23 Section 3 The PSoC Designer Assembler ss 25 nA EC re FC e n NT 25 Bold ESI orai Ge cubes CBeo tab Pte ect HIN FER UDp RAD FEE ELLO tersb oU Cose eme eoe oi R 26 NEUE UA TUORUM C V 27 Seko OP aS a HE 28 i Tod TU TINI U FN E EPRA A N ILATE A TIE EAA E AI A E A EEA E N E T 29 DO EMEN noniine e ET SPAN IS Fle NM Et cance reas aE sd aaa
58. ded by the nearest local or global label or the end of the source file The following example has a single global label called SubFun and a re usable local label called MoreFun Notice that while labels do not include the colon when referenced re usable local labels require that a period precede the label string for all instances Re usable local labels are case sensitive Re usable Local Label EXPORT SubFun mov X 10 SubFun xor reg 00h FFh mov A 5 MoreFun xor reg 04h FFh dec A jnz MoreFun dec X jnz SubFun Mnemonics An instruction mnemonic is a two to five letter string that represents one of the microprocessor instructions All mnemonics are defined in Section 4 M8C Instruction Set There can be 0 or 1 mnemonics per line of a source file Mne monics are not case sensitive December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 27 PSoC Designer Assembly Language User Guide 3 1 3 28 Operands Operands are the arguments to instructions The number of operands and the format they use are defined by the instruction being used The operand format for each instruction is covered in Section 4 M8C Instruction Set Operands may take the form of constants labels dot operator registers RAM or expressions Constants are operands bearing values explicitly stated in the source file Constants may be stated in the source file using one of the radixes listed in Table 17 Table 17 Constants
59. e Formats Example User Accessible Regis reg expr MoV A reg 0x08 register at address 8 ters MOV A reg OU 8 address label OU 8 M8C Registers A OV A 8 move 8 into the accumulator F Que e d set bit 0 of the flags SP MOV SP 8 set the stack pointer to 8 X MOV X 8 pset the MOCAZSU X reg to 8 RAM references are made by enclosing the address or expression in square brackets The assembler will evaluate the expression to create the actual RAM address Table 19 RAM Format Type Formats Example Current RAM Page expr MOV A 0x08 RAM at address 8 MOV A OU 8 address label OU 8 Expressions may be constructed using any combination of labels constants the dot operator and the arithmetic and logical operations defined in Table 20 Table 20 Expressions Precedence Expression Symbol Form 1 Bitwise Complement a 2 Multiplication if a b Division a b Modulo a b 3 Addition a b Subtraction a b 4 Bitwise AND amp a amp b 5 Bitwise XOR a b 6 Bitwise OR a b 7 High Byte of an Address gt gt a 8 Low Byte of an Address lt lt a Only the Addition expression may apply to a relocatable symbol i e an external symbol All other expressions must be applied to constants or sym bols resolvable by the assembler i e a symbol defined in the file Comments A comment starts with a semicolon or a double slash and goes to the end of a line It
60. e label is not visible to another file Another way to export a label is to end the label definition with two colons instead of one Syntax EXPORT label gt is exported ariable EA bss K 1 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 5 Assembler Directives 5 12 Conditional Source IF ELSE ENDIF Description All source lines between the IF and ENDIF or IF and ELSE directives are assembled if the condition is true These statements can be nested Else delineates a not true action for a previous IF directive ENDIF finishes a section of conditional assembly that began with an IF directive Directive Arguments IF value ELSE ENDIF 5 12 1 Example Sections of the source code are conditional Cond1 EQU 1 Cond2 EQU O RG 1000h F Condl DD A 33h F Cond2 DD A FFh NDIF OP ELSE MOV A FFh ENDIF Th xample creates the following code ADD A 33h NOP U U 2 IX gp d PH oO December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 83 PSoC Designer Assembly Language User Guide 5 13 Include Source File Description INCLUDE Used to add additional source files to the file being assembled When an INCLUDE directive is encountered the assembler reads in the specified source file until either another INCLUDE is encountered or the end of file is reached If additional INCLUDES are encountered addi
61. ed and modified assembly language source and or C Compiler files you must compile assemble the files and build the project This is done so PSoC Designer can generate a rom file to be used to debug the MCU program To compile the source files for the current project click the Compile Assemble icon in the toolbar To build the current project click the Build icon in the toolbar Each time you compile assemble files or build the project the Output Status Window is cleared and the current status entered as the process occurs When compiling or building is complete you will see the number of errors Zero errors signifies that the compilation assemblage or build was successful One or more errors indicate problems with one or more files For further infor mation on the PSoC Designer Output Status Window refer to section 3 in the PSoC Designer Integrated Development Environment User Guide The remainder of this section lists all compile assemble and build Linker errors and warnings you might encounter from your code 6 1 Linker Operations The main purpose of the linker is to combine multiple object files into a single output file suitable to be downloaded to the In Circuit Emulator for debugging the code and programming the device Linking takes place in PSoC Designer when a project build is executed The linker can also take input from a library which is basically a file containing multiple object files In producing the output
62. efined token can t be redefined defined token is not a name elif after else elif with no if else after else else with no if endif with no if if too deeply nested line specifies number out of range Bad in if endif Bad syntax for control line Bad token r produced by operator Character constant taken as not signed Could not find include file Disagreement in number of macro arguments Duplicate macro argument EOF in macro arglist Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 6 Compile Assemble Error Messages Table 23 Preprocessor Errors Warnings continued Error Warning EOF in string or char constant EOF inside comment Empty character constant Illegal operator or amp in if elsif Incorrect syntax for defined Macro redefinition Multibyte character constant undefined Sorry too many macro arguments String in if elsif Stringified macro arg is too long Syntax error in else Syntax error in endif Syntax error in if elsif Syntax error in if endif Syntax error in ifdef ifndef Syntax error in include Syntax error in line Syntax error in undef Syntax error in macro parameters Undefined expression value Unknown preprocessor control line Unterminated if ifdef ifndef Unterminated string or char const Table 24 Preprocessor Command Line Errors Error Warning Can t open input file Can t open output file Illegal D or U argument Too many l directives December 8
63. emi ahaeapluita Aca 30 3 3 Map File FolTat 2er enean PE AA ETA ANETE du bU CD A GEM 30 34 ROM File POET seris re tuckb cena as ERR bx ken adc cie EORR t ta pz EU tots CU psa n 6 31 3 5 Intel HEX File Format vemm oreet 31 3 6 Convention for Restoring Internal Registers ELOLE TAE sen dte to E em 34 3 7 Compiling a File into a Library Module coe Section 4 M8C Instruction Set sseeeeeeeee eene nennen nnn 39 SANDER ED i A ima a December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 3 PSoC Designer Assembly Language User Guide 2 PO nre ira ADD 41 AD Bites AIM pe AND 42 44 AIST Shin Lalo 44 nione bh RR HDI BG D RE UE ena RR p AR ASL 43 215 Antec Shin RISE ii rr rr a eO FEE E TE P ve PR etr ipeo HE Ee tR URBE EF IN QUE ASR 44 A CA terc RT TII mE CALL 45 4T Nordeste Compa O crc ree HP SeEpEH E ee RAE IR RR CMP 46 2B Complement Accumulator cde erp b dez Fr eet cR dr a RO Re OIGRT e ded CPL 46 SERE TEC TIO SIEUT DEC 47 BV A MMC HALT 47 Ae e TO ees INC 48 4 12 Relative Tae ISO oic po oer ear ien ono RE sep o Eso den INDEX 49 A 153 dump ACEDETIBEALOT aiat ibt seed ER adidas eee eae Dd ios MODA JACC 50 LECTURE cc JC 51 zw UP pe JMP 52 Ve Sie NO ae mec EE JNC 53 SEE ise T eats ae JNZ 54 A Te dunn JZ 55 SW RE br e m P LCA
64. en a MACRO statement and an ENDM statement are not directly assembled into the program Instead it forms a macro that can later be sub stituted into the code by a macro call Following the MACRO directive is used to call the macro as well as a list of parameters Each time a parameter is used in the macro body of a macro call it will be replaced by the corre sponding value from the macro call Any assembly statement is allowed in a macro body except for another macro statement Within a macro body the expression digit where digit is between 0 and 9 is replaced by the corresponding macro argument when the macro is invoked You cannot define a macro name that conflicts with an instruction mnemonic or an assembly directive Directive Arguments MACRO ENDM lt name gt lt arguments gt 5 15 1 Example A MACRO is defined and used in the source code MACRO MyMacro ADD A 42h MOV X 33h ENDM The Macro instructions are expanded at address 2400 December 8 2003 ORG 2400h MyMacro Document 38 12004 CY Rev A CMS Rev 2 1 85 PSoC Designer Assembly Language User Guide 5 16 Area Origin ORG Description Allows the programmer to set the value of the Program Data Counter during assembly This is most often used to set the start of a table in conjunction with the define directives DB DS and DW The ORG directive can only be used in areas with the ABS mode An operand is required for an ORG directive and may
65. ensure that the stack does not overlap with user defined variables in RAM As shown in Table 2 on page 14 the Flag register has 5 of 8 bits defined The PMODE and xro bits are used to control the active register and RAM address spaces in the PSoC device The C and Z bits are the Carry and Zero flags respectively These flags are affected by arithmetic logical and shift opera tions provided in the M8C instruction The GIE bit is the Global Interrupt Enable When set this bit allows the M8C to be interrupted by the PSoC device s interrupt controller Table 2 Flag F Register M8C Internal Flag Register F 7 6 5 4 3 2 1 0 PMODE XIO e Z GIE With the exception of the F register the M8C internal registers are not accessi ble via an explicit register address PSoC parts in the CY8C25xxx and CY8C26xxx device family do not have a readable r register The oR F expr and anD F expr instructions must be used to set and clear r register bits The internal M8C registers are accessed using special instructions such as MOV A expr MOV X expr SWAP A SP OR F expr JMP The r register may be read by using address oxr in any register bank except in CY8C25xxx and CY8C26xxx devices Address Spaces The M8C microcontroller has three address spaces ROM RAM and regis ters The ROM address space is accessed via its own address and data bus Figure 1 illustrates the arrangement of the PSoC microcontroller address
66. ent Title PSoC Designer Assembly Language User Guide Document Number 38 12004 Revision ECN Issue Date Origin of Change Description of Change da 115170 4 23 2002 Submit to CY Document Control New document to CY Document Con Updates trol Revision Revision 2 0 for CMS customers Misc updates received over the past A HMT few months including code compres sion and the AREA directive and cus tom libraries New directives Distribution External Public Posting None December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 101 PSoC Designer Assembly Language User Guide 102 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003
67. for each directive December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 75 PSoC Designer Assembly Language User Guide 5 1 Area AREA Description Defines where code or data is located in Flash by the Linker The Linker gathers all areas with the same name together from the source files and either concatenates or overlays them depending on the attributes specified All areas with the same name must have the same attributes even if they are used in different modules The following is a complete list of valid key words that can be used with the AREA directive RAM Specifies that data is stored in RAM Only used for variable storage Commonly used with BLK directive ROM Specifies that code or data is stored in Flash ABS Absolute i e non relocatable location for code or data specified by the ORG directive Default value if ABS or REL is not specified REL Allows the linker to relocate the code or data CON Specifies that sequential AREAs follow each other in memory Each AREA is allocated its own memory The total size of the AREA is the sum of all AREA sizes Default value if CON or OVR is not specified OVR Specifies that sequential AREAs start at the same address This is a union of the AREAs The total size of the AREA is the size of the largest area PSoC Designer requires that the bss area be used for RAM variables Directive Arguments AREA name lt RAM ROM gt A
68. g It is recommended that users take advantage of the SSC Macro provided in PSoC Designer to ensure that the debugger recognizes and therefore debugs supervisory operations correctly See separate data sheets for complete device specific options CY8C25xxx 26xxx or CY8C22xxx 24xxx 27Xxx mov X SP get stack pointers current value mov A X move SP to A add A 3 add 3 to SP value mov OxF9 A store SP 3 value in ram 0xF9 KEY2 mov OxF8 Ox3A set ram 0xF9 0x3A KEY1 mov A 2 set supervisory function code 2 ssc call supervisory function 72 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 4 36 Test with Mask Description Arguments TST expr expr TST X expr expr TST REG expr expr TST REG X expr expr Conditional Flags Example December 8 2003 Section 4 M8C Instruction Set TST Calculates a bitwise AND with the value of argument one and argu ment two Argument one s value is not affected by the instruction If the result of the AND is zero the Zero Flag is set otherwise the Zero Flag is cleared The Carry Flag is not affected by the instruc tion Operation Opcode Cycles Bytes ram k amp ky 0x47 8 3 ram X k amp kz 0x48 9 3 reg k4 amp k 0x49 9 3 reg X k amp k Ox4A 10 3 CF Unaffected ZF Set if the result of AND is zero cleared otherwise mov 0x00 0x03 tst 0x00 0x02 CF 0 ZF 0 i e bit 1 is 1 tst 0x00 Ox01 CF 0 ZF 0 i e bit O is
69. gs Example 1 Example 2 Example 3 Computes the bitwise complement of the Accumulator and stores the result in the Accumulator The Carry Flag is not affected but the Zero Flag will be set if the result of the compliment is O i e the original value was OxFF Operation Opcode Cycles Bytes elk 0x73 4 1 CF Unaffected ZF Set if the result is zero cleared otherwise mov A OxFF cpl A A 0x00 ZF 1 mov A O0xA5 cpl A A 0x5A ZF 0 mov A OxFE cpl A A 0x01 ZF 0 46 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 4 9 Decrement Description Arguments DEC A DEC X DEC expr DEC X expr Conditional Flags Example 4 10 Halt Description Arguments HALT Conditional Flags Example Section 4 M8C Instruction Set DEC Subtracts one from the value of the argument and replaces the argument s original value with the result If the result is 1 original value was zero the Carry Flag is set If the result is O original value was one the Zero Flag is set Operation Opcode Cycles Bytes A lt A 1 0x78 4 1 X X 1 0x79 4 1 ram k ram k 1 Ox7A 7 2 ram X k lt ram X k 1 0x7B 8 2 CF Set if the result is 1 cleared otherwise ZF Set if the result is zero cleared otherwise mov OxEB 3 loop2 The loop will be executed 3 times dec OxEB jnz loop2 Jump will not be taken when ZF is set by DEC i e wait until the loop counter 0xEB is de
70. ialize A to 0 and F 0x00 make sure flags are all 0 inc A A 0x00 CF 1 ZF 1 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 4 M8C Instruction Set 4 12 Relative Table Read INDEX Description Places the contents of ROM at the location indicated by the sum of the Accumulator the argument and the current Pc into the Accu mulator This instruction has a 12 bit two s complement offset address relative to the current PC The current PC value is defined as the PC value that corresponds to the ROM address of the first byte of the instruction The INDEX instruction is used to retrieve information from a table to the Accumulator The lower nibble of the first byte of the instruc tion is used as the upper 4 bits of the 12 bit address Therefore all instructions that begin with OxF are INDEX instructions so all of the following are INDEX opcodes OxFO OxF1 O0xF2 0xFF The offset into the table is taken as the value of the Accumulator when the INDEX instruction is executed The maximum readable table size is 256 bytes due to the Accumulator being 8 bits in lengths Arguments Operation Opcode Cycles Bytes INDEX expr A rom k A 2048 lt k lt 2047 OxFx 13 2 Conditional Flags CF Unaffected ZF Set if the byte returned to A is zero Example 0000 OUT REG equ 04h 0000 40 04 nop 0001 50 03 04 mov A 3 0003 FO E6 13 index ASCIInumbers 0005 60 04 05 mov reg O
71. indicates the address of the first byte of information in the record The address field is 16 December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 31 PSoC Designer Assembly Language User Guide bits in length 4 ASCII characters which allows room for 64 kilobytes of data per record Table 21 Intel HEX File Record Format Field Number Field Name Length bytes Description 1 start 1 The only valid value is the colon character 2 length 1 Indicates amount of data from 0 bytes to 255 bytes 3 starting 2 address 4 type 1 00 data 01 end of file 02 extended segment address 03 start segment address 04 extended linear address 05 start linear address record 5 data determined by length field 6 checksum 1 All hex files created by the PSoC Designer Assembler have the structure shown in Table 22 Each row in the table describes a record type used in the 32 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 3 The PSoC Designer Assembler hex file Each record type conforms to the record definitions discussed previ ously Table 22 PSoC Microcontroller Intel HEX File Format Record Description lt data record 1 flash data gt This is the first of many data records in the hex file that contain Flash data lt data record n flash data gt The nth record containing data for Flash last record The total number of data records for Flash data can be determined by dividing the availa
72. ing Directive ASCIZ Example NULL 00h character The string must start and end with quotation marks nw The string is stored character by character in ASCII hex format The back slash character is used in the string as an escape character Non printing characters such as n and V can be used A quotation mark can be entered into a string using the backslash a single quote as V and a backslash V as V Arguments lt character string gt My String is defined with a terminating NULL character MyString ASCIZ My String RAM Block in Bytes BLK Description Directive BLK Example Reserves blocks of RAM in bytes The argument is an expression specifying the size of the block in bytes to reserve The AREA directive must be used to ensure the block of bytes will reside in the correct memory location PSoC Designer requires that the bss area be used for RAM variables Arguments lt size gt A 4 byte variable called MyVariable is allocated ARI EA bss Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 ein Section 5 Assembler Directives MyVariable BLK 4 5 4 RAM Block in Words BLKW Description Reserves a block of RAM The amount of RAM reserved is determined by the size argument to the directive The units for the size argument is words 16 bits PSoC Designer requires that the AREA bss be used for RAM variables Directive Arguments
73. ion address For PSoC devices with more than 256 bytes of RAM the Data Page Write pPw pn regis ter is used to determine which RAM page to use with the destination address Therefore values may be stored in pages other than the current page without changing the Current Page Pointer ce pbR The pointer is always read from the current RAM page For information on the DPR DR and cpp pn registers please see the device data sheet Table 15 Destination Indirect Post Increment Opcode Operand 1 Instruction Destination Address Pointer Destination Indirect Post Increment example Source Code Machine Comments Code MVI 8 A 3F 08 The value in memory at address 8 the indirect address points to a memory location in RAM The Accumulator value is moved into the memory loca tion pointed to by the indirect address The indirect address in memory at address 8 is then incre mented December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 23 PSoC Designer Assembly Language User Guide 24 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 EE eee Section 3 The PSoC Designer Assembler Section 3 The PSoC Designer Assembler Assembly language is a low level language This means its structure is not like a human language By comparison C is a high level language with structures close to those used by human languages Even though assembly is a low level language it is an abstraction created to make programming hardwa
74. ions this Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 2 4 3 Section 2 The M8C Microprocessor would not provide a useful distinction between the three two byte instruction formats that the M8C uses Table 4 Two Byte Instruction Formats Byte 0 Byte 1 4 bit 12 bit relative address opcode 8 bit opcode 8 bit data 8 bit opcode 8 bit address The first two byte instruction format shown in Table 4 is used by short jumps and calls CALL JMP JACC INDEX JC JNC JNZ Jz This instruction format uses only 4 bits for the instruction opcode leaving 12 bits to store the relative desti nation address in a twos complement form These instructions can change pro gram execution to an address relative to the current address by 2048 or 2047 The second two byte instruction format Table 4 is used by instructions that employ the Source Immediate addressing mode 2 5 1 Source Immediate on page 19 The destination for these instructions is an internal M8C register while the source is a constant value An example of this type of instruction would be app a 7 The third two byte instruction format is used by a wide range of instructions and addressing modes The following is a list of the addressing modes that use this third two byte instruction format Source Direct app a 7 Source Indexed ADD a x 71 Destination Direct app 7 a Destination Indexed app x 7 A Source Indirect Post Incremen
75. ll instructions using the Destination Indexed Source Immediate addressing mode are three bytes in length Table 12 Destination Indexed Source Immediate Opcode Operand 1 Operand 2 Instruction Destination Index Immediate Value Destination Indexed Source Immediate examples Source Code Machine Comments Code ADD X7 5 07 07 05 The value in memory at address X 7 is added to the immediate value 5 The result is placed in mem ory at address X 7 MOV REG X 8 6 63 08 06 The immediate value 6 is moved into the register space at address X 8 Destination Direct Source Direct Only one instruction uses this addressing mode The destination address is stored in operand 1 of the instruction The source address is stored in operand 2 of the instruction All instructions using the Destination Direct Source Direct addressing mode are three bytes in length Table 13 Destination Direct Source Direct Opcode Operand 1 Operand 2 Instruction Destination Address Source Address Destination Direct Source Direct example Source Code Machine Comments Code MOV 7 8 5F 07 08 The value in memory at address 8 is moved to memory at address 7 Source Indirect Post Increment Only one instruction uses this addressing mode The source address stored in operand 1 is actually the address of a pointer During instruction execution the pointer s current value is read to determine the address in RAM where the source value will be found The pointer
76. low the colon are two bytes that form the mov a 74 instruction Notice that the assembler converts the constants used in the source file to decimal values and that the machine code is always show in hexidecimal In this case the source code expressed the constant as an octal value 0112 the assembler represented the same value in decimal 74 and the machine code uses hexidecimal 4A Example LST File 0014 mov A 0112 Octal constant OlAF 50 4A MOV A 74 Map File Format A lt project name gt mp file is created each time the assembler completes with out errors or warnings The map file documents where the assembler has placed areas defined by the arza assembler directive and lists the values of global labels also called global symbols Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 3 The PSoC Designer Assembler 3 4 ROM File Format A lt project name gt rom file is created each time the assembler completes with out errors or warnings This file is provided as an alternative to the intel hex file that is also created by the assembler The ROM file does not contain the user defined protection settings for the Flash or the fill value used to initialize unused portions of Flash after the end of user code The ROM file is a simple text file with eight columns of data delimited by spaces The example below is a complete ROM file for a 47 byte program The ROM file does not contain any information abou
77. nation indexed I EEEE E EN E ta nennen uo Table 11 Destination Direct Source Immediate up UE see aa ATE ERT Table 12 Destination Indexed Source medie aeaa 2 Table 13 Destination Direct Source Direct Mou ISI E wine 22 Table 14 Source Indirect Post IncPemsl ile oo ir tenere ex het eee Ie three ter tct eto BO Table 15 Destination Indirect Post Increment cp m ed ener ee Table 16 Five Basic Pari aroha of an Assembly Source File ORTU I Table 17 Table 18 Table 19 l Table 20 pale iy TNR NITE T Table 21 Intel HEX File Record Format Table 22 PSoC Microcontroller Intel HEX File Format e HR dd Table 23 Preprocessor Errors Warnings iaaiaee E Table 24 Preprocessor Command Line Errors cccececsssecccecceeeessaeececcceecesssessseceeeecessnssaaa Table 25 Assembler Errors Warnings EST ECRIRE ERNST A S S Table 26 Assembler Command Line Errors Warnings tnt RAPERE C TADE 2r Linker er Pe m e Oe Tabie AT Pa are Conventions TR PN REPREHEN ERREUR CERERI EORR 95 December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 7 PSoC Designer Assembly Language User Guide 8 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Notation Standards Following is input notation referenced throughout this guide and wherever applicable in the PSoC Designer suite of product documentation Table 1
78. nction B from Function X in the non text Area will not be fixed up All normal user code that is to be compressed must be in the default text Area If you create code in other area for example in a bootloader then it must not call any functions in the text Area However it is acceptable for a function in the text Area to call functions in other areas The exception is the TOP area where the interrupt vectors and the startup code can call functions in the text Area Addresses within the text Area must be not used directly oth erwise If you reference any text area function by address then it must be done indi rectly Its address must be put in a word in the area func lit At runtime you must de reference the content of this word to get the correct address of the function Note that if you are using C to call a function indirectly the compiler will take care of all these details for you The information is useful if you are writing assembly code For further details on enabling and using code compression see December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 77 PSoC Designer Assembly Language User Guide 5 2 5 2 1 5 3 5 3 1 78 PSoC Designer C Language Compiler User Guide Code Compression PSoC Designer Integrated Development Environment User Guide Project Settings NULL Terminated ASCII String ASCIZ Description Stores a string of characters as ASCII values and appends a terminat
79. o many include paths 6 4 Linker Errors Table 27 Linker Errors Warnings Error Warning Address lt address gt already contains a value can t find address for symbol lt symbol gt can t open file lt file gt can t open temporary file lt file gt cannot open library file lt file gt cannot write to lt file gt definition of builtin symbol lt symbol gt ignored ill formed line lt s gt in the listing file multiple define lt name gt no space left in section lt area gt redefinition of symbol lt symbol gt undefined symbol lt name gt unknown output format lt format gt 6 5 Code Compressor and Dead Code Elimination Error Messages X The compiler has failed an internal consistency check This may be due to incorrect input or an internal error Please report the information target new target at Noptm8c c 340 to Cypress MicroSystems support cypressmi cro com C Program Files Cypress MicroSystems PSoC Designer tools make output drc test rom Error 1 Possible Causes a The label in a LITERAL Or sEcTION Segment of code has not been made global using the export directive or a double colon b A LITERAL segment has only a label and no defined data SECTION was not followed by a label LITERAL was not followed by a label December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 93 PSoC Designer Assembly Language User Guide ENDSECTION has no matching SECT
80. of the first byte is used for the upper 4 bits of the 12 bit relative address This causes an effective 4 bit opcode Therefore the following are all valid opcode bytes for the JNC instruction OxDO OxD1 OxD2 0xDF Operation Opcode Cycles PC lt PC 1 k 2048 lt k x 2047 OxDx 5 CF ZF 0000 0000 0003 0006 0008 0009 0009 0009 Carry Flag unaffected Zero Flag unaffected main 55 3C 02 08 mov 3Ch 2 16 3C 02 09 sub 3Ch 2 2 2 0 CF 0 DO 02 05 jnc SubFun jump to SubFun 30 04 halt SubFun 40 04 nop Document 38 12004 CY Rev A CMS Rev 2 1 Bytes 2 ZF 1 53 PSoC Designer Assembly Language User Guide 4 17 Jump if Not Zero JNZ Description If the Zero Flag is not set jump to the address indicated by the sum of the argument and the current Pc 1 The current PC value is defined as the PC value that corresponds to the ROM address of the first byte of the JNZ instruction The JNZ instruction uses a two byte instruction format where the lower nibble of the first byte is used for the upper 4 bits of the 12 bit relative address This causes an effective 4 bit opcode Therefore the following are all valid opcode bytes for the JNZ instruction OxBO OxB1 OxB2 0xBF Arguments Operation Opcode Cycles Bytes JNZ expr PC PC 1 k 2048 lt k lt 2047 OxBx 5 2 Conditional Flags CF Carry Flag unaffected ZF Zero Flag unaffected Example 0000 main
81. ointer in RAM is used to move data between another RAM address and the Accumulator The data pointer is incremented after the data transfer has completed For PSoC microcontrollers with more than 256 bytes of RAM spe cial page pointers are used to allow the MVI instructions to access data in remote RAM pages Two page pointers are available one for MVI read MVI A expr and another for MVI write MVI expr A The data pointer is always found in the current RAM page The page pointers determine which RAM page the data pointer s address will be used At the end of an MVI instruction user code will be operating from the same RAM page as before the MVI instruction was executed Opcode Cycles Bytes Ox3E 10 2 Operation A ram ram k ram k lt ram k 1 ram ram k lt A Ox3F 10 2 ram k lt ram k 1 CF Unaffected ZF Set if A is updated with zero Document 38 12004 CY Rev A CMS Rev 2 1 59 PSoC Designer Assembly Language User Guide Example 1 mov 10h 4 mov 11h 3 mov EBh 10h initialize MVI read pointer to 10h F mvi A EBh A 4 ram EBh 11h mvi A EBh A 3 ram EBh 12h Example 2 mov EBh 10h initialize MVI write pointer to 10h mov A 8 mvi EBh A ram 10h 8 ram EBh 11h mov A 1 mvi EBh A ram 11h 2 1 ram EBh 12h Multi Page Example 3 mov reg CPP DR 2 set Current Page Pointer to 2 mov 10n 4 ram 2 10h 4 mov 11h 3 ram 2 11h 3 mov reg
82. owed by two 8 bit addresses The first address is the destination address in RAM while the second address is source address in RAM The following is an example of this instruction vov 7 5 For more information on addressing modes see 2 5 Addressing Modes on page 18 Addressing Modes The M8C has ten addressing modes Source Immediate Source Direct Source Indexed Destination Direct Destination Indexed Destination Direct Source Immediate Destination Indexed Source Immediate Destination Direct Source Direct Source Indirect Post Increment Destination Indirect Post Increment Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 2 5 1 2 5 2 Section 2 The M8C Microprocessor Source Immediate For these instructions the source value is stored in operand 1 of the instruc tion The result of these instructions is placed in either the M8C a r or x regis ter as indicated by the instruction s opcode All instructions using the Source Immediate addressing mode are two bytes in length Table 6 Source Immediate Opcode Operand 1 Instruction Immediate Value Source Immediate examples Source Code Machine Comments Code ADD A 7 01 07 The immediate value 7 is added to the Accumula tor The result is placed in the Accumulator MOV X 8 57 08 The immediate value 8 is moved into the X register AND F 9 70 09 The immediate value of 9 is logically ANDed with the F register and the res
83. ped off the stack first followed by the SP being decremented by one Next the upper 8 bits of the PC are popped off the stack followed by a decrement of the sP Neither Carry or Zero Flag is affected by this instruction For PSoC devices with more than 256 bytes of RAM the stack is confined to a single designated stack page defined in the device data sheet The M8C automatically selects the stack page as the source for the pop during the RET instruction Therefore an RET instruction may be issued in any RAM page After the RET has completed user code will be operating from the same RAM page as before the RET instruction was executed Operation Opcode Cycles Bytes SP SP 1 un 8 PC 7 0 lt ram SP SP amp SP 1 PC 15 8 lt ram SP CF Unaffected by this instruction ZF Unaffected by this instruction 0000 main 0000 90 02 11 call SubFun 0002 40 04 nop 0003 30 04 halt 0004 0004 SubFun 0004 40 04 nop 0005 TF 08 ret The ret instruction will set the PC to 0x0002 which is the starting address of the first instruction after the ca11 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 4 M8C Instruction Set 4 28 Return from Interrupt RETI Description Arguments RETI Conditional Flags Example The last three bytes placed on the stack are used to change the F register and the Pc The first byte removed from the stack is used to restore the F register The SP
84. pported Move Description Arguments MOV X SP MOV A expr MOV A expr MOV A Xtexpr MOV expr A MOV X expr A MOV expr expr MOV X expr expr MOV X expr MOV X expr MOV X X expr MOV expr X MOV A X MOV XA MOV A reg expr MOV A reg X expr MOV expr expr MOV REG expr A MOV REG X expr A MOV REG expr expr MOV REG X expr expr Condition Flags CF ZF Example mov mov Document 38 12004 CY Rev A CMS Rev 2 1 Operation X lt SP A lt k A lt ram k A lt ram X k ram k lt A ram X k A ram k k ram X k k X k X ram k Xe ram X k ram k lt X A lt X X lt A A reg k A lt reg X k ram k ram k reg k lt A reg X k lt A reg k k reg X ki lt k Carry Flag unaffected Opcode Ox4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 Ox5A 0x5B 0x5C 0x5D Ox5E Ox5F 0x60 0x61 0x62 0x63 Cycles Bytes 4 1 4 2 5 2 6 2 5 2 6 2 8 3 9 3 4 2 6 2 7 2 5 2 4 1 4 1 6 2 7 2 10 3 5 2 6 2 8 3 9 3 Set if A is the destination and the result is zero A 0x01 A 0x00 accumulator will equal 1 accumulator will equal 0 ZF 0 ZF 1 December 8 2003 4 22 Description Arguments MVI A expr MVI expr A Conditional Flags December 8 2003 Move Indirect Post Increment to Memory Section 4 M8C Instruction Set MVI A data p
85. re easier for humans Therefore this abstraction must be eliminated before an input in a form native to the microprocessor can be generated An assembler is used to convert the abstractions used in assembly language to machine code that the microprocessor can operate on directly This section will cover all of the information needed to use the PSoC Designer Assembler For information on generating source code in PSoC Designer see the PSoC Designer Integrated Development Environment User Guide 3 1 Source File Format Assembly language source files for the PSoC Designer Assembler have five basic components as listed in Table 16 Each line of the source file may hold a single label mnemonic comment or directive Multiple operands or expres sions may be used on a single source file line The maximum length for a line is 2 048 characters including spaces and the maximum word length is 256 characters A word is a string of characters surrounded by spaces Table 16 Five Basic Components of an Assembly Source File Component Description Label Symbolic name followed by a colon Mnemonic Character string representing an M8C instruction Operand Arguments to M8C instructions Comment May follow operands or expressions and starts in any column if first non space character is either a C style comment or semi colon Directive A command interpreted by the assembler to control the generation of machine code Avoid use of
86. represented by k k and k3 While the instruction mnemonics are often shown in all capital letters the PSoC Designer Assembler ignores case for directives and instructions mne monics However the assembler does consider case for user defined symbols i e labels The remainder of this section is divided into 37 sub sections arranged in alpha betical order according to the instruction types mnemonic Information about individual M8C instructions is also available via PSoC Designer Online Help Pressing the F1 key will cause the online help sys tem to search for the word at the current insertion point in a source file If your insertion point is an instruction mnemonic pressing F1 will direct you to information about that instruction December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 39 PSoC Designer Assembly Language User Guide 4 1 40 Add with Carry Description Arguments ADC A expr ADC A expr ADC A Xtexpr ADC expr A ADC X expr A ADC expr expr ADC X expr expr Conditional Flags Example 1 Example 2 ADC Computes the sum of the two operands plus the carry value from the Flag register The first operand s value is replaced by the com puted sum If the sum is greater than 255 the Carry Flag is set in the Flag register If the sum is zero the Zero Flag is set in the Flag register Operation Opcode Cycles Bytes A A k CF 0x09 4 2 A A RAM K C
87. rry Flag gt gt gt gt gt gt gt Ls 7 6 5 4 3 2 1 0 L 3 CF Operation Opcode Cycles Bytes 0x67 4 1 CF lt A 0 A 0 lt A 1 A 1 lt A2 AAD CAS A 3 AL AM eA A 5 A 6 A 6 A7 r E 0x68 T 2 CF ram k 0 ram k 0 lt ram k 1 ram k 1 lt ram k 2 ram k ram k 2 lt ram k 3 ram k 3 lt ram k 4 ram k 4 lt ram k 5 ram k 5 lt ram k 6 jram k 6 lt ram k 7 F 0x69 8 2 CF lt ram X k 0 ram X k 0 lt ram X k 1 ram X k 1 lt ram X k 2 ram X k ram X k 2 lt ram X k 3 ram X k 3 lt ram X k 4 ram X k 4 lt ram X k 5 ram X k 5 ram X k 6 jram X k 6 lt ram X k 7 CF Set if LSB of the source was set before the shift else cleared ZF Set if the result is zero cleared otherwise mov A 0x00 Pinitialize A to 0 and F 0x00 make sure all flags are cleared asr A A 0 CF 0 ZF 1 mov A OxFF Pinitialize A to 255 and F 0x00 make sure all flags are cleared asr A A OxFF CF 1 ZF 0 mov A OxAA initialize A to 170 and F 0x00 make sure all flags are cleared asr A A 0xD5 CF 0 ZF 0 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 4 6 Call Function Description Arguments CALL expr Conditional Flags Example December 8 2003 Section 4 M8C Instruction Set CALL Adds the signed argument to the current
88. ruction execution and the second argument s value at bit position 2 i e F 2 and expr 2 Forthe OR F expr instruction the Zero Flag is handled the same as the Carry Flag in that it is changed as a result of the logical OR of the Zero Flag s value at the beginning of instruction execution and the value of the second arguments value at bit position 1 i e F 1 and expr 1 However for all other OR instructions the Zero Flag will be set or cleared based on the result of the logical OR operation If the result of the OR is that all bits are zero the Zero Flag will be set otherwise the Zero Flag is cleared Note that OR or AND or XOR as appropriate is a read modify write instruction When operating on a register that register must be of the read write type Bitwise OR to a write only register will generate nonsense Operation Opcode Cycles Bytes A A k 0x29 4 2 A lt A ram k Ox2A 6 2 A lt A ram X k 0x2B 7 2 ram k lt ram k A 0x2C T 2 ram X k lt ram X k A 0x2D 8 2 ram k lt ram k k 0x2E 9 3 ram X k ram X ki k 0x2F 10 3 reg k reg k k 0x43 9 3 reg X k reg X k4ljk2 0x44 10 3 F lt Fik 0x71 4 2 Document 38 12004 CY Rev A CMS Rev 2 1 61 PSoC Designer Assembly Language User Guide Conditional Flags Example 1 Example 2 CF Unaffected unless F is destination ZF Set if the result is zero cleared otherwise unless F is desti nation 0x00 Ox
89. s Bytes PC lt PC 1 k A OxEx 7 2 CF Unaffected ZF Unaffected 0000 main 0000 50 03 mov A 3 set A with jump offset 0002 EO 01 jacc SubFun Program execution will jump to address 0x0007 halt 0004 SubFun 0004 40 nop 0005 40 nop 0006 40 nop 0007 30 halt Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 4 14 Jump if Carry Description Arguments JC expr Conditional Flags Example Section 4 M8C Instruction Set JC If the Carry Flag is set jump to the sum of the relative address argument and the current PC 1 The current PC value is defined as the PC value that corresponds to the ROM address of the first byte of the JC instruction The Jc instruction uses a two byte instruction format where the lower nibble of the first byte is used for the upper 4 bits of the 12 bit relative address This causes an effective 4 bit opcode Therefore the following are all valid opcode bytes for the Jc instruction OxCO OxC1 OxC2 0xCF Operation Opcode Cycles Bytes PC PC 1 k 2048 lt k lt 2047 OxCx 5 2 CF Carry Flag unaffected ZF Zero Flag unaffected 0000 main 0000 55 3C 02 mov 3Ch 2 0003 16 3C 03 sub 3Ch 3 2 2 0 CF 1 ZF 0 0006 CO 02 jc SubFun CF 1 jump to SubFun 0008 30 halt 0009 0009 SubFun 0009 40 nop December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 51 PSoC Designer Assembly Language User Guide 4 15 52 Jump Description
90. scription Stores a string of characters as UNICODE values with little ENDIAN byte order The string must start and end with quotation marks The string is stored character by character in UNICODE format Each char acter in the string is stored with the low byte followed by the high byte The backslash character is used in the string as an escape character Non printing characters such as M and Vr can be used A quotation mark can be entered into a string using the backslash a single quote as V and a backslash as V Directive Arguments DSU lt character string gt 5 7 1 Example My String is defined with little endian byte order MyString DSU My String 80 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 5 Assembler Directives 5 8 Define Word DW Description Reserves two byte pairs of ROM and assigns the specified words to each reserved byte This directive is useful for creating tables in ROM The arguments may be constants or labels Only the length of the source line limits the number of arguments in a DW statement Directive Arguments DW lt value1 gt value2 valuen 5 8 1 Example 6 bytes are defined starting at address 2000 MyNum EQU 3333h ORG 2000h MyTable DW 1111h 2222h MyNum 5 9 Define Word Little Endian Ordering DWL Description Reserves two byte pairs of ROM and assigns the specified words to each reserved byte
91. spaces The ROM address space is composed of the Supervisory ROM and the on chip Flash program store Flash is organized into 64 byte blocks The user need not be concerned with program store page boundaries as the M8C auto matically increments the 16 bit pc on every instruction making the block boundaries invisible to user code Instructions occurring on a 256 byte Flash page boundary with the exception of jump instructions incur an extra M8C clock cycle as the upper byte of the rc is incremented Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 2 4 Section 2 The M8C Microprocessor The register address space is used to configure the PSoC device s program mable blocks It consists of two banks of 256 bytes each To switch between banks the xro bit in the Flag register is set or cleared set for Bank1 cleared for BankO The common convention is to leave the bank set to BankO xro cleared switch to Bank1 as needed set xro then switch back to BankO Random Access Memory RAM is broken into 256 byte pages For PSoC microcontrollers with 256 bytes of RAM or less the program stack is stored in RAM page 0 For PSoC microcontrollers with 512 bytes of RAM or more the stack is constrained to a single RAM page For information on RAM configura tion in a specific device refer to the device s data sheet
92. t mvr a 71 Destination Indirect Post Increment mvi 7 A For more information on addressing modes see 2 5 Addressing Modes on page 18 Three Byte Instructions The three byte instruction formats are the second most prevalent instruction formats These instructions need three bytes because they either move data between two addresses in the user accessible address space registers and December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 17 PSoC Designer Assembly Language User Guide 2 5 RAM or they hold 16 bit absolute addresses as the destination of a long jump or long call Table 5 Three Byte Instruction Formats Byte 0 Byte 1 Byte 2 8 bit opcode 16 bit address MSB LSB 8 bit opcode 8 bit address 8 bit data 8 bit opcode 8 bit address 8 bit address The first instruction format shown in Table 5 is used by the row and caL instructions These instructions change program execution unconditionally to an absolute address The instructions use an 8 bit opcode leaving room for a 16 bit destination address The second three byte instruction format shown in Table 5 is used by the fol lowing two addressing modes Destination Direct Source Immediate app 7 5 Destination Indexed Source Immediate app x 7 5 The third three byte instruction format is for the Destination Direct Source Direct addressing mode which is used by only one instruction This instruction format uses an 8 bit opcode foll
93. t where the data should be located in Flash By convention the data in the ROM file starts at address 0x0000 in Flash For the example below only addresses 0x0000 through 0x002E of the Flash have assigned values according to the ROM file Example ROM File 80 5B 00 00 7E 00 00 00 7E 00 00 00 7D 02 62 7E 7E 00 00 00 7D 01 EF 7E 91 73 90 FE 90 89 90 14 3D 7F 60 3A 5B 60 3E 7F 3F 00 3D FF 3E CC FF 3 5 Intel HEX File Format The Intel HEX file created by the assembler is used as a platform independent way of distributing all of the information needed to program a PSoC microcon troller In addition to the user data created by the assembler the hex file also contains the protection settings for the project that will be used by the pro grammer The basic building block of the Intel HEX file format is called a record Every record consists of six fields as shown in Table 21 All fields except for the start field represent information as ASCII encoded hexidecimal This means that every 8 bits of information are encoded in two ASCII characters The start field is one byte in length and must always contain a colon The length field is also one byte in length and indicates the number of bytes of data stored in the record Because the length field is one byte in length the maxi mum amount of data stored in a record is 255 bytes which would require 510 ASCII characters in the hex file The starting address field
94. ter If the sum is zero the Zero Flag is set in the Flag register otherwise the Zero Flag is cleared Operation Opcode Cycles Bytes A A K 0x11 4 2 A A ram k 0x12 6 2 A A ram X k 0x13 7 2 ram k lt ram k A 0x14 7 2 ram X k lt ram X k A 0x15 8 2 ram k lt ram k k 0x16 9 3 ram X k 4 ram X k k 0x17 10 3 CF ZF Set if treating the numbers as unsigned the result lt 0 cleared otherwise Set if the result is zero cleared otherwise A 0 set accumulator to zero F 0x04 set carry flag A 12 accumulator value is now OxF4 0x39 2 initialize ram 0x39 0x02 l 0x40 FFh initialize ram 0x40 0xff 0x40 ram 0x40 0x00 CF 1 0x39 0 ram 0x39 0x02 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 4 34 Swap Description Arguments SWAP A X SWAP _ A expr SWAP X expr SWAP A SP Conditional Flags Section 4 M8C Instruction Set SWAP Each argument is updated with the other argument s value The Zero Flag is set if the Accumulator is updated with zero else the Zero Flag is cleared The swap X expr instruction does not affect either the Carry or Zero Flags Operation Opcode tex 0x4B XA Act Cycles Bytes 5 1 t ram k 0x4C 7 2 ram k lt A Act t lt ram k Ox4D T 2 ram k lt X Xet t lt SP SP lt A Act Ox4E 5 1 CF Carry Flag unaffected ZF Set if Accumulator is cleared Example mov A 0
95. tion from example ocal dep t eme Cub Paste to your loosl dep File define Add To MyCustomLib CRLF S LIBCMD a PSoCToolsLib a library file December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 35 PSoC Designer Assembly Language User Guide 36 endef obj 0 asm project mk ifeq ECHO COMMANDS novice echo call correct path endif S ASMCMD INCLUDEFLAGS DEFAULTASMFLAGS ASM FLAGS o 0 S call correct_path lt S foreach library file filter out obj main o 8 Add To MyCustomLib obj 0 c project mk ifeq ECHO COMMANDS novice echo call correct path endif CCMD S CFLAGS S CDEFINES S INCLUDEFLAGS S DEFAULTCFLAGS o call correct_path lt S foreach library file filter out obj main o 8 Add To MyCustomLib gocce Engl Dub The rules e g obj 0 asm project mk and obj 0 c project mk in the ocal dep file shown above are the same rules found in the master Makefile with one addition each The addition in the redefined rules is to add each object target to a library called PSoC ToolsLib a Let s look closely at this addition S foreach library file filter out obj main o 8 Add To MyCustomLib The MAKE keyword foreach causes one piece of text the first argument to be used repeatedly each time with a different substitution performed on it
96. tional source files are read in When an end of file is encountered the assembler resumes reading the previous file Specify the full or relative path to the file if the source file does not reside in the current directory Directive INCLUDE lt file name gt 5 13 1 Example Arguments Three files are included into the source code INCLUDE MyIncludel inc INCLUDE MyIncludeFilesMMyInclude2 inc INCLUDE C MyGlobalIncludeFiles MyInclude3 inc 5 14 Prevent Code Compression of Data LITERAL ENDLITERAL Used to avoid code compression of the data defined between the LIT directives For the code compressor to function n ROM with ASCIZ DB DS DSU DW or DWL must use this ERAL directive must be followed by an exported global directive resumes code compression Description ERAL and ENDLITERA all data defined i directive The LIT label The ENDLITERA Directive LITERAL lt none gt ENDLIT ERAL 5 14 1 Example Syntax Code compression is suspended for the data table Export DataTable LITERAL DataTable DB Olh 02h 03h ENDLITERAL 84 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 5 Assembler Directives 5 15 Macro Definition MACRO ENDM Description Used to specify the start and end of a macro definition The lines of code defined betwe
97. ult is placed in the F regis ter Source Direct For these instructions the source address is stored in operand 1 of the instruc tion During instruction execution the address will be used to retrieve the source value from RAM or register address space The result of these instruc tions is placed in either the M8C a or x register as indicated by the instruction s opcode All instructions using the Source Direct addressing mode are two bytes in length Table 7 Source Direct Opcode Operand 1 Instruction Source Address Source Direct examples Source Code Machine Comments Code ADD A 7 02 07 The value in memory at address 7 is added to the Accumulator and the result is placed into the Accu mulator MOV A REG 8 5D 08 The value in the register space at address 8 is moved into the Accumulator December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 19 PSoC Designer Assembly Language User Guide 2 5 3 2 5 4 20 Source Indexed For these instructions the source offset from the x register is stored in operand 1 of the instruction During instruction execution the current x register value is added to the signed offset to determine the address of the source value in RAM or register address space The result of these instructions is placed in either the M8C a or x register as indicated by the instruction s opcode All instructions using the Source Indexed addressing mode are two bytes in length Table 8 So
98. ur characters that represent the two byte checksum 00000001ff This is the end of file record The length and start ing address fields are all zero The type field has a value of 0x01 and the checksum value will always be Oxff December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 33 PSoC Designer Assembly Language User Guide 3 6 3 7 34 The following is an example of PSoC device hex file for a very small program Example Code mov A reg 0x04 inc A mov reg 0x04 A Example ROM File 5D 04 74 60 04 Example Hex File 40000000540474600430303030303030303030303030303030303 030303030303030303030303030303030303030303030303030303 0303030303030303030303030303077 40004000303030303030303030303030303030303030303030303 030303030303030303030303030303030303030303030303030303 0303030303030303030303030303080 Records removed to make example compact 403 c000303030303030303030303030303030303030303030303 030303030303030303030303030303030303030303030303030303 03030303030303030303030303030c1 020000040010ea 40000000 fffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffffffffffffffffffffffffffffffff fffffffffffffffffffffffffffff00 020000040020da 020000000049b5 00000001ff Convention for Restoring Internal Registers When calling PSoC User Module APIs and library functions it is the caller s responsibility to preserve the A and X registers This means that if the current context of the code has
99. urce Indexed Opcode Operand 1 Instruction Source Index Source Indexed examples Source Code Machine Comments Code ADD A X 7 03 07 The value in memory at address X 7 is added to the Accumulator The result is placed in the Accu mulator MOV X X 8 59 08 The value in RAM at address X 8 is moved into the X register Destination Direct For these instructions the destination address is stored in the machine code of the instruction The source for the operation is either the M8C a or x register as indicated by the instruction s opcode All instructions using the Destination Direct addressing mode are two bytes in length Table 9 Destination Direct Opcode Operand 1 Instruction Destination Address Destination Direct examples Source Code Machine Comments Code ADD 7 A 04 07 The value in the Accumulator is added to memory at address 7 The result is placed in memory at address 7 The Accumulator is unchanged MOV REG 8 A 60 08 The Accumulator value is moved to register space at address 8 The Accumulator is unchanged Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 2 The M8C Microprocessor 2 5 5 Destination Indexed For these instructions the destination offset from the x register is stored in the machine code for the instruction The source for the operation is either the M8C a or x register or an immediate value as indicated by the instruction s opcode All instructions using the
100. value at bit position 2 i e F 2 and expr 2 Forthe AND F expr instruction the ZF is handled the same as the CF in that it is changed as a result of the logical AND of the ZF s value at the beginning of instruction execution and the value of the second argument s value at bit position 1 i e F 1 and expr 1 However for all other AND instructions the Zero Flag will be set or cleared based on the result of the logical AND operation If the result of the AND is that all bits are zero the Zero Flag will be set otherwise the Zero Flag Is cleared Operation Opcode Cycles Bytes AcA amp k 0x21 4 2 A A amp ramik 0x22 6 2 A A amp ram X k 0x23 1 2 ram k ram k amp A 0x24 7 2 ram X k lt ram X k amp A 0x25 8 2 ram k lt ram k amp k 0x26 9 3 ram X kj lt ram X ky amp k 0x27 10 3 reg k reg k amp kp 0x41 9 3 reg X k reg X ky amp ky 0x42 10 3 Fc F amp k 0x70 4 2 CF Affected only by the AND F expr instruction ZF Set if the result is zero cleared otherwise AND F expr Will set this flag as a result of the AND opera tion and A 0x00 A 0 CF unchanged ZF 1 and F 0x00 F 0 therefore CF 0 ZF 0 Document 38 12004 CY Rev A CMS Rev 2 1 December 8 2003 Section 4 M8C Instruction Set 4 4 Arithmetic Shift Left ASL Description Shifts all bits of the instruction s argument one bit to the left Bit 7 is loaded into the Carry Flag and bit 0 is lo
101. with examples Section 3 The PSoC Designer Assembler Provides assembly language source syn tax including labels mnemonics oper ands expressions and comments Section 4 M8C Instruction Set Provides a detailed list of all instructions Section 5 Assembler Directives Provides a detailed list of all directives Section 6 Compile Assemble Error Messages Provides several lists of compile assem bler related errors and warnings December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 11 PSoC Designer Assembly Language User Guide 1 3 1 4 Product Updates The Cypress web site http www cypress com always has the most up to date information available about Cypress MicroSystems products Please visit the web site for the latest version of PSoC Designer the industry leading soft ware development tool for PSoC devices PSoC Designer is provided free of charge You may also order PSoC Designer on CD ROM by contacting your local distributor Support Support for Cypress MicroSystems products is available free at http www cypress com Resources include User Discussion Forums Application Notes CYPros Consultants listing TightLink Technical Support Email Knowl edge Base Tele Training seminars and contact information for Support Tech nicians Cypress MicroSystems was established as a subsidiary of Cypress Semicon ductor Corporation NYSE CY in the fourth quarter of 1999 PSoC related support is also availa
102. x30 swap A SP SP 0x30 A equals previous SP value December 8 2003 Document 38 12004 CY Rev A CMS Rev 2 1 71 PSoC Designer Assembly Language User Guide 4 35 System Supervisor Call SSC Description The System Supervisor Call instruction provides the method for users to access pre existing routines in the Supervisor ROM The supervisory routines perform various system related functions The PC and F registers are pushed on the stack prior to the execution of the supervisory routine All bits of the Flag register are cleared before any supervisory routine code is executed therefore inter rupts and page mode are disabled All supervisory routines return using the RETI instruction causing the PC and F register to be restored to their pre supervisory routine state Supervisory routines are device specific please reference the data sheet for the device you are using for detailed information on the available supervisory routines Arguments Operation Opcode Cycles Bytes SSC ram SP lt PC 15 8 0x00 15 1 SP lt SP 1 ram SP lt PC 7 0 SP SP 1 ram SP lt F PC lt 0x0000 F lt 0x00 Conditional Flags CF Unaffected ZF Unaffected Example The following example is one way to set up an SSC operation for the CY8C25xxx and CY8C26xxx PSoC devices PSoC Designer uses the signature created by the following lines of code to recog nize supervisory system calls and configures the In Circuit Emula tor for SSC debuggin

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