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1. 11 70 81071 39 91071639 BACKPLANE SLOT40 44 BACKPLANE 2 47 4 61 5 9 2 56 7 25 8 45 270775 2 57 5 24 1 80 3 19 7 18 3 26 011877 4 21 3 22 2 98 011477 DC LOADSIKWLIL CPU 2 51 5 15 2 33 4 701510159 2 111 2 79 5 15 3 32 QFT SLOTMOPREV Jj BVO SBN UU EAD OUI fU gt e pa gos dee Pe DOO Me ee 7 45 2 36 3 15 1 01 011477 RC11 4 16 5 20 04 10 092375 RF11 5 12 7 313 6 80 101375 11 6 87 5 32 6 51 090575 1190 010 1 9 19 10 7 8 29 690575 1 NEW 3 90 1 9 2 78 090575 5 56 4 97 1 92 121576 RL11 6 79 4 790 0 62 121576 RP11eC OR E RX41 3 19 4 97 2 78 121874 2 15 2 43 2 94 7 90 7 22 6 69 4 62 3 22 5 11 4 79 6 44 7 59 6 05 3 50 2 65 091975 122074 102974 121576 292275 121576 9 0099 9 EU P mm p m mh e omm mmt 7641 7 1 6 92 TERMINATOR 938 0 961 0 8 1 5 67 8 1 5 32 TMB11 6 4 11 TR 9 F 5 1 1 68 560 5 1 2 19 NOTES 1 19977 1 OPTIMIZE NPR DEVICES SEQUENCE t 1 0 7 11 7 11 RISA RJPQA RKG11 RISA RP1IC DMCTICIMB TJUIO RF11 DMC 1 56KD DH11 2 MEANS DATA IS SUSPICIDUS 3 FOREIGN DEVICES 4 YOU POURT SOME AF THE VALUES IN THE TABLE PLEASE CONTACT CHIH LI PK3 2 817 OR X5229 C
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3. TBBLUP 16 AS Please note the following information carefully 1 If the sector size of a device is larger than DBS TDBS is simply product of the instantaneous data transfer rate of the device and the DBS of the device controller For example the sector size of 04 is 256 words DBS 66 words and the instantaneous data transfer rate 15 2 48 us word so TDBS 2 48 X 66 164 If the sector size of a device is smaller than DBS the sector gap and interleaved sector and gap if any must be accounted for to compute TDBS The situation can be clarified better with the examples that follow RS03 has sectors of 64 words sector gaps of 25 6 us and an instantaneous data transfer rate of 3 6 us word Its DB or silo has two more words than sector therefore two words must be gotten to from the next sector Sector noninterleaved 4ls wd TDBS 3 6 X 64 25 6 3 6 2 263 us Sector interleaved 8 us wd TDBS 3 6 X 64 25 6 X 2 3 6 2 519 us NOTE Within category 2 devices with greater T1 should be placed after devices with smaller T1 All category 2 devices should be placed before category 1 devices with NPR rate less than 1 7 kHz except for asyn chronous communication devices e g DH11 which have great latency tolerance capacity DH11 can be placed in rear of all other devices 2 4 4 BR Devices the BR devices should be placed after NPR devices However sometimes for convenience sake
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5. THE switches and L E D are labeled on the M9803 Module NOTE If SACK turnaround is enabled tha M9308 must be used at the electrical END of the bus 2607 Figure 4 17 M9308 SACK Turnaround Logic 4 6 Modifying the M930 l 2 On side 2 of the M930 cut etch at pin AA2 On side 2 of the M930 cut etch at pin BA2 Attach one end of a 4 57 m 10 ft piece of No 16 gauge or larger insulated wire to the etch as indicated in Figure 4 18 step 3 This will be the plus lead to the variable power supply Attach one end of a 4 57 m 10 ft piece of No 16 gauge or larger insulated wire to the etch as indicated in Figure 4 18 step 4 This will be the minus lead to the variable power supply 4 22 1 2608 Figure 4 18 M930 Modification Example 4 6 3 Procedure for Use Turn all system power off 2 Connect modified terminators to the variable power supply double check polarity 3 Remove system M930 terminators from Unibus 4 Install modified terminators in system where standard terminators were 5 Turn on variable power supply and adjust output to 5 V 6 Turn on system power 7 Proceed with bus margining as described in Paragraph 4 3 4 23 5 UVM TA TESTER 51 UVM TA OVERVIEW This chapter provides DIGITAL Field Service personnel with sufficient information to operate and maintain the Unibus Voltage Margin Tester UVM TA and use it to troubleshoot Unibus Pr
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7. system do not guess Refer to the module utilization prints to determine which terminators go with which bus 4 2 3 Grant Line Termination The grant lines on the Unibus represent a special case of termination and assertion levels high true Grant lines may not always run from one physical end of the bus to the other The Grant line is broken at each device wired to it and repropagated if that device is not requesting see Figure 4 8 It should be noted that changing the bus quiescent levels at the terminator will not affect grant lines which have been repropagated To measure the quiescent level of grant lines or to observe grant line waveforms it necessary to check at the specific point of interest DEVICE B M930 TERMINATORS CP 2598 CHANGING QUIESCENT LEVELS BY CHANGING TERMINATOR VOLTAGE OR NETWORK DOES NOT AFFECT GRANT LINES WHICH HAVE BEEN REPROPAGATED Figure 4 8 Grant Line Bus Margining Technique 4 3 HI LO TERMINATOR BUS MARGINING The Hi Lo Terminator cards see Figure 4 9 are designed to test the high and low bus margining voltages by varying the terminator network rather than varying the voltage when using the UVM TA tester The M930 terminators must be removed from the system under test and be replaced by M9304 low margin or by the M9304 Y A high margin terminator cards There is a special terminator used in the 11 35 and 11 40 processors which combines the functions of a terminator and a unibus jum
8. LOADS SEMI LUMP LOAD WITH 20 AC UNIT LOADS CP 2574 Figure 2 15 Skewed Cable Length Violation Suppose that the length of cable no 1 equals the length of cable no 2 This violates Rule No 4 In this case the affected lumped load will see the following waveform Figure 2 16 when its driver unasserts the bus _ 8140 THRESHOLD ER 7 as DRIVER REFLECTION REFLECTION NET WAVEFORM WAVEFORM FROM END OF FROM END OF AT AFFECTED CABLE 1 CABLE 42 LUMPED LOAD CP 2575 Figure 2 16 Skewed Cable Length Violation Waveform Example The reflection in this waveform crosses 8640 threshold and may cause failure best way to implement Rule No 4 in this example is to increase the length of either cable no 1 or cable no 2 by 1 52 m 5 ft Suppose the length of cable no 2 is increased by 1 52 m 5 ft This violates Rule No 5 because this is the end with the smaller lumped load In this case the affected lumped load will see the following waveform Figure 2 17 when its driver unasserts the bus 8640 THRESHOLD m ME V t2 t i t2 i t2 DRIVER REFLECTION REFLECTION NET WAVEFORM WAVEFORM FROM END OF FROM END AT AFFECTED CABLE 1 OF CABLE 2 LUMPED LOADS CP 2576 Figure 2 17 Violation of Rule No 5 Waveform Example The reflection in this waveform also crosses the 8640 threshold and may cause a failure Now suppose the length of cable no 1 is increased
9. NPR11 DMC11 11 DC11 2686 Figure 2 20 Algorithm To Determine NPR Sequence Sheet 2 of 2 2 21 Using procedure outlined in Figure 2 20 the maximum NPR rates specified in Table 2 2 following steps should be used to approach a DATA LATE problem Determine the correct sequence of devices the Unibus If the configuration is incorrect correct it 2 Determine from the configuration tables whether or not the system is expected to experience DLTs due to Unibus bandwidth refer to Figure 2 24 3 Ifthe system is not expected to experience DLTs but nevertheless does isolate the hardware malfunction with the bus busy measurement technique In some cases it may be useful to apply the Bus Busy measurement technique to systems which may experience Data Lates due to Unibus bandwidth In such instances the tech nique helps to demonstrate that the hardware is functioning correctly NOTE For the purposes of this manual bandwidth is defined as the number of bus cycles that can be accom modated and still provide successful execution of the application software 2 4 Device Categories All existing NPR devices that are connected to the Unibus are considered to be in one of the two defined categories Note the fact that all communication devices are considered to be in category classification even though some devices have data buffers of more than six words usually these devices multiplex mo
10. each device bus contributes its own unique impedance and mismatch in complex time relationships Figure 3 10 DEVICE 4 M Figure 3 10 System Device Impedance Example CP 2595 of this impedance and resistance mismatch is normal and to be expected in Unibus systems The objective here is to point out the possible impedance mismatch and how to use the appropriate tools to minimize the effects of reflections and Reference the techniques listed in the following paragraphs 3 3 1 Line Termination Technique The question may be asked how can a 178 and 383 ohm resistor properly terminate a line which has an impedance of 120 ohms 3 11 perfect power supply has an ac resistance impedance of zero ohms so for ac considerations termination diagram changes somewhat to that shown in Figure 3 11B and simplified in Figure 3 11C 2 1200 POWER SUPPLY 2 1200 R1 R2 178 9 383 9 CP 2596 Figure 3 11 Line Termination Technique Example The choice of these two values satisfies both the quiescent condition and the required termination impedance 3 4 CABLE AND CONTACT RESISTANCE LOSSES The threshold point at which a bus receiver switches asserted from a 0 to a 1 is approximately 1 3 If a driver cannot pull the line low enough to completely assert the line erratic system operation will occur There must be adequate
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12. 2 23 BUS BUSY TEST TECHNIQUES Xy cde de RIA 2 24 Bus Busy and Latency Tolerance 2 24 Calculating Nominal Bus Busy Times 2 25 Measuring Bus Busy Times 2 27 Configuration Tables 22 55 UR o 2 30 jii 3 3 1 222 3 2 1 3 2 2 3 2 3 3 2 4 3 2 5 3 3 3 3 1 3 4 CHAPTER 4 4 1 4 2 4 2 1 4 2 2 4 2 3 4 3 4 4 4 4 1 4 4 2 4 5 4 5 1 4 5 2 4 5 3 4 6 4 6 1 4 6 2 4 6 3 5 5 1 5 2 5 3 5 4 9 9 5 6 5 7 5 8 5 9 5 10 5 11 CONTENTS Cont Page TROUBLESHOOTING GENERA CS iie oc es 3 1 TIMING CONSIDERATIONS 3 1 DATO DATOB er 3 1 DN EFEDATII sed euet S fee 3 1 Interrupt Transactions 3 5 High Frequency Cable Losses 3 5 Peripheral Data Rates 3 6 PROPAGATION DELAY 3 6 Line Termination Technique 3 11 CABLE AND CONTACT RESISTANCE LOSSES 3 12 BUS MARGINING GENERAL 4 4 1 BUS QUIESCENT LEVELS 4 1 Quiescent Conditions 4 2 Multiple Bus System Considerations 4 6 Grant Line Termination 4 8 HI LO TERMINATOR BUS MA
13. 3 APPENDIX D BUS LOADS 342012 X EE X GP 9E X 6p X 82 X 28 5 3 x osgxtizxzz S4 YG ve BT it 71 444 444 244 OPS LLL 42019 HUN T qed jeuiqe AST 9 Kjddns 5 9 Ast ASI q 096H OWA 052 ASI jaueg Sonjdej5 08 02 ZEST e x fe 2 o 0051 t 4 1 5 yoy 044 194 x pet ZZ x yeoy yoy 002 SZZ you 005 9 90090 095 yeoy 2046 588 9 AST eur yun Sure AGT 09 29341 1043009 241422121 ASI ASI AGT ASI v8 c onm et 245 245
14. 3 1 2 1 3 4 2 2 2 2 1 1 1 1 Table 2 1 Realistic Load Values Driver Type 8881 8881 8881 8881 8881 8881 8881 8881 NONE 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 8881 74 01 1 74 01 1 74 01 1 22 18 unit loads if Revrs are 380s N O RM jh pd unit loads if Revrs are 8640s Table 2 1 Realistic Load Values Cont Max No Max No unit unit loads if loads if No of Driver Revrs Revrs Type are 380s are 8640s MRII 1 1 29 MSII 2 1 6190 1 4 1 8571 4 1 1 238 8571 3 1 1 119 7380 2 1 1 6190 2 1 1 6190 2 1 1 6190 RPI 2 1 1 6190 3 1 1 119 7380 2 1 1 6190 TM11 2 1 1 6190 UDCII 2 l 76 24 UNIBUS LATENCY This section is designed to familiarize the Field Service Engineer with the recommended NPR Device Sequence on the Unibus and also provide the ability to determine and minimize possible Data Late errors The device sequences for a given PDP 11 System CPU memories and devices obtained by applying the algorithm given in Figure 2 20 and Table 2 2 Table 2 2 Maximum NPR Rates of t
15. 5 Preventive Maintenance Schedule 5 6 vi This user s manual is detailed troubleshooting and reference guide for isolating Unibus problems related to a systems which are inoperative and b systems which are marginal Due to the complexities and terminology associated with the Unibus this manual also contains descriptions definitions and reference material relative Unibus and associated hardware NOTE This manual does not define the optimum system configurations for throughput or latency tolerence which may be dependent on customer usage and applications environment This manual supersedes Unibus Margin Tester user s guide document number EK FS002 OP PRE NOTE The M9308 Margin Heads are direct replacements for the M9303 Margin Heads However the M9308 allows for greater margining voltage 2 93 to 7 85 V than the M9303 4 2 to 7 0 V 1 INTRODUCTION 1 1 SYSTEM OVERVIEW Most of the PDP 11 s internal electronic components and system peripherals are connected to and communicate with each other through the Unibus There are 56 lines on the bus that handle such signals as address data and control information Each device including memory locations and per ipheral device registers is assigned one address on the Unibus NOTE This manual is intended for use by authorized DIG ITAL EQUIPMENT CORPORATION personnel only Information contained in this manual
16. 55520252925 5 Exe SEU e xe 22241 Bus Segment uuum op deo Ie wor wot 2 1 Cable ans ai omar AERE SE ene Ende ed bos 2 2 Bus Element a erd adai SEO Eee 2 2 L mped Load qs aiota cas Ade 2 2 Bus Jumper pere Sox 2 2 Bus TerH HalOE kt oce 5 doe 2 4 Semi Lumped Load 2 4 AC Unit eee 2 5 DC Unit Load xus 2 6 Unibus Length and Loading 2 6 UNIBUS CONFIGURATION RULES 2 7 Maximum Cable Length Rule 1 2 8 Maximum dc Loading Rule No 2 2 8 Maximum Lumped Loading Rule No 3 2 8 Skewed Cable Lengths Rule No 4 2 11 Skewed Cable Lengths Supplement Rule No 5 2 13 Rule Violations Rule No 6 2 16 System Acceptance Rule No 7 2 16 Actual Bus 2 17 UNIBUS DATENGY wax ee moe Sacre eS eee Sane ERE SS 2 19 Device Categories 2 22 NPR Calculations for TL 2 22 Latency Tolerance Calculations 2 23 Devices ui eS ee 2 23 Unibus Loading Rules
17. CONTENTS Cont ECO HISTORY AND REWORK M9202 2 UNIBUS JUMPER INSTALLATION AC AND DC LOAD TABLE BUS LOADS FIGURES Title Page Lumped Loads Example 2 3 Lumped Loads Example B 2 4 Semi Lumped Loads Example C 2 5 Bus Load Example eR E Ost 2 7 Rule No 3 Violation Block Diagram 2 8 Rule No 3 Violation Waveform Example 2 9 No 3 Implementation Block Diagram 2 9 Rule No 3 Implementation Waveform Example 2 10 Multiple Bus System Example 2 10 Rule No 4 Violation Block Diagram 2 11 Rule No 4 Implementation Example A Block Diagram 2 11 Rule No 4 Implementation Example B Block Diagram 2 12 Rule No 4 Violation Waveform Example 2 12 Rule No 4 Implementation Waveform Example 2 13 Skewed Cable Length Violation 2 sooo e 2 14 Skewed Cable Length Violation Waveform Example 2 14 Violation of Rule No 5 Waveform Example 2 15 Implementation of Rule No 5 Waveform Example 2 15 Actual Bus Loads Example 2 17 Algorithm to Determine NPR Sequence 2 20 Unibus Length Between Device and Memory 2 28 Single Cycle Transaction 5 2 5 2 29 Dou
18. DATA at which point it is possible for high speed systems such as the 11 45 which allows only the 75 ns maximum skew to clock in erroneous data Some memories have a potential problem with this timing relationship in certain systems When a system is upgraded from an 11 05 or 11 20 to an 11 45 or when more of this memory is added in an extended cabinet by a longer Unibus cable the risk factor for problems becomes greater If problems are experienced with these memories MM11 L 11 MM11 E MMII F in high speed systems consult F S Product Support Refer to the 1975 Peripherals Handbook for Unibus timing information 3 1 ISOLATE SOURCE OF PROBLEM BREAK BUS SEGMENTS AND TERMINATE SUCCESSIVELY SMALLER SECTORS OF THE UNIBUS WHILE MONITORING THE QUIESCENT LEVEL ON THE BAD LINE BAD DRIVER OR RECEIVER REPLACE BAD DRIVER OR RECEIVER Figure 3 1 NO SUPPLIES TERMINATORS SHORTS AND OR OPENS ON THE UNIBUS RESOLVE THE PROBLEM BEFORE CONTINUING START CORRECT TERMINATORS BEING USED YES ARE UNIBUS CABLES FORMED YES ARE GRANT LINES PROPERLY ERMINATED YES ARE QUIESCENT LEVELS CORRECT YES CONFIGURATION RULES FOLLOWED YES NO NO NO NO INSTALL TERMINATORS SEE APPENDIX A INSTALL FOAM ON UNIBUS CABLES SEE APPENDIX A TERMINATE GRANT
19. L 8K MF11 LP 860 16K MF11 U 740 16K 1 920 Other Core Table 2 5 Transmitter Receiver Delay Dtr Dtr in nanoseconds Transmitter Receiver Single Type Dt 8881 Dt 8838 Dt 380 Dt 8640 Single Cycle Dp 3 4 X UL 3 5 X dc unit loads Double Cycle Dp 6 8 X UL 7 X dc unit loads 2 26 The summation of these four components yields a BBSY value unique to particular device and configuration BBSY Ddv Dma Dtr Dp The first three components of the formula Ddv Dma and Dtr are easily obtained by referring to the referenced tables Locate in the table the appropriate device memory type or transmitter receiver type and extract the number from either the single cycle or double cycle column as it pertains to the device Determining single cycle or double cycle is explained in Paragraph 2 5 3 The fourth component of the formula Dp may be derived in the following manner Single Cycle Dp 3 4 X UI 3 5 X dc unit loads Or Double Cycle Dp 6 8 X U1 7 X dc unit loads where 01 Unibus length in meters feet between the device and memory DC Unit Loads the number of DC Unit Loads between the devices and memory including the dc unit loads presented by memory itself To illustrate this look at the sample configuration shown in Figure 2 21 If the device under test were the RK11 D the value of U1 would be 60 96 cm 2 ft and the dc unit loads would
20. LINES WITH PROPER PULL UP RESISTORS SEE APPENDIX A REFER TO SECTION 2 FOR SYSTEM CONFIGURATION RULES IF CHANGES ARE MADE RETURN TO CP 2584 Unibus Troubleshooting Flowchart Sheet 1 of 3 3 2 DOES PROCESSOR HAVE SACK TIMEOUT OR BOOTSTRAP LOADER YES DO YOU HAVE SINGLE ENDED MARGINING CARDS NO OBTAIN SINGLE ENDED MARGINING CARDS FROM REGIONAL OFFICE YES DO YOU HAVE UVM TA TESTER BOX OBTAIN UVM TA TESTER BOX FROM REGIONAL OFFICE YES REFER TO SECTION 4 AND PERFORM SINGLE ENDED MARGINING TEST 1 DOULBLE CHECK THE QUIESCENT VALUES 2 TRY REPLACING 380 RECEIVERS ON FAILING LINE WITH 8640 S 3 POSSIBLE CAUSE IS REFLECTION ON UNIBUS OR MARGINAL RECEIVER TRY INSTALLING A M9202 2 BUS JUMPER NO YES DOES SYSTEM OPERATE PROPERLY REFER TO NOW SECTION 2 FOR SYSTEM CONFIGURATION YES RULES IF CHANGES MADE RETURN TO A Figure 3 1 NO NO OBTAIN HI LO TERMINATOR CARDS FROM REGIONAL OFFICE NO 1 DOUBLE CHECK THE QUIESCENT VALUES 2 TRY REPLACING THE 380 RECEIVERS WITH 8640 S 3 YOU MAY HAVE TO OBTAIN UVM TA FROM REGIONAL OFFICE POSSIBLE CAUSE IS REFLECTIONS ON UNIBUS OR A MARGINAL BUS RECEIVER TRY INSTALLING AN M9202 2 BUS JUMPER 3 3 DO YOU HAVE HI LO TERMINATOR CARDS NO YES REFER TO SECTION 4
21. Multiple Bus Systems 4 7 Grant Line Bus Margining Technique 4 8 CAES y ded ue Eu Ede aching Meu ders 4 9 Hi Lo Terminator Circuit Example 4 10 UVM TA Circuit Representation 4 11 Controls and Indicators 4 11 UVM TA Block Diagram 4 12 Single Ended Circuit Example 4 15 Quiescent Voltage vs UVM TA Voltage 4 18 M9308 Termination Circuit Example 4 20 M9308 SACK Turnaround Logic 4 22 M930 Modification Example 4 23 Unibus Voltage Margin Tester Box 5 2 Controls and Indicators Indexed 5 4 UVM TA Troubleshooting Flowchart 5 7 TABLES Title Page Realistic Load Values 2 18 Maximum NPR Rates of the NPR Devices with Variable Speed 2 19 Device Delay Ddy ei aa v mu eie Qa ud 2 26 Memory Access Delay 2 26 Transmitter Receiver Delay Dtr 2 26 Bus Quiescent Levels 4 Terminator Application Data 4 19 Tester Kit Components sa hha Se EP wt 5 1 Controls and Indicators Indexed 5
22. Refer to Chapter 4 for additional operational pro cedures and descriptions 1 5 SINGLE ENDED MARGINING TECHNIQUE For some PDP 11 processors e g PDP 11 04 and PDP 11 34 it is not possible to use the M930 margining heads with the Unibus Voltage Margin Tester Box This is due to additional hardware on the terminator module boot strap function sack turnaround etc which must be present in order for the processor to operate normally It is for these processors that the Unibus Tester Box single ended margining technique has been developed However this technique can be used with any Unibus pro cessor Refer to Chapter 4 for additional operational procedures and techniques 2 UNIBUS CONFIGURATION 2 1 GENERAL After the Unibus option configuration based on NPR latency physical location etc is determined these options must be interconnected using the correct procedure and techniques The definitions rules and guidelines outlined in this section are designed to aid you in configuring an electrically reliable Unibus These rules and guidelines are intended for new systems and are not to be considered as a justification for any changes in existing systems unless Unibus related problems are encountered and cannot be resolved in any other way The configuration rules Paragraph 2 3 ensure with reasonable confidence that Unibus segments will be electrically reliable i e resulting dc bus levels will guarantee an adequa
23. be 3 1 dc unit load for each 16K bank of memory If the device under test were the TM11 U1 would equal 2 13 m 7 ft and dc unit loads would equal 4 NOTE If the device under test is located behind one or more bus repeaters add 375 ns for devices doing single cycle transfers or 750 ns for devices doing double cycle transfers to the calculations for each bus repeater between the device and memory 2 5 3 Measuring Bus Busy Times dual trace oscilloscope with three probes will be needed to conduct the following tests The third probe will be used to monitor MSYN in order to determine if some of the NPR devices such as 15 are doing double cycle transactions If it is certain that all the devices to be tested will be conducting single cycle transfers only the third probe be eliminated and all calculations will be made from figures extracted from the single cycle columns in Tables 2 3 2 4 and 2 5 2 21 60 96 2 ft 1 52 m 5 ft 2 43 m 8 ft 1 52 m 5 ft UNIBUS ccc RH11 11 RP11 C L 1504 Ul ju eco de dmi CP 2683 Figure 2 21 Unibus Length Between Device and Memory Set up the oscilloscope as follows Coupling dc Trigger External positive Mode Alternate Vols Div 1 with X10 probes Time Div 5 microseconds Now locate a convenient access to the Unibus The TC11 DECtape is a good access point if available otherwise any
24. by 1 52 m 5 ft instead of cable no 2 This will implement Rule No 5 correctly In this case the affected lumped load will see the following waveform Figure 2 18 when its driver unasserts the bus 8140 THRESHOLD t t te t DRIVER REFLECTION REFLECTION NET WAVEFORM WAVEFORM FROM END OF FROM END OF AT AFFECTED CABLE 1 CABLE 2 LUMPED LOAD CP 2577 Figure 2 18 Implementation of Rule No 5 Waveform Example 2 15 The reflection from ends of cables 1 and 2 do superimpose somewhat but not much result the 8640 threshold is not crossed 2 3 6 Rule Violations Rule No 6 Rules No 1 through No 5 should be implemented if possible On rare occasions it may not be prac tical to do so For example the last bus segment on a system may exceed the 15 24 m 50 ft maximum length rule by 1 52 m 5 ft and implementing Rule No 1 may require another DB11 A repeater which may require another BA11 ES expander box which may require another H960 cabinet In this case it is acceptable to violate Rule No 1 providing that the system is tagged so that Rule No 6 is always followed when the system undergoes change or corrective maintenance Common sense has to be exercised if any of Rules No 1 through No 5 is violated The voltage margining procedure follows 1 Replace the two terminators of the segment M930 M9300 M9301 M9302 M981 with the appropriate low margin cards M
25. here to familiarize the user with Data Late DLT occurrence possibilities of some common PDP 11 systems No attempt is made in this manual to cover all possible configurations because of the complexity of the problems that could be encountered In all configurations the general rules are 1 Ifa configuration runs DLT free then a subset of the configuration should also run DLT free 2 Ifa configuration runs with DLT adding more devices to the system should also give DLT 2 30 8Knp 16Knp 8Kp 16Kp 1 RK11D TC11 RJSO04 RP11C TJU16 1 40H11 2 RK11D TC11 RJPO4 RP11C TJU16 1774DH11 3 RK11D TC11 RJPO4 RJS03 8 s TJU16 1 7 4DH11 4 RK11D TM11 TC11 RJSO3 ALs RP11C 1 4DH11 5 RK11D TC1 1 RJSO3 A4Ls RP11C TJU16 1 74DH11 6 RK11D TM11 TC11 RP11C RJS03 84s 174DH11 7 RK11D TC11 RP11C RJSO3 8 4s 17 4DH11 RJSOA4 R JPO4 RP 11C RJPO4 RJSO3 AU s RP11C DLT Free region The configurations that fall in this region should run without 8Knp non parity memory DLT errors when all devices are transferring data to from the main memory 8Kp parity memory simultaneously DLT region The configurations that fall LS in this region will give us DLT errors when all devices are transferring data to from the main memory simultaneously CP 2776 Figure 2 24 DLT Configurations 2 31 3 TROUBLESHOOTING 3 1 GENERAL This section is designed to aid in isolating and troubleshooting Unibus failur
26. improve system throughput 2 5 BUS BUSY TEST TECHNIQUES The following description is designed to aid in determining nominal device bus busy times for PDP 11 system configurations It is intended for use in cases where a system under test is configured correctly but is still incurring Unibus Data Late errors Almost every PDP 11 I O device transferring data at the NPR level has a period of time in which a word or byte of data can remain in its data buffer before the next incoming word displaces it This period of time is known as a device s latency If during this period of time the device is unable to complete a Unibus transfer the word in the data buffer will be displaced and lost A data late error will result and the transfer operation must be aborted and restarted This is obviously an undesirable condition Latency or Data Late errors may occur as a result of many factors e g device and memory types Unibus configurations software in use and hardware malfunction This document will address hard ware malfunctions 2 5 1 Bus Busy and Latency Tolerance In many instances stand alone diagnostics and system exercisers will provide sufficient information to allow the problem to be identified and isolated This generally leads to a traditional troubleshooting approach 2 24 Sometimes however the malfunction will be more subtle eluding even most rigorous diagnostics In the past large devices were slow by today s
27. is neither intended to be a product specification nor to super sede or replace any other published information that is available to customers or users of DIGITAL products Some PDP 11 system configurations experience permanent and intermittent bus failures due to improper signal termination and loading techniques These problems can exist even when the proper guidelines and rules for system configurations are followed This manual will assist in the proper procedures for isolating configuration and Unibus problems and corrective action that can be imple mented for better system operation Due to complexity of system configuration and operation all Unibus systems are subject to additional electrical and mechanical factors which may become even more relevant when and if these factors interact If this interaction becomes large enough it can cause false signal levels that can seriously effect system operation Some of the signal conditions that can occur because of these additional electrical and mechanical factors follow Signal caused by dc loading of receivers and drivers Signal loss caused by nonzero resistance of BC11 jumper cable Signal loss caused by connector contact resistance Standing wave reflections from devices on the line Increased propagation delay caused by devices on the line and high frequency cable losses Crosstalk on bus lines caused by the cable or by devices attached to the bus Signal skew caused by multiple high fr
28. low threshold margin to prevent this problem In the asserted low true condition wire and contact resistance may cause the input voltage at a receiver gate to be higher than the driver output 3 12 5 1780 178 Q 383 0 3830 DRIVER a RECEIVER CP 2597 Figure 3 12 Cable Resistance Problems Example Referring to Figure 3 12 assume a pure cable resistance of 0 60 3048 m 1 and ignore contact resistance which would only aggravate the problem If the cable between the driver A and receiver B were 15 24 m 50 ft then 30 0 60 X 15 24 50 9 14 30 A voltage will be developed across Ryg with the polarity as indicated when the driver asserts the line This voltage could be as great as 0 7 V Vi will not be 0 8 but instead Vin lt 0 8 VRUB In this case Vi might be as high as 1 5 V 0 8 0 7 and erratic system operation may result Unibus cable card contacts must be clean to minimize contact resistance and cable length should be as short as possible to minimize wire resistance 11 cable is typically 0 19 0 3048 m ft Considering the return path in addition to the signal line cable resistance is approximately 0 20 0 3048 m ft of cable length 3 13 4 BUS MARGINING 4 1 GENERAL Experience has shown that a properly functioning Unibus will operate with terminator source voltages of between 4 2 and 7 0 volts without any adverse effects If the v
29. make this determination This section deals with calculating or predicting a BBSY time for a device within a given configuration Component tolerances throughout the system make exact calculations impossible but typically a device should fall within a plus or minus 30 percent range of the predicted value If after measuring the real BBSY time it exceeds the predicted value by more than 30 percent a potential problem area has been found and steps should be taken to bring the offending device nearer to specification For the purposes of this manual BBSY can be thought of as composing four separate components 1 This is the internal timing delay of the device itself The figure can be obtained from Table 2 3 2 Dma This is memory access time or the time it takes memory to assert SSYN after it sees MSYN This figure can be obtained from Table 2 4 3 Dtr This is the delay associated with Unibus transmitters and receivers This figure may be obtained from Table 2 5 4 Dp This is the propagation delay of the Unibus itself taking into account its length and loading properties This must be calculated from a formula 2 25 Table 2 3 Device Delay Ddv nanoseconds Single Cycle Controller Double Type TM 1 11 RF11 DHI RK11 D RH11 680 Table 2 4 Memory Access Delay Dma Dma in nanoseconds Single Cycle Memory Double Type 8K MFII
30. than AC LO L or DC LOL For example an M930 terminator an M7821 module a BB11 backplane a BC11 cable and an RK11 controller are Unibus elements An H720 power supply an LA36 DECwriter and a 11 expander box are not Unibus elements 2 2 4 Lumped Load A Lumped Load is defined as a group of Unibus elements other than cables or jumpers which are interconnected via Unibus jumpers and direct wiring backplane wire PC etch only The group is not a lumped load if it uses a Unibus cable to interconnect the Unibus elements or if the elements are separated a bus repeater Be certain the difference between jumper and cable is understood see Figures 2 1 and 2 2 2 2 5 Bus Jumper A Bus Jumper is defined as a Unibus element connecting two backplanes which contains less than two feet of cable The following elements are Unibus jumpers M920 jumper M9200 jumper with boards 1 27 cm 0 5 in apart M981 jumper terminator 0 6 inch cable 15 24 The BC11A 0 is considered to be a jumper for the purposes of this manual because it contains less than 60 96 cm 2 feet of 120 ohm cable 2 2 JUMPER CABLE BC11A 15 MM11 L LUMPED LOAD LUMPED LOAD CP 2615 In this system there are two lumped loads 1 M930 11 05 CPU and MMII L 2 DD11 B DL11 A and M9301 Suppose the M920 is replaced by an M9202 LUMPED LOAD LUMPED LOAD LUMPED LOAD CP 2616 Now there are
31. three lumped loads 1 M930 11 05 CPU and MMII D 2 RKII D DDII B DL11 A and M9301 Figure 2 1 Lumped Loads Example 2 3 LUMPED LOAD LUMPED LOAD c UNIBUS SEGMENT CP 2617 This system has two Unibus segments separated by a bus repeater so the system has two lumped loads 1 M930 11 45 CPU left side 2 DBII A right side DD11 B four DL11 As M9301 NOTE These examples are for illustrative purposes only and do not represent practical configurations Figure 2 2 Lumped Loads Example 2 2 6 Bus Terminator A Bus Terminator is defined as a Unibus element or part of an element containing a resistive network which connects to the end of a Unibus segment and matches the 120 ohm characteristic impedance of the Unibus transmission path The M930 and M9306 are Unibus terminators if they connect to the Unibus The following bus elements contain Unibus terminators 981 jumper terminator M9300 Unibus B terminator M930 NPR logic M9301 bootstrap terminator M9302 M930 with SACK return bus switch 11 bus repeater PDP 11 04 CPU NOTE other CPUs also contain terminators A Unibus segment must always have a Unibus terminator at each end of its 120 ohm transmission path 2 2 7 Semi Lumped Load A semi lumped load is defined as a group of lumped loads interconnected by 91 44 cm 3 ft or less of cable M9202 BC11 2 or BC11 3 and not s
32. transfers will occur within 200 window 4 Calculate the time per transfer by dividing the total number of transfers into the window time 200 52 9 lt 3 78 us transfer rate If this figure is greater than 2 5 us the system should run without data lates This is approximately a rate of 400 kHz 3 3 PROPAGATION DELAY If a voltage is supplied between any two conductors they may be considered as a transmission line The ideal transmission line input impedance looks like pure resistance but in fact is mainly a com bination of capacitance and inductance see Figure 3 3 When the voltage at one end of the transmission line is changed that change does not instantaneously appear at the other end There is some delay which is called propagation delay see Figure 3 4 The propagation delay of BC11 Unibus cable is approximately 1 4 to 1 9 ns per foot or 0348 m Bus repeaters and bus switches will decrease the data rate supportable on the bus A figure of 3 0 may be more applicable on a repeated line 3 6 __ 1 2588 Figure 3 3 Transmission Line Circuit Example 15 24 m 50 ft BC11 CABLE A B ill Pd PROPAGATION TIME DELAY CP 2589 Figure 3 4 BC11 A Unibus Cable Delay Example 3 7 lossless transmission line of infinite length looks like a pure resistance of value 2 L C If such a line is broken and terminated with a resistor o
33. 1 70 HEAD PIN COMPATIBLE WITH 77 M930 TERMINATOR CP 2604 Figure 4 13 UVM TA Block Diagram 4 12 4 41 Functional Description Functionally the UVM TA consists of a fixed supply a variable supply a control panel Unibus cables and terminator cards that enable the user to margin voltages in the Unibus sections NOTE The use of the Unibus cable with this tester is as a power transmission cable The fixed supply provides the voltage for normal system operation The variable supply when selected provides the variable voltage for system margining purposes The front panel controls and indicators control the choice of fixed or variable voltage vary the voltage display the voltage indicate both ac and dc power on and select individual Unibus signal lines CAUTION This Unibus cable must never be plugged directly into a CPU option or peripheral while connected to the tester it should be plugged into the margining head only With the recommended program DECXI1 or operating system running in the system the user now selects any or all lines to be margined The respective switches should be placed in the VARIABLE position The margin voltage can then be varied by using the VARIABLE potentiometer The voltage level at which the system fails or when the limits of the supply are reached may be obtained by viewing the metered display 4 4 2 UVM T Operation and Test Procedures Unlatch and remove the top cover from the su
34. 5 6009 OSER A rman eo VARIA fate DISPLAY FIXED VOLTAGE SWITCHES SHOULD CHANGED WHILE PROGRAM IS RUNNING 1 ADDRESS REGISTER CAUTION AL swecues bE FRED POSTION BEFORE APPLYING POWER Figure 5 2 Controls and Indicators Indexed 7534 2 Table 5 2 Controls and Indicators Indexed Index No Function 1 FUSE 2 5 Protects tester from current overload 2 ON OFF Switch controls ac power to tester 3 ON OFF Indicator Lights when tester is on 4 56 single pole double throw switches control margining volt age to each of 56 individual Unibus lines When in the down position the selected line is connected to a 5 Vdc fixed voltage supply When in the up position the selected line is connected to variable dc voltage supply 5 Tester connectors connects selected voltage levels to margin ing heads 6 Controls output voltage of variable voltage 7 When depressed digital voltmeter monitors voltage of fixed supply voltage DVM normally monitors variable supply voltage 8 Digital voltmeter monitors voltage of selected power supply 9 VARIABLE lights when variable supply is operating Bright ness is proportional to selected voltage 10 FIXED lights when fixed supply is operating 5 8 MAINTENANCE PHILOSOPHY Tester maintenance consists of preve
35. 5 0C11 12 17 12 04 6 89 17 79 681274 0041 3 1 91 1 78 2 51 081976 00 1 gt 6 a 4 18 3 48 5 38 120178 REV 3 LOAD IS IN PROCESS 004 1 4 0 3 0 2 18 3 89 121576 0041 0 8107 1 4 121576 810 4 2FT lLOTs 0014107 SLOT 1 4 4 2 63 3 08 121876 810 4 31075 9 4 8 075 19011988 14 2 13 38 6 22 11 12 082175 0711 5 1 5 09 2 96 5 08 121874 0111 7800 3 1 1 64 0 79 2 49 030375 0L119C 8 1 3 1 1 76 4 98 2 72 030575 OLiseW 7856 3 1 2 15 0 80 2 30 230575 OMC11 3 1 3 13 1 48 9 47 121576 0911 5 1 4 56 4 78 4 16 030375 0011 8 1 7 27 6 6 17 80 101775 19B 9 1 9 14 8 15 7 88 101775 811 7869 5 i 4 35 4 93 Ait 191675 1 5 4 83 2 10 3 46 101775 DRILL 3 1 2 927 0 82 2 50 050775 CRijeM 3 1 2 90 0 82 2 50 050775 01703 7 1 4 67 2 96 6 52 01923 5 0 3 1 3 15 3 07 2 75 DTBA UNIBUS 2 0 1 78 1 75 1 23 081776 UNIBUS R 1 82 1 59 1 78 081776 IN amp 55 3 a 2 09 1 47 881776 B IN amp 59 2 78 2 29 2 90 081776 SR OUT 1 69 1 16 1 45 081776 SR amp 3 3 15 1 76 2 07 081776 0911 a 1 3 69 1 61 1 71 121575 11 3 1 3 03 1 79 0 50 121570 DV11 12 1 11 63 5 24 14 45 101575 0X11 6 1 3 82 5 26 2 56 101575 KE119B 4 1 611 0 19 1 12 3 89 101575 yeh M787 3 0 1 17 e 14 011477 3 83 1 85 1 85 051075 1 M7228 M722
36. 8 ot Gen 6 Be 2 02 2 28 3 59 102275 cs J KY119LA g 1 7859 5 1 1 79 2 18 1 15 122975 LKAL A 1 3 65 1 15 3 87 121576 LP11 5 1 2 95 4 91 4 57 101675 3 1 3 97 2 80 23 00 052776 LS11 3 1 1 56 7 687 2 81 050275 LV11 3 1 1 8 22 1 11 2 05 121576 MT SR PARITY MODULE MT amp S9 PROGRAM CONSOLE 5 1 5 1 0 512 4 99 65 50 121576 aMOORE SYSYEM DEVICES 1 8 4 87 4 72 1 03 17 47 081976 2 10CC 99559 99551 5 1 57 2 78 2 33 1 96 0811976 3 1701 99556 3 3 71 3 12 1 18 1 10 081976 4 1CALCULATOR 99319 3 1 9 74 2 30 0 67 081976 MM119DP 1 1 1 16 1 09 1 12 210575 MS1jeJP 1 1 0 56 4 33 0 58 010576 BACKPLANE 8 8 16 1 142 0 30 121975 MF119L 5 1 2 10 490 1 7 1 5 00 7 49 06 00 091975 MF11eL 3X8k 9 1 5 50 8 70 7 49 091976 MF119U 2X16K 8 e 3 76 8 00 6 00 630975 MK 11 1 16 6 2 11 5 59 4 49 001975 1 2 6 8 3 3 76 98 00 6 00 091975 6 1 1 26 5 46 1 49 6 4 160 A PCAICNEW 4 11 04 7263 9301 6 13 1 79 7 89 060176 11 05 8 8 45 8 50 9 9 120874 POP 11 34 WITH M9391 4 31 5 38 3 58 121576 11 35 12 63 6 03 12 14 121674 11 45 808 11 149 19 4 07 11 08 121075 0 LOADSIKWTI1L BUS CPU BUS 1 MOS BUS 2 MNS amp MINNTRONICS CACHE 11 60 11 60
37. 9202 folded cables or BC11A 2s if M9202 is unavailable should be used in place of M920s in order to separate large lumped loads The effect of the M9202 is to cause the peak reflections from the lumped loads it separates to occur at slightly different times The following examples see Figures 2 7 and 2 8 illustrate implementation of Rule No 3 AFFECTED ELEMENT 1780 LUMPED LOAD WITH 40 AC UNIT LOADS BC11A 15 3830 CP 2565 Figure 2 5 Rule No 3 Violation Block Diagram 2 8 The system shown Figure 2 5 violates Rule No 3 When the driver in the affected bus element unasserts the bus the receiver in that element will see the following waveform 8640 THRESHOLD DRIVER WAVEFORM REFLECTION NET WAVEFORM FROM LUMPED AT RECEIVER LOAD CP 2566 Figure 2 6 Rule No 3 Violation Waveform Example The reflection may cause the threshold of the 8640 receiver to be crossed a second time and a failure may result To implement Rule No 3 the lumped load must be split into two equal loads by adding an M9202 in place of an M920 see Figure 2 7 AFFECTED ELEMENT LUMPED LOAD WITH 20 AC UNIT LOADS LUMPED LOAD WITH 20 AC UNIT LOADS BC11A 15 CP 2567 Figure 2 7 Rule No 3 Implementation Block Diagram 2 9 The conditions to satisfy Rule 3 now implemented When driver in affected bus element unasserts the bus
38. 9304 M9305 2 Run complete diagnostics and system exercisers 3 Replace the two low margin cards by the corresponding high margin cards M9304 Y A M9305 Y A 4 Run complete diagnostics and system exercisers 5 Replace the two high margin cards with the original terminators If any diagnostic or system exerciser fails during this procedure the system has a problem It may be necessary to implement a rule violation in order to correct the problem A Unibus voltage margining tester box Chapter 4 may be necessary to isolate the problem To determine if there is a margin problem failures during margining must correspond with or compared to no failures when not margining 2 3 7 System Acceptance Rule No 7 On rare occasions Rules No 1 through No 5 may not be sufficient to eliminate all reflection prob lems On these occasions a Unibus voltage margin tester box UVM TA should be used along with common sense to isolate the problem and implement solutions When an option fails gives data errors hangs the bus etc during a margining test particularly the low margining test be suspicious of reflections from surronding options after eliminating weak drivers leaky receivers etc The solution may be to replace an additional M920 in those surrounding options with an M9202 or even a 3 in order to further spread out and reduce reflections If Rules No 1 through No 5 do not eliminate a reflection problem please consul
39. AND PERFORM HI LO TERMINATOR TEST DOES SYSTEM OPERATE WITH HI TERMINATOR CARDS YES DOES SYSTEM OPERATE WITH LO TERMINATOR CARDS YES IF MULTIPLE BUS SYSTEM REPEAT HI LO MARGIN TEST FOR REMAINING BUS SEGMENTS Unibus Troubleshooting Flowchart Sheet 2 of 3 OBTAIN UVM TA TESTER BOX FROM REGIONAL OFFICE NO UVM TA MARGINING WILL NOT HELP AT THIS TIME DISCONNECT UVM TA AND REPLACE SYSTEM TERMINATORS RETURN TO START NO DISCONNECT MARGIN BOX AND REPLACE SYSTEM TERMINATORS Figure 3 1 NO DO YOU HAVE UVM TA TESTER BOX YES REFER TO SECTION 4 AND PERFORM UVM TA MARGINING TEST SYSTEM OPERATE PROPERLY WITH NORMAL TERMINATION 5V 5 DOES SYSTEM OPERATE PROPERLY WITH 7V APPLIED TO TERMINATORS START AT POINT WHERE SYSTEM OPERATES AND SLOWLY ADJUST TERMINATOR VOLTAGE UNTIL FAILURE OCCURS RANGE OF 4 2 TO 7V DOES SYSTEM OPERATE PROPERLY WITH 4 2V APPLIED TO TERMINATORS START AT 5V AND SLOWLY DECREASE TERMINATOR VOLTAGE UNTIL FAILURE YES IS THIS A MULTIPLE BUS SYSTEM WITH REMAINING UNTESTED BUS SEGMENTS YES REPEAT FOR ALL OTHER BUS SEGMENTS 3 4 Unibus Troubleshooting Flowchart Sheet 3 of 3 FIND CRITICAL LINE OR LINES START WITH MSYN SSYN INTR SACK AND BBSY IF
40. D position 1 Place power switch in the OFF position 4 15 Turn system power off Remove 930 system terminator see application table and install the M9308 margin head If the M9308 is not used at the electrical end of the bus disable SACK turnaround with the switch located on the M9308 module Plug the Unibus cable BC11A into the M9308 margining head CAUTION Connecting the BC11 power cable directly into a CPU or peripheral without the margin head may cause equipment damage Connect the BC11 power cable into tester slots 1 or 2 Plug tester box ac cord into a convenient power source Power may now be applied to the system and the tester Place power switch in the ON position and adjust the variable voltage to 4 34 V Load recommended programs DECXI1 or operating system NOTE Signal switches must not be switched while system is running Always halt the system before attempting to change selection switch setting There is one switch for each of the designated bus signals and is labeled on the tester box control panel By setting a switch the VARIABLE up position the margin voltage displayed is applied to the individual pull up resistors thus the signal lines can be mar gined by varying the VARIABLE potentiometer With the system halted put all 56 bus signal switches in the VARIABLE position Adjust variable voltage to 6 V and restart system running program selected Then increase in 5 V steps
41. ECTIVE MAINTENANCE If the tester fails the acceptance test or fails while testing a Unibus system corrective maintenance must be performed The flowchart Figure 5 3 will pinpoint the faulty tester component However before using the flowchart unscrew and lift up the control panel and perform a visual inspection Look for burnt or damaged wires or components Replace any faulty wires and component s if found and perform the acceptance test procedure to determine if the tester has been repaired If not begin using the flowchart CAUTION Certain circuits in the tester operate at 110 Vac Special care must be taken when probing near these circuits Before disconnecting replacing and or reconnecting any part other than a fuse turn tester off and unplug it NOTE Turn tester off when replacing front panel fuse 5 11 DISASSEMBLY ASSEMBLY Many of the components within the tester are also accessible and can be replaced without performing any disassembly The switches indicators and plugs on the tester control panel are easily accessible for repair or replacement However to remove either power supply the transformer or the fan the tester must be disassembled To disassemble the tester perform the following procedure 1 Unplug line cord 2 Remove the tester from its carrying case by slipping it out of the case 3 Unscrew and lift up the control panel 4 remove the power supplies remove the power supply bracket using a sock
42. Figure A 1 Comparison of 8640 380 Threshold Worst Case Table A 1 Unibus Types Receivers Input Voltage Type DEC P N Function Note Low High Leakage 380 19 09485 Quad nor 1 1 3 2 5 160 8640 19 11469 2 1 3 1 7 80 11380 19 11113 1 Hysteresis 8644 Not assigned Hex inverter 3 1 3 1 7 80 8645 19 12128 7 input nor 3 1 3 1 7 80 314 19 09704 7 input nor 4 1 3 2 5 160 384 19 09486 Quad or 1 1 3 2 5 160 8837 19 11116 4 1 3 2 5 160 Drivers 8881 19 09705 Quad 25 74 01 19 09849 1 250 Transceivers 8641 19 11579 Quad transceiver 3 100 8838 19 11117 Quad transceiver 1 100 Notes l Not allowed in new designs 2 Replaces the DEC 380 in Unibus applications 3 Available in July 75 4 To be used in new designs only until pin compatible replacements are available I C Replacement 314 8645 8837 8644 A 2 2 BUS DRIVERS The DEC 8881 is the standard Unibus driver Others which have been used are listed in Table A 1 Unibus pin assignments are illustrated in Figure A 2 A 3 GRANT LINE TERMINATION The terminators on each of the Unibus do terminate grant lines which are received and repropa gated Grant lines are terminated as shown in Figure A 3 between devices receiving a grant line A recent series of ECOs that includes all devices using grant lines has changed the previous termination techniques as discussed previously 1809
43. GINING For some processors it is not possible to use the M9303 series of margin heads with the voltage margin tester This is because some machines include additional hardware on the terminator module boot strap function sack turnaround etc which must be present for the machine to operate normally For these machines a single ended margining technique has been developed PDP 11 04 11 34 This technique may be used with any Unibus machine Single ended margining is accomplished by placing a voltage margin terminator on only one end ofa bus segment and varying the voltage applied to it see Figure 4 14 This accomplishes the same results but the considerations are slightly different NOTE Using the M9308 single ended margin terminator a system should operate successfully between 7 85 V high margin and 2 93 V low margin as displayed by the panel meter on the voltage margin tester 5V SYSTEM TERMINATOR 180 9 UNIBUS VOLTAGE MARGIN TESTER M9308 SINGLE ENDED MARGIN TERMINATOR 390 9 5 2605 Figure 4 14 Single Ended Circuit Example 4 5 1 Setup and Operation Using M9308 Single Ended Margin Head 1 Unlatch and remove the top cover from the suitcase tester and place to one side This allows room for the cabling to be connected into the tester box 2 Remove test head M9308 and 11 from the inside cover top pocket Place all signal switches 56 in the down or FIXE
44. NG DEVICES WHOSE ORDER OF NPR RATES NPR RATE IS DECREASING NPR BEFORE LESS THAN RATES AFTER CATEGORY 2 TJU16 T1 180145 rd 1 1 9 11 T1 100 1 7 KHz l DB11 A DOES 1 NUMBER OF DEVICES YES DH11 Figure 2 20 Algorithm To Determine NPR Sequence Sheet 1 of 2 2 20 DOES THE CONFIGURATION VIOLATE UNIBUS LOADING RULES SEE SEC 2 3 5 ADD A BUS REPEATER AT THE END IF NOT ALREADY ADDED ARE THERE ANY CATEGORY 1 DEVICES BETWEEN THE LAST TWO REPEATERS MOVE THE LAST CATEGORY 1 BEFORE THE LAST BUS REPEATER TO IMMEDIATELY AFTER IT ARE THERE ANY CORE MEMORIES BETWEEN THE LAST TWO BUS REPEATERS MOVE THE HIGHEST BANK OF CORE MEMORY THIS IS AN BEFORE THE LAST ACCEPTABLE REPEATER TO SYSTEM IMMEDIATELY AFTER IT only one BUS REPEATER this means between the CPU and the BUS REPEATER Or the least frequently used category 1 device T1 Maximum tolerance between bus cycles Except asyncheonous communication devices e g DH11 which have great latency tolerance capacity DH11 can be placed in rear of all other devices NOTES 1 Throughput is conditional and is well studied at the CPU 1 bandwidth is more difficult to determine but has been investigated by Engineering 2 BR device can be put behind repeaters or behind NPR device BR device should be placed in front of asynchronous devices
45. PROBLEM NOT HERE TRY OTHER SECTIONS OF THE BUS 1 LOW BYTE DATA 2 ADDRESS AND C LINES 3 REQUEST LINES 4 HIGH BYTE DATA FIND THE CRITICAL DEVICE AND REPAIR IT POSSIBLY REPLACE THE BUS RECEIVER AND OR DRIVER ON THE FAILING LINE CP 2603 3 2 3 Interrupt Transactions A typical 11 45 system will experience problems if the data lags the INTR line on the cable by more than 30 40 ns Most DEC interfaces assert the vector address and INTR at exactly the same time and Unibus skew times may cause a timing problem if the bus is long Experiments with a typical system show the vector address lagging INTR on the cable by as much as 30 ns with 9 14 m 30 ft of Unibus cable and a TC11 or 45 ns with 9 44 m 31 ft of bus and a DL11 The electrical configuration rules as listed in Chapter 2 will minimize these problems when properly applied 3 2 4 High Frequency Cable Losses The increase in transmission line conductor resistance at high frequencies known as skin effect may be a factor in bus analysis This function exhibits a very fast rise time to 50 percent of the input buta very slow dribble up from 50 percent to 90 percent of the input A 15 24 m 50 ft bus cable could theoretically have a dribble up noticeable for up to 170 ns in response to a step function at the input The bus should therefore be kept as short as possible to avoid potential timing problems The pub lished i e allowa
46. RGINING 4 8 UNIBUS VOLTAGE MARGIN TESTER BOX 4 10 Functional Description a e aue doce be ooo C NOS E EE 4 13 UVM TA Operation and Test Procedures 4 13 SINGLE ENDED MARGINING 4 15 Setup and Operation Using M9308 Single Ended Margin Head 4 15 Single Ended Circuit Consideration 4 17 SACK Timeout ad ue nau fe 4 2 MODIFYING M930 TERMINATOR CARD 4 21 Equipment Required 4 21 Modifying the M930 4 22 Proced re for Use e a scatti wo e P A E 4 23 UVM TA TESTER UVM TA OVERVIEW 5 1 TESTER KIT COMPONENTS 5 1 TESTER SPECIFICATIONS 5 2 UNPACKING PROCEDURE 5 3 ACCEPTANCE TEST ed e ee ii i33 5 3 CONTROLS AND INDICATORS 5 3 OPERATING PROCEDURE 5 3 MAINTENANCE PHILOSOPHY 5 5 PREVENTIVE MAINTENANCE 5 5 CORRECTIVE MAINTENANCE 5 6 DISASSEMBLY ASSEMBLY 5 6 APPENDIX APPENDIX APPENDIX APPENDIX D Figure No 2 1 2 2 2 3 22 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 19 2 20 2 21 2 22 2 23 2 24 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8
47. Unibus Troubleshooting user s manual 25002 001 digital equipment corporation maynard massachusetts Ist Edition February 1977 Copyright O 1977 by Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without notice This manual is intended for use by authorized DIGITAL personnel only The information contained in this manual is intended to be used for analyzing product performance Printed in U S A This document was set on DIGITAL s DECset 8000 computerized typesetting system The following are trademarks of Digital Equipment Corporation Maynard Massachusetts DEC DECtape PDP DECCOMM DECUS RSTS DECsystem 10 DIGITAL 8 DECSYSTEM 20 MASSBUS 11 UNIBUS 1 1 1 1 1 2 2 1 252 2 2 1 2 2 2 2 2 3 2 2 4 2 25 2 2 6 2 27 2 2 8 2 2 9 2 2 10 2 3 2 3 1 2 3 2 2 3 3 2 3 4 2 3 5 2 3 6 2 31 2 3 8 2 4 2 4 1 2 4 2 2 4 3 2 4 4 2 4 5 2 5 2 5 1 2 5 2 2 5 3 2 5 4 CONTENTS Page INTRODUCTION SYSTEM OVERVIEW Xx ERE Rex OE ICA 1 1 UNIBUS TROUBLESHOOTING TECHNIQUES 1 2 HI LO TERMINATOR MARGIN CARDS 1 2 UNIBUS VOLTAGE MARGIN TESTER 1 2 SINGLE ENDED MARGINING TECHNIQUE 1 2 UNIBUS CONFIGURATION GENERAL dew beg ad BIS nov wa Xs eR 2 1 UNIBUS DEFINITIONS
48. VEL 3 3 3 2 TERMINATOR E 5 3 1 3 0 m n TERMINATORE 45 2 9 28 2 8 BUS LOADS WORST CASE N 2 6 2583 Figure 4 6 Quiescent Level vs Loading Worst Case By Unibus convention these lines are asserted true when low 1 and negated when high 20 The threshold point at which a receiver switches from a one to a zero is approximately 2 5 V using a DEC 380 Receiver Module or 1 7 V with an 8640 Receiver Module If enough loading is present to force the quiescent level low enough see Figure 4 6 system operation may become extremely erratic There must be an adequate noise margin above the threshold level to allow for crosstalk and reflections 4 2 2 Multiple Bus System Considerations Multiple bus systems are those which include bus repeaters or bus switches the entire Unibus is re propagated see Figure 4 7 When margining techniques are employed with multiple bus systems it is desirable to margin all bus sections on an individual basis It is not necessary to margin multiple buses simultaneously 4 6 16 sng o dn njN SuruigieJA 211814 IN31SAS 518 AIdILINW 8 6692 99 8 8 St Hu3iv3d3u HOLIMS vao St 9 IN31SAS 818 319 Hu31V3d3H sna 8 SNAINN S 4 7 It is important that correct termination points are used for any given bus
49. XED DVM IS PROBABLY BAD REPLACE IF NECESSARY REGULATOR BOARD SHOULD MEASURE 5 VDC BETWEEN PINS 2 AND 3 OF J1 DVM READS 3 VDC DISCONNECT P1 FROM J1 ON VARIABLE REGULATOR ISOLATE BOARD SHOULD PROBLEM MEASURE 5 VDC AND REPAIR BETWEEN PINS POSSIBLE 2 AND 3 ON 41 PROBLEM IS REGUALTOR BOARD OR BAD ADDRESS SWITCH MEASURED 5 ON BOTH BOARDS NO REPAIR REGULATOR BOARD S AS REQUIRED YES NO DVM IS YES PROBABLY REPLACE IF NECESSARY PRESS DISPLAY FIXED VOLTAGE PUSHBUTTON ON CONTROL PANEL NO DVM READS 5 VDC IF DC POWER YES LAMPS ON REGLATOR BOARDS ARE USE VARIABLE CONTROL AND ADJUST FOR 6 LIT REPLACE VDC ON DVM OR REPAIR FIXED VOLTAGE PUSHBUTTON DVM NO READS 7 VDC YES 2609 Figure 5 3 UVM TA Troubleshooting Flowchart 5 7 APPENDIX HISTORY AND REWORK 1 UNIBUS TERMINATORS M930 The initial ECOs to the M930 dated 1970 changed the termination of bus AC and DC LO which brought the M930 to etch revision B This etch revision is now obsolete If system bus problems are suspected for failure later etch terminators than the B etch should be tried A 1 1 Revision C Etch ECO No 3 to the M930 Unibus Terminators changed the termination resistors tolerance from 5 per cent to 1 percent This change improves the worst case noise tolerance and with suspected bus prob lems
50. argin tests a when the system is originally con figured and b when any Unibus element is added deleted or swapped including the swapping of a defective module or backplane Rule No 7 System acceptance Even if rules No 1 through No 5 are implemented all Unibus segments of a system should be voltage margined after the system is configured 2 3 4 Maximum Cable Length Rule No 1 If Rule No is violated a the dc drop across the bus when driven at one end and received at the other may be excessive and b far end crosstalk may be excessive In calculating lengths the M920 should be considered as zero feet the M9202 as 60 96 cm 2 ft and the BC11A 0 as 15 24 cm 6 in If the length of a segment exceeds 15 24 m 50 ft reconfiguring changing the order of bus elements may reduce the length If that fails a 11 bus repeater will be necessary 2 3 0 Maximum dc Loading Rule No 2 If too many dc loads are put on a Unibus segment the quiescent undriven voltage may be lowered to a level where bus receivers become susceptible to reflections from lumped loads and the overall noise margin on the high end bus undriven may become too small DB11 bus repeaters should be used as required to implement this rule 2 3 3 Maximum Lumped Loading Rule No 3 If a lumped load is too large it may generate a reflection on the Unibus large enough to create a false logic signal and cause a failure see Figures 2 5 and 2 6 M
51. ation will arrive at the same level The important point to note here is that what was intended to be a level change with a clean transition did not turn out that way on the line due to a termination mismatch between R and Z Essentially the same situation occurs when the termination resistor is smaller than the characteristic impedance of the line If resistance R is less than impedance Z there will be a mismatch and this will also be reflected back to the source see Figure 3 7 REFLECTION SOURCE lt TERMINATION 2592 Figure 3 7 Impedance Low Resistance Mismatch Example 3 9 Note that a transmission line which is not terminated in its characteristic impedance will have tions and b the voltage seen at any point on the line or at any instant in time will be a combination of the incident and reflected voltage The amount of reflection depends on the mismatch and approaches 100 percent for either a shorted or an open line see Figure 3 8 100 REFLECTION 100 2593 Figure 3 8 Mismatch Reflection Curve Example Essentially the same thing happens on the negative going edge of a level change so that what seemed to be a clean transition as in Figure 3 9A may look more like Figure 3 9B Nu E E A 2594 Figure 3 9 Unibus Cable Mismatch Waveform Example 3 10 To further compound problem
52. backplane with Unibus in or Unibus out will do Connect the probe corresponding to external trigger to SACK L at pin AR2 Connect the probe corresponding to channel 1 to BBSY L at pin AP2 Connect the probe corresponding to channel 2 to MSYN L at pin The software to be run during these tests will be DEC X11 Before proceeding note that Table 2 4 Dma doesn t include data on MOS or bi polar memory systems For this reason ensure that doesn t use MOS or bi polar as write buffer space If the system under test is an all core system this will not be of any concern If the system does include MOS or bi polar it will be necessary to lock the run time exerciser in memory via the RUNL command so that the beginning of 115 write buffer space which coincides with the last address 2 or the last module is in core It is acceptable if the DEC X11 code exercises from MOS or bi polar as long as the write buffer space is in core Finally inhibit write buffer rotation via the ROTOFF command 2 28 Before issuing RUNL command DESelect all modules and SELect module corresponding to the first device to be tested NOTE By testing only one device at a time and by triggering the scope from SACK it is ensured that the signals seen will be those issued by the device under test Once has been started and the scope trigger has been properly adjusted the brace should correspond to one of the two figures sho
53. ble Unibus length is 15 24 m 50 ft but it is desirable to use as little cable as possible for a given configuration see Figure 3 2 Devices should be physically arranged in the same order as they are electrically connected if possible If M9202 folded cables are needed due to physical arrangement they should not be replaced by M920s in order to decrease bus length CABINET CABINET CABINET CABINET CABINET CABINET A B THIS NOT THIS CP 2587 Figure 3 2 System Cabling Configuration Example 3 5 3 2 5 Peripheral Data Rate It is possible to support only a certain rate of data transfer on the Unibus beyond this rate data late situations will occur A method for roughly determining permissible combinations of simultaneous peripheral device activity such as would occur when executing DECX11 follows Determine a window for a given system based on the slowest NPR device transfer rate us 4 If you have an RK11 TM11 and the slowest device will be the TC11 with a transfer rate of 200 us word Window 200 ys in this case 2 Determine how many transfers the faster devices will perform in the window time Window Time Transfer Rate RK11 11 1 us word 200 11 1 18 02 TM11 27 7 us word 200 27 7 2 7 22 RP11 7 5 us word 200 7 5 26 66 3 Calculate the total number of transfers occurring within the window 1 RK11 18 02 26 66 7 22 Total 52 90
54. ble Cycle Transaction 2 30 DLT Configurations 4 4 2 31 Unibus Troubleshooting Flowchart rrr tnm 3 2 System Cabling Configuration Example 3 5 Transmission Line Circuit Example 3 7 11 Unibus Cable Delay Example 3 7 BC11 Unibus Cable Impedance Example 3 8 Impedance Mismatch Example 3 9 Impedance Low Resistance Mismatch Example o o9 3o m9 6 bX ea 3 9 Mismatch Reflection Curve Example 3 10 Figure 3 9 3 10 3 11 3 12 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 10 4 11 4 12 4 13 4 14 4 15 4 16 4 17 4 18 5 1 5 2 5 3 Table No 2 1 2 2 2 3 2 4 2 5 4 1 4 2 5 1 5 2 5 3 FIGURES Cont Title Page 1 Unibus Cable Mismatch Waveform Example 3 10 System Device Impedance Example 3 11 Line Termination Technique Example 3 12 Cable Resistance Problems Example 3 13 Unibus Slot Backplane Signals 4 3 Low True Unibus Line 4 4 Equivalent Unibus Line Circuit 4 4 Quiescent dc Level Example 4 5 Load Current Leakage Example 4 5 Quiescent Level vs Bus Loading Worst Case 4 6 Margining
55. ble tester designed to check all Unibus receivers and drivers in a system either singly or as a group Figure 4 11 illustrates the circuit represen tation of the UVM TA plus representative load values The control panel Figure 4 12 furnishes a switch for each of the designated bus signals and is used to provide fixed 5 V or variable termi nation voltage to special terminator boards called Margining Heads M9303 which are used in place of the standard M930 terminators The margining heads cards allow the voltages selected to be applied to each terminating network on an individual basis Refer to Figure 4 13 for a block diagram overview of the UVM TA NOTE This does not change the effective Unibus length 4 10 1789 VARIABLE POWER SUPPLY 383 0 CP 2602 Figure 4 11 UVM TA Circuit Representation x margin tester 282 Figure 4 12 Controls and Indicators 4 11 UNIBUS VOLTAGE MARGIN TESTER UVM TA VARIABLE DC POWER SUPPLY t VARIABLE DC 6 SWITCHES ONE FOR EACH LINE ON THE BUS 6000 0000 FIXED 6V POWER SUPPLY PANEL CONNECTORS BC11 CABLE WARNING Do NOT plug this cable directly into a UNIBUS slot it comes directly from the power supplies and may damage UNIBUS drivers EITHER 5 V FIXED OR VARIABLE DC AS SELECTED BY SWITCH IN MARGIN TESTO2 MARGINING HEAD M9303 OR M9303 4A 1
56. dual pull up resistors and thus the signal lines can be mar gined by varying the VARIABLE potentiometer With the system halted put all 56 bus signal switches in the VARIABLE up position Restart system running the selected program Adjust the variable voltage to 6 V and run system for 15 minutes or longer with all options selected Then increase in 5 V steps or smaller increments if necessary until the failure occurs Record this value CAUTION Halt and restart the program each time a new volt age is selected when running DECX11 Adjust variable voltage to 4 5 V and run system for 10 minutes or longer Then decrease in 5 V steps or smaller if necessary until a failure occurs Record this value CAUTION Halt and restart the program each time a new volt age is used when running DECX11 Every system must run between 4 2 V and 7 V If a system failure occurs margin follow ing five signals only SSYN MSYN INTR SACK BBSY If it is not one of these signals that failed continue to margin sections of the bus until a line failure or group of lines is isolated as the problem area Repair the defective line and recheck the margins for Low byte data Address and C lines Request lines NPR BR High byte data Remaining lines When tests are complete turn power off remove special test equipment replace terminator cards and remove tester from power source 4 14 4 5 SINGLE ENDED MAR
57. e via a front panel control and is monitored by a DVM also located on the front panel Any of the Unibus line terminating networks can be connected to this supply by setting the corresponding data switch to VARIABLE 5 Figure 5 1 Unibus Voltage Margin Tester Box The front panel DVM normally monitors the variable supply When the DISPLAY FIXED VOLT AGE button is pressed the DVM displays the voltage of the fixed supply 53 TESTER SPECIFICATIONS The tester contains two dc power supplies a fixed supply and a variable supply Fixed supply 5 Vdcat 2 amps Variable supply 2Vto3Vat2amps The tester is designed for use in the field It is packaged in a brief case type carrying case and weighs 35 pounds The carrying case holds the tester margining heads cables and the manual The tester requires 115 or 230 Vac 10 percent 50 or 60 Hz single phase power 5 2 5 4 UNPACKING PROCEDURE To unpack the UVM TA 1 Remove the carrying case from the shipping carton and inspect for exterior damage Dam age claim should be directed to the responsible shipper 2 Open the carrying case and inspect the components for damage 3 Verify that all components are present See Paragraph 5 2 for Kit Components 5 5 ACCEPTANCE TEST The is shipped ready to use If the unit is not operating properly refer to Preventive Maintenance Paragraph 5 9 to diagnose and correct the problem Service should be performed by qualified personnel o
58. eparated by a bus repeater Refer to Figure 2 3 2 4 11 10 LUMPED LUMPED LOAD LOAD LUMPED LOAD SEMI LUMPED LOAD SEMI LUMPED LOAD ee LUMPED LOAD m SEMI LUMPED LOAD UNIBUS UNIBUS a m SEGMENT SEGMENT CP 2618 This system has two Unibus segments with a total of four lumped loads and three semi lumped loads Lumped loads M930 11 45 CPU DB11 A left side DB11 A right side DDII B four 115 M9301 AU Semi lumped loads 1 M930 11 45 CPU DB11 A left side 2 DBII A right side 3 DDII B four DL11s M9301 Figure 2 3 Semi Lumped Loads Example C 2 2 8 AC Unit Load An ac unit load is defined as a number related to the impedance that a Unibus element presents to a Unibus signal line due to backplane wiring PC etch runs receiver input loading and driver output loading This impedance load on a transmission line causes a reflection to occur when a step is sent down the line This reflection shows up on an oscilloscope as a spike occurring shortly after asserting or unasserting edge An ac unit load is nominally 9 35 pF of capacitance Nine lumped ac loads reflect 20 percent and 20 lumped ac loads reflect 40 percent of a 25 ns risetime step AC loads must be distributed on the Unibus in the manner described by the rules in this manual in order to provide bus operation with reflections guaranteed to be at or l
59. equency loading on different lines by a device P 1 1 12 UNIBUS TROUBLESHOOTING TECHNIQUES Currently there are three troubleshooting aids that can be used to troubleshoot and isolate Unibus problems Hi Lo Terminator Margin Cards 2 Unibus Voltage Margin Tester Box 3 Single Ended Margining Technique A fourth troubleshooting aid is the flowchart refer to Chapter 3 which is organized into a general flow and reference diagram which points out particular sections that contain troubleshooting tech niques and supportive information The supportive information will aid in the understanding of and provide background for the use of the Unibus Troubleshooting techniques outlined in Chapter 3 of this manual 1 3 HI LO TERMINATOR MARGIN CARDS The Hi Lo Terminator Margin Cards are used to replace the M930 bus terminator in the PDP 11 system for margining purposes The Hi Lo Terminator Cards are used as a go no go test and are not to be installed in the system on a permanent basis Refer to Chapter 4 for additional operational procedures and descriptions 1 4 UNIBUS VOLTAGE MARGIN TESTER BOX The Unibus Voltage Margin Tester Box is designed to test Unibus driver and receiver terminating networks for the PDP 11 system The tester is connected to the Unibus through special terminator cards called margining heads When the tester is cabled to the Unibus the operator can select which signal s single groups or all is to be tested
60. es The Unibus Trouble shooting Flowchart Figure 3 1 is designed to provide a step by step procedure for checking and correcting Unibus problems The flowchart references chapters and paragraphs which contain addi tional information and possible solutions to solve Unibus problems are included for reference 3 2 TIMING CONSIDERATIONS Some system failures such as address errors missing data illegal traps and system halts can occur because of bus timing relationships 3 2 1 DATO DATOB The Unibus specification states that MSYN must be asserted 150 ns minimum after the address control and data for DATO and DATOB transactions This delay includes 75 ns to allow internal logic in the slave device to decode the address If MSYN is asserted before 150 ns insufficient deskew and signal decoding at the slave may result in errors An 8881 driver and an 8640 receiver combination can cause up to 60 ns of skew leaving as little as 15 ns as the allowable skew because of the Unibus transmission media The most timing sensitive lines have been found to be BBSY MSYN SSYN and INTR Cable length and configuration can be a noticeable factor in these lines 3 2 2 DATI DATIP For a DATI or DATIP operation the slave puts requested data on the D lines and then asserts SSY N The slave should not assert SSYN at the driver input before the data and enable lines are valid at the data driver inputs The critical point seems to be around 35 40 ns skew in SSYN vs
61. ess than a tolerable level 2 5 The unit load rating of Unibus elements is usually based on greatest of the capacitances that the element presents to the BBSY SSYN and MSYN Unibus signal lines Appendix C contains the ac loading specifications of the Unibus elements If the element is customer designed its ac unit loading must be determined from a reasonable estimate of the equivalent capacitance presented to the Unibus 2 2 9 DC Unit Load dc unit load is defined as a number related to amount of dc leakage current that Unibus element presents to a Unibus signal line which is high undriven A dc unit load is nominally 105 uA 80 receiver plus 25 driver However the dc unit load rating of a bus element is not strictly based on the element s signal line that has the greatest leakage e g dc leakage is less important on D lines than it is on SSYN The dc unit loading of an element should always be obtained from the specification for that element see Appendix D It should not be obtained from a calculation of the receiver and driver leakage current unless the element is custom designed and is not listed in the applicable documentation 2 2 10 Unibus Length and Loading The Unibus is a transmission line on which data transfers are asynchronous and interlocked Signifi cant electrical delay affecting system operation may therefore be imposed through unnecessarily long Unibus cables With ribbon cable
62. et screwdriver 4 Remove the transformer unscrew the four mounting bolts at the base of the transformer using a screwdriver Unsolder the transformer connecting leads 3 To remove the fan first remove the fan mounting bracket assembly from the tester using a Phillips head screwdriver Unsolder the fan connecting leads Then remove the fan from the mounting bracket using a socket head screwdriver and a Phillips head screwdriver 5 6 FUSE BLOWN OR MISSING NO NO CHECK FUSES ON REGULATOR BOARDS AND REPLACE IF NECESSARY 110 VAC MEASURED AT FUSEHOLDER YES REPLACE FUSE AC POWER INDICATOR LIT REFER NOTE 1 REPLACE POWER INDICATOR LAMP BAD AC POWER CORD BAD ON OFF SWITCH YES REMOVE AND REPLACE BAD YES POWER CORD REPLACE ON OFF SWITCH AC LINE CORD PLUGGED IN YES ON POWER ON INDICATOR LIT YES FAN NO OPERATING PROPERLY YES DIGITAL NO VOLTMETER TESTER BLOWING FUSES YES DISCONNECT UNIT FROM AC POWER SOURCE AND ISOLATE PROBLEM S gt TURNED MEASURE AC VOLTAGE BETWEEN LUGS T1 AND 2 OF T1 REPLACE FAN IF NECESSARY DC POWER LAMPS 11 AND 12 ON REGUALTOR BOARDS LIT NO USE VARIABLE CONTROL AND ADJUST FOR 3 VDC ON DVM DISCONNECT YES P2 FROM J1 ON 5 FI
63. f this value R 2 the line will behave like an infinitely long line i e appear resistive see Figure 3 5 The impedance 2 of Unibus BC11 cable is approx imately 120 ohms with Unibus foam and as low as 60 80 ohms unfoamed 1200 R TERMINATION CP 2590 Figure 3 5 BC11 Unibus Cable Impedance Example When a voltage is applied to the line the instantaneous power consumed will be 2 7 P E 120 Suppose now that the terminating resistor R is not equal to the characteristic impedance of the line The power which is traveling down the line before it reaches the termination during propagation delay is equal to E Z but the power dissipated in the resistor after propagation delay is approx imately equal to 2 If resistance R is greater than the impedance Z there will be extra energy available at the termi nation and since energy cannot simply disappear it will be reflected back into the line After one more propagation delay for the return journey this reflection will be seen back at the source see Figure 3 6A 3 8 SOURCE TERMINATION Figure 3 6 Impedance Mismatch Example Some of this reflection will be dissipated by the source impedance and some will be re reflected back into the line When this re reflection is seen at the termination Figure 3 6B after still another propa gation delay the energy difference will be reflected back to the source Eventually both source and termin
64. for any nicks cuts or sharp creases discard the cable if unserviceable Separate the cables and apply the foam tape to both edges for the entire length of the cable Retape the two mylar cables together with electrical tape Foam is sandwiched between cables and a single flat cable results Do not squeeze the cables together at the taped points If two BC11 cables run parallel to each other for any distance foam should be placed between them See Figure A 6 for multiple cable foam installation Figure A 6 Multiple Cable Foam Installation A 6 APPENDIX 9202 2 UNIBUS JUMPER INSTALLATION 1 GENERAL Reflections on the Unibus can be caused by termination mismatch stubs or loads Stubs cannot be matched any stub will cause a reflection Backplanes have wires attached to the Unibus which act as stubs In addition to this individual modules may have bus lines carried on etch which adds length to the backplane stub Individual device options cause reflections on the Unibus which are called signa tures These signatures combine to form the composite waveform seen on the bus See Figure B 1 CP 2611 Figure Composite and Signature Waveforms B 1 level change in theory should be a clean transition Devices placed on the bus may contribute signature reflections Many devices in close proximity may contribute to composite reflections great enough to cross over the threshold level of bus receive
65. he NPR Devices with Variable Speed Maximum Data Transfer Rate Maximum Device NPR Rate CD11 E 1000 1 33 kHz 11 1200 1 6 kHz DAII B DR1I B 500 000 word s 500 kHz 16 X 9600 Baud 15 4 kHz 10 000 kHz 2011 1 Megabaud 100 kHz GT40 20 us point 50 kHz 2 19 NPR DEVICE SEQUENCE ON UNIBUS CPU MEMORY GIVEN CPU MEMORIES AND DEVICES IN PDP11 SYSTEM gt 90 KHz NPR RATES PLACE MEMORIES RK11 RKOB 80 KHz CLOSEST TO CPU 90 KHz gt 36 KHz NO RATE OF DEVICE FIXED TM11 TU10 36 KHz 15 RATE DEVICE KNOWN amp 36 KHz gt 5 KHz TC11 TUB56 5 KHz ASSUME MAXIMUM XFER RATE FROM NPR SEQUENCE CHART lt 6 KHz gt 1 7 KHz 8504 T1 87s DOES DEVICE BELONG NO TO CATEGORY 2 SEE TEXT RJPO4 T1 132 3 15 DEVICE ON NPR CHART RK611 RKO6 T1 212 ys 28 15 RJSO3 405 971 23145 DEVICE SEE TEXT CALCULATE T1 SEE TEXT RP11C RPO3 1 463 5 IS NPR RATE 1 7 KHz RJSO3 8us wd T1 4875 PLACE DEVICE IN ORDER OF INCREASING T1 PLACE DEVICE I IN ORDER OF lt VALUES BEFORE ANY CATEGORY 1 PLACE DEVICE IN DECREASI
66. itcase tester and place to one side This allows room for the cabling to be connected into the tester box 2 Remove test heads M9303 M9303 Y A and 1 from inside the top cover pocket Place all signal switches 56 total in the down or FIXED position Place power switch in the OFF position 3 Turn system power off Remove the M930 terminators from both ends of a section of bus in the unit under test and replace with the M9303 margining heads M9303 Y A for 11 40 CPUs 4 Plug the Unibus cable BC11A into the margining heads 5 Plug the BC11 A power cable into the margining heads Plug the BC11 A cable into tester slots and 2 CAUTION Plugging the BC11 A Unibus cable directly into a CPU or peripheral without the test heads M9303 YA may cause the Unibus drivers to burn up 4 13 10 12 13 Plug tester box ac cord into a convenient power source Power now be applied to system and the tester Place power switch the ON position and adjust the variable voltage to 5 V Load recommended programs DECX11 or operating system NOTE Signal switches must not be switched while the sys tem is running Always halt the system before attempting to change selection switch setting There is one switch for each of the designated bus signals and is labeled on the tester box control panel By setting a switch in the VARIABLE position the margin voltage displayed is applied to the indivi
67. ith options containing drivers and receivers attached to it and another terminator in that order A single bus system is one which has one bus segment A multiple bus system is one which has more than one bus segment usually separated by bus repeaters DB11s or bus switches DTO3s which contain bus repeaters 2 1 2 2 2 Bus Cable is defined as cable connecting two backplanes which acts as 120 ohm transmission line with a length of two feet or more A BC11A cable is defined to be both a cable and a bus element For our purposes the cable is a subset of the bus element and should be treated as such The following bus elements are Unibus cables 2 2 foot Unibus cable 60 96 cm 3 3 foot Unibus cable 91 44 cm 5 5 foot Unibus cable 1 52 m 6 gt 6 foot Unibus cable 1 82 m 11 8 8 5 foot Unibus cable 2 59 m BC11A 10 10 foot Unibus cable 3 04 m BC11A 15 15 foot Unibus cable 4 57 m BC11A 20 20 foot Unibus cable 6 07 m BC11A 25 25 foot Unibus cable 8 60 m BC11A 30 30 foot Unibus cable 9 14 m M9202 24 inch folded Unibus cable 60 96 m The M9202 is considered to be a cable for the purposes of this manual because it contains 2 feet of 120 ohm cable 2 2 3 Bus Element A Bus Element is defined as any module backplane cable or group of these items that has a common designation which has a direct electrical connection to one or more Unibus signal lines other
68. loads AC unit loads equal 27 18 9 27 lumped at the ends of the BC11As of equal length One way to implement Rule No 4 is to increase the length of one cable to 4 57 m 15 ft see Figure 2 11 LUMPED LOAD LUMPED LOAD AFFECTED BC11A 16 LUMPED BC11A 10 WITH 9 AC LOAD UNIT LOADS UNIT LOADS CP 2570 Figure 2 11 Rule No 4 Implementation Example A Block Diagram Another way is to split lumped load on left into two lumped loads using an M9202 see Figure 2 12 LUMPED LOAD LUMPED LOAD AFFECTED LUMPED LOAD WITH 9 AC WITH 9 AC BC11A 10 LUMPED BC11A 10 WITH 9 AC UNIT LOADS UNIT LOADS LOAD UNIT LOADS SEMI LUMPED LOAD WITH 18 AC UNIT LOADS SEMI LUMPED LOAD WITH 9 AC UNIT LOADS 2572 Figure 2 12 Rule No 4 Implementation Example B Block Diagram When this rule is violated and when a driver in the affected lumped load unasserts the bus reflections from the ends of its bus in and bus out cables will arrive at the affected lumped load simultaneously and superimpose The net reflection may cross the 8640 threshold and cause a failure see Figure 2 13 i 8640 THRESHOLD DRIVER REFLECTION REFLECTION NET WAVEFORM WAVEFORM FROM END FROM END AT AFFECTED OF BUS IN OF BUS OUT LUMPED LOAD CABLE CABLE CP 2571 Figure 2 13 Rule No 4 Violation Waveform Example 2 12 When the rule is implemented by making the lengths of bu
69. nly A Tripplet model 630 NA or Simpson model 260 multimeter is required to perform the acceptance test To check out the UVM TA 1 Plug tester ac cord into power source 2 Place 56 signal switches in the down position 3 Turn tester on Verify visually that power indicator is on FIXED DC INTERNAL indicator is on and DVM is displaying a voltage between 1 and 9 Vdc An internal fan will come on This can be verified by listening for the sound of the fan 4 Using the VARIABLE potentiometer vary the internal variable dc supply between 2 and 8 volts This can be verified by observing the DVM Set the variable dc supply to 6 volts The VARIABLE DC INTERNAL indicator will be lit Press DISPLAY FIXED VOLTAGE DVM will read 5 V 5 Using the multimeter probe pin 1 of the test connector 1 Voltage will read 5 Vdc Put ADDRESS REGISTER switch in up or VARIABLE position Voltage will read 6 Vdc Put switch into FIXED or down position and probe similar pin on test connector 2 Voltage will read 5 Vdc Switch to up position Voltage will read 6 Vdc Leave switch up to indicate it has been tested 6 Repeat step 5 for remaining 55 Unibus signal switches 5 6 CONTROLS AND INDICATORS All controls and indicators for the UVM TA are located on the front panel of the unit Figure 5 2 The function of each control and indicator is listed in Table 5 2 57 OPERATING PROCEDURE Refer to Chapter 4 Paragraph 4 4 2 for operating procedures 5 3
70. ntive and corrective maintenance procedures The preventive maintenance procedures should be performed regularly in order to detect any damage caused by improper handling of the unit A troubleshooting flow diagram is provided to aid service personnel in isolating and repairing faults within the tester circuits The troubleshooting flowchart and corrective maintenance information given in this chapter covers only the tester unit The flow diagram makes use of the acceptance test procedure outlined in Paragraph 5 5 To perform disassembly assembly and preventive and correction maintenance only a multimeter and standard hand tools are required Recommended multimeters are 1 Triplett model 630 NA or 2 Simpson model 260 5 9 PREVENTIVE MAINTENANCE As preventive maintenance the acceptance test procedure should be performed from time to time to ensure complete operational readiness and to check the unit adjustments The frequency of the check outs depend on hours of handling and environmental conditions The schedule given in Table 5 3 is suggested as a minimum time table 5 5 Table 5 3 Preventive Maintenance Schedule Performance Interval Test or Procedure Monthly Visually inspect for physical damage correct if required Clean externally Quarterly Clean internally with vacuum cleaner or a soft brush Check for looseness of the knobs switches and indicators Perform acceptance test procedure Paragraph 5 5 5 10 CORR
71. o 3 Maximum lumped loading No lumped load on a Unibus segment should contain more than 20 ac unit loads unless the entire segment consists of one lumped load Rule No 4 Skewed cable lengths If a a lumped load called the affected lumped load has 2 59 m 8 5 ft or longer cables connected to both bus in and bus out and b the sum of the ac unit loads in the two lumped loads connected to the opposite ends of the cables exceeds 18 or the sum of the ac unit loads in the two semi lumped loads connected to the opposite ends of the cables exceeds 36 then the lengths of these cables should differ by 1 52 m 5 ft or more with the longer cable being on the end with the greatest number of ac unit loads if there is a practical choice 2 7 Rule No 5 Skewed cable lengths supplement If the length of one of the cables connected to affected lumped load in Rule No 4 must be increased because of that rule then the longer cable should have at its opposite end of the semi lumped load with the greater number of ac unit loads This rule should be implemented only if it is practical to do so i e in cases where its implementation will not increase total cable length more than 1 52 m 5 ft Rule No 6 Violation of Rules No 1 through No 5 Rules No 1 through No 5 should not be grossly violated If a bus segment violates a rule slightly and for practical reasons reconfiguring is undesirable then the segment must pass voltage m
72. oblems The is a portable device see Figure 5 1 designed to check all Unibus receivers and drivers in a system by applying a margining voltage to the Unibus lines The tester provides a dc termination voltage to special terminator boards These special terminator boards called margining heads are used in place of the standard M930 terminator The margining heads do not change effective Unibus length 5 2 TESTER KIT COMPONENTS The complete tester kit consists of the components shown in Table 5 1 Table 5 1 Tester Kit Components Number Description Part Number 1 Tester 2 Margining head M9303 2 Margining head M9303 YA TBS Unibus Cable 11 1 UVM TA Troubleshooting Guide The UVM TA is a relatively simple electrical Unibus testing device It contains two dc power supplies a fixed supply and a variable supply a digital voltmeter DVM to monitor the power supplier and 56 SPDT switches The fixed 5 Vdc power supply provides the voltage normally used to terminate the Unibus lines Any of the 56 Unibus line switches placed in the fixed position will connect the terminating network of the selected line to the fixed supply This allows the operator to keep certain lines at the normal termi nating voltage while varying the terminating voltage on other lines The fixed supply also supplies power to the DVM The variable dc power supply provides between 2 and 8 Vdc to margin Unibus lines The supply is adjustabl
73. of thumb is 3 42 079 UVM TA 2 V busline 4 5 3 SACK Timeout In some processors if SACK is not received within ten ms after a grant is issued the processor will timeout and proceed as if no grant had been issued unless of course a request line continues to be asserted In others the processor will continue to wait for the return of sack this will cause the bus to hang This problem is solved on some terminators by turning bus grant around and sending SACK back to the CPU The processor will then release BBSY and if no device is requesting will immedi ately regain control of the bus through the passive bus release mechanism The M9308 margin head will turn bus grant around into SACK and set a latch There is a LED installed on the M9308 to remember the fact that a grant was received not a normal condition at the end of the bus Switches are provided to enable SACK turnaround and reset the latch see Figure 4 17 NOTE If SACK turnaround is enabled the M9308 must be used at the electrical end of the bus 4 6 MODIFYING M930 TERMINATOR CARD If the test equipment previously described is not avilable it is still possible to employ voltage margin ing techniques 4 6 1 Equipment Required 1 Variable dc power supply with a percent a regulation or better and a 2 amp output rating minimum 2 Modified M930 Terminators two each 4 2 BUS NPG BUS BG7 H BUS BG6 H BUS SACK L BUS 805 H BUS 804
74. oltage is varied between these values it may be possible to detect and or aggravate bus problems and thus make it easier to define and correct the failures At present there are two methods that can be used to change the quiescent levels on the Unibus for margining purposes 1 Use a Unibus Voltage Margin Tester Box to vary the source voltage applied to the termi nator network 2 Hi Lo Terminator Cards to vary the terminator network rather than the voltage The hardware required for this method is less expensive and more portable than the Unibus Voltage Margin Tester Box however this method is more difficult to use for trouble shooting Unibus failures NOTE A third method referred to in this manual as the single ended margining techniques is an extension of the UVM TA method described in item 1 This method must be used for those processors that employ Sack turnaround or Bootstrap functions on the terminator cards 42 BUS QUIESCENT LEVELS Normal bus quiescent levels are listed in Table 4 1 Any level that deviates from the normal level should be considered as a potential failure In many instances the improper level will be the result of either a defective bus receiver or driver In the case of AC DC LOW these levels are power supply dependent Table 4 1 Bus Quiescent Levels Quiescent Level BG 7 4 45 V 50 35 NPG AC Low 4 9 0 35 DC Low Others 3 4 0 2 V Except BBSY which de
75. on qasinogqs spuq qog 1 pasq 6 006 0860 OZ VI 0 lt 11 se TT TT Oc TI SI TI 01 11 50 11 0 11 20 11 4 19 Thevinen equivalent impedance of the circuit is found by shorting generator and calcu lating the circuit impedance 1239 2561 The equivalent voltage source can be represented by a circuit consisting of a 3 42 V source in series with an impedance of 123 157 ohms 118 42 CP 2562 The termination network used on the M9308 single ended margin terminator consists of 180 ohms to the voltage source and 562 ohms to ground see Figure 4 16 If this network is considered a Thevenin generator it becomes a source of 78 9 percent X voltage applied because of the voltage divider action in series with 118 4 ohms R1 1232 118 4 a 5 BUS LINE 5620 BUS LINE Figure 4 16 M9308 Termination Circuit Example CP 2563 4 20 The voltage seen bus line may be computed by considering what happens when these two generators are connected together For example if the M9308 has 7 85 volts applied to it E 616 342 2 74 V 2 Rr 1230 118 40 241 40 3 11 35 mA 4 Voltage drop across Ry 11 35 mA X 1239 1 396 V 5 Voltage on the bus line 3 42 1 396 4 8 V In this application since the Thevenin equivalent impedances are similar a simple rule
76. or smaller increments if necessary until a failure occurs Record this value CAUTION Halt and restart the program each time a new volt age is selected when running DECX11 Adjust variable voltage to 4 0 V and run system for 10 minutes or longer Then decrease in 5 V steps or smaller if necessary until a failure occurs Record this value CAUTION Halt and restart the program each time a new volt age is used when running DECX11 Every system must run between 2 93 V and 7 85 V If system failure occurs margin the following five signals only SSYN MSYN INTR SACK BBSY 4 16 12 the problem is not with one of the above signals continue to margin sections of the bus until a failing line or group of lines is isolated as the problem area Repair the defective line and recheck margins for Low byte data Address C lines Request lines High byte data Remaining lines 13 When tests are complete turn power off remove special test equipment replace terminator module and remove tester from ac power source If margin values are recorded for future use be sure to note that these values were obtained with single ended techniques 4 5 2 Single Ended Circuit Consideration The user of the single ended margining technique should be aware of the theory and application of the Quiescent Voltage versus UVM TA Voltage considerations Calculations are not necessary because Figure 4 15 is designed to provide thi
77. pends on CPU type 4 1 To measure quiescent Unibus levels 1 Turn the system on with the processor halted Press the START key and release it with HALT down 2 Use a calibrated oscilloscope or voltmeter to measure the Unibus signal lines See chart of Unibus slot backplane pins Figure 4 1 NOTE To obtain meaningful readings of bus grant lines BG 4 7 and NPG they should be measured at the grant input of each device down the length of the bus All buses should be checked in multiple bus systems 4 2 1 Quiescent Conditions Low true lines Address Data Control and Arbitration The low true Unibus lines are characterized by a termination at both ends and some number of loads determined by the system configuration as shown in Figure 4 2 In the quiescent conditions we are dealing with dc levels Ignoring loads for a moment consider the equivalent Unibus line circuit based on termination alone as shown in Figure 4 3 The quiescent dc level on the line may be calculated using Ohms law where E RI R2 5 89 191 5 0 0178A IXR2 0 0178X191 5 3 4087 3 41 volts the potential on the line were measured with respect to ground it would be 3 41 volts as shown in Figure 4 4 In theory the loads should not affect the quiescent level of the bus lines but in practice this is impos sible to achieve To be considered acceptable one load cannot contribute more than 210 pA of leakage current see Chap
78. per module M981 There are Hi Lo terminator cards to fit this appli cation also M9305 low margin and M9305 Y A high margin Margin terminators are used go no go test and are to be installed in the system permanent basis They are too lar ge to fit in an expander box with the covers closed which will help avoid this mistake Figure 4 10 illustrates the circuit representation of the Hi Lo terminator cards plus represen tative load values WARNING When using special terminators it is important that the same type Hi or Lo be installed at both ends of the bus for the test to have meaning Figure 4 9 Margining Cards 4 9 5 1210 1219 UNIBUS UNIBUS 196 9 301 Q HIGH LOW 2601 Figure 4 10 Hi Lo Terminator Circuit Example High Margin M9304 YA Replaces the M930 Terminator 2 M9305 YA Replaces the M981 special case 11 35 11 40 terminator Quiescent 5 V IR drop caused by loads Failures here usually caused by weak drivers receiver with marginal threshold or dirty bus cable contact fingers Low Margin l M9304 Replaces the M930 2 M9305 Replaces the M981 special case 11 35 11 40 terminators Quiescent 3 03 drop caused by loads Failures here usually caused by a receiver with marginal threshold or reflections on MSYN SSYN INTR BBSY 4 4 UNIBUS VOLTAGE MARGIN TESTER BOX The Unibus Voltage Margin Tester UVM TA is a porta
79. percent terminators should be used CAUTION Some etch terminators were manufactured with missing etch runs Pins ANI API ARI and ASI should be connected to pin These runs were omitted The missing etch runs are grounds and if not present may contribute to system noise A 1 2 Revision D Etch ECO No 4 to the M930 Unibus Terminators adds four decoupling capacitors and improved ground ing This change significantly decreases noise on the bus Rev D is the optimum etch revision currently used Sept 1976 and should be used if bus problems are suspected because of old type etch boards There are other terminators which will be available for new processors and systems in the near future A BUS RECEIVERS A number of integrated circuit types i e chips have been or will be used as Unibus receivers Table 1 Of these the DEC 380 was most common It has been phased out and is no longer available A recent series of ECOs to most options which used the DEC 380 now uses DEC 8640 Bus receivers The DEC 8640 is a pin compatible replacement for the DEC 380 and is used in Unibus applications because it has more closely defined specifications and higher noise immunity see Figure A 1 Sub stituting one DEC 8640 on a module does not necessitate changing all DEC 380s these chips may reside in any combination This is a phase in and field rework is not intended except for repair purposes 380 8640 2585
80. permanent basis if required The M9202 will not fit in 11 or 11 mounting boxes In these systems use 2 cables BC11A 10 10 BUS CABLE MF11LP 24K 2613 Figure B 3 Configuration Using M920 Using the configuration shown in Figure B 3 the following waveforms see Figure B 4 were obtained at SSYN the backplane 1 V em 40 nsec div 380 THRESHOLD FALSE SSYN REAL SSYN SSYN AS SEEN AT RK11C SSYN as seen at RK11C with M920 jumpers replaced by 2 bus jumpers 2614 Figure B 4 Jumper Threshold Levels APPENDIX AC AND DC LOAD TABLE AC amp DC LOAD TABLE idein bini LOAD RESULTS NOTE3MEASURE DATE OPTIONS nc MSYN SSYN COR OTHER INFOR donis dede da de de de de diy dio do dedo de do die e di die ci dr de 9 cie do en AA11 K 4 2 47 1 80 3 22 121576 4 1 4 1 4 1 59 2 26 051076 AR11C 47389 6 1 5 89 5 42 5 16 692375 792 4 8 873 4 1 9 75 1 91 3 84 101575 3 1 1 91 1 0402 2 75 092375 044 gt 9 1 1 6 1 5 75 4 24 4 33 092275 08119A RIGHT 6 1 5 19 3 3 3 19 29227
81. pull up resistor has been added to the grant receivers of each device This significantly reduces reflections and false grants on the bus i e traps to 0 traps to 4 and undefined interrupts A 3 1 Rework Procedure Obtain a supply of 1809 resistors These may be ordered under DEC P N 13 01322 2 Using the proper print set for each option locate the grant receiver input 3 If no 1800 pull up resistor is installed from the input of the grant receiver to 5 V install one refer to the applicable ECOs NOTE Bus switches and repeaters already have these resist ors installed CAUTION Some devices receive more than one grant line and many devices receive both NPG and BGxx signals AM grant receivers should be terminated in this manner To maintain termination consistancy 1809 pull up could be added at the receiver a 390 pull down could be added at the driver If a device with the driv er pull down were used with a device which did have the receiver pull up the assertion level would not be high enough to ensure reliable operation 4 CABLE FOAM The cable see Figure A 4 consists of two 60 conductor mylar Flex print cables used to connect system units in different mounting cabinets or to connect peripheral devices not located within the cabinets The two Flex print cables are taped together to form a single flat 120 conductor cable In system applications there is little con
82. r The M920 Unibus jumper module double module connects the Unibus from one system unit device to the next Its length is very short electrically If device options are installed in close proximity to each other lumped loads their signatures may combine to place a large reflection and false information on the bus If these signatures could separated they would not present such a problem The M9202 2 Unibus Jumper Module is physically compatible with the M920 however it induces some delay and lessens the effect of lumped loads The same signatures shown in Figure B 2 can be separated to reduce the composite signal This will prevent composite signal from crossing the bus receiver threshold and thus from presenting false information due to large reflections RECEIVER THRESHOLD MULTIPLE REFLECTIONS SEPARATED IN TIME TO PREVENT THIER PEAKS FROM COMBINING CP 2612 Figure 2 Separation of Multiple Reflections This does not altogether eliminate the source of the problem however it does offer a reasonable alternative for reducing the effect of reflections B 1 2 Jumper Installation A first pass approximation is to install one M9292 2 bus jumper between each 4 to 8 unit loads replace the existing M920 with a M9202 Refer to Chapter 2 for detailed configuration rules NOTE The M9202 is a useful troubleshooting aid and should be left in the system on a
83. re than one line Category Devices whose controllers have six or fewer words of data buffer excluding RFII RSI1 which although it has only one word data buffer falls more closely into category 2 simply because it can wait for a maximum of three disk revolution time or 100 ms without getting data late errors Other devices in this category are CD11 DH11 GT40 RK11 RK05 TM11 TU10 and TC11 TUS6 Category 2 Devices whose controllers have more than six words of data buffer including 11 511 as described under category 1 Devices included in this category are RJS04 RJPO4 RK611 RK06 RJSO3 RPIIC RPO3 TJU45 16 and RF11 RS11 2 4 2 NPR Calculations for T1 NPR rates of category 1 devices can be computed in one of the following ways NPR RATE baud rate 10 may be different for different devices or word s or card min X 1 33 Within Category 1 devices with higher NPR rates should be placed before devices with lower NPR rates 2 22 2 4 3 Latency Tolerance Calculations The process of determining category 2 device sequence can be simplified by comparing maximum tolerance between bus cycles of each device which can be computed as follows TI TDBS TBBLUP X 2 where TDBS Timeto transfer DBS words to from the device in us DBS Data buffer size of the device controller for RH11 DBS 66 TBBLUP Typical data bubble up time of the device controller for
84. s in and bus cables different the reflections will arrive at slightly different times see Figure 2 14 DRIVER REFLECTION REFLECTION WAVEFORM FROM END FRUMEND OF BUS IN OF BUS OUT CABLE CABLE 8640 THRESHOLD 44 112 oru ro NET WAVEFORM AT AFFECTED LUMPED LOAD CP 2573 Figure 2 14 Rule No 4 Implementation Waveform Example Now the reflection does not cross the 8640 threshold and the danger of a failure is reduced The configuration in Figure 2 12 does not violate Rule No 4 because the sum of the ac unit loads lumped at the ends of the BC11A 10 cables is 18 9 9 18 and sum of ac unit loads in the semi lumped loads at the BC11A 10 s ends of the cables is 9 plus the lumped loads 18 for a total of 27 unit loads 9 18 27 Either of these methods could be used to implement Rule No 4 but the second is more desirable in this example because it minimizes the total cable length of the segment 2 3 5 Skewed Cable Lengths Supplement Rule No 5 To understand why this rule is necessary consider the following example Figure 2 15 LUMPED LOAD WITH 20 AC UNIT LOADS LUMPED LOAD WITH 20 AC UNIT LOADS LUMPED LOAD WITH 20 AC UNIT LOADS t SEMI LUMPED LOAD WITH 60 AC UNIT LOAD LUMPED CABLE 1 A ERTED CABLE 2 WITH 20 LUMPED gt 2 59 8 5 ft LOAD gt 2 59 m 8 5 ft AC UNIT
85. s information However the difference must be made between single ended and double ended margining techniques because of the different voltages that must be applied by the UVM TA tester under these conditions Table 4 2 supplies terminator application data for the M9308 single ended margin head plus double ended terminators and how they relate to particular CPU bus segments In bus segments not including a CPU the same procedures apply According to Thevinen s Theorem any line or network of impedance and generators when viewed from any two points in the network can be replaced by an equivalent voltage source and an equivalent impedance in series As an example consider the termination network used on the M930 Unibus terminator The voltage looking back into the network will be 3 42 V because of the voltage divider action of R1 and R2 This is an equivalent voltage source of 3 42 V CP 2560 4 17 8 1 98 1 90 9 210814 9092 49 318n00Q 315NIS 319NIS IVWHON bey 315NIS HDIH 5874 TM 62 LIWN iaioa 8 4 9 1VWNHON S v L z a18noa 1VWHON 319NIS rmx e ee a ey v NIDHVIN Lan 4 18
86. some BR devices may be put before NPR devices e g a DECwriter may be placed next to the CPU 2 4 5 Unibus Loading Rules Maximum loading before the first bus repeater is 19 dc bus loads between two adjacent bus repeaters is 18 dc bus loads Maximum Unibus cable length between the first bus repeater and the CPU or between the adjacent bus repeaters is 15 24 m 50 ft For example configure a system with 11 45 128K of MF11 UP DL11 A LA30 KW11 L 11 05 RJS04 RJPO4 DH11 at 12 5K baud 11 11 TJU16 GT40 CDII E Latency tolerance capacities of devices in category 2 are defined and computed using Latency Tolerance Capacities of NPR Controllers Devices and Configuration Guidelines 4 23 15 2 23 After going through Figure 2 20 and Table 2 2 the following sequence results Device Unibus Loads 11 45 2 1 DL11A LA30 1 128K 1 8 RK11 RK05 90 kHz 1 GT40 50 kHz 1 RJS04 1 4 1 TJU 16 1 RFI1 RSI1 1 15 4 kHz 2 1 33 1 1 25 kHz dl TOTAL 22 UNITLOADS There are a total of 22 unit loads Therefore a DB11 A is added at the end and DH11 1 and CDII E are repositioned after DB11 A NOTE The NPR device sequence algorithm does not take into account the measures of the usage of the devices For example suppose that in the system given above GT40 is seldom used GT40 may be placed behind RF11 RS11 to
87. standards and there was little concern about how long a device took to complete a transaction on Unibus systems have expanded in size and devices have become faster and software more stringent in its I O demands the need for NPR devices to complete their transactions and release the Unibus to another device as soon as possible has become imperative If an NPR device holds BBSY asserted on the Unibus for an abnormally long period of time that device in some configurations could crowd out another NPR device competing for Unibus time forcing an error condition to occur It should be evident then that Data Lates being reported by one device may be caused by another device on the system being a hog The following paragraphs will show how to predict nominal BBSY time for a given configuration and how to measure the actual BBSY times Guidelines are included to help determine whether or not the measured BBSY times fall within an acceptable range around the predicted value 2 5 2 Calculating Nominal Bus Busy Times NOTE It doesn t matter if the calculations necessary to pre dict a BBSY time are performed first or if the meas urements are made first In some cases however it is necessary to determine if a device is conducting single cycle or double cycle transactions as this will affect the calculations that must be made This will be true of some Massbus devices RH11 If in doubt proceed to Paragraph 2 4 3 and
88. t F S 11 Product Support in Maynard 2 16 2 3 8 Actual Bus Loading PDP 11 systems are configured to have no more than twenty loads or 15 24 m 50 ft of Unibus cable on a given bus Most devices are specified in terms of whole number loads but in fact this is not always the case Table 2 1 lists realistic numbers for various options and using the system shown Figure 2 19 it is seen how loading may differ from that determined by conventional configuration guidelines NOTE If quiescent voltages are correct then dc loading is probably not a problem 11 40 CPU BM 873 KW11P DL11 TM11 LP11 BUS LOADS ACTUAL 380 RECEIVERS ACTUAL 8640 RECEIVERS CP 2578 Figure 2 19 Actual Bus Loads Example Caution must be exercised in customer situations the published loading specifications for each device as listed in Appendix D must be used in discussions with non DEC personnel Table 2 1 is included only for your information Refer to Chapter 3 Paragraph 3 3 2 17 11 11 11 11 ADOI AFCII 792 873 CD11 DAIIB DH11 DLII DMIIBB DPI DRIIB DRIIC DTO3F DX11 GT40 KWIIL KWIIP LPS11 1511 792 No of Drivers 5 5 5 5 5 3 2 1 0 2 3 4 4 2 2 1 3 1 2 2 4 2 2 3 4 2 4 2 2
89. te noise margin and reflec tions from lumped loads will not be excessive To configure a Unibus system the required order of options on the Unibus based on NPR latency physical location etc should first be determined The rules will then determine the length the Unibus cable interconnecting the options and the number and location of bus repeaters If the number of bus repeaters is excessive total cable length can sometimes be reduced by rearranging the order of options on the bus again paying close attention to NPR latency etc Then after reapplying the rules in this guide one or more bus repeaters may be eliminated or located further down the bus to optimize system speed For large systems more than one pass of this procedure may be necessary to achieve satisfac tory results A reasonable effort should always be made to ensure total cable length is as short as possible partic ularly if one or more bus repeaters can be eliminated in the process Bus repeaters are costly and slow down the system Before implementing configuration rules the user should carefully read and under stand the definitions that follow 2 2 UNIBUS DEFINITIONS Prior to configuring the Unibus review the definitions outlined in Paragraphs 2 2 1 through 2 2 10 2 2 1 Bus Segment The Bus Segment is defined as that portion of a Unibus system between and including two terminators bus segment consists a terminator 120 ohm transmission path cable w
90. ter 2 for definition of dc unit load but even this level will have an effect on the quiescent level of the line If 20 loads are added to the original example Figure 4 5 with each drawing 210 uA of current the calculation changes somewhat 20 X 210 wA 0 0042 amps of leakage current The total current through R1 now increases which increases the drop The quiescent level of the line will now be approximately 3 volts 4 2 VIEWED FROM BACKPLANE INIT L A 5 INTR L B Q 00 02 01 04 03 06 05 08 DATA LINES H 07 10 J 09 12 K 11 14 L 13 PA M 15 NO PB PO C BBSY RO SACK soe NPR T BR7 2 Cj BR6 BG7 A 5 865 C BR6 BR4 4 r es AC 01 L H 00 03 J 02 05 04 07 L 06 09 ADDRESS LINES M 08 11 N 10 13 P 12 15 R 14 17 S 16 1 SSYN U CO MSYN 2 45 V V 49V 35 V GND 5 Figure 4 1 Unibus Slot Backplane Signals 4 3 2579 Figure 4 2 Low True Unibus Line 5 5 1780 1780 3839 3839 5 191 50 R2 0178A 2580 Figure 4 5 Equivalent Unibus Line Circuit 5 Ri 3 41 Rz CP 2581 Figure 4 4 Quiescent dc Level Example 210 2582 Figure 4 5 Load Current Leakage Example 4 5 3 7 3 6 QUIESCENT LE
91. the maximum length is 15 24 m 50 ft For proper operation the length of taps or stubs must be minimized The Unibus signals should have receivers and transmitters in one place near the Unibus cable to act as a buffer between the Unibus and the signal lines carrying Unibus signals within the equipment The maximum length of ribbon cable is obtainable only if the individual tap lengths are less than 5 08 cm 2 in including printed circuit etches and if the loading is not more than one standard bus load One bus load is defined as one transmitter and one receiver see Figure 2 4 The Unibus is limited to a maximum of 20 bus loads This limit is set to maintain a sufficient noise margin For more than 20 bus loads a Unibus repeater option DB11 A is used 2 6 TRANSMITTER RECEIVER 1 BUS LOAD 1 TRANSMITTER 1 RECEIVER CP 2564 Figure 2 4 Bus Load Example 2 3 UNIBUS CONFIGURATION RULES The following rules and guidelines are intended to be used for new systems and or existing systems that experience Unibus problems The seven rules are listed below for quick reference more detailed description comments and suggestions are described in the following paragraphs Rule No 1 Maximum cable length The total length of Unibus cable in a Unibus segment should not exceed 15 24 m 50 ft Rule No 2 Maximum dc loading The total number of dc unit loads on a Unibus signal line should not exceed 20 See Appendix D Rule N
92. the receiver in that element will see the following waveform Figure 2 8 DRIVER WAVEFORM REFLECTION NET WAVEFORM OF TWO LUMPED AT RECEIVER LOADS CP 2568 Figure 2 8 Rule No 3 Implementation Waveform Example Now the 8640 threshold is not crossed and the danger of a failure is reduced Rule No 3 states that there is no limit to the number of ac unit loads on a Unibus segment unless the entire segment consists of one lumped load The reason for this statement is that there is no 120 ohm cable in the segment on which reflections can travel The following segment Figure 2 9 is an example 0011 0011 E DL11 A DL11 A LUMPED LOAD a a UNIBUS SEGMENT tS 2569 Figure 2 9 Multiple Bus System Example This segment obeys all configuration rules It has zero 0 feet of cable 20 dc unit loads and an irrelevant number of ac loads In this configuration none of the M920s have to be replaced M9202s 2 3 4 Skewed Cable Lengths Rule No 4 There may be several ways to implement Rule No 4 Considerthefollowing bus segment Figure 2 10 LUMPED LOAD AFFECTED LUMPED LOAD WITH 18 AC BC11A 10 LUMPED BC11A 10 WITH 9 AC LOAD UNIT LOADS UNIT LOADS CP 2619 Figure 2 10 Rule No 4 Violation Block Diagram This segment violates Rule No 4 because the sum of the lumped loads that are connected to the opposite ends of the cables exceed 18 unit
93. trol over how this cable is routed Impedance of the BC11 cable can vary widely due to physical routing and has been found to be in the range of 60 80Q in typical systems Design specification is 1209 ECO No 004 corrects this low impedance problem with the addition of foam between the two mylar cables The impedance of the cable is stabilized at 1200 and is not too sensitive to physical configuration when this foam is installed A 3 aaoo lt 2 12 314 7314 14 1 GND 8 380 7380 8640 11380 NM aN lt 8881 DRIVER 14 11 i B e 5 e 8838 8641 TRANSCEIVER 13 11 12 10 8 9 5 4 2 3 7 14 74H01 DRIVER Figure 2 Pin Assignments of Unibus I C s 15 13 12 10 CP 2586 6 180 0 2610 Figure A 3 Grant Line Termination Figure 4 Cable A 4 1 Foam Installation Procedure Obtain sufficient foam to do the job This may be ordered under DEC part number 90 08881 see Figure 5 The length required will be twice the sum of all BC11 cable lengths in the system plus twice the length of all parallel cable runs Foam Tape Part 90 08881 Figure A 5 Foam Tape Installation Perform the following steps for all BC11 cables in the system Remove the tape holding the two mylar Flex print cables together Examine the cables
94. wn in Figures 2 22 and 2 23 Figure 2 22 shows a device doing single cycle transaction and Figure 2 23 shows a device performing double cycle transactions The key here is the channel 2 trace displaying MSYN If MSYN is seen being asserted once during the BBSY time displayed on channel 1 the device is performing single cycle transfers and the single cycle column in Tables 2 3 2 4 and 2 5 should be used If MSYN is seen being asserted twice during the BBSY time the device is performing double cycles and the double cycle column in the tables should be used for the calculations on that device The BBSY time being displayed on channel 1 is the time to be ultimately concerned with This is the value that should coincide plus or minus 30 percent with the calculated value Once the measurements have been taken for a device issue a control C from the keyboard to stop the run time exerciser When DEC X11 is ready to accept new commands DESelect the device just tested and SELect the module corresponding to the next device to be tested and repeat these procedures until all NPR devices on the system have been measured BBs TIME CHANNEL 1 2 2684 MSYN Figure 2 22 Single Cycle Transaction 2 29 TIME CHANNEL 1 2 1st MSYN 2nd MSYN CP 2685 Figure 2 23 Double Cycle Transaction 2 5 4 Configuration Tables The configuration table Figure 2 24 is presented

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