Xilinx SP601 User's Manual
Contents
1. Table C 1 VITA 57 1 FMC LPC Connections Cont d ie Schematic Netname ul Za ya pns Schematic Netname 9 EB G13 FMC LA08 N E11 H13 FMC LA07 P E7 G15 FMC LA12 P D6 H14 FMC LAO7 N E8 G16 FMC_LA12_N C6 H16 FMC_LA11_P B12 G18 FMC_LA16_P C7 H17 FMC_LA11_N A12 G19 FMC_LA16_N A7 H19 FMC LA15 P G9 G21 FMC LA20 P N7 H20 FMC_LA15_N F9 G22 FMC_LA20_N P8 H22 FMC LA19 P N6 G24 FMC LA22 P R7 H23 FMC LA19 N P7 G25 FMC LA22 N T7 H25 FMC LA21 P T4 G27 FMC LA25 P M11 H26 FMC LA21 N V4 G28 FMC_LA25_N N11 H28 FMC LA24 P U8 G30 FMC LA29 P M8 H29 FMC_LA24 N V8 G31 FMC_LA29_N N8 H31 FMC LA28 P U11 G33 FMC_LA31_P 16 H32 FMC_LA28_N V11 G34 FMC_LA31_N V6 H34 FMC_LA30_P T12 G36 FMC_LA33_P M10 H35 FMC_LA30_N V12 G37 FMC LA33 N N9 H37 FMC LA32 P U15 H38 FMC_LA32_N V15 50 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX SP601 Master UCF Appendix D The UCF template is provided for designs that target the SP601 Net names provided in the constraints below correlate with net names on the SP601 rev C schematic On identifying the appropriate pins the net names below should be replaced with net names in the user RTL See the Constraints Guide for more information NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET2. BPI Memory U10 FPGA U1 Pin Schematic Netname Pin Number Pin H16 FLASH_A6 23 A6 H15 FLASH A7 22 A7 H14 FLASH A8 20 A8 H13 FLASH_A9 19 A9 F18 FLASH_A10 18 A10 F17 FLASH_A11 17 A11 K13 FLASH_A12 13 A12 K12 FLASH_A13 12 A13 E18 FLASH_A14 11 A14 E16 FLASH_A15 10 A15 G13 FLASH_A16 8 A16 H12 FLASH_A17 7 A17 D18 FLASH_A18 6 A18 D17 FLASH_A19 5 A19 G14 FLASH_A20 4 A20 F14 FLASH_A21 3 A21 C18 FLASH_A22 1 A22 C17 FLASH_A23 30 A23 F16 FLASH_A24 56 A24 R13 FPGA_D0_DIN_MISO_MISO1 33 DQO T14 FPGA_D1_MISO2 35 DQ1 V14 FPGA_D2_MISO3 38 DQ2 U5 FLASH_D3 40 DQ3 V5 FLASH_D4 44 DQ4 R3 FLASH_D5 46 DQ5 T3 FLASH_D6 49 DQ6 R5 FLASH_D7 51 DQ7 M16 FLASH_WE_B 55 WE_B L18 FLASH_OE_B 54 OE_B SP601 Hardware User Guide www xilinx com 21 UG518 v1 1 August 19 2009 Chapter 1 SP601 Evaluation Board XILINX Table 1 7 BPI Memory Connections Cont d BPI Memory U10 FPGA U1 Pin Schematic Netname Pin Number Pin L17 FLASH CE B 14 CEO B3 FMC_PWR_GOOD_FLASH_RST_B 16 RP_B Note Memory U10 pin 56 address A24 is not connected on the 16 MB device It is made available for larger density devices FMC PWR GOOD FLASH RST B FPGA DO DIN MISO MISO1 LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC K18 K17 J18 J16
3. SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II See the Elpida DDR2 specifications for more information at http www elpida com en products details EDE1116ACBG html 1 1 Also see the Spartan 6 FPGA embedded hard memory controller block user guide at http www xilinx com support documentation user guides ug388 pdf SP601 Hardware User Guide UG518 v1 1 August 19 2009 www xilinx com 17 Chapter 1 SP601 Evaluation Board g XILINX 3 SPI x4 Flash The Xilinx Spartan 6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACT configuration tool The SPI memory device operates at 3 0V the Spartan 6 FPGA I Os are 3 3V tolerant and provide electrically compatible logic levels to directly access the SPI flash through a 2 5V bank The XC6SLX16 2CSG324 is a master device when accessing an external SPI flash memory device The SP601 SPI interface has two parallel connected configuration options see Figure 1 7 an SPI X4 Winbond W25Q64VSFIG 64 Mb flash memory device and a flash programming header J12 J12 supports a user defined SPI mezzanine board The SPI configuration source is selected via SPI select jumper J15 For details on configuring the FPGA see Configuration Options J12 FPGA PROG B FPGA D2 MISO3 FPGA D1 MISO2 SPI C
4. An n means the signal is active low usr teof nis active low Online Document The following conventions are used in this document Convention Blue text Meaning or Use Cross reference link to a location in the current document Example See the section Additional Resources for details Refer to Title Formats in Chapter 1 for details Blue underlined text Hyperlink to a website URL Go to http www xilinx com for the latest speed files www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX Chapter 1 SP601 Evaluation Board Overview The SP601 board enables hardware and software developers to create or evaluate designs targeting the Spartan 6 XC6SLX16 2CSG324 FPGA The SP601 provides board features for evaluating the Spartan 6 family that are common to most entry level development environments Some commonly used features include a DDR2 memory controller a parallel linear flash a tri mode Ethernet PHY general purpose I O GPIO and a UART Additional functionality can be added through the VITA 57 1 1 expansion connector Features page 10 provides a general listing of the board features with details provided in Detailed Description page 12 Additional Information Additional information and support material is located at e http www xilinx com sp601 This information includes e Current version of this user g
5. GPIO HDR6 GPIO HDR7 GPIO LED 0 GPIO LED 1 GPIO LED 2 GPIO LED 3 GPIO SWITCH 0 GPIO SWITCH 1 GPIO SWITCH 2 GPIO SWITCH 3 IIC SCL MAIN IIC SDA MAIN PHY COL PHY CRS PHY INT PHY MDC PHY MDIO PHY RESET PHY RXCLK PHY RXCTL RXDV PHY RXDO PHY RXD1 PHY RXD2 PHY RXD3 PHY RXD4 PHY RXD5 PHY RXD6 PHY RXD7 PHY RXER PHY TXCLK FPGA MO CMP MISO FPGA MOSI CSI B MISOO FPGA ONCHIP TERMI FPGA ONCHIP TERM2 LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC V16 H R13 H T14 A V14 d y17 DA n Fi U3 n T15 H N12 A T13 H L6 n 5 C2 n V2 n H R16 A A17 Fi D15 H D16 A B18 d p3 n Fi DA n h RE n EA n a F5 n N17 Fi M18 a A3 n T15 E15 H B4 n 2 E13 H P12 A E13 7 C14 x CA n AA n D14 u E12 7 E12 d V13 H pil A N10 H T 14 d M13 H J13 N14 A P16 A 13 H T16 A N18 H M14 d U18 A 017 H T18 H T17 H N16 N15 H P18 Ti P17 3 Bg 54 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX
6. NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET PHY TXCTL TXEN PHY TXC GTXCLK PHY TXDO PHY TXD1 PHY TXD2 PHY TXD3 PHY TXD4 PHY TXD5 PHY TXD6 PHY TXD7 PHY TXER SMACLK N SMACLK P SPI CS Bu SYSCLK N SYSCLK P USB 1 CTS USB 1 RTS USB 1 RX USB 1 TX USER CLOCK LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC B8 n Fi ag A FB n A G8 n a A6 n s B6 n s E6 n F7 n Fi A5 n C5 n i A8 n A H18 Fi H17 Fi V3 n E K16 Fi K15 5 U10 T5 n L12 H K14 V10 H SP601 Hardware User Guide UG518 v1 1 August 19 2009 www xilinx com 55
7. Chapter 1 SP601 Evaluation Board XILINX 12 FPGA INIT and DONE LEDs The typical Xilinx FPGA power up and configuration status LEDs are present on the SP601 The INIT LED DS10 comes on after the FPGA powers up and completes its internal power on process The DONE LED DS9 comes on after the FPGA programming bitstream has been downloaded and the FPGA successfully configured VCC2V5 VCC2V5 FPGA DONE VCC2V5 lINS dqau q31 L Y x Lsa INIT_B 0 LED ON 1 INIT_B 1 LED OFF LWS NY9 041 R90 274 196 1 16W FPGA INIT B UG518 21 070809 Figure 1 21 FPGA INIT and DONE LEDs Table 1 16 FPGA INIT and DONE LED Connections FPGA U1 Pin Schematic Netname Controlled LED U3 FPGA_INIT_B DS10 INIT V17 FPGA_DONE DSI DONE NET FPGA INIT B LOC U3 NET FPGA DONE LOC V17 Figure 1 22 UCF Location Constraints for FPGA INIT and DONE 34 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX Detailed Description 13 User I O The SP601 provides the following user and general purpose I O capabilities e User LEDs e User DIP switch e Pushbutton switches e CPU Reset pushbutton switch e GPIO male pin header Note All GPIO location constraints are collected in one partial UCF in Figure 1 27 User LEDs The SP601 provides four active high green LEDs as described in Figure 1 23 and Table 1 17 GPIO LED 3 G
8. DDR2 A9 LOC D1 DDR2 A8 LOC D2 DDR2 A7 LOC H6 DDR2 A6 LOC H3 DDR2 A5 LOC H4 DDR2 A4 LOC F3 DDR2 A3 LOC L7 DDR2 A2 LOC H5 DDR2 A1 LOC J6 DDR2 AO LOC J7 DDR2 A12 LOC G6 DR2 All LOC D3 DR2 A10 LOC F4 IOSTANDA IOSTANDA IOSTANDA IOSTANDA IOSTANDA IOST IOST IOST IOST IOST IOST IOST IOST TANDA TANDA TANDA TANDA TANDA TANDA TANDA TANDA RD SSTL18 II RD SSTL18 II RD SSTL18 II RD SSTL18 II RD SSTL18 II RD SSTL18 II RD SSTL18 II RD SSTL18 II RD SSTL18 II RD SSTL18 II RD SSTL18 II RD SSTL18 II RD SSTL18 II Figure 1 3 UCF Location Constraints for DDR2 SDRAM Address Inputs www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX Detailed Description Figure 1 4 provides the UCF constraints for the DDR2 SDRAM data pins including the I O pin assignment and I O standard used NET DDR2_DQ15 LOC NET DDR2_DQ14 LOC NET DDR2 DQ13 LOC NET DDR2 DQ12 LOC NET DDR2 DO11 LOC NET DDR2 DQ10 LOC NET DDR2 DQ9 LOC NET DDR2 DQ8 LOC NET DDR2 DQ7 LOC NET DDR2 DQ6 LOC NET DDR2 DQ5 LOC NET DDR2 DQ4 LOC NET DDR2 DO3 LOC NET DDR2 DQ2 LOC NET DDR2 DOQ1 LOC NET DDR2 DQO LOC Figure 1 4 UCF Location Constraints for DDR2 SDRAM Data I O Pins U1 U2 T1 T2 N1 N2
9. M1 M3 mgu WIS H1 H2 KI Ws K2 s VER ns 120 IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II Figure 1 5 provides the UCF constraints for the DDR2 SDRAM control pins including the I O pin assignment and the I O standard used NET DDR2 WE B LOC E3 NET DDR2 U NET DDR2 U DOS P LOC P2 DOS N LOC P1 NET DDR2 UDM LOC K4 NET DDR2 RAS B LOC NET DDR2 ODT LOC K6 NET DDR2 LDQS P NET DDR2 LDQS N L5 OC L4 OC L3 NET DDR2_LDM LOC K3 NET DDR2 CLK P LOC G3 NET DDR2 CLK N LOC G1 NET DDR2 CKE LOC H7 NET DDR2 CAS B LOC K5 NET DDR2 BA2 LOC E1 NET DDR2 BA1 LOC F1 NET DDR2 BAO LOC F2 Figure 1 5 UCF Location Constraints for DDR2 SDRAM Control Pins References IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDA IOSTANDA IOSTANDA IOSTANDA IOSTANDA IOSTANDA IOSTANDAR UU UU UU U U R R R R R R U U
10. SMA Connectors Differential A high precision clock signal can be provided to the FPGA using differential clock signals through the onboard 50 ohm SMA connectors J7 P J8 N NET SMACLK N LOC H18 NET SMACLK P LOC H17 Figure 1 17 UCF Location Constraints for SMA Connectors Connections 9 VITA 57 1 FMC LPC Connector The VITA 57 1 FMC expansion connector J1 on the SP601 implements the VITA 57 1 1 LPC format of the VITA 57 1 FMC standard specification The VITA 57 1 FMC LPC connector provides 68 single ended 34 differential user defined signals Table 1 13 The VITA 57 1 FMC standard calls for two connector densities a High Pin Count HPC and a Low Pin Count LPC implementation A common 10 x 40 position 400 pin locations connector form factor is used for both versions The HPC version has 400 pins present the LPC version 160 pins The Samtec connector system is rated for signaling speeds up to 9 GHz 18 Gb s based on a 3dB insertion loss point within a two level signaling environment Refer to the Samtec website for data sheets and characterization information for the RoHS compliant VITA 57 1 FMC LPC connector ASP 134603 01 and its mate Note that the SP601 board FMC LPC connector J1 VADJ voltage is FIXED at 2 5V non adjustable This rail cannot be turned off The SP601 VITA 57 1 FMC interface is compatible with 2 5V Mezzanine Cards capable of supporting 2 5V VADJ The SP601 supports all FMC LA Bus conne
11. 1 Spartan 6 XC6SLX16 2CSG324 FPGA A Xilinx Spartan 6 XC6SLX16 2CSG324 FPGA is installed on the Embedded Development Board Configuration The SP601 supports configuration in the following modes e Master SPI x4 e Master SPI x4 with off board device e BPI e JTAG using the included USB A to Mini B cable For details on configuring the FPGA see Configuration Options I O Voltage Rails There are four available banks on the LX16 CS324 device Banks 0 1 and 2 are connected for 2 5V I O Bank 3 is used for the 1 8V DDR2 component memory interface of Spartan 6 FPGA s hard memory controller The voltage applied to the FPGA I O banks used by the SP601 board is summarized in Table 1 2 Table 1 2 I O Voltage Rail of FPGA Banks FPGA Bank 0 I O Voltage Rail 2 5V 1 2 5V SP601 Hardware User Guide UG518 v1 1 August 19 2009 www xilinx com 13 Chapter 1 SP601 Evaluation Board 14 Table 1 2 VO Voltage Rail of FPGA Banks Cont d XILINX FPGA Bank I O Voltage Rail 2 2 5V 3 1 8V References See the Xilinx Spartan 6 FPGA documentation for more information at http www xilinx com support documentation spartan 6 htm 2 128 MB DDR2 Component Memory There are 128 MB of DDR2 memory available on the SP601 board A 1 Gb Elpida EDE1116ACBG 84 ball DDR2 memory component is accessible through Bank 3 of the LX16 device The Spartan 6 FPGA hard memory cont
12. SP601 Hardware User Guide www xilinx com 23 UG518 v1 1 August 19 2009 Chapter 1 SP601 Evaluation Board 24 Table 1 9 PHY Connections Cont d L14 M13 J13 N14 P16 T 13 L16 iis E Schematic Netname U3 M88E111 P18 PHY_RXD7 120 A9 PHY TXC GTXCLK 14 B9 PHY TXCLK 10 A8 PHY_TXER 13 B8 PHY_TXCTL_TXEN 16 F8 PHY TXDO 18 G8 PHY_TXD1 19 A6 PHY_TXD2 20 B6 PHY_TXD3 24 E6 PHY_TXD4 25 F7 PHY_TXD5 26 A5 PHY_TXD6 28 C5 PHY_TXD7 29 NET PHY COL LOC NET PHY CRS LOC NET PHY INT LOC NET PHY MDC LOC NET PHY MDIO LOC NET PHY RESET LOC NET PHY RXCLK LOC NET PHY RXCTL RXDV LOC NET PHY RXDO LOC NET PHY RXD1 LOC NET PHY RXD2 LOC NET PHY RXD3 LOC NET PHY RXD4 LOC NET PHY RXD5 LOC NET PHY RXD6 LOC NET PHY RXD7 LOC NET PHY RXER LOC NET PHY TXCLK LOC NET PHY TXCTL TXEN LOC NET PHY TXC_GTXCLK LOC NET PHY TXDO LOC NET PHY TXD1 LOC NET PHY TXD2 LOC NET PHY TXD3 LOC NET PHY TXD4 LOC NET PHY TXD5 LOC NET PHY TXD6 LOC NET PHY TXD7 LOC NET PHY TXER LOC N18 M14 U18 U17 T18 T17 N16 N15 P18 P17 B9 B8 A9 FB G8 A6 B6 E6 e ET AS C5 A8 XILINX Figure 1 11 UCF Location Constraints for PHY Connections www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILI
13. 1 0 1 3 mn 1 8V 8A 1 2 3 0 2 0 5 0 Ko 1 2V 8A Vrr 0 9 1 0 1 0 LTC3413 0 9V 1 0A SP601 Hardware User Guide www xilinx com 41 UG518 v1 1 August 19 2009 Chapter 1 SP601 Evaluation Board XILINX Configuration Options 42 The FPGA on the SP601 Evaluation Board can be configured by the following methods e 3 SPI x4 Flash page 18 e 4 Linear Flash BPI page 20 e JTAG Configuration page 42 For more information refer to the Spartan 6 FPGA Configuration User Guide Ref 2 Table 1 23 Mode Pin Settings M2 0 Mode Pins M1 MO Configuration Mode 00 Master Byte Peripheral Interface BPI 01 Master SPI x1 x2 or x4 10 Not implemented on SP601 11 Not implemented on SP601 JTAG Configuration JTAG configuration is provided through onboard USB to JTAG configuration logic where a computer host accesses the SP601 JTAG chain through a Type A computer host side to Type Mini B SP601 side USB cable The JTAG chain of the board is illustrated in Figure 1 31 JTAG configuration is allowable at any time under any mode pin setting JTAG initiated configuration takes priority over the mode pin settings FMC bypass jumper J4 must be connected between pins 1 2 for JTAG access to the FPGA on the basic SP601 board as shown in Figure 1 31 When the VITA 57 1 FMC expansion connector is populated with an expansion module that has a JTAG chain then jumper J4 must be set to connect pins 2 3 i
14. FLASH A4 FLASH A5 FLASH A6 FLASH A7 FLASH A8 FLASH A9 FLASH A10 FLASH A11 FLASH A12 FLASH A13 FLASH A14 FLASH A15 FLASH A16 FLASH A17 FLASH A18 FLASH A19 FLASH A20 FLASH A21 FLASH A22 FLASH A23 FLASH A24 FLASH CE B FLASH D3 FLASH D4 FLASH D5 FLASH D6 FLASH D7 FLASH OE B FLASH WE B DDR2 LDQS P DDR2 RAS B DDR2 UDOS N DDR2 UDOQS P FMC CLKO M2C N FMC CLKO M2C P FMC CLK1 M2C N FMC CLK1 M2C P EMC LA00 CC N EMC LA00 CC P FMC LAO1 CC N FMC LAO1 CC P FMC LAO2 N FMC LAO2 P FMC LAO3 N FMC LAO3 P FMC LAO4 N FMC LAQ4 P FMC LAO5 N FMC LAO5 P FMC LAO6 N FMC LAO6 P FMC LAO7 N LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LA n Fi K6 n d TS n A K4 n Fi pi s P2 n F E3 n A K18 H KIT Fi J18 Fi J16 n 318 Fi G16 Fi H16 H15 H H14 5 H13 E F18 H F17 H KI3 K12 H E18 x E16 i G13 Fi H12 H D18 s D17 G14 s F14 H C18 Fi c17 5 F16 L17 x Ub n Fi V5 n n R3 n i T3 n H R5 n A DL18 7 M16 A10 H C10 5 V9 n d To Fi ag i
15. NET NET NET NET NET n CPU RESET DDR2 A0 DDR2 Al DDR2 A2 DDR2 A3 DDR2 A4 DDR2 A5 DDR2 A6 DDR2 A7 DDR2 A8 DDR2 A9 DDR2 A10 DDR2 A11 DDR2 A12 DDR2 BAO DDR2 BAI DDR2 BA2 DDR2 CAS RB DDR2 CKE DDR2 CLK N DDR2 CLK P DDR2 DQO DDR2_DQ1 DDR2_DQ2 DDR2 DQ3 DDR2 DQ4 DDR2 DQ5 DDR2 DQ6 DDR2 DQ7 DDR2 DQ8 DDR2 DQ9 DDR2_DQ10 DDR2_DQ11 DDR2_DQ12 DDR2_DQ13 DDR2_DQ14 DDR2_DQ15 DDR2_LDM DDR2 LDQS Nu LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC NA n J7 Ne J6 mo WEB WI F3 HA Wo H3 WH6 s D2 n Wy F4 Mo Wp3d s G6 nes F2 ns RU EI KS n2 WEM s G1 G3 Ve L2 n n L1 K2 n A Ki H2 ns H1 J3 de J1 M3 nas M1 N2 n NI n T2 n TI A U2 n UL A K3 n L3 SP601 Hardware User Guide UG518 v1 1 August 19 2009 www xilinx com 51 Appendix D SP601 Master UCF XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET DDR2 ODT DDR2 UDM DDR2 WE B FLASH AO FLASH Al FLASH A2 FLASH A3
16. xilinx com UG518 v1 1 August 19 2009 XILINX Appendix A References Appendix B Default Jumper and Switch Settings Appendix C VITA 57 1 FMC Connections Appendix D SP601 Master UCF www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX Preface About This Guide This manual accompanies the Spartan 6 FPGA SP601 Evaluation Board and contains information about the SP601 hardware and software tools Guide Contents This manual contains the following chapters e Chapter 1 SP601 Evaluation Board provides an overview of the embedded development board and details the components and features of the SP601 board e Appendix A References e Appendix B Default Jumper and Switch Settings e Appendix D SP601 Master UCF Additional Resources To search the database of silicon and software questions and answers or to create a technical support case in WebCase see the Xilinx website at http www xilinx com support Conventions This document uses the following conventions An example illustrates each convention Typographical The following typographical conventions are used in this document Convention Meaning or Use Example Messages prompts and Courier font program files that the system speed grade 100 displays Literal commands that you enter courier bold in a syntactical statement ngdbuild design name Commands that you select f
17. 47 UG518 v1 1 August 19 2009 Appendix B Default Jumper and Switch Settings g XILINX 48 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX Appendix C VITA 57 1 FMC Connections Table C 1 shows the VITA 57 1 FMC LPC connections UG518 v1 1 August 19 2009 Table C 1 VITA 57 1 FMC LPC Connections ce av Schematic Netname ul G e d Schematic Netname ui S C10 FMC LAO06 P D12 D1 FMC_PWR_GOOD_FLASH_RST_B B3 C11 FMC LA06 N C12 D8 FMC LA01 CC P D11 C14 FMC LA10 P D8 D9 FMC_LA01_CC_N C11 C15 FMC LA10 N C8 D11 FMC LA05 P B14 C18 FMC LA14 P B2 D12 FMC LAO5 N A14 C19 FMC LA14 N A2 D14 FMC_LA09_P G11 C22 FMC LA18 CC P R10 D15 FMC LA09 N F10 C23 FMC LA18 CC N T10 D17 FMC LA13 P B11 C26 FMC LA27 P R11 D18 FMC LA13 N All C27 FMC_LA27_N T11 D20 FMC LA17 CC P R8 C30 IIC SCL MAIN P11 D21 FMC LA17 CC N T8 C31 IC SDA MAIN N10 D23 FMC LA23 P N5 D24 FMC LA23 N P6 D26 FMC LA26 P U7 D27 FMC LA26 N V7 G2 FMC CLK1 M2C P T9 H2 FMC PRSNT M2C L U13 G3 FMC_CLK1_M2C_N V9 H4 FMC CLKO M2C P C10 G6 FMC LA0O0 CC P D9 H5 FMC CLKO M2C N A10 G7 FMC LAOO CC N C9 H7 FMC LA P C15 G9 FMC LA03 P C13 H8 FMC LAO2 N A15 G10 FMC LAO3 N A13 H10 FMC LAO P B16 G12 FMC LAOS P F11 H11 FMC_LA04 N A16 SP601 Hardware User Guide www xilinx com 49 Appendix C VITA 57 1 FMC Connections XILINX
18. 56 0b1010100 061010110 2 1 O OJ J16 IIC EXTERNAL ACCESS CONNECTOR UG518_13_070809 Figure 1 13 IC Bus Topology The IIC Bus on the SP601 provides access to a 2 pin header the onboard 8 Kb EEPROM and the VITA 57 1 FMC interface The user must ensure there are no IIC address conflicts with the onboard EEPROM address when attaching additional IIC devices via FMC or the IIC 2 pin header Note that FMC Mezzanine cards are designed with 2 Kb IIC EEPROMs and will not conflict with the Carrier Card SP601 8 Kb EEPROM address range This is because 2 Kb EEPROMs reside below the 8 Kb EEPROM space See the VITA 57 1 specification along with any IIC 2 Kbit EEPROM data sheet for more details 26 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 g XILINX Detailed Description 8 Kb NV Memory The SP601 hosts a 8 Kb ST Microelectronics M24C08 WDW6TP IC parameter storage memory device U7 The IIC address of U7 is 061010100 and U7 is not write protected WP pin 7 is tied to GND Table 1 12 IIC Memory Connections i SPI Memory U7 ML Schematic Netname Pn Number Not Applicable Tied to GND 1 AO Not Applicable Tied to GND 2 Al Not Applicable Pulled up 0 ohm to VCC3V3 3 A2 N10 IIC SDA MAIN 5 SDA P11 IC SCL MAIN 6 SCL Not Applicable Tied to GND 7 WP NET IIC SCL MAIN LOC P11 NET IIC SDA MAIN LOC N10 Figure 1 14 UCF Location Cons
19. AC Adapter and 5V Input Power Jack Switch The SP601 is powered from a 5V source that is connected through a 2 1mm x 5 5mm type plug center positive SP601 power can be turned on or off through a board mounted slide switch When the switch is in the on position a green LED DS15 is illuminated Onboard Power Supplies The diagram in Figure 1 30 shows the power supply architecture and maximum current handling on each supply The typical operating currents are significantly below the maximum capable The board is normally shipped with a 15W power supply which should be sufficient for most applications 40 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX Power Management The SP601 uses power solutions from LTC An estimate of the current draw on the various power supply rails is shown in Table 1 22 Monolithic Regulator 0 9V 3A max Dual Switcher LTM4616 3 3V 98A max gt 2 5V 8A max Dual Switcher LTM4616 1 2V 8A max 1 8V 8A max Linear Regulator LT1763 3 OV 500mA max Buck Boost Regulator LT1731 12VQ1A max UG518_30 _070809 Figure 1 30 Power Supply Table 1 22 Estimated Current Draw Rail V Estimated Current A FMC maux Voco D I Geh CP2103 Socket EPHY Totals Module Comments 12 1 0 1 0 LT1731 12V 3A 3 3 3 0 2 0 0 3 0 1 0 1 5 5 T UM 3 3V 8A 2 5 0 1 1 0 1 1 NR 2 5V 8A 1 8
20. AKE INIT DONE 13 User I O User LEDs User DIP switch User pushbuttons GPIO male pin header 14 FPGA PROG B Pushbutton Switch Configuration Options 3 SPI x4 Flash both onboard and off board 4 Linear Flash BPI e JTAG Configuration Power Management AC Adapter and 5V Input Power Jack Switch Onboard Power Supplies www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX Related Xilinx Documents Block Diagram Figure 1 1 shows a high level block diagram of the SP601 and its peripherals LEDs DIP Switch FMC LPC 10 100 1000 GPIO Header Expansion Connector Ethernet GMII USB JTAG Connector Spartan 6 Parallel Flash XC6SLX16 Differential Clock Clock Socket U1 SMA Clock Pushbuttons Le IIC EEPROM MODE SPI x4 or USB UART and Header DIP Switch External Config UG518 01 070809 Figure 1 1 SP601 Features and Banking Related Xilinx Documents Prior to using the SP601 Evaluation Board users should be familiar with Xilinx resources See the following locations for additional documentation on Xilinx tools and solutions e ISE www xilinx com ise e Answer Browser www xilinx com support e Intellectual Property www xilinx com ipcenter SP601 Hardware User Guide www xilinx com 11 UG518 v1 1 August 19 2009 Chapter 1 SP601 Evaluation Board XILINX Detailed Description Figure 1 2 shows a board photo with numbered features correspondi
21. C LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC E7 E11 IR EJIQ G11 d e We D8 A12 BI2 6n s D6 A11 BILN A2 Ts B2 nes F9 G9 A7 nz NE pe WEB R8 WET Os WE pg NG ns pg N7 no VA Nos TA n ws R7 ns p6 NS Me V8 de U8 ns N11 M11 V7 nc U7 nos Wes RII PATI DIL N8 nos M8 n yi2 Ys tTI 2s V6 e To V15 O5 N9 M10 U13 B3 WPS M gt IRTEN ULG Y P13 SP601 Hardware User Guide UG518 v1 1 August 19 2009 www xilinx com 53 Appendix D SP601 Master UCF XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET FPGA CMP MOSI FPGA DO DIN MISO MISO1 FPGA D1 MISO2 FPGA D2 MISO3 FPGA DONE FPGA HSWAPEN FPGA INIT B FPGA M1 FPGA PROG B FPGA SUSPEND FPGA TCK_BUF FPGA TDI BUF FPGA TDO FPGA TMS_BUF FPGA VTEMP GPIO_BUTTONO GPIO_BUTTON1 GPIO_BUTTON2 GPIO_BUTTON3 GPIO HDRO GPIO HDR1 GPIO HDR2 GPIO HDR3 GPIO HDR4 GPIO HDR5
22. C GND GND NC NC 14 NC NC LAO7 N GND NC NC LAO9 P LA10 P NC NC 15 NC NC GND LA12_P NC NC LA09 N LA10_N NC NC 16 NC NC LA11_P LA12_N NC NC GND GND NC NC 17 NC NC LA11_N GND NC NC LA13_P GND NC NC 18 NC NC GND LA16_P NC NC LA13_N LA14_P NC NC 19 NC NC LA15 P LA16_N NC NC GND LA14_N NC NC 20 NC NC LA15_N GND NC NC LA17_P_CC GND NC NC 21 NC NC GND LA20_P NC NC LA17_N_CC GND NC NC 22 NC NC LA19_P LA20_N NC NC GND LA18 P CC NC NC 23 NC NC LA19_N GND NC NC LA23_P LA18_N_CC NC NC 24 NC NC GND LA22_P NC NC LA23_N GND NC NC 25 NC NC LA21_P LA22_N NC NC GND GND NC NC 26 NC NC LA21_N GND NC NC LA26_P LA27_P NC NC 27 NC NC GND LA25_P NC NC LA26_N LA27_N NC NC 28 NC NC LA24 P LA25 N NC NC GND GND NC NC 29 NC NC LA24_N GND NC NC TCK GND NC NC 30 NC NC GND LA29_P NC NC TDI SCL NC NC 31 NC NC LA28_P LA29_N NC NC TDO SDA NC NC 32 NC NC LA28_N GND NC NC 3P3VAUX GND NC NC 33 NC NC GND LA31_P NC NC TMS GND NC NC SP601 Hardware User Guide UG518 v1 1 August 19 2009 www xilinx com 29 Chapter 1 SP601 Evaluation Board XILINX Table 1 13 LPC Pinout Cont d 30 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX Detailed Description NET FMC CLK
23. C LA22 N LOC T7 NET FMC LA22 P LOC R7 NET FMC LA23 N LOC P6 NET FMC LA23 P LOC N5 NET FMC LA24 Hi LOC V8 NET FMC LA24 P LOC U8 NET FMC LA25 N LOC N11 NET FMC LA25 P LOC M11 NET FMC LA26 N LOC V7 NET FMC LA26 P LOC U7 NET FMC LA27 N LOC T11 NET FMC LA27 P LOC R11 NET FMC LA28 N LOC V11 NET FMC LA28 P LOC U11 NET FMC LA29 N LOC N8 NET FMC LA29 P LOC M8 NET FMC LA30 N LOC V12 NET FMC LA30 P LOC T12 NET FMC LA31 N LOC V6 NET FMC LA31 P LOC T6 NET FMC LA32 N LOC V15 NET FMC LA32 P LOC U15 NET FMC LA33 Hi LOC N9 NET FMC LA33 P LOC M10 NET FMC PRSNT M2C L LOC U13 NET FMC PWR GOOD FLASH RST B LOC B3 Figure 1 18 UCF Location Constraints for VITA 57 1 FMC LPC Connections SP601 Hardware User Guide www xilinx com 31 UG518 v1 1 August 19 2009 Chapter 1 SP601 Evaluation Board 10 Status LEDs Table 1 14 defines the status LEDs XILINX Table 1 14 Status LEDs ENER Signal Name Color Label Description Designator FLASH_RST_B reen GOOD expans o connector DS2 PHY_LED_LINK10 Green 10 DS3 PHY_LED_LINK100 Green 100 DS4 Green 1000 DS5 PHY_LED_DUPLEX Green DUP DS6 PHY_LED_RX Green RX DS7 PHY_LED_TX Green TX DS8 FPGA_AWAKE Green AWAKE DS9 Illuminates to indicate the status of the DONE pin when
24. G18 G16 H16 H15 Hla H13 F18 F17 K13 K12 E18 E16 G13 H12 D18 D17 G14 F14 C18 C17 F16 R13 T14 V14 U5 V5 R3 We T3 R5 M16 LOC LOC L18 L17 B3 Figure 1 10 UCF Location Constraints for BPI Flash Connections NET FLASH AO NET FLASH A1 NET FLASH A2 NET FLASH A3 NET FLASH A4 NET FLASH A5 NET FLASH A6 NET FLASH A7 NET FLASH A8 NET FLASH A9 NET FLASH A10 NET FLASH A11 NET FLASH A12 NET FLASH A13 NET FLASH A14 NET FLASH A15 NET FLASH A16 NET FLASH A17 NET FLASH A18 NET FLASH A19 NET FLASH A20 NET FLASH A21 NET FLASH A22 NET FLASH A23 NET FLASH A24 NET NET FPGA D1 MISO2 NET FPGA D2 MISO3 NET FLASH D3 NET FLASH D4 NET FLASH D5 NET FLASH D6 NET FLASH D7 NET FLASH WE B NET FLASH OE B NET FLASH CE B NET References See the Numonyx Flash Memory specifications for more information at http www numonyx com Documents Datasheets 308551 J3D Discrete DS pdf In addition see the Xilinx Spartan 6 Configuration User Guide for more information at http www xilinx com support documentation user guides ug380 pdf 22 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX 5 10 100 1000 Tri Speed Ethernet PHY The SP601 uses the onboard Marvell Alaska PHY device 88E1111 fo
25. NX Detailed Description References See the Marvell Alaska Gigabit Ethernet Transceiver product page for more information at http www marvell com products transceivers alaska gigabit index jsp Also see the Xilinx Tri Mode Ethernet MAC User Guide at http www xilinx com support documentation ip documentation tri mode eth ma c ug138 pdf 6 USB to UART Bridge The SP601 contains a Silicon Labs CP2103GM USB to UART bridge device U4 which allows connection to a host computer with a USB cable The USB cable is supplied in this evaluation kit Type A end to host computer Type Mini B end to SP601 connector J9 Table 1 10 details the SP601 J9 pinout Xilinx UART IP is expected to be implemented in the FPGA fabric The FPGA supports the USB to UART bridge using four signal pins transmit TX receive RX Request to Send RTS and Clear to Send CTS Silicon Labs provides royalty free Virtual COM Port VCP drivers which permit the CP2103GM USB to UART bridge to appear as a COM port to host computer communications application software for example HyperTerm or TeraTerm The VCP device driver must be installed on the host PC prior to establishing communications with the SP601 Refer to the SP601 Getting Started Guide for driver installation instructions Table 1 10 USB Type B Pin Assignments and Signal Definitions USE oe Signal Name Description 1 VBUS 5V from host system not used 2 USB_DATA_N Bid
26. O M2C N LOC A10 NET FMC CLKO M2C P LOC C10 NET FMC CLK1 M2C N LOC V9 NET FMC CLK1 M2C P LOC T9 NET FMC LA00 CC N LOC C9 NET FMC LAOO CC P LOC D9 NET FMC LAO1 CC N LOC C11 NET FMC LAO1 CC P LOC D11 NET FMC LA02 N LOC A15 NET FMC_LAO2 P LOC C15 NET FMC LA03 N LOC A13 NET FMC_LAO3 P LOC C13 NET FMC LA04 N LOC A16 NET FMC LA04 P LOC B16 NET FMC_LAO5 N LOC Al4 NET FMC LA05 P LOC B14 NET FMC LAO06 Hi LOC C12 NET FMC LA06 P LOC D12 NET FMC LAO7 N LOC E8 NET FMC_LAO7_P LOC E7 NET FMC LAO8 N LOC Ell NET FMC LAO8 P LOC F11 NET FMC_LAO9 N LOC F10 NET FMC LAO9 P LOC G11 NET FMC LA10 N LOC C8 NET FMC LA10 P LOC D8 NET FMC LA11 N LOC A12 NET FMC LA11 P LOC B12 NET FMC LA12 Hi LOC C6 NET FMC LA12 P LOC D6 NET FMC_LA13_N LOC All NET FMC LA13 P LOC B11 NET FMC LA14 N LOC A2 NET FMC LA14 P LOC B2 NET FMC LA15 N LOC F9 NET FMC LA15 P LOC G9 NET FMC LA16 N LOC A7 NET FMC LA16 P LOC C7 NET FMC LA17 CC N LOC T8 NET FMC LA17 CC P LOC R8 NET FMC LA18 CC N LOC T10 NET FMC LA18 CC P LOC R10 NET FMC LA19 N LOC P7 NET FMC LA19 P LOC N6 NET FMC LA20 N LOC P8 NET FMC LA20 P LOC N7 NET FMC LA21 N LOC V4 NET FMC LA21 P LOC T4 NET FM
27. OST PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION 2009 Xilinx Inc XILINX the Xilinx logo Virtex Spartan ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners SP601 Hardware User Guide www xilinx com UG518 v1 1 August 19 2009 Revision History The following table shows the revision history for this document Date Version Revision 07 15 2009 1 0 Initial Xilinx release 08 19 2009 11 e Added Appendix C VITA 57 1 FMC Connections Updated Figure 1 18 and Figure 1 32 Updated Table 1 4 Table 1 17 and Table 1 20 Added introductory paragraph to Appendix D SP601 Master UCE Miscellaneous typographical edits and new user guide template UG518 v1 1 August 19 2009 www xilinx com SP601 Hardware User Guide SP601 Hardware User Guide www xilinx com UG518 v1 1 August 19 2009 Table of Contents Preface About This Guide Guide Contents es pens daa eared eRe Bea DESCR bee Gb Reh ek Lowes hehe 7 Additional Resources ss eese RR e 7 Conventions uses ere 7 Typographical jasc dak e ae fk ter b Eb Een eb ed hides e dare ve 7 Online Document 8 Chapter 1 SP601 Evaluation Board aula EE 9 Additional Information 9 HE 10 Block Diagram eg eer dee p ep er dE me ud eG ee deese tos 11 Related Xilinx Documents 11 Detaile
28. PIO LED 2 GPIO LED 1 GPIO LED 0 N N N m m m m owo W W oW o w o NY o We o PE EP A up Wa Wal m Wa Wal E d d 1 rot oe upon 1j R94 27 4 27 4 27 4 27 4 1 1 1 1 S 1 16W E 1 16W 1 16W e 1 16W UG518 23 070809 Figure 1 23 User LEDs Table 1 17 User LEDs Reference Designator Signal Name Color Label FPGA Pin DS11 GPIO LED 0 Green E13 DS12 GPIO_LED_1 Green C14 SP601 Hardware User Guide www xilinx com 35 UG518 v1 1 August 19 2009 Chapter 1 SP601 Evaluation Board XILINX Table 1 17 User LEDs Cont d Fete ce Signal Name Color Label FPGA Pin Designator DS13 GPIO LED 2 Green C4 DS14 GPIO LED 3 Green A4 User DIP switch The SP601 includes an active high four pole DIP switch as described in Figure 1 24 and Table 1 18 VCC2V5 GPIO SWITCH O GPIO SWITCH 1 GPIO SWITCH 2 GPIO SWITCH 3 UG518 24 070809 Figure 1 24 User DIP Switch Table 1 18 User DIP Switch Connections FPGA U1 Pin Schematic Netname SW8 Pin Number D14 GPIO_SWITCH_0 1 E12 GPIO_SWITCH_1 2 F12 GPIO_SWITCH_2 3 V13 GPIO SWITCH 3 4 36 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 g XILINX Detailed Description User Pushbutton Switches The SP601 provides five active high pushbutton switches SW6 SW4 SW5 SW7 and SW9 The five pushbuttons all have the same topology as the sample shown in Figure 1 25 Four push
29. R15 Figure 1 8 UCF Location Constraints for BPI Flash Connections References See the Winbond Serial Flash specifications for more information at http www winbond usa com hq enu ProductAndSales ProductLines FlashMemory SerialFlash W25X64 htm See the XPS Serial Peripheral Interface specification for more information at http www xilinx com support documentation ip_documentation xps_spi pdf Flash BPI An 8 bit 16 MB Numonyx linear flash memory TE 28F128J3D 75 J3D type is used to provide non volatile bitstream code and data storage The J3D devices operate at 3 0V the Spartan 6 FPGA I Os are 3 3V tolerant and provide electrically compatible logic levels to directly access the linear flash BPI through a 2 5V bank For details on configuring the FPGA see Configuration Options U1 U10 FPGA ADDR DATA CTRL NUMONYX TYPE J3vD BPI FLASH T28F128J3D 75 INTERFACE UG518 09 070809 Figure 1 9 Linear Flash BPI Interface Table 1 7 BPI Memory Connections BPI Memory U10 FPGA U1 Pin Schematic Netname Pin Number Pin K18 FLASH_AO 32 AO K17 FLASH A1 28 A1 J18 FLASH A2 27 A2 J16 FLASH A3 26 A3 G18 FLASH A4 25 A4 G16 FLASH_A5 24 A5 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 g XILINX Detailed Description Table 1 7 BPI Memory Connections Cont d
30. S B FPGA MOSI CSI B MISOO FPGA DO DIN MISO MISO1 TMS TDI TDO Silkscreen TCK GND 3V3 O O O O O O O O O HDR_1X9 UG518_06_070809 Figure 1 6 J12 SPI Flash Programming Header 18 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX SPI X4 DIN DOUT CCLK FPGA SPI INTERFACE FLASH MEMORY Detailed Description J12 SPIX4 CS B SPI_CS_B WINBOND W25Q64VSFIG 2 1 ON SPI X4 U17 SPI PROGRAM OFF SPI EXT J12 O O uts HEADER SPI SELECT JUMPER UG518_07_070809 Figure 1 7 SPI Flash Interface Topology Table 1 6 SPI x4 Memory Connections FPGA U1 i SPI MEM U17 SPI HDR J12 Pin Schematic Netname i Pin Pin Name Pin Pin Name V2 FPGA_PROG_B 1 V14 FPGA_D2_MISO3 1 IO3 HOLD B 2 T14 FPGA_D1_MISO2_R 9 IO2 WP B 3 V3 SPI CS B 4 TMS T13 FPGA MOSI CSI B MISOO 15 DIN 5 TDI R13 FPGA DO DIN MISO MISO1 8 IO1 DOUT 6 TDO R15 FPGA_CCLK 16 CLK 7 TCK 8 GND 9 VCC3V3 J15 2 SPIX4 CS B 7 CS B SP601 Hardware User Guide www xilinx com 19 UG518 v1 1 August 19 2009 20 4 Linear Chapter 1 SP601 Evaluation Board XILINX Figure 1 8 provides the UCF constraints for the SPI serial flash PROM NET FPGA D2 MISO3 LOC V14 NET SPI CS B LOC V3 NET FPGA DO DIN MISO MISO1 LOC R13 NET FPGA Di MISO2 LOC T14 NET FPGA MOSI CSI B MISOO LOC T13 NET FPGA CCLK LOC
31. SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX amp XILINX Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOSS OF DATA OR L
32. ame J7 DDR2 A0 M8 AO J6 DDR2 A1 M3 A1 H5 DDR2 A2 M7 A2 L7 DDR2 A3 N2 A3 F3 DDR2 A4 N8 A4 H4 DDR2_A5 N3 A5 H3 DDR2 A6 N7 A6 H6 DDR2 A7 P2 A7 D2 DDR2_A8 P8 A8 D1 DDR2_A9 P3 A9 F4 DDR2 A10 M2 A10 D3 DDR2 A11 P7 A11 G6 DDR2_A12 R2 A12 L2 DDR2_DQ0 G8 DQO L1 DDR2_DQ1 G2 DQ1 K2 DDR2_DQ2 H7 DQ2 K1 DDR2_DQ3 H3 DQ3 H2 DDR2_DQ4 H1 DQ4 H1 DDR2_DQ5 H9 DQ5 J3 DDR2_DQ6 F1 DQ6 n DDR2 DQ7 F9 DQ7 M3 DDR2 DOS C8 DOS MI DDR2 DQ9 C2 DQ9 N2 DDR2_DQ10 D7 DQ10 N1 DDR2_DQ11 D3 DQ11 T2 DDR2_DQ12 D1 DQ12 T1 DDR2_DQ13 D9 DQ13 U2 DDR2_DQ14 B1 DQ14 U1 DDR2_DQ15 B9 DQ15 SP601 Hardware User Guide UG518 v1 1 August 19 2009 www xilinx com 15 Chapter 1 SP601 Evaluation Board 16 Table 1 5 DDR2 Component Memory Connections Cont d XILINX Memory U2 FPGA U1 Schematic Netname Pin Number Name F2 DDR2 BAO L2 BAO F1 DDR2 BA1 L3 BA1 E1 DDR2_BA2 L1 BA2 E3 DDR2_WE_B K3 WE L5 DDR2_RAS_B K7 RAS K5 DDR2_CAS_B L7 CAS K6 DDR2_ODT K9 ODT G3 DDR2_CLK_P J8 CK G1 DDR2_CLK_N K8 CK H7 DDR2_CKE K2 CKE L4 DDR2_LDQS_P F7 LDQS L3 DDR2_LDQS_N E8 LDQS P2 DDR2_UDQS_P B7 UDOS PI DDR2 UDOS N A8 UDQS K3 DDR2_LDM F3 LDM K4 DDR2_UDM B3 UDM Figure 1 3 provides the user constraints file UCF for the DDR2 SDRAM address pins including the I O pin assignment and the I O standard used NET NET NET NET NET NET NET NET NET NET NET NET NET n n D D
33. buttons are assigned as GPIO and the fifth is assigned as a CPU_RESET Figure 1 25 and Table 1 19 describe the pushbutton switches VCC1V8 Pushbutton CPU_RESET UG518 25 070809 Figure 1 25 User Pushbutton Switch Typical Table 1 19 Pushbutton Switch Connections FPGA U1 Pin Schematic Netname Switch Pin P4 GPIO BUTTON 0 SW6 2 F6 GPIO BUTTON 1 SW4 2 E4 GPIO_BUTTON_2 SW5 2 F5 GPIO BUTTON 3 SW7 2 N4 CPU_RESET SW9 2 SP601 Hardware User Guide www xilinx com 37 UG518 v1 1 August 19 2009 Chapter 1 GPIO HDRO GPIO HDR1 GPIO HDR2 GPIO HDR3 38 c M L L ML 9 e LY SP601 Evaluation Board XILINX GPIO Male Pin Header The SP601 provides a 2X6 GPIO male pin header supporting 3 3V power GND and eight I Os Figure 1 26 and Table 1 20 describe the J13 GPIO Male Pin Header JE NIE S 8 FR T TER o s ma GPIOHDR4 e a N EADS e 9 PIO HDR EFE CN di z 38 2 1 2 DS ex NE sog NOT eo GPIOHDR6 Sa E See a b o 7 lolo 8 o GPIO HDR7 9 ole 10 ep 11 oo 12 J13 VCC3V3 UG518 24 070809 Figure 1 26 GPIO Male Pin Header Topology Table 1 20 GPIO Header Pins FPGA U1 Pin Signal Name J13 Pin N17 GPIO_HDRO 1 M18 GPIO_HDR1 3 A3 GPIO HDR2 5 L15 GPIO HDR3 7 F15 GPIO_HDR4 2 B4 GPIO_HDR5 4 F13 GPIO_HDR6 6 P12 GPIO HDR7 8 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX Detailed Descr
34. ctions available on the FMC LPC connector LA 00 33 along with all available FMC M2C clock pairs CLKO M2C P N and CLK1 M2C P N The SP601 does not support the FMC DP Bus connections since the SP601 does not support any Gigabit Transceivers on the FMC DP Bus Therefore DPO COM P N DPO M2C P N and GBTCLKO M2C P N are not supported by the SP601 FMC interface For more details about FMC see the VITA57 1 specification available at http www vita com fmc html 28 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX Table 1 13 LPC Pinout Detailed Description K J H G F E D C B A 1 NC NC VREF A M2C GND NC NC PG COM GND NC NC 2 NC NC PRSNT_M2C_L CLKI M2C P NC NC GND DPO C2M P NC NC 3 NC NC GND CLKI M2C N NC NC GND DPO C2M N NC NC 4 NC NC CLKO M2C P GND NC NC GBICLKO M2C P GND NC NC 5 NC NC CLKO_M2C_N GND NC NC GBTCLKO_M2C_N GND NC NC 6 NC NC GND LAO0 P CC NC NC GND DPO M2C P NC NC 7 NC NC LAO2 P LAO0 N CC NC NC GND DPOM2CN NC NC 8 NC NC LAO2 N GND NC NC LAO1 P CC GND NC NC 9 NC NC GND LAO3 P NC NC LAO1 N CC GND NC NC 10 NC NC LA04_P LAO3 N NC NC GND LA06 P NC NC 11 NC NC LA04_N GND NC NC LA05_P LA06 N NC NC 12 NC NC GND LAOS P NC NC LA05 N GND NC NC 13 NC NC LAV P LAOS N NC N
35. d Description i aad ete OI ore EE op eee eed 12 1 Spartan 6 XC6SLX16 2CSG324 FPGA e 13 Ee EE 13 I O Voltage Ralls ber xb Erb moe deed EE RE pera mg s i pua 13 2 128 MB DDR2 Component Memor 14 9 SPI Xx4El sb 5d eve be UR CREE RV Vu eX ee ce RYR S 18 4 Linear Flash BPI an cc ie ce e rk age p Ras 20 5 10 100 1000 Tri Speed Ethernet PHY 23 6 USB to UART Bridge ocen cere be eta pa ve aie tea bias eed aa 25 Z IC BUS s hbro le be dies te de te Id Deve vXgu D Des PL PES 26 9 Kb NV Memory as cera etae bs id e ee t PEE Ea te eee 27 8 Clock Generation eben pen ti ETG Rr se CE E aac ped RET nan te weeds 27 Oscillator Differential 12 occa sa e RR e hae e rer b ee ma we 27 Oscillator Socket Single Ended 2 5V or 3 3V ciis eee 28 SMA Connectors Differential 0 0 2 eee cee eee ences 28 9 VITA 57 1 FMC LPC Connector 28 10 Status LEDS EE 32 11 FPGA Awake LED and Suspend Jumper 33 12 FPGA INIT and DONE LEDs n 34 13 User O acanstevrse ce eee e va ERE a e A er DeL ran kte EN rr EE iE erus 35 14 FPGA PROG B Pushbutton Switch 40 Power Management 4s her se d ade YR rorat ed EE RATE KERA EREGI 40 AC Adapter and 5V Input Power Jack SWitch eeeeeeeeeeeeeee 40 Onboard Power upper e ayi aa ENEE ar eee ee ad e d 40 Configuration Options ies iar ko odere I Rd oot eoe pte Me e Rie 42 JTAG Configuralion ceo be Sod bet ee t ebore eee ded Pau a recede am 42 SP601 Hardware User Guide www
36. iption NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET GPIO LED 0 GPIO LED 1 GPIO LED 2 GPIO LED 3 GPIO SWITCH 0 GPIO SWITCH 1 GPIO SWITCH 2 GPIO SWITCH 3 GPIO BUTTONO GPIO BUTTON1 GPIO BUTTON2 GPIO BUTTON3 CPU RESET GPIO HDRO GPIO HDR1 GPIO HDR2 GPIO HDR3 GPIO HDR4 GPIO HDR5 GPIO HDR6 GPIO HDR7 LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC E13 Fi C14 Fi C4 n i AA n H D14 E E12 FI2 gt V13 P4 n F6 n i EA n 2 F5 n i NA n 3 N17 H M18 A3 n n T15 5 F15 Fi B4 n ri E13 H P12 Fi Figure 1 27 UCF Location Constraints for User and General Purpose I O SP601 Hardware User Guide UG518 v1 1 August 19 2009 www xilinx com 39 Chapter 1 SP601 Evaluation Board XILINX 14 FPGA PROG B Pushbutton Switch The SP601 provides one dedicated active low FPGA PROG B pushbutton switch as shown in Figure 1 28 VCC2V5 Pushbutton FPGA PROG B UG518 28 070809 Figure 1 28 FPGA PROG B Pushbutton Switch Topology Table 1 21 FPGA PROG B Pushbutton Switch Connections FPGA U1 Pin Schematic Netname SW3 Pin V2 FPGA PROG B 1 NET FPGA PROG B LOC V2 Figure 1 29 UCF Location Constraints for BPI Flash Connections Power Management
37. irectional differential serial data N side 3 USB_DATA_P Bidirectional differential serial data P side 4 GROUND Signal ground Table 1 11 CP2103GM Connections Biers Ud Schematic Netname U4 CP2103GM U10 USB 1 CTS 22 T5 USB 1 RTS 23 L12 USB 1 RX 24 K14 USB 1 TX 25 NET USB 1 CTS LOC U10 NET USB 1 RTS LOC T5 NET USB 1 RX LOC L12 NET USB 1 TX LOC K14 Figure 1 12 UCF Location Constraints for CP2103GM Connections SP601 Hardware User Guide www xilinx com 25 UG518 v1 1 August 19 2009 Chapter 1 SP601 Evaluation Board XILINX References Technical information on the Silicon Labs CP2103GM and the VCP drivers can be found on their website at https www silabs com Pages default aspx In addition see some of the Xilinx UART IP specifications at e http www xilinx com support documentation ip_documentation opb_uartlite pdf e http www xilinx com support documentation ip_documentation xps_uartlite pdf e http www xilinx com support documentation ip_documentation xps_uart16550 pdf 7 IC Bus The SP601 IIC bus hosts four items e FPGA UIIIC interface e 2 pin IIC external access header e 8 Kb NV Memory e VITA 57 1 FMC Connector J1 The SP601 IIC bus topology is shown in Figure 1 13 VITA 57 1 FMC LPC FMC LPC v 0 O O JI C30 C31 ST MICRO FPGA IIC NC_SDA_MAIN M24 C08 WDW6TP INTERFACE IC SCL MAIN Address range 54
38. n Board 44 www xilinx com XILINX SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX Appendix A References This section provides references to documentation supporting Spartan 6 FPGAs tools and IP For additional information see www xilinx com support documentation index htm Documents supporting the SP601 Evaluation Board 1 UG138 LogiCORE IP Tri Mode Ethernet MAC v4 2 User Guide 2 UGS80 Spartan 6 FPGA Configuration User Guide 3 UGS381 Spartan 6 FPGA SelectIO Resources User Guide 4 UG388 Spartan 6 FPGA Memory Controller User Guide 5 DS614 Clock Generator v3 01a Data Sheet 6 DS643 Multi Port Memory Controller MPMC v5 02a Data Sheet SP601 Hardware User Guide www xilinx com 45 UG518 v1 1 August 19 2009 Appendix A References g XILINX 46 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX Appendix B Default Jumper and Switch Settings Table B 1 shows the default jumper and switch settings for the SP601 Table B 1 Default Jumper and Switch Settings REFDES Type Function Default SW1 SLIDE POWER ON OFF OFF SW2 DIP 2 POLE MODE 1 MO ON 1 2 M1 OFF 0 SW8 DIP 4 POLE GPIO 1 OFF 2 OFF 3 OFF 4 OFF J4 HDR_1X3 JTAG BYPASS JUMP 1 2 EXCLUDE FMC JA4 HDR 1X2 SUSPEND OPEN 0 AWAKE J15 HDR 1X2 SPI SELECT ON U17 SPI MEM SELECTED SP601 Hardware User Guide www xilinx com
39. n order to include the FMC expansion module s JTAG chain in the main SP601 JTAG chain J10 FPGA FMC LPC Expansion m TDI TDO gt TDI SS m S a J1 PO TDO D Default jumper setting excludes FMC To include FMC jumper pins 2 3 UG518_31_070809 Figure 1 31 JTAG Chain www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX Configuration Options J4 FPGA_TDO Bypass FMC LPC J1 Jumper 1 2 2 JTAG_TDO Include FMC LPC J1 Jumper 2 3 m FMC TDO H 1x3 UG518 32 081909 Figure 1 32 VITA 57 1 FMC JTAG Bypass Jumper The JTAG chain can be used to program the FPGA and access the FPGA for hardware and software debug The JTAG connector USB Mini B J10 allows a host computer to download bitstreams to the FPGA using the iMPACT software tool and also allows debug tools such as the ChipScope Pro Analyzer tool or a software debugger to access the FPGA The iMPACT software tool can also program the SPI x4 flash or the BPI flash via the USB J10 connection iMPACT can download a temporary design to the FPGA through the JTAG This provides a connection within the FPGA from the FPGA s JTAG port to the FPGA s SPI or BPI interface Through the connection made by the temporary design in the FPGA iMPACT can indirectly program the SPI flash or BPI flash from the JTAG USB J10 connector SP601 Hardware User Guide www xilinx com 43 UG518 v1 1 August 19 2009 Chapter 1 SP601 Evaluatio
40. nee DONE Sen DONE the FPGA is successfully configured DS10 Illuminates after power up to indicate that the FPGA has FPGA_INIT Red INIT successfully powered up and completed its internal power on process DS15 VCC5 Green Illuminates when SV supply is applied DS16 LED GRN Green s LED RED Red STATUS USB to JTAG logic DS17 LIC PWR GOOD Green Illuminates to indicate that the board power is good 32 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX Detailed Description 11 FPGA Awake LED and Suspend Jumper The suspend mode jumper permits the FPGA to enter an inactive suspend mode The FPGA Awake LED DSS8 will go out when the FPGA enters this mode FPGA AWAKE VCC2V5 FPGA SUSPEND IINS NHO G31 J14 Suspend Jumper OFF AWAKE default ON SUSPEND UG518 19 070809 Figure 1 19 FPGA Awake LED and Suspend Jumper Table 1 15 FPGA Awake Suspend Mode Jumper Connections FPGA U1 Pin Schematic Netname Suspend Mode I O P15 FPGA_AWAKE Awake LED DS8 2 R16 FPGA_SUSPEND Suspend J14 2 NET FPGA AWAKE LOC P15 NET FPGA SUSPEND LOC R16 Figure 1 20 UCF Location Constraints for FPGA Awake Suspend Mode Jumper See the Spartan 6 FPGA Configuration Guide for more information at http www xilinx com support documentation user_guides ug380 pdf SP601 Hardware User Guide www xilinx com 33 UG518 v1 1 August 19 2009
41. ng to Table 1 1 and the section headings in this document DUT LELEET EI Figure 1 2 SP601 Board Photo The numbered features in Figure 1 2 correlate to the features and notes listed in Table 1 1 Table 1 1 SP601 Features Number Feature Notes Mou 1 Spartan 6 FPGA XC65LX16 2CSG324 2 DDR2 Component Hard memory controller w OCT 5 3 SPI x4 Flash and Headers SPI select and External Headers 8 4 Linear Flash BPI StrataFlash 8 bit J3 device 3 pins 8 shared w SPI x4 5 10 100 1000 Ethernet PHY GMII Marvell Alaska PHY 7 6 RS232 UART USB Bridge Uses CP2103 Serial to USB connection 10 7 IC Goes to Header and VITA 57 1 FMC 10 8 Clock socket SMA Differential Single Ended Differential 9 12 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX Detailed Description Table 1 1 SP601 Features Cont d Number Feature Notes Mou 9 VITA 57 1 FMC LPC LVDS signals clocks PRSNT 6 connector 10 LEDs Ethernet PHY Status 7 11 LED Header FPGA Awake LED Suspend Header 8 12 LEDs FPGA INIT DONE 9 LED User I O active High 9 DIP Switch User I O active High 9 13 Pushbutton User I O CPU_RESET active High 9 12 pin 8 I O Header 6 pins x 2 male header with 8 I Os 10 active High 14 Pushbutton FPGA_PROG_B 9 15 USB JTAG Cypress USB to JTAG download cable 14 15 logic 16 Onboard Power Power Management 11 12 13
42. pg fi c11 H D11 Fi A15 H C15 Fi A123 5 C13 H A16 B16 7 A14 5 B14 gt C12 Fi D12 H ES n a 52 www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET NET FMC LAO7 P FMC LAO8 N FMC LAO8 P FMC LAO9 N FMC LAO9 P FMC LA10 N FMC LA10 P FMC LA11 N FMC LA11 P FMC LA12 N FMC LA12 P FMC LA13 N FMC LA13 P FMC LA14 N FMC LAl4 P FMC LA15 N FMC LA15 P FMC LA16 N FMC LA16 P FMC LA17 CC N FMC LA17 CC P FMC LA18 CC N FMC LA18 CC P FMC LA19 N FMC LA19 P FMC LA20 N FMC LA20 P FMC LA21 N FMC LA21 P FMC LA22 N FMC LA22 P FMC LA23 N FMC LA23 P FMC LA24 N FMC LA24 p FMC LA25 N FMC LA25 P FMC LA26 N FMC LA26 P FMC LA27 N FMC LA27 P FMC LA28 N FMC LA28 P FMC LA29 N FMC LA29 P FMC LA30 N FMC LA30 P FMC LA31 N FMC LA31 P FMC LA32 N FMC LA32 P FMC LA33 N FMC LA33 P FMC PRSNT M2C Lu FMC PWR GOOD FLASH RST FPGA AWAKE FPGA CCLK FPGA CMP CLK FPGA CMP CS B B LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LO
43. r Ethernet communications at 10 100 or 1000 Mb s The board supports a GMII MII interface from the FPGA to the PHY The PHY connection to a user provided Ethernet cable is through a Halo HFJ11 1G01E RJ 45 connector with built in magnetics Detailed Description On power up or on reset the PHY is configured to operate in GMII mode with PHY address 0b00111 using the settings shown in Table 1 8 These settings can be overwritten via software commands passed over the MDIO interface Table 1 8 PHY Configuration Pins Pin Connection on Bit 2 Bit 1 Bit 0 Board Definition and Value Definition and Value Definition and Value CFGO Vec 2 5V PHYADR 2 1 PHYADRI 1 1 PHYADR 0 1 CFG1 Ground ENA_PAUSE 0 PHYADR 4 0 PHYADR 3 0 CFG2 Vec 2 5V ANEG 3 1 ANEG 2 1 ANEG 1 1 CFG3 Vec 2 5V ANEG 0 1 ENA XC 1 DIS 125 1 CFG4 Vec 2 5V HWCFG MD 2 1 HWCFG MD 1 21 HWCFG MD 0 1 CFG5 Vec 2 5V DIS FC 1 DIS SLEEP 1 HWCFG_MDJ3 1 CFG6 PHY_LED_RX SEL BDT 0 INT_POL 1 75 50 OHM 0 Table 1 9 PHY Connections js ii Schematic Netname U3 M88E111 P16 PHY MDIO 33 N14 PHY MDC 35 J13 PHY INT 32 L13 PHY RESET 36 M13 PHY CRS 115 L14 PHY COL 114 L16 PHY RXCLK 7 P17 PHY_RXER 8 N18 PHY_RXCTL_RXDV 4 M14 PHY RXDO 3 U18 PHY RXD1 128 U17 PHY RXD2 126 T18 PHY RXD3 125 T17 PHY RXD4 124 N16 PHY RXD5 123 N15 PHY RXD6 121
44. roller is used for data transfer across the DDR2 memory interface s 16 bit data path using SSTL18 signaling The maximum data rate supported is 800 Mb s with a memory clock running at 400 MHz Signal integrity is maintained through DDR2 resistor terminations and memory on die terminations ODT as shown in Table 1 3 and Table 1 4 Table 1 3 Termination Resistor Requirements Signal Name Board Termination On Die Termination DDR2 A 14 0 49 9 ohms to Vrr DDR2 BA 2 0 49 9 ohms to VTT DDR2_CK PN DDR2_RAS_N 49 9 ohms to VTT DDR2 CAS N 49 9 ohms to Vrr DDR2 WE N 49 9 ohms to VTT DDR2 CS N 100 ohms to GND DDR2 CKE 4 7K ohms to GND DDR2 ODT 4 7K ohms to GND DDR2_DQ 15 0 ODT Semer om DDR2 UDM DDR2 LDM ODT 100 ohm differential at memory component Notes 1 Nominal value of Vyr for DDR2 interface is 0 9V Table 1 4 FPGA On Chip OCT Termination External Resistor Requirements FPGA U1 Pin FPGA Pin Number Board Connection for OCT ZIO L6 No Connect RZQ C2 100 ohms to GROUND www xilinx com SP601 Hardware User Guide UG518 v1 1 August 19 2009 XILINX Table 1 5 shows the connections and pin numbers for the DDR2 Component Memory Table 1 5 DDR2 Component Memory Connections Detailed Description Memory U2 FPGA U1 Schematic Netname Pin Number N
45. rom File Open Helvetica bold a menu Keyboard shortcuts Ctrl C SP601 Hardware User Guide www xilinx com 7 UG518 v1 1 August 19 2009 Preface About This Guide XILINX Convention Meaning or Use Example Variables in a syntax statement for which you must supply ngdbuild design_name values Italic font fi References to other manuals Ges ins id Gilde ton mine information If a wire is drawn so that it Emphasis in text overlaps the pin of a symbol the two nets are not connected Items that are not supported o Dark Shading l uppor This feature is not supported reserved Square brackets An optional entry or parameter However in bus specifications such as bus 7 0 they are required ngdbuild option_name design name Braces A list of items from which you must choose one or more lowpwr on off Vertical bar Separates items in a list of choices lowpwr on off Angle brackets lt gt User defined variable or in code samples directory name Vertical ellipsis Repetitive material that has been omitted IOB 1 IOB 2 Name QOUT Name CLKIN Horizontal ellipsis Repetitive material that has been omitted allow block block name loci loc2 locn Notations The prefix Ox or the suffix h indicate hexadecimal notation A read of address 0x00112975 returned 45524943h
46. traints for IIC Connections References See the ST Micro M24CO8 WDW6TP data sheet for more information at http www st com stonline products literature ds 5067 m24c08 w pdf In addition see the Xilinx XPS IIC Bus Interface specification at http www xilinx com support documentation ip documentation xps iic pdf Also see 9 VITA 57 1 FMC LPC Connector page 28 8 Clock Generation There are three clock sources available on the SP601 Oscillator Differential The SP601 has one 2 5V LVDS differential 200 MHz oscillator U5 soldered onto the board and wired to an FPGA global clock input e Crystal oscillator Epson EG2121CA e PPM frequency jitter 50 ppm NET SYSCLK N LOC K16 NET SYSCLK P LOC K15 Figure 1 15 UCF Location Constraints for Oscillator Connections References For more details see the Epson data sheet at http www epsontoyocom co jp english product OSC set04 eg2121ca index html SP601 Hardware User Guide www xilinx com 27 UG518 v1 1 August 19 2009 Chapter 1 SP601 Evaluation Board XILINX Oscillator Socket Single Ended 2 5V or 3 3V One populated single ended clock socket X2 is provided for user applications The option of 3 3V or 2 5V power may be selected via a 0 ohm resistor selection The SP601 board is shipped with a 27MHz 2 5V oscillator installed NET USER CLOCK LOC V10 Figure 1 16 UCF Location Constraints for Oscillator Socket Connections
47. uide in PDF format e Example design files for demonstration of Spartan 6 FPGA features and technology e Demonstration hardware and software configuration files for the SP601 linear and SPI memory devices e Reference Design Files e Schematics in PDF format and DxDesigner schematic format e Bill of materials BOM e Printed circuit board PCB layout in Allegro PCB format e Gerber files for the PCB Many free or shareware Gerber file viewers are available on the internet for viewing and printing these files e Additional documentation errata frequently asked questions and the latest news For information about the Spartan 6 family of FPGA devices including product highlights data sheets user guides and application notes see the Spartan 6 FPGA website at http www xilinx com support documentation spartan 6 htm SP601 Hardware User Guide www xilinx com 9 UG518 v1 1 August 19 2009 Chapter 1 SP601 Evaluation Board g XILINX Features The SP601 board provides the following features 10 1 Spartan 6 XC6SLX16 2CSG324 FPGA 128 MB DDR2 Component Memory SPI x4 Flash Linear Flash BPI 10 100 1000 Tri Speed Ethernet PHY IIC Bus 8Kb NV memory External access 2 pin header VITA 57 1 FMC LPC connector 8 Clock Generation N O A C N Oscillator Differential Oscillator Socket Single Ended 2 5V or 3 3V SMA Connectors Differential 9 VITA 57 1 FMC LPC Connector 10 Status LEDs FPGA AW
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