Vodafone SS 08 User's Manual
Contents
1. TECHNISCHE Memory Map eee s 64KB Internal On chip Periph 0180 0000 8000 0000 4 byte Port i i DSK status 2 Daughter Can Available via 256MB Extern aughter Card 000 0000 256 Extern Connector 000 0000 Slide 28 TECHNISCHE UNIVERSITAT Operands DRESDEN vodafone chair Operands can be a 5 bit constants or 16 bit in some special instruct 32 bit Registers a 40 bit Registers a 64 bit Registers A 40 bit or a 64 bit register can be obtained by concatenating two registers a The registers must be from the same side a The first register must be even and the second odd e g A1 A0 B9 B8 or 15 14 a he registers must be consecutive TU Dresden 4 29 2008 Slide 29 TECHNISCHE iti UNIVERSITAT Conditional execution DRESDEN vodafone chair All instructions in each Functional Unit of both Data paths can be executed conditionally Only the Registers A1 A2 BO B1 B2 can hold the condition Conditional Execution uses the Syntax condition Instruction e g BO ADD L1 1 2 3 addifBO BO ADD L1 1 2 3 addifBO 0 TU Dresden 4 29 2008 Slide 30 Branches vodafone chair Branches are required to realize loops2. D D H x 8 d E EST ELTE UND S Ae a D j TUR T TI A SEL Tei ined eL 3 e Ji An Wi OAO C ph ol universirar Introduction DRESDEN vodafone chair Hardware Why to use digital signal processing General introduction to DSPs The TMS320C6711 DSP Architecture Overview Peripherals DSK6711 evaluation board Software Code Composer Studio DSP BIOS Multi channel Buffered Serial Port McBSP TU Dresden 4 29 2008 Slide 2 TECHNISCHE 4 UNIVERSITAT DRESDEN vodafone chair Hardware TU Dresden 4 29 2008 Slide 3 Digital Signal Processing DSP universirar DRESDEN vodafone chair Wireless Cellular Voice band audio RF codecs Voltage regulation DI AD Speech synthesizer Mixed signal processor TU Dresden 4 29 2008 Slide 4 4 TECHNISCHE system Considerations UNIVERSITAT DRESDEN vodafone chair Performance Interfacing Power Size Ease of Use Integration Programming Cost e Memory Interfacing Device cost Peripherals Debugging System cost Development cost Time to market TU Dresden 4 29 2008 Slide 5 2 TECHNISCHE Why Go Digital UNIVERSITAT vodafone chair Digital signal processing techniques are now powertul that sometimes it is extremel
3. x h k k 0 N 1 Discrete Fourier Transform X k xa expI jQz N nk n 0 Discrete Cosine Transform cu f end x 0 TU Dresden 4 29 2008 Slide 11 TECHNISCHE Why do we need DSP processors UNIVERSITAT DRESDEN vodafone chair Use a DSP processor when the following are required Cost saving Smaller size Low power consumption a Processing of many high frequency signals in real time Use a GPP processor when the following are required Large memory Advanced operating systems TU Dresden 4 29 2008 Slide 12 T TECHNISCHE Hardware vs Microcode multiplication 7 DRESDEN vodafone chair DSP processors are optimized to perform multiplication and addition operations Multiplication and addition are done in hardware and in one cycle Example 4 bit multiply unsigned Hardware Microcode 1011 1011 x 1110 x 1110 10011010 0000 1011 1011 a 10011010 TU Dresden 4 29 2008 Slide 13 General Purpose DSP vs DSP in ASIC DOE DRESDEN vodafone chair Application Specific Integrated Circuits ASICs are semiconductors designed for dedicated functions advantages and disadvantages of using ASICs are listed below Advantages Disadvantages High throughput High investment cost Lower silicon area Less flexibility Lower power consumption Long time from desig
4. P ou E H dam Z md PETTITT rit ete CO Be Ma f wf en 4 ur TU Dresden 4 29 2008 Slide 50 TECHNISCHE 4 UNIVERSITAT DRESDEN Daughter Card I F EMIF Connector 1 8V Power Supply 16M SDRAM 128K FLASH m cc n Parallel ps _ Port I F C6711 ran D E DSP Power 8 Jack LJ AH A At A 445 H A CA D Card D i os A Periph Con Power 277 C CMM 17 Te User DIP switches Reset Three User LEDs 3 3V Power Supply Emulati ti 16 bit codec A D amp D A JTAG Header JTAG Header Line Level Input microphone Line Level Output speakers TECHNISCHE Software 4 gt DSK Communications CL universirar DRESDEN vodafone chair CCS uses parallel port to control DSP via JTAG port You can use full Tl eXtended Dev System XDS 14 header connector Communicate from Windows program C VB via parallel port using Win32 DLL Use HPI via Win32 DLL JTAG Emulation Port TU Dresden 4 29 2008 Slide 52 TECHNISCHE wy UNIVERSITAT DRESDEN Linear Assembl ues Optimizer Code Compiler d Assembler Ex
5. Use shift right 00 Use shift Sine Cosine Log Use look up tables convert a fractional number to hex Num x 27 Then convert to hex e g convert 0 5 to hex 0 5 x 215 16384 16384 0x4000 TU Dresden 4 29 2008 Slide 38 4 um TECHNISCHE Numerical Issues 32 bit Multiplication universirar DRESDEN vodafone chair 115 possible to perform 32 bit multiplication using 16 bit multipliers Example a x b with 32 bit values a b 32 bits a b lt lt 16 b lt lt 16 5 bj lt lt 32 b lt lt 16 b lt lt 16 b TU Dresden 4 29 2008 Slide 39 TECHNISCHE 4 UNIVERSITAT DRESDEN vodafone chair selected 6711 Peripherals TU Dresden 4 29 2008 Slide 40 C6000 Peripherals KEE DRESDEN internal LE SLV 0V Le cLg 0g Timer Count TU Dresden 4 29 2008 Slide 41 TECHNISCHE NIVERSITAT The McBSP DRESDEN Q vodafone chair Multichannel Buffered Serial Port Up to 100 Mb sec performance 2 or 3 full duplex synchronous serial ports Enables direct interfacing to industry standard Codecs Analog interface Chips and other serially connected devices Supports a wide range of data sizes including 8 12 16 20 24 and 32 bits gt Bit Word channel Frame Phase n our lab the McBSP is used to connect
6. advanced very long instruction words VLIW Program Memory Width is 256 Bit Up to 8 32 Bit instructions can be executed in parallel Cycle 16 32 and 40 bit fixed point operands 32 and 64 bit floating point operands a Instruction parallelism is detected at compile time data dependency checking 15 done Hardware Instruction Packing Reduces Code Size All operations work on registers Memory Architecture 4K Byte L1P Program Cache Direct Mapped a 4K Byte L1D Data Cache 2 Way Set Associative O 64K Byte L2 Unified Mapped RAM L2 Cache Flexible Data Program Allocation TU Dresden 4 29 2008 Slide 19 Functional Block and CPU Diagram KE BME 4 device Program cache program memory 32 bit address 256 bit data C62x C64x C67x CPU Power Program fetch down Instruction dispatch See Note Control registers Instruction decode DMA EMIF Data path A Data path B Control Register file A Register file B logic III D Additional peripherals Timers serial ports etc Data cache data memory 32 bit address 8 16 32 bit data 64 bit data C64x only TU olide 20 A 6711 Datapath universirar DRESDEN vodafone chair src Arithmetic Logical ut _ ERN amp Branch functions long dst long src M 32 Regist Multiply Rotation File A Bit expansion EN D
7. and change the program flow Branches are very useful in conjunction with conditional execution here are two branch types supported Relative Branching Absolute Branching TU Dresden 4 29 2008 Slide 31 TECHNISCHE More on the Branch Instruction 1 universirar DRESDEN vodafone chair With this processor all the instructions are encoded in a 32 bit Therefore the label must have a dynamic range of less than 32 bit as the instruction B has to be coded 32 bit Cc OO 21 bit relative address Case 1 SI label Relative branch Label limited to 220 offset TU Dresden 4 29 2008 Slide 32 TECHNISCHE More on the Branch Instruction 2 7 universirar DRESDEN vodafone chair By specifying a register as an operand instead of a label it is possible to have an absolute branch This will allow a dynamic range of 222 32 bit 58 Pup code Case 2 52 register Absolute branch Operates on S2 ONLY TU Dresden 4 29 2008 Slide 33 5 Getting Data from the Memory universirar vodafone chair All Instructions work exclusively on Registers The D Units in the Data Paths are used to load and store the required Data from and to the Memory Load and Store Instructions use an Address operator X LDW D1 5 STW D2 B11 xX TU Dresden 4 29 2008 Slide 34 TECHNISCHE Addressing Mode
8. to the A D D A daughter card TU Dresden 4 29 2008 Slide 42 eum Omm vodafone chair MONOLITHIC 20 BIT DS ADC AND DAC 16 20 BIT INPUT OUTPUT DATA HARDWARE CONTROL PCM3003 STEREO ADC SNR 90dB amp DynamicRange 90dB STEREO DAC SNR 94dB amp Dynamic Range 94dB Digital Attenuation 256 Steps Soft Mute Digital Loop Back SAMPLING RATE Up to 48kHz SYSTEM CLOCK 256fs 384fs 51215 Lehin Digital imi Si Digital Out Analog Front End Uma Decimation Filter Digital In serial Interface and Mode Control Lch Out Low Pass Filter Multi Level and Delta Sigma Rch Out Output Buffer Modulator Serial Mode Control 4 System Clock TU Dresden 4 29 2008 Slide 43 TECHNISCHE What is the bootloader UNIVERSITAT amme Chair m dd VCC Boot Config es gt C6211 C6711 When DSP is NOT powered or under reset the internal program memory Is random state Dresden 4 29 2008 5 44 TECHNISCHE What 1 the bootloader UNIVERSITAT DRESDEN VCC Boot Config nu e HR 8 18 DMA EMIF C6211 C6711 When the DSP is powered and the CPU is taken out of reset the internal memory Is still In a random state and the program will start running for address zero TU Dresden 4 29 2008 Slide 45 TECHNI
9. MHz C6711 DSP TI 16 bit A D Converter AD535 External Memory 1 dr E cn Risch 16M Bytes SDRAM hash ee 128K Bytes Flash ROM LED s Daughter card expansion Power Supply amp Parallel Port Cable Software Code Generation Tools C Compiler Assembler amp Linker B Code Composer Debugger 256K program limitation Example Programs amp S W Utilities Power on Self Test Flash Utility Program se Board Confidence Test Host access DLL Sample Program s m uu D bat 3 E EFFI 1 54 a I 2 a 21 EHH lIETEN pa MEI ii 4 Dre z UNE as W ae x 1 LG 3 SZ Ei 1 rl t A 8 11 erg os di d obese e L pee m e e DER gu T D TO m Zeie ran Sa BR r PP re 1 gt EF LE w Er d TI SST Te Tee Eh HIE TTT ab foes So eee aE n F i T Lu M
10. PLTDP RCPSP RCPDP RSQRSP RSQRDP SPDP Slide 23 C6x System Block Diagram UNIVERSITAT DRESDEN Addr m Internal Buses D 52 aM EMIF il d 2 2 Control Regs CPU TECHNISCHE C6000 Internal Buses universirar DRESDEN vodafone chair Program Addr Internal Program Data Memory External Data Addr T2 x32 DMA Addr Write x32 TU Dresden 4 29 2008 Slide 25 TECHNISCHE UNIVERSITAT How are Peripherals Controlled universi vodafone chair Control and configuration of internal peripherals is done by memory mapped control registers There is a separate memory mapped register file of control registers Example of Timer mode control register TU Dresden 4 29 2008 Slide 26 UNIVERSITAT DRESDEN 64K X 8 Internal vodafone chair L2 cache C6711 Memory universirar External Memor P On chip Peripherals N 256M x 8 SEI TTT Gene TU Dresden 4 29 2008
11. SCHE What is the bootloader UNIVERSITAT ee Boot Config mE gt DMA C6211 C6711 With the boot a portion of code can be automatically copied from external to internal memory TU Dresden 4 29 2008 Slide 46 UNIVERSITAT Interrupts DRESDEN vodafone chair DSPs must be able to execute tasks on asynchronous events Interrupts suspend the current processor task and save Its context A interrupt service routine ISR is executed After completion of the ISR the context of the former task 15 restored and the execution continues Interrupts are organized hierarchically gt vs Polling TU Dresden 4 29 2008 Slide 47 Interrupt Interrupt and Thread Types UNIVERSITAT DRESDEN vodafone chair HWI priorities set by hardware gt One ISR per interrupt Hardware Interrupts 14 SWI priority levels Multiple SWlIs each level software Interrupts 15 TSK priority levels Multiple TSKs at each level gt roe m mum E Em Multiple IDL functions gt Continuous loo Background gt HWI triggered by hardware interrupt gt IDL runs as the background thread TU Dresden 4 29 2008 Slide 48 TECHNISCHE 4 UNIVERSITAT DRESDEN vodafone chair The DSK6 711 Development Kit TU Dresden 4 29 2008 Slide 49 Pe Wm TECHNISCHE eun UNIVERSITAT 1 E E i Hardware 150
12. TECHNISCHE UNIVERSITAT DRESDEN Vodafone Chair Mobile Communications Systems Prof Dr Ing G Fettweis _ vodafone chair Digital Signal Transmission Lab oo 08 Oliver Arnold EN EON Steffen Kunze wes HE P ege 1 LE I d CA Wi E E a mu Pa D 75 TCU eee neta te a D R db ee 1 Bo 5 2 ET vem iT E F d 4 RT Kr d Pe ER EE l 1 LIS 2 LI zm T D NET P iHi d Pro aas bii RK m D ene H mmm HE OUER 4 m ut jee WI i F a a Di L IEEEBBER ETET 9 11 UI UL LERLE Tu CEET ELI d TTA E u am E _ BA IF j tia E EH EET EEL AsAT Tih jij all 5 1 Li Li LE I AU ar i L EE e d wu 2 D ob Le CHEM Fete rae i D 4 a el al M SKI 1 pte a 1 E I gt AA 1 Em P HET 1 d CH 1
13. ata addressin ds NENNEN 9 NEZ Only way to access WW E memory th Cf E oe 4 2 D2 1X src1 TU Dresden 4 29 2008 Slide 21 TECHNISCHE Functional Units and Operations Performed vodafone chair Functional Unit Fixed Point Operations Floating Point Operations L unit L1 L2 32 40 bit arithmetic and compare operations Arithmetic operations Leftmost 1 or 0 bit counting for 32 bits Conversion operations Normalization count for 32 and 40 bits SP INT DP INT SP 32 bit logical operations 5 unit 51 S2 32 bit arithmetic operations Compare reciprocal and reciprocal 32 40 bit shifts and 32 bit bit field operations square root operations 32 bit logical operations Absolute value operations Branches SP to DP conversion operations Constant generation Register transfers to from the control register file 52 only unit M1 M2 16 x 16 bit multiply operations 32 x 32 bit multiply operations Floating point multiply operations D unit D1 D2 32 bit add subtract linear and circular address Load double word with a 5 bit calculation constant offset Loads and stores with a 5 bit constant offset Loads and stores with a 15 bit constant offset D2 only TU Dresden 4 29 2008 Slide 22 C6700 Instruction Set CL Universitat TU Dresden 4 29 2008 DRESDEN ABSSP ABSDP CMPGTSP CMPEQSP CMPLTSP CMPGTDP CMPEQDP CM
14. ecutable COFF object file COFF file Linker Runtime library Linker command file TU Dresden 4 29 2008 Slide 53
15. n to Improved reliability market Reduction in system noise Low overall system cost TU Dresden 4 29 2008 Slide 14 CHNISC Floating vs Fixed point processors universirar vodafone chair Applications which require High precision Wide dynamic range High signal to noise ratio Ease of use gt Need a floating point processor Drawback of floating point processors Higher power consumption Usually higher cost Usually slower than fixed point counterparts and larger in size TU Dresden 4 29 2008 Slide 15 TECHNISCHE 4 UNIVERSITAT DRESDEN vodafone chair 1 5320 6711 Architectural Overview TU Dresden 4 29 2008 Slide 16 General DSP System Block Diagram CL universirar DRESDEN vodafone chair Internal Memory Internal Buses External Memory Central Processing Unit un m umi etm TU Dresden 4 29 2008 Slide 17 TECHNISCHE 6711 CPU Overview UNIVERSITAT vodafone chair Specification Clock Rate 100 150 MHz 600 900 MFLOPS a 0 18 um 5 Level Metal Process CMOS Technology CPU has got two Datapaths altogether Four ALUs Floating and Fixed Point Two ALUs Fixed Point Two Multipliers Floating and Fixed Point Load Store Architecture a 216 32 Bit General Purpose Registers TU Dresden 4 29 2008 Slide 18 6711 CPU Overview CL Universitat DRESDEN vodafone chair VelociT l gt
16. s UNIVERSITAT DRESDEN vodafone chair here are two addressing modes supported Linear Addressing Circular Addressing e g Convolution Circular Addressing supports block sizes 2 Only the lower bits of the Address are modified by address arithmetic This equals mod 2 operations he addressing mode 15 selected by control register AMR Operands for CA are limited to A4 A7 4 7 TU Dresden 4 29 2008 Slide 35 CHNISC Floating vs Fixed point processors universi TAT vodafone chair Fixed point arithmetic 16 bit integer or fractional Signed or unsigned Floating point arithmetic 32 bit single precision 64 bit single precision Using signed and unsigned integers N 1 Multiplication overflow y n 2 xn k Addition overflow gt Saturate the result Double precision result Fractional arithmetic e g If A and B are fractional then A x B lt min A B TU Dresden 4 29 2008 Slide 36 C6000 Data Types UNIVERSITAT DRESDEN vodafone chair Type Size Representation char signed char 9 bits ASCII unsigned char 9 bits ASCII int signed int 32 bits 2s complement unsigned int 32 bits binary 5 complement pointers binary TU Dresden 4 29 2008 Slide 37 3 J TECHNISCHE Numerical Issues Useful Tips UNIVERSITAT vodafone chair Multiply by 2 Use shitt left Divide by 2
17. y difficult if not impossible for analogue signal processing to achieve similar performance Examples FIR filter with linear phase Adaptive filters TU Dresden 4 29 2008 Slide 6 o TECHNISCHE Why Go Digital UNIVERSITAT vodafone chair Analogue signal processing 15 achieved by using analogue components such as Resistors Capacitors a Inductors The inherent tolerances associated with these components temperature voltage changes and mechanical vibrations can dramatically affect the effectiveness of the analogue circuitry TU Dresden 4 29 2008 Slide 7 o TECHNISCHE Why Go Digital UNIVERSITAT vodafone chair With DSP It is easy to Change applications Correct applications Update applications Additionally DSPs reduce a Noise susceptibility Chip count a Development time a Cost Power consumption TU Dresden 4 29 2008 Slide 8 TECHNISCHE 4 UNIVERSITAT DRESDEN vodafone chair General Introduction to DSPs TU Dresden 4 29 2008 Slide 9 TECHNISCHE 4 UNIVERSITAT DRESDEN ADC DAC Digital sampling of an analog signal A What are the typical DSP algorithms UNIVERSITAT DRESDEN vodafone chair The Sum of Products SOP 15 the key element in most DSP algorithms Finite Impulse Response Filter y n 2 4 Infinite Impulse Response Filter y 2 a x n k buy E k 0 k N Convolution
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