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Texas Instruments TSB12LV26 User's Manual

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1. Register Physical request filter high Type Read Set Clear Offset 1101 set register 114h clear register Default 0000 0000h Table 4 25 Physical Request Filter High Register Description BIT FIELD NAME TYPE DESCRIPTION gt Sanaa If this bitis set for local bus node number 53 then physical requests received by the TSB12LV26 physRednesourcesa from that node are handled through the physical request context If this bitis set for local bus node number 52 then physical requests received by the TSB12LV26 20 from that node are handled through the physical request context 4 31 Table 4 25 Physical Request Filter High Register Description Continued 4 32 4 35 Physical Request Filter Low Register The physical request filter low set clear register is used to enable physical receive requests on a per node basis and handles the lower node IDs When a packet is destined for the physical request context and the node ID has been compared against the asynchronous request filter registers then the node ID comparison is done again with this register If the bit corresponding to the node ID is not set in this register then the request is handled by the asynchronous request context instead of the physical request context See Table 4 26 for a complete description of the register contents 31 29 28 27 26 25 24
2. ear o o TX Register Interrupt event Type Read Set Clear Update Read Set Clear Read Update Read only Offset 80h set register 84h clear register returns the content of the interrupt event and interrupt mask registers when read Default XXXX OXXXh Table 4 14 Interrupt Event Register Description FIELD NAME TYPE DESCRIPTION RSVD R Reserved Bit 31 returns 0 when read m This vendor specific interrupt event is reported when either of the general purpose interrupts occur 30 vendorSpecific which are enabled via INT3 EN and INT2 EN in the GPIO control register offset FCh see Section 3 23 29 27 RSVD Bits 29 27 return 0s when read RSCU The TSB12LV26 has received a PHY register data byte which can be read from the PHY layer control register OHCI offset ECh see Section 4 30 If bit 21 cycleMaster of the link control register offset EOh E4h see Section 4 28 is set then cycleTooLong RSCU this indicates that over 125 us have elapsed between the start of sending a cycle start packet and the end of a subaction gap The link control register bit 21 cycleMaster is cleared by this event This event occurs when the TSB12LV26 encounters any error that forces it to stop operations on any RSCU unrecoverableError or all of its subunits for example when a
3. aavco 39 9 61 28 PHYDATMe 82 _ 33Voc The terminals in Table 2 3 through Table 2 8 are grouped in tables by functionality such as PCI system function and power supply function The terminal numbers are also listed for convenient reference E Ed Eod E ER En 0 Table 2 3 Power Supply Terminals TERMINAL DESCRIPTION 1 11 24 30 50 60 75 83 Device ground terminals 94 6 s 63 x PCI signaling clamp voltage power input PCI signals are clamped per the PCI Local Bus Specification 9 13 20 35 3 3 46 55 70 80 3 3 V power supply terminals 91 96 2 3 Table 2 4 PCI System Terminals E DESCRIPTION Global power reset This reset brings all of the TSB12LV26 internal registers to their default states including those registers not reset by PCI_RST When G_RST is asserted the device is completely nonfunctional RST When implementing wake capabilities from the 1394 host controller it is necessary to implement two resets to the TSB12LV26 RST should be a one time power on reset and RST should be connected to the PCI bus RST If wake capabilities are not required G_RST may be connected to the PCI bus RST see PCI RST terminal 76 PCI INTA Interrupt signal This output indicates interrupts from the
4. 4 17 Interrupt Mask Register Description 4 19 Isochronous Transmit Interrupt Event Register Description 4 20 Isochronous Receive Interrupt Event Register Description 4 22 Fairness Control Register Description 4 23 Link Control Register Description 4 24 Node Identification Register Description 4 25 PHY Control Register Description 4 26 Isochronous Cycle Timer Register Description 4 27 Asynchronous Request Filter High Register Description 4 28 Asynchronous Request Filter Low Register Description 4 30 Physical Request Filter High Register Description 4 31 Physical Request Filter Low Register Description 4 33 Asynchronous Context Control Register Description 4 35 Asynchronous Context Command Pointer Register Description 4 36 Isochronous Transmit Context Control Register Description 4 37 Isochronous Receive Context Control Register Description 4 38 Isochronous Receive Context Match Register Description 4 41 Registers and Loadable through Serial ROM 6 1 Serial iere xe 6 2 1 Introduction 11 Description T
5. 2 3 POL System TemlbldlS sex ace ee CA Ron weer 2 4 PCI Address and Data Terminals 2 5 PCI Interface Control 2 6 IEEE 1394 PHY Link Terminals 2 7 Miscellaneous Terminals 2 7 Bit Field Access Tag Descriptions 3 1 PCI Configuration Register Map 3 3 Command Register Description 3 4 Status Register Description 3 5 Class Code and Revision ID Register Description 3 6 Latency Timer and Class Cache Line Size Register Description 3 6 Header Type and BIST Register Description 3 7 Base Address Register Description 3 7 Subsystem Identification Register Description 3 8 Interrupt Line and Pin Register Description 3 9 MIN and MAX LAT Register Description 3 10 Control Register Description 3 10 Capability ID and Next Item Pointer Register Description 3 11 Power Management Capabilities Register Description 3 12 Power Management Control and Status Register Description 3 13 Power Management Extension Register Descr
6. Receive Context Control Register 4 38 4 42 Isochronous Receive Context Command Pointer Register 4 40 4 43 Isochronous Receive Context Match Register 4 41 GPIO Interface ns 5 1 Serial HOM Interface essor hah RR REIS 6 1 Electrical Characteristics IRE ERR ELSE 7 1 7 1 Absolute Maximum Ratings Over Operating Temperature Ranges 7 1 7 2 Recommended Operating Conditions 7 2 7 3 Electrical Characteristics Over Recommended Operating Conditions 7 3 7 4 Switching Characteristics for PCI Interface 7 3 Switching Characteristics for PHY Link Interface 8 Mechanical Information vi List of Illustrations Figure Title Page 2 1 Terminal Assignments 2 1 TSB12LV26 Block Diagram 3 2 5 1 2 and Logic Diagram 5 1 Table EO 4 1 dh List of Tables Title Page Signals Sorted by Terminal Number 2 2 Signal Names Sorted Alphanumerically to Terminal Number 2 3 Power Supply Terminals IRR
7. 4 4 4 2 GUID ROM Register 4 5 43 X Asynchronous Transmit Retries Register 4 6 4 4 CSR Bala Register 4 6 45 CSR Compare Register 4 7 4 6 CSR Control Register 4 7 4 7 Configuration ROM Header Register 4 8 4 8 Bus Identification Register 4 8 4 9 Bus Options Register 4 9 4 10 GUID High 4 10 4 71 GUID Low ERR 4 10 4 12 Configuration ROM Mapping Register 4 11 4 13 Posted Write Address Low Register 4 11 4 14 Posted Write Address High Register 4 12 4 15 Vendor ID Register 4 12 4 16 Host Controller Control Register 4 13 4 17 Self ID Buffer Pointer Register 4 14 4 18 Self ID Count Register 4 14 4 19 Isochronous Receive Channel Mask High Register 4 15 4 20 Receive Channel Mask Low Register 4 16 421 Interrupt Event Register
8. PCI CLKRUN PCI DEVSEL PCI FRAME PCI IRDY PCI PAR PCI PERR PCI PME A 44 5 A A aE Table 2 6 PCI Interface Control Terminals PCI bus commands and byte enables The command and byte enable signals are multiplexed on the same PCI terminals During the address phase of a bus cycle PCI C BEO defines the bus command During the data phase this 4 bit bus is used as byte enables Clock run This terminal provides clock control through the CLKRUN protocol An internal pulldown resistor is implemented on this terminal This terminal is implemented as open drain PCI device select The TSB12LV26 asserts this signal to claim a PCI cycle as the target device As a PCI initiator the TSB12LV26 monitors this signal until a target responds If no target responds before time out occurs then the TSB12LV26 terminates the cycle with an initiator abort PCI cycle frame This signal is driven by the initiator of a PCI bus cycle PCI FRAME is asserted to indicate that a bus transaction is beginning and data transfers continue while this signal is asserted When PCI FRAME is deasserted the PCI bus transaction is in the final data phase PCI bus grant This signal is driven by the PCI bus arbiter to grant the TSB12LV26 access to the PCI bus after the current data transaction has completed This signal may or may not follow a PCI bus request depending upon the
9. 52 then asynchronous requests received by the 5 a 51 then asynchronous requests received by the 4 28 Table 4 23 Asynchronous Request Filter High Register Description Continued FIELD NAME TYPE DESCRIPTION ReaR 50 If this bit is set for local bus node number 50 then asynchronous requests received by the TSB12LV26 from that node are accepted nReaR 6848 If this bit is set for local bus node number 49 then asynchronous requests received by the TSB12LV26 from that node are accepted ReaR 48 If this bit is set for local bus node number 48 then asynchronous requests received by the TSB12LV26 from that node are accepted nReaR 47 If this bit is set for local bus node number 47 then asynchronous requests received by the TSB12LV26 from that node are accepted ReaR 46 If this bit is set for local bus node number 46 then asynchronous requests received by the TSB12LV26 from that node are accepted nReaR If this bit is set for local bus node number 45 then asynchronous requests received by the asynneqnesource TSB12LV26 from that node are accepted asynReqResource44 asynReqResource43 asynReqResource42 If this bit is set for local bus node number 44 then asynchronous requests received by the TSB12LV26 from that node are accepted If this bit is set for local bus node number 43 then asynchronous
10. 10 9 8 7 5 4 2 1 Device ID 8 S S S o OE pem fo fo fo fo Register Device ID Type Read only Offset 02h Default 8020h 3 4 Command Register The command register provides control over the TSB12LV26 interface to the PCI bus All bit functions adhere to the definitions in the Local Bus Specification as seen in the bit descriptions of Table 3 3 __ 15 t 1 10 9 8 7 5 4 2 _____ __ _____ __ R in Rw Rw Rw R pem fo Register Command Type Read Write Read only Offset 04h Default 0000h Table 3 3 Command Register Description FIELD TYPE DESCRIPTION 15 10 RSVD R Reserved Bits 15 10 return Os when read FBB ENB Fast back to back enable The TSB12LV26 does not generate fast back to back transactions thus this bit returns 0 when read SERR ENB PCI SERR SERRenable When this bitis set the TSB12LV26 PCI SERR SERR driver is enabled PCI_SERR SERRcan be asserted after detecting an address parity error on the PCI bus Address data stepping control The TSB12LV26 does not support address data stepping thus this bit STEP_E
11. RW R hRRwiRw R FR BR Pm pea 1 Register Bus options Type Read Write Read only Offset 20h Default AOX2h Table 4 7 Bus Options Register Description BIT FIELDNAME TYPE DESCRIPTION 34 mie Isochronous resource manager capable IEEE 1394 bus management field Must be valid when bit 17 i linkEnable of the host controller control register OHCI offset 50h 54h see Section 4 16 is set m Cycle master capable IEEE 1394 bus management Must valid when bit 17 linkEnable of the host controller control register OHCI offset 50h 54h see Section 4 16 is set Isochronous support capable IEEE 1394 bus management field Must be valid when bit 17 linkEnable of the host controller control register OHCI offset 50h 54h see Section 4 16 is set Bus manager capable IEEE 1394 bus management field Must be valid when bit 17 linkEnable ofthe host controller control register OHCI offset 50h 54h see Section 4 16 is set Power management capable When set this indicates that the node is power management capable Must be valid when bit 17 linkEnable of the host controller control register offset 50h 54h see Section 4 16 is set 26 24 RSVD Bits 26 24 return 0 when read Cycle master clock accuracy in parts per million
12. timer begins counting from zero If the latency timer expires before the TSB12LV26 transaction has terminated then the TSB12LV26 terminates the transaction when its PCI GNT is deasserted 7 0 CACHELINE SZ R W Cache line size This value is used by the TSB12LV26 during memory write and invalidate memory read line and memory read multiple transactions 3 6 3 8 Header Type and BIST Register The header type and BIST register indicates the TSB12LV26 PCI header type and indicates no built in self test See Table 3 7 for a complete description of the register contents 15 1 1 12 9 8 7 5 4 2 Header type and BIST Name 77 22 mee pea fo fo Register Header type and BIST Type Read only Offset OEh Default 0000h Table 3 7 Header Type and BIST Register Description FIELD NAME TYPE DESCRIPTION Built in self test The TSB12LV26 does not include a built in self test thus this field returns 00h when 15 8 read PCI header type The TSB12LV26 includes the standard PCI header and this is communicated by HEADER_TYPE returning 00h when this field is read 3 9 Base Address Register The OHCI base address register is programmed with a base address referencing the memory mapped OHCI control When B
13. 29 24 return Os when read This bit informs upper level software that lower level software has consistently configured the P1394a enhancements in the Link and PHY When this bit is 1 generic software such as the driver is responsible for configuring P1394a enhancements in the PHY and bit 22 aPhyEnhanceEnable in the TSB12LV26 When this bit is 0 the generic software may not modify the P1394a enhancements in the TSB12LV26 or PHY and cannot interpret the setting of bit 22 aPhyEnhanceEnable This bit is initialized from serial EEPROM When bits 23 programPhyEnable and 17 linkEnable are 1 the OHCI driver can set this bit to aPhyEnhanceEnable use all P1394a enhancements When bit 23 programPhyEnable is set to 0 the software does not change PHY enhancements or this bit 15 14 13 12 30 9 8 7 5 4 2 1 programPhyEnable 21 20 RSVD Reserved Bits 21 20 return Os when read This bit is used to control the link power status Software must set this bit to 1 to permit link PHY communication A 0 prevents link PHY communication This bit is used to enable 1 or disable 0 posted writes Software should change this bit only when bit 17 linkEnable is 0 This bit is cleared to 0 by either a hardware or software reset Software must set this bit to 1 when the system is ready to begin operation and then force a bus reset This bit is necessary to keep 17 linkEnabl
14. A bit description table typically included when the register contains bits of more than one type or purpose indicates bit field names field access tags which appear in the type column and a detailed field description Table 3 1 describes the field access tags Table 3 1 Bit Field Access Tag Descriptions Rea Field be read by software Field may be written by software to any value Set Field may be set by a write of 1 Writes of 0 have no effect Field may be cleared by a write of 1 Writes of 0 have no effect Update Field may be autonomously updated by the TSB12LV26 A simplified block diagram of the TSB12LV26 is provided in Figure 3 1 3 2 Host Bus Interface PCI Target SM Internal Registers OHCI PCI Power Mgmt amp CLKRUN ISO Transmit MISC Contexts Interface Async Transmit Transmit Contexts FIFO Physical DMA Link amp Response Transmit Receive Acknowledge Central PHY Arbiter Register Cycle Start 55 Generator amp Pel amp Status Cycle Monitor Initiator Monitor SM Request Filters General Request Receive Async Response Receive Receive FIFO ISO Receive Contexts Figure 3 1 TSB12LV26 Block Diagram Resp Timeout PHY Link Synthesized Interface Link Receive 3 1 PCI Configuration Registers The TSB12LV26 is a single function PCI device The configuration header is co
15. Name 77777 isochonoustansmitcontextcommandponter we pea x x x x Tx Tx Px tx Px tx tx Tx Tx x Register Isochronous transmit context command pointer Type Read only Offset 20Ch 16 n Default XXXX XXXXh 4 41 Isochronous Receive Context Control Register The isochronous receive context control set clear register controls options state and status for the isochronous receive DMA contexts The n value in the following register addresses indicates the context number n 0 1 2 3 See Table 4 30 for a complete description of the register contents 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Isochronous receive context control RSU RSC R R R R R R R R R __ 15 14 13 12 t 10 8 7 6 5 Jo Name isocronosrecevecontextconrl Type Rscu R R RSU RU RU R R RU RU RU RU RU RU RU RU peau o Register Isochronous receive context control Type Read Set Clear Update Read Set Clear Read Update Read only Offset 400h 32 n set register 404h 32 n clear register Default X000 XOXXh Table 4 30 Isochronous Receive Context Contr
16. R n jRu a R R A pem fo 1 1 Register Status Type Read Clear Update Read only Offset 06h Default 0210h Table 3 4 Status Register Description FIELD NAME TYPE DESCRIPTION PAR_ERR Detected parity error This bit is set when a parity error is detected either address or data parity errors 14 SYS ERR RCU Signaled system error This bit is set when PCI SERR is enabled and the TSB12LV26 has signaled a system error to the host 13 MABORT RCU Received master abort This bit is set when a cycle initiated by the TSB12LV26 on the PCI bus has been terminated by a master abort 12 TABORT REC RCU Received target abort This bit is set when a cycle initiated by the TSB12LV26 on the PCI bus was terminated by a target abort TABORT SIG Signaled target abort This bit is set by the TSB12LV26 when it terminates a transaction on the PCI bus with a target abort PCI SPEED DEVSEL timing Bits 10 9 encode the timing of PCI DEVSEL and are hardwired to 01b indicating that the TSB12LV26 asserts this signal at a medium speed on nonconfiguration cycle accesses Data parity error detected This bit is set when the following conditions have been met DATAPAR PCI was asserted by any PCI device including the TSB12LV26 b The TSB12LV26 was the bus master during the data parity error c The parity error response bit is set in the PCI command register
17. UNIT tsu Setup time Dn CTLn LREQ to PHY_CLK 50 050 6 ms th Hold time Dn CTLn LREQ before 50 to 50 tq Delay time PHY_CLK to Dn CTLn 50 to 50 These parameters are ensured by design 7 3 8 Mechanical Information The TSB12LV26 is packaged in a 100 terminal PZ package The following shows the mechanical dimensions for the PZ package PZ S PQFP G100 PLASTIC QUAD FLATPACK 0 13 NOM ke 12 00 TYP Sese Planet 14 20 13 80 16 20 15 80 59 Y Seating Plane 1 60 MAX La Z 0 08 4040149 B 11 96 NOTES A Alllinear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MO 136 8 2 IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accorda
18. When this bit is set and the PHY has notified the TSB12LV26 that the PHY is root the TSB12LV26 generates a cycle start packet every time the cycle timer rolls over based on the setting of bit 22 21 cycleMaster RSCU When this bit is cleared the OHCI Lynx accepts received cycle start packets to maintain synchronization with the node which is sending them This bit is automatically cleared when bit 25 cycleTooLong of the interrupt event register OHCI offset 80h 84h see Section 4 21 is set and cannot be set until bit 25 cycleTooLong is cleared CycleTimerEnable appropriate time based on the settings of the above bits When this bitis cleared the cycle timer offset does not count 19 11 RSVD Reserved Bits 19 11 return Os when read 1 RcvPhyPkt RSC When this bit is set the receiver accepts incoming PHY packets into the AR request context if the AR request context is enabled This does not control receipt of self ID packets E When this bit is set the cycle timer offset counts cycles of the 24 576 MHz clock and rolls over at the 20 RevSelflD RSC When this bit is set the receiver accepts incoming self ID packets Before setting this bit to 1 ee software must ensure that the self ID buffer pointer register contains a valid address RSVD Reserved Bits 8 0 return Os when read 4 24 4 29 Node Identification Register The node identification register contains the address of the node on which OHCI Lynx
19. 3 22 Subsystem Access Register Write access to the subsystem access register updates the subsystem identification registers identically to OHCI Lynx The system ID value written to this register may also be read back from this register See Table 3 19 for a complete description of the register contents m 2 Subsystem access fau 0 fo fo 15 14 13 12 1 v0 9 J 8 j e s 4 2 t Name paw fo fo Register Subsystem access Type Read Write Offset F8h Default 0000 0000h Table 3 19 Subsystem Access Register Description FIELD TYPE DESCRIPTION 31 16 SUBDEV_ID Subsystem device ID This field indicates the subsystem device ID SUBVEN ID Subsystem vendor ID This field indicates the subsystem vendor ID 3 23 GPIO Control Register The GPIO control register has the control and status bits for the GPIO2 and GPIO3 ports See Table 3 20 for a complete description of the register contents s so 29 28 z7 26 25 24 23 22 21 20 19 18 17 16 GPIO control RW Rn RW RW R R RW eso 15 t 1 1
20. Name _____________ OO _______________ O e Vendor ID Type Read only Offset 40h Default 0000 0000h 4 12 4 16 Host Controller Control Register The host controller control set clear register pair provides flags for controlling the TSB12LV26 See Table 4 10 for a complete description of the register contents 31 so 29 26 27 26 25 24 23 22 21 20 1 18 17 16 Host controller control Hye 8 n R 955 R_ asc Asc nscu Demer 9 X 9 9 191 9 9 9 1 9 9 9 5 9 Host controller control po Host controllercontrol r R rR o Register Host controller control Type Read Set Clear Update Read Set Clear Read Clear Read only Offset 50h set register 54h clear register Default X00X 0000h Table 4 10 Host Controller Control Register Description FIELD NAME TYPE DESCRIPTION RSVD Reserved Bit 31 returns 0 when read ByteS Dat This bit is used to control whether physical accesses to locations outside the TSB12LV26 itself as moby owe adt well as any other DMA data accesses should be swapped 29 24 RSVD Reserved
21. Offset 3Ch Default 0100h Table 3 10 Interrupt Line and Pin Register Description FIELD NAME TYPE DESCRIPTION 15 8 INTR PIN Interrupt pin Returns 01h when read indicating that the TSB12LV26 PCI function signals interrupts on B the PCI INTA pin INTR LINE Interrupt line This field is programmed by the system and indicates to software which interrupt line the TSB12LV26 PCI_INTA is connected to 3 9 3 14 MIN GNT and MAX LAT Register The MIN GNT and MAX LAT register is used to communicate to the system the desired setting of bits 15 8 of the latency timer and class cache line size register offset OCh see Section 3 7 If a serial ROM is detected then the contents of this register are loaded through the serial ROM interface after a PCI reset If no serial ROM is detected then this register returns a default value that corresponds to the MIN GNT 2 MAX LAT 4 See Table 3 11 for a complete description of the register contents 15 t 19 12 10 7 5 a 2 Name MINGNTandMAXLAT ________ MIN GNT and LAT Register MIN_GNT and MAX_LAT Type Read Update Offset 3Eh Default 0402h Table 3 11 MIN_GNT and MAX_LAT Register Description FIELD NAME TYPE DESCRIPTION Maximum latency The contents of this register may be used by host BIOS to assign an arbitration 15 8
22. When this bit is set all quadlets read from and written to the PCI interface are byte swapped big endian This bit is loaded from ROM and should be programmed to 0 for normal operation 3 16 Capability ID and Next Item Pointer Register The capability ID and next item pointer register identifies the linked list capability item and provides a pointer to the next capability item See Table 3 13 for a complete description of the register contents 15 t 1 12 1 9 8 7 6 5 4 3 2 1 Capability ID and next item pointer Dandnextitem pointer pes mpm m mmo mm pem o Register Capability ID and next item pointer Type Read only Offset 44h Default 0001h Table 3 13 Capability ID and Next Item Pointer Register Description FIELD NAME TYPE DESCRIPTION 15 8 NEXT ITEM Next item pointer The TSB12LV26 supports only one additional capability that is communicated to the system through the extended capabilities list thus this field returns 00h when read 7 0 CAPABILITY_ID Capability identification This field returns 01h when read which is the unique ID assigned by the PCI SIG for PCI power management capability 3 17 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the TSB
23. offset 04h see Section 3 4 FBB CAP Fast back to back capable The TSB12LV26 cannot accept fast back to back transactions thus this bit is hardwired to 0 User definable features UDF supported The TSB12LV26 does not support the UDF thus this bit is hardwired to 0 5 66MHZ 66 MHz capable The TSB12LV26 operates at a maximum CLK frequency of 33 MHz therefore this bit is hardwired 10 0 CAPLIST Capabilities list This bit returns 1 when read indicating that capabilities additional to standard PCI are implemented The linked list of power management capabilities is implemented in this function RSVD Reserved Bits 3 0 return 05 when read 3 5 3 6 Class Code and Revision ID Register The class code and revision ID register categorizes the TSB12LV26 as a serial bus controller OCh controlling an IEEE 1394 bus 00h with an OHCI programming model 10h Furthermore the TI chip revision is indicated in the least significant byte See Table 3 5 for a complete description of the register contents Class code and revision ID Name 7 Classcodeandrevison ID mwe in Hm pea fo Register Class code and revision ID Type Read only Offset 08h Default 1000h Table 3 5 Class Code and Revision ID Register Description FIELD NAME TYPE DESCRIPTI
24. wo TERMINAL NO TERMINAL NAME wo TERMINAL NAME x ea s Pores s o wee eB Pos 7 oaos 93 ee PHY_UNKON 2 2 Table 2 2 Signal Names Sorted Alphanumerically to Terminal Number TERMINAL NAME wo TERMINAL NAME wo TERMINAL NAME wo TERMINAL NAME m s 7 uos Poroeven ws ases roas s 95 o 70 o e rece feof 7 6 2 1 o ar eem ve e n o a a 2 55 5
25. x x x x x x x x x x tx x x x 15 13 12 10 9 7 6 S5 4 3 2 1 CSR compare x x x x x x j x j x x x x j x j x j x j x j x Register CSR compare Type Read only Offset 10h Default XXXX XXXXh 4 6 CSR Control Register The CSR control register is used to access the bus management CSR registers from the host through compare swap operations This register is used to control the compare swap operation and to select the CSR resource See Table 4 5 for a complete description of the register contents 31 29 28 27 26 25 24 23 22 zi 20 18 17 16 CSR control CSR control Po 0 0 0 CSR control Type Read Write Read Update Read only Offset 14h Default 8000 000Xh Table 4 5 CSR Control Register Description FIELD DESCRIPTION ime bit is by the TSB12LV26 when compare swap operation is complete It is cleared whenever this register is written 30 2 RSVD R Reserved Bits 30 2 return Os when read EB ES This field selects the CSR resource as follows
26. 00 BUS MANAGER ID csrSel 01 BANDWIDTH AVAILABLE 10 CHANNELS AVAILABLE HI 11 CHANNELS AVAILABLE LO 4 7 Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM offset FFFF F000 0400h See Table 4 6 for a complete description of the register contents so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Configuration ROM header fat o 15 t 1 12 10 9 8 7 6 5 4 2 1 Deut X x x x X X x x X x x tx x x Register Configuration ROM header Type Read Write Offset 18h Default 0000 XXXXh Table 4 6 Configuration ROM Header Register Description BIT FIELDNAME TYPE DESCRIPTION 31 24 info length IEEE 1394 bus management field Must be valid when bit 17 linkEnable of the host controller control 9 register OHCI offset 50h 54h see Section 4 16 is set 23 16 lena IEEE 1394 bus management field Must be valid when bit 17 linkEnable of the host controller control erc eng register OHCI offset 50h 54h see Section 4 16 is set IEEE 1394 bus management field Must be valid at any time bit 17 linkEnable of the host controller 15 0 rom crc value R W control register offset 50h 54h see Section 4 16 is set The reset value is undefined if no serial ROM is pr
27. IEEE 1394 bus management field Must be valid 23 16 cyc clk acc R W when bit 17 linkEnable of the host controller control register offset 50h 54h see Section 4 16 is set Maximum request IEEE 1394 bus management field Hardware initializes this field to indicate the maximum number of bytes in a block request packet that is supported by the implementation This value max rec bytes must be 512 or greater and is calculated by 2 max rec 1 Software may 15 12 max rec R W this field however this field must be valid at any time bit 17 linkEnable of the host controller control register OHCI offset 50h 54h see Section 4 16 is set A received block write request packet with a length greater than max rec bytes may generate an ack type error This field is not affected by a soft reset and defaults to a value indicating 2048 bytes on a hard reset RSVD Reserved Bits 11 8 return Os when read Generation counter This field is incremented if any portion of the configuration ROM has been incremented since the prior bus reset RSVD Reserved Bits 5 3 return Os when read Link speed This field returns 010 indicating that the link speeds of 100 200 and 400 Mbits s are Lnk_spd supported 4 9 4 10 GUID High Register The GUID high register represents the upper quadlet in a 64 bit global unique ID GUID which maps to the third quadlet in the Bus Info Block This register contains node vendor
28. MAX LAT RU priority level to the TSB12LV26 The default for this register indicates that the TSB12LV26 may need to access the PCI bus as often as every 0 25 15 thus an extremely high priority level is requested The contents of this field may also be loaded through the serial ROM Minimum grant The contents of this register may be used by host BIOS to assign a latency timer and class 70 MIN GNT RU cache line size register offset OCh see Section 3 7 value to the TSB12LV26 The default for this register indicates that the TSB12LV26 may need to sustain burst transfers for nearly 64 us thus requesting a large value be programmed in bits 15 8 of the TSB12LV26 latency timer and class cache line size register 3 15 OHCI Control Register The OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a bit for big endian PCI support See Table 3 12 for a complete description of the register contents 3t so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OHCI control OHCI control Name ooo r rw Deant o o fo fo fo fo Register OHCI control Type Read Write Offset 40h Default 0000 0000h Table 3 12 OHCI Control Register Description FIELD NAME TYPE DESCRIPTION RSVD R Reserved Bits 31 1 return 05 when read
29. TSB12LV26 to the host This terminal is implemented as open drain PCI bus clock Provides timing for all transactions on the PCI bus All PCI signals are sampled at rising edge PCI CLK 12 of PCI CLK PCI reset When this bus reset is asserted the TSB12LV26 places all output buffers in a high impedance state and resets all internal registers except device power management context and vendor specific bits initialized by host power on software When PCI RST is asserted the device is completely nonfunctional If this terminal is implemented then it should be connected to the PCI bus RST signal Otherwise it should be pulled high to link through a 4 7 kQ resistor or strapped to the G_RST terminal see G_RST terminal 10 PCI RST wo 1 PCI AD30 PCI AD29 PCI AD28 PCI AD27 PCI AD26 PCI AD25 PCI AD24 PCI AD23 PCI AD22 PCI 21 PCI AD20 PCI AD19 PCI AD18 PCI AD17 PCI AD16 PCI AD15 PCI AD14 PCI AD13 PCI AD12 PCI AD11 PCI AD10 PCI AD9 PCI AD8 PCI 07 PCI AD6 PCI AD5 PCI 4 PCI AD3 PCI AD2 PCI AD1 PCI ADO Table 2 5 PCI Address and Data Terminals PCI address data bus These signals make up the multiplexed PCI address and data bus on the PCI interface lO During the address phase of a PCI cycle AD31 ADO contain a 32 bit address or other destination information During the data phase AD31 ADO contain data 2 5 TERMINAL PCI C BEO PCI C BE1 PCI C BE2 PCI
30. bit is ome set when a register transfer is received from the PHY 30 28 RSVD Reserved Bits 30 28 return Os when read 27 24 rdAddr This is the address of the register most recently received from the PHY 23 16 This field is the contents of a PHY register which has been read This bit is set by software to initiate a write request to a PHY register and is cleared by hardware when the request has been sent Bits 14 wrReg and 15 rdReg must be used exclusively 13 12 RSVD Reserved Bits 13 12 return 05 when read regAddr This field is the address of the PHY register to be written or read This field is the data to be written to a PHY register and is ignored for reads wrReg 15 RWU This bit is set by software to initiate a read request to a PHY register and is cleared by hardware when the request has been sent Bits 14 wrReg and 15 rdReg must be used exclusively 4 26 4 31 Isochronous Cycle Timer Register The isochronous cycle timer register indicates the current cycle number and offset When the TSB12LV26 is cycle master this register is transmitted with the cycle start message When the TSB12LV26 is not cycle master this register is loaded with the data field in an incoming cycle start In the eventthat the cycle start message is not received the fields can continue incrementing on their own if programmed to maintain a local time reference See Table 4 22 for a complete description of the register
31. chip resides and indicates the valid node number status The 16 bit combination of the busNumber field bits 15 6 and the NodeNumber field bits 5 0 is referred to as the node ID See Table 4 20 for a complete description of the register contents Node identification pO Nededemfeaon R nm nin n n in n n Petawn o o fo fe fo feo o 31 so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 13 12 f t0 e jJ e s 4 2 t Node identification 1 1 1 1 1 1 1 1 3 x x j x j x j x x Register Node identification Type Read Write Update Read Update Read only Offset E8h Default 0000 FFXXh Table 4 20 Node Identification Register Description FIELDNAME TYPE DESCRIPTION 34 iDValid RU This bit indicates whether or not the TSB12LV26 has a valid node number Itis cleared when 1394 bus nen reset is detected and set when the TSB12LV26 receives a new node number from the PHY This bit is set during the bus reset process if the attached PHY is root 29 28 RSVD Reserved Bits 29 28 return Os when read Set if the PHY is reporting that cable power status is OK 26 16 RSVD R Reserved Bits 26 16 return Os when read This number is used to identify the specific 1394 bus the TSB12LV26 belongs to w
32. command pointer Register Isochronous receive context command pointer Type Read only Offset 40Ch 32 n Default XXXX XXXXh 4 40 4 43 Isochronous Receive Context Match Register The isochronous receive context match register is used to start an isochronous receive context running on a specified cycle number to filter incoming isochronous packets based on tag values and to wait for packets with a specified sync value The n value in the following register addresses indicates the context number n 0 1 2 3 See Table 4 31 for a complete description of the register contents 3t ao 29 28 27 26 25 24 23 22 zi 20 19 18 16 Isochronous receive context match ______________________ RW Rw Rw RW RAW RW RW RW peau x x x x oo Po x x x x x x x x x 15 1 12 9 8 v e 5 4 3 j 2 1 Isochronous receive context match Name RW pesar x x Ex T T 1X1 Register Isochronous receive context match Type Read Write Read only Offset 410Ch 32 n Default XXXX XXXXh Table 4 31 Isochronous Receive Context Match Register Description sss R Resena Bis 27 25 reum swen re O OOOO O o o o o y y O Contains a 15 bit value corresponding to
33. complete description of the register contents 31 so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Configuration ROM mapping Default 0 I e __ 15 13 12 f 10 e 7 s j 3 2 t Configuration ROM mapping Aw e JR fo Configuration ROM mapping Type Read Write Read only Offset 34h Default 0000 0000h Table 4 8 Configuration ROM Mapping Register Description FIELD NAME TYPE DESCRIPTION If a quadlet read request to 1394 offset FFFF F000 0400h through offset FFFF F000 07FFh is 31 10 configROMaddr R W received then the low order 10 bits of the offset are added to this register to determine the host memory address of the read request Reserved Bits 9 0 return Os when read 4 13 Posted Write Address Low Register The posted write address low register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet This register contains the lower 32 bits of the 1394 destination offset of the write request that failed 29 28 27 26 25 24 23 22 zi 20 18 17 16 Posted write address low po Poste w
34. does not report dynamic data RSVD Reserved Bits 3 2 return Os when read Power state This 2 bit field is used to set the TSB12LV26 device power state and is encoded as follows 00 Current power state is DO 1 0 PWR 01 Current power state is D1 10 Current power state is D2 11 Current power state is D3 3 19 Power Management Extension Register The power management extension register provides extended power management features not applicable to the TSB12LV26 thus it is read only and returns 05 when read See Table 3 16 for a complete description of the register contents pi oe poe pas oue s Power management extension tee pean fo Register Power management extension Type Read only Offset 4Ah Default 0000h Table 3 16 Power Management Extension Register Description FIELD NAME TYPE DESCRIPTION 15 8 PM DATA Power management data This field returns 00h when read since the TSB12LV26 does not report dynamic data 70 Power management CSR bridge support extensions This field returns 00h when read since the TSB12LV26 does not provide P2P bridging 3 20 Miscellaneous Configuration Register The miscellaneous configuration register provides miscellaneous PCl related configuration See Table 3 17
35. enhancement HCControl RSVD RSVD RSVD Link enhancement Link enhancement Control enab unfair ProgramPhy Control enab_ Control enab_accel Enable insert_idle Mini ROM address GUID high Isbyte 0 GUID high byte 1 GUID high byte 2 GUID high msbyte 3 GUID low Isbyte 0 GUID low byte 1 GUID low byte 2 GUID low msbyte 3 OF Checksum 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSVD RSVD RSVD Disable GP2IIC Disable SCLK gate Disable PCI gate Keep PCI Target Abort 15 14 12 10 9 8 PME D3 Cold RSVD RSVD D2 support RSVD RSVD 6 5 4 3 2 1 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD gt 5 11 2 1 EN A 6 2 7 Electrical Characteristics 71 Absolute Maximum Ratings Over Operating Temperature Rangest Supply voltage range 2 0 5 V to 3 6 V Supply voltage range 0 5 V to 5 5 V Input voltage range for PCI 0 5 to 0 5 V Input voltage range for miscellaneous and PHY interface V 0 5 to 0 5 V Output voltage range for PGI riki iiin 0 5 to 0 5 V Input voltage range for miscellaneous and PHY interface Vo 0 5 to 0 5 V Input cla
36. interrupt An interrupt bit is set by the asserting edge of the corresponding interrupt signal or by writing a 1 to the corresponding bit in the set register The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register See Table 4 17 for a complete description of the register contents 9t so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name 777 lsoonousreceieintemupteven Isochronous receive interrupt event Register Isochronous receive interrupt event Type Read Set Clear Read only Offset AOh set register A4h clear register returns the contents of isochronous receive interrupt event and isochronous receive mask registers when read Default 0000 000Xh Table 4 17 Isochronous Receive Interrupt Event Register Description Para Rsv R Isochronous receive channel 1 caused the interrupt event register bit 7 isochRx interrupt RSC Isochronous receive channel 0 caused the interrupt event register bit 7 isochRx interrupt 4 26 Isochronous Receive Interrupt Mask Register The isochronous receive interrupt mask register is used to enable the isochRx interrupt source on a per channel basis Reads from either the set register or the clear register always return the contents of the isochronous receive interrupt mask register In all cases the enables for each interrupt event align with the event
37. is detected This field rolls over to 0 after 15 11 RSVD Reserved Bits 15 11 return Os when read This field indicates the number of quadlets that have been written into the self ID buffer for the current 10 2 selflDSize RU bits 23 16 selflDGeneration field This includes the header quadlet and the self ID data This field is cleared to 0 when the self ID reception begins RSVD R Reserved Bits 1 0 return Os when read 4 14 4 19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set clear register is used to enable packet receives from the upper 32 isochronous data channels A read from either the set register or clear register returns the content of the isochronous receive channel mask high register See Table 4 12 for a complete description of the register contents 31 so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Isochronous receive channel mask high _ channel petan X X x x x x x x x x x x x x x 15 13 12 10 8 7 5 4 3 2 1 Isochronous receive channel mask high hum peut x X X x x x x x x X x x x X x X Register Isochronous receive channel mask high Type Read Set Clear Offset 70h set register 74h clear register Default XXXX XXXXh Tabl
38. register bits detailed in Table 4 17 31 30 29 28 27 26 25 24 23 22 zi 20 18 17 16 Isochronous receive interrupt mask Isochronous receive interrupt mask Name rR jn n 955 psc pem fo tx Register Isochronous receive interrupt mask Type Read Set Clear Read only Offset A8h set register ACh clear register Default 0000 000Xh 4 22 4 27 Fairness Control Register The fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval See Table 4 18 for a complete description of the register contents 31 so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name fF o Fairness control Defaut 15 14 13 12 10 9 7 6 5 4 2 1 Fairness control pO m es fo Fairness control Type Read only Read Write Offset DCh Default 0000 0000h Table 4 18 Fairness Control Register Description FIELD NAME TYPE DESCRIPTION RSVD Reserved Bits 31 8 return Os when read This field specifies the maximum number of priority arbitration requests for asynchronou
39. safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be are used 5 publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 2000 Texas Instruments Incorporated Contents Section Title Page ice veri rete ta Rara x n CE RR RO Re Ea RO nde deere 1 1 14 1 1 1 2 0 P 1 1 1 3 Related Documents 1 2 1 4 Ordering Information 1 2 2 Terminal Descriptions ou ate tx sects weenie 2 1 3 TSB12LV26 Controller Programming Model 3 1 3 1 PCI Configuration Registers 3 3 3 2 Vendor ID Register abe toa Cane RE YER e et 3 3 3 3 Device ID 3 4 3 4 Command Register
40. 12LV26 related to PCI power management See Table 3 14 for a complete description of the register contents 15 t 13 12 10 8 7 5 4 3 2 1 Power management capabilities RU RU RU RU JR n JR JR JR pea o 1 1 1 fs Register Power management capabilities Type Read Update Read only Offset 46h Default 6401h Table 3 14 Power Management Capabilities Register Description FIELD NAME TYPE DESCRIPTION PCI supportfrom D3cojg When this bit set the TSB12LV26 generates wake event 15 PME D3COLD RU from This bit state is dependent upon the TSB12LV26 Vay x implementation and may be configured by host software using bit 15 PME _D3COLD in the PCI miscellaneous configuration register see Section 3 20 PCI PME support This 4 bit field indicates the power states from which the TSB12LV26 may assert PCI PME This field returns a value of 11006 by default indicating that PME may be asserted S RME SUPPORT M from the D3hot 02 power states Bit 13 may be modified by host software using bit 13 PME SUPPORT D2 inthe PCI miscellaneous configuration register offset FOh see Section 3 20 D2 support This bit can be set or cleared via bit 10 D2 SUPPORT in the PCI miscellaneous configuration register see Section 3 20 The PCI mi
41. 2 10 9 7 6 5 4 2 1 GPIO control mwe Pm pem fo fo Register GPIO control Type Read Write Update ReadWrite Read only Offset FCh Default 0000 0000h Table 3 20 GPIO Control Register Description FIELD NAME TYPE DESCRIPTION When this bit is set a TSB12LV26 general purpose interrupt event occurs on a level change of the 31 INT 3EN R W GPIO3 input This event may generate an interrupt with mask and event status reported through the E OHCI interrupt mask OHCI offset 88h 8Ch see Section 4 22 and interrupt event OHCI offset 80h 84h see Section 4 21 registers RSVD Reserved Bit 30 returns 0 when read GPIO_INV3 GPIO3 polarity invert When this bit is set the polarity of is inverted GPIO_ENB3 2 control When this bit is set the output is enabled Otherwise the output is high 27 25 RSVD Reserved Bits 27 25 return 0 when read GPIO3 data Reads from this bit return the logical value of the input to GPIO3 Writes to this bit update GPIO DATAS the value to drive to GPIO3 when output is enabled When this bit is set a TSB12LV26 general purpose interrupt event occurs on a level change of the 2 INT 2EN GPIO2 input This event may generate an interrupt with mask and event status reported through the OHCI interrupt
42. 23 22 zi 20 18 17 16 Physical request filter low eut fo fo fo o 15 14 13 12 M v0 9 8 7 5 4 2 t 0 Name Physical request filter low Dau 0 o o Register Physical request filter low Type Read Set Clear Offset 1181 register 11Ch clear register Default 0000 0000h Table 4 26 Physical Request Filter Low Register Description FIELD NAME TYPE DESCRIPTION If this bit is set for local bus node number 31 then physical requests received by the TSB12LV26 physReqResource31 from that node are handled through the physical request context If this bit is set for local bus node number 30 then physical requests received by the TSB12LV26 physReqResource30 from that node are handled through the physical request context Bits 29 through 2 follow the same pattern If this bit is set for local bus node number 1 then physical requests received by the TSB12LV26 from that node are handled through the physical request context hysReaR RSC If this bit is set for local bus node number 0 then physical requests received by the TSB12LV26 a ale from that node are handled through the physical request context 4 33 4 36 Physical Upper Bound Register Optional Register The physical upper bound register is an optional register and is n
43. 3 4 EE 3 5 3 6 Class Code and Revision ID Register 3 6 3 7 Latency Timer and Class Cache Line Size Register 3 6 3 8 Header Type and BIST Register 3 7 3 9 OHCI Base Address Register 3 7 3 10 Extension Base Address Register 3 8 3 11 Subsystem Identification Register 3 8 3 12 Power Management Capabilities Pointer Register 3 9 3 13 Interrupt Line and Pin Register 3 9 3 14 MIN and MAX LAT Register 3 10 3 15 OHGI Control Register 3 10 3 16 Capability ID and Next Item Pointer Register 3 11 3 17 Power Management Capabilities Register 3 12 3 18 Power Management Control Status Register 3 13 3 19 Power Management Extension Register 3 13 3 20 Miscellaneous Configuration Register 3 14 3 21 Link Enhancement Control 5 2 15 3 22 Subsystem Access Register 3 16 39 Control ERA nee 3 17 4 1 4 1 Version Register
44. 4 17 4 22 Interrupt Mask Register 4 19 4 23 lsochronous Transmit Interrupt Event Register 4 20 4 24 sochronous Transmit Interrupt Mask Register 4 21 4 25 Receive Interrupt Event Register 4 22 4 26 Receive Interrupt Mask Register 4 22 4 27 Fairness Control Register 4 23 4 28 Link Control Register 4 24 4 29 Node Identification Register 4 25 4 30 PHY Layer Control 5 4 26 431 Isochronous Cycle Timer Register 4 27 4 32 Asynchronous Request Filter High Register 4 28 4 33 Asynchronous Request Filter Low Register 4 30 4 34 Physical Request Filter Register 4 31 4 35 Physical Request Filter Low Register 4 33 4 36 Physical Upper Bound Register Optional Register 4 34 437 Asynchronous Context Control Register 4 35 4 38 Asynchronous Context Command Pointer Register 4 36 4 39 Isochronous Transmit Context Control Register 4 37 4 40 Isochronous Transmit Context Command Pointer Register 4 38 4 41
45. 435 TEXAS INSTRUMENTS TSB12LV26 OHCI Lynx PCI Based IEEE 1394 Host Controller Manual 2000 Bus Solutions 5 INSTRUMENTS Printed in U S A 03 00 SLLS366A TSB12LV26 OHCI Lynx PCI Based IEEE 1394 Host Controller Data Manual Literature Number SLLS366A March 2000 43 Texas 4 INSTRUMENTS uites IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using Tl components In order to minimize risks associated with the customer s applications adequate design and operating
46. Clear PhysicalUpperBound OFFSET 60h 64h 27 27 sj oj Ajlo 555 gt 9Ch A4h gt gt B0 D8h C E0h E4h E8h ECh h FAh FCh 100h 104h 108h 10Ch 110h 114h 118h 11Ch 120h 124h 17Ch Asychronous Request Transmit ATRQ Asychronous Response Transmit ATRS Asychronous Request Receive ARRQ Asychronous Response Receive Isochronous Transmit Context n 0 1 2 3 7 Isochronous Receive Context n n 0 1 2 3 Table 4 1 Register Map Continued REGISTER NAME ABBREVIATION OFFSET ContextControlSet 180h Asynchronous context control ContextControlClear 184h Asynchronous context command pointer CommandPtr 18Ch ContextControlSet Asynchronous context control ContextControlClear 1A4h Asynchronous context command pointer CommandPtr 1ACh ContextControlSet 1COh Asynchronous context control ContextControlClear 1C4h Asynchronous context command pointer CommandPtr 1CCh ContextControlSet 1E0h Asynchronous context control ContextControlClear 1E4h Asynchronous context command pointer CommandPtr 1ECh ContextControlSet 200h 16 n Isochronous transmit context control ContextControlClear 204h 16 n Isoch i transmit context command 20Ch 16 n Cont
47. D ROM register is used to access the serial ROM and is only applicable if bit 24 GUID ROM in the version register offset see Section 4 1 is set See Table 4 3 for a complete description of the register contents 31 so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name 2 GUID ROM R R RU RU RU RU RU RU RU o fo fo fe 15 14 1 12 9 8 7 5 4 2 1 Name 7 4 7 o GUID ROM pes B m l lsjms m m m peau o Register GUID ROM Type Read Set Update Read Update Read only Offset 04h Default 0000h Table 4 3 GUID ROM Register Description FIELD NAME TYPE DESCRIPTION 31 ddrReset RSU Software sets this bit to reset the GUID ROM address to 0 When the TSB12LV26 completes the reset 4 it clears this bit The TSB12LV26 does not automatically fill bits 23 16 rdData with the oth byte 30 26 RSVD Reserved Bits 30 26 return 05 when read rdStart A read of the currently addressed byte is started when this bit is set This bit is automatically cleared when the TSB12LV26 completes the read of the currently addressed GUID ROM byte RSVD Reser
48. DMA context sets its dead bit While this bit is set all normal interrupts for the context s that caused this interrupt are blocked from being set A cycle start was received that had values for cycleSeconds and cycleCount fields that are different 23 cyclelnconsistent RSCU from the values in bits 31 25 cycleSeconds field and bits 24 12 cycleCount field of the isochronous cycle timer register OHCI offset FOh see Section 4 31 A lost cycle is indicated when no cycle_start packet is sent received between two successive cycleSynch events A lost cycle can be predicted when a cycle_start packet does not immediately 22 cycleLost RSCU follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after cycleSynch event without an intervening cycle start This bit may be set either when a lost cycle occurs or when logic predicts that one will occur cycle64Seconds RSCU Indicates that the 71 bit of the cycle second counter has changed Indicates that a new isochronous cycle has started This bit is set when the low order bit of the cycle cycleSynch RSCU count toggles RSCU Indicates that the PHY requests an interrupt through a status transfer RSVD R Reserved Bit 18 returns 0 when read Table 4 14 Interrupt Event Register Description Continued FIELD NAME TYPE DESCRIPTION RSCU Indicates that the PHY chip has entered bus reset mode ifIDcomplete RSCU A packet stream h
49. FIELD NAME TYPE DESCRIPTION 31 16 5810 Subsystem device ID This field indicates the subsystem device ID OHCI_SSVID Subsystem vendor ID This field indicates the subsystem vendor ID 3 12 Power Management Capabilities Pointer Register The power management capabilities pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides The TSB12LV26 configuration header double words at offsets 44h and 48h provide the power management registers This register is read only and returns 44h when read 7 e s 4 s 2 1 Name __ _____ capabilities pointer Power management capabilities pointer R R petam 1 o o t o0 Register Power management capabilities pointer Type Read only Offset 34h Default 44h 3 13 Interrupt Line and Pin Register The interrupt line and pin register is used to communicate interrupt line routing information See Table 3 10 for a complete description of the register contents m O S we R R aR Rw Rw Rw pean fo Register Interrupt line and pin Type Read Write Read only
50. ID and chip ID fields This register initializes to Os on a hardware reset which is an illegal GUID value If a serial ROM is detected then the contents of this register are loaded through the serial ROM interface after a PCI reset At that point the contents of this register cannot be changed If no serial ROM is detected then the contents of this register are loaded by the BIOS after a PCI reset At that point the contents of this register cannot be changed Bt 31 29 28 27 26 25 24 23 22 zi 20 18 17 16 GUID high GUID high HR 0 GUID high Type Read only Offset 24h Default 0000 0000h 4 11 GUID Low Register The GUID low register represents the lower quadlet in a 64 bit global unique ID GUID which maps to chip ID lo in the Bus_Info_Block This register initializes to Os on a hardware reset and behaves identically to the GUID high register OHCI offset 24h see Section 4 10 GUID low Name ee Po GUID low Type Read only Offset 28h Default 0000 0000h 4 10 4 12 Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node See Table 4 8 for a
51. IOS writes all 1s to this register the value read back is FFFF F800h indicating that at least 2K bytes of memory address space are required for the registers See Table 3 8 for a complete description of the register contents gt 9t so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OHCI base address OHCI address we Aw a pem Register OHCI base address Type Read Write Read only Offset 10h Default 0000 0000h Table 3 8 OHCI Base Address Register Description FIELD NAME TYPE DESCRIPTION 31 11 OHCIREG_PTR OHCI register pointer Specifies the upper 21 bits of the 32 bit OHCI base address register SZ OHCI register size This field returns Os when read indicating that the OHCI registers require a 2 Kbyte region of memory OHCI register prefetch This bit returns 0 when read indicating that the OHCI registers are OHCI PF nonprefetchable memory type This field returns 0 when read indicating that the base address register is 32 bits wide and mapping can be done anywhere in the 32 bit memory space OHCI MEM OHCI memory indicator This bit returns 0 when read indicating that the OHCI registers are mapped into system memory space 3 7 3 10 Tl Extension Ba
52. NB is hardwired to 0 PERR ENB Parity error enable When this bit is set the TSB12LV26 is enabled to drive PCI PERR PERR response to parity errors through the PCI PERR PERR signal VGA palette snoop enable The TSB12LV26 does not feature VGA palette snooping This bit returns 0 5 VGA ENB when read Memory write and invalidate enable When this bit is set the TSB12LV26 is enabled to generate MWI 4 MWI ENB R W PCI bus commands If this bit is cleared then the TSB12LV26 generates memory write commands instead Special cycle enable The TSB12LV26 function does not respond to special cycle transactions This bit 3 SPECIAL returns 0 when read MASTER ENB Bus master enable When this bit is set the TSB12LV26 is enabled to initiate cycles on the PCI bus Memory response enable Setting this bit enables the TSB12LV26 to respond to memory cycles on the MEMORY PCI bus This bit must be set to access OHCI registers IO ENB space enable The TSB12LV26 does not implement any I O mapped functionality thus this bit re turns 0 when read 3 4 3 5 Status Register The status register provides status over the TSB12LV26 interface to the PCI bus All bit functions adhere to the definitions in the PCI Local Bus Specification See Table 3 4 for a complete description of the register contents 15 t 19 12 10 9 8 7 6 5 4 3 2 1 Status rcu
53. ON 31 24 BASECLASS Base class This field returns OCh when read which broadly classifies the function as a serial bus controller 23 16 SUBCLASS Subclass This field returns 00h when read which specifically classifies the function as controlling an IEEE 1394 serial bus Programming interface This field returns 10h when read indicating that the programming model is compliant with the 1394 Open Host Controller Interface Specification CHIPREV R Silicon revision This field returns 00h when read indicating the silicon revision of the TSB12LV26 3 7 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the TSB12LV26 See Table 3 6 for a complete description of the register contents m 14 1212 o Register Latency timer and class cache line size Type Read Write Offset OCh Default 0000h Table 3 6 Latency Timer and Class Cache Line Size Register Description FIELD NAME TYPE DESCRIPTION PCI latency timer The value in this register specifies the latency timer for the TSB12LV26 in units of PCI clock cycles When the TSB12LV26 is a PCI bus initiator and asserts FRAME the latency 19 9 EATENEX TIMER
54. PCI bus parking algorithm Initialization device select IDSEL selects the TSB12LV26 during configuration space accesses IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus PCI initiator ready IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the transaction A data phase is completed upon a rising edge of PCLK where both PCI IRDY and PCI TRDY are asserted PCI parity In all PCI bus read and write cycles TSB12LV26 calculates even parity across the AD and C BE buses As an initiator during PCI cycles the TSB12LV26 outputs this parity indicator with a one CLK delay As a target during PCI cycles the calculated parity is compared to the initiator parity indicator a miscompare can result in a parity error assertion PCI PERR PCI parity error indicator This signal is driven by a PCI device to indicate that calculated parity does not match PCI PAR when PERR ENB bit 6 is set in the PCI command register offset O4h see Section 3 4 Power management event This terminal indicates wake events to the host PCI bus request Asserted by the TSB12LV26 to request access to the bus as an initiator The host arbiter asserts the PCI GNT signal when the TSB12LV26 has been granted access to the bus PCI system error When SERR ENB bit 8 in the PCI command register offset 04h see Section 3 4 is set the output is pulsed indicating an address parity error has occu
55. Q 1E0h set register ARRS 1E4h clear register ARRS Default 0000 XOXXh Table 4 27 Asynchronous Context Control Register Description pit FIELDNAME TYPE DESCRIPTION 31 16 16 RSVD RSD R Reserved Bits 31 16 return Os when read RSCU This bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor processing The TSB12LV26 changes this bit only on a hardware or software reset 14 13 RSVD Reserved Bits 14 13 return 0s when read 12 RSU Software sets this bit to cause the TSB12LV26 to continue or resume descriptor processing The TSB12LV26 clears this bit on every descriptor fetch ERN The TSB12LV26 sets this bit when it encounters a fatal error and clears the bit when software resets bit 15 run RU The TSB12LV26 sets this bit to 1 when it is processing descriptors RSVD Reserved Bits 9 8 return Os when read This field indicates the speed at which a packet was received or transmitted and only contains meaningful information for receive contexts This field is encoded as 7 5 spd RU 000 100 Mbits sec 001 200 Mbits sec and 010 400 Mbits sec All other values are reserved 4 0 weniger RU This field holds the acknowledge sent by the link core for this packet or holds an internally generated error code if the packet was not transferred successfully 4 35 4 38 Asynchronous Context Command Po
56. as been received It is generated at the end of the bus initialization process sane This bit is turned off simultaneously when bit 17 busReset is turned on 15 10 RSVD Reserved Bits 15 10 return 0s when read ial 1 lockRespErr RSCU Indicates that the TSB12LV26 sent a lock response for a lock request to a serial bus register but did not receive an ack_complete Indicates that a host bus error occurred while the TSB12LV26 was trying to write a 1394 write request KW RSCU which had already been given an ack complete into system memory Isochronous receive DMA interrupt Indicates that one or more isochronous receive contexts have generated an interrupt This is not a latched event it is the logical OR of all bits in the isochronous 7 isochRx RU receive interrupt event OHCI offset AOh A4h see Section 4 25 and isochronous receive interrupt mask OHCI offset ABh ACh see Section 4 26 registers The isochronous receive interrupt event register indicates which contexts have interrupted Isochronous transmit DMA interrupt Indicates that one or more isochronous transmit contexts have generated an interrupt This is not a latched event it is the logical OR of all bits in the isochronous isochTx RU transmit interrupt event OHCI offset 90h 94h see Section 4 23 and isochronous transmit interrupt mask OHCI offset 98h 9Ch see Section 4 24 registers The isochronous transmit interrupt event register indicates which contexts
57. ating at PCI clock rates up to 33 MHz 1 2 Features The TSB12LV26 supports the following features 3 3 V core logic with universal PCI interfaces compatible with 3 3 V and 5 V PCI signaling environments e Serial bus data rates of 100 200 and 400 Mbits s Provides bus hold buffers on physical interface for low cost single capacitor isolation e Physical write posting of up to three outstanding transactions e Serial ROM interface supports 2 wire devices e External cycle timer control for customized synchronization e Implements PCI burst transfers and deep FIFOs to tolerate large host latency e Provides two general purpose I Os e Fabricated in advanced low power CMOS process e Packaged in 100 terminal LQFP PZ e Supports PCI CLKRUN protocol 1 3 Related Documents 1394 Open Host Controller Interface Specification 1 0 e P1394 Standard for a High Performance Serial Bus IEEE 1394 1995 1394 Draft Standard for a High Performance Serial Bus Supplement e PC 99 Design Guide e PCI Bus Power Management Interface Specification Revision 1 0 e PCI Local Bus Specification Revision 2 2 Serial Bus Protocol 2 SBP 2 1 4 Ordering Information TSB12LV26 OHCI Lynx PCI Based IEEE 1394 Host Controller 3 3V 5V Tolerant I Os 100 Terminal LQFP 2 Terminal Descriptions This section provides the terminal descriptions for the TSB12LV26 Figure 2 1 shows the signal assigned to each terminal in the package Table 2 1 is a listing
58. bit speeds is required When connected to the TSB41LVOX terminal a 1 kQ series resistor is required between the link and PHY Link power status The PHY LPS signal is asserted when the link is powered on and 3 3 V signaling is required Link request This signal is driven by the TSB12LV26 to initiate a request for the PHY to perform some service System clock This input from the PHY provides a 49 152 MHz clock signal for data synchronization Table 2 8 Miscellaneous Terminals TERMINAL CYCLEOUT 77 This terminal provides an 8 kHz cycle timer synchronization signal 3 The CYCLEIN terminal allows an external 8 kHz clock to be used as a cycle timer for synchronization with other CYCLEIN System devices GPIO2 GPIO3 REG_EN REG18 NI 5 LinkOn wake indication PHY_LINKON signal is pulsed by the PHY to activate the link and 3 3 V signaling If this terminal is not implemented then it should be pulled high to the link through a 4 7 resistor General purpose I O 2 This terminal defaults as an input and if it is not implemented then it is recommended that it be pulled low to ground with a 220 Q resistor General purpose I O 3 This terminal defaults as an input and if it is not implemented then it is recommended that it be pulled low to ground with a 220 Q resistor Regulator enable This terminal is pulled low to ground th
59. contents m mm T pear x x x x DX DX DX X EX EX EX EX LX LX m fos 17 11 mm T T eir x EX LX EX TX TX TX Register Isochronous cycle timer Type Read Write Update Offset FOh Default XXXX XXXXh Table 4 22 Isochronous Cycle Timer Register Description FIELD NAME TYPE DESCRIPTION 31 1 0 cycleSeconds RWU This field counts seconds rollovers from bits 24 12 cycleCount field modulo 128 24 12 cycleCount This field counts cycles rollovers from bits 11 0 cycleOffset field modulo 8000 1 leOffset RWU This field counts 24 576 MHz clocks modulo 3072 i e 125 us If an external 8 2 clock configuration is being used then this bit must cleared to 0 at each tick of the external clock 4 27 4 32 Asynchronous Request Filter High Register The asynchronous request filter high set clear register is used to enable asynchronous receive requests on a per node basis and handles the upper node IDs When a packet is destined for either the physical request context or the ARRQ context the source node 10 is examined If the bit corresponding to the node ID is not set in this register then the packet is not acknowledged and the request is not queued The node ID comparison is done if the so
60. e 4 12 Isochronous Receive Channel Mask High Register Description ASC When this bitis set TSB12LV26 is enabled to receive rom iso ieChameuo RSC When tis bitis set te TSB12LV28 is enabled to recive rom iso channel number ao Table 4 12 Isochronous Receive Channel Mask High Register Description Continued RSC When this bitis set the enabled to receive iso channel numbers 1 ioannes RSG_ When this bit is so the TSBT2LV26 is enabled to recive rom iso channel numbers 4 20 Isochronous Receive Channel Mask Low Register The isochronous receive channel mask low set clear register is used to enable packet receives from the lower 32 isochronous data channels See Table 4 13 for a complete description of the register contents s so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name its ochronous receive channel masklow petan x x x x x x x x x x x x x x x x 15 t 13 12 10 9 8 7 5 4 3 2 1 0 Name its ochronous receive channel masklow pea x x x x x Tx x Tx Tx Px Tx Tx Px Tx Tx Tx Register Isochronous receive channel mask low Type Read Set Clear Offset 78h set register 7Ch clear register Default XXXX XXXXh Table 4 13 Isochronous Receive Channel Mask Low Register Descriptio
61. e RSC other nodes from sending transactions before the local system is ready When this bit is cleared the TSB12LV26 is logically and immediately disconnected from the 1394 bus no packets are received or processed nor are packets transmitted When this bit is set all TSB12LV26 states are reset all FIFOs are flushed and all OHCI registers 16 SoftReset RSCU are set to their hardware reset values unless otherwise specified PCl registers are not affected by this bit This bit remains set while the soft reset is in progress and reverts back to 0 when the reset has completed RSVD Reserved Bits 15 0 return Os when read 4 17 Self ID Buffer Pointer Register The self ID buffer pointer register points to the 2 Kbyte aligned base address of the buffer in host memory where the self ID packets are stored during bus initialization Bits 31 11 are read write accessible Reserved bits 10 0 are read only and return Os when read Bt 31 29 28 27 26 25 24 23 22 zi 20 18 17 16 ead X x x x x X x x X PX IX X DX x x 15 14 1 12 9 7 e 5 a ja 2 1 Self ID buffer pointer n n Pm pea x x x Register Self ID buffer pointer Type Read Write Read only O
62. e that wake up from D2 is not supported 12 11 RSVD Reserved Bits 12 11 return Os when read D2 support This bit is used to program bit 10 02 SUPPORT in the power management capabilities register offset 46h see Section 3 17 If the D2 power state implemented in the 10 cea iii TSB12LV26 is not desired then this bit may be cleared to indicate to power management software that D2 is not supported RSVD Reserved Bits 9 5 return Os when read This bit defaults to 0 which provides OHCI Lynx compatible target abort signaling When this bit is set to 1 it enables the no target abort mode in which the TSB12LV26 returns indeterminate data instead of signaling target abort DIS TGT ABT R W The link is divided into the PCI_CLK and SCLK domains If software tries to access registers in the link that are not active because the SCLK is disabled a target abort is issued by the link On some systems this can cause a problem resulting in a fatal system error Enabling this bit allows the link to respond to these types of requests by returning FFh It is recommended that this bit be set to 1 3 GP2IIC When this bit is set 1 the GPIO3 and GPIO2 signals are internally routed to the SCL and SDA respectively The GPIO3 and GPIO2 terminals are also placed in a high impedance state When this bit is set to 1 the internal SCLK runs identically with the chip input This bit is a test DISABLE SCEKGATE feature only and sho
63. eaves the corresponding bit unaffected A 1 bit written to RegisterClear causes the corresponding bit in the set clear register to be cleared while a 0 bit leaves the corresponding bit in the set clear register unaffected Typically a read from either RegisterSet or RegisterClear returns the contents of the set or clear register respectively However sometimes reading the RegisterClear provides a masked version of the set or clear register The interrupt event register is an example of this behavior Table 4 1 OHCI Register Map Reserved 58 56 4 1 Table 4 1 OHCI Register Map Continued DMA CONTEXT REGISTER NAME Link control Asynchronous request filter high Asynchronous request filter low Physical request filter high Physical request filter low Physical upper bound ABBREVIATION SelflDBuffer SelflDCount IRChannelMaskHiSet IRChannelMaskHiClear IRChannelMaskLoSet IRChannelMaskLoClear IntEventSet IntEventClear IntMaskSet IntMaskClear IsoXmitlntEventSet IsoXmitlntEventClear IsoXmitlntMaskSet IsoXmitlntMaskClear IsoRecvIntEventSet IsoRecvIntEventClear IsoRecvintMaskSet IsoRecvintMaskClear FairnessControl LinkControlSet LinkControlClear NodelD PhyControl Isocyctimer AsyncRequestFilterHiSet AsyncRequestFilterHiClear AsyncRequestFilterLoSet AsyncRequestFilterloClear PhysicalRequestFilterHiSet PhysicalRequestFilterHiClear PhysicalRequestFilterLoSet PhysicalRequestFilterlo
64. ed UIS ERR ENS EN a 4 29 4 33 Asynchronous Request Filter Low Register The asynchronous requestfilter low set clear register is used to enable asynchronous receive requests on a per node basis and handles the lower node IDs Other than filtering different node IDs this register behaves identically to the asynchronous request filter high register See Table 4 24 for a complete description of the register contents 9t so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Asynchronous request filter low m o 15 t 13 10 9 8 5 4 2 1 Asynchronous request filter low peau o o Register Asynchronous request filter low Type Read Set Clear Offset 10881 set register 10Ch clear register Default 0000 0000h Table 4 24 Asynchronous Request Filter Low Register Description FIELD NAME TYPE DESCRIPTION If this bit is set for local bus node number 31 then asynchronous requests received by the asynReqResources1 TSB12LV26 from that node are accepted nReaR 0 If this bit is set for local bus node number 30 then asynchronous requests received by the TSB12LV26 from that node accepted ert Bits 29 through 2 follow the sa
65. erface consists of two GPIO ports GPIO2 and GPIO3 power up as general purpose inputs and are programmable via the GPIO control register Figure 5 1 shows the logic diagram for GPIO2 and GPIOS implementation GPIO Read Data lt GPIO Write Data lt Port V GPIO_Invert GPIO Enable Figure 5 1 GPIO2 and GPIO3 Logic Diagram 5 2 6 Serial ROM Interface The TSB12LV26 provides a serial bus interface to initialize the 1394 global unique ID register and a few PCI configuration registers through a serial ROM The TSB12LV26 communicates with the serial ROM via the 2 wire serial interface After power up the serial interface initializes the locations listed in Table 6 1 While the TSB12LV26 is accessing the serial ROM all incoming PCI slave accesses are terminated with retry status Table 6 2 shows the serial ROM memory map required for initializing the TSB12LV26 registers Table 6 1 Registers and Bits Loadable through Serial ROM BITS LOADED 00h PCI register 3Eh 15 0 PCI register 208 15 0 PCI register 2 15 0 05h bit 6 OHCI register 50h 23 05h PCI register F4h 7 2 1 register 40h POlOHClregster CE _ ____ 6 1 Table 6 2 Serial ROM BYTE ADDRESS BYTE DESCRIPTION PCI maximum latency PCI minimum grant Oh PCI vendor ID PCI vendor ID msbyte PCI subsystem ID Isbyte PCI subsystem ID 7 6 5 4 3 2 1 Link
66. esent If a serial ROM is present then this field is loaded from the serial ROM 4 8 Bus Identification Register The bus identification register externally maps to the first quadlet in the Bus Info Block and contains the constant 3133 3934h which is the ASCII value of 1394 31 3o 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name ooo 1 t fs 15 14 13 12 f v0 9 s 4 2 t Name we IR o t 1 o o o Register Bus identification Type Read only Offset 1Ch Default 3133 3934h 4 8 4 9 Options Register The bus options register externally maps to the second quadlet of the Bus Info Block See Table 4 7 a complete description of the register contents 31 so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bus options Hype Rw Rw Aw Rw Aw R R B RW Raw RA 5 Dx 15 t4 1 12 n 10 9 8 7 5 4 2 1 Bus options oo o Busoptions
67. extControlSet 400h 32 n Isochronous receive context control ContextControlClear 404h 32 n Isoch i receive context command 40Ch 32 Context match ContextMatch 410h 32 n 41 OHCI Version Register This register indicates the OHCI version support and whether or not the serial ROM is present See Table 4 2 for a complete description of the register contents 9t so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name OHCI version OHCI version Name LEEREN OHCI version Type Read only Offset 00h Default 0X01 0000h Table 4 2 Version Register Description FIELD NAME TYPE DESCRIPTION 31 25 RSVD Reserved Bits 31 25 return Os when read 24 GUID ROM The TSB12LV26 sets this bit if the serial ROM is detected If the serial ROM is present then the Bus Info Block is automatically loaded on hardware reset 23 16 Major version of the 1 The TSB12LV26 is compliant with the 1394 Open Host Controller Interface i versio Specification thus this field reads 01h RSVD Reserved Bits 15 8 return Os when read 70 r vision Minor version of the OHCI The TSB12LV26 is compliant with the 1394 Open Host Controller Interface Specification thus this field reads 4 2 GUID ROM Register The GUI
68. ffset 64h Default XXXX XX00h 4 18 Self ID Count Register The self ID count register keeps a count of the number of times the bus self ID process has occurred flags self ID packet errors and keeps a count of the self ID data in the self ID buffer See Table 4 11 for a complete description of the register contents m 2 5 Name _ Cd RUT ATA A RU AU e x 7 2 11 Self ID count R R R R R RU RU RU RU R Defaut fo Register Self ID count Type Read Update Read only Offset 68h Default 0000h Table 4 11 Self ID Count Register Description FIELD NAME TYPE DESCRIPTION When this bit is 1 an error was detected during the most recent self ID packet reception The con 31 selflIDError RU tents of the self ID buffer are undefined This bit is cleared after a self ID reception in which no errors are detected Note that an error can be a hardware error or a host bus write error 30 24 RSVD Reserved Bits 30 24 return 05 when read 23 16 selflDGeneration PEE field increments each time a bus reset
69. for a complete description of the register contents s so 29 28 27 26 25 24 23 22 21 20 19 18 17 Miscellaneous configuration R in n n in in __ 15 t 13 12 10 9 8 7 5 4 2 1 Miscellaneous configuration Po Miscellaneous configuration ________ Rw n A R Rw Rw pem fs Register Miscellaneous configuration Type Read Write Read only Offset FOh Default 0000 2400h Table 3 17 Miscellaneous Configuration Register FIELD NAME TYPE DESCRIPTION 31 16 RSVD Reserved Bits 31 16 return Os when read PME support from This bit is used to program bit 15 PME D3COLD in the power PME DSCOLD iiid management capabilities register offset 46h see Section 3 17 RSVD Reserved Bit 14 returns 0 when read PCI PME support This bit is used to program bit 13 PME SUPPORT D2 in the power management capabilities register offset 46h see Section 3 17 If wake from the D2 power state 15 FUN implemented in the TSB12LV26 is not desired then this bit may be cleared to indicate to power management softwar
70. have interrupted 5 RSPkt RSCU Indicates that a packet was sent to an asynchronous receive response context buffer and the descriptor xferStatus and resCount fields have been updated 4 ROPkt RSCU Indicates that a packet was sent to an asynchronous receive request context buffer and the descriptor xferStatus and resCount fields have been updated 3 ARRS RSCU Async receive response DMA interrupt This bit is conditionally set upon completion of an ARRS DMA context command descriptor Async receive request DMA interrupt This bit is conditionally set upon completion of an ARRQ DMA ARRQ RSCU context command descriptor Asynchronous response transmit DMA interrupt This bit is conditionally set upon completion of an respTxComplete RSCU ATRS DMA command Asynchronous request transmit DMA interrupt This bit is conditionally set upon completion of an reqTxComplete RSCU in DMA ae P 4 18 4 22 Interrupt Mask Register The interrupt mask set clear register is used to enable the various TSB12LV26 interrupt sources Reads from either the set register or the clear register always return the contents of the interrupt mask register In all cases except masterlIntEnable bit 31 and VendorSpecific bit 30 the enables for each interrupt event align with the interrupt event register bits detailed in Table 4 14 See Table 4 15 for a description of bits 31 and 30 This register is fully compliant with OHCI and the TSB12LV26 adds an OHCI 1 0 compliant i
71. he Texas Instruments TSB12LV26 is a PCI to 1394 host controller compatible with the latest PC Local PCI Bus Power Management Interface IEEE 1394 1995 and 1394 Open Host Controller Interface Specification The chip provides the IEEE 1394 link function and is compatible with serial bus data rates of 100 Mbits s 200 Mbits s and 400 Mbits s As required by the 1394 Open Host Controller Interface Specification OHCI and IEEE proposal 1394a specification internal control registers are memory mapped and nonprefetchable The PCI configuration header is accessed through configuration cycles specified by PCI and provides Plug and Play PnP compatibility Furthermore the TSB12LV26 is compliant with the PC Bus Power Management Interface Specification per the PC 99 Design Guide requirements TSB12LV26 supports the DO D2 and D3 power states The TSB12LV26 design provides PCI bus master bursting and is capable of transferring a cacheline of data at 132 Mbytes s after connection to the memory controller Since PCI latency can be large deep FIFOs are provided to buffer 1394 data The TSB12LV26 provides physical write posting buffers and a highly tuned physical data path for SBP 2 performance The TSB12LV26 also provides multiple isochronous contexts multiple cacheline burst transfers advanced internal arbitration and bus holding buffers on the interface An advanced CMOS process is used to achieve low power consumption while oper
72. hen multiple 1394 compatible buses are connected via a bridge This number is the physical node number established by the PHY during self ID It is automatically set 5 0 NedeNunber RU to the value received from the PHY after the self ID phase If the PHY sets the NodeNumber to 63 then software should not set the run bit bit 15 of the asynchronous context control register see Section 4 37 for either of the AT DMA contexts 4 25 4 30 PHY Layer Control Register The PHY layer control register is used to read or write a PHY register See Table 4 21 for a complete description of the register contents 9t so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PHY layer control RU R R R RU RU RU RU RU RU RU RU RU RU RU RU fau fo fo o 15 14 13 12 tw v0 9 j e s 4 2 Name _________________ RWU RWU RW RW RW RW RW RW RW RW Deian o o o fo fo fo J o fo o jo J o fo jJ o o Register PHY layer control Type Read Write Update Read Write Read Update Read only Offset ECh Default 0000 0000h Table 4 21 PHY Control Register Description FIELD NAME TYPE DESCRIPTION 81 This bit is cleared to 0 by the TSB12LV26 when either bit 15 rdReg or bit 14 wrReg is set This
73. ing The TSB12LV26 changes this bit only on a hardware or software reset The TSB12LV26 sets this bit when it encounters a fatal error and clears the bit when software resets bit 15 run The TSB12LV26 sets this bit to 1 when it is processing descriptors Reserved Bits 9 8 return 05 when read This field is not meaningful for isochronous transmit contexts Following OUTPUT LAST command the error code is indicated in this field Possible values are ack complete evt descriptor read evt data read and evt unknown 2 c RU RU event code R 4 37 4 40 Isochronous Transmit Context Command Pointer Register The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the TSB12LV26 accesses when software enables an isochronous transmit context by setting the isochronous transmit context control register see Section 4 39 bit 15 run The n value in the following register addresses indicates the context number n 0 1 2 3 7 31 so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Isochronous transmit context command pointer _ fsochronoustensmicontextcommandpointer Des omm e Beam x x x x x x x x x x x 15 19 12 10 9 8 7 e S 4 3 2 1 0 Isochronous transmit context command pointer
74. inter Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the TSB12LV26 accesses when software enables the context by setting the asynchronous context control register see Section 4 37 bit 15 run See Table 4 28 for a complete description of the register contents 9t so 28 27 26 25 24 23 22 21 20 19 18 17 16 Asynchronous context command pointer 0 Asynchronous context commandpointer Bea x x x x x x x x x ix x xix x x 15 t 13 10 9 8 7 5 4 2 1 0 Asynchronous context command pointer Po Asynchronous context command pointer pea x x x x Tx Tx Tx Px tx Px tx Px Tx Tx x Register Asynchronous context command pointer Type Read Write Update Offset 18Ch ATRQ 1ACh ATRS 1CCh_ ArRQ 1ECh 5 Default XXXX XXXXh Table 4 28 Asynchronous Context Command Pointer Register Description FIELD NAME TYPE DESCRIPTION descriptorAddress RWU Contains the upper 28 bits of the address of a 16 byte aligned descriptor block 3 0 Z RWU Indicates the number of contiguous descriptors at the address pointed to by the descriptor address If Z is 0 then it indicates that the descriptorAddress field bits 31 4 is not valid 4 36 4 39 Isochronous Transmit Context Control Register The isochronous transmit co
75. iption 3 13 Miscellaneous Configuration Register 3 14 Link Enhancement Control Register Description 3 15 Subsystem Access Register Description 3 16 GPIO Control Register Description 3 17 Register 225 5555 RR ERR RES 4 1 Version Register Description 4 4 GUID ROM Register Description 4 5 Asynchronous Transmit Retries Register Description 4 6 CSR Control Register Description 4 7 Configuration ROM Header Register Description 4 8 Bus Options Register Description 4 9 Configuration ROM Mapping Register Description 4 11 Posted Write Address High Register Description 4 12 vii viii 4 10 4 11 4 12 4 13 4 14 4 15 4 16 4 17 4 18 4 19 4 20 4 21 4 22 4 23 4 24 4 25 4 26 4 27 4 28 4 29 4 30 4 31 6 1 6 2 Host Controller Control Register Description 4 13 Self ID Count Register Description 4 14 Isochronous Receive Channel Mask High Register Description 4 15 Isochronous Receive Channel Mask Low Register Description 4 16 Interrupt Event Register Description
76. llaneous pins are GPIO2 GPIO3 SDA SCL CYCLEOUT 8 Applies for external output buffers AR E E V 0 0 V 0 lt o 0 475 0 325 ce ns ojo 1 The junction temperatures reflect simulation conditions Customer is responsible for verifying junction temperature 7 2 7 3 Electrical Characteristics Over Recommended Operating Conditions unless otherwise noted TEST Cl High level output voltage 4 PHY interface 8 Vcc 0 6 SS O VoLT Low level output voltage OL 9 PHY interface Miscellaneous loz 3 state output high impedance Output pins Low level input current pinst GND 20 nmm viz 20 High level input current Otherst t For I O pins input leakage and includes loz of the disabled output Miscellaneous pins are GPIO2 GPIO3 SDA SCL CYCLEOUT 7 4 Switching Characteristics for PCI Interface PARAMETER MEASURED MIN MAX UNIT tsu _ Setup time before PCLK 50 to 50 th Hold time before PCLK 50 0 50 0 tq Delay time PHY_CLK to data valid 50 to 50 These parameters are ensured by design 7 5 Switching Characteristics for PHY Link Interface PARAMETER MEASURED MIN
77. mask OHCI offset 88h 8Ch see Section 4 22 and interrupt event OHCI offset 80h 84h see Section 4 21 registers 3 R W 2 RSVD Reserved Bit 22 returns 0 when read 1 R W GPIO INV2 GPIO2 polarity invert When this bit is set the polarity of GPIO2 is inverted ENB2 control When this bit is set the output is enabled Otherwise the output is high R Reserved Bits 19 17 return Os when read RWU GPIO2 data Reads from this bit return the logical value of the input to GPIO2 Writes to this bit update the value to drive to GPIO2 when the output is enabled R Reserved Bits 15 0 return Os when read 4 OHCI Registers The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory mapped into a 2 Kbyte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space see Section 3 9 These registers are the primary interface for controlling the TSB12LV26 IEEE 1394 link function This section provides the register interface and bit descriptions There are several set clear register pairs in this programming model which are implemented to solve various issues with typical read modify write control registers There are two addresses for set clear register RegisterSet and RegisterClear Refer to Table 4 1 for an illustration A 1 bit written to RegisterSet causes the corresponding bit in the set clear register to be set while a 0 bit l
78. me pattern 1 RSC If this bit is set for local bus node number 1 then asynchronous requests received by the y 9 TSB12LV26 from node are accepted nReaR RSC If this bit is set for local bus node number 0 then asynchronous requests received by the i a SOME TSB12LV26 from that node are accepted 4 30 4 34 Physical Request Filter High Register The physical request filter high set clear register is used to enable physical receive requests on a per node basis and handles the upper node IDs When a packet is destined for the physical request context and the node ID has been compared against the ARRQ registers then the comparison is done again with this register If the bit corresponding to the node ID is not set in this register then the request is handled by the ARRQ context instead of the physical request context The node ID comparison is done if the source node is on the same bus as the TSB42AD2 Nonlocal bus sourced packets are not acknowledged unless bit 31 in this register is set See Table 4 25 for a complete description of the register contents 29 28 27 26 25 24 23 22 zi 20 18 17 16 Physical request filter high o os 7
79. mp current Vj lt 0 or Vj gt see Note 1 20 mA Output clamp current lox lt 0 or gt Vcc see Note 2 20 mA Storage temperature range 65 to 150 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTES 1 Applies to external input and bidirectional buffers Vj gt 2 Applies to external output and bidirectional buffers gt 7 2 Recommended Operating Conditions Voc Core voltage Commercial 3 3 V 3 3 V PCI I O clamping voltage Commercial PCI 3 3V High level input voltage a 3 PHY interface Miscellaneoust PCI Low level input voltage PHY interface Miscellaneoust PCI PHY interface 2 lt Input voltage Miscellaneoust PHY interface lt Output voltage Miscellaneoust tt Input transition time tr and tf Operating ambient temperature Tf Virtual junction temperature t Applies for external inputs and bidirectional buffers without hysteresis t Misce
80. mpliant with the PC Local Bus Specification as a standard header Table 3 2 illustrates the PCI configuration header that includes both the predefined portion of the configuration space and the user definable registers Table 3 2 PCI Configuration Register Map REGISTER NAME OFFSET OHCI registers base address TI extension registers base address Reserved Reserved Reserved Reserved Reserved Subsystem ID Subsystem vendor ID PCI power Reserved management 34h capabilities pointer Reserved 38h PCI OHCI control register Power management capabilities PM data Power management CSR 48h Reserved PCI miscellaneous configuration register Link Enhancements register Subsystem ID alias Subsystem vendor ID alias GPIO3 GPIO2 3 2 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device The vendor ID assigned to Texas Instruments is 104Ch 15 t 13 12 10 9 7 5 4 3 2 1 Vendor ID Nendo in Pm pem f fo Register Vendor ID Type Read only Offset 00h Default 104Ch 3 3 3 3 Device ID Register The device ID register contains a value assigned to the TSB12LV26 by Texas Instruments The device identification for the TSB12LV26 is 8020h 15 t 13
81. n 2tolowthesamepatern isoChannelt RSC When this bit is set the TSB12LV26 is enabled to receive from iso channel number 1 isoChannelO When this bit is set the TSB12LV26 is enabled to receive from iso channel number 0 4 16 4 21 Interrupt Event Register The interrupt event set clear register reflects the state of the various TSB12LV26 interrupt sources The interrupt bits are set by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register This register is fully compliant with OHCI and the TSB12LV26 adds an OHCI 1 0 compliant vendor specific interrupt function to bit 30 When reading the interrupt event register the return value is the bit wise AND function of the interrupt event and interrupt mask registers per the 1394 Open Host Controller Interface Specification See Table 4 14 for a complete description of the register contents m Ts 2 2 16 wm Jasc J A ascu nscu ascu nscu e x o 9 X X X X X X X X x as uu ps 7 155 14 1 2 22 2 T A A 5 59co nsco nu AU nscu nscu
82. n BIT FIELDNAME TYPE DESCRIPTION 31 14 RSVD Reserved Bits 31 14 return Os when read This field sets the initial AT threshold value which is used until the AT FIFO is underrun When the 13 12 atx thresh TSB12LV26 retries the packet it uses 2 Kbyte threshold resulting in a store and forward operation RSVD 00 Threshold 2K bytes resulting in a store and forward operation 01 Threshold 1 7K bytes default 10 Threshold 1K bytes 11 Threshold 512 bytes These bits fine tune the asynchronous transmit threshold For most applications the 1 7K threshold is optimal Changing this value may increase or decrease the 1394 latency depending on the average PCI bus latency Setting the AT threshold to 1 7K 1K or 512 bytes results in data being transmitted at these thresholds or when an entire packet has been checked into the FIFO If the packet to be transmitted is larger than the AT threshold then the remaning data must be received before the AT FIFO is emptied otherwise an underrun condition will occur resulting in a packet error at the receiving node As a result the link will then commence store and forward operation i e wait until it has the complete packet in the FIFO before retransmitting it on the second attempt to ensure delivery An AT threshold of 2K results in store and forward operation which means that asynchronous data will not be transmitted until an end of packet token is received Restated setti
83. nce with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using Tl components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be are used 5 publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 2000 Texas Instruments Incorporated
84. ng the AT threshold to 2K results in only complete packets being transmitted Reserved Bits 11 8 return Os when read Enable asynchronous priority requests OHCI Lynx compatible Setting this bit to 1 enables the link to respond to requests with priority arbitration It is recommended that this bit be set to 1 This bit is not assigned in the TSB12LV26 follow on products since this bit location loaded by the serial ROM from the enhancements field corresponds to bit 23 programPhyEnable in the host controller control register OHCI offset 50h 54h see Section 4 16 Reserved Bits 5 3 return Os when read Enable insert idle OHCI Lynx compatible When the PHY has control of the Ct 0 1 control lines and D 0 8 data lines and the link requests control the PHY drives 11b on the Ct 0 1 lines The link can then start driving these lines immediately Setting this bit to 1 inserts an idle state so the link waits one clock cycle before it starts driving the lines turnaround time It is recommended that this bit be set to 1 Table 3 18 Link Enhancement Control Register Description Continued FIELD NAME TYPE DESCRIPTION Enable acceleration enhancements OHCI Lynx compatible When set to 1 this bit notifies the PHY 1 enab_accel R W that the link supports the 1394a acceleration enhancements i e ack accelerated fly by concatenation etc It is recommended that this bit be set to 1 o jResevedBiOretumsOwhenread
85. nterrupt function to bit 30 m m T nsu ASC rcu nscu ascu nscu scu ascu RSGU nscu x x o o X X LX LX Lx Lx Lx 5 17 15 15 15 12 12 12 me T n A AU nscu nscu nscu nscu 8560 pem o o o x LX LX LX Lx LX LX LX Register Interrupt mask Type Read Set Clear Update Read Set Clear Read Update Read only Offset 88h set register 8Ch clear register Default XXXX OXXXh Table 4 15 Interrupt Mask Register Description FIELD NAME TYPE DESCRIPTION Master interrupt enable If this bit is set then external interrupts are generated in accordance with the 31 masterIntEnable interrupt mask register If this bitis cleared then external interrupts are not generated regardless of the interrupt mask register settings 3 vandorSn citic RSC When this bit is set this vendor specific interrupt mask enables interrupt generation when bit 30 p vendorSpecific of the interrupt event register OHCI offset 80h 84h see Section 4 21 is set See Table 4 14 4 23 Isochronous Transmit Interrupt Event Register The isochronous transmit interrupt event set clear register reflects the interrupt state of the isochronous transmit contexts An interrupt is generated on behalf of an i
86. ntext control set clear register controls options state and status for the isochronous transmit DMA contexts n value in the following register addresses indicates the context number n 0 1 2 3 7 See Table 4 29 for a complete description of the register contents Isochronous transmit context control eut x x X X X X X x 31 3o 29 28 27 26 25 24 23 22 2t 20 t9 18 17 16 Name 7277 lsochronous transmit context control 15 14 1 12 8 7 j e 5 j 3 2 1 Isochronous transmit context control _____________________ transmit context control Asc R rsu RU R RU RU RU RU RU RU RU o x fo 1 tx tx tx Tx Register Isochronous transmit context control Type Read Set Clear Update Read Set Clear Read Update Read only Offset 200h 16 n gt set register 2041 16 n clear register Default XXXX XOXXh Table 4 29 Isochronous Transmit Context Control Register Description FIELD NAME TYPE DESCRIPTION When this bit is set to 1 processing occurs such that the packet described by the context first 31 cycleMatchEnable descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field Contains a 15 bit value corresponding to the low order tw
87. o bits of the bus isochronous cycle timer register OHCI offset FOh see Section 4 31 cycleSeconds field bits 31 25 and the cycleCount field 30 16 RSC bits 24 12 If bit 31 cycleMatchEnable is set then this isochronous transmit DMA context becomes enabled for transmits when the low order two bits of the bus isochronous cycle timer register cycleSeconds field bits 31 25 and the cycleCount field bits 24 12 value equal this field cycleMatch value bits 30 16 The cycleMatch field bits 30 16 must match the low order two bits of cycleSeconds and the 13 bit cycleCount field in the cycle start packet that is sent or received immediately before isochronous transmission begins Since the isochronous transmit DMA controller may work ahead the processing of the first descriptor block may begin slightly in advance of the actual cycle in which the first packet is transmitted The effects of this bit however are impacted by the values of other bits in this register and are explained in the 1394 Open Host Controller Interface Specification Once the context has become active hardware clears this bit RSC SU Reserved Bits 14 13 return 05 when read Software sets this bit to cause the TSB12LV26 to continue or resume descriptor processing The TSB12LV26 clears this bit on every descriptor fetch This bit is set by software to enable descriptor processing for the context and cleared by software to stop descriptor process
88. ochronous Transmit Interrupt Event Register Description ex channel caused fe interrupt event reseter socht 4 20 4 24 Isochronous Transmit Interrupt Mask Register The isochronous transmit interrupt mask set clear register is used to enable the isochTx interrupt source on a per channel basis Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register In all cases the enables for each interrupt event align with the event register bits detailed in Table 4 16 st 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 777 dsohrnoustansmtinemuptmask __________ Isochronous transmit interrupt mask Register Isochronous transmit interrupt mask Type Read Set Clear Read only Offset 98h set register 9Ch clear register Default 0000 00XXh 4 21 4 25 Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set clear register reflects the interrupt state of the isochronous receive contexts An interrupt is generated on behalf of an isochronous receive context if an INPUT_ command completes and its interrupt bits are set Upon determining that the interrupt event register OHCI offset 80h 84h see Section 4 21 isochRx bit 7 interrupt has occurred software can check this register to determine which context s caused the
89. of signal names arranged in terminal number order and Table 2 2 lists terminals in alohanumeric order by signal names PZ PACKAGE TOP VIEW 98 LINKON 97 D 94 11 GND 92 1 PHY_CTL1 91 3 3 89 DATA1 O DATA2 87 L1 83 GND 99 PHY LPS 96 1 3 3 Vec 95 1 PHY SCLK 93 2 PHY 901 PHY DATAO 861 PHY 85 7 PHY 4 8415 PHY DATA5 82 O PHY DATA6 81 0 PHY_DATA7 3 3 Voc 79 REG EN 78 CYCLEIN 100 REG18 GND GPIO2 GPIO3 SCL SDA PCI CLKRUN PCI INTA 3 3 Voc G RST GND PCI CLK 3 3 PCI GNT PCI REQ PCI PME PCI AD31 PCI AD30 3 3 PCI AD29 PCI AD28 PCI AD27 GND PCI AD26 77 CYCLEOUT 76 PCI GND PCI ADO AD1 PCI AD2 PCI AD3 3 3 Voc PCI AD4 PCI AD5 PCI AD6 PCI AD7 PCI C BEO PCI AD8 VccP PCI AD9 PCI AD10 GND 011 PCI AD12 PCI AD13 PCI AD14 33 Voc PCI AD15 PCI PCI PAR PCI SERR GND PCI AD23 PCI AD22 PCI 21 PCI AD20 3 3 Voc PCI AD19 PCI AD16 PCI C BE2 REG18 PCI FRAME PCI IDSEL PCI AD18 PCI AD17 PCI IRDY PCI TRDY PCI AD25 PCI AD24 PCI Figure 2 1 Terminal Assignments PERR GND PCI STOP PCI DEVSEL 2 1 Table 2 1 Signals Sorted by Terminal Number TERMINAL NAME
90. ol Register Description FIELD NAME TYPE DESCRIPTION When this bit is set received packets are placed back to back to completely fill each receive buffer 81 butferFill RSC When this bit is cleared each received packet is placed in a single buffer If bit 28 multiChanMode is set to 1 then this bit must also be set to 1 The value of this bit must not be changed while bit 10 active or bit 15 run is set When this bit is 1 received isochronous packets include the complete 4 byte isochronous packet header seen by the link layer The end of the packet is marked with xferStatus in the first doublet and 30 isochHeadet RSC a 16 bit timeStamp indicating the time of the most recently received or sent cycleStart packet When this bit is cleared the packet header is stripped from received isochronous packets The packet header if received immediately precedes the packet payload The value of this bit must not be changed while bit 10 active or bit 15 run is set 4 38 Table 4 30 Isochronous Receive Context Control Register Description Continued BIT FIELD NAME TYPE DESCRIPTION When this bit is set the context begins running only when the 13 bit cycleMatch field bits 24 12 in the isochronous receive context match register see Section 4 43 matches the 13 bit cycleCount cycleMatchEnable field in the cycleStart packet The effects of this bit however are impacted by the values of other bits in this register Once the contex
91. ot implemented It returns all Os when read 0 m as o 17 1 5 T 202 LIB pad m Physical upper bound Type Read only Offset 120h Default 0000 0000h 4 34 4 37 Asynchronous Context Control Register The asynchronous context control set clear register controls the state and indicates status of the DMA context See Table 4 27 for a complete description of the register contents s so 29 20 27 26 25 24 23 22 21 20 19 18 17 16 Asynchronous context control OE 15 1 12 J wo 9 e 7 e s ja Ja e t Asynchronous context control Name 77 Asynhmomousconexconro RSCU R RSU RU R R RU RU RU RU RU RU RU RU fau 0 0 x o x Register Asynchronous context control Type Read Set Clear Update Read Set Update Read Update Read only Offset 180h setregister ATRQ 184h clear register ATRQ 1A0h set register ATRS 1A4h clear register 1COh set register 1C4h clear register ARR
92. requests received by the TSB12LV26 from that node are accepted If this bit is set for local bus node number 42 then asynchronous requests received by the TSB12LV26 from that node are accepted If this bit is set for local bus node number 40 then asynchronous requests received by the TSB12LV26 from that node are accepted If this bit is set for local bus node number 39 then asynchronous requests received by the TSB12LV26 from that node are accepted If this bit is set for local bus node number 38 then asynchronous requests received by the TSB12LV26 from that node are accepted If this bit is set for local bus node number 37 then asynchronous requests received by the TSB12LV26 from that node are accepted If this bit is set for local bus node number 36 then asynchronous requests received by the TSB12LV26 from that node are accepted If this bit is set for local bus node number 35 then asynchronous requests received by the TSB12LV26 from that node are accepted ReaR 34 If this bit is set for local bus node number 34 then asynchronous requests received by the TSB12LV26 from that node accepted ReaR If this bit is set for local bus node number 33 then asynchronous requests received by the asynneqnesource TSB12LV26 from that node are accepted ReaR 82 If this bit is set for local bus node number 32 then asynchronous requests received by the TSB12LV26 from that node are accept
93. rite address low Posted write address low Name peau x x x X x x Register Posted write address low Type Read Update Offset 38h Default XXXX XXXXh 4 14 Posted Write Address High Register The posted write address high register is used to communicate error information if a write request is posted and an error occurs while writing the posted data packet See Table 4 9 for a complete description of the register contents so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Posted write address high peut X X x x x x x x X x x Tx x x Register Posted write address high Type Read Update Offset 3Ch Default XXXX XXXXh Table 4 9 Posted Write Address High Register Description FIELD NAME TYPE DESCRIPTION 31 16 sourcelD RU This field is the bus and node number of the node that issued the write request that failed Bits 31 22 are the 10 bit bus number and bits 21 16 are the 6 bit node number The upper 16 bits of the 1394 destination offset of the write request that failed 4 15 Vendor ID Register The vendor ID register holds the company ID of an organization that specifies any vendor unique registers The TSB12LV26 does not implement Texas Instruments unique behavior with regards to OHCI Thus this register is read only and returns Os when read Vendor ID
94. rough a 220 Q resistor The REG18 terminals are connected to a 0 01 uF capacitor which in turn is connected to ground The capacitor provides a local bypass for the internal core voltage Serial clock The TSB12LV26 determines whether a two wire serial ROM is implemented at reset If a two wire Sojo serial ROM is implemented then this terminal provides the SCL serial clock signaling This terminal is implemented as open drain and for normal operation a ROM is implemented in the design this terminal should be pulled high to the ROM Vcc with a 2 7 kQ resistor Otherwise it should be pulled low to ground with a 220 Q resistor Serial data The TSB12LV26 determines whether a two wire serial ROM is implemented at reset If a two wire serial ROM is detected then this terminal provides the SDA serial data signaling This terminal must be wired low to indicate no serial ROM is present This terminal is implemented as open drain and for normal operation a ROM is implemented in the design this terminal should be pulled high to the ROM Vcc with a 2 7 kQ resistor Otherwise it should be pulled low to ground with a 220 Q resistor 2 8 3 TSB12LV26 Controller Programming Model This section describes the internal registers used to program the TSB12LV26 All registers are detailed in the same format a brief description for each register followed by the register offset and a bit table describing the reset state for each register
95. rred The TSB12LV26 needs not be the target of the PCI cycle to assert this signal This terminal is implemented as open drain PCI cycle stop signal This signal is driven by a PCI target to request the initiator to stop the current PCI bus transaction This signal is used for target disconnects and is commonly asserted by target devices which do not support burst data transfers PCI target ready PCI TRDY indicates the ability of the PCI bus targer to complete the current data phase of the transaction A data phase is completed upon a rising edge of PCI CLK where both PCI IRDY and PCI TRDY are asserted Table 2 7 IEEE 1394 PHY Link Terminals vo DESCRIPTION PHY link interface control These bidirectional signals control passage of information between the two devices PHY_CTL1 PHY_CTLO The TSB12LV26 can only drive these terminals after the PHY has granted permission following a link request PHY_LREQ PHY_DATA7 PHY_DATA6 PHY DATAS PHY_DATA4 PHY_DATA3 PHY_DATA2 PHY_DATA1 PHY_DATAO PHY_LINKON PHY_LPS PHY_LREQ PHY_SCLK PHY link interface data These bidirectional signals pass data between the TSB12LV26 and the PHY device These terminals are driven by the TSB12LV26 on transmissions and are driven by the PHY on reception Only PHY 1 DATAO are valid for 100 Mbit speeds are valid for 200 Mbit speeds and PHY DATA7 PHY DATAO are valid for 400 M
96. s request packets that the link is permitted to make of the PHY during a fairness interval pri_req 4 23 4 28 Link Control Register The link control set clear register provides the control flags that enable and configure the link core protocol portions of the TSB12LV26 It contains controls for the receiver and cycle timer See Table 4 19 for a complete description of the register contents 31 so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Link control fee Rn a R Beau o o o o o fo fo fo fo 0 15 14 13 v 0 9 7 5 4 2 1 Name R R RC RC R R R Deaut o o o x x o j o jf o o Register Link control Type Read Set Clear Update Read Set Clear Read only Offset EOh set register E4h clear register Default 00X0 Table 4 19 Link Control Register Description FIELD NAME TYPE DESCRIPTION 31 23 RSVD Reserved Bits 31 23 return Os when read When this bitis set the cycle timer uses an external source CYCLEIN to determine when to roll over 22 cycleSource RSC the cycle timer When this bit is cleared the cycle timer rolls over when the timer reaches 3072 cycles of the 24 576 MHz clock 125 us
97. scellaneous configuration register is loaded from 10 D2 SUPPORT RU ROM When this bit is set it indicates that D2 support is present When this bit is cleared it indicates that D2 support is not present for backward compatibility with the TSB12LV22 For normal operation this bit is set to 1 ER D1 SUPPORT ES D1 support This bit returns a 0 when read indicating that the TSB12LV26 does not support the D1 power state Dynamic data support This bit returns a 0 when read indicating that TSB12LV26 does not report DYN DATA dynamic power consumption data RSVD R Reserved Bits 7 6 return 05 when read Device specific initialization This bit returns 0 when read indicating that the TSB12LV26 does not 5 DSI require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it Auxiliary power source Since the TSB12LV26 does not support PME generation in the 4 AUX PWR i sk device state this bit returns 0 when read 3 PME CLK PME clock This bit returns 0 when read indicating that no host bus clock is required for the TSB12LV26 to generate PCI PME Power management version This field returns 001b when read indicating that the TSB12LV26 is 2 0 PM VERSION compatible with the registers described in the PC Bus Power Management Interface Specification Rev 1 0 3 18 Power Management Control and Status Register The power management control and status regis
98. se Address Register The extension base address register is programmed with a base address referencing the memory mapped extension registers See the OHCI Base Address Register Section 3 9 for bit field details s so 29 28 27 26 25 24 23 22 21 20 19 18 17 Tl extension base address Name 2 TleMensonbeseaddess 02 Default 0 Tl extension base address Rw ra rR n Pm TI extension base address Type Read Write Read only Offset 14h Default 0000 0000h 3 11 Subsystem Identification Register The subsystem identification register is used for system and option card identification purposes This register can be initialized from the serial ROM or programmed via the subsystem ID and subsystem vendor ID alias registers at offset F8h See Table 3 9 for a complete description of the register contents 9t so 28 27 26 25 24 23 22 21 20 19 18 17 16 Subsystem identification Name 72 Default 0 Name Subsystem identification peau o o o fo jo jo jo fo Register Subsystem identification Type Read Update Offset 2Ch Default 0000 0000h Table 3 9 Subsystem Identification Register Description
99. sets this bit when it encounters fatal error and clears the bit when software resets 11 dead bit 15 run RU The TSB12LV26 sets this bit to 1 when it is processing descriptors Reserved Bits 9 8 return Os when read This field indicates the speed at which the packet was received 000 100 Mbits sec 001 200 Mbits sec and 010 400 Mbits sec All other values are reserved For bufferFill mode possible values are ack_complete evt_descriptor_read evt_data_write and evt_unknown Packets with data errors either dataLength mismatches or dataCRC errors and 4 0 event code RU packets for which a FIFO overrun occurred are backed out For packet per buffer mode possible values are ack_complete ack_data_error evt_long_packet evt_overrun evt_descriptor_read evt_data_write and evt_unknown multiChanMode 4 39 4 42 Isochronous Receive Context Command Pointer Register The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the TSB12LV26 accesses when software enables an isochronous receive context by setting the isochronous receive context control register see Section 4 41 bit 15 run The n value in the following register addresses indicates the context number n 0 1 2 3 s 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name sowonourecevecontextcommandpomnter Isochronous receive context
100. sochronous transmit context if an OUTPUT_LAST command completes and its interrupt bits are set Upon determining that the interrupt event register OHCI offset 80h 84h see Section 4 21 isochTx bit 6 interrupt has occurred software can check this register to determine which context s caused the interrupt The interrupt bits are set by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register See Table 4 16 for a complete description of the register contents Isochronous transmit interrupt event 6 o o o fo fo fo fo 0 0 0 3t so 29 28 27 26 25 24 23 22 21 20 18 17 16 Isochronous transmit interrupt event ______________________ interrupt event R asc 955 Asc 850 RSC pea fo txt x x 15 14 1 12 v0 9 7 e 5 a ja 2 0 Register Isochronous transmit interrupt event Type Read Set Clear Read only Offset 90h set register 94h clear register returns IsoXmitEvent and IsoXmitMask when read Default 0000 00XXh Table 4 16 Is
101. t has become active hardware clears this bit The value of this bit must not be changed while bit 10 active or bit 15 run is set When this bit is set the corresponding isochronous receive DMA context receives packets for all isochronous channels enabled in the isochronous receive channel mask high OHCI offset 70h 74h see Section 4 19 and isochronous receive channel mask low OHCI offset 78h 7Ch see Section 4 20 registers The isochronous channel number specified in the isochronous receive context match register see Section 4 43 is ignored When this bit is cleared the isochronous receive DMA context receives packets for that single channel Only one isochronous receive DMA context may use the isochronous receive channel mask registers If more than one isochronous receive context control register has this bit set then results are undefined The value of this bit must not be changed while bit 10 active or bit 15 run is set to 1 27 16 RSVD Reserved Bits 27 16 return 0 when read 15 nin This bit is set by software to enable descriptor processing for the context and cleared by software to 7 stop descriptor processing The TSB12LV26 changes this bit only on a hardware or software reset 14 13 RSVD Bits 14 13 return 05 when read 12 RSU Software sets this bit to cause the TSB12LV26 to continue or resume descriptor processing The wase TSB12LV26 clears this bit on every descriptor fetch The TSB12LV26
102. ter implements the control and status of the PCI power management function This register is not affected by the internally generated reset caused by the transition from the DO state See Table 3 15 for a complete description of the register contents 15 14 v3 12 wo 7 j e 5 J 3 2 Power management control and status Powermanagement control and status we rc R R nn R few rR n R pem fo fo Register Power management control and status Type Read Clear Read Write Read only Offset 48h Default 0000h Table 3 15 Power Management Control and Status Register Description FIELD NAME TYPE DESCRIPTION This bit is set when the TSB12LV26 would normally be asserting the PME signal independent of the 15 PME STS RC state of bit 8 PME ENB This bit is cleared by a writeback of 1 and this also clears the PCI PME signal driven by the TSB12LV26 Writing a 0 to this bit has no effect Dynamic data control This field returns Os when read since the TSB12LV26 does not report dynamic DYN CTRL data PME_ENB PCI PME PME enable This bit enables the function to assert PCI PME PME If this bit is cleared then assertion of PCI PME PME is disabled RSVD Reserved Bits 7 5 return Os when read DYN_DATA Dynamic data This bit returns 0 when read since the TSB12LV26
103. the low order two bits of cycleSeconds and the 13 bit cycleCount field in the cycleStart packet If isochronous receive context control register see Section 24 12 cycleMatch R W 4 41 bit 29 cycleMatchEnable is set then this context is enabled for receives when the two low order bits of the bus isochronous cycle timer register OHCI offset FOh see Section 4 31 cycleSeconds field bits 31 25 and cycleCount field bits 24 12 value equal this cycleMatch field value field contains the 4 bit field which is compared to the sync field of each iso packet this channel the command descriptor w field is set to 116 7 RSVD Reserved Bit 7 returns 0 when read If this bit and bit 29 tag1 are set then packets with tag 01b are accepted into the context if the two most significant bits of the packets sync field 006 Packets with tag values other than 01b are filtered tag1SyncFilter according to 90 tag2 and tag3 bits 28 30 and 31 respectively without any additional restrictions If this bit is cleared then this context matches on isochronous receive packets as specified in bits 28 31 1490 1 93 with no additional restrictions This 6 bit field indicates the isochronous channel number for which this isochronous receive context accepts packets 4 41 4 42 5 GPIO Interface The general purpose input output GPIO int
104. uld be cleared to 0 all applications When this bit is set the internal PCI clock runs identically with the chip input This bit is a test DISABLE PCIGATE feature only and should be cleared 10 0 all applications KEEP PCLK R W When this bitis setto 1 the PCI clock is always kept running through the PCI_CLKRUN protocol When this bit is cleared the PCI clock may be stopped using PCI CLKRUN 3 21 Link Enhancement Control Register The link enhancement control register implements proprietary bits that are initialized by software or by a serial ROM if present After these bits are set their functionality is enabled only if bit 22 aPhyEnhanceEnable in the host controller control register offset 50h 54h see Section 4 16 is set See Table 3 18 for a complete description of the register contents Link enhancement control po mkenhncementcontiol fo fo fo fo fo fo opjo 0 s so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Be 35 Link enhancement control Name peau o Register Link enhancement control Type Read Write Read only Offset F4h Default 0000 1000h Table 3 18 Link Enhancement Control Register Descriptio
105. urce node is on the same bus as the TSB12LV26 Nonlocal bus sourced packets are not acknowledged unless bit 31 in this register is set See Table 4 23 for a complete description of the register contents 31 29 28 27 26 25 24 23 22 zi 20 18 17 16 Asynchronous request filter high __ 15 2 7 s 12 Asynchronous request filter high Deaut o o o o fo jo fo o jo jo o fo jo o Register Asynchronous request filter high Type Read Set Clear Offset 100h setregister 104h clear register Default 0000 0000h Table 4 23 Asynchronous Request Filter High Register Description FIELD NAME TYPE DESCRIPTION 4 us 62 then asynchronous requests received by the die e e 2 a 61 then asynchronous requests received by the 4 aia 2 60 then asynchronous requests received by the 59 then asynchronous requests received by the 2 a 58 then asynchronous requests received by the ome dh 2 57 then asynchronous requests received by the z Puce 1 55 then asynchronous requests received by the 2 d 1 2 54 then asynchronous requests received by the 4 2 a 53 then asynchronous requests received by the 42 bade
106. ved Bit 24 returns 0 when read EEN 16 RU This field represents the data read from the GUID ROM RSVD Reserved Bits 15 0 return Os when read 4 5 4 3 Asynchronous Transmit Retries Register The asynchronous transmit retries register indicates the number of times the TSB12LV26 attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit See Table 4 4 for a complete description of the register contents 9t so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Asynchronous transmit retries Asynchronous transmit retries Name Hye Rw pea o Register Asynchronous transmit retries Type Read Write Read only Offset 08h Default 0000 0000h Table 4 4 Asynchronous Transmit Retries Register Description 31 25 secondumi R Tne second imit field returns 0s when ead since outbound dual phase ety isnot implemented R Reserved Bits 15 12 return Os when read This field tells the physical response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node R W This field tells the asynchronous transmit response unit how man
107. y times to attempt to retry the transmit operation for the response packet when a busy acknowledge data error is received from the target node This field tells the asynchronous transmit DMA request unit how many times to attempt to retry the R W transmit operation for the response packet when a busy acknowledge or data error is received from the target node 4 4 CSR Data Register The CSR data register is used to access the bus management CSR registers from the host through compare swap operations This register contains the data to be stored in a CSR if the compare is successful 31 30 29 28 27 26 25 24 23 22 zi 20 18 17 16 CSR data CSR data X x x x x x X x x x x Tx Jx Register CSR data Type Read only Offset OCh Default XXXX XXXXh 4 6 4 5 CSR Compare Register The CSR compare register is used to access the bus management CSR registers from the host through compare swap operations This register contains the data to be compared with the existing value of the CSR resource 31 so 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name fT C8Remmpae o CSR compare R AR peau X X

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