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Texas Instruments TMS320DM357 User's Manual

1. 15 14 13 12 11 10 9 8 Reserved MODE DMAEN FRCDATATOG DMAMODE DATATOGWREN DATATOG R 0 R W 0 R W 0 R W 0 R W 0 WO R W 0 7 6 5 4 3 2 1 0 NAK_TIMEOUT CLRDATATOG RXSTALL SETUPPKT FLUSHFIFO ERROR FIFONOTEMPTY TXPKTRDY R W 0 WO R W 0 R W 0 W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only W Write only n value after reset Table 76 Control Status Register for Host Transmit Endpoint HOST_TXCSR Field Descriptions Bit Field Value Description 15 14 Reserved 0 Reserved 13 MODE 0 1 Set this bit to enable the endpoint direction as Tx and clear this bit to enable it as Rx Note This bit has any effect only where the same endpoint FIFO is used for both Transmit and Receive transactions 12 DMAEN 0 1 Set this bit to enable the DMA request for the Tx endpoint 11 FRCDATATOG 0 1 Set this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO regardless of whether an ACK was received This can be used by Interrupt Tx endpoints that are used to communicate rate feedback for Isochronous endpoints 10 DMAMODE 0 1 When using DMA clear this bit to receive an interrupt for each packet or set this bit to only receive error interrupts 9 DATATOGWREN 0 1 Set this bit to enable the DATATOG bit to be written This bit is automatically cleared once the new value is written to DATATOG 8 DATATOG 0 1 When read this bit indicates the current state of the Tx EP dat
2. Bit Field Value Description 31 0 DATA 0 FFFF FFFFh Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint Reading from these addresses unloads data from the Receive FIFO for the corresponding endpoint 136 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 78 OTG Device Control Register DEVCTL The OTG Device Control Register DEVCTL is shown in Figure 93 and described in Table 94 Figure 93 OTG Device Control Register DEVCTL 7 6 5 4 3 2 1 0 BDEVICE FSDEV LSDEV VBUS HOSTMODE HOSTREQ SESSION R 0 HO R 0 R 0 R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 94 OTG Device Control Register DEVCTL Field Descriptions Bit Field Value Description 7 BDEVICE This read only bit indicates whether the USB controller is operating as the A device or the B device 0 IA device B device Only valid while a session is in progress 6 FSDEV 0 1 This read only bit is set when a full speed or high speed device has been detected being connected to the port high speed devices are distinguished from full speed by checking for high speed chirps when the device is reset Only valid in Host mode 5 LSDEV 0 1 This read only bit is set when a low speed device has been detected being connected to the port Only valid in Host mode 4 3
3. LEGEND R W Read Write R Read only n value after reset Table 35 Transmit CPPI Interrupt Enable Set Register TCPPIIENSETR Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 0 COMP_PENDING_INTR_EN 0 Fh Transmit CPPI High Priority Interrupt Enables These are active high interrupt enables corresponding to the Transmit CPPI High Priority Completion Pending status bits 4 20 Transmit CPPI Interrupt Enable Clear Register TCPPIIENCLRR The Transmit CPPI Interrupt Enable Clear Register TCPPIIENCLRR is shown in Figure 35 and described in Table 36 Figure 35 Transmit CPPI Interrupt Enable Clear Register TCPPIIENCLRR 31 16 Reserved HO 15 4 3 0 Reserved COMP_PENDING_INTR_EN R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 36 Transmit CPPI Interrupt Enable Clear Register TCPPIIENCLRR Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 0 COMP_PENDING_INTR_EN 0 Fh Writing a 1 to any of the bits in the Transmit CPPI Interrupt Enable Clear Register will result in clearing of the corresponding bit in the Transmit CPPI High Priority Interrupt Enable Register SPRUGH3 November 2008 96 Universal Serial Bus USB Controller Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 21 Receive CPPI Control Register RCPPICR T
4. I TEXAS Preface INSTRUMENTS SPRUGH3 November 2008 Read This First About This Manual This document describes the universal serial bus USB controller in the TMS320DM357 Digital Media System on Chip DMSoC Notational Conventions This document uses the following conventions e Hexadecimal numbers are shown with the suffix h For example the following number is 40 hexadecimal decimal 64 40h e Registers in this document are shown in figures and described in tables Each register figure shows a rectangle divided into fields that represent the fields of the register Each field is labeled with its bit name its beginning and ending bit numbers above and its read write properties below A legend explains the notation used for the properties Reserved bits in a register figure designate a bit that is used for future device expansion Related Documentation From Texas Instruments The following documents describe the TMS320DM357 Digital Media System on Chip DMSoC Copies of these documents are available on the Internet at www ti com Tip Enter the literature number in the search box provided at www ti com SPRUGO6 TMS320DM357 DMSoC Video Processing Back End VPBE User s Guide Describes the video processing back end VPBE in the TMS320DM357 Digital Media System on Chip DMSoC video processing subsystem Included in the VPBE is the video encoder on screen display and digital LCD controller SPRUG25 TMS3
5. The EMIF supports a glueless interface to a variety of external devices SPRUG34 TMS320DM357 DMSoC Enhanced Direct Memory Access EDMA Controller User s Guide Describes the operation of the enhanced direct memory access EDMAS3 controller in the TMS320DM357 Digital Media System on Chip DMSoC The EDMAS controllers primary purpose is to service user programmed data transfers between two memory mapped slave endpoints on the DMSoC SPRUG35 TMS320DM357 DMSoC Audio Serial Port ASP User s Guide Describes the operation of the audio serial port ASP audio interface in the TMS320DM357 Digital Media System on Chip DMSoC The primary audio modes that are supported by the ASP are the AC97 and IIS modes In addition to the primary audio modes the ASP supports general serial port receive and transmit operation but is not intended to be used as a high speed interface SPRUG36 TMS320DM357 DMSoC Ethernet Media Access Controller EMAC Management Data Input Output MDIO Module User s Guide Discusses the ethernet media access controller EMAC and physical layer PHY device management data input output MDIO module in the TMS320DM357 Digital Media System on Chip DMSoC The EMAC controls the flow of packet data from the DMSoC to the PHY The MDIO module controls PHY configuration and status monitoring Read This First SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Notational Conventions
6. and 0 of USBPHY_CTL DMA DMA CO OO OO OO OO OO OO fd Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Introduction User Case 2 An example of how to program the USB Endpoints in peripheral mode Example 2 Programming the USB Endpoints in Peripheral Mode DMA channel number Valid values are 0 1 2 or 3 int CHAN_NUM 0 Fifo sizes uncomment the desired size This example uses 64 byte fifo int fifosize 0 8 bytes int fifosize 1 16 bytes int fifosize 2 32 bytes int fifosize 3 64 bytes int fifosize 4 128 bytes int fifosize 5 256 bytes int fifosize 6 512 bytes int fifosize 7 1024 bytes int fifosize 8 2048 bytes int fifosize 9 4096 bytes FIFO address Leave 64 bytes for endpoint 0 int fifo_start_address 8 Uncomment the desired buffering If double buffer is selected actual FIFO space will be twice the value listed above for fifosize This example uses single buffer int double_buffer 0 Single buffer int double_buffer 1 Double buffer For maximum packet size this formula will usually work but it can also be set to another value if needed If non power of 2 value is needed such as 1023 set it explicitly define FIFO_MAXP 8 1 lt lt fifosize Set the following variable to the device addres
7. DATA 0 FFFF FFFFh Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint Reading from these addresses unloads data from the Receive FIFO for the corresponding endpoint SPRUGH3 November 2008 Universal Serial Bus USB Controller 135 Submit Documentation Feedback JA TEXAS INSTRUMENTS Registers www ti com 4 76 Transmit and Receive FIFO Register for Endpoint 3 FIFO3 The Transmit and Receive FIFO Register for Endpoint 3 FIFO3 is shown in Figure 91 and described in Table 92 Figure 91 Transmit and Receive FIFO Register for Endpoint 3 FIFO3 DATA R W 0 LEGEND R W Read Write n value after reset Table 92 Transmit and Receive FIFO Register for Endpoint 3 FIFO3 Field Descriptions Bit Field Value Description 31 0 DATA 0 FFFF FFFFh Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint Reading from these addresses unloads data from the Receive FIFO for the corresponding endpoint 4 77 Transmit and Receive FIFO Register for Endpoint 4 FIFO4 The Transmit and Receive FIFO Register for Endpoint 4 FIFO4 is shown in Figure 92 and described in Table 93 Figure 92 Transmit and Receive FIFO Register for Endpoint 4 FIFO4 31 0 DATA R W 0 LEGEND R W Read Write n value after reset Table 93 Transmit and Receive FIFO Register for Endpoint 4 FIFO4 Field Descriptions
8. Descriptor zeroes the appropriate DMA state head descriptor pointer and then issues a Tx interrupt to the host by writing address of the last buffer descriptor processed by the DMA controller to the queue s associated Tx completion pointer TCPPICOMPPTR register On interrupt from the port the software can process the buffer queue detecting transmitted packets by the status of the Ownership bit in the SOP buffer descriptor If the Ownership bit is cleared to zero then the packet has been transmitted and the software may reclaim the buffers associated with the packet The software continues queue processing until the end of the queue or until a SOP buffer descriptor is read that contains a set Ownership bit indicating that the packet transmission is not complete The software determines that all packets in the queue have been transmitted when the last packet in the queue has a cleared Ownership bit in the SOP buffer descriptor the End of Queue bit is set in the last packet EOP buffer descriptor and the Next Descriptor Pointer of the last packet EOP buffer descriptor is zero The software acknowledges an interrupt by writing the address of the last buffer descriptor to the queue s associated Tx Completion Pointer TCPPICOMPPTR register If the software written buffer address value in TCCPICOMPPTR register is different from the buffer address written by the DMA controller after Tx completion then the interrupt for the Tx Channel remains asser
9. R 0 R 0 15 13 12 8 7 5 4 0 Reserved RX Reserved TX R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 21 USB Interrupt Source Register INTSRCR Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 16 USB 0 1FFh USB interrupt sources Generated by the USB core not the DMA 15 13 Reserved 0 Reserved 12 8 RX 0 1Fh Receive endpoint interrupt sources Generated by the USB core not the DMA 7 5 Reserved 0 Reserved 4 0 TX DER Transmit endpoint interrupt sources Generated by the USB core not the DMA SPRUGH3 November 2008 Submit Documentation Feedback Universal Serial Bus USB Controller 85 Registers 4 6 USB Interrupt Source Set Register INTSETR I TEXAS INSTRUMENTS www ti com The USB Interrupt Source Set Register INTSETR is shown in Figure 21 and described in Table 22 Figure 21 USB Interrupt Source Set Register INTSETR 31 25 24 16 Reserved USB R 0 15 13 12 WO Reserved RX Reserved TX R 0 W 0 LEGEND R Read only W Write only n value after reset R 0 W 0 Table 22 USB Interrupt Source Set Register INTSETR Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 16 USB 0 1FFh Write a 1 to set equivalent USB interrupt source Allows the USB interrupt sources to be manual
10. RCPPIENSETR eceeceeeeeeeeee na nn nnunnnnnnnnn nn nun nn nen 98 40 Receive CPPI Interrupt Enable Clear Register RCPPIIENCLRR uu2ussunnunnennennnannnnnannnnnnnnnnnn nen 99 41 Receive Buffer Count 0 Register RBUFCNTO 0ceeceeee eee e eee cence ence ee nun nannannnunnnnnannnannnnnnnn nen 99 42 Receive Buffer Count 1 Register RBUFCNT1 zuusssunnennnnnennnannnnnnunnunnunnnnnnnnnnnnnunnnunnun nun nunnenn 100 43 Receive Buffer Count 2 Register RBUFCNT2 zuesssennansunnannnennunnnnnnunnannnnnnnnnnnnnunnnunnnn nun nunnenn 100 44 Receive Buffer Count 3 Register RBUFCNTS zuuussunnannunnannnannunnnnnnunnannnnnnnnnnnn nun nnunnun nun nunnnn 101 45 Transmit CPPI DMA State Word 0 TCPPIDMASTATEWO zuruausannnunnannannnunnnnnannnnnnnnnnnnnnnnnunnunnn 101 46 Transmit CPPI DMA State Word 1 TCPPIDMASTATEWI eee eee eee eee eeeeeeeeeeeeeeeeeeneeneees 102 47 Transmit CPPI DMA State Word 2 TCPPIDMASTATEWD eee cece eee eeeeeeeeeeeeeeeeeeeeeeeenenes 102 48 Transmit CPPI DMA State Word 3 TCPPIDMASTATEW3 ences eeeeeeeeeeeeeeeeeeeeeeeeeees 103 49 Transmit CPPI DMA State Word 4 TCPPIDMASTATEWA seen eeeee ence eee eeeeeeeeeeeeeeeeeeneeneees 103 50 Transmit CPPI DMA State Word 5 TCPPIDMASTATEW5 zussaunannnnnnannunnnunnnnnannnunnnnnnnn nen nun 104 51 Transmit CPPI Completion Pointer TCPPICOMDPTD eee eeeeeeeeeeeeeeeeeeeeeeeeneeneeeees 104 52 Receive CPPI DMA State Word 0 RCPPIDMASTATEWO zuzusssnnennnunnennannnunnnnnnnnnan
11. Solutions www ti com lprf Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2008 Texas Instruments Incorporated
12. TEXAS INSTRUMENTS www ti com 3 3 2 4 USB Controller Host and Peripheral Modes Operation Receive Queue Figure 15 shows an Rx Queue Rx queue provide a logical queue of processor memory space for DMA packets to be received from DMA controller channel Each channel has single Rx queue There are no multiple queue as in transmit channels Each queue has one associated Rx Queue Head Descriptor Pointer and one associated Rx Completion Pointer contained in the channel Rx DMA State The Rx queue are linked lists of Rx buffer descriptors that constitute processor memory space for one or more packets to be received Packet space is added to the tail of the list by the software and received packets are freed from the list by the DMA controller as each packet is received 3 3 2 5 Figure 15 Rx Queue Flow Chart SOP descriptor EOP descriptor Rx queue head descriptor pointer Operation After reset the software must write zeroes to all Rx DMA State registers RCPPIDMASTATEWO RCPPIDMASTATEW1 RCPPIDMASTATEW2 RCPPIDMASTATEW3 RCPPIDMASTATEW4 RCPPIDMASTATEW5 and RCPPIDMASTATEW6 The software constructs receive queue in memory Enable DMA for the endpoint in the PERILRXCSR or HOST_RXCSR by setting the DMAEN bit Enable the DMA ports by setting RCPPI_ENABLE bit of RCPPICR register Set the value in RBUFCNTn register where n is the channel number for the number of buffers available in the Rx queue The hardware requires at least
13. Teardown allows software to terminate the current Tx queue by notifying the DMA The DMA will stop the current Tx DMA for that channel and update the channel parameters to remove all Tx descriptors from that queue Then the software is free to reclaim the buffers without worry of interrupting the DMA in progress Teardown of Tx channels is done using the TCPPITDR register If the READY bit of TCPPITDR register is set it signifies that the Tx channel can be torn down The channel number should be written in the CHANNEL field of TCPPITDR register to teardown the channel Note that the software must also teardown the core after the DMA Software should specify that the following steps are all completed before assuming teardown has completed successfully 1 After tearing down the channel DMA interrupt should be generated and the TCPPICOMPPTR register will be FFFF FFFCh This indicates that the DMA has completed the teardown and all the data buffers can be reclaimed 2 The software must set the FLUSHFIFO bit of the PERI_TXCSR or HOST_TXCSR register for the endpoint to be torn down After both the DMA and the core are torn down the DMA channel and endpoint can be restarted cleanly A failure to perform either of these steps could result in data loss or spurious data upon restart DMA Receive Operation For receive operation the software has to program the DMA channel with a chain of receive buffers 3 3 2 1 Receive Buffer 62 A receive
14. When operating in ISO mode this bit is set when RXPKTRDY is set if the data packet has a CRC or bit stuff error and cleared when RXPKTRDY is cleared In Bulk mode this bit will be set when the Receive endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK Limit by the RXINTERVAL register You should clear this bit to allow the endpoint to continue 2 ERROR 0 1 The USB controller sets this bit when 3 attempts have been made to receive a packet and no data packet has been received You should clear this bit An interrupt is generated when the bit is set Note This bit is only valid when the transmit endpoint is operating in Bulk or Interrupt mode In ISO mode it always returns zero 1 FIFOFULL 0 1 This bit is set when no more packets can be loaded into the Receive FIFO 0 RXPKTRDY 0 1 This bit is set when a data packet has been received You should clear this bit when the packet has been unloaded from the Receive FIFO An interrupt is generated when the bit is set 126 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers SPRUGH3 November 2008 Universal Serial Bus USB Controller 127 Submit Documentation Feedback JA TEXAS INSTRUMENTS Registers www ti com 4 64 Count 0 Register COUNTO The Count 0 Register COUNTO is shown in Figure 79 and described in Table 80 Figure 79 Count 0 Regis
15. ausunnsnsnennannnunnnnnannnnnnnnnnnnnnnnnnnnunnn 101 Transmit CPPI DMA State Word 1 TCPPIDMASTATEW1 uusannsunnennannnunnnnnannnnnnnnnnnn nenn nannunnn 102 Transmit CPPI DMA State Word 2 TCPPIDMASTATEW2 zausanssnnnannannnunnannunnnnnnnnnnnnnannnannunnn 102 Transmit CPPI DMA State Word 3 TCPPIDMASTATEWS ausunnennnannannnunnnnnannnnnnnnnnnnnnnnnunnenen 103 Transmit CPPI DMA State Word 4 TCPPIDMASTATEWA cece eeee eee eeeeeeeeeeeeeeeeeeeeeneees 103 Transmit CPPI DMA State Word 5 TCEPPIDMASTATEW5 tence ee eeeeneeeeeeeeeeeeeeeeneees 104 Transmit CPPI Completion Pointer TCPPICOMPPTR AN 104 Receive CPPI DMA State Word 0 HCPDPIDMAGSTATEWO test eee eee eee eeeeeeeeeeeeeeeeeeeee 105 Receive CPPI DMA State Word 1 HCPDPIDMAGSTATEWI seen eee eeeeeeeeeeeeeeeeeeeeeeeeeee 108 Receive CPPI DMA State Word 2 HCPDPIDMAGTATEWO teen eee eee teen eeeeeeeeeeeeeeneeeee 107 Receive CPPI DMA State Word 3 HCPDPIDMAGTATEWZ test ee eeeeeeeeeeeeeeeeeeeeeeneeeee 107 Receive CPPI DMA State Word 4 HCPDPIDMAGSTATEWA eee eee tees eee eeeeeeeeeeeeeeneeeneeeee 109 Receive CPPI DMA State Word 5 DCPDPIDMAGTATEWD teen ee eeee sees eeeeeeeeeeeeeeneeeee 109 Receive CPPI DMA State Word 6 HCPDPIDMAGTATEWG teense ence eee eeeeeeeeeeneeeeeeeee 110 Receive CPPI Completion Pointer DCPPICOMPPTDR namen nnnun nun nennen 110 Function Address Register FADDR zuusssnnnennnnnnnnnnnnnnnnnnenn nenne nun ernennen nenne nennen ennn nennen 111 Power Manageme
16. current packet 1 Reserved 0 Reserved 0 IN_PACKET Flag indicating the DMA is in the middle of processing a packet 0 Not currently in packet 0 Not currently in packet Currently in packet 4 40 Receive CPPI DMA State Word 3 RCPPIDMASTATEW3 The Receive CPPI DMA State Word 3 RCPPIDMASTATEWS3 is shown in Figure 55 and described in Table 56 Figure 55 Receive CPPI DMA State Word 3 RCPPIDMASTATEW3 31 16 CURR_DESCRIPTOR_PTR R W 0 15 1 0 CURR_DESCRIPTOR_PTR Reserved R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 56 Receive CPPI DMA State Word 3 RCPPIDMASTATEWS3 Field Descriptions Bit Field Value Description 31 2 CURR_DESCRIPTOR_PTR 0 3FFF FFFFh Current Buffer Descriptor Pointer 30 bit pointer to 32 bit aligned descriptor for buffer into which data is currently being received 1 0 Reserved 0 Reserved SPRUGH3 November 2008 Universal Serial Bus USB Controller 107 Submit Documentation Feedback I TEXAS INSTRUMENTS Registers www ti com 108 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 41 Receive CPPI DMA State Word 4 RCPPIDMASTATEW4 The Receive CPPI DMA State Word 4 RCPPIDMASTATEW4 is shown in Figure 56 and described in Table 57 Figure 56 Receive CPPI DMA State Word A RCPPIDMASTATEWA 31 0 C
17. ecceeeeeeeee eee e eee neeeee ences eeeeeenaeteeeeeeeeeeeaeeeeeeeenaeeaeees 88 24 USB Interrupt Mask Set Register INTMSKSETR 0 seeeeee seen eens ee ee eens eee eee tees un nnnn nun nn nun nun nn nen 89 25 USB Interrupt Mask Clear Register INTMSKCLRR seceeee sere cece eee renee eee nun nun sees eee nun nun nun nun nen 90 26 USB Interrupt Source Masked Register NTMAGKE DD 91 27 USB End of Interrupt Register EOID ENEE EE 92 28 USB Interrupt Vector Register INTVECTR zusrsusnanennnannnannunnannnannannnnnnannannnunnannannnannnnnann nen 92 29 Transmit CPPI Control Register TCPPICR ENEE 93 30 Transmit CPPI Teardown Register TCPPITDR cceeceeeeeeeeeeeee tease eeeee eee nannunnnnnnnnnunnnunnnnnnnn nen 93 31 CPPI DMA End of Interrupt Register CPPIEOID eee eee tent eects nannnun nun nun nannunn nun nnnnennnnn 94 32 Transmit CPPI Masked Status Register TCPPIMSKSR A 95 33 Transmit CPPI Raw Status Register TOPPIRAWSR AA 95 34 Transmit CPPI Interrupt Enable Set Register TCPPIENSETR este eee ee eeeeeeeeeeeeeeeeeeeeeeee 96 35 Transmit CPPI Interrupt Enable Clear Register TCPPIENCLDP nen 96 36 Receive CPPI Control Register DCPPICH eect eee ee eee eee eee sees eee eeeeeeeeeeeaeneeeneeeeeeaeees 97 37 Receive CPPI Masked Status Register RCPPIMSKSR seceeeeeee eect eee ence eee eee eee teen nese eeeeeeeaeeee 97 38 Receive CPPI Raw Status Register DCPPIDAWGP A 98 39 Receive CPPI Interrupt Enable Set Register
18. will be set Note DMA is not supported for endpoint 0 so the command should be read by accessing the endpoint 0 FIFO register 3 1 1 2 Write Requests Write requests involve an additional packet or packets of data being sent from the host after the 8 byte command An example of a Write standard device request is SET_DESCRIPTOR The sequence of events will begin as with all requests when the software receives an endpoint 0 interrupt The RXPKTRDY bit of PERI_CSRO will also have been set The 8 byte command should then be read from the Endpoint 0 FIFO and decoded As with a zero data request the PERI_CSRO register should then be written to set the SERV_RXPKTRDY bit bit 6 indicating that the command has been read from the FIFO but in this case the DATAEND bit bit 3 should not be set indicating that more data is expected When a second endpoint 0 interrupt is received the PERI_CSRO register should be read to check the endpoint status The RXPKTRDY bit of PERI_CSRO should be set to indicate that a data packet has been received The COUNTO register should then be read to determine the size of this data packet The data packet can then be read from the endpoint 0 FIFO SPRUGH3 November 2008 Universal Serial Bus USB Controller 27 Submit Documentation Feedback I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com If the length of the data associated with the request indicated by the wLength f
19. 110 Universal Serial Bus USB Controller Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers Table 60 Receive CPPI Completion Pointer RCPPICOMPPTR Field Descriptions continued Bit Field Value Description 0 RDBK_MODE Readback Compare Mode 0 Compare Mode Indicates that the value that is presented on bits 31 2 ofthe read data should be compared against the value that is currently contained in bits 31 2 of this location If the two match the interrupt bit corresponding to this Receive Queue should be deasserted 1 Readback Mode Indicates that the value that is presented on bits 31 2 ofthe read data should be read from this location and the interrupt for this Receive Queue should be asserted This bit is read as zero 4 45 Function Address Register FADDR The Function Address Register FADDR is shown in Figure 60 and described in Table 61 Figure 60 Function Address Register FADDR 7 6 0 Reserved FUNCADDR HO R W 0 LEGEND R W Read Write n value after reset Table 61 Function Address Register FADDR Field Descriptions Bit Field Value Description 7 Reserved 0 Reserved 6 0 FUNCADDR 0 7Fh 7 bit address of the peripheral part of the transaction When used in Peripheral mode DevCtl D2 0 this register should be written with the address received through a SET_ADDRESS command which will then be used for decoding the function address in subse
20. Control Transaction phases Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation 3 2 1 1 Setup Phase For the SETUP Phase of a control transaction Figure 9 the software driving the US host device needs to 1 Load the 8 bytes of the required Device request command into the Endpoint 0 FIFO 2 Set SETUPPKT and TXPKTRDY bits 3 and 1 of HOST_CSRO respectively Note These bits must be set together The controller then proceeds to send a SETUP token followed by the 8 byte command to Endpoint 0 of the addressed device retrying as necessary On errors controller retries the transaction three times Figure 9 Setup Phase of a Control Transaction Flow Chart Transaction scheduled TxPktRdy and SetupPkt No both set Yes SETUP token sent DATAO oacket sent Command not RxStall set supported by Stall Yes TxPktRdy cleared target received 5 Error Count cleared interrupt generated No ACK Yes TxPktRdy cleared received Error Count cleared Interrupt generated o N complete Yes NAK 2 received N o NAK limit reached No Error count cleared Yes Error count NAK Timeout set incr mented Endpoint halted Interrupt generated Implies problem Error bit set at peripheral end No Yes TxPktRdy cleared of connection Error Co
21. Controls if the Transmit CPP DMA controller is enabled Be sure to program the CPPI chain and set the DMA state words before enabling the DMA Failure to initialize the DMA before enabling could result in spurious transfers and memory corruption 0 Transmit CPPI DMA is disabled Transmit CPPI DMA is enabled 4 15 Transmit CPPI Teardown Register TCPPITDR The Transmit CPPI Teardown Register TCPPITDR is shown in Figure 30 and described in Table 31 Figure 30 Transmit CPPI Teardown Register TCPPITDR 31 30 16 READY Reserved R 1 R 0 15 2 1 0 Reserved CHANNEL HO R W 0 LEGEND R W Read Write R Read only n value after reset Table 31 Transmit CPPI Teardown Register TCPPITDR Field Descriptions Bit Field Value Description 31 READY 0 1 Indicates if the Teardown register can be written 30 2 Reserved 0 Reserved 1 0 CHANNEL 0 3h Teardown Channel Indicates the channel that is to be torn down SPRUGH3 November 2008 Universal Serial Bus USB Controller 93 Submit Documentation Feedback JA TEXAS INSTRUMENTS Registers www ti com 4 16 CPPI DMA End of Interrupt Register CPPIEOIR Note This register was previously named TCPPIEOIR and that name will continue to exist in the CSL for backward compatibility The CPPI DMA End of Interrupt Register CPPIEOIR is shown in Figure 31 and described in Table 32 Figure 31 CPPI DMA End of Interrup
22. DISNYET Ignored in isochronous transfers Bit 11 DMAMODE Always set this bit to 0 3 1 4 2 2 Operation An Isochronous endpoint does not support data retries so if a data overrun is to be avoided there must be space in the FIFO to accept a packet when it is received The host will send one packet per frame or microframe in High speed mode however the time within the frame can vary If a packet is received near the end of one frame microframe and another arrives at the start of the next frame there will be little time to unload the FIFO For this reason double buffering of the endpoint is usually necessary An interrupt is generated whenever a packet is received from the host and the software may use this interrupt to unload the packet from the FIFO and clear the RXPKTRDY bit in the PERI_RXCSR register bit 0 in the same way as for a Bulk Rx endpoint As the interrupt could occur almost any time within a frame microframe depending on when the host has scheduled the transaction the timing of FIFO unload requests will probably be irregular If the data sink for the endpoint is going to some external hardware it may be better to minimize the requirement for additional buffering by waiting until the end of each frame microframe before unloading the FIFO This can be done by using either the SOF interrupt or the external SOF_PULSE signal from the controller to trigger the unloading of the data packet The SOF_PULSE is generated once per fra
23. ERROR bit of HOST_RXCSR bit 2 The controller then generates the appropriate endpoint interrupt whereupon the software should read the corresponding HOST_RXCSR register to determine whether the RXPKTRDY RXSTALL ERROR or DATAERR_NAKTIMEOUT bit is set and act accordingly If the DATAERR_NAKTIMEOUT bit is set the controller can be directed either to continue trying this transaction until it times out again by clearing the DATAERR_NAKTIMEOUT bit or to abort the transaction by clearing REQPKT bit before clearing the DATAERR_NAKTIMEOUT bit The packets received should not exceed the size specified in the RXMAXP register as this should be the value set in the wMaxPacketSize field of the endpoint descriptor sent to the host In the general case the application software will need to read each packet from the FIFO individually If large blocks of data are being transferred the overhead of calling an interrupt service routine to unload each packet can be avoided by using DMA 3 2 2 1 3 Error Handling If the target wants to shut down the Bulk IN pipe it will send a STALL response to the IN token This will result in the RXSTALL bit of HOST_RXCSR bit 6 being set 3 2 2 2 Bulk OUT Transactions A Bulk OUT transaction may be used to transfer non periodic data from the host to the USB peripheral Following optional features are available for use with a Tx endpoint used in Host mode to transmit this data e Double packet buffering When enabled
24. Endpoint 4 0 Tx endpoint ready or error condition For endpoints 4 to 0 Rx and Tx for endpoint 0 Rx Endpoint 4 1 Rx endpoint ready or error condition For endpoints 4 to 1 Endpoint 0 has interrupt status in Tx interrupt USB Core 8 0 Interrupts for 9 USB conditions DMA Tx Completion 3 0 Tx DMA completion interrupt for channel 3 to 0 DMA Rx Completion 3 0 Rx DMA completion interrupt for channel 3 to 0 Whenever any of these interrupt conditions are generated the host processor is interrupted The software needs to read the different interrupt status registers discussed in later section to determine the source of the interrupt The nine USB interrupt conditions are listed in Table 15 Table 15 USB Interrupt Conditions Interrupt Description USBJ 8 DRVVBUS level change USB 7 VBus voltage lt VBus Valid Threshold VBus error USB 6 SRP detected USB 5 Device Disconnected Valid in Host Mode USB 4 Device Connected Valid in Host Mode Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation Table 15 USB Interrupt Conditions continued Interrupt Description USB 3 SOF started USB 2 Reset Signaling detected In Peripheral Mode Babble detected In Host Mode USB 1 Resume signaling detected USB 0 Suspend Signaling detected SPRUGH3 November 2008 Universal Serial Bus USB
25. HOGT TSTWPE N eee eeeeeeeeeeeeeeeeeeeeeeees 129 83 NAKLimitO Register Host mode only HOST NARKUIMITO eee eeeeeeee eee nnnnnn nun nennen 130 84 Transmit Interval Register Host mode only HOST TXINTEDRWNAL nun nen nun nun 130 85 Receive Type Register Host mode only HOST_RXTYPE 0sceeeeeeeee eee e eee ee eee nun nun nun nun nun une nn 131 86 Receive Interval Register Host mode only HOST_RXINTERVAL eee eeeeneeeeeeeeeeeeeeee 131 87 Configuration Data Register CONFIGDATAN cent cece eee eee e eee e eee ee ee ne snes eee eae nennnnnnun nennen 132 88 Transmit and Receive FIFO Register for Endpoint 0 FIFOO zursuusunnennennnunnnnnannnnnnnnnnnn nun ann nun 134 89 Transmit and Receive FIFO Register for Endpoint 1 FIFO1 eceeceeeeeeeeee ence eee eeeeeeeeeeeeeeeeeeeeeeees 135 90 Transmit and Receive FIFO Register for Endpoint 2 FIFO2 ccscceeeeeeeeeeeee eee eeeeeeeeeeeeeeeeeneeeeees 135 91 Transmit and Receive FIFO Register for Endpoint 3 FIFO3 ccccceeeeeeeeeeeee eset eeeeeeeeeeeeeeeeeeeeeeees 136 92 Transmit and Receive FIFO Register for Endpoint 4 FIFO4 zuzurunnsunnennannnunnnnnannnunnnnnnnn nenne nun nun 136 93 OTG Device Control Register DEVOTE u a ee a ea 137 94 Transmit Endpoint FIFO Size TXFIFOSZ u uu0 pea a nie 138 95 Receive Endpoint FIFO Size RXFIFOSZ EEN 138 96 Transmit Endpoint FIFO Address CT SEIEOADDD nun nun nen nun nnunnnnnunnnunnnnnnnn nenn nun 139 97 Receive Endpoint FIFO Ad
26. Mode Bulk OUT Transactions 38 A Bulk OUT transaction is used to transfer non periodic data from the host to the function controller The following optional features are available for use with an Rx endpoint used in peripheral mode for Bulk OUT transactions e Double packet buffering When enabled up to two packets can be stored in the FIFO on reception from the host Double packet buffering is enabled by setting the DPB bit of the RXFIFOSZ register bit 4 e DMA If DMA is enabled for the endpoint a DMA request will be generated whenever the endpoint has a packet in its FIFO This feature can be used to allow the DMA controller to unload packets from the FIFO without processor intervention When DMA is enabled endpoint interrupt will not be generated for completion of packet reception Endpoint interrupt will be generated only in the error conditions Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation 3 1 2 2 1 Setup In configuring an Rx endpoint for Bulk OUT transactions the RXMAXP register must be written with the maximum packet size in bytes for the endpoint This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the endpoint In addition the relevant interrupt enable bit in the INTRRXE register should be set if an interrupt is required for this endpoint an
27. November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 81 Transmit Endpoint FIFO Address TXFIFOADDR Section 2 5 describes dynamically setting endpoint FIFO sizes The Transmit Endpoint FIFO Address TXFIFOADDR is shown in Figure 96 and described in Table 97 Figure 96 Transmit Endpoint FIFO Address TXFIFOADDR 15 13 12 ADDR Reserved HO R W 0 LEGEND R W Read Write R Read only n value after reset Table 97 Transmit Endpoint FIFO Address TXFIFOADDR Field Descriptions Bit Field Value Description 15 13 Reserved 0 Reserved 12 0 ADDR 0 1FFFh Start Address of endpoint FIFO in units of 8 bytes If m ADDR 12 0 then the start address is 8 m 4 82 Receive Endpoint FIFO Address RXFIFOADDR Section 2 5 describes dynamically setting endpoint FIFO sizes The Receive Endpoint FIFO Address RXFIFOADDR is shown in Figure 97 and described in Table 98 Figure 97 Receive Endpoint FIFO Address RXFIFOADDR 15 13 12 ADDR Reserved HO R W 0 LEGEND R W Read Write R Read only n value after reset Table 98 Receive Endpoint FIFO Address RXFIFOADDR Field Descriptions Bit Field Value Description 15 13 Reserved 0 Reserved 12 0 ADDR 0 1FFFh Start Address of endpoint FIFO in units of 8 bytes If m ADDR 12 0 then the start address is 8 m SPRUGH3 November 2008 Universal Serial
28. Register RCPPICR Field DescriptionS nennen nn nn nun nenn nn nnnnn nen 97 38 Receive CPPI Masked Status Register RCPPIMSKSR Field Descriptions nn nen 97 39 Receive CPPI Raw Status Register RCPPIRAWSR Field Descriptions ur4zus40sn0nnnnnan nn ann nn nen 98 40 Receive CPPI Interrupt Enable Set Register RCPPIENSETR Field Descriptions 0 seeeeeeeeeeeeeeeees 98 41 Receive CPPI Interrupt Enable Clear Register RCPPIIENCLRR Field Description 99 42 Receive Buffer Count 0 Register RBUFCNTO Field Descriptions anne nen 99 43 Receive Buffer Count 1 Register RBUFCNT1 Field Descriptions ceeceeeeeeeeee aan nn nun nun nun 100 44 Receive Buffer Count 2 Register RBUFCNT2 Field Descriptions eceeeeeeeeeeeee nenn nun nenn nennen 100 45 Receive Buffer Count 3 Register RBUFCNT3 Field Descriptions eceeeeeeeeeeeee nennen nn nun nun nun 101 46 Transmit CPPI DMA State Word 0 TCPPIDMASTATEWO Field Descripttons nennen nenn 101 47 Transmit CPPI DMA State Word 1 TCPPIDMASTATEWI Field Descripttons nen nn an nn 102 48 Transmit CPPI DMA State Word 2 TCPPIDMASTATEW2 Field Descripttons nen nn nn nn 102 49 Transmit CPPI DMA State Word 3 TCPPIDMASTATEWS3 Field Descripttons nen nn anne 103 List of Tables SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com 50 Transmit CPPI DMA State Word 4 TCPPIDMASTATEW4 Field Descripttons nenn nen nn 103 51 Transmit CPPI DMA S
29. USB Interrupt Source Masked Register Section 4 11 3Ch EOIR USB End of Interrupt Register Section 4 12 40h INTVECTR USB Interrupt Vector Register Section 4 13 80h TCPPICR Transmit CPPI Control Register Section 4 14 84h TCPPITDR Transmit CPPI Teardown Register Section 4 15 88h CPPIEOIR CPPI DMA End of Interrupt Register Section 4 16 90h TCPPIMSKSR Transmit CPPI Masked Status Register Section 4 17 94h TCPPIRAWSR Transmit CPPI Raw Status Register Section 4 18 98h TCPPIIENSETR Transmit CPPI Interrupt Enable Set Register Section 4 19 9Ch TCPPIIENCLRR Transmit CPPI Interrupt Enable Clear Register Section 4 20 Coh RCPPICR Receive CPPI Control Register Section 4 21 DOh RCPPIMSKSR Receive CPPI Masked Status Register Section 4 22 D4h RCPPIRAWSR Receive CPPI Raw Status Register Section 4 23 D8h RCPPIENSETR Receive CPPI Interrupt Enable Set Register Section 4 24 DCh RCPPIIENCLRR Receive CPPI Interrupt Enable Clear Register Section 4 25 EOh RBUFCNTO Receive Buffer Count 0 Register Section 4 26 E4h RBUFCNT1 Receive Buffer Count 1 Register Section 4 27 E8h RBUFCNT2 Receive Buffer Count 2 Register Section 4 28 ECh RBUFCNT3 Receive Buffer Count 3 Register Section 4 29 Transmit Receive CPPI Channel 0 State Block 100h TCPPIDMASTATEWO Transmit CPPI DMA State Word 0 Section 4 30 104h TCPPIDMASTATEW1 Transmit CPPI DMA State Word 1 Section 4 31 108h TCPPIDMASTATEW2 Transmit CPPI DMA State Word 2 Section 4 32 10Ch TCPPIDMASTATEW3 Transmit CPPI DMA State Word 3 Section 4 33 11
30. VBUS 0 3h These read only bits encode the current VBus level as follows 0 Below Session End th Above Session End below AValid 2h Above AValid below VBusValid 3h Above VBusValid 2 HOSTMODE 0 1 This read only bit is set when the USB controller is acting as a Host 1 HOSTREQ 0 1 When set the USB controller will initiate the Host Negotiation when Suspend mode is entered It is cleared when Host Negotiation is completed B device only 0 SESSION 0 1 When operating as an A device you must set or clear this bit start or end a session When operating as a B device this bit is set cleared by the USB controller when a session starts ends You must also set this bit to initiate the Session Request Protocol When the USB controller is in Suspend mode you may clear the bit to perform a software disconnect A special software routine is required to perform SRP Details will be made available in a later document version SPRUGH3 November 2008 Universal Serial Bus USB Controller 137 Submit Documentation Feedback JA TEXAS INSTRUMENTS Registers www ti com 4 79 Transmit Endpoint FIFO Size TXFIFOSZ Section 2 5 describes dynamically setting endpoint FIFO sizes The Transmit Endpoint FIFO Size TXFIFOSZ is shown in Figure 94 and described in Table 95 Figure 94 Transmit Endpoint FIFO Size TXFIFOSZ 7 5 4 3 0 Reserved DPB SZ HO R W 0 HO LEGEND R W Read Write R Read only n
31. W Read Write n value after reset Table 68 Interrupt Enable Register for INTRUSB INTRUSBE Field Descriptions Bit Field Value Description 7 VBUSERR 0 1 Vbus error interrupt enable 6 SESSREQ 0 1 Session request interrupt enable 5 DISCON 0 1 Disconnect interrupt enable 4 CONN 0 1 Connect interrupt enable 3 SOF 0 1 Start of frame interrupt enable 2 RESET_BABBLE 0 1 Reset interrupt enable 1 RESUME 0 1 Resume interrupt enable 0 SUSPEND 0 1 Suspend interrupt enable 116 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 53 Frame Number Register FRAME The Frame Number Register FRAME is shown in Figure 68 and described in Table 69 Figure 68 Frame Number Register FRAME 15 11 10 0 Reserved FRAMENUMBER R 0 R 0 LEGEND R Read only n value after reset Table 69 Frame Number Register FRAME Field Descriptions Bit Field Value Description 15 11 Reserved 0 Reserved 10 0 FRAMENUMBER 0 7FFh Last received frame number 4 54 Index Register for Selecting the Endpoint Status and Control Registers INDEX The Index Register for Selecting the Endpoint Status and Control Registers INDEX is shown in Figure 69 and described in Table 70 Figure 69 Index Register for Selecting the Endpoint Status and Control Registers INDEX 7 4 3 0 Reserved EPSEL HO R
32. W 0 LEGEND R W Read Write R Read only n value after reset Table 70 Index Register for Selecting the Endpoint Status and Control Registers INDEX Field Descriptions Bit Field Value Description 7 4 Reserved 0 Reserved 3 0 EPSEL 0 Fh Each transmit endpoint and each receive endpoint have their own set of control status registers EPSEL determines which endpoint control status registers are accessed Before accessing an endpoint s control status registers the endpoint number should be written to the Index register to ensure that the correct control status registers appear in the memory map SPRUGH3 November 2008 Universal Serial Bus USB Controller 117 Submit Documentation Feedback I TEXAS INSTRUMENTS Registers www ti com 4 55 Register to Enable the USB 2 0 Test Modes TESTMODE The Register to Enable the USB 2 0 Test Modes TESTMODE is shown in Figure 70 and described in Table 71 Figure 70 Register to Enable the USB 2 0 Test Modes TESTMODE 7 6 5 4 3 2 1 0 FORCE_HOST FIFO_ACCESS FORCE_FS FORCE_HS TEST_PACKET TEST_K TEST_J TEST_SEO_NAK R W 0 W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write W Write only n value after reset Table 71 Register to Enable the USB 2 0 Test Modes TESTMODE Field Descriptions Bit Field Value 7 FORCE_HOST 0 1 Description Set this bit to forcibly put the USB controlle
33. acknowledge completion of an interrupt by writing to the EOI An eoi_write signal will be generated the EOI vector will be updated to the written value and another interrupt will be triggered if interrupt sources remain Software should always write zeros for the EOI vector value 4 13 USB Interrupt Vector Register INTVECTR The USB Interrupt Vector Register INTVECTR is shown in Figure 28 and described in Table 29 Figure 28 USB Interrupt Vector Register INTVECTR 31 0 VECTOR HO LEGEND R Read only n value after reset Table 29 USB Interrupt Vector Register INTVECTR Field Descriptions Bit Field Value Description 31 0 VECTOR 0 FFFF FFFFh Input Interrupt Vector Recycles the Interrupt Vector input to be read by the CPU 92 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 14 Transmit CPPI Control Register TCPPICR The Transmit CPPI Control Register TCPPICR is shown in Figure 29 and described in Table 30 Figure 29 Transmit CPPI Control Register TCPPICR 31 16 Reserved R 0 15 1 0 Reserved TCPPI_ENABLE R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 30 Transmit CPPI Control Register TCPPICR Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 TCPPI_ENABLE Transmit CPPI Enable
34. and described in Table 59 Figure 58 Receive CPPI DMA State Word 6 RCPPIDMASTATEW6 31 16 SOP_BUFFER_BYTECNT R W 0 15 0 CURR_BUFFER_BYTECNT R W 0 LEGEND R W Read Write n value after reset Table 59 Receive CPPI DMA State Word 6 RCPPIDMASTATEW6 Field Descriptions Bit Field Value Description 31 16 SOP_BUFFER_BYTECNT 0 FFFFh Packet Length Indicates how many bytes are contained in the packet This value is written into bits 15 0 of Word 3 of the SOP Descriptor during end of packet processing 15 0 CURR_BUFFER_BYTECNT 0 FFFFh Current Buffer Length Indicates how many free bytes remain in the current buffer that is being received into 4 44 Receive CPPI Completion Pointer RCPPICOMPPTR The Receive CPPI Completion Pointer RCPPICOMPPTR is shown in Figure 59 and described in Table 60 Figure 59 Receive CPPI Completion Pointer RCPPICOMPPTR 31 16 DESC_ADDR R W 0 15 2 1 0 DESC_ADDR Reserved RDBK_MODE R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 60 Receive CPPI Completion Pointer RCPPICOMPPTR Field Descriptions Bit Field Value Description 31 2 DESC_ADDR 0 7FFF FFFFh Descriptor Address This field contains the 30 bit word aligned pointer of the end of packet descriptor that the DMA has last processed 1 Reserved 0 Reserved SPRUGH3 November 2008
35. be connected via 1 uF capacitor to USB_Vppaipetpo II I Input O Output Z High impedance S Supply voltage GND Ground A Analog signal 2 3 Indexed and Non Indexed Registers USB controller provides two mechanism of accessing the endpoint control and status registers e Indexed Endpoint Control Status Registers These registers are memory mapped at offset 410h to 41Fh The endpoint is selected by programming the INDEX register of the controller e Non indexed Endpoint Control Status Registers These registers are memory mapped at offset 500h to 54Fh Registers at offset 500h 50Fh map to Endpoint 0 offset 510h 51Fh map to Endpoint 1 and so on For detailed information about the USB controller registers see Section 4 SPRUGH3 November 2008 Universal Serial Bus USB Controller 23 Submit Documentation Feedback JA TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com 2 4 2 5 24 USB PHY Initialization The following bits in USBPHY_CTL must be cleared to enable the USB controller OSCPDWN and PHYPDWN The following bits in USBPHY_CTL must be set to enable the level comparators VBDTCTEN and VBUSENS After this configuration is in place wait until the PLL clock is good prior to continuing i e wait until USBPHY_CTL PHYCLKGD bit is set Dynamic FIFO Sizing The USB controller supports a total of 4K RAM to dynamically allocate FIFO to all endpoints The allocation of FIFO space to the dif
36. buffer is a contiguous block of memory used to store received data Each Rx buffer has a corresponding Rx buffer descriptor Each Rx buffer can be linked together with other Rx buffers to make a DMA packet or a queue of DMA packets Receive buffers are byte aligned structures located in processor s main memory Rx buffer size may vary from 1 to 65 535 bytes Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation 3 3 2 2 CPPI Receive Buffer Descriptor Rx buffer descriptors provide information about a single corresponding Rx data buffer Every Rx buffer has a single Rx buffer descriptor that stores the following information e Pointer to the data buffer e Pointer to the next buffer descriptor in the queue e Buffer length and offset to the first valid byte of buffer data e Start of DMA packet SOP indicator e End of DMA packet EOP indicator e Ownership only valid with SOP e End of queue EOQ only valid on EOP e Packet Length only valid with SOP Receive buffer descriptors contain 16 bytes 4 words and must begin on 16 byte aligned addresses Receive buffer descriptors may be linked together to form packets Buffer descriptor SOP and EOP bits are used to delimit packets Packets in turn may be linked together to form receive queue Each queue consists of a chain of buffer descriptors linked together by
37. count incremented SPRUGH3 November 2008 Submit Documentation Feedback lt gt 5 RxStall set RegPkt cleared Error Count cleared Interrupt generated ACK sent RxPktRdy Error bit set RegPkt cleared Error Count cleared Interrupt generated Universal Serial Bus USB Controller RegPkt cleared Error Count cleared set Interrupt generated Transaction complete Command could not be completed Implies problem at peripheral end of connection Transaction deemed complete 49 JA TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com 3 4 3 2 1 5 For the OUT Status Phase of a control transaction Figure 13 the CPU driving the host device needs to 50 1 When the controller generates the Endpoint 0 interrupt read HOST_CSRO to establish whether the RXSTALL bit bit 2 the ERROR bit bit 4 the NAK_TIMEOUT bit bit 7 or RXPKTRDY bit bit 0 has been set If RXSTALL bit is set it indicates that the target could not complete the command and so has issued a STALL response If ERROR bit is set it means that the controller has tried to send the required IN token three times without getting any response If NAK_TIMEOUT bit is set it means that the controller has received a NAK response to each attempt to send the IN token for longer than the time set in the HOST_NAKLIMITO register The controller can then be directed either to continue trying this transact
38. disable interrupt sources appearing as masked interrupts 88 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com 4 9 USB Interrupt Mask Set Register INTMSKSETR Registers The USB Interrupt Mask Set Register INTMSKSETR is shown in Figure 24 and described in Table 25 Figure 24 USB Interrupt Mask Set Register INTMSKSETR 31 25 24 16 Reserved USB R 0 WO 15 13 12 8 7 5 4 0 Reserved RX Reserved TX R 0 W 0 R 0 W 0 LEGEND R Read only W Write only n value after reset Table 25 USB Interrupt Mask Set Register INTMSKSETR Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 16 USB 0 1FFh Write a 1 to set equivalent USB interrupt mask Allows the USB interrupt masks to be individually enabled 15 13 Reserved 0 Reserved 12 8 RX 0 1Fh Write a 1 to set equivalent Receive endpoint interrupt mask Allows the USB interrupt masks to be individually enabled 7 5 Reserved 0 Reserved 4 0 TX 0 Fh Write a1 to set equivalent Transmit endpoint interrupt mask Allows the USB interrupt masks to be individually enabled SPRUGH3 November 2008 Universal Serial Bus USB Controller 89 Submit Documentation Feedback I TEXAS INSTRUMENTS Registers www ti com 4 10 USB Interrupt Mask Clear Register INTMSKCLRR The USB Interrupt Mask Clear Regis
39. mask bits SPRUGH3 November 2008 Universal Serial Bus USB Controller 97 Submit Documentation Feedback JA TEXAS INSTRUMENTS Registers www ti com 4 23 Receive CPPI Raw Status Register RCPPIRAWSR The Receive CPPI Raw Status Register RCPPIRAWSR is shown in Figure 38 and described in Table 39 Figure 38 Receive CPPI Raw Status Register RCPPIRAWSR 31 16 Reserved HO 15 4 3 0 Reserved COMP_PENDING R 0 R 0 LEGEND R Read only n value after reset Table 39 Receive CPPI Raw Status Register RCPPIRAWSR Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 0 COMP_PENDING 0 Fh Raw Receive Completion Pending nn for channels 3 to 0 Active high flags which indicate that a packet has completed reception 4 24 Receive CPPI Interrupt Enable Set Register RCPPIENSETR The Receive CPPI Interrupt Enable Set Register RCPPIENSETR is shown in Figure 39 and described in Table 40 Figure 39 Receive CPPI Interrupt Enable Set Register RCPPIENSETR 31 16 Reserved R 0 15 4 3 0 Reserved COMP_PENDING_INTR_EN R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 40 Receive CPPI Interrupt Enable Set Register RCPPIENSETR Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 0 COMP_PENDING_INTR_EN DEN Receive CPPI Interrupt Enables T
40. of the target function that has to be accessed Section 4 83 through the associated Transmit Endpoint 482h TXHUBADDR Address of the hub that has to be accessed through the Section 4 84 associated Transmit Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub 483h TXHUBPORT Port of the hub that has to be accessed through the Section 4 85 associated Transmit Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub 484h RXFUNCADDR Address of the target function that has to be accessed Section 4 86 through the associated Receive Endpoint 486h RXHUBADDR Address of the hub that has to be accessed through the Section 4 87 associated Receive Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub 487h RXHUBPORT Port of the hub that has to be accessed through the Section 4 88 associated Receive Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub 78 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback JA TEXAS INSTRUMENTS www ti com Registers Table 16 Universal Serial Bus USB Registers continued Offset Acronym Register Description Section Target Endpoint 1 Control Registers Valid Only in Host Mode 488h TXFUNCADDR Address of the target function that has to be accessed Section 4 83 through
41. only n value after reset Table 27 USB Interrupt Source Masked Register INTMASKEDR Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 16 USB 0 1FFh USB interrupt sources masked Contains the status of the interrupt sources generated by the USB core masked by the USB Interrupt Mask Register values 15 13 Reserved 0 Reserved 12 8 RX 0 1Fh Receive endpoint interrupt sources masked Contains the status of the interrupt sources generated by the USB core masked by the USB Interrupt Mask Register values 7 5 Reserved 0 Reserved 4 0 TX 0 Fh Transmit endpoint interrupt sources masked Contains the status of the interrupt sources generated by the USB core masked by the USB Interrupt Mask Register values SPRUGH3 November 2008 Universal Serial Bus USB Controller 91 Submit Documentation Feedback I TEXAS INSTRUMENTS Registers www ti com 4 12 USB End of Interrupt Register EOIR The USB End of Interrupt Register EOIR is shown in Figure 27 and described in Table 28 Figure 27 USB End of Interrupt Register EOIR 31 16 Reserved R 0 15 8 7 0 Reserved VECTOR R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 28 USB End of Interrupt Register EOIR Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 VECTOR 0 FFh EOI Vector Allows the CPU to
42. phase and if so the direction of the data phase of the control transfer in order to set the FIFO direction See Figure 3 Depending on the direction of the data phase endpoint 0 goes into either TX state or RX state If there is no Data phase endpoint 0 remains in IDLE state to accept the next device request The actions that the CPU needs to take at the different phases of the possible transfers e g loading the FIFO setting TXPKTRDY are indicated in Figure 4 Note The controller changes the FIFO direction depending on the direction of the data phase independently of the CPU Figure 3 CPU Actions at Transfer Phases es Sequence 3 Sequence 1 Sequence 2 Tx state Rx state SPRUGH3 November 2008 Universal Serial Bus USB Controller 29 Submit Documentation Feedback I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com Figure 4 Sequence of Transfer i Idle pid TX state pid Idle Status phase zz OUT A Unload device tt Load FIFO L Load FIFO Load FIFO and CPU actions req and clear and set and set set TxPktRdy RxPktRdy TxPktRdy TxPktRdy and set DataEnd T Idle pid RX state pid Idle Sequence 2 Setup Int OUT data OUT data OUT data Status phase Int phase phase phase IN A t Unload Unload FIFO t Unload FIFO t Unload FIFO and CPU actions device req and cle
43. programmed with a queue of n DMA packets Transparent mode must be used whenever USB MaxPktSize for the endpoint is not a multiple of 64 bytes RNDIS mode DMA is used to transmit DMA packets which are larger than USB MaxPktSize This is accomplished by breaking the larger packet into smaller packets not larger than USB MaxPktSize This implies that the data to be transmitted will be sent over USB in multiple packets of MaxPktSize and the Tx DMA interrupt for the channel is generated after the transmission of complete DMA packet This mode of DMA is used for RNDIS type transfers over USB The protocol defines the end of the complete transfer by sending a short USB packet smaller than USB MaxPktSize as mentioned in USB specification 2 0 If the DMA packet size is an exact multiple of USB MaxPktSize the DMA controller sends a zero byte packet at the end of complete transfer to signify the completion of the transfer RNDIS Mode DMA is supported only when USB MaxPktSize and the associated FIFO size is an integral multiple of 64 bytes SPRUGH3 November 2008 Universal Serial Bus USB Controller 61 Submit Documentation Feedback I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com RNDIS Mode Setup The setup of RNDIS mode DMA is similar to the default Transparent Mode as mentioned in the previous section The following steps need to be taken for setting up RNDIS mode Tx DMA e After reset the software must wr
44. provided for each of the operational modes of the controller User Case 1 An example of how to initialize the USB controller Example 1 Initializing the USB Controller void usb_init local loop variable int vbu usb sys C usb GEN usb usb for I VBUS must be controlled externally should perform whatever actions are required turn off VBUS in the system s_off Reset the USB controller Regs gt CTRLR 0x00000001 Power on PHY and oscillator by clearing bits 2 Regs gt USB_PHY_CTRL 0x000000D0 lear all pending interrupts Regs gt INTCLRR usbRegs gt INTSRCR Initialize CPPI DMA Regs gt RCPPICR 0 Disable the RX Regs gt TCPPICR 0 Disable the TX Initialize CPPI DMA state I 0 i lt 4 I usbRegs gt CHANNEL i TCPPIDMASTAT usbRegs gt CHANNEL i TCPPIDMASTAT usbRegs gt CHANNEL i TCPPIDMASTATE usbRegs gt CHANNEL i TCPPIDMASTATE usbRegs gt CHANNEL i TCPPIDMASTATE usbRegs gt CHANNEL i TCPPIDMASTATE usbRegs gt CHANNEL i RCPPIDMASTATE usbRegs gt CHANNEL i RCPPIDMASTAT usbRegs gt CHANNEL i RCPPIDMASTA usbRegs gt CHANNEL i RCPPIDMASTA usbRegs gt CHANNEL i RCPPIDMASTATE usbRegs gt CHANNEL i RCPPIDMASTATE usbRegs gt CHANNEL i RCPPIDMASTATE Routine to initialize USB controller The following routine if any to 1
45. queue of DMA packets Transmit buffers are byte aligned structures located in processor s main memory Tx buffer size may vary from 1 to 65 535 bytes 3 3 1 2 CPPI Transmit Buffer Descriptor Tx buffer descriptors provide information about a single corresponding Tx data buffer Every Tx buffer has a single Tx buffer descriptor that stores the following information e Pointer to the data buffer e Pointer to the next buffer descriptor in the queue e Buffer length and offset to the first valid byte of buffer data e Start of DMA packet SOP indicator e End of DMA packet EOP indicator e Ownership only valid with SOP SPRUGH3 November 2008 Universal Serial Bus USB Controller 57 Submit Documentation Feedback JA TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com e End of queue EOQ only valid on EOP e Packet Length only valid with SOP Transmit buffer descriptors contain 16 bytes 4 words and must begin on 16 byte aligned addresses Transmit buffer descriptors may be linked together to form packets Buffer descriptor SOP and EOP bits are used to delimit packets Packets in turn may be linked together to form transmit queue Each queue consists of a chain of buffer descriptors linked together by Next Descriptor Pointers The last buffer descriptor in a queue has a zero Next Descriptor Pointer Each descriptor points to a data buffer yielding a queue of buffers 58 Four Words of Transmit Buffer Descri
46. register as this should be the value set in the wMaxPacketSize field of the endpoint descriptor sent to the host When a block of data larger than wMaxPacketSize needs to be sent to the function it will be sent as multiple packets All the packets will be wMaxPacketSize in size except the last packet which will contain the residue The software may use an application specific method of determining the total size of the block and hence when the last packet has been received Alternatively it may infer that the entire block has been received when it receives a packet which is less than wMaxPacketSize in size If the total size of the data block is a multiple of wMaxPacketSize a null data packet will be sent after the data to signify that the transfer is complete In the general case the application software will need to read each packet from the FIFO individually If large blocks of data are being transferred the overhead of calling an interrupt service routine to unload each packet can be avoided by using DMA SPRUGH3 November 2008 Universal Serial Bus USB Controller 39 Submit Documentation Feedback I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com 3 1 2 2 3 Error Handling 40 If the software wants to shut down the Bulk OUT pipe it should set the SENDSTALL bit bit 5 of PERI_RXCSR When the controller receives the next packet it will send a STALL to the host set the SENTSTALL bit bit 6 of PERI_R
47. setting the SERV_RXPKTRDY bit of PERI_CSRO bit 6 When the software detects the termination of a transfer by receiving either the expected amount of data or an empty data packet it should set the DATAEND bit bit 3 of PERI_CSRO to indicate to the controller that the data phase is complete and that the core should receive an acknowledge packet next Figure 8 RX Mode Flow Chart RxPktRdy set Yes Read CountO register n Unload n bytes from FIFO Last packet Yes Set ServicedRxPktRdy and DataEnd state gt IDLE Set ServicedRxPktRdy SPRUGH3 November 2008 Universal Serial Bus USB Controller 35 Submit Documentation Feedback I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com 3 1 1 5 4 Error Handling A control transfer may be aborted due to a protocol error on the USB the host prematurely ending the transfer or if the software wishes to abort the transfer e g because it cannot process the command The controller automatically detects protocol errors and sends a STALL packet to the host under the following conditions e The host sends more data during the OUT Data phase of a write request than was specified in the command This condition is detected when the host sends an OUT token after the DATAEND bit bit 3 of PERI_CSRO has been set e The host requests more data during the IN Data phase of a read request than was specified in the command This co
48. should be written to the FADDR register The PERI_CSRO register should then be written to set the SERV_RXPKTRDY bit bit 6 indicating that the command has been read from the FIFO and to set the DATAEND bit bit 3 indicating that no further data is expected for this request The interval between setting SERV_RXPKTRDY bit and DATAEND bit should be very small to avoid getting a SetupEnd error condition When the host moves to the status stage of the request a second endpoint 0 interrupt will be generated to indicate that the request has completed No further action is required from the software The second interrupt is just a confirmation that the request completed successfully For SET ADDRESS command the address should be set in FADDR register only after the status stage interrupt is received If the command is an unrecognized command or for some other reason cannot be executed then when it has been decoded the PERI_CSRO register should be written to set the SERV_RXPKTRDY bit bit 6 and to set the SENDSTALL bit bit 5 When the host moves to the status stage of the request the controller will send a STALL to tell the host that the request was not executed A second endpoint 0 interrupt will be generated and the SENTSTALL bit bit 2 of PERI_CSRO will be set If the host sends more data after the DATAEND bit has been set then the controller will send a STALL An endpoint 0 interrupt will be generated and the SENTSTALL bit bit 2 of PERI_CSRO
49. shows the USB port pins used in each mode Table 1 USB Pins Pin Type Function M24xl l Crystal input for M24 oscillator 24 MHZ for USB M24X0 O Crystal output for M24 oscillator M24Vpp S 1 8V power supply for M24 oscillator M24Vss Ground for M24 oscillator PLLVpp18 GND 1 8 Volt power supply for PLLs system and USB USB_VBUS VO 5V input that signifies that VBUS is connected The OTG section of the PHY can also pull up or down on this signal for HNP and SRP USB_ID VO USB_ID is an input that is open or pulled to ground depending on OTG connector configuration The state determines if controller starts in HOST or PERIPHERAL mode USB_DP VO USB bi directional Data Differential signal pair positive negative Input output DP signal of the differential signal pair USB_DM VO USB bi directional Data Differential signal pair positive negative Input output DM signal of the differential signal pair USB_R1 VO Reference current output This must be connected via a 10 kQ 1 resistor to USB_Vssrer USB_Vssrer GND Ground for reference current USB_Vppas3p3 S Analog 3 3 V power supply for USB phy USB_Vsga3p3 GND Analog ground for USB phy USB_Vpp1ps3 S 1 8 V I O power supply for USB phy USB_Vss ps GND WO Ground for USB phy USB_VppaiP2LDo S Core Power supply LDO output for USB phy This must be connected via 1 uF capacitor to USB_Vssaip2_po Do not connect this to other supply pins USB_Vssaip2_p0 GND Core Ground for USB phy This must
50. supports programmable FIFO sizes e External 5V power supply for VBUS can be controlled through 12C e Includes a DMA controller that supports four TX and four RX DMA channels e Includes RNDIS mode of DMA for accelerating RNDIS type protocols using short packet termination over USB Features Not Supported The following features are not supported e High Bandwidth Isochronous Transfer e High Bandwidth Interrupt Transfer e Automatic Amalgamation of Bulk Packets CPPI DMA will indirectly handle this feature and is not supported at the core level e Automatic Splitting of Bulk Packets CPPI DMA will indirectly handle this feature and is not supported at the core level Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Introduction 1 4 Functional Block Diagram The USB functional block diagram is shown in Figure 1 Figure 1 Functional Block Diagram Internal bus CPPI Packet DMA encode engine decode Registers interrupts endpoint control and packet scheduling crystal oscillator SPRUGH3 November 2008 Universal Serial Bus USB Controller 15 Submit Documentation Feedback Introduction 1 5 Supported Use Case Examples The USB supports the following user cases 16 JA TEXAS INSTRUMENTS www ti com Detailed information about the architecture and operation of the USB controller follows in Section 2 Programming examples are also
51. the Standard Endpoint Descriptor for the target endpoint SPRUGH3 November 2008 Universal Serial Bus USB Controller 53 Submit Documentation Feedback I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com e The HOST_TXINTERVAL register needs to be written with the required value for the NAK limit 2 215 frames microframes or cleared to 0 if the NAK timeout feature is not required e The relevant interrupt enable bit in the INTRTXE register should be set if an interrupt is required for this endpoint e The following bits of HOST_TXCSR register should be set as shown below Set the MODE bit bit 13 to 1 to ensure the FIFO is enabled only necessary if the FIFO is shared with an Rx endpoint Set the DMAEN bit bit 12 to 1 if a DMA request is required for this endpoint Clear the FRCDATATOG bit bit 11 to 0 to allow normal data toggle operations Set the DMAMODE bit bit 10 to 1 when DMA is enabled and the endpoint interrupt is not needed for each packet transmission When the endpoint is first configured the endpoint data toggle should be cleared to 0 either by using the DATATOGWREN bit and DATATOG bit of HOST_TXCSR bit 9 and bit 8 to toggle the current setting or by setting the CLRDATATOG bit of HOST_TXCSR bit 6 This will ensure that the data toggle which is handled automatically by the controller starts in the correct state Also if there are any data packets in the FIFO indi
52. the associated Transmit Endpoint 48Ah TXHUBADDR Address of the hub that has to be accessed through the Section 4 84 associated Transmit Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub 48Bh TXHUBPORT Port of the hub that has to be accessed through the Section 4 85 associated Transmit Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub 48Ch RXFUNCADDR Address of the target function that has to be accessed Section 4 86 through the associated Receive Endpoint 48Eh RXHUBADDR Address of the hub that has to be accessed through the Section 4 87 associated Receive Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub 48Fh RXHUBPORT Port of the hub that has to be accessed through the Section 4 88 associated Receive Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub Target Endpoint 2 Control Registers Valid Only in Host Mode 490h TXFUNCADDR Address of the target function that has to be accessed Section 4 83 through the associated Transmit Endpoint 492h TXHUBADDR Address of the hub that has to be accessed through the Section 4 84 associated Transmit Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub 493h TXHUBPORT Port of the hub that has to be accessed through the Se
53. this time The bit is cleared by the writing a 1 to the SERV_SETUPEND bit 3 DATAEND 0 1 Set this bit to 1 When setting TXPKTRDY for the last data packet 2 When clearing RXPKTRDY after unloading the last data packet 3 When setting TXPKTRDY for a zero length data packet It is cleared automatically 2 SENTSTALL 0 1 This bit is set when a STALL handshake is transmitted This bit should be cleared TXPKTRDY 0 1 Set this bit after loading a data packet into the FIFO It is cleared automatically when the data packet has been transmitted An interrupt is generated if enabled when the bit is cleared 0 RXPKTRDY 0 1 This bit is set when a data packet has been received An interrupt is generated when this bit is set This bit is cleared by setting the SERV_RXPKTRDY bit 120 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 58 Control Status Register for Endpoint 0 in Host Mode HOST_CSRO The Control Status Register for Endpoint 0 in Host Mode HOST_CSR0O is shown in Figure 73 and described in Table 74 Figure 73 Control Status Register for Endpoint 0 in Host Mode HOST_CSRO 15 11 10 9 8 Reserved DATATOGWREN DATATOG FLUSHFIFO R 0 WO R W 0 WO 7 6 5 4 3 2 1 0 NAK_TIMEOUT STATUSPKT REQPKT ERROR SETUPPKT RXSTALL TXPKTRDY RXPKTRDY W 0 R W 0 R W 0 W 0 R W
54. up to two packets can be stored in the FIFO awaiting transmission to the peripheral device Double packet buffering is enabled by setting the DPB bit of TXFIFOSZ register bit 4 e DMA If DMA is enabled for the endpoint a DMA request will be generated whenever the endpoint is able to accept another packet in its FIFO This feature can be used to allow the DMA controller to load packets into the FIFO without processor intervention When DMA is enabled and DMAMODE bit in HOST_TXCSR register is set an endpoint interrupt will not be generated for completion of packet reception An endpoint interrupt will be generated only in the error conditions 3 2 2 2 1 Setup Before initiating any bulk OUT transactions e The target function address needs to be set in the TXFUNCADDR register for the selected controller endpoint TXFUNCADDR register is available for all endpoints from EPO to EP4 e The HOST_TXTYPE register for the endpoint that is to be used needs to be programmed as follows Operating speed in the SPEED bit field bits 7 and 6 Set 10b in the PROT field for bulk transfer Endpoint Number of the target device in TENDPN field This is the endpoint number contained in the OUT Tx endpoint descriptor returned by the target device during enumeration e The TXMAXP register for the controller endpoint must be written with the maximum packet size in bytes for the transfer This value should be the same as the wMaxPacketSize field of
55. 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only W Write only n value after reset Table 74 Control Status Register for Endpoint 0 in Host Mode HOST_CSRO Field Descriptions Bit Field Value Description 15 11 Reserved 0 Reserved 10 DATATOGWREN 0 1 Set this bit to enable the DATATOG bit to be written This bit is automatically cleared once the new value is written to DATATOG 9 DATATOG 0 1 When read this bit indicates the current state of the EPO data toggle If DATATOGWREN is high this bit can be written with the required setting of the data toggle If DATATOGWREN is low any value written to this bit is ignored 8 FLUSHFIFO 0 1 Set this bit to flush the next packet to be transmitted read from the Endpoint 0 FIFO The FIFO pointer is reset and the TXPKTRDY RXPKTRDY bit is cleared Note FLUSHFIFO has no effect unless TXPKTRDY RXPKTRDY is set 7 NAK_TIMEOUT 0 1 This bit will be set when Endpoint 0 is halted following the receipt of NAK responses for longer than the time set by the NAKLIMITO register This bit should be cleared to allow the endpoint to continue 6 STATUSPKT 0 1 Set this bit at the same time as the TXPKTRDY or REQPKT bit is set to perform a status stage transaction Setting this bit ensures that the data toggle is set so that a DATA1 packet is used for the Status Stage transaction 5 REQPKT 0 1 Set this bit to request an IN transaction It is cleared when RXPK
56. 01 Transmit Hub Port TXHUBPORT Field Descriptions Bit Field Value Description 7 Reserved 0 Reserved 6 0 HUBPORT 0 7Fh Port number of the hub SPRUGH3 November 2008 140 Universal Serial Bus USB Controller Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 86 Receive Function Address RXFUNCADDR The Receive Function Address RXFUNCADDR is shown in Figure 101 and described in Table 102 Figure 101 Receive Function Address RXFUNCADDR 7 6 0 Reserved FUNCADDR HO R W 0 LEGEND R W Read Write R Read only n value after reset Table 102 Receive Function Address RXFUNCADDR Field Descriptions Bit Field Value Description 7 Reserved 0 Reserved 6 0 FUNCADDR 0 7Fh Address of target function 4 87 Receive Hub Address RXHUBADDR The Receive Hub Address RXHUBADDR is shown in Figure 102 and described in Table 103 Figure 102 Receive Hub Address RXHUBADDR 7 6 0 MULT_TRANS HUBADDR R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 103 Receive Hub Address RXHUBADDR Field Descriptions Bit Field Value Description 7 MULT_TRANS 0 1 Set to 1 if hub has multiple transaction translators Cleared to 0 if only single transaction translator is available 6 0 HUBADDR 0 7Fh Address of hub 4 88 Receive Hub Port RXHUBPORT The Receive Hub Po
57. 0h TCPPIDMASTATEW4 Transmit CPPI DMA State Word 4 Section 4 34 114h TCPPIDMASTATEWS5 Transmit CPPI DMA State Word 5 Section 4 35 11Ch TCPPICOMPPTR Transmit CPPI Completion Pointer Section 4 36 120h RCPPIDMASTATEWO Receive CPPI DMA State Word 0 Section 4 37 SPRUGH3 November 2008 Submit Documentation Feedback Universal Serial Bus USB Controller 75 Registers 1 TEXAS INSTRUMENTS www ti com Table 16 Universal Serial Bus USB Registers continued Offset Acronym Register Description Section 124h 128h 12Ch 130h 134h 138h 13Ch RCPPIDMASTATEW1 RCPPIDMASTATEW2 RCPPIDMASTATEW3 RCPPIDMASTATEW4 RCPPIDMASTATEWS5 RCPPIDMASTATEW6 RCPPICOMPPTR Receive CPPI DMA State Word 1 Receive CPPI DMA State Word 2 Receive CPPI DMA State Word 3 Receive CPPI DMA State Word 4 Receive CPPI DMA State Word 5 Receive CPPI DMA State Word 6 Receive CPPI Completion Pointer Section 4 38 Section 4 39 Section 4 40 Section 4 41 Section 4 42 Section 4 43 Section 4 44 140h 144h 148h 14Ch 150h 154h 15Ch 160h 164h 168h 16Ch 170h 174h 178h 17Ch TCPPIDMASTATEWO TCPPIDMASTATEW1 TCPPIDMASTATEW2 TCPPIDMASTATEW3 TCPPIDMASTATEW4 TCPPIDMASTATEW5 TCPPICOMPPTR RCPPIDMASTATEWO RCPPIDMASTATEW1 RCPPIDMASTATEW2 RCPPIDMASTATEW3 RCPPIDMASTATEW4 RCPPIDMASTATEW5 RCPPIDMASTATEW6 RCPPICOMPPTR Transmit Receive CPPI Channel 1 State Block Transmit CPPI DMA State Word 0 Transmit CPPI DMA State Word 1 Transmit CPPI
58. 20DM357 DMSoC ARM Subsystem Reference Guide Describes the ARM subsystem in the TMS320DM357 Digital Media System on Chip DMSoC The ARM subsystem is designed to give the ARM926EJ S ARMQ master control of the device In general the ARM is responsible for configuration and control of the device including the video processing subsystem and a majority of the peripherals and external memories SPRUG26 TMS320DM357 DMSoC Universal Asynchronous Receiver Transmitter UART User s Guide This document describes the universal asynchronous receiver transmitter UART peripheral in the TMS320DM357 Digital Media System on Chip DMSoC The UART peripheral performs serial to parallel conversion on data received from a peripheral device and parallel to serial conversion on data received from the CPU SPRUG27 TMS320DM357 DMSoC Inter Integrated Circuit I2C Peripheral User s Guide Describes the inter integrated circuit I2C peripheral in the TMS320DM357 Digital Media System on Chip DMSoC The I2C peripheral provides an interface between the DMSoC and other devices compliant with the I2C bus specification and connected by way of an I2C bus External components attached to this 2 wire serial bus can transmit and receive up to 8 bit wide data to and from the DMSoC through the 12C peripheral This document assumes the reader is familiar with the I2C bus specification SPRUGH3 November 2008 Preface 11 Submit Documentation Feedback I TEXAS INSTRUME
59. 3 available buffers to start the DMA A new transfer will not be started if the buffer count is below 3 The value in RBUFCNTn decrements as DMA controller consumes the buffers for reception Write the head of the queue descriptor pointer to the RCPPIDMASTATEW1 register to start the DMA The USB controller will send IN token and wait for the data on the bus Once data is received DMA controller will transfer the data in the Rx queue from the endpoint FIFO Once a complete DMA packet is received interrupt associated with the DMA channel is asserted SPRUGH3 November 2008 Universal Serial Bus USB Controller 65 Submit Documentation Feedback I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com The software enables packet reception on a given channel by writing the address of the first buffer descriptor in the queue nonzero value to the channel s head descriptor pointer RCCPIDMASTATEW1 in the channel s Rx DMA state When packet reception begins on a given channel the DMA controller fills each Rx buffer with data in order starting with the first buffer and proceeding through the Rx queue If the Buffer Offset in the Rx DMA State is nonzero then the controller will begin writing data after the offset number of bytes in the SOP buffer The DMA controller performs the following operations at the end of each packet reception e Overwrite the buffer length in the packet s EOP buffer descriptor with the number of b
60. 320DM357 Digital Media System on Chip DMSoC The HPI provides a parallel port interface through which an external host processor can directly access the TMS320DM357 DMSoC processor s resources configuration and program data memories SPRUG31 TMS320DM357 DMSoC General Purpose Input Output GPIO User s Guide Describes the general purpose input output GPIO peripheral in the TMS320DM357 Digital Media System on Chip DMSoC The GPIO peripheral provides dedicated general purpose pins that can be configured as either inputs or outputs When configured as an input you can detect the state of the input by reading the state of an internal register When configured as an output you can write to an internal register to control the state driven on the output pin SPRUG32 TMS320DM357 DMSoC Multimedia Card MMC Secure Digital SD Card Controller User s Guide Describes the multimedia card MMC secure digital SD card controller in the TMS320DM357 Digital Media System on Chip DMSoC The MMC SD card is used in a number of applications to provide removable data storage The MMC SD controller provides an interface to external MMC and SD cards The communication between the MMC SD controller and MMC SD card s is performed by the MMC SD protocol SPRUG33 TMS320DM357 DMSoC Asynchronous External Memory Interface EMIF User s Guide Describes the asynchronous external memory interface EMIF in the TMS320DM357 Digital Media System on Chip DMSoC
61. 4 2 Host Mode Isochronous Out Transactions An Isochronous OUT transaction may be used to transfer periodic data from the host to the USB peripheral Following optional features are available for use with a Tx endpoint used in Host mode to transmit this data 3 2 4 2 1 Double packet buffering When enabled up to two packets can be stored in the FIFO awaiting transmission to the peripheral device Double packet buffering is enabled by setting the DPB bit of TXFIFOSZ register bit 4 DMA If DMA is enabled for the endpoint a DMA request will be generated whenever the endpoint is able to accept another packet in its FIFO This feature can be used to allow the DMA controller to load packets into the FIFO without processor intervention However this feature is not particularly useful with isochronous endpoints because the packets transferred are often not maximum packet size When DMA is enabled and DMAMODE bit in HOST_TXCSR register is set endpoint interrupt will not be generated for completion of packet reception Endpoint interrupt will be generated only in the error conditions Setup Before initiating any Isochronous OUT transactions The target function address needs to be set in the TXFUNCADDR register for the selected controller endpoint TXFUNCADDR register is available for all endpoints from EPO to EP4 The HOST_TXTYPE register for the endpoint that is to be used needs to be programmed as follows Operating speed in t
62. 6 4 47 4 48 4 49 4 50 4 51 4 52 4 53 4 54 4 55 4 56 4 57 4 58 4 59 4 60 4 61 4 62 4 63 4 64 4 65 Contents Id TEXAS INSTRUMENTS www ti com Transmit CPPI Masked Status Register TCPPIMSKSR eee eeeeeee eee eeeeeeeeeeeaeeeeeeee 95 Transmit CPPI Raw Status Register TCPPIRAWSR A 95 Transmit CPPI Interrupt Enable Set Register TCPPIIENSETR seeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee 96 Transmit CPPI Interrupt Enable Clear Register TCPPIIENCLRR unzuusunsunnennnnnnnnnannun nn nn nun ann nenn 96 Receive CPPI Control Register RCPPICR ecceeeeeceee nen nnnnnunnnnnnannunnnnnnunnnnnnnnnnnnnnn nun nun nun 97 Receive CPPI Masked Status Register RCPPIMSKSR AN 97 Receive CPPI Raw Status Register RCPPIRAWSR uuusususnannunnnnnnannunnnunnnnnannnnnnnnnnnn nenn nennen 98 Receive CPPI Interrupt Enable Set Register DCPDPIENGETRI nun nennnnn nun nun nun nun nun 98 Receive CPPI Interrupt Enable Clear Register RCPPIIENCLRR uuzursunnannnnnannnannnnnnnn man nun nannn 99 Receive Buffer Count 0 Register RBUFCNTO AN 99 Receive Buffer Count 1 Register DHDDBUIECNTI eee ence eee ee nun nun nun nun nun nun ann nun nun nun nenn 100 Receive Buffer Count 2 Register RBUFCNT 2 uuzusnennannennnennannnunnannunnnannnun nun nannnannunnann nun nenn 100 Receive Buffer Count 3 Register RBUFCNT3 cccceeeeeeee nen nun nnan mann una nun nun nun nun nnan nun nann mann 101 Transmit CPPI DMA State Word 0 TCPPIDMASTATEWO
63. 6 5 0 SPEED Reserved R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 82 Type Register Host mode only HOST_TYPEO Field Descriptions Bit Field Value Description 7 6 SPEED 0 3h Operating Speed of Target Device 0 Illegal th High 2h Full 3h Low 5 0 Reserved 0 Reserved 4 67 Transmit Type Register Host mode only HOST_TXTYPE The Transmit Type Register Host mode only HOST_TXTYPE is shown in Figure 82 and described in Table 83 Figure 82 Transmit Type Register Host mode only HOST_TXTYPE 7 6 5 4 3 0 SPEED PROT TENDPN R W 0 R W 0 R W 0 LEGEND R W Read Write n value after reset Table 83 Transmit Type Register Host mode only HOST_TXTYPE Field Descriptions Bit Field Value Description 7 6 SPEED 0 3h Operating Speed of Target Device 0 Illegal th High 2h Full 3h Low 5 4 PROT 0 3h Set this to select the required protocol for the transmit endpoint 0 Control th Isochronous 2h Bulk 3h Interrupt 3 0 TENDPN 0 Fh Set this value to the endpoint number contained in the transmit endpoint descriptor returned to the USB controller during device enumeration SPRUGH3 November 2008 Universal Serial Bus USB Controller 129 Submit Documentation Feedback JA TEXAS INSTRUMENTS Registers www ti com 4 68 NAKLimitO Register Host mode only HOST_NAKLIMITO The NAKLimitO Register Hos
64. 8 INSTRUMENTS Universal Serial Bus USB Controller Introduction This document describes the universal serial bus USB controller in the TMS320DM357 Digital Media System on Chip DMSoC The controller supports high speed USB peripheral mode and high speed limited host mode operations The USB controller can be operated by ARM through the memory mapped registers Note The High Speed USB OTG Controller is an instantiation of the MUSBMHDRC from Mentor Graphics Corporation This document contains materials that are 2003 2007 Mentor Graphics Corporation Mentor Graphics is a registered trademark of Mentor Graphics Corporation or its affiliated companies in the United States and other countries Purpose of the Peripheral The USB controller supports data throughput rates up to 480 Mbps It provides a mechanism for data transfer between USB devices and also supports host negotiation Features The USB has the following features e Supports USB 2 0 peripheral at High Speed 480 Mbps and Full Speed 12 Mbps e Supports USB 2 0 host at High Speed 480 Mbps Full Speed 12 Mbps and Low Speed 1 5 Mbps e Supports USB 2 0 OTG e Supports four simultaneous RX and TX endpoints more can be supported by dynamically switching e Each endpoint can support all transfer types control bulk interrupt and isochronous e Supports USB extensions for Session Request SRP and Host Negotiation HNP e Includes a 4K endpoint FIFO RAM and
65. 83 Submit Documentation Feedback I TEXAS INSTRUMENTS Registers www ti com 4 4 Auto Request Register AUTOREQ The Auto Request Register AUTOREQ is shown in Figure 19 and described in Table 20 Figure 19 Auto Request Register AUTOREQ 31 16 Reserved R 0 15 8 7 6 5 4 3 2 1 0 Reserved Rx4 Rx3 Rx2 Rx1 R 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 20 Auto Request Register AUTOREQ Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 6 Rx4 0 3h RX endpoint 4 Auto Req enable 0 No auto req th Auto req on all but EOP 2h Reserved 3h Auto req always 5 4 Rx3 0 3h RX endpoint 3 Auto Req enable 0 No auto req th Auto req on all but EOP 2h Reserved 3h Auto req always 3 2 Rx2 0 3h RX endpoint 2 Auto Req enable 0 No auto req th Auto req on all but EOP 2h Reserved 3h Auto req always 1 0 Rx1 0 3h RX endpoint 1 Auto Req enable 0 No auto req th Auto req on all but EOP 2h Reserved 3h Auto req always 84 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 5 USB Interrupt Source Register INTSRCR The USB Interrupt Source Register INTSRCR is shown in Figure 20 and described in Table 21 Figure 20 USB Interrupt Source Register INTSRCR 31 25 24 16 Reserved USB
66. Buffer Count 2 Register RBUFCNT2 The Receive Buffer Count 2 Register RBUFCNT2 is shown in Figure 43 and described in Table 44 Figure 43 Receive Buffer Count 2 Register RBUFCNT2 31 16 Reserved HO 15 0 BUFCNT R W 0 LEGEND R W Read Write R Read only n value after reset Table 44 Receive Buffer Count 2 Register RBUFCNT2 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 0 BUFCNT 0 FFFFh Receive CPPI Buffer Count The current count of CPPI buffers in Receive channel 2 queue Writes add to current value not overwrite The DMA requires a minimum of 3 RX buffers to operate 100 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 29 Receive Buffer Count 3 Register RBUFCNT3 The Receive Buffer Count 3 Register RBUFCNTS is shown in Figure 44 and described in Table 45 Figure 44 Receive Buffer Count 3 Register RBUFCNT3 31 16 Reserved HO 15 0 BUFCNT R W 0 LEGEND R W Read Write R Read only n value after reset Table 45 Receive Buffer Count 3 Register RBUFCNT3 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 0 BUFCNT 0 FFFFh Receive CPPI Buffer Count 0 The current count of CPPI buffers in Receive channel 3 queue Writes add to current value not overwrite The DMA re
67. Bus USB Controller Submit Documentation Feedback 139 I TEXAS INSTRUMENTS Registers www ti com 4 83 Transmit Function Address TXFUNCADDR The Transmit Function Address TXFUNCADDR is shown in Figure 98 and described in Table 99 Figure 98 Transmit Function Address TXFUNCADDR 7 6 0 Reserved FUNCADDR HO R W 0 LEGEND R W Read Write R Read only n value after reset Table 99 Transmit Function Address TXFUNCADDR Field Descriptions Bit Field Value Description 7 Reserved 0 Reserved 6 0 FUNCADDR 0 7Fh Address of target function 4 84 Transmit Hub Address TXHUBADDR The Transmit Hub Address TXHUBADDR is shown in Figure 99 and described in Table 100 Figure 99 Transmit Hub Address TXHUBADDR 7 6 0 MULT_TRANS HUBADDR R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 100 Transmit Hub Address TXHUBADDR Field Descriptions Bit Field Value Description 7 MULT_TRANS 0 1 Set to 1 if hub has multiple transaction translators Cleared to 0 if only single transaction translator is available 6 0 HUBADDR 0 7Fh Address of hub 4 85 Transmit Hub Port TXHUBPORT The Transmit Hub Port TXHUBPORT is shown in Figure 100 and described in Table 101 Figure 100 Transmit Hub Port TXHUBPORT 7 6 0 Reserved HUBPORT HO R W 0 LEGEND R W Read Write R Read only n value after reset Table 1
68. CKed and the software should proceed to the following IN Data Phase OUT Data Phase or IN Status Phase specified for the particular Standard Device Request IN Data Phase Set REQPKT bit of HOST_CSRO bit 5 Wait while the controller sends the IN token and receives the required data back When the controller generates the Endpoint 0 interrupt read HOST_CSRO to establish whether the RXSTALL bit bit 2 the ERROR bit bit 4 the NAK_TIMEOUT bit bit 7 or RXPKTRDY bit bit 0 has been set If RXSTALL is set it indicates that the target has issued a STALL response If ERROR is set it means that the controller has tried to send the required IN token three times without getting any response If NAK_TIMEOUT bit is set it means that the controller has received a NAK response to each attempt to send the IN token for longer than the time set in HOST_NAKLIMITO The controller can then be directed either to continue trying this transaction until it times out again by clearing the NAK_TIMEOUT bit or to abort the transaction by clearing REQPKT before clearing the NAK_TIMEOUT bit If RXPKTRDY has been set the software should read the data from the Endpoint 0 FIFO then clear RXPKTRDY If further data is expected the software should repeat Steps 1 4 When all the data has been successfully received the CPU should proceed to the OUT Status Phase of the Control Transaction Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit
69. Controller 69 Submit Documentation Feedback I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com 3 4 1 3 4 2 3 5 70 USB Core Interrupts There are two methods available for software to access USB core interrupts selectable by the UINT bit of CTRLR The UINT bit cleared to 0 selects the PDR 2 0 compliant register set INTSRCR INTSETR INTCLRR INTMSKR INTMSKSETR INTMSKCLRR INTMASKEDR This is the default and should be used for most systems The DRVVBUS level change interrupt is only available in the PDR compliant register UINT set to one selects direct access to the USB core interrupt registers INTRUSB INTRUSBE INTRTX INTRRX Software should select a single method for interrupts and use its corresponding registers exclusively Interrupt status can be determined using the INTSRCR interrupt source register This register is non masked To clear the interrupt source set the corresponding interrupt bit in INTCLRR register For debugging purposes interrupt can be set manually through INTSETR register The interrupt controller provides the option of masking the interrupts A mask can be set using INTMSKSETR register and can be cleared by setting the corresponding bit in the INTMSKCLRR register The mask can be read from INTMSKR register The masked interrupt status is determined using the INTMASKEDR register Software should write all zeros to the End Of Interrupt Register EOIR to acknowl
70. DMA State Word 2 Transmit CPPI DMA State Word 3 Transmit CPPI DMA State Word 4 Transmit CPPI DMA State Word 5 Transmit CPPI Completion Pointer Receive CPPI DMA State Word 0 Receive CPPI DMA State Word 1 Receive CPPI DMA State Word 2 Receive CPPI DMA State Word 3 Receive CPPI DMA State Word 4 Receive CPPI DMA State Word 5 Receive CPPI DMA State Word 6 Receive CPPI Completion Pointer Section 4 30 Section 4 31 Section 4 32 Section 4 33 Section 4 34 Section 4 35 Section 4 36 Section 4 37 Section 4 38 Section 4 39 Section 4 40 Section 4 41 Section 4 42 Section 4 43 Section 4 44 180h 184h 188h 18Ch 190h 194h 19Ch 1A0h 1A4h 1A8h 1ACh 1BOh 1B4h 1B8h 1BCh TCPPIDMASTATEWO TCPPIDMASTATEW1 TCPPIDMASTATEW2 TCPPIDMASTATEW3 TCPPIDMASTATEW4 TCPPIDMASTATEW5 TCPPICOMPPTR RCPPIDMASTATEWO RCPPIDMASTATEW1 RCPPIDMASTATEW2 RCPPIDMASTATEW3 RCPPIDMASTATEW4 RCPPIDMASTATEW5 RCPPIDMASTATEW6 RCPPICOMPPTR Transmit Receive CPPI Channel 2 State Block Transmit CPPI DMA State Word 0 Transmit CPPI DMA State Word 1 Transmit CPPI DMA State Word 2 Transmit CPPI DMA State Word 3 Transmit CPPI DMA State Word 4 Transmit CPPI DMA State Word 5 Transmit CPPI Completion Pointer Receive CPPI DMA State Word 0 Receive CPPI DMA State Word 1 Receive CPPI DMA State Word 2 Receive CPPI DMA State Word 3 Receive CPPI DMA State Word 4 Receive CPPI DMA State Word 5 Receive CPPI DMA State Word 6 Receive CPPI Completion Pointer Section 4 30 Sec
71. Documentation Feedback 1 TEXAS INSTRUMENTS www ti com NAK limit reached Yes NAK Timeout set Error count cleared Endpoint halted Interrupt generated USB Controller Host and Peripheral Modes Operation Figure 10 IN Data Phase Flow Chart For each IN packet requested in SETUP phase RegPkt No set Yes IN token sent STALL Yes received Data0 1 received Error count incremented No Yes 3 2 1 3 OUT Data Phase Problem in data sent RxStall set RegPkt cleared Error Count cleared Interrupt generated ACK sent RxPktRdy set RegPkt cleared Error Count cleared Interrupt generated Transaction complete Implies problem at peripheral end of connection Transaction deemed complete Error bit set RegPkt cleared Error Count cleared Interrupt generated For the OUT Data Phase of a control transaction Figure 11 the software driving the USB host device needs to 1 Load the data to be sent into the endpoint 0 FIFO 2 Set the TXPKTRDY bit of HOST_CSRO bit 1 The controller then proceeds to send an OUT token followed by the data from the FIFO to Endpoint 0 of the addressed device retrying as necessary 3 At the end of the attempt to send the data the controller will generate an Endpoint 0 interrupt The software should then read HOST_CSRO to establish whether the RXSTALL bit bit 2 the ERROR bit bit 4 or the NAK_TIMEOUT bi
72. K 2 TEST_K 0 1 1 TEST_J 0 1 0 TEST_SEO_NAK 0 1 SPRUGH3 November 2008 Submit Documentation Feedback 118 Universal Serial Bus USB Controller 1 TEXAS INSTRUMENTS www ti com Registers 4 56 Maximum Packet Size for Peripheral Host Transmit Endpoint TXMAXP The Maximum Packet Size for Peripheral Host Transmit Endpoint TXMAXP is shown in Figure 71 and described in Table 72 Figure 71 Maximum Packet Size for Peripheral Host Transmit Endpoint TXMAXP 15 11 10 0 Reserved MAXPAYLOAD R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 72 Maximum Packet Size for Peripheral Host Transmit Endpoint TXMAXP Field Descriptions Bit Field Value Description 15 11 Reserved 0 Reserved 10 0 MAXPAYLOAD DEER The maximum payload transmitted in a single transaction The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk Interrupt and Isochronous transfers in full speed and high speed operations The value written to this register should match the wMaxPacketSize field of the Standard Endpoint Descriptor for the associated endpoint A mismatch could cause unexpected results SPRUGH3 November 2008 Universal Serial Bus USB Controller 119 Submit Documentation Feedback I TEXAS INSTRUMENTS Registers www ti com 4 57 Control Status Register for Endpo
73. K_TIMEOUT bit is set the controller can be directed either to continue trying this transaction until it times out again by clearing the NAK_TIMEOUT bit or to abort the transaction by flushing the FIFO before clearing the NAK_TIMEOUT bit If large blocks of data are being transferred then the overhead of calling an interrupt service routine to load each packet can be avoided by using DMA 3 2 2 2 3 Error Handling 3 2 3 54 If the target wants to shut down the Bulk OUT pipe it will send a STALL response This is indicated by the RXSTALL bit of HOST_TXCSR register bit 5 being set Host Mode Interrupt Transactions When the controller is operating as the host interactions with an Interrupt endpoint on the USB peripheral device are handled in very much the same way as the equivalent Bulk transactions described in previous sections The principal difference as far as operational steps are concerned is that PROT field of HOST_RXTYPE and HOST_TXTYPE bits 5 4 need to be set binary value to represent an Interrupt transaction The required polling interval also needs to be set in the HOST_RXINTERVAL and HOST_TXINTERVAL registers Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com 3 2 4 3 2 4 1 USB Controller Host and Peripheral Modes Operation Isochronous Transactions Host Mode Isochronous IN Transactions An Isochronous IN transaction is us
74. N and DATATOG bits of HOST_RXCSR bit 10 and bit 9 to toggle the current setting or by setting the CLRDATATOG bit of HOST_RXCSR bit 7 This will ensure that the data toggle which is handled automatically by the controller starts in the correct state Also if there are any data packets in the FIFO indicated by the RXPKTRDY bit bit 0 of HOST_RXCSR being set they should be flushed by setting the FLUSHFIFO bit of HOST_RXCSR bit 4 Note It may be necessary to set this bit twice in succession if double buffering is enabled Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation 3 2 2 1 2 Operation When Bulk data is required from the USB peripheral device the software should set the REQPKT bit in the corresponding HOST_RXCSR register bit 5 The controller will then send an IN token to the selected peripheral endpoint and waits for data to be returned If data is correctly received RXPKTRDY bit of HOST_RXCSR bit 0 is set If the USB peripheral device responds with a STALL RXSTALL bit bit 6 of HOST_RXCSR is set If a NAK is received the controller tries again and continues to try until either the transaction is successful or the POLINTVL_NAKLIMIT set in the HOST_RXINTERVAL register is reached If no response at all is received two further attempts are made before the controller reports an error by setting the
75. NTS Notational Conventions www ti com SPRUG28 TMS320DM357 DMSoC 64 Bit Timer User s Guide Describes the operation of the software programmable 64 bit timer in the TMS320DM357 Digital Media System on Chip DMSoC Timer 0 and Timer 1 are used as general purpose GP timers and can be programmed in 64 bit mode dual 32 bit unchained mode or dual 32 bit chained mode Timer 2 is used only as a watchdog timer The GP timer modes can be used to generate periodic interrupts or enhanced direct memory access EDMA synchronization events The watchdog timer mode is used to provide a recovery mechanism for the device in the event of a fault condition such as a non exiting code loop SPRUG29 TMS320DM357 DMSoC Serial Peripheral Interface SPI User s Guide Describes the serial peripheral interface SPI in the TMS320DM357 Digital Media System on Chip DMSoC The SPI is a high speed synchronous serial input output port that allows a serial bit stream of programmed length 1 to 16 bits to be shifted into and out of the device at a programmed bit transfer rate The SPI is normally used for communication between the DMSoC and external peripherals Typical applications include an interface to external I O or peripheral expansion via devices such as shift registers display drivers SPI ERROMs and analog to digital converters SPRUG30 TMS320DM357 DMSoC Host Port Interface HPI Reference Guide This document describes the host port interface in the TMS
76. Next Descriptor Pointers The last buffer descriptor in a queue has a zero Next Descriptor Pointer Each descriptor points to a data buffer yielding a queue of buffers Four Words of Receive Buffer Descriptor are described in Table 10 through Table 13 Table 10 Receive Buffer Descriptor Word 0 Bits Name Description 31 0 Next Descriptor Pointer The 32 bit word aligned memory address of the next buffer descriptor in the Rx queue This is the mechanism used to reference the next buffer descriptor from the current buffer descriptor If the value of this pointer is zero then the current buffer is the last buffer in the queue The software sets the Next Descriptor Pointer Table 11 Receive Buffer Descriptor Word 1 Bits Name Description 31 0 Buffer Pointer The Buffer Pointer is the byte aligned memory address of the buffer associated with the buffer descriptor The software sets the Buffer Pointer Table 12 Receive Buffer Descriptor Word 2 Bits Name Description 31 16 Buffer Offset The Buffer Offset indicates how many unused bytes are at the start of the buffer SOP buffers only A value of zero indicates that there are no unused bytes at the start of the buffer and that valid data begins on the first byte of the buffer A value of OOOFh decimal 15 indicates that the first 15 bytes of the buffer are to be ignored by the DMA controller while transmitting and that valid buffer da
77. Not end of packet buffer 1 End of packet buffer 29 Ownership The Ownership bit indicates ownership of the DMA packet and is valid only on SOP This bit is set by the software and cleared by the DMA controller when the packet has been transmitted The software can use this bit to reclaim buffers 0 The packet is owned by the host processor 1 The packet is owned by the DMA controller 28 EOQ End of Queue The End of Queue bit is set by the DMA controller to indicate that all packets in the queue have been transmitted and the Tx queue is empty This bit is valid only on when EOP is set Software should clear this bit when setting up the descriptor 0 The Tx queue has more packets to transfer 1 The DMA controller took this descriptor buffer as the last buffer descriptor in the last packet in the queue 27 24 Reserved Reserved 23 Zero Byte Zero Byte Packet Identifier This bit is set by the DMA controller when a zero byte USB packet has been received Software should ignore the Packet Length when this bit is set 22 16 Reserved Reserved 15 0 Packet Length The length of the DMA packet in bytes This field is valid only on SOP and is written by the DMA controller If the Packet Length is less than the sum of the buffer lengths then the packet data will be truncated Software should ignore the Packet Length when Zero Byte is set Four different cases are possible for the number of buffers in a DMA packet 1 Buffer Descripto
78. O is shown in Figure 41 and described in Table 42 Figure 41 Receive Buffer Count 0 Register RBUFCNTO 31 16 Reserved HO 15 0 BUFCNT R W 0 LEGEND R W Read Write R Read only n value after reset Table 42 Receive Buffer Count 0 Register RBUFCNTO Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 0 BUFCNT 0 FFFFh Receive CPPI Buffer Count The current count of CPPI buffers in Receive channel 0 queue Writes add to current value not overwrite The DMA requires a minimum of 3 RX buffers to operate SPRUGH3 November 2008 Universal Serial Bus USB Controller 99 Submit Documentation Feedback JA TEXAS INSTRUMENTS Registers www ti com 4 27 Receive Buffer Count 1 Register RBUFCNT1 The Receive Buffer Count 1 Register RBUFCNT1 is shown in Figure 42 and described in Table 43 Figure 42 Receive Buffer Count 1 Register RBUFCNT1 31 16 Reserved HO 15 0 BUFCNT R W 0 LEGEND R W Read Write R Read only n value after reset Table 43 Receive Buffer Count 1 Register RBUFCNT1 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved 15 0 BUFCNT 0 FFFFh Receive CPPI Buffer Count The current count of CPPI buffers in Receive channel 1 queue Writes add to current value not overwrite The DMA requires a minimum of 3 RX buffers to operate 4 28 Receive
79. O OO OO CH DMASTATEWO 0 PPIDMASTATEW1 PPIDMASTATEW2 PPIDMASTATEW3 PPIDMASTATEW4 PPIDMASTATEWS Il e o his code is also included in the controller initialization le Initialize CPPI DMA state aligned to 16 byte Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Introduction Example 4 Programming the USB DMA Controller continued usbRegs gt CHANNEL i RCPPIDMASTATEW6 0 tx_desc i 0 rx_desc i 0 Routine to flush TX fifo Must call this routine twice for double buffered FIFO void flush_tx_fifo int ep int index_save int status index_save usbRegs gt INDEX Save the index to restore later usbRegs gt INDEX ep Set the index to the desired endpoint status usbRegs gt PERI_TXCSR amp 3 Isolate the TxPktRdy and FIFONotEmpty bits if status Nothing showing in FIFO usbRegs gt PERI_TXCSR 1 Set TxPktRdy in case there is a partial packet already in FIFO usbRegs gt PERI_TXCSR usbRegs gt PERI_TXCSR amp OxFFFC 8 Write TXCSR with flush bit set FIFONotEmpty 0 and TxPktRdy 0 while usbRegs gt PERI_TXCSR amp 8 Keep looping until the flush bit clears usbRegs gt INDEX index_save Restore the index to previous value Routine to start the TX DMA for a given channel void start_tx_dma int ch Must have at least one descriptor befor
80. Operating speed in the SPEED bit field bits 7 and 6 Set 10 binary value in the PROT field for bulk transfer Endpoint Number of the target device in RENDPN field This is the endpoint number contained in the Rx endpoint descriptor returned by the target device during enumeration e The RXMAXP register for the controller endpoint must be written with the maximum packet size in bytes for the transfer This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the target endpoint e The HOST_RXINTERVAL register needs to be written with the required value for the NAK limit 2 215 frames microframes or cleared to 0 if the NAK timeout feature is not required e The relevant interrupt enable bit in the INTRRXE register should be set if an interrupt is required for this endpoint e The following bits of HOST _RXCSR register should be set as shown below Set DMAEN bit 13 to 1 if a DMA request is required for this endpoint Clear DSINYET bit 12 to 0 to allow normal PING flow control This will affect only High Speed transactions Always clear DMAMODE bit 11 to 0 e f DMA is enabled the AUTOREQ register can be set for generating IN tokens automatically after receiving the data Set the bit field RXn_AUTOREQ where n is the endpoint number with binary value 01 or 11 When the endpoint is first configured the endpoint data toggle should be cleared to 0 either by using the DATATOGWRE
81. P4TX EP3TX EP2TX EP1TX EPO HO HO HO HO R 0 HO LEGEND R Read only n value after reset Table 63 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 INTRTX Field Descriptions Bit Field Value Description 15 5 Reserved 0 Reserved 4 EP4TX 0 1 Transmit Endpoint 4 interrupt active 3 EP3TX 0 1 Transmit Endpoint 3 interrupt active 2 EP2TX 0 1 Transmit Endpoint 2 interrupt active 1 EP1TX 0 1 Transmit Endpoint 1 interrupt active 0 EPO 0 1 Endpoint 0 interrupt active 4 48 Interrupt Register for Receive Endpoints 1 to 4 INTRRX The Interrupt Register for Receive Endpoints 1 to 4 INTRRX is shown in Figure 63 and described in Table 64 112 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers Figure 63 Interrupt Register for Receive Endpoints 1 to 4 INTRRX 31 16 Reserved R 0 15 5 4 3 2 1 0 Reserved EP4RX EP3RX EP2RX EP1RX Reserved R 0 R 0 R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 64 Interrupt Register for Receive Endpoints 1 to 4 INTRRX Field Descriptions Bit Field Value Description 15 5 Reserved 0 Reserved 4 EP4RX 0 1 Receive Endpoint 4 interrupt active 3 EP3RX 0 1 Receive Endpoint 3 interrupt active 2 EP2RX 0 1 Receive Endpoint 2 interrupt active 1 EP1RX 0 1 Receive Endpoint 1 inte
82. Packet Size for Peripheral Host Receive Endpoint RXMAXP urssunsnnnunnennnnnnnnnnnnnnnnnn 124 Control Status Register for Peripheral Receive Endpoint PERI_RXCSR uuzussunnannnnnennnannnnnnnn nen 125 Control Status Register for Host Receive Endpoint HOST_RXCSR eceeceeeeeee eset eee eeeeeeeeeeeeeeee 126 Count 0 Register COUNTO as ss eat tease eege Ee tee x nt cements beste ENEE ee 128 Receive Count Register RXCOUNT EEN EEN 128 SPRUGH3 November 2008 Submit Documentation Feedback Id TEXAS INSTRUMENTS www ti com 4 66 Type Register Host mode only HOST_TYPEO ceeceeee cece nn nenn nun nun nenn nn nn nen nun nenn nennen 129 4 67 Transmit Type Register Host mode only HOST_TXTYPE z2444R 44H HR nn nn nun nn nenn nen nun nenn nun une nun 129 4 68 NAKLimitO Register Host mode only HOST_NAKLIMITO euuessannnunnennennnannannannnannnnnnun nun nnn nn 130 4 69 Transmit Interval Register Host mode only HOST_TXINTERVAL enusnnsunnannnannnnnannnannunnnnn nennen 130 4 70 Receive Type Register Host mode only HOST_RXTYPE zursessannennnnnnnn nun nun nun nnnn nun nun nun nenn 131 4 71 Receive Interval Register Host mode only HOST_RXINTERVAL a 131 4 72 Configuration Data Register CONEIGDATA AN 132 4 73 Transmit and Receive FIFO Register for Endpoint O FIFOO ccseceeeeeee eee nun eee nun nun nnun nun ann 134 4 74 Transmit and Receive FIFO Register for Endpoint 1 FIFO1 ccseeeeee seen an nun na
83. SPRUG37 TMS320DM357 DMSoC Pulse Width Modulator PWM Peripheral User s Guide Describes the pulse width modulator PWM peripheral in the TMS320DM357 Digital Media System on Chip DMSoC SPRUG38 TMS320DM357 DMSoC DDR2 Memory Controller User s Guide Describes the DDR2 memory controller in the TMS320DM357 Digital Media System on Chip DMSoC The DDR2 memory controller is used to interface with JESD79D 2A standard compliant DDR2 SDRAM devices SPRUG39 TMS320DM357 DMSoC Video Processing Front End VPFE User s Guide Describes the video processing front end VPFE in the TMS320DM357 Digital Media System on Chip DMSoC video processing subsystem Included in the VPFE is the preview engine CCD controller resizer histogram and hardware 3A H3A statistic generator SPRUGH2 TMS320DM357 DMSoC Peripherals Overview Reference Guide This document provides an overview of the peripherals in the TMS320DM357 Digital Media System on Chip DMSoC SPRUGH3 TMS320DM357 DMSoC Universal Serial Bus Controller User s Guide This document describes the universal serial bus USB controller in the TMS320DM357 Digital Media System on Chip DMSoC The USB controller supports data throughput rates up to 480 Mbps It provides a mechanism for data transfer between USB devices and also supports host negotiation SPRUGH3 November 2008 Read This First 13 Submit Documentation Feedback 1 1 1 2 1 3 IA TEXAS User s Guide SPRUGH3 November 200
84. STALL bit bit 2 of PERI_CSRO and generate an endpoint O interrupt 3 1 1 5 5 Additional Conditions When working as a peripheral device the controller automatically responds to certain conditions on the USB bus or actions by the host The details are given below e Stall Issued to Control Transfers The host sends more data during an OUT Data phase of a Control transfer than was specified in the device request during the SETUP phase This condition is detected by the controller when the host sends an OUT token instead of an IN token after the software has unloaded the last OUT packet and set DataEnd The host requests more data during an IN data phase of a Control transfer than was specified in the device request during the SETUP phase This condition is detected by the controller when the host sends an IN token instead of an OUT token after the software has cleared TXPKTRDY and set DataEnd in response to the ACK issued by the host to what should have been the last packet The host sends more than MaxPktSize data with an OUT data token The host sends the wrong PID for the OUT Status phase of a Control transfer The host sends more than a zero length data packet for the OUT Status phase e Zero Length Out Data Packets In Control Transfer A zero length OUT data packet is used to indicate the end of a Control transfer In normal operation such packets should only be received after the entire length of the device re
85. Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation Figure 2 Interrupt Service Routine Flow Chart Read interrupt status register Resume interrupt fe No A A A device device or B device B device Session req SESSREQ routine interrupt 2 Vbus Vbus error i error interrupt routine 9 p y Host Host Peripheral or peripheral Connect Connect _ EPO Peripheral routine interrupt interrupt EPO routine Babble Babble Receive Peripheral routine interrupt interrupt Rx routine Host EPO _ EPO Transmit Peripheral routine interrupt Interr p Tx routine Host Rx Ba routine interrupt Host Tx Transmit routine interrupt No SOF Resume interrupt routine Disconn Disconnect interrupt routine Suspend Suspend interrupt routine SPRUGH3 November 2008 Universal Serial Bus USB Controller 25 Submit Documentation Feedback I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com 3 1 26 USB Controller Peripheral Mode Operation e Soft connect After a reset the SOFTCONN bit of POWER register bit 6 is cleared to 0 The controller will therefore appear disconnected until the software has set the SOFTCONN bit to 1 The application
86. TALL SENDSTALL FLUSHFIFO UNDERRUN FIFONOTEMPTY TXPKTRDY W 0 R W 0 R W 0 WO R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only W Write only n value after reset Table 75 Control Status Register for Peripheral Transmit Endpoint PERI_TXCSR Field Descriptions Bit Field Value Description 15 Reserved 0 Reserved 14 ISO 0 1 Set this bit to enable the Tx endpoint for Isochronous transfers and clear this bit to enable the Tx endpoint for Bulk or Interrupt transfers 13 MODE 0 1 Set this bit to enable the endpoint direction as Tx and clear this bit to enable it as Rx Note This bit has any effect only where the same endpoint FIFO is used for both Transmit and Receive transactions 12 DMAEN 0 1 Set this bit to enable the DMA request for the Tx endpoint 11 FRCDATATOG 0 1 Set this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO regardless of whether an ACK was received This can be used by Interrupt Tx endpoints that are used to communicate rate feedback for Isochronous endpoints 10 DMAMODE 0 1 When using DMA clear this bit to receive an interrupt for each packet or set this bit to only receive error interrupts 9 7 Reserved 0 Reserved 6 CLRDATATOG 0 1 Set this bit to reset the endpoint data toggle to 0 5 SENTSTALL 0 1 This bit is set automatically when a STALL handshake is transmitted The FIFO is flushed and the TXPKTRDY bit is clear
87. TMS320DM357 DMSoC Universal Serial Bus USB Controller User s Guide is TEXAS INSTRUMENTS Literature Number SPRUGH3 November 2008 SPRUGH3 November 2008 Submit Documentation Feedback IJ TEXAS INSTRUMENTS Contents NC et 11 1 Introduction EE 14 1 1 Purpose of the Peripheral gea ge un an even ONSE EN KEEN EEN ENNEN EN ENER NEEN NNN AEN KE dude eas owed erae 14 1 2 FGAUICS eelere 14 1 3 Features Not SUPPONER eege Eeer Dee EEE 14 1 4 Functional Bl ck Diagram u n nn nie 15 1 5 S pponed Use Cass ul e 16 1 6 Industry Standard s Compliance Statement ssssssssssssssnnnnrrnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn 22 2 Peripheral ArchhectuUre css a a a E En he 23 2 1 Elek dee See a ee ee ee 28 2 2 Signal RI el TEE 23 2 3 Indexed and Non Indexed Heotsters KREE ANER NENNEN NEEN RER RENE nn nun nun nennen 23 2 4 e hf LE 24 2 5 Dynamic FIFO SIZING EE 24 3 USB Controller Host and Peripheral Modes Operation 44 HHRnan anne nn nennen anne 24 3 1 USB Controller Peripheral Mode Operation 26 3 2 USB Controller Host Mode Operation EEN 44 3 3 DIMA ee E 57 3 4 Jul de Luis ie DEER 68 3 5 Test ModS sn neun a a E E E 70 3 6 Reset Considerations um ea li 74 3 7 Interrupt SUPPOFT E 74 3 8 EDMA EVEN DEE EE 74 3 9 Power Management 74 4 Registers en Ran Rennen 75 4 1 Control Register IC TRB up 00 nenne ne 82 4 2 Status Register STAM A aan 83 4 3 RNDIS Register RNDISR ur eh 83 4 4 Auto Request R
88. TRDY is set ERROR 0 1 This bit will be set when three attempts have been made to perform a transaction with no response from the peripheral You should clear this bit An interrupt is generated when this bit is set 3 SETUPPKT 0 1 Set this bit at the same time as the TXPKTRDY bit is set to send a SETUP token instead of an OUT token for the transaction 2 RXSTALL 0 1 This bit is set when a STALL handshake is received You should clear this bit 1 TXPKTRDY 0 1 Set this bit after loading a data packet into the FIFO It is cleared automatically when the data packet has been transmitted An interrupt is generated if enabled when the bit is cleared 0 RXPKTRDY 0 1 This bit is set when a data packet has been received An interrupt is generated when this bit is set Clear this bit by setting the SERV_RXPKTRDY bit SPRUGH3 November 2008 Universal Serial Bus USB Controller 121 Submit Documentation Feedback I TEXAS INSTRUMENTS Registers www ti com 4 59 Control Status Register for Peripheral Transmit Endpoint PERI_TXCSR The Control Status Register for Peripheral Transmit Endpoint PERI_TXCSR is shown in Figure 74 and described in Table 75 Figure 74 Control Status Register for Peripheral Transmit Endpoint PERI_TXCSR 15 14 13 12 11 10 9 7 Reserved ISO MODE DMAEN FRCDATATOG DMAMODE Reserved R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 0 6 5 4 3 2 1 0 CLRDATATOG SENTS
89. The following optional features are available for use with an Rx endpoint used in host mode to receive the data e Double packet buffering When enabled up to two packets can be stored in the FIFO on reception from the host This allows that one packet can be received while another is being read Double packet buffering is enabled by setting the DPB bit of RXFIFOSZ register bit 4 e DMA If DMA is enabled for the endpoint a DMA request will be generated whenever the endpoint has a packet in its FIFO This feature can be used to allow the DMA controller to unload packets from the FIFO without processor intervention When DMA is enabled endpoint interrupt will not be generated for completion of packet reception Endpoint interrupt will be generated only in the error conditions e AutoRequest When the AutoRequest feature is enabled the REQPKT bit of HOST_RXCSR bit 5 will be automatically set when the RXPKTRDY bit is cleared This feature is applicable only when DMA is enabled To enable AutoRequest feature set the AUTOREQ register for the DMA channel associated for the endpoint 3 2 2 1 1 Setup 52 Before initiating any Bulk IN Transactions in Host mode e The target function address needs to be set in the RXFUNCADDR register for the selected controller endpoint RXFUNCADDR register is available for all endpoints from EPO to EP4 e The HOST_RXTYPE register for the endpoint that is to be used needs to be programmed as follows
90. Transmit CPPI DMA State Word 1 TCPPIDMASTATEWI Field Descriptions Bit Field Value Description 31 2 SOP_DESCRIPTOR_PTR 0 3FFF FFFFh Start of Packet Buffer Descriptor Pointer 30 bit pointer to 32 bit aligned descriptor which is the first descriptor for the current packet 1 Reserved 0 Reserved 0 IN_PACKET Flag indicating the DMA is in the middle of processing a packet 0 Not currently in packet Currently in packet 4 32 Transmit CPPI DMA State Word 2 TCPPIDMASTATEW2 The Transmit CPPI DMA State Word 2 TCPPIDMASTATEW2 is shown in Figure 47 and described in Table 48 Figure 47 Transmit CPPI DMA State Word 2 TCPPIDMASTATEW2 31 16 CURR_DESCRIPTOR_PTR R W 0 15 2 1 E CURR_DESCRIPTOR_PTR TRUNCATED_NON_EOP Reserved R W 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 48 Transmit CPPI DMA State Word 2 TCPPIDMASTATEW2 Field Descriptions Bit Field Value Description 31 2 CURR_DESCRIPTOR_PTR 0 3FFF FFFFh Current Buffer Descriptor Pointer 30 bit pointer to 32 bit aligned descriptor for buffer from which data is currently being transmitted 1 TRUNCATED_NON_EOP Flag indicating that packet truncation has occurred on the current packet within a buffer which was not designated as the end of packet buff 0 Truncation within non end of packet buffer has not occurred Truncation within non end of packet has occu
91. URR_BUFFER_PTR R W 0 LEGEND R W Read Write n value after reset Table 57 Receive CPPI DMA State Word 4 RCPPIDMASTATEWA Field Descriptions Bit Field Value Description 31 0 CURR_BUFFER_PTR 0 FFFF FFFFh Current Buffer Pointer 32 bit absolute byte address in buffer into which data is currently being received 4 42 Receive CPPI DMA State Word 5 RCPPIDMASTATEW5 The Receive CPPI DMA State Word 5 RCPPIDMASTATEWS5 is shown in Figure 57 and described in Table 58 Figure 57 Receive CPPI DMA State Word 5 RCPPIDMASTATEW5 31 16 PKT_LENGTH R W 0 15 o CURR_BUFFER_LENGTH R W 0 LEGEND R W Read Write n value after reset Table 58 Receive CPPI DMA State Word 5 RCPPIDMASTATEW5 Field Descriptions Bit Field Value Description 31 16 PKT_LENGTH 0 FFFFh Packet Length Indicates how many bytes are contained in the packet This value is written into bits 15 0 of Word 3 of the SOP Descriptor during end of packet processing 15 0 CURR_BUFFER_LENGTH 0 FFFFh Current Buffer Length Indicates how many free bytes remain in the current buffer that is being received into SPRUGH3 November 2008 Universal Serial Bus USB Controller 109 Submit Documentation Feedback JA TEXAS INSTRUMENTS Registers www ti com 4 43 Receive CPPI DMA State Word 6 RCPPIDMASTATEW6 The Receive CPPI DMA State Word 6 RCPPIDMASTATEWE6 is shown in Figure 58
92. XCSR and generate an interrupt When the software receives an interrupt with the SENTSTALL bit bit 6 of PERI_RXCSR set it should clear this bit It should however leave the SENDSTALL bit set until it is ready to re enable the Bulk OUT pipe Note If the host failed to receive the STALL packet for some reason it will send another packet so it is advisable to leave the SENDSTALL bit set until the software is ready to re enable the Bulk OUT pipe When a Bulk OUT pipe is re enabled the data toggle sequence should be restarted by setting the CLRDATATOG bit bit 7 in the PERI_RXCSR register Interrupt Transactions An Interrupt IN transaction uses the same protocol as a Bulk IN transaction and can be used the same way Similarly an Interrupt OUT transaction uses almost the same protocol as a Bulk OUT transaction and can be used the same way Tx endpoints in the USB controller have one feature for Interrupt IN transactions that they do not support in Bulk IN transactions In Interrupt IN transactions the endpoints support continuous toggle of the data toggle bit This feature is enabled by setting the FRCDATATOG bit in the PERI_TXCSR register bit 11 When this bit is set the controller will consider the packet as having been successfully sent and toggle the data bit for the endpoint regardless of whether an ACK was received from the host Another difference is that interrupt endpoints do not support PING flow control This means t
93. a toggle If DATATOGWREN is high this bit can be written with the required setting of the data toggle If DATATOGWREN is low any value written to this bit is ignored 7 NAK_TIMEOUT 0 1 This bit will be set when the Tx endpoint is halted following the receipt of NAK responses for longer than the time set as the NAKLIMIT by the TXINTERVAL register It should be cleared to allow the endpoint to continue Note This is valid only for Bulk endpoints 6 CLRDATATOG 0 1 Set this bit to reset the endpoint data toggle to 0 5 RXSTALL 0 1 This bit is set when a STALL handshake is received The FIFO is flushed and the TXPKTRDY bit is cleared You should clear this bit 4 SETUPPKT 0 1 Set this bit at the same time as TXPKTRDY is set to send a SETUP token instead of an OUT token for the transaction Note Setting this bit also clears the DATATOG bit 3 FLUSHFIFO 0 1 Set this bit to flush the next packet to be transmitted from the endpoint Tx FIFO The FIFO pointer is reset and the TXPKTRDY bit is cleared Note FlushFIFO has no effect unless TXPKTRDY is set Also note that if the FIFO is double buffered FLUSHFIFO may need to be set twice to completely clear the FIFO 2 ERROR 0 1 The USB controller sets this bit when 3 attempts have been made to send a packet and no handshake packet has been received You should clear this bit An interrupt is generated when the bit is set This is valid only when the endpoint is opera
94. acket in its FIFO This feature can be used to allow the DMA controller to unload packets from the FIFO without processor intervention However this feature is not particularly useful with Isochronous endpoints because the packets transferred are often not maximum packet size and the PERI_RXCSR register needs to be accessed following every packet to check for Overrun or CRC errors When DMA is enabled endpoint interrupt will not be generated for completion of packet reception Endpoint interrupt will be generated only in the error conditions Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation 3 1 4 2 1 Setup In configuring an Rx endpoint for Isochronous OUT transactions the RXMAXP register must be written with the maximum packet size in bytes for the endpoint This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the endpoint In addition the relevant interrupt enable bit in the INTRRXE register should be set if an interrupt is required for this endpoint and the PERI_RXCSR register should be set as shown in Table 5 Table 5 PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions Bit Position Bit Field Name Configuration Bit 14 ISO Set to 1 to enable isochronous protocol Bit 13 DMAEN Set to 1 if a DMA request is required for this endpoint Bit 12
95. amp usbRegs gt CHANNEL ch TCPPIDMASTATEWO 0 usbRegs gt CHANNEL ch TCPPIDMASTATEWO Uint32 amp tx_bufferDesc ch 4 tx_desc ch 0 SPRUGH3 November 2008 Universal Serial Bus USB Controller 21 Submit Documentation Feedback JA TEXAS INSTRUMENTS Introduction www ti com 1 6 22 Example 4 Programming the USB DMA Controller continued Increment descriptor counter tx_desc ch Routine to start the RX DMA for a given channel void start_rx_dma int ch int index_save index_save usbRegs gt INDEX Save the index to restore later Must have at least 3 descriptors to receive anything if rx_desc ch lt 2 error t else usbRegs gt INDEX ch 1 usbRegs gt RCPPICR 1 Enable Rx CPPI DMA usbRegs gt CHANNEL ch RCPPIDMASTATEWl1 Uint32 amp rx_bufferDesc ch 0 CSL_FINS usbRegs gt PERI_RXCSR USB_PERI_RXCSR_DMAEN 1 Update the buffer count register This ADDS to the existing value does not overwrite switch ch case 0 usbRegs gt RBUFCNTO rx_desc ch break case 1 usbRegs gt RBUFCNT1 rx_desc ch break case 2 usbRegs gt RBUFCNT2 rx_desc ch break case 3 usbRegs gt RBUFCNT3 rx_desc ch break usbRegs gt INDEX index_save Restore the index to previous value Function to build Rx DMA descriptors void add_rx_descriptor int ch unsigned char outBuf int bytes int index_save index_save usbRegs gt INDEX Save
96. ar and clear clear RxPktRdy and clear RxPktRdy RxPktRdy and set DataEnd RxPktRdy No data phase A gt Idle Unload device req and CPU actions clear RxPktRdy and set DataEnd 30 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation 3 1 1 5 Endpoint 0 Service Routine An Endpoint 0 interrupt is generated when e The controller sets the RXPKTRDY bit of PERI_CSRO bit 0 after a valid token has been received and data has been written to the FIFO e The controller clears the TXPKTRDY bit of PERI_CSRO bit 1 after the packet of data in the FIFO has been successfully transmitted to the host e The controller sets the SENTSTALL bit of PERI_CSRO bit 2 after a control transaction is ended due to a protocol violation e The controller sets the SETUPEND bit of PERI_CSRO bit 4 because a control transfer has ended before DATAEND bit 3 of PERI_CSRO is set Whenever the endpoint 0 service routine is entered the software must first check to see if the current control transfer has been ended due to either a STALL condition or a premature end of control transfer If the control transfer ends due to a STALL condition the SENTSTALL bit would be set If the control transfer ends due to a premature end of control transfer the SETUPEND bit would be set In either case the software should abort processing the c
97. ar equivalent Transmit endpoint interrupt source Allows the CPU to acknowledge an interrupt source and turn it off SPRUGH3 November 2008 Submit Documentation Feedback Universal Serial Bus USB Controller 87 I TEXAS INSTRUMENTS Registers www ti com 4 8 USB Interrupt Mask Register INTMSKR The USB Interrupt Mask Register INTMSKR is shown in Figure 23 and described in Table 24 Figure 23 USB Interrupt Mask Register INTMSKR 31 25 24 16 Reserved USB HO HO 15 13 12 8 7 5 4 0 Reserved RX Reserved TX R 0 R 0 R 0 R 0 LEGEND R Read only n value after reset Table 24 USB Interrupt Mask Register INTMSKR Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 16 USB 0 1FFh USB interrupt source masks Contains the masks of the interrupt sources generated by the USB core not the DMA These masks are used to enable or disable interrupt sources appearing as masked interrupts 15 13 Reserved 0 Reserved 12 8 RX 1Fh Receive endpoint interrupt source masks Contains the masks of the interrupt sources generated by the USB core not the DMA These masks are used to enable or disable interrupt sources appearing as masked interrupts 7 5 Reserved 0 Reserved 4 0 TX 0 Fh Transmit endpoint interrupt source masks Contains the masks of the interrupt sources generated by the USB core not the DMA These masks are used to enable or
98. atively it may infer that all the data has been sent when it receives a packet which is smaller than the stated payload TXMAXP bit 10 bit 0 In the latter case if the total size of the data block is a multiple of this payload it will be necessary for the function to send a null packet after all the data has been sent This is done by setting TXPKTRDY when the next interrupt is received without loading any data into the FIFO If large blocks of data are being transferred then the overhead of calling an interrupt service routine to load each packet can be avoided by using DMA 3 1 2 1 3 Error Handling If the software wants to shut down the Bulk IN pipe it should set the SENDSTALL bit bit 4 of PERI_TXCSR When the controller receives the next IN token it will send a STALL to the host set the SENTSTALL bit bit 5 of PERI_TXCSR and generate an interrupt When the software receives an interrupt with the SENTSTALL bit bit 5 of PERI_TXCSR set it should clear the SENTSTALL bit It should however leave the SENDSTALL bit set until it is ready to re enable the Bulk IN pipe Note If the host failed to receive the STALL packet for some reason it will send another IN token so it is advisable to leave the SENDSTALL bit set until the software is ready to re enable the Bulk IN pipe When a pipe is re enabled the data toggle sequence should be restarted by setting the CLRDATATOG bit in the PERI_TXCSR register bit 6 3 1 2 2 Peripheral
99. bRegs gt EPCSR CHAN_NUM 1 HOST_NAKLIMITO TXINTERVAL TX Polling interval usbRegs gt EPCSR CHAN_NUM 1 HOST_RXINTERVAL RXINTERVAL RX Polling interval else usbRegs gt EPCSR CHAN_NUM 1 HOST_NAKLIMITO 2 Frames to timeout from NAKs x usbRegs gt EPCSR CHAN_NUM 1 HOST_RXINTERVAL 2 Frames to timeout from NAKs Set the address for transactions after SET ADDRESS successfully completed usbRegs gt EPTRG CHAN_NUM 1 TXFUNCADDR device_address usbRegs gt EPTRG CHAN_NUM 1 RXFUNCADDR device_address SPRUGH3 November 2008 Universal Serial Bus USB Controller 19 Submit Documentation Feedback Introduction 20 User Case 4 An example of how to do host negotiation to support USB I TEXAS INSTRUMENTS www ti com If the HOSTREQ bit in the DEVCTL register is set host negotiation is performed by the hardware when the device enters suspend mode The bit is cleared when host negotiation is complete User Case 5 An example of how to program the USB DMA controller Example 4 Programming the USB DMA Controller Number of DMA channels define NUM_CHANNEL 4 Number of DMA buffers t define RX_BUFFERS 32 define TX_BUFFERS 32 define MEMORY_TARGET DD DMA defines define SOP Ui define EOP Ui define OWNER Uint define EOQ Ui define ZERO_BYTE Uint define RX_ABORT Uint3 DMA channel configurati define CHO 0 define CH1 1 define CH2 2 define CH3 3 L
100. cated by the FIFONOTEMPTY bit of HOST_TXCSR register bit 1 being set they should be flushed by setting the FLUSHFIFO bit bit 3 of HOST_TXCSR Note It may be necessary to set this bit twice in succession if double buffering is enabled 3 2 2 2 2 Operation When Bulk data is required to be sent to the USB peripheral device the software should write the first packet of the data to the FIFO or two packets if double buffered and set the TXPKTRDY bit in the corresponding HOST_TXCSR register bit 0 The controller will then send an OUT token to the selected peripheral endpoint followed by the first data packet from the FIFO If data is correctly received by the peripheral device an ACK should be received whereupon the controller will clear TXPKTRDY bit of HOST_TXCSR bit 0 If the USB peripheral device responds with a STALL the RXSTALL bit bit 5 of HOST_TXCSR is set If a NAK is received the controller tries again and continues to try until either the transaction is successful or the NAK limit set in the HOST_TXINTERVAL register is reached If no response at all is received two further attempts are made before the controller reports an error by setting ERROR bit in HOST_TXCSR bit 2 The controller then generates the appropriate endpoint interrupt whereupon the software should read the corresponding HOST_TXCSR register to determine whether the RXSTALL bit 5 ERROR bit 2 or NAK_TIMEOUT bit 7 bit is set and act accordingly If the NA
101. cket is received the interrupt associated with the DMA channel is asserted e If the DMA packet size is exact multiple of USB MaxPktSize a zero byte packet is expected and interrupt associated with the DMA channel is asserted when that zero byte packet is received e If the DMA packet size is not exact multiple of USB MaxPktSize the last USB packet received is a short packet and interrupt associated with the DMA channel is asserted An additional feature of automatically generating IN tokens is available This feature is used in USB Host mode operation of the USB controller This feature is functional in RNDIS mode DMA only To automatically generate the IN tokens while receiving data set the field RXn_AUTOREQ where n is the channel number of AUTOREQ register with binary 01 In this case IN tokens will be generated and sent to the target USB peripheral device after every successfully received packet No IN token will be generated after the End Of DMA Packet is reached Rx DMA interrupt is generated after the complete reception SPRUGH3 November 2008 Universal Serial Bus USB Controller 67 Submit Documentation Feedback I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com If RXn_AUTOREO where n is the channel number of AUTOREQ register is set with binary 11 IN tokens will be generated and sent to the target USB peripheral device even after the End Of DMA Packet is reached This feature is useful to keep
102. cond device may be either a high speed full speed or low speed USB function Or the controller can be used as the host to a range of such peripheral devices in a multi point setup Whether the controller expects to behave as a host or as a peripheral device depends on the way the devices are cabled together Each USB cable has an A end and a B end If the A end of the cable is plugged into the controller it will take the role of the Host device and go into host mode If the B end of the cable is plugged in the controller will go instead into peripheral mode The USB controller interrupts the ARM on completion of the data transfer on any of the endpoints or on detecting reset resume suspend connect disconnect or SOF on the bus When the ARM is interrupted with a USB interrupt it needs to read the interrupt status register to determine the endpoints that have caused the interrupt and jump to the appropriate routine If multiple endpoints have caused the interrupt endpoint 0 should be serviced first followed by the other endpoints The suspend interrupt should be serviced last The flowchart in Figure 2 describes the interrupt service routine for the USB module The following sections describe the programming of USB controller in Peripheral mode and Host mode DMA Operations and Interrupt Handler mechanisms are common to both peripheral and host mode operations and are discussed after the programming in Peripheral and Host Mode Universal
103. cription 7 6 SPEED 0 3h Operating Speed of Target Device 0 Illegal th High 2h Full 3h Low 5 4 PROT 0 3h Set this to select the required protocol for the transmit endpoint 0 Control th Isochronous 2h Bulk 3h Interrupt 3 0 RENDPN DER Set this value to the endpoint number contained in the Receive endpoint descriptor returned to the USB controller during device enumeration 4 71 Receive Interval Register Host mode only HOST_RXINTERVAL The Receive Interval Register Host mode only HOST_RXINTERVAL is shown in Figure 86 and described in Table 87 Figure 86 Receive Interval Register Host mode only HOST_RXINTERVAL POLINTVL_NAKLIMIT R W 0 LEGEND R W Read Write n value after reset SPRUGH3 November 2008 Universal Serial Bus USB Controller 131 Submit Documentation Feedback I TEXAS INSTRUMENTS Registers www ti com Table 87 Receive Interval Register Host mode only HOST_RXINTERVAL Field Descriptions Bit Field Value Description 7 0 POLINTVL_NAKLIMIT DEER For Interrupt and Isochronous transfers defines the polling interval for the currently selected transmit endpoint For Bulk endpoints this register sets the number of frames microframes after which the endpoint should timeout on receiving a stream of NAK responses There is a transmit Interval register for each configured transmit endpoint except Endpoint 0 In each case the value that is set defines a number of frames m
104. ction 4 85 associated Transmit Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub 494h RXFUNCADDR Address of the target function that has to be accessed Section 4 86 through the associated Receive Endpoint 496h RXHUBADDR Address of the hub that has to be accessed through the Section 4 87 associated Receive Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub 497h RXHUBPORT Port of the hub that has to be accessed through the Section 4 88 associated Receive Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub Target Endpoint 3 Control Registers Valid Only in Host Mode 498h TXFUNCADDR Address of the target function that has to be accessed Section 4 83 through the associated Transmit Endpoint 49Ah TXHUBADDR Address of the hub that has to be accessed through the Section 4 84 associated Transmit Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub 49Bh TXHUBPORT Port of the hub that has to be accessed through the Section 4 85 associated Transmit Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub 49Ch RXFUNCADDR Address of the target function that has to be accessed Section 4 86 through the associated Receive Endpoint SPRUGH3 November 2008 Universal Serial Bus USB Co
105. ction protocol and peripheral Section 4 67 endpoint number for the host Transmit endpoint 51Bh HOST_TXINTERVAL Sets the polling interval for Interrupt ISOC transactions or the Section 4 69 NAK response timeout on Bulk transactions for host Transmit endpoint 51Ch HOST_RXTYPE Sets the operating speed transaction protocol and peripheral Section 4 70 endpoint number for the host Receive endpoint 80 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback JA TEXAS INSTRUMENTS www ti com Registers Table 16 Universal Serial Bus USB Registers continued Offset Acronym Register Description Section 51Dh HOST_RXINTERVAL Sets the polling interval for Interrupt ISOC transactions or the Section 4 71 NAK response timeout on Bulk transactions for host Receive endpoint Control and Status Register for Endpoint 2 520h TXMAXP Maximum Packet Size for Peripheral Host Transmit Endpoint Section 4 56 522h PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint Section 4 59 peripheral mode HOST_TXCSR Control Status Register for Host Transmit Endpoint Section 4 60 host mode 524h RXMAXP Maximum Packet Size for Peripheral Host Receive Endpoint Section 4 61 526h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint Section 4 62 peripheral mode HOST_RXCSR Control Status Register for Host Receive Endpoint Section 4 63 host mode 528h RXCOUNT Number of Bytes in Host Receive en
106. d transaction protocol and peripheral Section 4 67 endpoint number for the host Transmit endpoint 54Bh HOST_TXINTERVAL Sets the polling interval for Interrupt ISOC transactions or the Section 4 69 NAK response timeout on Bulk transactions for host Transmit endpoint 54Ch HOST_RXTYPE Sets the operating speed transaction protocol and peripheral Section 4 70 endpoint number for the host Receive endpoint 54Dh HOST_RXINTERVAL Sets the polling interval for Interrupt ISOC transactions or the Section 4 71 NAK response timeout on Bulk transactions for host Receive endpoint 4 1 Control Register CTRLR The Control Register CTRLR is shown in Figure 16 and described in Table 17 Figure 16 Control Register CTRLR 31 16 Reserved HO 15 5 4 3 2 1 0 Reserved RNDIS UINT Reserved CLKFACK RESET HO R W 0 R W 0 HO R W 0 WO LEGEND R W Read Write R Read only n value after reset Table 17 Control Register CTRLR Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved 4 RNDIS 0 1 RNDIS mode enable 3 UINT 0 1 USB non PDR interrupt enable 2 Reserved 0 Reserved 1 CLKFACK 0 1 Clock stop fast ACK enable 0 RESET Soft reset 0 1 Writing a 1 starts a module reset 82 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 2 Status Register STATR The Status Register STATR is shown in Figure 17 and described in Table 18 Figure 17 Status Reg
107. d the PERI_RXCSR register should be set as shown in Table 3 Table 3 PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions Bit Position Bit Field Name Configuration Bit 14 ISO Cleared to 0 to enable Bulk protocol Bit 13 DMAEN Set to 1 if a DMA request is required for this endpoint Bit 12 DISNYET Cleared to 0 to allow normal PING flow control This will affect only high speed transactions Bit 11 DMAMODE Always set this bit to 0 When the endpoint is first configured following a SET_CONFIGURATION or SET_INTERFACE command on Endpoint 0 the lower byte of PERI_RXCSR should be written to set the CLRDATATOG bit bit 7 This will ensure that the data toggle which is handled automatically by the USB controller starts in the correct state Also if there are any data packets in the FIFO indicated by the RXPKTRDY bit bit 0 of PERI_RXCSR being set they should be flushed by setting the FLUSHFIFO bit bit 4 of PERI_RXCSR Note It may be necessary to set this bit twice in succession if double buffering is enabled 3 1 2 2 2 Operation When a data packet is received by a Bulk Rx endpoint the RXPKTRDY bit bit 0 of PERI_RXCSR is set and an interrupt is generated The software should read the RXCOUNT register for the endpoint to determine the size of the data packet The data packet should be read from the FIFO then the RXPKTRDY bit should be cleared The packets received should not exceed the size specified in the RXMAXP
108. data reception operational across multiple DMA packets in a Rx queue The host processor does not have to restart sending IN tokens for every DMA packet in the Rx queue Transparent Mode Setup Transparent receive DMA configuration is identical to RNDIS DMA configuration with the exception of the following e Each packet is defined by a single buffer descriptor with SOP and EOP bit fields set e Packet size is not bounded to be a multiple of 64 byte but by max packet size e CTRLR RNDIS bit field should be cleared to zero e RXn AUTOREQ register field is programmed with the value of 0 which is programmed for no Auto Request 3 3 2 8 DMA Teardown Procedure 3 4 68 In order to Teardown a TX channel the endpoint FIFO must be flushed after the DMA Teardown completes Teardown is not complete until the following steps are successfully completed e Write the TX Teardown register in the CPPI DMA with the channel to teardown The DMA will interrupt after the teardown is complete and the TX Completion Pointer will be FFFF FFFCh This indicates that the DMA has completed the teardown and all of the associated CPPI buffers can be reclaimed e Call the flush_tx_fifo routine code provided in Example 4 once if the FIFO is set up for single buffer or twice for double buffer Interrupt Handling Table 14 lists the interrupts generated by the USB controller Table 14 Interrupts Generated by the USB Coniroller Interrupt Description Tx
109. ddresses loads data into the Transmit FIFO for the corresponding endpoint Reading from these addresses unloads data from the Receive FIFO for the corresponding endpoint 134 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 74 Transmit and Receive FIFO Register for Endpoint 1 FIFO1 The Transmit and Receive FIFO Register for Endpoint 1 FIFO1 is shown in Figure 89 and described in Table 90 Figure 89 Transmit and Receive FIFO Register for Endpoint 1 FIFO1 DATA R W 0 LEGEND R W Read Write n value after reset Table 90 Transmit and Receive FIFO Register for Endpoint 1 FIFO1 Field Descriptions Bit Field Value Description 31 0 DATA 0 FFFF FFFF Writing to these addresses loads data into the Transmit FIFO for the corresponding endpoint Reading from these addresses unloads data from the Receive FIFO for the corresponding endpoint 4 75 Transmit and Receive FIFO Register for Endpoint 2 FIFO2 The Transmit and Receive FIFO Register for Endpoint 2 FIFO2 is shown in Figure 90 and described in Table 91 Figure 90 Transmit and Receive FIFO Register for Endpoint 2 FIFO2 31 0 DATA R W 0 LEGEND R W Read Write n value after reset Table 91 Transmit and Receive FIFO Register for Endpoint 2 FIFO2 Field Descriptions Bit Field Value Description 31 0
110. ded into three categories Zero Data Requests in which all the information is included in the command Write Requests in which the command will be followed by additional data and Read Requests in which the device is required to send data back to the host This section looks at the sequence of actions that the software must perform to process these different types of device request Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation Note The Setup packet associated with any standard device request should include an 8 byte command Any setup packet containing a command field of anything other than 8 bytes will be automatically rejected by the controller 3 1 1 1 Zero Data Requests Zero data requests have all their information included in the 8 byte command and require no additional data to be transferred Examples of Zero Data standard device requests are e SET_FEATURE e CLEAR_FEATURE e SET_ADDRESS e SET_CONFIGURATION e SET_INTERFACE The sequence of events will begin as with all requests when the software receives an endpoint 0 interrupt The RXPKTRDY bit of PERI_CSRO bit 0 will also have been set The 8 byte command should then be read from the endpoint 0 FIFO decoded and the appropriate action taken For example if the command is SET_ADDRESS the 7 bit address value contained in the command
111. defines the polling interval for the currently selected transmit endpoint For Bulk endpoints this register sets the number of frames microframes after which the endpoint should timeout on receiving a stream of NAK responses There is a transmit Interval register for each configured transmit endpoint except Endpoint 0 In each case the value that is set defines a number of frames microframes High Speed transfers as follows Transfer Type Speed Valid values m Interpretation Interrupt Low Speed or Full Speed 1 255 Polling interval is m frames High Speed 1 16 Polling interval is 21 microframes Isochronous Full Speed or High Speed 1 16 Polling interval is 2 frames microframes Bulk Full Speed or High Speed 2 16 NAK Limit is 27 frames microframes Note A value of 0 or 1 disables the NAK timeout function 130 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 70 Receive Type Register Host mode only HOST_RXTYPE The Receive Type Register Host mode only HOST_RXTYPE is shown in Figure 85 and described in Table 86 Figure 85 Receive Type Register Host mode only HOST_RXTYPE 7 6 5 4 3 0 SPEED PROT RENDPN R W 0 R W 0 R W 0 LEGEND R W Read Write n value after reset Table 86 Receive Type Register Host mode only HOST_RXTYPE Field Descriptions Bit Field Value Des
112. dicates how many bytes remain to be transmitted in the packet before truncation occurs 15 0 LENGTH 0 FFFFh Packet Length Indicates how many bytes are contained in the packet This value is copied from the packet length field in Word 3 of the SOP Descriptor This value is written into the AALS5 trailer for the packet 4 36 Transmit CPPI Completion Pointer TCPPICOMPPTR The Transmit CPPI Completion Pointer TCPPICOMPPTR is shown in Figure 51 and described in Table 52 Figure 51 Transmit CPPI Completion Pointer TCPPICOMPPTR 31 16 DESC_ADDR R W 0 15 2 1 0 DESC_ADDR Reserved WRBK_MODE R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset 104 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers Table 52 Transmit CPPI Completion Pointer TCPPICOMPPTR Field Descriptions Bit Field Value Description 31 2 DESC_ADDR 0 3FFF FFFFh Descriptor Address This field contains the 30 bit word aligned pointer of the end of packet descriptor that the DMA has last processed Reserved 0 Reserved 0 WRBK_MODE Writeback Compare Mode This bit controls the action that is to be taken when this location is written 0 Compare Mode Indicates that the value that is presented on bits 31 2 of the write data should be compared against the value that is currently contained in bit
113. dpoint FIFO Section 4 65 52Ah HOST_TXTYPE Sets the operating speed transaction protocol and peripheral Section 4 67 endpoint number for the host Transmit endpoint 52Bh HOST_TXINTERVAL Sets the polling interval for Interrupt ISOC transactions or the Section 4 69 NAK response timeout on Bulk transactions for host Transmit endpoint 52Ch HOST_RXTYPE Sets the operating speed transaction protocol and peripheral Section 4 70 endpoint number for the host Receive endpoint 52Dh HOST_RXINTERVAL Sets the polling interval for Interrupt ISOC transactions or the Section 4 71 NAK response timeout on Bulk transactions for host Receive endpoint Control and Status Register for Endpoint 3 530h TXMAXP Maximum Packet Size for Peripheral Host Transmit Endpoint Section 4 56 532h PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint Section 4 59 peripheral mode HOST_TXCSR Control Status Register for Host Transmit Endpoint Section 4 60 host mode 534h RXMAXP Maximum Packet Size for Peripheral Host Receive Endpoint Section 4 61 536h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint Section 4 62 peripheral mode HOST_RXCSR Control Status Register for Host Receive Endpoint Section 4 63 host mode 538h RXCOUNT Number of Bytes in Host Receive endpoint FIFO Section 4 65 53Ah HOST_TXTYPE Sets the operating speed transaction protocol and peripheral Section 4 67 endpoint number for the host Transmit endpoint 53Bh HOST_TXINTERVAL Sets the poll
114. dpoints 1 4 414h RXMAXP Maximum Packet Size for Peripheral Host Receive Endpoint Section 4 61 Index register set to select Endpoints 1 4 416h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint Section 4 62 Index register set to select Endpoints 1 4 HOST_RXCSR Control Status Register for Host Receive Endpoint Section 4 63 Index register set to select Endpoints 1 4 418h COUNTO Number of Received Bytes in Endpoint 0 FIFO Section 4 64 Index register set to select Endpoint 0 RXCOUNT Number of Bytes in Host Receive Endpoint FIFO Section 4 65 Index register set to select Endpoints 1 4 41Ah HOST_TYPEO Defines the speed of Endpoint 0 Section 4 66 HOST_TXTYPE Sets the operating speed transaction protocol and peripheral Section 4 67 endpoint number for the host Transmit endpoint Index register set to select Endpoints 1 4 SPRUGH3 November 2008 Submit Documentation Feedback Universal Serial Bus USB Controller 77 I TEXAS INSTRUMENTS Registers www ti com Table 16 Universal Serial Bus USB Registers continued Offset Acronym Register Description Section 41Bh HOST_NAKLIMITO Sets the NAK response timeout on Endpoint 0 Section 4 68 Index register set to select Endpoint 0 HOST_TXINTERVAL Sets the polling interval for Interrupt ISOC transactions or the Section 4 69 NAK response timeout on Bulk transactions for host Transmit endpoint Index register set to select Endpoints 1 4 41Ch HOST_RXTYPE Sets the ope
115. dress RXFIFOADDR AN 139 98 Transmit Function Address TSEUNCADDD nun nnnnnnnnn 140 99 Transmit Hub Address TXHUBADDR zunssennnennnnnnnnnnnnennnnnennnnnnn nennen nenn nenne nenn nennen nun nenne nenn 140 100 Transmit Hub Port TXHUBPORT z 4 2 canan aaa na a nennen 140 101 Receive Function Address RXFUNCADDR uuuusssunnannnnnannnannunnnunnunnannnunnnunnnnnunnnnnnun nun nunnenn 141 102 Receive Hub Address RXHUBADDR e 141 103 Receive Hub Port RXHUBPORT EEN 141 SPRUGH3 November 2008 List of Figures 7 Submit Documentation Feedback A TEXAS INSTRUMENTS www ti com List of Tables 1 USB E 23 2 PERI_TXCSR Register Bit Configuration for Bulk IN Transactions cceeeeeeeeee eee eee eee eee seen eeeeeeeeeeee 37 3 PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions ccceeeeeeeeeeee eee e eee eeeeeeeeeeeeeeee 39 4 PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions cceeeeeee eee eee eee eeeeeeeeeeee 41 5 PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactons nn nenn nennen 43 6 Transmit Buffer Descriptor Word ON 58 7 Transmit Buffer Descriptor Word 1 u2suusennnnennnnnnnnnenn nenn nnnnn nennen nun n nennen nenne nennen nenn nenne nenne nenne 58 8 Transmit Buffer Descriptor Word 2 uuunsunsennnnennnnnnnennnnnennnnnnnnnennnnnnnnnen nenn nennen nnnn ernennen nennen 58 9 Transmit Buffer Descriptor Word 3 uuussunsennnnennnnnnnennnnnennnnnnn nennen nnnnn nennen nenne
116. e Buffer Offset with the number of bytes in the offset to the data nonzero with SOP only e Set the SOP EOP and Ownership bits as appropriate e Clear the End Of Queue bit The DMA controller begins Tx DMA packet transmission on a given channel when the host writes the channel s Tx queue head descriptor pointer with the address of the first buffer descriptor in the queue nonzero value Each channel has one queue and a head descriptor pointer The first buffer descriptor for each Tx DMA packet must have the Start of Packet SOP bit and the Ownership bit set to one by the software The last buffer descriptor for each Tx DMA packet must have the End of Packet EOP bit set to one by the software The DMA controller will transmit DMA packets until all queued packets have been transmitted and the queue is empty When each packet transmission is complete the DMA controller will Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation clear the Ownership bit in the DMA packet s SOP buffer descriptor and issue an interrupt to the processor by writing the DMA packet s last buffer descriptor address to the queue s Tx DMA State Completion Pointer TCPPICOMPPTR register When the last packet in a queue has been transmitted the DMA controller sets the End Of Queue bit in the EOP buffer descriptor clears the Ownership bit in the SOP
117. e FIFO without processor intervention However this feature is not particularly useful with Isochronous endpoints because the packets transferred are often not maximum packet size and the PERI_TXCSR register needs to be accessed following every packet to check for Underrun errors When DMA is enabled and DMAMODE bit of PERI_TXCSR is set endpoint interrupt will not be generated for completion of packet transfer Endpoint interrupt will be generated only in the error conditions 3 1 4 1 1 Setup In configuring a Tx endpoint for Isochronous IN transactions the TXMAXP register must be written with the maximum packet size in bytes for the endpoint This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the endpoint In addition the relevant interrupt enable bit in the INTRTXE register should be set if an interrupt is required for this endpoint and the PERI_TXCSR register should be set as shown in Table 4 Table 4 PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions Bit Position Bit Field Name Configuration Bit 14 ISO Set to 1 to enable Isochronous transfer protocol Bit 13 MODE Set to 1 to ensure the FIFO is enabled only necessary if the FIFO is shared with an Rx endpoint Bit 12 DMAEN Set to 1 if DMA Requests have to be enabled Bit 11 FRCDATATOG Ignored in Isochronous mode Bit 10 DMAMODE Set it to 1 when DMA is enabled and EP interrupt is not needed for each packet trans
118. e USB controller has successfully negotiated for high speed mode SPRUGH3 November 2008 Submit Documentation Feedback Universal Serial Bus USB Controller 111 JA TEXAS INSTRUMENTS Registers www ti com Table 62 Power Management Register POWER Field Descriptions continued Bit Field Value Description 3 RESET 0 1 This bit is set when Reset signaling is present on the bus Note This bit is Read Write in Host Mode but read only in Peripheral Mode 2 RESUME 0 1 Set to generate Resume signaling when the controller is in Suspend mode The bit should be cleared after 10 ms a maximum of 15 ms to end Resume signaling In Host mode this bit is also automatically set when Resume signaling from the target is detected while the USB controller is suspended 1 SUSPENDM 0 1 In Host mode this bit should be set to enter Suspend mode In Peripheral mode this bit is set on entry into Suspend mode It is cleared when the interrupt register is read or the RESUME bit is set 0 ENSUSPM 0 1 Set to enable the SUSPENDM output 4 47 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 INTRTX The Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 INTRTX is shown in Figure 62 and described in Table 63 Figure 62 Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 INTRTX 15 S Reserved HO 7 5 4 3 2 1 0 Reserved E
119. e information for each transmit channel The state information is referred to as the Tx DMA State The Tx DMA State is a combination of control fields and DMA controller specific scratchpad space used to manipulate data structures and transmit DMA packets The Tx DMA State is stored in registers TCPPIDMASTATEWO TCPPIDMASTATEW1 TCPPIDMASTATEW2 TCPPIDMASTATEWS TCPPIDMASTATEW4 TCPPIDMASTATEW5 and TCPPICOMPPTR for each channel Each channel has one queue The queue has one head descriptor pointer and one completion pointer The following information is stored in the Tx DMA State e TCPPIDMASTATEWO Tx Queue Head Descriptor Pointer s e TCPPICOMPPTR Tx Completion Pointer s e TCPPIDMASTATEW Start of Packet Buffer Descriptor Pointer e TCPPIDMASTATEW2 Current Buffer Descriptor Pointer e TCPPIDMASTATEWS Current Buffer Pointer e TCPPIDMASTATEWS5 Remaining DMA Packet Length and Actual DMA Packet Length SPRUGH3 November 2008 Submit Documentation Feedback Universal Serial Bus USB Controller 59 JA TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com 3 3 1 4 Transmit Queue Figure 14 shows a Tx queue Tx queue provide a logical queue of DMA packets for transmission through a channel Each channel has one dedicated Tx queues The queue has one associated Tx Queue Head Descriptor Pointer and one associated Tx Completion Pointer container in the channel Tx DMA state The Tx queue is linked lists of Tx buffe
120. e turning on TX DMA if rx_desc ch lt 1 error t else Flush FIFO 2 times in case it is double buffered flush_tx_fifo ch 1l flush_tx_fifo ch 1 Start the DMA usbRegs gt TCPPICR 1 Enable Tx CPPI DMA usbRegs gt CHANNEL ch TCPPIDMASTATEWO Uint32 amp tx_bufferDesc ch 0 CSL_FINS usbRegs gt PERI_TXCSR USB_PERI_TXCSR_DMAEN 1 TXCSR bit DMAReqEnab Routine to add a TX descriptor void add_tx_descriptor int ch unsigned char inBuf int bytes if bytes lt 0 bytes gt 65535 bytes 64 error Link previous buffer to this one if this is not the first descriptor of the channel if tx_desc ch gt 0 tx_bufferDesc ch 4 tx_desc ch 1 Uint32 amp tx_bufferDesc ch 4 tx_desc ch Set up DMA buffer descriptors tx_bufferDesc ch 4 tx_desc ch 0 Uint32 0x00000000 Next Descriptor pointer tx_bufferDesc ch 4 tx_desc ch 1 Uint32 inBuf Buffer pointer tx_bufferDesc ch 4 tx_desc ch 2 0x0000 lt lt 16 bytes 31 16 Buffer offset 15 0 Buffer length if bytes 0 bytes ZERO_BYTE 1 Set the ZERO_BYTE bit and size 1 byte tx_bufferDesc ch 4 tx_desc ch 3 SOP EOP OWNER bytes 31 SOP 30 EOP 29 owner 28 EOQ 23 zero byte 19 rxabort 15 0 packet length I DMA already enabled and has stopped write this to the TX Queue head pointer if usbRegs gt TCPPICR 1 amp
121. ed Yes Error count NAK Timeout set incremented Endpoint halted Interrupt generated O 5 lt Universal Serial Bus USB Controller RxStall set TxPktRdy cleared Error Count cleared interrupt generated TxPktRdy cleared Error Count cleared Interrupt generated Transaction complete Error bit set TxPktRdy cleared Error Count cleared interrupt generated Command could not be completed Implies problem at peripheral end of connection Transaction deemed complete SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com 3 2 1 4 needs to USB Controller Host and Peripheral Modes Operation IN Status Phase following SETUP Phase or OUT Data Phase For the IN Status Phase of a Control Transaction Figure 12 the software driving the USB Host device 1 Set the STATUSPKT and REQPKT bits of HOST_CSRO bit 6 and bit 5 respectively 2 Wait while the controller sends an IN token and receives a response from the USB peripheral device Figure 12 Completion of SETUP or OUT Data Phase Flow Chart No NAK limit Yes reached Error count cleared Yes NAK Timeout set Endpoint halted Interrupt generated No Completion of either SETUP phase or OUT data phase RegPkt and StatusPkt No both set 2 Yes IN token sent STALL Yes received No NAK received No Data1 received Yes No Error
122. ed You should clear this bit 4 SENDSTALL 0 1 Set this bit to issue a STALL handshake to an IN token Clear this bit to terminate the stall condition Note This bit has no effect where the endpoint is being used for Isochronous transfers 3 FLUSHFIFO 0 1 Set this bit to flush the next packet to be transmitted from the endpoint Tx FIFO The FIFO pointer is reset and the TXPKTRDY bit is cleared Note FlushFIFO has no effect unless TXPKTRDY is set Also note that if the FIFO is double buffered FlushFIFO may need to be set twice to completely clear the FIFO 2 UNDERRUN 0 1 This bit is set automatically if an IN token is received when TXPKTRDY is not set You should clear this bit FIFONOTEMPTY 0 1 This bit is set when there is at least 1 packet in the Tx FIFO You should clear this bit 0 TXPKTRDY 0 1 Set this bit after loading a data packet into the FIFO It is cleared automatically when a data packet has been transmitted An interrupt is generated if enabled when the bit is cleared SPRUGH3 November 2008 Submit Documentation Feedback 122 Universal Serial Bus USB Controller 1 TEXAS INSTRUMENTS www ti com Registers 4 60 Control Status Register for Host Transmit Endpoint HOST_TXCSR The Control Status Register for Host Transmit Endpoint HOST_TXCSR is shown in Figure 75 and described in Table 76 Figure 75 Control Status Register for Host Transmit Endpoint HOST_TXCSR
123. ed and the RAM block by loading a packet of up to 64 bytes into the Endpoint 0 FIFO and then reading it back out again Endpoint 0 is used because it is a bi directional endpoint that uses the same area of RAM for its Tx and Rx FIFOs Note The core does not need to be connected to the USB bus to run this test If it is connected then no session should be in progress when the test is run The test procedure is as follows 1 Load a packet of up to 64 bytes into the Endpoint 0 Tx FIFO 2 Set CSRO TxPktRdy 3 Write 0x40 to the Testmode register 4 Unload the packet from the Endpoint Rx FIFO again 5 Set CSRO ServicedRxPktRdy Writing 0x40 to the Testmode register causes the following sequence of events 1 The Endpoint 0 CPU pointer which records the number of bytes to be transmitted is copied to the Endpoint 0 USB pointer which records the number of bytes received The Endpoint 0 CPU pointer is reset CSRO TxPktRdy is cleared CSRO RxPktRdy is set 5 An Endpoint 0 interrupt is generated if enabled AWN The effect of these steps is to make the Endpoint 0 controller act as if the packet loaded into the Tx FIFO has flushed and the same packet received over the USB The data that was loaded in the Tx FIFO can now be read out of the Rx FIFO Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operatio
124. ed section Renamed section Renamed section Renamed section Renamed section Changed third sentence second paragraph Changed second paragraph Renamed section Replaced first paragraph Changed figure Changed second sentence first paragraph Changed forth sentence first paragraph Changed second bullet Added Transparent Mode Setup and last paragraph Changed third sentence second paragraph Renamed section Changed first paragraph Changed figure Changed second bullet Changed third bullet Added Transparent Mode Setup and last paragraph Added section and subsections Changed third sentence Changed bit descriptions Changed bit descriptions SPRUGH3 November 2008 Submit Documentation Feedback Revision History 143 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and ot
125. ed to transfer periodic data from the USB peripheral to the host The following optional features are available for use with an Rx endpoint used in Host mode to receive this data 3 2 4 1 1 Double packet buffering When enabled up to two packets can be stored in the FIFO on reception from the host This allows that one packet can be received while another is being read Double packet buffering is enabled by setting the DPB bit of RXFIFOSZ register bit 4 DMA If DMA is enabled for the endpoint a DMA request will be generated whenever the endpoint has a packet in its FIFO This feature can be used to allow the DMA controller to unload packets from the FIFO without processor intervention However this feature is not particularly useful with isochronous endpoints because the packets transferred are often not maximum packet size When DMA is enabled endpoint interrupt will not be generated for completion of packet reception Endpoint interrupt will be generated only in the error conditions AutoRequest When the AutoRequest feature is enabled the REQPKT bit of HOST_RXCSR bit 5 will be automatically set when the RXPKTRDY bit is cleared This feature is applicable only when DMA is enabled To enable AutoRequest feature set the AUTOREQ register for the DMA channel associated for the endpoint Setup Before initiating an Isochronous IN Transactions in Host mode 3 2 4 1 2 The target function address needs to be set in the RXFUNCADDR regi
126. edge the completion of the USB core interrupt Note Ifthe EOIR is not written the interrupt output to the CPU will not be pulsed again for the next interrupt DMA Interrupts Interrupt status for the DMA interrupts is determined by TCCPIRAWSR and RCPPIRAWSR registers These are the raw interrupt status registers for DMA interrupts Tx DMA interrupts mask is set using TCPPIENSETR register and cleared using TCPPIIENCLRR register The masked status is read using TCPPIMSKSR register Rx DMA interrupts mask is set using RCPPIENSETR register and cleared using RCPPIIENCLRR register The masked status is read using RCPPIMSKSR register Like USB core interrupts the CPPIEOIR register needs to be written by the host processor software to acknowledge the completion of the interrupt Upon receipt of a DMA interrupt software should check TCPPIRAWSR RCPPIRAWSR to determine which DMA channel s to service Check the CPPI buffer descriptor ownership field for the completed channel for error conditions and add or update buffer descriptors as needed Write the RCPPICOMPPTR or TCPPICOMPPTR completion pointer with the address of the buffer descriptor serviced in order to clear the interrupt Finally write the DMA End Of Interrupt register CPPIEOIR with all zeros to enable future or current unserviced interrupts to pulse the interrupt output to the CPU When using DMA with a TX endpoint set the TXCSR register DMAMODE bit to one in order to receive o
127. ee 113 66 Interrupt Enable Register for INTRRX INTRRXE Field Descrpttons AN 114 67 Interrupt Register for Common USB Interrupts INTRUSB Field Descriptions eeeeeeeeeeeeeeeeeees 115 68 Interrupt Enable Register for INTRUSB INTRUSBE Field Descriptions u zussussunnennnannan nun nennen 116 69 Frame Number Register FRAME Field Descriptions uusuusssunneennnnennnnennnnnnnnnen nenne nennen nn nn 117 70 Index Register for Selecting the Endpoint Status and Control Registers INDEX Field Descriptions 117 71 Register to Enable the USB 2 0 Test Modes TESTMODE Field Descriptions nennen nn 118 72 Maximum Packet Size for Peripheral Host Transmit Endpoint TXMAXP Field Descriptions 119 73 Control Status Register for Endpoint 0 in Peripheral Mode PERI_CSRO Field Descriptions 120 74 Control Status Register for Endpoint 0 in Host Mode HOST_CSRO Field Descrtpotons 00 121 75 Control Status Register for Peripheral Transmit Endpoint PERI_TXCSR Field Descriptions sssssssu 122 76 Control Status Register for Host Transmit Endpoint HOST_TXCSR Field Descriptions 0sseeeeeees 123 77 Maximum Packet Size for Peripheral Host Receive Endpoint RXMAXP Field Descriptions ssssaa21 124 78 Control Status Register for Peripheral Receive Endpoint PERI_RXCSR Field Descriptions 125 79 Control Status Register for Host Receive Endpoint HOST_RXCSR Field Descrtotion
128. ees 136 93 Transmit and Receive FIFO Register for Endpoint 4 FIFO4 Field Description 136 94 OTG Device Control Register DEVCTL Field Descriptions cceeeeeeeeee eect ee eeeeeeeeeeeeeeeeeeeeeeaeees 137 95 Transmit Endpoint FIFO Size TXFIFOSZ Field Descriptions ceeceeeeeee eee ences nun nn nnnnn nenn nun 138 96 Receive Endpoint FIFO Size RXFIFOSZ Field Description 138 97 Transmit Endpoint FIFO Address TXFIFOADDR Field Descrtpotions nun nun nenn nn nn 139 98 Receive Endpoint FIFO Address RXFIFOADDR Field Descriptions cceeeeeeeeeeee nenn nn nun nun nun nn 139 99 Transmit Function Address TXFUNCADDR Field Descriptions ceeeeeee eee eee e mann eee ann nenn nenn 140 100 Transmit Hub Address TXHUBADDR Field Descriotons cece eee ee eeeeeeeeeneeeeneeeeneeeneeennes 140 SPRUGH3 November 2008 List of Tables 9 Submit Documentation Feedback 10 IA TEXAS INSTRUMENTS www ti com 101 Transmit Hub Port TXHUBPORT Field Description 140 102 Receive Function Address RXFUNCADDR Field Descriptions ccceeceee eects eeeee eee eeeeeeeeeeeeeeneee 141 103 Receive Hub Address RXHUBADDR Field Descriptions uussunnnennnnnnnnnennnennnnnnnn nenne nenne nennen 141 104 Receive Hub Port RXHUBPORT Field Descriptions 0ceeceeee eee eee teen eee e ee nun nun nun nun nun nnnnan nun 141 A 1 Document Revision Hietonm EEN 143 List of Tables SPRUGH3 November 2008 Submit Documentation Feedback
129. egister AUTOREQ zz 1 2 12 ee as aa en 84 4 5 USB Interrupt Source Register NTGPCH nun nennunn nun 85 4 6 USB Interrupt Source Set Register INTSETR AN 86 4 7 USB Interrupt Source Clear Register NTCLDD nun nun nun 87 4 8 USB Interrupt Mask Register NTMESKPD nen nnannun nun nennunnnnnnunnnnnnnnnnnnnnnnunn nennen 88 4 9 USB Interrupt Mask Set Register INTMSKSETR 0ceeceeeeeee eee nennen seen nun nun nunnnnn nun nun nun nun nun 89 4 10 USB Interrupt Mask Clear Register INTMSKCLRR ceeeeeee sete ee nenn nnnnnn nun nen nun nun nenn an nun nennen 90 4 11 USB Interrupt Source Masked Register INTMASKEDR urusssusnennannnnnnannannnnnnnnnannnnn nun nun nen 91 4 12 USB End of Interrupt Register EOIR a 400er nn in mi 92 4 13 USB Interrupt Vector Register INTVECTR uuusssussannnnnennnannunnunnnan nun nun nunnunnnnnnnnnunn nun nnunnnn nen 92 4 14 Transmit CPPI Control Register TOPPICR zuuruusunnennnannannunnnannannnnnnunnunnnunnnnnennnannnnnnnn nen 93 4 15 Transmit CPPI Teardown Register TCPPITDR eee ee ence eee nun nun nnnnnnnnunnnnnenn nun nun nun nen 93 4 16 CPPIDMA End of Interrupt Register CPPIEOIR 0 ccceeee sees eeee eee eee eee teen e 94 SPRUGH3 November 2008 Table of Contents 3 Submit Documentation Feedback 4 17 4 18 4 19 4 20 4 21 4 22 4 23 4 24 4 25 4 26 4 27 4 28 4 29 4 30 4 31 4 32 4 33 4 34 4 35 4 36 4 37 4 38 4 39 4 40 4 41 4 42 4 43 4 44 4 45 4 4
130. ements DMAs through the buffer descriptor chains stored in main memory The DMA utilizes incrementing addressing mode and can burst up to 64 bytes When a DMA is initiated the DMA controller reads the current parameters for that channel from the DMA registers reads the CPPI buffer descriptor pointed to by the parameters and performs the DMA using the data buffer in the descriptor The DMA controller updates and saves the DMA parameters when the data is completed The software can access the current parameters at any time by accessing the DMA registers The DMA controller has a concept of DMA packets which is different from the USB packets ADMA packet can be but not necessarily of the same size as USB packet Each DMA packet can comprise of one or multiple data buffers Each DMA channel can process one or multiple chains of these DMA packets The controller supports two modes of DMA transparent mode and RNDIS mode Transparent mode will interrupt the CPU for every USB data packet while RNDIS mode can service multiple USB packets with only a single CPU interrupt 3 3 1 DMA Transmit Operation For transmit operation the software has to program the DMA channel with a chain of transmit buffers 3 3 1 1 Transmit Buffer A Transmit buffer is a contiguous block of memory used to store data for transmission Each Tx buffer has a corresponding Tx buffer descriptor Each Tx buffer can be linked together with other Tx buffers to make a DMA packet or a
131. er and transaction scheduler Whether high speed operation is selected will be indicated by HSMODE bit of POWER register bit 4 Host Mode Control Transactions Host Control Transactions are conducted through Endpoint 0 and the software is required to handle all the Standard Device Requests that may be sent or received via Endpoint 0 as described in Universal Serial Bus Specification Revision 2 0 Chapter 9 As for a USB peripheral device there are three categories of Standard Device Requests to be handled Zero Data Requests in which all the information is included in the command Write Requests in which the command will be followed by additional data and Read Requests in which the device is required to send data back to the host 1 Zero Data Requests consist of a SETUP command followed by an IN Status Phase 2 Write Requests consist of a SETUP command followed by an OUT Data Phase which is in turn followed by an IN Status Phase 3 Read Requests consist of a SETUP command followed by an IN Data Phase which is in turn followed by an OUT Status Phase A timeout may be set to limit the length of time for which the controller will retry a transaction which is continually NAKed by the target This limit can be between 2 and 215 frames microframes and is set through the HOST_NAKLIMITO register The following sections describe the CPU actions required for these different types of requests by examining the steps to take in the different
132. errupts INTRUSB uzuusssunnunennnannnannunnnnnnunnunnnunnnnnunnnnn 115 67 Interrupt Enable Register for INTRUSB INTRUSBE eee ee eee tease eee eee eee nun nun nun nun nun nun 116 68 Frame Number Register FRAME AN 117 69 Index Register for Selecting the Endpoint Status and Control Registers NDE NI Ok 70 Register to Enable the USB 2 0 Test Modes TESTMODE ceeceeeeeeeeee eect ee nun nun nun nn nn nun nun nun nn 118 71 Maximum Packet Size for Peripheral Host Transmit Endpoint TXZMANP 119 72 Control Status Register for Endpoint 0 in Peripheral Mode PERI_CSRO A 120 73 Control Status Register for Endpoint 0 in Host Mode HOST CS 121 74 Control Status Register for Peripheral Transmit Endpoint PERI_TXCSR seceeeeeeeeee eee eeeeeeeeenee 122 75 Control Status Register for Host Transmit Endpoint HOST_TXCSR urzunsunnennnnnnnnnnnnnnnnnnnnnnnnn nen 123 76 Maximum Packet Size for Peripheral Host Receive Endpoint RXMAXP uzusssusunnnunnannnnnnunnnnn en nn 124 77 Control Status Register for Peripheral Receive Endpoint PERI_RXCSR cceeeeeeeeeeeee eee eeeeeeeeeeee 125 78 Control Status Register for Host Receive Endpoint HOST_RXCSR ecceeeeeeeee eee eee eeeeeeeeeeeeeeeaeee 126 79 Gount O Register COUNT E 128 80 Receive Count Register DSCOUNT EEN 128 81 Type Register Host mode only HOGT TvVPEO scence eee eee eee eens eee eeee seen eeeeeeeeeeneeeeeeeees 129 82 Transmit Type Register Host mode only
133. erved 0 Reserved 3 0 MASKED COMP_PENDING 0 Fh Masked High Priority Transmit Completion Pending Indicators for channels 3 to 0 Raw Transmit high priority completion indicators bitwise anded with Transmit high priority completion mask bits 4 18 Transmit CPPI Raw Status Register TCPPIRAWSR The Transmit CPPI Raw Status Register TCPPIRAWSR is shown in Figure 33 and described in Table 34 Figure 33 Transmit CPPI Raw Status Register TCPPIRAWSR 31 16 Reserved Ho 15 4 3 0 Reserved COMP_PENDING R 0 R 0 LEGEND R Read only n value after reset Table 34 Transmit CPPI Raw Status Register TCPPIRAWSR Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 0 COMP_PENDING 0 Fh Raw High Priority Transmit Completion Pending Indicators for channels 3 to 0 Active high flags which indicate that a packet has completed transmission on the high priority queue SPRUGH3 November 2008 Universal Serial Bus USB Controller 95 Submit Documentation Feedback I TEXAS INSTRUMENTS Registers www ti com 4 19 Transmit CPPI Interrupt Enable Set Register TCPPIIENSETR The Transmit CPPI Interrupt Enable Set Register TCPPIIENSETR is shown in Figure 34 and described in Table 35 Figure 34 Transmit CPPI Interrupt Enable Set Register TCPPIIENSETR 31 16 Reserved R 0 15 4 3 0 Reserved COMP_PENDING_INTR_EN R 0 R W 0
134. et the STATUS Phase has been correctly ACKed Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation Figure 13 Completion of IN Data Phase Flow Chart NAK limit reached No Error count cleared Yes Yes NAK Timeout set Endpoint halted Interrupt generated No Completion of IN data phase TxPktRdy and StatusPkt both set OUT token sent Zero length DATA1 packet sent an Stall received No ACK received No NAK received No Error count incremented SPRUGH3 November 2008 Submit Documentation Feedback Sal No Yes Yes Yes Command could not be completed RxStall set TxPktRdy cleared Error Count cleared interrupt generated TxPktRdy cleared Error Count cleared Interrupt generated Transaction complete Implies problem at peripheral end of connection Transaction deemed complete Error bit set TxPktRdy cleared Error Count cleared interrupt generated Universal Serial Bus USB Controller 51 I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com 3 2 2 Bulk Transactions 3 2 2 1 Host Mode Bulk IN Transactions A Bulk IN transaction may be used to transfer non periodic data from the external USB peripheral to the host
135. ferent endpoints requires the specification for each Tx and Rx endpoint of e The start address of the FIFO within the RAM block e The maximum size of packet to be supported e Whether double buffering is required These details are specified through four registers which are added to the indexed area of the memory map That is the registers for the desired endpoint are accessed after programming the INDEX register with the desired endpoint value Section 4 79 Section 4 80 Section 4 81 and Section 4 82 provide details of these registers Note The option of setting FIFO sizes dynamically only applies to Endpoints 1 4 Endpoint 0 FIFO has a fixed size 64 bytes and a fixed location start address 0 It is the responsibility of the firmware to ensure that all the Tx and Rx endpoints that are active in the current USB configuration have a block of RAM assigned exclusively to that endpoint that is at least as large as the maximum packet size set for that endpoint USB Controller Host and Peripheral Modes Operation The USB controller can be used in a range of different environments It can be used as either a high speed or a full speed USB peripheral device attached to a conventional USB host such as a PC It can be used as either host or peripheral device in point to point data transfers with another peripheral device or if the other device also contains a Dual Role Controller the two devices can switch roles as required This se
136. ftware The software may continue Rx queue processing until the end of the queue or until a buffer descriptor is read that contains a set Ownership bit indicating that the next packet s reception is not complete The software determines that the Rx queue is empty when the last packet in the queue has a cleared Ownership bit in the SOP buffer descriptor a set End of Queue bit in the EOP buffer descriptor and the Next Descriptor Pointer in the EOP buffer descriptor is zero The software acknowledges an interrupt by writing the address of the last buffer descriptor to the queue s associated Rx Completion Pointer RCPPICOMPPTR register If the software written buffer address value in RCCPICOMPPTR register is different from the buffer address written by the DMA controller after Rx completion then the interrupt for the Rx Channel remains asserted If the software written buffer address value matches with the buffer address written by the DMA controller the Rx Channel interrupt gets deasserted A misqueued buffer may occur when the software adds buffers to a queue as the DMA controller finishes the reception of the previous last packet in the queue The misqueued buffer is detected by the software when queue processing detects a cleared Ownership bit in the SOP buffer descriptor a set End of Queue bit in the EOP buffer descriptor and a nonzero Next Descriptor Pointer in the EOP buffer descriptor A misqueued buffer means that the DMA controller read
137. hat the controller should never respond with a NYET handshake only ACK NAK STALL To ensure this the DISNYET bit in the PERI_RXCSR register bit 12 should be set to disable the transmission of NYET handshakes in high speed mode Though DMA can be used with an interrupt OUT endpoint it generally offers little benefit as interrupt endpoints are usually expected to transfer all their data in a single packet Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation 3 1 4 Isochronous Transactions 3 1 4 1 Isochronous IN Transactions An Isochronous IN transaction is used to transfer periodic data from the function controller to the host The following optional features are available for use with a Tx endpoint used in Peripheral mode for Isochronous IN transactions e Double packet buffering When enabled up to two packets can be stored in the FIFO awaiting transmission to the host Double packet buffering is enabled by setting the DPB bit of TXFIFOSZ register bit 4 Note Double packet buffering is generally advisable for Isochronous transactions in order to avoid Underrun errors as described in later section e DMA If DMA is enabled for the endpoint a DMA request will be generated whenever the endpoint is able to accept another packet in its FIFO This feature allows the DMA controller to load packets into th
138. hat the request completed successfully If the command is an unrecognized command or for some other reason cannot be executed then when it has been decoded the PERI_CSRO register should be written to set the SERV_RXPKTRDY bit bit 6 and to set the SENDSTALL bit bit 5 When the host requests data the controller will send a STALL to tell the host that the request was not executed An endpoint 0 interrupt will be generated and the SENTSTALL bit of PERI_CSRO bit 2 will be set If the host requests more data after DATAEND bit 3 has been set then the controller will send a STALL An endpoint 0 interrupt will be generated and the SENTSTALL bit of PERI_CSRO bit 2 will be set Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation 3 1 1 4 Endpoint 0 States When the USB controller is operating as a peripheral device the endpoint 0 control needs three modes IDLE TX and RX corresponding to the different phases of the control transfer and the states endpoint 0 enters for the different phases of the transfer described in later sections The default mode on power up or reset should be IDLE RXPKTRDY bit of PERI_CSRO bit 0 becoming set when endpoint 0 is in IDLE state indicates a new device request Once the device request is unloaded from the FIFO the controller decodes the descriptor to find whether there is a data
139. he ARM or DSP CPUs does not affect the register values and operation of the USB controller Hardware Reset Considerations When a hardware reset is asserted all the registers are set to their default values USB Reset Considerations When operating in peripheral mode a USB reset received from the host causes some internal registers to be reset The USB controller setup operations for example FIFO sizing in peripheral mode should be performed after receiving the USB reset and again on each subsequent USB reset There are some conditions where multiple USB reset interrupts may be received in rapid succession Good interrupt handling practices must be observed to assure that the setup is performed again after the final USB reset interrupt Software must teardown any TX DMA channel use upon receipt of a USB reset See Section 3 3 2 8 Interrupt Support The USB peripheral presents a single interrupt to the ARM interrupt controller AINTC For information on the mapping of interrupts refer to the device specific data manual EDMA Event Support The USB is an internal bus master peripheral and therefore does not utilize any EDMA events The registers support only individual access Bursting data to or from the USB register space through EDMA is not supported Power Management The USB controller can be placed in reduced power modes to conserve power during periods of low activity The power management of the peripheral is controlled by t
140. he Receive CPPI Control Register RCPPICR is shown in Figure 36 and described in Table 37 Figure 36 Receive CPPI Control Register RCPPICR 31 16 Reserved HO 15 1 o Reserved RCPPI_ENABLE R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 37 Receive CPPI Control Register RCPPICR Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 RCPPI_ENABLE Receive CPPI Enable Controls if the Receive CPPI DMA controller is enabled Be sure to program the CPPI chain and set the DMA state words before enabling the DMA Failure to initialize the DMA before enabling could result in spurious transfers and memory corruption 0 Receive CPPI DMA is disabled Receive CPPI DMA is enabled 4 22 Receive CPPI Masked Status Register RCPPIMSKSR The Receive CPPI Masked Status Register RCPPIMSKSR is shown in Figure 37 and described in Table 38 Figure 37 Receive CPPI Masked Status Register RCPPIMSKSR 31 16 Reserved R 0 15 4 3 0 Reserved MASKED_COMP_PENDING R 0 R 0 LEGEND R Read only n value after reset Table 38 Receive CPPI Masked Status Register RCPPIMSKSR Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 0 MASKED_COMP_PENDING 0 Fh Masked Receive Completion Pending Indicators for channels 3 to 0 Raw Receive completion indicators bitwise ANDed with Receive completion
141. he SPEED bit field bits 7 and 6 Set 01 binary value in the PROT field for isochronous transfer Endpoint Number of the target device in TENDPN field This is the endpoint number contained in the OUT Tx endpoint descriptor returned by the target device during enumeration The TXMAXP register for the controller endpoint must be written with the maximum packet size in bytes for the transfer This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the target endpoint The HOST_TXINTERVAL register needs to be written with the required transaction interval usually one transaction per frame microframe The relevant interrupt enable bit in the INTRTXE register should be set if an interrupt is required for this endpoint The following bits of HOST_TXCSR register should be set as shown below Set the MODE bit bit 13 to 1 to ensure the FIFO is enabled only necessary if the FIFO is shared with an Rx endpoint Set the DMAEN bit bit 12 to 1 if a DMA request is required for this endpoint The FRCDATATOG bit bit 12 is ignored for isochronous transactions Set the DMAMODE bit bit 10 to 1 when DMA is enabled and the endpoint interrupt is not needed for each packet transmission 56 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation 3 2 4 2 2 O
142. he processor Power and Sleep Controller PSC The PSC acts as a master controller for power management for all of the peripherals on the device For detailed information on power management procedures using the PSC see the TMS320DMxxx DMSoC ARM Subsystem Reference Guide spru856 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback l TEXAS INSTRUMENTS www ti com 4 Registers Table 16 lists the memory mapped registers for the universal serial bus USB See the device specific data manual for the memory address of these registers The base address is 01C6 4000h Registers Note In some cases a single register address can have different names or meanings depending on the mode host peripheral or the setting of the index register The meaning of some bit fields varies with the mode Table 16 Universal Serial Bus USB Registers Offset Acronym Register Description Section 4h CTRLR Control Register Section 4 1 8h STATR Status Register Section 4 2 10h RNDISR RNDIS Register Section 4 3 14h AUTOREQ Autorequest Register Section 4 4 20h INTSRCR USB Interrupt Source Register Section 4 5 24h INTSETR USB Interrupt Source Set Register Section 4 6 28h INTCLRR USB Interrupt Source Clear Register Section 4 7 2Ch INTMSKR USB Interrupt Mask Register Section 4 8 30h INTMSKSETR USB Interrupt Mask Set Register Section 4 9 34h INTMSKCLRR USB Interrupt Mask Clear Register Section 4 10 38h INTMASKEDR
143. her quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive busine
144. hese are active high interrupt enables corresponding to the Receive CPPI Completion Pending status bits Writing a 1 to any of the bits in the Receive CPPI Interrupt Enable Set Register will result in setting of the corresponding bit in the Receive CPPI Interrupt Enable Register 98 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 25 Receive CPPI Interrupt Enable Clear Register RCPPIIENCLRR The Receive CPPI Interrupt Enable Clear Register RCPPIIENCLRR is shown in Figure 40 and described in Table 41 Figure 40 Receive CPPI Interrupt Enable Clear Register RCPPIIENCLRR 31 16 Reserved R 0 15 4 3 0 Reserved COMP_PENDING_INTR_EN R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 41 Receive CPPI Interrupt Enable Clear Register RCPPIIENCLRR Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved 3 0 COMP_PENDING_INTR_EN 0 Fh Receive CPPI Interrupt Enables These are active high interrupt enables corresponding to the Receive CPPI Completion Pending status bits Writing a 1 to any of the bits in the Receive CPPI Interrupt Enable Clear Register will result in clearing of the corresponding bit in the Receive CPPI Interrupt Enable Register 4 26 Receive Buffer Count 0 Register RBUFCNTO The Receive Buffer Count 0 Register RBUFCNT
145. his bit twice in succession if double buffering is enabled SPRUGH3 November 2008 Universal Serial Bus USB Controller 37 Submit Documentation Feedback I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com 3 1 2 1 2 Operation When data is to be transferred over a Bulk IN pipe a data packet needs to be loaded into the FIFO and the PERI_TXCSR register written to set the TXPKTRDY bit bit 0 When the packet has been sent the TXPKTRDY bit will be cleared by the USB controller and an interrupt generated so that the next packet can be loaded into the FIFO If double packet buffering is enabled then after the first packet has been loaded and the TXPKTRDY bit set the TXPKTRDY bit will immediately be cleared by the USB controller and an interrupt generated so that a second packet can be loaded into the FIFO The software should operate in the same way loading a packet when it receives an interrupt regardless of whether double packet buffering is enabled or not In the general case the packet size must not exceed the size specified by the lower 11 bits of the TXMAXP register This part of the register defines the payload packet size for transfers over the USB and is required by the USB Specification to be either 8 16 32 64 Full Speed or High Speed or 512 bytes High Speed only The host may determine that all the data for a transfer has been sent by knowing the total amount of data that is expected Altern
146. icroframes High Speed transfers as follows Transfer Type Speed Valid values m Interpretation Interrupt Low Speed or Full Speed 1 255 Polling interval is m frames High Speed 1 16 Polling interval is 21 microframes Isochronous Full Speed or High Speed 1 16 Polling interval is 21 frames microframes Bulk Full Speed or High Speed 2 16 NAK Limit is 27 frames microframes Note A value of 0 or 1 disables the NAK timeout function 4 72 Configuration Data Register CONFIGDATA The configuration data register CONFIGDATA is shown in Figure 87 and described in Table 88 Figure 87 Configuration Data Register CONFIGDATA 7 6 5 4 3 2 1 0 MPRXE MPTXE BIGENDIAN HBRXE HBTXE DYNFIFO SOFTCONE UTMIDATAWIDTH R 0 HO R 0 R 0 R 0 R 1 R 1 HO LEGEND R Read only n value after reset Table 88 Configuration Data Register CONFIGDATA Field Descriptions Bit Field Value Description 7 MPRXE Indicates automatic amalgamation of bulk packets 0 Automatic amalgamation of bulk packets is not selected 1 Automatic amalgamation of bulk packets is selected 6 MPTXE Indicates automatic splitting of bulk packets 0 Automatic splitting of bulk packets is not selected 1 Automatic splitting of bulk packets is selected 5 BIGENDIAN Indicates endian ordering 0 Little endian ordering is selected 1 Big endian ordering is selected 4 HBRXE Indicates high bandwidth Rx ISO endpoint su
147. ield RXn_AUTOREQ where n is the endpoint number with binary value 01 or 11 Operation The operation starts with the software setting REQPKT bit of HOST_RXCSR bit 5 This causes the controller to send an IN token to the target When a packet is received an interrupt is generated which the software may use to unload the packet from the FIFO and clear the RXPKTRDY bit in the HOST_RXCSR register bit 0 in the same way as for a Bulk Rx endpoint As the interrupt could occur almost any time within a frame microframe the timing of SPRUGH3 November 2008 Universal Serial Bus USB Controller 55 Submit Documentation Feedback I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com FIFO unload requests will probably be irregular If the data sink for the endpoint is going to some external hardware it may be better to minimize the requirement for additional buffering by waiting until the end of each frame before unloading the FIFO This can be done by using the SOF_PULSE signal from the controller to trigger the unloading of the data packet The SOF_PULSE is generated once per frame microframe The interrupts may still be used to clear the RXPKTRDY bit in HOST_RXCSR 3 2 4 1 3 Error Handling If a CRC or bit stuff error occurs during the reception of a packet the packet will still be stored in the FIFO but the DATAERR_NAKTIMEOUT bit of HOST_RXCSR bit 3 is set to indicate that the data may be corrupt 3 2
148. ield in the command is greater than the maximum packet size for endpoint 0 further data packets will be sent In this case PERI_CSRO should be written to set the SERV_RXPKTRDY bit but the DATAEND bit should not be set When all the expected data packets have been received the PERI_CSRO register should be written to set the SERV_RXPKTRDY bit and to set the DATAEND bit indicating that no more data is expected When the host moves to the status stage of the request another endpoint 0 interrupt will be generated to indicate that the request has completed No further action is required from the software the interrupt is just a confirmation that the request completed successfully If the command is an unrecognized command or for some other reason cannot be executed then when it has been decoded the PERI_CSRO register should be written to set the SERV_RXPKTRDY bit bit 6 and to set the SENDSTALL bit bit 5 When the host sends more data the controller will send a STALL to tell the host that the request was not executed An endpoint 0 interrupt will be generated and the SENTSTALL bit of PERI_CSRO bit 2 will be set If the host sends more data after the DATAEND has been set then the controller will send a STALL An endpoint 0 interrupt will be generated and the SENTSTALL bit of PERI_CSRO bit 2 will be set 3 1 1 3 Read Requests 28 Read requests have a packet or packets of data sent from the function to the host after the 8 byte com
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150. ill send a null data packet to the host and set the UNDERRUN bit in the PERI_TXCSR register bit 2 This is an indication that the software is not supplying data fast enough for the host It is up to the application to determine how this error condition is handled If the software is loading one packet per frame microframe and it finds that the TXPKTRDY bit in the PERI_TXCSR register bit 0 is set when it wants to load the next packet this indicates that a data packet has not been sent perhaps because an IN token from the host was corrupted It is up to the application how it handles this condition it may choose to flush the unsent packet by setting the FLUSHFIFO bit in the PERI_TXCSR register bit 3 or it may choose to skip the current packet 3 1 4 2 Isochronous OUT Transactions 42 An Isochronous OUT transaction is used to transfer periodic data from the host to the function controller Following optional features are available for use with an Rx endpoint used in Peripheral mode for Isochronous OUT transactions e Double packet buffering When enabled up to two packets can be stored in the FIFO on reception from the host Double packet buffering is enabled by setting the DPB bit of RXFIFOSZ register bit 4 Note Double packet buffering is generally advisable for Isochronous transactions in order to avoid Overrun errors e DMA If DMA is enabled for the endpoint a DMA request will be generated whenever the endpoint has a p
151. ing interval for Interrupt ISOC transactions or the Section 4 69 NAK response timeout on Bulk transactions for host Transmit endpoint 53Ch HOST_RXTYPE Sets the operating speed transaction protocol and peripheral Section 4 70 endpoint number for the host Receive endpoint 53Dh HOST_RXINTERVAL Sets the polling interval for Interrupt ISOC transactions or the Section 4 71 NAK response timeout on Bulk transactions for host Receive endpoint Control and Status Register for Endpoint 4 540h TXMAXP Maximum Packet Size for Peripheral Host Transmit Endpoint Section 4 56 542h PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint Section 4 59 peripheral mode HOST_TXCSR Control Status Register for Host Transmit Endpoint Section 4 60 host mode 544h RXMAXP Maximum Packet Size for Peripheral Host Receive Endpoint Section 4 61 SPRUGH3 November 2008 Universal Serial Bus USB Controller 81 Submit Documentation Feedback I TEXAS INSTRUMENTS Registers www ti com Table 16 Universal Serial Bus USB Registers continued Offset Acronym Register Description Section 546h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint Section 4 62 peripheral mode HOST_RXCSR Control Status Register for Host Receive Endpoint Section 4 63 host mode 548h RXCOUNT Number of Bytes in Host Receive endpoint FIFO Section 4 65 54Ah HOST_TXTYPE Sets the operating spee
152. int 0 in Peripheral Mode PERI_CSRO The Control Status Register for Endpoint 0 in Peripheral Mode PERI_CSRO is shown in Figure 72 and described in Table 73 Figure 72 Control Status Register for Endpoint 0 in Peripheral Mode PERI_CSRO 15 9 8 Reserved FLUSHFIFO HO WO T 6 5 4 3 2 1 0 SERV_SETUPEND SERV_RXPKTRDY SENDSTALL SETUPEND DATAEND SENTSTALL TXPKTRDY RXPKTRDY W 0 W 0 W 0 HO WO R W 0 R W 0 HO LEGEND R W Read Write R Read only W Write only n value after reset Table 73 Control Status Register for Endpoint 0 in Peripheral Mode PERI_CSRO Field Descriptions Bit Field Value Description 15 9 Reserved 0 Reserved 8 FLUSHFIFO 0 1 Set this bit to flush the next packet to be transmitted read from the Endpoint 0 FIFO The FIFO pointer is reset and the TXPKTRDY RXPKTRDY bit is cleared Note FLUSHFIFO has no effect unless TXPKTRDY RXPKTRDY is set 7 SERV_SETUPEND 0 1 Set this bit to clear the SETUPEND bit It is cleared automatically SERV_RXPKTRDY 0 1 Set this bit to clear the RXPKTRDY bit It is cleared automatically 5 SENDSTALL 0 1 Set this bit to terminate the current transaction The STALL handshake will be transmitted and then this bit will be cleared automatically 4 SETUPEND 0 1 This bit will be set when a control transaction ends before the DATAEND bit has been set An interrupt will be generated and the FIFO will be flushed at
153. ion until it times out again by clearing the NAK_TIMEOUT bit or to abort the transaction by clearing REQPKT bit and STATUSPKT bit before clearing the NAK_TIMEOUT bit If RxPktRdy has been set the CPU should simply clear RxPktRdy OUT Siatus Phase following IN Data Phase Set STATUSPKT and TXPKTRDY bits of HOST_CSRO bit 6 and bit 1 respectively Note These bits need to be set together Wait while the controller sends the OUT token and a zero length DATA1 packet At the end of the attempt to send the data the controller will generate an Endpoint 0 interrupt The software should then read HOST_CSRO to establish whether the RXSTALL bit bit 2 the ERROR bit bit 4 or the NAK_TIMEOUT bit bit 7 has been set If RXSTALL bit is set it indicates that the target could not complete the command and so has issued a STALL response If ERROR bit is set it means that the controller has tried to send the STATUS Packet and the following data packet three times without getting any response If NAK_TIMEOUT bit is set it means that the controller has received a NAK response to each attempt to send the IN token for longer than the time set in the HOST_NAKLIMITO register The controller can then be directed either to continue trying this transaction until it times out again by clearing the NAK_TIMEOUT bit or to abort the transaction by flushing the FIFO before clearing the NAK_TIMEOUT bit If none of RXSTALL ERROR or NAK_TIMEOUT bits is s
154. ional Block DidGraMicsicssevanenaiaianacaveeaeravevavauaves ats vet beyeuedeievesaluratenveiavasehevabunatdaeetay agama 15 2 Interrupt Service Routine Flow Chat 25 3 GPU Actions at Transfer Phases2 2 is een aan ee em 29 4 Seq ence of Transter ne ee 30 5 service Endpoint 0 FloWGCh ftei u uun see ae ana len d 32 6 IDLE Mode Flow Chart ugedo snes wie aan sn na En EES EEN ENER Ca 33 7 TX Mode Flow bat estie egegetN SN d ENEE na a a anna aa ann an a nn na EE eu deeg EE 34 8 RX Mode Flower ouetiegeteeetegsgeee goe EEN n ET Rein 35 9 Setup Phase of a Control Transaction Flow Chart 45 10 IND ates Phase Eeer dee 47 11 OUT Data Phase FLOW ET E 48 12 Completion of SETUP or OUT Data Phase Flow Chart 49 13 Completion of IN Data Phase Flow Chart 51 14 TX ele Uer TEE 60 15 EH Halt ae a BE ea ee 65 16 Control Register CTRLRY un m lan 82 17 SIALUS Register ST AMIR E 83 18 RNDIS Register RNDISR s 4 2 54 5 4 50 2280020000002 NEESS ea aa an EIER a a an a a an a ann nalen 83 19 Auto Request Register AUTOREQ zzuusnsnnannnannannannnannannannnannannnunnannunnnannnnn nun nannnun nun nannnen 84 20 USB Interrupt Source Register INTSRCR zuusuuunnannnnnannnannunnannnannannnnnnannannnunnannannnannannannnen 85 21 USB Interrupt Source Set Register INTSETR ENEE EEN 86 22 USB Interrupt Source Clear Register ONTCLDR eee eeeeeee eee eee eee eeeeeeeneeeeeeeeeeeeeeeeeeeee 87 23 USB Interrupt Mask Register INTMSKR 0
155. is empty This bit is valid only on when EOP is set 0 The Tx queue has more packets to transfer 1 The DMA controller took this descriptor buffer as the last buffer descriptor in the last packet in the queue 27 24 Reserved Reserved 23 Zero Byte Zero Byte Packet Identifier This bit is set by the software when a zero byte USB packet needs to be transmitted This bit tells the DMA controller that no data transfer needs to be done for transmitting this zero byte data buffer Set the Packet Length to 1 when setting this bit 22 16 Reserved Reserved 15 0 Packet Length The length of the DMA packet in bytes This field is valid only on SOP and is written by the software If the Packet Length is less than the sum of the buffer lengths then the packet data will be truncated A Packet Length greater than the sum of the buffers is a software error Packet Length must be nonzero Set to one when setting the Zero Byte bit Four different cases are possible for the number of buffers in a DMA packet 1 Buffer Descriptor contains Start of Packet field and End of Packet field 1 buffer in DMA packet 2 Buffer Descriptor contains Start of Packet field only 2 buffers in DMA packet 3 Buffer Descriptor contains End of Packet field only 2 buffers in DMA packet 4 Buffer Descriptor does not contain either of Start of Packet field and End of Packet field 3 buffers in packet 3 3 1 3 Transmit DMA State The DMA controller stores and maintains stat
156. ister STATR 31 16 Reserved HO 15 1 0 Reserved DRVVBUS R 0 R 0 LEGEND R Read only n value after reset Table 18 Status Register STATR Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved 0 DRVVBUS Current DRVVBUS value 0 DRVVBUS value is logic 0 1 DRVVBUS value is logic 1 4 3 RNDIS Register RNDISR The RNDIS Register RNDISR is shown in Figure 18 and described in Table 19 Figure 18 RNDIS Register RNDISR 31 20 19 18 17 16 Reserved RX4EN RX3EN RX2EN RX1EN R 0 R W 0 R W 0 R W 0 RIW 0 15 4 3 2 1 0 Reserved TX4EN TX3EN TX2EN TX1EN R 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 19 RNDIS Register RNDISR Field Descriptions Bit Field Value Description 31 20 Reserved 0 Reserved 19 RX4EN 0 1 Receive Endpoint 4 RNDIS mode enable 18 RX3EN 0 1 Receive Endpoint 3 RNDIS mode enable 17 RX2EN 0 1 Receive Endpoint 2 RNDIS mode enable 16 RX1EN 0 1 Receive Endpoint 1 RNDIS mode enable 15 4 Reserved 0 Reserved 3 TX4EN 0 1 Transmit Endpoint 4 RNDIS mode enable 2 TX3EN 0 1 Transmit Endpoint 3 RNDIS mode enable 1 TX2EN 0 1 Transmit Endpoint 2 RNDIS mode enable 0 TX1EN 0 1 Transmit Endpoint 1 RNDIS mode enable SPRUGH3 November 2008 Universal Serial Bus USB Controller
157. ite zeroes to all Tx DMA State registers TCPPIDMASTATEWO TCPPIDMASTATEW1 TCPPIDMASTATEW2 TCPPIDMASTATEW3 TCPPIDMASTATEW4 TCPPIDMASTATEWS e The software constructs transmit queue in memory one or more DMA Packets in for transmission e Enable DMA for the endpoint in the PERI_TXCSR or HOST_TXCSR by setting the DMAEN bit e Enable the DMA ports by setting TCPPI_ENABLE bit of TCPPICR register e Set RNDIS bit of CTRLR register for enabling RNDIS mode for all channels or set TXnEN bit of RNDISR register for specific DMA channel n e Write the head of the queue descriptor pointer to the TCPPIDMASTATEWO register to start the DMA e The USB controller will start transmitting data e If the DMA packet size is exact multiple of USB MaxPktSize a zero byte packet is transmitted and interrupt associated with the DMA channel is asserted e If the DMA packet size is not exact multiple of USB MaxPktSize the last USB packet transmitted is a short packet and interrupt associated with the DMA channel is asserted Transparent Mode Setup Transparent DMA configuration is identical to RNDIS DMA configuration with the exception of the followings Each packet is defined by a single buffer descriptor with SOP and EOP bit fields set Packet size is not bounded to be a multiple of 64 byte but by max packet size CTRLR RNDIS bit field should be cleared to zero 3 3 1 7 DMA Channel TearDown 3 3 2 The DMA also supports a teardown operation on TX channels
158. iversal Serial Bus USB Controller 105 Submit Documentation Feedback JA TEXAS INSTRUMENTS Registers www ti com Figure 53 Receive CPPI DMA State Word 1 RCPPIDMASTATEWI 31 16 RXQ_HEAD_PTR R W 0 15 2 1 0 RXQ_HEAD_PTR Reserved R W 0 HO LEGEND R W Read Write R Read only n value after reset Table 54 Receive CPPI DMA State Word 1 RCPPIDMASTATEWI Field Descriptions Bit Field Value Description 31 2 RXQ_HEAD_PTR 0 1FFF FFFFh Receive Queue Head Pointer 30 bit pointer to 32 bit aligned descriptor at the head of the Receive queue 1 0 Reserved 0 Reserved 106 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 39 Receive CPPI DMA State Word 2 RCPPIDMASTATEW2 The Receive CPPI DMA State Word 2 RCPPIDMASTATEW2 is shown in Figure 54 and described in Table 55 Figure 54 Receive CPPI DMA State Word 2 RCPPIDMASTATEW2 31 16 SOP_DESCRIPTOR_PTR R W 0 15 2 1 0 SOP_DESCRIPTOR_PTR Reserved IN_ PACKET R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 55 Receive CPPI DMA State Word 2 RCPPIDMASTATEW2 Field Descriptions Bit Field Value Description 31 2 SOP_DESCRIPTOR_PTR 0 1FFF FFFFh Start of Packet Buffer Descriptor Pointer 30 bit pointer to 32 bit aligned descriptor which is the first descriptor for the
159. l be started and no SOF packets will be generated If the ENSUSPM bit bit 0 of POWER register is set PHY will go into low power mode when the controller enters Suspend mode e Sending Resume Signaling When the application requires the controller to leave Suspend mode it must clear the SUSPENDM bit in the POWER register bit 1 set the RESUME bit bit 2 and leave it set for 20ms While the RESUME bit is high the controller will generate Resume signaling on the bus After 20 ms the application should clear the Resume bit at which point the frame counter and transaction scheduler will be started e Responding to Remote Wake up If Resume signaling is detected from the target while the controller is in Suspend mode the PHY will be brought out of low power mode The controller will then exit Suspend mode and automatically set the RESUME bit in the POWER register bit 2 to take over generating the Resume signaling from the target If the Resume interrupt is enabled an interrupt will be generated e Reset Signaling lf the RESET bit in the POWER register bit 3 is set while the controller is in Host mode it will generate Reset signaling on the bus If the HSENAB bit in the POWER register bit 5 was set it will also try to negotiate for high speed operation The software should keep the RESET bit set for at least 20 ms to ensure correct resetting of the target device After the software has cleared the bit the controller will start its frame count
160. ly triggered 15 13 Reserved 0 Reserved 12 8 RX 0 1Fh Write a 1 to set equivalent Receive endpoint interrupt source Allows the USB interrupt sources to be manually triggered 7 5 Reserved 0 Reserved 4 0 TX 0 Fh Write a 1 to set equivalent Transmit endpoint interrupt source Allows the USB interrupt sources to be manually triggered 86 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com 4 7 USB Interrupt Source Clear Register INTCLRR The USB Interrupt Source Clear Register INTCLRR is shown in Figure 22 and described in Table 23 31 25 24 Registers Figure 22 USB Interrupt Source Clear Register INTCLRR 16 Reserved USB 15 R 0 13 12 8 7 5 WO Reserved RX Reserved TX R 0 W 0 R 0 LEGEND R Read only W Write only n value after reset W 0 Table 23 USB Interrupt Source Clear Register INTCLRR Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 16 USB 0 1FFh Write a 1 to clear equivalent USB interrupt source Allows the CPU to acknowledge an interrupt source and turn it off 15 13 Reserved 0 Reserved 12 8 RX 0 1Fh Write a 1 to clear equivalent Receive endpoint interrupt source Allows the CPU to acknowledge an interrupt source and turn it off 7 5 Reserved 0 Reserved 4 0 TX 0 Fh Write a 1 to cle
161. ly when full speed or low speed device is connected via a USB2 0 high speed hub 4A7h RXHUBPORT Port of the hub that has to be accessed through the Section 4 88 associated Receive Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub Control and Status Register for Endpoint 0 502h PERI_CSRO Control Status Register for Endpoint 0 in Peripheral Mode Section 4 57 HOST_CSRO Control Status Register for Endpoint 0 in Host Mode Section 4 58 508h COUNTO Number of Received Bytes in Endpoint 0 FIFO Section 4 64 50Ah HOST_TYPEO Defines the Speed of Endpoint 0 Section 4 66 50Bh HOST_NAKLIMITO Sets the NAK Response Timeout on Endpoint 0 Section 4 68 50Fh CONFIGDATA Returns details of core configuration Section 4 72 Control and Status Register for Endpoint 1 510h TXMAXP Maximum Packet Size for Peripheral Host Transmit Endpoint Section 4 56 512h PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint Section 4 59 peripheral mode HOST_TXCSR Control Status Register for Host Transmit Endpoint Section 4 60 host mode 514h RXMAXP Maximum Packet Size for Peripheral Host Receive Endpoint Section 4 61 516h PERI_RXCSR Control Status Register for Peripheral Receive Endpoint Section 4 62 peripheral mode HOST_RXCSR Control Status Register for Host Receive Endpoint Section 4 63 host mode 518h RXCOUNT Number of Bytes in Host Receive endpoint FIFO Section 4 65 51Ah HOST_TXTYPE Sets the operating speed transa
162. mand Examples of Read Standard Device Requests are e GET_CONFIGURATION e GET_INTERFACE e GET_DESCRIPTOR e GET_STATUS e SYNCH_FRAME The sequence of events will begin as with all requests when the software receives an endpoint 0 interrupt The RXPKTRDY bit of PERI_CSRO bit 0 will also have been set The 8 byte command should then be read from the endpoint 0 FIFO and decoded The PERI_CSRO register should then be written to set the SERV_RXPKTRDY bit bit 6 indicating that the command has read from the FIFO The data to be sent to the host should then be written to the endpoint 0 FIFO If the data to be sent is greater than the maximum packet size for endpoint 0 only the maximum packet size should be written to the FIFO The PERI_CSRO register should then be written to set the TXPKTRDY bit bit 1 indicating that there is a packet in the FIFO to be sent When the packet has been sent to the host another endpoint 0 interrupt will be generated and the next data packet can be written to the FIFO When the last data packet has been written to the FIFO the PERI_CSRO register should be written to set the TXPKTRDY bit and to set the DATAEND bit bit 3 indicating that there is no more data after this packet When the host moves to the status stage of the request another endpoint 0 interrupt will be generated to indicate that the request has completed No further action is required from the software the interrupt is just a confirmation t
163. me microframe when a SOF packet is received The controller also maintains an external frame microframe counter so it can still generate a SOF_PULSE when the SOF packet has been lost The interrupts may still be used to clear the RXPKTRDY bit in PERI_RXCSR and to check for data overruns underruns 3 1 4 2 3 Error Handling If there is no space in the FIFO to store a packet when it is received from the host the OVERRUN bit in the PERI_LRXCSR register bit 2 will be set This is an indication that the software is not unloading data fast enough for the host It is up to the application to determine how this error condition is handled If the controller finds that a received packet has a CRC error it will still store the packet in the FIFO and set the RXPKTRDY bit bit 0 of PERI_RXCSR and the DATAERROR bit bit 3 of PERI_LRXCSR It is left up to the application how this error condition is handled SPRUGH3 November 2008 Universal Serial Bus USB Controller 43 Submit Documentation Feedback I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com 3 2 3 2 1 44 USB Controller Host Mode Operation e Entry into Suspend mode When operating as a host the controller can be prompted to enter Suspend mode by setting the SUSPENDM bit in the POWER register When this bit is set the controller will complete the current transaction then stop the transaction scheduler and frame counter No further transactions wil
164. mission 3 1 4 1 2 Operation An Isochronous endpoint does not support data retries so if data underrun is to be avoided the data to be sent to the host must be loaded into the FIFO before the IN token is received The host will send one IN token per frame or microframe in High speed mode however the timing within the frame or microframe can vary H an IN token is received near the end of one frame and then at the start of the next frame there will be little time to reload the FIFO For this reason double buffering of the endpoint is usually necessary SPRUGH3 November 2008 Universal Serial Bus USB Controller 41 Submit Documentation Feedback I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com An interrupt is generated whenever a packet is sent to the host and the software may use this interrupt to load the next packet into the FIFO and set the TXPKTRDY bit in the PERI_TXCSR register bit 0 in the same way as for a Bulk Tx endpoint As the interrupt could occur almost any time within a frame microframe depending on when the host has scheduled the transaction this may result in irregular timing of FIFO load requests If the data source for the endpoint is coming from some external hardware it may be more convenient to wait until the end of each frame microframe before loading the FIFO as this will minimize the requirement for additional buffering This can be done by using either the SOF interrup
165. n 3 5 6 FORCE_HOST The Force Host test mode enables the user to instruct the core to operate in Host mode regardless of whether it is actually connected to any peripheral i e the state of the CID input and the LINESTATE and HOSTDISCON signals are ignored While in this mode the state of the HOSTDISCON signal can be read from bit 7 of the DevCtl register This mode which is selected by setting bit 7 within the Testmode register allows implementation of the USB Test_Force_Enable 7 1 20 It can also be used for debugging PHY problems in hardware While the Force_Host bit remains set the core will enter Host mode when the Session bit is set and remain in Host mode until the Session bit is cleared even if a connected device is disconnected during the session The operating speed while in this mode is determined for the sitting of the Force_HS and Force_FS bits of the Testmode register SPRUGH3 November 2008 Universal Serial Bus USB Controller 73 Submit Documentation Feedback I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com 3 6 3 6 1 3 6 2 3 6 3 3 7 3 8 3 9 74 Reset Considerations The USB controller has two reset sources hardware reset and the soft reset RESET bit in CTRLR register Software Reset Considerations When the RESET bit in CTRLR is set all the USB controller registers and DMA operations are reset The bit is cleared automatically A software reset on t
166. nd TX modes are terminated It is also the mode in which the SETUP phase of control transfer is handled as outlined in Figure 6 Figure 6 IDLE Mode Flow Chart IDLE mode set Yes Unload FIFO Command No phase H Set ServicedRxPktRdy Yes Set DataEnd Set ServiceRxPktRdy Data Yes phase IN State gt TX S State gt RX Return SPRUGH3 November 2008 Universal Serial Bus USB Controller 33 Submit Documentation Feedback I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com 3 1 1 5 2 TX Mode When the endpoint is in TX state all arriving IN tokens need to be treated as part of a data phase until the required amount of data has been sent to the host If either a SETUP or an OUT token is received while the endpoint is in the TX state this will cause a SetupEnd condition to occur as the core expects only IN tokens See Figure 7 Three events can cause TX mode to be terminated before the expected amount of data has been sent 1 The host sends an invalid token causing a SETUPEND condition bit 4 of PERI_CSRO set 2 The software sends a packet containing less than the maximum packet size for endpoint 0 3 The software sends an empty data packet Until the transaction is terminated the software simply needs to load the FIFO when it receives an interrupt that indicates a packet has been sent from the FIFO An interrupt is generated when TXPKTRDY is cleared When the software f
167. ndition is detected when the host sends an IN token after the DATAEND bit in the PERI_CSRO register has been set e The host sends more than Max Packet Size data bytes in an OUT data packet e The host sends a non zero length DATA1 packet during the STATUS phase of a read request When the controller has sent the STALL packet it sets the SENTSTALL bit bit 2 of PERI_CSRO and generates an interrupt When the software receives an endpoint 0 interrupt with the SENTSTALL bit set it should abort the current transfer clear the SENTSTALL bit and return to the IDLE state If the host prematurely ends a transfer by entering the STATUS phase before all the data for the request has been transferred or by sending a new SETUP packet before completing the current transfer then the SETUPEND bit bit 4 of PERI_CSRO will be set and an endpoint 0 interrupt generated When the software receives an endpoint 0 interrupt with the SETUPEND bit set it should abort the current transfer set the SERV_SETUPEND bit bit 7 of PERI_CSRO and return to the IDLE state If the RXPKTRDY bit bit O of PERI_CSRO is set this indicates that the host has sent another SETUP packet and the software should then process this command If the software wants to abort the current transfer because it cannot process the command or has some other internal error then it should set the SENDSTALL bit bit 5 of PERI_CSRO The controller will then send a STALL packet to the host set the SENT
168. nennen nenn nenne nennen 58 10 Receive Buffer Descriptor Word D 63 11 Receive Buffer Descriptor Word 1 RRE NEEN KENE ENER ENKER KENE ER NEEN NEEN ENKER NEE NENNEN en 63 12 Receive Buffer Descriptor Word 3 ERKENNEN NEEN ENKER ENEE ENKEN ER ANER ENKEN NEEN NEE NENNEN en 63 13 Receive Buffer Descriptor Word 3 SEENEN REENEN ENKER nn nun nun nenn nn anne ann nn ann nun 64 14 Interrupts Generated by the USB Controller usssus anannnennnannunnannnannan nun nen nannnunnannannnannannann nen 68 15 USB Interrupt Conditions ssteseuegagek ee e SC en ANE ENEE NC aan ENER EEN NENNEN a an a Een a en 68 16 Universal Sserial B s USB Registers ua ne ee eek une 75 17 Control Register CTRLR Field Descriptions cceeee cess ee eee nannannnunnnnnannnunnnnnnnnnunnnunnun nun nn nn 82 18 Status Register STATR Field Descriptions uussuusnennannannnannannnunnannannnannannannnannunnnunnann ann nenn 83 19 RNDIS Register RNDISR Field Descriptions ccc eee eee cece eee e eee cence ee eee eeeeeeeeee seat eee eeeeeeeeaeeee 83 20 Auto Request Register AUTOREQ Field Descriptions 2 0ceeeceee eee eee ee eee eens eee eeeeeeeeeeeeeeeeeeeeeee 84 21 USB Interrupt Source Register INTSRCR Field Description 85 22 USB Interrupt Source Set Register INTSETR Field Descriptions uruuusunnennennnannnnnannnnnnnnnnnn nen 86 23 USB Interrupt Source Clear Register INTCLRR Field Descriptions 0 seceeeeeee seen an
169. nly error not packet completion interrupts For DMA with an RX endpoint the DMAMODE bit in RXCSR should be cleared to 0 Test Modes The controller supports the four USB 2 0 test modes defined for High speed functions It also supports an additional FIFO access test mode that can be used to test the operation of the CPU interface the DMA controller if configured and the RAM block The test modes are entered by writing to the TestMode register offset address 0x40F At test mode is usually requested by the host sending a SET_FEATURE request to Endpoint 0 When the software receives the request it should wait until the Endpoint 0 transfer has completed when it receives the Endpoint 0 interrupt indicating the status phase has completed then write to the TestMode register Note These test modes have no purpose in normal operation Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation 3 5 1 TEST_SEO_NAK To enter the Test_SEO_NAK test mode the software should set the Test_SEO NAK bit by writing 0x01 to the TestMode register The controller will then go into a mode in which it responds to any valid IN token with a NAK 3 5 2 TEST_J To enter the Test_J test mode the software should set the Test_J bit by writing 0x02 to the TestMode register The controller will then go into a mode in which it transmi
170. nly valid when the endpoint is operating in ISO mode In Bulk mode it always returns zero 1 FIFOFULL 0 1 This bit is set when no more packets can be loaded into the Receive FIFO 0 RXPKTRDY 0 1 This bit is set when a data packet has been received You should clear this bit when the packet has been unloaded from the Receive FIFO An interrupt is generated when the bit is set SPRUGH3 November 2008 Submit Documentation Feedback Universal Serial Bus USB Controller 125 I TEXAS INSTRUMENTS Registers 4 63 Control Status Register for Host Receive Endpoint HOST_RXCSR www ti com The Control Status Register for Host Receive Endpoint HOST_RXCSR is shown in Figure 78 and described in Table 79 Figure 78 Control Status Register for Host Receive Endpoint HOST_RXCSR 15 14 13 12 11 10 9 8 Reserved DMAEN DISNYET DMAMODE DATATOGWREN DATATOG Reserved R 0 R W 0 R W 0 R W O W 0 R W 0 R 0 7 6 5 4 3 2 1 0 CLRDATATOG RXSTALL REQPKT FLUSHFIFO DATAERR_NAK ERROR FIFOFULL RXPKTRDY TIMEOUT W 0 RIW 0 RIW 0 W 0 R 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only W Write only n value after reset Table 79 Control Status Register for Host Receive Endpoint HOST_RXCSR Field Descriptions Bit Field Value Description 15 14 Reserved 0 Reserved 13 DMAEN 0 1 Set this bit to enable
171. nn an nun nun nun n nn 133 4 75 Transmit and Receive FIFO Register for Endpoint 2 FIFO2 eussussunsunnannnannunnannnannunnnunnnnnnn nun 135 4 76 Transmit and Receive FIFO Register for Endpoint 3 FIFO3 ccceeeeeee scence nun nun nun nun nn un nun nnn 136 4 77 Transmit and Receive FIFO Register for Endpoint 4 FIFO4 ueuseunsunsunnennnannunnnnnnannunnnunnnnnunn nn 136 4 78 OTG Device Control Register DENTEN 137 4 79 Transmit Endpoint FIFO Size TXFIFOSZ unse a 138 4 80 Receive Endpoint FIFO Size RXFIFOSZ EEN 138 4 81 Transmit Endpoint FIFO Address TXFIFOADDR EN 139 4 82 Receive Endpoint FIFO Address DXEIFOADDD eee e ee eee sees eens eens nun nnun nun nun nun nenn 139 4 83 Transmit Function Address TXFUNCADDR ceeeeeee eee eee eee e eee ee ee ence eee e nena ee eeeeeeeeeeneeeeeneee 140 4 84 Transmit Hub Address TXHUBADDR EN 140 RS Transmit Hub Port TXHUBPORT wcceccwnctetenctecetnandtencuencxencctapetaranbantcnapaeunsmiesteccentenetexwusene 140 4 86 Receive Function Address RXFUNCADDR ceeeeeee cece eee eee e eee ee eee e eee eeeeeee eee e nese eeeeeeneeeeeenee 141 4 87 Receive Hub Address DHAHUDADDR EEN 141 4 88 Receive Hub Port RXHUBPORT 0 0ce eee eee e eee e eee e ee eee nee e eee ea eens nannnunnannannnannunnnunnann une nenn 141 Appendix A Revision History sine 143 SPRUGH3 November 2008 Contents 5 Submit Documentation Feedback A TEXAS INSTRUMENTS www ti com List of Figures 1 Funct
172. nnnnnun nun nennen 105 List of Figures SPRUGH3 November 2008 Submit Documentation Feedback Id TEXAS INSTRUMENTS www ti com 53 Receive CPPI DMA State Word 1 RCPPIDMASTATEW1 zuzennsnnannnunnannannnnnnnnnnnnnannnunnun nun nennen 106 54 Receive CPPI DMA State Word 2 RCPPIDMASTATEW2 uuzunnennennnunnnnnannnnnnnnnnnnnunnnunnunnnnn nennen 107 55 Receive CPPI DMA State Word 3 RCPPIDMASTATEWS anuennnennannnunnannannnnnnnnnnnnnunnnannunnnnn nennen 107 56 Receive CPPI DMA State Word 4 RCPPIDMASTATEWA nuuunnsnnannnunnannannnunnnnnnnnnannnannun nun nennen 109 57 Receive CPPI DMA State Word 5 RCPPIDMASTATEWS uununnennannnunnannannnunnnnnnnnnannnnnnun nun nennen 109 58 Receive CPPI DMA State Word 6 RCPPIDMASTATEW6 nununnsnnannnunnannannnunnnnnnnnnannnnnnun nun nennen 110 59 Receive CPPI Completion Pointer RCPPICOMPPTR cceeeeeeeeee seer eee ee seen eee nun nun nnannnn nun nennen 110 60 Function Address Register FADDR an 111 61 Power Management Register POWER AN Du 62 Interrupt Register for Endpoint 0 Plus Tx Endpoints 1 to 4 INTRTX uzznurennneennnnnn nen enn nennen nennen nenn 112 63 Interrupt Register for Receive Endpoints 1 to 4 INTRRX unennsssnnnennnnnennnennnnnnnnnnnnn nenn nennen nun nennen 113 64 Interrupt Enable Register for INTRTX ONTRHITSE I nennen nen nun nun nun nun nun nun nun nun nnnn nun nun nun nenn 113 65 Interrupt Enable Register for INTRRX INTRRXE AN 114 66 Interrupt Register for Common USB Int
173. nsparent Mode Receive DMA Operation Transparent Mode DMA operation is the default DMA mode as described in previous section where an interrupt is generated whenever a DMA packet is received In the transparent mode DMA packet size cannot be greater than USB MaxPktSize for the endpoint This means for receiving say n USB packets the DMA controller should be programmed with a queue of minimum n DMA packets RBUFCNTn register also needs to be written with value n The number n should be greater than 3 as the RBUFCNTn register should have at least 3 packets for the Rx DMA to receive packets from the endpoint FIFO RNDIS mode DMA is used to receive DMA packets which are larger than USB MaxPktSize This is accomplished by breaking the larger packet into smaller packets not larger than USB MaxPktSize This implies that multiple USB packets of MaxPktSize will be received and transferred together as a single large DMA packet and the DMA interrupt is generated only at the end of the complete reception of DMA packet This mode of DMA is used for RNDIS type transfers over USB The protocol defines the end of the complete transfer by receiving a short USB packet smaller than USB MaxPktSize as mentioned in USB specification 2 0 If the DMA packet size is an exact multiple of USB MaxPktSize the DMA controller waits for a zero byte packet at the end of complete transfer to signify the completion of the transfer RNDIS Mode DMA is supported only when USB MaxPktSi
174. nt Register POWER au 113 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 INTRTX zuuzsuunnen nn nn nun nenn nen nn 112 Interrupt Register for Receive Endpoints 1 to 4 NTRRNI nun nn nnn nenn 112 Interrupt Enable Register for INTRTX INTRTXE 0ccecceeeeee seen ee eee eee eee eee nun nun nun nun nun nenn nun nenn 118 Interrupt Enable Register for INTRRX INTRRXE zususususnen ran nun nun nun ann nnnnnnn nun nn nnnnn nenn nennen 118 Interrupt Register for Common USB Interrupts INTRUSB 2 cee eee eee eee neces nenn nan nun nun nun nannnnnnn 115 Interrupt Enable Register for INTRUSB NTDRUSBE nennen nnnnnnnnannnunnnunnnn nenn namen 116 FrameNumber Register FRAME se 2 82 0 00H ES aa EEN idee Ee 1127 Index Register for Selecting the Endpoint Status and Control Registers INDEX An 117 Register to Enable the USB 2 0 Test Modes TESTMODE cceeeeeeeee test eee eeeeeeeeeeeeeeeeeeeeeeeeeee 118 Maximum Packet Size for Peripheral Host Transmit Endpoint TXMAXP zusssusennnunnennannnunnannannnenn 119 Control Status Register for Endpoint 0 in Peripheral Mode PER CSO 120 Control Status Register for Endpoint 0 in Host Mode HOST_CSRO zuzuruHsun nennen nun nennen nn nennen 121 Control Status Register for Peripheral Transmit Endpoint PERI_TXCSR cseeeeeeeeee eee eeeeeeeeeeee 122 Control Status Register for Host Transmit Endpoint HOST_TXCSR cceeceeeeeeeeee eee eeeeeeeeeeeeeeee 123 Maximum
175. ntroller 79 Submit Documentation Feedback Id TEXAS INSTRUMENTS Registers www ti com Table 16 Universal Serial Bus USB Registers continued Offset Acronym Register Description Section 49Eh RXHUBADDR Address of the hub that has to be accessed through the Section 4 87 associated Receive Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub 49Fh RXHUBPORT Port of the hub that has to be accessed through the Section 4 88 associated Receive Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub Target Endpoint 4 Control Registers Valid Only in Host Mode 4A0h TXFUNCADDR Address of the target function that has to be accessed Section 4 83 through the associated Transmit Endpoint 4A2h TXHUBADDR Address of the hub that has to be accessed through the Section 4 84 associated Transmit Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub 4A3h TXHUBPORT Port of the hub that has to be accessed through the Section 4 85 associated Transmit Endpoint This is used only when full speed or low speed device is connected via a USB2 0 high speed hub 4A4h RXFUNCADDR Address of the target function that has to be accessed Section 4 86 through the associated Receive Endpoint 4A6h RXHUBADDR Address of the hub that has to be accessed through the Section 4 87 associated Receive Endpoint This is used on
176. nun ann nun nn nnnnn nen 87 24 USB Interrupt Mask Register INTMSKR Field Descriptions 0 sseeeeeeeeeee nennen nun nun nenn nennen 88 25 USB Interrupt Mask Set Register INTMSKSETR Field Descriptions 0cceeeeee eee eee nun na nn an nun nun nen 89 26 USB Interrupt Mask Clear Register INTMSKCLRR Field Descripttons eee eeeeeeeeeeeeeeee 90 27 USB Interrupt Source Masked Register INTMASKEDR Field Descriptions seeeeeeeeeeeeeeeeeeeee 91 28 USB End of Interrupt Register EOIR Field Descriptions cceeeeeeeee eee eee eee eee eee e eee nun nun nun nun nun nen 92 29 USB Interrupt Vector Register INTVECTR Field DescriptionS eee eeeeeeeeeeeeeeeeeeeeeeeees 92 30 Transmit CPPI Control Register TCPPICR Field Descriptions 0cceeeeeeeee ence eee eeeeeeeeeeeeeeeeeeeeeee 93 31 Transmit CPPI Teardown Register TCPPITDR Field Descriptions uuussuunnennannnannnnnannnnnnnnnnnn nen 93 32 CPPI DMA End of Interrupt Register CPPIEOIR Field Descriptions seceeeeeee seen eee eeeeeeeeeeeeeneee 94 33 Transmit CPPI Masked Status Register TCPPIMSKSR Field Descriptions seeeeeeeeeeeeeeeeeeeeeeees 95 34 Transmit CPPI Raw Status Register TCPPIRAWSR Field Description 95 35 Transmit CPPI Interrupt Enable Set Register TCPPIIENSETR Field Description 96 36 Transmit CPPI Interrupt Enable Clear Register TCPPIIENCLRR Field Descriptions seeseeeeeeeeeeee 96 37 Receive CPPI Control
177. oint 0 should be returned to IDLE state to await the next control transaction Note All command transactions include a field that indicates the amount of data the host expects to receive or is going to send If the endpoint is in RX state the interrupt indicates that a data packet has been received The software must respond by unloading the received data from the FIFO The software must then determine whether it has received all of the expected data If it has the software should set the DATAEND bit and return endpoint 0 to IDLE state If more data is expected the firmware should set the SERV_RXPKTRDY bit of PERI_CSRO bit 6 to indicate that it has read the data in the FIFO and leave the endpoint in RX state SPRUGH3 November 2008 Universal Serial Bus USB Controller 31 Submit Documentation Feedback USB Controller Host and Peripheral Modes Operation 32 Service endpoint 0 Read endpoint 0 CSR JA TEXAS INSTRUMENTS www ti com Figure 5 Service Endpoint 0 Flow Chart state gt IDLE No Setup Yes Set ServicedSetupEnd state gt IDLE No No No Yes y Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation 3 1 1 5 1 IDLE Mode IDLE mode is the mode the endpoint 0 control must select at power on or reset and is the mode to which the endpoint 0 control should return when the RX a
178. oop variable int I Variable to keep track int error 0 Variable to keep track int tx_desc NUM_CHANNEL int rx_desc NUM_CHANNEL Separate data section f boundaries pragma DATA_SECTION rx_bu Uint32 rx_bufferDesc NUM_C pragma DATA_SECTION tx_bu Uint32 tx_bufferDesc NUM_C Initialize CPPI DMA T usbRegs gt RCPPICR 0 usbRegs gt TCPPICR 0 for I 0 i lt NUM_CHANNEL i usbRegs gt CHANNEL i TC usbRegs gt CHANNEL i TC usbRegs gt CHANNEL i TC usbRegs gt CHANNEL i TC usbRegs gt CHANNEL i TC usbRegs gt CHANNEL i TC usbRegs gt CHAN usbRegs gt C usbRegs gt C usbRegs gt C usbRegs gt C sbRegs gt NEL i RCPPI HANNEL i RC HANNEL i RC HANNEL i RC HANNEL i RC HANNEL i R o allocate Memory region to place DMA buffers and descriptors REMIF_O_BUF nt32 1 lt lt 31 nt32 1 lt lt 30 32 1 lt lt 29 nt32 1 lt lt 28 32 1 lt lt 23 2 1 lt lt 13 on of errors of the number of descriptors built Current TX Buffer descriptor channel number Current RX Buffer descriptor channel number or bufferDesc NOTE CPPI buffers MUST be fferDesc MEMORY_TARGET HANNEL RX_BUFFERS fferDesc MEMORY_TARGET HANNEL TX_BUFFERS Disable the RX DMA Disab the TX DMA PIDMASTATEWO 0 PIDMASTATEW1 PIDMASTATEW2 PIDMASTATEW3 PIDMASTATEW4 PIDMASTATEW5 r H Weis y g y CO O
179. orces the termination of a transfer by sending a short or empty data packet it should set the DATAEND bit of PERI_CSRO bit 3 to indicate to the core that the data phase is complete and that the core should next receive an acknowledge packet Figure 7 TX Mode Flow Chart TX mode Write lt MaxP bytes to FIFO Last packet Set TxPktRdy Set TxPktRdy and set DataEnd state gt IDLE Return 34 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation 3 1 1 5 3 RX Mode In RX mode all arriving data should be treated as part of a data phase until the expected amount of data has been received If either a SETUP or an IN token is received while the endpoint is in RX state a SetupEnd condition will occur as the controller expects only OUT tokens Three events can cause RX mode to be terminated before the expected amount of data has been received as shown in Figure 8 1 The host sends an invalid token causing a SETUPEND condition setting bit 4 of PERI_CSRO 2 The host sends a packet which contains less than the maximum packet size for endpoint 0 3 The host sends an empty data packet Until the transaction is terminated the software unloads the FIFO when it receives an interrupt that indicates new data has arrived setting RXPKTRDY bit of PERI_CSRO and to clear RXPKTRDY by
180. peration The operation starts when the software writes to the FIFO and sets TXPKTRDY bit of HOST_TXCSR bit 0 This triggers the controller to send an OUT token followed by the first data packet from the FIFO An interrupt is generated whenever a packet is sent and the software may use this interrupt to load the next packet into the FIFO and set the TXPKTRDY bit in the HOST_TXCSR register bit 0 in the same way as for a Bulk Tx endpoint As the interrupt could occur almost any time within a frame depending on when the host has scheduled the transaction this may result in irregular timing of FIFO load requests If the data source for the endpoint is coming from some external hardware it may be more convenient to wait until the end of each frame before loading the FIFO as this will minimize the requirement for additional buffering This can be done by using the SOF_PULSE signal from the controller to trigger the loading of the next data packet The SOF_PULSE is generated once per frame microframe The interrupts may still be used to set the TXPKTRDY bit in HOST_TXCSR 3 3 DMA Operation The DMA controller sub module is a common 4 dual channel DMA controller It supports 4 TX and 4 RX channels and each channel attaches to the associated endpoint in the controller Channel 0 maps to Endpoint 1 up to Channel 3 mapping to Endpoint 4 while endpoint 0 cannot utilize the DMA The DMA is programmed through parameters stored in the DMA registers and impl
181. point configuration Uint8 type 0 Variable to keep track of errors int error 0 The following code should be run after resetting the attached device Initialize the endpoint FIFO RX and TX will be allocated the same sizes usbRegs gt INDEX CHAN_NUM 1 usbRegs gt RXFIFOSZ fifosize double_buffer amp 1 lt lt 4 usbRegs gt RXFIFOADDR fifo start address 18 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Introduction Example 3 Programming the USB Endpoints in Host Mode continued usbRegs gt TXFIFOSZ fifosize double_buffer amp 1 lt lt 4 usbRegs gt TXFIFOADDR fifo_start_address 1 lt lt fifosizetdouble_buffer usbRegs gt RXMAXP FIFO_MAXP usbRegs gt TXMAXP FIFO_MAXP Configure the endpoint switch device_speed case LOW_SPEED type 3 lt lt 6 device_protocol amp 3 lt lt 4 device_ep amp Oxf break case FULL_SPEED type 2 lt lt 6 device_protocol amp 3 lt lt 4 device_ep amp Oxf break case HIGH_SPEED type 1 lt lt 6 device_protocol amp 3 lt lt 4 device_ep amp Oxf break default errortt usbRegs gt EPCSR CHAN_NUM 1 HOST_TYPEO type TXTYPE usbRegs gt EPCSR CHAN_NUM 1 HOST_RXTYPE type Set NAK limit Polling interval Interrupt amp Iso protocols if device_protocol INT device_protocol ISO us
182. pport 0 High bandwidth Rx ISO endpoint support is not selected 1 High bandwidth Rx ISO endpoint support is selected 3 HBTXE Indicates high bandwidth Tx ISO endpoint support 0 High bandwidth Tx ISO endpoint support is not selected 1 High bandwidth Tx ISO endpoint support is selected 2 DYNFIFO Indicates dynamic FIFO sizing 0 Dynamic FIFO sizing option is not selected 1 Dynamic FIFO sizing option is selected 1 SOFTCONE Indicates soft connect disconnect 0 Soft connect disconnect option is not selected 1 Soft connect disconnect option is selected 0 UTMIDATAWIDTH Indicates selected UTMI data width 0 8 bits 1 16 bits 132 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers SPRUGH3 November 2008 Universal Serial Bus USB Controller 133 Submit Documentation Feedback I TEXAS INSTRUMENTS Registers www ti com 4 73 Transmit and Receive FIFO Register for Endpoint 0 FIFOO The Transmit and Receive FIFO Register for Endpoint 0 FIFOO is shown in Figure 88 and described in Table 89 Figure 88 Transmit and Receive FIFO Register for Endpoint 0 FIFOO DATA R W 0 LEGEND R W Read Write n value after reset Table 89 Transmit and Receive FIFO Register for Endpoint 0 FIFOO Field Descriptions Bit Field Value Description 31 0 DATA 0 FFFF FFFFh Writing to these a
183. ption 31 24 DESC_MSG DEER Descriptor Message Byte which is passed from the SOP Tx Descriptor to the SOP Receive descriptor Used to tag packets 23 18 Reserved 0 Reserved 17 CURR_BUFFER_EOP 0 1 Current Buffer is EOP Flag indicating whether or not the current buffer that is being transmitted from is the end of packet buffer 16 CURR_BUFFER_SOP 0 1 Current Buffer is SOP Flag indicating whether or not the current buffer that is being transmitted from is the start of packet buffer SPRUGH3 November 2008 Universal Serial Bus USB Controller 103 Submit Documentation Feedback I TEXAS INSTRUMENTS Registers www ti com Table 50 Transmit CPPI DMA State Word 4 TCPPIDMASTATEW4 Field Descriptions continued Bit Field Value Description 15 0 CURR_BUFFER_LENGTH 0 FFFFh Current Buffer Length Indicates how many valid bytes remain in the current buffer that is being transmitted from 4 35 Transmit CPPI DMA State Word 5 TCPPIDMASTATEW5 The Transmit CPPI DMA State Word 5 TCPPIDMASTATEWS is shown in Figure 50 and described in Table 51 Figure 50 Transmit CPPI DMA State Word 5 TCPPIDMASTATEW5 31 16 REM_LENGTH R W 0 15 Q LENGTH R W 0 LEGEND R W Read Write n value after reset Table 51 Transmit CPPI DMA State Word 5 TCPPIDMASTATEWS5 Field Descriptions Bit Field Value Description 31 16 REM_LENGTH 0 FFFFh Remaining Packet Length In
184. ptor are described below Table 6 Transmit Buffer Descriptor Word 0 Bits Name Description 31 0 Next Descriptor The 32 bit word aligned memory address of the next buffer descriptor in the Tx queue This is the Pointer mechanism used to reference the next buffer descriptor from the current buffer descriptor If the value of this pointer is zero then the current buffer is the last buffer in the queue The software sets the Next Descriptor Pointer Table 7 Transmit Buffer Descriptor Word 1 Bits Name Description 31 0 Buffer Pointer The Buffer Pointer is the byte aligned memory address of the buffer associated with the buffer descriptor The software sets the Buffer Pointer Table 8 Transmit Buffer Descriptor Word 2 Bits Name Description 31 16 Buffer Offset The Buffer Offset indicates how many unused bytes are at the start of the buffer SOP buffers only A value of zero indicates that there are no unused bytes at the start of the buffer and that valid data begins on the first byte of the buffer A value of OOOFh decimal 15 indicates that the first 15 bytes of the buffer are to be ignored by the DMA controller while transmitting and that valid buffer data starts on byte 16 of the buffer The Buffer Offset is valid only on Start Of Packet buffer descriptors and must be zero otherwise The software sets the Buffer Offset The Buffer Offset must be less than the Buffer Length 15 0 Buffer Length The Buffe
185. quent token packets When used in Host mode DevCtl D2 1 this register should be set to the value sent in a SET_ADDRESS command during device enumeration as the address for the peripheral device 4 46 Power Management Register POWER The Power Management Register POWER is shown in Figure 61 and described in Table 62 Figure 61 Power Management Register POWER 7 6 5 4 3 2 1 0 ISOUPDATE SOFTCONN HSEN HSMODE RESET RESUME SUSPENDM ENSUSPM R W 0 R W 0 R W 1 HO R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 62 Power Management Register POWER Field Descriptions Bit Field Value Description 7 ISOUPDATE 0 1 When set the USB controller will wait for an SOF token from the time TxPktRdy is set before sending the packet If an IN token is received before an SOF token then a zero length data packet will be sent Note This is only valid in Peripheral Mode This bit only affects endpoints performing Isochronous transfers 6 SOFTCONN 0 1 If Soft Connect Disconnect feature is enabled then the USB D D lines are enabled when this bit is set and tri stated when this bit is cleared Note This is only valid in Peripheral Mode 5 HSEN 0 1 When set the USB controller will negotiate for high speed mode when the device is reset by the hub If not set the device will only operate in full speed mode 4 HSMODE 0 1 This bit is set when th
186. quest has been transferred i e after the software has set DataEnd If however the host sends a zero length OUT data packet before the entire length of device request has been transferred this signals the premature end of the transfer In this case the controller will automatically flush any IN token loaded by software ready for the Data phase from the FIFO and set SETUPEND bit bit 4 of PERI_CSRO 36 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation 3 1 2 Bulk Transactions 3 1 2 1 Peripheral Mode Bulk In Transactions A Bulk IN transaction is used to transfer non periodic data from the USB peripheral device to the host The following optional features are available for use with a Tx endpoint used in peripheral mode for Bulk IN transactions e Double packet buffering When enabled up to two packets can be stored in the FIFO awaiting transmission to the host Double packet buffering is enabled by setting the DPB bit of TXFIFOSZ register bit 4 e DMA If DMA is enabled for the endpoint a DMA request will be generated whenever the endpoint is able to accept another packet in its FIFO This feature allows the DMA controller to load packets into the FIFO without processor intervention When DMA is enabled and DMAMODE bit of PERI_TXCSR is set an endpoint interrupt is not generated for completion of the packet
187. quires a minimum of 3 RX buffers to operate 4 30 Transmit CPPI DMA State Word 0 TCPPIDMASTATEWO The Transmit CPPI DMA State Word 0 TCPPIDMASTATEWO is shown in Figure 45 and described in Table 46 Figure 45 Transmit CPPI DMA State Word 0 TCPPIDMASTATEWO 31 16 TXQ_HEAD_PTR R W 0 15 2 1 0 TXQ_HEAD_PTR Reserved IN_PACKET R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 46 Transmit CPPI DMA State Word 0 TCPPIDMASTATEWO Field Descriptions Bit Field Value Description 31 2 TXQ_HEAD_PTR 0 3FFF FFFFh TX Queue Head Pointer 30 bit pointer to 32 bit aligned descriptor at the head of the high priority TX queue 1 Reserved 0 Reserved 0 IN_PACKET Flag indicating the DMA is in the middle of processing a packet 0 Not currently in packet Currently in packet SPRUGH3 November 2008 Universal Serial Bus USB Controller 101 Submit Documentation Feedback I TEXAS INSTRUMENTS Registers www ti com 4 31 Transmit CPPI DMA State Word 1 TCPPIDMASTATEW1 The Transmit CPPI DMA State Word 1 TCPPIDMASTATEW1 is shown in Figure 46 and described in Table 47 Figure 46 Transmit CPPI DMA State Word 1 TCPPIDMASTATEW1 31 16 SOP_DESCRIPTOR_PTR R W 0 15 2 1 0 SOP_DESCRIPTOR_PTR Reserved IN_PACKET R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 47
188. r Length field indicates how many valid data bytes are in the buffer Unused or protocol specific bytes at the beginning of the buffer are not counted in the Buffer Length field The software sets the Buffer Length Table 9 Transmit Buffer Descriptor Word 3 Bits Name Value Description 31 SOP Start of Packet SOP Indicates that the descriptor buffer is the first buffer in the packet The software sets the SOP bit 0 Not start of packet buffer Start of packet buffer 30 EOP End of Packet EOP Indicates that the descriptor buffer is the last buffer in the packet The software sets the EOP bit It is valid to set both SOP and EOP in the same descriptor 0 Not end of packet buffer End of packet buffer 29 Ownership The Ownership bit indicates ownership of the DMA packet and is valid only on SOP This bit is set by the software and cleared by the DMA controller when the packet has been transmitted The software can use this bit to reclaim buffers 0 The packet is owned by the host processor The packet is owned by the DMA controller Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation Table 9 Transmit Buffer Descriptor Word 3 continued Bits Name Value Description 28 EOQ End of Queue The End of Queue bit is set by the DMA controller to indicate that all packets in the queue have been transmitted and the Tx queue
189. r contains Start of Packet field and End of Packet field 1 buffer in DMA packet 2 Buffer Descriptor contains Start of Packet field only 2 buffers in DMA packet 3 Buffer Descriptor contains End of Packet field only 2 buffers in DMA packet 4 Buffer Descriptor does not contain either of Start of Packet field and End of Packet field 3 buffers in packet 3 3 2 3 Receive DMA State 64 The DMA controller stores and maintains state information for each receive channel The state information is referred to as the Rx DMA State The Rx DMA State is a combination of control fields and DMA controller specific scratchpad space used to manipulate data structures and receive DMA packets The Rx DMA State is stored in registers RCPPIDMASTATEWO RCPPIDMASTATEW1 RCPPIDMASTATEW2 RCPPIDMASTATEW3 RCPPIDMASTATEW4 RCPPIDMASTATEW5 RCPPIDMASTATEW6 and RCPPICOMPPTR for each channel Each channel has one receive queue that has a head descriptor pointer and one completion pointer The following information is stored in the Tx DMA State e RCPPIDMASTATEWO Rx Queue Head Descriptor Pointer e RCPPICOMPPTR Rx Completion Pointer e RCPPIDMASTATEW2 Start of Packet Buffer Descriptor Pointer e RCPPIDMASTATEWS Current Buffer Descriptor Pointer e RCPPIDMASTATEW4 Current Buffer Pointer e RCPPIDMASTATEWS Remaining DMA Packet Length and Actual DMA Packet Length Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1
190. r descriptors that constitute one or more packets queued for transmission Packets are added to the tail of the list by the software and packets are freed from the head of the list by the DMA controller as each packet transmission is completed Figure 14 Tx Queue Flow Chart SOP descriptor EOP descriptor Tx queue head descriptor pointer 3 3 1 5 Operation 60 e After reset the software must write zeroes to all Tx DMA State registers TCPPIDMASTATEWO TCPPIDMASTATEW1 TCPPIDMASTATEW2 TCPPIDMASTATEW3 TCPPIDMASTATEW4 TCPPIDMASTATEW5 e The software constructs transmit queues in memory one or more DMA packets for transmission e Enable DMA for the endpoint in the PERI_TXCSR or HOST_TXCSR by setting the DMAEN bit e Enable the DMA ports by setting TCPPI_ENABLE bit of TCPPICR register e Write the head of the queue descriptor pointer to the TCPPIDMASTATEWO register to start the DMA e The USB controller will start transmitting data Interrupt associated with the DMA channel is asserted after each DMA packet is transmitted For each buffer added to a transmit queue the software must initialize the Tx buffer descriptor values as follows e Write the Next Descriptor Pointer with the 32 bit aligned address of the next descriptor in the queue zero if last descriptor e Write the Buffer Pointer with the byte aligned address of the buffer data e Write the Buffer Length with the number of bytes in the buffer e Write th
191. r into Host mode when SESSION bit is set regardless of whether it is connected to any peripheral The controller remains in Host mode until the Session bit is cleared even if a device is disconnected And if the FORCE_HOST but remains set it will re enter Host mode next time the SESSION bit is set The operating speed is determined using the FORCE_HS and FORCE_FS bits Set this bit to transfer the packet in EPO Tx FIFO to EPO Receive FIFO It is cleared automatically 6 FIFO_ACCESS 0 1 FORCE_FS 0 1 FORCE_HS 0 1 TEST_PACKET 0 1 Set this bit to force the USB controller into full speed mode when it receives a USB reset Set this bit to force the USB controller into high speed mode when it receives a USB reset Set this bit to enter the Test_Packet test mode In this mode the USB controller repetitively transmits a 53 byte test packet on the bus the form of which is defined in the Universal Serial Bus Specification Revision 2 0 Note The test packet has a fixed format and must be loaded into the Endpoint 0 FIFO before the test mode is entered Set this bit to enter the Test_K test mode In this mode the USB controller transmits a continuous K on the bus Set this bit to enter the Test_J test mode In this mode the USB controller transmits a continuous J on the bus Set this bit to enter the Test_SEO_NAK test mode In this mode the USB controller remains in high speed mode but responds to any valid IN token with a NA
192. rating speed transaction protocol and peripheral Section 4 70 endpoint number for the host Receive endpoint Index register set to select Endpoints 1 4 41Dh HOST_RXINTERVAL Sets the polling interval for Interrupt ISOC transactions or the Section 4 71 NAK response timeout on Bulk transactions for host Receive endpoint Index register set to select Endpoints 1 4 41Fh CONFIGDATA Returns details of core configuration Index register set to Section 4 72 select Endpoint 0 FIFOn 420h FIFOO Transmit and Receive FIFO Register for Endpoint 0 Section 4 73 424h FIFO1 Transmit and Receive FIFO Register for Endpoint 1 Section 4 74 428h FIFO2 Transmit and Receive FIFO Register for Endpoint 2 Section 4 75 42Ch FIFO3 Transmit and Receive FIFO Register for Endpoint 3 Section 4 76 430h FIFO4 Transmit and Receive FIFO Register for Endpoint 4 Section 4 77 OTG Device Control 460h DEVCTL OTG Device Control Register Section 4 78 Dynamic FIFO Control 462h TXFIFOSZ Transmit Endpoint FIFO Size Section 4 79 Index register set to select Endpoints 1 4 463h RXFIFOSZ Receive Endpoint FIFO Size Section 4 80 Index register set to select Endpoints 1 4 464h TXFIFOADDR Transmit Endpoint FIFO Address Section 4 81 Index register set to select Endpoints 1 4 466h RXFIFOADDR Receive Endpoint FIFO Address Section 4 82 Index register set to select Endpoints 1 4 Target Endpoint 0 Control Registers Valid Only in Host Mode 480h TXFUNCADDR Address
193. ring a session Only valid when the USB controller is A device All active interrupts will be cleared when this register is read 6 SESSREQ 0 1 Set when session request signaling has been detected Only valid when USB controller is A device 5 DISCON 0 1 host mode when a device disconnect is detected Set in peripheral mode when a session ends CONN 0 1 Set when a device connection is detected Only valid in host mode 3 SOF 0 1 Set when a new frame starts RESET_BABBLE 0 1 Set in peripheral mode when reset signaling is detected on the bus set in host mode when babble is detected 1 RESUME 0 1 Set when resume signaling is detected on the bus while the USB controller is in suspend mode 0 SUSPEND 0 1 Set when suspend signaling is detected on the bus only valid in peripheral mode SPRUGH3 November 2008 Universal Serial Bus USB Controller 115 Submit Documentation Feedback 1 TEXAS INSTRUMENTS Registers www ti com 4 52 Interrupt Enable Register for INTRUSB INTRUSBE The Interrupt Enable Register for INTRUSB INTRUSBE is shown in Figure 67 and described in Table 68 Note Unless the UINT bit of CTRLR is set do not read or write this register directly Use the INTMSKSETR INTMSKCLRR registers instead Figure 67 Interrupt Enable Register for INTRUSB INTRUSBE 7 6 5 4 3 2 1 0 VBUSERR SESSREQ DISCON CONN SOF RESET_BABBLE RESUME SUSPEND R W 0 R W 0 R W 0 R W 0 R W 0 R W 1 R W 1 R W 0 LEGEND R
194. rite R Read only n value after reset Table 66 Interrupt Enable Register for INTRRX INTRRXE Field Descriptions Bit Field Value Description 15 5 Reserved 0 Reserved 4 EP4RX 0 1 1 0 Receive Endpoint 4 interrupt enable disable 3 EP3RX 0 1 1 0 Receive Endpoint 3 interrupt enable disable 2 EP2RX 0 1 1 0 Receive Endpoint 2 interrupt enable disable 1 EP1RX 0 1 1 0 Receive Endpoint 1 interrupt enable disable 0 Reserved 0 Reserved 114 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 51 Interrupt Register for Common USB Interrupts INTRUSB The Interrupt Register for Common USB Interrupts INTRUSB is shown in Figure 66 and described in Table 67 Reading this register causes all bits to be cleared Note Unless the UINT bit of CTRLR is set do not read or write this register directly Use the INTSRCR register instead Figure 66 Interrupt Register for Common USB Interrupts INTRUSB 7 6 5 4 3 2 1 0 VBUSERR SESSREQ DISCON CONN SOF RESET_BABBLE RESUME SUSPEND HO R 0 R 0 HO HO R 0 HO R 0 LEGEND R Read only n value after reset Table 67 Interrupt Register for Common USB Interrupts INTRUSB Field Descriptions Bit Field Value Description 7 VBUSERR 0 1 Set when VBus drops below the VBus valid threshold du
195. rred 102 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers Table 48 Transmit CPPI DMA State Word 2 TCPPIDMASTATEW2 Field Descriptions continued Bit Field Value Description 0 Reserved 0 Reserved 4 33 Transmit CPPI DMA State Word 3 TCPPIDMASTATEWS3 The Transmit CPPI DMA State Word 3 TCPPIDMASTATEWS is shown in Figure 48 and described in Table 49 Figure 48 Transmit CPPI DMA State Word 3 TCPPIDMASTATEW3 31 CURR_BUFFER_PTR R W 0 LEGEND R W Read Write n value after reset Table 49 Transmit CPPI DMA State Word 3 TCPPIDMASTATEWS3 Field Descriptions Bit Field Value Description 31 0 CURR_BUFFER_PTR 0 FFFF FFFFh Current Buffer Pointer 32 bit absolute byte address in buffer from which data is currently being transmitted 4 34 Transmit CPPI DMA State Word 4 TCPPIDMASTATEW4 The Transmit CPPI DMA State Word 4 TCPPIDMASTATEW4 is shown in Figure 49 and described in Table 50 Figure 49 Transmit CPPI DMA State Word 4 TCPPIDMASTATEW4 31 24 23 18 17 16 DESC_MSG Reserved CURR_BUFFER_EOP CURR_BUFFER_SOP R W 0 R 0 R W 0 R W 0 15 CURR_BUFFER_LENGTH R W 0 LEGEND R W Read Write R Read only n value after reset Table 50 Transmit CPPI DMA State Word 4 TCPPIDMASTATEW4 Field Descriptions Bit Field Value Descri
196. rrupt active 0 Reserved 0 Reserved 4 49 Interrupt Enable Register for INTRTX INTRTXE The Interrupt Enable Register for INTRTX INTRTXE is shown in Figure 64 and described in Table 65 Figure 64 Interrupt Enable Register for INTRTX INTRTXE 15 S Reserved HO 7 5 4 3 2 1 0 Reserved EP4TX EP3TX EP2TX EP1TX EPO HO R W 1 R W 1 R W 1 R W 1 R W 1 LEGEND R W Read Write R Read only n value after reset Table 65 Interrupt Enable Register for INTRTX INTRTXE Field Descriptions Bit Field Value Description 15 5 Reserved 0 Reserved 4 EP4TX 0 1 1 0 Transmit Endpoint 4 interrupt enable disable 3 EP3TX 0 1 1 0 Transmit Endpoint 3 interrupt enable disable 2 EP2TX 0 1 1 0 Transmit Endpoint 2 interrupt enable disable 1 EP1TX 0 1 1 0 Transmit Endpoint 1 interrupt enable disable 0 EPO 0 1 1 0 Endpoint 0 interrupt enable disable 4 50 Interrupt Enable Register for INTRRX INTRRXE The Interrupt Enable Register for INTRRX INTRRXE is shown in Figure 65 and described in Table 66 SPRUGH3 November 2008 Universal Serial Bus USB Controller 113 Submit Documentation Feedback JA TEXAS INSTRUMENTS Registers www ti com Figure 65 Interrupt Enable Register for INTRRX INTRRXE 15 8 Reserved HO 7 5 4 3 2 1 0 Reserved EP4RX EP3RX EP2RX EP1RX Reserved HO R W 1 R W 1 R W 1 R W 1 R 0 LEGEND R W Read W
197. rt RXHUBPORT is shown in Figure 103 and described in Table 104 Figure 103 Receive Hub Port RXHUBPORT 7 6 0 Reserved HUBPORT HO R W 0 LEGEND R W Read Write R Read only n value after reset Table 104 Receive Hub Port RXHUBPORT Field Descriptions Bit Field Value Description 7 Reserved 0 Reserved 6 0 HUBPORT 0 7Fh Port number of hub SPRUGH3 November 2008 Universal Serial Bus USB Controller 141 Submit Documentation Feedback I TEXAS INSTRUMENTS Registers www ti com 142 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback id TEXAS INSTRUMENTS www ti com Appendix A Appendix A Revision History Table A 1 lists the changes made since the previous version of this document Table A 1 Document Revision History Reference Additions Modifications Deletions Section 1 Added note Section 1 3 Added section Section 2 4 Changed section Section 3 1 1 Renamed section Section 3 1 2 1 Section 3 1 2 2 Section 3 2 1 Section 3 2 2 1 Section 3 2 3 Section 3 2 4 1 Section 3 2 4 2 Section 3 3 1 2 Section 3 3 1 3 Section 3 3 1 4 Section 3 3 1 4 Figure 14 Section 3 3 1 5 Section 3 3 1 5 Section 3 3 1 6 Section 3 3 2 7 Section 3 3 2 2 Section 3 3 2 4 Section 3 3 2 4 Figure 15 Section 3 3 2 5 Section 3 3 2 7 Section 3 3 2 8 Section 3 5 Section 4 Table 65 Table 66 Renamed section Renamed section Renam
198. s int device_address 0 The following code should be run after receiving a USB reset from the host Initialize the endpoint FIFO RX and TX will be allocated the same sizes usbRegs gt INDEX CHAN_NUM 1 usbRegs gt RXFIFOSZ fifosize double_buffer amp 1 lt lt 4 usbRegs gt RXFIFOADDR fifo_start_address usbRegs gt TXFIFOSZ fifosize double_buffer amp 1 lt lt 4 usbRegs gt TXFIFOADDR fifo_start_address 1 lt lt fifosizetdouble_buffer usbRegs gt RXMAXP FIFO_MAXP usbRegs gt TXMAXP FIFO_MAXP Force Data Toggle is optional for interrupt traffic Uncomment if needed CSL_FINS usbRegs gt PERI_TXCSR USB_PERI_TXCSR_FRCDATATOG 1 Uncomment below to configure the endpoint for ISO and not respond with a handshake packet CSL_FINS usbRegs gt PERI_RXCSR USB_PERI_RXCSR_ISO 1 CSL_FINS usbRegs gt PERI_TXCSR USB_PERI_TXCSR_ISO 1 After receiving a successful set address command set the following register to the specified address immediately following the status stage usbRegs gt FADDR device_address SPRUGH3 November 2008 Universal Serial Bus USB Controller 17 Submit Documentation Feedback JA TEXAS INSTRUMENTS Introduction www ti com User Case 3 An example of how to program the USB endpoints in host mode Example 3 Programming the USB Endpoints in Host Mode DMA channel number Valid values are 0 1 2 or 3 int CHAN_NUM 0 Fifo si
199. s 126 80 Count 0 Register COUNTO Field Descriptions 0c cccece cece eee ee eee eee nun nun nnnnun nun nun ann nun nun nun nen 128 81 Receive Count Register RXCOUNT Field Descriptions cceceee eee e eee eee eee e neces nun nnnnnun nun nnnnnn 128 82 Type Register Host mode only HOST_TYPEO Field Descriptions r4r 4u4HHHn nn nn nennen ann nn nn nn 129 83 Transmit Type Register Host mode only HOST_TXTYPE Field Descriptions seeeeeeeeeeeeeeeeeees 129 84 NAKLimitO Register Host mode only HOST_NAKLIMITO Field Descriptions 0ceeeeeeeeeeeeeeeeeeee 130 85 Transmit Interval Register Host mode only HOST_TXINTERVAL Field Descriptions esseeeeeeeees 130 86 Receive Type Register Host mode only HOST_RXTYPE Field Descriptons nennen nn 131 87 Receive Interval Register Host mode only HOST_RXINTERVAL Field Descrptions nn 00 132 88 Configuration Data Register CONFIGDATA Field Descriptions 2ceeeeeeeeee eee ee nun nn nn nen nenne 132 89 Transmit and Receive FIFO Register for Endpoint 0 FIFOO Field Descriptions 0cseeeeeeeeeeeeeeees 134 90 Transmit and Receive FIFO Register for Endpoint 1 FIFO1 Field Descriptions 0cseeeeeeeeeeeeeeees 135 91 Transmit and Receive FIFO Register for Endpoint 2 FIFO2 Field Descriptions 0csseeeeeeeeeeeeeees 135 92 Transmit and Receive FIFO Register for Endpoint 3 FIFO3 Field Descriptions 0cseeeeeeeeeeeeee
200. s 31 2 of this location If the two match the interrupt bit corresponding to this Tx Queue should be deasserted 1 Writeback Mode Indicates that the value that is presented on bits 31 2 of the write data should be written to this location and the interrupt for this Tx Queue should be asserted This bit is read as zero 4 37 Receive CPPI DMA State Word 0 RCPPIDMASTATEWO The Receive CPPI DMA State Word 0 RCPPIDMASTATEWO is shown in Figure 52 and described in Table 53 Figure 52 Receive CPPI DMA State Word 0 RCPPIDMASTATEWO 31 16 Reserved R 0 15 8 7 0 Reserved SOP_BUFFER_OFFSET R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 53 Receive CPPI DMA State Word 0 RCPPIDMASTATEWO Field Descriptions Bit Field Value Description 31 8 Reserved 0 7FFF FFh_ Reserved 7 0 SOP_BUFFER_OFFSET 0 FFh Start of Packet Buffer Offset Controls how many bytes the Receive DMA will skip at the beginning of the start of packet buffer before beginning to fill the buffer with receive data This field is programmed by the Host software when the channel is set up to facilitate addition of various protocol encapsulation headers for retransmission of received packets 4 38 Receive CPPI DMA State Word 1 RCPPIDMASTATEW1 The Receive CPPI DMA State Word 1 RCPPIDMASTATEWI is shown in Figure 53 and described in Table 54 SPRUGH3 November 2008 Un
201. software can then choose when to set the PHY into its normal mode Systems with a lengthy initialization procedure may use this to ensure that initialization is complete and the system is ready to perform enumeration before connecting to the USB Once the SOFTCONN bit has been set the software can also simulate a disconnect by clearing this bit to 0 e Entry into suspend mode When operating as a peripheral device the controller monitors activity on the bus and when no activity has occurred for 3 ms it goes into Suspend mode If the Suspend interrupt has been enabled an interrupt will be generated at this time At this point the controller can then be left active and hence able to detect when Resume signaling occurs on the USB or the application may arrange to disable the controller by stopping its clock However the controller will not then be able to detect Resume signaling on the USB As a result some external hardware will be needed to detect Resume signaling by monitoring the DM and DP signals so that the clock to the controller can be restarted e Resume Signaling When resume signaling occurs on the bus first the clock to the controller must be restarted if necessary Then the controller will automatically exit Suspend mode If the Resume interrupt is enabled an interrupt will be generated e Initiating a remote wakeup f the software wants to initiate a remote wakeup while the controller is in Suspend mode it should write to
202. ss practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are spec
203. ster for the selected controller endpoint RXFUNCADDR register is available for all endpoints from EPO to EP4 The HOST_RXTYPE register for the endpoint that is to be used needs to be programmed as follows Operating speed in the SPEED bit field bits 7 and 6 Set 01 binary value in the PROT field for isochronous transfer Endpoint Number of the target device in RENDPN field This is the endpoint number contained in the Rx endpoint descriptor returned by the target device during enumeration The RXMAXP register for the controller endpoint must be written with the maximum packet size in bytes for the transfer This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the target endpoint The HOST_RXINTERVAL register needs to be written with the required transaction interval usually one transaction per frame microframe The relevant interrupt enable bit in the INTRRXE register should be set if an interrupt is required for this endpoint The following bits of HOST_RXCSR register should be set as shown below Set the DMAEN bit bit 13 to 1 if a DMA request is required for this endpoint Clear the DISNYET it bit 12 to 0 to allow normal PING flow control This will only affect High Speed transactions Always clear the DMAMODE bit bit 11 to 0 If DMA is enabled AUTOREQ register can be set for generating IN tokens automatically after receiving the data Set the bit f
204. ster should match the wMaxPacketSize field of the Standard Endpoint Descriptor for the associated endpoint A mismatch could cause unexpected results 124 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com 4 62 Control Status Register for Peripheral Receive Endpoint PERI_RXCSR The Control Status Register for Peripheral Receive Endpoint PERI_RXCSR is shown in Figure 77 and described in Table 78 Registers Figure 77 Control Status Register for Peripheral Receive Endpoint PERI_RXCSR 15 14 13 12 11 10 8 Reserved ISO DMAEN DISNYET DMAMODE Reserved R 0 R W 0 R W 0 R W 0 R W 0 R 0 T 6 5 4 3 2 1 0 CLRDATATOG SENTSTALL SENDSTALL FLUSHFIFO DATAERROR OVERRUN FIFOFULL RXPKTRDY WO R W 0 R W 0 WO R 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only W Write only n value after reset Table 78 Control Status Register for Peripheral Receive Endpoint PERI_RXCSR Field Descriptions Bit Field Value Description 15 Reserved 0 Reserved 14 ISO 0 1 Set this bit to enable the Receive endpoint for Isochronous transfers and clear this bit to enable the Receive endpoint for Bulk Interrupt transfers 13 DMAEN 0 1 Set this bit to enable the DMA request for the Receive endpoints 12 DISNYET 0 1 Set this bit to disable
205. t bit 7 has been set If RXSTALL bit is set it indicates that the target has issued a STALL response If ERROR bit is set it means that the controller has tried to send the OUT token and the following data packet three times without getting any response SPRUGH3 November 2008 Submit Documentation Feedback Universal Serial Bus USB Controller 47 USB Controller Host and Peripheral Modes Operation If NAK_TIMEOUT is set it means that the controller has received a NAK response to each attempt to send the OUT token for longer than the time set in the HOST_NAKLIMITO register The controller can then be directed either to continue trying this transaction until it times out again by clearing the NAK_TIMEOUT bit or to abort the transaction by flushing the FIFO before clearing the NAK_TIMEOUT 48 bit JA TEXAS INSTRUMENTS www ti com If none of RXSTALL ERROR or NAKLIMIT is set the OUT data has been correctly ACKed If further data needs to be sent the software should repeat Steps 1 3 When all the data has been successfully sent the software should proceed to the IN Status Phase of the Control Transaction Figure 11 OUT Data Phase Flow Chart For each OUT packet specified in SETUP phase TxPktRdy No set Yes OUT token sent DATAO 1 packet sent Stall received Yes No ACK Yes received o N Yes NAK received S N o NAK limit reached No Error count clear
206. t Register CPPIEOIR 31 Reserved HO 15 8 Reserved VECTOR R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 32 CPPI DMA End of Interrupt Register CPPIEOIR Field Descriptions Bit Field Value Description 31 8 Reserved 0 Reserved 7 0 VECTOR 0 FFh End of Interrupt Vector This is an application specific register which is essentially a general purpose output from the LCSAR One cycle after this register is written the eoi_vector 7 0 value will appear on the eoi_vector output port from the LCSAR and the eoi_write output port will be asserted for 1 clock cycle This register is used to convert level sensitive interrupts to pulsed non redundant interrupts Software should write all zeros for the vector value SPRUGH3 November 2008 94 Universal Serial Bus USB Controller Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 17 Transmit CPPI Masked Status Register TCPPIMSKSR The Transmit CPPI Masked Status Register TCPPIMSKSR is shown in Figure 32 and described in Table 33 Figure 32 Transmit CPPI Masked Status Register TCPPIMSKSR 31 16 Reserved R 0 15 4 3 0 Reserved MASKED COMP_PENDING R 0 R 0 LEGEND R Read only n value after reset Table 33 Transmit CPPI Masked Status Register TCPPIMSKSR Field Descriptions Bit Field Value Description 31 4 Res
207. t mode only HOST_NAKLIMITO is shown in Figure 83 and described in Table 84 Figure 83 NAKLimit0 Register Host mode only HOST_NAKLIMITO 7 5 4 0 Reserved EPONAKLIMIT HO R W 0 LEGEND R W Read Write R Read only n value after reset Table 84 NAKLimitO Register Host mode only HOST_NAKLIMITO Field Descriptions Bit Field Value Description 7 5 Reserved 0 Reserved 4 0 EPONAKLIMIT 0 1Fh Sets the number of frames microframes high speed transfers after which Endpoint 0 should time out on receiving a stream of NAK responses The number of frames microframes selected is 25 where m is the value set in the register valid values 2 16 If the host receives NAK responses from the target for more frames than the number represented by the Limit set in this register the endpoint will be halted Note A value of 0 or 1 disables the NAK timeout function 4 69 Transmit Interval Register Host mode only HOST_TXINTERVAL The Transmit Interval Register Host mode only HOST_TXINTERVAL is shown in Figure 84 and described in Table 85 Figure 84 Transmit Interval Register Host mode only HOST_TXINTERVAL POLINTVL_NAKLIMIT R W 0 LEGEND R W Read Write n value after reset Table 85 Transmit Interval Register Host mode only HOST_TXINTERVAL Field Descriptions Bit Field Value Description 7 0 POLINTVL_NAKLIMIT DEER For Interrupt and Isochronous transfers
208. t or the external SOF_PULSE signal from the controller to trigger the loading of the next data packet The SOF_PULSE is generated once per frame microframe when a SOF packet is received The controller also maintains an external frame microframe counter so it can still generate a SOF_PULSE when the SOF packet has been lost The interrupts may still be used to set the TXPKTRDY bit in PERI_TXCSR bit 0 and to check for data overruns underruns Starting up a double buffered Isochronous IN pipe can be a source of problems Double buffering requires that a data packet is not transmitted until the frame microframe after it is loaded There is no problem if the function loads the first data packet at least a frame microframe before the host sets up the pipe and therefore starts sending IN tokens But if the host has already started sending IN tokens by the time the first packet is loaded the packet may be transmitted in the same frame microframe as it is loaded depending on whether it is loaded before or after the IN token is received This potential problem can be avoided by setting the ISOUPDATE bit in the POWER register bit 7 When this bit is set any data packet loaded into an Isochronous Tx endpoint FIFO will not be transmitted until after the next SOF packet has been received thereby ensuring that the data packet is not sent too early 3 1 4 1 3 Error Handling If the endpoint has no data in its FIFO when an IN token is received it w
209. ta starts on byte 16 of the buffer The software sets the buffer offset to zero on buffer initialization and the DMA controller overwrites the zero value on SOP packets with the Rx DMA State buffer offset value 15 0 Buffer Length The Buffer Length field indicates how many valid data bytes are in the buffer Unused or protocol specific bytes at the beginning of the buffer are not counted in the Buffer Length field The software sets the buffer length on buffer initialization The DMA controller will overwrite the software initialized value on an EOP buffer when the number of received data bytes is less than the host initiated value The DMA controller will overwrite the host initialized value on SOP when the Buffer Offset is greater than zero or the Packet Length is less than the buffer length SPRUGH3 November 2008 Submit Documentation Feedback Universal Serial Bus USB Controller 63 JA TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com Table 13 Receive Buffer Descriptor Word 3 Bit Field Value Description 31 SOP Start of Packet SOP Indicates that the descriptor buffer is the first buffer in the packet Software should clear the SOP bit when setting up the descriptor 0 Not start of packet buffer 1 Start of packet buffer 30 EOP End of Packet EOP Indicates that the descriptor buffer is the last buffer in the packet Software should clear the EOP bit when setting up the descriptor 0
210. tate Word 5 TCPPIDMASTATEWS5 Field Descripttons nenn nn nun 104 52 Transmit CPPI Completion Pointer TCPPICOMPPTR Field DescriptionS nennen nn 105 53 Receive CPPI DMA State Word 0 RCPPIDMASTATEWO Field Descriptions eeeeeeeeeeeeeeeeeeee 105 54 Receive CPPI DMA State Word 1 RCPPIDMASTATEW1 Field Descriptions 0seeeeeeeeeeeeeeeeeee 106 55 Receive CPPI DMA State Word 2 RCPPIDMASTATEW2 Field Descriptions urusnuunnannannnnnnannenn 107 56 Receive CPPI DMA State Word 3 RCPPIDMASTATEWS Field Descriptions c eeeeeeeeeeeeeeeeeeee 107 57 Receive CPPI DMA State Word 4 RCPPIDMASTATEW4 Field Descriptions eeeeeeeeeeeeeeeeeeee 109 58 Receive CPPI DMA State Word 5 RCPPIDMASTATEWS Field Descriptions urusnuunnannannnnnnennenn 109 59 Receive CPPI DMA State Word 6 RCPPIDMASTATEW6 Field Descriptions cceeeeeeeeeeeeeeeeeeee 110 60 Receive CPPI Completion Pointer RCPPICOMPPTR Field Description 110 61 Function Address Register FADDR Field Descriptions EEN 111 62 Power Management Register POWER Field Descriptions uuuussunsennennnnnnnnnnnnnannnnnnun nun nunnenn 111 63 Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 INTRTX Field Descriptions 112 64 Interrupt Register for Receive Endpoints 1 to 4 INTRRX Field Descriptions EN 113 65 Interrupt Enable Register for INTRTX INTRTXE Field Descriptions eceeeeeeeeeeeeeeeeeeeeeeeeeeene
211. ted If the software written buffer address value matches with the buffer address written by the DMA controller the Tx Channel interrupt gets deasserted A misqueued packet condition may occur when the software adds a packet to a queue for transmission as the DMA controller finishes transmitting the previous last packet in the queue The misqueued packet is detected by the software when queue processing detects a cleared Ownership bit in the SOP buffer descriptor a set End of Queue bit in the EOP buffer descriptor and a nonzero Next Descriptor Pointer in the EOP buffer descriptor A misqueued packet means that the DMA controller read the last EOP buffer descriptor before the host added the new last packet to the queue so the DMA controller determined queue empty just before the last packet was added The host software corrects the misqueued packet condition by initiating a new packet transfer for the misqueued packet by writing the misqueued packet s SOP buffer descriptor address to the head descriptor pointer in TCCPIDMASTATEWO register 3 3 1 6 Transparent Mode and RNDIS Mode Transmit DMA Operation Transparent Mode DMA operation is the default DMA mode as described in previous section where an interrupt is generated whenever a DMA packet is transmitted In the transparent mode DMA packet size cannot be greater than USB MaxPktSize and FIFO size for the endpoint This means for transmitting say n USB packets the DMA controller should be
212. ter COUNTO 15 7 6 0 Reserved EPORXCOUNT R 0 R 0 LEGEND R Read only n value after reset Table 80 Count 0 Register COUNTO Field Descriptions Bit Field Value Description 15 7 Reserved 0 Reserved 6 0 EPORXCOUNT 0 7Fh Indicates the number of received data bytes in the Endpoint 0 FIFO The value returned changes as the contents of the FIFO change and is only valid while RXPKTRDY of PERI_CSRO or HOST_CSRO is set 4 65 Receive Count Register RXCOUNT The Receive Count Register RXCOUNT is shown in Figure 80 and described in Table 81 Figure 80 Receive Count Register RXCOUNT 15 13 12 0 Reserved EPRXCOUNT HO R 0 LEGEND R Read only n value after reset Table 81 Receive Count Register RXCOUNT Field Descriptions Bit Field Value Description 15 13 Reserved 0 Reserved 12 0 EPRXCOUNT 0 1FFFh Holds the number of received data bytes in the packet in the Receive FIFO The value returned changes as the contents of the FIFO change and is only valid while RXPKTRDY of PERI_RXCSR or HOST_RXCSR is set 128 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 66 Type Register Host mode only HOST_TYPEO The Type Register Host mode only HOST_TYPEO is shown in Figure 81 and described in Table 82 Figure 81 Type Register Host mode only HOST_TYPEO 7
213. ter INTMSKCLRR is shown in Figure 25 and described in Table 26 Figure 25 USB Interrupt Mask Clear Register INTMSKCLRR 31 25 24 16 Reserved USB HO WO 15 13 12 8 7 5 4 0 Reserved RX Reserved TX R 0 WO R 0 W 0 LEGEND R Read only W Write only n value after reset Table 26 USB Interrupt Mask Clear Register INTMSKCLRR Field Descriptions Bit Field Value Description 31 25 Reserved 0 Reserved 24 16 USB 0 1FFh Write a 1 to clear equivalent USB interrupt mask Allows the USB interrupt masks to be individually disabled 15 13 Reserved 0 Reserved 12 8 RX 0 1Fh Write a 1 to clear equivalent Receive endpoint interrupt mask Allows the USB interrupt masks to be individually disabled 7 5 Reserved 0 Reserved 4 0 TX 0 Fh Write a 1 to clear equivalent Transmit endpoint interrupt mask Allows the USB interrupt masks to be individually disabled 90 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com Registers 4 11 USB Interrupt Source Masked Register INTMASKEDR The USB Interrupt Source Masked Register INTMASKEDR is shown in Figure 26 and described in Table 27 Figure 26 USB Interrupt Source Masked Register INTMASKEDR 31 25 24 16 Reserved USB R 0 R 0 15 13 12 8 7 5 4 0 Reserved RX Reserved TX R 0 R 0 R 0 R 0 LEGEND R Read
214. ter Section 4 44 Common USB Registers 400h FADDR Function Address Register Section 4 45 401h POWER Power Management Register Section 4 46 402h INTRTX Interrupt Register for Endpoint 0 and for Transmit Section 4 47 Endpoints 1 to 4 404h INTRRX Interrupt Register for Receive Endpoints 1 to 4 Section 4 48 406h INTRTXE Interrupt enable register for INTRTX Section 4 49 408h INTRRXE Interrupt Enable Register for INTRRX Section 4 50 40Ah INTRUSB Interrupt Register for Common USB Interrupts Section 4 51 40Bh INTRUSBE Interrupt Enable Register for INTRUSB Section 4 52 40Ch FRAME Frame Number Register Section 4 53 40Eh INDEX Index Register for Selecting the Endpoint Status and Control Section 4 54 Registers 40Fh TESTMODE Register to Enable the USB 2 0 Test Modes Section 4 55 Indexed Registers These registers operate on the endpoint selected by the INDEX register 410h TXMAXP Maximum Packet Size for Peripheral Host Transmit Endpoint Section 4 56 Index register set to select Endpoints 1 4 412h PERI_CSRO Control Status Register for Endpoint 0 in Peripheral Mode Section 4 57 Index register set to select Endpoint 0 HOST_CSRO Control Status Register for Endpoint 0 in Host Mode Section 4 58 Index register set to select Endpoint 0 PERI_TXCSR Control Status Register for Peripheral Transmit Endpoint Section 4 59 Index register set to select Endpoints 1 4 HOST_TXCSR Control Status Register for Host Transmit Endpoint Section 4 60 Index register set to select En
215. the DMA request for the Receive endpoints 12 DISNYET 0 1 Set this bit to disable the sending of NYET handshakes When set all successfully received Receive packets are ACKED including at the point at which the FIFO becomes full Note This bit only has any effect in high speed mode in which mode it should be set for all Interrupt endpoints 11 DMAMODE 0 This bit should always be cleared to 0 10 DATATOGWREN 0 1 Set this bit to enable the DATATOG bit to be written This bit is automatically cleared once the new value is written to DATATOG 9 DATATOG 0 1 When read this bit indicates the current state of the Receive EP data toggle If DATATOGWREN is high this bit can be written with the required setting of the data toggle If DATATOGWREN is low any value written to this bit is ignored Reserved 0 Reserved CLRDATATOG 0 1 Set this bit to reset the endpoint data toggle to 0 RXSTALL 0 1 When a STALL handshake is received this bit is set and an interrupt is generated You should clear this bit 5 REQPKT 0 1 Set this bit to request an IN transaction It is cleared when RXPKTRDY is set 4 FLUSHFIFO 0 1 Set this bit to flush the next packet to be read from the endpoint Receive FIFO The FIFO pointer is reset and the RXPKTRDY bit is cleared Note FLUSHFIFO has no effect unless RXPKTRDY is set Also note that if the FIFO is double buffered FLUSHFIFO may need to be set twice to completely clear the FIFO 3 DATAERR_NAKTIMEOUT 0 1
216. the Power register to set the RESUME bit to 1 The software should leave then this bit set for approximately 10 ms minimum of 2 ms a maximum of 15 ms before resetting it to 0 Note No resume interrupt will be generated when the software initiates a remote wakeup e Reset Signaling When reset signaling occurs on the bus the controller will perform the following actions Sets FADDR register to 0 Sets INDEX register to 0 Flushes all endpoint FIFOs Clears all control status registers Generates a reset interrupt If the HSENA bit in the POWER register bit 5 was set the controller also tries to negotiate for high speed operation Whether high speed operation is selected is indicated by HSMODE bit of POWER register bit 4 When the application software receives a reset interrupt it should close any open pipes and wait for bus enumeration to begin Peripheral Mode Control Transactions Endpoint 0 is the main control endpoint of the core The software is required to handle all the standard device requests that may be sent or received via endpoint 0 These are described in Universal Serial Bus Specification Revision 2 0 Chapter 9 The protocol for these device requests involves different numbers and types of transactions per transfer To accommodate this the software needs to take a state machine approach to command decoding and handling The Standard Device Requests received by a USB peripheral device can be divi
217. the index to restore later if bytes lt 1 bytes 64 error t t usbRegs gt INDEX ch 1 Link previous buffer to this one if this is not the first descriptor of the channel if rx_desc ch gt 0 rx_bufferDesc ch 4 rx_desc ch 1 Uint32 amp rx_bufferDesc ch 4 rx_desc ch rx_bufferDesc ch 4 rx_desc ch 0 Uint32 0x00000000 Next descriptor rx_bufferDesc ch 4 rx_desc ch 1 Uint32 outBuf Buffer address rx_bufferDesc ch 4 rx_desc ch 2 0x0000 lt lt 16 bytes Rx buffer size in bytes rx_bufferDesc ch 4 rx_desc ch 3 OWNER 0 OWNER rx_desc ch usbRegs gt INDEX index_save Restore the index to previous value Industry Standard s Compliance Statement This device conforms to USB 2 0 Specification and On The Go Supplement to the USB 2 0 Specification Rev 1 0a Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback l TEXAS INSTRUMENTS www ti com Peripheral Architecture 2 Peripheral Architecture 2 1 Clock Control Information related to clock generation and control for the USB peripheral will be added in a future revision of this document Clocks for USB are generated based on a crystal oscillator on the M24XI and M24XO pins The oscillator is enabled by bit OSCPDWN of the USBPHY_CTL register in the system module 2 2 Signal Descriptions The USB controller provides the following I O signals Table 1
218. the last EOP buffer descriptor before the software added buffer descriptor s to the queue so the DMA controller determined queue empty just before the software added more buffer descriptor s Receive overrun condition may occur in the misqueued buffer case If a new packet reception is begun during the time that the DMA controller has determined the end of queue condition then the received packet will overrun start of packet overrun If the misqueued buffer occurs during the middle of a packet reception then middle of packet overrun may occur If the misqueued buffer occurs after the last packet has completed and is corrected before the next packet reception begins then overrun will not occur The software acts on the misqueued buffer condition by writing the added buffer descriptor address to the appropriate Rx DMA State Head Descriptor Pointer in RCPPIDMASTATEW1 register 66 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com USB Controller Host and Peripheral Modes Operation 3 3 2 6 Receive Abort Handling The DMA controller sets Rx Abort bit used to identify Rx packets which were aborted due to lack of buffers Software must take care to inspect any Rx SOP packet for this bit and ignore all the buffers in that packet as the packet is incomplete Also for aborted packets the packet length may not match the data size in the buffers 3 3 2 7 RNDIS Mode and Tra
219. the sending of NYET handshakes When set all successfully received Receive packets are ACKed including at the point at which the FIFO becomes full Note This bit only has any effect in high speed mode in which mode it should be set for all Interrupt endpoints 11 DMAMODE 0 This bit should always be cleared to 0 10 8 Reserved 0 Reserved 7 CLRDATATOG 0 1 Set this bit to reset the endpoint data toggle to 0 6 SENTSTALL 0 1 This bit is set when a STALL handshake is transmitted The FIFO is flushed and the TXPKTRDY bit is cleared You should clear this bit 5 SENDSTALL 0 1 Set this bit to issue a STALL handshake Clear this bit to terminate the stall condition Note This bit has no effect where the endpoint is being used for Isochronous transfers 4 FLUSHFIFO 0 1 Set this bit to flush the next packet to be read from the endpoint Receive FIFO The FIFO pointer is reset and the RXPKTRDY bit is cleared Note FLUSHFIFO has no effect unless RXPKTRDY is set Also note that if the FIFO is double buffered FLUSHFIFO may need to be set twice to completely clear the FIFO 3 DATAERROR 0 1 This bit is set when RXPKTRDY is set if the data packet has a CRC or bit stuff error It is cleared when RXPKTRDY is cleared Note This bit is only valid when the endpoint is operating in ISO mode In Bulk mode it always returns zero 2 OVERRUN 0 1 This bit is set if an OUT packet cannot be loaded into the Receive FIFO You should clear this bit Note This bit is o
220. ting in Bulk or Interrupt mode 1 FIFONOTEMPTY 0 1 The USB controller sets this bit when there is at least 1 packet in the Tx FIFO 0 TXPKTRDY 0 1 Set this bit after loading a data packet into the FIFO It is cleared automatically when a data packet has been transmitted An interrupt is generated if enabled when the bit is cleared SPRUGH3 November 2008 Universal Serial Bus USB Controller 123 Submit Documentation Feedback I TEXAS INSTRUMENTS Registers www ti com 4 61 Maximum Packet Size for Peripheral Host Receive Endpoint RXMAXP The Maximum Packet Size for Peripheral Host Receive Endpoint RXMAXP is shown in Figure 76 and described in Table 77 Figure 76 Maximum Packet Size for Peripheral Host Receive Endpoint RXMAXP 15 11 10 0 Reserved MAXPAYLOAD R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 77 Maximum Packet Size for Peripheral Host Receive Endpoint RXMAXP Field Descriptions Bit Field Value Description 15 11 Reserved 0 Reserved 10 0 MAXPAYLOAD DEER Defines the maximum amount of data that can be transferred through the selected Receive endpoint in a single frame microframe high speed transfers The value set can be up to 1024 bytes but is subject to the constraints placed by the USB Specification on packet sizes for Bulk Interrupt and Isochronous transfers in full speed and high speed operations The value written to this regi
221. tion 4 31 Section 4 32 Section 4 33 Section 4 34 Section 4 35 Section 4 36 Section 4 37 Section 4 38 Section 4 39 Section 4 40 Section 4 41 Section 4 42 Section 4 43 Section 4 44 1C0h 1C4h 1C8h 1CCh 1D0h 1D4h TCPPIDMASTATEWO TCPPIDMASTATEW1 TCPPIDMASTATEW2 TCPPIDMASTATEW3 TCPPIDMASTATEW4 TCPPIDMASTATEW5 Transmit Receive CPPI Channel 3 State Block Transmit CPPI DMA State Word 0 Transmit CPPI DMA State Word 1 Transmit CPPI DMA State Word 2 Transmit CPPI DMA State Word 3 Transmit CPPI DMA State Word 4 Transmit CPPI DMA State Word 5 Section 4 30 Section 4 31 Section 4 32 Section 4 33 Section 4 34 Section 4 35 76 Universal Serial Bus USB Controller SPRUGH3 November 2008 Submit Documentation Feedback JA TEXAS INSTRUMENTS www ti com Registers Table 16 Universal Serial Bus USB Registers continued Offset Acronym Register Description Section 1DCh TCPPICOMPPTR Transmit CPPI Completion Pointer Section 4 36 1E0h RCPPIDMASTATEWO Receive CPPI DMA State Word 0 Section 4 37 1E4h RCPPIDMASTATEW1 Receive CPPI DMA State Word 1 Section 4 38 1E8h RCPPIDMASTATEW2 Receive CPPI DMA State Word 2 Section 4 39 1ECh RCPPIDMASTATEW3 Receive CPPI DMA State Word 3 Section 4 40 1FOh RCPPIDMASTATEW4 Receive CPPI DMA State Word 4 Section 4 41 1F4h RCPPIDMASTATEW5 Receive CPPI DMA State Word 5 Section 4 42 1F8h RCPPIDMASTATEW6 Receive CPPI DMA State Word 6 Section 4 43 1FCh RCPPICOMPPTR Receive CPPI Completion Poin
222. transfer An endpoint interrupt is generated only in the error conditions 3 1 2 1 1 Setup In configuring a TX endpoint for bulk transactions the TXMAXP register must be written with the maximum packet size in bytes for the endpoint This value should be the same as the wMaxPacketSize field of the Standard Endpoint Descriptor for the endpoint and the PERI_TXCSR register should be set as shown in Table 2 Table 2 PERI_TXCSR Register Bit Configuration for Bulk IN Transactions Bit Position Bit Field Name Configuration Bit 14 ISO Cleared to 0 for bulk mode operation Bit 13 MODE Set to 1 to make sure the FIFO is enabled only necessary if the FIFO is shared with an RX endpoint Bit 12 DMAEN Set to 1 if DMA requests must be enabled Bit 11 FRCDATATOG Cleared to 0 to allow normal data toggle operations Bit 10 DMAMODE Set to 1 when DMA is enabled and EP interrupt is not needed for each packet transmission When the endpoint is first configured following a SET_CONFIGURATION or SET_INTERFACE command on Endpoint 0 the lower byte of PERI_TXCSR should be written to set the CLRDATATOG bit bit 6 This will ensure that the data toggle which is handled automatically by the controller starts in the correct state Also if there are any data packets in the FIFO indicated by the FIFONOTEMPTY bit bit 1 of PERI_TXCSR being set they should be flushed by setting the FLUSHFIFO bit bit 3 of PERI_TXCSR Note It may be necessary to set t
223. ts a continuous J on the bus 353 TEST_K To enter the Test_K test mode the software should set the Test_K bit by writing 0x04 to the TestMode register The controller will go into a mode in which it transmits a continuous K on the bus SPRUGH3 November 2008 Universal Serial Bus USB Controller 71 Submit Documentation Feedback JA TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com 3 5 4 3 5 5 72 TEST_PACKET To execute the Test_Packet the software should 1 Start a session if the core is being used in Host mode 2 Write the standard test packet shown below to the Endpoint 0 FIFO 3 Write 0x8 to the TestMode register to enter Test_Packet test mode 4 Set the TxPktRdy bit in the CSRO register D1 The 53 by test packet to load is as follows all bytes in hex The test packet only has to be loaded once the controller will keep re sending the test packet without any further intervention from the software 00 00 00 00 00 00 00 00 00 AA AA AA AA AA AA AA AA EE EE EE EE EE EE EE EE FE FF FF FF FF FF FF FF FF FF FF Fr 7F BF ODF EF F7 FB FD FC 7E BF ODF EF F7 FB FD E This data sequence is defined in Universal Serial Bus Specification Revision 2 0 Section 7 1 20 The controller will add the DATAAO PID to the head of the data sequence and the CRC to the end FIFO_ACCESS The FIFO Access test mode allows the user to test the operation of CPU Interface the DMA controller if configur
224. unt cleared interrupt generated Transaction deemed complete SPRUGH3 November 2008 Universal Serial Bus USB Controller 45 Submit Documentation Feedback I TEXAS INSTRUMENTS USB Controller Host and Peripheral Modes Operation www ti com 3 At the end of the attempt to send the data the controller will generate an Endpoint 0 interrupt The 3 2 1 2 For the IN Data Phase of a control transaction Figure 10 the software driving the USB host device needs to 46 1 2 3 4 5 software should then read HOST_CSRO to establish whether the RXSTALL bit bit 2 the ERROR bit bit 4 or the NAK_TIMEOUT bit bit 7 has been set If RXSTALL is set it indicates that the target did not accept the command e g because it is not supported by the target device and so has issued a STALL response If ERROR is set it means that the controller has tried to send the SETUP Packet and the following data packet three times without getting any response If NAK_TIMEOUT is set it means that the controller has received a NAK response to each attempt to send the SETUP packet for longer than the time set in HOST_NAKLIMITO The controller can then be directed either to continue trying this transaction until it times out again by clearing the NAK_TIMEOUT bit or to abort the transaction by flushing the FIFO before clearing the NAK_TIMEOUT bit If none of RXSTALL ERROR or NAK_TIMEOUT is set the SETUP Phase has been correctly A
225. urrent control transfer and set the state to IDLE Once the software has determined that the interrupt was not generated by an illegal bus state the next action taken depends on the endpoint state Figure 5 shows the flow of this process If endpoint 0 is in IDLE state the only valid reason an interrupt can be generated is as a result of the controller receiving data from the bus The service routine must check for this by testing the RXPKTRDY bit of PERI_CSRO bit 0 If this bit is set then the controller has received a SETUP packet This must be unloaded from the FIFO and decoded to determine the action the controller must take Depending on the command contained within the SETUP packet endpoint 0 will enter one of three states e If the command is a single packet transaction SET_ADDRESS SET_INTERFACE etc without any data phase the endpoint will remain in IDLE state e If the command has an OUT data phase SET_DESCRIPTOR etc the endpoint will enter RX state e f the command has an IN data phase GET_DESCRIPTOR etc the endpoint will enter TX state If the endpoint 0 is in TX state the interrupt indicates that the core has received an IN token and data from the FIFO has been sent The software must respond to this either by placing more data in the FIFO if the host is still expecting more data or by setting the DATAEND bit to indicate that the data phase is complete Once the data phase of the transaction has been completed endp
226. value after reset Table 95 Transmit Endpoint FIFO Size TXFIFOSZ Field Descriptions Bit Field Value Description 7 5 Reserved 0 Reserved 4 DPB Double packet buffering enable 0 Single packet buffering is supported 1 Double packet buffering is enabled 3 0 SZ 0 Fh Maximum packet size to be allowed before any splitting within the FIFO of Bulk packets prior to transmission If m SZ 3 0 the FIFO size is calculated as 2 3 for single packet buffering and 2 4 for dual packet buffering 4 80 Receive Endpoint FIFO Size RXFIFOSZ Section 2 5 describes dynamically setting endpoint FIFO sizes The Receive Endpoint FIFO Size RXFIFOSZ is shown in Figure 95 and described in Table 96 Figure 95 Receive Endpoint FIFO Size RXFIFOSZ 7 5 4 3 0 Reserved DPB SZ HO R W 0 HO LEGEND R W Read Write R Read only n value after reset Table 96 Receive Endpoint FIFO Size RXFIFOSZ Field Descriptions Bit Field Value Description 7 5 Reserved 0 Reserved 4 DPB Double packet buffering enable 0 Single packet buffering is supported 1 Double packet buffering is enabled 3 0 SZ 0 Fh Maximum packet size to be allowed before any splitting within the FIFO of Bulk packets prior to transmission If m SZ 3 0 the FIFO size is calculated as 2 3 for single packet buffering and 2 for dual packet buffering 138 Universal Serial Bus USB Controller SPRUGH3
227. ytes actually received in the packet s last buffer The software initialized value is the buffer size The overwritten value will be less than or equal to the software initialized value e Set the EOP bit in the packet s EOP buffer descriptor e Set the EOQ bit in the packet s EOP buffer descriptor if the current packet is the last packet in the queue e Overwrite the packet s SOP buffer descriptor Buffer Offset with the Rx DMA state value the software initialized the buffer descriptor Buffer Offset value to zero All non SOP buffer descriptors must have a zero Buffer Offset initialized by the host e Overwrite the packet s SOP buffer descriptor buffer length with the number of valid data bytes in the buffer If the buffer is filled up the buffer length will be the buffer size minus buffer offset e Set the SOP bit in the packet s SOP buffer descriptor e Write the SOP buffer descriptor Packet Length field e Clear the Ownership bit in the packet s SOP buffer descriptor e Issue an Rx DMA interrupt to the host processor by writing the address of the packet s last buffer descriptor to the queue s Rx DMA State Completion Pointer RCPPICOMPPTR register On interrupt the software processes the Rx buffer queue detecting received packets by the status of the Ownership bit in each packet s SOP buffer descriptor If the Ownership bit is cleared then the packet has been completely received and is available to be processed by the so
228. ze is an integral multiple of 64 bytes RNDIS Mode Setup The setup of RNDIS mode DMA is similar to the default Transparent Mode as mentioned in the previous section The following steps need to be taken for setting up RNDIS mode Rx DMA e RNDIS mode requires that the associated MaxPkt Size and FIFO size must be integral multiples of 64 bytes e After reset the software must write zeroes to all Rx DMA State registers RCPPIDMASTATEWO RCPPIDMASTATEW1 RCPPIDMASTATEW2 RCPPIDMASTATEW3 RCPPIDMASTATEW4 RCPPIDMASTATEW5 and RCPPIDMASTATEWE6 e The software constructs receive queue in memory e Enable DMA for the endpoint in the PERI_RXCSR or HOST_RXCSR by setting the DMAEN bit e Enable the DMA ports by setting RCPPI_ENABLE bit of RCPPICR register e Set RNDIS bit of CTRLR register for enabling RNDIS mode for all channels or set TXnEN bit of RNDISR register for specific DMA channel n e Set the value in RBUFCNTn register where n is the channel number for the number of buffers available in the Rx queue The minimum value should be 3 for the Rx DMA to start operation The value in RBUFCNTn decrements as DMA controller consumes the buffers for reception e Write the head of the queue descriptor pointer to the RCPPIDMASTATEW1 register to start the DMA e The USB controller will send IN token and wait for the data on the bus Once data is received DMA controller will transfer the data in the Rx queue from the endpoint FIFO Once a complete DMA pa
229. zes uncomment the desired size This example uses 64 byte fifo int fifosize 0 8 bytes int fifosize 1 16 bytes int fifosize 2 32 bytes int fifosize 3 64 bytes int fifosize 4 128 bytes int fifosize 5 256 bytes int fifosize 6 512 bytes int fifosize 7 1024 bytes int fifosize 8 2048 bytes int fifosize 9 4096 bytes FIFO address Leave 64 bytes for endpoint 0 int fifo_start_address 8 Uncomment the desired buffering If double buffer is selected actual FIFO space will be twice the value listed above for fifosize This example uses single buffer int double_buffer 0 Single buffer int double_buffer 1 Double buffer Set the following variable to the device endpoint type CONTROL ISO BULK or IN int device_protocol BULK int device_protocol ISO int device_protocol INT USB speeds define LOW_SPEED 0 define FULL_SPEED 1 define HIGH_SPEED 2 TXTYPE protocol define CONTROL 0 define ISO 1 define BULK 2 define INT 3 For maximum packet size this formula will usually work but it can also be set to another value if needed If non power of 2 value is needed such as 1023 set it explicitly define FIFO_MAXP 8 1 lt lt fifosize Set the following variable to the device address int device_address 1 Set the following variable to the device endpoint number int device_ep 1 Variable used for end

Texas Instruments TMS320DM357 User's Manual

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