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Texas Instruments TMS320C64x DSP User's Manual

1. 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 Y 81 Y 30 Y 29 Y 28 Y 27 Y 26 Y 25 Y 24 Y 23 Y22 Y 21 Y 20 Y 19 Y 18 Y 17 Y 16 Y 15 Y 14 Y 13 Y 12 Y 11 Y 10 Y9 Y8 Y FIFO Y7 Y6 Y5 Y4 Y3 Y2 Y1 YO 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 4 Cb 15 Cb14 Cb 13 Cb 12 Cb 11 Cb 10 Cb9 Cb8 Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb 1 Cb 0 Cb FIFO 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 4 Cr 15 Cr 14 Cr 13 Cr 12 Cr 11 Cr 10 Cr9 Cr8 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cro Cr FIFO f Little Endian Packing 63 56 55 48 47 40 39 32 81 24 23 16 15 8 7 0 Y 24 Y25 Y 26 Y 27 Y 28 Y 29 Y 30 Y 31 Y 16 Y 17 Y 18 Y 19 Y 20 Y 21 Y 22 Y 23 Y8 Y9 Y 10 Y11 Y 12 Y 13 Y 14 Y 15 Y FIFO YO Y1 Y2 Y3 Y4 Y5 Y6 Y7 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 4 Cb8 Cb9 Cb10 Cb 11 Cb 12 Cb 13 Cb 14 Cb 15 Cb 0 Cb 1 Cb2 Cb3 Cb4 Cb5 Cb6 Cb7 Cb FIFO 63 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 4 Cr8 Cr9 Cr 10 Cr 11 Cr12 Cr 13 Cr 14 Cr 15 Cro Cr1 Cr2 Cr3 Cr4 Cr5 Cr 6 Cr7 Cr FIFO Big Endian Packing SPRU629 Video Capture Port 3 9 BT 656 Video Capture Mode The 10 bit BT 656 mode uses three FIFOs for color separation Two samples are packed into each word with zero or sign extension as shown in Figure 3 3 Figure 3 3 10 Bit BT 656 FIFO Packing VELKINA veLKINB LT LT LT LE LILI LIT LE LE LT LI VDIN 9 0 VDIN 19 10
2. One Line ka Next Line FPCOUNT es se ez o Ti P27 OO vokour UUUUUUUU o uuuunnnn Tyr a4 ma 268 4 4 ma 1440 gt R Blanking Ma Active Video 2 o 2 om olol ojojo ojojo 2 0 9 2 2 9 0 Tha Q 0 ooosoesooo VDOUT 9 0 HS SxS 8 2 5 SE 898 53 als s s ESI S amp 5 5 2 a EAV Blanking Data SAV EAV SPRU629 Video Display Port 4 9 BT 656 Video Display Mode Figure 4 10 625 50 BT 656 Horizontal Blanking Timing n One Line ma Next Line FPCOUNT 720 721 722 723 861 862 863 0 1 2 718 719 720 721 722 723 veLkouT UUW UC Ed lt _4 pla 280 ba 4 ma 1440 je Blanking gt ja Active Video oleae siesels elelosleses e 2 eB8eloeeseseesese VDOUTI9 0 tss gie 3 2 9 s598 5 8 alcssE ss sess EAV Blanking Data SAV EAV SAV and EAV codes are identified by a 3 byte preamble of FFh 00h and 00h This combination must be avoided in the video data output by the video port to prevent accidental generation of an invalid sync code The video display module provides programmable maximum and minimum value clipping on the video data to prevent this possibility The typical v
3. VDOUT 9 0 63 5857 4847 4241 3231 2625 1615 109 0 Y 15 Y 14 Y 13 Y 12 Y 11 Y 10 Y9 Y8 Y7 Y6 Y5 Y4 Y FIFO Y3 Y2 Y1 YO 63 5857 4847 4241 3231 2625 1615 109 0 1 Cb7 Cb6 Cb5 Cb4 Cb FIFO Cb3 Cb2 Cb1 Cb0 63 5857 4847 4241 3231 2625 1615 109 0 1 Cr7 Cr6 Cr5 Cr4 Cr FIFO Cr3 Cr2 Cr1 Cro Little Endian Unpacking 63 5857 4847 4241 3231 2625 1615 109 0 Y 12 Y 13 Y 14 Y 15 Y8 Y9 Y 10 Yi Y4 Y5 Y6 Y7 Y FIFO YO Y 1 Y2 Y3 63 5857 4847 4241 3231 2625 1615 109 0 t Cb4 Cb5 Cb6 Cb7 Cb FIFO Cb 0 Cb 1 Cb 2 Cb 3 63 5857 4847 4241 3231 2625 1615 109 0 1 Cr4 Cr5 Cr6 Cr7 Cr FIFO Cro Cr1 Cr2 Cr3 Big Endian Unpacking 4 14 Video Display Port SPRU629 BT 656 Video Display Mode In 10 bit BT 656 dense pack mode three samples are unpacked from each word in the FIFO as seen in Figure 4 14 Figure 4 14 BT 656 Dense FIFO Unpacking VDOUT 9 0 63 61 5251 4241 3231 29 2019 109 0 Y 23 Y 22 Y 21 Y 20 Y 19 Y 18 Y 17 Y 16 Y 15 Y 14 Y 13 Y 12 Y 11 Y 10 Y9 Y8 Y7 Y6 Y FIFO Y5 Y4 Y3 Y2 Y 1 YO 63 61 5251 4241 3231 29 2019 109 0 t Cb 11 Cb 10 Cb9 Cb8 Cb7 Cb6 Cb FIFO Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 63 61 5251 4241 3231 29 2019 109 0 t Cr 11 Cr 10 Cr9 Cr 8 Cr7 Cr6 Cr FIFO Cr5 Cr4 Cr3 Cr2 Cr 1 Cro Little Endian Unpacking
4. 63 5857 48 47 4241 3231 2625 1615 10 9 0 0 SE Y 15 0 SE Y 14 0 SE Y 13 0 SE Y 12 i 0 SE Yd 0 SE Y 10 0 SE Y9 0 SE Y8 0 SE Y7 0 SE Y6 0 SE Y4 0 SE Y4 Y FIFO 0 SE Y3 0 SE Y2 0 SE Y 1 0 SE YO 63 5857 48 47 4241 3231 2625 1615 10 9 0 0 SE Cb 7 0 SE Cb 6 0 SE Cb5 0 SE Cb4 xs 0 SE Cb3 0 SE Cb2 0 SE Cb 1 0 SE Cb 0 63 5857 48 47 42 41 3231 2625 1615 10 9 0 0 SE Cr7 0 SE Cr6 0 SE Cr5 0 SE Cr4 cass 0 SE Cr3 0 SE Cr2 0 SE Cr 1 0 SE Cro Little Endian Packing 63 58 57 48 47 4241 3231 26 25 1615 10 9 0 0 SE Y12 0 SE Y18 0 SE Y14 0 SE Y15 0 SE Y8 0 SE Y9 0 SE Y10 0 SE vi 0 SE Y4 0 SE Y4 0 SE Y6 0 SE Y7 YFIFO 0 SE YO 0 SE Yi 0 SE Y2 0 SE Y3 63 58 57 4847 4241 3231 26 25 1615 109 0 0 SE Cb4 0 SE Cb5 0 SE Cb 6 0 SE Cb7 cbriro POSE Cb0 0 SE Cb 1 0 SE Cb2 0 SE Cb3 63 58 57 4847 4241 3231 26 25 1615 109 0 4 0 SE Cr4 0 SE Cr5 0 SE Cr6 0 SE Cr7 CrFIFO 0 SE Cro 0 SE Cr 1 0 SE Cr2 0 SE Cr3 Big Endian Packing 3 10 Video Capture Port SPRU629 BT 656 Video Capture Mode The 10 bit BT 656 dense mode uses three FIFOs for color separation Three samples are packed into each word with zero extension to provide increased DMA bandwidth as shown in Figure 3 4 Figure 3 4 10 Bit BT 656 Dense FIFO Packing veLKINA VCLKING UI U LT LT LILI LILI LI Li Li VDIN 9 0 VDIN19 10
5. define VCA IMG HSIZE1 720 fieldl horizontal image size define VCA IMG VSIZE1 244 263 20 1 fldl vertical image size define VCA IMG HSIZE2 720 field2 horizontal image size define VCA IMG VSIZE2 243 525 283 1 fld2 vertical image size Define field image sizes define VCA IMAGE SIZE1 VCA IMG HSIZE1 VCA IMG VSIZE1 define VCA IMAGE SIZE2 VCA IMG HSIZE2 VCA IMG VSIZE2 S Define channel A capture window co ordinates for Fieldl kf HRST 0 start of horizontal blanking define VCA XSTART1 VCA HBLNK SIZE 2 EAV VRST 1 end of vertical blanking define VCA YSTART1 a define VCA XSTOP1 VCA XSTART1 VCA IMG HSIZE1 1 define VCA YSTOP1 VCA YSTART1 VCA IMG VSIZE1 1 pt Kf Define channel A capture window co ordinates for Field2 px EJ HRST 0 start of horizontal blanking define VCA_XSTART2 VCA HBLNK SIZE 2 EAV VRST 1 end of vertical blanking define VCA YSTART2 1 define VCA XSTOP2 VCA XSTART2 VCA IMG HSIZE2 1 define VCA YSTOP2 VCA YSTART2 VCA IMG VSIZE2 1 Define threshold values in double words Both fields should y same threshold value x define VCA THRID FIELDI1 VCA IMG HSIZE1 8 line length in define VCA THRLD FIELD2 VCA_THRLD_FIELD1 double words Define number of events to be generated for fieldl and field2 define VCA CAPEVT1 VCA IM
6. x 4 Define frame size JR ih define VD FRM WIDTH 858 no of pixels per frame lin including horizontal blanking x define VD FRM HEIGHT 525 total noof lines per frame define VD FRM SIZE VD FRM WIDTH VD FRM HEIGHT ts EE x Horizontal blanking f8 x define VD HBLNK START 720 starting location of EAV define VD HBLNK STOP 856 starting location of SAV define VD HBLNK SIZE VD HBLNK STOP VD HBLNK START 2 EAV 138 EAV SAV inclusive D Vertical blanking for fieldl Ki define VD VBINK XSTART1 720 pixel on which VBINK active edge occurs for fieldl define VD VBINK YSTART1 al line on which VBLNK active edge occurs for fieldl define VD VBLNK XSTOP1 720 pixel on which VBLNK inactive edge occurs for fieldl define VD VBLNK YSTOP1 20 line on which VBLNK inactive edge occurs for fieldl fx d Vertical blanking for field2 Kid define VD VBINK XSTART1 360 pixel on which VBINK active edge occurs for field2 define VD VBLNK YSTART1 263 line on which VBLNK active edge occurs for field2 define VD VBLNK XSTOP1 360 pixel on which VBLNK inactive edge occurs for field2 define VD VBLNK YSTOP1 283 line on which VBLNK inactive edge occurs for field2 A 10 Video Port Configuration Examples SPRU629 E
7. 63 61 5251 4241 3231 29 20 19 10 9 0 00 Y 23 Y22 Y 21 00 Y 20 Y 19 Y 18 00 Y 17 Y 16 Y 15 00 Y 14 Y 13 Y 12 00 Y 11 Y 10 Y9 00 Y8 Y7 Y6 Y FIFO 00 Y5 Y4 Y3 00 Y2 Y 1 YO 63 61 5251 4241 3231 29 20 19 10 9 0 00 Cb 11 Cb 10 Cb 9 00 Cb 8 Cb 7 Cb 6 Cb FIFO 00 Cb 5 Cb 4 Cb 3 00 Cb 2 Cb 1 Cb 0 63 61 5251 4241 3231 29 20 19 10 9 0 4 00 Cr 11 Cr 10 Cr 9 00 Cr8 Cr 7 Cr 6 Cr FIFO L 100 Cr5 Cr4 Cr 3 00 Cr2 Cr 1 Cro Little Endian Packing 63 61 5251 4241 3231 29 20 19 10 9 0 00 Y 18 Y 19 Y 20 00 Y 21 Y22 Y 23 00 Y 12 Y 13 Y 14 00 Y 15 Y 16 Y 17 00 Y6 Y7 Y8 00 Y9 Y 10 Y 11 YFIFO 00 YO Y1 Y2 00 Y3 Y4 Y5 63 61 52 51 4241 3231 29 2019 109 0 00 Cb 6 Cb 7 Cb 8 00 Cb 9 Cb 10 Cb 11 Cb FIFO L 00 Cb 0 Cb 1 Cb 2 00 Cb 3 Cb 4 Cb 5 63 61 5251 4241 3231 29 20 19 10 9 0 00 Cr 6 Cr 7 Cr8 00 Cr9 Cr 10 Cr 11 Cr FIFO 00 Cro Cr1 Cr2 00 Cr3 Cr4 Cr 5 Big Endian Packing SPRU629 Video Capture Port 3 11 Y C Video Capture Mode 3 3 Y C Video Capture Mode The Y C capture mode is similar to the BT 656 capture mode but captures 8 or 10 bit 4 2 2 data on separate luma and chroma data streams One data stream contains Y samples and the other stream contains multiplexed Cb and Cr samples co sited with every other Y sample The Y samples are written into a Y FIFO and the chroma samples are demultiplexed
8. 63 61 5251 4241 3231 29 2019 10 9 0 Y 18 Y 19 Y 20 Y 21 Y 22 Y 23 Y 12 Y 13 Y 14 Y 15 Y 16 Y 17 Y6 Y7 Y8 Y9 Y 10 Yt Y FIFO Yo Yi Y2 Y3 Ya Y5 63 61 5251 4241 3231 29 2019 109 o 1 Cb6 Cb7 Cb8 Cb9 Cb 10 Cb 11 Cb FIFO Cb0 Cb 1 Cb2 Cb3 Cb4 Cb5 63 61 5251 4241 3231 29 2019 10 9 o t Cr6 Cr7 Cr8 Cr9 Cr 10 Cr 11 Cr FIFO Cro Cr1 Cr2 Cr3 Cr4 Cr 5 Big Endian Unpacking SPRU629 Video Display Port 4 15 Y C Video Display Mode 4 3 Y C Video Display Mode The Y C display mode is similar to the BT 656 display mode but outputs 8 or 10 bit data on separate luma and chroma data streams One data stream contains Y samples and the other stream contains multiplexed Cb and Cr samples co sited with every other luminance sample The Y samples are read from the Y FIFO and the Cb and Cr samples are read from the Cb and Cr FIFOs and combined on the chroma output The unpacking and order of the samples is determined by the sample size 8 bit or 10 bit and the device endian mode The Y C display mode can generate HDTV standard output such as BT 1120 SMPTE260 or SMPTE296 with embedded EAV and SAV codes It can also output separate control signals Because 16 or 20 bits are used for data output the Y C output mode requires both halves of the video port data bus If the DCHDIS bit in VPCTL is set then Y C mode cannot be selected 4 3 1 Y C Display Timing Reference Codes The EAV and SAV embedded timing codes are identical to t
9. Video Port Pin Function Register PFUNC Field Descriptions 2 Video Port Pin Direction Register PDIR Field Descriptions se Video Port Pin Data Input Register PDIN Field Descriptions Video Port Pin Data Out Register PDOUT Field Descriptions Video Port Pin Data Set Register PDSET Field Descriptions Video Port Pin Data Clear Register PDCLR Field Descriptions Video Port Pin Interrupt Enable Register PIEN Field Descriptions Video Port Pin Interrupt Polarity Register PIPOL Field Descriptions Video Port Pin Interrupt Status Register PISTAT Field Descriptions Video Port Pin Interrupt Clear Register PICLR Field Descriptions VIC Port Interface Signals 0 000 cent eee eens Example Values for Interpolation Rate 2 cece eee eee eee VIC Port Registers 0 eee mm hn VIC Control Register VICCTL Field Descriptions VIC Input Register VICIN Field Descriptions 00 cece eee ees VIC Clock Divider Register VICDIV Field Descriptions 0000 eee ee SPRU629 Tables xvii Chapter 1 Overview This chapter provides an overview of the video port peripheral in the digital signal processors DSPs of the TMS320C6000 DSP family Included are an overview of the vide
10. a VCLK1 TSI clock pes VCTL1 CAPENA decoder 4 VCTL2 PACSTRT with VCTL3 PACERR FEC 5V DC 2 2 KQ VCXO 27 MHz VCTL 22 KQ ae Ld ie 100 pF STCLK i SPRU629 6 2 Interface Interface Operational Details The pin list for VIC port is shown in Table 6 1 pins are 3 3V I Os Table 6 1 VIC Port Interface Signals VIC Port Signal Direction Description VCTL Output VCXO control STCLK Input System time clock 6 3 Operational Details Synchronization is an important aspect of decoding and presenting data in real time digital data delivery systems This is addressed in the MPEG trans port packets by transmitting timing information in the adaptation fields of selected data packets This serves as a reference fortiming comparison in the receiving system A sample of the 27 MHz clock the program clock reference PCR header is shown in Figure 6 2 is transmitted within the bit stream which indicates the expected time at the completion of reading the field from the bit stream at the transport decoder The sample is a 42 bit field 9 bits cycle from 0 to 299 at 27 MHz while the other 33 bit field is incremented by 1 each time the 9 bit field reaches a value of 299 The transport data packets are in sync with the server system clock Figure 6 2 Program Clock Reference PCR Header Format 47 SPRU629 15 14 9 8 0 PCR PCR extension The video port in conjunction with the VIC port uses a combine
11. 4 12 12 Video Display Field 2 Image Size Register VDIMGSZ2 4 12 13 Video Display Field 1 Timing Register DFLDT1 a 4 12 14 Video Display Field 2 Timing Register VDFLDT2 4 12 15 Video Display Threshold Register VDTHRLD 00 000 4 12 16 Video Display Horizontal Synchronization Register VDHSYNC 4 12 17 Video Display Field 1 Vertical Synchronization Start Register VDVSYNS1 ssieueeee A Wla 4 12 18 Video Display Field 1 Vertical Synchronization End Register VDVSYNE1 8 99m Ga 4 12 19 Video Display Field 2 Vertical Synchronization Start Register VDVSYNS2 MI MR cence ene ees 4 12 20 Video Display Field 2 Vertical Synchronization End Register VDVSYNE2 a UB NP ee eee 4 12 21 Video Display Counter Reload Register VDRELOAD 4 12 22 Video Display Display Event Register VDDISPEVT 4 12 23 Video Display Clipping Register VDCLIP 2a 4 12 24 Video Display Default Display Value Register VDDEFVAL 4 12 25 Video Display Vertical Interrupt Register VDVINT sssee 4 12 26 Video Display Field Bit Register VDFBIT a 4 12 27 Video Display Field 1 Vertical Blanking Bit Register VDVBIT1 4 12 28 Video Display Field 2 Vertical Blanking Bit Register VDVBIT2 4 13 Video Display Registers Re
12. 0055 4 50 Video Display Field 2 Image Size Register VDIMGSZ2 0 aa 4 51 Video Display Field 1 Timing Register VDFLDT1 00 cece eee eee ee 4 52 Video Display Field 2 Timing Register VDFLDT2 00 cece eee eee 4 53 Video Display Threshold Register VDTHRLD 2 0000 c cece eee eee 4 54 Video Display Horizontal Synchronization Register VDHSYNC 4 4 55 Video Display Field 1 Vertical Synchronization Start Register VDVSYNS1 4 56 Video Display Field 1 Vertical Synchronization End Register VDVSYNE1 4 57 Video Display Field 2 Vertical Synchronization Start Register VDVSYNS2 4 58 Video Display Field 2 Vertical Synchronization End Register VDVSYNE2 4 59 Video Display Counter Reload Register VDRELOAD 00000e ee aces 4 60 Video Display Display Event Register VDDISPEVT 0 ccc cece e need SPRU629 Figures xiii Figures 4 61 4 62 4 63 4 64 4 65 4 66 4 67 5 1 5 2 5 3 A SALAT OONO ABO N N O c1 xiv Video Display Clipping Register VDCLIP 0 Video Display Default Display Value Register VDDEFVAL Luuuuusssssss Video Display Default Display Value Register VDDEFVAL Raw Data Mode Video Display Vertical Interrupt Register VDVINT 2 0 cece eee eee Video Display Field Bit Register VDFBIT
13. set field2 timing x VP RSETH vpDisplayHandle VDFLDT2 VP VDFLDT2 RMK VD FIELD2 YSTART VD FIELD2 XSTART set display field bit register VD FBIT VP RSETH vpDisplayHandle VDFBIT VP VDFBIT RMK VD FBIT SET VD FBIT CLR set horizontal sync control VCTL1S x VP RSETH vpDisplayHandle VDHSYNC VP VDESYNC RMK VD HSYNC STOP VD HSYNC START se VP RS vertical sync start for fieldl VCTL2S TH vpDisplayHandle VDVSYNS1 VP VDVSYNS1 RMK VD_VSYNC_YSTART1 VD_VSYNC_XSTART1 EH 1 se VP RS vertical sync end for fieldl VCTL2S TH vpDisplayHandle VDVSYNE1 VP_VDVSYNE1_RMK VD_VSYNC_YSTOP1 VD VSYNC XSTOP1 ER MAN se VP RS vertical sync start for field2 VCTL2S TH vpDisplayHandle VDVSYNS2 VP VDVSYNS2 RMK VD VSYNC YSTART2 VD VSYNC XSTART2 Gl T SPRU629 Video Port Configuration Examples A 15 Example 2 Noncontinuous Frame Display for 525 60 Format A 16 se t vertical sync end for field2 VCTL2S VP RSETH vpDisplayHandle VDVSYNE2 VP VDVSYNE2 RMK VD VSYNC YSTOP2 VD VSYNC XSTOP2 Let clipping values to be their defaults VD CLIP No need to set DEF VAL and VD RELOAD in this example set event register VP RSETH vpDisplayHandle VDDISPEVT VP VDDISPEVT RMK VD DISPEVT2 VD DISPEVT1 Vertical interrupts are not used
14. 22 42 e 4 9 525 60 BT 656 Horizontal Blanking Timing cece eee teens 4 10 625 50 BT 656 Horizontal Blanking Timing 0 c cece eee eee 4 11 Digital Vertical F and V Transitions 0 cece cece 4 12 8 Bit BT 656 FIFO Unpacking a ss re 4 13 10 Bit BT 656 FIFO Unpacking aa sss 4 14 BT 656 Dense FIFO Unpacking 0 00 cece eee eens 4 15 Y C Horizontal Blanking Timing BT 1120 601 0 0 e cece eee 4 16 8 Bit Y C FIFO Unpacking 2 22 2Ha teeta xii SPRU629 Figures 4 17 10 Bit Y C FIFO Unpacking ssssssssssesees RII rs 4 18 10 Bit Y C Dense FIFO Unpacking sssssssesssee e 4 19 Chrominance Resampling ns 4 20 2x Co Sited Scaling n 4 21 2x Interspersed Scaling c cece eee eens 4 22 Output Edge Pixel Replication 0 00 ccc ccc eens 4 23 Luma Edge Replication 0 cect el 4 24 Interspersed Chroma Edge Replication 000 c eee ee eee eee 4 25 8 Bit Raw FIFO Unpacking 00 ccc Rel 4 26 10 Bit Raw FIFO Unpacking 00 ccc eet eae 4 27 10 Bit Raw Dense FIFO Unpacking cc cece teenie 4 28 16 Bit Raw FIFO Unpacking 0 00 cece ete eee nl 4 29 20 Bit Raw FIFO Unpacking 00 ccc eee een 4 30 8 Bit Raw 3 4 FIFO Unpacking 2 enaa 4 31 10 Bit Raw 3 4 FIFO Unpacking 000 cee RII
15. 0 0c cece eee eee Video Display Field 1 Vertical Blanking Bit Register VDVBIT1 Video Display Field 2 Vertical Blanking Bit Register VDVBIT2 0 Video Port Peripheral Identification Register VPPID a Video Port Peripheral Control Register PCR 0 0000 cece eee eee eee ee Video Port Pin Function Register PFUNC 000 cc ee eee eee eee Video Port Pin Direction Register PDIR 0 cece eee Video Port Pin Data Input Register PDIN a re cece eee II Video Port Pin Data Output Register PDOUT 20 02 cece eee Video Port Pin Data Set Register PDSET 0 0 0 cee cece eee Video Port Pin Data Clear Register PDCLR 20 e cece eee eee eee Video Port Pin Interrupt Enable Register PIEN 0c cece eee eee eee Video Port Pin Interrupt Polarity Register PIPOL cece eee ee eee Video Port Pin Interrupt Status Register PISTAT cce cece eee Video Port Pin Interrupt Clear Register PICLR 2 cece eee eee eee TSI System Block Diagram Program Clock Reference PCR Header Format 0 000 a VIC Control Register VICCTL VIC Input Register VICIN VIC Clock Divider Register VICDIV SPRU629 Id LE E I dg oobi bbiddbdddbthordbsh eee vee ds OMAN OA RWN O ee ee qs oo ae D P ip nore ee Se En ee Fa To pode o
16. Default Value Default Value Default Value Default Value FIFO Data FIFO Data FIFO Data FIFO Data Default Value Default Value FLD1XSTART 720 FLD1YSTART 1 FLD2XSTART 360 FLD2YSTART 263 FBITSET n a FBITCLR n a t Assumes VCT2P bit in VPCTL is set to 1 active low output VSYNC output when VCTL2S bit in VDCTL is set to 00 VBLNK output when VCTL2S bit is set 01 4 42 Video Display Port SPRU629 Display Timing Examples 4 9 3 Y C Progressive Display Example SPRU629 This section shows an example of progressive display operation The output format follows SMPTE 296M 2001 specifications for a 1280 x 720 60 system The example is for a 1264 x 716 progressive output image The horizontal output timing is shown in Figure 4 37 This diagram assumes that there is a two VCLK pipeline delay between the internal counter changing and the output on external pins The actual delay can be longer or shorter as long as it is consistent within any display mode The SMPTE 296M 60 Hz active line is 1650 pixels wide Figure 4 37 shows the 1264 pixel image window centered in the screen that results in an IMGHOFFx of 8 pixels The HBLNK and HSYNC signals are shown as they would be output for active low operation Note that only one of the two signals is actually available exter nally The HBLNK inactive edge occurs either on sample 1646 coincident with the start of SAV or on sample 0 after SAV if the HBDLA bit is set
17. Display Image E Blanking rf Active Video gt pa a gt A gt gt b gt S gt voouns as ReER ER aee 3892012025585 Eee EEFE BERBEESE 5 BBBB SB 3 8 8 voouriie oi BE BEESBEE mH M NN EAV Blanking Data SAV FLCOUNT n i n FRMWIDTH 1650 IMGHOFF1 8 HSYNCSTART 1350 HBLNKSTART 1280 7 IMGHSIZE1 1264 HSYNCSTOP 1430 HBLNKSTOP 1646 IMGHOFF2 n a IMGHSIZE2 n a t Assumes VCT1P bit in VPCTL is set to 1 active low output HSYNC output when VCTL1S bit in VDCTL is set to 00 HBLNK output when VCTL1S bit is set 01 t HBLNK operation when HBDLA bit in VDHBLNK is set to 1 Diagram assumes a two VCLK pipeline delay between internal counters and output signals SPRU629 Display Timing Examples The vertical output timing is shown in Figure 4 38 SMPTE 296M has a single active field 1 that is 720 lines high This example shows the 716 line image window with an IMGVOFFn of 3 lines and also results in a nondata line at the end of the field The VBLNK and VSYNC signals are shown as they would be output for active low operation Note that only one of the two signals is actually available exter nally The VBLNK and VSYNC edges occur at the end of an active line so their XSTART XSTOP values are set to 1280 start of blanking The field 2 vertical timing start and stop registers are programmed to a value greater than 750 Since this value is never reached by FLCOUNT no extra VBLNK or VSYNC transitions occur For true SMPTE
18. 31 26 25 16 R 0 15 10 9 R W 0 0 R 0 Legend R Read only R W Read Write n value after reset Table 3 21 Bit fieldt 31 26 Reserved symvalt R W 0 Description Video Capture Channel x Threshold Register VCxTHRLD Field Descriptions Value BT 656 or Y C Mode Raw Data Mode TSI Mode 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 25 16 VCTHRLD2 OF value O 3FFh Number of field 2 Not used Not used doublewords required to generate DMA events 15 10 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 9 0 VCTHRLD1 OF value 0 3FFh Number of field 1 Number of raw Number of doublewords data doublewords doublewords required to generate required to required to DMA events generate a DMA generate a DMA event event t For CSL implementation use the notation VP VCXTHRLD VCTHRLDn symval 3 66 Video Capture Port SPRU629 Video Capture Registers 3 13 9 Video Capture Channel x Event Count Register VCAEVTCT VCBEVTCT The video capture channel x event count register VCAEVTCT VCBEVTCT is programmed with the number of DMA events to be generated for each capture field VCxEVTCT is shown in Figure 3 37 and described in Table 3 22 An event counter tracks how many events have been generated and indicates which threshold value VCTHRLD1 or VC
19. 0 0 cece tee eens 4 2 BT 656 Video Display Mode a eee tenets 4 2 1 Display Timing Reference Codes cece eee t eens 4 2 2 Blanking Codes 0 00 ee es 4 2 3 BT 656 Image Display 2 O a o oa 4 2 4 BT 656 FIFO Unpacking 00 ccs 43 Y C Video Display Mode 000 cece ete eens 4 3 1 Y C Display Timing Reference Codes aa 4 3 2 Y C Blanking Codes Aa cece teenies 4 3 8 Y C Image Display 0 060 c cece cette III 4 3 4 Y C FIFO Unpacking 0 2002 Y aaa 4 4 Video Output Filtering iaaea aanne tte eens 4 4 4 Output Filter Modes 0 b cece s 4 4 2 Chrominance Resampling Operation 000 c eee eee eee eee 4 4 8 Scaling Operation 0 cece tenes 4 4 4 Edge Pixel Replication 0 00 ccc eee ees 4 5 Ancillary Data Display W W ttn tenes 4 5 1 Horizontal Ancillary HANC Data Display cece eee 4 5 2 Vertical Ancillary VANC Data Display 000 e cece eee ee 4 6 Raw Data Display Mode 00 cece eee e eens 4 6 1 Raw Mode RGB Output Support 0 2 00 cece eee ee 4 6 2 Raw Data FIFO Unpacking 0c eee eee 4 7 Video Display Field and Frame Operation 0000 c cee eee eee ees 4 7 1 Display Determination and Notification 00 eee eee 4 7 2 Video Display Event Generation 000 0c cece eee
20. 2 0 DMODE Display mode select bit BT656B 0 Enables 8 bit BT 656 mode BT656D th Enables 10 bit BT 656 mode RAWB 2h Enables 8 bit raw data mode RAWD 3h Enables 10 bit raw data mode YC16 4h Enables 8 bit Y C mode YC20 5h Enables 10 bit Y C mode RAW16 6h Enables 16 bit raw data mode RAW20 7h Enables 20 bit raw data mode t For CSL implementation use the notation VP_VDCTL_field_symval For complete encoding of these bits see Table 4 4 SPRU629 Video Display Port 4 59 Video Display Registers 4 12 3 Video Display Frame Size Register VDFRMSZ The video display frame size register VDFRMSZ sets the display channel frame size by setting the ending values for the frame line counter FLCOUNT and the frame pixel counter FPCOUNT The VDFRMSZ is shown in Figure 4 41 and described in Table 4 8 The FPCOUNT starts at 0 and counts to FRMWIDTH 1 before restarting The FLCOUNT starts at 1 and counts to FRMHEIGHT before restarting Figure 4 41 Video Display Frame Size Register VDFRMSZ 31 28 27 16 R 0 R W 0 15 12 11 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 4 8 Video Display Frame Size Register VDFRMSZ Field Descriptions Bit fieldt symvalt Value Description 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 FRMHEIGHT OF value O FFFh Defines the total number of lines per frame The
21. PCR PFUNC PDIR PDIN PDOUT PDSET PDCLR PIEN PIPOL PISTAT PICLR Register Name Video Port Peripheral Identification Register Video Port Power Management Register Video Port Pin Function Register Video Port GPIO Direction Control Register 0 Video Port GPIO Data Input Register Video Port GPIO Data Output Register Video Port GPIO Data Set Register Video Port GPIO Data Clear Register Video Port GPIO Interrupt Enable Register Video Port GPIO Interrupt Polarity Register Video Port GPIO Interrupt Status Register Video Port GPIO Interrupt Clear Register 5 2 General Purpose I O Operation Section O O O O ER A N Ln O Q 5 1 1 N lo SPRU629 GPIO Registers 5 1 1 Video Port Peripheral Identification Register VPPID The video port peripheral identification register VPPID is a read only register used to store information about the peripheral The VPPID is shown in Figure 5 1 and described in Table 5 2 Figure 5 1 Video Port Peripheral Identification Register VPPID 31 24 23 16 R 0 R 0000 0001 15 8 7 0 R 0000 1001 R xt Legend R Read only n value after reset t See the device specific datasheet for the default value of this field Table 5 2 Video Port Peripheral Identification Register VPPID Field Descriptions Bit fieldt symvalt Value Description value written to this field has no effect 23 16 TYPE Identifies type of peripheral OF value Oih Video port 15 8 CLA
22. The SDTV Y C format CCIR601 is an interlaced format consisting of two fields just like BT 656 HDTV Y C formats may be interlaced or progressive scan For interlaced capture the capture windows are programmed identically to BT 656 mode For progressive scan formats only field1 is used In Y C mode HCOUNT increments on every luma sample period every VCLKINA rising edge for which capture is enabled Once YCOUNT VCYSTART line capture begins when HCOUNT VCXSTART It continues until HCOUNT VCXSTOP A fields capture is complete when HCOUNT VCXSTOP and VCOUNT VCYSTOP For the Y C video capture mode the FIFO buffer is divided into three sections three buffers One section is 2560 bytes deep and is dedicated for storage of Y data samples The other two sections are dedicated for storage of Cb and Cr data samples respectively The buffers for Cb and Cr samples are each 1280 bytes deep The incoming video data stream is separated into Y Cb and Cr data streams scaled if selected and the Y Cb and Cr buffers are filled Each of the three buffers has a memory mapped location associated with it YSRC CBSRC and CRSRC The YSRC CBSRC and CRSRC locations are read only and are used by DMAs to access video data samples stored in the FIFOs Reads must always be 64 bits If video capture is enabled pixels in the capture window are captured in the Y Cb and Cr buffers The video capture module uses the YEVT CbEVT and CrEVT events to n
23. VDEN DPK RGBX RSYNC DVEN RESMPL Reserved SCALE R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 0 R W 0 7 6 5 4 3 2 0 R W 0 R W 0 R W 0 R W 0 R 0 R W 0 Legend R Read only R W Read Write WS Write 1 to reset write of 0 has no effect n value after reset Table 4 7 Video Display Control Register VDCTL Field Descriptions Description Bit fieldt symvalt Value BT 656 and Y C Mode Raw Data Mode 31 RSTCH Reset channel bit Write 1 to reset the bit a write of O has no effect NONE 0 No effect RESET 1 Resets the video display module and sets its registers to their initial values Also clears the VDEN bit The video display module automatically clears RSTCH after software reset is completed t For CSL implementation use the notation VP VDCTL field symval tFor complete encoding of these bits see Table 4 4 SPRU629 Video Display Port 4 5 ol Video Display Registers Table 4 7 Video Display Control Register VDCTL Field Descriptions Continued Bit 8 fieldt symvalt 30 BLKDIS CLEAR BLOCK Description Value BT 656 and Y C Mode Raw Data Mode Block display events bit BLKDIS functions as a display FIFO reset without affecting the current programmable register values The video display module continues to function normally the counters count control outputs are generated EAV SAV codes are generated for BT 656 and Y C modes and default or blanking data is output during active display time No data is moved to th
24. pin signal polarity that generates an interrupt Interrupt is caused by a low to high transition on the VDATA n pin Interrupt is caused by a high to low transition on the VDATA n pin T For CSL implementation use the notation VP_PIPOL_PIPOLn_symval 5 22 General Purpose I O Operation SPRU629 GPIO Registers 5 1 11 Video Port Pin Interrupt Status Register PISTAT The video port pin interrupt status register PISTAT is shown in Figure 5 11 and described in Table 5 12 PISTAT is a read only register that indicates the GPIO pin that has a pending interrupt A bit in PISTAT is set when the corresponding GPIO pin is configured as an interrupt the corresponding bit in PIEN is set the pin is enabled for GPIO in PFUNC and the pin is configured as an input in PDIR and the appropriate transition as selected by the corresponding PIPOL bit occurs on the pin Whenever a PISTAT bit is set to 1 the GPIO bit in VPIS is set The PISTAT bits are cleared by writing a 1 to the corresponding bit in PICLR Writing a 0 has no effect Clearing all the PISTAT bits does not clear the GPIO bit in VPIS it must be explicitly cleared If any bits in PISTAT are still set when the GPIO bit is cleared the GPIO bit is set again Figure 5 11 Video Port Pin Interrupt Status Register PISTAT 31 24 R 0 23 22 21 20 19 18 17 16 PISTAT22 PISTAT21 PISTAT20 PISTAT19 PISTAT18 PISTAT17 PISTAT16 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11
25. 1 NTSC Compatible Interlaced Display Field 1 Field 2 Line 20 Line 282 Line 21 Line 283 Line 22 Line 284 Line 261 Line 523 Sue Fe Line 524 Line 263 Line 525 Figure 4 2 SMPTE 296M Compatible Progressive Scan Display Field 1 Line 26 _ 2 V OO __ Line 27 45 a Line 28 P Line 29 Line 30 Line 741 Line 742 ae SPENT E Mau EET Line 743 Line 744 Line 745 SPRU629 Video Display Port 4 3 Video Display Mode Selection Figure 4 3 Interlaced Blanking Intervals and Video Areas A A Field 1 Vertical Blanking Field 1 Image Vertical Offset Field 1 Active Video a k We S x m D HE 4 2 io E 8 2 8 5 g IN O D Oo E O na E 2 5 3 A it g Field 1 Image Width 2 iL 5 1 LL Field 2 Vertical Blanking Field 2 Image Vertical Offset es Field 2 Active Video E A we c amp pa N ta t O ME o 5 5 e o x o HE o O e s E I gt 5 o iL E CN Field 2 Image Width 2 v nA 4 4 Video Display Port SPRU629 Video Display Mode Selection Figure 4 4 Progressive Blanking Intervals and Video Area Aa A Field 1 Vertical Blanking Field 1 Image Vertical Offset Field 1 Active Video A Bo I o T E oO S g E LL E iL S iL Field 1 Image Width A A nA 4 1 2 Video Display
26. 10 In raw data mode VBLNK is asserted whenever the frame line counter FLCOUNT is equal to VBLNKYSTART1 and the frame pixel counter FPCOUNT is equal to VBLNKXSTART1 this is shown in Figure 4 6 page In BT 656 and Y C mode VBLNK is asserted whenever FLCOUNT VBLNKYSTART1 and FPCOUNT VBLNKXSTART1 This VBLNK output control is completely independent of the timing control codes The V bit in the EAV SAV codes for field 1 is controlled by the VDVBIT1 register 4 62 Video Display Port SPRU629 Video Display Registers Figure 4 43 Video Display Field 1 Vertical Blanking Start Register VDVBLKS1 31 28 27 16 R 0 R W 0 15 12 11 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 4 10 Video Display Field 1 Vertical Blanking Start Register VDVBLKS1 Field Descriptions Description Bit fieldt symvalt Value BT 656 and Y C Mode Raw Data Mode 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 VBLNKYSTART1 OF value O FFFh Specifies the line in Specifies the line in FLCOUNT where FLCOUNT where vertical VBLNK active edge blanking begins VBLNK occurs for field 1 Does active edge for field 1 not affect EAV SAV V bit operation 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 VBLNKXSTART1 OF value O FFFh Specifies the pixel in
27. ENABLE 1 Interrupt is enabled 9 8 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 7 LFDA Long field detected on channel A interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled 6 SFDA Short field detected on channel A interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled 5 VINTA2 Channel A field 2 vertical interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled 4 VINTA1 Channel A field 1 vertical interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled 3 SERRA Channel A synchronization error interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled 2 CCMPA Capture complete on channel A interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled 1 COVRA Capture overrun on channel A interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled 0 VIE Video port global interrupt enable bit Must be set for interrupt to be sent to DSP DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled t For CSL implementation use the notation VP VPIE field symval SPRU629 Video Port 2 23 Video Port Control Registers 2 7 4 Video Port Interrupt Status Register VPIS The video port interrupt status register VPIS displays the status of video port interrupts to the DSP The
28. PDOUT14 PDOUT13 PDOUT12 PDOUT11 PDOUT10 PDOUT9 PDOUT8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 PDOUT7 PDOUT6 PDOUTS PDOUT4 PDOUT3 PDOUT2 PDOUT1 PDOUTO R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Legend R Read only R W Read Write n value after reset SPRU629 General Purpose I O Operation 5 13 GPIO Registers Table 5 7 Video Port Pin Data Out Register PDOUT Field Descriptions Bit fieldt symvalt Value Description 31 23 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 22 PDOUT22 VCTL3LO VCTL3HI PDOUT22 bit drives the VCTL3 pin only when the GPIO is configured as output When reading data returns the bit value in PDOUT22 does not return input from pin When writing data writes to PDOUT22 bit Pin drives low Pin drives high 21 PDOUT21 VCTL2LO VCTL2HI PDOUT21 bit drives the VCTL2 pin only when the GPIO is configured as output When reading data returns the bit value in PDOUT21 does not return input from pin When writing data writes to PDOUT21 bit Pin drives low Pin drives high 20 PDOUT20 VCTL1LO VCTL1HI PDOUT20 bit drives the VCTL1 pin only when the GPIO is configured as output When reading data returns the bit value in PDOUT20 does not return input from pin When writing data writes to PDOUT20 bit Pin drives low Pin driv
29. Y e C1Yg 17Ye 17Y 1Yg 32 3Cbap 101Cbcg 33Cbef 3Cbgh 128 ma 4 Cb g 3Cbap 33Cbeq 101Cbef 3Cbgh 128 3Crap 101Croq 33Cref 3Crgh 128 8Crap od 33Cref SCrgh Cre 3Crap 33Crod 101Cref 3Crgh 128 _Luma Y Chroma Cb Cr O sample X samples 4 4 4 Edge Pixel Replication Because four tap filters are used on the output the first and last two pixels on each line must be mirrored An example of how the filter uses the mirrored pixels for the luminance filter 2x co sited is shown in Figure 4 22 Figure 4 22 Output Edge Pixel Replication a a b C n 2 n 1 n n n 1 ER KA O eO O O X K Horizontal Image Size k n 2 rcd B nog Trailing edge Leading edge pa NG O X ki SS SKO X O replicated pixels replicated pixel t 4 Ya SALA vo Yc CR Yee ne Yn Yn 2 Yn 4 Y a f Ya s Ya Yo Yo Y f Ya Yb Yo Yd Y n f Yn4 Yn Yn Yn 1 L Ch Cb Cr Y n f Yn 2 Yn 1 Yn Yn uma roma r O Eam x samples Y n 2 f Yn 3 Yn 2 Yn 1 s Yn SPRU629 Video Display Port 4 23 Video Output Filtering Examples of luma edge and chroma edge replication for 2x interspersed to co sited output are shown in Figure 4 23 and Figure 4 24 respectively Figure 4 23 Luma Edge Replication C Qv C0 o b pue Horizontal Image Size 4 k gt a b Cc KU KG z z Trailing edge Leading edge OOOO id eee OCO O CJ replicated luma replicate
30. Y72 Y73 A Y74 A Y75 A Y76 A Y77 A YDEF YDEF YDEF A YDEF A YDEF YDEF VDOUT 19 12 co 3e cr 36 cb 37 Cr 37 KCb 38 Cr se CbDEFICDEFCDDEFICrDERbDEFCIDE 63 56 55 48 47 4039 3231 2423 1615 87 0 i Y7 Y6 Y5 Y2 Yi Y 77 Y 74 Y 73 Y FIFO Y 71 Y 70 Y 69 Y 65 63 5655 4847 4039 3231 24 23 1615 87 0 a Cb 7 Cb6 Cb 1 Cb FIFO gues Ch a3 63 56 55 48 47 4039 3231 2423 1615 87 0 4 Cr 7 Cr 6 Cr 4 Cr 3 Cr Cr FIFO Cass Cra6_ Cras Cr Little Endian Packing Line n 1 E n Line n 1 Line n KKk RRP KK le Bo By E BBD k B Bp BO ka Bis B B x PP pp Rp Line n 1 Line n RD BO ka PI ka RP Rp 63 5655 48 47 4039 3231 2423 1615 87 0 1 YO Y 1 y2 Y3 Y4 Y6 Y7 Line n 1 Y 72 Y73 Y 74 Y 75 Y 76 y FIFO L_Y 64 Y 65 Y 66 Y 67 Y 68 63 5655 4847 4 Cb 0 Cb 1 Cb 2 Cb 3 Cb4 Cb 5 Cb 6 Cb7 Line n 1 Cb FIFO Cb32 Cb33 Cha4 Ch35 Ch368 Cb37 Cb38 Line n 1 63 5655 48 47 40 39 3231 2423 4 Cr 0 Cr 1 Cr2 Cr 3 Cr4 Cr 5 Cr 6 Cr 7 Line n 1 Cr FIFO L Cr 32 Cr 33 Cr 34 Cr 35 Cr 36 Cr 37 Cr 38 Line n Big Endian Packing m n Y 70 Y 71 SPRU629 Video Capture Port 3 43 Capturing Video in BT 656 or Y C Mode 3 10 Capturing Video in BT 656 or Y C Mode In order to capture video in the BT 656 or Y C format the following steps are needed 1 Set the last pixel to be captured in VOXSTOP1 and VCx
31. define VD DISPEVT2 P P El VD IMG VSIZI E2 VD IMG VSIZI E1 8 VD IMAGE SIZ VD IMAGE SIZ El E2 vertical image size Manipulate fieldl and field2 image sizes VD IMG HSIZI VD IMG HSIZI i3 E N H Both fields should line length in double words vents to be generated for fieldl and field2 VD VDTHRLD1 8 VD VDTHRLD2 8 define DISPLAY FRAME COUNT 5 in this example ye xf EDMA parameters for display Y event that are specific to this example LE Ef define VD Y EDMA ELECN VD VDTHRLD1 2 define VD Y EDMA FR A 12 CN VD DISPEVT1 x7 Bil aL 8 E x xy Ay iU ND VDTHRLDn is in double words and 32 bit VD DISPEVT2 DISPLAY FRAME COUNT Video Port Configuration Examples lement siz ay SPRU629 Example 2 Noncontinuous Frame Display for 525 60 Format KK KK KR A A A A AA A AA AA A AAA A AA kk kk kk EF koe koe FT FT FT FT oe IT TLT T Description 8 bit BT 656 non continuous frame display Bf fa Bil Some important field descriptions x i Ki DMODE 000 8 bit BT 656 mode CON 0 Ey FRAME 1 display frame 7 DF2 0 DF1 0 8 bit non continuous frame display x SCALE 0 no scaling RESMPL 0 no resampling xy DPK X not used in 8 bit display f RS
32. disable PDT mode for dest Xu EDMA OPT LINK NO Disable linking EDMA OPT FS NO Array synchronization y m U Dog ca bol Na pol K srcAddr K EDMA CNT FRMCNT OF frameCount 1 EDMA CNT ELECNT OF elementCount DST_RMK dstAddr A_IDX_RMK EDMA_IDX_FRMIDX_OF elementCount 4 IDX ELEIDX OF 0 note 32 bit element siz no RLD in 2D and no linking E A RLD RMK EDMA RLD ELERLD OF 0 EDMA RLD LINK OF 0 E O D Q z Se idl rp UU 40 UU i tccNum tcc SPRU629 Video Port Configuration Examples A 9 Example 2 Noncontinuous Frame Display for 525 60 Format A 2 Example 2 Noncontinuous Frame Display for 525 60 Format This is an example that explains how to configure the video port for 8 bit BT 656 noncontinuous frame display for 525 60 format See ITU R BT 656 4 and video port specification Figures 4 11 4 33 4 34 and Table 4 37 for more details on 525 60 format For simplicity this example does not contain any margins that is both vertical and horizontal offsets are zero In other words both active area and image area are the same KK HK KK Ck Ck A A A A A Kk Ck A A Ck Ck Kk kk kk ke ko ke koe ke ke e e eoe e e x x f Display parameter definitions based on 525 60 format E7 KK KK Ck A A A A Ck A A A A Ck Ck Kk kk kk ke ko ke koe koe eoe eoe ee x x
33. raw video and TSI modes For video capture operation the video port may operate as two 8 10 bit chan nels of BT 656 or raw video capture or as a single channel of 8 10 bit BT 656 8 10 bit raw video 16 20 bit Y C video 16 20 bit raw video or 8 bit TSI For video display operation the video port may operate as a single channel of 8 10 bit BT 656 8 10 bit raw video 16 20 bit Y C video or 16 20 bit raw video It may also operate in a two channel 8 10 bit raw mode in which the two channels are locked to the same timing Channel B is not used during single channel operation This document describes the full feature set offered by a 20 bit video port implementation Some devices may offer a subset of features such as video capture only or video display only Also some devices may limit the video port width to 8 or 10 bits In this case modes requiring wider video port widths such as 16 bit raw 20 bit raw and Y C are not supported See the device specific datasheet for details and for I O timing information Overview 1 3 Video Port Figure 1 1 Video Port Block Diagram Internal peripheral bus Memory Timing and mapped control logic registers Lm t C FEE 7 10 10 BT 656 display ppg pipeline VDIN 19 0 Y C video T l Y C video capture pipeline Capture display 20 display pipeline VDOUT 19 0 1 20 buffer 20 Rawvideo wl 2560 bytes Rawvideo capture pipeline 20 display pip
34. so FLD1YSTRT is set to 1 FLD2YSTART is set to 263 FBITCLR and FBITSET are ignored Note that FLD2XSTRT is 360 so that the field indicator output changes halfway through the line The active horizontal output column shows the output data during the active portion of the horizontal line Note that in raw mode there is no blanking data value so the default value is output for the active portion of all nonimage window lines Video Display Port 4 41 Display Timing Examples Figure 4 36 Raw Interlaced Display Vertical Timing Example FLCOUNT IMGVOFF1 2 IMGVSIZE1 240 IMGVOFF2 3 IMGVSIZE2 240 FRMHEIGHT 525 VBITSET1 n a VBITCLR1 n a VBITSET2 n a VBITCLR2 n a ILCOUNT Field 1 Blanking 262 282 Field 2 Blanking 239 240 240 VBLNKXSTART1 720 VBLNKYSTARTI 1 VBLNKXSTOP1 720 VBLNKYSTOP1 21 VBLNKXSTART2 360 VBLNKYSTART2 263 VBLNKXSTOP2 360 VBLNKYSTOP2 283 240 VSYNCXSTART1 720 VSYNCYSTART1 4 VSYNCXSTOP1 720 VSYNCYSTOP1 7 VSYNCXSTART2 360 VSYNCYSTART2 266 VSYNCXSTOP2 360 VSYNCYSTOP2 269 Active Horizontal Output Default Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value Default Value FIFO Data FIFO Data FIFO Data FIFO Data Default Value Default Value Default Value Default Value Default Value Default Value Default Value
35. use the notation VIC_VICDIV_VICCLKDIV_symval SPRU629 VCXO Interpolated Control Port 6 9 Appendix A Video Port Configuration Examples This appendix describes how to configure the video port in different modes with the help of examples All examples in this appendix use the video port Chip Support Library CSL Topic Page A 1 Example 1 Noncontinuous Frame Capture for 525 60 Format A 10 A 2 Example 2 Noncontinuous Frame Display for 525 60 Format A 1 Example 1 A 1 Example 1 Noncontinuous Frame Capture for 525 60 Format Noncontinuous Frame Capture for 525 60 Format This is an example that explains how to configure the video port for 8 bit BT 656 noncontinuous frame capture on channel A for 525 60 format See ITU R BT 656 4 and video port specification Figures 4 11 4 33 4 34 and Table 4 37 for more details on 525 60 format KK KK Ck Ck A A A A A EK A A A Ck Kk Kk kk kk ke koe koe ke ke eoe eoe e e x x f Captu KA define VCA VBLNK1 SIZI define VCA VBLNK2 SIZI re parameter definitions based on 525 60 format KK KK Ck Ck A A A A A A A A A A A Kk kk kk kk ke koe koe koe e e eoe ee x x f EAV SAV inclusive b FI A define VCA HBLNK SIZE 138 858 720 horizontal blanking 19 20 1 v blanking for fieldl 19 283 264 v blanking for field2
36. x interrupt void VPCapChaAIsr void Uint32 vpis 0 Get video port status register value xy vpis VP RGETH vpCaptureHandle VPIS if vpis amp VP VPIS CCMPA MASK capture complete Clear frame complete bit in VCX_CTL to EJ continue capture in non continuous mode x VP FSETH vpCaptureHandle VCASTAT FRMC VP VCASTAT FRMC CLEAR Clear CCMPA to enable next frame complete aed interrupts VP FSETH vpCaptureHandle VPIS CCMPA VP VPIS CCMPA CLEAR capChaAFrameCount increment captured frame count Ef if vpis amp _VP_VPIS_COVRA_MASK overrun error capChaAOverruntt VP FSETH vpCaptureHandle VPIS COVRA VP VPIS COVRA CLEAR if vpis amp VP VPIS SERRA MASK synchronization error capChaASyncErrortt VP FSETH vpCaptureHandle VPIS SERRA VP VPIS SERRA CLFAR A 6 Video Port Configuration Examples SPRU629 Example 1 Noncontinuous Frame Capture for 525 60 Format if vpis amp VP VPIS SFDA MASK capChaAShortFieldDetect tt VP FSETH vpCaptureHandle VP VPIS LFDA VPIS short field detect if vpis amp ASK capChaALongFieldDe VP FSETH vpCaptureHandle long field detect tect VPIS Function setupVPCapChaAEDMA Input s portNumber video port number i e 0 1 or 2 Description Sets up EDMA channels for Y U V events for
37. 0 R x R x R 0 Legend R Read only n value after reset x value is determined by chip level configuration Table 2 7 Video Port Status Register VPSTAT Field Descriptions Bit fieldt symvalt Value Description 31 4 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 3 DCDIS Dual channel disable bit The default value is determined by the chip level configuration ENABLE 0 Dual channel operation is enabled DISABLE 1 Port muxing selections prevent dual channel operation 2 HIDATA High data bus half HIDATA does not affect video port operation but is provided to inform you which VDATA pins may be controlled by the video port GPIO registers HIDATA is never set unless DCDIS is also set The default value is determined by the chip level configuration NONE 0 USE 1 Indicates that another peripheral is using VDATA 9 0 and the video port channel A VDIN 9 0 or VDOUT 9 0 is muxed onto VDATA 19 10 1 0 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect t For CSL implementation use the notation VP_VPSTAT_field_symval 2 20 Video Port SPRU629 Video Port Control Registers 2 7 3 Video Port Interrupt Enable Register VPIE The video port interrupt enable register VPIE enables sources of the video port interrupt to the DSP The VPIE is shown in Figure 2 5 and described in Tab
38. 00 4h 00 8h 00 Ch are reserved for data identification purposes and consequently only 254 of the possible 256 8 bit words or 1016 of 1024 10 bit words may be used to express signal value 3 2 4 BT 656 Capture Channels SPRU629 In dual channel operation the video port can support capture of two BT 656 data streams or one BT 656 data stream and one raw data stream In the latter case the BT 656 stream may occur on either Channel A or Channel B In either case the BT 656 stream s must have embedded timing reference codes and the appropriate VCTL input must be used as a CAPEN signal If the port is configured for single channel operation capture will take place on Channel A only The unused half of the VDATA bus may be used for GPIO or for another peripheral function For single channel operation non standard BT 656 data streams without embedded timing reference codes are supported through the use of the timing control VCTL input signals Video Capture Port 3 3 BT 656 Video Capture Mode 3 2 2 BT 656 Timing Reference Codes For standard digital video there are two reference signals one at the begin ning of each video data block start of active video SAV and one at the end of each video block end of active video EAV Technically each line begins with the SAV code and ends just before the subsequent EAV code Each timing reference signal consists of a four sample sequence in the following for mat FF Ch 00 0h 00 0h XY
39. 10 9 8 PISTAT15 PISTAT14 PISTAT13 PISTAT12 PISTAT11 PISTAT10 PISTAT9 PISTATS R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 PISTAT7 PISTAT6 PISTATS PISTAT4 PISTAT3 PISTAT2 PISTAT1 PISTATO R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Legend R Read only n value after reset SPRU629 General Purpose I O Operation 5 23 GPIO Registers Table 5 12 Video Port Pin Interrupt Status Register PISTAT Field Descriptions Bit fieldt symvalt Value Description 31 23 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 22 PISTAT22 PISTAT22 bit indicates if there is a pending interrupt on the VCTL3 pin NONE 0 No pending interrupt on the VCTL3 pin VCTL3INT 1 Pending interrupt on the VCTL3 pin 21 PISTAT21 PISTAT21 bit indicates if there is a pending interrupt on the VCTL2 pin NONE 0 No pending interrupt on the VCTL2 pin VCTL2INT 1 Pending interrupt on the VCTL2 pin 20 PISTAT20 PISTAT20 bit indicates if there is a pending interrupt on the VCTL1 pin NONE 0 No pending interrupt on the VCTL1 pin VCTL1INT 1 Pending interrupt on the VCTL 1 pin 19 0 PISTAT 19 0 PISTAT 19 0 bit indicates if there is a pending interrupt on the corresponding VDATA n pin NONE 0 No pending interrupt on the VDATA n pin VDATAnINT 1 Pending interrupt on the VDATA n pin t For CSL implementation use the notation VP_PISTAT_PISTATn_symval 5 2
40. 2 x Description Configures given video port for 8 bit BT 656 non JE continuous frame display x7 E EI void bt656_8bit_ncfd int portNumber A 14 Open video port for display vpDisplayHandle VP_open portNumber if vpDisplayHandle INV test_exit FAIL Control Reg PCR VP_OPEN_RESET Enable video port functionality in VP Peripheral VP FSETH vpDisplayHandle PCR PEREN VP PCR PEREN ENABLE VP FSETH vpDisplayHandle VPIE DCMP Se VP_FSETH vpDisplayHandle this port to display mode VPCTL DISP VP_VPCTL_DISP_DISPLAY Ff Enable all interrupts es enable display complete interrupt enable display underrun interrupt VP FSETH vpDisplayHandle VPIE DUND enable video port global in VP FSETH vpDisplayHandle VPIE VIE Dd Set all other fields set frame size Sc VP VDHBLNK Ri VP VDFRMSZ RMK VD FRM HI a VP RSETH vpDisplayHandle VDFRMSZ terrupt enable VP VPIE VIE ENABLE VP VPIE DCMP ENABLE VP VPIE DUND ENABLE t horizontal blanking VP RSETH vpDisplayHandle VDHBLNK K VD HBLNK STOP VD HBLNK START se se ct t vertical blanking VP RSETH vpDisplayHandle VDVB
41. 296M operation neither VBLNK nor VSYNC would be used The FLD output is setup to transition low at the start of each frame Since the FLD2YSTART value is never reached by FLCOUNT the FLD output remains always low The ILCOUNT operation follows the description in section 4 1 2 ILCOUNT resets to 1 at the first displayed line FLCOUNT VBLNKSTOPx IMGVOFFn and stops counting at the last displayed pixel IPCOUNT IMGVSIZEx The operation during nondisplay time is not a requirement it could continue count ing until the next FLCOUNT VBLNKSTOPx IMGVOFF n point or it could reset immediately after IMGVSIZEx or when FLCOUNT is reset The active horizontal output column shows the output data during the active portion of the horizontal line It is assumed that the DVEN bit in VDCTL is set to enable the default output Video Display Port 4 45 Display Timing Examples Figure 4 38 Y C Progressive Display Vertical Timing Example co 5 3 S Ev 29 d 5 Haggorfal FLCOUNT ILCOUNT VF ir gt gt Output 750 71 3 0 Blanking Value T _ 716 10 Blanking Value 2 716 10 Blanking Value 3 716 10 Blanking Value 4L 16 10 Blanking Value 5L P 716 10 Blanking Value 6 Field 1 Blanking 716 1 0 Blanking Value X C i 1 0 Blanking Value 00 Default ValueS 00 Default Values 00 Default Values 00 FIFO Data 0 0 FIFO Data 00 FIFO Data 00 FIFO Data IN 00 Default Value 746 716 10 Blanking Value 7
42. 4 32 Display Line Boundary Example 4 need 4 33 BT 656 Interlaced Display Horizontal Timing Example aa 4 34 BT 656 Interlaced Display Vertical Timing Example 0000 cece eee eeee 4 35 Raw Interlaced Display Horizontal Timing Example 000c ee eee ee eeee 4 36 Raw Interlaced Display Vertical Timing Example 00cc cece eee eee 4 37 Y C Progressive Display Horizontal Timing Example eee eee eee 4 38 Y C Progressive Display Vertical Timing Example cece eee eee 4 39 Video Display Status Register VDSTAT ccc cece eee ee eee eee 4 40 Video Display Control Register VDCTL 000 cece eee eee 4 41 Video Display Frame Size Register VDFRMSZ cece eee eee eee 4 42 Video Display Horizontal Blanking Register VDHBLNK 22 0005 4 43 Video Display Field 1 Vertical Blanking Start Register VDVBLKS1 4 44 Video Display Field 1 Vertical Blanking End Register VDVBLKE1 4 45 Video Display Field 2 Vertical Blanking Start Register VDVBLKS2 4 46 Video Display Field 2 Vertical Blanking End Register VDVBLKE2 4 47 Video Display Field 1 Image Offset Register VDIMGOFF1 2 0 05 4 48 Video Display Field 1 Image Size Register VDIMGSZ1 2a 4 49 Video Display Field 2 Image Offset Register VDIMGOFF2
43. 9 Video Capture Channel x Event Count Register VCAEVTCT VCBEVTCT 0000s cece cece cece e eee eee eee aees 3 13 10 Video Capture Channel B Control Register VCBCTL 3 13 11 TSI Capture Control Register TSICTL 00 cece eee eee eee 3 13 12 TSI Clock Initialization LSB Register TSICLKINITL 2 3 13 13 TSI Clock Initialization MSB Register TSICLKINITM 3 13 14 TSI System Time Clock LSB Register TSISTCLKL 3 13 15 TSI System Time Clock MSB Register TSISTCLKM 3 13 16 TSI System Time Clock Compare LSB Register TSISTCMPL 3 13 17 TSI System Time Clock Compare MSB Register TSISTCMPM 3 13 18 TSI System Time Clock Compare Mask LSB Register TSISTMSKL 3 13 19 TSI System Time Clock Compare Mask MSB Register TSISTMSKM 3 13 20 TSI System Time Clock Ticks Interrupt Register TSITICKS 3 14 Video Capture FIFO Registers 0c eee teen SPRU629 Contents vii Contents 4 Video Display Pani a a man DADA BNG DRAG xmi kx Rex Rose x Rond don Discusses the video display port 4 1 Video Display Mode Selection 0 0 44 1 Image Timing 22e sero Rb xn Er E KNANG KPA PALABAN PBB QE 4 1 2 Video Display Counters 00 ccc es 4 1 3 Sync Signal Generation sesana eeann aean 4 1 4 External Sync Operation cee ees 4 1 5 Port Sync Operation
44. BLKCAP or BLKDISP operation with the difference being that BLKCAP and BLKDISP operations take effect immedi ately rather than at field completion and rely on you to reset the DMA mecha nism before they are cleared There is no separate emulation suspend mechanism on the video capture side The field and frame operation see Table 3 6 on page B 18 can be used as emulation suspend Figure 5 2 Video Port Peripheral Control Register PCR 31 16 R 0 15 3 2 1 0 R 0 R W 0 R 0 R W 1 Legend R Read only R W Read Write n value after reset 5 4 General Purpose I O Operation SPRU629 GPIO Registers Table 5 3 Video Port Peripheral Control Register PCR Field Descriptions Bit fieldt symvalt 31 3 Reserved Value Description Reserved The reserved bit location is always read as 0 A value written to this field has no effect 2 PEREN DISABLE ENABLE Peripheral enable bit Video port is disabled Port clock VCLK1 VCLK2 STCLK inputs are gated off to save power DMA access to the video port is still acknowledged but indeterminate read data is returned and write data is discarded Video port is enabled 1 SOFT STOP COMP Soft bit enable mode bit This bit is used in conjunction with FREE bit to determine state of video port clock during emulation suspend This bit has no effect if FREE 1 The current field is completed upon emulation suspend After completion no new DMA events are gene
45. Capture Channel x Field 1 Stop Register VCxSTOP1 Field Descriptions Description Bit fieldt symvalt Value BT 656 or Y C Mode Raw Data Mode TSI Mode 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 VCYSTOP OF value O FFFh Last captured line Upper 12 bits of the Upper 12 bits of data size in data the data size in samples data samples 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 VCXSTOP OF value O FFFh Last captured pixel Lower 12 bits of the Lower 12 bits of VCXSTOP 1 data size in data the data size in Must be an even samples data samples value the LSB is treated as 0 T For CSL implementation use the notation VP VCxSTOP1 field symval 3 60 Video Capture Port SPRU629 Video Capture Registers 3 13 5 Video Capture Channel x Field 2 Start Register VCASTRT2 VCBSTRT2 The captured image is a subset of the incoming image The video capture channel x field 2 start register VCASTRT2 VCBSTRT2 defines the start of the field 2 captured image This allows different window alignment or size for each field Note that the size is defined relative to incoming data before scaling VCxSTRT2 is shown in Figure 3 33 and described in Table 3 18 In BT 656 or Y C modes the horizontal pixel counter is reset by the horizontal event as
46. Counters To generate the image timing the video display module uses five counters Frame line counter FLCOUNT Frame pixel counter FPCOUNT Image line counter ILCOUNT Image pixel counter IPCOUNT Video clock counter VCCOUNT O O O O L The frame line counter FLCOUNT counts the total number of lines per frame including vertical blanking intervals The frame pixel counter FPCOUNT counts the total number of pixels per line including horizontal blanking inter vals FLCOUNT begins counting at the start of the vertical blanking interval of the first field FPCOUNT begins counting at the end of the horizontal blanking interval of each line They are reset when they reach their stop values as speci fied in the video display frame size register VDFRMSZ SPRU629 Video Display Port 4 5 Video Display Mode Selection The image line counter ILCOUNT and the image pixel counter IPCOUNT track the visible image within the field ILCOUNT begins counting at the first display image line in each field IPCOUNT begins counting at the first dis played image pixel on each line They stop counting when they reach the image height and image width as specified in the video display field n image size register VDIMGSZn The video clock counter VCCOUNT counts VCLKIN transitions to determine when to increment FPCOUNT and IPCOUNT as determined by the video display mode In Y C mode FPCOUNT and IPCOUNT increment on each VCLKIN rising edge In
47. Display Port 4 91 Video Display Registers 4 12 28 Video Display Field 2 Vertical Blanking Bit Register VDVBIT2 The video display field 2 vertical blanking bit register VDVBIT2 controls the V bit in the EAV and SAV timing control words for field 2 The VDVBIT2 is shown in Figure 4 67 and described in Table 4 33 The VBITSET2 and VBITCLR2 bits control the V bit value in the EAV and SAV timing control codes The V bit is set to 1 indicating the start of field 2 digital vertical blanking in the EAV code at the beginning of the line whenever the frame line counter FLCOUNT is equal to VBITSET2 It remains a 1 for all EAV SAV codes until the EAV at the beginning of the line on when FLCOUNT VBITCLR2 where it changes to 0 indicating the start of the field 2 digital active display The V bit operation is completely independent of the VBLNK control signal For correct interlaced operation the region defined by VBITSET2 and VBITCLR2 must not overlap the region defined by VBITSET1 and VBITCLR1 For progressive scan operation VBITSET2 and VBITCLR2 should be programmed to a value greater than FRMHEIGHT Figure 4 67 Video Display Field 2 Vertical Blanking Bit Register VDVBIT2 31 R 0 28 27 16 R W 0 12 11 0 15 R 0 R W 0 Legend R Read only R W Read Write n value after reset 4 92 Video Display Port SPRU629 Video Display Registers Table 4 33 Video Display Field 2 Vertical Blanking Bit Register V
48. H H H H Line Number F V EAV SAV Line Number F V EAV SAV 1 3 1 1 0 1 22 0 1 0 4 19 0 1 0 23 310 0 0 0 20 263 0 0 0 311 312 0 0 0 264 265 0 1 0 313 335 1 1 0 266 282 1 1 0 336 623 1 0 0 283 525 1 0 1 0 624 625 1 1 1 0 SPRU629 Video Display Port 4 11 BT 656 Video Display Mode 4 2 2 Blanking Codes The time between the EAV and SAV code on each line represents the horizontal blanking interval During this time the video port outputs digital video blanking values These values are 10 0h for luma Y samples and 80 0h for chroma Cb Cr samples These values are also output during the active line period of vertical blanking between SAV and EAV when V 1 In addition if the DVEN bit in VDCTL is cleared to O the blanking values are output during the portion of active video lines that are not a part of the displayed image 4 2 3 BT 656 Image Display 4 12 For BT 656 display mode the FIFO buffer is divided into three sections One FIFO is 2560 bytes deep and is used for the storage of Y output samples the other two FIFOs are each 1280 bytes deep and are dedicated for storage of Cb and Cr samples Each FIFO has a memory mapped location associated with it YDST CBDST and CRDST The pseudo registers are write only and are used by DMAs to fill the FIFOs with output data The video display module multiplexes the data from the three FIFOs to generate the output CbYCrY data stream If video display is enabled the video display modul
49. Oh The FFh and 00h values are reserved for use in these timing reference signals The first three bytes are a fixed preamble The fourth byte contains information defining field identification the state of field blanking and state of line blanking The assignment of these bits within the timing reference signal is listed in Table 3 2 Note that the two least signifi cant bits should be ignored even during 10 bit operation Table 3 2 BT 656 Video Timing Reference Codes 1st Byte 2nd Byte 3rd Byte 4th Byte Data Bit FFh 00h 00h XYh 9 MSB 1 0 0 1 8 1 0 0 F field t 7 1 0 0 V vertical blanking t 6 1 0 0 H horizontal blanking S 5 1 0 0 P3 protection bit 3 T 4 1 0 0 P2 protection bit 2 T 3 1 0 0 P1 protection bit 1 T 2 1 0 0 PO protection bit 0 T 1 X X X X 0 X X X X tF 0 during Field 1 F 1 during Field 2 t V 0 elsewhere V 1 during field blanking S H 0 in SAV H 1 in EAV 1l PO P1 P2 and P3 Depends on F V and H state 3 4 Video Capture Port SPRU629 BT 656 Video Capture Mode Bits PO P1 P2 and P3 have different states depending on the state of bits F V and H as shown in Table 3 3 Table 3 3 BT 656 Protection Bits Line Information Bits Protection Bits F V H P3 P2 P1 PO 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 0 1 0 0 0 1 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 1 The protection bits allow the port to implement a DEDSEC double error detec tion single error c
50. Raw 11 0 SE Raw 4 0 SE Raw 5 0 SE Raw 6 0 SE Raw 7 Y FIFO 0 SE Raw 0 0 SE Raw 1 0 SE Raw 2 0 SE Raw 3 Big Endian Packing 3 34 Video Capture Port SPRU629 Raw Data Capture Mode The 10 bit dense raw data mode stores all data into a single FIFO Three sam ples are packed into each word with zero extension as shown in Figure 3 19 Figure 3 19 10 Bit Dense Raw Data FIFO Packing VDOUT 9 0 63 61 5251 4241 3231 29 2019 109 1 00 Raw 17 Raw 16 Raw 15 00d Raw14 Raw 13 Raw 12 00 Raw 11 Raw 10 Raw 9 00 Raw 8 Raw 7 Raw 6 Y FIFO og Raw 5 Raw4 Raw 3 00 Raw 2 Raw 1 Raw 0 Little Endian Unpacking 63 61 5251 4244 3231 29 2019 109 i 00 Raw 12 Raw 13 Raw 14 00 Raw 15 Raw 16 Raw 17 00 Raw 6 Raw 7 Raw 8 00 Raw 9 Raw 10 Raw 11 Y FIFO 00 Raw 0 Raw 1 Raw 2 00 Raw 3 Raw 4 Raw 5 The 16 bit raw data mode stores all data into a single FIFO Two samples are Big Endian Unpacking packed into each word as shown in Figure 3 20 Figure 3 20 16 Bit Raw Data FIFO Packing VDIN 19 12 VDIN 9 2 63 Raw 11 Raw 10 Raw 9 Raw 8 4 Raw 7 Raw 6 Raw 5 Raw 4 Raw FIFO Raw 3 Raw 2 Raw 1 Raw 0 Little Endian Packing 63 4847 3231 1615 Raw 8 Raw 9 Raw 10 Raw 11 nG Raw 4 Raw 5 Raw 6 Raw 7 Raw FIFO Raw 0 Raw 1 Raw 2 Raw 3 Big Endian Packing SPRU629 Video Capture Port 3 35 Raw Data Captu
51. SAV codes for field 2 is controlled by the VDVBIT2 register Video Display Port 4 65 Video Display Registers Figure 4 45 Video Display Field 2 Vertical Blanking Start Register VDVBLKS2 31 28 27 16 R 0 R W 0 15 12 11 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 4 12 Video Display Field 2 Vertical Blanking Start Register VDVBLKS2 Field Descriptions Description Bit fieldt symvalt Value BT 656 and Y C Mode Raw Data Mode 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 VBLNKYSTART2 OF value O FFFh Specifies the line in Specifies the line in FLCOUNT where FLCOUNT where vertical VBLNK active edge blanking begins VBLNK occurs for field 2 Does active edge for field 2 not affect EAV SAV V bit operation 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 VBLNKXSTART2 OF value O FFFh Specifies the pixel in Specifies the pixel in FPCOUNT where FPCOUNT where VBLNK active edge vertical blanking begins occurs for field 2 VBLNK active edge for field 2 t For CSL implementation use the notation VP VDVBLKS2 field symval 4 66 Video Display Port SPRU629 Video Display Registers 4 12 8 Video Display Field 2 Vertical Blanking End Register VDVBLKE2 The video display field 2 vertical blanking end register V
52. Specifies the pixel in FPCOUNT where FPCOUNT where VBLNK active edge vertical blanking begins occurs for field 1 VBLNK active edge for field 1 t For CSL implementation use the notation VP VDVBLKS1 field symval SPRU629 Video Display Port 4 63 Video Display Registers 4 12 6 Video Display Field 1 Vertical Blanking End Register VDVBLKE1 The video display field 1 vertical blanking end register VDVBLKE1 controls the end of vertical blanking in field 1 The VDVBLKE1 is shown in Figure 4 44 and described in Table 4 11 In raw data mode VBLNK is deasserted whenever the frame line counter FLCOUNT is equal to VBLNKYSTOP1 and the frame pixel counter FPCOUNT is equal to VBLNKXSTOP this is shown in Figure 4 6 page In BT 656 and Y C mode VBLNK is deasserted whenever FLCOUNT VBLNKYSTOP1 and FPCOUNT VBLNKXSTOP1 This VBLNK output control is completely independent of the timing control codes The V bit in the EAV SAV codes for field 1 is controlled by the VDVBIT1 register Figure 4 44 Video Display Field 1 Vertical Blanking End Register VDVBLKE 1 31 R 0 28 27 16 VBINKYSTOP R W 0 12 11 0 15 R 0 R W 0 Legend R Read only R W Read Write n value after reset 4 64 Video Display Port SPRU629 Video Display Registers Table 4 11 Video Display Field 1 Vertical Blanking End Register VDVBLKE1 Field Descriptions Description Bit fieldt symvalt Value BT 656 and Y C Mode Raw Da
53. The VPCTL is shown in Figure 2 3 and described in Table 2 5 Not all combinations of the port control bits are unique The control bit encoding is shown in Table 2 6 Additional mode options are selected using the video capture channel A control register VCACTL and video display control register VDCTL Figure 2 3 Video Port Control Register VPCTL 31 16 R 0 15 14 13 8 R WS 0 R WC 1 R 0 7 6 5 4 3 2 1 0 VCLK2P VCT3P VCT2P VCT1P DISP DCHNL R W 0 R W 0 R W 0 R W 0 R 0 R W 0 R W 0 R W 0 Legend R Read only R W Read Write WC Write a 1 to clear WS Write 1 to set write of 0 has no effect n value after reset Table 2 5 Video Port Control Register VPCTL Field Descriptions Bit fieldt symvalt Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 VPRST Video port software reset enable bit VPRST is set by writing a 1 Writing O has no effect NO 0 RESET 1 Flush all FIFOs and set all port registers to their initial values VCLK1 and VCLK2 are configured as inputs and all VDATA and VCTL pins are placed in high impedance Auto cleared after reset is complete t For CSL implementation use the notation VP_VPCTL_field_symval SPRU629 Video Port 2 17 Video Port Control Registers Table 2 5 Video Port Control Register VPCTL Field Descriptions Continued Bit field symvalt Value Description 1
54. Two samples are packed into each word with zero or sign extension as shown in Figure 3 6 Figure 3 6 10 Bit Y C FIFO Packing VDINIB o VDIN 19 10 63 58 57 4847 4241 3231 26 25 1615 109 0 0 SE Y 15 0 SE Y 14 0 SE Y 13 0 SE Y 12 0 SE Y 11 0 SE Y 10 0 SE Y9 0 SE Y8 0 SE Y7 0 SE Y6 0 SE Y4 0 SE Y4 Y FIFO 0 SE Y3 Y2 0 SE Y1 0 SE YO 63 58 57 48 47 4241 3231 26 25 1615 109 0 0 SE Cb 7 0 SE Cb 6 0 SE Cb 5 0 SE Cb4 0 SE Cb 3 0 SE Cb2 0 SE Cb 1 0 SE Cb 0 Cb FIFO 63 58 57 48 47 4241 3231 26 25 1615 109 0 0 SE Cr7 0 SE Cr6 0 SE Cr 5 0 SE Cr4 0 SE Cr3 0 SE Cr2 0 SE Cr 1 0 SE Cr 0 Cr FIFO Little Endian Packing 63 58 57 48 47 4241 3231 26 25 16 15 10 9 0 0 SE Y 12 0 SE Y 13 0 SE Y 14 0 SE Y 15 0 SE Y8 0 SE Y9 0 SE Y 10 0 SE Y 11 0 SE Y4 0 SE Y4 0 SE Y6 0 SE Y7 YFIFO 9 SE YO 0 SE Y 1 0 SE Y2 0 SE YS 63 58 57 48 47 4241 3231 26 25 16 15 10 9 0 0 SE Cb4 0 SE Cb 5 0 SE Cb 6 0 SE Cb7 0 SE Cb 0 0 SE Cb 1 0 SE Cb2 0 SE Cb 3 Cb FIFO 63 58 57 48 47 4241 3231 26 25 16 15 10 9 0 0 SE Cr4 0 SE Cr5 0 SE Cr6 0 SE Cr7 0 SE Cro 0 SE Cr 1 0 SE Cr2 0 SE Cr 3 Cr FIFO Big Endian Packing SPRU629 Video Capture Port 3 15 Y C Video Capture Mode The 10 bit Y C dense mode uses three FIFOs for color separation Three sam ples are packed into each word with zero extens
55. VPIS to be set This generates a DSP interrupt if the CCMPx bit is enabled in VPIE 10 If continuous capture is enabled the video port begins capturing again at the start of the next selected field or frame If noncontinuous field 1 and field 2 or frame capture is enabled the next field or frame is captured during which the DSP must clear the appropriate completion status bit or further capture is disabled If single frame capture is enabled capture is disabled until the DSP clears the FRMC bit 3 10 1 Handling FIFO Overrun in BT 656 or Y C Mode SPRU629 In case of a FIFO overrun the COVRxbit is setin VPIS This condition initiates an interrupt to the DSP if the overrun interrupt is enabled setting the COVR bit in VPIE enables overrun interrupt The overrun interrupt routine should set the BLKCAP bit in VCxCTL and it should reconfigure DMA channel settings The DMA channel must be reconfi gured for capture of the next frame since the current frame transfer failed Set ting the BLKCAP bit flushes the capture FIFO and blocks DMA events for the channel As long as the BLKCAP bit is set the video capture channel ignores the incoming data with exception of SAV and EAV codes but the internal counters continue counting The BLKCAP bit should be cleared to 0 in order to continue capture Clearing the BLKCAP bit takes effect in the subsequent video field DMA events are still going to be blocked in the video field in which the BLKCAP bit
56. VSYNC are shown active high 4 6 Video Display Port SPRU629 Video Display Mode Selection Note that the signals can transition at any place along the video line specified by the XSTART and XSTOP bits of the appropriate registers In this case VBLNK starts at horizontal count VBLNKXSTART2 429 on scan line VBLNKYSTART2 263 565 60 operation Figure 4 6 Vertical Blanking Sync and Even Odd Frame Signal Timing a One Frame gt One Line Lo of N Seo Galo tO tB o D N D c9 d Qi Ql cu co rto FLCOUNT ba ka QI QI QE QI QI QI au Ni Q A ai to tO VBLNK us REA m T A f A FLCOUNT VBLNKYSTOP1 FLCOUNT VBLNKYSTART2 FLCOUNT VBLNKYSTOP2 FLCOUNT VBLNKYSTART1 FPCOUNT VBLNKXSTOP1 FPCOUNT VBLNKXSTART2 FPCOUNT VBLNKXSTOP2 FPCOUNT VBLNKXSTART1 VSYNC 1 wa WP 7 A A FLCOUNT VSYNCYSTOP1 FLCOUNT VSYNCYSTART2 FLCOUNT VSYNCYSTOP2 FLCOUNT VSYNCYSTART1 FPCOUNT VSYNCXSTOP1 FPCOUNT VSYNCXSTART2 FPCOUNT VSYNCXSTOP2 FPCOUNT VSYNCXSTART1 HED EP AN WI Field 2 Lr FLCOUNT FLD2YSTART FLCOUNT FLD1YSTART FPCOUNT FLD2XSTART FPCOUNT FLD1XSTART 4 1 3 Sync Signal Generation SPRU629 The video display module must generate a number of control signals for both internal and external use As seen in section 4 1 2 the HSYNC HBLNK VSYNC VBLNK and FLD signals a
57. When the video port is in reset is not enabled PEREN bit cleared halted VPHALT bit is set or the active mode is not enabled VCEN or VDEN bit is cleared then the port will false acknowledge all DMA accesses to prevent bus lockup The video port DMA event generation logic is very tightly coupled to the DMA interface accesses An incorrectly programmed DMA size causes the DMA and FIFO to become misaligned causing aberrations in the captured or displayed data and likely resulting in an eventual FIFO overflow or underflow In the same manner if another system DMA incorrectly addresses the video port during active capture or display the video port has no way of determining that this is an errant DMA because all it monitors is a DMA access so it must perform the FIFO read or write Such an errant DMA eventually causes the FIFO to be overread or overwritten Video Port 2 11 Clocks Video Port Functionality Subsets 2 4 Clocks The video port has three external clock inputs as shown in Table 2 1 No synchronization is required between the clocks sourced by the external pins VCLK1 and VCLK2 clock frequencies should be less than the DMA interface clock On 64x devices the DMA interface clock is typically 1 2 the CPU clock so this allows VCLK1 and VCLK2 to run at full frequency unless the 64x CPU is running atless than 220 MHz STCLK should be less than the peripheral bus clock Table 2 1 Video Port Functional Clocks Clock Source F
58. Y samples x Configure Cr EDMA channel to move data from CrSRCA kj FIFO to Cr data buffer capChaACrSpace 7 configVPCapEDMAChannel amp hEdmaVPCapChaACr VEvent amp edmaCapChaACrTccNum vpCaptureHandle crsrcaAddr Uint32 capChaACrSpace VCA Y EDMA FRMCNT VCA Y EDMA ELECNT 2 1 2 of Y samples Enable three EDMA channels Xy EDMA enableChannel hEdmaVPCapChaAY EDMA enableChannel hEdmaVPCapChaACb EDMA enableChannel hEdmaVPCapChaACr hes Ey Function configVPCapEDMAChannel pe A Input s edmaHandle pointer to EDMA handle m eventId EDMA eventId kf px tccNum pointer to transfer complete number srcAddr Source address for EDMA transfer Ky y dstAddr destination address for EDMA transfer frameCount frame count j elementCount element count 32 bit element size 5 Kok Output s edmaHandle edma Handle of the given event ty IX tccNum transfer complete code for the given event Ki JE y Description Configures the given VP capture EDMA channel af The source address update is fixed address mod 7 pa because the captured data is read from the FIFO ki In this example the destination address mode is ay i auto increment But in real time applications there is lot of flexibility in the way capture EY yE buffers can be mana
59. and Cr buffers with separate write pointers and read registers YSRCA CBSRCA and CRSRCA Figure 1 4 shows how Y data is received on the VDIN 9 0 half of the bus and Cb Cr data is received on the VDIN 19 10 half of the bus and demultiplexed into the Cb and Cr buffers Figure 1 4 Y C Video Capture FIFO Configuration Capture FIFO VDIN 9 0 Y Buffer 2560 bytes CBSRCA Cb Buffer 1280 bytes VDIN 19 10 CRSRCA Cr Buffer 1280 bytes 1 8 Overview SPRU629 Video Port FIFO For 16 20 bit raw video the FIFO is configured as a single buffer as shown in Figure 1 5 The FIFO receives 16 20 bit data from the VDIN 19 0 bus The FIFO has a single write pointer and read register YSRCA Figure 1 5 16 20 Bit Raw Video Capture FIFO Configuration Capture FIFO VDIN 19 0 Data Buffer 5120 bytes 1 2 3 Video Display FIFO Configurations During video display operation the video port FIFO has one of five configura tions depending on the display mode For BT 656 operation a single output is provided on channel A as shown in Figure 1 6 with data output on VDOUT 9 0 The channels FIFO is split into Y Cb and Cr buffers with separate read pointers and write registers YDSTA CBDST and CRDST Figure 1 6 BT 656 Video Display FIFO Configuration Display FIFO Y Buffer 2560 bytes VDOUT 9 0 Cb Buffer 1280 bytes Cr Buffer 1280 bytes SPRU629 O
60. be cleared by the DSP or a DCNA interrupt occurs The DSP has the en tire field 2 time to clear F1D before next field 1 begins Can also be used for single progressive frame display internal timing codes only The DSP has vertical blanking time to clear F1D before next frame begins Noncontinuous field 2 display Display only field 2 F2D is set after field 2 display and causes DCMPx to be set The F2D bit must be cleared by the DSP or a DCNA interrupt occurs The DSP has the en tire field 1 time to clear F2D before next field 2 begins Noncontinuous field 1 and field 2 display Display both fields F1D is set after field 1 display and causes DCMPx to be set The F1D bit must be cleared by the DSP before the next field 1 display or a DONA interrupt occurs The DSP has the entire field 2 time to clear F1D before next field 1 begins F2D is set after field 2 display and also causes DCMPx to be set The F2D bit must be cleared by the DSP before the next field 2 display or a DCNA interrupt occurs The DSP has the entire field 1 time to clear F2D before next field 2 begins Noncontinuous frame display Display both fields FRMD is set after field 2 display and causes DCMPx to be set A DCNA interrupt occurs upon completion of the next frame unless the FRMD bit is cleared The DSP has the entire next frame time to clear FRMD Noncontinuous progressive frame display Display field 1 FRMD is set after field 1 display and causes DCMPx
61. blanking For field 2 VBLNK and VSYNC edges occur during the middle of the active horizontal line so their XSTART XSTOP values are set to 360 Note that from an analog standpoint vertical blanking begins a half line before digital blanking so that VBLNKYSTART2 is set to 263 with VBLNKXSTART2 set to 360 while VBITSET2 is programmed to 264 For true BT 656 operation neither VBLNK nor VSYNC would be used The FLD output is setup to transition at the start of each analog field start of vertical blanking Since EAV F transitions on lines 4 and 266 this requires programming FBITCLR to 4 FBITSET to 266 FLD1YSTART to 1 and FLD2YSTART to 263 Note that FLD2XSTRT is 360 so that the field indicator output changes halfway through the line The ILCOUNT operation follows the description in section 4 1 2 ILCOUNT resets to 1 at the first displayed line FLCOUNT VBLNKSTOPx IMGVOFF and stops counting at the last displayed pixel IPCOUNT IMGVSIZEx The operation during nondisplay time is not a requirement it could continue count ing until the next FLCOUNT VBLNKSTOPx IMGVOFFx point or it could reset immediately after IMGVSIZEx or when FLCOUNT is reset The active horizontal output column shows the output data during the active portion of the horizontal line It is assumed that the DVEN bit in VDCTL is set to enable the default output Video Display Port 4 37 Display Timing Examples Figure 4 34 BT 656 Interlaced Display Vertica
62. changing register bits the software should disable the system time clock interrupt clear the STEN bit in TSICTL prior to writing to TSISTMSKM Figure 3 47 TSI System Time Clock Compare Mask MSB Register TSISTMSKM 31 1 0 ATOM R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 3 32 TSI System Time Clock Compare Mask MSB Register TSISTMSKM Field Descriptions Description BT 656 Y C Mode Bit Field symvalt Value or Raw Data Mode TSI Mode 31 1 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 ATCM OF value 0 1 Not used Contains the MSB of the absolute time compare mask t For CSL implementation use the notation VP_TSISTMSKM_ATCM_symval SPRU629 Video Capture Port 3 81 Video Capture Registers 3 13 20 TSI System Time Clock Ticks Interrupt Register TSITICKS The transport stream interface system time clock ticks interrupt register TSITICKS is used to generate an interrupt after a certain number of ticks of the 27 MHz system time clock When the TICKCT value is set to X and the TCKEN bit in TSICTL is set the TICK bit in VPIS is set every X 1 STCLK cycles Note that the tick interrupt counter and comparison logic function are separate from the PCR logic and always count STCLK cycles regardless ofthe value of the CTMODE bit in TSICTL TSITICKS is shown in Figure 3 48 and described in Table 3 33 A write to TSITICKS
63. channel A capture void setupVPCapChaAEDMA Int32 portNumber Int32 YEvent get channelA Y U UEvent VEvent switch portNumber V EDMA event numbers case VP DEVO YEvent EDMA CHA VPOEVTYA UEvent EDMA CHA VPOEVTUA VEvent EDMA CHA VPOEVIVA break case VP DEV1 YEvent EDMA CHA VPIEVTYA UEvent EDMA CHA VPIEVTUA VEvent EDMA_CHA_VP1EVTVA break case VP_DEV2 YEvent EDMA CHA VP2EVTYA UEvent EDMA CHA VP2EVTUA VEvent EDMA CHA VP2EVIVA break Configure Y FIFO to Y data buffer EDMA channel to move data from YSRCA capChaAYSpace configVPCapEDMAChannel amp hEdmaVPCapChaAY YEvent amp edmaCapChaAYTccNum vpCaptureHandle ysrcaAddr Uint32 capChaAYSpace VCA Y EDMA FRMCNT VCA Y EDMA ELECNT SPRU629 Video Port Configuration Examples SFDA VP VPIS SFDA CLEAR LFDA VP VPIS LFDA CLEAR A ty 87 ud n Ey x E EY E A 7 Example 1 Noncontinuous Frame Capture for 525 60 Format Configure Cb EDMA channel to move data from CbSRCA KA FIFO to Cb data buffer capChaACbSpace x configVPCapEDMAChannel amp hEdmaVPCapChaACb UEvent amp edmaCapChaACbTccNum vpCaptureHandle cbsrcaAddr Uint32 capChaACbSpace VCA Y EDMA FRMCNT VCA Y EDMA ELECNT 2 1 2 of
64. cleared to a logic low without affecting other I O pins controlled by the same port NONE 0 No effect VDATAnCLR 1 Clears PDOUT n VDATA n bit to 0 T For CSL implementation use the notation VP_PDCLR_PDCLRn_symval 5 18 General Purpose I O Operation SPRU629 GPIO Registers 5 1 9 Video Port Pin Interrupt Enable Register PIEN The video port pin interrupt enable register PIEN is shown in Figure 5 9 and described in Table 5 10 The GPIOs can be used to generate DSP interrupts or DMA events The PIEN selects which pins may be used to generate an interrupt Only pins whose corresponding bits in PIEN are set may cause their corresponding PISTAT bit to be set Interrupts are enabled on a GPIO pin when the corresponding bit in PIEN is set the pin is enabled for GPIO in PFUNC andthe pin is configured as an input in PDIR Figure 5 9 Video Port Pin Interrupt Enable Register PIEN 31 24 R 0 23 22 21 20 19 18 17 16 PIEN22 PIEN21 PIEN20 PIEN19 PIEN18 PIEN17 PIEN16 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 PIEN15 PIEN14 PIEN13 PIEN12 PIEN11 PIEN10 PIEN9 PIEN8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 PIEN7 PIEN6 PIEN5 PIEN4 PIEN3 PIEN2 PIEN1 PIENO R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Legend R Read only R W Read Write n value after reset SPRU629 General Purpose I O Operation 5 19 GPIO Registers Table 5 10 Video Port Pin In
65. copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of that third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2003 Texas Instruments Incorporated Preface Read This First About This Manual This document describes the video port and VCXO i
66. current programmable register values The F1C F2C and FRMC status bits in VCBSTAT are not updated Field or frame complete interrupts and vertical interrupts are also not generated Clearing BLKCAP does not enable DMA events during the field where the bit is cleared Whenever BLKCAP is set and then cleared the software needs to clear the field and frame status bits F1C F2C and FRMC as part of the BLKCAP clear operation CLEAR Enables DMA events in the video frame that follows the video frame where the bit is cleared The capture logic must sync to the start of the next frame after BLKCAP is cleared BLOCK Blocks DMA events and flushes the capture channel FIFOs 29 21 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 20 FINV Detected field invert bit FIELD1 Detected 0 is field 1 Not used Not used FIELD2 Detected 0 is field 2 Not used Not used 19 18 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 17 VRST VCOUNT reset method bit V1EAV Start of vertical blank Not used Not used St V 1 EAV or VCTL2 active edge VOEAV End of vertical blank Not used Not used 1st V 0 EAV or VCTL2 inactive edge t For CSL implementation use the notation VP VCBCTL field symval t For complete encoding of these bits see Table 3 6 Table 3 11 and Table 3 12 SPRU629 Video Capture Port
67. cycles have elapsed 3 8 5 TSI Data Capture Notification Since TSI mode captures only data packets there is no need for field control Some flexibility in capture and DSP notification is still provided in order to accommodate various DMA structures and processing flows Each TSI data packet is treated similar to a progressive scan video frame The TSI mode uses the CON and FRAME bits of VCACTL in a slightly different manner as listed in Table 3 12 The CON bit controls the capture of multiple packets When CON 1 continuous capture is enabled the video port captures incoming data packets assuming the VCEN bit is set without the need for DSP interaction It relies on a DMA structure with circular buffering capability to service the capture FIFO When CON 0 continuous capture is disabled the video port sets the frame capture complete bit FRMC in VCASTAT upon the capture of each packet Once the capture complete bit is set at most one more frame can be received before capture operation is halted as determined by the FRAME bit state This prevents subsequent data from overwriting previous packets until the DSP has a chance to update DMA pointers or process those packets Table 3 12 TSI Capture Mode Operation VCACTL Bit CON FRAME CF2 CF1 Operation 0 0 X X Noncontinuous packet capture FRMC is set after packet capture and causes CCMPA to be set Capture will halt upon completion of the next data packet unless the FRMC bit is c
68. eee 4 8 Display Line Boundary Conditions 00 00 cee eee eee ees 49 Display Timing Examples sssssssssse ett eee ees 4 9 1 Interlaced BT 656 Timing Example 00 0c cee eee eee eee 4 9 2 Interlaced Raw Display Example 0 ccc eee eee eee eee 4 9 3 Y C Progressive Display Example 0 0c cece eee eens 4 10 Displaying Video in BT 656 or Y C Mode aaa 4 11 Displaying Video in Raw Data Mode ee 4 11 1 Handling Underrun Condition of the Display FIFO 2 4 12 Video Display Registers sssseesseeessses e 4 12 1 Video Display Status Register VDSTAT 000 cee eee eee eee 4 12 2 Video Display Control Register VDCTL 000 cece eens 4 12 3 Video Display Frame Size Register VDFRMSZ 0000005 4 12 4 Video Display Horizontal Blanking Register VDHBLNK 4 12 5 Video Display Field 1 Vertical Blanking Start Register VDVBLKS1 viii SPRU629 Contents 4 12 6 Video Display Field 1 Vertical Blanking End Register VDVBLKE1 4 12 7 Video Display Field 2 Vertical Blanking Start Register VDVBLKS2 4 12 8 Video Display Field 2 Vertical Blanking End Register VDVBLKE2 4 12 9 Video Display Field 1 Image Offset Register VDIMGOFF1 4 12 10 Video Display Field 1 Image Size Register VDIMGSZ1 4 12 11 Video Display Field 2 Image Offset Register VDIMGOFF2
69. field symvalt Value BT 656 or Y C Mode TSI Mode 31 RSTCH Reset channel bit Write 1 to reset the bit a write of O has no effect NONE 0 No effect RESET 1 Resets the channel by blocking further DMA event generation and flushing the FIFO upon completion of any pending DMAs Also clears the VCEN bit All channel registers are set to their initial values RSTCH is autocleared after channel reset is complete t For CSL implementation use the notation VP VCACTL field symval tFor complete encoding of these bits see Table 3 6 Table 3 11 and Table 3 12 SPRU629 Video Capture Port 3 5 Co Video Capture Registers Table 3 15 Video Capture Channel A Control Register VCACTL Field Descriptions Continued Bit 8H fieldt symvalt 30 BLKCAP Description Value BT 656 or Y C Mode Raw Data Mode TSI Mode Block capture events bit BLKCAP functions as a capture FIFO reset without affecting the current programmable register values The F1C F2C and FRMC status bits in VCASTAT are not updated Field or frame complete interrupts and vertical interrupts are also not generated Clearing BLKCAP does not enable DMA events during the field where the bit is cleared Whenever BLKCAP is set and then cleared the software needs to clear the field and frame status bits F1C F2C and FRMC as part of the BLKCAP clear operation CLEAR Enables DMA events in the video frame that follows the video frame where the bit is cleared
70. field is detected when VCOUNT VCYSTOPn 1 Along field is only detected when the VRST bit in VCXCTL is cleared to 0 when VRST 1 a long field is always detected Long field detection cannot be used if the capture window is a vertical subset of the field that crops lines at the bottom Such a window would always result in along field detection If VCTL2 is used for vertical sync then the VCTL2 sig nal must represent VBLNK vertical blank for proper long field detect If Video Capture Port 3 25 Video Input Filtering VCTL2 is a VSYNC vertical sync input then a long field is always detected Even if VCYSTOPn is set to the last active line VCOUNT usually increments past VCYSTOPn 1 while it counts the vertical front porch lines that occur prior to VSYNC active 3 5 Video Input Filtering 3 5 1 Table 3 10 CMODE x00 x00 x00 x00 x01 x10 x11 3 26 The video input filter performs simple hardware scaling and resampling on incoming 8 bit BT 656 or 8 bit Y C data Filtering hardware is always disabled during 10 bit or raw data capture modes For proper filter operation the channel s EXC bit in VCxCTL must be cleared to 0 embedded timing refer ence codes used and the CAPEN input must not go inactive during the active video window Input Filter Modes VCxCTL Bit RESMPL SCALE Filter Operation 0 0 1 The input filter has four modes of operation no filtering scaling chrominance resampling and scali
71. in this example VD VINT se VP RS Fl ctf threshold value for DMA events TH vpDisplayHandle VDTHRLD VP VDTHRLD RMK VD VDTHRLD2 VP VDTHRLD INCPIX DEFAULT VD VDTHRLD1 x7 NG TH vpDisplayHandle VDCTL DMODE VP VDCTL DMODE BT656B pDisplayHandle VDCTL CON VP VDCTL CON DISABLE pDisplayHandle VDCTL FRAME VP VDCTL FRAME FRMDIS pDisplayHandle VDCTL DF2 VP VDCTL DF2 NONE Set display control reg VD_CTL set display mode DMODE to 8 bit BT 656 VP_FSE set non continuous frame display VP_FSETH v VP_FSETH v VP_FSETH v VP_FSETH v pDisplayHandle VDCTL DF1 VP_VDCTL_DF1_NO let control outputs VCTL1S VCTL2S VCTL3S HXS VXS FXS be their defaults i e VCTLxS are output control signals no scaling and no resampling in this example no need to bother about 10 bit unpacking mode DPK bit in this 8 bit example Set up Y Cb and Cr EDMA channels setupVPDispEDMA portNumber Enable video port interrupts IRQ enable vpDisplayHandle eventId clear VPHLT in VP CTL to make video port function VP FSETH vpDisplayHandle VPCTL VPHLT VP VPCTL VPHLT CLEAR Video Port Configuration Examples RY Ef x xy EJ Ky x Ky x Ky sf x a Ky tj SPRU629 Example 2 Noncontinuous Frame Display for 52
72. is active Data is captured at the rate of the sender s clock without any interpretation or start stop of capture based on the data values To ensure initial capture synchronization to the beginning of a frame an optional setup synchronization enable SSE bit is provided in VCXSTRT1 If the SSE bit is set then when the VCEN bit is set to 1 the video port will not start capturing data until after detecting two vertical blanking intervals If the SSE bit is cleared to 0 capture begins immediately when the VCEN bit is set The incoming digital video capture data is stored in the FIFO which is 2560 bytes in dual channel operation or 5120 bytes deep in single channel operation The memory mapped location YSRCx is associated with the Y buffer The YSROx location is a read only register and is used to access video data samples stored in the buffer The captured data set size is set by VCxSTOPn The VCXSTOP and VCYSTOP bits set the 24 bits of data set size VCXSTOP sets the lower 12 bits and VCYSTOP sets the upper 12 bits Capture is complete and the appropriate F1C F2C or FRMC bit is set when the captured data size reaches the combined VCYSTOP and VCXSTOP value The video port generates a YEVT after the specified number of new samples has been captured in the buffer The number of samples required to generate YEVTx is programmable and is set in the VCTHRLDn bits of VCXTHRLD On every YEVT the DMA should move data from the buffer to the DSP
73. is set in the VCTHRLD1 bits of VCATHRLD VCTHRLD1 should be set to the packet size plus 8 bytes of timestamp On every YEVT the DMA should move data from the buffer to the DSP memory When moving data from the buffer to the DSP memory the DMA should use the memory address of the YSRCA location as a source address 3 9 Capture Line Boundary Conditions In order to simplify DMA transfers FIFO doublewords must not contain data from more than one capture line This means that a FIFO write must be performed whenever 8 bytes have been received or when the line complete condition HCOUNT VCXSTOP occurs Thus every captured line begins on a doubleword boundary and non doubleword length lines are padded atthe end An example is shown in Figure 3 28 3 42 Video Capture Port SPRU629 Capture Line Boundary Conditions In Figure 3 28 8 bit Y C mode the line length is not a doubleword When the condition HCOUNT VCXSTOP occurs the FIFO location is written even though 8 bytes have not been received The next capture line then begins in the next FIFO location at byte 0 This operation extends to all capture modes In the case of TSI and raw data modes there are no lines In these modes a final write at the end of the packet must be performed when the packet data count equals the 24 bit combined value of VOXCOUNT and VCYCOUNT Figure 3 28 Capture Line Boundary Example IPCOUNT IMGHSIZE 78 vetkout U LILI U LILI LL LU LU US ud VDOUT 9 2
74. memory When moving data from the buffer to the DSP memory the DMA should use the YSRCx location as a source address 3 7 1 Raw Data Capture Notification Raw data mode captures a single data packet of information using only CAPEN for control Field information is available only for channel A operation using the FID input on VCTL3 Ifthe RDFE bitin VCACTL is set then the video port samples the FID input at the start of each data block when DCOUNT 0 and CAPENA is active to determine the current field In this case the CON FRAME CF1 and CF2 bits in VOxCTL are used in a manner identical to BT 656 mode see section 3 4 1 For channel B operation or when the RDFE bit in VCACTL is not set no field information is available Some flexibility in capture and DSP notification is still provided in order to accommodate various DMA structures and processing flows Each raw data packet is treated similar to a progressive scan video frame The raw data mode uses the CON and FRAME bits of VCXCTL in a slightly different manner as listed in Table 3 11 3 32 Video Capture Port SPRU629 Raw Data Capture Mode Table 3 11 Raw Data Mode Capture Operation VCxCTL Bit CON FRAME CF2 CF1 Operation 0 0 x X Noncontinuous frame capture FRMC is set after data block capture and causes CCMPx to be set Capture will halt upon completion of the next frame unless the FRMC bit is cleared DSP has the entire next frame time to clear FRMC 0 1 X X Single f
75. number is the ending value of the frame line counter FLCOUNT For BT 656 operation the FRMHIGHT is set to 525 525 60 operation or 625 625 50 operation 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 FRMWIDTH OF value O FFFh Defines the total number of pixels per line including blanking The number is the frame pixel counter FPCOUNT ending value 1 For BT 656 operation the FRMWIDTH is typically 858 or 864 T For CSL implementation use the notation VP_VDFRMSZ_field_symval 4 60 Video Display Port SPRU629 Video Display Registers 4 12 4 Video Display Horizontal Blanking Register VDHBLNK The video display horizontal blanking register VDHBLNK controls the display horizontal blanking The VDHBLNK is shown in Figure 4 42 and described in Table 4 9 Every time the frame pixel counter FPCOUNT is equal to HBLNKSTART HBLNK is asserted HBLNKSTART also determines where the EAV code is inserted in the BT 656 and Y C output Every time FPCOUNT HBLNKSTOP the HBLNK signal is deasserted this is shown in Figure 4 5 page In BT 656 and Y C modes HBLNKSTOP determines the SAV code insertion point and HBLNK deassertion point The HBLNK inactive edge may optionally be delayed by 4 pixel clocks using the HBDLA bit Figure 4 42 Video Display Horizontal Blanking Register VDHBLNK 31 28 27 16 R 0 R W 0 15 14 12 11 0 R W 0 R 0 R
76. output 10x for Y C output Od Set desired field frame operation CON FRAME DF1 DF2 bits O Select control outputs VCTL1S VCTL2S VCTL3S bits or external sync inputs HXS VXS FXS bits Enable scaling SCALE and RESMPL bits if desired and in 8 bit mode L Select 10 bit unpacking mode DPK bit if appropriate L Set VDEN bit to enable the display 19 Wait for 2 or more frame times to allow the display counters and control signals to become properly synchronized 20 Write to VDCTL to clear the BLKDIS bit 21 Display is enabled at the start of the first frame after BLKDIS 0 and begins with the first selected field DMA events are generated as triggered by VDTHRLD and the DEVTCT counter When a selected field has been displayed FLCOUNT FRMHEIGHT and FPCOUNT FRMWIDTH the appropriate F1D F2D or FRMD bits are set and cause the DCMP bit in VPIS to be set This generates a DSP interrupt if the DCMP bit is enabled in VPIE 4 48 Video Display Port SPRU629 Displaying Video in Raw Data Mode 22 If continuous display is enabled the video port begins displaying again at the start of the next field or frame If noncontinuous field 1 and field 2 or frame display is enabled the next field or frame is displayed during which the DSP must clear the appropriate completion status bit or a DCNA interrupt occurs and incorrect data may be output 4 11 Displaying Video in Raw Data Mode In order to display vide
77. pin VDATAnLO 0 Pin is logic low VDATAnHI 1 Pin is logic high t For CSL implementation use the notation VP_PDIN_PDINn_symval 5 12 General Purpose I O Operation SPRU629 GPIO Registers 5 1 6 Video Port Pin Data Output Register PDOUT The video port pin data output register PDOUT is shown in Figure 5 6 and described in Table 5 7 The bits of PDOUT determine the value driven on the corresponding GPIO pin if the pin is configured as an output Writes do not affect pins not configured as GPIO outputs The bits in PDOUT are set or cleared by writing to this register directly A read of PDOUT returns the value of the register not the value at the pin that might be configured as an input An alternative way to set bits in PDOUT isto write a 1 to the corresponding bit of PDSET An alternative way to clear bits in PDOUT is to write a 1 to the corre sponding bit of PDCLR PDOUT has these aliases PDSET writing a 1 to a bit in PDSET sets the corresponding bit in PDOUT to 1 writing a O has no effect and keeps the bits in PDOUT unchanged PDCLR writing a 1 to a bit in PDCLR clears the corresponding bit in PDOUT to 0 writing a O has no effect and keeps the bits in PDOUT unchanged Figure 5 6 Video Port Pin Data Output Register PDOUT 31 24 R 0 23 22 21 20 19 18 17 16 PDOUT22 PDOUT21 PDOUT20 PDOUT19 PDOUT18 PDOUT17 PDOUT16 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 PDOUT15
78. set IPCOUNT is reset when FPCOUNT FRMWIDTH IMGHOFF1 The default output values or blanking values are output during active pixels prior to IMGHOFF1 4 68 Video Display Port SPRU629 Video Display Registers Figure 4 47 Video Display Field 1 Image Offset Register VDIMGOFF1 16 iMGVOFF 31 30 28 27 R W 0 R 0 15 14 12 11 R W 0 0 WGHOFF R W 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 4 14 Video Display Field 1 Image Offset Register VDIMGOFF1 Field Descriptions Description Bit fieldt symvalt Value BT 656 and Y C Mode Raw Data Mode 31 NV Negative vertical image offset enable bit NONE 0 Not used NEGOFF 1 Display image window Not used begins before the first active line of field 1 Used for VBI data output 30 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 IMGVOFF1 OF value O FFFh Specifies the display image vertical offset in lines from the first active line of field 1 15 NH Negative horizontal image offset NONE 0 Not used NEGOFF 1 Display image window Not used begins before the start of active video Used for HANC data output 14 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 IMGHOFF1 OF value O FFFh Specifies the display image Specifies the display image horizontal offset in pixels
79. the DMA transfer size is essentially fixed in the user programmed DMA parameter table The preferred transfer size is often one entire line of data because this allows the most flexibility in terms of frame buffer line pitch in RAM Some modes of operation for the highest display rates may require more frequent DMA requests such as on a half or quarter line basis All requests are based on buffer thresholds In video capture mode DMA requests are made whenever the number of samples in the buffer reaches the threshold value In order to ensure that all data from a capture field frame gets emptied from the buffer the transfer size must be equal to the threshold and the total amount of field frame data must be a multiple of the transfer size For video display operation DMA requests are made whenever there is at least the threshold number of doublewords free in the FIFO This means that the transfer size must be equal to or smaller than the threshold so that it fits into the available space The field frame size must still be a multiple of the transfer size or there are pixels left in the buffer at the end of the field which appear at the start of the next field Overview 1 5 Video Port FIFO 1 2 2 Video Capture FIFO Configurations During video capture operation the video port FIFO has one of four configura tions depending on the capture mode For BT 656 operation the FIFO is split into channel A and B as shown in Figure 1 2 Each F
80. timing Raw data display includes a synchronized dual channel option This allows channel B to output a separate data stream using the same clock and control as channel A This mode is useful when used with a second video port in systems that require 24 bit to 30 bit RGB output The raw data mode uses a single FIFO of 5120 bytes for storage of output data The FIFO is filled by DMAs writing to the Y FIFO destination register A YDSTA DMAs are requested using the YEVTA event In raw sync mode RSYNC bit is set the FIFO is split into 2560 byte channel A and B buffers The channel B FIFO is filled by DMAs using the Y FIFO destination register B YDSTB as a destination Both YEVTA and YEVTB events are generated using the channel A timing control Video Display Port 4 25 Raw Data Display Mode 4 6 1 Raw Mode RGB Output Support The raw data display mode has a special pixel count feature that allows the FPCOUNT increment rate to be set FPCOUNT increments only when INCPIX samples have been sent out This option allows proper tracking of the display pixels when sending out sequential RGB samples INCPIX would be set to three in this case to indicate that a single pixel is represented by three output samples Sequential RGB samples output are also supported through a special FIFO unpacking mode When the 8 bit raw 34 unpacking is selected RGBX bit in VDCTL three output bytes are selected from each word and the fourth byte is ignored Th
81. to take a timestamp of the hardware counters The FIFO write controller keeps track of number of bytes received in a packet It multiplexes the timestamp data and the packet data onto the FIFO write data bus The timestamp and packet error information are inserted after each packet in the FIFO and must use the correct endian byte ordering The format for the timestamp is shown in Figure 3 26 and Figure 3 27 Figure 3 26 TSI Timestamp Format Little Endian 63 62 61 42 41 33 32 31 SPRU629 Video Capture Port 3 41 TSI Capture Mode Capture Line Boundary Conditions Figure 3 27 TSI Timestamp Format Big Endian 63 56 55 48 47 40 39 32 PCR 7 0 PCR 15 8 PCR 23 16 PCR 31 24 31 25 24 23 18 17 16 PCR extension 6 0 PCR32 PCR ext 8 7 15 8 7 6 5 0 3 8 7 Reading from the FIFO The YSRCA location is associated with the TSI capture buffer The YSRCA location is a read only pseudo register and is used to access the TSI data samples stored in the buffer The captured data packet size is set by VCASTOP The VCXSTOP and VCYSTOP bits set the 24 bits of TSI packet size VCXSTOP sets the lower 12 bits and VCYSTOP sets the upper 12 bits Capture is complete and the FRMC bit is set when the data counter equals the combined VCYSTOP and VCXSTOP value The video port generates a YEVT after the specified number of new samples has been captured in the buffer The number of samples required to generate YEVT is programmable and
82. 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 IMGVSIZE1 OF value O FFFh Specifies the display image height in lines 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 IMGHSIZE1 OF value O FFFh Specifies the display image Specifies the display image width in pixels This number width in pixels must be even the LSB is treated as 0 T For CSL implementation use the notation VP VDIMGSZ1 field symval 4 70 Video Display Port SPRU629 4 12 11 Video Display Registers Video Display Field 2 Image Offset Register VDIMGOFF2 The video display field 2 image offset register VDIMGOFF2 defines the field 2 image offset and specifies the starting location of the displayed image relative to the start of the active display The VDIMGOFF2 is shown in Figure 4 49 and described in Table 4 16 The image line counter ILCOUNT is reset to 1 on the first image line when FLCOUNT VBLNKYSTOP2 IMGVOFF2 If the NV bit is set ILCOUNT is reset to 1 when FLCOUNT VBLNKYSTOP2 IMGVOFF2 Display image pixels are output in field 2 beginning on the line where ILCOUNT 1 The default output values or blanking values are output during active lines prior to ILCOUNT 1 For a negative offset IMGVOFF2 must not be greater than VBLNKYSTOP2 The field 2 active image must not overlap the field 2 a
83. 0 cee 2 83 4 DMA Interface Operation ccc teens fioe cn Video Port Functionality Subsets 00 0 cece cee ete eee 2 5 DbataBus Width isu elles Dotto ew doit beth Ree eee 252 FIFOSIZE sexos pter eRRRR anina aa agii ie ERE CP REP KAAWAAN Contents V Contents 2 6 Video Port Throughput and Latency ees 2 6 1 Video Capture Throughput 0 00 tees 2 6 2 Video Display Throughput 2 tees 2 7 Video Port Control Registers 0 00 eee eee eens 2 7 1 Video Port Control Register VPCTL 0c cece eee eens 2 7 2 Video Port Status Register VPSTAT cc cece eee eee eens 2 7 3 Video Port Interrupt Enable Register VPIE 2 7 4 Video Port Interrupt Status Register VPIS 3 Video Capture Port 002s 4 AA nnn nh hn n nmn Discusses operation of the video capture port 3 4 Video Capture Mode Selection eee eee eae 3 2 BT 656 Video Capture Mode 0c cece en 3 2 1 BT 656 Capture Channels 0000 eee ees 3 2 2 BT 656 Timing Reference Codes cc cee tenes 3 2 8 BT 656 Image Window and Capture an 3 2 4 BT 656 Data Sampling 0 0 cece tenes 3 2 5 BT 656 FIFO Packing a WA MM eee eee 3 3 Y C Video Capture Mode 0 0 c ccc ett eens 3 3 1 Y C Capture Channels 20 cece eens 3 3 2 Y C Timing Reference Codes 0000 c cece eee eee teens 3 3 3 Y C Im
84. 04 VCTL1 HBLNK T X t VCTL1 HSYNO f 8 UUU VCLKOUT AUU WU 1 U Display Image Active Video Blanking N o ERE KE DER Geese Det Or e VDOUT 9 0 BBEEBEB ay REMIS EAV Blanking Data SAV EAV FLCOUNT n 1 n na1 FRMWIDTH 858 IMGHOFF1 8 HSYNCSTART 736 HBLNKSTART 720 IMGHSIZE1 704 HSYNCSTOP 800 HBLNKSTOP 856 IMGHOFF2 8 IMGHSIZE2 704 t Assumes VCT1P bit in VPCTL is set to 1 active low output HSYNC output when VCTL1S bit in VDCTL is set to 00 HBLNK output when VCTL1S bit is set 01 HBLNK operation when HBDLA bit in VDHBLNK is set to 1 Diagram assumes a two VCLK pipeline delay between internal counters and output signals sejduiex3 Buwi Aejdsig SPRU629 Display Timing Examples The interlaced BT 656 vertical output timing is shown in Figure 4 34 The BT 656 active field 1 is 244 lines high and active field 2 is 243 lines high This example shows the 480 line image window centered in the screen This results in an IMGVOFFnof 3 lines and also results in a nondata line at the end of field 1 due to its extra active line The VBLNK and VSYNC signals are shown as they would be output for active low operation Note that only one of the two signals is actually available exter nally The VBLNK and VSYNC edges for field 1 occur at the end of an active line so their XSTART XSTOP values are set to 720 start of
85. 17 Y6 Y 7 Y8 Y9 Y 10 Yi Y FIFO YO Yi Y2 Y3 Y4 Y5 63 61 5251 4241 3231 29 2019 109 0 t Cb 6 Cb7 Cb 8 Cb 9 Cb 10 Cb 11 Cb FIFO Cb 0 Cb 1 Cb2 Cb3 Cb4 Cb5 63 61 5251 4241 3231 29 2019 109 0 1 Cr6 Cr7 Cr8 Cr9 Cr 10 Cr 11 Cr FIFO Cro Cr1 Cr2 Cr3 Cr4 Cr 5 Big Endian Packing 4 20 Video Display Port SPRU629 Video Output Filtering 4 4 Video Output Filtering The video output filter performs simple hardware scaling and resampling on outgoing 8 bit BT 656 or 8 bit Y C data Filtering hardware is disabled during 10 bit or raw data display modes 4 4 1 Output Filter Modes The output filter has four modes of operation no filtering 2x scaling chromi nance resampling and 2x scaling with chrominance resampling Filter opera tion is determined by the DMODE SCALE and RESMPL bits of the VDCTL Table 4 3 shows the output filter mode selection When 8 bit BT 656 or Y C display operation is selected DMODE x00 scaling is selected by setting the SCALE bit and chrominance resampling is selected by setting the RESMPL bit If 8 bit BT 656 or Y C display is not selected DMODE x00 filtering is disabled Table 4 3 Output Filter Mode Selection VDCTL Bit DMODE RESMPL SCALE Filter Operation x00 0 0 No filtering x00 0 1 2x scaling x00 1 0 Chrominance resampling full scale x00 1 1 2x scaling with chrominance resampling x01 x X No filtering x10 x X No filtering x11 x X No filtering SPRU629 Video Display Port 4 21 Video
86. 1YSTART and FPCOUNT FLD1XSTART The FLD output is completely independent of the timing control codes The F bit in the EAV SAV codes is controlled by the VDFBIT register Figure 4 51 Video Display Field 1 Timing Register VDFLDT1 31 28 27 16 R 0 R W 0 15 12 11 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 4 18 Video Display Field 1 Timing Register VDFLDT1 Field Descriptions Bit fieldt symvalt Value Description 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 FLD1YSTART OF value O FFFh Specifies the first line of field 1 The line where FLD is deasserted 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 FLD1XSTART OF value O FFFh Specifies the pixel on the first line of field 1 where the FLD output is deasserted t For CSL implementation use the notation VP VDFLDT1 field symval 4 74 Video Display Port SPRU629 Video Display Registers 4 12 14 Video Display Field 2 Timing Register VDFLDT2 The video display field 2 timing register VDFLDT2 sets the timing of the field identification signal The VDFLDT2 is shown in Figure 4 52 and described in Table 4 19 In raw data mode the FLD signal is asserted whenever the frame line counter FLCOUNT is equal to FLD2YSTART and the frame pixel counter FPCOUNT is
87. 2 11 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 4 17 Video Display Field 2 Image Size Register VDIMGSZ2 Field Descriptions Description Bit fieldt symvalt Value BT 656 and Y C Mode Raw Data Mode 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 IMGVSIZE2 OF value O FFFh Specifies the display image height in lines 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 IMGHSIZE2 OF value O FFFh Specifies the display image Specifies the display image width in pixels This number width in pixels must be even the LSB is treated as 0 t For CSL implementation use the notation VP VDIMGSZ2 field symval SPRU629 Video Display Port 4 73 Video Display Registers 4 12 13 Video Display Field 1 Timing Register VDFLDT1 The video display field 1 timing register VDFLDT1 sets the timing of the field identification signal The VDFLDT1 is shown in Figure 4 51 and described in Table 4 18 In raw data mode the FLD signal is deasserted to indicate field 1 display whenever the frame line counter FLCOUNT is equal to FLD1YSTART and the frame pixel counter FPCOUNT is equal to FLD1XSTART this is shown in Figure 4 6 page In BT 656 and Y C mode the FLD signal is deasserted to indicate field 1 dis play whenever FLCOUNT FLD
88. 29 Video Capture Port 3 33 Raw Data Capture Mode The 8 bit raw data mode stores all data in a single FIFO Four samples are packed into each word as shown in Figure 3 17 Figure 3 17 8 Bit Raw Data FIFO Packing vekna veks LT LT LE LE LE LILI LIE LI LILI VDIN 9 2 VDIN 19 12 63 5655 4847 4039 3231 2423 1615 87 0 t Raw 15 Raw 14 Raw 13 Raw 12 Raw 11 Raw 10 Raw 9 Raw 8 Raw FIFO Raw 7 Raw 6 Raw 5 Raw4 Raw 3 Raw 2 Raw 1 Raw 0 Little Endian Packing 63 5655 4847 4039 3231 2423 1615 87 0 t Raw 8 Raw 9 Raw 10 Raw 11 Raw 12 Raw 13 Raw 14 Raw 15 Raw FIFO Raw 0 Raw 1 Raw 2 Raw 3 Raw4 Raw 5 Raw 6 Raw 7 Big Endian Packing The 10 bit raw data mode stores all data into a single FIFO Two samples are packed into each word with zero or sign extension as shown in Figure 3 18 Figure 3 18 10 Bit Raw Data FIFO Packing verkina verkins LT LJ LT LI LT LFELELEFELELILI voiN e o VOIN t9 10 AA 1 Raw 2 Raw oY aw Raw AE N N 63 5857 4847 4241 3231 2625 1615 10 9 0 0 SE Raw 15 0 SE Raw 14 0 SE Raw 13 0 SE Raw 12 0 SE Raw 11 0 SE Raw 10 0 SE Raw 9 0 SE Raw8 0 SE Raw 7 0 SE Raw 6 0 SE Raw 5 0 SE Raw4 Y FIFO 0 SE Raw 3 0 SE Raw 2 0 SE Raw 1 0 SE Raw 0 Little Endian Packing 63 5857 4847 4241 3231 2625 1615 10 9 0 0 SE Raw 12 0 SE Raw 13 0 SE Raw 14 0 SE Raw 15 0 SE Raw 8 0 SE Raw 9 0 SE Raw 10 0 SE
89. 3 69 Video Capture Registers Table 3 23 Video Capture Channel B Control Register VCBCTL Field Descriptions Continued Description Bit field symvalt Value BT 656 or Y C Mode Raw Data Mode TSI Mode 16 HRST HCOUNT reset method bit EAV 0 EAV or Not used Not used VCTL1 active edge SAV 1 SAV or Not used Not used VCTL1 inactive edge 15 VCEN Video capture enable bit Other bits in VCBCTL except RSTCH and BLKCAP bits may only be changed when VCEN 0 DISABLE 0 Video capture is disabled ENABLE 1 Video capture is enabled 14 13 PK10B 10 bit packing format select bit ZERO 0 Zero extend Zero extend Not used SIGN th Sign extend Sign extend Not used DENSEPK 2h Dense pack zero Dense pack zero Not used extend extend 3h Reserved Reserved Not used 12 LFDE Long field detect enable bit DISABLE 0 Long field detect Not used Not used is disabled ENABLE 1 Long field detect Not used Not used is enabled 11 SFDE Short field detect enable bit DISABLE 0 Short field detect Not used Not used is disabled ENABLE 1 Short field detect Not used Not used is enabled t For CSL implementation use the notation VP VCBCTL field symval For complete encoding of these bits see Table 3 6 Table 3 11 and Table 3 12 3 70 Video Capture Port SPRU629 Table 3 23 Video Capture Channel B Control Register VCBCTL Field Descriptions Continued Video Capture Registers Descripti
90. 3 VSYNCYSTOP2 269 VBITCLR2 283 T Assumes VCT2P bit in VPCTL is set to 1 active low output VSYNC output when VCTL2S bit in VDCTL is set to 00 VBLNK output when VCTL2S bit is set 01 If DVEN bit in VDCTL is set to 1 otherwise blanking value is output 4 38 Video Display Port SPRU629 Display Timing Examples 4 9 2 Interlaced Raw Display Example SPRU629 This section shows an example of raw display output for the same 704 x 408 interlaced image The horizontal output timing is shown in Figure 4 35 This diagram assumes that there is a two VCLK pipeline delay between the internal counter changing and the output on external pins The actual delay can be longer or shorter as long as it is consistent within any display mode The active line is 720 pixels wide Figure 4 35 shows the 704 pixel image window centered in the screen that results in an IMGHOFFx of 8 pixels The HBLNK and HSYNC signals are shown as they would be output for active low operation Note that only one of the two signals is actually available exter nally The HBLNK inactive edge occurs on sample 0 The IPCOUNT operation follows the description in section 4 1 2 IPCOUNT resets to O at the first displayed pixel FRCOUNT IMGHOFF and stops counting at the last displayed pixel IPCOUNT IMGHSIZEx Both the IPCOUNT and FPCOUNT counters increment on every third VCLKIN rising edge as programmed by the INCPIX bits in VDTHRLD with a value of 3 VDOUT sho
91. 3 Y2 Y1 YO 63 5857 4847 4241 3231 2625 1615 109 0 1 Cb7 Cb6 Cb5 Cb4 Cb FIFO Cb3 Cb 2 Cb 1 Cb0 63 5857 4847 4241 3231 2625 1615 109 0 1 Cr7 Cr6 Cr5 Cr4 Cr FIFO Cr3 Cr2 Cr1 Cro Little Endian Unpacking 63 5857 4847 4241 3231 2625 1615 109 0 Y 12 Y 13 Y 14 Y 15 Y8 Y9 Y 10 Y 11 Y4 Y5 Y6 Y7 Y FIFO YO Yi Y2 Y3 63 5857 4847 4241 3231 2625 1615 109 0 t Cb4 Cb5 Cb6 Cb7 Cb FIFO Cb 0 Cb 1 Cb2 Cb3 63 5857 4847 4241 3231 2625 1615 109 0 t Cr4 Cr5 Cr6 Cr7 Cr FIFO Cro Cr 1 Cr2 Cr3 Big Endian Unpacking SPRU629 Video Display Port 4 19 Y C Video Display Mode In 10 bit Y C dense pack mode three samples are unpacked from each word in the FIFO as seen in Figure 4 18 Figure 4 18 10 Bit Y C Dense FIFO Unpacking VDOUT 9 0 VDOUT 19 10 Cb 0 63 61 5251 4241 3231 29 2019 109 0 Y 23 Y22 Y 21 Y 20 Y 19 Y 18 Y 17 Y 16 Y 15 Y 14 Y 13 Y 12 Yu Y 10 Y9 Y8 Y7 Y6 Y FIFO Y5 Y4 Y3 Y2 Yi YO 63 61 5251 4241 3231 29 2019 109 0 1 Cb 11 Cb 10 Cb 9 Cb8 Cb7 Cb 6 Cb FIFO Cb5 Cb4 Cb3 Cb2 Cb1 Cb0 63 61 5251 4241 3231 29 2019 109 0 1 Cr 11 Cr 10 Cr9 Cr8 Cr 7 Cr 6 Cr FIFO Cr 5 Cr4 Cr3 Cr2 Cr1 Cro Little Endian Packing 63 61 5251 4241 3231 29 2019 109 0 Y 18 Y 19 Y 20 Y 21 Y 22 Y 23 Y12 Y 13 Y14 Y 15 Y 16 Y
92. 3 us r t 5120 6 06 ns 165 MBytes s 20 bit n 1 tj lt te n ty tj lt 1280 110 MHz 1 3 88 us t lt 15 52 us r t 5120 3 03 ns 330 MBytes s Video Port 2 15 Video Port Control Registers A DMA write throughput of at least 330 MBytes s is required for the highest display rate operation supported by 20 bit implementations of the video port C64x devices including the video port typically have more than enough DMA bandwidth to support this throughput requirement However when using multi ple high bandwidth peripherals together it is important to consider the total DMA throughput required by the peripherals being used concurrently 2 7 Video Port Control Registers The video port control registers are listed in Table 2 4 See the device specific datasheet for the memory address of these registers After enabling the video port in the peripheral configuration register PERCFG there should be a delay of 64 CPU cycles before accessing the video port registers Table 2 4 Video Port Control Registers Acronym VPCTL Register Name Video Port Control Register VPSTAT VPIE VPIS 2 16 Video Port Video Port Status Register Video Port Interrupt Enable Register Video Port Interrupt Status Register 9 NII 2 N aj o Mi LW SPRU629 Video Port Control Registers 2 74 Video Port Control Register VPCTL The video port control register VPCTL determines the basic operation of the video port
93. 4 31 10 Bit Raw 3 4 FIFO Unpacking 63 5857 4847 4241 3231 2625 1615 109 Raw 5 B1 Raw 4 G1 Raw 3 R1 Raw 2 B0 Raw 1 G0 Raw 0 RO Raw FIFO Little Endian Unpacking 63 5857 4847 4241 3231 2625 1615 109 Raw 3 R1 Raw 4 G1 Raw 5 B1 Raw 0 RO Raw 1 G0 Raw 2 B0 Raw FIFO Big Endian Unpacking SPRU629 Video Display Port 4 29 Video Display Field and Frame Operation 4 7 Video Display Field and Frame Operation 4 7 1 4 30 As a video source the video port always outputs entire frames of data and transmits continuous video control signals Depending on the DMA structure however the video port may need to interrupt the DSP on a field or frame basis to allow it to update video port registers or DMA parameters To achieve this the video port provides programmable control over the display process Display Determination and Notification In order to accommodate various display scenarios DMA structures and processing flows the video port employs a flexible display and DSP notifica tion system This is programmed using the CON FRAME DF1 and DF2 bits in VDCTL The CON bit controls the display of multiple fields or frames When CON 1 continuous display is enabled the video port displays outgoing fields assuming the VDEN bit is set without the need for DSP interaction It relies on a single display buffer in memory or on a DMA structure wi
94. 4 General Purpose I O Operation SPRU629 GPIO Registers 5 1 12 Video Port Pin Interrupt Clear Register PICLR The video port pin interrupt clear register PICLR is shown in Figure 5 12 and described in Table 5 13 PICLR is an alias of the video port pin interrupt status register PISTAT for writes only Writing a 1 to a bit of PICLR clears the corre sponding bit in PISTAT Writing a 0 has no effect Register reads return all Os Figure 5 12 Video Port Pin Interrupt Clear Register PICLR 31 24 R 0 23 22 21 20 19 18 17 16 PICLR22 PICLR21 PICLR20 PICLR19 PICLR18 PICLR17 PICLR16 R 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 PICLR15 PICLR14 PICLR13 PICLR12 PICLR11 PICLR10 PICLR9 PICLR8 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 7 6 5 4 3 2 1 0 PICLR7 PICLR6 PICLR5 PICLR4 PICLR3 PICLR2 PICLR1 PICLRO W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 Legend R Read only W Write only n value after reset SPRU629 General Purpose I O Operation 5 25 GPIO Registers Table 5 13 Video Port Pin Interrupt Clear Register PICLR Field Descriptions Bit fieldt symvalt Value Description 31 23 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 22 PICLR22 Allows PISTAT22 bit to be cleared to a logic low NONE 0 No effect VCTLSCLR 1 Clears PISTAT22 VCTL3 bit to 0 21 PICLR21 Allows PISTAT21 bit to be cleared to a logic low NONE 0 No effect VC
95. 4 VPHLT Video port halt bit This bit is set upon hardware or software reset The other VPCTL bits except VPRST can only be changed when VPHLT is 1 VPHLT is cleared by writing a 1 Writing 0 has no effect NONE CLEAR 13 8 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 7 VCLK2P VCLKa pin polarity bit Has no effect in capture mode NONE REVERSE Inverts the VCLK2 output clock polarity in display mode 6 VCT3P VCTL3 pin polarity Does not affect GPIO operation If VCTL3 pin is used as a FLD input on the video capture side then the VCTL3 polarity is not considered the field inverse is controlled by the FINV bit in the video capture channel x control register VCxCTL NONE ACTIVELOW Indicates the VCTL3 control signal input or output is active low 5 VCT2P VCTL2 pin polarity bit Does not affect GPIO operation NONE ACTIVELOW Indicates the VCTL2 control signal input or output is active low 4 VCT1P VCTL1 pin polarity bit Does not affect GPIO operation NONE ACTIVELOW Indicates the VCTL1 control signal input or output is active low 3 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect t For CSL implementation use the notation VP_VPCTL_field_symval 2 18 Video Port SPRU629 Video Port Control Registers Table 2 5 Video Port Control Register VPCTL Field Descriptions Continued Bit fieldt
96. 47 716 10 Blanking Value 748 716 10 Blanking Value 749 1 i 716 10 Blanking Value 750L RU 716 10 Blanking Value 1 716 10 Blanking Value 716 10 Blanking Value IMGVOFF1 3 VBLNKXSTART1 1280 VSYNCXSTART1 1280 FLD1XSTART n a IMGVSIZE1 716 VBLNKYSTART1 746 VSYNCYSTART1 1 FLD1YSTART 1 IMGVOFF2 n a VBLNKXSTOP1 1280 VSYNCXSTOP1 1280 FLD2XSTART n a IMGVSIZE2 n a VBLNKYSTOP1 26 VSYNCYSTOP1 6 FLD2YSTART gt 750 FRMHEIGHT 750 VBLNKXSTART2 n a VSYNCXSTART2 n a VBITSET1 746 VBLNKYSTART2 gt 750 VSYNCYSTART2 gt 750 FBITSET 1 VBITCLR1 26 VBLNKXSTOP2 n a VSYNCXSTOP2 n a FBITCLR gt 750 VBITSET2 n a VBLNKYSTOP2 gt 750 VSYNCYSTOP2 gt 750 VBITCLR2 n a T Assumes VCT2P bit in VPCTL is set to 1 active low output VSYNC output when VCTL2S bit in VDCTL is set to 00 VBLNK output when VCTL2S bit is set 01 If DVEN bit in VDCTL is set to 1 otherwise blanking value is output 4 46 Video Display Port SPRU629 Displaying Video in BT 656 or Y C Mode 4 10 Displaying Video in BT 656 or Y C Mode In order to display video in the BT 656 or Y C format the following steps are needed 1 2 Set the frame size in VDFRMSZ Set the number of lines per frame FRMHIGHT and the number of pixels per line FRMWIDTH Set the horizontal blanking in VDHBLNK Specify the frame pixel counter value where horizontal blanking starts HBLNKSTART and pixel location where horizontal bl
97. 5 60 Format 8 YA enable display Je sy set VDEN to enable display for loop back VP FSETH vpBDisplayHandle VDCTL VDEN VP VDCTL VDEN ENABLE clear BLKDIS in VD CTL to enable display DMA events xy VP FSETH vpBDisplayHandle VDCTL BLKDIS VP VDCTL BLKDIS CLEAR i Function VPDispIsr Bil Description This display ISR clears FRMD to continue display in this non continuous mode and also clears other status bits x y xy interrupt void VPDispIsr void f Uint32 vpis 0 vpis VP RGETH vpDisplayHandle VPIS if vpis amp VP VPIS DCMP MASK frame display complete J Clear frame complete bit FRMD to continue display VP FSETH vpDisplayHandle VDSTAT FRMD VP VDSTAT FRMD CLEAR clear DCMPA to enable next frame complete interrupts ad VP FSETH vpDisplayHandle VPIS DCMP VP_VPIS_DCMP_CLEAR displayFrameCountt increment displayed frame count Bil if vpis amp _VP_VPIS_DUND_MASK underrun error dispUnderruntt clear DUND to enable next underrun interrupts 7 VP FSETH vpDisplayHandle VPIS DUND VP VPIS DUND CLEAR SPRU629 Video Port Configuration Examples A 17 Example 2 Noncontinuous Frame Display for 525 60 Format Function Input s Description setupVPDispEDMA portNumber display video por
98. 5 8 7 0 R W 0 R W 0 Legend R W Read Write n value after reset 4 86 Video Display Port SPRU629 Video Display Registers Figure 4 63 Video Display Default Display Value Register VDDEFVAL Raw Data Mode 31 20 19 16 R W 0 R W 0 15 0 DEFVAL R W 0 Legend R W Read Write n value after reset Table 4 29 Video Display Default Display Value Register VDDEFVAL Field Descriptions Description Bit fieldt symvalt Value BT 656 and Y C Mode Raw Data Mode 31 24 CRDEFVAL OF value 0 FFh Specifies the 8 MSBs of the Not used default Cr display value 31 20t Reserved 0 Not used Reserved The reserved bit location is always read as 0 A value written to this field has no effect 19 0t DEFVAL OF value O FFFFFh Not used Specifies the default raw data display value 23 16 CBDEFVAL OF value 0 FFh Specifies the 8 MSBs of the Not used default Cb display value 15 8 Reserved 0 Reserved The reserved bit Not used location is always read as 0 A value written to this field has no effect 7 0 YDEFVAL OF value 0 FFh Specifies the 8 MSBs of the Not used default Y display value t For CSL implementation use the notation VP_VDDEFVAL_field_symval Raw data mode only SPRU629 Video Display Port 4 87 Video Display Registers 4 12 25 Video Display Vertical Interrupt Register VDVINT The video display vertical interrupt register VDVINT controls the generation of vertical int
99. 5 Cb 34 Cb 33 Cb 32 Line n 63 5655 4847 4039 3231 2423 1615 87 0 1 Cr7 Cr6 Cr5 Cr4 Cr3 Cr2 Cr1 Cro Line n 1 Cr FIFO Cr 38 Cr 37 Cr 36 Cr 35 Cr 34 Cr 33 Cr 32 Line n Little Endian Packing 63 5655 4847 4039 3231 2423 1615 87 0 YO Y1 Y2 a3 Y4 Y5 Y6 Y7 Line n 1 Y 72 Y 73 Y 74 Y 75 Y 76 Y77 Line n Y FIFO Y 64 Y 65 Y 66 Y 67 Y 68 Y 69 Y 70 Y71 63 5655 4847 4039 3231 2423 1615 87 0 1 Cb 0 Cb 1 Cb2 Cb3 Cb4 Cb5 Cb6 Cb7 Line n 1 Cb FIFO Cb 32 Cb 33 Cb 34 Cb 35 Cb 36 Cb 37 Cb 38 Line n 63 5655 4847 4039 3231 2423 1615 87 0 t Cro Cri Cr2 Cr3 Cr4 Cr5 Cr6 Cr 7 Line n 1 Cr FIFO Cr 32 Cr 33 Cr 34 Cr 35 Cr 36 Cr 37 Cr 38 Line n Big Endian Packing SPRU629 4 34 Video Display Port Display Timing Examples 4 9 Display Timing Examples The following are examples of display output for several modes of operation 4 9 1 Interlaced BT 656 Timing Example SPRU629 This section shows an example of BT 656 display output for a 704 x 408 inter laced output image as might be generated by MPEG decoding The horizontal output timing is shown in Figure 4 33 This diagram assumes that there is a two VCLK pipeline delay between the internal counter changing and the output on external pins The actual delay can be longer or shorter as long as it is consistent within any display mode The BT 656 active line is 720 pixels wide Figure 4 33 shows the 704 pixel image window centered in the screen that results in an IMGHOFFx of 8 pixels The HBLNK and HSYNC signals a
100. 79 80 135 136 137 138 139 140 856 857 O 1 2 VCOUNT n n 1 SPRU629 Video Capture Port 3 23 BT 656 and Y C Mode Field and Frame Operation 3 4 4 Field Identification In order to properly synchronize to the source data stream and capture the correct fields field identification needs to be performed Field identification is made using one of three methods EAV field indicator input or field detect logic The field identification method is determined by the EXC FLDD and FINV bits in VCXCTL Table 3 9 Field Identification Programming VCxCTL Bit EXC FLDD 0 0 0 1 1 0 Field Detect Method EAV code EAV code Use FID input Use field detect from HSYNC and VSYNC inputs In the BT 656 standard and in many Y C standards a field identification F bit is contained in EAV and SAV codes embedded in the data stream In the EAV field detect method the F bit in the EAV of the first line of every field is checked If F 0 then the current field is defined as field 1 If F 1 then the current field is defined as field 2 Depending on how the first line of a field is defined as determined by the VRST bit in VCxCTL and the video stream being captured the F value at the start of a field may not reflect the actual field being supplied The FINV bit in VCxCTL allows the detected field value to be inverted For example in BT 656 525 60 operation the F bit changes to 0 to indicate field 1 on the fourth line of the field
101. 8 Raw 9 Raw 10 Raw 11 Raw 4 Raw 5 Raw 6 Raw 7 Raw 0 Raw 1 Raw 2 Raw 3 Raw FIFO Figure 4 29 20 Bit Raw FIFO Unpacking The FIFO unpacking for 20 bit raw format is shown in Figure 4 29 One sample Big Endian Unpacking is unpacked from each word of the FIFO 63 5251 3231 2019 Raw 7 Raw 6 Raw 5 Raw 4 Raw 3 Raw2 Y FIFO Raw 1 Raw 0 Little Endian Unpacking 63 5251 3231 2019 Raw 6 Raw 7 Raw 4 Raw 5 Raw 2 Raw 3 Y FIFO Raw 0 Raw 1 Big Endian Unpacking 4 28 Video Display Port In 8 bit raw 744 mode three samples are unpacked from the FIFO and the Raw Data Display Mode remaining byte is ignored This is shown in Figure 4 30 Figure 4 30 8 Bit Raw 3 4 FIFO Unpacking vexout LE LT LILI LIL LILI LI LU Lu 63 5655 4847 4039 3231 Raw 11 B3 Raw 10 G3 Raw 9 R3 Raw 5 B1 Raw 4 G1 Raw 3 R1 Raw FIFO Little Endian Unpacking 63 5655 4847 4039 3231 2423 1615 Raw 6 R2 Raw 7 G2 Raw 8 B2 Raw 9 R3 Raw 10 G3 Raw 11 B3 Raw 0 RO Raw 1 G0 Raw 2 B0 Raw 3 R1 Raw 4 G1 Raw 5 B1 Raw FIFO In 10 bit raw 34 mode three samples are unpacked from every doubleword of the FIFO and the remaining halfword is ignored This is shown in Figure 4 31 Big Endian Unpacking Figure
102. 9 Video Port Throughput and Latency 2 6 2 Video Display Throughput Video display throughput may be calculated in a manner similar to video capture In this case the time to fill the display FIFO must be less than the time to empty the FIFO or underflow occurs The 110 MHz display rate supports a maximum display resolution of 1280 x 1024 at 63 Hz frame rate This means that the horizontal blanking time is 3 88 us The time to empty a completely full FIFO may be represented by the formula tg n ty where tg is the time to empty the FIFO of active samples ty is the horizontal blanking time and n is the number of lines of active video that the FIFO can hold In raw display mode the FIFO is 5120 bytes The number of samples that the buffer can hold depends on the buffer packing mode as listed in Table 2 3 Table 2 3 Raw Video Display FIFO Capacity SPRU629 8 Bit 10 Bit Dense 10 16 Bit 20 Bit Samples 5120 3840 2560 1280 Using these values and the formula above the maximum time to fill the FIFO ti may be calculated for each case The DMA input rate rj is then calculated as the FIFO size divided by tj 8 bit n 4 t tg n ty t lt 5120 110 MHz 4 3 88 us t lt 62 6 us r 1 5120 12 12 ns 82 5 MBytes s 10 bit dense n23 t tg n ty tj lt 3840 110 MHz 3 3 88 us tj 46 55 us r t 5120 9 09 ns 110 MBytes s 16 bit n 2 ty lt te ty tj lt 2560 110 MHz 2 3 88 us tj lt 31 0
103. A interrupt occurs regardless of the state of FRMD Functions identically to continuous field 1 display mode except the FRMD bit is used instead of the F1D bit If external control signals are used they must follow progressive format 1 1 1 0 Reserved 1 1 1 1 Reserved 4 7 2 Video Display Event Generation The display FIFOs are filled using DMAs as requested by the video port DMA events The VDTHRLD value indicates the level at which the FIFO has enough roomto receive another DMA block of data Depending on the size of the DMA the FIFO may have room for multiple transfers before reaching the VDTHRLD level Once the threshold is reached another DMA event is generated as soon as the FIFO again falls below the VDTHRLD level Once an entire field worth of data has been sent to the FIFO the video port may need to stop generating events in order to allow the DSP to change DMA Since display may not yet be complete the FIFO continues to empty after falling belov VDTHRLD a display event counter DEVTCT is provided to track the number of requested YEVT events The counter is loaded with the number of events needed in a display field DISPEVT1 or DISPEVT2 and is decremented each time the event is requested Once the counter reaches 0 further display events are inhibited At the start of the next field DEVTCT is reloaded and display events are reenabled 4 32 Video Display Port SPRU629 Display Line Boundary Conditions 4 8 Display Line
104. AGE SIZE1 VCA VDTHRLD1 8 define VCA_CAPEVT2 VCA IMAGE SIZE2 VCA VDTHRLD2 8 define CAPCHA FRAME COUNT 5 in this example A 2 Video Port Configuration Examples y Ki are si Bi un x SPRU629 Example 1 Noncontinuous Frame Capture for 525 60 Format y f EDMA parameters for capture Y event that are specific to this example x Ha Ki define VCA Y EDMA ELECNT VCA THRLD FIELD1 2 because VCA THRLD FIELDn is in double words and element size is 32 bit define VCA Y EDMA FRMCN VCA CAPEVT1 VCA CAPEVT2 CAPCHA FRAME COUNT KK KK KK KR A AA A AA A AA A A A A A Kk Kk kk kk ke ko ke koe ko ke ok FT FT EF EF x x f Description 8 bit BT 656 non continuous frame capture f EX Ki Some important field descriptions rA JE xf CMODE 000 8 bit BT 656 mode CON 0 FRAME 1 capture frame x7 CF2 0 kf CF1 0 8 bit non continuous frame capture k SCALE 0 no scaling E RESMPL 0 no resampling f 10BPK X not used in 8 bit capture kf EXC 0 use EAV SAV codes 7 VRST 1 end of vertical blanking 4 HRST 0 start of horizontal blanking FLDD 0 1st line EAV or FID input FINV 0 no field invert KJ RDFE X used in Raw mode only Enable field identification SSE X used in Raw mode only S
105. BT 656 mode FPCOUNT and IPCOUNT increment on every other VCLKIN rising edge In raw mode FPCOUNT and IPCOUNT increment on every 1 to 16 VCLKIN cycles as programmed by the INCPIX bits in the video display threshold register VDTHRLD FPCOUNT and FLCOUNT are compared to various values to determine when to assert and negate various control signals The 12 bit FRCOUNT is used to determine where to enable and disable horizontal sync and blanking informa tion along each scan line The state of FPCOUNT is reflected in the VDXPOS bits of the video display status register VDSTAT Figure 4 5 shows how the horizontal blanking and horizontal synchronization signals are triggered HBLNK and HSYNC are shown active high Figure 4 5 Horizontal Blanking and Horizontal Sync Timing FPCOUNT 1 18j 719 720 7351736 7991800 857 Ol 1 HBLNK I L A A HSYNC calc AA CA 1 FPCOUNT HBLNKSTOP FPCOUNT HBLNKSTART mka bina bin Larah FPCOUNT HSYNCSTART The 12 bit FLCOUNT counts which scan line is being generated The FLCOUNT is reset to 1 after reaching the count specified in VDFRMSZ For BT 656 operation the FRMHIGHT would be set to 525 525 60 operation or 625 625 50 operation The state of FLCOUNT is reflected in the VDYPOS bits of VDSTAT Figure 4 6 shows how the vertical blanking vertical synchro nization and field identification signals are triggered VBLNK and
106. Because of slight timing variations the VSYNC transition may not coincide exactly with the HSYNC transition The detection logic should implement a 64 clock detection window around HSYNC If both HSYNC and VSYNC leading edges occur within 64 cycles of each other then field 1 is detected otherwise field 2 is assumed This is shown in Figure 3 11 for active low sync signals Figure 3 11 Field 1 Detection Timing VCLKIN VSYNC VCTL2 HSYNC VCTL1 STUNUU PLO eme rir ur lu is V C ss rae 64 Clocks gt t 64 Clocks 889 PLU 3 4 5 Short and Long Field Detect SPRU629 The short and long field detect logic is used to notify the DSP when a captured field shorter or longer than expected Detection is enabled by the SFDE and LFDE bits in VCXCTL The SFD and LFD bits in VPIS indicate when a short or long field occurred and trigger an interrupt to the DSP if enabled If a vertical blanking period is detected before the end of the capture field a short field is detected If EAV is used for vertical sync EXC 0 then a short field is detected when an EAV with V 1 occurs on or before VCOUNT VCYSTOPn If the VCTL2 input is used for vertical sync EXC 1 then a short field is detected if a VCTL2 active edge occurs before VCOUNT VCYSTOPn If a vertical blanking period occurs more than 1 line past the end of the capture field a long field is detected A long
107. Boundary Conditions SPRU629 In orderto simplify DMA transfers FIFO doublewords do not contain data from more than one display line This means that a FIFO read must be performed whenever 8 bytes have been output or when the line complete condition IPCOUNT IMGHSIZE occurs Thus every display line begins on a double word boundary and non doubleword length lines are truncated at the end An example is shown in Figure 4 32 In Figure 4 32 8 bit Y C mode the line length is not a doubleword When the condition IPCOUNT IMGHSIZE occurs the remaining bytes of the FIFO doubleword are ignored and the output switches to the default output value or the EAV code followed by blanking if the end of the active video line has been reached The next display line then begins in the next FIFO location at byte 0 This operation extends to all display modes Video Display Port 4 33 Display Line Boundary Conditions Figure 4 32 Display Line Boundary Example IPCOUNT IMGSIZE 78 Linen vetkout U LI LI LILI LILI LILI LU LU vu VDOUT 9 2 VDOUT 19 12 63 5655 4847 4039 3231 2423 1615 87 Y7 Y6 Y5 Y4 Y3 Y2 Y 1 YO Line n 1 Y 77 Y 76 Y 75 Y 74 Y 73 Y 72 Linen Y FIFO Y71 Y70 Y 69 Y 68 Y 67 Y 66 Y 65 Y 64 63 5655 4847 4039 3231 2423 1615 87 0 t Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb 1 Cb 0 Line n 1 Cb FIFO Cb 38 Cb 37 Cb 36 Cb 3
108. CBSTOP2 defines the end of the field 2 captured image VCxSTOP2 is shown in Figure 3 34 and described in Table 3 19 These registers are not used in raw data mode or TSI mode because their capture sizes are completely defined by the field 1 start and stop registers Figure 3 34 Video Capture Channel x Field 2 Stop Register VCASTOP2 VCBSTOP2 31 28 27 16 R 0 R W 0 15 12 11 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 3 19 Video Capture Channel x Field 2 Stop Register VCxSTOP2 Field Descriptions Description Bit field symvalt Value BT 656 or Y C Mode TSI Mode 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 VCYSTOP OF value 0 FFFh Last captured line Not used Not used 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 VCXSTOP OF value 0 FFFh Last captured pixel Not used Not used VCXSTOP 1 Must be an even value the LSB is treated as 0 T For CSL implementation use the notation VP VCxSTOP2 field symval 3 62 Video Capture Port SPRU629 Video Capture Registers 3 13 7 Video Capture Channel x Vertical Interrupt Register VCAVINT VCBVINT The video capture channel x vertical interrupt register VCAVINT VCBVINT controls the generation of vertical interrupts in each field VCxVINT is shown in Figur
109. CH bit self clears to O after completion of the above Once the port is configured and the VDEN bit is set the setting of other VDCTL bits except VDEN RSTCH and BLKDIS is prohibited and the display counters begin counting Data outputs are driven with default value blanking and control codes as appropriate and any control outputs are driven When the BLKDIS bit is cleared event generation may begin and FIFO data displayed SPRU629 Interrupt Operation 2 2 Interrupt Operation SPRU629 The video port can generate an interrupt to the DSP core after any of the follow ing events occur Capture complete CCMP bit is set Capture overrun COVR bit is set Synchronization byte error SERRX bit is set Vertical interrupt VINT xn bit is set Short field detect SFD bit is set Long field detect LFDx bit is set STC absolute time STC bit is set STC tick counter expired TICK bit is set Display complete DCMP bit is set Display underrun DUND bit is set Display complete not acknowledged DCNA bit is set GPIO interrupt GPIO bit is set O O O O O O C C O O O L The interrupt signal is a pulse only and does not hold state The interrupt pulse is generated only when the number of set flags in VPIS transitions from none to one or more Another interrupt pulse is not generated by setting additional flag bits Interrupts can be masked via the video port interrupt enable register VPIE using individu
110. CT VCBEVTCT 3 38 Video Capture Channel B Control Register VCBCTL 0 0ce eee eens 3 39 TSI Capture Control Register TSICTL 2 eean 3 40 TSI Clock Initialization LSB Register TSICLKINITL sssseeeeeeeennnn 3 41 TSI Clock Initialization MSB Register TSICLKINITM aaa 3 42 TSI System Time Clock LSB Register TSISTCLKL 000 cece eee eee 3 43 TSI System Time Clock MSB Register TSISTCLKM 00 0c eee eee eee 3 44 TSI System Time Clock Compare LSB Register TSISTCMPL 3 45 TSI System Time Clock Compare MSB Register TSISTCMPM 3 46 TSI System Time Clock Compare Mask LSB Register TSISTMSKL 3 47 TSI System Time Clock Compare Mask MSB Register TSISTMSKM 3 48 TSI System Time Clock Ticks Interrupt Register TSITICKS 005 4 1 NTSC Compatible Interlaced Display 000s cece eee eee teens 4 2 SMPTE 296M Compatible Progressive Scan Display eee eee eee 4 3 Interlaced Blanking Intervals and Video Areas 0c cece cence nett ene 4 4 Progressive Blanking Intervals and Video Area 2 0 cece a 4 5 Horizontal Blanking and Horizontal Sync Timing cece eects 4 6 Vertical Blanking Sync and Even Odd Frame Signal Timing LLuu 4 7 Video Display Module Synchronization Chain 60 000 c cece eee 4 8 BT 656 Output Sequence
111. CXSTOP2 bits 4 82 VSYNCYSTART1 bits VSYNCYSTART2 bits VSYNCYSTOP1 bits VSYNCYSTOP bits 4 82 VXS bit Y FIFO destination register A YDSTA 4 96 Y FIFO destination register B YDSTB 4 96 Y FIFO source register YSRCx Y C mode 3 12 4 16 blanking codes capture channels capture selection capturing video 3 44 displaying video field and frame operation FIFO overrun FIFO packing FIFO unpacking 4 17 image display image window and capture timing reference codes 3 12 H 16 YDEFVAL bits YDSTA YDSTB YSRCx SPRU629
112. DVBIT2 Field Descriptions Description Bit fieldt symvalt Value BT 656 and Y C Mode Raw Data Mode 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 VBITCLR2 OF value O FFFh Specifies the first line with an EAV of Not used V 0 indicating the start of field 2 active display 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 VBITSET2 OF value O FFFh Specifies the first line with an EAV of Not used V 1 indicating the start of field 2 vertical blanking t For CSL implementation use the notation VP VDVBIT2 field symval SPRU629 Video Display Port 4 93 Video Display Registers Recommended Values 4 13 Video Display Registers Recommended Values Sample recommended values decimal for video display registers for BT 656 output are given in Table 4 34 Table 4 34 Video Display Register Recommended Values Register Field 525 60 Value 625 50 Value VDFRMSZ FRMWIDTH 858 864 FRMHEIGHT 525 625 VDHBLNK HBLNKSTART 720 720 HBLNKSTOP 856 862 VDVBLKS1 VBLNKXSTART1 720t 720t VBLNKYSTART1 1t 6241 VDVBLKE1 VBLNKXSTOP1 7201 7201 VBLNKYSTOP1 20t 23t VDVBLKS2 VBLNKXSTART2 3601 3601 VBLNKYSTART2 2631 3111 VDVBLKE2 VBLNKXSTOP2 3601 3601 VBLNKYSTOP2 283t 3361 VDFLDT1 FLD1XSTART 7201 7201 FLD1YSTART 1t it VDFLDT2 FLD2XSTART 3601 3601 FLD2YSTART 263t 313t VDHSYNC HSYNCS
113. DVBLKE2 controls the end of vertical blanking in field 2 The VDVBLKE2 is shown in Figure 4 46 and described in Table 4 13 In raw data mode VBLNK is deasserted whenever the frame line counter FLCOUNT is equal to VBLNKYSTOP2 and the frame pixel counter FPCOUNT is equal to VBLNKXSTOP2 this is shown in Figure 4 6 page In BT 656 and Y C mode VBLNK is deasserted whenever FLCOUNT VBLNKYSTOP2 and FPCOUNT VBLNKXSTOP2 This VBLNK output control is completely independent of the timing control codes The V bit in the EAV SAV codes for field 2 is controlled by the VDVBIT2 register Figure 4 46 Video Display Field 2 Vertical Blanking End Register VDVBLKE2 31 R 0 28 27 16 VELNKYSTOR R W 0 11 0 15 12 VELNKXSTOP R 0 R W 0 Legend R Read only R W Read Write n value after reset SPRU629 Video Display Port 4 67 Video Display Registers Table 4 13 Video Display Field 2 Vertical Blanking End Register VDVBLKE2 Field Descriptions Description Bit fieldt symvalt Value BT 656 and Y C Mode Raw Data Mode 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 VBLNKYSTOP2 OF value O FFFh Specifies the line in Specifies the line in FLCOUNT where FLCOUNT where vertical VBLNK inactive edge blanking ends VBLNK occurs for field 2 Does inactive edge for field 2 not affect EAV SAV V bit operation 15 12 R
114. Delta module Write to the SDDIV register to set the divider value Sigma Delta inter polation frequency Video Capture Port 3 47 Capturing Data in TSI Capture Mode 6 Write to TSISTCMPL TSISTCMPM TSISTMSKL and TSISTMSKM if needed to initiate an interrupt based on STC absolute time 7 Write to TSITICKS if an interrupt is desired every x cycles of STC 8 Write to VPCTL to select TSI capture operation TSI 1 9 Writeto VPIEto enable overrun COVRA and capture complete CCMPA interrupts if desired 10 Write to VCACTL to set capture mode CMODE 010 11 Set VCEN bit in VCACTL to enable capture 12 Capture begins on the first VCLKINA rising edge when CAPENA and PACSTRT are valid A DMA event is generated as triggered by VCATHRLD1 When the entire packet has been captured DCOUNT VCYSTOP and VCXSTOP combined value the FRMC bit in VCASTAT is set causing the CCMP x bit in VPIS to be set This gener ates a DSP interrupt if CCMPx is enabled in VPIE 13 If continuous capture is enabled the video port begins capturing again on the next VCLKINA rising edge when CAPENA and PACSTRT are valid If noncontinuous capture is enabled the next data packet is captured during which the DSP must clear the FRMC bit or further capture is disabled If single frame capture is enabled capture is disabled until the DSP clears the FRMC bit 3 12 1 Handling FIFO Overrun Condition in TSI Capture Mode In case of a FIFO overr
115. FIFO Source Register A CBSRCA Cb FIFO Source Register A CRSRCA Cr FIFO Source Register A YSRCB Y FIFO Source Register B CBSRCB Cb FIFO Source Register B CRSRCB Cr FIFO Source Register B Table 3 35 Video Capture FIFO Registers Function Register YSRCx CBSRCx CRSRCx Capture Mode BT 656 or Y C Raw Data TSI Maps Y capture buffer into DSP memory Maps data capture buffer Maps data capture buffer into the DSP memory into the DSP memory Maps Cb capture buffer into DSP memory Not used Not used Maps Cr capture buffer into DSP memory Not used Not used SPRU629 In BT 656 or Y C capture mode three DMAs move data from the Y Cb and Cr capture FIFOs to the DSP memory by using the memory mapped YSRCx CBSRCx and CRSRCx registers The DMA transfers are triggered by the YEVT CbEVT and CrEVT events respectively In raw capture mode one DMA channel moves data from the Y capture FIFO to the DSP memory by using the memory mapped YSROx register The DMA transfers are triggered by a YEVT event The video port packs receive data into 64 bit words in the FIFO and the DMA should always move 64 bit wide data from YSRCx CBSRCx and CRSRCx to the memory Video Capture Port 3 83 Chapter 4 Video Display Port The video port peripheral can operate as a video capture port video display port or transport stream interface TSI capture port This chapter discusses the video display port Topic 44 Video Display Mode Sel
116. For CSL implementation use the notation VIC VICIN VICINBITS symval 6 8 VCXO Interpolated Control Port SPRU629 VIC Port Registers 6 5 3 VIC Clock Divider Register VICDIV The VIC clock divider register VICDIV defines the clock divider for the VIC interpolation frequency The VIC interpolation frequency is obtained by divid ing the module clock The divider value written to VICDIV is Divider Round DCLK R where DCLKis the CPU clock divided by 2 and Ris the desired interpolation frequency The interpolation frequency depends on precision p The default value of VICDIV is 0001h 0000h is an illegal value The VIC module uses a value of 0001h whenever 0000h is written to this register The DSP can write to VICDIV only when the GO bit in VICCTL is cleared to 0 If a write is performed when the GO bit is set to 1 the VICDIV bits remain unchanged The VICDIV is shown in Figure 6 5 and described in Table 6 6 Figure 6 5 VIC Clock Divider Register VICDIV 31 16 R 0 15 0 R W 0001h Legend R Read only R W Read Write n value after reset Table 6 6 VIC Clock Divider Register VICDIV Field Descriptions Bit Field symvalt Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 0 VICCLKDIV OF value O FFFFh The VIC clock divider bits define the clock divider for the VIC interpolation frequency t For CSL implementation
117. For true SMPTE 296M operation neither HBLNK nor HSYNC would be used The IPCOUNT operation follows the description in section 4 1 2 IPCOUNT resets to O at the first displayed pixel FRCOUNT IMGHOFF and stops counting at the last displayed pixel IPCOUNT IMGHSIZE The operation during nondisplay time is not a requirement it could continue counting until the next FPCOUNT IMGHOFFx point or it could reset immediately after IMGHSIZEx or when FPCOUNT is reset VDOUT shows the output data and switching between EAV Blanking Data SAV Default Data and FIFO Data It is assumed that the DVEN bit in VDCTL is set to enable the default output Video Display Port 4 43 vrV V Log Aejdsiq capi 629N4dS Figure 4 37 Y C Progressive Display Horizontal Timing Example sejduiex 3 Buwi Aejdsig vcLkiN MUTAN nn nn nnnnnnnnnn nnnn nnnn nj M 4H 362 rie 4H 1280 la One Line t Li FPCOUNT BREREERE SB RE BEBRSSPFMP heer SN N E vcoor BREREERS J RE SERSEERERS RHF SEER RERRRERR VCTL1 HBLNK f 73 LO ESTEE VCTL1 HSYNC t a vcukour UUULTTUUUU unnnnnnnnnnr unnnnnnnr uui
118. IC port register TSISTMSKM VIC clock divider register VICDIV TSI system time clock compare MSB register VIC control register VICCTL 6 6 TSISTCMPM VIC input register VICIN 6 8 TSI system time clock LSB register video capture TSISTCLKL Cb FIFO source register CBSRCx TSI system time clock MSB register channel A control register VCACTL TSISTCLKM channel A event count register TSI system time clock ticks interrupt register VCAEVTCT TSITICKS channel A field 1 start register Y FIFO source register YSRCx VCASTRT1 video display channel A field 1 stop register Cb FIFO destination register CBDST VCASTOP1 clipping register VDCLIP channel A field 2 start register control register VDCTL VCASTRT2 counter reload register VDRELOAD channel A field 2 stop register Cr FIFO destination register CRDST VCASTOP2 default display value register channel A status register VCASTAT VDDEFVAL channel A threshold register display event register VDDISPEVT VCATHRLD field 1 image offset register channel A vertical interrupt register VDIMGOFF1 VCAVINT field 1 image size register VDIMGSZ1 channel B control register VCBCTL field 1 timing register VDFLDT1 channel B event count register field 1 vertical blanking bit register VCBEVTCT VDVBIT1 channel B field 1 start register field 1 vertical blanking end register VCBSTRTI VDVBLKE1 channel B field 1 stop register field 1 vertical blanking start register VCBS
119. IFO is clocked indepen dently with the channel A FIFO receiving data from the VDIN 9 0 half of the bus and the channel B FIFO receiving data from the VDIN 19 10 half of the bus Each channel s FIFO is further split into Y Cb and Cr buffers with sepa rate write pointers and read registers YSRCx CBSRCx and CRSRC X Figure 1 2 BT 656 Video Capture FIFO Configuration Capture FIFO A Y Buffer A 1280 bytes a ae Cb Buffer A 640 bytes CBSRCA Cr Buffer A 640 bytes CRSRCA Capture FIFO B Y Buffer B 1280 bytes VDIN 19 10 Cb Buffer B 640 bytes CBSRCB Cr Buffer B 640 bytes CRSRCB 1 6 Overview SPRU629 Video Port FIFO For 8 10 bit raw video the FIFO is split into channel A and B as shown in Figure 1 3 Each FIFO is clocked independently with the channel A FIFO receiving data from the VDIN 9 0 half of the bus and the channel B FIFO receiving data from the VDIN 19 10 half of the bus Each channel s FIFO has a separate write pointer and read register YSRCx The FIFO configuration is identical for TSI capture but channel B is disabled Figure 1 3 8 10 Bit Raw Video Capture and TSI Video Capture FIFO Configuration Capture FIFOA VDIN 9 0 Buffer A 2560 bytes Capture FIFO B VDIN 19 10 Buffer B 2560 bytes SPRU629 Overview 1 7 Video Port FIFO For Y C video capture the FIFO is configured as a single channel split into sep arate Y Cb
120. INPCR symval 3 74 Video Capture Port SPRU629 Video Capture Registers 3 13 13 TSI Clock Initialization MSB Register TSICLKINITM The transport stream interface clock initialization MSB register TSICLKINITM is used to initialize the hardware counter to synchronize with the system time clock TSICLKINITM is shown in Figure 3 41 and described in Table 3 26 On receiving the first packet containing a program clock reference PCR header the DSP writes the most significant bit MSB of the PCR and the 9 bit PCR extension into TSICLKINITM This initializes the counter to the system time clock TSICLKINITM should also be updated by the DSP whenever a discontinuity in the PCR field is detected To ensure synchronization and prevent false compare detection the software should disable the system time clock interrupt clear the STEN bit in TSICTL prior to writing to TSICLKINITM All bits of the system time counter are initial ized whenever either TSICLKINITL or TSICLKINITM are written Figure 3 41 TSI Clock Initialization MSB Register TSICLKINITM 31 16 R 0 15 10 9 1 0 INPORE NPCRM R 0 R W 0 R W 0 Legend R Read only R W Read Write n value after reset Table 3 26 TSI Clock Initialization MSB Register TSICLKINITM Field Descriptions Description BT 656 Y C Mode Bit fieldt symvalt Value or Raw Data Mode TSI Mode 31 10 Reserved 0 Reserved The reserved bit location is always read as 0 A value w
121. IPOL9 PIPOL8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 PIPOL7 PIPOL6 PIPOL5 PIPOL4 PIPOL3 PIPOL2 PIPOL1 PIPOLO R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Legend R Read only R W Read Write n value after reset SPRU629 General Purpose I O Operation 5 21 GPIO Registers Table 5 11 Video Port Pin Interrupt Polarity Register PIPOL Field Descriptions Bit field 31 23 Reserved symvalt Value Description 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 22 PIPOL22 VCTLSACTHI VCTLSACTLO PIPOL22 bit determines the VCTL3 pin signal polarity that generates an interrupt Interrupt is caused by a low to high transition on the VCTL3 pin Interrupt is caused by a high to low transition on the VCTL3 pin 21 PIPOL21 VCTL2ACTHI VCTL2ACTLO PIPOL21 bit determines the VCTL2 pin signal polarity that generates an interrupt Interrupt is caused by a low to high transition on the VCTL2 pin Interrupt is caused by a high to low transition on the VCTL2 pin 20 PIPOL20 VCTL1ACTHI VCTL1ACTLO PIPOL20 bit determines the VCTL1 pin signal polarity that generates an interrupt Interrupt is caused by a low to high transition on the VCTL1 pin Interrupt is caused by a high to low transition on the VCTL1 pin 19 0 PIPOL 19 0 VDATAnACTHI VDATAnACTLO PIPOL 19 0 bit determines the corresponding VDATA n
122. IZE2 704 INCPIX 3 t Assumes VCT1P bit in VPCTL is set to 1 active low output HSYNC output when VCTL1S bit in VDCTL is set to 00 HBLNK output when VCTL1S bit is set 01 Diagram assumes a two VCLK pipeline delay between internal counters and output signals SPRU629 Display Timing Examples The vertical output timing for raw mode is shown in Figure 4 36 This example outputs the same 480 line window Note that the raw display mode is typically noninterlaced for output to a monitor This example shows the more complex interlaced case The active field 1 is 242 5 lines high and active field 2 is 242 5 lines high This example shows the 480 line image window centered in the screen This results in an IMGVOFF1 of 2 lines and an IMGVOFF2 of 3 lines and also results in a nondata half line at the end of field 1 and at the beginning of field 2 due to their noninteger line lengths The VBLNK and VSYNC signals are shown as they would be output for active low operation Note that only one of the two signals is actually available exter nally The VBLNK and VSYNC edges for field 1 occur at the end of an active line so their XSTART XSTOP values are set to 720 start of blanking For field 2 VBLNK and VSYNC edges occur during the middle of the active horizontal line so their XSTART XSTOP values are set to 360 The FLD output is setup to transition at the start of each analog field start of vertical blanking There is no EAV F bit in raw mode
123. If the VRST bit is cleared so the line counter begins counting at line 1 of the field the first EAV where V is 1 then the F bit still indi cates field 2 F 1 and needs to be inverted If the VRST bit is set to start counting lines beginning with the first active line the first EAV where V is 0 the F value will have already changed to indicate field 1 F 0 and no inver sion is necessary The field indicator method uses the FID input directly to determine the current field This is useful for Y C data streams that do not have embedded EAV and SAV codes The FID input is sampled at the start of each field If FID 0 then field 1 is starting if FID 1 then field 2 is starting The start of each field is defined by the VRST bit in VCxCTL and is either the start or end of vertical blanking as determined by the VBLNK input The FINV bit may be used in this method in systems where the FID input has the opposite polarity or where the field identification change lags the start of the field 3 24 Video Capture Port SPRU629 BT 656 and Y C Mode Field and Frame Operation The field detect method uses HYSNC and VSYNC based field detect logic This is used for BT 656 or Y C systems that provide only HSYNC and VSYNC The field detect logic samples the state of the HSYNC input on the VSYNC active edge If HSYNC is active on the active VSYNC edge then field 1 is detected if HSYNC is inactive on the active VSYNC edge then field 2 is detec ted
124. Interrupt is enabled 19 SERRB Channel B synchronization error interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled 18 CCMPB Capture complete on channel B interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled 17 COVRB Capture overrun on channel B interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled 16 GPIO Video port general purpose I O interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled 15 Reserved 0 Reserved The reserved bit location is always read as O A value written to this field has no effect 14 DCNA Display complete not acknowledged bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled 13 DCMP Display complete interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled 12 DUND Display underrun interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled 11 TICK System time clock tick interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled t For CSL implementation use the notation VP VPIE field symval 2 22 Video Port SPRU629 Video Port Control Registers Table 2 8 Video Port Interrupt Enable Register VPIE Field Descriptions Continued Bit fieldt symvalt Value Description 10 STC System time clock interrupt enable bit DISABLE 0 Interrupt is disabled
125. Itis applied only on the image areas defined by VDIMGSZn and VDIMGOFFn inside the active video area blanking values are not clipped VDCLIP allows output values to be clamped within the specified values The default values are the BT 601 specified peak black level of 16 and peak white level of 235 for luma and the maximum quantization levels of 16 and 240 for chroma For 10 bit operation the clipping is applied to the 8 MSBs ofthe value with the 2 LSBs cleared For example a Y value of FF 8h is clipped to EB Oh and a Y value of OF 4h is clipped to 10 0h Figure 4 61 Video Display Clipping Register VDCLIP 31 24 23 16 R W 1111 0000 R W 0001 0000 15 8 7 0 R W 1110 1011 R W 0001 0000 Legend R W Read Write n value after reset Table 4 28 Video Display Clipping Register VDCLIP Field Descriptions Description Bit fieldt symvalt Value BT 656 and Y C Mode Raw Data Mode 31 24 CLIPCHIGH OF value O FFh A Cb or Cr value greater than Not used CLIPCHIGH is forced to the CLIPCHIGH value 23 16 CLIPCLOW OF value O FFh A Cb or Cr value less than Not used CLIPCLOW is forced to the CLIPCLOW value 15 8 CLIPYHIGH OF value O FFh AY value greater than CLIPYHIGH is Not used forced to the CLIPYHIGH value 7 0 CLIPYLOW OF value O FFh AY value less than CLIPYLOW is Not used forced to the CLIPYLOW value t For CSL implementation use the notation VP_VDCLIP_field_symval SPRU629 Video Display Port 4 85 V
126. LKS1 VP_VDVBLKS1 vertical blanking VP RSETH vpDisplayHandle VDVBLKE1 VP VDVBLKE1 RMK VD VBLNK YSTOP1 VD VBLNK XSTOP1 Video Port Configuration Examples EIGHT VD FRM WIDTH VP VDHBLNK HBDLA NONE start for fieldl RMK VD VBLNK YSTART1 VD VBLNK XSTART1 end for fieldl x El 7 EA x x x E x s xy SPRU629 Example 2 Noncontinuous Frame Display for 525 60 Format set vertical blanking start for field2 VP RSETH vpDisplayHandle VDVBLKS2 VP VDVBLKS2 RMK VD VBLNK YSTART2 VD VBLNK XSTART2 set vertical blanking end for field2 VP RSETH vpDisplayHandle VDVBLKE2 VP VDVBLKE2 RMK VD VBLNK YSTOP2 VD VBLNK XSTOP2 set vertical blanking bit register for field 1 VD_VBIT1 VP RSETH vpDisplayHandle VDVBIT1 VP VDVBIT1 RMK VD VBIT CLR1 VD VBIT SET1 set vertical blanking bit register for field 2 VD VBIT2 VP RSETH vpDisplayHandle VDVBIT2 VP VDVBIT2 RMK VD VBIT CLR2 VD VBIT SET2 No image offsets in this example Bf set image size for fieldl VP RSETH vpDisplayHandle VDIMGSZ1 VP VDIMGSZ1 RMK VD IMG VSIZEl1 VD IMG HSIZE1 set image size for field2 VP RSETH vpDisplayHandle VDIMGSZ2 VP VDIMGSZ1 RMK VD IMG VSIZE2 VD IMG HSIZE2 set fieldl timing x VP RSETH vpDisplayHandle VDFLDT1 VP VDFLDT1 RMK VD FIELD1 YSTART VD FIELD1 XSTART
127. NC data before the SAV code is desired HMode 1 is the default mode and corresponds to most digital video standards by making the first active pixel pixelO It has the effect of associating horizontal blanking periods with the end of the previous line rather than the beginning of the line but this is only an issue if you try to capture HANC data In either mode HCOUNT increments on every VCLKIN edge for Y C operation and on every other VCLKIN edge for BT 656 operation but only when CAPEN is active HCOUNT operation for HMode 0 and HMode 1 is shown in Figure 3 9 HMode 2 and HMode 3 are used for BT 656 or Y C capture without embedded EAV SAV code and allow alignment with either the beginning of the horizontal blanking period or the first active pixel or the beginning or end of horizontal sync depending on the VCTL1 input When VCTL1 is configured as a horizontal control input no external CAPEN signal is available so the CAPEN signal is considered to always be active HCOUNT operation for HMode 3 and HMode 4 is shown in Figure 3 10 for VCTL1 operating as either HSYNC or AVID Port SPRU629 BT 656 and Y C Mode Field and Frame Operation Figure 3 9 HCOUNT Operation Example EXC 0 vew nnnnnnn gaunnmunnunnu uunnnlnt U H 4 268 bai s
128. O into DSP memory In some cases color separation is performed on the incoming video data requiring multiple FIFOs and DMAs to be used The video port enables capture of both interlaced and progressive scan data Interlaced capture can be performed on either a field by field or a frame by frame basis A capture window specifies the data to be captured within each field Frame and field synchronization can be performed using embedded sync codes or configurable control inputs allowing glueless interface to various encoders and ADCs Topic 3 4 Video Capture Mode Selection 3 2 BT 656 Video Capture Mode eeeeeeeeeeeeeeee 3 3 Y C Video Capture Mode 7 2 212 e ae Ee ea ea E 3 4 BT 656 and Y C Mode Field and Frame Operation 3 5 Video Input Filtering 22 9 3 6 Ancillary Data Capture 222220 3 7 Raw Data Capture Mode 2222220 3 8 aT SI Gapture M0de AA AA NA AP EE 3 9 Capture Line Boundary Conditions LLuuuuuee 3 10 Capturing Video in BT 656 or Y C Mode 3 11 Capturing Video in Raw Data Mode 3 12 Capturing Data in TSI Capture Mode 3 13 Video Capture Registers 2222 3 14 Video Capture FIFO Registers 0 ccceeee ee eee eee 3 1 Video Capture Mode Selection 3 4 Video Cap
129. O Registers Function Display Mode Register BT 656 or Y C Raw Data YDSTx Maps Y display FIFO into the Maps data display buffer into DSP memory the DSP memory CBDST Maps Cb display FIFO into the Not used DSP memory CRDST Maps Cr display FIFO into the Not used DSP memory In BT 656 or Y C display mode three DMAs move data from the DSP memory to Y Cb and Cr display FIFOs by using the memory mapped YDSTx CBDST and CRDST registers The DMA transfers are triggered by the YEVT CbEVT and CrEVT events respectively In raw display mode one DMA channel moves data from the DSP memory to the Y display FIFO by using the memory mapped YDSTx register The DMA transfers are triggered by a YEVT event The video display FIFO registers are write only locations Reads of these addresses returns arbitrary values and do not affect the status of the display FIFOs 4 96 Video Display Port SPRU629 Chapter 5 General Purpose I O Operation Signals not used for video display or video capture can be used as general purpose input output GPIO signals Topic Page Eu GPIO Registers i AA qM Peers 52 5 1 GPIO Registers 5 1 GPIO Registers The GPIO register set includes required registers such as peripheral identifi cation and emulation control The GPIO registers are listed in Table 5 1 See the device specific datasheet for the memory address of these registers Table 5 1 Video Port Registers Acronym VPPID
130. OPT_2DD_NO EDMA_OPT_DUM_NONE EDMA OPT TCINT YES pa EDMA OPT TCC OF tcc amp OxF EDMA OPT TCCM OF tcc amp 0x30 4 EDMA OPT ATCINT NO EDMA OPT ATCC OF 0 EDMA OPT PDTS DISABLE EDMA OPT PDTD DISABLE EDMA OPT LINK NO EDMA OPT FS NO ft EDMA SRC RMK srcAddr DMA CNT RMK EDMA_CNT_FRMCN EDMA CNT ELECN EDMA_DST_RMK dstAddr EDMA IDX RMK EDMA IDX FR EDMA IDX ELEIDX OF 0 no RLD in 2D and no linking ERLD EDMA RLD RMK EDMA RLD EL Video Port Configuration Examples OF 0 EDMA RID LINK OF 0 x x x7 t wy x f xy EL SPA ay Ry x ey 5j dA KY SPRU629 ancillary data capture ancillary data display architecture 1 3 ATC bit in TSISTCMPL in TSISTCMPM ATCM bit in TSISTMSKL in TSISTMSKM 3 81 BLKCAP bit in VCACTL 3 53 in VCBCTL 3 68 BLKDIS bit block diagrams 16 20 bit raw video capture FIFO configuration re 16 20 bit raw video display FIFO configuration 8 10 bit locked raw video display FIFO configuration 8 10 bit raw video capture FIFO configuration 17 8 10 bit raw video display FIFO configuration BT 656 video capture FIFO configuration BT 656 video display FIFO configuration system time clock counter TSI system TSI video capture FIFO configuration 1 7 VIC port video port Y C video capture FIFO configuration 1 8 Y C video display FIFO configuration SPRU629 Index boundary condition
131. Output Filtering 4 4 2 Chrominance Resampling Operation Chrominance resampling computes chrominance values at sample points corresponding to output luminance samples based on the input interspersed chrominance samples This filter performs the conversion between inter spersed YCbCr 4 2 2 format and co sited YCbCr 4 2 2 format The vertical portion of the conversion from YCbCr 4 2 0 to interspersed YCbCr 4 2 2 must be performed in software The chrominance resampling filters calculate the implied value of Cb and Cr co sited with luminance sample points based upon nearby interspersed Cb and Cr samples The resulting values are clamped to between 01h and FEh before being output Chrominance resampling is shown in Figure 4 19 Figure 4 19 Chrominance Resampling YCbCr 4 2 2 interspersed SO YO O Ac ad SO source pixels YCbCr 4 2 2 co sited e KG O O O output results O Luma Y XC Chroma Cb Cr E Cb t SCbap 33Cbeg 101Cber 3Cbgh 128 sample samples Cr 3Crgh 33Crcg 101Cref 3Crgh 128 4 4 3 Scaling Operation The 2x scaling mode is used to double the horizontal resolution of output luminance and chrominance data This allows processed CIF resolution images to be output at full size Vertical scaling must be performed in software Scaling for co sited source is shown in Figure 4 20 and scaling for interspersed source is shown in Figure 4 21 For a co sited source the source luminance pixels are output un
132. PDIR10 VDATA10TO11IN VDATA10TO11OUT PDIR10 bit controls the direction of the VDATA 11 10 pins Pins function as input Pins function as output 9 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect t For CSL implementation use the notation VP PDIR field symval SPRU629 General Purpose O Operation 5 9 GPIO Registers Table 5 5 Video Port Pin Direction Register PDIR Field Descriptions Continued Bit field symvalt Value Description 8 PDIR8 PDIRSG bit controls the direction of the VDATA 9 8 pins VDATA8TO9IN 0 Pins function as input VDATA8TO9OUT 1 Pins function as output 7 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 4 PDIR4 PDIR4 bit controls the direction of the VDATA 7 4 pins VDATA4TO7IN 0 Pins function as input VDATA4TO7OUT 1 Pins function as output 3 1 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 PDIRO PDIRO bit controls the direction of the VDATA 3 0 pins VDATAOTOSIN 0 Pins function as input VDATAOTO30UT 1 Pins function as output t For CSL implementation use the notation VP_PDIR_field_symval 5 10 General Purpose I O Operation SPRU629 GPIO Registers 5 1 5 Video Port Pin Data Input Register PDIN The read only video port pin data input register PDIN is shown
133. PEVT1 bits 4 84 DISPEVT2 bits display channel reset display line boundary conditions display selection video display mode displaying video BT 656 mode raw data mode Y C mode DMA operation DMODE bits DPK DUND bit in VPIE in VPIS DVEN ENSTC bit ERRFILT bit examples noncontinuous frame capture for 525 60 format noncontinuous frame display for 525 60 format EXC bit KS N ine me SPRU629 F1C bit F1D bit F2C bit F2D bit FBITCLR bits FBITSET bits FIFO overrun BT 656 mode raw data mode TSI capture mode Y C mode FIFO packing BT 656 mode raw data mode TSI capture mode Y C mode FIFO unpacking BT 656 mode raw data mode Y C mode FINV bit in VCACTL in VCBCTL FLD1XSTART bits 4 74 FLD1YSTART bits FLD2XSTART bits FLD2YSTART bits 4 75 FLDD bit FRAME bit in VCACTL in VCBCTL FREE bit FRMC bit FRMD bit FRMHEIGHT bits FRMWIDTH bits FSCL2 bit FSYNC bit FXS bit SPRU629 Index GO bit GPIO bit in VPIE in VPIS GPIO registers HBDLA bit HBLNKSTART bits HBLNKSTOP bits HIDATA bit HRLD bits HRST bit in VCACTL in VCBCTL HSYNCSTART bits HSYNCSTOP bits HXS bit IMGHOFF1 bits IMGHOFF bits IMGHSIZE1 bits IMGHSIZE2 bits IMGVOFF1 bits IMGVOFF2 bits IMGVSIZE1 bits IMGVSIZE2 bits INCPIX bits INPCR bits INPCRE bits INPCRM bit interrupt operation LFDA bit in VPIE in VPIS LFDB bit in VPIE in VPIS I
134. PRU629 Eight bit parallel data is received on the input data bus Data is captured on the rising edge of VCLKIN The data consists typically of 188 byte packets with the first byte a SYNC byte also called a preamble The capture packet length is determined by the value of VCASTOP Data on the data bus is considered valid and captured only when the CAPEN signal is active TSI data capture begins with a SYNC byte as indicated by PACSTRT and CAPEN active The SYNC byte may have any value Data is captured on each VCLK rising edge when CAPEN is active until the entire packet has been captured irrespective of additional PACSTRT transitions The end of packet condition occurs when the 24 bit capture byte counter as reflected by the VCYPOS and VCXPOS bits of VCASTAT equals the value in the VCYSTOP and VCXSTOP bits of VCASTOP The captured data includes both SYNC byte and the data payload as shown in Figure 3 22 After a packet is captured the video port waits for the next active PACSTRT to begin capture of another packet Received packet data is packed into 64 bits before being written to the FIFO Video Capture Port 3 37 TSI Capture Mode Figure 3 22 Parallel TSI Capture vik LJ LT LT LT LT LIL caen Na S PACSTRT N VDIN 9 2 LZ Sync ByieX Byte X Bye X Bye3 KZ Byte4 Start Capture T 3 8 3 TSI Capture Error Detection The video port checks for two types of errors during TSI capture The first is a packet err
135. Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 VINT2 OF value O FFFh Line that vertical interrupt Not used Not used occurs if VIF2 bit is set 15 VIF1 Setting of VINT in field 1 enable bit DISABLE 0 Setting of VINT in field 1 is Not used Not used disabled ENABLE 1 Setting of VINT in field 1 is Not used Not used enabled 14 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 VINTI OF value O FFFh Line that vertical interrupt Not used Not used occurs if VIF1 bit is set t For CSL implementation use the notation VP VCXVINT field symval 3 64 Video Capture Port SPRU629 Video Capture Registers 3 13 8 Video Capture Channel x Threshold Register VCATHRLD VCBTHRLD SPRU629 The video capture channel x threshold register VCATHRLD VCBTHRLD determines when DMA requests are sent VCxTHRLD is shown in Figure 3 36 and described in Table 3 21 The VCTHRLD1 bits determine when capture DMA events are generated Once the threshold is reached generation of further DMA events is disabled until service of the previous event s begins the first FIFO read by the DMA occurs In BT 656 and Y C modes every two captured pixels represent 2 luma values in the Y FIFO and 2 chroma values 1 each in the Cb and Cr FIFOs Depend ing on the data size and packing mode each value may be a byte 8 bit BT 656 or Y C h
136. SETH vpCaptureHandle VCACTL FRAME VP VCACTL FRAME FRMCAP VP FSETH vpCaptureHandle VCACTL CF2 VP VCACTL CF2 NONE VP FSETH vpCaptureHandle VCACTL CF1 VP VCACTL CF1 NONE Let FDD and FINV to be their defaults f Set VRST to end of vertical blanking VP FSETH vpCaptureHandle VCACTL VRST VP VCACTL VRST VOEAV Set HRST to start of horizontal blanking VP FSETH vpCaptureHandle VCACTL HRST VP VCACTL HRST OF 0 10 bit pack mode 10BPK bit in this 8 bit example No 1 2 scaling and no chroma re sampling in this example 7 Enable video port interrupts IRQ enable vpCaptureHandle gt eventId Setup Y Cb and Cr EDMA channels SetupVPCapChaAEDMA portNumber Clear VPHLT in VP CTL to make video port function VP FSETH vpCaptureHandle VPCTL VPHLT VP VPCTL VPHLT CLEAR SPRU629 Video Port Configuration Examples A 5 Example 1 Noncontinuous Frame Capture for 525 60 Format xy enable capture yos x set VCEN bit to enable capture Ki VP FSETH vpCaptureHandle VCACTL VCEN VP VCACTL VCEN ENABLE clear BLKCAP in VCA CTL to enable capture DMA events x VP FSETH vpCaptureHandle VCACTL BLKCAP VP VCACTL BLKCAP CLEAR Jer AY Function VPCapChaAIsr E Description This capture ISR clears FRMC to continue capture HE in this non continuous mode and also clears other status bits LEA
137. SMPTE 260M SMPTE 274M SMPTE 296M ITU BT 1120 etc YCbCr 4 2 0 to YCbCr 4 2 2 horizontal conversion and 2x scaling of output in 8 bit 4 2 2 modes Programmable clipping of BT 656 and Y C mode output values One channel of raw data output up to 20 bits for interface to RAM DACs Two channel synchronized raw data output Synchronizes to external video controller or another video display port Using the external clock the frame timing generator provides programmable image timing including horizontal and vertical blank ing start of active video SAV and end of active video EAV code insertion and horizontal and frame timing pulses Generates horizontal and vertical synchronization and blanking signals and a frame synchronization signal SPRU629 SPRU629 Video Port TSI capture mode Transport stream interface TSI from a front end device such as demodulator or forward error correction device in 8 bit parallel format at up to 30 Mbytes sec Theportgenerates up to three events per channel and one interruptto the DSP A high level block diagram of the video port is shown in Figure 1 1 The port consists of two channels A and B A 5120 byte capture display buffer is split table between the two channels The entire port both channels is always configured for either video capture or display only Separate data pipelines control the parsing and formatting of video capture or display data for each of the BT 656 Y C
138. SPRU629 Video Capture Port 3 73 Video Capture Registers 3 13 12 TSI Clock Initialization LSB Register TSICLKINITL The transport stream interface clock initialization LSB register TSICLKINITL is used to initialize the hardware counter to synchronize with the system time clock TSICLKINITL is shown in Figure 3 40 and described in Table 3 25 On receiving the first packet containing a program clock reference PCR and the PCR extension value the DSP writes the 32 least significant bits LSBs of the PCR into TSICLKINITL This initializes the counter to the system time clock TSICLKINITL should also be updated by the DSP whenever a disconti nuity in the PCR field is detected To ensure synchronization and prevent false compare detection the software should disable the system time clock interrupt clear the STEN bit in TSICTL prior to writing to TSICLKINITL All bits of the system time counter are initial ized whenever either TSICLKINITL or TSICLKINITM are written Figure 3 40 TSI Clock Initialization LSB Register TSICLKINITL 31 0 INPCR R W 0 Legend R W Read Write n value after reset Table 3 25 TSI Clock Initialization LSB Register TSICLKINITL Field Descriptions Description BT 656 Y C Mode Bit Field symvalt Value or Raw Data Mode 31 0 INPCR OF value O FFFFFFFFh Not used TSI Mode Initializes the 32 LSBs of the System time clock T For CSL implementation use the notation VP TSICLKINITL
139. SS Identifies class of peripheral OF value 09h Video 7 0 REVISION Identifies revision of peripheral OF value X See the device specific datasheet for the value t For CSL implementation use the notation VP_VPPID_field_symval SPRU629 General Purpose I O Operation 5 3 GPIO Registers 5 1 2 Video Port Peripheral Control Register PCR The video port peripheral control register PCR determines operation during emulation The video port peripheral control register is shown in Figure 5 2 and described in Table 5 3 Normal operation is to not halt the port during emulation suspend This allows a displayed image to remain visible during suspend However this will only work if one of the continuous capture display modes is selected because non continuous modes require CPU intervention for DMAs to continue indefinitely and the CPU is halted during emulation suspend When FREE 0 emulation suspend can occur Clocks and counters continue to run in order to maintain synchronization with external devices The video port waits until a field boundary to halt DMA event generation so that upon restart the video port can begin generating events again at the precise point it left off After exiting suspend the video port waits for the correct field bound ary to occur and then reenables DMA events The DMA pointers will be at the correct location for capture display to resume where it left off The emulation suspend operation is similar to the
140. STOP2 set the VCXSTOP and VCYSTOP bits 2 Set the first pixel to be captured in VCXSTRT1 and VCxSTRT42 set the VCXSTART and VCYSTART bits 3 Write to VCXTHRLD to set the capture threshold Every time the number of received pixels reaches the number specified by the VCTHRLD1 bits a YEVTx CbEVTx and CrEVTx are generated by the video capture module The VCTHRLD 1 bits value must be an even number 4 Configure a DMA channel to move data from YSROx to a destination in the DSP memory The channel transfers should be triggered by the YEVTx The size of the transfers should be set to VCTHRLD1 4 for 8 bit mode VCTHRLD1 2 for 10 bit mode or VCTHRLD1 3 for dense 10 bit mode This is because 4 2 or 3 pixels are packed per FIFO word and the DMA is moving 32 bit words from YSRCx to the memory The DMA must start on a doubleword boundary and move an even number of words 5 Configure a DMA channel to move data from CBSRCx to a destination in the DSP memory The channel transfers should be triggered by the CbEVTx The size of the transfers should be set to VCTHRLD1 8 for 8 bit mode VCTHRLD1 4 for 10 bit mode or VCTHRLD1 6 for dense 10 bit mode This is because 4 2 or 3 pixels are packed per FIFO word the DMA is moving 32 bit words from CBSRCx to the memory and there are half the number of pixels in the Cb FIFO as in the Y FIFO The DMA must start on a doubleword boundary and move an even number of words 6 Configure a DMA channel to m
141. SYNCYSTOP1 and frame pixel counter VSYNCXSTOP1 values for the pixel where vertical synchronization ends for field 1 Set the vertical synchronization start for field 2 in VDVSYNS2 Specify the frame line VSYNCYSTART2 and frame pixel counter VSYNCXSTART2 values for the pixel where vertical synchronization starts for field 2 10 Set the vertical synchronization end for field 2 in VDVSYNE2 Specify the SPRU629 frame line VSYNCYSTOP2 and frame pixel counter VSYNCXSTOP2 values for the pixel where vertical synchronization ends for field 2 Video Display Port 4 49 Displaying Video in Raw Data Mode 11 Set the horizontal synchronization in VDHSYNC Specify the frame pixel counter value for a pixel where HSYNC gets asserted HSYNCYSTART and width of the HSYNC pulse HSYNCSTOP in frame pixel clocks 12 Setthe video display field 1 timing Specify the first line and pixel of field 1 in VDFLDT1 13 Set the video display field 2 timing Specify the first line and pixel of field 2 in VDFLDT2 14 Configure a DMA to move data from table in the DSP memory to YDSTA memory mapped display FIFO The transfers should be triggered by the YEVT 15 Set DISPEVT1 and DISPEVT2 bits in VDDISPEVT Event count is total doublewords per field divided by total doublewords per Y DMA 16 Write to VPIE to enable underrun DUND and display complete DCMP interrupts if desired 17 Write to VDTHRLD to setthe display FIFO threshold VDTHRLD
142. TART 736 732 HSYNCSTOP 800 782 VDVSYNS1 VSYNCXSTART1 7201 7201 VSYNCYSTART1 4t it VDVSYNE1 VSYNCXSTOP1 7201 3601 VSYNCYSTOP1 7t 3t t Programming only required if external control signal is used 4 94 Video Display Port SPRU629 Video Display Registers Recommended Values Table 4 34 Video Display Register Recommended Values Continued Register Field 525 60 Value 625 50 Value VDVSYNS2 VSYNCXSTART2 3601 3601 VSYNCYSTART2 2661 313t VDVSYNE2 VSYNCXSTOP2 360t 720t VSYNCYSTOP2 269t 316t VDFBIT FBITCLR 4 1 FBITSET 266 313 VDVBIT1 VBITSET1 1 624 VBITCLR1 20 23 VDVBIT2 VBITSET2 264 311 VBITCLR2 283 336 t Programming only required if external control signal is used SPRU629 Video Display Port 4 95 Video Display FIFO Registers 4 14 Video Display FIFO Registers The display FIFO mapping registers are listed in Table 4 35 These registers provide DMA write access to the display FIFOs These pseudo registers should be mapped into DSP memory space rather than configuration register space in order to provide high speed access See the device specific data sheet for the memory address of these registers The function of the video display FIFO mapping registers is listed in Table 4 36 Table 4 35 Video Display FIFO Registers Acronym Register Name YDSTA Y FIFO Destination Register A CBDST Cb FIFO Destination Register CRDST Cr FIFO Destination Register YDSTB Y FIFO Destination Register B Table 4 36 Video Display FIF
143. THRLD2 in VCXTHRLD to use in event generation and in the outgoing data counter Once the CAPEVTCTn number of events have been generated the DMA logic switches to the other threshold value See section 2 3 1 Figure 3 37 Video Capture Channel x Event Count Register VCAEVTCT VCBEVTCT 31 28 27 16 R 0 R W 0 15 12 11 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 3 22 Video Capture Channel x Event Count Register VCxEVTCT Field Descriptions Description Bit fieldt symvalt Value BT 656 or Y C Mode Raw Data Mode TSI Mode 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 CAPEVTCT2 OF value O FFFh Number of DMA event Not used Not used sets YEVT CbEVT CrEVT to be generated for field 2 capture 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 CAPEVTCT1 OF value O FFFh Number of DMA event Not used Not used sets YEVT CbEVT CrEVT to be generated for field 1 capture t For CSL implementation use the notation VP VCxEVTCT CAPEVTCTn symval SPRU629 Video Capture Port 3 67 Video Capture Registers 3 13 10 Video Capture Channel B Control Register VCBCTL Video capture is controlled by the video capture channel B control register VCBCTL shown in Figure 3 38 and described in Table 3 23 Fig
144. TL2CLR 1 Clears PISTAT21 VCTL2 bit to 0 20 PICLR20 Allows PISTAT20 bit to be cleared to a logic low NONE 0 No effect VCTL1CLR 1 Clears PISTAT20 VCTL1 bit to O 19 0 PICLR 19 0 Allows PISTAT 19 0 bit to be cleared to a logic low NONE 0 No effect VDATAnCLR 1 Clears PISTAT n VDATA n bit to 0 T For CSL implementation use the notation VP_PICLR_PICLRn_symval 5 26 General Purpose I O Operation SPRU629 Chapter 6 VCXO Interpolated Control Port This chapter provides an overview ofthe VCXO interpolated control VIC port Topic Page GA OV EIVIGW os ccc en c E uem AA 6 2 G2 wintentace Sco eccL E a e cT eS 16 3 6 37 Operational Detalls AA NA 6 3 64 Enabling VIG Pon AA AA AA edd 16 5 6 5 VIC Por Registers 0 5 20905200 Somes a ee 16 5 6 1 Overview 6 4 Overview The VCXO interpolated control VIC port provides single bit interpolated VCXO control with resolution from 9 bits to up to 16 bits The frequency of inter polation is dependent on the resolution needed When the video port is used in transport stream interface TSI mode the VIC port is used to control the system clock VCXO for MPEG transport stream Figure 6 1 The VIC port supports following features Single bit interpolated VCXO control Programmable precision from 9 to 16 bits Figure 6 1 TSI System Block Diagram 6 2 VCXO Interpolated Control Port VDATA 7 0 TSI data in
145. TMS320C64x DSP Video Port VCXO Interpolated Control VIC Port Reference Guide Literature Number SPRU629 pril 3 35 TEXAS INSTRUMENTS IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each productis not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right
146. TOP1 VDVBLKS1 channel B field 2 start register field 1 vertical synchronization end register VCBSTRT2 VDVSYNE1 channel B field 2 stop register field 1 vertical synchronization start register VCBSTOP2 VDVSYNS1 channel B status register VCBSTAT field 2 image offset register channel B threshold register VDIMGOFF2 VCBTHRLD field 2 image size register VDIMGSZ2 channel B vertical interrupt register field 2 timing register VDFLDT2 VCBVINT field 2 vertical blanking bit register Cr FIFO source register CRSRCx VDVBIT2 FIFO field 2 vertical blanking end register TSI clock initialization LSB register VDVBLKE2 TSICLKINITL field 2 vertical blanking start register TSI clock initialization MSB register VDVBLKS2 TSICLKINITM field 2 vertical synchronization end register TSI control register TSICTL VDVSYNE2 TSI system time clock compare LSB register field 2 vertical synchronization start register TSISTCMPL VDVSYNS2 TSI system time clock compare mask LSB field bit register VDFBIT register TSISTMSKL FIFO SPRU629 Index 5 Index registers continued video display frame size register VDFRMSZ horizontal blanking register VDHBLNK horizontal synchronization register VDHSYNC recommended values status register VDSTAT threshold register VDTHRLD vertical interrupt register VDVINT Y FIFO destination register A YDSTA Y FIFO destination register B YDSTB video port control register VPCTL interr
147. TSI Mode 31 FSYNC Current frame sync bit CLEARD 0 VCOUNT VINT1 or Not used Not used VINT2 as selected by the FSCL2 bit in VCXVINT SET 1 VCOUNT 1 Not used Not used in field 1 30 FRMC Frame data captured bit Write 1 to clear the bit a write of 0 has no effect NONE 0 Complete frame has Complete data Entire data packet not been captured block has not has not been been captured captured CAPTURED 1 Complete frame has Complete data Entire data packet CLEAR been captured block has been has been captured captured 29 F2C Field 2 captured bit Write 1 to clear the bit a write of O has no effect NONE 0 Field 2 has not been Not used Not used captured CAPTURED 1 Field 2 has been Not used Not used CLEAR captured 28 F1C Field 1 captured bit Write 1 to clear the bit a write of O has no effect NONE 0 Field 1 has not been Not used Not used captured CAPTURED 1 Field 1 has been Not used Not used CLEAR captured t For CSL implementation use the notation VP VCxSTAT field symval SPRU629 Video Capture Port 3 51 Video Capture Registers Table 3 14 Video Capture Channel x Status Register VCxSTAT Field Descriptions Continued Description Bit fieldt symvalt Value BT 656 or Y C Mode Raw Data Mode TSI Mode 27 16 VCYPOS OF value O FFFh Current VCOUNT Upper 12 bits of Upper 12 bits of value and the line the data counter the data counter that is currently being received within th
148. TSI clock initialization LSB register TSICLKINITL TSI clock initialization MSB register TSICLKINITM TSI system time clock compare LSB register TSISTCMPL TSI system time clock compare mask LSB register TSISTMSKL TSI system time clock compare mask MSB register TSISTMSKM TSI system time clock compare MSB register TSISTCMPM TSI system time clock LSB register TSISTCLKL TSI system time clock MSB register TSISTCLKM TSI system time clock ticks interrupt register TSITICKS TSICLKINITL TSICLKINITM TSIGTL TSISTCLKL 3 TSISTCLKM 3 TSISTCMPL 3 TSISTCMPM TSISTMSKL 3 8 TSISTMSKM 3 81 TSITICKS 3 82 TYPE bits VBITCLR1 bits VBITCLR2 bits VBITSET1 bits VBITSET2 bits 4 92 VBLNK bit VBLNKXSTART1 bits VBLNKXSTART2 bits VBLNKXSTOP1 bits VBLNKXSTOP2 bits VBLNKYSTART1 bits VBLNKYSTART2 bits 4 66 VBLNKYSTOP1 bits 4 64 Co er sull Ole NI R SPRU629 Index VBLNKYSTOP2 bits VCASTAT VCASTOP1 VCASTOP2 VCASTRT1 VCAVINT VCBCTL VCBSTOP1 VCBSTOP2 VCBSTRT1 VCBSTRT2 VCBTHRLD VCBVINT VCEN bit in VCACT in VCBCT VCFLD bit VCLK2P bit VCTIP bit VCT2P bit rr VCTL2S bits VCTLSS bits VCXO interpolated control VIC port registers VCXPOS bits VCXSTART bits in VOXSTRT1 3 58 in VCxSTRT2 3 61 VCXSTOP bits in VCxSTOP1 3 60 in VCxSTOP2 3 62 VCYSTART bits in VCxSTRT1 3 5 in VCxSTRT2 3 6 VCYSTOP bits in VOXSTOP1 13 60 in VCxSTOP2 3 62 Index 7 Ind
149. The capture logic must sync to the start of the next frame after BLKCAP is cleared BLOCK Blocks DMA events and flushes the capture channel FIFOs 29 22 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 21 RDFE Field identification enable bit Channel A only DISABLE Not used Field identification Not used is disabled ENABLE Not used Field identification Not used is enabled 20 FINV Detected field invert bit FIELD1 Detected 0 is field 1 Not used Not used FIELD2 Detected 0 is field 2 Not used Not used 19 EXC External control select bit Channel A only EAVSAV Use EAV SAV codes Not used Not used EXTERN Use external control Not used Not used signals t For CSL implementation use the notation VP_VCACTL_field_symval For complete encoding of these bits see Table 3 6 Table 3 11 and Table 3 12 3 54 Video Capture Port SPRU629 Video Capture Registers Table 3 15 Video Capture Channel A Control Register VCACTL Field Descriptions Continued Description Bit fieldt symvalt Value BT 656 or Y C Mode Raw Data Mode TSI Mode 18 FLDD Field detect method bit Channel A only EAVFID 0 18t line EAV or FID Not used Not used input FDL 1 Field detect logic Not used Not used 17 VRST VCOUNT reset method bit V1EAV 0 Start of vertical blank Not used Not used st V 1 EAV or VCTL2 active edge VOEAV 1 End of
150. U LU LU u VDOUT 9 2 VDOUT 19 12 63 5655 4847 4039 3231 2423 1615 87 0 Y31 Y 30 Y29 Y 28 Y27 Y 26 Y 25 Y 24 Y 23 Y 22 Y 21 Y 20 Y 19 Y 18 Y 17 Y 16 Y 15 Y 14 Y 13 Y 12 Y 11 Y 10 Y9 Y8 Y FIFO Y7 Y6 Y5 Y4 Y3 Y2 Y1 YO 63 5655 4847 4039 3231 2423 1615 87 0 Cb 15 Cb 14 Cb 13 Cb 12 Cb 11 Cb 10 Cb9 Cb8 Cb FIFO Cb7 Cb6 Cb5 Cb4 Cb3 Cb2 Cb 1 Cb 0 63 5655 4847 4039 3231 2423 1615 87 0 Cr15 Cr14 Cr 13 Cr 12 Cr 11 Cr 10 Cr9 Cr 8 Cr FIFO Cr7 Cr 6 Cr 5 Cr4 Cr3 Cr2 Cr1 Cro Little Endian Unpacking 63 5655 4847 4039 3231 2423 1615 87 0 Y 24 Y 25 Y 26 Y 27 Y 28 Y 29 Y 30 Y 31 Y 16 Y17 Y 18 Y 19 Y 20 Y 21 Y22 Y 23 Y8 Y9 Y 10 Y11 Y12 Y13 Y14 Y15 Y FIFO YO Yi Y2 Y3 Y4 Y5 Y6 Y7 63 5655 4847 4039 3231 2423 1615 87 0 1 Cb8 Cb9 Cb 10 Cb11 Cb12 Cb 13 Cb 14 Cb 15 Cb FIFO Cb0 Cb 1 Cb2 Cb3 Cb4 Cb5 Cb6 Cb7 63 5655 4847 4039 3231 2423 1615 87 0 Cr8 Cr9 Cr 10 Cr 11 Cr 12 Cr 13 Cr 14 Cr 15 Cr FIFO Cro Cr 1 Cr2 Cr3 Cr4 Cr 5 Cr 6 Cr7 Big Endian Unpacking 4 18 Video Display Port SPRU629 Y C Video Display Mode For 10 bit operation two samples are unpacked from each FIFO word This is shown in Figure 4 17 Figure 4 17 10 Bit Y C FIFO Unpacking VDOUT 9 0 VDOUT 19 10 63 5857 4847 4241 3231 2625 1615 109 0 Y 15 Y 14 Y 13 Y 12 Y 11 Y 10 Y9 Y8 Y7 Y6 Y5 Y4 Y FIFO Y
151. Video Capture Channel A Field 2 Stop Register 3 13 6 VCAVINT Video Capture Channel A Vertical Interrupt Register VCATHRLD Video Capture Channel A Threshold Register VCAEVTCT Video Capture Channel A Event Count Register 9 13 9 VCBSTAT Video Capture Channel B Status Register VCBCTL Video Capture Channel B Control Register 3 13 10 VCBSTRT1 Video Capture Channel B Field 1 Start Register VCBSTOP1 Video Capture Channel B Field 1 Stop Register VCBSTRT2 Video Capture Channel B Field 2 Start Register VCBSTOP2 Video Capture Channel B Field 2 Stop Register VCBVINT Video Capture Channel B Vertical Interrupt Register VCBTHRLD Video Capture Channel B Threshold Register 3 8 VCBEVTCT Video Capture Channel B Event Count Register TSICTL TSI Capture Control Register 3 13 11 TSICLKINITL TSI Clock Initialization LSB Register TSICLKINITM TSI Clock Initialization MSB Register TSISTCLKL TSI System Time Clock LSB Register 3 13 14 TSISTCLKM TSI System Time Clock MSB Register SPRU629 Video Capture Port 3 49 Video Capture Registers Table 3 13 Video Capture Control Registers Continued Acronym Register Name Section TSISTCMPL TSI System Time Clock Compare LSB Register 3 13 16 TSISTCMPM TSI System Time Clock Compare MSB Register 9 13 1 TSISTMSKL TSI System Time Clock Compare Mask LSB Register 3 8 TSISTMSKM TSI System Time Clock Compare Mask MSB Register 3 13 19 TSITICKS TSI System Time Clock Ticks Interrupt Register 3 13 20 3 13 1 Video Capture Channel x Status Registe
152. W 0 Legend R Read only R W Read Write n value after reset SPRU629 Video Display Port 4 61 Video Display Registers Table 4 9 Video Display Horizontal Blanking Register VDHBLNK Field Descriptions Description Bit fieldt symvalt Value BT 656 and Y C Mode Raw Data Mode 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 HBLNKSTOP OF value O FFFh Location of SAV code and Ending pixel FPCOUNT HBLNK inactive edge of blanking video area within the line HBLNK HBLNK inactive within inactive edge may be the line optionally delayed by 4 VCLKs 15 HBDLA Horizontal blanking delay enable bit NONE 0 Horizontal blanking delay Not used is disabled DELAY 1 HBLNK inactive edge is Not used delayed by 4 VCLKs 14 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 HBLNKSTART OF value O FFFh Location of EAV code and Starting pixel FPCOUNT HBLNK active edge within of blanking video area the line HBLNK active within the line T For CSL implementation use the notation VP VDHBLNK field symval 4 12 5 Video Display Field 1 Vertical Blanking Start Register VDVBLKS1 The video display field 1 vertical blanking start register VDVBLKS1 controls the start of vertical blanking in field 1 The VDVBLKS1 is shown in Figure 4 43 and described in Table 4
153. Y A A Y A A Y A A Y A A Y A A Y A A Y A A Y A Dual Sync Raw Data 10 Bit gt gt DoD D S 5S 5S 5S Raw Data 16 Bit 20 Bit A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A Legend A Channel A display A C Channel A chroma A Y Channel A luma B Optional locked channel B display 1 16 Overview SPRU629 Chapter 2 Video Port This chapter discusses the basic operation of the video port Included is a discussion of the sources and types of resets interrupt operation DMA opera tion external clock inputs video port throughput and latency and the video port control registers Topic Page 23 Reset Operation a AA OE 12 2 2 2 Interrupt Operation sa NBA ennai 12 5 2397 DMAO pgkallon c AA AA AD 12 6 24 ClOCKS eer ce eee ie ee ee ee ee EU ME 2 12 2 5 Video Port Functionality Subsets saa 2 12 2 6 Video Port Throughput and Latency sasa 2 13 2 7 Video Port Control Registers aaa aaa 2 16 2 1 Reset Operation 2 1 Reset Operation 2 1 1 The video port has several sources and types of resets The actions performed by these resets and the state of the port following the resets is described in the following sections Power On Reset Power on reset is an asynchronous hardware reset caused by a chip level reset operation The reset is initiated by a power on reset inp
154. YNC X used in Raw mode Enable second synchronized raw JE data channel RGBX X used in Raw mode RGB extract enable Perform 3 4 FIFO unpacking VCTL1S 00 output HSYNC VCTL2S 00 output VSYNC VCTL3S 0 output CBLNK HXS 0 VCTL1 is an output x4 VXS 0 VCTL2 is an output FXS 0 VCTL3 is an output P PVPSYN 0 no previous port synchronization xy KK KK KK RR A A A A A A A A A A A A Kk Kk kk kk kk kk kk ke Kok ok ok oe oe x x f include csl vp h include csl edma h include csl irq h global variable declarations ay d ki VP Handle vpDisplayHandle handle of vp that to be configured Uint8 dispYSpace Display Y data buffer Uint8 dispCbSpace Display Cb data buffer Uint8 dispCrSpace Display Cb data buffer EDMA Handle hEdmaVPDispY EDMA Handle hEdmaVPDispCb EDMA Handle hEdmaVPDispCr Int32 edmaDispYTccNum 0 EDMA tcc for Y channel Int32 edmaDispCbTccNum 0 EDMA tcc for Cb channel Int32 edmaDispCrTccNum 0 EDMA tcc for Cb channel volatile Uint32 displayFrameCount 0 no of frames that are EJ displayed 7 volatile Uint32 dispUnderrun 0 underrun error flag x SPRU629 Video Port Configuration Examples A 13 Example 2 Noncontinuous Frame Display for 525 60 Format JF x Function bt656 8bit ncfd Input s portNumber video port number i e 0 1 or
155. a 1440 Blanking gt a Active Video 3 oes eese s ege VDIN 9 0 Esis slESBES 58 SIE E ag 3 OP OP WV NO vm M EAV Blanking Data SAV EAV EXC 0 ka One Line pia Next Line HRST 0 HCOUNT 720 721 722 725 855 856 857 0 1 2 718 719 720 721 722 723 a ta One Line ba Next Line gt HCOUNT 856 857 0 1 183 134 135 136 273 274 854 855 856 857 o 1 VCOUNT n 1 n ne Figure 3 10 HCOUNT Operation Example EXC 1 VELKIN imnnnnnnr wg uu uunnnnnnnnnnr CT unnunnuinU ke 276 gt ja 1440 gt ke Blanking gt ja Active Video alsigieie aieic eo eoo eoooeoseeo w Aldlddddda VDINS 0 gijesesese Ja AB anenee P55 acess _ 4 Blanking Data Hain a OTL EXC 1 HRST 0 HCOUNT _ 842 843 844 857 0 63 64 119 120 121 122 123 124 840 842 842 843 844 VCOUNT n 1 n EXC 1 HRST 1 HCOUNT 778 779 780 793 794 857 0 55 56 57 58 59 60 776 777 778 779 780 VCOUNT n 1 n Lo VLLL EXC 1 AVID pepee HRST 0 HCOUNT 720 721 722 735 736 799 800 855 856 857 0 1 2 718 719 720 721 722 VCOUNT n 1 n EXC 1 HRST 1 HCOUNT 0 1 2 15 16
156. a FIFO Packing 00 0 cece eee n 3 18 10 Bit Raw Data FIFO Packing 20 eee 3 19 10 Bit Dense Raw Data FIFO Packing 00 c cece eet ess 3 20 16 Bit Raw Data FIFO Packing 2 eee SPRU629 Figures xi Figures 3 21 20 Bit Raw Data FIFO Packing 0 cece cee es 3 22 Parallel TSI Capture 0 cece tenet teens 3 23 Program Clock Reference PCR Header Format aaa 3 24 System Time Clock Counter Operation 00sec eens 3 25 TSIFIFO Packing 03 KANE NAGA deed hehhe DRA EL AL ADEN GL LL hb ewes 3 26 TSI Timestamp Format Little Endian 0c scenes 3 27 TSI Timestamp Format Big Endian 2 0 00 cece eee eee 3 28 Capture Line Boundary Example 2 0000 cece eee eee eee eens 3 29 Video Capture Channel x Status Register VCASTAT VCBSTAT 3 30 Video Capture Channel A Control Register VCACTL ee eee eee eens 3 31 Video Capture Channel x Field 1 Start Register VCASTRT1 VCBSTRT1 3 32 Video Capture Channel x Field 1 Stop Register VCASTOP1 VCBSTOP1 3 33 Video Capture Channel x Field 2 Start Register VCASTRT2 VCBSTRT2 3 34 Video Capture Channel x Field 2 Stop Register VCASTOP2 VCBSTOP2 3 35 Video Capture Channel x Vertical Interrupt Register VCAVINT VCBVINT 3 36 Video Capture Channel x Threshold Register VCATHRLD VCBTHRLD 3 37 Video Capture Channel x Event Count Register VCAEVT
157. able 4 27 Figure 4 60 Video Display Display Event Register VDDISPEVT 31 28 27 16 R 0 R W 0 15 12 11 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 4 27 Video Display Display Event Register VDDISPEVT Field Descriptions Description Bit field symvalt Value BT 656 and Y C Mode Raw Data Mode 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 DISPEVT2 OF value O FFFh Specifies the number of DMA Specifies the number of DMA event sets YEVT CbEVT events YEVT to be CrEVT to be generated for generated for field 2 output field 2 output 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 DISPEVT1 OF value O FFFh Specifies the number of DMA Specifies the number of DMA event sets YEVT CbEVT events YEVT to be CrEVT to be generated for generated for field 1 output field 1 output t For CSL implementation use the notation VP_VDDISPEVT_DISPEVTn_symval 4 84 Video Display Port SPRU629 Video Display Registers 4 12 23 Video Display Clipping Register VDCLIP The video display clipping register VDCLIP is shown in Figure 4 61 and described in Table 4 28 The video display module in the BT 656 and Y C modes performs program mable clipping The clipping is performed as the last step of the video pipeline
158. absolute time The bits that are set to one mask the corresponding ATC bits during the compare TSISTMSKL is shown in Figure 3 46 and described in Table 3 31 To prevent inaccurate comparisons caused by changing register bits the software should disable the system time clock interrupt clear the STEN bit in TSICTL prior to writing to TSISTMSKL Figure 3 46 TSI System Time Clock Compare Mask LSB Register TSISTMSKL 31 0 ATCM R W 0 Legend R W Read Write n value after reset Table 3 31 TSI System Time Clock Compare Mask LSB Register TSISTMSKL Field Descriptions Description BT 656 Y C Mode Bit Field symvalt Value or Raw Data Mode 31 0 ATCM OF value O FFFFFFFFh Not used TSI Mode Contains the 32 LSBs of the absolute time compare mask t For CSL implementation use the notation VP_TSISTMSKL_ATCM_symval 3 80 Video Capture Port SPRU629 Video Capture Registers 3 13 19 TSI System Time Clock Compare Mask MSB Register TSISTMSKM The transport stream interface system time clock compare mask MSB register TSISTMSKM holds the most significant bit MSB of the absolute time compare mask ATCM This value is used with TSISTMSKL to mask out bits during the comparison of the ATC to the system time clock for absolute time The bits that are set to one mask the corresponding ATC bits during the compare TSISTMSKM is shown in Figure 3 47 and described in Table 3 32 To prevent inaccurate comparisons caused by
159. age Window and Capture 000 cece eee ees 3 3 4 Y C FIFO Packing 0 e eet en 3 4 BT 656 and Y C Mode Field and Frame Operation 2 00 e cece eee 3 4 1 Capture Determination and Notification a 3 4 2 Vertical Synchronization 0 00 cc eens 3 4 8 Horizontal Synchronization sssaaa aeaaaee 3 4 4 Field Identification 0 cect eens 3 4 5 Short and Long Field Detect 0 cece eee 3 5 Video Input Filtering 0 RII III 3 5 4 Input Filter Modes ssssssssssssse en 3 5 2 Chrominance Resampling Operation 0c eee eee es 3 5 8 Scaling Operation s sssserersrsererssrsrersererenrererrererae 3 5 4 Edge Pixel Replication 00 c cece ees 3 6 Ancillary Data Capture 0 0 s n eens 3 6 1 Horizontal Ancillary HANC Data Capture 000 0c cece 3 6 2 Vertical Ancillary VANC Data Capture 000 c eee eee eee 3 7 Raw Data Capture Mode 222222 0 ccc ete e eens 3 7 1 Raw Data Capture Notification 0 cece ees 3 7 2 Raw Data FIFO Packing 0 0 c eee eens vi SPRU629 Contents 3 8 TSI Capture Mode LA semen 3 8 1 TSI Capture Features n 3 8 2 TSI Data Capture LA eens 3 83 TSI Capture Error Detection 0 ccc eee eens 3 8 4 Synchronizing the System Clock 0 0 cece ee eee eens 3 85 TSI Data Capture Noti
160. al interrupt enables and the VIE global enable bit The interrupts are cleared in the video port interrupt status register VPIS using the individual status bits Writing a 1 to the appropriate bit clears the interrupt The clearing of an interrupt flag reenables the generation of another interrupt pulse if other flags are still set In other words pulse generation is reenabled by writing a 1 to any set bit of VPIS Upon receiving an interrupt you should 1 Read VPIS 2 Perform the service routine for whatever bits are set 3 Clear appropriate bits by writing a 1 to their VPIS locations 4 Upon return from the ISR if VPIS bits have been or remain set then another interrupt will occur Video Port 2 5 DMA Operation 2 3 DMA Operation 2 3 1 2 6 The video port uses up to three DMA events per channel for a total of six possible events Each DMA event uses a dedicated event output The outputs are VPYEVTA VPCbEVTA VPCrEVTA VPYEVTB VPCbEVTB VPCrEVTB O O O O O L Capture DMA Event Generation Video Port Capture DMA events are generated based on the state of the capture FIFO s If no DMA eventis currently pending and the FIFO crosses the value specified by VCTHRLDn a DMA event is generated Once an event has been requested another DMA event may not be generated until the servicing of the outstanding event has begun as indicated by the first read of the FIFO by the DMA event service If the capture FIFO lev
161. alf of the transfer size from the Y buffer since for every four Y samples there are two Cb and two Cr samples 3 2 4 BT 656 Data Sampling 3 8 Incoming data including timing codes are sampled and the HCOUNT counter advanced only on clock cycles for which the CAPEN input is active Inputs when CAPEN is inactive are ignored The timing reference codes are recognized only when three sequential samples with CAPEN valid are the FFh 00h 00h sequence A non 00h sample after the FFh or after the first 00h causes the timing reference recognition logic to be reset and to look for FFh again Unsampled data those with CAPEN inactive in the middle of a timing reference do not cause the recognition logic to be reset since these are not considered to be valid inputs Video Capture Port SPRU629 BT 656 Video Capture Mode 3 2 5 BT 656 FIFO Packing Captured data is always packed into 64 bits before being written into the cap ture FIFO s The packing and byte ordering is dependant upon the capture data size and the device endian mode For little endian operation default data is packed into the FIFO from right to left for big endian operation data is packed from left to right The 8 bit BT 656 mode uses three FIFOs for color separation Four samples are packed into each word as shown in Figure 3 2 Figure 3 2 8 Bit BT 656 FIFO Packing vexinavverkins LI LI LI LI LI LIT LELFLEFLFLEIELI VDINB a VOIND 12
162. alf word 10 bit BT 656 or Y C or subword dense pack 10 bit BT 656 or Y C within the FIFOs Therefore the VCTHRLD1 doubleword number represents 8 pixels in 8 bit modes 4 pixels in 10 bit modes or 6 pixels in dense pack 10 bit modes Since the Cb and Cr FIFO thresholds are repre sented by 12 VCTHRLD1 certain restrictions are placed on what VCTHRLD1 values are valid see section 2 3 3 In raw data mode each data sample may occupy a byte 8 bit raw mode half word 10 bit or 16 bit raw mode subword dense pack 10 bit raw mode or word 20 bit raw mode within the FIFO depending on the data size and pack ing mode Therefore the VCTHRLD1 doubleword number represents 8 sam ples 4 samples 6 samples or 2 samples respectively In TSI mode VCTHRLD1 represents groups of 8 samples with each sample occupying a byte in the FIFO The VCTHRLD2 bits behave identically to VCTHRLD1 but are used during field 2 capture It is only used if the field 2 DMA size needs to be different from the field 1 DMA size for some reason for example different captured line lengths in field 1 and field 2 If VT2EN is not set then the VCTHRLD1 value is used for both fields Note that the VCTHRLDn applies to data being written into the FIFO In the case of 8 bit BT 656 or Y C modes this means the output of any selected filter Video Capture Port 3 65 Video Capture Registers Figure 3 36 Video Capture Channel x Threshold Register VCATHRLD VCBTHRLD
163. alues for H V and F on different lines are shown in Table 4 2 and Figure 4 11 F and V are only allowed to change at EAV sequences The EAV and SAV sequences must occupy the first four words and the last four words of the digital horizontal blanking interval respectively The EAV code is inserted when FPCOUNT HBLNKSTART The SAV code is inserted when FPCOUNT HBLNKSTOP Table 4 2 BT 656 Frame Timing Line Number 625 50 525 60 624 625 1 3 1 22 4 19 23 310 20 263 311 312 264 265 313 335 266 282 336 623 283 525 4 10 Video Display Port F V Description 1 Vertical blanking for field 1 EAV SAV code still indicates field 2 0 1 Vertical blanking for field 1 Change EAV SAV code to field 1 0 0 Active video field 1 0 1 Vertical blanking for field 2 EAV SAV code still indicates field 1 1 1 Vertical blanking for field 2 Change EAV SAV code to field 2 1 0 Active video field 2 SPRU629 Figure 4 11 Digital Vertical F and V Transitions 525 lines 60 Hz BT 656 Video Display Mode 625 lines 50 Hz Line 4 Blanking fores Line 1 Blanking Optional blanking ty cue Field 1 Image Field 1 F 0 20 V 0 Fielg1 p Image Field 1 F 0 1 Line Line 266 Blanking ROSEN 543 Blanking 273 V X Optional blanking Image Field 2 Eu 5 283 V 0 Field 2 E Ei F 1 Image Field 2 Blanking 525 V 0 Line 3 gt Line 625 gt H 0 SAV H 0 SAV H 1 EAV H 1 EAV
164. ample n is the last sample In this case any filtering done on the first sample location uses the m leading edge captured pixels m is 3 in this example and any filtering done on the last sample location uses the mtrailing captured pixels From an implementation standpoint the mirroring and filter ing can still begin and end with SAV and EAV but the samples before VCXSTART or after VCXSTOP must not be saved to the YCbOr buffers Figure 3 16 Capture Window Not Requiring Edge Pixel Replication XSTART k XSIZE gt KO MOMOMOMOM OB OBOOR OR MO D Active line a 4 a 3 a 1 e n 4n 3n 2n 1 n n 1n 2n 3 OR OMO MO OMOMONO Leading edge replicated pixels Trailing edge replicated pixels Luma Y Chroma Cb Cr sample samples 3 30 Video Capture Port SPRU629 Ancillary Data Capture 3 6 Ancillary Data Capture The BT 656 and some Y C specifications includes provision for carrying ancillary nonvideo data within the horizontal and vertical blanking regions Horizontal ancillary HANC data appears between the EAV code and SAV codes Vertical ancillary VANC data also called vertical blanking interval VBI data appears during the active horizontal line portion of vertically blanking for example after an SAV with V 1 3 6 1 Horizontal Ancillary HANC Data Capture No special provisions are made for the capture of HANC data HANC data may be captured using the normal video capture mechanism by programmin
165. and from a pin standpoint the video display module appears to continue to function normally SAV EAV codes are generated in the BT 656 or Y C mode and the default data value is sent out The BLKDIS bit should then be cleared to reenable DMA events Clearing the BLKDIS bit does not enable DMA events during the frame where the bit is cleared Clearing this bit to zero enables DMA events in the frame that follows the frame where the bit is cleared Video Display Port 4 51 Video Display Registers 4 12 Video Display Registers Table 4 5 Video Display Control Registers The registers for controlling the video display mode of operation are listed in Table 4 5 See the device specific datasheet for the memory address of these registers Acronym VDSTAT VDCTL VDFRMSZ VDHBLNK VDVBLKS1 VDVBLKE1 VDVBLKS2 VDVBLKE2 VDIMGOFF1 VDIMGSZ1 VDIMGOFF2 VDIMGSZ2 VDFLDT1 VDFLDT2 VDTHRLD VDHSYNC VDVSYNS1 VDVSYNE1 VDVSYNS2 VDVSYNE2 VDRELOAD VDDISPEVT VDCLIP Register Name Video Display Status Register Video Display Control Register Video Display Frame Size Register Video Display Horizontal Blanking Register Video Display Field 1 Vertical Blanking Start Register Video Display Field 1 Vertical Blanking End Register Video Display Field 2 Vertical Blanking Start Register Video Display Field 2 Vertical Blanking End Register Video Display Field 1 Image Offset Register Video Display Field 1 Image Size Register Video Display Fi
166. and written into separate Cb and Cr FIFOs for transfer into Y Cb and Cr buffers in DSP memory The packing and order of the samples is determined by the sample size 8 bit or 10 bit and the device endian mode The Y C capture mode supports HDTV standards such as SMPTE260 SMPTE296 and BT 1120 with embedded EAV and SAV codes It also supports SDTV YCbCr modes that use separate control signals sometimes called CCIR601 mode As with the BT 656 capture mode data bytes where the 8 most significant bits are all setto 1 FF Oh FF 4h FF 8h FF Ch orare all cleared to 0 00 0h 00 4h 00 8h 00 Ch are reserved for data identification purposes and consequential ly only 254 of the possible 256 8 bit words or 1016 of 1024 10 bit words may be used to express signal value 3 3 1 Y C Capture Channels Because Y C mode requires the entire VDATA bus only single channel opera tion is supported If the DCHNL bit in VPCTL is set then Y C mode cannot be selected Y C capture takes place on channel A only Both embedded timing references and external control inputs are supported 3 3 2 Y C Timing Reference Codes Many high resolution Y C interface standards provide for embedded timing reference codes These codes are identical to those used in the BT 656 stan dard except that they appear on both the luma Y and chroma CbCr data streams in parallel 3 12 Video Capture Port SPRU629 Y C Video Capture Mode 3 3 3 Y C Image Window and Capture
167. anking stops HBLNKSTOP Set the V bit timing for field 1 in VDVBIT1 Specify the line where the V bit is set VBITSET1 and the line where the V bit is cleared VBITCLR1 If external VBLNK signal is needed set the VBLNK start for field 1 in VDVBLKS1 Specify the frame line VBLNKYSTART1 and frame pixel counter VBLNKXSTART1 values for the pixel where VBLNK goes active for field 1 Set the VBLNK end for field 1 in VDVBLKE1 Specify the frame line VBLNKYSTOP1 and frame pixel counter VBLNKXSTOP1 values for the pixel where VBLNK goes inactive for field 1 Set the V bit timing for field 2 in VDVBIT2 Specify the line where the V bit is set VBITSET2 and the line where the V bit is cleared VBITCLR2 If external VBLNK signal is needed set the VBLNK start for field 2 in VDVBLKS2 Specify the frame line VBLNKYSTART2 and frame pixel counter VBLNKXSTART2 values for the pixel where VBLNK goes active for field 2 Set the VBLNK end for field 2 in VDVBLKE2 Specify the frame line VBLNKYSTOP2 and frame pixel counter VBLNKXSTOP2 values for the pixel where VBLNK goes inactive for field 2 Set VDIMGSZn Adjust the displayed image size by setting the HSIZE and VSIZE bits Set VDIMOFF Adjust the displayed image offset within the active video area by setting HOFFSET and VOFFSET Set the F bit timing in VDFBIT Specify the line where the F bit is cleared FBITCLR and the line where the F bit is set FBITSET 10 If external FLD outpu
168. ar the bit a write of O has no effect Field 1 has not been displayed Field 1 has been displayed 27 16 VDYPOS OF value 0 FFFh Current frame line counter FLCOUNT value Index of the current line in the current field being displayed by the module 15 14 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 13 VBLNK EMPTY NOTEMPTY Vertical blanking bit Video display is not in a vertical blanking interval Video display is in a vertical blanking interval 12 VDFLD FIELD1ACT FIELD2ACT 0 1 VDFLD bit indicates which field is currently being displayed The VDFLD bit is updated at the start of the vertical blanking interval of the next field Field 1 is active Field 2 is active 11 0 VDXPOS OF value 0 FFFh Current frame pixel counter FPCOUNT value Index of the most recently output pixel t For CSL implementation use the notation VD VDSTAT field symval 4 54 Video Display Port SPRU629 Video Display Registers 4 12 2 Video Display Control Register VDCTL The video display is controlled by the video display control register VDCTL The VDCTL is shown in Figure 4 40 and described in Table 4 7 Figure 4 40 Video Display Control Register VDCTL 31 30 29 28 27 24 R WS 0 R W 1 R 0 R W 0 R 0 23 22 21 20 19 18 17 16 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8
169. ation is made using either VCTL3 as an external FLD input or by field detect logic using the VSYNC and HSYNC inputs 4 1 5 Port Sync Operation The video display module may be synchronized with the video display module of another video port on the device This mode is provided to enable the output of 24 bit or 30 bit RGB data for example 8 bits of R and 8 bits of G on video port O operating in dual channel synced 8 bit raw mode and 8 bits of B on video port 1 operating in 8 bit raw mode with VP1 synced to VPO The slave port must have the same VCLKIN and programmed register values as the master port The master port provides the control signals necessary to reset the slave port counters so that they maintain synchronization Each video port may only synchronize to the previous video port the one with a lower number An example for a three port device is shown in Figure 4 7 Figure 4 7 Video Display Module Synchronization Chain 4 8 Video port 0 Video port 1 Video port 2 display display display Can sync to Can sync to Video Display Port SPRU629 BT 656 Video Display Mode 4 2 BT 656 Video Display Mode The BT 656 display mode outputs 8 bit or 10 bit 4 2 2 co sited luma and chroma data multiplexed into a single data stream Pixels are output in pairs with each pair consisting of two luma samples and two chroma samples The chroma samples are associated with the first luma pixel of the pair Output pixels are valid on the positive
170. ay Port SPRU629 Video Display Registers 4 12 19 Video Display Field 2 Vertical Synchronization Start Register VDVSYNS2 The video display field 2 vertical synchronization start register VDVSYNS2 controls the start of vertical synchronization in field 2 The VDVSYNS2 is shown in Figure 4 57 and described in Table 4 24 Generation of the vertical synchronization is shown in Figure 4 6 page The VSYNC signal is asserted whenever the frame line counter FLCOUNT is equal to VSYNCYSTART2 and the frame pixel counter FPCOUNT is equal to VSYNCXSTART2 Figure 4 57 Video Display Field 2 Vertical Synchronization Start Register VDVSYNS2 31 28 27 16 R 0 R W 0 15 12 11 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 4 24 Video Display Field 2 Vertical Synchronization Start Register VDVSYNS2 Field Descriptions Bit fieldt symvalt Value Description 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 VSYNCYSTART2 OF value O FFFh Specifies the line where VSYNC is asserted for field 2 15 12 Reserved 0 Reserved The reserved bit location is always read as O A value written to this field has no effect 11 0 VSYNCXSTART2 OF value O FFFh Specifies the pixel where VSYNC is asserted in field 2 t For CSL implementation use the notation VP VDVSYNS2 field symval SPRU629 Video Display Port 4 81 Vid
171. bits and the FPCOUNT increment rate INCPIX bit 18 Write to VDCTL to Od Set display mode DMODE 01 x for 8 10 bit output 11x for 16 20 bit output Od Set desired field frame operation CON FRAME DF1 DF2 bits O Select control outputs VCTL1S VCTL2S VCTL3S bits or external sync inputs HXS VXS FXS bits L Select 10 bit unpacking mode DPK bit if appropriate L Set VDEN bit to enable the display 19 Wait for 2 or more frame times to allow the display counters and control signals to become properly synchronized 20 Write to VDCTL to clear the BLKDIS bit 21 Display is enabled at the start of the first frame after BLKDIS 0 and begins with the first selected field DMA events are generated as triggered by VDTHRLD and the DEVTCT counter When a selected field has been displayed FLCOUNT FRMHEIGHT and FPCOUNT FRMWIDTH the appropriate F1D F2D or FRMD bits are set and cause the DCMP bit in VPIS to be set This generates a DSP interrupt if the DCMP bit is enabled in VPIE 4 50 Video Display Port SPRU629 Displaying Video in Raw Data Mode 22 If continuous display is enabled the video port begins displaying again at the start of the next field or frame If noncontinuous field 1 and field 2 or frame display is enabled the next field or frame is displayed during which the DSP must clear the appropriate completion status bit or a DCNA interrupt occurs and incorrect data may be output 4 11 1 Handlin
172. bled ENABLE 1 Chroma is horizontally Not used Not used resampled from 4 2 2 co sited to 4 2 0 interspersed before saving to chroma buffers 9 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 8 SCALE Scaling select bit NONE 0 No scaling Not used Not used HALF 1 1 scaling Not used Not used 7 CON Continuous capture enable bit DISABLE 0 Continuous capture is disabled ENABLE 1 Continuous capture is enabled t For CSL implementation use the notation VP VCACTL field symval For complete encoding of these bits see Table 3 6 Table 3 11 and Table 3 12 3 56 Video Capture Port SPRU629 Video Capture Registers Table 3 15 Video Capture Channel A Control Register VCACTL Field Descriptions Continued Description Bit field symvalt Value BT 656 or Y C Mode Raw Data Mode TSI Mode 6 FRAMEt Capture frame data bit NONE 0 Do not capture frame Do not capture Do not capture single data block single packet FRMCAP 1 Capture frame Capture single Capture single data block packet 5 CF2t Capture field 2 bit NONE 0 Do not capture field 2 Do not capture Not used field 2 FLDCAP 1 Capture field 2 Capture field 2 Not used 4 CF1t Capture field 1 bit NONE 0 Do not capture field 1 Do not capture Not used field 1 FLDCAP 1 Capture field 1 Capture field 1 Not used 3 Reserved 0 Reserved The reserved bit loca
173. ccurs if VIF1 bit is set t For CSL implementation use the notation VP_VDVINT_field_symval 4 88 Video Display Port SPRU629 Video Display Registers 4 12 26 Video Display Field Bit Register VDFBIT The video display field bit register VDFBIT controls the F bit value in the EAV and SAV timing control codes The VDFBIT is shown in Figure 4 65 and described in Table 4 31 The FBITCLR and FBITSET bits control the F bit value in the EAV and SAV timing control codes The F bit is cleared to 0 indicating field 1 display in the EAV code at the beginning of the line whenever the frame line counter FLCOUNT is equal to FBITCLR It remains a 0 for all subsequent EAV SAV codes until the EAV at the beginning of the line when FLCOUNT FBITSET where it changes to 1 indicating field 2 display The F bit operation is completely inde pendent of the FLD control signal For interlaced operation FBITCLR and FBITSET are typically programmed such thatthe F bit changes coincidently with or some time after the V bittransi tions from 1 to O as determined by VBITCLR1 and VBITCLR2 in VDVBITn For progressive scan operation no field 2 output occurs so FBITSET should be programmed to a value greater than FRMHEIGHT so that the condition FLCOUNT FBITSET never occurs and the F bit is always O Figure 4 65 Video Display Field Bit Register VDFBIT 31 28 27 16 FBITSET R 0 15 12 R W 0 11 0 FBITOUR R 0 R W 0 Legend R Rea
174. changed for every even pixel a b c etc in Figure 4 20 Odd luminance pixels a b c etc are generated from neighboring source even pixels using a four tap fil ter The chrominance source pixels are output unchanged for every other even pixel a c e etc Other even output pixel b d f etc chrominance values are generated from neighboring source chrominance pixels using a four tap filter For an interspersed source the luminance is output identically to the co sited case Chrominance output is generated using a four tap filter with one of two different coefficient sets depending on which source chrominance pixel the output pixel is closest Note that because input scaling is limited to 2x full BT 656 width output is not achieved from CIF source images The horizontal location of the reduced image can be adjusted using HOFFSET 4 22 Video Display Port SPRU629 Video Output Filtering Figure 4 20 2x Co Sited Scaling b YCbCr 4 2 2 co sited NG O NG NG O x source pixels b c c d e e 2x upscaled output X X i O EC h O NG NG Yb Yg Sce Ye 17Yg 17Ye 1Y1 32 Cr c Orc Luma Y XK Chroma Cb Cr Cbg 1Cba 17Chg 17Cbg 1Cbg 32 ids samples Cr q 1Crg 17Crg 17Cre 1Crg 32 Figure 4 21 2x Interspersed Scaling YCbCr 4 2 2 interspersed a b C d e f g source pixels Xo OXO AKOO X 2 oe aa bb cc dd ee f f gh E OMOMOWMO KO KO KO co sited output fi L Ya Ya
175. commended Values aaa 4 14 Video Display FIFO Registers ssusssssssssssssee e 5 General Purpose I O Operation sseseeeeee eee n nnn Signals not used for video display or video capture can be used as general purpose I O signals bw GRIO Registers uosssesesleee RR RARI HR RR n 5 1 1 Video Port Peripheral Identification Register VPPID 5 1 2 Video Port Peripheral Control Register PCR ssuseesssessss 5 1 3 Video Port Pin Function Register PFUNC sseeessseenee 5 1 4 Video Port Pin Direction Register PDIR a 5 1 5 Video Port Pin Data Input Register PDIN eee eee eee 5 1 6 Video Port Pin Data Output Register PDOUT 2 2 0005 5 1 7 Video Port Pin Data Set Register PDSET cece eee eee 5 1 8 Video Port Pin Data Clear Register PDCLR 2 aa 5 1 9 Video Port Pin Interrupt Enable Register PIEN 5 1 10 Video Port Pin Interrupt Polarity Register PIPOL Lsse 5 1 11 Video Port Pin Interrupt Status Register PISTAT a 5 1 12 Video Port Pin Interrupt Clear Register PICLR ssusssse SPRU629 Contents ix Contents 6 VCXO Interpolated Control Port uuueeeeeeeeeeeeeeeee nnn Provides an overview of the VCXO interpolated control VIC port 61 OVEIVIOW sce ok bya peti ne xa ee eee Re RE SUE mene gine Seep
176. ctive image The image pixel counter IPCOUNT is reset to 0 at the start of an active line image Once ILCOUNT 1 image pixels from the FIFO are output on each line in field 2 beginning when FPCOUNT IMGHOFF2 If the NH bit is set IPCOUNT is reset when FPCOUNT FRMWIDTH IMGHOFF2 The default output values or blanking values are output during active pixels prior to IMGHOFF2 Figure 4 49 Video Display Field 2 Image Offset Register VDIMGOFF2 31 30 28 27 16 NGVOFF R W 0 15 14 R 0 12 R W 0 11 0 NGHOFF2 R W 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset SPRU629 Video Display Port 4 71 Video Display Registers Table 4 16 Video Display Field 2 Image Offset Register VDIMGOFF2 Field Descriptions Description Bit fieldt symvalt Value BT 656 and Y C Mode Raw Data Mode 31 NV Negative vertical image offset enable bit NONE 0 Not used NEGOFF 1 Display image window Not used begins before the first active line of field 2 Used for VBI data output 30 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 IMGVOFF2 OF value O FFFh Specifies the display image vertical offset in lines from the first active line of field 2 15 NH Negative horizontal image offset NONE 0 Not used NEGOFF 1 Display image window Not used begins before the start of active video Used
177. d hardware and software solution to synchronize the transport system time clock STC with the clock reference transmitted in the bitstream The video port maintains a hardware counter that counts the system time The counter is driven by system time clock STCLK input driven by an external VCXO controlled by the VIC port On reception of a packet the video port captures a snapshot of the counter Software uses this timestamp to determine the deviation of the system time clock from the server clock and drives VCTL output of the VIC port to keep it synchronized VCXO Interpolated Control Port 6 3 Operational Details Any time a packet with a PCR is received the timestamp for that packet is compared with the PCR value in software A PLL is implemented in software to synchronize the STCLK with the system time clock The DSP updates the VIC input register VICIN using the output from this algorithm which in turn drives the VCTL output that controls the system time clock VCXO If fis the frequency of PCRs in the incoming bit stream the interpolation rate R of the VCTL output is given in Equation 6 1 where kis determined by the precision B specified by you Equation 6 1 Relationship Between Interpolation Rate and Input Frequency R kf Equation 6 2 gives the relation between k and the precision p Equation 6 2 Relationship of Frequency Multiplier to Precision k gt NGO 1 3 Table 6 2 Example Values for Interpola
178. d luma n f f f Y a Ya Yb Y c7 Yo Y Yx Yy Yy Yz Yz a 1 Yp 17Yc 1Yq 32 Y z 1Yy 17Yz 17Yz 1Yy 32 Yy AY 17Yy 17Yz 1Yz 182 Y y 1Yw 17Yx 17Yy 1Yz 32 Ya 17Ya 17Yp 1Y 32 x Gilly rw 113 Figure 4 24 Interspersed Chroma Edge Replication cd ab a ab b c cd d w WX X y yz z yz wx X X OXO OXO OXO OXO X X i E w a a replicated chroma z Trailing edge samples X OO Ki OR oe 45 Ow O 59 re replicated Eno conem naga Seg k samples Cb a 3Cbog 33Cbab 101Cbap 3Cbcg 128 Cb z 3Cbwx 101Cbyz 33Cbyz 3Cbyz 128 Cr a 3Crcg 33Crab 101Crap 3Creg 128 Cr z 3Crwx 101Cryz 33Cryz 3Cbyy 128 Ch p 3Cbap 101Cbap 33Cbog 3Cbef 128 Cb y 3Cbyy 33Cby x 101Cby7 3Cbyz 128 Cr y 3Cruy 33Crwx 101Cryz 3Cby7 128 Cb x 3Cbyy 101Cby x 33Cbyz 3Cbyz 128 Cr p 3Crap 101Crap 33Creg 3Cref 128 Cb c 3Cbab 33Cbap 101Cbcg 3Cber 128 Cr 3Crap 33Crap 101Crgg 3Cref 128 Cr y 3Cryy 101Crwx 33Cryz 3Cryz 128 Cb g 3Cbap 101 Cog 33Cbet 3Cbgn 128 Cb w 3Cbst 33Cbyy 101Cbwx 3Cby7 128 Cr g 3Crab 101Crgg 33Cref 3Crgh 128 Cr w 3Crgt 33Cryy 101 Cry x 3Cryz 128 4 24 Video Display Port SPRU629 Ancillary Data Display Raw Data Display Mode 4 5 Ancillary Data Display Thefollowing sections discuss ancillary data display No special
179. d only R W Read Write n value after reset Table 4 31 Video Display Field Bit Register VDFBIT Field Descriptions Description Bit fieldt symvalt Value BT 656 and Y C Mode Raw Data Mode 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 FBITSET OF value O FFFh Specifies the first line with an EAV of Not used F 1 indicating field 2 display 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 FBITCLR OF value O FFFh Specifies the first line with an EAV of Not used F 0 indicating field 1 display t For CSL implementation use the notation VP_VDFBIT_field_symval SPRU629 Video Display Port 4 89 Video Display Registers 4 12 27 Video Display Field 1 Vertical Blanking Bit Register VDVBIT1 The video display field 1 vertical blanking bit register VDVBIT1 controls the V bit value in the EAV and SAV timing control codes for field 1 The VDVBIT1 is shown in Figure 4 66 and described in Table 4 32 The VBITSET1 and VBITCLR 1 bits control the V bit value in the EAV and SAV timing control codes The V bit is set to 1 indicating the start of field 1 digital vertical blanking in the EAV code at the beginning of the line whenever the frame line counter FLCOUNT is equal to VBITSET1 It remains a 1 for all EAV SAV codes until the EAV at the b
180. d stored in memory In some cases for example a DMA structure can be created to provide a set of ping pong or round robin memory buffers to which a continuous stream of fields are stored without DSP interven tion In other cases the DSP may need to modify DMA pointer addresses after each field or frame is captured In some applications only one field may be captured and the other ignored completely or a frame may need to be ignored in order to have time to process a previous frame The video port addresses these issues by providing programmable control over different aspects of the capture process 3 4 4 Capture Determination and Notification SPRU629 The video porttreats the capture of every field as a separate operation In order to accommodate various capture scenarios DMA structures and processing flows the video port employs a flexible capture and DSP notification method This is programmed using the CON FRAME CF1 and CF2 bits in VCxCTL The CON bit controls the capture of multiple fields or frames When CON 1 continuous capture is enabled the video port captures incoming fields assuming the VCEN bit is set without the need for DSP interaction It relies on a DMA structure with circular buffering capability to service the capture FIFOs When CON 0 continuous capture is disabled the video port sets a field or frame capture complete bit F1C F2C or FRMC in VCXSTAT upon the capture of each field as determined by the state
181. data is multiplexed and output on the VDOUT 19 10 half of the bus Figure 1 10 Y C Video Display FIFO Configuration Display FIFO VDOUT 9 0 zt 8 10 Y Buffer 2560 bytes Cb Buffer 1280 bytes VDOUT 19 10 Cr Buffer 1280 bytes 1 3 Video Port Registers 1 12 Overview The video port configuration register space is divided into several different sections with registers grouped by function including top level video port control video capture control video display control and GPIO The registers for controlling the video port are in section 2 7 The registers for controlling the video capture mode of operation are shown in section 3 13 An additional space is dedicated for FIFO read pseudo registers as shown in section 3 14 This space requires high speed access and is not mapped to the register access bus The registers for controlling the video display mode of operation are shown in section 4 12 An additional space is dedicated for FIFO write pseudo registers as shown in section 4 14 This space requires high speed access and is not mapped to the register access bus The registers for controlling the general purpose input output GPIO are shown in section 5 1 SPRU629 Video Port Pin Mapping 1 4 Video Port Pin Mapping The video port requires 21 external signal pins for full functionality Pin usage and direction changes depend on the selected operating mode Pin functional
182. decreasing it to 704 pixels SPRU629 DMA Operation Similarly if a subhorizontal line length is desired line for example then the line length and threshold must be chosen such that the threshold is divisible by 2 This can also be stated as the line length must be an even multiple of DMAslline x 8 For the subline case consider the 8 bit BT 656 capture mode with a line length of 624 Y If the threshold is set for 75 the line length this results in VCTHRLD 624 2 8 39 doublewords The DMA logic would calculate the Cb Cr threshold as 39 2 20 doublewords However two such Cb Cr DMA events would result in atransfer of 40 doublewords which is larger than the actual Cb Cr line length of 624 2 8 39 doublewords This can be corrected by changing the line size to 640 pixels or 608 pixels or by changing the threshold to be 1 3 the line length VCTHRLD 624 3 8 26 doublewords and the Cb Cr threshold is 26 2 13 doublewords 3 x 13 39 doublewords which is exactly the Cb Cr line length 2 3 4 DMA Interface Operation SPRU629 When the video port is configured for capture or TSI mode it only accepts read requests from the DMA interface Write requests are false acknowledged so the bus does not stall and the data is discarded When the video port is configured for display mode it only accepts write requests Read requests are false acknowledged so the bus does not stall and an arbitrary data value is returned
183. deo Display Counter Reload Register VDRELOAD When external horizontal or vertical synchronization are used the video display counter reload register VDRELOAD determines what values are loaded into the counters when an external sync is activated The VDRELOAD is shown in Figure 4 59 and described in Table 4 26 Figure 4 59 Video Display Counter Reload Register VDRELOAD 31 28 27 16 R 0 R W 0 15 12 11 0 R W 0 R W 0 Legend R Read only R W Read Write n value after reset Table 4 26 Video Display Counter Reload Register VDRELOAD Field Descriptions Bit fieldt symvalt Value Description 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 VRLD OF value O FFFh Value loaded into frame line counter FLCOUNT when external VSYNC occurs 15 12 CRLD OF value 0 Fh Value loaded into video clock counter VCCOUNT when external HSYNC occurs 11 0 HRLD OF value O FFFh Value loaded into frame pixel counter FPCOUNT when external HSYNC occurs t For CSL implementation use the notation VP VDRELOAD field symval SPRU629 Video Display Port 4 83 Video Display Registers 4 12 22 Video Display Display Event Register VDDISPEVT The video display display event register VDDISPEVT is programmed with the number of DMA events to be generated for display field 1 and field 2 The VDDISPEVET is shown in Figure 4 60 and described in T
184. deo capture mode the FIFO buffer is divided into three sec tions three buffers One section is 1280 bytes deep and is dedicated for stor age of Y data samples The other two sections are dedicated for storage of Cb and Cr data samples respectively The buffers for Cb and Cr samples are each 640 bytes deep The incoming video data stream is separated into Y Cb and Cr data streams scaled if selected and the Y Cb and Cr buffers are filled Each of the three buffers has a memory mapped location associated with it YSRC CBSRC and CRSRC The YSRC CBSRC and CRSRC locations are read only and are used by DMAs to access video data samples stored in the FIFOs If video capture is enabled BLKCAP bit in VCXxCTL is cleared pixels in the capture window are captured in the Y Cb and Cr buffers The video capture module uses the YEVT CbEVT and CrEVT eventsto notify the DMA controller to copy data from the capture buffers to the DSP memory The number of doublewords required to generate the events is set by the VCTHRLDn bits in VCxTHRLD On every YEVT the DMA should move data from the Y buffer to DSP memory using the YSRC location as the source address On every CbEVT the DMA should move data from the Cb buffer to DSP memory using the CBSRC location as the source address On every CrEVT the DMA should move data from the Cr buffer to DSP memory using the CRSRC location as the source address Note that transfer size from the Cb and Cr buffers is h
185. dispCrSpace vpDisplayHandle 5crdstAddr VD Y EDMA FRI CNT VD Y EDMA ELECNT 2 Video Port Configuration Examples 1 2 of Y x xd X tf x ef 4 E ay ry SPRU629 Example 2 Noncontinuous Frame Display for 525 60 Format enable three EDMA channels EDMA enableChannel hEdmaVPDispY EDMA enableChannel hEdmaVPDispCb EDMA enableChannel hEdmaVPDispCr Function configVPDispEDMAChannel Input s edmaHandle eventId tccNum srcAddr dstAddr frameCount elementCount Output s edmaHandle tccNum Description Configures t the displayed data is write to t EDMA eventId pointer to EDMA handle pointer to transfer complete number Source address for he destination address frame count EDMA transfer for EDMA transfer element count 32 bi lement size edma Handle of the given event transfer complete code for the given event given VP display EDMA channel The destination address update is fixed because he FIFO In this exampl auto increment there is lot of flexibility in t buffers can b robin etc the source address mode is But in real time applications he way display managed like ping pong and round void configVPDispEDMAChannel La
186. djs37Wigcc r EDMA Handle edmaHandle Int32 eventId Uint32 srcAddr Uint32 frameCount Int32 tccNum Uint32 dstAddr Uint32 elementCount Open Y event EDMA channel edmaHandle EDMA open eventId EDMA OPEN RESET if edmaHandle EDMA HINV test exit FAIL allocate TCC for Y event if tcc EDMA intAlloc 1 1 test exit FAIL SPRU629 Video Port Configuration Examples oy Ki Ki 7 Ay xf A y KJ aj Ay 7 Xf QA y sy x y tf E t to tip 54 Ef EA E7 A 19 Example 2 Noncontinuous Frame Display for 525 60 Format A 20 Configure EDMA configArgs EDMA parameters medium priority Element size 32 bits 2 dimensional source source address auto increment 1 dimensional destination FIFO fixed dest address mode FIFO Enable transfer complete indication Disable Alternate Transfer Complete Interrupt disable PDT peripheral devic transfer mode for source disable PDT mode for dest Disable linking Array synchronization OF frameCount 1 OF elementCount IDX OF elementCount 4 note 32 bit element siz edmaHandle EDMA OPT RMK EDMA OPT PRI MEDIUM EDMA OPT ESIZE 32BIT EDMA OPT 2DS YES EDMA_OPT_SUM_INC ex EDMA_
187. dp la ree onto ms EN Co 3 20 3 21 3 22 3 23 Tables Video Capture Signal Mapping 0 000 cece eee III Video Display Signal Mapping 22 22 44 RII VDIN Data Bus Usage for Capture Modes naana nunnana nanenane VDOUT Data Bus Usage for Display Modes 00 c cece eee eee eee Video Port Functional Clocks 0 000 e cence eens Y C Video Capture FIFO Capacity 2 c ccs Raw Video Display FIFO Capacity 0 teens Video Port Control Registers 0 0 c cee eee eee eee nh Video Port Control Register VPCTL Field Descriptions a Video Port Operating Mode Selection 0 00 cece eee eee eee Video Port Status Register VPSTAT Field Descriptions aa Video Port Interrupt Enable Register VPIE Field Descriptions Video Port Interrupt Status Register VPIS Field Descriptions Video Capture Mode Selection 0 00 cece eet ees BT 656 Video Timing Reference Codes 0 ccc eect eect eee BT 656 Protection Bits Bp ee eens Error Correction by Protection Bits 0 0 cece cece eee eee Common Video Source Parameters cece eect ence ees BT 656 and Y C Mode Capture Operation 00 cece eee eee Vertical Synchronization Programming 0000 cece eee eee Horizontal Synchronization Programming cece cece eens Field Identificati
188. e current field 15 13 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 12 VCFLD VCFLD bit indicates which field is currently being captured The VCFLD bit is updated based on the field detection logic selected by the FLDD bit in VCACTL NONE 0 Field 1 is active Not used Not used DETECTED 1 Field 2 is active Not used Not used 11 0 VCXPOS OrF value O FFFh Current HCOUNT Lower 12 bits of Lower 12 bits of value The pixel index of the last received pixel t For CSL implementation use the notation VP VCxSTAT field symval 3 52 Video Capture Port the data counter the data counter SPRU629 Video Capture Registers 3 13 2 Video Capture Channel A Control Register VCACTL Video capture is controlled by the video capture channel A control register VCACTL shown in Figure 3 30 and described in Table 3 15 Figure 3 30 Video Capture Channel A Control Register VCACTL 31 30 29 24 RSTCH BUKCAP R WS 0 R W 1 R 0 23 22 21 20 19 18 17 16 R 0 R W 0 R W 0 R W 0 R W 0 R W 1 R W 0 15 14 13 12 11 10 9 8 VCEN PK10B LFDE SFDE RESMPL SCALE R W 0 R W 0 R W 0 R W 0 R W 0 R 0 R W 0 7 6 5 4 3 2 0 FRAME CMODE R W 0 R W 0 R W 1 R W 1 R 0 R W 0 Legend R Read only R W Read Write WS Write 1 to reset write of 0 has no effect n value after reset Table 3 15 Video Capture Channel A Control Register VCACTL Field Descriptions Description Bit
189. e display FIFOs because no events occur The F1D F2D and FRMD bits in VDSTAT are still set when fields or frames are complete Clearing BLKDIS does not enable DMA events during the field in which the bit is cleared DMA events are enabled at the start of the next frame after the one in which the bit is cleared This allows the DMA to always be synced to the proper field Blocks DMA events and flushes the display FIFOs 29 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 28 PVPSYN DISABLE ENABLE Previous video port synchronization enable bit Output timing is locked to preceding video port VP2 is locked to VP1 or VP1 is locked to VPO see Figure 4 7 on page 4 8 27 24 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 23 FXS OUTPUT FSINPUT Field external synchronization enable bit VCTL3 is an output VCTL3 is an external field sync input 22 VXS OUTPUT VSINPUT 0 1 Vertical external synchronization enable bit VCTL2 is an output VCTL2 is an external vertical sync input t For CSL implementation use the notation VP_VDCTL_field_symval For complete encoding of these bits see Table 4 4 4 56 Video Display Port SPRU629 Video Display Registers Table 4 7 Video Display Control Register VDCTL Field Descriptions Continued Description B
190. e 3 35 and described in Table 3 20 In BT 656 or Y C mode an interrupt can be generated upon completion of the specified line in a field end of line when VCOUNT VINTn This allows the software to synchronize to the frame or field The interrupt can be programmed to occur in one or both fields or not at all using the VIF1 and VIF2 bits The VINTn bits also determine when the FSYNC bit in VOxSTAT is cleared If FSCL2 is 0 then the FSYNC bit is cleared in field 1 when VCOUNT VINT1 if FSCL2 is 1 then the FSYNC bit is cleared in field 2 when VCOUNT VINT2 Figure 3 35 Video Capture Channel x Vertical Interrupt Register VCAVINT VCBVINT 31 30 29 28 27 16 R AW 0 HR W 0 R 0 R W 0 15 14 12 11 0 R W 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset SPRU629 Video Capture Port 3 63 Video Capture Registers Table 3 20 Video Capture Channel x Vertical Interrupt Register VCxVINT Field Descriptions Description Bit fieldt symvalt Value BT 656 or Y C Mode Raw Data Mode TSI Mode 31 VIF2 Setting of VINT in field 2 enable bit DISABLE 0 Setting of VINT in field 2 is Not used Not used disabled ENABLE 1 Setting of VINT in field 2 is Not used Not used enabled 30 FSCL2 FSYNC bit cleared in field 2 enable bit NONE 0 FSYNC bit is not cleared Not used Not used FIELD2 1 FSYNC bit is cleared in Not used Not used field 2 instead of field 1 29 28 Reserved 0
191. e data bus must be configured as either functional pins or GPIO pins In the case of single BT 656 or raw 8 10 bit mode the upper 10 VDATA pins VDATA 19 10 can be used as GPIOs If the video port is disabled all pins can be used as GPIO Figure 5 3 Video Port Pin Function Register PFUNC 31 23 22 21 20 19 16 R 0 R W 0 R W 0 R W 0 R W 0 15 11 10 9 1 0 R 0 R W 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 5 4 Video Port Pin Function Register PFUNC Field Descriptions Bit fieldt symvalt Value Description 31 23 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 22 PFUNC22 PFUNC22 bit determines if VCTL3 pin functions as GPIO NORMAL 0 Pin functions normally VCTL3 1 Pin functions as GPIO pin 21 PFUNC21 PFUNC21 bit determines if VCTL2 pin functions as GPIO NORMAL 0 Pin functions normally VCTL2 1 Pin functions as GPIO pin t For CSL implementation use the notation VP PFUNC field symval 5 6 General Purpose I O Operation SPRU629 GPIO Registers Table 5 4 Video Port Pin Function Register PFUNC Field Descriptions Continued Bit fieldt symvalt 20 PFUNC20 NORMAL VCTL1 Value Description PFUNO20 bit determines if VCTL1 pin functions as GPIO Pin functions normally Pin functions as GPIO pin 19 11 Reserved Reserved The reserved bit location is always read as 0 A value written to this fie
192. e mode or display mode Not used No interrupt is detected Interrupt is detected Bit is cleared 5 VINTA2 NONE CLEAR Channel A field 2 vertical interrupt detected bit BT 656 or Y C capture mode or any display mode VINTA2 is set when a vertical interrupt occurred in field 2 Raw data mode or TSI capture mode Not used No interrupt is detected Interrupt is detected Bit is cleared 4 VINTA1 NONE CLEAR 0 1 Channel A field 1 vertical interrupt detected bit BT 656 or Y C capture mode or any display mode VINTA1 is set when a vertical interrupt occurred in field 1 Raw data mode or TSI capture mode Not used No interrupt is detected Interrupt is detected Bit is cleared t For CSL implementation use the notation VP VPIS field symval 2 28 Video Port SPRU629 Video Port Control Registers Table 2 9 Video Port Interrupt Status Register VPIS Field Descriptions Continued Bit field symval 3 SERRA NONE CLEAR Value Description Channel A synchronization error interrupt detected bit BT 656 or Y C capture mode Synchronization parity error on channel A An SERRA typically requires resetting the channel RSTCH or the port VPRST Raw data mode or TSI capture mode Not used No interrupt is detected Interrupt is detected Bit is cleared 2 CCMPA NONE CLEAR Capture complete on channel A interrupt detected bit Data is not in memory until the DMA t
193. e notation VP VDHSYNC field symval 4 78 Video Display Port SPRU629 Video Display Registers 4 12 17 Video Display Field 1 Vertical Synchronization Start Register VDVSYNS1 The video display field 1 vertical synchronization start register VDVSYNS1 controls the start of vertical synchronization in field 1 The VDVSYNS 1 is shown in Figure 4 55 and described in Table 4 22 Generation of the vertical synchronization is shown in Figure 4 6 page The VSYNC signal is asserted whenever the frame line counter FLCOUNT is equal to VSYNCYSTART1 and the frame pixel counter FPCOUNT is equal to VSYNCXSTART1 Figure 4 55 Video Display Field 1 Vertical Synchronization Start Register VDVSYNS1 31 28 27 16 R 0 R W 0 15 12 11 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 4 22 Video Display Field 1 Vertical Synchronization Start Register VDVSYNS1 Field Descriptions Bit fieldt symvalt Value Description 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 VSYNCYSTART1 OF value O FFFh Specifies the line where VSYNC is asserted for field 1 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 VSYNCXSTART1 OF value O FFFh Specifies the pixel where VSYNC is asserted in field 1 t For CSL implementation use the notation VP VDVSYNS1
194. e to clear F2C before next field 2 begins Noncontinuous field 1 and field 2 capture Capture both fields F1C is set after field 1 capture and causes CCMPx to be set The F1C bit must be cleared by the DSP before another field 1 capture can occur The DSP has the entire field 2 time to clear F1C before next field 1 begins F2C is set after field 2 capture and causes CCMPx to be set The F2C bit must be cleared by the DSP before another field 2 capture can occur The DSP has the entire field 1 time to clear F2C before next field 2 begins Noncontinuous frame capture Capture both fields FRMC is set after field 2 capture and causes CCMPx to be set Capture halts upon completion of the next frame unless the FRMC bit is cleared The DSP has the entire next frame time to clear FRMC Noncontinuous progressive frame capture Capture field 1 FRMC is set after field 1 capture and causes CCMPx to be set Capture halts upon completion of the next frame unless the FRMC bit is cleared The DSP has the entire next frame time to clear FRMC Reserved Single frame capture Capture both fields FRMC is set after field 2 capture and causes CCMPXx to be set Capture halts until the FRMC bit is cleared The DSP has the field 2 to field 1 vertical blanking time to clear FRMC Reserved Continuous field 1 capture Capture only field 1 F1C is set after field 1 capture and causes CCMPx to be set CCMPx interrupt can be disabled The video port con
195. e uses the YEVT CbEVT and CrEVT events to notify the DMA controller that data needs to be placed into the display FIFOs The number of pixels required to generate the events is set by the VDTHRLD bits in VDTHRLD VTHRLD must be an even number The video display module generates the event signals when the display buffer holds less than the VDTHRLD number of pixels and the DEVTCT counter has not expired On every YEVT the DMA should move data from DSP memory to the Y buffer using the Y FIFO destination register YDST content as the destination address On every CbEVT the DMA should move data from DSP memory to the Cb buffer using the Cb FIFO destination register CBDST content as the destination address On every CrEVT the DMA should move data from DSP memory to the Cr buffer using the Cr FIFO destination register CRDST content as the destination address The DMA transfer size for the Y buffer is twice the size of the DMA for the Cb or Cr buffers Video Display Port SPRU629 BT 656 Video Display Mode 4 2 4 BT 656 FIFO Unpacking Display data is always packed into the FIFOs in 64 bit words and must be unpacked before being sent to the video display data pipeline The unpacking and byte ordering is dependant upon the display data size and the device endian mode For little endian operation default data is unpacked from right to left for big endian operation data is unpacked from left to right The 8 bit BT 656 mode uses three FIFOs
196. ection 0ceeeeee eee e eee eee 4 2 BT 656 Video Display Mode naaa aaa 4 3 Y C Video Display Mode m ee eee e e PTS 4 4 Video Output Filtering sese 45 Ancillary Data Display 200272151813 r cess ccc e meena ne cece 4 6 Raw Data Display Mode eese 4 7 Video Display Field and Frame Operation 4 8 Display Line Boundary Conditions 4 9 Display Timing Examples lesen 4 10 Displaying Video in BT 656 or Y C Mode LLusese 4 11 Displaying Video in Raw Data Mode 4 12 Video Display Registers 222220 4 13 Video Display Registers Recommended Values 4 14 Video Display FIFO Registers aaa Video Display Mode Selection 4 1 Video Display Mode Selection The video display module operates in one of three modes as listed in Table 4 1 The DMODE bits are in the video display control register VDCTL The Y C and 16 20 bit raw display modes may only be selected if the DCDIS bit in the video port control register VPCTL is cleared to 0 Table 4 1 Video Display Mode Selection DMODE Bits 000 001 010 011 100 101 110 111 Mode Description 8 Bit ITU R BT 656 Digital video output is in YCbCr 4 2 2 with 8 bit resolution Display multiplexed in ITU R BT 656 format 10 Bit ITU R BT 656 Digital video output
197. ed t For CSL implementation use the notation VP VPIS field symval SPRU629 Video Port 2 25 Video Port Control Registers Table 2 9 Video Port Interrupt Status Register VPIS Field Descriptions Continued Bit field symval Value Description 18 CCMPB Capture complete on channel B interrupt detected bit Data is not in memory until the DMA transfer is complete BT 656 or Y C capture mode CCMPB is set after capturing an entire field or frame when F1C F2C or FRMC in VCBSTAT are set depending on the CON FRAME CF1 and CF2 control bits in VCBCTL Raw data mode RDFE is not set CCMPB is set when FRMC in VCBSTAT is set when the data counter the combined VCYSTOP VCXSTOP value TSI capture mode CCMPB is set when FRMC in VCBSTAT is set when the data counter the combined VCYSTOP VCXSTOP value NONE 0 No interrupt is detected CLEAR 1 Interrupt is detected Bit is cleared 17 COVRB Capture overrun on channel B interrupt detected bit COVRB is set when data in the FIFO was overwritten before being read out by the DMA NONE 0 No interrupt is detected CLEAR 1 Interrupt is detected Bit is cleared 16 GPIO Video port general purpose I O interrupt detected bit NONE 0 No interrupt is detected CLEAR 1 Interrupt is detected Bit is cleared 15 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 14 DCNA Display complete not acknowledg
198. ed Indicates that the F1D F2D or FRMD bit that caused the display complete interrupt was not cleared prior to the start of the next gating field or frame NONE 0 No interrupt is detected CLEAR 1 Interrupt is detected Bit is cleared t For CSL implementation use the notation VP VPIS field symval 2 26 Video Port SPRU629 Video Port Control Registers Table 2 9 Video Port Interrupt Status Register VPIS Field Descriptions Continued Bit field symval 13 DCMP NONE CLEAR Value Description Display complete Indicates that the entire frame has been driven out of the port The DMA complete interrupt can be used to determine when the last data has been transferred from memory to the FIFO DCMP is set after displaying an entire field or frame when F1D F2D or FRMD in VDSTAT are set depending on the CON FRAME DF1 and DF2 control bits in VDCTL No interrupt is detected Interrupt is detected Bit is cleared 12 DUND NONE CLEAR Display underrun Indicates that the display FIFO ran out of data No interrupt is detected Interrupt is detected Bit is cleared 11 TICK NONE CLEAR System time clock tick interrupt detected bit BT 656 Y C capture mode or raw data mode Not used TSI capture mode TICK is set when the TCKEN bit in TSICTL is set and the desired number of system time clock ticks has occurred as programmed in TSITICKS No interrupt is detected Interrupt is detected Bit is c
199. edge of VCLKOUT in the sequence CbYCrY as shown in Figure 4 8 Figure 4 8 BT 656 Output Sequence vcekor LI U LILI LIL LP LU LS Ud VDOUT 9 0 Co Yo cro v1 co v2 crt vs coe Y4 4 2 1 Display Timing Reference Codes The end active video EAV code and start active video SAV code are issued at the start of each video line EAV and SAV codes have a fixed format The format is shown in Table 3 2 page B 4 The EAV and SAV codes define the end and start of the horizontal blanking interval respectively and they also indicate the current field number and the vertical blanking interval The SAV and EAV codes have a 4 bit protection field to ensure valid codes The video display module generates these protection bits as part of the SAV and EAV codes Table 3 3 page 3 5 shows possible combinations of valid SAV and EAV codes with their protection bits The video display pipeline generates SAV and EAV sync codes and inserts them into the output video stream according to the BT 656 specification The BT 656 line timing is shown in Figure 4 9 and Figure 4 10 Each line begins with an EAV code a blanking interval an SAV code followed by the line of active video The EAV code indicates the end of active video for the previous line and the SAV code indicates the start of active video for the current line Figure 4 9 525 60 BT 656 Horizontal Blanking Timing
200. eee one ve Pee J MEN Cx de cha be bd che die bd cab bended needed eaten 6 3 Operational Details ccc RII 6 4 Enabling VIC Port nent e eens 6 5 VIC Port Registers c cece tenet hh 6 5 1 VIC Control Register VICCTL 000 eee eee 6 5 2 VIC Input Register VICIN 0 0c cee eee RII 6 5 3 VIC Clock Divider Register VICDIV 2 a A Video Port Configuration Examples seeeeeee eee III Describes how to configure the video port in different modes with the help of examples All examples in this appendix use the video port Chip Support Library CSL A 1 Example 1 Noncontinuous Frame Capture for 525 60 Format A 2 A 2 Example 2 Noncontinuous Frame Display for 525 60 Format A 10 x SPRU629 1 1 Video Port Block Diagram 0 00 cece Rm 1 2 BT 656 Video Capture FIFO Configuration eaaa e eaaa aa 1 3 8 10 Bit Raw Video Capture and TSI Video Capture FIFO Configuration 1 4 Y C Video Capture FIFO Configuration eee 1 5 16 20 Bit Raw Video Capture FIFO Configuration 0600 aa 1 6 BT 656 Video Display FIFO Configuration lesser 1 7 8 10 Bit Raw Video Display FIFO Configuration a 1 8 8 10 Bit Locked Raw Video Display FIFO Configuration aa 1 9 16 20 Bit Raw Video Display FIFO Configuration aaa 1 10 Y C Video Display FIFO Conf
201. efines the minimum vertical blank ing period If CAPEN stays deasserted longer than VCVBLNKP clocks then a vertical blanking interval is considered to have occurred If the SSE bit is set when the capture first begins the VCEN bit is set in VCxCTL the capture does not start until two intervals are counted This allows the video port to syn chronize its capture to the top of a frame when first started In TSI capture mode the capture starts when the CAPEN signal is asserted the FRMC bit in VCxSTAT is cleared and a SYNC byte is detected Figure 3 31 Video Capture Channel x Field 1 Start Register VCASTRT1 VCBSTRT1 31 28 27 16 R 0 R W 0 15 14 12 11 0 R W 1 R 0 R W 0 Legend R Read only R W Read Write n value after reset 3 58 Video Capture Port SPRU629 Video Capture Registers Table 3 16 Video Capture Channel x Field 1 Start Register VCxSTRT1 Field Descriptions Bit fieldt symvalt 31 28 Reserved BT 656 or Y C Mode Reserved The reserved value written to this field Description has no effect Raw Data Mode TSI Mode bit location is always read as 0 A 27 16 VCYSTART OF value Starting line number Not used Not used 15 SSE DISABLE ENABLE Startup synchronization enable bit Not used Not used synchronization is disabled synchronization is enabled Startup Not used Startup Not used 14 12 Reserved Reserved The reserved bit locatio
202. eginning of the line on when FLCOUNT VBITCLR1 where it changes to 0 indicating the start of the field 1 digital active display The V bit operation is completely independent of the VBLNK control signal The VBITSET1 and VBITCLR1 bits should be programmed so that FLCOUNT becomes set to 1 during field 1 vertical blanking The hardware only starts generating field 1 EDMA events when FLCOUNT 1 Figure 4 66 Video Display Field 1 Vertical Blanking Bit Register VDVBIT1 31 R 0 28 27 16 R W 0 12 11 0 15 R 0 R W 0 Legend R Read only R W Read Write n value after reset 4 90 Video Display Port SPRU629 Video Display Registers Table 4 32 Video Display Field 1 Vertical Blanking Bit Register VDVBIT1 Field Descriptions Description Bit fieldt symvalt Value BT 656 and Y C Mode Raw Data Mode 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 VBITCLR1 OF value O FFFh Specifies the first line with an EAV of Not used V 0 indicating the start of field 1 active display 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 VBITSET1 OF value O FFFh Specifies the first line with an EAV of Not used V 1 indicating the start of field 1 vertical blanking t For CSL implementation use the notation VP VDVBIT1 field symval SPRU629 Video
203. el exceeds 2x the VCTHRLDn value before the requested DMA event completes then another DMA event may be generated Thus up to one DMA event may be outstanding An outgoing data counter counts data read by the DMA This counter is loaded with the VCTHRLDn value whenever a new DMA service begins The counter then counts down for each double word read from the FIFO by the DMA The DMA is complete when the counter reaches zero Figure 2 1 shows the capture DMA event generation For BT 656 and Y C modes there are three FIFOs one for each of the Y Cb and Cr color components Each FIFO generates its own DMA event therefore the DMA event state and FIFO thresholds for each FIFO are tracked indepen dently The Cb and Cr FIFOs use a threshold value of 15 VCTHRLDn VCTHRLDn mod 2 SPRU629 Figure 2 1 Capture DMA Event Generation Flow Diagram Empty FIFO Capture data no DMA pending FIFO gt threshold Yes Generate DMA event Capture data DMA pend ing new events disabled No DMA Operation Ye AD Yes Generate DMA request Capture Data DMA active amp DMA pending Yes DMA complete Yes FIFO overflow SPRU629 FIFO overflow No Pending DMA begun FIFO overflow Yes Capture data DMA active new events enabled Yes No No No FIFO 2 2x threshold DMA complete Yes Overflow error Overflow error Video Port 2 7 DMA Operation Because the captu
204. el is enabled 11 DVEN Default value enable bit BLANKING 0 Blanking value is output during Not used non sourced active pixels DV 1 Default value is output during Not used non sourced active pixels 10 RESMPL Chroma resampling enable bit DISABLE 0 Chroma resampling is disabled Not used ENABLE 1 Chroma is horizontally Not used resampled from 4 2 0 interspersed to 4 2 2 co sited before output 9 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 8 SCALE Scaling select bit NONE 0 No scaling Not used X2 1 2x scaling Not used 7 CON Continuous display enable bit DISABLE 0 Continuous display is disabled ENABLE 1 Continuous display is enabled t For CSL implementation use the notation VP VDCTL field symval For complete encoding of these bits see Table 4 4 4 58 Video Display Port SPRU629 Video Display Registers Table 4 7 Video Display Control Register VDCTL Field Descriptions Continued Description Bit fieldt symvalt Value BT 656 and Y C Mode Raw Data Mode 6 FRAME Display frame bit NONE 0 Do not display frame FRMDIS 1 Display frame 5 DF2t Display field 2 bit NONE 0 Do not display field 2 FLDDIS 1 Display field 2 4 DF1t Display field 1 bit NONE 0 Do not display field 1 FLDDIS 1 Display field 1 3 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect
205. eld 2 Image Offset Register Video Display Field 2 Image Size Register Video Display Field 1 Timing Register Video Display Field 2 Timing Register Video Display Threshold Register Video Display Horizontal Synchronization Register Video Display Field 1 Vertical Synchronization Start Register Video Display Field 1 Vertical Synchronization End Register Video Display Field 2 Vertical Synchronization Start Register Video Display Field 2 Vertical Synchronization End Register Video Display Counter Reload Register Video Display Display Event Register Video Display Clipping Register 4 52 Video Display Port Section 4 12 K K A N IN amp A n2 x Ln Ng S O Em po x x S x O Co D x A D a IN amp pan NI a amp amp S n2 N n2 gt EP a O x S un n2 A S Qo E un n2 O S S S n i NI hv IN pad O A m ho to aS E S d Video Display Registers Table 4 5 Video Display Control Registers Continued Acronym Register Name Section VDDEFVAL Video Display Default Display Value Register VDVINT Video Display Vertical Interrupt Register VDFBIT Video Display Field Bit Register 4 12 26 VDVBIT1 Video Display Field 1 Vertical Blanking Bit Register 4 12 2 VDVBIT2 Video Display Field 2 Vertical Blanking Bit Register 4 8 4 12 1 Video Display Status Register VDSTAT The video display status register VDSTAT indicates the current display status of the video
206. eline TSI capture pipeline 8 Channel A BT 656 capture Raw video pipeline 10 10 display pipeline Capture display 10 Raw video a aha 10 nel tes VDIN 19 10 capture pipeline ytes VDOUT 19 10 Channel B LER S On Ln D rn DMA interface 1 4 Overview SPRU629 Video Port FIFO 1 2 Video Port FIFO The video port includes a FIFO to store data coming into or out from the video port The video port operates in conjunction with DMA transfers to move data between the video port FIFO and external or on chip memory You can pro gram threshold settings so DMA events are generated when the video port FIFO reaches a certain fullness for capture or goes below a certain fullness for display DMAs required to service the FIFO are set up independently by you and are key to correct operation of the video port The FIFO size is relative ly large to allow time for DMAs to service the transfer requests since devices typically have many peripheral interfaces often including multiple video ports The following sections briefly describe the interaction with the DMA and differ ent FIFO configurations used to support the various modes of the video port 1 2 1 DMA Interface SPRU629 Video port data transfers take place using DMAs DMA requests are based on buffer thresholds Since the video port does not directly source the transfer it can not adjust the transfer size based on buffer empty full status This means
207. eo Display Registers 4 12 20 Video Display Field 2 Vertical Synchronization End Register VDVSYNE2 The video display field 2 vertical synchronization end register VDVSYNE2 controls the end of vertical synchronization in field 2 The VDVSYNE2 is shown in Figure 4 58 and described in Table 4 25 Generation of the vertical synchronization is shown in Figure 4 6 page The VSYNC signal is deasserted whenever the frame line counter FLCOUNT is equal to VSYNCYSTOP2 and the frame pixel counter FPCOUNT is equal to VSYNCXSTOP2 Figure 4 58 Video Display Field 2 Vertical Synchronization End Register VDVSYNE2 31 28 27 16 R 0 R W 0 15 12 11 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 4 25 Video Display Field 2 Vertical Synchronization End Register VDVSYNE2 Field Descriptions Bit fieldt symvalt Value Description 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 VSYNCYSTOP2 OF value O FFFh Specifies the line where VSYNC is deasserted for field 2 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 VSYNCXSTOP2 OF value O FFFh Specifies the pixel where VSYNC is deasserted in field 2 t For CSL implementation use the notation VP VDVSYNE2 field symval 4 82 Video Display Port SPRU629 Video Display Registers 4 12 21 Vi
208. equal to FLD2XSTART this is shown in Figure 4 6 page In BT 656 and Y C mode the FLD signal is asserted to indicate field 2 display whenever FLCOUNT FLD2YSTART and FPCOUNT FLD2XSTART The FLD output is completely independent of the timing control codes The F bit in the EAV SAV codes is controlled by the VDFBIT register Figure 4 52 Video Display Field 2 Timing Register VDFLDT2 31 28 27 16 R 0 R W 0 15 12 11 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 4 19 Video Display Field 2 Timing Register VDFLDT2 Field Descriptions Bit fieldt symvalt Value Description 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 FLD2YSTART OF value O FFFh Specifies the first line of field 2 The line where FLD is asserted 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 FLD2XSTART OF value O FFFh Specifies the pixel on the first line of field 2 where the FLD output is asserted t For CSL implementation use the notation VP_VDFLDT2_field_symval SPRU629 Video Display Port 4 75 Video Display Registers 4 12 15 Video Display Threshold Register VDTHRLD The video display threshold register VDTHRLD sets the display FIFO thresh old to determine when to load more display data The VDTHRLD is shown in Figure 4 53 and descr
209. errun error Event counter expired No Generate DMA request Display Data DMA active and DMA pending Yes DMA complete SPRU629 DMA complete Yes FIFO underru Yes No FIFO underru Yes nderrun error Yes Underrun erro Video Port 2 9 DMA Operation A DMA event counter is used to track the number of DMA events generated in each field as programmed in the VDDISPEVT register The DISPEVT1 or DISPEVT2 value depending on the current display field is loaded at the start of each field The event counter then decrements with each DMA event gener ation until it reaches 0 at which point no more DMA events are generated until the next field begins Once the last line of data for a field has been requested the DMA logic stops generating events until the field is complete in case the CPU needs to modify the DMA address pointers For BT 656 and Y C modes there are three FIFOs one for each of the Y Cb and Cr color components Each FIFO generates its own DMA event therefore the DMA event state and FIFO thresholds for each FIFO are tracked indepen dently The Cb and Cr FIFOs use a threshold value of 7 2 VDTHRLD 2 3 3 DMA Size and Threshold Restrictions 2 10 Video Port The video port FIFOs are 64 bits wide and always read or write 64 bits at a time Forthis reason DMA accesses must always be an even number of words in length It is expected that in most cases the threshold size is set to
210. errupts in field 1 and field 2 The VDVINT is shown in Figure 4 64 and described in Table 4 30 An interrupt can be generated upon completion of the specified line in a field when FLCOUNT VINTn This allows the software to synchronize itself to the frame or field The interrupt can be programmed to occur in one both or no fields using the VIF1 and VIF2 bits Figure 4 64 Video Display Vertical Interrupt Register VDVINT 31 30 28 27 16 R W 0 R 0 R W 0 15 14 12 11 0 R W 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 4 30 Video Display Vertical Interrupt Register VDVINT Field Descriptions Bit fieldt symvalt Value Description 31 VIF2 Vertical interrupt VINT in field 2 enable bit DISABLE 0 Vertical interrupt VINT in field 2 is disabled ENABLE 1 Vertical interrupt VINT in field 2 is enabled 30 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 VINT2 OF value O FFFh Line where vertical interrupt VINT occurs if VIF2 bit is set 15 VIF1 Vertical interrupt VINT in field 1 enable bit DISABLE 0 Vertical interrupt VINT in field 1 is disabled ENABLE 1 Vertical interrupt VINT in field 1 is enabled 14 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 VINT1 OF value O FFFh Line where vertical interrupt VINT o
211. ers The VICDIV and VICCTL except for the GO bit registers cannot be written If a write is performed to the VICDIV or VICCTL registers when the GO bit is set the values of these registers remain unchanged If a write is performed that clears the GO bit to 0 and changes the values of other VICCTL bits it results in GO 0 while keeping the rest of the VICCTL bits unchanged The VIC port is in its normal working mode in this state t For CSL implementation use the notation VIC VICCTL field symval SPRU629 VCXO Interpolated Control Port 6 7 VIC Port Registers 6 5 2 VIC Input Register VICIN The DSP writes the input bits for VCXO interpolated control in the VIC input register VICIN The DSP decides how often to update VICIN The DSP can write to VICIN only when the GO bit in the VIC control register VICCTL is set to 1 The VIC module uses the MSBs of VICIN for precision values less than 16 The VICIN is shown in Figure 6 4 and described in Table 6 5 Figure 6 4 VIC Input Register VICIN 31 16 R 0 15 a RIW 0 Legend R Read only R W Read Write n value after reset Table 6 5 VIC Input Register VICIN Field Descriptions Bit Field symvalt Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 0 VICINBITS OF value 8 O FFFFh The DSP writes the input bits for VCXO interpolated control to the VIC input bits t
212. erved The reserved bit location is always read as 0 A value written to this field has no effect 22 PDIR22 PDIR22 bit controls the direction of the VCTL3 pin VCTL3IN 0 Pin functions as input VCTLSOUT 1 Pin functions as output t For CSL implementation use the notation VP_PDIR_field_symval ol 8 General Purpose I O Operation SPRU629 GPIO Registers Table 5 5 Video Port Pin Direction Register PDIR Field Descriptions Continued Bit fieldt symvalt Value Description 21 PDIR21 PDIR21 bit controls the direction of the VCTL2 pin VCTL2IN Pin functions as input VCTL20UT Pin functions as output 20 PDIR20 PDIR20 bit controls the direction of the VCTL1 pin VCTL1IN Pin functions as input VCTL1OUT Pin functions as output 19 17 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 16 PDIR16 VDATA16TO19IN VDATA16TO19OUT PDIR16 bit controls the direction of the VDATA 19 16 pins Pins function as input Pins function as output 15 13 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 12 PDIR12 VDATA12TO15IN VDATA12TO15OUT PDIR12 bit controls the direction of the VDATA 15 12 pins Pins function as input Pins function as output 11 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 10
213. es and 80 0h for chroma Cb Cr samples These values are also output during the active line period of vertical blanking between SAV and EAV when V 1 unless replaced by VBI data In addition if the DVEN bit in VDCTL is 0 the blanking values are output during the portion of active video lines that are not a part of the displayed image 4 3 3 Y C Image Display Many of the standards supported by the Y C display mode provide for both interlaced and progressive scan formats For interlaced display the display controls are programmed identically to BT 656 mode For progressive scan formats the frame size is programmed to the size of a single field and only field 1 is used The Y C display mode uses the same FIFO organization as the BT 656 display mode and generates DMA events in the same manner 4 3 4 Y C FIFO Unpacking SPRU629 Display data is always packed into the FIFOs in 64 bit words and must be unpacked before being sent to the display data pipeline The unpacking and byte ordering is dependant upon the display data size and the device endian mode For little endian operation default data is unpacked from right to left for big endian operation data is unpacked from left to right Video Display Port 4 17 Y C Video Display Mode The 8 bit Y C mode uses three FIFOs for color separation Four samples are unpacked from each word as shown in Figure 4 16 Figure 4 16 8 Bit Y C FIFO Unpacking vexout LI LI LILI LI LI LIU L
214. es high 19 0 PDOUT 19 0 VDATAnLO VDATAnHI PDOUT 19 0 bit drives the corresponding VDATA 19 0 pin only when the GPIO is configured as output When reading data returns the bit value in PDOUT n does not return input from pin When writing data writes to PDOUT 7 bit Pin drives low Pin drives high T For CSL implementation use the notation VP PDOUT PDOUTn symval 5 14 General Purpose I O Operation SPRU629 GPIO Registers 5 1 7 Video Port Pin Data Set Register PDSET The video port pin data set register PDSET is shown in Figure 5 7 and described in Table 5 8 PDSET is an alias ofthe video port pin data output reg ister PDOUT for writes only and provides an alternate means of driving GPIO outputs high Writing a 1 to a bit of PDSET sets the corresponding bit in PDOUT Writing a 0 has no effect Register reads return all Os Figure 5 7 Video Port Pin Data Set Register PDSET 31 24 R 0 23 22 21 20 19 18 17 16 PDSET22 PDSET21 PDSET20 PDSET19 PDSET18 PDSET17 PDSET16 R 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 PDSET15 PDSET14 PDSET13 PDSET12 PDSET11 PDSET10 PDSET9 PDSET8 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 7 6 5 4 3 2 1 0 PDSET7 PDSETe PDSET5 PDSET4 PDSET3 PDSET2 PDSET1 PDSETO W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 Legend R Read only W Write only n value after reset SPRU629 General Purpose O Operation 5 15 GPIO Registers Table 5 8 Vide
215. eserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 VBLNKXSTOP2 OF value O FFFh Specifies the pixel in Specifies the pixel in FPCOUNT where VBLNK inactive edge occurs for field 2 FPCOUNT where vertical blanking ends VBLNK inactive edge for field 2 t For CSL implementation use the notation VP_VDVBLKE2_field_symval 4 12 9 Video Display Field 1 Image Offset Register VDIMGOFF1 The video display field 1 image offset register VDIMGOFF1 defines the field 1 image offset and specifies the starting location of the displayed image relative to the start of the active display The VDIMGOFF1 is shown in Figure 4 47 and described in Table 4 14 The image line counter ILCOUNT is reset to 1 on the first image line when FLCOUNT VBLNKYSTOP1 IMGVOFF1 If the NV bit is set ILCOUNT is reset to 1 when FLCOUNT VBLNKYSTOP1 IMGVOFF1 Display image pixels are output in field 1 beginning on the line where ILCOUNT 1 The default output values or blanking values are output during active lines prior to ILCOUNT 1 For a negative offset IMGVOFF1 must not be greater than VBLNKYSTOP1 The field 1 active image must not overlap the field 2 active image The image pixel counter IPCOUNT is reset to 0 at the start of an active line image Once ILCOUNT 1 image pixels from the FIFO are output on each line in field 1 beginning when FPCOUNT IMGHOFF1 If the NH bit is
216. ex VDCLIP VDCTL voverat t PPR oo Oo lt iw gJ 0p ES 3 B Co BR VDFBIT 4 89 VDFLD bit VDFLDT1 4 VDFLDT2 VDFRMSZ VDHBLNK VDHSYNC VDIMGOFF VDIMGOFF VDIMGSZ1 VDIMGSZ VDRELOA VDSTAT 4 53 VDTHRLD 4 76 VDTHRLD1 bits VDTHRLD2 bits VDVBIT1 VDVBIT2 VDVBLKE1 VDVBLKE2 VDVBLKS1 VDVBLKS2 VDVINT 4 VDVSYNE VDVSYNE VDVSYNS1 VDVSYNS2 VDXPOS bit B F BR H RID 7 Blg N a BBL e ST STS TSS fea ea BHO S allo co Bb o Po Qo il FS FS FS ES D gt D D Ci N N A po C0 co co ANO NO 4 5 4 53 VIC clock divider register VICDIV VIC control register VICCTL VIC input register VICIN VIC port enabling features interface operational details overview registers 6 5 a Co lt O lt U O 0p o LG A ol Co Index 8 VICCLKDIV bits VICCTL VICDIV VICIN 6 8 VICINBITS bits video capture FIFO configurations FIFO registers mode selection overview registers signal mapping 1 throughput video capture channel A control register VCACTL video capture channel A event count register VCAEVTCT video capture channel A field 1 start register VCASTRT1 video capture channel A field 1 stop register VCASTOP1 video capture channel A field 2 start register VCASTRT2 video capture channel A field 2 stop register VCASTOP2 video capture channel A status register VCASTAT video capture channel A t
217. fication 0 ccc cece 3 8 6 Writing to the FIFO LA I s 3 8 7 Reading from the FIFO 0 e cece eee eens 3 9 Capture Line Boundary Conditions 0 cece tee 3 10 Capturing Video in BT 656 or Y C Mode 022 3 10 1 Handling FIFO Overrun in BT 656 or Y C Mode aaa 3 11 Capturing Video in Raw Data Mode eanan nananana teed 3 11 1 Handling FIFO Overrun Condition in Raw Data Mode 3 12 Capturing Data in TSI Capture Mode 2 aa 3 12 1 Handling FIFO Overrun Condition in TSI Capture Mode 3 13 Video Capture Registers cc cece teen 3 13 1 Video Capture Channel x Status Register VCASTAT VCBSTAT 3 13 2 Video Capture Channel A Control Register VCACTL 3 13 3 Video Capture Channel x Field 1 Start Register VCASTRT1 VCBSTRT1 0 000 cece cece eee ee eee teenies 3 13 4 Video Capture Channel x Field 1 Stop Register VCASTOP4 WEBSIIODI Y lllllueeeell IRR IRI 3 13 5 Video Capture Channel x Field 2 Start Register VCASTRT2 VCBSTRT2 00 0 cece cece eee s n 3 13 6 Video Capture Channel x Field 2 Stop Register VCASTOP2 VCBSTOP2 0 c cece cece ees 3 13 7 Video Capture Channel x Vertical Interrupt Register VCAVINT VCBVINT 0 0 III HI rns 3 13 8 Video Capture Channel x Threshold Register VCATHRLD VCBTHRLD 0 0 cece eee eee teen n 3 13
218. field 1 vertical blanking start register VDVBLKS1 video display field 1 vertical synchronization end register VDVSYNE1 video display field 1 vertical synchronization start register VDVSYNS1 video display field 2 image offset register VDIMGOFF2 SPRU629 Index video display field 2 image size register VDIMGSZ2 video display field 2 timing register VDFLDT2 video display field 2 vertical blanking bit register VDVBIT2 video display field 2 vertical blanking end register VDVBLKE2 video display field 2 vertical blanking start register VDVBLKS2 video display field 2 vertical synchronization end register VDVSYNE2 video display field 2 vertical synchronization start register VDVSYNS2 video display field bit register VDFBIT video display FIFO configurations 1 9 video display frame size register VDFRMSZ video display horizontal blanking register VDHBLNK video display horizontal synchronization register VDHSYNO video display mode BT 656 display selection display timing examples field and frame operation raw data Y C video display status register VDSTAT video display threshold register VDTHRLD video display vertical interrupt register VDVINT video input filtering video output filtering video port block diagram 1 4 clocks control registers 2 16 DMA interface 1 5 DMA operation FIFO configurations interrupt operation operating mode selection overview
219. field symval SPRU629 Video Display Port 4 79 Video Display Registers 4 12 18 Video Display Field 1 Vertical Synchronization End Register VDVSYNE1 The video display field 1 vertical synchronization end register VDVSYNE1 controls the end of vertical synchronization in field 1 The VDVSYNE1 is shown in Figure 4 56 and described in Table 4 23 Generation of the vertical synchronization is shown in Figure 4 6 page The VSYNC signal is deasserted wheneverthe frame line counter FLCOUNT is equal to VSYNCYSTOP1 and the frame pixel counter FPCOUNT is equal to VSYNCXSTOP1 Figure 4 56 Video Display Field 1 Vertical Synchronization End Register VDVSYNE 1 31 28 27 16 R 0 R W 0 15 12 11 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 4 23 Video Display Field 1 Vertical Synchronization End Register VDVSYNE 1 Field Descriptions Bit fieldt symvalt Value Description 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 VSYNCYSTOP1 OF value O FFFh Specifies the line where VSYNC is deasserted for field 1 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 VSYNCXSTOP1 OF value O FFFh Specifies the pixel where VSYNC is deasserted in field 1 t For CSL implementation use the notation VP_VDVSYNE1_field_symval 4 80 Video Displ
220. for HANC data output 14 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 IMGHOFF2 OF value O FFFh Specifies the display image Specifies the display image horizontal offset in pixels from the start of each line of active video in field 2 This must be an even number the LSB is treated as 0 T For CSL implementation use the notation VP VDIMGOFF2 field symval 4 72 Video Display Port horizontal offset in pixels from the start of each line of active video in field 2 SPRU629 Video Display Registers 4 12 12 Video Display Field 2 Image Size Register VDIMGSZ2 The video display field 2 image size register VDIMGSZ2 defines the field 2 image area and specifies the size of the displayed image within the active dis play The VDIMGSZ2 is shown in Figure 4 50 and described in Table 4 1 7 The image pixel counter IPCOUNT counts displayed image pixel output on each of the displayed image Displayed image pixel output stops when IPCOUNT IMGHSIZE2 The default output values or blanking values are output for the remainder of the active line The image line counter ILCOUNT counts displayed image lines Displayed image output stops when ILCOUNT IMGVSIZE2 The default output values or blanking values are output for the remainder of the active field Figure 4 50 Video Display Field 2 Image Size Register VDIMGSZ2 31 28 27 16 R 0 R W 0 15 1
221. for color separation Four samples are unpacked from each word as shown in Figure 4 12 Figure 4 12 8 Bit BT 656 FIFO Unpacking VboUT 63 5655 4847 4039 3231 2423 1615 87 0 Y 31 Y 30 Y 29 Y 28 Y 27 Y 26 Y 25 Y 24 Y 23 Y 22 Y 21 Y 20 Y 19 Y 18 Y17 Y 16 Y 15 Y 14 Y 13 Y 12 Y11 Y10 Y9 Y8 Y FIFO Y7 Y6 Y5 Y4 Y3 Y2 Y 1 YO 63 5655 4847 4039 3231 2423 1615 87 0 4 Cb 15 Cb 14 Cb 13 Cb 12 Cb 11 Cb 10 Cb 9 Cb8 Cb FIFO Cb7 Cb6 Cb5 Cb 4 Cb 3 Cb 2 Cb 1 Cb 0 63 5655 4847 4039 3231 2423 1615 87 0 4 Cr15 Cr 14 Cr 13 Cr12 Cr 11 Cr10 Cr9 Cr 8 Cr FIFO Cr 7 Cr 6 Cr 5 Cr4 Cr3 Cr2 Cr1 Cro Little Endian Unpacking 63 5655 4847 4039 3231 2423 1615 87 0 Y 24 Y 25 Y 26 Y 27 Y 28 Y 29 Y 30 Y 31 Y 16 Y 17 Y 18 Y 19 Y 20 Y 21 Y 22 Y 23 Y8 Y9 Y 10 Y 11 Y 12 Y 13 Y14 Y 15 Y FIFO YO Y 1 Y2 Y3 Y4 Y5 Y6 Y7 63 5655 4847 4039 3231 2423 1615 87 0 Cb8 Cb9 Cb 10 Cb 11 Cb 12 Cb 13 Cb 14 Cb 15 Cb FIFO Cb 0 Cb 1 Cb 2 Cb 3 Cb4 Cb 5 Cb6 Cb7 63 5655 4847 4039 3231 2423 1615 87 0 Cr8 Cr9 Cr 10 Cr 11 Cr 12 Cr 13 Cr 14 Cr 15 Cr FIFO Cro Cr 1 Cr2 Cr3 Cr4 Cr 5 Cr 6 Cr7 Big Endian Unpacking SPRU629 Video Display Port 4 13 BT 656 Video Display Mode For 10 bit BT 656 operation two samples are unpacked from each word as shown in Figure 4 13 Figure 4 13 10 Bit BT 656 FIFO Unpacking
222. from the start of each line of active video in field 1 This must be an even number the LSB is treated as 0 T For CSL implementation use the notation VP VDIMGOFF1 field symval SPRU629 Video Display Port horizontal offset in pixels from the start of each line of active video in field 1 4 69 Video Display Registers 4 12 10 Video Display Field 1 Image Size Register VDIMGSZ1 The video display field 1 image size register VDIMGSZ1 defines the field 1 image area and specifies the size of the displayed image within the active dis play The VDIMGSZ1 is shown in Figure 4 48 and described in Table 4 15 The image pixel counter IPCOUNT counts displayed image pixel output on each of the displayed image Displayed image pixel output stops when IPCOUNT IMGHSIZE1 The default output values or blanking values are output for the remainder of the active line The image line counter ILCOUNT counts displayed image lines Displayed image output stops when ILCOUNT IMGVSIZE1 The default output values or blanking values are output for the remainder of the active field Figure 4 48 Video Display Field 1 Image Size Register VDIMGSZ1 31 28 27 16 R 0 R W 0 15 12 11 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 4 15 Video Display Field 1 Image Size Register VDIMGSZ1 Field Descriptions Description Bit fieldt symvalt Value BT 656 and Y C Mode Raw Data Mode 31 28 Reserved
223. g VCXSTRT to occur before the SAV when HCOUNT is reset by the EAV code or by programming VCXSTOP to occur past the EAV code when HCOUNT is reset by the SAV code Note that the EAV code and any subsequent HANC data will still be YCbCr separated Software must parse the Y Cb and Cr memory buffers to determine any HANC data presence and to reconstruct the HANC data The VCTHRLD value and DMA size must be programmed to comprehend the additional samples You must disable scaling and chroma re sampling when including the capture of HANC data to prevent data corruption 3 6 2 Vertical Ancillary VANC Data Capture SPRU629 VANC or VBI data is commonly used for such features as teletext and closed captioning No special provisions are made for the capture of VBI data VBI data may be captured using the normal capture mechanism by programming VCYSTART to occur before the first line of active video on the first line of desired VBI data VCOUNT must be reset by an EAV with V 1 Note that the VBI data will be YCbCr separated Software must parse the Y Cb and Cr memory buffers to determine any VBI data presence and to reconstruct the VBI data You must disable scaling and chroma resampling when the capture of VBI data is desired or the data will be corrupted by the filters Video Capture Port 3 31 Raw Data Capture Mode 3 7 Raw Data Capture Mode In the raw data capture mode the data is sampled by the interface only when the CAPEN signal
224. g Underrun Condition of the Display FIFO SPRU629 A FIFO underrun occurs when the display FIFO is empty during an active display line because a pending DMA request failed to load the data in time In case of a FIFO underrun condition the DUND bit in VPIS is set This condition initiates an interrupt to the DSP if the underrun interrupt is enabled the DUND bit in VPIE is set Because video display is typically a continuous real time output data output is not halted when a FIFO underrun occurs To output a blanking of default value is just as catastrophic to a display as outputting an old data value Instead the FIFO read pointer continues to advance and old data continues to be output from the FIFO This means that if the pending DMA is only slightly late the data transfer has a chance to catch the FIFO back up to the read pointer and correct data output resumes If the pending DMA does not complete service within a threshold s worth of output data then the DMA request sequence is broken and the remainder of the display field is corrupted The underrun interrupt routine should set the BLKDIS bit in VDCTL and it should reconfigure the DMA channel settings Setting the BLKDIS bit flushes the channel display FIFO and prevents channel DMA events from reaching the DMA controller The DMA must be reconfigured correctly for the next frame display since the current frame transfer failed The frame line and frame pixel counters continue counting
225. g a 0 has no effect Register reads return all Os Figure 5 8 Video Port Pin Data Clear Register PDCLR 31 24 R 0 23 22 21 20 19 18 17 16 PDCLR22 PDCLR21 PDCLR20 PDCLR19 PDCLR18 PDCLR17 PDCLR16 R 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 15 14 13 12 11 10 9 8 PDCLR15 PDCLR14 PDCLR13 PDCLR12 PDCLR11 PDCLR10 PDCLR9 PDCLR8 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 7 6 5 4 3 2 1 0 PDCLR7 PDCLR6 PDCLR5 PDCLR4 PDCLR3 PDCLR2 PDCLR1 PDCLRO W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 Legend R Read only W Write only n value after reset SPRU629 General Purpose I O Operation 5 17 GPIO Registers Table 5 9 Video Port Pin Data Clear Register PDCLR Field Descriptions Bit fieldt symvalt Value Description 31 23 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 22 PDCLR22 Allows PDOUT22 bit to be cleared to a logic low without affecting other I O pins controlled by the same port NONE 0 No effect VCTL3CLR 1 Clears PDOUT22 VCTL3 bit to 0 21 PDCLR21 Allows PDOUT21 bit to be cleared to a logic low without affecting other I O pins controlled by the same port NONE 0 No effect VCTL2CLR 1 Clears PDOUT21 VCTL2 bit to 0 20 PDCLR20 Allows PDOUT20 bit to be cleared to a logic low without affecting other I O pins controlled by the same port NONE 0 No effect VCTL1CLR 1 Clears PDOUT20 VCTL1 bit to 0 19 0 PDCLR 19 0 Allows PDOUT 1 9 0 bit to be
226. ge for Capture Modes Capture Mode BT 656 Y C Raw Data BEER TSI Data Bus 10 Bit 8 Bit 10 Bit 8 Bit 8 Bit 10 Bit 16 Bit 20 Bit Mode VDIN19 B B A C A C B B A A VDIN18 B B A C A C B B A A VDIN17 B B A C A C B B A A VDIN16 B B A C A C B B A A VDIN15 B B A C A C B B A A VDIN14 B B A C A C B B A A VDIN13 B B A C A C B B A A VDIN12 B B A C A C B B A A VDIN11 B A C B A VDIN10 B A C B A VDIN9 A A A Y A Y A A A A A VDIN8 A A A Y A Y A A A A A VDIN7 A A A Y A Y A A A A A VDIN6 A A A Y A Y A A A A A VDIN5 A A A Y A Y A A A A A VDIN4 A A A Y A Y A A A A A VDIN3 A A A Y A Y A A A A A VDIN2 A A A Y A Y A A A A A VDIN1 A A Y A A VDINO A A Y A A Legend A Channel A capture A C Channel A chroma A Y Channel A luma B Channel B capture SPRU629 Overview 1 15 Video Port Pin Mapping 1 4 2 VDOUT Data Bus Usage for Display Modes The alignment and usage of data on the VDOUT bus depends on the display mode as shown in Table 1 4 Table 1 4 VDOUT Data Bus Usage for Display Modes Data Bus VDOUT19 VDOUT18 VDOUT17 VDOUT16 VDOUT15 VDOUT14 VDOUT13 VDOUT12 VDOUT11 VDOUT10 VDOUT9 VDOUT8 VDOUT7 VDOUT6 VDOUT5 VDOUT4 VDOUT3 VDOUT2 VDOUT1 VDOUTO BT 656 10 Bit gt gt DoD S S 5S 5S DD 8 Bit gt gt gt S S 5S DD Display Mode 8 Bit 8 Bit A C B A C B A C B A C B A C B A C B A C B A C B A
227. ge when CAPENkx is active DMA events YEVTx are generated as triggered by VCxTHRLD1 When a complete data block has been captured DCOUNT VCYSTOP and VCXSTOP combined value the FRMC bit in VCxSTAT is set causing the CCMP x bit in VPIS to be set This generates a DSP interrupt if CCMPx is enabled in VPIE If continuous capture is enabled the video port begins capturing again on the next VCLKIN rising edge when CAPEN is valid If noncontinuous capture is enabled the next data block is captured during which the DSP must clear the FRMC bit or further capture is disabled If single frame capture is enabled capture is disabled until the DSP clears the FRMC bit at which point raw data sync must again be performed if enabled 3 46 Video Capture Port SPRU629 Capturing Video in Raw Data Mode Capturing Data in TSI Capture Mode 3 11 1 Handling FIFO Overrun Condition in Raw Data Mode In case of a FIFO overrun the COVRxbit is set in VPIS This condition initiates an interrupt to the DSP if the overrun interrupt is enabled setting the COVRx bit in VPIE enables overrun interrupt The overrun interrupt routine should set the BLKCAP bit in VCxCTL and it should reconfigure DMA channel settings The DMA channel must be reconfi gured for capture of the next frame since the current frame transfer failed Set ting the BLKCAP bit flushes the capture FIFO and blocks DMA events for the channel As long as the BLKCAP bit is set the video capture c
228. ged like ping pong and round Af robin etc Ef Va A 8 Video Port Configuration Examples SPRU629 Example 1 Noncontinuous Frame Capture for 525 60 Format void configVPCapEDMAChannel EDMA Handle edmaHandle Int32 eventId Int32 tccNum Uint32 srcAddr Uint32 dstAddr Uint32 frameCount Uint32 elementCount Int32 tcc 0 Open Y EVT EDMA channel x edmaHandle EDMA open eventId EDMA OPEN RESET if edmaHandle EDMA HINV test exit FAIL allocate TCC for Y event if tcc EDMA intAlloc 1 1 test exit FAIL Configure EDMA parameters Ey EDMA_configArgs edmaHandle EDMA OPT RMK EDMA OPT PRI MEDIUM medium priority EDMA OPT ESIZE 32BIT Element size 32 bits EDMA OPT 2DS NO 1 dimensional source FIFO EDMA OPT SUM NONE fixed src address mode FIFO EDMA OPT 2DD YES 2 dimensional destination X EDMA OPT DUM INC destination increment x4 EDMA OPT TCINT YES Enable transfer complete Ki indication x EDMA OPT TCC OF tcc amp OxF EDMA OPT TCCM OF tcc amp 0x30 gt gt 4 EDMA OPT ATCINT NO Disable Alternate Transfer Complete Interrupt Ty EDMA OPT ATCC OF 0 EDMA OPT PDTS DISABLE disable PDT peripheral device transfer mode for source EDMA OPT PDTD DISABLE
229. hannel ignores the incoming data but the internal data counter continues counting The BLKCAP bit should be cleared to 0 in order to continue capture Clearing the BLKCAP bit takes effect in the subsequent frame after a raw data sync period is detected on CAPENx DMA events are still going to be blocked in the frame in which the BLKCAP bit is cleared 3 12 Capturing Data in TSI Capture Mode SPRU629 In order to capture data in TSI capture mode the following steps are needed 1 Set VCASTOP 1 to specify size of a data packet to be captured VCXSTOP sets the lower 12 bits and VCYSTOP sets the upper 12 bits of the data packet 2 Write to VCxTHRLD to set the capture threshold to the data packet size Every time the number of received bytes reaches the number specified by the VCTHRLD 1 bits a YEVTxis generated by the video capture module 3 Configure a DMA channel to move data from YSRCA to a destination in the DSP memory The channel transfers should be triggered by the VIDEVTA The size of the transfers should be set to the data packet size 8 bytes of timestamp information The DMA must start on a double word boundary and move an even number of words 4 Write to TSICTL to O SetTSI capture mode TCMODE 0for parallel data 1 for serial data LJ Select counter mode TCMODE Enable error packet filtering ERRFILT if desired 5 In Sigma Delta peripheral Write to the SDCTL register to set the precision for the Sigma
230. high impedance state unless enabled as GPIO by the PFUNC bits SPRU629 Reset Operation If software sets the PEREN bit in PCR but the VPHLT bit in VPCTL remains set VCLK1 VCLK2 and STCLK are enabled to the port allowing logic reset to complete L Peripheral bus accesses are acknowledged RREADY WREADY returned to prevent DMA lock up Any value returned on reads data accepted or discarded on writes L Peripheral bus MMR interface allows access to all registers Port Os VD 19 0 VCTL1 VCTL2 VCTL3 and VCLK2 remain in a high impedance state unless enabled as GPIO by the PFUNC bits VPCTL bits may be set until the VPHLT bit is cleared 2 1 3 Software Port Reset A software port reset may be performed on the entire video port by setting the VPRST bit in VPCTL This behaves identically to the peripheral bus reset except that it does not clear the PEREN bit in PCR This reset Od Performs an asynchronous reset on all port logic channel logic may stay in reset until port input clock pulses occur Lj Self clears the VPRST bit to O but leaves the VPHLT bit set Once the port is configured and the VPHLT bit is cleared the setting of other VPCTL bits except VPRST is disabled The VCLK2 output may also be driven atthis time if display mode is selected VCTL1 3 must remain in a high imped ance state unless enabled as GPIO since internal external sync is selected through VDCTL 2 1 4 Capt
231. hose output in BT 656 mode and timing is controlled in the same manner In Y C mode how ever the codes must be output on both the Y and C data streams VDOUT 9 0 and VDOUT 19 10 An example of BT 1120 line timing is shown in Figure 4 15 Figure 4 15 Y C Horizontal Blanking Timing BT 1120 601 pi One Line Me Next Line S A QI S QI e e ITS 7 HS ATAT YI aW FPCOUNT lololol a 3 a 9 TANAN TYO NP 5 3 2 5 ala A alala vekkout UUUUUUUU ununnunuuvy WU Kt 4 272 m 4 1920 Blanking s Active Video VDOUT S 0 igsgzeese S E S S X gt gt gt gt gt gt 2 2 8 8s9sse gt gt gt gt SS NI NAIA EAV Blanking Data SAV EAV eo D o HQ 9 9 9 9 9 9 9 AAO SS 9 o of Yu I5 aa VDOUT 19 10 i SSZ gg oe 9ESSgSzS3oo9o2o9o0 8 5 8 5 III 39s EAV Blanking Data SAV EAV 4 16 Video Display Port SPRU629 Y C Video Display Mode 4 3 2 Y C Blanking Codes The time between the EAV and SAV code on each line represents the horizon tal blanking interval During this time the video port outputs the digital video blanking values These values are 10 0h for luma Y sampl
232. hput and Latency Some low cost device implementations with narrow video ports width or restricted to lower video frequency operations may use a reduced FIFO size FIFO size does not affect the DMA request mechanism The selection of 8 bit or 10 bit port width automatically cuts the FIFO size in half with support for only a single channel of operation 2 6 Video Port Throughput and Latency Because of the large amount of buffering provided within the video port and the programmable threshold used to generate DMA events the required DMA latency is difficult to calculate Because video data is real time the video port s external interface may not be stalled so module throughput must be maintained 2 6 14 Video Capture Throughput SPRU629 In order to maintain throughput during video capture operation the capture FIFO must be emptied at a faster rate than it is filled The time to completely fill the capture FIFO may be represented by the formula tp n ty where tp is the time to fill the FIFO with active samples ty is the horizontal blanking time and n is the number of lines of active video that the FIFO can hold Maximum throughput requirements for capture occur during HDTV resolution Y C mode The BT 1120 standard 1125 line 60 Hz mode specifies a line size of 2200 Y samples 1920 active and 1100 ea Cb and Cr samples 960 ea active at a sample rate of 74 25 MHz This means that the horizontal blanking time is 280 74 25 MHz or 3 77 u
233. hreshold register VCATHRLD video capture channel A vertical interrupt register VCAVINT video capture channel B control register VCBCTL video capture channel B event count register VCBEVTCT video capture channel B field 1 start register VCBSTRT1 video capture channel B field 1 stop register VCBSTOP1 video capture channel B field 2 start register VCBSTRT2 video capture channel B field 2 stop register VCBSTOP2 video capture channel B status register VCBSTAT video capture channel B threshold register VCBTHRLD SPRU629 video capture channel B vertical interrupt register VCBVINT video capture FIFO configurations 1 6 video capture mode video display counters external sync operation FIFO registers image timing mode selection port sync operation registers recommended values signal mapping sync signal generation throughput video display clipping register VDCLIP 4 85 video display control register VDCTL video display counter reload register VDRELOAD video display default display value register VDDEFVAL video display display event register VDDISPEVT video display field 1 image offset register VDIMGOFF1 video display field 1 image size register VDIMGSZ1 video display field 1 timing register VDFLDT1 video display field 1 vertical blanking bit register VDVBIT1 video display field 1 vertical blanking end register VDVBLKE1 video display
234. ibed in Table 4 20 The VDTHRLDn bits determines how much space must be available in the display FIFOs before the appropriate DMA event may be generated The Y FIFO uses the VDTHRLDn value directly while the Cb and Cr values use the VDTHRLDn value rounded up to the next doubleword 1 2 VDTHRLDn VTHRLDn mod 2 The DMA transfer size must be less than the value used for each FIFO Typically VDTHRLDnis setto the horizontal line length rounded up to the next doubleword boundary For nonline length thresholds the display data unpacking mechanism places certain restrictions of what VDTHRLDn values are valid see section 2 3 3 The VDTHRLD2 bits behaves identically to VDTHRLD1 but are used during field 2 capture It is only used if the field 2 DMA size needs to be different from the field 1 DMA size for some reason for example different display line lengths in field 1 and field 2 In raw display mode the INCPIX bits determine when the frame pixel counter FPCOUNT is incremented If for example each output value represents the R G or B portion of a display pixel then the INCPIX bits are set to 3h so that the pixel counter is incremented only on every third output clock An INCPIX value of Oh represents a count of 16 rather than 0 Figure 4 53 Video Display Threshold Register VDTHRLD 31 26 25 16 R 0 R W 0 15 12 11 10 9 0 R W 0001 R 0 R W 0 Legend R Read only R W Read Write n value after reset 4 76 Video Displa
235. ideo Display Registers 4 12 24 Video Display Default Display Value Register VDDEFVAL The video display default display value register VDDEFVAL defines the default value to be output during the portion of the active video window that is not part of the displayed image The VDDEFVAL is shown in Figure 4 62 for the BT 656 and Y C modes and in Figure 4 63 for the raw data mode and described in Table 4 29 The default value is output during the nonimage display window portions of the active video This is the region between ILCOUNT 0 and ILCOUNT IMGVOFFn vertically and between IPCOUNT 0 and IPCOUNT IMGHOFFn horizontally In BT 656 mode CBDEFVAL YDEFVAL and CRDEFVAL are multiplexed on the output in the standard CbYCrY manner In Y C mode YDEFVAL is output on the VDOUT 9 0 bus and CBDEFVAL and CRDEFVAL are multiplexed on the VDOUT 19 10 bus In all cases the default values are output on the 8 MSBs of the bus 9 2 or 19 12 and the 2 LSBs 1 0 or 11 10 are driven as Os In raw data mode the least significant 8 10 16 or 20 bits of DEFVAL are output depending on the bus width The default value is also output during the horizontal and vertical blanking periods in raw data mode The default value is also output during the entire active video region when the BLKDIS bit in VDCTL is set and the FIFO is empty Figure 4 62 Video Display Default Display Value Register VDDEFVAL 31 24 23 16 R W 0 R W 0 1
236. iguration 0 cc ccc cette eens 2 1 Capture DMA Event Generation Flow Diagram 2 222 0c cece eee eee eee 2 2 Display DMA Event Generation Flow Diagram 0 cece eee eee 2 3 Video Port Control Register VPCTL III 2 4 Video Port Status Register VPSTAT eere 2 5 Video Port Interrupt Enable Register VPIE 00 cece eee eee ees 2 6 Video Port Interrupt Status Register VPIS 0 0 c cece eee eee eee 3 1 Video Capture Parameters 2 c cece ccc hs 3 2 8 Bit BT 656 FIFO Packing 2 een eee eens 3 3 10 Bit BT 656 FIFO Packing 0 c ccc eects 3 4 10 Bit BT 656 Dense FIFO Packing 2 eae 3 5 8 Bitg C RISO Packing AA te tence III 3 6 1O5Bit WiC FRO Packing AKA AA 3 7 10 Bit Y C Dense FIFO Packing 00 cece eee III 3 8 VCOUNT Operation Example EXC 0 2 0 ccc eee eee 3 9 HCOUNT Operation Example EXC 20 sssssssesessses nh 3 10 HCOUNT Operation Example EXC 1 2 2 2a eee eee 3 11 Field 1 Detection Timing IRR 3 12 Chrominance Resampling tenet ee eae 3 13 1 2 Scaled Co Sited Filtering AA tenets 3 14 1 2 Scaled Chrominance Resampled Filtering 0 0c cece eee eee eee 3 15 Edge Pixel Replication usce rtr reme NA BRA sankey wane a de 3 16 Capture Window Not Requiring Edge Pixel Replication a 3 17 8 Bit Raw Dat
237. ime clock compare LSB register TSISTCMPL is used to generate an interrupt at some absolute time based on the STC TSISTCMPL holds the 32 least significant bits LSBs of the absolute time compare ATC Whenever the value in TSISTCMPL and TSISTCMPM match the unmasked bits of the time kept by the STC hardware counter and the STEN bit in TSICTL is set the STC bit in VPIS is set TSISTCMPL is shown in Figure 3 44 and described in Table 3 29 To prevent inaccurate comparisons caused by changing register bits the software should disable the system time clock interrupt clear the STEN bit in TSICTL prior to writing to TSISTCMPL Figure 3 44 TSI System Time Clock Compare LSB Register TSISTCMPL 31 0 ATC R W 0 Legend R W Read Write n value after reset Table 3 29 TSI System Time Clock Compare LSB Register TSISTCMPL Field Descriptions Description BT 656 Y C Mode Bit Field symvalt Value or Raw Data Mode 31 0 ATC OF value O FFFF FFFFh Not used TSI Mode Contains the 32 LSBs of the absolute time compare t For CSL implementation use the notation VP_TSISTCMPL_ATC_symval 3 78 Video Capture Port SPRU629 Video Capture Registers 3 13 17 TSI System Time Clock Compare MSB Register TSISTCMPM The transport stream interface system time clock compare MSB register TSISTCMPM is used to generate an interrupt at some absolute time based onthe STC TSISTCMPM holds the most significant bit MSB of the absolute t
238. ime compare ATC Whenever the value in TSISTCMPM and TSISTCMPL match the unmasked bits of the time kept by the STC hardware counter and the STEN bit in TSICTL isset the STC bitin VPIS is set TSISTCMPM is shown in Figure 3 45 and described in Table 3 30 To prevent inaccurate comparisons caused by changing register bits the software should disable the system time clock interrupt clear the STEN bit in TSICTL prior to writing to TSISTCMPM Figure 3 45 TSI System Time Clock Compare MSB Register TSISTCMPM 31 1 0 ATO R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 3 30 TSI System Time Clock Compare MSB Register TSISTCMPM Field Descriptions Description BT 656 Y C Mode Bit Field symvalt Value or Raw Data Mode TSI Mode 31 1 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 ATC OF value 0 1 Not used Contains the MSB of the absolute time compare t For CSL implementation use the notation VP TSISTCMPM ATC symval SPRU629 Video Capture Port 3 79 Video Capture Registers 3 13 18 TSI System Time Clock Compare Mask LSB Register TSISTMSKL The transport stream interface system time clock compare mask LSB register TSISTMSKL holds the 32 least significant bits LSBs of the absolute time compare mask ATCM This value is used with TSISTMSKM to mask out bits during the comparison of the ATC to the system time clock for
239. in Figure 5 5 and described in Table 5 6 PDIN reflects the state of the video port pins When read PDIN returns the value from the pin s input buffer with appropriate synchronization regardless of the state of the corresponding PFUNC or PDIR bit Figure 5 5 Video Port Pin Data Input Register PDIN Reserved 0v A D o N A 20 19 18 17 16 PDIN22 PDIN21 PDIN20 PDIN19 PDIN18 PDIN17 PDIN16 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 15 14 13 12 11 10 9 PDIN15 PDIN14 PDIN13 PDIN12 PDIN11 PDIN10 PDIN9 PDIN8 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 y 6 5 4 3 2 1 0 PDIN7 PDING PDIN5 PDIN4 PDIN3 PDIN2 PDIN1 PDINO R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Legend R Read only n value after reset SPRU629 General Purpose I O Operation 5 11 GPIO Registers Table 5 6 Video Port Pin Data Input Register PDIN Field Descriptions Bit fieldt symvalt Value Description 31 23 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 22 PDIN22 PDIN22 bit returns the logic level of the VCTL3 pin VCTL3LO 0 Pin is logic low VCTL3HI 1 Pin is logic high 21 PDIN21 PDIN21 bit returns the logic level of the VCTL2 pin VCTL2LO 0 Pin is logic low VCTL2HI 1 Pin is logic high 20 PDIN20 PDIN20 bit returns the logic level of the VCTL1 pin VCTL1LO 0 Pin is logic low VCTL1HI 1 Pin is logic high 19 0 PDIN 19 0 PDIN 19 0 bit returns the logic level of the corresponding VDATA n
240. interrupt is only sent to the DSP if the corresponding enable bit in VPIE is set All VPIS bits are cleared by writing a 1 writing a 0 has no effect The VPIS is shown in Figure 2 6 and described in Table 2 9 Figure 2 6 Video Port Interrupt Status Register VPIS 31 24 R 0 20 19 18 17 16 23 22 21 LFDB SFDB VINTB2 VINTB1 SERRB CCMPB COVRB GPIO R WC 0 R WC 0 R WC 0 R WC 0 R WC 0 R WC 0 R WC 0 R WC 0 15 14 13 12 11 10 9 8 DONA Dow Pump TeK R 0 R WC 0 R WC 0 R WC 0 R WC 0 R WC 0 R 0 7 6 5 4 3 2 1 0 LFDA SFDA VINTA2 VINTA1 SERRA CCMPA COVRA R WC 0 R WC 0 R WC 0 R WC 0 R WC 0 R WC 0 R WC 0 R 0 Legend R Read only WC Write 1 to clear write of 0 has no effect n value after reset Table 2 9 Video Port Interrupt Status Register VPIS Field Descriptions Bit field symval Value Description 31 24 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 23 LFDB Long field detected on channel B interrupt detected bit A long field is only detected when the VRST bit in VCBCTL is cleared to 0 when VRST 1 a long field is always detected BT 656 or Y C capture mode LFDB is set when long field detection is enabled and VCOUNT is not reset before VCOUNT YSTOP 1 Raw data mode or TSI capture mode or display mode Not used NONE 0 No interrupt is detected CLEAR 1 Interrupt is detected Bit is cleared t For CSL implementation use the nota
241. ion to provide increased DMA bandwidth as shown in Figure 3 7 Figure 3 7 10 Bit Y C Dense FIFO Packing VDIN 9 0 voINti9 10 63 61 5251 4241 3231 29 2019 109 0 00 Y 23 Y 22 Y 21 00 Y 20 Y 19 Y 18 00 Y 17 Y 16 Y 15 00 Y 14 Y 13 Y 12 00 Y 11 Y 10 Y9 00 Y8 Y7 Y6 YFIFO 00 Y5 Y4 Y3 00 Y2 Y1 YO 63 61 5251 4241 3231 29 2019 109 0 4 00 Cb 11 Cb 10 Cb 9 00 Cb8 Cb 7 Cb6 CbFIFO 00 Cb5 Cb4 Cb 3 00 Cb2 Cb 1 Cb 0 63 61 5251 4241 3231 29 2019 109 0 00 Cr 11 Cr 10 Cr 9 00 Cr8 Cr7 Cr 6 CrFIFO 00 Cr 5 Cr4 Cr 3 00 Cr2 Cr 1 Cro Little Endian Packing 63 61 5251 4241 3231 29 2019 109 0 00 Y18 Y 19 v20 joo Yet Y 22 Y 23 oo Y12 Y 13 Y14 00 Y15 Y 16 Y17 00 Y6 Y7 Y8 00 Y9 Y 10 Y YFIFO 00 YO Y1 Y2 00 Y3 Y4 Y5 63 61 5251 4241 3231 29 2019 109 0 oo cbe Cb7 Cb8 o0 cCbo Cb 10 Cb 11 cbriro 00 Cbo Cb1 Cb2 oo Cb3 Cb4 Cb5 63 61 5251 4241 3231 29 2019 109 0 foo Cr6 Cr7 Cr8 00 Cr9 Cr 10 Crit CrFIFO 00 Cr 0 Cr 1 Cr2 00 Cr3 Cr4 Cr5 Big Endian Packing 3 16 Video Capture Port SPRU629 BT 656 and Y C Mode Field and Frame Operation 3 4 BT 656 and Y C Mode Field and Frame Operation Because DMAs are used to transfer data from the capture FIFOs to memory there is a large amount of flexibility in the way that capture fields and frames are transferred an
242. ions cee eh tok teme bee a AAR c Pon E XR ECL PC cake 4 81 4 25 Video Display Field 2 Vertical Synchronization End Register VDVSYNE2 Field Descriptions essei aaa Corea matan te es esee agent hue Padi h edd xvi SPRU629 4 26 4 27 4 28 4 29 4 30 4 31 4 32 4 33 4 34 4 35 4 36 DIA I OND O do 4 oa onto Cc C N ep Tables Video Display Counter Reload Register VDRELOAD Field Descriptions Video Display Display Event Register VDDISPEVT Field Descriptions Video Display Clipping Register VDCLIP Field Descriptions Video Display Default Display Value Register VDDEFVAL Field Descriptions Video Display Vertical Interrupt Register VDVINT Field Descriptions Video Display Field Bit Register VDFBIT Field Descriptions Video Display Field 1 Vertical Blanking Bit Register VDVBIT1 Field Descriptions Video Display Field 2 Vertical Blanking Bit Register VDVBIT2 Field Descriptions Video Display Register Recommended Values 0 aaa Video Display FIFO Registers 0 06 e cece tenet eee eens Video Display FIFO Registers Function 00000 cece eee e eee eee eens Video Port Registers a uA ERS tee eee Video Port Peripheral Identification Register VPPID Field Descriptions Video Port Peripheral Control Register PCR Field Descriptions
243. is allows the video port to correctly output data formatted as 24 bit RGB or RGBo words in memory 4 6 2 Raw Data FIFO Unpacking Display data is always packed into the FIFOs in 64 bit words and must be unpacked before being sent to the display data pipeline The unpacking and byte ordering is dependant upon the display data size and the device endian mode For little endian operation default data is unpacked from right to left for big endian operation data is unpacked from left to right The 8 bit raw mode uses a single data FIFO Four samples are unpacked from each word as shown in Figure 4 25 Figure 4 25 8 Bit Raw FIFO Unpacking Raw FIFO Raw FIFO 4 26 vetkout LI LE LILI LILI LILI LIL LIU VDOUT 9 2 63 5655 4847 4039 3231 2423 1615 87 0 Raw 15 Raw 14 Raw 13 Raw 12 Raw 11 Raw 10 Raw 9 Raw 8 Raw 7 Raw 6 Raw 5 Raw 4 Raw 3 Raw 2 Raw 1 Raw 0 Little Endian Unpacking 63 5655 4847 4039 3231 2423 1615 87 0 Raw 8 Raw 9 Raw 10 Raw 11 Raw 12 Raw 13 Raw 14 Raw 15 Raw 0 Raw 1 Raw 2 Raw 3 Raw 4 Raw 5 Raw 6 Raw 7 Big Endian Unpacking Video Display Port SPRU629 Raw Data Display Mode For 10 bit operation two samples are unpacked from each FIFO word This is shown in Figure 4 26 Figure 4 26 10 Bit Raw FIFO Unpacking vetkout LE LI LILI LILI LULU LU UU ul VDOUT 9 0 63 5857 4847 4241 3231 2625 1615 10 9 0 Raw 15 Ra
244. is cleared Video Capture Port 3 45 Capturing Video in Raw Data Mode 3 11 Capturing Video in Raw Data Mode In order to capture video in the raw data mode the following steps are needed 1 Set VCxSTOP1 to specify size of an image to be captured VCXSTOP sets the lower 12 bits and VCYSTOP sets the upper 12 bits of the captured image size in pixels Write to VCxTHRLD to set the capture threshold Every time the number of received pixels reaches the number specified by the VCTHRLD1 bits a YEVTx is generated by the video capture module Configure a DMA channel to move data from YSROx to a destination in the DSP memory The channel transfers should be triggered by the YEVTx The size of the transfers should be set to VCTHRLD1 4 for 8 bit mode VCTHRLD1 3 for dense 10 bit mode VCTHRLD1 2 for 10 bit or 16 bit mode or VCTHRLD1 for 20 bit mode The DMA must start on a doubleword boundary and move an even number of words Write to the video port interrupt enable register VPIE to enable overrun COVRx and capture complete CCMP interrupts if desired Write to VCxCTL to Set capture mode CMODE x1x for raw data mode Choose capture operation CON FRAME bits Set 10 bit pack mode 10BPK bits if 10 bit operation is selected Enable raw data sync RDS if desired Set VCEN bit to enable capture O O O O C Capture starts when the ICAPEN signal is asserted and VCEN 1 Data is captured on every VCLKINx rising ed
245. is in YCbCr 4 2 2 with 10 bit resolution Display multiplexed in ITU R BT 656 format 8 Bit Raw Display 8 bit data output 10 Bit Raw Display 10 bit data output 8 Bit Y C Display Digital video is output in YCbCr 4 2 2 with 8 bit resolution on parallel Y and Cb Cr multiplexed channels 10 Bit Y C Display Digital video is output in YCbCr 4 2 2 with 10 bit resolution on parallel Y and Cb Cr multiplexed channels 16 Bit Raw Display 16 bit data output 20 Bit Raw Display 20 bit data output 4 1 1 Image Timing Display devices generate interlaced images by controlling the vertical retrace timing The video display module emits a data stream used to generate a displayed image An NTSC compatible interlaced image with field and line information is shown in Figure 4 1 A progressive scan image SMPTE 296M compatible is shown in Figure 4 2 The active video area represents the pixels visible on the display The active video area begins after the horizontal and vertical blanking intervals The image area output by the video display module can be a subset of the active area The relationship between frame active video area and image area is presented in Figure 4 3 for interlaced video and in Figure 4 4 for progressive video The video display module generates timing for frames active video areas within frames and images within the active video area 4 2 Video Display Port SPRU629 Video Display Mode Selection Figure 4
246. it fieldt symvalt Value BT 656 and Y C Mode Raw Data Mode 21 HXS Horizontal external synchronization enable bit OUTPUT 0 VCTL1 is an output HSINPUT 1 VCTL1 is an external horizontal sync input 20 VCTL3S VCTL3 output select bit CBLNK 0 Output CBLNK FLD 1 Output FLD 19 18 VCTL2S VCTL2 output select bit VYSYNC 0 Output VSYNC VBLNK 1h Output VBLNK CSYNC 2h Output CSYNC FLD 3h Output FLD 17 16 VCTL1S VCTL 1 output select bit HYSYNC 0 Output HSYNC HBLNK 1h Output HBLNK AVID 2h Output AVID FLD 3h Output FLD 15 VDEN Video display enable bit Other bits in VDCTL except RSTCH and BLKDIS bits may only be changed when VDEN 0 DISABLE 0 Video display is disabled ENABLE 1 Video display is enabled 14 DPK 10 bit packing format select bit N10UNPK 0 Normal 10 bit unpacking D10UNPK 1 Dense 10 bit unpacking t For CSL implementation use the notation VP VDCTL field symval tFor complete encoding of these bits see Table 4 4 SPRU629 Video Display Port 4 57 Video Display Registers Table 4 7 Video Display Control Register VDCTL Field Descriptions Continued Description Bit field symvalt Value BT 656 and Y C Mode Raw Data Mode 13 RGBX RGB extract enable bit DISABLE 0 Not used ENABLE 1 Not used Perform 74 FIFO unpacking 12 RSYNC Second synchronized raw data channel enable bit DISABLE 0 Not used Second synchronized raw data channel is disabled ENABLE 1 Not used Second synchronized raw data chann
247. ity detail for video capture mode is listed in Table 1 1 Pin functionality detail for video display mode is listed in Table 1 2 All unused port signals except VCLK1 and VCLK2 can be configured as general purpose I O GPIO pins Table 1 1 Video Capture Signal Mapping Usage BT 656 Capture Mode Raw Data Capture Mode Video Port Dual Single Y C Capture TSI Capture Signal y o Channel Channel Mode 8 10 Bit 16 20 Bit Mode VDATA 9 0 O VDIN 9 0 VDIN 9 0 VDIN 9 0 VDIN 9 0 VDIN 9 0 VDIN 7 0 In Ch A In Ch A In Y In Ch A In In VDATA 19 10 l O VDIN 19 10 Not Used VDIN 19 10 VDIN 19 10 VDIN 19 10 Not Used In Ch B In Cb Cr In Ch B In VCLK1 VCLKINA In VCLKINA In VCLKINA In VCLKINA In VCLKINA In VCLKINA In VCLK2 l O VCLKINB In Not Used Not Used VCLKINB In Not Used Not Used VCTL1 I O CAPENA CAPENA CAPENA CAPENA CAPENA CAPENA In AVID HSYNC AVID HSYNC In In In In In VCTL2 I O CAPENB VBLNK VBLNK CAPENB Not Used PACSTRT In VSYNC In VSYNC In In In VCTL3 O Not Used FID FID FID In FID In PACERR In In ChA ChA In Legend VCLKINA Channel A capture clock CAPENA Channel A capture enable VCLKINB Channel B capture clock CAPENB Channel B capture enable AVID Active video HSYNC Horizontal synchronization VBLNK Vertical blanking VSYNC Vertical synchronization FID Field identification PACSTRT Pac
248. ket start PACERR Packet error SPRU629 Overview 1 13 Video Port Pin Mapping Table 1 2 Video Display Signal Mapping Usage Raw Data Display Mode Video Port BT 656 Y C Display 8 10 Bit Signal lO Display Mode Mode 8 10 Bit 16 20 Bit Dual Sync VDATA 9 0 I O VDOUT 9 0 VDOUT 9 0 VDOUT 9 0 VDOUT 9 0 VDOUT 9 0 Out Out Y Out Out Out Ch A VDATA 19 10 I O Not Used VDOUTT 19 10 Not Used VDOUT 19 10 VDOUT 9 0 Out Cb Cr Out Out Ch B VCLK1 l VCLKIN In VCLKIN In VCLKIN In VCLKIN In VCLKIN In VCLK2 lO VCLKOUT Out VCLKOUT Out VCLKOUT Out VCLKOUT Out VCLKOUT Out VCTL1 O HSYNC HBLNK HSYNC HBLNK HSYNC HBLNK HSYNC HBLNK HSYNC HBLNK AVID FLD Out AVID FLD Out AVID FLD Out AVID FLD Out AVID FLD Out or HSYNC In or HSYNC In or HSYNC In or HSYNC In or HSYNC In VCTL2 O VSYNONBLNK VSYNC VBLNK VSYNONBLNK VSYNC VBLNK VSYNC VBLNK CSYNC FLD Out CSYNC FLD Out CSYNC FLD Out CSYNC FLD Out CSYNC FLD Out or VSYNC In or VSYNC In or VSYNC In or VSYNC In or VSYNC In VCTL3 O CBLNK FLD Out CBLNK FLD Out CBLNK FLD Out CBLNK FLD Out CBLNK FLD Out or FLD In or FLD In or FLD In or FLD In or FLD In 1 14 Overview SPRU629 Video Port Pin Mapping 1 4 14 VDIN Bus Usage for Capture Modes The alignment and usage of data on the VDIN bus depends on the capture mode as shown in Table 1 3 Table 1 3 VDIN Data Bus Usa
249. l Timing Example c e g 3 a gt Active I m o Horizontal FLCOUNT ILCOUNT VF LL gt gt Output 525 240 0 1 Blanking Value Ti _ 240 11 Blanking Value 2L 240 11 Blanking Value 3L 240 kA Blanking Value 4L 240 10 Blanking Value 5 _ 240 10 Blanking Value e Field Blanking 240 10 Blanking Value i i 10 Blanking Value 00 Default Values 00 Default Value 00 Default Values 00 FIFO Data 0 0 FIFO Data 00 FIFO Data 00 FIFO Data 00 Default Value _ 240 10 Blanking Value 265 _ 240 10 Blanking Value 266 __ 240 11 Blanking Value 267 Field 2 Blanking 240 11 Blanking Value 268 _ 240 11 Blanking Value 269 240 14 Blanking Value Mid ae 1 1 1 L 240 1 i 1 Blanking Value 240 Oot Default Value 240 0 1 Default Value 240 0 1 Default Value 1 0 1 FIFO Data 2 01 FIFO Data 1 239 00 FIFO Data 240 0 1 FIFO Data 240 11 Blanking Value 240 11 Blanking Value IMGVOFF1 3 VBLNKXSTART1 720 VSYNCXSTART1 720 FLD1XSTART 720 IMGVSIZE1 240 VBLNKYSTART1 1 VSYNCYSTART1 4 FLD1YSTART 1 IMGVOFF2 3 VBLNKXSTOP1 720 VSYNCXSTOP1 720 FLD2XSTART 360 IMGVSIZE2 240 VBLNKYSTOP1 20 VSYNCYSTOP1 7 FLD2YSTART 263 FRMHEIGHT 525 VBLNKXSTART2 360 VSYNCXSTART2 360 VBITSET1 1 VBLNKYSTART2 263 VSYNCYSTART2 266 FBITSET 266 VBITCLR1 20 VBLNKXSTOP2 360 VSYNCXSTOP2 360 FBITCLR 4 VBITSET2 264 VBLNKYSTOP2 28
250. ld 1 Not used Not used FLDCAP 1 Capture field 1 Not used Not used 3 2 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 1 0 CMODE Capture mode select bit BT656B 0 Enables 8 bit BT 656 mode Not used BT656D 1h Enables 10 bit BT 656 mode Not used RAWB 2h Enables 8 bit raw data mode Not used RAWD 3h Enables 10 bit raw data mode Not used t For CSL implementation use the notation VP VCBCTL field symval t For complete encoding of these bits see Table 3 6 Table 3 11 and Table 3 12 3 13 11 TSI Capture Control Register TSICTL The transport stream interface capture control register TSICTL controls TSI capture operation TSICTL is shown in Figure 3 39 and described in Table 3 24 The ERRFILT STEN and TCKEN bits may be written at any time To ensure stable counter operation writes to the CTMODE bit are disabled unless the system time counter is halted ENSTC 0 Figure 3 39 TSI Capture Control Register TSICTL 31 16 R 0 15 6 5 4 3 2 1 0 Reseed J ENSTG TOKEN STEN oTMODE ensi R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 0 Legend R Read only R W Read Write n value after reset 3 72 Video Capture Port SPRU629 Video Capture Registers Table 3 24 TSI Capture Control Register TSICTL Field Descriptions BT 656 Y C Mode Description Bit fieldt symvalt Value or Raw Data Mode TSI Mode 31 6 Reser
251. ld has no effect 10 PFUNC10 NORMAL VDATA10TO19 PFUNC10 bit determines if VDATA 19 10 pins function as GPIO Pins function normally Pins function as GPIO pin 9 1 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 PFUNCO NORMAL VDATAOTO9 0 1 PFUNCO bit determines if VDATA 9 0 pins function as GPIO Pins function normally Pins function as GPIO pin t For CSL implementation use the notation VP PFUNC field symval SPRU629 General Purpose I O Operation 5 7 GPIO Registers 5 1 4 Video Port Pin Direction Register PDIR The video port pin direction register PDIR is shown in Figure 5 4 and described in Table 5 5 The PDIR controls the direction of IO pins in the video port for those pins set by PFUNC If a bitis setto 1 the relevant pin or pin group acts as an output If a bit is cleared to 0 the pin or pin group functions as an input The PDIR settings do not affect pins where the corresponding PFUNC bit is not set Figure 5 4 Video Port Pin Direction Register PDIR 31 24 R 0 23 22 21 20 19 17 16 R 0 R W 0 R W 0 R W 0 R 0 R W 0 15 13 12 11 10 9 8 R 0 R W 0 R 0 R W 0 R 0 R W 0 7 5 4 3 1 0 R 0 R W 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 5 5 Video Port Pin Direction Register PDIR Field Descriptions Bit fieldt symvalt Value Description 31 23 Reserved 0 Res
252. le 2 8 Figure 2 5 Video Port Interrupt Enable Register VPIE 31 24 R 0 23 22 21 20 19 18 17 16 LFDB SFDB VINTB2 VINTB1 SERRB CCMPB COVRB GPIO R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 DONA Dow Pump Tek R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R 0 7 6 5 4 3 2 1 0 LFDA SFDA VINTA2 VINTA1 SERRA CCMPA COVRA R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Legend R Read only R W Read Write n value after reset Table 2 8 Video Port Interrupt Enable Register VPIE Field Descriptions Bit fieldt symvalt Value Description 31 24 Reserved 0 Reserved The reserved bit location is always read as O A value written to this field has no effect 23 LFDB Long field detected on channel B interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled 22 SFDB Short field detected on channel B interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled 21 VINTB2 Channel B field 2 vertical interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1 Interrupt is enabled t For CSL implementation use the notation VP VPIE field symval SPRU629 Video Port 2 21 Video Port Control Registers Table 2 8 Video Port Interrupt Enable Register VPIE Field Descriptions Continued Bit field symvalt Value Description 20 VINTB1 Channel B field 1 vertical interrupt enable bit DISABLE 0 Interrupt is disabled ENABLE 1
253. leared 10 STC NONE CLEAR System time clock interrupt detected bit BT 656 Y C capture mode or raw data mode Not used TSI capture mode STC is set when the system time clock reaches an absolute time as programmed in TSISTCMPL and TSISTCMPM registers and the STEN bit in TSICTL is set No interrupt is detected Interrupt is detected Bit is cleared 9 8 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect t For CSL implementation use the notation VP VPIS field symval SPRU629 Video Port 2 27 Video Port Control Registers Table 2 9 Video Port Interrupt Status Register VPIS Field Descriptions Continued Bit field symval 7 LFDA NONE CLEAR Value Description Long field detected on channel A interrupt detected bit A long field is only detected when the VRST bit in VCACTL is cleared to 0 when VRST 1 a long field is always detected BT 656 or Y C capture mode LFDA is set when long field detection is enabled and VCOUNT is not reset before VCOUNT YSTOP 1 Raw data mode or TSI capture mode or display mode Not used No interrupt is detected Interrupt is detected Bit is cleared 6 SFDA NONE CLEAR Short field detected on channel A interrupt detected bit BT 656 or Y C capture mode SFDA is set when short field detection is enabled and VCOUNT is reset before VCOUNT YSTOP Raw data mode or TSI captur
254. leared DSP has the entire next data packet time to clear FRMC 0 1 X X Single packet capture FRMC is set after packet capture and causes CCMPA to be set Capture is halted until the FRMC bit is cleared 1 0 X x Continuous packet capture FRMC is set after packet capture and causes CCMPA to be set CCMPx interrupt can be disabled The port will continue capturing packets regardless of the state of FRMC 1 1 X X Reserved 3 40 Video Capture Port SPRU629 TSI Capture Mode 3 8 6 Writing to the FIFO The captured TSI packet data and the associated timestamps are written into the receive FIFO The packet data is written first followed by the timestamp The FIFO controller controls both data writes and timestamp writes into the FIFO The FIFO data packing is shown in Figure 3 25 Figure 3 25 TSI FIFO Packing VDIN 9 2 4 TSI FIFO 4 TSI FIFO 63 5655 4847 4039 32 31 2423 1615 87 TSI 15 TSI 14 TSI 13 TSI 12 TSI 11 TSI 10 TSI 9 TS18 TSI 7 TSI 6 TSI 5 TS14 TSI 3 TSI 2 TSI 1 TSIO Little Endian Packing 63 5655 4847 4039 3231 2423 1615 87 TS18 TSI 9 TSI 10 TSI 11 TSI 12 TSI 13 TSI 14 TSI 15 TSLO TSI 1 TSI2 TSI 3 TSI 4 TSI 5 TSI6 TSI 7 Big Endian Packing The data capture circuitry signals to the synchronizing circuit when
255. n is always read as 0 A value written to this field has no effect 11 0 VCXSTART OF value VCVBLNKP VCXSTART bits define the starting pixel number Must be an even number LSB is treated as 0 t For CSL implementation use the notation VP VCxSTRT1 field symval SPRU629 define the minimum CAPEN inactive time to be interpreted as a vertical blanking period Video Capture Port VCVBLNKP bits Not used 3 59 Video Capture Registers 3 13 4 Video Capture Channel x Field 1 Stop Register VCASTOP1 VCBSTOP1 The video capture channel x field 1 stop register VCASTOP1 VCBSTOP1 defines the end of the field 1 captured image or the end of the raw data or TSI packet VCxSTOP1 is shown in Figure 3 32 and described in Table 3 17 In raw capture mode the horizontal and vertical counters are combined into a single counter that keeps track of the total number of samples received In TSI capture mode the horizontal and vertical counters are combined into a single data counter that keeps track of the total number of bytes received The capture starts when a SYNC byte is detected The data counter counts bytes as they are received The FRMC bit in VCXSTAT gets set each time a packet has been received Figure 3 32 Video Capture Channel x Field 1 Stop Register VCASTOP1 VCBSTOP1 31 28 27 16 R 0 R W 0 15 12 11 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 3 17 Video
256. n the display FIFO a new Y DMA event may be generated 4 77 Video Display Registers 4 12 16 Video Display Horizontal Synchronization Register VDHSYNC The video display horizontal synchronization register VDHSYNC controls the timing of the horizontal synchronization signal The VDHSYNC is shown in Figure 4 54 and described in Table 4 21 Generation of the horizontal synchronization is shown in Figure 4 5 page 4 6 The HSYNC signal is asserted to indicate the start of the horizontal sync pulse whenever the frame pixel counter FPCOUNT is equal to HSYNC START The HSYNC signal is deasserted to indicate the end of the horizontal sync pulse whenever FPCOUNT HSYNCSTOP Figure 4 54 Video Display Horizontal Synchronization Register VDHS YNC 31 28 27 16 R 0 R W 0 15 12 11 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 4 21 Video Display Horizontal Synchronization Register VDHS YNC Field Descriptions Bit fieldt symvalt Value Description 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 HSYNCSTOP OF value O FFFh Specifies the pixel where HSYNC is deasserted 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 HSYNCSTART OF value O FFFh Specifies the pixel where HSYNC is asserted t For CSL implementation use th
257. ndex 3 Index LFDE bit in VCACTL in VCBCTL mode selection TSI capture video capture video display NH bit in VDIMGOFF1 in VDIMGOFF2 noncontinuous frame capture for 525 60 format example noncontinuous frame display for 525 60 format example notational conventions NV bit in VDIMGOFF1 in VDIMGOFF2 overview 1 2 VIC port video capture PCR PCR bits PCR header 3 39 PCRE bits PCRM bit PDCLR PDCLRn bits PDIN PDINn bits PDIR PDIRn bits PDOUT PDOUTR bits Index 4 PDSET PDSETn bits PEREN bit 5 4 peripheral bus reset PFUNC PFUNCn bits PICLR PICLRn bits PIEN PIENn bits PIPOL PIPOLn bits PISTAT PISTATn bits PK10B bits in VCACTL in VCBCTL power on reset 2 2 PRECISION bit program clock reference PCR header PVPSYN bit raw data mode 3 32 4 25 capture notification capturing video displaying video FIFO overrun FIFO packing FIFO unpacking RDFE bit registers GPIO peripheral control register PCR peripheral identification register VPPID pin data clear register PDCLR pin data input register PDIN pin data output register PDOUT pin data set register PDSET pin direction register PDIR pin function register PFUNC pin interrupt clear register PICLR pin interrupt enable register PIEN pin interrupt polarity register PIPOL pin interrupt status register PISTAT SPRU629 Index registers continued TSI system time clock compare mask MSB V
258. ng with chrominance resampling Filter operation is determined by the CMODE SCALE and RESMPL bits of VCxCTL Table 3 10 shows the input filter mode selection When 8 bit BT 656 or Y C capture operation is selected CMODE x00 scaling is selected by setting the SCALE bit and chrominance resampling is selected by setting the RESMPL bit If 8 bit BT 656 or Y C capture is not selected CMODE x00 filtering is disabled Input Filter Mode Selection 0 No filtering 1 1 scaling 0 Chrominance resampling full scale 1 1 scaling with chrominance resampling x No filtering x No filtering x No filtering Video Capture Port SPRU629 Video Input Filtering 3 5 2 Chrominance Resampling Operation Chrominance resampling computes chrominance values at sample points midway between the input luminance samples based on the input co sited chrominance samples This filter performs the horizontal portion of a conver sion between YCbCr 4 2 2 format and YCbCr 4 2 0 format The vertical portion of the conversion must be performed in software The chrominance resampling filters calculate the implied value of Cb and Cr in between luminance sample points based upon nearby co sited Cb and Cr samples The resulting values are clamped to between 01h and FEh and sent to the Cb and Cr capture buffers Chrominance resampling is shown in Figure 3 12 Figure 3 12 Chrominance Resampling YCbCr 4 2 2 co sited input samples chroma resampled capture re
259. nter is not used Figure 3 24 shows the system time clock counter operation Figure 3 24 System Time Clock Counter Operation 27 MHz CTMODE STCLK External VCXO SPRU629 Counter 233 Modulo 300 PCR Base PCR Extension On reception of a packet during the sync byte a snapshot of the counter is captured This snapshot or timestamp is inserted in the receiving FIFO at the end of each data packet Software uses this timestamp to determine the devi ation of the local system time clock from the encoder time clock Any time a packet with a PCR header is received the timestamp for that packet is compared with the PCR value by software A PLL is implemented in software to synchronize the STCLK with the encoder time clock value in the PCR This algorithm then drives the VIC which drives the VDAC output to the external VCXO which supplies STCLK Video Capture Port 3 39 TSI Capture Mode The systemtime clock counter is initialized by software with the PCR ofthe first packet with a PCR header After initialization the counter can be reinitialized by software upon detecting a discontinuity in subsequent packet PCR header values The system time is made available to the DSP at any time through the system time clock registers TSISTCLKL and TSISTCLKM The DSP can program the video portto interrupt the DSP whenever a specific system time is reached or whenever a specific number of system time clock
260. nterpolated control VIC port in the digital signal processors DSPs of the TMS320C6000 DSP family Notational Conventions This document uses the following conventions Hexadecimal numbers are shown with the suffix h For example the following number is 40 hexadecimal decimal 64 40h Related Documentation From Texas Instruments The following documents describe the C6000 devices and related support tools Copies of these documents are available on the Internet at www ti com Tip Enter the literature number in the search box provided at www ti com TMS320C6000 CPU and Instruction Set Reference Guide literature number SPRU189 describes the TMS320C6000 CPU architecture instruction set pipeline and interrupts for these digital signal processors TMS320C6000 Peripherals Reference Guide literature number SPRU190 describes the peripherals available on the TMS320C6000 DSPs TMS320C6000 Technical Brief literature number SPRU197 gives an introduction to the TMS320C62x and TMS320C67x DSPs develop ment tools and third party support TMS320C64x Technical Overview SPRUS95 gives an introduction to the TMS320C64x DSP and discusses the application areas that are enhanced by the TMS320C64x VelociTI TMS320C6000 Programmer s Guide literature number SPRU198 describes ways to optimize C and assembly code for the TMS320C6000 DSPs and includes application program examples TMS320C6000 Code Composer Studi
261. o Port a AIR OD 12 Video Port FIFO 9M DPI ee eee 1 2 1 DMA Interface SI eee eee 1 2 2 Video Capture FIFO Configurations 00sec eee eee ees 1 2 8 Video Display FIFO Configurations 0 cece eee ees 1 8 Video Port Registers 4 So W eens 1 4 Video Port Pin Mapping S cece cece teenies 1 4 1 VDIN Bus Usage for Capture Modes 0000 eee eee eee ees 1 4 8 VDOUT Data Bus Usage for Display Modes 2 Video Port uoo I ee NGALAN iue mex uma xxx cates Heke ee ote Discusses the basic operation of the video port Included is a discussion of the sources and types of resets interrupt operation DMA operation external clock inputs video port throughput and latency and the video port control registers 2 1 2 2 2 3 2 4 2 5 SPRU629 Reset Operation eee hn 2 1 1 Power On Reset 2 2 cent hh 2 1 2 Peripheral Bus Reset 00 0 ees 2 1 3 Software Port Reset c cece eee eens 2 1 4 Capture Channel Reset 000 cee ete eee es 2 1 5 Display Channel Reset 2 000 cece eee eee ees Interrupt Operation s ients ioia aia RR m DMA Operation siis saas kariaia aia AP PA i dea ih aede dei 2 3 1 Capture DMA Event Generation 0c cece teens 2 3 2 Display DMA Event Generation 000 2 cece eee eee eee es 2 83 8 DMA Size and Threshold Restrictions 0 0
262. o Port Pin Data Set Register PDSET Field Descriptions Bit fieldt symvalt Value Description 31 23 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 22 PDSET22 Allows PDOUT22 bit to be set to a logic high without affect ing other I O pins controlled by the same port NONE 0 No effect VCTL3HI 1 Sets PDOUT22 VCTL3 bit to 1 21 PDSET21 Allows PDOUT21 bit to be set to a logic high without affect ing other I O pins controlled by the same port NONE 0 No effect VCTL2HI 1 Sets PDOUT21 VCTL2 bit to 1 20 PDSET20 Allows PDOUT20 bit to be set to a logic high without affect ing other I O pins controlled by the same port NONE 0 No effect VCTL1HI 1 Sets PDOUT20 VCTL1 bit to 1 19 0 PDSET 19 0 Allows PDOUT 1 9 0 bit to be set to a logic high without affecting other I O pins controlled by the same port NONE 0 No effect VDATAnHI 1 Sets PDOUT n VDATA n bit to 1 T For CSL implementation use the notation VP_PDSET_PDSETn_symval 5 16 General Purpose I O Operation SPRU629 GPIO Registers 5 1 8 Video Port Pin Data Clear Register PDCLR The video port pin data clear register PDCLR is shown in Figure 5 8 and described in Table 5 9 PDCLR is an alias ofthe video port pin data output reg ister PDOUT for writes only and provides an alternate means of driving GPIO outputs low Writing a 1 to a bit of PDCLR clears the corresponding bit in PDOUT Writin
263. o Tutorial literature number SPRU301 introduces the Code Composer Studio integrated develop ment environment and software tools SPRU629 Contents iii Related Documentation From Texas Instruments Trademarks Code Composer Studio Application Programming Interface Reference Guide literature number SPRU321 describes the Code Composer Studio application programming interface API which allows you to program custom plug ins for Code Composer TMS320C6x Peripheral Support Library Programmer s Reference literature number SPRU273 describes the contents of the TMS320C6000 peripheral support library of functions and macros It lists functions and macros both by header file and alphabetically provides a complete description of each and gives code examples to show how they are used TMS320C6000 Chip Support Library API Reference Guide literature number SPRU401 describes a set of application programming interfaces APIs used to configure and control the on chip peripherals Trademarks Code Composer Studio C6000 C62x C64x C67x TMS320C6000 TMS320C62x TMS320C64x TMS320C67x and VelociTI are trademarks of Texas Instruments iv SPRU629 Contents 1 Overview aaa aaa aaa nhanh ee 1 1 Provides an overview of the video port peripheral in the digital signal processors DSPs of the TMS320C6000 DSP family Included are an overview of the video port functions FIFO configu rations and signal mapping 11 Vide
264. o in the raw data mode the following steps are needed 1 2 Set the frame size in VDFRMSZ Set the number of lines per frame FRMHIGHT and the number of pixels per line FRMWIDTH Set the horizontal blanking in VDHBLNK Specify the frame pixel counter value where horizontal blanking starts HBLNKSTART and pixel location where horizontal blanking stops HBLNKSTOP Set the vertical blanking start for field 1 in VDVBLKS1 Specify the frame line VBLNKYSTART1 and frame pixel counter VBLNKXSTART1 values for the pixel where vertical blanking starts for field 1 Set the vertical blanking end for field 1 in VDVBLKE1 Specify the frame line VBLNKYSTOP1 and frame pixel counter VBLNKXSTOP1 values for the pixel where vertical blanking ends for field 1 Set the vertical blanking start for field 2 in VDVBLKS2 Specify the frame line VBLNKYSTART2 and frame pixel counter VBLNKXSTART2 values for the pixel where vertical blanking starts for field 2 Set the vertical blanking end for field 2 in VDVBLKE2 Specify the frame line VBLNKYSTOP2 and frame pixel counter VBLNKXSTOP2 values for the pixel where vertical blanking ends for field 2 Set the vertical synchronization start for field 1 in VDVSYNS1 Specify the frame line VSYNCYSTART1 and frame pixel counter VSYNCXSTART1 values for the pixel where vertical synchronization starts for field 1 Set the vertical synchronization end for field 1 in VDVSYNE1 Specify the frame line V
265. o port functions FIFO configurations and signal mapping Topic Page SERIALS UESTRO 1 2 12 Wideo Port KIKO oerte EIE UE 11 5 ji 2msvideolDortiFtegistersm aaa aa 1 12 1 4 Video Port Pin Mapping AA AA 1 13 Video Port 1 1 Video Port 1 2 Overview The video port peripheral can operate as a video capture port video display port or transport stream interface TSI capture port It provides the following functions Video capture mode Capture rate up to 80 MHz Two channels of 8 10 bit digital video input from a digital camera or analog camera using a video decoder Digital video input is in YCbCr 4 2 2 format with 8 bit or 10 bit resolution multiplexed in ITU R BT 656 format One channel of Y C 16 20 bit digital video input in YCbCr 4 2 2 format on separate Y and Cb Cr inputs Supports SMPTE 260M SMPTE 274M SMPTE 296M ITU BT 1120 etc as well as older CCIR601 interfaces YCbCr 4 2 2 to YCbCr 4 2 0 horizontal conversion and scaling in 8 bit 4 2 2 modes Direct interface for two channels of up to 10 bit or one channel of up to 20 bit raw video from A D converters Video display mode Display rate up to 110 MHz One channel of continuous digital video output Digital video output is YCbCr 4 2 2 co sited pixel data with 8 10 bit resolution multiplexed in ITU R BT 656 format One channel of Y C 16 20 bit digital video output in YCbCr 4 2 2 format on separate Y and Cb Cr outputs Supports
266. o the FIFO from right to left for big endian opera tion data is packed from left to right The 8 bit Y C mode uses three FIFOs for color separation Four samples are packed into each word as shown in Figure 3 5 VOINIS 2 voIN t9 12 63 56 55 48 47 40 39 3231 24 23 1615 87 0 Y 31 Y 30 Y 29 Y 28 Y 27 Y 26 Y 25 Y 24 Y 23 Y 22 Y 21 Y 20 Y 19 Y 18 Y 17 Y 16 Y 15 Y 14 Y 13 Y 12 Y 11 Y 10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y 1 YO 63 56 55 48 47 40 39 3231 24 23 1615 87 0 Cb 15 Cb 14 Cb 13 Cb 12 Cb 11 Cb 10 Cb 9 Cb8 Cb 7 Cb 6 Cb 5 Cb4 Cb 3 Cb2 Cb 1 Cb 0 63 56 55 48 47 40 39 3231 24 23 1615 87 0 Cr 15 Cr 14 Cr 13 Cr 12 Cr 11 Cr 10 Cr 9 Cr8 Cr 7 Cr 6 Cr 5 Cr4 Cr3 Cr2 Cr1 Cro Little Endian Packing 63 56 55 48 47 40 39 3231 24 23 1615 87 0 Y 24 Y 25 Y 26 Y 27 Y 28 Y 29 Y 30 Y 31 Y 16 Y 417 Y 18 Y 19 Y 20 Y 21 Y 22 Y 23 Y8 Y9 Y 10 Y 11 Y 12 Y 13 Y 14 Y 15 YO Y 1 Y2 Y3 Y4 Y5 Y6 Y7 63 56 55 48 47 40 39 3231 24 23 1615 87 0 Cb8 Cb 9 Cb 10 Cb 11 Cb 12 Cb 13 Cb 14 Cb 15 Cb 0 Cb 1 Cb2 Cb 3 Cb4 Cb 5 Cb 6 Cb 7 63 56 55 48 47 40 39 3231 24 23 1615 87 0 Cr8 Cr9 Cr 10 Cr 11 Cr 12 Cr 13 Cr 14 Cr 15 Cro Cr 1 Cr2 Cr3 Cr4 Cr5 Cr6 Cr7 Big Endian Packing Video Capture Port SPRU629 Y C Video Capture Mode The 10 bit Y C mode uses three FIFOs for color separation
267. of the other capture control bits FRAME CF1 and CF2 Once the capture complete bit is set at most one more field or frame can be received before capture operation is halted This prevents subsequent data from overwriting previous fields until the DSP has a chance to update DMA pointers or process those fields When a capture halt occurs the video port stops capturing data for the halted field It then checks the appropriate capture complete bit at the start of each subsequent field and resumes capture if the bit has been cleared The CON FRAME CF1 and CF2 bits encode the capture operations as listed in Table 3 6 Video Capture Port 3 17 BT 656 and Y C Mode Field and Frame Operation Table 3 6 BT 656 and Y C Mode Capture Operation CON 0 0 VCxCTL Bit FRAME 0 0 CF2 0 0 CF1 0 1 Operation Reserved Noncontinuous field 1 capture Capture only field 1 F1C is set after field 1 capture and causes CCMPx to be set The F1C bit must be cleared by the DSP before capture can continue The DSP has the entire field 2 time to clear F1C before next field 1 begins Can also be used for single progressive frame capture The DSP has vertical blanking time to clear F1C before next frame begins Noncontinuous field 2 capture Capture only field 2 F2C is set after field 2 capture and causes CCMPx to be set The F2C bit must be cleared by the DSP before capture can continue The DSP has the entire field 1 tim
268. on Bit fieldt symvalt Value BT 656 or Y C Mode Raw Data Mode TSI Mode 10 RESMPL Chroma resampling enable bit DISABLE 0 Chroma resampling is Not used Not used disabled ENABLE 1 Chroma is horizontally Not used Not used resampled from 4 2 2 co sited to 4 2 0 interspersed before saving to chroma buffers 9 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 8 SCALE Scaling select bit NONE 0 No scaling Not used Not used HALF 1 scaling Not used Not used 7 CON Continuous capture enable bit DISABLE 0 Continuous capture is disabled ENABLE 1 Continuous capture is enabled 6 FRAME Capture frame data bit NONE 0 Do not capture frame Do not capture Do not capture single data block single packet FRMCAP 1 Capture frame Capture single Capture single data block packet 5 CF2t Capture field 2 bit NONE 0 Do not capture field 2 Not used Not used FLDCAP 1 Capture field 2 Not used Not used t For CSL implementation use the notation VP_VCBCTL_field_symval tFor complete encoding of these bits see Table 3 6 Table 3 11 and Table 3 12 SPRU629 Video Capture Port 3 71 Video Capture Registers Table 3 23 Video Capture Channel B Control Register VCBCTL Field Descriptions Continued Description Bit field symvalt Value BT 656 or Y C Mode Raw Data Mode TSI Mode 4 CF1t Capture field 1 bit NONE 0 Do not capture fie
269. on Programming 0 00 c cece ete II Input Filter Mode Selection 0000s cece eee nena Raw Data Mode Capture Operation 2 c cece teens TSI Capture Mode Operation a se Video Capture Control Registers cece eee ete eee eee Video Capture Channel x Status Register VCxSTAT Field Descriptions Video Capture Channel A Control Register VCACTL Field Descriptions Video Capture Channel x Field 1 Start Register VCxSTRT1 Field Descriptions Video Capture Channel x Field 1 Stop Register VCxSTOP1 Field Descriptions Video Capture Channel x Field 2 Start Register VCxSTRT2 Field Descriptions Video Capture Channel x Field 2 Stop Register VCxSTOP2 Field Descriptions Video Capture Channel x Vertical Interrupt Register VCxVINT Field Descriptions Video Capture Channel x Threshold Register VCxTHRLD Field Descriptions Video Capture Channel x Event Count Register VCxEVTCT Field Descriptions Video Capture Channel B Control Register VCBCTL Field Descriptions SPRU629 Tables XV Tables 3 24 TSI Capture Control Register TSICTL Field Descriptions 3 25 TSI Clock Initialization LSB Register TSICLKINITL Field Descriptions 3 26 TSI Clock Initialization MSB Register TSICLKINITM Field Descriptions 3 27 TSI System Time Clock LSB Register TSISTCLKL Field Descrip
270. or on the incoming packet as indicated by an active PACERR signal If PACERR is active during any of the first eight bytes of a packet and error packet filtering is enabled ERRFILT bit in TSICTL is set then the video port will ignore not capture the incoming data until the next PACSTRT is received If error packet filtering is not enabled or if PACERR becomes active sometime after the first eight bytes of the packet the entire packet is captured and the PERR bit is set in the timestamp inserted at the end of the packet The second error detected is an early PACSTRT error This occurs when an active PACSTRT is detected before an entire packet as determined by the packet size programmed in VCASTOP has been captured The port will con tinue to capture the expected packet size but will set the PSTERR bit in the timestamp inserted at the end of the packet After capture completion the port will wait for a subsequent PACSTRT before beginning capture of another packet 3 8 A Synchronizing the System Clock Synchronization is an important aspect of decoding and presenting data in real time digital data delivery systems This is addressed in MPEG 2 transport packets by transmitting timing information in the adaptation fields of selected data packets This value serves as a reference for timing comparison in the receiving system The program clock reference PCR header shown in Figure 3 23 is a 48 bit field six bits are reserved A 42 bit value i
271. orrection function on the received video timing reference code The corrected values for the F H and V bits based on the protection bit values are shown in Table 3 4 The entries indicate detected double bit errors that cannot be corrected Detection of these errors causes the SERRx bit in the video port interrupt status register VPIS to be set Table 3 4 Error Correction by Protection Bits Received F V and H Bits Received P3 P9 Bits 000 001 010 011 100 101 110 111 0000 000 000 000 000 111 0001 000 111 111 111 111 0010 000 011 101 0011 i 010 100 5 111 0100 000 011 110 0101 001 100 e 111 0110 011 011 011 100 011 SPRU629 Video Capture Port 3 5 BT 656 Video Capture Mode Table 3 4 Error Correction by Protection Bits Continued Received F V and H Bits Received EEE EE pm P3 Po Bits 000 001 010 011 100 101 110 111 0111 100 011 100 100 100 1000 000 101 110 1001 001 010 111 1010 101 010 101 101 101 1011 010 010 010 101 010 1100 E 001 110 110 110 110 1101 001 001 001 001 110 1110 011 E 101 110 1111 001 010 100 z d 3 2 3 BT 656 Image Window and Capture The BT 656 format is an interlaced format consisting of two fields The video port allows capture of one or both fields The captured image is a subset of each field and can be larger or smaller than the active
272. otify the DMA controller to copy data from the capture buff ers to the DSP memory The number of pixels required to generate the events is set by the VCTHRLDn bits in VOXTHRLD the VCTHRLDn value must be an even number for Y C mode The capture module generates the events after VCTHRLDn new pixels have been received On every YEVT the DMA should move data from the Y buffer to DSP memory using the YSRC register as the source address On every CbEVT the DMA should move data from the Cb buffer to DSP memory using the CBSRC register as the source address On every CrEVT the DMA should move data from the Cr buffer to DSP memory using the CRSRC register as the source address Note that transfer size from the Cb and Cr buffers is half of the transfer size from the Y buffer since for every four Y samples there are two Cb and two Cr samples The three DMA events are generated simultaneously when VCTHRLDn is reached Each event is reenabled when the first read of the respective FIFO by the requested DMA begins SPRU629 Video Capture Port 3 13 Y C Video Capture Mode 3 3 4 Y C FIFO Packing Figure 3 5 8 Bit Y C FIFO Packing Y FIFO Cb FIFO A Cr FIFO Y FIFO Cb FIFO A Cr FIFO 3 14 Captured data is always packed into 64 bits before being written into the capture FIFO s The packing and byte ordering is dependant upon the capture data size and the device endian mode For little endian operation default data is packed int
273. ove data from CRSRCx to a destination in the DSP memory The channel transfers should be triggered by the CrEVTx The size of the transfers should be set to VCTHRLD1 8 for 8 bit mode VCTHRLD1 4 for 10 bit mode or VCTHRLD1 6 for dense 10 bit mode This is because 4 2 or 3 pixels are packed per FIFO word the DMA is moving 32 bit words from CRSRCx to the memory and there are half the number of pixels in the Cr FIFO as in the Y FIFO The DMA must start on a double word boundary and move an even number of words 7 Write to the video port interrupt enable register VPIE to enable overrun COVRx and capture complete CCMP x interrupts if desired 3 44 Video Capture Port SPRU629 Capturing Video in BT 656 or Y C Mode 8 Write to VCxCTL to Set capture mode CMODE 00x for BT 656 input 10x for Y C input Set desired field frame operation CON FRAME CF2 CF1 bits Set sync and field ID control VRST HRST FDD FINV VCTL1 bits Set 10 bit pack mode 10BPK bits if 10 bit operation is selected Enable scaling SCALE and RESMP L bits if desired and using 8 bit data Set VCEN bit to enable capture 0 i 9 Capture is enabled atthe start of the first frame after VCEN 1 and begins at the start of the first selected field DMA events are generated as triggered by VCxTHRLD1 When a selected field has been captured VCXPOS VCXSTOP and VCYPOS VCYSTOP the F1C F2C or FRMC bits in VCxSTAT are set and cause the CCMPx bitin
274. pin mapping reset operation throughput and latency video port control register VPCTL Index 9 Index video port FIFO 1 5 video port interrupt enable register VPIE 2 21 video port interrupt status register VPIS 2 24 video port peripheral control register PCR video port peripheral identification register VPPID es video port pin data clear register NIE 5 17 video port pin data input register PDIN video port pin data output register ou 5 13 video port pin data set register Mad video port pin direction register PDIR video port pin function register eps video port pin interrupt clear register PICLR video port pin interrupt enable register PIEN 19 video port pin interrupt polarity register PIPOL video port pin interrupt status register PISTAT video port pin mapping video port status register VPSTAT VIE bit VIF1 bit in VCxVINT in VDVINT VIF2 bit in VOxVINT 3 63 in VDVINT 4 88 VINT1 bits in VCxVINT 3 63 in VDVINT 4 88 VINT2 bits in VCxVINT 3 63 in VDVINT 4 88 VINTAT1 bit in VPIE in VPIS VINTA2 bit in VPIE z in VPIS VINTB1 bit in VPIE in VPIS VINTB2 bit in VPIE z 1 in VPIS 2 24 Qo m ta ke No No Ing pin sg pre ine 1 NI ag EE Index 10 VPCTL VPHLT bit 2 17 VPIE VPIS VPPID 53 VPRST bit VPSTAT VRLD bits 4 83 VRST bit in VCACTL in VCBCTL VSYNCXSTART1 bits 4 79 VSYNCXSTART bits VSYNCXSTOP1 bits VSYN
275. pis PF o o 263 283 2 1 244 10 264 1 1 2 245 10 265 vu 2 246 11 26 Na g ad KA Ng Chat EN 11 282 19 263 1 2 0 1 283 20 1 2 1 0 1 284 E 21 2 A mA a Field 2 Active a 01 5244 261 242 0 1 525 262 1 2 243 1 1 1 1 2 1 244 2 1 SPRU629 Video Capture Port 3 21 BT 656 and Y C Mode Field and Frame Operation 3 4 3 Horizontal Synchronization Horizontal synchronization determines when the horizontal pixel sample counter is reset The EXC and HRST bits in VCxCTL allow you to program the event that triggers the start of a line The encoding of these bits is shown in Table 3 8 Table 3 8 Horizontal VCxCTL Bit Synchronization Programming HMode EXC HRST Horizontal Counter Reset Point 0 0 0 1 0 1 2 1 0 3 1 1 EAV code H 1 beginning of horizontal blanking SAV code H 0 Start of active video VCTL1 input active edge beginning of horizontal blanking or horizontal sync period VCTL1 must be configured as a horizontal control signal VCTL1 input inactive edge first active pixel on line or end of horizontal sync VCTL1 must be configured as a horizontal control signal 3 22 Video Capture HMode O is used for BT 656 or Y C capture with embedded control and corre sponds to the idea that each line begins with the horizontal blanking period It does not align with most standards that start counting with the first active pixel therefore is only useful if capturing of HA
276. port The VDSTAT is shown in Figure 4 39 and described in Table 4 6 The VDXPOS and VDYPOS bits track the coordinates of the most recently displayed pixel The F1D F2D and FRMD bits indicate the completion of fields or frames and may need to be cleared by the DSP to prevent a DCNA interrupt from being generated depending on the selected frame operation The F1D F2D and FRMD bits are set when the final pixel from the appropriate field has been sent to the output pad Figure 4 39 Video Display Status Register VDSTAT 31 30 29 28 27 16 R 0 R WC 0 R WC 0 R WC 0 R 0 15 14 13 12 11 0 R 0 R 0 R 0 R 0 Legend R Read only WC Write 1 to clear write of 0 has no effect n value after reset SPRU629 Video Display Port 4 53 Video Display Registers Table 4 6 Video Display Status Register VDSTAT Field Descriptions Bit 31 fieldt Reserved symvalt Value 0 Description Reserved The reserved bit location is always read as 0 A value written to this field has no effect 30 FRMD NONE DISPLAYED Frame displayed bit Write 1 to clear the bit a write of O has no effect Complete frame has not been displayed Complete frame has been displayed 29 F2D NONE DISPLAYED Field 2 displayed bit Write 1 to clear the bit a write of 0 has no effect Field 2 has not been displayed Field 2 has been displayed 28 F1D NONE DISPLAYED Field 1 displayed bit Write 1 to cle
277. previsions are made for the display of horizontal ancillary HANC or vertical ancillary VANC also called vertical blanking interval VBI data 4 5 1 Horizontal Ancillary HANC Data Display HANC data can be displayed using the normal video display mechanism by programming IMGHSIZEn to occur prior to the SAV code The HANC data including the ancillary data header must be part of the YCbCr separated data in the FIFOs The VCTHRLD value and DMA size must be programmed to comprehend the additional samples You must disable scaling and chroma re sampling when including the display of HANC data to prevent data corruption 4 5 2 Vertical Ancillary VANC Data Display VANC or VBI data is commonly used for such features as teletext and closed captioning No special provisions are made for the display of VBI data VBI data may be displayed using the normal display mechanism by programming IMGVOFF to occur before the first line of active video on the first line of desired VBI data Note that the VBI data must be YCbCr separated You must disable scaling and chroma resampling when the display of VBI data is desired or the data will be corrupted by the filters 4 6 Raw Data Display Mode SPRU629 The raw data display modes are intended to output data to a RAMDAC or other D A type device This is typically RGB formatted data No timing information is inserted into the output data stream instead selectable control signals are output to indicate
278. ptureHandle VCASTOP1 VP VCASTOP1 RMK VCA YSTOP1 Video Port Configuration Examples VCA XSTOP1 Ky Bf xy tf xy kj we EJ Ky EJ SPRU629 Example 1 Noncontinuous Frame Capture for 525 60 Format Se VP RS last pixel to be captured in Field2 VCA STOP2 reg y TH vpCaptureHandle VCASTOP2 VP_VCASTOP2_RMK VCA_YSTOP2 VCA_XSTOP2 Gl T Se VP RS first pixel to be captured in Field1 VCA STRT1 reg kj TH vpCaptureHandle VCASTRT1 VP VCASTRT1 RMK VCA YSTART1 VP VCASTRT1 SSE ENABLE VCA XSTART1 ET a 488 VP RS first pixel to be captured in Field2 VCA STRT2 reg kf TH vpCaptureHandle VCASTRT2 VP VCASTRT2 RMK VCA YSTART2 VCA XSTART2 I CT Se VP RS threshold values 7 TH vpCaptureHandle VCATHRID VP VCATHRLD RMK VCA THRLD FIELD2 VCA THRLD FIELD1 GI cT Set captur vent register values n VP RSETH vpCaptureHandle VCAEVTCT VP VCAEVTCT RMK VCA CAPEVT2 VCA CAPEVT1 Vertical interrupts VCA INT are not enabled in this a in this example eA Set CMODE to 8 bit BT 656 E VP FSETH vpCaptureHandle VCACTL CMODE VP VCACTL CMODE BT656B Set non continuous frame capture KH VP FSETH vpCaptureHandle VCACTL CON VP VCACTL CON DISABLE VP F
279. r VCASTAT VCBSTAT The video capture channel x status register VCASTAT VCBSTAT indicates the current status of the video capture channel The VCXSTAT is shown in Figure 3 29 and described in Table 3 14 In BT 656 capture mode the VCXPOS and VCYPOS bits indicate the HCOUNT and VCOUNT values respectively to track the coordinates of the most recently received pixel The F1C F2C and FRMC bits indicate comple tion of fields or frames and may need to be cleared by the DSP for capture to continue depending on the selected frame capture operation see section 3 4 1 In raw data and TSI modes the VCXPOS and VCYPOS bits reflect the lower and upper 12 bits respectively of the 24 bit data counter that tracks the number of received data samples The FRMC bit indicates when an entire data packet has been received and may need to be cleared by the DSP for capture to continue depending on the selected frame operation see section 3 7 1 and section 3 8 5 Figure 3 29 Video Capture Channel x Status Register VCASTAT VCBSTAT 31 30 29 28 27 16 R 0 R WC 0 R WC 0 R WC 0 R 0 15 13 12 11 0 R 0 R 0 R 0 Legend R Read only WC Write 1 to clear write of 0 has no effect n value after reset 3 50 Video Capture Port SPRU629 Video Capture Registers Table 3 14 Video Capture Channel x Status Register VCxSTAT Field Descriptions Description Bit fieldt symvalt Value BT 656 or Y C Mode Raw Data Mode
280. r VCYSTART2 and stop VCYSTOP1 or VCYSTOP2 values for the current field to determine if the current line is within the capture window In order to correctly align the capture window within the field the capture module must know which line should correspond to the first line of the field that is when to reset the line counter This point may vary depending on the type of capture being performed and the signals available for vertical synchronization The video port allows the vertical counter reset trigger to be determined by programming the EXC and VRST bits in VCxCTL The encoding of these bits is shown in Table 3 7 Note that VModes 2 and 3 are only available for single channel operation channel A Video Capture Port 3 19 BT 656 and Y C Mode Field and Frame Operation Table 3 7 Vertical Synchronization Programming VMode 0 VCxCTL Bit EXC 0 VRST Vertical Counter Reset Point 0 First EAV with V 1 after EAV with V 0 beginning of vertical blanking period VCOUNT increments on each EAV First EAV with V 0 after EAV with V 1 first active line VCOUNT increments on each EAV On HCOUNT reset after VCTL2 input active edge beginning of vertical blanking or vertical sync period VCTL2 must be configured as vertical control signal VCOUNT increments when HCOUNT is reset On HCOUNT reset after VCTL2 input inactive edge end of vertical sync or first active scan line VCTL2 must be configured as vertical cont
281. rame capture FRMC is set after data block capture and causes CCMPXx to be set Capture is halted until the FRMC bit is cleared 1 0 X X Continuous frame capture FRMC is set after data block capture and causes CCMPx to be set CCMPx interrupt can be disabled The port will continue capturing frames regardless of the state of FRMC 1 1 x x Reserved The CON bit controls the capture of multiple frames When CON 1 continuous capture is enabled the video port captures incoming frames assuming the VCEN bit is set without the need for DSP interaction It relies on a DMA structure with circular buffering capability to service the capture FIFO When CON 0 continuous capture is disabled the video port sets the frame capture complete bit FRMC in VOxSTAT upon the capture of each frame Once the capture complete bit is set at most one more frame can be received before capture operation is halted as determined by the FRAME bit state This prevents subsequent data from overwriting previous frames until the DSP has a chance to update DMA pointers or process those frames 3 7 2 Raw Data FIFO Packing Captured data is always packed into 64 bits before being written into the capture FIFO s The packing and byte ordering is dependant upon the capture data size and the device endian mode For little endian operation default data is packed into the FIFO from right to left for big endian opera tion data is packed from left to right SPRU6
282. ransfer is complete BT 656 or Y C capture mode CCMPA is set after capturing an entire field or frame when F1C F2C or FRMC in VCASTAT are set depending on the CON FRAME CF1 and CF2 control bits in VCACTL Raw data mode If RDFE bit is set CCMPA is set when F1C F2C or FRMC in VCASTAT is set when the data counter the combined VCYSTOP VCXSTOP value depending on the CON FRAME CF1 and CF2 control bits in VCACTL If RDFE bit is not set CCMPA is set when FRMC in VCASTAT is set when the data counter the combined VCYSTOP VCXSTOP value TSI capture mode CCMPA is set when FRMC in VCASTAT is set when the data counter the combined VCYSTOP VCXSTOP value No interrupt is detected Interrupt is detected Bit is cleared 1 COVRA NONE CLEAR Capture overrun on channel A interrupt detected bit COVRA is set when data in the FIFO was overwritten before being read out by the DMA No interrupt is detected Interrupt is detected Bit is cleared 0 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect t For CSL implementation use the notation VP VPIS field symval SPRU629 Video Port 2 29 Chapter 3 Video Capture Port Video capture works by sampling video data on the input pins and saving it to the video port FIFO When the amount of captured data reaches a programmed threshold level a DMA is performed to move data from the FIF
283. rated The port clocks and counters continue to run in order to maintain synchronization No interrupts are generated If the port is in display mode video control signals continue to be output and the default data value is output during the active video window Is not defined for this peripheral the bit is hardwired to O 0 FREE SOFT Free running enable mode bit This bit is used in conjunction with SOFT bit to determine state of video port during emulation suspend Free running mode is disabled During emulation suspend SOFT bit determines operation of video port Free running mode is enabled Video port ignores the emulation suspend signal and continues to function as normal t For CSL implementation use the notation VP_PCR_field_symval SPRU629 General Purpose I O Operation 5 5 GPIO Registers 5 1 3 Video Port Pin Function Register PFUNC The video port pin function register PFUNC selects the video port pins as GPIO The PFUNC is shown in Figure 5 3 and described in Table 5 4 Each bit controls either one pin or a set of pins When a bit is set to 1 it enables the pin s that map to it as GPIO The GPIO feature should not be used for pins that are used as part of the capture or display operation For pins that have been muxed out for use by another peripheral the PFUNC bits will have no effect The VDATA pins are broken into two functional groups VDATA 9 0 and VDATA 19 10 Thus each entire half of th
284. re FIFOs may hold multiple thresholds worth of data a problem arises at the boundaries between fields Since Field 1 and Field 2 may have different threshold values the amount of data in the FIFO required to generate the DMA event changes depending on the current capture field and the field of any outstanding DMA requests Similarly the threshold value loaded in the outgoing data counter needs to change depending on which fields DMA event is being serviced not which field is currently being captured To prevent confusion at the field boundaries the VCxEVTCT regis ter is programmed to indicate the number of events to generate for each field An event counter tracks how many events have been generated and indicates which threshold value to use in event generation and in the outgoing data counter After the last Field 1 event has been generated the DMA logic looks for FIFO gt THRSHLD1 THRSHLD2 to pregenerate the first Field 2 event Once the last Field 1 event completes the logic looks for FIFO gt 2 x THRSHLD2 assuming a Field 2 event is outstanding Some initial devices may require THRSHLD1 and THRSHLD2 to be set to the same value Check the latest device errata if you want to use different thresh olds for the two fields 2 3 2 Display DMA Event Generation 2 8 Video Port Display DMA events are generated based on the amount of room available in the FIFO The VDTHRLDn value indicates the level at which the FIFO has room to recei
285. re Mode The 20 bit raw data mode stores all data into a single FIFO One sample is placed right justified in each word and zero or sign extended as shown in Figure 3 21 Figure 3 21 20 Bit Raw Data FIFO Packing VDIN 19 0 63 5251 3231 2019 0 0 SE Raw 7 0 SE Raw 6 0 SE Raw 5 0 SE Raw 4 0 SE Raw 3 0 SE Raw 2 Y FIFO 0 SE Raw 1 0 SE Raw 0 Little Endian Packing 63 5251 3231 2019 0 0 SE Raw 6 0 SE Raw 7 0 SE Raw4 0 SE Raw 5 0 SE Raw 2 0 SE Raw 3 Y FIFO 0 SE Raw 0 0 SE Raw 1 Big Endian Packing 3 36 Video Capture Port SPRU629 TSI Capture Mode 3 8 TSI Capture Mode The transport stream interface TSI capture mode captures MPEG 2 trans port data 3 8 4 TSI Capture Features The video port TSI capture mode supports the following features Supports SYNC detect using the PACSTRT input from a front end device Data capture at the rising edge of incoming VCLK1 Parallel data reception Maximum data rate of 30 Mbytes second Programmable packet size Hardware counter mechanism to timestamp incoming packet data Programmable filtering of packets with errors Interrupt to the DSP based on absolute system time or system time clock cycles O O O O O O O L The video port does not perform following functions these functions should be performed in software _j PID filtering _j Data parsing Lj De scrambling of data 3 8 2 TSI Data Capture S
286. re generated directly from the pixel and line counters and comparison registers Several additional signals are also generated indirectly for use in external control A composite blank CBLNK signal is generated as the logical OR of the HBLNK and VBLNK signals A composite sync CSYNC signal is also gener ated as the logical OR of the HSYNC and VSYNC signals This is not a true analog CSYNC which must include serration pulses during VSYNC and equalization pulses during vertical front and back porch periods Finally an active video AVID signal is generated AVID is the inverted CBLNK signal indicating when active video data is being output Up to three of the eight sync signals may be output on VCTL1 VCTL2 and VCTL3 as selected by the video display control register VDCTL Each signal may be output in its noninverted or inverted form as selected by the VCTnP bits in the video port control register VPCTL Video Display Port 4 7 Video Display Mode Selection 4 1 4 External Sync Operation The video display module may be synchronized with an external video source using external sync signals VCTL1 may be configured as an external horizon tal sync input When the external HSYNC is asserted FPCOUNT is loaded with the HRLD value and VCCOUNT is loaded with the CRLD value VCTL2 may be configured as an external vertical sync input When the external VSYNC is asserted during field 1 FLCOUNT is loaded with the VRLD value Field determin
287. re shown as they would be output for active low operation Note that only one of the two signals is actually available exter nally The HBLNK inactive edge occurs either on sample 856 coincident with the start of SAV or on sample 0 after SAV if the HBDLA bit is set For true BT 656 operation neither HBLNK nor HSYNC would be used The IPCOUNT operation follows the description in section 4 1 2 IPCOUNT resets to O at the first displayed pixel FRCOUNT IMGHOFF and stops counting at the last displayed pixel IPCOUNT IMGHSIZE The operation during nondisplay time is not a requirement it could continue counting until the next FPCOUNT IMGHOFFx point or it could reset immediately after IMGHSIZEx or when FPCOUNT is reset VDOUT shows the output data and switching between EAV Blanking Data SAV Default Data and FIFO Data It is assumed that the DVEN bit in VDCTL is set to enable the default output Video Display Port 4 35 9 v Log Aejdsiq capi 629N4dS Figure 4 33 BT 656 Interlaced Display Horizontal Timing Example VCLKIN UU UUI Ul NN ka 268 1 a4 1440 One Line Next Line k FPCOUNT 72721 722 724 734 736 7es 8o0 less bse ast o 1 7 la o 10 zi 711 712 719 719 72d 721 IPCOUNT 03 703 703 zod 708 703 703 704 704704 704703 703 nj 1 2 702 709 703 703 zi 704 7
288. requency MHz Function VCLK1 External pin 13 5 110 Clocks capture channel A and display logic and pin side of the FIFOs VCLK2 External pin 13 5 80 Clocks capture channel B logic and FIFO pin side STCLK External pin 27 Clocks TSI system time counter and tick counter 2 5 Video Port Functionality Subsets 2 5 2 12 Video Port The video port may be implemented with reduced features in low cost devices 1 Data Bus Width The standard port has a 20 bit VDATA bus Lower cost implementations may use a more narrow data bus at the expense of functionality The following lists the choices and their effect on the design L 20 bit Full functionality UH 10 bit Single channel channel A only DCDIS bit in VPSTAT always set Limits CMODE selection to 8 10 bit BT 656 and 8 10 bit raw capture modes Limits DMODE selection to 8 10 bit BT 656 and 8 10 bit raw display TSI capture mode may also be selected 8 bit Single channel channel A only DCDIS bit in VPSTAT always set Limits CMODE selection to 8 bit BT 656 and 8 bit raw capture modes Limits DMODE selection to 8 bit BT 656 and 8 bit raw display TSI capture mode may also be selected Selection of 8 bit or 10 bit mode limits port operation to a single channel This selection also causes the removal of the channel B register file channel B filters and other logic and 72 of the FIFO SPRU629 2 5 2 FIFO Size Video Port Functionality Subsets Video Port Throug
289. resets the tick counter 0 Whenever the tick counter reaches the TICKCT value the TICK bit in VPIS is set and the counter resets to 0 To prevent inaccurate comparisons caused by changing register bits the soft ware should disable the tick count interrupt clear the TCKEN bit in TSICTL prior to writing to TSITICKS Figure 3 48 TSI System Time Clock Ticks Interrupt Register TSITICKS 31 0 R W 0 Legend R W Read Write n value after reset Table 3 33 TSI System Time Clock Ticks Interrupt Register TSITICKS Field Descriptions Bit Field symvalt Value or Raw Data Mode 31 0 TICKCT OF value O FFFFFFFFh_ Not used Description BT 656 Y C Mode TSI Mode Contains the number of ticks of the 27 MHz system time clock required to generate a tick count interrupt T For CSL implementation use the notation VP TSITICKS TICKCT symval 3 82 Video Capture Port SPRU629 Video Capture FIFO Registers 3 14 Video Capture FIFO Registers The capture FIFO mapping registers are listed in Table 3 34 These registers provide read access to the capture FIFOs These pseudo registers should be mapped into DSP memory space rather than configuration register space in order to provide high speed access See the device specific datasheet for the memory address of these registers The function of the video capture FIFO mapping registers is listed in Table 3 35 Table 3 34 Video Capture FIFO Registers Acronym Register Name YSRCA Y
290. riptions 99 eese 4 11 Video Display Field 1 Vertical Blanking End Register VDVBLKE1 Field Descriptions b Y AA mI Rh nne 4 12 Video Display Field 2 Vertical Blanking Start Register VDVBLKS2 Field Descriptions 0 0c cee RII 4 13 Video Display Field 2 Vertical Blanking End Register VDVBLKE2 Field Desetiptiongs 4J AA nne 4 14 Video Display Field 1 Image Offset Register VDIMGOFF1 Field Descriptions 4 15 Video Display Field 1 Image Size Register VDIMGSZ1 Field Descriptions 4 16 Video Display Field 2 Image Offset Register VDIMGOFF2 Field Descriptions 4 17 Video Display Field 2 Image Size Register VDIMGSZ2 Field Descriptions 4 18 Video Display Field 1 Timing Register VDFLDT1 Field Descriptions 4 19 Video Display Field 2 Timing Register VDFLDT2 Field Descriptions 4 20 Video Display Threshold Register VDTHRLD Field Descriptions 4 21 Video Display Horizontal Synchronization Register VDHSYNC Field Descriptions 4 22 Video Display Field 1 Vertical Synchronization Start Register VDVSYNS1 Field Descriptions cese seis KA eem Ree ced bended eed nd d eed 4 23 Video Display Field 1 Vertical Synchronization End Register VDVSYNE1 Field Descriptions serae ranor EEEE TETEE PARIA mme 4 24 Video Display Field 2 Vertical Synchronization Start Register VDVSYNS2 Field Descript
291. ritten to this field has no effect 9 1 INPCRE OF value 0 1FFh Not used Initializes the extension portion of the system time clock 0 INPCRM OF value 0 1 Not used Initializes the MSB of the system time clock T For CSL implementation use the notation VP_TSICLKINITM_field_symval SPRU629 Video Capture Port 3 75 Video Capture Registers 3 13 14 TSI System Time Clock LSB Register TSISTCLKL The transport stream interface system time clock LSB register TSISTCLKL contains the 32 least significant bits LSBs of the program clock reference PCR The system time clock value is obtained by reading TSISTCLKL and TSISTCLKM TSISTCLKL is shown in Figure 3 42 and described in Table 3 27 TSISTCLKL represents the current value of the 32 LSBs of the base PCR that normally counts at a 90 kHz rate Since the system time clock counter contin ues to count the DSP may need to read TSISTCLKL twice in a row to ensure an accurate value Figure 3 42 TSI System Time Clock LSB Register TSISTCLKL 31 0 PCR R W 0 Legend R W Read Write n value after reset Table 3 27 TSI System Time Clock LSB Register TSISTCLKL Field Descriptions Description BT 656 Y C Mode Bit Field symvalt Value or Raw Data Mode 31 0 PCR OF value O FFFF FFFFh Not used TSI Mode Contains the 32 LSBs of the program clock reference t For CSL implementation use the notation VP_TSISTCLKL_PCR_symval 3 76 Video Capture Port SPRU629 Video Cap
292. rol signal VCOUNT increments when HCOUNT is reset 3 20 VMode O is used for BT 656 or Y C capture with embedded control and corre sponds to most digital video standards that number lines beginning with the start of vertical blanking VMode 1 can also be used for BT 656 or Y C capture but counts from the first active video line This makes field detection more straightforward in some instances see section 3 4 4 and allows the VCYSTARTR bit to be set to 1 but also has the effect of associating vertical blanking periods with the end of the previous field rather than the beginning of the current field This could be an issue when capturing VBI data VCOUNT operation for VMode 0 and VMode 1 is shown in Figure 3 8 VMode 2 and VMode 3 are used for BT 656 or Y C capture without embedded EAV SAV codes and allow alignment with either the active or inactive edge of the vertical control signal on VCTL2 This can be a VBLNK or VSYNC signal from the video decoder Video Capture Port SPRU629 BT 656 and Y C Mode Field and Frame Operation Figure 3 8 VCOUNT Operation Example EXC 0 VRST 0 VRST 1 FINV 0 FINV 1 FINV 0 FINV 1 BN VCOUNT mag Field VGGUNT Field Field 01 5 5 262 1 2 243 2 1 1 1 1 1 2 1 244 1 1 2 m 2 245 1 3 3 3 246 10 aj 4 247 1 0 5 Field 1 Blanking m 5 248 Lip 1 Ng mw ow 10 ig 19 262 2 1 00 20 20 1 1 2 00 af A 21 2 ali Field 1 Active Ale NG
293. rored to the left of sample 0 and the last m samples before the last sample are mirrored to the right of the last sample Figure 3 15 shows edge pixel replication assuming an m value of 3 Sample a is the first sample after the SAV code Therefore samples b d are mirrored to the left of sample a to provide values for the filter calculations on the first few pixels in the line Likewise samples n 1 to n 3 are mirrored to the right of the last sample n to provide values for the last few pixels on the line Note that edge pixel replication only comes into effect when the full BT 656 stream is being captured If VCXSTART is greater than 0 then only some of the leading edge replicated pixels are used by the filter If VCXSTART is greater than m then none of the leading edge replicated pixels are used Similarly if VCXSTOP is less than the number of samples before EAV then none or only some of the trailing edge replicated pixels are used by the filters Figure 3 15 Edge Pixel Replication SAV a n 4 n 3 n 2 n 1 n EAV BOBO OXON v Active line n 4n 3n 2n 1 n N 1 n 2 n 3 OM OBOBOR OMOMOWOM os Leading edge replicated pixels Trailing edge replicated pixels Luma Y Chroma Cb Cr C sample P samples SPRU629 Video Capture Port 3 29 Video Input Filtering Figure 3 16 shows an example of a capture window that is smaller than the BT 656 active line Sample a is the first sample in the horizontal capture window and s
294. s In Y C mode the Y buffer is 2560 bytes and the Cr Cb buffers are 1280 bytes each The number of samples that the buffers can hold depends on the buffer packing mode as listed in Table 2 2 Video Port 2 13 Video Port Throughput and Latency Table 2 2 Y C Video Capture FIFO Capacity Sample 8 Bit 10 Bit Dense 10 Bit Y Samples 2560 1920 1280 Cb Samples 1280 960 640 Cr Samples 1280 960 640 Using these values and the formula above the maximum time to empty the FIFO to may be calculated for each case The DMA output rate ro is then calculated as the FIFO size divided by to 8 bit n 1 to lt tr n ty to lt 2560 74 25 MHz 1 3 77 us to lt 38 3 us ro 9 5120 7 4 ns 134 MBytes s 10 bit dense n 1 to tp n ty to lt 1920 74 25 MHz 1 3 77 us to lt 29 63 us ro 9 5120 5 79 ns 173 MBytes s 10 bit n 2 0 to lt tr n ty to lt 1280 74 25 MHz to lt 17 24 us ro 15 5120 3 37 ns 297 MBytes s A DMA read throughput of at least 300 MBytes s is required for the highest capture rate operation supported by 20 bit implementations of the video port C64x devices including the video port typically have more than enough DMA bandwidth to support the highest throughput required by a single video port However when using multiple high bandwidth peripherals together it is impor tant to consider the total DMA throughput required by the peripherals being used concurrently 2 14 Video Port SPRU62
295. s transmitted within the 48 bit stream and consists of a 33 bit PCR field that represents a 90 kHz clock sample and a 9 bit PCR extension field that repre sents a 27 MHz clock sample The PCR indicates the expected time at the completion of reading the field from the bit stream at the transport decoder The transport data packets are in sync with the encoder time clock 3 38 Video Capture Port SPRU629 TSI Capture Mode Figure 3 23 Program Clock Reference PCR Header Format 47 15 14 9 8 0 PCR PCR extension The video port in conjunction with the VCXO interpolated control VIC allows a combined hardware and software solution to synchronize the local system time clock STC with the encoder time clock reference transmitted in the bit stream The video port maintains a hardware counter that counts the system time The counter is driven by a system time clock STCLK input driven by an external VCXO The counter is split into two fields a 33 bit field PCR base that counts at 90 kHz and a 9 bit field PCR extension that counts at 27 MHz The 9 bit counter counts from 0 to 299 at 27 MHz Each time the 9 bit counter rolls over to 0 the 33 bit counter is incremented by 1 This is equivalent to the PCR time stamp transmitted in the bit stream The 33 bit field can also be programmed to count at 27 MHz for compatibility with the MPEG 1 32 bit PCR by setting the CTMODE bit in VCCTL to 1 in which case the PCR extension portion of the cou
296. s video capture video display BT 656 mode blanking codes BT 656 image displa capture channels capture selection capturing video data sampling display timing reference codes displaying video field and frame operation FIFO overrun FIFO packing 3 9 FIFO unpacking image window and capture timing reference codes video capture video display 4 9 CAPEVTCT1 bits CAPEVTCT2 bits capture channel reset capture line boundary conditions capture selection BT 656 mode raw data mode TSI capture mode capturing data in TSI capture mode Y C mode capturing video BT 656 mode raw data mode Y C mode Cb FIFO destination register CBDST Cb FIFO source register CBSRCx Index 1 Index CbDEFVAL bits CBDST CBSRCx CCMPA bit in VPIE in VPIS CCMPB bit in VPIE 2 21 in VPIS 2 24 CF1 bit in VCACTL 3 53 in VCBCTL 3 68 CF2 bit in VCACTL 3 53 in VCBCTL 3 68 CLASS bits 5 3 CLIPCHIGH bits CLIPCLOW bits CLIPYHIGH bits CLIPYLOW bits clocks CMODE bits in VCACTL in VCBCTL CON bit in VCACTL in VCBCTL COVRA bit in VPIE in VPIS COVRB bit in VPIE in VPIS Cr FIFO destination register CRDST Cr FIFO source register CRSRCx CrDEFVAL bits CRDST CRLD bits CRSRCx 3 83 CTMODE bit 3 72 r r Index 2 DCDIS bit 2 20 DCHNL bit 2 17 DCMP bit in VPIE in VPIS 2 24 DCNA bit in VPIE 2 in VPIS 2 24 DEFVAL bits 4 87 DF1 bit DF2 bit DISP bit DIS
297. s in YCbCr 4 2 2 with 10 bit resolution on parallel Y and Cb Cr multiplexed channels Raw 16 bit data capture at sampling rates up to 80 MHz Raw 20 bit data capture at sampling rates up to 80 MHz 8 bit parallel TSI capture at rates up to 30 MHz 3 2 Video Capture Port SPRU629 BT 656 Video Capture Mode 3 2 BT 656 Video Capture Mode The BT 656 capture mode captures 8 bit or 10 bit 4 2 2 luma and chroma data multiplexed into a single data stream Video data is conveyed in the order Cb Y Cr Y Cb Y Cr etc where the sequence Cb Y Cr refers to co sited luma and chroma samples and the following Y value corresponds to the next lu minance sample The data stream is demultiplexed and each component is written in packed form into separate FIFOs for transfer into Y Cb and Cr buff ers in DSP memory This is commonly called planar format The packing and order of the samples is determined by the sample size 8 bit or 10 bit and the selected endianess of the DSP The ITU BT 656 standard provides for either 8 bit or 10 bit component sam ples When 10 bit samples are used the 2 least significant bits are considered fractional values Thus for 8 bit operation input data is aligned to the most sig nificant bits 9 2 of the input and the two least significant bits are ignored In BT 656 video capture mode data bytes in which the 8 most significant bits are all set to 1 FF 0h FF 4h FF 8h FF Ch or are all set to O 00 0h
298. selected by the HRST bit in VCxCTL and the vertical line counter is reset by the vertical event as selected by the VRST bit in VCxCTL Field 2 capture starts when HCOUNT VCXSTART VCOUNT VCYSTART and field 2 capture is enabled These registers are not used in raw data mode or TSI mode because their capture sizes are completely defined by the field 1 start and stop registers Figure 3 33 Video Capture Channel x Field 2 Start Register VCASTRT2 VCBSTRT2 31 28 27 16 R 0 R W 0 15 12 11 0 R 0 R W 0 Legend R Read only R W Read Write n value after reset Table 3 18 Video Capture Channel x Field 2 Start Register VCxSTRT2 Field Descriptions Description Bit field symvalt Value BT 656 or Y C Mode TSI Mode 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 VCYSTART OF value O FFFh Starting line number Not used Not used 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 VCXSTART OF value O FFFh Starting pixel number Not used Not used Must be an even number LSB is treated as 0 t For CSL implementation use the notation VP_VCxSTRT2_field_symval SPRU629 Video Capture Port 3 61 Video Capture Registers 3 13 6 Video Capture Channel x Field 2 Stop Register VCASTOP2 VCBSTOP2 The video capture channel x field 2 stop register VCASTOP2 V
299. ster VICCTL 31 16 Reserved R 0 15 4 3 1 0 PRECISION R 0 R W 0 R W 0 Legend R Read only R W Read Write n value after reset Table 6 4 VIC Control Register VICCTL Field Descriptions Bit fieldt symvalt Value Description 31 4 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 3 1 PRECISION 0 7h Precision bits determine the resolution of the interpolation The PRECISION bits can only be written when the GO bit is cleared to 0 If the GO bit is set to 1 a write to the PRECISION bits does not change the bits 16BITS 0 16 bits 15BITS 1 15 bits 14BITS 2h 14 bits 13BITS 3h 13 bits 12BITS 4h 12 bits 11BITS 5h 11 bits 10BITS 6h 10 bits 9BITS 7h 9 bits t For CSL implementation use the notation VIC_VICCTL_field_symval 6 6 VCXO Interpolated Control Port SPRU629 VIC Port Registers Table 6 4 VIC Control Register VICCTL Field Descriptions Continued Bit 0 fieldt GO symvalt Value Description The GO bit can be written to at any time The VICDIV and VICCTL registers can be written to without affecting the operation of the VIC port All the logic in the VIC port is held in reset state and a 0 is output on the VCTL output line A write to VICCTL bits as well as setting GO to 1 is allowed in a single write operation The VICCTL bits change and the GO bit is set disallowing any further changes to the VICCTL and VICDIV regist
300. sults O KONONONONONO QOQO OO OO AO go N7 Ch Cb Cr D Cb er 3Cbc 101Cbe 33Cbg 3Cb 128 W Chroma r ms ie ZN samples Cr ef 3Cre 101Cre 33Crg 3Cri 128 3 5 3 Scaling Operation SPRU629 The 1 2 scaling mode is used to reduce the horizontal resolution of captured luminance and chrominance data by a factor of two For applications that require only CIF or lower resolutions this reduces the video capture buffer memory requirements and the bandwidth needed to write the buffer by a factor of two Vertical scaling must be performed in software The bandwidth to load in the buffer is again reduced by 5096 over the nonhorizontal scaled case The filtering for the luminance portion of the scaling filter changes depending onif chrominance resampling is also enabled By changing the luminance filter the chrominance filters can remain the same The resulting values are clamped to between 01h and FEh andsenttothe Y Cb and Cr capture buffers Scaling for co sited capture is shown in Figure 3 13 and scaling for chromi nance resampling is shown in Figure 3 14 Video Capture Port 3 27 Video Input Filtering Figure 3 13 1 2 Scaled Co Sited Filtering Venere dun a b c d e f g h j k input sariples NG O NG O NG O NG O NG O O ap Paa Qu O MW CX SS O Ly 3Ye 32Yg 70Yp 32Y 3Yp 128 Luma Y Chroma Cb Cr sample Samples Y au 32Ye 70Y 32Yg 3Y 128 Ch 1Cbe 17Cbet 17Cb
301. symvalt Value Description 2 TSI TSI capture mode select bit NONE 0 TSI capture mode is disabled CAPTURE 1 TSI capture mode is enabled 1 DISP Display mode select bit VDATA pins are configured for output VCLK2 pin is configured as VCLKOUT output CAPTURE 0 Capture mode is enabled DISPLAY 1 Display mode is enabled 0 DCHNL Dual channel operation select bit If the DCDIS bit in VPSTAT is set this bit is forced to 0 SINGLE 0 Single channel operation is enabled DUAL 1 Dual channel operation is enabled t For CSL implementation use the notation VP VPCTL field symval Table 2 6 Video Port Operating Mode Selection VPCTL Bit TSI DISP DCHNL Operating Mode 0 0 0 Single channel video capture BT 656 Y C or raw mode as selected in VCACTL Video capture B channel not used 0 0 1 Dual channel video capture Either BT 656 or raw 8 10 bit as selected in VCACTL and VCBCTL Option is available only if DCDIS is 0 0 1 X Single channel video display BT 656 Y C or raw mode as selected in VDCTL Video display B channel is only used for dual channel sync raw mode 1 x x Single channel TSI capture SPRU629 Video Port 2 19 Video Port Control Registers 2 7 2 Video Port Status Register VPSTAT The video port status register VPSTAT indicates the current condition of the video port The VPSTAT is shown in Figure 2 4 and described in Table 2 7 Figure 2 4 Video Port Status Register VPSTAT 31 16 R 0 15 4 3 2 1 0 00015 HIDATA R
302. t is required set the video display field 1 timing Specify the line and pixel where FLD goes inactive VDFLDT1 Set the video display field 2 timing Specify the line and pixel where FLD goes active VDFLDT2 11 Set VDCLIP Default values for video clipping are 16 for the lower clipping SPRU629 235 for the higher clipping of the Y values and 240 for the higher clipping of the Cb and Cr values Video Display Port 4 47 Displaying Video in BT 656 or Y C Mode 12 Configure a DMA to move data from the Y buffer in the DSP memory to YDSTA memory mapped Y display FIFO The transfers should be triggered by the YEVT 13 Configure a DMA to move data from the Cb buffer in the DSP memory to CBDST memory mapped Cb display FIFO The transfers should be triggered by the CbEVT The size of the transfers should be set to 1 2 the Y transfer size 14 Configure a DMA to move data from the Cr buffer in the DSP memory to CRDST memory mapped Cr display FIFO The transfers should be triggered by the CrEVT The size of the transfers should be set to the Y transfer size 15 Set DISPEVT1 and DISPEVT2 bits in VDDISPEVT Event count is total doublewords per field divided by total doublewords per Y DMA 16 Write to VPIE to enable underrun DUND and display complete DCMP interrupts if desired 17 Write to VDTHRLD to set the display FIFO threshold VDTHRLD bits 18 Write to VDCTL to Od Set display mode DMODE 00x for BT 656
303. t line with an EAV with F 1 indicating Field 2 display xy LA X Define horzontal synchronization x define VD HSYNC START 736 define VD HSYNC STOP 800 L38 7 Define vertical synchronization for fieldl Z8 xf define VD VSYNC XSTART1 720 define VD VSYNC YSTART1 4 define VD VSYNC XSTOP1 720 define VD VSYNC YSTOP1 7 SPRU629 Video Port Configuration Examples A 11 Example 2 Noncontinuous Frame Display for 525 60 Format tf Define vertical synchronization for field2 E define VD_VSYNC_XSTART2 360 define VD_VSYNC_YSTART2 266 define VD_VSYNC_XSTOP2 360 define VD_VSYNC_YSTOP2 269 a kf Define image offsets for both the fields which are zero in this example pi px ay D a horizontal image size vertical image size horizontal image size define VD IMG HOFF1 0 define VD IMG VOFF1 0 define VD IMG HOFF2 0 define VD IMG VOFF2 0 Define image active vertical and horizontal sizes define VD IMG HSIZE1 720 fieldl define VD IMG VSIZE1 244 fieldl define VD IMG HSIZE2 720 field2 define VD IMG VSIZE2 243 field2 define VD I define VD I Define threshold values in double words AGE SIZE1 AGE SIZE2 have same threshold value define VD VDTHRID1 define VD VDTHRLD2 VD IMG HSIZI VD VDTHRID1 Define number of define VD DISPEVT1
304. t number i e Sets up DMA channels for Y U QL Or zx V events for VP void setupVPDisp A 18 Int32 YEvent U get Y U V switch portNumb case VP_DEVO YEven case VP DEV1 YEven case VP_DEV2 YEven Configure Y Y data buffe configVPDispEDMAChannel gh Configure Cb Cb data buffer EDMA Int32 portNumber Event VEvent er UEvent E VEvent E break UEvent E VEvent E break UEven VEven break Ej Ej Dd ct ct ct EDMA channel to to YDSTA EdmaVPDispY YEvent r dispYSpace EDMA event numbers CHA VPOEVTYA CHA VPOEVTUA CHA_VPOEVTVA CHA_VP1EVTYA CHA_VP1EVTUA CHA_VP1EVTVA HA VP2EV e YA CHA VP2EV C UA move data from FIFO amp edmaDispYTccNum Uint32 dispYSpace vpDisplayHandle ydstaAddr VD Y EDMA FR CNT VD Y EDMA ELECNT EDMA channel dispCbSpace LO move data from to CbDSTA FIFO configVPDispEDMAChannel amp hEdmaVPDispCb UEvent amp edmaDispCbTccNum Uint32 dispCbSpace vpDisplayHandle 5cbdstAddr Configure Cr Cr data buffer VD Y EDMA FR CNT VD Y EDMA ELECNT 2 EDMA channel dispCrSpace LO move data from to CrDSTA FIFO configVPDispEDMAChannel amp hEdmaVPDispCr VEvent amp edmaDispCrTccNum Uint32
305. ta Mode 31 28 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 27 16 VBLNKYSTOP1 OF value O FFFh Specifies the line in Specifies the line in FLCOUNT where FLCOUNT where vertical VBLNK inactive edge blanking ends VBLNK occurs for field 1 Does inactive edge for field 1 not affect EAV SAV V bit operation 15 12 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 11 0 VBLNKXSTOP1 OF value O FFFh Specifies the pixel in Specifies the pixel in FPCOUNT where FPCOUNT where VBLNK inactive edge vertical blanking ends occurs for field 1 VBLNK inactive edge for field 1 t For CSL implementation use the notation VP VDVBLKE1 field symval 4 12 7 Video Display Field 2 Vertical Blanking Start Register VDVBLKS2 SPRU629 The video display field 2 vertical blanking start register VDVBLKS2 controls the start of vertical blanking in field 2 The VDVBLKS2 is shown in Figure 4 45 and described in Table 4 12 In raw data mode VBLNK is asserted whenever the frame line counter FLCOUNT is equal to VBLNKYSTART2 and the frame pixel counter FPCOUNT is equal to VBLNKXSTART2 this is shown in Figure 4 6 page In BT 656 and Y C mode VBLNK is asserted whenever FLCOUNT VBLNKYSTART2 and FPCOUNT VBLNKXSTART2 This VBLNK output control is completely independent of the timing control codes The V bit in the EAV
306. tartup synch enable EJ KK KK KR KR A AA A A A A A A A A KK A A A Kk kk A ko ke ok koe ok oe eoe x x f include lt csl_vp h gt include lt csl_edma h gt include csl irq h kai Xy global variable declarations 7 VP Handle vpCaptureHandle handle of vp that to be configured x Uint8 capChaAYSpace buffer to store captured Y data xir Uint8 capChaACbSpace buffer to store captured Cb data kj Uint8 capChaACrSpace buffer to store captured Cb data kf EDMA Handle hEdmaVPCapChaAY EDMA Handle hEdmaVPCapChaACb EDMA Handle hEdmaVPCapChaACr Int32 edmaCapChaAYTccNum 0 EDMA tcc for Y channel Int32 edmaCapChaACbTccNum 0 EDMA tcc for Cb channel Int32 edmaCapChaACrTccNum 0 EDMA tcc for Cb channel volatile Uint32 capChaAFrameCount 0 no of frames captured SPRU629 Video Port Configuration Examples A 3 Example 1 Noncontinuous Frame Capture for 525 60 Format Error flags volatile Uint32 volatile Uint32 volatile Uint32 capChaAOverrun capChaASyncError 0 capChaAShortFieldDetect 0 volatile Uint32 capChaALongFi eldDetect 0 Function Input s bt656 8bit n portNumber efc video port number i e O Ll or 2 Description Configures given video port for 8 bit BT 656 non je continuos frame capture on channel A void bt656 8bit ncfc int portNumber A 4 Open video port for vpCap
307. terrupt Enable Register PIEN Field Descriptions Bit fieldt symvalt Value Description 31 23 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 22 PIEN22 PIEN22 bit enables the interrupt on the VCTL3 pin VCTL3LO 0 Interrupt is disabled VCTL3HI 1 Pin enables the interrupt 21 PIEN21 PIEN21 bit enables the interrupt on the VCTL2 pin VCTL2LO 0 Interrupt is disabled VCTL2HI 1 Pin enables the interrupt 20 PIEN20 PIEN20 bit enables the interrupt on the VCTL1 pin VCTL1LO 0 Interrupt is disabled VCTL1HI 1 Pin enables the interrupt 19 0 PIEN 19 0 PIEN 19 0 bits enable the interrupt on the corresponding VDATA n pin VDATAnLO 0 Interrupt is disabled VDATAnHI 1 Pin enables the interrupt t For CSL implementation use the notation VP_PIEN_PIENn_symval 5 20 General Purpose I O Operation SPRU629 GPIO Registers 5 1 10 Video Port Pin Interrupt Polarity Register PIPOL The video port pin interrupt polarity register PIPOL is shown in Figure 5 10 and described in Table 5 11 The PIPOL determines the GPIO pin signal polarity that generates an interrupt Figure 5 10 Video Port Pin Interrupt Polarity Register PIPOL 31 24 R 0 23 22 21 20 19 18 17 16 PIPOL22 PIPOL21 PIPOL20 PIPOL19 PIPOL18 PIPOL17 PIPOL16 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 PIPOL15 PIPOL14 PIPOL13 PIPOL12 PIPOL11 PIPOL10 P
308. th circular buffering capabili ty to service the display FIFOs When CON 0 continuous display is disabled the video port sets a field or frame display complete bit F1D F2D or FRMD in VDSTAT upon the display of each field as determined by the state of the other display control bits FRAME CD1 and CD2 Once the display complete bit is set the processor must update the appropriate DMA parameters within the allotted time frame or a subsequent field or frame may output invalid data In this case the video port continues to generate DMA requests but it issues a DCNA display complete not acknowledged interrupt to indicate that the DMA parameters may not have been updated and bad data is being sent to the video port When a field or frame has not been enabled for display no DMA events are sentfor that field or frame The video port still generates all timings for the field but outputs the default data values rather than data from the display FIFO during the display image window The CON FRAME DF1 and DF2 bits encode the display operations as listed in Table 4 4 Video Display Port SPRU629 Table 4 4 Display Operation VDCTL Bit CON FRAME DF2 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 SPRU629 DF1 0 1 Video Display Field and Frame Operation Operation Reserved Noncontinuous field 1 display Display only field 1 F1D is set after field 1 display and causes DCMPx to be set The F1D bit must
309. the line length rounded up to the next doubleword This always works because differ ent lines are not packed together within a doubleword and the Cb and Cr thresholds v VCTHRLDx VDTHRLD are always rounded up to the double word For example in 8 bit BT 656 capture mode with a line length of 712 Y setting the threshold to the line length results in a VCTHRLD of 712 pixels x 1 bytes pixel x doubleword 8 bytes 89 doublewords The Cb and Cr FIFOs contain half the data 44 5 doublewords so their thresholds are set to 45 double words Therefore the Cb and Cr DMAs each transmit an extra 4 bytes at the end of each line If a multihorizontal line length threshold is desired 2 lines for example then the chosen line length must round up to an even number of doublewords so that it is evenly divisible by 2 If this is not the case then the Cb and Cr FIFO transfers are corrupted For the multiline case consider the same 8 bit BT 656 capture mode with a line length of 712 Y If the threshold is set for 2 lines this results in a VCTHRLD value of 2 x 89 178 doublewords The actual Cb Cr line length is 44 5 doublewords that requires a length of 45 To transfer 2 lines requires 2 x 45 90 doublewords However for this VCTHRLD the DMA logic would calculate the Cb Cr threshold size as 178 2 89 doublewords which is 1 doubleword off This can be corrected by increasing the line length to 720 pixels and ignoring the extra captured pixels or
310. tinues capturing field 1 fields regardless of the state of F1C 3 18 Video Capture Port SPRU629 BT 656 and Y C Mode Field and Frame Operation Table 3 6 BT 656 and Y C Mode Capture Operation Continued CON 1 VCxCTL Bit FRAME CF2 0 1 0 1 1 0 1 0 CF1 Operation 0 Continuous field 2 capture Capture only field 2 F2C is set after field 2 capture and causes CCMPx to be set CCMPx interrupt can be disabled The video port continues capturing field 2 fields regardless of the state of F2C 1 Reserved 0 Continuous frame capture Capture both fields FRMC is set after field 2 capture and causes CCMPx to be set CCMPx interrupt can be disabled The video port continues capturing frames regardless of the state of FRMC 1 Continuous progressive frame capture Capture field 1 FRMC is set after field 1 capture and causes CCMPx to be set CCMPx interrupt can be disabled The video port continues capturing frames regardless of the state of FRMC Functions identically to continuous field 1 capture mode except the FRMC bit is used instead of the F1C bit 0 Reserved 1 Reserved 3 4 2 Vertical Synchronization SPRU629 The video port uses a capture window to determine which incoming data samples to capture in each field The capture module uses a vertical line counter VCOUNT to track which video line is currently being received The line count er is compared to the appropriate capture window start VCYSTART1 o
311. tion Rate 6 4 Table 6 2 gives some k and R values for different D s with f fixed at 40 kHz Once a suitable interpolation frequency is determined the clock divider can be set p 9 k 96 0 151 0 240 0 381 0 605 0 960 0 1523 0 2418 0 VCXO Interpolated Control Port R 3 8 MHz 6 0 MHz 9 6 MHz 15 2 MHz 24 2 MHz 38 4 MHz 60 9 MHz 96 7 MHz SPRU629 Enabling VIC Port VIC Port Registers 6 4 Enabling VIC Port Perform the following steps to enable the VIC port 1 Clear the GO bit in the VIC control register VICCTL to 0 2 Setthe PRECISION bits in VICCTL to the desired precision 3 Setthe VIC clock divider register VICDIV bits to appropriate value based on the precision and interpolation frequency 4 Setthe GO bit in VICCTL to 1 5 The VIC input register VICIN is written into every time a new input code is available for interpolation Repeat step 3 as often as needed 6 5 VIC Port Registers The VIC port registers are listed in Table 6 3 See the device specific data sheet for the memory address of these registers Table 6 3 VIC Port Registers Acronym Register Name Section VICCTL VIC Control Register VICIN VIC Input Register 6 5 2 VICDIV VIC Clock Divider Register SPRU629 VCXO Interpolated Control Port 6 5 VIC Port Registers 6 5 1 VIC Control Register VICCTL The VIC control register VICCTL is shown in Figure 6 3 and described in Table 6 4 Figure 6 3 VIC Control Regi
312. tion VP VPIS field symval N 24 Video Port SPRU629 Video Port Control Registers Table 2 9 Video Port Interrupt Status Register VPIS Field Descriptions Continued Bit field symval Value Description 22 SFDB Short field detected on channel B interrupt detected bit BT 656 or Y C capture mode SFDB is set when short field detection is enabled and VCOUNT is reset before VCOUNT YSTOP Raw data mode or TSI capture mode or display mode Not used NONE 0 No interrupt is detected CLEAR 1 Interrupt is detected Bit is cleared 21 VINTB2 Channel B field 2 vertical interrupt detected bit BT 656 or Y C capture mode VINTB2 is set when a vertical interrupt occurred in field 2 Raw data mode or TSI capture mode Not used NONE 0 No interrupt is detected CLEAR 1 Interrupt is detected Bit is cleared 20 VINTB1 Channel B field 1 vertical interrupt detected bit BT 656 or Y C capture mode VINTB1 is set when a vertical interrupt occurred in field 1 Raw data mode or TSI capture mode Not used NONE 0 No interrupt is detected CLEAR 1 Interrupt is detected Bit is cleared 19 SERRB Channel B synchronization error interrupt detected bit BT 656 or Y C capture mode Synchronization parity error on channel B An SERRB typically requires resetting the channel RSTCH or the port VPRST Raw data mode or TSI capture mode Not used NONE 0 No interrupt is detected CLEAR 1 Interrupt is detected Bit is clear
313. tion is always read as 0 A value written to this field has no effect 2 0 CMODE Capture mode select bit BT656B 0 Enables 8 bit BT 656 mode Not used BT656D 1h Enables 10 bit BT 656 mode Not used RAWB 2h Enables 8 bit raw data mode 8 bit TSI mode RAWD 3h Enables 10 bit raw data mode Not used YCB 4h Enables 16 bit Y C mode Not used YCD 5h Enables 20 bit Y C mode Not used RAW16 6h Enables 16 bit raw mode Not used RAW20 7h Enables 20 bit raw mode Not used t For CSL implementation use the notation VP_VCACTL_field_symval For complete encoding of these bits see Table 3 6 Table 3 11 and Table 3 12 SPRU629 Video Capture Port 3 57 Video Capture Registers 3 13 3 Video Capture Channel x Field 1 Start Register VCASTRT1 VCBSTRT1 The captured image is a subset of the incoming image The video capture channel x field 1 start register VCASTRT1 VCBSTRT1 defines the start of the field 1 captured image Note that the size is defined relative to incoming data before scaling VOXSTRT1 is shown in Figure 3 31 and described in Table 3 16 In BT 656 or Y C modes the horizontal pixel counter is reset to 0 by the hori zontal event as selected by the HRST bit in VCxCTL and the vertical line counter is reset to 1 by the vertical event as selected by the VRST bit in VCxCTL Field 1 capture starts when HCOUNT VCXSTART VCOUNT VCYSTART and field 1 capture is enabled In raw capture mode the VCVBLNKP bits d
314. tions 3 28 TSI System Time Clock MSB Register TSISTCLKM Field Descriptions 3 29 TSI System Time Clock Compare LSB Register TSISTCMPL Field Descriptions 3 30 TSI System Time Clock Compare MSB Register TSISTCMPM Field Descriptions 3 31 TSI System Time Clock Compare Mask LSB Register TSISTMSKL Field Descriptions crescer aaa aa o NE een 888 3 32 TSI System Time Clock Compare Mask MSB Register TSISTMSKM Field Descriptions aaa in NM ee 3 33 TSI System Time Clock Ticks Interrupt Register TSITICKS Field Descriptions 3 34 Video Capture FIFO Registers 0 0 c cece een 3 35 Video Capture FIFO Registers Function 0000 eee eee e eee eae 4 1 Video Display Mode Selection 00 060 c cece eee 4 2 BT 656 Frame Timing aaa gee BAM eee eed 4 3 Output Filter Mode Selection 0 cece cece tenet e eee e eens 4 4 Display Operation fft WB WP eee 4 5 Video Display Control Registers eee eee e eee nes 4 6 Video Display Status Register VDSTAT Field Descriptions 4 7 Video Display Control Register VDCTL Field Descriptions aa 4 8 Video Display Frame Size Register VDFRMSZ Field Descriptions 4 9 Video Display Horizontal Blanking Register VDHBLNK Field Descriptions 4 10 Video Display Field 1 Vertical Blanking Start Register VDVBLKS1 Field Desc
315. to be set A DCNA interrupt occurs upon completion of the next frame unless the FRMD bit is cleared The DSP has the entire next frame time to clear FRMD If external control signals are used they must follow progressive format Reserved Single frame display Display both fields FRMD is set after field 2 dis play and causes DCMPx to be set A DONA interrupt occurs unless the FRMD bit is cleared The DSP has the field 2 to field 1 vertical blank ing time to clear FRMD Reserved Continuous field 1 display Display only field 1 F1D is set after field 1 display and causes DCMPx to be set DCMPx interrupt can be dis abled No DONA interrupt occurs regardless of the state of F1D Video Display Port 4 31 Video Display Field and Frame Operation Table 4 4 Display Operation Continued VDCTL Bit CON FRAME DF2 DF1 Operation 1 0 1 0 Continuous field 2 display Display only field 2 F2D is set after field 2 display and causes DCMPx to be set DCMPx interrupt can be dis abled No DCNA interrupt occurs regardless of the state of F2D 1 0 1 1 Reserved 1 1 0 0 Continuous frame display Display both fields FRMD is set after field 2 display and causes DCMPx to be set DCMPx interrupt can be dis abled No DCNA interrupt occurs regardless of the state of FRMD 1 1 0 1 Continuous progressive frame display Display field 1 FRMD is set af ter field 1 display and causes DCMPx to be set DCMPx interrupt can be disabled No DON
316. ture Mode Selection The video capture module operates in one of nine modes as listed in Table 3 1 The transport stream interface TSI selection is made using the TSI bit in the video port control register VPCTL The CMODE bits are in the video capture channel x control register VCxCTL The Y C and 16 20 bit raw capture modes may only be selected for channel A and only if the DCHNL bit in VPCTL is cleared to O When operating as a raw video capture channel no data selection or data interpretation is performed The 16 20 bit raw capture mode is designed to accept data from A D converters with resolution higher than eight bits used for example in medical imaging Table 3 1 Video Capture Mode Selection TSI Bit CMODE Bits Mode 0 000 8 Bit ITU R BT 656 Capture 0 001 10 Bit ITU R BT 656 Capture 0 010 8 Bit Raw Capture 0 011 10 Bit Raw Capture 0 100 8 Bit Y C Capture 0 101 10 Bit Y C Capture 0 110 16 Bit Raw Capture 0 111 20 Bit Raw Capture 1 010 TSI Capture Description Digital video input is in YCbCr 4 2 2 with 8 bit resolution multiplexed in ITU R BT 656 format Digital video input is in YCbCr 4 2 2 with 10 bit resolution multiplexed in ITU R BT 656 format Raw 8 bit data capture at sampling rates up to 80 MHz Raw 8 bit or 10 bit data capture at sampling rates up to 80 MHz Digital video input is in YCbCr 4 2 2 with 8 bit resolution on parallel Y and Cb Cr multiplexed channels Digital video input i
317. ture Registers 3 13 15 TSI System Time Clock MSB Register TSISTCLKM The transport stream interface system time clock MSB register TSISTCLKM contains the most significant bit MSB of the program clock reference PCR and the 9 bits of the PCR extension The system time clock value is obtained by reading TSISTCLKM and TSISTCLKL TSISTCLKM is shown in Figure 3 43 and described in Table 3 28 The PCRE value changes at a 27 MHz rate and is probably not reliably read by the DSP The PCRM bit normally changes at a 10 5 uHz rate every 26 hours Figure 3 43 TSI System Time Clock MSB Register TSISTCLKM 31 16 Reserved R 0 15 10 9 1 0 PORE PCRM R 0 R W 0 R W 0 Legend R Read only R W Read Write n value after reset Table 3 28 TSI System Time Clock MSB Register TSISTCLKM Field Descriptions Description BT 656 Y C Mode Bit fieldt symvalt Value or Raw Data Mode TSI Mode 31 10 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 9 1 PCRE OF value 0 1FFh Not used Contains the extension portion of the program clock reference 0 PCRM OF value 0 1 Not used Contains the MSB of the program clock reference T For CSL implementation use the notation VP TSISTCLKM field symval SPRU629 Video Capture Port 3 77 Video Capture Registers 3 13 16 TSI System Time Clock Compare LSB Register TSISTCMPL The transport stream interface system t
318. tureHandl capture if vpCaptureHandle test_exit FAIL Enable video port functionali Control Reg PCR VP_FSETH vpCaptureHandle VP open portNumber INV VP OPEN RESET x Enable all interrupts Enable capture overrun interrupt COVRA H vpCaptureHandle VP FSE Enable captur IYA VPIE COVRA VP VP VP FSE complete in H vpCaptureHandle rrupt CCMPA VPIE CCMPA VP VP Enable channel synchronization error inte VP channel A PCR PEREN VP PCR PEREN ty in VP Peripheral ENABLE for VP channel A IE COVRA ENABLE for VP channel A for rrupt SERRA IE CCMPA ENABLE Xf EN uf 1 K u VP FSETH vpCaptureHandle VPIE SERRA VP VPIE SERRA ENABLE Enable short field detect interrupt SFDA for VP channel A VP FSETH vpCaptureHandle VPIE SFDA VP VPIE SFDA ENABLE Enable video port global interrupt enable VP FSETH vpCaptureHandle VPIE VIE VP VPIE VIE ENABLE Ed Setup all other fields Bili Enable short field detect VP FSETH vpCaptureHandle VCACTL SFDE VP VCACTL SFDE ENABL Set last pixel to be captured in Fieldl VCA STOP1 reg VP RSETH vpCa
319. un the COVRxbit is set in VPIS This condition initiates an interrupt to the DSP if the overrun interrupt is enabled setting the COVRx bit in VPIE enables overrun interrupt The overrun interrupt routine should set the BLKCAP bit in VCxCTL and it should reconfigure DMA channel settings The DMA channel must be reconfi gured for capture of the next frame since the current frame transfer failed Set ting the BLKCAP bit flushes the capture FIFO and blocks DMA events for the channel As long as the BLKCAP bit is set the video capture channel ignores the incoming data but the internal data counter continues counting The BLKCAP bit should be cleared to 0 in order to continue capture Clearing the BLKCAP bit takes effect on the next PACSTRT DMA events are still going to be blocked in the TSI packet in which the BLKCAP bit is cleared Video Capture Port SPRU629 Video Capture Registers 3 13 Video Capture Registers The registers for controlling the video capture mode of operation are listed in Table 3 13 See the device specific datasheet for the memory address of these registers Table 3 13 Video Capture Control Registers Acronym Register Name Section VCASTAT Video Capture Channel A Status Register 3 13 1 VCACTL Video Capture Channel A Control Register VCASTRT1 Video Capture Channel A Field 1 Start Register VCASTOP1 Video Capture Channel A Field 1 Stop Register 3 13 4 VCASTRT2 Video Capture Channel A Field 2 Start Register VCASTOP2
320. upt enable register VPIE interrupt status register VPIS peripheral control register PCR peripheral identification register VPPID pin data clear register PDCLR pin data input register PDIN pin data output register PDOUT pin data set register PDSET pin direction register PDIR pin function register PFUNC pin interrupt clear register PICLR pin interrupt enable register PIEN pin interrupt polarity register PIPOL pin interrupt status register PISTAT status register VPSTAT related documentation from Texas Instruments reset operation RESMPL RESMPL bit in VCACTL in VCBCTL REVISION bits RGBX RSTCH bit in VCACTL in VCBCTL RSYNC Index 6 SERRA bit in VPIE 2 21 in VPIS 2 24 SERRB bit in VPIE 2 21 in VPIS 2 24 SFDA bit in VPIE 2 21 in VPIS 2 24 SFDB bit in VPIE 2 21 in VPIS 2 24 SFDE bit in VCACTL in VCBCTL SOFT bit software port reset SSE bit STC bit in VPIE in VPIS STEN bit TCKEN bit throughput and latency TICK bit in VPIE in VPIS TICKCT bits trademarks TSI bit TSI capture control register TSICTL TSI capture mode capture selection 3 40 capturing data data capture data capture notification error detection features FIFO overrun mode selection reading from the FIFO synchronizing the system clock timestamp format big endian timestamp format little endian writing to the FIFO SPRU629
321. ure 3 38 Video Capture Channel B Control Register VCBCTL 31 30 29 24 RSTCH BLKCAP R WS 0 R W 1 R 0 23 21 20 19 18 17 16 FINV var West R 0 R W 0 R 0 R W 1 R W 0 15 14 13 12 11 10 9 8 VCEN PK10B LFDE SFDE RESMPL SCALE R W 0 R W 0 R W 0 R W 0 R W 0 R 0 R W 0 7 6 5 4 3 2 1 0 FRAME CMODE R W 0 R W 0 R W 1 R W 1 R 0 R W 0 Legend R Read only R W Read Write WS Write 1 to reset write of 0 has no effect n value after reset Table 3 23 Video Capture Channel B Control Register VCBCTL Field Descriptions Description Bit fieldt symvalt Value BT 656 or Y C Mode TSI Mode 31 RSTCH Reset channel bit Write 1 to reset the bit a write of O has no effect NONE 0 No effect RESET 1 Resets the channel by blocking further DMA event generation and flushing the FIFO upon completion of any pending DMAs Also clears the VCEN bit All channel registers are set to their initial values RSTCH is autocleared after channel reset is complete t For CSL implementation use the notation VP_VCBCTL_field_symval For complete encoding of these bits see Table 3 6 Table 3 11 and Table 3 12 Co 68 Video Capture Port SPRU629 Video Capture Registers Table 3 23 Video Capture Channel B Control Register VCBCTL Field Descriptions Continued Bit fieldt symvalt 30 BLKCAP Description Value BT 656 or Y C Mode Raw Data Mode TSI Mode Block capture events bit BLKCAP functions as a capture FIFO reset without affecting the
322. ure Channel Reset A software reset may be performed on a single capture channel by setting the RSTCH bitin VCxCTL This reset requires that the channel VCLKIN be trans itioning On capture channel reset L No new DMA events are generated _j Peripheral bus accesses are acknowledged RREADY returned to prevent DMA lock up Any value returned on reads Channel capture registers are set to their default values Channel capture FIFO is flushed pointers reset The VCEN bit in VCxCTL is cleared to 0 D D D O The RSTCH bit self clears to O after completion of the above SPRU629 Video Port 2 3 Reset Operation Once the port is configured and the VCEN bit is set the setting of other VCxCTL bits except VCEN RSTCH and BLKCAP is prohibited and the capture counters begin counting When BLKCAP is cleared data capture and event generation may begin 2 1 5 Display Channel Reset 2 4 Video Port A software reset may be performed on the display channel by setting the RSTCH bit in VDCTL This reset requires that the channel VCLKIN be trans itioning On display channel reset J No new DMA events are generated _j Peripheral bus accesses are acknowledged WREADY returned to prevent DMA lock up Write data may be written into the FIFO or discarded Channel display registers are set to their default values Channel display FIFO is flushed pointers reset The VDEN bit in VDCTL is cleared to 0 Lo Q The RST
323. ut to the video port When the input is active the port places all I Os VD 19 0 VCTL1 VCTL2 VCTL3 and VCLK2 in a high impedance state 2 1 2 Peripheral Bus Reset 2 2 Video Port Peripheral bus reset is a synchronous hardware reset caused by a chip level reset operation The reset is initiated by a peripheral bus reset input to the video port This reset can be used internally continuously asserted to disable the video port for low power operation When the input is active the port does the following Places keeps all l Os VD 19 0 VCTL1 VCTL2 VCTL3 and VCLK2 in a high impedance state Flushes the FIFOs resets pointers Li Resets all port capture display and GPIO registers to their default values These may not complete until the appropriate module clock VCLK1 VCLK2 STCLK edges occur to synchronously release the logic from reset Clears PEREN bit in PCR to 0 Sets VPHLT bit in VPCTL to 1 While the peripheral remains disabled PEREN 0 VCLK1 VCLK2 and STCLK are gated off to save peripheral power _j Peripheral bus accesses are acknowledged RREADY WREADY returned to prevent DMA lock up Any value returned on reads data accepted or discarded on writes Peripheral bus MMR interface allows access to GPIO registers only PID PCR PFUNC PDIR PIN PDOUT PDSET PDCLR PIEN PIPOL PISTAT and PICLR O Port I Os VD 19 0 VCTL1 VCTL2 VCTL3 and VCLK2 remain in a
324. ve another DMA If the FIFO has at least VDTHRLDn locations available a DMA event is generated Once a DMA event has been requested another DMA event may not be generated until the servicing of the first DMA event has begun as indicated by the first write to the FIFO by the DMA event service If there is at least 2x the threshold space still available in the FIFO after the first DMA service is begun and the display event counter has not expired then another DMA event may be generated Thus up to one DMA request may be outstanding An incoming data counter is loaded with the VDTHRLDn or VDTHRLD7 2 for Cb and Cr FIFOs value at the beginning of each DMA event service and counts down the incoming DMA doublewords When the counter reaches 0 the DMA event is complete Figure 2 2 shows the display DMA event generation SPRU629 Figure 2 2 Display DMA Event Generation Flow Diagram Display data no DMA pending FIFO space threshold No Yes Eo Jes Event counter expired No Generate DMA event Display data DMA pending new events disabled Start of field FIFO empty Generate DMA event new events disabled Pending DMA S NO begun Yes Display data DMA lt FIFO underrun DMA Operation Display data Underrun error Underrun error active new events enabled FIFO space No 2x threshold FIFO underrun No Yes Und
325. ved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 5 ENSTC System time clock enable bit HALTED 0 Not used System time clock input is disabled to save power The system time clock counters and tick counter do not increment CLKED 1 Not used System time input is enabled The system time clock counters and tick counters are incremented by STCLK 4 TCKEN Tick count interrupt enable bit DISABLE 0 Not used Setting of the TICK bit is disabled SET 1 Not used The TICK bit in VPIS is set whenever the tick count is reached 3 STEN System time clock interrupt enable bit DISABLE 0 Not used Setting of the STC bit is disabled SET 1 Not used A valid STC compare sets the STC bit in VPIS 2 CTMODE Counter mode select bit 90KHZ 0 Not used The 33 bit PCR portion of the system time counter increments at 90 kHz when PCRE rolls over from 299 to 0 STCLK 1 Not used The 33 bit PCR portion of the system time counter increments by the STCLK input 1 ERRFILT Error filtering enable bit ACCEPT 0 Not used Packets with errors are received and the PERR bit is set in the timestamp inserted at the end of the packet REJECT 1 Not used Packets with errors are filtered out not received in the FIFO 0 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect t For CSL implementation use the notation VP_TSICTL_field_symval
326. vertical blank Not used Not used St V 0 EAV or VCTL2 inactive edge 16 HRST HCOUNT reset method bit EAV 0 EAV or Not used Not used VCTL1 active edge SAV 1 SAV or Not used Not used VCTL1 inactive edge 15 VCEN Video capture enable bit Other bits in VCACTL except RSTCH and BLKCAP bits may only be changed when VCEN 0 DISABLE 0 Video capture is disabled ENABLE 1 Video capture is enabled 14 13 PK10B 10 bit packing format select bit ZERO 0 Zero extend Zero extend Not used SIGN th Sign extend Sign extend Not used DENSEPK 2h Dense pack zero Dense pack zero Not used extend extend 3h Reserved Reserved Not used t For CSL implementation use the notation VP VCACTL field symval tFor complete encoding of these bits see Table 3 6 Table 3 11 and Table 3 12 SPRU629 Video Capture Port 3 55 Video Capture Registers Table 3 15 Video Capture Channel A Control Register VCACTL Field Descriptions Continued Description Bit field symvalt Value BT 656 or Y C Mode Raw Data Mode TSI Mode 12 LFDE Long field detect enable bit DISABLE 0 Long field detect Not used Not used is disabled ENABLE 1 Long field detect Not used Not used is enabled 11 SFDE Short field detect enable bit DISABLE 0 Short field detect Not used Not used is disabled ENABLE 1 Short field detect Not used Not used is enabled 10 RESMPL Chroma resampling enable bit DISABLE 0 Chroma resampling is Not used Not used disa
327. verview 1 9 Video Port FIFO For 8 10 bit raw video the FIFO is configured as a single buffer as shown in Figure 1 7 The FIFO outputs data on the VDOUT 9 0 half of the bus The FIFO has a single read pointer and write register YDSTA Figure 1 7 8 10 Bit Raw Video Display FIFO Configuration Display FIFO VDOUT 9 0 Data Buffer 5120 bytes For locked raw video the FIFO is split into channel A and B The channels are locked together and use the same clock and control signals Each channel uses a single buffer and write register YDSTx as shown in Figure 1 8 1 10 Overview SPRU629 Video Port FIFO Figure 1 8 8 10 Bit Locked Raw Video Display FIFO Configuration Display FIFO A VDOUT 9 0 Buffer A 2560 bytes Display FIFO B VDOUT 19 10 Buffer B 2560 bytes For 16 20 bit raw video the FIFO is configured as a single buffer as shown in Figure 1 9 The FIFO outputs data on VDOUT 19 0 The FIFO has a single read pointer and write register YDSTA Figure 1 9 16 20 Bit Raw Video Display FIFO Configuration Display FIFO VDOUTT 19 0 Data Buffer 5120 bytes SPRU629 Overview 1 11 Video Port FIFO Video Port Registers For Y C video display the FIFO is configured as a single channel split into sep arate Y Cb and Cr buffers with separate read pointers and write registers YDSTA CBDST and CRDST Figure 1 10 shows how Y data is output on the VDOUT 9 0 half of the bus and Cb Cr
328. video region The cap tured image position is defined by the VCxSTRT1 and VCxSTOP1 registers for field 1 and the VCxSTRT2 and VCxSTOP2 registers for field 2 The VCXSTART and VCXSTOP bits set the horizontal window position for the field relative to the HCOUNT pixel counter The VCYSTART and VCYSTOP bits set the vertical position relative to the VCOUNT line counter This is shown in Figure 3 1 HCOUNT increments on every chroma sample period every other VCLKIN rising edge for which capture is enabled Once VCOUNT VCYSTART line capture begins when HCOUNT VCXSTART It continues until HCOUNT VCXSTOP A fields capture is complete when HCOUNT VCXSTOP and VCOUNT VCYSTOP 3 6 Video Capture Port SPRU629 BT 656 Video Capture Mode Figure 3 1 Video Capture Parameters Hcount 0 Ycount 1 Capture Image Field 1 Ycount 1 I Capture Image Table 3 5 shows common digital camera standards and the number of fields per second number of active lines per field and the number of active pixels per line Table 3 5 Common Video Source Parameters Number of Active Lines Video Source Field 1 Field 2 Number of Active Pixels Field Rate Hz square pixel 240 240 640 60 60Hz 525 lines BT 601 244 243 720 60 60 Hz 525 lines square pixel 288 288 768 50 50Hz 625 lines BT 601 288 288 720 50 50 Hz 625 lines SPRU629 Video Capture Port 3 7 BT 656 Video Capture Mode For the BT 656 vi
329. w 14 Raw 13 Raw 12 Raw 11 Raw 10 Raw9 Raw 8 Raw 7 Raw 6 Raw 5 Raw 4 Y FIFO Raw 3 Raw 2 Raw 1 Raw 0 Little Endian Unpacking 63 5857 4847 4241 3231 2625 1615 109 0 Raw 12 Raw 13 Raw 14 Raw 15 Raw 8 Raw9 Raw 10 Raw 11 Raw 4 Raw 5 Raw 6 Raw 7 Y FIFO Raw 0 Raw 1 Raw 2 Raw 3 Big Endian Unpacking In 10 bit raw dense pack mode three samples are unpacked from each word in the FIFO as seen in Figure 4 27 Figure 4 27 10 Bit Raw Dense FIFO Unpacking VDOUT 9 0 63 61 5251 4241 3231 29 2019 109 0 Raw 17 Raw 16 Raw 15 Raw 14 Raw 13 Raw 12 Raw 11 Raw 10 Raw 9 Raw 8 Raw 7 Raw 6 Y FIFO Raw 5 Raw 4 Raw 3 Raw 2 Raw 1 Raw 0 Little Endian Unpacking 63 61 5251 4241 3231 29 2019 109 0 Raw 12 Raw 13 Raw 14 Raw 15 Raw 16 Raw 17 Raw 6 Raw 7 Raw 8 Raw 9 Raw 10 Raw 11 Raw 0 Raw 1 Raw2 Raw 3 Raw4 Raw 5 Y FIFO Big Endian Unpacking SPRU629 Video Display Port 4 27 Raw Data Display Mode Figure 4 28 shows the 16 bit raw mode Two samples are unpacked from each word of the FIFO Figure 4 28 16 Bit Raw FIFO Unpacking vuor LT LILI LILI LILI LI LILI LU u VDOUT 19 12 VDOUT 9 2 63 4847 3231 1615 Raw 11 Raw 10 Raw 9 Raw 8 Raw 7 Raw 6 Raw 5 Raw 4 Raw 3 Raw 2 Raw 1 Raw 0 Raw FIFO Little Endian Unpacking 63 4847 3231 1615 Raw
330. ws the output data and switching between Default Data and FIFO Data Three values are output sequentially on VDOUT for each pixel count Note that the default value is output during both the blanking and nondisplay image active video regions Video Display Port 4 39 Ov v Log Aejdsiq capi 629N4dS Figure 4 35 Raw Interlaced Display Horizontal Timing Example sejduiex 3 Buwi Aejdsig VCLKIN IuuuuuL numni ut un nnn nuu nnmnuUmnt j 414 n 2112 ka One Line Next Line FPCOUNT 720 721 735 736 799 800 857 0 1 7 8 9 71 712 719 720 721 IPCOUNT 703 703 703 703 703 703 703 703 703 1 703 703 703 703 703 VCTL1 HBLNK T gt N Lo VCTL1 HSYNO T 8 VCLKOUT UUUUU UU UU uui LU UU UU Uu UUUUUUUU Display Image k Blanking na Active Video VDOUT 19 0 8 FLCOUNT n i n ASSs T ooo cOooooo coo MAAN DO DODODO 33333 333333 332 arom 33 222222 SSSSS SSSSSS_SSSOGSEGE wgc SS SSSSSS FRERE S35888 SSS9z 2255 JASE HABITS oo ooo 000o DOD C OOOOGGO qo gooo oOOO00 DDODO DADADA AMOK cdceaxcoo ADAMA FRMWIDTH 858 IMGHOFF1 8 HSYNCSTART 736 HBLNKSTART 720 IMGHSIZE1 704 HSYNCSTOP 800 HBLNKSTOP 0 IMGHOFF2 8 IMGHS
331. xample 2 Noncontinuous Frame Display for 525 60 Format y Define vertical blanking bit VD VBITn reg values Ex define VD VBIT SET1 1 first line with an EAV with V 1 indicating the start of Fieldl a vertical blanking 7 define VD VBIT CIR1 20 first line with an EAV with V 0 x indicating the start of Fieldl active display EJ define VD_VBLNK1_SIZE VD_VBIT_CLR1 VD_VBIT_SET1 19 lines define VD_VBIT_SET2 264 first line with an EAV with V 1 indicating the start of Field2 vertical blanking uf define VD VBIT CLR2 283 first line with an EAV with V 0 indicating the start of Field2 active display ay define VD VBLNK2 SIZE VD VBIT CLR2 VD VBIT SET2 19 lines f PR 22S x Field timing fam x define VD FIELD1 XSTAR 720 pixel on the first line of Fieldl on which FLD ouput eff is de asserted of define VD_FIELD1_YSTAR N line on which FLD is de asserted define VD FIELD1 XSTAR 360 pixel on the first line of Fieldl on which FLD ouput is asserted Fy define VD FIELD1 YSTAR 263 line on which FLD is asserted A LA Define field bit VD FBIT reg values X define VD FBIT CLR 4 first line with an EAV with F 0 indicating Field 1 display define VD FBIT SET 266 firs
332. y 1Cb 32 Cr t 1Cre 17Cret 17Crg 1Cr 32 Figure 3 14 1 2 Scaled Chrominance Resampled Filtering m T a b C d e fg h i j k input samples V O WO EO G9 O EO XO ama o TEC Q X Q Q 74 O O pa O capture results Dv 3Yg 32Y 70Yg 32Yp 3Yj 128 Luma Y 7 Chroma Cb Cr sample samples P P Gb 1Cbg 17Cbe 17Cbg 1Cb 32 Cr 1Crc 17Cre 17Crg 1Cr 32 Note that because input scaling is limited to 4 true CIF horizontal resolution is not achieved if the full BT 656 horizontal line 720 pixels is captured A CIF size line can be captured by selecting a 704 pixel sized window within the BT 656 line This window size and location on the line are programmed using the VCXSTART n and VCXSTOPn bits Note that when 7 scaling is selected horizontal timing applies to the incoming data before scaling The VCTHRLD value applies to the data written into the FIFO after scaling 3 28 Video Capture Port SPRU629 Video Input Filtering 3 5 4 Edge Pixel Replication Because the filters make use of preceding and trailing samples filtering arti facts can occur at the beginning of the BT 656 or Y C active line because no samples exist before the SAV code and at the end of the BT 656 active line because no samples exist after the EAV code In order to minimize artifacts the first m samples after sample 0 where m is the maximum number of preceding samples used by any of the filters are mir
333. y Port SPRU629 Video Display Registers Table 4 20 Video Display Threshold Register VDTHRLD Field Descriptions Description Bit fieldt symvalt Value BT 656 and Y C Mode Raw Data Mode 31 26 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 25 16 VDTHRLD2 OF value 0 3FFh Field 2 threshold Whenever Field 2 threshold Whenever there are atleast VDTHRLD there are at least VDTHRLD doublewords of space in the doublewords of space in the Y display FIFO a new Y display FIFO a new Y DMA DMA event may be event may be generated generated Whenever there are at least 5 VDTHRLD doublewords of space in the Cb or Cr display FIFO a new Cb or Cr DMA event may be generated 15 12 INCPIX OF value 0 Fh Not used FPCOUNT is incremented every INCPIX output clocks 11 10 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 9 0 VDTHRLD1 OF value O SFFh Field 1 threshold Whenever Field 1 threshold Whenever there are at least VDTHRLD doublewords of space in the Y display FIFO a new Y DMA event may be generated Whenever there are at least 2 VDTHRLD doublewords of space in the Cb or Cr display FIFO a new Cb or Cr DMA event may be generated t For CSL implementation use the notation VP VDTHRLD field symval SPRU629 Video Display Port there are at least VDTHRLD doublewords of space i

Texas Instruments TMS320C64x DSP User's Manual

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