Texas Instruments TMS320C645X User's Manual
Contents
1. Direction Register DIR Field Descriptions 0 0000 Output Data Register OUT DATA Field Descriptions cece eee eee Set Data Register SET DATA Field Descriptions 0000 e eens Clear Data Register CLR DATA Field Descriptions a Input Data Register IN DATA Field Descriptions a Set Rising Edge Interrupt Register SET RIS TRIG Field Descriptions Clear Rising Edge Interrupt Register CLR RIS TRIG Field Descriptions Set Falling Edge Interrupt Register SET FAL TRIG Field Descriptions Clear Falling Edge Interrupt Register CLR FAL TRIG Field Descriptions ONoOoaRWD i O aah N SPRU724 General Purpose Input Output GPIO 7 This page is intentionally left blank General Purpose Input Output GPIO SPRU724 General Purpose Input Output GPIO 1 Overview SPRU724 This document describes the general purpose input output GPIO peripheral in the digital signal processors DSPs of the TMS320C645x DSP family The general purpose input output GPIO peripheral provides dedicated general purpose pins that can be configured as either inputs or outputs When configured as an output you can write to an internal register to control the state driven on the output pin When configured as an input you can detect the state of the input by reading the state of an internal register2. 31 16 R 0 14 12 11 IN15 IN14 IN13 IN12 IN11 IN10 Kila R 0 R 0 R 0 R 0 R 0 R 0 R 0 7 6 5 4 3 2 1 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 Legend R Read only R W Read Write n value after reset Table 8 Input Data Register IN DATA Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 0 INn Returns the status of the corresponding GPn pin SPRU724 General Purpose Input Output GPIO 21 Registers 5 7 Set Rising Edge Interrupt Register SET_RIS_ TRIG The GPIO rising trigger register RIS_TRIG configures the edge detection logic to trigger GPIO interrupts and EDMA events on the rising edge of GPIO signals Setting a bit to 1 in RIS_TRIG causes the corresponding GPIO interrupt and EDMA event GPINTn to be generated on the rising edge of GPn RIS_TRIG is not directly accessible by the CPU it must be configured using the GPIO set rising trigger and clear rising trigger registers The GPIO set rising trigger register SET_RIS_TRIG is shown in and described in lable 9 Writing a 1 to a bit of SET RIS TRIG sets the corresponding bit in RIS_TRIG Writing a O has no effect Reading SET_RIS_TRIG returns the value in RIS TRIG Figure 9 Set Rising Edge Interrupt Register SET RIS TRIG 31 16 R 0 15 14 13 12 11 10 9 8 SETRIS15 SETRIS14 SETRIS13 SETRIS12 SETRIS11 SETRIS10 SETRIS9 SETRIS8 R W 0 R W
3. Index interrupt generation interrupts notational conventions overview 9 registers related documentation from Texas Instruments E trademarks General Purpose Input Output GPIO 27
4. Clear Data Register CLR_DATA 20 ees 5 6 Input Data Register IN DATA 2 22 20 ene ee 5 7 Set Rising Edge Interrupt Register SET RIS TRIG aa 5 8 Clear Rising Edge Interrupt Register CLR RIS TRIG 2 0020005 5 9 Set Falling Edge Interrupt Register SET FAL TRIG 0a 5 10 Clear Falling Edge Interrupt Register CLR FAL TRIG a SPRU724 General Purpose Input Output GPIO 5 Figures TMS320C645x DSP Block Diagram 0 0 tenes GPIO Peripheral Block Diagram 0 00 ccc cece tenet eee eee Interrupt Per Bank Enable Register BINTEN 0 00 cece eee eee eee Direction Register DIR AA eee nee eee Output Data Register OUT_DATA 2 Set Data Register SET DATA 22 2222 2 tenet ene enenes Clear Data Register CLR_DATA 0 Input Data Register IN DATA 2 22 2200 eet teens Set Rising Edge Interrupt Register SET RIS TRIG 020 c eee e eens Clear Rising Edge Interrupt Register CLR_RIS_TRIG Set Falling Edge Interrupt Register SET _FAL_TRIG 000 cece eee eee Clear Falling Edge Interrupt Register CLR_FAL_TRIG ONoOoaRWD i o O 4 NI 6 General Purpose Input Qutput GPIO SPRU724 Tables GPIO Interrupt and EDMA Event Configuration Options aaa GPIO Registe a sa Dinaan ad fete bil vend este ew ieee ee hee ade ede Interrupt Per Bank Enable Register BINTEN Field Descriptions
5. RIS_ TRIG Figure 10 Clear Rising Edge Interrupt Register CLR_RIS_TRIG 31 16 Reserved R 0 14 13 12 11 10 9 8 15 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 4 3 2 1 0 7 6 5 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Legend R Read only R W Read Write n value after reset Table 10 Clear Rising Edge Interrupt Register CLR_RIS_TRIG Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 0 CLRRISn Writing a 1 disables rising edge detection for the corresponding GPn pin Reading this register returns the state of the RIS_TRIG register 0 No effect 1 Clears the corresponding bit in RIS_TRIG SPRU724 General Purpose Input Output GPIO 23 Registers 5 9 Set Falling Edge Interrupt Register SET_FAL_TRIG The GPIO falling trigger register FAL_TRIG configures the edge detection logic to trigger GPIO interrupts and EDMA events on the falling edge of GPIO signals Setting a bit to 1 in FAL_TRIG causes the corresponding GPIO interrupt and EDMA event GPINTn to be generated on the falling edge of GPn FAL_TRIG is not directly accessible by the CPU it must be configured using the GPIO set falling trigger and clear falling trigger registers The GPIO set falling trigger register SET_FAL_TRIG is shown in and described in Table 11 Writing a 1 to a bit of SET_FAL_TRIG sets the corresp
6. data register CLR_DATA is shown in and described in CLR_DATA provides an alternate means of driving GPIO outputs low Writing a 1 to a bit of CLR_DATA clears the corresponding bit in OUT_DATA Writing a O has no effect Reading CLR_DATA returns the contents of OUT_DATA Figure 7 Clear Data Register CLR DATA 31 16 R 0 15 14 13 12 11 10 9 8 CLR15 CLR14 CLR13 CLR12 CLR11 CLR10 CLR9 CLR8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 CLR7 CLR6 CLR5 CLR4 CLR3 CLR2 CLR1 CLRO R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Legend R Read only R W Read Write n value after reset Table 7 Clear Data Register CLR DATA Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 0 CLRn Writing 1 clears the corresponding bit the OUT_DATA register Reading this register returns the contents of the OUT_DATA register Writing a 0 has no effect 0 No effect 1 Clears the corresponding bit in OUT_DATA 20 General Purpose Input Output GPIO SPRU724 Registers 5 6 Input Data Register IN DATA The GPIO input data register IN DATA reflects the state of the GPIO pins The IN DATA register is shown in and described in Table 8 When read IN DATA returns the state of the GPIO pins regardless of the state of the corresponding bits in the DIR and OUT DATA registers Figure 8 Input Data Register IN DATA
7. 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 SETRIS7 SETRIS6 SETRIS5 SETRIS4 SETRIS3 SETRIS2 SETRIS1 SETRISO R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Legend R Read only R W Read Write n value after reset Table 9 Set Rising Edge Interrupt Register SET_RIS_TRIG Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 0 SETRISn Writing a 1 enables the rising edge detection for the corresponding GPn pin Reading this register returns the state of the RIS_TRIG register 0 No effect 1 Sets the corresponding bit in RIS_TRIG 22 General Purpose Input Output GPIO SPRU724 Registers 5 8 Clear Rising Edge Interrupt Register CLR_RIS_TRIG The GPIO rising trigger register RIS_TRIG configures the edge detection logic to trigger GPIO interrupts and EDMA events on the rising edge of GPIO signals Setting a bit to 1 in RIS_TRIG causes the corresponding GPIO interrupt and EDMA event GPINTn to be generated on the rising edge of GPn RIS_TRIG is not directly accessible by the CPU it must be configured using the GPIO set rising trigger and clear rising trigger registers The GPIO clear rising trigger register CLR_RIS_TRIG is shown in and described in Table 19 Writing a 1 to a bit of CLR_RIS_TRIG clears the corresponding bit in RIS TRIG Writing a 0 has no effect Reading CLR_RIS_TRIG returns the value in
8. FAL TRIG Clear Falling Edge Interrupt Register 6 9 SPRU724 General Purpose Input Output GPIO 15 Registers 5 1 Interrupt Per Bank Enable Register BINTEN To use the GPIO pins as sources for CPU interrupts and EDMA events bit 0 in the bank interrupt enable register BINTEN must be set BINTEN is shown in and described in Table 3 Figure 3 Interrupt Per Bank Enable Register BINTEN 31 1 0 R 0 RW 0 Legend R Read only R W Read Write n value after reset Table 3 Interrupt Per Bank Enable Register BINTEN Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 EN Enables all GPIO pins as interrupt sources to the DSP CPU 0 Disables GPIO interrupts 1 Enables GPIO interrupts 16 General Purpose Input Output GPIO SPRU724 Registers 5 2 Direction Register DIR The GPIO direction register DIR determines if a given GPIO pin is an input or an output The GPDIR is shown in and described in lable 4 By default all the GPIO pins are configured as input pins When GPIO pins are configured as output pins the GPIO output buffer drives the GPIO pin If it is necessary to place the GPIO output buffer in a high impedance state the GPIO pin must be configured as an input pin DIRn 0 At reset GPIO pins default to input mode Figure 4 Direction Register DIR 31 16 R 0 15 14 13 12 11 10 9 8 D
9. IR15 DIR14 DIR13 DIR12 DIR11 DIR10 DIR9 DIRS R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 7 6 5 4 3 2 1 0 DIR7 DIR6 DIRs DIR4 DIR3 DIR2 DIRI DIRO R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 R W 1 Legend R Read only R W Read Write n value after reset Table 4 Direction Register DIR Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 0 DIRn Controls the direction of the GPn pin 0 GPn pin configured as output pin 1 GPn pin configured as input pin SPRU724 General Purpose Input Output GPIO 17 Registers 5 3 Output Data Register OUT_DATA The GPIO output data register OUT DATA indicates the value to be driven on a given GPIO output pin The OUT DATA registers are shown in and described in Table 5 Figure 5 Output Data Register OUT DATA 31 16 R 0 15 14 13 12 11 10 9 8 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 OUT7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 OUTO R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Legend R Read only R W Read Write n value after reset Table 5 Output Data Register OUT DATA Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 0 OUTn Controls the drive state of the c
10. In addition the GPIO peripheral can produce CPU interrupts and EDMA synchronization events in different interrupt event generation modes shows the GPIO peripheral in the TMS320C645x DSP shows the GPIO peripheral block diagram General Purpose Input Output GPIO 9 Overview Figure 1 TMS320C645x DSP Block Diagram LIP cache SRAM L2 memory L1 program memory controller Advanced controller overit Cache control triggering Cache Bandwidth management AET control Memory protection DDR2 memory controller Bandwidth management C64x CPU Memory Instruction fetch protection SPLOOP buffer 16 32 bit instruction dispatch Instruction decode Data path A Data path B Dewy External memory controller Switched central resource E Register file A Register file B eripherals perp Master DMA L1 data memory controller Interrupt EDMA Slave Cache control and exception controller DMA r controller Memory protection Bandwidth management Boot cache SRAM Some GPIO pins are MUXed with other device pins Refer to the device specific datasheet for details on specific MUXing and for the availability of the register bits GPINT 0 15 are all available as synchronization events to the EDMA controller and as interrupt sources to the CPU 10 General Purpose Input Output GPIO SPRU724 Overview Figure 2 G
11. PIO Peripheral Block Diagram GPIO peripheral Data input output Set data SET_DATA Output data OUT_DATA K GPn Peripheral clock Clear data CLR DATA CPU 6 Input V Synchronization data IN_DATA logic EDMA event and interrupt Interrupt and generation Edge detection EDMA event logic GPINTn Set rising edge trigger SET_RIS_TRIG Rising edge trigger RIS_TRIGS Clear rising edge trigger CLR_RIS_TRIG Set falling edge trigger SET_FAL_TRIG Falling edge tiog r FAL_TRIGS Clear falling edge trigger CLR FAL TRIG t Some of the GPn pins are MUXed with other device signals Refer to the device specific datasheet for details All GPINTn can be used as CPU interrupts and synchronization events to the EDMA controller The RIS TRIG and FAL TRIG registers are internal to the GPIO module and are not visible to the CPU SPRU724 General Purpose Input Output GPIO 11 GPIO Function 2 GPIO Function You can independently configure each GPIO pin GPn as either an input or an output using the GPIO direction registers The GPIO direction register DIR specifies the direction of each GPIO signal Logic 0 indicates the GPIO pin is configured as output and logic 1 indicates input When configured as output writing a 1 to a bit in the set data register drives the corresponding GPn to a logic high state Writing a 1 to a bit in the clear data register drives the corresponding GPn to a logic low
12. RIG register sets the corresponding bit on the RIS_TRIG register Writing 1 to a bit of CLR_RIS_TRIG register clears the corresponding bit on the RIS_TRIG register Writing to SET_FAL_TRIG and CLR_FAL_TRIG works the same way on the FAL_TRIG register General Purpose Input Output GPIO 13 Interrupt and Event Generation Interrupts and Events Reading the SET_RIS_TRIG or CLR_RIS_TRIG register returns the value of RIS TRIG register Reading from SET FAL TRIG and CLR_FAL_TRIG register returns the value of FAL TRIG register To use the GPIO pins as sources for CPU interrupts and EDMA events bit 0 in the bank interrupt enable register BINTEN must be set to 1 4 Emulation Halt Operation The GPIO peripheral is not affected by emulation halts 14 General Purpose Input Output GPIO SPRU724 Registers 5 Registers The GPIO peripheral is configured through the registers listed in Table 2 See the device specific datasheet for the memory address of these registers Table 2 GPIO Registers Offsets Acronym Register Name Section 0008 BINTEN Interrupt Per Bank Enable Register 6 1 0010 DIR Direction Register 6 3 0014 OUT DATA Output Data Register 5 3 0018 SET_DATA Set Data Register 6 4 001C CLR DATA Clear Data Register bo 0020 IN_DATA Input Data Register 6 6 0024 SET_RIS_TRIG Set Rising Edge Interrupt Register 6 7 0028 CLR RIS TRIG Clear Rising Edge Interrupt Register 6 3 002C SET FAL TRIG Set Falling Edge Interrupt Register 6 3 0030 CLR
13. TMS320C645x DSP General Purpose Input Output GPIO User s Guide Literature Number SPRU724 December 2005 9 TEXAS INSTRUMENTS IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment Tl warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards Tl does not warrant or represent that any license either express or implied is granted under any TI patent right copyri
14. es of the GPIO signal The edge detection logic is synchronized to the GPIO peripheral clock The direction of the GPIO pin does not need to be input when using the pin to generate the interrupt and EDMA event When the GPIO pin is configured as input transitions on the pin trigger interrupts and EDMA events When the GPIO pin is configured as output software can toggle the GPIO output register to change the pin state and in tum trigger the interrupt and EDMA event Two internal registers RIS TRIG and FAL TRIG specify which edge of the GPn signal generates an interrupt and EDMA event Each bit in these two registers corresponds to a GPn pin Table 1 describes the CPU interrupt and EDMA event generation of GPn pin based on the bit settings of the RIS_TRIG and FAL_TRIG registers GPIO Interrupt and EDMA Event Configuration Options RIS TRIG bitn FAL TRIG bitn CPU Interrupt and EDMA Event Generation 0 0 SPRU724 0 GPINTn interrupt and EDMA event is disabled 1 GPINTn interrupt and EDMA event is triggered on falling edge of GPn signal 0 GPINTn interrupt and EDMA event is triggered on rising edge of GPn signal 1 GPINTn interrupt and EDMA event is triggered on both rising and falling edge of GPn signal RIS_TRIG and FAL_TRIG are not directly accessible or visible to the CPU These registers are accessed indirectly through four registers SET_RIS_TRIG CLR_RIS_ TRIG SET_FAL_TRIG and CLR_FAL_TRIG Writing 1 to a bit on the SET RIS T
15. ght mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www t
16. i com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2005 Texas Instruments Incorporated Preface Read This First About This Manual This document describes the general purpose input output GPIO peripheral in the digital signal processors DSPs of the TMS320C645x DSP family Notational Conventions This document uses the following conventions O Hexadecimal numbers are shown with the suffix h For example the following number is 40 hexadecimal decimal 64 40h When referencing specific register bits the X in the register bit name is replaced with the bit number for example GPXDIR refers to the bit field of the GPIO direction register and GP15DIR refers to bit 15 of GPDIR D Registers in this document are shown in figures and described in tables m Each register figure shows a rectangle divided into fields that represent the fields of the register Each field is labeled with its bit name its beginning and ending bit numbers above and its read write properties bel
17. nfigured using the GPIO set falling trigger and clear falling trigger registers The GPIO clear falling trigger register CLR FAL TRIG is shown in Figure 11 and described in Writing a 1 to a bit of CLR_FAL_TRIG clears the corresponding bit in FAL TRIG Writing a O has no effect Reading CLR_FAL_TRIG returns the value in FAL_TRIG Figure 12 Clear Falling Edge Interrupt Register CLR_FAL_TRIG 31 16 Reserved R 0 14 12 11 10 9 8 15 13 CLRFAL15 CLRFAL14 CLRFAL13 CLRFAL12 CLRFAL11 CLRFAL10 CLRFAL9 CLRFAL8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 4 3 2 7 6 5 1 0 CLRFAL7 CLRFAL6 CLRFAL5 CLRFAL4 CLRFAL3 CLRFAL2 CLRFAL1 CLRFALO R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Legend R Read only R W Read Write n value after reset Table 12 Clear Falling Edge Interrupt Register CLR_FAL_TRIG Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as zero A value written to this field has no effect 15 0 CLRFALn Writing a 1 disables falling edge detection for the corresponding GPn pin Reading this register returns the state of the FAL_TRIG register 0 No effect 1 Clears the corresponding bit in FAL_TRIG SPRU724 General Purpose Input Output GPIO 25 This page is intentionally left blank 26 General Purpose Input Output GPIO SPRU724 block diagram C645x DSP GPIO event generation events function SPRU724
18. onding bit in FAL_TRIG Writing a O has no effect Reading SET_FAL_TRIG returns the value in FAL_TRIG Figure 11 Set Falling Edge Interrupt Register SET FAL TRIG 31 16 R 0 15 14 13 12 11 10 9 8 SETFAL15 SETFAL14 SETFAL13 SETFAL12 SETFAL11 SETFAL10 SETFAL9 SETFAL8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 SETFAL7 SETFAL6 SETFAL5 SETFAL4 SETFAL3 SETFAL2 SETFAL1 SETFALO R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Legend R Read only R W Read Write n value after reset Table 11 Set Falling Edge Interrupt Register SET_FAL_TRIG Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as zero A value written to this field has no effect 15 0 SETFALn Writing a 1 enables the falling edge detection for the corresponding GPn pin Reading this register returns the state of the FAL TRIG register 0 No effect 1 Sets the corresponding bit in FAL TRIG 24 General Purpose Input Output GPIO SPRU724 Registers 5 10 Clear Falling Edge Interrupt Register CLR_FAL_TRIG The GPIO falling trigger register FAL_TRIG configures the edge detection logic to trigger GPIO interrupts and EDMA events on the falling edge of GPIO signals Setting a bit to 1 in FAL_TRIG causes the corresponding GPIO interrupt and EDMA event GPINTn to be generated on the falling edge of GPn FAL_TRIG is not directly accessible by the CPU it must be co
19. orresponding GPn pin These bits do not affect the state of the pin when the pin is configured as an input Reading these bits returns the value of this register not the state of the pin 18 General Purpose Input Output GPIO SPRU724 Registers 5 4 Set Data Register SET_DATA The GPIO set data register SET_DATA is shown in and described in Table 6 SET DATA provides an alternate means of driving GPIO outputs high Writing a 1 to a bit of SET_DATA sets the corresponding bit in OUT_DATA Writing a 0 has no effect Reading SET_DATA returns the contents of OUT_DATA Figure 6 Set Data Register SET DATA 31 16 R 0 15 14 13 12 11 10 9 8 SET15 SET14 SET13 SET12 SET11 SET10 SET9 SET8 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 SET7 SET6 SET5 SET4 SET3 SET2 SET1 SETO R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 Legend R Read only R W Read Write n value after reset Table 6 Set Data Register SET DATA Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 0 SETn Writing 1 sets the corresponding bit the OUT_DATA register Reading this register returns the contents of the OUT_DATA register Writing a 0 has no effect 0 No effect 1 Sets the corresponding bit in OUT_DATA SPRU724 General Purpose Input Output GPIO 19 Registers 5 5 Clear Data Register CLR_DATA The GPIO clear
20. ow A legend explains the notation used for the properties m Reserved bits in a register figure designate a bit that is used for future device expansion Related Documentation From Texas Instruments The following documents describe the C6000 devices and related support tools Copies of these documents are available on the Internet at www ti com Tip Enter the literature number in the search box provided at www ti com TMS320C6000 CPU and Instruction Set Reference Guide literature number SPRU189 gives an introduction to the TMS320C62x and TMS320C67x DSPs development tools and third party support TMS320C6455 Technical Reference literature number SPRU965 gives an introduction to the TMS320C6455 DSP and discusses the application areas that are enhanced SPRU724 General Purpose Input Output GPIO 3 Related Documentation From Texas Instruments Trademarks Trademarks TMS320C6000 Programmer s Guide literature number SPRU198 describes ways to optimize C and assembly code for the TMS320C6000 DSPs and includes application program examples TMS320C6000 Code Composer Studio Tutorial literature number SPRU301 introduces the Code Composer Studio integrated develop ment environment and software tools Code Composer Studio Application Programming Interface Reference Guide literature number describes the Code Composer Studio application programming interface API which allows you to program custom plug in
21. s for Code Composer TMS320C64x Megamodule Reference Guide literature number describes the TMS320C64x digital signal processor DSP megamodule Included is a discussion on the internal direct memory ac cess IDMA controller the interrupt controller the power down control ler memory protection bandwidth management and the memory and cache TMS320C6000 DSP Peripherals Overview Reference Guide literature number SPRU190 provides a brief description of the peripherals avail able on the TMS320C6000 digital signal processors DSPs TMS320C6455 Chip Support Libraries CSL literature number SPRC234 is a download with the latest chip support libraries Code Composer Studio C6000 C62x C64x C67x TMS320C6000 TMS320C62x TMS320C64x TMS320C67x and VelociTI are trademarks of Texas Instruments General Purpose Input Output GPIO SPRU724 Contents T SOVONVIOW aa pete ae oat es wean nr a re ew ese tie eae oe ee eet ANG 2 GPIO FUNCION Ha eae ee eee ad oe te eee o meted ade 3 Interrupt and Event Generation 222 4 KA 4 Emulation Halt Operation AA AA eee 5 JREgISLEES N3 N INN nce emandeln dee needed AGILA AR LPG ANAN AABANG 5 1 Interrupt Per Bank Enable Register BINTEN 220 cee eeeeee ee ees 5 2 Direction Register DIR erita neriie tian GEEAE EEA 5 3 Output Data Register OUT DATA 0 cece cece eens 5 4 Set Data Register SET DATA 22222 ccc eee eens 5 5
22. state The output state of each GPn can also be directly controlled by writing to the output data register For example to set GP8 to a logic high state the software can perform one of the following Write 0x100 to the SET DATA register 1 Read in OUT DATA register change the eighth bit to 1 and write the new value back to OUT_DATA To set GP8 to a logic low state the software can perform one of the following Write 0x100 to the CLR DATA register 1 Read in OUT DATA register change the eighth bit to O and write the new value back to OUT_DATA Note that writing a 0 to bits in the set data and clear data registers does not affect the GPIO pin state Also for GPIO pins configured as input writing to the set data clear data or output data registers does not affect the pin state For a GPIO pin configured as input reading the input data register IN_DATA will return the pin state Reading the SET_DATA register or the CLR_DATA data register will return the value in OUT_DATA not the actual pin state The pin state is available by reading the input data register 12 General Purpose Input Output GPIO SPRU724 Interrupt and Event Generation 3 Interrupt and Event Generation Table 1 Each GPIO pin GPn can be configured to generate a CPU interrupt GPINTn and a synchronization event to the EDMA controller GPINTn The interrupt and EDMA event can be generated on the rising edge falling edge or on both edg
Download Pdf Manuals
Related Search