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Texas Instruments TMS320C6455 User's Manual

1. 4 5 SDRAM Timing 1 Register SDTIM1 The SDRAM timing 1 register SDTIM1 configures the DDR2 memory controller to meet many of the AC timing specification of the DDR2 memory Note that DDR2CLKOUT is equal to the period of the DDR2CLKOUT signal For information on the appropriate values to program each field see the DDR2 memory section of the device specific data manual The bit fields in the SDTIM1 register are only writeable when the TIMUNLOCK bit of the SDRAM Configuration register SDCFG is unlocked The SDTIM1 is shown in Figure 23 and described in Table 22 Figure 23 SDRAM Timing 1 Register SDTIM1 31 25 24 22 21 19 18 16 T RFC T RP T RCD T WR R W 0x3F R W 0x7 R W 0x7 R W 0x7 15 11 10 6 5 3 2 1 0 T RAS T RC T RRD Rsvd T WTR R W 0x1F R W 0x1F R W 0x7 R 0 R W 0x3 LEGEND R W Read Write R Read only n value after reset Table 22 SDRAM Timing 1 Register SDTIM1 Field Descriptions Bit Field Value Description 31 25 T_RFC These bits specify the minimum number of DDR2CLKOUT cycles from a refresh or load mode command to a refresh or activate command minus one The value for these bits can be derived from the t AC timing parameter in the DDR2 memory section of the device specific data manual Calculate using this formula T_RFC t DDR2CLKOUT 1 24 22 These bits specify the minimum number of DDR2CLKOUT cycles from a precharge command to a refresh or activate command minus 1
2. sseeseesen III Hn 48 List of Figures SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated l TEXAS INSTRUMENTS www ti com List of Tables 1 DDR2 Memory Controller Signal De SCriptiONnS 0 cceceeeeee cece eee eee eee eee nnn I I I nem nen 12 2 DDR2 SDRAM Gommarids x3 exeun Eaa EEA En a aAa eies RERRERERR DANA EAE T3 3 Truth Table for DDR2 SDRAM Commands ceseesseeeseseeeee enne n enne nenne nenne ener 13 4 Addressable Memory Ranges eeeseeeeieieieiereiise e nnna enne hme a anna nemen enne nma nme 20 5 Bank Configuration Register Fields for Address Mapping 0cseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeaes 21 6 DDR2 Memory Controller FIFO Description sseeseeeeeeeeenee nnn en Innen nen nne nnn 24 7 Refresh Urgency bevelsi iissciasc tese ere ono Durw ipe Ropa va e Rap EUR EE aEU Dada eMa E DU M DITE MEAN MEM DUF ADEM Da MEE er 8 Device and DDR2 Memory Controller Reset Relationship eesseeeeeeen nm 28 9 DDR2 SDRAM Mode Register Configuration 0ceeceeee eee ee eee ee ee eee e eee eee eee e nese ne n nem nnn nenne 29 10 DDR2 SDRAM Extended Mode Register 1 Configuration 0 ceceeee ence eee eeeeee sees eeeeeeeeeeeeeeeeeneeeaees 29 11 SDCFG CONG UAC mec D 35 12 DDR2 Memory Refresh Specification ccceceeeeeee cece eee eeeeeeeeeeeeeeeeeeeeeeaeeesee
3. T WTR t DDR2CLKOUT 1 SPRU970G December 2005 Revised June 2011 C6455 C6454 DDR2 Memory Controller 45 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated I TEXAS INSTRUMENTS DDR2 Memory Controller Registers www ti com 4 6 SDRAM Timing 2 Register SDTIM2 Like the SDRAM timing 1 register SDTIM1 the SDRAM timing 2 register SDTIM2 also configures the DDR2 memory controller to meet the AC timing specification of the DDR2 memory For information on the appropriate values to program each field see the DDR2 memory section of the device specific data manual The bit fields in the SDTIM2 register are only writeable when the TIMUNLOCK bit of the SDRAM Configuration register SDCFG is unlocked SDTIM2 is shown in Figure 24 and described in Table 23 Figure 24 SDRAM Timing 2 Register SDTIM2 31 25 24 23 22 16 Reserved T_ODT T_XSNR R 0x0 R W 0x3 R W 0x7F 15 8 7 5 4 0 T_XSRD T_RTP T_CKE R W 0OxFF R W 0x7 R W 0x1F LEGEND R W Read Write R Read only n value after reset x value is indeterminate after reset Table 23 SDRAM Timing 2 Register SDTIM2 Field Descriptions Bit Field Value Description 31 25 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 24 23 T ODT Minimum number of DDR clock cycles from ODT enable to write data driven for DDR2 SD
4. C6455 C6454 DDR2 Memory Controller Copyright 2005 2011 Texas Instruments Incorporated 33 I TEXAS INSTRUMENTS Using the DDR2 Memory Controller www ti com Figure 18 Connecting to Two 8 Bit DDR2 SDRAM Devices DDR2CLKOUT DDR2CLKOUT DSDCKE DDR2 DCEO sere DSDWE DSDRAS DSDCAS DSDDQMO DSDDQSO DSDDQSO DBA 2 0 DEA 13 0 DED 7 0 DSDDOM1 DSDDOS1 DSDDOS1 DED 15 8 ODTO ODT1 Vaerssr DDRSLRATE DSDDQGATEO DSDDQGATE 1 DSDDQGATE2 DSDDQGATE3 RDQS RDQS BA 2 0 A 13 0 DQ 7 0 ODT VReF A These pins are used as a timing reference during memory reads For routing rules see the device specific data manual 34 C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Using the DDR2 Memory Controller 3 2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications The DDR2 memory controller allows a high degree of programmability for shaping DDR2 accesses This provides the DDR2 memory controller with the flexibility to interface with a variety of DDR2 devices By programming the SDRAM Configuration Register SDCFG SDRAM Refresh Control Register SDRFC SDRAM Timing 1 Register SDTIM1 and SDRAM Timing 2 Register S
5. Revised June 2011 f Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated J TEXAS Preface SPRU970G December 2005 Revised June 201 1 NSTRUMENTS Read This First About This Manual This document describes the DDR2 memory controller in the TMS320C6455 C6454 digital signal processors DSPs Notational Conventions This document uses the following conventions e Hexadecimal numbers are shown with the suffix h For example the following number is 40 hexadecimal decimal 64 40h Registers in this document are shown in figures and described in tables Each register figure shows a rectangle divided into fields that represent the fields of the register Each field is labeled with its bit name its beginning and ending bit numbers above and its read write properties below A legend explains the notation used for the properties Reserved bits in a register figure designate a bit that is used for future device expansion Related Documentation From Texas Instruments The following documents describe the C6000 devices and related support tools Copies of these documents are available on the Internet Tip Enter the literature number in the search box provided at www ti com SPRU189 TMS320C6000 DSP CPU and Instruction Set Reference Guide Describes the CPU architecture pipeline instruction set and interrupts for the TMS320C6000 digital signal processors DSPs SPRU198 TMS320C
6. requirement 3 2 3 Configuring SDRAM Timing Registers SDTIM1 and SDTIM2 The SDRAM timing 1 register SDTIM1 and SDRAM timing 2 register SDTIM2 configure the DDR2 memory controller to meet the data sheet timing parameters of the attached DDR2 device Each field in SDTIM1 and SDTIM2 corresponds to a timing parameter in the DDR2 data sheet specification Table 14 and Table 15 display the register field name and corresponding DDR2 data sheet parameter name along with the data sheet value These tables also provide a formula to calculate the register field value and displays the resulting calculation Each of the equations include a minus 1 because the register fields are defined in terms of DDR2 clock cycles minus 1 See Section 4 5 and Section 4 6 for more information Table 14 SDTIM1 Configuration DDR2 SDRAM Register Field Data Sheet Data Sheet Formula Register Field Must Field Name Parameter Name Description Value ns Be 2 Value T RFC trrc Refresh cycle time 127 5 tare fpona cud 1 31 T RP tap Precharge command to 15 tae X fppga cu 1 3 refresh or activate command T RCD trepo Activate command to 15 taco fopre_cix 1 3 read write command T WR twn Write recovery time 15 twr fopre cu 1 3 T RAS tras Active to precharge 45 trac fopra cik 1 11 command T_RC tac Activate to Activate 60 tac fopre cu 1 14 command in the same bank T RRD tarp Activate to Activate 10 4 tig 2 4 Eta
7. SDRAM Timing Register 2 SDTIM2 A write to this bit causes the DDR2 Memory Controller to start the SDRAM initialization sequence 0 Register fields in the SDTIM1 and SDTIM2 registers may not be changed Register fields in the SDTIM1 and SDTIM2 registers may be changed 14 NM DDR2 data bus width A write to this bit will cause the DDR2 Memory Controller to start the SDRAM initialization sequence 0 32 bit bus width 16 bit bus width 13 12 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect SPRU970G December 2005 Revised June 2011 C6455 C6454 DDR2 Memory Controller 41 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated DDR2 Memory Controller Registers I TEXAS INSTRUMENTS www ti com Table 20 SDRAM Configuration Register SDCFG Field Descriptions continued Bit Field Value Description 11 9 CL a A U N CAS latency The value of this field defines the CAS latency to be used when accessing connected SDRAM devices A write to this field will cause the DDR2 Memory Controller to start the SDRAM initialization sequence This field is writeable only when the TIMUNLOCK bit is unlocked Values 0 1 6 and 7 are reserved for this field CAS latency of 2 CAS latency of 3 CAS latency of 4 CAS latency of 5 8 7 Reserved Reserved The reserved bit location is always read
8. SR bit in SDRFC is cleared While in the self refresh state if a request for a memory access is received the DDR2 memory controller services the memory access request returning to the self refresh state upon completion The DDR2 memory controller will not exit the self refresh state whether from a memory access request or from clearing the SR bit until T CKE 1 cycles have expired since the self refresh command was issued The value of T CKE is defined in the SDRAM timing 2 register SDTIM2 After exiting from the self refresh state the DDR2 memory controller will not immediately start using commands Instead it will wait T XSNR 1 clock cycles before issuing non read commands and T XSRD 41 clock cycles before issuing read commands The SDRAM timing 2 register SDTIM2 programs the values of T XSNR 1 and T_XSRD 1 Reset Considerations The DDR2 memory controller can be reset through a hard reset or a soft reset A hard reset resets the state machine the FIFOs and the internal registers A soft reset only resets the state machine and the FIFOs A soft reset does not reset the internal registers except for the interrupt registers Register accesses cannot be performed while either reset is asserted The DDR2 memory controller hard and soft reset are derived from device level resets C6455 C6454 devices have several types of device level resets power on reset warm reset max reset system reset and CPU reset Table 8 shows the relations
9. TEXAS INSTRUMENTS www ti com Figure 11 and Figure 12 show how the logical address bits map to the row column bank and chip select bits all combinations of IBANK and PAGESIZE values Note that the upper three bits of the logical address cannot be used for memory addressing as the DDR2 memory controller has a maximum addressable memory range of 512M bytes The DDR2 memory controller address pins provide the row and column address to the DDR2 SDRAM thus the DDR2 memory controller appropriately shifts the logical address during row and column address selection The bank address is driven to the DDR2 SDRAM using the bank address pins The two lower bits of the logical address decode the value of the byte enable pins only used for accesses less than the width of the DDR2 memory controller data bus Figure 11 Logical Address to DDR2 SDRAM Address Map for 32 Bit SDRAM SDCFG Bit Logical Address IBANK PAGESIZE 31 29 28 27 26 25 24 23 22 17 16 15 14 13 12 11 10 9 2 0 0 X X X X X x nrb 14 ncb 8 1 0 X x x x X nrb 14 nbb i ncb 8 2 0 X X X x nrb 14 nbb 2 ncb 8 3 0 X X x nrb 14 nbb 3 ncb 8 0 1 x x x x x nrb 14 ncb 9 1 1 x x x x nrb 14 nbb 1 ncb 9 2 1 X X x nrb 14 nbb 2 ncb 9 3 1 x x nrb 14 nbb 3 ncb 9 0 2 x x x x
10. 1 2 command in a different bank T WTR twrr Write to read command 7 5 twrr X foor cu 1 1 delay 36 C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated l TEXAS INSTRUMENTS www ti com 3 2 4 Using the DDR2 Memory Controller Table 15 SDTIM2 Configuration DDR2 SDRAM Data Register Field Sheet Parameter Data Sheet Formula Register Field Name Name Description Value Field Must Be 2 Value T_ODT taonp taonp Specifies the ODT turn on 2 tex cycles taonp 2 delay T_XSNR tysnr Exit self refresh to a non read 137 5 ns txsna foore cu 1 34 command T_XSRD tysrp Exit self refresh to a read 200 tex cycles txsnp 1 199 command T RTP tarp Read to precharge command 7 5 ns tate X fppg2 ctx 1 1 delay T_CKE teke CKE minimum pulse width 3 tex cycles teke 1 2 Configuring the DDR2 Memory Controller Control Register DMCCTL The DDR2 memory controller control register DMCCTL contains a read latency RL field that helps the DDR2 memory controller determine when to sample read data The RL field should be programmed to a value equal to CAS latency 1 For example if a CAS latency of 4 is used then RL should be programmed to 5 Table 16 DMCCTL Configuration Register Register Field Name Description Value IFRESET Programmed to be out of reset 0 RL Read latency is equal to CAS lat
11. 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Revision History Revision History This revision history highlights the technical changes made to the document in this revision See Additions Modifications Deletions Table 1 Modified Description for DEODT 1 0 Pins Table 10 Modified Descriptions for Bits 6 and 2 Figure 16 Modified ODT pins in figure Figure 17 Modified ODT pins in figure Figure 18 Modified ODT pins in figure NOTE Page numbers for previous revisions may differ from page numbers in the current version SPRU970G December 2005 Revised June 2011 Revision History 49 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and othe
12. I TEXAS INSTRUMENTS DDR2 Memory Controller Registers www ti com 4 8 DDR2 Memory Controller Control Register DMCCTL The DDR2 memory controller control register DMCCTL resets the interface logic of the DDR2 memory controller The DMCCTL is shown in Figure 26 and described in Table 25 Figure 26 DDR2 Memory Controller Control Register DMCCTL 31 16 Reserved R 0x5000 15 6 5 4 3 2 0 Reserved RESET Rsvd Rsvd RL R W 0x0190 R W R W R 0x0 R W 0x7 0x1 0x0 LEGEND R W Read Write R Read only n value after reset Table 25 DDR2 Memory Controller Control Register DMCCTL Field Descriptions Bit Field Value Description 31 6 Reserved Reserved Writes to this register must keep this field at its default value 5 IFRESET DDR2 memory controller interface logic reset The interface logic controls the signals used to communicate with DDR2 SDRAM devices This bit resets the interface logic The status of this interface logic is shown on the DDR2 memory controller status register 0 Release reset Assert reset 4 Reserved Reserved Writes to this register must keep this field at its default value 3 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 2 0 RL Read latency bits These bits must be set equal to the CAS latency 1 48 C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June
13. controller parallel to each other The same peripheral bus is used to write and read data from external memory as well as internal memory mapped registers Table 6 DDR2 Memory Controller FIFO Description Depth 64 Bit FIFO Description Doublewords Command Stores all commands coming from on chip requestors 7 Write Stores write data coming from on chip requestors to 11 memory Read Stores read data coming from memory to on chip 17 requestors 24 C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated l TEXAS INSTRUMENTS www ti com Peripheral Architecture 2 7 1 Figure 15 DDR2 Memory Controller FIFO Block Diagram Command FIFO Command Data Command Scheduler to Memory Write FIFO Write Data to Memory EDMA BUS Read FIFO Read Data from Memory Registers Command Data Command Ordering and Scheduling Advanced Concept The DDR2 memory controller performs command re ordering and scheduling in an attempt to achieve efficient transfers with maximum throughput The goal is to maximize the utilization of the data address and command buses while hiding the overhead of opening and closing DDR2 SDRAM rows Command re ordering takes place within the command FIFO The DDR2 memory controller examines all the commands stored in the command FIFO
14. controller supports the DDR2 SDRAM commands listed in Table 2 Table 3 shows the signal truth table for the DDR2 SDRAM commands Table 2 DDR2 SDRAM Commands Command Function ACTV Activates the selected bank and row DCAB Precharge all command Deactivates precharges all banks DEAC Precharge single command Deactivates precharges a single bank DESEL Device Deselect EMRS Extended Mode Register set Allows altering the contents of the mode register MRS Mode register set Allows altering the contents of the mode register NOP No operation Power Down Power down mode READ Inputs the starting column address and begins the read operation READ with Inputs the starting column address and begins the read operation The read operation is followed by a autoprecharge precharge REFR Autorefresh cycle SLFREFR Self refresh mode WRT Inputs the starting column address and begins the write operation WRT with Inputs the starting column address and begins the write operation The write operation is followed by a autoprecharge precharge Table 3 Truth Table for DDR2 SDRAM Commands DDR2 SDRAM Signals CKE cs RAS CAS WE BA 2 0 A 13 11 9 0 A10 DSDCKE DDR2 Memory Previous Controller Signals Cycles Current Cycle DCEO DSDRAS DSDCAS DSDWE DBA 2 0 DEA 13 11 9 0 DEA 10 ACTV HM H E L H H Bank Row Address DCAB H H i L H L x x H DEAC H H L H H L Bank x L MRS H H L L L
15. may read stale data and therefore receive an incorrect message In order to confirm that a write from master A has landed before a read from master B is performed master A must wait for the write completion status from the DDR2 memory controller before indicating to master B that the data is ready to be read If master A does not wait for indication that a write is complete it must perform the following workaround 1 Perform the required write 2 Perform a dummy write to the DDR2 memory controller module ID and revision register 3 Perform a dummy read to the DDR2 memory controller module ID and revision register 4 Indicate to master B that the data is ready to be read after completion of the read in step 3 The completion of the read in step 3 ensures that the previous write was done For a list of the master peripherals that need this workaround see the device specific data manual 2 8 Refresh Scheduling The DDR2 memory controller issues autorefresh REFR commands to DDR2 SDRAM devices at a rate defined in the refresh rate REFRESH_RATE bit field in the SDRAM refresh control register SDRFC A refresh interval counter is loaded with the value of the REFRESH_RATE bit field and decrements by 1 each cycle until it reaches zero Once the interval counter reaches zero it reloads with the value of the REFRESH_RATE bit Each time the interval counter expires a refresh backlog counter increments by 1 Conversely each time the DDR2 memory
16. nrb 14 ncb 10 1 2 x x x nrb 14 nbb 1 ncb 10 2 2 x x nrb 14 nbb 2 ncb 10 3 2 X nrb 14 nbb 3 ncb 10 0 3 X X x nrb 14 ncb 11 1 3 X x nrb 14 nbb 1 neb 11 2 3 x nrb 14 nbb 2 ncb 11 3 3 X nrb 13 nbb 3 ncb 11 LEGEND nrb number of row address bits ncb number of column address bits nbb number of bank address bits Figure 12 Logical Address to DDR2 SDRAM Address Map for 16 bit SDRAM SDCFG Bit Logical Address IBANK PAGESIZE 31 29 28 27 26 25 24 23 22 2136 15 14 13 12 11 10 9 8 1 0 0 X X x x x x x nrb 14 ncb 8 1 0 X X X X X X nrb 14 nbb 1 ncb 8 2 0 X X X X X nrb 14 nbb 2 ncb 8 3 0 x x x x nrb 14 nbb 3 ncb 8 0 1 X X X X X X nrb 14 ncb 9 1 1 x x x x x nrb 14 nbb 1 ncb 9 2 1 x x x x nrb 14 nbb 2 ncb 9 3 1 X X X nrb 14 nbb 3 ncb 9 0 2 X X X X X nrb 14 ncb 10 1 2 x x x x nrb 14 nbb 1 ncb 10 2 2 x x x nrb 14 nbb 2 ncb 10 3 2 X X nrb 14 nbb 3 ncb 10 0 3 X x x x nrb 14 neb 11 1 3 x x x nrb 14 nbb 1 neb 11 2 3 x x nrb 14 nbb 2 ncb 11 3 3 X nrb 14 nbb 3 ncb 11 LEGEND nrb number of row address bits ncb number of column address bits nbb number of bank address bits 22 Figure 11 shows how the DSP memory map is partitioned into columns rows and banks Note that during a linear access the DDR2 memory controller increments the column address as the logical address increments When the DDR2 memory controller reaches a page row boundary it moves onto the same page row in the next bank This movement continues
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18. to schedule commands to the external memory For each master the DDR2 memory controller reorders the commands based on the following rules Selects the oldest command Aread command is advanced before an older write command if the read is to a different block address 2048 bytes and the read priority is equal to or greater than the write priority NOTE Most masters issue commands on a single priority level Also the EDMA transfer controller read and write ports are considered different masters and thus the above rule does not apply The second bullet above may be viewed as an exception to the first bullet This means that for an individual master all of its commands will complete from oldest to newest with the exception that a read may be advanced ahead of an older lower or equal priority write Following this scheduling each master may have one command ready for execution SPRU970G December 2005 Revised June 2011 C6455 C6454 DDR2 Memory Controller 25 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated I TEXAS INSTRUMENTS Peripheral Architecture www ti com 2 7 2 26 Next the DDR2 memory controller examines each of the commands selected by the individual masters and performs the following reordering Among all pending reads selects reads to rows already open Among all pending writes selects writes to rows already open Selects the highest priority command from pend
19. until the same page has been accessed in all banks To the DDR2 SDRAM this process looks as shown on Figure 14 By traversing across banks while remaining on the same row page the DDR2 memory controller maximizes the number of activated banks for a linear access This results in the maximum number of open pages when performing a linear access being equal to the number of banks Note that the DDR2 memory controller never opens more than one page per bank SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback C6455 C6454 DDR2 Memory Controller Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Peripheral Architecture Ending the current access is not a condition that forces the active DDR2 SDRAM row page to be closed The DDR2 memory controller leaves the active row open until it becomes necessary to close it This decreases the deactivate reactivate overhead Figure 13 Logical Address to DDR2 SDRAM Address Map Col 0 Col 1 Col 2 Col 3 Col 4 coe Col M 1 Col M Row 0 bank 0 Row 0 bank 1 Row 0 bank 2 Row 0 bank P Row 1 bank 0 Row 1 bank 1 Row 1 bank 2 Row 1 bank P Row N bank 0 Row N bank 1 Row N bank 2 Row N bank P A Mis number of columns as determined by PAGESIZE minus 1 P is number of banks as determined by IBANK minus 1 and
20. 0031 15 8 7 0 MJ_REV MN_REV R 0x03 R 0xOF LEGEND R W Read Write R Read only n value after reset Table 18 Module ID and Revision Register MIDR Field Descriptions Bit Field Value Description 31 30 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 29 16 MOD ID Module ID bits 15 8 MJ REV Major revision 7 0 MN REV Minor revision SPRU970G December 2005 Revised June 2011 C6455 C6454 DDR2 Memory Controller 39 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated I TEXAS INSTRUMENTS DDR2 Memory Controller Registers www ti com 42 DDR2 Memory Controller Status Register DMCSTAT The DDR2 memory controller status register DMCSTAT is shown in Figure 20 Figure 20 DDR2 Memory Controller Status Register DMCSTAT 31 30 29 38 BE Rsvd Reserved R 0x0 R 0x1 R 0x0 15 3 2 1 0 Reserved IFRDY Reserved R 0x0 R 0x0 R 0x0 LEGEND R W Read Write R Read only n value after reset Table 19 DDR2 Memory Controller Status Register DMCSTAT Field Descriptions Bit Field Value Description 31 BE Big endian bit Reflects whether the DDR2 Memory Controller is configured for big or little endian mode 0 DDR2 Memory Controller is configured for little endian mode 1 DDR2 Memory Controller is configured for big endian mode 30 Reserved Reser
21. 4 5 READ Command Peripheral Architecture Figure 8 shows the DDR2 memory controller performing a read burst from DDR2 SDRAM The READ command initiates a burst read operation to an active row During the READ command DSDCAS drives low and remain high the column address is driven on DEA 12 0 and the bank address is driven on DBA 2 0 The DDR2 memory controller uses a burst length of 8 and has a programmable CAS latency of 2 3 4 or 5 The CAS latency is three cycles in Figure 8 Read latency is equal to CAS latency plus additive latency The DDR2 memory controller always configures the memory to have an additive latency of 0 so read latency equals CAS latency Since the default burst size is 8 the DDR2 memory controller returns 8 pieces of data for every read command If additional accesses are not pending to the DDR2 memory controller the read burst completes and the unneeded data is disregarded If additional accesses are pending depending on the scheduling result the DDR2 memory controller can terminate the read burst and start a new read burst Furthermore the DDR2 memory controller does not issue a DCAB DEAC command until page information becomes invalid DDR2CLKOUT DDR2CLKOUT DSDCKE DCEO DSDRAS DSDCAS DSDWE DEA 13 0 DBA 2 0 DEA 10 DSDDQN 3 0 DED 31 0 DSDDQS 3 0 SPRU970G December 2005 Revised June 2011 Figure 8 DDR2 READ Command igi Submit Documentation Fee
22. 6000 Programmer s Guide Describes ways to optimize C and assembly code for the TMS320C6000 DSPs and includes application program examples SPRU301 TMS320C6000 Code Composer Studio Tutorial Introduces the Code Composer Studio integrated development environment and software tools SPRU321 Code Composer Studio Application Programming Interface Reference Guide Describes the Code Composer Studio application programming interface API which allows you to program custom plug ins for Code Composer SPRU871 TMS320C64x Megamodule Reference Guide Describes the TMS320C64x digital signal processor DSP megamodule Included is a discussion on the internal direct memory access IDMA controller the interrupt controller the power down controller memory protection bandwidth management and the memory and cache C6000 TMS320C6000 Code Composer Studio are trademarks of Texas Instruments All other trademarks are the property of their respective owners SPRU970G December 2005 Revised June 2011 Preface 7 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated Read This First SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated j Users Guide TE S SPRU970G December 2005 Revised June 2011 INSTRUMENTS C6455 C6454 DDR2 Memory Controller 1 Introduction 1 1 Purpose of the Peripheral The DDR2 memory controlle
23. CLKOUT driven by internal clock sources Command signals Row and column address strobe DSDRAS and DSDCAS write enable strobe DSDWE data strobe DSDDQS 3 0 and DSDDQSJ3 0 and data mask DSDDQN 3 0 Onechip select signal DCEO Oneclock enable signal DSDCKE Two on die termination output signals DEODT 1 0 These pins are reserved for future use SPRU970G December 2005 Revised June 2011 C6455 C6454 DDR2 Memory Controller 11 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated Peripheral Architecture I TEXAS INSTRUMENTS www ti com Figure 2 DDR2 Memory Controller Signals DDR2CLKOUT DDR2CLKOUT DSDCKE DCEO DSDWE DSDRAS DSDCAS DDR2 DSDDQMI3 0 E DSDDOS 3 0 DSDDOS 3 0 DBA 2 0 DEA 13 0 DED 31 0 DEODT 1 0 DSDDQGATE 3 0 VREFSSTL DDRSLRATE Table 1 DDR2 Memory Controller Signal Descriptions Pin Description DED 31 0 Bidirectional data bus Input for data reads and output for data writes DEA 13 0 External address output DCEO Active low chip enable for memory space CEO DCEO is used to enable the DDR2 SDRAM memory device during external memory accesses The DCEO pin stays low throughout the operation of the DDR2 memory controller it never goes high Note that this behavior does not affect the ability of the DDR2 memory controller to access DDR2 SDRAM memory devices DSDDQW 3 0 Active low output data mask DDR2CLKOUT Differen
24. DR2CLKOUT cycles from an activate command to an activate command minus 1 The value for these bits can be derived from the t AC timing parameter in the DDR2 memory section of the device specific data manual Calculate using this formula T RC t DDR2CLKOUT 1 44 C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com DDR2 Memory Controller Registers Table 22 SDRAM Timing 1 Register SDTIM1 Field Descriptions continued Bit Field Value Description 5 3 T RRD These bits specify the minimum number of DDR2CLKOUT cycles from an activate command to an activate command in a different bank minus 1 The value for these bits can be derived from the t AC timing parameter in the DDR2 memory section of the device specific data manual Calculate using this formula T RRD t DDR2CLKOUT 1 When connecting to an 8 bank DDR2 SDRAM this field must be equal to T RRD 4 tig 2 t4 Ft 1 2 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 1 0 T WTR These bits specify the minimum number of DDR2CLKOUT cycles from the last write to a read command minus 1 The value for these bits can be derived from the ty AC timing parameter in the DDR2 memory section of the device specific data manual Calculate using this formula
25. DTIM2 the DDR2 memory controller can be configured to meet the data sheet specification for JESD79 2B compliant DDR2 SDRAM devices As an example the following sections describe how to configure each of these registers for access to two 1Gb 16 bit wide DDR2 SDRAM devices connected as shown on Figure 16 where each device has the following configuration Maximum data rate 533MHz Number of banks 8 Page size 1024 words CAS latency 4 It is assumed that the frequency of the DDR2 memory controller clock DDR2CLKOUT is set to 250MHz 3 2 1 Programming the SDRAM Configuration Register SDCFG The SDRAM configuration register SDCFG contains register fields that configure the DDR2 memory controller to match the data bus width CAS latency number of banks and page size of the attached DDR2 memory Table 11 shows the resulting SDCFG configuration Note that the value of the TIMUNLOCK field is dependent on whether or not it is desirable to unlock SDTIM1 and SDTIM2 The TIMUNLOCK bit should only be set to 1 when the SDTIM1 and SDTIM2 needs to be updated Table 11 SDCFG Configuration Field Value Function Selection TIMUNLOCK x Set to 1 to unlock the SDRAM timing and timing 2 registers Cleared to 0 to lock the SDRAM timing and timing 2 registers NM Oh To configure the DDR2 memory controller for a 32 bit data bus width CL 4h To select a CAS latency of 4 IBANK 3h To select 8 internal DDR2 banks PAGESIZE 2h To selec
26. Init Value Description 12 Power down Mode 0 Active power down exit time bit Configured for Fast exit 11 9 Write Recovery SDTIM1 T_WR Write recovery bits for auto precharge Initialized using the T_WR bits of the SDRAM timing 1 register SDTIM1 8 DLL Reset 0 DLL reset bits DLL is not in reset Mode 0 Operating mode bit Normal operating mode is always selected 6 4 CAS Latency SDCFG CL CAS latency bits Initialized using the CL bits of the SDRAM configuration register SDCFG 3 Burst Type 0 Burst type bits Sequential burst mode is always used 2 0 Burst Length 3h Bust length bits A burst length of 8 is always used Table 10 DDR2 SDRAM Extended Mode Register 1 Configuration Mode Register Bit Mode Register Field Init Value Description 12 Output Buffer Enable 0 Output buffer enable bits Output buffer is always enabled 11 RDQS Enable 0 RDQS enable bits Always initialized to 0 RDQS signals disabled 10 DQS enable 0 DQS enable bit Always initialized to 0 DQS signals enabled 9 7 OCD Operation Oh Off chip driver impedance calibration bits This bit is always initialized to Oh 6 ODT Value Rtt 0 On die termination effective resistance Rtt bit This bit is reserved for future use 5 8 Additive Latency Oh Additive latency bits Always initialized to Oh no additive latency 2 ODT Value Rtt 1 On die termination effective resistance Rtt bit This bit is reserved for future use 1 Output Driver Impedance SDCFG DDR DRIVE Output driver im
27. L BAO OP Code EMRS H H L L L L BA OP Code READ H H L H L H BA Column Address L READ with H H i H L H BA Column Address H precharge WRT H H H L L BA Column Address L WRT with precharge H H k H L L BA Column Address REFR H H L L L H x x x SLFREFR H L L L L H x x x entry SLFREFR L H H x x x x x x ext L H H H Xx x x NOP x L H H H x x x DESEL x H x x x x x x Power down L H X X X X X X ently L H H H X x x Power down It H H X X X X X X ext L H H H X x x LEGEND H logic high L logic low X don t care either H or L BA refers to the bank address pins BA 2 0 SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback C6455 C6454 DDR2 Memory Controller 13 Copyright 2005 2011 Texas Instruments Incorporated I TEXAS INSTRUMENTS Peripheral Architecture www ti com 2 4 1 Mode Register Set MRS and EMRS DDR2 SDRAM contains mode and extended mode registers that configure the DDR2 memory for operation These registers control burst type burst length CAS latency DLL enable disable single ended strobe etc The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands When the MRS or EMRS command is executed the value on DBA 1 0 selects the mode register to be written and the data on DEA 12 0 is loaded into the register Figure 3 shows the timing for an MRS and EMRS command The DDR2 memory con
28. N is number of rows as determined by both PAGESIZE and IBANK minus 1 SPRU970G December 2005 Revised June 2011 C6455 C6454 DDR2 Memory Controller 23 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated I TEXAS INSTRUMENTS Peripheral Architecture www ti com Figure 14 DDR2 SDRAM Column Row and Bank Access C 66 C 000 o Logd Og ewe C Bank0 0 1 2 3 M o 0 0 o R owe JALALA TALA Pe o ccc c Row Bank1 0 1 2 3 M 000 o Row 2 R owo JA AAAA LU ME ccc c Row 1 Bank2 0 1 2 83 M 000 o Row 2 Row 0 alalalals 11 Row 1 BankPNO 1 2 83 M Row 2 Row 0 alalalals Row 1 Row N 2 Row 2 Row N i Row N Row N A Mis number of columns as determined by PAGESIZE minus 1 P is number of banks as determined by IBANK minus 1 and N is number of rows as determined by both PAGESIZE and IBANK minus 1 2 7 DDR2 Memory Controller Interface To move data efficiently from on chip resources to external DDR2 SDRAM device the DDR2 memory controller makes use of a command FIFO a write FIFO a read FIFO and command and data schedulers Table 6 describes the purpose of each FIFO Figure 15 shows the block diagram of the DDR2 memory controller FIFOs Commands write data and read data arrive at the DDR2 memory
29. QS DSDDQSO LDQS DSDDQS1 UDQS DSDDQST UDQS DBA 2 0 BA 2 0 DEA 13 0 12 0 DED 15 0 DQ 15 0 DSDDQM2 ODT DSDDQM3 DSDDQS2 DSDDQS2 DSDDQS3 DSDDQS3 DED 31 16 ODTO ODT1 DDRSLRATE DSDDQGATEO DSDDQGATE1 DSDDOGATE2 DSDDOGATE3 A These pins are used as a timing reference during memory reads For routing rules see the device specific data manual 32 C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Using the DDR2 Memory Controller Figure 17 Connecting to a Single 16 Bit DDR2 SDRAM Device DDR2CLKOUT DDR2CLKOUT DSDCKE DDR2 DCEO Controller DSDWE DSDRAS DSDCAS DSDDQMO DSDDOM1 DSDDQSO DSDDQSO DSDDQS1 DSDDQS1 DBA 2 0 DEA 13 0 DED 15 0 ODTO ODT1 VREFSSTL DDRSLRATE DSDDQGATEO A DSDDQGATE1 DSDDQGATE2 DSDDQGATE3 CK CK CS WE RAS CAS LDM UDM LDQS LDQS UDQS UDQS BA 2 0 A 12 0 DQ 15 0 ODT VREF A These pins are used as a timing reference during memory reads For routing rules see the device specific data manual SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback
30. R2 SDRAM Address Map eceeeeeeeeee eee e eee eee eee II II Henn eme emen nenne 23 14 DDR2 SDRAM Column Row and Bank ACCESS ssssssssseseeen nnne nnne nena n sss nnn 24 15 DDR2 Memory Controller FIFO Block Diagram eeceee eect cece ee ee eee e ee IH III mn 25 16 Connecting to Two 16 Bit DDR2 SDRAM Devices ecceeee eee ee eee e eee eee eee HII HI ne nene nnne de 17 Connecting to a Single 16 Bit DDR2 SDRAM Device cecee cece ee ee eee ee eee III Hm nennen 33 18 Connecting to Two 8 Bit DDR2 SDRAM DeVICES ccceece cece ee eee eee nee e eee eee HH Hn e nne nemen 34 19 Module ID and Revision Register MIDR cceeeeeeeeeeeeeeeeeee eens eeeeeeneeeeneeeeneeeneeeteeeeeneeetneeenneeens 39 20 DDR2 Memory Controller Status Register DMCSTAT 0cceeeeeeeeeeeeeee seen eeeeeeeeeeeeeeeeeeeeeeeeneeneaees 40 21 SDRAM Configuration Register SDCFG c seceeeseeeeeeeee cess eeeeee eee eeeeeeeeeeeneeeeeeeeeeeeeeeeeeeneeenans 41 22 SDRAM Refresh Control Register SDRFC 0ccceeeee eee eee ee eee e eee e eee e enn e n eme emen nnnm nenne 43 23 SDRAM Timing 1 Register SDTIM1 eecseeeeeeeee cece eee nee eee n enn e nh hem nnne hn nnn nnn nnne nn 44 24 SDRAM Timing 2 Register SDTIM2 sssrinds dtr equa euo eoru nsa a cepa resa rumE EIE E RP un EE 46 25 Burst Priority Register BRIO sits sss oce stus eau eem ss utum E tee PR LA DRE ENE OEE MEE oc ese e TREES 47 26 DDR2 Memory Controller Control Register DMCCTL
31. RAM T ODT must be equal to tionn T ODT taonp 22 16 T XSNR 0 7Fh_ These bits specify the minimum number of DDR2CLKOUT cycles from a self refresh exit to any other command except a read command minus 1 The value for these bits can be derived from the tysyr AC timing parameter in the DDR2 section of the device specific data manual Calculate using this formula T XSNR txsnr 1 15 8 T XSRD 0 FFh These bits specify the minimum number of DDR2CLKOUT cycles from a self refresh exit to a read command minus 1 The value for these bits can be derived from the txsro AC timing parameter in the DDR2 section of the device specific data manual Calculate using this formula T XSRD tysap 1 7 b T_RTP 0 7h_ These bits specify the minimum number of DDR2CLKOUT cycles from a last read command to a precharge command minus 1 The value for these bits can be derived from the t4 AC timing parameter in the DDR2 section of the device specific data manual Calculate using this formula T RTP t DDR2CLKOUT 1 4 0 T CKE 0 1Fh These bits specify the minimum number of DDR2CLKOUT cycles between transitions on the DSDCKE pin minus 1 The value for these bits can be derived from the txe AC timing parameter in the DDR2 section of the device specific data manual Calculate using this formula T_CKE txe 1 46 C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June 2011 Submit Documentation Fe
32. TMS320C6455 C6454 DSP DDR2 Memory Controller User s Guide X TEXAS INSTRUMENTS Literature Number SPRU970G December 2005 Revised June 201 1 SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated IJ TEXAS INSTRUMENTS Contents luc ERR 7 1 Huge ge 9 1 1 Purpose Of the Peripheral 9 1 2 upper 9 1 3 Functional Block Diagram ccessseeeseeenn en n nm n hh hn nhe nne hh nh e nne nne nnne nnn 9 1 4 Industry Standard s Compliance Statement cceeeeeee eee eee eee eee eee eee e eee ee sees seas teen eeeneeeeeeneeeeee 10 2 Peripheral Architect re oret enitn eonun tun dicelnisestaniewaitoaatensiesis asia cin sa M aa 11 2 1 ele sees m 11 2 2 Memory om 11 2 3 Signal Descriptions tc E 11 2 4 Protocol DescrIptlOn s sx3 suxssekukunuxexcam en paE ak YR PLE PRRR ADIRE anne EEEE EEE PDA BERN EE 13 2 5 Memory Width Byte Alignment and Endianness c eee eect ences I HH m nnn 20 2 6 Address MAPPING RTT 21 2 7 DDR2 Memory Controller Interface cceceeeee eee eee ee eee e nee eee eee eeeeeeeeeeeeeeeeeenaeeeeeeeeeaeeeaseeeeaee 24 2 8 Refresh Scheduling ee 27 2 9 Self Refresh Mode RR Sem 28 2 10 Reset Consid
33. The value for these bits can be derived from the t AC timing parameter in the DDR2 memory section of the device specific data manual Calculate using the formula T RP t DDR2CLKOUT 1 21 19 T RCD These bits specify the minimum number of DDR2CLKOUT cycles from an activate command to a read or write command minus 1 The value for these bits can be derived from the t4 AC timing parameter in the DDR2 memory section of the device specific data manual Calculate using the formula T RCD t DDR2CLKOUT 1 18 16 T WR These bits specify the minimum number of DDR2CLKOUT cycles from the last write transfer to a precharge command minus 1 The value for these bits can be derived from the tw AC timing parameter in the DDR2 memory section of the device specific data manual Calculate using the formula T WR t DDR2CLKOUT 1 The SDRAM initialization sequence will be started when the value of this field is changed from the previous value and the DDR2 ENABLE in SDCFG is equal to 1 15 11 T RAS These bits specify the minimum number of DDR2CLKOUT cycles from an activate command to a precharge command minus 1 The value for these bits can be derived from the t AC timing parameter in the DDR2 memory section of the device specific data manual Calculate using this formula T RAS t DDR2CLKOUT 1 T RAS must be greater than or equal to T RCD 10 6 These bits specify the minimum number of D
34. ached DDR2 device by programming the rate at which the DDR2 memory controller issues autorefresh commands The SDRFC is shown in Figure 22 and described in Table 21 Figure 22 SDRAM Refresh Control Register SDRFC 31 30 29 16 SR Rsvd Reserved R W R W R 0x0 0x0 0x0 15 8 REFRESH RATE R W 0x753 LEGEND R W Read Write R Read only n value after reset Table 21 SDRAM Refresh Control Register SDRFC Field Descriptions Bit Field Value Description 31 SR Self refresh bit Writing a 1 to this bit will cause connected SDRAM devices to be place into Self Refresh mode and the DDR2 Memory Controller to enter the Self Refresh state 0 Exit self refresh mode Enter self refresh mode 30 16 Reserved Reserved Writes to this register must keep this field at its default value 15 0 REFRESH RATE Refresh rate bits The value in this field is used to define the rate at which connected SDRAM devices will be refreshed as follows SDRAM refresh rate DDR2CLKOUT clock rate REFRESH RATE Writing a value less than 0x0100 to this field will cause it to be loaded with 2 T RFC value from the SDRAM Timing 1 Register SPRU970G December 2005 Revised June 2011 C6455 C6454 DDR2 Memory Controller 43 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated DDR2 Memory Controller Registers I TEXAS INSTRUMENTS www ti com
35. as 0 A value written to this field has no effect 6 4 IBANK w N O Internal SDRAM bank setup bits Defines number of banks inside connected SDRAM devices A write to this bit will cause the DDR2 Memory Controller to start the SDRAM initialization sequence Values 4 7 are reserved for this field One bank SDRAM devices Two banks SDRAM devices Four banks SDRAM devices Eight banks SDRAM devices Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 2 0 PAGESIZE on O Page size bits Defines the internal page size of the external DDR2 memory A write to this bit will cause the DDR2 Memory Controller to start the SDRAM initialization sequence Values 4 7 are reserved for this field 256 word page requiring 8 column address bits 512 word page requiring 9 column address bits 1024 word page requiring 10 column address bits 2048 word page requiring 11 column address bits 42 C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com DDR2 Memory Controller Registers 44 SDRAM Refresh Control Register SDRFC The SDRAM refresh control register SDRFC is used to configure the DDR2 memory controller to Enter and Exit the self refresh state Meetthe refresh requirement of the att
36. ble Memory Ranges Memory Width Maximum Addressable Bytes Address Type Generated by DDR2 Memory Controller x16 256M bytes Halfword address x32 512M bytes Word address 20 C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Peripheral Architecture Figure 10 shows the byte lanes used on the DDR2 memory controller The external memory is always right aligned on the data bus Figure 10 Byte Alignment DDR2 memory controller data bus DED 31 24 DED 23 16 DED 15 8 DED 7 0 Byte Lane 3 Byte Lane 2 Byte Lane 1 Byte Lane 0 32 bit memory device 16 bit memory device The DDR2 memory controller supports both little endian and big endian formats The endianness mode determines whether byte lane 0 DED 7 0 is accessed as byte address 0 little endian or as byte address N big endian where 2 is the memory width in bytes Similarly byte lane N is addresses as either byte address 0 big endian or as byte address N little endian The DDR2 memory controller uses the endianness mode being used by the rest of the DSP The endianness mode of the DSP is set during device reset for more details see the device specific data manual The endianness mode of the DDR2 memory controller is shown on the BE bit of the DDR2 memory controller status register DMCSTAT BE 1
37. controller performs a REFR command the backlog counter decrements by 1 This means the refresh backlog counter records the number of REFR commands the DDR2 memory controller currently has outstanding The DDR2 memory controller issues REFR commands based on the level of urgency The level of urgency is defined in Table 7 Whenever the refresh level of urgency is reached the DDR2 memory controller issues a REFR command before servicing any new memory access requests Following a REFR command the DDR2 memory controller waits T_RFC cycles defined in the SDRAM timing 1 register SDTIM1 before rechecking the refresh urgency level In addition to the refresh counter previously mentioned a separate backlog counter ensures the interval between two REFR commands does not exceed 8x the refresh rate This backlog counter increments by 1 each time the interval counter expires and resets to zero when the DDR2 memory controller issues a REFR command When this backlog counter is greater than 7 the DDR2 memory controller issues four REFR commands before servicing any new memory requests The refresh counters do not operate when the DDR2 memory is in self refresh mode Table 7 Refresh Urgency Levels Urgency Level Description Refresh May Backlog count is greater than 0 Indicates there is a backlog of REFR commands when the DDR2 memory controller is not busy it will issue the REFR command Refresh Release Backlog count is greater than 3 Indicat
38. dback 4 CAS Latency p C6455 C6454 DDR2 Memory Controller 19 Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS Peripheral Architecture www ti com 2 4 6 Write WRT Command Prior to a WRT command the desired bank and row are activated by the ACTV command Following the WRT command a write latency is incurred Write latency is equal to CAS latency minus 1 All writes have a burst length of 8 The use of the DSDDQM outputs allows byte and halfword writes to be executed Figure 9 shows the timing for a write on the DDR2 memory controller If the transfer request is for less than 8 words depending on the scheduling result and the pending commands the DDR2 memory controller can Mask out the additional data using DSDDQM outputs Terminate the write burst and start a new write burst The DDR2 memory controller does not perform the DEAC command until page information becomes invalid Figure 9 DDR2 WRT Command DDR2CLKOUT TX KOKO XD DDR2CLKOUT I Sample Write Latency DSDRAS DSDCAS DSDWE N DEAL DBA Z 0 O LL DEA 10 DED 31 0 DsppaQs 3 0 Q 7N N N NL A 2 5 Memory Width Byte Alignment and Endianness The DDR2 memory controller supports memory widths of 16 bits and 32 bits Table 4 summarizes the addressable memory ranges on the DDR2 memory controller Table 4 Addressa
39. ddition it provides flexibility through programmable parameters such as the refresh rate CAS latency and many SDRAM timing parameters The following sections describe the architecture of the DDR2 memory controller as well as how to interface and configure it to perform read and write operations to DDR2 SDRAM devices Also Section 3 provides a detailed example of interfacing the DDR2 memory controller to a common DDR2 SDRAM device Clock Control The DDR2 memory controller is clocked directly from the output of the second phase locked loop PLL2 of C6455 C6454 devices The PLL2 multiplies its input clock by 20 This clock is divided by 2 to generate DDR2CLKOUT The frequency of DDR2CLKOUT can be determined by using the following formula DDR2CLKOUT frequency PLL2 input clock frequency x 20 2 PLL2 input clock frequencyx 10 The second output clock of the DDR2 memory controller DDR2CLKOUT is the inverse of DDR2CLKOUT For more information on the PLL2 see the device specific data manual Memory Map For information describing the device memory map see the device specific data manual Signal Descriptions The DDR2 memory controller signals are shown in Figure 2 and described in Table 1 The following features are included The maximum width for the data bus DED 31 0 is 32 bits The address bus DEA 13 0 is 14 bits wide with an additional 3 bank address pins DBA 2 0 Two differential output clocks DDR2CLKOUT and DDR2
40. ecifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Audio Amplifiers Data Converters DLP Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID RF IF and ZigBee Solutions www ti com audio amplifier ti com dataconverter ti com www dlp com www ti com clocks interface ti com logic ti com power ti com microcontroller ti com www ti rfid com www ti com lprf Applications Communications and Telecom Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space Avionics and Defense Transportation and Automo
41. ection 2 11 1 The SDCFG register is shown in Figure 21 and described in Table 20 Figure 21 SDRAM Configuration Register SDCFG 31 24 Reserved R 0x0 23 22 19 18 17 16 ieee Reserved DDR_DRIVE Reserved R W 0 R W 0xA R 0 R 0x3 15 14 13 12 11 9 8 TIMUNLOCK NM Reserved CL Reserved R W 0 R W 0 R 0x0 R W 0x5 R 0x0 7 6 4 3 2 0 Reserved IBANK Reserved PAGESIZE R 0x0 R W 0x2 R 0x0 R W 0x0 LEGEND R W Read Write R Read only n value after reset Table 20 SDRAM Configuration Register SDCFG Field Descriptions Bit Field Value Description 31 24 Reserved Reserved Writes to this register must keep these bits at their default values 23 BOOT_UNLOCK Boot unlock bit Controls write access to bits 16 22 and 27 of this register 0 Writes to bits 22 16 of this register are not permitted Writes to bits 22 16 of this register are allowed 22 19 Reserved Reserved Writes to this register must keep these bits at their default value 18 DDR_DRIVE DDR2 SDRAM drive strength This bit is used to select the drive strength used by the DDR2 SDRAM This bit is writeable only when BOOT UNLOCK is unlocked set to 1 0 Normal drive strength Weak 60 drive strength 17 16 Reserved Reserved Writes to this register must keep these bits at their default value 15 TIMUNLOCK Timing unlock bit Controls write access for the SDRAM Timing Register SDTIM1 and
42. ed June 2011 C6455 C6454 DDR2 Memory Controller 15 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS Peripheral Architecture www ti com 2 4 3 16 Activation ACTV The DDR2 memory controller automatically issues the activate ACTV command before a read or write to a closed row of memory The ACTV command opens a row of memory allowing future accesses reads or writes with minimum latency The value of DBA 2 0 selects the bank and the value of A 12 0 selects the row When the DDR2 memory controller issues an ACTV command a delay of tac is incurred before a read or write command is issued Figure 5 shows an example of an ACTV command Reads or writes to the currently active row and bank of memory can achieve much higher throughput than reads or writes to random areas because every time a new row is accessed the ACTV command must be issued and a delay of tacp incurred Figure 5 ACTV Command ACTV orero 7 DDR2CLKOUT DSDCKE DCEO DSDRAS N DSDCAS DSDWE DEA 3 0 X ROW AX DBA AX BANK OX osoon C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com 2 4 4 Deactivation DCAB and DEAC Peripheral Architecture The precharge all ba
43. edback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com DDR2 Memory Controller Registers 47 Burst Priority Register BPRIO The Burst Priority Register BPRIO helps prevent command starvation within the DDR2 memory controller To avoid command starvation the DDR2 memory controller momentarily raises the priority of the oldest command in the command FIFO after a set number of transfers have been made The PRIO_RAISE bit sets the number of transfers that must be made before the DDR2 memory controller raises the priority of the oldest command The BPRIO is shown in Figure 25 and described in Table 24 For more details on command starvation see Section 2 7 2 Figure 25 Burst Priority Register BPRIO 31 16 Reserved R 0 15 8 7 0 Reserved PRIO RAISE R 0 R W OxFF LEGEND R W Read Write R Read only n value after reset Table 24 Burst Priority Register BPRIO Field Descriptions Bit Field Value Description 31 8 Reserved 000h Reserved The reserved bit location is always read as 0 A value written to this field has no effect 7 0 PRIO_RAISE Oh 1 memory transfer th 2 memory transfers FEh 255 memory transfers FFh EMIF reorders commands based on its arbitration SPRU970G December 2005 Revised June 2011 C6455 C6454 DDR2 Memory Controller 47 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated
44. eeeeeeneeeeeeeeeeeenanes 36 13 SDRFOC Configurations sacs cose mu tto tuna RI ux D eR EIRDE UA ME A END ENDM PIU SEN DU NNIDNREA DUANE MUN NN RE ROME EE 36 14 SDTIMA CONMGUIALION e 36 15 SDTIM2 GCohfigiralolisszseeseonbs estes iqe see ae denessas EE a S NE aaa NE EUER HENDRER NUUS RUNE UE 37 16 DMCOTL rere nie Url nOERRR 37 17 DDR2 Memory Controller Registers eeeeeeeeeeeeeeseeee eene nnne hen hn nnne nnn nnn nnn 38 18 Module ID and Revision Register MIDR Field Descriptions eeeeeee HH 39 19 DDR2 Memory Controller Status Register DMCSTAT Field Descriptions eese 40 20 SDRAM Configuration Register SDCFG Field Descriptions cceceeee eee eee eee e eee eee eens eeeeeeeeeeeeeeeee 41 21 SDRAM Refresh Control Register SDRFC Field Descriptions eeeeeeeeeeernII 43 22 SDRAM Timing 1 Register SDTIM1 Field Descriptions eeeeeeeeenHHIHH 44 23 SDRAM Timing 2 Register SDTIM2 Field Descriptions esses 46 24 Burst Priority Register BPRIO Field Descriptions cceeeeeeeee eee eeeeee eee e neces III 47 25 DDR2 Memory Controller Control Register DMCCTL Field Descriptions seeeeeee eene 48 SPRU970G December 2005 Revised June 2011 List of Tables 5 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 6 List of Tables SPRU970G December 2005
45. ency 1 5 SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback C6455 C6454 DDR2 Memory Controller 37 Copyright 2005 2011 Texas Instruments Incorporated IJ TEXAS INSTRUMENTS DDR2 Memory Controller Registers www ti com 4 DDR2 Memory Controller Registers Table 17 lists the memory mapped registers for the DDR2 memory controller For the memory address of these registers see the device specific data manual Table 17 DDR2 Memory Controller Registers Offset Acronym Register Description Section 00h MIDR Module ID and Revision Register Section 4 1 04h DMCSTAT DDR2 Memory Controller Status Register Section 4 2 08h SDCFG SDRAM Configuration Register Section 4 3 OCh SDRFC SDRAM Refresh Control Register Section 4 4 10h SDTIM1 SDRAM Timing 1 Register Section 4 5 14h SDTIM2 SDRAM Timing 2 Register Section 4 6 20h BPRIO Burst Priority Register Section 4 7 E4h DMCCTL DDR2 Memory Controller Control Register Section 4 8 38 C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com DDR2 Memory Controller Registers 4 1 Module ID and Revision Register MIDR The Module ID and Revision register MIDR is shown in Figure 19 and described in Table 18 Figure 19 Module ID and Revision Register MIDR 31 30 29 16 Reserved MOD_ID R 0x0 R 0x
46. erallons ais sicecsesareseird ssn ferhcsieietesaerarecoerevna sana wisenere arresaietae miners UNS EN MEN UNIS CQNEROSN E 28 2 11 DDR2 SDRAM Memory Initialization ceeeeseeeeeenn e III I I III HI Ie nennen 28 2 12 INEMUPL SUPPO eccL UE 30 2 13 EDMA Event SUPPO e 30 2 14 Emulation Considerations siesecedicisimcaitad ctedewmeumudeinecuisteaudnde a a O CEN UMEN OE 30 3 Using the DDR2 Memory Controller c cccceeeeee eee eee eee eee eee eee ee eee meme meme eren 31 3 1 Connecting the DDR2 Memory Controller to DDR2 SDRAM cese 31 3 2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications 35 4 DDR2 Memory Controller Registers sess eren 38 4 1 Module ID and Revision Register MIDR eeeeeseeeeen II III HII nmn nnn nnn 39 4 2 DDR2 Memory Controller Status Register DMCSTAT eceeeeeee settee eee eeeeee eee III mnn 40 4 3 SDRAM Configuration Register SDCFG cceceeeee scence eee ee ee ee eee n II mne nene nnne 41 4 4 SDRAM Refresh Control Register SDRFO eeeeeceeeeeee eee ee eee seen n eme nenne nn nennen 43 4 5 SDRAM Timing 1 Register SPINE sss coste nenea a a aa aaa E E ai 44 4 6 SDRAM Timing 2 Register SDTIM2 aaaaaannnsssssnnnnnnnnnnnnnnsnnnnnnnnnnrnnnnnnnnnnnnnnnnnnnnnnnnnnn menneen 46 4 7 Burst Priority Register BPRIO isis sic esee exortum imet m
47. es the level at which enough REFR commands have been performed and the DDR2 memory controller may service new memory access requests Refresh Need Backlog count is greater than 7 Indicates the DDR2 memory controller should raise the priority level of a REFR command above servicing a new memory access Refresh Must Backlog count is greater than 11 Indicates the level at which the DDR2 memory controller should perform a REFR command before servicing new memory access requests SPRU970G December 2005 Revised June 2011 C6455 C6454 DDR2 Memory Controller 27 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated I TEXAS INSTRUMENTS Peripheral Architecture www ti com 2 9 2 10 2 11 28 Self Refresh Mode Setting the self refresh SR bit in the SDRAM refresh control register SDRFC to 1 forces the DDR2 memory controller to place the external DDR2 SDRAM in a low power mode self refresh in which the DDR2 SDRAM maintains valid data while consuming a minimal amount of power When the SR bit is asserted the DDR2 memory controller continues normal operation until all outstanding memory access requests have been serviced and the refresh backlog has been cleared At this point all open pages of DDR2 SDRAM are closed and a self refresh SLFRFR command an autorefresh command with DSDCKE low is issued The DDR2 memory controller exits the self refresh state when a memory access is received or when the
48. hip between the device level resets and the DDR2 memory controller resets Table 8 Device and DDR2 Memory Controller Reset Relationship DDR2 Memory Controller Reset Effect Initiated by Hard reset Resets control logic and all DDR2 memory Power on reset controller registers Warm reset Max reset Soft reset Resets control logic and interrupt registers System reset CPU reset In case of a warm reset on the DSP the DDR2 SDRAM memory content can be retained if the user places the DDR2 SDRAM in self refresh mode before invoking the warm reset However the DDR2 memory controller registers will be reset and need to be reprogrammed to the required values after the warm reset For more information on the device level resets see the device specific data manual DDR2 SDRAM Memory Initialization DDR2 SDRAM devices contain mode and extended mode registers that configure the mode of operation for the device These registers control parameters such as burst type burst length and CAS latency The DDR2 memory controller programs the mode and extended mode registers of the DDR2 memory by issuing MRS and EMRS commands during the initialization sequence described in Section 2 11 2 and Section 2 11 3 The initialization sequence performed by the DDR2 memory controller is compliant with the JESDEC79 2A specification The DDR2 memory controller performs the initialization sequence under the following conditions Automatically following a hard or sof
49. indicates big endian mode and BE 0 indicates little endian mode 2 6 Address Mapping The DDR2 memory controller views external DDR2 SDRAM as one continuous block of memory This statement is true regardless of the number of memory devices located on the chip select space The DDR2 memory controller receives DDR2 memory access requests along with a 32 bit logical address from the rest of the system In turn DDR2 memory controller uses the logical address to generate a row page column bank address and chip selects for the DDR2 SDRAM The number of column and bank address bits used is determined by the IBANK and PAGESIZE fields The chip selection pins used are determined by the DCEO field see Table 5 The DDR2 memory controller uses up to 14 bits for the row page address Table 5 Bank Configuration Register Fields for Address Mapping Bit Field Bit Value Bit Description IBANK Defines the number of internal banks on the external DDR2 memory 0 1 bank th 2 banks 2h 4 banks 3h 8 banks PAGESIZE Defines the page size of each page of the external DDR2 memory 0 256 words requires 8 column address bits th 512 words requires 9 column address bits 2h 1024 words requires 10 column address bits 3h 2048 words requires 11 column address bits SPRU970G December 2005 Revised June 2011 C6455 C6454 DDR2 Memory Controller 21 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated Peripheral Architecture I
50. ing reads and writes to open rows If multiple commands have the highest priority then the DDR2 memory controller selects the oldest command The DDR2 memory controller may now have a final read and write command If the Read FIFO is not full then the read command will be performed before the write command otherwise the write command will be performed first Besides commands received from on chip resources the DDR2 memory controller also issues refresh commands The DDR2 memory controller attempts to delay refresh commands as long as possible to maximize performance while meeting the SDRAM refresh requirements As the DDR2 memory controller issues read write and refresh commands to DDR2 SDRAM device it follows the following priority scheme 1 Highest Refresh request resulting from the Refresh Must level of urgency see Section 2 8 being reached Read request without a higher priority write selected from above reordering algorithm Refresh request resulting from the Refresh Need level of urgency see Section 2 8 being reached Write request selected from above reordering algorithm Refresh request resulting from Refresh May level of urgency see Section 2 8 being reached Lowest Request to enter self refresh mode oo0sRONM The following results from the above scheduling algorithm All writes from a single master will complete in order All reads from a single master will complete in order From the same master any read to
51. nce 1 Set the BOOT_UNLOCK bit in the SDRAM configuration register SDCFG 2 Write a 0 to the BOOT_UNLOCK bit along with the desired value for the DDR_DRIVE bit 3 Program the rest of the SDCFG to the desired value with the TIMUNLOCK bit set unlocked 4 Program the SDRAM timing 1 register SDTIM1 and SDRAM timing register 2 SDTIM2 with the value needed to meet the DDR2 SDRAM device timings Program the REFRESH_RATE bits in the SDRAM refresh control register SDRFC to a value that meets the refresh requirements of the DDR2 SDRAM device 6 Program SDCFG with the desired value and the TIMUNLOCK bit cleared locked 7 Program the read latency RL bit in the DDR2 memory controller control register DMCCTL to the desired value e Interrupt Support The DDR2 memory controller does not generate any interrupts EDMA Event Support The DDR2 memory controller is a DMA slave peripheral and therefore does not generate EDMA events Data read and write requests may be made directly by masters including the EDMA controller Emulation Considerations The DDR2 memory controller will remain fully functional during emulation halts to allow emulation access to external memory C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Using the DDR2 Memory Controller 3 Using the DDR2 Memor
52. nks command DCAB is performed after a reset to the DDR2 memory controller or following the initialization sequence DDR2 SDRAMs also require this cycle prior to a refresh REFR and mode set register commands MRS and EMRS During a DCAB command DEA10 is driven high to ensure the deactivation of all banks Figure 6 shows the timing diagram for a DCAB command Figure 6 DCAB Command DCAB DDRZCLKOUT aXX X DDR2CLKOUT DSDCKE DCEO E E E E DSDRAS N DSDCAS E EL X DSDWE ee 7 een 7 1 NCC peat I osoon 7 SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback C6455 C6454 DDR2 Memory Controller 17 Copyright 2005 2011 Texas Instruments Incorporated Peripheral Architecture I TEXAS INSTRUMENTS www ti com The DEAC command closes a single bank of memory specified by the bank select signals Figure 7 shows the timings diagram for a DEAC command DDR2CLKOUT DDR2CLKOUT DSDCKE DCEO Figure 7 DEAC Command DEAC DD CD M M i DSDRAS N M oH M DSDCAS DSDWE N pEA 13 11 9 9 LL peat N 4 18 C6455 C6454 DDR2 Memory Controller Copyright 2005 2011 Texas Instruments Incorporated SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback 1 TEXAS INSTRUMENTS www ti com 2
53. pedance control bits Initialized using the DDR DRIVE bit of the SDRAM configuration register SDCFG 0 DLL Enable 0 DLL enable disable bits DLL is always enabled SPRU970G December 2005 Revised June 2011 C6455 C6454 DDR2 Memory Controller 29 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated I TEXAS INSTRUMENTS Peripheral Architecture www ti com 2 11 2 2 11 3 2 12 2 13 2 14 30 DDR2 SDRAM Initialization After Reset After a hard or a soft reset the DDR2 memory controller will automatically start the initialization sequence The DDR2 memory controller will use the default values in the SDRAM timing 1 and timing 2 registers and the SDRAM configuration register to configure the mode registers of the DDR2 SDRAM device s Note that since a soft reset does not reset the DDR2 memory controller registers an initialization sequence started by a soft reset would use the register values from a previous configuration DDR2 SDRAM Initialization After Register Configuration The initialization sequence can also be initiated by performing a write to the two least significant bytes in the SDRAM configuration register SDCFG Using this approach data and commands stored in the DDR2 memory controller FIFOs are not lost and the DDR2 memory controller ensures read and write commands are completed before starting the initialization sequence Perform the following steps to start the initialization seque
54. r is used to interface with JESD79 2B standard compliant DDR2 SDRAM devices Memory types such as DDR1 SDRAM SDR SDRAM SBSRAM and asynchronous memories are not supported The DDR2 memory controller SDRAM can be used for program and data storage 1 2 Features The DDR2 memory controller supports the following features e JESD79 2B standard compliant DDR2 SDRAM e 512M byte memory space Data bus width of 32 or 16 bits CAS latencies 2 3 4 and 5 Internal banks 1 2 4 and 8 Burst length 8 Burst type sequential 1CE signal Page sizes 256 512 1024 and 2048 SDRAM autoinitialization Self refresh mode Prioritized refresh Programmable refresh rate and backlog counter Programmable timing parameters Little endian and big endian transfers 1 3 Functional Block Diagram The DDR2 memory controller is the main interface to external DDR2 memory see Figure 1 Master peripherals such as the EDMA controller and the CPU can access the DDR2 memory controller through the switched central resource SCR The DDR2 memory controller performs all memory related background tasks such as opening and closing banks refreshes and command arbitration SPRU970G December 2005 Revised June 2011 C6455 C6454 DDR2 Memory Controller 9 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated Introduction 1 4 10 DDR2 memory controller BEEN Switched central resource O
55. r quality control techniques are used to the extent Tl deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business
56. t 1024 word page size 3 2 2 Programming the SDRAM Refresh Control Register SDRFC The SDRAM refresh control register SDRFC configures the DDR2 memory controller to meet the refresh requirements of the attached DDR2 device SDRFC also allows the DDR2 memory controller to enter and exit self refresh In this example we assume that the DDR2 memory controller is not is in self refresh mode The REFRESH RATE field in SDRFC is defined as the rate at which the attached DDR2 device is refreshed in DDR2 cycles The value of this field may be calculated using the following equation REFRESH_RATE DDR2CLKOUT frequency x memory refresh period SPRU970G December 2005 Revised June 2011 C6455 C6454 DDR2 Memory Controller 35 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS Using the DDR2 Memory Controller www ti com Table 12 displays the DDR2 533 refresh rate specification Table 12 DDR2 Memory Refresh Specification Symbol Description Value trer Average Periodic Refresh Interval 7 8 us Therefore the value for the REFRESH RATE can be calculated as follows REFRESH RATE 250 MHz x 7 8 us 1950 79Eh Table 13 shows the resulting SDRFC configuration Table 13 SDRFC Configuration Field Value Function Selection SR 0 DDR2 memory controller is not in self refresh mode REFRESH RATE 79Eh Set to 79Eh DDR2 clock cycles to meet the DDR2 memory refresh rate
57. t reset see Section 2 11 2 C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Peripheral Architecture Following a write to the two least significant bytes in the SDRAM configuration register SDCFG see Section 2 11 3 At the end of the initialization sequence the DDR2 memory controller performs an auto refresh cycle leaving the DDR2 memory controller in an idle state with all banks deactivated When the initialization section is started automatically after a hard or soft reset commands and data stored in the DDR2 memory controller FIFOs are lost However when the initialization sequence is initiated by a write to the two least significant bytes in SDCFG data and commands stored in the DDR2 memory controller FIFOs are not lost and the DDR2 memory controller ensures read and write commands are completed before starting the initialization sequence 2 11 4 DDR2 SDRAM Device Mode Register Configuration Values The DDR2 memory controller initializes the mode register and extended mode register 1 of the memory device with the values shown on Table 9 and Table 10 The DDR2 SDRAM extended mode registers 2 and 3 are configured with a value of Oh Table 9 DDR2 SDRAM Mode Register Configuration Mode Register Bit Mode Register Field
58. the same location or within 2048 bytes as a previous write will complete in order Command Starvation The reordering and scheduling rules listed above may lead to command starvation which is the prevention of certain commands from being processed by the DDR2 memory controller Command starvation results from the following conditions Acontinuous stream of high priority read commands can block a low priority write command Acontinuous stream of DDR2 SDRAM commands to a row in an open bank can block commands to the closed row in the same bank To avoid these conditions the DDR2 memory controller can momentarily raise the priority of the oldest command in the command FIFO after a set number of transfers have been made The PRIO RAISE field in the Burst Priority Register BPRIO sets the number of the transfers that must be made before the DDR2 memory controller will raise the priority of the oldest command C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Peripheral Architecture 2 7 3 Possible Race Condition A race condition may exist when certain masters write data to the DDR2 memory controller For example if master A passes a software message via a buffer in DDR2 memory and does not wait for indication that the write completes when master B attempts to read the software message it
59. ther peripherals EDMA controller Boot Industry Standard s Compliance Statement Figure 1 Device Block Diagram L2 memory controller Cache control Bandwidth management Memory protection External memory controller L1P cache SRAM L1 program memory controller I TEXAS INSTRUMENTS www ti com Advanced Cache control event triggering Bandwidth management AET Memory protection Configuration registers Master DMA Slave DMA C64x CPU Instruction fetch SPLOOP buffer 16 32 bit instruction dispatch Instruction decode Data path A Register file A Data path B Register file B L1 data memory controller Interrupt Cache control and exception controller Memory protection Bandwidth management Power control cache SRAM The DDR2 memory controller is compliant with the JESD79 2B DDR2 SDRAM C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June 2011 Copyright 2005 2011 Texas Instruments Incorporated Submit Documentation Feedback l TEXAS INSTRUMENTS www ti com Peripheral Architecture 2 2 1 2 2 2 3 Peripheral Architecture The DDR2 memory controller can gluelessly interface to most standard DDR2 SDRAM devices and supports such features as self refresh mode and prioritized refresh In a
60. tial clock outputs DDR2CLKOUT DSDCKE Clock enable used for self refresh mode DSDCAS Active low column address strobe DSDRAS Active low row address strobe DSDWE Active low write enable DSDDQS 3 0 Differential data strobe bidirectional signals DSDDQSJ3 0 DEODTT 1 0 On die termination signals to external DDR2 SDRAM These pins are reserved for future use and should not be connected to the DDR2 SDRAM DBA 2 0 Bank address control outputs DSDDQGATE 3 0 Data strobe gate pins These pins are used as a timing reference during memory reads The DSDDQGATEO and DSDDQGATE2 pins should be routed out and connected to the DSDDQGATE1 and DSDDQGATES pins respectively For more routing requirements on these pins see the device specific data manual VnerssrL DDR2 Memory Controller reference voltage This voltage must be supplied externally For more details see the device specific data manual DDRSLRATE Pulling the DDRSLRATE input pin low selects the normal slew rate If pulled high the slew rate is reduced by 3396 For normal full speed operation the DDRSLRATE should be pulled low This pin needs to be pulled low or high at all times it is not latched 12 C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Peripheral Architecture 2 4 Protocol Description s The DDR2 memory
61. tive Video and Imaging Wireless TI E2E Community Home Page www ti com communications www ti com computers www ti com consumer apps www ti com energy www ti com industrial www ti com medical www ti com security www ti com space avionics defense www ti com automotive www ti com video www ti com wireless apps Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2011 Texas Instruments Incorporated
62. tn nint cicteaieinininulnictnals witnaiain aie siete trim IDEE RIS 47 4 8 DDR2 Memory Controller Control Register DMCCTL cesses III 48 bhiLibnNLi JAe EET 49 SPRU970G December 2005 Revised June 2011 Table of Contents 3 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 4 IJ TEXAS INSTRUMENTS www ti com List of Figures 1 Device Block Diagram ccceececnsee eter eee ee eee eee eeen eee nse nena ee eene een eeenseeeneeenanereneeeasenenaeenanonenee 10 2 DDR2 Memory Controller Signals cceceeeeeeee ee ee eee ee eee eee e ee eee tees nese nene mnn hn nnn nene enn nenne 12 3 DDR2 MBS and EMRS Gorfirmaldiss secet cuiuios es cuatue E seize Er Rx DIR DER RG EUMD RUBUS UNES 14 4 Refresh COMMAND tL 15 5 TR ABeruurupper rr 16 6 DGAB GOMMANG eet 17 7 DEAC Gommardz 53 cesse e eee omnei bie E a tena anccedets ann Sstatamaten cuenta manisepaienets 18 8 DDR2 READ Commands cicicicscncs exe edens iM Apex DIU IE NU RUNDIDIR IIO INDIA DIM USD MIR e IDEM E RM EN NEUES 19 9 DDR2 WRT Command 5 52 9 Serre a neue remeras ealiiex kunst exe cue cis seu S eipae ciii eds 20 10 PCW e 21 11 Logical Address to DDR2 SDRAM Address Map for 32 Bit SDRAM eee 22 12 Logical Address to DDR2 SDRAM Address Map for 16 bit SDRAM c cesse 22 13 Logical Address to DD
63. troller only issues MRS and EMRS commands during the DDR2 memory controller initialization sequence For more information see Section 2 11 Figure 3 DDR2 MRS and EMRS Command L MRS EMRS occ A S QM G DDRZCLKOUT DSDCKE DCEO n DSDRAS n y DSDCAS DSDWE N DEA13 COL ES DBAZ0 BANK 14 C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Peripheral Architecture 2 4 2 Refresh Mode The DDR2 memory controller issues refresh commands to the DDR2 SDRAM device Figure 4 REFR is automatically preceded by a DCAB command ensuring the deactivation of all CE spaces and banks selected Following the DCAB command the DDR2 memory controller begins performing refreshes at a rate defined by the refresh rate REFRESH_RATE bit in the SDRAM refresh control register SDRFC Page information is always invalid before and after a REFR command thus a refresh cycle always forces a page miss This type of refresh cycle is often called autorefresh Autorefresh commands may not be disabled within the DDR2 memory controller See Section 2 8 for more details on REFR command scheduling Figure 4 Refresh Command REFR DDRZCLKGUT XXL DDR2CLKOUT EL DSDCKE DCEO DSDRAS Nj S DSDWE peatts o 7 oag 7 psppamps o 7 SPRU970G December 2005 Revis
64. ved The reserved bit location is always read as 1 A value written to this field has no effect 29 3 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 2 IFRDY DDR2 memory controller interface logic ready bit The interface logic controls the signals used to communicate with DDR2 SDRAM devices This bit displays the status of the interface logic 0 Interface logic is not ready either powered down not ready or not locked 1 Interface logic is powered up locked and ready for operation 1 0 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 40 C6455 C6454 DDR2 Memory Controller SPRU970G December 2005 Revised June 2011 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com DDR2 Memory Controller Registers 43 SDRAM Configuration Register SDCFG The SDRAM configuration register SDCFG contains fields that program the DDR2 memory controller to meet the specification of the DDR2 memory These fields configure the DDR2 memory controller to match the data bus width CAS latency number of internal banks and page size of the external DDR2 memory Bits 0 14 of the SDCFG register are only writeable when the TIMUNLOCK bit is set to 0 unlocked for more information on initializing the configuration registers of the DDR2 memory controller see S
65. y Controller The following sections show various ways to connect the DDR2 memory controller to DDR2 memory devices The steps required to configure the DDR2 memory controller for external memory access are also described 3 1 Connecting the DDR2 Memory Controller to DDR2 SDRAM Figure 16 Figure 17 and Figure 18 show a high level view of the three memory topologies A 32 bit wide configuration interfacing to two 16 bit wide DDR2 SDRAM devices A 16 bit wide configuration interfacing to a single 16 bit wide DDR2 SDRAM device A 16 bit wide configuration interfacing to two 8 bit wide DDR2 SDRAM devices All DDR2 SDRAM devices must be complaint to the JESD79 2B standard Not all of the memory topologies shown may be supported by your device For more information see the device specific data manual Printed circuit board PCB layout rules and connection requirements between the DSP and the memory device exist and are described in a separate document For more information see the device specific data manual SPRU970G December 2005 Revised June 2011 C6455 C6454 DDR2 Memory Controller 31 Submit Documentation Feedback Copyright 2005 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS Using the DDR2 Memory Controller www ti com Figure 16 Connecting to Two 16 Bit DDR2 SDRAM Devices DDR2CLKOUT CK DDR2CLKOUT CK DSDCKE DDR2 DCEO cs DDR2 Contralor DSDWE WE MEL SDRAS RAS DSDCAS CAS DSDDQMO LDM DSDDQM1 UDM DSDDQSO LD

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