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Texas Instruments TMS320C6454 User's Manual

1. HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A2 0000 PID Peripheral Identification Register 02A2 0004 TCCFG Configuration Register 02A2 0008 02A2 00FC Reserved 02A2 0100 TCSTAT Channel Status Register 02 2 0104 02 2 011 Reserved 02A2 0120 ERRSTAT Error Register 02A2 0124 ERREN Error Enable Register 02A2 0128 ERRCLR Error Clear Register 02A2 012C ERRDET Error Details Register 02A2 0130 ERRCMD Error Interrupt Command Register 02A2 0134 02A2 013C Reserved 02A2 0140 RDRATE Read Rate Register 02A2 0144 02 2 023C Reserved 02A2 0240 SAOPT Source Active Options Register 02A2 0244 SASRC Source Active Source Address Register 02A2 0248 SACNT Source Active Count Register 02A2 024C SADST Source Active Destination Address Register 02A2 0250 SABIDX Source Active Source B Index Register 02A2 0254 SAMPPRXY Source Active Memory Protection Proxy Register 02A2 0258 SACNTRLD Source Active Count Reload Register 02A2 025C SASRCBREF _ Source Active Source Address B Reference Register 02A2 0260 SADSTBREF Source Active Destination Address B Reference Register 02A2 0264 02A2 027C Reserved 02A2 0280 DFCNTRLD Destination FIFO Set Count Reload 02A2 0284 DFSRCBREF _ Destination FIFO Set Destination Address B Reference Register 02A2 0288 DFDSTBREF Destination FIFO Set Destination Address B Reference Register 02A2 028 02A2 02FC Reserved 02A2
2. SIGNAL TYPE IPD IPU DESCRIPTION NAME NO Reserved This pin must be connected to the 1 8 V I O supply DVppig via a RSV34 E6 1 resistor for proper device operation Reserved This pin must be connected directly to ground for proper device RSV35 D6 operation RSV63 AD20 RSV64 AC15 RSV65 AC17 RSV66 AD16 RSV67 U16 RSV68 V15 RSV69 V17 5 70 W16 Reserved These pins must be connected directly to Vgg for proper device RSV71 W18 operation RSV72 AE17 RSV73 AE19 RSV74 AE23 RSV75 AF20 RSV76 AH20 RSV77 AJ17 RSV78 AJ23 SUPPLY VOLTAGE MONITOR PINS Die side 1 2 V core supply CVpp voltage monitor pin The monitor pins indicate the voltage on the die and therefore provide the best probe point for CVppmMon N1 voltage monitoring purposes For more information regarding the use of this and other voltage monitoring pins If the pin is not used it should be connected directly to the 1 2 V core supply CVpp Die side 3 3 V I O supply DVpp33 voltage monitor pin The monitor pins indicate the voltage on the die and therefore provide the best probe point for DVpp33MON L6 voltage monitoring purposes For more information regarding the use of this and other voltage monitoring pins If the DVpp33mon is not used it should be connected directly to the 3 3 V I O supply DVpp33 Die side 1 5 1 8 V I O supply DVpp s voltage monitor
3. RGREFCLK C4 O Z generate RXC clock to communicate with the EMAC This clock is stopped while the device is in reset This pin is available only when RGMII mode is selected MACSEL 1 0 711 RGMII transmit clock O This pin is available only when RGMII mode is RGTXG D4 0 2 selected MACSEL 1 0 11 RGTXD3 A2 RGTXD2 RGMII transmit data 3 0 This pin is available only when RGMII mode is RGTXD1 B3 selected MACSEL 1 0 11 RGTXDO A3 RGMII transmit enable This pin is available only when RGMII mode is RGIXCTL D3 0 2 selected MACSEL 1 0 11 RGMII receive clock I This pin is available only when RGMII mode is selected RGRXC MACSEL 1 0 11 RGRXD3 C1 RGRXD2 4 RGMII receive data 3 0 I This pin is available only when RGMII mode is RGRXD1 2 selected 5 1 0 11 RGRXDO E1 RGMII receive control I This pin is available only when RGMII mode is RGRXCTL c2 selected MACSEL 1 0 11 RESERVED FOR TEST RSV02 V5 RSV03 ws Reserved These pins must be connected directly to core supply CVpp for RSV04 N11 proper device operation RSV05 P11 RSV07 G4 Reserved This pin must be connected directly to 1 5 1 8 V I O supply DVpp15 for proper device operation RSV09 D26 Note If the EMAC RGMII is not used these pins be connected directly to ground Vss Reserved This pin must be connected to ground Vss via a 200 Q resistor for proper d
4. 94 2 5 Pin Assignments 2 4 4 3 14 7 1 Parameter Information 94 2 6 Signal Groups Description 18 7 2 Recommended Clock and Control Signal Transition 2 7 Terminal 24 nnn 96 2 8 47 7 3 Power Supplies eee eee rennen nennen nn 96 3 Device Configuration 50 7 4 Enhanced Direct Memory Access EDMA3 3 1 Device Configuration at Device Reset 50 25 m 98 3 2 Peripheral Configuration at Device Reset 52 7 9 uu s 112 3 8 Peripheral Selection After Device Reset 53 7 6 ResetOGControllerzc Wayaqa 116 3 4 Device State Control Registers 55 7 7 and PLL1 123 3 5 Device Status Register Description 65 7 8 PLL2 and PLL2 Controller 138 36 JTAG ID JTAGID Register Description 67 7 9 DDR2 Memory 147 3 7 Pullup Pulldown Resistors 67 7 10 External Memory Interface EMIFA 149 3 8 Configuration
5. Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 13 2 McBSP Electrical Data Timing 7 13 2 1 Multichannel Buffered Serial Port McBSP Timing Table 7 59 Timing Requirements for McBSP see Figure 7 52 720 850 NO 1000 UNIT MIN MAX te CKRX Cycle time CLKR X ext 6P 10 2 3 ns tw CKRX Pulse duration CLKR X high or CLKR X low CLKR X ext 0 5tecKrxy 1 ns CLKR int 5 tsu FRH CKRL Setup time external FSR high before CLKR low CLKR ext 14 ns CLKR int 6 th CKRL FRH Hold time external FSR high after CLKR low GLKR ext ns CLKR int 8 7 tsu DRV CKRL Setup time DR valid before CLKR low OLKA ext 09 ns f CLKR int 3 8 th CKRL DRV Hold time DR valid after CLKR low GLKA ext 34 ns CLKX int 9 10 tsu FXH CKXL Setup time external FSX high before CLKX low CLKX ext T3 ns CLKX int 6 11 th CKXL FXH Hold time external FSX high after CLKX low CLKX exi 3 ns 1 CLKRP CLKXP FSRP FSXP 0 If polarity of any of the signals is inverted then the timing references of that signal are also inverted P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 3 Use whichever value is greater Minimum CLKR X cycle times must be met even when CLKR X is generated by an internal clock source The minimum CLKR X cycle times are based on internal logic speed the maximum usable speed may
6. 69 7 11 12C 160 4 System 71 7 12 Host Port Interface HPI Peripheral 166 44 Internal Buses Bridges and Switch Fabrics 71 7 13 Multichannel Buffered Serial Port McBSP 177 42 Data Switch Fabric Connections 79 4 Ethene MAG EMAC lun 43 Configuration Switch 74 205 44 Priority 76 716 Peripheral Component Interconnect PCI 207 5 C64x4 77 717 General Purpose Input Output GPIO E 5 1 77 7 18 IEEE Tigi TAG aa 21 5 2 80 8 Mechanical Data 217 5 3 Bandwidth 80 8 1 Thermal Data 217 5 4 Power Down 81 8 2 Packaging Information a 217 Revision History 218 Submit Documentation Feedback Contents 5 PRODUCT PREVIEW Mal aad TMS32006454 Fixed Point Digital Sig
7. CLKR X needs resync Figure 7 53 FSR Timing When GSYNC 1 182 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 62 Timing Requirements for McBSP as SPI Master or Slave CLKSTP 10b CLKXP 0 see Figure 7 54 720 850 NO 1000 UNIT MASTER SLAVE MIN MAX MIN MAX tsu DRV CKXL Setup time DR valid before CLKX low 12 2 18 ns th CKXL DRV Hold time DR valid after CLKX low 4 5 36P ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 2 For all SPI Slave modes CLKG is programmed as 1 6 of the CPU clock by setting CLKSM CLKGDV 1 Table 7 63 Switching Characteristics Over Recommended O Master or Slave CLKSTP 10b CLKXP ote see Figure 7 54 erating Conditions for McBSP as SPI 720 850 NO PARAMETER 1000 UNIT MASTER SLAVE MIN MAX MIN MAX 1 n CKXL FXL Hold time FSX low after CLKX low T 2 T 3 ns 2 ta FXL CKXH Delay time FSX low to CLKX high L 2 1 3 ns 3 ta CKXH DXV Delay time CLKX high to DX valid 2 4 18P 2 8 30P 17 ns 6 sscotoxw bit rom CLKX ow 1 20 1 3 ns 7 ldis FXH DXHZ r aay 3 18 17 ns 8 laFXL DXV Delay time FSX lo
8. TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 1 1 1 ZTZ GTZ BGA Package Bottom View The TMS320C6454 devices are designed for a package temperature range of 0 C to 90 C commercial temperature range ZTZ GTZ 697 PIN BALL GRID ARRAY BGA PACKAGE BOTTOM VIEW AJ AH AG AF AE AD AC w OOOOOOOOO V OOOOOOOOO U OOOOOOOOO T OOOOOOOOO R OOOOOOOOO P N OOOOOOOOO M OOOOOOOOO L OOOOOOOOO K J H G OOOOOOOOOOOO F E OOOOOOOOOOOO D OOOOOOOOOOOOOOOOOOOOOOOOOOOOO B OOOOOOOOOOOOOOOOOOOOOOOOOOOOO A OOOOOOOOOOOOOOOOOOOOOOOOOOOOO 1 35 7 9 11 13 15 17 19 21 23 25 27 29 2 4 6 8 10 12 14 16 18 20 22 24 26 28 NOTE The ZTZ mechanical package designator represents the version of the GTZ package with lead free balls For more detailed information see the Mechanical Data section of this document Figure 1 1 ZTZ GTZ BGA Package Bottom View 1 2 Description The TMS320C64x DSPs including the TMS320C6454 device are the highest performance fixed point DSP generation in the TMS320C6000 DSP platform The C6454 device is based on the third generation high performance advanced VelociTI M very long instruction word VLIW architecture developed by Texas Instruments making these DSPs an excellent choice for applications including video and telecom infrastructure imaging medical and wireless infrastr
9. 9 AECLKOUT T UN y X Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register AWCC Figure 7 35 AARDY Timing 154 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 6 INSTRUMENTS www ti com 7 10 3 2 Programmable Synchronous Interface Timing 5320 6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 46 Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module see Figure 7 36 NO 720 850 1000 MAX UNIT tsu EDV EKOH Setup time read AEDx valid before AECLKOUT high 2 ns th EKOH EDV Hold time read AEDx valid after AECLKOUT high 1 5 ns Table 7 47 Switching Characteristics Over Recommended Operating Conditions for Programmable Synchronous Interface Cycles for EMIFA Module see Figure 7 36 Figure 7 38 720 850 NO PARAMETER 1000 UNIT MIN MAX 1 la EKOH CEV Delay time AECLKOUT high to ACEx valid 1 3 4 9 ns 2 la EKOH BEV Delay time AECLKOUT high to ABEx valid 4 9 ns 3 ta EKOH BEIV Delay time AECLKOUT high to ABEx invalid 1 3 ns 4 la EKOH EAV Delay time AECLKOUT high to AEAx valid 4 9 ns 5 ty EKOH EAIV Delay time AECLKOUT high to AEAx invalid 1 3 ns 8 la
10. 4 T Vss CVpp Vss CVpp Vss 11 AEA3 SYSCLKOUT T CFGGP2 _EN AEA14 R Vss CVpp Vss DVpp33 Vss _ 12 AHOLD ASRE LENDIAN WIDTH 16 17 18 19 20 21 22 23 24 25 _ 207 328 29 MM MM Figure 2 3 C6454 Pin Map Bottom View Quadrant B Submit Documentation Feedback Device Overview 15 PRODUCT PREVIEW MalAddd TMS320C6454 49 Texas Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 16 17 18 19 20 21 22 23 8 amp 28 _ _ 27 28 29 AEA16 AEA15 P 8 Vss CVpp Vss CVop RSV30 RSV31 BOOT AECLKIN DVpps3 Vss MODEO _SEL AEA19 N CVpp Vss CVpp Vss Vss DVpp33 BOOT AHOLDA AEA7 CLKIN1 AECLKIN N MODE3 AEA10 AEA9 M V CV V M SS CVpp Vss DD 55 MACSEL1 Vss MACSELO DVpp33 Vss AEA17 AEA18 L CVpp Vss CVpp Vss Vss DVppss BOOT BOOT ABUSREQ ABE4 ABES L MODE1 MODE2 i DVpp33 Vss AED33 ABE6 AED32 AED34 AARDY K J Vss DVppa3 AED38 AED46 AED44 AED42 AED40 J H DVpp33 Vss AED47 AED45 AED43 DVDD33 Vss H G Vss DVpp18 Vss DVpp18 Vss DVppie Vss DVDp18 AED55 AED54 AED50 AED48 AED35 G F T DSDDQ F 55 DVpp18 RSV19 Vss aes Vss DVpp18 Vss AED63 AED36 AED56 AED52 AED37 E DSDDQ E DEO
11. TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 6 7 Reset Electrical Data Timing NOTE If a configuration pin must be routed out from the device and 3 stated not driven the internal pullup pulldown IPU IPD resistor should not be relied upon TI recommends the use of an external pullup pulldown resistor For more detailed information on pullup pulldown resistors and situations where external pullup pulldown resistors are required see Section 3 7 Pullup Pulldown Resistors Table 7 14 Timing Requirements for Reset Figure 7 8 and Figure 7 9 720 850 NO 1000 UNIT MIN MAX twPor Pulse duration POR low 256D 4 ns tw RESET Pulse duration RESET low 24C ns 7 Setup time boot mode and configuration pins valid before POR high or 6P su ooot RESET high ns 8 Hold time boot mode and configuration pins valid after POR high or 6P h boot RESET high 9 ns 1 C 1 CLKIN1 clock frequency in ns 2 D 1 CLKIN2 clock frequency in ns 3 P 1 CPU clock frequency in nanoseconds ns Note that after power on reset and warm reset the CPU frequency is equal to the CLKIN1 frequency divided by three due to the PLL1 controller being reset see Section 7 6 Heset Controller If CLKIN2 is not used tyveon must be measured in terms of CLKIN1 cycles otherwise use CLKIN2 cycles 5 AEA 19 0 ABA 1
12. Input k 2 649 3 je 5 MRXD1 MRXDO N63 00 69 06 04 93 03 648 03 98 64 9804 98 64 99 MCRSDV OY OY rrr RIC ASA MRXER Inputs Figure 7 67 EMAC Receive Interface Timing RMII Operation Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 199 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 14 3 3 EMAC RGMII Electrical Data Timing An extra clock signal RGREFCLK running at 125 MHz is included as a convenience to the user Note that this reference clock is not a free running clock This should only be used by an external device if it does not expect a valid clock during device reset Table 7 84 Switching Characteristics Over Recommended Operating Conditions for EMAC RGREFCLK RGMII Operation see Figure 7 68 720 NO PARAMETER pod UNIT MIN MAX 1 to RGFCLK Cycle time RGREFCLK 8 0 8 8 0 8 ns 2 tw RGFCLKH Pulse duration RGREFCLK high 3 2 4 8 ns 3 tw RGFCLKL Pulse duration RGREFCLK low 3 2 4 8 ns 4 tyRGFCLK Transition time RGREFCLK 0 75 ns 1 gt 4 ME ce X RM XC Nx Output k 3 4 le Figure 7 68 RGREFCLK Timing Table 7 85 Timing Requirements for RXC RGMII Operat
13. HEX ADDRESS RANGE ACRONYM REGISTER NAME 02 8 0648 TX2CP E Channel 2 Completion Pointer Interrupt Acknowledge egister 02C8 064C TX3CP Moro Channel 3 Completion Pointer Interrupt Acknowledge egister 02C8 0650 TX4CP sa sa Channel 4 Completion Pointer Interrupt Acknowledge egister 02C8 0654 TX5CP 2 Channel 5 Completion Pointer Interrupt Acknowledge egister 02C8 0658 TX6CP 2 Channel 6 Completion Pointer Interrupt Acknowledge egister 02C8 065C TX7CP Channel 7 Completion Pointer Interrupt Acknowledge egister 02C8 0660 RXOCP 2 Channel 0 Completion Pointer Interrupt Acknowledge egister 02C8 0664 RX1CP 5 Channel 1 Completion Pointer Interrupt Acknowledge egister 02C8 0668 RX2CP Channel 2 Completion Pointer Interrupt Acknowledge egister 02C8 066C RX3CP s Channel 3 Completion Pointer Interrupt Acknowledge egister 02C8 0670 RX4CP Channel 4 Completion Pointer Interrupt Acknowledge egister 02C8 0674 RX5CP Ba Channel 5 Completion Pointer Interrupt Acknowledge egister 02C8 0678 RX6CP 1 Channel 6 Completion Pointer Interrupt Acknowledge egister 02C8 067C RX7CP Receive Channel 7 Completion Pointer Interrupt Acknowledge Register 02C8 0680 02C8 06 Reserved 02C8 0700 02C8 077C Reserved was State RAM Test Access Registers Processor Read and Write Access to Head Descriptor Pointers and Interrupt Acknowledge Registers 02C8 0780 02C8 OFFF Reser
14. input Pt gt 14 38 4 3 5 la 35 P ole 5 4 HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed information on the HPI peripheral see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 Figure 7 50 HPI32 Write Timing HAS Not Used Tied High Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 175 PRODUCT PREVIEW Mal aad TMS320C6454 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 10 HAS input X e 9 11 4 HCNTL 1 0 input HR W input gt 9 4 13 HSTROBE X f input 4 7 HCS input 4 18 4 17 HD 31 0 input IZ MI 4 35 kasa 4 38 4 36 Es SN 5 HRDY output Y N HSTROBE refers to the following logical operation on 5 HDS1 and HDS2 NOT HDST HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPID with auto incrementi
15. 720 850 NO PARAMETER 1000 UNIT MIN MAX tw GPOH Pulse duration GPOx high 36P 8 ns 4 Pulse duration GPOx low 36P 82 ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 2 This parameter value should not be used as a maximum performance specification Actual performance of back to back accesses of the GPIO is dependent upon internal bus activity i 2 4 E XLI 4 y 7 GPIx 4 gt 2 GPOx N Figure 7 74 GPIO Port Timing Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 215 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 18 IEEE 1149 1 JTAG 7 18 1 JTAG Device Specific Information 7 18 1 1 IEEE 1149 1 JTAG Compatibility Statement For maximum reliability the C6454 DSP includes an internal pulldown IPD on the TRST pin to ensure that IRST will always be asserted upon power up and the DSP s internal emulation logic will always be properly initialized when this pin is not routed out JTAG controllers from Texas Instruments actively drive TRST high However some third party JTAG controllers may not drive TRST high but expect the use of an external pullup resistor on TRST When using this type of JTAG controller assert TRST to initialize the DSP
16. 4 MES AEA IS OYABA I X EA2 X EAS X X AED 63 0 Gi X Q X 03 X Q wl 8 prm 8 ASADS ASRE B 4 jo k 9 KS 9 AAOE ASOE B AAWE ASWEB OCO The following parameters are programmable via the EMIFA Chip Select n Configuration Register CESECn Read latency R_LTNCY 1 2 or 3 cycle read latency Write latency W_LTNCY 0 1 2 or 3 cycle read latency ACEx assertion length EXT For standard SBSRAM or ZBT SRAM interface ACEx goes inactive after the final command has been issued CE_EXT 0 For synchronous FIFO interface ACEx is active when ASOE is active CE_EXT 1 Function of ASADS ASRE ENABLE For standard SBSRAM ZBT SRAM interface ASADS ASRE acts as ASADS with deselect cycles R_ENABLE 0 For FIFO interface ASADS ASRE acts as SRE with NO deselect cycles R_ENABLE 1 In this figure LTNCY 2 CE EXT 0 ENABLE 0 and SSEL 1 AAOE ASOE and AAWE ASWE operate as ASOE and ASWE respectively during programmable synchronous interface accesses Figure 7 36 Programmable Synchronous Interface Read Timing for EMIFA With Read Latency 2 AECLKOUT NV A A Xy X 1 gt _ 1 1 MEE k 2 e 3 ABE ZTO BE X BE X BE X BEA X A la 5 AEA 19 0 ABA 1 0 ERE ERO X ER X EZ E s L 11 AED 63 0
17. Reserved Table 7 5 EDMA3 Parameter RAM HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 4000 02A0 401F Parameter Set 0 02A0 4020 02A0 403F Parameter Set 1 02A0 4040 02A0 405F Parameter Set 2 02A0 4060 02A0 407F Parameter Set 3 02A0 4080 02A0 409F Parameter Set 4 02A0 40A0 02A0 40BF Parameter Set 5 02A0 40 0 02 0 40DF Parameter Set 6 02A0 40 0 02 0 40FF Parameter Set 7 02A0 4100 02A0 411F Parameter Set 8 02A0 4120 02A0 413F Parameter Set 9 1 entry Submit Documentation Feedback The C6454 device has 256 EDMAS parameter sets total Each parameter set can be used as a DMA entry a QDMA entry or a link C64x Peripheral Information and Electrical Specifications 105 PRODUCT PREVIEW Mal aad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 5 EDMA3 Parameter RAM continued 6 INSTRUMENTS www ti com HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 47E0 02 0 47 Parameter Set 63 02A0 4800 02 0 481F Parameter Set 64 02A0 4820 02 0 483F Parameter Set 65 02A0 5FCO 02A0 5FDF Parameter Set 254 02A0 5FEO 02A0 5 Parameter Set 255 Table 7 6 EDMA3 Transfer Controller 0 Registers
18. Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 207 PRODUCT PREVIEW Mal aad TMS320C6454 43 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 16 2 PCI Peripheral Register Description s Table 7 97 PCI Configuration Registers 9 2 ACRONYM PCI HOST ACCESS REGISTER NAME 0x00 PCIVENDEV Vendor ID Device ID 0x04 PCICSR Command Status 0x08 PCICLREV Class Code Revision ID 0x0C PCICLINE BIST Header Type Latency Timer Cacheline Size 0x10 PCIBARO Base Address 0 0x14 PCIBAR1 Base Address 1 0x18 PCIBAR2 Base Address 2 0x1C Base Address 3 0x20 PCIBAR4 Base Address 4 0x24 5 Base Address 5 0x28 0x2B Reserved 0x2C PCISUBID Subsystem Vendor ID Subsystem ID 0x30 Reserved 0x34 PCICPBPTR Capabilities Pointer 0x38 Ox3B Reserved 0x3C PCILGINT Max Latency Min Grant Interrupt Pin Interrupt Line 0x40 Ox7F Reserved 208 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS 5320 6454 INSTRUMENTS Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 98 PCI Back End Configuration Registers HEX ADDRESS LANGE AC
19. HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed information on the HPI peripheral see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 Figure 7 47 16 Write Timing HAS Used 172 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor SPRS311A APRIL 2006 C REVISED DECEMBER 2006 www ti com HAS input 8 lt 16 HCNTLI1 0 input O E HR W input na Ha 13 gt HSTROBE input lt 37 HCS input lt 1 3 lt oup AF gt 4 HRDY output HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed information on the HPI peripheral see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 Figure 7 48 HPI32 Read Timing HAS Not Used Tied High Submit Documentation Feedback C64x Peripheral Inf
20. 0 CLKRO FSR DRO 0 A These HPI pins are muxed with the PCI peripheral By default these pins function as HPI When the HPI is enabled the number of HPI pins used depends on the HPI configuration 116 or 2 For more details on these muxed pins see the Device Configuration section of this document B These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins For more details see the Device Configuration section of this document Figure 2 9 HPI McBSP I2C Peripheral Signals Submit Documentation Feedback Device Overview 21 PRODUCT PREVIEW Mal aad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 MTXD 7 2 MTXD 1 0 RMTXD 1 0 RGTXD 3 0 MRXD 7 2 MRXD 1 0 RMRXD 1 0 RGRXDJ 3 0 MRXER RMRXER MRXDV MCRS RMCRSDV MCOL MTXEN RMTXEN RGTXCTL RGRXCTL MTCLK RMREFCLK MRCLK GMTCLK RGTXC RGRXC RGREFCLK Ethernet MAC EMAC Transmit RMII GMII RGMII A Receive RMII GMII RGMII A Error Detect and Control RMII GMII RGMII A Ethernet MAC EMAC and MDIO Input Output RMII GMII RGMII A A ROGMII signals are mutually exclusive to all other EMAC signals 6 I
21. PLL2 and PLL2 Controller D SBSRAM L1P Cache Direct Mapped 32 32K Bytes Bytes E ZBT SRAM ROM FLASH Devices C64x DSP Core Instruction Fetch Control Registers McBSPO SPLOOP Buffer Instruction Dispatch Instruction w N Decode In Circuit Emulation Data Path A Data Path B McBSP1 A i HPI 32 16 B P PCI66 B J EMAC 10 100 1000 MII RMII GMII RMGII MDIO Power Control A Register File B Register File A31 A16 B31 B16 15 0 Interrupt and Exception Controller Systema Internal DMA IDMA o s 8 o o o gt L1D Cache 2 Way PLL1 and Device PLL1 Configuration GPIO16 Set Associative ee 32K Bytes Total 12 Controller Logic LO Switched Central LO Resource Boot Configuration A McBSPs Framing Chips H 100 MVIP SCSA 1 E1 AC97 Devices SPI Devices Codecs B The PCI peripheral pins are muxed with some of the HPI peripheral pins For more detailed information see the Device Configuration section of this document C Each of the TIMER peripherals TIMER1 and TIMERO is configurable as either two 64 bit general purpose timers or two 32 bit general purpose timers or a watchdog timer D The PLL2 controller also generates clocks for the EMAC E Whe
22. LD2a Even Odd register register file B file B B0 B2 B1 B3 B4 B30 B5 B31 LD2b Data path B ST2a lt ST2b 4 On M unit dst2 is 32 MSB On M unit dst1 is 32 LSB oom Control Register On C64x CPU M unit src2 is 32 bits on C64x CPU M unit src2 is 64 bits On L and S units odd dst connects to odd register files and even dst connects to even register files Figure 2 1 TMS320C64x CPU DSP Core Data Paths Submit Documentation Feedback Device Overview 9 PRODUCT PREVIEW MalAddd TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 2 3 Memory Map Summary Table 2 2 shows the memory map address ranges of the C6454 device The external memory configuration register address ranges in the C6454 device begin at the hex address location 0x7000 0000 for EMIFA and hex address location 0x7800 0000 for DDR2 Memory Controller Table 2 2 C6454 Memory Map Summary MEMORY BLOCK DESCRIPTION BLOCK SIZE BYTES HEX ADDRESS RANGE Reserved 1024K 0000 0000 000F FFFF Internal ROM 32K 0010 0000 0010 7FFF Reserved 7M 32K 0010 8000 007F FFFF Internal RAM L2 L2 SRAM 1 0080 0000 008F FFFF Reserved 5M 0090 0000 OO
23. SYSCLKOUT EN PCI 2 EEPROM Auto Initialization PCI EEAI T27 AEAS PCI auto initialization via external 2 EEPROM AEA2 CFGGP2 T26 Eo peripheral is disabled PCI EN pin 0 this pin must not be AEA1 CFGGP1 U26 0 PCI auto initialization through 2 EEPROM is disabled default 1 PCI auto initialization through I2C EEPROM is enabled PCI Frequency Selection PCI66 The PCI peripheral needs be enabled PCI EN 1 to use this function Selects the PCI operating frequency of 66 MHz or 33 MHz PCI operating frequency is selected at reset via the pullup pulldown resistor on the PCI66 pin AEA6 0 2 IPD 0 PCI operates at 33 MHz default 1 PCI operates at 66 MHz Note If the PCI peripheral is disabled PCI EN 0 this pin must not be pulled up McBSP1 Enable bit MCBSP1 EN Selects which function is enabled on the McBSP1 GPIO muxed pins AEA5 AEA0 CFGGPO U25 0 GPIO pin functions enabled default 1 McBSP1 pin functions enabled SYSCLKOUT Enable bit SYSCLKOUT_EN Selects which function is enabled on the SYSCLK4 GP 1 muxed pin 4 0 GP 1 pin function of the SYSCLK4 GP 1 pin enabled default 1 SYSCLKA pin function of the SYSCLK4 GP 1 pin enabled Configuration GPI CFGGP 2 0 AEA 2 0 These pins are latched during reset and their values are shown in the DEVSTAT register These values can be used by software routines for boot operations For proper C6454 devic
24. 02 0 403C 02 0 405 Reserved 02 0 4060 02B3 407F Reserved 02 0 4080 02B3 FFFF Reserved 162 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 7 11 3 12 Electrical Data Timing 7 11 3 1 Inter Integrated Circuits I2C Timing Table 7 52 Timing Requirements for I2C Timings see Figure 7 42 720 850 NO am UNIT STANDARD MODE FAST MODE MIN MAX MIN MAX 1 ic scL Cycle time SCL 10 2 5 us AMNES SD 3 M after SDA low for a 4 06 T peated START condition 4 lu scLL Pulse duration SCL low 4 7 1 3 us 5 tw SCLH Pulse duration SCL high 4 0 6 us 6 tsu SDAV SDLH Setup time SDA valid before SCL high 250 10000 ns 7 aen bus E valid after SCL low For PC 0 0 09 us Pulse duration SDA high between STOP and 8 twspaH START 47 1 3 us conditions LJ 9 SDA Rise time SDA 1000 20 0 1049 300 ns gt 10 tscL Rise time SCL 1000 20 0 1049 300 ns LLI 11 Fall time SDA 300 20 0 16 300 ns 12 Fall time SCL 300 20 0 1005 300 ns 13 EE 1 high before SDA high for 4 06 us T 14 tw SP Pulse duration spike must be suppressed 0 50 ns 5 15 C Capacitive load for each bus l
25. 2 1 CPU clock frequency in ns For example when running parts at 1000 MHz use 1 ns For all SPI Slave modes CLKG is programmed as 1 6 of the CPU clock by setting CLKSM CLKGDV 1 Table 7 69 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave CLKSTP 11b CLKXP 1 see Figure 7 57 720 850 NO PARAMETER 1000 UNIT MASTER SLAVE MIN MAX MIN MAX 1 n CKXH FXL Hold time FSX low after CLKX high 4 H 2 H 3 ns 2 la FXL CKXL Delay time FSX low to CLKX low 9 T 2 T 1 ns 3 ta CKXH DXV Delay time CLKX high to DX valid 2 4 18P 2 8 30P 17 ns 6 ldis CKXH DXHZ a following 2 4 18 17 ns 7 la FxL DXV Delay time FSX low to DX valid L 2 L 4 12P 2 24 17 ns 186 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns For all SPI Slave modes CLKG is programmed as 1 6 of the CPU clock by setting CLKSM CLKGDV 1 S Sample rate generator input clock 6P if CLKSM 1 P 1 CPU clock frequency S Sample rate generator input clock P_clks if CLKSM 0 P_clks CLKS period T CLKX period 1 CLKGDV S CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd L CLKX low pulse width CLKGDV 2 S if CLKGDV is even L CLKGDV 1 2 S if CLKGDV is odd FSRP FSXP 1 As a SPI Master
26. Linking mechanism allows for ping pong buffering circular buffering and repetitive continuous transfers all with no CPU intervention Chaining allows multiple transfers to execute with one event e 256 PaRAM entries Used to define transfer context for channels Each PaRAM entry can be used as a DMA entry QDMA entry or link entry 64 channels Manually triggered CPU writes to channel controller register external event triggered and chain triggered completion of one transfer triggers another 8 Quick channels Used for software driven transfers Triggered upon writing to a single PaRAM set entry e 4 transfer controllers event queues with programmable system level priority e Interrupt generation for transfer completion and error conditions e Memory protection support Active memory protection for accesses to PaRAM and registers Debug visibility Queue watermarking threshold allows detection of maximum usage of event queues Error and status recording to facilitate debug Each of the transfer controllers has a direct connection to the switched central resource SCR Table 4 1 lists the peripherals that can be accessed by the transfer controllers EDMAS Device Specific Information interrupt must be generated at the end of an or PCI boot operation to begin execution of the loaded application Since the DSP interrupt generated by the HPI and PCI is mapped to the
27. Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Low Power Wireless www ti com lpw Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2007 Texas Instruments Incorporated
28. REVISED DECEMBER 2006 7 10 4 HOLD HOLDA Timing 3 TEXAS www ti com Table 7 48 Timing Requirements for the HOLD HOLDA Cycles for EMIFA Module see Figure 7 39 720 850 NO 1000 UNIT MIN MAX 3 th HOLDAL HOLDL Hold time HOLD low after HOLDA low E ns 1 EMIF input clock period in ns for EMIFA Table 7 49 Switching Characteristics Over Recommended Operating Conditions for the HOLD HOLDA Cycles for EMIFA Module see Figure 7 39 720 850 NO PARAMETER 1000 UNIT MIN MAX 1 ta HOLDL EMHZ Delay time HOLD low to EMIFA Bus high impedance 2E 2 ta EMHZ HOLDAL Delay time EMIF Bus high impedance to HOLDA low 0 2E ns 4 ta HOLDH EMLZ Delay time HOLD high to EMIF Bus low impedance 2 7E ns 5 ta EMLZ HOLDAH Delay time EMIFA Bus low impedance to HOLDA high 0 2 ns 1 EMIF input clock period in ns for EMIFA 2 EMIFA Bus consists of ACE 5 2 ABE 7 0 AED 63 0 AEA 19 0 ABA 1 0 ARW ASADS ASRE AAOE ASOE and AAWE ASWE 3 All pending EMIF transactions are allowed to complete before HOLDA is asserted If no bus transactions are occurring then the minimum delay time can be achieved 158 EMIF Bus AECLKOUT External Requestor Owns Bus DSP Owns Bus 3 gt DSP Owns Bus NE EMIFA Bus consists of ACE 5 2 ABE 7 0 AED 63 0 AEA 19 0
29. 02A2 8254 SAMPPRXY Source Active Memory Protection Proxy Register 02A2 8258 SACNTRLD Source Active Count Reload Register 02A2 825C SASRCBREF _ Source Active Source Address B Reference Register 02A2 8260 SADSTBREF Source Active Destination Address B Reference Register 02A2 8264 02A2 827C Reserved 02A2 8280 DFCNTRLD Destination FIFO Set Count Reload Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 107 PRODUCT PREVIEW Mal aad L9naoad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com Table 7 7 EDMA3 Transfer Controller 1 Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A2 8284 DFSRCBREF _ Destination FIFO Set Destination Address Reference Register 02A2 8288 DFDSTBREF Destination FIFO Set Destination Address B Reference Register 02A2 828C 02A2 82FC Reserved 02A2 8300 DFOPTO Destination FIFO Options Register 0 02A2 8304 DFSRCO Destination FIFO Source Address Register 0 02A2 8308 DFCNTO Destination FIFO Count Register 0 02A2 830C DFDSTO Destination FIFO Destination Address Register 0 02A2 8310 DFBIDXO Destination FIFO BIDX Register 0 02A2 8314 DFMPPRXYO Destination FIFO Memory Protection Proxy Register 0 02A2 8318 02A2 833C Reserved 02A2 8340 DFOPT1 Destination FIF
30. 6 INSTRUMENTS www ti com Table 2 3 Terminal Functions continued SIGNAL TYPE IPD IPU DESCRIPTION NAME NO MULTICHANNEL BUFFERED SERIAL PORT 1 AND MULTICHANNEL BUFFERED SERIAL PORT 0 McBSP1 and McBSPO cus ONER N undi MULTICHANNEL BUFFERED SERIAL PORT 1 McBSP1 CLKR1 GP 0 AF4 VO Z IPD McBSP 1 receive clock 2 or GP 0 I O Z default FSR1 GP 10 AE5 VO Z IPD McBSP1 receive frame sync I O Z or GP 10 I O Z default DR1 GP 8 AH5 VO Z IPD McBSP1 receive data 1 or GP 8 1 0 2 default DX1 GP 9 AG5 VO Z IPD McBSP1 transmit data 0 2 or GP 9 0 2 default FSX1 GP 11 AG4 VO Z IPD McBSP1 transmit frame sync 1 0 2 or GP 11 I O Z default CLKX1 GP 3 AF5 VO Z IPD McBSP1 transmit clock 1 0 2 or GP 3 1 0 2 default MULTICHANNEL BUFFERED SERIAL PORT 0 McBSPO CLKRO AG1 VO Z IPU McBSPO receive clock 2 FSRO AH3 VO Z IPD McBSPO receive frame sync 2 DRO AJ5 IPD McBSPO receive data I 6 VO Z IPD McBSPO transmit data O Z 5 0 AJ3 VO Z IPD McBSPO transmit frame sync 0 2 CLKXO AG6 VO Z IPU McBSPO transmit clock I O Z MANAGEMENT DATA INPUT OUTPUT MDIO FOR MII RMII GMII MDCLK M5 VO Z IPD MDIO serial clock MDCLK for MII RMII RGMII mode MDIO N3 VO Z IPU MDIO serial data MDIO for MII RMII RGMII mode I O MANAGEMENT DATA INPUT OUTPUT MDIO FOR RGMII RGMDCLK B4 O Z MDIO serial clock for RGM
31. C G 8 8 ASADS ASRE SOSS S F AAOE ASOE 12 AAWE ASWE EE EES The following parameters are programmable via the EMIFA Chip Select n Configuration Register CESECn Read latency R_LTNCY 1 3 or 3 cycle read latency Write latency W_LTNCY 0 1 2 or 3 cycle read latency ACEx assertion length standard SBSRAM or ZBT SRAM interface goes inactive after the final command has been issued CE_EXT 0 For synchronous FIFO interface ACEx is active when ASOE is active CE_EXT 1 Function of ASADS ASRE ENABLE For standard SBSRAM or ZBT SRAM interface ASADS ASRE acts as ASADS with deselect cycles R ENABLE 0 For FIFO interface ASADS ASRE acts as SRE with NO deselect cycles R ENABLE 1 In this figure W_LTNCY 0 CE EXT 0 R ENABLE 0 and SSEL 1 AAOE ASOE AAWE ASWE operate as ASOE and ASWE respectively during programmable synchronous interface accesses Figure 7 37 Programmable Synchronous Interface Write Timing for EMIFA With Write Latency 0 156 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 249 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 Write Latency 1 8 OA XA AXA A f N f N N 1 1 fT st 2 3 ABE
32. DR1 CLKS1 Did ipse cued McBSP1 and PLL2 CLKIN2 PLLV2 Controller CLKRO FSRO DRO CLKSO TINP1L FSX0 CLKXO McBSPO TIMER1 TOUTIL 7 0 MRXER MRXDV MCOL B TINPO MCRS MTCLK MRCLK TIMERO MTXD 7 0 MTXEN SCL MDIO MDCLK SDA Shading denotes a peripheral module not available for this configuration DEVSTAT Register 0x0061 C161 PCI EN 0 PCI disabled default 1 EMIFA EN 1 EMIFA enabled ABAO DDR2 EN 1 DDR2 Memory Controller enabled AEA 19 16 BOOTMODE 3 0 0001 HPI Boot AEA 8 PCI_EEAI 0 PCI I2C EEPROM Auto Init disabled default AEA 15 AECLKIN SEL 0 AECLKIN default AEA 7 0 do not oppose IPD AEA 14 WIDTH 1 HPI 32 bit Operation 6 PCI66 0 PCI 33 MHz default don t care AEA 13 LENDIAN IPU Little Endian Mode default AEA 5 MCBSP1 1 McBSP1 enabled AEA 12 0 do not oppose IPD AEA 4 SYSCLKOUT_EN 1 SYSCLK4 pin function AEA 11 0 do not oppose IPD AEA 3 0 do not oppose IPD AEA 10 9 MACSEL 1 0 00 10 100 MII Mode AEA 2 0 CFGGP 2 0 000 default Figure 3 13 Configuration Example B 2 McBSPs 2 2 EMIFA DDR2 Memory Controller TIMERS EMAC GMII MDIO 70 Device Configuration Submit Documentation Feedback Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006
33. Divide frequency by 5 Others Reserved Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 141 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 8 3 2 PLL Controller Command Register The PLL controller command register PLLCMD contains the command bit for GO operation PLLCMD is shown in Figure 7 25 and described in Table 7 34 31 16 Reserved R 0 15 2 1 0 Reserved Rsvd GOSET R 0 R W 0 R W 0 LEGEND R W Read Write Read only n value after reset Figure 7 25 PLL Controller Command Register PLLCMD Hex Address 029C 0138 Table 7 34 PLL Controller Command Register PLLCMD Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 1 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 GOSET GO operation command for SYSCLK rate change and phase alignment Before setting this bit to 1 to initiate a GO operation check the GOSTAT bit in the PLLSTAT register to ensure all previous GO operations have completed 0 No effect Write of 0 clears bit to 0 Initiates GO operation Write of 1 initiates GO operation Once set GOSET remains set bu
34. Do not use 112 Reserved Reserved Do not use 113 ED1 single bit error detected during DMA read 114 115 Reserved Reserved Do not use 116 L2_ED1 L2 single bit error detected 117 L2_ED2 L2 two bit error detected 118 PDC_INT Powerdown sleep interrupt 119 Reserved Reserved Do not use 120 L1P_CMPA L1P CPU memory protection fault 121 DMPA L1P DMA memory protection fault 122 L1D CMPA L1D CPU memory protection fault 123 L1D DMPA L1D DMA memory protection fault 124 L2 CMPA L2 CPU memory protection fault Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 113 PRODUCT PREVIEW Mal aad TMS32006454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 10 C6454 DSP Interrupts continued 6 INSTRUMENTS www ti com EVENT NUMBER INTERRUPT EVENT INTERRUPT SOURCE 125 L2_DMPA L2 DMA memory protection fault 126 IDMA_CMPA IDMA CPU memory protection fault 127 IDMA_BUSERR IDMA bus error interrupt 114 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 7 5 2 External Interrupts Electrical Data Timing Table 7 11 Timing Requirements for External Interrupts see Figure 7 6 720 850
35. NO 1000 UNIT MIN MAX tw NMIL Width of the NMI interrupt pulse low 6P ns 2 tw NMIH Width of the NMI interrupt pulse high 6P ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use 1 ns m NL Figure 7 6 NMI Interrupt Timing Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 115 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 6 Reset Controller The reset controller detects the different type of resets supported on the C6454 device and manages the distribution of those resets throughout the device The C6454 device has several types of resets power on reset warm reset system reset and CPU reset Table 7 12 explains further the types of reset the reset initiator and the effects of each reset on the chip For more information on the effects of each reset on the PLL controllers and their clocks see Section 7 6 7 Reset Electrical Data Timing Table 7 12 Reset Types TYPE INITIATOR EFFECT s Power on Reset POR pin Resets the entire chip including the test and emulation logic Warm Reset RESET pin Resets everything except for the test and emulation logic and PLL2 Emulator stays alive during Warm Reset A system reset maintains memory contents and does not reset the System Reset Emulator test and e
36. RESET Pin A Warm Reset has the same effects as a Power on Reset except that in this case the test and emulation logic and PLL2 are not reset The following sequence must be followed during a Warm Reset 1 Hold the RESET pin low for a minimum of 24 CLKIN1 cycles Within the minimum 24 CLKIN1 cycles Within the low period of the RESET pin the following happens The 2 group pins low group pins and the high group pins are set to their reset state with one exception The PCI pins are not affected by warm reset if the PCI module was enabled before RESET went low In this case PCI pins stay at whatever their value was before RESET went low The reset signals flow to the entire chip excluding the test and emulation logic resetting modules that use reset asynchronously The PLL1 controller is reset thereby switching back to bypass mode and resetting all its registers to their default values PLL1 is placed in reset and loses lock The PLL1 controller clocks start running at the frequency of the system reference clock The clocks are propagated throughout the chip to reset modules that use reset synchronously The PLL2 controller is reset thereby resetting all its registers to their default values The PLL2 controller clocks start running at the frequency of the system reference clock PLL2 is not reset therefore it remains locked The RESETSTAT pin becomes active low indicating the device is in reset 2 The RESET pi
37. SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 2 3 Terminal Functions continued SIGNAL NAME NO F20 F22 F24 G1 G5 G7 G9 G11 G13 G15 G17 G19 G21 G23 H6 H24 Vss H29 GND Ground pins J7 J23 K2 K6 K24 L7 L11 L13 L15 L17 L19 L23 M6 M12 M14 TYPE IPD IPUO DESCRIPTION Submit Documentation Feedback Device Overview 43 PRODUCT PREVIEW Mal aad TMS32006454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com Table 2 3 Terminal Functions continued SIGNAL NAME NO TYPE IPD IPU 2 DESCRIPTION M16 M18 M24 M26 M29 N2 N13 N15 N17 N19 N23 P7 P12 P14 P16 P18 P29 Vss GND R7 R11 R13 R15 R17 R19 R24 T6 T12 T14 T16 T18 T23 U7 U11 U13 Ground pins 44 Device Overview Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 2 3 Terminal Functions continued SIGNAL NAME NO TYPE IPD IPU 2 DESCRIPTION Vss U15 U17 U19 U24 V2 V6 V12 V14 V
38. collateral is available in the C6000 DSP product folder at www ti com c6000 SPRU732 TMS320C64x C64x DSP CPU and Instruction Set Reference Guide Describes the CPU architecture pipeline instruction set and interrupts for the TMS320C64x and TMS320C64x digital signal processors DSPs of the TMS320C6000 DSP family The C64x C64x DSP generation comprises fixed point devices in the C6000 DSP platform The C64x DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set SPRU862 7 5320 64 DSP Cache User s Guide Explains the fundamentals of memory caches and describes how the two level cache based internal memory architecture in the 5320 64 digital signal processor DSP of the TMS320C6000 DSP family can be efficiently used in DSP applications Shows how to maintain coherence with external memory how to use DMA to reduce memory latencies and how to optimize your code to improve cache efficiency The internal memory architecture in the C64x DSP is organized in a two level hierarchy consisting of a dedicated program cache L1P and a dedicated data cache L1D on the first level Accesses by the CPU to the these first level caches can complete without CPU pipeline stalls If the data requested by the CPU is not contained in cache it is fetched from the next lower memory level L2 or external memory SPRU871 5320 64 DSP Megamodule Reference Guide Describes the TMS320C64x digital signal p
39. good board design practice such delays must always be taken into account Timing values may be adjusted by increasing decreasing such delays recommends utilizing the available I O buffer information specification IBIS models to analyze the timing characteristics correctly To properly use IBIS models to attain accurate timing analysis for a given system see the Using IBIS Models for Timing Analysis application report literature number SPRAS839 If needed external logic hardware such as buffers may be used to compensate any timing differences For inputs timing is most impacted by the round trip propagation delay from the DSP to the external device and from the external device to the DSP This round trip delay tends to negatively impact the input setup time margin but also tends to improve the input hold time margins see Table 7 1 and Figure 7 4 Figure 7 4 represents a general transfer between the DSP and an external device The figure also represents board route delays and how they are perceived by the DSP and the external device Table 7 1 Board Level Timing Example see Figure 7 4 NO DESCRIPTION 1 Clock route delay 2 Minimum DSP hold time 3 Minimum DSP setup time 4 External device hold time requirement 5 External device setup time requirement 6 Control signal route delay 7 External device hold time 8 External device access time 9 DSP hold time requirement 10 DSP se
40. must be set to 0001b at device reset Conversely to use the PCI interface for host boot the PCI EN pin Y29 must be high enabling the PCI peripheral and 3 0 must be set to 0111b at device reset For the HPI host boot the DSP interrupt can be generated through the use of the DSPINT bit in the HPI Control HPIC register For the HPI host boot the CPU is actually held in reset until DSP interrupt is generated by the host The interrupt can be generated through the use of the DSPINT bit in the Control HPIC register Since the CPU is held in reset during HPI host boot it will not respond to emulation software Device Overview Submit Documentation Feedback Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 such as Code Composer Studio For the PCI host boot the CPU is out of reset but it executes an IDLE instruction until a DSP interrupt is generated by the host The host can generate a DSP interrupt through the PCI peripheral by setting the DSPINT bit in the Back End Application Interrupt Enable Set Register PCIBINTSET and the Status Set Register PCISTATSET Note that the HPI host boot is a hardware boot mode while the PCI host boot is a software boot mode If PCI boot is selected the on chip bootloader configures the PLL1 Controller such that CLKIN1 is multiplied by 15 More specifically PLLM is set to OEh x15 and RA
41. 0 7 12 2 HPI Peripheral Register Description s Table 7 54 HPI Control Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0288 0000 Reserved 2 PWREMU has both 0288 0004 PWREMU MGMT power and emulation management register Host CPU read write access 0288 0008 0288 0024 Reserved 0288 0028 Reserved 0288 002C Reserved The Host and the CPU have 0288 0030 HPIC HPI control register read write access to the HPIC register 1 HPIA HPI address register The Host has read write 0288 0034 HPIAW 2 Write access to the HPIA registers HPIA HPI address register The CPU has only read 0288 0038 HPIAR 2 Read access to the HPIA registers 0288 000 028B 007F Reserved 0288 0080 028B FFFF Reserved 1 The CPU can write 1 to the HINT bit to generate an interrupt to the host and it can write 1 to the DSPINT bit to clear acknowledge an interrupt from the host 2 There are two 32 bit HPIA registers HPIAR for read operations and HPIAW for write operations The can be configured such that HPIAR and HPIAW act as a single 32 bit HPIA single HPIA mode or as two separate 32 bit HPIAs dual HPIA mode from the perspective of the host The CPU can access HPIAW and HPIAR independently For details about the HPIA registers and their modes see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 166 64 Peripheral
42. 0 Reserved TIMER1CTL Reserved EMACCTL Reserved R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write n value after reset Figure 3 4 Peripheral Configuration Register 0 PERCFGO 0 02 0008 Table 3 7 Peripheral Configuration Register 0 PERCFGO Field Descriptions Bit Field Value Description 31 21 Reserved Reserved 20 PCICTL Mode control for PCI This bit defaults to 1 when Host boot is used BOOTMODE 3 0 01110 0 Set PCI to disabled mode 1 Set PCI to enabled mode 19 Reserved Reserved 18 HPICTL Mode control for HPI This bit defaults to 1 when Host boot is used BOOTMODE 3 0 00010 0 Set HPI to disabled mode 1 Set HPI to enabled mode 17 Reserved 1 Reserved 16 McBSP1CTL Mode control for McBSP1 0 Set McBSP1 to disabled mode 1 Set McBSP1 to enabled mode 15 Reserved Reserved 14 McBSPOCTL Mode control for McBSPO 0 Set McBSPO to disabled mode 1 Set McBSPO to enabled mode 13 Reserved Reserved Submit Documentation Feedback Device Configuration 57 PRODUCT PREVIEW Mal aad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com Table 3 7 Peripheral Configuration Register 0 PERCFGO Field Descriptions continued Bit Field Value Description 12 I2CCTL Mode control for 2 0 Set 2 to disabled mode 1 Set 2 to enabled mode 11 Reserved Reserved
43. 0284 DFSRCBREF _ Destination FIFO Set Destination Address B Reference Register 02A3 0288 DFDSTBREF Destination FIFO Set Destination Address B Reference Register 02 028 02 02FC Reserved 02A3 0300 DFOPTO Destination FIFO Options Register 0 02A3 0304 DFSRCO Destination FIFO Source Address Register 0 02A3 0308 DFCNTO Destination FIFO Count Register 0 02A3 030C DFDSTO Destination FIFO Destination Address Register 0 02A3 0310 DFBIDXO Destination FIFO BIDX Register 0 02A3 0314 DFMPPRXYO Destination FIFO Memory Protection Proxy Register 0 02A3 0318 02A3 033C Reserved 02A3 0340 DFOPT1 Destination FIFO Options Register 1 02A3 0344 DFSRC1 Destination FIFO Source Address Register 1 02A3 0348 DFCNT1 Destination FIFO Count Register 1 02A3 034C DFDST1 Destination FIFO Destination Address Register 1 02A3 0350 DFBIDX1 Destination FIFO BIDX Register 1 02A3 0354 DFMPPRXY1 Destination FIFO Memory Protection Proxy Register 1 02A3 0358 02A3 037C Reserved 02A3 0380 DFOPT2 Destination FIFO Options Register 2 02A3 0384 DFSRC2 Destination FIFO Source Address Register 2 02A3 0388 DFCNT2 Destination FIFO Count Register 2 02A3 038C DFDST2 Destination FIFO Destination Address Register 2 02A3 0390 DFBIDX2 Destination FIFO BIDX Register 2 02A3 0394 DFMPPRXY2 Destination FIFO Memory Protection Proxy Register 2 02A3 0398 02A3 03BC Reserved 02A3 03C0 DFOPT3 Destination FIFO Options Register 3 02A3 03 4 DFSRC3 Destination FIFO Source Add
44. 0300 DFOPTO Destination FIFO Options Register 0 02A2 0304 DFSRCO Destination FIFO Source Address Register 0 02A2 0308 DFCNTO Destination FIFO Count Register 0 02A2 030C DFDSTO Destination FIFO Destination Address Register 0 02A2 0310 DFBIDXO Destination FIFO BIDX Register 0 02A2 0314 DFMPPRXYO Destination FIFO Memory Protection Proxy Register 0 02A2 0318 02A2 033C Reserved 02A2 0340 DFOPT1 Destination FIFO Options Register 1 02A2 0344 DFSRC1 Destination FIFO Source Address Register 1 106 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6454 Fixed Point Digital Signal Processor ki TEXAS INSTRUMENTS www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 6 EDMA3 Transfer Controller 0 Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A2 0348 DFCNT1 Destination FIFO Count Register 1 02A2 034C DFDST1 Destination FIFO Destination Address Register 1 02A2 0350 DFBIDX1 Destination FIFO BIDX Register 1 02A2 0354 DFMPPRXY1 Destination FIFO Memory Protection Proxy Register 1 02A2 0358 02A2 037C Reserved 02A2 0380 DFOPT2 Destination FIFO Options Register 2 02A2 0384 DFSRC2 Destination FIFO Source Address Register 2 02A2 0388 DFCNT2 Destination FIFO Count Register 2 02A2 038C DFDST2 Destination FIFO Destination Address Register 2 02A2 0390 DFBIDX2 Destination FIFO BIDX Register 2
45. 0350 PCIADDSUB15 PCI Address Substitute 15 Register 02 0 0354 PCIADDSUB16 PCI Address Substitute 16 Register 02 0 0358 PCIADDSUB17 PCI Address Substitute 17 Register 02C0 035C PCIADDSUB18 PCI Address Substitute 18 Register 02 0 0360 PCIADDSUB19 PCI Address Substitute 19 Register 02 0 0364 PCIADDSUB2O PCI Address Substitute 20 Register 02 0 0368 PCIADDSUB 21 PCI Address Substitute 21 Register 02C0 036C PCIADDSUB22 PCI Address Substitute 22 Register 02 0 0370 PCIADDSUB23 PCI Address Substitute 23 Register 02 0 0374 PCIADDSUB24 PCI Address Substitute 24 Register 02 0 0378 PCIADDSUB25 PCI Address Substitute 25 Register 02C0 037C PCIADDSUB26 PCI Address Substitute 26 Register 02 0 0380 PCIADDSUB27 PCI Address Substitute 27 Register 02 0 0384 PCIADDSUB28 PCI Address Substitute 28 Register 02 0 0388 PCIADDSUB29 PCI Address Substitute 29 Register 02 0 038C PCIADDSUB30 PCI Address Substitute 30 Register 02 0 0390 PCIADDSUB31 PCI Address Substitute 31 Register 210 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS 5320 6454 INSTRUMENTS Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 100 PCI Hook Configuration Registers Vi ADDBESS BANGE ACRONYM DSP ACCESS REGISTER NAME 02 0 0394 PCIVENDEVPRG PCI Vendor I
46. 1 0 DED 31 0 DEA 13 0 DSDDQM3 DSDDQM2 DSDDQM1 DSDDQMO Memory Map Space Select External Memory I F ET Byte Enables Memory Map Space Select Bus Arbitration EMIFA 64 bit Data Bus External n Memory Byte Enables DDR2 Memoty Controller 32 bit Data Bus Bank Address A EMIFA ACEO and are not functionally supported on the C6454 device 20 Device Overview Figure 2 8 EMIFA DDR2 Memory Controller Peripheral Signals Texas INSTRUMENTS www ti com AECLKIN AECLKOUT ASWE AAWE AARDY AR W AAOE ASOE ASADS ASRE AHOLD AHOLDA ABUSREQ DDR2CLKOUT DDR2CLKOUT DSDCKE DSDCAS DSDRAS DSDWE DSDDOQS 3 0 DSDDQGS 3 0 DSDDQGATE 0 DSDDQGATE 1 DSDDQGATE 2 DSDDQGATE 3 DEODT 1 0 DBA 2 0 Submit Documentation Feedback Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 HPI A Host Port Interface 32 HD 15 0 AD 15 0 HD 31 16 AD 31 16 HCNTLO PSTOP HCNTL1 PDEVSEL Register Select Control HHWIL PCLK sean 16 ONLY McBSPO CLKX1 GP 3 FSX1 GP 11 DX1 GP 9 CLKR1 GP 0 FSR1 GP 10 DR1 GP 8 CLKS SHARED Multichannel Buffered Serial Ports ihe SCL SDA HAS PPAR HR W PCBE2 HCS PPERR HDS1 PSERR HDS2 PCBE1 HRDY PIRDY HINT PFRAME CLKXO FSX
47. 1 in SPCR if DXENA 0 then D1 D2 0 if DXENA 1 then D1 6P D2 12P 9 Extra delay from FSX high to DX valid applies only to the first data bit of a device if and only if DXENA 1 in SPCR if DXENA 0 then D1 D2 0 if DXENA 1 then D1 6P D2 12P Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 181 PRODUCT PREVIEW Mal aad TMS320C6454 49 Texas Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 CLKS 1 gt le ND A gl CLKR 4 4 le gt 5 5 63 FSR ext pt Tr 8 DR __ X n2 X m3 X 34 3 CLKX ee 9 ke 5 J N 11 10 FSX ext J 1 FSX XDATDLY 00b gt 13 k 12 4 43 A Ein 2 C m3 Xd A Parameter No 13 applies to the first data bit only when XDATDLY z 0 B The CLKS signal is shared by both McBSP0 and McBSP1 on this device Figure 7 52 McBSP Timing Table 7 61 Timing Requirements for FSR When GSYNC 1 see Figure 7 53 720 850 NO 1000 UNIT MIN MAX tsu FRH CKSH Setup time FSR high before CLKS high 4 ns 2 th CKSH FRH Hold time FSR high after CLKS high 4 ns Gs N X Wu XX X Y XL 1 5 FSR external CLKR X need to
48. 1Fh Reserved do not use Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 131 PRODUCT PREVIEW M3l aad TMS320C6454 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 7 3 6 PLL Controller Command Register The PLL controller command register PLLCMD contains the command bit for GO operation PLLCMD is shown in Figure 7 16 and described in Table 7 24 31 16 Reserved R 0 15 2 1 0 Reserved Rsvd GOSET R 0 R W 0 R W 0 LEGEND R W Read Write Read only n value after reset Figure 7 16 PLL Controller Command Register PLLCMD Hex Address 029A 0138 Table 7 24 PLL Controller Command Register PLLCMD Field Descriptions Bit Field Value Description 31 2 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 1 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 GOSET GO operation command for SYSCLK rate change and phase alignment Before setting this bit to 1 to initiate a GO operation check the GOSTAT bit in the PLLSTAT register to ensure all previous GO operations have completed 0 No effect Write of 0 clears bit to 0 Initiates GO operation Write of 1 initiates GO operation Once set GOSET remains set but further wr
49. 2006 JNV A JN AVA JN A V AA AVANA AA V NVA AVNAVJAVA VNA JAVMAA MNVAA AAN A NVAJNVJANAJAV NA JA JAA JA AVAVJAVA JAVAJAVA JMAVAAVA AVAAVA AAA AA A N L 6 9 RESETSTAT EE X X008 08 000808 7 POR I 8 Boot and H M Eh a Device Configuration A RESET should only be used after device has been powered up For more details on the use of the RESET pin see Section 7 6 Reset Controller B A reset signal is generated internally during a Warm Reset This internal reset signal has the same effect as the RESET pin during a Warm Reset C Boot and Device Configurations Inputs during reset include AEA 19 0 ABA 1 0 and PCI EN Figure 7 9 Warm Reset Timing 122 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 7 7 PLL1 and PLL1 Controller The primary PLL controller generates the input clock to the C64x megamodule including the CPU as well as most of the system peripherals such as the multichannel buffered serial ports McBSPs and the external memory interface EMIF As shown in Figure 7 10 the PLL1 controller features a software programmable PLL multiplier controller PLLM
50. AAOE identified under select signals AAWE respectively during asynchronous memory accesses B Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register AWCC Figure 7 33 Asynchronous Memory Read Timing for EMIFA Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 153 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 k Strobe 4 4 1 4 k Hold 1 E ECERKOUTZ N f XY NX N I 11 4 7 ACEx ee 12 Y ABE 7 0 XC Byte Enables _ 11 E 12 AEA 19 0 1 0 u _ 12 AED 63 0 Write 5 E 13 4 AAWE ASWEU a 11 4 f 12 ARAW AA _ 5 A AAOE ASOE and AAWE ASWE operate as AAOE identified under select signals and AAWE respectively during asynchronous memory accesses Polarity of the AARDY signal is programmable through the AP field of the EMIFA Async Wait Cycle Configuration register AWCC Figure 7 34 Asynchronous Memory Write Timing for EMIFA f Strobe 7 f 34 Strobe 99 2 k Extended Strobe I Hold 2 4
51. APRIL 2006 REVISED DECEMBER 2006 220 C6454 Revision History continued SEE ADDITIONS MODIFICATIONS DELETIONS Section 7 7 3 Section 7 7 4 Section 7 8 Section 7 8 1 Section 7 8 1 1 Section 7 8 4 Section 7 9 Section 7 10 2 Section 7 10 3 Section 7 12 2 Section 7 12 3 Section 7 13 1 Section 7 13 2 Section 7 14 1 Section 7 14 2 Section 7 14 3 1 Section 7 14 3 2 PLL1 Controller Register Descriptions Added Values and Descriptions for RATIO bit field in Table 7 21 PLL Pre Divider Control Register PREDIV Field Descriptions Deleted PLL Controller Divider Registers section Added new sections for PLL Controller Divider 4 Register and PLL Controller Divider 5 Register Change RATIO bit field reset to R W 3 in Figure 7 14 PLL Controller Divider 4 Register PLLDIV4 Changed RATIO bit field reset to R W 3 in Figure 7 15 PLL Controller Divider 5 Register PLLDIV5 PLL1 Controller Input and Output Clock Electrical Data Timing Updated Figure 7 22 SYSCLK4 Timing PLL2 and PLL2 Controller Updated Notes A and B on Figure 7 23 PLL2 Block Diagram PLL2 Controller Device Specific Information Updated Footnote 1 in Table 7 31 PLL2 Clock Frequency Ranges Internal Clocks and Maximum Operating Frequencies Updated paragraphs PLL2 Controller Input Clock Electrical Data Timing Updated Footnote 3 in Table 7 39 Timing Requirements for CLKIN2 DDR2 Memory Controller Updated paragr
52. Channel 0 Source Address Register 0182 000C IDMAODST IDMA Channel 0 Destination Address Register 0182 0010 IDMAOCNT IDMA Channel 0 Count Register 0182 0014 0182 O0FC Reserved 0182 0100 IDMA1STAT IDMA Channel 1 Status Register 0182 0104 Reserved 0182 0108 IMDA1SRC IDMA Channel 1 Source Address Register 0182 010C IDMA1DST IDMA Channel 1 Destination Address Register 0182 0110 IDMA1CNT IDMA Channel 1 Count Register 0182 0114 0182 017C Reserved 0182 0180 2 Reserved 0182 0184 0182 01FF Reserved 84 C64x Megamodule Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS www ti com Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 5 8 Megamodule Cache Configuration Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 0000 L2CFG L2 Cache Configuration Register 0184 0004 0184 001F Reserved 0184 0020 L1PCFG L1P Configuration Register 0184 0024 L1PCC L1P Cache Control Register 0184 0028 0184 003F Reserved 0184 0040 L1DCFG L1D Configuration Register 0184 0044 L1DCC L1D Cache Control Register 0184 0048 0184 OFFF Reserved 0184 1000 0184 104F See Table 5 10 CPU Megamodule Bandwidth Management Registers 0184 1050 0184 SFFF Reserved 0184 4000 L2WBAR L2 Writeback Base Address Register for Block Writebacks 0184 4004 L2WWC
53. Documentation Feedback C64x Peripheral Information and Electrical Specifications 101 PRODUCT PREVIEW Mal aad L9naoad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 4 EDMA3 Channel Controller Registers continued 6 INSTRUMENTS www ti com HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 0300 EMR Event Missed Register 02A0 0304 EMRH Event MissedRegister High 02A0 0308 EMCR Event Missed Clear Register 02A0 030C EMCRH Event Missed Clear Register High 02A0 0310 QEMR QDMA Event Missed Register 02A0 0314 QEMCR QDMA Event Missed Clear Register 02A0 0318 CCERR EDMASCC Error Register 02A0 031C CCERRCLR EDMASCC Error Clear Register 02A0 0320 EEVAL Error Evaluate Register 02A0 0324 02A0 033C Reserved 02A0 0340 DRAEO DMA Region Access Enable Register for Region 0 02A0 0344 DRAEHO DMA Region Access Enable Register High for Region 0 02A0 0348 DRAE1 DMA Region Access Enable Register for Region 1 02A0 034C DRAEH1 DMA Region Access Enable Register High for Region 1 02A0 0350 DRAE2 DMA Region Access Enable Register for Region 2 02A0 0354 DRAEH2 DMA Region Access Enable Register High for Region 2 02A0 0358 DRAE3 DMA Region Access Enable Register for Region 3 02A0 035C DRAEH3 DMA Region Access Enable Register High for Region 3 02A0 0360 D
54. EDMA event DSP EVT channel 0 it will get recorded in bit 0 of the EDMA Event Register ER This event must be cleared by software before triggering transfers on DMA channel 0 The EDMA3 on the C6454 DSP supports active memory protection but it does not support proxied memory protection The EDMA supports two addressing modes constant addressing and increment addressing mode On the C6454 DSP constant addressing mode is not supported by any peripheral or internal memory For more information on these two addressing modes see the TMS320C645x DSP Enhanced EDMA Controller User s Guide literature number SPRU966 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 6 INSTRUMENTS www ti com TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 42 EDMAS Channel Synchronization Events The EDMAS supports up to 64 DMA channels that can be used to service system peripherals and to move data between system memories DMA channels can be triggered by synchronization events generated by system peripherals Table 7 3 lists the source of the synchronization event associated with each of the DMA channels On the C6454 the association of each synchronization event and DMA channel is fixed and cannot be reprogrammed For more detailed information on the EDMA3 module and how EDMAS events are enabled captured processed prioritized linke
55. FFFF 0184 82 0 MAR176 Controls EMIFA Range 000 0000 BOFF FFFF 0184 82 4 MAR177 Controls EMIFA Range B100 0000 B1FF FFFF 0184 82C8 MAR178 Controls EMIFA Range B200 0000 B2FF FFFF 0184 82CC MAR179 Controls EMIFA Range B300 0000 B3FF FFFF 0184 8200 MAR180 Controls EMIFA CE3 Range B400 0000 B4FF FFFF 0184 82D4 MAR181 Controls EMIFA Range B500 0000 B5FF FFFF 0184 82D8 MAR182 Controls EMIFA Range 600 0000 BeFF FFFF 0184 82DC MAR183 Controls EMIFA CE3 Range B700 0000 B7FF FFFF 0184 82E0 MAR184 Controls EMIFA Range B800 0000 FFFF 0184 82E4 MAR185 Controls EMIFA Range B900 0000 FFFF 0184 82E8 MAR186 Controls EMIFA Range 0000 BAFF FFFF 0184 82EC MAR187 Controls EMIFA Range 00 0000 BBFF FFFF 0184 82 0 MAR188 Controls Range 00 0000 BCFF FFFF 0184 82F4 MAR189 Controls EMIFA Range 000 0000 BDFF FFFF 0184 82F8 MAR190 Controls EMIFA Range 0000 BEFF FFFF 0184 82FC MAR191 Controls EMIFA Range BF00 0000 BFFF FFFF 0184 8300 MAR192 Controls EMIFA CE4 Range C000 0000 COFF FFFF 0184 8304 MAR193 Controls EMIFA CE4 Range C100 0000 C1FF FFFF 0184 8308 MAR194 Controls EMIFA CE4 Range C200 0000 C2FF FFFF 0184 830C MAR195 Controls EMIFA CE4 Range C300 0000 C3FF FFFF 0184 8310 MAR196 Controls EMIFA CE4 Range C400 0000 C4FF FFFF 0184 8314 MAR197 Controls EMIFA CE4 Range C500 0000 C5FF
56. Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com Table 7 4 EDMA3 Channel Controller Registers continued Mal aad HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 04FC Q3E15 Event Queue 3 Entry Register 15 02A0 0500 02A0 051C Reserved 02A0 0520 02 0 05 Reserved 02A0 0600 QSTATO Queue Status Register 0 02A0 0604 QSTAT1 Queue Status Register 1 02A0 0608 QSTAT2 Queue Status Register 2 02A0 060 QSTAT3 Queue Status Register 3 02A0 0610 02 0 061C Reserved 02A0 0620 QWMTHRA Queue Watermark Threshold A Register 02A0 0624 02A0 063C Reserved 02A0 0640 CCSTAT Status Register 02A0 0644 02A0 06FC Reserved 02A0 0700 02A0 07FC Reserved 02A0 0800 MPFAR Memory Protection Fault Address Register 02 0 0804 MPFSR Memory Protection Fault Status Register 02A0 0808 MPFCR Memory Protection Fault Command Register 02A0 080C MPPAO Memory Protection Page Attribute Register 0 02A0 0810 MPPA1 Memory Protection Page Attribute Register 1 02A0 0814 MPPA2 Memory Protection Page Attribute Register 2 02A0 0818 MPPAS3 Memory Protection Page Attribute Register 3 02A0 081C MPPA4 Memory Protection Page Attribute Register 4 02A0 0820 MPPA5 Memory Protection Page Attribute Register 5 02A0 0824 MPPA6 Memory P
57. Global Control Register 0298 0028 WDTCR1 Timer 1 Watchdog Timer Control Register 0298 002 Reserved 0298 0030 Reserved 0298 0034 0299 FFFF Reserved Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 205 PRODUCT PREVIEW Mal aad LONAOYd TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 15 3 Timers Electrical Data Timing Table 7 94 Timing Requirements for Timer Inputs see Figure 7 73 720 850 NO 1000 UNIT MIN MAX lw TINPH Pulse duration TINPLx high 12P ns 2 lw TINPL Pulse duration TINPLx low 12P ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use 1 ns Table 7 95 Switching Characteristics Over Recommended Operating Conditions for Timer Outputs see Figure 7 73 720 850 NO PARAMETER 1000 UNIT MIN MAX 3 tw TOUTH Pulse duration TOUTLx high 12P 3 hs tw TOUTL Pulse duration TOUTLx low 12P 3 ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use 1 ns k 2 4 Eie TNPLx 7f r TOUTLx b Figure 7 73 Timer Timing 206 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www t
58. Guide This document provides a functional description of the Ethernet Media Access Controller EMAC and Physical layer PHY device Management Data Input Output MDIO module integrated with the devices of the TMS320C645x family TMS320C645x DSP External Memory Interface EMIF User s Guide This document describes the operation of the external memory interface EMIF in the digital signal processors DSPs of the TMS320C645x DSP family TMS320C645x DSP General Purpose Input Output GPIO User s Guide This document describes the general purpose input output GPIO peripheral in the digital signal processors DSPs of the TMS320C645x DSP family The GPIO peripheral provides dedicated general purpose pins that can be configured as either inputs or outputs When configured as an input you can detect the state of the input by reading the state of an internal register When configured as an output you can write to an internal register to control the state driven on the output pin TMS320C645x DSP Host Port Interface HPI User s Guide This guide describes the host port interface HPI on the TMS320C645x digital signal processors DSPs The HPI enables an external host processor host to directly access DSP resources including internal and external memory using a 16 bit 16 or 32 bit HPI32 interface TMS320C645x DSP Inter Integrated Circuit I2C Module User s Guide This document describes the inter integrated circuit I2C module in
59. IESR Interrupt Enable Set Register 02A0 1064 IESRH Interrupt Enable Set High Register 02A0 1068 IPR Interrupt Pending Register 02A0 106C IPRH Interrupt Pending High Register 02A0 1070 ICR Interrupt Clear Register 02A0 1074 ICRH Interrupt Clear High Register 02A0 1078 IEVAL Interrupt Evaluate Register 02A0 107C Reserved 02A0 1080 QER QDMA Event Register 02A0 1084 QEER QDMA Event Enable Register 02A0 1088 QEECR QDMA Event Enable Clear Register 02A0 108C QEESR QDMA Event Enable Set Register 02A0 1090 QSER QDMA Secondary Event Register 02A0 1094 QSECR QDMA Secondary Event Clear Register 02 0 1098 02A0 1FFF Reserved 02A0 2000 02A0 2097 Shadow Region 0 Channel Registers 02A0 2098 02 0 21FF Reserved 02A0 2200 02A0 2297 Shadow Region 1 Channel Registers 02A0 2298 02 0 23FF Reserved 02A0 2400 02A0 2497 Shadow Region 2 Channel Registers 02A0 2498 02A0 25FF Reserved 02A0 2600 02A0 2697 Shadow Region 3 Channel Registers 02A0 2698 02A0 27FF Reserved 02A0 2800 02A0 2897 Shadow Region 4 Channel Registers 02A0 2898 02A0 29FF Reserved 02A0 2 00 02A0 2 97 Shadow Region 5 Channel Registers 02A0 2A98 02A0 2BFF Reserved 02A0 2 00 02 0 2C97 Shadow Region 6 Channel Registers 02A0 2C98 02A0 2DFF Reserved 02A0 2 00 02A0 2E97 Shadow Region 7 Channel Registers 02A0 2E98 02A0 2FFF
60. Input and Output Clock Electrical Data Timing Table 7 29 Timing Requirements for CLKIN1 Devices 99 see Figure 7 21 720 850 1000 NO PLL MODES UNIT x1 Bypass x15 X20 x25 x30 x32 MIN MAX 1 tc CLKIN1 Cycle time CLKIN1 4 15 30 3 ns 2 tw CLKIN1H Pulse duration CLKIN1 high 0 4 ns 3 tw CLKIN1L Pulse duration CLKIN1 low 0 4C ns 4 tyCLKIN1 Transition time CLKIN1 1 2 ns 5 U CLKIN1 Period jitter peak to peak CLKIN1 100 ps 1 The reference points for the rise and fall transitions are measured at 3 3 V Vi MAX and Vj MIN 2 For more details on the PLL multiplier factors x1 BYPASS x 15 x20 x25 x30 x32 see Section 7 7 1 2 PLL1 Controller Operating Modes cycle time in ns For example when CLKIN1 frequency is 50 MHz use C 20 ns 4 The PLL1 multiplier factors x1 BYPASS x 15 x20 x25 x30 x32 further limit the MIN and MAX values for For more detailed information on these limitations see Section 7 7 1 1 Internal Clocks and Maximum Operating Frequencies 54 6 1 4 I k 3 4 4 le Figure 7 21 CLKIN1 Timing Table 7 30 Switching Characteristics Over Recommended Operating Conditions for SYSCLK4 CPU 8 CPU 12 see Figure 7 22 720 850 NO PARAMETER 1000 UNIT MIN MAX 2 tw CKO3H Pulse duration SYSCLK4 high 4P 0 7 0 7 ns 3 tw CK
61. L2 Writeback Word Count Register 0184 4008 0184 400C Reserved 0184 4010 L2WIBAR L2 Writeback and Invalidate Base Address Register for Block Writebacks 0184 4014 L2WIWC L2 Writeback and Invalidate word count register 0184 4018 L2IBAR L2 Invalidate Base Address Register 0184 401C L2IWC L2 Invalidate Word Count Register 0184 4020 L1PIBAR L1P Invalidate Base Address Register 0184 4024 L1PIWC L1P Invalidate Word Count Register 0184 4030 L1DWIBAR L1D Writeback and Invalidate Base Address Register 0184 4034 L1DWIWC L1D Writeback and Invalidate Word Count Register 0184 4038 Reserved 0184 4040 L1DWBAR L1D Writeback Base Address Register for Block Writebacks 0184 4044 L1DWWC L1D Writeback Word Count Register 0184 4048 L1DIBAR L1D Invalidate Base Address Register 0184 404C L1DIWC L1D Invalidate Word Count Register 0184 4050 0184 4FFF Reserved 0184 5000 L2WB L2 Global Writeback Register 0184 5004 L2WBINV L2 Global Writeback and Invalidate Register 0184 5008 L2INV L2 Global Invalidate Register 0184 500C 0184 5024 Reserved 0184 5028 L1PINV L1P Global Invalidate Register 0184 502C 0184 503C Reserved 0184 5040 L1DWB L1D Global Writeback Register 0184 5044 L1DWBINV L1D Global Writeback and Invalidate Register 0184 5048 L1DINV L1D Global Invalidate Register 0184 8000 0184 81FC MARIO Reserved 0184 8200 0184 823C 12810 Reserved 0184 8240 0184 827C mise Reserved 0184 8280 MAR160 Controls EMIFA CE2 Range A000 0000 AOFF FFFF 0184 828
62. N26 hold request acknowledge to the host AHOLD R29 EMIFA hold request from the host ABUSREQ L27 bus request output EMIFA 64 BIT ASYNCHRONOUS SYNCHRONOUS MEMORY CONTROL EMIFA external input clock The EMIFA input clock AECLKIN or SYSCLK4 AECLKIN N29 IPD clock is selected at reset via the pullup pulldown resistor on the AEA 15 pin Note AECLKIN is the default for the EMIFA input clock AECLKOUT V29 O Z IPD EMIFA output clock at EMIFA input clock AECLKIN or SYSCLKA frequency AAWE ASWE AB25 O Z IPU 2 memory write enable Programmable synchronous interface AARDY K29 Asynchronous memory ready input AR W W25 O Z IPU Asynchronous memory read write AAOE ASOE Y28 O Z IPU Asynchronous Programmable synchronous memory output enable Programmable synchronous address strobe or read enable For programmable synchronous interface the enable field in the Chip Select x Configuration Register selects between ASADS and ASRE ASADS ASRE R26 O Z IPU fr enable 0 then the ASADS ASRE signal functions as the ASADS signal fr enable 1 then the ASADS ASRE signal functions as the ASRE signal Submit Documentation Feedback Device Overview 27 PRODUCT PREVIEW MalAddd TMS32006454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com Table 2 3 Terminal Functions contin
63. NUMBER MANUFACTURER 4 bit 16 bit 11 bit R n R 0000 0000 1000 1010b 0000 0010 111b R 1 LEGEND R Read only n value after reset Figure 3 11 JTAG ID Register 0 02 8 0008 Table 3 14 JTAG ID JTAGID Register Field Descriptions Field Value Description 31 28 VARIANT Variant 4 Bit value The value of this field depends on the silicon revision being used For more information see the TMS320C6455 54 Digital Signal Processor Silicon Errata literature number SPRZ234 Note the VARIANT field may be invalid if no CLKIN1 signal is applied 27 12 PART NUMBER Part Number 16 Bit value C6454 value 0000 0000 1000 10100 11 1 MANUFACTURER Manufacturer 11 Bit value C6454 value 0000 0010 111b 0 LSB LSB This bit is read as a 1 for C6454 3 7 Pullup Pulldown Resistors Proper board design should ensure that input pins to the C6454 device always be at a valid logic level and not floating This may be achieved via pullup pulldown resistors The C6454 device features internal pullup IPU and internal pulldown IPD resistors on most pins to eliminate the need unless otherwise noted for external pullup pulldown resistors An external pullup pulldown resistor needs to be used in the following situations e Device Configuration Pins If the pin is both routed out and 3 stated not driven an external pullup pulldown resistor must be used even if the IPU IPD
64. PLL Controller User s Guide literature number SPRUE56 are supported on the TMS320C6454 Only those registers documented in this section are supported Furthermore only the bits within the registers described here are supported You should not write to any reserved memory location or change the value of reserved bits 7 7 3 1 PLL1 Control Register The PLL control register PLLCTL is shown in Figure 7 11 and described in Table 7 19 1 16 R 0 15 8 7 6 5 4 3 2 1 0 R 0 R W 0 R 1 R W 0 R W 1 R 0 R W 0 R W 0 LEGEND R W Read Write Read only n value after reset Figure 7 11 PLL1 Control Register PLLCTL Hex Address 029A 0100 Table 7 19 PLL1 Control Register PLLCTL Field Descriptions Bit Field Value Description 31 8 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 7 Reserved Reserved Writes to this register must keep this bit as 0 6 Reserved Reserved The reserved bit location is always read as 1 A value written to this field has no effect 5 4 Reserved Reserved Writes to this register must keep this bit as 0 3 PLLRST PLL reset bit 0 PLL reset is released 1 PLL reset is asserted 2 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect PLLPWRDN PLL power down mode select bit 0 PLL is operational PLL is placed in power down state i e all analog circuitry in the PLL is turned
65. Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 3 4 6 Emulator Buffer Powerdown Register EMUBUFPD Description The Emulator Buffer Powerdown Register EMUBUFPD is used to control the state of the pin buffers of emulator pins EMU 18 2 These buffers can be powered down if the device trace feature is not needed 31 8 Reserved R 0 7 1 0 Reserved EMUCTL R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Figure 3 9 Emulator Buffer Powerdown Register EMUBUFPD 0x02AC 0054 Table 3 12 Emulator Buffer Powerdown Register EMUBUFPD Field Descriptions Bit Field Value Description 31 1 Reserved Reserved 0 EMUCTL Buffer powerdown for EMU 18 2 pins 0 Power up buffers 1 Power down buffers 64 Device Configuration Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 3 5 Device Status Register Description The device status register depicts the device configuration selected upon device reset Once set these bits will remain set until a device reset For the actual register bit names and their associated bit field descriptions see Figure 3 10 and Table 3 13 Note that enabling or disabling peripherals through the Peripheral Configuration Registers PERCFGO and PERCFG 1 does not affect the DEVSTAT register
66. Read Write Read only n value after reset Figure 3 5 Peripheral Configuration Register 1 PERCFG1 0 02 002C Table 3 8 Peripheral Configuration Register 1 PERCFG1 Field Descriptions Bit Field Value Description 31 2 Reserved Reserved 1 DDR2CTL Mode Control for DDR2 Memory Controller Once this bit is set to 1 it cannot be changed to 0 0 Set DDR2 to disabled 1 Set DDR2 to enabled 0 EMIFACTL Mode control for EMIFA Once this bit is set to 1 it cannot be changed to O This bit defaults to 1 if EMIFA 8 bit ROM boot is used BOOTMODE 3 0 0100b 0 Set EMIFA to disabled 1 Set EMIFA to enabled Submit Documentation Feedback Device Configuration 59 PRODUCT PREVIEW MalAddd TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 3 4 4 Peripheral Status Registers Description The Peripheral Status Registers PERSTATO and PERSTAT1 show the status of the C6454 peripherals 31 30 29 27 26 24 Reserved HPISTAT McBSP1STAT R 0 R 0 R 0 23 21 20 18 17 16 McBSPOSTAT I2CSTAT GPIOSTAT R 0 R 0 R 0 15 14 12 11 9 8 GPIOSTAT TIMER1STAT TIMEROSTAT EMACSTAT R 0 R 0 R 0 R 0 7 6 5 0 EMACSTAT Reserved R 0 R 0 LEGEND R Read only n value after reset Figure 3 6 Peripheral Status Register 0 PERSTATO 0x02AC 0014 Table 3 9 Periphera
67. Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 45 Switching Characteristics Over Recommended Operating Conditions for Asynchronous Memory Cycles for EMIFA Module 99 see Figure 7 33 and Figure 7 34 720 850 NO PARAMETER 1000 UNIT MIN MAX 1 tosu SELV AOEL Output setup time select signals valid to AAOE low RS E 1 5 ns 2 loh AOEH SELIV Output hold time AAOE high to select signals invalid RS E 1 9 ns 10 la EKOH AOEV Delay time AECLKOUT high to AAOE valid 1 7 ns 11 losu SELV AWEL Output setup time select signals valid to AAWE low WS E 1 7 ns 12 tohAWEH SELIV Output hold time AAWE high to select signals invalid WH 1 8 ns 13 la EKOH AWEV Delay time AECLKOUT high to AAWE valid 1 3 7 1 ns 1 E AECLKOUT period in ns for EMIFA 2 RS Read setup RST Read strobe RH Read hold WS Write setup WST Write strobe WH Write hold These parameters are programmed via the EMIFA CE Configuration registers CEnCFG 3 Select signals for EMIFA include ACEx ABE 7 0 AEA 19 0 ABA 1 0 and for EMIFA writes also include AR W AED 63 0 k 2171 Strobe 4 8 1 k 2 y 1 w e mem c 1 1 y E ABA 1 0 aa AED 63 0 3 4 10777 AAWE ASWE AR W AARDY B DEASSERTED A 5 and AAWE ASWE operate as
68. Supply Voltage Monitor Pins Changed Signal to DVppismon updated Description and moved under Supply Voltage Monitor Pins Changed Signal A26 to DVppigmon updated Description and moved under Supply Voltage Monitor Pins Updated Descriptions for Signals AVppA DVppnw gt AVppr and CVpp Device and Development Support Tool Nomenclature Updated Figure 2 12 TMS320C64x DSP Device Nomenclature including the TMS320C6454 DSP Documentation Support Updated list of related documentation Device Configuration at Device Reset Updated paragraph and Note Updated Footnote 1 and Configuration Pin AEA3 Description in Table 3 1 C6454 Device Configuration Pins AEA 19 0 ABA 1 0 and PCI EN Peripheral Selection After Device Reset Updated Table 3 4 Peripheral States Added Note Peripheral Lock Register Description Added Note Revision History Submit Documentation Feedback 4 6 INSTRUMENTS www ti com TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 C6454 Revision History continued SEE ADDITIONS MODIFICATIONS DELETIONS Section 3 4 2 Section 3 4 5 Section 3 7 Section 3 8 Section 5 1 Section 6 Section 7 3 1 Section 7 3 4 Section 7 4 Section 7 4 1 Section 7 4 3 Section 7 5 1 Section 7 6 Section 7 6 7 Section 7 7 Section 7 7 1 Peripheral Configuration Register 0 Description Updated paragraph
69. Table 7 87 title to Switching Characteristics Over Recommended Operating Conditions for TXC RGMII Operation for 10 100 100 Mbit s MDIO Device Specific Information Updated paragraph PCI Device Specific Information Updated paragraphs Added Table 7 96 Default Values for PCI Configuration Registers PCI Electrical Data Timing Deleted Peripheral Component Interconnect PCI Timing section Added new paragraph Mechanical Data Added the GTZ S PBGA N697 Plastic Ball Grid Array mechanical package drawing Submit Documentation Feedback Revision History 221 PRODUCT PREVIEW 9 Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 7 Dec 2006 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing Qty TMS320C6454BZTZ ACTIVE FCBGA ZTZ 697 44 Pb Free RoHS SNAGCU Level 4 260C 72HR Exempt TMS320C6454BZTZ7 ACTIVE FCBGA ZTZ 697 44 Pb Free RoHS SNAGCU Level 4 260C 72HR Exempt TMS320C6454BZTZ8 ACTIVE FCBGA ZTZ 697 44 Pb Free RoHS SNAGCU Level 4 260C 72HR Exempt The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but does not recommend using this part in a new design PREVIEW De
70. These pins function as open drain outputs when configured as PCI pins Submit Documentation Feedback Device Overview 25 PRODUCT PREVIEW Mal aad TMS32006454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com Table 2 3 Terminal Functions continued SIGNAL TYPE IPD IPU DESCRIPTION NAME NO PTRDY P4 VO Z PCI target ready PRTDY I O Z By default this pin has no function HD31 AD31 HD30 AD30 5 HD29 AD29 AC4 HD28 AD28 AAA HD27 AD27 AC5 HD26 AD26 Y1 HD25 AD25 AD2 HD24 AD24 Voz Host port data 31 16 pin 1 0 2 default or PCI data address bus 31 16 HD23 AD23 AC3 VO Z HD22 AD22 AE1 HD21 AD21 AD1 HD20 AD20 w2 HD19 AD19 AC1 HD18 AD18 Y2 HD17 AD17 1 HD16 AD16 HD15 AD15 AB2 HD14 AD14 W4 HD13 AD13 AC2 HD12 AD12 V4 HD11 AD11 AF3 HD10 AD10 HD9 AD9 AB3 HD8 AD8 W5 VO Z Host port data 15 0 pin I O Z default or PCI data address bus 15 0 0 2 HD7 AD7 ABA HD6 AD6 Y4 HD5 AD5 AD3 HD4 AD4 Y5 HD3 AD3 AD4 HD2 AD2 W6 HD1 AD1 AB5 HD0 AD0 AE2 EMIFA 64 BIT CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY ABA1 EMIFA_EN V25 O Z IPD ABAO DDR2 EN V26 O Z IPD EMIFA bank address control ABA 1 0 e Active low bank selects for the 64 bit
71. To determine the status of peripherals following writes to the PERCFGO and 1 registers read the Peripherals Status Registers PERSTATO and PERSTAT1 31 24 Reserved R 0000 0000 23 22 21 20 19 18 17 16 Reserved EMIFA_EN DDR2_EN CFGGP2 CFGGP1 CFGGPO Reserved R 0 R x R x R x R x R x R x R 1 15 14 13 12 11 10 9 8 MCBSP1 66 Reserved PCI_EEAI MAC SEL1 MAC SELO Reserved R x R x R x R 0 R x R x R x R 1 7 6 5 4 3 2 1 0 Reserved LENDIAN HPI WIDTH AECLKINSEL BOOTMODES BOOTMODE2 BOOTMODE1 BOOTMODEO R 0 R x R x R x R x R x R x R x LEGEND R W Read Write R Read only x value after reset Figure 3 10 Device Status Register DEVSTAT 0x02A8 0000 Table 3 13 Device Status Register DEVSTAT Field Descriptions Bit Field Value Description 31 23 Reserved Reserved Read only writes have no effect 22 EMIFA EN EMIFA Enable EMIFA EN status bit Shows the status of whether the EMIFA peripheral pins are enabled disabled 0 EMIFA peripheral pins are disabled default 1 EMIFA peripheral pins are enabled 21 DDR2 EN DDR2 Memory Controller Enable DDR2 EN status bit Shows the status of whether the DDR2 Memory Controller peripheral pins are enabled disabled 0 DDR2 Memory Controller peripheral pins are disabled default 1 DDR2 Memory Controller peripheral pins are enabled 20 PC
72. and added Note Changed all bit field resets to R W 0 and updated Figure 3 4 Peripheral Configuration Register 0 PERCFGO Updated Table 3 7 Peripheral Configuration Register 0 PERCFGO Field Descriptions EMAC Configuration Register EMACCFG Description Changed bits 23 19 reset value to R W 0001b and moved in RMII_RST field to bit 18 Figure 3 8 EMAC Configuration Register EMACCFG Updated Reserved Bits 31 19 Description and RMII_RST Bit 18 Description Values 0 and 1 in Table 3 11 EMAC Configuration Register EMACCFG Field Descriptions Deleted Debugging Considerations Added new section Pullup Pulldown Resistors Configuration Examples Added comments for AEA 12 AEA 11 and AEA 3 and changed SYSCLK3 to SYSCLK4 in comment for AEA 4 in Figure 3 12 Configuration Example and Figure 3 13 Configuration Example Memory Architecture Updated paragraphs Updated Figure 5 4 TMS320C6454 L2 Memory Configurations Device Operating Conditions Updated Section 6 1 Absolute Maximum Ratings Over Operating Case Temperature Range Updated Section 6 2 Recommended Operating Conditions Updated Section 6 3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature Power Supply Sequencing Updated paragraph Deleted Power Supply Sequence Option 1 figure and Timing Requirements for Power Supply Sequence Option 1 table Preserving Boundary Scan Functionality on RGMII and DDR2 Memory Pins s
73. are allowed Submit Documentation Feedback 4 6 INSTRUMENTS www ti com k 26 lq 23 19 mone SCL le 16 3 l kb 18 Stop Start Submit Documentation Feedback NAT wv 21 F 2 k 27 22 Lp 5320 6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Fe Zx i 18 17 Repeated Start Figure 7 43 12 Transmit Timings 24 ke 28 k C64x Peripheral Information and Electrical Specifications 165 PRODUCT PREVIEW Mal aad LONAOYd TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 12 Host Port Interface HPI Peripheral 6 INSTRUMENTS www ti com 7 12 1 HPI Device Specific Information The C6454 device includes a user configurable 16 bit or 32 bit Host port interface HPI16 HPI32 AEA14 pin controls the HPl_WIDTH allowing the user to configure the HPI as a 16 bit or 32 bit peripheral Software handshaking via the HRDY bit of the Host Port Control Register HPIC is not supported on the C6454 An HPI boot is terminated using a DSP interrupt The DSP interrupt is registered in bit 0 channel of the EDMA Event Register ER This event must be cleared by software before triggering transfers on DMA channel
74. auto increment 10 M 20 and read FIFO initially empty 9 7 ty HDV HRDYL Delay time HD valid to HRDY low 0 ns Case 1 HPIA write 9 5 M 20 Delay time HSTROBE high to 34 ta DSH HRDYL HRDY low Case 2 HPID write with no 5 M 20 ns auto increment 9 Delay time HSTROBE low to HRDY low for HPIA write and FIFO not 35 td HSTBL HRDYL l 40 20 36 ty HASL HRDYH Delay time HAS low to HRDY high 12 ns 1 M SYSCLKS period 6 CPU clock frequency in ns For example when running parts at 1000 MHz use M 6 ns 2 HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS 3 Assumes the is accessing L2 L1 memory and no other master is accessing the same memory location 168 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com HC o HAS HCNTL 1 0 HR W HHWIL HSTROBE HD 15 0 4 5320 6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 4 38 7 h 6 gt SS A 22 2 HRDY B X HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO tra
75. be relied upon TI recommends the use of an external pullup pulldown resistor For more detailed information on pullup pulldown resistors and situations where external pullup pulldown resistors are required see Section 3 7 Pullup Pulldown Resistors Table 3 1 C6454 Device Configuration Pins AEA 19 0 ABA 1 0 and PCI CONFIGURATION PIN NO IPD FUNCTIONAL DESCRIPTION AEA 19 16 N25 L26 L25 P26 IPD Boot Mode Selections BOOTMODE 3 0 These pins select the boot mode for the device 0000 0001 0010 0011 0100 0101 0110 0111 1000 thru Reserved 1111 If selected for boot the corresponding peripheral is automatically enabled after device reset For more detailed information on boot modes see Section 2 4 Boot Sequence CFGGP 2 0 pins must be set to 000b during reset for proper operation of the PCI boot mode No boot default mode Host boot Reserved Reserved EMIFA 8 bit ROM boot Master I2C boot Slave 12 boot Host boot PCI AEA15 P27 IPD EMIFA input clock source select AECLKIN SEL 0 1 AECLKIN default mode SYSCLKA CPU x Clock Rate The SYSCLKA clock rate is software selectable via the Software PLL1 Controller By default SYSCLKA is selected as CPU 8 clock rate 1 IPD Internal pulldown Internal pullup For most systems a 1 kQ resistor can be used to oppose the IPU IPD For more detailed
76. channel 0 interrupt 140 IDMA1 IDMA channel 1 interrupt 150 DSPINT HPI PCI to DSP interrupt 16 I2CINT 12 interrupt 17 MACINT Ethernet MAC interrupt 18 AEASYNCERR EMIFA error interrupt 19 23 Reserved Reserved Do not use 24 GINT channel global completion interrupt 25 39 Reserved Reserved Do not use 40 RINTO McBSPO receive interrupt 41 XINTO McBSPO transmit interrupt 42 RINT1 McBSP 1 receive interrupt 43 XINT1 McBSP1 transmit interrupt 44 50 Reserved Reserved Do not use 51 GPINTO GPIO interrupt 52 GPINT1 GPIO interrupt 53 GPINT2 GPIO interrupt 54 GPINT3 GPIO interrupt 55 GPINT4 GPIO interrupt 56 GPINT5 GPIO interrupt 57 GPINT6 GPIO interrupt 58 GPINT7 GPIO interrupt 1 Interrupts 0 through 3 are non maskable and fixed 2 Interrupts 4 through 15 are programmable by modifying the binary selector values in the Interrupt Selector Control registers fields shows the default interrupt sources for Interrupts 4 through 15 112 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 Table 7 10 C6454 DSP Interrupts continued EVENT NUMBER INTERRUPT EVENT INTERRUPT SOURCE 59 GPINT8 GPIO
77. clock cycles to change the state of the peripherals Poll the PERSTAT registers to verify state change Figure 3 2 Peripheral State Change Flow A 32 bit key value 0x0F0A 0B00 must be written to the Peripheral Lock register PERLOCK in order to allow access to the register Writes to the PERCFG1 register can be done directly without going through the PERLOCK register NOTE The instructions that write to the PERLOCK and PERCFG0 registers must be in the same fetch packet if code is being executed from external memory If the instructions are in different fetch packets fetching the second instruction from external memory may stall the instruction long enough such that PERCFG0 register will be locked before the instruction is executed 54 Device Configuration Submit Documentation Feedback 4 6 INSTRUMENTS www ti com 3 4 Device State Control Registers TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 The C6454 device has a set of registers that are used to control the status of its peripherals These registers are shown in Table 3 5 and described in the next sections NOTE The device state control registers can only be accessed using the CPU or the emulator Table 3 5 Device State Control Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02AC 0000 Reserved 02AC 0004 PERLOCK Peri
78. controller registers O29A 0000 029A 01FF see Table 7 18 7 6 6 1 Reset Type Status Register Description The rest type status RSTYPE register latches the cause of the last reset If multiple reset sources occur simultaneously this register latches the highest priority reset source The reset type status register is shown in Figure 7 7 and described in Table 7 13 31 16 Reserved R 0 15 4 3 2 1 0 Reserved SRST Rsvd WRST POR R 0 R 0 R 0 R 0 R 0 LEGEND R W Read Write Read only n value after reset Figure 7 7 Reset Type Status Register RSTYPE Hex Address 029A 00E4 Table 7 13 Reset Type Status Register RSTYPE Field Descriptions Bit Field Value Description 31 4 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 3 SRST System reset 0 System Reset was not the last reset to occur 1 System Reset was the last reset to occur 2 Reserved Reserved The reserved bit location is always read as 0 A value written to this field has no effect 1 WRST Warm reset 0 Warm Reset was not the last reset to occur 1 Warm Reset was the last reset to occur 0 POR Power on reset 0 Power on Reset was not the last reset to occur 1 Power on Reset was the last reset to occur Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 119 PRODUCT PREVIEW M3al aad
79. e The RESETSTAT pin stays asserted low indicating the device is in reset 3 The POR pin may now be deasserted driven high When the pin is deasserted the configuration pin values are latched and the PLL controllers change their system clocks to their default divide down values PLL2 is taken out of reset and automatically starts its locking sequence Other device initialization is also started 4 After device initialization is complete the RESETSTAT pin is deasserted driven high By this time PLL2 has already completed its locking sequence and is outputting a valid clock The system clocks of both PLL controllers are allowed to finish their current cycles and then paused for 10 cycles of their respective system reference clocks After the pause the system clocks are restarted at their default divide by settings 5 The device is now out of reset device execution begins as dictated by the selected boot mode see Section 2 4 Boot Sequence NOTE To most of the device reset is de asserted only when the POR and RESET pins are both de asserted driven high Therefore in the sequence described above if the RESET pin is held low past the low period of the POR pin most of the device will remain in reset The only exception being that PLL2 is taken out of reset as soon as POR is de asserted driven high regardless of the state of the RESET pin The RESET pin should not be tied together with the POR pin 7 6 2 Warm Reset
80. generate all the clocks to the EMAC module When enabled the input clock to the PLL2 Controller CLKIN2 must have a 25 MHz frequency For more information see Section 7 8 PLL2 and PLL2 Controller The EMAC uses SYSCLK1 of the PLL2 Controller to generate the necessary clocks for the GMII and RGMII modes When these modes are used the frequency of CLKIN2 must be 25 MHz Also divider D1 should be programmed to 2 mode default when using the GMII mode and to 5 mode when using the RGMII mode Divider D1 is software programmable and if necessary must be programmed after device reset to 5 when the RGMII mode of the EMAC is used 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 ki TEXAS INSTRUMENTS www ti com 7 14 2 Peripheral Register Description s Table 7 71 Ethernet MAC EMAC Control Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02C8 0000 TXIDVER Transmit Identification and Version Register 02C8 0004 TXCONTROL Transmit Control Register 02C8 0008 TXTEARDOWN Transmit Teardown Register 02C8 000 s Reserved 02C8 0010 RXIDVER Receive Identification and Version Register 02C8 0014 RXCONTROL Receive Control Register 02C8 0018 RXTEARDOWN Receive Tear
81. in ns for EMIFA AECLKIN N ra le AECLKOUT1 _ w Figure 7 32 AECLKOUT Timing for the Module 7 10 3 1 Asynchronous Memory Timing Table 7 44 Timing Requirements for Asynchronous Memory Cycles for EMIFA Module 72 9 see Figure 7 33 and Figure 7 34 720 850 NO 1000 UNIT MIN MAX 3 tsu EDV AOEH Setup time AEDx valid before AAOE high 6 5 ns 4 th AOEH EDV Hold time AEDx valid after AAOE high 3 ns 5 Isu ARDY EKOH Setup time AARDY valid before AECLKOUT low 1 ns 6 th EKOH ARDY Hold time AARDY valid after AECLKOUT low 2 ns T tw ARDY Pulse width AARDY assertion and deassertion 2E 5 ns 8 t Delay time from AARDY sampled deasserted on AECLKOUT falling to 4E d ARDY HOLD beginning of programmed hold period 9 Setup time before end of programmed strobe period by which AARDY 2E i su ARDY HOLD should be asserted in order to insert extended strobe wait states 1 E AECLKOUT period in ns for EMIFA 2 To ensure data setup time simply program the strobe width wide enough 3 AARDY is internally synchronized To use AARDY as an asynchronous input the pulse width of the AARDY signal should be at least 2E to ensure setup and hold time is met 152 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com TMS320C6454 Fixed Point Digital
82. information on pullup pulldown resistors and situations where external pullup pulldown resistors are required see Section 3 7 Pullup Pulldown Resistors 50 Device Configuration Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 3 1 C6454 Device Configuration Pins AEA 19 0 ABA 1 0 and continued CONFIGURATION PIN NO IPD FUNCTIONAL DESCRIPTION AEA14 R25 IPD HPI peripheral bus width select HPI_WIDTH 0 HPI operates in 16 mode default HPI bus is 16 bits wide HD 15 0 pins are used and the remaining HD 31 16 pins are reserved pins in the Hi Z state 1 HPI operates in HPI32 mode HPI bus is 32 bits wide HD 31 0 pins are used Applies only when HPI function of HPI PCI multiplexed pins is selected PCI EN 0 AEA13 R27 IPU Device Endian mode LENDIAN 0 System operates in Big Endian mode 1 System operates in Little Endian mode default AEA12 R28 IPD For proper C6454 device operation this pin must be externally pulled down with a 1 resistor at device reset AEA11 T25 IPD For proper C6454 device operation this pin must be externally pulled down with a 1 resistor at device reset AEA 10 9 M25 M27 IPD EMAC Interface Selects MACSEL 1 0 These pins select the interface
83. module 12 NOTE when using the 2 module ensure there are external pullup resistors on the SDA and SCL pins 2 modules on the C6454 may be used by the DSP to control local peripherals ICs DACs ADCs etc or may be used to communicate with other controllers in a system or to implement a user interface The 2 port supports e Compatible with Philips 2 Specification Revision 2 1 January 2000 Fast Mode up to 400 Kbps no fail safe I O buffers e Noise Filter to remove noise 50 ns or less e 7 and 10 Bit Device Addressing Modes e Multi Master Transmit Receive and Slave Transmit Receive Functionality e Events DMA Interrupt or Polling Slew Rate Limited Open Drain Output Buffers Figure 7 41 is a block diagram of the 2 module 160 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com 2 Module SCL 12C Clock X Noise Filter 12C Data X Noise Filter Clock Prescale Y Bit Clock Generator TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Peripheral Clock CPU 6 Transmit Transmit Shift Transmit Buffer Control Own 2 Address Slave IPCSAR Address I2CMDR Mode Data I2CCNT Count Extended Mode I2ZCEMDR Receive I2CDRR Shading denotes c
84. off 0 PLLEN PLL enable bit 0 Bypass mode Divider PREDIV PLL are bypassed All the system clocks SYSCLKn divided down directly from input reference clock 1 PLL mode Divider PREDIV and PLL are not bypassed PLL output path is enabled All the system clocks SYSCLKn are divided down from PLL output Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 127 PRODUCT PREVIEW Mal aad TMS320C6454 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 7 3 2 PLL Multiplier Control Register The PLL multiplier control register PLLM is shown in Figure 7 12 and described in Table 7 20 The PLLM register defines the input reference clock frequency multiplier in conjunction with the PLL divider ratio bits RATIO in the PLL controller pre divider register PREDIV 31 16 Reserved R 0 15 5 4 0 Reserved PLLM R 0 R W 0h LEGEND R W Read Write R Read only n value after reset Figure 7 12 PLL Multiplier Control Register PLLM Hex Address 029A 0110 Table 7 20 PLL Multiplier Control Register PLLM Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 4 0 PLLM PLL multiplier bits Defines the frequency multiplier of the input reference clo
85. output only pins indicating off state hi Z output leakage current Assumes the following conditions 6096 CPU utilization DDR2 at 5095 utilization 250 MHz 5096 writes 32 bits 5096 bit switching two 2 MHz McBSPs at 100 utilization 5096 switching two 75 MHz Timers at 100 utilization device configured for HPI32 mode with pull up resistors on pins room temperature 25 The actual current draw is highly application dependent For more details on core and I O activity see the TMS320C6455 54 Power Consumption Summary application report literature number SPRAAES Submit Documentation Feedback Device Operating Conditions 93 PRODUCT PREVIEW Mal aad TMS320C6454 49 Texas Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 64 Peripheral Information and Electrical Specifications 7 1 Parameter Information Tester Pin Electronics Data Sheet Timing Reference Point 429 3 5 nH Output sess 13 Unde T 70 500 eet see Note Device Pin ZF 4 0 1 85 pF see Note NOTE The data sheet provides timing at the device pin For output timing analysis the tester pin electronics and its transmission line effects must be taken into account A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect The transmission line is intended as a load only It is not necessary to add or subtract the tr
86. the Software PLL1 Controller By default SYSCLK4 is selected as CPU 8 clock rate e HPI peripheral bus width HPI WIDTH select Applies only when is enabled PCI EN pin 0 AEA14 0 HPI operates as an 16 default HPI bus is 16 bits wide HD 15 0 pins are used and the remaining HD 31 16 pins are reserved pins in the Hi Z state 1 HPI operates as an HPI32 e Device Endian mode LENDIAN AEA13 0 System operates in Big Endian mode 1 System operates in Little Endian mode default Note For proper C6454 device operation the AEA12 and AEA11 pins must be externally pulled down with a 1 kQ resistor at device reset 28 Device Overview Submit Documentation Feedback 4 TEXAS 5320 6454 INSTRUMENTS Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 2 3 Terminal Functions continued SIGNAL TYPE IPD IPU DESCRIPTION NAME NO AEA10 MACSEL1 M25 EMAC MDIO interface select bits MACSEL 1 0 AEA9 MACSELO M27 There are two configuration pins MACSEL 1 0 to select the EMAC MDIO interface gee P25 AEA 10 9 MACSEL 1 0 AEA7 N27 00 10 100 EMAC MDIO MII Mode Interface default AEA6 PCI 27 01 10 100 EMAC MDIO RMII Interface 6 PCIBG s 10 10 100 1000 EMAC MDIO GMII Mode Interface AEAS MCBSP1_EN U28 11 10 100 1000 with RGMII Mode Interface AEA4 T28 RGMII interface requires a 1 8 V or 1 5 V I O supply
87. the falling edge of RXC Similarly RXCTL carries RXDV on rising edge of RXC and RXERR on falling edge must be externally delayed relative to the data and control pins Figure 7 69 EMAC Receive Interface Timing RGMII Operation X Table 7 87 Switching Characteristics Over Recommended Operating Conditions for TXC RGMII Operation for 10 100 1000 Mbit s see Figure 7 70 720 850 e 1000 UNIT MIN MAX 10 Mbps 360 440 1 Cycle time TXC 100 Mbps 36 44 n 1000 Mbps 7 2 8 8 10 Mbps 0 40 lt 0 60 lt 2 tw TXCH Pulse duration TXC high 100 Mbps 0 40 0 60 te TxC ns 1000 Mbps O 45 trxc _0 55 tecrxe 10 Mbps 0 40 lt _0 60 torxc 3 tw TXCL Pulse duration TXC low 100 Mbps 0 40 tytxc 0 60 teTxC ns 1000 Mbps O 45 trxc _0 55 tecrxe 10 Mbps 0 75 4 Transition time 100 Mbps 0 75 ns 1000 Mbps 0 75 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 201 PRODUCT PREVIEW Mal aad L9naoad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 88 Switching Characteristics Over Recommended Operating Conditions for EMAC RGMII Transmit see Figure 7 70 720 850 NO PARAMETER 1000 UNIT MIN MAX su TXD TXCH Setup time transmit selected signals valid b
88. used by the EMAC MDIO peripheral 00 10 100 EMAC MDIO with MII Interface default 01 10 100 EMAC MDIO with RMII Interface 10 10 100 1000 EMAC MDIO with GMII Interface 11 10 100 1000 EMAC MDIO with RGMII Interface For more detailed information on the SEL 1 0 control pin selections see Table 3 3 AEA8 P25 IPD PCI 2 EEPROM Auto Initialization PCI_EEAI PCI auto initialization via external 2 EEPROM 0 PCI auto initialization through external 2 EEPROM is disabled The PCI peripheral uses the specified PCI default values default 1 PCI auto initialization through external 2 EEPROM is enabled The PCI peripheral is configured through external 2 EEPROM provided the PCI peripheral pins are enabled PCI_EN 1 Note If the PCI pin function is disabled PCI_EN pin 0 this pin must not be pulled up AEA7 N27 IPD For proper C6454 device operation do not oppose the IPD on this pin AEA6 U27 IPD PCI Frequency Selection PCI66 Selects the operating frequency of the PCI either 33 MHz or 66 MHz 0 PCI operates at 33 MHz default 1 PCI operates at 66 MHz Note If the PCI pin function is disabled PCI_EN pin 0 this pin must not be pulled up AEAS U28 IPD McBSP1 pin function enable bit MCBSP1 EN Selects which function is enabled on the McBSP1 GPIO multiplexed pins 0 GPIO pin function enabled default This means all multiplexed McBSP1 GPIO pins function
89. 0 0180 003C Reserved 0180 0040 EVTCLRO Event Clear Register 0 Events 31 0 0180 0044 EVTCLR1 Event Clear Register 1 0180 0048 EVTCLR2 Event Clear Register 2 0180 004C EVTCLRS Event Clear Register 3 0180 0050 0180 007C Reserved 0180 0080 EVTMASKO Event Mask Register 0 Events 31 0 0180 0084 EVTMASK1 Event Mask Register 1 0180 0088 EVTMASK2 Event Mask Register 2 0180 008C EVTMASK3 Event Mask Register 3 0180 0090 0180 009C Reserved 0180 00 0 MEVTFLAGO Masked Event Flag Status Register 0 Events 31 0 0180 00A4 MEVTFLAG1 Masked Event Flag Status Register 1 0180 00A8 MEVTFLAG2 __ Masked Event Flag Status Register 2 0180 00 MEVTFLAG3 __ Masked Event Flag Status Register 0180 00 0 0180 00 5 Reserved 0180 00 0 EXPMASKO Exception Mask Register 0 Events 31 0 0180 00 4 EXPMASK1 Exception Mask Register 1 0180 00C8 EXPMASK2 Exception Mask Register 2 0180 00CC EXPMASK3 Exception Mask Register 3 0180 0000 0180 00DC Reserved 0180 00 0 MEXPFLAGO _ Masked Exception Flag Register 0 0180 00 4 MEXPFLAG1 Masked Exception Flag Register 1 0180 00 8 MEXPFLAG2 _ Masked Exception Flag Register 2 0180 00 MEXPFLAGS _ Masked Exception Flag Register 3 0180 00 0 0180 00 Reserved 0180 0100 Reserved 0180 0104 INTMUX1 Interrupt Multiplexor Register 1 0180 0108 INTMUX2 Interrupt Multiplexor Register 2 0180 010 INTMUX3 Interrupt Multiplexor Register 3 0180 0110 0180 013C Reserved 0180 0140 AEGMUXO Advan
90. 0 and PCI EN are the boot configuration pins during device reset Table 7 15 Switching Characteristics Over Recommended Operating Conditions During Reset see Figure 7 9 720 850 NO PARAMETER 1000 UNIT MIN MAX 9 typorH RsTaTH Delay time POR high AND RESET high to RESETSTAT high 15000C ns 1 1 CLKIN1 clock frequency in ns For Figure 7 8 note the following e Z group consists of all 1 0 4 and O Z pins except for Low and High group pins Pins become high impedance as soon as their respective power supply has reached normal operating coditions Pins remain in high impedance until configured otherwise by their respective peripheral Low group consists of MTXDO RMTXDO MTXD1 RMTXD1 MTXD2 RMTXD2 MTXD3 RMTXD3 MTXD4 RMTXD4 MTXEN RMTXEN and ABUSREQ Pins become low as soon as their respective power supply has reached normal operating conditions Pins remain low until configured otherwise by their respective peripheral e High group consists of AHOLD and HRDY PIRDY Pins become high as soon as their respective power supply has reached normal operating conditions Pins remain high until configured otherwise by their respective peripheral All peripherals must be enable through software following a Power on Reset for more details see Section 7 6 1 Power on Reset For power supply sequence requirements see Section 7 3 1 Power Supply Sequencing 120 C64x Peripheral Information and El
91. 006 REVISED DECEMBER 2006 Table 2 3 Terminal Functions continued SIGNAL TYPE IPD PU DESCRIPTION NAME NO RSV17 AE21 A RSV18 E13 A RSV19 F18 A RSV20 U29 A RSV21 A6 A RSV22 B26 RSV23 C26 RSV24 B6 RSV25 C6 RSV26 AJ11 A RSV27 AH11 A RSV36 AD11 VO Z IPU RSV37 AD9 VO Z IPU RSV38 AG10 VO Z IPU RSV39 AG11 VO Z IPU RSV40 AJ12 VO Z IPU RSV41 W28 O Z IPU RSV42 Y26 O Z IPU RSV43 Y25 O Z IPU Reserved Leave unconnected do not connect to power or ground RSV44 Y27 O Z RSV45 AF15 RSV46 AG15 RSV47 AF17 O Z RSV48 AG18 O Z RSV49 AG22 O Z RSV50 AF23 O Z RSV51 AF18 O Z RSV52 AG19 O Z RSV53 21 O Z RSV54 AF22 O Z RSV55 AH18 RSV56 AJ18 RSV57 AJ22 RSV58 AH22 RSV59 AH17 l RSV60 AJ19 RSV61 21 RSV62 AH23 l RSV28 N7 A RSV29 N6 A Reserved These pins must be connected directly to Vss for proper device RSV30 P23 A operation RSV31 P24 A RSV32 D25 Reserved This pin must be connected to the 1 8 V I O supply DVppig via 1 resistor for proper device operation RSV33 C25 Reserved This pin must be connected directly to ground for proper device operation Submit Documentation Feedback Device Overview 37 PRODUCT PREVIEW M3al aad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com Table 2 3 Terminal Functions continued
92. 029A 0114 PREDIV PLL Pre Divider Control Register 029A 0118 Reserved 029A 011G Reserved 029A 0120 Reserved 029A 0124 2 Reserved 029A 0128 Reserved 029A 012C Reserved 029A 0130 Reserved 029A 0134 Reserved 029A 0138 PLLCMD PLL Controller Command Register 029A 013G PLLSTAT PLL Controller Status Register 029A 0140 ALNCTL PLL Controller Clock Align Control Register 029A 0144 DCHANGE PLLDIV Ratio Change Status Register 029A 0148 Reserved 029A 014G Reserved 029A 0150 SYSTAT SYSCLK Status Register 029A 0154 5 Reserved 029A 0158 Reserved 029A 015C Reserved 029A 0160 PLLDIV4 PLL Controller Divider 4 Register 029A 0164 PLLDIV5 PLL Controller Divider 5 Register 029A 0168 029B FFFF Reserved 126 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 7 7 3 PLL1 Controller Register Descriptions This section provides a description of the PLL1 controller registers For details on the operation of the PLL controller module see the TMS320C645x DSP Software Programmable Phase Locked Loop PLL Controller User s Guide literature number SPRUE56 NOTE The PLL1 controller registers can only be accessed using the CPU or the emulator Not all of the registers documented in the TMS320C645x DSP Software Programmable Phase Locked Loop
93. 02A2 0394 DFMPPRXY2 Destination FIFO Memory Protection Proxy Register 2 02A2 0398 02A2 03BC Reserved 02A2 03C0 DFOPT3 Destination FIFO Options Register 3 02 2 03 4 DFSRC3 Destination FIFO Source Address Register 3 02A2 03C8 DFCNT3 Destination FIFO Count Register 3 02A2 03CC DFDST3 Destination FIFO Destination Address Register 3 02A2 03D0 DFBIDX3 Destination FIFO BIDX Register 3 02A2 03D4 DFMPPRXY3 _ Destination FIFO Memory Protection Proxy Register 02A2 03D8 02A2 7FFF Reserved Table 7 7 EDMA3 Transfer Controller 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A2 8000 PID Peripheral Identification Register 02A2 8004 TCCFG Configuration Register 02A2 8008 02A2 80FC Reserved 02A2 8100 TCSTAT Channel Status Register 02 2 8104 02A2 811C Reserved 02A2 8120 ERRSTAT Error Register 02A2 8124 ERREN Error Enable Register 02A2 8128 ERRCLR Error Clear Register 02A2 812C ERRDET Error Details Register 02A2 8130 ERRCMD Error Interrupt Command Register 02A2 8134 02A2 813C Reserved 02A2 8140 RDRATE Read Rate Register 02A2 8144 02A2 823C Reserved 02A2 8240 SAOPT Source Active Options Register 02A2 8244 SASRC Source Active Source Address Register 02A2 8248 SACNT Source Active Count Register 02A2 824C SADST Source Active Destination Address Register 02A2 8250 SABIDX Source Active Source B Index Register
94. 02C0 013C PCILGINTMIR PCI Max Latency Min Grant Interrupt Pin Interrupt Line Mirror Register 02 0 0140 02 0 017F Reserved 02C0 0180 PCISLVCNTL PCI Slave Control Register 02 0 0184 02 0 01BF Reserved 02 0 01 0 PCIBAROTRL PCI Slave Base Address 0 Translation Register 02C0 0104 PCIBAR1TRL PCI Slave Base Address 1 Translation Register 02 0 01C8 PCIBAR2TRL PCI Slave Base Address 2 Translation Register 02C0 01CC PCIBARSTRL Slave Base Address Translation Register 02 0 01D0 PCIBAR4TRL PCI Slave Base Address 4 Translation Register 02C0 01D4 PCIBARBTRL PCI Slave Base Address 5 Translation Register 02 0 0108 02C0 01DF Reserved 02 0 01 0 PCIBAROMIR PCI Base Address Register 0 Mirror Register 02 0 01E4 PCIBAR1MIR Base Address Register 1 Mirror Register 02C0 01E8 PCIBAR2MIR PCI Base Address Register 2 Mirror Register 02 0 01EC PCIBAR3MIR PCI Base Address Register Mirror Register 02 0 01 0 PCIBARAMIR PCI Base Address Register 4 Mirror Register 02 0 01 4 PCIBAR5MIR PCI Base Address Register 5 Mirror Register 02 0 01F8 02C0 02FF Reserved 02 0 0300 PCIMCFGDAT Master Configuration IO Access Data Register 02 0 0304 PCIMCFGADR PCI Master Configuration IO Access Address Register Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 209 PRODUCT PREVIEW TMS320C6454 49 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS31
95. 058 Reserved Submit Documentation Feedback C64x Megamodule 89 PRODUCT PREVIEW Mal aad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 Device Operating Conditions 6 INSTRUMENTS www ti com 6 1 Absolute Maximum Ratings Over Operating Case Temperature Range Unless Otherwise Noted Supply voltage range CVpp 2 0 5 V to 1 5 V DVpp33 2 0 5 V to 4 2 V DV aris DVppig 0 5 V t0 2 5 V PLLV1 PLLV2 2 0 5 V to 2 5 V Input voltage VI range 3 3 V pins except PCI capable pins 0 5 V to DVpp33 0 5V PCl capable pins 0 5 V to DVpp33 0 5V RGMII pins 0 5 V to 2 5 V DDR2 memory controller pins 0 5 V to 2 5 V Output voltage VO range 3 3 V pins except PCI capable pins 0 5 V to DVpp33 0 5V PCl capable pins 0 5 V to DVpp33 0 5V RGMII pins 0 5 V to 2 5 V DDR2 memory controller pins 0 5V to 2 5 V Operating case temperature range default 0 C to 90 C Storage temperature range 65 C to 150 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum
96. 0E14 Event Queue 0 Entry Register 14 02A0 043G Q0E15 Event Queue 0 Entry Register 15 102 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com Table 7 4 Channel Controller Registers continued 5320 6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 0440 Q1E0 Event Queue 1 Entry Register 0 02A0 0444 Q1E1 Event Queue 1 Entry Register 1 02A0 0448 1 2 Event Queue 1 Entry Register 2 02A0 044C Q1E3 Event Queue 1 Entry Register 3 02A0 0450 Q1E4 Event Queue 1 Entry Register 4 02A0 0454 Q1E5 Event Queue 1 Entry Register 5 02A0 0458 Q1E6 Event Queue 1 Entry Register 6 02A0 045C Q1E7 Event Queue 1 Entry Register 7 02 0 0460 1 8 Event Queue 1 Entry Register 8 02A0 0464 Q1E9 Event Queue 1 Entry Register 9 02 0 0468 1 10 Event Queue 1 Entry Register 10 02A0 046C Q1E11 Event Queue 1 Entry Register 11 02A0 0470 Q1E12 Event Queue 1 Entry Register 12 02A0 0474 Q1E13 Event Queue 1 Entry Register 13 02A0 0478 Q1E14 Event Queue 1 Entry Register 14 02A0 047C Q1E15 Event Queue 1 Entry Register 15 02A0 0480 Q2E0 Event Queue 2 Entry Register 0 02A0 0484 Q2E1 Event Queue 2 Entry Register 1 02A0 0488 Q2E2 Event Queue 2 En
97. 1 Ethernet MAC EMAC Control Registers EMAC MII and GMII Electrical Data Timing Updated Figure 7 59 MRCLK Timing EMAC Receive MII and GMII Operation Updated Figure 7 60 Timing EMAC Transmit MII GMII Operation Changed Table 7 77 title to Switching Characteristics Over Recommended Operating Conditions for GMTCLK GMII Operation Updated Figure 7 61 GMTCLK Timing EMAC Transmit GMII Operation Updated Figure 7 64 EMAC Transmit Interface Timing GMII Operation EMAC RMII Electrical Data Timing Added the following tables and figures Table 7 82 Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit 10 100 Mbit s Figure 7 66 EMAC Transmit Interface Timing RMII Operation Table 7 83 Timing Requirements for EMAC RMII Input Receive for 100 Mbps Figure 7 67 EMAC Receive Interface Timing RMII Operation Revision History Submit Documentation Feedback 4 TEXAS 5320 6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 C6454 Revision History continued SEE ADDITIONS MODIFICATIONS DELETIONS Section 7 14 3 3 Section 7 14 4 1 Section 7 16 1 Section 7 16 3 Section 8 EMAC RGMIl Electrical Data Timing Updated Table 7 84 Switching Characteristics Over Recommended Operating Conditions for EMAC RGREFCLK RGMII Operation Updated Figure 7 68 RGREFCLK Timing Changed
98. 1 3 3 ns 4 is 1 pst MRCLK r Input Figure 7 59 MRCLK Timing EMAC Receive MII and GMII Operation Table 7 76 Timing Requirements for MTCLK MII and GMII Operation see Figure 7 60 720 850 NO 1000 UNIT 100 Mbps 10 Mbps MIN MAX MIN MAX 1 c MTCLK Cycle time MTCLK 40 400 ns 2 tuMTCLKH Pulse duration MTCLK high 14 140 3 tw MTCLKL Pulse duration MTCLK low 14 140 4 Transition time MTCLK 3 3 ns h 1 1 gt 3 e Input Figure 7 60 MTCLK Timing EMAC Transmit MII and GMII Operation Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 195 PRODUCT PREVIEW M3l aad TMS320C6454 49 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 77 Switching Characteristics Over Recommended Operating Conditions for GMTCLK GMII Operation see Figure 7 61 720 850 NO 1000 UNIT 1000 Mbps MIN MAX 1 te GMTCLK Cycle time GMTCLK 8 2 twGMTCLKH Pulse duration GMTCLK high 2 8 3 tw GMTCLKL Pulse duration GMTCLK low 28 EM 4 tyGMTCLK Transition time GMTCLK 1 is w i 4 pues 7 1 gt i amu XN Output Figure 7 61 GMTCLK Timing EMAC Transmit GMII Operation Table 7 78 Timing Requiremen
99. 1 is on Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 145 PRODUCT PREVIEW MalAddd TMS320C6454 49 Texas Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 8 4 PLL2 Controller Input Clock Electrical Data Timing Table 7 39 Timing Requirements for 2 see Figure 7 30 720 850 NO 1000 UNIT MIN MAX 1 te CLKIN2 Cycle time CLKIN2 37 5 80 ns 2 tw CLKIN2H Pulse duration CLKIN2 high 0 4C ns 3 tw CLKIN2L Pulse duration CLKIN2 low 0 4C ns 4 tyCLKIN2 Transition time CLKIN2 1 2 ns 5 U CLKIN2 Period jitter peak to peak CLKIN2 100 ps 1 The reference points for the rise and fall transitions are measured at 3 3 V Vi MAX and Vj MIN 2 CLKIN cycle time in ns For example when CLKIN2 frequency is 25 MHz use C 40 ns 3 If EMAC is enabled with RGMII or GMII CLKIN2 cycle time must be 40 ns 25 MHz 5 gt je h 1 L 2 ae ome N ZA NE INA k 3 4 gt l le Figure 7 30 CLKIN2 Timing 146 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback K Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 9 DDR2 Memory Controller 7 9 1 The 32 bit DDR2 Memory Controller bus of
100. 10 GPIOCTL Mode control for GPIO 0 Set GPIO to disabled mode 1 Set GPIO to enabled mode 9 Reserved Reserved 8 TIMEROCTL Mode control for Timer 0 0 Set Timer 0 to disabled mode 1 Set Timer 0 to enabled mode 7 Reserved Reserved 6 TIMER1CTL Mode control for Timer 1 0 Set Timer 1 to disabled mode 1 Set Timer 1 to enabled mode 5 Reserved Reserved 4 EMACCTL Mode control for EMAC MDIO 0 Set EMAC MDIO to disabled mode 1 Set EMAC MDIO to enabled mode 3 0 Reserved Reserved 58 Device Configuration Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 3 4 3 Peripheral Configuration Register 1 Description The Peripheral Configuration Register PERCFG1 is used to enable the EMIFA and DDR2 Memory Controller EMIFA and the DDR2 Memory Controller do not have corresponding status bits in the Peripheral Status Registers The EMIFA and DDR2 Memory Controller peripherals can be used within 16 SYSCLK3 cycles after EMIFACTL and DDR2CTL set to 1 Once EMIFACTL and DDR2CTL are set to 1 they cannot be set to 0 Note that if the DDR2 Memory Controller and EMIFA are disabled at reset through the device configuration pins DDR2 EN ABAO and EMIFA ABA1 they cannot be enabled through the PERCFG1 register 31 8 Reserved R 0x00 7 2 1 0 Reserved DDR2CTL EMIFACTL R 0x00 R W 0 R W 0 LEGEND R W
101. 16 V18 V23 W7 W11 W13 W15 W17 W19 W24 Y6 Y23 AA2 AA7 AA24 AB6 AB23 AC7 AC8 AC10 AC12 AC14 AC16 AC18 GND Ground pins Submit Documentation Feedback Device Overview 45 PRODUCT PREVIEW Mal aad TMS32006454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com Table 2 3 Terminal Functions continued SIGNAL NAME NO TYPE IPD IPU 2 DESCRIPTION AC20 AC22 AC24 AC28 AD6 AD13 AD15 AD17 AD19 AD21 AD23 AE4 AE7 AE16 AE18 AE20 AE22 AE24 AF2 AF19 AF21 AG13 16 20 24 1 15 19 21 25 29 AJ8 AJ14 AJ16 AJ20 24 GND Ground pins 46 Device Overview Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 2 8 Development 2 8 1 Development Support In case the customer would like to develop their own features and software on the C6454 device TI offers an extensive line of development tools for the TMS320C6000 D
102. 1A APRIL 2006 REVISED DECEMBER 2006 Table 7 98 PCI Back End Configuration Registers continued Mal aad m ce ACRONYM DSP ACCESS REGISTER NAME 02C0 0308 PCIMCFGCMD PCI Master Configuration IO Access Command Register 02 0 030C 02 0 030F Reserved 02C0 0310 PCIMSTCFG PCI Master Configuration Register Table 7 99 DSP to PCI Address Translation Registers HEXRDBRESS BANGE ACRONYM DSP ACCESS REGISTER NAME 02 0 0314 PCIADDSUBO PCI Address Substitute 0 Register 02 0 0318 PCIADDSUB1 PCI Address Substitute 1 Register 02 0 031C PCIADDSUB2 PCI Address Substitute 2 Register 02 0 0320 PCIADDSUB3 PCI Address Substitute Register 02 0 0324 PCIADDSUBA PCI Address Substitute 4 Register 02 0 0328 PCIADDSUB5 PCI Address Substitute 5 Register 02C0 032C PCIADDSUB6 PCI Address Substitute 6 Register 02 0 0330 PCIADDSUB7 PCI Address Substitute 7 Register 02 0 0334 PCIADDSUBS8 PCI Address Substitute 8 Register 02 0 0338 PCIADDSUB9 PCI Address Substitute 9 Register 02C0 033C PCIADDSUB10 PCI Address Substitute 10 Register 02 0 0340 PCIADDSUB11 PCI Address Substitute 11 Register 02 0 0344 PCIADDSUB12 PCI Address Substitute 12 Register 02 0 0348 PCIADDSUB13 PCI Address Substitute 13 Register 02C0 034C PCIADDSUB14 PCI Address Substitute 14 Register 02 0
103. 2 0210 0182 02FF Reserved 0184 1000 L2DCPUARBU 120 CPU Arbitration Control Register 0184 1004 L2DIDMAARBU L2D IDMA Arbitration Control Register 0184 1008 L2DSDMAARBU L2D Slave DMA Arbitration Control Register 0184 100C L2DUCARBU L2D User Coherence Arbitration Control Resgiter 0184 1010 0184 103F Reserved 0184 1040 L1DCPUARBD L1D CPU Arbitration Control Register 0184 1044 L1DIDMAARBD 110 IDMA Arbitration Control Register 0184 1048 L1DSDMAARBD 110 Slave DMA Arbitration Control Register 0184 104C L1DUCARBD 110 User Coherence Arbitration Control Resgiter Table 5 11 Device Configuration Registers Chip Level Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 02A8 0000 DEVSTAT Device Status Register jain uc e 2 02 8 0004 PRI Priority Allocation Register Sets priority for Master peripherals 02A8 0008 JTAGID B BSDL Identification Provides 32 bit JTAG ID of 02A8 000C 02AB FFFF z Reserved 02 0000 Reserved 02AC 0004 PERLOCK Peripheral Lock Register 02AC 0008 PERCFGO Peripheral Configuration Register 0 02AC 000C Reserved 02AC 0010 Reserved 02 0014 PERSTATO Peripheral Status Register 0 02AC 0018 PERSTAT1 Peripheral Status Register 1 02 001C 02 001 Reserved 02AC 0020 EMACCFG EMAC Configuration Register 02AC 0024 02AC 002B Reserved 02AC 002C PERCFG1 Peripheral Configuration Register 1 02AC 0030 02 0053 Reserved 02AC 0054 EMUBUFPD Emulator Buffer Powerdown Register 02AC 0
104. 248 SACNT Source Active Count Register 02A3 824C SADST Source Active Destination Address Register 02A3 8250 SABIDX Source Active Source B Index Register 02A3 8254 SAMPPRXY Source Active Memory Protection Proxy Register 02A3 8258 SACNTRLD Source Active Count Reload Register 02A3 825C SASRCBREF _ Source Active Source Address B Reference Register 02A3 8260 SADSTBREF Source Active Destination Address B Reference Register 02A3 8264 02A3 827C Reserved 02A3 8280 DFCNTRLD Destination FIFO Set Count Reload 02A3 8284 DFSRCBREF _ Destination FIFO Set Destination Address B Reference Register 02A3 8288 DFDSTBREF _ Destination FIFO Set Destination Address B Reference Register 02A3 828C 02A3 82FC Reserved 02A3 8300 DFOPTO Destination FIFO Options Register 0 02A3 8304 DFSRCO Destination FIFO Source Address Register 0 02A3 8308 DFCNTO Destination FIFO Count Register 0 02A3 830C DFDSTO Destination FIFO Destination Address Register 0 02A3 8310 DFBIDXO Destination FIFO BIDX Register 0 02A3 8314 DFMPPRXYO Destination FIFO Memory Protection Proxy Register 0 02A3 8318 02A3 833C Reserved 02A3 8340 DFOPT1 Destination FIFO Options Register 1 02A3 8344 DFSRC1 Destination FIFO Source Address Register 1 02A3 8348 DFCNT1 Destination FIFO Count Register 1 02A3 834C DFDST1 Destination FIFO Destination Address Register 1 02A3 8350 DFBIDX1 Destination FIFO BIDX Register 1 02A3 8354 DFMPPRXY1 Destination FIFO Memory Protection Proxy Register 1 02A3 8358 02A3 837C R
105. 32KB L2 ROM C64x Megamodule Megamodule Revision ID Register address location See Section 5 6 Megamodule Revision Revision ID 0181 2000h JTAG BSDL ID JTAGID register address location 0x02A80008 See Sachan 3 0 do Ae Register Frequency MHz 720 850 and 1000 1 GHz mS 5 1 39 ns C6454 720 1 17 ns C6454 850 1 ns 6454 1000 1 GHz CPU 1 25 V 1000 Core V 1 2 V 850 720 voltage 1 5 1 8 EMAC RGMII and VO V 51 8 1 8 and 3 3 V I O Supply Voltage PLL1 and PLL1 Controller Options CLKIN1 frequency multiplier Bypass x1 x15 x20 x25 x30 x32 PLL2 CLKIN2 frequency multiplier DDR2 Memory Controller and EMAC support only x20 697 Pin Flip Chip Plastic BGA ZTZ BGA Package 697 Plastic BGA GTZ Process Technology 0 09 um Product Status Product Preview PP Advance Information Al PP or Production Data PD 1 PRODUCT PREVIEW information concerns experimental products designated as TMX that are in the formative or design phase of development Characteristic data and other specifications are design goals Texas Instruments reserves the right to change or discontinue these products without notice 6 Device Overview Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 Table 2 1 Characte
106. 4 MAR161 Controls EMIFA CE2 Range A100 0000 A1FF FFFF 0184 8288 MAR162 Controls EMIFA CE2 Range A200 0000 A2FF FFFF 0184 828C MAR163 Controls EMIFA CE2 Range A300 0000 FFFF 0184 8290 MAR164 Controls EMIFA CE2 Range A400 0000 A4FF FFFF Submit Documentation Feedback C64x4 Megamodule 85 PRODUCT PREVIEW Mal aad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 5 8 Megamodule Cache Configuration Registers continued 6 INSTRUMENTS www ti com HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 8294 MAR165 Controls EMIFA CE2 Range A500 0000 ASFF FFFF 0184 8298 MAR166 Controls EMIFA CE2 Range A600 0000 A6FF FFFF 0184 829C MAR167 Controls EMIFA CE2 Range A700 0000 A7FF FFFF 0184 82A0 MAR168 Controls EMIFA CE2 Range A800 0000 ABFF FFFF 0184 82A4 MAR169 Controls EMIFA CE2 Range A900 0000 A9FF FFFF 0184 82A8 MAR170 Controls EMIFA 2 Range 00 0000 AAFF FFFF 0184 82AC MAR171 Controls EMIFA CE2 Range 00 0000 ABFF FFFF 0184 82 0 MAR172 Controls EMIFA 2 Range 00 0000 ACFF FFFF 0184 82B4 MAR173 Controls EMIFA CE2 Range ADOO 0000 ADFF FFFF 0184 82B8 MAR174 Controls EMIFA CE2 Range 00 0000 AEFF FFFF 0184 82BC MAR175 Controls EMIFA CE2 Range 00 0000 AFFF
107. 4 System Interconnect On the C6454 device the C64x Megamodule the EDMAGS transfer controllers and the system peripherals are interconnected through two switch fabrics The switch fabrics allow for low latency concurrent data transfers between master peripherals and slave peripherals Through a switch fabric the CPU can send data to the EMIFA without affecting a data transfer between the PCI and the DDR2 memory controller The switch fabrics also allow for seamless arbitration between the system masters when accessing system slaves 4 1 Internal Buses Bridges and Switch Fabrics Two types of buses exist in the C6454 device data buses and configuration buses Some C6454 peripherals have both a data bus and a configuration bus interface while others only have one type of interface Furthermore the bus interface width and speed varies from peripheral to peripheral Configuration buses are mainly used to access the register space of a peripheral and the data buses are used mainly for data transfers However in some cases the configuration bus is also used to transfer data For example data is transferred to the McBSP via its configuration bus Similarly the data bus can also be used to access the register space of a peripheral For example the EMIFA and DDR2 memory controller registers are accessed through their data bus interface The C64x Megamodule the EDMAS traffic controllers and the various system peripherals can be classified int
108. 5 MTXEN RMTXEN MTXEN RMTXEN MTXEN J4 MCRS RMCRSDV MCRS RMCRSDV MCRS K3 MCOL MCOL MCOL K5 GMTCLK GMTCLK H1 MRCLK MRCLK MRCLK N4 MTCLK REFCLK MTCLK RMREFCLK MTCLK N3 GMDIO MDIO MDIO MDIO M5 GMDCLK MDCLK MDCLK MDCLK Using the RMII Mode of the EMAC The Ethernet Media Access Controller EMAC contains logic that allows it to communicate using the Reduced Media Independent Interface RMII protocol This logic must be taken out of reset before being used To use the RMII mode of the EMAC follow these steps 1 Enable the EMAC MDIO through the Device State Control Registers Unlock the PERCFGO register by writing OxOFOA to the PERLOCK register Set bit 4 in the PERCFGO register within 16 SYSCLKS clock cycles to enable the EMAC MDIO Poll the PERSTATO register to verify state change 2 Initialize the EMAC MDIO as needed 3 Release the RMII logic from reset by clearing the bit of the EMAC Configuration Register see Section 3 4 5 As described in the previous section the RMII mode of the EMAC must be selected by setting MACSEL 1 0 01b at device reset Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 189 PRODUCT PREVIEW MalAddd TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 190 www ti com Interface Mode Clocking The on chip PLL2 and PLL2 Controller
109. 58 MAR214 Controls EMIFA CES Range D600 0000 D6FF FFFF 0184 835C MAR215 Controls EMIFA CES Range D700 0000 D7FF FFFF 0184 8360 MAR216 Controls EMIFA CES Range 0800 0000 D8FF FFFF 0184 8364 MAR217 Controls EMIFA CES Range 0900 0000 D9FF FFFF 0184 8368 MAR218 Controls EMIFA CES Range DA00 0000 DAFF FFFF 0184 836C MAR219 Controls EMIFA CES Range 0000 DBFF FFFF 0184 8370 MAR220 Controls EMIFA CES Range 0000 DCFF FFFF 0184 8374 MAR221 Controls EMIFA 5 Range DD00 0000 DDFF FFFF 0184 8378 MAR222 Controls EMIFA CE5 Range DE00 0000 DEFF FFFF 0184 837C MAR223 Controls EMIFA CES Range DF00 0000 DFFF FFFF 0184 8380 MAR224 Controls DDR2 Range E000 0000 EOFF FFFF 0184 8384 MAR225 Controls DDR2 Range E100 0000 E1FF FFFF 0184 8388 MAR226 Controls DDR2 Range E200 0000 E2FF FFFF 0184 838C MAR227 Controls DDR2 Range E300 0000 E3FF FFFF 0184 8390 MAR228 Controls DDR2 Range E400 0000 E4FF FFFF 0184 8394 MAR229 Controls DDR2 Range E500 0000 FFFF 0184 8398 MAR230 Controls DDR2 Range E600 0000 E6FF FFFF 0184 839C MAR231 Controls DDR2 Range E700 0000 E7FF FFFF 0184 83A0 MAR232 Controls DDR2 Range E800 0000 E8FF FFFF 0184 83A4 MAR233 Controls DDR2 Range E900 0000 E9FF FFFF 0184 83A8 MAR234 Controls DDR2 Range 00 0000 EAFF FFFF 0184 83AC MAR235 Controls DDR2 Range EBOO 0000 EBFF FFF
110. 6 3h 8 Divide frequency by 8 4h 7h 10 to 16 Divide frequency by 10 to divide frequency by 16 8h 1Fh Reserved do not use 130 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 7 7 3 5 PLL Controller Divider 5 Register The PLL controller divider 5 register PLLDIV5 is shown in Figure 7 15 and described in Table 7 23 31 16 Reserved R 0 15 14 5 4 0 D5EN Reserved RATIO R W 1 R 0 R W 3 LEGEND R W Read Write Read only n value after reset Figure 7 15 PLL Controller Divider 5 Register PLLDIV5 Hex Address 029A 0164 Table 7 23 PLL Controller Divider 5 Register PLLDIV5 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 Dn4EN Divider 4 enable bit 0 Divider 4 is disabled No clock output 1 Divider 4 is enabled 14 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 4 0 RATIO O 1Fh Divider ratio bits 0 1 Divide frequency by 1 1h 2 Divide frequency by 2 2h 3 Divide frequency by 3 3h 4 Divide frequency by 4 4h 7h 5 to 8 Divide frequency by 5 to divide frequency by 8 8h
111. 6 Timing Requirements for McBSP as SPI Master or Slave CLKSTP 10b CLKXP 1 see Figure 7 56 720 850 NO 1000 UNIT MASTER SLAVE MIN MAX MIN MAX tsu DRV CKXH Setup time DR valid before CLKX high 12 2 18 ns th CKXH DRV Hold time DR valid after CLKX high 4 5 36P ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use 1 ns 2 Forall SPI Slave modes CLKG is programmed as 1 6 of the CPU clock by setting CLKSM CLKGDV 1 Table 7 67 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave CLKSTP 10b CLKXP 10 see Figure 7 56 720 850 NO PARAMETER 1000 UNIT MASTER SLAVE MIN MAX MIN MAX 1 th CKXH FXL Hold time FSX low after CLKX high T 2 T 3 ns 2 ta FXL CKXL Delay time FSX low to CLKX low 9 H 2 H 3 ns 3 ta CKXL DXV Delay time CLKX low to DX valid 2 4 18 2 8 30P 17 ns mng EIU INN 8 laFXL DXV Delay time FSX low to DX valid 12P 2 24P 17 ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 2 For all SPI Slave modes CLKG is programmed as 1 6 of the CPU clock by setting CLKSM CLKGDV 1 3 S Sample rate generator input clock 6P if CLKSM 1 P 1 CPU clock frequency S Sample rate generator input clock P_clks if CLKSM 0 P_clks CLKS period T CLKX period 1 CL
112. 64x M unit doubles the multiply throughput versus the C64x core by performing four 16 bit x 16 bit multiply accumulates MACs every clock cycle Thus eight 16 bit x 16 bit MACs can be executed every cycle on the C64x core At a 1 GHz clock rate this means 8000 16 bit MMACs can occur every second Moreover each multiplier on the C64x4 core can compute one 32 bit x 32 bit MAC or four 8 bit x 8 bit MACs every clock cycle The C6454 DSP integrates a large amount of on chip memory organized as a two level memory system The level 1 L1 program and data memories on the C6454 device are 32KB each This memory can be configured as mapped RAM cache or some combination of the two When configured as cache L1 program L1P is a direct mapped cache where as L1 data L1D is a two way set associative cache The level 2 L2 memory is shared between program and data space and is 1048KB in size L2 memory can also be configured as mapped RAM cache or some combination of the two The C64x Megamodule also has a 32 bit peripheral configuration CFG port an internal DMA IDMA controller a system component with reset boot control interrupt exception control a power down control and a free running 32 bit timer for time stamp The peripheral set includes an inter integrated circuit bus module I2C two multichannel buffered serial ports McBSPs a user configurable 16 bit or 32 bit host port interface HPI16 HPI32 a peripheral component interconnect
113. 7 0 4 Kr 5 19 0 1 01 10 41710 roe 11 AED 63 0 C A Q X Q X Q 8 KL 8 ASADS ASRE B eee j r e AAOE ASOE 4 12 12 A O Oooo The following parameters are programmable via the EMIFA Chip Select n Configuration Register CESECn Read latency R_LTNCY 1 2 or 3 cycle read latency Write latency W_LTNCY 0 1 2 or 3 cycle read latency ACEx assertion length EXT For standard SBSRAM or ZBT SRAM interface goes inactive after the final command has been issued CE_EXT 0 For synchronous FIFO interface ACEx is active when ASOE is active 1 Function of ASADS ASRE R_ENABLE For standard SBSRAM or ZBT SRAM interface ASADS ASRE acts as ASADS with deselect cycles R_ENABLE 0 For FIFO interface ASADS ASRE acts as SRE with NO deselect cycles R_ENABLE 1 In this figure W_LTNCY 1 CE EXT 0 R ENABLE 0 and SSEL 1 AAOE ASOE and AAWE ASWE operate as ASOE and ASWE respectively during programmable synchronous interface accesses Figure 7 38 Programmable Synchronous Interface Write Timing for EMIFA With Write Latency 1 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 157 PRODUCT PREVIEW Mal aad TMS32006454 Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006
114. 7 5 1 Interrupt Sources and Interrupt Controller The CPU interrupts on the C6454 device are configured through the C64x Megamodule Interrupt Controller The interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU interrupt inputs the CPU exception input or the advanced emulation logic Table 8 4 shows the mapping of system events to the interrupt controller inputs Event numbers 0 31 correspond to the default interrupt mapping of the device The remaining events must be mapped using software For more information on the Interrupt Controller see the TMS320C64x Megamodule Reference Guide literature number SPRU871 Table 7 10 C6454 DSP Interrupts EVENT NUMBER INTERRUPT EVENT INTERRUPT SOURCE 00 EVTO Interrupt Controller output of event combiner 0 for events 1 31 10 Interrupt Controller output of event combiner 1 for events 32 63 20 2 Interrupt Controller output of event combiner 2 for events 64 95 30 Interrupt Controller output of event combiner 3 for events 96 127 4 80 Reserved Reserved Do not use EMU interrupt for 9 2 EMU_DTDMA 1 Host scan access 2 DTDMA transfer complete AET interrupt 1002 Reserved Reserved Do not use 112 EMU_RTDXRX EMU real time data exchange RTDX receive complete 120 EMU RTDXTX EMU RTDX transmit complete 1302 IDMAO IDMA
115. 7 AH10 VO Z IPU Emulation pin 17 EMU18 AE13 VO Z IPU Emulation pin 18 RESETS INTERRUPTS AND GENERAL PURPOSE INPUT OUTPUTS RESET AG14 Device reset 1 l Input Output Z High impedance S Supply voltage GND Ground A Analog signal 2 IPD Internal pulldown IPU Internal pullup For most systems a 1 kQ resistor can be used to oppose the IPU IPD For more detailed information on pullup pulldown resistors and situations where external pullup pulldown resistors are required see Section 3 7 Pullup Pulldown Resistors Device Overview These pins are multiplexed pins For more details see Section 3 Device Configuration 4 C6454 DSP does not require external pulldown resistors on the EMUO and EMU1 pins for normal or boundary scan operation Submit Documentation Feedback 4 TEXAS 5320 6454 INSTRUMENTS Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 2 3 Terminal Functions continued SIGNAL TYPE IPD IPU DESCRIPTION NAME NO Nonmaskable interrupt edge driven rising edge NMI AH4 IPD Any noise on the NMI pin may trigger an NMI interrupt therefore if the NMI pin is not used it is recommended that the NMI pin be grounded versus relying on the IPD RESETSTAT AE14 Reset Status The RESETSTAT pin indicates when the devic
116. 8M 000 0000 BO7F FFFF Reserved 256M 8M B080 0000 BFFF FFFF EMIFA CE4 SBSRAM Async 8M C000 0000 7 FFFF Reserved 256M 8M C080 0000 CFFF FFFF EMIFA CES SBSRAM Async 8M 0000 0000 DO7F FFFF Reserved 256M 8M D080 0000 DFFF FFFF DDR2 Memory Controller CEO DDR2 SDRAM 256M E000 0000 EFFF FFFF Reserved 256M F000 0000 FFFF FFFF 1 The EMIFA and are not functionally supported on the C6454 device and therefore are not pinned out Submit Documentation Feedback Device Overview 11 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 www ti com 2 4 Boot Sequence 2 4 1 12 The boot sequence is a process by which the DSP s internal memory is loaded with program and data sections and the DSP s internal registers are programmed with predetermined values The boot sequence is started automatically after each power on reset warm reset and system reset For more details on the initiators of these resets see Section 7 6 Reset Controller There are several methods by which the memory and register initialization can take place Each of these methods is referred to as a boot mode The boot mode to be used is selected at reset through the 3 0 pins Each boot mode can be classified as a hardware boot mode or as a software boot mode Software boot modes require the use o
117. 9 AED20 AJ28 AED19 AF29 AED18 AH28 AED17 AE29 AED16 AG28 AED15 AF28 AED14 AH26 AED13 AE28 AED12 AE26 AED11 AD26 VO Z IPU EMIFA external data AED10 AF27 AED9 27 AED8 AD27 AED7 AE25 AED6 AJ27 AED5 AJ26 AED4 AE27 AED3 AG25 AED2 AH27 AED1 AF25 AEDO AD25 DDR2 MEMORY CONTROLLER 32 BIT CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY DDR2 Memory Controller memory space enable When the DDR2 Memory PRODUCT PREVIEW DCE0 Fla 0 2 Controller is enabled it always keeps this low DBA2 E15 O Z DBA1 D15 O Z DDR2 Memory Controller bank address control DBAO C15 O Z DDR2CLKOUT B14 O Z DDR2 Memory Controller output clock CLKIN2 frequency x 10 DDR2CLKOUT 14 O Z Negative DDR2 Memory Controller output clock CLKIN2 frequency x 10 DSDCAS D13 O Z DDR2 Memory Controller SDRAM column address strobe DSDRAS C13 O Z DDR2 Memory Controller SDRAM row address strobe DSDWE B13 O Z DDR2 Memory Controller SDRAM write enable DSDCKE D14 O Z DDR2 Memory Controller SDRAM clock enable used for self refresh mode DEODT1 A17 O Z On die termination signals to external DDR2 SDRAM These pins should not be connected to the DDR2 SDRAM DEODTO E16 O Z Note There are no on die termination resistors implemented on the C6454 DSP die DSDDQGATE3 F21 l DDR2 Memory Controller data strobe gate 3 0 DSDDQGATE2 E21 O Z For hookup of these signals please refer to the Implementing
118. A 0 AECLKIN default mode SYSCLK4 CPU x Clock Rate The SYSCLK4 clock rate is software selectable via the PLL1 Controller By default SYSCLK4 is selected as CPU 8 clock rate 66 Device Configuration Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 Table 3 13 Device Status Register DEVSTAT Field Descriptions continued Bit Field Value Description 3 0 BOOTMODE 3 0 Boot mode configuration bits Shows the status of what device boot mode configuration is operational BOOTMODE 3 0 Note if selected for boot the corresponding peripheral is automatically enabled after device reset 0000 No boot default mode 0001 Host boot HPI 0010 Reserved 0011 Reserved 0100 EMIFA 8 bit ROM boot 0101 Master 2 boot 0110 Slave 2 boot 0111 Host boot PCI 1000 Reserved thru 1111 For more detailed information on the boot modes see Section 2 4 Boot Sequence 3 6 JTAG ID JTAGID Register Description The JTAG ID register is a read only register that identifies to the customer the JTAG Device ID For the C6454 device the JTAG ID register resides at address location 0 02 8 0008 For the actual register bit names and their associated bit field descriptions see Figure 3 11 and Table 3 14 31 28 27 12 11 1 O VARIANT PART
119. A Channel 29 Mapping Register 02A0 0178 DCHMAP30 DMA Channel 30 Mapping Register 02A0 017C DCHMAP31 DMA Channel 31 Mapping Register 100 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com Table 7 4 Channel Controller Registers continued 5320 6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 0180 DCHMAP32 DMA Channel 32 Mapping Register 02A0 0184 DCHMAP33 DMA Channel 33 Mapping Register 02A0 0188 DCHMAP34 DMA Channel 34 Mapping Register 02A0 018C DCHMAP35 DMA Channel 35 Mapping Register 02A0 0190 DCHMAP36 DMA Channel 36 Mapping Register 02A0 0194 DCHMAP37 DMA Channel 37 Mapping Register 02A0 0198 DCHMAP38 DMA Channel 38 Mapping Register 02A0 019C DCHMAP39 DMA Channel 39 Mapping Register 02A0 01A0 DCHMAP40 DMA Channel 40 Mapping Register 02A0 01A4 DCHMAP41 DMA Channel 41 Mapping Register 02A0 01A8 DCHMAP42 DMA Channel 42 Mapping Register 02A0 01AC DCHMAP43 DMA Channel 43 Mapping Register 02A0 01 0 DCHMAP44 DMA Channel 44 Mapping Register 02A0 01B4 DCHMAP45 DMA Channel 45 Mapping Register 02A0 01B8 DCHMAP46 DMA Channel 46 Mapping Register 02A0 01BC DCHMAP47 DMA Channel 47 Mapping Register 02A0 01 0 DCHMAP48 DMA Channel 48 Ma
120. ABA 1 0 ARW ASADS ASRE 5 and AAWE ASWE Figure 7 39 HOLD HOLDA Timing for EMIFA 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 249 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 7 10 5 BUSREQ Timing Table 7 50 Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles for EMIFA Module see Figure 7 40 720 850 NO PARAMETER 1000 UNIT MIN MAX 1 la AEKOH ABUSRV Delay time AECLKOUT high to ABUSREQ valid 1 5 5 ns AECLKOUTx LX _ s t 1 44 1 ABUSREQ Y Figure 7 40 BUSREQ Timing for EMIFA Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 159 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 11 12C Peripheral The inter integrated circuit I2C module provides an interface between a C64x DSP and other devices compliant with Philips Semiconductors Inter IC bus bus specification version 2 1 and connected by way of I C bus External components attached to this 2 wire serial bus can transmit receive up to 8 bit data to from the DSP through the 2 module 7 11 1 2 Device Specific Information The C6454 device includes an 2 peripheral
121. AH AG FSX1 DX1 AG CLKRO GP 7 GP 6 on TOUTLI EMUG EMU2 RSV38 RSV39 DVppas Vss RESET RSV46 HD11 CLKRI CLKX1 555 DV V EMUO TOUTLO EMU4 EMU3 EMUS EMU14 POR RSV45 AF ppss S AD11 GP 0 GP 3 AE HD22 HDO HD10 Vss FSR1 DVpp33 Vss DVppas EMU15 EMU12 EMUS EMU18 RESETSTAT DV AE AD22 ADO AD10 GP 10 Digs HD21 HD25 HD5 HD3 AD DV V DV EMU13 EMU11 V DV V AD ee 2 mE DD33 ss DD33 RSV37 EMU10 RSV36 55 m ES HD19 HD13 HD23 HD29 HD27 AC V DV V RSV64 AG AD19 AD13 AD23 AD29 AD27 SS 58 DD33 ss DVppss Vss DD33 ss AB HD17 HD15 HD9 HD7 HD1 Vs 17 AD15 AD9 AD7 AD1 HD31 HD28 HD30 AA V 0092 99 AD31 AD28 AD30 poss 59 HD26 HD18 HD16 HD6 HD4 Y Vss DVppss AD26 AD18 AD16 AD6 AD4 HD24 HD20 HD14 HD8 HD2 w RSV03 V V V cy V w AD24 AD20 AD14 AD8 AD2 8 98 BD ss 9D 5 HHWIL HD12 V DV V RSV02 V DV CV V RSV68 V DD33 55 PCLK AD12 SS DD33 DD SS DD 55 HDS2 HDS1 HINT HCNTL1 HCNTLO HCS U U PCBE1 PSERR PFRAME PDEVSEL PSTOP PPERR Vss Vss CVop Vss Vss HAS HRDY HRANI T RSV15 RSV16 V DV CV V BIHDY PCBEZ 55 DD33 DD ss DD 55 DD PGNT PRST R DV Vi PIDSEL DV 7 V V cy 0033 55 GP 12 GP 13 DD33 ss ss DD ss DD ss kau 4 5 6 7 8 9 10 11 12 13 14 5 Figure 2 2 C6454 Pin Map Bottom View Quadrant 14 Dev
122. CT PREVIEW 32 SYSCLK2 S EDMA3 CC 32 SYSCLK2 EpMA3 TCO 32 32 SYSCLK2 SYSCLK2 _ s EDMA3 TC1 32 YSCLK2 S EDMA3 TC2 32 SYSCLK2 4 S EDMA3TC3 Configuration Bus Data Bus A Only accessible by the C64x Megamodule B All clocks in this figure are generated by the PLL1 controller Figure 4 2 C64x Megamodule SCR Connection Submit Documentation Feedback System Interconnect 75 Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 www ti com 4 4 Priority Allocation On the C6454 device each of the masters excluding the C64x Megamodule are assigned a priority via the Priority Allocation Register PRI ALLOC see Figure 4 3 The priority is enforced when several masters in the system are vying for the same endpoint A value of 000b has the highest priority while 111b has the lowest priority Note that the configuration SCR port on the data SCR is considered a single endpoint meaning priority will be enforced when multiple masters try to access the configuration SCR Priority is also enforced on the configuration SCR side when a master through the data SCR tries to access the same endpoint as the C64x Megamodule Other Master peripherals are not present in the PRI ALLOC register as they have their own registers to program their priorities For more informatio
123. CT PREVIEW Mal aad TMS320C6454 9 Texa 5 Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 www ti com 7 14 1 EMAC Device Specific Information 188 Interface Modes The EMAC module on the TMS320C6454 supports four interface modes Media Independent Interface MII Reduced Media Independent Interface RMII Gigabit Media Independent Interface GMII and Reduced Gigabit Media Independent Interface RGMII The MII and GMII interface modes are defined in the IEEE 802 3 2002 standard The RGMII mode of the EMAC conforms to the Reduced Gigabit Media Independent Interface RGMII Specification version 2 0 The RGMII mode implements the same functionality as the GMII mode but with a reduced number of pins Data and control information is transmitted and received using both edges of the transmit and receive clocks TXC and RXC Note The internally delays the transmit clock TXC with respect to the transmit data and control pins Therefore the EMAC conforms to the RGMII ID operation of the RGMII specification However the EMAC does not delay the receive clock this signal must be delayed with respect to the receive data and control pins outside of the DSP The RMII mode of the EMAC conforms to the RMII Specification revision 1 2 as written by the RMII Consortium As the name implies the Reduced Media Independent Interface RMII mode is a reduced pin c
124. D and Device ID Program Register 02 0 0398 PCICMDSTATPRG PCI Command and Status Program Register 02 0 039C PCICLREVPRG PCI Class Code and Revision ID Program Register 02 0 03A0 PCISUBIDPRG PCI Subsystem Vendor ID and Subsystem ID Program Register 02 0 03A4 PCIMAXLGPRG PCI Max Latency and Min Grant Program Register 02C0 03A8 PCILRSTREG PCI LRESET Register 02C0 03AC PCICFGDONE _ PCI Configuration Done Register 02C0 03B0 PCIBAROMPRG PCI Base Address Mask Register 0 Program Register 02 0 03B4 PCIBAR1MPRG PCI Base Address Mask Register 1 Program Register 02 0 03B8 PCIBAR2MPRG PCI Base Address Mask Register 2 Program Register 02 0 03BC PCIBARSMPRG _ PCI Base Address Mask Register Program Register 02C0 03CO PCIBARAMPRG PCI Base Address Mask Register 4 Program Register 02 0 03C4 PCIBARSMPRG PCI Base Address Mask Register 5 Program Register 02 0 03C8 PCIBAROPRG PCI Base Address Register 0 Program Register 02C0 03CC PCIBAR1PRG PCI Base Address Register 1 Program Register 02C0 03DO PCIBAR2PRG PCI Base Address Register 2 Program Register 02 0 0304 PCIBAR3PRG PCI Base Address Register 3 Program Register 02C0 03D8 PCIBAR4PRG PCI Base Address Register 4 Program Register 02C0 03DC PCIBAR5PRG PCI Base Address Register 5 Program Register 02 0 03E0 PCIBAROTRLPRG PCI Base Address Translation Register 0 Program Register 02 0 03E4 PCIBAR1TRLPRG PCI Base Address Translation Register 1 Program Register 02 0 03E8 PCIBAR2TRLPRG PCI Base Ad
125. DDR2 PCB DSDDQGATE1 9 Layout TMS320C6454 Hardware Design Application Report literature number SPRAAAQ DSDDQGATEO A9 O Z DSDDQM3 C23 O Z DDR2 Memory Controller byte enable controls DSDDQM2 C20 O Z e Decoded from the low order address bits The number of address bits or byte enables used depends on the width of external memory DSDDQM1 C8 O Z e Byte write enables for most types of memory DSDDQMO C11 O Z be directly connected to SDRAM read and write mask signal SDQM Submit Documentation Feedback Device Overview 31 Mal aad TMS32006454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com Table 2 3 Terminal Functions continued SIGNAL TYPE IPD IPU DESCRIPTION NAME NO DSDDQS3 E23 VO Z DSDDQS2 E20 VO Z DDR2 Memory Controller data strobe 3 0 positive DSDDQS1 E8 VO Z DSDDQSO E11 VO Z DSDDQS3 D23 VO Z DSDDQS2 D20 VO Z DDR2 data strobe 3 0 negative DSDDQS1 D8 VO Z Note These pins are used to meet AC timings DSDDQSO D11 VO Z DDR2 MEMORY CONTROLLER 32 ADDRESS DEA13 B15 DEA12 A15 DEA11 A16 DEA10 B16 DEA9 C16 DEA8 D16 DEA7 B17 O Z DDR2 Memory Controller external address DEA6 C17 DEA5 D17 DEA4 E17 DEA3 A18 DEA2 B18 DEA1 C18 DEAO D18 32 Device Overview Submit Documentat
126. DF FFFF L1P SRAM 32K 00 0 0000 00 0 7FFF Reserved 1M 32K 00 0 8000 OOEF FFFF L1D SRAM 32K 00 0 0000 OOFO 7FFF Reserved 1M 32K OOFO 8000 OOFF FFFF Reserved 8M 0100 0000 017F FFFF C64x Megamodule Registers 4M 0180 0000 01BF FFFF Reserved 12 5M 01 0 0000 0287 FFFF HPI Control Registers 256K 0288 0000 028 FFFF McBSP 0 Registers 256K 028C 0000 028F FFFF McBSP 1 Registers 256K 0290 0000 0293 FFFF Timer 0 Registers 256K 0294 0000 0297 FFFF Timer 1 Registers 128K 0298 0000 0299 FFFF PLL1 Controller including Reset Controller Registers 512 029A 0000 029A 01FF Reserved 256K 512 029A 0200 029B FFFF PLL2 Controller Registers 512 029C 0000 029C 01FF Reserved 64K 029C 0200 029C FFFF EDMAS Channel Controller Registers 32K 02A0 0000 02A0 7FFF Reserved 96K 02A0 8000 02A1 FFFF Transfer Controller 0 Registers 32K 02 2 0000 02 2 7FFF EDMAS Transfer Controller 1 Registers 32K 02A2 8000 02A2 FFFF EDMAS Transfer Controller 2 Registers 32K 02 0000 02A3 7FFF EDMAS Transfer Controller 3 Registers 32K 02 8000 02A3 FFFF Reserved 256K 02 4 0000 02A7 FFFF Chip Level Registers 256K 02A8 0000 02AB FFFF Device State Control Registers 256 02AC 0000 2 FFFF GPIO Registers 16K 02 0 0000 02B0 3FFF 12 Data and Control Registers 256K 02 0 4000 02B3 FFFF Reserved 720K 02B4 0000 02BF FFFF PCI Control Registers 256K 02 0 0000 02C3 FFFF Reserved 256K 02C4 0000 02 7 FFFF EMAC Con
127. DTO DEA4 AVpLL2 Vss DSDDQS2 Gates DVppig DSDDQS3 DVppis Vss AED59 DVppaa Vss D DEA8 DEA5 DEAO DED19 DSDDQS2 DED23 DED27 DSDDQS3 RSV11 RSV32 RSVo9 AED57 AED58 AED39 D DEA9 DEA6 DEA1 DEDi8 DSDDQM2 DED22 DED26 DSDDQM3 RSV12 RSV33 RSV23 AED61 AED60 AED41 DEA10 DEA7 DEA2 DED16 DED21 DED25 DVppis DED29 DED31 RSV22 AED49 AEDS51 Vss B DEAN DEODT1 DEA3 DED17 Vss DED20 DED24 Vss DED28 DED30 DVppismon AED62 AED53 DVppas 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Figure 2 4 C6454 Pin Map Bottom View Quadrant 16 Device Overview Submit Documentation Feedback 4 TEXAS 5320 6454 INSTRUMENTS Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 nw 6 7 8 9 10 11 12 13 14 15 Eon GEI ai PTRDY DVpp33 Vss RSV05 Vss CVpp Vss CVpp N Vss MDIO MTXD7 RSV29 RSV28 RSV04 CVpp Vss CVpp Vss M Liane MRXD7 MTXD6 MTXD2 MDCLK Vss DVpp33 CVpp Vss CVpp Vss CVop L MRXD4 MRXD5 MTXD4 MTXD5 DVppsamon Vss Vss CVpp Vss CVpp Vss K DvVppss Vss MCOL MTXD3 GMTCLK Vss DVpp33 a moe MDA umoa MERS MEN va H MRCLK MRXD6 asa MRXDV Vss DVppis Vss DVppss CLKIN2 RSV07 Vss DVpp15 Vss DVpp18 Vss DVpp18 Vss DVpp18 Vss DVppis Vss F Rsvi4 RSV13 DVppi15MON Vss DVppis Vss DVppi8 V
128. EKOH ADSV Delay time AECLKOUT high to ASADS ASRE valid 1 3 4 9 ns 9 la EKOH OEV Delay time AECLKOUT high to ASOE valid 1 3 4 9 ns 10 la EKOH EDV Delay time AECLKOUT high to AEDx valid 4 9 ns 11 ta EKOH EDIV Delay time AECLKOUT high to AEDx invalid 1 3 ns 12 gEkOH wEV Delay time AECLKOUT high to ASWE valid 1 3 4 9 ns 1 The following parameters are programmable via the EMIFA CE Configuration registers CEnCFG Submit Documentation Feedback Read latency R_LTNCY 0 1 2 or 3 cycle read latency Write latency LTNCY 0 1 2 or 3 cycle write latency ACEx assertion length CE EXT For standard SBSRAM or ZBT SRAM interface ACEx goes inactive after the final command has been issued EXT 0 For synchronous FIFO interface with glue ACEx is active when ASOE is active CE EXT 1 Function of ASADS ASRE ENABLE For standard SBSRAM or ZBT SRAM interface ASADS ASRE acts as ASADS with deselect cycles ENABLE 0 For FIFO interface ASADS ASRE acts ASRE with NO deselect cycles ENABLE 1 C64x Peripheral Information and Electrical Specifications 155 PRODUCT PREVIEW Mal aad TMS320C6454 49 Texas Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 READ latency 2 AEcLKouT _ _ f A VS L S Ls VJ e 1 ACEx L LL c Jp Lt ABE ZO X BE1 X BE X BES X BE X
129. EMIFA When interfacing to 16 bit Asynchronous devices 1 carries bit 1 of the byte address For an 8 bit Asynchronous interface ABA 1 0 are used to carry bits 1 and 0 of the byte address DDR2 Memory Controller enable DDR2 EN ABAO 0 DDR2 Memory Controller peripheral pins are disabled default 1 DDR2 Memory Controller peripheral pins are enabled EMIFA enable EMIFA EN ABA1 0 EMIFA peripheral pins are disabled default 1 EMIFA peripheral pins are enabled 26 Device Overview Submit Documentation Feedback INSTRUMENTS Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 2 3 Terminal Functions continued SIGNAL TYPE IPD IPU DESCRIPTION NAME NO ACES 27 0 2 EMIFA memory space enables ACE4 V28 O Z IPU Enabled by bits 28 through 31 of the word address ACES W26 O Z IPU Only one pin is asserted during any external data access ACE W27 O Z IPU Note The C6454 device does not have ACEO and pins ABE7 W29 O Z IPU ABE6 K26 O Z IPU ABES L29 0 2 pH EMIFA byte enable control ABE4 L28 0 2 IPU Decoded from the low order address bits The number of address bits or ABE3 AA29 O Z IPU byte enables used depends on the width of external memory ABE AA28 0 2 IPU Byte write enables for most types of memory ABET AA25 O Z IPU ABEO AA26 O Z IPU EMIFA 64 BIT BUS ARBITRATION AHOLDA
130. F 0184 83B0 MAR236 Controls DDR2 GEO Range EC00 0000 ECFF FFFF 0184 83B4 MAR237 Controls DDR2 Range ED00 0000 EDFF FFFF 0184 83B8 MAR238 Controls DDR2 CEO Range 00 0000 EEFF FFFF 0184 83BC MAR239 Controls DDR2 Range EF00 0000 EFFF FFFF 0184 83CO 0184 83FC Reserved Table 5 9 Megamodule L1 L2 Memory Protection Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 A000 L2MPFAR L2 memory protection fault address register 0184 A004 L2MPFSR L2 memory protection fault status register 0184 A008 L2MPFCR L2 memory protection fault command register 0184 00 0184 AOFF Reserved 0184 A100 L2MPLKO L2 memory protection lock key bits 31 0 0184 A104 L2MPLK1 L2 memory protection lock key bits 63 32 0184 A108 L2MPLK2 L2 memory protection lock key bits 95 64 0184 A10C L2MPLK3 L2 memory protection lock key bits 127 96 0184 A110 L2MPLKCMD L2 memory protection lock key command register 0184 A114 L2MPLKSTAT 12 memory protection lock key status register 0184 A118 0184 A1FF Reserved 0184 A200 L2MPPAO L2 memory protection page attribute register 0 0184 A204 L2MPPA1 L2 memory protection page attribute register 1 0184 A208 L2MPPA2 L2 memory protection page attribute register 2 Submit Documentation Feedback C64x4 Megamodule 87 PRODUCT PREVIEW Mal aad L9naoad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS S
131. FFFF 0184 8318 MAR198 Controls EMIFA CE4 Range C600 0000 C6FF FFFF 0184 831C MAR199 Controls EMIFA CE4 Range C700 0000 C7FF FFFF 0184 8320 MAR200 Controls EMIFA CE4 Range C800 0000 C8FF FFFF 0184 8324 MAR201 Controls EMIFA CE4 Range C900 0000 C9FF FFFF 0184 8328 MAR202 Controls EMIFA CE4 Range 00 0000 CAFF FFFF 0184 832C MAR203 Controls EMIFA 4 Range 00 0000 CBFF FFFF 0184 8330 MAR204 Controls EMIFA CE4 Range 0000 CCFF FFFF 0184 8334 MAR205 Controls EMIFA CE4 Range CD00 0000 CDFF FFFF 0184 8338 MAR206 Controls EMIFA CE4 Range 00 0000 CEFF FFFF 0184 833C MAR207 Controls EMIFA CE4 Range 0000 CFFF FFFF 0184 8340 MAR208 Controls EMIFA CE5 Range 0000 0000 DOFF FFFF 0184 8344 MAR209 Controls EMIFA CE5 Range D100 0000 D1FF FFFF 0184 8348 MAR210 Controls EMIFA CE5 Range D200 0000 D2FF FFFF 0184 834 MAR211 Controls EMIFA 5 Range D300 0000 D3FF FFFF 86 C64x Megamodule Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com 5320 6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 5 8 Megamodule Cache Configuration Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 8350 MAR212 Controls EMIFA CES Range 0400 0000 D4FF FFFF 0184 8354 MAR213 Controls EMIFA CES Range 0500 0000 D5FF FFFF 0184 83
132. FSX is inverted to provide active low slave enable output As a Slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for Master McBSP CLKXM CLKRM FSXM FSRM 0 for Slave McBSP FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock CLKX CLKX 4 i k 1 k 2 FSX 2 6 k 75h DX Bio Bitn 1 X 2 X n3 X n4 X 4 _ gt 5 DR BitO C Bin n2 X m3 X n4 Xj Figure 7 57 McBSP Timing as SPI Master or Slave CLKSTP 11b CLKXP 1 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback K Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 7 14 Ethernet MAC EMAC The Ethernet Media Access Controller EMAC module provides an efficient interface between the C6454 DSP core processor and the networked community The EMAC supports 10Base T 10 Mbits second Mbps and 100BaseTX 100 Mbps in either half or full duplex mode and 1000BaseT 1000 Mbps in full duplex mode with hardware flow control and quality of service QOS support The EMAC module conforms to the IEEE 802 3 2002 standard describing the Carrier Sense Multiple Access with Collision Detection CSMA CD Access Method and Phys
133. GPIO Pins 256K Bit 32K Byte L2 ROM System PLL and PLL Controller Time Stamp Counter e Secondary PLL and PLL Controller Dedicated Endianess Little Endian Big Endian to EMAC and DDR2 Memory Controller e 64 Bit External Memory Interface EMIFA IEEE 1149 1 JTAG Glueless Interface to Asynchronous Ho ndary scan campatible Memories SRAM Flash and EEPROM and 697 Pin Ball Grid Array BGA Package Synchronous Memories SBSRAM and ZBT ZTZ or GTZ Suffix 0 8 mm Ball Pitch SRAM 0 09 7 Cu Metal Process CMOS Supports Interface to Standard Sync 1 8 1 5 V I 1 25 1 2 V I Devices and Custom Logic FPGA CPLD m 29110 merna ASICs etc e Pin Compatible with the TMS320C6455 _ 32M Byte Total Addressable External Fixed Point Digital Signal Processor Memory Space 5 Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document All trademarks are the property of their respective owners PRODUCT PREVIEW information concerns products in the Copyright 2006 2006 Texas Instruments Incorporated formative or design phase of development Characteristic data and other specifications are design goals Texas Instruments reserves the right to change or discontinue these products without notice PRODUCT PREVIEW Mal aad
134. I EN PCI Enable PCI EN status bit Shows the status of which function is enabled on the HPI PCI multiplexed pins 0 pin functions are enabled default 1 PCI pin functions are enabled 19 17 CFGGP 2 0 Used as General Purpose inputs for configuration purposes These pins are latched at reset These values can be used by S W routines for boot operations 16 Reserved Reserved Read only writes have no effect 15 SYSCLKOUT EN SYSCLKOUT Enable SYSCLKOUT status bit Shows the status of which function is enabled on the SYSCLK4 GP 1 muxed pin 0 GP 1 pin function of the SYSCLK4 GP 1 pin enabled default 1 SYSCLKA pin function of the SYSCLKA GP 1 pin enabled Submit Documentation Feedback Device Configuration 65 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 3 13 Device Status Register DEVSTAT Field Descriptions continued Bit Field Value Description 14 MCBSP1 EN McBSP1 Enable MCBSP1 EN status bit Shows the status of which function is enabled on the McBSP1 GPIO muxed pins 0 GPIO pin functions enabled default McBSP1 pin functions enabled 13 66 PCI Frequency Selection PCI66 status bit Shows the PCI operating frequency selected at reset 0 PCI operates at 33 MHz default PCI operates at 66 MHz 12 Reserved Reserved Read only writes have no effect 11 PCI EEAI
135. IFA Configuration Register 7000 0088 CE4CFG EMIFA CE4 Configuration Register 7000 008C CE5CFG EMIFA CE5 Configuration Register 7000 0090 7000 009C Reserved 7000 00 0 AWCC EMIFA Async Wait Cycle Configuration Register 7000 00A4 7000 00BC Reserved 7000 00CO INTRAW EMIFA Interrupt RAW Register 7000 00 4 INTMSK EMIFA Interrupt Masked Register 7000 00C8 INTMSKSET EMIFA Interrupt Mask Set Register 7000 00CC INTMSKCLR EMIFA Interrupt Mask Clear Register 7000 0000 7000 00DC Reserved 7000 00 0 77FF FFFF Reserved 150 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com 7 10 3 EMIFA Electrical Data Timing TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 42 Timing Requirements for AECLKIN for EMIFA see Figure 7 31 720 850 NO 1000 UNIT MIN MAX 1 le EKI Cycle time AECLKIN 3 40 ns 2 tw EKIH Pulse duration AECLKIN high 2 7 ns 3 luEKIL Pulse duration AECLKIN low 2 7 ns 4 trex Transition time AECLKIN 2 ns 5 Period Jitter 0 02E 4 ns 1 The reference points for the rise and fall transitions are measured at Vy MAX and Vj MIN 2 E the EMIF input clock AECLKIN or SYSCLK4 period in ns for EMIFA 3 Minimum cycle times must be met even when AECLKIN is generated by an internal clock so
136. II mode RGMDCLK O RGMDIO 4 VO Z serial data for RGMII mode RGMDIO I O ETHERNET MAC EMAC MII RMII GMII There are two configuration pins the MAC_SEL 1 0 AEA 10 9 pins that select one of the four interface modes MII or RGMII for the EMAC MDIO interface For more detailed information on the EMAC configuration pins see Section 3 Device Configuration This pin is EMAC receive clock MRCLK for MII default or GMII MACSEL 1 0 dependent This pin is EMAC carrier sense MCRS 1 for MII default or GMII or EMAC MCRS RMCRSDV J4 VO Z carrier sense receive data valid RMCRSDV I for MACSEL 1 0 dependent This pin is EMAC receive error MRXIR I for MII default or GMII MACSEL 1 0 dependent This pin is EMAC MII default or GMII receive data valid MRXDV I NERDY MACSEL 1 0 dependent MRXD7 M2 MRXD6 H2 i fault RMII or GMII MRXD4 E EMAC receive data bus for MII default or MRXD3 J3 These pins function as EMAC receive data pins for MII default RMII or GMII MRXD x 0 1 MACSEL 1 0 dependent MRXD2 J1 MRXD1 RMRXD1 H3 MRXDO RMRXDO J2 GMTCLK K5 O Z This pin is EMAC transmit clock GMTCLK O MACSEL 1 0 dependent This pin is either EMAC MII default or GMII transmit clock MTCLK 1 or the EMAC RMII reference clock RMREFCLK I Th
137. INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 TINPL1 Timer 1 senti TOUTLO TOUTL1 4 TINPLO Timers 64 Bit PREQ GP 15 O 4 gt lt gt 7 PINTA GP 14 O 4 lt GP 6 PRST GP 13 O 4 lt GP 5 PGNT GP 12 4 gt lt GP 4 FSX1 GP 11 B 4 gt lt gt CLKX1 GP 3 B 1 10 4 gt lt gt PCBEO GP 2 O DX1 GP 9 B 4 lt gt SYSCLK4 GP 1 4 DR1 GP 8 B 4 gt lt gt General Purpose Input Output 0 GPIO Port A This pin functions as GP 1 by default For more details see the Device Configuration section of this document B These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins For more details see the Device Configuration section of this document C These PCI peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins For more details see the Device Configuration section of this document Figure 2 7 Timers GPIO Peripheral Signals Submit Documentation Feedback Device Overview 19 PRODUCT PREVIEW Mal aad TMS32006454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 AED 63 0 2 AEA 19 0 ABA
138. INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 1 TMS320C6454 Fixed Point Digital Signal Processor 1 1 Features High Performance Fixed Point DSP C6454 32 Bit DDR2 Memory Controller DDR2 533 1 39 1 17 and 1 ns Instruction Cycle Time SDRAM 720 MHz 850 MHz and 1 GHz Clock Rate EDMAG Controller 64 Independent Channels Eight 32 Bit Instructions Cycle e 32 16 Bit Host Port Interface HPI 8000 MIPS MMACS 16 Bits 32 Bit 33 66 MHz 3 3 V Peripheral Component Commercial Temperature 0 C to 90 C Interconnect PCI Master Slave Interface TMS320C64x DSP Core Conforms to PCI Specification 2 3 Dedicated SPLOOP Instruction Inter Integrated Circuit I7C Bus Compact Instructions 16 Bit e Two McBSPs Instruction Set Enhancements 10 100 1000 Mb s Ethernet MAC EMAC Exception Handling IEEE 802 3 Compliant TMS320C64x Megamodule L1 L2 Memory Supports Multiple Media Independent Architecture Interfaces MII GMII RMII and RGMII 256K Bit 32K Byte L1P Program Cache 8 Independent Transmit TX and Direct Mapped 8 Independent Receive RX Channels 256K Bit 32K Byte L1D Data Cache Two 64 Bit General Purpose Timers 2 Way Set Associative 8M Bit 1048K Byte L2 Unified d Configurable as Four 32 Bit Timers Byte nified Mappe RAM Cache Flexible Allocation 16 General Purpose I O
139. ION SCR PCI MEGAMODULE TCO N N N Y Y Y Y Y Y Y Y Y TC2 N N Y Y Y Y TC3 N N Y Y Y Y EMAC N N N Y Y Y HPI N Y N Y Y Y PCI N Y N Y Y Y 4 3 Configuration Switch Fabric Figure 4 2 shows the connection between the C64x Megamodule and the configuration switched central resource SCR The configuration SCR is mainly used by the C64x Megamodule to access peripheral registers The data SCR also has a connection to the configuration SCR which allows masters to access most peripheral registers The only registers not accessible by the data SCR through the configuration SCR are the device configuration registers and the PLL1 and PLL2 controller registers these can only be accessed by the C64x Megamodule The configuration SCR uses 32 bit configuration buses running at SYSCLK2 frequency SYSCLK2 is supplied by the PLL1 controller and is fixed at a frequency equal to the CPU frequency divided by 3 74 System Interconnect Submit Documentation Feedback INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 CFG SCR McBSPs PCI 32 bit 32 SYSCLK2 SYSCLK3 12C SYSCLK3 Timers SYSCLK3 32 SYSCLK2 HPI 32 SYSCLK2 Megamodule 32 SYSCLK2 Data SCR uus SYSCLK3 EMAC MDIO SYSCLK3 PLL Controllers A SYSCLK3 Device Configuration Registers A PRODU
140. IPU 2 DESCRIPTION DVppas AD5 AD7 AD14 AD18 AD22 AD24 AE6 AE8 AE15 AF 1 AF16 AF24 AG12 AG17 AG23 AH14 AH16 AH24 AJ1 AJ7 AJ15 AJ25 AJ29 3 3 V I O supply voltage CVpp L12 L14 L16 L18 M11 M13 M15 M17 M19 N12 N14 N16 N18 P13 P15 P17 P19 R12 R14 R16 1 2 V core supply voltage Submit Documentation Feedback Device Overview 41 PRODUCT PREVIEW Mal aad TMS32006454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com Table 2 3 Terminal Functions continued SIGNAL NAME NO TYPE IPD IPU 2 DESCRIPTION CVpp R18 T11 T13 T15 T17 T19 U12 U14 U18 V11 V13 V19 W12 W14 1 2 V core supply voltage GROUND PINS Vss A8 A11 A20 A23 B1 B29 C5 D1 E5 E7 E19 E25 E29 F4 F6 F8 F10 F12 F14 F16 GND Ground pins 42 Device Overview Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com
141. Information and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 12 3 Electrical Data Timing Table 7 55 Timing Requirements for Host Port Interface Cycles see Table 7 56 through Figure 7 51 720 850 NO 1000 UNIT MIN MAX 9 tsu HASL HSTBL Setup time HAS low before HSTROBE low 5 ns 10 tnhsrBL HASL Hold time HAS low after HSTROBE low 2 ns 11 lsu SELV HASL Setup time select signals valid before HAS low 5 ns 12 th HASL SELV Hold time select signals 9 valid after HAS low 5 ns 13 Pulse duration HSTROBE low 15 ns 14 iw tHSTBH Pulse duration HSTROBE high between consecutive accesses 2M ns 15 lsu SELV HSTBL Setup time select signals valid before HSTROBE low 5 ns 16 th HSTBL SELV Hold time select signals 9 valid after HSTROBE low 5 ns 17 su HDV HSTBH Setup time host data valid before HSTROBE high 5 ns 18 Hold time host data valid after HSTROBE high 1 ns 37 tsu HCSL HSTBL Setup time HCS low before HSTROBE low 0 ns Hold time HSTROBE low after HRDY low HSTROBE should not be 38 th HRDYL HSTBL inactivated until HRDY is active low otherwise HPI writes will not 1 1 ns complete properly 1 HSTROBE refers to the following logical operation on HCS HDS1 HDS2 N
142. KGDV S CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even H CLKGDV 1 2 S if CLKGDV is odd L CLKX low pulse width CLKGDV 2 S if CLKGDV is even L CLKGDV 1 2 S if CLKGDV is odd 4 FSRP FSXP 1 As a SPI Master FSX is inverted to provide active low slave enable output As a Slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for Master McBSP CLKXM CLKRM FSXM FSRM 0 for Slave McBSP 5 FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock CLKX eak PP Xo _ FSX 66 91 8 3 DX C Bio einn X 2 X n3 X n4 X 4 5 Figure 7 56 McBSP Timing as SPI Master or Slave CLKSTP 10b CLKXP 1 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 185 PRODUCT PREVIEW Mal aad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com Table 7 68 Timing Requirements for McBSP as SPI Master or Slave CLKSTP 11b CLKXP 147 see Figure 7 57 720 850 NO 1000 UNIT MASTER SLAVE MIN MAX MIN MAX tsu DRV CKXH Setup time DR valid before CLKX high 12 2 18 ns th CKXH DRV Hold time DR valid after CLKX high 4 5 36P ns 1
143. L Z CC AN KT k 8 6 14 13 k 10 3 1 8 5 gt k em EM oai Stop Start Repeated Stop Start Figure 7 42 2 Receive Timings Table 7 53 Switching Characteristics for 2 Timings see Figure 7 43 720 850 NO PARAMETER 21090 UNIT STANDARD MODE FAST MODE MIN MAX MIN MAX 16 Cycle time SCL 10 2 5 us Delay time SCL high to SDA low for a 17 tascLH spaL repeated START condition 0 6 us Delay time SDA low to SCL low for a START 18 latspat soL and a repeated START condition 4 0 6 us 19 tw SCLL Pulse duration SCL low 4 7 1 3 us 20 tw SCLH Pulse duration SCL high 4 0 6 us 21 la SDAV SDLH Delay time SDA valid to SCL high 250 100 ns Valid time SDA valid after SCL low For 12C 22 twspLL sDAV bus devices 0 0 0 9 us Pulse duration SDA high between STOP and 23 tutspar START conditions id 13 us 24 t spa Rise time SDA 1000 20 0 1040 300 ns 25 Rise time SCL 1000 20 0 1040 300 ns 26 tyspa Fall time SDA 300 20 0 1C 300 ns 27 Fall time SCL 300 20 0 1C 300 ns Delay time SCL high to SDA high for STOP 28 ta scLH SDAH Condition 9 gh 4 0 6 us 29 C Capacitance for each 12C 10 10 pF 1 164 C64x Peripheral Information and Electrical Specifications total capacitance of one bus line in pF If mixed with HS mode devices faster fall times
144. L1 data L1D memory protection fault address register 0184 4 L1DMPFSR L1D memory protection fault status register 0184 ACO8 L1DMPFCR L1D memory protection fault command register 0184 ACOC 0184 ACFF Reserved 0184 ADOO L1DMPLKO L1D memory protection lock key bits 31 0 0184 AD04 L1DMPLK1 L1D memory protection lock key bits 63 32 88 C64x4 Megamodule Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 5 9 Megamodule L1 L2 Memory Protection Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 ADO8 L1DMPLK2 L1D memory protection lock key bits 95 64 0184 ADOC L1DMPLK3 L1D memory protection lock key bits 127 96 0184 AD10 L1DMPLKCMD L1D memory protection lock key command register 0184 AD14 L1DMPLKSTAT L1D memory protection lock key status register 0184 AD18 0185 FFFF Reserved Table 5 10 CPU Megamodule Bandwidth Management Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0182 0200 EMCCPUARBE CPU Arbitration Control Register 0182 0204 EMCIDMAARBE EMC IDMA Arbitration Control Register 0182 0208 EMCSDMAARBE EMC Slave DMA Arbitration Control Register 0182 020C EMCMDMAARBE EMC Master DMA Arbitration Control Resgiter 018
145. ME 02C8 0228 RXFILTERED Filtered Receive Frames Register 02C8 022G RXQOSFILTERED Received QOS Filtered Frames Register 0280230 OS Is Aa carb 2 Dus in good frames 02 8 0234 TXGOODFRAMES aad 22 02C8 0238 TXBCASTFRAMES Broadcast Transmit Frames Register 02C8 023C TXMCASTFRAMES Multicast Transmit Frames Register 02C8 0240 TXPAUSEFRAMES Pause Transmit Frames Register 02C8 0244 TXDEFERRED Deferred Transmit Frames Register 02C8 0248 TXCOLLISION Transmit Collision Frames Register 02C8 024C TXSINGLECOLL Transmit Single Collision Frames Register 02C8 0250 TXMULTICOLL Transmit Multiple Collision Frames Register 02C8 0254 TXEXCESSIVECOLL Transmit Excessive Collision Frames Register 02C8 0258 TXLATECOLL Transmit Late Collision Frames Register 02C8 025C TXUNDERRUN Transmit Underrun Error Register 02C8 0260 TXCARRIERSENSE Transmit Carrier Sense Errors Register 02C8 0264 TXOCTETS Transmit Octet Frames Register 02C8 0268 FRAME64 Transmit and Receive 64 Octet Frames Register 02C8 026C FRAME65T127 Transmit and Receive 65 to 127 Octet Frames Register 02C8 0270 FRAME128T255 Transmit and Receive 128 to 255 Octet Frames Register 02C8 0274 FRAME256T51 1 Transmit and Receive 256 to 511 Octet Frames Register 02C8 0278 FRAMES512T1023 Transmit and Receive 512 to 1023 Octet Frames Register 02C8 027C FRAME1024TUP Transmit and Receive 1024 to 1518 Octet Frames Register 02C8 0280 NETOCTETS Network Octet Frames Register 02C8 0284 RXSOFOVERRUNS Receive FIFO or DMA Start of F
146. MS TMDS Device development evolutionary flow TMX Experimental device that is not necessarily representative of the final device s electrical specifications TMP Final silicon die that conforms to the device s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow TMDX Development support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development support product TMX and TMP devices and TMDX development support tools are shipped with against the following disclaimer Developmental product is intended for internal evaluation purposes TMS devices and TMDS development support tools have been characterized fully and the quality and reliability of the device have been demonstrated fully Tl s standard warranty applies Predictions show that prototype devices TMX or TMP have a greater failure rate than the standard production devices Texas Instruments recommends that these devices not be used in any production system because their expected end use failure rate still is undefined Only qualified production devices are to be used Submit Documentation Feedback Device Overview 47 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 idi TI device nomenclat
147. Master to send data using a standard boot table format Using the Slave I2C boot a single DSP or a device acting as an I2C Master can simultaneously boot multiple slave DSPs connected to the same 2 bus Note that the Master DSP may require booting via an 2 EEPROM before acting as a Master and booting other DSPs The Slave 2 boot is a software boot mode 2 4 2 2nd Level Bootloaders Any of the boot modes can be used to download a 2nd level bootloader A 2nd level bootloader allows for any level of customization to current boot methods as well as definition of a completely customized boot offers a few 2nd level bootloaders such as an EMAC bootloader which can be loaded using the Master I2C boot Submit Documentation Feedback Device Overview 13 PRODUCT PREVIEW Mal aad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 2 5 Pin Assignments 2 5 1 Pin Map Figure 2 2 through Figure 2 5 show the C6454 pin assigments in four quadrants A B C and D 6 INSTRUMENTS www ti com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 AJ DVppss GP 5 FSXO CLKS DRO TINPL1 DVppss Vss TMS RSV26 RSV40 5 Vss DVppss AJ AH GP 4 FSRO NMI sue TINPLO TRST TDO TDI EMU17 RSV27 EMU16 EMU9 DVpp33 Vss
148. NSTRUMENTS www ti com MDIO RGMDIO MDCLK RGMDCLK Figure 2 10 EMAC MDIO MII RMII GMII RGMII Peripheral Signals 22 Device Overview Submit Documentation Feedback INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 HD 15 0 AD 15 0 HD 31 16 AD 31 16 Data Address HHWIL PCLK PIDSEL HCNTL1 PDEVSEL PCBE3 HINT PFRAME HR W PCBE2 Command PINTA GP 14 HDS2 PCBE1 Byte Enable Control HAS PPAR 2 PRST GP 13 HRDY PIRDY HCNTLO PSTOP PTRDY PGNT GP 12 PREQ GP 15 Arbitration HDS1 PSERR HCS PPERR PCI Interface A A These PCI pins are muxed with the HPI or GPIO peripherals By default these signals function as HPI or GPIO or EMAC For more details on these muxed pins see the Device Configuration section of this document Figure 2 11 Peripheral Signals Submit Documentation Feedback Device Overview 23 PRODUCT PREVIEW Mal aad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 2 7 Terminal Functions 6 INSTRUMENTS www ti com The terminal functions table Table 2 3 identifies the external signal names the associated pin ball numbers along with the mechanical package designator the pin type l O Z or 1 2 whether the pin has any internal pullup pulldown resistors and a functional pin description For more deta
149. O DMA Channel 0 Mapping Register 02A0 0104 DCHMAP1 DMA Channel 1 Mapping Register 02A0 0108 DCHMAP2 DMA Channel 2 Mapping Register 02A0 010C DMA Channel 3 Mapping Register 02A0 0110 DCHMAP4 DMA Channel 4 Mapping Register 02A0 0114 DCHMAP5 DMA Channel 5 Mapping Register 02A0 0118 DCHMAP6 DMA Channel 6 Mapping Register 02A0 011C DCHMAP7 DMA Channel 7 Mapping Register 02A0 0120 DCHMAP8 DMA Channel 8 Mapping Register 02A0 0124 DCHMAP9 DMA Channel 9 Mapping Register 02A0 0128 DCHMAP10 DMA Channel 10 Mapping Register 02A0 012C DCHMAP11 DMA Channel 11 Mapping Register 02A0 0130 DCHMAP12 DMA Channel 12 Mapping Register 02A0 0134 DCHMAP13 DMA Channel 13 Mapping Register 02A0 0138 DCHMAP14 DMA Channel 14 Mapping Register 02A0 013C DCHMAP15 DMA Channel 15 Mapping Register 02A0 0140 DCHMAP16 DMA Channel 16 Mapping Register 02A0 0144 DCHMAP17 DMA Channel 17 Mapping Register 02A0 0148 DCHMAP18 DMA Channel 18 Mapping Register 02A0 014C DCHMAP19 DMA Channel 19 Mapping Register 02A0 0150 DCHMAP20 DMA Channel 20 Mapping Register 02A0 0154 DCHMAP21 DMA Channel 21 Mapping Register 02A0 0158 DCHMAP22 DMA Channel 22 Mapping Register 02A0 015C DCHMAP23 DMA Channel 23 Mapping Register 02A0 0160 DCHMAP24 DMA Channel 24 Mapping Register 02A0 0164 DCHMAP25 DMA Channel 25 Mapping Register 02A0 0168 DCHMAP26 DMA Channel 26 Mapping Register 02A0 016C DCHMAP27 DMA Channel 27 Mapping Register 02A0 0170 DCHMAP28 DMA Channel 28 Mapping Register 02A0 0174 DCHMAP29 DM
150. O Options Register 1 02A2 8344 DFSRC1 Destination FIFO Source Address Register 1 02A2 8348 DFCNT1 Destination FIFO Count Register 1 02A2 834C DFDST1 Destination FIFO Destination Address Register 1 02A2 8350 DFBIDX1 Destination FIFO BIDX Register 1 02A2 8354 DFMPPRXY1 Destination FIFO Memory Protection Proxy Register 1 02A2 8358 02A2 837C Reserved 02A2 8380 DFOPT2 Destination FIFO Options Register 2 02A2 8384 DFSRC2 Destination FIFO Source Address Register 2 02A2 8388 DFCNT2 Destination FIFO Count Register 2 02A2 838C DFDST2 Destination FIFO Destination Address Register 2 02A2 8390 DFBIDX2 Destination FIFO BIDX Register 2 02A2 8394 DFMPPRXY2 Destination FIFO Memory Protection Proxy Register 2 02A2 8398 02A2 83BC Reserved 02A2 83C0 DFOPT3 Destination FIFO Options Register 3 02 2 83 4 DFSRC3 Destination FIFO Source Address Register 3 02A2 83C8 DFCNT3 Destination FIFO Count Register 3 02A2 83CC DFDST3 Destination FIFO Destination Address Register 3 02A2 83D0 DFBIDX3 Destination FIFO BIDX Register 3 02A2 83D4 DFMPPRXY3 _ Destination FIFO Memory Protection Proxy Register 02A2 83D8 02A2 FFFF Reserved Table 7 8 EDMA3 Transfer Controller 2 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A3 0000 PID Peripheral Identification Register 02A3 0004 TCCFG EDMAS3TC Configuration Register 02A3 0008 02 00 Reserved 02A3 0100 TCSTAT Channel Statu
151. OSL Pulse duration SYSCLK4 low 4 07 6P 0 7 ns 4 Transition time SYSCLK4 1 ns 1 The reference points for the rise and fall transitions are measured at 3 3 V Vo MAX and Voy MIN 2 P 1 CPU clock frequency in nanoseconds ns 4 T k 3 4 le Figure 7 22 SYSCLKA Timing Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 137 PRODUCT PREVIEW MalAddd TMS320C6454 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 8 PLL2 and PLL2 Controller 1 8 V www ti com The secondary PLL controller generates interface clocks for the Ethernet media access controller EMAC and the DDR2 memory controller As shown in Figure 7 23 the PLL2 controller features a PLL multiplier controller and one divider D1 The PLL multiplier is fixed to a x20 multiplier rate and the divider D1 can be programmed to a 2 or 5 mode PLL2 power is supplied externally via the PLL2 power supply PLLV2 An external PLL filter circuit must be added to PLLV2 as shown in Figure 7 23 The 1 8 V supply for the EMI filter must be from the same 1 8 V power plane supplying the I O power supply pin DVpp a TI requires EMI filter manufacturer Murata part number NFM18CC222R1C3 All PLL external components C161 C162 and the EMI Filter should be placed as close to the C64x DSP device as possible For the best performa
152. OT HDS1 HDS2 OR 5 2 SYSCLK3 period 6 CPU clock frequency in ns For example when running parts at 1000 MHz use M 6 ns 3 Select signals include 1 0 and HR W For 16 mode only select signals also include HHWIL Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 167 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 56 Switching Characteristics for Host Port Interface Cycles see Table 7 56 through Figure 7 51 720 850 NO PARAMETER 1000 UNIT MIN MAX Case 1 HPIC or HPIA read 5 15 Case 2 HPID read with no A auto increment 9 9 M 20 Delay time HSTROBE low to Case 3 HPID read with auto increment 1 DSP data valid and read FIFO initially empty 9 9 M r20 de Case 4 HPID read with auto increment and data previously prefetched into the 5 15 read FIFO 2 ldis HSTBH HDV Disable time HD high impedance from HSTROBE high 1 4 ns 3 ten HSTBL HD Enable time HD driven from HSTROBE low 3 15 ns 4 ty HSTBL HRDYH Delay time HSTROBE low to HRDY high 12 ns 5 ld HSTBH HRDYH Delay time HSTROBE high to HRDY high 12 ns Case 1 HPID read with no 10 M 20 amp li Delay time HSTROBE low auto increment a HRDY low Case 2 HPID read with
153. PCI a 16 pin general purpose input output port GPIO with programmable interrupt event generation modes an 10 100 1000 Ethernet media access controller EMAC which provides an efficient interface between the C6454 DSP core processor and the network a management data input output MDIO module also part of the that continuously polls all 33 MDIO addresses order to enumerate all PHY devices in the system a glueless external memory interface 64 bit EMIFA which is capable of interfacing to synchronous and asynchronous peripherals and a 32 bit DDR2 SDRAM interface The 2 ports on the C6454 allows the DSP to easily control peripheral devices and communicate with a host processor In addition the standard multichannel buffered serial port McBSP may be used to communicate with serial peripheral interface SPI mode peripheral devices The C6454 has a complete set of development tools which includes a new C compiler an assembly optimizer to simplify programming and scheduling and a Windows debugger interface for visibility into source code execution Submit Documentation Feedback TMS320C6454 Fixed Point Digital Signal Processor 3 PRODUCT PREVIEW MalAddd TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 1 3 Functional Block Diagram Figure 1 2 shows the functional block diagram of the C6454 device DDR2 DDR2 SDRAM
154. PCI I2C EEPROM Auto Initialization PCI EEAI status bit Shows whether the PCI auto initialization via external 2 EEPROM is enabled disabled 0 PCI auto initialization through external 2 EEPROM is disabled the PCI peripheral uses the specified PCI default values default 1 PCI auto initialization through external 2 EEPROM is enabled the PCI peripheral is configured through external 2 EEPROM provided the PCI peripheral pin is enabled PCI EN 1 10 9 MACSEL 1 0 EMAC Interface Select MACSEL 1 0 status bits Shows which interface mode has been selected 00 10 100 EMAC MDIO with MII Interface default 01 10 100 EMAC MDIO with RMII Interface 10 10 100 1000 EMAC MDIO with GMII Interface 11 10 100 1000 EMAC MDIO with RGMII Mode Interface RGMII interface requires a 1 8 V or 1 5 V I O supply 8 7 Reserved Reserved Read only writes have no effect 6 LENDIAN Device Endian mode LENDIAN Shows the status of whether the system is operating in Big Endian mode or Little Endian mode default 0 System is operating in Big Endian mode System is operating in Little Endian mode default 5 HPI_WIDTH HPI bus width control bit Shows the status of whether the HPI bus operates in 32 bit mode or in 16 bit mode default 0 HPI operates in 16 bit mode default HPI operates in 32 bit mode 4 AECLKINSEL EMIFA input clock select Shows the status of what clock mode is enabled or disabled for EMIF
155. PRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com Table 7 101 External Memory Space continued HEX ADDRESS OFFSET ACRONYM REGISTER NAME 4780 0000 47FF FFFF PCI Master Window 15 4800 0000 487F FFFF PCI Master Window 16 4880 0000 48FF FFFF PCI Master Window 17 4900 0000 497F FFFF PCI Master Window 18 4980 0000 49FF FFFF PCI Master Window 19 4A00 0000 4A7F FFFF PCI Master Window 20 4A80 0000 4AFF FFFF PCI Master Window 21 4B00 0000 4B7F FFFF PCI Master Window 22 4B80 0000 4BFF FFFF PCI Master Window 23 4 00 0000 4C7F FFFF PCI Master Window 24 4C80 0000 4CFF FFFF PCI Master Window 25 4000 0000 4D7F FFFF PCI Master Window 26 4080 0000 4DFF FFFF PCI Master Window 27 4E00 0000 4E7F FFFF PCI Master Window 28 4 80 0000 4EFF FFFF PCI Master Window 29 4 00 0000 4F7F FFFF PCI Master Window 30 4 80 0000 4FFF FFFF PCI Master Window 31 212 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 7 16 3 PCI Electrical Data Timing Texas Instruments TI has performed the simulation and system characterization to ensure that the PCI peripheral meets all AC timi
156. PRS311A APRIL 2006 REVISED DECEMBER 2006 Table 5 9 Megamodule L1 L2 Memory Protection Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 0184 20 L2MPPA3 L2 memory protection page attribute register 3 0184 A210 L2MPPA4 L2 memory protection page attribute register 4 0184 A214 L2MPPA5 L2 memory protection page attribute register 5 0184 A218 L2MPPA6 L2 memory protection page attribute register 6 0184 A21G L2MPPA7 L2 memory protection page attribute register 7 0184 A220 L2MPPA8 L2 memory protection page attribute register 8 0184 A224 L2MPPA9 L2 memory protection page attribute register 9 0184 A228 L2MPPA10 L2 memory protection page attribute register 10 0184 A22G L2MPPA11 L2 memory protection page attribute register 11 0184 A230 L2MPPA12 L2 memory protection page attribute register 12 0184 A234 L2MPPA13 L2 memory protection page attribute register 13 0184 A238 L2MPPA14 L2 memory protection page attribute register 14 0184 A23C L2MPPA15 L2 memory protection page attribute register 15 0184 A240 L2MPPA16 L2 memory protection page attribute register 16 0184 A244 L2MPPA17 L2 memory protection page attribute register 17 0184 A248 L2MPPA18 L2 memory protection page attribute register 18 0184 24 L2MPPA19 L2 memory protection page attribute register 19 0184 A250 L2MPPA20 L2 memory protection page
157. Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 8 2 PLL2 Controller Memory The memory map of the PLL2 controller is shown in Table 7 32 Note that only registers documented here are accessible on the TMS320C6454 Other addresses in the PLL2 controller memory map should not be modified Table 7 32 PLL2 Controller Registers HEX ADDRESS RANGE ACRONYM DESCRIPTION 029C 0000 029C 0114 Reserved 029C 0118 PLLDIV1 PLL Controller Divider 1 Register 029 011C 029C 0134 Reserved 029C 0138 PLLCMD PLL Controller Command Register 029C 013C PLLSTAT PLL Controller Status Register 029C 0140 ALNCTL PLL Controller Clock Align Control Register 029C 0144 DCHANGE PLLDIV Ratio Change Status Register 029C 0148 Reserved 029C 014C Reserved 029C 0150 SYSTAT SYSCLK Status Register 029C 0154 029C 0190 Reserved 029C 0194 029C 01FF Reserved 029C 0200 029C FFFF Reserved 7 8 3 PLL2 Controller Register Descriptions This section provides a description of the PLL2 controller registers For details on the operation of the PLL controller module see the TMS320C645x DSP Software Programmable Phase Locked Loop PLL Controller User s Guide literature number SPRUE56 NOTE The PLL2 controller registers can only be accessed using the CPU or the emulator Not all of the registers documented in the TMS320C645x DSP Software Programmable Phase Locked Loop PLL Contro
158. RAE4 DMA Region Access Enable Register for Region 4 02A0 0364 DRAEH4 DMA Region Access Enable Register High for Region 4 02A0 0368 DRAE5 DMA Region Access Enable Register for Region 5 02A0 036C DRAEH5 DMA Region Access Enable Register High for Region 5 02A0 0370 DRAE6 DMA Region Access Enable Register for Region 6 02A0 0374 DRAEH6 DMA Region Access Enable Register High for Region 6 02A0 0378 DRAE7 DMA Region Access Enable Register for Region 7 02A0 037C DRAEH7 DMA Region Access Enable Register High for Region 7 02A0 0380 QRAEO QDMA Region Access Enable Register for Region 0 02A0 0384 QRAE1 QDMA Region Access Enable Register for Region 1 02A0 0388 QRAE2 QDMA Region Access Enable Register for Region 2 02A0 038C QRAE3 QDMA Region Access Enable Register for Region 3 02A0 0390 02A0 039C z Reserved 02A0 0400 QOEO Event Queue 0 Entry Register 0 02A0 0404 QOE1 Event Queue 0 Entry Register 1 02A0 0408 QOE2 Event Queue 0 Entry Register 2 02A0 040C QOES3 Event Queue 0 Entry Register 3 02A0 0410 QOE4 Event Queue 0 Entry Register 4 02A0 0414 QOE5 Event Queue 0 Entry Register 5 02A0 0418 QOE6 Event Queue 0 Entry Register 6 02A0 041C QOE7 Event Queue 0 Entry Register 7 02 0 0420 QOE8 Event Queue 0 Entry Register 8 02 0 0424 QOE9 Event Queue 0 Entry Register 9 02 0 0428 QOE10 Event Queue 0 Entry Register 10 02A0 042C QOE11 Event Queue 0 Entry Register 11 02A0 0430 Q0E12 Event Queue 0 Entry Register 12 02A0 0434 Q0E13 Event Queue 0 Entry Register 13 02A0 0438 Q
159. REFCLKH Pulse duration RMREFCLK high 7 13 ns 2 tw RMREFCLKL Pulse duration RMREFCLK low 7 13 ns lRMREFCLK Transition time RMREFCLK 2 ns od aa Input k 2 3 4 le Figure 7 65 RMREFCLK Timing Table 7 82 Switching Characteristics Over Recommended Operating Conditions for EMAC RMII Transmit 10 100 Mbit s see Figure 7 66 720 850 NO PARAMETER 1000 UNIT 1000 Mbps MIN MAX 1 ta RMREFCLKH MTXD Delay time RMREFCLK high to transmit selected signals valid 3 10 ns 1 For RMIl transmit selected signals include MTXD 1 0 and MTXEN RMREFCLK u Input N NF N MTXD1 MTXD0 A 059500000000 MTXEN Outputs 4 900 RRRS Figure 7 66 EMAC Transmit Interface Timing RMII Operation 198 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 Table 7 83 Timing Requirements for EMAC RMII Input Receive for 100 Mbps see Figure 7 67 720 850 NO 1000 UNIT MIN MAX Setup time receive selected signals valid before MREFCLK at DSP 1 tsu MRXD MREFCLK pi 4 0 ns high low 2 thimREFCLK MRxD Hold time receive selected signals valid after MREFCLK at DSP high low 2 0 ns 1 For RMII receive selected signals include MRXD 1 0 MRXER and MCRSDV
160. RONYM DSP ACCESS REGISTER NAME 02 0 0000 02 0 000F Reserved 02 0 0010 PCISTATSET PCI Status Set Register 02C0 0014 PCISTATCLR PCI Status Clear Register 02 0 0018 02 0 001F Reserved 02C0 0020 PCIHINTSET PCI Host Interrupt Enable Set Register 02C0 0024 PCIHINTCLR PCI Host Interrupt Enable Clear Register 02 0 0028 02 0 002F Reserved 02C0 0030 PCIBINTSET PCI Back End Application Interrupt Enable Set Register 02C0 0034 PCIBINTCLR PCI Back End Application Interrupt Enable Clear Register 02C0 0038 PCIBCLKMGT PCI Back End Application Clock Management Register 02 0 003C 02 0 OOFF Reserved 02 0 0100 PCIVENDEVMIR PCI Vendor ID Device ID Mirror Register 02 0 0104 PCICSRMIR PCI Command Status Mirror Register 02 0 0108 PCICLREVMIR PCI Class Code Revision ID Mirror Register 02 0 010C PCICLINEMIR PCI BIST Header Type Latency Timer Cacheline Size Mirror Register 02 0 0110 PCIBAROMSK Base Address Mask Register 0 02C0 0114 PCIBAR1MSK PCI Base Address Mask Register 1 02 0 0118 PCIBAR2MSK PCI Base Address Mask Register 2 02 0 011C PCIBAR3MSK PCI Base Address Mask Register 02 0 0120 PCIBARAMSK PCI Base Address Mask Register 4 02 0 0124 PCIBAR5MSK PCI Base Address Mask Register 5 02 0 0128 02C0 012B Reserved 02C0 012C PCISUBIDMIR PCI Subsystem Vendor ID Subsystem ID Mirror Register 02 0 0130 Reserved 02C0 0134 PCICPBPTRMIR PCI Capabilities Pointer Mirror Register 02C0 0138 02C0 013B Reserved
161. ROjc Junction to case 1 45 N A 2 Junction to board 8 34 N A 3 16 1 0 00 4 13 0 1 0 ROJA Junction to free air 5 11 9 2 0 6 10 7 3 0 0 37 0 00 0 89 1 0 7 Junction to package top 101 15 1 17 3 00 7 6 0 00 6 7 1 0 8 Junction to board 64 15 5 8 3 00 1 m s meters per second 8 2 Packaging Information The following packaging information reflects the most current released data available for the designated device s This data is subject to change without notice and without revision of this document Submit Documentation Feedback Mechanical Data 217 PRODUCT PREVIEW Mal aad Lonaoad TMS32006454 Fixed Point Digital Signal Processor 6 INSTRUMENTS www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 218 Revision History This data sheet revision history highlights the technical changes made to the SPRS311 device specific data sheet to make it an SPRS311A revision Scope Applicable updates to the C64x device family specifically relating to the TMS320C6454 device have been incorporated C6454 Revision History Section 2 8 2 1 Section 2 8 2 2 Section 3 1 Section 3 3 Section 3 4 1 SEE ADDITIONS MODIFICATIONS DELETIONS Global Changed DDR2 Memory Controller speed to 533 MHz Changed L2 Memory size to 1048KB Section 1 1 Features Changed EMIFA bullet to 64 Bit External Memory Interface EMIFA Added 1 25 V Internal Sectio
162. SH Receive Channel 1 Flow Control Threshold Register 02C8 0128 RX2FLOWTHRESH Receive Channel 2 Flow Control Threshold Register 02C8 012C RXSFLOWTHRESH Receive Channel 3 Flow Control Threshold Register 02C8 0130 RX4FLOWTHRESH Receive Channel 4 Flow Control Threshold Register 02C8 0134 RX5FLOWTHRESH Receive Channel 5 Flow Control Threshold Register 02C8 0138 RX6FLOWTHRESH Receive Channel 6 Flow Control Threshold Register 02C8 013C RX7FLOWTHRESH Receive Channel 7 Flow Control Threshold Register 02C8 0140 RXOFREEBUFFER Receive Channel 0 Free Buffer Count Register 02C8 0144 RX1FREEBUFFER Receive Channel 1 Free Buffer Count Register 02C8 0148 RX2FREEBUFFER Receive Channel 2 Free Buffer Count Register 02C8 014C RX3FREEBUFFER Receive Channel 3 Free Buffer Count Register 02C8 0150 RX4FREEBUFFER Receive Channel 4 Free Buffer Count Register Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 191 PRODUCT PREVIEW Mal aad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com Table 7 71 Ethernet MAC EMAC Control Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02C8 0154 RX5FREEBUFFER Receive Channel 5 Free Buffer Count Register 02C8 0158 RX6FREEBUFFER Receive Channel 6 Free Buffer Count Register 02C8 015C RX7FREEBUFFER Rece
163. SP platform including tools to evaluate the performance of the processors generate code develop algorithm implementations and fully integrate and debug software and hardware modules The tool s support documentation is electronically available within the Code Composer Studio Integrated Development Environment IDE The following products support development of 60007 DSP based applications Software Development Tools Code Composer Studio Integrated Development Environment IDE including Editor C C Assembly Code Generation and Debug plus additional development tools Scalable Real Time Foundation Software DSP BIOS which provides the basic run time target software needed to support any DSP application Hardware Development Tools Extended Development System XDS Emulator Supports C6000 DSP multiprocessor system debug EVM Evaluation Module 2 8 2 Device Support 2 8 2 1 Device and Development Support Tool Nomenclature To designate the stages in the product development cycle assigns prefixes to the part numbers of all DSP devices and support tools Each DSP commercial family member has one of three prefixes TMX TMP or TMS e g TMX320C6454ZTZ Texas Instruments recommends two of three possible prefix designators for its support tools TMDX and TMDS These prefixes represent evolutionary stages of product development from engineering prototypes TMX TMDX through fully qualified production devices tools T
164. STER NAME 7800 0000 MIDR DDR2 Memory Controller Module and Revision Register 7800 0004 DMCSTAT DDR2 Memory Controller Status Register 7800 0008 SDCFG DDR2 Memory Controller SDRAM Configuration Register 7800 000 SDRFC DDR2 Memory Controller SDRAM Refresh Control Register 7800 0010 SDTIM1 DDR2 Memory Controller SDRAM Timing 1 Register 7800 0014 SDTIM2 DDR2 Memory Controller SDRAM Timing 2 Register 7800 0018 Reserved 7800 0020 BPRIO DDR2 Memory Controller Burst Priority Register 7800 0024 7800 004 Reserved 7800 0050 7800 0078 Reserved 7800 007C 7800 00 Reserved 7800 00 0 7800 00 0 Reserved 7800 00 4 DMCCTL DDR2 Memory Controller Control Register 7800 00 8 7800 00FC Reserved 7800 0100 7FFF FFFF Reserved 7 9 3 DDR2 Memory Controller Electrical Data Timing The mplementing DDR2 PCB Layout on the TMS320C6454 application report literature number SPRAAA7 specifies a complete DDR2 interface solution for the C6454 as well as a list of compatible DDR2 devices TI has performed the simulation and system characterization to ensure all DDR2 interface timings in this solution are met therefore no electrical data timing information is supplied here for this interface only supports designs that follow the board design guidelines outlined in the SPRAAA7 application report 148 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 Texas TMS320C6454 INSTRUMEN
165. TIO is set to 0 1 in the PLL1 Multiplier Control Register PLLM and PLL1 Pre Divider Register PREDIV respectively The CLKIN1 frequency must not be greater than 50 MHz so that the maximum speed of the internal ROM 750 MHz is not violated The CFGGP 2 0 pins must be set to 000b during reset for proper operation of the PCI boot mode As mentioned previously a DSP interrupt must be generated at the end of the host boot process to begin execution of the loaded application Since the DSP interrupt generated by the and PCI is mapped to the event DSP EVT DMA channel 0 it will get recorded in bit 0 of the EDMA Event Register ER This event must be cleared by software before triggering transfers on DMA channel 0 EMIFA 8 bit ROM boot BOOTMODE S 0 0100b After reset the device will begin executing software out of an Asynchronous 8 bit ROM located in EMIFA CES space using the default settings in the EMIFA registers This boot mode is a hardware boot mode e Master I2C boot BOOTMODE 3 0 0101b After reset the DSP can act as a master to the 2 bus and copy data from an 2 EEPROM or a device acting as an 2 slave to the DSP using a predefined boot table format The destination address and length are contained within the boot table This boot mode is a software boot mode e Slave I2C boot BOOTMODE 3 0 0110b A Slave 2 boot is also implemented which programs the DSP as 12C Slave and simply waits for a
166. TS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 7 10 External Memory Interface A EMIFA The EMIFA can interface to a variety of external devices or ASICs including e Pipelined and flow through Synchronous Burst SRAM SBSRAM ZBT Zero Bus Turnaround SRAM and Late Write SRAM e Synchronous FIFOs e Asynchronous memory including SRAM ROM and Flash 7 10 1 Device Specific Information Timing analysis must be done to verify all AC timings are met recommends utilizing I O buffer information specification IBIS to analyze all AC timings To properly use IBIS models to attain accurate timing analysis for a given system see the Using IBIS Models for Timing Analysis application report literature number SPRA839 To maintain signal integrity serial termination resistors should be inserted into all EMIF output signal lines for the EMIF output signals see Table 2 3 Terminal Functions A race condition may exist when certain masters write data to the EMIFA For example if master A passes a software message via a buffer in external memory and does not wait for indication that the write completes when master B attempts to read the software message then the master B read may bypass the master A write and thus master B may read stale data and therefore receive an incorrect message Some master peripherals e g EDMAS transfer controllers will always wait for the wr
167. Table 7 16 PLL1 Clock Frequency Ranges CLOCK SIGNAL MIN MAX UNIT CLKIN1 66 6 MHz PLLREF PLLEN 1 33 3 66 6 MHz PLLOUT 400 1000 MHz SYSCLK4 25 166 MHz SYSCLK5 333 MHz 1 Only applies when the PLL1 Controller is set to PLL mode 1 in the PLLCTL register 7 7 1 2 PLL1 Controller Operating Modes The PLL1 controller has two modes of operation bypass mode and PLL mode The mode of operation is determined by the PLLEN bit of the PLL control register PLLCTL In PLL mode SYSREFCLK is generated from the device input clock CLKIN1 using the divider PREDIV and the PLL multiplier PLLM In bypass mode CLKIN1 is fed directly to SYSREFCLK All hosts HPI PCI etc must hold off accesses to the DSP while the frequency of its internal clocks is changing A mechanism must be in place such that the DSP notifies the host when the PLL configuration has completed 7 7 1 3 PLL1 Stabilization Lock and Reset Times The PLL stabilization time is the amount of time that must be allotted for the internal PLL regulators to become stable after device powerup The PLL should not be operated until this stabilization time has expired The PLL reset time is the amount of wait time needed when resetting the PLL writing PLLRST 1 in order for the PLL to properly reset before bringing the PLL out of reset writing PLLRST 0 For the PLL1 reset time value see Table 7 17 Submit Documentation Feedback C64x Peripheral Inform
168. Therefore when using a software boot mode care must be taken such that the CPU frequency does not exceed 750 MHz at any point during the boot sequence After the boot sequence has completed the CPU frequency can be programmed to the frequency required by the application For more detailed information ont he boot modes see Section 2 4 Boot Sequence Submit Documentation Feedback Block base address 0080 0000h 008C 0000h 008E 0000h 008F 0000h 008F 8000h 0090 0000h C64x4 Megamodule 79 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 www ti com 5 2 Memory Protection Memory protection allows an operating system to define who or what is authorized to access L1D L1P and L2 memory To accomplish this the L1D L1P and L2 memories are divided into pages There are 16 pages of L1P 2KB each 16 pages of L1D 2KB each and 16 pages of L2 64KB each The L1D L1P and L2 memory controllers in the C64x Megamodule are equipped with a set of registers that specify the permissions for each memory page Each page may be assigned with fully orthogonal user and supervisor read write and execute permissions Additionally a page may be marked as either or both locally or globally accessible A local access is a direct CPU access to L1D L1P and L2 while a global access is initiated by a DMA either IDMA or
169. XD7 MTXD4 GMII only M M NN N NA N N N N N N N N NZ N N NAMA NZ N N NZ N NZ N NZ N NN N Y Y Y Y Y Y Y Y Y MTXD3 MTXDO RARE a TGS EU MTXEN Outputs _ Figure 7 63 EMAC Transmit Interface Timing MII and GMII Operation Table 7 80 Switching Characteristics Over Recommended Operating Conditions for EMAC GMII Transmit 1000 Mbit s see Figure 7 64 720 850 NO PARAMETER 1909 UNIT 1000 Mbps MIN MAX 1 Delay time GMTCLK high to transmit selected signals valid 0 5 5 ns 1 For GMII Transmit selected signals include GMTXD 7 0 and MTXEN ly 1 GMTCLK Output MU MTXD7 MTXDO AAA 555222200 MTXEN Outputs RRR KKK Figure 7 64 EMAC Transmit Interface Timing GMII Operation Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 197 PRODUCT PREVIEW MalAddd LONGOWd TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 14 3 2 EMAC RMII Electrical Data Timing The RMREFCLK pin is used to source a clock to the EMAC when it is configured for RMII operation The RMREFCLK frequency should be 50 MHz 50 PPM with a duty cycle between 35 and 65 inclusive Table 7 81 Timing Requirements for RMREFCLK RMII Operation see Figure 7 65 720 850 NO PARAMETER 1000 UNIT MIN MAX tw RM
170. able in progress state Others Reserved 14 12 TIMER1STAT status 000 is in the disabled state 001 Timer1 is in the enabled state 011 Timer1 is in the static powerdown state 101 Timer1 is in the enable in progress state Others Reserved 11 9 TIMEROSTAT TimerO status 000 0 is in the disabled state 001 is in the enabled state 011 is in the static powerdown state 101 is in the enable in progress state Others Reserved 8 6 EMACSTAT EMAC MDIO status 000 EMAC MDIO is the disabled state 001 EMAC MDIO is in the enabled state 011 EMAC MDIO is in the static powerdown state 101 EMAC MDIO is in the enable in progress state Others Reserved 5 0 Reserved Reserved Submit Documentation Feedback Device Configuration 61 PRODUCT PREVIEW Mal aad TMS320C6454 49 Texas Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 31 16 Reserved R 0 15 3 2 0 Reserved PCISTAT R 0 R 0 LEGEND R Read only n value after reset Figure 3 7 Peripheral Status Register 1 PERSTAT1 0x02AC 0018 Table 3 10 Peripheral Status Register 1 PERSTAT1 Field Descriptions Bit Field Value Description 31 3 Reserved Reserved 2 0 PCISTAT PCI status 000 PClis in the disabled state 001 PCI is in the enabled state 011 PCI is in the
171. after powerup and externally drive TRST high before attempting any emulation or boundary scan operations 7 18 2 JTAG Peripheral Register Description s 7 18 3 JTAG Electrical Data Timing Table 7 105 Timing Requirements for JTAG Test Port see Figure 7 75 720 850 NO 1000 UNIT MIN MAX 1 tock Cycle time TCK 35 ns 3 tsu TDIV TCKH Setup time TDI TMS TRST valid before TCK high 10 ns 4 th TCKH TDIV Hold time TDI TMS TRST valid after TCK high 9 ns Table 7 106 Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port see Figure 7 75 720 850 NO PARAMETER 1000 UNIT MIN MAX 2 Delay time low valid 3 18 ns 1 gt TCK y Y maaa _ 4 4 3 TD TMS TRSTL XR C C aaa C WAY Figure 7 75 JTAG Test Port Timing 216 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 6 INSTRUMENTS www ti com 8 Mechanical Data 8 1 Thermal Data Table 8 1 shows the thermal resistance characteristics for the PBGA ZTZ GTZ mechanical package 5320 6454 Table 8 1 Thermal Resistance Characteristics S PBGA Package ZTZ GTZ Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 NO C W AIR FLOW m s 1
172. and five dividers PREDIV D2 D3 D4 and D5 The PLL1 controller uses the device input clock to generate a system reference clock SYSREFCLK and four system clocks SYSCLK2 SYSCLK3 SYSCLK4 and SYSCLK5 PLL1 power is supplied externally via the PLL1 power supply pin PLLV1 An external EMI filter circuit must be added to PLLV1 as shown in Figure 7 10 The 1 8 V supply of the EMI filter must be from the same 1 8 V power plane supplying the I O power supply pin DVppig TI requires EMI filter manufacturer Murata part number NFM18CC222R1C3 All PLL external components C1 C2 and the EMI Filter must be placed as close to the C64x DSP device as possible For the best performance TI recommends that all the PLL external components be on a single side of the board without jumpers switches or components other than the ones shown For reduced PLL jitter maximize the spacing between switching signals and the PLL external components C1 C2 and the EMI Filter The minimum CLKIN1 rise and fall times should also be observed For the input clock timing requirements see Section 7 7 4 PLL1 Controller Input and Output Clock Electrical Data Timing CAUTION The PLL controller module as described in the 7MS320C645x DSP Software Programmable Phase Locked Loop PLL Controller User s Guide literature number SPRUE56 includes a superset of features some of which not supported on the C6454 DSP The following sections describe the f
173. ansmission line delay 2 ns from the data sheet timings Input requirements in this data sheet are tested with an input slew rate of lt 4 Volts per nanosecond 4 V ns at the device pin Figure 7 1 Test Load Circuit for AC Timing Measurements The load capacitance value stated is only for characterization and measurement of AC timing signals This load capacitance value does not indicate the maximum load the device is capable of driving 7 1 1 3 3 V Signal Transition Levels All input and output timing parameters are referenced to 1 5 V for both 0 and 1 logic levels Vret 1 5 V Figure 7 2 Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are referenced to V MAX and Vj MIN for input clocks Voi MAX and Voy MIN for output clocks Vret Vin MIN or MIN Vref Vip MAX or VoL MAX Figure 7 3 Rise and Fall Transition Time Voltage Reference Levels 7 1 2 3 3 V Signal Transition Rates All timings are tested with an input edge rate of 4 volts per nanosecond 4 V ns 94 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback K Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 1 3 Timing Parameters and Board Routing Analysis The timing parameter values specified in this data sheet do not include delays by board routings As a
174. aphs EMIFA Peripheral Register Description s Changed Burst Priority Register acronym to BURST_PRIO in Table 7 41 EMIFA Registers EMIFA Electrical Data Timing Updated footnotes for Table 7 45 Table 7 47 and Figure 7 33 Figure 7 36 Figure 7 37 and Figure 7 38 Updated Figure 7 34 Asynchronous Memory Write Timing for EMIFA HPI Peripheral Register Description s Updated Comments for HPIC in Table 7 54 HPI Control Registers Updated Hex Address and Comments for HPIA registers Added Footnote 1 Updated Footnote 2 HPI Electrical Data Timing Changed Parameter NO 18 MIN value to 1 ns and Parameter NO 38 MIN value to 1 1 ns in Table 7 55 Timing Requirements for Host Port Interface Cycles Replaced TBD document reference with TMS320C645x DSP Host Port Interface User s Guide literature number SPRU969 in Figure 7 44 through Figure 7 51 McBSP Device Specific Information Added paragraph McBSP Electrical Data Timing Changed Parameter NO 4 MAX value to 3 3 ns in Table 7 60 Switching Characteristics Over Recommended Operating Conditions for McBSP EMAC Device Specific Information Deleted Step 1 and changed setting to clearing under Using the RMII Mode of the EMAC Moved Table 7 70 EMAC MDIO Multiplexed Pins MII and GMII Modes under Interface Mode Select Added Interface Mode Clocking section and paragraphs EMAC Peripheral Register Description s Corrected Hex Addresses for 02C8 0080 through 02C8 0090 in Table 7 7
175. as GPIO pins 1 McBSP1 pin function enabled This means all multiplexed McBSP1 GPIO pins function as McBSP1 pins AEA4 T28 IPD SYSCLKOUT Enable bit SYSCLKOUT_EN Selects which function is enabled on the SYSCLK4 GP 1 muxed pin 0 GP 1 pin function is enabled default 1 SYSCLKA pin function is enabled 27 IPD For proper C6454 device operation the AEA3 pin must be pulled down to Vss using a 1 kQ resistor AEA 2 0 T26 U26 U25 IPD Configuration General Purpose Inputs CFGGP 2 0 The value of these pins is latched to the Device Status Register following device reset and is used by the on chip bootloader for some boot modes For more information on the boot modes see Section 2 4 Boot Sequence Submit Documentation Feedback Device Configuration 51 PRODUCT PREVIEW Mal aad TMS320C6454 49 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 3 1 C6454 Device Configuration Pins AEA 19 0 ABA 1 0 and continued bM M ange FUNCTIONAL DESCRIPTION PCI pin function enable bit PCI EN Selects which function is enabled on the HPI PCI multiplexed pins POLEN d RD Pe O ie pins function as HPI pins 1 PCI pin function enabled This means all multiplexed HPI PCI pins function as PCI pins DDR2 Memory Controller enable DDR2_EN ABAO V26 IPD 0 DDR2 Memory Controller pe
176. ation and Electrical Specifications 125 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 The PLL lock time is the amount of time needed from when the PLL is taken out of reset PLLRST 1 with PLLEN 0 to when to when the PLL controller can be switched to PLL mode PLLEN 1 The PLL1 lock time is given in Table 7 17 Table 7 17 PLL1 Stabilization Lock and Reset Times MIN TYP MAX UNIT PLL stabilization time 150 us PLL lock time 2000 C 1 ns PLL reset time 128 1 ns 1 CLKIN1 cycle time in ns For example when CLKIN1 frequency is 50 MHz use C 20 ns 7 7 2 PLL1 Controller Memory Map The memory map of the PLL1 controller is shown in Table 7 18 Note that only registers documented here are accessible on the TMS320C6454 Other addresses in the PLL1 controller memory map should not be modified Table 7 18 PLL1 Controller Registers Including Reset Controller HEX ADDRESS RANGE ACRONYM REGISTER NAME 029A 0000 029A 00 Reserved 029A 00 4 RSTYPE Reset Type Status Register Reset Controller 029A 00 8 029A 00FF Reserved 029A 0100 PLLCTL PLL Control Register 029A 0104 Reserved 029A 0108 Reserved 029A 010G Reserved 029A 0110 PLLM PLL Multiplier Control Register
177. attribute register 20 0184 A254 L2MPPA21 L2 memory protection page attribute register 21 0184 A258 L2MPPA22 L2 memory protection page attribute register 22 0184 A25G L2MPPA23 L2 memory protection page attribute register 23 0184 A260 L2MPPA24 L2 memory protection page attribute register 24 0184 A264 L2MPPA25 L2 memory protection page attribute register 25 0184 A268 L2MPPA26 L2 memory protection page attribute register 26 0184 A26G L2MPPA27 L2 memory protection page attribute register 27 0184 A270 L2MPPA28 L2 memory protection page attribute register 28 0184 A274 L2MPPA29 L2 memory protection page attribute register 29 0184 A278 L2MPPA30 L2 memory protection page attribute register 30 0184 27 L2MPPA31 L2 memory protection page attribute register 31 0184 A280 0184 A3FF Reserved 0184 A400 L1PMPFAR L1 program L1P memory protection fault address register 0184 A404 L1PMPFSR L1P memory protection fault status register 0184 A408 L1PMPFCR L1P memory protection fault command register 0184 A40C 0184 A4FF Reserved 0184 A500 L1PMPLKO L1P memory protection lock key bits 31 0 0184 A504 L1PMPLK1 L1P memory protection lock key bits 63 32 0184 A508 L1PMPLK2 L1P memory protection lock key bits 95 64 0184 A50C L1PMPLKS L1P memory protection lock key bits 127 96 0184 A510 L1PMPLKCMD L1P memory protection lock key command register 0184 A514 L1PMPLKSTAT L1P memory protection lock key status register 0184 A518 0184 ABFF Reserved 0184 ACOO L1DMPFAR
178. be lower due to EDMA limitations and AC timing requirements 4 This parameter applies to the maximum McBSP frequency Operate serial clocks CLKR X in the reasonable range of 40 60 duty cycle Table 7 60 Switching Characteristics Over Recommended Operating Conditions for McBSP see Figure 7 52 720 850 NO PARAMETER 1000 UNIT MIN MAX Delay time CLKS high to CLKR X high for internal CLKR X la CKSH CKRXH generated from CLKS input 14 10 ms 2 lc CKRX Cycle time CLKR X CLKR X int 6P or 10 4 5 6 ns 1 CLKRP CLKXP FSRP FSXP 0 If polarity of any of the signals is inverted then the timing references of that signal are also inverted Minimum delay times also represent minimum output hold times 3 The CLKS signal is shared by both McBSPO and McBSP1 on this device Minimum CLKR X cycle times must be met even when CLKR X is generated by an internal clock source Minimum CLKR X cycle times are based on internal logic speed the maximum usable speed may be lower due to EDMA limitations and AC timing requirements P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 6 Use whichever value is greater 180 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 Table 7 60 Swi
179. bmit Documentation Feedback Device Overview 49 PRODUCT PREVIEW Mal aad TMS32006454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 3 Device Configuration 6 INSTRUMENTS www ti com On the C6454 device certain device configurations like boot mode pin multiplexing and endianess are selected at device reset The status of the peripherals enabled disabled is determined after device reset By default the peripherals on the C6454 device are disabled and need to be enabled by software before being used 3 1 Device Configuration at Device Reset Table 3 1 describes the C6454 device configuration pins The logic level of the AEA 19 0 ABA 1 0 and PCI_EN pins is latched at reset to determine the device configuration The logic level on the device configuration pins can be set by using external pullup pulldown resistors or by using some control device e g FPGA CPLD to intelligently drive these pins When using a control device care should be taken to ensure there is no contention on the lines when the device is out of reset The device configuration pins are sampled during reset and are driven after the reset is removed To avoid contention the control device should only drive the EMIFA pins when RESETSTAT is low NOTE If a configuration pin must be routed out from the device and 3 stated not driven the internal pullup pulldown IPU IPD resistor should not
180. c Information The CLKS signal is shared by both McBSPO and McBSP1 on this device Also the CLKGDV field of the Sample Rate Generator Register SRGR must always be set to a value of 1 or greater The McBSP Data Receive Register DRR and Data Transmit Register DXR can be accessed through two separate busses a configuration bus and a data bus Both paths can be used by the CPU and the EDMA The data bus should be used to service the McBSP as this path provides better performance However since the data path shares a bridge with the PCI peripheral see Figure 4 1 the configuration path should be used in cases where this peripheral is being used to avoid any performance degradation Note that the PCI peripheral consists of an independent master and slave Performance degradation is only a concern when this peripheral is used to initiate transactions on the external bus 7 13 1 1 McBSP Peripheral Register Description s Table 7 57 McBSP 0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS The CPU and EDMA3 controller can only read 028C 0000 DRRO McBSPO Data Receive Register via Configuration Bus this register they cannot write to it 3000 0000 DRRO McBSPO Data Receive Register via EDMAS3 Bus 028C 0004 DXRO McBSPO Data Transmit Register via Configuration Bus 3000 0010 DXRO McBSPO Data Transmit Register via EDMA Bus 028C 0008 SPCRO McBSPO Serial Port Control Regis
181. ced Event Generator Register 0 0180 0144 AEGMUX1 Advanced Event Generator Mux Register 1 0180 0148 0180 017C Reserved 0180 0180 INTXSTAT Interrupt Exception Status Register Submit Documentation Feedback C64x Megamodule 83 PRODUCT PREVIEW MalAddd TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com Table 5 4 Megamodule Interrupt Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 0180 0184 INTXCLR Interrupt Exception Clear Register 0180 0188 INTDMASK Dropped Interrupt Mask Register 0180 0188 0180 01BC Reserved 0180 01 0 EVTASRT Event Asserting Register 0180 01C4 0180 FFFF Reserved Table 5 5 Megamodule Powerdown Control Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0181 0000 PDCCMD Power down controller command register 0181 0004 0181 1FFF Reserved Table 5 6 Megamodule Revision Register HEX ADDRESS RANGE ACRONYM REGISTER NAME 0181 2000 MM_REVID Megamodule Revision ID Register 0181 2004 0181 2FFF Reserved Table 5 7 Megamodule IDMA Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0182 0000 IDMAOSTAT IDMA Channel 0 Status Register 0182 0004 IDMAOMASK IDMA Channel 0 Mask Register 0182 0008 IMDAOSRC IDMA
182. ck in conjunction with the PLL divider ratio bits RATIO in PREDIV Oh x1 multiplier rate Eh x15 multiplier rate 13h x20 multiplier rate 18h x25 multiplier rate 1Dh x30 multiplier rate 1Fh x32 multiplier rate 128 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 6 INSTRUMENTS www ti com TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 7 3 3 PLL Pre Divider Control Register The PLL pre divider control register PREDIV is shown in Figure 7 13 and described in Table 7 21 31 16 R 0 15 14 5 4 0 R W 1 R 0 R W 2h LEGEND R W Read Write Read only n value after reset Figure 7 13 PLL Pre Divider Control Register PREDIV Hex Address 029A 0114 Table 7 21 PLL Pre Divider Control Register PREDIV Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 PREDEN Pre divider enable bit 0 Pre divider is disabled No clock output 1 Pre divider is enabled 14 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 4 0 RATIO O 1Fh Divider ratio bits 0 1 Divide frequency by 1 1h 2 Divide frequency by 2 2h 3 Divide frequency by 3 3h 1Fh Reserved do not use Submit Docum
183. d chained and cleared etc see the TMS320C645x DSP Enhanced DMA Controller User s Guide literature number SPRU966 Table 7 3 C6454 EDMA3 Channel Synchronization Events EHANNEL BINARY EVENT NAME EVENT DESCRIPTION 02 000 0000 DSP_EVT HPI PCI to DSP event 1 000 0001 TEVTLOO Timer 0 lower counter event 2 000 0010 TEVTHIO Timer 0 high counter event 3 000 0011 None 4 000 0100 None 5 000 0101 None 6 000 0110 None 7 000 0111 None 8 000 1000 None 9 000 1001 None 10 000 1010 None 11 000 1011 None 12 000 1100 XEVTO McBSPO transmit event 13 000 1101 REVTO McBSPO receive event 14 000 1110 XEVT1 McBSP1 transmit event 15 000 1111 REVT1 McBSP1 receive event 16 001 0000 TEVTLO1 Timer 1 lower counter event 17 001 0001 TEVTHI1 Timer 1 high counter event 18 43 None 44 010 1100 ICREVT I2C receive event 45 010 1101 ICXEVT I2C transmit event 46 47 None 48 011 0000 GPINTO GPIO event 0 49 011 0001 GPINT1 GPIO event 1 50 011 0010 GPINT2 GPIO event 2 51 011 0011 GPINTS GPIO event 3 52 011 0100 GPINT4 GPIO event 4 53 011 0101 GPINT5 GPIO event 5 54 011 0110 GPINT6 GPIO event 6 55 011 0111 GPINT7 GPIO event 7 56 011 1000 GPINT8 GPIO event 8 57 011 1001 GPINT9 GPIO event 9 1 In addition to the events shown in this table each of the 64 channels can also be synchronized with the transfer completion o
184. d Descriptor Pointer Register 02C8 060C TX3HDP Transmit Channel 3 DMA Head Descriptor Pointer Register 02C8 0610 TX4HDP Transmit Channel 4 DMA Head Descriptor Pointer Register 02C8 0614 TX5HDP Transmit Channel 5 DMA Head Descriptor Pointer Register 02C8 0618 TX6HDP Transmit Channel 6 DMA Head Descriptor Pointer Register 02C8 061C TX7HDP Transmit Channel 7 DMA Head Descriptor Pointer Register 02C8 0620 RXOHDP Receive Channel 0 DMA Head Descriptor Pointer Register 02C8 0624 RX1HDP Receive Channel 1 DMA Head Descriptor Pointer Register 02C8 0628 RX2HDP Receive Channel 2 DMA Head Descriptor Pointer Register 02C8 062C RX3HDP Receive Channel 3 DMA Head Descriptor Pointer Register 02C8 0630 RX4HDP Receive Channel 4 DMA Head Descriptor Pointer Register 02C8 0634 RX5HDP Receive Channel 5 DMA Head Descriptor Pointer Register 02C8 0638 RX6HDP Receive Channel 6 DMA Head Descriptor Pointer Register 02C8 063C RX7HDP Receive Channel 7 DMA Head Descriptor Pointer Register 02C8 0640 TXOCP B Channel 0 Completion Pointer Interrupt Acknowledge 02C8 0644 1 Transmit Channel 1 Completion Pointer Interrupt Acknowledge Register C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 71 Ethernet MAC EMAC Control Registers continued
185. d Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 The L2 memory configuration for the C6454 device is as follows e Port 0 configuration Memory size is 1048KB Starting address is 0080 0000h 2 cycle latency 4 x 128 bit bank configuration Port 1 configuration Memory size is 32K bytes this corresponds to the internal ROM Starting address is 0010 0000h 1 cycle latency 1 x 256 bit bank configuration L2 memory can be configured as all SRAM or as part 4 way set associative cache The amount of L2 memory that is configured as cache is controlled through the L2MODE field of the L2 Configuration Register L2CFG of the C64x Megamodule Figure 5 4 shows the available SRAM cache configurations for L2 By default L2 is configured as all SRAM after device reset L2 mode bits 000 001 010 011 111 L2 memory 3 4 SRAM 792K bytes 7 8 SRAM All 31 32 1916 SRAM SRAM 4 way 128K bytes cache 4 way 64K bytes a 4 way 32K bytes 4 way cache 32K bytes For more information on the operation L1 and L2 caches see the TMS320C64x DSP Cache User s Figure 5 4 TMS320C6454 L2 Memory Configurations Guide literature number SPRU862 All memory on the C6454 has a unique location in the memory map see Table 2 2 C6454 Memory Map Summary When accessing the internal ROM of the DSP the CPU frequency must always be less than 750 MHz
186. d described in Table 7 26 31 16 Reserved R 0 15 5 4 3 2 0 Reserved ALN5 ALN4 Reserved R 0 R 1 R 1 R 1 LEGEND R W Read Write Read only n value after reset Figure 7 18 PLL Controller Clock Align Control Register ALNCTL Hex Address 029A 0140 Table 7 26 PLL Controller Clock Align Control Register ALNCTL Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 433 ALNn SYSCLKn alignment Do not change the default values of these fields 0 Do not align SYSCLKn to other SYSCLKs during GO operation If SYSn in DCHANGE is set to 1 SYSCLKn switches to the new ratio immediately after the GOSET bit in PLLCMD is set 1 Align SYSCLKn to other SYSCLKs selected in ALNCTL when the GOSET bit in PLLCMD is set SYSCLKn ratio is set to the ratio programmed in the RATIO bit in PLLDIVn 2 0 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 134 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback K Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 7 7 3 9 PLLDIV Ratio Change Status Register Whenever a different ratio is written to the PLLDIVn registers the PLLCTRL flags t
187. d has no effect Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 135 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 7 3 10 SYSCLK Status Register The SYSCLK status register SYSTAT shows the status of the system clocks SYSCLKn SYSTAT is shown in Figure 7 20 and described in Table 7 28 31 16 Reserved R 0 15 B Reserved R 0 7 5 4 3 2 1 0 Reserved SYS5ON SYS4ON SYS3ON 5 52 R 0 R 1 R 1 R 1 R 1 R 1 LEGEND R Read only n value after reset Figure 7 20 SYSCLK Status Register SYSTAT Hex Address 029A 0150 Table 7 28 SYSCLK Status Register SYSTAT Field Descriptions Bit Field Value Description 31 4 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 41 SYSnON SYSCLKn on status 0 SYSCLKn is gated 1 SYSCLKn is on 0 Reserved 1 Reserved The reserved bit location is always read as 1 A value written to this field has no effect 136 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 7 4 PLL1 Controller
188. down Register 02C8 001C n Reserved 02C8 0020 02C8 007C Reserved 02C8 0080 TXINTSTATRAW Transmit Interrupt Status Unmasked Register 02C8 0084 TXINTSTATMASKED Transmit Interrupt Status Masked Register 02C8 0088 TXINTMASKSET Transmit Interrupt Mask Set Register 02C8 008C TXINTMASKCLEAR Transmit Interrupt Mask Clear Register 02C8 0090 MACINVECTOR MAC Input Vector Register 02C8 0194 02C8 019C Reserved 02C8 01A0 RXINTSTATRAW Receive Interrupt Status Unmasked Register 01C8 01A4 RXINTSTATMASKED Receive Interrupt Status Masked Register 01C8 01A8 RXINTMASKSET Receive Interrupt Mask Set Register 01C8 01AC RXINTMASKCLEAR Receive Interrupt Mask Clear Register 01C8 01BO MACINTSTATRAW MAC Interrupt Status Unmasked Register 01C8 01B4 MACINTSTATMASKED MAC Interrupt Status Masked Register 01C8 01B8 MACINTMASKSET MAC Interrupt Mask Set Register 01C8 01BC MACINTMASKCLEAR MAC Interrupt Mask Clear Register 02C8 00 0 02C8 00FC Reserved 02 8 0100 RXMBPENABLE Receive Multicast Broadcast Promiscuous Channel Enable Register 02 8 0104 RXUNICASTSET Receive Unicast Enable Set Register 02 8 0108 RXUNICASTCLEAR Receive Unicast Clear Register 02C8 010C RXMAXLEN Receive Maximum Length Register 02 8 0110 RXBUFFEROFFSET Receive Buffer Offset Register 02 8 0114 RXFILTERLOWTHRESH Receive Filter Low Priority Frame Threshold Register 02C8 0118 02C8 011C Reserved 02C8 0120 RXOFLOWTHRESH Receive Channel 0 Flow Control Threshold Register 02C8 0124 RX1FLOWTHRE
189. dress Translation Register 2 Program Register 02C0 03EC PCIBARSTRLPRG PCI Base Address Translation Register 3 Program Register 02 0 03F0 PCIBAR4TRLPRG PCI Base Address Translation Register 4 Program Register 02 0 03F4 PCIBAR5TRLPRG PCI Base Address Translation Register 5 Program Register 02C0 03F8 PCIBASENPRG PCI Base En Prog Register 02 0 03FC 02 0 O3FF Reserved Table 7 101 PCI External Memory Space HEX ADDRESS OFFSET ACRONYM REGISTER NAME 4000 0000 407F FFFF PCI Master Window 0 4080 0000 40FF FFFF PCI Master Window 1 4100 0000 417F FFFF PCI Master Window 2 4180 0000 41FF FFFF PCI Master Window 3 4200 0000 427F FFFF PCI Master Window 4 4280 0000 42FF FFFF PCI Master Window 5 4300 0000 437F FFFF PCI Master Window 6 4380 0000 43FF FFFF PCI Master Window 7 4400 0000 447F FFFF PCI Master Window 8 4480 0000 44FF FFFF PCI Master Window 9 4500 0000 457F FFFF PCI Master Window 10 4580 0000 45FF FFFF PCI Master Window 11 4600 0000 467F FFFF PCI Master Window 12 4680 0000 46FF FFFF PCI Master Window 13 4700 0000 477F FFFF PCI Master Window 14 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 211 PRODUCT PREVIEW Mal aad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A A
190. e EMAC function is controlled MTOLI RMREFGLK Ld by the MACSEL 1 0 AEA 10 9 pins For more detailed information see Section 3 Device Configuration 34 Device Overview Submit Documentation Feedback 4 TEXAS 5320 6454 INSTRUMENTS Fixed Point Digital Signal Processor B SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 2 3 Terminal Functions continued SIGNAL TYPE IPD IPU2 DESCRIPTION NAME NO This pin is the EMAC collision sense MCDL I for MII default or GMII MCOL Voz MACSEL 1 0 dependent This pin is either the EMAC transmit enable MTXEN O for MII default ulis J5 voz RMII or GMII MACSEL 1 0 dependent MTXD7 N5 MTXD6 M3 MTXD5 L5 MTXD4 L3 EMAC transmit data bus for MII default RMII or GMII MTXD3 KA O Z These pins function as EMAC transmit data pins MTXD x 0 O for MII RMII or GMII MACSEL 1 0 dependent MTXD2 M4 MTXD1 RMTXD1 L4 MTXDO RMTXDO M1 ETHERNET MAC EMAC RGMII There are two configuration pins the SEL 1 0 AEA 10 9 pins that select one of the four interface modes MII GMII or RGMII for the EMAC MDIO interface For more detailed information on the EMAC configuration pins see Section 3 Device Configuration RGMII reference clock O This 125 MHz reference clock is provided as a convenience It can be used as a clock source to a PHY so that the PHY may
191. e is in reset POR AF14 Power on reset GP 7 AG2 VO Z IPD GP 6 AG3 VO Z IPD 6 General purpose input output GPIO pins I O Z GP 5 AJ2 VO Z IPD GP 4 AH2 VO Z IPD PREQ GP 15 P2 VO Z PINTA 5 P3 2274 PCI peripheral pins or general purpose input output GPIO 15 12 2 pins PRST GP 13 R5 VO Z 00 2 default PGNT GP 12 R4 10 2 PCI bus request 0 2 or GP 15 0 2 default FSX1 GP 11 AG4 VO Z IPD PCI interrupt 0 2 or GP 14 0 2 default PCI reset 1 or GP 13 1 0 2 default FSR1 GP 10 AES WO Z IPD PCI bus grant I or GP 12 0 2 default DX1 GP 9 AG5 VO Z IPD PCI command byte enable 0 2 or GP 2 I O Z default DR1 GP 8 5 2 IPD McBSP1 transmit clock 0 2 or GP 3 2 default PCBEO GP 2 1 0 2 1 2 SYSCLK4 is the clock output at 1 8 of the device speed O Z SYSCLKA GP 1 O 0 7 IPD or this can be programmed as a GP 1 pin 1 0 2 default CLKR1 GP 0 4 VO Z IPD HOST PORT INTERFACE HPI or PERIPHERAL COMPONENT INTERCONNECT PCI PCI enable pin This pin controls the selection enable disable of the HPI and PCI EN Y29 IPD GP 15 8 or PCI peripherals This pin works in conjunction with the MCBSP1 EN 5 pin to enable disable other peripherals for more details see Section 3 Device Configuration HINT PFRAME U3 VO Z Host interrupt from DSP to host 0 2 or PCI frame 1 2 Host control selects between c
192. e operation the pin must be pulled down to Vss with a 1 kQ resistor at device reset Submit Documentation Feedback Device Overview 29 PRODUCT PREVIEW Mal aad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com Table 2 3 Terminal Functions continued SIGNAL TYPE IPD IPU DESCRIPTION NAME NO EMIFA 64 BIT DATA AED63 F25 AED62 A27 AED61 C27 AED60 C28 AED59 E27 AED58 D28 AED57 D27 AED56 F27 AED55 G25 AED54 G26 AED53 A28 AED52 F28 AED51 B28 AED50 G27 AED49 B27 AED48 G28 AED47 H25 AED46 J26 AED45 H26 AED44 J27 AED43 H27 VO Z IPU EMIFA external data AED42 J28 AED41 C29 AED40 J29 AED39 D29 AED38 J25 AED37 F29 AED36 F26 AED35 G29 AED34 K28 AED33 K25 AED32 K27 AED31 AA27 AED30 AG29 AED29 AB29 AED28 AC27 AED27 AB28 AED26 AC26 AED25 AB27 AED24 AC25 AED23 AB26 AED22 AD28 30 Device Overview Submit Documentation Feedback K Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 Table 2 3 Terminal Functions continued SIGNAL TYPE IPD IPU DESCRIPTION NAME NO AED21 AD2
193. eatures that are supported it should be assumed that any feature not included in these sections is not supported by the C6454 DSP Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 123 PRODUCT PREVIEW MalAddd TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 www ti com 5320 6454 DSP PLLV1 X A B 7 7 1 7 7 1 1 124 PLL1 Controller Le PLLREF 79 PLLOUT 4 PLLEN PLLCTL 0 CLKIN1 8 DIVIDER PREDIV SYSREFCLK IVA V AA 72 I3 SUM C64x MegaModule l 1 15 DIVIDER D2 A x20 x25 30 32 B SYSCLK2 L PREDEN PREDIV 15 DIVIDER DS 16 SYSCLK3 DIVIDER D4 12 14 SYSCLK4 H6 Internal EMIF Clock Input D4EN PLLDIV4 15 ENA DIVIDER D5 A Ho SYSCLK 2 18 5 D5EN PLLDIV4 15 ENA Emulation and Trace Lllcl l lILlllIlllll lI LI I N AECLKIN External EMIF Clock Input 12 CLKDIV CTRL 18 16D o 1 AECLKINSELN 0 syscLKOUT_EN AEA 15 pin AEA 4 pin EMIF Input Clock EMIFA AECLKOUT GP1 SYSCLK4 DIVIDER D2 and DIVIDER D3 are always enabled CLKIN1 is a 3 3 V signal Figure 7 10 PLL1 and PLL1 Controll
194. ection Added DVppismon to paragraph and list Enhanced Direct Memory Access EDMA3 Controller Changed 4 Quick DMA QDMA channels to 8 Quick DMA QDMA channels EDMAS3 Device Specific Information Updated paragraph EDMAS Peripheral Register Description s Changed Table 7 4 title to EDMA3 Channel Controller Registers Updated Hex Address Ranges for Parameter Sets 7 9 254 and 255 on Table 7 5 EDMA3 Parameter RAM Added Table 7 6 EDMA3 Transfer Controller 0 Registers Table 7 7 EDMA3 Transfer Controller 1 Registers Table 7 8 EDMA3 Transfer Controller 2 Registers and Table 7 9 EDMA3 Transfer Controller Registers Interrupt Sources and Interrupt Controller Changed Event Number 80 to Reserved in Table 7 10 C6454 DSP Interrupts Reset Controller Updated System Reset Effect s and added Footnote 2 in Table 7 12 Reset Types Deleted System Reset Timing figure Reset Electrical Data Timing Updated Note Added new Footnote 3 and renumbered Footnotes to 4 and 5 in Table 7 14 Timing Requirements for Reset PLL1 and PLL1 Controller Updated Figure 7 10 PLL1 and PLL1 Controller PLL1 Controller Device Specific Information Updated SYSCLKA bullet Updated paragraphs Updated Footnote 1 in Table 7 16 PLL1 Clock Frequency Ranges Submit Documentation Feedback Revision History 219 PRODUCT PREVIEW M3l aad TMS320C6454 49 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A
195. ectrical Specifications 183 PRODUCT PREVIEW Mal aad S320C6454 49 Texas ed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 64 Timing Requirements for McBSP as SPI Master or Slave CLKSTP 11b CLKXP 047 see Figure 7 55 720 850 NO 1000 UNIT MASTER SLAVE MIN MAX MIN MAX tsu DRV CKXH Setup time DR valid before CLKX high 12 2 18 ns th CKXH DRV Hold time DR valid after CLKX high 4 5 36P ns 1 2 1 CPU clock frequency in ns For example when running parts at 1000 MHz use 1 ns For all SPI Slave modes CLKG is programmed as 1 6 of the CPU clock by setting CLKSM CLKGDV 1 Table 7 65 Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI Master or Slave CLKSTP 11b CLKXP 0 see Figure 7 55 720 850 NO PARAMETER 1000 UNIT MASTER SLAVE MIN MAX MIN MAX 1 n CKXL FXL Hold time FSX low after CLKX low L 2 1 3 ns 2 ta FXL CKXH Delay time FSX low to CLKX high T 2 T 3 ns 3 ta CKXL DXV Delay time CLKX low to DX valid 2 4 18P 2 8 17 ns 6 ldis CKXL DXHZ 2 n Pii folowing 2 4 18P 3 17 ns 7 Delay time FSX low to DX valid H 2 H 4 12P 2 24 17 ns 184 1 CPU clock frequency in ns For example when running parts at 1000 MHz use 1 ns Fo
196. ectrical Specifications Submit Documentation Feedback 249 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 Power Supplies Ramping Power Supplies Stable PCLK UU U UU UU UU UU UU UU U8 k 5 RESETSTAT JN 0 SYSREFCLK PLL1C Win _ SYSCLK4 t ninn _ AECLKOUT Internal Boot and Device 7 Configuration Pins 8 Z Group EE _ Low Group Undefined Low High Group Undefined n CLKIN2 Internal Reset PLL2C Undefined ee SYSREFCLK PLL2C Undefined i X t PLL2 Unlocked X PLL2 Locked A PLL2C Undefined X PLL2 Unlocked X Clock Valid Clock Valid B SYSREFCLK of the PLL2 controller runs at CLKIN2 x10 B SYSCLK1 of PLL2 controller runs at SYSREFCLK 2 default C Power supplies CLKIN1 CLKIN2 if used and PCLK if used must be stable before the start of tw Pon Figure 7 8 Power Up Timing Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 121 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER
197. ed ABAO DDR2 EN 1 DDR2 Memory Controller enabled AEA 19 16 BOOTMODE 3 0 0001 HPI Boot AEA 8 PCI EEAI 0 PCI I2C EEPROM Auto Init disabled default AEA 15 SEL 0 AECLKIN default AEA 7 0 do not oppose IPD AEA 14 WIDTH 1 HPI 32 bit Operation 6 PCI66 0 PCI 33 MHz default don t care AEA 13 LENDIAN IPU Little Endian Mode default AEA 5 MCBSP1 EN 0 McBSP1 disabled default AEA 12 0 do not oppose IPD AEA 4 SYSCLKOUT EN 1 SYSCLKA pin function AEA 11 0 do not oppose IPD 3 0 do not oppose IPD AEA 10 9 MACSEL 1 0 00 10 100 MII Mode AEA 2 0 CFGGP 2 0 000 default Figure 3 12 Configuration Example A McBSP 2 2 EMIFA DDR2 Memory Controller TIMERS EMAC MIl MDIO Submit Documentation Feedback Device Configuration 69 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 32 HD 31 0 HRDY HINT HCNTLO HCNTL1 HHWIL HAS HR W HCS HDS1 HDS2 AED 63 0 AECLKIN AARDY AHOLD AEA 22 3 ACE 3 0 ABE 7 0 AECLKOUT ASDCKE AHOLDA ABUSREQ ASADS ASRE AAOE ASOE GP 15 12 2 1 AAWE ASWE PLLV1 ED 31 0 DEA 21 2 DCE 1 0 DBE 3 0 DDRCLK DDRCLK SYSCLKA Controller DSDCKE DDOS DDQS DSDCAS DSDRAS DSDWE PLL2 CLKR1 FSR1
198. ed and its subsidiaries 1 reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with 5 standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI rega
199. ed event triggering AET Memory protection External memory controller Configuration Registers Data path 2 Data path 1 C64x CPU Slave DMA L1 data memory controller Cache control Bandwidth management Interrupt and exception controller Power control 47 To primary Master DMA Memory protection L1D cache SRAM A When accessing the internal ROM of the DSP the CPU frequency must always be less than 750 MHz Figure 5 1 64x Megamodule Block Diagram For more detailed information on the TMS320C64x Megamodule on the C6454 device see the TMS320C64x Megamodule Reference Guide literature number SPRUS71 5 1 Memory Architecture The TMS320C6454 device contains a 1048KB level 2 memory L2 a 32KB level 1 program memory L1P and a 32KB level 1 data memory L1D The L1P memory configuration for the C6454 device is as follows e Region 0 size is OK bytes disabled e Region 1 size is 32K bytes with no wait states The L1D memory configuration for the C6454 device is as follows e Region 0 size is OK bytes disabled Submit Documentation Feedback C64x Megamodule 77 PRODUCT PREVIEW Mal aad TMS320C6454 49 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 e Region 1 size is 32K bytes with no wait states L1D is a two way set ass
200. efore TXC at DSP high low 1 2 ns h TXCH TXD Hold time transmit selected signals valid after TXC at DSP high low 1 2 1 For RGMII transmit selected signals include TXD 3 0 and TXCTL TXC at DSP pins Internal TXC K 4 at DSP B TXD 3 0 4 23 Data control information is transmitted using both edges of the clocks TXD 3 0 carries data bits 3 0 the rising edge of TXC and data bits 7 4 on the falling edge of TXC Similarly TX_CTL carries TXEN on rising edge of TXC and TXERR of falling edge B TXC is delayed internally before being driven to the TXC pin Figure 7 70 EMAC Transmit Interface Timing RGMII Operation 202 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 7 14 4 Management Data Input Output MDIO The Management Data Input Output MDIO module implements the 802 3 serial management interface to interrogate and controls up to 32 Ethernet PHY s connected to the device using a shared two wire bus Application software uses the MDIO module to configure the auto negotiation parameters of each PHY attached to the EMAC retrieve the negotiation results and configure required parameters in the EMAC module for correct operation The module is designed to allow almost transparent operation of t
201. election HPI and PCI continued CONFIGURATION PIN SETTING PERIPHERAL FUNCTION SELECTED PCI ENPIN AL HPI DATA HPI DATA 32 BIT PCI PCI Y29 UZ7 P25 0 R25 LOWER UPPER 66 33 MHz AUTO INIT Disabled 0 0 u Disapled default values Enabled 33 MHz Enabled 1 0 1 X Disabled via External 2 EEPROM The MAC SEL 1 0 configuration pins AEA 10 9 control which interface is used by the EMAC MDIO Table 3 3 describes the effect of the MACSEL 1 0 configuration pins Table 3 3 MAC SEL 1 0 Peripheral Selection EMAC SEL 1 0 AEA 10 9 PINS M25 M27 CONFIGURATION PIN SETTING EMAC MDIO PERIPHERAL FUNCTION SELECTED 00b 10 100 EMAC MDIO with MII Interface default 01b 10 100 EMAC MDIO with RMII Interface 10b 10 100 1000 EMAC MDIO with GMII Interface 11b 10 100 1000 EMAC MDIO with RGMII Interface 1 RGMII interface requires a 1 5 1 8 V I O supply 3 3 Peripheral Selection After Device Reset On the C6454 device peripherals can be in one of several states These states are listed in Table 3 4 Table 3 4 Peripheral States PERIPHERALS THAT CAN STATE DESCRIPTION BE IN THIS STATE HPI PCI Peripheral pin function has been completely disabled through the device McBSP1 Static powerd n configuration pins Peripheral is held in reset and clock is turned off EMAC MDIO EMIFA DDR2 Memory Controlle
202. entation Feedback C64x Peripheral Information and Electrical Specifications 129 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 7 3 4 PLL Controller Divider 4 Register The PLL controller divider 4 register PLLDIV4 is shown in Figure 7 14 and described in Table 7 22 Besides being used as the EMIFA internal clock SYSCLK4 is also used in other parts of the system Disabling this clock will cause unpredictable system behavior Therefore the PLLDIV4 register should never be used to disable SYSCLK4 31 16 Reserved R 0 15 14 5 4 0 D4EN Reserved RATIO R W 1 R 0 R W 3 LEGEND R W Read Write Read only n value after reset Figure 7 14 PLL Controller Divider 4 Register PLLDIV4 Hex Address 029A 0160 Table 7 22 PLL Controller Divider 4 Register PLLDIV4 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 D4EN Divider 4 enable bit 0 Divider 4 is disabled No clock output 1 Divider 4 is enabled 14 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 4 0 RATIO O 1Fh Divider ratio bits 0 2 Divide frequency by 2 th 4 Divide frequency by 4 2h 6 Divide frequency by
203. er PLL1 Controller Device Specific Information Internal Clocks and Maximum Operating Frequencies As shown in Figure 7 10 the PLL1 controller generates several internal clocks including the system reference clock SYSREFCLK and the system clocks SYSCLK2 3 4 5 The high frequency clock signal SYSREFCLK is directly used to clock the C64x megamodule including the CPU and also serves as a reference clock for the rest of the DSP system Dividers D2 D3 D4 and D5 divide the high frequency clock SYSREFCLK to generate SYSCLK2 SYSCLK3 SYSCLK4 and SYSCLKS5 respectively The system clocks are used to clock different portions of the DSP SYSCLK is used to clock the switched central resources SCRs EDMA3 as well as the data bus interfaces of the EMIFA and DDR2 Memory Controller e SYSCLK3 clocks the PCI HPI McBSP GPIO TIMER and 2 peripherals as well as the configuration bus of the PLL2 Controller C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 e SYSCLK4 is used as the internal clock for the EMIFA It is also used to clock other logic within the DSP e SYSCLKS5 clocks the emulation and trace logic of the DSP The divider ratio bits of dividers D2 and are fixed at 3 and 6 respectively The divider ratio bits of dividers D4 and 54 are program
204. er 02 0 0020 IN DATA GPIO Input Data Register 02 0 0024 SET RIS TRIG GPIO Set Rising Edge Interrupt Register 02 0 0028 CLR RIS TRIG GPIO Clear Rising Edge Interrupt Register 02 0 002C SET FAL TRIG GPIO Set Falling Edge Interrupt Register 02 0 0030 CLR FAL TRIG GPIO Clear Falling Edge Interrupt Register 02 0 008C Reserved 02 0 0090 02 0 00FF Reserved 02 0 0100 02 0 3FFF Reserved 214 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com 7 17 3 GPIO Electrical Data Timing 5320 6454 Table 7 103 Timing Requirements for GPIO Inputs see Figure 7 74 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 720 850 NO 1000 UNIT MIN MAX tw GPIH Pulse duration high 12P ns 2 tw GPIL Pulse duration GPIx low 12P ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 2 The pulse width given is sufficient to generate a CPU interrupt or an EDMA event However if a user wants to have the DSP recognize the GPIx changes through software polling of the GPIO register the GPIx duration must be extended to at least 12P to allow the DSP enough time to access the GPIO register through the CFGBUS Table 7 104 Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs see Figure 7 74
205. er or as two separate 32 bit timers Each timer is made up of two 32 bit counters a high counter and a low counter The timer pins TINPLx and TOUTLx are connected to the low counter The high counter does not have any external device pins 7 15 2 Timers Peripheral Register Description s Table 7 92 Timer 0 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0294 0000 Reserved 0294 0004 EMUMGT_CLKSPDO Management Clock Speed 0294 0008 Reserved 0294 000 Reserved 0294 0010 CNTLOO Timer 0 Counter Register Low 0294 0014 CNTHIO Timer 0 Counter Register High 0294 0018 PRDLOO Timer 0 Period Register Low 0294 001C PRDHIO Timer 0 Period Register High 0294 0020 TCRO Timer 0 Control Register 0294 0024 TGCRO Timer 0 Global Control Register 0294 0028 WDTCRO Timer 0 Watchdog Timer Control Register 0294 002C Reserved 0294 0030 Reserved 0294 0034 0297 FFFF Reserved Table 7 93 Timer 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS 0298 0000 Reserved 0298 0004 EMUMGT_CLKSPD1 Timer 1 Emulation Management Clock Speed Register 0298 0008 Reserved 0298 000C Reserved 0298 0010 CNTLO1 Timer 1 Counter Register Low 0298 0014 CNTHI1 Timer 1 Counter Register High 0298 0018 PRDLO1 Timer 1 Period Register Low 0298 001 PRDHI1 Timer 1 Period Register High 0298 0020 TCR1 Timer 1 Control Register 0298 0024 TGCR1 Timer 1
206. eserved 02A3 8380 DFOPT2 Destination FIFO Options Register 2 02A3 8384 DFSRC2 Destination FIFO Source Address Register 2 02A3 8388 DFCNT2 Destination FIFO Count Register 2 02A3 838C DFDST2 Destination FIFO Destination Address Register 2 02A3 8390 DFBIDX2 Destination FIFO BIDX Register 2 110 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 9 EDMA3 Transfer Controller 3 Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A3 8394 DFMPPRXY2 Destination FIFO Memory Protection Proxy Register 2 02A3 8398 02A3 83BC Reserved 02A3 83 0 DFOPT3 Destination FIFO Options Register 3 02A3 83C4 DFSRC3 Destination FIFO Source Address Register 3 02A3 83C8 DFCNT3 Destination FIFO Count Register 3 02A3 83CC DFDST3 Destination FIFO Destination Address Register 3 02A3 83D0 DFBIDX3 Destination FIFO BIDX Register 3 02A3 83D4 DFMPPRXY3 _ Destination FIFO Memory Protection Proxy Register 3 02A3 83D8 02A3 FFFF Reserved Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 111 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 5 Interrupts
207. etting of the Megamodule either both globally or just locally Table 5 2 Megamodule Reset Global or Local GLOBAL LOCAL RESET TYPE MEGAMODULE MEGAMODULE RESET RESET Power On Reset Y Y Warm Reset Y Y System Reset Y Y CPU Reset N Y For more detailed information on the global and local Megamodule resets see the TMS320C64x Megamodule Reference Guide literature number SPRU871 And for more detailed information on device resets see Section 7 6 Reset Controller Submit Documentation Feedback C64x Megamodule 81 PRODUCT PREVIEW Mal aad Lo9naoad TMS320C6454 49 Texas Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 5 6 Megamodule Revision 31 The version and revision of the C64x Megamodule can be read from the Megamodule Revision ID Register MM_REVID located at address 0181 2000h The MM_REVID register is shown in Figure 5 5 and described in Table 5 3 The C64x Megamodule revision is dependant on the silicon revision being used For more information see the TMS320C6455 54 Digital Signal Processor Silicon Errata literature number SPRZ234 16 15 0 VERSION REVISION R 1h R n LEGEND R Read only n value after reset A The C64x Megamodule revision is dependant on the silicon revision being used For more information see the 5320 6455 54 Digital Signal Processor Silicon Errata literature n
208. evice Reset Once in a static power down state the peripheral is held in reset and its clock is turned off Peripherals cannot be enabled once they are in a static power down state To take a peripheral out of the static power down state a device reset must be executed with a different configuration pin setting After device reset all peripherals on the C6454 device are in a disabled state and must be enabled by software before being used It is possible to enable only the peripherals needed by the application while keeping the rest disabled Note that peripherals in a disabled state are held in reset with their clocks gated For more information on how to enable peripherals see Section 3 3 Peripheral Selection After Device Reset C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com 7 3 4 SPRS311A APRIL 2006 REVISED DECEMBER 2006 Peripherals used for booting like I2C and HPI are automatically enabled after device reset It is not possible to disable these peripherals after the boot process is complete The C64x Megamodule also allows for software driven power down management for all of the C64x megamodule components through its Power Down Controller PDC The CPU can power down part or the entire C64x megamodule through the power down controller based on its own execution thread or in response to an external s
209. evice operation NOTE If the DDR2 Memory Controller is not used the Vrersst_ RSV11 and RSV11 D24 RSV12 pins can be connected directly to ground Vss to save power However connecting these pins directly to ground will prevent boundary scan from functioning on the DDR2 Memory Controller pins To preserve boundary scan functionality on the DDR2 Memory Controller pins see Section 7 3 4 Submit Documentation Feedback Device Overview 35 PRODUCT PREVIEW Mal aad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com Table 2 3 Terminal Functions continued SIGNAL NAME NO TYPE IPD IPU 2 DESCRIPTION RSV12 C24 Reserved This pin must be connected to the 1 8 V I O supply DVppig via a 200 0 resistor for proper device operation NOTE If the DDR2 Memory Controller is not used the Vaersst_ RSV11 and RSV12 pins can be connected directly to ground Vss to save power However connecting these pins directly to ground will prevent boundary scan from functioning on the DDR2 Memory Controller pins To preserve boundary scan functionality on the DDR2 Memory Controller pins see Section 7 3 4 RSV13 F2 Reserved This pin must be connected to ground Vss via a 200 Q resistor for proper device operation NOTE If the RGMII mode of the EMAC is not used the DVppis VREFHSTL RSV13 a
210. ew 3 10 MAX lle x Le 0 12 4206099 2 01 06 NOTES All linear dimensions are in millimeters B This drawing is subject to change without notice C Thermally enhanced plastic package with heat slug HSL D Flip chip application only 35 TEXAS INSTRUMENTS www ti com MECHANICAL DATA ZTZ 5 697 PLASTIC BALL GRID ARRAY 22 40 TYP DOOOOOOOOOO OOOOOOOOO0O0000000000000 1 Corner 2 HEAT SLUG 11 11 13 15 17 19 21 252 10 12 14 16 18 2022 24 Bottom View Seating Plane x Lam 4206100 2 C 01 06 NOTES All linear dimensions are in millimeters B This drawing is subject to change without notice C Thermally enhanced plastic package with heat slug HSL D Flip chip application only E This is a lead free solder ball design 3 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporat
211. except PCI capable and 08 V I2C pins PCI capable pins 0 5 0 3 V Low level input voltage 12 pins 0 0 3DVpp33 V RGMII pins 0 3 VREFHSTL 0 1 V DDR2 memory controller pins 0 3 VrersstL 0 125 V DC Operating case temperature 0 90 Submit Documentation Feedback Device Operating Conditions 91 PRODUCT PREVIEW Mal aad TMS32006454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com 6 3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature Unless Otherwise Noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3 3 V pins except _ PCl capable and I2C MIN 0 8DVppas OH High level PCI capable pins KOH 0 MA 0 9DV V Von output voltage dd DVppas 3 3 V ES RGMII pins DVpp15 0 4 V DDR2 memory controller pins 0 28 3 3 V pins except _ PCl capable and I2C P Vppas MIN 0 22DVppss V pins OL PCl capable pins 2 2 bibe V 0 1DVppss V VoL Low level output DD33 9 voltage Pulled up to 3 3 V 3 mA sink 2 pins 0 4 V RGMII pins 0 4 V DDR2 memory controller pins 0 28 Vi Vss to pins without internal pullup or 1 1 uA 3 3 V pins except pulldown resistor PCl capable and 12C Vi Vss to DVppss pins
212. f the on chip bootloader The bootloader is DSP code that transfers application code from an external source into internal or external program memory after the DSP is taken out of reset The bootloader is permanently stored in the internal ROM of the DSP starting at byte address 0010 0000h Hardware boot modes are carried out by the boot configuration logic The boot configuration logic is actual hardware that does not require the execution of DSP code Section 2 4 1 Boot Modes Supported describes each boot mode in more detail When accessing the internal ROM of the DSP the CPU frequency must always be less than 750 MHz Therefore when using a software boot mode care must be taken such that the CPU frequency does not exceed 750 MHz at any point during the boot sequence After the boot sequence has completed the CPU frequency can be programmed to the frequency required by the application Boot Modes Supported The C6454 has six boot modes e No boot BOOTMODE 3 0 0000b With no boot the CPU executes directly from the internal L2 SRAM located at address 0x80 0000 Note device operations is undefined if invalid code is located at address 0x80 0000 This boot mode is a hardware boot mode e Host boot BOOTMODE 3 0 0001b and BOOTMODE 3 0 01110 If host boot is selected after reset the CPU is internally stalled while the remainder of the device is released During this period an external host can initialize the CPU s memory space a
213. gisters are not reset In addition the DDR2 SDRAM memory content is retained if the user places the DDR2 SDRAM in self refresh mode before invoking the System Reset The contents of the memory connected to the EMIFA are retained The EMIFA registers are not reset Test emulation and clock logic are unaffected The device configuration pins are also not re latched and the state of the peripherals see Table 3 4 is not affected During a System Reset the following happens 1 The System Reset is initiated by the emulator During this time the following happens The reset signals flow to the entire chip resetting all the modules on chip except the test and emulation logic The PLL controllers are not reset Internal system clocks are unaffected If PLL1 PLL2 were locked before the System Reset they remain locked The RESETSTAT pin goes low to indicate an internal reset is being generated 2 After device initialization is complete the RESETSTAT pin is deasserted driven high In addition the PLL controllers pause their system clocks for about 10 cycles At this point The state of the peripherals before the System Reset is not changed For example if McBSPO was in the enabled state before System Reset it will remain in the enabled state after System Reset The I O pins are controlled as dictated by the DEVSTAT register The DDR2 Memory Controller and EMIFA registers retain their previous values On
214. he MDIO interface with very little maintenance from the core processor The EMAC control module is the main interface between the device core processor the MDIO module and the EMAC module The relationship between these three components is shown in Figure 7 58 The MDIO uses the same pins for the MII GMII and RMII modes Standalone pins are included for the RGMII mode due to specific voltage requirements Only one mode can be used at a time The mode used is selected at device reset based on the MACSEL 1 0 configuration pins for more detailed information see Section 3 Device Configuration Table 7 70 above shows which multiplexed pin are used in the MII GMII and RMII modes on the MDIO For more detailed information on the EMAC MDIO see the TMS320C645x DSP EMAC MDIO Module Reference Guide literature number SPRU975 7 14 4 4 Device Specific Information Clocking Information The MDIO clock is based on a divide down of the SYSCLK3 from the PLL1 controller and is specified to run up to 2 5 MHz although typical operation is 1 0 MHz Since the peripheral clock frequency is variable the application software or driver controls the divide down amount 7 14 4 2 MDIO Peripheral Register Description s Table 7 89 MDIO Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02C8 1800 VERSION MDIO Version Register 02C8 1804 CONTROL MDIO Control Register 02C8 1808 ALIVE MDIO PHY Alive S
215. he change in the PLLDIV ratio change status registers DCHANGE During the GO operation the PLL controller will only change the divide ratio of the SYSCLKs with the bit set in DCHANGE Note that changed clocks will be automatically aligned to other clocks The PLLDIV divider ratio change status register is shown in Figure 7 19 and described in Table 7 27 31 16 Reserved R 0 15 5 4 3 2 0 Reserved SYS5 SYS4 Reserved R 0 R 0 R 0 R 0 LEGEND R W Read Write Read only n value after reset Figure 7 19 PLLDIV Divider Ratio Change Status Register DCHANGE Hex Address 029A 0144 Table 7 27 PLLDIV Divider Ratio Change Status Register DCHANGE Field Descriptions Bit Field Value Description 31 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 4 SYS5 Identifies when the SYSCLKS5 divide ratio has been modified 0 5 5 5 ratio has not been modified When GOSET is set SYSCLK5 will not be affected SYSCLK5 ratio has been modified When GOSET is set SYSCLK5 will change to the new ratio 3 SYS4 Identifies when the SYSCLK4 divide ratio has been modified 0 SYSCLK4 ratio has not been modified When GOSET is set SYSCLK4 will not be affected SYSCLK4 ratio has been modified When GOSET is set SYSCLK4 will change to the new ratio 2 0 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this fiel
216. hould be above the highest level of all inputs on the net A reasonable choice would be to target the Vo or Voy levels for the logic family of the limiting device which by definition have margin to the Vi and Vj levels e Select a pullup pulldown resistor with the largest possible value but which can still ensure that the net will reach the target pulled value when maximum current from all devices on the net is flowing through the resistor The current to be considered includes leakage current plus any other internal and external pullup pulldown resistors on the net e For bidirectional nets there is an additional consideration which sets a lower limit on the resistance value of the external resistor Verify that the resistance is small enough that the weakest output buffer can drive the net to the opposite logic level including margin e Remember to include tolerances when selecting the resistor value For pullup resistors also remember to include tolerances on the DV rail For most systems a 1 resistor be used to oppose the IPU IPD while meeting the above criteria Users should confirm this resistor value is correct for their specific application For most systems a 20 kO resistor can be used to compliment the IPU IPD on the device configuration pins while meeting the above criteria Users should confirm this resistor value is correct for their specific application For more detailed information on input curren
217. i com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 7 16 Peripheral Component Interconnect PCI The C6454 DSP supports connections to a PCI backplane via the integrated PCI master slave bus interface The PCI port interfaces to DSP internal resources via the data switched central resource The data switched central resource is described in more detail in Section 4 For more detailed information on the PCI port peripheral module see the TMS320C645x DSP Peripheral Component Interconnect PCI User s Guide literature number SPRUE60 7 16 1 PCI Device Specific Information The PCI peripheral on the C6454 DSP conforms to the PCI Local Bus Specification version 2 3 The PCI peripheral can act both as a PCI bus master and as a target It supports PCI bus operation of speeds up to 66 MHz and uses a 32 bit data address bus On the C6454 device the pins of the PCI peripheral are multiplexed with the pins of the and GPIO peripherals PCI functionality for these pins is controlled enabled disabled by the PCI EN pin Y29 The maximum speed of the PCI 33 MHz or 66 MHz is controlled through the PCI66 pin U27 For more detailed information on the peripheral control see Section 3 Device Configuration The C6454 device provides an initialization mechanism through which the default values for some of the PCI configuration registers can be read from an I2C EEPROM Table 7 96 shows the registers which can be initialized through the PCI auto i
218. ical Layer specifications The IEEE 802 3 standard has also been adopted by ISO IEC and re designated as ISO IEC 8802 3 2000 E Deviation from this standard the EMAC module does not use the Transmit Coding Error signal MTXER Instead of driving the error pin when an underflow condition occurs on a transmitted frame the EMAC will intentionally generate an incorrect checksum by inverting the frame CRC so that the transmitted frame will be detected as an error by the network The EMAC control module is the main interface between the device core processor the MDIO module and the EMAC module The relationship between these three components is shown in Figure 7 58 The EMAC control module contains the necessary components to allow the EMAC to make efficient use of device memory plus it controls device interrupts The EMAC control module incorporates 8K bytes of internal RAM to hold EMAC buffer descriptors The relationship between these three components is shown in Figure 7 58 Interrupt Configuration Bus u Peripheral Bus nterrupt MDIO Module p EMAC Control Module EMAC MDIO EMAC Module Ethernet Bus MDIO Bus Figure 7 58 EMAC MDIO and EMAC Control Modules For more detailed information on the EMAC MDIO see the TMS320C645x DSP EMAC MDIO Module Reference Guide literature number SPRU975 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 187 PRODU
219. ice Reset 2 Once all the power supplies are within valid operating conditions the POR pin must remain asserted low for a minimum of 256 CLKIN2 cycles The PLL1 controller input clock CLKIN1 and the PCI input clock PCLK must also be valid during this time PCLK is only needed if the PCI module is being used If the DDR2 memory controller and the EMAC peripheral are not needed CLKIN2 can be tied low and in this case the POR pin must remain asserted low for a minimum of 256 CLKIN1 cycles after all power supplies have reached valid operating conditions Within the low period of the POR pin the following happens The reset signals flow to the entire chip including the test and emulation logic resetting modules that use reset asynchronously The PLL1 controller clocks are started at the frequency of the system reference clock The clocks are propagated throughout the chip to reset modules that use reset synchronously By default PLL1 is in reset and unlocked The PLL2 controller clocks are started at the frequency of the system reference clock PLL2 is held in reset Since the PLL2 controller always operates in PLL mode the system reference clock and 116 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback K Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 all the system clocks are invalid at this point
220. ice Overview Submit Documentation Feedback 4 TEXAS 5320 6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 16 17 18 19 20 21 22 23 24 25 26 27 28 29 AJ Vss RSV77 RSV56 RSV60 Vss RSV61 RSV57 RSV78 Vss DVDp33 AED5 AED6 AED20 DVppas AJ DVppss RSV59 RSV55 Vss RSV76 Vss RSV58 RSV62 DVpp33 Vss AED14 AED2 AED18 Vss AH AG Vss DVpp33 RSV48 RSV52 Vss RSV53 RSV49 DVpp33 Vss AED3 SCL AED9 AED16 AED30 AG AF DVppss RSV47 RSV51 Vss RSV75 Vss RSV54 RSV50 DVpp33 AED1 SDA AED10 AED15 AEDi9 AE Vss RSV72 Vss RSV73 Vss RSV17 Vss RSV74 Vss AED7 AED12 AED4 AED13 17 AE AD RSV66 Vss DVppas Vss RSV63 Vss DVpp33 Vss DVpp33 AED0 AED11 AED8 AED22 AED21 AD AC Vss RSV65 Vss DVppas Vss DVpps3 Vss DVpps3 Vss AED24 AED26 AED28 Vss Vss DVppss AED25 AED27 AED29 ASWE AA DVpp33 Vss ABE1 ABE0 AED31 ABE2 ABE3 AA AAOE Y V DV EN Y 55 DD33 RSV43 RSV42 RSV44 ASGE E W RSV7O Vss RSV71 Vss DVpp33 Vss ARW 2 RSV41 ABE7 W 1 V V RSV69 V 5 ACE4 AECLKOUT V 55 ss ss 0083 EMIFA_EN DDR2_EN AEA5 AEA0 AEA1 AEA6 U RSV67 V V DV V Rsv20 U i i gt pos 58 CFGGPO 1 66 in
221. iled information on device configuration peripheral selection multiplexed shared pins and pullup pulldown resistors see Section 3 Device Configuration Table 2 3 Terminal Functions SIGNAL TYPE IPD IPU DESCRIPTION NAME NO CLOCK PLL CONFIGURATIONS CLKIN1 N28 IPD Clock Input for PLL1 CLKIN2 G3 IPD Clock Input for PLL2 PLLV1 T29 A 1 8 V I O supply voltage for PLL1 PLLV2 5 1 8 V I O supply voltage for PLL2 SYSCLK4 GP 1 AJ13 Volz IPD 4 21 pra speed O Z or this pin can be JTAG EMULATION TMS AJ10 JTAG test port mode select TDO AH8 O Z IPU JTAG test port data out TDI AH9 test port data AJ9 test port clock ar 1 eo EMUO 4 AF7 VO Z IPU Emulation pin 0 EMU1 4 AE11 VO Z IPU Emulation pin 1 EMU2 9 VO Z IPU Emulation pin 2 EMU3 10 VO Z IPU Emulation pin 3 EMU4 AF9 VO Z IPU Emulation pin 4 EMU5 AE12 VO Z IPU Emulation pin 5 EMU6 AG8 VO Z IPU Emulation pin 6 EMU7 AF12 VO Z IPU Emulation pin 7 EMU8 AF11 VO Z IPU Emulation pin 8 EMU9 AH13 VO Z IPU Emulation pin 9 EMU10 AD10 VO Z IPU Emulation pin 10 EMU11 AD12 VO Z IPU Emulation pin 11 EMU12 AE10 VO Z IPU Emulation pin 12 EMU13 AD8 VO Z IPU Emulation pin 13 EMU14 AF13 VO Z IPU Emulation pin 14 EMU15 9 VO Z IPU Emulation pin 15 EMU16 AH12 VO Z IPU Emulation pin 16 EMU1
222. ill prevent F5 boundary scan from functioning on the RGMII pins of the EMAC To preserve G6 boundary scan functionality on the RGMII pins see Section 7 3 4 H7 B8 B11 B20 B23 E10 E12 E22 E24 F7 F11 F13 F15 E S 1 8 V I O supply voltage DDR2 Memory Controller F19 F23 G8 G10 912 914 916 G18 G20 G22 G24 Submit Documentation Feedback Device Overview 39 PRODUCT PREVIEW Mal aad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com Table 2 3 Terminal Functions continued SIGNAL NAME NO TYPE IPD IPU 2 DESCRIPTION DVppas A29 E26 E28 G2 H23 H28 J6 J24 K1 K7 K23 L24 M7 M23 M28 N24 P6 P28 R1 R6 R23 T7 T24 U23 V1 V7 V24 W23 Y7 Y24 AAI AA6 AA23 AB7 AB24 AC6 9 11 1 19 21 23 29 3 3 V I O supply voltage 40 Device Overview Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 2 3 Terminal Functions continued SIGNAL NAME NO TYPE IPD
223. ine 400 400 pF e 1 Dus I2C pins SDA and SCL do not feature fail safe buffers These pins could potentially draw current when the device is powered O 2 device can be used a Standard mode 1 C bus system but the requirement tsu SDA SCLH 2 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line t max tsuspa scLH 1000 250 1250 ns according to the Standard mode 2 Specification before the SCL line is released 3 device must internally provide a hold time of at least 300 ns for the SDA signal referred to the Viymin of the SCL signal to bridge the undefined region of the falling edge of SCL 4 The maximum tyspa scLL has only to be met if the device does not stretch the low period of the SCL signal total capacitance of one bus line in pF If mixed with HS mode devices faster fall times are allowed Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 163 TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 ii l 11 9 0 k Mal aad L1 em 1 AT
224. ing HAS Used 170 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 6 INSTRUMENTS www ti com o HAS HCNTL 1 0 HR W HHWIL HSTROBE A HD 15 0 4 35 TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 gt 18 17 Me 5 He mowa Ll 7 ANS N A xc HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 XOR HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed information on the HPI peripheral see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 Figure 7 46 HPI16 Write Timing HAS Not Used Tied High Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 171 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 12 K 12 le L 11 11 46 XXX 37 gt lt 14 7 1 4 woso PZ A HSTROBE refers to the following logical operation HCS HDS1 and HDS2 NOT HDS1
225. interrupt 60 GPINT9 GPIO interrupt 61 GPINT10 GPIO interrupt 62 GPINT11 GPIO interrupt 63 GPINT12 GPIO interrupt 64 GPINT13 GPIO interrupt 65 GPINT14 GPIO interrupt 66 GPINT15 GPIO interrupt 67 TINTLOO Timer O lower counter interrupt 68 TINTHIO Timer 0 higher counter interrupt 69 1 Timer 1 lower counter interrupt 70 TINTHI1 Timer 1 higher counter interrupt 71 EDMAS3CO INTO completion interrupt 72 EDMA3CC_INT1 completion interrupt Mask1 73 EDMA3CC_INT2 EDMASCC completion interrupt Mask2 74 EDMA3CC_INT3 completion interrupt Mask3 75 EDMA3CC_INT4 completion interrupt Mask4 76 EDMA3CC_INT5 completion interrupt Mask5 77 EDMA3CC_INT6 completion interrupt Mask6 78 EDMA3CC_INT7 EDMASCC completion interrupt Mask7 79 EDMA3CC_ERRINT EDMASCC error interrupt 80 Reserved Reserved Do not use 81 EDMA3TCO_ERRINT error interrupt 82 EDMA3TC1_ERRINT EDMASTC1 error interrupt 83 EDMA3TC2_ERRINT 2 error interrupt 84 EDMA3TC3_ERRINT error interrupt 85 Reserved Reserved Do not use 86 95 Reserved Reserved Do not use 96 INTERR Interrupt Controller dropped CPU interrupt event 97 EMC_IDMAERR EMC invalid IDMA parameters 98 Reserved Reserved Do not use 99 Reserved Reserved Do not use 100 EFIINTA EFI interrupt from side A 101 EFIINTB EFI interrupt from side B 102 111 Reserved Reserved
226. ion see Figure 7 69 720 850 NO 1000 UNIT MIN MAX 10 Mbps 360 440 1 te RXC Cycle time RXC 100 Mbps 36 44 ns 1000 Mbps 7 2 8 8 10 Mbps 0 40 tyRxc 0 60 2 tw RXCH Pulse duration RXC high 100 Mbps 0 40 tyAxcy 0 60 tc xc ns 1000 Mbps 0 45 0 55 10 Mbps 0 40 0 60 3 tw RXCL Pulse duration RXC low 100 Mbps 0 40 tyRxc 0 60 ns 1000 Mbps 0 45 tyRxc 0 55 10 Mbps 0 75 4 Transition time RXC 100 Mbps 0 75 ns 1000 Mbps 0 75 200 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 Table 7 86 Timing Requirements for EMAC RGMII Input Receive for 10 100 1000 Mbps see Figure 7 69 720 850 NO 1000 UNIT MIN MAX tsu RXD RXCH Setup time receive selected signals valid before RXC at DSP high low 1 0 ns h RXCH RXD Hold time receive selected signals valid after RXC at DSP high low 1 0 ns 1 For RGMII receive selected signals include RXD 3 0 and RXCTL i 1 5 9 4 5 4 RXC at DSP B 4 5 1st Half byte 2nd Half byte 6 gt A Data and control information is received using both edges of the clocks RXD 3 0 carries data bits 3 0 on the rising edge of RXC and data bits 7 4 on
227. ion Feedback 4 TEXAS 5320 6454 INSTRUMENTS Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 2 3 Terminal Functions continued SIGNAL TYPE IPD IPU DESCRIPTION NAME NO DDR2 MEMORY CONTROLLER 32 BIT DATA DED31 B25 DED30 A25 DED29 B24 DED28 A24 DED27 D22 DED26 C22 DED25 B22 DED24 A22 DED23 D21 DED22 C21 DED21 B21 DED20 A21 DED19 D19 DED18 C19 DED17 A19 DED16 B19 VO Z DDR2 Memory Controller external data DED15 C7 DED14 D7 DED13 A7 DED12 B7 DED11 F9 DED10 E9 DED9 D9 DED8 C9 DED7 D10 DED6 C10 DED5 B10 DED4 A10 DED3 D12 DED2 C12 DED1 B12 DEDO A12 TIMER 1 TOUTL1 AG7 O Z IPD Timer 1 output pin for lower 32 bit counter TINPL1 AJ6 IPD Timer 1 input pin for lower 32 bit counter TIMER 0 TOUTLO AF8 O Z IPD Timer 0 output pin for lower 32 bit counter TINPLO AH6 IPD Timer 0 input pin for lower 32 bit counter INTER INTEGRATED CIRCUIT 2 SCL AG26 VO Z 2 clock When the 2 module is used use an external pullup resistor SDA AF26 VO Z 12 data When 2 is used ensure there is an external pullup resistor Submit Documentation Feedback Device Overview 33 PRODUCT PREVIEW Mal aad L9naoasd TMS32006454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006
228. irectly to ground will prevent boundary scan from functioning on the DDR2 Memory Controller pins To preserve boundary scan functionality on the DDR2 Memory Controller pins see Section 7 3 4 38 Device Overview Submit Documentation Feedback Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 Table 2 3 Terminal Functions continued SIGNAL TYPE IPD IPU DESCRIPTION NAME NO DVppis 2 V reference for HSTL buffer EMAC RGMII can be generated directly from DVpp15 using two 1 kQ resistors to form a resistor divider circuit B2 A NOTE If the RGMII mode of the EMAC is not used the DVppis VREFHSTL REFPISTE RSV13 and RSV14 pins can be connected to directly ground Vas to save power However connecting these pins directly to ground will prevent boundary scan from functioning on the RGMII pins of the EMAC To preserve boundary scan functionality on the RGMII pins see Section 7 3 4 13 1 8 V I O supply voltage AVpLL2 E18 A1 Be 1 8 V or 1 5 V I O supply voltage for the RGMII function of the EMAC D2 NOTE If the RGMII mode of the EMAC is not used the 15 VREFHSTL RSV13 and RSV14 pins can be connected to directly ground Vss to save power However connecting these pins directly to ground w
229. is set in software through the PLL1 controller registers after device reset The PLL2 multiply factor is fixed For more information see Section 7 7 PLL1 and PLL1 Controller and Section 7 8 PLL2 and PLL2 Controller On the C6454 device the PCI peripheral pins are multiplexed with the pins The PCI EN pin selects the function for the HPI PCI multiplexed pins The PCl66 PCI EEAI and HPI WIDTH control other functions of the PCI and HPI peripherals Table 3 2 describes the effect of the PCI EN 66 PCI EEAI and HPI WIDTH configuration pins Table 3 2 PCI EN PCI66 PCI EEAI and HPI WIDTH Peripheral Selection HPI and PCI CONFIGURATION PIN SETTING PERIPHERAL FUNCTION SELECTED PCI ENPIN AL CN RERS PN NEA PI HPI DATA HPI DATA 32 BIT PCI PCI Y29 U27 P25 R25 LOWER UPPER 66 33 MHz AUTO INIT 0 0 0 0 Enabled Hi Z Disabled N A 0 0 0 1 Enabled Enabled Disabled N A Enabled 1 1 1 X Disabled Enabled via External l2C 66 MHz EEPROM 1 1 0 X Disabled Disabled 1 PCI EEAI is latched at reset as a configuration input If PCI EEAI is set as one then default values are loaded from an external 2 EEPROM 52 Device Configuration Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com 5320 6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 3 2 PCI 66 PCI EEAI and HPI WIDTH Peripheral S
230. ite to complete before signaling an interrupt to the system thus avoiding this race condition For masters that do not have hardware guarantee of write read ordering it may be necessary to guarantee data ordering via software If master A does not wait for indication that a write is complete it must perform the following workaround 1 Perform the required write 2 Perform a dummy write to the EMIFA module ID and revision register 3 Perform a dummy read to the EMIFA module ID and revision register 4 Indicate to master B that the data is ready to be read after completion of the read in step 3 The completion of the read in step 3 ensures that the previous write was done Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 149 PRODUCT PREVIEW Mal aad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 10 2 EMIFA Peripheral Register Description s 6 INSTRUMENTS www ti com Table 7 41 EMIFA Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 7000 0000 MIDR Module ID and Revision Register 7000 0004 STAT Status Register 7000 0008 Reserved 7000 000 7000 001C Reserved 7000 0020 BURST PRIO Burst Priority Register 7000 0024 7000 004C Reserved 7000 0050 7000 007C Reserved 7000 0080 CE2CFG EMIFA CE2 Configuration Register 7000 0084 CE3CFG EM
231. ites of 1 can initiate the GO operation 132 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 7 7 3 7 PLL Controller Status Register The PLL controller status register PLLSTAT shows the PLL controller status PLLSTAT is shown in Figure 7 17 and described in Table 7 25 31 16 R 0 15 1 0 R 0 R 0 LEGEND R W Read Write Read only n value after reset Figure 7 17 PLL Controller Status Register PLLSTAT Hex Address 029A 013C Table 7 25 PLL Controller Status Register PLLSTAT Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 GOSTAT GO operation status 0 GO operation is not in progress SYSCLK divide ratios are not being changed 1 GO operation is in progress SYSCLK divide ratios are being changed Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 133 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 7 38 PLL Controller Clock Align Control Register The PLL controller clock align control register ALNCTL is shown in Figure 7 18 an
232. ive Channel 7 Free Buffer Count Register 02C8 0160 MACCONTROL MAC Control Register 02C8 0164 MACSTATUS MAC Status Register 02C8 0168 EMCONTROL Emulation Control Register 02C8 016C FIFOCONTROL FIFO Control Register Transmit and Receive 02C8 0170 MACCONFIG MAC Configuration Register 02C8 0174 SOFTRESET Soft Reset Register 02C8 0178 02C8 01CC Reserved 02C8 01DO MACSRCADDRLO MAC Source Address Low Bytes Register Lower 32 bits 02C8 01D4 MACSRCADDRHI MAC Source Address High Bytes Register Upper 32 bits 02C8 01D8 MACHASH1 MAC Hash Address Register 1 02C8 01DC MACHASH2 MAC Hash Address Register 2 02 8 01 0 5 Back Test Register 02C8 01E4 TPACETEST Transmit Pacing Algorithm Test Register 02C8 01E8 RXPAUSE Receive Pause Timer Register 02C8 01EC TXPAUSE Transmit Pause Timer Register 02C8 01 0 02C8 01FC Reserved 02C8 0200 02C8 02FC see Table 7 72 EMAC Statistics Registers 02C8 0300 02C8 03FC Reserved 02C8 0400 02C8 04FC Reserved MAC Address Low Bytes Register used in receive address 02C8 0500 MACADDRLO matching 02 8 0504 MACADDRHI 7 High Bytes Register used receive address 02C8 0508 MACINDEX MAC Index Register 02C8 050C 02C8 05FC Reserved 02C8 0600 TXOHDP Transmit Channel 0 DMA Head Descriptor Pointer Register 02C8 0604 TX1HDP Transmit Channel 1 DMA Head Descriptor Pointer Register 02C8 0608 TX2HDP Transmit Channel 2 DMA Hea
233. l Status Register 0 PERSTATO Field Descriptions Bit Field Value Description 31 30 Reserved Reserved 29 27 HPISTAT status 000 HPI is in the disabled state 001 is in the enabled state 011 is in the static powerdown state 101 is in the enable in progress state Others Reserved 26 24 McBSP1STAT McBSP 1 status 000 is in the disabled state 001 McBSP1 is in the enabled state 011 McBSP1 is in the static powerdown state 101 McBSP1 is in the enable in progress state Others Reserved 23 21 McBSPOSTAT McBSPO status 000 McBSPO is in the disabled state 001 McBSPO is in the enabled state 011 McBSPO is in the static powerdown state 101 McBSPO is in the enable in progress state Others Reserved 20 18 I2CSTAT 12C status 000 2 is in the disabled state 001 12 is in the enabled state 011 12 is in the static powerdown state 101 12 is in the enable in progress state Others Reserved 60 Device Configuration Submit Documentation Feedback Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 3 9 Peripheral Status Register 0 PERSTATO Field Descriptions continued Bit Field Value Description 17 15 GPIOSTAT GPIO status 000 GPIO is in the disabled state 001 GPIO is in the enabled state 011 GPIO is in the static powerdown state 101 GPIO is in the en
234. le 3 6 Peripheral Lock Register PERLOCK Field Descriptions Bit Field Value Description 31 0 LOCKVAL When programmed with OxOFOA 0 00 allows one write to the PERCFGO register within 16 SYSCLK3 clock cycles 56 Device Configuration Submit Documentation Feedback K Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor SPRS311A APRIL 2006 C REVISED DECEMBER 2006 3 4 2 Peripheral Configuration Register 0 Description The Peripheral Configuration Register PERCFGO is used to change the state of the peripherals One write is allowed to this register within 16 SYSCLKS cycles after the correct key is written to the PERLOCK register NOTE The instructions that write to the PERLOCK and PERCFGO registers must be in the same fetch packet if code is being executed from external memory If the instructions are in different fetch packets fetching the second instruction from external memory may stall the instruction long enough such that PERCFGO register will be locked before the instruction is executed 31 24 Reserved R W 0 23 21 20 19 18 17 16 Reserved PCICTL Reserved HPICTL Reserved McBSP1CTL R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 15 14 13 12 11 10 9 8 Reserved McBSPOCTL Reserved I2CCTL Reserved GPIOCTL Reserved TIMEROCTL R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3
235. ller User s Guide literature number SPRUE56 are supported on the TMS320C6454 Only those registers documented in this section are supported Furthermore only the bits within the registers described here are supported You should not write to any reserved memory location or change the value of reserved bits 140 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback K Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 7 8 3 4 PLL Controller Divider 1 Register The PLL controller divider 1 register PLLDIV1 is shown in Figure 7 24 and described in Table 7 33 31 16 Reserved R 0 15 14 5 4 0 D1EN Reserved RATIO R W 1 R 0 R W 1 LEGEND R W Read Write Read only n value after reset Figure 7 24 PLL Controller Divider 1 Register PLLDIV1 Hex Address 029C 0118 Table 7 33 PLL Controller Divider 1 Register PLLDIV1 Field Descriptions Bit Field Value Description 31 16 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 15 D1EN Divider D1 enable bit 0 Divider D1 is disabled No clock output 1 Divider D1 is enabled 14 5 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 4 0 RATIO O 1Fh Divider ratio bits 1h 2 Divide frequency by 2 4h 5
236. ly the DDR2 Memory Controller and EMIFA state machines are reset by the System Reset The PLL controllers are operating in the mode prior to System Reset System clocks are unaffected The boot sequence is started after the system clocks are restarted Since the configuration pins including the BOOTMODE 3 0 pins are not latched with a System Reset the previous values as shown in the DEVSTAT register are used to select the boot mode 7 6 4 CPU Reset A CPU Reset is initiated by the or PCI peripheral This reset only affects the CPU During a PCl initiated CPU Reset the PCI pins are set to their reset state With the exception of the HRDY PIRDY pin the PCI pins have a reset state of high impedance the HRDY PIRDY pin goes high during reset 118 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 6 5 Reset Priority If any of the above reset sources occur simultaneously the PLLCTRL only processes the highest priority reset request The rest request priorities are as follows high to low e Power on Reset e Maximum Reset e Warm Reset e System Reset e CPU Reset 7 6 6 Reset Controller Register The reset type status RSTYPE register 029A OOE4 is the only register for the reset controller This register falls in the same memory range as the PLL1
237. mable through the PLL controller divider registers PLLDIV4 and PLLDIV5 respectively The PLL multiplier controller PLLM and the dividers D4 and D5 must be programmed after reset There is no hardware CLKMODE selection on the C6454 device Since the divider ratio bits for dividers D2 and D3 are fixed the frequency of SYSCLK2 and SYSCLK3 is tied to the frequency of SYSREFCLK However the frequency of SYSCLK4 and SYSCLK5 depends the configuration of dividers D4 and D5 For example with PLLM in the PLL1 multiply control register set 10011b x20 mode and a 50 MHz CLKIN1 input the PLL output PLLOUT is set to 1000 MHz SYSCLK2 and SYSCLK3 run at 333 MHz and 166 MHz respectively Divider D4 can be programmed through the PLLDIV4 register to divide SYSREFCLK by 10 such that SYSCLK4 and hence the EMIF internal clock runs at 100 MHz All hosts PCI etc must hold off accesses to the DSP while the frequency of its internal clocks is changing A mechanism must be in place such that the DSP notifies the host when the PLL configuration has completed Note that there is a minimum and maximum operating frequency for PLLREF PLLOUT SYSCLK4 and SYSCLK5 The PLL1 Controller must not be configured to exceed any of these constraints certain combinations of external clock input internal dividers and PLL multiply ratios might not be supported For the PLL clocks input and output frequency ranges see Table 7 16
238. matches the desired value state Submit Documentation Feedback Device Configuration 67 PRODUCT PREVIEW MalAddd LONGOWd TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 e Other Input Pins If the IPU IPD does not match the desired value state use an external pullup pulldown resistor to pull the signal to the opposite rail For the device configuration pins listed in Table 3 1 if they are both routed out and 3 stated not driven it is strongly recommended that an external pullup pulldown resistor be implemented Although internal pullup pulldown resistors exist on these pins and they may match the desired configuration value providing external connectivity can help ensure that valid logic levels are latched on these device configuration pins In addition applying external pullup pulldown resistors on the device configuration pins adds convenience to the user in debugging and flexibility in switching operating modes Tips for choosing an external pullup pulldown resistor e Consider the total amount of current that may pass through the pullup or pulldown resistor Make sure to include the leakage currents of all the devices connected to the net as well as any internal pullup or pulldown resistors Decide a target value for the net For a pulldown resistor this should be below the lowest V level of all inputs connected to the net For a pullup resistor this s
239. me MDCLK 5 ns 4 tsu mDIO MDcLKH Setup time MDIO data input valid before MDCLK high 10 ns th MDCLKH MDIO Hold time MDIO data input valid after MDCLK high 10 ns 1 MDCLK e a QRAN input YD QQ Figure 7 71 MDIO Input Timing Table 7 91 Switching Characteristics Over Recommended Operating Conditions for MDIO Output see Figure 7 72 720 850 NO PARAMETER 1000 UNIT MIN MAX 7 ta MDCLKL MDIO Delay time MDCLK low to MDIO data output valid 100 ns 1 gt MDCLK ow x i 2 4 7 MDIO XX XXX 555555555550 CX CXXXX XX XXX XX XXX U U U 660000000060 LAVINA Figure 7 72 MDIO Output Timing 204 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com 7 15 Timers The timers can be used to time events count events generate pulses interrupt the CPU and send TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 synchronization events to the EDMAS channel controller 7 15 1 Timers Device Specific Information The C6454 device has two general purpose timers 0 and Timer1 each of which can be configured as a general purpose timer or a watchdog timer When configured as a general purpose timer each timer can be programmed as a 64 bit tim
240. mulation circuitry The device configuration pins are also not re latched and the state of the peripherals is also not affected 1 CPU Local Reset CPU local reset 1 On the C6454 device peripherals can be in one of several states These states are listed in Table 3 4 7 6 1 Power on Reset POR Pin Power on Reset is initiated by the POR pin and is used to reset the entire chip including the test and emulation logic Power on Reset is also referred to as a cold reset since the device usually goes through a power up cycle During power up the POR pin must be asserted driven low until the power supplies have reached their normal operating conditions Note that a device power up cycle is not required to initiate a Power on Reset The following sequence must be followed during a Power on Reset 1 Wait for all power supplies to reach normal operating conditions while keeping the POR pin asserted driven low While POR is asserted all pins will be set to high impedance After the POR pin is deasserted driven high all Z group pins low group pins and high group pins are set to their reset state and will remain at their reset state until the otherwise configured by their respective peripheral All peripherals except those selected for boot purposes are disabled after a Power on Reset and must be enabled through the Device State Control registers for more details see Section 3 3 Peripheral Selection After Dev
241. n 1 1 1 Change section title to ZTZ GTZ BGA Package Bottom View Added GTZ to Section 1 1 1 ZTZ GTZ BGA Package Bottom View Section 1 3 Functional Block Diagram Updated Figure 1 2 Functional Block Diagram Section 2 1 Device Characteristics Table 2 1 Characteristics of the C6454 Processor Deleted 133 MHz from EMIFA 64 bit bus width Changed On Chip Memory Size to 1144 Updated Core Voltages Updated Megamodule Revision ID Updated JTAG BSDL_ID Added GTZ Package Section 2 3 Memory Map Summary Added EDMA Transfer Controller 0 3 Registers to Table 2 2 C6454 Memory Map Summary Section 2 4 1 Boot Modes Supported Updated paragraphs under Host boot bullet Replaced TBD document reference with TMS320C645x Bootloader User s Guide literature number SPRUEC6 Section 2 5 1 Pin Map Updated Figure 2 4 C6454 Pin Map Bottom View Quadrant C and Figure 2 5 C6454 Pin Map Bottom View Quadrant D Section 2 6 Signal Groups Description Updated Figure 2 6 CPU and Peripheral Signals Table 2 3 Terminal Functions Updated Footnote 2 Added footnote 5 reference to Signals PSERR and PINTA Updated Signal Description for AR W Updated Signal Description for DEODT1 and DEODT2 Updated Signal Descriptions for RSV07 RSV09 RSV15 RSV16 RSV32 RSV33 RSV34 and RSV35 Changed Signal 1 to updated Description and moved under Supply Voltage Monitor Pins Changed Signal L6 to DVpp33mon updated Description and moved under
242. n accessing the internal ROM of the DSP the CPU frequency must always be less than 750 MHz Figure 1 2 Functional Block Diagram 4 TMS320C6454 Fixed Point Digital Signal Processor Submit Documentation Feedback Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Contents 1 TMS320C6454 Fixed Point Digital Signal 5 5 Megamodule Resets 81 8 u uqa 1 56 Megamodule Revision 82 1 1 E 1 5 7 C64x Megamodule Register Description s 83 1 1 1 ZTZ GTZ BGA Package Bottom View 2 6 Device Operating Conditions 90 1 2 Description 2 61 Absolute Maximum Ratings Over Operating Case 1 8 Functional Block Diagram 4 Temperature Range Unless Otherwise Noted 90 2 Device Overview 6 6 2 Recommended Operating Conditions 90 24 Device eene 8 6 3 Electrical Characteristics Over Recommended 2 2 DSP Core Description 7 4 2 MS 92 2 3 Memory Map Summary 10 7 C64x Peripheral Information and Electrical 24 1 2 2 12
243. n may now be released driven inactive high When the RESET pin is released the configuration pin values are latched and the PLL controllers immediately change their system clocks to their default divide down values Other device initialization is also started 3 After device initialization is complete the RESETSTAT pin goes inactive high All system clocks are allowed to finish their current cycles and then paused for 10 cycles of their respective system reference clocks After the pause the system clocks are restarted at their default divide by settings Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 117 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 ii 4 The device is now out of reset device execution begins as dictated by the selected boot mode see Section 2 4 Boot Sequence NOTE The POR pin should be held inactive high throughout the Warm Reset sequence Otherwise if POR is activated brought low the minimum POR pulse width must be met The RESET pin should not be tied together with the POR pin 7 6 3 System Reset A System Reset is initiated by the emulator via the C64x emulation logic This reset can be masked by the emulator The following memory contents are maintained during a System Reset DDR2 Memory Controller The DDR2 Memory Controller re
244. n on the default priority values in these peripheral registers see the device compatible peripheral reference guides recommends that these priority registers be reprogrammed upon initial use 31 16 Reserved R 0000 0000 0000 0000 15 12 11 9 8 6 5 3 2 0 Reserved Reserved Reserved HOST EMAC R 000 0 R W 001 R 0 R W 010 R W 001 LEGEND R W Read Write Read only n value at reset 76 Figure 4 3 Priority Allocation Register PRI ALLOC System Interconnect Submit Documentation Feedback Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 5 64 Megamodule C64x Megamodule consists of several components the C64x CPU the L1 program and data memory controllers the L2 memory controller the internal DMA IDMA the interrupt controller power down controller and external memory controller The C64x Megamodule also provides support for memory protection for L1P L1D and L2 memories and bandwidth management for resources local to the 64 Megamodule Figure 5 1 shows a block diagram of the 64 Megamodule L1P cache SRAM 256 Internal ROM To Chip 32 registers 128 switch fabric 128 L2 memory controller L1 program memory controller Cache control Bandwidth management Cache control Memory protection Bandwidth management Advanc
245. nal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 2 Device Overview 2 1 Device Characteristics Table 2 1 provides an overview of the C6454 DSP The tables show significant features of the C6454 device including the capacity of on chip RAM the peripherals the CPU frequency and the package type with pin count 6 INSTRUMENTS www ti com Table 2 1 Characteristics of the C6454 Processor HARDWARE FEATURES C6454 Peripherals Not all peripherals pins are available at the same time For more detail see the Device Configuration section EMIFA 64 bit bus width clock source AECLKIN or SYSCLK4 DDR2 Memory Controller 32 bit bus width 1 8 V I O clock source CLKIN2 1 64 independent channels CPU 3 clock rate 1 12C 1 HPI 32 or 16 bit user selectable 1 16 HPI32 PCI 32 bit 66 2 33 MHz 1 PCI66 or PCI33 McBSPs internal CPU 6 or external clock source up to 100 Mbps 2 10 100 1000 Ethernet MAC EMAC 1 Management Data Input Output MDIO 1 64 Bit Timers Configurable internal clock source CPU 6 clock frequency 2 64 bit or 4 32 bit General Purpose Input Output Port GPIO 16 Size Bytes 1144K 32K Byte 32KB L1 Program Memory Controller On Chip Memory SRAM Cache Organization 32KB Data Memory Controller SSRAM Cache 1048KB L2 Unified Memory Cache
246. nce TI requires that all the PLL external components be on a single side of the board without jumpers switches or components other than the ones shown For reduced PLL jitter maximize the spacing between switching signals and the PLL external components C161 C162 and the EMI Filter The minimum 2 rise and fall times should also be observed For the input clock timing requirements see Section 7 8 4 PLL2 Controller Input Clock Electrical Data Timing CAUTION The PLL controller module as described in the 7MS320C645x DSP Software Programmable Phase Locked Loop PLL Controller User s Guide literature number SPRUE56 includes a superset of features some of which not supported on the C6454 DSP The following sections describe the features that are supported it should be assumed that any feature not included in these sections is not supported by the C6454 DSP TMS320C6454 DSP SYSCLK3 From PLL1 Controller gt PLLV2 r SYSCLK From PLL1 Controller DDR2 gt Memory Controller 138 74560 pF 0 1 pF X n s V A B C CLKIN2 BXC DIVIDER D1 B SYSREFCLK SYSCLK1 EMAC 9 x must be programmed to 2 for GMII default and to 5 for RGMII If EMAC is enabled with RGMII or GMII CLKIN2 frequency must be 25 MHz 2 is a 3 3 V signal Figure 7 23 PLL2 Block Diagram 64 Peripheral Information and Elec
247. nd RSV14 pins can be connected to directly ground Vas to save power However connecting these pins directly to ground will prevent boundary scan from functioning on the RGMII pins of the EMAC To preserve boundary scan functionality on the RGMII pins see Section 7 3 4 RSV14 F1 Reserved This pin must be connected to the 1 5 1 8 V I O supply DVpp s via a 200 resistor for proper device operation NOTE If the RGMII mode of the EMAC is not used the 15 VREFHSTL RSV13 and RSV14 pins can be connected to directly ground Vss to save power However connecting these pins directly to ground will prevent boundary scan from functioning on the RGMII pins of the EMAC To preserve boundary scan functionality on the RGMII pins see Section 7 3 4 RSV15 T1 Reserved This pin must be connected via a 39 Q resistor directly to ground Vss for proper device operation The resistor used should have a minimal rating of 1 10 W RSV16 T2 Reserved This pin must be connected via 20 Q resistor directly to 3 3 V I O Supply DVpp33 for proper device operation The resistor used should have a minimal rating of 1 10 W 36 Device Overview Submit Documentation Feedback 4 TEXAS 5320 6454 INSTRUMENTS Fixed Point Digital Signal Processor SPRS311A APRIL 2
248. ne of the following each clock cycle 32 x 32 bit multiply two 16 x 16 bit multiplies two 16 x 32 bit multiplies four 8 x 8 bit multiplies four 8 x 8 bit multiplies with add operations and four 16 x 16 multiplies with add subtract capabilities including a complex multiply There is also support for Galois field multiplication for 8 bit and 32 bit data Many communications algorithms such as FFTs and modems require complex multiplication The complex multiply CMPY instruction takes for 16 bit inputs and produces a 32 bit real and a 32 bit imaginary output There are also complex multiplies with rounding capability that produces one 32 bit packed output that contain 16 bit real and 16 bit imaginary values The 32 x 32 bit multiply instructions provide the extended precision necessary for audio and other high precision algorithms on a variety of signed and unsigned 32 bit data types The L or Arithmetic Logic Unit now incorporates the ability to do parallel add subtract operations on a pair of common inputs Versions of this instruction exist to work on 32 bit data or on pairs of 16 bit data performing dual 16 bit add and subtracts in parallel There are also saturated forms of these instructions The 64 core enhances the S unit in several ways In the C64x core dual 16 bit MIN2 and MAX2 comparisons were only available on the L units On the 64 core they are also available on the S unit which increases the performance of algori
249. ng and the state of the FIFO transitions on HRDY may or may not occur For more detailed information on the HPI peripheral see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 Figure 7 51 2 Write Timing HAS Used 176 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 13 Multichannel Buffered Serial Port McBSP The McBSP provides these functions e Full duplex communication e Double buffered data registers which allow a continuous data stream Independent framing and clocking for receive and transmit e Direct interface to industry standard codecs analog interface chips and other serially connected analog to digital A D and digital to analog D A devices e External shift clock or an internal programmable frequency shift clock for data transfer For more detailed information on the McBSP peripheral see the TMS320C6000 DSP Multichannel Buffered Serial Port McBSP Reference Guide literature number SPRU580 rev E or later Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 177 PRODUCT PREVIEW Mal aad TMS320C6454 49 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 13 1 McBSP Device Specifi
250. ng specifications as required by the PC Local Bus Specification version 2 3 The AC timing specifications are not reproduced here For more information on the AC timing Specifications see section 4 2 3 Timing Specification 33 MHz timing and section 7 6 4 Timing Specification 66 MHz timing of the PCI Local Bus Specification version 2 3 Note that the C6454 PCI peripheral only supports 3 3 V signaling Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 213 PRODUCT PREVIEW Mal aad TMS320C6454 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 17 General Purpose Input Output GPIO 7 17 1 GPIO Device Specific Information On the C6454 the GPIO peripheral pins GP 15 8 GP 3 0 muxed with the PCI and McBSP1 peripheral pins and the SYSCLK4 signal For more detailed information on device peripheral configuration and the C6454 device pin muxing see Section 3 Device Configuration 7 17 2 GPIO Peripheral Register Description s Table 7 102 GPIO Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02 0 0008 GPIO interrupt per bank enable register 02 0 000 Reserved 02 0 0010 DIR GPIO Direction Register 02 0 0014 OUT_DATA GPIO Output Data register 02B0 0018 SET_DATA GPIO Set Data register 02 0 001 CLR DATA GPIO Clear Data Regist
251. nitialization Also shown is the default value of these registers when PCI auto initialization is not used PCI auto initialization is controlled enabled disabled through the PCI EEAI pin P25 For more information on this feature see the TMS320C645x DSP Peripheral Component Interconnect PCI User s Guide literature number SPRUE60 and the TMS320C645x Bootloader User s Guide literature number SPRUEC6 Table 7 96 Default Values for PCI Configuration Registers DEFAULT REGISTER VALUE Vendor ID Device ID Register PCIVENDEV 104C B000h Class Code Revision ID Register PCICLREV 0000 0001h Subsystem Vendor ID Subsystem ID Register 0000 0000h PCISUBID Max Latency Min Grant Interrupt Pin Interrupt Line 0000 0100h Register PCILGINT The on chip Bootloader supports a host boot which allows an external PCI device to load application code into the DSP s memory space The PCI boot is terminated when the Host generates a DSP interrupt The Host can generate a DSP interrupt through the PCI peripheral by setting the DSPINT bit in the Back End Application Interrupt Enable Set Register PCIBINTSET and the Status Set Register PCISTATSET For more information on the boot sequence of the C6454 DSP see Section 2 4 NOTE After the host boot is complete the DSP interrupt is registered in bit 0 channel 0 of the EDMA Event Register ER This event must be cleared by software before triggering transfers on DMA channel 0
252. nsitions on HRDY may or may not occur For more detailed information on the HPI peripheral see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 Figure 7 44 16 Read Timing HAS Not Used Tied High Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 169 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 HAS _ 7 7 x 4 12 1 1 XXX k gt 12 12 e 11 e 11 ABb IU y T l C i O O kH 12 12 4 1 11 Ila 21 11 www 4 5 10 4 9 37 4 13 135 697 0 4 14 gt HSTROBE __ v 7 1 3 4 2 3 2 HD 15 0 _ _ac gt ax 7 36 l 6 m HRDY B HSTROBE refers to the following logical operation HCS HDS1 and 052 NOT HDS1 XOR HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed information on the HPI peripheral see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 Figure 7 45 16 Read Tim
253. ntended to aid the programmer in isolating bugs The C64x CPU is able to detect and respond to exceptions both from internally detected sources such as illegal op codes and from system events such as a watchdog time expiration Privilege Defines user and supervisor modes of operation allowing the operating system to give a basic level of protection to sensitive resources Local memory is divided into multiple pages each with read write and execute permissions Time Stamp Counter Primarily targeted for Real Time Operating System RTOS robustness a free running time stamp counter is implemented in the CPU which is not sensitive to system stalls For more details on the C64x CPU and its enhancements over the C64x architecture see the following documents TMS320C64x C64x DSP CPU and Instruction Set Reference Guide literature number SPRU732 TMS320C64x DSP Cache User s Guide literature number SPRU862 TMS320C64x Megamodule Reference Guide literature number SPRU871 TMS320C6455 Technical Reference literature number SPRU965 TMS320C64x to TMS320C64x CPU Migration Guide literature number SPRAA84 8 Device Overview Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Even register file A 0 2 4 0 Odd register file A A1 5 1 0 Data path LD1b LD1a
254. o two categories masters and slaves Masters are capable of initiating read and write transfers in the system and do not rely on the for their data transfers Slaves on the other hand rely on the EDMAG to perform transfers to and from them Masters include the EDMAS traffic controllers and PCI Slaves include the McBSP and 2 The C6454 device contains two switch fabrics through which masters and slaves communicate The data switch fabric known as the data switched central resource SCR is a high throughput interconnect mainly used to move data across the system for more information see Section 4 2 The data SCR connects masters to slaves via 128 bit data buses running at SYSCLK2 frequency SYSCLK2 is generated from PLL1 controller Peripherals that have a 128 bit data bus interface running at this speed can connect directly to the data SCR other peripherals require a bridge The configuration switch fabric also known as the configuration switch central resource SCR is mainly used by the C64x Megamodule to access peripheral registers for more information see Section 4 3 The configuration SCR connects C64x Megamodule to slaves via 32 bit configuration buses running at a SYSCLK2 frequency SYSCLK2 is generated from PLL1 controller As with the data SCR some peripherals require the use of a bridge to interface to the configuration SCR Note that the data SCR also connects to the configuration SCR Bridges perform a varie
255. ociative cache while L1P is a direct mapped cache The L1P and L1D cache can be reconfigured via software through the L1PMODE field of the L1P Configuration Register L1PMODE and the L1DMODE field of the L1D Configuration Register L1DCFG of the C64x Megamodule After device reset L1P and L1D cache are configured as all cache or all SRAM The on chip Bootloader changes the reset configuration for L1P and L1D For more information see the TMS320C645x Bootloader User s Guide literature number SPRUEC6 Figure 5 2 and Figure 5 3 show the available SRAM cache configurations for L1P and L1D respectively L1P mode bits Block base 000 001 010 011 100 L1P memory address 00 0 0000h 16K bytes 3 4 7 8 SRAM All SRAM direct SRAM mapped 00 0 4000h cache 8K bytes direct L mapped 00 0 6000h direct cache 4K bytes 00 0 7000h cache 4K bytes 00 0 8000h Figure 5 2 TMS320C6454 L1P Memory Configurations L1D mode bits Block base 000 001 010 011 100 L1D memory address 00 0 0000h eben 16K bytes 3 4 7 8 SRAM All SRAM 2 wa y SRAM 00 0 4000h 8K bytes 2 way 00 0 6000h 4K bytes 2 00F0 7000h 4K bytes 00 0 8000h 78 C64x Megamodule Figure 5 3 TMS320C6454 L1D Memory Configurations Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com 5320 6454 Fixe
256. of these constraints For the PLL clocks input and output frequency ranges see Table 7 31 Also when EMAC is enabled with RGMII or CLKIN2 must be 25 MHz Table 7 31 PLL2 Clock Frequency Ranges CLOCK SIGNAL MIN MAX UNIT PLLREF PLLEN 1 12 5 26 7 MHz PLLOUT 250 533 MHz 5 5 1 50 125 2 1 SYSCLK1 restriction applies only when the EMAC is enabled and the RGMII GMII modes are used SYSCLK1 must be programmed to 125 MHz when the mode is used and to 50 MHz when the RGMII mode is used 7 8 1 2 PLL2 Controller Operating Modes Unlike the PLL1 controller which can operate in bypass and a PLL mode the PLL2 controller only operates in PLL mode In this mode SYSREFCLK is generated outside the PLL2 controller by dividing the output of PLL2 by two The PLL2 controller is affected by power on reset and warm reset During these resets the PLL2 controller registers get reset to their default values The internal clocks of the PLL2 controller are also affected as described in Section 7 6 Reset Controller PLL2 is only unlocked during the power up sequence see Section 7 6 Reset Controller and is locked by the time the RESETSTAT pin goes high It does not lose lock during any of the other resets Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 139 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal
257. oherency operations and IDMA initiated transfers are declared through registers in the C64x Megamodule The priority level for operations initiated outside the C64x Megamodule by system peripherals is declared through the Priority Allocation Register PRI ALLOC see Section 4 4 System peripherals with no fields in PRI ALLOC have their own registers to program their priorities More information on the bandwidth management features of the 64 Megamodule can be found in the TMS320C64x Megamodule Reference Guide literature number SPRU871 C64x4 Megamodule Submit Documentation Feedback 249 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 5 4 Power Down Control The C64x Megamodule supports the ability to power down various parts of the C64x Megamodule The power down controller PDC of the C64x Megamodule can be used to power down L1P the cache control hardware the CPU and the entire C64x Megamodule These power down features can be used to design systems for lower overall system power requirements NOTE The C6454 does not support power down modes for the L2 memory at this time More information on the power down features of the 64 Megamodule can be found in the TMS320C64x Megamodule Reference Guide literature number SPRU871 5 5 Megamodule Resets Table 5 2 shows the reset types supported on the C6454 device and they affect the res
258. onnect to a voltage of DVpp 4 2 The DVpp 4 2 voltage can be generated directly from the DVppig supply using two 1 kQ resistors to form a resistor divider circuit e RSV11 connect this pin to ground Vss via 200 0 resistor e RSV12 connect this pin to the 1 8 V I O supply DVppig via a 200 0 resistor Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 97 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 4 Enhanced Direct Memory Access Controller 7 4 1 98 www ti com The primary purpose of the EDMA3 is to service user programmed data transfers between two memory mapped slave endpoints on the device EDMAS services software driven paging transfers e g data movement between external memory and internal memory performs sorting or subframe extraction of various data structures services event driven peripherals such as the McBSP and offloads data transfers from the device CPU The EDMAG includes the following features e Fully orthogonal transfer description Stransfer dimensions array multiple bytes frame multiple arrays and block multiple frames Single event can trigger transfer of array frame or entire block Independent indexes on source and destination e Flexible transfer definition Increment or FIFO transfer addressing modes
259. onnect to all slaves Allowed connections are summarized in Table 4 1 72 System Interconnect Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com EDMA3 Channel Controller EDMA3 Transfer Controllers EMAC Megamodule MASTER 128 SYSCLK2 A Events Data SCR 128 SYSCLK2 128 gt 2 128 SYSCLK2 5320 6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 128 SYSCLK2 3 2 SYSCLK3 128 bit SYSCLK2 128 SYSCLK2 32 SYSCLK2 Bridge 32 32 SYSCLK3 32 32 5 5 128 SYSCLK2 128 SYSCLK2 v Q Configuration Bus Data Bus SYSCLK3 SYSCLK3 128 SYSCLK2 128 SYSCLK2 SYSCLK2 SYSCLK2 32 SYSCLK3 Se 32 SYSCLK3 64 64 128 SYSCLK2 SCR McBSPs Figure 4 1 Switched Central Resource Block Diagram Submit Documentation Feedback Megamodule DDR2 Memory Controller System Interconnect 73 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 4 1 SCR Connection Matrix McBSPs CONFIGURAT
260. ontrol address or data registers 1 default or PONTE VEDEVSEL Us VOZ PCI device select VO Z DOTAD Host control selects between control address or data registers 1 default or HCNTLO PSTOP U5 VO Z PCI stop 2 Host half word select first or second half word not necessarily high or low HHWIL PCLK V3 VO Z order For HPI16 bus width selection only I default or PCI clock I HR W PCBE2 T5 VO Z Host read or write select I default or PCI command byte enable 2 2 HAS PPAR T3 VO Z Host address strobe I default or PCI parity 0 2 HCS PPERR U6 VO Z Host chip select I default or PCI parity error 0 2 HDS1 PSERR U2 VO Z Host data strobe 1 I default or PCI system error 1 0 2 HDS2 PCBE1 U1 VO Z Host data strobe 2 I default or PCI command byte enable 1 I O Z HRDY PIRDY T4 VO Z Host ready from DSP to host 0 2 default or PCI initiator ready 0 2 PREQ GP 15 P2 VO Z PCI bus request 0 2 or GP 15 I O Z default PINTA O GPT 14 P3 VO Z PCI interrupt 0 2 or GP 14 0 2 default PRST GP 13 R5 VO Z PCI reset I or GP 13 0 2 default PGNT GP 12 R4 VO Z PCI bus grant I or GP 12 VO Z default PCBEO GP 2 P1 VO Z PCI command byte enable 0 2 or GP 2 VO Z default PCBE3 P5 VO Z PCI command byte enable 3 2 By default this pin has no function PIDSEL R3 PCI initialization device select I By default this pin has no function 5
261. ontrol status reg Receive Buffer Receive Shift Interrupt DMA Interrupt I2CIMR Mask Status Interrupt 2 5 Status Interrupt I2CIVR Vector isters Figure 7 41 I2C Module Block Diagram Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 161 PRODUCT PREVIEW Mal aad TMS32006454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 6 INSTRUMENTS www ti com 7 11 2 12 Peripheral Register Description s Table 7 51 2 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02 0 4000 ICOAR 12 own address register 02 0 4004 ICIMR 2 interrupt mask status register 02 0 4008 ICSTR 12 interrupt status register 02B0 400C ICCLKL 2 clock low time divider register 02 0 4010 2 clock high time divider register 02 0 4014 ICCNT 12C data count register 02B0 4018 ICDRR 12 data receive register 02B0 401C ICSAR I2C slave address register 02 0 4020 ICDXR 12 data transmit register 02B0 4024 ICMDR 2 mode register 02B0 4028 ICIVR 12 interrupt vector register 02 0 402C ICEMDR 2 extended mode register 02B0 4030 ICPSC 12 prescaler register 02B0 4034 ICPID1 2 peripheral identification register 1 Value 0 0000 0105 02B0 4038 ICPID2 12 peripheral identification register 2 Value 0x0000 0005
262. ormation and Electrical Specifications 173 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 gt 10 HAS input 11 HCNTL 1 0 input HR W input x lt 9 13 HSTROBE input 4 HCS input lt 1 3 HD 31 0 output S00 7 4 38 4 6 I 36 HRDY output 4 2 HSTROBE refers to the following logical operation on HCS HDS1 and HDS2 NOT HDS1 HDS2 OR HCS B Depending on the type of write or read operation HPID without auto incrementing HPIA HPIC or HPID with auto incrementing and the state of the FIFO transitions on HRDY may or may not occur For more detailed information on the HPI peripheral see the TMS320C645x DSP Host Port Interface HPI User s Guide literature number SPRU969 Figure 7 49 HPI32 Read Timing HAS Used 174 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com HAS input 16 154 t 5320 6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 HCNTL 1 0 Y X mu 9 input HR W input e 13 gt HSTROBE N input 4 18
263. ount version of the MII mode Interface Mode Select The EMAC uses the same pins for the GMII and RMII modes Standalone pins are included for the RGMII mode due to specific voltage requirements Only one mode can be used at a time The mode used is selected at device reset based on the MACSEL 1 0 configuration pins for more detailed information see Section 3 Device Configuration Table 7 70 shows which multiplexed pins are used in the MII GMII and RMII modes on the EMAC For a detailed description of these pin functions see Table 2 3 Terminal Functions 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 Table 7 70 EMAC MDIO Multiplexed Pins MII RMII and GMII Modes BALL NUMBER DEVICE PIN NAME MII RMII GMII SEL MAC SEL MAC_SEL 00b 01b 10b J2 MRXD0 RMRXD0 MRXD0 RMRXD0 MRXD0 H3 MRXD1 RMRXD1 MRXD1 RMRXD1 MRXD1 MRXD2 MRXD2 MRXD2 J3 MRXD3 MRXD3 MRXD3 L1 MRXD4 MRXD4 L2 MRXD5 MRXD5 H2 MRXD6 MRXD6 M2 MRXD7 MRXD7 M1 MTXDO RMTXDO MTXDO RMTXDO MTXDO L4 MTXD1 RMTXD1 MTXD1 RMTXD1 MTXD1 M4 MTXD2 MTXD2 MTXD2 K4 MTXD3 MTXD3 MTXD3 L3 MTXD4 MTXD4 L5 MTXD5 MTXD5 M3 MTXD6 MTXD6 N5 MTXD7 MTXD7 H4 MRXER RMRXER MRXER RMRXER MRXER H5 MRXDV MRXDV MRXDV J
264. perature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by to Customer on an annual basis Addendum Page 1 MECHANICAL DATA GTZ S PBGA N697 PLASTIC BALL GRID ARRAY 22 40 TYP OOOOOOOOOOOOOO OOOOOOOOOOOOOO OOOQQOOOOOOOOOQ0 Qoooooooooooooe 5 2 A1 Corner OOOOOOOOOOOOO OOOOOOOOOOOOCO ie HEAT SLUG OOOOOOOO 19 21 23 25 27 29 12 14 16 18 20 22 24 26 28 oooooooooooooo Bottom Vi
265. pheral Lock Register 02AC 0008 PERCFGO Peripheral Configuration Register 0 02AC 000C Reserved 02AC 0010 Reserved 02AC 0014 PERSTATO Peripheral Status Register 0 02AC 0018 PERSTAT1 Peripheral Status Register 1 02AC 001C 02AC 001F Reserved 02AC 0020 EMACCFG EMAC Configuration Register 02 0024 02AC 002B Reserved 02AC 002C PERCFG1 Peripheral Configuration Register 1 02AC 0030 02AC 0053 Reserved 02AC 0054 EMUBUFPD Emulator Buffer Powerdown Register 02AC 0058 Reserved Submit Documentation Feedback Device Configuration 55 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 3 4 1 Peripheral Lock Register Description When written with correct 32 bit key 0x0F0A0B00 the Peripheral Lock Register PERLOCK allows one write to the PERCFGO register within 16 SYSCLK3 cycles NOTE The instructions that write to the PERLOCK and PERCFGO registers must be in the same fetch packet if code is being executed from external memory If the instructions are in different fetch packets fetching the second instruction from external memory may stall the instruction long enough such that PERCFGO register will be locked before the instruction is executed 31 0 LOCKVAL R W FOFO FOFO LEGEND R W Read Write value after reset Figure 3 3 Peripheral Lock Register PERLOCK 0x02AC 0004 Tab
266. pin The monitor pins indicate the voltage on the die and therefore provide the best probe point for voltage monitoring purposes For more information regarding the use of this and other voltage monitoring pins If the DVpp4syow pin is not used it should DV F3 be connected directly to the 1 5 1 8 V I O supply DVpp s DD15MON NOTE If the RGMII mode of the EMAC is not used the DVppis5 DVppisMoN VreFHstL RSV13 and RSV14 pins can be connected directly to ground Vss to save power However connecting these pins directly to ground will prevent boundary scan from functioning on the RGMII pins of the EMAC To preserve boundary scan functionality on the RGMII pins see Section 7 3 4 Die side 1 8 V I O supply DVppig voltage monitor pin The monitor pins indicate the voltage on the die and therefore provide the best probe point for DVpp18MON A26 voltage monitoring purposes For more information regarding the use of this and other voltage monitoring pins If the DVppigmon pin is not used it should be connected directly to the 1 8 V I O supply DVpp g SUPPLY VOLTAGE PINS DVpp18 2 V reference for SSTL buffer DDR2 Memory Controller This input voltage can be generated directly from DVpp g using two 1 resistors to form a resistor divider circuit NOTE The DDR2 Memory Controller is not used the Vrersst_ RSV11 and VREFSSTL C14 A RSV12 pins can be connected directly to ground Vss to save power However connecting these pins d
267. pping Register 02A0 0104 DCHMAP49 DMA Channel 49 Mapping Register 02A0 01C8 DCHMAP50 DMA Channel 50 Mapping Register 02A0 01CC DCHMAP51 DMA Channel 51 Mapping Register 02 0 0100 52 DMA Channel 52 Mapping Register 02A0 01D4 DCHMAP53 DMA Channel 53 Mapping Register 02A0 01D8 DCHMAP54 DMA Channel 54 Mapping Register 02A0 01DC DCHMAP55 DMA Channel 55 Mapping Register 02A0 01E0 DCHMAP56 DMA Channel 56 Mapping Register 02A0 01E4 DCHMAP57 DMA Channel 57 Mapping Register 02A0 01E8 DCHMAP58 DMA Channel 58 Mapping Register 02A0 01EC DCHMAP59 DMA Channel 59 Mapping Register 02A0 01 0 DCHMAP60 DMA Channel 60 Mapping Register 02A0 01F4 DCHMAP61 DMA Channel 61 Mapping Register 02A0 01F8 DCHMAP62 DMA Channel 62 Mapping Register 02A0 01FC DCHMAP63 DMA Channel 63 Mapping Register 02A0 0200 QCHMAPO QDMA Channel 0 Mapping Register 02A0 0204 1 QDMA Channel 1 Mapping Register 02A0 0208 QCHMAP2 QDMA Channel 2 Mapping Register 02A0 020C QCHMAP3 QDMA Channel 3 Mapping Register 02A0 0210 02 0 021C Reserved 02A0 0220 02A0 023C Reserved 02A0 0240 DMAQNUMO DMA Queue Number Register 0 02A0 0244 DMAQNUM1 DMA Queue Number Register 1 02A0 0248 DMAQNUM2 DMA Queue Number Register 2 02A0 024C DMAQNUM3 DMA Queue Number Register 3 02A0 0250 02A0 025C 5 Reserved 02 0 0260 QDMAQNUM QDMA Queue Number Register 02A0 0264 02A0 0280 Reserved 02A0 0284 QUEPRI Queue Priority Register 02A0 0288 02A0 02FC Reserved Submit
268. r 12C Timer 0 Timer 1 GPIO I Peripheral is held in reset and clock is turned off Default state for all Disabled peripherals not in static powerdown mode McBSP1 HPI PCI 2 0 1 GPIO MDIO Enabled Clock to the peripheral is turned on and the peripheral is taken out of reset cee McBSP1 HPI PCI EMIFA DDR2 Memory Controller Enable in progress Not a user programmable state This is an intermediate state when transitioning from an disabled state to an enabled state peripherals that be in an enabled state Submit Documentation Feedback Device Configuration 53 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 Following device reset all peripherals that are not in the static powerdown state are in the disabled state by default Peripherals used for boot such as HPI and PCI are enabled automatically following a device reset Peripherals are only allowed certain transitions between states see Figure 3 1 Static Powerdown Enable In Progress Disabled Enabled Figure 3 1 Peripheral Transitions Between States Figure 3 2 shows the flow needed to change the state of a given peripheral on the C6454 device Unlock the PERCFG0 register by using the PERLOCK register Write to the PERCFGO register within 16 SYSCLK3
269. r all SPI Slave modes CLKG is programmed as 1 6 of the CPU clock by setting CLKSM CLKGDV 1 S Sample rate generator input clock 6P if CLKSM 1 P 1 CPU clock frequency S Sample rate generator input clock P clks if CLKSM 0 P clks period T CLKX period 1 CLKGDV S CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd L CLKX low pulse width CLKGDV 2 S if CLKGDV is even L CLKGDV 1 2 S if CLKGDV is odd FSRP FSXP 1 As a SPI Master FSX is inverted to provide active low slave enable output As a Slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for Master McBSP CLKXM CLKRM FSXM FSRM 0 for Slave McBSP FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock CLKX CLKX j LS LS 1 gt l le 2 l FSX y 6 k 7 gt ke 83 DX Bitn X n2 X m3 X m X dE fuu DR X m2 X GEE X mQ J Figure 7 55 McBSP Timing as SPI Master or Slave CLKSTP 11b CLKXP 0 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 6
270. r alternate transfer completion events For more detailed information on EDMA event transfer chaining see the TMS320C645x DSP Enhanced DMA Controller User s Guide literature number SPRU966 2 HPI boot and PCI boot are terminated using a DSP interrupt The DSP interrupt is registered in bit 0 channel 0 of the EDMA Event Register ER This event must be cleared by software before triggering transfers on DMA channel 0 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 99 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 3 C6454 EDMA3 Channel Synchronization Events continued EVENT DESCRIPTION 58 011 1010 GPINT10 GPIO event 10 59 011 1011 GPINT11 GPIO event 11 60 011 1100 GPINT12 GPIO event 12 61 011 1101 GPINT13 GPIO event 13 62 011 1110 GPINT14 GPIO event 14 63 011 1111 GPINT15 GPIO event 15 7 43 EDMAS Peripheral Register Description s Table 7 4 EDMA3 Channel Controller Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 0000 PID Peripheral ID Register 02 0 0004 CCCFG EDMA3CC Configuration Register 02A0 0008 02A0 00 x Reserved 02A0 0100 DCHMAP
271. rame Overruns Register 02C8 0288 RXMOFOVERRUNS Receive FIFO or DMA Middle of Frame Overruns Register 02C8 028C RXDMAOVERRUNS DMA Start of Frame and Middle of Frame Overruns 02 8 0290 02C8 02FC Reserved Table 7 73 EMAC Control Module Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02C8 1000 Reserved 02C8 1004 EWCTL EMAC Control Module Interrupt Control Register 02C8 1008 EWINTTCNT EMAC Control Module Interrupt Timer Count Register 02C8 100C 02C8 17FF Reserved Table 7 74 EMAC Descriptor Memory HEX ADDRESS RANGE ACRONYM DESCRIPTION 02C8 2000 02C8 3FFF EMAC Descriptor Memory 194 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com 7 14 3 EMAC Electrical Data Timing 7 14 3 1 EMAC and GMII Electrical Data Timing 5320 6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 75 Timing Requirements for MRCLK MII GMII Operation see Figure 7 59 720 850 1000 UNIT 1000 Mbps GMII Only 100 Mbps 10 Mbps MIN MAX MIN MAX MIN MAX 1 te MRCLK Cycle time MRCLK 8 40 400 ns 2 tw MRCLKH Pulse duration MRCLK high 2 8 14 140 ns 3 tw MRCLKL Pulse duration MRCLK low 2 8 14 140 ns 4 li MRCLK Transition time MRCLK
272. rated conditions for extended periods may affect device reliability 2 All voltage values are with respect to Vss 6 2 Recommended Operating Conditions MIN NOM MAX UNIT 1000 1 2125 1 25 1 2875 V CV Supply voltage Core z B 2 1 1640 1 20 1 2360 720 DVpp33 Supply voltage I O 3 14 3 3 3 46 V DVpp18 Supply voltage I O 1 71 1 8 1 89 V Supply voltage I O 1 71 1 8 1 89 V Supply voltage I O 1 71 1 8 1 89 V VREFSSTL Reference voltage 0 49DVppi8 0 50DVppig 0 51 DVppi8 V DV Supply voltage I O required only 1 8 V operation 1 71 1 8 1 89 V 0015 for EMAC RGMII 1 5 V operation 1 43 1 5 1 57 V 1 8 V operation 0 855 0 9 0 945 V VrerHst Reference voltage 1 5 V operation 0 713 0 75 0 787 V DLL Supply voltage PLL 1 71 1 8 189 V Vss Supply ground 0 0 0 V 3 3 V pins except PCl capable and 2 V I2C pins PCI capable pins 0 5DVpp33 DVpp33 0 5 V High level input voltage 12 pins 0 7DVpp33 V RGMII pins VREFHSTL 0 10 DVpp15 0 30 V DDR2 memory controller pins VREFSSTL 0 125 DVppi8 0 3 V DC 90 Device Operating Conditions Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 Recommended Operating Conditions continued MIN NOM MAX UNIT 3 3 V pins
273. rding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated product or service and is an unfair and deceptive business practice Tl is not responsible or liable for any such statements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military
274. ress Register 3 02A3 03C8 DFCNT3 Destination FIFO Count Register 3 02A3 03CC DFDST3 Destination FIFO Destination Address Register 3 02A3 03D0 DFBIDX3 Destination FIFO BIDX Register 3 02A3 03D4 DFMPPRXY3 _ Destination FIFO Memory Protection Proxy Register 02A3 0308 02A3 7FFF Reserved Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 109 PRODUCT PREVIEW Mal aad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 9 EDMAS Transfer Controller 3 Registers 6 INSTRUMENTS www ti com HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A3 8000 PID Peripheral Identification Register 02A3 8004 TCCFG Configuration Register 02A3 8008 02A3 80FC Reserved 02A3 8100 TCSTAT Channel Status Register 02A3 8104 02A3 811C Reserved 02A3 8120 ERRSTAT Error Register 02A3 8124 ERREN Error Enable Register 02A3 8128 ERRCLR Error Clear Register 02A3 812C ERRDET Error Details Register 02A3 8130 ERRCMD Error Interrupt Command Register 02A3 8134 02A3 813C Reserved 02A3 8140 RDRATE Read Rate Register 02A3 8144 02A3 823C Reserved 02A3 8240 SAOPT Source Active Options Register 02A3 8244 SASRC Source Active Source Address Register 02A3 8
275. ripheral pins are disabled default 1 DDR2 Memory Controller peripheral pins are enabled EMIFA enable EMIFA_EN ABA1 V25 IPD 0 EMIFA peripheral pins are disabled default 1 EMIFA peripheral pins are enabled 3 2 Peripheral Configuration at Device Reset Some C6454 peripherals share the same pins internally multiplexed and are mutually exclusive Therefore not all peripherals may be used at the same time The device configuration pins described in Section 3 1 Device Configuration at Device Reset determine which function is enabled for the multiplexed pins Note that when the pin function of a peripheral is disabled at device reset the peripheral is permanently disabled and cannot be enabled until its pin function is enabled and another device reset is executed Also note that enabling the pin function of a peripheral does not enable the corresponding peripheral All peripherals on the C6454 device are disabled by default except when used for boot and must be enabled through software before being used Other peripheral options like PCI clock speed and EMAC MDIO interface mode can also be selected at device reset through the device configuration pins The configuration selected is also fixed at device reset and cannot be changed until another device reset is executed with a different configuration selected The multiply factor of the PLL1 Controller is not selected through the configuration pins The PLL1 multiply factor
276. ristics of the C6454 Processor continued HARDWARE FEATURES C6454 Device Part Numbers For more details on the C64x DSP part T numbering see Figure 2 12 TMX320C6454ZTZ 2 2 CPU DSP Core Description The 64 Central Processing Unit CPU consists of eight functional units two register files and two data paths as shown in Figure 2 1 The two general purpose register files A and B each contain 32 32 bit registers for a total of 64 registers The general purpose registers can be used for data or can be data address pointers The data types supported include packed 8 bit data packed 16 bit data 32 bit data 40 bit data and 64 bit data Values larger than 32 bits such as 40 bit long or 64 bit long values are stored in register pairs with the 32 LSBs of data placed in an even register and the remaining 8 or 32 MSBs in the next upper register which is always an odd numbered register The eight functional units M1 L1 D1 S1 M2 12 D2 and S2 are each capable of executing one instruction every clock cycle The M functional units perform all multiply operations The S and L units perform a general set of arithmetic logical and branch functions The D units primarily load data from memory to the register file and store results from the register file into memory The C64x CPU extends the performance of the C64x core through enhancements and new features Each C64x M unit can perform o
277. rocessor DSP megamodule Included is a discussion on the internal direct memory access IDMA controller the interrupt controller the power down controller memory protection bandwidth management and the memory and cache SPRAA84 TMS320C64x to TMS320C64x CPU Migration Guide Describes migrating from the Texas Instruments TMS320C64x digital signal processor DSP to the TMS320C64x DSP The 48 Device Overview Submit Documentation Feedback 4 6 INSTRUMENTS www ti com SPRU889 SPRU970 SPRU966 SPRU975 SPRU971 SPRU724 SPRU969 SPRU974 SPRUE60 SPRUE56 SPRU968 TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 objective of this document is to indicate differences between the two cores Functionality in the devices that is identical is not included High Speed DSP Systems Design Reference Guide Provides recommendations for meeting the many challenges of high speed DSP system design These recommendations include information about DSP audio video and communications systems for the C5000 and C6000 DSP platforms TMS320C645x DSP DDR2 Memory Controller User s Guide This document describes the DDR2 memory controller in the TMS320C645x digital signal processors DSPs TMS320C645x DSP Enhanced EDMA3 Controller User s Guide This document describes the Enhanced DMA EDMA3 Controller on the TMS320C645x device TMS320C645x DSP EMAC MDIO Module User s
278. rotection Page Attribute Register 6 02A0 0828 MPPA7 Memory Protection Page Attribute Register 7 02A0 082C 02A0 OFFC Reserved 02A0 1000 ER Event Register 02A0 1004 ERH Event Register High 02A0 1008 ECR Event Clear Register 02A0 100C ECRH Event Clear Register High 02A0 1010 ESR Event Set Register 02A0 1014 ESRH Event Set Register High 02A0 1018 CER Chained Event Register 02A0 101C CERH Chained Event Register High 02A0 1020 EER Event Enable Register 02A0 1024 EERH Event Enable Register High 02A0 1028 EECR Event Enable Clear Register 02A0 102C EECRH Event Enable Clear Register High 02A0 1030 EESR Event Enable Set Register 02A0 1034 EESRH Event Enable Set Register High 02A0 1038 SER Secondary Event Register 02A0 103C SERH Secondary Event Register High 02A0 1040 SECR Secondary Event Clear Register 02A0 1044 SECRH Secondary Event Clear Register High 02A0 1048 02A0 104C Reserved 02A0 1050 IER Interrupt Enable Register 02A0 1054 IERH Interrupt Enable High Register 02A0 1058 IECR Interrupt Enable Clear Register C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS 5320 6454 INSTRUMENTS Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 4 EDMA3 Channel Controller Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02 0 105 IECRH Interrupt Enable Clear High Register 02A0 1060
279. s Register 02A3 0104 02A3 011 Reserved 02A3 0120 ERRSTAT Error Register 02A3 0124 ERREN Error Enable Register 02A3 0128 ERRCLR Error Clear Register 02A3 012C ERRDET Error Details Register 02A3 0130 ERRCMD Error Interrupt Command Register 02A3 0134 02 013 Reserved 02A3 0140 RDRATE Read Rate Register 108 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS www ti com Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 8 EDMA3 Transfer Controller 2 Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A3 0144 02A3 023C Reserved 02A3 0240 SAOPT Source Active Options Register 02A3 0244 SASRC Source Active Source Address Register 02A3 0248 SACNT Source Active Count Register 02A3 024C SADST Source Active Destination Address Register 02A3 0250 SABIDX Source Active Source B Index Register 02A3 0254 SAMPPRXY Source Active Memory Protection Proxy Register 02A3 0258 SACNTRLD Source Active Count Reload Register 02A3 025C SASRCBREF _ Source Active Source Address B Reference Register 02A3 0260 SADSTBREF Source Active Destination Address B Reference Register 02A3 0264 02A3 027C Reserved 02A3 0280 DFCNTRLD Destination FIFO Set Count Reload 02A3
280. s necessary through Host Port Interface HPI or the Peripheral Component Interconnect PCI interface Internal configuration registers such as those that control the EMIF can also be initialized by the host with two exceptions Device State Control registers Section 3 4 PLL1 and PLL2 Controller registers Section 7 7 and Section 7 8 cannot be accessed through any host interface including and PCI Once the host is finished with all necessary initialization it must generate a DSP interrupt DSPINT to complete the boot process This transition causes boot configuration logic to bring the CPU out of the stalled state The CPU then begins execution from the internal L2 SRAM located at 0x80 0000 Note that the DSP interrupt is registered in bit 0 channel 0 of the EDMA Event Register ER This event must be cleared by software before triggering transfers on DMA channel 0 All memory with the exceptions previously described may be written to and read by the host This allows for the host to verify what it sends to the DSP if required After the CPU is out of the stalled state the CPU needs to clear the DSPINT otherwise no more DSPINTs can be received As previously mentioned for the C6454 device the Host Port Interface and the Peripheral Component Interconnect PCI interface can be used for host boot To use the for host boot the PCI EN pin Y29 must be low default enabling the HPI peripheral and BOOTMODE 3 0
281. ss DED11 Vss DVppis Vss DVpp18 Vss DVpp18 E RGRXDO RGRXD1 RGRXC RGRXD2 Vss RSV34 Vss DSDDQS1 DED10 DVppig DSDDQSO DVppig RSV18 DCEO DBA2 b Vss DVppis RGTXCTL RGTXC DVppis RSV35 DEDi4 0500051 DED9 DED7 0500050 DSDCAS DSDCKE DBA1 C RGRXD3 RGRXCTL RGTXD2 RGREFCLK Vss RSV25 DED15 DSDDQM1 DED8 DED6 DSDDQMO DED2 DSDRAS VrersstL DBAO B Vss VrerHst RGTXDi RGMDCLK DVppis RSV24 DED12 DVpp18 4 DED5 DVppis DED1 DSDWE A eit DEA13 A DVppis RGTXD3 RGTXDO RGMDIO PLLV2 RSV21 DED13 Vss Dee DED4 Vss DEDO AVDLLi _DDR2_ DEA12 GATEO CLKOUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Figure 2 5 C6454 Pin Map Bottom View Quadrant Submit Documentation Feedback Device Overview 17 PRODUCT PREVIEW Mal aad TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 2 6 Signal Groups Description 2 Clock PLL1 SYSCLK4 GP 1 and Reset and PLLV1 PLL Controller Interrupts CLKIN2 PLLV2 Clock PLL2 TMS TDO TDI TCK TRST Reserved IEEE Standard EMUO 1149 1 EMU1 JTAG Emulation Peripheral Enable Disable Control Status 6 INSTRUMENTS www ti com RESETSTAT RESET NMI POR A This pin functions as GP 1 by default For more details see the Device Configuration section of this document Figure 2 6 CPU and Peripheral Signals 18 Device Overview Submit Documentation Feedback
282. static powerdown state 101 PCI is in the enable in progress state Others Reserved 62 Device Configuration Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com 3 4 5 EMAC Configuration Register EMACCFG Description 5320 6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 The EMAC Configuration Register EMACCFG is used to assert and deassert the reset of the Reduced Media Independent Interface RMII logic of the EMAC For more details on how to use this register see Section 7 14 Ethernet MAC EMAC 31 24 Reserved R W 0 23 19 18 17 16 Reserved Reserved R W 0001b R W 1 R W 0 15 0 Reserved R W 0 LEGEND R W Read Write R Read only n value after reset Figure 3 8 EMAC Configuration Register EMACCFG 0x02AC 0020 Table 3 11 EMAC Configuration Register EMACCFG Field Descriptions Bit Field Value Description 31 19 Reserved Reserved Writes to this register must keep the default values of these bits 18 RMII RMII reset bit This bit is used to reset the RMII logic of the EMAC 0 RMII logic reset is released 1 RMII logic reset is asserted 17 0 Reserved Reserved Writes to this register must keep this bit as 0 Submit Documentation Feedback Device Configuration 63 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed
283. t I and the low high level input voltages V and Vip for the C6454 device see Section 6 3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature To determine which pins on the C6454 device include internal pullup pulldown resistors see Table 2 3 Terminal Functions 68 Device Configuration Submit Documentation Feedback K Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 3 8 Configuration Examples Figure 3 12 and Figure 3 13 illustrate examples of peripheral selections options that are configurable on the C6454 device 32 HD 31 0 HRDY HINT HCNTLO HCNTL1 HHWIL HAS HR W HCS HDS1 HDS2 AED 63 0 AECLKIN AARDY AHOLD 22 3 ACE 3 0 ABE 7 0 AECLKOUT ASDCKE AHOLDA ABUSREQ ASADS ASRE GP 15 12 2 1 AAOE ASOE AAWE ASWE CLKIN1 PLLV1 ED 31 0 DEA 21 2 DCE 1 0 DBE 3 0 DDRCLK DDRCLK SYSGLIA Controller DSDCKE DDQS 5005 DSDCAS DSDRAS DSDWE PLL2 McBSP1 and PLL2 CLKIN2 PLLV2 Controller CLKRO FSR0 DRO CLKS0 TINP1L FSX0 CLKX0 McBSP0 TIMER1 TOUTIL 7 0 MRXER MRXDV MCOL lt TINPO MCRS MTCLK MRCLK TIMERO Taita MTXD 7 0 MTXEN SCL MDIO MDCLK SDA Shading denotes a peripheral module not available for this configuration DEVSTAT Register 0x0061 8161 PCI EN 0 PCI disabled default ABA1 EMIFA EN 1 EMIFA enabl
284. t further writes of 1 can initiate the GO operation 142 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 7 8 3 3 PLL Controller Status Register The PLL controller status register PLLSTAT shows the PLL controller status PLLSTAT is shown in Figure 7 26 and described in Table 7 35 31 16 R 0 15 1 9 R 0 R 0 LEGEND R W Read Write Read only n value after reset Figure 7 26 PLL Controller Status Register PLLSTAT Hex Address 029C 013C Table 7 35 PLL Controller Status Register PLLSTAT Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 GOSTAT GO operation status 0 Go operation is not in progress SYSCLK divide ratios are not being changed 1 GO operation is in progress SYSCLK divide ratios are being changed 7 8 3 4 PLL Controller Clock Align Control Register The PLL controller clock align control register ALNCTL is shown in Figure 7 18 and described in Table 7 26 31 16 Reserved R 0 15 1 0 Reserved ALN1 R 0 R W 1 LEGEND R W Read Write Read only n value after reset Figure 7 27 PLL Controller Clock Align Control Register ALNCTL He
285. t www ti com dsppower CVpp12 5 y power supplies Figure 7 5 Power Supply Sequence Table 7 2 Timing Requirements for Power Supply Sequence 720 850 NO 1000 UNIT MIN MAX 1 lsupvppas cvbp12 Setup time DVppg3 supply stable before CVpp12 supply stable 0 5 200 ms 2 lsucvbpizALLsUP Setup time CVpp12 supply stable before all other supplies stable 0 200 ms 7 3 2 Power Supply Decoupling In order to properly decouple the supply planes from system noise place as many capacitors caps as possible close to the DSP These caps need to be close to the DSP no more than 1 25 cm maximum distance to be effective Physically smaller caps are better such as 0402 but need to be evaluated from a yield manufacturing point of view Parasitic inductance limits the effectiveness of the decoupling capacitors therefore physically smaller capacitors should be used while maintaining the largest available capacitance value As with the selection of any component verification of capacitor availability over the product s production lifetime should be considered 7 3 3 Power Down Operation 96 One of the power goals for the C6454 is to reduce power dissipation due to unused peripherals There are different ways to power down peripherals on the C6454 device Some peripherals can be statically powered down at device reset through the device configuration pins see Section 3 1 Device Configuration at D
286. ta manual specifications and I O buffer information specification IBIS models For the C6454 DDR2 memory bus the approach is to specify compatible DDR2 devices and provide the printed circuit board PCB solution and guidelines directly to the user Texas Instruments has performed the simulation and system characterization to ensure all DDR2 interface timings in this solution are met The complete DDR2 system solution is documented in the Implementing DDR2 PCB Layout on the TMS320C6454 application report literature number SPRAAA7 only supports designs that follow the board design guidelines outlined in the SPRAAA7 application report DDR2 Memory Controller pins must be enabled by setting the DDR2 EN configuration pin ABAO high during device reset For more details see Section 3 1 Device Configuration at Device Heset The ODT 1 0 pins of the memory controller must be left unconnected The ODT pins on the DDR2 memory device s must be connected to ground The DDR2 memory controller on the C6454 device supports the following memory topologies e A 32 bit wide configuration interfacing to two 16 bit wide DDR2 SDRAM devices A 16 bit wide configuration interfacing to a single 16 bit wide DDR2 SDRAM device A race condition may exist when certain masters write data to the DDR2 memory controller For example if master A passes a software message via a buffer in external memory and does not wait for indication that the wri
287. tatus Register 02C8 180C LINK MDIO PHY Link Status Register 02C8 1810 LINKINTRAW MDIO Link Status Change Interrupt Unmasked Register 02C8 1814 LINKINTMASKED MDIO Link Status Change Interrupt Masked Register 02C8 1818 02C8 181C Reserved 02C8 1820 USERINTRAW MDIO User Command Complete Interrupt Unmasked Register 02C8 1824 USERINTMASKED MDIO User Command Complete Interrupt Masked Register 02C8 1828 USERINTMASKSET MDIO User Command Complete Interrupt Mask Set Register 02C8 182C USERINTMASKCLEAR MDIO User Command Complete Interrupt Mask Clear Register 02C8 1830 02C8 187C Reserved 02C8 1880 USERACCESSO MDIO User Access Register 0 02C8 1884 USERPHYSELO MDIO User PHY Select Register 0 02C8 1888 USERACCESS1 MDIO User Access Register 1 02C8 188C USERPHYSEL1 MDIO User PHY Select Register 1 02C8 1890 02C8 1FFF Reserved Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 203 PRODUCT PREVIEW Mal aad TMS320C6454 49 Texas Fixed Point Digital Signal Processor INSTRUMENTS www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 14 4 3 Electrical Data Timing Table 7 90 Timing Requirements for MDIO Input R G MII see Figure 7 71 720 850 NO 1000 UNIT MIN MAX 1 c MDCLK Cycle time MDCLK 400 n 28 twMDCLK Pulse duration MDCLK high 180 s 2b wMDCLK Pulse duration MDCLK low 180 m 3 li MDCLK Transition ti
288. tching Characteristics Over Recommended Operating Conditions for McBSP see Figure 7 52 continued 720 850 NO PARAMETER 1000 UNIT MIN MAX 3 tw CKRX Pulse duration CLKR X high or CLKR X low CLKR X int C 10 C 10 ns ta CKRH FRV Delay time CLKR high to internal FSR valid CLKR int 2 1 3 3 ns 22 CLKX int AF 3 9 la CKXH FXV Delay time CLKX high to internal FSX valid CLKX ext 17 9 ns 12 Disable time DX high impedance following CLKX int 3 9 4 ns dis CKXH DXHZ last data bit from CLKX high CLKX ext 21 9 ect CLKX int 3 9 D18 4 D28 CLKX ext 2 1 D18 S Delay time FSX high to DX valid FSX int 2 3 D1 9 5 6 D2 9 14 ta FxH Dxv ONLY applies when in data ns 9 9 delay 0 XDATDLY 00b mode FSX ext 1 94 DI 9 D2 7 C HorL S sample rate generator input clock 6P if CLKSM 1 P 1 CPU clock frequency S sample rate generator input clock P_clks if CLKSM 0 P_clks CLKS period H CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even H CLKGDV 1 2 S if CLKGDV is odd L CLKX low pulse width CLKGDV 2 S if CLKGDV is even L CLKGDV 1 2 S if CLKGDV is odd CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit see 4 above 8 Extra delay from CLKX high to DX valid applies only to the first data bit of a device if and only if DXENA
289. te completes when master B attempts to read the software message then the master B read may bypass the master A write and thus master B may read stale data and therefore receive an incorrect message Some master peripherals e g EDMAS transfer controllers will always wait for the write to complete before signaling an interrupt to the system thus avoiding this race condition For masters that do not have hardware guarantee of write read ordering it may be necessary to guarantee data ordering via software If master A does not wait for indication that a write is complete it must perform the following workaround 1 Perform the required write 2 Perform a dummy write to the DDR2 memory controller module ID and revision register 3 Perform a dummy read to the DDR2 memory controller module ID and revision register 4 Indicate to master B that the data is ready to be read after completion of the read in step 3 The completion of the read in step 3 ensures that the previous write was done Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 147 PRODUCT PREVIEW M3l aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 9 2 DDR2 Memory Controller Peripheral Register Description s Table 7 40 DDR2 Memory Controller Registers HEX ADDRESS RANGE ACRONYM REGI
290. ter 028C 000C RCRO McBSPO Receive Control Register 028C 0010 XCRO McBSPO0 Transmit Control Register 028C 0014 SRGRO McBSPO0 Sample Rate Generator register 028C 0018 MCRO McBSPO0 Multichannel Control Register McBSPO0 Enhanced Receive Channel Enable 0280 0016 RCERE00 Register 0 Partition A B McBSP0 Enhanced Transmit Channel Enable 0287 0020 Register 0 Partition 028 0024 PCRO McBSPO Pin Control Register McBSPO0 Enhanced Receive Channel Enable 028C 0028 0 Register 1 Partition C D McBSPO0 Enhanced Transmit Channel Enable 028 002C XCERE10 Register 1 Partition C D McBSP0 Enhanced Receive Channel Enable 028 0030 RCERE20 Register 2 Partition E F McBSPO0 Enhanced Transmit Channel Enable 02850034 XCERE20 Register 2 Partition E F McBSPO0 Enhanced Receive Channel Enable 0286 0038 RCERE30 Register 3 Partition G H McBSP0 Enhanced Transmit Channel Enable 028C 003 XCERE30 Register 3 Partition G H 028C 0040 028F FFFF Reserved 178 C64x Peripheral Information and Electrical Specifications Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com 5320 6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 58 McBSP 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS The CPU and EDMA controller can only read 0290 0000 DRR1 McBSP1 Data Receive Register via Config
291. the or by other system masters Note that EDMA or IDMA transfers programmed by the CPU count as global accesses The CPU and the system masters on the C6454 device are all assigned a privilege ID of 0 Therefore it is only possible to specify whether memory pages are locally or globally accessible The AIDO and LOCAL bits of the memory protection page attribute registers specify the memory page protection scheme see Table 5 1 Table 5 1 Available Memory Page Protection Schemes AIDO Bit LOCAL Bit Description 0 0 No access to memory page is permitted 0 1 Only direct access by CPU is permitted 1 0 Only accesses by system masters and IDMA are permitted includes EDMA and IDMA accesses initiated by the CPU 1 1 All accesses permitted For more information on memory protection for L1D L1P and L2 see the TMS320C64x Megamodule Reference Guide literature number SPRUS71 5 3 Bandwidth Management 80 When multiple requestors contend for a single C64x Megamodule resource the conflict is solved by granting access to the highest priority requestor The following four resources are managed by the Bandwidth Management control hardware Level 1 Program L1P SRAM Cache e Level 1 Data L1D SRAM Cache e Level 2 L2 SRAM Cache e Memory mapped registers configuration bus The priority level for operations initiated within the C64x Megamodule e g CPU initiated transfers user programmed cache c
292. the C6454 is used to interface to JESD79D 2A standard compliant DDR2 SDRAM devices The DDR2 external bus only interfaces to DDR2 SDRAM devices it does not share the bus with any other types of peripherals The decoupling of DDR2 memories from other devices both simplifies board design and provides I O concurrency from a second external memory interface EMIFA The internal data bus clock frequency and DDR2 bus clock frequency directly affect the maximum throughput of the DDR2 bus The clock frequency of the DDR2 bus is equal to the CLKIN2 frequency multiplied by 10 The internal data bus clock frequency of the DDR2 Memory Controller is fixed at a divide by three ratio of the CPU frequency The maximum DDR2 throughput is determined by the smaller of the two bus frequencies For example if the internal data bus frequency is 333 MHz CPU frequency is 1 GHz and the DDR2 bus frequency is 250 MHz CLKIN2 frequency is 25 MHz the maximum data rate achievable by the DDR2 memory controller is 2 0 Gbytes sec The DDR2 bus is designed to sustain a maximum throughput of up to 2 0 Gbytes sec at 533 2 data rate 250 MHz clock rate as long as data requests are pending in the DDR2 Memory Controller DDR2 Memory Controller Device Specific Information The approach to specifying interface timing for the DDR2 memory bus is different than on other interfaces such as EMIF HPI and McBSP For these other interfaces the device timing was specified in terms of da
293. the TMS320C645x Digital Signal Processor DSP The 2 provides an interface between the TMS320C645x device and other devices compliant with Philips Semiconductors Inter IC bus I2C bus specification version 2 1 and connected by way of an I2C bus This document assumes the reader is familiar with the I2C bus specification TMS320C645x DSP Peripheral Component Interconnect PCI User s Guide This document describes the peripheral component interconnect PCI port in TMS320C645x devices See the PCI Specification revision 2 3 for details on the PCI interface TMS320C645x DSP Software Programmable Phase Locked Loop PLL Controller User s Guide This document describes the operation of the software programmable phase locked loop PLL controller in the TMS320C645x digital signal processors DSPs The PLL controller offers flexibility and convenience by way of software configurable multipliers and dividers to modify the input signal internally The resulting clock outputs are passed to the TMS320C645x DSP core peripherals and other modules inside the TMS320C645x DSP TMS320C645x DSP 64 Bit Timer User s Guide This document provides an overview of the 64 bit timer in the TMS320C645x DSP The timer can be configured as a general purpose 64 bit timer dual general purpose 32 bit timers or a watchdog timer When configured as a dual 32 bit timers each half can operate in conjunction chain mode or independently unchained mode of each other Su
294. thms that do searching and sorting Finally to increase data packing and unpacking throughput the S unit allows sustained high performance for the quad 8 bit 16 bit and dual 16 bit instructions Unpack instructions prepare 8 bit data for parallel 16 bit operations Pack instructions return parallel results to output precision including saturation support Submit Documentation Feedback Device Overview 7 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 www ti com Other new features include SPLOOP A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel The SPLOOP buffer reduces the code size associated with software pipelining Furthermore loops in the SPLOOP buffer are fully interruptible Compact Instructions The native instruction size for the C6000 devices is 32 bits Many common instructions such as MPY AND OR ADD and SUB can be expressed as 16 bits if the C64x compiler can restrict the code to use certain registers in the register file This compression is performed by the code generation tools Instruction Set Enhancements As noted above there are new instructions such as 32 bit multiplications complex multiplications packing sorting bit manipulation and 32 bit Galois field multiplication Exception Handling I
295. timulus from a host or global controller More information on the power down features of the C64x Megamodule can be found in the TMS320C64x Megamodule Reference Guide literature number SPRU871 Preserving Boundary Scan Functionality on RGMII and DDR2 Memory Pins When the RGMII mode of the EMAC is not used the DVppis DVppismon RSV13 RSV14 pins can be connected directly to ground Vss to save power However this will prevent boundary scan from functioning on the RGMII pins of the EMAC To preserve boundary scan functionality on the RGMII pins DVppis RSV14 and RSV13 should be connected as follows DVpp 5 and DVppismon connect these pins to the 1 8 V I O supply VeerHst connect to a voltage of DVpp 4 2 The DVpp 4 2 voltage can be generated directly from the DVppig supply using two 1 kQ resistors to form a resistor divider circuit e RSV13 connect this pin to ground Vss via a 200 0 resistor e RSV14 connect this pin to the 1 8 V I O supply DVpp ig via a 200 0 resistor Similarly when the DDR2 Memory Controller is not used the Varrsst_ RSV11 and RSV12 pins be connected directly to ground Vss to save power However this will prevent boundary scan from functioning on the DDR2 Memory Controller pins To preserve boundary scan functionality on the DDR2 Memory Controller pins Vaersst_ RSV11 and RSV12 should be connected as follows Vpersst_ c
296. tio Change Status Register DCHANGE Hex Address 029C 0144 Table 7 37 PLLDIV Divider Ratio Change Status Register DCHANGE Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 SYS1 SYSCLK1 divide ratio has been modified SYSCLK1 ratio will be modified during GO operation 0 SYSCLK1 ratio has not been modified When GOSET is set SYSCLK1 will not be affected 1 SYSCLK1 ratio has been modified When GOSET is set SYSCLK1 will change to the new ratio 144 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 8 3 6 SYSCLK Status Register The SYSCLK status register SYSTAT shows the status of the system clock SYSCLK1 SYSTAT is shown in Figure 7 29 and described in Table 7 38 31 16 0 15 1 0 SYSION R 0 1 LEGEND R W Read Write Read only n value after reset Figure 7 29 SYSCLK Status Register Hex Address 029C 0150 Table 7 38 SYSCLK Status Register Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 SYS1ON SYSCLK1 on status 0 SYSCLK1 is gated SYSCLK
297. trical Specifications Submit Documentation Feedback Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 8 1 PLL2 Controller Device Specific Information 7 8 1 1 Internal Clocks and Maximum Operating Frequencies As shown in Figure 7 23 the output of PLL2 PLLOUT is divided by 2 and directly fed to the DDR2 memory controller This clock is used by the DDR2 memory controller to generate DDR2CLKOUT and DDR2CLKOUT Note that internally the data bus interface of the DDR2 memory controller is clocked by SYSCLK of the PLL1 controller The PLLOUT 2 clock is also fed back into the PLL2 controller where it becomes SYSREFCLK Divider D1 of the PLL2 controller generates SYSCLK1 for the Ethernet media access controller EMAC The EMAC uses SYSCLK1 to generate the necessary clock for each of its interfaces Divider D1 should be programmed to 2 mode default when using the Gigabit Media Independent Interface GMII mode and to 5 mode when using the Reduce Gigabit Media Independent Interface RGMII Divider D1 is software programmable and if necessary must be programmed after device reset to 5 when the RGMII mode of the EMAC is used Note that internally the data bus interface of the EMAC is clocked by SYSCLK3 of the PLL2 controller Note that there is a minimum and maximum operating frequency for PLLREF PLLOUT and SYSCLK1 The clock generator must not be configured to exceed any
298. trol 4K 02C8 0000 02C8 OFFF EMAC Control Module Registers 2K 02C8 1000 02C8 17FF MDIO Control Registers 2K 02C8 1800 02C8 1FFF EMAC Descriptor Memory 8K 02C8 2000 02C8 3FFF Reserved 496K 02C8 4000 2 FFFF Reserved 220M 0200 0000 OFFF FFFF Reserved 256M 1000 0000 1FFF FFFF 10 Device Overview Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 2 2 C6454 Memory Map Summary continued MEMORY BLOCK DESCRIPTION BLOCK SIZE BYTES HEX ADDRESS RANGE Reserved 256M 2000 0000 2FFF FFFF McBSP 0 Data 256 3000 0000 3000 00FF Reserved 64M 256 3000 0100 33FF FFFF McBSP 1 Data 256 3400 0000 3400 OOFF Reserved 64M 256 3400 0100 37FF FFFF Reserved 2K 3C00 0000 3C00 07FF Reserved 16M 2K 3C00 0800 3CFF FFFF Reserved 48M 3D00 0000 3FFF FFFF PCI External Memory Space 256M 4000 0000 4FFF FFFF Reserved 256M 5000 0000 5FFF FFFF Reserved 256M 6000 0000 6FFF FFFF EMIFA EMIF64 Configuration Registers 128M 7000 0000 77FF FFFF DDR2 Memory Controller Configuration Registers 128M 7800 0000 7FFF FFFF Reserved 256M 8000 0000 8FFF FFFF Reserved 256M 9000 0000 9FFF FFFF EMIFA CE2 SBSRAM Async 8M A000 0000 A07F FFFF Reserved 256M 8M A080 0000 AFFF FFFF EMIFA 6 5
299. try Register 2 02A0 048C Q2E3 Event Queue 2 Entry Register 3 02A0 0490 Q2E4 Event Queue 2 Entry Register 4 02A0 0494 Q2E5 Event Queue 2 Entry Register 5 02A0 0498 Q2E6 Event Queue 2 Entry Register 6 02A0 049C Q2E7 Event Queue 2 Entry Register 7 02A0 04A0 Q2E8 Event Queue 2 Entry Register 8 02A0 04A4 Q2E9 Event Queue 2 Entry Register 9 02A0 04A8 Q2E10 Event Queue 2 Entry Register 10 02A0 04AC Q2E11 Event Queue 2 Entry Register 11 02A0 04B0 Q2E12 Event Queue 2 Entry Register 12 02A0 04B4 Q2E13 Event Queue 2 Entry Register 13 02A0 04B8 Q2E14 Event Queue 2 Entry Register 14 02A0 04BC Q2E15 Event Queue 2 Entry Register 15 02A0 04 0 Q3E0 Event Queue 3 Entry Register 0 02A0 04 4 Q3E1 Event Queue 3 Entry Register 1 02A0 04C8 Q3E2 Event Queue 3 Entry Register 2 02A0 04CC Q3E3 Event Queue 3 Entry Register 3 02A0 04D0 Q3E4 Event Queue 3 Entry Register 4 02A0 04D4 Q3E5 Event Queue 3 Entry Register 5 02A0 04D8 Q3E6 Event Queue 3 Entry Register 6 02A0 04DC Q3E7 Event Queue 3 Entry Register 7 02A0 04E0 Q3E8 Event Queue 3 Entry Register 8 02A0 04E4 Q3E9 Event Queue 3 Entry Register 9 02A0 04E8 Q3E10 Event Queue 3 Entry Register 10 02A0 04EC Q3E11 Event Queue 3 Entry Register 11 02A0 04F0 Q3E12 Event Queue 3 Entry Register 12 02A0 04F4 Q3E13 Event Queue 3 Entry Register 13 02A0 04F8 Q3E14 Event Queue 3 Entry Register 14 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 103 PRODUCT PREVIEW TMS320C6454
300. ts for EMAC MII and Receive 10 100 1000 Mbit s see Figure 7 62 720 850 NO 1000 UNIT 1000 Mbps 100 10 Mbps MIN MAX MIN MAX 1 Setup time receive selected signals valid before 2 8 tsu MRXD MRCLKH MRCLK high ns 2 Hold time receive selected signals valid after 8 th MRCLKH MRXD MRCLK high 0 ns 1 For Receive selected signals include MRXD 3 0 MRXDV and MRXER For Receive selected signals include MRXD 7 0 MRXDV and MRXER MRCLK Input cu CEN 1r m RN MRXD7 MRXDA GMII only SEED s SORA AAA AAA MRXDS MRXDO Figure 7 62 EMAC Receive Interface Timing MII and GMII Operation mM MRXDV MRXER Inputs 196 64 Peripheral Information and Electrical Specifications Submit Documentation Feedback TMS320C6454 Fixed Point Digital Signal Processor SPRS311A APRIL 2006 REVISED DECEMBER 2006 4 6 INSTRUMENTS www ti com Table 7 79 Switching Characteristics Over Recommended Operating Conditions for EMAC and GMII Transmit 10 100 Mbit s see Figure 7 63 720 850 NO PARAMETER on UNIT 100 10 Mbps MIN MAX 1 ta MTCLKH MTXD Delay time MTCLK high to transmit selected signals valid 5 25 ns 1 For Transmit selected signals include MTXD 3 0 and MTXEN For Transmit selected signals include GMTXD 7 0 and MTXEN 1 MTCLK Input SF IF E MT
301. tup time requirement 11 Data route delay AECLKOUT Output from DSP t 1 aa N Z N Input to Ext Devi Input to External Device 2 Control Signals 3 EN Output from DSP 4 pots Control Signals 6 Input to External Device Lo 7 8 34 Data Signals B Output from External Device 9 qO 1 Data Signals B Input to DSP gt A Control signals include data for Writes Data signals are generated during Reads from an external device Figure 7 4 Board Level Input Output Timings Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 95 PRODUCT PREVIEW M3al aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 www ti com 7 2 Recommended Clock and Control Signal Transition Behavior All clocks and control signals must transition between Vj and V or between and Vip in a monotonic manner 7 3 Power Supplies 7 3 1 Power Supply Sequencing TI recommends the power supply sequence shown in Figure 7 5 After the DVpp33 supply is stable the remaining power supplies can be powered up at the same time as CVpp as long as their supply voltage never exceeds the CVpp voltage during powerup Some power supply devices include features that facilitate power sequencing for example Auto Track or Slow Start Enable features For more information visi
302. ty of functions e Conversion between configuration bus and data bus e Width conversion between peripheral bus width and SCR bus width e Frequency conversion between peripheral bus frequency and SCR bus frequency For example the EMIFA and DDR2 memory controller require a bridge to convert their 64 bit data bus interface into a 128 bit interface so that they can connect to the data SCR Note that some peripherals can be accessed through the data SCR and also through the configuration SCR Submit Documentation Feedback System Interconnect 71 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 4 2 Data Switch Fabric Connections Figure 4 1 shows the connection between slaves and masters through the data switched central resource SCR Masters are shown on the right and slaves on the left The data SCR connects masters to slaves via 128 bit data buses running at a SYSCLK2 frequency SYSCLK is supplied by the PLL1 controller and is fixed at a frequency equal to the CPU frequency divided by 3 Some peripherals like PCI and the C64x Megamodule have both slave and master ports Note that each EDMAS transfer controller has an independent connection to the data SCR Note that masters can access the configuration SCR through the data SCR The configuration SCR is described in Section 4 3 Not all masters on the C6454 DSP may c
303. ucture WI The C64x devices are upward code compatible from previous devices that are part of the C6000 DSP platform The C6454 offers a lower cost pin compatible migration path for C6455 customers who don t need the 2MB of the C6455 or the high speed interconnect provided by Serial RapidlO The C6454 also provides an excellent migration path for existing C6414 6415 6416 customers who require C6454 advanced peripherals DDR2 at 533 MHz provides 2x performance boost over older SDRAM interface gigabit Ethernet provides low cost high performance ubiquitous packet interface and 66 MHz PCI revision 2 3 complaint provides legacy high bandwidth interconnect Based on 90 nm process technology and with performance of up to 8000 million instructions per second MIPS or 8000 16 bit MMACs per cycle at a clock rate of 1 GHz the C6454 device offers cost effective solutions to high performance DSP programming challenges The C6454 DSP possesses the operational flexibility of high speed controllers and the numerical capability of array processors 2 TMS320C6454 Fixed Point Digital Signal Processor Submit Documentation Feedback Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 REVISED DECEMBER 2006 The C64x DSP core employs eight functional units two register files and two data paths Like the earlier C6000 devices two of these eight functional units are multipliers or M units Each C
304. ued SIGNAL TYPE IPD IPU DESCRIPTION NAME NO EMIFA 64 BIT ADDRESS AEA19 BOOTMODE3 N25 EMIFA external address word address O Z Controls initialization of the DSP modes at reset I via pullup pulldown resistors RESTSIBOGTMERIEE 26 For more detailed information see Section 3 Device Configuration AEA17 BOOTMODE1 L25 Note If a configuration pin must be routed out from the device the internal AEA16 BOOTMODEO P26 0 2 IPD pullup pulldown IPU IPD resistor should not be relied upon TI recommends the use of an external pullup pulldown resistor AEA15 AECLKIN_SEL P27 e Boot mode device boot mode configurations 3 0 Note AEA14 HPI WIDTH R25 the peripheral must be enabled to use the particular boot mode AEA13 LENDIAN R27 O Z IPU AEA 19 16 12 R28 0000 No boot default mode 0001 Host boot HPI 0010 Reserved 0011 Reserved 0100 EMIFA 8 bit ROM boot 0101 Master 2 boot 0110 Slave 2 boot 0111 Host boot PCI 1000 thru 1111 Reserved For more detailed information on the boot modes see Section 2 4 Boot Sequence CFGGP 2 0 pins must be set to 000b during reset for proper operation of the PCI boot mode e EMIFA input clock source select Clock mode select for EMIFA AECLKIN SEL AEA15 0 AECLKIN default mode AEA11 T25 0 2 IPD 1 SYSCLK4 CPU x Clock Rate The SYSCLK4 clock rate is software selectable via
305. umber SPRZ234 Figure 5 5 Megamodule Revision ID Register MM REVID Hex Address 0181 2000h Table 5 3 Megamodule Revision ID Register MM REVID Field Descriptions Bit Field Value Description 31 16 VERSION 1h Version of the C64x Megamodule implemented on the device This field is always read as 1h 15 0 REVISION Revision of the C64x Megamodule version implemented on the device The C64x Megamodule revision is dependant on the silicon revision being used For more information see the TMS320C6455 54 Digital Signal Processor Silicon Errata literature number SPRZ234 82 C64x4 Megamodule Submit Documentation Feedback 33 Texas TMS320C6454 INSTRUMENTS Fixed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 5 7 C64x Megamodule Register Description s Table 5 4 Megamodule Interrupt Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 0180 0000 EVTFLAGO Event Flag Register 0 Events 31 0 0180 0004 EVTFLAG1 Event Flag Register 1 0180 0008 EVTFLAG2 Event Flag Register 2 0180 000C EVTFLAG3 Event Flag Register 3 0180 0010 0180 001C 2 Reserved 0180 0020 EVTSETO Event Set Register 0 Events 31 0 0180 0024 EVTSET1 Event Set Register 1 0180 0028 EVTSET2 Event Set Register 2 0180 002C EVTSET3 Event Set Register 3 0180 003
306. uration Bus this register they cannot write to it 3400 0000 DRR1 McBSP1 Data Receive Register via EDMA bus 0290 0004 DXR1 McBSP1 Data Transmit Register via configuration bus 3400 0010 DXR1 McBSP1 Data Transmit Register via EDMA bus 0290 0008 SPCR1 serial port control register 0290 000C RCR1 McBSP1 Receive Control Register 0290 0010 XCR1 McBSP1 Transmit Control Register 0290 0014 SRGR1 McBSP1 sample rate generator register 0290 0018 MCR1 McBSP1 multichannel control register McBSP1 Enhanced Receive Channel Enable 0290 001C 1 Register 0 Partition McBSP1 Enhanced Transmit Channel Enable 0290 0020 1 Register 0 Partition 0290 0024 PCR1 McBSP1 Pin Control Register McBSP1 Enhanced Receive Channel Enable 0290 0028 ROERE11 Register 1 Partition C D McBSP1 Enhanced Transmit Channel Enable 0290 002 JOEREN Register 1 Partition C D McBSP1 Enhanced Receive Channel Enable 0290 0030 RCERE21 Register 2 Partition E F McBSP1 Enhanced Transmit Channel Enable 0230 0034 XCERE21 Register 2 Partition E F McBSP1 Enhanced Receive Channel Enable 0290 0038 1 Register 3 Partition G H 0290 003C XCERE31 McBSP1 Enhanced Transmit Channel Enable Register 3 Partition G H 0290 0040 0293 FFFF Reserved Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 179 PRODUCT PREVIEW Mal aad TMS32006454 3 TEXAS
307. urce Minimum AECLKIN times are based on internal logic speed the maximum useable speed of the EMIF may be lower due to AC timing requirements 4 This timing only applies when AECLKIN is used for EMIFA m 8 5 FN NSS k 3 p D 4 gt le Figure 7 31 AECLKIN Timing for EMIFA Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 151 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 idi Table 7 43 Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the EMIFA Module see Figure 7 32 720 850 NO PARAMETER 1000 UNIT MIN MAX 1 c EKO Cycle time AECLKOUT E 0 7 0 7 ns 2 tw EKOH Pulse duration AECLKOUT high EH 0 7 EH 0 7 ns 3 tw EKOL Pulse duration AECLKOUT low EL 0 7 EL 4 0 7 ns 4 Transition time AECLKOUT 1 ns 5 ta EKIH EKOH Delay time AECLKIN high to AECLKOUT high 1 8 ns 6 la EKIL EKOL Delay time AECLKIN low to AECLKOUT low 1 8 ns 1 E the EMIF input clock AECLKIN or SYSCLK4 period in ns for EMIFA 2 The reference points for the rise and fall transitions are measured at and Voy MIN 3 EHis the high period of E input clock period ns and EL is the low period of E input clock period
308. ure also includes a suffix with the device family name This suffix indicates the package type for example ZTZ the temperature range for example blank is the default commercial temperature range and the device speed range in megahertz for example blank is 1000 MHz 1 GHz Figure 2 12 provides a legend for reading the complete device name for any TMS320C64x DSP generation member For device part numbers and further ordering information for TMS320C6454 in the ZTZ GTZ package type see the TI website www ti com or contact your TI sales representative TMX 320 C6454 717 PREFIX m DEVICE SPEED RANGE TMX Experimental device 7 720 MHz TMS Qualified device 8 850 MHz Blank 1 GHz DEVICE FAMILY TEMPERATURE RANGE 320 TMS320 DSP family Blank 0 C to 90 C default commercial temperature DEVICE PACKAGE TYPE A C64x DSP ZTZ 697 pin plastic BGA with Pb Free solder balls C6454 GTZ 697 pin plastic BGA with Pb ed solder balls A BGA Ball Grid Array Figure 2 12 TMS320C64x DSP Device Nomenclature including the TMS320C6454 DSP 2 8 2 2 Documentation Support The following documents describe the TMS320C6454 Fixed Point Digital Signal Processor Copies of these documents are available on the Internet at www ti com Tip Enter the literature number in the search box provided at www ti com The current documentation that describes the TMS320C6454 related peripherals and other technical
309. ved Table 7 72 EMAC Statistics Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 02C8 0200 RXGOODFRAMES Good Receive Frames Register Broadcast Receive Frames Register 0208 0204 RXBCASTERAMES Total number of good broadcast frames received Multicast Receive Frames Register 0208 0209 RXMCASTFRAMES Total number of good multicast frames received 02C8 020C RXPAUSEFRAMES Pause Receive Frames Register Receive CRC Errors Register Total number of frames received with 02C8 0210 RXCRCERRORS CRC errors Receive Alignment Code Errors Register RXALIGNCODEERRORS Total number of frames received with alignment code errors Receive Oversized Frames Register 0208 0218 RXOVERSIZED Total number of oversized frames received Receive Jabber Frames Register 02680216 RAJABBER Total number of jabber frames received Receive Undersized Frames Register 0208 0220 RXUNDERSIZED Total number of undersized frames received 02C8 0224 RXFRAGMENTS Receive Frame Fragments Register Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 193 PRODUCT PREVIEW Mal aad TMS320C6454 X3 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 Table 7 72 EMAC Statistics Registers continued HEX ADDRESS RANGE ACRONYM REGISTER NA
310. vice has been announced but is not in production Samples may or may not be available OBSOLETE has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free ROHS Pb Free ROHS Exempt or Green RoHS amp no Sb Br please check http Avww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder tem
311. w to DX valid 12P 2 24 17 ns 1 P 1 CPU clock frequency in ns For example when running parts at 1000 MHz use P 1 ns 2 For all SPI Slave modes CLKG is programmed as 1 6 of the CPU clock by setting CLKSM CLKGDV 1 3 S Sample rate generator input clock 6P if CLKSM 1 P 1 CPU clock frequency S Sample rate generator input clock P_clks if CLKSM 0 P_clks CLKS period T CLKX period 1 CLKGDV S CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd L CLKX low pulse width CLKGDV 2 S if CLKGDV is even L CLKGDV 1 2 S if CLKGDV is odd 4 FSRP FSXP 1 As a SPI Master FSX is inverted to provide active low slave enable output As a Slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for Master McBSP CLKXM CLKRM FSXM FSRM 0 for Slave McBSP 5 FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master clock CLKX CLKX f k f E V 9 28 FSX y 7 8 L 6 k 3 _ Bio Bit n 1 2 X 5 X n4 X 4 5 DR 0 __ 1 n2 X m3 X m4 X Figure 7 54 McBSP Timing as SPI Master or Slave CLKSTP 10b CLKXP 0 Submit Documentation Feedback C64x Peripheral Information and El
312. with pins internal pullup resistor 50 100 400 V Vss to DVppss pins with DC 1 Vss 0033 d E DC internal pulldown resistor 400 100 30 uA 12C pins 0 1 DVpps3 lt Vis 0 9DVpp33 10 10 uA PCl capable pins 4 1000 1000 uA RGMII pins 0 4 V AECLKOUT CLKR1 GP O0 CLKX1 GP 3 _ SYSCLKA GP 1 8 mA EMU 18 0 CLKR0 CLKX0 EMIF pins except AECLKOUT NMI TOUTOL TINPOL TOUTIL TINP1L PCI EN High level EMAC capable pins loH Da current except RGMII pins 4 mA RESETSTAT McBSP capable pins except CLKR1 GP 0 CLKX1 GP 3 CLKRO CLKXO GP 7 4 and TDO PCI capable pins 0 5 mA RGMII pins 8 mA DDR2 memory controller pins mA For test conditions shown as MIN or NOM use the appropriate value specified in the recommended operating conditions table These rated numbers are from the PC Local Bus Specification version 2 3 The DC specification and AC specifications are defined in Table 4 3 and Table 4 4 respectively of the PC Local Bus Specification applies to input only pins and bi directional pins For input only pins indicates the input leakage current For bi directional pins includes input leakage current and off state hi Z output leakage current PCI input leakage currents include Hi Z output leakage for all bidirectional buffers with 3 state outputs Device Operating Conditions Submit Documentation Feedback K Texas TMS320C6454 INSTRUMENTS Fi
313. x Address 029C 0140 Table 7 36 PLL Controller Clock Align Control Register ALNCTL Field Descriptions Bit Field Value Description 31 1 Reserved 0 Reserved The reserved bit location is always read as 0 A value written to this field has no effect 0 ALN1 SYSCLK1 alignment Do not change the default values of these fields 0 Do not align SYSCLK1 during GO operation If SYS1 in DCHANGE is set to 1 SYSCLK1 switches to the new ratio immediately after the GOSET bit in PLLCMD is set 1 Align SYSCLK1 when the GOSET bit in PLLCMD is set The SYSCLK1 ratio is set to the ratio programmed in the RATIO bit in PLLDIV1 Submit Documentation Feedback C64x Peripheral Information and Electrical Specifications 143 PRODUCT PREVIEW Mal aad TMS320C6454 49 Texas Fixed Point Digital Signal Processor INSTRUMENTS SPRS311A APRIL 2006 REVISED DECEMBER 2006 7 8 3 5 PLLDIV Ratio Change Status Register Whenever a different ratio is written to the PLLDIV1 register the PLLCTRL flags the change in the DCHANGE status register During the GO operation the PLL controller will only change the divide ratio SYSCLK1 if SYS1 DCHANGE is 1 The PLLDIV divider ratio change status register is shown in Figure 7 28 and described in Table 7 37 31 16 Reserved R 0 15 1 0 Reserved SYS1 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Figure 7 28 PLLDIV Divider Ra
314. xed Point Digital Signal Processor www ti com SPRS311A APRIL 2006 C REVISED DECEMBER 2006 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature Unless Otherwise Noted continued PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AECLKOUT CLKR1 GP 0 CLKX1 GP 3 SYSCLKA GP 1 B MA EMU 18 0 CLKRO CLKXO EMIF pins except AECLKOUT NMI TOUTOL TINPOL TOUTP1L TINP1L PCI EN Low level output EMAC capable pins OL current DC except RGMII pins 4 mA RESETSTAT McBSP capable pins except CLKR1 GP 0 CLKX1 GP 3 CLKRO CLKX0 GP 7 4 and TDO PCl capable pins 15 mA RGMII pins 8 mA DDR2 memory 13 4 mA controller pins Off state output 5 2 loz current DC 3 3 V pins Vo DVpps33 or 0 V 20 20 uA CVpp 1 25 V CPU frequency 1000 MHz Loe CVpp 1 2 V 6 DD Pcop Core supply power CPU frequency 850 MHz 1 30 w 1 2 V CPU frequency 720 MHz TB DVppss 3 3 V DVppie 1 8 V PLLV1 2 11 0 54 AVpiio 1 8 V CPU frequency 1000 MHz DVppss 3 3 V Vopie 1 8 V Pppp IO supply power 6 PLLV1 PLLV2 AVpLLi 0 53 AVput2 1 8 V CPU frequency 850 MHz DVppss 3 3 V DVppie 1 8 V PLLV1 PLLV2 AVptui 0 52 w AVput2 1 8 V CPU frequency 720 MHz Input capacitance 10 pF Co Output capacitance 10 pF 5 loz applies to

Texas Instruments TMS320C6454 User's Manual

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