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Texas Instruments TMS320C6202 User's Manual

1. 21 11 16 20 22 T Input Output Z High Impedance S Supply Voltage GND Ground 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 21 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 development support Texas Instruments offers an extensive line of development tools for the C6200 generation of DSPs including tools to evaluate the performance of the processors generate code develop algorithm implementations and fully integrate and debug software and hardware modules The following products support development of C6200 based applications Software Development Tools Assembly optimizer Assembler Linker Simulator Optimizing ANSI C compiler Application algorithms C Assembly debugger and code profiler Hardware Development Tools Extended development system XDS emulator supports C6200 multiprocessor system debug EVM Evaluation Module The TMS320 DSP Development Support Reference Guide SPRU011 contains information about development support products for all TMS320 family member devices including documentation See this document for further information on TMS320 documentation or any TMS320 support products from Texas Instruments An additional document the TMS320 Third Party Support Reference Guide SPRU052 contains information about
2. Control Register File Figure 2 TMS320C62x CPU Data Paths vy TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 7 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 signal groups description CLKIN CLKOUT2 lt CLKOUT1 4 CLKMODE0 CLKMODE1T Clock PLL CLKMODE2T PLLV PLLG PLLF Reset and Interrupts TMS TDO 4 TDI TCK TRST EMU1 4 EMU0 4 IEEE Standard 1149 1 JTAG Emulation Power Down 5 4 4 Status RSV3 4 RSV2 Reserved RSV1 RSV0 Control Status T For GLS devices only Figure 3 CPU Signals 35 TEXAS INSTRUMENTS 3 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 ww w w w w vvvv RESET NMI EXT_INT7 EXT_INT6 EXT_INT5 EXT_INT4 IACK INUM3 INUM2 INUM1 INUMO DMAC3 DMAC2 DMAC1 DMACO PD 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 signal groups description continued Asynchronous ARE ED 31 0 Memory AOE Control AWE ARDY 2 CE1 SDA10 Space Select Synchronous SUAI GEO Memory SDRAS SSOE id SDWESSWE EA 21 2 Word Address HOLD BE2 En 1 Byte Enables
3. low CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns switching characteristics for timer outputsT see Figure 47 C6202 200 C6202 233 PARAMETER C6202 250 wrourH Pulse duration TOUT high tP clock 5 in ns For SHE when running parts at 250 MHz use P 4 ns 2 m Ne s TOUTx N Figure 47 Timer Timing 49 5 INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 69 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 DMAC TIMER POWER DOWN TIMING CONTINUED switching characteristics for power down outputst see Figure 48 C6202 200 C6202 233 PARAMETER v 250 1 tw PDH Pulse duration PD high 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns 1 gt Figure 48 Power Down Timing Ji TEXAS INSTRUMENTS 70 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 UNIT 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 JTAG TEST PORT TIMING timing requirements for JTAG test port see Figure 49 C6202 200 C6202 233 Be 250 UNIT ime TOK ues tsu TDIV TCKH Setup time TDI TMS TRST valid before high th TCKH TDIV _ Hold time TDI TMS TRST valid after
4. gt dais IN m 7 XDI31 0 11 12 N zh 14 6 xot xon XHOLDA T XW R input output polarity selected at boot tXBLAST output polarity is always active low 5 3 0 5 2 operates as byte enables XBE 3 0 during host port accesses Internal arbiter enabled External arbiter enabled ll This diagram illustrates XBOFF timing Bus arbitration timing is shown in Figure 38 and Figure 39 Figure 35 C6202 as Bus Master BOFF 49 5 INSTRUMENTS 54 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING timing requirements with external device as asynchronous bus mastert see Figure 36 and Figure 37 px 2 1 tsu XBEV XCSH Setup time XBE 3 0 XA 5 2 valid before XCS high th XCSH XBEV Hold time XBE 3 0 XA 5 2 valid after XCS high tsu XDV XCSH Setup time XDx valid before XCS high 14 th XCSH XDV Hold time XDx valid after XCS high 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns t Expansion bus select signals include XCNTL and XR W XBE 3 0 XA 5 2 operates as byte enables XBE 3 0 during host port accesses switching characteristics with external device as asynchronous bus master see Fi
5. 2 Strobe 5 Not ready 2 HOLD 2 N MU NN 10 11 e 2 XRE gt 12 T 1 1 i XWE XWAIT DNE us sum 2 i nc n t XBE 3 0 3 0 5 2 operates as address signals XA 5 2 during asynchronous peripheral accesses tXWE XWAIT operates as the write enable signal XWE during asynchronous peripheral accesses XRDY operates as active high ready input during asynchronous peripheral accesses 48 Figure 30 Expansion Bus Asynchronous Peripheral Write Timing 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING timing requirements with external device as bus master see Figure 31 and Figure 32 a th XCKIH XCS Hold time XCS valid after XCLKIN high _ XONTL vald after XOLKIN gh 8 th XCKIH XWR Hold time XW R valid after XCLKIN hight 9 wuxgrrvxck _ Setup time XBLAST valid before XCLKIN ng 9 th XCKIH XD Hold time XDx valid after XCLKIN high T XW R input output polarity selected at boot tXBLAST input polarity selected at boot 3 0 5 2 operates as byte enables XBE 3 0 during h
6. SCSA Bit Counting F Normalization NN ST Bus Switching Compatible 3M Bit On Chip SRAM Up to 256 Channels Each 2M Bit Internal Program Cache AC97 Compatible Two 128K Byte Blocks Offer Improved Serial Peripheral Interface SPI i Compatible Motorola ock 0 ytes Memory Mappe Block 1 128K Bytes Direct Mapped Two 32 Bit General Purpose Timers Cache Memory Mapped IEEE 1149 1 JTAGT 1M Bit Dual Access Internal Data Boundary Scan Compatible 128K Bytes 352 Package GJL Suffix Two 64K Byte Blocks Offer Improved 384 Pin Package GLS Suffix Concurrency 0 18 um 5 Level Metal Process CMOS Technology 3 3 V I Os 1 8 V Internal Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet VelociTl is a trademark of Texas Instruments Incorporated Motorola is a trademark of Motorola Inc t IEEE Standard 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture ADVANCE INFORMATION concerns new products in the sampling or Copyright 1999 Texas Instruments Incorporated prase data other X specifications are subject to change without notice TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 1 ADVANCE I
7. 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 Highest Performance Fixed Point Digital 32 Bit External Memory Interface Signal Processor DSP TMS320C6202 Glueless Interface to Synchronous 4 ns Instruction Cycle Time Memories SDRAM or SBSRAM 250 MHz Clock Rate Glueless Interface to Asynchronous Eight 32 Bit Instructions Cycle Memories SRAM and EPROM 2000 MIPS Four Channel Bootloading VelociTI Advanced Very Long Instruction Direct Memory Access DMA Controller Word VLIW C6200 CPU Core With an Auxiliary Channel Eight Highly Independent Functional Flexible Phase Locked Loop PLL Clock Units Generator Six ALUs 32 40 Bit Two 16 Bit Multipliers 32 Bit Result Load Store Architecture With 32 32 Bit General Purpose Registers Instruction Packing Reduces Code Size All Instructions Conditional 32 Bit Expansion Bus Glueless Low Glue Interface to Popular PCI Bridge Chips Glueless Low Glue Interface to Popular Synchronous or Asynchronous Microprocessor Buses Instruction Set Features Master Slave Functionality Byte Addressable 8 16 32 Bit Data Glueless Interface to Synchronous FIFOs 32 Bit Address Range and Asynchronous Peripherals e Overlfow Protachon Three Multichannel Buffered Serial Ports Saturation McBSPs Bit Field Extract Set Clear Direct Interface to T1 E1
8. ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING CONTINUED timing requirements for McBSP as SPI master or slave CLKSTP 11b CLKXP 11 see Figure 45 C6202 200 C6202 233 C6202 250 MASTER SLAVE UNIT 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns t For all SPI slave modes is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 switching characteristics for McBSP as SPI master or slave CLKSTP 11b CLKXP 1 see Figure 45 C6202 200 C6202 233 PARAMETER C6202 250 UNIT SLAVE th CKXH FXL Hold time FSX low after CLKX high H 2 H 3 T td FXL CKXL Delay time FSX low to CLKX T 2 T Jj ns td CKXH DXV Delay time CLKX high to DX valid 3P 4 5 17 Disable time DX high impedance following last data bit from td FXL DXV Delay time FSX low to DX valid L 2 L 4 2P 2 4P 17 T P 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns t For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 sample rate generator input clock P if CLKSM 1 P 1 CPU clock frequency sample rate generator input clock P clks if CLKSM 0 P period CLKX period 1 CLKGDV S OCLKX high pulse CLKGDV 2 1 S if
9. cur Giu Aux au AES 9 l 5 int 1 10 5 5 XDATDLY 00b N 4 3 1 12 13 DC y Bn X 1 Figure 40 McBSP Timings 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 61 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING CONTINUED timing requirements for FSR when GSYNC 1 see Figure 41 6202 200 6202 233 SS 250 UNIT 1 tsu FRH CKSH Setup time FSR high before CLKS high 2 th CKSH FRH Hold time FSR high after CLKS high 5 CLKS FSR external CLKR X no need to resync CLKR X needs resync Figure 41 FSR Timing When GSYNC 1 Ji TEXAS INSTRUMENTS 62 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING CONTINUED timing requirements for McBSP as SPI master or slave CLKSTP 10b CLKXP 01 see Figure 42 C6202 200 C6202 233 C6202 250 UNIT MASTER SLAVE T P 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns t For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CL
10. 0 for slave McBSP FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock CLKX 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 63 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING CONTINUED k hi 2 5 aa e iig 4 7 le 3 DX Bito Bit n 1 _ n 2 X n3 X n 43 X 4 5 DR BitO C X n2 X n3 X 4 X Figure 42 McBSP Timing as SPI Master or Slave CLKSTP 10b CLKXP 0 49 5 INSTRUMENTS 64 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING CONTINUED timing requirements for McBSP as SPI master or slave CLKSTP 11b CLKXP 01 see Figure 43 C6202 200 C6202 233 C6202 250 UNIT MASTER SLAVE 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns t For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 switching characteristics for McBSP as SPI master or slave CLKSTP 11b CLKXP ott see Figure 43 C6202 200 C6202 233 PARAMETER C6202 250 UNIT MASTERS SLAVE th
11. 2 e 2 3 0 52 X X X X XOE XRE ret 7 9 XD 31 0 CCo X Db X Db X Db O t XBE 3 0 XBE 3 0 XA 5 2 operates as address signals XA 5 2 during synchronous FIFO accesses tXWE XWAIT operates as the write enable signal XWE during synchronous FIFO accesses Figure 28 FIFO Write Timing TEXAS INSTRUMENTS 46 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING timing requirements for asynchronous peripheral cyclest see Figure 29 Figure 30 C6202 200 C6202 233 C6202 250 MIN MAX wckomxov ime o Setup ime XRDY vaid before T 9 th CKO1H XRY Hold time XRDY valid after CLKOUT1 high on T To ensure data setup time simply program the strobe width wide enough XRDY is internally synchronized If XRDY does meet setup or hold time it may be recognized in the current cycle or the next cycle Thus XRDY can be an asynchronous input switching characteristics for asynchronous peripheral cyclest l see Figure 29 Figure 30 C6202 200 C6202 233 PARAMETER C6202 250 td CKO1H XCEV Delay time CLKOUT1 high to XCEx valid td CKO1H XAV Delay time CLKOUT1 high to XBE 3 0 XA 5 2 valid 4 0 td CKO1H XAIV ay
12. CONTINUED EA9 R25 M21 EA8 R24 N22 EA7 R23 N20 EA6 T25 N21 O Z External address word address EA5 T24 P21 4 025 20 23 R22 EA2 V26 R21 EMIF DATA ED31 AD8 Y6 2030 9 AA6 ED29 AF7 AB6 ED28 AD9 Y7 ED27 AC10 AA7 ED26 AE9 AB8 ED25 AF9 Y8 ED24 AC11 AA8 ED23 AE10 AA9 ED22 AD11 Y9 ED21 AE11 AB10 ED20 AC12 Y10 ED19 AD12 AA10 ED18 AE12 AA11 ED17 AC13 Y11 ED16 AD14 AB12 ED15 AC14 Y12 ED14 AE15 AA12 ED13 AD15 AA13 ED12 AC15 Y13 ED11 AE16 AB13 ED10 AD16 Y14 ED9 AE17 AA14 ED8 AC16 AA15 ED7 AF18 Y15 ED6 AE18 AB15 ED5 17 16 ED4 AD18 Y16 ED3 AF20 AB17 ED2 AC18 AA17 ED1 AD19 Y17 EDO AF21 AA18 11 Input Output Z High Impedance Supply Voltage GND Ground 49 TEXAS INSTRUMENTS 14 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 l O Z External data 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 Signal Descriptions Continued SIGNAL T DESCRIPTION ASYNCHRONOUS MEMORY CONTROL ARDY wes 1 Asynchronous memory ready nput CV SYNCHRONOUS DRAM SDRAM SYNCHRONOUS BURST SRAM SBSRAM CONTROL EMIF BUS ARBITRATION 2 uz O Horenuestaoknowedge o esr ss O Hou O G2 Fi 1 orgeneralpurposeinput OSS O orgeneral purpose oupur m
13. FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 SYNCHRONOUS DRAM TIMING timing requirements for synchronous DRAM cycles see Figure 17 C6202 200 6202 233 C6202250 MIN MAX MIN MAX switching characteristics for synchronous DRAM cyclest see Figure 17 22 C6202 200 C6202 233 C6202 250 Output setup time CEx valid Output hold time CEx valid after Output setup time BEx valid Output hold time BEx invalid after 4 loh CKO2H BEIV CLKOUT2 high 5 t Output setup time EAx valid osu EAV CKO2H before CLKOUT2 high Output hold time EAx invalid after toh CKO2H EAIV CLKOUT high Output setup time losu CASV CKO2H SDCAS SSADS valid before CLKOUT2 high 0 1 Output hold time SDCAS SSADS oh CKO2H CASV valid after CLKOUT2 high t Output setup time EDx valid osu EDV CKO2H before CLKOUT2 high Output hold time EDx invalid after 12 toh CKO2H EDIV CLKOUT high 3 1 Output setup time SDWE SSWE osu WEV CKO2H valid before CLKOUT2 high 4 Output hold time SDWE SSWE oh CKO2H WEV valid after CLKOUT2 high 15 Output setup time SDA10 valid tosu SDA10V CKO2H before CLKOUT2 high Output hold time SDA10 invalid 16 toh CKO2H SDA10lV after CLKOUT2 high 7 Output setup time SDRAS SSOE osu RASV CKO2H valid before CLKOUT2 high s Output hold time SDRAS SSOE oh CKO2H RASV valid after CLKOUT2 high TP 1 CPU clock frequency in ns For e
14. TEXAS 77251 1443 RESET TIMING CONTINUED TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 k 1 k 2 gt 4 2 RESET 3 444 0 5 6 le HIGH GROUP 7 7 gt 8 h LOW GROUPI Y z Tj 9 10 zeou a 12 XD 31 0 t High group consists of XFCLK Low group consists of IACK INUM 3 0 DMAC 3 0 PD TOUTO and TOUT1 Z group consists of EA 21 2 ED 31 0 CE 3 0 BE 3 0 ARE AWE AOE SDCAS SSADS SDRAS SSOE SDWE SSWE SDA10 CLKXO CLKX1 CLKX2 FSX0 FSX1 5 2 0 0 DX1 DX2 CLKRO CLKR1 CLKR2 FSRO FSR1 FSR2 XCE 3 0 XBE 3 0 XA 5 2 XOE XWE XWAIT XAS XW R XRDY XBLAST XHOLD and XHOLDA t XD 31 0 are the boot configuration pins during device reset Figure 24 Reset Timing 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 43 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 EXTERNAL INTERRUPT TIMING timing requirements for interrupt response see Figure 25 C6202 200 C6202 233 C6202 250 2 tw ILOW Width of the interrupt pulse low J tw IHIGH Width of the interrupt pulse high 1 CPU clock frequency in ns For example when running parts
15. gt d CKXH FXV CLKX ext 3 3 3 9 gt i Disable time DX high impedance following last data bit CLKX int 1 4 pom CLIK a ENTIS Delay time CLKX high to DX valid EXE Delay time FSX high to DX valid d FXH DXV ONLY applies when in data delay 0 XDATDLY 00b FSX ext mode ex td CKXH DXV _ E T CLKRP CLKXP FSRP FSXP 0 If polarity of any of the signals is inverted then the timing references of that signal are also inverted t Minimum delay times also represent minimum output hold times P 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns c HorL S sample rate generator input clock P if CLKSM 1 P 1 CPU clock frequency sample rate generator input clock P clks if CLKSM 0 P period CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero L CLKX low pulse width CLKGDV 2 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero Ji TEXAS INSTRUMENTS 60 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 ns 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING CONTINUED CLKS 1 TT cas Re FSR int J EE RR 6 8 DR X n2 X X CLKX D
16. 15 and Figure 16 C6202 200 C6202 233 C6202 250 Output setup time CEx valid mE mem losu CEV CKO2H before CLKOUT2 high Output hold time CEx valid after 1 1 1 CLKOUT2 high i Output setup time BEx valid before CLKOUT2 high 27 39 ees arse ES toh CKO2H CEV losu BEV CKO2H Output hold time BEx invalid after CLKOUT2 high loh CKO2H BEIV losu EAV CKO2H loh CKO2H EAIV losu ADSV CKO2H toh CKO2H ADSV _ tosu OEV CKO2H N loh CKO2H OEV losu EDV CKO2H loh CKO2H EDIV tosu WEV CKO2H 16 toh CKO2H WEV Output setup time EAx valid before CLKOUT2 high Output hold time EAx invalid after CLKOUT2 high Output setup time SDCAS SSADS valid before CLKOUT2 high Output hold time SDCAS SSADS valid after CLKOUT2 high Output setup time SDRAS SSOE valid before CLKOUT2 high Output hold time SDRAS SSOE valid after CLKOUT2 high Output setup time EDx valid before CLKOUT2 high Output hold time EDx invalid after CLKOUT2 high Output setup time SDWE SSWE valid before CLKOUT2 high Output hold time SDWE SSWE valid after CLKOUT2 high 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns t SDCAS SSADS SDRAS SSOE and SDWE SSWE operate as SSADS SSOE and SSWE respectively during SBSRAM accesses For the first write in a series of one or more consecutive adjacent writes the write
17. 1998 REVISED AUGUST 1999 Signal Descriptions Continued SIGNAL t DESCRIPTION MEN EXPANSION BUS CONTINUED 5 08 D8 ala Expansion bus multiplexed byte enable control address signals Actas byte enable for host port operation e Actas address for I O port operation E E 6 B A6 XBE0 XA2 Zl RT xen __ Expansion bus host control selects between expansion bus address or data register Expansion bus host port ready active low and port ready active high EMIF CONTROL SIGNALS COMMON TO ALL TYPES OF MEMORY AB25 AA24 W20 Memory space enables Enabled by bits 24 and 25 of the word address nes eres Only one asserted during any external data access W21 Byte enable control Decoded from the two lowest bits of the internal address W22 Byte write enables for most types of memory Can be directly connected to SDRAM read and write mask signal SDQM ADDRESS External address word address T Input Output Z High Impedance S Supply Voltage GND Ground 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 13 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 Signal Descriptions Continued SIGNAL T DESCRIPTION e _ ADDRESS
18. 4 5 DR X X X X Figure 43 McBSP Timing as SPI Master or Slave CLKSTP 11b CLKXP 0 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 65 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING CONTINUED timing requirements for McBSP as SPI master or slave CLKSTP 10b CLKXP 1T see Figure 44 C6202 200 C6202 233 C6202 250 MASTER SLAVE UNIT 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns t For all SPI slave modes is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 switching characteristics for McBSP as SPI master or slave CLKSTP 10b CLKXP 11 see Figure 44 C6202 200 C6202 233 PARAMETER C6202 250 UNIT SLAVE th CKXH FXL Hold time FSX low after high T 2 T 3 td EXL CKXL Delay time FSX low to CLKX low H 2 H 3 ns td CKXL DXV Delay time CLKX low to DX valid 4 5 17 Disable time DX high impedance following last data bit from Disable time DX high impedance following last data bit from 2P 2 4P 17 8 ta FxL DXV Delay time FSX low to DX valid P 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns For all SPI slave modes CLKG is programmed as 1 2 of the
19. CKXL FXL Hold time FSX low after CLKX low l L 2 1 3 J ns td FXL CKXH Delay time FSX low to CLKX high T 2 T 3 ns ta CKXL DXV Delay time CLKX low to DX valid 3P 4 5 17 Disable time DX high impedance following last data bit from td EXL DXV Delay time FSX low to DX valid H 2 H 4 2P 2 4 17 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns t For all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 sample rate generator input clock P if CLKSM 1 P 1 CPU clock frequency sample rate generator input clock P clks if CLKSM 0 P period CLKX period 1 S high pulse width CLKGDV 2 1 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero L CLKX low pulse width CLKGDV 2 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero FSXP 1 As a SPI master FSX is inverted to provide active low slave enable output As a slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for master McBSP CLKXM CLKRM FSXM FSRM 0 for slave McBSP FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock CLKX FSX y Y 6 7 le k3 DX BitO C Bit n 1 A n2 X n 3 X n4 X
20. TEXAS 77251 1443 11 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 Signal Descriptions Continued SIGNAL T DESCRIPTION Wee seem EXPANSION 5 XCLKIN A9 C8 Expansion bus synchronous host interface clock input XFCLK B9 A8 Expansion bus interface clock output D15 B16 A17 B17 D16 A18 B18 D17 C18 A20 D18 C19 A21 D19 C20 B21 A22 D20 B22 E25 F24 E26 F25 G24 H23 F26 G25 423 26 25 424 C13 A13 C14 B14 B15 C15 A15 B16 C16 A17 B17 C17 B18 A19 C18 B19 C19 B20 A21 C21 D20 B22 D21 E20 E21 D22 F20 F21 E22 G20 Expansion bus data e Used for transfer of data address and control Also controls initialization of DSP modes and expansion bus at reset via pullup pulldown resistors XCE 3 0 memory type XBLAST polarity XW R polarity Asynchronous or synchronous host operation Arbitration mode internal or external FIFO mode Little endian big endian Boot mode Expansion bus I O port memory space enables Enabled by bits 28 29 and 30 of the word address Only one asserted during any I O port data access 11 Input Output Z High Impedance S Supply Voltage GND Ground 12 49 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST
21. clock either drives the PLL which generates the internal CPU clock or bypasses the PLL to become the CPU clock To use the PLL to generate the CPU clock the filter circuit shown in Figure 6 must be properly designed To configure the C6202 PLL clock for proper operation see Figure 6 and Table 3 To minimize the clock jitter a single clean power supply should power both the C6202 device and the external clock oscillator circuit The minimum CLKIN rise and fall times should also be observed See the input and output clocks section for input clock timing requirements R1 1 CLKOUT1 11N A A CPU Clock 7 2 i 5 C 2 jp CLKOUT2 nr 10uF O1gF C1 C2 GND V Bypass CLKMODE0 0 MULTx1 f CPU Clock f CLKIN 0 0 1 MULTx4 Clock f CLKIN x4 Other Modes Reserved CLKMODE2 CLKMODF1 NOTES The C6202 PLL can generate CPU clock frequencies in the range of 130 MHz to 250 MHz For frequencies below 130 MHz the PLL should be configured to operate in bypass mode For the C6202 values for C1 C2 and R1 are fixed and apply to all valid frequency ranges of CLKIN and CPU clock frequency For CLKMODE x1 the PLL is bypassed and all six external PLL components can be removed For this case the PLLV terminal has to be connected to a clean 3 3 V supply and the PLLG and PLLF terminals should be tied together The 3 3 V supply for
22. external FSR high before CLKR low CLKR ext CLKR int Hold time external FSR high after CLKR low CLKR ext CLKR int 7 t Setup time DR valid before CLKR low su DRV CKRL p CLKR ext Hold ti DR valid after ___ old time valid after ow h CKRL DRV CLKR ext CLKX int 10 tsu FXH CKXL Setup time external FSX high before CLKX low CLKX ext Hold ti ternal FSX high after CLKX old time externa igh after ow h CKXL FXH g CLKX ext 16 CLKXP FSRP 0 If polarity any of the signals is inverted then the timing references of that PET are also inverted den clock frequency in ns For example when running parts at 250 MHz use 4 ns h CKRL FRH 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 59 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING CONTINUED switching characteristics for 5 see Figure 40 C6202 200 C6202 233 PARAMETER em 250 t Delay time CLKS high to CLKR X high for internal 4 10 d CKSH CKRXH cL KR X generated from CLKS input te CKRX Cycle time CLKR X CLKR X int tw CKRX Pulse duration CLKR X high or CLKR X low CLKR X int 11 411 4 Delay time CLKR high to internal FSR valid CLKR int j Delay time CLKX high to internal FSX valid 3
23. functional units Each set contains four units and a register file One set contains functional units L1 S1 M1 and D1 the other set contains units D2 M2 S2 and L2 The two register files each contain 16 32 bit registers for a total of 32 general purpose registers The two sets of functional units along with two register files compose sides A and B of the CPU see Figure 1 and Figure 2 The four functional units on each side of the CPU can freely share the 16 registers belonging to that side Additionally each side features a single data bus connected to all the registers on the other side by which the two sets of functional units can access data from the register files on the opposite side While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle register access using the register file across the CPU supports one read and one write per cycle Another key feature of the C6200 CPU isthe load store architecture where all instructions operate on registers as opposed to data in memory Two sets of data addressing units D1 and D2 are responsible for all data transfers between the register files and the memory The data address driven by the D units allows data addresses generated from one register file to be used to load or store data to or from the other register file The C6200 CPU supports a variety of indirect addressing modes using either linear o
24. includes three multichannel buffered serial ports McBSPs two general purpose timers an expansion bus XB that offers ease of interface to synchronous asynchronous industry standard host bus protocols and a glueless external memory interface EMIF capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals The C6202 has a complete set of development tools which includes a new C compiler an assembly optimizer to simplify programming and scheduling and a Windows debugger interface for visibility into source code execution device characteristics Table 1 provides an overview of the C6202 DSP The table shows significant features of each device including the capacity of on chip RAM the peripherals the execution time and the package type with pin count Table 1 Characteristics of the C6202 Processors CHARACTERISTICS DESCRIPTION 2 Mbit Program Memory l organized as 2 blocks 1 Mbit Data Memory organized as 2 blocks 3 Multichannel Buffered Serial Ports McBSP P r herals 2 General Purpose Timers P External Memory Interface EMIF Expansion Bus XB Package 27 mm x 27 352 BGA GJL 18 x 18 384 GLS 1 8 Nominal Voltage 33 V 1 0 Tl is a trademark of Texas Instruments Incorporated Windows is a registered trademark of the Microsoft Corporation vy TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 3 A
25. until all the execute packets from the current fetch packet have been dispatched After decoding the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle While most results are stored in 32 bit registers they can be subsequently moved to memory as bytes or half words as well All load and store instructions are byte half word or word addressable 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 CPU description continued Program Memory 32 Bit Address 256 Bit Data Program Fetch Instruction Dispatch Instruction Decode Data Path A Data Path B External Memory Register File Register File B Interface Data Memory 32 Bit Address 8 16 32 Bit Data Figure 1 TMS320C62x CPU Block Diagram 49 5 INSTRUMENTS 8 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 C62x CPU Control Registers Test Emulation Interrupts Additional Peripherals Timers Serial Ports etc 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 CPU description continued Register Data Path A File A 0 15 Register Data Path B File B B0 B15
26. valid after XCLKIN hight tsu XBFF XCKIH Setup time XBOFF valid before XCLKIN high th XCKIH XBFF Hold time XBOFF valid after XCLKIN high t XRDY operates as active low ready input output during host port accesses switching characteristics with C6202 as bus master see Figure 33 Figure 34 and Figure 35 wg PRATER UNT td XCKIH XBEV Delay time XCLKIN high to XBE 3 0 XA 5 2 valid Delay time XOLKIN high to xev 8 td XCKIH XDHZ Delay time XCLKIN high to XDx high impedance td XCKIH XWTV Delay time XCLKIN high to XWE XWAIT valid tXW R input output polarity selected at boot 8 XBLAST output polarity is always active low 3 0 5 2 operates as byte enables XBE 3 0 during host port accesses XWE XWATT operates as XWAIT output signal during host port accesses 49 5 INSTRUMENTS 52 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING CONTINUED N A NA 1 ii XS 114141111422 gt 2 e 2 xwRt Of Xw RT XBLAST 3 0 5 2 8 gt jede XD 31 0 AX AD XJ C 1 A D2 Xx __ 23 DA M X ZTT T XW R input output polarity selected at boot t XBLAST output polarity is a
27. 000000000000000 B oooooooooooooooooooooooooo 00000000000000000000000000 1 3 5 7 9 1113 15 17 19 21 23 25 2 4 6 8 10 12 14 46 18 20 22 24 26 Heat Slug See Note E 3 50 MAX 1 00 NOM yg Seating Plane 0 70 t i 0 40 4173516 2 C 07 99 NOTES A Alllinear dimensions are in millimeters B This drawing is subject to change without notice C Thermally enhanced plastic package with heat slug HSL D Flip chip application only E Possible protrusion in this area but within 3 50 max package height specification Falls within JEDEC MO 151 AAL 1 thermal resistance characteristics S PBGA package mI T LFPM Linear Feet Per Minute 35 TEXAS INSTRUMENTS 72 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 MECHANICAL DATA GLS S PBGA N384 PLASTIC BALL GRID ARRAY gt gt gt 16 80 O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O0 O O O O O O O O O O O O OOOOOOOOOOO OOOOOOOOOOO OOOOOOOOOOO OOOOOOOOOOO OOOOOOOOOOO O O O O O O O O O O O O OOOOOO OOOOOO OOOOOO OOOOOO O O O O O O OOOOOO O O O O O O O O O O O O O OC O O O O O O O O OO O O O O O O O O O O O O O O O O O O O O0 O O O O O O O O O O O O OOOOOOOOOOO OOOOOOOOOOO OOOOOOOOOOO 11 13 15 17 19 2
28. 01 introduces the Code Composer Studio integrated development environment and software tools 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 25 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 documentation support continued 26 The TMS320C6000 Technical Brief literature number SPRU197 gives an introduction to the C62x C67x devices associated development tools and third party support A series of DSP textbooks is published by Prentice Hall and John Wiley amp Sons to support DSP research and education The TMS320 newsletter Details on Signal Processing is published quarterly and distributed to update TMS320 customers on product information The TMS320 DSP bulletin board service BBS provides access to information pertaining to the TMS320 family including documentation source code and object code for many DSP algorithms and utilities The BBS can be reached at 281 274 2323 Information regarding DSP products is also available on the Worldwide Web at http www ti com uniform resource locator URL 49 5 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 clock PLL All of the internal C6202 clocks are generated from a single source through the CLKIN pin This source
29. 1 10 12 14 16 18 20 22 OOOOOO OOOOOO n TA Z 4 lt lt gt Z Heat Slug 1 00 NOM Seating Plane 0 15 4188959 B 12 98 NOTES A Alllinear dimensions are in millimeters B This drawing is subject to change without notice C Thermally enhanced plastic package with heat slug HSL D Flip chip application only thermal resistance characteristics S PBGA package meu smoor es 0 4 ROjc T LFPM Linear Feet Per Minute 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 73 ADVANCE INFORMATION IMPORTANT NOTICE Texas Instruments its subsidiaries TI reserve the rightto make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are utilized to
30. 443 27 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 absolute maximum ratings over operating case temperature range unless otherwise noted T Supply voltage range CVpp see Note 1 0 3 Vto 2 3 V Supply voltage range DVpp see Note 1 0 3 V to 4 V Mpu volage range h n 0 3 V to 4 V Output voltage FANGS sessio d DE td a 0 3 V to 4 V Operating case temperature range 0 to 90 Storage temperature range HHH kn nnn 55 C to 150 C T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTE 1 All voltage values are with respect to Vss recommended operating conditions wx UNIT Wss s Towlevelinutvotage ___ electrical characteristics over recommended
31. CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero L CLKX low pulse width CLKGDV 2 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero FSXP 1 As a SPI master FSX is inverted to provide active low slave enable output As a slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for master McBSP CLKXM CLKRM FSXM FSRM 0 for slave McBSP FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock CLKX 4 5 DR Cini X X XC X Figure 45 McBSP Timing as SPI Master or Slave CLKSTP z 11b CLKXP z 1 35 TEXAS INSTRUMENTS 68 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 DMAC TIMER POWER DOWN TIMING switching characteristics for DMAC outputst see Figure 46 C6202 200 C6202 233 PARAMETER C6202 250 tw DMACH Pulse duration DMAC high 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns 1 0 Figure 46 Timing timing requirements for timer inputsT see Figure 47 C6202 200 C6202 233 ENS 250 tw TINPH Pulse duration TINP high Pulse duration
32. CPU clock by setting CLKSM CLKGDV 1 S sample rate generator input clock P if CLKSM 1 P 1 CPU clock frequency sample rate generator input clock P clks if CLKSM 0 P clks CLKS period CLKX period 1 CLKGDV S H CLKX high pulse width CLKGDV 2 1 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero L CLKX low pulse width CLKGDV 2 S if CLKGDV is even CLKGDV 1 2 S if CLKGDV is odd or zero 1 FSRP FSXP 1 As a SPI master FSX is inverted to provide active low slave enable output As a slave the active low signal input on FSX and FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for master McBSP CLKXM CLKRM FSXM FSRM 0 for slave McBSP FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock CLKX xi TEXAS INSTRUMENTS 66 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING CONTINUED 1 4 2 gt FSX k 6 8 le 3 ___Bito0 Bit n 1 n2 X 3 X n4 X 4 4 5 DR Figure 44 McBSP Timing as SPI Master or Slave CLKSTP 10b CLKXP 1 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 67 ADVANCE INFORMATION
33. DVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 functional block diagram Timers Data Memory Interrupt Selector Peripheral McBSPs Bus XB Control Controller DMA Control EMIF Control Data Memory Controller DMA Expansion Bus XB Controller Interface Program Memory Controller Program Memory Cache 49 5 INSTRUMENTS 4 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 CPU description The CPU fetches advanced very long instruction words VLIW 256 bits wide to supply up to eight 32 bit instructions to the eight functional units during every clock cycle The VelociTI VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute The first bit of every 32 bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction or whether it should be executed in the following clock as a part of the next execute packet Fetch packets are always 256 bits wide however the execute packets can vary in size The variable length execute packets are a key memory saving feature distinguishing the C6200 CPU from other VLIW architectures The CPU features two sets of
34. During that time RESET must be asserted to ensure proper device operation See the clock PLL section for PLL lock times XD 31 0 are the boot configuration pins during device reset switching characteristics during reset see Figure 24 C6202 200 C6202 233 PARAMETER C6202 250 UNIT MIN LKOUT1 2 tR RST Response time to change of value in RESET signal BEE E td CKO1H CKO2IV Delay time CLKOUT1 high to CLKOUT invalid 5 Delay tine GLKOUTI high group waid 10 Delay time GLKOUTI Fgh to high groupvald tsckowitowv Delay time CLKOUTI high to low grojpval of Delay time CLKOUTI high to Z group high impedance Te td CKO1H ZV Delay time CLKOUT1 high to Z group valid i invali 10 td CKO1H CKO2V Delay time CLKOUT1 high to CLKOUT2 valid c c T NC 10 ns ns ns s High group consists of XFCLK Low group consists of IACK INUM 3 0 DMAC 3 0 PD TOUTO and TOUT1 Z group consists of 21 2 ED 31 0 CE 3 0 BE 3 0 ARE AWE AOE SDCAS SSADS SDRAS SSOE SDWE SSWE SDA10 CLKX1 CLKX2 FSX1 FSX2 DX1 DX2 CLKRO CLKR1 CLKR2 FSRO FSR1 FSR2 XCE 3 0 3 0 5 2 XOE XWE XWAIT XAS XW R XRDY XBLAST XHOLD and XHOLDA 49 5 INSTRUMENTS 42 POST OFFICE BOX 1443 HOUSTON
35. EREZ mr 5 OCH Ep8t0J q6 ESSES 17 kk SDRAS SSOET n r 5 f 9 k i SDCAS SSADST 14 SDWE SSWET T SDCAS SSADS SDRAS SSOE and SDWE SSWE operate as SDCAS SDRAS and SDWE respectively during SDRAM accesses Figure 22 SDRAM MRS Command 49 TEXAS INSTRUMENTS 40 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 HOLD HOLDA TIMING timing requirements for the HOLD HOLDA cyclest see Figure 23 C6202 200 C6202 233 C6202 250 MIN MAX toh HOLDAL HOLD Hold time HOLD low after HOLDA low 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns switching characteristics for the HOLD HOLDA cyclestt see Figure 23 C6202 200 C6202 233 PARAMETER C6202 250 3P 5 td EMLZ HOLDAH Delay time EMIF Bus low impedance to HOLDA high 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns t EMIF Bus consists of CE 3 0 BE 3 0 ED 31 0 EA 21 2 ARE AOE AWE SDCAS SSADS SDRAS SSOE SDWE SSWE and SDA10 All pending EMIF transactions are allowed to complete before HOLDA is asserted The worst case for this is an asynchronous read or write with external ARDY used or a minimum of eight consecutive SDRAM reads or writes when RBTR8 1 If no bus transactions are occurrin
36. FICE BOX 1443 9 HOUSTON TEXAS 77251 1443 33 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 ASYNCHRONOUS MEMORY TIMING CONTINUED Setup 2 Strobe 5 Not ready 2 i HOLD 1 C N X AC A C ST SU 1 gt k 1 gt CEx Y 2 3 4 le 5 EA 21 2 e 6 7 ED 31 0 a l o COES 8 89 EA ef ee 9 k 1 j AWE i 11 64 11 k 14 10 lt TUN _ Figure 13 Asynchronous Memory Read Timing Setup 2 Strobe 5 Not ready 2 HOLD T TC XANA ST EA 21 2 BENE irr 20131 _ 4 g 11 10 10 Sas Figure 14 Asynchronous Memory Write Timing 35 TEXAS INSTRUMENTS 34 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 SYNCHRONOUS BURST MEMORY TIMING timing requirements for synchronous burst SRAM cycles see Figure 15 C6202 200 C6202 233 C6202 250 Setup time read EDx valid before CLKOUT2 switching characteristics for synchronous burst SRAM cyclestt see Figure
37. GA Pin Grid Array Chip Carrier QFP Quad Flat Package TQFP Thin Quad Flat Package BGA Ball Grid Array GFN 256 pin plastic BGA GGU 144 plastic BGA 352 plastic GJC 352 plastic BGA GJL 352 pin plastic BGA GLS 384 pin plastic BGA DEVICE 1x DSP 10 16 14 17 15 2x DSP 25 26 2xx DSP 203 206 240 204 209 DSP 30 31 32 40 44 5x 50 53 51 56 52 57 54x DSP 541 545 542 546 543 548 6x 6201 6201 6202 6203 6211 6701 6711 Figure 5 5320 Device Nomenclature Including 5320 6202 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 documentation support Extensive documentation supports all TMS320 family generations of devices from product announcement through applications development The types of documentation available include data sheets such as this document with design specifications complete user s reference guides for all devices technical briefs development support tools and hardware and software applications The following is a brief descriptive list of support documentation specific to the C6x devices TMS320C6000 CPU and Instruction Set Reference Guide literature number SPRU189 describes the C6000 CPU architecture instruction set pipeline and associated in
38. HOLDA BEO s External Memory Interface TOUTI TOUTO TINP1 La TINP0 CLKX0 FSX0 DX0 CLKR0 McBSP1 FSR0 DR0 CLKX1 FSX1 DX1 4 CLKR1 4 FSR1 4 Receive DR1 4 McBSP2 Transmit q Receive DEN CLKSO CLKX2 FSX2 DX2 CLKR2 FSR2 DR2 CLKS2 McBSPs Multichannel Buffered Serial Ports Figure 4 Peripheral Signals vy TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 9 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 signal groups description continued XD 31 0 Clocks XBE3 XA5 XBE2 XA4 Byte Enable XBE1 XA3 Control XOE 2 Address Port XWE XWAIT Control XCE3 XRDY Control XCES XCEO XHOLDA EX Arbitration XCS XAS s E t XCNTL nterface XW R Expansion Bus Control Figure 4 Peripheral Signals Continued 49 5 INSTRUMENTS 10 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 Signal Descriptions SIGNAL t DESCRIPTION Wee seem CLOCK PLL o Bo Tm TT tt Am O mom j mode selects Note CLKMODE1 CLKMODE2 selects are for GLS devices only e Selects whether the CPU
39. KGDV 1 switching characteristics for McBSP as SPI master or slave CLKSTP 10b CLKXP 01 see Figure 42 C6202 200 C6202 233 PARAMETER C6202 250 UNIT MASTERS SLAVE th CKXL FXL Hold time FSX low after CLKX low l T 2 T 3 td FXL CKXH Delay time FSX low to CLKX high L 2 L 3 J ns Disable time DX high impedance following last data bit from td CKXH DXV Delay time CLKX high to DX valid 4 5 17 Lad Disable time DX high impedance following last data bit from p 8 ta FXL DXV Delay time FSX low to DX valid 2P 2 4 17 1 CPU clock frequency ns For example when running parts at 250 use P 4 ns or all SPI slave modes CLKG is programmed as 1 2 of the CPU clock by setting CLKSM CLKGDV 1 sample rate generator input clock P if CLKSM 1 P 1 CPU clock frequency sample rate generator input clock P clks if CLKSM 0 P clks period CLKX period 1 CLKGDV S CLKX high pulse width CLKGDV 2 1 5 if CLKGDV is even CLKGDV 1 2 5 if CLKGDV is or zero L CLKX low pulse CLKGDV 2 S if CLKGDV is even CLKGDV 1 2 5 if CLKGDV 15 or zero FSRP FSXP 1 As a SPI master FSX is inverted to provide active low slave enable output As a slave the active low signal input FSX FSR is inverted before being used internally CLKXM FSXM 1 CLKRM FSRM 0 for master McBSP CLKXM CLKRM FSXM FSRM
40. NFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 gt Z amp Z U JHC lt KES lt GJL 352 PIN BALL GRID ARRAY BGA PACKAGE BOTTOM VIEW O O O O O O O O O O 0O O O O O O0 O0 O O O O 0 O O O O O O O O O O O O O O O O O0 O O O0 O O O0 O0 O O O OO O 0O O O O O O O O0 O 0O 0O O O 0 0 O0 O0 O0 O O0 O0 0 O O O O O O O O O O O O 0O O0 O O O0 O0 O0 O0 O O 0 O OOOOOOOOOOOOOOOOOOOOO00 OOOOOOOOOOOOOOOOOOOOOOOOO00 O O O O O O O O O 0 O O O O O O0 O O 0 O0 O O O O 0 O OOOO OOOO OOOO OOOO OOOO OOOO OOOO OOOO OOOO OOOO OOOO OOOO 11 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 GLS 384 PIN BALL GRID ARRAY BGA PACKAGE BOTTOM VIEW OOOOOO OOOOOO OOOOOO OOOOOO OOOOOO OOOOOO OOOOOO OOOOOO OC O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O OOOOOOOOOOOOOOOOOOOO000 1 3 5 7 9 41 43 45 17 19 21 2 4 6 8 10 12 14 16 18 20 22 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 description The 5320 62 DSPs including the TMS320C6202 device are the fi
41. NSTRUMENTS 50 POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING CONTINUED xek NCC xes A XONTL X X M 23M EE e I J i 1 XBE 3 0 XA b2 0 _ 4 10 9 xass r 10 94 5 19 18 XD 31 0 L D1 X D2 X D3 X D4 20 gt gt 15 gt 15 T XW R input output polarity selected at boot t 3 0 5 2 operates as byte enables XBE 3 0 during host port accesses 5 XBLAST input polarity selected at boot operates as active low ready input output during host port accesses Figure 32 External Host as Bus Master Write 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 51 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING CONTINUED timing requirements with C6202 as bus master see Figure 33 Figure 34 and Figure 35 N tnx UNIT 9 tsu XDV XCKIH Setup time XDx valid before XCLKIN high th XCKIH XDV Hold time XDx valid after XCLKIN high tsu XRY XCKIH Setup time XRDY valid before XCLKIN hight th XCKIH XRY Hold time XRDY
42. NTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 29 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 INPUT AND OUTPUT CLOCKS timing requirements for CLKINT see Figure 8 C6202 200 C6202 233 C6202 250 CLKMODE CLKMODE CLKMODE CLKMODE CLKMODE CLKMODE UNIT x4 x1 x4 x1 x4 x1 Pulse duration Iw CLKINH CLKIN high 5 J Pulse duration Iw CLKINL CLKIN low 5 s J Transition time CLKIN 3 m T The reference points for the rise and fall transitions are measured at 20 and 80 respectively of VIH zc 1 ZA k 3 4 gt le Figure 8 CLKIN Timings timing requirements for XCLKINT see Figure 9 C6202 200 C6202 233 C6202 250 1 tc XCLKIN Cycle time XCLKIN tw XCLKINH Pulse duration XCLKIN high tw XCLKINL Pulse duration XCLKIN low tt XCLKIN Transition time XCLKIN 0 osef t The reference points for the rise and fall transitions are measured at 20 and 80 respectively of VIH t P 1 CPU clock frequency in nanoseconds ns 1 gt T r XCLKIN a 5 4 gt le Figure 9 XCLKIN Timings 35 TEXAS INSTRUMENTS 30 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCE
43. SSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 INPUT AND OUTPUT CLOCKS CONTINUED switching characteristics for CLKOUT1T see Figure 10 6202 200 6202 233 PARAMETER C6202 250 init CLKMODE x4 CLKMODE x1 2 5 2 05 05 2 05 4 wckon Tension time is the high period of CLKIN in ns and PL is the low period of CLKIN in ns 1 CPU clock frequency in nanoseconds ns MEC psc dE lt 3 4 4 le Figure 10 CLKOUT1 Timings switching characteristics for CLKOUT2 see Figure 11 C6202 200 C6202 233 PARAMETER C6202 250 tt CKO2 Transition time CLKOUT2 FB 1 CPU clock frequency in nanoseconds ns ADVANCE INFORMATION 1 gt 4 2 CLKOUT2 k 3 4 9 le Figure 11 CLKOUT2 Timings vy TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 31 ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 INPUT AND OUTPUT CLOCKS CONTINUED switching characteristics for XFCLKT see Figure 12 C6202 200 C6202 233 PARAMETER C6202 250 UNIT tc XFCK Cycle time XFCLK D 7 807 tw XFCKL Pulse duration XFCLK low tt XFCK Transition time XFCLK 06 T P 1 CPU clock frequency in ns 0 8 6 4 or 2 FIFO clock divide ratio user progr
44. TMS320 related products from other companies in the industry To receive TMS320 literature contact the Literature Response Center at 800 477 8924 See Table 2 for a complete listing of development support tools for the C6200 For information on pricing and availability contact the nearest TI field sales office or authorized distributor Table 2 TMS320C6xx Development Support Tools TT TT EVM Evaluation Kit including TMDX3246855 07 PC Win95 Windows NT TMDX326006201 T Includes XDS510 board and JTAG emulation cable TMDX324016X 07 C source Debugger Emulation software is not included t Includes XDS510WS box SCSI cable power supply and JTAG emulation cable XDS XDS510 and XDS510WS are trademarks of Texas Instruments Incorporated Win32 and Windows NT are trademarks of Microsoft Corporation SPARC is a trademark of SPARC International Inc Solaris is a trademark of Sun Microsystems Inc 22 49 5 INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 device and development support tool nomenclature To designate the stages in the product development cycle assigns prefixes to the part numbers of all TMS320 devices and support tools Each TMS320 member has one of three prefixes TMX TMP or TMS Texas Instruments recommends two of three possible prefix designators for support tools TMDX and TMDS Th
45. Voltage GND Ground xi TEXAS INSTRUMENTS 16 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 Signal Descriptions Continued SIGNAL t DESCRIPTION a T SUPPLY VOLTAGE PINS CONTINUED TI JN K1 N P1 AD10 AD13 T1 AD17 AD21 9 9 19 9 9 U19 3 3 V supply voltage s 1 8 V supply voltage D m s CVDD T Input O Tm Z High Impedance S Supply Voltage GND Ground 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 17 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 Signal Descriptions Continued Sew T DESCRIPTION SUPPLY VOLTAGE PINS CONTINUED C2 F14 C3 15 C4 F16 C23 G g I ojo H17 H18 D23 J6 D24 J17 4 K5 E23 K18 AB L5 AB23 L6 AC3 117 ACA L18 5 22 6 23 17 24 18 a 1 8 V supply voltage gt 9 z a AD2 N18 AD P6 AD4 P17 AD23 R5 AD24 R6 AD25 R17 AD26 R18 gt gt ala 9 17 24 18 25 07 26 08 1 09 2 U11 AF3 U12 AF24 U14 AF25 U15 11 Input O Output Z High Impedance S Supply Voltage GND Ground 35 TEXAS INSTRUMENTS 18 POST OFFICE BO
46. X 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 Signal Descriptions Continued SIGNAL t DESCRIPTION Wee SUPPLY VOLTAGE PINS CONTINUED U16 CVDD 1 8 supply voltage GROUND PINS A13 A12 GND Ground pins C16 D12 tI Input mE High Impedance S Supply Voltage GND Ground 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 19 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 Signal Descriptions Continued Sew T DESCRIPTION GROUND PINS CONTINUED K1 F13 5 gt co N z lt c z Ul U N a ied r r 2 N 2 W1 N17 N 2 GND Ground pins gt 9 o Q N a T Input Output Z High Impedance S Supply Voltage GND Ground 35 TEXAS INSTRUMENTS 20 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 Signal Descriptions Continued Sew 1 DESCRIPTION n GROUND PINS CONTINUED 20 NOS Ground pins AA2 AB1 AB3 7
47. ammable 1 4 S XFCLK k 3 4 4 le Figure 12 Timings 49 5 INSTRUMENTS 32 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 ASYNCHRONOUS MEMORY TIMING timing requirements for asynchronous memory cycles see Figure 13 Figure 14 C6202 200 C6202 233 C6202 250 MIN MAX tsu EDV CKO1H Setup time read EDx valid before CLKOUT1 high th CKO1H EDV Hold time read EDx valid after CLKOUT1 high o tsu ARDY CKO1H Setup time ARDY valid before CLKOUT1 high th CKO1H ARDY Hold time ARDY valid after CLKOUT1 high t To ensure data setup time simply program the strobe width wide enough ARDY is internally synchronized If ARDY does meet setup or hold time it may be recognized in the current cycle or the next cycle Thus ARDY can be an asynchronous input switching characteristics for asynchronous memory cyclest see Figure 13 Figure 14 6202 200 6202 233 PARAMETER C6202 250 td CKO1H AREV ay time CLKOUT1 high to ARE valid 12 tq CKO1H EDV ay time CLKOUT1 high to EDx valid 13 tq CKO1H EDIV ay time CLKOUT1 high to EDx invalid o n td CKO1H AWEV Delay time CLKOUT1 high to AWE valid 0 40 The minimum delay is also the minimum output hold after CLKOUT1 high De De De De De De De 5 TEXAS INSTRUMENTS POST OF
48. as byte enables XBE 3 0 during host port accesses tXW R input output polarity selected at boot Figure 37 External Device as Asynchronous Master Write 49 5 INSTRUMENTS 56 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 XHOLD XHOLDA TIMING timing requirements for expansion bus arbitration internal arbiter enabled t see Figure 38 toh XHDAH XHDH Output hold time XHOLD high after XHOLDA high m T P 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns switching characteristics for expansion bus arbitration internal arbiter enabled tt see Figure 38 NO PARAMETER 1 tR XHDH XBHZ Response time XHOLD high to XBus high impedance td XBHZ XHDAH Delay time XBus high impedance to XHOLDA high tR XHDL XHDAL Response time XHOLD low to XHOLDA low td XHDAL XBLZ Delay time XHOLDA low to XBus low impedance 1 CPU clock frequency in ns For example when running parts at 250 MHz use 4 ns t XBus consists of 3 0 5 2 XAS XW R and XBLAST All pending XBus transactions are allowed to complete before XHOLDA is asserted DSP Owns Bus Externa ae DSP Owns 3 XHOLD input __ XHOLDA output N XBust C6202 C6202 t XBus consists of 3 0 5 2 XAS XW R and XBLAST Figure 38 Expansion B
49. at 250 MHz use P 4 ns switching characteristics during interrupt response cyclest see Figure 25 C6202 200 C6202 233 PARAMETER C6202 250 1 tR EINTH IACKH Response time EXT INTx high to IACK high td CKO2L IACKV Delay time CLKOUT2 low to IACK valid td CKO2L INUMV Delay time CLKOUT2 low to INUMx valid 6 taCKO2L INUMIV Delay time low to INUMx invalid 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns k 1 gt CLKOUT2 3 2 5 EXT Intr Flag 4 i IACK gt 6 5 Interrupt Number Figure 25 Interrupt Timing 35 TEXAS INSTRUMENTS 44 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS FIFO TIMING timing requirements for synchronous FIFO interface see Figure 26 Figure 27 and Figure 28 uox uer tsu XDV XECKH Setup time read valid before XFCLK high 6 th XFCKH XDV Hold time read XDx valid after XFCLK high switching characteristics for synchronous FIFO interface see Figure 26 Figure 27 and Figure 28 PRE td XFCKH XAV Delay time XFCLK high to XBE 3 0 XA 5 2 validt Delay tie XECLK high 9 ta XFCKH XDIV Delay
50. ates the package type for example GJL the temperature range for example blank is the default commercial temperature range and the device speed range in megahertz for example 250 is 250 MHz Figure 5 provides a legend for reading the complete device name for any TMS320 family member 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 23 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 device and development support tool nomenclature continued 24 TMS 320 PREFIX TMX Experimental device Prototype device TMS Qualified device SMJ MIL STD 883C SM High Rel non 883C DEVICE FAMILY 320 TMS320 family 6202 GJL 250 E DEVICE SPEED RANGE 100 MHz 150 MHz 167 MHz 200 MHz 233 MHz 250 MHz 300 MHz TEMPERATURE RANGE DEFAULT 0 TO 90 Blank 0 C to 90 C commercial temperature A 40 to 105 C extended temperature PACKAGE TYPET N CLE DIP Y J Ceramic DIP TECHNOLOG JD Ceramic DIP side brazed C CMOS GB Ceramic PGA E 5 EPROM FZ Ceramic CC F CMOS Flash EEPROM FN Plastic leaded CC FD Ceramic leadless PJ 100 pin plastic EIAJ QFP PQ 132 plastic bumpered QFP PZ 100 plastic PBK 128 pin plastic TQFP PGE 144 pin plastic TQFP t DIP Dual In Line Package P
51. clock frequency input clock frequency x4 or x1 Er 71 on JTAG EMULATION vs i test port mode select features TD Tars va 1 test port data in eaturesanintemalpulup Tok _ TRT ans features an intemal puldqow RESET AND INTERRUPTS REET 12 pa I interrupt Edge driven rising edge INT7 EXT_ EXT_INT6 Y2 U Y2 External interrupts EXT_INTS AA AA Edge driven rising edge INT4 W4 IACK Interrupt acknowledge for all active interrupts serviced by the CPU INUM3 TI Active interrupt identification number e Valid during IACK for all active interrupts not just external e Encoding order follows the interrupt service fetch packet ordering a RH we POWER DOWN STATUS PD AB2 Y2 O Power down modes 2 or 3 active if high 1 Input O Output Z High Impedance Supply Voltage GND Ground t PLLV and PLLG are not part of external voltage supply or ground See the clock PLL section for information on how to connect these pins Analog Signal PLL Filter 1l For emulation and normal operation pull up EMU1 and EMUO with a dedicated 20 kQ resistor For boundary scan pull down EMU1 and EMUO with a dedicated 20 kO resistor 5 INSTRUMENTS POST OFFICE BOX 1443 HOUSTON
52. data is generated one CLKOUT2 cycle early to accommodate the ED enable time o o 2 o o 2 z 2 2 o o o o 2 o 2 o 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 35 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 SYNCHRONOUS BURST MEMORY TIMING CONTINUED AC Z N AV NA N N N N N S 1 3 4 BE 3 0 X BE XBE _X BE4 EA2 2 X A A X M 01 X Q2 X G3 X Q4 K gt 10 SDCAS SSADST lt 12 SDRAS SSOEt SDWE SSWET ED 31 0 T SDCAS SSADS SDRAS SSOE and SDWE SSWE operate as SSADS SSOE and SSWE respectively during SBSRAM accesses Figure 15 SBSRAM Read Timing CLKOUT2 4 2 a gt 4 BE 3 0 m gt 6 3 _ X BE X BES X BEA 21 2 2 X X 4 13 A 02 A Q A 04 lt 4 14 gt 9 gt 10 SDCAS SSADST SDRAS SSOET ED 31 0 5 lt gt 16 SDWE SSWET t SDCAS SSADS SDRAS SSOE and SDWE SSWE operate as SSADS SSOE and SSWE respectively during SBSRAM accesses Figure 16 SBSRAM Write Timing 35 TEXAS INSTRUMENTS 36 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202
53. e 1 Timer orgeneralpurpseinpt OOOO DMA ACTION COMPLETE STATUS DMAC3 zn DMAC2 AA2 DMAC1 AB1 MULTICHANNEL BUFFERED SERIAL PORT 0 McBSPO __ Externa look source as opposed to tema T D Re u _ MULTICHANNEL BUFFERED SERIAL PORT 1 McBSP1 clock source as opposed to tema T om ia wr 1 11 Input O Output Z High Impedance S Supply Voltage GND Ground DMA action complete 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 15 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 Signal Descriptions Continued SIGNAL T DESCRIPTION e MULTICHANNEL BUFFERED SERIAL PORT 2 McBSP2 1 __TExtemal clock source as opposed to nema OS gg vw e RESERVED FOR TEST Svo i3 1 Reserved for testing pulup wih a dedicaa sv ES Resevedfertestno pulupwihadedcaedzDk ressor BH Resevedfortestno pulup wih a dedioated 20x ressor nsvs Reserved eave unconnected do not connect power or ground 2 Reserved leave unconnected do not connect power or ground SUPPLY VOLTAGE PINS 3 3 V supply voltage 11 Input O Output Z High Impedance S Supply
54. ese prefixes represent evolutionary stages of product development from engineering prototypes TMX TMDX through fully qualified production devices tools TMS TMDS Device development evolutionary flow TMX Experimental device that is not necessarily representative of the final device s electrical specifications TMP Final silicon die that conforms to the device s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow TMDX Development support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development support product TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluation purposes TMS devices and TMDS development support tools have been characterized fully and the quality and reliability of the device have been demonstrated fully Tl s standard warranty applies Predictions show that prototype devices TMX or TMP have a greater failure rate than the standard production devices Texas Instruments recommends that these devices not be used in any production system because their expected end use failure rate still is undefined Only qualified production devices are to be used Tl device nomenclature also includes a suffix with the device family name This suffix indic
55. g then the minimum delay time can be achieved Also bus hold can be indefinitely delayed by setting NOHOLD 1 External Requestor Owns Bus k 3 5 13 22 DSP Owns Bus DSP Owns Bus 2 4 544 5 1 gt EMIF Bust Bus consists of CE 3 0 3 0 ED 31 0 EA 21 2 ARE AOE AWE SDCAS SSADS SDRAS SSOE SDWE SSWE and SDA10 Figure 23 HOLD HOLDA Timing HOLDA 4 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 41 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 RESET TIMING timing requirements for reset see Figure 24 6202 200 6202 233 C6202 250 UNIT MIN Width of the RESET pulse stable t 1 tw RST y Width of the RESET pulse PLL needs to sync up t 250 us LKOUT1 tsu XD Setup time XD configuration bits valid before RESET high 5 LKOUT1 th XD Hold time XD configuration bits valid after RESET high e 5 T This parameter applies to CLKMODE x1 when is stable and applies to CLKMODE x4 when CLKIN and PLL are stable t This parameter only applies to CLKMODE x4 The RESET signal is not connected internally to the clock PLL circuit The PLL however may need up to 250 us to stabilize following device power up or after PLL configuration has been changed
56. gure 36 and Figure 37 uyest xov Delay time Delay time XADY low t9 XDxval 7 Delay ime KOS igh o XRDY nig 1 gt lt 1 gt ke 2 gt 10 10 XCS EEG Ema III 3 gt 3 4 4 xr 3 0 5 2 ZI E c lt 3 k 3 4 4 k 7 5 le 8 gt 6 5 gt 8 je gt 6 XD 31 0 C A Word X J L AX X 9 9 XRDY t XBE 3 0 XA 5 2 operates as byte enables XBE 3 0 during host port accesses tXW R input output polarity selected at boot Figure 36 External Device as Asynchronous Master Read 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 55 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 EXPANSION BUS ASYNCHRONOUS HOST PORT TIMING CONTINUED 10 je 1 gt 2 gt 10 xcs TS L lt gt 3 4 m4 X X X amp 11 11 lt 2 H1 2 0 5 2 HEEE gt 3 4 XR WT 4 4 XR Wt 6 13 6 13 39 1 4 HI 4 XD 31 0 gt 9 k 9 XRDY t XBE 3 0 XA 5 2 operates
57. high switching characteristics for JTAG test port see Figure 49 C6202 200 C6202 233 PARAMETER mm 250 UNIT d TCKL TDOV Delay time low to valid 2 2 I w TDI TMS TRST Figure 49 JTAG Test Port Timing 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 7i ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 GJL S PBGA N352 MECHANICAL DATA PLASTIC BALL GRID ARRAY 27 20 sQ 26 80 25 20 lt gt SQ gt 24 80 4 16 30 NOM gt Y oooo o Ooo U o ooo E oooo M L oooo K J H oooo E oooo 00000000000
58. ler linker and other tools used to develop assembly language code assembler directives macros common object file format and symbolic debugging directives for the C6000 generation of devices TMS320C6x Evaluation Module Reference Guide literature number SPRU269 provides instructions for installing and operating the C6x evaluation module It also includes support software documentation application programming interfaces and technical reference material TMS320C62x Multichannel Evaluation Module User s Guide literature number SPRU285 provides instructions for installing and operating the C62x multichannel evaluation module It also includes support software documentation application programming interfaces and technical reference material TMS320C62x Multichannel Evaluation Module Technical Reference SPRU308 provides provides technical reference information for the C62x multichannel evaluation module McEVM It includes support software documentation application programming interface references and hardware descriptions for the C62x TMS320C6000 DSP BIOS User s Guide literature number SPRU303 describes how to use DSP BIOS tools and APIs to analyze embedded real time DSP applications Code Composer User s Guide literature number SPRU296 explains how to use the Code Composer development environment to build and debug embedded real time DSP applications Code Composer Studio Tutorial literature number SPRU3
59. lways active low 5 3 0 5 2 operates as byte enables XBE 3 0 during host port accesses TXWE XWAIT operates as XWAIT output signal during host port accesses Figure 33 C6202 as Bus Master Read ima CUI ied E an YE n W q 5 nPO gt 2 gt 2 xwiRt T gt H 63 gt 3 XBLASTT xC ss s N je 4 gt 4 XBEBS XA 28 TN gt 7 A pae Alke XD 31 0 C X Adr X DT A 92 03 JA 94 X k 11 gt 12 LX eee 13 13 Xw RT XWE XWAIT I T XW R input output polarity selected at boot tXBLAST output polarity is always active low XBE 3 0 XA 5 2 operates as byte enables XBE 3 0 during host port accesses TXWE XWAIT operates as XWAIT output signal during host port accesses Figure 34 C6202 as Bus Master Write 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 53 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING CONTINUED XCLKIN f W Vf A Af f NX NX XAS XW RT jjj 2 lt 2 1 417 r XBLAST gt 4 lt 4 3 0 5 2 8
60. ost port accesses switching characteristics with external device as bus master see Figure 31 and Figure 32 td XCKIH XDIV Delay time XCLKIN high to XDx invalid 1 td XCKIH XRYHZ Delay time XCLKIN high to XRDY high impedance ADVANCE INFORMATION 1 CPU clock frequency in ns For example when running parts at 250 MHz use 4 ns TP XRDY operates as active low ready input output during host port accesses 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 49 ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS HOST PORT TIMING CONTINUED N V A AA VA NS gt 2 1 xente 74 xw Rf vs 4 8 8 1 9 lt 10 xass 10 9 3 xass 0 __ __ ______ gt 13 nt 7 die List 14 XD 31 0 X51 C 92 4 221 eta Txw R input output polarity selected at boot t 3 0 5 2 operates as byte enables XBE 3 0 during host port accesses 5 XBLAST input polarity selected at boot operates as active low ready input output during host port accesses Figure 31 External Host as Bus Master Read 49 5 I
61. r circular addressing modes with 5 or 15 bit offsets All instructions are conditional and most can access any one of the 32 registers Some registers however are singled out to support specific addressing or to hold the condition for conditional instructions if the condition is not automatically true The two M functional units are dedicated for multiplies The two S L functional units perform a general set of arithmetic logical and branch functions with results available every clock cycle The processing flow begins when a 256 bit wide instruction fetch packet is fetched from a program memory The 32 bit instructions destined for the individual functional units are linked together by 1 bits in the least significant bit LSB position of the instructions The instructions that are chained together for simultaneous execution up to eight in total compose an execute packet A 0 in the LSB of an instruction breaks the chain effectively placing the instructions that follow it in the next execute packet If an execute packet crosses the fetch packet boundary 256 bits wide the assembler places it in the next fetch packet while the remainder of the current fetch packet is padded with NOP instructions The number of execute packets within a fetch packet can vary from one to eight Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256 bit fetch packet is not fetched
62. ranges of supply voltage and operating case temperature unless otherwise noted V PARAMETER TEST CONDITIONS MIN t TMS and TDI are not included due to internal pullups TRST is not included due to internal pulldown Measured with average CPU activity BD BD BD 50 of time 8 instructions per cycle 32 bit DMEM access per cycle 50 of time 2 instructions per cycle 16 bit DMEM access per cycle T Measured with average peripheral activity 50 of time Timers at max rate McBSPs at E1 rate DMA burst transfer betveen DMEM and SDRAM 50 of time Timers at max rate McBSPs at E1 rate DMA servicing McBSPs Measured with average I O activity 30 pF load SDCLK on 25 of time Reads from external SDRAM 25 of time Writes to external SDRAM 50 of time No activity 35 TEXAS INSTRUMENTS 28 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 PARAMETER MEASUREMENT INFORMATION 1 ES yo Tester Pin Electronics Output V Under ref Test 30 T Typical distributed load circuit capacitance signal transition levels All input and output timing parameters are referenced to 1 5 V for both 0 and 1 logic levels Vref 1 5 V Figure 7 Input and Output Voltage Reference Levels for ac Timing Measurements 5 TEXAS INSTRUME
63. s SDCAS SDRAS and SDWE respectively during SDRAM accesses Figure 18 Three SDRAM WRT Commands 35 TEXAS INSTRUMENTS 38 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 SYNCHRONOUS DRAM TIMING CONTINUED 1 2 CEx _ 72707 E 1 5 EA i5 2 1 A BankActivate Row Address EDD1 0 le 15 SDA10l 4 Row Address 4 17 gt 4 18 SDRAS SSOET _ SDCAS SSADST SDWE SSWET t SDCAS SSADS SDRAS SSOE and SDWE SSWE operate as SDCAS SDRAS SDWE respectively during SDRAM accesses Figure 19 SDRAM ACTV Command SDCAS SSADST SDWE SSWET lt 14 t SDCAS SSADS SDRAS SSOE SDWE SSWE operate as SDCAS SDRAS SDWE respectively during SDRAM accesses Figure 20 SDRAM DCAB Command 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 39 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 SYNCHRONOUS DRAM TIMING CONTINUED SDWE SSWET T SDCAS SSADS SDRAS SSOE and SDWE SSWE operate as SDCAS SDRAS and SDWE respectively during SDRAM accesses Figure 21 SDRAM REFR Command j MRS XA 12 BE 3 0 mm
64. terrupts TMS320C6000 Peripherals Reference Guide literature number SPRU190 describes the functionality of the peripherals available on C6x devices such as the external memory interface EMIF host port interface HPI multichannel buffered serial ports McBSPs direct memory access DMA enhanced direct memory access EDMA controller expansion bus XB clocking and phase locked loop PLL and power down modes This guide also includes information on internal data and program memories The TMS320C6000 Programmer s Guide literature number SPRU198 describes ways to optimize and assembly code for C6x devices and includes application program examples TMS320C6x Source Debugger User s Guide literature number SPRU1 88 describes how to invoke the simulator and emulator versions of the source debugger interface and discusses various aspects of the debugger including command entry code execution data management breakpoints profiling and analysis TMS320C6x Peripheral Support Library Programmer s Reference literature number SPRU273 describes the contents of the C6x peripheral support library of functions and macros It lists functions and macros both by header file and alphabetically provides a complete description of each and gives code examples to show how they are used TMS320C6000 Assembly Language Tools User s Guide literature number SPRU1686 describes the assembly language tools assemb
65. the EMI filter and PLLV must be from the same 3 3 V power plane supplying the I O voltage DVpp EMI filter manufacturer TDK part number ACF451832 153 T CLKMODE2 and CLKMODE 1 exist only on the GLS device There are no equivalent connections on the GJL device The reserved PLL clock modes GLS devices only may or may not be supported on future devices as additional PLL multiply factors For future flexibility a board can be designed so that these inputs are configurable either through jumpers switches or 0 resistors Figure 6 Block Diagram Table 3 TMS320C6202 PLL Component Selection Tablet CPU CLOCK koure TYPICAL CLKMODE FREQUENCY RANGE RI e LOCK TIME CLKOUT1 MHz us RANGE MHz 325 625 130 250 65 125 T Under some operating conditions the maximum PLL lock time may vary as much as 150 from the specified typical value For example if the typical lock time is specified as 100 us the maximum value may be as long as 250 us power supply sequencing The 1 8 V supply powers the core and the 3 3 V supply powers the buffers The core supply should be powered up first or at the same time as the I O buffers supply This is to ensure that the I O buffers have valid inputs from the core before the output buffers are powered up thus preventing bus contention with other chips on the board 35 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1
66. the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be are used 5 publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1999 Texas Instruments Incorporated
67. time CLKOUT1 high to XBE 3 0 XA 5 2 invalid td CKO1H XOEV ay time CLKOUT1 high to XOE valid 10 tg CKO1H XDV ay time CLKOUT1 high to XDx valid 11 taCKO1H XDIV ay time CLKOUT1 high to XDx invalid o 12 td cko1H xwEv Delay time CLKOUT1 high to XWE XWAIT valid t The minimum delay is also the minimum output hold after CLKOUT1 high 8 3 0 5 2 operates as address signals XA 5 2 during asynchronous peripheral accesses E De i i 5 De i i De i TXWE XWAIT operates as the write enable signal XWE during asynchronous peripheral accesses 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 47 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 EXPANSION BUS ASYNCHRONOUS PERIPHERAL TIMING CONTINUED Setup 2 Strobe 5 Not ready 2 HOLD 2 N NS XWE XWAIT 7 gt le i XRE _y 9 8 44 8 ye t XBE 3 0 3 0 5 2 operates as address signals XA 5 2 during asynchronous peripheral accesses tXWE XWAIT operates as the write enable signal XWE during asynchronous peripheral accesses XRDY operates as active high ready input during asynchronous peripheral accesses Figure 29 Expansion Bus Asynchronous Peripheral Read Timing
68. time XFCLK high to XDx invalid t XBE 3 0 XBE 3 0 XA 5 2 operates as address signals XA 5 2 during synchronous FIFO accesses tXWE XWAIT operates as the write enable signal XWE during synchronous FIFO accesses XFCLK Af CN C 1 1 XCE3T N XBE 3 0JXA 5 2 X X XA 4 XOE zgZ jii v k kjyjVvk e XRE XWE XWAITS 6 ge XD 31 0 C Di X 02 X D3 X 14 T FIFO read glueless mode only available in XCE3 t XBE 3 0 XA 5 2 operates as address signals XA 5 2 during synchronous FIFO accesses 5 XWE XWAIT operates as the write enable signal XWE during synchronous FIFO accesses Figure 26 FIFO Read Timing Glueless Read Mode vy TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 45 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 EXPANSION BUS SYNCHRONOUS FIFO TIMING CONTINUED N FF 3 0 5 2 XE 4 7 XWE XWAIT L 6 5 XD 31 0 C Di X D2 X 23 X 04 t XBE 3 0 XBE 3 0 XA 5 2 operates as address signals XA 5 2 during synchronous FIFO accesses tXWE XWAIT operates as the write enable signal XWE during synchronous FIFO accesses Figure 27 FIFO Read Timing Nf Wy ott fen XCex
69. us Arbitration Internal Arbiter Enabled 5 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 57 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 XHOLD XHOLDA TIMING CONTINUED switching characteristics for expansion bus arbitration internal arbiter disabled T see Figure 39 NO MIN UNIT td XHDAH XBLZ Delay time XHOLDA high to XBus low impedancet 2P 10 td XBHZ XHDL Delay time XBus high impedance to XHOLD low 1 CPU clock frequency in ns For example when running parts at 250 MHz use P 4 ns XBus consists of XBE 3 0 XA 5 2 XAS XW R and XBLAST 2 XHOLD output _ x 5 0 XHOLDA input N zm k na 1 xaust GB S T XBus consists of XBE 3 0 XA 5 2 XAS XW R and XBLAST Figure 39 Expansion Bus Arbitration lInternal Arbiter Disabled 49 5 INSTRUMENTS 58 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 5320 6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 MULTICHANNEL BUFFERED SERIAL PORT TIMING timing requirements for McBSPT see Figure 40 C6202 200 C6202 233 250 te CKRX Cycle time CLKR X CLKR X ext tw CKRX Pulse duration CLKR X high or CLKR X low CLKR X ext HEC 1 CLKR int tsu FRH CKRL X Setup time
70. xample when running parts at 250 MHz use P 4 ns SDCAS SSADS SDRAS SSOE and SDWE SSWE operate as SDCAS SDRAS SDWE respectively during SDRAM accesses For the first write in a series of one or more consecutive adjacent writes the write data is generated one CLKOUT2 cycle early to accommodate the ED enable time vy TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77251 1443 37 ADVANCE INFORMATION ADVANCE INFORMATION TMS320C6202 FIXED POINT DIGITAL SIGNAL PROCESSOR SPRS072B AUGUST 1998 REVISED AUGUST 1999 SYNCHRONOUS DRAM TIMING CONTINUED READ j READ READ N 3 0 X BE X X 6 EA 15 2 X X CA2 ui s gt ED 31 0 15 k 16 50190 SDRAS SSOET 8 4 10 SDCASSSADSI N SDWE SSWET t SDCAS SSADS SDRAS SSOE and SDWE SSWE operate as SDCAS SDRAS and SDWE respectively during SDRAM accesses Figure 17 Three SDRAM READ Commands WRITE WRITE WRITE HH 1 gt 2 4 __ O 6 52 O 1 2 11 12 C A D 2 A D ED 31 0 31 0 15 lt 16 SDA10 SDRAS SSOET k 9 6 10 SDCAS SSADST 6 13 14 SDWE SSWET T SDCAS SSADS SDRAS SSOE and SDWE SSWE operate a
71. xed point DSP family in the TMS320C6000 platform The TMS320C6202 C6202 device is based on the high performance advanced VelociTI very long instruction word VLIW architecture developed by Texas Instruments making this DSP an excellent choice for multichannel and multifunction applications With performance of up to 2000 million instructions per second MIPS at a clock rate of 250 MHz the C6202 offers cost effective solutions to high performance DSP programming challenges The C6202 DSP possesses the operational flexibility of high speed controllers and the numerical capability of array processors This processor has 32 general purpose registers of 32 bit word length and eight highly independent functional units The eight functional units provide six arithmetic logic units ALUS for a high degree of parallelism and two 16 bit multipliers for a 32 bit result The C6202 can produce two multiply accumulates MACs per cycle for total of 500 million MACs per second MMACS The C6202 DSP also has application specific hardware logic on chip memory and additional on chip peripherals The C6202 includes a large bank of on chip memory and has a powerful and diverse set of peripherals Program memory consists of two 128K byte blocks with one block configured as memory mapped program space and the other block user configured as cache or memory mapped program space Data memory consists of two 64K byte blocks of RAM The peripheral set

Texas Instruments TMS320C6202 User's Manual

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