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Texas Instruments TMS320C2802 User's Manual

1. 51 4 1 5 DEM VE EAE 53 4 2 CPU Timer Interrupt Signals and Output 4 4 1 4 mn nemen nnne 54 4 3 Multiple PWM Modules in 280x System nnn nnn nnn 55 4 4 ePWM Sub Modules Showing Critical Internal Signal Interconnections 57 4 5 eCAP Functional Block se neminem s 59 4 6 eQEP Functional Block hn hehehe hn heme he he 61 4 7 Block Diagram of the ADC Module 1 1 1 1 51 1 nessun 64 4 8 ADC Pin Connections With Internal Reference emen enemies nnne nennen 65 4 9 ADC Pin Connections With External Reference sess 66 4 10 eCAN Block Diagram and Interface 1 1 nemen sene 69 4 11 eCAN A Memory
2. 60 4 4 eQEP Control and Status Registers 41 1 44 4 1 lt 62 4 5 151678 m UEM 67 4 6 3 3 V eCAN Transceivers nun 69 4 7 IREGIStER c 72 4 8 iei 74 4 9 secreta cit 74 4 10 SPLA Registers 4 11 SPEB Beglsters sugu u a we D UAE 77 4 12 SPIC Registers e T 78 4 13 SPIED 78 4 14 2 Wil M 81 4 15 GPIO cun cp c 83 4 16 F2808 GPIO MUX Tale 84 5 1 TMS320x280x 2801x Peripheral Selection Guide 88 6 1 TMS320F2809 TMS320F2808 Current Consumption by Power Supply Pins at 100 MHz SYSCLKOUT 95 6 2 TMS320F2806 Current Consumption by Power Supply Pins at 100 MHz SYSCLKOUT
3. 103 6 7 Glock TIMING nm 106 6 8 1 107 Copyright 2003 2009 Texas Instruments Incorporated List of Figures 5 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TEXAS 5320 2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 6 9 lul CI 108 6 10 Example of Effect of Writing Into PLLCR Register mm nennen 109 6 11 General Purpose Q tp t Timing 2 eoe cose dote o oa I a REPE nea 110 6 12 Sampling 110 6 13 General Purp se Mpui TIMING 5 EO I RES DNE EIER cM DNE 111 6 14 IDLE Entry and Exit 0 1 II II HI HII hm hm e nenne ehh nmn nnne nnn 112 6 15 STANDBY Entry and Exit Timing a E E RUE basis siasa 113 6 16 HALT Wake Up GPION e a 114 6 17 PWM Hi Z Characteristics 2 4 115 6 18 ADCSOCAO or AD
4. FEATURE TYPE F2809 F2808 F2806 F2802 F2801 C2802 C2801 Instruction cycle at 100 MHz 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns 10 ns Single access RAM SARAM 16 bit word 10 uo M1 LO L1 Mo M1 Lo i MO T T Mo T du bo m Mo B T Mb 3 3 V on chip flash 16 bit word 128 64K 32K 32K 16K On chip ROM 16 bit word 32K 16K Code security for on chip flash SARAM OTP blocks Yes Yes Yes Yes Yes Yes Yes Boot ROM 4K x 16 Yes Yes Yes Yes Yes Yes Yes one OTP ROM _ 1K 1K PWM outputs 0 ePWM1 2 3 4 5 6 ePWM1 2 3 4 5 6 ePWM1 2 3 4 5 6 ePWM1 2 3 ePWM1 2 3 1 2 3 1 2 3 HRPWM channels 0 emer di T MR ePWM1A 2A 3A ePWM1A 2A 3A ePWM1A 2A 3A ePWM1A 2A 3A 32 bit CAPTURE inputs or auxiliary PWM outputs 0 eCAP 1 2 3 4 eCAP 1 2 3 4 eCAP1 2 3 4 eCAP1 2 eCAP1 2 eCAP1 2 eCAP1 2 32 bit QEP channels four inputs channel 0 eQEP1 2 eQEP1 2 eQEP1 2 eQEP1 eQEP1 eQEP1 eQEP1 Watchdog timer Yes Yes Yes Yes Yes Yes Yes 12 Bit 16 channel ADC conversion time 1 80 ns 160 ns 160 ns 160 ns 160 ns 160 ns 160 ns 32 Bit CPU timers 3 3 3 3 3 3 3 Serial Peripheral Interface SPI 0 SPI A B C D SPI A B C D SPI A B C D SPI A B SPI A B SPI A B SPI A B Serial Communications Interface SCI 0 SCI A B SCI A B SCI A B SCI A SCI A SCI A SCI A Enhanced Controller Area Network eCAN 0 eCAN A B eCAN A B eCAN A eCAN A eCAN A eCAN A eCAN A Inter Integrated Circuit I2C 0 2 2 2
5. 133 7 1 Migration ISSUCS M m 133 8 FREVISIONVPISTONY ama s qasa 134 9 Mechanical 2 2 135 4 Contents Copyright 2003 2009 Texas Instruments Incorporated TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 mecs TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 List of Figures 2 1 TMS320F2809 TMS320F2808 100 Pin PZ LQFP Top View 2 15 2 2 TMS320F2806 100 Pin PZ LQFP Top m 16 2 3 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 100 Pin PZ LQFP Top AY 2 4 TMS320F2801x 100 PZ LQFP Top View 1 nnn nennen 18 2 5 TMS320F2809 TMS320F2808 TMS320F 2806 TMS320F2802 TMS320F2801 TMS320F 28016 TMS320F28015 TMS320C2802 TMS320C2801 100 Ball and ZGM MicroStar BGA Bottom 18 3 1 Functional Block 1 26 3 2 F2809 Memory Map iss ira nisu vu rt rao echa nas ta
6. 96 6 3 TMS320F2802 TMS320F2801 Current Consumption by Power Supply Pins at 100 MHz SYSCLKOUT 87 6 4 TMS320C2802 TMS320C2801 Current Consumption by Power Supply Pins at 100 MHz SYSCLKOUT 98 6 5 Typical Current Consumption by Various Peripherals at 100 MHz 99 6 6 TMS320x280x Clock Table and Nomenclature 100 MHz 104 6 7 TMS320x280x 2801x Clock Table and Nomenclature 60 2 Devices 104 6 8 P DD pm 105 Copyright 2003 2009 Texas Instruments Incorporated List of Tables 7 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TEXAS 5320 2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 6 9 XCLKIN Timing Requirements PLL Enabled nennen 105 6 10 XCLKIN Timing Requirements PLL Disabled 1 2 1 1 4 6 nnn 105 6 11 XCLKOUT Switching Characteristics PLL Bypassed or Enabled 105 6 12 Power Management and Supervisory Circuit Solutions 21 4 4 2 4224 lt 106 6 13 Reset XRS Timing Requirements
7. rcc 82 5 p Ele 86 5 1 Device and Development Support Tool Nomenclature 2 86 5 2 Documentation 88 6 Electrical Specifications uu E 93 6 1 Absolute Maximum Ratings 93 6 2 Recommended Operating Conditions 94 6 3 Electrical Characteristics 6 sena 94 6 4 Consumption 95 6 4 1 Reducing Current Consumption 99 6 4 2 Current Consumption Graphs 4 4 4 4 1 4 lt 100 6 5 Emulator Connection Without Signal Buffering for the DSP 102 6 6 Timing Parameter Symbology heme hene nnn nnne nenne enn nnn 103 6 6 1 General Notes on Timing Parameters 103 6 6 0 Test Load Circuit 4 ss meses 103 6 6 3
8. 7 3 lopais Ippa33 4 TYP MAX 9 5 MAX MAX TYPO MAX 9 Operational Flash The following peripheral clocks are enabled 1 2 3 4 5 6 eCAP1 2 3 4 eQEP1 2 eCAN A SCI A B SPIA ADC 2 All PWM pins toggled at 100 kHz All I O pins are left unconnected Data is continuously transmitted out of the SCI A SCI B and eCAN A ports The hardware multiplier is exercised Code is running out of flash with 3 wait states XCLKOUT is turned off 195 mA 230 15 27 35 40 30 38 1 5 2 mA IDLE Flash is powered down XCLKOUT is turned off The following peripheral clocks are enabled eCAN A SPI A 120 75 mA 90 mA 500 uA 2mA 2 10 pA 5 50 uA 15 30 pA STANDBY Flash is powered down Peripheral clocks are off 6mA 12 mA 100 pA 500 pA 2 uA 10 pA 5 50 uA 15 30 pA HALT Flash is powered down Peripheral clocks are off Input clock is disabled 70 uA 60 uA 120 uA 2yA 10 pA 5 50 uA 15 30 1 lppio current is dependent on the electrical loading on the I O pins 2 The _ current indicated in this table is the flash read current and does not include additional current for erase write operations During flash prog
9. 53 4 2 Enhanced PWM Modules ePWM1 2 3 4 5 6 2 2 4 4 1 2 2 4 4472 2 2 4444 2 0 55 4 3 FisResol tion PWM HRPWMM 2 uuu 58 2 Contents Copyright 2003 2009 Texas Instruments Incorporated TMS320F2809 TMS320F2808 TMS320F2806 Texas TMS320F2802 TMS320F2801 TMS320C2802 i TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 4 4 Enhanced CAP Modules CCAP 1 2 3 4 2 4 1 lt nnne 58 4 5 Enhanced QEP Modules eQEP 1 2 MUR e a 61 4 6 Enhanced Analog to Digital Converter ADC Module 63 4 6 1 Connections if the ADC Is Not Used 2 4 66 4 6 2 ADC RegiSlers cusa YR RR EE acu 67 4 7 Enhanced Controller Area Network eCAN Modules eCAN A and eCAN B 68 4 8 Serial Communications Interface SCI Modules SCI A SCI B 0 2 73 4 9 Serial Peripheral Interface SPI Modules SPI A SPI B SPI C SPI D 76 4 10 IInter Itegrated Circult I2O iei mim ia sateen ici fme ul hole mnis 80
10. Figure 6 26 Sequential Sampling Mode Single Channel Timing Table 6 41 Sequential Sampling Mode Timing AT 12 5 MHz SAMPLE n SAMPLE n 1 ADC CLOCK REMARKS tc apccik 80 ns ta SH Delay time from event trigger to 2 5tc ADCCLK sampling tsu Sample Hold width Acquisition 1 Acqps 80 ns with 0 Acaps value 0 15 Width c ADCCLK ADCTRL1 8 11 ta schx_n Delay time for first result to appear 4tc apccik 320 ns in Result register ta schx_n 1 Delay time for successive results to 2 160 ns appear in Result register c ADCCLK 128 Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 Pe Rees TMS320C2801 TMS320F28016 TMS320F28015 6 10 7 4 Simultaneous Sampling Mode Dual Channel SMODE 1 In simultaneous mode the ADC can continuously convert input signals on any one pair of channels A0 BO to A7 B7 The ADC can start conversions on event triggers from the ePWM software trigger or from an external ADCSOC signal If the SMODE bit is 1 the ADC will do conversions on two selected channels on every Sample Hold pulse The conversion time and latency of th
11. 5 INSTRUMENTS www ti com Table 2 2 Hardware Features 60 MHz Devices TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 FEATURE TYPE F2802 60 F2801 60 F28016 F28015 Instruction cycle at 60 MHz 16 67 ns 16 67 ns 16 67 ns 16 67 ns Single access RAM SARAM 16 bit word LO Mo M1 LO Mo M1 LO 1 LO 1 3 3 V on chip flash 16 bit word 32K 16K 16K 16K On chip ROM 16 bit word Code security for on chip flash SARAM OTP blocks Yes Yes Yes Yes Boot ROM 4K x 16 Yes Yes Yes Yes 222 7 OTP ROM PWM outputs 0 ePWM1 2 3 ePWM1 2 3 ePWM1 2 3 4 ePWM1 2 3 4 HRPWM channels 0 ePWM1A 2A 3A ePWM1A 2A 3A ePWM1A 2A 3A 4A ePWM1A 2A 3A 4A 32 bit CAPTURE inputs or auxiliary PWM outputs 0 eCAP1 2 eCAP1 2 eCAP1 2 eCAP1 2 32 bit QEP channels four inputs channel 0 eQEP1 eQEP1 Watchdog timer Yes Yes Yes Yes No of channels 16 16 16 16 12 Bit ADC MSPS 1 3 75 3 75 3 75 3 75 Conversion time 267 ns 267 ns 267 ns 267 ns 32 Bit CPU timers 3 3 3 3 Serial Peripheral Interface SPI 0 SPI A B SPI A B SPI A SPI A Serial Communications Interface 5 0 SCI A SCI A SCI A SCI A Enhanced Controller Area Network eCAN 0 eCAN A eCAN A eCAN A Inter In
12. 14 tw SPCL S Pulse duration SPICLK low clock polarity 0 0 5tspcjs 10 0 5tgspc s h tw SPCH S Pulse duration SPICLK high clock polarity 1 0 5tspcjs 10 0 15 ta SPCH SOMI S Delay time SPICLK high to SPISOMI valid clock polarity 0 35 ng ta SPCL SOMI S Delay time SPICLK low to SPISOMI valid clock polarity 1 35 18 tv SPCL SOMI S Valid time SPISOMI data valid after SPICLK low clock polarity 0 0 75 tv SPCH SOMI S Valid time SPISOMI data valid after SPICLK high clock polarity 1 0 75tcsPC s 19 tsu SIMO SPCL S Setup time SPISIMO before SPICLK low clock polarity 0 35 T tsu SIMO SPCH S Setup time SPISIMO before SPICLK high clock polarity 1 35 50 tv SPCL SIMO S Valid time SPISIMO data valid after SPICLK low clock polarity 0 O 5tcspc s 10 us tv SPCH SIMO S Valid time SPISIMO data valid after SPICLK high clock polarity 1 O 5tcspojs 10 1 The MASTER SLAVE bit SPICTL 2 is cleared and the CLOCK PHASE bit SPICTL 3 is cleared 2 SPI clock cycle time LSPCLK 4 or LSPCLK SPIBRR 1 3 Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate Master mode transmit 25 MHz MAX master mode receive 12 5 MHz MAX Slave mode transmit 12 5 MHz MAX slave mode receive 12 5 MHz MAX teco LSPCLK cycle time 5 The active edge of the SPICLK signal referenced is controlled by the C
13. A SPISTE is driven low by the master for a slave device Figure 4 14 SPI Module Block Diagram Slave Mode Copyright 2003 2009 Texas Instruments Incorporated Peripherals 79 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 ees SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 4 10 Inter Integrated Circuit 12C 80 280x device contains one 2 Serial Port Figure 4 15 shows how the 2 peripheral module interfaces within the 280x device The 2 module has the following features Compliance with the Philips Semiconductors I2C bus specification version 2 1 Support for 1 bit to 8 bit format transfers T bit and 10 bit addressing modes General call START byte mode Support for multiple master transmitters and slave receivers Support for multiple slave transmitters and master receivers Combined master transmit receive and receive transmit mode Data transfer rate of from 10 kbps up to 400 kbps I2C Fast mode rate One 16 word receive FIFO and one 16 word transmit FIFO Oneinterrupt that can be used by the CPU This interrupt can be generated as a result of one of the following conditions Transmit data ready
14. tw WAKE GPIo 74 gt _ tp gt X1 X2 or XCLKIN Oscillator Start up Time XCLKOUT M td IDLE XCOL A instruction is executed to put the device into HALT mode B The PLL block responds to the HALT signal SYSCLKOUT is held for approximately 32 cycles if CLKINDIV 0 or 64 cycles if CLKINDIV 1 before the oscillator is turned off and the CLKIN to the core is stopped This delay enables the CPU pipe and any other pending operations to flush properly C Clocks to the peripherals are turned off and the PLL is shut down If a quartz crystal or ceramic resonator is used as the clock source the internal oscillator is shut down as well The device is now in HALT mode and consumes absolute minimum power D When the GPIOn pin used to bring the device out of HALT is driven low the oscillator is turned on and the oscillator wake up sequence is initiated The GPIO pin should be driven high only after the oscillator has stabilized This enables the provision of a clean clock signal during the PLL lock sequence Since the falling edge of the GPIO pin asynchronously begins the wakeup process care should be taken to maintain a low noise environment prior to entering and during HALT mode E Once the oscillator has stabilized the PLL lock sequence is initiated which takes 131 072 OSCCLK X1 X2 or X1 or XCLKIN cycles Note that these 131 072 clock cycles are
15. ra REV ula NLIS sisa atasi susan 27 3 3 2808 Memory 1 1 1 4 6 28 3 4 2806 Map uu 29 3 5 F2802 G2802 Memory Map m 30 3 6 F2801 F28015 F28016 C2801 Memory 30 3 7 External and PIE Interrupt Saa aaa asa me sisse messe sese sese sene 44 3 8 Multiplexing of Interrupts Using the PIE Block 44 3 9 Clock and Reset Domains 1 1 11 1 66 6 66 46 3 10 OSG and PLL Block nemen ese 47 3 11 Using 3 3 V External 1 2 lt me heme he nnns sense sinensis 48 3 12 Using a 1 8 V External 1 nennen emen nnn 48 3 13 Using the Internal Oscillator E heme memesi ness sss ness nnn 48 3 14 Watchdog
16. 40 to 85 C S version ZGM PZ 40 to 125 C Q version PZ 40 to 125 C Junction temperature range Ty 40 C to 150 C Storage temperature range Tstg 65 to 150 C 1 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Section 6 2 is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability All voltage values are with respect to Vas unless otherwise noted 3 Continuous clamp current per pin is 2 mA This includes the analog inputs which have an internal clamping circuit that clamps the voltage to a diode drop above Vppa2 or below Vssao 4 Long term high temperature storage and or extended use at maximum temperature conditions may result in a reduction of overall device life For additional information see C Package Thermal Metrics Application Report literature number SPRA953 and Reliability Data for TMS320LF24xx and TMS320F28xx Devices Application Report literature number SPRA963 Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 5320 28016 TMS320F28015 Electrical Specific
17. 5320 2806 5320 2802 TMS320F2801 5320 2802 5320 2801 5320 28016 5320 28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 TEXAS INSTRUMENTS www ti com Signal Descriptions continued PIN NO NAME pz GGM DESCRIPTION PIN ZGM BALL Internal External Oscillator Input To use the internal oscillator a quartz crystal or a ceramic resonator may be connected across X1 and X2 The X1 pin is referenced to the 1 8 V core digital X1 88 E6 power supply A 1 8 V external oscillator may be connected to the X1 pin In this case the XCLKIN pin must be connected to ground If a 3 3 V external oscillator is used with the XCLKIN pin X1 must be tied to GND I x2 86 C6 Internal Oscillator Output A quartz crystal or a ceramic resonator may be connected across X1 and X2 If X2 is not used it must be left unconnected O RESET Device Reset in and Watchdog Reset out Device reset 5 causes the device to terminate execution The PC will point to the address contained at the location When XRS is brought to a high level execution begins at the XRS 78 B8 location pointed to by the PC This pin is driven low by the DSP when a watchdog r
18. Figure 4 4 ePWM Sub Modules Showing Critical Internal Signal Interconnections Copyright 2003 2009 Texas Instruments Incorporated Peripherals 57 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 5320 2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 ee SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 4 3 Hi Resolution PWM HRPWM The HRPWM module offers PWM resolution time granularity which is significantly better than what can be achieved using conventionally derived digital PWM methods The key points for the HRPWM module are Significantly extends the time resolution capabilities of conventionally derived digital PWM Typically used when effective PWM resolution falls below 9 10 bits This occurs at PWM frequencies greater than 200 kHz when using a CPU System clock of 100 MHz This capability can be utilized in both duty cycle and phase shift control methods Finer time granularity control or edge positioning is controlled via extensions to the Compare A and Phase registers of the ePWM module HRPWM capabilities are offered only on the A signal path of an ePWM module i e on the EPWMxA output EPWMXxB output has conventional PWM capabilities 4 4 Enhanced CAP Modules eCAP1 2 3 4 The 280x device c
19. Mailbox 4 RX Control CANRIOC Time Stamp Counter CANTSC Time Out Control CANTOC Time Out Status CANTOS 61E0h 61E7h Mailbox 28 61E8h 61EFh Mailbox 29 61FOh 61F7h Mailbox 30 61F8h 61FFh Mailbox 31 Reserved Message Mailbox 16 Bytes Message Identifier MSGID 61EAh 61EBh Message Control MSGCTRL 61ECh 61EDh Message Data Low MDL 61EEh 61EFh a i uuu Message Data High Figure 4 11 eCAN A Memory Map If the eCAN module is not used in an application the RAM available LAM MOTS MOTO and mailbox RAM can be used as general purpose RAM The CAN module clock should be enabled for this 70 Peripherals Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 5 INSTRUMENTS www ti com eCAN B Memory 512 Bytes 6200h Control and Status Registers 623Fh 6240h Local Acceptance Masks LAM 627Fh 32 x 32 Bit RAM 6280h Message Object Time Stamps MOTS 62BFh 32 x 32 Bit RAM 62C0h Message Object Time Out MOTO 62FFh 32 x 32 Bit RAM eCAN B Memory RAM 512 Bytes 6300h 6307h Mailbox 0 6308h 630Fh Mailbox 1 6310h 6317h Mailbox 2 6318h 631Fh Mailbox 3 6320h 6327h Mailbox 4
20. 4 ta WAKE IDLE Address Data o internal s XCLKOUT N Z N Z N Z NZ N Z tw WAKE IN n WAKE INT A A WAKE INT can be any enabled interrupt WDINT XNMI or XRS Figure 6 14 IDLE Entry and Exit Timing 112 Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 Table 6 18 STANDBY Mode Timing Requirements TEST CONDITIONS MIN NOM UNIT Pulse duration external Without input qualification tw WAKE INT k ignal NR cycles wake up signa With input qualification 2 QUALSTDBY tcosccug 1 QUALSTDBY is a 6 bit field in the LPMCRO register Table 6 19 STANDBY Mode Switching Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Delay time IDLE instruction Q IDLE XCOL to XCLKOUT low 3214500 45tesco cycles Delay time external wake signal to program execution resume Wake up from flash Without input qualifier 100tc scoy Flash module in active zx 9 cycles
21. 5320 2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 5320 2801 TMS320F28016 TMS320F28015 Digital Signal Processors Data Manual X TEXAS INSTRUMENTS PRODUCTION DATA information is current as of publication date Instruments standard warranty Production processing does not necessarily include testing of all parameters Literature Number SPRS230L October 2003 Revised December 2009 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com Contents 1 F280x 2801 C280x DSPS 9 1 1 cuc M 9 10 Getting Started e 10 2 Inirod ctio Ee ES 11 2 1 Pin On 14 2 2 SiglialDes riptigriS ese 19 3 5 ccna 25 3 1 Memory RETE TITOLO LT LL ILI 26 3 2 Brief 34 3 2 1 eciam 34 3 2 2 Memory Bus Harvard Bus Architecture 34 3 2 8 Peripheral Bus nemen
22. 60 100 MHz MIN TYP MAX UNIT Micro Edge Positioning MEP step size 150 310 ps 1 Maximum MEP step size is based on worst case process maximum temperature and maximum voltage MEP step size will increase with low voltage and high temperature and decrease with voltage and cold temperature Applications that use the HRPWM feature should use MEP Scale Factor Optimizer SFO estimation software functions See the software libraries for details of using SFO function in end applications SFO functions help to estimate the number of MEP steps per SYSCLKOUT period dynamically while the HRPWM is in operation Table 6 26 shows the eCAP timing requirement and Table 6 27 shows the eCAP switching characteristics Table 6 26 Enhanced Capture eCAP Timing Requirement TEST CONDITIONS MIN MAX UNIT tw CAP Capture input pulse width Asynchronous 2lc sco cycles Synchronous 2tctsco With input qualifier twiasw 1 For an explanation of the input qualifier parameters see Table 6 15 Table 6 27 eCAP Switching Characteristics PARAMETER TEST CONDITIONS MIN MAX UNIT Pulse duration APWMx output high low 20 ns lw APWM Table 6 28 shows the eQEP timing requirement and Table 6 29 shows the eQEP switching characteristics Table 6 28 Enhanced Quadrature Encoder Pulse eQEP Timing Requirements
23. lt ADCINA7 gt 12 Bit Result Reg 7 70AFh ADC Module Result Reg 8 70 0 ADCINBO ADCINB7 Result Reg 15 70B7h ADC Control Registers S W EPWMSOCA Sequencer 1 Sequencer 2 GPIO XINT2 _ADCSOC S W EPWMSOCB Figure 4 7 Block Diagram of the ADC Module To obtain the specified accuracy of the ADC proper board layout is very critical To the best extent possible traces leading to the ADCIN pins should not run in close proximity to the digital signal paths This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs Furthermore proper isolation techniques must be used to isolate the ADC module power pins VppiA18 Vopeats gt Vppaio from the digital supply Figure 4 8 shows the ADC pin connections for the 280x devices NOTE 1 The ADC registers are accessed at the SYSCLKOUT rate The internal timing of the ADC module is controlled by the high speed peripheral clock HSPCLK 2 The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows ADCENCLK On reset this signal will be low While reset is active low XRS the clock to the register will still function This is necessary to make sure all registers and modes go into their default reset state The analog module however will be in a low power inactive state As soon as reset goes high then the clock to the registers will be disabled When the user sets the AD
24. nga cene nane Rak Ra Ray Ra OR eR gc Na DA aaa 108 6 14 General Purpose Output Switching 109 6 15 General Purpose Input Timing Requirements nnne nn nnn 110 6 16 IDLE Mode Timing Requirements enn nnn nnn kann anne nenas nen anne 112 6 17 IDLE Mode Switching Characteristics 4 166 112 6 18 STANDBY Mode Timing Requirements nn nnns nnn nn 113 6 19 STANDBY Mode Switching Characteristics 2 2 4 1 41 212 12641 113 6 20 HALT Mode Timing Requirements r 114 6 21 HALT Mode Switching Characteristics 114 6 22 ePWM Timing Requirements GR iaa RR UTR OF Ri TR RUE 115 6 23 ePWM Switching Characteristics 5 6 nn 115 6 24 Trip Zone input Ti
25. www ti com Table 6 6 TMS320x280x Clock Table and Nomenclature 100 MHz Devices MIN NOM MAX UNIT On chip oscillator tos Cycle time 28 6 50 ns clock Frequency 20 35 MHz XCLKIN Cycle time 10 250 ns Frequency 4 100 MHz SYSCLKOUT tesco Cycle time 10 500 ns Frequency 2 100 MHz XCLKOUT tcxco Cycle time 10 2000 ns Frequency 0 5 100 MHz 5 teco Cycle time 10 20 ns Frequency 50 100 MHz TOT teco Cycle time 10 40 ns Frequency 2509 100 MHz te ADCCLK Cycle time All devices except F2809 80 ns ADC clock Frequency All devices except F2809 12 5 MHz cloc tc ApccLk Cycle time F2809 40 ns Frequency F2809 25 MHz 1 This also applies to the X1 pin if a 1 8 V oscillator is used 2 Lower LSPCLK and HSPCLK will reduce device power consumption 3 This is the default reset value if SYSCLKOUT 100 MHz Table 6 7 TMS320x280x 2801x Clock Table and Nomenclature 60 MHz Devices MIN NOM MAX UNIT On chip oscillator Cycle time 28 6 50 ns clock Frequency 20 35 MHz XCLKIN Cycle time 16 67 250 ns Frequency 4 60 MHz tesco Cycle time 16 67 500 ns SYSCLKOUT Frequency 2 60 MHz XCLKOUT tcxco Cycle time 16 67 2000 ns Frequency 0 5 60 MHz teco Cycle time 16 67 33 30 ns Frequency 30 60 MHz Cycle time 16 67 667 ns
26. 0x697F 64 eCAP1 Registers 0x6A00 Ox6A1F 32 eCAP2 Registers 0x6A20 32 eCAP3 Registers 0 6 40 Ox6A5F 32 Not EALLOW protected eCAP4 Registers 0x6A60 7 32 eQEP1 Registers 0x6B00 OxeB3F 64 eQEP2 Registers 0x6B40 0x6B7F 64 GPIO Control Registers Ox6F80 Ox6FBF 128 EALLOW protected GPIO Data Registers Ox6FCO 0x6F DF 32 Not EALLOW protected GPIO Interrupt and LPM Select Registers Ox6FEO0 Ox6FFF 32 EALLOW protected 1 The eCAN control registers only support 32 bit read write operations All 32 bit accesses are aligned to even address boundaries 2 Missing segments of memory space are reserved and should not be used in applications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 Functional Overview 41 5320 2801 5320 28016 5320 28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 TEXAS INSTRUMENTS www ti com Table 3 10 Peripheral Frame 2 Registers 2 NAME ADDRESS RANGE SIZE x16 ACCESS TYPE System Control Registers 0x7010 0x702F 32 EALLOW Protected SPI A Registers 0x7040 0x704F 16 SCI A Registers 0x7050 0x705F 16 Externa
27. 1 EQEP2A 1 SPISIMOB 19 18 GPIO25 2 I O EQEP2B I SPISOMIB 21 20 GPIO26 ECAP3 EQEP2 I O SPICLKB I O 23 22 GPIO27 ECAP4 I O 25 I O SPISTEB I O 25 24 GPIO28 SCIRXDA 1 Reserved 9 175 I 27 26 GPIO29 SCITXDA O Reserved 9 176 I 29 28 GPIO30 CANRXA I Reserved Reserved 31 30 GPIO31 CANTXA O Reserved 9 Reserved GPBMUX1 1 0 GPIO32 SDAA EPWMSYNCI 1 ADCSOCAO O 3 2 GPIO33 SCLA EPWMSYNCO O ADCSOCBO O 5 4 GPIO34 Reserved 9 Reserved 9 Reserved 9 1 GPxMUX1 2 refers to the appropriate MUX register for the pin GPAMUX1 GPAMUX or GPBMUX1 2 This table pertains to the 2808 device Some peripherals may not be available in the 2809 2806 2802 or 2801 devices See the pin descriptions for more detail 3 The word Reserved means that there is no peripheral assigned to this GPxMUX1 2 register setting Should it be selected the state of the pin will be undefined and the pin may be driven This selection is a reserved configuration for future expansion 84 Peripherals Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 Texas TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS2
28. 200 0 n 8 1000 2 I I 10 20 30 40 50 60 70 80 90 100 SYSCLKOUT MHz TOTAL POWER Figure 6 2 Typical Operational Power Versus Frequency F2808 NOTE Typical operational current for 60 MHz devices can be estimated from Figure 6 1 For Ipp current alone subtract the current contribution of non existent peripherals after scaling the peripheral currents for 60 MHz For example to compute the current of F2801 60 device the contribution by the following peripherals must be subtracted from lpp ePWM4 5 6 eCAP3 4 eQEP2 SCI B 100 Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 Texas TMS320F2802 TMS320F2801 TMS320C2802 eee TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Current Vs SYSCLKOUT 200 4 180 4 160 4 140 N o Current mA eeo eoo o o o o o o N n n a tt 10 20 30 40 50 60 70 80 90 10 SYSCLKOUT MHz m IDD e IDDA18 1 8v current IDDIO IDD3VFL e 3 3v current Figure 6 3 Typical Operational Current Versus Frequency C280
29. EPWM1A 47 K8 Enhanced PWM1 Output and HRPWM channel O GPIO1 General purpose input output 1 I O Z 9 EPWM1B 44 K7 Enhanced PWM1 Output B O SPISIMOD SPI D slave in master out 1 not available on 2801 2802 GPIO2 General purpose input output 2 1 0 2 9 EPWM2A 45 J7 Enhanced PWM2 Output HRPWM channel O GPIO3 General purpose input output 3 1 0 2 4 EPWM2B 48 J8 Enhanced PWM 2 Output B O SPISOMID SPI D slave out master in 1 not available on 2801 2802 GPIO4 General purpose input output 4 1 0 2 9 51 19 Enhanced PWM3 output A HRPWM channel GPIO5 General purpose input output 5 1 0 2 9 EPWM3B 53 H9 Enhanced PWMS output SPICLKD SPI D clock I O not available on 2801 2802 ECAP1 Enhanced capture input output 1 1 2 Some peripheral functions may not be available in TMS320F2801x devices See Table 2 2 for details 3 GPIO pins are 2 4 mA drive typical unless otherwise indicated and have an internal pullup which can be selectively enabled disabled on a per pin basis This feature only applies to the GPIO pins The GPIO function shown in Italics is the default at reset The peripheral signals that are listed under them are alternate functions 4 The pullups on GPIOO GPIO11 pins are not enabled at reset Copyright 2003 2009 Texas Instruments Incorporated Introduction 21 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F
30. PCLKCRO 0x701C 1 Peripheral Clock Control Register 0 PCLKCR1 0x701D 1 Peripheral Clock Control Register 1 LPMCRO Ox701E 1 Low Power Mode Control Register 0 Reserved 0x701F 0x7020 1 Reserved PLLCR 0x7021 1 PLL Control Register SCSR 0x7022 1 System Control and Status Register WDCNTR 0x7023 1 Watchdog Counter Register Reserved 0x7024 1 Reserved WDKEY 0x7025 1 Watchdog Reset Key Register Reserved 0x7026 0x7028 3 Reserved WDCR 0x7029 1 Watchdog Control Register Reserved 0x702A 0x702F 6 Reserved 1 All of the registers in this table are EALLOW protected 3 6 1 OSC and PLL Block Figure 3 10 shows the OSC and PLL block on the 280x XCLKIN OSCE A 3 3 V clock input A OSCCLK 0 OSCCLK or VCOCLK PLLSTS OSCOFF VCOCLK PLL nj PLLSTS PLLOFF PLLSTS CLKINDIV 4 01 PLL Select PLLCR Figure 3 10 OSC and PLL Block Diagram The on chip oscillator circuit enables crystal resonator to be attached to the 280x devices using the X1 and X2 pins If the on chip oscillator is not used an external oscillator can be used in either one of the following configurations 1 A 3 3 V external oscillator can be directly connected to the XCLKIN pin The X2 pin should be left unconnected and the X1 pin tied low The logic high level in this case should not exceed 2 A 1 8 external oscillator can be directly connected to the X1 pin The X2 pin should be left uncon
31. PRIMARY I O PERIPHERAL PERIPHERAL PERIPHERAL REGISTER FUNCTION SELECTION 1 SELECTION 2 SELECTION 3 BITS GPxMUX1 2 GPxMUX1 2 BITS 0 1 GPxMUX1 2 BITS 1 0 GPxMUX1 2 BITS 1 1 BITS 0 0 GPAMUX1 1 0 GPIOO EPWM1A Reserved 9 Reserved 3 2 GPIO1 SPISIMOD I O Reserved 5 4 GPIO2 EPWM2A Reserved 9 Reserved 9 7 6 GPIO3 EPWM2B O SPISOMID I O Reserved 9 8 GPIO4 EPWM3A Reserved 9 Reserved 11 10 GPIO5 EPWM3B SPICLKD I O 1 I O 13 12 O EPWMSYNCI 1 EPWMSYNCO 0 15 14 GPIO7 EPWM4B O SPISTED I O 2 I O 17 16 GPIO8 EPWMBA CANTXB ADCSOCAO 0 19 18 GPIO9 EPWMBB SCITXDB O ECAP3 21 20 GPIO10 EPWM6A CANRXB 1 ADCSOCBO 0 23 22 GPIO11 EPWM6B O SCIRXDB l ECAPA I O 25 24 GPIO12 171 1 CANTXB O SPISIMOB 27 26 GPIO13 172 1 I SPISOMIB 29 28 GPIO14 TZ3 I SCITXDB O SPICLKB I O 31 30 GPIO15 174 I SCIRXDB 1 SPISTEB I O GPAMUX2 1 0 GPIO16 SPISIMOA CANTXB O 175 1 3 2 GPIO17 SPISOMIA I 176 1 5 4 GPIO18 SPICLKA SCITXDB O Reserved 9 7 6 GPIO19 SPISTEA SCIRXDB Reserved 9 9 8 GPIO20 EQEP1A I SPISIMOC I O CANTXB O 11 10 GPIO21 I SPISOMIC I O I 13 12 GPIO22 EQEP1S I O SPICLKC I O SCITXDB O 15 14 23 EQEP 1I I O SPISTEC I O SCIRXDB 1 17 16 24
32. TEST CONDITIONS MIN MAX UNIT tw QEPP QEP input period Asynchronous synchronous 2lcisco cycles With input qualifier 2 1tcsco twiasw tw INDEXH QEP Index Input High time Asynchronous synchronous 2lc sco cycles With input qualifier 2tc sco tw losw tw INDEXL QEP Index Input Low time Asynchronous synchronous 2lc sco cycles With input qualifier 2tc sco twiiasw tw STROBH QEP Strobe High time Asynchronous synchronous 2lc sco cycles With input qualifier 2tc sco twiiasw tw STROBL QEP Strobe Input Low time Asynchronous synchronous 2lc sco cycles With input qualifier 2tc sco tw losw 1 Foran explanation of the input qualifier parameters see Table 6 15 Table 6 29 Switching Characteristics PARAMETER TEST CONDITIONS MIN MAX UNIT la CNTR xin Delay time external clock to counter increment 4tysco cycles laPcs ounaeP Delay time QEP input edge to position compare sync output cycles 116 Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 5320 2801 5320 28016 5320 28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 Pel Rene TMS320C2801 TMS320F28016 TMS320F28015 Table 6 30 External ADC Start of Conversion Switching Characteristics PARAMETER
33. Texas TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 The 280x supports 34 GPIO pins The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32 bit operations on the registers along with 16 bit operations Table 4 15 shows the GPIO register mapping Table 4 15 GPIO Registers NAME ADDRESS SIZE x16 DESCRIPTION GPIO CONTROL REGISTERS EALLOW PROTECTED GPACTRL Ox6F80 2 GPIO A Control Register GPIOO to 31 GPAQSEL1 Ox6F82 2 GPIO A Qualifier Select 1 Register GPIOO to 15 GPAQSEL2 Ox6F84 2 GPIO A Qualifier Select 2 Register GPIO16 to 31 GPAMUX1 Ox6F86 2 GPIO A MUX 1 Register GPIOO to 15 GPAMUX2 Ox6F88 2 GPIO A MUX 2 Register GPIO16 to 31 GPADIR Ox6F8A 2 GPIO A Direction Register GPIOO to 31 GPAPUD Ox6F8C 2 GPIO A Pull Up Disable Register GPIOO to 31 Reserved 1 2 Reserved GPBCTRL Ox6F90 2 GPIO B Control Register GPIO32 to 35 GPBQSEL1 Ox6F92 2 GPIO B Qualifier Select 1 Register GPIO32 to 35 GPBQSEL2 Ox6F94 2 Reserved GPBMUX1 Ox6F96 2 GPIO B MUX 1 Register GPIO32 to 35 GPBMUX2 Ox6F98 2 Reserved GPBDIR Ox6F9A 2 GPIO B Direction Register GPIO32 to 35 GPBPUD Ox6F9C 2 GPIO B Pull Up Disable Register GPIO32 to 35 Reserved 2 2 Reserved Reserved pois 32 Reserved GPIO DATA REGISTERS NOT EALLOW PROTECTED GPADAT Ox6FCO 2 GPIO Data Register GPI
34. The following peripheral clocks are enabled ePWM1 2 3 4 5 6 eCAP1 2 3 4 eQEP1 2 eCAN A SCI A B SPI A ADC i All PWM pins are toggled 195 mA 230 15 27 35mA 40 30 38mA 1 5 mA 2 at 100 kHz All I O pins are left unconnected Data is continuously transmitted out of the SCI A SCI B and eCAN A ports The hardware multiplier is exercised Code is running out of flash with 3 wait states XCLKOUT is turned off Flash is powered down XCLKOUT is turned off The following peripheral clocks are enabled IDLE eCAN A 75mA 90 500 2mA 2 yA 10 pA 5 pA 50 pA 15 pA 30 pA SCI A SPLA 2 Flash is powered down STANDBY Peripheral clocks are off 6 mA 12mA 100 500ygA 2pA 10 pA 5 pA 50 uA 15 uA 30 uA Flash is powered down HALT Peripheral clocks are off 70 uA 60 pA 120 pA 2 pA 10 5 50 pA 15 30 uA Input clock is disabled 1 Ippio current is dependent on the electrical loading on the I O pins 2 The Ipp3ve current indicated in this table is the flash read current and does not include additional current for erase write operations During flash programming extra current is drawn from the Vpp and Vppavyr rails as indicated in Table 6 45 If the user application involves on board flash programming this extra current must be taken into account while architecting the power supply stage 3 lppa1s includes c
35. a EU DEP 70 4 12 eCAN B Memory Mapas se al ROTE EE 71 4 13 Serial Communications Interface SCI Module Block E 4 14 SPI Module Block Diagram Slave Mode 1 hn n nn n nnn 79 4 15 I2C Peripheral Module Interfaces 81 4 16 MUX Block nem memese heme ese sk se sessi senses nn 82 4 17 Qualification Using Sampling WiNdOW 85 5 1 Example of TMS320x280x 2801x Device Nomenclature 2 87 6 1 Typical Operational Current Versus Frequency 2808 100 6 2 Typical Operational Power Versus Frequency 2808 4 4 100 6 3 Typical Operational Current Versus Frequency 280 11 nnne 101 6 4 Typical Operational Power Versus Frequency C280x 101 6 5 Emulator Connection Without Signal Buffering for the 050 102 6 6 3 3 V Test Load Circuit
36. 0 689 0x68DE 0 691 0 695 1 0 PWM Chopper Control Register HRCNFG 0x6820 0 6860 0 68 0 0 68 0 0 6920 2 0 6960 2 1 0 HRPWM Configuration Register 1 Registers that are EALLOW protected 2 Applicable to F2809 only 56 Peripherals Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 Texas TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 Time Base TB Sync TBPRD Shadow 16 ZERO In Out EPWMxSYNCO CTR CMPB Select TBPRD Active 16 Disabled Mux ge CTR PRD TBCTL SYNCOSEL TBCTL PHSEN Counter m 2 cC EPWMxSYNCI Up Down TBCTL SWFSYNC 16 Bit Software Forced Sync CTR ZERO TBCNT Active 16 CTR_Dir TBPHSHR 8 CTR PRD Phase Event TBPHS Active 24 Control CTR ZERO EPWMxSOCA SIR ENTS nEn EPWMxSOCB CTR_Dir Counter Compare CC Action Jl CTR CMPA Qualifier AQ CMPAHR 8 HiRes PWM HRPWM CMPA Active 24 EPWMA EPWMxAO CMPA Shadow 24 gt 16 EPWMxBO Active 16 EPWMxtTZINT X CMPB Shadow 16 CTR ZERO TZ1 to TZ6
37. 2 2 2 2 Digital I O pins shared 35 35 35 35 35 35 35 External interrupts 3 3 3 3 3 3 3 Supply voltage 1 8 V Core 3 3 V I O Yes Yes Yes Yes Yes Yes Yes 100 2 Yes Yes Yes Yes Yes Yes Yes 100 Ball GGM ZGM Yes Yes Yes Yes Yes 40 to 85 C PZ GGM ZGM PZ GGM ZGM PZ GGM ZGM PZ ZGM PZ GGM ZGM PZ GGM ZGM PZ GGM ZGM Temperature options S 40 to 125 C PZ GGM ZGM PZ ZGM PZ GGM ZGM PZ ZGM PZ GGM ZGM PZ GGM ZGM PZ GGM ZGM Q 40 C to 125 C 2 2 2 2 2 2 2 Product status 2 TMS TMS TMS TMS TMS TMS TMS 1 A type change represents a major functional feature difference a peripheral module Within a peripheral type there may be minor differences between devices that do not affect the basic functionality of the module These device specific differences are listed in the TMS320x28xx 28xxx DSP Peripheral Reference Guide literature number SPRU566 and in the peripheral reference guides 2 See Section 5 1 Device and Development Support Tool Nomenclature for descriptions of device stages 12 Introduction Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015
38. 2801 28015 28016 Figure 5 1 Example of TMS320x280x 2801x Device Nomenclature Copyright 2003 2009 Texas Instruments Incorporated Device Support 87 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS 5320 2801 TMS320F28016 TMS320F28015 Nee SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 5 2 Documentation Support Extensive documentation supports all of the TMS320 DSP family generations of devices from product announcement through applications development The types of documentation available include data sheets and data manuals with design specifications and hardware and software applications Table 5 1 shows the peripheral reference guides appropriate for use with the devices in this data manual See the 7MS320x28xx 28xxx DSP Peripheral Reference Guide literature number SPRU566 for more information on types of peripherals Table 5 1 TMS320x280x 2801x Peripheral Selection Guide F2809 F2808 PERIPHERAL GUIDE NUMBER TYPE E 2801 28016 28015 TMS320x280x 2801 2804 DSP System Control and Interrupts SPRU712 X TMS320x280x 2801x 2804x Boot ROM SPRU722 TMS320x280x 2801 2804x DSP Analog to Digital Converter ADC SPRU716 1 X TMS320x280x 28
39. SPICCR 6 lt 12 gt SPICLK clock polarity 0 14 gt SPICLK clock polarity 1 lt 17 gt 4 18 vata 8 2 4 2 sso AAR st Beats SPISTE A A In the slave mode the SPISTE signal should be asserted low at least 0 5 before the valid SPI clock edge and remain low for at least 0 after the receiving edge SPICLK of the last data bit Figure 6 23 SPI Slave Mode External Timing Clock Phase 1 124 Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 Pen MENG TMS320C2801 TMS320F28016 TMS320F28015 6 10 7 On Chip Analog to Digital Converter Table 6 38 ADC Electrical Characteristics over recommended operating conditions 2 PARAMETER MIN TYP MAX UNIT DC SPECIFICATIONS Resolution 12 Bits ADC clock 60 MHz device 0 001 7 5 MHz 100 MHz device 0 001 12 5 MHz 100 MHz device F2809 only 0 001 25 ACCURACY INL Integral nonlinearity 1 12 5 MHz ADC clock 6 25 MSPS 1 5 LSB 12 5 25 MHz ADC cl
40. This is to enable the entire device to start from a known condition 2 During power down the XRS pin must be pulled low at least 8 us prior to Vpp reaching 1 5 V This is to enhance flash reliability Additionally it is recommended that no voltage larger than a diode drop 0 7 V should be applied to any pin prior to powering up the device Voltages applied to pins on an unpowered device can bias internal p n junctions in unintended ways and produce unpredictable results 6 8 1 Power Management and Supervisory Circuit Solutions Table 6 12 lists the power management and supervisory circuit solutions for 280x DSPs LDO selection depends on the total power consumed in the end application Go to http Awww power ti com for complete list of power ICs Table 6 12 Power Management and Supervisory Circuit Solutions SUPPLIER TYPE PART DESCRIPTION Texas Instruments LDO TPS767D301 Dual 1 A low dropout regulator LDO with supply voltage supervisor SVS Texas Instruments LDO TPS70202 Dual 500 250 mA LDO with SVS Texas Instruments LDO TPS766xx 250 mA LDO with PG Texas Instruments SVS TPS3808 Open Drain SVS with programmable delay Texas Instruments SVS TPS3803 Low cost Open drain SVS with 5 uS delay Texas Instruments LDO TPS799xx 200 mA LDO in WCSP package Texas Instruments LDO TPS736xx 400 LDO with 40 mV of Vpo Texas Instruments DC DC TPS62110 High Vin 1 2 A dc dc converter in 4x4 QFN package Texas Instruments DC DC TPS6230x 500 m
41. denotes flash devices FF denotes ROM devices Other values are reserved for future devices Figure 3 7 shows how the various interrupt sources are multiplexed within the 280x devices Eight PIE block interrupts are grouped into one CPU interrupt In total 12 CPU interrupt groups with 8 interrupts per group equals 96 possible interrupts On the 280x 43 of these are used by peripherals as The TRAP VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified TRAP 0 attempts to transfer program control to the address pointed to by the reset vector The PIE vector table does not however include a reset vector Therefore TRAP 0 should not be used when the PIE is enabled Doing so will result in undefined behavior 3 5 Interrupts shown in Table 3 12 42 Functional Overview Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 5320 2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 Pe ene TMS320C2801 TMS320F28016 TMS320F28015 When the PIE is enabled TRAP 1 through TRAP 12 will transfer program control to the interrupt service routine corresponding to the first vector within the PIE group For example TRAP 1 fetches the vector from INT1 1 TRAP 42 fetches the
42. e sessi enne nnn 138 6 49 OTP area Minimum Required Wait States at Different 132 9 1 F280x Thermal Model 100 pin GGM Results ene nene he nene nenne 1985 9 2 F280x Thermal Model 100 PZ 5 135 9 3 C280x Thermal Model 100 pin GGM 6 135 9 4 C280x Thermal Model 100 PZ 66 sese 135 9 5 F2809 Thermal Model 100 GGM Results 0 2 54 nennen 135 9 6 F2809 Thermal Model 100 pin PZ Results 136 8 List of Tables Copyright 2003 2009 Texas Instruments Incorporated 5 INSTRUMENTS www ti com TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Digital Signal Processors Samples TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 1 F280x F2801x C280x DSPs 1 1 Features High Performance Static CMOS Technology 100 MHz 10 ns Cycle Time 60 MHz 16 67 ns Cycle Time Low Power 1 8 V Core 3 3
43. 0 775 1 SCI B FIFO Receive Register SCIFFCTB 0x775C 1 SCI B FIFO Control Register SCIPRIB 0 775 1 SCI B Priority Control Register 1 Registers in this table are mapped to peripheral bus 16 space undefined results 2 These registers are new registers for the FIFO mode 74 Peripherals Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 5320 2802 TMS320F2801 TMS320C2802 Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback 5320 2801 5320 28016 TMS320F28015 INSTRUMENTS This space only allows 16 bit accesses 32 bit accesses produce TMS320F2809 TMS320F2808 TMS320F2806 TEXAS INSTRUMENTS TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Figure 4 13 shows the SCI module block diagram SCICTL1 1 SCITXD Frame Format and Mode SCITXD Parity Even Odd Enable SCICCR 6 SCICCR TX INT ENA Transmitter Data O E SCICTL2 0 5 1 3 Logic SCITXBUF 7 0 TX FIFO registers SCIFFENA SCIHBAUD 15 8 SCIRXD s SCIRXD Register RXWAKE LSPCLK i SCIRXST 1 SCILBAUD 7 0 Baud Rate LSbyte ScicTL2 1 TL2 1 Register Receiv Buffer SCIRXI Data register RXRDY RX BK INT ENA BUF 7 0 8 SCIRXST S SCIRXBUF 7 0 Logic RX FIFO registers SCIRXST 7 SCIRXST 4 2 6 1
44. 1 PIE INT2 Group Flag Register PIEIER3 0x0CE6 1 PIE INT3 Group Enable Register PIEIFR3 0x0CE7 1 PIE INT3 Group Flag Register PIEIER4 0x0CE8 1 PIE INT4 Group Enable Register PIEIFR4 0x0CE9 1 PIE INT4 Group Flag Register PIEIER5 OxOCEA 1 PIE INT5 Group Enable Register PIEIFR5 1 PIE INT5 Group Flag Register PIEIER6 OxOCEC 1 PIE INT6 Group Enable Register PIEIFR6 OxOCED 1 PIE INT6 Group Flag Register PIEIER7 OxOCEE 1 PIE INT7 Group Enable Register PIEIFR7 OxOCEF 1 PIE INT7 Group Flag Register PIEIER8 OxOCFO 1 PIE INT8 Group Enable Register PIEIFR8 OxOCF1 1 PIE INT8 Group Flag Register PIEIER9 OxOCF2 1 PIE INT9 Group Enable Register PIEIFR9 OxOCF3 1 PIE INT9 Group Flag Register PIEIER10 OxOCF4 1 PIE INT10 Group Enable Register PIEIFR10 OxOCF5 1 PIE INT10 Group Flag Register PIEIER11 OxOCF6 1 PIE INT11 Group Enable Register PIEIFR11 OxOCF7 1 PIE INT11 Group Flag Register PIEIER12 OxOCF8 1 PIE INT12 Group Enable Register PIEIFR12 OxOCF9 1 PIE INT12 Group Flag Register Reserved OxOCFA 6 Reserved OxOCFF 1 The PIE configuration and control registers are not protected by EALLOW mode The PIE vector table is protected 3 5 1 External Interrupts Table 3 14 External Interrupt Registers NAME ADDRESS SIZE x16 DESCRIPTION XINT1CR 0x7070 1 XINT1 control register XINT2CR 0x7071 1 2 control register Reserved 0x7072 0x7076 5 Reserved XNMI
45. 16 46 Table 9 2 280 Thermal Model 100 PZ Results AIR FLOW PARAMETER 150 250 500 Ifm 8 A C W High k PCB 48 16 40 06 37 96 35 17 V C W 0 3425 0 85 1 0575 1 410 12 89 29 58 Table 9 3 280 Thermal Model 100 pin GGM Results AIR FLOW PARAMETER 0 lfm 150 Ifm 250 Ifm 500 Ifm 8 A SC W High k PCB 36 33 35 01 33 81 32 31 0 57 0 43 0 52 0 67 1418 21 36 Table 9 4 280 Thermal Model 100 PZ Results AIR FLOW PARAMETER 0 lfm 150 250 500 Ifm OjA C W High k PCB 69 81 60 34 57 46 53 63 0 42 1 23 1 54 2 11 13 52 54 78 Table 9 5 F2809 Thermal Model 100 pin GGM Results AIR FLOW PARAMETER 0 lfm 150 Ifm 250 Ifm 500 Ifm A C AW High PCB 28 15 26 89 25 68 24 22 WV 0 38 0 35 0 33 0 44 10 36 13 3 Copyright 2003 2009 Texas Instruments Incorporated Mechanical Data 135 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Table 9 6 F2809 Thermal Model 100 pin P
46. 2 Registers 4 4 21 42 3 11 Device Emulation 42 3 12 PIEPeripheral E a 44 3 13 PIE Configuration and Control S 45 3 14 External Interrupt Registers issue tee eee E DIM E DU M EDU Ea NE UNDA DN VUE M 45 3 15 PLL Clocking Watchdog and Low Power Mode Registers 47 3 16 PLLCR Register Bit nemen ne meme meses nemine 49 3 17 Possible PLL Configuration Modes 1 4 nnne 49 3 18 un a AR ERU ER MER ne 4 1 CPU Timers 0 1 2 Configuration and Control Registers 54 4 2 ePWM Control and Status Registers 41 41 21 4 lt si sese 56 4 3 eCAP Control and Status Registers
47. 2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 5320 28016 TMS320F28015 5 INSTRUMENTS www ti com Block Start Address 0x00 0000 0x00 0040 0x00 0400 0x00 0800 0x00 0000 0x00 0 00 Low 64K 0000 FFFF 24x 240x equivalent data space 0x00 6000 0x00 7000 0x00 8000 0x00 9000 0x3D 7800 0x3D 7 00 0000 7FF8 8000 Ox3F 9000 High 64K 3F0000 3FFFF 24x 240x equivalent program space Ox3F 000 0x3F FFCO TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Data Space Prog Space 0 Vector RAM 32 x 32 Enabled if 0 0 SARAM 1K x 16 M1 SARAM 1K x 16 Peripheral Frame 0 PIE Vector RAM 256 x 16 Enabled if ENPIE 1 Reserved Reserved Peripheral Frame 1 protected Reserved Peripheral Frame 2 protected LO SARAM 0 wait 4K x 16 Secure Zone Dual Mapped Reserved OTP F2802 Only 1K x 16 Secure Zone Reserved FLASH F2802 or ROM C2802 32K x 16 Secure Zone 128 bit Password LO 0 wait x 16 Secure Zone Dual Mapped Reserved Boot ROM 4K x 16 Vectors 32 x 32 enabled if VMAP 1 ENPIE 0 A The 1K x 16 OTP has been replaced with 1K x 16 ROM in C2802 w Memory bloc
48. 4K x 16 Secure Zone Dual Mapped 0x00 9000 Reserved 0x3D 7800 OTP F2801 F2801x 1K x 16 Secure Zone 0x3D 7C00 Reserved Ox3F 4000 FLASH F2801 or ROM C2801 v 16K x 16 Secure Zone 9 7FF8 128 bit Password u 0x3F 8000 10 0 9 gt 4K x 16 Secure Zone Dual Mapped 95 9000 St s x Reserved o0 55 x Ox3F 000 Boot ROM 4K x 16 Ox3F FFCO Vectors 32 x 32 enabled if VMAP 1 ENPIE 0 A The 1K x 16 OTP has been replaced with 1K x 16 ROM C2801 Memory blocks are not to scale C Peripheral Frame 0 Peripheral Frame 1 and Peripheral Frame 2 memory maps are restricted to data memory only User program cannot access these memory maps in program space D Protected means the order of Write followed by Read operations is preserved rather than the pipeline order Certain memory ranges are EALLOW protected against spurious writes after configuration F Some locations in ROM are reserved for See Table 3 5 for more information Figure 3 6 F2801 F28015 F28016 C2801 Memory Map w m 30 Functional Overview Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 5320 2801 5320 2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TEXAS TMS320F2802 TMS320F2801 5320 2
49. 6 37 SPI Slave Mode External Timing Clock Phase 1 11 6 6 124 6 38 ADC Electrical Characteristics over recommended operating conditions 13 1111 125 6 39 Power Up DelayS s seines oru iste sore ne Eu nte dE clerk IUE ERI Muf 126 6 40 Current Consumption for Different ADC Configurations at 12 5 MHz ADCCLK 126 6 41 Sequential Sampling Mode uuu rot rr ao E Ide DRE MEE 128 6 42 simultaneous Sampling TIMING E MERE cp NK E 129 6 43 Flash Endurance for and S Temperature Material 1 2 1 1 4 4 6 nnne 131 6 44 Flash Endurance for Q Temperature nenne nennen nnns 131 6 45 Flash Parameters at 100 MHz 5 5 1 11 semen 131 6 46 Flash OTP Access TIMING uawan an E SE a so d tw ad Rm B Ra ER 131 6 47 Minimum Required Flash OTP Wait States at Different Frequencies 192 6 48 ROM OTP Access Timing 1 2 2 1 11 1 6 0 066
50. 63E0h 63E7h Mailbox 28 63E8h 63EFh Mailbox 29 63F0h 63F7h Mailbox 30 63F8h 63FFh Mailbox 31 63E8h 63E9h 63EAh 63EBh 63ECh 63EDh 63EEh 63EFh NoJEF 5320 2809 5320 2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 eCAN B Control and Status Registers Mailbox Enable CANME Mailbox Direction CANMD Transmission Request Set CANTRS Transmission Request Reset CANTRR Transmission Acknowledge CANTA Abort Acknowledge CANAA Received Message Pending CANRMP Received Message Lost CANRML Remote Frame Pending CANRFP Global Acceptance Mask CANGAM Master Control CANMC Bit Timing Configuration CANBTC Error and Status CANES Transmit Error Counter CANTEC Receive Error Counter CANREC Global Interrupt Flag 0 CANGIFO Global Interrupt Mask CANGIM Global Interrupt Flag 1 CANGIF1 Mailbox Interrupt Mask CANMIM Mailbox Interrupt Level CANMIL Overwrite Protection Control CANOPC TX Control CANTIOC RX Control CANRIOC Time Stamp Counter CANTSC Time Out Control CANTOC Time Out Status CANTOS Reserved N Message Mailbox 16 Bytes Message Identifier MSGID Message Control MSGCTRL Message Data Low MDL Message Data High MDH Figure 4 12 eCAN
51. Consumption 280x devices have a richer peripheral mix compared to the 281x family While the McBSP has been removed the following new peripherals have been added on the 280x SPI modules 1 CAN module 112C module The two event manager modules of the 281x have been enhanced and replaced with separate ePWM 6 eCAP 4 and eQEP 2 modules providing tremendous flexibility in applications Like 281x 280x DSPs incorporate a unique method to reduce the device current consumption Since each peripheral unit has an individual clock enable bit significant reduction in current consumption can be achieved by turning off the clock to any peripheral module that is not used in a given application Furthermore any one of the three low power modes could be taken advantage of to reduce the current consumption even further Table 6 5 indicates the typical reduction in current consumption achieved by turning off the clocks Table 6 5 Typical Current Consumption by Various Peripherals at 100 MHz PERIPHERAL Ipp CURRENT MODULE REDUCTION mA ADC g9 2 eQEP ePWM eCAP SCl SPI eCAN 1 All peripheral clocks are disabled upon reset Writing to reading from peripheral registers is possible only after the peripheral clocks are turned on 2 For peripherals with multiple instances the current quoted is per module For example the 5 mA number quoted for ePWM is for one ePWM module 3 This number represents the current drawn by
52. Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 5 INSTRUMENTS www ti com 6 Electrical Specifications TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 This section provides the absolute maximum ratings and the recommended operating conditions for the 5320 280 DSPs 6 1 Absolute Maximum Ratings Unless otherwise noted the list of absolute maximum ratings are specified over operating temperature ranges Supply voltage range Vppio Vpp3vFL with respect to Vss 0 3 V to 4 6 V Supply voltage range VppAio with respect to VssA 0 3 V to 4 6 V Supply voltage range Vpp with respect to Vss 0 3 V to 2 5 V Supply voltage range Vpp1A18 2 18 with respect to VssA 0 3 V to 2 5 V Supply voltage range Vssaio Vss1AGND VSS2AGND with respect to Vss 0 3 V to 0 3 V Input voltage range Vin 0 3 V to 4 6 V Output voltage range Vo 0 3 V to 4 6 V Input clamp current Vin lt 0 or Vin gt Vppio 9 20 mA Output clamp current Vo lt 0 or Vo gt Vppio 20 mA Operating ambient temperature ranges A version ZGM PZ
53. DALLAS TEXAS 75265 1 MECHANICAL DATA ZGM 5 100 PLASTIC BALL GRID ARRAY 4 720 OOOOOOOOOO OOOOOIOOOOO PIO OJO O CO LO QOSQO OOO OOO OOOO CO OOOO Al Corner 234567 8 9 10 Bottom View 1 40 MAX 7 757575757577 07 0 55 045 910 0 08 0 45 30 0 Y Seating Plane 4204740 A 10 02 NOTES All linear dimensions are in millimeters This drawing is subject to change without notice MicroStar BGA configuration This package is lead free com MicroStar BGA is a trademark of Texas Instruments 1 INSTRUMENTS www ti com MECHANICAL DATA MTQF013A OCTOBER 1994 REVISED DECEMBER 1996 PZ S PQFP G100 PLASTIC QUAD FLATPACK 0 13 NOM WOU OULU UU UU ddl 0001090100900909090040000 1 25 12 00 TYP p Plane i 14 20 13 80 50 16 20 15 80 SQ 0 05 MIN Seating Plane 1 60 MAX 4040149 B 11 96 NOTES All linear dimensions in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 3 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its pr
54. Low Speed Prescaler LSPCLK a Peripheral Low Speed Peripherals Registers SCI A B SPI A B C D High Speed Prescaler HSPCLK ADG 12 Bit ADC Registers Watchdog Block Power XCLKIN Modes Control 16 ADC inputs CLKIN is the clock into the CPU It is passed out of the CPU as SYSCLKOUT that is CLKIN is the same frequency as SYSCLKOUT Figure 3 9 Clock and Reset Domains 46 Functional Overview Submit Documentation Feedback Copyright 2003 2009 Texas Instruments Incorporated Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 5320 2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 TMS320F28015 5 INSTRUMENTS www ti com TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 The PLL clocking watchdog and low power modes are controlled by the registers listed in Table 3 15 Table 3 15 PLL Clocking Watchdog and Low Power Mode Registers NAME ADDRESS SIZE x16 DESCRIPTION XCLK 0x7010 1 XCLKOUT Pin Control X1 and XCLKIN Status Register PLLSTS 0x7011 1 PLL Status Register Reserved 0x7012 0x7019 8 Reserved HISPCP 0x701A 1 High Speed Peripheral Clock Prescaler Register for HSPCLK LOSPCP 0x701B 1 Low Speed Peripheral Clock Prescaler Register for LSPCLK
55. Receive data ready Register access ready No acknowledgment received Arbitration lost Stop condition detected Addressed as slave An additional interrupt that can be used by the CPU when in FIFO mode Module enable disable capability Free data format mode Peripherals Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 Texas TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 System Control Mee C28X CPU Block I2CAENCLK SYSCLKOUT o m s lt 2 Data 16 5 a Data 16 16 I2CINT1A PIE Block 2 2 A registers are accessed at the SYSCLKOUT rate The internal timing and signal waveforms of the 12C port also at the SYSCLKOUT rate B The clock enable bit 2 in the PCLKCRO register turns off the clock to the 12 port for low power operation Upon reset 2 is clear which indicates the peripheral internal clocks are off Figure 4 15 2 Peripheral Module Interfaces The registers in Table 4 14 configure and control the 2 port operation Tabl
56. Register 1 SCIHBAUDA 0x7052 1 SCI A Baud Register High Bits SCILBAUDA 0x7053 1 SCI A Baud Register Low Bits SCICTL2A 0x7054 1 SCI A Control Register 2 SCIRXSTA 0x7055 1 SCI A Receive Status Register SCIRXEMUA 0x7056 1 SCI A Receive Emulation Data Buffer Register SCIRXBUFA 0x7057 1 SCI A Receive Data Buffer Register SCITXBUFA 0x7059 1 SCI A Transmit Data Buffer Register 0 705 1 SCI A FIFO Transmit Register 0 705 1 SCI A FIFO Receive Register SCIFFCTA 0x705C 1 SCI A FIFO Control Register SCIPRIA 0 705 1 SCI A Priority Control Register 1 Registers in this table are mapped to Peripheral Frame 2 space This space only allows 16 bit accesses 32 bit accesses produce undefined results 2 These registers are new registers for the FIFO mode Table 4 9 SCI B Registers 2 NAME ADDRESS SIZE x16 DESCRIPTION SCICCRB 0x7750 1 SCI B Communications Control Register SCICTL1B 0x7751 1 SCI B Control Register 1 SCIHBAUDB 0x7752 1 SCI B Baud Register High Bits SCILBAUDB 0x7753 1 SCI B Baud Register Low Bits SCICTL2B 0x7754 1 SCI B Control Register 2 SCIRXSTB 0x7755 1 SCI B Receive Status Register SCIRXEMUB 0x7756 1 SCI B Receive Emulation Data Buffer Register SCIRXBUFB 0x7757 1 SCI B Receive Data Buffer Register SCITXBUFB 0x7759 1 SCI B Transmit Data Buffer Register 0 775 1 SCI B FIFO Transmit Register
57. SPIBRR 0 OR2 SPIBRR 3 UNIT MIN MAX MIN MAX 1 lc SPC M Cycle time SPICLK Atc co 128tc 5tc co 127tc ns tw SPCH M Pulse duration SPICLK high 0 5 10 0 5tc SPC M 0 5tc spc M 0 5 Lco 10 0 5tc sPc M 0 5tc Lco 2 clock polarity 0 ns tw SPCL M Pulse duration SPICLK low 0 10 O Stc sPC M 0 0 5 10 0 0 5te Lco clock polarity 1 tw SPCL M Pulse duration SPICLK low 0 5tespcym 10 0 5tc SPC M 0 5 0 10 0 5tc sPc M 0 5 3 clock polarity 0 ns tw SPCH M Pulse duration SPICLK high 0 10 0 5tc SPC M 0 5tc spcym 0 10 0 0 5tc Lco clock polarity 1 tsu SIMO SPCH M Setup time SPISIMO data valid 0 5te spcym 10 0 5tg spcym 10 before SPICLK high 6 clock polarity 0 ns tsu SIMO SPCL M Setup time SPISIMO data valid 0 5tespcym 10 0 5tg spcym 10 before SPICLK low clock polarity 1 tv SPCH SIMO M Valid time SPISIMO data valid after 0 5tc SPC M 10 O StcisPc M 10 y SPICLK high clock polarity 0 ns tv SPCL SIMO M Valid time SPISIMO data valid after 0 10 0 5 5 10 SPICLK low clock polarity 1 tsu SOMI SPCH M Setup time SPISOMI before 35 35 16 SPICLK high clock polarity 0 ns tsu SOMI SPCL M Setup time SPISOMI before 35 35 SPICLK low clock polarity 1 tv SPCH SOMI M Valid
58. Specification and Timing 1 13 HII 118 6 10 5 Serial Peripheral Interface SPI Master Mode Timing 118 6 10 6 SPI Slave Mode Timing 4 4 1 1 2 1 21 1146 6 nnn 123 6 10 7 On Chip Analog to Digital Converter nn II mnm ne nene nenne 125 6 10 7 1 ADC Power Up Control Bit Timing 126 6 10 7 2 Definitions uuu i ecteli Pra s a dd ERE bubuk 127 6 10 7 3 Sequential Sampling Mode Single Channel SMODE 0 128 6 10 7 4 Simultaneous Sampling Mode Dual Channel SMODE 1 129 6 11 Detailed Descriptions ask ska sns nnne 130 6 12 SESH uu uuu Tod Copyright 2003 2009 Texas Instruments Incorporated Contents 3 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 S TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 6 13 Timing 280 ONIY 132 7 Migrating From F280x Devices to C280x Devices
59. TI TMS320C2802PZS ACTIVE LQFP PZ 100 TBD Call TI Call TI TMS320C2802ZGMA ACTIVE BGA ZGM 100 TBD Call TI Call TI MICROSTAR TMS320C2802ZGMS ACTIVE BGA ZGM 100 TBD Call TI Call TI MICROSTAR TMS320F28015PZA ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F28015PZQ ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F28015PZS ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F28015ZGMA ACTIVE BGA ZGM 100 184 Green ROHS SNAGCU Level 3 260C 168 HR MICROSTAR amp no Sb Br TMS320F28016PZA ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br Addendum Page 1 PACKAGE OPTION ADDENDUM TEXAS INSTRUMENTS www ti com 5 Nov 2010 Orderable Device Status Package Type Package Pins Package Qty Eco Plan 2 Lead MSL Peak Temp Samples Drawing Ball Finish Requires Login TMS320F28016PZQ ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F28016PZS ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F2801GGMA ACTIVE BGA GGM 100 184 TBD SNPB Level 3 220C 168 HR MICROSTAR TMS320F2801GGMS ACTIVE BGA GGM 100 184 TBD SNPB Level 3 220C 168 HR MICROSTAR TMS320F2801PZA ACTIVE LQFP PZ 100 1 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F2801PZA 60 ACTIVE LQFP PZ 100 1 Green RoHS CU
60. Tester Pin Electronics Data Sheet Timing Reference Point 420 3 5 Output f 0 Under es Z0 50 04 Device Pin B 40pF 1 85 pF A Input requirements in this data sheet are tested with an input slew rate of lt 4 Volts per nanosecond 4 V ns at the device pin B The data sheet provides timing at the device pin For output timing analysis the tester pin electronics and its transmission line effects must be taken into account A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect The transmission line is intended as a load only It is not necessary to add or subtract the transmission line delay 2 ns or longer from the data sheet timing Figure 6 6 3 3 V Test Load Circuit Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 103 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 6 6 3 Device Clock Table This section provides the timing requirements and switching characteristics for the various clock options available on the 280x DSPs Table 6 6 and Table 6 7 list the cycle times of various clocks TEXAS INSTRUMENTS
61. Texas Instruments Incorporated Submit Documentation Feedback TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 Table 6 34 SPI Master Mode External Timing Clock Phase 0 2 3 4 5 TMS320F2809 TMS320F2808 TMS320F2806 SPI WHEN SPIBRR 1 IS EVEN OR SPI WHEN SPIBRR 1 IS ODD AND NO SPIBRR 0 OR2 SPIBRR 3 UNIT MIN MAX MIN MAX 1 Cycle time SPICLK co 128 127tc 5 tw SPCH M Pulse duration SPICLK high 0 5tc SPC M 10 0 5tc SPC M 0 5tc SPC M 0 5te Lco 10 0 5tc SPC M 0 5te Lco 2 clock polarity 0 T tw SPCL M Pulse duration SPICLK low 0 10 0 0 9 5te Lco 10 O StcisPc M 0 5tc Lco clock polarity 1 tw SPCL M Pulse duration SPICLK low 0 5te spcym 10 0 5 0 5 0 5 10 0 51 0 5 3 clock polarity 0 H tw SPCH M Pulse duration SPICLK high O 5ic sPc M 10 0 0 0 5 10 0 0 51 clock polarity 1 ta SPCH SIMO M Delay time SPICLK high to SPISIMO 10 10 1 valid clock polarity 0 s la SPCL SIMO M Delay time SPICLK low to SPISIMO 10 10 valid clock polarity 1 tv SPCL SIMO M Valid time SPISIMO data valid after 0 5tc SPC M 10 O StcisPc M 0 5tc Lco 10 5 SPICLK low clock
62. Two Quadrature Encoder Interfaces Up to Six 32 bit Six 16 bit Timers Serial Port Peripherals Up to 4 SPI Modules Up to 2 SCI UART Modules Up to 2 CAN Modules One Inter Integrated Circuit I2C Bus 12 Bit ADC 16 Channels 2x8 Channel Input Multiplexer Two Sample and Hold Single Simultaneous Conversions Fast Conversion Rate 80 ns 12 5 MSPS F2809 only 160 ns 6 25 MSPS 280x 267 ns 3 75 MSPS F2801x Internal or External Reference Up to 35 Individually Programmable Multiplexed GPIO Pins With Input Filtering Advanced Emulation Features Analysis Breakpoint Functions Real Time Debug via Hardware Development Support Includes ANSI C C Compiler Assembler Linker Code Composer Studio IDE DSP BIOS Digital Motor Control and Digital Power Software Libraries Low Power Modes and Power Savings IDLE STANDBY HALT Modes Supported Disable Individual Peripheral Clocks Please be aware that important notice concerning availability standard warranty and use critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet Code Composer Studio DSP BIOS MicroStar BGA TMS320C28x C28x TMS320C2000 are trademarks of Texas Instruments eZdsp is a trademark of Spectrum Digital All other trademarks are the property of their respective owners PRODUCTION DATA information is current as of publicati
63. V I O Design JTAG Boundary Scan Support High Performance 32 Bit CPU TMS320C28x 16 x 16 and 32 x 32 MAC Operations 16 x 16 Dual MAC Harvard Bus Architecture Atomic Operations Fast Interrupt Response and Processing Unified Memory Programming Model Code Efficient in C C and Assembly e On Chip Memory F2809 128K x 16 Flash 18K x 16 SARAM F2808 64K x 16 Flash 18K x 16 SARAM F2806 32K x 16 Flash 10K x 16 SARAM F2802 32K x 16 Flash 6K x 16 SARAM F2801 16K x 16 Flash 6K x 16 SARAM F2801x 16K x 16 Flash 6K x 16 SARAM 1K x 16 OTP ROM Flash Devices Only C2802 32K x 16 ROM 6K x 16 SARAM C2801 16K x 16 ROM 6K x 16 SARAM Boot ROM x 16 With Software Boot Modes via SCI SPI CAN 2 and Parallel Standard Math Tables Clock and System Control Dynamic PLL Ratio Changes Supported On Chip Oscillator Watchdog Timer Module Any GPIO A Pin Can Be Connected to One of the Three External Core Interrupts Peripheral Interrupt Expansion PIE Block That Supports All 43 Peripheral Interrupts 128 Bit Security Key Lock Protects Flash OTP LO L1 Blocks 1 IEEE Standard 1149 1 1990 Standard Test Access Port and Boundary Scan Architecture Prevents Firmware Reverse Engineering Three 32 Bit CPU Timers Enhanced Control Peripherals Up to 16 PWM Outputs Up to 6 HRPWM Outputs With 150 ps MEP Resolution Up to Four Capture Inputs Up to
64. clock to the CPU SYSCLKOUT is the output clock from the CPU The frequency of SYSCLKOUT is the same as CLKIN If CLKINDIV 0 n 2 if CLKINDIV 1 1 NOTE PLLSTS CLKINDIV enables or bypasses the divide by two block before the clock is fed to the core This bit must be 0 before writing to the PLLCR and must only be set after PLLSTS PLLLOCKS 1 The PLL based clock module provides two modes of operation Crystal operation This mode allows the use of an external crystal resonator to provide the time base to the device External clock source operation This mode allows the internal oscillator to be bypassed The device clocks are generated from an external clock source input on the X1 or the XCLKIN pin Table 3 17 Possible PLL Configuration Modes SYSCLKOUT PLL MODE REMARKS PLLSTS CLKINDIV CLKIN Invoked by the user setting the PLLOFF bit in the PLLSTS register The PLL block 0 OSCCLK 2 is disabled in this mode This can be useful to reduce system noise and for low PLL Off power operation The PLLCR register must first be set to 0x0000 PLL Bypass before entering this mode The CPU clock CLKIN is derived directly from the 1 OSCCLK input clock on either X1 X2 X1 or XCLKIN PLL Bypass is the default PLL configuration upon power up or after an external 0 OSCCLK 2 PLL Bypass reset XRS This mode is selected when the PLLCR register is set to 0x0000 or yp while the PLL locks to a new
65. counter does not change with the limp mode clock In addition to this the device will be reset and the Missing Clock Status MCLKSTS bit will be set These conditions could be used by the application firmware to detect the input clock failure and initiate necessary shut down procedure for the system NOTE Applications in which the correct CPU operating frequency is absolutely critical should implement a mechanism by which the DSP will be held in reset should the input clocks ever fail For example an R C circuit may be used to trigger the XRS pin of the DSP should the capacitor ever get fully charged An pin be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged Such a circuit would also help in detecting failure of the flash memory and the rail 50 Functional Overview Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 Pe Rees TMS320C2801 TMS320F28016 TMS320F28015 3 6 2 Watchdog Block The watchdog block on the 280x is similar to the one used on the 240x and 281x devices The watchdog module generates an output pulse 512 oscillator clocks wide OSCCLK whenever the 8 bit watchdog up counter has r
66. designate the stages in the product development cycle assigns prefixes to the part numbers of all TMS320 DSP devices and support tools Each TMS320 DSP commercial family member has one of three prefixes TMX TMP or TMS e g TMS320F2808 Texas Instruments recommends two of three possible prefix designators for its support tools TMDX and TMDS These prefixes represent evolutionary stages of product development from engineering prototypes TMX TMDX through fully qualified production devices tools TMS TMDS Device development evolutionary flow TMX Experimental device that is not necessarily representative of the final device s electrical specifications TMP Final silicon die that conforms to the device s electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Support tool development evolutionary flow TMDX Development support product that has not yet completed Texas Instruments internal qualification testing TMDS qualified development support product TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer Developmental product is intended for internal evaluation purposes TMS devices and TMDS development support tools have been characterized fully and the quality and reliability of the device have been demonstrated fully Tl s standard warranty applies Device Support Copyright 2003 2009 Texas In
67. ensure 5 sampling periods for detection to occur Since external signals are driven asynchronously an 13 SYSCLKOUT wide pulse ensures reliable recognition Figure 6 12 Sampling Mode Table 6 15 General Purpose Input Timing Requirements MIN MAX UNIT QUALPRD 0 1tesco cycles tw SP Sampling period QUALPRD 0 2lcsco QUALPRD cycles twiasw Input qualifier sampling window twp n 1 cycles Synchronous mode 2t cycles Pulse duration GPIO low high y With input qualifier twiasw twsp 1lc sco cycles 1 represents the number of qualification samples as defined by GPxQSELn register 2 For twp pulse width is measured from to Vi for an active low signal and to for an active high signal 110 Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 Texas TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 6 9 3 Sampling Window Width for Input Signals The following section summarizes the sampling window width for input signals for various input qualifier configurations Sampling frequency denotes how often a sign
68. frequency after the PLLCR register has been 1 OSCCLK modified In this mode the PLL itself is bypassed but the PLL is not turned off Achieved by writing a non zero value n into the PLLCR register Upon writing to the PLLCR the device will switch to PLL Bypass mode until the PLL locks NA Copyright 2003 2009 Texas Instruments Incorporated Functional Overview 49 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 3 6 1 3 Loss of Input Clock In PLL enabled and PLL bypass mode if the input clock OSCCLK is removed or absent the PLL will still issue a limp mode clock The limp mode clock continues to clock the CPU and peripherals at a typical frequency of 1 5 MHz Limp mode is not specified to work from power up only after input clocks have been present initially In PLL bypass mode the limp mode clock from the PLL is automatically routed to the CPU if the input clock is removed or absent Normally when the input clocks are present the watchdog counter decrements to initiate a watchdog reset or WDINT interrupt However when the external input clock fails the watchdog counter stops decrementing i e the watchdog
69. if the CPU clock CLKIN is turned off The various low power modes operate as follows IDLE Mode This mode is exited by any enabled interrupt or an XNMI that is recognized by the processor The LPM block performs no tasks during this mode as long as the LPMCRO LPM bits are set to 0 0 STANDBY Mode GPIO port A signal GPIO 31 0 can wake the device from STANDBY mode The user must select which signal s will wake the device in the GPIOLPMSEL register The selected signal s are also qualified by the OSCCLK before waking the device The number of OSCCLKs is specified in the LPMCRO register HALT Mode Only the XRS any GPIO port A signal GPIO 31 0 can wake the device from HALT mode The user selects the signal in the GPIOLPMSEL register NOTE The low power modes do not affect the state of the output pins PWM pins included They will be in whatever state the code left them in when the IDLE instruction was executed See the TMS320x280x 2801x 2804x DSP System Control and Interrupts Reference Guide literature number SPRU712 for more details 52 Functional Overview Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 Texas TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320
70. j tw SPCL S Pulse duration SPICLK low clock polarity 0 O 5tcspo s 10 0 5tc sPc s tw SPCH S Pulse duration SPICLK high clock polarity 1 O 5tcspo s 10 O 5tcsPc s lsu SOMI SPCH S Setup time SPISOMI before SPICLK high clock polarity 0 0 125tc spc s 17 tsu SOMI SPCL S Setup time SPISOMI before SPICLK low 0 125t spc s ns clock polarity 1 tv SPCL SOMI S Valid time SPISOMI data valid after SPICLK low 0 75tc sPC s 18 clock polarity 1 m tv SPCH SOMI S Valid time SPISOMI data valid after SPICLK high 0 75tc sPC 5 clock polarity 0 tsu SIMO SPCH S Setup time SPISIMO before SPICLK high clock polarity 0 35 T tsu SIMO SPCL S Setup time SPISIMO before SPICLK low clock polarity 1 35 tv SPCH SIMO S Valid time SPISIMO data valid after SPICLK high O 5tc spc s 10 55 clock polarity 0 T tv SPCL SIMO S Valid time SPISIMO data valid after SPICLK low O StcisPc s 10 clock polarity 1 1 The MASTER SLAVE bit SPICTL 2 is cleared and the CLOCK PHASE bit SPICTL 3 is cleared 2 tc sPc SPI clock cycle time LSPCLK 4 or LSPCLK SPIBRR 1 3 Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate Master mode transmit 25 MHz MAX master mode receive 12 5 MHz MAX Slave mode transmit 12 5 MHz MAX slave mode receive 12 5 MHz MAX 4 The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit
71. more then one GPIO pin Also when an input signal is not selected the input signal will default to either a O or 1 state depending on the peripheral Copyright 2003 2009 Texas Instruments Incorporated Peripherals 85 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS 5320 2801 TMS320F28016 TMS320F28015 Nene SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 5 Device Support 5 1 86 Texas Instruments offers an extensive line of development tools for the C28x generation of DSPs including tools to evaluate the performance of the processors generate code develop algorithm implementations and fully integrate and debug software and hardware modules The following products support development of 280x based applications Software Development Tools Code Composer Studio Integrated Development Environment IDE C C Compiler Code generation tools Assembler Linker Cycle Accurate Simulator Application algorithms Sample applications code Hardware Development Tools 2808 eZdsp Evaluation modules e JTAG based emulators SPI515 XDS510PP XDS510PP Plus XDS510USB Universal 5 V dc power supply Documentation and cables Device and Development Support Tool Nomenclature To
72. state With input qualifier 100tc sco tuwAKE INT laWwAKE STBY Wake up from flash Without input qualifier 1125t sco _ cycles dea module in sleep input qualifier 1125tysco d WEE SARAN Without input qualifier 100tcsco Suns rom E x d With input qualifier 100tc sco tw WAKE INT I 1 This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction execution of an ISR triggered by the wake up signal involves additional latency ke E B K D 9 P Device STANDBY STANDBY X Normal Execution Status Flushing Pipeline Wake up Signal f 4 lw WAKE INT gt 9 td WAKE STBY P X1 X2 or XCLKIN 48 ta DLE XCOL A IDLE instruction is executed to put the device into STANDBY mode B The PLL block responds to the STANDBY signal SYSCLKOUT is held for approximately 32 cycles if CLKINDIV 0 or 64 cycles if CLKINDIV 1 before being turned off This delay enables the CPU pipe and any other pending operations to flush properly C Clock to the peripherals are turned off However the PLL and watchdog are not shut down The device is now in STANDBY mode D The external wake up signal is driven active After a latency period the STANDBY mode is exited F Normal execution resumes The device will respond to the interrupt if enabled F
73. the digital portion of the ADC module Turning off the clock to the ADC module results in the elimination of the current drawn by the analog portion of the ADC Ippa18 as well NOTE Ippio Current consumption is reduced by 15 mA typical when XCLKOUT is turned off NOTE The baseline lpp current current when the core is executing a dummy loop with no peripherals enabled is 110 mA typical To arrive at the lpp current for a given application the current drawn by the peripherals enabled by that application must be added to the baseline lpp current Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 99 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 Texas TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 6 4 2 Current Consumption Graphs 250 0 200 0 1500 2 5 100 0 50 0 0 0 10 20 30 40 50 60 70 80 90 100 SYSCLKOUT MHz m IDD IDDA18 4 1 8 V current 6 IDDIO lt lt IDD3VFL e 3 3 V current Figure 6 1 Typical Operational Current Versus Frequency F2808 600 0 500 0 400 0 300 0
74. time SPISOMI data valid after 0 25tcsPc M 10 O StcisPc M 10 1 SPICLK high clock polarity 0 ns tv SPCL SOMI M Valid time SPISOMI data valid after 0 25tc spcym 10 0 5tc spcym 10 SPICLK low clock polarity 1 1 The MASTER SLAVE bit SPICTL 2 is set and the CLOCK PHASE bit SPICTL 3 is set 2 tc sPc SPI clock cycle time LSPCLK 4 or LSPCLK SPIBRR 1 3 Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate Master mode transmit 25 MHz MAX master mode receive 12 5 MHz MAX Slave mode transmit 12 5 MHz MAX slave mode receive 12 5 MHz MAX teco LSPCLK cycle time 5 The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit SPICCR 6 Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 121 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 5320 2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 ip Texas TMS320C2801 TMS320F28016 TMS320F28015 NSIRUMENIS SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 1 gt SPICLK clock polarity 0 4 3 gt SPICLK clock polarity 1 48 6 4 7 PISO 52055005509 Data Valid l
75. 00 ms 8K Sector 250 ms 4K Sector 125 ms Erase Time 16K Sector 10 S 8K Sector 10 S 4K Sector 10 S IppavrFLP Vpp3veL Current consumption during the Erase 75 mA Erase Program cycle Program 35 mA Ippp Vpp current consumption during 140 mA Erase Program cycle IppioP Vppio current consumption during 20 mA Erase Program cycle 1 Typical parameters as seen at room temperature including function call overhead with all peripherals off Table 6 46 Flash OTP Access Timing PARAMETER MIN TYP MAX UNIT la tp Paged flash access time 36 ns la tr Random flash access time 36 ns ta oTP OTP access time 60 ns Equations to compute the Flash page wait state and random wait state in Table 6 47 are as follows lat Flash Page Wait State round up to the next highest integer or 0 whichever is larner c SCO t ali up to the next highest integer 1 whichever is larger Flash Random Wait State 5 Equation to compute the OTP wait state in Table 6 47 is as follows t OTP Wait State Yon up to the next highest integer or 1 whichever is larger c SCO Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 131 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS32
76. 01 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 6 9 4 Low Power Mode Wakeup Timing Table 6 16 shows the timing requirements Table 6 17 shows the switching characteristics and Figure 6 14 shows the timing diagram for IDLE mode Table 6 16 IDLE Mode Timing Requirements MIN NOM MAX UNIT Without input qualifier 2tcsco twwAkE INT Pulse duration external wake up signal m m cycles With input qualifier 5tc sco twiiasw 1 For an explanation of the input qualifier parameters see Table 6 15 Table 6 17 IDLE Mode Switching Characteristics PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Delay time external wake signal to program execution resume Wake up from Flash Without input qualifier 20 cycles Flash module in active state With input qualifier 20tc sco twiiasw d WAKE IDLE Wake up from Flash Without input qualifier 10505 cycles Flash module in sleep state With input qualifier 1050tc sco twiosw Wake up from SARAM Without input qualifier 20 cycles With input qualifier 20tc sco twiiasw 1 For an explanation of the input qualifier parameters see Table 6 15 2 This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction execution of an ISR triggered by the wake up signal involves additional latency
77. 01x 2804x Enhanced Pulse Width Modulator SPRU791 0 X ePWM Module TMS320x280x 2801x 2804x High Resolution Pulse Width Modulator SPRU924 0 X TMS320x280x 2801x 2804x Enhanced Capture eCAP Module SPRU807 0 X TMS320x280x 2801x 2804x Enhanced Quadrature Encoder Pulse SPRU790 0 X eQEP Module TMS320x280x 2801x Enhanced Controller Area Network eCAN SPRUEUO 0 X TMS320x280x 2801x 2804x Serial Communication Interface SCI SPRUFK7 0 X TMS320x280x 2801x 2804x Serial Peripheral Interface SPRUG72 0 X TMS320x28xx 28xxx Inter Integrated Circuit Module SPRU721 0 X 1 A type change represents a major functional feature difference in a peripheral module Within a peripheral type there may be minor differences between devices that do not affect the basic functionality of the module These device specific differences are listed in the TMS320x28xx 28xxx DSP Peripheral Reference Guide literature number SPRU566 and in the peripheral reference guides 88 The following documents are available on the TI website www ti com CPU User s Guides SPRU430 SPRU712 TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit CPU and the assembly language instructions of the TMS320C28x fixed point digital signal processors DSPs It also describes emulation features available on these DSPs TMS320x280x 2801x 2804x DSP System Control and Interrupts Reference Guide describes the various interrupts a
78. 03 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 6 6 Timing Parameter Symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100 To shorten the symbols some of the pin names and other related terminology have been abbreviated as follows Lowercase subscripts and their Letters and symbols and their meanings meanings a access time H High cycle time period L Low d delay time V Valid f fall time X oe changing or don t care h hold time Z High impedance r rise time su setup time t transition time valid time w pulse duration width 6 6 1 General Notes on Timing Parameters All output signals from the 28x devices including XCLKOUT are derived from an internal clock such that all output transitions for a given half cycle occur with a minimum of skewing relative to each other The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles For actual cycle examples see the appropriate cycle description section of this document 6 6 2 Test Load Circuit This test load circuit is used to measure all switching characteristics provided in this document
79. 0F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 ee SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com Table 6 47 Minimum Required Flash OTP Wait States at Different Frequencies Svea SYSCLKOUT ns WAT STATE WAIT STATEC OTP WAIT STATE 100 10 3 3 5 75 13 33 2 2 4 60 16 67 2 2 3 50 20 1 1 2 30 33 33 1 1 1 25 40 0 1 1 15 66 67 0 1 1 4 250 0 1 1 1 Random wait state must be greater than or equal to 1 6 13 ROM Timing C280x only Table 6 48 ROM OTP Access Timing PARAMETER MIN TYP MAX UNIT ta rp Paged ROM access time 19 ns lam Random ROM access time 19 ns ta ROM ROM OTP area access time 1 60 ns 1 In C280x devices a 1K X 16 ROM block replaces the OTP block found in Flash devices Equations to compute the page wait state and random wait state in Table 6 49 are as follows t ROM Page Wait State i alp round up to the next highest integer or 0 whichever is larger c SCO ROM Random Wait State round up to the next highest integer or 1 whichever is larger Table 6 49 ROM ROM OTP area Minimum Required Wait States at Different Frequencies SYSCLKOUT SYSCLKOUT PAGE RANDOM MHz ns WAIT STATE WAIT STATE 100 10 1 1 75 13 33 1 1 50 20 0 1 30 33 33 0 1 25 40 0 1 15 66 67 0 1 4 250 0 1 1 Random wait
80. 0F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 NSTRUMENTS SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 8 Revision History This data sheet revision history highlights the technical changes made to the SPRS230K device specific data sheet to make it an SPRS230L revision Scope Changed MIN value Flash endurance for the array write erase cycles from 100 cycles to 20000 cycles See Table 6 43 and Table 6 44 Changed TYP N value Flash endurance for the array write erase cycles from 1000 cycles to 50000 cycles See Table 6 43 and Table 6 44 See table below LOCATION ADDITIONS DELETIONS AND MODIFICATIONS Table 2 3 Signal Descriptions TRST Changed In a low noise environment TRST may be left floating In other instances an external pulldown resistor is highly recommended to An external pulldown resistor is required on this pin Figure 4 4 ePWM Sub Modules Showing Critical Internal Signal Interconnections Changed TBCTL CNTLDE to TBCTL PHSEN Resized HiRes PWM HRPWM dashed box Table 4 5 ADC Registers Ox711E 0Ox711F Changed DESCRIPTION from ADC Status Register to Reserved Section 5 2 Documentation Support Updated Software list Table 6 37 SPI Slave Mode External Timing Clock Phase 1 Parameter 18 Valid time SPISOMI data valid after SPICLK low Changed clock polarity 0 to clock polarit
81. 1 cycle delay Peripheral Frame 2 0 wait writes 2 wait reads aA Fixed LO amp L1 SARAMs 0 wait Programmable Programmed via the Flash registers 1 wait state operation OTP wait minirnum is possible ata reduced CPU frequency See Section 3 2 5 for more information Programmed via the Flash registers 0 wait state operation Flash Programmable is possible at reduced CPU frequency The CSM password 0 wait minimum locations are hardwired for 16 wait states See Section 3 2 5 for more information HO SARAM 0 wait Fixed Boot ROM 1 wait Fixed Copyright 2003 2009 Texas Instruments Incorporated Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 Functional Overview Submit Documentation Feedback 5320 2801 5320 28016 TMS320F28015 33 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 3 2 Brief Descriptions 3 2 1 C28x CPU C28x DSP generation is the newest member of the TMS320C2000 DSP platform The C28x is very efficient C C engine enabling users to develop not only their system control software in a high level language but also enables math algorithms to be developed using C C The C28x is as efficient in DSP math tasks as it is in system control tasks t
82. 120 uA 5 50 uA 15 pA 30 pA 1 lppio current is dependent on the electrical loading on the pins 2 Ippaig includes current into and pins In order to realize the currents shown for IDLE STANDBY and HALT clock to the ADC module must be turned off explicitly by writing to the PCLKCRO register lppass includes current into and Vppaio pins 4 TYP numbers are applicable over room temperature and nominal voltage MAX numbers are at 125 C and MAX voltage NOTE The peripheral multiplexing implemented in the 280x devices prevents all available peripherals from being used at the same time This is because more than one peripheral function may share an pin It is however possible to turn on the clocks to all the peripherals at the same time although such a configuration is not useful If this is done the current drawn by the device will be more than the numbers specified in the current consumption tables 98 Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 5320 2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 6 4 1 Reducing Current
83. 15 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 6 10 4 2 Electrical Specification and Timing Table 6 33 2 Timing TEXAS INSTRUMENTS www ti com TEST CONDITIONS MIN MAX UNIT fscL SCL clock frequency 2 clock module frequency is between 400 kHz 7 MHz and 12 MHz and 2 prescaler and clock divider registers are configured appropriately Vil Low level input voltage 0 3 Vppio V Vin High level input voltage 0 7 Vppio V Vnys Input hysteresis 0 05 Vppio V Vol Low level output voltage 3 mA sink current 0 0 4 V Low period of SCL clock 2 clock module frequency is between 1 3 us 7 MHz and 12 MHz 2 prescaler and clock divider registers are configured appropriately High period of SCL clock 2 clock module frequency is between 0 6 us 7 MHz and 12 MHz and 2 prescaler and clock divider registers are configured appropriately Input current with input voltage 10 10 between 0 1 Vppio and 0 9 Vppio 6 10 5 Serial Peripheral Interface SPI Master Mode Timing Table 6 34 lists the master mode timing clock phase 0 and Table 6 35 lists the timing clock 118 phase 1 Figure 6 20 and Figure 6 21 show the timing waveforms Electrical Specifications Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 TMS320F28015 Copyright 2003 2009
84. 2 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Table 6 3 TMS320F2802 TMS320F2801 Current Consumption by Power Supply Pins at 100 MHz SYSCLKOUT MODE 2 3 4 1 Ipp Ippio IppavrL Ippais Ippaas TESE GONDITIONS TYP MAX TYP MAX TYP MAX Operational Flash The following peripheral clocks are enabled 1 2 3 e 1 2 1 SCI A SPI A ADC 2 180mA 210 15 mA 27 mA 35mA 40 30mA 38 mA 1 5 mA 2mA All PWM pins are toggled at 100 kHz All I O pins are left unconnected Data is continuously transmitted out of the SCI A SCI B and eCAN A ports The hardware multiplier is exercised Code is running out of flash with 3 wait states XCLKOUT is turned off IDLE Flash is powered down XCLKOUT is turned off The following peripheral clocks are enabled eCAN A 75 mA 90 mA 500 pA 2mA 2 pA 10 uA 5 yA 50 pA 15 uA 30 pA e 5 SPA J2C STANDBY Flash is powered down Peripheral clocks are 6mA 12 100pA 500 2yA 10pA 5pA 50uA 15 HALT Flash is powered down Peripheral clocks are off 70 pA 60 pA 120 pA 2 pA 10 pA 5 50 uA 15 30 uA Input clock is disabled 1 current is dependent on the electrical l
85. 20C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 Texas TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 2 Introduction The TMS320F2809 5320 2808 5320 2806 TMS320F2802 TMS320F2801 TMS320F28015 TMS320F28016 TMS320C2802 and TMS320C2801 devices members of the TMS320C28x DSP generation are highly integrated high performance solutions for demanding control applications Throughout this document TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28015 and TMS320F28016 are abbreviated as F2809 F2808 F2806 F2802 F2801 C2802 C2801 F28015 and F28016 respectively TMS320F28015 and TMS320F28016 are abbreviated as F2801x Table 2 1 provides a summary of features for each device Copyright 2003 2009 Texas Instruments Incorporated Introduction 11 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 TEXAS INSTRUMENTS www ti com Table 2 1 Hardware Features 100 MHz Devices
86. 20F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 eCAN A Memory 512 Bytes TEXAS INSTRUMENTS www ti com eCAN A Control and Status Registers Mailbox Enable CANME Mailbox Direction CANMD Transmission Request Set CANTRS Transmission Request Reset CANTRR Transmission Acknowledge CANTA Abort Acknowledge CANAA Received Message Pending CANRMP Received Message Lost CANRML h 6000 Control and Status Registers 603Fh 6040h Local Acceptance Masks LAM 607Fh 32 x 32 Bit RAM Remote Frame Pending CANRFP Global Acceptance Mask CANGAM 6080h Message Object Time Stamps MOTS 60BFh 32 x 32 Bit RAM Master Control Bit Timing Configuration CANBTC 60C0h Message Object Time Out MOTO 60FFh 32 x 32 Bit RAM eCAN A Memory RAM 512 Bytes 6100h 6107h Mailbox 0 Error and Status CANES Transmit Error Counter CANTEC Receive Error Counter CANREC Global Interrupt Flag 0 CANGIF0 Global Interrupt Mask CANGIM Global Interrupt Flag 1 CANGIF1 Mailbox Interrupt Mask CANMIM 6108h 610Fh Mailbox 1 Mailbox Interrupt Level CANMIL 6110h 6117h Mailbox 2 Overwrite Protection Control 6118h 611Fh Mailbox 3 TX I O Control CANTIOC 6120h 6127h
87. 20F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 Texas TMS320C2801 TMS320F28016 TMS320F28015 NSTRUMENTS 4 1 SPICLK clock polarity 0 Z 7 92 SPICLK clock polarity 1 4 4 5 gt SPISIMO Master Out Data ts Valid XY 8 68 gt 9 00000000000 Master In Data X SPISOM Mast Be valid PR 005 0056 000 SPISTE A A In the master mode SPISTE goes active 0 5t gpc minimum before valid SPI clock edge On the trailing end of the word the SPISTE will go inactive 0 5t spc after the receiving edge SPICLK of the last data bit except that SPISTE stays active between back to back transmit words in both FIFO and non FIFO modes Figure 6 20 SPI Master Mode External Timing Clock Phase 0 120 Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 Texas TMS320F2802 TMS320F2801 TMS320C2802 Pie ee TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Table 6 35 SPI Master Mode External Timing Clock Phase 1 9 9 4 5 SPI WHEN SPIBRR 1 IS EVEN OR SPI WHEN SPIBRR 1 IS ODD AND NO
88. 2808 5320 2806 5320 2802 TMS320F2801 5320 2802 5320 2801 5320 28016 5320 28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 TEXAS INSTRUMENTS www ti com Signal Descriptions continued PIN NO NAME pz GGM DESCRIPTION PIN ZGM BALL GPIO6 General purpose input output 6 1 0 2 9 EPWM4A 56 G9 Enhanced PWM4 output and HRPWM channel not available on 2801 2802 O EPWMSYNCI External ePWM sync pulse input I EPWMSYNCO External ePWM sync pulse output O GPIO7 General purpose input output 7 1 0 2 9 58 G8 Enhanced PWM4 output B not available on 2801 2802 SPISTED SPI D slave transmit enable not available on 2801 2802 I O ECAP2 Enhanced capture input output 2 I O GPIO8 General purpose input output 8 1 0 2 9 EPWM5A 60 F9 Enhanced PWM5 output A and HRPWM channel not available on 2801 2802 O CANTXB Enhanced CAN B transmit not available on 2801 2802 F2806 O ADCSOCAO ADC start of conversion A O GPIO9 General purpose input output 9 1 0 2 9 EPWM5B 61 F8 Enhanced 5 output B not available on 2801 2802 O SCITXDB SCI B transmit data not available on 2801 2802 O Enhanced capture input output 3 not available 2801 2802 I O GPIO10 General pu
89. 280x devices contain these two blocks of single access memory each 1K x 16 in size The stack pointer points to the beginning of block M1 on reset The MO and M1 blocks like all other memory blocks on C28x devices are mapped to both program and data space Hence the user can use MO and M1 to execute code or for data variables The partitioning is performed within the linker The C28x device presents a unified memory map to the programmer This makes for easier programming in high level languages Copyright 2003 2009 Texas Instruments Incorporated Functional Overview 35 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 5320 28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 ee SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 3 2 8 L0 L1 SARAMs The F2809 and F2808 each contain an additional 16K x 16 of single access RAM divided into 3 blocks LO 4K L1 4K 0 8 The F2806 contains an additional 8K x 16 of single access RAM divided into 2 blocks LO 4K L1 4K The 2802 F2801 C2802 and C2801 each contain an additional 4K x 16 of single access RAM L0 4K Each block can be independently accessed to minimize CPU pipeline stalls Each block is mapped to both program and data space 3 2 9 Boot ROM The Boot ROM is factor
90. 288 a O a2 ui o ane 2 8 or lt lt u a Onn IJE 58288 os T 0 999 549 5 250 88 2058 595 9 amp nono FFFO 6 gt gt gt 60 gt gt 6 0 0 gt 06660 GPIO16 SPISIMOA TZ5 Vss Vss XRS GPIOS EPWM2B SPISTEB GPIO27 GPIOO EPWM1A EMUO Vppio EMU1 GPIO2 EPWM2A Vppio GPIO1 EPWM1B SPISIMOB GPIO24 ECAP1 GPIO34 TRST Vpp Vpp Vss x2 Vpp2A18 Vss Vss2AGND x1 ADCRESEXT Vss ADCREFP XCLKIN ADCREFM GPIO25 ECAP2 SPISOMIB ADCREFIN GPIO28 SCIRXDA TZ5 ADCINB7 Vpp ADCINB6 Vss ADCINB5 SPISOMIB GPIO13 TZ2 ADCINB4 A ADCINB3 TEST1 ADCINB2 TEST2 ADCINB1 SPICLKB GPIO26 ADCINBO GPIO32 SDAA EPWMSYNCI ADSOCAO Vppato RosRREZERRSPSIPIISIIBSIIIQ a gt Sag gt gt o a lt s 0 gt X lt lt lt lt lt lt lt lt gt S 5685099 5 290098 o n 8266206 o a ao GPIO33 SCLA EPWMSYNCO ADCSOCBO A the C280x devices the VppavFL pin is Vbpio Figure 2 3 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 100 Pin PZ LQFP Top View 16 Introduction Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TM
91. 30L OCTOBER 2003 REVISED DECEMBER 2009 The user can select the type of input qualification for each GPIO pin via the GPxQSEL1 2 registers from four choices Synchronization To SYSCLKOUT Only GPxQSEL1 2 0 0 This is the default mode of all GPIO pins at reset and it simply synchronizes the input signal to the system clock SYSCLKOUT Qualification Using Sampling Window GPxQSEL1 2 0 1 and 1 0 In this mode the input signal after synchronization to the system clock SYSCLKOUT is qualified by a specified number of cycles before the input is allowed to change Time between samples GPyCTRL Reg Qualification Input Signal Qualified By 3 or 6 Samples GPxQSEL SYSCLKOUT Number of Samples Figure 4 17 Qualification Using Sampling Window The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in groups of 8 signals It specifies a multiple of SYSCLKOUT cycles for sampling the input signal The sampling window is either 3 samples or 6 samples wide and the output is only changed when ALL samples are the same all Os or all 1s as shown in Figure 6 12 for 6 sample mode No Synchronization GPxQSEL1 2 1 1 This mode is used for peripherals where synchronization is not required synchronization is performed within the peripheral Due to the multi level multiplexing that is required on the 280x device there may be cases where a peripheral input signal can be mapped to
92. 320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 eee SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com je C10 re iem 4 K 9 C5 The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen The waveform relationship shown is intended to illustrate the timing parameters only and may differ based on actual configuration B XCLKOUT configured to reflect SYSCLKOUT Figure 6 7 Clock Timing 6 8 Power Sequencing No requirements are placed on the power up down sequence of the various power pins to ensure the correct reset state for all the modules However if the 3 3 V transistors in the level shifting output buffers of the I O pins are powered prior to the 1 8 V transistors it is possible for the output buffers to turn on causing a glitch to occur on the pin during power up To avoid this behavior power the Vpp core voltage pins prior to or simultaneously with the Vppio input output voltage pins ensuring that the Vpp pins reached 0 7 V before the Vppio pins reach 0 7 V There are some requirements on the XRS pin 1 During power up the XRS pin must be held low for tag 1 after the input clock is stable see Table 6 13
93. 320F2809 TMS320F2808 TMS320F2806 Texas TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 3 2 4 Heal Time JTAG and Analysis The 280x implements the standard IEEE 1149 1 JTAG interface Additionally the 280x supports real time mode of operation whereby the contents of memory peripheral and register locations can be modified while the processor is running and executing code and servicing interrupts The user can also single step through non time critical code while enabling time critical interrupts to be serviced without interference The 280x implements the real time mode in hardware within the CPU This is a unique feature to the 280x no software monitor is required Additionally special analysis hardware is provided which allows the user to set hardware breakpoint or data address watch points and generate various user selectable break events when a match occurs 3 25 Flash The F2809 contains 128K x 16 of embedded flash memory segregated into eight 16K x 16 sectors The F2808 contains 64K x 16 of embedded flash memory segregated into four 16K x 16 sectors The F2806 and F2802 have 32K x 16 of embedded flash segregated into four 8K x 16 sectors The F2801 device contains 16K x 16 of embedded flash segregated into four 4K x 16 sectors All five devices also contain a single 1K x 16 of OTP memory at address range Ox3D 7800 Ox3D 7BFF The user
94. 39 3 2 19 32 0 1 2 39 3 2 20 Control Peripherals 39 3 2 21 Serial Port Peripherals 41 11 5 40 3 3 Register FOIE 40 3 4 Device Emulation Registers 42 3 5 m 42 3 5 1 External Interrupts 1 45 3 6 System 46 3 6 1 OSG and PEL Block DD 47 3 6 1 1 External Reference Oscillator Clock Option 22 421 48 3 6 4 2 PLI Based Clock Module uuu teurer necu tle T ce dnd 49 Lbossof Inp t ays de ende E 50 3 6 2 X Watchdog Block 1 111 ne hehe nnn nne ne ne nnn 51 3 7 Low Power Modes Block 52 4 Peripherals U L 53 4 1 2 0 2 25 S ks w NSS ER ERE AED M EMI
95. 5 oE RX ERR INT ENA SCICTL1 6 SCI RX Interrupt select logic Figure 4 13 Serial Communications Interface SCI Module Block Diagram Copyright 2003 2009 Texas Instruments Incorporated Peripherals 75 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 5320 2802 TMS320F2801 5320 2802 5320 2801 5320 28016 5320 28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 4 9 Serial Peripheral Interface SPI Modules SPI A SPI B SPI C SPI D 76 The 280x devices include the four pin serial peripheral interface SPI module Up to four SPI modules SPI A SPI B SPI C and SPI D are available The SPI is a high speed synchronous serial I O port that allows a serial bit stream of programmed length one to sixteen bits to be shifted into and out of the device at a programmable bit transfer rate Normally the SPI is used for communications between the DSP controller and external peripherals or another processor Typical applications include external I O or peripheral expansion through devices such as shift registers display drivers and ADCs Multidevice communications are supported by the master slave operation of the SPI The SPI module features include Four external pins SPISOMI SPI sla
96. 6K x 16 C2801 12 PWM outputs 6 trip zones 6 timers 16 bit lt FLASH 128K x 16 F2809 64K x 16 F2808 32K x 16 F2806 32 32K x 16 F2802 16K x 16 F2801 System Control 16K x 16 F2801x XCLKOUT lt XRS Oscillator PLL 4 Peripheral Clocking Low Power Modes D Xo Watchdog 7 OTP lt 1K x 16 ADCSOCA B 5 prn gt 1 wait state 16 Channels Protected by the code security module Peripheral Bus 43 of the possible 96 interrupts are used on the devices B Not available in F2802 F2801 C2802 and C2801 C Not available in F2806 F2802 F2801 C2802 and C2801 D The 1K x 16 OTP has been replaced with 1K x 16 ROM for C280x devices Figure 3 1 Functional Block Diagram Copyright 2003 2009 Texas Instruments Incorporated Functional Overview Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 TMS320F28015 25 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 NOEROMENDS SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 31 Memory Maps Block Start Address Data Space Prog Space 0x00 0000 0 Vector RAM 32 x 32 Enabled if VMAP 0 0x00 0040 0 SARAM 1K x 16 4i ee M1 SARAM 1K x 16 0x00 0800 Peripheral Fra
97. 802 INSTRUMENTS TMS320C2801 TMS320F28016 TMS320F28015 Table 3 1 Addresses of Flash Sectors in F2809 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3D 8000 0x3D BFFF Sector H 16K x 16 0x3D C000 0x3D FFFF Sector G 16K x 16 0x3E 0000 0x3E 3FFF Sector F 16K x 16 0x3E 4000 0x3E 7 Ox3E 8000 Ox3E BFFF C000 Ox3E FFFF Sector C 16K x 16 0000 OxSF Sector E 16K x 16 Sector D 16K x 16 Sector B 16K x 16 4000 7F7F 7F80 7FF5 Ox3F 7FF6 OxSF 7FF7 Ox3F 7FF8 OxSF 7FFF Sector A 16K x 16 Program to 0x0000 when using the Code Security Module Boot to Flash Entry Point program branch instruction here Security Password 128 Bit Do not program to all zeros Table 3 2 Addresses of Flash Sectors in F2808 ADDRESS RANGE PROGRAM AND DATA SPACE Ox3E 8000 Ox3E BFFF Sector D 16K x 16 Ox3E C000 Ox3E Sector C 16K x 16 0000 Sector B 16K x 16 Ox3F 4000 OxSF 7F7F Ox3F 7F80 Ox3F 7FF5 Ox3F 7FF6 OxSF 7FF7 Ox3F 7FF8 OxSF 7FFF Sector A 16K x 16 Program to 0x0000 when using the Code Security Module Boot to Flash Entry Point program branch instruction here Security Password 128 Bit Do not program to all zeros Table 3 3 Addresse
98. A converter WCSP package 106 Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 5 INSTRUMENTS www ti com VppsvFL Vppa2 VpDAIO 3 3 V Vpp1A18 Vpp2A18 1 8 V XCLKIN XCLKOUT XRS TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 UM N INS NN NS LXXXXX 4 AS XS SN OSCCLK 8 A User Code Dependen toscsT gt tw RSL1 9 Address Data Valid Internal Boot ROM Code Execution Phase Address Data Control Internal ta Ex User Code Execution Phase tn boot mode User Code Dependent Boot Mode GPIO Pins as Input Pins n Peripheral GPIO Function Boot ROM Execution Starts Based on Boot Code Pins C GPIO Pins as Input State Depends on Internal PU PD User Code Dependent A Upon power up SYSCLKOUT is OSCCLK 2 Since the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0 SYSCLKOUT is further divided by 4 before it appears at XCLKOUT This explains why XCLKOUT OSCCLK 8 during this phase B After reset the boot ROM
99. A85 SPRAA88 SPRAA 91 SPRAAH1 SPRAAI1 SPRAAD5 SPRAAD8 Device Support Key Links Include 1 C2000 Get Started www ti com c2000getstarted 2 C2000 Digital Motor Control Software Library www ti com c2000appsw 3 C2000 Digital Power Supply Software Library www ti com dpslib 4 DSP Power Management Reference Designs www ti com dsppower TMS320x281x to TMS320x2833x or 2823x Migration Overview describes how to migrate from the 281x device design to 2833x or 2823x designs TMS320x280x to TMS320x2833x or 2823x Migration Overview describes how to migrate from a 280x device design to 2833x or 2823x designs C28x FPU Primer provides an overview of the floating point unit FPU in the TMS320F28335 TMS320F28334 and TMS320F28332 Digital Signal Controller DSC devices Getting Started With TMS320C28x Digital Signal Controllers is organized by development flow and functional areas to make your design effort as seamless as possible Tips on getting started with C28x DSP software and hardware development are provided to aid in your initial design and debug efforts Each section includes pointers to valuable information including technical documentation software and tools for use in each phase of design Running an Application from Internal Flash Memory on the TMS320F28xxx DSP covers the requirements needed to properly configure application software for execution from on chip flash memory Requirements for both DSP BIOS
100. ADC ADC Status Control and Result Register 2 Inter Integrated Circuit Module and Registers 3 2 18 General Purpose Input Output GPIO Multiplexer Most of the peripheral signals are multiplexed with general purpose input output GPIO signals This enables the user to use a pin as GPIO if the peripheral signal or function is not used On reset GPIO pins are configured as inputs The user can individually program each pin for GPIO mode or peripheral signal mode For specific inputs the user can also select the number of input qualification cycles This is to filter unwanted noise glitches The GPIO signals can also be used to bring the device out of specific low power modes 3 2 19 32 Bit CPU Timers 0 1 2 CPU Timers 0 1 and 2 are identical 32 bit timers with presettable periods and with 16 bit clock prescaling The timers have a 32 bit count down register which generates an interrupt when the counter reaches zero The counter is decremented at the CPU clock speed divided by the prescale value setting When the counter reaches zero it is automatically reloaded with a 32 bit period value CPU Timer 2 is reserved for the DSP BIOS Real Time OS and is connected to INT14 of the CPU If DSP BIOS is not being used CPU Timer 2 is available for general use CPU Timer 1 is for general use and can be connected to INT13 of the CPU CPU Timer 0 is also for general use and is connected to the PIE block 3 2 20 Control Peripherals The 280x devi
101. AG TRST 84 A6 JTAG test reset with internal pulldown TRST when driven high gives the scan system control of the operations of the device If this signal is not connected or driven low the device operates in its functional mode and the test reset signals are ignored NOTE Do not use pullup resistors on TRST it has an internal pull down device TRST is an active high test pin and must be maintained low at all times during normal device operation An external pulldown resistor is required on this pin The value of this resistor should be based on drive strength of the debugger pods applicable to the design A 2 2 kQ resistor generally offers adequate protection Since this is application specific it is recommended that each target board be validated for proper operation of the debugger and the application 75 10 JTAG test clock with internal pullup I 1 TMS 74 B10 JTAG test mode select TMS with internal pullup This serial control input is clocked into the TAP controller on the rising edge of TCK 1 TDI 73 C9 JTAG test data input TDI with internal pullup TDI is clocked into the selected register instruction or data a rising edge of 1 1 TDO 76 B9 JTAG scan out test data output TDO The contents of the selected register instruction or data are shifted out of TDO on the falling edge of TCK O Z 8 mA drive EMUO 80 A8
102. B Memory Map Copyright 2003 2009 Texas Instruments Incorporated Peripherals 71 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 at el SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com The CAN registers listed in Table 4 7 are used by the CPU to configure and control the CAN controller and the message objects eCAN control registers only support 32 bit read write operations Mailbox RAM can be accessed as 16 bits or 32 bits 32 bit accesses are aligned to an even boundary Table 4 7 CAN Register REGISTER NAME ADDRESS ADDRESS aes DESCRIPTION CANME 0x6000 0x6200 1 Mailbox enable CANMD 0x6002 0x6202 1 Mailbox direction CANTRS 0x6004 0x6204 1 Transmit request set CANTRR 0x6006 0x6206 1 Transmit request reset CANTA 0x6008 0x6208 1 Transmission acknowledge CANAA 0x600A 0x620A 1 Abort acknowledge CANRMP 0x600C 0x620C 1 Receive message pending CANRML 0 600 0 620 1 Receive message lost CANRFP 0x6010 0x6210 1 Remote frame pending CANGAM 0x6012 0x6212 1 Global acceptance mask CANMC 0x6014 0x6214 1 Master control CANBTC 0x6016 0x6216 1 Bit timing configuration CANES 0x6018 0x6218 1 Err
103. CENCLK signal high then the clocks to the registers will be enabled and the analog module will be enabled There will be a certain time delay ms range before the ADC is stable and can be used HALT This mode only affects the analog module It does not affect the registers In this mode the ADC module goes into low power mode This mode also will stop the clock to the CPU which will stop the HSPCLK therefore the ADC register logic will be turned off indirectly 64 Peripherals Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 5320 28015 TMS320F2809 TMS320F2808 TMS320F2806 Texas TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Figure 4 8 shows the ADC pin biasing for internal reference and Figure 4 9 shows the ADC pin biasing for external reference ADCINA 7 0 ADCINB 7 0 ADCLO ADCREFIN ADC 16 Channel Analog Inputs Analog input 0 3 V with respect to ADCLO Connect to analog ground Float or ground if internal reference is used 22 ADC External Current Bias Resistor ADCRESEXT ADC Ref Positive O ADCREFP did 2 2 uF A ADCREFP and ADCREFM should not ADC Reference Medium Output ADCREFM e be loaded by external circuit
104. CR 0x7077 1 XNMI control register XINT1CTR 0x7078 1 XINT1 counter register XINT2CTR 0x7079 1 XINT2 counter register Reserved 0x707A 0x707E 5 Reserved XNMICTR 0x707F 1 XNMI counter register Copyright 2003 2009 Texas Instruments Incorporated Functional Overview 45 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Each external interrupt can be enabled disabled or qualified using TEXAS INSTRUMENTS www ti com positive negative or both positive and negative edge For more information see the TMS320x280x 2801x 2804x DSP System Control and Interrupts Reference Guide literature number SPRU712 3 6 System Control This section describes the 280x oscillator PLL and clocking mechanisms the watchdog function and the low power modes Figure 3 9 shows the various clock and reset domains in the 280x devices that will be discussed 4 Reset SYSCLKOUT A gt Peripheral Reset CLKIN A 28x 4 CPU Peripheral CPU Registers Timers System Clock Enables Control Registers Peripheral ePWM 1 2 3 4 5 6 Registers eCAP 1 2 3 4 eQEP 1 2 eCAN A B Registers s
105. CSOCBO Timing 117 6 19 External Interrupt TIMING 117 6 20 SPI Master Mode External Timing Clock Phase 0 2 n I HH nennen 120 6 21 SPI Master Mode External Timing Clock Phase 1 1 74 2 122 6 22 SPI Slave Mode External Timing Clock Phase 0 4441 2 1 124 6 23 SPI Slave Mode External Timing Clock Phase 1 4 7 4 42 2 1 41 22 25 6 24 ADC Powei Up Control Bit TIMING u u u eeepc s ere ecu amu de ceu exar erras ME ERE 126 6 25 ADC Analog Input Impedance Model cete Au De snp CDM C NM ERN 127 6 26 Sequential Sampling Mode Single Channel Timing 4 1 1 mn 128 6 27 Simultaneous Sampling Mode nnn ren tunt m ren nr nion ntn nm nio nin id sa sia xime eta niga 12 6 List of Figures Copyright 2003 2009 Texas Instruments Incorporated TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 List of Tables 2 1 Hardw
106. Controller Mailbox RAM Memory Management 512 Bytes Unit eCAN Memory 512 Bytes CPU Interface Registers and Message 32 Message Mailbox Receive Control Unit Objects Control of 4 x 32 Bit Words Timer Management Unit eCAN Protocol Kernel Receive Buffer Transmit Buffer Control Buffer Status Buffer SN65HVD23x 3 3 V CAN Transceiver CAN Bus Figure 4 10 eCAN Block Diagram and Interface Circuit Table 4 6 3 3 V eCAN Transceivers PART NUMBER VOLTAGE BE CONTROL VREF OTHER TA SN65HVD230 3 3 V Standby Adjustable Yes _ 40 to 85 C SN65HVD230Q 3 3 V Standby Adjustable Yes 40 C to 125 C SN65HVD231 3 3 V Sleep Adjustable Yes 40 to 85 C SN65HVD231Q 3 3 V Adjustable Yes 40 C to 125 C SN65HVD232 3 3 V None None None 40 C to 85 C SN65HVD232Q 3 3 V None None None 40 to 125 C SN65HVD233 3 3 V Standby Adjustable None Diagnostic 40 C to 125 C Loopback SN65HVD234 3 3 V Standby amp Sleep Adjustable None 40 to 125 C SN65HVD235 3 3 V Standby Adjustable None Autobaud 40 to 125 C Loopback Copyright 2003 2009 Texas Instruments Incorporated Peripherals 69 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS3
107. DCREFM 36 is of 2 2 uF to analog ground CPU AND I O POWER PINS Vppa2 15 F2 ADC Analog Power Pin 3 3 V Vssa2 14 F1 ADC Analog Ground Pin 26 42 ADC Analog I O Power Pin 3 3 V Vssalo 25 K1 ADC Analog I O Ground Pin Vpp1A18 12 E4 ADC Analog Power Pin 1 8 V Vss1AGND 13 E5 ADC Analog Ground Pin Vpp2A18 40 J6 ADC Analog Power Pin 1 8 V Vss2AGND 39 K6 ADC Analog Ground Pin 20 Introduction Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 5 INSTRUMENTS www ti com TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Signal Descriptions continued PIN NO NAME pz GGM DESCRIPTION PIN ZGM BALL Vpp 10 2 Vpp 42 G6 59 10 CPU and Logic Digital Power Pins 1 8 V 68 07 Vpp 85 B6 Vpp 93 D4 Vppio 46 H7 an Digital Power Pin 3 3 V Vppio 65 E9 Vppio 82 A7 Vss 2 B1 Vss 11 E3 Vss 41 H6 Vss 49 K9 Vss 55 H10 Vss 62 F7 Digital Ground Pins Vss 69 D10 Vss 77 A9 Vss 87 D6 Vss 89 A5 Vss 94 A4 GPIOA AND PERIPHERAL SIGNALS 9 GPIOO General purpose input output 0 I O Z
108. Device Clock Table 2 4 41 4 41 40 semen sens 104 6 7 Clock Requirements and Characteristics 4 4 1 4 44 105 6 8 EC LII 106 6 8 1 Power Management and Supervisory Circuit Solutions 2 106 6 9 General Purpose Input Output GPIO 1 44 2 2224 412 lt nne n nnn 109 6 9 1 GPIO Ing MIC I 109 6 9 2 GPIO TIMING RM IRR NEU 110 6 9 3 Sampling Window Width for Input Signals 2 2 4 2 211 6 9 4 Low Power Mode Wakeup Timing 1 lt 112 6 10 Enhanced Control Peripherals 2 414 22 2 244 2421 0 66 115 6 10 1 Enhanced Pulse Width Modulator ePWM Timing 115 6 10 2 Trip Zone Input Timing 2 2 44 4 4411 nn 145 6 10 3 External Interrupt Timing 117 6 10 4 2 Electrical
109. E ACCESSED THROUGH OTHER MEANS MOREOVER EXCEPT AS SET FORTH ABOVE MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE EVENT SHALL BE LIABLE FOR ANY CONSEQUENTIAL SPECIAL INDIRECT INCIDENTAL OR PUNITIVE DAMAGES HOWEVER CAUSED ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE WHETHER OR NOT HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES EXCLUDED DAMAGES INCLUDE BUT ARE NOT LIMITED TO LOSS OF DATA LOSS OF GOODWILL LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS Copyright 2003 2009 Texas Instruments Incorporated Functional Overview 37 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 3 2 11 Peripheral Interrupt Expansion PIE Block The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs The PIE block can support up to 96 peripheral interrupts On the 280x 43 of the possible 96 interrupts are used by peripherals The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU inter
110. Emulator pin 0 When TRST is driven high this pin is used as an interrupt to or from the emulator System and is defined as input output through the JTAG scan This pin is also used to put the device into boundary scan mode With the EMUO pin at a logic high state and the EMU1 pin at a logic low state a rising edge on the TRST pin would latch the device into boundary scan mode 10 2 8 mA drive 1 NOTE An external pullup resistor is recommended on this pin The value of this resistor should be based on the drive strength of the debugger pods applicable to the design A 2 2 kO to 4 7 kO resistor is generally adequate Since this is application specific it is recommended that each target board be validated for proper operation of the debugger and the application EMU1 81 B7 Emulator pin 1 When TRST is driven high this pin is used as an interrupt to or from the emulator system and is defined as input output through the JTAG scan This pin is also used to put the device into boundary scan mode With the EMUO pin at a logic high state and the EMU1 pin ata logic low state a rising edge on the TRST pin would latch the device into boundary scan mode VO Z 8 mA drive 1 NOTE An external pullup resistor is recommended on this pin The value of this resistor should be based on the drive strength of the debugger pods applicable to the design A 2 2 kO to 4 7 resistor is generally adequate Since this is application specific it is recomme
111. F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 4 Peripherals The integrated peripherals of the 280x are described in the following subsections Three 32 bit CPU Timers Up to six enhanced PWM modules ePWM1 ePWM2 ePWM3 ePWMA4 ePWM5 ePWM6 Up to four enhanced capture modules eCAP1 2 eCAP3 eCAP4 Up to two enhanced QEP modules eQEP1 eQEP2 Enhanced analog to digital converter ADC module Upto two enhanced controller area network eCAN modules eCAN A eCAN B Upto two serial communications interface modules SCI A SCI B Upto four serial peripheral interface SPI modules SPI A SPI B SPI C SPI D Inter integrated circuit module 12C Digital and shared pin functions 41 32 Bit CPU Timers 0 1 2 There are three 32 bit CPU timers on the 280x devices CPU TIMERO 2 CPU Timer 0 and CPU Timer 1 can be used in user applications Timer 2 is reserved for DSP BIOS These timers are different from the timers that are present in the ePWM modules NOTE If the application is not using DSP BIOS then CPU Timer 2 can be used in the application Timer Reload nd irs 32 Bit Timer Period PRDH PRD SYSCLKOUT 16 Bit TCR 4 32 Bit Counter Timer Start Status Borrow TIMH TIM Borrow 4 A e Figure 4 1 CPU Timers Copyright 2003 2009 Texas Instruments Incorporated Peripherals 53 Submit Documentation Feedback Pro
112. Frequency 159 60 MHz ADC clock te aDccLk Cycle time 133 33 ns Frequency 7 5 MHz 1 This also applies to the X1 pin if a 1 8 V oscillator is used 2 Lower LSPCLK and HSPCLK will reduce device power consumption 3 This is the default reset value if SYSCLKOUT 60 MHz 104 Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 5320 2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 TMS320F28015 l TEXAS INSTRUMENTS www ti com 6 7 Clock Requirements and Characteristics TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Table 6 8 Input Clock Frequency PARAMETER MIN TYP MAX UNIT Resonator X1 X2 20 35 Crystal X1 X2 20 35 fx Input clock frequency MHz External oscillator clock 100 MHz device 100 source XCLKIN or X1 pin 60 MHz device 60 fi Limp mode SYSCLKOUT frequency range with 2 enabled 1 5 MHz Table 6 9 Timing Requirements PLL Enabled NO MIN MAX UNIT C8 Cycle time XCLKIN 33 3 2001 ns C9 til Fall time XCLKIN 6 ns C10 tyr Rise time XCLKIN 6 ns C11
113. GPIO14 TZ3 SCITXDB SPICLKB GPIO15 TZ4 SCIRXDB SPISTEB ADCINA1 ADCINAO ADCLO Vssalo TEXAS INSTRUMENTS www ti com GPIO16 SPISIMOA CANTXB TZ5 Vss GPIO3 EPWM2B SPISOMID GPIOO EPWM1A Vppio GPIO2 EPWM2A GPIO1 EPWM1B SPISIMOD GPIO34 Vpp Vss 2 18 Vss2AGND ADCRESEXT ADCREFP ADCREFM ADCREFIN ADCINB7 ADCINB6 ADCINB5 ADCINB4 ADCINB3 ADCINB2 ADCINB1 ADCINBO Figure 2 1 TMS320F2809 TMS320F2808 100 PZ LQFP Top View Introduction Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 TMS320F28015 5 INSTRUMENTS www ti com TDO Vss XRS GPIO27 ECAP4 EQEP2S SPISTEB EMU0 EMU1 Vppio GPIO24 ECAP1 EQEP2A SPISIMOB TRST XCLKIN GPIO25 ECAP2 EQEP2B SPISOMIB GPIO28 SCIRXDA TZ5 Vpp Vss GPIO13 TZ2 SPISOMIB VppavrFL TEST1 TEST2 GPIO26 ECAP3 EQEP2I SPICLKB GPIO32 SDAA EPWMSYNCI ADCSOCAO TCK TMS TDI GP1023 EQEP1I SPISTEC SCIRXDB GPIO22 EQEP1S SPICLKC SCITXDB GP1IO11 EPWM6B SCIRXDB ECAP4 GPIO21 EQEP1B SPISOMIC XCLKOUT Vpbio GPIO10 EPWM6A ADCSOCBO GPIO20 EQEP1A SPISIMOC Vss 5320 2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 G
114. IE Peripheral Interrupts TEXAS INSTRUMENTS INTM From Peripherals or External Interrupts www ti com CPU PIE INTERRUPTS INTERRUPTS INTx 8 INTx 7 INTx 6 INTx 5 4 INTx 3 INTx 2 INTx 1 MP FUMER 0 pod XINT2 Reserved eo EOM INT2 Reserved Reserved EPWM6_TZINT EPWM5_TZINT EPWM4 TZINT EPWMS TZINT EPWM2 TZINT EPWM1 TZINT ePWM6 ePWMB ePWM4 ePWM3 ePWM2 ePWM1 INT3 Reserved Reserved 6 INT EPWM5_INT EPWM4_INT EPWM3_INT EPWM2_INT EPWM1_INT ePWM6 ePWMB ePWM4 ePWM3 ePWM2 ePWM1 INT4 Reserved Reserved Reserved Reserved pos Fd pu gu pe ARES INT5 Reserved Reserved Reserved Reserved Reserved Reserved gd po INT6 SPITXINTD SPIRXINTD SPITXINTC SPIRXINTC SPITXINTB SPIRXINTB SPITXINTA SPIRXINTA SPI D SPI D SPI C SPI C SPI B SPI B SPI A SPI A INT7 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT8 Reserved Reserved Reserved Reserved Reserved Reserved py ps INT9 ECAN1 INTB ECANO INTB ECAN1 INTA ECANO INTA SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA CAN B CAN B CAN A CAN A SCI B SCI B SCI A SCI A INT10 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT11 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved INT12 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Out of the 96 possible inte
115. IVE BGA ZGM 100 184 Green RoHS SNAGCU Level 3 260C 168 HR MICROSTAR amp no Sb Br TMS320F2809GGMA ACTIVE BGA GGM 100 184 TBD SNPB Level 3 220C 168 HR MICROSTAR TMS320F2809GGMS ACTIVE BGA GGM 100 184 TBD SNPB Level 3 220C 168 HR MICROSTAR PACKAGE OPTION ADDENDUM TEXAS INSTRUMENTS www ti com 5 Nov 2010 Orderable Device Status Package Type Package Pins Package Qty Eco Plan 2 Lead MSL Peak Temp Samples Drawing Ball Finish Requires Login TMS320F2809PZA ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br 5320 2809 70 LQFP PZ 100 1 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F2809PZS ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F2809ZGMA ACTIVE BGA ZGM 100 1 Green RoHS SNAGCU Level 3 260C 168 HR MICROSTAR amp no Sb Br TMS320F2809ZGMS ACTIVE BGA ZGM 100 184 Green RoHS SNAGCU Level 3 260C 168 HR MICROSTAR amp no Sb Br 0 The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLE
116. LOCK POLARITY bit SPICCR 6 12 SPICLK clock polarity 0 SPICLK 0N 4M N clock polarity 1 15 4 18 SPISOM XXX _SPISOMIDatals Valid 19 gt I4 20 SPISIMO Data SPISIMO Must Be Vai RD A slave mode the SPISTE signal should be asserted low at least 0 5 5 minimum before the valid SPI clock edge and remain low for at least 0 5te spc after the receiving edge SPICLK of the last data bit Figure 6 22 SPI Slave Mode External Timing Clock Phase 0 Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 123 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 TEXAS INSTRUMENTS www ti com Table 6 37 SPI Slave Mode External Timing Clock Phase 1 2 9 4 NO MIN MAX UNIT 12 tc sPc s Cycle time SPICLK 8tc L ns 43 tw SPCH S Pulse duration SPICLK high clock polarity 0 O 5tcspo s 10 O 5tcsPc s tw SPCL S Pulse duration SPICLK low clock polarity 1 O 5tcspo s 10 0 5tc sPc s
117. MIN MAX UNIT lw ADCSOCAL Pulse duration ADCSOCAO low 32lc uco cycles gt tw ADCSOCAL ADCSOCAO or N ADCSOCBO Figure 6 18 ADCSOCAO or ADCSOCBO Timing 6 10 3 External Interrupt Timing lw INT XINT1 XINT2 N gt ta INT Address us Interrupt Vector y internal KKK KKK Interrupt Vector Figure 6 19 External Interrupt Timing Table 6 31 External Interrupt Timing Requirements TEST CONDITIONS MIN MAX UNIT twv 2 Pulse duration INT input low high Synchronous 115 cycles With qualifier 1tcsco twilasw 1 For an explanation of the input qualifier parameters see Table 6 15 2 This timing is applicable to any GPIO pin configured for ADCSOC functionality Table 6 32 External Interrupt Switching Characteristics PARAMETER MIN MAX UNIT laa Delay time INT low high to interrupt vector fetch twiasw 121 cycles 1 For an explanation of the input qualifier parameters see Table 6 15 Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 117 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F280
118. MS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 Norn MENS SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com Table 4 2 ePWM Control and Status Registers NAME ePWM1 ePWM2 ePWM3 ePWM4 ePWMS5 ePWM6 pared DESCRIPTION TBCTL 0 6800 0x6840 0x6880 0 68 0 0 6900 0x6940 1 0 Time Base Control Register TBSTS 0x6801 0x6841 0x6881 0x68C1 0x6901 0x6941 1 0 Time Base Status Register TBPHSHR 0x6802 0x6842 0x6882 0x68C2 N A N A 1 0 Time Base Phase HRPWM Register TBPHS 0x6803 0x6843 0x6883 0x68C3 0x6903 0x6943 1 0 Time Base Phase Register TBCTR 0x6804 0x6844 0x6884 0x68C4 0x6904 0x6944 1 0 Time Base Counter Register TBPRD 0x6805 0x6845 0x6885 0x68C5 0x6905 0x6945 1 1 Time Base Period Register Set CMPCTL 0x6807 0x6847 0x6887 0x68C7 0x6907 0x6947 1 0 Counter Compare Control Register CMPAHR 0x6808 0x6848 0x6888 0x68C8 N A N A 1 1 Time Base Compare A HRPWM Register CMPA 0x6809 0x6849 0x6889 0x68C9 0x6909 0x6949 1 1 Counter Compare A Register Set CMPB 0x680A 0x684A 0x688A 0x68CA 0x690A 0x694A 1 1 Counter Compare B Register Set AQCTLA 0x680B 0x684B 0x688B 0x68CB 0 690 0 694 1 0 Action Qualifier Control Register For Output A AQCTLB 0x680C 0x684C 0x688C 0x68CC 0x690C 0x694C 1 0 Action
119. NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F2801PZQ ACTIVE LQFP PZ 100 1 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F2801PZS ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F2801PZS 60 ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F2801ZGMA ACTIVE BGA ZGM 100 184 Green RoHS SNAGCU Level 3 260C 168 HR MICROSTAR amp no Sb Br TMS320F2801ZGMS ACTIVE BGA ZGM 100 184 Green RoHS SNAGCU Level 3 260C 168 HR MICROSTAR amp no Sb Br TMS320F2802GGMA ACTIVE BGA GGM 100 184 TBD SNPB Level 3 220C 168 HR MICROSTAR TMS320F2802GGMS ACTIVE BGA GGM 100 184 TBD SNPB Level 3 220C 168 HR MICROSTAR TMS320F2802PZA ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F2802PZA 60 ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F2802PZQ ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F2802PZS ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F2802PZS 60 ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br Addendum Page 2 5 INSTRUMENTS PACKAGE OPTION ADDENDUM Addendum Page 3 www ti com 5 Nov 2010 Orderable Device Status Package Type Package Pins Package Qty Eco Plan 2 Lead MSL Peak Temp Samples Drawin
120. OO to 31 GPASET Ox6FC2 2 GPIO Data Set Register GPIOO to 31 GPACLEAR Ox6FC4 2 GPIO Data Clear Register GPIOO to 31 GPATOGGLE Ox6FC6 2 GPIO Data Toggle Register GPIOO to 31 GPBDAT Ox6FC8 2 GPIO Data Register GPIO32 to 35 GPBSET Ox6FCA 2 GPIO Data Set Register GPIO32 to 35 GPBCLEAR Ox6FCC 2 GPIO Data Clear Register GPIO32 to 35 GPBTOGGLE Ox6FCE 2 GPIO Data Toggle Register GPIO32 to 35 Reserved um 16 Reserved GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS EALLOW PROTECTED GPIOXINT1SEL Ox6FEO 1 XINT1 GPIO Input Select Register GPIOO to 31 GPIOXINT2SEL Ox6FE1 1 XINT2 GPIO Input Select Register GPIOO to 31 GPIOXNMISEL Ox6FE2 1 XNMI GPIO Input Select Register GPIOO to 31 Reserved petis 5 Reserved GPIOLPMSEL Ox6FE8 2 LPM GPIO Select Register GPIOO to 31 Reserved a 22 Reserved Copyright 2003 2009 Texas Instruments Incorporated Peripherals 83 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Table 4 16 F2808 GPIO MUX Table 5 INSTRUMENTS www ti com DEFAULT AT RESET GPAMUX1 2
121. PIO9 EPWMSB SCITXDB ECAP3 GPIO8 EPWM5A ADCSOCAO GPIO6 EPWM4A EPWMSYNCI EPWMSYNCO Vss Vpp GPIO5 EPWM3B SPICLKD ECAP1 GPIO17 SPISOMIA TZ6 GPIO7 EPWM4B SPISTED ECAP2 GPIO4 EPWM3A GPIO19 SPISTEA SCIRXDB GPIO18 SPICLKA SCITXDB GPIO16 SPISIMOA TZ5 Vss GPIO3 EPWM2B SPISOMID GPIOO EPWM1A Vppio GPIO2 EPWM2A GPIO1 EPWM1B SPISIMOD GPIO34 Vpp Vss VpD2A18 Vss2AGND ADCRESEXT ADCREFP ADCREFM ADCREFIN ADCINB7 ADCINB6 ADCINB5 ADCINB4 ADCINB3 ADCINB2 ADCINB1 ADCINBO GPIO12 TZ1 SPISIMOB Vpbio GPIO29 SCITXDA TZ6 GPIO33 SCLA EPWMSYNCO ADCSOCBO GPIO30 CANRXA GPIO31 CANTXA GPIO14 TZ3 SCITXDB SPICLKB GPIO15 TZ4 SCIRXDB SPISTEB Vpp Vss Vpp1A18 Vss1AGND NA7 NA6 5 4 2 1 NAO CLO Vssa2 Vppa2 ADC ADC ADC Figure 2 2 TMS320F2806 100 PZ LQFP View Copyright 2003 2009 Texas Instruments Incorporated Introduction 15 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 i al SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com o 8 5 9 lt lt lt ms 9 Gi
122. Pen MENG TMS320C2801 TMS320F28016 TMS320F28015 3 2 10 Security The 280x devices support high levels of security to protect the user firmware from being reverse engineered The security features a 128 bit password hardcoded for 16 wait states which the user programs into the flash One code security module CSM is used to protect the flash OTP and the LO L1 SARAM blocks The security feature prevents unauthorized users from examining the memory contents via the JTAG port executing code from external memory or trying to boot load some undesirable software that would export the secure memory contents To enable access to the secure blocks the user must write the correct 128 bit KEY value which matches the value stored in the password locations within the Flash NOTE The 128 bit password at 0 3 7FF8 Ox3F 7FFF must not be programmed to zeros Doing so would permanently lock the device disclaimer Code Security Module Disclaimer THE CODE SECURITY MODULE CSM INCLUDED ON THIS DEVICE WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY EITHER ROM OR FLASH AND 15 WARRANTED BY TEXAS INSTRUMENTS ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS TO CONFORM TO TI S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE DOES NOT HOWEVER WARRANT OR REPRESENT THAT THE CSM CANNOT COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT B
123. Qualifier Control Register For Output B AQSFRC 0x680D 0x684D 0x688D 0x68CD 0x690D 0x694D 1 0 Action Qualifier Software Force Register AQCSFRC 0 680 0 684 0 688 0 68 0 690 0 694 1 1 Action Qualifier Continuous S W Force Register Set DBCTL 0x680F 0x684F 0x688F 0 68 0 690 0 694 1 1 Dead Band Generator Control Register DBRED 0x6810 0x6850 0x6890 0x68DO 0x6910 0x6950 1 0 Dead Band Generator Rising Edge Delay Count Register DBFED 0x6811 0x6851 0x6891 0x68D1 0x691 1 0x6951 1 0 Dead Band Generator Falling Edge Delay Count Register TZSEL 0x6812 0x6852 0x6892 0x68D2 0x6912 0x6952 1 0 Trip Zone Select Register TZCTL 0x6814 0x6854 0x6894 0x68D4 0x6914 0x6954 1 0 Trip Zone Control Register TZEINT 0x6815 0x6855 0x6895 0x68D5 0x6915 0x6955 1 0 Trip Zone Enable Interrupt Register TZFLG 0x6816 0x6856 0x6896 0x68D6 0x6916 0x6956 1 0 Trip Zone Flag Register TZCLR 0x6817 0x6857 0x6897 0x68D7 0x6917 0x6957 1 0 Trip Zone Clear Register TZFRC 0x6818 0x6858 0x6898 0x68D8 0x6918 0x6958 1 0 Trip Zone Force Register ETSEL 0x6819 0x6859 0x6899 0x68D9 0x6919 0x6959 1 0 Event Trigger Selection Register ETPS 0x681A 0x685A 0x689A 0x68DA 0x691A 0x695A 1 0 Event Trigger Prescale Register ETFLG 0x681B 0x685B 0x689B 0x68DB 0x691B 0x695B 1 0 Event Trigger Flag Register ETCLR 0x681C 0x685C 0x689C 0x68DC 0x691C 0x695C 1 0 Event Trigger Clear Register ETFRC 0x681D 0x685D 0x689D 0x68DD 0x691D 0x695D 1 0 Event Trigger Force Register PCCTL 0 681 0 685
124. Register SPITXBUF 0x7788 1 SPI D Serial Output Buffer Register SPIDAT 0x7789 1 SPI D Serial Data Register SPIFFTX 0x778A 1 SPI D FIFO Transmit Register SPIFFRX 0x778B 1 SPI D FIFO Receive Register SPIFFCT 0x778C 1 SPI D FIFO Control Register SPIPRI 0x778F 1 SPI D Priority Control Register 1 Registers in this table are mapped to Peripheral Frame 2 This space only allows 16 bit accesses 32 bit accesses produce undefined results 78 Peripherals Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 Texas TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Figure 4 14 is a block diagram of the SPI in slave mode SPIFFENA Receiver Overrun Overrun Flag INT ENA RX FIFO registers SPISTS 7 9 SPICTL 4 SPIRXBUF RX FIFO Interrupt SPIINT SPIRXINT RX FIFO 15 endo zum EN SPIFFRX 15 TX Interrupt Logic TXFIFO 15 NE ss SPITXINT SPITXBUF Buffer Register SPIDAT 15 0 Talk SPICTL 1 State Control Master Slave 3 2 1 Jo Clock Clock SPI Bit Rate Polarity Phase SPIBRR 6 0 spicer 6 SPICTL LSPCL
125. Reserved FLASH 64K x 16 Secure Zone 128 bit Password LO SARAM 0 4K x 16 Secure Zone Dual Mapped L1 SARAM 0 wait 4K x 16 Secure Zone Dual Mapped HO SARAM 0 wait 8K x 16 Dual Mapped Reserved Boot ROM 4K x 16 Vectors 32 x 32 enabled if VMAP 1 ENPIE 0 Peripheral Frame 0 Peripheral Frame 1 and Peripheral Frame 2 memory maps are restricted to data memory only User program cannot access these memory maps in program space Protected means the order of Write followed by Read operations is preserved rather than the pipeline order Certain memory ranges are EALLOW protected against spurious writes after configuration Figure 3 3 F2808 Memory Map Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 TMS320F28015 Functional Overview 27 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 NOEROMENDS SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com Block Start A adress Data Space Prog Space 0x00 0000 0 Vector RAM 32 x 32 Enabled if 0 0x00 0040 0 5 1K x 16 0x00 0400 M1 SARAM 1K x 16 0x00 0800 Peripheral Frame 0 8 re PIE
126. S320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TEXAS TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 GPIO6 EPWM4A EPWMSYNCI EPWMSYNCO N T 4 lt g o 8 8 6 ag Same o o te o o osos a o 28 a Z a gt 5 g 8 Roo o3 SEES DO pa 200 55 2 a aa 00 0 0820 PERG GOSS ELSEELESGLESEEFEGES PNE TDO GPIO16 SPISIMOA TZ5 Vss Vss XRS GPIO3 EPWM2B GPIO27 GPIOO0 EPWM1A EMUO EMU1 GPIO2 EPWM2A GPIO1 EPWM1B GPIO24 ECAP1 GPIO34 TRST Vpp Vpp Vss x2 Vpp2A18 Vss Vss2AGND xi ADCRESEXT Vss ADCREFP XCLKIN ADCREFM GPIO25 ECAP2 ADCREFIN GPIO28 SCIRXDA TZ5 ADCINB7 Vpp ADCINB6 Vss ADCINBS GPIO13 TZ2 ADCINB4 VppavrL 9 ADCINB3 TESTI ADCINB2 TEST2 ADCINB1 GPIO26 ADCINBO GPIO32 SDAA EPWMSYNCI ADSOCAO VpbAIO ES lt Mit a o q P Rout ghBs shh 2332322222233 3 a 5 zzzo gt gt 450 gt 0 22 2220258 lt gt 8 x 60929 2 lt lt lt lt lt lt lt lt G 95060 25898 o a GP1033 SCLA EPWMSYNCO ADCSOCBO pin 7 and CANRXA 6 pins not applicable for the TMS320F28015 Figure 2 4 TMS320F2801x 100 Pin PZ LQFP Top View Copyright 2003 2009 Texas Instruments Incorporated Intro
127. Serial Port Peripherals The 280x devices support the following serial communication peripherals eCAN SPI SCI 3 3 Register Map This is the enhanced version of the CAN peripheral It supports 32 mailboxes time stamping of messages and is CAN 2 0B compliant The SPI is a high speed synchronous serial port that allows a serial bit stream of programmed length one to sixteen bits to be shifted into and out of the device at a programmable bit transfer rate Normally the SPI is used for communications between the DSP controller and external peripherals or another processor Typical applications include external I O or peripheral expansion through devices such as shift registers display drivers and ADCs Multi device communications are supported by the master slave operation of the SPI On the 280x the SPI contains a 16 level receive and transmit FIFO for reducing interrupt servicing overhead The serial communications interface is a two wire asynchronous serial port commonly known as UART On the 280x the SCI contains a 16 level receive and transmit FIFO for reducing interrupt servicing overhead The inter integrated circuit 2 module provides an interface between a DSP and other devices compliant with Philips Semiconductors Inter IC bus I2C bus specification version 2 1 and connected by way of an I2C bus External components attached to this 2 wire serial bus can transmit receive up to 8 bit data to from th
128. TE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free RoHS Pb Free RoHS Exempt or Green RoHS amp no Sb Br please check http www ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 196 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Pb Free RoHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS amp no Sb Br TI defines Green to mean Pb Free RoHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 196 by weight in homogeneous material 9 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s
129. TMS320F2801 5320 2802 POSUERE TMS320C2801 TMS320F28016 TMS320F28015 Figure 6 10 shows an example for the effect of writing into PLLCR register In the first phase PLLCR 0x0004 SYSCLKOUT OSCCLK x 2 The PLLCR is then written with 0x0008 Right after the PLLCR register is written the PLL lock up phase begins During this phase SYSCLKOUT OSCCLK 2 After the PLL lock up is complete which takes 131072 OSCCLK cycles SYSCLKOUT reflects the new operating frequency OSCCLK x 4 OSCCLK w Write to PLLCR SYSCLKOUT L LJ OSCCLK 2 OSCCLK 2 OSCCLK 4 Current CPU CPU Frequency While PLL is Stabilizing Changed CPU Frequency Frequency With the Desired Frequency This Period PLL Lock up Time tp is 131072 OSCCLK Cycles Long Figure 6 10 Example of Effect of Writing Into PLLCR Register 6 9 General Purpose Input Output GPIO 6 9 11 GPIO Output Timing Table 6 14 General Purpose Output Switching Characteristics PARAMETER MIN MAX UNIT Rise time GPIO switching low to high All 8 ns Fall time GPIO switching high to low All GPIOs 8 ns Toggling frequency GPO pins 25 MHz GPIO 4 lt Figure 6 11 General Purpose Output Timing Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 109 Submit Documentation Feedbac
130. TMS320F28015 77 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 TEXAS INSTRUMENTS www ti com Table 4 12 SPI C Registers NAME ADDRESS SIZE x16 DESCRIPTION SPICCR 0x7760 1 SPI C Configuration Control Register SPICTL 0x7761 1 SPI C Operation Control Register SPISTS 0x7762 1 SPI C Status Register SPIBRR 0x7764 1 SPI C Baud Rate Register SPIRXEMU 0x7766 1 SPI C Receive Emulation Buffer Register SPIRXBUF 0x7767 1 SPI C Serial Input Buffer Register SPITXBUF 0x7768 1 SPI C Serial Output Buffer Register SPIDAT 0x7769 1 SPI C Serial Data Register SPIFFTX 0x776A 1 SPI C FIFO Transmit Register SPIFFRX 0x776B 1 SPI C FIFO Receive Register SPIFFCT 0x776C 1 SPI C FIFO Control Register SPIPRI Ox776F 1 SPI C Priority Control Register 1 UN in this table are mapped to Peripheral Frame 2 This space only allows 16 bit accesses 32 bit accesses produce undefined results Table 4 13 SPI D Registers NAME ADDRESS SIZE x16 DESCRIPTION SPICCR 0x7780 1 SPI D Configuration Control Register SPICTL 0x7781 1 SPI D Operation Control Register SPISTS 0x7782 1 SPI D Status Register SPIBRR 0x7784 1 SPI D Baud Rate Register SPIRXEMU 0x7786 1 SPI D Receive Emulation Buffer Register SPIRXBUF 0x7787 1 SPI D Serial Input Buffer
131. Vector RAM m E 256 x 16 Reserved _ Enabled if ENPIE 1 0 00 0 00 S 8 Reserved 0 00 6000 gt 2 Peripheral Frame 1 protected aa 0x00 7000 Resetved 2 protected 9x00 8000 10 SARAM 0 wait 4K x 16 Secure Zone Dual Mapped 0x00 9000 L1 SARAM 0 wait 4K x 16 Secure Zone Dual Mapped 0x00 A000 Reserved 0x3D 7800 OTP 1K x 16 Secure Zone 0x3D 7 00 Reserved 0x3F 0000 FLASH 32K x 16 Secure Zone 8 7FF8 128 bit Password ro 8000 LO SARAM 0 wait 4K 16 Secure Zone Dual Mapped D S 0x3F 9000 L1 SARAM 0 wait Se 4K x 16 Secure Zone Dual Mapped Ps gs Ox3F A000 X Reserved lt 2s Ox3F F000 5 Boot ROM 4K x 16 Ox3F FFCO Vectors 32 x 32 enabled if 1 ENPIE 0 Memory blocks not to scale B Peripheral Frame 0 Peripheral Frame 1 and Peripheral Frame 2 memory maps are restricted to data memory only User program cannot access these memory maps in program space Protected means the order of Write followed by Read operations is preserved rather than the pipeline order D Certain memory ranges are EALLOW protected against spurious writes after configuration Figure 3 4 F2806 Memory Map o 28 Functional Overview Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320
132. Z Results TEXAS INSTRUMENTS www ti com AIR FLOW PARAMETER 0 lfm 150 250 lfm 500 Ifm Oyal C W High k PCB 44 02 28 34 36 28 33 68 YW C W 0 2 0 56 0 7 0 95 7 06 28 76 136 Mechanical Data Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 TMS320F28015 OPTION ADDENDUM TEXAS NSTRUMENTS www ti com 5 Nov 2010 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Qty Eco Plan 2 Lead MSL Peak Temp Samples Drawing Ball Finish Requires Login TMS320C2801GGMA ACTIVE BGA GGM 100 TBD Call TI Call TI MICROSTAR TMS320C2801GGMS ACTIVE BGA GGM 100 TBD Call TI Call TI MICROSTAR TMS320C2801PZA ACTIVE LQFP PZ 100 TBD Call TI Call TI TMS320C2801PZQ ACTIVE LQFP PZ 100 TBD Call TI Call TI TMS320C2801PZS ACTIVE LQFP PZ 100 TBD Call TI Call TMS320C2801ZGMA ACTIVE BGA ZGM 100 TBD Call TI Call TI MICROSTAR TMS320C2801Z2GMS ACTIVE BGA ZGM 100 TBD Call TI Call TI MICROSTAR TMS320C2802GGMA ACTIVE BGA GGM 100 TBD Call TI Call TI MICROSTAR TMS320C2802GGMS ACTIVE BGA GGM 100 TBD Call TI Call TI MICROSTAR TMS320C2802PZA ACTIVE LQFP PZ 100 TBD Call TI Call TI TMS320C2802PZQ ACTIVE LQFP PZ 100 TBD Call TI Call
133. ach has its own separate enable and interrupt bits Both can be operated independently or simultaneously in the full duplex mode To ensure data integrity the SCI checks received data for break detection parity overrun and framing errors The bit rate is programmable to over 65000 different speeds through a 16 bit baud select register Features of each SCI module include Two external pins SCITXD SCI transmit output pin SCIRXD SCI receive input pin NOTE Both pins can be used as GPIO if not used for SCI Baud rate programmable to 64K different rates LSPCLK Baud rate BRR 1 8 when BRR 0 Baud rate ESTELK when BRR 0 Data word format One start bit Data word length programmable from one to eight bits Optional even odd no parity bit One or two stop bits Four error detection flags parity overrun framing and break detection Two wake up multiprocessor modes idle line and address bit e Half or full duplex operation Double buffered receive and transmit functions Transmitter and receiver operations can be accomplished through interrupt driven or polled algorithms with status flags Transmitter TXRDY flag transmitter buffer register is ready to receive another character and TX EMPTY flag transmitter shift register is empty Receiver RXRDY flag receiver buffer register is ready to receive another character BRKDT flag break condition occurred and RX ERROR flag monitorin
134. al is sampled with respect to SYSCLKOUT Sampling frequency SYSCLKOUT 2 QUALPRD if QUALPRD 0 Sampling frequency SYSCLKOUT if QUALPRD 0 Sampling period SYSCLKOUT cycle x 2 x QUALPRD if QUALPRD 0 In the above equations SYSCLKOUT cycle indicates the time period of SYSCLKOUT Sampling period SYSCLKOUT cycle if QUALPRD 0 In a given sampling window either 3 or 6 samples of the input signal are taken to determine the validity of the signal This is determined by the value written to GPxQSELn register Case 1 Qualification using 3 samples Sampling window width SYSCLKOUT cycle x 2 x QUALPRD x 2 if QUALPRD 0 Sampling window width SYSCLKOUT cycle x 2 if QUALPRD 0 Case 2 Qualification using 6 samples Sampling window width SYSCLKOUT cycle x 2 x QUALPRD x 5 if QUALPRD 0 Sampling window width SYSCLKOUT cycle x 5 if QUALPRD 0 NU e GPIOxn X X h gt Figure 6 13 General Purpose Input Timing NOTE The pulse width requirement for general purpose input is applicable for the XINT2_ADCSOC signal as well Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 111 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 5320 2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C28
135. and non DSP BIOS projects are presented Example code projects are included Programming TMS320x28xx and 28xxx Peripherals in C C explores a hardware abstraction layer implementation to make C C coding easier on 28x DSPs This method is compared to traditional define macros and topics of code efficiency and special case registers are also addressed Using PWM Output as a Digital to Analog Converter on a TMS320F280x Digital Signal Controller presents a method for utilizing the on chip pulse width modulated PWM signal generators on the TMS320F280x family of digital signal controllers as a digital to analog converter DAC TMS320F280x Digital Signal Controller USB Connectivity Using the TUSB3410 USB to UART Bridge Chip presents hardware connections as well as software preparation and operation of the development system using a simple communication echo program Using the Enhanced Quadrature Encoder Pulse eQEP Module in TMS320x280x 28xxx as a Dedicated Capture provides a guide for the use of the eQEP module as a dedicated capture unit and is applicable to the TMS320x280x 28xxx family of processors Using the ePWM Module for 0 100 Duty Cycle Control provides a guide for the use of the ePWM module to provide 0 to 100 duty cycle control and is applicable to the TMS320x280x family of processors Power Line Communication for Lighting Applications Using Binary Phase Shift Keying BPSK with a Single DSP Controller presents a complete im
136. and transmit message Protects against reception of new message Holds the dynamically programmable priority of transmit message Employs a programmable interrupt scheme with two interrupt levels Employs a programmable alarm on transmission or reception time out Low power mode Programmable wake up on bus activity Automatic reply to a remote request message Automatic retransmission of a frame in case of loss of arbitration or error 32 bit local network time counter synchronized by a specific message communication in conjunction with mailbox 16 Self test mode Operates in a loopback mode receiving its own message A dummy acknowledge is provided thereby eliminating the need for another node to provide the acknowledge bit NOTE For a SYSCLKOUT of 100 MHz the smallest bit rate possible is 15 625 kbps For a SYSCLKOUT of 60 MHz the smallest bit rate possible is 9 375 kbps 68 Peripherals Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 5320 2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 ip Texas TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 eCANOINT eCAN1INT Controls Address Data Enhanced CAN Controller 32 Message
137. applicable even when the PLL is disabled i e code execution will be delayed by this duration even when the PLL is disabled F Clocks to the core and peripherals are enabled The HALT mode is now exited The device will respond to the interrupt if enabled after a latency G Normal operation resumes Figure 6 16 HALT Wake Up Using GPlOn 114 Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 Texas TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 6 10 Enhanced Control Peripherals 6 10 1 Enhanced Pulse Width Modulator ePWM Timing PWM refers to PWM outputs on ePWM1 6 Table 6 22 shows the PWM timing requirements and Table 6 23 switching characteristics Table 6 22 ePWM Timing Requirements TEST CONDITIONS MIN MAX UNIT tw SYCIN Sync input pulse width Asynchronous 2lc sco cycles Synchronous 2lc sco cycles With input qualifier 1tcsco twiosw cycles 1 For an explanation of the input qualifier parameters see Table 6 15 Table 6 23 ePWM Switching Characteristics PARAMETER TEST CONDITIONS MIN MAX UNIT tw PWM Pulse dura
138. are Features 100 MHz 1 44 1 12 2 2 Hardware Features 60 MHz Devices 4 he e nnne nnn 13 2 3 S 19 3 1 Addresses of Flash Sectors in F2809 4 4 1 1 lt 31 3 2 Addresses of Flash Sectors in F2808 1 2 1 31 3 3 Addresses of Flash Sectors F2806 2802 2 31 3 4 Addresses of Flash Sectors in F2801 F28015 28016 4 4 44 7 7 32 3 5 Impact of Using the Code Security Module 2 2 2 4 4 4 1 6 32 3 6 MEDECIN 33 3 7 Boot Mode 36 3 8 Peripheral Frame 0 Registers 41 3 9 Peripheral Frame 1 Registers 2 2 1 nnn nnn 41 3 10 Peripheral Frame
139. ation tool to get started on your project Step 2 Download starter software To simplify programming for C28x devices it is recommended that users download and use the C C Header Files and Example s to begin developing software for the C28x devices and their various peripherals After downloading the appropriate header file package for your device refer to the following resources for step by step instructions on how to run the peripheral examples and use the header file structure for your own software The Quick Start Readme in the doc directory to run your first application Programming TMS320x28xx and 28xxx Peripherals in C C Application Report literature number SPRAA85 Step 3 Download flash programming software Many C28x devices include on chip flash memory and tools that allow you to program the flash with your software IP Flash Tools C28x Flash Tools TMS320F281x Flash Programming Solutions literature number SPRB169 Running an Application from Internal Flash Memory on the TMS320F28xxx DSP literature number SPRA958 Step 4 Move on to more advanced topics For more application software and other advanced topics visit the website at http www ti com or http www ti com c2000getstarted 10 F280x F2801x C280x DSPs Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS3
140. ations 93 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 TEXAS INSTRUMENTS www ti com 6 2 Recommended Operating Conditions over operating free air temperature range unless otherwise noted Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 MIN NOM MAX UNIT Device supply voltage I O Vppio 3 14 3 3 3 47 V Device supply voltage CPU Vpp 1 71 1 8 1 89 V Supply ground Ves Vssio 0 V ADC supply voltage 3 3 V 3 14 3 3 3 47 V Vppa2 VDDAIO ADC supply voltage 1 8 V 1 71 1 8 1 89 V Vpp1A18 VDD2A18 Flash supply voltage Vppavri 3 14 3 3 3 47 V Device clock frequency system clock 100 MHz devices 2 100 MHz fevscLkour 60 MHz devices 2 60 MHz High level input voltage inputs except X1 2 Vppio 0 3 V 0 7 Vpp 0 05 Vpp Low level input voltage Vii All inputs except X1 Vss 0 3 0 8 V X1 0 3 Vpp 0 05 High level output source current All Os except Group 2 mA 2 4 V Group 2 8 Low level output sink current All Os except Group 2 4 mA VoL VoL MAX loL Group 20 8 A version 40 85 Ambient temperature S v
141. bes differences between the Texas Instruments TMS320x281x and the TMS320x280x 2801x 2804x DSPs to assist in application migration Software SPRC191 280 C2801x C C Header Files and Peripheral Examples BSDL Models SPRM244 F2809 GGM ZGM BSDL Model SPRM245 F2809 PZ BSDL Model SPRM198 F2808 100 Pin GGM ZGM BSDL Model SPRM197 F2808 100 Pin PZ BSDL Model SPRM196 F2806 100 Pin PZ BSDL Model SPRM200 F2806 100 Pin GGM ZGM BSDL Model SPRM414 F2802 GGM BSDL Model SPRM413 F2802 PZ BSDL Model SPRM415 F2802 ZGM BSDL Model SPRM194 F2801 100 Pin GGM ZGM BSDL Model SPRM195 F2801 100 Pin PZ BSDL Model SPRM261 C2802 100 Pin GGM ZGM BSDL Model SPRM260 C2802 100 Pin PZ BSDL Model SPRM259 C2801 100 Pin GGM ZGM BSDL Model SPRM258 C2801 100 Pin PZ BSDL Model SPRM416 28016 GGM BSDL Model SPRM357 F28016 PZ BSDL Model SPRM417 F28016 ZGM BSDL Model SPRM412 F28015 GGM BSDL Model SPRM356 F28015 PZ BSDL Model SPRM355 F28015 ZGM BSDL Model IBIS Models SPRM445 F2809 GGM IBIS Model SPRM295 F2809 PZ IBIS Model Copyright 2003 2009 Texas Instruments Incorporated Device Support 91 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti c
142. can individually erase program and validate a flash sector while leaving other sectors untouched However it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase program other sectors Special memory pipelining is provided to enable the flash module to achieve higher performance The flash OTP is mapped to both program and data space therefore it can be used to execute code or store data information Note that addresses 0x3F7FFO Ox3F7FF5 are reserved for data variables and should not contain program code NOTE The F2809 F2808 F2806 F2802 F2801 Flash and OTP wait states can be configured by the application This allows applications running at slower frequencies to configure the flash to use fewer wait states Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options register With this mode enabled effective performance of linear code execution will be much faster than the raw performance indicated by the wait state configuration alone The exact performance gain when using the Flash pipeline mode is application dependent For more information on the Flash options Flash wait state and OTP wait state registers see the 5320 280 2801x 2804x DSP System Control and Interrupts Reference Guide literature number SPRU712 3 2 6 ROM The C2802 contains 32K x 16 of ROM while the C2801 contains 16K x 16 of ROM 3 2 7 1 SARAMs All
143. ces support the following peripherals which are used for embedded control and communication ePWM The enhanced PWM peripheral supports independent complementary PWM generation adjustable dead band generation for leading trailing edges latched cycle by cycle trip mechanism Some of the PWM pins support HRPWM features eCAP The enhanced capture peripheral uses a 32 bit time base and registers up to four programmable events in continuous one shot capture modes This peripheral can also be configured to generate an auxiliary PWM signal Copyright 2003 2009 Texas Instruments Incorporated Functional Overview 39 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TEXAS TMS320C2801 5320 28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com eQEP The enhanced QEP peripheral uses a 32 bit position counter supports low speed ADC measurement using capture unit and high speed measurement using a 32 bit unit timer This peripheral has a watchdog timer to detect motor stall and input error detection logic to identify simultaneous edge transition in QEP signals The ADC block is a 12 bit converter single ended 16 channels It contains two sample and hold units for simultaneous sampling 3 2 21
144. code samples Boot Mode pins Based on the status of the Boot Mode pin the boot code branches to destination memory or boot code function If boot ROM code executes after power on conditions in debugger environment the boot code execution time is based on the current SYSCLKOUT speed The SYSCLKOUT Will be based on user environment and could be with or without PLL enabled C See Section 6 8 for requirements to ensure a high impedance state for GPIO pins during power up Figure 6 8 Power on Reset Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 107 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 5320 28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 5320 28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com Table 6 13 Reset XRS Timing Requirements MIN NOM MAX UNIT Pulse duration stable XCLKIN to XRS high 8tctosccLk cycles tw RSL2 Pulse duration XRS low Warm reset 8tcosccuk cycles kiss ben 2 reset pulse generated by la Ex Delay time address data valid after XRS high 32tc osccLk cycles toscsr 2 Oscillator start up time 1 10 ms th boot mode Hold time for boot mode pins 200tc sccLk cycles 1 2 108 In addition to the tym
145. ctional Overview 51 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 at el SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 3 7 Low Power Modes Block The low power modes on the 280x are similar to the 240x devices Table 3 18 summarizes the various modes Table 3 18 Low Power Modes MODE LPMCRO 1 0 OSCCLK CLKIN SYSCLKOUT IDLE 00 On On ee interrupt any enabled STANDBY 2 off Off ir oo B uy HALT 1X oscillator ndi PLL turned off Off Off Portia signal watchdog not functional 1 The Exit column lists which signals or under what conditions the low power mode will be exited A low signal on any of the signals will exit the low power condition This signal must be kept low long enough for an interrupt to be recognized by the device Otherwise the IDLE mode will not be exited and the device will go back into the indicated low power mode 2 The IDLE mode on the C28x behaves differently than on the 24x 240x On the C28x the clock output from the CPU SYSCLKOUT is still functional while on the 24x 240x the clock is turned off 3 On the C28x the JTAG port can still function even
146. dback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 6 10 7 3 Sequential Sampling Mode Single Channel SMODE 0 In sequential sampling mode the ADC can continuously convert input signals on any of the channels Ax to Bx The ADC can start conversions on event triggers from the ePWM software trigger or from an external ADCSOC signal If the SMODE bit is 0 the ADC will do conversions on the selected channel on every Sample Hold pulse The conversion time and latency of the Result register update are explained below The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update The selected channels will be sampled at every falling edge of the Sample Hold pulse The Sample Hold pulse width can be programmed to be 1 ADC clock wide minimum or 16 ADC clocks wide maximum Sample n 2 Sample n 1 Analog Input on I Channel Ax or Bx Samp T Sample Hold sHPuse d LJ LT LT LT l TT LI Ur SMODE Bit t dS ta SH 4 gt 4 laschx n 1 ADC Event Trigger from ePWM or Other Sources IM M NE lt gt
147. de Security Module Boot to Flash Entry Point program branch instruction here Ox3F 7FF8 OxSF 7FFF Security Password 128 Bit Do not program to all zeros NOTE When the code security passwords are programmed all addresses between OxS3F7F80 0x3F7FF5 cannot be used as program code or data These locations must be programmed to 0x0000 If the code security feature is not used addresses Ox3F7F80 through Ox3F7FEF may be used for code or data Addresses 7 OxS3F7FF5 are reserved for data and should not contain program code On ROM devices addresses 0x3F7FFO OxSF7FF5 Ox3D7BFC Ox3D7BFF are reserved for irrespective of whether code security has been used or not User application should not use these locations in any way Table 3 5 shows how to handle these memory locations Table 3 5 Impact of Using the Code Security Module ADDRESS FLASH ROM Code security enabled Code security disabled Code security enabled Code security disabled Ox3F7F80 Ox3F7FEF Ox3F7FFO OxSF7FF5 Fill with 0x0000 Application code and data Fill with 0 0000 Application code and data Reserved for data only Ox3D7BFC Ox3D7BFF Application code and data Reserved for TI Do not use Peripheral Frame 1 and Peripheral Frame 2 are grouped together so as to enable these blocks to be write read peripheral block protected The protected m
148. duct Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 ee SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com In the 280x devices the timer interrupt signals TINTO TINT1 TINT2 are connected as shown in Figure 4 2 CPU TIMER 0 CPU TIMER 1 XINT13 CPU TIMER 2 Reserved for DSP BIOS A timer registers are connected to the memory bus of the C28x processor B The timing of the timers is synchronized to SYSCLKOUT of the processor clock Figure 4 2 CPU Timer Interrupt Signals and Output Signal The general operation of the timer is as follows The 32 bit counter register TIMH TIM is loaded with the value in the period register PRDH PRD The counter register decrements at the SYSCLKOUT rate of the C28x When the counter reaches 0 a timer interrupt output signal generates an interrupt pulse The registers listed in Table 4 1 are used to configure the timers For more information see the TMS320x280x 2801x 2804x DSP System Control and Interrupts Reference Guide literature number SPRU712 Table 4 1 CPU Timers 0 1 2 Configuration and Conirol Registers NAME ADDRESS SIZE x16 DESCRIPTION TIMEROTIM 0x0C00 1 CPU Time
149. duction 17 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com i i C Q0 1 2 3 4 5 6 7 8 9 10 Bottom View Figure 2 5 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320F28016 TMS320F28015 TMS320C2802 TMS320C2801 100 Ball and ZGM MicroStar BGA Bottom View 18 Introduction Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 5 INSTRUMENTS www ti com 2 2 Signal Descriptions TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Table 2 3 describes the signals on the 280x devices All digital inputs are TTL compatible All outputs are 3 3 V with CMOS levels Inputs are not 5 V tolerant Table 2 3 Signal Descriptions NAME PIN NO PZ PIN GGM ZGM BALL DESCRIPTION 9 JT
150. e DSP through the 2 module On the 280x the 2 contains a 16 level receive and transmit FIFO for reducing interrupt servicing overhead The 280x devices contain three peripheral register spaces The spaces are categorized as follows Peripheral Frame 0 Peripheral Frame 1 Peripheral Frame 2 40 Functional Overview Product Folder Link s These are peripherals that are mapped directly to the CPU memory bus See Table 3 8 These are peripherals that are mapped to the 32 bit peripheral bus See Table 3 9 These are peripherals that are mapped to the 16 bit peripheral bus See Table 3 10 Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback 5320 2809 TMS320F2808 5320 2806 5320 2802 TMS320F2801 5320 2802 5320 2801 TMS320F28016 TMS320F28015 5 INSTRUMENTS www ti com TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Table 3 8 Peripheral Frame 0 Registers 2 NAME ADDRESS RANGE SIZE x16 ACCESS TYPE Device Emulation Registers 0x0880 0xO9FF 384 EALLOW protected FLASH Registers 0x0A80 OxOADF 96 Code Security Module Registers OxOAEF 16 EALLOW protected ADC Result Registers dual mapped 0x0B00 16 Not EALLOW protected CPU TIMERO 1 2 R
151. e 4 14 2 Registers NAME ADDRESS DESCRIPTION I2COAR 0x7900 I2C own address register I2CIER 0x7901 I2C interrupt enable register I2ZCSTR 0x7902 I2C status register I2CCLKL 0x7903 2 clock low time divider register I2CCLKH 0x7904 I2C clock high time divider register I2CCNT 0x7905 I2C data count register I2CDRR 0x7906 I2C data receive register 12 0 7907 I2C slave address register I2CDXR 0x7908 I2C data transmit register I2CMDR 0x7909 2 mode register I2CISRC 0x790A I2C interrupt source register I2CPSC 0x790C I2C prescaler register 2 0 7920 2 FIFO transmit register I2CFFRX 0x7921 2 FIFO receive register I2CRSR 2 receive shift register not accessible to the CPU I2CXSR 2 transmit shift register not accessible to the CPU Copyright 2003 2009 Texas Instruments Incorporated Peripherals 81 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 at el SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 4 11 GPIO MUX On the 280x the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO in addition to providing individual pin bit banging ca
152. e peak spurious signal Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 POSUERE TMS320C2801 TMS320F28016 TMS320F28015 6 12 Flash Timing Table 6 43 Flash Endurance for A and S Temperature Material MIN TYP MAX UNIT Flash endurance for the array write erase cycles 0 to 85 C ambient 20000 50000 cycles Noter OTP endurance for the array write cycles 0 to 85 C ambient 1 write 1 Write erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers Table 6 44 Flash Endurance for Q Temperature Material MIN TYP MAX UNIT Flash endurance for the array write erase cycles 40 to 125 C ambient 20000 50000 cycles Notp OTP endurance for the array write cycles 40 C to 125 C ambient 1 write 1 Write erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers Table 6 45 Flash Parameters at 100 MHz SYSCLKOUT PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Program 16 Bit Word 50 us 16K Sector 5
153. e result register update are explained below The ADC interrupt flags are set a few SYSCLKOUT cycles after the Result register update The selected channels will be sampled simultaneously at the falling edge of the Sample Hold pulse The Sample Hold pulse width can be programmed to be 1 ADC clock wide minimum or 16 ADC clocks wide maximum NOTE In simultaneous mode the ADCIN channel pair select has to be 0 0 1 1 A7 B7 and not in other combinations such as A1 B3 etc Sample n Sample 1 Analog Input on Channel Ax Analog Input on Channel Bx AbDccock LI LT LT U LT U LT LT LT LJ LT Sample and Hold SH Pulse SMODE Bit j gt ta SH 4 gt ldschA0 1 ADC Event Trigger from tsH 71 ePWM or Other Sources f taschaon 4 n 1 T P Figure 6 27 Simultaneous Sampling Mode Timing Table 6 42 Simultaneous Sampling Mode Timing AT 12 5 MHz SAMPLE n SAMPLE n 1 ADC CLOCK REMARKS 80 ns ta SH Delay time from event trigger to 2 5 sampling tsu Sample Hold width Acquisition 1 Acqps 80 ns with Acqps 0 value 0 15 Width c ADCCLK ADCTRL1 8 11 ta schA0_n Delay time for first result to Atc ADCCLK 320 ns appear in Result register ta schBo_n Delay time for first result to 5tc ADCCLK 400 ns appear
154. eached its maximum value To prevent this the user disables the counter or the software must periodically write a 0x55 OxAA sequence into the watchdog key register which will reset the watchdog counter Figure 3 14 shows the various functional blocks within the watchdog module WDCR WDDIS WDCR WDPS 2 0 WDCNTR 7 0 OSCCLK WDCLK t 8 Bit o Watchdog Counter CLR Clear Counter Internal Pullup WDKEY 7 0 Watchdog Output Pulse 55 Good Key 512 OSCCLKs Bad Key Detector gt m Ls i Core reset WDCHK XRS lt 1 WDCR WDCHK 2 0 mE A The WDRSI signal is driven low for 512 OSCCLK cycles Figure 3 14 Watchdog Module Generate SCSR WDENINT The WDINT signal enables the watchdog to be used as a wakeup from IDLE STANDBY mode In STANDBY mode all peripherals are turned off on the device The only peripheral that remains functional is the watchdog The WATCHDOG module will run off OSCCLK The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY if enabled See Section 3 7 Low Power Modes Block for more details In IDLE mode the WDINT signal can generate an interrupt to the CPU via the PIE to take the CPU out of IDLE mode In HALT mode this feature cannot be used because the oscillator and PLL are turned off and hence so is the WATCHDOG Copyright 2003 2009 Texas Instruments Incorporated Fun
155. egisters 0 0 00 0x0C3F 64 Not EALLOW protected PIE Registers OxOCEO OxOCFF 32 Not EALLOW protected PIE Vector Table 0 0000 OxODFF 256 EALLOW protected 1 Registers in Frame 0 support 16 bit and 32 bit accesses 2 disables writes to prevent stray code or pointers from corrupting register contents 4 The Flash Registers are also protected by the Code Security Module CSM 2 Missing segments of memory space are reserved and should not be used in applications 3 If registers EALLOW protected then writes cannot be performed until the EALLOW instruction is executed The EDIS instruction Table 3 9 Peripheral Frame 1 Registers NAME ADDRESS RANGE SIZE x16 ACCESS TYPE Some eCAN control registers and selected eCANA Registers 0x6000 Ox60FF 256 bits in other eCAN control registers are EALLOW protected eCANA Mailbox RAM 0x6100 0x61FF 256 Not EALLOW protected Some eCAN control registers and selected eCANB Registers 0x6200 0x62FF 256 bits in other eCAN control registers are EALLOW protected eCANB Mailbox RAM 0x6300 0x63FF 256 Not EALLOW protected ePWM 1 Registers 0x6800 0x683F 64 ePWMe Registers 0x6840 0x687F 64 ePWMS Registers 0x6880 0x68BF 64 Some ePWM registers are EALLOW ePWM4 Registers 0 68 0 0x68FF 64 protected See Table 4 2 ePWMS5S Registers 0x6900 0x693F 64 ePWM6 Registers 0x6940
156. encoder to get position direction and speed information from a rotating machine in high performance motion and position control systems It includes the module description and registers TMS320x280x 2801x 2804x Enhanced Capture eCAP Module Reference Guide describes the enhanced capture module It includes the module description and registers TMS320x280x 2801x 2804x High Resolution Pulse Width Modulator Reference Guide describes the operation of the high resolution extension to the pulse width modulator HRPWM TMS320x280x 2801x Enhanced Controller Area Network eCAN Reference Guide describes the enhanced controller area network eCAN on the x280x and x2801x devices TMS320x280x 2801x 2804x Serial Communication Interface SCI Reference Guide describes the features and operation of the serial communication interface SCI module that is available on the TMS320x280x 2801x 2804x devices TMS320x280x 2801x 2804x Serial Peripheral Interface Reference Guide describes how the serial peripheral interface works TMS320x28xx 28xxx Inter Integrated Circuit I2C Module Reference Guide describes the features and operation of the inter integrated circuit I2C module TMS320x280x 2801x 2804x Boot ROM Reference Guide describes the purpose and features of the bootloader factory programmed boot loading software It also describes other contents of the device on chip boot ROM and identifies where all of the information is located within
157. ent 8 channel modules can be cascaded to form a 16 channel module Although there are multiple input channels and two sequencers there is only one converter in the ADC module Figure 4 7 shows the block diagram of the ADC module The two 8 channel modules have the capability to autosequence a series of conversions each module has the choice of selecting any one of the respective eight channels available through an analog MUX In the cascaded mode the autosequencer functions as a single 16 channel sequencer On each sequencer once the conversion is complete the selected channel value is stored in its respective RESULT register Autosequencing allows the system to convert the same channel multiple times allowing the user to perform oversampling algorithms This gives increased resolution over traditional single sampled conversion results Copyright 2003 2009 Texas Instruments Incorporated Peripherals 63 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 5320 28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 ee SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com System High Speed SYSCLKOUT Control Block Prescaler ADCENCLK HSPCLK Analog MUX Result Registers ADCINAO Result Reg 0 70A8h Result Reg 1 x S H
158. er Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 100 MHz SYSCLKOUT TEXAS INSTRUMENTS www ti com Table 6 4 TMS320C2802 TMS320C2801 Current Consumption by Power Supply Pins at MODE TEST CONDITIONS Ipp 1 Ippio Ippais 2 Ippa33 3 MAX Operational ROM The following peripheral clocks are enabled ePWM1 2 3 eCAP1 2 eQEP1 eCAN A SCI A SPI A ADC 12 All PWM pins are toggled at 100 kHz pins are left unconnected Data is continuously transmitted out of the SCI A SCI B and eCAN A ports The hardware multiplier is exercised Code is running out of ROM with 3 wait states XCLKOUT is turned off 150 mA 165 mA 5 mA 10 mA 30 mA 38 mA 1 5 mA 2 IDLE XCLKOUT is turned off The following peripheral clocks are enabled eCAN A SCI A SPI A lac 75 mA 90 mA 500 pA 2mA 5 50 uA 15 pA 30 pA STANDBY Peripheral clocks are off 6mA 12 mA 100 pA 500 pA 5 50 uA 15 pA 30 pA HALT Peripheral clocks are off Input clock is disabled 70 uA 80 uA
159. ernal band gap reference sources both ADCREFP and ADCREFM signals and hence these voltages track together The ADC converter uses the difference between these two as its reference The total gain error listed for the internal reference is inclusive of the movement of the internal bandgap over temperature Gain error over temperature for the external reference option will depend on the temperature profile of the source used 6 Voltages above VppA 0 3 V or below Vss 0 3 V applied to an analog input pin may temporarily affect the conversion of another pin To avoid this the analog inputs should be kept within these limits 7 Tl recommends using high precision external reference TI part REF3020 3120 or equivalent for 2 048 V reference Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 125 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 6 10 7 1 ADC Power Up Control Bit Timing ADC Power Up Delay ADC Ready for Conversions PWDNBG E PWDNREF 4 lqBaeR PWDNADC ce O tapwo Request for ADC 7 Conversion Figure 6 24 ADC Power Up Control Bit T
160. ersion 40 125 Q version 40 125 1 Group 2 pins are as follows GPIO28 GPIO29 GPIO30 GPIO31 XCLKOUT EMUO and EMU1 6 3 Electrical Characteristics over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT lou lou 24 Vou High level output voltage 50 pA Vopio 0 2 Low level output voltage lo MAX 0 4 V Pin with pulluP e V bio 3 3 Vie 0 V All 1 Os including XRS 80 140 190 j Input current enabled low level Pin with pulldown enabled Vppio 3 3 V Vin 0 V 2 Pin with pullu enabled PERCHE Vopio 3 3 V Vin Vppio 2 Input current Pin with pulldown _ u high level enabled 3 3 V 280 28 50 80 Pin with pulldown Vppio 3 3 V Vin Vppio C280x 80 140 190 Output current pullup or _ loz pulldown disabled Vo or 0 V 2 pA Ci Input capacitance 2 pF 94 Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 6 4 Current Consumption Table 6 1 TMS320F2809 TMS320F2808 Current Consumption by Power Supply Pins at 100 MHz SYSCLKOUT 2 3 4 1 Ipp lopio IppavrL Ippais Ippaas MODE TEST CONDITIONS TYP MAX TYP MAX TYPO MAX
161. eset occurs During watchdog reset the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles I OD 1 The output buffer of this pin is an open drain with an internal pullup It is recommended that this pin be driven by an open drain device ADC SIGNALS ADCINA7 16 F3 ADC Group A Channel 7 input I ADCINA6 17 F4 ADC Group A Channel 6 input I ADCINA5 18 G4 ADC Group A Channel 5 input I ADCINA4 19 G1 ADC Group A Channel 4 input I ADCINA3 20 G2 ADC Group A Channel input I ADCINA2 21 G3 ADC Group A Channel 2 input 1 ADCINA1 22 H1 ADC Group A Channel 1 input I ADCINAO 23 H2 ADC Group A Channel 0 input I ADCINB7 34 K5 ADC Group B Channel 7 input I ADCINB6 33 H4 ADC Group B Channel 6 input 1 ADCINB5 32 K4 ADC Group B Channel 5 input I ADCINB4 31 J4 ADC Group Channel 4 input I ADCINB3 30 K3 ADC Group Channel input I ADCINB2 29 H3 ADC Group B Channel 2 input I ADCINB1 28 J3 ADC Group B Channel 1 input I ADCINBO 27 K2 ADC Group B Channel 0 input I ADCLO 24 J1 Low Reference connect to analog ground 1 ADCRESEXT 38 F5 ADC External Current Bias Resistor Connect a 22 resistor to analog ground ADCREFIN 35 J5 External reference input 1 Internal Reference Positive Output Requires a low ESR 50 1 5 ceramic bypass capacitor ADCREFE d G5 of 2 2 uF to analog ground Internal Reference Medium Output Requires a low ESR 50 mQ 1 5 ceramic bypass capacitor A
162. fer Register SPITXBUF 0x7048 1 SPI A Serial Output Buffer Register SPIDAT 0x7049 1 SPI A Serial Data Register SPIFFTX 0x704A 1 SPI A FIFO Transmit Register SPIFFRX 0x704B 1 SPI A FIFO Receive Register SPIFFCT 0x704C 1 SPI A FIFO Control Register SPIPRI 0x704F 1 SPI A Priority Control Register 1 baie in this table are mapped to Peripheral Frame 2 This space only allows 16 bit accesses 32 bit accesses produce undefined results Table 4 11 SPI B Registers NAME ADDRESS SIZE x16 DESCRIPTION SPICCR 0x7740 1 SPI B Configuration Control Register SPICTL 0 7741 1 SPI B Operation Control Register SPISTS 0x7742 1 SPI B Status Register SPIBRR 0x7744 1 SPI B Baud Rate Register SPIRXEMU 0x7746 1 SPI B Receive Emulation Buffer Register SPIRXBUF 0 7747 1 SPI B Serial Input Buffer Register SPITXBUF 0x7748 1 SPI B Serial Output Buffer Register SPIDAT 0x7749 1 SPI B Serial Data Register SPIFFTX 0x774A 1 SPI B FIFO Transmit Register SPIFFRX 0x774B 1 SPI B FIFO Receive Register SPIFFCT 0x774C 1 SPI B FIFO Control Register SPIPRI 0x774F 1 SPI B Priority Control Register 1 results Copyright 2003 2009 Texas Instruments Incorporated Registers in this table are mapped to Peripheral Frame 2 This space only allows 16 bit accesses 32 bit accesses produce undefined Peripherals Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016
163. g Ball Finish Requires Login TMS320F2802ZGMA ACTIVE BGA ZGM 100 184 Green RoHS SNAGCU Level 3 260C 168 HR MICROSTAR amp no Sb Br TMS320F2802ZGMS ACTIVE BGA ZGM 100 184 Green RoHS SNAGCU Level 3 260C 168 HR MICROSTAR amp no Sb Br TMS320F2806GGMA ACTIVE BGA GGM 100 184 TBD SNPB Level 3 220C 168 HR MICROSTAR TMS320F2806GGMS ACTIVE BGA GGM 100 184 TBD SNPB Level 3 220C 168 HR MICROSTAR TMS320F2806PZA ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br 5320 2806 70 LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F2806PZS ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F2806ZGMA ACTIVE BGA ZGM 100 184 Green RoHS SNAGCU Level 3 260C 168 HR MICROSTAR amp no Sb Br TMS320F2806ZGMS ACTIVE BGA ZGM 100 184 Green RoHS SNAGCU Level 3 260C 168 HR MICROSTAR amp no Sb Br TMS320F2808GGMA ACTIVE BGA GGM 100 1 TBD SNPB Level 3 220C 168 HR MICROSTAR TMS320F2808GGMS ACTIVE BGA GGM 100 1 TBD SNPB Level 3 220C 168 HR MICROSTAR TMS320F2808PZA ACTIVE LQFP PZ 100 90 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br 5320 2808 70 LQFP PZ 100 1 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F2808PZS ACTIVE LQFP PZ 100 1 Green RoHS CU NIPDAU Level 2 260C 1 YEAR amp no Sb Br TMS320F2808ZGMA ACTIVE BGA ZGM 100 1 Green RoHS SNAGCU Level 3 260C 168 HR MICROSTAR amp no Sb Br TMS320F2808ZGMS ACT
164. g four interrupt conditions Separate enable bits for transmitter and receiver interrupts except BRKDT _ 100 MHz _ Max bit rate 16 6 25 108 b s for 100 MHz devices _ 60 MHz _ bit rate 16 3 75 x 10 b s for 60 MHz devices non return to zero format SCI module control registers located in the control register frame beginning at address 7050h NOTE All registers in this module are 8 bit registers that are connected to Peripheral Frame 2 When a register is accessed the register data is in the lower byte 7 0 and the upper byte 15 8 is read as zeros Writing to the upper byte has no effect Copyright 2003 2009 Texas Instruments Incorporated Peripherals 73 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Enhanced features Auto baud detect hardware logic 16 level transmit receive FIFO The SCI port operation is configured and controlled by the registers listed in Table 4 8 and Table 4 9 Table 4 8 SCI A Registers NAME ADDRESS SIZE x16 DESCRIPTION SCICCRA 0x7050 1 SCI A Communications Control Register SCICTL1A 0x7051 1 SCI A Control
165. ght 2003 2009 Texas Instruments Incorporated Peripherals 61 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 POTBOMENDS SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com Table 4 4 eQEP Control and Status Registers NAME aa ADDRESS REGISTER DESCRIPTION SHADOW QPOSCNT 0 6 00 0x6B40 2 0 eQEP Position Counter QPOSINIT 0 6 02 0 6 42 2 0 eQEP Initialization Position Count QPOSMAX 0 6 04 0 6 44 2 0 eQEP Maximum Position Count QPOSCMP 0 6 06 0 6 46 2 1 eQEP Position compare QPOSILAT 0 6 08 0x6B48 2 0 eQEP Index Position Latch QPOSSLAT Ox6BOA Ox6B4A 2 0 eQEP Strobe Position Latch QPOSLAT 0x6B0C 0x6B4G 2 0 eQEP Position Latch QUTMR 0x6B0E 0x6B4E 2 0 eQEP Unit Timer QUPRD 0x6B10 0x6B50 2 0 eQEP Unit Period Register QWDTMR 0x6B12 0x6B52 1 0 eQEP Watchdog Timer QWDPRD 0x6B13 0x6B53 1 0 eQEP Watchdog Period Register QDECCTL 0 6 14 0 6 54 1 0 eQEP Decoder Control Register QEPCTL 0 6 15 0 6 55 1 0 eQEP Control Register QCAPCTL 0x6B16 0 6 56 1 0 eQEP Capture Control Register QPOSCTL 0x6B17 0x6B57 1 0 eQEP Position compare Control Register QEINT 0x6B18 0x6B58 1 0 eQEP Interr
166. hat typically are handled by microcontroller devices This efficiency removes the need for a second processor in many systems The 32 x 32 bit MAC capabilities of the C28x and its 64 bit processing capabilities enable the C28x to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive floating point processor solution Add to this the fast interrupt response with automatic context save of critical registers resulting in a device that is capable of servicing many asynchronous events with minimal latency The C28x has an 8 level deep protected pipeline with pipelined memory accesses This pipelining enables the C28x to execute at high speeds without resorting to expensive high speed memories Special branch look ahead hardware minimizes the latency for conditional discontinuities Special store conditional operations further improve performance 3 2 2 Memory Bus Harvard Bus Architecture As with many DSP type devices multiple busses are used to move data between the memories and peripherals and the CPU The C28x memory bus architecture contains a program read bus data read bus and data write bus The program read bus consists of 22 address lines and 32 data lines The data read and write busses consist of 32 address lines and 32 data lines each The 32 bit wide data busses enable single cycle 32 bit operations The multiple bus architecture commonly termed Harvard Bus enables the C28x to fetch an instructio
167. hereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulato
168. i com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DLP Products www dlp com Communications and www ti com communications Telecom DSP dsp ti com Computers and www ti com computers Peripherals Clocks and Timers www ti com clocks Consumer Electronics www ti com consumer apps Interface interface ti com Energy www ti com energy Logic logic ti com Industrial www ti com industrial Power Mgmt power ti com Medical www ti com medical Microcontrollers microcontroller ti com Security www ti com security RFID www ti rfid com Space Avionics amp www ti com space avionics defense Defense and ZigBee Solutions www ti com Iprf Video and Imaging www ti com video Wireless www ti com wireless apps Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2010 Texas Instruments Incorporated
169. igure 6 15 STANDBY Entry and Exit Timing Diagram m Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 113 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 at el SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com Table 6 20 HALT Mode Timing Requirements MIN NOM MAX UNIT twwake cpio Pulse duration GPIO wake up signal loscst 2lcosccu cycles tw WAKE XRS Pulse duration XRS wakeup signal tosest 8te osccLk cycles 1 See Table 6 13 for an explanation of Table 6 21 HALT Mode Switching Characteristics PARAMETER MIN TYP MAX UNIT ta IDLE xcoL Delay time IDLE instruction executed to XCLKOUT low S2lc sco 45tysco cycles tp PLL lock up time 1310724 cycles Delay time PLL lock to program execution resume Wake up from flash 1125tesco cycles la WAKE HALT Flash module in sleep state Wake up from SARAM 35tc sco cycles A 4 0 B 4 D F Device Status HALT Flushing Pipeline PLL Lock up Time Normal Wake up Latency Execution ta WAKE HALT
170. iming Table 6 39 ADC Power Up Delays PARAMETER MIN TYP UNIT ta BGR Delay time for band gap reference to be stable Bits 7 and 6 of the ADCTRL3 5 ms register ADCBGRFDN 1 0 must be set to 1 before the PWDNADC bit is enabled la PWD Delay time for power down control to be stable Bit delay time for band gap 20 50 us reference to be stable Bits 7 and 6 of the ADCTRLS register ADCBGRFDN1 0 1 must be set to 1 before the PWDNADC bit is enabled Bit 5 of the ADCTRL3 register PWDNADO must be set to 1 before any ADC conversions are initiated ms 1 Timings maintain compatibility to the 281x ADC module The 280x ADC also supports driving all 3 bits at the same time and waiting tagar Ms before first conversion Table 6 40 Current Consumption for Different ADC Configurations at 12 5 MHz ADCCLK 2 ADC OPERATING MODE CONDITIONS VpDA18 Vppa3 3 UNIT Mode A Operational Mode and REF enabled 30 2 mA PWD disabled Mode B ADC clock enabled 9 0 5 mA BG and REF enabled PWD enabled Mode C ADC clock enabled 5 29 Ba BG and REF disabled PWD enabled Mode D ADC clock disabled 5 15 Ba BG and REF disabled PWD enabled 1 Test Conditions SYSCLKOUT 100 MHz ADC module clock 12 5 MHz ADC performing a continuous conversion of all 16 channels in Mode A 2 VppA18 includes current into Vpp1A18 and Vpp2A18 VppaA3 3 includes current i
171. in Result register laschA0 Delay time for successive results 3 Acqps tapccuk 240 ns to appear in Result register ta schBo_n 1 Delay time for successive results 3 Acqps 240 ns to appear in Result register Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 129 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 NSTRUMENTS SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 6 11 Detailed Descriptions 130 Integral Nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale The point used as zero occurs one half LSB before the first code transition The full scale point is defined as level one half LSB beyond the last code transition The deviation is measured from the center of each particular code to the true straight line between these two points Differential Nonlinearity An ideal ADC exhibits code transitions that are exactly 1 LSB apart DNL is the deviation from this ideal value A differential nonlinearity error of less than 1 LSB ensures no missing codes Zero Offset The major carry transition should occur when the ana
172. ional Overview Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 5 INSTRUMENTS www ti com Low 64K 0000 FFFF 24x 240x equivalent data space High 64K 3F0000 3FFFFF 24x 240x equivalent program space Memory blocks are not to scale Block Start Address 0x00 0000 0x00 0040 0x00 0400 0x00 0800 0x00 0000 0x00 0 00 0x00 6000 0x00 7000 0x00 8000 0x00 9000 0x00 A000 0x00 C000 0x3D 7800 Ox3D 7C00 Ox3E 8000 7FF8 8000 9000 A000 000 FFCO TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Data Space Prog Space 0 Vector RAM 32 x 32 Enabled if VMAP z 0 0 SARAM 1K x 16 M1 SARAM 1K x 16 Peripheral Frame 0 PIE Vector RAM Reserved 256 x 16 Enabled if ENPIE 1 Reserved Peripheral Frame 1 protected Reserved Peripheral Frame 2 protected LO SARAM 0 wait 4K x 16 Secure Zone Dual Mapped L1 SARAM 0 wait 4K x 16 Secure Zone Dual Mapped HO SARAM 0 wait 8K x 16 Dual Mapped Reserved OTP 1K x 16 Secure Zone
173. ional port I OD EPWMSYNCO Enhanced PWM external synch pulse output O ADCSOCBO ADC start of conversion O GPIO34 General Purpose Input Output 34 2 I 43 G7 1 pullups on GPIO12 GPIO34 are enabled upon reset NOTE Some peripheral functions may not be available in TMS320F2801x devices See Table 2 2 for details 24 Introduction Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TEXAS INSTRUMENTS www ti com TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 3 Functional Overview 32 bit CPU TIMER 0 Memory Bus TINTO Real Time JTAG TDI TDO TRST TCK 7 TMS EMUO EMU1 TINT1 32 bit CPU TIMER 1 32 bit CPU TIMER 2 PIE 96 Interrupts 0 SARAM 1K x 16 M1 SARAM 1K x 16 1L dL iL Bii Interrupt 4 trol em SPI A B C D FIFO 0 wait SARAM 0 wait eCAN A B 32 mbox KY s os y 2 z eQEP1 2 o 5 eCAP1 2 3 4 C28x CPU ROM GPIOs timers 32 bit 100 MHz 32K x 16 C2802 35 W 1
174. ise to tune the tank circuit The vendor can also advise the customer regarding the proper tank component values that will produce proper start up and stability over the entire operating range 48 Functional Overview Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 Penne TMS320C2801 TMS320F28016 TMS320F28015 3 6 1 2 PLL Based Clock Module The 280x devices have an on chip PLL based clock module This module provides all the necessary clocking signals for the device as well as control for low power mode entry The PLL has a 4 bit ratio control PLLCR DIV to select different CPU clock rates The watchdog module should be disabled before writing to the PLLCR register It can be re enabled if need be after the PLL module has stabilized which takes 131072 OSCCLK cycles Table 3 16 PLLCR Register Bit Definitions PLLCR DIV POKING 0000 PLL bypass OSCCLK n 0001 OSCCLK 1 n 0010 OSCCLK 2 n 0011 OSCCLK 3 n 0100 OSCCLK 4 n 0101 OSCCLK 5 n 0110 OSCCLK 6 n 0111 OSCCLK 7 n 1000 OSCCLK 8 n 1001 OSCCLK 9 n 1010 OSCCLK 10 n 1011 1111 Reserved 1 This register is EALLOW protected 2 CLKIN is the input
175. k Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 ee SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 6 9 2 GPIO Input Timing GPIO Signal p Pil dtd td 1 0 0 Sampling Period determined by GPxCTRL QUALPRD B twilasw Sampling Window gt 4 SYSCLKOUT cycle 2 QUALPRD 5 O SYSCLKOUT QUALPRD 1 SYSCLKOUT 2 D Output From Qualifier This glitch will be ignored by the input qualifier The QUALPRD bit field specifies the qualification sampling period It can vary from 00 to OxFF If QUALPRD 00 then the sampling period is 1 SYSCLKOUT cycle For any other value n the qualification sampling period in 2n SYSCLKOUT cycles i e at every 2n SYSCLKOUT cycles the GPIO pin will be sampled qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins C The qualification block can take either three or six samples The GPxQSELn Register selects which sample mode is used D Inthe example shown for the qualifier to detect the change the input should be stable for 10 SYSCLKOUT cycles or greater In other words the inputs should be stable for 5 x QUALPRD x 2 SYSCLKOUT cycles This would
176. knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 4 MECHANICAL DATA MPBG028B FEBRUARY 1997 REVISED MAY 2002 GGM S PBGA N100 PLASTIC BALL GRID ARRAY 7 20 TYP OGOGO OOOOO OOOOO OO OO O O m TZ A A1 Corner 1 2 3 4 5 6 7 8 9 10 Bottom View 1 40 MAX 4145257 3 C 12 01 NOTES A Alllinear dimensions are in millimeters B This drawing is subject to change without notice C MicroStar BGA configuration Texas INSTRUMENTS POST OFFICE BOX 655303
177. ks are not to scale C Peripheral Frame 0 Peripheral Frame 1 and Peripheral Frame 2 memory maps are restricted to data memory only User program cannot access these memory maps in program space D Protected means the order of Write followed by Read operations is preserved rather than the pipeline order m Certain memory ranges are EALLOW protected against spurious writes after configuration F Some locations in ROM are reserved for TI See Table 3 5 for more information Figure 3 5 F2802 C2802 Memory Map Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 Functional Overview 29 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 1 TEXAS 5320 2801 TMS320F28016 5320 28015 INSTRUMENTS Block Start Address Data Space Prog Space 0x00 0000 0 Vector RAM 32 x 32 Enabled if VMAP 0 0x00 0040 0 SARAM 1K x 16 0x00 0400 M1 SARAM 1K x 16 8 0 00 0800 0 us rs 0x00 0000 PIE Vector RAM 8 5 256 16 Reserved Enabled if ENPIE 1 5 0x00 0E00 265 Reserved 0x00 6000 24 Peripheral Frame 1 X protected x 0x00 7000 R serv d Peripheral Frame 2 protected 0x00 8000 LO SARAM 0 wait
178. l Interrupt Registers 0x7070 0x707F 16 ADC Registers 0x7100 Ox711F 32 SPI B Registers 0x7740 774 16 Not EALLOW Protected SCI B Registers 0x7750 0x775F 16 SPI C Registers 0x7760 0x776F 16 SPI D Registers 0x7780 0x778F 16 I2C Registers 0x7900 0x792F 48 1 Peripheral Frame 2 only allows 16 bit accesses All 32 bit accesses are ignored invalid data may be returned or written 2 Missing segments of memory space are reserved and should not be used in applications 3 4 Device Emulation Registers These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals The registers are defined in Table 3 11 Table 3 11 Device Emulation Registers ADDRESS NAME RANGE SIZE x16 DESCRIPTION 0x0880 DEVICECNF 0x0881 2 Device Configuration Register PARTID 0x0882 1 Part ID Register 0x002C F2801 0x0024 F2802 0x0034 F2806 0x003C F2808 F2809 0x0014 F28016 0x001C F28015 OxFF2C C2801 OxFF24 C2802 REVID 0x0883 1 Revision ID Register 0x0000 Silicon Rev 0 TMX 0x0001 Silicon Rev A 0x0002 Silicon Rev B TMS 0x0003 Silicon Rev TMS Revision ID Register 0x0000 Silicon rev 0 TMS F2809 only PROTSTART 0x0884 1 Block Protection Start Address Register PROTRANGE 0x0885 1 Block Protection Range Address Register 1 The first byte 00
179. ling the user to scale back on operating frequency if lower power operation is desired Refer to the Electrical Specification section for timing details The PLL block can be set in bypass mode 3 2 14 Watchdog The 280x devices contain a watchdog timer The user software must regularly reset the watchdog counter within a certain time frame otherwise the watchdog will generate a reset to the processor The watchdog can be disabled if necessary 3 2 15 Peripheral Clocking The clocks to each individual peripheral can be enabled disabled so as to reduce power consumption when peripheral is not in use Additionally the system clock to the serial ports except 2 and eCAN and the ADC blocks can be scaled relative to the CPU clock This enables the timing of peripherals to be decoupled from increasing CPU clock speeds 3 2 16 Low Power Modes The 280x devices are full static CMOS devices Three low power modes are provided IDLE Place CPU into low power mode Peripheral clocks may be turned off selectively and only those peripherals that need to function during IDLE are left operating An enabled interrupt from an active peripheral or the watchdog timer will wake the processor from IDLE mode STANDBY Turns off clock to CPU and peripherals This mode leaves the oscillator and PLL functional An external interrupt event will wake the processor and the peripherals Execution begins on the next valid cycle after detection of the interrupt even
180. log input is at zero volts Zero error is defined as the deviation of the actual transition from that point Gain Error The first code transition should occur at an analog value one half LSB above negative full scale The last transition should occur at an analog value one and one half LSB below the nominal full scale Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions Signal to Noise Ratio Distortion SINAD SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency including harmonics but excluding dc The value for SINAD is expressed in decibels Effective Number of Bits ENOB For a sine wave SINAD can be expressed in terms of the number of bits Using the following formula N SINAD 1 76 6 02 it is possible to get a measure of performance expressed as the effective number of bits Thus effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD Total Harmonic Distortion THD THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels Spurious Free Dynamic Range SFDR SFDR is the difference in dB between the rms amplitude of the input signal and th
181. me 0 S 0x00 0000 2 256 x 16 Reserved Enabled if ENPIE 1 us i us 0x00 0 00 85 Reserved os 5 0 00 6000 1 protected H 0x00 7000 Reserved aa Peripheral Frame 2 x protected x 0x00 8000 LO SARAM 0 wait 4K x 16 Secure Zone Dual Mapped 0009000 11 0 wait 4K x 16 Secure Zone Dual Mapped 9x09 4000 HO SARAM 0 wait 8K x 16 Dual Mapped 0x00 C000 Reserved 0x3D 7800 1K x 16 Secure Zone 0x3D 7C00 Reserved 0x3D 8000 FLASH 128K x 16 Secure Zone 0 3 7FF8 128 bit Password s 0x3F 8000 m LO SARAM 0 wait 16 Secure Zone Dual Mapped 99 9000 11 SARAM 0 wait x 16 Secure Zone Dual Mapped ow S5 Ox3F A000 v HO SARAM 0 wait T E 8K x 16 Dual Mapped 59 0 3 C000 R serv d cx Ox3F 000 Boot ROM 4K x 16 0x3F FFCO Vectors 32 x 32 enabled if VMAP 1 ENPIE 0 A Memory blocks are not to scale B Peripheral Frame 0 Peripheral Frame 1 and Peripheral Frame 2 memory maps are restricted to data memory only User program cannot access these memory maps in program space C Protected means the order of Write followed by Read operations is preserved rather than the pipeline order D Certain memory ranges are EALLOW protected against spurious writes after configuration Figure 3 2 F2809 Memory Map 26 Funct
182. mers 0 1 2 Configuration and Control Registers continued NAME ADDRESS SIZE x16 DESCRIPTION Reserved 0x0C15 1 Reserved TIMER2TPR 0x0C16 1 CPU Timer 2 Prescale Register TIMER2TPRH 0x0C17 1 CPU Timer 2 Prescale Register High 0x0C18 Reserved 40 Reserved 4 2 Enhanced PWM Modules ePWM1 2 3 4 5 6 The 280x device contains up to six enhanced PWM Modules ePWM Figure 4 3 shows a block diagram of multiple ePWM modules Figure 4 4 shows the signal interconnections with the ePWM See the TMS320x280x 2801x 2804x Enhanced Pulse Width Modulator ePWM Module Reference Guide literature number SPRU791 for more details EPWM1SYNCI EPWM1SYNCI EPWM1INT EPWM1A EPWM1SOC ePWM1 module EPWM1B TZ1 to TZ6 to eCAP1 EPWM1SYNCO module 4 sync in EPWM1SYNCO EPWM2SYNCI EPWM2INT EPWM2A EPWM2SOC 2 module EPWM2B EPWM2SYNCO 12110 126 EPWMxSYNCI EPWMXxINT EPWMxA EPWMxSOC ePWMx module EPWMxB TZi to TZ6 EPWMxSYNCO to 126 ADCSOCx0 u Peripheral Bus ADC Figure 4 3 Multiple PWM Modules in a 280x System Table 4 2 shows the complete ePWM register set per module Copyright 2003 2009 Texas Instruments Incorporated Peripherals 55 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 T
183. ming Requirements 115 6 25 High Resolution PWM Characteristics at SYSCLKOUT 60 100 MHZ 116 6 26 Enhanced Capture eCAP Timing Requirement 44 24 41 1 nnne 116 6 27 eCAP Switching Characteristics 411 1 2 2 2 1 1 nene 116 6 28 Enhanced Quadrature Encoder Pulse eQEP Timing Requirements 116 6 29 eQEP Switching Characteristics 116 6 30 External ADC Start of Conversion Switching 2 1 117 6 31 External Interrupt Timing Requirements cesses nn II nnns nnne nnn 117 6 32 External Interrupt Switching Characteristics U U 117 6 33 Paene ecce 118 6 34 SPI Master Mode External Timing Clock Phase 0 11 1 0 119 6 35 SPI Master Mode External Timing Clock Phase 1 121 6 36 SPI Slave Mode External Timing Clock Phase 0 123
184. n read a data value and write a data value in a single cycle All peripherals and memories attached to the memory bus will prioritize memory accesses Generally the priority of memory bus accesses can be summarized as follows Highest Data Writes Simultaneous data and program writes cannot occur on the memory bus Program Writes Simultaneous data and program writes cannot occur on the memory bus Data Reads Program Simultaneous program reads and fetches cannot occur on the Reads memory bus Lowest Fetches Simultaneous program reads and fetches cannot occur on the memory bus 3 2 3 Peripheral Bus 34 To enable migration of peripherals between various Texas Instruments DSP family of devices the 280x devices adopt a peripheral bus standard for peripheral interconnect The peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals Two versions of the peripheral bus are supported on the 280x One version only supports 16 bit accesses called peripheral frame 2 The other version supports both 16 and 32 bit accesses called peripheral frame 1 Functional Overview Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS
185. nd system control features of the 280x digital signal processors DSPs Peripheral Guides SPRU566 SPRU716 SPRU791 Device Support TMS320x28xx 28xxx DSP Peripheral Reference Guide describes the peripheral reference guides of the 28x digital signal processors DSPs TMS320x280x 2801x 2804x DSP Analog to Digital Converter ADC Reference Guide describes how to configure and use the on chip ADC module which is a 12 bit pipelined ADC TMS320x280x 2801x 2804x Enhanced Pulse Width Modulator ePWM Module Reference Guide describes the main areas of the enhanced pulse width modulator that include digital motor control switch mode power supply control UPS uninterruptible power supplies and other forms of power conversion Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 5320 2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 TMS320F28015 5 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 INSTRUMENTS TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRU790 SPRU807 SPRU924 SPRUEUO SPRUFK7 SPRUG72 SPRU721 SPRU722 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 TMS320x280x 2801x 2804x Enhanced Quadrature Encoder Pulse eQEP Module Reference Guide describes the eQEP module which is used for interfacing with a linear or rotary incremental
186. nded that each target board be validated for proper operation of the debugger and the application FLASH VppavFL 96 C4 3 3 V Flash Core Power Pin This pin should be connected to 3 3 V at all times On the ROM parts C280x this pin should be connected to Vppio TESTI 97 A3 Test Pin Reserved for TI Must be left unconnected 1 TEST2 98 B3 Test Pin Reserved for TI Must be left unconnected 1 CLOCK XCLKOUT 66 E8 Output clock derived from SYSCLKOUT XCLKOUT is either the same frequency one half the frequency or one fourth the frequency of SYSCLKOUT This is controlled by the bits 1 0 XCLKOUTDIV in the XCLK register At reset XCLKOUT SYSCLKOUT 4 The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3 Unlike other GPIO pins the XCLKOUT pin is not placed in high impedance state during a reset O Z 8 mA drive XCLKIN 90 B5 External Oscillator Input This pin is used to feed a clock from an external 3 3 V oscillator In this case tie the X1 pin to GND Alternately when a crystal resonator is used or if an external 1 8 V oscillator is fed into the X1 pin tie the XCLKIN pin to GND 1 1 I Input Output Z High impedance OD Open drain 1 Pullup Pulldown Copyright 2003 2009 Texas Instruments Incorporated Introduction 19 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808
187. nected and the XCLKIN pin tied low The logic high level in this case should not exceed Vpp Copyright 2003 2009 Texas Instruments Incorporated Functional Overview 47 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com The three possible input clock configurations are shown in Figure 3 11 through Figure 3 13 XCLKIN x1 X2 External Clock Signal NC Toggling 0 Vppio Figure 3 11 Using a 3 3 V External Oscillator XCLKIN x1 x2 External Clock Signal NC Toggling 0 Vpp Figure 3 12 Using a 1 8 V External Oscillator XCLKIN X1 X2 n 5 Cu 2 Crystal Figure 3 13 Using the Internal Oscillator 3 6 1 1 External Reference Oscillator Clock Option The typical specifications for the external quartz crystal for a frequency of 20 MHz are listed below Fundamental mode parallel resonant C load capacitance 12 pF Cu Cu 24 pF Cshunt 6 pF ESR range 30 to 60 recommends that customers have the resonator crystal vendor characterize the operation of their device with the DSP chip The resonator crystal vendor has the equipment and expert
188. nennen nasum enses sensns nennen 34 3 2 4 Real Time JTAG and Analysis 1 4 4 4 1 2 41 nennen 35 3 2 5 IAS Meer 35 32 6 35 3 2 7 MT SARAMS uuu lu 35 2028 50 1 casts senses 36 929 JBoOL HOM 36 3 2 10 SCULLY 37 3 2 11 Peripheral Interrupt Expansion PIE Block 38 3 2 12 External Interrupts 1 XINT2 XNMI 38 32 18 Oscillator and AE AUR 38 3 2 14 Watchdog 44 22 2 46 EALE ENEKEN kaya unen nnn 38 3 2 15 Peripheral Clockin px Ese open M isuu suqqa 38 3 2 16 LOW Power Modes 38 3 2 17 Peripheral Frames 0 1 2 Rh RR 39 3 2 18 General Purpose Input Output GPIO Multiplexer
189. nnel Select Sequencing Control Register 2 ADCCHSELSEQ3 0x7105 1 ADC Channel Select Sequencing Control Register 3 ADCCHSELSEQ4 0x7106 1 ADC Channel Select Sequencing Control Register 4 ADCASEQSR 0x7107 1 ADC Auto Sequence Status Register ADCRESULTO 0x7108 0 0 00 1 ADC Conversion Result Buffer Register 0 ADCRESULT1 0x7109 0x0B01 1 ADC Conversion Result Buffer Register 1 ADCRESULT2 0 710 0x0B02 1 ADC Conversion Result Buffer Register 2 ADCRESULT3 0x710B 0x0B03 1 ADC Conversion Result Buffer Register 3 ADCRESULT4 0x710C 0x0B04 1 ADC Conversion Result Buffer Register 4 ADCRESULT5 0x710D 0 0 05 1 ADC Conversion Result Buffer Register 5 ADCRESULT6 Ox710E 0 0 06 1 ADC Conversion Result Buffer Register 6 ADCRESULT7 0x710F 0 0 07 1 ADC Conversion Result Buffer Register 7 ADCRESULT8 0x7110 0 0 08 1 ADC Conversion Result Buffer Register 8 ADCRESULT9 0 7111 0 0 09 1 ADC Conversion Result Buffer Register 9 ADCRESULT10 0 7112 Ox0BOA 1 ADC Conversion Result Buffer Register 10 ADCRESULT11 0x7113 OxOBOB 1 ADC Conversion Result Buffer Register 11 ADCRESULT12 0x7114 OxOBOC 1 ADC Conversion Result Buffer Register 12 ADCRESULT13 0 7115 OxOBOD 1 ADC Conversion Result Buffer Register 13 ADCRESULT14 0 7116 OxOBOE 1 ADC Conversion Result Buffer Register 14 ADCRESULT15 0 7117 OxOBOF 1 ADC Conversion Result Buffer Register 15 ADCTRL3 0x7118 1 ADC Control Register 3 ADCST 0x7119 1 ADC Status Register Reserved pim 2 Reserved ADCREFSEL Ox711C 1 ADC Reference Selec
190. ns in a single session Each conversion can be programmed to select any 1 of 16 input channels Sequencer can be operated as two independent 8 state sequencers or as one large 16 state sequencer i e two cascaded 8 state sequencers Sixteen result registers individually addressable to store conversion values The digital value of the input analog voltage is derived by Digital Value 0 when input x 0 V Input Analog Voltage ADCLO 3 Digital Value 4095 when input gt 3 V A All fractional values are truncated Multiple triggers as sources for the start of conversion SOC sequence SM software immediate start ePWM start of conversion XINT2 ADC start of conversion Flexible interrupt control allows interrupt request on every end of sequence EOS or every other EOS e Sequencer can operate in start stop mode allowing multiple time sequenced triggers to synchronize conversions SOCA SOCB triggers can operate independently in dual sequencer mode Sample and hold S H acquisition time window has separate prescale control Digital Value 4096 x when 0 V input 3 V The ADC module in the 280x has been enhanced to provide flexible interface to ePWM peripherals The ADC interface is built around a fast 12 bit ADC module with a fast conversion rate of up to 80 ns at 25 MHz ADC clock The ADC module has 16 channels configurable as two independent 8 channel modules The two independ
191. nto VppA2 and Vppalo 126 Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 Ron Switch Rs ADCINO 1kQ AAA ao Sorat T 28x DSP Typical Values of the Input Circuit Components Switch Resistance Ron 1kQ Sampling Capacitor Cr 1 64 pF Parasitic Capacitance 10 pF Source Resistance Rs 500 Figure 6 25 ADC Analog Input Impedance Model 6 10 7 2 Definitions Reference Voltage The on chip ADC has a built in reference which provides the reference voltages for the ADC Analog Inputs The on chip ADC consists of 16 analog inputs which are sampled either one at a time or two channels at atime These inputs are software selectable Converter The on chip ADC uses a 12 bit four stage pipeline architecture which achieves a high sample rate with low power consumption Conversion Modes The conversion can be performed in two different conversion modes Sequential sampling mode SMODE 0 Simultaneous sampling mode SMODE 1 Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 127 Submit Documentation Fee
192. nts TMS320F2809 TMS320F2808 TMS320F2806 5320 2802 5320 2801 5320 2802 5320 2801 TMS320F28015 and 5320 28016 100 PZ low profile quad flatpack LQFP assignments are shown in Figure 2 1 Figure 2 2 Figure 2 3 and Figure 2 4 The 100 ball GGM and ZGM ball grid array BGA terminal assignments are shown in Figure 2 5 Table 2 3 describes the function s of each pin TDO Vss XRS GPIO27 ECAPA EQEP2S SPISTEB EMUO EMU1 Vppio GPIO24 ECAP1 EQEP2A SPISIMOB TRST Vpp x2 Vss Vss XCLKIN GPIO25 ECAP2 EQEP2B SPISOMIB GPIO28 SCIRXDA TZ5 Vpp Vss GPIO13 TZ2 CANRXB SPISOMIB VppavrFL TEST1 TEST2 GPIO26 ECAP3 EGEP2I SPICLKB GPIO32 SDAA EPWMSYNCI ADCSOCAO TCK GPIO10 EPWM6A CANRXB ADCSOCBO GPIO20 EQEP1 A SPISIMOC CANTXB GPIO6 EPWM4A EPWMSYNCI EPWMSYNCO Vss Vss GP1IO8 EPWM5A CANTXB ADCSOCAO GP1023 EQEP1I SPISTEC SCIRXDB GPIO22 EQEP1S SPICLKC SCITXDB Vpp GP1011 EPWM6B SCIRXDB ECAP4 Vss Vpp GPIO21 EQEP1B SPISOMIC CANRXB XCLKOUT Vppio GPIO9 EPWMSB SCITXDB ECAP3 GPIO7 EPWM4B SPISTED ECAP2 GPIO19 SPISTEA SCIRXDB TMS TDI GPIO18 SPICLKA SCITXDB GPIO5 EPWM3B SPICLKD ECAP1 GPIO17 SPISOMIA CANRXB TZ6 GPIO4 EPWMS3A GPIO12 TZ1 CANTXB SPISIMOB Vss Vppio GPIO29 SCITXDA TZ6 GPIO33 SCLA EPWMSYNCO ADCSOCBO Vpp Vss Vpp1A18 Vss1AGND Vppa2 ADCINA7 ADCINA6 ADCINA5 ADCINA4 ADCINA3 ADCINA2 GPIO30 CANRXA GPIO31 CANTXA
193. oading on the I O pins 2 The _ current indicated in this table is the flash read current and does not include additional current for erase write operations During flash programming extra current is drawn from the Vpp and Vppavyr rails as indicated in Table 6 45 If the user application involves on board flash programming this extra current must be taken into account while architecting the power supply stage 3 18 includes current into Vpp1A18 and Vppeaig pins In order to realize the currents shown for IDLE STANDBY and HALT clock to the ADC module must be turned off explicitly by writing to the PCLKCRO register 4 includes current into and pins 5 TYP numbers are applicable over room temperature and nominal voltage 6 MAX numbers are at 125 C and MAX voltage NOTE The peripheral multiplexing implemented in the 280x devices prevents all available peripherals from being used at the same time This is because more than one peripheral function may share an pin It is however possible to turn on the clocks to all the peripherals at the same time although such a configuration is not useful If this is done the current drawn by the device will be more than the numbers specified in the current consumption tables Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 97 Submit Documentation Feedback Product Fold
194. ock 12 5 MSPS 2 LSB DNL Differential nonlinearity 9 1 LSB Offset error 60 60 LSB Offset error with hardware trimming 4 LSB Overall gain error with internal reference 9 60 60 LSB Overall gain error with external reference 60 60 LSB Channel to channel offset variation 4 LSB Channel to channel gain variation 4 LSB ANALOG INPUT Analog input voltage ADCINx to ADCLO 0 3 V ADCLO 5 0 5 mV Input capacitance 10 pF Input leakage current 5 INTERNAL VOLTAGE REFERENCE 9 VapcnerP ADCREFP output voltage at the pin 1 275 V based on internal reference VapcRErM ADCREFM output voltage at the pin 0 525 V based on internal reference Voltage difference ADCREFP ADCREFM 0 75 V Temperature coefficient 50 EXTERNAL VOLTAGE REFERENCE 7 Vapcrerin External reference voltage input on ADCREFSEL 15 14 11b 1 024 V ADCREFIN pin 0 2 or better accurate ADCREFSEL 15 14 10b 1 500 V recommended ADCREFSEL 15 14 016 2 048 V AC SPECIFICATIONS SINAD 100 kHz Signal to noise ratio 4 67 5 dB distortion SNR 100 kHz Signal to noise ratio 68 dB THD 100 kHz Total harmonic distortion 79 dB ENOB 100 kHz Effective number of bits 10 9 Bits SFDR 100 kHz Spurious free dynamic range 83 dB 1 Tested at 12 5 MHz ADCCLK 2 All voltages listed in this table are with respect to Vasa 3 Tl specifies that the ADC will have no missing codes 4 1 LSB has the weighted value of 3 0 4096 0 732 mV 5 Asingle internal ext
195. ode ensures that all accesses to these blocks happen as written Because of the C28x pipeline a write immediately followed by a read to different memory locations will appear in reverse order on the memory bus of the CPU This can cause problems in certain peripheral applications where the user expected the write to occur first as written The C28x CPU supports a block protection mode where a region of memory can be protected so as to make sure that operations occur as written the penalty is extra cycles are added to align the operations This mode is programmable and by default it will protect the selected zones 32 Functional Overview Submit Documentation Feedback Copyright 2003 2009 Texas Instruments Incorporated Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 5320 2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 TMS320F28015 5 INSTRUMENTS www ti com TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 The wait states for the various spaces in the memory map area are listed in Table 3 6 Table 3 6 Wait states AREA WAIT STATES COMMENTS MO and M1 SARAMs 0 wait Fixed Peripheral Frame 0 0 wait Fixed Peripheral Frame 1 0 wait writes 2 wait reads Fixed The eCAN peripheral can extend a cycle as needed Back to back writes will introduce a
196. oducts and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement t
197. om SPRM444 2809 ZGM IBIS Model SPRM291 F2808 GGM IBIS Model SPRM292 F2808 PZ IBIS Model SPRM293 F2808 ZGM IBIS Model SPRM288 F2806 GGM IBIS Model SPRM289 F2806 PZ IBIS Model SPRM290 2806 ZGM IBIS Model SPRM285 2802 GGM IBIS Model SPRM286 F2802 PZ IBIS Model SPRM287 F2802 ZGM IBIS Model SPRM282 F2801 GGM IBIS Model SPRM283 F2801 PZ IBIS Model SPRM284 2801 ZGM IBIS Model SPRM310 C2802 GGM IBIS Model SPRM449 C2802 PZ IBIS Model SPRM311 C2802 ZGM IBIS Model SPRM308 C2801 GGM IBIS Model SPRM448 C2801 PZ IBIS Model SPRM309 C2801 ZGM IBIS Model 405 28016 GGM IBIS Model SPRM300 F28016 PZ IBIS Model SPRM404 F28016 ZGM IBIS Model SPRM403 F28015 GGM IBIS Model SPRM299 F28015 PZ IBIS Model SPRM402 F28015 ZGM IBIS Model A series of DSP textbooks is published by Prentice Hall and John Wiley amp Sons to support digital signal processing research and education The 5320 DSP newsletter Details on Signal Processing is published quarterly and distributed to update TMS320 DSP customers on product information Updated information on the TMS320 DSP controllers can be found on the worldwide web at http www ti com To send comments regarding this data manual literature number SPRS230 use the comments books sc ti com email address which is a repository for feedback For questions and support contact the Product Information Center listed at the http www ti com sc docs pic home htm site 92 Device Support
198. on date Products conform to specifications per the terms of the Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters Copyright 2003 2009 Texas Instruments Incorporated TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 1 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com Package Options Temperature Options Thin Quad Flatpack PZ A 40 C to 85 C PZ GGM ZGM MicroStar BGA GGM ZGM 40 C to 125 C PZ GGM ZGM Q 40 C to 125 C PZ 1 2 Getting Started This section gives a brief overview of the steps to take when first developing for a C28x device For more detail on each of these steps see the following Getting Started With TMS320C28x Digital Signal Controllers literature number SPRAAMO e C2000 Getting Started Website http www ti com c2000getstarted Step 1 Acquire the appropriate development tools The quickest way to begin working with a C28x device is to acquire an eZdsp kit for initial development which in one package includes e On board JTAG emulation via USB or parallel port Appropriate emulation driver Code Composer Studio IDE for eZdsp Once you have become familiar with the device and begin developing on your own hardware purchase Code Composer Studio IDE separately for software development and a JTAG emul
199. onnect to Vss e ADCLO Connect to Vss e ADCREFIN Connect to Vss ADCREFP ADCREFM Connect a 100 nF cap to Vss e ADCRESEXT Connect 20 kO resistor very loose tolerance to e ADCINAn ADCINBn Connect to Vss When the ADC is not used be sure that the clock to the ADC module is not turned on to realize power savings When the ADC module is used in an application unused ADC input pins should be connected to analog ground VssiAGND Vss2AGND Peripherals Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 5 INSTRUMENTS www ti com 4 6 2 ADC Registers TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 The ADC operation is configured controlled and monitored by the registers listed in Table 4 5 Table 4 5 ADC Registers NAME ADDRESS ADDRESS SIZE x16 DESCRIPTION ADCTRL1 0x7100 1 ADC Control Register 1 ADCTRL2 0x7101 1 ADC Control Register 2 ADCMAXCONV 0 7102 1 ADC Maximum Conversion Channels Register ADCCHSELSEQ1 0x7103 1 ADC Channel Select Sequencing Control Register 1 ADCCHSELSEQ2 0x7104 1 ADC Cha
200. ontains up to four enhanced capture eCAP modules Figure 4 5 shows a functional block diagram of a module See the TMS320x280x 2801x 2804x Enhanced Capture eCAP Module Reference Guide literature number SPRU807 for more details The eCAP modules are clocked at the SYSCLKOUT rate The clock enable bits ECAP1 2 3 4ENCLK in the register are used to turn off the eCAP modules individually for low power operation Upon reset ECAP1ENCLK ECAP2ENCLK ECAP3ENCLK and ECAPAENCLK are set to low indicating that the peripheral clock is off 58 Peripherals Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 l arenes TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 CTRPHS phase register 32 bit APWM mode SYNCIn ovr CTR_OVF _ SYNCOut TSCTR 0 31 counter 32 bit Delta mode PRD 0 31 compare logic CMP 0 31 32 mer PRD 0 31 Sa eCAPx CAP1 Polarity active LD 32 CMP 0 31 CAP2 LD4 Polarity ACMP active select Event qualifier Event Pre scale Polarity select CAP3 APRD shadow 0 CAP4 ACMP shadow 0 Cap
201. or and status CANTEC 0x601A 0x621A 1 Transmit error counter CANREC 0x601C 0x621C 1 Receive error counter CANGIFO 0x601E 0 621 1 Global interrupt flag 0 CANGIM 0x6020 0x6220 1 Global interrupt mask CANGIF1 0x6022 0 6222 1 Global interrupt flag 1 CANMIM 0x6024 0x6224 1 Mailbox interrupt mask CANMIL 0x6026 0 6226 1 Mailbox interrupt level CANOPC 0x6028 0x6228 1 Overwrite protection control CANTIOC 0x602A 0x622A 1 TX I O control CANRIOC 0x602C 0x622C 1 RX control CANTSC 0x602E 0 622 1 Time stamp counter Reserved SCC mode 0 6030 0 6230 1 Time out control Reserved in SCC mode CANTOS 0x6032 0x6232 1 Time out status Reserved in SCC mode 1 These registers are mapped to Peripheral Frame 1 72 Peripherals Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 4 8 Serial Communications Interface SCI Modules SCI A SCI B The 280x devices include two serial communications interface SCI modules The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non return to zero NRZ format The SCI receiver and transmitter are double buffered and e
202. p Enhanced input A I SPISOMIC SPI C master in slave out not available on 2801 2802 I O CANRXB Enhanced CAN B receive not available on 2801 2802 F2806 I GPIO22 General purpose input output 22 1 O Z 9 EQEP1S 71 08 Enhanced 1 strobe I O SPICLKC SPI C clock not available on 2801 2802 I O SCITXDB SCI B transmit not available on 2801 2802 O GPIO23 General purpose input output 23 1 O Z 9 72 10 Enhanced QEP1 index I O SPISTEC SPI C slave transmit enable not available on 2801 2802 I O SCIRXDB SCI B receive 1 not available on 2801 2802 GPIO24 General purpose input output 24 1 0 2 9 ECAP1 83 C7 Enhanced capture 1 EQEP2A Enhanced input A I not available on 2801 2802 SPISIMOB SPI B slave in master out I O GPIO25 General purpose input output 25 I O Z 9 ECAP2 91 C5 Enhanced capture 2 I O EQEP2B Enhanced input B I not available on 2801 2802 SPISOMIB SPI B master in slave out I O GPIO26 General purpose input output 26 1 0 2 9 99 A2 Enhanced capture 3 not available on 2801 2802 EQEP2I Enhanced index I O not available on 2801 2802 SPICLKB SPI B clock I O GPIO27 General purpose input output 27 1 0 2 9 ECAP4 79 Enhanced capture 4 I O not available 2801 2802 EQEP2S Enhanced QEP2 strobe I O not available on 2801 2802 SPISTEB SPI B slave transmit enable I O GPIO28 General purpose input ou
203. pability The GPIO MUX block diagram per pin is shown in Figure 4 16 Because of the open drain capabilities of the 2 pins the GPIO MUX block diagram for these pins differ See the TMS320x280x 2801x 2804x DSP System Control and Interrupts Reference Guide literature number SPRU712 for details GPIOLMPSEL LPMCRO Low Power Modes Block GPIOXINT1SEL GPIOXINT2SEL GPIOXNMISEL External Interrupt MUX Asynchronous path GPxDAT read N C Peripheral 1 Input Input Qualification Peripheral 2 Input Peripheral 3 Input GPxTOGGLE Asynchronous path GPxCLEAR GPxSET GPxDAT latch Peripheral 1 Output High Impedance Output Control GPxDIR latch Peripheral 1 Output Enable 0 Input 1 Output X C ow Peripheral 2 Output Enable Peripheral 3 Output Enable z Default at Reset GPxMUX1 2 A x stands for the port either A or B For example GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular GPIO pin selected B GPxDAT latch read are accessed at the same memory location Figure 4 16 GPIO MUX Block Diagram 82 Peripherals Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806
204. plementation of a power line modem following CEA 709 protocol using a single DSP TMS320x280x and TMS320F2801x ADC Calibration describes a method for improving the absolute accuracy of the 12 bit ADC found on the TMS320x280x and TMS320F2801x devices Inherent gain and offset errors affect the absolute accuracy of the ADC The Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 methods described in this report can improve the absolute accuracy of the ADC to levels better than 0 596 This application report has an option to download an example program that executes from RAM on the F2808 EzDSP SPRA820 Online Stack Overflow Detection on the TMS320C28x DSP presents the methodology for online stack overflow detection on the TMS320C28x DSP C source code is provided that contains functions for implementing the overflow detection on both DSP BIOS and non DSP BIOS applications 5 806 An Easy Way of Creating a C callable Assembly Function for the TMS320C28x DSP provides instructions and suggestions to configure the C compiler to assist with C callable assembly routines SPRAA58 TMS320x281x to TMS320x280x Migration Overview descri
205. polarity 0 twSPCH SIMO M Valid time SPISIMO data valid after 0 5tespcym 10 O 5tcsPc M 0 5 10 SPICLK high clock polarity 1 tsu SOMI SPCL M Setup time SPISOMI before SPICLK 35 35 8 low clock polarity 0 is tsu SOMI SPCH M Setup time SPISOMI before SPICLK 35 35 high clock polarity 1 tv SPCL SOMI M Valid time SPISOMI data valid after 0 25tcsPc M 10 O 5tctsPC M 0 5te Lco 10 SPICLK low clock polarity 0 tv SPCH SOMI M Valid time SPISOMI data valid after 0 25tc sPC M 10 O 5tc sPC M 0 5 10 SPICLK high clock polarity 1 The MASTER SLAVE bit SPICTL 2 is set and the CLOCK PHASE bit SPICTL 3 is cleared 5 SPI clock cycle time LSPCLK 4 or LSPCLK SPIBRR 1 teco LSPCLK cycle time Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate Master mode transmit 25 MHz MAX master mode receive 12 5 MHz MAX Slave mode transmit 12 5 MAX slave mode receive 12 5 MHz MAX 5 The active edge of the SPICLK signal referenced is controlled by the clock polarity bit SPICCR 6 anann BRON aH Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 Electrical Specifications 119 TMS320F2809 TMS3
206. r 0 Counter Register TIMEROTIMH 0x0C01 1 CPU Timer 0 Counter Register High TIMEROPRD 0x0C02 1 CPU Timer 0 Period Register TIMEROPRDH 0x0C03 1 CPU Timer 0 Period Register High TIMEROTCR 0x0C04 1 CPU Timer 0 Control Register Reserved 0x0C05 1 Reserved TIMEROTPR 0x0C06 1 CPU Timer 0 Prescale Register TIMEROTPRH 0 0 07 1 CPU Timer 0 Prescale Register High TIMER1TIM 0x0C08 1 CPU Timer 1 Counter Register TIMER1TIMH 0x0C09 1 CPU Timer 1 Counter Register High TIMER1PRD 1 CPU Timer 1 Period Register TIMER1PRDH OxOCOB 1 CPU Timer 1 Period Register High TIMER1TCR 0x0C0G 1 CPU Timer 1 Control Register Reserved 0x0C0D 1 Reserved TIMER1TPR 0x0C0E 1 CPU Timer 1 Prescale Register TIMER1TPRH 0x0C0F 1 CPU Timer 1 Prescale Register High TIMER2TIM 0x0C10 1 CPU Timer 2 Counter Register TIMER2TIMH 0x0C11 1 CPU Timer 2 Counter Register High TIMER2PRD 0x0C12 1 CPU Timer 2 Period Register TIMER2PRDH 0x0C13 1 CPU Timer 2 Period Register High TIMER2TCR 0x0C14 1 CPU Timer 2 Control Register 54 Peripherals Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 5 INSTRUMENTS www ti com TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 CPU Ti
207. r polled algorithms Nine SPI module control registers Located in control register frame beginning at address 7040h NOTE All registers in this module are 16 bit registers that are connected to Peripheral Frame 2 When a register is accessed the register data is in the lower byte 7 0 and the upper byte 15 8 is read as zeros Writing to the upper byte has no effect Enhanced feature 16 level transmit receive FIFO Delayed transmit control Peripherals Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 5 INSTRUMENTS www ti com TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 The SPI port operation is configured and controlled by the registers listed in Table 4 10 through Table 4 13 Table 4 10 SPI A Registers NAME ADDRESS SIZE x16 DESCRIPTION SPICCR 0x7040 1 SPI A Configuration Control Register SPICTL 0x7041 1 SPI A Operation Control Register SPISTS 0x7042 1 SPI A Status Register SPIBRR 0x7044 1 SPI A Baud Rate Register SPIRXEMU 0x7046 1 SPI A Receive Emulation Buffer Register SPIRXBUF 0x7047 1 SPI A Serial Input Buf
208. r user applications The paged and random wait state specifications for the Flash and ROM parts are different While migrating from Flash to ROM parts the same wait state values must be used for best performance compatibility for example in applications that use software delay loops or where precise interrupt latencies are critical The analog input switch resistance is smaller in C280x devices compared to F280x devices While migrating from a Flash to a ROM device care should be taken to design the analog input circuits to meet the application performance required by the sampling network The PART ID register value is different for Flash and ROM parts From a silicon functionality errata standpoint rev A ROM devices are equivalent to rev C flash devices See the errata applicable to 280x devices for details As part of the ROM code generation process all unused memory locations in the customer application are automatically filled with OxFFFF Unused locations should not be manually filled with any other data For errata applicable to 280x devices see the TMS320F280x TMS320C280x and TMS320F2801x DSC Silicon Errata literature number SPRZ171 Copyright 2003 2009 Texas Instruments Incorporated Migrating From F280x Devices to C280x Devices 133 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 5320 28015 TMS320F2809 TMS32
209. ramming extra current is drawn from the Vpp and VppsvF involves on board flash programming this extra current must be taken into account while architecting the power supply stage 3 includes current into Vpp1aig and Vpp2a18 pins In order to realize the Ippaig currents shown for IDLE STANDBY and HALT clock to the ADC module must be turned off explicitly by writing to the PCLKCRO register lppass includes current into and Vppaio pins 5 TYP numbers are applicable over room temperature and nominal voltage 6 MAX numbers are at 125 C and MAX voltage NOTE The peripheral multiplexing implemented in the 280x devices prevents all available peripherals from being used at the same time This is because more than one peripheral function may share pin It is however possible to turn on the clocks to all the peripherals at the same time although such a configuration is not useful If this is done the current drawn by the device will be more than the numbers specified in the current consumption tables 96 Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 5320 2801 5320 28016 5320 28015 L rails as indicated Table 6 45 If the user application TMS320F2809 TMS320F2808 TMS320F2806 Texas TMS320F280
210. rence Medium Output ADCREFM be loaded by external circuitry Vpp1A18 Analog Power Pin 1 8 V Vpp2A18 ADC Analog Power Pin 1 8 V ADC Analog Power Vss1AGND ADC Analog Ground Pin Vss2AGND ADC Analog Ground Pin VppA2 ADC Analog Power Pin 3 3 V VssA2 ADC Analog Ground Pin VpDAIO ADC Analog Power Pin 3 3 V ADC Analog and Reference Power ADC Analog Ground Pin TAIYO YUDEN LMK212BJ225MG T or equivalent External decoupling capacitors are recommended on all power pins Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance External voltage on ADCREFIN is enabled by changing bits 15 14 in the ADC Reference Select register depending on the voltage used on this recommends part REF3020 or equivalent for 2 048 V generation Overall gain accuracy will be determined by accuracy of this voltage source Figure 4 9 ADC Pin Connections With External Reference NOTE The temperature rating of any recommended component must match the rating of the end product 4 601 ADC Connections if the ADC Is Not Used 66 It is recommended to keep the connections for the analog power pins even if the ADC is not used Following is a summary of how the ADC pins should be connected if the ADC is not used in an application Connect to Vpp Vbpaz Vppaio Connect to Vppio VssiAGND Vss2AGND Vssae Vssaio C
211. rpose input output 10 1 O Z EPWM6A 64 10 Enhanced PWM6 output A HRPWM channel not available 2801 2802 CANRXB Enhanced CAN B receive not available on 2801 2802 F2806 I ADCSOCBO ADC start of conversion B O GPIO11 General purpose input output 11 2 EPWM6B 70 Enhanced PWM6 output not available 2801 2802 SCIRXDB SCI B receive data not available on 2801 2802 1 ECAP4 Enhanced CAP Input Output 4 not available on 2801 2802 I O GPIO12 General purpose input output 12 1 O Z 9 TZ1 1 B2 Trip Zone input 1 I CANTXB Enhanced CAN B transmit not available on 2801 2802 F2806 O SPISIMOB SPI B Slave in Master out I O GPIO13 General purpose input output 13 1 O Z 9 TZ2 95 B4 Trip zone input 2 1 CANRXB Enhanced CAN B receive not available on 2801 2802 F2806 I SPISOMIB SPI B slave out master in I O GPIO14 General purpose input output 14 1 0 2 9 TZ3 8 D3 Trip zone input 3 1 SCITXDB SCI B transmit not available on 2801 2802 O SPICLKB SPI B clock input output I O GPIO15 General purpose input output 15 1 O Z 9 TZ4 9 E1 Trip zone input 1 SCIRXDB SCI B receive not available on 2801 2802 I SPISTEB slave transmit enable I O GPIO16 General purpose input output 16 1 O Z 9 SPISIMOA 50 K10 SPI A slave in master out I O CANTXB Enhanced CAN B transmit not available on 2801 2802 F2806 O TZ5 Trip zone input 5 I GPIO17 General purpose input outpu
212. rrupts 43 interrupts are currently used The remaining interrupts are reserved for future devices These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level provided none of the interrupts within the group is being used by a peripheral Otherwise interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR To summarize there are two safe cases when the reserved interrupts could be used as software interrupts 1 No peripheral within the group is asserting interrupts 2 No peripheral interrupts are assigned to the group example PIE group 12 44 Functional Overview Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 Pen MENG TMS320C2801 TMS320F28016 TMS320F28015 Table 3 13 PIE Configuration and Control Registers NAME ADDRESS SIZE x16 DESCRIPTION PIECTRL OxOCEO 1 PIE Control Register PIEACK OxOCE1 1 PIE Acknowledge Register PIEIER1 2 1 PIE INT1 Group Enable Register PIEIFR1 1 PIE INT1 Group Flag Register PIEIER2 0x0CE4 1 PIE INT2 Group Enable Register PIEIFR2 0x0CE5
213. rupt lines INT1 to INT12 Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that can be overwritten by the user The vector is automatically fetched by the CPU on servicing the interrupt It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers Hence the CPU can quickly respond to interrupt events Prioritization of interrupts is controlled in hardware and software Each individual interrupt can be enabled disabled within the PIE block 3 2 12 External Interrupts XINT1 XINT2 XNMI The 280x supports three masked external interrupts XINT1 XINT2 XNMI XNMI can be connected to the INT13 or NMI interrupt of the CPU Each of the interrupts can be selected for negative positive or both negative and positive edge triggering and can also be enabled disabled including the XNMI The masked interrupts also contain a 16 bit free running up counter which is reset to zero when a valid interrupt edge is detected This counter can be used to accurately time stamp the interrupt Unlike the 281x devices there are no dedicated pins for the external interrupts Rather any Port A GPIO pin can be configured to trigger any external interrupt 3 2 13 Oscillator and PLL The 280x can be clocked by an external oscillator or by a crystal attached to the on chip oscillator circuit A PLL is provided supporting up to 10 input clock scaling ratios The PLL ratios can be changed on the fly in software enab
214. ry 1 18 ADC Analog Power Pin 1 8 V Vpp2A18 ADC Analog Power Pin 1 8 V ADG Powei Vss1AGND ADC Analog Ground Pin Vss2AGND ADC Analog Ground Pin VppA2 ADC Analog Power Pin 3 3 V Vssa2 ADC Analog Ground Pin ADC Analog and Reference I O Power VpDAIO I ADC Analog Power Pin 3 3 V VssAIO ADC Analog Ground Pin A TAIYO YUDEN LMK212BJ225MG T or equivalent External decoupling capacitors are recommended on all power pins C Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance Figure 4 8 ADC Pin Connections With Internal Reference w Copyright 2003 2009 Texas Instruments Incorporated Peripherals 65 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 ee SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com ADCINA 7 0 ADCINB 7 0 ADCLO ADCREFIN ADC 16 Channel Analog Inputs Analog input 0 3 V with respect to ADCLO Connect to Analog Ground Connect to 1 500 1 024 or 2 048 V precision source D 22 ADC External Current Bias Resistor ADCRESEXT 2 2 uF ADC Reference Positive Output ADCREFP 2 2 uF ADCREFP and ADCREFM should not ADC Refe
215. ry and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific products are designated by as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier t
216. s of Flash Sectors in F2806 F2802 ADDRESS RANGE PROGRAM AND DATA SPACE 0000 OxSF 1FFF Sector D 8K x 16 2000 OxSF Sector C 8K x 16 4000 OxSF 5 Sector B 8K x 16 6000 OxSF 7F7F 7F80 OxSF 7FF5 Ox3F 7FF6 OxSF 7FF7 Ox3F 7FF8 OxSF 7FFF Sector A 8K x 16 Program to 0x0000 when using the Code Security Module Boot to Flash Entry Point program branch instruction here Security Password 128 Bit Do not program to all zeros Copyright 2003 2009 Texas Instruments Incorporated Functional Overview 31 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 TEXAS INSTRUMENTS www ti com Table 3 4 Addresses of Flash Sectors in F2801 F28015 F28016 ADDRESS RANGE PROGRAM AND DATA SPACE 4000 OxSF 4FFF Sector D 4K x 16 5000 5FFF Sector C 4K x 16 6000 OxSF 6FFF Sector B 4K x 16 7000 OxSF 7F7F Sector A 4K x 16 7F80 OxSF 7FF5 7FF6 OxSF 7FF7 Program to 0x0000 when using the Co
217. si 1 requirement XRS has to be low at least for 1 ms after Vpp reaches 1 5 V Dependent on crystal resonator and board design _ ad X Z 4 LS Nat N N Z XCLKOUT OSCCLK 8 x User Code Dependent OSCCLK 5 0 5 U t ser Code Execution Phase Address Data ODD TETTE vm Internal Boot ROM Execution Starts th boot mode Boot Mode 6 Function X us Ba Peripheral GPIO Function GPIO Pins as Input Peripheral GPIO Function User Code Execution Starts Pins User Code Dependent GPIO Pins as Input State Depends on Internal PU PD User Code Dependent A After reset the Boot ROM code samples BOOT Mode pins Based on the status of the Boot Mode pin the boot code branches to destination memory or boot code function If Boot ROM code executes after power on conditions in debugger environment the Boot code execution time is based on the current SYSCLKOUT speed The SYSCLKOUT will be based on user environment and could be with or without PLL enabled Figure 6 9 Warm Reset Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802
218. state must be greater than or equal to 1 132 Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 Texas TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 7 Migrating From F280x Devices to C280x Devices 7 1 Migration Issues The migration issues to be considered while migrating from the F280x devices to 280 devices as follows The 1K OTP memory available in F280x devices has been replaced by 1K ROM C280x devices Current consumption differs for F280x and C280x devices for all four possible modes See the appropriate electrical section for exact numbers The pin is the 3 3 V Flash core power pin F280x devices but is Vppio pin C280x devices F280x and C280x devices are pin compatible and code compatible however they are electrically different with different EMI ESD profiles Before ramping production with C280x devices evaluate performance of the hardware design with both devices Addresses Ox3D 7BFC through Ox3D 7BFF in the OTP and addresses 7FFO through Ox3F 7FF5 in the main ROM array are reserved for ROM part specific information and are not available fo
219. struments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 Predictions show that prototype devices TMX or TMP have a greater failure rate than the standard production devices Texas Instruments recommends that these devices not be used in any production system because their expected end use failure rate still is undefined Only qualified production devices are to be used TI device nomenclature also includes a suffix with the device family name This suffix indicates the package type for example GGM and temperature range for example A Figure 5 1 provides a legend for reading the complete device name for any family member TMS 320 F 28015 7 A 60 PREFIX ee Indicates 60 MHz device ae Absence of 60 indicates MHz device TMS Qualified Device 100 Mhiz device TEMPERATURE RANGE 40 C to 85 40 10125 524 Eu Q 40 Cto 125 C 0100 Qualification PACKAGE TYPE PZ 100 Pin Low Profile Quad Flatpack LQFP GGM 100 Ball Ball Grid Array BGA ZGM 100 Ball Lead Free BGA TECHNOLOGY F Flash EEPROM DEVICE 1 8 V Core 3 3 V 1 0 2809 C ROM 50 1 8 V Core 3 3 V 1 8 V Core 3 3 V I O 2802
220. t 10 gt lt n spisom Mast MSE A In the master mode SPISTE goes active O 5t spc minimum before valid SPI clock edge On the trailing end of the word the SPISTE will go inactive O 5tc spc after the receiving edge SPICLK of the last data bit except that SPISTE stays active between back to back transmit words in both FIFO and non FIFO modes Figure 6 21 SPI Master Mode External Timing Clock Phase 1 122 Electrical Specifications Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 TMS320F2802 TMS320F2801 5320 2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 Texas TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 6 10 6 SPI Slave Mode Timing Table 6 36 lists the slave mode external timing clock phase 0 and Table 6 37 clock phase 1 Figure 6 22 and Figure 6 23 show the timing waveforms Table 6 36 SPI Slave Mode External Timing Clock Phase 0 9 9 4 6 NO MIN MAX UNIT 12 tc sPc s Cycle time SPICLK A4tc LCO ns 13 tw SPCH S Pulse duration SPICLK high clock polarity 0 O 5tespcjs 10 0 5tgspc s tw SPCL S Pulse duration SPICLK low clock polarity 1 0 5tspcjs 10 0
221. t HALT Turns off the internal oscillator This mode basically shuts down the device and places it in the lowest possible power consumption mode A reset or external signal can wake the device from this mode 38 Functional Overview Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 Texas TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 3 2 17 Peripheral Frames 0 1 2 PFn The 280x segregate peripherals into three sections The mapping of peripherals is as follows PFO PIE PIE Interrupt Enable and Control Registers Plus PIE Vector Table Flash Flash Control Programming Erase Verify Registers Timers CPU Timers 0 1 2 Registers CSM Code Security Module KEY Registers ADC ADC Result Registers dual mapped PF1 eCAN eCAN Mailbox and Control Registers GPIO GPIO MUX Configuration and Control Registers ePWM Enhanced Pulse Width Modulator Module and Registers eCAP Enhanced Capture Module and Registers eQEP Enhanced Quadrature Encoder Pulse Module and Registers PF2 SYS System Control Registers SCI Serial Communications Interface SCI Control and RX TX Registers SPI Serial Port Interface SPI Control and RX TX Registers
222. t 17 1 0 2 9 SPISOMIA 52 J10 SPI A slave out master in I O CANRXB Enhanced CAN B receive not available on 2801 2802 F2806 I TZ6 Trip zone input 6 GPIO18 General purpose input output 18 1 O Z 9 SPICLKA SPI A clock input output 1 SCITXDB 54 H8 SCI B transmit not available on 2801 2802 O GPIO19 General purpose input output 19 I O Z 9 SPISTEA SPI A slave transmit enable input output I O SCIRXDB 57 G10 5 receive not available on 2801 2802 1 5 The pullups on GPIO12 GPIO34 are enabled upon reset 22 Introduction Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 5320 2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 TMS320F28015 5 INSTRUMENTS www ti com TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Signal Descriptions continued PIN NO NAME pz GGM DESCRIPTION PIN ZGM BALL GPIO20 General purpose input output 20 I O Z 9 EQEP1A 6 pg Enhanced QEP1 input A 1 SPISIMOC SPI C slave in master out not available on 2801 2802 I O CANTXB Enhanced CAN B transmit not available on 2801 2802 F2806 O GPIO21 General purpose input output 21 I O Z 9 EQEP1B 67
223. t Register ADCOFFTRIM 0x711D 1 ADC Offset Trim Register Reserved 1 7 F 2 Reserved 1 The registers in this column are Peripheral Frame 2 Registers 2 The ADC result registers are dual mapped in the 280x DSP Locations in Peripheral Frame 2 0x7108 0x7117 are 2 wait states and left justified Locations in Peripheral frame 0 space 0x0B00 0xOBOF are 0 wait sates and right justified During high speed continuous conversion use of the ADC use the 0 wait state locations for fast transfer of ADC results to user memory Copyright 2003 2009 Texas Instruments Incorporated Peripherals 67 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 NSTRUMENTS SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 4 7 Enhanced Controller Area Network eCAN Modules and eCAN B The CAN module has the following features Fully compliant with CAN protocol version 2 0B Supports data rates up to 1 Mbps Thirty two mailboxes each with the following properties Configurable as receive or transmit Configurable with standard or extended identifier Has a programmable receive mask Supports data and remote frame Composed of 0 to 8 bytes of data Uses a 32 bit time stamp on receive
224. tegrated Circuit I2C 0 2 2 2 2 Digital I O pins shared 35 35 35 35 External interrupts 3 3 3 3 Supply voltage AV VO petro Packagino 100 Pin PZ Yes Yes Yes Yes 100 Ball GGM ZGM Yes Yes Yes Yes 40 to 85 C PZ GGM ZGM PZ GGM ZGM PZ GGM ZGM PZ GGM ZGM Temperature options S 40 C to 125 C PZ GGM ZGM PZ GGM ZGM PZ GGM ZGM PZ GGM ZGM 40 C to 125 C PZ PZ PZ PZ Product status TMS TMS TMS TMS 1 A type change represents a major functional feature difference a peripheral module Within a peripheral type there be minor differences between devices that do not affect the basic functionality of the module These device specific differences are listed in the TMS320x28xx 28xxx DSP Peripheral Reference Guide literature number SPRU566 and in the peripheral reference guides 2 See Section 5 1 Device and Development Support Tool Nomenclature for descriptions of device stages Copyright 2003 2009 Texas Instruments Incorporated Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 Submit Documentation Feedback TMS320C2801 TMS320F28016 TMS320F28015 Introduction 13 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 2 1 14 Pin Assignme
225. that memory Tools Guides SPRU513 SPRU514 SPRU608 SPRU625 TMS320C28x Assembly Language Tools v5 0 0 User s Guide describes the assembly language tools assembler and other tools used to develop assembly language code assembler directives macros common object file format and symbolic debugging directives for the TMS320C28x device TMS320C28x Optimizing C C Compiler v5 0 0 User s Guide describes the TMS320C28x C C compiler This compiler accepts ANSI standard C C source code and produces TMS320 DSP assembly language source code for the TMS320C28x device TMS320C28x Instruction Set Simulator Technical Overview describes the simulator available within the Code Composer Studio for TMS320C2000 IDE that simulates the instruction set of the C28x core TMS320C28x DSP BIOS 5 32 Application Programming Interface API Reference Guide describes development using DSP BIOS Copyright 2003 2009 Texas Instruments Incorporated Device Support 89 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 90 TEXAS INSTRUMENTS www ti com Application Reports and Software SPRAAQ7 SPRAAQS SPRAAN9 SPRAAMO SPRA958 SPRA
226. tion PWMx output high low 20 ns tw SYNCOUT Sync output pulse width 8tc sco cycles la PWMytza Delay time trip input active to PWM forced high no pin load 25 ns Delay time trip input active to PWM forced low latrz PWM HZ Delay time trip input active to PWM Hi Z 20 ns 6 10 2 Trip Zone Input Timing xo ZN FNS NSN AN ta TZz PWM HZ A TZ TZ1 TZ2 TZ3 TZ4 TZ5 TZ6 B PWM refers to all the PWM pins in the device The state of the PWM pins after TZ is taken high depends on the PWM recovery software Figure 6 17 PWM Hi Z Characteristics Table 6 24 Trip Zone input Timing Requirements MIN MAX UNIT lw TZ Pulse duration TZx input low Asynchronous 1tc sco cycles Synchronous 2ic scO cycles With input qualifier 1tc sco twiasw cycles 1 For an explanation of the input qualifier parameters see Table 6 15 Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 115 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5320 2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 at el SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com Table 6 25 shows the high resolution PWM switching characteristics Table 6 25 High Resolution PWM Characteristics at SYSCLKOUT
227. tput 28 This pin has an 8 mA typical output buffer 1 0 2 9 SCIRXDA SCI receive data 1 92 D5 175 2 5 GPIO29 General purpose input output 29 This pin has an 8 mA typical output buffer 1 0 2 9 SCITXDA SCI transmit data O 4 C3 1 26 Trip zone 6 input I GPIO30 General purpose input output 30 This pin has an 8 mA typical output buffer 1 0 2 9 CANRXA 6 D2 Enhanced CAN A receive data I GPIO31 General purpose input output 31 This pin has an 8 mA typical output buffer 2 9 CANTXA 7 D1 Enhanced CAN A transmit data O GPIO32 General purpose input output 32 1 0 2 9 SDAA 100 1 I2C data open drain bidirectional port EPWMSYNCI Enhanced PWM external sync pulse input I ADCSOCAO ADC start of conversion O Copyright 2003 2009 Texas Instruments Incorporated Introduction 23 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 5320 2802 TMS320F2801 TMS320C2802 5320 2801 5320 28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 5 INSTRUMENTS TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 Signal Descriptions continued PIN NO NAME pz GGM DESCRIPTION 9 PIN ZGM BALL GPIO33 General Purpose Input Output 33 2 SCLA 5 C1 I2C clock open drain bidirect
228. ture events Polarity select 4 Interrupt Continuous to PIE Trigger Oneshot ES CTR OVF Capture Control control CIR SPRD CTR CMP Figure 4 5 eCAP Functional Block Diagram Copyright 2003 2009 Texas Instruments Incorporated Peripherals 59 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 ee SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com Table 4 3 eCAP Control and Status Registers NAME eCAP1 eCAP2 eCAP3 eCAP4 a DESCRIPTION TSCTR 0 6 00 0x6A20 0x6A40 0x6A60 2 Time Stamp Counter CTRPHS 0x6A02 0x6A22 0x6A42 0x6A62 2 Counter Phase Offset Value Register CAP1 0x6A04 Ox6A24 Ox6A44 0x6A64 2 Capture 1 Register CAP2 0x6A06 Ox6A26 Ox6A46 Ox6A66 2 Capture 2 Register CAP3 0x6A08 0x6A28 0x6A48 0x6A68 2 Capture 3 Register 0x6A0A Ox6A2A Ox6A4A Ox6A6A 2 Capture 4 Register Reserved Ox6A0C Ox6A2C Ox6A4C Ox6A6C 8 Reserved Ox6A12 0x6A32 0x6A52 0x6A72 ECCTL1 0x6A14 0 6 34 0x6A54 0x6A74 1 Capture Control Register 1 ECCTL2 0x6A15 0 6 5 0x6A55 0x6A75 1 Capture Control Register 2 ECEINT 0x6A16 0x6A36 0x6A56 0x6A76 1 Capture Interrupt Enable Register ECFLG 0x6A17 0 6 7 0x6A57 0x6A77 1 Capture Interr
229. two Pulse duration XCLKIN low as a percentage of 45 55 96 C12 Lw CIH Pulse duration XCLKIN high as a percentage of tcoscci x 45 55 1 This applies to the 1 pin also Table 6 10 XCLKIN Timing Requirements PLL Disabled NO MIN MAX UNIT C8 tcc Cycle time XCLKIN 100 MHz device 10 250 ns 60 MHz device 16 67 250 C9 Fall time XCLKIN Up to 20 MHz 6 ns 20 MHz to 100 MHz 2 ns C10 tc Rise time XCLKIN Up to 20 MHz 6 ns 20 MHz to 100 MHz 2 ns C11 Pulse duration XCLKIN low as a percentage of tcosccuk 45 55 C12 Pulse duration XCLKIN high as a percentage of tcosccik 45 55 96 1 This applies to the X1 pin also The possible configuration modes are shown in Table 3 17 Table 6 11 XCLKOUT Switching Characteristics PLL Bypassed or Enabled 2 NO PARAMETER MIN TYP MAX UNIT 100 MHz device 10 C1 terxco Cycle time XCLKOUT ns 60 MHz device 16 67 Fall time XCLKOUT ns C4 tyxco Rise time XCLKOUT ns C5 twxcoL Pulse duration XCLKOUT low H H 2 ns C6 twxcoH Pulse duration XCLKOUT high H H 2 ns b PLL lock time 1310721 cycles 1 A load of 40 pF is assumed for these parameters 2 H O 5tc xco 3 OSCCLK is either the output of the on chip oscillator or the output from an external oscillator Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 105 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS
230. upt Enable Register QFLG 0x6B19 0 6 59 1 0 eQEP Interrupt Flag Register QCLR Ox6B1A Ox6B5A 1 0 eQEP Interrupt Clear Register QFRC Ox6B1B Ox6B5B 1 0 eQEP Interrupt Force Register QEPSTS Ox6B1C Ox6B5C 1 0 eQEP Status Register QCTMR 0x6B1D Ox6B5D 1 0 eQEP Capture Timer QCPRD Ox6B1E Ox6B5E 1 0 eQEP Capture Period Register QCTMRLAT Ox6B1F Ox6B5F 1 0 eQEP Capture Timer Latch QCPRDLAT 0 6 20 0 6 60 1 0 eQEP Capture Period Latch Reserved 0x6B21 Ox6B61 31 0 Reserved Ox6B3F 0 6 7 62 Peripherals Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 Texas TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 www ti com SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 4 6 Enhanced Analog to Digital Converter ADC Module A simplified functional block diagram of the ADC module is shown in Figure 4 7 The ADC module consists of a 12 bit ADC with a built in sample and hold S H circuit Functions of the ADC module include 12 bit ADC core with built in S H Analog input 0 0 V to 3 0 V Voltages above 3 0 V produce full scale conversion results Fast conversion rate Up to 80 ns at 25 MHz ADC clock 12 5 MSPS 16 channel MUXed inputs Autosequencing capability provides up to 16 autoconversio
231. upt Flag Register ECCLR 0x6A18 0x6A38 0x6A58 0x6A78 1 Capture Interrupt Clear Register ECFRC 0x6A19 0x6A39 0x6A59 0x6A79 1 Capture Interrupt Force Register Reserved Ox6A1A Ox6A3A Ox6A5A Ox6A7A 6 Reserved Ox6A1F Ox6A3F Ox6A5F Ox6A7F 60 Peripherals Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 4 5 Enhanced QEP Modules eQEP1 2 The 280x device contains up to two enhanced quadrature encoder eQEP modules See the TMSS320x280x 2801x 2804x Enhanced Quadrature Encoder Pulse eQEP Module Reference Guide literature number SPRU790 for more details control registers g To CPU EQEPxENCLK SYSCLKOUT Data bus Quadrature capture unit QCTMRLAT QCAP QCPRDLAT Registers QUTMR QWDTMR used by QUPRD QWDPRD multiple units 16 QEPCTL QEPSTS QDECCTL 16 WDTOUT EQEPxAIN EQEPxINT EQEPxA XCLK 16 EQEPxB XDIR Position counter Quadrature EQEPxIOUT control unit decoder PCCU EQEPxI EQEPxS Enhanced QEP eQEP peripheral Figure 4 6 eQEP Functional Block Diagram Copyri
232. urrent into and Vppaa1g pins In order to realize the Ippaig currents shown for IDLE STANDBY and HALT clock to the ADC module must be turned off explicitly by writing to the PCLKCRO register lIppass includes current into and pins 5 TYP numbers are applicable over room temperature and nominal voltage 6 MAX numbers are at 125 C and MAX voltage NOTE The peripheral multiplexing implemented in the 280x devices prevents all available peripherals from being used at the same time This is because more than one peripheral function may share an pin It is however possible to turn on the clocks to all the peripherals at the same time although such a configuration is not useful If this is done the current drawn by the device will be more than the numbers specified in the current consumption tables Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 95 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 TEXAS INSTRUMENTS www ti com Table 6 2 TMS320F2806 Current Consumption by Power Supply Pins at 100 MHz SYSCLKOUT MODE TEST CONDITIONS lbp 2
233. ve output master input pin SPISIMO SPI slave input master output pin SPISTE SPI slave transmit enable pin SPICLK SPI serial clock pin NOTE All four pins can be used as GPIO if the SPI module is not used Two operational modes master and slave Baud rate 125 different programmable rates LSPCLK _ Baud rate SPIBRR 1 1 when SPIBRR 3 to 127 Baud rate when SPIBRR 0 1 2 Data word length one to sixteen data bits Four clocking schemes controlled by clock polarity and clock phase bits include Falling edge without phase delay SPICLK active high SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal Falling edge with phase delay SPICLK active high SPI transmits data one half cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal Rising edge without phase delay SPICLK inactive low SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal Rising edge with phase delay SPICLK inactive low SPI transmits data one half cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal Simultaneous receive and transmit operation transmit function can be disabled in software Transmitter and receiver operations are accomplished through either interrupt driven o
234. vector from INT2 1 and so forth Peripherals SPI SCI 2 eCAN ADC Watchdog A Low Power Modes XINT1 XINT1 d Interrupt Control e e XINT1CR 15 0 o0 5 XINT1CTR 15 0 INT1 to INT12 GPIOXINT1SEL 4 0 o XINT2SOC ADC e XINT2 Interrupt Control XINT2CR 15 0 XINT2CTR 15 0 GPIOXINT2SEL 4 0 CPU TIMER 0 CPU TIMER 2 Reserved for DSP BIOS CPU TIMER 1 inti3_select z nmi_select GPIOO int e Interrupt Control e GPIO E MUX XNMICR 15 0 GPIO31 int 1 e XNMICTR 15 0 GPIOXNMISEL 4 0 Figure 3 7 External and PIE Interrupt Sources Copyright 2003 2009 Texas Instruments Incorporated Functional Overview 43 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 INT1 IFR 12 1 IER 12 1 y Y INT2 eeo vy vy y Y y v o o y vy PIEACKx Enable Flag Enable AAAAAAAA AAAAAAAA AAAAAAAA PIEIERx 8 1 PIEIFRx 8 1 Figure 3 8 Multiplexing of Interrupts Using the PIE Block Table 3 12 P
235. x Device Power Vs SYSCLKOUT 400 0 300 0 200 0 4 100 0 4 Device Power mW 0 0 10 20 30 40 50 60 70 80 90 100 SYSCLKOUT MHz TOTAL POWER Figure 6 4 Typical Operational Power Versus Frequency C280x Copyright 2003 2009 Texas Instruments Incorporated Electrical Specifications 101 Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TEXAS TMS320C2801 TMS320F28016 TMS320F28015 at el SPRS230L OCTOBER 2003 REVISED DECEMBER 2009 www ti com 6 5 Emulator Connection Without Signal Buffering for the DSP Figure 6 5 shows the connection between the DSP and JTAG header for a single processor configuration If the distance between the JTAG header and the DSP is greater than 6 inches the emulation signals must be buffered If the distance is less than 6 inches buffering is typically not needed Figure 6 5 shows the simpler no buffering situation For the pullup pulldown resistor values see the pin description section 6 inches or less VDDIO VDDIO o lt DSP JTAG Header Figure 6 5 Emulator Connection Without Signal Buffering for the DSP 102 Electrical Specifications Copyright 20
236. y 1 Parameter 18 Valid time SPISOMI data valid after SPICLK high Changed clock polarity 1 to clock polarity 0 Table 6 43 Flash Endurance for A and S Temperature Material Ni Flash endurance for the array write erase cycles Changed MIN value from 100 cycles to 20000 cycles Changed TYP value from 1000 cycles to 50000 cycles Table 6 44 Flash Endurance for Q Temperature Material N Flash endurance for the array write erase cycles Changed MIN value from 100 cycles to 20000 cycles Changed TYP value from 1000 cycles to 50000 cycles 134 Revision History Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 5320 2806 5320 2802 5320 2801 5320 2802 5320 2801 5320 28016 5320 28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 9 Mechanical Data Table 9 1 through Table 9 6 show the thermal data The mechanical package diagram s that follow the tables reflect the most current released mechanical data available for the designated device s Table 9 1 F280x Thermal Model 100 pin GGM Results AIR FLOW PARAMETER 150 250 500 8 A C W High k PCB 30 58 29 31 28 09 26 62 YP n C W 0 4184 0 32 0 3725 0 4887 Bic 12 08
237. y programmed with boot loading software Boot mode signals are provided to tell the bootloader software what boot mode to use on power up The user can select to boot normally or to download new software from an external connection or to select boot software that is programmed in the internal Flash ROM The Boot ROM also contains standard tables such as SIN COS waveforms for use in math related algorithms Table 3 7 Boot Mode Selection GPIO18 MODE DESCRIPTION SPICLKA DA GPIO34 SCITXDB Boot to Flash ROM Jump to Flash ROM address Ox3F 7FF6 1 1 1 You must have programmed a branch instruction here prior to reset to redirect code execution as desired SCI A Boot Load a data stream from SCI A 1 1 0 SPI A Boot Load from an external serial SPI EEPROM on SPI A 1 0 1 I2C Boot Load data from an external EEPROM at address 0x50 on 1 0 the 2 bus eCAN A Boot Call CAN Boot to load from eCAN A mailbox 1 0 1 1 Boot to M0 SARAM Jump to 0 SARAM address 0x00 0000 0 1 0 Boot to OTP Jump to OTP address Ox3D 7800 0 0 1 Parallel Boot Load data from GPIOO GPIO15 0 0 0 36 Functional Overview Copyright 2003 2009 Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link s TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802 TMS320C2801 TMS320F28016 TMS320F28015 TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 5320 2802

Texas Instruments TMS320C2802 User's Manual

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