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Texas Instruments TMS320 User's Manual

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1. 0 to 70 Storage temperature range 55 to 150 T Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions section of this specification is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability t All voltage values are with respect to Vss recommended operating conditions Voc Supply voltage 4 75 5 525 Vss Supply voltage All inputs except CLKIN 2 Voc 0 3 High level input voltage m loL Low level output current mA NOTES 1 Case temperature must be maintained below 90 2 36 C Watt 6 C Watt electrical characteristics over specified free air temperature range unless otherwise noted Supply current TA 25 C Vcc MAX fx MAX Tc 90 C MAX fx Co All typical values for Icc are at 5 V TA 25 y This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields These circuits have been qualified to protect this device against electrostatic discharges ESD of up to 2 kV accor
2. 1 5W Operating free air temperature range 0 to 70 Storage temperature range 55 to 150 T Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions section of this specification is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability t All voltage values are with respect to Vgs recommended operating conditions Tv except CLRNIGLENICLKRINT O 28 voros Ci v Dwg electrical characteristics over specified free air temperature range unless otherwise noted Input current VI Vss to 10 10 Low level input volt TA 0 Voc MAX fx MAX ow level input voltage A x C Input capacitance Output All typical values are at Voc 5 V TA 25 Caution This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields These circuits have been qualified to protect this device
3. 20 TMS32020 C25 C25 50 2 TMS320E25 5 60 EPROM protection verification 58 65 external interface 9 pinouts TMS32020 C25 C25 50 1 flowcharts TMS320E25 de Rcs 60 EPROM protect 63 programming levels for EPROM 58 65 IGE repeat feature 10 NONE a x 18 reflow soldering precaution 54 immediate addressing 10 I indirect addressing 10 17 serial 7 9 instruction set_ 10 16 shifter D GRAUE qaaa a 7 IntertuplS 22 25 44 442224 Ron e Gun we dana 9 specification 20 introduction 3 Subroutines 9 supply current characteristics 54 key features switching characteristics 5320 family 1 532020 2 5 2 4 223 21 23 26 TMS32020 4 5320 25 25 a cnn 27 28 33 TMS320C25 C25 50 E25 4 TMS320C25 50 34 35 40 mechanical data 7 532020 ver eed edes 55 timing diagrams 41 53 62 65 TMS320
4. external timing CLKOUT1 NSN SNS DS ta XF om wa D 1 2 3 _ AVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAN VAN kxas 9 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 49 ADVANCE INFORMATION NOILVINYOSNI 3ONVAGV TMS32020 SPRS010B MAY 1987 REVISED NOVEMBER 1990 HOLD timing part A CLKOUT2 4 1 2 HOLD NI 9 9 9 09 Y R W uo 4 ldis C1L A 4 tdis AL A HOLDA NI gt td C1L AL N N 1 N A N A lt I I I gt N 1 N D D EXECUTE 4 gt lt BIO Cag I tHOLDisan asynchronous input and can occur at any time during a clock cycle If the specified timing is met the exact sequence shown will occur otherwise a delay of one CLKOUT2 cycle will occur TEXAS 4 INSTRUMENTS 50 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 TMS32020 5 5010 MAY 1987 REVISED NOVEMBER 1990 HOLD timing part B ee ten A C1L 2 STRB N Iiq td C2H H HOLD Gu 15 RW gt td HH AH D15 D0 N 2 N 3 gt lt gt lt gt Dead Dead N 1 N 2 EXECUTE lt gt lt gt lt gt lt gt FETCH
5. ta FL DX gt nd td CH DX td CH gt P Output 1 _ _ W INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 47 ADVANCE INFORMATION NOILVINYOSNI 3ONVAQV TMS32020 SPRS010B MAY 1987 REVISED NOVEMBER 1990 BIO timing mas X XU CX UN PE NN Z N Z N FETCH Branch Address FETCH Next Instruction CURE D 1 2 3 Branch Address tsu IN 12 thin X XX XX X X X N X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X OL 182A external timing CLKOUT1 gt M XC n 1 PC N 1 2 RR RR RR RA ERN AVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAN 25 TEXAS INSTRUMENTS 48 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 5320 25 5 5010 MAY 1987 REVISED NOVEMBER 1990 BIO timing ew NN NS C A Branch Address FETCH Next Instruction XX BEX 1 3 2 Branch Address tsu IN e F lt X XX X X X X XY N X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X OL
6. A m Value derived from characterization data and not tested NOTES 3 Q 1 4tc C 4 CLKIN duty cycle tr CI tw CIH te Cl must be within 40 60 2 15 V 2 RL 825 From Output Under Test Tl 7 Test Point CL 100pF Figure 3 Test Load Circuit 1 88 V lt 0 92 V Max ax 0 80 V lt IL 0 a Input gt 22 7 08V VoL Max ax 06V lt 0 b Output Figure 4 Reference Levels TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 23 ADVANCE INFORMATION NOILVINYOSNI 532020 SPRS010B MAY 1987 REVISED NOVEMBER 1990 MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions see Note 3 PARAMETER MIN TYP MAX UNIT td C1 S STRB from CLKOUT1 if STRB is present Q 15 Q Q 15 ns td C2 S CLKOUT2 to STRB if STRB is present 15 0 15 ns tsu A Address setup hold time before STRB low see Note 5 Q 30 n th A Address hold time after STRB high see Note 5 n tw SL STRB low pulse duration no wait states see Note 6 tw SH STRB high pulse duration between consecutive cycles see Note 6 tsu D W Data write setup time before STRB high no wait states T Value derived from characterization data and not tested NOTES 3 Q 1 4te C 5 15 0 PS DS IS RAN and BR timings are all included in timings referenced as
7. T In accordance with TMS27C64 LEGEND TTL high level TTL low level ADDR byte address bit Vpp 12 5 V 0 5 V Vcc 5 0 25 V X don t care PULSE low going TTL level pulse byte to be programmed at ADDR QouT byte stored at ADDR RBIT ROM protect bit erasure Before programming the device is erased by exposing the chip through the transparent lid to high intensity ultraviolet light wavelength 2537 A The recommended minimum exposure dose UV intensity x exposure time is 15 Wes cm2 A typical 12 mW cm2 filterless UV lamp will erase the device in 21 minutes The lamp should be located approximately 2 5 cm above the chip during erasure After erasure all bits are in the high state Note that normal ambient light contains the correct wavelength for erasure Therefore when using the TMS320E25 the window should be covered with an opaque label fast programming After erasure all memory bits in the cell are logic one logic zeroes are programmed into the desired locations The fast programming algorithm shown in Figure 10 is normally used to program the entire EPROM contents although individual locations may be programmed separately A programmed logic zero can be erased only by ultraviolet light Data is presented in parallel eight bits on pins Q8 Q1 Once addresses and data are stable is pulsed The programming mode is achieved when Vpp 12 5 V Vcc 6 V G
8. AND with accumulator AND immediate with accumulator with shift Complement accumulator Load accumulator with shift Load accumulator immediate short Load accumulator with shift specified by T register Load accumulator long immediate with shift Negate accumulator Normalize contents of accumulator OR with accumulator OR immediate with accumulator with shift Rotate accumulator left Rotate accumulator right Store high accumulator with shift O O A oo o o 60 o o Store low order accumulator with shift Subtract from accumulator long immediate with shift Shift accumulator left Shift accumulator right Subtract from accumulator with shift Subtract from accumulator with borrow Conditional subtract 4 O Subtract from high accumulator Subtract from accumulator short immediate Subtract from low accumulator with sign extension suppressed T These instructions are not included in the TMS320C1x instruction set t These instructions are not included in the TMS32020 instruction set TEXAS 4 INSTRUMENTS 12 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 5320 25 5 5010 MAY 1987 REVISED NOVEMBER 1990 Table 3 TMS320C25 Instruction Set Summary continued ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS MNEMONIC DESCRIPTION NO WORDS Subtract from accumulator with shift specified by T regis
9. XDS 22 Emulator see Note TMDS3262221 XDS 22 Upgrade TMS32020 to TMS320C2x TMDX3282226 NOTE Emulation support for the TMS320C25 50 is available from Macrochip Research Inc refer to the TMS320 Family Development Support Reference Guide SPRU011A for the mailing address IBM is a trademark of International Business Machines Corporation PC DOS is a trademark of International Business Machines Corporation VAX and VMS are trademarks of Digital Equipment Corporation XDS is a trademark of Texas Instruments Incorporated TEXAS 4 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 19 5320 SECOND GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 documentation support Extensive documentation supports the second generation TMS320 devices from product announcement through applications development The types of documentation include data sheets with design specifications complete user s guides and 750 pages of application reports published in the book Digital Signal Processing Applications with the TMS320 Family SPRA012A An application report Hardware Interfacing to the TMS320C25 14 is available for that device A series of DSP textbooks is being published by Prentice Hall and John Wiley amp Sons to support digital signal processing research and education The TMS320 newsletter Details on Signal Processing is published quarterly and distributed to update TMS320 customers on p
10. address 6 Delays between CLKOUT1 CLKOUT2 edges and STRB edges track each other resulting in tw SL tw SH being 20 with no wait states 5 5 timing requirements over recommended operating conditions see Note 3 8 t Value derived from characterization data and not tested NOTES 3 Q T 4tc C 5 15 0 PS DS IS R W and BR timings are all included in timings referenced as address 7 Read data access time is defined as ta A tsu A tw SL tsu D R TEXAS INSTRUMENTS 24 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 TMS32020 SPRSO010B MAY 1987 REVISED NOVEMBER 1990 RS INT BIO AND XF TIMING switching characteristics over recommended operating conditions see Note 3 and 8 PARAMETER MIN TYP MAX UNIT ta RS CLKOUT1 low to reset state entered ta IACK CLKOUT1 to IACK valid 25 0 25 valid before falling edge of STRB NOTES 3 Q 1 4tc C 8 RS INT and BIO are asynchronous inputs and can occur at any time during a clock cycle However if the specified setup time is met the exact sequence shown in the timing diagrams will occur timing requirements over recommended operating conditions see Note 3 and 8 MN 0 0 T Value derived from characterization data and not tested NOTES 3 Q 1 4te C 8 RS INT and BIO are asynchronous inputs and can occur at a
11. scaling shifter The TMS320C2x scaling shifter has 16 bit input connected to the data bus and a 32 bit output connected to the ALU The scaling shifter produces a left shift of 0 to 16 bits on the input data as programmed in the instruction The LSBs of the output are filled with zeroes and the MSBs may be either filled with zeroes or sign extended depending upon the status programmed into the SXM sign extension mode bit of status register ST1 16 x 16 bit parallel multiplier The 16 x 16 bit hardware multiplier is capable of computing a signed or unsigned 32 bit product in a single machine cycle The multiplier has the following two associated registers 9 A 16 bit Temporary Register TR that holds one of the operands for the multiplier and 32 Product Register PR that holds the product Incorporated into the instruction set are single cycle multiply accumulate instructions that allow both operands to be processed simultaneously The data for these operations may reside anywhere in internal or external memory and can be transferred to the multiplier each cycle via the program and data buses Four product shift modes are available at the Product Register PR output that are useful when performing multiply accumulate operations fractional arithmetic or justifying fractional products timer The TMS320C2x provides a memory mapped 16 bit timer for control operations The on chip timer TIM register is a down counter that i
12. 6 7 20 5 fxs Serial port frequency TA 0 to 70 501 2563 C2 0 C to 70 C T Value derived from characterization data minimum fsx at test 825 kHz Crystal Figure 2 Internal Option external clock option An external frequency source can be used by injecting the frequency directly into X2 CLKIN with X1 left unconnected The external frequency injected must conform to the specifications listed in the following table switching characteristics over recommended operating conditions see Note 3 PARAMETER MIN NO te C CLKOUT1 CLKOUT2 cycle time 195 td CIH C high to CLKOUT1 CLKOUT2 STRB high low 25 CLKOUT1 CLKOUT2 STRB fall time tr C CLKOUT1 CLKOUT2 STRB rise time tw CL CLKOUT1 CLKOUT2 low pulse duration 20 15 20 20 15 tw CH CLKOUT1 CLKOUT2 high pulse duration 20 15 20 20 15 td C1 C2 high to CLKOUT2 low CLKOUT2 high to CLKOUT1 high etc Q 10 Q Q 10 ns NOTE 3 Q 1 4tc C TEXAS INSTRUMENTS 22 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 TMS32020 SPRS010B MAY 1987 REVISED NOVEMBER 1990 timing requirements over recommended operating conditions see Note 3 INN 0 CLKIN cycle time 195 597 wor OKWkwmisdwa 5015 m GRN high duration ee 50 ns Note 4 E ms wis SYNCsetuptineeoreGLKINow ws
13. E Vi More than one TMS320E25 can be programmed when the devices are connected in parallel Locations can be programmed in any order Programming uses two types of programming pulses prime and final The length of the prime pulse is 1 ms After each prime pulse the byte being programmed is verified If correct data is read the final programming pulse is applied if correct data is not read an additional 1 ms prime pulse is applied up to a maximum of 15 times The final programming pulse is 4 ms times the number of prime programming pulses applied This sequence of programming and verification is performed at 6 V and Vpp 12 5 V When the full fast programming routine is complete all bits are verified with Vcc Vpp 5 V TEXAS INSTRUMENTS 60 POST OFFICE BOX 1443 HOUSTON TEXAS 77001 TMS320E25 SPRS010B MAY 1987 REVISED NOVEMBER 1990 program verify Programmed bits may be verified with Vpp 12 5 V when G Vj and Figure 11 shows the timing for the program and verify operation W Address First Location 6 0 25 V 12 5 V 0 25 Pulse of 3X ms Duration A Increment Address Fail Compare All Bytes to Original Data Device Passed Figure 10 Fast Programming Flowchart TEXAS 4 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 61 ADVANCE INFORMATION NOILVINYOSN
14. 0 950 see Note A 0 995 0 985 23 62 0 930 23 11 0 910 At Seating Plane 0 94 0 037 1 22 0 048 sa 0 69 0 027 1 07 0 042 1 35 0 053 24 33 0 956 1 19 0 047 45 24 13 0 950 25 27 0 995 Thermal Resistance Characteristics PARAMETER MAX UNIT Junction to free air thermal resistance 46 C W Junction to case thermal resistance 11 C W 2 79 0 110 gt 2 41 0 095 z 25 02 0 985 4 50 0 177 4 24 0 167 0 81 0 032 1 52 0 060 0566 0 026 0 64 0 025 Lead Detail 0 51 0 020 0 36 0 014 ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES NOTES A Centerline of center pin each side is within 0 10 0 004 of package centerline as determined by this dimension B Location of each pin is within 0 127 0 005 of true position with respect to center pin on each side WARNING When reflow soldering is required refer to page 54 for special handling instructions 56 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77001 TMS320E25 SPRS010B MAY 1987 REVISED NOVEMBER 1990 MECHANICAL DATA 68 lead FZ CER QUAD ceramic leaded chip carrier package TMS320E25 only This hermetically sealed chip carrier package consists of a ceramic base ceramic cap and a 68 lead
15. 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 OO N lt lt 3 8 3 23 2 559 gt gt 3 9K A9 TMS27C64 Pin Nomenclature TMS320E25 I A12 5 0 LSB On chip EPROM programming address lines oscillator input chip select EPROM test mode select EPROM read verify select Ground EPROM write program select Data lines for byte wide programming of on chip 8K bytes of EPROM Reset for initializing the device 5 V power supply 12 5 V power supply Figure 9 TMS320E25 EPROM Conversion to TMS27C64 EPROM Pinout TEXAS 4 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 59 ADVANCE INFORMATION NOILVINHOHMNI 3ONVAQV TMS320E25 SPRS010B MAY 1987 REVISED NOVEMBER 1990 Table 5 shows the programming levels required for programming verifying and reading the EPROM cell The paragraphs following the table describe the function of each programming level Table 5 TMS320E25 Programming Mode Levels MN ws 2252 x x 24553 wm x amp e x s s An x en en ae x m x J oaa m An x A
16. and other serial systems The interface signals are compatible with codecs and many other serial devices with a minimum of external hardware The serial port may also be used for intercommunication between processors in multiprocessing applications The serial port has two memory mapped registers the data transmit register DXR and the data receive register DRR Both registers operate in either the byte mode or 16 bit word mode and may be accessed in the same manner as any other data memory location Each register has an external clock a framing synchronization pulse and associated shift registers One method of multiprocessing may be implemented by programming one deviceto transmit while the others are in the receive mode The serial port on the TMS320C25 is double buffered and fully static multiprocessing The flexibility of the TMS320C2x allows configurations to satisfy a wide range of system requirements and can be used as follows standalone processor multiprocessor with devices in parallel Aslave host multiprocessor with global memory space A peripheral processor interfaced processor controlled signals to another device For multiprocessing applications the TMS320C2x has the capability of allocating global data memory space and communicating with that space via the BR bus request and READY control signals Global memory is data memory shared by more than one processor Global data memory access must be ar
17. 4 1 tHOLDisan asynchronous input and can occur at any time during a clock cycle If the specified timing is met the exact sequence shown will occur otherwise a delay of one CLKOUT2 cycle will occur TEXAS 4 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 51 ADVANCE INFORMATION NOILVINHOHMNI TMS320C25 SPRS010B MAY 1987 REVISED NOVEMBER 1990 HOLD timing part A CLKOUT2 tacon nyt HOLD NI e QC Co X XX Y R W 4 tdis C1L A 4 tdis AL A HOLDA NI gt 4 td C1L AL RS FETCH 4 1 1 I gt EXECUTE lt I I I gt tHOLDisan asynchronous input and can occur at any time during a clock cycle If the specified timing is met the exact sequence shown will occur otherwise a delay of one CLKOUT2 cycle will occur TEXAS 4 INSTRUMENTS 52 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 5320 25 5 5010 MAY 1987 REVISED NOVEMBER 1990 HOLD timing part B ee ten A C1L 2 STRB N Iiq td C2H H HOLD _ O A 7 PS DS 555 5 Valid D15 D0 DQ gt td HH AH mE om N 2 FETCH 4 gt lt gt lt gt lt gt N 1 EXECUTE 4 gt lt gt lt gt tHOLDisan asynchronous input and can occur at any time during a clo
18. 9 Execute the Reset Overflow Mode ROVM instruction immediately prior to the BIT instruction and the Set Overflow Mode SOVM instruction immediately following the BIT instruction fdirect memory addressing is being used during the instructions reorganize memory so that the page relative locations 0 4 8 C 10 are not used If indirect addressing is being used during the Bit instruction select a new ARP which is not ARO or ARA If necessary follow the instruction with a LARP ARO or LARP ARA to restore the code Use the Test Bit Specified by T Register BITT instruction instead of the BIT instruction The BITT instruction operates correctly and will not affect the accumulator under any circumstances Replace TMS32020 with TMS320C25 for ideal pin to pIn and object code compatibility The instruction on the TMS320C25 executes properly and will not affect the accumulator under any circumstances I TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 17 5320 SECOND GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 development support Together Texas Instruments and its authorized third party suppliers offer an extensive line of development support products to assist the user in all aspects of TMS320 second generation based design and development These products range from development and application software to complete hardware development and evaluation systems Table 4
19. FSX 1 6 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 45 ADVANCE INFORMATION NOILVINYOSNI 3ONVAQV 5320 SECOND GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 interrupt timing TMS32020 4 5 tsu IN 4 th IN E tw IN gt INT2 INTO N 4 td IACK ta IACK gt V XX XXX PER 07 KLLKK interrupt timing TMS320C25 gt tsu IN STRB N N 4 thin lt tw IN gt INT2 INTO N lt gt 14 td IACK 15 0 FETCH 1 2 FETCH I x tdlACK ne KIA 6 INSTRUMENTS 46 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 TMS320 SECOND GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 serial port receive timing 4 tc SCK gt gt M 4 5 DR gt MC p th FS twsck FSR N gt tsu FS Sul gt k tsu DR S MNN XX N N V XX XX x XXX DR serial port transmit timing K te SCK gt tw SCK lt gt lt tr sckK ta CH DX gt pl 4 gt tw Sck FSX Input TXM 0 3 t su FS 34
20. architecture Each processor has software and hardware tools to facilitate rapid design introduction TMS32010 the first NMOS digital signal processor in the TMS320 family was introduced 1983 Its powerful instruction set inherent flexibility high speed number crunching capabilities and innovative architecture have made this high performance cost effective processor the ideal solution to many telecommunications computer commercial industrial and military applications Since that time the TMS320C10 a low power CMOS version of the industry standard TMS32010 and other spinoff devices have been added to the first generation of the 5320 family The second generation of the TMS320 family referred to as 5320 2 includes four members the TMS32020 TMS320C25 TMS320C25 50 and TMS320E25 The architecture of these devices is based upon that of the TMS32010 The TMS32020 processed in NMOS technology is source code compatible with he TMS32010 and in many applications is capable of two times the throughput of the first generation devices Its enhanced instruction set 109 instructions large on chip data memory 544 words large memory spaces on chip serial port and hardware timer make the TMS32020 powerful addition to the 320 family The TMS320C25 is the second member of the TMS320 second generation Itis processed in CMOS technology is capable of an instruction cycle time of 100 ns and is pin for pin and o
21. defines Green to mean Pb Free ROHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 1 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by to Customer on an annual basis OTHER QUALIFIED VERSIONS OF TMS320C25 e Military SMJ320C25 NOTE Qualified Version Definitions e Military QML certified for Military and Defense Applications Addendum Page 1 IMPORTANT NOTICE Texas Instr
22. option Theinternal oscillator is enabled by connecting a crystal across X1 and X2 CLKIN The frequency of CLKOUT 1 is one fourth the crystal fundamental frequency The crystal should be in either fundamental or overtone mode and parallel resonant with an effective series resistance of 30 O a power dissipation of 1 mW and be specified at a load capacitance of 20 pF Note that overtone crystals require an additional tuned LC circuit PARAMETER TEST CONDITIONS MIN fx Input clock frequency TA 0 to 70 6 7 51 2 5 Serial port frequency TA 0 to 70 t The serial port was tested at a minimum frequency of 1 25 MHz However the serial port was fully static but will properly function down to fsx 0 Hz Crystal Figure 6 Internal Option external clock option An external frequency source can be used by injecting the frequency directly into X2 CLK with X1 left unconnected The external frequency injected must conform to specifications listed in the following table switching characteristics over recommended operating conditions see Note 3 te C CLKOUT1 CLKOUT2 cycle time 78 13 id CIH C high to CLKOUT1 CLKOUT2 STRB high low CLKOUT1 CLKOUT2 STRB fall time tr C CLKOUT1 CLKOUT2 STRB rise time tw CL CLKOUT1 CLKOUT2 STRB low pulse duration tw CH CLKOUT1 CLKOUT2 STRB high pulse duration CLKOUT1 high to CLKOUT2 low 1 2 _ CLKOUT2 high to C
23. through AR7 respectively There are seven types of indirect addressing auto increment or auto decrement post indexing by either adding or subtracting the contents of ARO single indirect addressing with no increment or decrement and bit reversal addressing used in FFTs on the TMS320C25 only with increment or decrement All operations are performed on the current auxiliary register in the same cycle as the original instruction following which the current auxiliary register and ARP may be modified repeat feature A repeat feature used with instructions such as multiply accumulates block moves I O transfers and table read writes allows a single instruction to be performed up to 256 times The repeat counter RPTC is loaded with either a data memory value RPT instruction or an immediate value RPTK instruction The value of this operand is one less than the number of times that the next instruction is executed Those instructions that are normally multicycle are pipelined when using the repeat feature and effectively become single cycle instructions TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 TMS320 SECOND GENERATION DEVICES SPRSO010B MAY 1987 REVISED NOVEMBER 1990 instruction set summary Table 2 lists the symbols and abbreviations used in Table 3 the TMS320C25 instruction set summary Table 3 consists primarily of single cycle single word instructions Infrequently used branch I O and CA
24. 025 ehe ned 55 56 TMS320 Second Generation 41 47 TMS320C25 50 56 532020 46 48 50 51 1MS320E25 57 5320 25 25 46 49 52 53 memory TMS3220 product notification 17 addressing modes 10 17 CONTON PEE 8 i TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 67 1 TEXAS PACKAGE ADDENDUM INSTRUMENTS www ti com 4 May 2009 PACKAGING INFORMATION Orderable Device Status Package Package Pins Package Eco Plan 2 Lead Ball Finish MSL Peak Temp 9 Type Drawing Qty TMS320C25FNA NRND PLCC FN 68 18 Green RoHS amp NIPDAU Level 3 260C 168 HR no Sb Br TMS320C25FNAR NRND PLCC FN 68 TBD Call TI Call TI TMS320C25FNL NRND PLCC FN 68 18 Green RoHS amp NIPDAU Level 3 260C 168 HR no Sb Br 5320 25 33 OBSOLETE PLCC FN 68 TBD Call TI Call TI TMS320C25FNLR NRND PLCC FN 68 250 Green RoHS amp NIPDAU Level 3 260C 168 HR no Sb Br TMS320C25FNLW OBSOLETE PLCC FN 68 Green ROHS amp CU NIPDAU Level 3 260C 168 HR no Sb Br TMS320C25GBA NRND CPGA GB 68 21 TBD AU N A for Pkg Type TMS320C25GBL NRND CPGA GB 68 21 TBD AU N A for Pkg Type TMS320C25PHL NRND QFP PH 80 66 Green RoHS amp NIPDAU Level 4 260C 72 HR no Sb Br The marketing status values are defined as follows A
25. 0h 511 01FFh 512 0200h 767 02FFh 768 0300h 1023 03FFh 1024 0400h If MP MC 0 Microcomputer Mode on TMS320C25 65 535 0FFFFh 65 535 0FFFFh a Memory Maps After a CNFD Instruction Program 0 0000h Interrupts 0 0000h and Reserved On Chip ROM EPROM 31 001Fh 5 0005h 32 00201 On Chip 6 0006h ROM EPROM 4015 0FAFh 95 005Fh 4016 0FBOh 96 0060h Reserved 4095 0FFFh 4096 1000h 127 007Fh 128 0080h 511 01FFh 512 0200h 767 02FFh External 768 0300h 1023 03FFh 1024 0400h 65 279 0FEFFh 65 280 0FF00h TEQUE On Chip Block 65 535 0FFFFh 65 535 0FFFFh If MP MC 0 Microcomputer Mode on TMS320C25 b Memory Maps After a CNFP Instruction Figure 1 Memory Maps TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 Data On Chip Memory Mapped Registers On Chip Block B2 On Chip Block B0 Pages 4 5 On Chip Block B1 Pages 6 7 Pages 8 511 Data On Chip Memory Mapped Registers On Chip Block B2 Does Not 5m 1 Pages 6 7 Pages 8 511 TMS320 SECOND GENERATION DEVICES SPRSO010B MAY 1987 REVISED NOVEMBER 1990 interrupts and subroutines The TMS320C2x has three external maskable user interrupts INT2 INTO available for external devices that interrupt the processor Internal interrupts are generated by the serial port RINT and XINT by the timer TINT and by the so
26. B low write tdis D Data bus high impedance state after STRB high write ns T value derived from characterization data and not tested NOTES 3 1 4 0 5 15 0 PS DS IS RAN and BR timings all included timings referenced address 6 Delay between CLKOUT1 CLKOUT2 and STRB edges track each other resulting ty s and being 2Q with no wait states n A w SL D W h D W timing requirements over recommended operating conditions see Note 3 mp 2 th SL READY hold time after STRB low no wait states READY valid after MSC valid 20 24 READY hold time after MSC valid n NOTES 3 1 4 5 15 0 PS DS IS R W BR timings included in timings referenced as address 7 Read data access time is defined as tsu A tw SL tsu D R ADVANCE INFORMATION TEXAS 4 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 37 NOILVINYOSNI 3ONVAQV 5320 25 50 SPRS010B MAY 1987 REVISED NOVEMBER 1990 RS INT BIO AND XF TIMING switching characteristics over recommended operating conditions see Notes 3 and 16 PARAMETER MIN TYP MAX UNIT ta RS CLKOUT1 low to reset state entered td XF XF valid before falling edge of STRB Q 8 n T Value derived from characterization data and not tested NOTES 3 Q 1 4 16 RS INT BIO are
27. C25FNL is exposed to uncontrolled levels of humidity prior to reflow solder This moisture can flash to steam during solder reflow causing sufficient stress to crack the package and compromise device integrity If the TMS320C25FNL is being socketed no special handling precautions are required In addition once the device is soldered into the board no special handling precautions are required In order to minimize moisture absorption ships the TMS320C25FNL in dry pack shipping bags with a RH indicator card and moisture absorbing desiccant These moisture barrier shipping bags will adequately block moisture transmission to allow shelf storage for 12 months from date of seal when stored at less than 60 relative humidity RH and less than 30 C Devices may be stored outside the sealed bags indefinitely if stored at less than 25 RH and 30 C Once the bag seal is broken the devices should be stored at less than 60 RH and 30 C as well as reflow soldered within two days of removal In the event that either of the above conditions is not met TI recommends these devices be baked in a clean oven at 125 C and 10 maximum RH for 24 hours This restores the devices to their dry packed moisture level NOTE Shipping tubes will not withstand the 125 C baking process Devices should be transferred to a metal tray or tube be fore baking Standard ESD precautions should be followed In addition recommends that the reflow proce
28. CE BOX 1443 9 HOUSTON TEXAS 77001 31 ADVANCE INFORMATION NOILVINHOHMNI 3ONVAGV 5320 25 5320 25 SPRS010B MAY 1987 REVISED NOVEMBER 1990 SERIAL PORT TIMING switching characteristics over recommended operating conditions see Note 3 PARAMETER MIN TYP MAX UNIT td CH DX DX valid after CLKX rising edge see Note 10 ta FL DX DX valid after FSX falling edge 0 see Note 10 td CH FS FSX valid after CLKX rising edge TXM 1 NOTES 3 1 4 10 last occurrence of FSX falling and CLKX rising timing requirements over recommended operating conditions see Note 3 NOM MAX i SCK Serial port clock CLKX CLKR cycle timet fSCK Serial port clock CLKX CLKR fall time tr SCK Serial port clock CLKX CLKR rise time ns tw SCK Serial port clock CLKX CLKR low pulse duration see Note 11 5 tw SCK Serial port clock CLKX CLKR high pulse duration see Note 11 5 tsu FS FSX FSR setup time before CLKX CLKR falling edge 0 o 5 5 n n 18 n th FS FSX FSR hold time after CLKX CLKR falling edge TXM 0 20 n 10 n 20 n tsu DR DR setup time before CLKR falling edge x th DR DR hold time after CLKR falling edge 120 t The serial port was tested at a minimum frequency of 1 25 MHz However the serial port was fully static but will properly function down to fsx 0 Hz t Value derived from characterization data
29. CLKOUT1 CLKOUT2 STRB A15 A0 BR PS DS R W or IS READY D15 DO For Read Operation D15 DO For Write Operation MSC 1 1 th C2H R GQ 4 55 th C2H R tatum td C2H R lt X ta M R 4 lt m gt K th M R td M R 4 gt gt 050500009 th M R X Data RLY gt 14 44 TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77001 TMS320 SECOND GENERATION DEVICES SPRSO010B MAY 1987 REVISED NOVEMBER 1990 reset timing CLKOUT1 Z XZ X gt k tsu IN gt gt tsu IN gt RS NI tw RS gt s 7 A15 A0 Valid KX Fetch lt gt Location 0 D15 D0 AN oe e e e LAG Valid 4 Begin gt Program PS ANS SS SS N Execullon STRB N IVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAVAY 3 I O Control 55955555955 Signalst 550050505002 Y Y x XX MANSIS lt gt AN 1 Control signals are DS IS R W and t Serial port controls are DX and
30. CODE DESCRIPTION 14 13 12 109 8 7 Add P register to accumulator 1 0 0 Load high P register Load T register Load T register and accumulate previous product wv V Load T register accumulate previous product and move data Load T register and store P register in accumulator Load T register and subtract previous product Multiply and accumulate Multiply and accumulate with data move Multiply with T register store product in P register Multiply and accumulate previous product Multiply immediate Multiply and subtract previous product Multiply unsigned Load accumulator with P register Subtract P register from accumulator Store high P register S O vv V www y Store low P register y P register output shift mode Square and accumulate Square and subtract previous product T These instructions are not included in the TMS320C1x instruction set t These instructions are not included in the TMS32020 instruction set TEXAS 4 INSTRUMENTS 14 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 5320 25 SPRS010B MAY 1987 REVISED NOVEMBER 1990 Table 3 TMS320C25 Instruction Set Summary continued BRANCH CALL INSTRUCTIONS NO INSTRUCTION BIT CODE MNEMONIC DESCRIPTION WORDS 2 13 12 Branch unconditionally Branch to address specified by accumulator Branch on auxiliary registe
31. CTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free ROHS Pb Free ROHS Exempt or Green ROHS amp no Sb Br please check http Awww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS TI s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures Pb Free products are suitable for use in specified lead free processes Pb Free ROHS Exempt This component has a RoHS exemption for either 1 lead based flip chip solder bumps used between the die and package or 2 lead based die adhesive used between the die and leadframe The component is otherwise considered Pb Free RoHS compatible as defined above Green RoHS 8 no Sb Br
32. D R 5 Y BIO and XF timing TMS320C25 TMS320C25 50 PARAMETER UNIT MIN TYP MAX MIN TYP MAX 778 fpe fe 217 777 HOLD timing TMS320C25 TMS320C25 50 PARAMETER MIN MAX UNIT td C2H H serial port timing 20 ns TEXAS INSTRUMENTS 40 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 TMS320 SECOND GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 TIMING DIAGRAMS This section contains all the timing diagrams forthe TMS320 second generation devices Referto the top corner of page for the specific device Timing measurements are referenced to and from a low voltage of 0 8 voltage and a high voltage of 2 volts unless otherwise noted clock timing tw ciH th S gt gt e tw CIL tsu S tsu S SYNC NI b te C td CIH C gt i tw CL gt gt td CIH C CLKOUT1 N N td CIH C gt M lt tC STRB N lt gt ta CIH C te C gt tw CL CLKOUT2 ld C1 C2 ta C1 C2 le tc gt lt td C1 C2 K tw CH id C1 C2 4 9 1 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 41 ADVANCE INFORMATION NOILVINYOSNI 3ONVAQV 5320 SECOND GENERATION D
33. ER MIN TYP MAX UNIT td CH DX DX valid after CLKX rising edge see Note 18 ta FL DX DX valid after falling edge 0 see Note 18 td CH FS FSX valid after CLKX raising edge 1 NOTES 3 Q 1 4 tec 18 The last occurrence of FSX falling and CLKX rising timing requirements over recommended operating conditions see Note 3 tsu FS FSX or FSR setup time before CLKX CLKR falling edge TXM 0 t The serial port was tested at a minimum frequency of 1 25 MHz However the serial port was fully static but will properly function down to fsx 0 Hz Value derived from characterization data and not tested NOTES 3 1 4 tec 19 The cycle of the serial port must be within 40 60 CONTRAST SUMMARY OF ELECTRICAL SPECIFICATIONS The following table presents electrical parameters which differ between TMS320C25 40 MHz 100 ns and TMS320C25 50 50 MHz 80 ns clock characteristics and timing PARAMETER tc SCk w C w C d h S L H 5 TEXAS 4 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 39 ADVANCE INFORMATION NOILVINYOSNI ili 5320 25 50 SPRS010B MAY 1987 REVISED NOVEMBER 1990 memory and peripheral interface timing TMS320C25 TMS320C25 50 PARAMETER MIN TYP MAX MIN TYP MAX ld C1 S Q 6 Q Q 6 Q 5 Q 3 td C2 S 2 tsu A 12 Q 11 0 4 iw SL 20 5 tw SH 20 2 tsu D W 20 17 th D W 0 5 Id MSC 12 ta A 30 35 3Q 30 tsu
34. EVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 memory read timing ta c1 s gt CLKOUT1 2 CLKOUT2 STRB s gt uA o RW READY D15 D0 td C1 S TN ta C2 S gt 4 ta C2 s gt 4 tsu A EN 4 lt ta A PY td SL R gt lt gt th SL R 4 Pi tw SL gt tsu D R gt gt 4 tw SH XXXX XW N X X X X X X X X LY th D R 42 6 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 TMS320 SECOND GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 memory write timing CLKOUT1 CLKOUT2 N Z NAN 7 gt th A tsu A 4 2 15 0 WV W M SR PS DS CO YD R W DN DA AA XX DAA XX XX m tsu D W 4 5 th D w 015 00 NN Data Out QS ten D 4 tais p Pl W INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 43 ADVANCE INFORMATION NOILVINYOSNI 3ONVAQV 5320 SECOND GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 one wait state memory access timing
35. I 3ONVAQV 5320 25 SPRS010B 1987 REVISED NOVEMBER 1990 4 lk Verity P 12 0 Address Stab VIH e Address 1 VIL 08 01 Data Stable HI Z Data Out Valid VIL VoL M Vcc 1 _ VIH E VIL VIL y E VIL Figure 11 Fast Programming Timing program inhibit Programming may be inhibited by maintaining a high level input on the E pin or PGM pin read The EPROM contents may be read independent of the programming cycle provided the RBIT ROM protect bit has not been programmed The read is accomplished by setting E to zero and pulsing G low The contents of the EPROM location selected by the value on the address inputs appear Q8 Q1 output disable During the EPROM programming process the EPROM data outputs may be disabled if desired by establishing the output disable state This state is selected by setting the G and PGM pins high While output disable is selected Q8 Q1 are placed in the high impedance state ROM protection and verification This section describes the code protection feature included in the EPROM cell which protects code against copyright violations Table 6 shows the programming levels required for protecting and verifying the EPROM The paragraphs following the table describe the protect and verify f
36. LKOUT1 high etc NOTE 3 Q 1 4 te C TEXAS 4 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 35 ADVANCE INFORMATION NOILVINYOSNI 5320 25 50 SPRS010B MAY 1987 REVISED NOVEMBER 1990 TMS320C25 fcrystal 10 74HC04 4 7 KQ F11 CLKIN lt ANN ie 20 01 uF 47 pF 74 504 10 lt 1 222 feysa TMS320C25 TMS320C25 50 TMS320E25 Figure 7 External Clock Option timing requirements over recommended operating conditions see Note 3 s ai CLKIN rise time tw CIL CLKIN low pulse duration tc CI 50 ns see Note 4 tw CIH CLKIN high pulse duration 50 ns see Note 4 tsu S SYNC setup time before CLKIN low th S SYNC hold time from CLKIN low T Value derived from characterization data and not tested NOTES 3 Q 1 4 te C 4 CLKIN duty cycle tr CI tw CIH l tc cI must be within 40 60 TEXAS 4 INSTRUMENTS 36 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 5320 25 50 5 5010 MAY 1987 REVISED NOVEMBER 1990 MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics over recommended operating conditions see Note 3 PARAMETER iq C1 s STRB from CLKOUT if STRB is present td C2 S CLKOUT to STRB if STRB is present tsu A Address setup time before STRB low see Note 5 igh i len D Data bus starts being driven after STR
37. LL instructions are multicycle The instruction set summary is arranged according to function and alphabetized within each functional grouping The symbol 7 indicates those instructions that not included in the TMS320C1x instruction set The symbol indicates instructions that are not included in the TMS32020 instruction set Table 2 Instruction Symbols SYMBOL DEFINITION 4 bit field specifying a bit code 2 bit field specifying compare mode Data memory address field Format status bit Addressing mode bit Immediate operand field Port address PAO through PA15 are predefined assembler symbols equal to 0 through 15 respectively 2 bit field specifying P register output shift code 3 bit operand field specifying auxiliary register 4 bit left shift code 3 bit accumulator left shift field TEXAS 4 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 11 5320 25 SPRS010B MAY 1987 REVISED NOVEMBER 1990 Table 3 TMS320C25 Instruction Set Summary ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS NO INSTRUCTION BIT CODE MNEMONIC DESCRIPTION 14 13 1 109 8 7 Absolute value of accumulator 1 0 Add to accumulator with shift Add to accumulator with carry Add to high accumulator Add to accumulator short immediate Add to low accumulator with sign extension suppressed Add to accumulator with shift specified by T register Add to accumulator long immediate with shift
38. ROM Protect Timing W INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 65 ADVANCE INFORMATION NOILVINHOHMNI TMS320 SECOND GENERATION INDEX DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 EXAS INSTRUMENTS 66 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 NIL NIL NIL SPRS010B MAY 1987 REVISED NOVEMBER 1990 accumulatot 5 microcomputer microprocessor mode adapter socket 58 multiplier Q isi nr bte 7 addressing modes 10 multiprocessing 9 ALU Mec 5 yanuq a dad uas 5 operation conditions TMS32020 ERRARE RS 17 21 instruction 17 TMSS90G25 UL LE Eden 27 block diagram 6 TMS320C25 50 34 Bulletin board Service 18 TMS320E25 iik Rr emen 27 33 OVelTlOW serisi ig darts tie e Ra eck 17 clock 1 ccc cr 22 overview TMS320C25 E25 28 29 20 5 TMS320C25 50 35 36 specification 20 description 1 package 1 5 development support 18 19 pu 2 direct addressing 10 17 nomenclature DMA documentation support
39. TEXAS INSTRUMENTS 2 POST OFFICE BOX 1443 HOUSTON TEXAS 77001 TMS320 SECOND GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 description The TMS320 family of 16 32 bit single chip digital signal processors combines the flexibility of a high speed controller with the numerical capability of an array processor thereby offering an inexpensive alternative to multichip bit slice processors The highly paralleled architecture and efficient instruction set provide speed and flexibility to produce a MOS microprocessor family that is capable of executing more than 12 5 MIPS million instructions per section The TMS320 family optimizes speed by implementing functions in hardware that other processors implement through microcode or software This hardware intensive approach provides the design engineer with processing power previously unavailable on a single chip The TMS320 family consists of three generations of digital signal processors The first generation contains the TMS32010 and its spinoffs The second generation includes the TMS32020 TMS320C25 and TMS320E25 which are described in this data sheet The 320 30 is a floating point DSP device designed for even higher performance Many features are common among the TMS320 processors Specific features are added in each processor to provide different cost performance tradeoffs Software compatibility is maintained throughout the family to protect the user s investment in
40. TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS SPRSO010B MAY 1987 REVISED NOVEMBER 1990 80 ns Instruction Cycle Time 68 Pin GB Top View 544 Words of On Chip Data RAM 1234567 8 9 1011 4K Words of On Chip Secure Program EPROM 5320 25 4K Words of On Chip Program ROM TMS320C25 128K Words of Data Program Space 32 Bit ALU Accumulator 16 x 16 Bit Multiplier With a 32 Bit Product Block Moves for Data Program Management Z G gt Repeat Instructions for Efficient Use of Program Space Serial Port for Direct Codec Interface 68 Pin FN and FZ Packagest Top View Synchronization Input for Synchronous o Multiprocessor Configurations orny ole olo e Wait States for Communication Slow Off Chip Memories Peripherals 0 Timer for Control Operations 4 Single 5 V Supply e Packaging 68 Pin PGA PLCC and dm CER QUAD 8 X2 CLKIN X1 68 to 28 Pin Conversion Adapter Socket for BR EPROM Programming Ms Commercial and Military Versions Available S DS NMOS Technology Vss 532020 200 ns cycle time CMOS Technology 5320 25 100 ns cycle time 5320 25 100 ns cycle time TMS320C25 50 80 ns cycle time description This data sheet provides complete de
41. a Bus 16 I 4 16 9 16 16 to ARO 16 7188 16 3 AR1 16 From IR ARP 3 AR2 16 DP n 16 16 Multiplier 1 9 T3 AR5 16 PR 32 6 16 1 AR7 16 16 32 32 ARB 3 4 9 Shifter 6 0 1 4 16 16 32 1 ARAU 16 ND 16 15 2 1 32 16 16 2 DATA PROG 32 X 16 RAM 256 X 16 Book E RAM ock BO 6 16 Block B1 16 32 256 X 16 Shifters 0 7 16 16 16 Data Bus LEGEND ACCH Accumulator high IFR Interrupt flag register PC Program counter ACCL Accumulator low IMR Interrupt mask register PFC Prefetch counter ALU Arithmetic logic unit IR Instruction register RPTC Repeat instruction counter ARAU Auxiliary register arithmetic unitMCS Microcall stack GREG Global memory allocation register ARB Auxiliary register pointer buffer QIR Queue instruction register RSR Serial port receive shift register ARP Auxiliary register pointer PR Product register XSR Serial port transmit shift register DP Data memory page pointer PRD Period register for timer ARO AR7 Auxiliary registers DRR Serial port data receive register TIM STO ST1 Status registers Serial port data transmit register TR Temporary register Carry bit TEXAS INSTRUMENTS 6 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 TMS320 SECOND GENERATION DEVICES SPRSO010B MAY 1987 REVISED NOVEMBER 1990
42. ackage centerline as determined by dimension B 3 Location of each pin is within 0 127 0 005 of true position with respect to center pin on each side 4 The lead contact points are within 0 15 0 006 of being planar TEXAS 4 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 57 ADVANCE INFORMATION NOILVINYOSNI 3ONVAQV 5320 25 5 5010 MAY 1987 REVISED NOVEMBER 1990 programming the TMS320E25 EPROM cell The TMS320E25 includes a 4K x 16 bit EPROM implemented from an industry standard EPROM cell to perform prototyping and early field testing and to achieve low volume production When used with a 4K word masked ROM TMS320C25 the TMS320E25 yields a high volume low cost production as a result of more migration paths for data An EPROM adapter socket part TMDX3270120 shown in Figure 8 is available to provide 68 pin to 28 pin conversion for programming the TMS320E25 Figure 8 EPROM Adapter Socket Key features ofthe EPROM cell include standard programming and verification For security against copyright violations the EPROM cell features an internal protection mechanism to prevent proprietary code from being read The protection feature can be used to protect reading the EPROM contents This section describes erasure fast programming and verification and EPROM protection and verification fast programming
43. against electrostatic discharges ESD of up to 2 kV according to Y MIL STD 883C Method 3015 however it is advised that precautions to be taken to avoid application of any voltage higher than maximum rated voltages to these high impedance circuits During storage or handling the device leads should shorted together or the device should be placed in conductive foam In a circuit unused inputs should always be connected to an appropriate logic voltage level preferably either Vcc or ground Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic Discharge Sensitive ESDS Devices and Assemblies available from Texas Instruments TEXAS 4 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 27 ADVANCE INFORMATION NOILVINYOSNI 5320 25 5320 25 5 5010 MAY 1987 REVISED NOVEMBER 1990 CLOCK CHARACTERISTICS AND TIMING The TMS32025 can use either its internal oscillator or an external frequency source for a clock internal clock option Theinternal oscillator is enabled by connecting a crystalacross X1 and X2 CLKIN see Figure 2 The frequency ofCLKOUT1 is one fourth the crystal fundamental frequency The crystal should be either fundamental or overtone mode and parallel resonant with an effective series resistance of 30 O a power dissipation of 1 mW and be specified at a load capacitance of 20 pF Note that ove
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45. and not tested NOTES 3 1 41 11 duty cycle of the serial port clock must within 40 60 TEXAS INSTRUMENTS 32 POST OFFICE BOX 1443 HOUSTON TEXAS 77001 5320 25 SPRS010B MAY 1987 REVISED NOVEMBER 1990 EPROM PROGRAMMING absolute maximum ratings over specified temperature range unless otherwise noted T Supply voltage range Vppt o PITT 0 6V to 15V Input voltage range on pins 24 and 25 0 3 15V 1 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions section of this specification is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability voltage values are with respect to GND recommended operating conditions NOM MA UNIT Vcc Programming mode supply voltage see Note 13 6 J v Read mode supply voltage 4 75 525 Vpp Programming mode supply voltage 12 12 5 13 Read mode supply voltage see Note 12 NOTES 12 Vpp can be connected to Vcc directly except in the program mode Vcc supply current in this case would be Icc Ipp During programming Vpp must be maintained at 12 5 V 0 25 V 13 must be applied before or at the sa
46. and verification The TMS320E25 EPROM cell is programmed using the same family and device codes as the TMS27C64 8K x 8 bit EPROM The TMS27C64 EPROM series are ultraviolet light erasable electrically programmable read only memories fabricated using HVCMOS technology The TMS27C64 is pin compatible with existing 28 pin ROMs and EPROMs The TMS320E25 like the TMS27C64 operates from a single 5 V supply in the read mode however a 12 5 V supply is needed for programming All programming signals are TTL level For programming outside the system existing EPROM programmers can be used Locations may be programmed singly in blocks or at random When programmed in blocks the data is loaded into the EPROM cell one byte at a time the high byte first and the low byte second 58 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 TMS320E25 SPRS010B MAY 1987 REVISED NOVEMBER 1990 Figure 9 shows the wiring conversion to program the TMS320E25 using the 28 pin pinout of the TMS27C64 The pin nomenclature table provides a description of the TMS27C64 pins The code to be programmed into the device should be serial mode The TMS320E25 uses 13 address lines to address the 4K word memory in byte format 9 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 TMS27C64 10 60 11 59 12 58 13 57 14 56 15 55 16 54 17 TMS320E25 CLKIN 18 68 Pin FZ 52 19 51 20 50 21 49 22 48 23 47 24 46
47. asynchronous inputs and can occur at any time during a clock cycle timing requirements over recommended operating conditions see Notes 3 and 16 UNIT tsu IN INT BIO RS setup before CLKOUT1 high Ge iom tw RS RS low pulse duration T Value derived from characterization data and not tested NOTES 3 Q 1 4 16 RS INT are asynchronous inputs occur at any time during a clock cycle HOLD TIMING switching characteristics over recommended operating conditions see Note 3 PARAMETER MN MAX UNIT HOLDA low after CLKOUT1 low 11 11 tdis AL A HOLDA low to address high impedance tdis CIL A Address high impedance after CLKOUT1 low HOLD mode see Note 17 td HH AH HOLD high to HOLDA high ten A CIL Address driven before CLKOUT1 low HOLD mode see Note 17 T Value derived from characterization data and not tested NOTES 3 Q 1 4 17 15 0 PS DS STRB RAW timings are included in timings referenced as address timing requirements over recommended operating conditions see Note 3 in MAX UNIT id C2H H HOLD valid after CLKOUT high ns NOTE 3 Q 1 4 te C TEXAS INSTRUMENTS 38 POST OFFICE BOX 1443 HOUSTON TEXAS 77001 5320 25 50 SPRS010B MAY 1987 REVISED NOVEMBER 1990 SERIAL PORT TIMING switching characteristics over recommended operating conditions see Note 3 PARAMET
48. bitrated The 8 bit memory mapped GREG global memory allocation register specifies part of the TMS320C2x s data memory as global external memory The contents of the register determine the size of the global memory space If the current instruction addresses an operand within that space BR is asserted to request control of the bus The length of the memory cycle is controlled by the READY line The TMS320C2x supports DMA direct memory access to its external program data memory using the HOLD and HOLDA signals Another processor can take complete control of the TMS320C2x s external memory by asserting HOLD low This causes the TMS320C2x to place its address data and control lines in a high impedance state and assert HOLDA On the TMS320C2x program execution from on chip ROM may proceed concurrently when the device is in the hold mode li TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 9 5320 SECOND GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 instruction set The TMS320C2x microprocessor implements a comprehensive instruction set that supports both numeric intensive signal processing operations well general purpose applications such as multiprocessing and high speed control The TMS32020 source code is upward compatible with TMS320C25 source code TMS32020 object code runs directly on the TMS320C25 For maximum throughput the next instruction is prefetched while the curr
49. bject code compatible with the TMS32020 The TMS320C25 s enhanced feature set greatly increases the functionality of the device over the TMS32020 Enhancements included 24 additional instructions 133 total eight auxiliary registers an eight level hardware stack 4K words of on chip program ROM a bit reversed indexed addressing mode and the low power dissipation inherent to the CMOS process An extended temperature range version TMS320C25GBA is also available The TMS320C25 50 is a high speed version of the TMS320C25 It is capable of an instruction cycle time of less than 80 ns Itis architecturally identical to the original 40 MHz version ofthe TMS320C25 and thus is pin for pin and object code compatible with the TMS320C25 The TMS320E25 is identical to the TMS320C25 with the exception that the on chip 4K word program ROM is replaced with a 4K word on chip program EPROM On chip EPROM allows realtime code development and modification for immediate evaluation of system performance 1 6 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 3 5320 SECOND GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 Key Features TMS32020 5 V GND 200 ns Instruction Cycle Time 544 Words of On Chip Data RAM 128K Words of Total Data Program Interrupts p Data 16 Memory Space RAM iulii Wait States for Communication to Slower Off Chip Processo
50. ccumulator Testa specified bit of a word in data memory One input to the ALU is always provided from the accumulator and the other input may be provided from the Product Register PR of the multiplier or the input scaling shifter which has fetched data from the RAM on the data bus After the ALU has performed the arithmetic or logical operations the result is stored in the accumulator The 32 bit accumulator is split into two 16 bit segments for storage in data memory Additional shifters at the output of the accumulator perform shifts while the data is being transferred to the data bus for storage The contents of the accumulator remain unchanged 1 6 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 5 TMS320 SECOND GENERATION DEVICES SPRSO010B MAY 1987 REVISED NOVEMBER 1990 functional block diagram TMS320C2x SYNC Program Bus IS R 255 o9g 16 16 2820 16 RAN PFC 16 QIR 16 STRB 16 16 READY STO 16 BR XE 5 164 ST1 16 HOLD T 16 16 RPTC 8 HOLDA 8 2 MCS 16 PC 16 TRIS MSC DR Bio 4 gt CLKR FSR 16 116 DX FS 16 16 16 ESX INT 2 0 Program 8x16 1 5806 R W AG 4 16 16 EPROM 16 DRR 16 A15 A0 4096 X 16 22 21 DXR 16 28 6 16 16 6 gt GREG 8 D15 D0 16 16 Dat
51. ck cycle If the specified timing is met the exact sequence shown will occur otherwise a delay of one CLKOUT2 cycle will occur TEXAS 4 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 53 ADVANCE INFORMATION NOILVINYOSNI 3ONVAQV 5320 SECOND GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 TYPICAL SUPPLY CURRENT CHARACTERISTICS FOR TMS320C25 vs f CLKIN Icc vs f CLKIN and Vcc Normal Operating Mode Powerdown Mode 170 80 160 TA 25 5 50 V 150 5 25 V 70 5 50 V 140 5 00 V 5 25 V 130 4 75 V 60 5 00 V 120 4 50 V lt 4 75 V 110 50 4 50 V 100 90 40 80 9 70 30 60 50 20 40 30 10 20 10 0 4 8 12 16 20 24 28 32 36 40 44 48 52 4 8 12 16 20 24 28 32 36 40 44 48 52 f CLKIN MHz f CLKIN MHz TMS320C25FNL PLCC reflow soldering precautions 54 Recent tests have identified an industry wide problem experienced by surface mounted devices exposed to reflow soldering temperatures This problem involves a package cracking phenomenon sometimes experienced by large e g 68 lead plastic leaded chip carrier PLCC packages during surface mount manufacturing This phenomenon occur if the TMS320
52. ding to MIL STD 883C 2 y Method 3015 however it is advised that precautions should be taken to avoid application of any voltage higher than maximum rated voltages to these high impedance circuits During storage or handling the device leads should be shorted together or the device should be placed in conductive foam In a circuit unused inputs should always be connected to an appropriated logic voltage level preferably either Vcc or ground Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic Discharge Sensitive ESDS Devices and Assemblies available from Texas Instruments TEXAS 4 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 21 ADVANCE INFORMATION 3ONVAQV TMS32020 5 5010 MAY 1987 REVISED NOVEMBER 1990 CLOCK CHARACTERISTICS AND TIMING The 532020 can use either its internal oscillator or an external frequency source for a clock internal clock option internal oscillator is enabled by connecting a crystal across X1 and X2 CLKIN see Figure 2 The frequency of CLKOUT1 is one fourth the crystal fundamental frequency The crystal should be fundamental mode and parallel resonant with an effective series resistance of 30 O a power dissipation of 1 mW and be specified at a load capacitance of 20 pF PARAMETER TEST CONDITIONS UNIT fx Input clock frequency TA 0 to 70
53. e air temperature range 1 0 to 70 Storage temperature range 55 to 150 T Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions section of this specification is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability t All voltage values are with respect to Vgs recommended operating conditions wax ww v electrical characteristics over specified free air temperature range unless otherwise noted Voi _towieveloutputvotage 8 v 20 Input current VI to 10 10 N TA 0 Vcc fx MAX Supply current Idle HOLD C Input capacitance Output capacitance All typical values are at Vcc 5 V TA 25 TEXAS INSTRUMENTS 34 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 5320 25 50 SPRS010B MAY 1987 REVISED NOVEMBER 1990 CLOCK CHARACTERISTICS AND TIMING The TMS320C25 50 can use either its internal oscillator or an external frequency source for a clock internal clock
54. ed by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary experti
55. ed in the TMS320C1x instruction set t These instructions are not included in the TMS32020 instruction set TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 15 5320 25 SPRS010B MAY 1987 REVISED NOVEMBER 1990 Table 3 TMS320C25 Instruction Set Summary concluded CONTROL INSTRUCTIONS DESCRIPTION NO INSTRUCTION BIT CODE ORDS 1 4 14 13 12 109 8 7 6 5 4 3 2 0 Test bit gt gt Test bit specified by T register Configure block as data memory Configure block as program memory Disable interrupt Enable interrupt Idle until interrupt Load status register STO Load status register ST1 No operation o Pop of stack to low accumulator Pop top of stack to data memory Push data memory value onto stack Push low accumulator onto stack Reset carry bit Reset hold mode lt 0 0 0 0 0 lt lt 0 0 lt lt 0 0 0 0 Reset overflow mode Repeat instruction as specified by data memory value Repeat instruction as specified immediate value Reset sign extension mode Reset test control flag Set carry bit Set hold mode Set overflow mode Store status register STO Store status register ST1 Set sign extension mode Set test control flag o Software interrupt 1 These instructions are not included in the TMS320C1x instructi
56. ee separate address spaces for program memory data memory and I O The on chip memory is mapped into either the 64K word data memory or program memory space depending upon the memory configuration see Figure 1 The CNFD configure block BO as data memory and CNFP configure block BO as program memory instructions allow dynamic configuration of the memory maps through software Regardless of the configuration the user may still execute from external program memory The TMS320C2x has six registers that are mapped into the data memory space a serial port data receive register serial port data transmit register timer register period register interrupt mask register and global memory allocation register 1 6 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 7 5320 SECOND GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 Program 0 0000h Interrupts and Reserved External 31 001Fh 32 0020h 65 535 FFFFh If MP MC 1 Microprocessor Mode Program 0 0000h Interrupts and Reserved External 31 001Fh 32 0020h External 65 279 0FEFFh 65 280 0FF00h EE REP ES On Chip Block BO 65 535 0FFFFh If MP MC 1 Microprocessor Mode Program 0 0000h interrupts 0 0000h and Reserved On Chip 31 001Fh 5 0005h 32 0020h 6 0006h On Chip T ROM EPROM 95 005Fh 4016 0FBOh 96 0060h 127 007Fh Reserved 128 0080h 4095 0FFFh 4096 100
57. ent one is being executed Since the same data lines are used to communicate to external data program or I O space the number of cycles may vary depending upon whether the next data operand fetch is from internal or external memory Highest throughput is achieved by maintaining data memory on chip and using either internal or fast external program memory addressing modes The TMS320C2x instruction set provides three memory addressing modes direct indirect and immediate addressing Both direct and indirect addressing can be used to access data memory In direct addressing seven bits of the instruction word are concatenated with the nine bits of the data memory page pointer to form the 16 bit data memory address Indirect addressing accesses data memory through the auxiliary registers In immediate addressing the data is based on a portion of the instruction word s In direct memory addressing the instruction word contains the lower seven bits of the data memory address This field is concatenated with the nine bits of the data memory page pointer to form the full 16 bit address Thus memory is paged in the direct addressing mode with a total of 512 pages each page containing 128 words Up to eight auxiliary registers ARO AR7 provide flexible and powerful indirect addressing five on the TMS32020 eight on the TMS320C25 To select a specific auxiliary register the Auxiliary Register Pointer ARP is loaded with a value from 0 to 7 for ARO
58. fetch and execution The TMS320 family s modification of the Harvard architecture allows transfers between program and data spaces thereby increasing the flexibility of the device This modification permits coefficients stored in program memory to be read into the RAM eliminating the need for a separate coefficient ROM It also makes available immediate instructions and subroutines based on computed values Increased throughput on the TMS320C2x devices for many DSP applications is accomplished by means of single cycle multiply accumulate instructions with a data move option up to eight auxiliary registers with a dedicated arithmetic unit and faster necessary for data intensive signal processing The architectural design of the TMS320C2x emphasizes overall speed communication and flexibility in processor configuration Control signals and instructions provide floating point support block memory transfers communication to slower off chip devices and multiprocessing implementations 32 bit ALU accumulator The 32 bit Arithmetic Logic Unit ALU and accumulator perform a wide range of arithmetic and logical instructions the majority of which execute in a single clock cycle The ALU executes a variety of branch instructions dependent on the status of the ALU or a single bitin a word These instructions provide the following capabilities Branch to an address specified by the accumulator Normalize fixed point numbers contained in the a
59. fore falling edge of STRB NOTES 3 f 4tc C 8 RS INT BIO asynchronous inputs can occur at any time during clock cycle However if the specified setup time is met the exact sequence shown in the timing diagrams will occur timing requirements over recommended operating conditions see Note 3 and 8 e 1 T value derived from characterization data and not tested NOTES 3 Q 1 4te C 8 RS INT and BIO are asynchronous inputs and can occur at any time during a clock cycle However if the specified setup time is met the exact sequence shown in the timing diagrams will occur HOLD TIMING switching characteristics over recommended operating conditions see Note 3 PARAMETER MIN TYP MAX UNIT id CiL AL HOLDA low after CLKOUT1 low tdis AL A HOLDA low to address three state tdis C1L A Address three state after CLKOUT1 low HOLD mode see Note 9 td HH AH HOLD high to HOLDA high len A C1L Address driven before CLKOUT1 low HOLD mode see Note 9 t Value derived from characterization data and not tested NOTES 3 Q t 4t c 9 A15 A0 PS DS IS STRB R W timings are all included in timings referenced as address timing requirements over recommended operating conditions see Note 3 td C2H H HOLD valid after CLKOUT2 high 3 NOTE3 1 46 TEXAS 4 INSTRUMENTS POST OFFI
60. frame Hermetic sealing is accomplished with glass The FZ package is intended for both socket or surface mounting Having a Sn Pb ratio of 60 40 the tin lead coated leads do not require special cleaning or processing when being surface mounted A 4 57 0 180 see Note 2 3 94 0 155 la B 3 55 0 140 3 05 0 120 1 02 0 040 45 gt 1 27 0 050 Typ see Note 3 A 0 81 0 032 0 66 0 026 _v 4 r 0 51 0 020 0 64 0 025 0 36 0 014 R Max 4 1 016 0 040 Min 3 Places Ref see Note 1 Thermal Resistance Characteristics 3 05 0 120 PARAMETER MAX UNIT 2 29 0 090 Junction to free air thermal resistance 49 Seating Plane see Note 4 Junction to case thermal resistance JEDEC NO OF OUTLINE TERMINALS MIN MAX 12 32 12 57 10 92 11 56 10 41 10 92 087 0 485 0 465 0430 0 455 0 410 0 430 17 40 17 65 16 00 16 64 15 49 16 00 EN 0 685 0695 0630 0 655 0 610 0 630 25 02 25 27 23 62 24 26 23 11 23 62 0 985 0 995 0 930 0 955 0 910 0 930 ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES C W NOTES 1 Glass is optional and the diameter is dependent on device application 2 Centerline of center pin each side is within 0 10 0 004 of p
61. ftware interrupt TRAP instruction Interrupts are prioritized with reset RS having the highest priority and the serial port transmit interrupt XINT having the lowest priority All interrupt locations are on two word boundaries so that branch instructions can be accommodated in those locations if desired A built in mechanism protects multicycle instructions from interrupts If an interrupt occurs during a multicycle instruction the interrupt is not processed until the instruction is completed This mechanism applies to instructions that are repeated and to instructions that become multicycle due to the READY signal external interface The 5320 2 supports a wide range of system interfacing requirements Program data and address spaces provide interface to memory 1 0 thus maximizing system throughput design is simplified by having I O treated the same way as memory devices are mapped into the I O address space using the processor s external address and data buses in the same manner as memory mapped devices Interface to memory and devices of varying speeds is accomplished by using the READY line When transactions are made with slower devices the TMS320C2x processor waits until the other device completes its function and signals the processor via the READY line Then the TMS320C2x continues execution A full duplex serial port provides communication with serial devices such as codecs serial A D converters
62. ing requirements over recommended operating conditions see Note 3 NOM UNI i SCK Serial port clock CLKX CLKR cycle time tr SCK Serial port clock CLKX CLKR rise time ns tw SCK Serial port clock CLKX CLKR low pulse duration see Note 11 150 12 000 ns tw SCK Serial port clock CLKX CLKR high pulse duration see Note 11 150 12 000 ns tsu FS FSX FSR setup time before CLKX CLKR falling edge TXM 0 20 ns th FS FSX FSR hold time after CLKX CLKR falling edge TXM 0 20 ns tsu DR DR setup time before CLKR falling edge 2 ns th DR DR hold time after CLKR falling edge T Value derived from characterization data minimum fsx at test 825 kHz t Value derived from characterization data and not tested NOTES 3 1 4 11 duty cycle of the serial port clock must within 40 60 TEXAS INSTRUMENTS 26 POST OFFICE BOX 1443 HOUSTON TEXAS 77001 5320 25 5320 25 5 5010 MAY 1987 REVISED NOVEMBER 1990 absolute maximum ratings over specified temperature range unless otherwise noted T Supply voltage range VIT 0 3 7 V Input voltage range TMS320E25 pins 24 25 0 3V to 15 V All other Inp ls 335 4e egeret etait aed 0 3Vto7 V Output voltage range 0 3Vto7V Continuous power dissipation
63. lists the development support products for the second generation TMS320 devices System development may begin with the use of the simulator Software Development System SWDS or emulator XDS along with an assembler linker These tools give the TMS320 user various means of evaluation from software simulation of the second generation TMS320s simulator to full speed in circuit emulation with hardware and software breakpoint trace and timing capabilities XDS Software and hardware can be developed simultaneously by using the macro assembler linker C compiler and simulator for software development the XDS for hardware development and the Software Development System for both software development and limited hardware development Many third party vendors offer additional development support for the second generation TMS320s including assembler linkers simulators high level languages applications software algorithm development tools application boards software development boards and in circuit emulators Refer to the TMS320 Family Development Support Reference Guide SPRU011A for further information about TMS320 development support products offered by both Texas Instruments and its third party suppliers Additional support for the TMS320 products consists of an extensive library or product and applications documentation Three day DSP design workshops are offered by the TI Regional Technology Centers RTCs These workshops provide insigh
64. me time as Vpp and removed after or at the same time as Vpp This device must not be inserted into or removed from the board when Vpp or Vcg is applied electrical characteristics over specified temperature range unless otherwise noted PARAMETER TEST CONDITIONS MIN MAX UNIT Ipp2 Vpp supply current during program pulse 13V 30 50 All typical values for are at Vcc 5 V TA 25 recommended timing requirements for programming 25 C Vcc 6 V Vpp 12 5 V see Notes 14 and 15 derived from characterization data and not tested NOTES 14 For all switching characteristics and timing measurements input pulse levels are 0 4 V to 2 4 V and Vpp 12 5 V 0 5 V during programming 15 Common test conditions apply for tdis G except during programming TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 33 ADVANCE INFORMATION NOILVINYOSNI 3ONVAQV 5320 25 50 SPRS010B MAY 1987 REVISED NOVEMBER 1990 absolute maximum ratings over specified temperature range unless otherwise noted T Supply voltage range 0 3V to 7 V Input voltage range 2c see inde ERE CUR ERR sewed 0 3Vto7 V Output voltage range 0 3Vto7V Continuous power dissipation 1 5W Operating fre
65. nal Security Mechanism TMS320E25 Eight Auxiliary Registers With Dedicated 68 to 28 Pin Conversion Adapter Socket Arithmetic Unit CMOS Technology I e ae Addressing Moda Tor 68 Pin Grid Array PGA Package TMS320C25 Double Buffered Serial Port e 68 Lead Plastic Leaded Chip Carrier PLCC Package TMS320C25 TMS320C25 50 68 Lead CER QUAD Package TMS320E25 TEXAS INSTRUMENTS 4 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 TMS320 SECOND GENERATION DEVICES SPRSO010B MAY 1987 REVISED NOVEMBER 1990 Table 1 provides an overview of the second generation TMS320 processors with comparisons of memory cycle timing power package type technology and military support For specific availability contact the nearest TI Field Sales Office Table 1 TMS320 Second Generation Device Overview vot TYP OFF CHIP TIMER POWER RAM ROM EPROM PROG DATA SER PAR mw PLCC CER QUAD T SER serial PAR parallel DMA direct memory access CON concurrent DMA t Military version available contact nearest TI Field Sales Office for availability Military version planned contact nearest TI Field Sales Office for details architecture TMS320 family utilizes modified Harvard architecture for speed and flexibility In a strict Harvard architecture program and data memory lie in two separate spaces permitting a full overlap of instruction
66. ny time during a clock cycle However if the specified setup time is met the exact sequence shown in the timing diagrams will occur HOLD TIMING switching characteristics over recommended operating conditions see Note 3 PARAMETER MIN TYP MAX UNIT ta C1L aL HOLDA low after CLKOUT1 low 25t 25 tdis AL A HOLDA low to address three state ns tdis C1L A Address three state after CLKOUT1 low HOLD mode see Note 9 sot len A C1L Address driven before CLKOUT1 low HOLD mode see Note 9 T Value derived from characterization data and not tested NOTES 8 Q T 4tc C 9 A15 A0 PS DS 15 STRB and RAW timings are all included in timings referenced as address timing requirements over recommended operating conditions see Note 3 td C2H H X HOLD valid after CLKOUT2 high AR NOTE 3 1 4tc C TEXAS 4 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 25 ADVANCE INFORMATION NOILVINYOSNI 532020 SPRS010B MAY 1987 REVISED NOVEMBER 1990 SERIAL PORT TIMING switching characteristics over recommended operating conditions see Note 3 PARAMETER MIN TYP MAX UNIT td CH DX DX valid after CLKX rising edge see Note 10 tqFL DX DX valid after FSX falling edge 0 see Note 10 8 ns td CH FS FSX valid after CLKX rising edge TXM 1 NOTES 3 1 4tc C 10 The last occurrence of FSX falling and CLKX rising tim
67. on set t These instructions are not included in the TMS32020 instruction set TEXAS 4 INSTRUMENTS 16 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 TMS32020 SPRS010B MAY 1987 REVISED NOVEMBER 1990 TMS32020 PRODUCT NOTIFICATION Texas Instruments has identified an unusual set of circumstances that will cause the BIT Test Bit instruction on the TMS32020 to affect the contents of the accumulator ideally the BIT instruction should not affect the accumulator This set of conditions is 1 The overflow mode is set the OVM status register bit is set to one 2 And the two LSBs of the BIT instruction opcode word are zero a When direct memory addressing is used every fourth data word is affected all other locations are not affected b When indirect addressing is used the two LSBs will be zero if a new ARP is not selected or if a new ARP is selected and that ARP is O or 4 3 And adding the contents of the accumulator with the contents of the addressed data memory location shifted by 2 bit code causes an overflow of the accumulator If all of these conditions are met the contents of the accumulator will be replaced by the positive or negative saturation value depending on the polarity of the overflow Various methods for avoiding this phenomenon are available TMS32020 is not in the saturation mode when the instruction is executed the device operates properly and the accumulator is not affected
68. r Memories peer Interface Source Code Compatible With the TMS320C1x 32 BIT ALU ACC Serial Single Cycle Multiply Accumulate Instructions e Interface 9 Repeat Instructions Global Data Memory Interface Timer Block Moves for Data Program Management an oss Tu s With Dedicated On Chip Clock Generator Serial Port for Multiprocessing or Interfacing Single 5 Supply to Codecs Serial Analog to Digital NMOS Technology Converters etc 68 Grid Array PGA Package Key Features TMS320C25 TMS320C25 50 TMS320E25 80 ns Instruction Cycle Time TMS320C25 50 5 V GND 100 ns Instruction Cycle Time TMS320C25 Y Y 4 Words of On Chip Secure Program EPROM TMS320E25 Interrupts 256 Word 288 Word 4 Words of On Chip Program TM 5320 25 544 Words of RAM E 128K Words of Total Program Data Interface Memory Space Multiplier Wait States for Communications to 32 Bit ALU ACC Slower Off Chip Memories Object Code Compatible With the TMS32020 Source Code Compatible With TMS320C1x 24 Additional Instructions to Support Adaptive Filtering FFTs and Extended Precision Arithmetic On Chip Clock Generator Interface Shifters Address 16 Block Moves for Data Program Management Single 5 V Supply Single Cycle Multiply Accumulate Instructions nter
69. r not zero Branch if TC bit 0 Branch if TC bit 0 Branch on carry 8 1 0 1 1 Branch if accumulator 2 0 Branch if accumulator 0 Branch status 0 Branch if accumulator lt 0 Branch if accumulator 0 Branch on no carry Branch if no overflow Branch if accumulator 0 Branch on overflow Branch if accumulator 0 N N m mm mm m m NY NY YO m O O O O O O 0 0 Call subroutine indirect k c subroutine W O V V V V V V V V V V V V V Return from subroutine INSTRUCTION BIT CODE DESCRIPTION 13 12 1 10 9 8 7 6 5 4 3 2 Block move from data memory to data memory Block move from program memory to data memory Data move in data memory Format serial port registers Input data from port gt vv Output data to port U gt Reset serial port frame synchronization mode Reset serial port transmit mode Reset external flag Set serial port frame synchronization mode Set serial port transmit mode Set external flag O O O O O O O O O Table read O O O O gt Qj cx ko k Table write 1 These instructions are not includ
70. roduct information The TMS320 DSP bulletin board service provides access to large amounts of information pertaining to the TMS320 family Refer to the TMS320 Family Development Support Reference Guide SPRU011A for further information about TMS320 documentation To receive copies of second generation TMS320 literature call the Customer Response Center at 1 800 232 3200 specification overview The electrical specifications for the TMS32020 TMS320C25 TMS320E25 and TMS320C25 50 are given in the following pages Note that the electrical specifications for the 5320 25 are identical to those for the TMS320C25 with the addition of EPROM related specifications A summary of differences between TMS320C25 and TMS320C25 50 specifications immediately follows the TMS320C25 50 specification 20 TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 TMS32020 SPRSO010B MAY 1987 REVISED NOVEMBER 1990 absolute maximum ratings over specified temperature range unless otherwise noted t Supply voltage range Vent i d d did dnd 0 3Vto7 V Input voltage trange ie ere dee aypa q asa Cn 0 3V to 7 V Output voltage range 0 3Vto7V Continuous power dissipation 2W Operating free air temperature range
71. rtone crystals require an additional tuned LC circuit see the application report Hardware Interfacing to the TMS320C25 SPRAO144A C2 TA 0 C to 70 t The serial port was tested at a minimum frequency of 1 25 MHz However the serial port was fully static but will properly function down to fsx 0 Hz Crystal Figure 2 Internal Option external clock option An external frequency source can be used by injecting the frequency directly into X2 CLKIN with X1 left unconnected The external frequency injected must conform to the specifications listed in the following table switching characteristics over recommended operating conditions see Note 3 PARAMETER MIN TYP UNIT 5 2Q td CIH C high to CLKOUT1 CLKOUT2 STRB high low CLKOUT1 CLKOUT2 STRB fall time DIENEN CLKOUT1 CLKOUT2 STRB rise time CLKOUT1 CLKOUT2 low pulse duration 2Q 8 20 8 CLKOUT1 CLKOUT2 high pulse duration 2Q 8 20 20 8 ns id C1 C2 CLKOUT1 high to CLKOUT2 low CLKOUT2 high to CLKOUT1 high etc Q 5 Q Q 5 ns NOTE 3 Q 1 4tc C MAX 0 CLKOUT1 CLKOUT2 cycle time 30 5 5 ns ns ns ns ns TEXAS INSTRUMENTS 28 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 5320 25 5320 25 5 5010 MAY 1987 REVISED NOVEMBER 1990 timing requirements over recommended operating conditions see Note 3 r MIN NOM MA UNIT te Cl CLKIN cycle time 24 4 150 20 tw CIL CLKIN low pulse dura
72. rystal X2 CLKIN Input to internal oscillator from crystal or external clock CLKOUT1 Master clock output crystal or CLKIN frequency 4 CLKOUT2 A second clock output signal 015 00 16 bit data bus 015 MSB through DO LSB Multiplexed between program data and I O spaces A15 A0 16 bit address bus A15 MSB through A0 LSB PS DS 15 Program data and space select signals R W Read write signal STRB Strobe signal RS Reset input INT2 INTO External user interrupt inputs MP MC Microprocessor microcomputer mode select pin MSC Microstate complete signal Interrupt acknowledge signal READY Data ready input Asserted by external logic when using slower devices to indicate that the current bus transaction is complete BR Bus request signal Asserted when the TMS320C2x requires access to an external global data memory space External flag output latched software programmable signal Hold input When asserted TMS320C2x goes into an idle mode and places the data address and control lines in the high impedance state Hold acknowledge signal Synchronization input Branch control input Polled by BIOZ instruction Serial data receive input Clock for receive input for serial port Frame synchronization pulse for receive input Serial data transmit output Clock for transmit output for serial port Frame synchronization pulse for transmit Configuration as either an input or an output t I O Z denotes input output high impedance state
73. s continuously clocked by CLKOUT1 on the TMS320C25 The timer is clocked by CLKOUT1 4 onthe TMS32020 A timer interrupt TINT is generated every time the timer decrements to zero The timer is reloaded with the value contained in the period PRD register within the next cycle after it reaches zero so that interrupts may be programmed to occur at regular intervals of PRD 1 cycles of CLKOUT 1 on the TMS320C25 or 4 x PRD x CLKOUT 1 cycles on the TMS32020 memory control The TMS320C2x provides a total of 544 16 bit words of on chip data RAM divided into three separate blocks BO B1 and B2 Of the 544 words 288 words blocks B1 and B2 are always data memory and 256 words block are programmable as either data or program memory data memory size of 544 words allows the TMS320C2x to handle a data array of 512 words 256 words if on chip RAM is used for program memory while still leaving 32 locations for intermediate storage When using block as program memory instructions can be downloaded from external program memory into on chip RAM and then executed When using on chip program RAM ROM EPROM or high speed external program memory the TMS320C2x runs at full speed without wait states However the READY line can be used to interface the TMS320C2x to slower less expensive external memory Downloading programs from slow off chip memory to on chip program RAM speeds processing while cutting system costs The TMS320C2x provides thr
74. se in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific products are designated by as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obt
75. sign documentation for the second generation devices of the TMS320 family This facilitates the selection of the devices best suited for user applications by providing all specifications and special features for each TMS320 member This data sheetis divided into four major sections architecture electrical specifications 5 and CMOS timing diagrams and mechanical data In each of these sections generic information is presented first followed by specific device information An index is provided for quick reference to specific information about a device sampling or preproduction phase of development Characteristic data and other specifications are subject to ADVANCE INFORMATION concerns new products in the i Copyright 1991 Texas Instruments Incorporated change without notice TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 1 ADVANCE INFORMATION 5320 SECOND GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 PGA AND PLCC CER QUAD PIN ASSIGNMENTS A2 L3 29 D4 0114 DR J1 24 1 10 oum cross STAG e oux Bas WcK ran mno rina 012 Wr voo 1808 or om 0884 805 T On the TMS32020 MP MC must be connected to oz Voc 5 V supply pins Vss Ground pins X1 Output from internal oscillator for c
76. ss not exceed two solder cycles and the temperature not exceed 220 C If you have any additional questions or concerns please contact your local TI representative TEXAS INSTRUMENTS POST OFFICE BOX 1443 HOUSTON TEXAS 77001 TMS320 SECOND GENERATION DEVICES SPRS010B MAY 1987 REVISED NOVEMBER 1990 MECHANICAL DATA 68 pin GB grid array ceramic package TMS32020 TMS320C25 28 448 1 120 27 432 1 080 Thermal Resistance Characteristics 17 02 0 670 Nom PARAMETER MAX UNIT Junction to free air thermal resistance 36 C W 28 448 1 120 Junction to case C W 27 432 1 080 thermal resistance 17 02 0 670 Nom 4 953 0 195 2 032 0 080 1 397 0 055 Max 3 302 0 130 1 575 0 062 2 794 0 110 0 508 0 020 1 473 0 058 0 406 0 016 1 524 0 060 Nom 4 Places 1 10 11 127 0 050 gt ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES 1 6 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 55 ADVANCE INFORMATION NOILVINHOHMNI TMS320C25 TMS320C25 50 SPRS010B MAY 1987 REVISED NOVEMBER 1990 68 lead plastic leaded chip carrier package TMS320C25 and TMS320C25 50 Seating Plane 27 0 050 T P 0 25 0 010 R Max see Note B 3 Places 24 33 0 956 24 13
77. t into the architecture and the instruction set of the second generation TMS320s as well as hands on training with the TMS320 development tools When technical questions arise regarding the TMS320 family contact the Texas Instruments TMS320 Hotline at 713 274 2320 Or keep informed on the latest TI and third party development support tools by accessing the DSP Bulletin Board Service BBS at 713 274 2323 The BBS serves 2400 1200 and 300 bps modems Also TMS320 application source code may be downloaded from the BBS TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 TMS320 SECOND GENERATION DEVICES SPRSO010B MAY 1987 REVISED NOVEMBER 1990 Table 4 TMS320 Second Generation Software and Hardware Support SOFTWARE TOOLS PART NUMBER Macro Assembler Linker IBM MS PC DOS TMDS3242850 02 VAX VMS TMDS3242250 08 VAX ULTRIX TMDS3242260 08 SUN UNIX TMDS3242550 08 Simulator IBM MS PC DOS TMDS3242851 02 VAX VMS TMDS3242251 08 C Compiler IBM MS PC DOS TMDX3242855 02 VAX VMS TMDX3242255 08 VAX ULTRIX TMDX3242265 08 SUN UNIX TMDX3242555 08 Digital Filter Design Package DFDP IBM PC DOS DFDP IBM002 DSP Software Library IBM MS PC DOS TMDC324081 2 12 VAX VMS TMDC3204212 18 HARDWARE TOOLS PART NUMBER Analog Interface Board 2 AIB2 RTC AIB320A 06 Analog Interface Board Adaptor RTC ADP320A 06 EPROM Programmer Adaptor Socket 68 to 28 pin TMDX3270120 Software Development System SWDS TMDX3268821
78. ter Exclusive OR with accumulator Exclusive OR immediate with accumulator with shift Zero accumulator Zero low accumulator and load high accumulator Zero low accumulator and load high accumulator with rounding Zero accumulator and load low accumulator with sign extension suppressed INSTRUCTION BIT CODE 14 13 12 109 8 7 6 5 4 3 2 0 AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS MNEMONIC DESCRIPTION NO WORDS 1 Add to auxiliary register short immediate Compare auxiliary register with auxiliary register ARO Load auxiliary register Load auxilliary register short immediate Load auxilliary register pointer Load data memory page pointer Load data memory page pointer immediate Load auxiliary register long immediate Modify auxiliary register Store auxiliary register Subtract from auxiliary register short immediate T These instructions are not included in the TMS320C1x instruction set t These instructions are not included in the TMS32020 instruction set INSTRUCTION BIT CODE 14 13 12 109 8 7 6 5 4 3 2 0 lt 4 0q _R 0 000000 0 1 011 lt D 04 R 4 D 1 1 4 K TEXAS INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 13 5320 25 SPRS010B MAY 1987 REVISED NOVEMBER 1990 Table 3 TMS320C25 Instruction Set Summary continued T REGISTER P REGISTER AND MULTIPLY INSTRUCTIONS NO INSTRUCTION BIT
79. ting the E G PGM and A4 pins high Vpp and EPT to 2 5 V 0 5 V and pulsing Q8 low The complete sequence of operations involved in programming the RBIT is shown in the flowchart of Figure 12 The required setups in the figure are detailed in Table 6 1 6 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 63 ADVANCE INFORMATION 5320 25 SPRS010B 1987 REVISED NOVEMBER 1990 Program One Pulse of 3X ms Duration Program One 1 ms Pulse Verify RBIT Device Device Failed Passed Protect Setup NOILVINYOSNI 3ONVAGV Figure 12 EPROM Protect Flowchart protect verify Protect verify is used following the EPROM protect to verify correct programming of the RBIT see Figure 12 When using protect verify Q8 outputs the state of the When RBIT 1 the EPROM is unprotected when RBIT 0 EPROM is protected The EPROM protect and verify timings are shown in Figure 13 TEXAS INSTRUMENTS 64 POST OFFICE BOX 1443 HOUSTON TEXAS 77001 TMS320E25 5 5010 MAY 1987 REVISED NOVEMBER 1990 4 Protect Verify I yy VIH PGM VIL E VIH G VIL 08 2 HI Z 2 R ViL VoL Vss YY YY YW YYW YW NNN M NZ NZ NZ YW YW YW YW WW NZ NZ NZ NS VIH Figure 13 EP
80. tion tc CI 50 ns see Note 4 tw CIH CLKIN high pulse duration 50 ns see Note 4 isuS setup time before CLKIN low th S SYNC hold time from CLKIN low 8 t Value derived from characterization data and not tested NOTES 3 Q 1 4te C 4 CLKIN duty cycle tr CI tw CIH l te cI must be within 40 60 5V TMS320C25 fcrystal 10 74HC04 4 7 F11 CLKIN lt 1 d 20pF 0 1uF 47 pF 74AS04 eS 10 lt 1 jt forysta MHz TMS320C25 40 96 TMS320C25 50 51 20 TMS320E25 40 96 Figure 3 External Clock Option Shown above is a crystal oscillator circuit suitable for providing the input clock signal to the TMS320C25 TMS320E25 and TMS320C25 50 Please referto Hardware Interfacing to the TMS320C25 document number SPRAO0144 for details on circuit operation 2 15 V 2 RL 8250 From Output Under Test N o Test Point CL 100 pF Figure 4 Test Load Circuit TEXAS 4 INSTRUMENTS POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 29 ADVANCE INFORMATION NOILVINHOHMNI 3ONVAQV TMS320C25 TMS320E25 SPRS010B MAY 1987 REVISED NOVEMBER 1990 20V 24 VOH Min 1 88 V lt 2 2 V 7 0 92 V 0 8 V Vip V Max 0 80V IL 0 6V oL 0 0 a Input b Output Figure 5 Voltage Reference Levels MEMORY AND PERIPHERAL INTERFACE TIMING switching characteristics o
81. uments Incorporated and its subsidiaries reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information publish
82. unctions TEXAS INSTRUMENTS 62 POST OFFICE BOX 1443 9 HOUSTON TEXAS 77001 TMS320E25 SPRSO010B MAY 1987 REVISED NOVEMBER 1990 Table 6 TMS320E25 Protect and Verify EPROM Mode Levels SIGNAL T TMS320E25 PIN TMS27C64 PIN ROM PROTECT PROTECT VERIFY V E 2 e gt 27 VH Vd Do 12 ve Ve maa CiN 5 O 00 Les sa T Lex ssa ass 1 31 r 6 VH X aao 32596 to x T In accordance with TMS27C64 LEGEND TTL high level TTL low level 5 V 0 25 V Vpp 12 5 V z 0 5 V X don t care PULSE low going TTL level pulse RBIT ROM protect bit EPROM protect The EPROM protect facility is used to completely disable reading of the EPROM contents to guarantee security of propietary algorithms This facility is implemented through a unique EPROM cell called the RBIT EPROM protect bit cell Once the contents to be protected are programmed into the EPROM the RBIT is programmed disabling access to the EPROM contents and disabling the microprocessor mode on the device Once programmed the RBIT can be cleared only by erasing the entire EPROM array with ultraviolet light thereby maintaining security of the propietary algorithm Programming the RBIT is accomplished using the EPROM protect cycle which consists of set
83. ver recommended operating conditions see Note 3 1 6 STRB 1 if STRB is present ns td C2 S CLKOUT2 to STRB if STRB is present n tsu A Address setup time before STRB low see Note 5 n th A Address hold time after STRB high see Note 5 Qa 3 tdis D Data bus three state after STRB high write cycle T value derived from characterization data and not tested NOTES 3 Q 1 4tc C 5 15 0 PS DS IS RAN and BR timings are all included in timings referenced as address 6 Delays between CLKOUT1 CLKOUT2 edges and STRB edges track each other resulting in tw SL and tw SH being 2Q with no wait states S S timing requirements over recommended operating conditions see Note 3 mp ta M R READY valid after MSC valid NOTES 3 Q 1040 5 15 0 PS DS IS RAN and BR timings are all included in timings referenced as address 7 Read data access time is defines as ta A tsu A tw SL tsu D R TEXAS INSTRUMENTS 30 POST OFFICE BOX 1443 HOUSTON TEXAS 77001 5320 25 5320 25 5 5010 MAY 1987 REVISED NOVEMBER 1990 RS INT BIO AND XF TIMING switching characteristics over recommended operating conditions see Note 3 and 8 PARAMETER MIN TYP MAX UNIT ta RS CLKOUT low to reset state entered CLKOUT1 to IACK valid 6 0 12 td XF XF valid be

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