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Texas Instruments TCM4300 User's Manual

1. 2 1 Absolute Maximum Ratings Over Operating Free Air Temperature Range 2 2 Dissipation Rating Table 2 3 Recommended Operating Conditions 2 4 Electrical Characteristics Over Full Range Of Operating Conditions 2 4 1 Power Consumption 2 4 2 Reference Characteristics 2 4 3 Terminal Impedance 2 4 44 RXIP RXIN RXQP and RXQN Inputs AVDD 3 V 4 5 V 5 V 2 4 5 Transmit and Channel Outputs 2 4 6 Auxiliary D A Converters 2 4 7 Auxiliary D A Converters Slope AGC AFC PWRCONT 2 4 8 Auxiliary D A Converters Slope 2 4 9 RSSI Battery A D 2 5 Operating Characteristics Over Full Range of Operating Conditions 2 5 1 Receive RX Channel Frequency Response RXQ Input in Digital Mode 2 5 2 Receive RX Channel Frequency Response FM Input Analog 2 5 3 Transmit TX Channel Frequency Response Digital Mode 2 5 4 Transmit TX Channel Frequency Response Analog Mode Para
2. 4 18 4 14 Microcontroller DSP Communications 4 20 4 15 Microcontroller Register Map 4 21 4 16 Wide Band Data Control Register 4 22 4 17 Microcontroller Status and Control Registers 4 23 4 48 LOD Gontrast uses eee oper Lr bns bee eee 4 24 4 19 DSP Register Map 4 25 4 20 Wide Band Data Registers 4 26 4 21 Base Station Offset Register 4 26 4 22 DSP Status and Control Registers 4 27 423 ROSEI aj erige ett 4 28 4 23 1 Power On 4 28 4 23 2 Internal Reset State 4 28 4 24 Microcontroller Interface 4 29 4 24 1 Intel Microcontroller Mode Of Operation 4 29 4 24 2 Mitsubishi Microcontroller Mode of Operation 4 30 4 24 3 Motorola Microcontroller Mode of Operation 4 30 5 Data 5 1 3 9 4300 to Microcontroller Interface Timing Requirements
3. Sampling frequency SINT digital mode 486 Km Sampling frequency SINT analog mode o amp Receive erorvectormagniude EVM 66 ND m Signaltonoisepusdsiorion romanse 108 s dcofsetvotage 6 m FM input sensitivity for full scale 14 kHz FM input dc offset wrt VHR o o rs FM input idle channel noise below full scale input Fuganeror 1 Power supply rejection f 0 kHz to 15 kHz 1 Provides 12 dB headroom for AGC fading conditions It is recommended that the single ended output of an external FM discriminator be capacitively coupled to the FM terminal for analog mode voice and WBD reception An external bias resistor is needed to bias the FM terminal to VHR The signal at this terminal is conveyed to the Q side of the receiver using the multiplexer and the other Q input is connected internally to the VHR reference voltage The input of the receive section circuitry is disabled in the analog mode The FM signal passes through the antialiasing filter as specified in Table 4 3 before passing through the A D converter The signal at the FM terminal is also routed directly to the WBD demodulator through a low pass filter LPF with the 3 dB point at 270 kHz Table 4 3 Receive RX Channel Frequency Response FM Input in Analog Mode PARAMETER TEST CONDITIONS
4. UNIT 0 kHz to 6 kHz see Note 1 Frequency response 2 5 V peak to peak 20 kHz to 30 kHz see Note 2 34 kHz to 46 kHz see Note 3 Peak to peak group delay distortion 2 5 V peak to peak 0 kHz to 6 kHz 2 us Absolute channel delay 2 5 V peak to peak 0 kHz to 6 kHz NOTES 1 Ripple magnitude 2 Stopband 3 Stopband and multiples of stopband The VHR can provide a bias voltage for the received inputs when capacitively coupled from the RF section To meet noise requirements the VHR output should have an external decoupling capacitor connected to ground The VHR output buffer is enabled by the OR of TXEN FMVOX and IQRXEN The VHR output is high impedance otherwise In the digital mode both the and Q receive sides are enabled Table 4 4 lists the receive channel frequency response Table 4 4 Receive RX Channel Frequency Response RXI RXQ Input in Digital Mode PARAMETER TEST CONDITIONS MAX UNIT 0 kHz to 8 kHz see Note 4 0 5 0 75 t1 26 30 46 8 kHz to 15 kHz see Note 4 When the and Q sample conversion is complete and the data is placed in the and sample registers the SINT interrupt line is asserted to indicate the presence of that data This occurs at 48 6 kHz rate in the digital mode and at 40 kHz rate in the analog mode In the analog mode only the RXQ conversion path is used and the RXI path is powered down Frequenc 16 2 kHz to 18 kHz see Note 2
5. receiver circuits and connects the receivers Q channel input to FM see Figure 4 9 5 R W FMRXEN FM receiver enable FMRXEN is connected to bit 5 see Figure 4 9 Transmitter enable TXEN is connected to bit 3 When TXEN is 1 it enables 3 R W TXEN 1 power to the internal transmitter circuits and when TXEN is 0 it disables 0 power to the internal transmitter circuits see Figure 4 9 2 OUT1 Output 1 OUT1 is a user defined general purpose data or control signal Receive channel offset When RXOF 1 it disconnects the RXIP RXIN 1 RXQP and RXQN terminals from receive channel and shorts internal RXIP to RXIN and to RXQN It provides the capability of measuring the dc offset of the receive channel Analog loop back When ALB 1 it disconnects the RXIP RXIN RXQP R W and RXQN terminals from the internal receive channels and connects the corresponding internal signals to attenuated copies of the TXIP TXIN TXQP and TXQN signals The attenuation factor is 8 Q receiver enable The IQRXEN is connected to bit 4 When IQRXEN is 1 itenables 1 power to the and sides of the internal receiver circuits 4 R W and when IQRXEN is 0 it disables 0 power to the and Q sides of the internal receiver circuits see Figure 4 9 4 27 4 23 Reset A low on RSINL causes the TCM4300 internal registers to assume their reset values The power on
6. 4 1 4 1 Data ees a de RE UNES 4 1 4 2 RECEIVE Section e hates ea en 4 1 4 3 Transmit 4 3 4 4 Transmit Burst Operation Digital Mode 4 5 4 5 Transmit And Q Output 4 7 4 6 Wide Band Data Demodulator 4 7 4 7 Wide band Data Interrupts 4 8 4 8 Wide band Data Demodulator General Information 4 9 4 9 Auxiliary DACs LCD Contrast 4 11 4 10 RSSI Battery Monitor 4 11 4 11 Timing And Clock 4 11 4 11 1 Clock Generation 4 12 4 11 2 Speech Codec Clock Generation 4 12 4 11 3 Microcontroller Clock 4 12 4 11 4 Sample Interrupt 4 12 4 11 5 Phase Adjustment Strategy 4 13 4 12 Frequency Synthesizer Interface 4 15 4 13 Power Control
7. gt 4 97 tn R W DSPRW DSPA DSPD gt tsu W lt P thw Figure 3 11 TCM4300 to DSP Interface Write Cycle 4 Principles of Operation This section describes the operation of the TCM4300 in detail NOTE Timing diagrams and associated tables are contained in Section 3 of this data manual 41 Data Transfer The interface to both the system digital signal processor and microcontroller is in the form of 2s complement 4 2 Receive Section The mode of operation is determined by the state of the MODE FMVOX IQRXEN and FMRXEN bits of the DStatCtrl register as shown in Table 4 1 Table 4 1 TCM4300 Receive Channel Control Signals omm In the digital mode MODE 1 the receive section accepts RXIP RXIN RXQP and RXQN analog inputs These inputs are passed to continuous time antialiasing filters AAF baseband filtering and A D conversion blocks and then to sample registers where 10 bit registers can be read The sample rate is 48 6 ksps In the analog mode MODE 0 the FMVOX bit of the DStatCtrl register enables or disables the Q side of the receiver channel and the FMRXEN bit controls the external functions In the digital mode IQRXEN enables both the and receive channels and external functions as well To save power the receive and Q channels are enabled separately This operation occurs because in the analog mode only the Q channel is used When
8. ness 65 to 150 C Lead temperature 1 6 mm 1 16 inch from case 10 seconds 260 C 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTES 1 Voltage values are with respect DVss 2 Maximum supplied voltage should not exceed 6 V 3 Voltage values are with respect to AVss 2 2 Dissipation Rating Table PACKAGE lt 25 C DERATING FACTOR 85 FOWERHATINS ABOVE Ta 25 C POWER RATING 1530 mW 15 25 mW C 615 mW 2 1 2 3 Recommended Operating Conditions UNT 24 Electrical Characteristics Over Full Range Of Operating Conditions Unless Otherwise Noted 2 41 Power Consumption PARAMETER TEST CONDITIONS MIN T MAX UNIT Analog transmitting and receiving DVpp 55V 55 DVpp 55V 55 AVpp 5 5 V Digital receiving Doa transmitting MCLKOUT enabled DVpp 3 V AVpp 3 V MCLKOUT disabled DVpp 3 V 14 17 Idle mode MCLKOUT enabled DVpp 5 5V AVpp 5 5V 150 160 MCLKOUT disabled DVpp 5 5V AVpp 5 5V Digital mode 1 3 transmitting 1 3 receiving DVpp 3 V AV
9. megonineaiy FM input sensitivity full scale 14 kHz deviation FM input dc offset relative to VHR FM input idle channel noise below full scale input FM gain error Power supply rejection RXQN Inputs AVpp 3 V 4 5 V 5 V TEST CONDITIONS MIN TY 1 NENNEN NK Input signal 0 15 kHz 5 Input at full scale 1 dB 0 dB to 60 GB input 4 54 5 2 f 0 kHz to 15 kHz Provides 12 dB headroom for AGC fading conditions 2 3 2 4 5 Transmit and Q Channel Outputs PARAMETER MIN TYP MAX 1 5 Differential 2 24 Peak output voltage full scale centered at VOM Nominal output level constellation radius centered Differential SS S N D ratio at differential outputs 48 52 dB Gain E s Gsnmsmachbewenladd Gain sampling mismatch between and Q Zero code error differential 9 mV Zero code error each output with respect to VCM 880 m Zero code error to Q with respect to other channel differential or 10 single ended 5 Transmit DAGs o bs LSB Transmit offset DACs integral nonlinearity LSB 2 4 6 Auxiliary D A Converters PARAMETER TEST CONDITIONS MIN MAX UNIT AVpp gt 3Vt AUXFS 1 0 00 02 Output range AVpp gt 4 5 Vf AUXFS 1 0 10 AVpp gt 5Vt AUXFS t0 11 02 Resolution AGC AFC PWRCONT DACs Resol
10. 1 4 Saon INIS MHON 04450 SSAq Lddsa eadsa ddSd VOIN vadsa eVON LYON 9ddsa OVOW adsa HSOOW 80450 ISOOW 6ddSd LS LW OSIN SSAG 5 M1089 YINOOdD1 N39S MIONAS NIXYN4 VIONAS N3XHUOI Za INAS SSA LATINAS J3uSS Ay 031NAS JONAS LINO REGGE ES GLE BESSLEK EGR ESE E 779 E BRR OR ee 1 4 Terminal Functions TERMINA 1 0 DESCRIPTION NAME NO AFC 11 Automatic frequency control The AFC DAC output provides the means to adjust system temperature compensated reference oscillator TCXO Automatic gain control The AGC digital to analog converter DAC output can be used to control the gain of system receiver circuits AVDDREF Analog supply voltage for FM receive path Power applied to AVppREF powers the FM receive path circuitry AVppRX Analog supply voltage for receive path Power applied to AVppRX powers the receive path circuitry AVppTX 19 Analog supply voltage for transmit path Power applied to AVppTX powers the transmit path circuitry AVssREF 98 _ Analog ground for REFCAP AVssRX 12 Analog ground for receive path ST 2 Analog ground for transmit path Battery strength monitor A sample of the battery voltage is applied to BAT and this sample monitors the battery strength CINT Controller data interrupt CINT is the microcontroller data interrupt active low signal that is sent
11. 4 11 5 Phase Adjustment Strategy For 15 54 system in the digital mode receiver sample timing must be phase adjusted to synchronize the A D conversions to optimum sampling points of the received symbols and to synchronize the mobile unit timing to the base station timing This is done by temporarily increasing or decreasing the periods of the clocks to be adjusted To avoid undesirable transients each cycle of the clock being adjusted is altered by only one period of MCLKIN A total adjustment equivalent to multiple MCLKIN periods is accomplished by altering multiple cycles of the clock being adjusted The number of cycles altered is controlled by internal counters In the TCM4300 there are two clocks which must be adjusted CMCLK and an internal 9 72 MHz clock from which SINT is derived Each of these clocks has an associated counter that counts the number of cycles that have been lengthened or shortened by one MCLKIN period each and thus detects when the total adjustment is complete These counters are shown in Figure 4 5 as Adjust Counter A and Adjust Counter B The magnitude of the 2s complement value written to the timing adjustment register determines the number of cycles ofthe clocks to be lengthened or shortened by one MCLKIN period each to achieve the total desired timing adjustment in units of MCLKIN periods If a negative number is written the clock periods are lengthened for the duration of the timing adjustment resulting in a ti
12. Figure ee O gt Q O N T r List of Illustrations Title Page MCLKOUT Timing Diagram 3 1 Microcontroller Interface Timing Requirements Mitsubishi Configuration Read Cycle MTS 1 0 10 3 2 Microcontroller Interface Timing Requirements Mitsubishi Configuration Write Cycle MTS 1 0 10 3 3 Microcontroller Interface Timing Requirements Intel Configuration Read Cycle MTS 1 0 00 3 4 Microcontroller Interface Timing Requirements Intel Configuration Write Cycle MTS 1 0 00 3 5 Microcontroller Interface Timing Requirements Motorola 16 Bit Read Cycle MTS 1 0 10 3 6 Microcontroller Interface Timing Requirements Motorola 16 Bit Write Cycle MTS 1 0 10 3 7 Microcontroller Interface Timing Requirements Motorola 8 Bit Read Cycle MTS 1 0 01 3 8 Microcontroller Interface Timing Requirements Motorola 8 Bit Write Cycle MTS 1 0 01 3 9 TCM4300 to DSP Interface Read 3 10 TCM4300 to DSP Interface Write 3 11 Power Ramp Up Ramp Down TlIming 4 6 Transmit Power Ramp U
13. 1 6 1 4 Terminal Functions Continued TERMINAL DESCRIPTION NAME SCEN Speech CODEC enable A high out from SCEN can enable the speech CODEC SINT Sample interrupt SINT is active low In the analog mode SINT occurs at 40 kHz in the digital mode SINT occurs at 48 6 kHz SYNCLK 32 Synthesizer clock SYNCLK clocks the serial data stream SYNDTA 31 o Synthesizer serial data SYNDTA provides the serial bit stream output SYNLEO 28 o Synthesizer 0 1 and 2 latch enables An active high on SYNLEO SYNLE1 and SYNLE1 29 EE SYNLE2 indicates that the latch is enabled SYNLE2 30 SYNOL 27 Em Synthesizer out of lock An active high at SYNOL indicates a synthesizer is not locked TXEN 23 Transmit power enable An active high output from TXEN can be used to enable various System transmitter circuit devices TXIN 18 In phase differential negative baseband transmit The negative component of the differential baseband transmit signal is output from TXIN TXIP 17 In phase differential positive baseband transmit The positive component of the differential baseband transmit signal is output from TXIP TXONIND 24 Transmit on indicator A signal is applied to TXONIND to indicate that power is applied to the power amplifier TXQN 21 Quadrature differential negative baseband transmit The negative component of the quadrature differential transmit signal is output from TXQN TXQP 20 Quadrature differential positive baseband transmit The
14. Microcontroller Interface Connections for Intel Mode TCM4300 TERMINAL MICROCONTROLLER TERMINAL MCA4 MCAO Demultiplexed address bits not on microcontroller MCRW WR Active low write data strobe MCDS RD Active low read data strobe MCDS configured to active low operation by MTS1 and MTSO The microcontroller bus must be demultiplexed by external hardware MWBDFINT Either one of INT3 through INTO as appropriate DINT Either one of INT3 through INTO as appropriate 4 29 4 24 2 Mitsubishi Microcontroller Mode of Operation When the microcontroller type select MTS1 and MTSO inputs are held high and low respectively the TCM4300 microcontroller interface is configured in Mitsubishi mode In this mode the interface has a single read write control R W signal active low data strobe MCDS signal and active low interrupt request signals The processor E and R W signals should be connected to the TCM4300 MCDS signal and the MCRW signal respectively Table 4 26 lists the microcontroller interface connections for Mitsubishi mode Table 4 26 Microcontroller Interface Connections for Mitsubishi Mode TCM4300 TERMINAL MICROCONTROLLER TERMINAL MTSI MTSO cost 7 MORW DINT 4 24 3 Motorola Microcontroller Mode of Operation When the microcontroller selects MTSO high and MTS1 low the TCM4300 microcontroller interface is configured for 8 bit family 6800 family derivatives e g 68HC11D3 and
15. OR SYSTEMS OR OTHER CRITICAL APPLICATIONS Inclusion of TI products in such applications is understood to be fully at the risk of the customer Use of TI products in such applications requires the written approval of an appropriate TI officer Questions concerning potential risk applications should be directed to TI through a local SC sales office In order to minimize risks associated with the customer s applications adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards TI assumes no liability for applications assistance customer product design software performance or infringement of patents or services described herein Nor does TI warrant represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Copyright 1996 Texas Instruments Incorporated Contents Section Title 1 Introd ction ee uie RI orte n ERE esce shreds 1 2 4300 Functional Block Diagram 1 3 5 Lee ey ee ee eee es 1 4 Terminal E rctloris u uu cette edente etaed eg Electrical Specifications
16. to 0 when the microcontroller reads either of these locations Table 4 13 RSSI Battery A D Converter PARAMETER TEST CONDITIONS MAX UNIT 0 2 2 Input range AVpp 3V 4 5 V 5V V Conversion time AVpp 3 V 45V 5 V Differential nonlinearity Integral nonlinearity In order to save power the entire RSSI battery converter circuit is powered down when A D conversions are requested for 40 The microcontroller writes to RSSI or BAT registers causing power to be applied to the converter circuit Power is applied to the converter circuit until the data value has been latched into the corresponding register at which time power to the converter is removed Data remains in the result registers after the converter is powered down 2 0 Gain offset error full scale 1 1 2 4 11 Timing And Clock Generation The digital timing generation system uses 38 88 MHz master clock as shown in Figure 4 4 The upper waveform shows the clock generation for clocks that must be phase adjusted in order to synchronize the mobile unit with the received symbol stream in the digital mode In the analog mode these clocks operate without phase adjustments The bottom waveform of Figure 4 4 shows the clocks that are directly derived from the master clock Codec Master Clock 2 048 MHz MO MALO MA Nf RH Ke Codec Sample Clock 8 kHz CSCLK N Figure 4 4 Codec Master and Sample Clock Timing 4 11 1 Cl
17. 10 AVpp gt 5Vt AUXFS 1 0 11 0 2 45 4 1 1 Resolution AGC AFC PWRCONT DACs Gain offset error full scale AGC Resoliion LCOCONTR DAC MEER ERE AFC PWRCONT DAC Gain offset error full scale LCDCONTR DAC Differential nonlinearity Integral nonlinearity 1 Range settings depends only AUXFS 1 0 supply voltage is not detected The LCDCONTR output is used by the microcontroller to adjust the contrast of the liquid crystal display LCD This converter is a separate 4 bit DAC The auxiliary DACs be powered down The AGC and AFC DACs have dedicated bits the MIntCtrl register to enable the DACs The PWRCONT DAC is enabled by the TXEN bit in the DStatCtrl register The LCDCONTR DAC is enabled when the LCDEN bit of the LCD D A register clears to 0 the four data bits being left justified The AFC AGC and PWRCONT DACs are disabled after powerup or after a reset of the 4300 After power up or reset the default AUXFS 1 0 is 00 When the DACs are powered down their output terminals go to a high impedance state and can tolerate any voltage present on the terminal that falls within the supply range The slope and the corresponding output values for the auxiliary DACs are listed in Table 4 11 and Table 4 12 Table 4 11 Auxiliary D A Converters Slope AGC AFC PWRCONT NOMINAL LSB NOMINAL OUTPUT VOLTAGE NOMINAL OUTPUT VOLTAGE AUXFS 1 0 SLOPE VALUE FOR DIGITAL CODE
18. 128 FOR DIGITAL CODE 256 SETTING V MIDRANGE MAX VALUE V V The maximum input code is 255 The value shown for 256 is extrapolated 4 9 Auxiliary DACs LCD Contrast Converter continued Table 4 12 Auxiliary D A Converters Slope LCDCONTR NOMINAL LSB NOMINAL OUTPUT VOLT NOMINAL OUTPUT VOLTAGE AUXFS 1 0 SLOPE VALUE AGE FOR DIGITAL CODE 8 FOR DIGITAL CODE 161 SETTING MIDRANGE MAX VALUE 0 V o 2516 5 1 The maximum input code is 15 The value shown for 16 is extrapolated 4 10 RSSI Battery Monitor The received signal strength indicator RSSI and battery BAT strength monitor share a common register The input source is determined by writing any value to the mapped register location for that analog to digital converter ADC see Table 4 13 and the result of the conversion is stored in both register locations The conversion process is initiated when the register is written to The CVRDY bit in the MStatCtrl register is set to 1 to show completion of the conversion process Reading from either of the register locations causes the CVRDY bit to change to 0 The RSSI allows the mobile unit to choose the proper control channels and to report signal levels to the base stations When the CVRDY bit in the MStatCtrl register goes to 1 this indicates that the latest RSSI or battery voltage A D conversion has been completed and can be read from the RSSI or BAT register location CVRDY clears
19. 3 3 TCM4300 to Microcontroller Interface Timing Requirements Mitsubishi Write Cycle see Figure 3 3 and Note 2 MCRW stable before falling edge of COENE ie Md MCRW stable after rising edge of tsu WA ast cos MCA stable before falling edge CAEN 2 Setup time write data stable MCD before rising edge of su W strobe MCDS TWD SU ene write data stable MCD after rising edge of strobe TWD HO 20 tw WSTB Pulse duration write strobe pulse width low on MCDS TWR STB t Hold time chip select MCCSH and MCCSL stable before TCS T h CS rising edge of strobe MCDS HO t Setup time chip select stable MCCSH and MCCSL before TCS su CS falling edge of strobe MCDS SU NOTE 2 Timings based upon Mitsubishi 3773254 16 MHz and Mitsubishi 3772541 8 MHz M tw WSTB 90 90 Mee 10 10 see Note A tsu R W 4 gt lt MCRW 4992N 10 tsu WA tsu WA t suw P gt thw MCD7 MCDO X X 9096 90 MCCSH i DR MCCSL 10 10 NOTE A Chip selection is defined as both MCCS and MCDS active Figure 3 3 Microcontroller Interface Timing Requirements Mitsubishi Configuration Write Cycle MTS 1 0 10 3 4 4300 to Microcontroller Interface Timing Requirements Intel Read Cycle see Figure 3 4 and Note 3 ALTERNATE PARAMETER SYMBOL t Setup time read address MCA stable before falling edge of
20. 68HC11G5 bus characteristics and when the microcontroller selects MTSO low and MTS1 high the microcontroller interface is configured for 16 bit family 680 x 0 family derivatives e g 68008 and 68302 characteristics The Motorola mode makes use of a single read write control R W signal and active low interrupt request signals The processor E 8 bit or DS 16 bit and R W control signals should be connected to the TCM4300 MCDS signal and the MCRW signal respectively Table 4 27 illustrates the connections between the TCM4300 and an 8 bit Motorola processor Table 4 28 illustrates the connections between the TCM4300 and a 16 bit Motorola processor Table 4 27 Microcontroller Interface Connections for Motorola Mode 8 bits TCM4300 TERMINAL MICROCONTROLLER TERMINAL MCA4 MCAO Demultiplexed address output PF 4 0 on microcontroller for nonmultiplexed machines e g 68 1165 and not on micro for multiplexed bus machines e g 68HC11D3 MCDS E Active high data strobe MCDS configured to active high operation by MTS1 and MTSO AT MWBDFINT IRQ and or NMI as appropriate DINT and or NMI as appropriate 4 30 Table 4 28 Microcontroller Interface Connections for Motorola Mode 16 bits TCM4300 TERMINAL MICROCONTROLLER TERMINAL MTS1 MTSO Tie to logic levels high and low respectively MCCSH Not on microcontroller can be used for address decoding MCCSL Not on microcontroller 68000 68008
21. 8 kHz to 15 kHz see Note 1 Peak to peak group delay distortion Absolute channel delay 0 kHz to 15 kHz 30 NOTES 2 Stopband 4 Deviation from ideal 0 35 SQRC response 0 kHz to 15 kHz YP 0 3 0 5 3 320 gt 75 kHz see Note 2 Any 30 kHz band centered at gt 90 kHz see Note 2 20 kHz to 45 kHz see Note 2 Frequency response 45 kHz to 75 kHz see Note 2 31 70 70 70 Any 30 kHz band centered at gt 90 kHz see Note 2 Peak to peak group delay distortion kHz to 15 kHz Absolute channel delay 0 kHz to 15 kHz 54 NOTES 1 Ripple magnitude 2 Stopband 4 4 Transmit Burst Operation Digital Mode In the digital mode the TCM4300 performs all encoding signal processing and power ramping for the burst Start and stop timing of the variable length bursts are set by means of the TXGO bit in the DStatCtrl register The SINT interrupt output interrupts the DSP at 48 6 kHz which is T 2 interval T 1 symbol period 1 24 3 kHz The burst is initiated by the DSP writing 1 to 5 dibits to the TXI register a small positive delay offset value d to the base station BST register and a 1 to the TXGO bit in the DStatCtrl register YP 0 5 3 540 The TXGO bit is sampled on the falling edge of SINT The transmit outputs are held at zero differential voltage each output terminal is held at the voltage supplied to the VCM input terminal for 9 5 SINT periods 195 5 us plus BST offs
22. Functional Block Diagram TXIP Low Digital Filter TXI 04b TXIN File d Analog 4 Shifted Mode LPF 1 4 Shifte DQPSK Modulation Registers TXQ DIA Digital 4 1 Mode SQRC TXQ 05b orn DSP Interface pm 3 RXIP Anti Digital Filter 02h Control CONTROL aliasing Analog 10 RXIN Fi Data DATA Mode LPF Sample 1 Register Address ADDRESS RXGN Digital mE Mode SQRC RXQ 03h Internal Low Wide band WBD RESET RSINL FM gt Pass Data Register on Filter Demodulator WBD oth SINT Control ooh MCCLK Internal CSCLK ap Clocks Clock CMCLK 8 Generation Clock XTAL AGC D A 09h D and 5 an MCLKIN Timing MCLKOUT 5 Adjustment AFC D A OAh D Logic VCM Control Registers 8 RBIAS PWRCONT D A OBh D B PAEN OCh VHR OUT1 DStatCtrl FMRXEN Register REFCAP IQRXEN ow TXEN Control MWBDFINT SCEN OEh SYNOE DWBDINT TXONIND Register gt CINT DINT Microcontroller 06h FIF to DS O oth FIFO SYNCLK Synthesizer SYNDTA Interface SYNLE 3 Qon Micro 2 0 controller Interface RSSI gt Control CONTROL BAT Data DATA Address ADDRESS LCDCONTR 0Dh PZ PACKAGE TOP VIEW 1 3 Pin Assignments 4 me gt E S 55 94 AVOOZO0RR0R000 gt 0 0 0 0 0 0 gt gt
23. at the system level is required to ensure data integrity The WBD stream carries with it a 10 2 clock The Manchester coded data format contains a transition at the middle of every bit clock period which aids in clock recovery The polarity of the transition is data dependent In a typical Manchester coded WBD stream a positive voltage for the first half of the data sequence bit time followed by a negative voltage for the second half of the data sequence bit time represents the value 0 in the data sequence Likewise a negative voltage followed by a transition to a positive voltage represents the value 1 in the data sequence This is illustrated in Figure 4 3 WBD stream can also be seen as the exclusive OR of the clock and data sequence The data sequence is in nonreturn to zero NRZ format Data Sequence WBD Stream Recovered Clock 10 kHz Figure 4 3 WBD Manchester Coded Data Stream 4 9 4 9 Auxiliary DACs LCD Contrast Converter Auxiliary DACs generate AFC AGC and power control signals for the RF system These three D A converters are updated when the corresponding data is received from the DSP In fewer than 5 us after the corresponding registers are written to the output has settled to within 1 LSB of its new value see Table 4 10 Table 4 10 Auxiliary D A Converters PARAMETER TEST CONDITIONS UNIT AVpp gt 3Vt AUXFS 1 0 00 02 2 5 Output range AVpp gt 4 5 Vt AUXES 1 0
24. data to the DSP the microcontroller writes data to FIFO A To indicate to the DSP that FIFO A is ready to be read the microcontroller writes a 1 to the Send C bit of the microcontroller interrupt control register MIntCtrl When this happens the DSP interrupt line CINT goes active signaling to the DSP that data is waiting At the same time the value that can be read from the Clear C bit in the DIntCtrl register goes from 0 to 1 indicating that the interrupt is pending When the DSP writes a 1 to the Clear C bit the CINT line returns to the inactive state and the value that can be read from Clear C is 0 The microcontroller cannot deassert the CINT line The microcontroller DSP communications interface is symmetric Data sent from the DSP to the microcontroller is handled as described above with the roles of A and B FIFOs and C and D bits and interrupts reversed When the number of reads exceeds the number of writes from the other side the values read are undefined 4 20 4 15 Microcontroller Register Map The microcontroller can access 17 locations within the TCM4300 The register locations are 8 bits wide as shown in Table 4 16 and Table 4 17 Table 4 16 Microcontroller Register ADDR D7 pe p ps p bt p 01h MSB FIFO A B Microcontroller to DSP DSP to microcontroller om Gest Sendo AGCEN AFCEN rum
25. diagram of the frequency synthesizer interface CLKPOL NUMCLKS lt LOWVAL 3 Control HIGHVAL lt Registers Read SEL 2 0 eady and MSB LSB FIRST Timing Logic SYNRDY MStatCtrl Register SYNDTA 4 32 Bit Data 8 uc SYNLEO 32 Register Bus SEL 0 5 MSB LSB FIRST SEL 1 HIGHVAL Q SYNLE2 SEL 2 LOWVAL N CLKPOL 5 Em NUMCLKS Circuit n 303 75 KHz Figure 4 6 Synthesizer Interface Circuit Block Diagram The SynData0 register contains the least significant bits of the 32 bit data register SynData3 contains the most significant bits The bits in the SynCtrl0 SynCtrl1 and SynCtrl2 registers are allocated as shown in Figure 4 7 SynCtrlo SEL 2 0 LOWVAL SynCtrl1 MSB LSB Reserved FIRST HIGHVAL Figure 4 7 Contents of SynData Registers Table 4 14 identifies the meaning of each of the bit fields in SynCtrI 2 0 Table 4 14 Synthesizer Control Fields 0 0 CLKPOL This is a 1 bit field When CLKPOL 1 the SYNCLK signal is a positive going 50 duty cycle pulse CLKPOL 0 reverses the polarity of SYNCLK NUMCLKS This 5 bit field defines the total number of clock pulses that are to be produced on SYNCLK The value written into NUMCLKS is the desired number of output clock pulses with one exception When 32 clock pulses are desired all zeroes are written into NUMCLKS HIGHVAL This 5 bit field defines
26. positive component of the quadrature differential transmit signal is output from TXQP Voltage common mode VCM establishes the dc operating point for transmit outputs and can be tied to VHR Voltage half rail The voltage level at VHR is approximately 0 5 x AVpp VHR establishes the dc operating point for receive inputs Substrate ground EM Crystal input A crystal connected between XTAL and MCLIN forms an oscillator circuit 2 Electrical Specifications This section lists the electrical specifications the absolute maximum ratings the recommended operating conditions and operating characteristics for the TCM4300 Advanced RF Cellular Telephone Interface Circuit 21 Absolute Maximum Ratings Over Operating Free Air Temperature Range unless otherwise noted t Supply voltage range DVpp see Notes 1 and 2 Vss 0 3 V to AVpp 0 3 V AVpp see Notes 2 and 3 Vss 0 3 V to DVpp 40 3 V Input voltage range Vi Digital signals Vss 0 3 V to DVpp 0 3 V Analog signals 0 3 V to AVpp 0 3 V Output voltage range Vo Digital signals Vss to DVpp Analog signals Vss to AVpp Continuous total power dissipation See Dissipation Rating Table Operating free air temperature range TA 40 to 85 C Storage temperature range Testa i cies
27. reset circuit also causes internal reset However the logic level at RSINL has no effect on reset outputs RSOUTH and RSOUTL The effects of resetting the TCM4300 are described in the following paragraphs 4 23 1 Power On Reset The power on reset POR is digitally implemented and provides a timed POR signal at RSOUTL and RSOUTH The POR pulse duration is equal to 388 800 cycles of MCLKIN 10 ms There are two outputs to provide a high reset and a low reset in order to accommodate the reset polarity requirements of any external device The TCM4300 internal registers are reset when the POR outputs are activated See Figure 4 12 tw gt 10 ms Minimum RSOUTH 90 90 Figure 4 12 Power On Reset Timing 4 23 2 Internal Reset State After power on reset the TCM4300 register bits are initialized to the values shown in Table 4 23 The synthesizer control terminals SYNCLK SYNLEO SYNLE1 SYNLE2 and SYNDTA are high after reset and the synthesizer interface circuit is in the stable idle state with no SYNCLK outputs Table 4 23 Power On Reset Register Initialization REeGISTERNAME JBT9 8 7 6 5 4 3 2 1 o NOTE 5 r reserved ext bit value from external terminal 4 28 4 24 Microcontroller Interface The microcontroller interface of the TCM4300 is a general purpose bus interface see Table 4 24 which ensures compatibility with a wide range of microcontrollers including the Mitsubshi M37700
28. series and most Intel and Motorola series The interface consists of a pair of microcontroller type select inputs MTS1 and MTSO address and data buses as well as several input and output control signals that are designed to operate in a manner compatible with the microcontroller selected by the user See Sections 3 2 to 3 11 for Interface timing requirements Table 4 24 Microcontroller Interface Configuration POLARITY MTS1 MTSO DATA STROBE DS INTERRUPT OUTPUT ACTIVE ACTIVE Low poo foo fm separate read and write The microcontroller interface of the TCM4300 is designed to allow direct connection to many microcontrollers Except for the interrupt terminals it is designed to connect to microcontrollers in the same manner as a memory device The internal chip select is asserted when MCCSH 1 and MCCSL 0 4 24 4 Intel Microcontroller Mode Of Operation When the microcontroller type select inputs MTS1 and 50 are both held low the TCM4300 micro controller interface is configured into Intel mode see Table 4 25 In this mode the interface uses separate read and write control strobes and active high interrupt signals The processor RD and WR strobe signals should be connected to the TCM4300 MCDS signal and MCRW signal respectively The multiplexed address and data buses of the microcontroller must be demultiplexed by external hardware Table 4 25 lists the microcontroller interface connections for Intel mode Table 4 25
29. su RA strobe MCDS Hold time read address MCA stable after rising edge of strobe MCDS t Enable time read data on falling edge of strobe MCDS to en RD 4300 driving data bus MCD Valid time read data on falling edge of strobe MCDS to valid data MCD tiny Data MCD invalid after rising edge of strobe MCDS TRD INV Disable time read data TCM4300 releases MCD data bus TRD 28 fie dis RD after rising edge of strobe MCDS DIS t Setup time chip select MCCSH and MCCSL stable before TCS su CS falling edge of strobe MCDS SU Hold time chip select MCCSH and MCCSL stable before TCS rising edge of strobe MCDS HO NOTE 3 Timings are based upon Intel 80C186 16 MHz 90 90 see Ned 1076 1096 MCRW 4 t tsu RA thra rot BD 9 tdis RD ten RD gt tiny P MCD7 MCDO MCCSH 90 9052 tsu CS 4 th Cs 4 10 10 NOTE A Chip selection is defined as both MCCS and MCDS active Figure 3 4 Microcontroller Interface Timing Requirements Intel Configuration Read Cycle MTS 1 0 00 3 5 4300 to Microcontroller Interface Timing Requirements Intel Write Cycle see Figure 3 5 and Note 3 tgu WA ane pelt address MCA stable before falling edge th WA address MCA stable after rising edge of S Setup time write data stable MCD before rising edge of su W strobe MCRW TWb sU Hold time write data stable MCD after risi
30. the FMVOX bit is set to 1 it controls the input multiplexer connects the FM input to the receiver RXQP signal and connects the RXQN signal to VHR When the MODE control bit and the IQRXEN control bit are set to 1 both sides of the receive channel are enabled for use in the digital mode The input signals RXIP RXIN and RXQP RXQN are differential pair signals see Table 4 2 Differential signals are used to minimize the pickup of interference ground and supply noise while maintaining a larger signal level In single ended applications the unused RXIN and RXQN terminals must be connected to VHR or to an externally supplied bias voltage equal to the dc value of the input signal and the input signal level must be adjusted in the RF circuitry to provide the proper signal level so that the digital output codes are properly calibrated 0 5 V peak to peak corresponds to full scale digital output In the analog mode the RXQN inputis internally referenced to VHR Alternatively the unused inputs can be connected to VHR and the used inputs can be capacitively coupled Note that when the RX and FM inputs are capacitively coupled it is recommended that the input terminals be connected to VHR using a bias resistor 4 1 Table 4 2 RXIP RXIN RXQP and RXQN Inputs AVpp 3 V 4 5 V 5 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input voltage range 565 6 4 0 3 eae digital output 2 ended esee L 0250
31. to the DSP CINT is caused by a microcontroller write to the Send C interrupt register location CMCLK Codec master clock CMCLK provides a 2 048 MHz clock that is used as the master clock and bit clock for the speech codec CSCLK 93 Codec sample clock CSCLK provides an 8 kHz frame synchronization pulse for the speech codec CSCLK is also connected to the DSP for speech sample interrupts DINT Microcontroller interrupt request DINT is output when the DSP writes to the SEND DINT register location DINT can be active high or low according to the levels of the MTSO and 1 signals DSP 4 bit parallel address bus DSPAO through DSPAG3 provides the address bus for the DSP interface DSPA3 is the MSB and DSPAO is the LSB DSPCSL DSP chip select active low A low signal at DSPCSL enables the specific DSP addressed l O Z DSP 10 bit parallel data bus DSPDO through DSPD9 provide a 10 bit data bus for the DSP DSPDO9 is the MSB and DSPDO is the LSB tZ high impedance 1 4 1 4 Terminal Functions Continued TERMINAL VO DESCRIPTION NAME DSPRW DSP read write A high on DSPRW enables a read operation and a low enables a write operation to the DSP DSPSTRBL DSP strobe low The DSPSTRL active low is used in conjunction with DSPCSL to enable read write operations to the DSP 35 45 63 Digital power supply All supply terminals must be connected together 75 90 DVss 34 46 65 Digital ground All supply terminals
32. when the strobe signal for the selected synthesizer is driven high HIGHVAL is the bit number at which the signal changes state Bits being transferred on SYNDTA are sequentially designated 0 1 31 independent of any MSB LSB selection LOWVAL The value written into this 5 bit field affects the strobe signal for the selected synthesizer LOWVAL is the bit number at which the strobe signal is driven low The first bit transferred out of the serial interface is defined to occur at bit time 0 independent of any MSB LSB selection MSB LSB FIRST Writing a 0 to MSB LSB FIRST causes the LSB SynDataO 0 to be the first bit sent to SYNDTA of the serial synthesizer interface Writing a 1 to this bit programs the block for MSB first operation SynData3 7 SEL 2 0 This is a 3 bit field that selects which synthesizer strobe line is active 1 in any of the SELx bits activates the corresponding latch enable In the status register MStatCtrl two bits SYNOL and SYNRDY are dedicated to the synthesizers The first is an out of lock indicator that comes from the SYNOL input terminal When the SYNOL input terminal is connected to the OR of the out of lock signals from the external synthesizers the lock condition of the synthesizers can be monitored by reading the MStatCtrl register A high on SYNOL also prevents the PAEN output from being asserted and forces the TXI and TXQ outputs to zero The SYNRDY bit active high indicates when the synthesi
33. write address of FIFO B is the same as the read address of FIFO A Figure 4 11 details the connection of TCM4300 to an example DSP Table 4 20 DSP Register Map ps os pr MSB FIFO A B microcontroller to DSP DSP to microcontroller LSB Table 4 21 DSP Register Definitions ADDR CATEGORY WBDCtrl Wide band data control RX channel A D results Analog mode D A data 04h TXI w Digital mode 1 4 DQPSK modulator input data Analog mode TXQ D A data Digital mode Not used FIFO A B microcontroller to DSP DSP to microcontroller 05h TXQ 4 25 DSPD 9 0 D 15 6 DSPA 3 0 A 3 0 DSPCSL 4 is TCM4300 lt RW DSPSTRBL 4 STRB SINT gt INT 1 CINT gt INT3 BDINT gt H INT4 Figure 4 11 DSP Interface 4 20 Wide Band Data Registers Bit 9 of the wide band data register is the most recently received bit as shown below WBD Ws Data 38 7 4 WBDCtrl WBD_LCKD WBD_ON WBD_BW 4 21 Base Station Offset Register BST OFFSET values are 00 01 10 and 11 which correspond to an offset value d of 0 1 2 and 3 respectively as shown below BST OFFSET The delay the TCM4300 TX channels is increased the amount BST OFFSET d X 4 4 26 4 22 DSP Status and Control Registers DIntCtrl Clear and Send Bits The bit names in the DIntCtrl regi
34. 00 releases data bus after TRD 12 Re dis R rising edge of strobe DSPSTRBL DIS DSPCSL T 5 1 th CS 90 90 DSPSTRBL 405 th R W tsu R W 4 gt R W 90 J 90 DSPA h R ten R gt 5 tdis R Figure 3 10 TCM4300 to DSP Interface Read Cycle 3 11 Switching Characteristics TCM4300 to DSP Interface Write Cycle see Figure 3 11 ALTERNATE PARAMETER SYMBOL Setup time read write DSPRW stable before falling edge of P TRW SU ISu R W strobe DSPSTRBL t Hold time read write DSPRW stable after rising edge of h R W strobe DSPSTRBL t Setup time chip select stable DSPCSL before falling edge su CS DSPSTRBL Hold time chip select DSPCSL stable after rising edge of strobe DSPSTRBL t Setup time write address DSPA stable before falling edge su WA of strobe DSPSTRBL Hold time write address DSPA stable after rising edge of strobe DSPSTRBL TRW HO TCS SU TCS H TWA sU TWA H t Setup time write data stable DSPD before rising edge of su W strobe DSPSTRBL Hold time write data stable DSPD after rising edge of TWD H strobe DSPSTRBL w WSTB Pulse duration write strobe pulse width low on DSPSTRBL TWR STB DSPCSL d ijs isu CS gt lt th CS 4 tw WSTB 90 90 DSPSTRBL qs disc
35. 9 TEXAS INSTRUMENTS TCM4300 Advanced RF Cellular Telephone Interface Circuit ARCTIC Data Manual 1996 Mixed Signal Products 48 5 INSTRUMENTS Printed in U S A SLWS010F 10 96 TCM4300 Data Manual Advanced RF Cellular Telephone Interface Circuit ARCTIC SLWS010F October 1996 48 PRINTED WITH TEXAS 2 SOYINK INSTRUM ENTS Printed on Recycled Paper IMPORTANT NOTICE Texas Instruments reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice and advises its customers to obtain the latest version of relevant information to verify before placing orders that the information being relied on is current Tl warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with standard warranty Testing and other quality control techniques are utilized to the extent deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Certain applications using semiconductor products may involve potential risks of death personal injury or severe property or environmental damage Critical Applications SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED INTENDED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT APPLICATIONS DEVICES
36. Bits in Control Register WBDCtrl 4 8 Auxiliary D A Converters 86 Soa Ree 4 10 Auxiliary D A Converters Slope AGC AFC PWRCONT 4 10 Auxiliary D A Converters Slope LCDCONTR 4 11 RSSI Battery A D Converter 4 11 Sy thesizer Control Fields ume hei ie 4 17 External Power Control Signals 4 18 Microcontroller Register Map 4 21 Microcontroller Register Definitions 4 22 WBDGtrl Register 2 5 2 2 eee ee ready 4 23 MStatCtrl Register 5 4 24 DSP Register Map 4 25 DSP Register Definitions 4 25 DStatCtrl Register Bits 4 27 Power On Reset Register Initialization 4 28 Microcontroller Interface Configuration 4 29 Microcontroller Interface Connections for Intel Mode 4 29 Microcontroller Interface Connections for Mitsubishi Mode 4 30 Microcontroller Interface Connections for Motor
37. CS1 CS2 or CS3 68302 MCD7 MCDO D 7 0 data bus on microcontroller MCA4 MCAO A 4 0 68008 5 1 68000 68302 MCRW R W MCDS DS active low data strobe 68008 LDS active low data strobe 68000 68302 MCDS configured to active low operation by MTS1 and MTSO MWBDFINT 7 IACK6 or IACK1 68302 Not on microcontroller 68000 68008 DINT Either one of INT3 through INTO as appropriate 4 31 4 32 5 Mechanical Data 5 1 PZ S PQFP G100 PLASTIC QUAD FLATPACK IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII 00010 110 01001011 1 25 k 12 00 TYP 14 20 13 80 50 Y Gage Planer 16 20 15 80 sQ 0 13 NOM 0 45 Seating Plane 1 60 MAX 4040149 A 03 95 NOTES All linear dimensions in millimeters B This drawing is subject to change without notice C Falls within JEDEC MO 136 5 1 IMPORTANT NOTICE Texas Instruments reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice and advises its customers to obtain the latest version of relevant information to verify before placing orders that the information being relied on is current Tl warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and othe
38. CTION RESET VALUE Wide band data lock data WBD_LCKD determines whether edge WBDSEGRD detector is locked 1 or unlocked 0 E 8 WBD ON Wide banddata on WBD_ON turns the WBDD module on off 1 0 0 7 5 R W BW 2 0 Wide band data bandwidth WBD_BWJ 2 0 sets the appropriate PLL bandwidth 000 20 Hz 001 39 Hz 010 78Hz 011 156Hz 100 313 Hz 101 625 2 110 1250Hz Hsu 4 17 Microcontroller Status and Control Registers MCClock This location is used by the microcontroller to change the speed of its own clock The division modulus is equal to a binary coded value written into this register Only bits 5 0 are significant After reset MCClock is equal to MCLKIN 32 Division moduli 2 through 32 are valid 0 1 moduli are prohibited The clock speed change occurs after the write is complete MintCtrl Bits 7 4 The bit names in this field indicate the resulting action when the bitis set to 1 When these bits are being read a 1 indicates that the corresponding interrupt is pending A 0 indicates that the interrupt is clear Writing a 0 into any bit location has no effect MintCtrl Bits 3 1 These bits enable power to the AGC and AFC DACs and their corresponding outputs as shown below FMRXEN can assert set to 1 the FMRXEN external function The reset value is 0 off ER ee ee ee MintCtrl Clear Clear F Clear D Send C AGCE
39. K twWSTB MCDS 9096 9096 see Note A 10 10 isu R W TT o ih R W MCRW 10 134 tsu WA th WA M gt gt thw MCDO0 MCD7 X X 90 90 MCCSH 9 P tsu CS th cs MCCSL 10 10 NOTE A Chip selection is defined as both MCCS and MCDS active Figure 3 9 Microcontroller Interface Timing Requirements Motorola 8 Bit Write Cycle MTS 1 0 01 3 10 Switching Characteristics TCM4300 to DSP Interface Read Cycle see Figure 3 10 ALTERNATE PARAMETER SYMBOL t Setup time read write DSPRW stable before falling edge of SU R W strobe DSPSTRBL t Hold time read write DSPRW stable after rising edge of h R W DSPSTRBL Setup time chip select stable DSPCSL before falling edge su CS of strobe DSPSTRBL TCS SU t Hold time chip select DSPCSL stable after rising edge of h CS strobe DSPSTRBL Setup time read address DSPA stable before strobe TRW SU TRW HO TCS HO TWA SU tsu RA DSPSTRBL goes low t Hold time read address DSPA stable after strobe goes high t Enable time read data on falling edge of strobe DSPSTRBL en R to TCM4300 driving data bus DSPD TWA HO TRD Delay read data valid time on falling edge of strobe IdDV DSPSTRBL to valid data VEI d DV Hold time read data DSPD invalid after rising edge of i5 Disable time read data TCM43
40. N WBD p mn AFCEN FMRXEN Reserved RW MStatCtrl This register contains various signals needed for system monitoring and control as shown here also see Table 4 19 2 R W ww RW 22 Exe amp n aw n T m w 4 23 Table 4 19 MStatCirl Register Bits fem NAME seservanue Synthesizer out of lock SYNOL is equal to the level applied to SYNOL input pin SYNOL can be used as an input for an externally generated Level on status signal to prevent transmission when external synthesizers are SYNOL input out of lock In digital mode when SYNOL is high PAEN is not asserted terminals and no signal can be transmitted from TXIP TXIN TXQP and TXQN Transmitter on indicator TXONIND is equal to the level applied to Level for TXONIND TXONIND and it can indicate that power is applied to the power TXONIND input amplifier terminals Synthesizer interface ready SYNRDY indicates that frequency 5 SYNRDY synthesizer is ready to be programmed by the microcontroller When SYNRDY is 1 the microcontroller can program the frequency synthesizer interface a 0 indicates the interface circuit is busy MCLKOUT enable When MCLKEN is set to 1 by the microcontroller 4 R W MCLKEN 38 88 MHz master clock is output at MCLKOUT Writing 0 to MCLKEN disables MCLKOUT Conversion ready A 1 indicates that the latest RSSI o
41. ak to peak 16 2 kHz to 18 kHz see Note 5 26 response 0 125 V peak to peak 18 kHz to 45 kHz see Note 5 30 0 125 V peak to peak 45 kHz to 75 kHz see Note 5 46 0 125 V peak to peak 8 kHz to 15 kHz see Note 5 0 125 V peak to peak gt 75 kHz 60 i 2 group delay 0 125 V peak to peak 0 kHz 15 kHz us distortion S Absolute channel delay RXI Q IN to 0 125 V peak to peak 0 kHz to 15 kHz 325 digital OUT NOTES 4 Deviation from ideal 0 35 square root raised cosine 5 response 5 Stopband 2 5 2 Receive RX Channel Frequency Response FM Input in Analog Mode PARAMETER TEST CONDITIONS MIN T MAX UNIT 2 5 V peak to peak 0 kHz to 6 kHz see Note 6 Frequency response 2 5 V peak to peak 20 kHz to 30 kHz see Note 5 2 5 V peak to peak 34 kHz to 46 kHz see Note 7 YP Peak to peak group delay distortion 2 5 V peak to peak 0 kHz to 6 kHz 2 Absolute channel delay 2 5 V peak to peak 0 kHz to 6 kHz NOTES 5 Stopband 6 Ripple magnitude 7 Stopband and multiples of stopband 2 3 Transmit TX Channel Frequency Response Digital Mode PARAMETER TEST CONDITIONS MAX UNIT 0 kHz to 8 kHz see Note 4 8 kHz to 15 kHz see Note 4 20 kHz to 45 kHz see Note 5 Frequency response 55 45 kHz to 75 kHz see Note 5 gt 75 kHz see Note 5 Peak to peak group delay distortion 0 kHz to 15 kHz Absolute channel delay 0 kHz to 15 kHz 320 NOTES 4 Devi
42. am 3 1 3 2 4300 to Microcontroller Interface Timing Requirements Mitsubishi Read Cycle see Figure 3 2 and Note 2 E R MCRW stable before falling edge of mss o RAN Pu coer MCRW stable after rising edge of tsu RA 2 bem address MCS stable before falling edge of tras o t Enable time read data on falling edge of strobe MCDS to TRD 10 en RD TCM4300 driving data bus MCD EN Read data valid time on falling edge of strobe MCDS to valid data MCD TRD Dv SLE tiny Data MCD invalid after rising edge of strobe MCDS TRD INV t Disable time read data TCM4300 releases MCD data bus TRD dis RD after rising edge of strobe MCDS DIS Hold time chip select MCCSH and MCCSL stable before TCS rising edge of strobe MCDS HO t Setup time chip select MCCSH and MCCSL stable before TCS su CS falling edge of strobe MCDS SU NOTE 2 Timings are based upon Mitsubishi 3773284 16 MHz and Mitsubishi 3772S4L 8 MHz 90 90 MCDS o 9 see Note A 10 10 tsu R W gt lt gt M th R W 90 90 MCRW 4 su RA gt tn RA 4 Paar tv R tais RD ten RD MCD7 MCDO 90 MCCSH 90 tsu CS th Cs MCCSL 10 10 NOTE A Chip selection is defined as both MCCS and MCDS active Figure 3 2 Microcontroller Interface Timing Requirements Mitsubishi Configuration Read Cycle MTS 1 0 10
43. analog form by two 9 bit digital to analog converters DACs The output of the DAC is then filtered by a continuous time resistance capacitance RC filter The TCM4300 generates a power amplifier PA control signal PAEN to enable the power supply for the PA The start and stop times of the TDM burst are controlled by writing to a single bit TXGO in the DSP DStatCtrl register In the analog mode MODE 0 the DSP writes 8 bit and Q samples into the TXI and TXQ data registers at a 40 ksps rate These writes are timed by the SINT interrupt signal The samples are fed to a low pass filter before D A conversion In the transmit analog mode PAEN is always set to 1 The transmit section provides differential and Q outputs see Table 4 5 for both analog and digital modes The differential dc offset for the TXI and TXQ outputs can be independently adjusted using the transmit offset registers Table 4 5 Transmit TX and Q Channel Outputs PARAMETER E lt U Differential lt Peak output voltage full scale centered at VCM Single ended Nominal output level constellation radius centered at Differential VCM Single ended Low level drift Transmit error vector magnitude EVM Resolution S N D ratio at differential outputs 8 12 0 3 Gain error 1 or Q channel Gain mismatch between I and Q Gain sampling mismatch between and Q 5 n Zero code error differential 3 Zero code err
44. ation from ideal 0 35 square root raised cosine SQRC response 5 Stopband Any 30 kHz band centered at gt 90 kHz see Note 5 60 2 6 2 5 4 Transmit TX Channel Frequency Response Analog Mode PARAMETER TEST CONDITIONS MIN UNIT 0 kHz to 8 kHz see Note 4 8 kHz to 15 kHz see Note 4 20 kHz to 45 kHz see Note 5 Frequency response 45 kHz to 75 kHz see Note 5 gt 75 kHz see Note 5 Any 30 kHz band centered at gt 90 kHz see Note 5 0 kHz to 15 kHz 3 delay distortion Absolute channel delay 0 kHz to 15 kHz NOTES 4 Ripple magnitude 5 Stopband 2 7 2 8 3 Parameter Measurement Information This section contains the timing waveforms and parameter values for MCLKOUT and several microcontroller interface configurations possible when using the TCM4300 The timing parameters are contained in Section 3 1 through Section 3 11 The timing waveforms are shown in Figures 3 1 through 3 11 All parameters shown in the separate waveforms have their values listed an associated table Not all parameter values listed in the tables are necessarily shown in an associated waveform 31 MCLKOUT Timing Requirements see Figure 3 1 and Note 1 twH Pulse duration MCLKOUT high 9 10 12 iw Pulse duration MCLKOUT low 9 10 12 Fall time MCLKOUT 2 3 4 NOTE 1 Tested with 15 pF loading on MCLKOUT MCLKOUT VOH gt P Figure 3 1 MCLKOUT Timing Diagr
45. be MCDS t Hold time chip select MCCSH and MCCSL stable before h CS falling edge of strobe MCDS t Setup time chip select stable MCCSH and MCCSL before su CS rising edge of strobe MCDS NOTE 4 Timings are based upon Motorola 68 000 16 67 MHz and Motorola 68302 16 MHz tdis RD 90 90 see NO 10 10 gt lt 4 in R W 90 90 MCRW 4 tsu RA th RA 1 01 tv RD 1 gt tdis RD ten RD gt tiny 90 90 tsu CS th CS MCCSL 10 10 NOTE A Chip selection is defined as both MCCS and MCDS active Figure 3 6 Microcontroller Interface Timing Requirements Motorola 16 Bit Read Cycle MTS 1 0 10 3 7 TCM4300 to Microcontroller Interface Timing Requirements Motorola 16 Bit Write Cycle see Figure 3 7 and Note 4 MCRW stable before falling edge of ws th R W dia 2 MCRW stable after rising edge of tgu WA d b address MCA stable before falling edge UNIT ns ns ns d address MCA stable after rising edge of 5 Setup time write data stable MCD before rising edge of su W strobe MCDS TWD su n Hold time write data stable MCD after rising edge of strobe tw WSTB Pulse duration write strobe pulse width low on MCDS TWR STB 6 t Hold time chip select MCCSH and MCCSL stable before TCS ae h CS falling edge of strobe MCDS HO t Se
46. ee possible moduli 3 4 and 5 For counter B there are four possible moduli 17 18 19 and 20 From DSP 38 88 MHz y From Micro controller 2 048 MHz Codec Master Clock CMCLK 17 18 19 20 RCO 8 kHz Codec Sample Clock CSCLK Adjust Counter B Adjust A Counter A Phase Adjusted 9 72 MHz Clock Analog Digital 40 0 48 6 kHz A D Sample Clock SINT Analog Digital Mode MODE bit Frequency Synth Clock 303 75 kHz Clock WBD Demod 6 48 MHz e gt Divider ADC Clocks 5 Chain DAC Clocks e Microcontroller Clock MCCLK N 2 3 32 Sync Enable External Clock Output MCLKOUT MCLKEN Logic Figure 4 5 Timing and Clock Generation for 38 88 MHz Clock 4 12 Frequency Synthesizer Interface The synthesizer interface provides a means of programming three synthesizers The synthesizer side outputs are a data line a clock line and three latch enable lines that separately strobe data into each synthesizer The control inputs are registers mapped into the microcontroller address space The status of the interface can be monitored to determine when the programming operation has been completed The synthesizer interface is designed to be general purpose Most of the currently available synthesizers can be accommodated by programming the interface according to the required synthesizer data and logic level formats The output of
47. en Reserved Fem ome 0 7 77750 om spa Ew m Pom 19x CIE ue Lom Snowe nese NS copa vso i50 ONNO SYNROY MOLKEN ovo Aree venen Lom newer Sm MB 8 4 21 Table 4 17 Microcontroller Register Definitions appr wwe 0 Wide band data FIFO A B microcontroller to DSP DSP to microcontroller Synthesizer interface om om Offset Transmit offset compensation TXQ Offset 4 16 Wide Band Data Control Register This register is used for two functions depending on whether it is being read from or written to When read from the register provides the latest 8 bits of received and demodulated data according to the microcontroller register map to the microcontroller When it is written to the bits are placed into the WBDCtrl register see Table 4 16 as shown here j WBDCtrl WBD LCKD WBD ON WBD BW 2 0 When the register is read bit 7 MSB is the last received data bit The definition of the WBDCtrl register according to the DSP register map is shown in Table 4 18 4 22 Table 4 18 WBDCtrl Register mw NAME FUN
48. et delay after SINT has detected TXGO high then the transmit outputs begin to ramp to the initial 7 4 DQPSK constellation value The shape of the ramp is the transient resulting from the internal SQRC filtering At the same time that the transmit outputs are beginning to ramp the PAEN digital output goes high This output can enable the power amplifier of a cellular radio transmitter The TCM4300 transmit outputs reach the first 1 4 DQPSK constellation value maximum effect point 6 SINT periods 3 symbol periods after the start of the ramp The bit stream to be encoded as 2 4 DQPSK symbols is generated by right shifts on each SINT of the TXI register with bit O LSB used first Previously written data continues to propagate through the TCM4300 internal filters until the last 1 4 DQPSK constellation value last MEP occurs at the transmit outputs 15 5 SINT periods 318 9 us plus BST offset 4 5 delay after the last symbol occurs 2 SINT periods before TXGO goes low then the transmit outputs decay to zero differential voltage each output at the voltage supplied to the VCM input terminal The shape of the decay is the transient resulting from the internal SQRC filtering The transmit outputs are held at zero differential voltage 6 SINT periods 3 symbol periods after the start of the decay At this time the PAEN digital output is set low see Figure 4 1 and Figure 4 2 Nonzero values of the BST offset register increase the delays
49. ion machine or process in which such semiconductor products or services might be or are used Copyright 1996 Texas Instruments Incorporated
50. l mode telephone functional blocks such as the speech codec FM receiver and Q demodulator transmitter signal processor and RF power amplifier In addition the TCM4300 is designed to reduce system power consumption through low voltage operation and standby mode The TCM4300 is offered in the 100 pin PZ package and is characterized for free air operation from 40 C to 85 C 1 1 Features e Compliance With TIA IS 54B Dual Mode Cellular Standard e Baseband Transmit Digital to Analog D A Conversion and Receive Analog to Digital A D Conversion in Analog Transmit Mode Using Dual 10 Bit Sigma Delta Converters e Square Root Raised Cosine SQRC Filtering in the Digital Mode Using Dual 10 Bit Sigma Delta Converters e 1 4 Differential Quadrature Phase Shift Key DQPSK Modulation Encoder in Digital Transmit Mode e Power Control Supervision for Radio Frequency RF Power Amplifier Automatic Frequency Control AFC Automatic Gain Control AGC and Synthesizer e Received Signal Strength Indicator RSSI and Battery Level A D Conversion Circuitry e Internal Clock Generation e Wide Band Data Clock Recovery and Manchester Decoding e General Purpose Digital Signal Processor DSP and Microcontroller Interface 3 9 V and 5 V Operation e Low Power Consumption TI and ARCTIC are trademarks of Texas Instruments Incorporated 1 1 1 2 TCM4300
51. low BST Offset PAEN Delay gt Delay A e SINT 95 p 19 5 v PAEN Delay d T 8 TXGO high 9 5 SINT periods d T 8 PAEN high TXGO low 19 5 SINT periods d T 8 PAEN low Figure 4 2 Transmit Power Ramp Up Ramp Down Functional Diagram 4 5 Transmit And Q Output Level In the digital mode the output level at TXI and TXQ is controlled by the TCM4300 During the burst but not including ramp up ramp down periods the average output level 2 Q2 1 2 should approximate the specified value There is no variable level control for TXI and TXQ within the TCM4300 other than the fixed ramping In the analog mode the output of the TCM4300 depends only on the sample values written to the and TXQ registers There are small differences in the average output power levels between the digital and the analog modes These differences require compensation at the system level by a small attenuation in the sample values of the analog output When a change in transmit power is necessary the microcontroller can change the value sent to the PWRCONT DAC the output of which can be connected to a voltage controlled attenuator in the transmit path of the RF section 4 6 Wide Band Data Demodulator The wide band data demodulator WBDD module demodulates the FM signal and outputs a Manchester decoded data stream The WBDD is used for receiving the analog control channels of the forward co
52. meter Measurement 31 MCLKOUT Timing Requirements 3 2 TCM4300 to Microcontroller Interface Timing Requirements Mitsubishi Read Cycle 3 3 4300 to Microcontroller Interface Timing Requirements Mitsubishi Write 3 4 TCM4300 to Microcontroller Interface Timing Requirements Intel Read 3 5 4300 to Microcontroller Interface Timing Requirements Intel Write Cycle 3 6 4300 to Microcontroller Interface Timing Requirements Motorola 16 Bit Read 3 7 TCMA4300 to Microcontroller Interface Timing Requirements Motorola 16 Bit Write Cycle 3 8 4300 to Microcontroller Interface Timing Requirements Motorola 8 Bit Read Cycle Page 2 6 3 5 3 6 3 7 Motorola 8 Bit Write Cycle 3 9 3 10 Switching Characteristics TCM4300 to DSP Interface Read Cycle 3 10 3 11 Switching Characteristics TCM4300 to DSP Interface Write Cycle 3 11 4 Principles of Operation
53. ming delay If a positive number is written the clock periods are shortened for the duration of the timing adjustment resulting in a timing advance The divider generates CMCLK normally divides MCLKIN by either 19 or 18 When the CMCLK period is being lengthened during a timing adjustment MCLKIN is divided by either 20 or 19 When the CMCLK period is being shortened MCLKIN is divided by either 18 or 17 see subsection 4 11 2 The divider used to generate a 9 72 MHz clock divides by 4 during normal operation by 5 when its period is being lengthened during timing adjustments and by 3 when its period is being shortened during timing adjustments Because CMCLK and the 9 72 MHz internal clock have different periods and the timing adjustments are limited to one period of MCLKIN per period of the clock these clocks take different times to complete the entire timing adjustment Because the total adjustment is the same number of MCLKIN periods for both clocks the relative phases of the two clocks are the same after the adjustment as they were before Both adjust counters reach zero when the adjustment is complete so there is no need to write to the timing adjustment register until another timing adjustment is required For each write to the timing adjustment register a single timing adjustment of the direction and magnitude requested is performed The output of each adjustment counter is fed to a variable modulus divider For counter A there are thr
54. must be connected together 76 91 DWBDINT DSP wide band data interrupt active low The DWBDINT output goes low to indicate that the wide band data WBD demodulation circuits have traffic on them Frequency modulation FM terminal is connected to the output of the FM discriminator FMRXEN 95 FM receive path enable A high output from FMRXEN can be used to enable the power for the receiver FM path IQRXEN In phase and quadrature receive path enable A high output on IQRXEN can be used to enable the power for receiver path LCDCONTR Liquid crystal display LCD contrast This LCDCONTR control DAC can be used to control the amount of drive to the liquid crystal display MCLKOUT Master clock out MCLKOUT is a buffered version of MCLKIN Microcontroller 5 bit parallel address bus MCAO through MCAA provide a 5 bit bus to address the microcontroller MCA4 is the MSB and MCAO is the LSB MCCLK Microcontroller clock MCCLK provides an adjustable frequency with 1 215 MHz at powerup Microcontroller interface chip select A high at MCCSH in conjunction with a low at MCCSL allows the microcontroller to read from or write to the TCM4300 Microcontroller interface chip select A low at MCCSL in conjunction with a high atthe MCCSH allows the microcontroller to read from or write to the TCM4300 7 Microcontroller 8 bit parallel data bus MCDO through MCD7 provides an 8 bit parallel data bus to send receive data to from the microc
55. ng edge of th W strobe MCRW TWD HO tw WSTB Pulse duration write strobe pulse width low on MCRW TWR STB t Setup time chip select MCCSH and MCCSL stable before TCS su CS falling edge of strobe MCRW SU t Hold time chip select MCCSH and MCCSL stable before TCS n h CS rising edge of strobe MCRW HO NOTE 3 Timings are based upon Intel 8C186 16 MHz MCDS tw WSTB 90 9096 MCRW 10 10 see Note A 0 tsu WA 4 th WA lt t 4 thw MCD7 MCDO X 9096 9096 MCCSH tsu CS tcs MCCSL 10 10 NOTE A Chip selection is defined as both MCCS and MCRW active Figure 3 5 Microcontroller Interface Timing Requirements Intel Configuration Write Cycle MTS 1 0 00 3 6 TCM4300 to Microcontroller Interface Timing Requirements Motorola 16 Bit Read Cycle see Figure 3 6 and Note 4 ards Meee MCRW stable before falling edge of C 2577 MCRW stable after rising edge of tsu RA address MCA stable before falling edge of Bus C address MCA stable after rising edge of t Enable time read data on falling edge of strobe MCDS to TRD en RD 4300 driving data bus MCD EN t Valid time read data on falling edge of strobe MCDS to v RD valid data MCD tinv Data MCD invalid after rising edge of strobe MCDS Disable time read data TCM4300 releases MCD data bus after rising edge of stro
56. ntrol channel FOCC and the forward voice channel FVC The bit error rate BER performance requirements are listed in Table 4 8 4 7 Table 4 8 Typical Bit Error Rate Performance WBD_BW 000 TEST CONDITIONS PARAMETER UNIT MEAN CNR The WBDD is controlled by the bits in the control register WBDCtrl see Table 4 9 Table 4 9 Bits in Control Register WBDCtrl BIT CODE FUNCTION WBD_LCKD o Indicates whether edge detector is locked 1 or unlocked 0 WBDON Turn the WBDD module on off 1 0 WBD BW Sets the appropriate PLL bandwidth 20 Hz 39 Hz 78Hz 156 Hz 313 Hz 625 Hz 1250 Hz WBD_LCKD This bit reduces the effects of signal dropouts due to fading In the Manchester coded signal there are two types of data edges One type occurs at the midpoint of each data bit and the other occurs randomly depending on the transmitted data sequence Inside the WBDD an edge detector rapidly synchronizes itself to the midpoint edges when the WBD LCKD bit clears to 0 However when a signal dropout occurs the edge detector may momentarily lock to the wrong edge because it cannot distinguish the midpoint edges from the data edges A small number of additional bits may be lost in this instance When the WBD LCKD bitis setto 1 the edge detector uses the WBDD internal phase lock loop PLL output to distinguish the correct edge Once acquisition of data has occurred when this bit is set to 1 the loss of bits d
57. o SynCtrlO 31h into SynCtrl1 and 32h into SynCtrl2 SYNDTA Apos sa o _ SYNLE1 SYNLEO 2 SYNRDY Figure 4 8 Example Synthesizer Output 4 13 Power Control Port For systems requiring minimum system current consumption power can be provided to each functional part of the TCM4300 only when that function is required for proper system operation To accomplish this the TCM4300 provides six external power control signals accessible through the DStatCtrl and MStatCtrl registers These signals can be used to minimize the on time of the functional units These power control signals are SCEN FMRXEN IQRXEN TXEN PAEN and OUT1 see Table 4 15 The polarity of each of these signals is high enable low disable Table 4 15 External Power Control Signals RESET SUGGESTED EXTERNAL APPLICATION t SCEN Speech codec microphone speaker interface circuit enable FMRXEN FM demodulator enable IQRXEN and Q receive enable IQRXEN enables the QPSK demodulator and the AGC amplifier Oo Transmit enable TXEN enables power to the transmitter signal processing circuits QPSK modulator voltage controlled amplifier driver amplifier PA negative bias This signal can be used to enable these subsystems only during the transmit burst in digital mode OUT1 User defined Power amplifier enable PAEN enables power to PA Oo In addition to allowing control of power to exte
58. ock Generation There are three options for generating the master clock A fundamental crystal or a third overtone crystal with a frequency of 38 88 MHz can be connected between the MCLKIN and the XTAL terminals or an external clock source can be connected directly to the MCLKIN terminal The MCLKOUT is a buffered master clock output at the same frequency as MCLKIN MCLKOUT can be used as the source clock for other devices in the system Setting the MCLKEN bit in the MStatCtrl register enables or disables this output The MCLKOUT enable is synchronous with MCLKIN to eliminate abnormal cycles of the clock output All output clocks are derived from the master clock MCLKIN The sample clocks for the digital and analog modes the 8 2 speech codec sample clock and the clocks for the A D and D A functions are also derived from the master clock 4 11 2 Speech Codec Clock Generation The TCM4300 generates two clock outputs for use with speech codecs the 2 048 MHz CMCLK and the 8 kHz CSCLK These clocks are generated so that each CSCLK period contains exactly 256 cycles of CMCLK Since 2 048 MHz is not an integer division of the 38 88 MHz MCLKIN one out of every 64 CMCLK cycles is 18 MCLKIN periods long and the remaining 63 out of 64 are 19 MCLKIN periods long The average frequency of MCLKIN is therefore 63 1 19 18 64 CSCLK is exactly CMCLK divided by 256 see Figure 4 4 To save power the codec clocks are only generated by TCM4300 when
59. of both the transmit waveforms and PAEN relative to the edges of TXGO after it is internally sampled by SINT The delays are increased in increments of 1 4 SINT 1 8 symbol period For delays of 1 SINT or greater the fractional part of the delay can be achieved using the BST offset register with the remaining integer SINT delay implemented externally by delaying the writing to TXGO and TXI The relative timing of PAEN and the transmit waveforms is not affected by the BST offset register The 15 54 standard describes shortened bursts and normal bursts The two types differ in duration and number of transmitted bursts burst length being determined by the TXGO bit 4 N 3 SINT Periods N Total number of bits sent 19 5 SINT Periods d T 8 M gt 6SINT Periods 9 5 SINT Periods gt _ 15 5 SINT Periods d T 8 lq d T 8 t SINT TXGO TXI data bit PAEN TXI Q output ramp Input Bits 000000 0 o0 o0 0 0 o gt gt gt gt gt Dibit transmission n D DO gt gt gt a n First MEP Last MEP t Total delay d SINT 4 or T 8 where d integer value 0 1 2 3 written to the BST offset register Figure 4 1 Power Ramp Up Ramp Down Timing Diagram 4 6 Dibit In TXGO BST Offset Channel Delay Delay 15 5 SINT Periods Transmit Channel Delay d T 8 Delay 0 1 4 1 2 3 4 from last symbol 2 SINT periods before TXGO goes
60. ola Mode 8 bits 4 30 Microcontroller Interface Connections for Motorola Mode 16 bits 4 31 1 Introduction Texas Instruments TI TCM4300 IS 54B advanced RF cellular telephone interface circuit ARCTIC provides a baseband interface between the digital signal processor DSP the microcontroller and the RF modulator demodulator in a dual mode IS 54B cellular telephone See the TCM4300 functional block diagram In the analog mode the TCM4300 provides all required baseband filtering as well as transmit D A conversion and receive A D conversion using dual 10 bit sigma delta converters In addition a WBD wide band data WBD 10 kb s Manchester frequency shift key FSK demodulator is provided to allow reduced DSP processing load during subscriber standby mode In the digital mode the TCM4300 accepts and Q baseband data and performs A D and D A conversion and square root raised cosine filtering using dual 10 bit sigma delta converters The TCM4300 also has a m 4 DQPSK modulation encoder for dibit to symbol conversion in the digital transmit mode The microcontroller interface is compatible with a wide range of microcontrollers A microcontroller can be used to communicate with the user interface keyboard display etc and to program up to three frequency synthesizers by using the on chip synthesizer interface circuit The TCM4300 provides advanced power control to minimize the power consumption of many dua
61. ontroller MCD7 is the MSB and MCDO is the LSB tZ high impedance 1 4 Terminal Functions Continued TERMINAL DESCRIPTION NAME MCDS 48 pe Microcontroller data strobe MCDS is configured by the signals present on MTSO and MTS1 MCLKIN 64 Master clock input The MCLKIN frequency input requirement is 38 88 MHz 100 ppm A crystal can be connected between MCLKIN and XTAL to provide an oscillator circuit As an alternative XTAL can be left open and an external TTL CMOS level clock signal can be connected to MCLKIN MCRW 47 Microcontroller read write Microcontroller read write operations are selected in accordance with the signals present on MTSO and MTS1 MTSO 36 Microcontroller type select configuration control inputs The interface is controlled by MTS 1 0 as follows 00 Intel microcontroller interface characteristics MTS1 37 10 Mitsubishi and Motorola microcontroller 16 bit bus interface characteristics 01 Motorola microcontroller 8 bit bus characteristics MWBDFINT 50 Microcontroller interrupt request A wide band data ready interrupt is output when the WBD demodulator is in analog mode or when a frame interrupt is sent by the DSP in digital mode MWDBFINT can be active high or low according to the levels of the MTSO and MTS1 signals OUT1 26 EE Output number 1 OUT1 provides a user defined general purpose data or control signal PAEN 25 Power amplifier enable PAEN can be used to enable the transmit powe
62. or each output with respect to VCM 3 Zero code error to Q with respect to other channel differential or single ended lt O Load impedance between P and N terminals Transmit offset DACs and Q resolution ine H en wo gt 3 Transmit offset DACs and average step size Transmit offset DACs and Q full scale positive output 3 x Transmit offset DACs and Q full scale negative output Transmit offset DACs differential nonlinearity Transmit offset DACs integral nonlinearity 3 Modulation Error In the digital mode during the transmit burst the complex output of the transmitter circuits consists of an ideal output I iqeal JQideal error e ej jeg In Table 4 5 the modulation error vector magnitude EVM is defined as the peak value of the magnitude of e relative to the ideal output e Modulation error percentage 100 lel 5 Table 4 6 and Table 4 7 show the frequency response of the transmit section for digital and analog mode respectively 4 4 Table 4 6 Transmit TX Channel Frequency Response Digital Mode PARAMETER TEST CONDITIONS UNIT Table 4 7 Transmit TX Channel Frequency Response Analog Mode MIN T 8 kHz to 15 kHz see Note 4 20 kHz to 45 kHz see Note 2 29 55 PARAMETER TEST CONDITIONS UNIT 0 kHz to 8 kHz see Note 1 Frequency response 2 45 kHz to 75 kHz see Note 2 55
63. p Ramp Down Functional Diagram 4 7 WBD Manchester Coded Data Stream 4 9 Codec Master and Sample Clock Timing 4 12 Timing and Clock Generation for 38 88 MHz Clock 4 14 Synthesizer Interface Circuit Block Diagram 4 16 Contents of SynData Registers 4 17 Example Synthesizer 4 18 Internal and External Power Control 4 19 Microcontroller DSP Data Buffers 4 20 DSP aa erat 4 26 Power On Reset Timingis cre ecs onis teste ea hele deen 4 28 vi List of Tables Title Page TCM4300 Receive Channel Control Signals 4 1 RXIP RXIN RXQP and RXQN Inputs AVpp V 4 5 V 5 V 4 2 Receive RX Channel Frequency Response FM Input in Analog Mode 4 3 Receive RX Channel Frequency Response RXI RXQ Input in Digital Mode 4 3 Transmit TX and Channel Outputs 4 4 Transmit TX Channel Frequency Response Digital Mode 4 5 Transmit TX Channel Frequency Response Analog Mode 4 5 Typical Bit Error Rate Performance WBD_BW 000 4 8
64. p time chip select MCCSH and MCCSL stable before TCS SU CS rising edge of strobe MCDS SU NOTE 5 Timings are based upon Motorola 68HC11D3 3 MHz and Motorola 68HC11G5 2 1 MHz MCDS 90 90 see Note A 10 10 tsu R W gt gt th R W 90 90 MCRW gt tsu RA th RA Pex tv RD amp 1 tdis RD t ten RD 49 inv 4 MCD0 MCD7 MCCSH 20 5 tsu CS E MCCSL 10 10 NOTE A Chip selection is defined as both MCCS and MCDS active Figure 3 8 Microcontroller Interface Timing Requirements Motorola 8 Bit Read Cycle MTS 1 0 01 3 9 4300 to Microcontroller Interface Timing Requirements Motorola 8 Bit Write Cycle see Figure 3 9 and Note 5 __ ce m 1027 MCRW stable before rising edge of rams o as PEINS Roe Hes MCRW stable after falling edge of tsu WA address MCA stable before rising edge of Lee Setup time write data stable MCD before falling edge of su W strobe MCDS TWD SU Hold time write data stable MCD after falling edge of tw WSTB Pulse duration write strobe pulse width high on MCDS TWR STB 6 ms t Hold time chip select MCCSH and MCCSL stable before TCS h CS rising edge of strobe MCDS HO t Setup time chip select MCCSH and MCCSL stable before TCS su CS falling edge of strobe MCDS SU NOTE 5 Timings are based upon Motorola 68HC11D3 3 MHz and Motorola 68HC11G5 2 1 MHz
65. pp 23V 25 z T All typical values are at TA 25 C 2 4 2 Reference Characteristics PARAMETER TEST CONDITIONS MIN MAX UNIT VOH VHR High level output voltage gt 05 02 0 5 AVpp 0 2 FMVOX or IQRXEN 100 or TXEN high Output resistance FMVOX or or TXEN low t All typical values are at DVpp 5 V AVpp 5 V and TA 25 C 2 2 2 4 3 Terminal Impedance FUNCTION Receive channel input impedance single ended RXIP N and RXQP N Transmit channel output impedance single ended TXIP N and TXQP N 40 50 100 MIN UNIT 40 70 kQ NEM FM input impedance WBD 25 200 MCLKOUT impedance MCLKOUT at 3 3 V MCLKOUT at 5 V T All typical values are at DVpp 5 V AVpp 5 V and TA 25 C unless otherwise specified 2 4 4 RXIP RXIN RXQP and PARAMETER Input voltage range Input voltage forfull Differential Scale digital output Single ended Nominal operating Differential level Input CMRR RXI RXQ Sampling frequency SINT digital mode Single ended o ojo ala 79 Sampling frequency SINT analog mode Receive error vector magnitude EVM sample timing skew A D resolution Signal to noise plus distortion Integral nonlinearity Gain error Q channel Gain mismatch between and Q Differential dc offset voltage ADreowon
66. q 0 125 V peak to peak response 18 kHz to 45 kHz see Note 2 45 kHz to 75 kHz see Note 2 gt 75 kHz distortion Absolute channel delay QIN to 0 125 V peak to peak 0 kHz 15 kHz digital OUT NOTES 2 Stopband 4 Deviation from ideal 0 35 square root raised cosine SQRC response Peak to peak group delay 0 125 V peak to peak 0 kHz 15 kHz 4 3 Transmit Section The transmit section operates in two distinct modes digital or analog The mode of operation is determined by the MODE bit of the DStatCtrl register In the digital mode data is input to the transmit section by writing to the TXI register The resulting output is a 7 4 DQPSK modulated time division multiplexed TDM burst In the analog mode the data is in the form of direct and Q samples which are written to both the TXI and TXQ registers then D A converted filtered and output through TXIP TXIN TXQP and TXQN The and Q outputs are zero IF FM signals that is no baseband connection is necessary for FM transmission In the digital mode MODE 1 the data is written to the TXI register using the SINT interrupt to synchronize the data transfer The TCM4300 performs parallel to serial conversion of the bits in the TXI register and encodes the resulting bit stream as 1 4 DQPSK data samples These samples are then filtered by a digital 4 3 square root raised cosine SQRC shaping filter with a roll off rate of o 0 35 and converted to sampled
67. r and Q circuits Setting the MODE bit low connects RXQP to the FM input and RXQN to VHR In the digital mode MODE bit set high setting IQRXEN high turns on both sides of the receiver The TXEN enables the internal transmit functions When the TXEN bit is set low the PWRCONT output goes to a high impedance state and the PAEN output is set low The TXEN signal can be used to power down most of the external transmit circuits between transmit bursts In the analog mode MODE bit set low PAEN is high whenever TXEN is active and SYNOL is low The SYNOL input can be used as an indication to the TCM4300 that the external synthesizers are out of lock The PAEN signal is gated by SYNOL to prevent off channel transmissions The TXEN IQRXEN and MODE signals are generated by sampling the corresponding bits of the DStatCtrl register with the internal SINT The effect of a write to the DStatCtrl register on these signals does not appear until the next SINT after the write 4 14 Microcontroller DSP Communications The microcontroller and the DSP communicate by means of two separate 32 byte first in first out FIFO buffers Figure 4 10 illustrates this scheme The microcontroller writes to FIFO A but data read from the same address comes from FIFO B On the DSP side the situation is reversed Send CINT CINT Status Clear DINT Send DINT DINT Status Clear CINT Figure 4 10 Microcontroller DSP Data Buffers To send
68. r amplifier This signal is active high PWRCONT 16 Power amplifier PA power control The PWRCONT DAC output can be used to control the amount of power output from the PA RBIAS 99 Input for bias current setting resistor To achieve correct bias voltage a 100 kQ 1 tolerance resistor connected between RBIAS and AVss is recommended REFCAP 100 Reference decoupling capacitor For proper decoupling It is recommended that a 3 3 uF capacitor in parallel with a 470 pF capacitor be connected between REFCAP and ground RSINL 59 EN Reset input low An active low applied to RSINL resets the TCM4300 RSSI 2 mE Received signal strength indicator RSSI samples received signal strength RSOUTH 60 Reset out high An active high is output from RSOUTH for 10 ms after the TCM4300 is powered up RSOUTL 61 Reset out low An active low is output from RSOUTL for 10 ms after the TCM4300 is powered up RXIN Negative receive input The in phase differential negative baseband received signal is applied to RXIN RXIP Positive receive input The in phase differential positive baseband received signal is applied to RXIP RXQN Negative receive input The quadrature negative baseband received signal is applied to RXQN RXQP Positive receive input The quadrature differential positive baseband received signal is applied to RXQP Intel is a trademark of Intel Corporation Mitsubishi is a trademark of Mitsubishi Inc Motorola is a trademark of Motorola Inc
69. r battery voltage 3 CVRDY A D conversion is complete and can be read from the RSSI or battery register location CVRDY goes to 0 when the microcontroller reads from either of these locations AuxFS 1 Auxiliary DACs full scale select The auxiliary DACs are AGC AFC PWRCONT and also LCD CONTR DAC The microcontroller selects AuxFSIO the full scale output ranges with these bits see Table 4 11 and uxFS 0 Table 4 12 for bit to output range mapping Microcontroller PA enable A 0 indicates that the external PA enable line is prevented from going active see Figure 4 9 Offset and TXQ Offset These registers allow the differential offset voltages TXIP TXIN and TXQP TXQN to be adjusted to compensate for internal and or external offsets The magnitude of adjustmentis D x step size where D is 6 bit 2s complement integer written into bits 5 0 of these registers as shown here TXI Q Offset TXI Q Value 4 18 LCD Contrast The LCD contrast register allows for 16 levels of control of terminal LCD contrast The register is input to the LCD contrast D A converter allowing control of the level of intensity of the LCD display as shown here p e gpl e LCDEN active low LDC D A LCD Contrast Reserved Sr W 4 24 4 19 DSP Register Map The register map accessible to the DSP port is shown in Table 4 20 and Table 4 21 There are 14 system addressable locations Note that the
70. r quality control techniques are utilized to the extent deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Certain applications using semiconductor products may involve potential risks of death personal injury or severe property or environmental damage Critical Applications SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED INTENDED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT APPLICATIONS DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS Inclusion of TI products in such applications is understood to be fully at the risk of the customer Use of TI products in such applications requires the written approval of an appropriate TI officer Questions concerning potential risk applications should be directed to TI through a local SC sales office In order to minimize risks associated with the customer s applications adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards TI assumes no liability for applications assistance customer product design software performance or infringement of patents or services described herein Nor does TI warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combinat
71. rnal functional modules these power control bits combined with other control bits are used to control internal TCM4300 functions This control system is shown in Figure 4 9 WBD_ON x 9 gt WBD Demodulator Circuit FMRXEN MintCtrl TX Signal Processing DStatCirl PWRCONT Enable Hi z when disabled SYNOL v v T MStatCtrl ransmitter 2 Control Circuits 4 TXONIND MPAEN Figure 4 9 Internal and External Power Control Logic OUT1 SC Clock Generation SCEN FMRXEN Q Side Input MUX Q Side RX Enable 1 2 1 5 RX Enable VHR High Drive Enable Hi Z when disabled IQRXEN IQRXEN TXEN TXEN MODE TXGO e TX and Filter Select To allow for further system power savings the TCM4300 receive and Q channels are enabled separately because only the Q side is used analog mode The FMVOX bit controls the Q side input multiplexer When FMVOX is high the QP side of the receiver is connected to the FM input terminal the QN input is connected to the VHR reference voltage and the Q side of the receiver is powered up The MODE bit controls the Q side filter characteristics for digital or analog mode The IQRXEN bit enables both the and Q receiver sides The bit IQRXEN can be set high while still in analog mode FMVOX high or MODE low to allow sufficient power up settling time for the external receive
72. ster indicate the action to be taken when a 1 is written to the respective bit When these bits are being read a 1 indicates that the corresponding interrupt is pending A 0 indicates that the interrupt is not pending Writing a 0 to any bit has no effect Writing a 1 to the clear bits clears the corresponding interrupt and the interrupt terminal returns to its inactive level Writing a 1 to the send bits causes the corresponding interrupt to go active DIntCtrl SDIS When a 1 is written to the SDIS bit the SINT interrupt going to the DSP is disabled The disabling and re enabling function is buffered to prevent the SINT signal from having shortened periods of output active The SDIS bit is active 1 upon reset R W The DStatCtrl register contains various signals needed for system and control These are described in Table 4 22 PO R W Table 4 22 DStatCirl Register Bits RESET 2 go TXGO is used in digital mode to initiate 1 and terminate 9 rw TXGO 0 a transmit burst R W MODE n Analog 0 mode select MODE affects the clock dividers and the ae modes of operation and the Q side filter Speech codec enable microphone speaker interface chip SCEN is 7 R W SCEN connected to bits SCEN also enables 1 or disables 0 the internal speech codec clock generation circuits 2 048 MHz 8 kHz outputs FM voice enable When FMVOX is 1 it enables the Q side of the internal R W
73. the SCEN bit of the DStatCtrl register is set high When SCEN is low both outputs CSCLK and CMCLK are held low SCEN is also available as an output MCLKIN x 2 048092 MHz 4 11 3 Microcontroller Clock Avariable modulus divider provides a selection of frequencies for use as a microcontroller clock The master clock is divided by an integer from 32 to 2 giving a wide range of frequencies available to the microcontroller 1 215 MHz to 19 88 MHz The modulus can be changed by writing to the microcontroller clock register The output duty cycle is within the requirements of most microcontrollers that is from 40 to 60 At power on reset the clock divider defaults to 1 215 MHz 4 11 4 Sample Interrupt SINT The SINT interrupt signal is the primary timing signal for the TCM4300 interface The primary function of the SINT is to indicate the ready condition to receive or transmit data It also conveys timing marks to allow for the synchronization of system DSP functions In the digital mode SINT is used in conjunction with the received sync word to track cellular system timing The SINT can be disabled by writing a 1 to the SDIS bit of the DIntCtrl register When enabled the SINT operates continuously at 48 6 kHz in the digital mode and at40 kHz inthe analog mode The SINT signal does not require an interrupt acknowledge The SINT is active low for 5 5 MCLK cycles 141 5 ns in the analog mode and 6 5 MCLK cycles 167 2 ns in the digital mode
74. the synthesizer interface consists of five signals SYNCLK is the common data clock for all attached synthesizer chips The clock rate is MCLK 128 304 kHz The clock pulse has 50 duty factor The serial data output SYNDTA is common to all synthesizers Three strobe signals SYNLEO SYNLE1 and SYNLE2 are provided There is one for each synthesizer chip The attributes of this interface are controlled by means of the synthesizer control registers SynCtrl0 SynCtrl1 and SynCtrl2 These attributes determine e The polarity of the clock rising or falling edge e Whether data is shifted left or right e number of bits sent to the synthesizer e The timing and polarity of the latch enable bits e selection of which synthesizer to program Programming of the synthesizers is accomplished by writing to four microcontroller mapped data registers These registers are chained to form a 32 bit data shift register that can be operated in either shift left or shift right mode This register set can accommodate various formats of synthesizer control data When fewer than 32 bits of data are to be transmitted the significant data bits must be justified such that the first bit to be transferred is either the LSB or the MSB of the register set as defined by the control register for LSB or MSB first operation All 32 bits of the data register are transmitted each time see Section 4 15 for register location and Figure 4 6 for a representative block
75. tup time chip select MCCSH and MCCSL stable before TCS su CS rising edge of strobe MCDS SU NOTE 4 Timings are based upon Motorola 68HC000 16 67 MHz and Motorola 68302 16 MHz MK tw wsTB 90 90 MCDS X 10 10 see Note tsu R W lt gt th R W 10 y 10 tsu WA gt th WA C90 7 lec nw MCD0 MCD7 X X 90 90 MCCSH gt tsu CS ics MCCSL 10 10 NOTE A Chip selection is defined as both MCCS and MCDS active Figure 3 7 Microcontroller Interface Timing Requirements Motorola 16 Bit Write Cycle MTS 1 0 10 3 8 4300 to Microcontroller Interface Timing Requirements Motorola 8 Bit Read Cycle see Figure 3 8 and Note 5 Cm ce x n MCRW stable before rising edge of Wen o A Pablo MCRW stable after falling edge of tsu RA address MCA stable before rising edge of tracy t Enable time read data on rising edge of strobe MCDS to TRD 10 en RD TCM4300 driving data bus MCD EN t Valid time read data on rising edge of strobe MCDS to valid TRD v RD data MCD DV tinv Data MCD invalid after falling edge of strobe MCDS TRD INV T Disable time read data TCM4300 releases MDS data bus TRD 28 dis RD after falling edge of strobe MCDS DIS t Hold time chip select MCCSH and MCCSL stable before TCS h CS falling edge of strobe MCDS HO is t Setu
76. ue to signal dropouts is restricted to the fade duration only When the WBDD PLL is not synchronized as at power up the LCKD bit must be cleared to 0 to allow edge synchronization to the data WBD BW The variable bandwidth is required for fast acquisition in the beginning using a wide bandwidth for the PLL and a narrower bandwidth is used afterwards to reduce the likelihood of noise causing loss of synchronization The WBDCtrl register is accessible by both the DSP and the microcontroller 4 7 Wide band Data Interrupts The WBDD operates whenever WBD is high and it does not require the receive channels to be enabled While WBD ON is high every 800 us 8 bits are placed in the WBD register which is accessible by both the DSP and the microcontroller ports This value should be written at the same time as WBD ON is initially set high 4 8 At the same time the interrupts DWBDINT and MWBDFINT are asserted The interrupt rate is 800 us 8 bits 10 kHz These interrupts are individually cleared when the WBD register is read by the corresponding processor They can also be cleared by their respective processor by writing a 1 to the corresponding clear WBD bit There is one WBD control register It can be written to by either processor port 4 8 Wide band Data Demodulator General Information The WBDD recovers the transmitter clock from the data stream which is Manchester encoded and decodes the data bits Consideration
77. ution LCDCONTR DAC Gain offset error full scale AGC AFC PWRCONT DAC GNE 1 Gain offset error full scale LCDCONTR DAC Differential nonlinearity Integral nonlinearity Range settings depends only on AUXFS 1 0 The supply voltage is not detected 0 75 2 4 2 4 7 Auxiliary D A Converters Slope AGC AFC PWRCONT NOMINAL LSB NOMINAL OUTPUT VOLTAGE NOMINAL OUTPUT VOLTAGE AUXFS 1 0 SLOPE FOR DIGITAL CODE 128 FOR DIGITAL CODE 256 UE MIDRANGE MAX VALUE SETTING 0 V 1 The maximum input code is 255 The value shown for 256 is extrapolated 2 4 8 Auxiliary D A Converters Slope LCDCONTR NOMINAL OUTPUT VOLT NOMINAL OUTPUT VOLTAGE VALUE AGE FOR DIGITAL CODE 8 FOR DIGITAL CODE 169 0 MIDRANGE MAX VALUE V V oo 56 P The maximum input code is 15 The value shown for 16 is extrapolated 2 4 9 RSSI Battery A D Converter Gain offset error full scale LSB AUXFS 1 0 NOMINAL LSB Differential nonlinearity Input resistance Integral nonlinearity 0 75 1 LSB 2 5 2 5 Operating Characteristics Over Full Range of Operating Conditions Unless Otherwise Noted 2 5 1 Receive RX Channel Frequency Response RXI RXQ Input in Digital Mode PARAMETER TEST CONDITIONS MAX UNIT 0 125 V peak to peak 0 kHz to 8 kHz see Note 4 40 55 075 MIN Frequency 0 125 V pe
78. zer interface is idle and ready for programming When SYNRDY is low the synthesizer interface is busy Controlling the synthesizer interface is straightforward The microcontroller checks to see if the SYNRDY bitis low When it is low the synthesizer interface is not ready When SYNRDY goes high the microcontroller programs the desired information into the four registers When the microcontroller write to the SynCtrl2 register is complete the synthesizer interface sets the SYNRDY bit low and begins to send data clock and latch enable according to the format established in the registers SYNRDY returns high when the entire operation is complete Up to 31 data bits plus a latch enable SYNLEO 1 2 can be programmed in one programming cycle When data greater than or equal to 32 bits must be programmed TI recommends using two or more programming cycles with data in each cycle and a latch enable in the final programming cycle Two or more programming cycles are recommended because all programming cycles must contain at least one SYNCLK pulse whereas the latch enable can be suppressed in any programming cycle Figure 4 8 shows an example of the synthesizer output signals In this case an 18 bit pattern 0x10664 was chosen to write into synthesizer 1 with a positive going latch enable pulse at the eighteenth bit In order to do so the microcontroller writes the values 00h into SynData0 00h into SynData1 99h into SynData2 41h into SynData3 52h int

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