Texas Instruments PCI445X User's Manual
Contents
1. Important Information 1 5 Important Information This section clarifies important system implementation 1 5 1 G RST Clamping Rail G_RST is clamped to Vccp so removing Vccp causes assertion of G_RST Figure 1 7 G_RST and Vocp Relationship Vecr Vecp 0 VCCP removed E G RST lt G RST All other signals with clamping rails behave the same way 1 5 2 PME RI_OUT Bit Definition If PME is selected only PME is signaled on the PME RI_OUT terminal If RI OUT is selected only RI_OUT is signaled The PCI445X device can signal PME and RI_OUT as completely separated signals In this case RI_OUT should be assigned on the MFUNC terminal 1 5 3 Serialized IRQ Data Stream PCI clock is needed for operation of the PCI445X serialized IRQ state machine During SUSPEND assertion the PCI445X device stops the IRQSER stream Before asserting SUSPEND IRQSER must be stopped 1 5 4 Socket Power Control An internal or external CLOCK source is needed for the socket power control through the P2C interface The internal ring oscillator is on while the core Vcc is applied to the PC1445X device External CLOCK source is dependent on the system 1 5 5 External CLOCK Frequency for P2C Interface If an external P2C CLOCK is used then it will affect Advanced CD line noise filtering Li VS test speed TPS22X6 power control interface speed Use of the internal ring oscillator is recommended Recommended external CLOCK2. These terminals can be connected to the system PCI bus directly GNT and REQ are dedicated signals from the PCI bus arbitrator OU PERR SERR and LOCK PERR and SERR are required signals LOCK is an optional signal and available in MFUNC1 MFUNC3 and MFUNC7 O IDSEL If there is a pulldown on LATCH then the IDSEL will be routed to AD23 but the consequence of this is that the system designer must use AD23 as System Implementation IDSEL there is no alternative If another AD line is to be used for IDSEL then the system designer must leave the pullup off LATCH and use MFUNC7 to route IDSEL Also if AD23 is used then the resistive coupling should not be used Refer to the Implementation Note System Generation of IDSEL in the PC Local Bus Specification Revision 2 2 section 3 2 2 3 5 PCI Local Bus Specification Revision 2 2 section 4 2 6 footnote 31 recommends resistive coupling A 100 O resistor is recommended Y PRST PCI reset and G RST Global reset G_RST initializes all of the registers and state machines of the PCl445X device and PRST does not G RST should be asserted during power on and rebooting It puts the PCI445X device into the initialized state PRST does not initialize global reset only bits and if PME is enabled PME context bits Refer to Table A 1 Global Reset Only Cleared Bits and Table A 2 PME Context Bits PRST is connected to PCI RESET G_RST requires a special signal in the motherboard It wi
3. 0x08 0x00 0x00 0x00 0x22 0x22 0x22 0x04 0x02 0x66 0x61 0x00 0x82 11111111 711111111 gl a a ei 700000000 700010010 700110100 701010110 701111000 701100000 710110000 701000100 700001000 700000000 00000000 00000000 00100010 00100010 00100010 700000100 700000010 701100110 701100001 00000000 10000010 System Implementation Flag Byte if OxFF do not load Function 0 SubSys Byte 3 SubSys Byte 2 SubSys Byte 1 SubSys Byte 0 SysCtrl Byte 0 SysCtrl Byte 1 SysCtrl Byte 2 SysCtrl Byte 3 General Control GP Event Enable GP Output MF Route Byte 0 F Route Byte 1 MF Route Byte 2 MF Route Byte 3 Card Control Device Control Diagnostic PMC Byte 1 ExCA ID and Rev Insert Insert Insert Insert your SSVID MSB your SSVID LSB your SSID MSB your SSID LSB PCI445X Device 1 13 System Implementation 1 3 1 P2C Interface for TPS22X6 Power Switch The interface between the PC1445X device and TPS22X6 power switch is serialized to reduce the number of signal lines The P2C interface requires only three lines to control the switch As a PCI445X default the CLOCK signal is selected from an external source It is usually provided from RTC 32 768 kHz The PCI445X device can also generate this clock from an internal ring oscillator The typical frequency of the internal ring oscillator is 16 kHz If using the internal clock source the
4. CAD20 a Ts A CPERR STS Note The voltage sense terminals VS1 CVS1 VS2 CVS2 are always driven low except under the following conditions 1 High impedance state during RESET 2 Toggle during socket interrogation C 2 Table C 1 PCI445X Terminal Function paa and Buffer Types Continued Signal Name A_CVS2 A_RSVD A_RSVD A_RSVD ADO AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 fe Anes EL is s es T B s es I Ros es CO E wm es m s m m es T m qm CIC Fre kw qm eem p rs we qm eee pe T kw qs eem pe fe kw qm feo ee re we qs feo Tee E ws qe Tem T wm ecw ve rs wr EA rs ww qm feo Tem rs kw qm eoe E woe esee for T e qs eee rw rs kw m esee fee E m qm ECON E m qs ecw fe E p qs fpo pe fe me ECON E e fs porn fee fe me s ECON E mm qs ees ee E Fw s ecw pr fe ke s EN LE PCI445X Buffer Types Note The voltage sense terminals VS1 CVS1 VS2 CVS2 are always driven low except under the following conditions 1 High impedance state during RESET 2 Toggle during socket interrogation PCI445X Buffer Types C 3 PCI445X Buffer Types Table C 1 PCI445X Terminal Function Assignment and Buffer Types Continued B CAD22 rs B CSERR B11 STS B_CAD23 aa rs e B CSTOP A20 STS B CAD31 pps Ts C BEO TS B_CAUDIO Ct Mo 1 C BET TS B CBLOCK o sTs C BE2 TS B CCD2 Bo fl FRAME V20 STS B CDEVSE
5. And PRST uis EL it ans ame at ae 1 3 14 3 PME and RI Signaling 1 3 1 14 ZV AA 1 3 1 1 5 EEPROM for Subsystem Vendor and Subsystem ID Registers 1 3 1 1 6 PCI and ISA Style Interrupt 0 0 eee ees 1 4 1 1 7 Socket Power Switches 0 00 ccc eese eese 1 4 1 1 8 Distributed DMA DDMA 000 cee IH n 1 4 1 1 9 Optional PCI Signals 0 ccc eens 1 4 1 1 10 Socket Activity LEDs 00 00 a nia eee ees 1 5 1 1 11 MFUNC7 MFUNCO Terminal Assignments 2 2 22222 2 nennen 1 5 1 1 12 Miscellaneous Functions Description 0 0 0 0 eee ees 1 5 1 2 System Implementation 00 ccc nett eens 1 8 12 1 Clamping Rails iei en ehh eae a 1 8 1 2 2 PCI Bus Interface teen eens 1 8 1 2 3 PC Card Interface 0 cece teens 1 10 1 24 2 Wire I2C Interface for EEPROM 1 10 1 2 Sample PCI445X EEPROM Data File 00 0 eens 1 12 1 3 1 P C Interface for TPS22x6 Power Switch 0 0 cece eee eee aes 1 14 1 3 2 Zoomed Video ZV Interface 0 eee es 1 14 1 3 3 Interrupt Signaling Interface llle 1 15 1 3 4 Miscellaneous Signals 0 00 teens 1 15 1 3 5 Requirement of Pullup Pulldown Registers 0000 c eee eee eee 1 16 1 4 BIOS Considerations sersises N S RT KE T ekai nter es nn 1 19 141 AMMA Z AVON usada tidad tab 1 19 1 4 2 System Sleeping State Consideration 00 0 cece 1 20 1 43 Docking
6. CardBus 32 bit interface mode Damping resistor on CCLK terminal A series damping resistor is recommended on the CCLK signal The damping resistor is system dependent If line impedance is in the 60 90 Q range a 47 Q resistor is recommended see PC Card Standard Revision 7 Lj CD line filtering PCI445X device has the advanced CDx line filtering circuit It provides 90 us of noise immunity A 270 pF filtering capacitor is still recommended for each of the power supply terminals Vcc Vecs and Vccp Socket power supply Socket power is supplied through TPS22X6 power switches The PCI445X device requires VccA and Vccp for the protection of the other device s on the bus 1 2 4 2 Wire I2C Interface for EEPROM The PCI445X device can load configuration registers from EEPROM after G_RST assertion The SDA and SCL lines require pullup resistors to enable this function Depending on the EEPROM requirements the SDA and SCL lines must be pulled up to 3 3 V or 5 V Figure 1 3 EEPROM 2 Wire Interface PCI445X EEPROM slave address should be 101 0000b Table 1 1 Registers and Bits Loadable Through Serial EEPROM System Implementation Register Offset Register Bits Loaded From EEPROM The following are configuration registers for the OHCI function function 2 PCI register 2Ch PCI subsystem ID 15 0 PCI register 2Dh PCI vendor ID 15 0 PCI register 3Eh PCI maximum latency minimum
7. MFUNC7 0 0 0 0 Latched 0 0 0 1 Latched Latched CSTSCHG 0 0 1 0 Latched 0 0 1 1 Latched RENE 0 1 0 0 Latched mE 0 1 0 1 Latched Latched CSTSCHG 0 1 1 0 Latched 0 1 1 1 Latched Latched CSTSCHG 1 0 0 0 Latched 1 0 0 1 Latched Latched CSTSCHG 1 0 1 0 Latched CSTSCHG CSTSCHG 1 0 1 1 Latched CSTSCHG CSTSCHG 1 1 0 0 Latched 1 1 0 1 Latched Latched CSTSCHG 1 1 1 0 Latched CSTSCHG 1 1 1 1 Latched Latched CSTSCHG CSTSCHG Table B 2 16 Bit Card RI STSCHG and Wake Up Signals Truth Table B 2 RINGEN RIMUX RIENB PME EN PME STAT RI OUT PME MFUNC7 0 FEINE ze 1 0 0 0 Latched 1 0 0 1 Latched Latched RI 1 0 1 0 Latched RI RI 1 0 1 1 Latched RI RI 1 1 0 0 Latched 1 1 0 1 Latched Latched RI 1 1 1 0 Latched RI 1 1 1 1 Latched Latched RI RI Appendix C PCI445X Buffer Types Topic Page C 1 PCI445X Buffer Types C 2 C 1 PCI445X Buffer Types C 1 PCI445X Buffer Types Table C 1 PCI445X Terminal Function Assignment and Buffer Types C8 TS P1 TS ko Ja fe CECI ku m s farm e A CADG Iz rs A CC BEO TS A CAD7 rs A CC BET TS A_CAD8 TSO A CC BE2 TS A CAD9 s A CC BE3 TS A CAD15 B rs A_CFRAME STS A_CAD16 a rs A_CGNT STS A_CAD18 a Ts A CIRDY STS A CAD19 a P A CPAR TS A
8. be slowed down rather than stopped by CCLKRUN If CCLKRUN is set the CLKCTRLEN CardBus socket 20h bit 16 and CLKCTR CardBus socket 20h bit 0 bits are both set to 1 The clock is slowed down to 1 16 In this mode the PCI clock is not allowed to stop A PC card power change event can be reported to the system as SMI IRQ2 or CSC It can be controlled with the SMIROUTE SMISTATUS and SMIENB bits system control register PCI offset 80h bits 26 25 and 24 respectively 1 1 12 10 Socket Power Lock Socket power can be protected from software control in the D3pot state It can be done with the socket power lock bit device control register PCI offset 92h bit 7 1 1 12 11Vcc Protection The VCCPROT bit system control register PCI offset 80h bit 21 controls Vcc protection for 16 bit cards This feature protects applying the wrong higher Vcc to the 16 bit card If a 3 3 V only card is inserted then it protects against applying 5 V to the card Default is 0 enabled 1 1 12 12 ZV Port Control and Auto Detect Function Internal zoomed video buffers can be controlled with the ZV autodetect function It can be turned on by setting the zoomed video autodetect bit multimedia control register PCI offset 84h bit 5 to 1 Autodetect priority encoding bits multimedia control register PCI offset 84h bits 4 2 can control the priority scheme PCI445X Device 1 7 System Implementation 1 2 System Implementation This section d
9. by changing the PWRSAVINGS bit system control register PCI offset 80h bit 6 to 0 When this bit is enabled default PCI CLOCK is internally gated for a nonfunctioning circuit For example the CardBus interface does not function when a 16 bit card is inserted This power saving mode will not degrade performance therefore the default setting is recommended 1 1 12 7 PME RI OUT Terminal Control Clarification PME RI OUT terminal can be set up to signal a combination of these events The terminal is set up using the PME RI OUT bit system control register PCI offset 80h bit 0 the RIENB bit card control register PCI offset 91h bit 7 and PME enable bit power management control status PCI offset A4h bit 8 If the terminal is set up as RI OUT and RIENB has ring indicate enabled then this signal follows the RI OUT signal for 16 bit I O cards If RIENB has ring indicate disabled but PME has PME enabled then this line reflects the state of the PMESTAT bit power management control status PCI offset A4h bit 15 If both PME and ring indicate are disabled then the line remains high If the line is configured as PME and PME is enabled then this line follows the state of the PMESTAT bit otherwise the line remains high 1 1 12 8 CLKRUN Control PCLK can be kept running using CLKRUN protocol by setting the KEEPCLK bit system control register PCI offset 80h bit 1 to 1 1 1 12 9 SMI System Features Selection CCLK can
10. grant 11 8 3 0 PCI register FOh PCI miscellaneous configuration 15 13 10 3 0 PCI register F4h Link enhancements control 7 2 1 OHCI register 24h 1394 global unique ID Hi 31 0 OHCI register 28h 1394 global unique ID Lo 31 0 The following are configuration registers for PC Card functions functions O and 1 PCI register 40h Subsystem vendor ID 15 0 PCI register 42h Subsystem ID 15 0 PCI register 80h System control 31 24 22 14 6 3 1 0 PCI register 86h General control 3 0 PCI register 89h General purpose event enable 7 6 3 0 PCI register 8Bh General purpose output 3 0 PCI register 8Ch Multifunction routing 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 PCI register 91h Card control 7 6 2 0 PCI register 92h Device control 7 6 2 0 PCI register 93h Diagnostic 7 5 0 PCI register A2h Power management capabilities 15 PCI register ExCA ID and revision 7 0 PCI445X Device 1 11 System Implementation 1 3 Sample PCI445X EEPROM Data File Following is an example EEPROM data file used with the PCI445X device 25 PCI4450 default Register OxXX Binary 00 0x43 01000011 4 bits PCI min gnt lower 4 01 Ox4C 01001100 your SSVID LSB 02 0x10 00010000 your SSVID MSB 03 0x11 00010001 your SSID LSB 04 0x80 10000000 your SSID MSB 05 OxC2 11000010 defaults 06 0x40 0100000
11. 0 07 0x56 01010110 008 0x28 00101000 109 0x00 00000000 20A 0x08 00001000 30B OxXX XXXXXXXX incremented from serial dat OC OxXX XXXXXXXX incremented from serial dat OD OxXX XXXXXXXX incremented from serial dat OE OxXX XXXXXXXX incremented from serial dat OF OxXX XXXXXXXX 10 0x10 00010000 IT 0x00 00000000 12 0x24 00100100 13 OxFF 11111111 19 OxFF 11111111 1A OxFF 11111111 1B OxFF 11111111 LG OxFF 11111111 EEPROM Data File Description PCI max_lat bits lower PCI Subsystem Vendor ID PCI Subsystem Vendor ID 1sbyte Insert msbyte Insert PCI Subsystem ID lsbyte PCT Subsystem ID Msbyte Link MiniROM_Addr 1394 1394 1394 1394 1394 1394 1394 1394 ROM CRC Link GUIDHi GUIDHi GUIDHi GUIDHi GUIDLo Enhancement Insert Insert Register HC Control lsbyte Insert GUIDHi byte lsbyte Insert GUIDHi byte msbyte Insert GUIDHi byte msbyte Insert GUIDHi byte lsbyte GUIDLo byte O0 auto lsbyte GUIDLo byte 1 auto msbyte GUIDLo byte 2 auto msbyte GUIDLo byte 3 auto Calculated by Enh Byte 1 PCI Misc Byte O0 PCI Misc Byte 1 this area reserved ELynx IF 20 and 1 21 22 23 24 2 5 26 27 28 29 2A 2F 30 31 32 33 34 OxFF OxFF OxFF 0x00 0x12 0x34 0x56 0x78 0x60 OxBO 0x44
12. 3 12 System lmplementation as 1 8 1 3 Sample PCI445X EEPROM Data File 1 12 1 4 BIOS Consideration S R Tar ST TS RSE TER 1 19 1 5 Important Information e ae 1 22 Figure 1 1 illustrates a platform using the PCI445X device along with the TSB41LV03 3 port PHY which provides the necessary interface to implement a 3 port IEEE1394 node Figure 1 1 Typical System Architecture lt PCI Bus gt 19 South Sound Graphics Controller Controller POIs ZV Socket Audio 4 Power Power Codec Switch PC Card 2 EEPROM Interrupt PME RI TSB41LV03A PHY System Features Selection 1 1 System Features Selection This section explains selectable system features Feature selection is required for GPIO and MFUNC terminal assignments and PCI445X register initialization Detailed system implementation methods are described in the following sections All functions cannot necessarily be used at the same time because of the limitations of programmable multifunction terminals i e MFUNC7 MFUNCO 1 1 1 Package Types The Texas Instruments PCI445X device is offered in two package types 256 terminal ball grid array BGA and 257 terminal MicroStar BGA MicroStar BGA is a type of chip scale packaging CSP 1 1 2 G_RST and PRST The PCI445X device has two reset inputs G RST and PRST G_RST resets all registers and state machines PRST resets registers that are not required to ma
13. E and RI Behavior provides truth tables that explain events and conditions which can wake up a device that has been placed in partially functional state for power conservation Appendix C PCI445X Buffer Types lists the type of signal buffering used for input and or output on each terminal of the device Notational Conventions This document uses the following conventions Program listings program examples and interactive displays are shown inaspecial typeface similar to a typewriter s Examples use a bold version ofthe special typeface for emphasis interactive displays use a bold version ofthe special typeface to distinguish commands that you Contents enter from items that the system displays such as prompts command output error messages etc Here is a sample program listing 0011 0005 0001 field lj 2 0012 0005 0003 field 3 4 0013 0005 0006 field Gy 3 0014 0006 even Here is an example of a system prompt and a command that you might enter C esr a user ti simuboard utilities In syntax descriptions the instruction command or directive is in a bold typeface font and parameters are in an italic typeface Portions of a syntax that are in bold should be entered as shown portions of a syntax that are in italics describe the type of information that should be entered Here is an example of a directive syntax asect section name address asect is the directive This directive has two parameters ind
14. L B18 sTS GND IM P B CFRAME ats sTS GND ps P Emp jm Jo e CC m je qp pee ps T Emm m ae here imm e o fe e Ts Note The voltage sense terminals VS1 CVS1 VS2 CVS2 are always driven low except under the following conditions 1 High impedance state during RESET 2 Toggle during socket interrogation C 4 PCI445X Buffer Types Table C 1 PCI445X Terminal Function paa and Buffer Types Continued ao fin fe GC a s wo foe po po a b p ean np wo je mme fm mx mw pe je p E es je p m fm E armen m qe e Tee armen m fe e 18 arme je EC e Te armen fee fe es e m ws es em fen m qe fe ee Ten mm me qe er CN Ul Ul Ul Uy U U Vi VDI U U U VI U DI U vu PCI445X Buffer Types C 5 PCI445X Buffer Types Table C 1 PCI445X Terminal Function Assignment and Buffer Types Continued C 6 PCI445X Buffer Types Table C 2 Buffer Type Abbreviations Buffer Type Description 1 0 Standard input output Standard input only O Standard output only OD Open drain P Power GND or clamp rail STS Sustained 3 state bidirectional An active low signal must be driven high for one cycle before deasserting TS 3 state bidirectional TSO 3 state output only PCI445X Buffer Types C 7 C 8
15. System Consideration ccc eee tees 1 21 1 5 Important Information 00 0 ccc I A a E E 1 22 1 5 1 G_RST Clamping Ral lt a a Tog 00 1 22 15 2 PME RI OUT Bit Definition u een en 1 22 1 5 3 Serialized IRQ Data Streams cresi tiressi arici nanio tees 1 22 1 5 4 Socket Power Control 00 0 cece eee ees 1 22 1 5 5 External CLOCK Frequency for P2C Interface cece eee 1 22 vii Contents A viii Global Reset Only Bits PME Context Bits 0ooooocooorronn eee A 1 A 1 Global Reset Only Bits PME Context Bits 000s A 2 PME and RI Behavior nin tnnt ns A nga Rd Nen een a Rn B 1 Bt PME and Ri Behavior wcccccsaccceeceen ae uai aeaa da ern ees B 2 PCI445X Buffer Types oooccocccncccc eee eee C 1 CA PCI445X Buffer Types coco chase a na ana ana C 2 OND a oL db o k k Figures Typical System Architecture r K R r R K r eee n 1 2 Serialized Interrupt Signal 0 00 cece ocn 1 5 EEPROM 2 Wire Interface 0 000 N Kar R tenes 1 10 TPS22X6 Power Switch Interface K K ete nennen nn nn 1 14 Example of a ZV Interface ia ete nh 1 14 Distributed DMA Signal Connection 00 006 c cee eee 1 16 G RST and Vccp Relationship sees e a e 0 e e 6 R 0 e 6 eee 1 22 Tables Registers and Bits Loadable Through Serial EEPROM cece eeee 1 11 PC Card Interface Pullup Register SL 1 16 PCI Bus Interface Pullup Register List 0 cec
16. X Device 1 5 System Features Selection 1 1 12 3 Asynchronous CSC Interrupt Generation The ASYNC_CSC bit diagnostic register PCI offset 93h bit 0 controls the CSC interrupt signaling method If this bit is set to 0 then CSC is generated synchronously to PCLK recommended By default this bit is set to 1 which is the asynchronous mode 1 1 12 4 CardBus Reserved Terminal Signaling The CardBus interface has reserved terminals Usually the CardBus controller drives these terminals low If the CBRSVD bit system control register PCI offset 80h bit 22 is set to 0 then the CardBus reserved terminal signals are in a high impedance state when a CardBus card is inserted in the socket 1 1 12 5 Memory Burst R W Operation Control Memory read bursting is controlled via the MRBURSTDN bit system control register PCI offset 80h bit 15 for downstream burst transactions PCI to PC Card and the MRBURSTUP bit system control register PCI offset 80h bit 14 for upstream burst transactions PC Card to PCl Memory write bursting is controlled via the POSTEN bit bridge control register PCI offset 3Eh bit 10 This bit enables write posting if disabled No write data can be accepted including burst writes until any previous write data has been forwardedto its destination By default write posting and upstream read bursts are disabled 1 1 12 6 Power Savings Mode The PCI445X device has a proprietary power saving mode It can be disabled
17. cp or GND GPIO3 GPIOO MFUNC7 LOCK N C or used as output Vocp CLOCK Internal OSC is selected GND LATCH If MFUNC7 is used for IDSEL GND RI_OUT PME KEEN System dependent Note Removing clamping voltage makes all the clamped signals low PCI445X Device 1 17 System Implementation Table 1 5 Required Pullup Pulldown Resistors Signal Recommended Condition Value Q LPS Pulldown Default 1 0k Required Note All pullup pulldown resistor value recommendations are provided as guidelines only The best value for an individual design varies depending upon board characteristics standard design rules and practices etc System Implementation 1 4 BIOS Considerations 1 4 1 Initialization This section explains which registers require initialization but does not discuss detailed information about the registers themselves Refer to the corresponding specifications Reference white paper htip www microsoft com hwdev busbios cardbus 1 htm 1 4 1 1 PCI Standard Registers Initialization Lj Command register PCI offset 04h 16 bit Set to 0007h enables bus master control memory space control and I O space control Cache line size register PCI offset OCh 8 bit Set to 08h It is dependent on host to PCl bridge specification It enables memory read line and memory read multiple command Latency timer PCI offset ODh 8 bit This register should reflect each PC Card requirement but Windows does not d
18. e eee tees 1 17 Miscellaneous Terminals Pullup Register List 000 cece eee eee eee 1 17 Required Pullup Pulldown Resistors 000 e cece cece eee teen eens 1 18 Global Reset Only Cleared Bits 0000 eet eens A 2 PME Context Bits Tn 2 san ea iaai need hn A 3 CardBus CTSCHG and Wake Up Signals Truth Tapie 0 0000 seen B 2 16 Bit Card RI STSCHG and Wake Up Signals Truth Table 2 B 2 PCI445X Terminal Function Assignment and Buffer Types eres C 2 Buffer Type Abbreviations 00 c cece eee RH C 7 Chapter 1 PCI445X Device This implementation guide assists platform hardware developers designing with the PCI445X dual socket PC card and 1394 open host controller interface OHCI link layer controller LLC The PCI445X designation refers to any device in the PCI445X family for example the PCI4450 or PCI4451 device The document includes an overview of the PCI445X function and features terminal assignments and pinout illustrations PCI445X lO electrical characteristics identification of required passive components and recommendations for system implementation and PHY Link interface signal isolation considerations Advantages of the PCI445X device Y G_RST Section 1 1 2 Internal ring oscillator Section 1 3 1 L Zoomed video auto detect function Sections 1 1 4 1 3 2 I Integrated IEEE1394 OHCI link layer controller Topic Page T SystemiEeatures Selectiong 7 ii 1
19. escribes signal connection for each interface PCI bus PC card interface I2C interface P2C interface ZV interface interrupt interface parallel and serial miscellaneous signals and the PHY Link interface It also explains pullup pulldown resistor requirements 1 2 1 Clamping Rails The PCI445X device has three clamping rails VccA Voce and Vecp Veca and Vccg are not power supplies for PC cards After a card is powered up the supply voltage to the card is fed back into the VccA or Vecp input to the controller This provides the controller a clamping level for signals to the card Technically the power switch controlling VccA is also supplying power to the card via this signal but actually Vaca is not a signal via which the controller supplies power to the card The PCI445X device only drives out a maximum signal of 3 3 V due to the 3 3 V core This is not a problem as 3 3 V is still seen as a logic 1 to a 5 V system LY VccA and Vccp PC Card interface clamping rails CD1 CD2 VS1 VS2 and STSCHG RI are not clamped because these terminals should be able to signal without Veca VccB O VccP PCI bus interface clamping rail It includes the MFUNC7 LOCK MFUNC7 MFUNCO IRQSER GRST and P2C terminals It excludes INTA INTB INTC and PME Note The PME RI_OUT terminal uses an open drain OD buffer ss 1 2 2 PCI Bus Interface PCLK AD31 ADO C BE3 C BEO PAR DEVSEL FRAME STOP TRDY IRDY GNT REQ
20. ffset 80h bit 5 EEPROM may be required for docking systems and is required for add in cards The EEPROM interface terminals SDA and SCL are PCI445X Device 1 3 System Features Selection automatically assigned on the dedicated SDA and SCL terminals A pullup resistor typically 10 kQ must be added on SDA and SCL when using an EEPROM The value of the pullup resistor can vary for different EEPROMs Refer to the EEPROM data sheet or contact the manufacturer for the recommended pullup resistor value 1 1 6 PCI and ISA Style Interrupt The PCI445X device provides three modes of interrupt signaling Parallel PCI interrupts only Y Parallel PCI interrupts and serialized ISA interrupts Serialized PCI interrupts and serialized ISA interrupts Three PCI interrupts INTA INTB and INTC may be used and signaled in either the parallel mode using the MFUNC terminals or in the serial mode The number of PCI interrupts may be reduced by setting the INTRTIE bit system control register PCI offset 80h bit 29 which allows both the CardBus functions function 0 and function 1 to report and use INTA or by setting the TIEALL bit system control register PCI offset 80h bit 28 which allows all 3 functions both CardBus OHCI to report and use INTA 1 1 7 Socket Power Switches The PCI445X device supports TPS2206 and TPS2216 power switches Refer to the detailed explanation on each data sheet The interface between the power switch and
21. h 32 bit Set to 0000 03E1h 16 bit mode and set to 0000 0001 CardBus mode in response to a disable call Power management capabilities register PCI offset A2h 16 bit If the system does not support Vaux in D3cojg state then clear bit 15 Power management control status register PCI offset A4h 16 bit Clear bit 15 by writing a 1 This should be done after all the other initialization for the PCI445X device is finished Make sure that the PCI445X device is in the DO state especially after reboot 1 4 1 2 PCI TI Proprietary Registers Initialization The registers listed below should be set up according to system requirements Refer to Section 1 1 12 L L U C oo C O System control register PCI offset 80h 32 bit Multimedia control register PCI offset 84h 8 bit GPIOS GPIOO control registers PCI offset 88h 8Bh 8 bit Multifunction routing register PCI offset 8Ch 32 bit Card control register PCI offset 91h 8 bit Device control register PCI offset 92h 8 bit Diagnostic register PCI offset 93h 8 bit DMA socket register 0 and 1 PCI offset 94h 98h 32 bit GPE control status register PCI offset A8h 16 bit ExCA identification and revision ExCA offset 800h 8 bit Socket power management register CardBus socket registers offset 20h 32 bit 1 4 2 System Sleeping State Consideration Supporting sleeping states such as SUSPEND STANDBY and HIBERNATION are important for a notebook PC en
22. here is no support in the OS for the PME type wake events of the 1394 peripherals at this time A 2 Table A 2 PME Context Bits Global Reset Only Bits PME Context Bits Register Name Space Offset Bit Bridge control PCI 3Eh 6 Power management capabilities PCI A2h 15 Power management control status PCI A4h 15 8 ExCA power control ExCA 802h 842h 4 3 1 0 ExCA interrupt and general control ExCA 803h 843h 6 ExCA card status change ExCA 804h 844h 3 2 1 0 ExCA card status change interrupt ExCA 805h 845h 3 2 1 0 CardBus socket event CardBus 00h 3 2 1 0 CardBus socket mask CardBus 04h 3 2 1 0 CardBus socket status CardBus 10h 6 5 4 2 1 0 asserted Global Reset Only Bits PME Context Bits 4 Global reset only bits are cleared to default value only when G_RST is Gg PME context bits are not cleared to default value by PRST ifthe PME EN bit is setto 1 Both G RST and PRST can be gated by asserting the SUSPEND signal A 3 A 4 Appendix B PME and RI Behavior This appendix clarifies PME and RI signal behavior These signals are important to support the wake up event from a PC Card CardBus and 16 bit cards Topic Page B 1 PME and RI Behavior B 2 B 1 B 1 PME and RI Behavior Table B 1 CardBus CTSCHG and Wake Up Signals Truth Table RINGEN RIMUX RIENB PME_EN PME_STAT RI_OUT PME
23. icated by section name and address When you use asect the first parameter must be an actual section name enclosed in double quotes the second parameter must be an address Square brackets and identify an optional parameter If you use an optional parameter you specify the information within the brackets you don t enter the brackets themselves Here s an example of an instruction that has an optional parameter LALK 16 bit constant shift The LALK instruction has two parameters The first parameter 16 bit constant is required The second parameter shift is optional As this syntax shows if you use the optional second parameter you must precede it with a comma Square brackets are also used as part of the pathname specification for VMS pathnames in this case the brackets are actually part of the path name they are not optional Braces and indicate alist The symbol read as or separates items within the list Here s an example of a list e qp oe gp ex This provides three choices or Unless the list is enclosed in square brackets you must choose one item from the list Some directives can have a varying number of parameters For example the byte directive can have up to 100 parameters The syntax for this directive is byte value values Trademarks This syntax shows that byte must have at least one value parameter but you have the option of supplying additional
24. intain context in a low power state see Table A 1 and Table A 2 If the system does not support a wake up event from D3 state hot or cold then these terminals can be tied together 1 1 3 PME and RI Signaling 1 1 4 ZV Support For supporting a wake up event a power management event PME and or an RI signal should be signaled to the system PME is available only on the RI_OUT PME terminal RI_OUT is available on RI_OUT PME or MFUNC7 PME and RI_OUT signals are usually connected to the south bridge or embedded controller EC Detailed PME and RI signal behavior is explained later The PCI445X device has internal zoomed video ZV buffers It can support three ZV sources from two PC cards and one external source Refer to the detailed implementation guide in Section 1 3 2 The PCI445X device has the ZV autodetect function for supporting a third external zoomed video source ZVSTAT and ZVPCLK are required to support the third source The ZV autodetect function needs ZVPCLK for input and ZVSTAT for enabling ZVSTAT can be assigned on the MFUNCO MFUNC1 or MFUNC4 terminal 1 1 5 EEPROM for Subsystem Vendor and Subsystem ID Registers Subsystem vendor ID and subsystem ID registers PCI offsets 40h and 42h can be loaded from EEPROM through a two wire serial interface These registers can be configured by BIOS if the PCI445X device is implemented on the motherboard by setting the SUBSYSRW bit system control register PCI o
25. ion 1 1 12 1 Serialized Interrupt Control Serialized interrupt signaling is described below Figure 1 2 Serialized Interrupt Signal START Frame IRQO n IRQS IRQ4 IRQS IRQS IRQ7 IRs IRQ10 IRQI IRdi2 IRQSER LT dips NGHE md P Ter l J L J La LJ Lud Lud La La L J IRQ13 IRQ14 IRQ15IOCHCK INTA INTB INTC INTD STOP Frame The start frame width may vary from four to eight PCI clock cycles The STOP frame width is two clock cycles for quiet mode and three clock cycles for continuous mode Default mode is continuous mode for all slave devices and a host device PIIX4 does not support IRQO IRQ8 and IRQ13 The PCI445X can generate serial IRQ frames for ISA and PCI interrupts Below are related registers and their definitions 1 INTMODE bits device control register PCI offset 92h bits 2 1 Select interrupt mode Y SER STEP bits system control register PCI offset 80h bits 31 30 Change PCI interrupt data frame serial interrupts only I INTRTIE bit system control register PCI offset 80h bit 29 Tie CardBus PCl interrupts to INTA TIEALL bit system control register PCI offset 80h bit 28 Tie all PCI interrupts internally Refer to the Serialized IRQ Support for PCI Systems specification revision 6 0 1 1 12 2 CSC Interrupt Routing for Windows Compatibility The CSC interrupt routing control bit diagnostic register PCI offset 93h bit 5 should be set to 1 default to keep Windows compatibility PCI445
26. ith other devices Parallel PCI Interrupt See Section 1 2 2 PCI Bus Interface 1 3 4 Miscellaneous Signals 1 3 4 1 SUSPEND The SUSPEND signal gates the PRST and G_RST signals from the PCI445X device SUSPEND also gates PCLK inside the PCI445X device in order to minimize power consumption Gating PCLK makes the IRQSER state machine stop until SUSPEND is deasserted Two requirements for implementing suspend mode are that the PCI bus must not be parked on the PCI445X device and IRQSER signaling is not proceeding when SUSPEND is asserted 1 3 4 2 RI OUT and PME 1 3 4 3 1 3 4 4 1 3 4 5 SPKROUT Activity LEDs RI OUT can be programmed on the RI_OUT PME or MFUNCT7 terminal PME can be programmed only on the RI OUT PME terminal To support both RI OUT and PME in a system the RI OUT PME terminal must be programmed as PME These signals are usually connected to the south bridge ex PIIX4 or an embedded controller EC Buffers of the RI OUT PME type are open drain therefore a pullup resistor is required on this terminal SPKROUT is a dedicated terminal and it is usually mixed to PC sound and connected to a sound device Activity LEDs can be programmed on MFUNC terminals These signals are active high and driven for 64 ms duration Distributed DMA DDMA The PCI445X device supports both PC PCI centralized DMA and a distributed DMA slave engine for 16 bit PC Card DMA support PCI445X Device 1 15 Syste
27. ki TEXAS INSTRUMENTS PC1445X PC Card and 1394 OHCI Link Controller Implementation Guide August 2000 PCI Bus Solutions SCPUO007 IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using TI components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any licen
28. ll come from the chipset If the system does not support wake up from D3 o1d then PRST and G RST can be tied together Note that G_RST and PRST are clamped to VCCP O INTA INTB and INTC When using one ofthe parallel PCI interrupt modes INTA INTB and INTC should be connected to the PCI interrupt lines If the INTRTIE bit system control register PCI offset 80h bit 29 is set then both CardBus functions functions 0 and 1 will signal and report INTA and only INTA and INTC will need to be routed If the TIEALL bit system control register PCI offset 80h bit 28 is set then all functions 0 1 and 2 will report INTA and INTA will be the only interrupt required a CLKRUN This signal is optional However if saving power is a concern this signal should be implemented Refer to the PCI Mobile Design Guide Revision 1 1 Section 2 jj PME This signal is required for the ACPI systems In a notebook PC this signal is usually connected to the south bridge ex PIIX4 or embedded controller EC The PME terminal uses an open drain type buffer Note Pullup Resistor Requirements A pullup resistor is required for each of the following terminals IRDY TRDY FRAME STOP DEVSEL PERR SERR LOCK PRST G RST INTA INTB INTC CLKRUN and PME Le PCI445X Device 1 9 System Implementation 1 2 3 PC Card Interface The PC Card interface has two modes the 16 bit interface mode and the
29. m Implementation Figure 1 6 Distributed DMA Signal Connection PCI445X PCGNT Bridge ex PIIX4 1 3 5 Requirement of Pullup Pulldown Resistors Note The PCI445X device has integrated pullup resistors and does not require external pullups a oo e Table 1 2 PC Card Interface Pullup Resistor Listt Terminal Name Terminal Name Terminal Name 16 bit Memory PC Card 16 bit I O PC Card CardBus PC Card Pull Up to Voltage A20 A20 CSTOP Vcca or VccB A21 A21 CDEVSEL Veca or VccB A22 A22 Veca or VccB READY IREQ CINT VCCA Or VccB A15 A15 CIRDY Veca or Voce WP IOIS16 CCLKRUN Veca or VccB t The PCI445X device has integrated pullup resistors and does not require external pullups t CFRAME needs a pullup resistor but it should be implemented on each PC Card System Implementation Table 1 3 PCI Bus Interface Pullup Resistor List PCI Signal Pull Up Voltage FRAME Vocp TRDY CLKRUN Vocp Vocp PRST Vocp G_RST Vocp PME System dependent The pullup pulldown on MFUNC depends on how it is implemented Some signals may require pullups others pulldowns and for a GPI or GPO only the system designer would know how that line should be pulled Table 1 4 Miscellaneous Terminals Pullup Resistor List PCI Signal Required Situation Pullup Pulldown Voltage MFUNC7 MFUNCA NIC or used as output Vocp or GND MFUNC3 MFUNCO N C or used as output Vc
30. n a pulldown resistor is required on the CLOCK terminal If arranging for D3 wake implementation then connect the power switch RESET terminal to GRST Figure 1 4 TPS22X6 Power Switch Interface SLOT A VccA VccB PCI445X TPS22X6 gt Pulldown on CLOCK AAN Ti 1 3 2 Zoomed Video ZV Interface The PCI445X device has an internally buffered and selectable ZV interface It supports three ZV sources two from PC Cards and one from an external source An auto ZV detect function provides software independent ZV switching The auto ZV detect function senses the pixel clocks arbitrates three inputs and selects one of them according to priority bits Figure 1 5 Example of a ZV Interface 3rd ZV Source ZVPCLK ZVSTAT Graphic Controller PCI445X Stereo Sound Controller 1 3 3 System Implementation If the third ZV source is not implemented ZVPCLK and ZVSTAT are not required To support ZV audio an audio codec device is required for L and R sound decoding Interrupt Signaling Interface Serialized Interrupt Interface The serialized interrupt ISA and PCI interface is a single line interface IRQSER A pullup resistor is required on this terminal The signal is synchronous to PCLK so PCLK is a required signal Please remember that SUSPEND gates PCLK internally Usually this signal is connected to the south bridge ex PIIX4 The IRQSER signal is sharable w
31. o so Therefore system imlementers should determine the value A detailed description of this register is in the PC Local Bus Interface Specification Typical setting for this register is 40h CardBus socket registers ExCA base address PCI offset 10h 32 bit It should be set to 0000 0000h default CardBus latency timer register PCI offset 1Bh 8 bit Setup of this register is not required because the CardBus bus is a single device bus and the PCI445X device does not deassert CGNT until a transaction is finished It does not mean that the PCI445X device continues the transaction The PCI445X device would terminate and disconnect or abort the transaction as required Memory and I O windows PCI offset 1Ch 3Fh All memory and I O windows should be closed set to base gt limit Interrupt line register PCI offset 3Ch 8 bit This register is set to FFh default Subsystem vendor ID and subsystem ID registers PCI offsets 40h and 42h 16 bit 16 bit These registers can be set through EEPROM or BIOS These registers are read only as default Before writing to the registers the SUBSYSRW bit system control register PCI offset 80h bit 5 should be set to 1 After setting up the registers the SUBSYSRW bit should be set 0 to protect PCI445X Device 1 19 System Implementation against unexpected overwriting The values are system and vendor dependent PC Card 16 bit I F legacy mode base address register PCI offset 44
32. se either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used TTS publication of information regarding any third party s products or services does not constitute TTS approval warranty or endorsement thereof Copyright 2000 Texas Instruments Incorporated About This Manual Preface Read This First This manual is intended to assist the designer who is attempting to implement a solution using the PCI4450 or PCI4451 Much but not all of the information contained herein can also be found elsewhere However the smaller size of this manual as well as its organization by topics of primary interest to the hardware designer make it a much more usable source regarding those problems most likely to be encountered in the design process How to Use This Manual This document contains the following chapters Chapter 1 PCI445X Device provides the designer with information and examples beyond that contained in the data manuals which will be useful for implementing solutions using the PCI4450 or PCI4451 Appendix A Global Reset Only Bits PME Context Bits contains tabular listings of those register bits that can only be cleared by a global reset and of those register bits used in conjunction with power management events Appendix B PM
33. source is the 32 768 kHz real time clock RTC 1 22 Appendix A Global Reset Only Bits PME Context Bits Topic Page A 1 Global Reset Only Bits PME Context Bits A 2 A 1 Global Reset Only Bits PME Context Bits A 1 Global Reset Only Bits PME Context Bits Table A 1 Global Reset Only Cleared Bits Register Name Space Offset Bit Subsystem IDs PCI 40h 31 0 PC card 16 bit legacy mode base address PCI 44h 31 1 System control PCI 80h 31 29 27 24 22 14 6 3 1 0 Multimedia control PCI 84h 7 0 General status PCI 85h 2 0 GPIOO control PCI 88h 7 6 4 3 1 0 GPIO1 control PCI 89h 7 6 3 1 0 GPIO2 control PCI 8Ah 7 6 4 3 1 0 GPI03 control PCI 8Bh 7 6 3 1 0 MFUNC routing PCI 8Ch 31 0 Retry status PCI 90h 7 1 Card control PCI 91h 7 6 2 1 0 Device control PCI 92h 7 0 Diagnostic PCI 93h 7 0 Socket DMA register O PCI 94h 1 0 Socket DMA register 1 PCI 98h 15 0 GPE control status PCI A8h 10 9 8 2 1 0 Note The following link registers are reset by global reset only a a a a a a PCI subsystem identification register PCl offset 2Ch MIN GNT and MAX LAT register PCI offset 3Eh PCI OHCI control register PCI offset 40h Power management control and status register PCI offset 48h PCI miscellaneous and configuration register PCl offset FOh Link enhancement control register PCI offset F4h However t
34. the PCIA45X device is serialized so an external or internal clock source is required By default an external power switch clock is assumed but this can be changed to use the oscillator internal to the PCI445X device by setting P2CCLK bit system control register PCI offset 80h bit 27 1 1 8 Distributed DMA DDMA Most of the systems do not use this function This function needs PCGNT and PCREQ signals PCGNT can be assigned to the MFUNC2 or MFUNC3 terminal PCREQ can be assigned to the MFUNCO MFUNCA or MFUNC7 terminal See Section 1 3 4 5 Distributed DMA 1 1 9 Optional PCI Signals 1 1 9 1 CLKRUN CLKRUN is the primary method for power reduction on the PCI bus Most of the notebook PCs implement CLKRUN The PCI445X device has a dedicated CLKRUN terminal If it is not used then a pulldown resistor is required to prevent oscillations on this input 1 1 9 2 LOCK This signal can be assigned on the MFUNC1 MFUNC3 or MFUNCT7 terminal System Features Selection 1 1 10 Socket Activity LEDs Socket activity signals can be assigned on MFUNCA slot 1 MFUNCS slot 2 MFUNC5 OHCI LED MFUNC6 OHCI_LED and MFUNC7 OHCI LED 1 1 11 MFUNC7 MFUNCO Terminal Assignments After selecting required functions for the system multifunction terminals MFUNC7 MFUNCO are ready to be assigned Texas Instruments offers Windows based software named TIROUTE EXE to assist with terminal assignment 1 1 12 Miscellaneous Functions Descript
35. value parameters separated by commas Related Documentation From Texas Instruments FCC Warning Trademarks PCI4450 GFN GJG PC Card and OHCI Controller Data Sheet SCPS046 PC14451 GFN GJG PC Card and OHCI Controller Data Manual SCPS054 OHCI Lynx Configuration Information Application Report SLLAO77 PHY Layout Recommendations Application Report SLLAO20A TSB41LVO3A Data Sheet SLLS364 http www ti com sc 1394 http www ti com sc docs apps analog 1394 physical layer controllers html This equipment is intended for use in a laboratory test environment only It generates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other environments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to correct this interference MicroStar BGA is a trademark of Texas Instruments Tl is a trademark of Texas Instruments Windows is a registered trademark of Microsoft Corporation Windows 95 Windows vi Contents 1 PCl445X Device iii nun eee ee eee eee a ann ale 1 1 1 1 System Features Selection 0 eee eee 1 3 14 41 Package Types ocius an ee a date 1 3 1 1 2 BSI
36. vironment The following describes the sleeping state in APM systems 1 1 20 SUSPEND Reset signals G_RST and PRST are gated while SUSPEND is asserted Power consumption of the PCI445X device is low if SUSPEND is asserted System Implementation 2 Register save restore Register content is not preserved in the sleeping state it depends on the system implementation Therefore BIOS should restore the register content Under Windows98 most of the register content is saved and restored by the pci vxd and cbss vxd 3 Troubleshooting tips for sleep resume issues Symptoms of sleep resume issues are B System hung up during resume m PC Card does not work after resume m PC Card is not recognized after resume The probable reason for these problems is that the register content is not preserved correctly Checking the register content before taking the system to the sleep mode and after resuming from the sleep mode may shed some light If some of the register settings are not the same after resuming from the sleep mode then the BIOS most likely did not restore those values 1 4 3 Docking System Consideration Subsystem IDs can be assigned as long as the SUBSYSRW bit system control register PCI offset 80h bit 5 is set It is better to do this from EEPROM as no driver will be running to set the SSID up after a hot dock warm dock Therefore the IDs should be loaded through the 12C interface using an EEPROM PCI445X Device 1 21
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