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Texas Instruments PCI7421 User's Manual

1. 0c cee eee ete eens 1500 V Operating free air temperature Ta 0 eee tenes 0 C to 70 C Storage temperature Tange Tergriiarin arar a A RR 65 C to 150 C Virtual junction temperature Tj 2 3 na waah BRA BITS A ta DENG sale op NG NG 150 C T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTES 1 Applies for external input and bidirectional buffers Vj gt Vcc does not apply to fail safe terminals PCI terminals and miscellaneous terminals are measured with respect to Vccp instead of Vcc PC Card terminals are measured with respect to CardBus Vcc The limit specified applies for a dc condition 2 Applies for external output and bidirectional buffers Vo gt Vcc does not apply to fail safe terminals PCI terminals and miscellaneous terminals are measured with respect to Vccp instead of Vcc PC Card terminals are measured with respect to CardBus Vcc The limit specified applies for a dc condition 14 2 Recommended Operating Conditions see Note 3 VR_PORT see Table 2 4 for description AVDD VDPLL_15 VDPLL_33 VCCP PCI and miscellaneous I O clamp voltage VCCA PC Card I O clamp voltage VCCB PC
2. GLOBAL SWAP When bit 0 is set to 1 all quadlets read from and written to the PCI interface are byte swapped big endian The default value for this bit is O which is little endian mode 7 18 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked list capability item and provides a pointer to the next capability item See Table 7 15 for a complete description of the register contents Bit 5 14 13 12 11 10 9 8 7 te 5 4 3 2 1 Name Capability ID and next item pointer Type R R R R R R Default 0 0 0 0 0 0 Register Capability ID and next item pointer Offset 44h Type Read only Default 0001h Table 7 15 Capability ID and Next Item Pointer Registers Description BIT FIELD NAME TYPE DESCRIPTION Next item pointer The PCI7x21 PCI7x11 controller supports only one additional capability that is 15 8 NEXT ITEM communicated to the system through the extended capabilities list therefore this field returns 00h when read Capability identification This field returns 01h when read which is the unique ID assigned by the PCI SIG for PCI power management capability 7 0 CAPABILITY_ID R 7 19 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the PCI7x21 PCI7x11 controller related to PCI power management See Table 7 16 for a complete description of the register contents
3. OANOOOAHRWDND O ng mb ak 0 N 2 14 2 15 2 16 N N N hb bh mb O CO Y DO AND OK OWN O P mb mob ow N 3 14 3 15 3 16 3 17 List of Tables Title Page Terms and Definitions 2 lt c2inscvdseuedegsesedasetieeedewonecs suede 1 7 Signal Names by GHK Terminal Number 00000e eee ee 2 5 CardBus PC Card Signal Names Sorted Alphabetically 2 9 16 Bit PC Card Signal Names Sorted Alphabetically 2 11 Power Supply TStMiNdlS cdc2sntet tient evened ented dt 2 14 PC Card Power Switch Terminals cece eee eee eee 2 15 PCI System Terminals sp mka KPA NAK AL eles HUAN ENNA KEAN 2 15 PCI Address and Data Terminals 000 cece eee eee 2 16 PCI Interface Control Termihalgi aaah KPA PATA DAA AD 2 17 Multifunction and Miscellaneous Terminals a 2 18 16 Bit PC Card Address and Data Terminals aa 2 19 16 Bit PC Card Interface Control TerminalS 0 oo 2 20 CardBus PC Card Interface System Terminals 2 22 CardBus PC Card Address and Data Terminals 2 23 CardBus PC Card Interface Control Terminals 2 24 IEEE 1394 Physical Layer Terminals 7 44pa asawa pa waa pee coe AGANE 2 26 SD MMC Terminals ar meee Saxe eee ea Ries ex 2 27 Memory Stick PRO Terminals Xem 28 4eeeeed seh ide 2 27 Smart Media XD Terminals 0000 eee eee t
4. 11 11 11 18 Power Management Control and Status Register 11 12 11 19 Power Management Bridge Support Extension Register 11 12 11 20 Power Management Data Register eee ee 11 13 11 21 General Control Register 22 204 iced ted ci id ic 11 13 11 22 Subsystem Access Register eee eee eee 11 14 11 23 Diagnostic Register ahaha nki er NANO vik BNG ved seams 11 15 12 SD Host Controller Programming Model o oooooomommoo 12 1 12 1 Nendarbhegister iecerei sietan eet bd beeen 12 2 12 2 Device ID Regist cues iia air a ty oxese 2s 12 2 12 3 Command Register eii ra eii 12 3 124 Status Register annae 12 4 12 5 Class Code and Revision ID Register o ooooooo 12 5 12 6 Latency Timer and Class Cache Line Size Register 12 6 12 7 Header Type and BIST Register a 12 6 12 8 SD Host Base Address Register la 12 7 12 9 Subsystem Vendor Identification Register 12 7 12 10 Subsystem Identification Register 0 cee eee eee ee 12 8 12 11 Capabilities Pointer Register a 12 8 12 12 Interrupt Line Register a2c ccrickseeieeticei teres ebtedeseiee es 12 8 1213 Interrupt Pin Register 22 2 ads ea aid 12 9 12 14 Minimum Grant Register 0 c cece eee 12 9 12 15 Maximum Latency Register aaa 12 10 Section Title Page 12 16 Slot Informati
5. 4 1 Command Register Description 0 00 cee eee eee eee 4 4 Status Register Description 2000600000 8090 058589007042 G4 00 4 5 Secondary Status Register Description oooococcooccooooo 4 9 Interrupt Pin Register Cross Reference coococcoocccooo coo 4 15 Bridge Control Register Description 0 0 cee eee eee 4 15 System Control Register Description oooooooommoooo 4 18 General Control Register Description 0 00 eee 4 22 General Purpose Event Status Register Description 4 23 General Purpose Event Enable Register Description 4 24 General Purpose Input Register Description 4 24 General Purpose Output Register Description 4 25 Multifunction Routing Status Register Description 4 26 Retry Status Register Description a 4 27 Card Control Register Description 4 nasaan 0 BGM AA DAGA KSE 4 28 Device Control Register Description aa 4 29 Diagnostic Register Description oooooooooorrommmmoo 4 30 Power Management Capabilities Register Description 4 32 Power Management Control Status Register Description 4 33 Power Management Control Status Bridge Support Extensions Register PESCNpUDN ostra tii de a gs ksi dant ais 4 34 Serial Bus Data Register Description 00 cece eee eee 4 35 Serial Bus
6. CardBus Socket Registers Functions 0 and1 Socket Event Register ii seis Ama ak KA eek dene a eas Socket Mask Register oooococcoocccccorr eee Socket Present State Register cece eee eee Socket Force Event Register cece eee eee Socket Control Register ssc apa kad GAAN DBA ida obio Socket Power Management Register ooooooccooooo Section Title Page 7 OHCI Controller Programming Model 2 00eee cece eee eeee 7 1 7 1 Vendor ID Register c i cece ces nananana anaa 7 2 7 2 Device ID Registers oras erre ESPOIRS guess 7 2 7 3 Command Register e consorcios rra pi PG GNG 7 3 7 4 Status REgISte ra ek kd KANG kde Endara 7 4 7 5 Class Code and Revision ID Register oooocooccocooo 7 5 7 6 Latency Timer and Class Cache Line Size Register 7 5 7 7 Header Type and BIST Register 0c eee eee eee 7 6 7 8 OHCI Base Address Register 0a 7 6 7 9 TI Extension Base Address Register 7 7 7 10 CardBus CIS Base Address Register 7 8 7 11 CardBus CIS Pointer Register a 7 8 7 12 Subsystem Identification Register o ooooooomomooo 7 9 7 13 Power Management Capabilities Pointer Register 7 9 7 14 Interrupt Line Register 2220hcceseesseeeeuegesiges equbeskea aes 7 10 7 15 Interr pt PI Register 4m K ERA NG AKA AD ria
7. Register Latency timer and class cache line size Offset OCh Type Read Write Default 0000h Table 12 5 Latency Timer and Class Cache Line Size Register Description FIELD NAME TYPE DESCRIPTION LATENCY_TIMER PCI latency timer The value in this register specifies the latency timer for the SD host controller in units of PCI clock cycles When the SD host controller is a PCI bus initiator and asserts FRAME the latency timer begins counting from zero If the latency timer expires before the SD host transaction has terminated then the SD host controller terminates the transaction when its GNT is deasserted 7 0 CACHELINE_SZ RW Cache line size This value is used by the SD host controller during memory write and invalidate memory read line and memory read multiple transactions 12 7 Header Type and BIST Register The header type and built in self test BIST register indicates the SD host controller PCI header type and no built in self test See Table 12 6 for a complete description of the register contents js 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o0 Header type and BIST Name we R7 R R RIR R R R R R RIR R R R R petam o o o fo fo fo fo fo r oflofolojololo Register Header type and BIST Offset OEh Type Read only Default 0080h Table 12 6 Header Type and BIST Register Description FIELD NAME DESCRIPTION BIST Built in self test The SD host controller does not include a BIST therefore
8. Cycle master capable IEEE 1394 bus management field Must be valid when bit 17 linkEnable in the host controller control register at OHCI offset 50h 54h see Section 8 16 is set to 1 The default value for this bit is O 2 i Isochronous support capable IEEE 1394 bus management field Must be valid when bit 17 linkEnable in the host controller control register at OHCI offset 50h 54h see Section 8 16 is set to 1 The default value for this bit is 0 2 Bus manager capable IEEE 1394 bus management field Must be valid when bit 17 linkEnable in the host controller control register at OHCI offset 50h 54h see Section 8 16 is set to 1 The default value for this bit is 0 Power management capable IEEE 1394 bus management field When bit 27 is set to 1 this indicates that the node is power management capable Must be valid when bit 17 linkEnable in the host controller control register at OHCI offset 50h 54h see Section 8 16 is set to 1 The default value for this bit is O 26 24 RSVD R Reserved Bits 26 24 return Os when read 23 16 cyc clk acc Cycle master clock accuracy in parts per million IEEE 1394 bus management field Must be valid when IT 1 0 9 8 7 bit 17 linkEnable in the host controller control register at OHCI offset 50h 54h see Section 8 16 is set to 1 The default value for this field is 00h 15 124 max rec Maximum request IEEE 1394 bus management field Hardware initializes this field to in
9. cece eee eee 6 1 6 2 Socket Event Register Description a 6 2 6 3 Socket Mask Register Description aa 6 3 6 4 Socket Present State Register Description 6 4 6 5 Socket Force Event Register Description aa 6 6 6 6 Socket Control Register Description aaa 6 7 6 7 Socket Power Management Register Description 6 8 7 1 Function 2 Configuration Register Map cece ee eae 7 1 7 2 Command Register Description 20 c eee eee ee eee 7 3 7 3 Status Register Description s2escrrcsisiteriaiaria dai bs 7 4 7 4 Class Code and Revision ID Register Description 7 5 7 5 Latency Timer and Class Cache Line Size Register Description 7 5 7 6 Header Type and BIST Register Description 7 6 7 7 OHCI Base Address Register Description ooooccooococo 7 6 7 8 TI Base Address Register Description eee eee ee 7 7 7 9 CardBus CIS Base Address Register Description 7 8 7 10 Subsystem Identification Register Description 7 9 7 11 Interrupt Line Register Description a 7 10 7 12 PCI Interrupt Pin Register Read Only INTPIN Per Function 7 10 7 13 Minimum Grant and Maximum Latency Register Description 7 11 7 14 OHCI Control Register Description 0 a 7 11 7 15 Capability ID and N
10. 01h INTA 01h INTA 01h INTA 4 25 Bridge Control Register The bridge control register provides control over various PCI7x21 PCI7x11 bridging functions Some bits in this register are global in nature and must be accessed only through function 0 See Table 4 7 for a complete description of the register contents Name Bridge control Tee R R R R R Aw Rw aw Deant o o o o fo fo ft Tt Register Bridge control Offset 3Eh Function 0 1 Type Read only Read Write Default 0340h Table 4 7 Bridge Control Register Description SIGNAL TYPE FUNCTION RSVD These bits return Os when read Write posting enable Enables write posting to and from the CardBus sockets Write posting enables the POSTEN posting of write data on burst cycles Operating with write posting disabled impairs performance on burst cycles Note that burst write data can be posted but various write transactions may not This bit is socket dependent and is not shared between functions O and 1 Memory window 0 type This bit specifies whether or not memory window 0 is prefetchable This bit is socket dependent This bit is encoded as 0 Memory window 0 is nonprefetchable 1 Memory window 0 is prefetchable default Memory window 1 type This bit specifies whether or not memory window 1 is prefetchable This bit is PREFETCH1 RW socket dependent This bit is encoded as 0 Memory window 1 is nonprefetchable 1 Memory w
11. Dean o o o lolol lolololololoflolofoj o Bit 5 4 ts 12 1 10 9 8 7 6 5 4 3 2 1 Socket event Type R R R R R R R R RI RR rR Rwc Rwo Rwo wo 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default 0 Register Socket event Offset CardBus Socket Address 00h Type Read only Read Write to Clear Default 0000 0000h Table 6 2 Socket Event Register Description SIGNAL TYPE FUNCTION RSVD R These bits return Os when read 3t PWREVENT Power cycle This bit is set when the PCI7x21 PCI7x11 controller detects that the PWRCYCLE bit in the socket present state register offset 08h see Section 6 3 has changed This bit is cleared by writing a 1 Specie CCD2 This bit is set when the PCI7x21 PCI7x11 controller detects that the CDETECT field in the socket present state register offset 08h see Section 6 3 has changed This bit is cleared by writing a 1 it CD1EVENT CCD1 This bit is set when the PCI7x21 PCI7x11 controller detects that the CDETECT 1 field in the socket present state register offset 08h see Section 6 3 has changed This bit is cleared by writing a 1 CSTSCHG This bit is set when the CARDSTS field in the socket present state register offset 08h see ot CSTSEVENT Section 6 3 has changed state For CardBus cards this bit is set on the rising edge of the CSTSCHG signal For 16 bit PC Cards this bit is set on both transitions of the CSTSCHG signal This bit is reset by
12. Es els pa lA STA ALEA LA Power management capabilities Type RU R R R R R R R R Default 0 1 1 1 1 1 1 0 0 Register Power management capabilities Offset 46h Type Read Update Read only Default 7E02h Table 7 16 Power Management Capabilities Register Description FIELD NAME DESCRIPTION PME support from D3cold This bit can be set to 1 or cleared to 0 via bit 15 PME D3COLD in the PCI miscellaneous configuration register at offset FOh in the PCI configuration space see Section 7 23 The PCI miscellaneous configuration register is loaded from ROM When this bit is set to 1 it indicates that the PCI7x21 PCI7x11 controller is capable of generating a PME wake event from D3 qjq This bit state is dependent upon the PCI7x21 PCI7x11 Vaux implementation and may be configured by using bit 15 PME_D3COLD in the PCI miscellaneous configuration register see Section 7 23 PME support This 4 bit field indicates the power states from which the PCI7x21 PCI7x11 controller PME_SUPPORT may assert PME This field returns a value of 1111b by default indicating that PME may be asserted from the D3hot D2 D1 and DO power states 10 D2 SUPPORT R D2 support Bit 10 is hardwired to 1 indicating that the PCI7x21 PCI7x11 controller supports the D2 power state 9 D1 SUPPORT R nba Lita Bit 9 is hardwired to 1 indicating that the PCI7x21 PCI7x11 controller supports the D1 Auxiliary current This 3 bit field reports the 3 3 VAUX auxiliary current
13. Figure 6 1 Accessing CardBus Socket Registers Through PCI Memory Table 6 1 CardBus Socket Registers REGISTER NAME OFFSET Socket event t Socket mask t Socket power management t One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled If PME is not enabled then these bits are cleared by the assertion of PRST or GRST One or more bits in this register are cleared only by the assertion of GRST 6 1 6 1 Socket Event Register This register indicates a change in socket status has occurred These bits do not indicate what the change is only that one has occurred Software must read the socket present state register for current status Each bit in this register can be cleared by writing a 1 to that bit The bits in this register can be set to a 1 by software through writing a 1 to the corresponding bit in the socket force event register All bits in this register are cleared by PCI reset They can be immediately set again if when coming out of PC Card reset the bridge finds the status unchanged i e CSTSCHG reasserted or card detect is still true Software needs to clear this register before enabling interrupts If it is not cleared and interrupts are enabled then an unmasked interrupt is generated based on any bit that is set See Table 6 2 for a complete description of the register contents Socket event Name re RIRIRIRIRIRIRI IR R RI IRIR R R R
14. Function 4 of the PCI7611 controller is a PCI based SD host controller that supports MMC SD and SDIO cards This function controls communication with these Flash Media cards through a passive PC Card adapter or through a dedicated Flash Media socket In addition this function is compliant with the SD Host Controller Standard Specification and includes both DMA capabilities and support for SD suspend resume Function 5 of the PCI7611 controller is a PCl based Smart Card controller used for communication with Smart Cards inserted in PC Card adapters Utilizing Smart Card technology from Gemplus this function provides compatibility with many different types of Smart Cards 1 1 4 PC17411 Controller The PC17411 controller is a four function PCI controller compliant with PC Local Bus Specification Revision 2 3 Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard Release 8 1 The PCI7411 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards and supports Smart Card Flash Media 16 bit CardBus or USB custom card interface PC Cards powered at 5 V or 3 3 V as required All card signals are internally buffered to allow hot insertion and removal without external buffering The PCI7411 controller is register compatible with the Intel 82365SL DF ExCA controller The PCI7411 internal data path logic allows the host to access 8 16 and 32 bit cards using fu
15. Read write command Bit 0 indicates the read write command bit presented to the serial bus on byte read and write accesses 04 BOMB El 0 A byte write access is requested to the serial bus interface 1 A byte read access is requested to the serial bus interface These bits are cleared only by the assertion of GRST 4 50 Serial Bus Control Status Register The serial bus control and status register communicates serial bus status information and selects the quick command protocol Bit 5 REQBUSY in this register must be polled during serial bus byte reads to indicate when data is valid in the serial bus data register See Table 4 25 for a complete description of the register contents Bito o o7 d e 5 a a 2 1 o Name Serial bus control status we w R R R w w ro ro petan o o o o 0 o _ o o Register Serial bus control status Offset B3h function 0 Type Read only Read Write Read Clear Default 00h Table 4 25 Serial Bus Control Status Register Description SIGNAL TYPE FUNCTION Protocol select When bit 7 is set the send byte protocol is used on write requests and the receive byte TI PROT SEL RW protocol is used on read commands The word address byte in the serial bus index register see Section 4 48 is not output by the PCI7x21 PCI7x11 controller when bit 7 is set 6 RSVD R Reserved Bit 6 returns 0 when read Requested serial bus access busy Bit 5 indicates t
16. VoD Differential output voltage 56 Q See Figure 14 1 172 265 IpiFF Driver difference current TPA TPA TPB TPB Drivers enabled speed signaling off 1 05t 1 05t Isp209 Common mode speed signaling current TPB TPB S200 speed signaling enabled 4 844 253 mA ISP499 Common mode speed signaling current TPB TPB S400 speed signaling enabled 124t 8 10t mA VoFF Off state differential voltage Drivers disabled See Figure 14 1 T Limits defined as algebraic sum of TPA and TPA driver currents Limits also apply to TPB and TPB algebraic sum of driver currents E Limits defined as absolute limit of each of TPB and TPB driver currents TPAX TPBx 56 Q TPAx TPBx Figure 14 1 Test Load Diagram 14 4 3 Receiver PARAMETER TEST CONDITION MIN TYP MAX UNIT ZID Differential impedance Drivers disabled Zic Common mode impedance Drivers disabled 14 5 14 5 PCI Clock Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free Air Temperature ALTERNATE PARAMETER SYMBOL TEST CONDITIONS UNIT AA e e f a Pule duration wid POr gs i ro Fit Pulse duration width POL pno Aa i su Seuptime POLK ace arendt PRST DL we po poo is MIN 30 11 11 1 1 100 14 6 Switching Characteristics for PHY Port Interface 14 7 Operating Timing and Switching Characteristics of XI e SSCs a 14 8 PCI Timing Requirements Over Recommended Ranges of Supply Vo
17. ae ea e ee ee ee ala a l E o fo joa o n o pa testo__ meso pw san san eo is NA S o em pv son so ee f ps fO n aces m soo eo oe o mwe monos o w SUSPEND SUSPEND y a ACTICIN lt lt ojo NS Ros PRST PRST MFUNC1 Ros AD21 AD21 LC o wo 2 a MFUNC1 o x eo w me o oo w maY gt Uwe Ro ao ADS Cee ao o e Cos am os A05 a AI A IST so m ww ww ews m ww ww Cao IATA NA ESA ees emo O a 2 7 Table 2 1 Signal Names by GHK Terminal Number Continued TERMINAL TERMINAL NUMBER NUMBER R19 AA wel 4o Ao Tor GASTO GASTO wo FRAME FRAME Toa GNT GNT vos PERR__ PERR_ Tos RLOUTPME RLOUTPME vos ams abs mir vss vsspt vio ab ab 18 words wopiias vw av ao ma f fsw Ro ve Ads Ara dos Ra Ra vs Pcaresta Pcarestsa w f Abe Abe vis TPP TPBoP O vos abe o abols o vis tea O TRACP O os abs abs tee TPP vos ee abe o o wi avo avon vos abr abi tate TRAP vor o TROY vis vopiLas VDplL33 pus SERRA SERRA wo ab aber vos abia AD wo coe ce Uto f awo aAbto wa oB CBe3 pout Ts ws osos ura o ado a gt gt uta Pcwresta Pcwresta wo oez
18. ame Default Register Offset Register Offset Register Offset Register Offset Register Offset Type Default ExCA memory window 0 start address E CardBus Socket Address 810h Card A ExCA Offset 10h Card B ExCA Offset 50h ExCA memory window 1 start address low byte CardBus Socket Address 818h Card A ExCA Offset 18h Card B ExCA Offset 58h ExCA memory window 2 start address low byte CardBus Socket Address 820h Card A ExCA Offset 20h Card B ExCA Offset 60h ExCA memory window 3 start address low byte CardBus Socket Address 828h Card A ExCA Offset 28h Card B ExCA Offset 68h ExCA memory window 4 start address low byte CardBus Socket Address 830h Card A ExCA Offset 30h Card B ExCA Offset 70h Read Write 00h 5 15 5 14 ExCA Memory Windows 0 4 Start Address High Byte Registers These registers contain the high nibble of the 16 bit memory window start address for memory windows 0 1 2 3 and 4 The lower 4 bits of these registers correspond to bits A23 A20 of the start address In addition the memory window data width and wait states are set in this register See Table 5 11 for a complete description of the register contents Bit d o 7 e 5 a 3 2 1 o Name ExCA memory windows 0 4 start address high byte Register ExCA memory window 0 start address high byte Offset CardBus Socket Address 811h Card A ExCA Offset 11h Card B ExCA Offset 51h Register ExC
19. 18 INPACK IB_A3 B_CAD24 1 B A2 B CAD26 B_AO A_CAD30 JIA_D9 A_CAD28 A_D8 A_CCLRRUN IA WP A TINT A READY IREQ A CAD22 A CAD19 IA_A4 I A A25 PA CFRAME 1A A23 A_CDEVSEL IA A21 A RSVD A_A18 A_CAD13 IIA TORD A_CAD11 IIA OE A_CAD4 A_D12 B_CAD27 B_DO B_CAUDIO B_BVD2 SPKR B_CVS1 BYST A_CAD27 A DO A_CSTSCHG A_BVD1 STSCHG R1 A CAD26 A_AO A CAD23 IA A3 A GAD21 A CAD18 ALAS AAT ACCIRDY 1A A15 A CGNT WE A_CC BEI A_A8 A_CAD12 NA At A CAD10 IA TEZ A_RSVD A CAD1 A_D14 B CAD31 B_D10 B_CAD29 B D1 B_CCD2 B CD2 B_CSERR BAWAT A CAUDIO A_BVD2 SPKR A_CAD25 AAA VCCA 1A RESET A A24 5 6 7 A CTRDY A_A22 A_CSTOP A_A20 8 9 A_CAD16 1A A17 10 VCCA 11 A CAD9 1A A10 12 A CAD5 A CAD2 A_D11 13 14 B_RSVD 18_D2 15 Figure 2 1 PCI7621 GHK ZHK Package Terminal Diagram B_CAD30 B D9 B CAD28 1B CCLKRUN TA B_WP 16 TOIST6 17 18 19 2 2 TPBIASO ITPBIAS1 SUSPEND PRST VSSPLL PHY_ TEST_ MA XO MFUNC3 MFUNC4 VSSPLL CNA B_CAD1 B_D4 B_CAD2 IB_D11 B_CADO IB_D3 MFUNCO MFUNC5 DEVSEL B_CAD4 IB_D12 B_RSVD 8_D14 B_CAD5 IB_D6 B_CAD6 IB_D
20. 20h Read only Read Write 0000 0000h Table 6 7 Socket Power Management Register Description SIGNAL TYPE FUNCTION Reserved These bits return Os when read SKTACCES SKTMODE R RSVD R CLKCTRLEN Socket access status This bit provides information on whether a socket access has occurred This bit is cleared by a read access 0 No PC Card access has occurred default 1 PC Card has been accessed Socket mode status This bit provides clock mode information 0 Normal clock operation 1 Clock frequency has changed These bits return Os when read CardBus clock control enable This bit when set enables clock control according to bit 0 CLKCTRL 0 Clock control disabled default 1 Clock control enabled CLKCTRL RW These bits return Os when read CardBus clock control This bit determines whether the CardBus CLKRUN protocol attempts to stop or slow the CardBus clock during idle states The CLKCTRLEN bit enables this bit 0 Allows the CardBus CLKRUN protocol to attempt to stop the CardBus clock default 1 Allows the CardBus CLKRUN protocol to attempt to slow the CardBus clock by a factor of 16 This bit is cleared only by the assertion of GRST 6 8 7 OHCI Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21 PCI7x11 1394 open host controller interface All registers are detailed in the same format a brie
21. 3 1 Power Supply Sequencing The PC17x21 PC17x11 controller contains 3 3 V I O buffers with 5 V tolerance requiring a core power supply and clamp voltages The core power supply is always 1 5 V The clamp voltages can be either 3 3 V or 5 V depending on the interface The following power up and power down sequences are recommended The power up sequence is 1 2 3 4 Power core 1 5 V Apply the I O voltage Apply the analog voltage Apply the clamp voltage The power down sequence is 1 2 3 4 Remove the clamp voltage Remove the analog voltage Remove the I O voltage Remove power from the core NOTE If the voltage regulator is enabled then steps 2 3 and 4 of the power up sequence and steps 1 2 and 3 of the power down sequence all occur simultaneously 3 2 I O Characteristics The PCI7x21 PCI7x11 controller meets the ac specifications of the PC Card Standard release 8 1 and the PCI Local Bus Specification Figure 3 2 shows a 3 state bidirectional buffer Section 14 2 Recommended Operating Conditions provides the electrical characteristics of the inputs and outputs Tied for Open Drain NO VCCP MT OE b gt Figure 3 2 3 State Bidirectional Buffer 3 3 Clamping Voltages The clamping voltages are set to match whatever external environment the PCI7x21 PCI7x11 controller is interfaced with 3 3 V or 5 V The I O sites can be pulled through a clamping diode to a voltage rail that protects the co
22. A84h clear register Type Read Set Clear Read only Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o0 Default 0000 0000h Table 9 2 Isochronous Receive Digital Video Enhancements Register Description BIT FIELDNAME TYPE DESCRIPTION 31 14 RSVD R Reserved Bits 31 14 return Os when read 13 DV_Branch3 RSC When bit 13 is set to 1 the isochronous receive context 3 synchronizes reception to the DV frame start tag in bufferfill mode if input more b 01b and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place This bit is only interpreted when bit 12 CIP_Strip3 is set to 1 and bit 30 isochHeader in the isochronous receive context control register at OHCI offset 460h 464h see Section 8 44 is cleared to 0 12 CIP_Strip3 RSC When bit 12 is set to 1 the isochronous receive context 3 strips the first two quadlets of payload This bit is only interpreted when bit 30 isochHeader in the isochronous receive context control register at OHCI offset 460h 464h see Section 8 44 is cleared to 0 11 10 RSVD R Reserved Bits 11 and 10 return Os when read DV_Branch2 RSC When bit 9 is set to 1 the isochronous receive context 2 synchronizes reception to the DV frame start tag in bufferfill mode if input more b 01b and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place This bit is only interpreted when bit 8 CIP_Strip2
23. C07 PC Card address 16 bit PC Card address lines A25 is the most significant bit Dm PC Card data 16 bit PC Card data lines D15 is the most significant bit ete ei ww hea ie T These terminals are reserved for the PCI7611 and PCI7411 controllers Table 2 11 16 Bit PC Card Interface Control Terminals External components are not applicable for the 16 bit PC Card interface control terminals If any 16 bit PC Card interface control terminal is unused then the terminal may be left floating SKT A TERMINAL SKT B TERMINALT vo POWER A_BVD1_ STSCHGRI B_BVD1 STSCHG RI protect or battery voltage dead condition of a 16 bit I O PC Card Ring indicate Rl is used by 16 bit modem cards to indicate a ring detection NAME No Battery voltage detect 2 BVD2 is generated by 16 bit memory PC Cards that include batteries BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card Both BVD1 and BVD2 are high when the battery is good When BVD2 is low and BVD1 is high the battery is weak and must be replaced When BVD1 is low the battery is no longer serviceable and the data in the memory PC Card is lost See Section 5 6 ExCA Card Status Change Interrupt Configuration Register for enable bits See Section 5 5 ExCA Card C17 Status Change Register and Section 5 2 ExCA Interface Status Register for the VCCA status bits for this signal VCCB Speaker SPKR is an optiona
24. INTB 10 INTC 11 INTD D3_COLD D3cold PME support This bit sets and clears the D3cold PME support bit in the power management capabilities register RSVD oR Reserved Bit 3 returns 0 when read 21t SM DIS RW SmartMedia disable Setting this bit disables support for SmartMedia cards The flash media controller reports a SmardMedia card as an unsupported card if this bit is set If this bit is set then all of the SM_SUPPORT bits in the socket enumeration register are 0 1f MMC SD DIS RW MMC SD disable Setting this bit disables support for MMC SD cards The flash media controller reports a MMC SD card as an unsupported card if this bit is set If this bit is set then all of the SD_SUPPORT bits in the socket enumeration register are 0 0t MS DIS RW Memory Stick disable Setting this bit disables support for Memory Stick cards The flash media controller reports a Memory Stick card as an unsupported card if this bit is set If this bit is set then all of the MS SUPPORT bits in the socket enumeration register are 0 One or more bits in this register are cleared only by the assertion of GRST 11 13 11 22 Subsystem Access Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 2Ch and 2Eh respectively See Table 11 15 for a complete description of the register contents Default Register Subsystem access Offset 50h Typ
25. Indicates that the seventh bit of the cycle second counter has changed 20 cycleSynch RSCU Indicates that a new isochronous cycle has started Bit 20 is set to 1 when the low order bit of the cycle count toggles 19 phy RSCU Indicates that the PHY layer requests an interrupt through a status transfer 18 regAccessFail RSCU Indicates that a PCI7x21 PCI7x11 register access has failed due to a missing SCLK clock signal from the PHY layer When a register access fails bit 18 is set to 1 before the next register access 17 busReset RSCU Indicates that the PHY layer has entered bus reset mode 16 selflDcomplete RSCU A self ID packet stream has been received It is generated at the end of the bus initialization process Bit 16 is turned off simultaneously when bit 17 busReset is turned on 15 selflDcomplete2 RSCU Secondary indication of the end of a self ID packet stream Bit 15 is set to 1 by the PCI7x21 PCI7x11 controller when it sets bit 16 selflDcomplete and retains the state independent of bit 17 busReset 14 10 RSVD R Reserved Bits 14 10 return Os when read 9 lockRespErr RSCU Indicates that the PCI7x21 PCI7x11 controller sent a lock response for a lock request to a serial bus register but did not receive an ack_complete 8 postedWriteErr RSCU Indicates that a host bus error occurred while the PCI7x21 PCI7x11 controller was trying to write a 1394 write request which had already been given an ack_complete into syste
26. O base registers 0 1 Offset 2Ch 34h Type Read only Read Write Default 0000 000Xh 4 22 CardBus I O Limit Registers 0 1 These registers indicate the upper address of a PCI I O address range They are used by the PCI7x21 PCI7x11 controller to determine when to forward an I O transaction to the CardBus bus and likewise when to forward a CardBus cycle to PCI The lower 16 bits of this register locate the top of the I O window within a 64 Kbyte page and the upper 16 bits are a page register which locates this 64 Kbyte page in 32 bit PCI I O address space Bits 15 2 are read write and allow the I O limit address to be located anywhere in the 64 Kbyte page indicated by bits 31 16 of the appropriate I O base register on doubleword boundaries Bits 31 16 are read only and always return Os when read The page is set in the I O base register Bits 15 2 are read write and bits 1 0 are read only returning 00 or 01 when read depending on the value of bit 12 IO LIMIT SEL in the general control register PCI offset 86h see Section 4 31 Writes to read only bits have no effect These I O windows are enabled when either the I O base register or the I O limit register is nonzero By default the I O windows are not enabled to pass the first doubleword of I O to CardBus Either the I O base register or the I O limit register must be nonzero to enable any I O transactions Bt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1
27. Power management control status CSR 3 8 9 3 Flash Media Function 3 Power Management The PCI Bus Power Management Interface Specification is applicable for the flash media dedicated sockets This function supports the DO and D3 power states Table 3 17 Function 3 Power Management Registers REGISTER NAME 0 Power management capabilities Next item pointer Capability ID Power management control status register bridge support extensions Power management control status CSR 48h 3 8 9 4 SD Host Function 4 Power Management The PCI Bus Power Management Interface Specification is applicable for the SD host dedicated sockets This function supports the DO and D3 power states Table 3 18 Function 4 Power Management Registers REGISTER NAME OFFSET Power management capabilities Next item pointer Capability ID Power management control status register bridge support extensions Power management control status CSR 3 8 9 5 Smart Card Function 5 Power Management The PCI Bus Power Management Interface Specification is applicable for the Smart Card dedicated sockets This function supports the DO and D3 power states Table 3 19 Function 5 Power Management Registers REGISTER NAME OFFSET Power management capabilities Next item pointer Capability ID Power management control status register bridge support extensions _Power management control status CSR 3 8 10 CardBus Bridge Power Management The PCI Bus Power Management
28. Reserved This bit returns 0 when read A write has no effect TEST RW TI test bit Write only 0 to this bit 10 IRQ serialized interrupts and parallel PCI interrupts INTA INTB INTC and INTD 11 IRQ and PCI serialized interrupts default RSVD RW Reserved Bit 0 is reserved for test purposes Only a 0 must be written to this bit This bit is cleared only by the assertion of GRST These bits are global in nature and must be accessed only through function 0 Interrupt mode These bits select the interrupt signaling mode The interrupt mode bits are encoded 00 Parallel PCI interrupts only 2 118 INTMODE 01 Reserved RW RW RW RW RW RW 4 29 4 40 Diagnostic Register The diagnostic register is provided for internal TI test purposes It is a read write register but only Os must be written to it See Table 4 18 for a complete description of the register contents pit o 7 d e 5 4 3 2 1 o0 Name PO Diagnostic OE Diagnostic yee w a w w w w w w Detaut o 1 7 o0 o o o0 o Register Diagnostic Offset 93h functions 0 1 Type Read Write Default 60h Table 4 18 Diagnostic Register Description SIGNAL TYPE FUNCTION This bit defaults to 0 This bit is encoded as 738 TRUE_VAL RW 0 Reads true values in PCI vendor ID and PCI device ID registers default 1 Returns all 1s to reads from the PCI vendor ID and PCI device ID registers RSVD R Reserve
29. See Table 12 16 for a complete description of the register contents The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at Function 4 PCI offsets 2Ch and 2Eh respectively See Table 12 16 for a complete description of the register contents 3 4 8 Function 5 Smart Card Subsystem Identification The subsystem identification register is used for system and option card identification purposes This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset 50h in the PCI configuration space see Section 13 23 Subsystem ID Alias Register See Table 13 14 for a complete description of the register contents The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at Function 5 PCI offsets 2Ch and 2Eh respectively See Table 13 14 for a complete description of the register contents 3 5 PC Card Applications The PCI7x21 PCI7x11 controller supports all the PC Card features and applications as described below Card insertion removal and recognition per the PC Card Standard release 8 1 Speaker and audio applications LED socket activity indicators PC Card controller programming model CardBus socket registers 3 5 1 PC Card Insertion Removal and Recognition The PC Card Standard release 8 1 addresses the card detection and recognition process through an interrogation proced
30. The PCI Bus Power Management Interface Specification for PCI to CardBus Bridges establishes the infrastructure required to let the operating system control the power of PCI functions This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus The PCI bus and the PCI functions can be assigned one of seven power management states resulting in varying levels of power savings The seven power management states of PCI functions are e DO uninitialized Before controller configuration controller not fully functional e D0 active Fully functional state e D1 Low power state e D2 Low power state e D3hot Low power state Transition state before D3cold e D3cold PME signal generation capable Main power is removed and VAUX is available e D3 ff No power and completely nonfunctional 1 In the DO uninitialized state the PCI7x21 PCI7x11 controller does not generate PME and or interrupts When bits 0 IO_EN and 1 MEM EN of the command register PCI offset 04h see Section 4 4 are both set the PCI7x21 PCI7x11 controller switches the state to DO active Transition from D3 ojg to the DO uninitialized state happens at the deassertion of PRST The assertion of GRST forces the controller to the DO uninitialized state immediately NOTE 2 The PWR_STATE bits bits 1 0 of the power management control status register PCI offset A4h see Section 4 44 only code for four power states DO D1
31. therefore bit 7 is hardwired to 0 Reserved Bit 6 returns O when read 66 MHz capable The Smart Card controller operates at a maximum PCLK frequency of 33 MHz therefore bit 5 is hardwired to 0 Capabilities list Bit 4 returns 1 when read indicating that the Smart Card controller supports additional PCI capabilities The linked list of PCI power management capabilities is implemented in this function Interrupt status This bit reflects the interrupt status of the function Only when bit 10 INT_DISABLE in the command register see Section 11 3 is a O and this bit is 1 is the function s INTx signal asserted Setting the INT DISABLE bit to 1 has no effect on the state of this bit This bit is set only when a valid interrupt condition exists This bit is not set when an interrupt condition exists and signaling of that event is not enabled INT_STAT mi o a ee oo T N o TI 2 0 RSVD Reserved Bits 3 0 return Os when read 13 4 13 5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class subclass and programming interface of the function The base class is 07h identifying the controller as a communication device The subclass is 80h identifying the function as other mass storage controller and the programming interface is 00h Furthermore the TI chip revision is indicated in the least significant byte 00h See Table 13 4 for a complete descriptio
32. y DY Note When flash media SD host priority is selected there must be a two level priority scheme with the first level being a round robin between the flash media and SD host functions and the second level being a round robin between the CardBus and 1394 functions These bits are cleared only by the assertion of GRST tot 12V sw sEL 9 8 FM_IF_SEL DISABLE_SC DISABLE_SD DISABLE_FM DISABLE_SKTB w AJAJ Hi Ww WU Ww Ww Ww Ww Ww RW RW RW RW Ww Ww RW 4 22 4 32 General Purpose Event Status Register The general purpose event status register contains status bits that are set when general events occur and can be programmed to generate general purpose event signaling through GPE See Table 4 10 for a complete description of the register contents 4 3 General purpose event status Register General purpose event status Offset 88h Type Read Clear Update Read only Default 00h Table 4 10 General Purpose Event Status Register Description SIGNAL TYPE FUNCTION PWR STS Power change status This bit is set when software changes the Vcc or Vpp power state of either socket 6 VPP12 STS 12 V Vpp request status This bit is set when software has changed the requested Vpp level to or from 12 V for either socket RSVD Reserved This bit returns O when read A write has no effect GPI4 status This bit is set on a change in status of the MFUNC5 terminal input level if configured as a
33. 10 Memory read multiple 11 Reserved behavior reverts to default y b m bt RSVD RSVD Bit 4 defaults to 0 which provides OHCI Lynx compatible target abort signaling When this bit is set to 1 it enables the no target abort mode in which the PCI7x21 PCI7x11 controller returns indeterminate data instead of signaling target abort 4t DIS_TGT_ABT RW The PCI7x21 PCI7x11 LLC is divided into the PCLK and SCLK domains If software tries to access Reserved Bits 7 6 return Os when read Reserved Bit 5 returns 0 when read registers in the link that are not active because the SCLK is disabled then a target abort is issued by the link On some systems this can cause a problem resulting in a fatal system error Enabling this bit allows the link to respond to these types of requests by returning FFh It is recommended that this bit be cleared to 0 GP2IIC When bit 3 is set to 1 the GPIO3 and GPIO2 signals are internally routed to the SCL and SDA respectively The GPIO3 and GPIO2 terminals are also placed in the high impedance state DISABLE When bit 2 is set to 1 the internal SCLK runs identically with the chip input This is a test feature only SCLKGATE and must be cleared to 0 all applications Table 7 20 PCI Miscellaneous Configuration Register Description Continued FIELD NAME DESCRIPTION DISABLE When bit 1 is set to 1 the internal PCI clock runs identically with the chip input This is a test feature
34. 18_A3 B_CREQ B_INPACK B_CAD22 IB_A4 B_CAD26 IB_AO B CAD24 IB_A2 VCCB A_CAD30 A_D9 A_CAD28 A_D8 A_CINT A_READY TREO A_CAD22 A_A4 A_CAD19 A CFRAME A_A25 A_A23 HA A21 AODEVSEL A RSVD A_A18 A_CAD13 IIA TORD A_CAD11 I A OE A_CAD4 A_D12 B_CAD27 B_DO B CAUDIO B_BVD2 B_CAD25 A CAD27 A_DO 1A CSTSCHG A_BVD1 STSCHG RI ACSERR KNAIT A_CAD26 JA AO A CAD23 IA A3 A CAD21 1A A5 A CAD18 A CIRDY NAA IA A15 ACCGNT JAWE la_CC BET IA_A8 A_CAD12 NA A11 A CAD10 JIA CE2 A RSVD HA D14 A CAD1 B CAD31 B CAD29 B Dio B D1 B_CSERR B_WAIT A CAUDIO A_BVD2 A_CVS1 IA NST SPKR A_CAD25 1A A1 VCCA 5 A CRS A RESET 6 A_CAD17 A_CTRDY NA A24 IA A22 7 8 A_A20 9 A_CSTOP A_CAD16 JIA A17 VCCA 10 11 A CAD9 IA A10 12 A CAD5 13 A CAD2 A_D11 14 B RSVD B CAD30 1B D2 B Do 15 16 Figure 2 2 PCI7421 GHK ZHK Package Terminal Diagram B_CAD28 B_D8 17 5_CCLKRUN NB_WP 101516 18 19 TPBON TPAON TPBOP TPAOP AGND TPBIASO PBIAS1 ISUSPEND PCO TEST1 VSSPLL PHY_ TEST_ MA MFUNC3 MFUNC4 TESTO VSSPLL MFUNCO MFUNC5 DEVSEL SCL MFUNC1 SC_
35. 21 20 19 18 17 16 CSR compare Type R R R R R R R R R R R R R R R R Default X X X X X X X X X X X X X X X X CSR compare mo RAR TR A ERROR ORAR AAA RIERA REA ae AAA AAA AA AA ATA TA TA TA AS Register CSR compare Offset 10h Type Read only Default XXXX XXXXh Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 fo 8 6 CSR Control Register The CSR control register accesses the bus management CSR registers from the host through compare swap operations This register controls the compare swap operation and selects the CSR resource See Table 8 5 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name CSR control ps RU B Ro RR RR eR e Re oe e RA Default 1 o o o o o o o o o o o o o o o er s u ws e n o s e 7 eo s aToT T To Name CSR control Type R rR R R R R rR r r rR R ARA RO Rw rw Dean o o o o o o po o jo o po o o o Register CSR control Offset 14h Type Read Write Read Update Read only Default 8000 000Xh Table 8 5 CSR Control Register Description FIELD NAME TYPE DESCRIPTION csrDone Bit 31 is set to 1 by the PCI7x21 PCI7x11 controller when a compare swap operation is complete It is cleared whenever this register is written RSVD Reserved Bits 30 2 return Os when read csrSel This field selects the C
36. 8 34 Isochronous Cycle Timer Register ee eeeeee 8 31 8 35 Asynchronous Request Filter High Register 8 32 8 36 Asynchronous Request Filter Low Register 8 34 8 37 Physical Request Filter High Register o oooocococcoooo 8 35 8 38 Physical Request Filter Low Register 8 37 8 39 Physical Upper Bound Register Optional Register 8 37 8 40 Asynchronous Context Control Register 8 38 8 41 Asynchronous Context Command Pointer Register 8 39 8 42 Isochronous Transmit Context Control Register 8 40 8 43 Isochronous Transmit Context Command Pointer Register 8 41 8 44 Isochronous Receive Context Control Register 8 41 8 45 Isochronous Receive Context Command Pointer Register 8 43 8 46 BIsochronous Receive Context Match Register 8 44 TI Extension Registers sx cc RKB NENA KAN PK ALABANG 9 1 9 1 DV and MPEG2 Timestamp Enhancements 9 1 9 2 Isochronous Receive Digital Video Enhancements 9 2 9 3 Isochronous Receive Digital Video Enhancements Register 9 2 9 4 Link Enhancement Register 002 c eee eee eens 9 4 9 5 Timestamp Offset Register 72 47 maa aaa ca Naka KANG 9 5 PHY Register Configuration eee eee eee eee eee 10 1 10 1 JBase RegisterS sssstaapr tipica id edt 10 1 10 2
37. Default 0000 0000h Table 9 4 Timestamp Offset Register Description B FIELD NAME TYPE DESCRIPTION RW IT 31 DisablelnitialOffset Bit 31 disables the use of the initial timestamp offset when the MPEG2 enhancements are enabled A value of 0 indicates the use of the initial offset a value of 1 indicates that the initial offset must not be applied to the calculated timestamp This bit has no meaning for the DV timestamp enhancements The default value for this bit is 0 30 25 RSVD R Reserved Bits 30 25 return Os when read CycleCount RW This field adds an offset to the cycle count field in the timestamp when the DV or MPEG2 enhancements are enabled The cycle count field is incremented modulo 8000 therefore values in this field must be limited between O and 7999 The default value for this field is all Os 11 0 CycleOffset RW This field adds an offset to the cycle offset field in the timestamp when the DV or MPEG2 enhancements are enabled The cycle offset field is incremented modulo 3072 therefore values in this field must be limited between O and 3071 The default value for this field is all Os 9 5 9 6 10 PHY Register Configuration There are 16 accessible internal registers in the PCI7x21 PCI7x11 controller The configuration of the registers at addresses Oh through 7h the base registers is fixed whereas the configuration of the registers at addresses 8h through Fh the paged registers is dependent u
38. GRA STS Reu general purpose input GP14 GP3 STS GPI3 status This bit is set on a change in status of the MFUNC4 terminal input level if configured as a E general purpose input GPI3 GPI2 status This bit is set on a change in status of the MFUNC2 terminal input level if configured as a general purpose input GPI2 GPI1 status This bit is set on a change in status of the MFUNC1 terminal input level if configured as a general purpose input GPI1 GPIO status This bit is set on a change in status of the MFUNCO terminal input level if configured as a GP0O STS j general purpose input GPIO GP2_STS GP1_STS RCU RCU RCU RCU RCU RCU RCU This bit is cleared only by the assertion of GRST 4 23 4 33 General Purpose Event Enable Register The general purpose event enable register contains bits that are set to enable GPE signals See Table 4 11 for a complete description of the register contents Name General purpose event enable Type RW Default 0 Register General purpose event enable Offset 89h Type Read only Read Write Default 00h Table 4 11 General Purpose Event Enable Register Description BIT SIGNAL TYPE FUNCTION T PWR_EN RW Power change GPE enable When this bit is set GPE is signaled on PWR_STS events RW 12 V Vpp GPE enable When this bit is set GPE is signaled on VPP12 STS events R Reserved This bit returns 0 when read A write has no effect RW GP1I4 GPE enable When thi
39. If PME is not enabled then these bits are cleared by the assertion of PRST or GRST 6 4 Socket Force Event Register This register is used to force changes to the socket event register offset 00h see Section 6 1 and the socket present state register offset 08h see Section 6 3 The CVSTEST bit bit 14 in this register must be written when forcing changes that require card interrogation See Table 6 5 for a complete description of the register contents Register Socket force event Offset CardBus Socket Address OCh Type Read only Write only Default 0000 XXXXh 6 5 Table 6 5 Socket Force Event Register Description TYPE FUNCTION Reserved These bits return 0s when read BIT SIGNAL 31 15 RSVD Card VS test When this bit is set the PCI7x21 PCI7x11 controller reinterrogates the PC Card updates 14 the socket present state register offset 08h see Section 6 3 and re enables the socket power control CVSTEST W Force YV card Writes to this bit cause the YVCARD bit in the socket present state register offset 08h see Section 6 3 to be written When set this bit disables the socket power control 3 FYVCARD Force XV card Writes to this bit cause the XVCARD bit in the socket present state register offset 08h see Section 6 3 to be written When set this bit disables the socket power control FXVCARD Force 3 V card Writes to this bit cause the 3VCARD bit in the socket present
40. If PME is not enabled then PRST acts the same as a normal PCI reset Please see the master list of PME context bits in Section 3 8 12 e Power source in D3 oig if wake up support is required from this state Since Vcc is removed in D3 jg an auxiliary power source must be supplied to the PCI7x21 PCI7x11 Voc terminals Consult the PC 14xx Implementation Guide for D3 Wake Up or the PCI Power Management Interface Specification for PCI to CardBus Bridges for further information 3 8 11 ACPI Support The Advanced Configuration and Power Interface ACPI Specification provides a mechanism that allows unique pieces of hardware to be described to the ACPI driver The PCI7x21 PCI7x11 controller offers a generic interface that is compliant with ACPI design rules Two doublewords of general purpose ACPI programming bits reside in PCI7x21 PCI7x11 PCI configuration space at offset 88h The programming model is broken into status and control functions In compliance with ACPI the top level event status and enable bits reside in the general purpose event status register PCI offset 88h see Section 4 32 and general purpose event enable register PCI offset 89h see Section 4 33 The status and enable bits are implemented as defined by ACPI and illustrated in Figure 3 16 Status Bit Event Input Enable Bit Event Output Figure 3 16 Block Diagram of a Status Enable Cell The status and enable bits generate an event that allows the ACPI driver to call a
41. Register Smart Card Configuration 2 Offset 54h Type Read only Read Write EEPROM GRST only Default 0000 0000h Table 13 16 Smart Card Configuration 2 Register Description BIT SIGNAL TYPE FUNCTION Power up delay for the PCMCIA socket This register indicates how long the external power switch takes to apply stable power to the PCMCIA socket in ms Software must wait before starting operation after power up This field has no effect for the hardware PWRUP_DELAY_ PCMCIA 15 8 13 17 13 18 14 Electrical Characteristics 14 1 Absolute Maximum Ratings Over Operating Temperature Rangest Supply voltage range VR PORT 2 22 2222 eee eens 0 2V to 2 2 V NB pA adoro bear 0 3V to 4 V NG darte 0 3V to 4 V VDPLL AS ustonidrs parda ria ia 0 5 V to 1 836 V NA cinta asis 0 3V to 4 V VOCI rss AA AA 0 5 V to 5 5 V VOB ria ias e 0 5 V to 5 5 V ele AA eee 0 5 V to 5 5 V SO VOC BV och maana need ad iea one Ra he ADA 0 5 V to 5 5 V Clamping voltage range Vecp Vacas and VCCB 2 0 5Vto6V Input voltage range Vj PCI CardBus PHY SC miscellaneous 0 5 V to Vcc 0 5 V Output voltage range Vo PCI CardBus PHY SC miscellaneous 0 5 V to Vcc 0 5 V Input clamp current lik V lt O or Vj gt Vcc see Note 1 2 eee eee 20 mA Output clamp current lox Vo lt 0 or Vo gt Veco see Note 2 na nn ana naaa naa cna rd 20 mA Human Body Model HBM ESD performance
42. Since socket 3 is not implemented in the controller this bit is a read only 0 6 PME_SUPPORT_SKT2 RW Socket 2 PME support Since socket 2 is not implemented in the controller this bit is a read only 0 5 PME_SUPPORT_SKT1 RW Socket 1 PME support When this bit is set to 1 socket 1 card insertions cause a PME event 4 PME_SUPPORT_SKTO RW Socket 0 PME support When this bit is set to 1 socket 0 card insertions cause a PME event SKT3_EN R Socket 3 enable Since socket 3 is not implemented in the controller this bit is a read only 0 SKT2_EN RW Socket 2 enable Since socket 2 is not implemented in the controller this bit is a read only 0 SKT1_EN RW Socket 1 enable When this bit is set to 1 socket 1 is enabled 0 SKTO_EN RW Socket 0 enable When this bit is set to 1 socket 0 is enabled 13 16 13 26 Smart Card Configuration 2 Register BIOS or EEPROM configure system dependent Smart Card interface information through this register Information of this register can be read from the Smart Card configuration 2 alias in the Smart Card global control register set The software utilizes this information and adjusts the software and firmware behavior if necessary See Table 13 16 for a complete description of the register contents All bits in this register are reset by GRST only o o fo o o o Bit ts 14 13 12 1 109 8 76 59 32 1 o Name Smart Card configuration 2 fo o o o o o o fo o o o ojo jojojo
43. TS aaa Isochronous transmit context control Type RSC R R RSU RU RU RU RU RU RU RU RU RU RU Default 0 0 0 X 0 0 X X X X X X X X TS EA EA e FEE Register Isochronous transmit context control Offset 200h 16 n set register 204h 16 n clear register Type Read Set Clear Update Read Set Clear Read Set Update Read Update Read only Default XXXX XOXXh Table 8 33 Isochronous Transmit Context Control Register Description BIT FIELD NAME TYPE DESCRIPTION cycleMatchEnable RSCU When bit 31 is set to 1 processing occurs such that the packet described by the context first descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field bits 30 16 The cycleMatch field bits 30 16 must match the low order two bits of cycleSeconds and the 13 bit cycleCount field in the cycle start packet that is sent or received immediately before isochronous transmission begins Since the isochronous transmit DMA controller may work ahead the processing of the first descriptor block may begin slightly in advance of the actual cycle in which the first packet is transmitted The effects of this bit however are impacted by the values of other bits in this register and are explained in the 1394 Open Host Controller Interface Specification Once the context has become active hardware clears this bit 30 16 cycleMatch This field contains a 15 bit value corresponding to the low order two bits of
44. When bit 8 is set to 1 the flash media interface SERR driver is enabled SERR can be ii asserted after detecting an address parity error on the PCI bus 7 STEP ENB R Address data stepping control The flash media interface does not support address data stepping therefore bit 7 is hardwired to 0 6 PERR_ENB Parity error enable When bit 6 is set to 1 the flash media interface is enabled to drive PERR response pa to parity errors through the PERR signal 5 VGA ENB R VGA palette snoop enable The flash media interface does not feature VGA palette snooping therefore bit 5 returns O when read 4 MWI_ENB Memory write and invalidate enable The flash media controller does not generate memory write a invalidate transactions therefore bit 4 returns O when read 3 SPECIAL R Special cycle enable The flash media interface does not respond to special cycle transactions therefore bit 3 returns 0 when read 2 MASTER_ENB RW Bus master enable When bit 2 is set to 1 the flash media interface is enabled to initiate cycles on the PCI bus 1 MEMORY ENB RW Memory response enable Setting bit 1 to 1 enables the flash media interface to respond to memory cycles on the PCI bus 0 IO ENB R I O space enable The flash media interface does not implement any l O mapped functionality therefore bit 0 returns 0 when read 11 4 Status Register The status register provides device information to the host system All bit functions a
45. is set to 1 and bit 30 isochHeader in the isochronous receive context control register at OHCI offset 440h 444h see Section 8 44 is cleared to 0 8 CIP_Strip2 RSC When bit 8 is set to 1 the isochronous receive context 2 strips the first two quadlets of payload This bit is only interpreted when bit 30 isochHeader in the isochronous receive context control register at OHCI offset 440h 444h see Section 8 44 is cleared to 0 9 2 Table 9 2 Isochronous Receive Digital Video Enhancements Register Description Continued BIT FIELD NAME TYPE DESCRIPTION 7 6 RSVD Reserved Bits 7 and 6 return Os when read 5 R DV Branch1 RSC When bit 5 is set to 1 the isochronous receive context 1 synchronizes reception to the DV frame start tag in bufferfill mode if input more b 01b and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place This bit is only interpreted when bit 4 CIP Strip1 is set to 1 and bit 30 isochHeader in the isochronous receive context control register at OHCI offset 420h 424h see Section 8 44 is cleared to 0 CIP Strip1 When bit 4 is set to 1 the isochronous receive context 1 strips the first two quadlets of payload This bit is only interpreted when bit 30 isochHeader in the isochronous receive context control register at OHCI offset 420h 424h see Section 8 44 is cleared to 0 Reserved Bits 3 and 2 return Os when read DV Branch0 When bit 1 is set to 1
46. o OFh Reserved nonloadable PCI 82h system control byte 2 10h PCI 83h system control byte 3 bits 7 2 0 11h PCI 8Ch MFUNC routing byte 0 12h PCI 8Dh MFUNC routing byte 1 13h PCI 8Eh MFUNC routing byte 2 14h PCI 8Fh MFUNC routing byte 3 15h PCI 90h retry status bits 7 6 16h PCI 91h card control bit 7 17h PCI 92h device control bits 6 5 3 0 bit O must be programmed to 0 18h PCI 93h diagnostic bits 4 0 19h PCI A2h power management capabilities function O bit 15 bit 7 of EEPROM offset 16h corresponds to bit 15 1Ah PCI A2h power management capabilities function 1 bit 15 bit 7 of EEPROM offset 16h corresponds to bit 15 1Bh CB Socket OCh function O socket force event bit 27 bit 3 of EEPROM offset 17h corresponas to bit 27 1Ch CB Socket OCh function 1 socket force event bit 27 bit 3 of EEPROM offset 18h corresponds to bit 27 1Dh ExCA 00h ExCA identification and revision bits 7 0 PCI 86h general control byte 0 bits 7 0 1Fh PCI 87h general control byte 1 bits 7 6 can only be set to 1 if bits 1 0 01 4 0 20 PCI 89h GPE enable bits 7 6 4 0 h m Table 3 9 EEPROM Loading Map Continued peters BYTE DESCRIPTION 5h PCI 2Ch subsystem vendor ID byte O PCI 2Dh subsystem vendor ID byte 1 PCI 2Eh subsystem ID byte 0 PCI 2Fh subsystem ID byte 1 PCI F4h Link_Enh byte 0 bits 7 2 1 OHCI 50h host controller control bit 23 7 6 2 1 Link Enh HCControl Progra
47. see Section 8 12 configuration ROM header register at OHCI offset 18h see Section 8 7 and bus options register at OHCI offset 20h see Section 8 9 are not updated Software can set this bit only when bit 17 linkEnable is 0 Once bit 31 is set to 1 it can be cleared by a system hardware reset a software reset or if a fetch error occurs when the PCI7x21 PCI7x11 controller loads bus info block registers from host memory noByteSwapData Bit 30 controls whether physical accesses to locations outside the PCI7x21 PCI7x11 controller itself as well as any other DMA data accesses are byte swapped AckTardyEnable Bit 29 controls the acknowledgement of ack tardy When bit 29 is set to 1 ack tardy may be returned as an acknowledgment to accesses from the 1394 bus to the PCI7x21 PC17x11 controller including accesses to the bus info block The PCI7x21 PCI7x11 controller returns ack tardy to all other asynchronous packets addressed to the PCI7x21 PCI7x11 node When the PCI7x21 PCI7x11 controller sends ack tardy bit 27 ack tardy in the interrupt event register at OHCI offset 80h 84h see Section 8 21 is set to 1 to indicate the attempted asynchronous access Software ensures that bit 27 ack tardy in the interrupt event register is 0 Software also unmasks wake up interrupt events such as bit 19 phy and bit 27 ack_tardy in the interrupt event register before placing the PCI7x21 PCI7x11 controller into the D1 power mode Software must n
48. writing a 1 t This bit is cleared only by the assertion of GRST when PME is enabled If PME is not enabled then this bit is cleared by the assertion of PRST or GRST 6 2 6 2 Socket Mask Register This register allows software to control the CardBus card events which generate a status change interrupt The state of these mask bits does not prevent the corresponding bits from reacting in the socket event register offset 00h see Section 6 1 See Table 6 3 for a complete description of the register contents 24 23 Socket mask Register Socket mask Offset CardBus Socket Address 04h Type Read only Read Write Default 0000 0000h Table 6 3 Socket Mask Register Description SIGNAL FUNCTION 31 4 RSVD oR These bits return Os when read Power cycle This bit masks the PWRCYCLE bit in the socket present state register offset 08h see Section 6 3 from causing a status change interrupt 3t PWRMASK 0 PWRCYCLE event does not cause a CSC interrupt default 1 PWRCYCLE event causes a CSC interrupt Card detect mask These bits mask the CDETECT1 and CDETECT2 bits in the socket present state register offset 08h see Section 6 3 from causing a CSC interrupt 21t CDMASK 00 Insertion removal does not cause a CSC interrupt default 01 Reserved undefined 10 Reserved undefined 11 Insertion removal causes a CSC interrupt CSTSCHG mask This bit masks the CARDSTS field in the sock
49. 0010 IRQ2 0110 IRQ6 1010 IRQ10 1110 IRQ14 27 24 MFUNC6 0011 IRQ3 0111 IRQ7 1011 IRQ11 1111 IRQ15 Multifunction terminal 5 configuration These bits control the internal signal mapped to the MFUNC5 terminal as follows 0000 GPI4 0100 SC_DBG_RX 1000 CAUDPWM 1100 LEDA1 23 204 MFUNGS 0001 GPO4 0101 IRQS 1001 IRAQ 1101 LED_SKT 0010 PCGNT 0110 RSVD 1010 FM_LED 1110 GPE 0011 IRQ3 0111 RSVD 1011 OHCI_LED 1111 IRQ15 Multifunction terminal 6 configuration These bits control the internal signal mapped to the MFUNC6 terminal as follows 0000 RSVD 0100 IRQ4 1000 IRQ8 1100 IRQ12 0001 CLKRUN 0101 IRQ5 1001 IRQ9 1101 IRQ13 0010 RSVD 0110 RSVD 1010 INTD 1110 GPE 0011 IRQ3 0111 RSVD 1011 FM_LED 1111 IRQ15 Multifunction terminal 3 configuration These bits control the internal signal mapped to the MFUNC3 terminal as follows 0000 RSVD 0100 IRQ4 1000 IRQ8 1100 IRQ12 0001 IRQSER 0101 IRQ5 1001 IRQ9 1101 IRQ13 Multifunction terminal 4 configuration These bits control the internal signal mapped to the MFUNC4 terminal as follows 19 164 MFUNC4 0000 GPI3 0100 IRQ4 1000 CAUDPWM 1100 RI OUT 15 124 MFUNC3 0010 IRQ2 0110 IRQ6 1010 IRQ10 1110 IRQ14 0011 IRQ3 0111 IRQ7 1011 IRQ11 1111 IRQ15 Multifunction terminal 2 configuration These bits control the internal signal mapped to the MFUNC2 terminal as follows 0000 GPI2 0100 IRQ4 1
50. 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved Table 10 4 Page 0 Port Status Register Field Descriptions FIELD SIZE TYPE DESCRIPTION AStat 2 TPA line state This field indicates the TPA line state of the selected port encoded as follows Code Arb Value 11 10 01 00 invalid BStat 2 TPB line state This field indicates the TPB line state of the selected port This field has the same encoding as the AStat field Ch 1 Child parent status A 1 indicates that the selected port is a child port A O indicates that the selected port is the parent port A disconnected disabled or suspended port is reported as a child port The Ch bit is invalid after a bus reset until tree ID has completed Con 1 Debounced port connection status This bit indicates that the selected port is connected The connection must be stable for the debounce time of approximately 341 ms for the Con bit to be set to 1 The Con bit is cleared to 0 by system hardware reset and is unaffected by bus reset NOTE The Con bit indicates that the port is physically connected to a peer PHY device but the port is not necessarily active Bias 1 Debounced incoming cable bias status A 1 indicates that the selected port is detecting incoming cable bias The incoming cable bias must be stable for the debounce time of 52 us for the Bias bit to be set to 1 Dis 1 RW Port disabled control If the Dis bit is set to 1 the selected port is disabled The Dis bit is cle
51. 13 return Os when read 12 0 InitBWAvailable RW This field is reset to 1333h on a system hardware or software reset and is not affected by a 1394 bus reset The value of this field is loaded into the BANDWIDTH_AVAILABLE CSR register upon a GRST PRST or a 1394 bus reset 8 28 Initial Channels Available High Register The initial channels available high register value is loaded into the corresponding bus management CSR register on a system hardware or software reset See Table 8 20 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Initial channels available bai Type RW EE AE Initial channels available high RW RW RW RW RW RW Register Initial channels available high Offset B4h Type Read Write Default FFFF FFFFh Table 8 20 Initial Channels Available High Register Description BIT FIELD NAME TYPE DESCRIPTION 31 InitChanAvailHi This field is reset to FFFF_FFFFh on a system hardware or software reset and is not affected by a 1394 bus reset The value of this field is loaded into the CHANNELS_AVAILABLE_HI CSR register upon a GRST PRST or a 1394 bus reset 8 29 Initial Channels Available Low Register The initial channels available low register value is loaded into the corresponding bus management CSR register on a system hardware or software reset See Table 8 21 for a complete
52. 2e to bits A19 A12 of the offset address 7 i memory 0 EE offset address low ko mame Default Register Offset Register Offset Register Offset Register Offset Register Offset Type Default ExCA memory window 0 offset address aan CardBus Socket Address 814h Card A ExCA Offset 14h Card B ExCA Offset 54h ExCA memory window 1 offset address low byte CardBus Socket Address 81Ch Card A ExCA Offset 1Ch Card B ExCA Offset 5Ch ExCA memory window 2 offset address low byte CardBus Socket Address 824h Card A ExCA Offset 24h Card B ExCA Offset 64h ExCA memory window 3 offset address low byte CardBus Socket Address 82Ch Card A ExCA Offset 2Ch Card B ExCA Offset 6Ch ExCA memory window 4 offset address low byte CardBus Socket Address 834h Card A ExCA Offset 34h Card B ExCA Offset 74h Read Write 00h 5 19 5 18 ExCA Memory Windows 0 4 Offset Address High Byte Registers These registers contain the high 6 bits of the 16 bit memory window offset address for memory windows 0 1 2 3 and 4 The lower 6 bits of these registers correspond to bits A25 A20 of the offset address In addition the write protection and common attribute memory configurations are set in this register See Table 5 13 for a complete description of the register contents Bit 07 e 5 4 3 2 1 o Name ExCA memory window 0 4 offset address high byte Register ExCA memory
53. 3 8 9 PCI Power Management 22 aaa 3 25 3 8 9 1 CardBus Power Management Functions O ANO T anG ABAKA MERA GANA 3 25 3 8 9 2 OHCI 1394 Function 2 Power Management aa 3 26 3 8 9 3 Flash Media Function 3 Power Management 3 26 3 8 9 4 SD Host Function 4 Power Management aaa 3 26 3 8 9 5 Smart Card Function 5 Power Management 3 26 3 8 10 CardBus Bridge Power Management 3 26 20 1 ACPLOUPPON zuma aba fa0 IBG HKSAR L NA AG EK BAKA Dene oe 3 27 3 8 12 Master List of PME Context Bits and Global Reset Only BUS sp ir are 3 27 IEEE 1394 Application Information ccc eee ee eee 3 30 3 9 1 PHY Port Cable Connection 020005 3 30 3 9 2 Crystal Selection agama KG AG cl sth AK hik 3 31 3 9 3 Bus Reset 4a h aa iaa 3 32 Section Title Page 4 PC Card Controller Programming Model 22 222 4 1 4 1 PCI Configuration Register Map Functions O and 1 4 1 4 2 Vendor ID REQISTE hs 0060500000008 Eo BA NG KG NG a 4 2 4 3 Device ID Register Functions 0 and1 occcccccccoccc o 4 3 4 4 Command Register osre recia cri aida ra 4 4 4 5 Status MEGS uv teas nla ARN TREE DEAN 4 5 4 6 Revision ID Register soi ar perra re rre 4 6 4 7 Class Code Register 2 0 00 cece eee ees 4 6 4 8 Cache Line Size Register ccec napaka sees bade eewt wes 4 6 4 9 Latency Timer Register
54. 70h 74h see Section 8 19 and isochronous receive channel mask low register at OHCI offset 78h 7Ch see Section 8 20 The isochronous channel number specified in the isochronous receive context match register see Section 8 46 is ignored When this bit is cleared the isochronous receive DMA context receives packets for the single channel specified in the isochronous receive context match register see Section 8 46 Only one isochronous receive DMA context may use the isochronous receive channel mask registers see Sections 8 19 and 8 20 If more than one isochronous receive context control register has this bit set then the results are undefined The value of this bit must not be changed while bit 10 active or bit 15 run is set to 1 26 16 dualBufferMode RSC When bit 27 is set to 1 receive packets are separated into first and second payload and streamed independently to the firstBuffer series and secondBuffer series as described in Section 10 2 3 in the 1394 Open Host Controller Interface Specification Also when bit 27 is set to 1 both bits 28 multiChanMode and 31 bufferFill are cleared to O The value of this bit does not change when either bit 10 active or bit 15 run is set to 1 Reserved Bits 26 16 return Os when read 14 13 RSVD RSCU JONES Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software to stop descriptor processing The PCI7x21 PCI7x11 c
55. 8 3 Asynchronous Transmit Retries Register The asynchronous transmit retries register indicates the number of times the PCI7x21 PC17x11 controller attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit See Table 8 4 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Asynchronous transmit retries tee RIRIRIRIRIRI IR R R R R RIRI R R R Dea o o o o fofofoefofofofofofofofo fo me A A A AW AW AW Aw aw pera o o o o o o o o o o o o o o fo jo Register Asynchronous transmit retries Offset 08h Type Read Write Read only Default 0000 0000h Table 8 4 Asynchronous Transmit Retries Register Description BIT FIELD NAME TYPE DESCRIPTION 31 29 secondLimit The second limit field returns Os when read because outbound dual phase retry is not implemented 28 16 cycleLimit The cycle limit field returns Os when read because outbound dual phase retry is not implemented 15 12 Reserved Bits 15 12 return Os when read 11 8 maxPhysRespRetries This field tells the physical response unit how many times to attempt to retry the transmit operation Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o for the response packet when a busy acknowledge or ack data error is received from the target node The default value for this field is Oh 7 4 maxATRe
56. A CAD2 A14 B CAD2 A CAD1 B14 B CAD1 A_CADO E14 B_CADO CardBus bus commands and byte enables CC BE3 CC BEO are multiplexed on the same CardBus terminals During the address A CC BE3 B CC BE3 phase of a CardBus cycle CC BE3 CC BEO define the bus A CC BE2 B CC BE2 command During the data phase this 4 bit bus is used as byte Y oe pS enables The byte enables determine which byte paths of the full I O PCII7 PCIO7 CCA A_CC BE1 B_CC BE1 32 bit data bus carry meaningful data CC BEO applies to byte 0 VCCB A_CC BEO B_CC BEO CAD7 CADO CC BE1 applies to byte 1 CAD15 CAD8 CC BE2 applies to byte 2 CAD23 CAD16 and CC BE3 applies to byte 3 CAD31 CAD24 CardBus parity In all CardBus read and write cycles the controller calculates even parity across the CAD and CC BE buses As an initiator during CardBus cycles the controller outputs CPAR with a vo Ipci7 Pcio7 VECA one CCLK delay As a target during CardBus cycles the controller VECB compares its calculated parity to the parity indicator of the initiator a compare error results in a parity error assertion T These terminals are reserved for the PCI7611 and PCI7411 controllers 2 23 Table 2 14 CardBus PC Card Interface Control Terminals If any CardBus PC Card interface control terminal is unused then the terminal may be left floating SKT A TERMINAL SKT B TERMINALT VO PU POWER NAME NO NAME NO DESCRIPTION TYPE INPUT OUTPUT PD RAIL CardBus audio CAUDIO
57. A_BVD2 SPKR A_CAD25 1A A1 VCCA 5 ACCRST A CAD17 A_RESET A A24 6 7 ALCTRDY IA_A22 A_CSTOP IA_A20 8 9 A_CAD16 1A m17 VCCA 10 11 A CAD9 JIA A10 12 A CAD5 A_D6 13 A_CAD2 A_D11 14 15 Figure 2 3 PCI7611 GHK ZHK Package Terminal Diagram 16 17 18 19 TPAON TPBIASO ITPBIAS1 VSSPLL PHY_ SUSPEND TEST MA MFUNG3 MFUNC4 VSSPLL RSVD MFUNCO MFUNC5 DEVSEL MFUNC1 RSVD CLOCK SPKROUT ix SM_PHYS _WP RSVD RSVD SD DAT3 SD_CMD SD_CLK SD_DAT1 SM_D6 SM_D7 SM_ALE SM_RE SM_D5 VR oa SD DATO pcia b SD_DAT3 V PORT VR_EN SM_DA e CC VCC VCC VCC MS_SDIO E MS DATAZ MS CLK DATA Ari ana T SO paroy SD_DATI SD_ SD_CLK SM_D1 SM D2 SM EL WP A CAD20 A CPAR A_CAD14 A_CC BEO IIA_A6 A_A13 NA A9 I ACET MS Bs MC PWR MS CD D lA_CC BE2 A _CPERRI A_CAD6 _cTRL_1 SD CMD NA A12 A_A14 A_D13 SMWE RSVD SD CD A CCLK A CBLOCK A CAD15 A CAD8 A CAD3 A_CADO Hi MA A16 A_A19 ATOWR A_D15 A D5 A D3 A CAD31 A_RSVD A CAD29 NA DIO0 A D2 WADI A TINT A CAD30 A CAD28 A REABY A CAD22 A CAD19 CFRAME ALCDEVSEL A RSVD A_CAD13 A CAD11 A_CAD7 A CAD4 1A D8 REG A_A4 JA A25 n
58. All outputs are placed in a high impedance state but the contents of the registers are preserved P05 PCI bus clock PCLK provides timing for all transactions on the PCI bus All PCI pcia v signals are sampled at the rising edge of PCLK CCP GRST PCLK PCI bus reset When the PCI bus reset is asserted PRST causes the controller to place all output buffers in a high impedance state and reset some internal registers When PRST is asserted the controller is completely nonfunctional After PRST is PRST deasserted the controller is in a default state PCII3 Vocp When SUSPEND and PRST are asserted the controller is protected from PRST clearing the internal registers All outputs are placed in a high impedance state but the contents of the registers are preserved Table 2 7 PCI Address and Data Terminals Internal pullup pulldown resistors and pin strapping are not applicable for the PCI address and data terminals cs POWER DESCRIPTION ae INPUT OUTPUT RAIL PCI address data bus These signals make up the multiplexed PCI address and data bus on the primary interface During the address phase of a primary bus PCI cycle AD31 ADO contain a 1 0 PCII3 PCIO3 Vecp 32 bit address or other destination information During the data phase AD31 ADO contain data PCl bus commands and byte enables These signals are multiplexed on the same PCI terminals During the address phase of a primary bus PCI cycle C BE3 C BEO define the bus command
59. B USB EN external CBT switch for each socket when an USB LVCO1 CBT switch Float im card is inserted into the socket CLK_48 mo A 48 MHz clock must be connected to this terminal EE LVCI1 Lk ki pee clock kQ to 47 kQ 10 kQ to 47 kQ 10 kQ to 47 kQ Multifunction terminals 0 6 See Section 4 36 10 kQ to 47kQ MFUNC3 P02 Multifunction Routing Status Register tor VO PCII3 PCIO3 a p I pullup resistor configuration details 10 kQ to 47 kQ MFUNC5 Nos vo Pens Pcio3 NG KENO TRN pullup resistor MFUNC6 PCII3 PCIO3 o FARC pullup resistor Reserved This terminal has no connection Float anywhere within the package PHY_TEST_ PHY test pin Not for customer use It must be pulled high with a 4 7 kQ resistor EN ee Ooo el eee SURAT Ring indicate out and power management event RILOUT TO3 output This terminal provides an output for LVCO2 Fulup kasa tor per PME ho soe PCI specification ring indicate or PME signals RSVD 119 Reserved This terminal has no connection Float anywhere within the package Serial clock At PRST the SCL signal is sampled to determine if a two wire serial ROM is present If the serial ROM is detected then this terminal provides Pullup resistor per the serial clock signaling and is implemented as 12C specification Tie to GND if not open drain For normal operation a ROM is VO TTLH TTLO1 value depends on using EEPROM implemented in the design this terminal must be EEPROM 9 pulled high to the ROM Vpp
60. Bit 31 is cleared to 0 by the PCI7x21 PCI7x11 controller when either bit 15 rdReg or bit 14 wrReg is set to 1 This bit is set to 1 when a register transfer is received from the PHY layer 30 28 RSVD 27 24 rdAddr 23 16 rdData rdReg 13 12 RSVD 11 8 regAddr CO CO O CO CIA CICR IC Reserved Bits 30 28 return Os when read This field is the address of the register most recently received from the PHY layer This field is the contents of a PHY register that has been read Bit 15 is set to 1 by software to initiate a read request to a PHY register and is cleared by hardware when the request has been sent Bits 14 wrReg and 15 rdReg must not both be set to 1 simultaneously Bit 14 is set to 1 by software to initiate a write request to a PHY register and is cleared by hardware when the request has been sent Bits 14 wrReg and 15 rdReg must not both be set to 1 simultaneously Reserved Bits 13 and 12 return Os when read This field is the address of the PHY register to be written or read The default value for this field is Oh This field is the data to be written to a PHY register and is ignored for reads The default value for this field is 00h 8 34 Isochronous Cycle Timer Register The isochronous cycle timer register indicates the current cycle number and offset When the PCI7x21 PCI7x11 controller is cycle master this register is transmitted with the cycle start message When the PCI7x21
61. CLKRUN protocol is preparing to stop slow the PCI bus clock 1 The CardBus CLKRUN protocol can only attempt to stop slow the CaredBus clock if the socket has been idle for 8 clocks regardless of the state of the PCI CLKRUN signal Vcc control These bits are used to request card Vcc changes 000 Request power off default 100 Request Vcc X X V 6 41 VCCCTRL 001 Reserved 101 Request Voc Y Y V 010 Request Vcc 5 V 110 Reserved 011 Request Vcc 3 3 V 111 Reserved RSVD This bit returns 0 when read Vpp control These bits are used to request card Vpp changes 000 Request power off default 100 Request Vpp X X V 2 01 VPPCTRL RW 001 Request Vpp 12V 101 Request Vpp Y Y V 010 Request Vpp 5 V 110 Reserved 011 Request Vpp 3 3 V 111 Reserved t One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled If PME is not enabled then this bit is cleared by the assertion of PRST or GRST 6 7 6 6 Socket Power Management Register This register provides power management control over the socket through a mechanism for slowing or stopping the clock on the card interface when the card is idle See Table 6 7 for a complete description of the register contents Default BIT 31 26 25 241 23 17 sk al gt o re ieee Offset Type Default Socket power management CardBus Socket Address
62. Card I O clamp voltage SC_VCC_5V NOTE 3 Unused terminals input or I O must be held high or low to prevent them from floating 14 1 Recommended Operating Conditions continued 3 3 V PCI 3 3 V CardBus High level input PC Card 3 3 V 16 bit voltage 5 V 16 bit PC 0 2 0 7Vcc z SC_DATA SC_FCB SC_RFU 0 6 SC_VCC_5V SC_VCC_5V 3 3 V 0 PCI 3 3 V CardBus vit Low level input PC Card 3 3 V 16 bit E voltage 5 V 16 bit ire t Applies to external inputs and bidirectional buffers without hysteresis Miscellaneous terminals are A03 B17 C15 C18 E05 E08 F19 HO3 JO1 JO2 JO3 JO5 JO6 J07 L02 LO3 LO5 MO1 M02 M03 NO1 NO2 N13 P12 P15 R02 R17 TO1 A CCDx A_CDx A CVSx A VSx B_CCDx B CDx B CVSx B VSx SD DATO SD DAT2 SD DAT3 SD CMD SD CLK SD DAT1 SM CLE SC CD SC OC SC PWR CTRL CLK 48 SDA SCL DATA LATCH TESTO CNA SUSPEND PHY TEST MA and GRST terminals Applies to external output buffers 1 For a node that does not source power see Section 4 2 2 2 in IEEE Std 1394a 2000 These junction temperatures reflect simulation conditions The customer is responsible for verifying junction temperature AMFUNC 0 6 share the same specifications as the PCI terminals a lt lt Q O ojo o 5 Co a lt o ojojo k 14 2 Recommended Operating Conditions continued ns Receive input jitter TPA TPB cable inputs S200 operation S
63. During the data phase this 4 bit bus is used as byte enables The byte enables determine which byte paths of the full 32 bit data bus carry meaningful data C BEO applies to NG ROIS POISS VccP byte O AD7 ADO0 C BE1 applies to byte 1 AD15 AD8 C BE2 applies to byte 2 AD23 AD16 and C BE3 applies to byte 3 AD31 AD24 PCI bus parity In all PCI bus read and write cycles the controller calculates even parity across the AD31 ADO and C BE3 C BEO buses As an initiator during PCI cycles the controller outputs this parity indicator with a one PCLK delay As a target during PCI cycles the controller 1 0 PCII3 PCIO3 compares its calculated parity to the parity indicator of the initiator A compare error results in the assertion of a parity error PERR AA PP SSSS Al gt 2 o PP SSS STS TS SSS Table 2 8 PCI Interface Control Terminals Internal pullup pulldown resistors and pin strapping are not applicable for the PCI interface control terminals TERMINAL POWER EXTERNAL name DESCRIPTION Pia INPUT OUTPUT RAIL COMPONENTS PCI device select The controller asserts DEVSEL to claim a PCI cycle as the target device As a PCI initiator on the bus the controller monitors pcs Pcios v Pullup resistor per DEVSEL until a target responds If no target responds before timeout CCP PCI specification occurs then the controller terminates the cycle with an initiator abort PCII3 PCIOS v Pullup resistor per CCP PCI
64. E CpHy CBD gt is 24 576 MHz e XO C10 Figure 3 20 Load Capacitance for the PCI7x21 PCI7x11 PHY The layout of the crystal portion of the PHY circuit is important for obtaining the correct frequency minimizing noise introduced into the PHY phase lock loop and minimizing any emissions from the circuit The crystal and two load capacitors must be considered as a unit during layout The crystal and the load capacitors must be placed as close as possible to one another while minimizing the loop area created by the combination of the three components Varying the size of the capacitors may help in this Minimizing the loop area minimizes the effect of the resonant current Is that flows in this resonant circuit This layout unit crystal and load capacitors must then be placed as close as possible to the PHY X1 and XO terminals to minimize etch lengths as shown in Figure 3 21 o o X1 Ld For more details on crystal selection see application report SLLA051 available from the TI website http www ti com sc 1394 Figure 3 21 Recommended Crystal and Capacitor Layout 3 9 3 Bus Reset In the PCI7x21 PCI7x11 controller the initiate bus reset IBR bit may be set to 1 in order to initiate a bus reset and initialization sequence The IBR bit is located in PHY register 1 along with the root holdoff bit RHB and Gap Count field as required by IEEE Std 1394a 2000 Therefore whenever the IBR bit is written the RHB and Gap_Cou
65. Interface Specification for PCI to CardBus Bridges was approved by PCMCIA in December of 1997 This specification follows the device and bus state definitions provided in the PC Bus Power Management Interface Specification published by the PCI Special Interest Group SIG The main issue addressed in the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges is wake up from D3hot or D3cold without losing wake up context also called PME context The specific issues addressed by the PCI Bus Power Management Interface Specification for PCI to CardBus Bridges for D3 wake up are as follows e Preservation of device context The specification states that a reset must occur during the transition from D3 to DO Some method to preserve wake up context must be implemented so that the reset does not clear the PME context registers e Power source in D3 jq if wake up support is required from this state The Texas Instruments PCI7x21 PCI7x11 controller addresses these D3 wake up issues in the following manner e Two resets are provided to handle preservation of PME context bits Global reset GRST is used only on the initial boot up of the system after power up It places the PCI7x21 PCI7x11 controller in its default state and requires BIOS to configure the controller before becoming fully functional PCI reset PRST has dual functionality based on whether PME is enabled or not If PME is enabled then PME context is preserved
66. Name SS amay near o o o o o o o Register Maximum latency Offset 3Fh Type Read Update Default 04h Table 12 10 Maximum Latency Register Description FIELD NAME TYPE DESCRIPTION 7 0 MAX LAT RU Maximum latency The contents of this field may be used by host BIOS to assign an arbitration priority level to the SD host controller The default for this register indicates that the SD host controller may need to access the PCI bus as often as every 0 25 us thus an extremely high priority level is requested The contents of this field may also be loaded through the serial EEPROM 12 16 Slot Information Register This read only register contains information on the number of SD sockets implemented and the base address Registers used Slot information Name Slotintormaon we r RR R R R R R Deta o x x x o o o o Register Maximum latency Offset 40h Type Read Update Default XOh Table 12 11 Maximum Latency Register Description B FIELD NAME TYPE DESCRIPTION RSVD R Reserved This bit returns O when read IT 7 6 4 NUMBER SLOTS R Number of slots This field indicates the number of SD sockets supported by the SD host controller Since the controller supports three SD sockets this field returns 010 when read 3 RSVD R Reserved This bit returns O when read 2 0 FIRST BAR R First base address register number This field is hardwired to 000b to indicate that the first BAR u
67. Ob specifies that these windows are nonprefetchable Bits 2 1 00b specify that this memory window can allocate anywhere in the 32 bit address space ex a 00 ala Name naban akes E DD Rw an ela Alala A CU GC GG AA Cu A Sr Care acres me lawlaw A Al Al aAl aAl aAl A A A A AA mern o o o o o o lo l o o o lo lo o leo lo o0 Register Smart Card base address register 1 4 Offset 14h 18h 1Ch and 20h Type Read Write Read only Default 0000 0000h 13 10 Subsystem Vendor Identification Register This register is read update and can be modified through the subsystem vendor ID alias register Default value is 104Ch This default value complies with the WLP Windows Logo Program requirements without BIOS or EEPROM configuration All bits in this register are reset by GRST only Bit 15 14 13 2 m wo 9 e 7 te 5 4 3 2 1 o Subsystem vendor identification RU RU RU RU RU RU RU RU RU RU RU Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0 Register Subsystem vendor identification Offset 2Ch Type Read Update Default 104Ch 13 11 Subsystem Identification Register This register is read update and can be modified through the subsystem ID alias register This register has no effect to the functionality Default value is 8035h This default value complies with the WLP Windows Logo Program requirements without BIOS or EEPROM configuration All bits in this register are re
68. Offset 9Ch Default 0000h 12 16 12 28 Slot 3 3 3 V Maximum Current Register This register is a read write register and the contents of this register are aliased to the 3 3 MAX CURRENT field in the slot 3 maximum current capabilities register at offset 48h in the SD host standard registers This register is a GRST only register If slot 3 is not implemented this register is read only and returns Os when read 7 CO pr E A a name ra menmun onen Lacie ae ee ee Register Slot 3 3 3 V maximum current Type Read Write Offset AOh Default 0000h 12 29 Slot 4 3 3 V Maximum Current Register This register is a read write register and the contents of this register are aliased to the 3 3 MAX CURRENT field in the slot 4 maximum current capabilities register at offset 48h in the SD host standard registers This register is a GRST only register If slot 4 is not implemented this register is read only and returns Os when read 7 DECA CA EC NE KA Name fo o o o o o o o Register Slot 4 3 3 V maximum current Type Read Write Offset A4h Default 0000h 12 30 Slot 5 3 3 V Maximum Current Register This register is a read write register and the contents of this register are aliased to the 3 3 MAX CURRENT field in the slot 5 maximum current capabilities register at offset 48h in the SD host standard registers This register is a GRST only register If slot 5 is not implemented this register is read only
69. Offset 78h Type Read Write Read only Default 00h 5 22 ExCA I O Windows 0 and 1 Offset Address High Byte Registers These registers contain the high byte of the 16 bit I O window offset address for I O windows 0 and 1 The 8 bits of these registers correspond to the upper 8 bits of the offset address 7 ExCA I O windows 0 and 1 offset address high byte Name Type w w w w w w w w petan o0 o o o0 o oo o o Register ExCA I O window 0 offset address high byte Offset CardBus Socket Address 837h Card A ExCA Offset 37h Card B ExCA Offset 77h Register ExCA I O window 1 offset address high byte Offset CardBus Socket Address 839h Card A ExCA Offset 39h Card B ExCA Offset 79h Type Read Write Default 00h 5 23 5 23 ExCA Memory Windows 0 4 Page Registers The upper 8 bits of a 4 byte PCI memory address are compared to the contents of this register when decoding addresses for 16 bit memory windows Each window has its own page register all of which default to 00h By programming this register to a nonzero value host software can locate 16 bit memory windows in any one of 256 16 Mbyte regions in the 4 gigabyte PCI address space These registers are only accessible when the ExCA registers are memory mapped that is these registers may not be accessed using the index data I O scheme 7 Name ExCA memory windows 0 4 page tye AW w w w w w w o Register ExCA memory win
70. Port Status Register 0 cece eee ee 10 4 10 3 Vendor Identification Register a 10 5 Section Title Page 10 4 Vendor Dependent Register cee eee eee eee 10 6 10 5 Power Class Programming 20cc eee cece eee eee 10 7 11 Flash Media Controller Programming Model 11 1 11 1 Vendor ID Register ccc ceec vee vaxerecgianr ens eterea pee 11 2 die Device ID Register sore residir e 11 2 11 3 Command Register i aan cis NGA ARENA LEG KAKA WALA ENGR KNA ENE 11 3 114 Stat s ASUSTE 607908002 n arinn ERE EEEE EEY 11 4 11 5 Class Code and Revision ID Register a a 11 5 11 6 Latency Timer and Class Cache Line Size Register 11 5 11 7 Header Type and BIST Register a 11 6 11 8 Flash Media Base Address Register 11 6 11 9 Subsystem Vendor Identification Register 11 7 11 10 Subsystem Identification Register oooocoooooo 11 7 11 11 Capabilities Pointer Register 20 cece eee eee eee 11 7 11 12 Interrupt Line Register saccusetucow cede rre 11 8 11 13 _Interr pt Pin Register am IA Ah EP praia ad 11 8 11 14 Minimum Grant Register 427 74 xa pw awan NILAGA KANG a KUDA KA 11 9 11 15 Maximum Latency Register aaa 11 9 11 16 Capability ID and Next Item Pointer Registers 11 10 11 17 Power Management Capabilities Register
71. Posted Write Address Low Register o 0ooo ooo o 8 11 8 14 Posted Write Address High Register 0a 8 12 vii viii Section Title Page 10 8 15 Vendor ID Register 0 eee ees 8 12 8 16 Host Controller Control Register eee eee eee 8 13 8 17 Self ID Buffer Pointer Register a 8 14 8 18 Self ID Count Register 2 00 cee eee 8 15 8 19 Isochronous Receive Channel Mask High Register 8 16 8 20 Isochronous Receive Channel Mask Low Register 8 17 B 21 Interrupt Event Register 2a nakaw pa G DAG KA raras 8 18 8 22 Interrupt Mask Register 0 00 c eee eee eee eee eee 8 20 8 23 Isochronous Transmit Interrupt Event Register 8 22 8 24 Isochronous Transmit Interrupt Mask Register 8 23 8 25 Isochronous Receive Interrupt Event Register 8 24 8 26 Isochronous Receive Interrupt Mask Register 8 25 8 27 Initial Bandwidth Available Register aa 8 25 8 28 Initial Channels Available High Register 8 26 8 29 Initial Channels Available Low Register oooooooooo 8 26 8 30 Fairness Control Register soncinsrorsi dr DAGA ANAN PAA 8 27 8 31 Link Control Register evocar ec ai 8 28 8 32 Node Identification Register a 8 29 8 33 PHY Layer Control Register 24scacesecssegaentebegesteeess oad 8 30
72. R pw ew or petam o o of o Poo fojoJfojofojojopfojojpo Register Offset Type Default FIELD NAME RSVD Command 04h Read Write Read only 0000h Table 12 2 Command Register Description TYPE DESCRIPTION Reserved Bits 15 11 return Os when read INT_DISABLE INTx disable When set to 1 this bit disables the function from asserting interrupts on the INTx signals 0 INTx assertion is enabled default 1 INTx assertion is disabled 9 FBB_ENB R Fast back to back enable The SD host controller does not generate fast back to back transactions therefore bit 9 returns 0 when read 8 SERR_ENB RW SERR enable When bit 8 is set to 1 the SD host controller SERR driver is enabled SERR can be asserted after detecting an address parity error on the PCI bus Y STEP_ENB R Address data stepping control The SD host controller does not support address data stepping therefore bit 7 is hardwired to 0 6 PERR_ENB RW Parity error enable When bit 6 is set to 1 the SD host controller is enabled to drive PERR response to parity errors through the PERR signal 5 VGA_ENB R VGA palette snoop enable The SD host controller does not feature VGA palette snooping therefore bit 5 returns O when read 4 MWI ENB RW Memory write and invalidate enable The SD host controller does not generate memory write invalidate transactions therefore bit 4 returns O when read 3 SPECIAL R Special cycle enable The SD host controll
73. RR OR RIR_R IR R _R R R RA R IRIA Den o o o o f fofofofofofofofof fofi Bit 15 14 13 12 9 10 9 8 7 6 5 4 3 2 1 o Class code and revision ID fee R RITR RIR R R R R R RIR RI R R R petam o o o fo fo o fo x txt xt xix xix xx Register Offset Type Default FIELD NAME BASECLASS Class code and revision ID 08h Read only 0805 OXXXh Table 12 4 Class Code and Revision ID Register Description TYPE DESCRIPTION Base class This field returns 08h when read which broadly classifies the function as a generic system peripheral SUBCLASS CHIPREV Subclass This field returns 05h when read which specifically classifies the function as an SD host controller Programming interface If bit 0 DMA_EN in the general control register is 0 then this field returns 00h when read to indicate that the function is a standard SD host without DMA capabilities If the DMA_EN bit is 1 then this field returns 01h when read to indicate that the function is a standard SD host with DMA capabilities Silicon revision This field returns the silicon revision of the SD host controller 12 5 12 6 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the SD host controller See Table 12 5 for a complete description of the register contents
74. Register Description BIT FIELD NAME TYPE DESCRIPTION 31 isoChannel31 RSC When bit 31 is set to 1 the controller is enabled to receive from isochronous channel number 31 isoChannel30 When bit 30 is set to 1 the controller is enabled to receive from isochronous channel number 30 Bits 29 through 2 isoChanneln where n 29 28 27 2 follow the same pattern as bits 31 and 30 isoChannel1 When bit 1 is set to 1 the controller is enabled to receive from isochronous channel number 1 o isoChannel0 When bit 0 is set to 1 the controller is enabled to receive from isochronous channel number 0 8 21 Interrupt Event Register The interrupt event set clear register reflects the state of the various PCI7x21 PCI7x11 interrupt sources The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register This register is fully compliant with the 1394 Open Host Controller Interface Specification and the PCI7x21 PCI7x11 controller adds a vendor specific interrupt function to bit 30 When the interrupt event register is read the return value is the bit wise AND function of the interrupt event and interrupt mask registers See Table 8 15 for a complete description of the register contents ra els js ss 2 2 aso RSC
75. Register Description SIGNAL TYPE FUNCTION 7 04 SBDATA RW Serial bus data This bit field represents the data byte in a read or write transaction on the serial interface On reads the REQBUSY bit must be polled to verify that the contents of this register are valid These bits are cleared only by the assertion of GRST 4 48 Serial Bus Index Register The serial bus index register is for programmable serial bus byte reads and writes This register represents the byte address when generating cycles on the serial bus interface To write a byte the serial bus data register must be programmed with the data this register must be programmed with the byte address and the serial bus slave address must be programmed with both the 7 bit slave address and the read write indicator On byte reads the word address is programmed into this register the serial bus slave address must be programmed with both the 7 bit slave address and the read write indicator bit and bit 5 REQBUSY in the serial bus control and status register see Section 4 50 must be polled until clear Then the contents of the serial bus data register are valid read data from the serial bus interface See Table 4 23 for a complete description of the register contents Be z J e TOOT EAS 4 Name 2222 Serialbusimde Default Register Serial bus index Offset Bth function 0 Type Read Write Default 00h Table 4 23 Serial Bus Index Register Description S
76. SD DAT3 SD DAT3 SD CLK SD CLK SM D7 SM D7 SM EL WP SM EL WP SC_GPIO3 SC_GPIO3 GND GND J03 SD_CMD SD_CMD ISM_ALE SM ALE SC_GPIO2 SC_GPIO2 N J05 SD CLK SD CLK ISM_RE ISM_RE SC_GPIO1 SC_GPIO1 J06 SD DAT1 SD DATI SM D5 SM D5 SC GPIO5 SC_GPIO5 pu m O RESET o D _A6 A_CAD20 A_CPAR A_CAD14 A_CC BEO 10 Zz O B CAD21 H03 SD DATO B CBLOCK SM D4 SC_GPIO6 SC_GPIO6 HO5 MS_DATA3 MS DATA3 SD DAT3 SD DAT3 SM D3 SM D3 H07 SD WP SD WP K02 SM_PHYS_WP SM_PHYS_WP ISM_CE ISM_CE ISC_FCB ISC_FCB mes veo CCT kos scRs7 SRST 2 6 Table 2 1 Signal Names by GHK Terminal Number Continued SIGNAL NAME TERMINAL SIGNAL NAME CardBus PC Card 16 Bit PC Card NUMBER CardBus PC Card 16 Bit PC Card TERMINAL NUMBER KO5 SC_CLK CC BEO B CE1 K07 K08 K09 K10 K11 K12 K13 K14 K15 K17 K18 K19 SC_VCC_5V i J vwo w om om eno mo io ao eno w mo FUNC eno a nw we os com ens no lss sa seso eae w AD Abo scape ea m o Ar scab eas wm AGNO AGND Voos voce w ee eo scpata scoa ws sow sm so so o eewo eo so so me sows so sc Pwa ci scrwcm wo sca aoa ao aox mm munoz wuoz oo e ma ma eno ro pak Pak o e Ang IEA o o pak PAR a ElE E ofpojo O0 n r o o o Co o I k a
77. When a packet is destined for either the physical request context or the ARRQ context the source node ID is examined If the bit corresponding to the node ID is not set to 1 in this register then the packet is not acknowledged and the request is not queued The node ID comparison is done if the source node is on the same bus as the PCI7x21 PCI7x11 controller Nonlocal bus sourced packets are not acknowledged unless bit 31 in this register is set to 1 See Table 8 27 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Asynchronous request filter high pea o o o o o o o o o lololol oloi oie Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Asynchronous request filter high pesar o o o o o lo o lololo lo o fo o o jo Register Asynchronous request filter high Offset 100h set register 104h clear register Type Read Set Clear Default 0000 0000h Table 8 27 Asynchronous Request Filter High Register Description BIT FIELD NAME TYPE DESCRIPTION 31 asynRegAllBuses RSC If bit 31 is set to 1 all asynchronous requests received by the controller from nonlocal bus nodes are accepted 30 asynReqResource62 RSC If bit 30 is set to 1 for local bus node number 62 asynchronous requests received by the controller from that node are accepted 29 asynReqResource61 RSC If bit 29 is set to 1 for local bus node number 61
78. XXXXh Table 8 13 Isochronous Receive Channel Mask High Register Description isoChannel58 When bit 26 is set to 1 the controller is enabled to receive from isochronous channel number 58 isoChannel57 When bit 25 is set to 1 the controller is enabled to receive from isochronous channel number 57 isoChannel56 RS When bit 24 is set to 1 the controller is enabled to receive from isochronous channel number 56 isoChannel55 When bit 23 is set to 1 the controller is enabled to receive from isochronous channel number 55 isoChannel54 When bit 22 is set to 1 the controller is enabled to receive from isochronous channel number 54 RSC R a SC isoChannel51 When bit 19 is set to 1 the controller is enabled to receive from isochronous channel number 51 isoChannel49 When bit 17 is set to 1 the controller is enabled to receive from isochronous channel number 49 When bit 16 is set to 1 the controller is enabled to receive from isochronous channel number 48 isoChannel47 When bit 15 is set to 1 the controller is enabled to receive from isochronous channel number 47 isoChannel46 When bit 14 is set to 1 the controller is enabled to receive from isochronous channel number 46 isoChannel45 When bit 13 is set to 1 the controller is enabled to receive from isochronous channel number 45 When bit 12 is set to 1 the controller is enabled to receive from isochronous channel number 44 isoChannel43 When bit 11 is set to 1 the controller is enabled to re
79. a a smc r07 we oa we so we soe o vo Car w o o mo o vo Kz erst m soak ws smm co voc m7 osa ws scam o smo co voc mo mov ow sre o smo vos voc mo me o sc mos so smo vos veo mz mc ewr cro eon somos s swos so vec Nor Mc Pwe orata Fo scemo s smo wl voca as menco no somos s smo s voca m mewn vw somos s Swecwe co voos bw gt mence Po somos os SPS WP Ko voos Ko menco Po sccpios ro swag Ko voo we mwa Po seo me o voo wo mens nos sc pwn cra tos smwe ro vonis Tie runes Ro so aro Ko seror o7 vones ve mses scrsr Ko sop ws ven w mee seves K SUSPEND eo varon Hor ms ca os sos o testo pre vapor wo ws barat co S05 eo Teaow wis vs Pa ws pamo co soak co ee vs vu m7 ms pama Hos soak s rean we x me ms ooon co so omo re sap ve xo Ro 2 1 Detailed Terminal Descriptions Please see Table 2 4 through Table 2 19 for more detailed terminal descriptions The following list defines the column headings and the abbreviations used in the detailed terminal description tables e I O Type Digital input O Digital output O Digital input output Al Analog input PWR Power GND Ground e Input Output D
80. accessed section of card memory and is generally used to record card capacity and other configuration and v attribute information Naal DMA acknowledge REG is used as a DMA acknowledge DACK during DMA CCB operations to a 16 bit PC Card that supports DMA The controller asserts REG to A VEGA VccB Vcca VccB Veca VCCB Veca VccB Veca VCCB DMA write IORD strobes to transfer data B WAIT Bus cycle wait WAIT is driven by a 16 bit PC Card to extend the completion of the memory or I O cycle in progress Write enable WE is used to strobe memory write data into 16 bit memory PC Cards WE is also used for memory PC Cards that employ programmable memory technologies 1 DMA terminal count WE is used as a TC during DMA operations to a 16 bit PC Card that supports DMA The controller asserts WE to indicate the TC for a DMA read operation Write protect WP applies to 16 bit memory PC Cards WP reflects the status of the T These terminals are reserved for the PCI7611 and PCI7411 controllers write protect switch on 16 bit memory PC Cards For 16 bit I O cards WP is used for the 16 bit port IOIS16 function I O is 16 bits IOIS16 applies to 16 bit I O PC Cards IOIS16 is asserted by the 16 bit PC Card when the address on the bus corresponds to an address to which the 16 bit PC Card responds and the I O port that is addressed is capable of 16 bit accesses B B A_OE VSI _VS2 Ca A WE A WP OIST6 D
81. and next item pointer Offset 44h Type Read only Default 0001h Table 11 11 Capability ID and Next Item Pointer Registers Description BIT FIELD NAME TYPE DESCRIPTION Next item pointer The flash media controller supports only one additional capability PCI power 15 8 NEXT_ITEM management that is communicated to the system through the extended capabilities list therefore this field returns 00h when read Capability identification This field returns 01h when read which is the unique ID assigned by the PCI SIG for PCI power management capability 7 0 CAPABILITY_ID R 11 10 11 17 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the flash media controller related to PCI power management See Table 11 12 for a complete description of the register contents ee eee Power management capabilities ame RU Default Register Power management capabilities Offset 46h Type Read Update Read only Default 7E02h Table 11 12 Power Management Capabilities Register Description FIELD NAME TYPE DESCRIPTION PME support from D3gojg This bit can be set to 1 or cleared to 0 via bit 4 D3 COLD in the general control register at offset 4Ch in the PCI configuration space see Section 11 21 When this bit is set PME_D3COLD to 1 it indicates that the controller is capable of generating a PME wake event from D3c6 g This bit state is dependent upon the PCI7x
82. and notifies the host controller using one of several interrupt signaling protocols To simplify the discussion of interrupts in the PCI7x21 PCI7x11 controller PC Card interrupts are classified either as card status change CSC or as functional interrupts The method by which any type of PCI7x21 PCI7x11 interrupt is communicated to the host interrupt controller varies from system to system The PCI7x21 PCI7x11 controller offers system designers the choice of using parallel PCI interrupt signaling parallel ISA type IRQ interrupt signaling or the IRQSER serialized ISA and or PCI interrupt protocol It is possible to use the parallel PCI interrupts in combination with either parallel IRQs or serialized IRQs as detailed in the sections that follow All interrupt signaling is provided through the seven multifunction terminals MFUNCO MFUNCE 3 7 1 PC Card Functional and Card Status Change Interrupts PC Card functional interrupts are defined as requests from a PC Card application for interrupt service and are indicated by asserting specially defined signals on the PC Card interface Functional interrupts are generated by 16 bit I O PC Cards and by CardBus PC Cards Card status change CSC type interrupts are defined as events at the PC Card interface that are detected by the PCI7x21 PCI7x11 controller and may warrant notification of host card and socket services software for service CSC events include both card insertion and removal from PC Card sock
83. and returns Os when read CO NA BA CI a Name pao lo please Te Register Slot 5 3 3 V maximum current Type Read Write Offset A8h Default 0000h 12 17 12 18 13 Smart Card Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21 PCI7x11 Smart Card controller interface All registers are detailed in the same format a brief description for each register is followed by the register offset and a bit table describing the reset state for each register A bit description table typically included when the register contains bits of more than one type or purpose indicates bit field names a detailed field description and field access tags which appear in the type column Table 4 1 describes the field access tags The PCI7x21 PCI7x11 controller is a multifunction PCI device The Smart Card controller core is integrated as PCI function 5 The function 5 configuration header is compliant with the PC Local Bus Specification as a standard header Table 13 1 illustrates the configuration header that includes both the predefined portion of the configuration space and the user definable registers Table 13 1 Function 5 Configuration Register Map REGISTER NAME Device ID Vendor ID Class code Revision ID 08h Header type Latency timer OCh SC global control base address SC socket 0 base address SC socket 1 base address Reserved Subsystem ID Subsystem ven
84. are loaded through the serial EEPROM interface after a GRST At that point the contents of this register cannot be changed If no serial EEPROM is detected then the contents of this register are loaded by the BIOS At that point the contents of this register cannot be changed All bits in this register are reset by GRST only Register GUID high Offset 24h Type Read only Default 0000 0000h 8 11 GUID Low Register The GUID low register represents the lower quadlet in a 64 bit global unique ID GUID which maps to chip ID lo in the Bus_Info_Block This register initializes to Os on a system hardware reset and behaves identical to the GUID high register at OHCI offset 24h see Section 8 10 All bits in this register are reset by GRST only Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 GUID low EAT EA __ ___A A rrr Po fo fo fofofofofofofofofofofofofo meee EA OS EA A A ET GUID low fee R Ri R R AR R R aAteatri r ral rRi ri ere petat o o o fo fo fo PoP of of o lolofloljolo o Register GUID low Offset 28h Type Read only Default 0000 0000h 8 12 Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node See Table 8 8 for a complete description of the register contents eae le le e
85. are specific to the capability of the function The PCI power management capability implements the register block outlined in Table 3 15 Table 3 15 Power Management Registers REGISTER NAME OFFSET Power management capabilities Next item pointer Capability ID Power management control status register bridge support extensions Power management control status CSR The power management capabilities register PCI offset A2h see Section 4 43 provides information on the capabilities of the function related to power management The power management control status register PCI offset A4h see Section 4 44 enables control of power management states and enables monitors power management events The data register is an optional register that can provide dynamic data For more information on PCI power management see the PC Bus Power Management Interface Specification for PCI to CardBus Bridges 3 8 9 2 OHCI 1394 Function 2 Power Management The PCI7x21 PCI7x11 controller complies with the PCI Bus Power Management Interface Specification The controller supports the DO unitialized DO active D1 D2 and D3 power states as defined by the power management definition in the 1394 Open Host Controller Interface Specification Appendix A4 Table 3 16 Function 2 Power Management Registers REGISTER NAME OFFSET Power management capabilities Next item pointer Capability ID Power management control status register bridge support extensions
86. are tied internally When the TIEALL bit is set all four functions return a value of 01h on reads from the interrupt pin register for both parallel and serial PCI interrupts 3 19 The INTRTIE and TIEALL bits affect the read only value provided through accesses to the interrupt pin register PCI offset 3Dh see Section 4 24 Table 3 12 summarizes the interrupt signaling modes Table 3 12 Interrupt Pin Register Cross Reference INTPIN INTPIN INTPIN INTPIN INTPIN INTPIN ak ee Function 0 Function 1 Function 2 Function 3 Function 4 Function 5 CardBus CardBus 1394 OHCI Flash Media SD Host Smart Card Foo foo 0x01 INTA 0x02 INTB 0x03 INTC Determined by bits Determined by bits Determined by bits 6 5 INT SEL field in 6 5 INT SEL field in 6 5 INT SEL field in flash media general SD host general Smart Card general 1 0x01 INTA 0x01 INTA 0x03 INTC control register see control register see control register see Section 11 21 Section 12 22 Section 13 22 0x01 INTA 0x01 INTA 0x01 INTA 0x01 INTA 0x01 INTA 0x01 INTA 3 7 5 Using Serialized IRQSER Interrupts The serialized interrupt protocol implemented in the PCI7x21 PCI7x11 controller uses a single terminal to communicate all interrupt status information to the host controller The protocol defines a serial packet consisting of a start cycle multiple interrupt indication cycles and a stop cycle All data in the packet is synchronous w
87. asynchronous requests received by the controller from that node are accepted 28 asynReqResource60 RSC _ If bit 28 is set to 1 for local bus node number 60 asynchronous requests received by the controller from that node are accepted 27 asynReqResource59 RSC If bit 27 is set to 1 for local bus node number 59 asynchronous requests received by the controller from that node are accepted 26 asynReqResource58 RSC If bit 26 is set to 1 for local bus node number 58 asynchronous requests received by the controller from that node are accepted 25 asynReqResource57 RSC If bit 25 is set to 1 for local bus node number 57 asynchronous requests received by the controller from that node are accepted 24 asynReqResource56 RSC If bit 24 is set to 1 for local bus node number 56 asynchronous requests received by the controller from that node are accepted 23 asynReqResource55 RSC If bit 23 is set to 1 for local bus node number 55 asynchronous requests received by the controller from that node are accepted 22 asynReqResource54 RSC If bit 22 is set to 1 for local bus node number 54 asynchronous requests received by the controller from that node are accepted 21 asynReqResource53 RSC If bit 21 is set to 1 for local bus node number 53 asynchronous requests received by the controller from that node are accepted 20 asynReqResource52 RSC If bit 20 is set to 1 for local bus node number 52 asynchronous requests received by the contr
88. bits 6 4 2 0 50h Number of bytes 0Eh PCI 5Bh Smart Card configuration 1 byte 3 bits 7 4 2 0 PCI 09h class code byte 0 PCI 5Ch Smart Card configuration 2 byte O PCI 5Dh Smart Card configuration 2 byte 1 PCI Smart Card function indicator 05h 5Fh End of list indicator 80h 49h 4Ah 4Bh Ch Dh 4Eh 4Fh 50h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh 5Fh PCI 59h Smart Card configuration 1 byte 1 bits 6 4 2 0 3 7 Programmable Interrupt Subsystem Interrupts provide a way for I O devices to let the microprocessor know that they require servicing The dynamic nature of PC Cards and the abundance of PC Card I O applications require substantial interrupt support from the PCI7x21 PCI7x11 controller The PCI7x21 PCI7x11 controller provides several interrupt signaling schemes to accommodate the needs of a variety of platforms The different mechanisms for dealing with interrupts in this controller are based on various specifications and industry standards The ExCA register set provides interrupt control for some 16 bit PC Card functions and the CardBus socket register set provides interrupt control for the CardBus PC Card functions The PCI7x21 PCI7x11 controller is therefore backward compatible with existing interrupt control register definitions and new registers have been defined where required The PCI7x21 PCI7x11 controller detects PC Card interrupts and events at the PC Card interface
89. cleared by writing a 1 to the bit Access this register only through function 0 See Table 4 15 for a complete description of the register contents Name Retry status we aw w mw a mc A A aA ibatay A A A A A A 0 Register Retry status Offset 90h Functions O 1 Type Read only Read Write Read Clear Default COh Table 4 15 Retry Status Register Description SIGNAL TYPE FUNCTION PCI retry time out counter enable This bit is encoded as 74 PCIRETRY W 0 PCI retry counter disabled 1 PCI retry counter enabled default 6 t CBRETRY WwW 0 CardBus retry counter disabled 1 CardBus retry counter enabled default CardBus target B retry expired Write a 1 to clear this bit 57 TEXP CBB RC 0 Inactive default 1 Retry has expired RC R CardBus retry time out counter enable This bit is encoded as R RSVD Reserved This bit returns O when read CardBus target A retry expired Write a 1 to clear this bit 318 TEXP CBA 0 Inactive default 1 1 Retry has expired Reserved This bit returns O when read PCI target retry expired Write a 1 to clear this bit t TEXP_PCI 0 Inactive default 1 Retry has expired O RSVD oR Reserved This bit returns 0 when read This bit is cleared only by the assertion of GRST These bits are global in nature and must be accessed only through function 0 4 27 4 38 Card Control Register The card control register is provided f
90. clock Information on the DATA line is sampled at the rising edge of PCMCIA power L06 CLOCK CLOCK defaults to an input but can be changed to an output by using bit 27 VO TTLH TTLO1 switch P2CCLK in the system control register offset 80h see Section 4 29 Power switch data DATA is used to communicate socket power control information PCMCIA power N01 LVCO1 h serially to the power switch switch 02 Power switch latch LATCH is asserted by the controller to indicate to the power Lvcot PCMCIA power switch that the data on the DATA line is valid switch Table 2 6 PCI System Terminals N Internal pullup pulldown resistors and pin strapping are not applicable for the PCI terminals TERMINAL VO POWER EXTERNAL UNO DESCRIPTION type INPUT pai COMPONENTS Global reset When the global reset is asserted the GRST signal causes the controller to place all output buffers in a high impedance state and reset all internal registers When GRST is asserted the controller is completely in its default state For systems that require wake up from D3 GRST is normally asserted only during initial PaWekohrasetor boot PRST must be asserted following initial boot so that PME context is retained LVCl2 tied to PRST when transitioning from D3 to DO For systems that do not require wake up from D3 GRST must be tied to PRST When the SUSPEND mode is enabled the controller is protected from the GRST and the internal registers are preserved
91. clock connected to the CLK 48 terminal to provide the reference for an internal oscillator circuit This oscillator in turn drives a PLL circuit that generates the various clocks required for the flash media function Function 3 of the PCI7x21 PCI7x11 controller The 48 MHz clock is needed as follows in the designated states e Power up Follow the power up sequence e DO Clock must not be stopped e D1 D2 D3 Clock can be stopped e D1 D2 D3notto DO Need 10 clocks before DO state e D3colg to DO Need 10 clocks before PRST de assert The 48 MHz clock must maintain a frequency of 48 MHz 0 8 over normal operating conditions This clock must maintain a duty cycle of 40 60 The PCI7x21 PCI7x11 controller requires that the 48 MHz clock be running and stable a minimum of 10 clock pulses before a GRST deassertion The following are typical specifications for crystals used with the PCI7x21 PCI7x11 controller in order to achieve the required frequency accuracy and stability e Crystal mode of operation Fundamental e Frequency tolerance 25 C Total frequency variation for the complete circuit is 100 ppm A crystal with 30 ppm frequency tolerance is recommended for adequate margin e Frequency stability overtemperature and age A crystal with 30 ppm frequency stability is recommended for adequate margin NOTE The total frequency variation must be kept below 100 ppm from nominal with some allowance for error introduced by
92. control status bridge support extensions Type Default Register Power management control status bridge support extensions Offset A6h Functions 0 1 Type Read only Default COh Table 4 21 Power Management Control Status Bridge Support Extensions Register Description SIGNAL TYPE FUNCTION Bus power clock control enable This bit returns 1 when read This bit is encoded as 0 Bus power clock control is disabled 1 Bus power clock control is enabled default 7 BPCC EN R A 0 indicates that the bus power clock control policies defined in the PC Bus Power Management Interface E Specification are disabled When the bus power clock control enable mechanism is disabled the power state field bits 1 0 of the power management control status register PCI offset A4h see Section 4 44 cannot be used by the system software to control the power or the clock of the secondary bus A 1 indicates that the bus power clock control mechanism is enabled B2 B3 support for D3hot The state of this bit determines the action that is to occur as a direct result of programming the function to D3pot This bit is only meaningful if bit 7 BPCC_EN is a 1 This bit is encoded B2_B3 R SARA 0 When the bridge is programmed to D3pgt its secondary bus has its power removed B3 1 When the bridge function is programmed to D3p t its secondary bus PCI clock is stopped B2 default R Reserved These bits return Os when read 4 46 Power Mana
93. controller receives a new node number from its PHY layer Bit 30 is set to 1 during the bus reset process if the attached PHY layer is root Reserved Bits 29 and 28 return Os when read Bit 27 is set to 1 if the PHY layer is reporting that cable power status is OK Reserved Bits 26 16 return Os when read This field identifies the specific 1394 bus the PCI7x21 PCI7x11 controller belongs to when multiple 1394 compatible buses are connected via a bridge The default value for this field is all 1s This field is the physical node number established by the PHY layer during self identification It is automatically set to the value received from the PHY layer after the self identification phase If the PHY layer sets the nodeNumber to 63 then software must not set bit 15 run in the asynchronous context control register see Section 8 40 for either of the AT DMA contexts 8 29 8 33 PHY Layer Control Register The PHY layer control register reads from or writes to a PHY register See Table 8 25 for a complete description of the register contents lalalalala A PHY layer control ame RU RU RU RU RU RU RU RU RU RU RU RU Default e awu awu a n aw AW AW Aw RW Denn o o o lo o o o o o lo o o o lo lo o Register PHY layer control Offset ECh Type Read Write Update Read Write Read Update Read only Default 0000 0000h Table 8 25 PHY Control Register Description BIT FIELD NAME TYPE DESCRIPTION rdDone RU
94. controller to enable 16 bit I O PC Card data output during host I O read cycles A_IORD B_IORD L15 DMA write IORD is used as the DMA write strobe during DMA operations from a 16 bit PC Card that supports DMA The controller asserts IORD during DMA BE transfers from the PC Card to host memory A A_IOWR T These terminals are reserved for the PCI7611 and PCI7411 controllers C15 N13 Card detect 1 and card detect 2 CD1 and CD2 are internally connected to ground E05 B17 on the PC Card When a PC Card is inserted into a socket CD1 and CD2 are Input acknowledge INPACK is asserted by the PC Card when it can respond to an 1 0 read cycle at the current address DMA request INPACK can be used as the DMA request signal during DMA operations from a 16 bit PC Card that supports DMA If it is used as a strobe then the PC Card asserts this signal to indicate a request for a DMA operation 1 O write IOWR is driven low by the controller to strobe write data into 16 bit I O PC Cards during host I O write cycles DMA read IOWR is used as the DMA write strobe during DMA operations from a 16 bit PC Card that supports DMA The controller asserts IOWR during transfers from host memory to the PC Card 2 20 Table 2 11 16 Bit PC Card Interface Control Terminals Continued SKT A TERMINAL SKT B TERMINALT 1 0 POWER C name fno name ana mee pi Output enable OE is driven low by the controller to enable 16 bit memory PC Card data output
95. controls the state of all of the 16 bit outputs on the PCI7x21 PCI7x11 controller This bit is encoded as Al COE ae 0 16 bit PC Card outputs are disabled default 1 16 bit PC Card outputs are enabled RSVD R Reserved These bits return Os when read Writes have no effect VCC These bits are used to request changes to card Vcc This field is encoded as 4 31 EXCAVCC RW 00 0 V default 10 5V 01 0 V reserved 11 3 3V RSVD R This bit returns 0 when read A write has no effect Vpp These bits are used to request changes to card Vpp The PCI7x21 PCI7x11 controller ignores this field unless Vcc to the socket is enabled i e 5 Vdc or 3 3 Vdc This field is encoded as 120 F EXGSIRE Li NN 00 0 V default 10 12V 01 Voc 11 0 V reserved t This bit is cleared only by the assertion of GRST when PME is enabled If PME is not enabled then this bit is cleared by the assertion of PRST or GRST 5 7 5 4 ExCA Interrupt and General Control Register This register controls interrupt routing for I O interrupts as well as other critical 16 bit PC Card functions See Table 5 6 for a complete description of the register contents ee TE interrupt a general Sal Offset CardBus Socket Address 803h Card A ExCA Offset 03h Card B ExCA Offset 43h Type Read Write Default 00h Table 5 6 ExCA Interrupt and General Control Register Description BIT SIGNAL TYPE FUNCTION Card ring indicate enable Enabl
96. default CSC interrupts are routed to PCI Interrupts This bit setting is ORed with bit 4 CSCROUTE for backward compatibility 0001 IRQ1 enabled 0010 SMI enabled 0011 IRQ3 enabled 0100 IRQ4 enabled 0101 IRQ5 enabled INTSELECT 0110 IRQ6 enabled 0111 IRQ7 enabled 1000 IRQ8 enabled 1001 IRQ9 enabled 1010 IRQ10 enabled 1011 IRQ11 enabled 1100 IRQ12 enabled 1101 IRQ13 enabled 1110 IRQ14 enabled 1111 IRQ15 enabled This bit is cleared only by the assertion of GRST when PME is enabled If PME is not enabled then this bit is cleared by the assertion of PRST or GRST 5 8 5 5 ExCA Card Status Change Register The ExCA card status change register controls interrupt routing for I O interrupts as well as other critical 16 bit PC Card functions The register enables these interrupt sources to generate an interrupt to the host When the interrupt source is disabled the corresponding bit in this register always reads 0 When an interrupt source is enabled the corresponding bit in this register is set to indicate that the interrupt source is active After generating the interrupt to the host the interrupt service routine must read this register to determine the source of the interrupt The interrupt service routine is responsible for resetting the bits in this register as well Resetting a bit is accomplished by one of two methods a read of this register or an explicit writeback of 1 to the status
97. description of the register contents Bt 31 30 29 28 27 26 25 2a 23 22 21 20 19 18 17 16 Initial channels available low Name initia channels availablelow OOO Fe a E E Default pee eps be eee ee eee Initial channels available low are RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default Register Initial channels available low Offset B8h Type Read Write Default FFFF FFFFh Table 8 21 Initial Channels Available Low Register Description BIT FIELD NAME TYPE DESCRIPTION 31 0 InitChanAvailLo This field is reset to FFFF_FFFFh on a system hardware or software reset and is not affected by a 1394 bus reset The value of this field is loaded into the CHANNELS AVAILABLE LO CSR register upon a GRST PRST or a 1394 bus reset 8 26 8 30 Fairness Control Register The fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval See Table 8 22 for a complete description of the register contents 24 23 22 21 20 19 18 17 16 Fairness control Fairness control Ca aw Aw Aw Aw Aw AW AW AW Po flofofofofo jojo o Register Fairness control Offset DCh Type Read only Default 0000 0000h Table 8 22 Fairness Control Register Description a FIELDNAME TYPE DESCRIPTION RSVD BE Reserved Bits 31 8 return Os when re
98. during host r memory read cycles v C12 DMA terminal count OE is used as terminal count TC during DMA operations to a bia 16 bit PC Card that supports DMA The controller asserts OE to indicate TC for a DMA CCB A READY o A03 E08 B B READY IREQ B_REG 3 OE B_RESET PC Card reset RESET forces a hard reset to a 16 bit PC Card B_VS1 C1 oltage sense 1 and voltage sense 2 VS1 and VS2 when used in conjunction with B_VS2 Fi each other determine the operating voltage of the PC Card WE WP 01816 indicate a DMA operation REG is used in conjunction with the DMA read IOWR or write operation A_REG Ready The ready function is provided when the 16 bit PC Card and the host socket are configured for the memory only interface READY is driven low by 16 bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command READY is driven high when the 16 bit memory PC Card is ready to accept a VECA B19 new data transfer command VCCB Interrupt request IREQ is asserted by a 16 bit I O PC Card to indicate to the host that a controller on the 16 bit I O PC Card requires service by the host software IREQ is high deasserted when no interrupt is requested A RESET Attribute memory select REG remains high for all common memory accesses When REG is asserted access is limited to attribute memory OE or WE active and to the I O space IORD or IOWR active Attribute memory is a separately
99. for this field is all Os TI SZ TI register size This field returns Os when read indicating that the TI registers require a 16K byte region of memory 3 TPF R TI register prefetch Bit 3 returns 0 when read indicating that the TI registers are nonprefetchable TI memory type This field returns Os when read indicating that the TI base address register is 32 bits TI MEMTYPE wide and mapping can be done anywhere in the 32 bit memory space TI MEM TI memory indicator Bit 0 returns 0 when read indicating that the TI registers are mapped into system memory space 7 7 7 10 CardBus CIS Base Address Register The internal CARDBUS input to the 1394 OHCI core is tied high such that this register returns Os when read See Table 7 9 for a complete description of the register contents Register CardBus CIS base address Offset 18h Type Read Write Read only Default 0000 0000h Table 7 9 CardBus CIS Base Address Register Description FIELD NAME DESCRIPTION CIS BASE CIS base address This field specifies the upper 21 bits of the 32 bit CIS base address If CARDBUS is sampled high on a GRST then this field is read only returning Os when read cls sz CIS address space size This field returns Os when read indicating that the CIS space requires a 2K byte region of memory CIS prefetch Bit 3 returns 0 when read indicating that the CIS is nonprefetchable Furthermore the CIS_PF CIS is a byte acces
100. function response to parity errors through PERR Data parity errors are indicated by asserting PERR whereas address parity errors are indicated by asserting SERR 0 This function ignores detected parity error default 1 This function responds to detected parity errors VGA palette snoop enable The Smart Card interface does not feature VGA palette snooping therefore bit 5 returns 0 when read Memory write and invalidate enable The Smart Card controller does not generate memory write invalidate transactions therefore bit 4 returns 0 when read 3 SPECIAL R Special cycle enable The Smart Card interface does not respond to special cycle transactions therefore bit 3 returns 0 when read 2 MAST_EN R Bus master enable This function is target only 1 MEM_EN RW Memory space enable This bit controls memory access 0 Disables this function from responding to memory space accesses default 1 Enables this function to respond to memory space accesses 0 IO_EN R I O space enable The Smart Card interface does not implement any l O mapped functionality therefore bit O returns 0 when read 13 3 13 4 Status Register The status register provides device information to the host system All bit functions adhere to the definitions in the PCI Local Bus Specification as seen in the following bit descriptions Bits in this register may be read normally A bit in the status register is reset when a 1 is written to that bit l
101. host BIOS to assign a latency timer register value to the PCI7x21 PCI7x11 controller The default for this register indicates that the PCI7x21 PCI7x11 RU controller may need to sustain burst transfers for nearly 64 us and thus request a large value be FIELD NAME TYPE DESCRIPTION programmed in bits 15 8 of the PCI7x21 PCI7x11 latency timer and class cache line size register at offset OCh in the PCI configuration space see Section 7 6 Bits 3 0 of this field may also be loaded through the Maximum latency The contents of this field may be used by host BIOS to assign an arbitration priority level 15 8 MAX_LAT 7 0 MIN_GNT serial EEPROM to the PCI7x21 PCI7x11 controller The default for this register indicates that the PCI7x21 PCI7x11 These bits are cleared only by the assertion of GRST 7 17 OHCI Control Register The PCI OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a bit for big endian PCI support See Table 7 14 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name OHCI control A O o A o Default 15 4 13 12 11 10 8 7 Name OHCI control Type R R R R RW Default 0 0 0 0 0 Register OHCI control Offset 40h Type Read Write Read only Default 0000 0000h Table 7 14 OHCI Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 1 RSVD Reserved Bits 31 1 return Os when read
102. in the ExCA registers described in this chapter I O windows have byte granularity Access to memory mapped 16 bit PC Cards is available to the host system via five ExCA memory windows These are regions of host memory space into which the card memory space is mapped These windows are defined by start end and offset addresses programmed in the ExCA registers described in this chapter Memory windows have 4 Kbyte granularity A bit location followed by a means that this bit is not cleared by the assertion of PRST This bit is only cleared by the assertion of GRST This is necessary to retain device context during the transition from D3 to DO 5 2 Host I O Space Offset PCI7x21 PCI7x11 Configuration Registers Offset 00h PC Card A ExCA Registers CardBus Socket ExCA Base Address 10h E 40h 16 Bit Legacy Mode Base Address 44h PC Card B ExCA Registers Note The 16 bit legacy mode base address 7Fh register is shared by function 0 and 1 as indicated by the shading y g Offset of desired register is placed in the index register and the data from that location is returned in the data register Figure 5 1 ExCA Register Access Through I O Host Host PCI7x21 PCI7x11 Configuration Registers Memory Space Memory Space Offset Offset Offset 00h CardBus Socket A av CardBus Socket ExCA Base Address 10h i Registers pra 00h 16 Bit L Mode Base Add amen Socket B Bit Legacy Mode Base ress 44h l Registers Reg
103. input output polarity control for GPIOO 0 Noninverted default 1 Inverted GPIOO enable control When bit 7 DISABLE_BMC is set to 1 this bit controls the output enable for GPIOO 0 High impedance output default 1 Output is enabled R W 3 RSVD Reserved Bits 3 1 return Os when read 1 R GPIOO0 data When bit 7 DISABLE BMC is set to 1 and GPIOO output is enabled the value written to 0 GPIO_DATAO RAV this bit represents the logical data driven to the GPIOO terminal 8 OHCI Registers The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory mapped into a 2K byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space see Section 7 8 These registers are the primary interface for controlling the PCI7x21 PCI7x11 IEEE 1394 link function This section provides the register interface and bit descriptions Several set clear register pairs in this programming model are implemented to solve various issues with typical read modify write control registers There are two addresses for a set clear register RegisterSet and RegisterClear See Table 8 1 for a register listing A 1 bit written to RegisterSet causes the corresponding bit in the set clear register to be set to 1 a O bit leaves the corresponding bit unaffected A 1 bit written to RegisterClear causes the corresponding bit in the set clear register to be cleared a 0 bit
104. is an automatic COE that is the PWRDWN performs the COE function when there is no card activity NOTE The 16 bit PC Card must implement the proper pullup resistors for the COE and PWRDWN modes 3 8 6 Suspend Mode The SUSPEND signal provided for backward compatibility gates the PRST PCI reset signal and the GRST global reset signal from the PCI7x21 PCI7x11 controller Besides gating PRST and GRST SUSPEND also gates PCLK inside the PCI7x21 PCI7x11 controller in order to minimize power consumption It should also be noted that asynchronous signals such as card status change interrupts and RI OUT can be passed to the host system without a PCI clock However if card status change interrupts are routed over the serial interrupt stream then the PCI clock must be restarted in order to pass the interrupt because neither the internal oscillator nor an external clock is routed to the serial interrupt state machine Figure 3 14 is a signal diagram of the suspend function RESET GNT SUSPEND PCLK External Terminals Internal Signals RESETIN SUSPENDIN Figure 3 14 Signal Diagram of Suspend Function 3 8 7 Requirements for Suspend Mode The suspend mode prevents the clearing of all register contents on the assertion of reset PRST or GRST which would require the reconfiguration of the PCI7x21 PCI7x11 controller by software Asserting the SUSPEND signal 3 23 places the PCI outputs of the
105. is set to 1 for local bus node number 43 asynchronous requests received by the controller from that node are accepted 10 asynReqResource42 RSC If bit 10 is set to 1 for local bus node number 42 asynchronous requests received by the controller from that node are accepted 9 asynReqResource41 RSC If bit 9 is set to 1 for local bus node number 41 asynchronous requests received by the controller from that node are accepted 8 asynReqResource40 RSC If bit 8 is set to 1 for local bus node number 40 asynchronous requests received by the controller from that node are accepted TA asynReqResource39 RSC If bit 7 is set to 1 for local bus node number 39 asynchronous requests received by the controller from that node are accepted 6 asynReqResource38 RSC If bit 6 is set to 1 for local bus node number 38 asynchronous requests received by the controller from that node are accepted 5 asynReqResource37 RSC If bit 5 is set to 1 for local bus node number 37 asynchronous requests received by the controller from that node are accepted 4 asynReqResource36 RSC If bit 4 is set to 1 for local bus node number 36 asynchronous requests received by the controller from that node are accepted 3 asynReqResource35 RSC If bit 3 is set to 1 for local bus node number 35 asynchronous requests received by the controller from that node are accepted 2 asynReqResource34 RSC If bit 2 is set to 1 for local bus node number 34 asynchronous r
106. is set to 1 for local bus node number 57 physical requests received by the controller from that node are handled through the physical request context 24 physReqResource56 RSC If bit 24 is set to 1 for local bus node number 56 physical requests received by the controller from that node are handled through the physical request context 23 physReqResource55 RSC If bit 23 is set to 1 for local bus node number 55 physical requests received by the controller from that node are handled through the physical request context 22 physReqResource54 RSC If bit 22 is set to 1 for local bus node number 54 physical requests received by the controller from that node are handled through the physical request context 21 physReqResource53 RSC If bit 21 is set to 1 for local bus node number 53 physical requests received by the controller from that node are handled through the physical request context 20 physReqResource52 RSC If bit 20 is set to 1 for local bus node number 52 physical requests received by the controller from that node are handled through the physical request context 19 physReqResource51 RSC If bit 19 is set to 1 for local bus node number 51 physical requests received by the controller from that node are handled through the physical request context 8 35 BIT Table 8 29 Physical Request Filter High Register Description Continued FIELD NAME TYPE DESCRIPTION 18 physReqResource50 RSC If bit 18 is set to 1 for local bus node number 50 ph
107. leaves the corresponding bit in the set clear register unaffected Typically a read from either RegisterSet or RegisterClear returns the contents of the set or clear register respectively However sometimes reading the RegisterClear provides a masked version of the set or clear register The interrupt event register is an example of this behavior Table 8 1 OHCI Register Map DMA CONTEXT REGISTER NAME ABBREVIATION OFFSET OHCI version Version 00h CSR compare CSRCompareData 10h Configuration ROM header ConfigROMhdr 18h Bus identification BusID 1Ch GUID high GUIDHi 24h HCControlSet 50h HCControlClr 54h Reserved 58h 5Ch Host controller control One or more bits in this register are cleared only by the assertion of GRST 8 1 Table 8 1 OHCI Register Map Continued DMA CONTEXT REGISTER NAME ABBREVIATION OFFSET Self ID Reserved Self ID buffer pointer SelflDBuffer Self ID count SelfIDCount 7 60h 64h 68h Ch Interrupt mask IntMaskClear 8Ch Na IsoXmitIntEventSet 90h Isochronous transmit interrupt event IsoXmitIntEventClear 94h a IsoXmitIntMaskSet 98h Isochronous transmit interrupt mask IsoXmitintMaskClear 9Ch o IsoRecvIntEventSet A0h Isochronous receive interrupt event Boh B4h B8h DCh EOh E4h E8h ECh FOh Reems oo y y B0h Dah Initial bandwidth available InitialBandwidthAvailable LinkControlSet Link control LinkControlClear Initial channels
108. multispeed concatenation arbitration acceleration fly by concatenation and port disable suspend resume Power down features to conserve energy in battery powered applications include automatic device power down during suspend PCI power management for link layer and inactive ports powered down ultralow power sleep mode Two IEEE Std 1394a 2000 fully compliant cable ports at 100M bits s 200M bits s and 400M bits s Cable ports monitor line conditions for active connection to remote node Cable power presence monitoring Separate cable bias TPBIAS for each port Physical write posting of up to three outstanding transactions PCI burst transfers and deep FIFOs to tolerate large host latency 1 3 e External cycle timer control for customized synchronization e Extended resume signaling for compatibility with legacy DV components e PHY Link logic performs system initialization and arbitration functions e PHY Link encode and decode functions included for data strobe bit level encoding e PHY Link incoming data resynchronized to local clock e Low cost 24 576 MHz crystal provides transmit and receive data at 100M bits s 200M bits s and 400M bits s e Node power class information signaling for system power management e Register bits give software control of contender bit power class bits link active control bit and IEEE Std 1394a 2000 features e Isochronous receive dual buffer mode e Out of order pipelining for asynchronous transmit
109. no PCI clock is required for the function to generate PME Functions that do not support PME generation in any state must return 0 for this field These 3 bits return 010b when read indicating that there are 4 bytes of general purpose power 2 0 Version R management PM registers as described in draft revision 1 1 of the PC Bus Power Management Interface Specification This bit is cleared only by the assertion of GRST 4 32 4 44 Power Management Control Status Register The power management control status register determines and changes the current power state of the PCI7x21 PCI7x11 CardBus function The contents of this register are not affected by the internally generated reset caused by the transition from the D3p to DO state See Table 4 20 for a complete description of the register contents All PCI registers EXCA registers and CardBus registers are reset as a result of a D3p to DO state transition with the exception of the PME context bits if PME is enabled and the GRST only bits 7 Power management control status PR Ra rw a r ria r pw ew po fo fo fofoftofoftoftoftofo Register Power management control status Offset A4h Functions 0 1 Type Read only Read Write Read Write Clear Default 0000h Table 4 20 Power Management Control Status Register Description SIGNAL TYPE FUNCTION PME status This bit is set when the CardBus function would normally assert the PME signal indepe
110. of frame packet in a DV stream before transferring the received isochronous stream into the memory buffer described by the INPUT_MORE descriptors This can improve the DV capture application performance by reducing the amount of processing overhead required to strip the CIP header and copy the received packets into frame sized buffers The start of a DV frame is represented in the 1394 packet as a 16 bit pattern of 1FX7h first byte 1Fh and second byte X7h received as the first two bytes of the third quadlet in a DV isochronous packet 9 3 Isochronous Receive Digital Video Enhancements Register The isochronous receive digital video enhancements register enables the DV enhancements in the PCI7x21 PCI7x11 controller The bits in this register may only be modified when both the active bit 10 and run bit 15 bits of the corresponding context control register are 0 See Table 9 2 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Isochronous receive digital video enhancements ooo Sochronoue receive digital video enhancements mwe RIRIRIRIRIRI IR R R R R RIRI R R R Detam o o o o o fo o o o lo fo fo o fofoJo Isochronous receive digital video enhancements Frans receive dial video enpancements perno fo o lo o o o o o lo o o o lololo Register Isochronous receive digital video enhancements Offset A80h set register
111. offset 80h 84h see Section 8 21 are set to 1 this request transmit complete interrupt mask enables interrupt generation 8 21 8 23 Isochronous Transmit Interrupt Event Register The isochronous transmit interrupt event set clear register reflects the interrupt state of the isochronous transmit contexts An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST command completes and its interrupt bits are set to 1 Upon determining that the isochTx bit 6 interrupt has occurred in the interrupt event register at OHCI offset 80h 84h see Section 8 21 software can check this register to determine which context s caused the interrupt The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register See Table 8 17 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Isochronous transmit interrupt event ee RIRIRIRIRIRIRI R R R R RIR RI R R peat o o o fofofofofoftofofofofofofofo Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o0 Isochronous transmit interrupt event mwe R R R R RA R A rse RSC petan o o o fo fo fo fo fo KE xT xt xxx xx Register Isochronous tran
112. only Read Write when bit 5 in the system control register is 0 Default 0000h 4 27 Subsystem ID Register The subsystem ID register used for system and option card identification purposes may be required for certain operating systems This register is read only or read write depending on the setting of bit 5 SUBSYSRW in the system control register PCI offset 80h see Section 4 29 When bit 5 is O this register is read write when bit 5 is 1 this register is read only The default mode is read only All bits in this register are reset by GRST only If an EEPROM is present then the subsystem ID and subsystem vendor ID is loaded from the EEPROM after a reset is arar wf fo e 7 Poe Ps Pat se eta o Subsystem ID Name Subsystem i mwe R R IR R RIR R R R R R R R R R R De o o o o fo fo fo fo fo fo foto ftofofo fo Register Subsystem ID Offset 42h Functions 0 1 Type Read only Read Write when bit 5 in the system control register is 0 Default 0000h 4 28 PC Card 16 Bit I F Legacy Mode Base Address Register The PCI7x21 PCI7x11 controller supports the index data scheme of accessing the ExCA registers which is mapped by this register An address written to this register is the address for the index register and the address 1 is the data address Using this access method applications requiring index data ExCA access can be supported The base address can be mapped anywhere in 32 bit I O spa
113. over specification and is used to latch commands TIROS swa Veo passed over SM_D7 SM_DO SmartMedia data terminals These signals pass data to and from the SmartMedia and functions TTLI2 TTLO2 SW2 Vcc as specified in the SmartMedia specifications SmartMedia electrical write protect NE TTLO2 SmartMedia physical write protect This input K02 comes from the write protect tab of the PCII5 PCIO5 SW3 SmartMedia card SmartMedia read enable This signal functions as SM_RE J05 specified in the SmartMedia specification and is TTLO2 SW2 Vcc used to latch a read transfer from the card SM_EL_WP SM_PHYS_WP SM_R B SM_WE SmartMedia read busy This signal functions as specified in the SmartMedia specification and is PCII5 PCIOS SW3 Voc used to pace data transfers to the card SmartMedia write enable This signal functions as specified in the SmartMedia specification and is TTLO2 SW2 Vcc used to latch a write transfer to the card 2 28 Table 2 19 Smart Card Terminals t If any Smart Card terminal is unused then the terminal may be left floating except for SC_VCC_5V which must be connected to 5 V NON 1 0 PU POWER EXTERNAL DESCRIPTION TYPE INPUT OUTPUT PD RAIL maa Smart Card card detect This input is asserted when Smart pg kQ resistor to Smart Card clock The controller drives a 3 MHz clock to the GND Seer Smart Card interface when enabled pals 68 pF capacitor GND O E oo E Smart Card overcu
114. parity errors through the PERR signal Data parity errors are indicated by asserting PERR while address parity errors are indicated PERR_EN by asserting SERR 0 PCI7x21 PCI7x11 controller ignores detected parity errors default 1 PCI7x21 PCI7x11 controller responds to detected parity errors VGA palette snoop When set to 1 palette snooping is enabled i e the PCI7x21 PCI7x11 controller does VGA_EN RW not respond to palette register writes and snoops the data When the bit is 0 the PCI7x21 PCI7x11 controller treats all palette accesses like all other accesses Memory write and invalidate enable This bit controls whether a PCI initiator device can generate memory write and invalidate commands The PCI7x21 PCI7x11 controller does not support memory write and invalidate commands it uses memory write commands instead therefore this bit is hardwired to O This bit returns O when read Writes to this bit have no effect MWI_EN R Special cycles This bit controls whether or not a PCI device ignores PCI special cycles The SPECIAL R PCI7x21 PCI7x11 controller does not respond to special cycle operations therefore this bit is hardwired to 0 This bit returns 0 when read Writes to this bit have no effect Bus master control This bit controls whether or not the PCI7x21 PCI7x11 controller can act as a PCI bus initiator master The PCI7x21 PCI7x11 controller can take control of the PCI bus only when this bit is set 0 Disables t
115. pin polarity This bit controls the polarity of the MC_PWR_CTRL_0 and FM_PWR_CTRL POL MC_PWR_CTRL_1 terminals 44 SC_IF_SEL TE 0 MC PWR CTRL xx terminals are active low default 1 MC_PWR_CTRL_x terminals are active high SIM MODE lO LIMIT SEL 11t lIO BASE SEL BIT 15t Smart Card interface select This bit controls the selection of the dedicated Smart Card interface used by the controller 0 EMV interface selected default 1 PCI7x10 style interface selected Note The PCI7x10 style interface is only allowed when bits 9 8 FM_IF_SEL field are 01 If bits 9 8 contain any other value then this bit is O Care must be taken in the design to ensure that this bit can be set to 1 at the same time that bits 9 8 are set to 01 When this bit is set it reduces the query time for UltraMedia card types 0 Query time is unaffected default 1 Query time is reduced for simulation purposes When this bit is set bit O in the I O limit registers PCI offsets 30h and 38h for both CardBus functions is set 0 Bit 0 in the I O limit registers is O default 1 Bit 0 in the I O limit registers is 1 When this bit is set bit O in the I O base registers PCI offsets 2Ch and 34h for both CardBus functions R is set 0 Bit 0 in the I O base registers is 0 default 1 Bit 0 in the I O base registers is 1 wo k N i Power switch select This bit selects which power switch is implemented in the system 0 A 1 8 V ca
116. power management control and status register implements the control and status of the Smart Card controller This register is not affected by the internally generated reset caused by the transition from the D3p to DO state See Table 13 12 for a complete description of the register contents Register Power management control and status Offset 48h Type Read Clear Update Read Write Read only Default 0000h Table 13 12 Power Management Control and Status Register Description pit FIELDNAME TYPE DESCRIPTION 15t PME STAT PME status This bit is set when the function would normally assert the PME signal independent of the state of PME EN bit Writing a 1 to this bit clears it and causes the function to stop asserting a PME if enabled Writing a O has no effect This bit is initialized by GRST only when the PME D3cold bit is1 RSVD R Reserved Bits 14 9 return Os when read PME EN PME enable This bit is initialized by GRST only when PME D3cold bit is 1 RSVD A Reserved Bits 7 2 return Os when read 1 0 DSTATE Device State This bit field controls device power management state Invalid state assignments are ignored ex Current state 10b writing 01b This is rejected and stays 10b See the latest PCI Local Bus Specification This bit field is initialized by GRST only when PME D3cold bit is 1 One or more bits in this register are cleared only by the assertion of GRST 13 20 Power Management Bridge Support Ext
117. rates of 100 200 and 400 Mbits per second Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies The PCI7421 provides physical write posting and a highly tuned physical data path for SBP 2 performance Function 3 of the PCI7421 controller is a PCl based Flash Media controller that supports Memory Stick Memory Stick Pro SmartMedia XD SD and MMC cards This function controls communication with these Flash Media cards through a passive PC Card adapter or through a dedicated Flash Media socket In addition this function includes DMA capabilities for improved Flash Media performance Function 4 of the PCI7421 controller is a PCl based SD host controller that supports MMC SD and SDIO cards This function controls communication with these Flash Media cards through a passive PC Card adapter or through a dedicated Flash Media socket In addition this function is compliant with the SD Host Controller Standard Specification and includes both DMA capabilities and support for SD suspend resume 1 1 3 PCI7611 Controller The PCI7611 controller is a five function PCI controller compliant with PCI Local Bus Specification Revision 2 3 Function 0 provides an independent PC Card socket controller compliant with the PC Card Standard Release 8 1 The PCI7611 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards and supports Smart Card Flash Media 16 bit CardBus or USB cust
118. receive context command CommandPtr 40Ch 32 n Isochronous receive context match ContextMatch 410h 32 n 8 1 OHCI Version Register The OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is present See Table 8 2 for a complete description of the register contents q AAA A OHCI version ame RU Default OHCI version A e ss fee R7 R RIR R R R R R R R R R R R R peran o o o o fo fo fo fo Po fof oft foto foto Register OHCI version Offset 00h Type Read only Default 0X01 0010h Table 8 2 OHCI Version Register Description FIELD NAME TYPE DESCRIPTION 31 25 RSVD Reserved Bits 31 25 return Os when read GUID_ROM The PC17x21 PC17x11 controller sets bit 24 to 1 if the serial EEPROM is detected If the serial EEPROM is present then the Bus_Info_Block is automatically loaded on system hardware reset The default value for this bit is 0 version Major version of the OHCI The PCI7x21 PCI7x11 controller is compliant with the 1394 Open Host Controller Interface Specification Release 1 1 thus this field reads 01h o COCO CI EIA CCP Reserved Bits 15 8 return Os when read revision Minor version of the OHCI The PCI7x21 PCI7x11 controller is compliant with the 1394 Open Host Controller Interface Specification Release 1 1 thus this field reads 10h This bit is cleared only by the assertion of GRST 8 4 8 2 GUID ROM
119. requests e Register access fail interrupt when the PHY SCLK is not active e PCI power management DO D1 D2 and D3 power states e Initial bandwidth available and initial channels available registers e PME support per 1394 Open Host Controller Interface Specification e Advanced submicron low power CMOS technology Related Documents e Advanced Configuration and Power Interface ACP Specification Revision 2 0 e 1394 Open Host Controller Interface Specification Release 1 1 e EEE Standard for a High Performance Serial Bus IEEE Std 1394 1995 e IEEE Standard for a High Performance Serial Bus Amendment 1 IEEE Std 1394a 2000 e PC Card Standard Release 8 1 e PCI Bus Power Management Interface Specification Revision 1 1 e Serial Bus Protocol 2 SBP 2 e Serialized IRQ Support for PCI Systems e PCI Mobile Design Guide e PCI Bus Power Management Interface Specification for PCI to CardBus Bridges e PCI14xx Implementation Guide for D3 Wake Up e PCI to PCMCIA CardBus Bridge Register Description e Texas Instruments TPS2224 and TPS2226 product data sheet SLVS317 e Texas Instruments TPS2223A product data sheet SLVS428 e Texas Instruments TPS2228 product data sheet SLVS419 e PCI Local Bus Specification Revision 2 3 e PCMCIA Proposal 262 e The Multimedia Card System Specification Version 3 31 SD Memory Card Specifications SD Group March 2000 Memory Stick Format Specification Version 2 0 Memory Stick Pro ISO Sta
120. se gt A022 Ases se e ke eso ev no23 aco ows ea m ames s1 Aes a Ar a A aa AD25 acer oe em oe emn en moze vo ace m em ao ever co Ca eee Caos w ao o eas oo e e0 Cao we Ace ow eae we owe 5 Taso wi Acs ew ea7 7 aweios ae aos ue aos ou eae xis ose wn _ aano wie Ads leo ea ws ome ww 7 Cano ua Ace ao exo om owes wr aano us aor cw ean wie oes wo Tavs ao Ave coo eax wi aka wor amoo ria Avo cr ess es clock ws Taos wir ao on eam cw oma ps Mago ao aon aw eas ww ops wn _ Cam o Adie cw area ria vata nov Cas Ao ome sevo om Dever noe aaa e Ao CCA e AA Kaw cosas eel ter a er Table 2 3 16 Bit PC Card Signal Names Sorted Alphabetically Continued sana nawe owen SONAL Name nes SIONAL NAME Women name NUMBER e e w sow wo oso us eno o pa o so paro cor pans uw oo ms ece os so paro Hoo men wa ono comes me soomi coe reo wa Pano mo oes ura so parn so paw wie oo m career vo soome co or ve mua aa AA AA AP eno ko resta a soome ros voc Hoe eno kn a Ro sobra oa voc Hoo gt o o Rea uw sow tor ve Ho mua AA 00 ves em oa wo aso ro swag so vee mz maa a AN aw
121. selects the signaling mode for the PCI7x21 PCI7x11 host interrupt for card status changes This bit is encoded as 0 Host interrupt is edge mode default 1 Host interrupt is level mode Power down mode select When this bit is set to 1 the PCI7x21 PCI7x11 controller is in power down mode In power down mode the PCI7x21 PCI7x11 card outputs are placed in a high impedance state until an active cycle is executed on the card interface Following an active cycle the outputs are again placed in a high impedance state The PCI7x21 PCI7x11 controller still receives functional interrupts and or card status change interrupts however an actual card access is required to wake up the interface This bit is encoded as 0 Power down mode disabled default 1 Power down mode enabled E One or more bits in this register are cleared only by the assertion of GRST 5 21 ExCA I O Windows 0 and 1 Offset Address Low Byte Registers These registers contain the low byte of the 16 bit I O window offset address for I O windows 0 and 1 The 8 bits of these ici to the lower 8 bits of the offset address and bit 0 is a 0 7 dH windows 0 and EE offset address low zz ame Default Register ExCA I O window 0 offset address ae Offset CardBus Socket Address 836h Card A ExCA Offset 36h Card B ExCA Offset 76h Register ExCA I O window 1 offset address low byte Offset CardBus Socket Address 838h Card A ExCA Offset 38h Card B ExCA
122. state register offset 08h see Section 6 3 to be written When set this bit disables the socket power control 1 F3VCARD Force 5 V card Writes to this bit cause the 5VCARD bit in the socket present state register offset 08h see Section 6 3 to be written When set this bit disables the socket power control Force BadVccReq Changes to the BADVCCREQ bit in the socket present state register offset 08h see Section 6 3 can be made by writing this bit 0 F5VCARD FBADVCCREQ Force data lost Writes to this bit cause the DATALOST bit in the socket present state register offset FDATALOST 08h see Section 6 3 to be written Force not a card Writes to this bit cause the NOTACARD bit in the socket present state register offset 08h see Section 6 3 to be written N FNOTACARD This bit returns O when read Force CardBus card Writes to this bit cause the CBCARD bit in the socket present state register offset 08h see Section 6 3 to be written Force 16 bit card Writes to this bit cause the 16BITCARD bit in the socket present state register offset 08h see Section 6 3 to be written RSVD FCBCARD 4 F16BITCARD Force power cycle Writes to this bit cause the PWREVENT bit in the socket event register offset 00h see Section 6 1 to be written and the PWRCYCLE bit in the socket present state register offset 08h see Section 6 3 is unaffected Force CCD2 Writes to this bit cause the CD2EVENT bit in the
123. termination see reference schematics 24 576 MHz oscillator see implementation guide Pullup to Voc through 1 kQ resistor Tie to GND Float Pull directly to Vcc Tie to GND Tie to GND Tie to GND Float Table 2 16 SD MMC Terminals If any SD MMC terminal is unused then the terminal may be left ang CU Uu PU POWER EXTERNAL DESCRIPTION Ba INPUT OUTPUT RAIL COMPONENTS MC PWR CTRL 0 Power switch or Media card power control for flash media sockets LVCO1 FET to turn power MC PWR CTRL 1 on to FM socket SD MMC card detect This input is asserted when SD flash clock This output provides the SD MMC SD_CLK J05 G05 clock which operates at 16 MHz vo Tico Swe Voc SD flash command This signal provides the SD SDECNE i i command per the SD Memory Card Specifications NO Trea a Swe Voc SD_DAT3 J02 H05 SD_DAT2 J01 G03 SD flash data 3 0 These signals provide the SD SD_DAT1 Jo6 G02 data path per the SD Memory Card Specifications NO TAREE ne 9NG OS SD DATO H03 G01 SD write protect data This signal indicates that the eai media inserted in the socket is write protected KE a o mje Table 2 17 Memory Stick PRO Terminals If any Memory Stick PRO terminal is unused then the terminal may be left floating EA O PU POWER EXTERNAL DESCRIPTION TYPE INPUT OUTPUT PD RAIL COMPONENTS MC PWR CTRL 0 Power switch or Media card power control for flash media sockets LVCO1 FET to turn power MC PWR C
124. the functionality is shared between the CardBus registers and the ExCA registers software must not program the chip through both register sets when a CardBus card is functioning 3 7 3 Using Parallel IRQ Interrupts The seven multifunction terminals MFUNC6 MFUNCO implemented in the PCI7x21 PCI7x11 controller can be routed to obtain a subset of the ISA IRQs The IRQ choices provide ultimate flexibility in PC Card host interruptions To use the parallel ISA type IRQ interrupt signaling software must program the device control register PCI offset 92h see Section 4 39 to select the parallel IRQ signaling scheme See Section 4 36 Multifunction Routing Status Register for details on configuring the multifunction terminals A system using parallel IRQs requires at a minimum one PCI terminal INTA to signal CSC events This requirement is dictated by certain card and socket services software The INTA requirement calls for routing the MFUNCO terminal for INTA signaling The INTRTIE bit is used in this case to route socket interrupt events to INTA This leaves at a maximum six different IRQs to support legacy 16 bit PC Card functions As an example suppose the six IRQs used by legacy PC Card applications are IRQ3 IRQ4 IRQ5 IRQ9 IRQ10 and IRQ15 The multifunction routing status register must be programmed to a value of OA9F 5432h This value routes the MFUNCO terminal to INTA signaling and routes the remaining terminals as illustrated in Fig
125. the highest priority USE_INTx terminal that is asserted If bit 28 the tie all bit TIEALL in the system control register PCI offset 80h see Section 4 29 is set to 1 then the PCI7x21 PCI7x11 controller asserts the USE_INTA input to the Smart Card controller core If bit 28 TIEALL in the system control register PCI offset 80h see Section 4 29 is set to 0 then none of the USE_INTx inputs are asserted and the interrupt for the Smart Card function is selected by the INT_SEL bits in the Smart Card general control register et 7 6e 5 4 3 2 1 o Interrupt pin EAT moe 0 18 7 7 La Default o o o o o x x x Register Interrupt pin Offset 3Dh Type Read only Default OXh Table 13 7 PCI Interrupt Pin Register Uo o ona o o o o o oo n o o AA BY 13 15 Minimum Grant Register The minimum grant register contains the minimum grant value for the Smart Card controller core Register Minimum grant Offset 3Eh Type Read Update Default 00h Table 13 8 Minimum Grant Register Description FIELD NAME TYPE DESCRIPTION 7 0 MIN GNT RU Minimum grant The contents of this field may be used by host BIOS to assign a latency timer register value to the Smart Card controller The default for this register indicates that the Smart Card controller may need to sustain burst transfers for nearly 64 us and thus request a large value be programmed in bits 15 8 of the PC
126. the isochronous cycle timer register at OHCI offset FOh see Section 8 34 cycleSeconds field bits 31 25 and the cycleCount field bits 24 12 If bit 31 cycleMatchEnable is set to 1 then this isochronous transmit DMA context becomes enabled for transmits when the low order two bits of the isochronous cycle timer register at OHCI offset FOh cycleSeconds field bits 31 25 and the cycleCount field bits 24 12 value equal this field cycleMatch value Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software to stop descriptor processing The PCI7x21 PCI7x11 controller changes this bit only on a system hardware or software reset 14 13 RSVD Reserved Bits 14 and 13 return Os when read Software sets bit 12 to 1 to cause the PCI7x21 PCI7x11 controller to continue or resume descriptor processing The PCI7x21 PCI7x11 controller clears this bit on every descriptor fetch dead active RSVD 4 0 event mer RU Following an OUTPUT_LAST command the error code is indicated in this field Possible values are ack_complete evt_descriptor_read evt_data_read and evt_unknown The PCI7x21 PCI7x11 controller sets bit 11 to 1 when it encounters a fatal error and clears the bit when software clears bit 15 run to 0 The PCI7x21 PCI7x11 controller sets bit 10 to 1 when it is processing descriptors Reserved Bits 9 and 8 return Os when read This field in not meaningful for isochronous transmit contex
127. the time of the most recently received or sent cycleStart Table 8 34 Isochronous Receive Context Control Register Description Ml buffer When this bit is cleared each received packet is placed in a single buffer If bit 28 isochHeader When bit 30 is set to 1 received isochronous packets include the complete 4 byte isochronous packet When this bit is cleared the packet header is stripped from received isochronous packets The packet header if received immediately precedes the packet payload The value of this bit must not be changed while bit 10 active or bit 15 run is set to 1 8 41 BIT 29 28 Table 8 34 Isochronous Receive Context Control Register Description Continued FIELD NAME cycleMatchEnable multiChanMode TYPE RSCU RSC DESCRIPTION When bit 29 is set to 1 and the 13 bit cycleMatch field bits 24 12 in the isochronous receive context match register See Section 8 46 matches the 13 bit cycleCount field in the cycleStart packet the context begins running The effects of this bit however are impacted by the values of other bits in this register Once the context has become active hardware clears this bit The value of this bit must not be changed while bit 10 active or bit 15 run is set to 1 When bit 28 is set to 1 the corresponding isochronous receive DMA context receives packets for all isochronous channels enabled in the isochronous receive channel mask high register at OHCI offset
128. this field returns 00h when read 7 0 HEADER_TYPE PCI header type The SD host controller includes the standard PCI header Bit 7 indicates if the SD host is a multifunction device 12 6 12 8 SD Host Base Address Register The SD host base address register specifies the base address of the memory mapped interface registers for each standard SD host socket The size of each base address register BAR is 256 bytes The number of BARs is dependent on the number of SD sockets in the implementation See Table 12 7 for a complete description of the register contents SD host base address a O tasa es a RW Derun o o of fo ofjo ofof fo of fo ofo ofofo Bit 15 14 13 12 9 10 9 8 7 6 sh Pat st ata fo Name SD host base address Type RW RW RW RW RW R R R paa o opo tele pete pepe pepe pete pepe te Register SD host base address Offset 10h Type Read Write Read only Default 0000 0000h Table 12 7 SD host Base Address Register Description B FIELD NAME TYPE DESCRIPTION IT 31 8 BAR RW Base address This field specifies the upper 24 bits of the 32 bit starting base address The size of the base address is 256 bytes 7 4 RSVD R Reserved Bits 7 4 return Os when read 3 PREFETCHABLE Prefetchable indicator This bit is hardwired to O to indicate that the memory space is not prefetchable 2 1 TYPE This field is hardwired to 00 to indicate that the base address is located in 32 bit addre
129. to 1 for local bus node number 30 asynchronous requests received by the controller from that node are accepted 29 2 asynReqResourcen RSC Bits 29 through 2 asynReqResourcen where n 29 28 27 2 follow the same pattern as bits 31 and 30 1 asynReqResource1 RSC If bit 1 is set to 1 for local bus node number 1 asynchronous requests received by the controller from that node are accepted asynReqResource0 RSC If bit O is set to 1 for local bus node number 0 asynchronous requests received by the controller from that node are accepted 8 34 8 37 Physical Request Filter High Register The physical request filter high set clear register enables physical receive requests on a per node basis and handles the upper node IDs When a packet is destined for the physical request context and the node ID has been compared against the ARRQ registers then the comparison is done again with this register If the bit corresponding to the node ID is not set to 1 in this register then the request is handled by the ARRQ context instead of the physical request context The node ID comparison is done if the source node is on the same bus as the PCI7x21 PCI7x11 controller Nonlocal bus sourced packets are not acknowledged unless bit 31 in this register is set to 1 See Table 8 29 for a complete description of the register contents 26 25 24 23 22 21 20 19 18 17 16 Name Physical request filter high Fo o o oo o o o lololo lolol oloo CO
130. to the software card detect interrupt bit has no effect This bit is write only A read operation of this bit always returns 0 Writing a 1 to this bit also clears it If bit 2 of the ExCA global control register ExCA offset 81Eh see Section 5 20 is set and a 1 is written to clear bit 3 of the ExCA card status change interrupt register then this bit also is cleared CDRESUME RW RSVD R These bits return Os when read Writes have no effect Register configuration upon card removal This bit controls how the ExCA registers for the socket react to a card removal event This bit is encoded as 1 REGCONFIG RW 0 No change to ExCA registers upon card removal default 1 Reset ExCA registers upon card removal o RSVD R This bit returns 0 when read A write has no effect t One or more bits in this register are cleared only by the assertion of GRST when PME is enabled If PME is not enabled then this bit is cleared by the assertion of PRST or GRST Card detect resume enable If this bit is set to 1 and a card detect change has been detected on the CD1 and CD2 inputs then the RI OUT output goes from high to low The RI OUT remains low until the card status change bit in the ExCA card status change register ExCA offset 804h see Section 5 5 is cleared If this bit is a 0 then the card detect resume functionality is disabled 0 Card detect resume disabled default 1 Card detect resume enabled 5 21 5 20 ExCA Global C
131. unaffected by bus reset Enab multi 1 R W Enable multispeed concatenated packets This bit enables the PHY layer to transmit concatenated packets of differing speeds in accordance with the protocols defined in IEEE Std 1394a 2000 This bit is cleared to 0 by system hardware reset and is unaffected by bus reset Page_Select 3 R W Page Select This field selects the register page to use when accessing register addresses 8 through 15 This field is cleared to 0 by a system hardware reset and is unaffected by bus reset Port_Select 4 R W Port_Select This field selects the port when accessing per port status or control for example when one of the port status control registers is accessed in page 0 Ports are numbered starting at 0 This field is cleared to 0 by system hardware reset and is unaffected by bus reset 10 3 10 2 Port Status Register The port status page provides access to configuration and status information for each of the ports The port is selected by writing O to the Page Select field and the desired port number to the Port Select field in base register 7 Table 10 3 shows the configuration of the port status page registers and Table 10 4 shows the corresponding field descriptions If the selected port is not implemented all registers in the port status page are read as 0 Table 10 3 Page 0 Port Status Register Configuration BIT POSITION po IIA ADDRESS o 1 2 3 5 6 7 Reserved 1011 Reserved
132. with a 2 7 kQ resistor typically 2 7 kQ Otherwise it must be pulled low to ground with a 220 Q resistor Serial data This terminal is implemented as A F Pullup resistor per open drain and for normal operation a ROM is 2 ESO h A F A 1 C specification implemented in the design this terminal must be vo Tru ttLot value depends on Tie to GND if not pulled high to the ROM Vpp with a 2 7 kQ resistor EEBRON using EEPROM Otherwise it must be pulled low to ground with a typicall 27 kQ 220 0 resistor ypIca y Speaker output SPKROUT is the output to the host system that can carry SPKR or CAUDIO through the 7 d a e SPKROUT controller from the PC Card interface SPKROUT is TILO1 TOKAN ATRA NG GAT Ka ee pulldown resistor pulldown resistor driven as the exclusive OR combination of card SPKR CAUDIO inputs Suspend SUSPEND protects the internal registers SUSPEND from clearing when the GRST or PRST signal is PCIIG 10 kQ to 47 kQ 10 kQ to 47 kQ asserted See Section 3 8 6 Suspend Mode for pullup resistor pullup resistor details Terminal TESTO is used for factory test of the TESTO controller and must be connected to ground for 1 0 LVCI1 Tie to GND normal operation Table 2 10 16 Bit PC Card Address and Data Terminals External components are not applicable for the 16 bit PC Card address and data terminals If any 16 bit PC Card address and data terminal is unused then the terminal may be left floating
133. writing 7 to the Page Select field in base register 7 Table 10 7 shows the configuration of the vendor dependent page and Table 10 8 shows the corresponding field descriptions Table 10 7 Page 7 Vendor Dependent Register Configuration BIT POSITION 1001 Reserved for test 1010 Reserved for test 1011 Reserved for test 1100 Reserved for test 1101 Reserved for test 1110 Reserved for test 1111 Reserved for test Table 10 8 Page 7 Vendor Dependent Register Field Descriptions FIELD SIZE TYPE DESCRIPTION NPA 1 RW Null packet actions flag This bit instructs the PHY layer to not clear fair and priority requests when a null packet is received with arbitration acceleration enabled If this bit is set to 1 fair and priority requests are cleared only when a packet of more than 8 bits is received ACK packets exactly 8 data bits null packets no data bits and malformed packets less than 8 data bits do not clear fair and priority requests If this bit is cleared to O fair and priority requests are cleared when any non ACK packet is received including null packets or malformed packets of less than 8 bits This bit is cleared to 0 by system hardware reset and is unaffected by bus reset Link_Speed 2 RW Link speed This field indicates the top speed capability of the attached LLC Encoding is as follows Code Speed 00 100 01 200 10 400 11 illegal This field is replicated in the sp field of the self ID packet to indicate
134. 0 0 L06 8 07 AD4 AD5 AD9 oo aon Pao ao ao MIC MC ME aa oro nao ana VEZ o ana anas anas apa Manas Anao ao MVE IEC MC aano o NC MN MEX MEX MEX acana conos 2 9 Table 2 2 CardBus PC Card Signal Names Sorted Alphabetically Continued Sionat name Women SNL NAWE Wimpern name NuMBER o e w7 ow wo ons us oao o n o so paro cor pans uw oa ms ox os so paro Hoo men wa o eones me soomi co reo wa o mo oes ur so parn so tre wie oo m eones ve soome co or vie oa o e ve AA TROY roe oo ko resta mr soome Hs veo Hoe eno m past mos oom oa voc Hoo gt o o Rea uw sow tor veo Ho mua AA 00 ves em oa wo aso ro swag so vee mz maa a AN aw a a smc r07 we oa we so we soe o vo Car w o o mo o vo Kz erst m soak ws smm co voc m7 osa ws scam o smo co voc mo mov ow sre o smo vos voc mo me o sc mos so smo vos veo mz mc ewr cro eon somos s swos so vec Nor Mc Pwe orata Fo scemo s smo wl voca as menco no somos s smo s voca m mewn vw somos s Swecwe co voos bw gt mence Po somos os SPS WP Ko voos Ko menco Po sccpios ro swag Ko voo w
135. 00 0 cece cece 4 7 4 10 Header Type Register wuss oc scctveescuateesgecetedeecee paga cer 4 7 4 11 BIST Register ja pusceud rine eevee NPGA NBA LUKE oie eens vexcdue ee 4 7 4 12 CardBus Socket Registers ExCA Base Address Register 4 8 4 13 Capability Pointer Register 0 a 4 8 4 14 Secondary Status Register cee ee eee 4 9 4 15 PCI Bus Number Register 0d id ria 4 10 4 16 CardBus Bus Number Register a 4 10 4 17 Subordinate Bus Number Register a 4 10 4 18 CardBus Latency Timer Register cee eee eee 4 11 4 19 CardBus Memory Base Registers 0 1 A A 4 11 4 20 CardBus Memory Limit Registers 0 1 o oooooomooooo 4 12 4 21 CardBus I O Base Registers 0 1 aa 4 12 4 22 CardBus I O Limit Registers 0 1 0 e eee eee eee 4 13 4 23 Interrupt Line Register lt cimsio soriana ede ree a dedos 4 13 4 24 Interrupt Pin Register 0 002 paaa cae ce eevee eee ieessaases 4 14 4 25 Bridge Control Register ccoo iia cad 4 15 4 26 Subsystem Vendor ID Register cece eee eee eee 4 16 4 27 Subsystem ID Register 2 24 25 sivtebiaceddhectaebaeed recede rs 4 17 4 28 PC Card 16 Bit I F Legacy Mode Base Address Register 4 17 429 System Control Register ociiaocvrn cir reeds ees 4 18 4 30 MC CD Debounce Register 0 0 cee eee eee eee 4 20 4 31 General Control Register costes verde cdeweterte
136. 000 CAUDPWM 1100 RI OUT Mega MFUNGE oR 0001 GPO2 0101 IRQS 1001 FM_LED 1101 TEST_MUX 0010 PCREQ 0110 RSVD 1010 IRQ10 1110 GPE 0011 IRQ3 0111 RSVD 1011 INTC 1111 IRQ7 0001 GPO3 0101 SC_DBG_TX 1001 IRQ9 1101 LED_SKT These bits are cleared only by the assertion of GRST RW RW RW RW Ww 4 26 Table 4 14 Multifunction Routing Status Register Description Continued Multifunction terminal 1 configuration These bits control the internal signal mapped to the MFUNC1 terminal as follows 0000 GPI1 0100 OHCI LED 1000 CAUDPWM 1100 LEDA1 e95 MFUNCI RW o 0t GPO1 0101 IRQ5 1001 IRQ9 1101 LEDA2 0010 INTB 0110 RSVD 1010 IRQ10 1110 GPE 0011 IRQ3 0111 RSVD 1011 IRQ11 1111 IRQ15 Multifunction terminal 0 configuration These bits control the internal signal mapped to the MFUNCO terminal as follows 0000 GPIO 0100 IRQ4 1000 CAUDPWM 1100 LEDA1 3 0 MFUNCO RW 0001 GPO0 0101 IRQ5 1001 IRQ9 1101 LEDA2 0010 INTA 0110 RSVD 1010 IRQ10 1110 GPE 0011 IRQ3 0111 RSVD 1011 IRQ11 1111 IRQ15 These bits are cleared only by the assertion of GRST 4 37 Retry Status Register The contents of the retry status register enable the retry time out counters and display the retry expiration status The flags are set when the PCI7x21 PCI7x11 controller as a master receives a retry and does not retry the request within 215 clock cycles The flags are
137. 000000000 000 000 000 000 000 O 000 000 000 660 000 000 000 O 000 000 000 000 000 0000000000 O O O O O 7 9 1 13 15 17 19 8 10 12 14 16 18 0 95 Bottom View 0 85 1 40 MAX A1 Corner WVUUUUUUUUUUUUUUUUU 0 55 0 45 Z 0 08 0 45 c 0 12 0 35 L y F Seating Plane ji 4145273 4 E 08 02 NOTES B All linear dimensions are in millimeters C This drawing is subject to change without notice D MicroStar BGA configuration MicroStar BGA is a trademark of Texas Instruments 15 1 15 2 KG Texas PACKAGE OPTION ADDENDUM INSTRUMENTS www ti com 18 Oct 2005 PACKAGING INFORMATION Orderable Device Status Y Package Package Pins Package Eco Plan Lead Ball Finish MSL Peak Temp Type Drawing Qty PC17411GHK ACTIVE BGA GHK 288 1 TBD Call TI Level 3 220C 168 HR PC17411ZHK ACTIVE BGA MI ZHK 288 1 Green RoHS amp Call TI Level 3 260C 168HRS CROSTA no Sb Br R PC17421GHK ACTIVE BGA GHK 288 90 TBD Call TI Level 3 220C 168 HR PCI7421ZHK ACTIVE BGA MI ZHK 288 90 Green RoHS amp Call TI Level 3 260C 168HRS CROSTA no Sb Br R PC17611GHK ACTIVE BGA GHK 288 90 TBD Call TI Level 3 220C 168 HR PC17611ZHK ACTIVE BGA MI ZHK 288 90 Green RoHS amp Call TI Level 3 260C 168HRS CROSTA no Sb Br R PC17621GHK ACTIVE BGA GHK 288 90 TBD Call TI Level 3 220C 168 HR PC17621ZHK ACTIVE BGA MI ZHK 288 90 Green RoHS amp Call TI Level 3 260C 168H
138. 1 controller to claim any memory transactions through CardBus memory windows i e these windows by default are not enabled to pass the first 4 Kbytes of memory to CardBus 31 30 28 27 26 25 24 23 22 21 20 19 18 17 15 Name Memory base registers 0 1 Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW Memory base registers 0 1 O coe cee DEA oom E Deau o o o of of of ofoftoftoftotTototofotfo Register Memory base registers 0 1 Offset 1Ch 24h Type Read only Read Write Default 0000 0000h 4 11 4 20 CardBus Memory Limit Registers 0 1 These registers indicate the upper address of a PCI memory address range They are used by the PCI7x21 PCI7x11 controller to determine when to forward a memory transaction to the CardBus bus and likewise when to forward a CardBus cycle to PCI Bits 31 12 of these registers are read write and allow the memory base to be located anywhere in the 32 bit PCI memory space on 4 Kbyte boundaries Bits 11 0 are read only and always return Os Writes to these bits have no effect Bits 8 and 9 of the bridge control register PCI offset 3Eh see Section 4 25 specify whether memory windows 0 and 1 are prefetchable or nonprefetchable The memory base register or the memory limit register must be nonzero in order for the PCI7x21 PCI7x11 controller to claim any memory transactions through CardBus memory windows i e these windows by default are not enabled to pa
139. 1 for local bus node number 42 physical requests received by the controller from that node are handled through the physical request context 9 physReqResource41 RSC If bit 9 is set to 1 for local bus node number 41 physical requests received by the controller from that node are handled through the physical request context 8 physReqResource40 RSC If bit 8 is set to 1 for local bus node number 40 physical requests received by the controller from that node are handled through the physical request context 7 physReqResource39 RSC If bit 7 is set to 1 for local bus node number 39 physical requests received by the controller from that node are handled through the physical request context 6 physReqResource38 RSC If bit 6 is set to 1 for local bus node number 38 physical requests received by the controller from that node are handled through the physical request context 5 physReqResource37 RSC If bit 5 is set to 1 for local bus node number 37 physical requests received by the controller from that node are handled through the physical request context 4 physReqResource36 RSC If bit 4 is set to 1 for local bus node number 36 physical requests received by the controller from that node are handled through the physical request context 3 physReqResource35 RSC If bit 3 is set to 1 for local bus node number 35 physical requests received by the controller from that node are handled through the physical request context 2 physReqResource34 RSC If bit 2 is se
140. 13 MFUNC1 B_CAD3 8_D5 B_CAD8 8_D15 B_CAD7 8_D7 B_CAD9 IB_A10 B CET B_CC BEO ISPKROUT B_CAD15 BTOWR B CAD13 BIORD B CAD12 IB A11 B CAD11 B_0E SM_R B SM_PHYS WP RSVD RSVD B_CPAR IB_A13 8_A8 B_CC BET B_RSVD B A18 B CAD16 18_A17 B_CAD14 IB_AQ SD_DAT2 ISM_D6 SD_DAT3 SM D7 SD CMD SM ALE SD CLK SMURE SD DAT1 SM D5 SM CLE B CIRDY 1B A15 BZCGNT B_WE IB_A20 B_A14 B CSTOP B CPERR IB_A19 VR_ PORT VR_EN SD_DATO SM_D4 IMS_DATA3 SD_DAT3 SM_D3 SD WP VCC VCC VCC VCC GND B_CAD19 IB_A25 B CAD18 IB_A7 IB_A22 B CTADY B_CCLK 18_A16 B_CDEVSEL B A21 MS SDIO DATAO SD_DATO SM_DO MS_DATA1 SD_DAT1 SM D1 MS DATA2 SD_DAT2 SM D2 MS CLK SD CLK A CAD20 IA_A6 A_CPAR A_A13 A CAD14 IA_A9 A_CC BEQ IIA CET GND B_CAD21 IB_AS B_CAD17 IB_A24 1 B A12 B_CC BE4B_CFRAME B A23 MC PWR _CTRL_O MC_PWR _CTRL_1 MS_BS SD_CMD ISM_WE MS_CD A_A12 lA_CC BE2 A CPERR A_A14 A_CAD6 1A D13 B_CSTSCHG B BVD1 STSCHG RI B CC BE3 B REG B CAD20 B RESET B AG B_CVS2 1 B S2 A_CCLK 1A A16 1A A19 A CAD15 IKIOWR A CAD8 A_D15 A_CADO A_D3 A_CAD31 A_Dt0 A_RSVD JIA_D2 B_CAD23
141. 21 PCI7x11 Vay x implementation and may be configured by using bit 4 D3_COLD in the general control register see Section 11 21 PME support This 4 bit field indicates the power states from which the flash media interface may PME_SUPPORT assert PME This field returns a value of 1111b by default indicating that PME may be asserted from the D3pgt D2 D1 and DO power states D2 support Bit 10 is hardwired to 1 indicating that the flash media controller supports the D2 power D2 SUPPORT stat D1 support Bit 9 is hardwired to 1 indicating that the flash media controller supports the D1 power D1_SUPPORT state Auxiliary current This 3 bit field reports the 3 3 VaUx auxiliary current requirements When bit 15 PME_D3COLD is cleared this field returns 000b otherwise it returns 001b 000b Self powered 001b 55 mA 3 3 VAyx maximum current required AUX_CURRENT Device specific initialization This bit returns 0 when read indicating that the flash media controller does not require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it Reserved Bit 4 returns 0 when read PME clock This bit returns 0 when read indicating that the PCI clock is not required for the flash media controller to generate PME PME_CLK Power management version This field returns 010b when read indicating that the flash media PM_VERSION controller is compatible with the r
142. 3 12 14 12 15 12 16 12 17 13 1 13 2 13 3 13 4 13 5 13 6 13 7 13 8 13 9 13 10 13 11 13 12 13 13 13 14 Title Page Latency Timer and Class Cache Line Size Register Description 11 5 Header Type and BIST Register Description 11 6 Flash Media Base Address Register Description 11 6 PCI Interrupt Pin Register vox a nakaw KAEN GANG e 11 8 Minimum Grant Register Description a 11 9 Maximum Latency Register Description ooooooooo 11 9 Capability ID and Next Item Pointer Registers Description 11 10 Power Management Capabilities Register Description 11 11 Power Management Control and Status Register Description 11 12 General Control Register oooooccocooccccocncnr 11 13 Subsystem Access Register Description 11 14 Diagnostic Register Description aa 11 15 Function 4 Configuration Register Map cece ee eae 12 1 Command Register Description 22 waaa 8 Ka kk KPA KA PAG ese pes veer 12 3 Status Register Description 27 c cte2stiecc td h ak AA GA kada KALA 12 4 Class Code and Revision ID Register Description 12 5 Latency Timer and Class Cache Line Size Register Description 12 6 Header Type and BIST Register Description 12 6 SD host Base Address Register Description 12 7 PCI Interrup
143. 3 10 caused the interrupt Internal registers in the PCI7x21 PCI7x11 controller provide flags that report the source of an interrupt By reading these status bits the interrupt service routine can determine the action to be taken Table 3 10 details the registers and bits associated with masking and reporting potential interrupts All interrupts can be masked except the functional PC Card interrupts and an interrupt status flag is available for all types of interrupts Notice that there is not a mask bit to stop the PCI7x21 PCI7x11 controller from passing PC Card functional interrupts through to the appropriate interrupt scheme These interrupts are not valid until the card is properly powered and there must never be a card interrupt that does not require service after proper initialization Table 3 10 lists the various methods of clearing the interrupt flag bits The flag bits in the ExCA registers 16 bit PC Card related interrupt flags can be cleared using two different methods One method is an explicit write of 1 to the flag bit to clear and the other is by reading the flag bit register The selection of flag bit clearing methods is made by bit 2 IFCMODE in the ExCA global control register ExCA offset 1Eh 5Eh 81Eh see Section 5 20 and defaults to the flag cleared on read method The CardBus related interrupt flags can be cleared by an explicit write of 1 to the interrupt flag in the socket event register see Section 6 1 Although some of
144. 3 is not implemented in the controller this bit is a read only 0 18 EMVIF_EN_SKT2 RW Socket 2 EMV interface enable Since socket 2 is not implemented in the controller this bit is a read only 0 17 EMVIF_EN_SKT1 RW Socket 1 EMV interface enable When this bit is set to 1 the internal EVM interface for socket 1 is enabled 16 EMVIF_EN_SKTO RW Socket 0 EMV interface enable When this bit is set to 1 the internal EVM interface for socket 0 is enabled GPIO_EN_SKT3 R Socket 3 GPIO enable Since socket 3 is not implemented in the controller this bit is a read only 0 GPIO_EN_SKT2 RW Socket 2 GPIO enable Since socket 2 is not implemented in the controller this bit is a read only 0 GPIO_EN_SKT1 RW Socket 1 GPIO enable When this bit is set to 1 the SC_GPIOSs for socket 1 are enabled 12 GPIO EN SKTO RW Socket 0 GPIO enable When this bit is set to 1 the SC_GPIOs for socket O are enabled 11 PCMCIA_MODE_SKT3 R Socket 3 PCMCIA mode Since socket 3 is not implemented in the controller this bit is a read only 0 10 PCMCIA_MODE_SKT2 R Socket 2 PCMCIA mode Since socket 2 is not implemented in the controller this bit is a read only 0 9 PCMCIA_MODE_SKT1 R Socket 1 PCMCIA mode Since socket 1 is implemented as a dedicated socket in the controller this bit returns 1 when read PCMCIA_MODE_SKTO R Socket 0 PCMCIA mode Since socket 0 is implemented as a dedicated socket in the controller this bit returns 1 when read 7 PME_SUPPORT_SKT3 R Socket 3 PME support
145. 4 29 is set to 0 then none of the USE_INTx inputs are asserted and the interrupt for the SD host controller function is selected by the INT_SEL bits in the SD host general control register ge 7 6e 5 4 a 2 1 o Interrupt pin Name me R a 1 a 2 e 4 FF petan o0 o o o o x x x Register Interrupt pin Offset 3Dh Type Read only Default OXh Table 12 8 PCI Interrupt Pin Register Uo o on o o aano o o om n o oo 12 14 Minimum Grant Register The minimum grant register contains the minimum grant value for the SD host controller core Name Minimum grant Dea o o o o o 1 fs 1 Register Minimum grant Offset 3Eh Type Read Update Default 07h Table 12 9 Minimum Grant Register Description FIELD NAME TYPE DESCRIPTION 7 0 MIN_GNT RU Minimum grant The contents of this field may be used by host BIOS to assign a latency timer register value to the SD host controller The default for this register indicates that the SD host controller may need to sustain burst transfers for nearly 64 us and thus request a large value be programmed in bits 15 8 of the PCI7x21 PCI7x11 latency timer and class cache line size register at offset OCh in the PCI configuration space see Section 12 6 12 9 12 15 Maximum Latency Register The maximum latency register contains the maximum latency value for the SD host controller core Maximum latency
146. 400 operation 0 315 Receive input skew Between TPA and TPB cable inputs 200 operation ns TA Operating ambient temperature range 0 25 70 TJ Virtual junction temperature 0 25 115 t Applies to external inputs and bidirectional buffers without hysteresis Miscellaneous terminals are A03 B17 C15 C18 E05 E08 F19 HO3 JO1 J02 JO3 J05 JO6 J07 L02 L03 L05 MO1 MO2 M03 NO1 NO2 N13 P12 P15 R02 R17 T01 A_CCDx A CDx A CVSx A VSx B CCDx B CDx B CVSx B VSx SD DATO SD DAT2 SD DAT3 SD CMD SD CLK SD DAT1 SM CLE SC CD SC OC SC PWR CTRL CLK 48 SDA SCL DATA LATCH TESTO CNA SUSPEND PHY TEST MA and GRST terminals Applies to external output buffers T For a node that does not source power see Section 4 2 2 2 in IEEE Std 1394a 2000 These junction temperatures reflect simulation conditions The customer is responsible for verifying junction temperature AMFUNC 0 6 share the same specifications as the PCI terminals 14 3 14 3 Electrical Characteristics Over Recommended Operating Conditions unless otherwise noted O PARAWETER TERWALS OPERATION TEST CONDITIONS WiN AX UNT IOH 4 MA Vcoc 0 6 3 3 V loL 1 5 mA 0 1 VCC Miscellaneous PCI 5V loL 6 mA 0 55 3 3 V CardBus lo 0 7 mA 3 3 V 16 bit loL 0 7 mA 0 4 0 1 Vcc VoL Low level output voltage PC Card Vi Miscellaneous 3 state output high impedance Output terminals loz High
147. 7 16 Name VO limitregstes o TN O mann Po fofofofofofofofofofofofofofofo e Pe Dee De tet terete Rw Rw aw ew Aw aw oA R pean o o o fo fo fo fofofofofoftofofofof x Register I O limit registers 0 1 Offset 30h 38h Type Read only Read Write Default 0000 000Xh 4 23 Interrupt Line Register The interrupt line register is a read write register used by the host software As part of the interrupt routing procedure the host software writes this register with the value of the system IRQ assigned to the function 7 jae Se E O A A ee Name fo a Den A P f Register Interrupt line Offset 3Ch Type Read Write Default FFh 4 13 4 24 Interrupt Pin Register The value read from this register is function dependent The default value for function 0 is 01h INTA the default value for function 1 is 02h INTB the default value for function 2 is 03h INTC the default value for function 3 is 01h INTA the default value for function 4 is 01h INTA the default value for function 5 is 01h INTA The value also depends on the values of bits 28 the tie all bit TIEALL and 29 the interrupt tie bit INTRTIE in the system control register PCI offset 80h see Section 4 29 The INTRTIE bit is compatible with previous TI CardBus controllers and when set to 1 ties INTB to INTA internally The TIEALL bit ties INTA INTB INTC and INTD together internally The internal inte
148. 7 10 Subsystem Identification Register Description BIT FIELDNAME TYPE DESCRIPTION 31 16 OHCI_SSID RU Subsystem device ID This field indicates the subsystem device ID 15 0 OHCI_SSVID RU Subsystem vendor ID This field indicates the subsystem vendor ID These bits are cleared only by the assertion of GRST 7 13 Power Management Capabilities Pointer Register The power management capabilities pointer register provides a pointer into the PCI configuration header where the power management register block resides The PCI7x21 PCI7x11 configuration header doublewords at offsets 44h and 48h provide the power management registers This register is read only and returns 44h when read z7 e 5 a 3 a Name Power management capabilities pointer mwe rR rR R R R R R R Detaut o 1 o o o 1 o Register Power management capabilities pointer Offset 34h Type Read only Default 44h 7 9 7 14 Interrupt Line Register The interrupt line register communicates interrupt line routing information See Table 7 11 for a complete description of the register contents a line Nono Default Register Interrupt line Offset 3Ch Type Read Write Default FFh Table 7 11 Interrupt Line Register Description FIELD NAME TYPE DESCRIPTION 7 0 INTR LINE RW Interrupt line This field is programmed by the system and indicates to software which interrupt line the F P
149. 8 lists the registers used to program a serial bus device through software Table 3 8 PCI7x21 PCI7x11 Registers Used to Program Serial Bus Devices PCI OFFSET REGISTER NAME DESCRIPTION Serial bus data Contains the data byte to send on write commands or the received data byte on read commands Bih Serial bus iridex The content of this register is sent as the word address on byte writes or reads This register is not used in the quick command protocol Serial bus slave Write transactions to this register initiate a serial bus transaction The slave device address and the B2h _ address R W command selector are programmed through this register Serial bus control Read data valid general busy and general error status are communicated through this register In B3h os as a and status addition the protocol select bit is programmed through this register 3 6 3 Serial Bus Interface Protocol The SCL and SDA signals are bidirectional open drain signals and require pullup resistors as shown in Figure 3 4 The PCI7x21 PCI7x11 controller which supports up to 100 Kb s data transfer rate is compatible with standard mode I2C using 7 bit addressing All data transfers are initiated by the serial bus master The beginning of a data transfer is indicated by a start condition which is signaled when the SDA line transitions to the low state while SCL is in the high state as shown in Figure 3 7 The end of a requested data transfer is indicated
150. 9 3 Link Enhancement Register Description FIELD NAME TYPE DESCRIPTION 31 16 RSVD R Reserved Bits 31 16 return Os when read dis at pipeline KA AT pipelining When bit 15 is set to 1 out of order AT pipelining is disabled The default value for this RSVD R Reserved Bit 14 defaults to O and must remain 0 for normal operation of the OHCI core This field sets the initial AT threshold value which is used until the AT FIFO is underrun When the PCI7x21 PCI7x11 controller retries the packet it uses a 2K byte threshold resulting in a store and forward operation 00 Threshold 2K bytes resulting in a store and forward operation 01 Threshold 1 7K bytes default 10 Threshold 1K bytes 11 Threshold 512 bytes These bits fine tune the asynchronous transmit threshold For most applications the 1 7K byte threshold is optimal Changing this value may increase or decrease the 1394 latency depending on the average PCI bus latency 13 12 atx thresh RW Setting the AT threshold to 1 7K 1K or 512 bytes results in data being transmitted at these thresholds or t when an entire packet has been checked into the FIFO If the packet to be transmitted is larger than the AT threshold then the remaining data must be received before the AT FIFO is emptied otherwise an underrun condition occurs resulting in a packet error at the receiving node As a result the link then commences a store and forward operation It waits until it has the comp
151. 9 TEXAS INSTRUMENTS PCI7621 PCI761 1 PCI7421 PCI7411 Dual Single Socket CardBus and UltraMedia Controller With Integrated 1394a 2000 OHCI Two Port PHY Link Layer Controller With Dedicated Flash Media Socket Data Manual June 2004 Connectivity Solutions SCPS081 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment Tl warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operat
152. A memory window 1 start address high byte Offset CardBus Socket Address 819h Card A ExCA Offset 19h Card B ExCA Offset 59h Register ExCA memory window 2 start address high byte Offset CardBus Socket Address 821h Card A ExCA Offset 21h Card B ExCA Offset 61h Register ExCA memory window 3 start address high byte Offset CardBus Socket Address 829h Card A ExCA Offset 29h Card B ExCA Offset 69h Register ExCA memory window 4 start address high byte Offset CardBus Socket Address 831h Card A ExCA Offset 31h Card B ExCA Offset 71h Type Read Write Default 00h en 5 11 ExCA Memory Windows 0 4 Start Address High Byte Registers Description SIGNAL FUNCTION This bit controls the memory window data width This bit is encoded as DATASIZE 0 Window data width is 8 bits default 1 Window data width is 16 bits Zero wait state This bit controls the memory window wait state for 8 and 16 bit accesses This wait state timing emulates the ISA wait state used by the 82365SL DF This bit is encoded as ZEROWAIT 0 8 and 16 bit cycles have standard length default 1 8 bit cycles reduced to equivalent of three ISA cycles 16 bit cycles reduced to the equivalent of two ISA cycles SCRATCH Scratch pad bits These bits have no effect on memory window operation Start address high nibble These bits represent the upper address bits A23 A20 of the memory window STAHN start address 5 15 ExCA Memory Windows 0 4 End Addr
153. A to EO E EA E AAA EE EA E a A AA A A O CO CIO CO O CIO CO IO IO CIO CI CS CE CA CE Register Smart Card configuration 1 Offset 58h Type Read Write Read only EEPROM GRST only Default 0374 3307h 13 15 Table 13 15 Smart Card Configuration 1 Register Description FIELD NAME TYPE DESCRIPTION 31 28 SCRTCH_PAD RW Scratch pad 27 CLASS B SKT3 R Socket 3 Class B Smart Card support Since socket 3 is not implemented in the controller this bit is a read only 0 26 CLASS B SKT2 RW Socket 2 Class B Smart Card support Since socket 2 is not implemented in the controller this bit is a read only 0 25 CLASS B SKT1 RW Socket 1 Class B Smart Card support When this bit is set to 1 socket 1 supports Class B Smart Cards 24 CLASS B SKTO RW Socket 0 Class B Smart Card support When this bit is set to 1 socket O supports Class B Smart Cards 23 CLASS A SKT3 R Socket 3 Class A Smart Card support Since socket 3 is not implemented in the controller this bit is a read only 0 22 CLASS A SKT2 RW Socket 2 Class A Smart Card support Since socket 2 is not implemented in the controller this bit is a read only 0 21 CLASS A SKT1 RW Socket 1 Class A Smart Card support When this bit is set to 1 socket 1 supports Class A Smart Cards 20 CLASS A SKTO RW Socket 0 Class A Smart Card support When this bit is set to 1 socket 0 supports Class A Smart Cards 19 EMVIF_EN_SKT3 R Socket 3 EMV interface enable Since socket
154. ATARAN RW a PERR was asserted by any PCI device including the PCI7x21 PCI7x11 controller b The PCI7x21 PCI7x11 controller was the bus master during the data parity error c The parity error response bit is set in the command register Fast back to back capable The PCI7x21 PCI7x11 controller cannot accept fast back to back transactions TA FBB CAP AA F thus this bit is hardwired to 0 UDF UDF supported The PCI7x21 PCI7x11 controller does not support user definable features therefore this bit is hardwired to 0 5 66MHZ 66 MHz capable The PCI7x21 PCI7x11 controller operates at a maximum PCLK frequency of 33 MHz therefore this bit is hardwired to 0 t This bit is cleared only by the assertion of GRST 4 5 Table 4 4 Status Register Description continued SIGNAL TYPE FUNCTION Capabilities list This bit returns 1 when read This bit indicates that capabilities in addition to standard PCI 4 CAPLIST R capabilities are implemented The linked list of PCI power management capabilities is implemented in this function 2 0 Interrupt status This bit reflects the interrupt status of the function Only when bit 10 INT_DISABLE in the INT_STATUS RU command register PCI offset 04h see Section 4 4 is a O and this bit is a 1 is the function s INTx signal asserted Setting the INT_DISABLE bit to a 1 has no effect on the state of this bit RSVD R Reserved These bits return Os when read 4 6 Revision ID Register
155. B CAD15 B_IOWR B_CAD13 BIORD B_CAD12 IB_A11 B_CAD11 BOE SM R B SC RFU SM_PHYS WP SC_FCB SC_RST SC_CLK SC_VCC 5V B_CPAR IB_A13 B_CC BET IB_A8 B_RSVD IB_A18 B CAD16 18_A17 B_CAD14 IB_AQ SD_DAT2 ISM_D6 SC_GPIO4 SD DAT3 SM_D7 SC_GPIO3 SD CMD SM ALE SC GPI02 SD CLK SM RE SC GPIO1 SD DAT1 SM D5 SC_GPIO5 SM_CLE SC_GPIOO B_CIRDY 18_A15 B_CSTOP B_CPERR B_A20 B_A14 8_A19 VR_ PORT VR_EN ISD_DATO SM_D4 ISC GPIO8 IMS_DATA3 SD DAT3 SM D3 SD WP VCC VCC VCC B_CAD19 GND B_A25 BLCTRDY IB_A22 B_CCLK IB_A16 B CDEVSEL 1 B A21 MS SDIO DATAO SD DATO sM Do MS DATA1 SD_DAT1 SM D1 MS DATA2 SD DAT2 SM D2 MS CLK SD CLK A CAD20 A_A6 A_CPAR 1A A13 A CAD14 A_A9 B_CAD17 18_A24 B_A12 B_CC BEAB CFRAME 8_A23 MC_PWR _CTRL_O MC_PWR _CTRL_1 MS_BS SD CMD SN_WE MS CD SM CD lA_CC BEZ 1A A12 ACPERR 1A A14 A_D13 B_CSTSCHG B_BVD1 STSCHG AT B_CRS B_RESET B_CAD20 B_AG B_CVS2 SD_CD ACCD2 AZCD2 A_CAD24 1A A2 A CVs2 IIA NSZ A_CCLK 1A A16 A CBLOCKA CAD15 IA A19 A_IOWR A CAD8 A_D15 A_CADO A_D3 A_CAD31 A_D10 A_D2 A_CAD29 A_D1 B CREQ B CAD23 Bi
156. BER uta o aoo cto Stop STOP us trBIaso teBlaso wo om BET ute aomp aomp ww vop Yop uz triacs triacs ww oB c ro os roo Ro w Ade Apa puso rm Rt wa aAdo Ad vor Abe aso ww ron TPBoN vo aba abe ws TRAN TRAIN vos abe abe ws ren TPRINZ vos Abe abes ww wo NG vos aws abe _ ww tra man 2 8 Table 2 2 CardBus PC Card Signal Names Sorted Alphabetically TERMINAL TERMINAL TERMINAL TERMINAL NUMBER SIGNAL NAME NUMBER SIGNAL NAME NUMBER SIGNAL NAME NUMBER A_CAD5 A13 A CPERR F10 B CAD30 A16 ADO W13 AD1 N11 A_CAD6 F12 A_CREQ B_CAD31 B15 A_CAD7 C13 A_CRST B_CAUDIO C17 SIGNAL NAME AD2 U12 a A_CSTSCHG w o EO AO BO AO BO AO AO EO 0 0 U N is R10 U10 V10 o E A_RSVD B13 B_CGNT J15 B_CINT B19 7 6 3 9 2 8 3 8 2 2 wi 2 7 3 4 1 K N V V W V Vi V W V V 09 U09 09 R07 U06 06 06 U05 05 04 U04 03 02 U03 02 01 U02 N12 U14 U16 R13 R14 V17 E14 B14 A14 E13 C14 W o og w BEO BE2 BE3 LO Cc E O A S 00 E E E DATA DEVSEL FRAME 607 M P15 M11 NO N Vi AO BO CO 0 BO CO BO EO AO BO BO CO DO CO DO AO FO CO EO EO CO CO CO BO CO 0 BO 7 7 7 9 6 6 5 6 4 4 1 2 3 1 1 2 9 5 5 9 3 9 8 9 4 8 0 0
157. BINDEX Serial bus index This bit field represents the byte address in a read or write transaction on the serial interface These bits are cleared only by the assertion of GRST 4 49 Serial Bus Slave Address Register The serial bus slave address register is for programmable serial bus byte read and write transactions To write a byte the serial bus data register must be programmed with the data the serial bus index register must be programmed with the byte address and this register must be programmed with both the 7 bit slave address and the read write indicator bit On byte reads the byte address is programmed into the serial bus index register this register must be programmed with both the 7 bit slave address and the read write indicator bit and bit 5 REQBUSY in the serial bus control and status register See Section 4 50 must be polled until clear Then the contents of the serial bus data register are valid read data from the serial bus interface See Table 4 24 for a complete description of the register contents Ei TF EAS Name Derat o o o o o o o0 o Register Serial bus slave address Offset B2h function 0 Type Read Write Default 00h Table 4 24 Serial Bus Slave Address Register Description BIT SIGNAL TYPE FUNCTION 7 14 SLAVADDR RW Serial bus slave address This bit field represents the slave address of a read or write transaction on the serial interface Ww Serial bus slave address
158. CI7x21 PCI7x11 PCI_INTA is connected to The default value for this field is 00h 7 15 Interrupt Pin Register The value read from this register is function dependent and depends on the values of bits 28 the tie all bit TIEALL and 29 the interrupt tie bit INTRTIE in the system control register PCI offset 80h see Section 4 29 The INTRTIE bit is compatible with previous TI CardBus controllers and when set to 1 ties INTB to INTA internally The TIEALL bit ties INTA INTB INTC and INTD together internally The internal interrupt connections set by INTRTIE and TIEALL are communicated to host software through this standard register interface This read only register is described for all PCI7x21 PCI7x11 functions in Table 7 12 Register Interrupt pin Offset 3Dh Type Read only Default 02h Table 7 12 PCI Interrupt Pin Register Read Only INTPIN Per Function INTRTIE BIT TIEALL BIT INTPIN INTPIN INTPIN INTPIN INTPIN INTPIN BIT 29 BIT 28 FUNCTION 0 FUNCTION 1 FUNCTION 2 FUNCTION 3 FUNCTION 4 FUNCTION 5 OFFSET 80h OFFSET 80h CARDBUS CARDBUS 1394 OHCI FLASH MEDIA SD HOST SMART CARD Determined by A am Determined b Determined b a la aN Daren 203M NTG Prete he bits INT SEL in bits INT SEL in INT ki me the SD host the Smart Card flash media general control general control general control 1 Oth INTA 01h INTA 03h INTC register see register see ii Gal ii Ea pan Sect
159. CSR_BSE Power management control and status Reserved General control Subsystem alias Ch Slot 0 3 3 V Reserved maximum current Kasalusd Slot 1 3 3 V ESEIVE maximum current Slot 2 3 3 V Reserved One or more bits in this register are cleared only by the assertion of GRST 12 4 12 1 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device The vendor ID assigned to Texas Instruments is 104Ch pe eee AS AETA pA pw Vendor ID Type R R R R R R Default 1 0 1 0 4 1 Register Vendor ID Offset 00h Type Read only Default 104Ch 12 2 Device ID Register The device ID register contains a value assigned to the SD host controller by Texas Instruments The device identification for the SD host controller is 8034h pis 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o0 Device ID CAE TT we R R RA_R R R R R AIRA R_IR R R IAIO Deta 1 o o fo pfofofopofofop1if fop1ipojo Register Device ID Offset 02h Type Read only Default 8034h 12 3 Command Register The command register provides control over the SD host controller interface to the PCI bus All bit functions adhere to the definitions in the PCI Local Bus Specification as seen in the following bit descriptions See Table 12 2 for a complete description of the register contents 8 7 Name Command mwe r AR R rR rR rw a ew ea rw e rw
160. Card CardBus sockets No additional hardware requirements are placed on the system designer in order to support these devices The PC Card Standard addresses the card detection and recognition process through an interrogation procedure that the socket must initiate upon card insertion into a cold unpowered socket Through this interrogation card voltage requirements and interface type 16 bit vs CardBus are determined The scheme uses the CD1 CD2 VS1 and VS2 signals CCD1 CCD2 CVS1 CVS2 for CardBus A PC Card designer connects these four terminals in a certain configuration to indicate the type of card and its supply voltage requirements The encoding scheme for this defined in the PC Card Standard is shown in Table 3 2 on 3 2 PE Card Card I Detect and aiid Sense Connections A A Open Open 16 bit PC Card 5V Per CIS Vpp f 5 V 3 3 V and Per CIS Vpp EFE E E E ane Connect to Connect to Ground Iv 16btPC Card 33VandXXV Paos bara Connect to Connect to CVs CCD Ground LV CardBus PC Card 3 3VandX XV Per CIS Per cis ver Connect to Connect to 3 3 V X X V Per CIS Vpp Connect to Connect to cvse Ground CCD Open LV CardBus PC Card 1 8 V VCORE Ground Gonnectto Qonnect te o LV CardBus PC Card X X Vand Y Y V Per CIS v roun CVs CCDi pen ardBus ar a e PP Connect to Connect to CVS1 Ground Open CCD2 CardBus PC Card MEM Per CIS Vpp Connect to Connect to Ground CVS1 Ground CCDT UltraMedia Per qu
161. Control Register Description 8 41 Isochronous Receive Context Match Register Description 8 44 TI Extension Register Map aka desc cis dias cri A 9 1 Isochronous Receive Digital Video Enhancements Register Description ciar re ts AP 9 2 Link Enhancement Register Description o0oooooococoooo 9 4 Timestamp Offset Register Description 9 5 Base Register Configuration 00 c eee eee eee 10 1 Base Register Field Descriptions 00ce eee eee ee 10 2 Page O Port Status Register Configuration 10 4 Page O Port Status Register Field Descriptions 10 4 Page 1 Vendor ID Register Configuration aa 10 5 Page 1 Vendor ID Register Field Descriptions 10 5 Page 7 Vendor Dependent Register Configuration 10 6 Page 7 Vendor Dependent Register Field Descriptions 10 6 Power Class Descriptions sac ada aah eonueesendsket NA MAK BRA WG 10 7 Function 3 Configuration Register Map occoooocccccccc 11 1 Command Register Description a 11 3 Status Register Description cee eee ee ee eee 11 4 Class Code and Revision ID Register Description 11 5 Table 11 5 11 6 11 7 11 8 11 9 11 10 11 11 11 12 11 13 11 14 11 15 11 16 12 1 12 2 12 3 12 4 12 5 12 6 12 7 12 8 12 9 12 10 12 11 12 12 12 1
162. D register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device The vendor ID assigned to Texas Instruments is 104Ch pe eee AS AETA LA Vendor ID Type R R R R R R Default 1 0 1 0 4 1 Register Vendor ID Offset 00h Type Read only Default 104Ch 7 2 Device ID Register The device ID register contains a value assigned to the PCI7x21 PCI7x11 controller by Texas Instruments The device identification for the PCI7x21 PCI7x11 controller is 8032h js 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o0 Device ID Name q ETT we 7 R R RIR R R R R R R R R R R R Deta 1 o o fo pfofofopofofop1if jopojsjo Register Device ID Offset 02h Type Read only Default 8032h 7 3 Command Register The command register provides control over the PCI7x21 PCI7x11 interface to the PCI bus All bit functions adhere to the definitions in the PCI Local Bus Specification as seen in the following bit descriptions See Table 7 2 for a complete description of the register contents 8 7 Name Command mwe r rR R rR R rw a ew ea jaw e rw rR pw ew or petam o o o fo fo fo fo fo foto fotoftotototo Register Command Offset 04h Type Read Write Read only Default 0000h Table 7 2 Command Register Description FIELD NAME DESCRIPTION RSVD Reserved Bits 15 11 return Os when read INTx disable When set to 1 this bit disables the function from asserting inter
163. D2 and D3hot The differences between the three D3 states is invisible to the software because the controller is not accessible in the D3cold or D3off state NOTE Similarly bus power states of the PCI bus are BO B3 The bus power states BO B3 are derived from the device power state of the originating bridge device For the operating system OS to manage the controller power states on the PCI bus the PCI function must support four power management operations These operations are e Capabilities reporting e Power status reporting e Setting the power state e System wake up The OS identifies the capabilities of the PCI function by traversing the new capabilities list The presence of capabilities in addition to the standard PCI capabilities is indicated by a 1 in bit 4 CAPLIST of the status register PCI offset 06h see Section 4 5 The capabilities pointer provides access to the first item in the linked list of capabilities For the PCI7x21 PCI7x11 controller a CardBus bridge with PCI configuration space header type 2 the capabilities pointer is mapped to an offset of 14h The first byte of each capability register block is required to be a unique ID of that capability PCI power management has been assigned an ID of 01h The next byte is a pointer to the next pointer item in the list of capabilities If there are no more items in the list then the next item pointer must be set to 0 The registers following the next item pointer
164. DATA SC_OC SC_ PWR_ CTRL ISPKROUT SM_R B SC_RFU SC_FCB SC RST SC CLK SC VCC 5V SD DAT2 SM_D6 SC_GPIO4 SD_DAT3 SM_D7 SC_GPIO3 SD CMD SM ALE SC GPI02 SD CLK SM RE SC_GPIO1 SD_DAT1 SM_D5 SC_GPIOS5 SM CLE SC_GPIOO VR_ PORT VR_EN SD_DATO SM_D4 SC_GPIO6 MS_DATA3 SD_DAT3 SM D3 SD WP VCC VCC VCC VCC MS_SDIO DATAO SD_DATO sM Do MS DATA1 SD_DAT1 SM D1 MS DATA2 SD_DAT2 SM_D2 MS CLK SD CLK A CAD20 IA_A6 A_CPAR 1A A13 A CAD14 A_A9 A_CC BED IIA CET MC_PWR _CTRL_O MC_PWR _CTRL_1 MS_BS SD_CMD SMWE MS CD A_CC BEZ IA A12 A_CPERR 1A A14 A CAD6 A_D13 SD_CD A_CCLK 1A A16 A CBLOCH A CAD15 JIA A19 ETOWR A CAD8 A_D15 A_CAD31 A_D10 A_D2 A_CAD29 A_D1 A_CAD30 1A D9 A CAD28 IA D8 A CINT A READY TREO A_CC BE3 A_REG A_CAD22 A_CAD19 JIA_A4 I A A25 PA CFRAME IA A23 A CAD13 IIA TORD A_RSVD 1A A18 A CAD11 IIA OE A_CAD7 1A D7 A CAD4 A_D12 A_CAD27 A_DO IA CSTSCHG HA BVD1 STSCHG Al A_CAD26 A_AO A_CAD23 IA A3 A CAD21 A CAD18 ALAS IA A7 ACCIRDY IAMS IA WE la_CC BET A_A8 A_CAD12 NAAN A CAD10 A_CE2 A_RSVD A_D14 A CAD1 A_D4 A_CAUDIO
165. ED Socket Activity Indicators 3 9 3 5 10 CardBus Socket Registers a 3 10 3 5 11 48 MHZz Clock Requirements aaa 3 10 Serial EEPROM Interface coa de kA KG KANAN KG eddies TH WAYNE 3 11 3 6 1 Serial Bus Interface Implementation 3 11 3 6 2 Accessing Serial Bus Devices Through Software 3 11 3 6 3 Serial Bus Interface Protocol 3 11 3 6 4 Serial Bus EEPROM Application oo 3 13 Programmable Interrupt Subsystem aa 3 16 3 7 1 PC Card Functional and Card Status Change Interrupts 3 17 3 7 2 Interrupt Masks and Flags eee eeee eee 3 18 3 7 3 Using Parallel IRQ Interrupts 0 00e ee eee 3 19 3 7 4 Using Parallel PCI Interrupts a 3 19 ER Using Serialized IRQSER Interrupts 3 20 3 7 6 SMI Support in the PCI7x21 PCI7x11 Controller 3 20 Power Management Overview aaa 3 20 3 8 1 1394 Power Management Function 2 3 21 3 8 2 Integrated Low Dropout Voltage Regulator LDO VR 3 22 3 8 3 CardBus Functions 0 and 1 Clock Run Protocol 3 22 3 8 4 CardBus PC Card Power Management 3 22 3 8 5 16 Bit PC Card Power Management 3 23 3 8 6 Suspend Mode 0 aaa 3 23 3 8 7 Requirements for Suspend Mode 3 23 3 8 8 Ring INACIO naaa cons PEK ANA KYLA Aka AA 3 24
166. I7x21 PCI7x11 controller sets bit 11 to 1 when it encounters a fatal error and clears the bit when RSCU Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by software to stop descriptor processing The PCI7x21 PCI7x11 controller changes this bit only on a system hardware or software reset 14 13 RSVD Reserved Bits 14 and 13 return Os when read software clears bit 15 run Asynchronous contexts supporting out of order pipelining provide unique ContextControl dead functionality See Section 7 7 in the 1394 Open Host Controller Interface wake dead Specification Release 1 1 for more information active The PCI7x21 PCI7x11 controller sets bit 10 to 1 when it is processing descriptors RSVD Reserved Bits 9 and 8 return Os when read 000 100M bits sec 001 200M bits sec 010 400M bits sec All other values are reserved ii This field indicates the speed at which a packet was received or transmitted and only contains meaningful information for receive contexts This field is encoded as ae This field holds the acknowledge sent by the link core for this packet or an internally generated error code if the packet was not transferred successfully N 8 38 8 41 Asynchronous Context Command Pointer Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the PCI7x21 PCI7x11 controller accesses when software e
167. I7x21 PCI7x11 functions as separate entities when enabling functionality through the command register The SERR_EN and PERR_EN enable bits in this register are internally wired OR between the three functions and these control bits appear to software to be separate for each function m e a e o e e s a e a ame Gama Type R R RW RW RW RW R RW RW Default 0 0 0 0 0 0 0 0 0 4 Register Command Offset 04h Type Read only Read Write Default 0000h Table 4 3 Command Register Description BIT SIGNAL TYPE FUNCTION 15 11 Reserved Bits 15 11 return Os when read INTx disable When set to 1 this bit disables the function from asserting interrupts on the INTx signals INT_DISABLE 0 INTx assertion is enabled default 1 INTx assertion is disabled Fast back to back enable The PCI7x21 PCI7x11 controller does not generate fast back to back transactions therefore this bit is read only This bit returns a 0 when read System error SERR enable This bit controls the enable for the SERR driver on the PCI interface SERR can be asserted after detecting an address parity error on the PCI bus Both this bit and bit 6 must be set SERR_EN for the PCI7x21 PCI7x11 controller to report address parity errors 0 Disables the SERR output driver default 1 Enables the SERR output driver Reserved Bit 7 returns 0 when read Parity error response enable This bit controls the PCI7x21 PCI7x11 response to
168. I7x21 PCI7x11 latency timer and class cache line size register at offset OCh in the PCI configuration space see Section 13 6 13 16 Maximum Latency Register The maximum latency register contains the maximum latency value for the Smart Card controller core Maximum latency Name SS amay near o o o o o o foo Register Maximum latency Offset 3Fh Type Read Update Default 00h Table 13 9 Maximum Latency Register Description FIELD NAME TYPE DESCRIPTION 7 0 MAX LAT RU Maximum latency The contents of this field may be used by host BIOS to assign an arbitration priority level to the Smart Card controller The default for this register indicates that the Smart Card controller may need to access the PCI bus as often as every 0 25 us thus an extremely high priority level is requested The contents of this field may also be loaded through the serial EEPROM 13 17 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked list capability item and provides a pointer to the next capability item See Table 13 10 for a complete description of the register contents as 14 o 6 7 6 5 4 5 2 1 0 Name Capability ID and next item pointer Type R R R R R iR R RiR R R R R _R Rie Dean o o o o o fo fo fo fo fo fo fofyofofol Register Capability ID and next item pointer Offset 44h Type Read only Default 0001h Table 13 10 Capab
169. INT_SEL RW Interrupt select These bits are program the INTPIN register and set which interrupt output is used This field is ignored if one of the USE_INTx terminals is asserted 00 INTA pin 1 01 INTB pin 2 10 INTC pin 3 11 INTD pin 4 D3_COLD RW Disable function Setting this bit to 1 hides this function PCI configuration register of this function R must be accessible at any time Clock PCI and 48 MHz to the rest of the function blocks must be gated to reduce power consumption 3 0 RSVD Reserved Bits 3 0 return Os when read E One or more bits in this register are cleared only by the assertion of GRST 13 13 13 23 Subsystem ID Alias Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 2Ch and 2Eh respectively See Table 13 14 for a complete description of the register contents Default Register Subsystem ID alias Offset 50h Type Read Write EEPROM GRST only Default 8035 104Ch Table 13 14 Subsystem ID Alias Register Description FIELD NAME TYPE DESCRIPTION 31 16 SubsystemID RW Subsystem device ID The value written to this field is aliased to the subsystem ID register at PCI offset 2Eh 15 0 SubsystemVendorlD RW Subsystem vendor ID The value written to this field is aliased to the subsystem vendor ID register at PCI offset 2Ch 13 24 Class Code Alias Register This r
170. IO2 20 GPIO_ENB2 R W 0 High impedance output default 1 Output is enabled 19 17 RSVD Reserved Bits 19 17 return Os when read GPIO_DATA2 GPIO2 data When GPIO2 output is enabled the value written to this bit represents the logical data driven to the GPIO2 terminal Disable link power status LPS This bit configures this terminal as DISABLE_LPS 0 LPS default 1 GPIO1 14 RSVD oR Reserved Bit 14 returns 0 when read GPIO1 polarity invert When bit 15 DISABLE_LPS is set to 1 this bit controls the input output polarity control of GPIO1 0 Noninverted default 1 Inverted 13 GPIO_INV1 R W Table 7 23 GPIO Control Register Description Continued BIT SIGNAL TYPE FUNCTION GPIO1 enable control When bit 15 DISABLE LPS is set to 1 this bit controls the output enable for GPIO1 le ORIO EAB a 0 High impedance output default 1 Output is enabled 11 9 RSVD R Reserved Bits 11 9 return Os when read GPIO_DATA1 GPIO1 data When bit 15 DISABLE_LPS is setto 1 and GPIO1 output is enabled the value written to this bit represents the logical data driven to the GPIO1 terminal DISABLE_BMC Disable bus manager contender BMC This bit configures this terminal as bus manager contender or GPIOO 0 BMC default 1 GPIOO 6 RSVD R Reserved Bit 6 returns 0 when read 5 GPIO_INVO GPIO_ENBO GPIOO polarity invert When bit 7 DISABLE_BMC is set to 1 this bit controls the
171. Index Register Description 0ooocccoooccooooo 4 35 Serial Bus Slave Address Register Description 4 36 Serial Bus Control Status Register Description 4 37 ExCA Registers and Offsets 0 00 c ccc eee eee 5 3 ExCA Identification and Revision Register Description 5 5 ExCA Interface Status Register Description 5 6 ExCA Power Control Register Description 82365SL Support 5 7 ExCA Power Control Register Description 82365SL DF Support 5 7 ExCA Interrupt and General Control Register Description 5 8 ExCA Card Status Change Register Description 5 9 ExCA Card Status Change Interrupt Configuration Register Description coxis ev seen hehesieae RAP crs 5 10 ExCA Address Window Enable Register Description 5 11 ExCA I O Window Control Register Description 5 12 ExCA Memory Windows 0 4 Start Address High Byte Registers Descriptio Za GRAE NAKAKA ARENA aora 5 16 ExCA Memory Windows 0 4 End Address High Byte Registers DeSCrpuon sisi sabina elabore pia dit 5 18 Table Title Page 5 13 ExCA Memory Windows 0 4 Offset Address High Byte Registers Description RA ean tee ee teas eee ee 5 20 5 14 ExCA Card Detect and General Control Register Description 5 21 5 15 ExCA Global Control Register Description 5 22 6 1 CardBus Socket Registers
172. MA request WP can be used as the DMA request signal during DMA operations to a 16 bit PC Card that supports DMA If used then the PC Card asserts WP to indicate a request for a DMA operation 2 21 Table 2 12 CardBus PC Card Interface System Terminals A 33 Q to 47 Q series damping resistor per PC Card specification is the only external component needed for terminals B08 A_CCLK and H17 B_CCLK If any CardBus PC Card interface system terminal is unused then the terminal may be left floating SKT A TERMINAL SKT B TERMINALT CardBus clock CCLK provides synchronous timing for all transactions on the CardBus interface All signals except CRST CCLKRUN CINT CSTSCHG CAUDIO CCD2 CCD1 CVS2 and CVS1 are v f sampled on the rising edge of CCLK and all timing PCIO3 ne parameters are defined with the rising edge of this signal CCLK operates at the PCI bus clock frequency but it can be stopped in the low state or slowed down for power savings CardBus clock run CCLKRUN is used by a CardBus EEN EIAN PC Card to request an increase in the CCLK Voca PCGOERRON BLOGLKRUN frequency and by the controller to indicate that the No pale Pol VECB CCLK frequency is going to be decreased CardBus reset CRST brings CardBus PC Card specific registers sequencers and signals to a known state When CRST is asserted all CardBus Voca A_CRST A06 B CRST F17 PC Card signals are placed in a high impedance PCIl4 PCIO4 P Voce state and the con
173. Maximum Current Register This register is a read write register and the contents of this register are aliased to the 3 3 MAX CURRENT field in the slot O maximum current capabilities register at offset 48h in the SD host standard registers This register is a GRST only register ARR KA CI EC A RA A EC CN E TEEN TATI ko ls e po po Jefe Je Register Slot 3 3 V maximum current Type Read Write Offset 94h Default 0000h 12 26 Slot 1 3 3 V Maximum Current Register This register is a read write register and the contents of this register are aliased to the 3 3 MAX CURRENT field in the slot 1 maximum current capabilities register at offset 48h in the SD host standard registers This register is a GRST only register If slot 1 is not implemented this register is read only and returns Os when read CTO po CI CI CI A AC I gt Name fo fo foftoftototfotfo Register Slot 1 3 3 V maximum current Type Read Write Offset 98h Default 0000h 12 27 Slot 2 3 3 V Maximum Current Register This register is a read write register and the contents of this register are aliased to the 3 3 MAX CURRENT field in the slot 2 maximum current capabilities register at offset 48h in the SD host standard registers This register is a GRST only register If slot 2 is not implemented this register is read only and returns Os when read CT A CI ICO a Name fo o o o o o o o Register Slot 2 3 3 V maximum current Type Read Write
174. NTA INTB INTC INTD slots default 01 INTA INTB INTC INTD signal in INTB ANTC INTD INTA slots 10 INTA INTB INTC INTD signal in INTC INTD INTA INTB slots 11 INTA INTB INTC INTD signal in INTD INTA INTB INTC slots This bit ties INTA to INTB internally to INTA and reports this through the interrupt pin register PCI offset 3Dh see Section 4 24 This bit has no effect on INTC or INTD This bit ties INTA INTB INTC and INTD internally to INTA and reports this through the interrupt pin register PCI offset 3Dh see Section 4 24 P2C power switch clock The PCI7x21 PCI7x11 CLOCK signal clocks the serial interface power switch and the internal state machine The default state for this bit is O requiring an external clock source provided to the CLOCK terminal Bit 27 can be set to 1 allowing the internal oscillator to provide the clock signal 0 CLOCK is provided externally input to the PCI7x21 PCI7x11 controller 1 CLOCK is generated by the internal oscillator and driven by the PCI7x21 PCI7x11 controller default SMI interrupt routing This bit is shared between functions 0 and 1 and selects whether IRQ2 or CSC is signaled when a write occurs to power a PC Card socket 0 PC Card power change interrupts are routed to IRQ2 default 1 A CSC interrupt is generated on PC Card power changes 29 t INTRTIE RW 287 TIEALL RW 271 PSCCLK RW 26 SMIROUTE RW SMI interrupt status This socket dependent bit is set
175. P is driven by a CardBus target to request the initiator to stop the current CardBus VEca B CSTOP J17 transaction CSTOP is used for target disconnects PU3 VCCB and is commonly asserted by target devices that do not support burst data transfers CardBus status change CSTSCHG alerts the system v B_CSTSCHG F14 to a change in the card status and is used as a SW1 ae wake up mechanism A_CSTOP A_CSTSCHG CardBus voltage sense 1 and CardBus voltage sense 2 CVS1 and CVS2 are used in conjunction with CCD1 and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and card type B CVS1 B_CVS2 CardBus target ready CTRDY indicates the ability of the CardBus target to complete the current data mon phase of the transaction A data phase is completed PU5 VCCA A_CTRDY BGTRDY on a rising edge of CCLK when both CIRDY and VecB CTRDY are asserted until this time wait states are inserted A CVS1 A CVS2 T These terminals are reserved for the PCI7611 and PCI7411 controllers 2 25 Table 2 15 IEEE 1394 Physical Layer Terminals vO EXTERNAL PIN STRAPPING TNA DESCRIPTION INPUT OUTPUT COMPONENTS IF USED Cable not active This terminal is asserted high when there are no ports receiving incoming bias voltage If it is not used then this terminal must be strapped either to DVDD or GND through a resistor The CNA terminal can be disabled by setting bit 7 CNAOUT of the PCI PHY co
176. PCI offset 80h see Section 4 29 Once this bit is cleared the BIOS can write a subsystem identification value into the registers at PCI offset 40h The BIOS must set the SUBSYSRW bit such that the subsystem vendor ID register and subsystem ID register are limited to read only access This approach saves the added cost of implementing the serial electrically erasable programmable ROM EEPROM In some conditions such as in a docking environment the subsystem vendor ID register and subsystem ID register must be loaded with a unique identifier via a serial EEPROM The PCI7x21 PCI7x11 controller loads the data from the serial EEPROM after a reset of the primary bus Note that the SUSPEND input gates the PCI reset from the entire PCI7x21 PCI7x11 core including the serial bus state machine see Section 3 8 6 Suspend Mode for details on using SUSPEND The PC17x21 PC17x11 controller provides a two line serial bus host controller that can interface to a serial EEPROM See Section 3 6 Serial EEPROM Interface for details on the two wire serial bus controller and applications 3 4 5 Function 2 OHCI 1394 Subsystem Identification The subsystem identification register is used for system and option card identification purposes This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space see Section 7 25 Subsystem Access Register See Table 7 22 for a complete descrip
177. PCI7x11 controller is not cycle master this register is loaded with the data field in an incoming cycle start In the event that the cycle start message is not received the fields can continue incrementing on their own if programmed to maintain a local time reference See Table 8 26 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Isochronous cycle timer CA Cd RWU RWU pan x x x x hhehehe ex 195 ae a2 n o e le r l e ls le le le i le Isochronous cycle timer CAY CCS RWU RWU Dean x x x x AA AA Register Isochronous cycle timer Offset FOh Type Read Write Update Default XXXX XXXXh Table 8 26 Isochronous Cycle Timer Register Description FIELD NAME TYPE DESCRIPTION 31 25 cycleSeconds RWU This field counts seconds rollovers from bits 24 12 cycleCount field modulo 128 24 12 cycleCount RWU This field counts cycles rollovers from bits 11 0 cycleOffset field modulo 8000 11 0 cycleOffset RWU This field counts 24 576 MHz clocks modulo 3072 that is 125 us If an external 8 kHz clock configuration is being used then this field must be cleared to Os at each tick of the external clock 8 31 8 35 Asynchronous Request Filter High Register The asynchronous request filter high set clear register enables asynchronous receive requests on a per node basis and handles the upper node IDs
178. PCIGATE only and must be cleared to O all applications When bit 0 is set to 1 the PCI clock is always kept running through the CLKRUN protocol When this bit is cleared the PCI clock can be stopped using CLKRUN on MFUNC6 This bit is cleared only by the assertion of GRST 0t KEEP PCLK RW 7 24 Link Enhancement Control Register The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial EEPROM if present After these bits are set to 1 their functionality is enabled only if bit 22 aPhyEnhanceEnable in the host controller control register at OHCI offset 50h 54h see Section 8 16 is set to 1 See Table 7 21 for a complete description of the register contents Link enhancement control Name Linkenhancement control Type RIR RIR IR R R RIR R R R R R R R Dea o o o o o o o o o o o0o o oJ o o o 7 Link enhancement control R RW RW R Register Link enhancement control Offset F4h Type Read Write Read only Default 0000 1000h Table 7 21 Link Enhancement Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 16 RSVD Reserved Bits 31 16 return Os when read Disable AT pipelining When bit 15 is set to 1 out of order AT pipelining is disabled The default value for this bit is 0 RSVD 7 Reserved Bit 14 defaults to O and must remain 0 for normal operation of the OHCI core This field sets
179. PHY layer is notified that the link supports the IEEE Std 1394a 2000 acceleration enhancements that is ad PNY ack accelerated fly by concatenation etc It is recommended that this bit be set to 1 The default value for this bit is 0 RSVD R Reserved Bit 0 returns 0 when read This bit is cleared only by the assertion of GRST 7 25 Subsystem Access Register Write access to the subsystem access register updates the subsystem identification registers identically to OHCI Lynx The system ID value written to this register may also be read back from this register See Table 7 22 for a complete description of the register contents Subsystem access Name a ew TTR Ta Ta Taw w Default Register Subsystem access Offset F8h Type Read Write Default 0000 0000h Table 7 22 Subsystem Access Register Description FIELDNAME TYPE DESCRIPTION 31 164 SUBDEV ID Subsystem device ID alias This field indicates the subsystem device ID 15 0 SUBVEN_ID Subsystem vendor ID alias This field indicates the subsystem vendor ID These bits are cleared only by the assertion of GRST 7 26 GPIO Control Register The GPIO control register has the control and status bits for GPIOO GPIO1 GPIO2 and GPIO3 ports Upon reset GPIOO and GPIO1 default to bus manager contender BMC and link power status terminals respectively The BMC terminal can be configured as GPIOO by setting bit 7 DISABLE_BMC t
180. RR B_CPERR T These terminals are reserved for the PCI7611 and PCI7411 controllers CardBus request CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator CardBus cycle frame CFRAME is driven by the initiator of a CardBus bus cycle CFRAME is asserted to indicate that a bus transaction is beginning and Voca l PCII7 PCIO7 B_CFRAME data transfers continue while this signal is asserted de G gio VCCB When CFRAME is deasserted the CardBus bus transaction is in the final data phase CardBus bus grant CGNT is driven by the controller Vocal B_CGNT PCIO7 VCCB CardBus interrupt CINT is asserted low by a CardBus PC Card to request interrupt servicing from the host CardBus initiator ready CIRDY indicates the ability of the CardBus initiator to complete the current data phase of the transaction A data phase is completed on arising edge of CCLK when both CIRDY and Pela PcIO4 VCCA VCCB CardBus system error CSERR reports address parity errors and other system errors that could lead to catastrophic results CSERR is driven by the card synchronous to CCLK but deasserted by a weak pullup deassertion may take several CCLK periods The controller can report CSERR to the system by assertion of SERR on the PCI interface Perla Pcios VCCA VCCB 2 24 Table 2 14 CardBus PC Card Interface Control Terminals Continued SKT A TERMINAL SKT B TERMINALT 1 0 PU POWER CardBus stop CSTO
181. RS CROSTA no Sb Br R The marketing status values are defined as follows ACTIVE Product device recommended for new designs LIFEBUY TI has announced that the device will be discontinued and a lifetime buy period is in effect NRND Not recommended for new designs Device is in production to support existing customers but TI does not recommend using this part in a new design PREVIEW Device has been announced but is not in production Samples may or may not be available OBSOLETE TI has discontinued the production of the device 2 Eco Plan The planned eco friendly classification Pb Free RoHS or Green RoHS amp no Sb Br please check http Awww ti com productcontent for the latest availability information and additional product content details TBD The Pb Free Green conversion plan has not been defined Pb Free RoHS Tl s terms Lead Free or Pb Free mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances including the requirement that lead not exceed 0 1 by weight in homogeneous materials Where designed to be soldered at high temperatures TI Pb Free products are suitable for use in specified lead free processes Green RoHS amp no Sb Br TI defines Green to mean Pb Free ROHS compatible and free of Bromine Br and Antimony Sb based flame retardants Br or Sb do not exceed 0 1 by weight in homogeneous material 3 MSL Peak Temp The Moisture Sensitivit
182. RW Power state This 2 bit field determines the current power state and sets the SD host controller to a new power state This field is encoded as follows 00 Current power state is DO 01 Current power state is D1 10 Current power state is D2 11 Current power state is D3 ot E One or more bits in this register are cleared only by the assertion of GRST 12 20 Power Management Bridge Support Extension Register The power management bridge support extension register provides extended power management features not applicable to the SD host controller thus it is read only and returns 00h when read 7 Isla sla la eo Name we R R R R R R o Detam o o o o o o o o Register Power management bridge support extension Offset 86h Type Read only Default 00h 12 13 12 21 Power Management Data Register The power management bridge support extension register provides extended power management features not applicable to the SD host controller thus it is read only and returns 0 when read Bit 7 6 5 4 3 Name Power management data Type Default Register Power management data Offset 87h Type Read only Default 00h 12 22 General Control Register The general control register provides miscellaneous PCI related configuration See Table 12 15 for a complete description of the register a Name EEN Type Default Register General control Off
183. Register The GUID ROM register accesses the serial EEPROM and is only applicable if bit 24 GUID_ROM in the OHCI version register at OHCI offset 00h see Section 8 1 is set to 1 See Table 8 3 for a complete description of the register contents Register Offset Type Default FIELD NAME addrReset RSVD GUID ROM 04h Read Set Update Read Update Read only 00XX 0000h Table 8 3 GUID ROM Register Description TYPE DESCRIPTION Software sets bit 31 to 1 to reset the GUID ROM address to O When the PCI7x21 PCI7x11 controller completes the reset it clears this bit The PCI7x21 PCI7x11 controller does not automatically fill bits 23 16 rdData field with the oth byte Reserved Bits 30 26 return Os when read rdStart RSVD A read of the currently addressed byte is started when bit 25 is set to 1 This bit is automatically cleared when the PCI7x21 PCI7x11 controller completes the read of the currently addressed GUID ROM byte rdData RSVD R Reserved Bit 24 returns 0 when read RU This field contains the data read from the GUID ROM Reserved Bits 15 8 return Os when read miniROM The miniROM field defaults to 00h indicating that no mini ROM is implemented If an EEPROM is implemented then all 8 bits of this miniROM field are downloaded from EEPROM word offset 28h For this device the miniROM field must be greater than h to indicate a valid miniROM offset into the EEPROM
184. Register Physical request filter low Offset 118h set register 11Ch clear register Type Read Set Clear Default 0000 0000h Table 8 30 Physical Request Filter Low Register Description BIT FIELD NAME TYPE DESCRIPTION 31 physReqResource31 RSC If bit 31 is set to 1 for local bus node number 31 physical requests received by the controller from that node are handled through the physical request context physReqResource30 If bit 30 is set to 1 for local bus node number 30 physical requests received by the controller from that node are handled through the physical request context physReqResourcen Bits 29 through 2 pbhysReqResourcen where n 29 28 27 2 follow the same pattern as bits 31 and 30 physReqResource1 If bit 1 is set to 1 for local bus node number 1 physical requests received by the controller from that node are handled through the physical request context physReqgResource0 RS If bit O is set to 1 for local bus node number O physical requests received by the controller from that node are handled through the physical request context 8 39 Physical Upper Bound Register Optional Register The physical upper bound register is an optional register and is not implemented This register returns all Os when read Bt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Physical upper bound re R IR RIR RIR RIR R R R RIR R R R Defaut o o o o o fo fo fo fo
185. SR resource as follows 00 BUS MANAGER ID 01 BANDWIDTH AVAILABLE 10 CHANNELS AVAILABLE HI 11 CHANNELS AVAILABLE LO 8 7 8 7 Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM offset FFFF F000 0400h See Table 8 6 for a complete description of the register contents esl ele ee ee eee lol eee Configuration ROM header ame RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default me Poe CIO KG CCD II RW AW AW Dean x x x x xi xitxi x x x x x x x x x Register Configuration ROM header Offset 18h Type Read Write Default 0000 XXXXh Table 8 6 Configuration ROM Header Register Description FIELD NAME DESCRIPTION info length IEEE 1394 bus management field Must be valid when bit 17 linkEnable in the host controller control register at OHCI offset 50h 54h see Section 8 16 is set to 1 The default value for this field is 00h 23 16 crc length RW IEEE 1394 bus management field Must be valid when bit 17 linkEnable in the host controller control register at OHCI offset 50h 54h see Section 8 16 is set to 1 The default value for this field is 00h 15 0 rom crc value RW IEEE 1394 bus management field Must be valid at any time bit 17 linkEnable in the host controller control register at OHCI offset 50h 54h see Section 8 16 is set to 1 8 8 Bus Identification Register The bus identifica
186. Socket Address 802h Card A ExCA Offset 02h Card B ExCA Offset 42h Type Read only Read Write Default 00h Table 5 4 ExCA Power Control Register Description 82365SL Support SIGNAL TYPE FUNCTION Card output enable Bit 7 controls the state of all of the 16 bit outputs on the PCI7x21 PCI7x11 controller This bit is encoded as GOE AW 0 16 bit PC Card outputs disabled default 1 16 bit PC Card outputs enabled RSVD Reserved Bit 6 returns 0 when read Auto power switch enable AUTOPWRSWEN RW 0 Automatic socket power switching based on card detects is disabled 1 Automatic socket power switching based on card detects is enabled PC Card power enable 0 Vcc No connection CAPWREN RUY 1 Vcc is enabled and controlled by bit 2 EXCAPOWER of the system control register PCI offset 80h see Section 4 29 RSVD R Reserved Bits 3 and 2 return Os when read PC Card Vpp power control Bits 1 and 0 are used to request changes to card Vpp The PCI7x21 PCI7x11 controller ignores this field unless Vcc to the socket is enabled This field is encoded as Da PACAVEE RWY 00 No connection default 10 12V 01 Vcc 11 Reserved t One or more bits in this register are cleared only by the assertion of GRST when PME is enabled If PME is not enabled then this bit is cleared by the assertion of PRST or GRST Table 5 5 ExCA Power Control Register Description 82365SL DF Support SIGNAL TYPE FUNCTION Card output enable This bit
187. T One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled If PME is not enabled then this bit is cleared by the assertion of PRST or GRST One or more bits in this register are cleared only by the assertion of GRST One or more bits in this register are global in nature and must be accessed only through function 0 4 2 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG that identifies the manufacturer of the PCI device The vendor ID assigned to Texas Instruments is 104Ch Register Vendor ID Offset 00h Functions O 1 Type Read only Default 104Ch 4 2 4 3 Device ID Register Functions 0 and 1 This read only register contains the device ID assigned by TI to the PCI7x21 PCI7x11 CardBus controller functions functions 0 and 1 anta aa o 7 e pa Device ID Smart Card enabled ame Default Register Device ID Offset 02h Functions 0 and 1 Type Read only Default 8031h 4 3 4 4 Command Register The PCI command register provides control over the PCI7x21 PCI7x11 interface to the PCI bus All bit functions adhere to the definitions in the PCI Local Bus Specification see Table 4 3 None of the bit functions in this register are shared among the PCI7x21 PCI7x11 PCI functions Three command registers exist in the PCI7x21 PCI7x11 controller one for each function Software manipulates the PC
188. TDL Ca a 15 11 tun Os amen end rs Rew mesones Bits 7 5 ram 0s when read 11 15 11 16 12 SD Host Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21 PCI7x11 SD host controller interface All registers are detailed in the same format a brief description for each register is followed by the register offset and a bit table describing the reset state for each register A bit description table typically included when the register contains bits of more than one type or purpose indicates bit field names a detailed field description and field access tags which appear in the type column Table 4 1 describes the field access tags The PCI7x21 PCI7x11 controller is a multifunction PCI device The SD host controller core is integrated as PCI function 4 The function 4 configuration header is compliant with the PC Local Bus Specification as a standard header Table 12 1 illustrates the configuration header that includes both the predefined portion of the configuration space and the user definable registers Table 12 1 Function 4 Configuration Register Map Class code Slot 0 base address Slot 1 base address Slot 2 base address Reserved 1Ch 28h Subsystem vendor ID Subsystem ID Reserved PCI power Reserved management 34h capabilities pointer Reserved Reserved Slot information Reserved Power management capabilities Capability ID pee PM
189. TRL 1 on to FM socket Memory Stick bus state This signal provides Memory Mako z Stick bus state information mitos Sw2 INGG Media Card detect This input is asserted when a baga Memory Stick or Memory Stick Pro media is inserted a ae pwelwo Memory Stick clock This output provides the MS clock MS SUI which operates at 16 MHz Los awe Nee MS_DATA3 Memory Stick data 3 1 These signals provide the MS_DATA2 Memory Stick data path 1 0 TTLI2 TTLO2 sw2 Voc MS_DATA1 Memory Stick serial data I O This signal provides MS_SDIO DATO Memory Stick data input output Memory Stick data 0 ue TITE Meee Sw2 Vcc 2 27 Table 2 18 Smart Media XD Terminals If any Smart Media XD terminal is unused then the terminal may be left floating Eu Ui PU POWER EXTERNAL DESCRIPTION Bi INPUT OUTPUT RAIL PARTS MC PWR CTRL 0 Power switch or Media card power control for flash media sockets LVCO1 FET to turn power Me even on to FM socket SmartMedia address latch enable This signal functions as specified in the SmartMedia SMLALE specification and is used to latch addresses TrLO2 Swe Vcc passed over SM_D7 SM_DO SmartMedia card detect This input is asserted SmartMedia card enable This signal functions as specified in the SmartMedia specification and is SMLGE HOY used to enable the media for a pending ee Swe Voc transaction SmartMedia command latch enable This signal functions as specified in the SmartMedia
190. Table 5 1 identifies each ExCA register and its respective ExCA offset The PCI7x21 PCI7x11 controller also provides a memory mapped alias of the ExCA registers by directly mapping them into PCI memory space They are located through the CardBus socket registers ExCA registers base address register PCI register 10h at memory offset 800h Each socket has a separate base address programmable by function See Figure 5 2 for an ExCA memory mapping illustration Note that memory offsets are 800h 844h for both functions 0 and 1 This illustration also identifies the CardBus socket register mapping which is mapped into the same 4K window at memory offset Oh The interrupt registers in the ExCA register set as defined by the 82365SL specification control such card functions as reset type interrupt routing and interrupt enables Special attention must be paid to the interrupt routing registers and the host interrupt signaling method selected for the PCI7x21 PCI7x11 controller to ensure that all possible PCI7x21 PCI7x11 interrupts can potentially be routed to the programmable interrupt controller The ExCA registers that are critical to the interrupt signaling are at memory address ExCA offsets 803h and 805h Access to I O mapped 16 bit PC Cards is available to the host system via two ExCA I O windows These are regions of host I O address space into which the card I O space is mapped These windows are defined by start end and offset addresses programmed
191. Table 7 6 for a complete description of the register contents 15 14 ts 2 to 9 8 Header type and BIST Name fee R RIR RIR R RIR R R R R R m eee GC Register Header type and BIST Offset OEh Type Read only Default 0080h Table 7 6 Header Type and BIST Register Description FIELDNAME TYPE DESCRIPTION Built in self test The PCI7x21 PCI7x11 controller does not include a BIST therefore this field returns 15 8 BIST 00h when read PCI header type The PCI7x21 PCI7x11 controller includes the standard PCI header which is HERDERLIIPE ES communicated by returning 80h when this field is read 7 8 OHCI Base Address Register The OHCI base address register is programmed with a base address referencing the memory mapped OHCI control When BIOS writes all 1s to this register the value read back is FFFF F800h indicating that at least 2K bytes of memory address space are required for the OHCI registers See Table 7 7 for a complete description of the register contents aw aw Aw A ARR ern o o o o o o lolo fo o olo oilo ieo Register OHCI base address Offset 10h Type Read Write Read only Default 0000 0000h Table 7 7 OHCI Base Address Register Description FIELDNAME TYPE DESCRIPTION OHCI register pointer This field specifies the upper 21 bits of the 32 bit OHCI base address register sla OHGIREGSPTA The default value for this field is all Os 10 4 OHCI sz OHCI re
192. The revision ID register indicates the silicon revision of the PCI7x21 PCI7x11 controller Revision ID Name Revision CA IE O ION EO AH petam o o 00 Too loo o o o Register Revision ID Offset 08h functions O 1 Type Read only Default 00h 4 7 Class Code Register The class code register recognizes PCI7x21 PC17x11 functions O and 1 as a bridge device 06h and a CardBus bridge device 07h with a 00h programming interface Bit 23 22 21 20 19 18 17 16 15 14 13 12 ji 10 9 8 7 6 5 4 3 2 1 o0 PCI class code Basedass we R R R R R R R RIR R R R R R RIR R R RIR R R R Deta 0 fo 0 0 0 1 1 0o o ofo olo 1 1 1l o o olo o olo o Register PCI class code Offset 09h functions O 1 Type Read only Default 06 0700h 4 8 Cache Line Size Register The cache line size register is programmed by host software to indicate the system cache line size Name Cache line size Type RW RW Default 0 0 Register Cache line size Offset OCh Functions O 1 Type Read Write Default 00h 4 6 4 9 Latency Timer Register The latency timer register specifies the latency timer for the PCI7x21 PCI7x11 controller in units of PCI clock cycles When the PCI7x21 PCI7x11 controller is a PCI bus initiator and asserts FRAME the latency timer begins counting from zero If the latency timer expires before the PCI7x21 PCI7x11 transaction has terminated then the PCI7x21 PCI7x11 cont
193. V tolerant I Os 288 ball PBGA Integrated 1394a 2000 OHCI Two Port PHY Link Layer GHK or ZHK Controller with Dedicated Flash Media Socket PCI7611 Single Socket CardBus and UltraMedia Controller with 3 3 V 5 V tolerant I Os 288 ball PBGA Integrated 1394a 2000 OHCI Two Port PHY Link Layer GHK or ZHK Controller with Dedicated Flash Media Socket PCI7411 Single Socket CardBus and UltraMedia Controller with 3 3 V 5 V tolerant I Os 288 ball PBGA Integrated 1394a 2000 OHCI Two Port PHY Link Layer GHK or ZHK Controller with Dedicated Flash Media Socket 2 Terminal Descriptions The PCI7x21 PCI7x11 controller is available in the 288 terminal MicroStar BGA package GHk or the 288 terminal lead free Pb atomic number 82 MicroStar BGA package ZHK Figure 2 1 is a pin diagram of the PCI7621 package Figure 2 2 is a pin diagram of the PCI7421 package Figure 2 3 is a pin diagram of the PCI7611 package Figure 2 4 is a pin diagram of the PCI7411 package TPBOP TPAOP PBIASO ITPBIAS1 VSSPLL PHY_ TEST_ MA XO MFUNC3 MFUNC4 VSSPLL CNA B CAD1 B_D4 B_CAD2 18_D11 B_CADO 8_D3 MFUNCO MFUNC5 DEVSEL B_CAD4 18_D12 B_RSVD IB_D14 B CAD5 8_D6 B_CAD6 IB_D13 CLK_48 SDA MFUNC1 B_CAD3 8_D5 B_CAD8 IB_D15 B_CAD7 IB_D7 B_CC BE0 1B CET B CAD9 18_A10 sc DATA SC CD SC OC SC_ PWR_ CTRL ISPKROUT
194. W Rw Rw Rw Rw Default Register Subsystem access Offset 8Ch Type Read Write Default 0000 0000h Table 12 16 Subsystem Access Register Description FIELD NAME TYPE DESCRIPTION 31 16 SubsystemID RW Subsystem device ID The value written to this field is aliased to the subsystem ID register at PCI offset 2Eh 15 0 SubsystemVendorlD RW Subsystem vendor ID The value written to this field is aliased to the subsystem vendor ID register at PCI offset 2Ch 12 24 Diagnostic Register This register enables the diagnostic modes See Table 12 17 for a complete description of the register contents All bits in this register are reset by GRST only Bt 31 30 29 28 27 26 25 2a 23 22 21 20 19 18 17 16 Name Diagnostic fee RIR R R RIR R RIR R R R R R R ew etn a fe fe le te ea fe Pe a ee fe de ps 4 3 18 13 1 10 o e 7 Diagnostic CM NN A fee RIRLR R RIR R RIR R R R R R R R petan o o o fo fo fo fo fo fo fo fo fo fo fo fo lo Register Diagnostic Type Read only Read Write Offset 90h Default 0000 0000h Table 12 17 Diagnostic Register Description BIT SIGNAL TYPE FUNCTION 31 17 RSVD R Reserved Bits 31 17 return Os when read DIAGNOSTIC Diagnostic test bit This test bit shortens the card detect debounce times for simulation and TDL 15 0 RSVD R Reserved Bits 15 0 return Os when read 12 15 12 25 Slot 0 3 3 V
195. Write Read only Default 0000 0000h Table 7 20 PCI Miscellaneous Configuration Register Description FIELD NAME TYPE DESCRIPTION 31 16 RSVD Reserved Bits 31 16 return Os when read 15 PME_D3COLD PME support from D3colg This bit programs bit 15 PME_D3COLD in the power management t capabilities register at offset 46h in the PCI configuration space see Section 7 19 14 12 RSVD R Reserved Bits 14 12 return Os when read PCI 2 3 Enable The PCI7x21 PCI7x11 1394 OHCI function always conforms to the PCI 2 3 Na PCI2 SEN specification Therefore this bit is tied to 0 Ignore IntMask msterIntEnable bit for PME generation When set this bit causes the PME generation behavior to be changed as described in Section 3 8 When set this bit also causes bit 26 of the OHCI ignore mstrlntEna Vendor ID register at OHCI offset 40h see Section 8 15 to read 1 otherwise bit 26 reads 0 for pme 0 PME behavior generated from unmasked interrupt bits and IntMask masterIntEnable bit default 1 PME generation does not depend on the value of IntMask masterIntEnable This field selects the read command behavior of the PCI master for read transactions of greater than two data phases For read transactions of one or two data phases a memory read command is used The default of this field is 00 This register is loaded by the serial EEPROM word 12 bits 1 0 10t MR ENHANCE 00 Memory read line default 01 Memory read
196. a RSCU ASCU ascu nou RSCU ascu ascu ascu RSCU ascu ascu ASCU olo x x x x x x x x Jo x x Interrupt event Deta 0 o fo jo of of xt xt xtxtxtxtxt xt xt x Register Interrupt event Offset 80h set register 84h clear register returns the content of the interrupt event register bit wise ANDed with the interrupt mask register when read Type Read Set Clear Update Read Set Clear Read Update Read only Default XXXX OXXXh Table 8 15 Interrupt Event Register Description TYPE DESCRIPTION 31 30 Reserved Bits 31 and 30 return 0 when read Reserved Bit 28 returns 0 when read ack_tardy RSCU Bit 27 is set to 1 when bit 29 AckTardyEnable in the host controller control register at OHCI offset 50h 54h see Section 8 16 is set to 1 and any of the following conditions occur a Data is present in a receive FIFO that is to be delivered to the host b The physical response unit is busy processing requests or sending responses c The PCI7x21 PCI7x11 controller sent an ack_tardy acknowledgment phyRegRevd RSCU The PCI7x21 PCI7x11 controller has received a PHY register data byte which can be read from bits 23 16 in the PHY layer control register at OHCI offset ECh see Section 8 33 cycleTooLong RSCU If bit 21 cycleMaster in the link control register at OHCI offset EOh E4h see Section 8 31 is set to 1 then this indicates that over 125 us has elapsed between the start of sending a cycle start pac
197. a a23 Mangi 6_A18 ATORD moe A_D7 A_D12 A_CSTSCHG A_BVD1 A CSERR A CAD26 A CAD23 A CAD21 A_CAD18 A_CIRDY A_CGNT a_CC BET A_CAD12 A_CAD10 A_RSVD A CAD1 stscraan AWAIT MALAO A_A3 0_A5 MAA7 A_A15 AWE A_A8 A_A11 HA D14 A_D4 AA CAUDIO JIN BVD2 A CVS1 A CAD25 VCCA ACRST A CAD17A CTRDY A CSTOP A CAD16 A CAD9 A CAD5 A CAD2 SPER NANST A A1 IA RESET A_A24 A_A22 A_A20 I A A17 VCCA NA A10 A_D6 A D11 Figure 2 4 PCI7411 GHK ZHK Package Terminal Diagram Table 2 1 lists the terminal assignments arranged in terminal number order with corresponding signal names for both CardBus and 16 bit PC Cards for the PCI7421 and PCI7621 GHK packages Table 2 2 and Table 2 3 list the terminal assignments arranged in alphanumerical order by signal name with corresponding terminal numbers for the GHK package Table 2 2 is for CardBus signal names and Table 2 3 is for 16 bit PC Card signal names Terminal E5 on the GHK package is an identification ball used for device orientation 2 4 TERMINAL NUMBER A02 A03 A A A06 07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C01 ojo aja gt Q O NO C03 Table 2 1 Signal Names by GHK Terminal Number SIGNAL NAME TERMINAL CardBus PC Car
198. aMedia PC Card controller IEEE 1394 open HCI host controller and PHY and flash media controller This high performance integrated solution provides the latest in PC Card IEEE 1394 SD MMC Memory Stick PRO SmartMedia and XD technology For the remainder of this document the PCI7x21 controller refers to the PCI7621 and PCI7421 controllers and the PC17x11 controller refers to the PCI7611 and PCI7411 controllers 1 1 Controller Functional Description 1 1 1 PCI7621 Controller The PCI7621 controller is a six function PCI controller compliant with PCI Local Bus Specification Revision 2 3 Functions 0 and 1 provide the independent PC Card socket controllers compliant with the PC Card Standard Release 8 1 The PCI7621 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards and supports any combination of Smart Card Flash Media 16 bit CardBus and USB custom card interface PC Cards in the two sockets powered at 5 V or 3 3 V as required All card signals are internally buffered to allow hot insertion and removal without external buffering The PCI7621 controller is register compatible with the Intel 82365SL DF ExCA controller The PCI7621 internal data path logic allows the host to access 8 16 and 32 bit cards using full 32 bit PCI cycles for maximum performance Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting The PCI7621 c
199. ad pri_req This field specifies the maximum number of priority arbitration requests for asynchronous request packets that the link is permitted to make of the PHY layer during a fairness interval The default value for this field is 00h 8 27 8 31 Link Control Register The link control set clear register provides the control flags that enable and configure the link core protocol portions of the PCI7x21 PC17x11 controller It contains controls for the receiver and cycle timer See Table 8 23 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 Name Link control l AAA AA 15 13 10 8 7 Name Link control me R R R r r Asc Asc r r res r r rR rR rRIA Deta o o o fo fof xP xpotototototototot o Register Link control Offset EOh set register E4h clear register Type Read Set Clear Update Read Set Clear Read only Default 00X0 OX00h Table 8 23 Link Control Register Description FIELD NAME TYPE DESCRIPTION 31 23 RSVD Reserved Bits 31 23 return Os when read When bit 22 is set to 1 the cycle timer uses an external source CYCLEIN to determine when to roll over the cycle timer When this bit is cleared the cycle timer rolls over when the timer reaches cycleSource 3072 cycles of the 24 576 MHz clock 125 us cycleMaster RSCU When bit 21 is set to 1 the PCI7x21 PCI7x11 controller is root and it generates a cycle start packet every time t
200. aded by the serial EEPROM from the enhancements field corresponds to bit 23 programPhyEnable in the host controller control register at OHCI offset 50h 54h see Section 8 16 enab_dv_ts Reserved Bits 5 3 return Os when read 23 RSVD R Reserved Bit 2 returns O when read Enable acceleration enhancements OHCI Lynx compatible When bit 1 is set to 1 the PHY layer is notified that the link supports the IEEE Std 1394a 2000 acceleration enhancements that is ack accelerated fly by concatenation etc It is recommended that this bit be set to 1 The default value for this bit is O R Reserved Bit 0 returns 0 when read This bit is cleared only by the assertion of GRST enab_accel 9 5 Timestamp Offset Register The value of this register is added as an offset to the cycle timer value when using the MPEG DV and CIP enhancements A timestamp offset register is implemented per isochronous transmit context The n value following the offset indicates the context number n 0 1 2 3 7 These registers are programmed by software as appropriate See Table 9 4 for a complete description of the register contents Timestamp offset CO ampo SS o aw A A A A AA ew rw a oe o lo o o lolo o lololo o o lolo fo o Bit 15 14 13 12 11 10 8 7 4 Name Timestamp offset aa aa veran o o o o o o o o o o lololo lololo Register Timestamp offset Offset AQ0h 4n Type Read Write Read only
201. age regulator is enabled VR_EN 0 V When the internal voltage regulator is disabled 1 5 V must be supplied to this terminal and a parallel combination of high frequency decoupling capacitors near the terminal is suggested such as 0 1 uF and 0 001 uF Lower frequency 10 uF filtering capacitors are also recommended 3 3 V PLL circuit power terminal A parallel combination of high frequency decoupling capacitors near the terminal is suggested such as 0 1 uF and 0 001 uF Lower frequency 10 yF filtering capacitors are also recommended This supply terminal is separated from AVDD internal to the controller to provide noise isolation It must be tied to a low impedance point on the circuit board When the internal voltage regulator is disabled VR_EN 3 3 V no voltage is required to be supplied to this terminal Internal voltage regulator enable Active low 1 5 V output from the internal voltage regulator PLL circuit ground terminal This terminal must be tied to the low impedance circuit board ground plane 0 1 uF 0 001 uF and 10 uF capacitors tied to 0 1 uF 0 001 uF and 10 uF capacitors tied to 0 1 uF 0 001 pF capacitors tied to Pulled directly to GND 0 1 uF capacitor tied to GND Table 2 5 PC Card Power Switch Terminals Internal pullup pulldown resistors power rail designation and pin strapping are not applicable for the power switch terminals DESCRIPTION INPUT OUTPUT COMPONENTS Power switch
202. agement extension register provides extended power management features not applicable to the PCI7x21 PCI7x11 controller thus it is read only and returns O when read See Table 7 18 for a complete description of the register contents 15 14 ts 2 1 to 9 8 Power management extension Name w R R R R R R R R R R R R R CA EA e E ODA E AO a EA Register Power management extension Offset 4Ah Type Read only Default 0000h Table 7 18 Power Management Extension Registers Description FIELD NAME TYPE DESCRIPTION 15 0 RSVD R Reserved Bits 15 0 return Os when read 7 22 PCI PHY Control Register The PCI PHY control register provides a method for enabling the PHY CNA output See Table 7 19 for a complete description of the register contents PCI PHY control Bit 31 30 29 pz SS A A y ee Default PCI PHY control r r w rR R Rw Rw Rw Rw RW 0 0 0 0 0 1 0 0 0 Default 0 0 0 0 0 0 0 Register PCI PHY control Offset ECh Type Read Write Read only Default 0000 0008h Table 7 19 PCI PHY Control Register Description BIT FIELD NAME TYPE DESCRIPTION 31 8 RSVD R Reserved Bits 31 8 return Os when read T CNAOUT RW When bit 7 is set to 1 the PHY CNA output is routed to terminal P18 When implementing a serial EEPROM this bit is loaded via the serial EEPROM as defined by Table 3 9 and must be 1 for normal operation 6 5 RSVD Reserved Bits 6 5 retur
203. ain burst transfers for nearly 64 us and thus request a large value be programmed in bits 15 8 of the PCI7x21 PCI7x11 latency timer and class cache line size register at offset OCh in the PCI configuration space see Section 11 6 11 15 Maximum Latency Register The maximum latency register contains the maximum latency value for the flash media controller core Bit 7 6 5 4 3 2 1 0 Maximum latency Name amining O esn o o o o fo fs o po Register Maximum latency Offset 3Eh Type Read Update Default 04h Table 11 10 Maximum Latency Register Description DESCRIPTION Maximum latency The contents of this field may be used by host BIOS to assign an arbitration priority level FIELD NAME MAX LAT to the flash media controller The default for this register indicates that the flash media controller may need to access the PCI bus as often as every 0 25 us thus an extremely high priority level is requested The contents of this field may also be loaded through the serial EEPROM 11 16 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked list capability item and provides a pointer to the next capability item See Table 11 11 for a complete description of the register contents Bit 15 14 13 12 1 10 9 8 7 te 5 4 3 2 1 Name Capability ID and next item pointer Type R R R R R R Default 0 0 0 0 0 0 Register Capability ID
204. ains set to 1 while the software reset is in progress and reverts back to 0 when the reset has completed 15 0 Reserved Bits 15 0 return Os when read 8 17 Self ID Buffer Pointer Register The self ID buffer pointer register points to the 2K byte aligned base address of the buffer in host memory where the self ID packets are stored during bus initialization Bits 31 11 are read write accessible Bits 10 0 are reserved and return Os when read Self ID buffer pointer R R R R R R R R R R R pon xfxtxtxtxtetoftofetofofefofopefo Register Self ID buffer pointer Offset 64h Type Read Write Read only Default XXXX XX00h 8 18 Self ID Count Register The self ID count register keeps a count of the number of times the bus self ID process has occurred flags self ID packet errors and keeps a count of the self ID data in the self ID buffer See Table 8 12 for a complete description of the register contents 24 23 Self ID count Register Self ID count Offset 68h Type Read Update Read only Default XOXX 0000h Table 8 12 Self ID Count Register Description FIELD NAME TYPE DESCRIPTION selfIDError When bit 31 is set to 1 an error was detected during the most recent self ID packet reception The contents of the self ID buffer are undefined This bit is cleared after a self ID reception in which no errors are detected Note that an error can be a hardware error or a host bus wr
205. all nodes have correctly updated their RHBs and Gap_Count values and to ensure that a subsequent new connection to the bus causes the Gap_Count to be set to 63 on all nodes in the bus If this bus reset is initiated by setting the IBR bit to 1 then the RHB and Gap Count field must also be loaded with the correct values consistent with the just transmitted PHY config packet In the PCI7x21 PCI7x11 controller the RHB and Gap_Count are updated to their correct values upon the transmission of the PHY config packet so these values may first be read from register 1 and then rewritten Other than to initiate the bus reset which must follow the transmission of a PHY config packet whenever the IBR bit is set to 1 in order to initiate a bus reset the Gap Count value must also be set to 63 so as to be consistent with other nodes on the bus and the RHB must be maintained with its current value The PHY register 1 must not be written to except to set the IBR bit The RHB and Gap_Count must not be written without also setting the IBR bit to 1 3 34 4 PC Card Controller Programming Model This chapter describes the PCI7x21 PCI7x11 PCI configuration registers that make up the 256 byte PCI configuration header for each PCI7x21 PCI7x11 function There are some bits which affect both CardBus functions but which in order to work properly must be accessed only through function 0 These are called global bits Registers containing one or more global bits are den
206. and 1 The 8 bits of these ea CU to the lower 8 bits of the start address 7 ExCA I O windows 0 and 1 end address low ka mane Default Register ExCA O window 0 end address aa Offset CardBus Socket Address 80Ah Card A ExCA Offset OAh Card B ExCA Offset 4Ah Register ExCA I O window 1 end address low byte Offset CardBus Socket Address 80Eh Card A ExCA Offset OEh Card B ExCA Offset 4Eh Type Read Write Default 00h 5 12 ExCA I O Windows 0 and 1 End Address High Byte Registers These registers contain the high byte of the 16 bit I O window end address for I O windows 0 and 1 The 8 bits of these registers correspond to the upper 8 bits of the end address 7 ExCA I O windows 0 and 1 end address high byte Name Type w w w w w w w w petan o o o o o oo o o Register ExCA I O window 0 end address high byte Offset CardBus Socket Address 80Bh Card A ExCA Offset OBh Card B ExCA Offset 4Bh Register ExCA I O window 1 end address high byte Offset CardBus Socket Address 80Fh Card A ExCA Offset OFh Card B ExCA Offset 4Fh Type Read Write Default 00h 5 14 5 13 ExCA Memory Windows 0 4 Start Address Low Byte Registers These registers contain the low byte of the 16 bit memory window start address for memory windows 0 1 2 3 and 4 The 8 bits of these Hani pin pan to bits A19 A12 of the start address 7 memory 0 EE start address low ae
207. ared by functions 0 and 1 If CSC SMI interrupts are selected then the SMI interrupt is sent as the CSC on a per socket basis The CSC interrupt can be either level or edge mode depending upon the CSCMODE bit in the ExCA global control register ExCA offset 1Eh 5Eh 81Eh see Section 5 20 If IRQ2 is selected by SMIROUTE then the IRQSER signaling protocol supports SMI signaling in the IRQ2 IRQ Data slot In a parallel ISA IRQ system the support for an active low IRQ2 is provided only if IRQ2 is routed to either MFUNG3 or MFUNC6 through the multifunction routing status register PCI offset 8Ch see Section 4 36 3 8 Power Management Overview In addition to the low power CMOS technology process used for the PCI7x21 PCI7x11 controller various features are designed into the controller to allow implementation of popular power saving techniques These features and techniques are as follows Clock run protocol Cardbus PC Card power management 16 bit PC Card power management Suspend mode Ring indicate PCI power management Cardbus bridge power management ACPI support L PCI Bus gt SD MMC MS MSPRO PCI7x21 P SM xD C17x11 1394a Socket PC PC Card Card UltraMedia UltraMedia Card Card T The system connection to GRST is implementation specific GRST must be asserted on initial power up of the PCI7x21 PCI7x11 controller PRST must be asserted for subsequent warm resets Figure 3 13 System Diagram Imp
208. ared to 0 by system hardware reset all ports are enabled for normal operation following system hardware reset The Dis bit is not affected by bus reset Peer_Speed 3 Port peer speed This field indicates the highest speed capability of the peer PHY device connected to the selected port encoded as follows Code Peer Speed 000 100 001 200 010 400 011 111 invalid The Peer_Speed field is invalid after a bus reset until self ID has completed NOTE Peer speed codes higher than 010b S400 are defined in IEEE Std 1394a 2000 However the PCI7x21 PCI7x11 controller is only capable of detecting peer speeds up to S400 10 4 Table 10 4 Page 0 Port Status Register Field Descriptions Continued FIELD SIZE TYPE DESCRIPTION Int_enable 1 RW Port event interrupt enable When the Int_enable bit is set to 1 a port event on the selected port sets the port event interrupt Port_event bit and notifies the link This bit is cleared to 0 by a system hardware reset and is unaffected by bus reset Fault 1 RW Fault This bit indicates that a resume fault or suspend fault has occurred on the selected port and that the port is in the suspended state A resume fault occurs when a resuming port fails to detect incoming cable bias from its attached peer A suspend fault occurs when a suspending port continues to detect incoming cable bias from its attached peer Writing 1 to this bit clears the fault bit to 0 This bit is cleared to 0 by sys
209. at OHCI offset 80h 84h see Section 8 21 are set to 1 this isochronous receive DMA interrupt mask enables interrupt generation isochTx RSC When this bit and bit 6 isochTx in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this isochronous transmit DMA interrupt mask enables interrupt generation RSPkt RSC When this bit and bit 5 RSPkt in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this receive response packet interrupt mask enables interrupt generation When this bit and bit 4 RQPkt in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this receive request packet interrupt mask enables interrupt generation When this bit and bit 3 ARRS in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this asynchronous receive response DMA interrupt mask enables interrupt generation When this bit and bit 2 ARRQ in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this asynchronous receive request DMA interrupt mask enables interrupt generation respTxComplete reqTxComplete When this bit and bit 1 respTxComplete in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this response transmit complete interrupt mask enables interrupt generation When this bit and bit 0 reqTxComplete in the interrupt event register at OHCI
210. available high InitialChannelsAvailableHi Initial channels available low InitialChannelsAvailableLo Node identification NodelD Isochronous cycle timer Isocyctimer Physical request filter low PhysicalUpperBound 120h One or more bits in this register are cleared only by the assertion of GRST Table 8 1 OHCI Register Map Continued DMA CONTEXT REGISTER NAME ABBREVIATION OFFSET A i ContextControlSet 180h synchronous context contro Asynchronous y ContextControlClear 184h ATRQ Asynchronous context command pointer CommandPtr 18Ch Reserved 190h 19Ch ContextControlSet 1A0h Asynchronous context control Asynchronous ContextControlClear 1A4h Reserved 1A8h Response Transmit ATRS Asynchronous context command pointer CommandPtr 1ACh Reserved 1B0h 1BCh A 8 ContextControlSet 1C0h synchronous context contro Asynchronous y ContextControlClear 1C4h ARRQ Asynchronous context command pointer CommandPtr 1CCh Asynchronous ContextControlClear 1E4h ARRS Asynchronous context command pointer CommandPtr 1ECh oa i ContextControlSet 200h 16 n sochronous transmit context contro ContextControlClear 204h 16 n Isochronous Transmit Context n Isoch i n 0 1 2 3 7 ee a cane 20Ch 16 n i ContextControlSet 400h 32 n sochronous receive context contro ContextControlClear 404h 32 n Isochronous Receive Context n n 0 1 2 3 de
211. aw Aw wi aw ra rR r A _R rR A R RA RAR Detaut o o o fo foe fo toto ftototototototo Register Flash media base address Offset 10h Type Read Write Read only Default 0000 0000h Table 11 7 Flash Media Base Address Register Description FIELD NAME TYPE DESCRIPTION 31 13 Base address This field specifies the upper bits of the 32 bit starting base address RSVD R Reserved Bits 12 4 return Os when read to indicate that the size of the base address is 8192 bytes 3 PREFETCHABLE Prefetchable Since this base address is not prefetchable bit 3 returns 0 when read 2 1 RSVD Reserved Bits 2 1 return Os when read o MEM INDICATOR DR la space indicator Bit 0 is hardwired to 0 to indicate that the base address maps into memory 11 9 Subsystem Vendor Identification Register The subsystem identification register used for system and option card identification purposes may be required for certain operating systems This read only register is initialized through the EEPROM and can be written through the subsystem access register at PCI offset 50h see Section 11 All bits in this register are reset by GRST only CONCE oe Te e nano UU ea Default Register Subsystem vendor identification Offset 2Ch Type Read Update Default 0000h 11 10 Subsystem Identification Register The subsystem identification register used for system and option card identification purposes may be requi
212. bit The choice of these two methods is based on bit 2 interrupt flag clear mode select in the ExCA global control register CB offset 81Eh see Section 5 20 See Table 5 7 for a complete description of the register contents Bitoo 07 06 05 a J s 2 1 o ExCA card status change Name EXC cadstatuschange mwe R R R R R R R R petan o o0 oo o o o o o Register ExCA card status change Type Read only Offset CardBus socket address 804h Card A ExCA offset 04h Card B ExCA offset 44h Default 00h Table 5 7 ExCA Card Status Change Register Description SIGNAL TYPE FUNCTION RSVD oR Reserved Bits 7 4 return Os when read Card detect change Bit 3 indicates whether a change on CD1 or CD2 occurred at the PC Card interface This bit is encoded as CPEHANGE 0 No change detected on either CD1 or CD2 1 Change detected on either CD1 or CD2 Ready change When a 16 bit memory is installed in the socket bit 2 includes whether the source of a PCI7x21 PCI7x11 interrupt was due to a change on READY at the PC Card interface indicating that the PC Card is now ready to accept new data This bit is encoded as READYCHANGE 0 No low to high transition detected on READY default 1 Detected low to high transition on READY When a 16 bit I O card is installed bit 2 is always 0 Battery warning change When a 16 bit memory card is installed in the socket bit 1 indicates whether the sour
213. board and device variations Trade offs between frequency tolerance and stability may be made as long as the total frequency variation is less than 100 ppm For example the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible variation due to the crystal alone Crystal aging also contributes to the frequency variation 3 6 Serial EEPROM Interface The PCI7x21 PCI7x11 controller has a dedicated serial bus interface that can be used with an EEPROM to load certain registers in the PCI7x21 PCI7x11 controller The EEPROM is detected by a pullup resistor on the SCL terminal See Table 3 9 for the EEPROM loading map 3 6 1 Serial Bus Interface Implementation The PCI7x21 PCI7x11 controller drives SCL at nearly 100 kHz during data transfers which is the maximum specified frequency for standard mode 12C The serial EEPROM must be located at address A0h Some serial device applications may include PC Card power switches card ejectors or other devices that may enhance the user s PC Card experience The serial EEPROM device and PC Card power switches are discussed in the sections that follow 3 6 2 Accessing Serial Bus Devices Through Software The PCI7x21 PCI7x11 controller provides a programming mechanism to control serial bus devices through software The programming is accomplished through a doubleword of PCI configuration space at offset BOh Table 3
214. both DMA capabilities and support for SD suspend resume 1 1 5 Multifunctional Terminals Various implementation specific functions and general purpose inputs and outputs are provided through eight multifunction terminals These terminals present a system with options in PC PCI DMA serial and parallel interrupts PC Card activity indicator LEDs flash media LEDs and other platform specific signals PCI complaint general purpose events may be programmed and controlled through the multifunction terminals and an ACPI compliant programming interface is included for the general purpose inputs and outputs 1 1 6 PCI Bus Power Management The PCI7x21 PCI7x11 controller is compliant with the latest PCI Bus Power Management Specification and provides several low power modes which enable the host power system to further reduce power consumption 1 1 7 Power Switch Interface The PCI7x21 PCI7x11 controller also has a three pin serial interface compatible with the Texas Instruments TPS2228 default TPS2226 TPS2224 and TPS2223A power switches All four power switches provide power to the CardBus socket s on the PCI7x21 PCI7x11 controller The power to each dedicated socket is controlled through separate power control pins Each of these power control pins can be connected to an external 3 3 V power switch 1 2 Features The PCI7x21 PCI7x11 controller supports the following features PC Card Standard 8 1 compliant PCI Bus Power Management Interfac
215. bus control and status register PCI offset B3h see Section 4 50 Bit 3 SBDETECT in this register indicates whether or not the PCI7x21 PCI7x11 serial ROM circuitry detects the pullup resistor on SCL Any undefined condition such as a missing acknowledge results in bit 0 ROM_ERR being set Bit 4 ROMBUSY is set while the subsystem ID register is loading serial ROM interface is busy The subsystem vendor ID for functions 2 and 3 is also loaded through EEPROM The EEPROM load data goes to all four functions from the serial EEPROM loader Vcc eo SCL o SDA PCI7x21 PCI7x11 Figure 3 4 Serial ROM Application 3 4 4 Functions 0 and 1 CardBus Subsystem Identification The subsystem vendor ID register PCI offset 40h see Section 4 26 and subsystem ID register PCI offset 42h see Section 4 27 make up a doubleword of PCI configuration space for functions 0 and 1 This doubleword register is used for system and option card mobile dock identification purposes and is required by some operating systems Implementation of this unique identifier register is a PC 99 PC 2001 requirement The PCI7x21 PCI7x11 controller offers two mechanisms to load a read only value into the subsystem registers The first mechanism relies upon the system BIOS providing the subsystem ID value The default access mode to the subsystem registers is read only but can be made read write by clearing bit 5 SUBSYSRW in the system control register
216. by Sony Memory Stick Pro Memory Stick Version 2 0 same physical dimensions of MS with higher speed data exchange and higher data capacity than conventional Memory Stick R C l MultiMediaCard Specified by the MMC Association and scope is encompassed by the SD Flash specification SP Serial peripheral interface a general purpose synchronous serial interface For more information see the Multimedia Card System Specification version 3 2 SSFDC Solid State Floppy Disk Card The SSFDC Forum specifies SmartMedia TI Smart Card driver A qualified software component provided by Texas Instruments that loads when an UltraMedia based Smart Card adapter is inserted into a PC Card slot This driver is logically attached to a CIS provided by the PCI7621 when the adapter and media are both inserted UltraMedia De facto industry standard promoted by Texas Instruments that integrates CardBus Smart Card Memory Stick MultiMediaCard Secure Digital and SmartMedia functionality into one controller Extreme Digital small form factor flash based on SmartMedia cards developed by Fuji Film and Olympus Optical 1 6 Ordering Information ORDERING NUMBER nwe J VOLTAGE PACKAGE PCI7621 Dual Socket CardBus and UltraMedia Controller with 3 3 V 5 V tolerant I Os 288 ball PBGA Integrated 1394a 2000 OHCI Two Port PHY Link Layer GHK or ZHK Controller with Dedicated Flash Media Socket PC17421 Dual Socket CardBus and UltraMedia Controller with 3 3 V 5
217. by a stop condition which is signaled by a low to high transition of SDA while SCL is in the high state as shown in Figure 3 7 Data on SDA must remain stable during the high state of the SCL signal as changes on the SDA signal during the high state of SCL are interpreted as control signals that is a start or a stop condition 3 11 ck OO AE GU E CP Y Start Stop Change of Condition Condition Data Allowed Data Line Stable Data Valid Figure 3 7 Serial Bus Start Stop Conditions and Bit Transfers Data is transferred serially in 8 bit bytes The number of bytes that may be transmitted during a data transfer is unlimited however each byte must be completed with an acknowledge bit An acknowledge ACK is indicated by the receiver pulling the SDA signal low so that it remains low during the high state of the SCL signal Figure 3 8 illustrates the acknowledge protocol SCL From Master manse NL AA AA XA Y By Transmitter Simic SDA Output gt 2 By Receiver Figure 3 8 Serial Bus Protocol Acknowledge 1 2 3 7 8 9 The PCI7x21 PCI7x11 controller is a serial bus master all other devices connected to the serial bus external to the PC17x21 PC17x11 controller are slave devices As the bus master the PCI7x21 PCI7x11 controller drives the SCL clock at nearly 100 kHz during bus cycles and places SCL in a high impedance state zero frequency during
218. by using bit 4 D3 COLD in the general control register see Section 13 22 14 PME D3HOT PME support This 4 bit field indicates the power states from which the Smart Card interface may 13 PME D2 assert PME This field returns a value of 1111b by default indicating that PME may be asserted from the D3hot D2 D1 and DO power states 12 PME_D1 11 PME_DO D2_SUPPORT D2 support Bit 10 is hardwired to 1 indicating that the Smart Card controller supports the D2 power state D1_SUPPORT D1 support Bit 9 is hardwired to 1 indicating that the Smart Card controller supports the D1 power state AUX_CURRENT Auxiliary current This 3 bit field reports the 3 3 VaUx auxiliary current requirements When bit 15 PME_D3COLD is cleared this field returns 000b otherwise it returns 001b 000b Self powered 001b 55 mA 3 3 Vayx maximum current required Device specific initialization This function requires device specific initialization RSVD Reserved Bit 4 returns 0 when read PME_CLK PM_VERSION PME clock This bit returns 0 when read indicating that the PCI clock is not required for the Smart Card controller to generate PME Power management version This field returns 010b when read indicating that the Smart Card controller is compatible with the registers described in the PC Bus Power Management Interface Specification Revision 1 1 13 11 13 19 Power Management Control and Status Register The
219. ce of a PCI7x21 PCI7x11 interrupt was due to a battery low warning condition This bit is encoded as BATWARN 0 No battery warning condition default 1 Detected battery warning condition When a 16 bit I O card is installed bit 1 is always 0 Battery dead or status change When a 16 bit memory card is installed in the socket bit 0 indicates whether the source of a PCI7x21 PCI7x11 interrupt was due to a battery dead condition This bit is encoded as BATDEAD 0 STSCHG deasserted default 1 STSCHG asserted Ring indicate When the PCI7x21 PCI7x11 is configured for ring indicate operation bit O indicates the status of RI T These are PME context bits and can be cleared only by the assertion of GRST when PME is enabled If PME is not enabled then these bits are cleared by the assertion of PRST or GRST 5 9 5 6 ExCA Card Status Change Interrupt Configuration Register This register controls interrupt routing for CSC interrupts as well as masks unmasks CSC interrupt sources See Table 5 8 for a complete description of the register contents 7 Name ExCA card status change interrupt configuration Register ExCA card status change interrupt configuration Offset CardBus Socket Address 805h Card A ExCA Offset 05h Card B ExCA Offset 45h Type Read Write Default 00h Table 5 8 ExCA Card Status Change Interrupt Configuration Register Description BIT SIGNAL TYPE FUNCTION Interrupt select for card status chan
220. ce on a word boundary hence bit 0 is read only returning 1 when read As specified in the PCI to PCMCIA CardBus Bridge Register Description specification this register is shared by functions 0 and 1 See the ExCA register set description in Section 5 for register offsets All bits in this register are reset by GRST only m lao ll Tl T Name PO Card Teen IF legacy mode based DD Deraan 0 PC Card 16 bit I F legacy mode base address ame PO GORE legacy mode baseadess O O O OOOO OOO U O na O AE aa aaa A Fo o o o o o o o o o o o fo fo 1 Register PC Card 16 bit I F legacy mode base address Offset 44h Functions 0 1 Type Read only Read Write Default 0000 0001h 4 29 System Control Register System level initializations are performed through programming this doubleword register Some of the bits are global in nature and must be accessed only through function O See Table 4 8 for a complete description of the register contents Register System control Offset 80h Functions 0 1 Type Read only Read Write Default 0844 9060h Table 4 8 System Conirol Register Description BIT SIGNAL FUNCTION Serial input stepping In serial PCI interrupt mode these bits are used to configure the serial stream PCI interrupt frames and can be used to accomplish an even distribution of interrupts signaled on the four PCI interrupt slots A ee 31 30 SER STEP RW 00 INTA INTB INTC INTD signal in I
221. ceive from isochronous channel number 43 When bit 10 is set to 1 the controller is enabled to receive from isochronous channel number 42 sc 7 isoChannel39 R When bit 7 is set to 1 the controller is enabled to receive from isochronous channel number 39 BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 8 16 Table 8 13 Isochronous Receive Channel Mask High Register Description Continued FIELD NAME DESCRIPTION isoChannel38 RSC When bit 6 is set to 1 the controller is enabled to receive from isochronous channel number 38 isoChannel37 R When bit 5 is set to 1 the controller is enabled to receive from isochronous channel number 37 SC 8 20 Isochronous Receive Channel Mask Low Register 6 EA The isochronous receive channel mask low set clear register enables packet receives from the lower 32 isochronous data channels See Table 8 14 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Isochronous receive channel mask low nb aaa channelmaskiow SS pan x x x AAA AAA AAN am 193 04 13 12 ols 0 7 6 5 4 3 2 1 o0 ame O co a mala OOOO OOOO O Dean x x x AAN Register Isochronous receive channel mask low Offset 78h set register 7Ch clear register Type Read Set Clear Default XXXX XXXXh Table 8 14 Isochronous Receive Channel Mask Low
222. ck using the CLKRUN protocol under any of the following conditions A 16 bit PC Card IREQ or a CardBus CINT has been asserted by either card A CardBus CBWAKE CSTSCHG or 16 bit PC Card STSCHG RI event occurs in the socket A CardBus attempts to start the CCLK using CCLKRUN A CardBus card arbitrates for the CardBus bus using CREQ A 1394 device changes the status of the twisted pair lines from idle to active Bit 1 KEEPCLK in the system control register PCI offset 80h see Section 4 29 is set Data is in any of the FIFOs receive or transmit The master state machine is busy There are pending interrupts 3 8 4 CardBus PC Card Power Management The PCI7x21 PCI7x11 controller implements its own card power management engine that can turn off the CCLK to a socket when there is no activity to the CardBus PC Card The PCI clock run protocol is followed on the CardBus CCLKRUN interface to control this clock management 3 22 3 8 5 16 Bit PC Card Power Management The COE bit bit 7 of the ExCA power control register ExCA offset 02h 42h 802h see Section 5 3 and PWRDWN bit bit 0 of the ExCA global control register ExCA offset 1Eh 5Eh 81Eh see Section 5 20 are provided for 16 bit PC Card power management The COE bit places the card interface in a high impedance state to save power The power savings when using this feature are minimal The COE bit resets the PC Card when used and the PWRDWN bit does not Furthermore the PWRDWN bit
223. coded as 0 Disables host interrupt generation default 1 Enables host interrupt generation Battery dead enable This bit enables disables a battery dead condition on a memory PC Card or assertion of the STSCHG I O PC Card signal to generate a CSC interrupt BATDEADEN RW 3 k 0 Disables host interrupt generation default 1 Enables host interrupt generation t This bit is cleared only by the assertion of GRST when PME is enabled If PME is not enabled then this bit is cleared by the assertion of PRST or GRST 5 7 ExCA Address Window Enable Register The ExCA address window enable register enables disables the memory and I O windows to the 16 bit PC Card By default all windows to the card are disabled The PCI7x21 PCI7x11 controller does not acknowledge PCI memory or I O cycles to the card if the corresponding enable bit in this register is 0 regardless of the programming of the memory or I O window start end offset address registers See Table 5 9 for a complete description of the register contents Bee 2 6e 5 4 s 2 1 o Name ExCA address window enable mwe w w R w w w w w Register ExCA address window enable Type Read only Read Write Offset CardBus socket address 806h Card A ExCA offset 06h Card B ExCA offset 46h Default 00h Table 5 9 ExCA Address Window Enable Register Description SIGNAL TYPE FUNCTION 1 0 window 1 enable Bit 7 enables disables I O window 1 fo
224. control method associated with the pending status bit The control method can then control the hardware by manipulating the hardware control bits or by investigating child status bits and calling their respective control methods A hierarchical implementation would be somewhat limiting however as upstream devices would have to remain in some level of power state to report events For more information of ACPI see the Advanced Configuration and Power Interface ACPI Specification 3 8 12 Master List of PME Context Bits and Global Reset Only Bits PME context bit means that the bit is cleared only by the assertion of GRST when the PME enable bit bit 8 of the power management control status register PCI offset A4h see Section 4 44 is set If PME is not enabled then these bits are cleared when either PRST or GRST is asserted The PME context bits functions 0 and 1 are Bridge control register PCI offset 3Eh see Section 4 25 bit 6 System control register PCI offset 80h see Section 4 29 bits 10 8 Power management control status register PCI offset A4h see Section 4 44 bit 15 ExCA power control register ExCA 802h 842h see Section 5 3 bits 7 5 82365SL mode only 4 3 1 0 ExCA interrupt and general control ExCA 803h 843h see Section 5 4 bits 6 5 e ExCA card status change register ExCA 804h 844h see Section 5 5 bits 3 0 3 27 ExCA card status change interrupt configuration register EXCA 805h 845h see Se
225. controller always uses a store and forward operation when the asynchronous transmit retries register at OHCI offset 08h see Section 8 3 is cleared These bits are cleared only by the assertion of GRST Table 7 21 Link Enhancement Control Register Description Continued FIELD NAME TYPE DESCRIPTION RSVD Reserved Bit 11 returns 0 when read da RSVD RSVD a aw ap RSV a Enable MPEG CIP timestamp enhancement When bit 9 is set to 1 the enhancement is enabled for MPEG CIP transmit streams FMT 20h The default value for this bit is 0 Reserved Bit 9 returns 0 when read Enable DV CIP timestamp enhancement When bit 8 is set to 1 the enhancement is enabled for DV CIP transmit streams FMT 00h The default value for this bit is 0 Enable asynchronous priority requests OHCI Lynx compatible Setting bit 7 to 1 enables the link to respond to requests with priority arbitration It is recommended that this bit be set to 1 The default value for this bit is 0 This bit is not assigned in the PCI7x21 PCI7x11 follow on products because this bit location loaded by the serial EEPROM from the enhancements field corresponds to bit 23 programPhyEnable in the host controller control register at OHCI offset 50h 54h see Section 8 16 p N eo Reserved Bits 5 3 return Os when read Reserved Bit 2 returns 0 when read Enable acceleration enhancements OHCI Lynx compatible When bit 1 is set to 1 the
226. controller in a high impedance state and gates the PCLK signal internally to the controller unless a PCI transaction is currently in process GNT is asserted It is important that the PCI bus not be parked on the PCI7x21 PCI7x11 controller when SUSPEND is asserted because the outputs are in a high impedance state The GPIOs MFUNC signals and RI OUT signal are all active during SUSPEND unless they are disabled in the appropriate PCI7x21 PCI7x11 registers 3 8 8 Ring Indicate The Rl OUT output is an important feature in power management allowing a system to go into a suspended mode and wake up on modem rings and other card events Tl designed flexibility permits this signal to fit wide platform requirements RI_OUT on the PCI7x21 PCI7x11 controller can be asserted under any of the following conditions e A 16 bit PC Card modem in a powered socket asserts RI to indicate to the system the presence of an incoming call e A powered down CardBus card asserts CSTSCHG CBWAKE requesting system and interface wake up e A powered CardBus card asserts CSTSCHG from the insertion removal of cards or change in battery voltage levels Figure 3 15 shows various enable bits for the PCI7x21 PCI7x11 RI OUT function however it does not show the masking of CSC events See Table 3 10 for a detailed description of CSC interrupt masks and flags PC Card Socket A RINGEN PC Card Socket B RI_OUT Function RIENB D Pm F
227. ction etc The terminal numbers are also listed for convenient reference 2 13 Table 2 4 Power Supply Terminals Output description internal pullup pulldown resistors and the power rail designation are not applicable for the power VO EXTERNAL PIN STRAPPING DESCRIPTION INPUT COMPONENTS IF UNUSED supply terminals TERMINAL N12 U14 R13 R14 7 G07 G08 G13 H13 JO9 J10 J11 KO9 K10 K11 L08 LO9 L10 L11 L12 M08 A05 A11 D19 K19 W03 W10 VDPLL 15 VDPLL 33 VR PORT H01 M19 VSSPLL P14 T17 Analog circuit ground terminals Analog circuit power terminals A parallel combination of high frequency decoupling capacitors near each terminal is suggested such as 0 1 uF and 0 001 uF Lower frequency 10 F filtering capacitors are also recommended These supply terminals are separated from VDPLL_33 internal to the controller to provide noise isolation They must be tied to a low impedance point on the circuit board Digital ground terminal Power supply terminal for I O and internal voltage regulator Clamp voltage for PC Card A interface Matches card A signaling environment 5 V or 3 3 V Clamp voltage for PC Card B interface Matches card B signaling environment 5 V or 3 3 V Clamp voltage for PCI and miscellaneous l O 5 V or 3 3 V PWR 1 5 V PLL circuit power terminal An external capacitor 0 1 uF recommended must be placed between terminals T18 and T17 VSSPLL when the internal volt
228. ction 5 6 bits 3 0 ExCA card detect and general control register ExCA 816h 856h see Section 5 19 bits 7 6 Socket event register CardBus offset 00h see Section 6 1 bits 3 0 Socket mask register CardBus offset 04h see Section 6 2 bits 3 0 Socket present state register CardBus offset 08h see Section 6 3 bits 13 7 5 1 Socket control register CardBus offset 10h see Section 6 5 bits 6 4 2 0 Global reset only bits as the name implies are cleared only by GRST These bits are never cleared by PRST regardless of the setting of the PME enable bit The GRST signal is gated only by the SUSPEND signal This means that assertion of SUSPEND blocks the GRST signal internally thus preserving all register contents Figure 3 13 is a diagram showing the application of GRST and PRST The global reset only bits functions O and 1 are Status register PCI offset O6h see Section 4 5 bits 15 11 8 Secondary status register PCI offset 16h see Section 4 14 bits 15 11 8 Subsystem vendor ID register PCI offset 40h see Section 4 26 bits 15 0 Subsystem ID register PCI offset 42h see Section 4 27 bits 15 0 PC Card 16 bit I F legacy mode base address register PCI offset 44h see Section 4 28 bits 31 0 System control register PCI offset 80h see Section 4 29 bits 31 24 22 13 11 6 0 MC CD debounce register PCI offset 84h see Section 4 30 bits 7 0 General control register PCI offset 86h see Section 4 31 b
229. d A_CAUDIO ia ol koo me A DVG as co acai Aa Aca an com ACFRAME ams Voca Vea co ACDEVSEL Aao ACRST ARESET co arso ams ACAD aaa on acas AJORD ACTROY aage oz acan AGE ACSTOP aao os aca av Acapie amz ca acasa a Voca cca s TAT acaos Akto s Bco Bo acads a C17 BcauDo B BvD26PKP acab ao os eos Bvst BAS Bo cts Bocanas ba sca go ox aco ano BAD 8ps oo arsw Ape e B_CCLKRUN PO ft bo oro fT A caD27 Apo ni7 Bocas Bao ACSTSCHG ABvD1 STSCHGR D18 Bco BA ACSERR AWAT m Vecs Vecs HER 1 T l A CAD26 A A0 a B 5 USB EN EN B B_USB_EN EN A CAD12 A Att A LA CCLK A A16 a ar a B_CSERR B WAI Es B CREQ B INPACK A CCLKRUN A WP IO al MS BS ISD_CMD SM WE A READY IREQ A_CC BES eres 7 gt E Zz 2 5 Table 2 1 Signal Names by GHK Terminal Number Continued acomes aag ms vec vee gt o rem am m vwo vwe n2 acaba awm an veo wo ra B CSTSCHG B BVD1STSCRGR F18 B_CAD20 B_A6 B_A7 G01 MS SDIO DATAO MS SDIO DATAO H18 B CCLK B A16 SD DATO SD DATO SM DO SM DO MS DATA MS DATA1 H19 B_CDEVSEL B A21 SD DAT1 SD DAT1 SM D1 ISM_D1 MS_DATA2 MS DATA2 Jot SD_DAT2 SD_DAT2 ISD_DAT2 SD DAT2 SM D6 ISM_D6 SM D2 SM D2 SC_GPIO4 SC GPI04 JO MS CLK MS CLK
230. d This bit is read only and returns 1 when read CSC interrupt routing control 5 csc RW 0 CSC interrupts routed to PCI if ExCA 803 bit 4 1 1 CSC interrupts routed to PCI if ExCA 805 bits 7 4 0000b default In this case the setting of ExCA 803 bit 4 is a don t care Diagnostic DISCARD_TIM_SEL_CB Set 210 reset 215 Diagnostic DISCARD_TIM_SEL_PCI Set 210 reset 215 This bit is cleared only by the assertion of GRST This bit is global and is accessed only through function 0 4 30 4 41 Capability ID Register The capability ID register identifies the linked list item as the register for PCI power management The register returns 01h when read which is the unique ID assigned by the PCI SIG for the PCI location of the capabilities pointer and the value Bit 7 6 5 4 3 2 1 0 Name Capability ID mwe rR rR R R R R R R CE a if EI es a Register Capability ID Offset AOh Type Read only Default 01h 4 42 Next Item Pointer Register The contents of this register indicate the next item in the linked list of the PCI power management capabilities Because the PCI7x21 PCI7x11 functions only include one capabilities item this register returns Os when read Bit 7 6 5 4 3 2 1 0 Name Next item pointer piper BI BSA a ae Deut o o o o o o o o Register Next item pointer Offset Ath Type Read only Default 00h 4 31 4 43 Power Management Capabilitie
231. d Standard describes the power up sequence that must be followed by the PCI7x21 PCI7x11 controller when an insertion event occurs and the host requests that the socket Vcc and Vpp be powered Upon completion of this power up sequence the PCI7x21 PCI7x11 interrupt scheme can be used to notify the host system see Table 3 11 denoted by the power cycle complete event This interrupt source is considered a PCI7x21 PCI7x11 internal event because it depends on the completion of applying power to the socket rather than on a signal change at the PC Card interface 3 7 2 Interrupt Masks and Flags Host software may individually mask or disable most of the potential interrupt sources listed in Table 3 11 by setting the appropriate bits in the PCI7x21 PCI7x11 controller By individually masking the interrupt sources listed software can control those events that cause a PCI7x21 PCI7x11 interrupt Host software has some control over the system interrupt the PCI7x21 PCI7x11 controller asserts by programming the appropriate routing registers The PCI7x21 PCI7x11 controller allows host software to route PC Card CSC and PC Card functional interrupts to separate system interrupts Interrupt routing somewhat specific to the interrupt signaling method used is discussed in more detail in the following sections When an interrupt is signaled by the PCI7x21 PCI7x11 controller the interrupt service routine must determine which of the events listed in Table
232. d by the host system to specify the latency timer for the PCI7x21 PCI7x11 CardBus interface in units of CCLK cycles When the PCI7x21 PCI7x11 controller is a CardBus initiator and asserts CFRAME the CardBus latency timer begins counting If the latency timer expires before the PCI7x21 PCI7x11 transaction has terminated then the PCI7x21 PCI7x11 controller terminates the transaction at the end of the next data phase A recommended minimum value for this register of 20h allows most transactions to be completed Bit 7 6 5 4 3 2 1 0 CardBus latency timer RW Default 0 0 0 0 0 0 0 0 Register CardBus latency timer Offset 1Bh Functions 0 1 Type Read Write Default 00h 4 19 CardBus Memory Base Registers 0 1 These registers indicate the lower address of a PCI memory address range They are used by the PCI7x21 PCI7x11 controller to determine when to forward a memory transaction to the CardBus bus and likewise when to forward a CardBus cycle to PCI Bits 31 12 of these registers are read write and allow the memory base to be located anywhere in the 32 bit PCI memory space on 4 Kbyte boundaries Bits 11 0 are read only and always return Os Writes to these bits have no effect Bits 8 and 9 of the bridge control register PCI offset 3Eh see Section 4 25 specify whether memory windows 0 and 1 are prefetchable or nonprefetchable The memory base register or the memory limit register must be nonzero in order for the PCI7x21 PCI7x1
233. d in the pwr field bits 21 23 of the self ID packet This field is reset to the state specified by the PCO PC2 input terminals upon a system hardware reset and is unaffected by a bus reset See Table 10 9 Watchdog 1 R W Watchdog enable This bit if set to 1 enables the port event interrupt Port event bit to be set whenever resume operations begin on any port This bit is cleared to 0 by system hardware reset and is unaffected by bus reset 10 2 Table 10 2 Base Register Field Descriptions Continued FIELD SIZE TYPE DESCRIPTION ISBR 1 R W Initiate short arbitrated bus reset This bit if set to 1 instructs the PHY layer to initiate a short 1 3 us arbitrated bus reset at the next opportunity This bit is cleared to 0 by a bus reset NOTE Legacy IEEE Std 1394 1995 compliant PHY layers can not be capable of performing short bus resets Therefore initiation of a short bus reset in a network that contains such a legacy device results ina long bus reset being performed Loop 1 R W Loop detect This bit is set to 1 when the arbitration controller times out during tree ID start and may indicate that the bus is configured in a loop This bit is cleared to 0 by system hardware reset or by writing a 1 to this register bit If the Loop and Watchdog bits are both set and the LLC is or becomes inactive the PHY layer activates the LLC to service the interrupt NOTE If the network is configured in a loop only those nodes which a
234. depends on the state of the PC Card interface See Table 5 3 for a complete description of the register contents Register Offset Type Default SIGNAL RSVD CARDPWR CARDWP CDETECT2 CDETECT1 BVDSTAT 5 6 ExCA interface status CardBus Socket Address 801h Card A ExCA Offset 01h Card B ExCA Offset 41h Read only 00XX XXXXb Table 5 3 ExCA Interface Status Register Description TYPE FUNCTION R This bit returns O when read A write has no effect CARDPWR Card power This bit indicates the current power status of the PC Card socket This bit reflects how the ExCA power control register has been programmed The bit is encoded as 0 Vcc and Vpp to the socket are turned off default 1 Vcc and Vpp to the socket are turned on This bit indicates the current status of the READY signal at the PC Card interface 0 PC Card is not ready for a data transfer 1 PC Card is ready for a data transfer Card write protect This bit indicates the current status of the WP signal at the PC Card interface This signal reports to the PCI7x21 PCI7x11 controller whether or not the memory card is write protected Further write protection for an entire PCI7x21 PCI7x11 16 bit memory window is available by setting the appropriate bit in the EXCA memory window offset address high byte register 0 WP signal is 0 PC Card is R W 1 WP signal is 1 PC Card is read only Card detect 2 This bit indicates the status
235. dhere to the definitions in the PCI Local Bus Specification as seen in the following bit descriptions Bits in this register may be read normally A bit in the status register is reset when a 1 is written to that bit location a O written to a bit location has no effect See Table 11 3 for a complete description of the register contents as 14 ra 2 1 9 8 Status Name Type acu cu rcu rcu rcu R a rou rR rR rR r ru R R Fo E E SOMA E AE EA ERA EE Register Status Offset 06h Type Read Clear Update Read only Default 0210h Table 11 3 Status Register Description FIELD NAME TYPE DESCRIPTION PAR_ERR MABORT RCU Detected parity error Bit 15 is set to 1 when either an address parity or data parity error is detected Signaled system error Bit 14 is set to 1 when SERR is enabled and the flash media controller has signaled a system error to the host Received master abort Bit 13 is set to 1 when a cycle initiated by the flash media controller on the PCI bus has been terminated by a master abort wo Received target abort Bit 12 is set to 1 when a cycle initiated by the flash media controller on the PCI bus was terminated by a target abort N TABORT_REC RCU Signaled target abort Bit 11 is set to 1 by the flash media controller when it terminates a transaction on the PCI bus with a target abort DEVSEL timing Bits 10 and 9 encode the timing of DEVSEL and are hardwired t
236. dicate the maximum number of bytes in a block request packet that is supported by the implementation This value max rec bytes must be 512 or greater and is calculated by 24 max rec 1 Software may change this field however this field must be valid at any time bit 17 linkEnable in the host controller control register at OHCI offset 50h 54h see Section 8 16 is set to 1 A received block write request packet with a length greater than max_rec_bytes may generate an ack_type_error This field is not affected by a software reset and defaults to value indicating 2048 bytes on a system hardware reset The default value for this field RSVD Reserved Bits 11 8 return Os when read 7 6 Generation counter This field is incremented if any portion of the configuration ROM has been incremented since the prior bus reset RSVD Reserved Bits 5 3 return Os when read 2 0 Lnk_spd Link speed This field returns 010 indicating that the link speeds of 100M bits s 200M bits s and 400M bits s are supported These bits are cleared only by the assertion of GRST 8 10 GUID High Register The GUID high register represents the upper quadlet in a 64 bit global unique ID GUID which maps to the third quadlet in the Bus Info Block This register contains node vendor ID and chip ID hi fields This register initializes to Os on a system hardware reset which is an illegal GUID value If a serial EEPROM is detected then the contents of this register
237. dicates the current status of the READY IREQ CINT signal at the PC Card interface 0 READY IREQ CINT is low 1 READY IREQ CINT is high CardBus card detected This bit indicates that a CardBus PC Card is inserted in the socket This bit is not updated until another card interrogation sequence occurs card insertion or moss n 16 bit card detected This bit indicates that a 16 bit PC Card is inserted in the socket This bit is not updated until another card interrogation sequence occurs card insertion Power cycle This bit indicates the status of each card powering request This bit is encoded as 0 Socket is powered down default 1 Socket is powered up CCD2 This bit reflects the current status of the CCD2 signal at the PC Card interface Changes to this signal during card interrogation are not reflected here 0 CCD2 is low PC Card may be present 1 CCD2 is high PC Card not present 0 CARDSTS R CCD1 This bit reflects the current status of the CCD1 signal at the PC Card interface Changes to this signal during card interrogation are not reflected here 0 CCD1 is low PC Card may be present 1 CCD1 is high PC Card not present CSTSCHG This bit reflects the current status of the CSTSCHG signal at the PC Card interface 0 CSTSCHG is low 1 CSTSCHG is high T One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled
238. dio chips may not support both modes on one terminal and may have a separate terminal for binary and PWM The PCI7x21 PCI7x11 implementation includes a signal for PWM CAUDPWM which can be routed to an MFUNC terminal Bit 2 AUD2MUX located in the card control register is programmed to route a CardBus CAUDIO PWM terminal to CAUDPWM See Section 4 36 Multifunction Routing Register for details on configuring the MFUNC terminals Figure 3 5 illustrates the SPKROUT connection System Core Logic Speaker Subsystem BINARY_SPKR SPKROUT PCI7x21 PCI7x11 CAUDPWM EWMSPRB Figure 3 5 SPKROUT Connection to Speaker Driver 3 5 9 LED Socket Activity Indicators The socket activity LEDs are provided to indicate when a PC Card is being accessed The LEDA1 and LEDA2 signals can be routed to the multifunction terminals When configured for LED outputs these terminals output an active high signal to indicate socket activity LEDA1 indicates socket A card A activity and LEDA2 indicates socket B card B activity The LED_SKT output indicates socket activity to either socket A or socket B See Section 4 36 Multifunction Routing Status Register for details on configuring the multifunction terminals The active high LED signal is driven for 64 ms When the LED is not being driven high it is driven to a low state Either of the two circuits shown in Figure 3 6 can be implemented to provide LED signaling and the board designer must
239. dor ID Reserved PCI power Reserved management capabilities pointer Reserved Maximum latency Interrupt pin Interrupt line Reserved Power management capabilities Next item pointer Capability ID PM data PMCSR_BSE Power management control and status Reserved Reserved General control Subsystem alias Class code alias Smart Card configuration 1 Smart Card configuration 2 Reserved One or more bits in this register are cleared only by the assertion of GRST 13 1 13 1 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device The vendor ID assigned to Texas Instruments is 104Ch pe eee AS AETA pA TA Vendor ID Type R R R R R R Default 1 0 1 0 4 1 Register Vendor ID Offset 00h Type Read only Default 104Ch 13 2 Device ID Register The device ID register contains a value assigned to the Smart Card controller by Texas Instruments The device identification for the Smart Card controller is 8035h js 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o0 Device ID Name q evi we R7 R7 R RIR R R R R R R R R R R R Deta 1 0 o0 o o o lof ololofi i ofi o i Register Device ID Offset 02h Type Read only Default 8035h 13 3 Command Register The command register provides control over the Smart Card controller interface to the PCI bus All bit functions adhere to the definitions in the PC Local Bus Specif
240. dows 0 4 page Offset CardBus Socket Address 840h 841h 842h 843h 844h Type Read Write Default 00h 5 24 6 CardBus Socket Registers Functions 0 and 1 The 1997 PC Card Standard requires a CardBus socket controller to provide five 32 bit registers that report and control socket specific functions The PCI7x21 PCI7x11 controller provides the CardBus socket ExCA base address register PCI offset 10h see Section 4 12 to locate these CardBus socket registers in PCI memory address space Each function has a separate base address register for accessing the CardBus socket registers see Figure 6 1 Table 6 1 gives the location of the socket registers in relation to the CardBus socket ExCA base address In addition to the five required registers the PCI7x21 PCI7x11 controller implements a register at offset 20h that provides power management control for the socket Host Host PCI7x21 PCI7x11 Configuration Registers Memory Space Memory Space Offset Offset 4 Socket A NN CardBus Socket ExCA Base Address 10h i Registers 30h Offset 00h CardBus 00h CardBus 16 Bit L Mode Base Add soon Socket B 16 Bit Legacy Mode Base Address it Legacy Mode Base ress 44h l Registers Registers CardA 20h Note The CardBus socket ExCA base address mode register is separate for functions 0 and 1 800h ExCA Registers Card B 844h Offsets are from the CardBus socket ExCA base address register s base address
241. e mwa o seo me o voo wo miramos nos sc pwn cri tos smwe ro vonis Tie runes Ro so aro Ko sekour o7 vones ve ms es scrsr Ko sop wo wen w me seves K SUSPEND eo varon Hor woa o soa o reso Pre varorr wo uson co e eo ean wis vs pa sonas co soak co ee vs vu m7 usoa Hos soak s rean we x me ms ooon co so omo re ap ve xo Ro Table 2 3 16 Bit PC Card Signal Names Sorted Alphabetically ite Vies Sowane emer ci eer sawa wane aen favo wo Ams w awa cor BCH we Past ow a ane e Mao ua aa eo ao en eo cw Mao ve avs leo Ace cw eo as aoe wie avo on IG co aoe as aos an Amo aw ao cos aoa ro as un aan en areser AA aor vn Ame roo Auseen ee eos wa Kao wo aa leo Aver ace aoe ne aos mo am mo Avs ee e ws Pano uo Ams 60 AwaT eos aoe an Caon vio Ame foo Awe eo as Aw Tao noo Aa ao amos cm ao es Tapa rs ame co e ov son Pe ao ue amo fo ea cw soa we Tas wo Aso ao ea ow aoa io Pape a07 aa coo ea ew sol 7 Tao ues Amz aw em ew som ww Mana wos Aves coe eas os no Fi Fae we ame w eas m oo us Cao roo ames c7 ewm S we o T3 a amero ene em ww
242. e Read Write Default 0000 0000h Table 11 15 Subsystem Access Register Description BIT FIELD NAME TYPE DESCRIPTION 31 16 SubsystemID RW Subsystem device ID The value written to this field is aliased to the subsystem ID register at PCI offset 2Eh Subsystem vendor ID The value written to this field is aliased to the subsystem vendor ID Subsystem VendorlD register at PCI offset 2Ch 11 14 11 23 Diagnostic Register This register programs the M and N inputs to the PLL and enables the diagnostic modes The default values for M and N in this register set the PLL output to be 80 MHz which is divided to get the 40 MHz and 20 MHz needed by the flash media cores See Table 11 16 for a complete description of the register contents All bits in this register are reset by GRST only Bit 31 30 28 27 26 25 2a 23 22 21 20 19 18 17 16 Diagnostic Diagnostic Name PO Diagnostic mwe FR R AR arpa aA Rw eR r r Rw Rw Rw Aw rw Bean o o Y o fo fo fo fo fs Po fo fo fo fo fs fol s Register Diagnostic Type Read only Read Write Offset 54h Default 0000 0105h Table 11 16 Diagnostic Register Description SIGNAL TYPE FUNCTION 31 17 TBD_CTRL R PLL control bits These bits are reserved for PLL control and test bits Diagnostic test bit This test bit shortens the PLL clock CLK VALID time and shortens the card detect DIAGNOSTIC debounce times for simulation and
243. e ID Register The device ID register contains a value assigned to the flash media controller by Texas Instruments The device identification for the flash media controller is 8033h pis 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o0 Device ID Name q ETT we 7 R R RIR R R R R R R R R R R R Deta 1 0 o0 o o o lofololofi i ofol i Register Device ID Offset 02h Type Read only Default 8033h 11 3 Command Register The command register provides control over the PCI7x21 PCI7x11 interface to the PCI bus All bit functions adhere to the definitions in the PCI Local Bus Specification as seen in the following bit descriptions See Table 11 2 for a complete description of the register contents 8 7 Name Command Type r rR Rr R rw a ew ea jaw e rw rR pw ew or petam o o of o fo fo fo fo foto fotoftotototo Register Offset Type Default FIELD NAME RSVD Command 04h Read Write Read only 0000h Table 11 2 Command Register Description TYPE DESCRIPTION Reserved Bits 15 11 return Os when read INT_DISABLE INTx disable When set to 1 this bit disables the function from asserting interrupts on the INTx signals 0 INTx assertion is enabled default 1 INTx assertion is disabled 9 EBB ENB R Fast back to back enable The flash media interface does not generate fast back to back transactions therefore bit 9 returns 0 when read 8 SERR_ENB SERR enable
244. e Specification 1 1 compliant Advanced Configuration and Power Interface ACPI Specification 2 0 compliant PCI Local Bus Specification Revision 2 3 compliant PC 98 99 and PC2001 compliant Windows Logo Program 2 0 compliant PCI Bus Interface Specification for PCI to CardBus Bridges Fully compliant with provisions of IEEE Std 1394 1995 for a high performance serial bus and IEEE Std 1394a 2000 Fully compliant with 1394 Open Host Controller Interface Specification 1 1 1 5 V core logic and 3 3 V I O cells with internal voltage regulator to generate 1 5 V core Voc Universal PCI interfaces compatible with 3 3 V and 5 V PCI signaling environments Supports PC Card or CardBus with hot insertion and removal Supports 132 MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus Supports serialized IRQ with PCI interrupts Programmable multifunction terminals Many interrupt modes supported Serial ROM interface for loading subsystem ID and subsystem vendor ID ExCA compatible registers are mapped in memory or I O space Intel 82365SL DF register compatible Supports ring indicate SUSPEND and PCI CLKRUN protocols Provides VGA palette memory and I O and subtractive decoding options LED activity terminals Fully interoperable with FireWire and i LINK implementations of IEEE Std 1394 Compliant with Intel Mobile Power Guideline 2000 Full IEEE Std 1394a 2000 support includes connection debounce arbitrated short reset
245. e eee l ol eee Configuration ROM mapping a a CT a Default CEE EE O A R E Name Configuration ROM mapping Rw ew ew R R R R R R R R R R Deian o o o o o o o o o o o o o oj ojpo Register Configuration ROM mapping Offset 34h Type Read Write Default 0000 0000h Table 8 8 Configuration ROM Mapping Register Description FIELD NAME DESCRIPTION configROMaddr If a quadlet read request to 1394 offset FFFF F000 0400h through offset FFFF F000 07FFh is received then the low order 10 bits of the offset are added to this register to determine the host memory address of the read request 90 RSVD R Reserved Bits 9 0 return Os when read 8 13 Posted Write Address Low Register The posted write address low register communicates error information if a write request is posted and an error occurs while the posted data packet is being written See Table 8 9 for a complete description of the register contents Bit 31 30 29 28 27 26 25 2a 23 22 21 20 19 18 17 16 Posted write address low Defaut x x x x x x x Xx Xx xx x Name Posted write address low pra a Le xe x x eee ex Pe ee Register Posted write address low Offset 38h Type Read Update Default XXXX XXXXh Table 8 9 Posted Write Address Low Register Description FIELDNAME TYPE DESCRIPTION The lower 32 bits of the 1394 destination offset of the
246. e register contents Bitoo 07 se 05 4 3 2 1 0o Name ExCA O window control Register ExCA I O window control Type Read Write Offset CardBus socket address 807h Card A ExCA offset 07h Card B ExCA offset 47h Default 00h Table 5 10 ExCA I O Window Control Register Description SIGNAL 1 0 window 1 wait state Bit 7 controls the I O window 1 wait state for 16 bit I O accesses Bit 7 has no effect on 8 bit accesses This wait state timing emulates the ISA wait state used by the Intel 82365SL DF This bit is encoded as 0 16 bit cycles have standard length default 1 16 bit cycles are extended by one equivalent ISA wait state WAITSTATE1 1 0 window 1 zero wait state Bit 6 controls the I O window 1 wait state for 8 bit I O accesses Bit 6 has no effect on 16 bit accesses This wait state timing emulates the ISA wait state used by the Intel 82365SL DF This bit is encoded as 0 8 bit cycles have standard length default 1 8 bit cycles are reduced to equivalent of three ISA cycles ZEROWS1 1 0 window 1 IOIS16 source Bit 5 controls the I O window 1 automatic data sizing feature that uses lOIS16 from the PC Card to determine the data width of the I O data transfer This bit is encoded as 0 Window data width determined by DATASIZE1 bit 4 default 1 Window data width determined by IOIS16 10SIS16W1 1 0 window 1 data size Bit 4 controls the I O window 1 data size Bit 4 is ignored i
247. ed bit 6 tag1SyncFilter in the isochronous receive context match register has read write access This bit is cleared when GRST is asserted o o 5 0 RSVD This bit is cleared only by the assertion of GRST Reserved Bits 5 0 return Os when read 8 32 Node Identification Register The node identification register contains the address of the node on which the OHCI Lynx chip resides and indicates the valid node number status The 16 bit combination of the busNumber field bits 15 6 and the NodeNumber field bits 5 0 is referred to as the node ID See Table 8 24 for a complete description of the register contents Bt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Node identification PN identification Type RU AU R R ea R R A R Ri AR RAR Ria RR petam o o o o o fo o lolol lo lolololololo ee ee ee a Node identification MER a x Default Register Node identification Offset E8h Type Read Write Update Read Update Read only Default 0000 FFXXh Table 8 24 Node Identification Register Description BIT FIELD NAME TYPE DESCRIPTION 31 iDValid RU 30 root RU 29 28 RSVD R 27 CPS RU 26 16 RSVD 15 6 busNumber NodeNumber Bit 31 indicates whether or not the PCI7x21 PCI7x11 controller has a valid node number It is cleared when a 1394 bus reset is detected and set to 1 when the PCI7x21 PCI7x11
248. ee eee ee E Physical request filter high sean o fo o lo o o o lololo lololo leo lolo Register Physical request filter high Offset 110h set register 114h clear register Type Read Set Clear Default 0000 0000h Table 8 29 Physical Request Filter High Register Description FIELD NAME TYPE DESCRIPTION 31 physRegAllBusses RSC If bit 31 is set to 1 all asynchronous requests received by the controller from nonlocal bus nodes are accepted Bit 31 is not cleared by a PRST 30 physReqResource62 RSC If bit 30 is set to 1 for local bus node number 62 physical requests received by the controller from that node are handled through the physical request context 29 physReqResource61 RSC If bit 29 is set to 1 for local bus node number 61 physical requests received by the controller from that node are handled through the physical request context 28 physReqResource60 RSC If bit 28 is set to 1 for local bus node number 60 physical requests received by the controller from that node are handled through the physical request context 27 physReqResource59 RSC If bit 27 is set to 1 for local bus node number 59 physical requests received by the controller from that node are handled through the physical request context 26 physReqResource58 RSC If bit 26 is set to 1 for local bus node number 58 physical requests received by the controller from that node are handled through the physical request context 25 physReqResource57 RSC If bit 25
249. eee eee eee eee 14 1 14 1 Absolute Maximum Ratings Over Operating Temperature Ranges 14 1 14 2 Recommended Operating Conditions oooooooooo 14 1 14 3 Electrical Characteristics Over Recommended Operating GONGHIONG eh KEAN KAKA TEREKE red REER EEE 14 4 144 Electrical Characteristics Over Recommended Ranges of Operating LONDMONG cronica dani ai dia 14 5 A da exh seth Nh GG BEA 14 5 14 4 2 Driver PAA PA eee tb ee es 14 5 14 4 3 A 14 5 145 PCI Clock Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free Air Temperature 14 6 14 6 Switching Characteristics for PHY Port Interface 14 6 14 7 Operating Timing and Switching Characteristics of XI 14 6 148 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free Air Temperature 14 6 15 Mechanical Information 0 20 e cece eee eee eee 15 1 xi xii List of Illustrations Figure Title 2 1 PC17621 GHK ZHK Package Terminal Diagram 2 2 PC17421 GHK ZHK Package Terminal Diagram 2 3 PC17611 GHK ZHK Package Terminal Diagram 4 2 4 PC17411 GHK ZHK Package Terminal Diagram aa 3 1 PCI7x21 PCI7x11 System Block Diagram eee eee 3 2 3 State Bidirectional Buffer 00 0 0 cece eee ee 3 3 PCI Reset Requirement anaana cece ene eee en eeee 3 4 Serial ROM Applica
250. egister Status Offset 06h Functions O 1 Type Read only Read Write Default 0210h Table 4 4 Status Register Description SIGNAL TYPE FUNCTION Detected parity error This bit is set when a parity error is detected either an address or data parity error 15 t PAR_ERR MANG Write a 1 to clear this bit 144 SYS ERR Signaled system error This bit is set when SERR is enabled and the PCI7x21 PCI7x11 controller signaled a system error to the host Write a 1 to clear this bit 134 MABORT Received master abort This bit is set when a cycle initiated by the PCI7x21 PCI7x11 controller on the PCI bus has been terminated by a master abort Write a 1 to clear this bit 124 TABT REC Received target abort This bit is set when a cycle initiated by the PCI7x21 PCI7x11 controller on the PCI Bi bus was terminated by a target abort Write a 1 to clear this bit nt TABT SIG Signaled target abort This bit is set by the PCI7x21 PCI7x11 controller when it terminates a transaction on the PCI bus with a target abort Write a 1 to clear this bit PCI SPEED DEVSEL timing These bits encode the timing of DEVSEL and are hardwired to 01b indicating that the PCI7x21 PCI7x11 controller asserts this signal at a medium speed on nonconfiguration cycle accesses Data parity error detected Write a 1 to clear this bit 0 The conditions for setting this bit have not been met 1 A data parity error occurred and the following conditions were met SG D
251. egister is alias of the class code Not like original register this register is read write and loadable from EEPROM Bit 31 30 28 28 27 26 25 2a 23 22 21 20 19 18 17 16 COTTON o o o LC CC CC Class code alias AA E Po o fo fo Jo fo fo o o o o o fo o o o CAE E Register Class code alias Offset 54h Type Read only Read Write EEPROM GRST only Default 0780 0000h 13 14 13 25 Smart Card Configuration 1 Register BIOS or EEPROM configure system dependent Smart Card interface information through this register Information of this register can be read from the Smart Card configuration 1 alias register in the Smart Card global control register set The software utilizes this information and adjusts the software and firmware behavior if necessary Corresponding bits are tied to 0 if the socket is not implemented Class A and B support are depend on the system and integrated device Supporting both classes requires method pins to control 5 0 V and 3 0 V Default value and bit types are depending on the device When this core is integrated into a device and does not have all four sockets removed sockets bits must be tied to 0 and changed to read only bits See Table 13 15 for a complete description of the register contents All bits in this register are reset by GRST only 29 28 27 26 25 2a 25 22 21 20 19 18 17 16 me O OOO O U O OO S EE a e AA lol C
252. egisters described in the PC Bus Power Management Interface Specification Revision 1 1 11 11 11 18 Power Management Control and Status Register The power management control and status register implements the control and status of the flash media controller This register is not affected by the internally generated reset caused by the transition from the D3p to DO state See Table 11 13 for a complete description of the register contents Register Power management control and status Offset 48h Type Read Clear Read Write Read only Default 0000h Table 11 13 Power Management Control and Status Register Description BIT DESCRIPTION 151 PME STAT RCU PME status This bit defaults to 0 14 13 R This field returns Os because the data register is not implemented 12 9 DATA SELECT R This field returns Os because the data register is not implemented PME EN PME enable Enables PME signaling assertion is disabled RSVD oR Reserved Bits 7 2 return Os when read Power state This 2 bit field determines the current power state and sets the flash media controller to a new power state This field is encoded as follows 1 0 PWR_STATE RW 00 Current power state is DO 01 Current power state is D1 10 Current power state is D2 11 Current power state is D3hot One or more bits in this register are cleared only by the assertion of GRST 11 19 Power Management Bridge Support Extension Regist
253. egrated as PCI functions O and 1 The configuration header compliant with the PCI Local Bus Specification as a CardBus bridge header is PC99 PC2001 compliant as well Table 4 2 illustrates the PCI configuration register map which includes both the predefined portion of the configuration space and the user definable registers Table 4 2 Functions 0 and 1 PCI Configuration Register Map Header type Latency timer Cache line size OCh CardBus socket registers ExCA base address register 10h 14h 20h 24h 28h Secondary status Reserved Capability pointer CardBus latency timer Subordinate bus number CardBus bus number PCI bus number CardBus memory base register 0 CardBus memory limit register O 20h CardBus memory base register 1 24h CardBus memory limit register 1 28h One or more bits in this register are cleared only by the assertion of GRST Table 4 2 Functions 0 and 1 PCI Configuration Register Map Continued General purpose event General purpose event General purpose output General purpose input enable status Power management control status bridge support Power management control status extensions Power management data Reserved Reserved Serial bus control status Serial bus slave address Serial bus index Serial bus data Reserved OFFSET 2Ch 30h 34h 38h 3Ch 40h 44h 48h 7Ch 80h 84h 88h 8Ch 90h 94h 9Ch A0h A4h A8h ACh Boh B4h FCh
254. emory read line and memory read multiple transactions 11 7 Header Type and BIST Register The header type and built in self test BIST register indicates the flash media controller PCI header type and no built in self test See Table 11 6 for a complete description of the register contents pas rea 13 2 wo 9 8 Header type and BIST Name we R7 R R RIR R R R R R RIR R R R R Detaut o o fo fo fo fo Popo fs toto ftotototote Register Header type and BIST Offset OEh Type Read only Default 0080h Table 11 6 Header Type and BIST Register Description FIELD NAME TYPE DESCRIPTION BIST Built in self test The flash media controller does not include a BIST therefore this field returns 00h when read PCI header type The flash media controller includes the standard PCI header Bit 7 indicates if the flash media is a multifunction device HEADER_TYPE 11 8 Flash Media Base Address Register The flash media base address register specifies the base address of the memory mapped interface registers Since the implementation of the flash media controller core in the PCI7x21 PCI7x11 controller contains 2 sockets the size of the base address register is 4096 bytes See Table 11 7 for a complete description of the register contents Flash media base address name Tee nw AW AW Rw a a aeee fete fete tetete fete Bit Name Flash media base address Type Rw
255. enes 2 28 Smart Card Terminals AAP AA 2 29 POI BUS OUDDON ca orar da ri E EE a xt 3 2 PC Card Card Detect and Voltage Sense Connections 3 7 TPS2228 Control Logic xVPP VCORE aaa 3 8 152228 Control Logic XxVCC escindida haaha DE 3 8 TPS2226 Control Logic xVPP 0 0c cece eee eee eee 3 8 TPS2226 Control Logic xV GG a ew eae is Kuh aaa 3 8 CardBus Socket Registers an 3 10 PCI7x21 PCI7x11 Registers Used to Program Serial Bus Devices 3 11 EEPROM Loading MAD sis ias lega 3 14 Interrupt Mask and Flag Registers 00 cee eee eee 3 17 PC Card Interrupt Events and Description o oooooooo o 3 18 Interrupt Pin Register Cross Reference cece eee 3 20 SMI SOMUG sia intros ri andes eee 3 20 Requirements for Internal External 1 5 V Core Power Supply 3 22 Power Management Registers ooooococococconnrr o 3 25 Function 2 Power Management Registers a 3 26 Function 3 Power Management Registers aa 3 26 xiii xiv str DO DN DD O KAOWON 7 O Loto it OB WP AA GA A l 0 Y O 0d BA ON N N N N Ci Gan i O O NG ak NI Title Page Function 4 Power Management Registers aa 3 26 Function 5 Power Management RegisterS oo oooooooo o 3 26 Bit Field Access Tag Descriptions a 4 1 Functions O and 1 PCI Configuration Register Map
256. ensedarens xe Terminal Descriptions 22 24x38 883a 888GB EERE RTP pr 2 1 Detailed Terminal Descriptions a Feature Protocol Descriptions 7 7772x4 2053088848348 pA ERA NAGA 3 1 Power Supply Sequencing 22 aaa 3 2 V Ch haracteristieS piro neu etted rinia cda bis ER 3 3 Clamping Voltages AA AA 3 4 Peripheral Component Interconnect PCI Interface 3 4 1 1394 PCI Bus Master sua daa 3 4 2 Device Resets 0 0 ccc cee eee eens 3 4 3 Serial EEPROM IC Bus 00 cece eee eee eee 3 4 4 Functions 0 and 1 CardBus Subsystem Identification 3 4 5 Function 2 OHCI 1394 Subsystem Identification 3 4 6 Function 3 Flash Media Subsystem Identification 3 4 7 Function 4 SD Host Subsystem Identification 3 4 8 Function 5 Smart Card Subsystem Identification 3 5 PC Card AppiiCdiOnS ccccesetaugeneese s0taeshey aa con pa RS 3 5 1 PC Card Insertion Removal and Recognition 3 5 2 Low Voltage CardBus Card Detection 3 5 3 UltraMedia Card Detection cece eee ee 3 5 4 Flash Media Card Detection oooocoooocooooo 3 5 5 Power Switch Interface iiccccvierntadattatadadtiiads 3 5 6 Internal Ring Oscillator 00 c eee eee eee 3 5 7 Integrated Pullup Resistors for PC Card Interface Section 3 6 3 7 3 8 3 9 Title Page 3 5 8 SPKROUT and CAUDPWM Usage 4 3 9 3 5 9 L
257. ension Register The power management bridge support extension register provides extended power management features not applicable to the Smart Card controller thus it is read only and returns 0 when read Power management bridge support extension R R Default 0 0 0 0 0 0 0 0 Register Power management bridge support extension Offset 4Ah Type Read only Default 00h 13 12 13 21 Power Management Data Register The power management bridge support extension register provides extended power management features not applicable to the Smart Card controller thus it is read only and returns 0 when read Power management data Bit 7 6 Let Name Type R R paan III Register Power management data Offset 4Bh Type Read only Default 00h 13 22 General Control Register This register controls this function Information of this register can be read from the socket configuration register in the Smart Card socket control register set See Table 13 13 for a complete description of the register contents is 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o0 General control Name we R7 R R R R R R R R RW Rw Rw R R R R Deta o o o fo fe fo fo fot oftotoftototototea Register General control Offset 4Ch Type Read Write EEPROM GRST only Default 0000h Table 13 13 General Control Register BIT FIELD NAME TYPE DESCRIPTION 15 7 RSVD oR Reserved Bits 15 7 return Os when read
258. equests received by the controller from that node are accepted 1 asynReqResource33 RSC If bit 1 is set to 1 for local bus node number 33 asynchronous requests received by the controller from that node are accepted 0 asynReqResource32 RSC If bit O is set to 1 for local bus node number 32 asynchronous requests received by the controller from that node are accepted 8 33 8 36 Asynchronous Request Filter Low Register The asynchronous request filter low set clear register enables asynchronous receive requests on a per node basis and handles the lower node IDs Other than filtering different node IDs this register behaves identically to the asynchronous request filter high register See Table 8 28 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Asynchronous request filter low Deen o o o o o po o lololol olo lololo o 14 13 12 11 Bit 15 10 9 8 7 6 5 4 3 2 1 0 Name Asynchronous request filter low Register Asynchronous request filter low Offset 108h set register 10Ch clear register Type Read Set Clear Default 0000 0000h Table 8 28 Asynchronous Request Filter Low Register Description BIT FIELD NAME TYPE DESCRIPTION 31 asynReqResource31 RSC If bit 31 is set to 1 for local bus node number 31 asynchronous requests received by the controller from that node are accepted 30 asynReqResource30 RSC _ If bit 30 is set
259. er The power management bridge support extension register provides extended power management features not applicable to the flash media controller thus it is read only and returns 0 when read Bit 7 e 5 3 2 1 Name Power management bridge support extension Type Default Register Power management bridge support extension Offset 4Ah Type Read only Default 00h 11 12 11 20 Power Management Data Register The power management bridge support extension register provides extended power management features not applicable to the flash media controller thus it is read only and returns 0 when read Power management data Name Power managementdata we R8 R R R AR aA R Register Power management data Offset 4Bh Type Read only Default 00h 11 21 General Control Register The general control register provides miscellaneous PCl related configuration See Table 11 14 for a complete description of the register contents General control CONT CO AAA ern o o lo o o o jojo Register General control Offset 4Ch Type Read Write Read only Default 00h Table 11 14 General Control Register FIELD NAME TYPE DESCRIPTION RSVD EA Reserved Bit 7 returns 0 when read 6 5 INT_SEL Interrupt select These bits are program the INTPIN register and set which interrupt output is used This field is ignored if one of the USE_INTx terminals is asserted 00 INTA 01
260. er does not respond to special cycle transactions therefore bit 3 returns O when read 2 MASTER ENB RW Bus master enable When bit 2 is set to 1 the SD host controller is enabled to initiate cycles on the PCI bus 1 MEMORY ENB RW Memory response enable Setting bit 1 to 1 enables the SD host controller to respond to memory cycles on the PCI bus 0 10_ENB R I O space enable The SD host controller does not implement any I O mapped functionality therefore bit O returns O when read 12 3 12 4 Status Register The status register provides device information to the host system All bit functions adhere to the definitions in the PCI Local Bus Specification as seen in the following bit descriptions Bits in this register may be read normally A bit in the status register is reset when a 1 is written to that bit location a 0 written to a bit location has no effect See Table 12 3 for a complete description of the register contents 15 14 ra 2 nm wo 9 8 Status Name Type acu cu rcu rcu rcu R R rou rR rR rk r ru R R Fr AA Register Status Offset 06h Type Read Clear Update Read only Default 0210h Table 12 3 Status Register Description FIELD NAME TYPE DESCRIPTION PAR_ERR MABORT Received master abort Bit 13 is set to 1 when a cycle initiated by the SD host controller on the PCI bus has been terminated by a master abort TABORT_REC RCU Received target abort Bit 12 is
261. er to attempt to become root after the next bus reset The RHB bit is cleared to 0 by a system hardware reset and is unaffected by a bus reset 1 R W Initiate bus reset This bit instructs the PHY layer to initiate a long 166 us bus reset at the next opportunity Any receive or transmit operation in progress when this bit is set completes before the bus reset is initiated The IBR bit is cleared to 0 after a system hardware reset or a bus reset Gap_Count R W Arbitration gap count This value sets the subaction fair gap arb reset gap and arb delay times The gap count can be set either by a write to the register or by reception or transmission of a PHY_CONFIG packet The gap count is reset to 3Fh by system hardware reset or after two consecutive bus resets without an intervening write to the gap count register either by a write to the PHY register or by a PHY_CONFIG packet ee na register definition For the PCI7x21 PCI7x11 controller this field is 111b indicating that the nat register set is implemented A Number of ports This field indicates the number of ports implemented in the PHY layer For the PCI7x21 PCI7x11 controller this field is 2 Max_Speed 3 PHY speed capability For the PCI7x21 PCI7x11 PHY layer this field is 010b indicating S400 speed capability Delay PHY repeater data delay This field indicates the worst case repeater data delay of the PHY layer expressed as 144 delay x 20 ns For the PCI7x21 PCI7x11 contro
262. ery terminals Connect to Connect to Ground cvse CCD1 Ground Reserved Reserved 3 5 4 Flash Media Card Detection The PCI7x21 PCI7x11 controller detects an MMC SD card insertion through the MC CD O terminal When this terminal is 0 an MMC SD card is inserted in the socket The PCI7x21 PCI7x11 controller debounces the MC CD 0 signal such that instability of the signal does not cause false card insertions The debounce time is approximately 50 ms The MC CD O signal is not debounced on card removals The filtered MC CD O signal is used in the MMC SD card detection and power control logic The MMC SD card detection and power control logic contains three main states e Socket empty power off e Card inserted power off e Card inserted power on The PCI7x21 PCI7x11 controller detects a Memory Stick card insertion through the MC_CD_1 terminal When this terminal is 0 a Memory Stick card is inserted in the socket The PCI7x21 PCI7x11 controller debounces the MC_CD_1 signal such that instability of the signal does not cause false card insertions The debounce time is approximately 50 ms The MC_CD_1 signal is not debounced on card removals The filtered MC_CD_1 signal is used in the Memory Stick card detection and power control logic The Memory Stick card detection and power control logic contains three main states e Socket empty power off e Card inserted power off e Card inserted power on 3 7 3 5 5 Power Switch Interface The powe
263. es the ring indicate function of the BVD1 RI terminals This bit is encoded as 0 Ring indicate disabled default 1 Ring indicate enabled RINGEN Card reset This bit controls the 16 bit PC Card RESET signal and allows host software to force a card reset This bit affects 16 bit cards only This bit is encoded as 0 RESET signal asserted default 1 RESET signal deasserted Card type This bit indicates the PC Card type This bit is encoded as CARDTYPE 0 Memory PC Card is installed default 1 I O PC Card is installed PCI interrupt CSC routing enable bit This bit has meaning only if the CSC interrupt routing control bit PCI offset 93h bit 5 is 0 In this case when this bit is set high the card status change interrupts are routed to PCI interrupts When low the card status change interrupts are routed using bits 7 4 in the ExCA card status change interrupt configuration register ExCA offset 805h see Section 5 6 This bit is encoded CSCROUTE as 0 CSC interrupts routed by ExCA registers default 1 CSC interrupts routed to PCI interrupts If the CSC interrupt routing control bit bit 5 of the diagnostic register PCI offset 93h see Section 4 40 is set to 1 this bit has no meaning which is the default case Card interrupt select for I O PC Card functional interrupts These bits select the interrupt routing for I O PC Card functional interrupts This field is encoded as 0000 No IRQ selected
264. escription AF Analog feedthrough TTLI1 5 V tolerant TTL input buffer TTLI2 5 V tolerant TTL input buffer with hysteresis TTLO1 5 V tolerant low noise 4 mA TTL output buffer PCII1 5 V tolerant PCI input buffer PCII2 5 V tolerant PCI input buffer PCII3 5 V tolerant PCI input buffer PCII4 5 V tolerant PCI input buffer PCII5 5 V tolerant PCI input buffer PCIO2 5 V tolerant PCI output buffer PCIO4 5 V tolerant PCI output buffer PCIO5 5 V tolerant PCI output buffer LVCI1 LVCMOS input buffer LVCO1 Low noise 4 mA LVCMOS open drain output buffer LVCO2 Low noise 4 mA LVCMOS open drain output buffer LVCO3 Low noise 8 mA LVCMOS open drain output buffer e PU PD signifies whether the terminal has an internal pullup or pulldown resistor These pullups are disabled and enabled by design when appropriate to preserve power PD1 20 yA failsafe pulldown PD2 100 uA failsafe pulldown PU1 200 yA pullup PU2 100 yA pullup PU3 100 uA pullup PU4 100 yA pullup SW Switchable 50 uA pullup 200 1A pulldown implemented depending on situation e Power Rail signifies which rail the terminal is clamped to for protection e External Components signifies any external components needed for normal operation e Pin Strapping If Unused signifies how the terminal must be implemented if its function is not needed The terminals are grouped in tables by functionality such as PCI system function power supply fun
265. ess Low Byte Registers These registers contain the low byte of the 16 bit memory window end address for memory windows 0 1 2 3 and 4 The 8 bits of these to bits A19 A12 of the end address 7 A memory EE LE 4 end address low ka ame Default Register Offset Register Offset Register Offset Register Offset Register Offset Type Default ExCA memory window 0 end address PAY CardBus Socket Address 812h Card A ExCA Offset 12h Card B ExCA Offset 52h ExCA memory window 1 end address low byte CardBus Socket Address 81Ah Card A ExCA Offset 1Ah Card B ExCA Offset 5Ah ExCA memory window 2 end address low byte CardBus Socket Address 822h Card A ExCA Offset 22h Card B ExCA Offset 62h ExCA memory window 3 end address low byte CardBus Socket Address 82Ah Card A ExCA Offset 2Ah Card B ExCA Offset 6Ah ExCA memory window 4 end address low byte CardBus Socket Address 832h Card A ExCA Offset 32h Card B ExCA Offset 72h Read Write 00h 5 16 ExCA Memory Windows 0 4 End Address High Byte Registers These registers contain the high nibble of the 16 bit memory window end address for memory windows 0 1 2 3 and 4 The lower 4 bits of these registers correspond to bits A23 A20 of the end address In addition the memory window wait states are set in this register See Table 5 12 for a complete description of the register contents Register ExCA memory window 0 e
266. et due to a missing acknowledge Bit 0 is also set on invalid EEPROM data formats See Section 3 6 4 Serial Bus EEPROM Application for details on EEPROM data format Bit 0 is cleared by a writeback of 1 0 No error detected during autoload from serial bus EEPROM 1 Data error detected during autoload from serial bus EEPROM Serial bus test When bit 2 is set the serial bus clock frequency is increased for test purposes 2t SBTEST RW 0 Serial bus clock at normal operating frequency 100 kHz default 1 Serial bus clock frequency increased for test purposes 4 37 4 38 5 ExCA Compatibility Registers Functions 0 and 1 The ExCA exchangeable card architecture registers implemented in the PCI7x21 PCI7x11 controller are register compatible with the Intel 82365SL DF PCMCIA controller EXCA registers are identified by an offset value which is compatible with the legacy I O index data scheme used on the Intel 82365 ISA controller The ExCA registers are accessed through this scheme by writing the register offset value into the index register I O base and reading or writing the data register I O base 1 The I O base address used in the index data scheme is programmed in the PC Card 16 bit I F legacy mode base address register which is shared by both card sockets The offsets from this base address run contiguously from 00h to 3Fh for socket A and from 40h to 7Fh for socket B See Figure 5 1 for an ExCA I O mapping illustration
267. et present state register offset 08h see ot ESTSMASK E Section 6 3 from causing a CSC interrupt 0 CARDSTS event does not cause a CSC interrupt default 1 CARDSTS event causes a CSC interrupt t This bit is cleared only by the assertion of GRST when PME is enabled If PME is not enabled then this bit is cleared by the assertion of PRST or GRST 6 3 6 3 Socket Present State Register This register reports information about the socket interface Writes to the socket force event register offset OCh see Section 6 4 as well as general socket interface status are reflected here Information about PC Card Vcc support and card type is only updated at each insertion Also note that the PCI7x21 PC17x11 controller uses the CCD1 and CCD2 signals during card identification and changes on these signals during this operation are not reflected in this register Register Socket present state Offset CardBus Socket Address 08h Type Read only Default 3000 00XXh Table 6 4 Socket Present State Register Description SIGNAL TYPE FUNCTION YV socket This bit indicates whether or not the socket can supply Vcc Y Y V to PC Cards The 31 YVSOCKET PCI7x21 PCI7x11 controller does not support Y Y V Vcc therefore this bit is always reset unless XVSOCKET XV socket This bit indicates whether or not the socket can supply Vcc X X V to PC Cards The PCI7x21 PCI7x11 controller does not support X X V Vcc therefore this b
268. ets as well as transitions of certain PC Card signals Table 3 10 summarizes the sources of PC Card interrupts and the type of card associated with them CSC and functional interrupt sources are dependent on the type of card inserted in the PC Card socket The four types of cards that can be inserted into any PC Card socket are 16 bit memory card 16 bit I O card CardBus cards UltraMedia card Table 3 10 Interrupt Mask and Flag Registers CA EVENT WA Y SOS 16 bit 1 O UltraMedia Mterrupt request IREQ Always enabled PCI configuration offset 91h bit O All 16 bit PC Cards Smart Card adapters UltraMedia Flash Media Change in card status CSTSCHG Socket mask bit 0 Socket event bit 0 CardBus Power cycle complete ExCA offset 05h 45h 805h bit 3 ExCA offset 04h 44h 804h bit 3 Interrupt request CINT Always enabled PCI configuration offset 91h bit O Power cycle complete Socket mask bit 3 Socket event bit 3 Card insertion or removal Socket mask bits 2 and 1 Socket event bits 2 and 1 Functional interrupt events are valid only for 16 bit I O and CardBus cards that is the functional interrupts are not valid for 16 bit memory cards Furthermore card insertion and removal type CSC interrupts are independent of the card type Table 3 11 PC Card Interrupt Events and Description CARD TYPE EVENT TYPE SIGNAL DESCRIPTION BVD1 STSCHG CSTSCHG A transition on BVD1 indicates a change in the Battery condi
269. evita 7 10 7 16 Minimum Grant and Maximum Latency Register 7 11 7 47 ONG Conrol Register socorrer NLA BKA inte abode Bee 7 11 7 18 Capability ID and Next Item Pointer Registers 7 12 7 19 Power Management Capabilities Register 7 13 7 20 Power Management Control and Status Register 7 14 7 21 Power Management Extension Registers 7 14 7 22 PCI PHY Control Register maawa kaha Pana vas KAPAG 7 15 7 23 PCI Miscellaneous Configuration Register 7 16 7 24 Link Enhancement Control Register aa 7 17 7 25 Subsystem Access Register a 7 18 7 26 GPIO Control Register 0 c eee ees 7 19 8 OHCURGGISICNS essere ANGAS 8 1 8 1 OHCI Version Register 0000 cece eee eee ees 8 4 8 2 GUID ROM Register cosmos suas rei 8 5 8 3 Asynchronous Transmit Retries Register 8 6 8 4 Cor Data Fegisier Dana NA aan AA AA Ph kA 8 6 8 5 CSR Compare Register cece eee ees 8 7 8 6 CSR Control Register pasa paka haaa bA AUG xsi 8 7 8 7 Configuration ROM Header Register aa 8 8 8 8 Bus Identification Register cocidas 8 8 8 9 Bus Options Register aanu e nrnna 8 9 8 10 GUID High Register crop ario 8 10 8 11 GUID Low Register 2 03nn npka kaa LAAN hAP ING BAGA KGG NEA 8 10 8 12 Configuration ROM Mapping Register aa 8 11 8 13
270. ext Item Pointer Registers Description 7 12 7 16 Power Management Capabilities Register Description 7 13 7 17 Power Management Control and Status Register Description 7 14 7 18 Power Management Extension Registers Description 7 14 7 19 PCI PHY Control Register Description oooooocooomomo 7 15 7 20 PCI Miscellaneous Configuration Register Description 7 16 7 21 Link Enhancement Control Register Description 7 17 7 22 Subsystem Access Register Description 0ooooooooomo 7 18 8 1 OHCI Register Map 2 eens 8 1 8 2 OHCI Version Register Description aa 8 4 8 3 GUID ROM Register Description a 8 5 8 4 Asynchronous Transmit Retries Register Description 8 6 8 5 CSR Control Register Description 60 a 8 7 8 6 Configuration ROM Header Register Description 8 8 8 7 Bus Options Register Description 7747k ahahahha KAM hh 8 9 8 8 Configuration ROM Mapping Register Description 8 11 8 9 Posted Write Address Low Register Description 8 11 8 10 Posted Write Address High Register Description 8 12 Title Page Host Controller Control Register Description 8 13 Self ID Count Register Description o0oooooooorommmmoo 8 15 Isochronous Receive Channel Mask High Register Descr
271. f bit 5 IOSIS16W1 is set This bit is encoded as IZE1 RW DATAS 0 Window data width is 8 bits default W 1 Window data width is 16 bits 1 0 window 0 wait state Bit 3 controls the I O window 0 wait state for 16 bit I O accesses Bit 3 has no effect on 8 bit accesses This wait state timing emulates the ISA wait state used by the Intel 82365SL DF This bit is encoded as 0 16 bit cycles have standard length default 1 16 bit cycles are extended by one equivalent ISA wait state WAITSTATEO 1 0 window 0 zero wait state Bit 2 controls the I O window 0 wait state for 8 bit I O accesses Bit 2 has no effect on 16 bit accesses This wait state timing emulates the ISA wait state used by the Intel 82365SL DF This bit is encoded as 0 8 bit cycles have standard length default 1 8 bit cycles are reduced to equivalent of three ISA cycles ZEROWSO 1 0 window 0 IOIS16 source Bit 1 controls the I O window 0 automatic data sizing feature that uses OIS16 from the PC Card to determine the data width of the I O data transfer This bit is encoded as 0 Window data width is determined by DATASIZEO bit 0 default 1 Window data width is determined by IOIS16 IOSIS16WO 0 Window data width is 8 bits default 1 Window data width is 16 bits 1 0 window 0 data size Bit 0 controls the I O window 0 data size Bit 0 is ignored if bit 1 IOSIS16WO0 is DATASIZEO R set This bit is encoded as 5 9 ExCA I O Windo
272. f description for each register is followed by the register offset and a bit table describing the reset state for each register A bit description table typically included when the register contains bits of more than one type or purpose indicates bit field names a detailed field description and field access tags which appear in the type column Table 4 1 describes the field access tags The PCI7x21 PCI7x11 controller is a multifunction PCI device The 1394 OHCI is integrated as PCI function 2 The function 2 configuration header is compliant with the PCI Local Bus Specification as a standard header Table 7 1 illustrates the configuration header that includes both the predefined portion of the configuration space and the user definable registers Table 7 1 Function 2 Configuration Register Map Headerype Latency imer Oachelnesize ocn OHCI base address TI extension base address CardBus CIS base address Reserved 0 CardBus CIS pointer 2 Subsystem ID Subsystem vendor ID Reserved PCI power Reserved management capabilities pointer PCI OHCI control 40h Power management capabilities Next item pointer CapabilityID 44h CU POlmiscolaneous configurations Fo e Fa atm ene E One or more bits in this register are cleared only by the assertion of GRST 00h 04h 08h Ch 28h Ch 30h 34h Reserved 38h Ch 40h 44h 48h Ch FOh F4h F8h Ch 7 1 7 1 Vendor ID Register The vendor I
273. filtered according to bit 28 tag0 bit 30 tag2 and bit 31 tag3 without any additional restrictions If this bit is cleared then this context matches on isochronous receive packets as specified in bits 28 31 tag0 tag3 with no additional restrictions 5 0 channelNumber RW This 6 bit field indicates the isochronous channel number for which this isochronous receive DMA context accepts packets 8 44 9 TI Extension Registers The TI extension base address register provides a method of accessing memory mapped TI extension registers See Section 7 9 TI Extension Base Address Register for register bit field details See Table 9 1 for the TI extension register listing Table 9 1 TI Extension Register Map 9 1 DV and MPEG2 Timestamp Enhancements The DV timestamp enhancements are enabled by bit 8 enab_dv_ts in the link enhancement control register located at PCI offset F4h and are aliased in TI extension register space at offset A88h set and A8Ch clear The DV and MPEG transmit enhancements are enabled separately by bits in the link enhancement control register located in PCI configuration space at PCI offset F4h The link enhancement control register is also aliased as a set clear register in TI extension space at offset A88h set and A8Ch clear Bit 8 enab_dv_ts of the link enhancement control register enables DV timestamp support When enabled the link calculates a timestamp based on the cycle timer and the timesta
274. fo foto fo fo fo fo Bit ts 14 13 12 11 10 9 8 7 6 5 4a 3 2 1 o Pia ae bound Register Physical upper bound Offset 120h Type Read only Default 0000 0000h 8 37 8 40 Asynchronous Context Control Register The asynchronous context control set clear register controls the state and indicates status of the DMA context See Table 8 31 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Asynchronous context control Type R R R Default 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o hoe esco A R ASU AUT AU R a Rol eo Ru AU AU AU AU AU oem o o lo Xx o o o o x x x x x x x x1 Register Asynchronous context control Offset 180h set register ATRQ 184h clear register ATRQ 1A0h set register ATRS 1A4h clear register ATRS 1C0h set register ARRQ 1C4h clear register ARRQ 1E0h set register ARRS 1E4h clear register ARRS Type Read Set Clear Update Read Set Update Read Update Read only Default 0000 XOXXh Table 8 31 Asynchronous Context Control Register Description FIELD NAME TYPE DESCRIPTION 31 16 RSVD Reserved Bits 31 16 return Os when read al Software sets bit 12 to 1 to cause the PCI7x21 PCI7x11 controller to continue or resume descriptor processing The PCI7x21 PCI7x11 controller clears this bit on every descriptor fetch The PC
275. for a complete description of the register contents as 14 13 12 11 roo 7 foe 5s 4 3 2 Secondary status Name Secondarystatus IO Type Rc Rc rc rc ec re re ec re rei ri ri e rte e Defaut o o o o fo o fs o fo foto o ojo o fo Register Secondary status Offset 16h Type Read only Read Clear Default 0200h Table 4 5 Secondary Status Register Description SIGNAL TYPE FUNCTION Detected parity error This bit is set when a CardBus parity error is detected either an address or data CBPARITY a nee parity error Write a 1 to clear this bit Signaled system error This bit is set when CSERR is signaled by a CardBus card The PCI7x21 PCI7x11 controller does not assert the CSERR signal Write a 1 to clear this bit CBSERR RC RC CBMABORT RC Received master abort This bit is set when a cycle initiated by the PCI7x21 PCI7x11 controller on the CardBus bus is terminated by a master abort Write a 1 to clear this bit RC RC C m CardBus bus is terminated by a target abort Write a 1 to clear this bit Signaled target abort This bit is set by the PCI7x21 PCI7x11 controller when it terminates a transaction Iba aIGcRBin on the CardBus bus with a target abort Write a 1 to clear this bit CardBus data parity error detected Write a 1 to clear this bit 0 The conditions for setting this bit have not been met 1 A data parity error occurred and the followi
276. ftware enables an isochronous receive context by setting bit 15 run in the isochronous receive context control register see Section 8 44 to 1 The n value in the following register addresses indicates the context number n 0 1 2 3 Isochronous receive context command pointer Name Type R R RIR R RIR R R IR R R R R R R petan Xx x x x x x x x x x x x x x x x4 a ee a a a a de Isochronous receive context command rame Default Register Isochronous receive context command pointer Offset 40Ch 32 n Type Read only Default XXXX XXXXh 8 46 Isochronous Receive Context Match Register The isochronous receive context match register starts an isochronous receive context running on a specified cycle number filters incoming isochronous packets based on tag values and waits for packets with a specified sync value The n value in the following register addresses indicates the context number n O 1 2 3 See Table 8 35 for a complete description of the register contents Bt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Isochronous receive context match a an pen x x x x o o o x lo ee ee ee a Isochronous receive context match were RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default Register Isochronous receive context match Offset 410Ch 32 n Type Read Write Read only Default XXXX XXXXh Table 8 35 Is
277. ge These bits select the interrupt routing for card status change interrupts This field is encoded as 0000 CSC interrupts routed to PCI interrupts if bit 5 of the diagnostic register PCI offset 93h is set to 1b In this case bit 4 of ExCA 803 is a don t care This is the default setting 0000 No ISA interrupt routing if bit 5 of the diagnostic register PCI offset 93h is set to Ob In this case CSC interrupts are routed to PCI interrupts by setting bit 4 of ExCA 803h to 1b 0001 IRQ1 enabled 0010 SMI enabled 0011 IRQ3 enabled 0100 IRQ4 enabled CSCSELECT 0101 IRQ5 enabled 0110 IRQ6 enabled 0111 IRQ7 enabled 1000 IRQ8 enabled 1001 IRQ9 enabled 1010 IRQ10 enabled 1011 IRQ11 enabled 1100 IRQ12 enabled 1101 IRQ13 enabled 1110 IRQ14 enabled 1111 IRQ15 enabled Card detect enable Enables interrupts on CD1 or CD2 changes This bit is encoded as 0 Disables interrupts on CD1 or CD2 line changes default 1 Enables interrupts on CD1 or CD2 line changes Ready enable This bit enables disables a low to high transition on the PC Card READY signal to generate READYEN a host interrupt This interrupt source is considered a card status change This bit is encoded as 0 Disables host interrupt generation default 1 Enables host interrupt generation Battery warning enable This bit enables disables a battery warning condition to generate a CSC interrupt BATWARNEN EW This bit is en
278. gement Data Register The power management data register returns Os when read because the CardBus functions do not report dynamic data Name Power management data mwe R R R R R R R R pean o 00 o0 o oo oo o0 o Register Power management data Offset A7h functions 0 1 Type Read only Default 00h 4 34 4 47 Serial Bus Data Register The serial bus data register is for programmable serial bus byte reads and writes This register represents the data when generating cycles on the serial bus interface To write a byte this register must be programmed with the data the serial bus index register must be programmed with the byte address the serial bus slave address must be programmed with the 7 bit slave address and the read write indicator bit must be reset On byte reads the byte address is programmed into the serial bus index register the serial bus slave address register must be programmed with both the 7 bit slave address and the read write indicator bit and bit 5 REQBUSY in the serial bus control and status register see Section 4 50 must be polled until clear Then the contents of this register are valid read data from the serial bus interface See Table 4 22 for a complete description of the register contents ee 7 5 4 5 2 7 0 a SSS Register Serial bus data Offset BOh function 0 Type Read Write Default 00h Table 4 22 Serial Bus Data
279. gister Type Read Set Clear Update Read Set Clear Read Update Read only Default XXXX OXXXh Table 8 16 Interrupt Mask Register Description BIT FIELD NAME TYPE DESCRIPTION masterIntEnable RSCU Master interrupt enable If bit 31 is set to 1 then external interrupts are generated in accordance with the interrupt mask register If this bit is cleared then external interrupts are not generated regardless of the interrupt mask register settings VendorSpecific RSC When this bit and bit 30 vendorSpecific in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this vendor specific interrupt mask enables interrupt generation wo a SoftInterrupt RSC When this bit and bit 29 SoftInterrupt in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this soft interrupt mask enables interrupt generation RSVD Reserved Bit 28 returns O when read ack tardy RSC When this bit and bit 27 ack tardy in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this acknowledge tardy interrupt mask enables interrupt generation phyRegRcvd RSC When this bit and bit 26 phyRegRcvd in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this PHY register interrupt mask enables interrupt generation cycleTooLong RSC When this bit and bit 25 cycleTooLong in the interrupt event register at OHCI offset 80h 84h see Sect
280. gister Vendor ID Offset 40h Type Read only Default 0108 0028h 8 16 Host Controller Control Register The host controller control set clear register pair provides flags for controlling the PCI7x21 PCI7x11 controller See Table 8 11 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Host controller control Bit 15 14 13 12 11 10 9 8 7 56 Name Type RSU RSC RSC R R R RSC R R RSC RSC RSC RSCU Default 0 X 0 0 0 1 0 0 0 0 X 0 0 Host controller control Type R R R R Default 0 0 0 0 Register Host controller control Offset 50h set register 54h clear register Type Read Set Clear Update Read Set Clear Read Clear Read only Default X08X 0000h Table 8 11 Host Controller Control Register Description FIELD NAME TYPE DESCRIPTION BIBimage Valid When bit 31 is set to 1 the PCI7x21 PCI7x11 physical response unit is enabled to respond to block read requests to host configuration ROM and to the mechanism for atomically updating configuration ROM Software creates a valid image of the bus info block in host configuration ROM before setting this bit When this bit is cleared the PCI7x21 PCI7x11 controller returns ack type error on block read requests to host configuration ROM Also when this bit is cleared and a 1394 bus reset occurs the configuration ROM mapping register at OHCI offset 34h
281. gister Description continued SIGNAL TYPE CB_DPAR RSVD R EXCAPOWER KEEPCLK RIMUX FUNCTION CardBus data parity SERR signaling enable 0 CardBus data parity not signaled on PCI SERR signal default 1 CardBus data parity signaled on PCI SERR signal Reserved This bit returns 0 when read ExCA power control bit 0 Enables 3 3 V default 1 Enables 5V Keep clock When this bit is set the PCI7x21 PCI7x11 controller follows the CLKRUN protocol to maintain the system PCLK and the CCLK CardBus clock This bit is global to the PCI7x21 PCI7x11 functions 0 Allow system PCLK and CCLK clocks to stop default 1 Never allow system PCLK or CCLK clock to stop Note that the functionality of this bit has changed relative to that of the PCI12XX family of TI CardBus controllers In these CardBus controllers setting this bit only maintains the PCI clock not the CCLK In the PCI7x21 PCI7x11 controller setting this bit maintains both the PCI clock and the CCLK PME RI OUT select bit When this bit is 1 the PME signal is routed to the PME RI_OUT terminal R03 When this bit is O and bit 7 RIENB of the card control register is 1 the RI OUT signal is routed to the PME RI_OUT terminal If this bit is O and bit 7 RIENB of the card control register is O then the output is placed in a high impedance state This terminal is encoded as 0 RI_OUT signal is routed to the PME RI OUT terminal if bit 7 of the card control reg
282. gister size This field returns Os when read indicating that the OHCI registers require a E 2K byte region of memory OHCI register prefetch Bit 3 returns O when read indicating that the OHCI registers are 3 OHCI PF nonprefetchable OHCI memory type This field returns Os when read indicating that the OHCI base address register OHCIUMEMTYRE EN is 32 bits wide and mapping can be done anywhere in the 32 bit memory space OHCI MEM OHCI memory indicator Bit O returns 0 when read indicating that the OHCI registers are mapped into system memory space 7 6 7 9 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory mapped TI extension registers When BIOS writes all 1s to this register the value read back is FFFF COOOh indicating that at least 16K bytes of memory address space are required for the TI registers See Table 7 8 for a complete description of the register contents Name CTlextension base address Rw Rw Den o o o o o fofofofofofofofofofo o 7 Name TI extension base address Type RW RW R R Default 0 0 0 0 Register Tl extension base address Offset 14h Type Read Write Read only Default 0000 0000h Table 7 8 Tl Base Address Register Description FIELD NAME TYPE DESCRIPTION TI register pointer This field specifies the upper 18 bits of the 32 bit TI base address register The di TIREG PTR KEI default value
283. gisters to determine when to forward PCI configuration cycles to its secondary buses LT AC DEE Ch UE oe YU Tare pbb Register PCI bus number Offset 18h Functions 0 1 Type Read Write Default 00h 4 16 CardBus Bus Number Register The CardBus bus number register is programmed by the host system to indicate the bus number of the CardBus bus to which the PCI7x21 PCI7x11 controller is connected The PCI7x21 PCI7x11 controller uses this register in conjunction with the PCI bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to its secondary buses This register is separate for each PCI7x21 PCI7x11 controller function Register CardBus bus number Offset 19h Type Read Write Default 00h 4 17 Subordinate Bus Number Register The subordinate bus number register is programmed by the host system to indicate the highest numbered bus below the CardBus bus The PCI7x21 PCI7x11 controller uses this register in conjunction with the PCI bus number and CardBus bus number registers to determine when to forward PCI configuration cycles to its secondary buses This register is separate for each CardBus controller function Name Subordinate bus number a a a 0 A E Gm PF EL Default 0 0 0 0 0 0 0 Register Subordinate bus number Offset 1Ah Type Read Write Default 00h 4 10 4 18 CardBus Latency Timer Register The CardBus latency timer register is programme
284. hat a requested serial bus access byte read or write is in progress A request is made and bit 5 is set by writing to the serial bus slave address register see Section 4 49 Bit 5 must be polled on reads from the serial interface After the byte read access has been completed this bit is cleared and the read data is valid in the serial bus data register Serial EEPROM busy status Bit 4 indicates the status of the PCI7x21 PCI7x11 serial EEPROM circuitry Bit 4 is set during the loading of the subsystem ID and other default values from the serial bus EEPROM 0 Serial EEPROM circuitry is not busy 1 Serial EEPROM circuitry is busy REQBUSY ROMBUSY SBDETECT Serial bus detect When the serial bus interface is detected through a pullup resistor on the SCL terminal after reset this bit is set to 1 0 Serial bus interface not detected 1 Serial bus interface detected Requested serial bus access error Bit 1 indicates when a data error occurs on the serial interface during a requested cycle and may be set due to a missing acknowledge Bit 1 is cleared by a writeback of 1 0 No error detected during user requested byte read or write cycle 1 Data error detected during user requested byte read or write cycle REQ_ERR ROM_ERR This bit is cleared only by the assertion of GRST EEPROM data error status Bit 0 indicates when a data error occurs on the serial interface during the auto load from the serial bus EEPROM and may be s
285. he PCI7x21 PCI7x11 ability to generate PCI bus accesses default 1 Enables the PCI7x21 PCI7x11 ability to generate PCI bus accesses MAST_EN RW 4 Table 4 3 Command Register Description continued SIGNAL TYPE FUNCTION Memory space enable This bit controls whether or not the PCI7x21 PCI7x11 controller can claim cycles in PCI memory space MENGEN Ra 0 Disables the PCI7x21 PCI7x11 response to memory space accesses default 1 Enables the PCI7x21 PCI7x11 response to memory space accesses 1 0 space control This bit controls whether or not the PCI7x21 PCI7x11 controller can claim cycles in PCI IO EN RW I O space 0 Disables the PCI7x21 PCI7x11 controller from responding to I O space accesses default 1 Enables the PCI7x21 PCI7x11 controller to respond to I O space accesses 4 5 Status Register The status register provides device information to the host system Bits in this register can be read normally A bit in the status register is reset when a 1 is written to that bit location a O written to a bit location has no effect All bit functions adhere to the definitions in the PCI Bus Specification as seen in the bit descriptions PCI bus status is shown through each function See Table 4 4 for a complete description of the register contents Las 18 19 32 30 o 6 7 6 5 4 9 2 1 o Name taas ripe aw aw aw aw aw a Da a ALAALA Dea o o o o o o 1 o o o o r ololo o R
286. he clear register always return the contents of the isochronous transmit interrupt mask register In all cases the enables for each interrupt event align with the isochronous transmit interrupt event register bits detailed in Table 8 17 Isochronous transmit interrupt mask Name _ _ o A Po fo fo fofofofofofoefofofofofofofo papa 999009999 Isochronous transmit interrupt mask Mame RSC RSC RSC RSC RSC RSC RSC RSC Default Register Isochronous transmit interrupt mask Offset 98h set register 9Ch clear register Type Read Set Clear Read only Default 0000 00XXh 8 25 Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set clear register reflects the interrupt state of the isochronous receive contexts An interrupt is generated on behalf of an isochronous receive context if an INPUT_ command completes and its interrupt bits are set to 1 Upon determining that the isochRx bit 7 interrupt in the interrupt event register at OHCI offset 80h 84h see Section 8 21 has occurred software can check this register to determine which context s caused the interrupt The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register See Table 8 18 for a complete description of the reg
287. he cycle timer rolls over based on the setting of bit 22 cycleSource When bit 21 is cleared the OHCI Lynx accepts received cycle start packets to maintain synchronization with the node which is sending them Bit 21 is automatically cleared when bit 25 cycleTooLong in the interrupt event register at OHCI offset 80h 84h see Section 8 21 is set to 1 Bit 21 cannot be set to 1 until bit 25 cycleTooLong is cleared CycleTimerEnable When bit 20 is set to 1 the cycle timer offset counts cycles of the 24 576 MHz clock and rolls over at the appropriate time based on the settings of the above bits When this bit is cleared the cycle timer offset does not count Reserved Bits 19 11 return Os when read 19 11 RSVD RevPhyPkt au Mm O When bit 10 is set to 1 the receiver accepts incoming PHY packets into the AR request context if the AR request context is enabled This bit does not control receipt of self identification packets RevSelflD RSVD tag1SyncFilterLock When bit 9 is set to 1 the receiver accepts incoming self identification packets Before setting this bit to 1 software must ensure that the self ID buffer pointer register contains a valid address po Mm gt E Reserved Bits 8 and 7 return Os when read pu n When bit 6 is set to 1 bit 6 tag1SyncFilter in the isochronous receive context match register see Section 8 46 is set to 1 for all isochronous receive contexts When bit 6 is clear
288. his address The serial EEPROM chip in the sample application Figure 3 11 assumes the 1010b high address nibble The lower three address bits are terminal inputs to the chip and the sample application shows these terminal inputs tied to GND 3 13 Table 3 9 EEPROM Loading Map SERIAL ROM OFFSET BYTE DESCRIPTION 00h CardBus function indicator 00h 01h Number of bytes 20h PCI 04h command register function 0 bits 8 6 5 2 0 02h 7 6 5 2 1 0 Command Command Command Command Command Command register bit 8 register bit 6 register bit 5 register bit 2 register bit 1 register bit 0 PCI 04h command register function 1 bits 8 6 5 2 0 7 6 5 2 1 0 Command Command Command Command Command Command register bit 8 register bit 6 register bit 5 register bit 2 register bit 1 register bit 0 04h PCI 40h subsystem vendor ID byte 0 05h PCI 41h subsystem vendor ID byte 1 06h PCI 42h subsystem ID byte 0 07h PCI 43h subsystem ID byte 1 08h PCI 44h PC Card 16 bit I F legacy mode base address register byte O bits 7 1 09h PCI 45h PC Card 16 bit I F legacy mode base address register byte 1 h PCI 46h PC Card 16 bit I F legacy mode base address register byte 2 Bh PCI 47h PC Card 16 bit I F legacy mode base address register byte 3 OCh PCI 80h system control function 0 byte 0 bits 6 0 ODh PCI 80h system control function 1 byte 0 bit 2 OEh PCI 81h system control byte 1 bits 7 6 o
289. hronous receive request DMA interrupt Bit 2 is conditionally set to 1 upon completion of an ARRQ DMA context command descriptor respTxComplete RSCU Asynchronous response transmit DMA interrupt Bit 1 is conditionally set to 1 upon completion of an ATRS DMA command 0 reqTxComplete RSCU Asynchronous request transmit DMA interrupt Bit O is conditionally set to 1 upon completion of an ATRQ DMA command 8 22 Interrupt Mask Register The interrupt mask set clear register enables the various PCI7x21 PCI7x11 interrupt sources Reads from either the set register or the clear register always return the contents of the interrupt mask register In all cases except masterlntEnable bit 31 and vendorSpecific bit 30 the enables for each interrupt event align with the interrupt event register bits detailed in Table 8 15 This register is fully compliant with the 1394 Open Host Controller Interface Specification and the PCI7x21 PCI7x11 controller adds an interrupt function to bit 30 See Table 8 16 for a complete description of bits 31 and 30 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Interrupt mask Default x x o lol lo x x x x x x x x o0o x xs Bit 15 14 13 12 11 10 9 8 7 6 5 4a 3 2 1 o Name Interrupt mask im Re A a A A A rse ASC asc ASC ASC ASC ASC ASC ASC aso Register Interrupt mask Offset 88h set register 8Ch clear re
290. icating that the PCI clock is not required for the SD host controller to generate PME 2 0 PM_VERSION Power management version This field returns 010b when read indicating that the SD host controller is compatible with the registers described in the PCI Bus Power Management Interface Specification Revision 1 1 12 12 12 19 Power Management Control and Status Register The power management control and status register implements the control and status of the SD host controller This register is not affected by the internally generated reset caused by the transition from the D3p to DO state See Table 12 14 for a complete description of the register contents 9 8 7 6 5 Name Power management control and status Type rou R RRA RI reo ealedle lel rr ew ew petam o o o fo fo of of o foto fotoftotototo Register Power management control and status Offset 84h Type Read Clear Read Write Read only Default 0000h Table 12 14 Power Management Control and Status Register Description FIELD NAME TYPE DESCRIPTION PME_STAT PME status This bit defaults to 0 DATA_SCALE Data scale This field returns Os when read because the SD host controller does not use the data register DATA_SELECT Data select This field returns Os when read because the SD host controller does not use the data register PME_EN PME enable Enables PME signaling Reserved Bits 7 2 return Os when read 1 0 PWR_STATE
291. ication as seen in the following bit descriptions The SERR_EN and PERR_EN enable bits in this register are internally wired OR between other functions and these control bits appear separately according to their software function See Table 13 2 for a complete description of the register contents is 4 13 2 11 10 9 8 7 6 5 4 3 2 1 o Command EA mwe R AR AR RAR ra few ra frew a A rR R Aw e petam o o o fo fo o fo fo fo fo fo ftofototolto Register Command Offset 04h Type Read Write Read only Default 0000h Table 13 2 Command Register Description BIT FIELD NAME TYPE DESCRIPTION 15 11 RSVD R Reserved Bits 15 11 return Os when read 1 INT DIS RW INTx disable When set to 1 this bit disables the function from asserting interrupts on the INTx signals 0 INTx assertion is enabled default 1 INTx assertion is disabled 0 9 R Fast back to back enable The Smart Card interface does not generate fast back to back transactions therefore bit 9 returns 0 when read System error SERR enable Bit 8 controls the enable for the SERR driver on the PCI interface SERR can be asserted after detecting an address parity error on the PCI bus Both bits 8 and 6 PERR_EN must be set for this function to report address parity errors 0 Disable SERR output driver default 1 Enable SERR output driver RSVD Reserved Bit 7 returns 0 when read PERR_EN Parity error response enable Bit 6 controls this
292. idle states Typically the PCI7x21 PCI7x11 controller masters byte reads and byte writes under software control Doubleword reads are performed by the serial EEPROM initialization circuitry upon a PCI reset and may not be generated under software control See Section 3 6 4 Serial Bus EEPROM Application for details on how the PCI7x21 PCI7x11 controller automatically loads the subsystem identification and other register defaults through a serial ous EEPROM Figure 3 9 illustrates a byte write The PCI7x21 PCI7x11 controller issues a start condition and sends the 7 bit slave device address and the command bit zero A 0 in the R W command bit indicates that the data transfer is a write The slave device acknowledges if it recognizes the address If no acknowledgment is received by the PCI7x21 PCI7x11 controller then an appropriate status bit is set in the serial bus control status register PCI offset B3h see Section 4 50 The word address byte is then sent by the PCI7x21 PC17x11 controller and another slave acknowledgment is expected Then the PCI7x21 PCI7x11 controller delivers the data byte MSB first and expects a final acknowledgment before issuing the stop condition Slave Address Word Address Data Byte PRE RA A Slave Acknowledgement S P Start Stop Condition Figure 3 9 Serial Bus Protocol Byte Write Figure 3 10 illustrates a byte read The read protocol is very similar to the write protocol except the R W command bit must be se
293. ignaled target abort Bit 11 is set to 1 by the PCI7x21 PCI7x11 controller when it terminates a transaction on the PCI bus with a target abort DEVSEL timing Bits 10 and 9 encode the timing of DEVSEL and are hardwired to 01b indicating that the PCI7x21 PCI7x11 controller asserts this signal at a medium speed on nonconfiguration cycle accesses DATAPAR Data parity error detected Bit 8 is set to 1 when the following conditions have been met a PERR was asserted by any PCI device including the PCI7x21 PCI7x11 controller b The PCI7x21 PCI7x11 controller was the bus master during the data parity error c Bit 6 PERR_EN in the command register at offset 04h in the PCI configuration space see Section 7 3 is set to 1 Fast back to back capable The PCI7x21 PCI7x11 controller cannot accept fast back to back transactions therefore bit 7 is hardwired to 0 User definable features UDF supported The PCI7x21 PCI7x11 controller does not support the UDF therefore bit 6 is hardwired to 0 66 MHz capable The PCI7x21 PCI7x11 controller operates at a maximum PCLK frequency of 33 MHz therefore bit 5 is hardwired to 0 Capabilities list Bit 4 returns 1 when read indicating that capabilities additional to standard PCI are implemented The linked list of PCI power management capabilities is implemented in this function Interrupt status This bit reflects the interrupt status of the function Only when bit 10 INT_DISABLE Po l ev
294. igure 3 15 RI OUT Functional Diagram RI from the 16 bit PC Card interface is masked by bit 7 RINGEN in the ExCA interrupt and general control register ExCA offset 03h 43h 803h see Section 5 4 This is programmed on a per socket basis and is only applicable when a 16 bit card is powered in the socket The CBWAKE signaling to RI OUT is enabled through the same mask as the CSC event for CSTSCHG The mask bit bit 0 CSTSMASK is programmed through the socket mask register CB offset 04h see Section 6 2 in the CardBus socket registers RI OUT can be routed through any of three different pins RI OUT PME MFUNC2 or MFUNC4 The RI OUT function is enabled by setting bit 7 RIENB in the card control register PCI offset 91h see Section 4 38 The PME function is enabled by setting bit 8 PME ENABLE in the power management control status register PCI offset A4h see Section 4 44 When bit 0 RIMUX in the system control register PCI offset 80h see Section 4 29 is set to 0 both the RI OUT function and the PME function are routed to the RI OUT PME terminal If both functions are enabled and RIMUX is set to O then the RI OUT PME terminal becomes RI_OUT only and PME assertions are never seen Therefore in a system using both the RI_OUT function and the PME function RIMUX must be set to 1 and RI OUT must be routed to either MFUNC2 or MFUNC4 3 24 3 8 9 PCI Power Management 3 8 9 1 CardBus Power Management Functions 0 and 1
295. ility ID and Next Item Pointer Registers Description FIELD NAME DESCRIPTION NEXT_ITEM Next item pointer The Smart Card controller supports only one additional capability PCI power management that is communicated to the system through the extended capabilities list therefore this field returns 00h when read 7 0 CAPABILITY_ID Capability identification This field returns 01h when read which is the unique ID assigned by the PCI SIG for PCI power management capability 13 10 13 18 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the Smart Card controller related to PCI power management See Table 13 11 for a complete description of the register contents CS ae a eee Se ee AA Power management capabilities Type RU R R R R R R R R Default 0 1 1 1 1 1 1 0 0 Register Power management capabilities Offset 46h Type Read Update Read only Default 7E02h Table 13 11 Power Management Capabilities Register Description FIELD NAME TYPE DESCRIPTION PME D3COLD PME support from D3cold This bit can be set to 1 or cleared to 0 via bit 4 D3 COLD in the general control register at offset 4Ch in the PCI configuration space see Section 13 22 When this bit is set to 1 it indicates that the controller is capable of generating a PME wake event from D3c6 g This bit state is dependent upon the PCI7x21 PCI7x11 Vaux implementation and may be configured
296. impedance low level lozL dliput current Output terminals l0ZH i o al E wo o lt o High impedance high level Output terminals output current Input terminals 20 E E 25 I O terminals 3 6 V V GND E IL Low level input current wo o lt IH High level input current Input terminals 5 25 V Vi Vect 20 t For PCI and miscellaneous terminals Vj Vccp For PC Card terminals Vj VCC A B For I O terminals input leakage IL and l H includes loz leakage of the disabled output Miscellaneous terminals are A03 B17 C15 C18 E05 E08 F19 H03 JO1 JO2 J03 JO5 JO6 J07 L02 L03 L05 MO1 MO2 MO3 NO1 NO2 N13 P12 P15 R02 R17 TO1 A CCDx A_CDx A CVSx A VSx B_CCDx B CDx B CVSx B VSx SD DATO SD DAT2 SD DAT3 SD CMD SD CLK SD DAT1 SM CLE SC CD SC OC SC PWR CTRL CLK 48 SDA SCL DATA LATCH TESTO CNA SUSPEND PHY TEST MA and GRST terminals V V uA uA uA uA uA H N o H l4 i N N o o o o 14 4 14 4 Electrical Characteristics Over Recommended Ranges of Operating Conditions unless otherwise noted 14 4 1 Device PARAMETER TEST CONDITION MN MAX UNIT VTH Power status threshold CPS inputt 400 kQ resistort 4 7 7 5 Vo TPBIAS output voltage At rated lg current 1 665 2 015 l Input current PCO PC2 inputs Voc 3 6 V t Measured at cable power side of resistor 14 4 2 Driver PARAMETER TEST CONDITION MIN MAX UNIT
297. implement the circuit that best fits the application The LED activity signals are valid when a card is inserted powered and not in reset For PC Card 16 the LED activity signals are pulsed when READY IREQ is low For CardBus cards the LED activity signals are pulsed if CFRAME IRDY or CREQ are active Current Limiting R 150 Q MFUNCx PCI7x21 Current Limiting Socket A PCI7x11 R 150 Q LED MFUNCy VS Socket B gt Na Figure 3 6 Two Sample LED Circuits As indicated the LED signals are driven for a period of 64 ms by a counter circuit To avoid the possibility of the LEDs appearing to be stuck when the PCI clock is stopped the LED signaling is cut off when the SUSPEND signal is asserted when the PCI clock is to be stopped during the clock run protocol or when in the D2 or D1 power state If any additional socket activity occurs during this counter cycle then the counter is reset and the LED signal remains driven If socket activity is frequent at least once every 64 ms then the LED signals remain driven 3 5 10 CardBus Socket Registers The PCI7x21 PCI7x11 controller contains all registers for compatibility with the PCI Local Bus Specification and the PC Card Standard These registers which exist as the CardBus socket registers are listed in Table 3 7 Table 3 7 CardBus Socket Registers 3 5 11 48 MHz Clock Requirements The PCI7x21 PCI7x11 controller is designed to use an external 48 MHz
298. in the type column Table 4 1 describes the field access tags The PCI7x21 PCI7x11 controller is a multifunction PCI device The flash media controller core is integrated as PCI function 3 The function 3 configuration header is compliant with the PC Local Bus Specification as a standard header Table 11 1 illustrates the configuration header that includes both the predefined portion of the configuration space and the user definable registers Table 11 1 Function 3 Configuration Register Map REGISTER NAME Device ID Vendor ID Class code Revision ID Header type Latency timer Flash media base address Reserved 14h 28h Subsystem vendor ID Subsystem ID Reserved Reserved management capabilities pointer Reserved Maximum latency Interrupt pin Interrupt line Power management capabilities Next item pointer Capability ID PM data PMCSR_BSE Power management control and status Reserved Reserved General control Subsystem access Reserved Diagnostic Reserved 58h FCh One or more bits in this register are cleared only by the assertion of GRST 11 1 Vendor ID Register The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device The vendor ID assigned to Texas Instruments is 104Ch pe eee AS AETA pA TA Vendor ID Type R R R R R R Default 1 0 1 0 4 1 Register Vendor ID Offset 00h Type Read only Default 104Ch 11 2 Devic
299. indow 1 is prefetchable default PREFETCHO 7 INTR RW PCI interrupt IREQ routing enable This bit is used to select whether PC Card functional interrupts are routed to PCI interrupts or to the IRQ specified in the ExCA registers 0 Functional interrupts are routed to PCI interrupts default 1 Functional interrupts are routed by ExCA registers Table 4 7 Bridge Control Register Description Continued SIGNAL TYPE i FUNCTION CardBus reset When this bit is set the CRST signal is asserted on the CardBus interface The CRST signal can also be asserted by passing a PRST assertion to CardBus 0 CRST is deasserted 1 CRST is asserted default This bit is not cleared by the assertion of PRST It is only cleared by the assertion of GRST MABTMODE RW a nw n CSERREN RW H CPERREN RW Master abort mode This bit controls how the PCI7x21 PCI7x11 controller responds to a master abort when the PCI7x21 PCI7x11 controller is an initiator on the CardBus interface This bit is common between each socket 0 Master aborts not reported default 1 Signal target abort on PCI and signal SERR if enabled This bit returns O when read VGA enable This bit affects how the PCI7x21 PCI7x11 controller responds to VGA addresses When this bit is set accesses to VGA addresses are forwarded ISA mode enable This bit affects how the PCI7x21 PCI7x11 controller passes I O cycles within the 64 Kbyte ISA ra
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301. ion 12 22 Section 13 22 01h INTA 01h INTA Oth INTA 01h INTA 01h INTA 01h INTA NOTE When configuring the PCI7x21 PCI7x11 functions to share PCI interrupts multifunction terminal MFUNC3 must be configured as IRQSER prior to setting the INTRTIE bit 7 10 7 16 Minimum Grant and Maximum Latency Register The minimum grant and maximum latency register communicates to the system the desired setting of bits 15 8 in the latency timer and class cache line size register at offset OCh in the PCI configuration space see Section 7 6 If a serial EEPROM is detected then the contents of this register are loaded through the serial EEPROM interface after a GRST If no serial EEPROM is detected then this register returns a default value that corresponds to the MAX LAT 4 MIN_GNT 2 See Table 7 13 for a complete description of the register contents 115 ais rn o 7 Pe sf AP se 2 fo Minimum grant and maximum latency Name Minimum grant and maximum latency petam 0 o 6 e o o o o feo te tea Register Minimum grant and maximum latency Offset 3Eh Type Read Update Default 0402h Table 7 13 Minimum Grant and Maximum Latency Register Description RG controller may need to access the PCI bus as often as every 0 25 us thus an extremely high priority level is requested Bits 11 8 of this field may also be loaded through the serial EEPROM Minimum grant The contents of this field may be used by
302. ion 8 21 are set to 1 this cycle too long interrupt mask enables interrupt generation unrecoverableError RSC When this bit and bit 24 unrecoverableError in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this unrecoverable error interrupt mask enables interrupt generation cyclelnconsistent RSC When this bit and bit 23 cyclelnconsistent in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this inconsistent cycle interrupt mask enables interrupt generation cycleLost RSC When this bit and bit 22 cycleLost in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this lost cycle interrupt mask enables interrupt generation cycle64Seconds RSC When this bit and bit 21 cycle64Seconds in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this 64 second cycle interrupt mask enables interrupt generation cycleSynch RSC When this bit and bit 20 cycleSynch in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this isochronous cycle interrupt mask enables interrupt generation phy RSC When this bit and bit 19 phy in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this PHY status transfer interrupt mask enables interrupt generation 30 29 28 27 26 25 24 23 22 21 20 19 8 N o Table 8 16 Interrupt Mask Register De
303. iption 8 16 Isochronous Receive Channel Mask Low Register Description 8 17 Interrupt Event Register Description o00ooooooomom o 8 18 Interrupt Mask Register Description cece eee eee 8 20 Isochronous Transmit Interrupt Event Register Description 8 22 Isochronous Receive Interrupt Event Register Description 8 24 Initial Bandwidth Available Register Description 8 25 Initial Channels Available High Register Description 8 26 Initial Channels Available Low Register Description 8 26 Fairness Control Register Description aa 8 27 Link Control Register Description a 8 28 Node Identification Register Description ooooooo 8 29 PHY Control Register Description 2a pama criar ae 8 30 Isochronous Cycle Timer Register Description 8 31 Asynchronous Request Filter High Register Description 8 32 Asynchronous Request Filter Low Register Description 8 34 Physical Request Filter High Register Description 8 35 Physical Request Filter Low Register Description 8 37 Asynchronous Context Control Register Description 8 38 Asynchronous Context Command Pointer Register Description 8 39 Isochronous Transmit Context Control Register Description 8 40 Isochronous Receive Context
304. is a digital input signal from A CAUDIO B CAUDIO a PC Card to the system speaker The controller pcia Pelo4 PU3 Voca supports the binary audio mode and outputs a binary VECB signal from the card to SPKROUT SAR Sas am CardBus lock CBLOCK is used to gain exclusive Voca E1 1 l PCIlI4 PCIO4 PU3 pes o access toa target io row pios feus VCcB CardBus detect 1 and CardBus detect 2 CCD1 and CCD2 are used in conjunction with CVS1 and CVS2 F i TTLI2 PU4 to identify card insertion and interrogate cards to determine the operating voltage and card type CardBus device select The controller asserts CDEVSEL to claim a CardBus cycle as the target eee SSS device As a CardBus initiator on the bus the Voca H1 y l PCII4 PCIO4 P GE AG ay B CDEVSEL a controller monitors CDEVSEL until a target responds 19 G GIG Ya VCCB If no target responds before timeout occurs then the controller terminates the cycle with an initiator abort bus after the current data transaction has been completed PCIO4 NCCA VCCB both sampled asserted wait states are inserted CardBus parity error CPERR reports parity errors during CardBus transactions except during special VCCA beg y PCII4 PCIO4 cycles It is driven low by a target two clocks following VECB the data cycle during which a parity error is detected A CFRAME to grant a CardBus PC Card access to the CardBus por pois NCCA VCCB CTRDY are asserted Until CIRDY and CTRDY are A_CPE
305. is register controls how the ExCA registers for the socket respond to card removal It also reports the status of the VS1 and VS2 signals at the PC Card interface Table 5 14 describes each bit in the ExCA card detect and general control register Bit 4 3 Name ExCA card detect and general control mwe rR R w w R R w R CEE a A AAA A AE A Register ExCA card detect and general control Offset CardBus Socket Address 816h Card A ExCA Offset 16h Card B ExCA Offset 56h Type Read only Write only Read Write Default XX00 0000b Table 5 14 ExCA Card Detect and General Control Register Description SIGNAL TYPE FUNCTION VS2 This bit reports the current state of the VS2 signal at the PC Card interface and therefore does not have a default value 7t VS2STAT 0 VS2 is low 1 VS2 is high VS1 This bit reports the current state of the VS1 signal at the PC Card interface and therefore does not E VSISTAT have a default value t 0 VS1 is low 1 VS1 is high Software card detect interrupt If card detect enable bit 3 in the ExCA card status change interrupt configuration register ExCA offset 805h see Section 5 6 is set then writing a 1 to this bit causes a card detect card status change interrupt for the associated card socket If the card detect enable bit is cleared to 0 in the ExCA card status change interrupt configuration register 5 SWCSC W ExCA offset 805h see Section 5 6 then writing a 1
306. ister contents Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Isochronous receive interrupt event Name 9 agn fo fo fofofofofofofofofofofofofofo Co AAA EIA Name Isochronous receive interrupt event fee R AR R R R R R A aA A AR R asc asc asc asc Deta o o o o fo fo foto ft oftotototxi x xt x Register Isochronous receive interrupt event Offset AOh set register A4h clear register returns the contents of isochronous receive interrupt event register bit wise ANDed with the isochronous receive mask register when read Type Read Set Clear Read only Default 0000 000Xh Table 8 18 Isochronous Receive Interrupt Event Register Description BIT FIELD NAME TYPE DESCRIPTION 31 4 RSVD R Reserved Bits 31 4 return Os when read Isochronous receive channel 3 caused the interrupt event register bit 7 isochRx interrupt 2 isoRecv2 RSC Isochronous receive channel 2 caused the interrupt event register bit 7 isochRx interrupt eee ee ESO Isochronous receive channel 1 caused the interrupt event register bit 7 isochRx interrupt isoRecv0 RSC Isochronous receive channel 0 caused the interrupt event register bit 7 isochRx interrupt 8 24 8 26 Isochronous Receive Interrupt Mask Register The isochronous receive interrupt mask set clear register enables the isochRx interrupt source on a per channel basis Reads from eithe
307. ister is 1 _ default _ 1 PME signal is routed to the PME RI_OUT terminal of the PCI7x21 PCI7x11 controller NOTE If this bit bit 0 is O and bit 7 of the card control register PCI offset 91h see Section 4 38 is 0 then the output on the PME RI_OUT terminal is placed in a high impedance state This bit is cleared only by the assertion of GRST These bits are global in nature and must be accessed only through function 0 4 30 MC_CD Debounce Register This register provides debounce time in units of 2 ms for the MC_CD signal on UltraMedia cards This register defaults to 19h which gives a default debounce time of 50 ms All bits in this register are reset by GRST only MC_CD debounce Register MC_CD debounce Offset 84h Functions 0 1 Type Read Write Default 19h 4 20 4 31 General Control Register The general control register provides top level PCI arbitration control It also provides the ability to disable the 1394 OHCI function and provides control over miscellaneous new functionality See Table 4 9 for a complete description of the register contents 7 6 5 4 3 2 1 0 Name General control o RR AW AW AW AW A A A A AW AW AW A AW AW Deen o o o lo o olol o o lololol oloi Register General control Offset 86h Type Read Write Read only Default 0003h 4 21 Table 4 9 General Control Register Description SIGNAL TYPE FUNCTION Flash media power control
308. isters CardBus CardA 20h 844h Note The CardBus socket ExCA base address mode register is separate for functions O and 1 800h ExCA Registers Card B 844h Offsets are from the CardBus socket ExCA base address register s base address Figure 5 2 ExCA Register Access Through Memory Table 5 1 ExCA Registers and Offsets Identification and revision Identification and revision ss lt SsSSCid o rr or address window enable DD o o Go ITO window star adaress loma G0 o o a ITO windowo staaderess hgrbye o e 1 0 window 0 end aderess Pighrbye O OB A 1 0 window starragaress higher o o Memory window 2 sarvaddressiowbye Dp 20 o Memory window 2 offset address high byte HTT t One or more bits in this this register are cleared only by the assertion of GRST when PME is enabled If PME is not enabled then this bit is cleared by the assertion of PRST or GRST E One or more bits in this register are cleared only by the assertion of GRST 5 3 Table 5 1 ExCA Registers and Offsets continued a a IE Memory window 3 sanaos ome da Go Memory window siarraderess gays l o o Memory window 3 erg aderess goya pO a e Memory window 3 ofseraderess moya e o Memory window page regar O Ga pH pO Memory window page register o Cd Memory window page regeter2 T w pp Memory window page register 3 Merron window O O 5 4 5 1 ExCA Identification and Revision Regi
309. it is always reset unless overridden by the socket force event register offset OCh see Section 6 4 This bit defaults to 0 wo o 3 V socket This bit indicates whether or not the socket can supply Vcc 3 3 Vdc to PC Cards The PC17x21 PC17X11 controller does support 3 3 V Vcc therefore this bit is always set unless overridden by the socket force event register offset OCh see Section 6 4 overridden by the socket force event register offset OCh see Section 6 4 This bit defaults to 0 3VSOCKET 5VSOCKET 27 14 RSVD 131 YVCARD 121 XVCARD 5 V socket This bit indicates whether or not the socket can supply Vcc 5 Vdc to PC Cards The PCI7x21 PCI7x11 controller does support 5 V Vcc therefore this bit is always set unless overridden by bit 6 of the device control register PCI offset 92h see Section 4 39 Mm 00 These bits return Os when read ye o YV card This bit indicates whether or not the PC Card inserted in the socket supports Vcc Y Y Vdc This bit can be set by writing a 1 to the corresponding bit in the socket force event register offset OCh see Section 6 4 XV card This bit indicates whether or not the PC Card inserted in the socket supports Vcc X X Vdc This bit can be set by writing a 1 to the corresponding bit in the socket force event register offset OCh see Section 6 4 3 V card This bit indicates whether or not the PC Card inserted in the socket supports Vcc 3 3 Vdc This bit ca
310. ite error RSVD Reserved Bits 30 24 return Os when read selflDGeneration The value in this field increments each time a bus reset is detected This field rolls over to O after reaching 255 RSVD Reserved Bits 15 11 return Os when read selfIDSize This field indicates the number of quadlets that have been written into the self ID buffer for the current bits 23 16 selflDGeneration field This includes the header quadlet and the self ID data This field is cleared to Os when the self ID reception begins oR Reserved Bits 1 and 0 return Os when read 8 19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set clear register enables packet receives from the upper 32 isochronous data channels A read from either the set register or clear register returns the content of the isochronous receive channel mask high register See Table 8 13 for a complete description of the register contents Bt 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name isccfromousrecevechamnmelmaskhigh Isochronous receive channel mask high betau x x x x x x x x x x x x x x x x Bit 15 14 13 12 11 10 9 8 7 6 5 Name Isochronous receive channel mask high pea x x x AA AAA E OA E Xx x Register Isochronous receive channel mask high Offset 70h set register 74h clear register Type Read Set Clear Default XXXX
311. ith the PCI clock The packet data describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA INTB INTC and INTD For details on the IRQSER protocol refer to the document Serialized RQ Support for PCI Systems 3 7 6 SMI Support in the PCI7x21 PCI7x11 Controller The PCI7x21 PCI7x11 controller provides a mechanism for interrupting the system when power changes have been made to the PC Card socket interfaces The interrupt mechanism is designed to fit into a system maintenance interrupt SMI scheme SMI interrupts are generated by the PCI7x21 PCI7x11 controller when enabled after a write cycle to either the socket control register CB offset 10h see Section 6 5 of the CardBus register set or the ExCA power control register ExCA offset 02h 42h 802h see Section 5 3 causes a power cycle change sequence to be sent on the power switch interface The SMI control is programmed through three bits in the system control register PCI offset 80h see Section 4 29 These bits are SMIROUTE bit 26 SMISTATUS bit 25 and SMIENB bit 24 Table 3 13 describes the SMI control bits function Table 3 13 SMI Control BIT NAME FUNCTION SMIROUTE This shared bit controls whether the SMI interrupts are sent as a CSC interrupt or as IRQ2 SMISTAT This socket dependent bit is set when an SMI interrupt is pending This status flag is cleared by writing back a 1 SMIENB When set SMI interrupt generation is enabled This bit is sh
312. its 13 10 7 5 3 1 0 General purpose event status register PCI offset 88h see Section 4 32 bits 7 6 4 0 General purpose event enable register PCI offset 89h see Section 4 33 bits 7 6 4 0 General purpose output register PCI offset 8Bh see Section 4 35 bits 4 0 Multifunction routing register PCI offset 8Ch see Section 4 36 bits 31 0 Retry status register PCI offset 90h see Section 4 37 bits 7 5 3 1 Card control register PCI offset 91h see Section 4 38 bits 7 2 0 Device control register PCI offset 92h see Section 4 39 bits 7 5 3 0 Diagnostic register PCI offset 93h see Section 4 40 bits 7 0 Power management capabilities register PCI offset A2h see Section 4 43 bit 15 Power management CSR register PCI offset A4h see Section 4 44 bits 15 8 Serial bus data register PCI offset BOh see Section 4 47 bits 7 0 Serial bus index register PCI offset B1h see Section 4 48 bits 7 0 Serial bus slave address register PCI offset B2h see Section 4 49 bits 7 0 Serial bus control status register PCI offset B3h see Section 4 50 bits 7 3 0 ExCA identification and revision register ExCA 800h 840h see Section 5 1 bits 7 0 ExCA global control register ExCA 81Eh 85Eh see Section 5 20 bits 2 0 CardBus socket power management register CardBus 20h see Section 6 6 bits 25 24 The global reset only bit function 2 is Subsystem vendor ID register PCI offset 2Ch see Section 7 12 bits 15 0 S
313. ket and the end of a subaction gap Bit 21 cycleMaster in the link control register is cleared by this event Bit 29 is used by software to generate a PCI7x21 PCI7x11 interrupt for its own use unrecoverableError RSCU This event occurs when the PCI7x21 PCI7x11 controller encounters any error that forces it to stop operations on any or all of its subunits for example when a DMA context sets its dead bit to 1 While bit 24 is set to 1 all normal interrupts for the context s that caused this interrupt are blocked from being set to 1 cyclelnconsistent RSCU A cycle start was received that had values for the cycleSeconds and cycleCount fields that are different from the values in bits 31 25 cycleSeconds field and bits 24 12 cycleCount field in the isochronous cycle timer register at OHCI offset FOh see Section 8 34 N wo 8 18 Table 8 15 Interrupt Event Register Description Continued BIT FIELD NAME TYPE DESCRIPTION 22 cycleLost RSCU A lost cycle is indicated when no cycle start packet is sent or received between two successive cycleSynch events A lost cycle can be predicted when a cycle_start packet does not immediately follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after a cycleSynch event without an intervening cycle start Bit 22 may be set to 1 either when a lost cycle occurs or when logic predicts that one will occur 21 cycle64Seconds RSCU
314. l binary audio signal available only when the card and socket have been configured for the 16 bit I O interface The audio signals from cards A and B are combined by the controller and are output on SPKROUT DMA request BVD2 can be used as the DMA request signal during DMA Battery voltage detect 1 BVD1 is generated by 16 bit memory PC Cards that include batteries BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card Both BVD1 and BVD2 are high when the battery is good When BVD2 is low and BVD1 is high the battery is weak and must be replaced When BVD1 is low the battery is no longer serviceable and the data in the memory PC Card is lost See Section 5 6 ExCA Card Status Change Interrupt Vocal Configuration Register for enable bits See Section 5 5 EXCA Card VecB Status Change Register and Section 5 2 ExCA Interface Status Register for the status bits for this signal Status change STSCHG alerts the system to a change in the READY write operations to a 16 bit PC Card that supports DMA The PC Card asserts BVD2 to indicate a request for a DMA operation pulled low For signal status see Section 5 2 ExCA Interface Status Register G12 M18 Card enable 1 and card enable 2 CE1 and CE2 enable even and odd numbered B12 L19 address bytes CE1 enables even numbered address bytes and CE2 enables odd numbered address bytes A_ A_INPACK eG B B INPACK 1 O read IORD is asserted by the
315. latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the PCI7x21 PCI7x11 controller See Table 7 5 for a complete description of the register contents js 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o0 Name Latency timer and class cache line size Default Saan a timer and class cache line size Offset OCh Type Read Write Default 0000h Table 7 5 Latency Timer and Class Cache Line Size Register Description BIT FIELD NAME TYPE DESCRIPTION PCI latency timer The value in this register specifies the latency timer for the PCI7x21 PCI7x11 controller in units of PCI clock cycles When the PCI7x21 PCI7x11 controller is a PCI bus initiator and asserts 15 8 LATENCY_TIMER RW FRAME the latency timer begins counting from zero If the latency timer expires before the PCI7x21 PCI7x11 transaction has terminated then the PCI7x21 PCI7x11 controller terminates the transaction when its GNT is deasserted The default value for this field is 00h Cache line size This value is used by the PCI7x21 PCI7x11 controller during memory write and invalidate memory read line and memory read multiple transactions The default value for this field is OOh 7 0 CACHELINE_SZ RW 7 5 7 7 Header Type and BIST Register The header type and built in self test BIST register indicates the PCI7x21 PCI7x11 PCI header type and no built in self test See
316. le 13 5 Latency Timer and Class Cache Line Size Register Description FIELD NAME TYPE DESCRIPTION 15 8 LATENCY_TIMER RW PCI latency timer The value in this register specifies the latency timer for the Smart Card controller in units of PCI clock cycles When the Smart Card controller is a PCI bus initiator and asserts FRAME the latency timer begins counting from zero If the latency timer expires before the Smart Card transaction has terminated then the Smart Card controller terminates the transaction when its GNT is deasserted 7 0 CACHELINE_SZ RW Cache line size This value is used by the Smart Card controller during memory write and invalidate memory read line and memory read multiple transactions 13 5 13 7 Header Type and BIST Register The header type and built in self test BIST register indicates the Smart Card controller PCI header type and no built in self test See Table 13 6 for a complete description of the register contents atera Tesla Header type and BIST meme Default Register Header type and BIST Offset OEh Type Read only Default 0080h Table 13 6 Header Type and BIST Register Description FIELD NAME TYPE DESCRIPTION 15 8 BIST Built in self test The Smart Card controller does not include a BIST therefore this field returns 00h when read 7 0 HEADER_TYPE PCI header type The Smart Card controller includes the standard PCI header Bit 7 indicates if the Smart Card is a multifunctio
317. le to assert this signal When SERR is enabled in the command register this signal also pulses indicating that an address parity error has occurred on a CardBus interface IE a AMA Pullup resistor per PCIOS VCCP PCI specification Pullup resistor per POIS Paga VecP PCI specification Pullup resistor per Pele PCIO3 VCCP PCI specification n m pu pe PCI cycle stop signal STOP is driven by a PCI target to request the initiator to stop the current PCI bus transaction STOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers PCI target ready TRDY indicates the ability of the primary bus target to complete the current data phase of the transaction A data phase is completed on a rising edge of PCLK when both IRDY and TRDY are asserted Until both IRDY and TRDY are asserted wait states are inserted PCI parity error indicator PERR is driven by a PCI controller to indicate Puillua fesisionper that calculated parity does not match PAR when PERR is enabled PCII3 PCIO3 VECP PCI sak through bit 6 of the command register PCI offset 04h see Section 4 4 4 D O lt Table 2 9 Multifunction and Miscellaneous Terminals The power rail designation is not applicable for the multifunction and miscellaneous terminals quae ee O PU EXTERNAL PIN STRAPPING DESCRIPTION TYPE INPUT OUTPUT PD COMPONENTS IF UNUSED _ KC enable These output terminals control an
318. lementing CardBus Device Class Power Management 3 8 1 1394 Power Management Function 2 The PCI7x21 PCI7x11 controller complies with PCI Bus Power Management Interface Specification The controller supports the DO uninitialized DO active D1 D2 and D3 power states as defined by the power management definition in the 1394 Open Host Controller Interface Specification Appendix A 4 and PCI Bus Power Management Specification PME is supported to provide notification of wake events Per Section A 4 2 the 1394 OHCI sets PMCSR PME STS in the DO state due to unmasked interrupt events In previous OHCI implementations unmasked interrupt events were interpreted as IntEvent n amp amp IntMask n amp amp IntMask masterlntEnable where n represents a specific interrupt event Based on feedback from Microsoft this implementation may cause problems with the existing Windows power management arcitecture as a PME and an interrupt could be simultaneously signaled on a transition from the D1 to DO state where interrupts were enabled to generate wake events If bit 10 ignore mstrlntEna for pme in the PCI miscellaneous configuration register OHCI offset FOh see Section 7 23 is set then the PCI7x21 PCI7x11 controller implements the preferred behavior as IntEvent n amp amp IntMask n Otherwise the PCI7x21 PC17x11 controller implements the preferred behavior as IntEvent n amp amp IntMask n amp amp IntMask masterIntEnable In addition when the ig
319. lete packet in the FIFO before retransmitting it on the second attempt to ensure delivery An AT threshold of 2K results in a store and forward operation which means that asynchronous data is not transmitted until an end of packet token is received Restated setting the AT threshold to 2K results in only complete packets being transmitted Note that this controller always uses a store and forward operation when the asynchronous transmit retries register at OHCI offset 08h see Section 8 3 is cleared RSVD R Reserved Bit 11 returns 0 when read 10 Gia t RW Enable MPEG CIP timestamp enhancement When bit 9 is set to 1 the enhancement is enabled for MPEG E Shab mpeg ts CIP transmit streams FMT 20h The default value for this bit is 0 This bit is cleared only by the assertion of GRST 9 4 Table 9 3 Link Enhancement Register Description Continued BIT FIELD NAME TYPE DESCRIPTION 9 RSVD R Reserved Bit 9 returns 0 when read Enable DV CIP timestamp enhancement When bit 8 is set to 1 the enhancement is enabled for DV CIP transmit streams FMT 00h The default value for this bit is 0 Enable asynchronous priority requests OHCI Lynx compatible Setting bit 7 to 1 enables the link to enab_unfair respond to requests with priority arbitration It is recommended that this bit be set to 1 The default value for this bit is O This bit is not assigned in the PCI7x21 PCI7x11 follow on products because this bit location lo
320. ll 32 bit PCI cycles for maximum performance Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting The PCI7411 controller can be programmed to accept posted writes to improve bus utilization Function 2 of the PCI7411 controller is compatible with IEEE Std 1394a 2000 and the latest 1394 Open Host Controller Interface Specification The chip provides the IEEE1394 link and 2 port PHY function and is compatible with data rates of 100 200 and 400 Mbits per second Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies The PCI7411 controller provides physical write posting and a highly tuned physical data path for SBP 2 performance Function 3 of the PCI7411 controller is a PCI based Flash Media controller that supports Memory Stick Memory Stick Pro SmartMedia XD SD and MMC cards This function controls communication with these Flash Media cards through a passive PC Card adapter or through a dedicated Flash Media socket In addition this function includes DMA capabilities for improved Flash Media performance Function 4 of the PCI7411 controller is a PCl based SD host controller that supports MMC SD and SDIO cards This function controls communication with these Flash Media cards through a passive PC Card adapter or through a dedicated Flash Media socket In addition this function is compliant with the SD Host Controller Standard Specification and includes
321. ller this field is 0 LCtrl R W Link active status control This bit controls the active status of the LLC as indicated during self ID The logical AND of this bit and the LPS active status is replicated in the L field bit 9 of the self ID packet The LLC is considered active only if both the LPS input is active and the LCtrl bit is set The LCtrl bit provides a software controllable means to indicate the LLC active status in lieu of using the LPS input The LCirl bit is set to 1 by a system hardware reset and is unaffected by a bus reset NOTE The state of the PHY LLC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit If the PHY LLC interface is operational as determined by the LPS input being active received packets and status information continue to be presented on the interface and any requests indicated on the LREQ input are processed even if the LCtrl bit is cleared to 0 C 1 R W Contender status This bit indicates that this node is a contender for the bus or isochronous resource manager This bit is replicated in the c field bit 20 of the self ID packet Jitter 3 PHY repeater jitter This field indicates the worst case difference between the fastest and slowest repeater data delay expressed as Jitter 1 x 20 ns For the PCI7x21 PCI7x11 controller this field is O Pwr_Class 3 R W Node power class This field indicates this node power consumption and source characteristics and is replicate
322. ltage and Operating Free Air Temperature This data manual uses the following conventions to describe time t intervals The format is ta where subscript A indicates the type of dynamic parameter being represented One of the following is used tod propagation delay time tg ten tqis delay time ts setup time and tp hold time ALTERNATE PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNIT PCLK to shared signal t 11 valid delay time val Ci 50 pF tpd Propagation delay time See Note 4 L pu p PCLK to shared signal A See Note 4 7 invalid delay time iny fen Enable time igh impedance o atve delay ime rom POLK on eis Disable time activo high impedance delay metrom POLK tot z E p7 CT CU TJ UU 14 6 15 Mechanical Information The PCI7x21 PCI7x11 device is available in the 288 terminal MicroStar BGA package GHk or the 288 terminal lead Pb atomic number 82 free MicroStar BGA package ZHK The following figure shows the mechanical dimensions for the GHK package The GHK and ZHK packages are mechanically identical therefore only the GHK mechanical drawing is shown GHK S PBGA N288 PLASTIC BALL GRID ARRAY 000 000 OO 000 000 000 000000000Y000000000 00000000006000000000O O 000 OPOOO O OOO O OO 000 0 0 OPOOOOO O00 00000 O O00 OPOO0O 00000000000000000 PUOQUMTOICAPFZEZUDAC lt S lt 00000000000000000 0000000000000000000 0000000000
323. lutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security Telephony www ti com telephony Video amp Imaging www ti com video Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright O 2004 Texas Instruments Incorporated Contents Section Title INMOGUCHON cit nie bana nia bet ond ADA 1 1 Controller Functional Description cee eee eee 1 1 1 POI7621 Controler 55 pama ka kaka AKUN ATA as 1 1 2 PO 7421 GCOmraen voi apa se KGG WENG EK ANON K RAR 1 1 3 POI7611 Controller oe ec ges up a HAGGANG oe 1 1 4 PCI7411 Controller 0 ccc ccc cece eee 1 1 5 Multifunctional Terminals soi ovis eine ewes 1 1 6 PCI Bus Power Management o ococccccccccc 1 1 7 Power Switch Interface aaa era 1 2 Features 0 cect E EE AUR E BAR E eens 1 3 Related Documents 00 0c ccc ete e eee 1 4 Trademarks 0 2 0 0 ccc cette eee tenes 1 5 Terms and DSUMIONS eso mk AKA KG KA estab seers ABR AREA KAG aks 1 6 Ordering Informati n ccverticexcRacmnereatviev
324. m Phy Enable Link Enh bit 2 Link Enh enab unfair enab accel Mini ROM address this byte indicates the MINI ROM offset into the EEPROM 00h No MINI ROM Other Values MINI ROM offset OHCI 24h GUIDHi byte O OHCI 25h GUIDHi byte 1 OHCI 26h GUIDHi byte 2 OHCI 27h GUIDHi byte 3 OHCI 28h GUIDLo byte O OHCI 29h GUIDLo byte 1 OHCI 2Ah GUIDLo byte 2 OHCI 2Bh GUIDLo byte 3 Checksum Reserved no bit loaded PCI F5h Link_Enh byte 1 bits 7 6 5 4 PCI FOh PCI miscellaneous byte O bits 5 4 2 1 0 PCI F1h PCI miscellaneous byte 1 bits 7 3 2 1 0 Reserved CardBus CIS pointer Mm oj Y mo Q N N TY m o eg wj j amp aJ AJN ga a gt al PCI ECh PCI PHY control bits 7 3 1 Flash media core function indicator 03h Number of bytes 05h PCI 2Dh subsystem vendor ID byte 1 a PCI 2Eh subsystem ID byte 0 PCI 2Fh subsystem ID byte 1 PCI 2Ch subsystem vendor ID byte O 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 42h 43h 44h 45h 46h 47h 48h Table 3 9 EEPROM Loading Map Continued e Po gan SIOLOSSVmavimUMoueME CS E E SSCSCSC S E E i an ese POT ABR sot 58 3 V maximum coren O amn san Gon also code bye Po las ie E a E Pa subsystem vendor bye sah NN YT TT MCU E sah NN Ba general eonrol bis 64 son GIBO Sma Gar coniguraton bie 0 PS 6412 0 sin sen scx son sen PCI 5Ah Smart Card configuration 1 byte 2
325. m a PC Card interface and is socket dependent i e not global Write back a 1 to clear this bit 0 No PC Card functional interrupt detected default 1 PC Card functional interrupt detected This bit is cleared only by the assertion of GRST This bit is global in nature and must be accessed only through function 0 4 28 4 39 Device Control Register The device control register is provided for PCI1130 compatibility It contains bits that are shared between functions 0 and 1 The interrupt mode select is programmed through this register The socket capable force bits are also programmed through this register See Table 4 17 for a complete description of the register contents Bit 4 3 Name Device control yee w w w n w w AW aw CO w d a O d a O aa O a e gg ee Register Device control Offset 92h Functions 0 1 Type Read only Read Write Default 66h Table 4 17 Device Control Register Description SIGNAL TYPE FUNCTION Socket power lock bit When this bit is set to 1 software cannot power down the PC Card socket while in D3 It may be necessary to lock socket power in order to support wake on LAN or RING if the 7t SKTPWR LOCK a A h operating system is programmed to power down a socket when the CardBus controller is placed in the D3 state 3 V socket capable force bit 6 48 3VCAPABLE 0 Not 3 V capable 1 3 V capable default IO16R2 RW Diagnostic bit This bit defaults to 1 RSVD R
326. m memory RU 7 isochRx Isochronous receive DMA interrupt Indicates that one or more isochronous receive contexts have generated an interrupt This is not a latched event it is the logical OR of all bits in the isochronous receive interrupt event register at OHCI offset AOh A4h see Section 8 25 and isochronous receive interrupt mask register at OHCI offset A8h ACh see Section 8 26 The isochronous receive interrupt event register indicates which contexts have been interrupted 6 isochTx RU Isochronous transmit DMA interrupt Indicates that one or more isochronous transmit contexts have generated an interrupt This is not a latched event it is the logical OR of all bits in the isochronous transmit interrupt event register at OHCI offset 90h 94h see Section 8 23 and isochronous transmit interrupt mask register at OHCI offset 98h 9Ch see Section 8 24 The isochronous transmit interrupt event register indicates which contexts have been interrupted 5 RSPkt RSCU Indicates that a packet was sent to an asynchronous receive response context buffer and the descriptor xferStatus and resCount fields have been updated 4 RQPkt RSCU Indicates that a packet was sent to an asynchronous receive request context buffer and the descriptor xferStatus and resCount fields have been updated 3 ARRS RSCU Asynchronous receive response DMA interrupt Bit 3 is conditionally set to 1 upon completion of an ARRS DMA context command descriptor 2 ARRQ RSCU Async
327. memory read transactions to burst downstream RW R VCCPROT MRBURSTDN 0 MRBURSTDN downstream is disabled 1 MRBURSTDN downstream is enabled default Memory read burst enable upstream When this bit is set the PCI7x21 PCI7x11 controller allows memory read transactions to burst upstream 0 MRBURSTUP upstream is disabled default 1 MRBURSTUP upstream is enabled Socket activity status When set this bit indicates access has been performed to or from a PC Card Reading this bit causes it to be cleared This bit is socket dependent 0 No socket activity default 1 Socket activity Reserved This bit returns 1 when read Power stream in progress status bit When set this bit indicates that a power stream to the power switch is in progress and a powering change has been requested When this bit is cleared it indicates PWRSTREAM that the power stream is complete 0 Power stream is complete delay has expired default 1 Power stream is in progress Power up delay in progress status bit When set this bit indicates that a power up stream has been sent to the power switch and proper power may not yet be stable This bit is cleared when the power up DELAYUP delay has expired 0 Power up delay has expired default 1 Power up stream sent to switch Power might not be stable Power down delay in progress status bit When set this bit indicates that a power down stream has been sent to the power switch and pr
328. mp offset register and substitutes it in the SYT field of the CIP once per DV frame Bit 10 enab_mpeg_ts of the link enhancement control register enables MPEG timestamp support Two MPEG time stamp modes are supported The default mode calculates an initial delta that is added to the calculated timestamp in addition to a user defined offset The initial offset is calculated as the difference in the intended transmit cycle count and the cycle count field of the timestamp in the first TSP of the MPEG2 stream The use of the initial delta can be controlled by bit 31 DisablelnitialOffset in the timestamp offset register see Section 9 5 The MPEG2 timestamp enhancements are enabled by bit 10 enab_mpeg_ts in the link enhancement control register located at PCI offset F4h and aliased in TI extension register space at offset A88h set and A8Ch clear When bit 10 enab_mpeg_ts is set to 1 the hardware applies the timestamp enhancements to isochronous transmit packets that have the tag field equal to 01b in the isochronous packet header and a FMT field equal to 10h 9 2 Isochronous Receive Digital Video Enhancements The DV frame sync and branch enhancement provides a mechanism in buffer fill mode to synchronize 1394 DV data that is received in the correct order to DV frame sized data buffers described by several INPUT_MORE descriptors see 1394 Open Host Controller Interface Specification Release 1 1 This is accomplished by waiting for the start
329. n Os when read These bits must be Os for normal operation PHYRST PHY reset This bit controls the RST input to the PHY When bit 4 is set the PHY reset is asserted The default value is O This bit must be O for normal operation RSVD Reserved Bit 3 defaults to 1 to indicate compliance with IEEE Std 1394a 2000 This bit is loaded via the serial EEPROM as defined by Table 3 9 and must be 1 for normal operation This bit controls the power down input to the PHY When bit 2 is set the PHY is in the power down mode and enters the ULP mode if the LPS is disabled If PD is asserted then a reset to the physical layer must be initiated via bit 4 PHYRST after PD is cleared The default value is 0 This bit must be 0 for normal operation Reserved Bits 1 0 return Os when read These bits are affected when implementing a serial EEPROM thus bits 1 0 are loaded via the serial EEPROM as defined by Table 3 9 and must be Os for normal operation These bits are cleared only by the assertion of GRST 7 23 PCI Miscellaneous Configuration Register The PCI miscellaneous configuration register provides miscellaneous PCl related configuration See Table 7 20 for a complete description of the register contents PCI miscellaneous configuration Type rw r rw a Rw pw ew aw A r R RW RW Deau o o o o fo o fo fo fo fo fo fo fo fo Register PCI miscellaneous configuration Offset FOh Type Read
330. n be set by writing a 1 to the corresponding bit in the socket force event register offset OCh see Section 6 4 5 V card This bit indicates whether or not the PC Card inserted in the socket supports Vcc 5 Vdc 111 3VCARD 104 5VCARD This bit can be set by writing a 1 to the corresponding bit in the socket force event register offset OCh see Section 6 4 t One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled If PME is not enabled then these bits are cleared by the assertion of PRST or GRST 6 4 Table 6 4 Socket Present State Register Description Continued SIGNAL FUNCTION BADVCCREQ BIT 9t BESO EE Cn Bad Vcc request This bit indicates that the host software has requested that the socket be powered at an invalid voltage 0 Normal operation default 1 Invalid Vcc request by host software Data lost This bit indicates that a PC Card removal event may have caused lost data because the cycle did not terminate properly or because write data still resides in the PCI7x21 PCI7x11 controller 0 Normal operation default 1 Potential data loss due to card removal Not a card This bit indicates that an unrecognizable PC Card has been inserted in the socket This bit is not updated until a valid PC Card is inserted into the socket 0 Normal operation default 1 Unrecognizable PC Card detected READY IREQ CINT This bit in
331. n device 13 8 Smart Card Base Address Register 0 This register is used by this function to determine where to forward a memory transaction to the Smart Card global control register set Bits 31 12 of this register are read write and allow the base address to be located anywhere in the 32 bit PCI memory space on 4 Kbyte boundary The window size is always 4K bytes Bits 11 0 are read only and always return Os Write transactions to these bits have no effect Bit 3 Ob specifies that this window is nonprefetchable Bits 2 1 00b specify that this memory window can allocate anywhere in the 32 bit address space were Rw RW RW RW R Default 0 0 0 0 0 Register Smart Card base address register 0 Offset 10h Type Read Write Read only Default 0000 0000h 13 9 Smart Card Base Address Register 1 4 Each socket has its own base address register For example a device supports three Smart Card sockets uses three base address registers BA1 socket 0 BA2 socket 1 and BAS socket 2 These registers are used by this function to determine where to forward a memory transaction to the Smart Card Control and Communication Register sets Bits 31 12 of this register are read write and allow the base address to be located anywhere in the 32 bit PCI memory space on 4 Kbyte boundaries and the window size is always 4K bytes Bits 11 4 are read only and always return Os Write transactions to these bits have no effect Bit 3
332. n of the register contents 27 26 25 24 23 22 21 20 19 18 17 16 Ce T77 Deren o o o lo po liliit lo lo tooo o o0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name T T T 0 0 0 0 0 0 0 0 0 0 0 0 0 Default 0 0 0 Register Class code and revision ID Offset 08h Type Read only Default 0780 0000h Table 13 4 Class Code and Revision ID Register Description BIT FIELD NAME TYPE DESCRIPTION 31 24 BASECLASS R Base class This field returns 07h when read which classifies the function as a communication device 23 16 SUBCLASS R Subclass This field returns 80h when read which specifically classifies the function as other mass storage controller R 15 8 PGMIF Programming interface This field returns 00h when read 7 0 CHIPREV R Silicon revision This field returns 00h when read which indicates the silicon revision of the Smart Card controller 13 6 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the Smart Card controller See Table 13 5 for a complete description of the register contents 115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o0 Name Tanay mer and ass cache Ie a Dean o fo o o lololo o o lolo o o o o Register Latency timer and class cache line size Offset OCh Type Read Write Default 0000h Tab
333. nables the context by setting bit 15 run in the asynchronous context control register see Section 8 40 to 1 See Table 8 32 for a complete description of the register contents Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Asynchronous context command pointer nera coment commander OOOO O RWU RWU pn x x x hhehe AAA ee Asynchronous context command pointer ER CAE Default Register Asynchronous context command pointer Offset 18Ch ATRQ 1ACh ATRS 1CCh ARRQ 1ECh ARRS Type Read Write Update Default XXXX XXXXh Table 8 32 Asynchronous Context Command Pointer Register Description ee FIELD NAME TYPE DESCRIPTION a Contains the upper 28 bits of the address of a 16 byte aligned descriptor block Indicates the number of contiguous descriptors at the address pointed to by the descriptor address If Z is O then it indicates that the descriptorAddress field bits 31 4 is not valid 8 39 8 42 Isochronous Transmit Context Control Register The isochronous transmit context control set clear register controls options state and status for the isochronous transmit DMA contexts The n value in the following register addresses indicates the context number n 0 1 2 3 7 See Table 8 33 for a complete description of the register contents 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 15 Isochronous transmit context control LT
334. nagement control and status Offset 48h Type Read Clear Read Write Read only Default 0000h Table 7 17 Power Management Control and Status Register Description BIT FIELD NAME TYPE DESCRIPTION Bit 15 is set to 1 when the PCI7x21 PCI7x11 controller normally asserts the PME signal independent 154 PME_STS RWC of the state of bit 8 PME_ENB This bit is cleared by a writeback of 1 which also clears the PME signal driven by the PCI7x21 PCI7x11 controller Writing a O to this bit has no effect 14 13 DATA_SCALE This field returns Os because the data register is not implemented 12 9 DATA_SELECT This field returns Os because the data register is not implemented When bit 8 is set to 1 PME assertion is enabled When bit 8 is cleared PME assertion is disabled This 8t PME ENB RW bit defaults to 0 if the function does not support PME generation from D3c g If the function supports PME from D3cold then this bit is sticky and must be explicitly cleared by the operating system each time it is initially loaded 7 2 RSVD R Reserved Bits 7 2 return Os when read Power state This 2 bit field sets the PCI7x21 PCI7x11 controller power state and is encoded as follows 1 0 PWR STATE RW 00 Current power state is DO y 01 Current power state is D1 10 Current power state is D2 11 Current power state is D3 These bits are cleared only by the assertion of GRST 7 21 Power Management Extension Registers The power man
335. nd Status Register Description 13 12 General Control Register o oooooccococcccccncnr 13 13 Subsystem ID Alias Register Description 0ooooooooo o 13 14 xvii xviii Table Title 13 15 Smart Card Configuration 1 Register Description 13 16 Smart Card Configuration 2 Register Description 1 Introduction The Texas Instruments PCI7621 controller is an integrated dual socket UltraMedia PC Card controller Smart Card controller IEEE 1394 open HCI host controller and PHY and flash media controller This high performance integrated solution provides the latest in PC Card Smart Card IEEE 1394 Secure Digital SD MultiMediaCard MMC Memory Stick PRO SmartMedia and XD technology The Texas Instruments PCI7421 controller is an integrated dual socket UltraMedia PC Card controller IEEE 1394 Open HCI host controller and PHY and flash media controller This high performance integrated solution provides the latest in PC Card IEEE 1394 SD MMC Memory Stick PRO SmartMedia and XD technology The Texas Instruments PCI7611 controller is an integrated single socket UltraMedia PC Card controller Smart Card controller IEEE 1394 open HCI host controller and PHY and flash media controller This high performance integrated solution provides the latest in PC Card Smart Card IEEE 1394 SD MMC Memory Stick PRO SmartMedia and XD technology The Texas Instruments PCI7411 controller is an integrated single socket Ultr
336. nd address high byte Offset CardBus Socket Address 813h Card A ExCA Offset 13h Card B ExCA Offset 53h Register ExCA memory window 1 end address high byte Offset CardBus Socket Address 81Bh Card A ExCA Offset 1Bh Card B ExCA Offset 5Bh Register ExCA memory window 2 end address high byte Offset CardBus Socket Address 823h Card A ExCA Offset 23h Card B ExCA Offset 63h Register ExCA memory window 3 end address high byte Offset CardBus Socket Address 82Bh Card A ExCA Offset 2Bh Card B ExCA Offset 6Bh Register ExCA Memory window 4 end address high byte Offset CardBus Socket Address 833h Card A ExCA Offset 33h Card B ExCA Offset 73h Type Read Write Read only Default 00h Table 5 12 ExCA Memory Windows 0 4 End Address High Byte Registers Description BIT SIGNAL TYPE 7 6 MEMWS FUNCTION Wait state These bits specify the number of equivalent ISA wait states to be added to 16 bit memory accesses The number of wait states added is equal to the binary value of these 2 bits RW 5 4 RSVD oR Reserved These bits return Os when read Writes have no effect RW 5 4 End address high nibble These bits represent the upper address bits A23 A20 of the memory window end 3 0 ENDHN address 5 18 5 17 ExCA Memory Windows 0 4 Offset Address Low Byte Registers These registers contain the low byte of the 16 bit memory window offset address for memory windows 0 1 2 3 and 4 The 8 bits of these ie tt
337. ndards for Identification Cards ISO IEC 7816 SD Host Controller Standard Specification rev 1 0 Memory Stick Format Specification Sony Confidential ver 2 0 SmartMedia Standard 2000 May 19 2000 1 4 Trademarks Intel is a trademark of Intel Corporation Tl and MicroStar BGA are trademarks of Texas Instruments FireWire is a trademark of Apple Computer Inc i LINK is a trademark of Sony Corporation of America Memory Stick is a trademark of Sony Kabushiki Kaisha TA Sony Corporation Japan Other trademarks are the property of their respective owners 1 5 Terms and Definitions Terms and definitions used in this document are given in Table 1 1 Table 1 1 Terms and Definitions TERM DEFINITIONS AT advanced technology as in PC AT attachment interface ATA driver An existing host software component that loads when any flash media adapter and card is inserted into a PC Card socket This driver is logically attached to a predefined CIS provided by the PCI7x21 PCI7x11 controller when the adapter and media are both inserted FF Card information structure Tuple list defined by the PC Card standard to communicate card information to the host computer CIS i CS Control and status register Flash Media SmartMedia Memory Stick MS PRO xD MMC or SD MMC Flash operating in an ATA compatible mode ISO IEC 7816 The Smart Card standard MM Memory Stick A small form factor flash interface that is defined promoted and licensed
338. ndent 151 PMESTAT of the state of the PME EN bit This bit is cleared by a writeback of 1 and this also clears the PME signal if PME was asserted by this function Writing a O to this bit has no effect 14 13 DATASCALE DATASEL oR This 2 bit field returns Os when read The CardBus function does not return any dynamic data This bit enables the function to assert PME If this bit is cleared then assertion of PME is disabled This PNE SENARE aN bit is not cleared by the assertion of PRST It is only cleared by the assertion of GRST R Data select This 4 bit field returns Os when read The CardBus function does not return any dynamic data Reserved These bits return Os when read PWRSTATE t One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled If PME is not enabled then this bit is cleared by the assertion of PRST or GRST This bit is cleared only by the assertion of GRST Power state This 2 bit field is used both to determine the current power state of a function and to set the function into a new power state This field is encoded as 00 DO 01 D1 10 D2 11 D3hot 4 33 4 45 Power Management Control Status Bridge Support Extensions Register This register supports PCI bridge specific functionality It is required for all PCI to PCI bridges See Table 4 21 for a complete description of the register contents Name Power management
339. ne Size Register 13 5 13 7 Header Type and BIST Register a 13 6 13 8 Smart Card Base Address Register 0 13 6 13 9 Smart Card Base Address Register 1 4 13 7 13 10 Subsystem Vendor Identification Register 13 7 13 11 Subsystem Identification Register A eee eee eee 13 8 13 12 Capabilities Pointer Register 2 0 23 sama nakakasa 13 8 13 13 Interrupt Line Register isi vos ns vent ARKA NA DRE ANEK W dee herens 13 8 13 14 Interrupt Pin Register ci0 s c veseeeed eae aes 13 9 13 15 Minimum Grant Register naass eect 13 9 13 16 Maximum Latency Register 4 a sanam a RAK KA PARIAN AASA 13 10 13 17 Capability ID and Next Item Pointer Registers 13 10 13 18 Power Management Capabilities Register 13 11 13 19 Power Management Control and Status Register 13 12 13 20 Power Management Bridge Support Extension Register 13 12 13 21 Power Management Data Register a 13 13 13 22 General Control Register a 13 13 13 23 Subsystem ID Alias Register a 13 14 13 24 Class Code Alias Register aa 13 14 13 25 Smart Card Configuration 1 Register 13 15 13 26 Smart Card Configuration 2 Register 13 17 Section Title Page 14 Electrical Characteristics 0 ccc eee
340. neral purpose output register is used to drive the GRO4 GPO0 outputs See Table 4 13 for a complete description of the register contents Name General purpose output Type R RW RW Default 0 0 Register General purpose output Offset 8Bh Type Read only Read Write Default 00h Table 4 13 General Purpose Output Register Description BIT SIGNAL FUNCTION SIGNAL 7 5 nsv R Reseved These bits retum Os when read Writeshavenoeiiect RW _ This bit represents the logical value of the data driven to GPO4 x This bit represents the logical value of the data driven to GPO2 RW 0t GPO0 DATA This bit represents the logical value of the data driven to GPOO This bit is cleared only by the assertion of GRST 4 25 4 36 Multifunction Routing Status Register The multifunction routing status register is used to configure the MFUNC6 MFUNCO terminals These terminals may be configured for various functions This register is intended to be programmed once at power on initialization The default value for this register can also be loaded through a serial EEPROM See Table 4 14 for a complete description of the register contents Multifunction routing status Register Multifunction routing status Offset 8Ch Type Read Write Read only Default 0000 1000h Table 4 14 Multifunction Routing Status Register Description SIGNAL TYPE FUNCTION 31 281 RSVD Bits 31 28 return Os when read
341. ng conditions were met CB_DPAR R a CPERR was asserted on the CardBus interface CDEVSEL timing These bits encode the timing of CDEVSEL and are hardwired to 01b indicating that the PC17x21 PC17x11 controller asserts this signal at a medium speed REC CBTA ES Received target abort This bit is set when a cycle initiated by the PCI7x21 PCI7x11 controller on the b The PCI7x21 PCI7x11 controller was the bus master during the data parity error c The parity error response enable bit bit 0 is set in the bridge control register PCI offset 3Eh see Section 4 25 Fast back to back capable The PCI7x21 PCI7x11 controller cannot accept fast back to back transactions therefore this bit is hardwired to 0 User definable feature support The PCI7x21 PCI7x11 controller does not support user definable CB_UDF par ee features therefore this bit is hardwired to 0 7 CBFBB CAP CB66MHZ 66 MHz capable The PCI7x21 PCI7x11 CardBus interface operates at a maximum CCLK frequency of 33 MHz therefore this bit is hardwired to 0 RSVD These bits return Os when read This bit is cleared only by the assertion of GRST A T o 4 9 4 15 PCI Bus Number Register The PCI bus number register is programmed by the host system to indicate the bus number of the PCI bus to which the PCI7x21 PCI7x11 controller is connected The PCI7x21 PCI7x11 controller uses this register in conjunction with the CardBus bus number and subordinate bus number re
342. nge This bit is not common between sockets When this bit is set the PCI7x21 PCI7x11 controller does not forward the last 768 bytes of each 1K I O range to CardBus CSERR enable This bit controls the response of the PCI7x21 PCI7x11 controller to CSERR signals on the CardBus bus This bit is separate for each socket 0 CSERR is not forwarded to PCI SERR default 1 CSERR is forwarded to PCI SERR CardBus parity error response enable This bit controls the response of the PCI7x21 PCI7x11 to CardBus parity errors This bit is separate for each socket 0 CardBus parity errors are ignored default 1 CardBus parity errors are reported using CPERR t One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled If PME is not enabled then this bit is cleared by the assertion of PRST or GRST 4 26 Subsystem Vendor ID Register The subsystem vendor ID register used for system and option card identification purposes may be required for certain operating systems This register is read only or read write depending on the setting of bit 5 SUBSYSRW in the system control register PCI offset 80h See Section 4 29 When bit 5 is 0 this register is read write when bit 5 is 1 this register is read only The default mode is read only All bits in this register are reset by GRST only Register Subsystem vendor ID Offset 40h Functions 0 1 Type Read
343. nore mstrlntEna for pme bit is set it causes bit 26 of the OHCI vendor ID register OHCI offset 40h see Section 8 15 to read 1 otherwise bit 26 reads 0 An open drain buffer is used for PME If PME is enabled in the power management control status register PCI offset A4h see Section 4 44 then insertion of a PC Card causes the PCI7x21 PCI7x11 controller to assert PME which wakes the system from a low power state D3 D2 or D1 The OS services PME and takes the PCI7x21 PCI7x11 controller to the DO state 3 21 3 8 2 Integrated Low Dropout Voltage Regulator LDO VR The PCI7x21 PCI7x11 controller requires 1 5 V core voltage The core power can be supplied by the PCI7x21 PCI7x11 controller itself using the internal LDO VR The core power can alternatively be supplied by an external power supply through the VR PORT terminal Table 3 14 lists the requirements for both the internal core power supply and the external core power supply Table 3 14 Requirements for Internal External 1 5 V Core Power Supply Internal 1 5 V LDO VR is enabled A 1 0 uF bypass capacitor is required on the VR PORT il Ka GUIP terminal for decoupling This output is not for external use Ext 33V Vv 4 5 V input Internal 1 5 V LDO VR is disabled An external 1 5 V power supply of minimum 50 mA cales CC i pu capacity is required A 0 1 uF bypass capacitor on the VR PORT terminal is required 3 8 3 CardBus Functions 0 and 1 Clock Run Protocol The PCI CLKRUN fea
344. nt are also written The RHB and Gap_Count may also be updated by PHY config packets The PCI7x21 PCI7x11 controller is IEEE 1394a 2000 compliant and therefore both the reception and transmission of PHY config packets cause the RHB and Gap_Count to be loaded unlike older IEEE 1394 1995 compliant PHY devices which decode only received PHY config packets The gap count is set to the maximum value of 63 after 2 consecutive bus resets without an intervening write to the Gap Count either by a write to PHY register 1 or by a PHY config packet This mechanism allows a PHY config packet to be transmitted and then a bus reset initiated so as to verify that all nodes on the bus have updated their RHBs and Gap_Count values without having the Gap_Count set back to 63 by the bus reset The subsequent connection of a new node to the bus which initiates a bus reset then causes the Gap_Count of each node to be set to 63 Note however that if a subsequent bus reset is instead initiated by a write to register 1 to set the IBR bit all other nodes on the bus have their Gap Count values set to 63 while this node Gap Count remains set to the value just loaded by the write to PHY register 1 3 32 Therefore in order to maintain consistent gap counts throughout the bus the following rules apply to the use of the IBR bit RHB and Gap_Count in PHY register 1 Following the transmission of a PHY config packet a bus reset must be initiated in order to verify that
345. ntrol register at offset ECh in the PCI configuration space see Section 7 22 vo Gel Tee END PCI PHY Control Register This bit is loaded by the serial EEPROM If an EEPROM is implemented and CNA functionality is needed then the appropriate bit in the serial EEPROM must be cleared as defined in Table 3 9 TPBIASO TPBIAS1 2 26 Cable power status input This terminal is normally connected to cable power through a 400 kQ resistor This circuit drives an internal comparator that is used to detect the presence of cable power If CPS is not used to detect cable power then this terminal must be pulled to GND Power class programming inputs On hardware reset these inputs set the default value of the power class indicated during self ID Programming is done by tying these terminals high or low Current setting resistor terminals These terminals are connected to an external resistance to set the internal operating currents and cable driver output currents A resistance of 6 34 kQ 1 is required to meet the IEEE Std 1394 1995 output voltage limits Twisted pair cable A differential signal terminals Board trace lengths from each pair of positive and negative differential signal pins must be matched and as short as possible to the external load resistors and to the cable connector For an unused port TPA and TPA can be left open Twisted pair bias output This provides the 1 86 V nominal bias voltage needed for proper operation
346. o INT_STATUS RU in the command register see Section 7 3 is a O and this bit is 1 is the function s INTx signal asserted Setting the INT_DISABLE bit to 1 has no effect on the state of this bit RSVD R Reserved Bits 3 0 return Os when read 7 4 7 5 Class Code and Revision ID Register The class code and revision ID register categorizes the PCI7x21 PCI7x11 controller as a serial bus controller OCh controlling an IEEE 1394 bus 00h with an OHCI programming model 10h Furthermore the TI chip revision is indicated in the least significant byte See Table 7 4 for a complete description of the register contents Register Class code and revision ID Offset 08h Type Read only Default 0C00 1000h Table 7 4 Class Code and Revision ID Register Description FIELD NAME DESCRIPTION BASECLASS gt This field returns OCh when read which broadly classifies the function as a serial bus Subclass This field returns 00h when read which specifically classifies the function as controlling an eee SUBCLASS IEEE 1394 serial bus 15 8 PGMIF R Programming interface This field returns 10h when read which indicates that the programming model is compliant with the 1394 Open Host Controller Interface Specification Silicon revision This field returns 00h when read which indicates the silicon revision of the 72 oases R PGI7x21 PCI7x11 controller 7 6 Latency Timer and Class Cache Line Size Register The
347. o 01b indicating that the flash media controller asserts this signal at a medium speed on nonconfiguration cycle accesses pre TABORT_SIG RCU PCI_SPEED R Data parity error detected Bit 8 is set to 1 when the following conditions have been met a PERR was asserted by any PCI device including the flash media controller DATAPAR RCU b The flash media controller was the bus master during the data parity error c Bit 6 PERR_EN in the command register at offset 04h in the PCI configuration space see Section 11 3 is set to 1 Fast back to back capable The flash media controller cannot accept fast back to back transactions oor therefore bit 7 is hardwired to 0 User definable features UDF supported The flash media controller does not support the UDF therefore bit 6 is hardwired to 0 66 MHz capable The flash media controller operates at a maximum PCLK frequency of 33 MHz cies therefore bit 5 is hardwired to 0 Capabilities list Bit 4 returns 1 when read indicating that the flash media controller supports additional PCI capabilities Interrupt status This bit reflects the interrupt status of the function Only when bit 10 INT_DISABLE in the command register see Section 11 3 is a 0 and this bit is 1 is the function s INTx signal asserted INT_STATUS RU Setting the INT_DISABLE bit to 1 has no effect on the state of this bit This bit is set only when a valid interrupt condition exists This bit i
348. o 1 The LPS terminal can be configured as GPIO1 by setting bit 15 DISABLE_LPS to 1 See Table 7 23 for a complete description of the register contents Bt 31 30 20 28 27 26 25 24 23 22 21 20 19 18 17 16 GPIO control pe contol me R R ww R Rk a Rw rR R Rwjrw a R R Rw GPIO control pe contol Type Rw R rw rw a R Rk rw Rw R Rrw rw R R R Rw petan o o o fo fo fo fo fo ftofofofofofofo fo Register GPIO control Type Read only Read Write Offset FCh Default 0000 0000h Table 7 23 GPIO Control Register Description SIGNAL TYPE FUNCTION 31 30 RSVD R Reserved Bits 31 and 30 return Os when read GPIO3 polarity invert This bit controls the input output polarity control of GPIO3 29 GPIO_INV3 R W 0 Noninverted default 1 Inverted GPIO3 enable control This bit controls the output enable for GPIO3 28 GPIO_ENB3 R W 0 High impedance output default 1 Output is enabled 27 25 RSVD R Reserved Bits 27 25 return Os when read GPIO3 data When GPIO3 output is enabled the value written to this bit represents the logical data GPIO DATAS driven to the GPIO3 terminal 23 22 RSVD R Reserved Bits 23 and 22 return Os when read GPIO2 polarity invert This bit controls the input output polarity control of GPIO2 21 GPIO_INV2 R W 0 Noninverted default 1 Inverted GPIO2 enable control This bit controls the output enable for GP
349. ocation a O written to a bit location has no effect See Table 13 3 for a complete description of the register contents as 14 13 2 9 3 Status Name Type ecu ecu R rR ru r R a rR rR re ek rut er IR CH GA Register Status Offset 06h Type Read Clear Update Read only Default 0210h Table 13 3 Status Register Description FIELD NAME TYPE DESCRIPTION PAR ERR MABORT TABT REC Detected parity error Bit 15 is set to 1 when either an address parity or data parity error is detected Signaled system error Bit 14 is set to 1 when SERR is enabled and the Smart Card controller has signaled a system error to the host This function does not support bus mastering This bit is hardwired to 0 This function does not support bus mastering and never receives a target abort This bit is hardwired to 0 TABT_SIG RCU Signaled target abort Bit 11 is set to 1 by the Smart Card controller when it terminates a transaction on the PCI bus with a target abort DEVSEL timing Bits 10 and 9 encode the timing of DEVSEL and are hardwired to 01b indicating that the Smart Card controller asserts this signal at a medium speed on nonconfiguration cycle accesses PCI_SPEED DATAPAR FBB_CAP RSVD 66MHZ CAPLIST This function does not support bus mastering This bit is hardwired to 0 Fast back to back capable The Smart Card controller cannot accept fast back to back transactions
350. ochronous Receive Context Match Register Description If bit 31 is set to 1 this context matches on isochronous receive packets with a tag field of 11b If bit 30 is set to 1 this context matches on isochronous receive packets with a tag field of 10b If bit 29 is set to 1 this context matches on isochronous receive packets with a tag field of 01b If bit 28 is set to 1 this context matches on isochronous receive packets with a tag field of 00b 27 Rep R Reserved Bit 27 returns 0 when read 26 12 cycleMatch RW This field contains a 15 bit value corresponding to the two low order bits of cycleSeconds and the 13 bit cycleCount field in the cycleStart packet If cycleMatchEnable bit 29 in the isochronous receive context control register see Section 8 44 is set to 1 then this context is enabled for receives when the two low order bits of the isochronous cycle timer register at OHCI offset FOh see Section 8 34 cycleSeconds field bits 31 25 and cycleCount field bits 24 12 value equal this field cycleMatch value 11 8 sync RW This 4 bit field is compared to the sync field of each isochronous packet for this channel when the command descriptor w field is set to 11b 7 RSVD KE Reserved Bit 7 returns 0 when read tag1SyncFilter If bit 6 and bit 29 tag1 are set to 1 then packets with tag 01b are accepted into the context if the two most significant bits of the packet sync field are 00b Packets with tag values other than 01b are
351. of pullup resistors on the SCL and SDA signal lines The PCI7x21 PCI7x11 controller is always the source of the clock signal SCL System designers who wish to load register values with a serial EEPROM must use pullup resistors on the SCL and SDA terminals If the PCI7x21 PCI7x11 controller detects a logic high level on the SCL terminal at the end of GRST then it initiates incremental reads from the external EEPROM Any size serial EEPROM up to the 12C limit of 16 Kbits can be used but only the first 96 bytes from offset 00h to offset 5Fh are required to configure the PCI7x21 PCI7x11 controller Figure 3 3 shows a serial EEPROM application In addition to loading configuration data from an EEPROM the PCI7x21 PCI7x11 12C bus can be used to read and write from other 12C serial devices A system designer can control the 12C bus using the PCI7x21 PCI7x11 controller as bus master by reading and writing PCI configuration registers Setting bit 3 SBDETECT in the serial bus control status register PCI offset B3h see Section 4 50 causes the PCI7x21 PCI7x11 controller to route the SDA and SCL signals to the SDA and SCL terminals respectively The read write data slave address and byte addresses are manipulated by accessing the serial bus data serial bus index and serial bus slave address registers PCI offsets BOh Bih and B2h see Sections 4 47 4 48 and 4 49 respectively EEPROM interface status information is communicated through the serial
352. of the CD2 signal at the PC Card interface Software can use this and CDETECT1 to determine if a PC Card is fully seated in the socket 0 CD2 signal is 1 No PC Card inserted 1 CD2 signal is 0 PC Card at least partially inserted Card detect 1 This bit indicates the status of the CD1 signal at the PC Card interface Software can use this and CDETECT2 to determine if a PC Card is fully seated in the socket 0 CD1 signal is 1 No PC Card inserted 1 CD1 signal is 0 PC Card at least partially inserted Battery voltage detect When a 16 bit memory card is inserted the field indicates the status of the battery voltage detect signals BVD1 BVD2 at the PC Card interface where bit 0 reflects the BVD1 status and bit 1 reflects BVD2 00 Battery is dead 01 Battery is dead 10 Battery is low warning 11 Battery is good When a 16 bit I O card is inserted this field indicates the status of the SPKR bit 1 signal and the STSCHG bit 0 at the PC Card interface In this case the two bits in this field directly reflect the current state of these card outputs 5 3 ExCA Power Control Register This register provides PC Card power control Bit 7 of this register enables the 16 bit outputs on the socket interface and can be used for power management in 16 bit PC Card applications See Table 5 5 for a complete description of the register contents ExCA power control Register ExCA power control Offset CardBus
353. of the twisted pair cable drivers and receivers and for signaling to the remote nodes that there is an active cable connection Each of these pins must be decoupled with a 1 0 uF capacitor to ground Twisted pair cable B differential signal terminals Board trace lengths from each pair of positive and negative differential signal pins must be matched and as short as possible to the external load resistors and to the cable connector For an unused port TPB and TPB must be pulled to ground Crystal oscillator inputs These pins connect to a 24 576 MHz parallel resonant fundamental mode crystal The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used see Section 3 9 2 Crystal Selection An external clock input can be connected to the XI terminal When using an external clock input the XO terminal must be left unconnected and the clock must be supplied before the controller is taken out of reset Refer to Section 3 9 2 for the operating characteristics of the XI terminal 390 kQ series resistor to BUSPOWER if providing power through the 1394 port Pullup resistors if high Can be tied directly to ground if set to low 6 34 kQ 1 resistor between RO and R1 per 1394 specification 1394 termination see reference schematics 1394 termination see reference schematics 1394 termination see reference schematics 1394 termination see reference schematics 1394
354. oller from that node are accepted 19 asynRegResource51 RSC If bit 19 is set to 1 for local bus node number 51 asynchronous requests received by the controller from that node are accepted 8 32 Table 8 27 Asynchronous Request Filter High Register Description Continued BIT FIELD NAME TYPE DESCRIPTION 18 asynReqResource50 RSC If bit 18 is set to 1 for local bus node number 50 asynchronous requests received by the controller from that node are accepted 17 asynReqResource49 RSC If bit 17 is set to 1 for local bus node number 49 asynchronous requests received by the controller from that node are accepted 16 asynReqResource48 RSC If bit 16 is set to 1 for local bus node number 48 asynchronous requests received by the controller from that node are accepted 15 asynReqResource47 RSC If bit 15 is set to 1 for local bus node number 47 asynchronous requests received by the controller from that node are accepted 14 asynReqResource46 RSC If bit 14 is set to 1 for local bus node number 46 asynchronous requests received by the controller from that node are accepted 13 asynReqResource45 RSC If bit 13 is set to 1 for local bus node number 45 asynchronous requests received by the controller from that node are accepted 12 asynReqResource44 RSC If bit 12 is set to 1 for local bus node number 44 asynchronous requests received by the controller from that node are accepted 11 asynReqResource43 RSC If bit 11
355. om card interface PC Cards powered at 5 V or 3 3 V as required All card signals are internally buffered to allow hot insertion and removal without external buffering The PCI7611 controller is register compatible with the Intel 82365SL DF ExCA controller The PCI7611 internal data path logic allows the host to access 8 16 and 32 bit cards using full 32 bit PCI cycles for maximum performance Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting The PCI7611 controller can be programmed to accept posted writes to improve bus utilization Function 2 of the PCI7611 controller is compatible with IEEE Std 1394a 2000 and the latest 1394 Open Host Controller Interface Specification The chip provides the IEEE1394 link and 2 port PHY function and is compatible with data rates of 100 200 and 400 Mbits per second Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies The PCI7611 controller provides physical write posting and a highly tuned physical data path for SBP 2 performance Function 3 of the PCI7611 controller is a PCl based Flash Media controller that supports Memory Stick Memory Stick Pro SmartMedia XD SD and MMC cards This function controls communication with these Flash Media cards through a passive PC Card adapter or through a dedicated Flash Media socket In addition this function includes DMA capabilities for improved Flash Media performance
356. on Register a 12 10 12 17 Capability ID and Next Item Pointer Registers 12 11 12 18 Power Management Capabilities Register 12 12 12 19 Power Management Control and Status Register 12 13 12 20 Power Management Bridge Support Extension Register 12 13 12 21 Power Management Data Register 12 14 12 22 General Control Register 4 101 a 2caccereiseseesasecseeseauses 12 14 12 23 Subsystem Access Register aaa 12 15 12 24 Diagnostic Register 1 24 ak KAKA KA PRA KAG AA KAG ADA eri 12 15 12 25 Slot 0 3 3 V Maximum Current Register 12 16 12 26 Slot 1 3 3 V Maximum Current Register 12 16 12 27 Slot 2 3 3 V Maximum Current Register 12 16 12 28 Slot 3 3 3 V Maximum Current Register 12 17 12 29 Slot 4 3 3 V Maximum Current Register 12 17 12 30 Slot 5 3 3 V Maximum Current Register 12 17 13 Smart Card Controller Programming Model 13 1 13 1 Vendor ID Register a 0vircecucey NANA ERE A AWAKE L INE weees vets 13 2 13 2 Device ID Register 4 mwaa ma N ANAK KA ten tkdered beaten Sun 13 2 133 Command Register so icacivenceuteagesehee ey mb anG BA cae KG PA esx 13 3 13 SR Uk AA 13 4 13 5 Class Code and Revision ID Register oo ooooooo 13 5 13 6 Latency Timer and Class Cache Li
357. ontrol Register This register controls both PC Card sockets and is not duplicated for each socket The host interrupt mode bits in this register are retained for 82365SL DF compatibility See Table 5 15 for a complete description of the register contents Register Offset Type Default RSVD INTMODEB RW INTMODEA RW 2t IFCMODE RW BIT 7 5 4 Ot PWRDWN RW ExCA global control CardBus Socket Address 81Eh Card A ExCA Offset 1Eh Card B ExCA Offset 5Eh Read only Read Write Table 5 15 ExCA Global Control Register Description FUNCTION These bits return Os when read Writes have no effect Level edge interrupt mode select card B This bit selects the signaling mode for the PCI7x21 PCI7x11 host interrupt for card B interrupts This bit is encoded as 0 Host interrupt is edge mode default 1 Host interrupt is level mode Level edge interrupt mode select card A This bit selects the signaling mode for the PCI7x21 PCI7x11 host interrupt for card A interrupts This bit is encoded as 0 Host interrupt is edge mode default 1 Host interrupt is level mode Interrupt flag clear mode select This bit selects the interrupt flag clear mechanism for the flags in the ExCA card status change register This bit is encoded as 0 Interrupt flags cleared by read of CSC register default 1 Interrupt flags cleared by explicit writeback of 1 Card status change level edge mode select This bit
358. ontroller can be programmed to accept posted writes to improve bus utilization Function 2 of the PCI7621 controller is compatible with IEEE Std 1394a 2000 and the latest 1394 Open Host Controller Interface Specification The chip provides the IEEE1394 link and 2 port PHY function and is compatible with data rates of 100 200 and 400 Mbits per second Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies The PCI7621 controller provides physical write posting and a highly tuned physical data path for SBP 2 performance Function 3 of the PCI7621 controller is a PCl based Flash Media controller that supports Memory Stick Memory Stick Pro SmartMedia XD SD and MMC cards This function controls communication with these Flash Media cards through a passive PC Card adapter or through a dedicated Flash Media socket In addition this function includes DMA capabilities for improved Flash Media performance Function 4 of the PCI7621 controller is a PCI based SD host controller that supports MMC SD and SDIO cards This function controls communication with these Flash Media cards through a passive PC Card adapter or through a dedicated Flash Media socket In addition this function is compliant with the SD Host Controller Standard Specification and includes both DMA capabilities and support for SD suspend resume Function 5 of the PCI7621 controller is a PCl based Smart Card controller used for communication with Smart Cards in
359. ontroller changes this bit only on a system hardware or software reset Reserved Bits 14 and 13 return Os when read o RSVD wake active pol n ca Software sets bit 12 to 1 to cause the PCI7x21 PCI7x11 controller to continue or resume descriptor processing The PCI7x21 PCI7x11 controller clears this bit on every descriptor fetch The PCI7x21 PCI7x11 controller sets bit 11 to 1 when it encounters a fatal error and clears the bit when software clears bit 15 run The PCI7x21 PCI7x11 controller sets bit 10 to 1 when it is processing descriptors Reserved Bits 9 and 8 return Os when read T pr de N al 8 42 RSVD This field indicates the speed at which the packet was received 000 100M bits sec 001 200M bits sec 010 400M bits sec All other values are reserved For bufferFill mode possible values are ack_complete evt_descriptor_read evt_data_write and evt_unknown Packets with data errors either dataLength mismatches or dataCRC errors and packets for which a FIFO overrun occurred are backed out For packet per buffer mode possible values are ack_complete ack_data_error evt_long_packet evt_overrun evt_descriptor_read evt_data_write and evt_unknown 8 45 Isochronous Receive Context Command Pointer Register The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the PCI7x21 PCI7x11 controller accesses when so
360. oper power may not yet be stable This bit is cleared when the DELAYDOWN power down delay has expired 0 Power down delay has expired default 1 Power down stream sent to switch Power might not be stable Interrogation in progress When set this bit indicates an interrogation is in progress and clears when INTERROGATE the interrogation completes This bit is socket dependent 0 Interrogation not in progress default 1 Interrogation in progress R Reserved This bit returns 0 when read Power savings mode enable When this bit is set the PCI7x21 PCI7x11 controller consumes less power with no performance loss This bit is shared between the two PCI7x21 PCI7x11 CardBus 6 t PWRSAVINGS RW functions 0 Power savings mode disabled 1 Power savings mode enabled default Subsystem ID and subsystem vendor ID ExCA ID and revision register read write enable This bit also controls read write for the function 3 subsystem ID register 0 Registers are read write 1 Registers are read only default MRBURSTUP SOCACTIVE 5 SUBSYSRW RW t One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled If PME is not enabled then this bit is cleared by the assertion of PRST or GRST These bits are cleared only by the assertion of GRST These bits are global in nature and must be accessed only through function 0 Table 4 8 System Conirol Re
361. or PCI1130 compatibility RI OUT is enabled through this register and the enable bit is shared between functions O and 1 See Table 4 16 for a complete description of the register contents The RI_OUT signal is enabled through this register and the enable bit is shared between functions 0 and 1 Register Card conirol Offset 91h Type Read only Read Write Default 00h RIENB RW novo AW AUD2MUX RW SPKROUTEN RW Table 4 16 Card Control Register Description FUNCTION Ring indicate enable When this bit is 1 the RI OUT output is enabled This bit defaults to O These bits are reserved Do not change the value of these bits CardBus audio to MFUNC When this bit is set the CAUDIO CardBus signal must be routed through an MFUNC terminal If this bit is set for both functions then function 0 is routed 0 CAUDIO set to CAUDPWM on MFUNC terminal default 1 CAUDIO is not routed When bit 1 is set the SPKR terminal from the PC Card is enabled and is routed to tthe SPKROUT terminal The SPKR signal from socket 0 is XORed with the SPKR signal from socket 1 and sent to SPKROUT The SPKROUT terminal drives data only when the SPKROUTEN bit of either function is set This bit is encoded as 0 SPKR to SPKROUT not enabled default 1 SPKR to SPKROUT enabled i Interrupt flag This bit is the interrupt flag for 16 bit O PC Cards and for CardBus cards This bit is set when a functional interrupt is signaled fro
362. ot set this bit if the PCI7x21 PCI7x11 node is the 1394 bus manager 28 24 RSVD R Reserved Bits 28 24 return Os when read programPhyEnable Bit 23 informs upper level software that lower level software has consistently configured the IEEE 1394a 2000 enhancements in the link and PHY layers When this bit is 1 generic software such as the OHCI driver is responsible for configuring IEEE 1394a 2000 enhancements in the PHY layer and bit 22 aPhyEnhanceEnable When this bit is 0 the generic software may not modify the IEEE 1394a 2000 enhancements in the PHY layer and cannot interpret the setting of bit 22 aPhyEnhanceEnable This bit is initialized from serial EEPROM This bit defaults to 1 This bit is cleared only by the assertion of GRST Table 8 11 Host Controller Control Register Description Continued o T FIELD NAME TYPE aPhyEnhanceEnable RSC NI N 21 20 RSVD R RSC postedWriteEnable linkEnable SoftReset RSCU DESCRIPTION When bits 23 programPhyEnable and 17 linkEnable are 1 the OHCI driver can set bit 22 to 1 to use all IEEE 1394a 2000 enhancements When bit 23 programPhyEnable is cleared to 0 the software does not change PHY enhancements or this bit Reserved Bits 21 and 20 return Os when read Bit 19 controls the link power status Software must set this bit to 1 to permit the link PHY communication A 0 prevents link PHY communication The OHCI link is divided into two clock domain
363. oted by in Table 4 2 Any bit followed by a 1 is not cleared by the assertion of PRST see CardBus Bridge Power Management Section 3 8 10 for more details if PME is enabled PCI offset A4h bit 8 In this case these bits are cleared only by GRST If PME is not enabled then these bits are cleared by GRST or PRST These bits are sometimes referred to as PME context bits and are implemented to allow PME context to be preserved during the transition from D3p or D3colg to DO If a bit is followed by a then this bit is cleared only by GRST in all cases not conditional on PME being enabled These bits are intended to maintain device context such as interrupt routing and MFUNC programming during warm resets A bit description table typically included when the register contains bits of more than one type or purpose indicates bit field names a detailed field description and field access tags which appear in the type column Table 4 1 describes the field access tags Table 4 1 Bit Field Access Tag Descriptions Field can be read by software Field can be written by software to any value Field can be set by a write of 1 Writes of 0 have no effect Field can be cleared by a write of 1 Writes of 0 have no effect Update Field can be autonomously updated by the PCI7x21 PCI7x11 controller 4 1 PCI Configuration Register Map Functions 0 and 1 The PCI7x21 PCI7x11 is a multifunction PCI device and the PC Card controller is int
364. pable power switch TPS2228 is used default 1 A 12 V capable power switch TPS2226 is used Dedicated flash media interface selection This field controls the mode of the dedicated flash media interface 00 Flash media interface configured as SD MMC socket MS socket default 01 Flash media interface configured as 2 in 1 SD MMC MS socket 10 Flash media interface configured as 3 in 1 SD MMC MS SM XD socket 11 Reserved When this bit is set the Smart Card function is completely nonaccessible and nonfunctional When this bit is set the SD host controller function is completely nonaccessible and nonfunctional When this bit is set the flash media function is completely nonaccessible and nonfunctional When this bit is set CardBus socket B function 1 is completely nonaccessible and nonfunctional When this bit is set the OHCI 1394 controller function is completely nonaccessible and nonfunctional DISABLE OHCI Dedicated Smart Card power control This bit determines how power to the dedicated Smart Card socket is controlled 0 Controlled through the SC PWR CTRL terminal default 1 Controlled through the VPP voltage of socket B of the CardBus power switch the design ot DED_SC_PWR CTRL must ensure that this mode can only be set when CardBus socket B is disabled Controls top level PCI arbitration 00 1394 OHCI priority 10 Flash media SD host priority 01 CardBus priority 11 Fair round robin 1 0 ARB_CTRL
365. pointer Offset 20Ch 16 n Type Read only Default XXXX XXXXh 8 44 Isochronous Receive Context Control Register The isochronous receive context control set clear register controls options state and status for the isochronous receive DMA contexts The n value in the following register addresses indicates the context number n 0 1 2 3 See Table 8 34 for a complete description of the register contents er 80 29 28 27 26 25 24 2 2 20 w w 0w Name Isochronous receive context control ye aso asc ascu aso aso A n n rR IR ALALA LALA LA peet A A o o jofojojpojojJpo Bit 15 14 13 12 10 9 8 7 6 Name Isochronous receive context control pe escu A R ASU RU ao a a AU AU AU peras o o o x o o lolo x xxxi xixixi Register Isochronous receive context control Offset 400h 32 n set register 404h 32 n clear register Type Read Set Clear Update Read Set Clear Read Set Update Read Update Read only FIELD NAME TYPE DESCRIPTION multiChanMode is set to 1 then this bit must also be set to 1 The value of this bit must not be packet header seen by the link layer The end of the packet is marked with a xferStatus in the first Default XX00 XOXXh bufferFill When bit 31 is set to 1 received packets are placed back to back to completely fill each receive changed while bit 10 active or bit 15 run is set to 1 doublet and a 16 bit timeStamp indicating
366. pon which one of eight pages numbered Oh through 7h is currently selected The selected page is set in base register 7h 10 1 Base Registers Table 10 1 shows the configuration of the base registers and Table 10 2 shows the corresponding field descriptions The base register field definitions are unaffected by the selected page number A reserved register or register field marked as Reserved in the following register configuration tables is read as 0 but is subject to future usage All registers in address pages 2 through 6 are reserved Table 10 1 Base Register Configuration BIT POSITION RON MIN gt TA AI EI oor ao EA Y Reserved Table 10 2 Base Register Field Descriptions FIELD SIZE TYPE DESCRIPTION Physical ID This field contains the physical address ID of this node determined during self ID The physical ID is invalid after a bus reset until self ID has completed as indicated by an unsolicited register 0 status transfer 1 Root This bit indicates that this node is the root node The R bit is cleared to O by bus reset and is set to 1 during tree ID if this node becomes root CPS 1 Cable power status This bit indicates the state of the CPS input terminal The CPS terminal is normally tied to serial bus cable power through a 400 kQ resistor A 0 in this bit indicates that the cable power voltage has dropped below its threshold for ensured reliable operation RHB 1 R W Root holdoff bit This bit instructs the PHY lay
367. r switch interface of the PCI7x21 PCI7x11 controller is a 3 pin serial interface This 3 pin interface is implemented such that the PCI7x21 PCI7x11 controller can connect to both the TPS2226 and TPS2228 power switches Bit 10 12V_SW_SEL in the general control register PCI offset 86h see Section 4 31 selects the power switch that is implemented The PCI7x21 PCI7x11 controller defaults to use the control logic for the TPS2228 power switch See Table 3 3 and Table 3 6 below for the power switch control logic Table 3 3 TPS2228 Control Logic xVPP VCORE AVPP VCORE CONTROL SIGNALS OUTPUT BVPP VCORE CONTROL SIGNALS OUTPUT pasion Do pi oo Y AVPPIVCORE panon DERA A AVCC CONTROL SIGNALS OUTPUT BVCC CONTROL SIGNALS OUTPUT son A EA ACT oe br veve AVPP CONTROL SIGNALS OUTPUT BVPP CONTROL SIGNALS OUTPUT pasion vo Dr oo WAP fusion bs os om vee AVCC CONTROL SIGNALS OUTPUT BVCC CONTROL SIGNALS OUTPUT V_AVCC V BVCC ason os a son oe or 3 5 6 Internal Ring Oscillator The internal ring oscillator provides an internal clock source for the PCI7x21 PC17x11 controller so that neither the PCI clock nor an external clock is required in order for the PCI7x21 PCI7x11 controller to power down a socket or interrogate a PC Card This internal oscillator operating nominally at 16 kHz is always enabled 3 8 3 5 7 Integrated Pullup Resistors for PC Card Interface The PC Card Standard requires pullup resistors on various terminal
368. r the PC Card This bit is encoded as 7 IOWIN1 EN RW 0 I O window 1 disabled default 1 1 0 window 1 enabled 1 0 window 0 enable Bit 6 enables disables I O window 0 for the PC Card This bit is encoded as IOWINOEN RW 0 I O window 0 disabled default 1 I O window 0 enabled RSVD OR Reserved Bit 5 returns 0 when read Memory window 4 enable Bit 4 enables disables memory window 4 for the PC Card This bit is encoded as 0 Memory window 4 disabled default 1 Memory window 4 enabled MEMWIN4EN RW MEMWIN3EN Memory window 3 enable Bit 3 enables disables memory window 3 for the PC Card This bit is encoded as 0 Memory window 3 disabled default 1 Memory window 3 enabled Memory window 1 enable Bit 1 enables disables memory window 1 for the PC Card This bit is encoded as 0 Memory window 1 disabled default 1 Memory window 1 enabled MEMWIN1EN MEMWINOEN Memory window 0 enable Bit 0 enables disables memory window O for the PC Card This bit is encoded as 0 Memory window 0 disabled default 1 Memory window 0 enabled Memory window 2 enable Bit 2 enables disables memory window 2 for the PC Card This bit is encoded as vee RW 0 Memory window 2 disabled default 1 Memory window 2 enabled O 5 8 ExCA I O Window Control Register The ExCA I O window control register contains parameters related to I O window sizing and cycle timing See Table 5 10 for a complete description of th
369. r the set register or the clear register always return the contents of the isochronous receive interrupt mask register In all cases the enables for each interrupt event align with the isochronous receive interrupt event register bits detailed in Table 8 18 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Isochronous receive interrupt mask Name A E ____ o Po foto ftoftoftoftoftoftTotoftoftoftotofolfoa pepe pete te tee bepepe pepe rere tet Isochronous receive interrupt mask ane RSC RSC RSC RSC Default Register Isochronous receive interrupt mask Offset A8h set register ACh clear register Type Read Set Clear Read only Default 0000 000Xh 8 27 Initial Bandwidth Available Register The initial bandwidth available register value is loaded into the corresponding bus management CSR register on a system hardware or software reset See Table 8 19 for a complete description of the register contents 27 26 25 24 23 22 21 20 19 a8 17 16 Initial bandwidth available Name m aa A Lo o ls Fo o bo bo lo o bolo po lolo Ca AA Name habaan aako me alala AW aw eun o olo o o 1 ofo 0 0 1 1 Register Initial bandwidth available Offset Boh Type Read only Read Write Default 0000 1333h Table 8 19 Initial Bandwidth Available Register Description BIT FIELD NAME TYPE DESCRIPTION 31 13 RSVD R Reserved Bits 31
370. ration header where the power management register block resides Since the PCI power management registers begin at 80h this read only register is hardwired to 80h Capabilities pointer Name mo R R R R R R R R petan 1 o o0 o o0 o o0 o Register Capabilities pointer Offset 34h Type Read only Default 80h 12 12 Interrupt Line Register The interrupt line register is programmed by the system and indicates to the software which interrupt line the SD host controller has assigned to it The default value of this register is FFh indicating that an interrupt line has not yet been assigned to the function Bit Name Type Default Register Interrupt line Offset 3Ch Type Read Write Default FFh 12 8 12 13 Interrupt Pin Register This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 12 8 indicating that the SD host controller uses an interrupt If one of the USE_INTx terminals is asserted the interrupt select bits are ignored and this register returns the interrupt value for the highest priority USE_INTx terminal that is asserted If bit 28 the tie all bit TIEALL in the system control register PCI offset 80h see Section 4 29 is set to 1 then the PCI7x21 PC17x11 controller asserts the USE INTA input to the SD host controller core If bit 28 TIEALL in the system control register PCI offset 80h see Section
371. re from external signals The core power supply is 1 5 V and is independent of the clamping voltages For example PCI signaling can be either 3 3 V or 5 V and the PCI7x21 PCI7x11 controller must reliably accommodate both voltage levels This is accomplished by using a 3 3 V I O buffer that is 5 V tolerant with the applicable clamping voltage applied If a system designer desires a 5 V PCI bus then Vccp can be connected to a 5 V power supply 3 4 Peripheral Component Interconnect PCI Interface The PCI7x21 PCI7x11 controller is fully compliant with the PCI Local Bus Specification The PCI7x21 PCI7x11 controller provides all required signals for PCI master or slave operation and may operate in either a 5 V or 3 3 V signaling environment by connecting the Vccp terminals to the desired voltage level In addition to the mandatory PCI signals the PCI7x21 PCI7x11 controller provides the optional interrupt signals INTA INTB INTC and INTD 3 4 1 1394 PCI Bus Master As a bus master the 1394 function of the PCI7x21 PCI7x11 controller supports the memory commands specified in Table 3 1 The PCI master supports the memory read memory read line and memory read multiple commands The read command usage for read transactions of greater than two data phases are determined by the selection in bits 9 8 MR ENHANCE field of the PCI miscellaneous configuration register refer to Section 7 23 for details For read transactions of one or two data phase
372. re part of the loop generate a configuration timeout interrupt All other nodes instead time out waiting for the tree ID and or self ID process to complete and then generate a state time out interrupt and bus reset Pwr_fail 1 R W Cable power failure detect This bit is set to 1 whenever the CPS input transitions from high to low indicating that cable power may be too low for reliable operation This bit is cleared to 0 by system hardware reset or by writing a 1 to this register bit Timeout 1 R W State time out interrupt This bit indicates that a state time out has occurred which also causes a bus reset to occur This bit is cleared to O by system hardware reset or by writing a 1 to this register bit Port_event 1 R W Port event detect This bit is set to 1 upon a change in the bias unless disabled connected disabled or fault bits for any port for which the port interrupt enable Int enable bit is set Additionally if the Watchdog bit is set the Port event bit is set to 1 at the start of resume operations on any port This bit is cleared to O by system hardware reset or by writing a 1 to this register bit Enab accel 1 R W Enable accelerated arbitration This bit enables the PHY layer to perform the various arbitration acceleration enhancements defined in IEEE Std 1394a 2000 ACK accelerated arbitration asynchronous fly by concatenation and isochronous fly by concatenation This bit is cleared to O by system hardware reset and is
373. red for certain operating systems This read only register is initialized through the EEPROM and can be written through the subsystem access register at PCI offset 50h see Section 11 All bits in this register are reset by GRST only COMICO oo s e e o o eT are Default Register Subsystem identification Offset 2Eh Type Read Update Default 0000h 11 11 Capabilities Pointer Register The power management capabilities pointer register provides a pointer into the PCI configuration header where the power management register block resides Since the PCI power management registers begin at 44h this read only register is hardwired to 44h Ti ET POS par il a Name Capabilities pointer mwe R R R R R R na R Detaut o 1 o0 o o0 1 0 o Register Capabilities pointer Offset 34h Type Read only Default 44h 11 7 11 12 Interrupt Line Register The interrupt line register is programmed by the system and indicates to the software which interrupt line the flash media interface has assigned to it The default value of this register is FFh indicating that an interrupt line has not yet been assigned to the function Register Interrupt line Offset 3Ch Type Read Write Default FFh 11 13 Interrupt Pin Register This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 11 8 indicating that the flash media inte
374. requirements When bit 15 PME D3COLD is cleared this field returns 000b otherwise it returns 001b 000b Self powered 001b 55 mA 3 3 VAyx maximum current required PME D3COLD AUX CURRENT Device specific initialization This bit returns 0 when read indicating that the PCI7x21 PCI7x11 controller does not require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it Reserved Bit 4 returns 0 when read PME clock This bit returns 0 when read indicating that no host bus clock is required for the PCI7x21 PCI7x11 controller to generate PME PME_CLK Power management version This field returns 010b when read indicating that the PCI7x21 PCI7x11 PM_VERSION controller is compatible with the registers described in the PC Bus Power Management Interface Specification Revision 1 1 7 20 Power Management Control and Status Register The power management control and status register implements the control and status of the PCI power management function This register is not affected by the internally generated reset caused by the transition from the D3p to DO state See Table 7 17 for a complete description of the register contents Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Power management control and status Name Powermanagement control andstatus Type Rwc rR r R R A AR Aw a R R R R R Aw Rw Register Power ma
375. rface uses an interrupt If one of the USE_INTx terminals is asserted the interrupt select bits are ignored and this register returns the interrupt value for the highest priority USE_INTx terminal that is asserted If bit 28 the tie all bit TIEALL in the system control register PCI offset 80h see Section 4 29 is set to 1 then the PCI7x21 PCI7x11 controller asserts the USE INTA input to the flash media controller core If bit 28 TIEALL in the system control register PCI offset 80h see Section 4 29 is set to 0 then none of the USE_INTx inputs are asserted and the interrupt for the flash media function is selected by the INT_SEL bits in the flash media general control register ee 7 s la 8s lg ku Cn T Default 0 0 0 0 0 X X X Register Interrupt pin Offset 3Dh Type Read only Default OXh Table 11 8 PCI Interrupt Pin Register 11 8 11 14 Minimum Grant Register The minimum grant register contains the minimum grant value for the flash media controller core Minimum grant Name esn o o o o poi Register Minimum grant Offset 3Eh Type Read Update Default 07h Table 11 9 Minimum Grant Register Description FIELD NAME TYPE DESCRIPTION Minimum grant The contents of this field may be used by host BIOS to assign a latency timer register value to the flash media controller The default for this register indicates that the flash media controller may need 7 0 MIN GNT RU to sust
376. rminals for D3cp d wake up support then BIOS must write a 0 to this bit 14 11 Bit 14 contains the value 1 to indicate that the PME signal can be asserted from the D3hot state Bit 13 contains the value 1 to indicate that the PME signal can be asserted from the D2 state D Bit 12 contains the value 1 to indicate that the PME signal can be asserted from the D1 state Bit 11 contains the value 1 to indicate that the PME signal can be asserted from the DO state o or suon es asw Device specific initialization This bit returns 0 when read Auxiliary power source This bit is meaningful only if bit 15 D3 4 supporting PME is set When this bit is set it indicates that support for PME in D3cojg requires auxiliary power supplied by the system by way of a proprietary delivery vehicle 4 AUX_PWR KANAN de f o m A 0 zero in this bit field indicates that the function supplies its own auxiliary power source If the function does not support PME while in the D3gojg state bit 15 0 then this field must always return This bit returns a 1 when read indicating that the function supports the D2 device power state This bit returns a 1 when read indicating that the function supports the D1 device power state Reserved These bits return 000b when read J D D R 0 When this bit is 1 it indicates that the function relies on the presence of the PCI clock for PME operation 3 PMECLK R When this bit is 0 it indicates that
377. roller terminates the transaction when its GNT is deasserted w 7 ef s TA TF TE 9 COI a Register Latency timer Offset ODh Type Read Write Default 00h 4 10 Header Type Register The header type register returns 82h when read indicating that the PCI7x21 PCI7x11 functions O and 1 configuration spaces adhere to the CardBus bridge PCI header The CardBus bridge PCI header ranges from PCI registers 00h 7Fh and 80h FFh is user definable extension registers 7 Header type Name mwe rR rR R R R R R R pemn o0 o o o o 1 o Register Header type Offset OEh Functions 0 1 Type Read only Default 82h 4 11 BIST Register Because the PCI7x21 PCI7x11 controller does not support a built in self test BIST this register returns the value of 00h when read Register BIST Offset OFh Functions 0 1 Type Read only Default 00h 4 12 CardBus Socket Registers ExCA Base Address Register This register is programmed with a base address referencing the CardBus socket registers and the memory mapped ExCA register set Bits 31 12 are read write and allow the base address to be located anywhere in the 32 bit PCI memory address space on a 4 Kbyte boundary Bits 11 0 are read only returning Os when read When software writes all 1s to this register the value read back is FFFF FOooh indicating that at least 4K bytes of memory address space are required The CardBus registers s
378. rrent This input comes from the Smart LVCI1 Card power switch Power switch or SC PWR CTRL LO5 Smart Card power control for the Smart Card socket LVCO1 FENIG turmen power to FM socket Smart Card function code The controller does not support SC_FCB synchronous Smart Cards as specified in ISO IEC 7816 10 PCII5 PCIO5 SW3 and this terminal is in a high impedance state Smart Card general purpose I O terminals These signals can be controlled by firmware and are used as control TILI TTLO2 signals for an external Smart Card interface chip or level shifter SC_RFU Smart Card reserved This terminal is in a high impedance PCIIS PCIOS state Smart Card This signal starts and stops the Smart Card SC_RST K03 reset sequence The controller asserts this reset when PCIO6 requested by the host T These terminals are reserved for the PCI7421 and PCI7411 controllers 2 29 2 30 3 Feature Protocol Descriptions The following sections give an overview of the PCI7x21 PCI7x11 controller Figure 3 1 shows the connections to the PCI7x21 PCI7x11 controller The PCI interface includes all address data and control signals for PCI protocol The interrupt interface includes terminals for parallel PCI parallel ISA and serialized PCI and ISA signaling L PCI Bus SD MMC MS MSPRO PCI7x21 SM xD PC17x11 PC PC Card Card UltraMedia UltraMedia Card Card Figure 3 1 PCI7x21 PCI7x11 System Block Diagram
379. rrupt connections set by INTRTIE and TIEALL are communicated to host software through this standard register interface This read only register is described for all PCI7x21 PCI7x11 functions in Table 4 6 PCI function 0 Bito 7 06 5 4a 3 2 1 o Name Interrupt pin PCI function O Default 0 0 0 0 0 0 1 PCI function 1 PCI function 3 ee 7 s TUT 3s 2 7 CON ET ye A A A A A aA A A Deen o lo lolo x x x _ PCI function 4 7 ee p r J e J o 3s 2 47 3 name ETT tye a A A a A A aA A Postea o 0 0 x x PCI function 5 Default 4 14 Register Interrupt pin Offset 3Dh Type Read only Default 01h function 0 02h function 1 03h function 2 04h function 3 04h function 4 04h function 5 Table 4 6 Interrupt Pin Register Cross Reference INTRTIE BIT TIEALL BIT INTPIN INTPIN INTPIN INTPIN INTPIN INTPIN BIT 29 BIT 28 FUNCTION 0 FUNCTION 1 FUNCTION 2 FUNCTION 3 FUNCTION 4 FUNCTION 5 OFFSET 80h OFFSET 80h CARDBUS CARDBUS 1394 OHCI FLASH MEDIA SD HOST SMART CARD Determined by Determined by Determined by bits 6 5 bits 6 5 bits 6 5 INT_SEL inthe INT_SEL inthe INT_SEL in the flash media SD host general Smart Card general control control register general control register see see register see Section 11 21 Section 12 22 Section 13 22
380. rupts on the INTx signals INT DISABLE 0 INTx assertion is enabled default 1 INTx assertion is disabled 9 FBB ENB R Fast back to back enable The PCI7x21 PCI7x11 controller does not generate fast back to back transactions therefore bit 9 returns O when read 8 SERR ENB RW SERR enable When bit 8 is set to 1 the PCI7x21 PCI7x11 SERR driver is enabled SERR can be asserted after detecting an address parity error on the PCI bus The default value for this bit is O 7 RSVD R Reserved Bit 7 returns 0 when read 6 PERR ENB RW Parity error enable When bit 6 is set to 1 the PCI7x21 PCI7x11 controller is enabled to drive PERR response to parity errors through the PERR signal The default value for this bit is 0 5 VGA ENB R VGA palette snoop enable The PCI7x21 PCI7x11 controller does not feature VGA palette snooping ag therefore bit 5 returns O when read Memory write and invalidate enable When bit 4 is set to 1 the PCI7x21 PCI7x11 controller is enabled 4 MWI ENB RW to generate MWI PCI bus commands If this bit is cleared then the PCI7x21 PCI7x11 controller generates memory write commands instead The default value for this bit is O 3 SPECIAL R Special cycle enable The PCI7x21 PCI7x11 function does not respond to special cycle transactions therefore bit 3 returns 0 when read Bus master enable When bit 2 is set to 1 the PCI7x21 PCI7x11 controller is enabled to initiate cycles MASTER ENB RW on the PCI bus The default value for thi
381. s PCLK and PHY_SCLK If software tries to access any register in the PHY SCLK domain while the PHY SCLK is disabled then a target abort is issued by the link This problem can be avoided by setting bit 4 DIS TGT ABT to 1 in the PCI miscellaneous configuration register at offset FOh in the PCI configuration space see Section 7 23 This allows the link to respond to these types of request by returning all Fs hex OHCI registers at offsets DCh FOh and 100h 11Ch are in the PHY SCLK domain After setting LPS software must wait approximately 10 ms before attempting to access any of the OHCI registers This gives the PHY SCLK time to stabilize Bit 18 enables 1 or disables 0 posted writes Software changes this bit only when bit 17 linkEnable is O Bit 17 is cleared to O by either a system hardware or software reset Software must set this bit to 1 when the system is ready to begin operation and then force a bus reset This bit is necessary to keep other nodes from sending transactions before the local system is ready When this bit is cleared the PCI7x21 PCI7x11 controller is logically and immediately disconnected from the 1394 bus no packets are received or processed nor are packets transmitted When bit 16 is set to 1 all PCI7x21 PCI7x11 states are reset all FIFOs are flushed and all OHCI registers are set to their system hardware reset values unless otherwise specified PCI registers are not affected by this bit This bit rem
382. s a memory read command is used Table 3 1 PCI Bus Support COMMAND 0110 DMA read from memory Memory read line 1110 DMA read from memory Memory read multiple 1100 DMA read from memory Memory write and invalidate 1111 DMA write to memory 3 4 2 Device Resets The following are the requirements for proper reset of the PCI7x21 PCI7x11 controller 1 GRST and PRST must both be asserted at power on 2 GRST must be asserted for at least 2 ms at power on 3 PRST must be deasserted either at the same time or after GRST is asserted 4 PCLK must be stable for 100 us before PRST is deasserted NAM K gt 2ms X 50ns ab INV vec PRET PCLK K gt 100 us A Figure 3 3 PCI Reset Requirement 3 4 3 Serial EEPROM I2C Bus The PCI7x21 PCI7x11 controller offers many choices for modes of operation and these choices are selected by programming several configuration registers For system board applications these registers are normally programmed through the BIOS routine For add in card and docking station port replicator applications the PCI7x21 PCI7x11 controller provides a two wire inter integrated circuit IIC or 12C serial bus for use with an external serial EEPROM The PCI7x21 PCI7x11 controller is always the bus master and the EEPROM is always the slave Either device can drive the bus low but neither device drives the bus high The high level is achieved through the use
383. s Register The power management capabilities register contains information on the capabilities of the PC Card function related to power management Both PCI7x21 PCI7x11 CardBus bridge functions support DO D1 D2 and D3 power states Default register value is FE12h for operation in accordance with PC Bus Power Management Interface Specification revision 1 1 See Table 4 19 for a complete description of the register contents is ars 2 noo e 765937211 o Power management capabilities Name Power management capabilities Type RW R R R R R R R R R R R R R R R pean PA a 4 p4 LA la jew lee o 4 lo o pa Register Power management capabilities Offset A2h Functions 0 1 Type Read only Read Write Default FE12h Table 4 19 Power Management Capabilities Register Description SIGNAL TYPE FUNCTION This 5 bit field indicates the power states from which the PCI7x21 PC17x11 controller functions can assert PME A 0 for any bit indicates that the function cannot assert the PME signal while in that power state These 5 bits return 11111b when read Each of these bits is described below 154 RW Bit 15 defaults to a 1 indicating the PME signal can be asserted from the D3 ojq state This bit is read write because wake up support from D3 ojiq is contingent on the system providing an auxiliary power source PME support to the Vcc terminals If the system designer chooses not to provide an auxiliary power source to the VCC te
384. s bit is 0 Memory response enable Setting bit 1 to 1 enables the PCI7x21 PCI7x11 controller to respond to 1 MEMORY_ENB RW memory cycles on the PCI bus This bit must be set to access OHCI registers The default value for this bit is 0 0 I O space enable The PCI7x21 PCI7x11 controller does not implement any l O mapped functionality 10_ENB R therefore bit 0 returns 0 when read 7 4 Status Register The status register provides status over the PCI7x21 PCI7x11 interface to the PCI bus All bit functions adhere to the definitions in the PCI Local Bus Specification as seen in the following bit descriptions See Table 7 3 for a complete description of the register contents Register Status Offset 06h Type Read Clear Update Read only Default 0210h Table 7 3 Status Register Description FIELD NAME TYPE DESCRIPTION 15 PAR_ERR Detected parity error Bit 15 is set to 1 when either an address parity or data parity error is detected SYS_ERR Signaled system error Bit 14 is set to 1 when SERR is enabled and the PCI7x21 PCI7x11 controller MABORT has signaled a system error to the host Received master abort Bit 13 is set to 1 when a cycle initiated by the PCI7x21 PCI7x11 controller on the PCI bus has been terminated by a master abort Received target abort Bit 12 is set to 1 when a cycle initiated by the PCI7x21 PCI7x11 controller on the PCI bus was terminated by a target abort TABORT REC S
385. s bit is set GPE is signaled on GP4_STS events RW GPI3 GPE enable When this bit is set GPE is signaled on GP3 STS events RW GPI2 GPE enable When this bit is set GPE is signaled on GP2 STS events RW GPI1 GPE enable When this bit is set GPE is signaled on GP1 STS events RW GPIO GPE enable When this bit is set GPE is signaled on GPO STS events This bit is cleared only by the assertion of GRST 4 34 General Purpose Input Register The general purpose input register contains the logical value of the data input to the GPI terminals See Table 4 12 for a complete description of the register contents General purpose input Register General purpose input Offset 8Ah Type Read Update Read only Default XXh Table 4 12 General Purpose Input Register Description BIT SIGNAL TYPE FUNCTION 7 5 RSVD R Reserved These bits return Os when read Writes have no effect GP14 DATA RU GPI4 data input This bit represents the logical value of the data input from GPI4 GPI13 DATA RU GPI3 data input This bit represents the logical value of the data input from GP13 GPI2 DATA RU GPI2 data input This bit represents the logical value of the data input from GPI2 GPI1 DATA RU GPI1 data input This bit represents the logical value of the data input from GPI1 0 GPI0 DATA RU GPIO data input This bit represents the logical value of the data input from GPIO 4 24 4 35 General Purpose Output Register The ge
386. s not set when an interrupt condition exists and signaling of that event is not enabled GE CAPLIST a w IN oa o NI o o 2 0 RSVD Reserved Bits 3 0 return Os when read 11 5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class subclass and programming interface of the function The base class is 01h identifying the controller as a mass storage controller The subclass is 80h identifying the function as other mass storage controller and the programming interface is 00h Furthermore the TI chip revision is indicated in the least significant byte 00h See Table 11 4 for a complete description of the register contents 27 26 25 24 23 22 21 20 19 18 17 16 Class code and revision ID Name T T TT me A A ATA A A A A A A A TA TA A A A Poeta o o o o o lo lo lito o Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH T7 T me lalalala a R R R R x A ALALA AA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default 0 Register Class code and revision ID Offset 08h Type Read only Default 0180 0000h Table 11 4 Class Code and Revision ID Register Description BIT FIELD NAME TYPE DESCRIPTION 31 24 BASECLASS R Base class This field returns 01h when read which classifies the function as a mass storage controller 23 16 SUBCLASS R Subclass This field returns 80h when read which specifically classifies the function as o
387. s to support both CardBus and 16 bit PC Card configurations The PCI7x21 PCI7x11 controller has integrated all of these pullup resistors and requires no additional external components The I O buffer on the BVD1 STSCHG CSTSCHG terminal has the capability to switch to an internal pullup resistor when a 16 bit PC Card is inserted or switch to an internal pulldown resistor when a CardBus card is inserted This prevents inadvertent CSTSCHG events The pullup resistor requirements for the various UltraMedia interfaces are either included in the UltraMedia cards or the UltraMedia adapter or are part of the existing PCMCIA architecture The PCI7x21 PCI7x11 controller does not require any additional components for UltraMedia support 3 5 8 SPKROUT and CAUDPWM Usage The SPKROUT terminal carries the digital audio signal from the PC Card to the system When a 16 bit PC Card is configured for I O mode the BVD2 terminal becomes the SPKR input terminal from the card This terminal in CardBus applications is referred to as CAUDIO SPKR passes a TTL level binary audio signal to the PCI7x21 PCI7x11 controller The CardBus CAUDIO signal also can pass a single amplitude binary waveform as well as a PWM signal The binary audio signal from each PC Card sockets is enabled by bit 1 SPKROUTEN of the card control register PCI offset 91h see Section 4 38 Older controllers support CAUDIO in binary or PWM mode but use the same output terminal SPKROUT Some au
388. scription ea FIELD NAME TYPE DESCRIPTION PME_D3COLD PME support from D3cold This bit can be set to 1 or cleared to O via bit 4 D3 COLD in the general control register at offset 88h in the PCI configuration space see Section 12 22 When this bit is set to 1 it indicates that the SD host controller is capable of generating a PME wake event from D3cold This bit state is dependent upon the SD host controller VAyx implementation and may be configured by using bit 4 D3 COLD in the general control register see Section 12 22 14 11 PME_SUPPORT PME support This 4 bit field indicates the power states from which the SD host controller may assert PME This field returns a value of 1111b by default indicating that PME may be asserted from the D3pgt D2 D1 and DO power states 10 D2 SUPPORT D1 SUPPORT AUX CURRENT RSVD PME CLK D2 support Bit 10 is hardwired to 1 indicating that the SD host controller supports the D2 power state D1 support Bit 9 is hardwired to 1 indicating that the SD host controller supports the D1 power state 3 3 VAUx auxiliary current requirements This requirement is design dependent Device specific initialization This bit returns O when read indicating that the SD host controller does not require special initialization beyond the standard PCI configuration header before a generic class driver is able to use it Reserved Bit 4 returns O when read PME clock This bit returns O when read ind
389. scription Continued FIELD NAME TYPE DESCRIPTION 18 regAccessFail When this bit and bit 18 regAccessFail in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this register access failed interrupt mask enables interrupt generation When this bit and bit 17 busReset in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this bus reset interrupt mask enables interrupt generation selflDcomplete When this bit and bit 16 selflDcomplete in the interrupt event register at OHCI offset 80h 84h see busReset Section 8 21 are set to 1 this self ID complete interrupt mask enables interrupt generation selflDcomplete2 When this bit and bit 15 selflDcomplete2 in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this second self ID complete interrupt mask enables interrupt generation RSVD Reserved Bits 14 10 return Os when read lockRespErr RSC When this bit and bit 9 lockRespErr in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this lock response error interrupt mask enables interrupt generation postedWriteErr RSC When this bit and bit 8 postedWriteErr in the interrupt event register at OHCI offset 80h 84h see Section 8 21 are set to 1 this posted write error interrupt mask enables interrupt generation isochRx RSC When this bit and bit 7 isochRx in the interrupt event register
390. sed for the SD host standard registers is BARO 12 10 12 17 Capability ID and Next Item Pointer Registers The capability ID and next item pointer register identifies the linked list capability item and provides a pointer to the next capability item See Table 12 12 for a complete description of the register contents 7 Capability ID and next item pointer Type Default Register Capability ID and next item pointer Offset 80h Type Read only Default 0001h Table 12 12 Capability ID and Next Item Pointer Registers Description FIELD NAME TYPE DESCRIPTION 15 8 NEXT ITEM Next item pointer The SD host controller supports only one additional capability PCI power management that is communicated to the system through the extended capabilities list therefore this field returns 00h when read CAPABILITY ID Capability identification This field returns 01h when read which is the unique ID assigned by the PCI SIG for PCI power management capability 12 11 12 18 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the SD host controller related to PCI power management See Table 12 13 for a complete description of the register contents eee Power management meme RU Default Register Power management capabilities Offset 82h Type Read Update Read only Default 7E02h Table 12 13 Power Management Capabilities Register De
391. serted in PC Card adapters Utilizing Smart Card technology from Gemplus this function provides compatibility with many different types of Smart Cards 1 1 2 PCI7421 Controller The PCI7421 controller is a five function PCI controller compliant with PCI Local Bus Specification Revision 2 3 Functions 0 and 1 provide the independent PC Card socket controllers compliant with the PC Card Standard Release 8 1 The PCI7421 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards and supports any combination of Smart Card Flash Media 16 bit CardBus and USB custom card interface PC Cards in the two sockets powered at 5 V or 3 3 V as required All card signals are internally buffered to allow hot insertion and removal without external buffering The PCI7421 controller is register compatible with the Intel 82365SL DF ExCA controller The PCI7421 internal data path logic allows the host to access 8 16 and 32 bit cards using full 32 bit PCI cycles for maximum performance Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting The PCI7421 controller can be programmed to accept posted writes to improve bus utilization Function 2 of the PCI7421 controller is compatible with IEEE Std 1394a 2000 and the latest 1394 Open Host Controller Interface Specification The chip provides the IEEE1394 link and 2 port PHY function and is compatible with data
392. set 88h Type Read Write Read only Default 00h Table 12 15 General Control Register BIT FIELD NAME TYPE DESCRIPTION RSVD oR Reserved Bit 7 returns 0 when read 6 5 INT_SEL RW Interrupt select These bits are program the INTPIN register and set which interrupt output is used This field is ignored if one of the USE_INTx terminals is asserted 00 INTA 01 INTB 10 INTC 11 INTD 41 D3 COLD RW D3cold PME support This bit sets and clears the D3gqjg PME support bit in the power management capabilities register RSVD oR Reserved Bits 3 1 return Os when read 01t DMA EN RW DMA enable This bit enables DMA functionality of the SD host controller core When this bit is set the PGMIF field in the class code register returns 01h and the DMA SUPPORT bit in the capabilities register of each SD host socket is set When this bit is O the PGMIF field returns 00h and the DMA SUPPORT bit of each SD host socket is 0 One or more bits in this register are cleared only by the assertion of GRST 12 14 12 23 Subsystem Access Register The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at PCI offsets 2Ch and 2Eh respectively See Table 12 16 for a complete description of the register contents C S T a a Dean o o o o o o o o o o lo lo lololo o halalan lll lali le Subsystem access mame Rw RW RW RW RW RW RW RW RW RW Rw R
393. set by GRST only as 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o0 CIN Ca 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 Default i Register Subsystem identification Offset 2Eh Type Read Update Default 8035h 13 12 Capabilities Pointer Register The power management capabilities pointer register provides a pointer into the PCI configuration header where the power management register block resides Since the PCI power management registers begin at 44h this read only register is hardwired to 44h Capabilities pointer Name mo an J a t5 lht 5 ER R R Detaut o 1 o0 o o0 vs o0 o Register Capabilities pointer Offset 34h Type Read only Default 44h 13 13 Interrupt Line Register The interrupt line register is programmed by the system and indicates to the software which interrupt line the Smart Card interface has assigned to it The default value of this register is FFh indicating that an interrupt line has not yet been assigned to the function Bit Name Type Default Register Interrupt line Offset 3Ch Type Read Write Default FFh 13 14 Interrupt Pin Register This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 13 7 indicating that the Smart Card interface uses an interrupt If one of the USE_INTx terminals is asserted the interrupt select bits are ignored and this register returns the interrupt value for
394. set to 1 when a cycle initiated by the SD host controller on the PCI bus was terminated by a target abort Detected parity error Bit 15 is set to 1 when either an address parity or data parity error is detected Signaled system error Bit 14 is set to 1 when SERR is enabled and the SD host controller has signaled a system error to the host N a ar TABORT_SIG RCU Signaled target abort Bit 11 is set to 1 by the SD host controller when it terminates a transaction on the PCI bus with a target abort PCI_SPEED R DEVSEL timing Bits 10 and 9 encode the timing of DEVSEL and are hardwired to 01b indicating that the SD host controller asserts this signal at a medium speed on nonconfiguration cycle accesses DATAPAR RCU Data parity error detected Bit 8 is set to 1 when the following conditions have been met a PERR was asserted by any PCI device including the SD host controller b The SD host controller was the bus master during the data parity error c Bit 6 PERR_EN in the command register at offset 04h in the PCI configuration space see Section 12 3 is set to 1 FBB_CAP Fast back to back capable The SD host controller cannot accept fast back to back transactions therefore bit 7 is hardwired to 0 User definable features UDF supported The SD host controller does not support the UDF therefore bit 6 is hardwired to 0 66MHZ 66 MHz capable The SD host controller operates at a maximum PCLK frequenc
395. sible address space and either a doubleword or 16 bit word access yields indeterminate results CIS MEMTYPE CIS memory type This field returns Os when read indicating that the CardBus CIS base address register is 32 bits wide and mapping can be done anywhere in the 32 bit memory space CIS MEM CIS memory indicator Bit O returns 0 when read indicating that the CIS is mapped into system memory space 7 11 CardBus CIS Pointer Register The internal CARDBUS input to the 1394 OHCI core is tied high such that this register returns Os when read pe lee a ups ls let 2147 CardBus CIS pointer we RIR R R IR R R R R R R R R R R deat o o o of ofloloj ololojololojo o Register CardBus CIS pointer Offset 28h Type Read only Default 0000 0000h 7 8 7 12 Subsystem Identification Register The subsystem identification register is used for system and option card identification purposes This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space see Section 7 25 See Table 7 10 for a complete description of the register contents Bit 31 30 Name Subsystem identification peur e foe fotete fete e fete fo fote to foto Subsystem identification 15 13 pesa o lolo o e lo o of o o o o o ololo Register Subsystem identification Offset 2Ch Type Read Update Default 0000 0000h Table
396. smit interrupt event Offset 90h set register 94h clear register returns the contents of the isochronous transmit interrupt event register bit wise ANDed with the isochronous transmit interrupt mask register when read Type Read Set Clear Read only Default 0000 00XXh Table 8 17 Isochronous Transmit Interrupt Event Register Description BIT DESCRIPTION 31 8 Rsv R Reserved Bits 31 8 return Os when read RSC lsochronous transmit channel 7 caused the interrupt event register bit 6 isochTx interrupt 6 isoXmit6 RSC Isochronous transmit channel 6 caused the interrupt event register bit 6 isochTx interrupt RSC Isochronous transmit channel 5 caused the interrupt event register bit 6 isochTx interrupt RSC Isochronous transmit channel 4 caused the interrupt event register bit 6 isochTx interrupt RSC Isochronous transmit channel 3 caused the interrupt event register bit 6 isochTx interrupt RSC lsochronous transmit channel 2 caused the interrupt event register bit 6 isochTx interrupt RSC lsochronous transmit channel 1 caused the interrupt event register bit 6 isochTx interrupt o isoXmito RSC lsochronous transmit channel 0 caused the interrupt event register bit 6 isochTx interrupt 8 22 8 24 Isochronous Transmit Interrupt Mask Register The isochronous transmit interrupt mask set clear register enables the isochTx interrupt source on a per channel basis Reads from either the set register or t
397. socket event register offset 00h see Section 6 1 to be written and the CDETECT2 bit in the socket present state register offset 08h see Section 6 3 is unaffected Force CCD1 Writes to this bit cause the CD1EVENT bit in the socket event register offset 00h see Section 6 1 to be written and the CDETECT 1 bit in the socket present state register offset 08h see Section 6 3 is unaffected Force CSTSCHG Writes to this bit cause the CSTSEVENT bit in the socket event register offset 00h see Section 6 1 to be written The CARDSTS bit in the socket present state register offset 08h see Section 6 3 is unaffected FPWRCYCLE FCDETECT2 FCDETECT1 o FCARDSTS 6 5 Socket Control Register This register provides control of the voltages applied to the socket Vpp and Vcc The PCI7x21 PCI7x11 controller ensures that the socket is powered up only at acceptable voltages when a CardBus card is inserted See Table 6 6 for a complete description of the register contents 24 23 Socket control Register Socket conirol Offset CardBus Socket Address 10h Type Read only Read Write Default 0000 0400h Table 6 6 Socket Control Register Description This bit controls how the CardBus clock run state machine decides when to stop the CardBus clock to the CardBus card 0 The CardBus CLKRUN protocol can only attempt to stop slow the CaredBus clock if the 7 STOPCLK sockethas been idle for 8 clocks and the PCI
398. spRetries This field tells the asynchronous transmit response unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack data error is received from the target node The default value for this field is Oh 0 3 maxATRegRetries This field tells the asynchronous transmit DMA request unit how many times to attempt to retry the transmit operation for the response packet when a busy acknowledge or ack_data_error is received from the target node The default value for this field is Oh 8 4 CSR Data Register The CSR data register accesses the bus management CSR registers from the host through compare swap operations This register contains the data to be stored in a CSR if the compare is successful Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CN T Type R R R R_ R R_ R R R R R R R_ RRA pean x x x x x x xlx xi x x x x x x x Bit 15 14 13 12 1 10 9 87 te s 9372 10 CN T me AR RT TAR AA RAR ER RA AA AREA past ee ee eo ee oe ee oe Register CSR data Offset OCh Type Read only Default XXXX XXXXh 8 6 8 5 CSR Compare Register The CSR compare register accesses the bus management CSR registers from the host through compare swap operations This register contains the data to be compared with the existing value of the CSR resource Bit 31 30 29 28 27 26 25 2a 23 22
399. specification E PCI cycle frame FRAME is driven by the initiator of a bus cycle FRAME PCII3 PCIOS v Pullup resistor per CCP PCI specification DEVSEL is asserted to indicate that a bus transaction is beginning and data transfers continue while this signal is asserted When FRAME is deasserted the PCI bus transaction is in the final data phase PCI bus grant GNT is driven by the PCI bus arbiter to grant the controller access to the PCI bus after the current data transaction has completed GNT may or may not follow a PCI bus request depending on the PCI bus parking algorithm 2 Z Initialization device select IDSEL selects the controller during configuration space accesses IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus No PCI initiator ready IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the transaction A data phase is completed on a rising edge of PCLK where both IRDY and TRDY are asserted Until IRDY and TRDY are both sampled asserted wait states are inserted 3 O Lal O m pu D PCI bus request REQ is asserted by the controller to request access to the PCI bus as an initiator PCI system error SERR is an output that is pulsed from the controller when enabled through bit 8 of the command register PCI offset 04h see Section 4 4 indicating a system error has occurred The controller need not be the target of the PCI cyc
400. ss space 0 MEM_INDICATOR KJ Memory space indicator Bit 0 is hardwired to 0 to indicate that the base address maps into memory space 12 9 Subsystem Vendor Identification Register The subsystem identification register used for system and option card identification purposes may be required for certain operating systems This read only register is initialized through the EEPROM and can be written through the subsystem access register at PCI offset 8Ch see Section 12 23 All bits in this register are reset by GRST only Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Subsystem vendor identification Name Default Register Subsystem vendor identification Offset 2Ch Type Read Update Default 0000h 12 10 Subsystem Identification Register The subsystem identification register used for system and option card identification purposes may be required for certain operating systems This read only register is initialized through the EEPROM and can be written through the subsystem access register at PCI offset 8Ch see Section 12 23 All bits in this register are reset by GRST only a5 14 feta 10 9 8 7 6 5 4 3 2 1 o0 CON Ca 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default 0 Register Subsystem identification Offset 2Eh Type Read Update Default 0000h 12 11 Capabilities Pointer Register The power management capabilities pointer register provides a pointer into the PCI configu
401. ss the first 4 Kbytes of memory to CardBus Memory limit registers 0 1 Name rw Aw R AR rR Ri AR R R AR AR RR OR Deam o o of o ofofofojojopofojfojojo Register Memory limit registers 0 1 Offset 20h 28h Type Read only Read Write Default 0000 0000h 4 21 CardBus I O Base Registers 0 1 These registers indicate the lower address of a PCI I O address range They are used by the PCI7x21 PCI7x11 controller to determine when to forward an I O transaction to the CardBus bus and likewise when to forward a CardBus cycle to the PCI bus The lower 16 bits of this register locate the bottom of the I O window within a 64 Kbyte page The upper 16 bits 31 16 are all Os which locates this 64 Kbyte page in the first page of the 32 bit PCI I O address space Bits 31 2 are read write and always return Os forcing I O windows to be aligned on a natural doubleword boundary in the first 64 Kbyte page of PCI I O address space Bits 1 0 are read only returning 00 or 01 when read depending on the value of bit 11 IO_BASE_SEL in the general control register PCI offset 86h see Section 4 31 These I O windows are enabled when either the I O base register or the I O limit register is nonzero The I O windows by default are not enabled to pass the first doubleword of I O to CardBus Either the I O base register or the I O limit register must be nonzero to enable any I O transactions Register
402. ster This register provides host software with information on 16 bit PC Card support and 82365SL DF compatibility See Table 5 2 for a complete description of the register contents NOTE If bit 5 SUBSYRW in the system control register is 1 then this register is read only Type R Default 1 Register ExCA identification and revision Offset CardBus Socket Address 800h Card A ExCA Offset 00h Card B ExCA Offset 40h Type Read Write Read only Default 84h Table 5 2 ExCA Identification and Revision Register Description BIT SIGNAL TYPE FUNCTION Interface type These bits which are hardwired as 10b identify the 16 bit PC Card support provided by the 6t IFTYPE PCI7x21 PCI7x11 controller The PCI7x21 PCI7x11 controller supports both I O and memory 16 bit PC Cards 82365SL DF revision This field stores the Intel 82365SL DF revision supported by the PCI7x21 PCI7x11 3 365REV controller Host software can read this field to determine compatibility to the 82365SL DF register set This field defaults to 0100b upon reset Writing 0010b to this field places the controller in the 82356SL mode These bits are cleared only by the assertion of GRST R RSVD RW These bits can be used for 82365SL emulation 0 RW 5 5 5 2 ExCA Interface Status Register This register provides information on current status of the PC Card interface An X in the default bit values indicates that the value of the bit after reset
403. t Pin Register 2 0 0 c eee eee ee eee 12 9 Minimum Grant Register Description cece eee eee 12 9 Maximum Latency Register Description 0oooooo 12 10 Maximum Latency Register Description ooooooo o 12 10 Capability ID and Next Item Pointer Registers Description 12 11 Power Management Capabilities Register Description 12 12 Power Management Control and Status Register Description 12 13 General Control Register notorias dra as 12 14 Subsystem Access Register Description 12 15 Diagnostic Register Description ooooooooommmmmmoo 12 15 Function 5 Configuration Register Map 2 ee eee eee 13 1 Command Register Description asaan aaa DALA kA DAA GA Dh 13 3 Status Register Description ooococcoocccccocrcr 13 4 Class Code and Revision ID Register Description 13 5 Latency Timer and Class Cache Line Size Register Description 13 5 Header Type and BIST Register Description 13 6 PCI Interrupt Pin Register 224 nah nak eed Wee bude bes KARA es 13 9 Minimum Grant Register Description a 13 9 Maximum Latency Register Description o oo o o 13 10 Capability ID and Next Item Pointer Registers Description 13 10 Power Management Capabilities Register Description 13 11 Power Management Control a
404. t to 1 for local bus node number 34 physical requests received by the controller from that node are handled through the physical request context 1 physReqResource33 RSC If bit 1 is set to 1 for local bus node number 33 physical requests received by the controller from that node are handled through the physical request context 0 physReqResource32 RSC If bit O is set to 1 for local bus node number 32 physical requests received by the controller from that node are handled through the physical request context 8 36 8 38 Physical Request Filter Low Register The physical request filter low set clear register enables physical receive requests on a per node basis and handles the lower node IDs When a packet is destined for the physical request context and the node ID has been compared against the asynchronous request filter registers then the node ID comparison is done again with this register If the bit corresponding to the node ID is not set to 1 in this register then the request is handled by the asynchronous request context instead of the physical request context See Table 8 30 for a complete description of the register contents 26 25 24 23 22 21 20 19 18 17 16 Name Physical request filter low pesa o o Lo Lo o o o to fo fo o 9 0 o o Bit 15 14 13 12 11 10 9 8 7 6 5 4a 3 2 1 0 Name Physical request filter low Type RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC RSC
405. t to 1 to indicate a read data transfer In addition the PCI7x21 PCI7x11 master must acknowledge reception of the read bytes from the slave transmitter The slave transmitter drives the SDA signal during read data transfers The SCL signal remains driven by the PCI7x21 PCI7x11 master Slave Address Word Address Slave Address Eelke EET a Ral E 0 Data Byte i SEREEERELT Paa A Slave Acknowledgement M Master Acknowledgement S P Start Stop Condition Figure 3 10 Serial Bus Protocol Byte Read Figure 3 11 illustrates EEPROM interface doubleword data collection protocol Slave Address Word Address Slave Address Aa a A an ka a an O ara ma Oe nG ed pa PAKA aaa Data Byte 3 ci Data Byte 2 m Data Byte 1 m Data Byte 0 mie A Slave Acknowledgement M Master Acknowledgement S P Start Stop Condition Figure 3 11 EEPROM Interface Doubleword Data Collection 3 6 4 Serial Bus EEPROM Application When the PCI bus is reset and the serial bus interface is detected the PCI7x21 PCI7x11 controller attempts to read the subsystem identification and other register defaults from a serial EEPROM This format must be followed for the PCI7x21 PCI7x11 controller to load initializations from a serial EEPROM All bit fields must be considered when programming the EEPROM The serial EEPROM is addressed at slave address 1010 000b by the PCI7x21 PCI7x11 controller All hardware address bits for the EEPROM must be tied to the appropriate level to achieve t
406. tart at offset 000h and the memory mapped ExCA registers begin at offset 800h This register is not shared by functions 0 and 1 so the system maps each socket control register separately m Jalolelelolels ale e e e w e Bes ade Poet 0 CardBus socket registers ExCA base address Name EA ka A po fofoftoftofoftofofofofofofofofofo Register CardBus socket registers ExCA base address Offset 10h Type Read only Read Write Default 0000 0000h 4 13 Capability Pointer Register The capability pointer register provides a pointer into the PCI configuration header where the PCI power management register block resides PCI header doublewords at AOh and A4h provide the power management PM registers Each socket has its own capability pointer register This register is read only and returns AOh when read 7 fee 7 3s pg 1 A T mwe rR R R R R R R C EE a aa A Register Capability pointer Offset 14h Type Read only Default AOh 4 8 4 14 Secondary Status Register The secondary status register is compatible with the PCI PCI bridge secondary status register It indicates CardBus related device information to the host system This register is very similar to the PCI status register PCI offset 06h see Section 4 5 and status bits are cleared by a writing a 1 This register is not shared by the two socket functions but is accessed on a per socket basis See Table 4 5
407. tem hardware reset and is unaffected by bus reset 10 3 Vendor Identification Register The vendor identification page identifies the vendor manufacturer and compliance level The page is selected by writing 1 to the Page Select field in base register 7 Table 10 5 shows the configuration of the vendor identification page and Table 10 6 shows the corresponding field descriptions Table 10 5 Page 1 Vendor ID Register Configuration BIT POSITION appress o 4 2 3 4 8 6 7 gt 1000 Compliance 1001 Reserved 1010 Vendor_ID 0 1011 Vendor ID 1 1100 Vendor ID 2 1101 Product ID O 1110 Product ID 1 1111 Product ID 2 Table 10 6 Page 1 Vendor ID Register Field Descriptions FIELD SIZE TYPE DESCRIPTION pee OR Compliance level For the PCI7x21 PCI7x11 controller this field is 01h indicating compliance with IEEE Std 1394a 2000 Vendor ID Manufacturer s organizationally unique identifier OUI For the PCI7x21 PCI7x11 controller this field is 08 0028h Texas Instruments the MSB is at register address 1010b Product_ID heme aad Product identifier For the PCI7x21 PCI7x11 controller this field is 42 4499h the MSB is at register address 1101b 10 5 10 4 Vendor Dependent Register The vendor dependent page provides access to the special control features of the PCI7x21 PCI7x11 controller as well as to configuration and status information used in manufacturing test and debug This page is selected by
408. the initial AT threshold value which is used until the AT FIFO is underrun When the PCI7x21 PCI7x11 controller retries the packet it uses a 2K byte threshold resulting in a store and forward operation 00 Threshold 2K bytes resulting in a store and forward operation 01 Threshold 1 7K bytes default 10 Threshold 1K bytes 11 Threshold 512 bytes These bits fine tune the asynchronous transmit threshold For most applications the 1 7K byte threshold is optimal Changing this value may increase or decrease the 1394 latency depending on the average PCI bus latency atx_thresh Setting the AT threshold to 1 7K 1K or 512 bytes results in data being transmitted at these thresholds or when an entire packet has been checked into the FIFO If the packet to be transmitted is larger than the AT threshold then the remaining data must be received before the AT FIFO is emptied otherwise an underrun condition occurs resulting in a packet error at the receiving node As a result the link then commences a store and forward operation It waits until it has the complete packet in the FIFO before retransmitting it on the second attempt to ensure delivery An AT threshold of 2K results in a store and forward operation which means that asynchronous data is not transmitted until an end of packet token is received Restated setting the AT threshold to 2K results in only complete packets being transmitted dis_at_pipeline na 12 Note that this
409. the isochronous receive context 0 synchronizes reception to the DV frame start tag in bufferfill mode if input more b 01b and jumps to the descriptor pointed to by frameBranch if a DV frame start tag is received out of place This bit is only interpreted when bit O CIP Strip0 is set to 1 and bit 30 isochHeader in the isochronous receive context control register at OHCI offset 400h 404h see Section 8 44 is cleared to 0 CIP Stripo When bit 0 is set to 1 the isochronous receive context 0 strips the first two quadlets of payload This bit is only interpreted when bit 30 isochHeader in the isochronous receive context control register at OHCI offset 400h 404h see Section 8 44 is cleared to 0 9 4 Link Enhancement Register This register is a memory mapped set clear register that is an alias of the link enhancement control register at PCI offset F4h These bits may be initialized by software Some of the bits may also be initialized by a serial EEPROM if one is present as noted in the bit descriptions below If the bits are to be initialized by software then the bits must be initialized prior to setting bit 19 LPS in the host controller control register at OHCI offset 50h 54h see Section 8 16 See Table 9 3 for a complete description of the register contents Default Register Link enhancement Offset A88h set register A8Ch clear register Type Read Set Clear Read only Default 0000 0000h Table
410. the speed capability of the node PHY and LLC in combination However this field does not affect the PHY speed capability indicated to peer PHYs during self ID the PCI7x21 PCI7x11 PHY layer identifies itself as S400 capable to its peers regardless of the value in this field This field is set to 10b S400 by system hardware reset and is unaffected by bus reset 10 6 10 5 Power Class Programming The PCO PC2 terminals are programmed to set the default value of the power class indicated in the pwr field bits 21 23 of the transmitted self ID packet Table 10 9 shows the descriptions of the various power classes The default power class value is loaded following a system hardware reset but is overridden by any value subsequently loaded into the Pwr_Class field in register 4 Table 10 9 Power Class Descriptions 000 Node does nal need power and does notre poner 10 7 10 8 11 Flash Media Controller Programming Model This section describes the internal PCI configuration registers used to program the PCI7x21 PCI7x11 flash media controller interface All registers are detailed in the same format a brief description for each register is followed by the register offset and a bit table describing the reset state for each register A bit description table typically included when the register contains bits of more than one type or purpose indicates bit field names a detailed field description and field access tags which appear
411. ther mass storage controller 1 5 8 PGMIF R Programming interface This field returns 00h when read Silicon revision This field returns 00h when read which indicates the silicon revision of the flash media GElrBEY R controller 11 6 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the flash media controller See Table 11 5 for a complete description of the register contents 115 14 13 12 11 10 9 8 7 6 5 4 3 2 1 o0 Name Tanay mer and ass cache ine za peram o fo o o lo o o o o o lolo o o o o Register Latency timer and class cache line size Offset OCh Type Read Write Default 0000h Table 11 5 Latency Timer and Class Cache Line Size Register Description FIELD NAME TYPE DESCRIPTION PCI latency timer The value in this register specifies the latency timer for the flash media controller in units of PCI clock cycles When the flash media controller is a PCI bus initiator and asserts FRAME 15 8 LATENCY_TIMER RW the latency timer begins counting from zero If the latency timer expires before the flash media transaction has terminated then the flash media controller terminates the transaction when its GNT is deasserted 7 0 CACHELINE SZ RW Cache line size This value is used by the flash media controller during memory write and invalidate m
412. tion 0 3 5 SPKROUT Connection to Speaker Driver oo oocoooooo o 3 6 Two Sample LED Circuits 0 AN see rai a ita PARA a 3 7 Serial Bus Start Stop Conditions and Bit Transfers 3 8 Serial Bus Protocol Acknowledge aa 3 9 Serial Bus Protocol Byte Write cece eee eee eee 3 10 Serial Bus Protocol Byte Read cece eee eee 3 11 EEPROM Interface Doubleword Data Collection 3 12 IRQ Implementation oococcccocccccocccr eee 3 13 System Diagram Implementing CardBus Device Class Power Management 20 6 kesitaa APA 3 14 Signal Diagram of Suspend Function a 3 15 ROUT Functional Diagram lt 2 tic cca eieadetaesdpeaien eee iades 3 16 Block Diagram of a Status Enable Cell ooooocooocoooooo 3 17 TP Cable Connections 703 cess peckeraied dex ELENA vee iba TEN sea de 3 18 Typical Compliant DC Isolated Outer Shield Termination 3 19 Non DC Isolated Outer Shield Termination aa 3 20 Load Capacitance for the PCI7x21 PCI7x11 PHY 3 21 Recommended Crystal and Capacitor Layout 5 1 ExCA Register Access Through I O 2 0 c eee eee eee 5 2 ExCA Register Access Through Memory 0000 ee eee eens 6 1 Accessing CardBus Socket Registers Through PCI Memory 14 1 Test Load Diagram wi vevstad eves PUN NBA ecko de eee whe ee Table
413. tion 12 9 bits 15 0 Subsystem ID register PCI offset 2Eh see Section 12 10 bits 15 0 Power management control and status register PCI offset 84h see Section 12 19 bits 15 8 1 0 General control register PCI offset 88h see Section 12 22 bits 6 4 0 Diagnostic register PCI offset 90h see Section 12 24 bits 31 0 The global reset only function 5 register bits Subsystem vendor ID register PCI offset 2Ch see Section 13 10 bits 15 0 Subsystem ID register PCI offset 2Eh see Section 13 11 bits 15 0 Power management control and status register PCI offset 48h see Section 13 19 bits 15 8 1 0 General control register PCI offset 4Ch see Section 13 22 bits 6 4 0 3 29 3 9 IEEE 1394 Application Information 3 9 1 PHY Port Cable Connection PCI7x21 PCI7x11 CPS PO 1 uF gt TPBIAS 56 2 56 2 PT T TOTO a TPA gt TPA l Cable Port e TPB a AL gt TPB n 56 2 56 2 4 5 AAA RNA Ki 220 pF see Note A 5 ko Outer Shield Termination NOTE A IEEE Std 1394 1995 calls for a 250 pF capacitor which is a nonstandard component value A 220 pF capacitor is recommended Figure 3 17 TP Cable Connections Outer Cable Shield 1MQ 0 01u4F 0 001 uF Chassis Ground Figure 3 18 Typical Compliant DC Isolated Outer Shield Termination 3 30 Outer Cable Shield Chassis Ground Fig
414. tion of the register contents Write access to the subsystem access register updates the subsystem identification registers identically to OHCI Lynx The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at Function 2 PCI offsets 2Ch and 2Eh respectively The system ID value written to this register may also be read back from this register See Table 7 22 for a complete description of the register contents 3 4 6 Function 3 Flash Media Subsystem Identification The subsystem identification register is used for system and option card identification purposes This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset 50h in the PCI configuration space see Section 11 22 Subsystem Access Register See Table 11 15 for a complete description of the register contents The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers at Function 3 PCI offsets 2Ch and 2Eh respectively See Table 11 15 for a complete description of the register contents 3 4 7 Function 4 SD Host Subsystem Identification The subsystem identification register is used for system and option card identification purposes This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset 8Ch in the PCI configuration space see Section 12 23 Subsystem Access Register
415. tion register externally maps to the first quadlet in the Bus_Info_Block and contains the constant 3133 3934h which is the ASCII value of 1394 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Bus identification Laag po o 4 La fo 0 4 5 Li li o 6 Jai 4 Be Ee Name fo Busidemifeation we r r IR IR RIRIR R R R R R R R R R peta o o Pt fs o o 1 fo o 1 1lo i1 o lo Register Bus identification Offset 1Ch Type Read only Default 3133 3934h 8 8 8 9 Bus Options Register The bus options register externally maps to the second quadlet of the Bus Info Block See Table 8 7 for a complete description of the register contents 27 26 25 24 23 22 21 20 19 18 17 16 Name Ba T aw aw A aja AW AW Derun x x polo OO oo er ss 9 a 2 9 frofofe 7 o 5s 0 32 130 CAS EN Bus options Type rw Rw RW Awl R R R r Rw Rw R R R R R R pean o o o o fo o XT x o o o o 1 o Register Bus options Offset 20h Type Read Write Read only Default XOXX A0X2h Table 8 7 Bus Options Register Description FIELD NAME TYPE DESCRIPTION irmc Isochronous resource manager capable IEEE 1394 bus management field Must be valid when bit 17 linkEnable in the host controller control register at OHCI offset 50h 54h see Section 8 16 is set to 1 The default value for this bit is O
416. tions PC Card battery conditions BVD1 BVD2 A transition on BVD2 indicates a change in the bts evDaSPRRVICAUDIO BVD2SPRRJ CAUDO PC Card battery conditions memory Wait stat s A transition on READY indicates a change in the READY IREQ CINT ability of the memory PC Card to accept or provide READY data Change in card The assertion of STSCHG indicates a status change 16 bit 1 O status STSCHG KI BVD1 STSCHG CSTSCHG an tho PC Card 16 bit 1 O Interrupt request The assertion of IREQ indicates an interrupt request UltraMedia REQ READY IREQV CINT from the PG Card Change in card The assertion of CSTSCHG indicates a status status CSTSCHG KI BVD1 STSCHG CSTSCHG change on the PC Card CardBus Interrupt request The assertion of CINT indicates an interrupt request CINT READY IREQ JICINT from the PC Card PCC carmen co ES Smart Card or removal CD2 CCD adapters CardBus PC Card UltraMedia Power cycle esc N A An interrupt is generated when a PC Card power up Flash Media complete cycle has completed The naming convention for PC Card signals describes the function for 16 bit memory I O cards and CardBus For example READY IREQ CINT includes READY for 16 bit memory cards IREQ for 16 bit I O cards and CINT for CardBus cards The 16 bit memory card signal name is first with the I O card signal name second enclosed in parentheses The CardBus signal name follows after a double slash The 1997 PC Car
417. troller drives these signals to a valid logic level Assertion can be asynchronous to CCLK but deassertion must be synchronous to CCLK T These terminals are reserved for the PCI7611 and PCI7411 controllers PD PU3 U3 2 22 Table 2 13 CardBus PC Card Address and Data Terminals External components are not applicable for the 16 bit PC Card address and data terminals If any CardBus PC Card address and data terminal is unused then the terminal may be left floating SKT A TERMINAL SKT B TERMINALT vo POWER A_CAD31 D01 B_CAD31 A_CAD30 C01 B CAD30 A CAD29 D03 B CAD29 A CAD28 C02 B CAD28 A CAD27 B01 B_CAD27 A_CAD26 B04 B CAD26 A CAD25 A04 B CAD25 A CAD24 E06 B CAD24 A CAD23 B05 B_CAD23 A_CAD22 C06 B CAD22 A CAD21 B06 B_CAD21 A_CAD20 Gog B_CAD20 A_CAD19 C07 B_CAD19 A_CAD18 B07 B CAD18 A CAD17 A07 B CAD17 CardBus address and data These signals make up the multiplexed A CAD16 A10 B_CAD16 CardBus address and data bus on the CardBus interface During Vocal the address phase of a CardBus cycle CAD31 CADO contain a I O PCII7 PCIO7 A_CAD15 E11 B CAD15 32 bit address During the data phase of a CardBus cycle VCCB A_CAD14 G11 B CAD14 CAD31 CADO contain data CAD31 is the most significant bit A CAD13 C11 B CAD13 A CAD12 B11 B CAD12 A CAD11 C12 B CAD11 A CAD10 B12 B CAD10 A CAD9 A12 B CAD9 A CAD8 E12 B CAD8 A CAD7 C13 B CAD7 A CAD6 F12 B CAD6 A CAD5 A13 B CAD5 A CAD4 C14 B CAD4 A CAD3 E13 B CAD3
418. ts T w de N On an overflow for each running context the isochronous transmit DMA supports up to 7 cycle skips when the following are true 1 Bit 11 dead in either the isochronous transmit or receive context control register is set to 1 2 Bits 4 0 eventcode field in either the isochronous transmit or receive context control register is set to evt timeout 3 Bit 24 unrecoverableError in the interrupt event register at OHCI offset 80h 84h see Section 8 21 is set to 1 8 S o 8 43 Isochronous Transmit Context Command Pointer Register The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the PCI7x21 PCI7x11 controller accesses when software enables an isochronous transmit context by setting bit 15 run in the isochronous transmit context control register see Section 8 42 to 1 The isochronous transmit DMA context command pointer can be read when a context is active The n value in the following register addresses indicates the context number n 0 1 2 3 7 26 25 24 23 22 21 20 19 18 17 16 Name Isochronous transmit context command pointer AA EE A NEO NA EC PEA A a petan x x x x x x x x Tx x x x Isochronous transmit context command pointer ame etarras command pami ye A ATA ATA A A R A A AR ATA A ATA pemn x x x x x x x x x x x x x Register Isochronous transmit context command
419. ture is the primary method of power management on the PCI interface of the PCI7x21 PCI7x11 controller CLKRUN signaling is provided through the MFUNC6 terminal Since some chip sets do not implement CLKRUN this is not always available to the system designer and alternate power saving features are provided For details on the CLKRUN protocol see the PC Mobile Design Guide The PC17x21 PC17x11 controller does not permit the central resource to stop the PCI clock under any of the following conditions e Bit 1 KEEPCLK in the system control register PCI offset 80h see Section 4 29 is set e The 16 bit PC Card resource manager is busy e The PCI7x21 PC17x11 CardBus master state machine is busy A cycle may be in progress on CardBus e The PCI7x21 PCI7x11 master is busy There may be posted data from CardBus to PCI in the PCI7x21 PCI7x11 controller e Interrupts are pending e The CardBus CCLK for the socket has not been stopped by the PCI7x21 PCI7x11 CCLKRUN manager e Bit 0 KEEP PCLK in the miscellaneous configuration register PCI offset FOh see Section 7 23 is set e The 1394 resource manager is busy e The PCI7x21 PCI7x11 1394 master state machine is busy A cycle may be in progress on 1394 e The PCI7x21 PCI7x11 master is busy There may be posted data from the 1394 bus to PCI in the PCI7x21 PCI7x11 controller e PC Card interrogation is in progress e The 1394 bus is not idle The PCI7x21 PCI7x11 controller restarts the PCI clo
420. ubsystem ID register PCI offset 2Eh see Section 7 12 bits 31 16 Minimum grant and maximum latency register PCI offset 3Eh see Section 7 16 bits 15 0 Power management control and status register PCI offset 48h see Section 7 20 bits 15 8 1 0 Miscellaneous configuration register PCI offset FOh see Section 7 23 bits 15 11 8 5 0 Link enhancement control register PCI offset F4h see Section 7 24 bits 15 12 10 8 7 2 1 Bus options register OHCI offset 20h see Section 8 9 bits 15 12 GUID high register OHCI offset 24h see Section 8 10 bits 31 0 GUID low register OHCI offset 28h see Section 8 11 bits 31 0 Host controller control register OHCI offset 50h 54h see Section 8 16 bit 23 Link control register OHCI offset EOh E4h see Section 8 31 bit 6 PHY link loopback test register Local offset C14h bits 6 4 O Link test control register Local offset COOh bits 12 8 3 28 The global reset only function 3 register bits Subsystem vendor ID register PCI offset 2Ch see Section 11 9 bits 15 0 Subsystem ID register PCI offset 2Eh see Section 11 10 bits 15 0 Power management control and status register PCI offset 48h see Section 11 18 bits 15 8 1 0 General control register PCI offset 4Ch see Section 11 21 bits 6 4 2 0 Diagnostic register PCI offset 54h see Section 11 23 bits 31 0 The global reset only function 4 register bits Subsystem vendor ID register PCI offset 2Ch see Sec
421. uced by board and device variations Trade offs between frequency tolerance and stability may be made as long as the total frequency variation is less than 100 ppm For example the frequency tolerance of the crystal may be specified at 50 ppm and the temperature tolerance may be specified at 30 ppm to give a total of 80 ppm possible variation due to the crystal alone Crystal aging also contributes to the frequency variation e Load capacitance For parallel resonant mode crystal circuits the frequency of oscillation is dependent upon the load capacitance specified for the crystal Total load capacitance C_ is a function of not only the discrete load capacitors but also board layout and circuit It is recommended that load capacitors with a maximum of 5 tolerance be used For example load capacitors C9 and C10 in Figure 3 20 of 16 pF each were appropriate for the layout of the PCI7x21 PCI7x11 evaluation module EVM which uses a crystal specified for 12 pF loading The load specified for the crystal includes the load capacitors C9 and C10 the loading of the PHY pins Cpyy and the loading of the board itself Cpp The value of Cpyy is typically about 1 pF and Cpp is typically 0 8 pF per centimeter of board etch a typical board can have 3 pF to 6 pF or more The load capacitors C9 and C10 combine as capacitors in series so that the total load capacitance is C9 x C10 CL Go4 cio 1 CPHY CBD y x1 x
422. ure 3 12 Not shown is that INTA must also be routed to the programmable interrupt controller PIC or to some circuitry that provides parallel PCI interrupts to the host PCI7x21 PCI7x11 MFUNC1 MFUNC2 MFUNC3 MFUNC4 MFUNC5 MFUNC6 Figure 3 12 IRQ Implementation Power on software is responsible for programming the multifunction routing status register to reflect the IRQ configuration of a system implementing the PCI7x21 PCI7x11 controller The multifunction routing status register is a global register that is shared between the four PCI7x21 PCI7x11 functions See Section 4 36 Multifunction Routing Status Register for details on configuring the multifunction terminals The parallel ISA type IRQ signaling from the MFUNC6 MFUNCO terminals is compatible with the input signal requirements of the 8259 PIC The parallel IRQ option is provided for system designs that require legacy ISA IRQs Design constraints may demand more MFUNC6 MFUNCO IRQ terminals than the PCI7x21 PCI7x11 controller makes available 3 7 4 Using Parallel PCI Interrupts Parallel PCI interrupts are available when exclusively in parallel PCI interrupt parallel ISA IRQ signaling mode and when only IRQs are serialized with the IRQSER protocol The INTA INTB INTC and INTD can be routed to MFUNC terminals MFUNCO MFUNC1 MFUNC2 and MFUNC4 If bit 29 INTRTIE is set in the system control register PCI offset 80h see Section 4 29 then INTA and INTB
423. ure 3 19 Non DC Isolated Outer Shield Termination 3 9 2 Crystal Selection The PCI7x21 PCI7x11 controller is designed to use an external 24 576 MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit This oscillator in turn drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data at the S100 through S400 media data rates A variation of less than 100 ppm from nominal for the media data rates is required by IEEE Std 1394 1995 Adjacent PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks and PHY devices must be able to compensate for this difference over the maximum packet length Large clock variations may cause resynchronization overflows or underflows resulting in corrupted packet data The following are some typical specifications for crystals used with the PHYs from TI in order to achieve the required frequency accuracy and stability e Crystal mode of operation Fundamental e Frequency tolerance 25 C Total frequency variation for the complete circuit is 100 ppm A crystal with 30 ppm frequency tolerance is recommended for adequate margin e Frequency stability over temperature and age A crystal with 30 ppm frequency stability is recommended for adequate margin NOTE The total frequency variation must be kept below 100 ppm from nominal with some allowance for error introd
424. ure that the socket must initiate on card insertion into a cold nonpowered socket Through this interrogation card voltage requirements and interface 16 bit versus CardBus are determined The scheme uses the card detect and voltage sense signals The configuration of these four terminals identifies the card type and voltage requirements of the PC Card interface 3 5 2 Low Voltage CardBus Card Detection The card detection logic of the PCI7x21 PCI7x11 controller includes the detection of Cardbus cards with Voc 3 3 V and Vpp 1 8 V The reporting of the 1 8 V CardBus card Vcc 3 3 V Vpp 1 8 V is reported through the socket present state register as follows based on bit 10 12V_SW_SEL in the general control register PCI offset 86h see Section 4 31 e If the 12V_SW_SEL bit is 0 TPS2228 is used then the 1 8 V CardBus card causes the 3VCARD bit in the socket present state register to be set e Ifthe 12V_SW_SEL bit is 1 TPS2226 is used then the 1 8 V CardBus card causes the XVCARD bit in the socket present state register to be set 3 5 3 UltraMedia Card Detection The PCI7x21 PCI7x11 controller is capable of detecting all the UltraMedia devices defined by the PCMCIA Proposal 0262 MultiMedia Cards Secure Digital Memory Stick devices and Smart Card devices The detection of these devices is made possible through circuitry included in the PCI7x21 PCI7x11 controller and the adapters used to interface these devices with the PC
425. when a write occurs to set the socket power and the SMIENB bit is set Writing a 1 to this bit clears the status 0 SMI interrupt is signaled 1 SMI interrupt is not signaled 257 SMISTATUS RW SMI interrupt mode enable When this bit is set the SMI interrupt signaling generates an interrupt when a write to the socket power control occurs This bit is shared and defaults to 0 disabled 0 SMI interrupt mode is disabled default 1 SMI interrupt mode is enabled RSVD R Reserved 24 SMIENB RW 2 0v These bits are cleared only by the assertion of GRST These bits are global in nature and must be accessed only through function 0 U 00 Table 4 8 System Conirol Register Description continued BIT SIGNAL TYPE FUNCTION CardBus reserved terminals signaling When this bit is set the RSVD CardBus terminals are driven low when a CardBus card has been inserted When this bit is low these signals are placed in a high impedance state 0 Place the CardBus RSVD terminals in a high impedance state 1 Drive the CardBus RSVD terminals low default CBRSVD Vcc protection enable This bit is socket dependent 0 Vcc protection is enabled for 16 bit cards default 1 Vcc protection is disabled for 16 bit cards RW RW RSVD RW These bits are reserved Do not change the value of these bits Memory read burst enable downstream When this bit is set the PCI7x21 PCI7x11 controller allows RW
426. window 0 offset address high byte Offset CardBus Socket Address 815h Card A ExCA Offset 15h Card B ExCA Offset 55h Register ExCA memory window 1 offset address high byte Offset CardBus Socket Address 81Dh Card A ExCA Offset 1Dh Card B ExCA Offset 5Dh Register ExCA memory window 2 offset address high byte Offset CardBus Socket Address 825h Card A ExCA Offset 25h Card B ExCA Offset 65h Register ExCA memory window 3 offset address high byte Offset CardBus Socket Address 82Dh Card A ExCA Offset 2Dh Card B ExCA Offset 6Dh Register ExCA memory window 4 offset address high byte Offset CardBus Socket Address 835h Card A ExCA Offset 35h Card B ExCA Offset 75h Type Read Write Default 00h Table 5 13 ExCA Memory Windows 0 4 Offset Address High Byte Registers Description SIGNAL TYPE FUNCTION Write protect This bit specifies whether write operations to this memory window are enabled 7 WINWP This bit is encoded as 0 Write operations are allowed default 1 Write operations are not allowed This bit specifies whether this memory window is mapped to card attribute or common memory REG a 0 Memory window is mapped to common memory default 1 Memory window is mapped to attribute memory RW This bit is encoded as RW Offset address high byte These bits represent the upper address bits A25 A20 of the memory window offset OFFHB RW addfess 5 19 ExCA Card Detect and General Control Register Th
427. write request that failed 8 14 Posted Write Address High Register The posted write address high register communicates error information if a write request is posted and an error occurs while a the posted data packet See Table 8 10 for a eae snail of the ae contents aa Mm DER write Ea ECHEN ame RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU Default CEE a E ERE E Name Posted write address high Dean x x x x xf xitxi x x x x x x x x x Register Posted write address high Offset 3Ch Type Read Update Default XXXX XXXXh Table 8 10 Posted Write Address High Register Description FIELD NAME DESCRIPTION sourcelD This field is the 10 bit bus number bits 31 22 and 6 bit node number bits 21 16 of the node that issued the write request that failed The upper 16 bits of the 1394 destination offset of the write request that failed 8 15 Vendor ID Register The vendor ID register holds the company ID of an organization that specifies any vendor unique registers The PCI7x21 PCI7x11 controller implements Texas Instruments unique behavior with regards to OHCI Thus this register is read only and returns 0108 0028h when read 27 26 25 24 23 22 21 20 19 18 17 16 Name Vendor ID we ANA ee A asan asimag magan naaa ololololololo ir ololofo rlojoj o e CG O Vendor ID fee R R R IR R R R R R R R R R R R R Deta o o o foftotofotoftotyotrtoti totes Re
428. ws 0 and 1 Start Address Low Byte Registers These registers contain the low byte of the 16 bit I O window start address for I O windows 0 and 1 The 8 bits of these bana a to the lower 8 bits of the start address 7 d windows 0 and i start address low we ame Default Register ExCA I O window 0 start address oa Offset CardBus Socket Address 808h Card A ExCA Offset 08h Card B ExCA Offset 48h Register ExCA I O window 1 start address low byte Offset CardBus Socket Address 80Ch Card A ExCA Offset 0Ch Card B ExCA Offset 4Ch Type Read Write Default 00h 5 10 ExCA I O Windows 0 and 1 Start Address High Byte Registers These registers contain the high byte of the 16 bit I O window start address for I O windows 0 and 1 The 8 bits of these registers correspond to the upper 8 bits of the start address 7 ExCA I O windows 0 and 1 start address high byte Name Type w w w w w w w w petan oo o o o0 o o o o Register ExCA I O window 0 start address high byte Offset CardBus Socket Address 809h Card A ExCA Offset 09h Card B ExCA Offset 49h Register ExCA I O window 1 start address high byte Offset CardBus Socket Address 80Dh Card A ExCA Offset 0Dh Card B ExCA Offset 4Dh Type Read Write Default 00h 5 13 5 11 ExCA I O Windows 0 and 1 End Address Low Byte Registers These registers contain the low byte of the 16 bit I O window end address for I O windows 0
429. xCA Compatibility Registers Functions 0 and1 ExCA Identification and Revision Register ExCA Interface Status Register 0 0 0 cece eee eee ExCA Power Control Register 0 0c cece eee eee ExCA Interrupt and General Control Register ExCA Card Status Change Register la ExCA Card Status Change Interrupt Configuration Register ExCA Address Window Enable Register ExCA I O Window Control Register cece ee eee ExCA I O Windows 0 and 1 Start Address Low Byte Registers ExCA I O Windows 0 and 1 Start Address High Byte Registers ExCA I O Windows 0 and 1 End Address Low Byte Registers ExCA I O Windows 0 and 1 End Address High Byte Registers ExCA Memory Windows 0 4 Start Address Low Byte Registers ExCA Memory Windows 0 4 Start Address High Byte Registers ExCA Memory Windows 0 4 End Address Low Byte Registers ExCA Memory Windows 0 4 End Address High Byte Registers ExCA Memory Windows 0 4 Offset Address Low Byte Registers ExCA Memory Windows 0 4 Offset Address High Byte Registers ExCA Card Detect and General Control Register ExCA Global Control Register 224 cincecicmdeaduemeunae ee ts ExCA I O Windows 0 and 1 Offset Address Low Byte Registers ExCA I O Windows 0 and 1 Offset Address High Byte Registers ExCA Memory Windows 0 4 Page Registers
430. xeted Fa paid 4 21 4 32 General Purpose Event Status Register 4 23 4 33 General Purpose Event Enable Register 4 24 4 34 General Purpose Input Register 0 cee eee eee 4 24 4 35 General Purpose Output Register eee eee 4 25 4 36 Multifunction Routing Status Register oococoooccoooo 4 26 4 37 Retry Status Register i 2 0 0ce sweetest kka 4 27 4 38 Card Control Register 0 c cece cee eee 4 28 4 39 Device Control Register wawa ir ree KAWI haaha 4 29 4 40 Diagnostic Register 0 2 cece 4 30 4 41 Capability ID Register y oo xt AGA ide exe ba es 4 31 vi Section 4 42 4 43 4 44 4 45 4 46 4 47 4 48 4 49 4 50 5 1 Be 5 3 5 4 5 5 5 6 Dl 5 8 5 9 5 10 5 11 5 12 5 13 5 14 5 15 5 16 5 17 5 18 5 19 5 20 5 21 5 22 5 23 6 1 6 2 6 3 6 4 6 5 6 6 Next Item Pointer Register ama a naaa errar Power Management Capabilities Register Power Management Control Status Register Power Management Control Status Bridge Support Extensions Register vis 1st Dh K BARA BARAT KG HAAN id Power Management Data Register aa Serial Bus Data Register e eee eee eee Serial Bus Index Register 22 64 wa KAN AKA NANA Serial Bus Slave Address Register a eee Serial Bus Control Status Register 0 cee eee eee E
431. y Level rating according to the JEDEC industry standard classifications and peak solder temperature Important Information and Disclaimer The information provided on this page represents TI s knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from third parties TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals TI and TI suppliers consider certain information to be proprietary and thus CAS numbers and other limited information may not be available for release In no event shall TI s liability arising out of such information exceed the total purchase price of the TI part s at issue in this document sold by TI to Customer on an annual basis Addendum Page 1
432. y of 33 MHz therefore bit 5 is hardwired to 0 EEE i CAPLIST Capabilities list Bit 4 returns 1 when read indicating that the SD host controller supports additional PCI capabilities Interrupt status This bit reflects the interrupt status of the function Only when bit 10 INT_DISABLE in the command register See Section 12 3 is a 0 and this bit is 1 is the function s INTx signal asserted Setting the INT_DISABLE bit to 1 has no effect on the state of this bit This bit is set only when a valid interrupt condition exists This bit is not set when an interrupt condition exists and signaling of that event is not enabled INT_STATUS D C a w IN oO o NI z o 2 0 RSVD Reserved Bits 3 0 return Os when read 12 4 12 5 Class Code and Revision ID Register The class code and revision ID register categorizes the base class subclass and programming interface of the function The base class is 08h identifying the controller as a generic system peripheral The subclass is 05h identifying the function as an SD host controller The programming interface is 01h indicating that the function is a standard SD host with DMA capabilities Furthermore the TI chip revision is indicated in the least significant byte 00h See Table 12 4 for a complete description of the register contents 27 26 25 24 23 22 21 20 19 18 17 16 Class code and revision ID Name lass code andirevision ID mwe R
433. ysical requests received by the controller from that node are handled through the physical request context 17 physReqResource49 RSC If bit 17 is set to 1 for local bus node number 49 physical requests received by the controller from that node are handled through the physical request context 16 physReqResource48 RSC If bit 16 is set to 1 for local bus node number 48 physical requests received by the controller from that node are handled through the physical request context 15 physReqResource47 RSC If bit 15 is set to 1 for local bus node number 47 physical requests received by the controller from that node are handled through the physical request context 14 physReqResource46 RSC If bit 14 is set to 1 for local bus node number 46 physical requests received by the controller from that node are handled through the physical request context 13 physReqResource45 RSC If bit 13 is set to 1 for local bus node number 45 physical requests received by the controller from that node are handled through the physical request context 12 physReqResource44 RSC If bit 12 is set to 1 for local bus node number 44 physical requests received by the controller from that node are handled through the physical request context 11 physReqResource43 RSC If bit 11 is set to 1 for local bus node number 43 physical requests received by the controller from that node are handled through the physical request context 10 physReqResource42 RSC If bit 10 is set to

Texas Instruments PCI7421 User's Manual

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