Texas Instruments DAC3482 User's Manual
Contents
1. I II n heme eme eme hne nennen nn 2 2 DE d 3 PEE COnfiguratlolk EE 4 4 Digital BIOCk OPHONS sussies 5 5 OUTPUT Control OPMS sae P 6 6 CDCE62005 Tab Configured for 4x Inn 7 7 Test Set Up Block DiaQram EDD 8 8 TSW3100 CommsSignalPattern WCDMA Programming GUI eee HH 10 9 DAC3484 TRF3703 15 WCDMA Output 11 10 DAC3484 TRF3703 15 WCDMA Output 12 11 Locations of DAC348x to Transformer Output Jumper Locations 18 12 DAC3484 Transformer Coupled Output at 60MHz IF m 14 13 DAC3484 Transformer Coupled Output at 30MHZ IF IH 15 14 Locations of the DAC3482 to TRF3703 15 Interface Jumpers cesses 16 15 TSW3100 GUI Configuration for Generating a WCDMA Signal for 482 17 SLAUS36 March 201 1 DAC3484 DAC3482 EVM 1 Submit Documentation Feedback 2011 Texas Instruments Incorporated TEXAS INSTRUMENTS Introduction www ti com 1 Introduction 1 1 Overview This document is intended to serve as a2. LJ W 1c DE Power 10 58 dBm Lower 785 16 dB Upper 76 14 dB Lower 84 31 dB Upper B3 37 baseband 30MHz NCO 30MHz with NCO Gain disabled QMC Gain 1446 Figure 12 DAC3484 Transformer Coupled Output at 60MHz IF 14 DAC3484 DAC3482 EVM SLAUS36 March 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Optional Configuration Power 7 52 dBm d Lower 75 95 dB Upper 78 04 AB Lower 84 06 dB Upper 02 97 dB baseband 30MHz NCO disabled QMC Gain 1024 Figure 13 DAC3484 Transformer Coupled Output at 30MHz IF 42 Using the DAC3482 or Configuring DAC3484 in DAC3482 mode The DAC3484 EVM can also be used to evaluate the performance of DAC3482 or configure the DAC3484 in Dual DAC mode instead of the Quad DAC mode For DAC3482 or DAC3484 in Dual DAC mode only the Inner Channels B and C are functional and the other two channels A and D are disabled The software can be configured as DAC3482 interface by selecting DAC3482 EVM Software Control from the upper left hand corner of the pull down menu The DAC3484 EVM needs to be configured differently for the DAC3482 mode with the TRF3703 15 modulator The inner DACs need to be routed to the third TRF3703 15 modulator in the middle To enable the DAC3482 Dual DAC with the TRF3703 15 interface do the following board modifications 1 Remove R136 R278 R277 and R279
3. Enable Off Freq MHz Gain dB SCR Code Amplitude dB 8 co Carrier 1 30 us C Carrier 2 100 150 0 Frequency MHz C Carrier 3 2 TSW3100 Control master Two s TF LOAD and Run C Carrier 4 E ines 2 BwDDR 665325 16b MSB Justify C Bt Reverse C 16b aDAC 192 168 1123 C Bit Reverse v2 5 c 2005 2010 Texas Instruments Figure 8 TSW3100 CommsSignalPattern WCDMA Programming GUI 3 4 DAC348x Software Quick Start Guide Provide the clock input 1228 8 MHz at 1 5Vrms at J9 SMA connector of the DAC3484 EVM the LO source of 1 9GHz 12dBm max at either J19 or J22 SMA connector of the DAC3484 EVM Provide the LO source to J24 SMA connector for the DAC3482 EVM Turn on power to the board and press the reset button on the EVM Press the Reset USB Port button in GUI and verify USB communication Switch to the INPUT tab of GUI Click LOAD REGS browse to the installation folder and load example file DACS3484 FDAC 1228p8MHz 4xint 30MHz QMcCon txt This file contains settings for 4x interpolation with the DAC3484 running at 1228 8MSPS Load this file and wait a couple of seconds for the settings to go into effect e Verify the spectrum using the Spectrum Analyzer at the two RF outputs of the DAC EVM J20 and J21 Toggle the SIF SYNC button to sync the appr
4. F sample MHz 1228 8000 4 Enable Mixer Offset B 0 4 QMC GainB 1446 NCOFreq AB MHz 30 0000 4 Mixer Bypass M OffsetAB Sync REGWR 0 NCOFreg CD MHz 30 0000 Inverse sinx x filter CorrectAB Sync 51 SYNC Gain OdB E s U ee EER esee 0 S amccorectco enabled 104657600 _ Clock Receiver Sleep Offset D 0 s QC Gane TR Phase Offset AB tT n eek Diner sme OffsetCD Syne REGWR MIxAB Sync SIFSYNC Clock Div Sync source OSTR v QMC GainD 1446 PhaseCD 0 t NCO DOSED 204657600 E Grow Deitv A o CorrectCD Sync SIFSYNC MEE 0 Group Delay 0 Sync CD MixCD Sync SIF SYNC Group Delay C 0 Group Delay D 0 DAC Gain 10 SIF Sync Figure 4 Digital Block Options Interpolation allows control of the data rate versus DAC sampling rate ratio i e data rate x interpolation DAC sampling rate e Digital Mixer allows control of the coarse mixer function Note If fine mixer NCO is used the Enable Mixer button must be checked and the coarse mixer must be bypassed See NCO section for detail e Inverse sinx x filter allows compensation of the sinx x attenuation of the DAC output Note If inverse sinx x filter is used the input data digital full scale must be backed off accordingly to avoid digital saturation e Clock Receiver Sleep allows the DAC clock receiver to be in sleep mode The DAC has minimum power consumpti
5. 15 Output for DAC3482 Dual DAC Mode Figure 1 DAC3484 DAC3482 EVM Block Diagram 2 DAC3484 DAC3482 EVM SLAUS36 March 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Software Control 2 Software Control 2 1 Installation Instructions Open the folder named DAC348x Installer vxpx represents the latest version Run Setup exe Follow the on screen instructions installed launch by clicking on the DAC348x GUI vxpx program in Start Texas Instruments DACs When plugging in the USB cable for the first time you will be prompted to install the USB drivers When a pop up screen opens select Continue Downloading Follow the on screen instructions to install the USB drivers f needed you can access the drivers directly in the install directory 2 2 Software Operation The software allows programming control of the DAC device and the CDC device The front panel provides a tab for full programming of each device The GUI tabs provide more convenient and simplified interface to the most used registers of each device Each device including the DAC3484 DAC3482 DAC34H84 has its own custom control interface Select the device option from the top left hand corner The DAC3484 EVM Software Control is described in this section 2 2 1 Input Control Options DAC3484 EVM Software Control w Input Digital Output Advanced CDCE6200
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7. correct this interference EVM Warnings and Restrictions It is important to operate this EVM within the input voltage range of 5 5 V to 7 0V and the output voltage range of OV to 3 3 V Exceeding the specified input range may cause unexpected operation and or irreversible damage to the EVM If there are questions concerning the input range please contact a TI field representative prior to connecting the input power Applying loads outside of the specified output range may result in unintended operation and or possible permanent damage to the EVM Please consult the EVM User s Guide prior to connecting any load to the EVM output If there is uncertainty as to the load specification please contact a TI field representative During normal operation some circuit components may have case temperatures greater than 55 C The EVM is designed to operate properly with certain components above 55 C as long as the input and output ranges are maintained These components include but are not limited to linear regulators switching transistors pass transistors and current sense resistors These types of devices can be identified using the EVM schematic located in the EVM User s Guide When placing measurement probes near these devices during operation please be aware that these devices may be very warm to the touch Mailing Address Texas Instruments Post Office Box 655308 Dallas Texas 75265 Copyright O 2011 Texas Instruments Incorporated IMPORTANT
8. zero ohm jumpers 2 Install R137 R138 R246 R261 Refer to Figure 14 for locations of these zero ohm jumpers SLAU336 March 2011 DAC3484 DAC3482 EVM 15 Submit Documentation Feedback 2011 Texas Instruments Incorporated TEXAS INSTRUMENTS Optional Configuration www ti com gu nimus R209 MI I gas Pag S I i i I e 4 I UL Ci TT ALIUM Figure 14 Locations of the DAC3482 to TRF3703 15 Interface Jumpers The pattern generation is different for DAC3484 EVM when it is used as a Quad DAC compared to when itis used as a Dual DAC Figure 15 shows a screen shot of TSW3100 GUI for generating a communication signal for DAC3482 LVDS output option is selected The setting displayed generates a single carrier WCDMA signal at an IF of 30MHz for a DAC3482 running at 1228 8MHz with 4x interpolation enabled 16 DAC3484 DAC3482 EVM SLAUS36 March 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Optional Configuration TSW3100_CommSignalPattern_v2p7 m Test Models Signal Type Signal Characteristics i TEXAS 64ch Complex 3 84 Chiprate MSPS 16 Resolution C max size INSTRUMENTS 32ch C Complex IF 80 Interpolation INT 0 95 Backoff v time offset 30ch swap va TDSCDMA O Real O QAM T i dualRF Factory only Res BW 30000 Hz Time ms 1
9. 0 Center Frequency 154 ExactFreq 300 Vector size 022 alpha Random Seed Display Options C CCDF plot C Ext FFT Plot ResBW kHz Carriers Enable Off Freq MHz Gain dB SCR Code Amplitude dB 80 Carrier 1 60 Carrier 2 40 200 150 100 Frequency MHz C Carrier 3 f TSW3100 Control master LVDS Two s Comp C Carrier 4 79 slave cmos Offset Bin ocan us 466 MSB Justif 18b QDAC C Reverse 192 168 1123 2w Serial YDS C Bit Reverse v2 7 c 2005 2010 Texas Instruments Figure 15 TSW3100 GUI Configuration for Generating a WCDMA Signal for DAC3482 SLAUS36 March 201 1 DAC3484 DAC3482 EVM 17 Submit Documentation Feedback 2011 Texas Instruments Incorporated Evaluation Board Kit Important Notice Texas Instruments TI provides the enclosed product s under the following conditions This evaluation board kit is intended for use for ENGINEERING DEVELOPMENT DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer use Persons handling the product s must have electronics training and observe good engineering practice standards As such the goods being provided are not intended to be complete in terms of required design marketing
10. 100 Quick Start Operation Reference operation DAC348x higher the TSW3100 User s Guide for more detailed explanations of the TSW3100 set up and This document assumes the TSW3100 software is installed and functioning properly The needs TSW3100 operating software version 2 5 or higher with TSW3100 board Rev D or CommsSignalPattern Setup from Default Configuration WCDMA Change Interpolation value to DAC Clock Rate Interpolation 3 84 i e 1228 8 4 3 84 80 Enter desired Offset Frequency i e 30 MHz for each desired carrier e Select e Check the 16b QDAC output button the LOAD and Run box Press the green Create button SLAUS36 March 201 1 DAC3484 DAC3482 EVM 9 Submit Documentation Feedback 2011 Texas Instruments Incorporated TEXAS INSTRUMENTS Basic Test Procedure www ti com TSW3100_CommSignalPattern_v2p7 m Test Models Signal Type Signal Characteristics 64ch Complex 3 84 Chiprate MSPS 3 j C max size INSTRUMENTS ni C Complex IF 80 Interpolation INT 095 Bj v time offset TM5 30ch Random Seed 2 C Invert oe Ti 1 0 dualRF Factory only Res BW 30000 Hz ime ms Center Frequency TDSCDMA O Real 300 Vector size K e ExactFreq Display Options CCDF plot C Ext FFT Plot 30 ResBW kHz E ex e Carriers o
11. 5 Control DX wake up Reset USB Port FIFO SIF Control Input Format Parity Version 1 FIFO enabled Serial interface 3 pin v Format 2 s complement Parity Style odd z FIFO offset 4 Reverse bus normal Parity Check disabled FIFO Input Sync FRAME v SIF S Ril Input data 16 Bit Single Mode Block Parity disabled 9 FIFO Output Sync OSTR v SIF TXENABLE Enable Constant Input Data Formatter Sync FRAME v Constant Input 25000 3 LVDS delay PLL Settings Temperature sensor data ps 0 PLL enabled PLL Output PLL reset v x _ Prescaler 3 Fref 1228 8 PLL Sleep m v Pee em Clock ps 160 r 12288 Syne PLL dividers Data Routing Charge Pump Single aa FCO 3686 4 4 Bias OpAmp Off ml v Word in 0 v M 16 4 PFD MHz 76 8 4 v Fuse Sleep WordinB 1 v N 16 Stability P m 48 13 Pu Lock word in C 2 v 5 4 PLLLF Voltage Word in D 3 F Freq Tune Coarse 35 Y 9 0 10 20 30 40 50 63 Figure 2 Input Control Options SLAU336 March 2011 DAC3484 DAC3482 EVM 3 Submit Documentation Feedback 2011 Texas Instruments Incorporated TEXAS INSTRUMENTS Software Control www ti com 2 2 1 1 FIFO allows the configuration of the FIFO and FIFO sync sources LV
12. DS delay provides internal delay of either the LVDS DATA or LVDS DATACLK to help meet the input setup hold time Data Routing provides flexible routing of the A B and D sample input data to the appropriate digital path Note the DAC3482 does not support this mode Control provides control of the Serial Interface 3 wires or 4 wires and Serial Interface Sync SIF Input Format provides control of the input data format i e 2 s complement or offset binary Parity provides configuration of the parity input PLL Settings provides configuration of the on chip PLL circuitry Temperature Sensor provides temperature monitoring of DAC3484 2 die temperature LVDS Delay Settings The TSW3100 pattern generator sends out LVDS DATA and DATACLK as edge aligned signal The following options can be implemented to meet the minimum setup and hold time of DAC348x data latching 2 2 1 2 Set the on chip LVDS DATACLOCK delay Typical setting of 160ps or more will help meet the timing requirement for most of the TSW3100 DAC348x EVM setup This LVDS DATACLOCK delay does not account for additional PCB trace to trace delay variation only the internal DATACLK delay Modify the external LVDS DATACLK PCB trace delay Additional trace length on the bottom side of the PCB can be added to the LVDS DATACLK PCB trace length Set SJP9 SJP10 SUP11 and SJP12 to 2 3 position for approximately 220ps of trace delay PLL Settings PLL Set
13. Interpolation Clock frequency control is determined by register values in the CDCE62005 Control tab Please refer to the CDCE62005 datasheet for detailed explanations of the register configuration to change the clock frequency The following CDCE62005 outputs are critical to proper operation of the DAC348x e Y1 DAC348x FIFO OSTR clock The clock rate for this should be at least F Interpolation 8 for DAC3484 mode and DAC3482 mode O The whole OSTR clock equation needs to take account of both the Y1 CDCE62005 clock divider ratio and the additional CDCP1803 divide by 2 clock divider O This OSTR signal can be a slower periodic signal or a pulse depending on the application O Note The FIFO OSTR clock should be disabled when the DAC348x is configured in PLL mode e Y2 DAC348x DAC sampling clock If the DAC348x is configured for internal PLL mode this will be the reference clock input for the PLL block e TSW3100 FPGA clock The clock rate for this should be F interpolation 2 for DAC3484 mode and F p interpolation 4 for DAC3482 mode SLAU336 March 2011 DAC3484 DAC3482 EVM 7 Submit Documentation Feedback 2011 Texas Instruments Incorporated Basic Test Procedure 2 2 5 2 2 6 3 1 8 TEXAS INSTRUMENTS www ti com Register Control e Send All Sends the register configuration to all devices e Read All Reads register configuration from DAC348x device e Load Regs Load a register file for all device
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15. VM Connect the PC s Ethernet port to J13 Ethernet port of the TSW3100 The cable should be a standard cross over Cat5e Ethernet cable C3484 EVM Connect J13 connector of DAC348x EVM to J74 connector of TSW3100 EVM Connect 6V to the J18 Power In jack of the DAC3484 EVM Connect PC s USB port to J14 USB port of the DAC3484 EVM The cable should be a standard A to mini B connector cable Provide a 1 5Vrms 1 25GHz max Clock at J9 CLKIN SMA port of DAC3484 EVM Provide 12dBm max 350MHz to 4GHz LO source at J19 or J22 port of the DAC3484 EVM This is to provide the LO source to the TRF3703 15 modulators Connect the RF output port of J20 or J21 to the spectrum analyzer C3482 EVM Repeat steps 1 to 4 of DAC3484 EVM connection Provide 12dBm max 350MHz to 4GHz LO source at J24 port of the DAC3484 EVM This is to provide the LO source to the TRF3703 15 modulators Connect the RF output port of J23 to the spectrum analyzer C3484 2 EVM jumpers make sure the following jumpers are at their default setting JP6 on pin 1 2 JP4 on pin 2 3 JP5 on pin 1 2 JP2 on pin 1 2 JP3 on pin 2 3 JP1 and JP8 should be installed JP12 normally can be set in 1 2 position If 5V supply is used to bias the DAC to modulator interface then J12 needs to be in 2 3 position prior to the 6V power supply connection Once the 6V power supply is connected then J12 can be in 1 2 position to start the 5V sequence 3 8 TSWS
16. and or manufacturing related protective considerations including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards This evaluation board kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility restricted substances RoHS recycling WEEE FCC CE or UL and therefore may not meet the technical requirements of these directives or other related directives Should this evaluation board kit not meet the specifications indicated in the User s Guide the board kit may be returned within 30 days from the date of delivery for a full refund THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES EXPRESSED IMPLIED OR STATUTORY INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE The user assumes all responsibility and liability for proper and safe handling of the goods Further the user indemnifies TI from all claims arising from the handling or use of the goods Due to the open construction of the product it is the user s responsibility to take any and all appropriate precautions with regard to electrostatic discharge EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES TI currently deals with a variety of customers for p
17. arch 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated TEXAS INSTRUMENTS www ti com Optional Configuration E z229 M nes um LY Oc c OE NM LL Del Pm Pm Marte C490 Be Mese Pd Ca x ac OK or Qc exc gt de L 38551 33 Dan 0709 8209 82082 134 136 oy Figure 11 Locations of DAC348x to Transformer Output Jumper Locations Provide the clock input 1228 8 MHz at 1 5Vrms at J9 SMA connector of the DAC3484 EVM Turn on power to the board and press the reset button on the EVM Press the Reset USB Port button in GUI and verify USB communication Switch to the INPUT tab of GUI Click LOAD REGS browse to the installation folder and load example file DAC3484_FDAC_1228p8MHz_4xint_NCO_30MHz_QMCon txt This file contains settings for 4x interpolation with the DAC3484 running at 1228 8MSPS Load this file and wait a couple of seconds for the settings to go into effect Verify the spectrum using the Spectrum Analyzer at the four DAC outputs of the DAC EVM J7 J6 J3 and J2 Toggle the SIF SYNC button to sync the appropriate digital blocks if example file with NCO setting is used SLAU336 March 201 1 DAC3484 DAC3482 EVM 13 Submit Documentation Feedback 2011 Texas Instruments Incorporated TEXAS INSTRUMENTS Optional Configuration www ti com Per he i ee ULL e 177 LIII
18. basic user s guide for the DAC3484 2 EVM Revision D The EVM provides a basic platform to evaluate the DAC3484 and DAC3482 which are a family of 1 25GSPS up to 16x interpolation 16 bit high speed digital to analog converters The DAC3484 is a quad channel DAC and the DAC3482 is a dual channel DAC The EVM includes the CDCE62005 clocking source which provides the clocks required for the DAC and the pattern generator The on board TRF3703 15 modulators provide on board IF to RF upconversion for basic transmitter evaluation This EVM is ideally suited for mating with the TSW3100 pattern generation card for evaluating WCDMA LTE or other high performance modulation schemes 1 2 EVM Block Diagram Figure 1 shows the configuration of the EVM with the TSW3100 used for pattern generation Ext CLK Input 1 5 Vrms Single Ended 1 25GHz Max Primary Reference LVPECL AC coupled 19 2 MHz Reference LVCMOS Level Secondary Reference for CDCE62005 PLL Mode 19 2MHz PRI TCXO SEC EX CLK Output CDCE62005 FPGA CLK is 10 TSW3100 3 a Default TRF3703 15 OSTR_CLK LVPECL AC Coupled DAC_CLK LVPECL AC Coupled LVPECL DC coupled Y1 Output DATA DATA_CLK FRAME SYNC PARITY ns LO LVDS DC Coupled 123 RF TRF3703 15 DAC348X Power Supply Circuits Default TRF3703 15 Output 7 q 5 Optional DAC Output Optional TRF3703
19. e pee 02 0 81400002 bled M amp N Settings 03 0 81040003 Pri Ref PreDivider 3 State Pri term Disabled Sin p Input Divider 04 0x00040004 FECLK Enabled 125 05 Ox29F01A55 Sec Ref PreDivider 3 State Sec term Disabled Feedback Divider 06 Ox44AF0006 07 0x165294A7 Cert INN ves Ref Divider 1 LVDS Failsafe Disable Feedback Divider 8 08 0 20001808 Clsec_Inn_ves FB Bypass Divider CDCE Output Settings Prescale 5 m YO Unused Y1 0STR Y2 FDAC__Y3 3100 Clk Y4 Ext EXT LP filter Settings in MHz 19 2 Select Disabled v Enabled Enabled Enabled v Disabled ExtLPSEL External LP Out Freq MHz Inf Source Primary Primary Primary Primary Primary C1 Settings 28pF YO MHz Inf Divider 1 v 32 1 v 8 v 8 v C2 Settings 148pF 1 1 Yi MHz Inf Output LVPECL LVPECL LVPECL 84 LVPECL LVCMOS R2 Settings 80 4k Y2 MHz Inf Phase v v v gt j C3 Settings 90 5p MHz Inf HSwing Disabled Disabled Disabled Disabled Disabled gt d R3 Settings 20k Y4 MHz Inf active ative active active active Ww rd PLL_LOCK n output active active active active active m Lock Window 8 step wider AUX OUTPUT Charge Pump 1 5mA AUXOUTPUTSEL AUXOUTEN ATEST Output2 L Disabled PLL Calibration Startup mode ee Figure 6 CDCE62005 Tab Configured for 4x
20. j TEXAS User s Guide SLAU336 March 2011 INSTRUMENTS DAC3484 DAC3482 EVM Contents 1 INTODUCTION 2 1 1 el cleanin ead sie wa eed ede le ean a eae ade eed 2 1 2 EVM E ERE EX 2 SoftWare yeaa niet tee wins eteeurada cies 3 2 1 Installation Instructions I Im mm mnm Hm e nme 3 2 2 Software Operation d 3 Basic Test Procedure niue auta Ut asa 8 3 1 Test Block Diagrami 8 3 2 Test Set Up Connection 9 3 3 TSW3100 Quick Stant ES 9 3 4 DAC348x Software Quick Start Guide 10 4 Optional Configuration 25 2 e pui a aa 12 4 1 Configuring and Testing the DAC3484 Transformer Coupled Output 12 4 2 Using the DAC3482 or Configuring DAC3484 in DAC3482 mode 15 List of Figures 1 DAC3484 DAC3482 EVM Block Diagram
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22. on in this mode e Clock Divider Sync allows the syncing of the internal divided down clocks using either Frame Sync or OSTR signal Enable the divider sync as part of the initialization procedure or resynchronization procedure e Group Delay allows adjustment of group delay for each 1 9 channel This is useful for wideband sideband suppression e Offset Adjustment allows adjustment of DC offset to minimize the LO feed through of the modulator output This section requires sync for proper operation The sync options are listed below REGWR auto sync from SIF register write O OSTR sync from the external LVPECL OSTR signal Clock divider sync must be enabled with OSTR set as sync source O SYNC sync from the external LVDS SYNC signal O SIF SYNC sync from SIF Sync Uncheck and check the SIF Sync button for sync event e Adjustment allows adjustment of the gain and phase of the channel to minimize sideband power of the modulator output REGWR auto sync from SIF register write OSTR sync from the external LVPECL OSTR signal Clock divider sync must be enabled with OSTR set as sync source O SYNC sync from the external LVDS SYNC signal O SIF SYNC sync from SIF Sync Uncheck and check the SIF Sync button for sync event SLAU336 March 2011 DAC3484 DAC3482 EVM 5 Submit Documentation Feedback 2011 Texas Instruments Incorporated Software Control TEXAS INSTRUMENTS www ti com e NCO all
23. opriate digital blocks if example file with NCO setting is used 10 DAC3484 DAC3482 EVM SLAUS336 March 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated 13 TEXAS INSTRUMENTS www ti com Basic Test Procedure 2 x i 1 BR FWE Power 12 82 dBm PA Lower 73 01 Upper F 3002 LE dd Lower 77 76 Upper eg V AB Baseband 30MHz NCO 30MHz with NCO Gain disabled QMC Gain 1446 LO 1900MHz Figure 9 DAC3484 TRF3703 15 WCDMA Output SLAU336 March 2011 DAC3484 DAC3482 EVM 11 Submit Documentation Feedback 2011 Texas Instruments Incorporated TEXAS INSTRUMENTS Optional Configuration www ti com lane tds emt EP _ E oL LLL p 4 4 1 12 Power 5 865 dBm Lower 72 26 dB Upper I1 84 pie Lawes 79 95 dB Upper 7 9 96 dB Baseband 30MHz NCO disabled QMC Gain 1024 LO 1930MHz Figure 10 DAC3484 TRF3703 15 WCDMA Output Optional Configuration ee and Testing the DAC3484 Transformer Coupled Output Eight 0 Ohm resistors must be moved to configure the output of the DAC3484 to be 4 1 transformer coupled remove these resistors Horizontal position R19 R26 R33 R27 R35 R97 R76 R98 Install the following resistors Vertical position R162 R163 R17 R161 R8 R11 R1 See Figure 11 below for detail DAC3484 DAC3482 EVM SLAUS36 M
24. ows fine mixing of the I Q signal The procedure to adjust the NCO mixing frequency are listed below Enter the DAC sampling frequency in Fsample 1 2 3 4 Sync the NCO block from the following options Enter the desired mixing frequency in both NCO freq_AB and NCO freq_CD Press Update freq REGWR auto sync from SIF register write Writing to either Phase OffsetAB or Phase OffsetCD can create a sync event OSTR sync from the external LVPECL OSTR signal Clock divider sync must be enabled with OSTR set as sync source Refer to the datasheet for OSTR period requirement SYNC sync from the external SYNC signal SIF SYNC sync from SIF Sync Uncheck and check the SIF Sync button for sync event 2 2 3 Output Control Options DAC3484 EVM Software Control w Input Digital Output Output Options Output AB Delay Output CD Delay 0 Data Routing Version 3 2 Advanced CDCE62005 Control up Reset USB Port DAC Gain Output Shutoff __ Complement A disabled DACA Sleep DAC Gain 10 a DACCLK Gone disabled E Complement disabled C DACE Sleep mes Gr BH ra ed E s DAC one isable 0 Complement disabled Sleep s Complement D disabled CI DACD Sleep FIFO Collision disabled DACA Decoder Thermometer e Clock monitor sync disabled Word out A 0 Word OutB 1 PE Word OutC 2 M Word outD 3 M Figure 5 Output Control Options e O
25. roducts and therefore our arrangement with the user is not exclusive TI assumes no liability for applications assistance customer product design software performance or infringement of patents or services described herein Please read the User s Guide and specifically the Warnings and Restrictions notice in the User s Guide prior to handling the product This notice contains important safety information about temperatures and voltages For additional information on TI s environmental and or safety programs please contact the TI application engineer or visit www ti com esh No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine process or combination in which such TI products or services might be or are used FCC Warning This evaluation board kit is intended for use for ENGINEERING DEVELOPMENT DEMONSTRATION OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end product fit for general consumer use It generates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other environments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to
26. s Sample configuration files for common frequency plans are located in the install directory O Select Load Hegs button O Double click on the data folder O Double click on the desired register file O Click on Send All to ensure all of the values are loaded properly e Save Regs Saves the register configuration for all devices Miscellaneous Settings e Reset USB Toggle this button if the USB port is not responding This generates a new USB handle address O Note It is recommended that the board be reset after every power cycle and the reset usb button on the GUI be clicked e Exit Stops the program Basic Test Procedure This section outlines the basic test procedure for testing the EVM Test Block Diagram The test set up for general testing of the DAC348x with the TSW3100 pattern generation card is shown in Figure 7 Ethernet Signal Generator CLK Source USB Mini B Cross over Ethernet Cable Spectrum Analyzer TSW3100 Pattern Generator Signal Generator LO Source Figure 7 Test Set up Block Diagram DAC3484 DAC3482 EVM SLAUS36 March 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Basic Test Procedure 3 2 Test Set Up Connection e TSW3100 Pattern Generator 1 2 e DA 1 2 3 4 5 6 e DA 1 2 3 e DA NO Of WD Connect 5V power supply to J9 5V_IN jack of the TSW3100 E
27. tings PLL enabled PLL Output PLL reset Prescaler 3 Fref 1228 8 Sleep Bias Tune 1 FDAC MHz 1228 8 C Sync PLL dividers Charge Pump Single FWCO MHz 3686 4 Bias OpAmp Off M 16 5 PED MHz 76 8 Fuse Sleep 16 Stability P M 48 3 PLL Lock Freq Tune Coarse ss 9 4 PLL LF Voltage 010 20 30 40 50 63 Figure 3 PLL Configuration Follow the steps below to configure the PLL Enable PLL Uncheck PLL reset and PLL sleep Set M and N ratio such that Fpac M N xFref Set the prescaler such that the Fpaoxprescaler is within 3 3GHz and 4 0GHz Set VCO Bias Tune to 1 Charge Pump setting If stability PxM is less than 120 then set to Single If stability PxM is greater than 120 then set to Double or install external loop filter Adjust the Freq Tune coarse tune accordingly 4 DAC3484 DAC3482 EVM SLAUS36 March 2011 Submit Documentation Feedback 2011 Texas Instruments Incorporated TEXAS INSTRUMENTS www ti com Software Control 2 2 2 Digital Block Options DAC3484 EVM Software Control w Input Digtal Output Advanced CDCE62005 Control DX Wake up Digital Filters Offset Adjustment QMC NCO Interpolation 4x OffsetAB adjust enabled Correct enabled Enable Update freq lt C Digital Mixer Offset A 0 QMC Gain 1446 S
28. utput Options allows the configuration of reference output polarity and output delay e Data Routing provides flexible routing of the A B C and D digital path to the desired output channels Note The DAC3482 does not support this mode e DAC Gain configures the full scale DAC current and DAC3484 DAC3482 mode With Rbiaj resistor set at 1 28kQ DAC Gain 15 for 30mA full scale current DAC Gain 10 for 20mA full scale current default DAC3484 QDAC DAC3482 DDAC This allows the DAC3484 to be configured as DAC3482 see Using DAC3484 as DAC3482 section for detail DAC Sel Enable inner outputs of Ch B and Ch C as the DAC3482 output DAC Sel Enable outer outputs of Ch A and Ch D as the DAC3482 output Outer channels are grounded for the DAC3482 device e Output Shutoff On allows outputs to shut off wnen DACCLK GONE DATACLK GONE or FIFO COLLISION alarm event occurs DAC3484 DAC3482 EVM SLAUS36 March 201 1 Submit Documentation Feedback 2011 Texas Instruments Incorporated 1 TEXAS INSTRUMENTS www ti com Software Control 2 2 4 CDCE62005 DAC3484 EVM Software Control w Input Digital Output Advanced CDCE62005 Control Dk wake up Reset USB Port Control Advanced e 2 R Val CDCE62005 Input settings CDCE62005 VCO Settings aaa A ico sa 01 0 811 0001 Input Source Manual PRIIN Input Level LVPECL AC Tu S
29. where you can obtain information on other Texas Instruments products and application solutions Products Audio Amplifiers Data Converters DLP Products DSP Clocks and Timers Interface Logic Power Mgmt Microcontrollers RFID RF IF and ZigBee Solutions www ti com audio amplifier ti com dataconverter ti com www dlp com www ti com clocks interface ti com logic ti com power ti com microcontroller ti com www ti rfid com www ti com lprf Applications Communications and Telecom Computers and Peripherals Consumer Electronics Energy and Lighting Industrial Medical Security Space Avionics and Defense Transportation and Automotive Video and Imaging Wireless TI E2E Community Page www ti com communications www ti com computers www ti com consumer apps www ti com energy www ti com industrial www ti com medical www ti com security www ti com space avionics defense www ti com automotive www ti com video www ti com wireless apps Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2011 Texas Instruments Incorporated
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