Home

Texas Instruments 28xxx User's Manual

1. Z o nN 6 o Vouti A Buck 1 7 f 6 WN o Vout2 A Buck 2 7 gt i CVS kd o Vout3 A Buck 3 7 ka On ka o Vout4 A Buck HA 7 Applications to Power Topologies 75 K TEXAS INSTRUMENTS www ti com Controlling Multiple Buck Converters With Same Frequencies Figure 3 6 Buck Waveforms for Figure 3 5 Note Fpwm2 Fpwm1 Z 600 Z Z EPWM1A CB CB CB CB ky Y A v EPWM1B 500 500 EPWM2A CB CB CB CB A Y A v EPWM2B 76 Applications to Power Topologies SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Controlling Multiple Buck Converters With Same Frequencies Example 3 2 Code Snippet for Configuration in Figure 3 5 EPWM Module 1 config EPwmlRegs TBPRD 600 Period 1200 TBCLK counts EPwmlRegs TBPHS 0 Set Phase register to zero EPwmlRegs TBCTL bit CTRMODE TB_COUNT_UPDOWN Symmetrical mode EPwmlRegs TBCTL bit PHSEN TB_DISABLE Master module EPwmlRegs TBCTL bit PRDLD TB_SHADOW EPwmlRegs TBCTL bit SYNCOSEL TB_CTR_ZERO Syne down stream module EPwmlRegs CMPCTL bit SHDWAMODE CC_SHADOW EPwmlRegs CMPCTL bit SH
2. SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Controlling Zero Voltage Switched Full Bridge ZVSFB Converter Example 3 6 Code Snippet for Configuration in Figure 3 15 Set Phase reg to 300 1200 360 EPWM Module 1 config EPwmlRegs TBPRD 1200 Period EPwmlRegs CMPA 600 EPwmlRegs TBPHS 0 EPwmlRegs TBCTL bit CTRMODE TB_COUNT_UP EPwmlRegs TBCTL bit PHSEN TB_DISABLE Master EPwmlRegs TBCTL bit PRDLD TB_SHADOW EPwmlRegs TBCTL bit SYNCOSEL TB_CTR_ZERO EPwmlRegs CMPCTL bit SHDWAMODE CC_SHADOW EPwmlRegs CMPCTL bit SHDWBMODE CC_SHADOW EPwmlRegs CMPCTL bit LOADAMODE CC CTR ZERO EPwmlRegs CMPCTL bit LOADBMODE CC_CTR_ZERO EPwmlRegs AQCTLA bit ZRO AQ_SET Tf EPwmlRegs AQCTLA bit CAU AQ_CLEAR EPwmlRegs DBCTL bit MODE DB_FULL_ENABLE enable EPwmlRegs DBCTL bit POLSEL DB_ACTV_HIC Active EPwmlRegs DBFED 50 EPwmlRegs DBRED 70 RED EPWM Module 2 config EPwm2Regs TBPRD 1200 Period EPwm2Regs CMPA half CMPA 600 EPwm2Regs TBPHS 0 EPwm2Regs TBCTL bit CTRMODE TB_COUNT_UP EPwm2Regs TBCTL bit PHSEN TB_ENABLE EPwm2Regs TBCTL bit PRDLD TB_SHADOW EPwm2Regs TBCTL bit SYNCOSEL TB_SYNC_IN EPwm2Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm2Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm2Regs CMPCTL bit LOADAMODE CC_CTR_Z
3. 15 14 13 12 11 10 9 8 SOCBCNT SOCBPRD SOCACNT SOCAPRD R 0 R W 0 R 0 R W 0 7 4 3 2 1 0 Reserved INTCNT INTPRD R 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 24 Event Trigger Prescale Register ETPS Field Descriptions Bits Name Description 15 14 SOCBCNT ePWM ADC Start of Conversion B Event EPWMxSOCB Counter Register These bits indicate how many selected ETSEL SOCBSEL events have occurred 00 No events have occurred 01 1 event has occurred 10 2 events have occurred 11 3 events have occurred 13 12 SOCBPRD ePWM ADC Start of Conversion B Event EPWMxSOCB Period Select These bits determine how many selected ETSEL SOCBSEL events need to occur before an EPWMxSOCB pulse is generated To be generated the pulse must be enabled ETSEL SOCBEN 1 The SOCB pulse will be generated even if the status flag is set from a previous start of conversion ETFLG SOCB 1 Once the SOCB pulse is generated the ETPS SOCBCNT bits will automatically be cleared 00 Disable the SOCB event counter No EPWMxSOCB pulse will be generated 01 Generate the EPWMxSOCB pulse on the first event ETPS SOCBCNT 0 1 10 Generate the EPWMxSOCB pulse on the second event ETPS SOCBCNT 1 0 11 Generate the EPWMxSOCB pulse on the third event ETPS SOCBCNT 1 1 11 10 SOCACNT ePWM ADC Start of Conversion A Event EPWMxSOCA Counter Register These bits indicate how many selected ETSEL SOCASEL events
4. 20 eeeeeeeeeeeeeeeeeeeeeeeeeees 85 3 13 Control of a 3 Phase Interleaved DC DC Converter ss sss sse r e e eee e ereer 86 3 14 3 Phase Interleaved DC DC Converter Waveforms for Figure 3 13 sss se ee e e e eee eee 87 3 15 Controlling a Full H Bridge Stage Fpwm2 Few s esse sese ereer erer erer erer erer eee err 89 3 16 ZVS Full H Bridge Waveforms sisssssieierrr nisde onie a wee icuemautslate EAE 90 4 1 Time Base Period Register TBPHRDI sss esse sss esse ereer sees eee Keene neee ennenen 94 4 2 Time Base Phase Register TBPHBI ss sse ee er eee e seene eenn nenen eenn 94 4 3 Time Base Counter Register TBCTR sse eee 94 4 4 Time Base Control Register TBCTL essere eee 95 4 5 Time Base Status Register TL BSUS orto aaaea ea esinen E aa Ea a anaa E S 97 4 6 Counter Compare A Register COMPA sss eee eee eee renee 97 4 7 Counter Gompare B Register CMPB na vosa ara graag ER VE EE T Era ROE N EN AENEAN RNARO 98 4 8 Counter Compare Control Register CMPCTL 0cseceeeeeeeeeee eee e eee e eee ee eee ene e teen eeenee teen eeeeeeeeeenaeees 99 4 9 Action Qualifier Output A Control Register AQCTLA 0 ccceeee ects ee eee eee nese essen eee eeeeneeeaeeeeeeeeeaees 100 4 10 Action Qualifier Output B Control Register AQCTLB cceeeeeee eee 101 4 11 Action Qualifier Software Force Register AQSFRC cceceeeeeeeeeee eee e eee ee sees eeeeeeeeeeeeeeeeeeeeeeeeeenes 102 4 12 Action Qualifier Continuous Software Force R
5. The PWM output signals are made available external to the device through the GPIO peripheral described in the system control and interrupts guide for your device Trip zone signals TZ1 to TZ6 These input signals alert the ePWM module of an external fault condition Each module on a device can be configured to either use or ignore any of the trip zone signals The trip zone signals can be configured as asynchronous inputs through the GPIO peripheral Time base synchronization input EPWMxSYNCI and output EPWMxSYNCO signals The synchronization signals daisy chain the ePWM modules together Each module can be configured to either use or ignore its synchronization input The clock synchronization input and output signal are brought out to pins only for ePWM1 ePWM module 1 The synchronization output for ePWM1 EPWM1SYNCO is also connected to the SYNCI of the first enhanced capture module eCAP1 ADC start of conversion signals EPWMxSOCA and EPWMxSOCB Each ePWM module has two ADC start of conversion signals one for each sequencer Any ePWM module can trigger a start of conversion for either sequencer Which event triggers the start of conversion is configured in the Event Trigger submodule of the ePWM Peripheral Bus The peripheral bus is 32 bits wide and allows both 16 bit and 32 bit writes to the ePWM register file Introduction SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUME
6. EPwm3Regs TBCTL bit SYNCOSEL TB_SYNC_IN sync flow through EPwm3Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm3Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm3Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwm3Regs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwm3Regs AQCTLA bit CAU AQ_SET set actions for EPWM3A EPwm3Regs AQCTLA bit CAD AQ_CLEAR EPwm3Regs DBCTL bit MODE DB_FULL_ENABLE enable Dead band module EPwm3Regs DBCTL bit POLSEL DB_ACTV_HIC Active Hi complementary EPwm3Regs DBFED 50 FED 50 TBCLKs EPwm3Regs DBRED 50 RED 50 TBCLKs Run Time Note Example execution of one run time instant 500 adjust duty for output EPWM1A 600 adjust duty for output EPWM2A 700 adjust duty for output EPWM3A SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback Applications to Power Topologies 83 3 TEXAS INSTRUMENTS www ti com Practical Applications Using Phase Control Between PWM Modules 3 7 Practical Applications Using Phase Control Between PWM Modules So far none of the examples have made use of the phase register TBPHS It has either been set to zero or its value has been a don t care However by programming appropriate values into TBPHS multiple PWM modules can address another class of power topologies that rely on phase relationship between legs or stages for correct operation As described in the TB module section
7. Submit Documentation Feedback ePWM Submodules 21 Overview 22 Example 2 1 Constant Definitions Used in the Code Examples continued Wy TEXAS INSTRUMENTS www ti com define DB_ACTV_LO 0x3 PCCTL chopper control pesos E ea sees ees seseeages CHPEN bit define CHP_ENABLE 0x0 define CHP_DISABLE 0x1 CHPFREQ bits define CHP_DIV1 0x0 define CHP_DIV2 0x1 define CHP_DIV3 0x2 define CHP_DIV4 0x3 define CHP_DIV5 0x4 define CHP_DIV6 0x5 define CHP_DIV7 0x6 define CHP_DIV8 0x7 CHPDUTY bits define CHP1_8TH 0x0 define CHP2_8TH 0x1 define CHP3_8TH 0x2 define CHP4_8TH 0x3 define CHP5_8TH 0x4 define CHP6_8TH 0x5 define CHP7_8TH 0x6 TZSEL Trip zone Select ee ee CBCn and OSHTn bits define TZ_ENABLE 0x0 define TZ_DISABLE 0x1 TZCTL Trip zone Control ee TZA and TZB bits define TZ_HIZ 0x0 define TZ_FORCE_H 0x1 define TZ_FORCE_LO 0x2 define TZ_DISABLE 0x3 ETSEL Event trigger Select T E T E INTSEL SOCASEL SOCBSEL bits define R_ZERO 0x1 define TR_PRD 0x2 define TRU_CMPA 0x4 define TRD_CMPA 0x5 define ET_CTRU_CMPB 0x6 define ET_CTRD_CMPB Ox7 ETPS Event trigger Prescale fossa ee a a INTPRD SOCAPRD SOCBPRD bits define ET DISABLE 0x0 define ET_1ST 0x1 define ET_2ND 0x2 define ET_3RD 0x3 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENT
8. CC_SHADOW EPwm2Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm2Regs CMPCTL bit LOADAMODE CC CTR ZERO load on CTR Zero EPwm2Regs CMPCTL bit LOADBMODE CC CTR ZERO load on CTR Zero EPwm2Regs AQCTLA bit CAU AQ_SET set actions for EPWM2A EPwm2Regs AQCTLA bit CAD AQ_CLEAR EPwm2Regs DBCTL bit MODE DB_FULL_ENABLE enable Dead band module EPwm2Regs DBCTL bit POLSEL DB_ACTV_HIC Active Hi Complementary EPwm2Regs DBFED 20 FED 20 TBCLKs EPwm2Regs DBRED 20 RED 20 TBCLKs EPWM Module 3 config EPwm3Regs TBPRD 450 Period 900 TBCLK counts EPwm3Regs TBPHS 300 Phase 300 900 360 120 deg EPwm3Regs TBCTL bit CTRMODE TB_COUNT_UPDOWN Symmetrical mode EPwm3Regs TBCTL bit PHSEN TB_ENABLE Slave module EPwm2Regs TBCTL bit PHSDIR TB_UP Count UP on sync 240 deg EPwm3Regs TBCTL bit PRDLD TB_SHADOW EPwm3Regs TBCTL bit SYNCOSEL TB_SYNC_IN sync flow through EPwm3Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm3Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm3Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwm3Regs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwm3Regs AQCTLA bit CAU AQ_SET set actions for EPWM3Ai EPwm3Regs AQCTLA bit CAD AQ_CLEAR EPwm3Regs DBCTL bit MODE DB_FULL_ENABLE enable Dead band module EPwm3Regs DBCTL bit POLSEL DB_ACTV_HIC Active Hi complementary EPwm3Regs DBFED 20 FED 20 TBCLKs EPwm3Regs DBR
9. Do nothing action disabled 01 Clear force EPWMxB output low 10 Set force EPWMxB output high 11 Toggle EPWMxB output low output signal will be forced high and a high signal will be forced low 3 2 PRD Action when the counter equals the period Note By definition in count up down mode when the counter equals period the direction is defined as 0 or counting down 00 Do nothing action disabled 01 Clear force EPWMxB output low 10 Set force EPWMxB output high 11 Toggle EPWMxB output low output signal will be forced high and a high signal will be forced low 1 0 ZRO Action when counter equals zero Note By definition in count up down mode when the counter equals 0 the direction is defined as 1 or counting up 00 Do nothing action disabled 01 Clear force EPWMxB output low 10 Set force EPWMxB output high 11 Toggle EPWMxB output low output signal will be forced high and a high signal will be forced low SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback Registers 101 K TEXAS INSTRUMENTS www ti com Action Qualifier Submodule Registers Figure 4 11 Action Qualifier Software Force Register AQSFRC 15 l Reserved R 0 7 6 5 4 3 2 1 0 RLDCSF OTSFB ACTSFB OTSFA ACTSFA R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 11 Action Qualifier Software Force Register AQSFRC Field Description
10. Generate interrupt on ETPS INTCNT 1 1 third event Figure 4 25 Event Trigger Flag Register ETFLG 15 8 Reserved R 0 7 4 3 2 1 0 Reserved SOCB SOCA Reserved INT R 0 R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset SPRU791D November 2004 Revised October 2007 Registers 113 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Event Trigger Submodule Registers Table 4 25 Event Trigger Flag Register ETFLG Field Descriptions Bits Name Value Description 15 4 Reserved Reserved 3 SOCB Latched ePWM ADC Start of Conversion B EPWMxSOCB Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB The EPWMxSOCB output will continue to be generated even if the flag bit is set 2 SOCA Latched ePWM ADC Start of Conversion A EPWMxSOCA Status Flag Unlike the ETFLG INT flag the ERPWMxSOCA output will continue to pulse even if the flag bit is set 0 Indicates no event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCA The EPWMxSOCA output will continue to be generated even if the flag bit is set 1 Reserved Reserved 0 INT Latched ePWM Interrupt EPWMx_INT Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt EWPMx_INT was generated No further interrupts will be generated until the flag bit is cleared Up to one interrup
11. INSTRUMENTS www ti com Event Trigger Submodule Registers Figure 4 23 Event Trigger Selection Register ETSEL 15 14 12 11 10 8 SOCBEN SOCBSEL SOCAEN SOCASEL R W 0 R W 0 R W 0 R W 0 7 4 3 2 0 Reserved INTEN INTSEL R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 23 Event Trigger Selection Register ETSEL Field Descriptions Bits Name Value Description 15 SOCBEN Enable the ADC Start of Conversion B EPWMxSOCB Pulse 0 Disable EPWMxSOCB 1 Enable EPWMxSOCB pulse 14 12 SOCBSEL EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated 000 Reserved 001 Enable event time base counter equal to zero TBCTR 0x0000 010 Enable event time base counter equal to period TBCTR TBPRD 011 Reserved 100 Enable event time base counter equal to CMPA when the timer is incrementing 101 Enable event time base counter equal to CMPA when the timer is decrementing 110 Enable event time base counter equal to CMPB when the timer is incrementing 111 Enable event time base counter equal to CMPB when the timer is decrementing 11 SOCAEN Enable the ADC Start of Conversion A EPWMxSOCA Pulse 0 Disable EPWMxSOCA 1 Enable EPWMxSOCA pulse 10 8 SOCASEL EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated 000 Reserved 001 Enable event time base counter equal to zero TBCTR 0x0000 010 Enable event time base counter equa
12. TZSEL CBC1 to CBC6 TZCLR CBC 4 Clear TZSEL OSHT1 to OSHT6 EPWMxB Clear Latch a gt CBC trip event TZFLG CBC ane LK OSHT trip event Async Trip Set TZFLG OST Clear SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com Event Trigger ET Submodule Figure 2 37 Trip Zone Submodule Interrupt Logic TZFLG INT TZFLG CBC TZCLR INT TZCLR CBC CBC TZEINT CBC trip event TZFLG OST Zo Generate EPWMx_TZINT nora TZCLR OST PIE ulse when rE input 1 oT o OSHT TZEINT OST trip event 2 8 Event Trigger ET Submodule The key functions of the event trigger submodule are e Receives event inputs generated by the time base and counter compare submodules e Uses the time base direction information for up down event qualification e Uses prescaling logic to issue interrupt requests and ADC start of conversion at Every event Every second event Every third event e Provides full visibility of event generation via event counters and flags e Allows software forcing of Interrupts and ADC start of conversion The event trigger submodule manages the events generated by the time base submodule and the counter compare submodule to generate an interrupt to the CPU and or a start of conversion pulse to the ADC when a selected event occurs Figure 2 38 illustrates where the even
13. and frequency Fawn relationships for the up count down count and up down count time base counter modes when when the period is set to 4 TBPRD 4 The time increment for each step is defined by the time base clock TBCLk which is a prescaled version of the system clock SYSCLKOUT The time base counter has three modes of operation selected by the time base control register TBCTL Up Down Count Mode In up down count mode the time base counter starts from zero and increments until the period TBPRD value is reached When the period value is reached the time base counter then decrements until it reaches zero At this point the counter repeats the pattern and begins to increment Up Count Mode In this mode the time base counter starts from zero and increments until it reaches the value in the period register TBPRD When the period value is reached the time base counter resets to zero and begins to increment once again Down Count Mode In down count mode the time base counter starts from the period TBPRD value and decrements until it reaches zero When it reaches zero the time base counter is reset to the period value and it begins to decrement once again SPRU791D November 2004 Revised October 2007 ePWM Submodules 25 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com Time Base TB Submodule 2 2 3 1 26 Figure 2 3 Time Base Frequency and Period TEW 4 gt PRD For Up Count and Dow
14. described in reference is represented by the more simplified block diagram shown in Figure 3 1 This simplified eP WM block shows only the key resources needed to explain how a multiswitch power topology is controlled with multiple ePWM modules working together Figure 3 1 Simplified ePWM Module Syncin Phase reg EN bU a G I K EPWMxA EPWMxB CTR 0 o CTR CMPB o X o SyncOut 3 2 Key Configuration Capabilities The key configuration choices available to each module are as follows e Op tions for Syncin Load own counter with phase register on an incoming sync strobe enable EN switch closed Do nothing or ignore incoming sync strobe enable switch open Sync flow through SyncOut connected to Syncin Master mode provides a sync at PWM boundaries SyncOut connected to CTR PRD Master mode provides a sync at any programmable point in time SyncOut connected to CTR CMPB Module is in standalone mode and provides No sync to other modules SyncOut connected to X disabled e Options for SyncOut Sync flow through SyncOut connected to Syncin Master mode provides a sync at PWM boundaries SyncOut connected to CTR PRD Master mode provides a sync at any programmable point in time SyncOut connected to CTR CMPB Module is in standalone mode and provides No sync to other modules SyncOut connected to X disabled For each choice of SyncOut a module may also choose to load its own
15. describes the operation of the high resolution extension to the pulse width modulator HRPWM SPRU807 TMS320x28xx 28xxx Enhanced Capture eCAP Module Reference Guide describes the enhanced capture module It includes the module description and registers SPRU791D November 2004 Revised October 2007 Read This First 9 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com Related Documentation From Texas Instruments SPRU790 TMS320x28xx 28xxx Enhanced Quadrature Encoder Pulse eQEP Reference Guide describes the eQEP module which is used for interfacing with a linear or rotary incremental encoder to get position direction and speed information from a rotating machine in high performance motion and position control systems It includes the module description and registers SPRU074 TMS320x28xx 28xxx Enhanced Controller Area Network eCAN Reference Guide describes the eCAN that uses established protocol to communicate serially with other controllers in electrically noisy environments SPRU051 TMS320x28xx 28xxx Serial Communication Interface SCI Reference Guide describes the SCI which is a two wire asynchronous serial port commonly known as a UART The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non return to zero NRZ format SPRU059 TMS320x28xx 28xxx Serial Peripheral Interface SPI Reference Guide describes the SPI a
16. when the timer is incrementing when the timer is decrementing when the timer is incrementing when the timer is decrementing a we wre ra ePWM Submodules 65 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com Event Trigger ET Submodule The number of events that have occurred can be read from the interrupt event counter ETPS INTCNT register bits That is when the specified event occurs the ETPS INTCNT bits are incremented until they reach the value specified by ETPS INTPRD When ETPS INTCNT ETPS INTPRD the counter stops counting and its output is set The counter is only cleared when an interrupt is sent to the PIE When ETPS INTCNT reaches ETPS INTPRD the one of the following behaviors will occur e f interrupts are enabled ETSEL INTEN 1 and the interrupt flag is clear ETFLG INT 0 then an interrupt pulse is generated and the interrupt flag is set ETFLG INT 1 and the event counter is cleared ETPS INTCNT 0 The counter will begin counting events again e f interrupts are disabled ETSEL INTEN 0 or the interrupt flag is set ETFLG INT 1 the counter stops counting events when it reaches the period value ETPS INTCNT ETPS INTPRD e f interrupts are enabled but the interrupt flag is already set then the counter will hold its output high until the ENTFLG INT flag is cleared This allows for one interrupt to be pending while one is serviced Writing to the INTPRD bits will au
17. 2 VOVO IEW a ee EE E re ress usteme TEE EA EE ons 20 2 2 Time Base TB Submodule sss e eee 23 2 3 Counter Compare CC Submodule sss sees eee eee eee 32 2 4 Action Qualifier AQ Submodule ceceeeeeeeeeeeeeeeeeeeees 37 2 5 Dead Band Generator DB Submodule eeceeeeeeeeeeeees 50 2 6 PWM Chopper PC Submodule 2 cceeeeeeeeeeeeeeeeeeeeeeeees 55 27 Tnp Zone TZ Submodul sxs Saxe aa RR ERRER TRER 59 2 8 Event Trigger ET Submodule 0cceeeeeeeeee eee eeeeeeeeeeeeeees 63 SPRU791D November 2004 Revised October 2007 ePWM Submodules Submit Documentation Feedback Overview 2 1 Overview Wy TEXAS INSTRUMENTS www ti com Table 2 1 lists the seven key submodules together with a list of their main configuration parameters For example if you need to adjust or control the duty cycle of a PWM waveform then you should see the counter compare submodule in Section 2 3 for relevant details Table 2 1 Submodule Configuration Parameters Submodule Configuration Parameter or Option Time base TB Counter compare CC Action qualifier AQ Dead band DB PWM chopper PC Trip zone TZ Scale the time base clock TBCLKk relative to the system clock SYSCLKOUT Configure the PWM time base counter TBCTR frequency or period Set the mode for the time base counter count up mode used for asymmetric PWM count down mode used for
18. 4 Set TBCLKSYNC 1 2 2 5 Time base Counter Modes and Timing Waveforms 30 The time base counter operates in one of four modes e Up count mode which is asymmetrical e Down count mode which is asymmetrical e Up down count which is symmetrical e Frozen where the time base counter is held constant at the current value To illustrate the operation of the first three modes the following timing diagrams show when events are generated and how the time base responds to an ERPWMxSYNCI signal Figure 2 7 Time Base Up Count Mode Waveforms TBCTR 15 0 OxFFFF a Ir TBPRD value TBPHS value gt 0000 gt EPWMxSYNCI CTR_dir CTR zero fl CTR PRD CNT_max ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com TBCTR 15 0 a OxFFFF IF Figure 2 8 Time Base Down Count Mode Waveforms Time Base TB Submodule value value gt 0x000 EPWMxSYNCI T fl j CTR dir T IS CTR zero l fl j j CTR PRD T jl ll l jl CNT_max T Figure 2 9 Time Base Up Down Count Waveforms TBCTL PHSDIR 0 Count Down On Synchronization Event TBCNT 15 0 A OxFFFF a TBPRD TS value TBPHS gt value 0x0000 E EPWMxSYNCI l l CTR dir l l l CTR zero j jl CTR PRD ll ll CNT
19. 4 1 Time Base Period Register TBPRD Field Descriptions Bits Name Value Description 15 0 TBPRD 0000 These bits determine the period of the time base counter This sets the PWM frequency FFFF Shadowing of this register is enabled and disabled by the TBCTL PRDLD bit By default this register is shadowed s If TBCTL PRDLD 0 then the shadow is enabled and any write or read will automatically go to the shadow register In this case the active register will be loaded from the shadow register when the time base counter equals zero s If TBCTL PRDLD 1 then the shadow is disabled and any write or read will go directly to the active register that is the register actively controlling the hardware e The active and shadow registers share the same memory map address 15 Figure 4 2 Time Base Phase Register TBPHS 0 TBPHS R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 2 Time Base Phase Register TBPHS Field Descriptions Bits Name Value Description 15 0 TBPHS 0000 These bits set time base counter phase of the selected ePWM relative to the time base that is FFFF supplying the synchronization input signal s If TBCTL PHSEN 0 then the synchronization event is ignored and the time base counter is not loaded with the phase s If TBCTL PHSEN 1 then the time base counter TBCTR will be loaded with t
20. AQ_SET EPWM Module 2 config EPwm2Regs TBPRD 1400 EPwm2Regs TBPHS 0 EPwm2Regs TBCTL bit CTRMODE TB_COUNT_UP EPwm2Regs TBCTL bit PHSEN TB_DISABLE EPwm2Regs TBCTL bit PRDLD TB_SHADOW EPwm2Regs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwm2Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm2Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm2Regs CMPCTL bit LOADAMODE CC_CTR_ZERO EPwm2Regs CMPCTL bit LOADBMODE CC_CTR_ZERO EPwm2Regs AQCTLA bit PRD AQ_CLEAR EPwm2Regs AQCTLA bit CAU AQ_SET EPWM Module 3 config EPwm3Regs TBPRD 800 EPwm3Regs TBPHS 0 EPwm3Regs TBCTL bit CTRMODE TB_COUNT_UP EPwm3Regs TBCTL bit PHSEN TB_DISABLE EPwm3Regs TBCTL bit PRDLD TB_SHADOW EPwm3Regs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwm3Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm3Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm3Regs CMPCTL bit LOADAMODE CC_CTR_ZERO EPwm3Regs CMPCTL bit LOADBMODE CC_CTR_ZERO EPwm3Regs AQCTLA bit PRD AQ_CLEAR EPwm3Regs AQCTLA bit CAU AQ_SET Run Time Note Example execution of one run time aS Se SSS SSS aa Ss SS SS SS Ss SS SS SS SSS SSS5SS55 EPwmlRegs CMPA half CMPA 700 EPwm2Regs CMPA half CMPA 700 EPwm3Regs CMPA half CMPA 500 Period Set Phase register to zero Asymmetrical mode Phase loading disabled 1201 TBCLK counts load on CTR Zero load on CTR Zero Period 1401 TBCLK counts Set Pha
21. E 56 2 7 Trip Zone TZ SUDMOGUIS sssini n a a 9 0 0 Ee Heg 0 a 59 2 7 1 Purpose of the Trip Zone Submodule sss sese ee ecce ecce e renee 59 2 7 2 Controlling and Monitoring the Trip Zone SUDMOUIe ceeee eect ee eee ee neces e e e e ee 60 2 7 3 Operational Highlights for the Trip Zone SUDMOCUIC cecceeeeeeeee eee ee ee ee e 60 2 7 4 Generating Trip Event Interrupts cce eee e ee ce c c c eee e e e e e e e e e cece ereer 62 2 8 Event Trigger EM 2SUBMOGUIG sce wisjecls cciata ceierociciciamte nihete cele apeinare a E E aG 63 2 8 1 Operational Overview of the Event Trigger SUDMOUIe ece ee eee eee ee ee ee 64 3 Applications to Power Topologies sese sese ee ee eee reer 69 3 1 Overview of Multiple Modules css sss sss sec e e e e e eee cere ree eee 70 3 2 Key GContigtiration Capabilities sovitcitinccerchccdetdeii cease e a 70 3 3 Controlling Multiple Buck Converters With Independent Frequencies cs eee e e e e e e x K K e e e e x 71 SPRU791D November 2004 Revised October 2007 Contents 3 Submit Documentation Feedback 3 4 Controlling Multiple Buck Converters With Same Frequencies sss e e e e e e c e e e c e x e e e e K e e 75 3 5 Controlling Multiple Half H Bridge HHB Converters sss s e e e e e e ee ee c ee eee 78 3 6 Controlling Dual 3 Phase Inverters for Motors ACI and PMSM css e eee eee e eee 80 3 7 Practical Applications Using Phase Control Between PWM Modules 2eeeeeeeeeeeeeeeeeeeeeees 84 3 8 Control
22. List of Tables 1 1 ePWM Module Control and Status Register Set Grouped by Submodule s sss sss sse eee eee eee eeeeeeeeeeeeeeeee 18 2 1 Submodule Configuration Parameters see eee ecce ee c c r r eee eee eee eree 20 2 2 Time Base SubmoOdule RegistetS aisacistictcaean ivan toate vadedadeey EEEE E A EEN 24 2 3 Key Tim Base Signals visions eea vOe ORSR a i VE OK NNN Aa RRR KNN TOR aaa R ZN AT a KR R d 25 2 4 Counter Compare Submodule Registers sss eee c ecce eee ee eee eee 33 2 5 Counter Compare Submodule Key Signals cceeceeeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 34 2 6 Action Qualifier Submodule Redisiera sss ee ecce cere eee eee 37 2 7 Action Qualifier Submodule Possible Input Events sss sss se ee ee e e e e ee Keene 38 2 8 Action Qualifier Event Priority for Up Down Count Mode sss ees s sss sss eee eee eee ee e e e e eree 40 2 9 Action Qualifier Event Priority for Up Count Mode sss sss ss eee cesse ecce eee eee eee eee 40 2 10 Action Qualifier Event Priority for Down Count Mode ceeceeee eee eee eee eee e c ce eee e e eee eee 40 2 11 Behavior if CMPA CMPB is Greater than the Period secceeeeeeeeeeeee eee eee eee eee eee eeeeeeeeeeeeeeeeeeenees 41 2 12 Dead Band Generator Submodule Register cce esse esec eee 50 2 13 Classical Dead Band Operating Modes xas 959 cx siya YAEY SNE ZN XE R X KZU KESE E EEEE Y YR TVE S 52 2 14 Dead Band Delay Values in uS as a Function of DBFED and DBR
23. No PWM chopper Control Register 2 6 3 Operational Highlights for the PWM Chopper Submodule Figure 2 31 shows the operational details of the PWM chopper submodule The carrier clock is derived from SYSCLKOUT Its frequency and duty cycle are controlled via the CHPFREQ and CHPDUTY bits in the PCCTL register The one shot block is a feature that provides a high energy first pulse to ensure hard and fast power switch turn on while the subsequent pulses sustain pulses ensuring the power switch remains on The one shot width is programmed via the OSHTWTH bits The PWM chopper submodule can be fully disabled bypassed via the CHPEN bit SPRU791D November 2004 Revised October 2007 ePWM Submodules 55 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com PWM Chopper PC Submodule Figure 2 31 PWM Chopper Submodule Operational Details Bypass EPWMxA EPWMxA E shot gt Clk Pulse width SYSCLKOUT gt 8 PCCTL OSHTWTH l l Divider and PSCLK PCCTL duty control CHPEN PCCTL OSHTWTH PCCTL CHPFREQ Pulse width PCCTL CHPDUTY EPWMxB One PWMB_ch EPWMxA gt 2 6 4 Waveforms Figure 2 32 shows simplified waveforms of the chopping action only one shot and duty cycle control are not shown Details of the one shot and duty cycle control are discussed in the following sections Figure 2 32 Simple PWM Chopper Submodule Waveforms Showing Chopping Action On
24. October 2007 Revision History 117 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Appendix A Table A 1 Changes for Revision D continued Location Modifications Additions and Deletions Table 4 13 Modified the 10 description of the Dead Band Generator Control Register OUT_MODE field Table 4 14 Modified the bit numbers of the Dead Band Generator Rising Edge Delay Register Reserved field Table 4 15 Modified the bit numbers of the Dead Band Generator Falling Edge Delay Register Reserved field Section 2 8 1 Updated description of event counter Table 4 24 Updated INTPRD description Table 4 25 Updated the INTFLG INT bit description Table 4 27 Modified descriptions in the Event trigger Force register field descriptions 118 Revision History SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to TTS terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the
25. Register CMPB 0 CMPB R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 7 Counter Compare B Register CMPB Field Descriptions Bits Name Description 15 0 CMPB The value in the active CMPB register is continuously compared to the time base counter TBCTR When the values are equal the counter compare module generates a time base counter equal to counter compare B event This event is sent to the action qualifier where it is qualified and converted it into one or more actions These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers The actions that can be defined in the AQCTLA and AQCTLB registers include s Do nothing event is ignored s Clear Pull the EPWMxA and or EPWMxB signal low s Set Pull the EPWMxA and or EPWMxB signal high e Toggle the EPWMxA and or EPWMXxB signal Shadowing of this register is enabled and disabled by the CMPCTL SHDWBMODE bit By default this register is shadowed s If CMPCTL SHDWBMODE 0 then the shadow is enabled and any write or read will automatically go to the shadow register In this case the CMPCTL LOADBMODE bit field determines which event will load the active register from the shadow register s Before a write the CMPCTL SHDWBFULL bit can be read to determine if the shadow register is currently full s If CMPCTL SHDWBMODE 1 then
26. ZRO AQ_SET set actions for EPWM1A EPwm2Regs AQCTLA bit CAU AQ_CLEAR EPwm2Regs AQCTLB bit ZRO AQ_CLEAR set actions for EPWM1B EPwm2Regs AQCTLB bit CAD AQ_SET SSssss sss sss SSS SSS SS SS SSS SSS SSS SS SS SS SS SSS SS SSS SSS SSS 5555555 EPwmlRegs CMPA half CMPA 400 adjust duty for output EPWM1A amp EPWM1B EPwmlRegs CMPB 200 adjust point in time for ADCSOC trigger EPwm2Regs CMPA half CMPA 500 adjust duty for output EPWM2A amp EPWM2B EPwm2Regs CMPB 250 adjust point in time for ADCSOC trigger Controlling Dual 3 Phase Inverters for Motors ACI and PMSM The idea of multiple modules controlling a single power stage can be extended to the 3 phase Inverter case In such a case six switching elements can be controlled using three PWM modules one for each leg of the inverter Each leg must switch at the same frequency and all legs must be synchronized A master two slaves configuration can easily address this requirement Figure 3 9 shows how six PWM modules can control two independent 3 phase Inverters each running a motor As in the cases shown in the previous sections we have a choice of running each inverter at a different frequency module 1 and module 4 are masters as in Figure 3 9 or both inverters can be synchronized by using one master module 1 and five slaves In this case the frequency of modules 4 5 and 6 all equal can be integer multiples of the frequency for modules 1 2
27. an SOCA and SOCB pulse can be configured separately in the ETSEL SOCASEL and ETSEL SOCBSEL bits The possible events are the same events that can be specified for the interrupt generation logic 66 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Event Trigger ET Submodule Figure 2 42 Event Trigger SOCA Pulse Generator ETCLR SOCA ETFLG SOCA ETPS SOCACNT ETSEL SOCASEL Generate Clear CNT ETFRC SOCA soc 2 bit SOCA pulse Counter lt 0 when 4 _CTR Zero input 1 4 CTR PRD Inc CNT 0 CTRU CMPA ETSEL SOCAEN lt CTRD CMPA ETPS SOCAPRD a OTEDLeLIEE Figure 2 43 shows the operation of the event trigger s start of conversion B SOCB pulse generator The event trigger s SOCB pulse generator operates the same way as the SOCA Figure 2 43 Event Trigger SOCB Pulse Generator ETCLR SOCB ETFLG SOCB ETPS SOCBCNT ETSEL SOCBSEL Clear CNT Generate ETFRC SOCB SOC 2 bit SOCB pulse Counter 0 when CTR Zero input 1 Inc CNT CTR PRD 0 CTRU CMPA ETSEL SOCBEN CTRD CMPA CTRU CMPB ETPS SOCBPRD CTRD CMPB SPRU791D November 2004 Revised October 2007 ePWM Submodules 67 Submit Documentation Feedback 68 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback a TEXAS INSTRUMENTS Chapter 3 SPRU791
28. asymmetric PWM count up and down mode used for symmetric PWM Configure the time base phase relative to another ePWM module Synchronize the time base counter between modules through hardware or software Configure the direction up or down of the time base counter after a synchronization event Configure how the time base counter will behave when the device is halted by an emulator Specify the source for the synchronization output of the ePWM module Synchronization input signal Time base counter equal to zero Time base counter equal to counter compare B CMPB No output synchronization signal generated Specify the PWM duty cycle for output EPWMxA and or output EPWMxB Specify the time at which switching events occur on the EPWMxA or EPWMxB output Specify the type of action taken when a time base or counter compare submodule event occurs No action taken Output EPWMxA and or EPWMxB switched high Output EPWMxA and or EPWMxB switched low Output EPWMxA and or EPWMxB toggled Force the PWM output state through software control Configure and control the PWM dead band through software Control of traditional complementary dead band relationship between upper and lower switches Specify the output rising edge delay value Specify the output falling edge delay value Bypass the dead band module entirely In this case the PWM waveform is passed through without modification Create a chopping carrier frequen
29. counter with a new phase value on a Syncin strobe input or choose to ignore it i e via the enable switch Although various combinations are possible the two most common master module and slave module modes are shown in Figure 3 2 70 Applications to Power Topologies SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com Controlling Multiple Buck Converters With Independent Frequencies Figure 3 2 EPWM1 Configured as a Typical Master EPWM2 Configured as a Slave Ext Syncin optional Master Slave Phase reg Syncin Phase reg EN 0 4 O I gt EPWM1A 0 gt EPWM2A EPWM1B EPWM2B CTR 0 o CTR CMPB o x O SyncOut CTR 0 o CTR CMPB o x O 2 SyncOut 3 3 Controlling Multiple Buck Converters With Independent Frequencies One of the simplest power converter topologies is the buck A single ePWM module configured as a master can control two buck stages with the same PWM frequency If independent frequency control is required for each buck converter then one ePWM module must be allocated for each converter stage Figure 3 3 shows four buck stages each running at independent frequencies In this case all four ePWM modules are configured as Masters and no synchronization is used Figure 3 4 shows the waveforms generated by the setup shown in Figure 3 3 note that only three waveforms are show
30. dead band by having full control over edge placement using both the CMPA and CMPB resources of the ePWM module However if the more classical edge delay based dead band with polarity control is required then the dead band submodule described here should be used The key functions of the dead band module are e Generating appropriate signal pairs EPWMxA and EPWMxB with dead band relationship from a single EPWMXA input e Programming signal pairs for Active high AH Active low AL Active high complementary AHC Active low complementary ALC e Adding programmable delay to rising edges RED e Adding programmable delay to falling edges FED e Can be totally bypassed from the signal path note dotted lines in diagram 2 5 2 Controlling and Monitoring the Dead Band Submodule The dead band submodule operation is controlled and monitored via the following registers Table 2 12 Dead Band Generator Submodule Registers Register Name Address offset Shadowed Description DBCTL 0x000F No Dead Band Control Register DBRED 0x0010 No Dead Band Rising Edge Delay Count Register DBFED 0x0011 No Dead Band Falling Edge Delay Count Register 50 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com Dead Band Generator DB Submodule 2 5 3 Operational Highlights for the Dead Band Submodule The following sections provide the operational highlight
31. direction CNT_dir Figure 4 12 Action Qualifier Continuous Software Force Register AQCSFRC 15 8 Reserved R 0 Reserved CSFB CSFA R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset 102 Registers SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Dead Band Submodule Registers Table 4 12 Action qualifier Continuous Software Force Register AQCSFRC Field Descriptions Bits Name Value Description 15 4 Reserved Reserved 3 2 CSFB Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register To configure shadow mode use AQSFRC RLDCSF 00 Forcing disabled i e has no effect 01 Forces a continuous low on output B 10 Forces a continuous high on output B 11 Software forcing is disabled and has no effect 1 0 CSFA Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge In shadow mode a continuous force takes effect on the next TBCLK edge after a shadow load into the active register 00 Forcing disabled i e has no effect 01 Forces a continuous low on output A 10 Forces a continuous high on output A 11 Software forcing is disabled and has no
32. e Clear Low Set output EPWMxA or EPWMxB to a low level e Toggle If EPWMxA or EPWMxB is currently pulled high then pull the output low If EPWMxA or EPWMxB is currently pulled low then pull the output high e Do Nothing Keep outputs EPWMxA and EPWMxB at same level as currently set Although the Do Nothing option prevents an event from causing an action on the EPWMxA and EPWMxB outputs this event can still trigger interrupts and ADC start of conversion See the Event trigger Submodule description in Section 2 8 for details ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com Action Qualifier AQ Submodule Actions are specified independently for either output EPWMxA or EPWMxB Any or all events can be configured to generate actions on a given output For example both CTR CMPA and CTR CMPB can operate on output EPWMxA All qualifier actions are configured via the control registers found at the end of this section For clarity the drawings in this document use a set of symbolic actions These symbols are summarized in Figure 2 19 Each symbol represents an action as a marker in time Some actions are fixed in time zero and period while the CMPA and CMPB actions are moveable and their time positions are programmed via the counter compare A and B registers respectively To turn off or disable an action use the Do Nothing option it is the d
33. ePWM modules In this way you can set up a master time base for example ePWM1 and downstream modules ePWM2 ePWMx may elect to run in synchronization with the master See the Application to Power Topologies Chapter 3 for more details on synchronization strategies SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback ePWM Submodules 29 3 TEXAS INSTRUMENTS www ti com Time Base TB Submodule 2 2 4 Phase Locking the Time Base Clocks of Multiple ePWM Modules The TBCLKSYNC bit can be used to globally synchronize the time base clocks of all enabled ePWM modules on a device This bit is part of the DSPs clock enable registers and is described in the specific device version of the System Control and Interrupts Reference Guide listed in Section 1 When TBCLKSYNC 0 the time base clock of all ePWM modules is stopped default When TBCLKSYNC 1 all ePWM time base clocks are started with the rising edge of TBCLK aligned For perfectly synchronized TBCLKs the prescaler bits in the TBCTL register of each ePWM module must be set identically The proper procedure for enabling the ePWM clocks is as follows 1 Enable the individual ePWM module clocks This is described in the specific device version of the System Control and Interrupts Reference Guide listed in Section 1 2 Set TBCLKSYNC 0 This will stop the time base clock within any enabled ePWM module 3 Configure the prescaler values and desired ePWM modes
34. enabled by clearing the CMPCTL SHDWBMODE bit Shadow mode is enabled by default for both CMPA and CMPB If the shadow register is enabled then the content of the shadow register is transferred to the active register on one of the following events CTR PRD Time base counter equal to the period TBCTR TBPRD CTR Zero Time base counter equal to zero TBCTR 0x0000 Both CTR PRD and CTR Zero Which of these three events is specified by the CMPCTL LOADAMODE and CMPCTL LOADBMODE register bits Only the active register contents are used by the counter compare submodule to generate events to be sent to the action qualifier e Immediate Load Mode If immediate load mode is selected i e TBCTL SHADWAMODE 1 or TBCTL ISHADWBMODE 1 then a read from or a write to the register will go directly to the active register 2 3 4 Count Mode Timing Waveforms The counter compare module can generate compare events in all three count modes e Up count mode used to generate an asymmetrical PWM waveform e Down count mode used to generate an asymmetrical PWM waveform 34 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback A TEXAS INSTRUMENTS www ti com Counter Compare CC Submodule e Up down count mode used to generate a symmetrical PWM waveform To best illustrate the operation of the first three modes the timing diagrams in Figure 2 13 through Figure 2 16 show when event
35. for falling edge delayed signal 11 EPWMxB In from the action qualifier is the source for both rising edge delay and falling edge delayed signal 3 2 POLSEL Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 2 28 This allows you to selectively invert one of the delayed signals before it is sent out of the dead band submodule The following descriptions correspond to classical upper lower switch control as found in one leg of a digital motor control inverter These assume that DBCTL OUT_MODE 1 1 and DBCTL IN_MODE 0 0 Other enhanced modes are also possible but not regarded as typical usage modes 00 Active high AH mode Neither EPWMxA nor EPWM xgB is inverted default 01 Active low complementary ALC mode EPWMXA is inverted 10 Active high complementary AHC EPWMxB is inverted 11 Active low AL mode Both EPWMxA and EPWMxgB are inverted 1 0 OUT_MODE Dead band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the SO switch shown in Figure 2 28 This allows you to selectively enable or bypass the dead band generation for the falling edge and rising edge delay 00 Dead band generation is bypassed for both output signals In this mode both the EPWMxA and EPWMxB output signals from the action qualifier are passed directly to the PWM chopper submodule In this mode the POLSEL and IN_MODE bits have no effect 01 Disable rising edge delay The EPWMXA signa
36. have occurred 00 No events have occurred 01 1 event has occurred 10 2 events have occurred 11 3 events have occurred 112 Registers SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com Event Trigger Submodule Registers Table 4 24 Event Trigger Prescale Register ETPS Field Descriptions continued Bits Name Description 9 8 SOCAPRD 00 01 10 11 ePWM ADC Start of Conversion A Event EPWMxSOCA Period Select These bits determine how many selected ETSEL SOCASEL events need to occur before an EPWMxSOCA pulse is generated To be generated the pulse must be enabled ETSEL SOCAEN 1 The SOCA pulse will be generated even if the status flag is set from a previous start of conversion ETFLG SOCA 1 Once the SOCA pulse is generated the ETPS SOCACNT bits will automatically be cleared Disable the SOCA event counter No EPWMxSOCA pulse will be generated Generate the EPWMxSOCA pulse on the first event ETPS SOCACNT 0 1 Generate the EPWMxSOCA pulse on the second event ETPS SOCACNT 1 0 Generate the EPWMxSOCA pulse on the third event ETPS SOCACNT 1 1 7 4 Reserved Reserved 3 2 INTCNT 00 01 10 11 ePWM Interrupt Event EPWMx_INT Counter Register These bits indicate how many selected ETSEL INTSEL events have occurred These bits are automatically cleared when an interrupt pulse is generated If inte
37. high speed synchronous serial input output I O port that allows a serial bit stream of programmed length one to sixteen bits to be shifted into and out of the device at a programmed bit transfer rate SPRU721 TMS320x28xx 28xxx Inter Integrated Circuit I2C Reference Guide describes the features and operation of the inter integrated circuit 12C module that is available on the TMS320x280x digital signal processor DSP SPRU722 TMS320x280x 2801x 2804x Boot ROM Reference Guide describes the purpose and features of the bootloader factory programmed boot loading software It also describes other contents of the device on chip boot ROM and identifies where all of the information is located within that memory Tools Guides SPRU513 TMS320C28x Assembly Language Tools User s Guide describes the assembly language tools assembler and other tools used to develop assembly language code assembler directives macros common object file format and symbolic debugging directives for the TMS320C28x device SPRU514 TMS320C28x Optimizing C Compiler User s Guide describes the TMS320C28x C C compiler This compiler accepts ANSI standard C C source code and produces TMS320 DSP assembly language source code for the TMS320C28x device SPRU608 The TMS320C28x Instruction Set Simulator Technical Overview describes the simulator available within the Code Composer Studio for TMS320C2000 IDE that simulates the instruction
38. is proportional to CMPA Duty modulation for EPWMxB is set by CMPB and is active low that is the low time duty is proportional to CMPB Outputs EPWMxA and EPWMxB can drive independent power switches 00 WD gt Example 2 5 contains a code sample showing initialization and run time for the waveforms in Figure 2 24 Use the code in Example 2 1 to define the headers Example 2 5 Code Sample for Figure 2 24 Initialization Time 77 555555555 SF SSF SSeS SSeS EPwmlRegs TBPRD 600 Period 2x600 TBCLK counts EPwmlRegs CMPA half CMPA 400 Compare A 400 TBCLK counts EPwmlRegs CMPB 500 Compare B 500 TBCLK counts EPwmlRegs TBPHS 0 Set Phase register to zero EPwmlRegs TBCNT 0 clear TB counter EPwmlRegs TBCTL bit CTRMODE TB_UPDOWN Symmetric xEPwmlRegs TBCTL bit PHSEN TB_DISABLE Phase loading disabled xEPwmlRegs TBCTL bit PRDLD TB_SHADOW EPwmlRegs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwmlRegs TBCTL bit HSPCLKDIV TB_DIV1 TBCLK SYSCLKOUT EPwmlRegs TBCTL bit CLKDIV TB_DIV1 EPwmlRegs CMPCTL bit SHDWAMODE CC_SHADOW EPwmlRegs CMPCTL bit SHDWBMODE CC_SHADOW EPwmlRegs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwmlRegs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwmlRegs AQCTLA bit CAU AQ_SET EPwmlRegs AQCTLA bit CAD AQ_CLEAR EPwmlRegs AQCTLB bit CBU AQ_SET EPwml
39. kad Oo Slave Phase reg En VDC bus 0 RD gt EPWM2A tg T 0 Voutz CTR zero o EPWM2B Ke aS A A CTR CMPB o EADIE Xx o SyncOut 3E SR L kd v A A EPWM2B d O Applications to Power Topologies SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Controlling Multiple Half H Bridge HHB Converters Figure 3 8 Half H Bridge Waveforms for Figure 3 7 Note Here Fpwm2 Fpwmi 600 EPWM1A L ji A CB Z CA CB Z 4 A y 4 A v EPWM1B Pulse Center 500 500 250 250 1 i Z CB CA Z CB CA 4 A v 4 A v EPWM2A 1 CA CB Z CA cB z 4 A v 4 A v EPWM2B Pulse Center_ SPRU791D November 2004 Revised October 2007 Applications to Power Topologies 79 Submit Documentation Feedback Wy TEXAS INSTRUMENTS www ti com Controlling Dual 3 Phase Inverters for Motors ACI and PMSM 3 6 80 Example 3 3 Code Snippet for Configuration in Figure 3 7 Sssss sss Sess SSS SS SS SSS SSS SSS SS SS SS SS SS SSS SS SS SSS SSS SS SS SSS SSS SSSS5555 Config Sssss sss Ss SSS SSS SSS SSS SSS SSS SS SS SS SS
40. set of the C28x core SPRU625 TMS320C28x DSP BIOS Application Programming Interface API Reference Guide describes development using DSP BIOS Application Reports SPRAAMO Getting Started With TMS320C28x Digital Signal Controllers is organized by development flow and functional areas to make your design effort as seamless as possible Tips on getting started with C28x DSP software and hardware development are provided to aid in your initial design and debug efforts Each section includes pointers to valuable information including technical documentation software and tools for use in each phase of design SPRAAD5 Power Line Communication for Lighting Apps using BPSK w a Single DSP Controller presents a complete implementation of a power line modem following CEA 709 protocol using a single DSP SPRAA85 Programming TMS320x28xx and 28xxx Peripherals in C C explores a hardware abstraction layer implementation to make C C coding easier on 28x DSPs This method is compared to traditional define macros and topics of code efficiency and special case registers are also addressed Read This First SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com Related Documentation From Texas Instruments SPRA958 Running an Application from Internal Flash Memory on the TMS320F28xx DSP covers the requirements needed to properly configure applicati
41. specified in the TZCTL register is carried out immediately on the EPWMxA and or EPWMxB output Table 2 18 lists the possible actions In addition the one shot trip event flag TZFLG OST is set and a EPWMx_TZINT interrupt is generated if it is enabled in the TZEINT register and PIE peripheral The one shot trip condition must be cleared manually by writing to the TZCLR OST bit The action taken when a trip event occurs can be configured individually for each of the ePWM output pins by way of the TZCTL TZA and TZCTL TZB register bits One of four possible actions shown in Table 2 18 can be taken on a trip event ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Trip Zone TZ Submodule Table 2 18 Possible Actions On a Trip Event TZCTL TZA EPWMxA Comment and or and or TZCTL TZB EPWMxB 0 0 High Impedance Tripped 0 1 Force to High State Tripped 1 0 Force to Low State Tripped 1 1 No Change Do Nothing No change is made to the output Example 2 8 Trip Zone Configurations Scenario A _ A one shot trip event on T ZT pulls both EPWM1A EPWM1B low and also forces EPWM2A and EPWM2B high e Configure the ePWM1 registers as follows TZSEL OSHT1 1 enables TZT as a one shot event source for ePWM1 TZCTL TZA 2 EPWM1A will be forced low on a trip event TZCTL TZB 2 EPWM1B will be forced low on a trip event e Configu
42. will cause an EPWMx_TZINT PIE interrupt 0 Reserved Reserved The Peripheral Interrupt Expansion PIE module is described in the specific device version of the System Control and Interrupts Reference Guide listed in Section 1 Figure 4 20 Trip Zone Flag Register TZFLG 15 8 Reserved R 0 7 3 2 1 0 Reserved OST CBC INT R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 4 20 Trip Zone Flag Register TZFLG Field Descriptions Bits Name Value Description 15 3 Reserved Reserved OST Latched Status Flag for A One Shot Trip Event 0 No one shot trip event has occurred Indicates a trip event has occurred on a pin selected as a one shot trip source This bit is cleared by writing the appropriate value to the TZCLR register Table 4 21 CBC Latched Status Flag for Cycle By Cycle Trip Event 0 No cycle by cycle trip event has occurred Indicates a trip event has occurred on a pin selected as a cycle by cycle trip source The TZFLG CBC bit will remain set until it is manually cleared by the user If the cycle by cycle trip event is still present when the CBC bit is cleared then CBC will be immediately set again The specified condition on the pins is automatically cleared when the ePWM time base counter reaches zero TBCTR 0x0000 if the trip condition is no longer present The condition on the pins is only c
43. 0 PWM duty See the Using Enhanced Pulse Width Modulator ePWM Module for 0 100 Duty Cycle Control Application Report literature number SPRAAI1 Figure 2 20 shows how a symmetric PWM waveform can be generated using the up down count mode of the TBCTR In this mode 0 100 DC modulation is achieved by using equal compare matches on the up count and down count portions of the waveform In the example shown CMPA is used to make the comparison When the counter is incrementing the CMPA match will pull the PWM output high Likewise when the counter is decrementing the compare match will pull the PWM signal low When CMPA 0 the PWM signal is low for the entire period giving the 0 duty waveform When CMPA TBPRD the PWM signal is high achieving 100 duty SPRU791D November 2004 Revised October 2007 ePWM Submodules 41 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com Action Qualifier AQ Submodule When using this configuration in practice if you load CMPA CMPB on zero then use CMPA CMPB values greater than or equal to 1 If you load CMPA CMPB on period then use CMPA CMPB values less than or equal to TBPRD 1 This means there will always be a pulse of at least one TBCLK cycle in a PWM period which when very short tend to be ignored by the system 42 Mode Up Down Count TBPRD 4 CAU SET CAD CLEAR 0 100 Duty TBCNTR Direction CMPA 3 25 Duty Figure 2 20 Up Down Count Mode Symmetrical Wave
44. 3 also all equal Applications to Power Topologies SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Controlling Dual 3 Phase Inverters for Motors ACI and PMSM Figure 3 9 Control of Dual 3 Phase Inverter Stages as Is Commonly Used in Motor Control Ext Syncin optional Phase reg En 0 EPWM1A CTR zero EPWMIB CTR CMPB x o SyncOut m Slave Phase reg Syncin En P07 EPWM2A VAB VCD CTR zero ee S CTR CMPB VEF _ xX o SyncOut EPWM1B Ke EPWM2B H EPWM3B Ke 3 phase motor EPWM1A Kt EPWM2A Kt EPWM3A Ke lave Phase reg Syncin En P 0 EPWM3A 3 phase inverter 1 CTR zero EPWMSB CTR CMPB x o SyncOut lave Phase reg Syncin En 0 EPWM4A CTR zero o eee CTR CMPB X o ka ka L SyncOut EPWM4A Kt EPWM5A Kt EPWM6A Kt Phase reg Syncin ined En T EPWMS5A VCD VEF CTR zero ERWMSB CIR CMEB EPWM4B H EPWMS5B le EPWM6B La xX o SyncOut 3 phase motor Slave dl Ae Phase reg Syncin En p 0 EPWM6A CTR zero EPWMGB 3 phase inverter 2 CTR CMPB x o SyncOut SPRU791D November 2004 R
45. A ADC The event trigger submodule monitors various event conditions the left side inputs to event trigger submodule shown in Figure 2 40 and can be configured to prescale these events before issuing an Interrupt request or an ADC start of conversion The event trigger prescaling logic can issue Interrupt requests and ADC start of conversion at e Every event e Every second event e Every third event 64 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com Event Trigger ET Submodule Figure 2 40 Event Trigger Submodule Showing Event Inputs and Prescaled Outputs clear CTR Zero EPWMxINTn Event Trigger S PIE Module Logic CTR PRD CTRU CMPA ETSEL reg CTR CMPA CTRD CMPA EPWMxSOCA Direction CTRU CMPB ETPS reg qualifier count CTR CMPB CTRD CMPB ADC ETFLG reg clear ETCLR reg EPWMxSOCB CTR_dir ETFRC reg count The key registers used to configure the event trigger submodule are shown in Table 2 19 Table 2 19 Event Trigger Submodule Registers Register Name Address offset Shadowed Description ETSEL 0x0019 No Event trigger Selection Register ETPS 0x001A No Event trigger Prescale Register ETFLG 0x001B No Event trigger Flag Register ETCLR 0x001C No Event trigger Clear Register ETFRC 0x001D No Event trigger Force Register ETSEL This selects which of the po
46. A ZIIP 4 x X v A x x y A x E ae Fai a EPWMxA Z P CB CA Z 1P CB CA ZIIP j x y x Ai x v x All x os we a EPWMxB moO WD gt PWM period TBPRD 1 x Trgcik Duty modulation for EPWM xA is set by CMPA and is active high that is high time duty proportional to CMPA Duty modulation for EPWMxB is set by CMPB and is active high that is high time duty proportional to CMPB The Do Nothing actions X are shown for completeness but will not be shown on subsequent diagrams Actions at zero and period although appearing to occur concurrently are actually separated by one TBCLK period TBCTR wraps from period to 0000 Example 2 2 contains a code sample showing initialization and run time for the waveforms in Figure 2 21 Example 2 2 Code Sample for Figure 2 21 Initialization Time 77 5555555 SS SSF SSeS eS EPwmlRegs TBPRD 600 Period 601 TBCLK counts EPwmlRegs CMPA half CMPA 350 Compare A 350 TBCLK counts EPwmlRegs CMPB 200 Compare B 200 TBCLK counts EPwmlRegs TBPHS 0 Set Phase register to zero EPwmlRegs TBCTR 0 clear TB counter EPwmlRegs BCTL bit CTRMODE TB_UP EPwmlRegs TBCTL bit PHSEN TB_DISABLE Phase loading disabled EPwmlRegs TBCTL bit PRDLD TB_SHADOW EPwmlRegs BCTL bit SYNCOSEL TB_SYNC_DISABLE EPwmlRegs TBCTL bit HSPCLKDIV TB_DIV1 TBCLK SYSCLK EPwmlRegs BCTL bit CLKDIV TB_DIV1 EPwmlRegs CMPCTL bit SHDWAMODE
47. AQ_SET set actions for EPWM1A EPwmlRegs AQCTLA bit CAD AQ_CLEAR EPwmlRegs DBCTL bit MODE DB_FULL_ENABLE enable Dead band module EPwmlRegs DBCTL bit POLSEL DB_ACTV_HIC Active Hi complementary EPwmlRegs DBFED 50 FED 50 TBCLKs EPwmlRegs DBRED 50 RED 50 TBCLKs EPWM Module 2 config EPwm2Regs TBPRD 800 Period 1600 TBCLK counts EPwm2Regs TBPHS 0 Set Phase register to zero EPwm2Regs TBCTL bit CTRMODE TB_COUNT_UPDOWN Symmetrical mode EPwm2Regs TBCTL bit PHSEN TB_ENABLE Slave module EPwm2Regs TBCTL bit PRDLD TB_SHADOW EPwm2Regs TBCTL bit SYNCOSEL TB_SYNC_IN sync flow through EPwm2Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm2Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm2Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs AQCTLA bit CAU AQ_SET set actions for EPWM2A EPwm2Regs AQCTLA bit CAD AQ_CLEAR EPwm2Regs DBCTL bit MODE DB_FULL_ENABLE enable Dead band module EPwm2Regs DBCTL bit POLSEL DB_ACTV_HIC Active Hi complementary EPwm2Regs DBFED 50 FED 50 TBCLKs EPwm2Regs DBRED 50 RED 50 TBCLKs EPWM Module 3 config EPwm3Regs TBPRD 800 Period 1600 TBCLK counts EPwm3Regs TBPHS 0 Set Phase register to zero EPwm3Regs TBCTL bit CTRMODE TB_COUNT_UPDOWN Symmetrical mode EPwm3Regs TBCTL bit PHSEN TB_ENABLE Slave module EPwm3Regs TBCTL bit PRDLD TB_SHADOW
48. CC_SHADOW EPwmlRegs CMPCTL bit SHDWBMODE CC_SHADOW EPwmlRegs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwmlRegs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwmlRegs AQCTLA bit ZRO AQ_SET EPwmlRegs AQCTLA bit CAU AQ_CLEAR EPwmlRegs AQCTLB bit ZRO AQ_SET EPwmlRegs AQCTLB bit CBU AQ_CLEAR Ff Run Time JP 555555 Se SSeS See SE SS SS EPwmlRegs CMPA half CMPA DutylA adjust duty for output EPWM1A EPwmlRegs CMPB Duty1B adjust duty for output EPWM1B SPRU791D November 2004 Revised October 2007 ePWM Submodules 43 Submit Documentation Feedback 44 Wy TEXAS INSTRUMENTS www ti com Action Qualifier AQ Submodule Figure 2 22 Up Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Active Low TBCTR A TBPRD Value 1 N 1 P CA P CA P v 4 A 1 EPWMxA P CB P CB P A y 4 Y T T EPWMxB PWM period TBPRD 1 x Trgcik Duty modulation for EPWM xA is set by CMPA and is active low that is the low time duty is proportional to CMPA Duty modulation for EPWMxB is set by CMPB and is active low that is the low time duty is proportional to CMPB The Do Nothing actions X are shown for completeness here but will not be shown on subs
49. CMPA and CMPB are typically updated from their respective shadow registers once every period The user specifies when the update will take place either when the time base counter reaches zero or when the time base counter reaches period There are some cases when the action based on the new value can be delayed by one period or the action based on the old value can take effect for an extra period Some PWM configurations avoid this situation These include but are not limited to the following Use up down count mode to generate a symmetric PWM e f you load CMPA CMPB on zero then use CMPA CMPB values greater than or equal to 1 e If you load CMPA CMPB on period then use CMPA CMPB values less than or equal to TBPRD 1 This means there will always be a pulse of at least one TBCLK cycle in a PWM period which when very short tend to be ignored by the system Use up down count mode to generate an asymmetric PWM e To achieve 50 0 asymmetric PWM use the following configuration Load CMPA CMPB on period and use the period action to clear the PWM anda compare up action to set the PWM Modulate the compare value from 0 to TBPRD to achieve 50 0 PWM duty When using up count mode to generate an asymmetric PWM e To achieve 0 100 asymmetric PWM use the following configuration Load CMPA CMPB on TBPRD Use the Zero action to set the PWM anda compare up action to clear the PWM Modulate the compare value from 0 to TBPRD 1 to achieve 0 10
50. CTLB bit PRD AQ_CLEAR EPwmlRegs AQCTLB bit CBU AQ_SET Run Time fips 555 SSS eee eee Se Se Se SE Ee EPwmlRegs CMPA half CMPA DutylA adjust duty for output EPWM1A EPwmlRegs CMPB Duty1B adjust duty for output EPWM1B Figure 2 23 Up Count Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA TBCTR TBPRD value A 4 A l EPWMxA Z Z Z T T T EPWMxB PWM frequency 1 TBPRD 1 x Tac High time duty proportional to CMPB CMPA 00 WD gt Pulse can be placed anywhere within the PWM cycle 0000 TBPRD EPWM xB can be used to generate a 50 duty square wave with frequency 1 2 x TBPRD 1 x TBCLK Example 2 4 contains a code sample showing initialization and run time for the waveforms Figure 2 23 Use the code in Example 2 1 to define the headers SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback ePWM Submodules 45 Action Qualifier AQ Submodule Wy TEXAS INSTRUMENTS www ti com Example 2 4 Code Sample for Figure 2 23 Initialization Time ima aaa ae See aS SS Se SSeS PwmlRegs TBPRD 600 EPwmlRegs CMPA half CMPA 200 EPwmlRegs CMPB 400 EPwmlRegs TBPHS 0 EPwmlRegs TBCTR 0 EPwmlRegs TBCTL bit CTRMODE TB_UP EPwmlRegs TBCTL bit PHSEN TB_DISABLE EPw
51. CTRI 15 0 16 JL CTR CMPA cmpalis5 o 16 Digital comparator A J z CMPCTL CTR PRD Shadow CMPA enero Action load Compare A Active Reg CMPCTL Qualifier CMPA AQ Compare A Shadow Reg Ly NZ x Module CMPCTL LOADAMODE n0 16 CMPB 15 0 Digital comparator B CTR PRD oe CMPB _ CMPCTL SHDWBFULL load Compare B Active Reg CMPB Compare B Shadow Reg 1 CMPCTLISHDWBMODE CMPCTL LOADBMODE SPRU791D November 2004 Revised October 2007 ePWM Submodules 33 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com Counter Compare CC Submodule The key signals associated with the counter compare submodule are described in Table 2 5 Table 2 5 Counter Compare Submodule Key Signals Signal Description of Event Registers Compared CTR CMPA Time base counter equal to the active counter compare A value TBCTR CMPA CTR CMPB Time base counter equal to the active counter compare B value TBCTR CMPB CTR PRD Time base counter equal to the active period TBCTR TBPRD Used to load active counter compare A and B registers from the shadow register CTR ZERO Time base counter equal to zero TBCTR 0x0000 Used to load active counter compare A and B registers from the shadow register 2 3 3 Operational Highlights for the Counter Compare Submodule The counter compare submodule is responsible for generating two independent compare events based on t
52. Counter Compare Submodule sss ees s se e e e e e e c c e e c e 34 2 3 4 Count Mode Timing Waveforms ceceeeeeeeeeeeeeeee ence eeeeeeeeaeeeeeneeeeeenaeeaeeeeeneenaees 34 2 4 Action Qualifier AQ Submodule sss sss sese ee ecce eee neee eee 37 2 4 1 Purpose of the Action Qualifier Submodule esse ee eee eee eee c eee 37 2 4 2 Action Qualifier Submodule Control and Status Register Definitions seceeeeeeeeeeeeees 37 2 4 3 Action Qualifier Event Priority c ccceceeeeeeee nescence ence eeeeeeeeeeeneeseeeeeeeeeeeeeeeeneenenen 40 2 4 4 Waveforms for Common Configurations sss se eee e e e e eee e e e ee eee eee 41 2 5 Dead Band Generator DB Submodule 2 eee cce c ecce ee eee eee 50 2 5 1 Purpose of the Dead Band Submodule sss ssc eee ecce ecce serene 50 2 5 2 Controlling and Monitoring the Dead Band SUubMOdUIe 20 e cece cece eect teense eeeeeeeeees 50 2 5 3 Operational Highlights for the Dead Band SUDMOMUIe 0cce cece ecce ee e e ee e 51 2 6 PWM Chopper PG SubMOdUl iicssicceiticneiiumconnrbiiehcanmcrnatsaancanuedeimoeniobbabnongmay ebetautinde 55 2 6 1 Purpose of the PWM Chopper Submodule sese eee ecce eee e ee ee eee 55 2 6 2 Controlling the PWM Chopper Submodule cesses eee ee eee eee eee r eee 55 2 6 3 Operational Highlights for the PWM Chopper SUbMmoOduIe 20ceeeee e e e eee ee eee 55 2 0 4 WAVGTONIMS iis ascisiesidieie ad niaiacicinanpiaiasaisiaisteaceiz E E E E a EO EE
53. D November 2004 Revised October 2007 Applications to Power Topologies An ePWM module has all the local resources necessary to operate completely as a standalone module or to operate in synchronization with other identical ePWM modules Topic Page 3 1 Overview of Multiple Modules sss sese sees e essere eee 70 3 2 Key Configuration Capabilities cesse eee e eee ee eree e e eee rere eee 70 3 3 Controlling Multiple Buck Converters With Independent Frequencies 7 eet arcarant mas taeeccr a teneecn amen 71 3 4 Controlling Multiple Buck Converters With Same Frequencies 75 3 5 Controlling Multiple Half H Bridge HHB Converters 78 3 6 Controlling Dual 3 Phase Inverters for Motors ACI and PMSM 80 3 7 Practical Applications Using Phase Control Between PWM Modules a a ance cco e torte Aer Sasa aerate ica ren E tace ce ten semaecueracacace 84 3 8 Controlling a 3 Phase Interleaved DC DC Converter 85 3 9 Controlling Zero Voltage Switched Full Bridge ZVSFB Converter 89 SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback Applications to Power Topologies 69 3 TEXAS INSTRUMENTS www ti com Overview of Multiple Modules 3 1 Overview of Multiple Modules Previously in this user s guide all discussions have described the operation of a single module To facilitate the understanding of multiple modules working together in a system the ePWM module
54. DWBMODE CC_SHADOW EPwmlRegs CMPCTL bit LOADAMODE CC CTR ZERO load on CTR Zero EPwmlRegs CMPCTL bit LOADBMODE CC CTR ZERO load on CTR Zero EPwmlRegs AQCTLA bit CAU AQ_SET set actions for EPWM1A EPwmlRegs AQCTLA bit CAD AQ_CLEAR EPwmlRegs AQCTLB bit CBU AQ_SET set actions for EPWM1B EPwmlRegs AQCTLB bit CBD AQ CLEAR EPWM Module 2 config EPwm2Regs TBPRD 600 Period 1200 TBCLK counts EPwm2Regs TBPHS 0 Set Phase register to zero EPwm2Regs TBCTL bit CTRMODE TB_COUNT_UPDOWN Symmetrical mode EPwm2Regs TBCTL bit PHSEN TB_ENABLE Slave module EPwm2Regs TBCTL bit PRDLD TB_SHADOW EPwm2Regs TBCTL bit SYNCOSEL TB_SYNC_IN sync flow through EPwm2Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm2Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm2Regs CMPCTL bit LOADAMODE CC CTR ZERO load on CTR Zero EPwm2Regs CMPCTL bit LOADBMODE CC CTR ZERO load on CTR Zero EPwm2Regs AQCTLA bit CAU AQ_SET set actions for EPWM2A EPwm2Regs AQCTLA bit CAD AQ_CLEAR EPwm2Regs AQCTLB bit CBU AQ_SET set actions for EPWM2B EPwm2Regs AQCTLB bit CBD AQ_CLEAR Run Time Note Example execution of one run time instance SSS SSS SSS SSS SSS SSS SS SS SS SS SSS SSS SS SS SSS SSS SSS SSS SSS SSS SS SSS EPwmlRegs CMPA half CMPA 400 adjust duty for output EPWM1A EPwmlRegs CMPB 200 adjust duty for output EPWM1B EPwm2Regs CMPA half CMPA 500 adjust d
55. ED ceceeee eee ee eee eee e eee e 54 2 15 PWM Chopper Submodule ReQisters ssa r Oy SRN eee eeeeeeeeeeeeeeeeeeneeeeeeeeeeaeeneeeeeeeeeeeeeaeees 55 2 16 Possible Pulse Width Values for SYSCLKOUT 100 MHZ e eee ee e e e sete rere 57 2 17 Trip Zone SUBMOAUIE s TT TT 60 2 18 Possible Actions Ona Tip aT a a a woud S E a E A 61 2 19 Event Trigger Submodule Registers ceeceeeeeeeeee cece cece eee n ee eeeeeeeeeeeeeeeeeeeeeeeeeaeeeeeeeeeeeenaeeaeees 65 4 1 Time Base Period Register TBPRD Field Descriptions sese see e e e e e e eee eect e ee e e e ee eee 94 4 2 Time Base Phase Register TBPHS Field DeSCriptionS 0 sseceeeeee eee eee e e e ee eee 94 4 3 Time Base Counter Register TBCTR Field DeSCriptionS cceeeceeeeeee eee eee tees eee eee 94 4 4 Time Base Control Register TBCTL Field Descriptions eceeeeeee settee eens eee eee 95 4 5 Time Base Status Register TBSTS Field Descriptions eceeeeeee eee e eens e e e e sees eee eee 97 4 6 Counter Compare A Register CMPA Field Descriptions css esse see sete eee e e e ee eree 98 4 7 Counter Compare B Register CMPB Field Descriptions ceceeeeeee eee ener e e e ee eree 98 4 8 Counter Compare Control Register CMPCTL Field Descriptions sss sss sse e e e e e e esse ee e e tees eee eee 99 4 9 Action Qualifier Output A Control Register AQCTLA Field Descriptions sss sss sese ee e e e e e e e e e e e r e eee 100 4 10 Action Qualifier
56. ED 20 RED 20 TBCLKs Run Time Note Example execution of one run time instant EPwmlRegs CMPA half CMPA 285 adjust duty for output EPWMI1A EPwm2Regs CMPA half CMPA 285 adjust duty for output EPWM2A EPwm3Regs CMPA half CMPA 285 adjust duty for output EPWM3A 88 Wy TEXAS Applications to Power Topologies SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback Ww TEXAS INSTRUMENTS www ti com Controlling Zero Voltage Switched Full Bridge ZVSFB Converter 3 9 Controlling Zero Voltage Switched Full Bridge ZVSFB Converter SPRU791D November 2004 Revised October 2007 The example given in Figure 3 15 assumes a static or constant phase relationship between legs modules In such a case control is achieved by modulating the duty cycle It is also possible to dynamically change the phase value on a cycle by cycle basis This feature lends itself to controlling a class of power topologies known as phase shifted full bridge or zero voltage switched full bridge Here the controlled parameter is not duty cycle this is kept constant at approximately 50 percent instead it is the phase relationship between legs Such a system can be implemented by allocating the resources of two PWM modules to control a single power stage which in turn requires control of four switching elements Figure 3 16 shows a master slave module combination synchronized t
57. ERO if EPwm2Regs CMPCTL bit LOADBMODE CC_CTR_ZERO ff EPwm2Regs AQCTLA bit ZRO AQ_SET EPwm2Regs AQCTLA bit CAU AQ_CLEAR EPwm2Regs DBCTL bit MODE DB_FULL_ENABLE enable EPwm2Regs DBCTL bit POLSEL DB_ACTV_HIC Active EPwm2Regs DBFED 30 EPwm2Regs DBRED 40 RED Run Time Note Example execution of one run time instant sassss355 5555555555555 555555555555 55555555555 5555 5 555555555 EPwm2Regs TBPHS 1200 300 EPwmlRegs DBFED FED1_NewValue Update EPwmlRegs DBRED RED1_NewValue Update EPwm2Regs DBFED FED2_NewValue Update EPwm2Regs DBRED RED2_NewValue Update EPwmlRegs CMPB 200 adjust 1201 TBCLK counts Set 50 fixed duty for EPWM1A Set Phase register to zero Asymmetrical mode module Sync down stream module load on CTR Zero load on CTR Zero set actions for EPWM1A Dead band module Hi complementary FED 50 TBCLKs initially 70 TBCLKs initially 1201 TBCLK counts Set 50 fixed duty EPWM2A Set Phase register to zero initially Asymmetrical mode Slave module sync flow through load on CTR Zero load on CTR Zero set actions for EPWM2A Dead band module Hi complementary FED 30 TBCLKs initially 40 TBCLKs initially 90 deg ZVS transition interval ZVS transition interval ZVS transition interval ZVS transition interval point in time for ADCSOC trigger SPRU791D November 2004 Revised October 2007 Submit Documen
58. KOUT 010 Divide by 3 4 16 MHz at 100 MHz SYSCLKOUT 011 Divide by 4 3 12 MHz at 100 MHz SYSCLKOUT 100 Divide by 5 2 50 MHz at 100 MHz SYSCLKOUT 101 Divide by 6 2 08 MHz at 100 MHz SYSCLKOUT 110 Divide by 7 1 78 MHz at 100 MHz SYSCLKOUT 111 Divide by 8 1 56 MHz at 100 MHz SYSCLKOUT 4 1 OSHTWTH One Shot Pulse Width 0000 1 x SYSCLKOUT 8 wide 80 nS at 100 MHz SYSCLKOUT 0001 2 x SYSCLKOUT 8 wide 160 nS at 100 MHz SYSCLKOUT 0010 3x SYSCLKOUT 8 wide 240 nS at 100 MHz SYSCLKOUT 0011 4x SYSCLKOUT 8 wide 320 nS at 100 MHz SYSCLKOUT 0100 5x SYSCLKOUT 8 wide 400 nS at 100 MHz SYSCLKOUT 0101 6x SYSCLKOUT 8 wide 480 nS at 100 MHz SYSCLKOUT 0110 7x SYSCLKOUT 8 wide 560 nS at 100 MHz SYSCLKOUT 0111 8x SYSCLKOUT 8 wide 640 nS at 100 MHz SYSCLKOUT 1000 9x SYSCLKOUT 8 wide 720 nS at 100 MHz SYSCLKOUT 1001 10 x SYSCLKOUT 8 wide 800 nS at 100 MHz SYSCLKOUT 1010 11 x SYSCLKOUT 8 wide 880 nS at 100 MHz SYSCLKOUT 1011 12 x SYSCLKOUT 8 wide 960 nS at 100 MHz SYSCLKOUT 1100 13 x SYSCLKOUT 8 wide 1040 nS at 100 MHz SYSCLKOUT 1101 14 x SYSCLKOUT 8 wide 1120 nS at 100 MHz SYSCLKOUT 1110 15 x SYSCLKOUT 8 wide 1200 nS at 100 MHz SYSCLKOUT 1111 16 x SYSCLKOUT 8 wide 1280 nS at 100 MHz SYSCLKOUT 0 CHPEN PWM chopping Enable 0 Disable bypass PWM chopping function 1 Enable chopping function 4 6 Trip Zone S
59. KOUT 100 MHz 54 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com PWM Chopper PC Submodule 2 6 PWM Chopper PC Submodule Figure 2 30 illustrates the PWM chopper PC submodule within the ePWM module Figure 2 30 PWM Chopper Submodule oie Ee EPWMxINT a Sh i g Pe c Trigger CTR CMPA and EPWMxSOCA T CTR PRD JL CTR CMPB Interrupt ER et EPWMxSYNGCO ea CTR 0 JL CTR Dir EPWMxSOCB E CTR_Dir EPWMxA CTR CMPA JL Bag EPWMxB MUX gt TZ1 to TZ6 4 Counter Compare CC CTR CMPB JL EPWMxTZINT The PWM chopper submodule allows a high frequency carrier signal to modulate the PWM waveform generated by the action qualifier and dead band submodules This capability is important if you need pulse transformer based gate drivers to control the power switching elements 2 6 1 Purpose of the PWM Chopper Submodule The key functions of the PWM chopper submodule are e Programmable chopping carrier frequency e Programmable pulse width of first pulse e Programmable duty cycle of second and subsequent pulses e Can be fully bypassed if not required 2 6 2 Controlling the PWM Chopper Submodule The PWM chopper submodule operation is controlled via the registers in Table 2 15 Table 2 15 PWM Chopper Submodule Registers mnemonic Address offset Shadowed Description PCCTL 0x001E
60. L CTR_Dir EPWMxSOCB E CTR Dir EPWMxA JL chopper CTR CMPA Bag EPWMxB MUX gt TZ1 to TZ6 4 Counter Compare CC CTR CMPB JL EPWMxTZINT Each ePWM module is connected to six TZn signals TZT to TZ6 that are sourced from the GPIO MUX These signals indicate external fault or trip conditions and the ePWM outputs can be programmed to respond accordingly when faults occur 2 7 1 Purpose of the Trip Zone Submodule The key functions of the Trip Zone submodule are e Trip inputs TZT to TZ6 can be flexibly mapped to any ePWM module e Upon a fault condition outputs EPWMxA and EPWMxB can be forced to one of the following High Low High impedance No action taken e Support for one shot trip OSHT for major short circuits or over current conditions e Support for cycle by cycle tripping CBC for current limiting operation s Each trip zone input pin can be allocated to either one shot or cycle by cycle operation e Interrupt generation is possible on any trip zone pin e Software forced tripping is also supported e The trip zone submodule can be fully bypassed if it is not required SPRU791D November 2004 Revised October 2007 ePWM Submodules 59 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com Trip Zone TZ Submodule 2 7 2 Controlling and Monitoring the Trip Zone Submodule The trip zone submodule operation is controlled and monitored through the following registers Table 2 17
61. N Ea r 2 42 Event Trigger SOCA Pulse Generator eee c e e e e e e e e e e eee eee SPRU791D November 2004 Revised October 2007 List of Figures Submit Documentation Feedback 6 2 43 Event Trigger SOCB Pulse Generator eee e r r e e e e e eee eee eee eee 67 3 1 Simplified GRWM Module arenen a E E E EEE E ese faci 70 3 2 EPWM1 Configured as a Typical Master EPWM2 Configured as a Slave cesse ee e eee e e eee eee 71 3 3 Control of Four Buck Stages Here Fpwm Fpwmo Fewuat Fewog cesses eee ee e e e e c e eee e e e eee T2 3 4 Buck Waveforms for Figure 3 3 Note Only three bucks shown here sss sse e e e eee e e e e ee Ke 73 3 5 Control of Four Buck Stages Note Fewme N X EGwMil s sss ees e ecce e eee eee 75 3 6 Buck Waveforms for Figure 3 5 Note Fpwma Few sssssscss yyy sv vye cv evrscvyr vy rnr rrer syr s cry YY YYY X yy 76 3 7 Control of Two Half H Bridge Stages Fpwme N X Frwy sss ecce cece eee e e eee 78 3 8 Half H Bridge Waveforms for Figure 3 7 Note Here Fpwm2 Few Tess sss s ess e c ce ce e e ee e e e seen e eee 79 3 9 Control of Dual 3 Phase Inverter Stages as Is Commonly Used in Motor Control ss sss see ee eee eee eee c 81 3 10 3 Phase Inverter Waveforms for Figure 3 9 Only One Inverter SHOWN eee e e e ee e e e eee e c e e e eens eeeeeeeeeeeee 82 3 11 Configuring Two PWM Modules for Phase Controls sss esse s e e e e e e e e e eee e e e e e e 84 3 12 Timing Waveforms Associated With Phase Control Between 2 Modules
62. NTS www ti com Register Mapping Figure 1 3 ePWM Submodules and Critical Internal Signal Interconnects Time base TB TBPRD shadow 16 TBPRD active 16 CTR_PRD Sync in out select MUX So Si TBCTL SWFSYNC EPWMxSYNCO gt EPWMxSYNCI tL 4 Counter Nk kad cC L UP DWN TBCTL PHSEN J 16 bit JLCTR ZERO active CTR_Dir TBPHS active 16 control Counter compare CC CMPA active 16 CMPA shadow 16 16 CMPB active 16 Phase CTR PRD EPWMxTZINT trigger and EPWMxSOCA interrupt CMPB shadow 16 CTR ZERO TBCTL SWFSYNC software T forced sync EPWMxINT EPWMxSOCB EPWMxA EPWMxB TZ1 to TZ6 ete r Figure 1 3 also shows the key internal submodule interconnect signals Each submodule is described in detail in its respective section 1 3 Register Mapping The complete ePWM module control and status register set is grouped by submodule as shown in Table 1 1 Each register set is duplicated for each instance of the ePWM module The start address for each ePWM register file instance on a device is specified in the appropriate data manual SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback Introduction 17 Register Mapping 18 4i TEXAS INSTRUMENTS www ti com Table 1 1 ePWM Module Control and Status Reg
63. Output B Control Register AQCTLB Field Descriptions sss ss sse e e e e e e e e e ee e e e r e eee 101 4 11 Action Qualifier Software Force Register AQSFRC Field DeScriptionS cceeeeeeeeeeeeeeeeeeeeeeeeeees 102 4 12 Action qualifier Continuous Software Force Register AQCSFRC Field Descriptions ceeeeeeeeeees 103 4 13 Dead Band Generator Control Register DBCTL Field DeScriptionS eceeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 104 4 14 Dead Band Generator Rising Edge Delay Register DBRED Field Descriptions cce eee e ecce eee c c c ee e e e 105 4 15 Dead Band Generator Falling Edge Delay Register DBFED Field Descriptions 0cseeeeeeeeeeeeeeees 105 4 16 PWM Chopper Control Register PCCTL Bit Descriptions sss sss se e ee e eee ee e e e Kerer eee 105 4 17 Trip Zone Submodule Select Register TZSEL Field Descriptions ccs eee e e e e e e cess eee e e e e eee 107 4 18 Trip Zone Control Register TZCTL Field Descriptions sese sss esse c eee e e ereer 108 4 19 Trip Zone Enable Interrupt Register TZEINT Field Descriptions sss se e e e e r r eee eens e e e e K Ke K K x x e e e ee eee e 108 4 20 Trip Zone Flag Register TZFLG Field Descriptions ccc eee eee eee ee eee eee ee ee e ereenn eee 109 4 21 Trip Zone Clear Register TZCLR Field Descriptions cce ecce eee e xe c ence eee e ereenn eee 110 4 22 Trip Zone Force Register TZFRC Field Descriptions sse sees eee e ee eect ence eee 110 4 23 Event Trigger Selection Re
64. PRD gt 200 200 TBPHS 0000 E Syncln ll il i ime 3 8 Controlling a 3 Phase Interleaved DC DC Converter A popular power topology that makes use of phase offset between modules is shown in Figure 3 13 This system uses three PWM modules with module 1 configured as the master To work the phase relationship between adjacent modules must be F 120 This is achieved by setting the slave TBPHS registers 2 and 3 with values of 1 3 and 2 3 of the period value respectively For example if the period register is loaded with a value of 600 counts then TBPHS slave 2 200 and TBPHS slave 3 400 Both slave modules are synchronized to the master 1 module This concept can be extended to four or more phases by setting the TBPHS values appropriately The following formula gives the TBPHS values for N phases TBPHS N M TBPRD N x 1 Where N number of phases M PWM module number For example for the 3 phase case N 3 TBPRD 600 TBPHS 3 2 600 3 x 2 1 200 i e Phase value for Slave module 2 TBPHS 3 3 400 i e Phase value for Slave module 3 Figure 3 14 shows the waveforms for the configuration in Figure 3 13 SPRU791D November 2004 Revised October 2007 Applications to Power Topologies 85 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Con
65. R 0x0000 By default the TBPRD shadow register is enabled Time Base Period Immediate Load Mode If immediate load mode is selected TBCTL PRDLD 1 then a read from or a write to the TBPRD memory address goes directly to the active register ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com 2 2 3 2 Time Base Counter Synchronization Time Base TB Submodule A time base synchronization scheme connects all of the ePWM modules on a device Each ePWM module has a synchronization input EPWMxSYNCI and a synchronization output EPWMxSYNCO The input synchronization for the first instance ePWM1 comes from an external pin The possible synchronization connections for the remaining ePWM modules are shown in Figure 2 4 Figure 2 5 and Figure 2 6 Scheme 1 shown in Figure 2 4 applies to the 280x and 2801x devices Scheme 1 also applies to the 2804x devices when the ePWM pinout is configured for 280x compatible mode GPAMCFG EPWMMODE 0 Figure 2 4 Time Base Counter Synchronization Scheme 1 SYNCI eCAP1 SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback EPWM1SYNCI ePWM1 EPWM1SYNCO EPWM2SYNCI ePWM2 EPWM2SYNCO EPWMS3SYNCI ePWM3 EPWM38SYNCO EPWMxSYNCI ePWMx EPWMxSYNCO GPIO MUX ePWM Submodules 27 Wy TEXAS INSTRUMENTS www ti com Time Base TB Submodule Sche
66. R Read only n value after reset Table 4 15 Dead Band Generator Falling Edge Delay Register DBFED Field Descriptions Bits Name Description 15 10 Reserved Reserved 9 0 DEL Falling Edge Delay Count 10 bit counter 4 5 PWM Chopper Submodule Control Register Figure 4 16 and Table 4 16 provide the definitions for the PWM chopper submodule control register Figure 4 16 PWM Chopper Control Register PCCTL 15 11 10 8 Reserved CHPDUTY R 0 R W 0 7 5 4 1 0 CHPFREQ OSHTWTH CHPEN R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 16 PWM Chopper Control Register PCCTL Bit Descriptions Bits Name Value Description 15 11 Reserved Reserved SPRU791D November 2004 Revised October 2007 Registers Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Trip Zone Submodule Control and Status Registers Table 4 16 PWM Chopper Control Register PCCTL Bit Descriptions continued Bits Name Value Description 10 8 CHPDUTY Chopping Clock Duty Cycle 000 Duty 1 8 12 5 001 Duty 2 8 25 0 010 Duty 3 8 37 5 011 Duty 4 8 50 0 100 Duty 5 8 62 5 101 Duty 6 8 75 0 110 Duty 7 8 87 5 111 Reserved 75 CHPFREQ Chopping Clock Frequency 000 Divide by 1 no prescale 12 5 MHz at 100 MHz SYSCLKOUT 001 Divide by 2 6 25 MHz at 100 MHz SYSCL
67. R PRD JL gt AQCTLB 15 0 CTR Zero JL Action qualifier control B gt pie tres AQSFRC 15 0 Action qualifier S W force CTR CMPB TBCLK E AQCTLA 15 0 EPWMA Action qualifier control A 15 Action qualifier AQ Module EPWMB AQCSFRC 3 0 shadow CTR_dir continuous S W force AQCSFRCJ 3 0 active continuous S W force For convenience the possible input events are summarized again in Table 2 7 Table 2 7 Action Qualifier Submodule Possible Input Events Signal Description Registers Compared CTR PRD Time base counter equal to the period value TBCTR TBPRD CTR Zero Time base counter equal to zero TBCTR 0x0000 CTR CMPA Time base counter equal to the counter compare A TBCTR CMPA CTR CMPB Time base counter equal to the counter compare B TBCTR CMPB Software forced event Asynchronous event initiated by software The software forced action is a useful asynchronous event This control is handled by registers AQSFRC and AQCSFRC The action qualifier submodule controls how the two outputs EPWMxA and EPWMxB behave when a particular event occurs The event inputs to the action qualifier submodule are further qualified by the counter direction up or down This allows for independent action on outputs on both the count up and count down phases The possible actions imposed on outputs EPWMxA and EPWMxXB are s Set High Set output EPWMxA or EPWMxB to a high level
68. Regs AQCTLB bit CBD AQ_CLEAR fil Run Time JP 5555S SSeS eee Se Se Se ES EE EPwmlRegs CMPA half CMPA DutylA adjust duty for output EPWM1A EPwmlRegs CMPB Duty1B adjust duty for output EPWM1B SPRU791D November 2004 Revised October 2007 ePWM Submodules 47 Submit Documentation Feedback Wy TEXAS INSTRUMENTS www ti com Action Qualifier AQ Submodule Figure 2 25 Up Down Count Dual Edge Symmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Complementary TBCTR TBPRD value CA CA CA CA t T EPWMxA CB CB CB CB A A v v EPWMxB PWM period 2 x TBPRD x Trgcik Duty modulation for EPWM xA is set by CMPA and is active low i e low time duty proportional to CMPA Duty modulation for EPWMxB is set by CMPB and is active high i e high time duty proportional to CMPB Outputs EPWMx can drive upper lower complementary power switches mn G OW gt Dead band CMPB CMPA fully programmable edge placement by software Note the dead band module is also available if the more classical edge delay method is required Example 2 6 contains a code sample showing initialization and run time for the waveforms in Figure 2 25 Use the code in Example 2 1 to define the headers Example 2 6 Code Sample for Figure 2 25 I
69. S www ti com Time Base TB Submodule 2 2 Time Base TB Submodule Each ePWM module has its own time base submodule that determines all of the event timing for the ePWM module Built in synchronization logic allows the time base of multiple ePWM modules to work together as a single system Figure 2 1 illustrates the time base module s place within the ePWM Figure 2 1 Time Base Submodule Block Diagram _CTR PRD Pre Event EPWMxINT IE H Trigger Action CTR CMPA and EPWMxSOCA EPWMxSYNCI Qualifier ee oe L CTR lt PRD JL AQ CTR CMPB Interrupt ADC or EPWMxSYNCO Das cTR 0 Jt CTR_Dir ET EPWMxSOCB x Qus CTR Dir EPWMxA E IL CTR CMPA n EPWMxB S MUX Counter Compare CC CTR CMPB JL 2 2 1 Purpose of the Time Base Submodule TZ1 to TZ6 EPWMxTZINT You can configure the time base submodule for the following e Specify the ePWM time base counter TBCTR frequency or period to control how often events occur e Manage time base synchronization with other ePWM modules s Maintain a phase relationship with other ePWM modules e Set the time base counter to count up count down or count up and down mode e Generate the following events CTR PRD Time base counter equal to the specified period TBCTR TBPRD CTR Zero Time base counter equal to zero TBCTR 0x0000 e Configure the rate of the time base clock a prescaled version of the CPU system clock S
70. S wiisscaienacundnicdsismamamenetacadadedeideunsibeinen avis A ewanevawavedeus Seeteviat ovate eeu 2 28 Configuration Options for the Dead Band Submodule ceece eee ee eee eee eee e eee e ee e eree 2 29 Dead Band Waveforms for Typical Cases 0 lt Duty lt 100 ccecceec cece eee e e eee eee 2 30 PWM Chopper Submodule T 2 31 PWM Chopper Submodule Operational Detalls ss sss ss sees ereer 2 32 Simple PWM Chopper Submodule Waveforms Showing Chopping Action Only sss sees ee ee e e e e e e e e e c 2 33 PWM Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses 2 34 PWM Chopper Submodule Waveforms Showing the Pulse Width Duty Cycle Control of Sustaining PUSS actasatdcaraiotesacacavattarancnvaiaitia T EAEE S E aE EEEE alate alslaaiaislelhciascielsiaatalslaslaisletaiatsialacia 2 35 MP Zone SUBIMOUIG HH 2 36 Trip Zone Submodule Mode Control LOGIC cesses sese esse eee ereenn eee 2 37 Trip Zone Submodule Interrupt LOg G ves xs sagr ry yey axa RN eee e ee eee eee eee e eens nee OXR YR SRN KRN VRAS R VRAN RVU N 2 38 Event Tigger H sle E TTT 2 39 Event Trigger Submodule Inter Connectivity of ADC Start of Conversion and Interrupt Signals 2 40 Event Trigger Submodule Showing Event Inputs and Prescaled OUuOUuIS sees eee ecce cc c c c c e e e e e e e e e e e 2 41 Event Trigger Interrupt Generator cc csd eren ay 9 C C SN SS 9 cece N N R XR 4 YX EVR S N N SN SYR ENN EVR NR E
71. SS SSS SS SS SSS SSS SSS SSS SSS SSSSS5555 Initialization Time ssssssssssssssssssssssss EPWM Module 1 config EPwmlRegs TBPRD 600 Period 1200 TBCLK counts EPwmlRegs TBPHS 0 Set Phase register to zero EPwmlRegs TBCTL bit CTRMODE TB_COUNT_UPDOWN Symmetrical mode EPwmlRegs TBCTL bit PHSEN TB_DISABLE Master module EPwmlRegs TBCTL bit PRDLD TB_SHADOW EPwmlRegs TBCTL bit SYNCOSEL TB_CTR_ZERO Syne down stream module EPwmlRegs CMPCTL bit SHDWAMODE CC_SHADOW EPwmlRegs CMPCTL bit SHDWBMODE CC_SHADOW EPwmlRegs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwmlRegs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwmlRegs AQCTLA bit ZRO AQ_SET set actions for EPWM1A EPwmlRegs AQCTLA bit CAU AQ_CLEAR EPwmlRegs AQCTLB bit ZRO AQ_CLEAR set actions for EPWM1B EPwmlRegs AQCTLB bit CAD AQ_SET EPWM Module 2 config EPwm2Regs TBPRD 600 Period 1200 TBCLK counts EPwm2Regs TBPHS 0 Set Phase register to zero EPwm2Regs TBCTL bit CTRMODE TB_COUNT_UPDOWN Symmetrical mode EPwm2Regs TBCTL bit PHSEN TB_ENABLE Slave module EPwm2Regs TBCTL bit PRDLD TB_SHADOW EPwm2Regs TBCTL bit SYNCOSEL TB_SYNC_IN syne flow through EPwm2Regs CMPCTL bit SHDWAMODE CC_SHADOW EPwm2Regs CMPCTL bit SHDWBMODE CC_SHADOW EPwm2Regs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwm2Regs AQCTLA bit
72. TBPRD CTR Zero Time base counter equal to zero TBCTR 0x0000 CTR CMPA Time base counter equal to the counter compare A register TBCTR CMPA CTR CMPB Time base counter equal to the counter compare B register TBCTR CMPB e Managing priority when these events occur concurrently e Providing independent control of events when the time base counter is increasing and when it is decreasing 2 4 2 Action Qualifier Submodule Control and Status Register Definitions The action qualifier submodule operation is controlled and monitored via the registers in Table 2 6 Table 2 6 Action Qualifier Submodule Registers Register Address offset Shadowed Description Name AQCTLA 0x000B No Action Qualifier Control Register For Output A EPWMxA AQCTLB 0x000C No Action Qualifier Control Register For Output B EPWMxB AQSFRC 0x000D No Action Qualifier Software Force Register AQCSFRC Ox000E Yes Action Qualifier Continuous Software Force SPRU791D November 2004 Revised October 2007 ePWM Submodules 37 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com Action Qualifier AQ Submodule 38 The action qualifier submodule is based on event driven logic It can be thought of as a programmable cross switch with events at the input and actions at the output all of which are software controlled via the set of registers shown in Table 2 6 Figure 2 18 Action Qualifier Submodule Inputs and Outputs CT
73. TMS320x28xx 28xxx Enhanced Pulse Width Modulator ePWM Module Reference Guide Literature Number SPRU791D November 2004 Revised October 2007 d TEXAS INSTRUMENTS SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback Contents NT 9 1 Tuiigece Ce 0 en ee 13 1 1 IMTOO UCTOM ati sietinats dedsiaicnd a s atsloaistd EEE EESE EEES AARNE 14 1 2 SUDMOGUIESOVETVIGW icc reer TTT 14 1 3 Register Tees ani atavednduidnavdnanawatanedauueut st aub yavanna 17 2 ePWM SUDMOGUCS isisisi ennaa an a aa aa aa aA aa 19 2 1 VIVO WW o siei a che E E T 20 2 2 Time Base MB SUDMOGUIS cic cisicitatctsidietsacdietnote ache acicicialeregiace n Sate aa i a 23 2 2 1 Purpose of the Time Base SUDMOUIC ecceeee cece e eee e eee 23 2 2 2 Controlling and Monitoring the Time base SUDMOAUIe eeee esse eee eee eee r eee 24 2 2 3 Calculating PWM Period and Frequency sese cce e e e e e e e e e e r eee 25 2 2 4 Phase Locking the Time Base Clocks of Multiple ePWM Modules s sss ss sss se eee 30 2 2 5 Time base Counter Modes and Timing Waveforms sese esec e eee eee e e ee ee 30 2 3 Counter Compare CC Submodule 0 cece ence ee eee eee eee rag cart cacr Ra NR OR eR R CRRI RRR ra 32 2 3 1 Purpose of the Counter Compare SUDMOUIe cesses sese cece eee ee eee ee eee eee 33 2 3 2 Controlling and Monitoring the Counter Compare SUDMOUIC 2 20ee sees eee c c e c c e x 33 2 3 3 Operational Highlights for the
74. TS www ti com Action Qualifier Submodule Registers Figure 4 10 Action Qualifier Output B Control Register AQCTLB 15 12 11 10 9 8 Reserved CBD CBU R 0 R W 0 R W 0 7 6 5 4 3 2 1 0 CAD CAU PRD ZRO R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 10 Action Qualifier Output B Control Register AQCTLB Field Descriptions Bits Name Value Description 15 12 Reserved 11 10 CBD Action when the counter equals the active CMPB register and the counter is decrementing 00 Do nothing action disabled 01 Clear force EPWMxB output low 10 Set force EPWMxB output high 11 Toggle EPWMxB output low output signal will be forced high and a high signal will be forced low 9 8 CBU Action when the counter equals the active CMPB register and the counter is incrementing 00 Do nothing action disabled 01 Clear force EPWMxB output low 10 Set force EPWMxB output high 11 Toggle EPWMxB output low output signal will be forced high and a high signal will be forced low 7 6 CAD Action when the counter equals the active CMPA register and the counter is decrementing 00 Do nothing action disabled 01 Clear force EPWMxB output low 10 Set force EPWMxB output high 11 Toggle EPWMxB output low output signal will be forced high and a high signal will be forced low 5 4 CAU Action when the counter equals the active CMPA register and the counter is incrementing 00
75. Trip Zone Submodule Registers Register Name Address offset Shadowed Description 7 TZSEL 0x0012 No Trip Zone Select Register reserved 0x0013 TZCTL 0x0014 No Trip Zone Control Register TZEINT 0x0015 No Trip Zone Enable Interrupt Register TZFLG 0x0016 No Trip Zone Flag Register TZCLR 0x0017 No Trip Zone Clear Register TZFRC 0x0018 No Trip Zone Force Register AI trip zone registers are EALLOW protected and can be modified only after executing the EALLOW instruction For more information see the device specific version of the System Control and Interrupts Reference Guide listed in Section 1 2 7 3 Operational Highlights for the Trip Zone Submodule 60 The following sections describe the operational highlights and configuration options for the trip zone submodule The trip zone signals at pins TZT to TZ6 also collectively referred to as TZn are active low input signals When one of these pins goes low it indicates that a trip event has occurred Each ePWM module can be individually configured to ignore or use each of the trip zone pins Which trip zone pins are used by a particular ePWM module is determined by the TZSEL register for that specific ePWM module The trip zone signals may or may not be synchronized to the system clock SYSCLKOUT and digitally filtered within the GPIO MUX block A minimum 1 SYSCLKOUT low pulse on TZn inputs is sufficient to trigger a fault condition in the ePWM module The asynchronous trip makes sure th
76. VENT wessxisctconccusscauamstatcuntiencanmaamomenanand mal stale enmeunnanaahelscsesem aN 2 16 Counter Compare Events In Up Down Count Mode TBCTL PHSDIR 1 Count Up On Synchronization EVERI H aaa ain aja alelersidlava areiajea EE G 2 17 Action Qualifier SUBMOGUIE TTT 2 18 Action Qualifier Submodule Inputs and Outputs sss sss sss e eee eee eee eee reer 2 19 Possible Action Qualifier Actions for EPWMxA and EPWMXxB Outputs xs s xe eee e e e sees eee eee e eee eee 2 20 Up Down Count Mode Symmetrical Waveform s sss s sss sse e eee eee ee ee e e e e eee eee 2 21 Up Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMXB ACtive HiQh cc s sss sss s ves ereer serres esse enen nenen Keene nenen nenen 2 22 Up Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMXB ACtive LOW cceccee eee c eee eee ee eee e enna ence ee neee eens en nee sense ences eens eneeeeeeeeeneeeeeeeteneeeeeeennes 2 23 Up Count Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMXA 2 06 2 24 Up Down Count Dual Edge Symmetric Waveform With Independent Modulation on EPWMxA and EPWMXB Active Ee 2 25 Up Down Count Dual Edge Symmetric Waveform With Independent Modulation on EPWMxA and EPWMXB elai Sa TL 2 26 Up Down Count Dual Edge Asymmetric Waveform With Independent Modulation on EPWMxA Active LOW vsiieievnaiuiney a WanatnitaniennanGieaencnanedaneNaa dian E E T 2 27 Dead Band SuUDMOAUI
77. WMxB oO gt techniques T m D oO EPWMxA Active Low S 1w gt U PWM period 2 x TBPRD x TBCLK Rising edge and falling edge can be asymmetrically positioned within a PWM cycle This allows for pulse placement Duty modulation for EPWMXA is set by CMPA and CMPB Low time duty for EPWMXA is proportional to CMPA CMPB To change this example to active high CMPA and CMPB actions need to be inverted i e Set Clear and Clear Set Duty modulation for EPWMXxB is fixed at 50 utilizes spare action resources for EPWMxB Action Qualifier AQ Submodule gt U La y S E w Example 2 7 contains a code sample showing initialization and run time for the waveforms in Figure 2 26 Use the code in Example 2 1 to define the headers Example 2 7 Code Sample for Figure 2 26 Initialization Time TLS SP SSS eee esses SS SS Se Se Se SS Ss EPwmlRegs TBPRD 600 EPwmlRegs CMPA half CMPA 250 EPwmlRegs CMPB 450 EPwmlRegs TBPHS 0 EPwmlRegs TBCNT 0 EPwmlRegs TBCTL bit CTRMODE TB_UPDOWN EPwmlRegs TBCTL bit PHSEN TB_DISABLE EPwmlRegs TBCTL bit PRDLD TB_SHADOW EPwmlRegs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwmlRegs TBCTL bit HSPCLKDIV TB_DIV1 EPwmlRegs TBCTL bit CLKDIV TB_DIV1 EPwmlRegs CMPCTL bit SHDWAMODE CC_SHADOW EPwmlRegs CMPCTL bi
78. YSCLKOUT This allows the time base counter to increment decrement at a slower rate SPRU791D November 2004 Revised October 2007 ePWM Submodules 23 Submit Documentation Feedback Wy TEXAS INSTRUMENTS www ti com Time Base TB Submodule 2 2 2 Controlling and Monitoring the Time base Submodule Table 2 2 shows the registers used to control and monitor the time base submodule Table 2 2 Time Base Submodule Registers Register Address offset Shadowed Description TBCTL 0x0000 No Time Base Control Register TBSTS 0x0001 No Time Base Status Register TBPHSHR 0x0002 No HRPWM extension Phase Register 7 TBPHS 0x0003 No Time Base Phase Register TBCTR 0x0004 No Time Base Counter Register TBPRD 0x0005 Yes Time Base Period Register 1 This register is available only on ePWM instances that include the high resolution extension HRPWM On ePWM modules that do not include the HRPWM this location is reserved This register is described in the TMS320x28xx 28xxx High Resolution Pulse Width Modulator HRPWM Reference Guide SPRU924 See the device specific data manual to determine which ePWM instances include this feature The block diagram in Figure 2 2 shows the critical signals and registers of the time base submodule Table 2 3 provides descriptions of the key signals associated with the time base submodule Figure 2 2 Time Base Submodule Signals and Registers TBPRD Period Shadow TBCTL PRDLD TBPRD Period Acti
79. _max SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback ePWM Submodules A Texas INSTRUMENTS www ti com Counter Compare CC Submodule Figure 2 10 Time Base Up Down Count Waveforms TBCTL PHSDIR 1 Count Up On Synchronization Event TBCNT 15 0 OxFFFF TBPRD value TBPHS value 0x0000 EPWMxSYNCI CTR_dir DOWN DOWN DOWN CTR zero jl CTR PRD l l l CNT_max 2 3 Counter Compare CC Submodule Figure 2 11 illustrates the counter compare submodule within the ePWM Figure 2 11 Counter Compare Submodule CTR PRD e EPWMxINT CTR 0 PIE Action CTR CMPA EPWMxSOCA EPWMxSYNCI Qualifier d eee CTR PRD JL AQ CTR CMPB ADC SEE p EPWMxSYNCO w d CTR 0 JL CTR_Dir EPWMxSOCB z CTR_Dir EPWMxA TL CTR CMPA ero Counter EPWMxB MUX Compare CC CTR CMPB JL EPWMxTZINT TZ1 to TZ6 Figure 2 12 shows the basic structure of the counter compare submodule 32 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Counter Compare CC Submodule 2 3 1 Purpose of the Counter Compare Submodule The counter compare submodule takes as input the time base counter value This value is continuously compared to the counter compare A CMPA and counter compare B CMPB registers When the time base counter is equal to one of the c
80. a PWM module can be configured to allow a Syncin pulse to cause the TBPHS register to be loaded into the TBCTR register To illustrate this concept Figure 3 11 shows a master and slave module with a phase relationship of 120 i e the slave leads the master Figure 3 11 Configuring Two PWM Modules for Phase Control Ext Syncin optional Master Phase reg Syncin En oreo o T gt EPWM1A EPWM1B CTR zero O CTR CMPB oO x Oo SyncOut Slave Phase reg En 120 gt EPWM2A EPWM2B CTR zero O CTR CMPB xX O 2 SyncOut Figure 3 12 shows the associated timing waveforms for this configuration Here TBPRD 600 for both master and slave For the slave TBPHS 200 i e 200 600 X 360 120 Whenever the master generates a Syncin pulse CTR PRD the value of TBPHS 200 is loaded into the slave TBCTR register so the slave time base is always leading the master s time base by 120 84 Applications to Power Topologies SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com Controlling a 3 Phase Interleaved DC DC Converter Figure 3 12 Timing Waveforms Associated With Phase Control Between 2 Modules FFFFh A TBCTR 0 15 Master Module 600 600 TBPRD 0000 z CTR PRD l l SycnOut time FFFFh 4 TBCTR 0 15 lt 2 gt Phase 120 Slave Module 600 600 TB
81. ar Register TZFRC 0x0018 1 No Trip Zone Force Register Event Trigger Submodule Registers ETSEL 0x0019 1 No Event Trigger Selection Register ETPS 0x001A 1 No Event Trigger Pre Scale Register ETFLG 0x001B 1 No Event Trigger Flag Register ETCLR 0x001C 1 No Event Trigger Clear Register ETFRC 0x001D 1 No Event Trigger Force Register PWM Chopper Submodule Registers PCCTL 0x001E 1 No PWM Chopper Control Register High Resolution Pulse Width Modulator HRPWM Extension Registers HRCNFG 0x0020 1 No HRPWM Configuration Register 12 UI Locations not shown are reserved 2 These registers are only available on ePWM instances that include the high resolution PWM extension Otherwise these locations are reserved These registers are described in the TMS320x28xx 28xxx High Resolution Pulse Width Modulator HRPWM Reference Guide SPRU924 See the device specific data manual to determine which instances include the HRPW M 3 EALLOW protected registers as described in the specific device version of the System Control and Interrupts Reference Guide listed in Section 1 Introduction SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback a TEXAS INSTRUMENTS Seven submodules are included in every ePWM peripheral Each of these submodules performs specific Chapter 2 SPRU791D November 2004 Revised October 2007 ePWM Submodules tasks that can be configured by software Topic Page
82. at if clocks are missing for any reason the outputs can still be tripped by a valid event present on TZn inputs providing the GPIO is appropriately configured For more information see the GPIO section of the specific device version of the System Control and Interrupts Reference Guide listed in Section 1 Each TZn input can be individually configured to provide either a cycle by cycle or one shot trip event for a ePWM module The configuration is determined by the TZSEL CBCn and TZSEL OSHTh control bits where n corresponds to the trip pin respectively e Cycle by Cycle CBC When a cycle by cycle trip event occurs the action specified in the TZCTL register is carried out immediately on the EPWMxA and or EPWMXB output Table 2 18 lists the possible actions In addition the cycle by cycle trip event flag TZFLG CBC is set and a EPWMx_TZINT interrupt is generated if it is enabled in the TZEINT register and PIE peripheral The specified condition on the pins is automatically cleared when the ePWM time base counter reaches zero TBCTR 0x0000 if the trip event is no longer present Therefore in this mode the trip event is cleared or reset every PWM cycle The TZFLG CBC flag bit will remain set until it is manually cleared by writing to the TZCLR CBC bit If the cycle by cycle trip event is still present when the TZFLG CBC bit is cleared then it will again be immediately set e One Shot OSHT When a one shot trip event occurs the action
83. ations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements TI products are not authorized for use in safety critical applications such as life support where a failure of the TI product would reasonably be expected to cause severe personal injury or death unless officers of the parties have executed an agreement specifically governing such use Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications and acknowledge and agree that they are solely responsible for all legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed
84. cy Pulse width of the first pulse in the chopped pulse train Duty cycle of the second and subsequent pulses Bypass the PWM chopper module entirely In this case the PWM waveform is passed through without modification Configure the ePWM module to react to one all or none of the trip zone pins Specify the tripping action taken when a fault occurs Force EPWMxA and or EPWMxB high Force EPWMXxA and or EPWMxB low Force EPWMxA and or EPWMxB to a high impedance state Configure EPWMxA and or EPWMxB to ignore any trip condition Configure how often the ePWM will react to each trip zone pin One shot Cycle by cycle Enable the trip zone to initiate an interrupt Bypass the trip zone module entirely 20 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback Ww TEXAS INSTRUMENTS www ti com Overview Table 2 1 Submodule Configuration Parameters continued Submodule Configuration Parameter or Option Event trigger ET e Enable the ePWM events that will trigger an interrupt s Enable ePWM events that will trigger an ADC start of conversion event e Specify the rate at which events cause triggers every occurrence or every second or third occurrence s Poll set or clear event flags Code examples are provided in the remainder of this document that show how to implement various ePWM module configurations These examples use the constant definitions sho
85. dow FIFO is full a CPU write will overwrite the current shadow value Reserved Reserved SHDWBMODE Counter compare B CMPB Register Operating Mode Shadow mode Operates as a double buffer All writes via the CPU access the shadow register Immediate mode Only the active compare B register is used All writes and reads directly access the active register for immediate compare action Reserved Reserved SHDWAMODE Counter compare A CMPA Register Operating Mode Shadow mode Operates as a double buffer All writes via the CPU access the shadow register Immediate mode Only the active compare register is used All writes and reads directly access the active register for immediate compare action LOADBMODE 00 01 10 11 Active Counter Compare B CMPB Load From Shadow Select Mode This bit has no effect in immediate mode CMPCTL SHDWBMODE 1 Load on CTR Zero Time base counter equal to zero TBCTR 0x0000 Load on CTR PRD Time base counter equal to period TBCTR TBPRD Load on either CTR Zero or CTR PRD Freeze no loads possible LOADAMODE 00 01 10 11 Active Counter Compare A CMPA Load From Shadow Select Mode This bit has no effect in immediate mode CMPCTL ISHDWAMODE 1 Load on CTR Zero Time base counter equal to zero TBCTR 0x0000 Load on CTR PRD Time base counter equal to period TBCTR TBPRD Load on either CTR Zero or CTR PRD Freeze n
86. e c ee e eee e e e eee e e e e e e r e e eee eee 2 1 Time Base Submodule Block Diagram sss cx rx ry Sa RX x 0 YN N N Y SN 04 YR N ENR AN EEN AN YR YR OUR NR AN NEN RVU 2 2 Time Base Submodule Signals and Registers sccecceeeeeeeeee cece eeeeeeeeeeneeeeeeneeeeeeeeeeeeeeeeeeeeenees 2 3 Time Base Frequency and Period ccenereceee czo gn rene gaya yR 0 9 0 RR RKR N KRU dR 9 RR U RR R A N UN V 2 4 Time Base Counter Synchronization SCHEME 1 cesses eee ee e eee e e e eee 2 5 Time Base Counter Synchronization SCHEME 2 sese e eee ee c eee e e e ee e Keene 2 6 Time Base Counter Synchronization SCHEME 2 esec eee eee e e e x e e e eee ee eee eee eee 2 7 Time Base Up Count Mode Waveforms cesses sese c ecce ecce c e c e r r eee e e e e e ee ee eee 2 8 Time Base Down Count Mode Waveforms eceeeeece ents eee e e e e e e ee e eee eee 2 9 Time Base Up Down Count Waveforms TBCTL PHSDIR 0 Count Down On Synchronization Event 2 10 Time Base Up Down Count Waveforms TBCTL PHSDIR 1 Count Up On Synchronization Event 2 11 Counter Compare SuDMOdUle T 2 12 Detailed View of the Counter Compare SUDMOUIC cceee eee e e e eee eee eee e eee e e e e ee eee 2 13 Counter Compare Event Waveforms in Up Count Mode sss eee esse cece ee eee eee eee ee e eee 2 14 Counter Compare Events in Down Count Modes sss sss see ence cece eens e e eee eee 2 15 Counter Compare Events In Up Down Count Mode TBCTL PHSDIR 0 Count Down On SYNCHrONIZATION E
87. e can be extended to the capture peripheral modules eCAP The number of modules is device dependent and based on target application needs Modules can also operate stand alone Each ePWM module supports the following features e Dedicated 16 bit time base counter with period and frequency control e Two PWM outputs EPWMxA and EPWMxB that can be used in the following configurations Two independent PWM outputs with single edge operation Two independent PWM outputs with dual edge symmetric operation One independent PWM output with dual edge asymmetric operation e Asynchronous override control of PWM signals through software e Programmable phase control support for lag or lead operation relative to other ePWM modules e Hardware locked synchronized phase relationship on a cycle by cycle basis e Dead band generation with independent rising and falling edge delay control e Programmable trip zone allocation of both cycle by cycle trip and one shot trip on fault conditions e A trip condition can force either high low or high impedance state logic levels at PWM outputs e All events can trigger both CPU interrupts and ADC start of conversion SOC e Programmable event prescaling minimizes CPU overhead on interrupts s PWM chopping by high frequency carrier signal useful for pulse transformer gate drives Each ePWM module is connected to the input output signals shown in Figure 1 1 The signals are described in detail in subsequent section
88. e last two entries in Table 2 13 show combinations where either the falling edge delay FED or rising edge delay RED blocks are bypassed Table 2 13 Classical Dead Band Operating Modes DBCTL POLSEL DBCTL OUT_MODE Mode Mode Description 7 3 2 S1 so 1 EPWMxA and EPWMxB Passed Through No Delay X X 0 0 2 Active High Complementary AHC 1 0 1 1 3 Active Low Complementary ALC 0 1 1 1 4 Active High AH 0 0 1 1 5 Active Low AL 1 1 1 1 EPWMxA Out EPWM lt xA In No Delay 6 l i Oori Oor1 0 1 EPWMxB Out EPWM XA In with Falling Edge Delay EPWM xA Out EPWM XA In with Rising Edge Delay 7 l Oori Oor1 1 0 EPWMxB Out EPWMxB In with No Delay 1 These are classical dead band modes and assume that DBCTL IN_MODE 0 0 That is EPWMxA in is the source for both the falling edge and rising edge delays Enhanced non traditional modes can be achieved by changing the IN _ MODE configuration 52 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com Dead Band Generator DB Submodule Figure 2 29 shows waveforms for typical cases where 0 lt duty lt 100 Figure 2 29 Dead Band Waveforms for Typical Cases 0 lt Duty lt 100 4 Period gt Original i outA 1 RED gt d Rising Edge Delayed RED FED gt a Falling Edge Delayed FED Active High N es ee Complementary AHC Active Low Compleme
89. efault at reset Figure 2 19 Possible Action Qualifier Actions for EPWMxA and EPWMxB Outputs TB Counter equals Actions Comp A Comp B Period Do Nothing Clear Low Set High SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback ePWM Submodules 39 KN TEXAS INSTRUMENTS www ti com Action Qualifier AQ Submodule 2 4 3 Action Qualifier Event Priority It is possible for the ePWM action qualifier to receive more than one event at the same time In this case events are assigned a priority by the hardware The general rule is events occurring later in time have a higher priority and software forced events always have the highest priority The event priority levels for up down count mode are shown in Table 2 8 A priority level of 1 is the highest priority and level 7 is the lowest The priority changes slightly depending on the direction of TBCTR Table 2 8 Action Qualifier Event Priority for Up Down Count Mode Event If TBCTR is Incrementing TBCTR Zero up to TBCTR TBPRD Priority Level Event If TBCTR is Decrementing TBCTR TBPRD down to TBCTR 1 1 Highest Software forced event Software forced event 2 Counter equals CMPB on up count CBU Counter equals CMPB on down coun
90. effect 4 4 Dead Band Submodule Registers Figure 4 13 through Figure 4 15 and Table 4 13 through Table 4 15 provide the register definitions Figure 4 13 Dead Band Generator Control Register DBCTL 15 8 Reserved R 0 7 6 5 4 3 2 1 0 Reserved IN_MODE POLSEL OUT_MODE R 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset SPRU791D November 2004 Revised October 2007 Registers 103 Submit Documentation Feedback Dead Band Submodule Registers 4i TEXAS INSTRUMENTS www ti com Table 4 13 Dead Band Generator Control Register DBCTL Field Descriptions Bits Name Value Description 15 6 Reserved Reserved 5 4 IN MODE Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 2 28 This allows you to select the input source to the falling edge and rising edge delay To produce classical dead band waveforms the default is EPWMxA In is the source for both falling and rising edge delays 00 EPWM xA In from the action qualifier is the source for both falling edge and rising edge delay 01 EPWM xB In from the action qualifier is the source for rising edge delayed signal EPWMXA In from the action qualifier is the source for falling edge delayed signal 10 EPWMXA In from the action qualifier is the source for rising edge delayed signal EPWMxB In from the action qualifier is the source
91. egister AQCSFRO 0ceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 102 4 13 Dead Band Generator Control Register DBCTL cesse ee ecce ecce eee 103 4 14 Dead Band Generator Rising Edge Delay Register DBRED 0 seceeeeeee eee eeee nese eee eeeeeeeeeeeeeeeees 105 4 15 Dead Band Generator Falling Edge Delay Register DBFED sss se eee 105 4 16 PWM Chopper Control Register PCCTL 0cceceeee eree 105 4 17 Trip Zone Select Register TZSEL T caa rrr ra ORO ORN Raa H OR RTT E O rR ET T RR VRE Paa 107 4 18 Trip Zone Control Register TGT a SS Oaai a 0 0 CEST e R R Sa go a a RR eE HAOR HE yra 108 4 19 Trip Zone Enable Interrupt Register TZEINTI sss sse e e e e e e r eee e eee 108 4 20 Trip Zone Flag Register LT ZRL GT ey cN v SERRE RRR K KK EUA RRR RX UUE VES RNK RNK KRK Z KY ENNES 109 4 21 Trip Zone Clear Register TZCLR sse ee e e ee eee ee eenn 110 4 22 Trip Zone Force Register p 9 s 161 T 110 4 23 Event Trigger Selection Register ETSEL see e ecce eee 111 4 24 Event Trigger Prescale Register ETPS sese ecce renee 112 4 25 _ Event Tirigger Flag Register ET FLG cay edr 900 ds eas N KRN N OYNA R elev ENRN ENR NR ER N EN AN EN ENR EVR Urs 113 4 26 Event Trigger Clear Register ETCLR esse ee eee renee 114 4 27 Event Trigger Force Register ETFRC cceeceeeeeee eee eee eee eeeeeeeeaeeeeeeeenaeeeeeeeeeeeeeeeeaseneeneenaees 115 List of Figures SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback
92. equent diagrams Actions at zero and period although appearing to occur concurrently are actually separated by one TBCLK period TBCTR wraps from period to 0000 moO Ww gt Example 2 3 contains a code sample showing initialization and run time for the waveforms in Figure 2 22 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Example 2 3 Code Sample for Figure 2 22 Action Qualifier AQ Submodule Initialization Time 77 555555555 SF SSS SSeS SPS EPwmlRegs TBPRD 600 Period 601 TBCLK counts EPwmlRegs CMPA half CMPA 350 Compare A 350 TBCLK counts EPwmlRegs CMPB 200 Compare B 200 TBCLK counts EPwmlRegs TBPHS 0 Set Phase register to zero EPwmlRegs TBCTR 0 clear TB counter EPwmlRegs TBCTL bit CTRMODE TB_UP EPwmlRegs TBCTL bit PHSEN TB_DISABLE Phase loading disabled EPwmlRegs TBCTL bit PRDLD TB_SHADOW EPwmlRegs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwmlRegs TBCTL bit HSPCLKDIV TB_DIV1 TBCLK SYSCLKOUT EPwmlRegs TBCTL bit CLKDIV TB_DIV1 EPwmlRegs CMPCTL bit SHDWAMODE CC_SHADOW EPwmlRegs CMPCTL bit SHDWBMODE CC_SHADOW EPwmlRegs CMPCTL bit LOADAMODE CC_CTR_ZERO load on TBCTR Zero EPwmlRegs CMPCTL bit LOADBMODE CC_CTR_ZERO load on TBCTR Zero EPwmlRegs AQCTLA bit PRD AQ_CLEAR EPwmlRegs AQCTLA bit CAU AQ_SET EPwmlRegs AQ
93. evised October 2007 Applications to Power Topologies 81 Submit Documentation Feedback Controlling Dual 3 Phase Inverters for Motors ACI and PMSM 82 Wy TEXAS INSTRUMENTS www ti com Figure 3 10 3 Phase Inverter Waveforms for Figure 3 9 Only One Inverter Shown 800 FED EPWM2A i R RED EPWM2B FED EPWM3A 7 EPWMSB ED Applications to Power Topologies SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com Controlling Dual 3 Phase Inverters for Motors ACI and PMSM Example 3 4 Code Snippet for Configuration in Figure 3 9 EPwmlRegs CMPA half CMPA EPwm2Regs CMPA half CMPA EPwm3Regs CMPA half CMPA E 800 Period 1600 TBCLK counts E Set Phase register to zero E CTRMODE TB_COUNT_UPDOWN Symmetrical mode E PHSEN TB_DISABLE Master module E PRDLD TB SHADOW E SYNCOSEL TB_CTR_ZERO Syne down stream module E SHDWAMODE CC_SHADOW E SHDWBMODE CC_SHADOW E LOADAMODE CC CTR ZERO load on CTR Zero E LOADBMODE CC_CTR_ZERO load on CTR Zero E CAU
94. fault on reset 010 4 011 6 100 8 101 10 110 12 111 14 SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback Registers 95 Time Base Submodule Registers Wy TEXAS INSTRUMENTS www ti com Table 4 4 Time Base Control Register TBCTL Field Descriptions continued Bit Field Value Description SWFSYNC Software Forced Synchronization Pulse Writing a 0 has no effect and reads always return a 0 Writing a 1 forces a one time synchronization pulse to be generated This event is ORed with the EPWMxSYNCI input of the ePWM module SWFSYNC is valid operates only when EPWMxSYNCI is selected by SYNCOSEL 00 5 4 SYNCOSEL 00 01 10 11 Synchronization Output Select These bits select the source of the EPWMxSYNCO signal EPWMxSYNC CTR zero Time base counter equal to zero TBCTR 0x0000 CTR CMPB Time base counter equal to counter compare B TBCTR CMPB Disable EPWMxSYNCO signal PRDLD Active Period Register Load From Shadow Register Select The period register TBPRD is loaded from its shadow register when the time base counter TBCTR is equal to zero A write or read to the TBPRD register accesses the shadow register Load the TBPRD register immediately without using a shadow register A write or read to the TBPRD register directly accesses the active register PHSEN Counter Register Load From Phase Register Enable Do n
95. form TBCNTR UP DOWN UP DOWN L Case 1 EPWMxA EPWMxB CMPA 4 0 Duty Y Case 2 EPWMxA EPWMxB Case 3 Case 3 T aid la CMPA 1 75 Duty E es ey ae EPWMxA EPWMxB CMPA 0 100 Duty E Case 4 EPWMxA EPWMxB The PWM waveforms in Figure 2 21 through Figure 2 26 show some common action qualifier configurations The C code samples in Example 2 2 through Example 2 7 shows how to configure an ePWM module for each case Some conventions used in the figures and examples are as follows TBPRD CMPA and CMPB refer to the value written in their respective registers The active register not the shadow register is used by the hardware CMPx refers to either CMPA or CMPB EPWMxA and EPWMxB refer to the output signals from ePWMx Up Down means Count up and down mode Up means up count mode and Dwn means down count mode Sym Symmetric Asym Asymmetric ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback Ww TEXAS INSTRUMENTS www ti com Action Qualifier AQ Submodule Figure 2 21 Up Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Active High TBCTR TBPRD value i 1 i Z P CB CA Z P CB C
96. gister ETSEL Field Descriptions esse e e ee e eee e e e eee e e eee eee 111 4 24 Event Trigger Prescale Register ETPS Field Descriptions sese se c e eee e e eee ee e K e eee eee 112 4 25 Event Trigger Flag Register ETFLG Field Descriptions cesse eee e e ee e e ee e e e e eee eee 114 4 26 Event Trigger Clear Register ETCLR Field Descriptions sss esse c eee e eee e eee e eee eee 114 4 27 Event Trigger Force Register ETFRC Field Descriptions cesses see eee r eee ence e reer TIS A 1 Changes Tor REVISION D H 117 SPRU791D November 2004 Revised October 2007 List of Tables 7 Submit Documentation Feedback 8 List of Tables SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback A TEXAS Preface IN STRUMENTS SPRU791D November 2004 Revised October 2007 Read This First This guide describes the Enhanced Pulse Width Modulator ePWM Module It includes an overview of the module and information about each of the sub modules e Time Base Module e Counter Compare Module e Action Qualifier Module s Dead Band Generator Module e PWM Chopper PC Module e Trip Zone Module e Event Trigger Module Related Documentation From Texas Instruments The following books describe the TMS320x280x and related support tools that are available on the TI website Data Manuals SPRS230 TMS320F2809 F2808 F2806 F2802 F2801 C2802 C2801 and F2801x DSPs Data Manual contains the pinout signal descriptions as
97. he phase TBPHS when a synchronization event occurs The synchronization event can be initiated by the input synchronization signal EPWMxSYNCI or by a software forced synchronization 15 Figure 4 3 Time Base Counter Register TBCTR 0 TBCTR R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 3 Time Base Counter Register TBCTR Field Descriptions Bits Name Value Description 15 0 TBCTR 0000 Reading these bits gives the current time base counter value FFFF Writing to these bits sets the current time base counter value The update happens as soon as the write occurs the write is NOT synchronized to the time base clock TBCLK and the register is not shadowed 94 Registers SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Time Base Submodule Registers Figure 4 4 Time Base Control Register TBCTL 15 14 13 12 10 9 8 FREE SOFT PHSDIR CLKDIV HSPCLKDIV R W 0 R W 0 R W 0 R W 0 0 1 7 6 5 4 3 2 1 0 HSPCLKDIV SWFSYNC SYNCOSEL PRDLD PHSEN CTRMODE R W 0 0 1 R W 0 R W 0 R W 0 R W 0 R W 11 LEGEND R W Read Write R Read only n value after reset Table 4 4 Time Base Control Register TBCTL Field Descriptions Bit Field Value Description 15 14 FREE SOFT Emulation Mode Bits These bits select the behavior
98. here P v v 700 950 EPWM1A Pulse center 700 1150 1400 P CA CB P CA Y A A Y a EPWM2A 650 500 800 P v K K cal A Al EPWM3A Indicates this event triggers an interrupt CB Indicates this event triggers an ADC start A of conversion SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback Applications to Power Topologies 73 Controlling Multiple Buck Converters With Independent Frequencies Example 3 1 Configuration for Example in Figure 3 4 Wy TEXAS INSTRUMENTS www ti com YO a na Note code for only 3 modules shown Initialization Time EPWM Module 1 config EPwmlRegs TBPRD 1200 EPwmlRegs TBPHS 0 EPwmlRegs TBCTL bit CTRMODE TB_COUNT_UP EPwmlRegs TBCTL bit PHSEN TB_DISABLE EPwmlRegs TBCTL bit PRDLD TB_SHADOW EPwmlRegs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwmlRegs CMPCTL bit SHDWAMODE CC_SHADOW EPwmlRegs CMPCTL bit SHDWBMODE CC_SHADOW EPwmlRegs CMPCTL bit LOADAMODE CC_CTR_ZERO EPwmlRegs CMPCTL bit LOADBMODE CC_CTR_ZERO EPwmlRegs AQCTLA bit PRD AQ_CLEAR EPwmlRegs AQCTLA bit CAU
99. ing a 0 will have no effect Reading a 1 on this bit indicates that the time base counter reached the max value OxFFFF Writing a 1 to this bit will clear the latched event 1 SYNCI Input Synchronization Latched Status Bit Writing a 0 will have no effect Reading a 0 indicates no external synchronization event has occurred Reading a 1 on this bit indicates that an external synchronization event has occurred EPWMxSYNCI Writing a 1 to this bit will clear the latched event 0 CTRDIR Time Base Counter Direction Status Bit At reset the counter is frozen therefore this bit has no meaning To make this bit meaningful you must first set the appropriate mode via TBCTL CTRMODE Time Base Counter is currently counting down Time Base Counter is currently counting up 4 2 Counter Compare Submodule Registers Figure 4 6 through Figure 4 8 and Table 4 6 through Table 4 8 illustrate the counter compare submodule control and status registers Figure 4 6 Counter Compare A Register CMPA 15 CMPA R W 0 LEGEND R W Read Write R Read only n value after reset SPRU791D November 2004 Revised October 2007 Registers 97 Submit Documentation Feedback Wy TEXAS INSTRUMENTS www ti com Counter Compare Submodule Registers Table 4 6 Counter Compare A Register CMPA Field Descriptions Bits Name Description 15 0 CMPA The value in the active CMPA registe
100. input pulse 2 CTR Zero The time base counter equal to zero TBCTR 0x0000 3 CTR CMPB The time base counter equal to the counter compare B TBCTR CMPB register CTR PRD Time base counter equal to the specified period This signal is generated whenever the counter value is equal to the active period register value That is when TBCTR TBPRD CTR Zero Time base counter equal to zero This signal is generated whenever the counter value is zero That is when TBCTR equals 0x0000 CTR CMPB Time base counter equal to active counter compare B register TBCTR CMPB This event is generated by the counter compare submodule and used by the synchronization out logic CTR_dir Time base counter direction Indicates the current direction of the ePWM s time base counter This signal is high when the counter is increasing and low when it is decreasing CTR_max Time base counter equal max value TBCTR OxFFFF Generated event when the TBCTR value reaches its maximum value This signal is only used only as a status bit TBCLK Time base clock This is a prescaled version of the system clock SYSCLKOUT and is used by all submodules within the ePWM This clock determines the rate at which time base counter increments or decrements 2 2 3 Calculating PWM Period and Frequency The frequency of PWM events is controlled by the time base period TBPRD register and the mode of the time base counter Figure 2 3 shows the period Tpwm
101. ipheral is a key element in controlling many of the power related systems found in both commercial and industrial equipments These systems include digital motor control switch mode power supply control uninterruptible power supplies UPS and other forms of power conversion The ePWM peripheral performs a digital to analog DAC function where the duty cycle is equivalent to a DAC analog value it is sometimes referred to as a Power DAC This reference guide is applicable for the ePWM found on the TMS320x280x TMS320x2801x and TMS320x2804x processors This includes all Flash based ROM based and RAM based devices Topic Page 1 1 Inroad uch on 14 a IE SU MO dUe eT TATE 14 1 3 weeRegisten Napa A A emarsrentscn 17 SPRU791D November 2004 Revised October 2007 Introduction 13 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com Introduction 1 1 1 2 Introduction An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU overhead or intervention It needs to be highly programmable and very flexible while being easy to understand and use The ePWM unit described here addresses these requirements by allocating all needed timing and control resources on a per PWM channel basis Cross coupling or sharing of resources has been avoided instead the ePWM is built up from smaller single channel modules with separate resources and that can operate together as required to form a s
102. is ePWM module Enable TZ5 as a one shot trip source for this ePWM module OSHT4 Trip zone 4 TZ4 Select Disable TZ4 as a one shot trip source for this ePWM module Enable TZ4 as a one shot trip source for this ePWM module OSHT3 Trip zone 3 TZ3 Select Disable TZ3 as a one shot trip source for this ePWM module Enable TZ3 as a one shot trip source for this ePWM module OSHT2 Trip zone 2 TZ2 Select Disable TZ2 as a one shot trip source for this ePWM module Enable TZ2 as a one shot trip source for this ePWM module OSHT1 0 1 Trip zone 1 TZT Select Disable TZT as a one shot trip source for this ePWM module Enable TZT as a one shot trip source for this ePWM module Cycle by Cycle CBC Trip zone enable disable When any of the enabled pins go low a cycle by cycle trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register Table 4 18 is taken on the EPWMxA and EPWMxB outputs A cycle by cycle trip condition is automatically cleared when the time base counter reaches zero 7 6 Reserved Reserved 5 CBC6 Trip zone 6 TZ6 Select Disable TZ6 as a CBC trip source for this ePWM module Enable TZ6 as a CBC trip source for this ePWM module CBC5 Trip zone 5 TZ5 Select Disable TZ5 as a CBC trip source for this ePWM module Enable TZ5 as a CBC trip source for this ePWM module CBC4 Trip zone 4 TZ4 Select Disable TZ4 as a CBC trip sou
103. ister Set Grouped by Submodule Size x16 Shadow Description Name Offset Time Base Submodule Registers TBCTL 0x0000 1 No Time Base Control Register TBSTS 0x0001 1 No Time Base Status Register TBPHSHR 0x0002 1 No Extension for HRPWM Phase Register 7 TBPHS 0x0003 1 No Time Base Phase Register TBCTR 0x0004 1 No Time Base Counter Register TBPRD 0x0005 1 Yes Time Base Period Register Counter Compare Submodule Registers CMPCTL 0x0007 1 No Counter Compare Control Register CMPAHR 0x0008 1 No Extension for HRPWM Counter Compare A Register 2 CMPA 0x0009 1 Yes Counter Compare A Register CMPB 0x000A 1 Yes Counter Compare B Register Action Qualifier Submodule Registers AQCTLA 0x000B 1 No Action Qualifier Control Register for Output A EPWMXxA AQCTLB 0x000C 1 No Action Qualifier Control Register for Output B EPWMxB AQSFRC 0x000D 1 No Action Qualifier Software Force Register AQCSFRC Ox000E 1 Yes Action Qualifier Continuous S W Force Register Set Dead Band Generator Submodule Registers DBCTL 0x000F 1 No Dead Band Generator Control Register DBRED 0x0010 1 No Dead Band Generator Rising Edge Delay Count Register DBFED 0x0011 1 No Dead Band Generator Falling Edge Delay Count Register Trip Zone Submodule Registers TZSEL 0x0012 1 No Trip Zone Select Register TZCTL 0x0014 1 No Trip Zone Control Register TZEINT 0x0015 1 No Trip Zone Enable Interrupt Register TZFLG 0x0016 1 No _ Trip Zone Flag Register TZCLR 0x0017 1 No Trip Zone Cle
104. l from the action qualifier is passed straight through to the EPWM xA input of the PWM chopper submodule The falling edge delayed signal is seen on output EPWMxB The input signal for the delay is determined by DBCTL IN_MODE 10 The rising edge delayed signal is seen on output EPWMKXA The input signal for the delay is determined by DBCTL IN_MODE Disable falling edge delay The EPWMxB signal from the action qualifier is passed straight through to the EPWMxB input of the PWM chopper submodule 11 Dead band is fully enabled for both rising edge delay on output EPWMxA and falling edge delay on output EPWMxB The input signal for the delay is determined by DBCTL IN_MODE 104 Registers SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com PWM Chopper Submodule Control Register Figure 4 14 Dead Band Generator Rising Edge Delay Register DBRED 15 10 9 8 Reserved DEL R 0 R W 0 7 0 DEL R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 14 Dead Band Generator Rising Edge Delay Register DBRED Field Descriptions Bits Name Value Description 15 10 Reserved Reserved 9 0 DEL Rising Edge Delay Count 10 bit counter Figure 4 15 Dead Band Generator Falling Edge Delay Register DBFED 15 10 9 8 Reserved DEL R 0 R W 0 DEL R W 0 LEGEND R W Read Write
105. l to period TBCTR TBPRD 011 Reserved 100 Enable event time base counter equal to CMPA when the timer is incrementing 101 Enable event time base counter equal to CMPA when the timer is decrementing 110 Enable event time base counter equal to CMPB when the timer is incrementing 111 Enable event time base counter equal to CMPB when the timer is decrementing 7 4 Reserved Reserved 3 INTEN Enable ePWM Interrupt EPWMx_INT Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation SPRU791D November 2004 Revised October 2007 Registers 111 Submit Documentation Feedback Wy TEXAS INSTRUMENTS www ti com Event Trigger Submodule Registers Table 4 23 Event Trigger Selection Register ETSEL Field Descriptions continued Bits Name Value Description 2 0 INTSEL ePWM Interrupt EPWMx_INT Selection Options 000 Reserved 001 Enable event time base counter equal to zero TBCTR 0x0000 010 Enable event time base counter equal to period TBCTR TBPRD 011 Reserved 100 Enable event time base counter equal to CMPA when the timer is incrementing 101 Enable event time base counter equal to CMPA when the timer is decrementing 110 Enable event time base counter equal to CMPB when the timer is incrementing 111 Enable event time base counter equal to CMPB when the timer is decrementing Figure 4 24 Event Trigger Prescale Register ETPS
106. leared when the TBCTR 0x0000 no matter where in the cycle the CBC flag is cleared This bit is cleared by writing the appropriate value to the TZCLR register Table 4 21 INT Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition No further EPWMx_TZINT PIE interrupts will be generated until this flag is cleared If the interrupt flag is cleared when either CBC or OST is set then another interrupt pulse will be generated Clearing all flag bits will prevent further interrupts This bit is cleared by writing the appropriate value to the TZCLR register Table 4 21 SPRU791D November 2004 Revised October 2007 Registers 109 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Event Trigger Submodule Registers Figure 4 21 Trip Zone Clear Register TZCLR 15 8 Reserved R 0 7 3 2 1 0 Reserved OST CBC INT R 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 21 Trip Zone Clear Register TZCLR Field Descriptions Bits Name Value Description 15 3 Reserved Reserved 2 OST Clear Flag for One Shot Trip OST Latch 0 Has no effect Always reads back a 0 1 Clears this Trip set condition 1 CBC Clear Flag for Cycle By Cycle CBC Trip Latch 0 Has no effect A
107. ling a 3 Phase Interleaved DC DC Converters eee ee e e eee e ee 85 3 9 Controlling Zero Voltage Switched Full Bridge ZVSFB Converter cs e eee e e e e x xe K ee 89 4 Sa I o E A E A A nieces dads ec E deeded edad dea cee nee eeatatieeae 93 4 1 Time Base Submodule ReQisters vcvo vez YE roy Se NET KERE EaR AK 95 Y YR Aaa aR YN KRA RER 94 4 2 Counter Compare Submodule ReGiSters cceceeeeeee eee re e eee eee 97 4 3 Action Qualifier Submodule ReQisterS cccseeeeeeeeeeeeeeeeeeeeeeeeeeeeeneeeeeeeeeeeeneeenaeeneeeeeneee 99 4 4 Dead Band Submodule Registers cce ees sse s esser reenn eee eenn 103 4 5 PWM Chopper Submodule Control ReQister cseceeeeeceeee ence eee eee eee eeeeeeeeeeeeeeeeeeneeeeeeenes 105 4 6 Trip Zone Submodule Control and Status Regisiera c ce e eee e e e e e e c ce e e ence eee eee 106 4 7 Event Trigger Submodule Registers cce ee eee e eee x xe r eee eenn 110 4 8 Proper Interrupt Initialization Procedure sss see c cesse eee e e e eens e r r x ee e ee eee e eee 115 A Revision HIStory aaas naaa aa aa Taa Rar E EE A E a E AEAEE ERES 117 Contents SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback List of Figures 1 1 Multiple CP WM Module sse ros YS Y SS ar rrr eN SN R temas EUN ER T ENR RSR RR AVR ER EK ER NSN 0 naa 1 2 Submodules and Signal Connections for an EPWM Module ses sss ssc ce e e e e e e e ee e e e r r ee eree 1 2 ePWM Submodules and Critical Internal Signal Interconnects cesse ee e e
108. lways reads back a 0 1 Clears this Trip set condition 0 INT Global Interrupt Clear Flag 0 Has no effect Always reads back a 0 1 Clears the trip interrupt flag for this ePWM module TZFLG INT NOTE No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared If the TZFLG INT bit is cleared and any of the other flag bits are set then another interrupt pulse will be generated Clearing all flag bits will prevent further interrupts Figure 4 22 Trip Zone Force Register TZFRC 15 8 Reserved R 0 7 3 2 1 0 Reserved OST CBC Reserved R 0 R W 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset 4 7 110 Table 4 22 Trip Zone Force Register TZFRC Field Descriptions Bits Name Value Description 15 3 Reserved Reserved 2 OST Force a One Shot Trip Event via Software 0 Writing of 0 is ignored Always reads back a 0 1 Forces a one shot trip event and sets the TZFLG OST bit 1 CBC Force a Cycle by Cycle Trip Event via Software 0 Writing of 0 is ignored Always reads back a 0 1 Forces a cycle by cycle trip event and sets the TZFLG CBC bit 0 Reserved Reserved Event Trigger Submodule Registers Figure 4 23 through Figure 4 27 and Table 4 23 through Table 4 27 describe the registers for the event trigger submodule Registers SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS
109. ly EPWMxA EPWMxB 56 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com PWM Chopper PC Submodule 2 6 4 1 One Shot Pulse The width of the first pulse can be programmed to any of 16 possible pulse width values The width or period of the first pulse is given by Tistpuise TsyscLkouT X 8 x OSHTWTH Where TsyscLkour S the period of the system clock SYSCLKOUT and OSHTWTH is the four control bits value from 1 to 16 Figure 2 33 shows the first and subsequent sustaining pulses and Table 7 3 gives the possible pulse width values for a SYSCLKOUT 100 MHZ Figure 2 33 PWM Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses T Start OSHT pulse EPWMXA in PSCLK Prog pulse width E OSHTWTH OSHT EPWM XA out II irl Sustaining pulses Table 2 16 Possible Pulse Width Values for SYSCLKOUT 100 MHz OSHTWTHz Pulse Width hex nS 0 80 160 240 320 400 480 560 640 720 800 880 960 1040 1120 1200 1280 TMmDUOOadDPFAAN DAP WD SPRU791D November 2004 Revised October 2007 ePWM Submodules 57 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com PWM Chopper PC Submodule 2 6 4 2 Duty Cycle Control 58 Pulse transformer based gate drive designs need to comprehend the magnetic pr
110. ly of processors SPRAA88 Using PWM Output as a Digital to Analog Converter on a TMS320F280x presents a method for utilizing the on chip pulse width modulated PWM signal generators on the TMS320F280x family of digital signal controllers as a digital to analog converter DAC SPRAAH1 Using the Enhanced Quadrature Encoder Pulse eQEP Module provides a guide for the use of the eQEP module as a dedicated capture unit and is applicable to the TMS320x280x 28xxx family of processors SPRA820 Online Stack Overflow Detection on the TMS320C28x DSP presents the methodology for online stack overflow detection on the TMS320C28x DSP C source code is provided that contains functions for implementing the overflow detection on both DSP BIOS and non DSP BIOS applications SPRA806 An Easy Way of Creating a C callable Assembly Function for the TMS320C28x DSP provides instructions and suggestions to configure the C compiler to assist with understanding of parameter passing conventions and environments expected by the C compiler Trademarks TMS320C28x C28x are trademarks of Texas Instruments SPRU791D November 2004 Revised October 2007 Read This First 11 Submit Documentation Feedback 12 Read This First SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback a TEXAS Chapter 1 IN STRUMENTS SPRU791D November 2004 Revised October 2007 Introduction The enhanced pulse width modulator ePWM per
111. me 2 shown in Figure 2 5 is used by the 2804x devices when the ePWM pinout is configured for A channel only mode GPAMCFG EPWMMODE 3 If the 2804x ePWM pinout is configured for 280x compatible mode GPAMCFG EPWMMODE 0 then Scheme 1 is used Figure 2 5 Time Base Counter Synchronization Scheme 2 EPWM1SYNCI ePWM1 EPWM1SYNCO SYNCI eCAP1 EPWM13SYNCI ePWM13 EPWM13SYnCO EPWM14SYNCI ePWM14 EPWM14SYNCO EPWM15SYNCI ePWM15 EPWM15SYNCO EPWM16SYNCI ePWM16 EPWM16SYNCO EPWM9SYNCI ePWM9 EPWM9SYNCO EPWM10SYNCI ePWM10 EPWM10SYNCO EPWM11SYNCI ePWM11 EPWM11SYNCO EPWM12SYNCI ePWM12 EPWM12SYNCO EPWMSSYNCI ePWM5 EPWMS5SYNCO EPWM6SYNCI ePWM6 EPWM36YNCO EPWM7SYNCI ePWM7 EPWM7SYNCO EPWM8SYNCI ePWM8 EPWM8SYNCO Scheme 3 shown in Figure 2 6 is used by all other devices 28 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback EPWM2SYNCI ePWM2 EPWM2SYNCO EPWM3SYNCI ePWM3 EPWM3SYNCO EPWM4SYNCI ePWM4 EPWM4SYNCO 4 TEXAS INSTRUMENTS www ti com Time Base TB Submodule Figure 2 6 Time Base Counter Synchronization Scheme 3 EPWM1SYNCI GPIO ePWM1 MUX SYNCI EPWM1SYNCO eCAP1 EPWM2SYNCI ePWM4 EPWM2SYNCO EPWM3SYNCI ePWM5 EPWM3SYNCO EPWM2SYNCI ePWM2 EPWM2SYNCO EPWM3SYNCI ePWM3 EPWM3SYNCO EPWMxSYNCI ePWM6 EPWMxSYNCO Each ePWM module can be configured to use or ignore the synchroni
112. mlRegs TBCTL bit PRDLD TB_SHADOW EPwmlRegs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwmlRegs TBCTL bit HSPCLKDIV TB_DIV1 EPwmlRegs TBCTL bit CLKDIV TB_DIV1 EPwmlRegs CMPCTL bit SHDWAMODE CC_SHADOW EPwmlRegs CMPCTL bit SHDWBMODE CC_SHADOW EPwmlRegs CMPCTL bit LOADAMODE CC_CTR_ZERO EPwmlRegs CMPCTL bit LOADBMODE CC_CTR_ZERO EPwmlRegs AQCTLA bit CAU AQ_SET EPwmlRegs AQCTLA bit CBU AQ_CLEAR EPwmlRegs AQCTLB bit ZRO AQ_TOGGLE Run Time Ve Se eS ee ee ee ee ee EPwmlRegs CMPA half CMPA EdgePosA EPwmlRegs CMPB EdgePosB Period 601 TBCLK counts Compare A 200 TBCLK counts Compare B 400 TBCLK counts Set Phase register to zero clear TB counter Phase loading disabled TBCLK SYSCLKOUT load on TBCTR Zero load on TBCTR Zero adjust duty for output EPWM1A only 46 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Action Qualifier AQ Submodule Figure 2 24 Up Down Count Dual Edge Symmetric Waveform With Independent Modulation on EPWMxA and EPWMxB Active Low TBCTR TBPRD value EPWMxA CB CB CB CB Aj oly 4 Ly EPWMxB PWM period 2 x TBPRD x Trgcik Duty modulation for EPWM xA is set by CMPA and is active low that is the low time duty
113. n although there are four stages SPRU791D November 2004 Revised October 2007 Applications to Power Topologies 71 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Controlling Multiple Buck Converters With Independent Frequencies Figure 3 3 Control of Four Buck Stages Here Fpwm Fpwm2 Fpwms Fewma ___ Ext Syncin Master1 optional Phase reg Syncin En Vini 0 N G o Vouti DX eo o gt EPWM1A Y EPWM1B CTR zero o Buck 1 GTRECMPP o EPWM1A __ _ SyncOut Master2 7 l Phase reg Syncin Vin2 o nan 6 o Vout2 mg Y X O K EPWM2A _ L EPWM2B ee T CTR zero o EPWM2A GIRECMPE o SyncOut Master3 Phase reg Syncin ee 9 Vin3 0 C WN o Vout3 X S i gt EPWM3A CTRezero o EPWM3B Buck 3 75 CTR CMPB a EPWM3A X SyncOut Master4 i i Phase reg Syncin Vin4 o INNA o o Vout4 En Y o xke o gt EPWM4A I Saring Buck 4 gt 4 CTR zero o EPWM4A SEE o SyncOut NOTE X indicates value in phase register is a don t care 72 Applications to Power Topologies SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Controlling Multiple Buck Converters With Independent Frequencies Figure 3 4 Buck Waveforms for Figure 3 3 Note Only three bucks shown
114. n 2 4 3 Corrected register name from TBCNTR to TBCTR in first paragraph and the Acton qualifier Event Priority table Figure 2 21 Modified figure Figure 2 22 Modified figure Figure 2 23 Modified figure Figure 2 25 Modified figure Figure 2 26 Modified figure Section 2 6 3 Corrected register name from CHPCTL to PCCTL in the first paragraph of the section on operational highlights for the PWM chopper Submodule Figure 2 31 Modified figure Figure 2 36 Modified figure Figure 2 37 Modified figure Table 4 24 Modified the descriptive name of the Event Trigger Prescale Register INTPRD field Figure 2 41 Corrected bit name ESOOCA to SOCAEN in the paragraph following the Event trigger Interrupt Generator figure Figure 2 42 Modified figure Figure 2 43 Modified figure Table 4 2 Modified the description of the Time base Phase Register TBPHS field Figure 4 4 Modified the reset value of the CTRMODE field in the Time Base Control Register TBCTL figure Table 4 4 Modified the bit description of SYNCOSEL in the TBCTL register field descriptions Table 4 5 Modified two field descriptions in the TBSTS register field descriptions table Figure 4 6 Corrected the CMPA Register figure changing 7 to 15 Table 4 7 Modified descriptions in CMPB Field Descriptions table Table 4 11 Changed AQCSF to AQCSFRC in the AQSFRC field descriptions table Table 4 12 Modified description of CSFB field in the AQCSFRC field descriptions table SPRU791D November 2004 Revised
115. n Count Tew 2 TBPRD 1 X TTBCLK Fpwm 1 Tpwm For Up and Down Count Tpwm 2 X TBPRD x TTBCLK Fpwm 1 Tpwm CTR_dir Up Down Up Down Time Base Period Shadow Register The time base period register TBPRD has a shadow register Shadowing allows the register update to be synchronized with the hardware The following definitions are used to describe all shadow registers in the ePWM module Active Register The active register controls the hardware and is responsible for actions that the hardware causes or invokes Shadow Register The shadow register buffers or provides a temporary holding location for the active register It has no direct effect on any control hardware At a strategic point in time the shadow register s content is transferred to the active register This prevents corruption or spurious operation due to the register being asynchronously modified by software The memory address of the shadow period register is the same as the active register Which register is written to or read from is determined by the TBCTL PRDLD bit This bit enables and disables the TBPRD shadow register as follows Time Base Period Shadow Mode The TBPRD shadow register is enabled when TBCTL PRDLD 0 Reads from and writes to the TBPRD memory address go to the shadow register The shadow register contents are transferred to the active register TBPRD Active lt TBPRD shadow when the time base counter equals zero TBCT
116. nitialization Time 77 555555555 SS SSeS SSeS EPwmlRegs TBPRD 600 Period 2x600 TBCLK counts EPwmlRegs CMPA half CMPA 350 Compare A 350 TBCLK counts EPwmlRegs CMPB 400 Compare B 400 TBCLK counts EPwmlRegs TBPHS 0 Set Phase register to zero EPwmlRegs TBCNT 0 clear TB counter EPwmlRegs TBCTL bit CTRMODE TB_UPDOWN Symmetric EPwmlRegs TBCTL bit PHSEN TB_DISABLE Phase loading disabled EPwmlRegs TBCTL bit PRDLD TB_SHADOW EPwmlRegs TBCTL bit SYNCOSEL TB_SYNC_DISABLE EPwmlRegs TBCTL bit HSPCLKDIV TB_DIV1 TBCLK SYSCLKOUT EPwmlRegs TBCTL bit CLKDIV TB_DIV1 EPwmlRegs CMPCTL bit SHDWAMODE CC_SHADOW EPwmlRegs CMPCTL bit SHDWBMODE CC_SHADOW EPwmlRegs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwmlRegs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwmlRegs AQCTLA bit CAU AQ_SET EPwmlRegs AQCTLA bit CAD AQ_CLEAR EPwmlRegs AQCTLB bit CBU AQ_CLEAR EPwmlRegs AQCTLB bit CBD AQ_SET Run Time JP 555555 SS SSeS Se Se SSE SE SSS EPwmlRegs CMPA half CMPA DutylA adjust duty for output EPWM1A EPwmlRegs CMPB Duty1B adjust duty for output EPWM1B 48 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Figure 2 26 Up Down Count Dual Edge Asymmetric Waveform With Independent Modulation on TBCTR A EPWMxA EP
117. nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications TI will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ticom Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller ti com Security www ti com security RFID www ti rfid c
118. not being properly initialized The proper procedure for initializing the ePWM peripheral is as follows 1 Disable Global Interrupts CPU INTM flag 2 Disable ePWM Interrupts 3 Initialize Peripheral Registers 4 Clear Any Spurious ePWM Flags including PIEIFR 5 Enable ePWM Interrupts 6 Enable Global Interrupts Figure 4 27 Event Trigger Force Register ETFRC 15 a Reserved R 0 7 4 3 2 1 0 Reserved SOCB SOCA Reserved INT R 0 R 0 R 0 R 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 4 27 Event Trigger Force Register ETFRC Field Descriptions Bits Name Value Description 15 4 Reserved Reserved 3 SOCB SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register The ETFLG SOCB flag bit will be set regardless 0 Has no effect Always reads back a 0 Generates a pulse on EPWMxSOCB and sets the SOCBFLG bit This bit is used for test purposes 2 SOCA SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register The ETFLG SOCA flag bit will be set regardless 0 Writing 0 to this bit will be ignored Always reads back a 0 Generates a pulse on EPWMxSOCA and set the SOCAFLG bit This bit is used for test purposes Reserved 0 Reserved 0 INT INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register The INT flag bit will be set rega
119. ntary ALC Active High AH Active Low i AL SPRU791D November 2004 Revised October 2007 ePWM Submodules 53 Submit Documentation Feedback Wy TEXAS INSTRUMENTS www ti com Dead Band Generator DB Submodule The dead band submodule supports independent values for rising edge RED and falling edge FED delays The amount of delay is programmed using the DBRED and DBFED registers These are 10 bit registers and their value represents the number of time base clock TBCLK periods a signal edge is delayed by For example the formula to calculate falling edge delay and rising edge delay are FED DBFED x Track RED DBRED x Track Where Traci is the period of TBCLK the prescaled version of SYSCLKOUT For convenience delay values for various TBCLK options are shown in Table 2 14 Table 2 14 Dead Band Delay Values in uS as a Function of DBFED and DBRED Dead Band Value Dead Band Delay in pS 7 DBFED DBRED TBCLK SYSCLKOUT 1 TBCLK SYSCLKOUT 2 TBCLK SYSCLKOUT 4 1 0 01 pS 0 02 uS 0 04 pS 5 0 05 uS 0 10 uS 0 20 pS 10 0 10 uS 0 20 uS 0 40 pS 100 1 00 uS 2 00 uS 4 00 uS 200 2 00 uS 4 00 uS 8 00 uS 300 3 00 uS 6 00 US 12 00 uS 400 4 00 uS 8 00 uS 16 00 uS 500 5 00 uS 10 00 uS 20 00 uS 600 6 00 uS 12 00 uS 24 00 uS 700 7 00 uS 14 00 uS 28 00 uS 800 8 00 uS 16 00 uS 32 00 uS 900 9 00 uS 18 00 uS 36 00 uS 1000 10 00 US 20 00 uS 40 00 uS Table values are calculated based on SYSCL
120. o loads possible 4 3 Action Qualifier Submodule Registers Figure 4 9 through Figure 4 12 and Table 4 9 through Table 4 12 provide the action qualifier submodule register definitions SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback Registers K TEXAS INSTRUMENTS www ti com Action Qualifier Submodule Registers Figure 4 9 Action Qualifier Output A Control Register AQCTLA 15 12 11 10 9 8 Reserved CBD CBU R 0 R W 0 R W 0 7 6 5 4 3 2 1 0 CAD CAU PRD ZRO R W 0 R W 0 R W 0 RW 0 LEGEND R W Read Write R Read only n value after reset Table 4 9 Action Qualifier Output A Control Register AQCTLA Field Descriptions Bits Name Value Description 15 12 Reserved Reserved 11 10 CBD Action when the time base counter equals the active CMPB register and the counter is decrementing 00 Do nothing action disabled 01 Clear force EPWMXA output low 10 Set force EPWMxA output high 11 Toggle EPWMxA output low output signal will be forced high and a high signal will be forced low 9 8 CBU Action when the counter equals the active CMPB register and the counter is incrementing 00 Do nothing action disabled 01 Clear force EPWMXA output low 10 Set force EPWMxA output high 11 Toggle EPWMxA output low output signal will be forced high and a high signal will be forced low 7 6 CAD Action when
121. of the ePWM time base counter during emulation events 00 Stop after the next time base counter increment or decrement 01 Stop when counter completes a whole cycle e Up count mode stop when the time base counter period TBCTR TBPRD s Down count mode stop when the time base counter 0x0000 TBCTR 0x0000 e Up down count mode stop when the time base counter 0x0000 TBCTR 0x0000 1X Free run 13 PHSDIR Phase Direction Bit This bit is only used when the time base counter is configured in the up down count mode The PHSDIR bit indicates the direction the time base counter TBCTR will count after a synchronization event occurs and a new phase value is loaded from the phase TBPHS register This is irrespective of the direction of the counter before the synchronization event In the up count and down count modes this bit is ignored 0 Count down after the synchronization event 1 Count up after the synchronization event 12 10 CLKDIV Time base Clock Prescale Bits These bits determine part of the time base clock prescale value TBCLK SYSCLKOUT HSPCLKDIV x CLKDIV 000 1 default on reset 001 2 010 4 011 8 100 16 101 32 110 64 111 128 9 7 HSPCLKDIV High Speed Time base Clock Prescale Bits These bits determine part of the time base clock prescale value TBCLK SYSCLKOUT HSPCLKDIV x CLKDIV This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager EV peripheral 000 A 001 2 de
122. ogether to control a full H bridge In this case both master and slave modules are required to switch at the same PWM frequency The phase is controlled by using the slave s phase register TBPHS The master s phase register is not used and therefore can be initialized to zero Figure 3 15 Controlling a Full H Bridge Stage Fpwm2 Fpwm1 Ext Syncin optional Master Phase reg Syncin En p 0 k4 o T K EPWM1A VDC bus l Vout CTR zero P EPWM1B CTR CMPB A A A A o SyncOut EPWM1A l EPWM2A E l Slave Eii Phase reg Syncin En i mA H A A L e omo EPWM1B EPWM2B gt O CTR zero o CTR CMPB X O SyncOut Var Variable Applications to Power Topologies 89 Submit Documentation Feedback 90 Controlling Zero Voltage Switched Full Bridge ZVSFB Converter Wy TEXAS INSTRUMENTS www ti com Figure 3 16 ZVS Full H Bridge Waveforms 600 200 Z CB CA A A EPWM1A Power phase 1200 Z CB v A RED ZVS transition i gt N EPWM1B 4 ke FED ZVS transition TBPHS 1200 2 EPWM2A EPWM2B Power phase Applications to Power Topologies gt 300 2 variable
123. om Telephony www ti com telephony Low Power www ti com lpw Video amp Imaging www ti com video Wireless Wireless www ti com wireless Mailing Address Texas Instruments Post Office Box 655303 Dallas Texas 75265 Copyright 2007 Texas Instruments Incorporated
124. ompare registers the counter compare unit generates an appropriate event The counter compare e Generates events based on programmable time stamps using the CMPA and CMPB registers CTR CMPA Time base counter equals counter compare A register TBCTR CMPA CTR CMPB Time base counter equals counter compare B register TBCTR CMPB e Controls the PWM duty cycle if the action qualifier submodule is configured appropriately e Shadows new compare values to prevent corruption or glitches during the active PWM cycle 2 3 2 Controlling and Monitoring the Counter Compare Submodule The counter compare submodule operation is controlled and monitored by the registers shown in Table 2 4 Table 2 4 Counter Compare Submodule Registers Register Name Address Offset Shadowed Description CMPCTL 0x0007 No Counter Compare Control Register CMPAHR 0x0008 Yes HRPWM Counter Compare A Extension Register 7 CMPA 0x0009 Yes Counter Compare A Register CMPB 0x000A Yes Counter Compare B Register UI This register is available only on ePWM modules with the high resolution extension HRPWM On ePWM modules that do not include the HRPWM this location is reserved This register is described in the TMS320x28xx 28xxx High Resolution Pulse Width Modulator HRPWM Reference Guide SPRU924 Refer to the device specific data manual to determine which ePWM instances include this feature Figure 2 12 Detailed View of the Counter Compare Submodule TB
125. on software for execution from on chip flash memory Requirements for both DSP BIOS and non DSP BIOS projects are presented Example code projects are included SPRAA91 TMS320F280x DSC USB Connectivity Using TUSB3410 USB to UART Bridge Chip presents hardware connections as well as software preparation and operation of the development system using a simple communication echo program SPRAA58 TMS320x281x to TMS320x280x Migration Overview describes differences between the Texas Instruments TMS320x281x and TMS320x280x DSPs to assist in application migration from the 281x to the 280x While the main focus of this document is migration from 281x to 280x users considering migrating in the reverse direction 280x to 281x will also find this document useful SPRAAD8 TMS320280x and TMS320F2801x ADC Calibration describes a method for improving the absolute accuracy of the 12 bit ADC found on the TMS320280x and TMS3202801x devices Inherent gain and offset errors affect the absolute accuracy of the ADC The methods described in this report can improve the absolute accuracy of the ADC to levels better than 0 5 This application report has an option to download an example program that executes from RAM on the F2808 EzDSP SPRAAI1 Using Enhanced Pulse Width Modulator ePWM Module for 0 100 Duty Cycle Control provides a guide for the use of the ePWM module to provide 0 to 100 duty cycle control and is applicable to the TMS320x280x fami
126. operties or characteristics of the transformer and associated circuitry Saturation is one such consideration To assist the gate drive designer the duty cycles of the second and subsequent pulses have been made programmable These sustaining pulses ensure the correct drive strength and polarity is maintained on the power switch gate during the on period and hence a programmable duty cycle allows a design to be tuned or optimized via software control Figure 2 34 shows the duty cycle control that is possible by programming the CHPDUTY bits One of seven possible duty ratios can be selected ranging from 12 5 to 87 5 Figure 2 34 PWM Chopper Submodule Waveforms Showing the Pulse Width Duty Cycle Control of Sustaining Pulses PSCLK PSCLK P s P period 75 50 25 PSCLK Period 87 5 62 5 37 5 12 5 Duty 1 8 Duty 2 8 Duty 3 8 Duty 4 8 Duty 5 8 Duty 6 8 Duty 7 8 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback Ww TEXAS INSTRUMENTS www ti com Trip Zone TZ Submodule 2 7 Trip Zone TZ Submodule Figure 2 35 shows how the trip zone TZ submodule fits within the ePWM module Figure 2 35 Trip Zone Submodule _CTR PRD EPWMxINT CTR 0 PIE gt Trigger CTR CMPA EPWMxSOCA o yp SEPWMXS YNGI CTR PRD JL CTR CMPB a EPWMxSYNCO ae CTR 0 J
127. ot load the time base counter TBCTR from the time base phase register TBPHS Load the time base counter with the phase register when an EPWMxSYNCI input signal occurs or when a software synchronization is forced by the SWFSYNC bit CTRMODE 00 01 10 11 Counter Mode The time base counter mode is normally configured once and not changed during normal operation If you change the mode of the counter the change will take effect at the next TBCLK edge and the current counter value shall increment or decrement from the value before the mode change These bits set the time base counter mode of operation as follows Up count mode Down count mode Up down count mode Stop freeze counter operation default on reset 96 Registers SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com Counter Compare Submodule Registers Figure 4 5 Time Base Status Register TBSTS 15 8 Reserved R 0 7 3 2 1 0 Reserved CTRMAX SYNCI CTRDIR R 0 R W1C 0 R W1C 0 R 1 LEGEND R W Read Write R Read only R W1C Read Write 1 to clear n value after reset Table 4 5 Time Base Status Register TBSTS Field Descriptions Bit Field Value Description 15 3 Reserved Reserved 2 CTRMAX Time Base Counter Max Latched Status Bit Reading a 0 indicates the time base counter never reached its maximum value Writ
128. r is continuously compared to the time base counter TBCTR When the values are equal the counter compare module generates a time base counter equal to counter compare A event This event is sent to the action qualifier where it is qualified and converted it into one or more actions These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers The actions that can be defined in the AQCTLA and AQCTLB registers include s Do nothing the event is ignored s Clear Pull the EPWMxA and or EPWMxB signal low s Set Pull the EPWMxA and or EPWMxB signal high e Toggle the EPWMxA and or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL SHDWAMODE bit By default this register is shadowed s If CMPCTL SHDWAMODE 0 then the shadow is enabled and any write or read will automatically go to the shadow register In this case the CMPCTL LOADAMODE bit field determines which event will load the active register from the shadow register s Before a write the CMPCTL SHDWAFULL bit can be read to determine if the shadow register is currently full s If CMPCTL SHDWAMODE 1 then the shadow register is disabled and any write or read will go directly to the active register that is the register actively controlling the hardware e In either mode the active and shadow registers share the same memory map address 15 Figure 4 7 Counter Compare B
129. rce for this ePWM module Enable TZ4 as a CBC trip source for this ePWM module CBC3 Trip zone 3 TZ3 Select Disable TZ3 as a CBC trip source for this ePWM module Enable TZ3 as a CBC trip source for this ePWM module SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback Registers 107 Wy TEXAS INSTRUMENTS www ti com Trip Zone Submodule Control and Status Registers Table 4 17 Trip Zone Submodule Select Register TZSEL Field Descriptions continued Bits Name Value Description 1 CBC2 Trip zone 2 TZ2 Select 0 Disable TZ2 as a CBC trip source for this eP WM module 1 Enable TZ2 as a CBC trip source for this eP WM module 0 CBC Trip zone 1 TZT Select 0 Disable TZT as a CBC trip source for this eP WM module 1 Enable TZT as a CBC trip source for this eP WM module Figure 4 18 Trip Zone Control Register TZCTL 15 8 Reserved R 0 Reserved TZB TZA R 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 18 Trip Zone Control Register TZCTL Field Descriptions Bits Name Value Description 15 4 Reserved Reserved 3 2 TZB When a trip event occurs the following action is taken on output EPWMxB Which trip zone pins can cause an event is defined in the TZSEL register Table 4 17 00 High impedance EPWMxB High impedance state 01 Force EPWMxB to a high state 10 Force EPWMxgB to a lo
130. rdless 0 Writing 0 to this bit will be ignored Always reads back a 0 Generates an interrupt on EPWMxINT and set the INT flag bit This bit is used for test purposes SPRU791D November 2004 Revised October 2007 Registers 115 Submit Documentation Feedback 116 Registers SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback A TEXAS INSTRUMENTS Appendix A SPRU791D November 2004 Revised October 2007 Revision History This document was revised to SPRU791D from SPRU791C The scope of the revision was limited to technical changes as shown in Table A 1 Table A 1 Changes for Revision D Location Modifications Additions and Deletions Figure 2 12 Modified the Detailed View of the Counter compare Submodule figure Section 2 2 3 Corrected register name from TBCTRL to TBCTL in the second paragraph of calculating PWM Period and Frequency Figure 2 2 Modified figure Figure 2 13 Modified the Counter compare Event Waveforms in Up count Mode figure and the Counter compare Events in Down count Mode figure Figure 2 5 Modified figure Figure 2 6 Added new figure for synchronization scheme 3 Figure 2 12 Modified figure Figure 2 18 Modified figure Table 2 7 Corrected register name from AQCSF to AQCSFRC in the paragraph following the Action qualifier submodule Possible Input Events Sectio
131. re the ePWM2 registers as follows TZSEL OSHT1 1 enables TZT as a one shot event source for ePWM2 TZCTL TZA 1 EPWM2A will be forced high on a trip event TZCTL TZB 1 EPWM2B will be forced high on a trip event Scenario B _ A cycle by cycle event on TZ5 pulls both EPWM1A EPWM1B low A one shot event on TZ1 or TZ6 puts EPWM2A into a high impedance state e Configure the ePWM1 registers as follows TZSEL CBC5 1 enables TZ5 as a one shot event source for ePWM1 TZCTL TZA 2 EPWM1A will be forced low on a trip event TZCTL TZB 2 EPWM1B will be forced low on a trip event e Configure the ePWM2 registers as follows TZSEL OSHT1 1 enables TZT as a one shot event source for ePWM2 TZSEL OSHTE6 1 enables TZ6 as a one shot event source for ePWM1 TZCTL TZA 0 EPWM1A will be put into a high impedance state on a trip event TZCTL TZB 3 EPWM1B will ignore the trip event SPRU791D November 2004 Revised October 2007 ePWM Submodules 61 Submit Documentation Feedback Trip Zone TZ Submodule 2 7 4 Generating Trip Event Interrupts 62 3 TEXAS INSTRUMENTS www ti com Figure 2 36 and Figure 2 37 illustrate the trip zone submodule control and interrupt logic respectively EPWMxA EPWMxB Figure 2 36 Trip Zone Submodule Mode Control Logic TZCTL TZB TZCTL TZA EPWMxA CTR zero TZFRC CBC TZCLR OST TZFRC OSHT ePWM Submodules
132. rrupts are disabled ETSEL INT 0 or the interrupt flag is set ETFLG INT 1 the counter will stop counting events when it reaches the period value ETPS INTCNT ETPS INTPRD No events have occurred 1 event has occurred 2 events have occurred 3 events have occurred 1 0 INTPRD 00 01 10 11 ePWM Interrupt EPWMx_INT Period Select These bits determine how many selected ETSEL INTSEL events need to occur before an interrupt is generated To be generated the interrupt must be enabled ETSEL INT 1 If the interrupt status flag is set from a previous interrupt ETFLG INT 1 then no interrupt will be generated until the flag is cleared via the ETCLR INT bit This allows for one interrupt to be pending while another is still being serviced Once the interrupt is generated the ETPS INTCNT bits will automatically be cleared Writing a INTPRD value that is the same as the current counter value will trigger an interrupt if it is enabled and the status flag is clear Writing a INTPRD value that is less than the current counter value will result in an undefined state If a counter event occurs at the same instant as a new zero or non zero INTPRD value is written the counter is incremented Disable the interrupt event counter No interrupt will be generated and ETFRC INT is ignored Generate an interrupt on the first event INTCNT 01 first event Generate interrupt on ETPS INTCNT 1 0 Second event
133. s Bit Field Value Description 15 8 Reserved 7 6 RLDCSF AQCSFRC Active Register Reload From Shadow Options 00 Load on event counter equals zero 01 Load on event counter equals period 10 Load on event counter equals zero or counter equals period 11 Load immediately the active register is directly accessed by the CPU and is not loaded from the shadow register 5 OTSFB One Time Software Forced Event on Output B 0 Writing a 0 zero has no effect Always reads back a 0 This bit is auto cleared once a write to this register is complete i e a forced event is initiated This is a one shot forced event It can be overridden by another subsequent event on output B 1 Initiates a single s w forced event 4 3 ACTSFB Action when One Time Software Force B Is invoked 00 Does nothing action disabled 01 Clear low 10 Set high 11 Toggle Low gt High High gt Low Note This action is not qualified by counter direction CNT_dir 2 OTSFA One Time Software Forced Event on Output A 0 Writing a 0 zero has no effect Always reads back a 0 This bit is auto cleared once a write to this register is complete i e a forced event is initiated 1 Initiates a single software forced event 1 0 ACTSFA Action When One Time Software Force A Is Invoked 00 Does nothing action disabled 01 Clear low 10 Set high 11 Toggle Low High High Low Note This action is not qualified by counter
134. s Introduction SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Submodule Overview Figure 1 1 Multiple ePWM Modules xSYNCI EPWMI1INT EPWM1A EPWM1SOC ePWM1 module EPWM1B ToeCAP1i xSYNCO EPWM2INT EPWM2A EPWM2SOC ePWM2 module EPWM2B EPWMxINT EPWMxSOC ePWMx module Peripheral Frame 1 ADC The order in which the ePWM modules are connected may differ from what is shown in Figure 1 1 See Section 2 2 3 2 for the synchronization scheme for a particular device Each ePWM module consists of seven submodules and is connected within a system via the signals shown in Figure 1 2 SPRU791D November 2004 Revised October 2007 Introduction 15 Submit Documentation Feedback 3 TEXAS INSTRUMENTS Submodule Overview 16 www ti com Figure 1 2 Submodules and Signal Connections for an ePWM Module EPWMxSYNCI S S EPWMxSYNCO ime base TB module Counter compare CC module EPWMXTZINT Action qualifier AQ module PIE EPWMxINT oe Dead band DB module 121 to TZ6 EPWMxSOCA EPWMxA GPIO PWM ch P T ADC EPWMxSOCB chopper PC module Sns EPWMxB Event trigger ET module Peripheral bus Trip zone TZ module Figure 1 3 shows more internal details of a single ePWM module The main signals used by the ePWM module are PWM output signals EPWMxA and EPWMxB
135. s The dead band submodule has two groups of independent selection options as shown in Figure 2 28 EPWM xA in EPWMxs in Input Source Selection The input signals to the dead band module are the EPWMxA and EPWMxB output signals from the action qualifier In this section they will be referred to as EPWMxA In and EPWMxB In Using the DBCTL IN_MODE control bits the signal source for each delay falling edge or rising edge can be selected EPWM A In is the source for both falling edge and rising edge delay This is the default mode EPWM A In is the source for falling edge delay EPWMxB In is the source for rising edge delay EPWM A In is the source for rising edge delay EPWMxB In is the source for falling edge delay EPWM xgB In is the source for both falling edge and rising edge delay Output Mode Control The output mode is configured by way of the DBCTL OUT_MODE bits These bits determine if the falling edge delay rising edge delay neither or both are applied to the input signals Polarity Control The polarity control DBCTL POLSEL allows you to specify whether the rising edge delayed signal and or the falling edge delayed signal is to be inverted before being sent out of the dead band submodule Figure 2 28 Configuration Options for the Dead Band Submodule Rising edge EPWMxA s4 delay RED Q O L n ou lr _ o 1 10 bit coun
136. s are generated and how the EPWMxSYNCI signal interacts Figure 2 13 Counter Compare Event Waveforms in Up Count Mode TBCTR 15 0 2 OxFFFF TBPRD gt value CMPA value CMPB __ value TBPHS value 0x0000 9 EPWMxSYNCI h CTR CMPA jl l CTR CMPB l NOTE An EPWMxSYNCI external synchronization event can cause a discontinuity in the TBCTR count sequence This can lead to a compare event being skipped This skipping is considered normal operation and must be taken into account Figure 2 14 Counter Compare Events in Down Count Mode TBCTR 15 0 A OxFFFF TBPRD value CMPA value CMPB value TBPHS value 0x0000 E EPWMxSYNCI T CTR CMPA jl CTR CMPB l l gt gt SPRU791D November 2004 Revised October 2007 ePWM Submodules 35 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com Counter Compare CC Submodule Figure 2 15 Counter Compare Events In Up Down Count Mode TBCTL PHSDIR 0 Count Down On Synchronization Event TBCTR 15 0 A OxFFFF L TBPRD value CMPA value gt CMPB value gt TBPHS value 0x0000 E EPWMxSYNCI CTR CMPB gt CTR CMPA Oo Figure 2 16 Counter Compare Events In Up Down Count Mode TBCTL PHSDIR 1 Count Up On Synchronization Even
137. se register to zero Asymmetrical mode Phase loading disabled load on CTR Zero load on CTR Zero Period 801 TBCLK counts Set Phase register to zero Phase loading disabled load on CTR Zero load on CTR Zero instant adjust duty for output EPWMI1A adjust duty for output EPWM2A adjust duty for output EPWM3A 74 Applications to Power Topologies SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com 3 4 Controlling Multiple Buck Converters With Same Frequencies If synchronization is a requirement ePWM module 2 can be configured as a slave and can operate at Controlling Multiple Buck Converters With Same Frequencies integer multiple N frequencies of module 1 The sync signal from master to slave ensures these modules remain locked Figure 3 5 shows such a configuration Figure 3 6 shows the waveforms generated by the configuration Figure 3 5 Control of Four Buck Stages Note Fpwm2 N x Fpwm1 Ext Syncin optional Master Phase reg Syncin Vini EPWM1A Vin2 0 En 0 4 OO CTR zero CTR CMPB O Xx O SyncOut Slave Phase reg Syncin X K EPWM1A EPWM1B EPWM1B Vin3 0 EPWM2A CTR zero O CTR CMPB O X O SyncOut gt EPWM2A EPWM2B Vin4 o EPWM2B SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback
138. specifications applicable at the time of sale in accordance with TIS standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limit
139. ssible events will trigger an interrupt or start an ADC conversion ETPS This programs the event prescaling options mentioned above ETFLG These are flag bits indicating status of the selected and prescaled events ETCLR These bits allow you to clear the flag bits in the ETFLG register via software ETFRC These bits allow software forcing of an event Useful for debugging or s w intervention A more detailed look at how the various register bits interact with the Interrupt and ADC start of conversion logic are shown in Figure 2 41 Figure 2 42 and Figure 2 43 Figure 2 41 shows the event trigger s interrupt generation logic The interrupt period ETPS INTPRD bits specify the number of events required to cause an interrupt pulse to be generated The choices available are Do not generate an interrupt Generate an interrupt on every event Generate an interrupt on every second event Generate an interrupt on every very third event Which event can cause an interrupt is configured by the interrupt selection ETSEL INTSEL bits The event can be one of the following SPRU791D November 2004 Revised October 2007 Time base counter equal to zero TBCTR 0x0000 Time base counter equal to period TBCTR TBPRD Time base counter equal to the compare A register CMPA Time base counter equal to the compare A register CMPA Time base counter equal to the compare B register CMPB Time base counter equal to the compare B register CMPB
140. t TBCTR 15 0 OxFFFF TBPRD N value CMPA BI value CMPB __ value TBPHS _ value 0x0000 EPWMxSYNCI CTR CMPB jl j l CTR CMPA il fl 36 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com Action Qualifier AQ Submodule 2 4 Action Qualifier AQ Submodule Figure 2 17 shows the action qualifier AQ submodule see shaded block in the ePWM system Figure 2 17 Action Qualifier Submodule _CTR PRD p PE Event LEPWMRINT p PiE gt Trigger CTR CMPA and EPWMxSOCA Ee Ne CTR PRD JL CTR CMPB Interrupt ne p EPWMxSYNCO E CTR 0 JL CTR_Dir ET EPWMxSOCB T CTR_Dir EPWMxA JL CTR CMPA ae EPWMxB MUX gt TZ1 to TZ6 4 Counter Compare CC CTR CMPB JL EPWMxTZINT The action qualifier submodule has the most important role in waveform construction and PWM generation It decides which events are converted into various action types thereby producing the required switched waveforms at the EPWMxA and EPWMxB outputs 2 4 1 Purpose of the Action Qualifier Submodule The action qualifier submodule is responsible for the following e Qualifying and generating actions set clear toggle based on the following events CTR PRD Time base counter equal to the period TBCTR
141. t CBD 3 Counter equals CMPA on up count CAU Counter equals CMPA on down count CAD 4 Counter equals zero Counter equals period TBPRD 5 Counter equals CMPB on down count CBD Counter equals CMPB on up count CBU 71 6 Lowest Counter equals CMPA on down count CAD Counter equals CMPA on up count CBU UI To maintain symmetry for up down count mode both up events CAU CBU and down events CAD CBD can be generated for TBPRD Otherwise up events can occur only when the counter is incrementing and down events can occur only when the counter is decrementing Table 2 9 shows the action qualifier priority for up count mode In this case the counter direction is always defined as up and thus down count events will never be taken Table 2 9 Action Qualifier Event Priority for Up Count Mode Priority Level Event 1 Highest Software forced event 2 Counter equal to period TBPRD 3 Counter equal to CMPB on up count CBU 4 Counter equal to CMPA on up count CAU 5 Lowest Counter equal to Zero Table 2 10 shows the action qualifier priority for down count mode In this case the counter direction is always defined as down and thus up count events will never be taken Table 2 10 Action Qualifier Event Priority for Down Count Mode Priority Level Event 1 Highest Software forced event 2 Counter equal to Zero 3 Counter equal to CMPB on down count CBD 4 Counter equal to CMPA on down count CAD 5 Lowes
142. t Counter equal to period TBPRD It is possible to set the compare value greater than the period In this case the action will take place as shown in Table 2 11 SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 40 ePWM Submodules K TEXAS INSTRUMENTS www ti com Action Qualifier AQ Submodule Table 2 11 Behavior if CMPA CMPB is Greater than the Period Counter Mode Compare on Up Count Event Compare on Down Count Event CAU CBU CAU CBU Up Count Mode If CMPA CMPB lt TBPRD period then the event Never occurs occurs on a compare match TBCTR CMPA or CMPB If CMPA CMPB gt TBPRD then the event will not occur Down Count Mode Never occurs If CMPA CMPB lt TBPRD the event will occur on a compare match TBCTR CMPA or CMPB If CMPA CMPB gt TBPRD the event will occur on a period match TBCTR TBPRD Up Down Count If CMPA CMPB lt TBPRD and the counter is If CMPA CMPB lt TBPRD and the counter is Mode incrementing the event occurs on a compare match decrementing the event occurs on a compare match TBCTR CMPA or CMPB TBCTR CMPA or CMPB If CMPA CMPB is gt TBPRD the event will occur ona If CMPA CMPB gt TBPRD the event occurs on a period match TBCTR TBPRD period match TBCTR TBPRD 2 4 4 Waveforms for Common Configurations Note The waveforms in this document show the ePWMs behavior for a static compare register value In a running system the active compare registers
143. t SHDWBMODE CC_SHADOW EPwmlRegs CMPCTL bit LOADAMODE CC_CTR_ZERO EPwmlRegs CMPCTL bit LOADBMODE CC_CTR_ZERO EPwmlRegs AQCTLA bit CAU AQ_SET EPwmlRegs AQCTLA bit CBD AQ_CLEAR EPwmlRegs AQCTLB bit ZRO AQ_CLEAR EPwmlRegs AQCTLB bit PRD AQ_SET Run Time J EPwmlRegs CMPA half CMPA EdgePosA EPwmlRegs CMPB EdgePosB Period Compare A Compare B 2 x 600 TBCLK counts 250 TBCLK counts 450 TBCLK counts Set Phase register to zero clear TB counter Symmetric Phase loading disabled TBCLK load on CTR load on CTR adjust duty SYSCLKOUT Zero Zero for output EPWM1A only SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback ePWM Submodules 49 K TEXAS INSTRUMENTS www ti com Dead Band Generator DB Submodule 2 5 Dead Band Generator DB Submodule Figure 2 27 illustrates the dead band submodule within the ePWM module Figure 2 27 Dead_Band Submodule _CTR PRD EPWNKINT CTR 0 Event 7 p gt PIE e Trigger CTR CMPA and EPWMxSOCA 5 EP WMS ING CTR PRD JL CTR CMPB Interrupt ADC EPWMxSYNCO bara CTR_Dir ET EPWMxSOCB 5 EPWMxA JL CTR CMPA GPO Counter Compare CC CTR CMPB JL 2 5 1 Purpose of the Dead Band Submodule The Action qualifier AQ Module section discussed how it is possible to generate the required TZ1 to TZ6 4 EPWMxTZINT EPWMxB MUX gt
144. t can be pending while the ETFLG INT bit is still set If an interrupt is pending it will not be generated until after the ETFLG INT bit is cleared Refer to Figure 2 41 Figure 4 26 Event Trigger Clear Register ETCLR 15 l Reserved R 0 7 4 3 2 1 0 Reserved SOCB SOCA Reserved INT R 0 R W 0 R W 0 R 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 26 Event Trigger Clear Register ETCLR Field Descriptions Bits Name Value Description 15 4 Reserved Reserved 3 SOCB ePWM ADC Start of Conversion B EPWMxSOCB Flag Clear Bit 0 Writing a 0 has no effect Always reads back a 0 1 Clears the ETFLG SOCB flag bit 2 SOCA ePWM ADC Start of Conversion A EPWMxSOCA Flag Clear Bit 0 Writing a 0 has no effect Always reads back a 0 1 Clears the ETFLG SOCA flag bit 1 Reserved Reserved 0 INT ePWM Interrupt EPWMx_INT Flag Clear Bit 0 Writing a 0 has no effect Always reads back a 0 1 Clears the ETFLG INT flag bit and enable further interrupts pulses to be generated 114 Registers SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback ki TEXAS INSTRUMENTS www ti com Proper Interrupt Initialization Procedure 4 8 Proper Interrupt Initialization Procedure When the ePWM peripheral clock is enabled it may be possible that interrupt flags may be set due to spurious events due to the ePWM registers
145. t trigger submodule fits within the ePWM system Figure 2 38 Event Trigger Submodule CTR PRD eer _ gt EPWMxINT CTR 0 l gt Trigger acion CTR CMPA EPWMxSOCA aes CTR PRD JL AQ CTR CMPB __ gt EPWMxSYNCO ba CTR_Dir EPWMxSOCB e CTR Dir EPWMxA X C CTR CMPA JL Counter EPWMxB Compare CC CTR CMPBJL a EPWMXTZINT 4 TZ to TZ6 L SPRU791D November 2004 Revised October 2007 ePWM Submodules 63 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com Event Trigger ET Submodule 2 8 1 Operational Overview of the Event Trigger Submodule The following sections describe the event trigger submodule s operational highlights Each ePWM module has one interrupt request line connected to the PIE and two start of conversion signals one for each sequencer connected to the ADC module As shown in Figure 2 39 ADC start of conversion for all ePWM modules are ORed together and hence multiple modules can initiate an ADC start of conversion If two requests occur on one start of conversion line then only one will be recognized by the ADC Figure 2 39 Event Trigger Submodule Inter Connectivity of ADC Start of Conversion and Interrupt Signals EPWMI1INT EPwm1 EPWM1SOCA module Epwm1SOCB EPWWV2INT EPWM2 EPWM2SOCA PIE module EPWM2SOCB EPWIVxINT EPWMx EPWMxSOCA module T EpwmxSOCB SOCB SOC
146. tation Feedback Applications to Power Topologies 91 92 Applications to Power Topologies SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback a TEXAS Chapter 4 IN STRUMENTS SPRU791D November 2004 Revised October 2007 Registers This chapter includes the register layouts and bit description for the submodules Topic Page 4 1 Time Base Submodule Registers 2 0 ceceeeeeeeeeeeeeeeeeeeeeees 94 4 2 Counter Compare Submodule RegisterS c eeeeeeeeeeeeees 97 4 3 Action Qualifier Submodule RegisterS 2 ceeceeeeeeeeeeeee 99 4 4 Dead Band Submodule Registers 2 ecceeeeeeeeeeeeeeeeeeeees 103 4 5 PWM Chopper Submodule Control Register sees sees eee eee 105 4 6 Trip Zone Submodule Control and Status Registers 106 4 7 Event Trigger Submodule Registers esse sees essere 110 4 8 Proper Interrupt Initialization Procedure ccceceeeeeeeeees 115 SPRU791D November 2004 Revised October 2007 Registers 93 Submit Documentation Feedback Wy TEXAS INSTRUMENTS www ti com Time Base Submodule Registers 4 1 Time Base Submodule Registers Figure 4 1 through Figure 4 5 and Table 4 1 through Table 4 5 provide the time base register definitions 15 Figure 4 1 Time Base Period Register TBPRD 0 TBPRD R W 0 LEGEND R W Read Write R Read only n value after reset Table
147. ter Falling edge 0 S5 delay FED 1 so EPWMxB O In O Sot gt 1 10 bit counter l n l m d DBCTL IN_MODE DBCTL POLSEL DBCTL OUT_MODE Although all combinations are supported not all are typical usage modes Table 2 13 documents some classical dead band configurations These modes assume that the DBCTL IN_MODE is configured such that EPWMXA In is the source for both falling edge and rising edge delay Enhanced or non traditional modes can be achieved by changing the input signal source The modes shown in Table 2 13 fall into the following categories Mode 1 Bypass both falling edge delay FED and rising edge delay RED Allows you to fully disable the dead band submodule from the PWM signal path Mode 2 5 Classical Dead Band Polarity Settings These represent typical polarity configurations that should address all the active high low modes required by available industry power switch gate drivers The waveforms for these typical cases are shown in Figure 2 29 Note that to generate equivalent waveforms to Figure 2 29 configure the SPRU791D November 2004 Revised October 2007 ePWM Submodules 51 Submit Documentation Feedback Wy TEXAS INSTRUMENTS www ti com Dead Band Generator DB Submodule action qualifier submodule to generate the signal as shown for EPWMXA s Mode 6 Bypass rising edge delay and Mode 7 Bypass falling edge delay Finally th
148. the counter equals the active CMPA register and the counter is decrementing 00 Do nothing action disabled 01 Clear force EPWMXA output low 10 Set force EPWMxA output high 11 Toggle EPWMxA output low output signal will be forced high and a high signal will be forced low 5 4 CAU Action when the counter equals the active CMPA register and the counter is incrementing 00 Do nothing action disabled 01 Clear force EPWMXA output low 10 Set force EPWMxA output high 11 Toggle EPWMxA output low output signal will be forced high and a high signal will be forced low 3 2 PRD Action when the counter equals the period Note By definition in count up down mode when the counter equals period the direction is defined as 0 or counting down 00 Do nothing action disabled 01 Clear force EPWMXA output low 10 Set force EPWMxA output high 11 Toggle EPWMxA output low output signal will be forced high and a high signal will be forced low 1 0 ZRO Action when counter equals zero Note By definition in count up down mode when the counter equals 0 the direction is defined as 1 or counting up 00 Do nothing action disabled 01 Clear force EPWMXA output low 10 Set force EPWMxA output high 11 Toggle EPWMxA output low output signal will be forced high and a high signal will be forced low 100 Registers SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMEN
149. the shadow register is disabled and any write or read will go directly to the active register that is the register actively controlling the hardware e In either mode the active and shadow registers share the same memory map address 98 Registers SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Action Qualifier Submodule Registers Figure 4 8 Counter Compare Control Register CMPCTL 15 10 9 8 Reserved SHDWBFULL SHDWAFULL R 0 R 0 R 0 7 6 5 4 3 2 1 0 Reserved SHDWBMODE Reserved SHDWAMODE LOADBMODE LOADAMODE R 0 R W 0 R 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 8 Counter Compare Control Register CMPCTL Field Descriptions Bits Name Value Description 15 10 Reserved Reserved SHDWBFULL Counter compare B CMPB Shadow Register Full Status Flag This bit self clears once a load strobe occurs CMPB shadow FIFO not full yet Indicates the CMPB shadow FIFO is full a CPU write will overwrite current shadow value SHDWAFULL Counter compare A CMPA Shadow Register Full Status Flag The flag bit is set when a 32 bit write to CMPA CMPAHR register or a 16 bit write to CMPA register is made A 16 bit write to CMPAHR register will not affect the flag This bit self clears once a load strobe occurs CMPA shadow FIFO not full yet Indicates the CMPA sha
150. tion in Figure 3 13 Config Initialization Time ssssssssssssssssssssssss EPWM Module 1 config EPwmlRegs TBPRD 450 Period 900 TBCLK counts EPwmlRegs TBPHS 0 Set Phase register to zero EPwmlRegs TBCTL bit CTRMODE TB_COUNT_UPDOWN Symmetrical mode EPwmlRegs TBCTL bit PHSEN TB_DISABLE Master module EPwmlRegs TBCTL bit PRDLD TB_SHADOW EPwmlRegs TBCTL bit SYNCOSEL TB_CTR_ZERO Syne down stream module EPwmlRegs CMPCTL bit SHDWAMODE CC_SHADOW EPwmlRegs CMPCTL bit SHDWBMODE CC_SHADOW EPwmlRegs CMPCTL bit LOADAMODE CC_CTR_ZERO load on CTR Zero EPwmlRegs CMPCTL bit LOADBMODE CC_CTR_ZERO load on CTR Zero EPwmlRegs AQCTLA bit CAU AQ_SET set actions for EPWM1A EPwmlRegs AQCTLA bit CAD AQ_CLEAR EPwmlRegs DBCTL bit MODE DB_FULL_ENABLE enable Dead band module EPwmlRegs DBCTL bit POLSEL DB_ACTV_HIC Active Hi complementary EPwmlRegs DBFED 20 FED 20 TBCLKs EPwmlRegs DBRED 20 RED 20 TBCLKs EPWM Module 2 config EPwm2Regs TBPRD 450 Period 900 TBCLK counts EPwm2Regs TBPHS 300 Phase 300 900 360 120 deg EPwm2Regs TBCTL bit CTRMODE TB_COUNT_UPDOWN Symmetrical mode EPwm2Regs TBCTL bit PHSEN TB_ENABLE Slave module EPwm2Regs TBCTL bit PHSDIR TB_DOWN Count DOWN on sync 120 deg EPwm2Regs TBCTL bit PRDLD TB_SHADOW EPwm2Regs TBCTL bit SYNCOSEL TB_SYNC_IN sync flow through EPwm2Regs CMPCTL bit SHDWAMODE
151. tomatically clear the counter INTCNT 0 and the counter output will be reset so no interrupts are generated Writing a 1 to the ETFRC INT bit will increment the event counter INTCNT The counter will behave as described above when INTCNT INTPRD When INTPRD 0 the counter is disabled and hence no events will be detected and the ETFRC INT bit is also ignored The above definition means that you can generate an interrupt on every event on every second event or on every third event An interrupt cannot be generated on every fourth or more events Figure 2 41 Event Trigger Interrupt Generator ETFLG INT ETPS INTCNT Generate 0 ETSEL INTSEL interrupt EPWMxINT pulse when input 1 Clear CNT 2 bit ETFRC INT Counter INT 0 CTR Zero CTR PRD Inc CNT 0 CTRU CMPA CTRD CMPA CTRU CMPB CTRD CMPB ETSEL INT ETPS INTPRD Figure 2 42 shows the operation of the event trigger s start of conversion A SOCA pulse generator The ETPS SOCACNT counter and ETPS SOCAPRD period values behave similarly to the interrupt generator except that the pulses are continuously generated That is the pulse flag ETFLG SOCA is latched when a pulse is generated but it does not stop further pulse generation The enable disable bit ETSEL SOCAEN stops pulse generation but input events can still be counted until the period value is reached as with the interrupt generation logic The event that will trigger
152. trolling a 3 Phase Interleaved DC DC Converter Figure 3 13 Control of a 3 Phase Interleaved DC DC Converter Ext Syncin optional Master Phase re g Syncin Vin A E En p 0 4 a I K EPWM1A EPWM1B HA H HH CTR zero CTR CMPB o EPWM1A EPWM2A EPWM3A xX o SyncOut 3 3 a a a EPWM1B EPWM2B EPWM3B y Phase reg Syncin OUT En p 120 NOD K EPWM2A L EPWM2B L L CTR zero o CTR CMPB X o 2 SyncOut Slave Phase reg Syncin En 240 _O O K EPWM3A CTR zero o epee CTR CMPB xX o SyncOut 86 Applications to Power Topologies SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback R Texas INSTRUMENTS www ti com Controlling a 3 Phase Interleaved DC DC Converter Figure 3 14 3 Phase Interleaved DC DC Converter Waveforms for Figure 3 13 450 EPWM1A RED RED gt RED EPWM1B FED aa FED FED lt 300 2 120 TBPHS 300 EPWM2A EPWM2B R 300 gt 62 120 TBPHS 300 EPWM3A EPWM3B SPRU791D November 2004 Revised October 2007 Applications to Power Topologies 87 Submit Documentation Feedback INSTRUMENTS www ti com Controlling a 3 Phase Interleaved DC DC Converter Example 3 5 Code Snippet for Configura
153. ubmodule Control and Status Registers Figure 4 17 and Table 4 17 provide the trip zone control and status register definitions 106 Registers SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback 4 TEXAS INSTRUMENTS www ti com Trip Zone Submodule Control and Status Registers Figure 4 17 Trip Zone Select Register TZSEL 15 14 13 12 11 10 9 8 Reserved OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1 R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 7 6 5 4 3 2 1 0 Reserved CBC6 CBC5 CBC4 CBC3 CBC2 CBC R 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 LEGEND R W Read Write R Read only n value after reset Table 4 17 Trip Zone Submodule Select Register TZSEL Field Descriptions Bits Name Value Description One Shot OSHT Trip zone enable disable When any of the enabled pins go low a one shot trip event occurs for this ePWM module When the event occurs the action defined in the TZCTL register Table 4 18 is taken on the EPWMxA and EPWMxB outputs The one shot trip condition remains latched until the user clears the condition via the TZCLR register Table 4 21 15 14 Reserved Reserved 13 OSHT6 Trip zone 6 TZ6 Select Enable TZ6 as a one shot trip source for this ePWM module Disable TZ6 as a one shot trip source for this ePWM module OSHT5 Trip zone 5 TZ5 Select Disable TZ5 as a one shot trip source for th
154. uty for output EPWM2A EPwm2Regs CMPB 300 adjust duty for output EPWM2B SPRU791D November 2004 Revised October 2007 Applications to Power Topologies 77 Submit Documentation Feedback 3 TEXAS INSTRUMENTS www ti com Controlling Multiple Half H Bridge HHB Converters 3 5 78 Controlling Multiple Half H Bridge HHB Converters Topologies that require control of multiple switching elements can also be addressed with these same ePWM modules It is possible to control a Half H bridge stage with a single ePWM module This control can be extended to multiple stages Figure 3 7 shows control of two synchronized Half H bridge stages where stage 2 can operate at integer multiple N frequencies of stage 1 Figure 3 8 shows the waveforms generated by the configuration shown in Figure 3 7 Module 2 slave is configured for Sync flow through if required this configuration allows for a third Half H bridge to be controlled by PWM module 3 and also most importantly to remain in synchronization with master module 1 Figure 3 7 Control of Two Half H Bridge Stages Fpwme2 N x Fpwmi Ext Syncin VDC bus meee optional kg 6 o Vouti Master Phase reg tH gt A A Syncin EPWM1A p 0 R oo T K EPWM1A YET L kd CTR zero EPWMIE CTR CMPB XS aN A A SyncOut EPWM1B kad
155. ve TBCTL SWFSYNC TBCTR 15 0 Be JL CTR PRD 4 JL EPWMxSYNCI CTR Zero R Zero Counter eet pir UP DOWN Mode TBCTL CTRMODE CTR max Max Load T clk TR CMPB TECTA TBCTL PHSEN c Counter Active Reg Disable JL EPWMxSYNCO CTR Zero X 16 TBPHS TBCTL SYN EL Phase Active Reg CTL SYNCOSEL SYSCLKOUT TBCTL HSPCLKDIV TBCTL CLKDIV 24 ePWM Submodules SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Time Base TB Submodule Table 2 3 Key Time Base Signals Signal Description EPWMxSYNCI Time base synchronization input Input pulse used to synchronize the time base counter with the counter of ePWM module earlier in the synchronization chain An ePWM peripheral can be configured to use or ignore this signal For the first ePWM module EPWM1 this signal comes from a device pin For subsequent ePWM modules this signal is passed from another ePWM peripheral For example EPWM2SYNCI is generated by the ePWM1 peripheral EPWM8SYNCI is generated by ePWM2 and so forth See Section 2 2 3 2 for information on the synchronization order of a particular device EPWMxSYNCO _ Time base synchronization output This output pulse is used to synchronize the counter of an ePWM module later in the synchronization chain The ePWM module generates this signal from one of three event sources 1 EPWMxSYNCI Synchronization
156. w state 11 Do nothing no action is taken on EPWMXxB 1 0 TZA When a trip event occurs the following action is taken on output EPWMxA Which trip zone pins can cause an event is defined in the TZSEL register Table 4 17 00 High impedance EPWMxA High impedance state 01 Force EPWM XA to a high state 10 Force EPWMXA to a low state 11 Do nothing no action is taken on EPWMXxA Figure 4 19 Trip Zone Enable Interrupt Register TZEINT 15 8 Reserved R 0 7 3 2 1 0 Reserved OST CBC Reserved R 0 R W 0 R W 0 R 0 LEGEND R W Read Write R Read only n value after reset Table 4 19 Trip Zone Enable Interrupt Register TZEINT Field Descriptions Bits Name Value Description 15 3 Reserved Reserved 2 OST Trip zone One Shot Interrupt Enable 0 Disable one shot interrupt generation 108 Registers SPRU791D November 2004 Revised October 2007 Submit Documentation Feedback K TEXAS INSTRUMENTS www ti com Trip Zone Submodule Control and Status Registers Table 4 19 Trip Zone Enable Interrupt Register TZEINT Field Descriptions continued Bits Name Value Description 1 Enable Interrupt generation a one shot trip event will cause a EPWMx_TZINT PIE interrupt CBC Trip zone Cycle by Cycle Interrupt Enable Disable cycle by cycle interrupt generation Enable ee generation a cycle by cycle trip event
157. well as electrical and timing specifications for the F280x devices SPRS357 TMS320F 28044 Digital Signal Processor Data Manual contains the pinout signal descriptions as well as electrical and timing specifications for the F28044 device CPU User s Guides SPRU430 TMS320C28x DSP CPU and Instruction Set Reference Guide describes the central processing unit CPU and the assembly language instructions of the TMS320C28x fixed point digital signal processors DSPs It also describes emulation features available on these DSPs SPRU712 TMS320x280x 2801x 2804x System Control and Interrupts Reference Guide describes the various interrupts and system control features of the 280x digital signal processors DSPs Peripheral Guides SPRU566 TMS320x28xx 28xxx Peripheral Reference Guide describes the peripheral reference guides of the 28x digital signal processors DSPs SPRU716 TMS320x280x 2801x 2804x Analog to Digital Converter ADC Reference Guide describes how to configure and use the on chip ADC module which is a 12 bit pipelined ADC SPRU791 TMS320x28xx 28xxx Enhanced Pulse Width Modulator ePWM Module Reference Guide describes the main areas of the enhanced pulse width modulator that include digital motor control switch mode power supply control UPS uninterruptible power supplies and other forms of power conversion SPRU924 TMS320x28xx 28xxx High Resolution Pulse Width Modulator HRPWM
158. wn in Example 2 1 These definitions are also used in the C280x C C Header Files and Peripheral Examples SPRC191 Example 2 1 Constant Definitions Used in the Code Examples AQCTLA and AQCTLB I ZRO PRD CAU CAD CBU CBD bits 0x0 0x1 0x0 0x1 0x2 0x3 0x0 0x1 0x2 TBCTL Time Base Control TBCTR MODE bits define TB_COUNT_UP define TB_COUNT_DOWN define TB_COUNT_UPDOWN define TB_FREEZE PHSEN bit define TB_DISABLE define TB_ENABLE PRDLD bit define TB_SHADOW define TB_IMMEDIATE SYNCOSEL bits define TB_SYNC_IN define TB_CTR_ZERO define TB_CTR_CMPB define TB_SYNC_DISABLE HSPCLKDIV and CLKDIV bits define TB_DIV1 define TB_DIV2 define TB_DIV4 PHSDIR bit define TB_DOWN define TB_UP CMPCTL Compare Control 77 LOADAMODE and LOADBMODE bits define CC_CTR_ZERO define CC_CTR_PRD define CC_CTR_ZERO_PRD define CC_LD_DISABLE SHDWAMODE and SHDWBMODE bits define CC_SHADOW define CC_IMMEDIATE 0x0 0x1 0x2 0x3 0x0 0x1 Action qualifier Control define AQ_NO_ACTION 0x0 define AQ_CLEAR 0x1 define AQ_SET 0x2 define AQ_TOGGLE 0x3 DBCTL Dead Band Control ee MODE bits define DB_DISABLE 0x0 define DBA_ENABLE 0x1 define DBB_ENABLE 0x2 define DB_FULL_ENABLE 0x3 POLSEL bits define DB_ACTV_HI 0x0 define DB_ACTV_LOC 0x1 define DB_ACTV_HTC 0x2 SPRU791D November 2004 Revised October 2007
159. wo compare registers 1 CTR CMPA Time base counter equal to counter compare A register TBCTR CMPA 2 CTR CMPB Time base counter equal to counter compare B register TBCTR CMPB For up count or down count mode each event occurs only once per cycle For up down count mode each event occurs twice per cycle if the compare value is between 0x0000 TBPRD and once per cycle if the compare value is equal to 0x0000 or equal to TBPRD These events are fed into the action qualifier submodule where they are qualified by the counter direction and converted into actions if enabled Refer to Section 2 4 1 for more details The counter compare registers CMPA and CMPB each have an associated shadow register Shadowing provides a way to keep updates to the registers synchronized with the hardware When shadowing is used updates to the active registers only occurs at strategic points This prevents corruption or spurious operation due to the register being asynchronously modified by software The memory address of the active register and the shadow register is identical Which register is written to or read from is determined by the CMPCTL SHDWAMODE and CMPCTL ISHDWBMODE bits These bits enable and disable the CMPA shadow register and CMPB shadow register respectively The behavior of the two load modes is described below e Shadow Mode The shadow mode for the CMPA is enabled by clearing the CMPCTL SHDWAMODE bit and the shadow register for CMPB is
160. ystem This modular approach results in an orthogonal architecture and provides a more transparent view of the peripheral structure helping users to understand its operation quickly In this document the letter x within a signal or module name is used to indicate a generic ePWM instance on a device For example output signals EPWMxA and EPWM lt xB refer to the output signals from the ePWMx instance Thus EPWM1A and EPWM1B belong to ePWM1 and likewise EPWM4A and EPWM4B belong to ePWM4 Submodule Overview The ePWM module represents one complete PWM channel composed of two PWM outputs EPWMxA and EPWMxB Multiple ePWM modules are instanced within a device as shown in Figure 1 1 Each ePWM instance is identical with one exception Some instances include a hardware extension that allows more precise control of the PWM outputs This extension is the high resolution pulse width modulator HRPWM and is described in the TMS320x28xx 28xxx High Resolution Pulse Width Modulator HRPWM Reference Guide SPRU924 See the device specific data manual to determine which ePWM instances include this feature Each ePWM module is indicated by a numerical value starting with 1 For example ePWM1 is the first instance and ePWMs3 is the 3rd instance in the system and ePWMx indicates any instance The ePWM modules are chained together via a clock synchronization scheme that allows them to operate as a single system when required Additionally this synchronization schem
161. zation input If the TBCTL PHSEN bit is set then the time base counter TBCTR of the ePWM module will be automatically loaded with the phase register TBPHS contents when one of the following conditions occur e EPWMxSYNCI Synchronization Input Pulse The value of the phase register is loaded into the counter register when an input synchronization pulse is detected TBPHS TBCNT This operation occurs on the next valid time base clock TBCLk edge e Software Forced Synchronization Pulse Writing a 1 to the TBCTL SWFSYNC control bit invokes a software forced synchronization This pulse is ORed with the synchronization input signal and therefore has the same effect as a pulse on EPWMxSYNCI This feature enables the ePWM module to be automatically synchronized to the time base of another ePWM module Lead or lag phase control can be added to the waveforms generated by different ePWM modules to synchronize them In up down count mode the TBCTL PSHDIR bit configures the direction of the time base counter immediately after a synchronization event The new direction is independent of the direction prior to the synchronization event The TBPHS bit is ignored in count up or count down modes See Figure 2 7 through Figure 2 10 for examples Clearing the TBCTL PHSEN bit configures the ePWM to ignore the synchronization input pulse The synchronization pulse can still be allowed to flow through to the EPWMxSYNCO and be used to synchronize other

Texas Instruments 28xxx User's Manual

Contents

Download Pdf Manuals

Related Search

Related Contents