Sundance Catalog Sundance TV Cables SMT 348 User's Manual
Contents
1. User Manual SMT348 Page 16 of 29 Last Edited 29 02 2008 17 52 00 The SMT348 module contains a SOMHz LVTTL clock a 200MHz clock and a connector for an external LVTTL clock input output 50 MHz LVTTL oscillator Main system clock Clocks the CPLD and the FPGA Can be input ina DCM 200MHz LVTTL oscillator ODRII clock Can also be used as a main FPGA clock Can be input in a DCM An external clock input is provided to the Virtex 4 FPGA via an MMCX connector This connector is NOT fitted by default or if a mezzanine is required YOU MUST ask Sundance if needed for your application 4 Red LEDs connect to the FPGA and are available to the User D4 D5 D6 D7 1 Green Led DI connects to the DONE pin of the FPGA and 1s lit to show that the FPGA is configured depending on supply from manufacturer a red led can be fitted instead 4 2 15 Performance The FPGA features like speed grade and density dictate most performances The performances achievable by the other components are given in the chapters above and the components respective data sheets 4 3 Interface Description For the TIM to carrier board or external world interfacing see in Sundance Help file that you can download from the Sundance Wizzard 4 3 1 Power Budget The SMT348 draws its power from the 3 3v rail of the PCI The PCI specification stipulates that the maximum power for one card is 25W Therefore the maximum current that the SMT348 could draw fro2. Comport3 1s a communication resource shared by the CPLD and the FPGA But only 1 entity 1s allowed to use 1t at a time If you implement comport 3 in the FPGA you have to use Fpgaresetn generated by the CPLD as the comport is shared between the two The Reset control 1s operated by the CPLD line FPGAResetn The following diagram shows the CPLD states after Reset TIM Reset or TIM Config Hogaresetn asserted FPGA Configured and STARTKEY Received ENDKEY Received FPGA Configured Fpderesetn de agserted and ENDKEY Received Figure 2 CPLD state machine If you generated you FPGA bitstream using Diamond FPGA you do not need any other handling The app file created can be used as is to configure the FPGA If you used Xilinx ISE and created a bit file you need to use the Sundance executable Getrawdata exe provided for free in the SMT6001 package Please read the SMT6001 help file at chapter Saving FPGA configuration data to file The resulting file can be used as is to configure the FPGA Up to 4 Mbytes of QDR2 SRAM per bank The memory 1s available as 4 independent banks The QDR2 memory runs at 250MHz Each bank 1s fully independent with separate address control and data busses and arranged as follows Vrerm VReEr 2 R 50 Ohms XC4V QQ 15 0 QD 15 0 NC QSA 19 0 QWn QRn QK QKn output CQ input Vrerm gt VREF 2 Figure 3 FPGA connections to
3. Unit Module Number SMT348 Document Issue Number User Manual Revision History 1 0 1 Minor inconsistency about comports removed from 26 02 07 E P block Diagram Clarification about the elements in the JTAG chain 15 11 07 1 0 3 Updated JTAG header information Wrong marking 29 02 08 E P of position Added chapters about bitstream formatting FPGA configuration Table of Contents 1 2 4 L07019 10 690 FREE RR RR RAR pon S tonikom no on 6 Related Document Siero reason nti 1 21L kRelerenced OCG Mi CI 86a osoafnnn odo no O Aio to door no nn hon T 2 2 Applicable Documents ss sss sss ss esse s eee 7 Acronyms Abbreviations and Definitions sss sss sees essen 8 3 1 Acronyms and Abbreviations eee 8 IRR RI 8 Functional DESErIpLioDi sissczisrenrazzz a gircicnzianta nannini siae 9 bl PORD 1 0 arc cc 9 AD Mod le DESC PION diciciscesdsticadnacsduscuedsswsvnvnsihuadisuaetiansaintiakonsadseasaavaredwasaviuiegeedsdoeied 10 I A OE 10 SO lara 10 123 FLASH MEMORY lalla 10 AE S JE Gy lt T E ia adoncisonudsdeap ide sanauneuntnsncers 10 4 2 5 FPGA Configuration schenmes sss sees e 11 210 EPG Reset SC CMG siriana oo oo obno 12 4 2 1 FPGA Bitstreamionnattind acne 13 45 0A ainsi 14 42 9 Sundance High speed BUS siii rain 15 4 2 105undanee Low voltage Bussola 15 AZ Ml WINER ONCOL Ole PROPRI E RT 16 AD Ne LP SV ILC TTT 16 A Dade VOC TI SCTE TTT 17 A WA CED T 17 Ae Delia S S KO ING TT 17 ko Tnterlaco
4. 3 3 Depends on Virtex 4 power LVTTL Vcco 3 3v implemented estimator design Table 10 Power budget on 3 3v User Manual SMT348 Pace 20 of 29 Last Edited 29 02 2008 17 52 00 Details Coolrunner XC2C256 6 CP132 power requirements based on design Macrocells Function Block Used Pterms Used Registers Used Pins Used lapas Used 218 256 86 531 896 60 190 256 75 69 106 66 445 640 70 Table 11 Coolrunner II resources summary Signal Type Required Mapped a Type Zeed Input 3 8 Output 40 40 GCKIIO i Bidirectional 20 20 GTS IO 0 GCK 1 1 GSR IO 1 GTS 0 0 CDR IO 0 GSR 0 0 DGE IO 0 Table 12 Coolrunner II pin resources o Footprint 5 1 Top View FHOSNIS dWal sng 178019 L e M L oe ete o RAEE one L NV4 SHS Pht tS tS COLA AC A a A AL A AJ SE e RARE A A A U A m s L L EEEE RKR R 98 da Ha m 8 0 6 L L a a n 1 a E n FRPP REP ee m L CHCI AC A A A AOC A DA S A A EE o ee r F R m F R m F E m R R m R R R m F m EF P F R r F F R m F R ALDA LL PPPS a LL ERESIA RE PSPS TRT RTE PSPS FEFEFE FSP eS EEFE SPEER a A A A A A A i RARA R ET EE BEE FTF FEE FEE TEE EE FEE H tht hihi LE AO LA A UA A A OL AAA EEE AJ a nd ama ul il cio olo R RKR BR
5. o o o o 4 0 8 0 o 0 amp 0 4 0 0 d Figure 5 Bottom view User Manual SMT348 Last Edited 29 02 2008 17 52 00 6 Pinout 6 1 FPGA Pin allocation by bank Clocks amp DLL control Bank C Data Control Bank B Data Control Bank D Data amp Control Bank A Data amp Control 1xSHB 2XCP 1xSHB 2XCP Vr Vrp Vrn Vref Table 13 Pin allocation by Bank 6 2 SHD SUNDANCE SHB specification 6 3 SLB SUNDANCE SLB specification SLB LVTTL 16 Diff Data amp 4 Diff Clocks 16 Diff Data amp 4 Diff Clocks 13 Control 32 Data amp 31 Address amp 1 Control 8xConfig Clocks amp Reset amp Switches PXI TTL INTs LEDs Misc 13 64 64 64 64 64 64 64 64 46 46 6 4 JTAG i ai kd Au 6 6 6 A 6 e hd AA JA e 6 SE SE SE SE SE SE SE M SE SE SE SE A A A v ka s eae tee ee R RR Re V Pe OE dan Sis Tie c TL lt SS S s sil TT TTT TT TTT T de ZIA U4 k m kd x L A ilo ol wee 1 i gt I PALI TEN TEELE i Lo d LU l ni nb m Wir d d x at Ch x sas d LPR a alli Figure 6 JTAG Connector top view 1 Qualification Requirements 1 1 Qualification Tests 7 1 1 Meet Sundance standard specifications e Meet the TIM standard specifications e Meet
6. on QDRII 0 9v Termination voltage 19 Table 9 Power budget on QDRII and FPGA 0 9v reference voltage 20 Table 10 Power budget on IV sini 20 Table 11 Coolrunner II resources SUMMALy i 21 Table 12 Coolrunner II pin resources ere 21 Table 19 Pinalhocation Dy Banik ilo 24 1 Introduction The SMT 348 is an FPGA TIM module designed to be integrated in modular systems It 1s designed to connect to the huge range of other TIM modules and carriers developed by Sundance Sundance modular solutions provide flexible and upgradeable systems The SMT348 is a TIM module aimed at completing the range of Sundance Virtex4 modules like SMT368 SMT362 SMT339 It provides a communications platform between an XC4VSX55 or XC4VLX160 FPGA and e 4banks of QDR2 SRAM at a frequency of up to 250Mhz e 2 32 bit SHBs e TIM Global Bus e LVDS connections for high speed parallel connections e VTIL connections and connectors This variety of connectors and interfaces provides a wide range of development options for designers to explore the capabilities of the comprehensive Sundance TIM modules family 2 Related Documents 2 1 Referenced Documents SUNDANCE SDB specification SUNDANCE SHB specification SUNDANCE SLB specification Samsung ODRII Datasheet Spansion S29GLXXXN flash 2 2 Applicable Documents TI TIM specification amp user s guide Samtec OSH Cata
7. 4VSX55 LX160 and configuration scheme Block2 QDR2 SRAM memory e Block3 IO connectors for general purpose or dedicated interfaces Block4 50MHz or 200MHz local clocks and external clock input Block5 LEDs for development and in use monitoring and general purpose use Xilinx Virtex 4 XC4VSX55FF1148 or XC4VLX160FF1148 FPGA This device 1s packaged in a 1148 pin BGA package Xilinx Coolrunner II device XC2C256 6CP132C This device is packaged in a 132 ball BGA type package with a 6 speed grade It can be used to configure the FGPA via Comport 3 or from a configuration stored in flash memory The flash memory is programmed using the CPLD and data via the ComPort3 4 2 3 FLASH MEMORY S29GL256N11TFIO1 is a 256Mbit flash from Spansion It can be used to configure the FPGA at power up Flash accessed using Comport3 via the CPLD Flash programming selection via switch SW1 See Table 3 Software Library Support available from Sundance The code can run on Sundance DSP TIM or a Host All the flash functionalities are available The JTAG header is compatible with Xilinx Parallel I V cable signals It supports code download for the FPGA FPGA configuration Hardware and Software Debugging tools for the Virtex 4 This cable connects the parallel port of an engineer s Workstation PC to the JTAG chain of the SMT348 Module All the Xilinx devices from blockl are chained and accessible via this JTAG header 4 2 5 FP
8. Bank of QDRII The devices used are Samsung K7R321884M Alternative part numbers fully compatible can be fitted depending on availability at time of order 4 2 9 Sundance High speed Bus 2 x 60 pin connectors provide 80 IO connections between the FPGA and the outside word They allow interfacing to other Sundance modules providing that you implement an SHB interface in the FPGA See 2 1 The SHB interface 1s available in Sundance SMT6500 support package Either two 16 bit or 1 32 bit interface can be implemented per connector They allow interfacing to the outside world by implementing your own interface in the FPGA The FPGA IO banks hosting the SHB signals are powered using Veco 3 3V 4 2 10 Sundance Low voltage Bus This bus is present on the LX160 version of the module only This is an LVDS bus comprising data 2 x 16 bit buses I amp Q clock and control signals They allow interfacing to Sundance mezzanine modules providing that you implement an SLB interface in the FPGA See 2 1 They allow interfacing to the outside world by implementing your own LVDS interface in the FPGA All LVDS data pins both I and Q are connected to a 2 5 3 3V powered FPGA banks link selectable by jumper JP3 The FPGA LVDS DIFF_TERM standard should be used instead of the DCI terminations when LVDS standard 19 selected DCI terminations are only available when a 2 5v standard is selected The LVDS Clock signals are also in these b
9. GA Configuration schemes Different schemes are available to provide maximum flexibility in systems where the SMT348 is involved The FPGA configuration bitstream source is e On Comport 3 The CPLD is connected to the Comport 3 link of the SMT348 TIM connector See block1 A switch is used to select Comport 3 as the link that will be used to receive the bitstream The CPLD allows for FPGA configuration in slave SelectMAP mode e Using the on board Flash memory The CPLD monitors the configuration data between the Flash and the FPGA The FPGA configuration is operated in Slave SelectMap mode A switch is used to select the Flash as the source for the configuration bitstream e Using the on board JTAG header and Xilinx JTAG programming tools The JTAG header 1s a Parallel IV Header Note Using JTAG to configure the FPGA bypasses the CPLD which controls configuration The following section describes the CPLD role and the reset scheme used As the CPLD 1s bypassed when JTAG 1s used to configure the FPGA 1t 1s necessary to adopt one of the three following ways e If your FPGA design does not implement comport3 o donot use the Reset signal generated by the CPLD but use the TIM reset signal as your design s reset You can use JTAG to configure your FPGA with your application and the design will reset and run everytime you issue a new TIM reset e If your design implements comport3 o Set the switch to configure the FPGA from flash after res
10. T a a dh i d d A A A A A A A A A A A CHA A IA A EE ES SF A Li F F nd KR R T a nad BRT B nic ic a RR TRR E EEEE lll AA AA A A A A AL A A A ETF EE TEBE iR FE GTF EE EE CH COP ee TC NC TN CEL CCL Ce AL EA AO A A A LA A A A UA U O A A UA A A A AL A O TLL M PoP eee Se o na ee 8 90 K 80 6 A RE 686680 RRR RRR EL 6 84 6 Pee 1111111111111 Pc ce TEET vimini CELA RT RRR TRB R nb RRC R Co ia oi i RRB EA I I HOLIMS dHS WOd4 fe i A A A A A R i eat CE E A A A A A A RI LE A A et A A CE OA A thee dl FREE abbi COLI A OL A A CA A PREPRESS A abit NOUILYNIN AL C 9400 si a HES HEG CLA A OL AE AC A A A A CO A A OL A A A ee fl ala RR LA AAA AAA AA A A A A A A A A A A CO OA A A A A A A AJ PEER PERE U MA A AL A A A A LI n tthe 11 15 ALA ALA AA LL AJ o oa be EHEHEH RCA A AO A A A AAA BB O O EEE EEEE A EEEE ELA A dd AA LA Lh bitte OOCR xa L cado HYIMOd 415 VIVO 4 15 To 9 0 0 0 0 0 E 9 0 0 9 a o o ot i 4 n a ata a e a a e a a a SalddNns HYHIMOd MIO 1x3 1142 914NO2 Figure 4 Top View 5 2 Bottom View SOOO 0 6 6 0 LOCAL OSCILLATORS FLASH MEMORY 4 amp 6 6 amp
11. anks All LVTTL signals are connected to a 3 3V powered FPGA bank 4 2 11 TIM Connectors TIM connectors provide 4 communication links Comports and a Global Bus to the FPGA The comports which are available on the SMT 348 are CPO CP1 CP3 and CP4 They allow interfacing to Sundance TIM modules or to a Host PC providing that you implement a Comport Interface inside the FPGA See 2 1 The Comport interface is available in Sundance SMT6500 support package The FPGA 10 banks hosting the Comport signals are powered using Veco 3 3v The TIM connectors also provide power ground reset and various control signals References and specifications for these connectors are available in TI TIM specification amp user s guide 4 2 12 DIP Switches One four position DIP switch 19 connected to the CPLD to provide control over the selection of the configuration bitstream source and a special reset feature called TIM Confign SW1 pos 4 TIM Config Table 1 DIP switch SWI position for special reset feature Table 2 DIP switch SWI position for the selection of the configuration bitstream source SW1 pos 3 2 1 JPC8 Table 3 DIP switch SWI position for the selection of the Flash erase amp program operations The Flash erase amp program operations are operated by the CPLD Commands are provided via Comport3 from an application running on a Host or DSP Status information from the Flash 1s given over Comport3 as well
12. e Description seereis EE EEEE 17 do Foner Dido TT 17 sene n E ini 22 o A caste EEEE EAEE EA EAEE E 22 i BOE V ON ee o AR AI Iii 23 PUTO UG PR E 24 6 1 FPGA Pin allocation by bank sees 24 DI PBE eA e E E EE E A A E E EEEE E A E pe 24 bo Cei were eter tee TT oT erm 24 04 Ilie ee Cnn ene na 25 7 Qualification Requirements sss esec ee eee eee 25 Tol BTT ST TY GT e X TT 25 1 1 1 Meet Sundance standard specifications erre 25 ili Spese Uda iCal 0 iii iodio 26 1 1 3 Integration qualification tests e eee 26 8 ZET s Pack rina RO A re 26 PRYSICALEFGDEE LES ci TO r ono 27 IO Siberia 28 I E 29 Table of Figures Figure 1 Block Diagram rinato ariano 9 Figure 2 CPLD state TOE 13 Figure 3 FPGA connections to Bank1 of QDRIL sss 14 Fig re Re 22 Figure 5 Bottom VIEW esse eee eee 23 Figure 6 JTAG Connector top View eee 25 Table of Tables Table 1 DIP switch SW1 position for special reset feature 16 Table 2 DIP switch SW1 position for the selection of the configuration bitstream source E E E E E 16 Table 3 DIP switch SW1 position for the selection of the Flash erase amp program OD TAO eE EEA AA E EA E EA EA E E 16 Table 4 Total available power eee 18 Table 5 Power budget on 1 2V Le 18 Table 6 Power budget on 2 5V o none nn no r nr nr rn 18 Table 7 Power budget on 1 8V e 19 Table 8 Power budget
13. et In this way a default bitstream being stored in flash will be loaded in the FPGA by the CPLD Jn this manner the CPLD has gone trhough the cycle of configuring the FPGA and releases the reset FPGAresetn Then you can reconfigure the FPGA via JTAG with your application o Set the switch to configure from comport 3 After reset configure the FPGA via JTAG and provide an end key word on comport 3 to the CPLD so that it releases the Reset FPGAresetn 4 2 6 FPGA Reset Scheme The CPLD is connected to a TIM global Reset signal provided to the SMT348 via its primary TIM connector pin 30 See TI TIM specification amp User s guide This signal goes to the CPLD and the FPGA Nevertheless as a general rule for good practice the FPGA should not use this reset but should use the reset signal generated by the CPLD The CPLD provides another signal called FPGAResetn that offers a better Reset control over the FPGA At power up or on reception of a low TIM global Reset pulse the CPLD drives the FPGAResetn signal low and keeps it low This 1s used to keep the FPGA design in reset A new FPGA configuration bitstream can then be downloaded When the ENDKEY has been received the CPLD drives FPGAResetn high Use FPGAResetn for the Global Reset signal of your FPGA designs In this manner you can control your FPGA design Reset activity and you will also avoid possible conflicts on ComPort 3 if your FPGA design implements 1t
14. logue page Virtex 4 Datasheet 3 Acronyms Abbreviations and Definitions 3 1 Acronyms and Abbreviations TIM TI DSP Xilinx FPGA QDR CP SDB SHB Texas Instruments Module Texas Instrument Digital Signal Processor Xilinx Field Programmable Gate Array Quad Data Rate ComPort Communication interface Sundance Digital Bus Communication interface Sundance High Speed Bus Communication interface 3 2 Definitions DSP Module Typically a TIM module hosting a TI DSP and a Xilinx FPGA FPGA only Module A TIM with no on board DSP where the FPGA provides all Firmware functionality A proprietary FPGA design providing some sort of functionality Sundance Firmware is the firmware running in an FPGA of a DSP module 4 Functional Description This module conforms to the TIM standard Texas Instrument Module See TI TIM specification amp user s guide for single width modules It sits on a carrier board The carrier board provides power 5V 3 3V 12V ground communication links Comport links between all the modules fitted and a pathway to the host for a non stand alone system The SMT348 requires a 3 3V power supply as present on all Sundance TIM carrier boards which must be provided by the two diagonally opposite mounting holes 4 1 Block Diagram Flash memory 11 O pins A h de Figure 1 Block Diagram 4 2 Module Description e Blockl and Xilinx Virtex 4 XC
15. m 3 3V is 7 6A assuming zero current on all the other supply voltages But this limit is system dependent so a given system might not have the full 7 6A available for a slot even if 1t 1s the only PCI card in the system A system might balance the power capabilities differently between the 5V and 3 3V and 12V supplies rather than making 25W available from 5V and 25W available from 3 3V User Manual SMT348 Page 17 of 29 Last Edited 29 02 2008 17 52 00 As a result check your main power supply ratings If your system 1s likely to reach 25W per power rail we advice that you provide extra power to the carrier board using an external power supply ad ian si Table 4 Total available power t mA XC4VLX160FF1148 11 a 1 805 2 166 Virtex 4 MESI design implementation of 4 si r independent qdrii controllers Fpga Vccint power plane M 14000 TI TPS50410 capacity Table 5 Power budget on 1 2v Mec ie li XC4VLX160FF1148 11 V25 Virtex 4 power Veco 2 5v LVDS TX estimator pairs on SLB bus XC4VLX160FF1148 11 V25 21 Virtex 4 ds302 v1 17 Veco 2 5v LVCMOS p 7 TX on SLB bus Fpga 2 5v power plane l LT1963 1 5A Linear capacity Regulator 3 3v to 2 5v 1 5A Excess power Table 6 Power budget on 2 5v User Manual SMT348 Page 18 of 29 Last Edited 29 02 2008 17 52 00 Device Name Guantity Voltage a Power W Source V Samsung GDR II burst V18 1 8 Samsung QDRII 4 18 bit inte
16. rface 25 datasheet rev1 1 p 9 ML6554CU DC DC 1 8 0 0 0 018 Fairchild converter ML6554CU obsolete Coolrunner 0 00099 Ise 8 2 031 Xpower XC2C256CP132 software version 1 34 XC4VLX160FF1148 11 1 497 Virtex 4 power HSTL II estimator an implementation of 4 independent qdrii HSTL power plane 6000 TI TPS54611PWP 1 8v capacity Excess power Table 7 Power budget on 1 8v QDRII Vtt Samsung QDRII 25 datasheet termination resistor rev1 1 p 9 50 ohms See details HSTL Vtt termination Power Plane 0 9v capacity Excess power Table 8 Power budget on QDRII 0 9v Termination voltage Device 000 Device Name Quantity Voltage V Current mA Power W QDRII Vref a Samsung QDRII 25 datasheet revl 1 p 9 XC4VLX160FF1148 11 HSTL VRO9 0 0 0 000144 DS302 v1 17 Vref table 3 p 3 HSTL Vref plane 0 9v VRO9 1 3 0 0027 Fairchild capacity ML6554CU obsolete Excess power 0 002556 Re Table 9 Power budget on QDRII and FPGA 0 9v reference voltage 25 Mhz Clock oscillator Eccc 05 Jauch VX3 Quartz crystal oscillators datasheet 200 Mhz Clock 0 066 Jauch VX3 Quartz oscillator crystal oscillators datasheet Linear Regulator 3 3v 1 136 Lala 1 5A to 2 5v 1 5A DC DC converter 3 3v ee ML6554CU to 0 9v obsolete DC DC converter 3 3v V33 14000 N A TI TPS50410 to 1 2v 057 1 8v DIP DIPSwitch oz 0 009 002 Four 4 7 Kohm Four 4 7 Kohm pullup XC4VLX160FF1148 11 V33
17. the SLB specifications LVDS standard e Meet the SHB specifications 7 1 2 Speed qualification tests e QDR2 memory accesses at 250MHz 7 1 3 Integration qualification tests e Must work on ALL Sundance platforms as a root TIM module or as part of a network of TIMs on carriers e Must be able to work stand alone 8 Support Packages 9 Physical Properties mena __ Wi T_T Suppl vole Supply ouret wav SE 5V 10 Safety This module presents no hazard to the user when 1n normal use 11 EMC This module 1s designed to operate from within an enclosed host system which 1s build to provide EMC shielding Operation within the EU EMC guidelines is not guaranteed unless it 1s installed within an adequate host system This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the output cables Short circuiting any output to ground does not cause the host PC system to lock up or reboot
Download Pdf Manuals
Related Search