Summit S93WD462 User's Manual
Contents
1. Write Capability BLOCK DIAGRAM Vcc l I i I i 8 l l I RESET sits _ Pose BE ai QSCILLATOR GENERATOR le I Viu i 2 I 1 l 7 RESET m i hd I CONTROL Le 4 RESET t l l 1 26V 1 es HH gt 1 I l y I sk mope WRITE DECODE CONTROL DI E gt I l I l I I H 2 L y E PROM l i DATA I O MEMORY DO ora ARRAY 1 I AR AAA Dalle Oost oU MEL eee GND 2029 T BD 2 0 SUMMIT MICROELECTRONICS Inc 2001 300 Orchard City Drive Suite 131 Campbell CA 95008 Telephone 408 378 6461 Fax 408 378 6586 www summitmicro com Characteristics subject to change without notice 2029 2 2 1 23 01 S93WD462 S93WD463 PIN CONFIGURATION 8 Pin PDIP or 8 Pin SOIC CS 1 8 Vcc SK 2 7 RESET DI C 3 6 RESET DO 4 5 L1 GND 2029 T PCon 2 0 PIN FUNCTIONS Pin Name Function CS Chip Select SK Clock Input DI Serial Data Input DO Serial Data Output Vcc 2 7 to 6 0V Power Supply GND Ground RESET RESET RESET I O DEVICE OPERATION APPLICATIONS The S93WD462 WD463 is ideal for applications requir ing low voltage and low power consumption This device provides microcontroller RESET control and can be manually resettable RESET CONTROLLER DESCRIPTION The S93WD462 WD463 provides a precision reset con troller that ensures correct system2. immediately followed by the first byte of data to be written The host can then continue clocking in 8 bit bytes of data with each byte to be written to the next higher address Internally the address pointer is incremented after receiving each group of eight clocks however once the address counter reaches xxx 1111 it will roll over to xxx 0000 with the next clock After the last bit is clocked in no internal write operation will occur until CS is brought low 93WD463 Assume WEN has been issued The host will then take CS high and begin clocking in the start bit write command and 6 bit address immediately followed by the first 16 bit word of data to be written The host can then continue clocking in 16 bit words of data with each word to be written to the next higher 2029 2 2 1 23 01 S93WD462 S93WD463 Erase All Upon receiving an ERAL command the CS Chip Se lect pin must be deselected for a minimum of 250ns tcsmin The falling edge of CS will start the self clocking clear cycle of all memory locations in the device The clocking of the SK pin is not necessary after the device has entered the self clocking mode The ready busy status of the S93WD462 WD463 can be determined by selecting the device and polling the DO pin Once cleared the contents of all memory bits will be in a logical 1 state Write All Upon receiving a WRAL command and data the CS Chip Select pin must be deselected for a minimum of 250ns tcsmi
3. memory array is inaccessible After starting the write operation taking CS low the host can implement a 10ms timeout routine or alternatively it can employ a polling routine that tests the state of the DO pin After starting the write testing for the status is easily accomplished by taking CS high and testing the state of DO If it is low the device is still busy with the internal write If it is high the write operation has completed For the polling routine the host has the option of toggling CS for each test of DO or it can place CS high and then intermittently test DO SK is not required for any of these operations Once the device is ready it will continue to drive DO high whenever the S93WD462 WD463 is selected The ready state of DO can be cleared by clocking in a start bit this start bit can either be the beginning of anew command sequence or it can be a dummy start bit with CS returning low before the host issues a new command XXX UU UU UU UU UU UU SK CS gt STATUS VERIFY tcs DI tsv DO t STATUS CLEARED ra EW 2029 ILL 13 0 12 2029 2 2 1 23 01 SUMMIT MICROELECTRONICS Inc S93WD462 S93WD463 ORDERING INFORMATION S93WD462 P A T Base Part Number ll Tape amp Reel Option S93WD462 8 bit configuration Blank Tube S93WD463 16 bit configuration T Tape amp Reel Package Operating Voltage Range P 8 lead PDIP A 4 5V to 5 5V VTRIPp min B 4 25V S 8 lead 150mil S
4. 9 PGM T1 0 tGLITCH VTRIP LY eA VRVALID i Voc PURST tPURST RESET tRPD RESET 1 2029 T figo8 2 0 Figure 8 RESET Timing Diagram SUMMIT MICROELECTRONICS Inc 2029 2 2 1 23 01 9 8 Pin SOIC Ref JEDEC MS 012 0 150 0 157 3 80 4 00 Inches Millimeters 0 189 0 196 4 80 5 00 0 053 0 069 1 i 1 75 0 010 0 020 x45 opo ci EI 0 25 0 50 DT F 0 004 0 010 0 016 0 050 SER 0013 0020 L 0 10 0 25 0 40 1 27 0 228 0 244 0 33 0 51 205 1 27 1YP 5 80 6 20 re 8 Pin PDIP 0 355 0 400 i 9 02 10 2 Ref JEDEC MS 001 PIN 1 INDICATOR 0 24 0 28 6 1 7 1 Inches Millimeters ot 0 045 0 070 T a 1 14 1 78 0 300 0 325 7 62 8 25 0 21 0 115 0 195 5 33 2 92 4 95 Rus 5 381 SEATING PLANE Y 4 0 008 0 014 A am t B 0 43 wg at 020 098 0 20 0 38 0 014 0 022 E l 2 54 10 9 0 36 0 56 0 115 0 195 2 92 4 95 8 Pin PDIP 2029 2 2 1 23 01 SUMMIT MICROELECTRONICS Inc Ka S93WD462 593WD463 atio Sg IK Q y A Q Frequently the reset controller will be deployed on a PC board that provides a peripheral function to a system Examples might be modem or network cards in a PC or a PCMCIA card in a laptop In instances like this the peripheral card may have a requirement for a clean reset function to insure proper operation The system may or may not provide a reset pulse of sufficient d
5. Ao DN Do c_x tsy BUSY gt thz HIGH Z DO READY HIGH Z I tew 2029 ILL 5 0 Figure 3 Write Instruction Timing se F ET T KKK s STATUS VERIFY STANDBY tcs DI tsv tHz HIGH Z D nn BUSY READY HIGH Z I EW 1 aa 2029 ILL6 0 Figure 4 Erase Instruction Timing Ee cs fo o Di Aa K OOOO ENABLE 11 DISABLE 00 2029 Fig05 Figure 5 EWEN EWDS Instruction Timing SUMMIT MICROELECTRONICS Inc 2029 2 2 1 23 01 5 S93WD462 S93WD463 CS DI DO HIGH Z 4 SR i E XXX UU UU UU UU IX tew Figure 6 ERAL Instruction Timing STATUS VERIFY STANDBY 2029 ILL 8 0 CS DI 09 0 1 NANAON DO x MUUA LU EO QR STATUS VERIFY STANDBY tcs tsy e t ew Figure 7 WRAL Instruction Timing 2029 ILL 10 0 INSTRUCTION SET Instruction Start Opcode Address Data Comments Bit x8 x16 x8 x16 READ 1 10 A6 A0 A5 A0 Read Address AN AO ERASE 1 11 A6 A0 A5 A0 Clear Address AN AO WRITE 1 01 A6 A0 A5 A0 D7 DO D15 DO Write Address AN AO EWEN 1 00 11xxxxx 11xxxx Write Enable EWDS 1 00 O0Xxxxx OOxxxx Write Disable ERAL 1 00 10xxxxx 10xxxx Clear All Addresses WRAL 1 00 01xxxxx 01xxxx D7 DO D15 DO Write All Addresses 2029 2 2 1 23 01 2029 PGM T5 0 SUMMIT MICROELECTRONICS Inc FI S93WD462 593WD463 A
6. BSOLUTE MAXIMUM RATINGS Temperature Under B sa ned abide eee RR Eee EE cai Ets 55 C to 125 C Storage Temperature 2 ong eee a tede tet aie rope DR ubica Lu a oder tty 65 C to 150 C Voltage on any Pin with Respect to Ground esssssssssssseseeseeee nennen 2 0V to Vcc 2 0V Veo with Respect to Gro rid 4 03225 ncs eR editt dee Eur 2 0V to 7 0V Package Power Dissipation Capability Ta 25 C sssssssssssseeseseeeeeeenene nennen neret nennen nennen rennen nenne 1 0W Lead Soldering Temperature 10 secs L MA entente nne tr entes n mkuwa retinerent eene 300 C Output Short Circuit Current els s aee er pta edi leds dated ete tee os 100 mA COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied Exposure to any absolute maximum rating for extended periods may affect device performance and reliability RECOMMENDED OPERATING CONDITIONS Temperature Min Max Commercial 0 C 70 C Industrial 40 C 85 C 2029 PGM T7 0 RELIABILITY CHARACTERISTICS Symbol Parameter Min Max Units Nenp 3 Endurance 100 000 Cvcles Bvte Tpn9 Data Retention 100 Ye
7. IN e OKT ALI XXX Figure 1 Sychronous Data Timing EIE x FLELELE LLLP LL EET tcs cs STANDBY AN AN 1 AQ i ND oE GMO luz ATI 56 HIGH Z Lu RUN pape HIGH Z DN DNn 1 Di Do 2029 ILL4 0 Figure 2 Read Instruction Timing SUMMIT MICROELECTRONICS Inc 2029 2 2 1 23 01 3 Erase Upon receiving an ERASE command and address the CS Chip Select pin must be deselected for a minimum of 250ns tcsmin The falling edge of CS will start the auto erase cycle of the selected memory location The ready busy status of the S93WD462 WD463 can be determined by selecting the device and polling the DO pin Once cleared the content of a cleared location returns to a logical 1 state Erase Write Enable and Disable The S93WD462 WD463 powers up in the write disable state Any writing after power up or after an EWDS write disable instruction must first be preceded by the EWEN write enable instruction Once the write in struction is enabled it will remain enabled until power to the device is removed or the EWDS instruction is sent The EWDS instruction can be used to disable all S93WD462 WD463 write and clear instructions and will prevent any accidental writing or clearing of the device Data can be read normally from the device regardless of the write enable disable status Page Write 93WD462 Assume WEN has been issued The host will then take CS high and begin clocking in the start bit write command and 7 bit address
8. MIT MICROELECTRONICS Inc 2029 2 2 1 23 01 7 S93WD462 S93WD463 PIN CAPACITANCE 1 This parameter is tested initially and after a design or process change that affects the parameter A C CHARACTERISTICS over recommended operating conditions unless otherwise specified Symbol Test Max Units Conditions Cour OUTPUT CAPACITANCE DO 5 pF Vour OV Cn INPUT CAPACITANCE CS SK DI ORG 5 pF Vin OV Note 2029 PGM T4 0 Limits Vcc22 7V 4 5V Vcc 4 5V 5 5V Test SYMBOL PARAMETER Min Max Min Max JUNITS Conditions tcss CS Setup Time 100 50 ns tcsH CS Hold Time 0 0 ns tpis DI Setup Time 200 100 ns tDIH DI Hold Time 200 100 ns tPD1 Output Delay to 1 0 5 0 25 Us tPDO Output Delav to 0 0 5 0 25 Us tuzo Output Delay to High Z 200 iod ches eo tew Program Erase Pulse Width 10 10 ms tCSMIN Minimum CS Low Time 0 5 0 25 us tSKHI Minimum SK High Time 0 5 0 25 Us tsKLOW Minimum SK Low Time 0 5 0 25 us tsv Output Delay to Status Valid 0 5 0 25 us SKmax Maximum Clock Frequency DC 500 DC 1000 KHZ Note 2029 PGM T6 0 1 This parameter is tested initially and after a design or process change that affects the parameter 2029 2 2 1 23 01 SUMMIT MICROELECTRONICS Inc S93WD462 S93WD463 RESET CIRCUIT AC and DC ELECTRICAL CHARACTERISTICS Twin waeseroaaoar f ST ts E st eee es ee MT 202
9. OIC B 4 5V to 5 5V VTRIP min 4 50V 2 7 2 7V to 5 5V VTRIP min 2 55V 2029 Tree 2 0 SUMMIT MICROELECTRONICS Inc 2029 2 2 1 23 01 13 FI S93WD462 593WD463 NOTICE SUMMIT Microelectronics Inc reserves the right to make changes to the products contained in this publication in order to improve design performance or reliabilitv SUMMIT Microelectronics Inc assumes no responsibilitv for the use of anv circuits described herein convevs no license under anv patent or other right and makes no representation that the circuits are free of patent infringement Charts and schedules contained herein reflect representative operating parameters and mav varv depending upon a user s specific application While the information in this publication has been carefully checked SUMMIT Microelectronics Inc shall not be liable for any damages arising as a result of any error or omission SUMMIT Microelectronics Inc does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness Products are not authorized for use in such applications unless SUMMIT Microelectronics Inc receives written assurances to its satisfaction that a the risk of injury or damage has been minimized b the user assumes all such risks and c potential liability of SUMMIT M
10. SUMMIT MICROELECTRONICS Inc S93WD462 S93WD463 Precision Supply Voltage Monitor and Reset Controller With a Watchdog Timer and 1k bit Microwire Memory FEATURES OVERVIEW Precision Monitor amp RESET Controller The S93WD462 and S93WD463 are precision power RESET and RESET Outputs supervisory circuits providing both active high and Guaranteed RESET Assertion to Vcc z 1V active low reset output Both devices also incorporate a 150ms Reset Pulse Width l Eur Internal 1 26V Reference with 1 Accuracy watchdog timer with a nominal time out value of 1 6 ZERO External Components Required seconds e Watchdog Timer Both devices have 1k bits of E7PROM memory that is Nominal 1 6 Second Time out Period accessible via the industry standard microwire bus The Reset by Any Transition of CS S93WD462 is configured with an internal ORG pin tied Memory L providing a 8 bit bvte CE e the 4K NiE Mi i 93WD463 is configured with an internal ORG pin tied ge E DI dS memory high providing a 16 bit word organization Both the Internally Ties ORG Low S93WD462 and S938WD463 have page write capabil 100 Compatible With all 8 bit ity The devices are designed for a minimum 100 000 Implementations program erase cycles and have data retention in ex Sixteen Byte Page Write Capability cess of 100 years S93WD463 Internally Ties ORG High 100 Compatible With all 16 bit Implementations Eight Word Page
11. WATCHDOG TIMER DESCRIPTION The S93WD462 WD463 has a watchdog timer with a nominal time out period of 1 6 seconds Whenever the watchdog times out it will generate a reset output to both pins 6 and 7 The watchdog timer is reset by any transition on CS The watchdog timer will be held in a reset state during power on while Vcc is less than Vrnip Once Vcc exceeds Vtrip the watchdog will continue to be held in a reset state for the tpurst period After tpurst it will be released and the timer will begin operation If either reset input is asserted the watchdog timer will be reset and remain in the reset condition until either tPunsT has expired or the reset input is released whichever is longer GENERAL OPERATION The S93WD462 WD463 is a 1024 bit nonvolatile memory intended for use with industry standard microproces sors The S93WD463 is organized as X16 seven 9 bit instructions control the reading writing and erase operations of the device The S93WD462 is organized as X8 seven 10 bit instructions control the reading writing and erase operations of the device The device operates on asingle 3V or 5V supply and willgenerate on chip the high voltage required during any write opera tion SUMMIT MICROELECTRONICS Inc FI S93WD462 593WD463 Instructions addresses and write data are clocked into the DI pin on the rising edge of the clock SK The DO pin is normally in a high impedance state except when reading data from the
12. ars Vzap 9 ESD Susceptibility 2000 Volts TABOA Latch Up 100 mA D C OPERATING CHARACTERISTICS over recommended operating conditions unless otherwise specified Limits Symbol Parameter Min Typ Max Units Test Conditions lcc Power Supply Current 3 mA DI 0 0V fsk 1MHz Operating Vcc 5 0V CS 5 0V Output Open IsB Power Supply Current 50 uA CS 0V Standby Reset Outputs Open lui Input Leakage Current 2 HA Vin OV to Vcc ILo Output Leakage Current 10 uA Vout OV to Vcc Including ORG pin CS 0V Vind Input Low Voltage 0 1 0 8 V 4 5V Vcc 5 5V VIHA Input High Voltage 2 Vcc41 V VIL2 Input Low Voltage 0 VccXO0 2 V 1 8V Vcc 2 7V ViH2 Input High Voltage VccX0 7 Vcc 1 V Vout Output Low Voltage 0 4 V 4 5V Vcoc 5 5V VoHt Output High Voltage 2 4 V lo 2 1mA loH 400HA VoL2 Output Low Voltage 0 2 V 1 8V Vcce2 7V VoH2 Output High Voltage Vcc 0 2 V lo 1mA loH 100A 2029 PGM T3 0 Note 1 The minimum DC input voltage is 0 5V During transitions inputs may undershoot to 2 0V for periods of less than 20 ns Maximum DC voltage on output pins is Voc 0 5V which may overshoot to Vcc 2 0V for periods of less than 20 ns 2 Output shorted for no more than one second No more than one output shorted at a time 3 This parameter is tested initially and after a design or process change that affects the parameter 4 Latch up protection is provided for stresses up to 100 mA on address and data pins from 1V to Voc HIV SUM
13. device or when checking the ready busy status after a write operation The ready busy status can be determined after the start of a write operation by selecting the device CS high and polling the DO pin DO low indicates that the write operation is not completed while DO high indicates that the device is ready for the next instruction See the Applications Aid section for detailed use of the ready busy status The format for all instructions is one start bit two op code bits and either six x16 or seven x8 address or instruction bits Read Upon receiving a READ command and an address clocked into the DI pin the DO pin of the S93WD462 WD463 will come out of the high impedance state and will first output an initial dummy zero bit then begin shifting out the data addressed MSB first The output data bits will toggle on the rising edge ofthe SK clock and are stable after the specified time delay tPpo or tpp Write After receiving a WRITE command address and the data the CS Chip Select pin must be deselected for a minimum of 250ns tcsmin The falling edge of CS will start automatic erase and write cycle to the memory location specified in the instruction The ready busy status of the S93WD462 WD463 can be determined by selecting the device and polling the DO pin P skr t sow gt tcsh SK tDIH Di AQUA vann OQQOQOOOQ varn XOU UU CS tpis tppo PD1 CSM
14. icroelectronics Inc is adequately protected under the circumstances Copyright 2001 SUMMIT Microelectronics Inc This Document supersedes all previous versions 14 2029 2 2 1 23 01 SUMMIT MICROELECTRONICS Inc
15. n The falling edge of CS will start the self clocking data write to all memory locations in the device The clocking of the SK pin is not necessary after the device has entered the self clocking mode The ready busy status of the S93WD462 WD463 can be deter mined by selecting the device and polling the DO pin It is not necessary for all memory locations to be cleared before the WRAL command is executed address Internally the address pointer is incremented after receiving each group of sixteen clocks however once the address counter reaches xxx x111 it will roll over to xx x000 with the next clock After the last bit is clocked in no internal write operation will occur until CS is brought low Continuous Read This begins just like a standard read with the host issuing a read instruction and clocking out the data byte word If the host then keeps CS high and continues generating clocks on SK the S98WD462 WD4A6S will output data from the next higher address location The S93WD462 WD463 will continue incrementing the address and outputting data so long as CS stays high If the highest address is reached the address counter will roll over to address 0000 CS going low will reset the instruction register and any subsequent read must be initiated in the normal man ner of issuing the command and address SUMMIT MICROELECTRONICS Inc FI S93WD462 593WD463 JIMMILITA r cs CS V STATUS STANDBY VERIFY AN AN 1
16. operation during brownout and power up down conditions It is config ured with two open drain reset outputs pin 7 is an active high output and pin 6 is an active low output During power up the reset outputs remain active until Vcc reaches the Vrnip threshold The outputs will con tinue to be driven for approximately 150ms after reaching 2 2029 2 2 1 23 01 Vrnip The reset outputs will be valid so long as Vcc is 1 0V During power down the reset outputs will begin driving active when Vcc falls below VTRIP The reset pins are I Os therefore the S93WD462 WD4A63 can act as a signal conditioning circuit for an externally applied reset The inputs are edge triggered that is the RESET input will initiate a reset time out after detecting a low to high transition and the RESET input will initiate a reset time out after detecting a high to low transition Refer to the applications Information section for more details on device operation as a debounce reset extender circuit It should be noted the reset outputs are open drain When used as outputs driving a circuit they need to be either tied high RESET or tied to ground RESET through the use of pull up or pull down resistors Refer to the applications aid section for help in determining the value of resistor to be used Internally these pins are weakly pulled up RESET and pulled down RESET there fore ifthe signals are not being used the pins may be left unconnected
17. uration to clear the peripheral or to protect data stored in a nonvolatile memory The I O capability of the RESET pins can provide a solution The system s reset signal to the peripheral can be fed into the S93WD462 WD463 andit in turn can clean up the signal and provide a known entity to the peripheral s circuits The figure below shows the basic timing characteristics under the assumption the reset input is shorter in duration than tpurst The same reset output affect can be attained by using the active high reset input RESET Input RESET Output RESET Olu tpURST 2029 T fig09 2 0 When planning your resistor pull up and pull down values use the following chart to help determine min resistances Worst Case RESET Sink Source Capabilities at Various Vcc Levels Parameter Symbol Condition min Typ v ov toto KA Ci RESET Output Vo Woo 1 2V l 100a fe fo Voltage vezv osa fa Voo 36V to s00ua fo vezav az fo RESET Output Vos C veo 12v omis Voltage Ove 30v aro TVoo 36V toxima Wo 4SVlaeimA olojolojololojojole APRIRPR IRL O lwO W w o RESET Output Voc 1 2V lon 800UA Vcc 0 75 Voltage Voc 3 0V loH 800HA Voc 3 6V lon 800pA Voc 4 5V lon 800pA 2029 PGM T5 0 SUMMIT MICROELECTRONICS Inc 2029 2 2 1 23 01 11 FI S93WD462 593WD463 Readv Busv Status During the internal write operation the S93WD462 WD463
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