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Silicon Laboratories C8051F340 User's Manual

1. D D1 Table 4 2 TQFP 48 Package Dimensions n MM MIN TYP MAX 7420 1 005 015 A2 0 95 1 00 1 05 b 017 022 027 D 900 Di 7 00 e 0 50 E 9 00 E1 7 00 48 5 1 IDENTIFIER A2 P 1 b 1 Figure 4 2 48 Package Diagram Rev 0 5 37 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 PO 4 PO 5 PO 6 PO 7 P1 0 n E P1 1 SN o a 8 3 C8051F342 3 6 7 Top View LO 2 E a oO P2 6 P2 4 P2 3 P2 2 N RST C2CK P3 0 C2D Figure 4 3 LQFP 32 Pinout Diagram Top View 38 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 D D1 Table 4 3 32 Package Dimensions II i MIN TYP MAX 1 60 1 A1 0 05 0 15 A2 135 1 40 1 45 E1 E b 0 30 0 37 0 45 det D 9
2. NA Comparator 0 wired OR 4 CORSEF V Missing Clock Detector one PCA x WIDU Software Reset SWRSF Errant EN FLASH o Internal LF Operation o Oscillator alg ka g Ole Ole 215 Internal Oscillator i System Clock USB VBUS EISE CIP 51 Controller Transition Microcontroller System Reset XTAL1 X External Core Oscillator lt Clock Select XTAL2 X __ Drive Extended Interrupt Handler Figure 1 3 On Chip Clock and Reset 22 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 1 2 On Chip Memory The CIP 51 has a standard 8051 program and data address configuration It includes 256 bytes of data RAM with the upper 128 bytes dual mapped Indirect addressing accesses the upper 128 bytes of general purpose RAM and direct addressing accesses the 128 byte SFR address space The lower 128 bytes of RAM are accessible via direct and indirect addressing The first 32 bytes are addressable as four banks of general purpose registers and the next 16 bytes can be byte addressable or bit addressable Program memory consists of 64 k C8051F340 2 4 6 or 32 k C8051F341 3 5 7 bytes of Flash This memory may be reprogrammed in system in 512 byte sectors and requires no special off chip program ming voltage On chip XRAM is also included for the entir
3. Pre scaled Clock 0 TRIS THO MN 8 bits Eu E SYSCLK 1 TFO gt Interrupt TRO 0 2 ET O HE TTO gt o l i TRO 1 Crossbar i GATEO INOPL INTO Figure 21 3 TO Mode 3 Block Diagram 246 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 21 1 TCON Timer Control R W R W R W R W R W R W R W Reset Value TR1 TFO TRO IE1 IT1 IEO ITO 00000000 Bit6 Bit5 Bit4 Bit3 Bit2 Biti BitO SFR Address bit addressable 0x88 TF1 Timer 1 Overflow Flag Set by hardware when Timer 1 overflows This flag can be cleared by software but is auto matically cleared when the CPU vectors to the Timer 1 interrupt service routine 0 No Timer 1 overflow detected 1 Timer 1 has overflowed TR1 Timer 1 Run Control 0 Timer 1 disabled 1 Timer 1 enabled TFO Timer 0 Overflow Flag Set by hardware when Timer 0 overflows This flag can be cleared by software but is auto matically cleared when the CPU vectors to the Timer 0 interrupt service routine 0 No Timer 0 overflow detected 1 Timer 0 has overflowed TRO Timer 0 Run Control 0 Timer 0 disabled 1 Timer 0 enabled IE1 External Interrupt 1 This flag is set by hardware when an edge level of type defined
4. Register Address Description Page ACC OxEO Accumulator 86 ADCOCF OxBC ADCO Configuration 50 ADCOCN OxE8 ADCO Control 51 ADCOGTH 0 4 ADCO Greater Than Compare High 52 ADCOGTL 0xC3 ADCO Greater Than Compare Low 52 ADCOH OxBE ADCO High 50 ADCOL OxBD ADCO Low 50 ADCOLTH 0xC6 ADCO Less Than Compare Word High 53 ADCOLIL 0xC5 ADCO Less Than Compare Word Low 53 AMXON AMUXO Negative Channel Select 49 AMXOP OxBB AMUXO Positive Channel Select 48 B OxFO B Register 87 CKCON Ox8E Clock Control 249 CLKMUL OxB9 Clock Multiplier 142 CLKSEL OxA9 Clock Select 144 CPTOCN Ox9B ComparatorO Control 62 CPTOMD 0x9D ComparatorO Mode Selection 64 CPTOMX Ox9F Comparator0 MUX Selection 63 CPT1CN Ox9A Comparator1 Control 65 CPT1MD 0x9C Comparator1 Mode Selection 67 CPT1MX Ox9E Comparator1 MUX Selection 66 DPH 0x83 Data Pointer High 85 DPL 0x82 Data Pointer Low 85 EIE1 OxE6 Extended Interrupt Enable 1 92 EIE2 0 Extended Interrupt Enable 2 94 EIP1 OxF6 Extended Interrupt Priority 1 93 EIP2 OxF7 Extended Interrupt Priority 2 94 EMIOCN OxAA External Memory Interface Control 120 EMIOCF 0x85 External Memory Interface Configuration 121 EMIOTC 0x84 External Memory Interface Timing 126 FLKEY 0 7 Flash Lock and Key 114 FLSCL 0xB6 Flash Scale 115 IE 0xA8 Interrupt Enable 90 IP 0xB8 Interrupt Priority 91 ITO1CF OxE4 INTO INT1 Configuration 95 OSCICL 0xB3 Internal Oscilla
5. 191 17 SMBus Figure 17 1 SMBus Block Diagram ee eee ee ae as 193 Figure 17 2 Typical SMBus 194 Figure 17 3 SMBus TrariSaellOfl cor vest cti e rebelde bees bea cue 195 Table 17 1 SMBus Clock Source Selection eese 198 Figure 17 4 Typical SMBus SCL 199 Table 17 2 Minimum SDA Setup and Hold 199 Table 17 3 Sources for Hardware Changes to SMBOCN 203 Figure 17 5 Typical Master Transmitter 205 Figure 17 6 Typical Master Receiver 206 Figure 17 7 Typical Slave Receiver 207 Figure 17 8 Typical Slave Transmitter 208 Table 17 4 SMBus Status 4440 0 209 18 UARTO Figure 18 1 UARTO Block o 211 Figure 18 2 UARTO Baud Rate Logic n 212 Figure 18 3 UART Interconnect Diagram dere 213 Figure 18 4 8 Bit UART Timing 213 Figure 18 5 9 Bit UART Timi
6. 252 21 2 3 Timer 2 Capture Modes USB Start of Frame or LFO Falling Edge 253 Zi 257 21 3 1 16 bit Timer with 0 257 21 3 2 8 bit Timers with 258 21 3 3 USB Start of Frame 4 259 22 Programmable Counter Array 222 2 nn 263 z mueren ADLER 264 22 2 Capture Compare 201 265 22 2 1 Edge triggered Capture Mode 266 22 2 2 Software Timer Compare 267 22 2 3 High Speed Output eee ut cep cias 268 22 2 4 Frequency Output ie tb ERN S 269 22 2 5 8 Bit Pulse Width Modulator 270 22 2 6 16 Bit Pulse Width Modulator 271 22 3 Watchdog Timer Mode 272 22 3 1 Watchdog Timer 272 22 3 2 Watchdog Timer Usage netos k 273 22 4 Register Descriptions for 274 29 62 Interface rod RF un Dra abus YR DRE 279 23 112 Interface coa coat uh vb e i ob nee Rr tbi eret 279 292 021 55h 3t lig ss deett
7. 85 SFR Definition 9 4 PSW Program Status Word 86 SFR Definition 9 5 Accumulator lt 2 st pad di kate rak nd TRIP ERES 86 SFR Definition 9 6 B B Register 87 SFR Definition 9 7 IE Interrupt Enable 90 SFR Definition 9 8 IP Interrupt Priority 91 SFR Definition 9 9 EIE1 Extended Interrupt Enable 1 92 SFR Definition 9 10 EIP1 Extended Interrupt Priority 1 93 SFR Definition 9 11 EIE2 Extended Interrupt Enable 2 94 SFR Definition 9 12 EIP2 Extended Interrupt Priority 2 94 SFR Definition 9 13 ITO1CF INTO INT1 Configuration 95 SFR Definition 9 14 PCON Power Control 97 SFR Definition 10 1 PFEOCN Prefetch Engine Control 99 SFR Definition 11 1 VDMOCN Vpp Monitor Control 103 SFR Definition 11 2 RSTSRC Reset Source 106 SFR Definition 12 1 PSCTL Program Store R W Control 114 SFR Definition 12 2 FLKEY Flash Lock and Key 114 SFR Definition 12 3 FLSCL Flash 115 SFR Definition 13 1 EMIOCN External Memory Interface Control
8. C8051F340 1 2 3 4 5 6 7 P3 1 P3 7 Unavailable on 32 pin Package 4 5 6 7 0 710 1 2 3 NSS is only pinned out in 4 wire SPI mode SYSCLK o o 1 1 o0 ofo ofo 0 00 0 0 0 POSKIP 0 7 P1SKIP 0 7 P2SKIP 0 7 P3SKIP 0 7 Port pin potentially available to peripheral Sasina Special Function Signals are not assigned by the Crossbar When these signals are enabled the Crossbar must be manually configured to skip their corresponding port pins Figure 15 4 Crossbar Priority Decoder with Crystal Pins Skipped Registers XBRO XBR1 and XBR2 are used to assign the digital I O resources to the physical I O Port pins Note that when the SMBus is selected the Crossbar assigns both pins associated with the SMBus SDA and SCL when either UART is selected the Crossbar assigns both pins associated with the UART TX and RX UARTO pin assignments are fixed for bootloading purposes UART TXO is always assigned to P0 4 UART RXO is always assigned to PO 5 Standard Port l Os appear contiguously after the prioritized functions have been assigned Important Note The SPI can be operated in either 3 wire or 4 wire modes depending on the state of the NSSMD1 NSSMDO bits in register SPIOCN According to th
9. 229 20 1 Signal Descriptions 5 oin cotta tae hod en te eon ere ves b 230 20 1 1 Master Out Slave In 00 11 230 20 1 2 Master In Slave Out 5 230 201 3 Serial Clock SCK aient hasten a ule 230 all A Slave Select NGO uad otii i per AE RU CUI k 230 20 2 SPIO Master Mode ODOFallOT e a ccn pn 231 20 3 9PI0 Slave 233 20 4 5 10 Interrupt Sources isti oaa la 233 20 5 Serial Clock ieee ea ead ee b odd Db a nn nnnenee 234 20 6 SPI Special Function 236 ANN CH 9 243 21 1 Timer Timer eoa dg FERRE UR ned reer MR eec xor rer 243 21 1 1 Mode 0 13 bit 00 243 21 1 2 Mode 1 16 bit 0 244 21 1 3 Mode 2 8 bit Counter Timer with Auto Reload 245 21 1 4 Mode 3 Two 8 bit Counter Timers Timer 0 Only 246 6 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 2a REZANIA N 251 21 2 1 16 bit Timer with 251 21 2 2 8 bit Timers with
10. Parameter Conditions Min Typ Max Units RST Output Low Voltage loy 8 5 mA Vpp 2 7 to 3 6 V 0 6 V RST Input High Voltage 0 7 x Vpp V RST Input Low Voltage 0 3 x Vpp RST Input Pull Up Current RST 0 0 V 25 40 Vpp POR Threshold 2 40 2 55 2 70 V Missing Clock Detector Tim Time from last system clock ris 100 220 500 us eout ing edge to reset initiation Delay between release of any Reset Time Delay reset source and code execution 5 0 us at location 0x0000 Minimum RST Low Time to 15 S Generate a System Reset H Vpp Monitor Turn on Time 100 us Vpp Monitor Supply Current 20 50 0 5 107 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 NOTES 108 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 12 Flash Memory On chip re programmable Flash memory is included for program code and non volatile data storage The Flash memory can be programmed in system through the C2 interface or by software using the MOVX instruction Once cleared to logic 0 a Flash bit must be erased to set it back to logic 1 Flash bytes would typically be erased set to OxFF before being reprogrammed The write and erase operations are automat ically timed by hardware for proper execution data polling to determine the end of the write erase opera tion is not required Code execution is stalled during a Flash write erase operation Refer to Table 12 1 for complete Flash memory electrical
11. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address OxB4 Bits7 0 SBRLL1 7 0 Low Byte of reload value for UART1 Baud Rate Generator e Rev 0 5 227 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 NOTES 228 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 20 Enhanced Serial Peripheral Interface SPIO The Enhanced Serial Peripheral Interface SPIO provides access to a flexible full duplex synchronous serial bus SPIO can operate as a master or slave device in both 3 wire or 4 wire modes and supports mul tiple masters and slaves on a single SPI bus The slave select NSS signal can be configured as an input to select SPIO in slave mode or to disable Master Mode operation in a multi master environment avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers NSS can also be configured as a chip select output in master mode or disabled for 3 wire operation Additional gen eral purpose port I O pins be used to select multiple slave devices in master mode 2 SFR Bus 2 SPIOCKR SPIOCFG SPIOCN Zero gt z li amp aar m z Au z S5555555 575522284 29092282 0000 O2 C
12. 24 4 4 52 5 4 1 Window Detector In Single Ended Mode 54 5 4 2 Window Detector In Differential 55 6 Voliade Reference T PH 57 s GOompalr ats iodtp dus no zone 59 8 Voltage Regulator d ER sese i dg rw EE DR E daa 69 8 1 Regulator Mode 02 24 0 000 69 8 2 VBUS DGOIOGHOfl zia utu E 69 9 CIP 51 Microcontroller 2 22 73 9 Te ISEMUICHION SOL NE 74 9 1 1 Instruction and CPU Timing errem tree 74 9 1 2 MOVX Instruction and Program 75 9 2 Memory ORGANIZANON hel obese etate tea 79 9 2 1 Program REUS 79 9 2 2 DATA Memory s ssa 80 9 2 3 General Purpose Registers 4 0 0 41 80 9 2 4 Bit Addressable EO6allofis ue iet o sie ni n pueriles 80 SUA NIC gebe eec pa ia 80 9 2 6 Special Function 81 9 2 7 Register Descriptions iuuat e
13. Notes 1 Includes ADC offset gain and linearity variations 2 Represents mean one standard deviation 56 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 6 Voltage Reference The Voltage reference MUX on C8051F340 1 2 3 4 5 6 7 devices is configurable to use an externally con nected voltage reference the on chip reference voltage generator or the power supply voltage Vpp see Figure 6 1 The REFSL bit in the Reference Control register REFOCN selects the reference source For the internal reference or an external source REFSL should be set to 0 For Vpp as the reference source REFSL should be set to 1 The BIASE bit enables the internal ADC bias generator which is used by the ADC and Internal Oscillator This enable is forced to logic 1 when either of the aforementioned peripherals is enabled The ADC bias generator may be enabled manually by writing a 1 to the BIASE bit in register REFOCN see SFR Defini tion 6 1 for REFOCN register details The Reference bias generator see Figure 6 1 is used by the Internal Voltage Reference Temperature Sensor and Clock Multiplier The Reference bias is automatically enabled when any of the aforementioned peripherals are enabled The electrical specifications for the volt age reference and bias circuits are given in Table 6 1 Important Note About the VREF Pin The VREF pin when not using the on chip voltage reference or an e
14. Bits7 0 P2 7 0 Write Output appears on I O pins per Crossbar Registers when XBARE 1 0 Logic Low Output 1 Logic High Output high impedance if corresponding PEMDOUT n bit 0 Read Always reads 0 if selected as analog input in register P2MDIN Directly reads Port pin when configured as digital input 0 P2 n pin is logic low 1 P2 n pin is logic high SFR Definition 15 13 P2MDIN Port2 Input Mode R W R W R W R W R W R W Reset Value 11111111 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0xF3 Analog Input Configuration Bits for P2 7 P2 0 respectively Port pins configured as analog inputs have their weak pull up digital driver and digital receiver disabled 0 Corresponding P2 n pin is configured as an analog input 1 Corresponding P2 n pin is not configured as an analog input 62 Rev 0 5 157 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 15 14 P2MDOUT Port2 Output Mode R W R W R W R W R W R W R W Reset Value 00000000 Bit6 Bit5 Bit4 Bit2 Bit Bito SFR Address OxA6 Bits7 0 Output Configuration Bits for P2 7 P2 0 respectively ignored if corresponding bit in regis ter P2MDIN is logic 0 0 Corresponding P2 n Output is open drain 1 Corresponding P2 n Output is push pull SFR Definition 15 15 P2SKIP Port2 Skip R W R W R W R W R W Reset Value 00000000 Bit
15. Table Title Page No ADCO Electrical Characteristics 56 Voltage Reference Electrical Characteristics 58 Comparator Electrical Characteristics 68 Voltage Regulator Electrical Specifications 69 Reset Electrical Characteristics 107 Flash Electrical Characteristics 111 AC Parameters for External Memory Interface 133 Oscillator Electrical Characteristics 145 Port I O DC Electrical Characteristics 162 USB Transceiver Electrical Characteristics 191 32 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 4 Pinout and Package Definitions Table 4 1 Pin Definitions for the C8051F340 1 2 3 4 5 6 7 Pin Numbers Name Type Description 48 pin 32 pin Vpp 10 6 Power In 2 7 3 6 V Power Supply Voltage Input Power 3 3 V Voltage Regulator Output See Section 8 Out GND Ground RST 13 D Device Reset Open drain output of internal POR or Vpp monitor An external source can initiate a system reset by driving this pin low for at least 15 us See Section 11 C2CK D O Clock signal for the C2 Debug Interface C2D 14 DI O Bi directional data signal for the C2 Debug Interface P3 0 10 DV O 3 0 See Section 15 for a complete description of Port 3 C2D D I O Bi directional data signal for the C2 Debug Interface REGIN 11 7 Power In 5 V Regulator Input This pin is the input to the on chip volt age regulator
16. 260 22 Programmable Counter Array PCAO Figure 22 1 PGA Block DISOESITI aieo En n o e eR od retta 263 Table 22 1 PCA Timebase Input 264 Figure 22 2 PCA Counter Timer Block 264 Table 22 2 PCAOCPM Register Settings for PCA Capture Compare Modules 265 Figure 22 3 PCA Interrupt Block Diagram 265 Figure 22 4 PCA Capture Mode Diagram eese 266 Figure 22 5 PCA Software Timer Mode 267 Figure 22 6 PCA High Speed Output Mode 268 Figure 22 7 PCA Frequency Output 269 Figure 22 8 PCA 8 Bit PWM Mode 270 Figure 22 9 PCATo BIEPWM MOGOS erat an 271 Figure 22 10 PCA Module 4 with Watchdog Timer Enabled 272 Table 22 3 Watchdog Timer Timeout 1 273 23 C2 Interface Figure 23 1 Typical C2 Pin Satis see c e evt pet repr e eel a a eed t return 281 12 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 List of Registers SFR Definition 5 1 AMXOP AMUXO Positive Channel Select 48 SFR Definition 5 2 AMXON AMUXO Negative Channel Select
17. Write to N 1 PCAOCPLn 8 bit Adder PCAOCPHn 0 o SEXY Crossbar Port I O be OE 5 Enable 8 bit PCAOCPLn 0 Reset D Comparator C AA AO MO P P TIG 6 ninin n X 00 X PCA Timebase PCA0L Figure 22 7 PCA Frequency Output Mode e Rev 0 5 269 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 22 2 5 8 Bit Pulse Width Modulator Mode Each module can be used independently to generate a pulse width modulated PWM output on its associ ated CEXn pin The frequency of the output is dependent on the timebase for the PCA counter timer The duty cycle of the PWM output signal is varied using the module s PCAOCPLn capture compare register When the value in the low byte of the PCA counter timer PCAOL is equal to the value in PCAOCPLn the output on the CEXn pin will be set When the count value in PCAOL overflows the CEXn output will be reset see Figure 22 8 Also when the counter timer low byte PCAOL overflows from OxFF to 0x00 PCAOCPLn is reloaded automatically with the value stored in the module s capture compare high byte PCAOCPHn without software intervention Setting the ECOMn and PWMn bits in the PCAOCPMn register enables 8 Bit Pulse Width Modulator mode The duty cycle for 8 Bit PWM Mode is given by Equation 22 2 Important Note About Capture C
18. PWM16 ECOM CAPP CAPN MAT TOG PWM ECCF Operation Mode Capture triggered by positive edge on X X 1 0 0 0 0 X CEXn X X 0 1 0 0 0 X Capture triggered by negative edge on CEXn X X 1 1 0 0 0 X Capture triggered by transition on CEXn X 1 0 0 1 0 0 X Software Timer X 1 0 0 1 1 0 X High Speed Output X 1 0 0 X 1 1 X Frequency Output 0 1 0 0 X 0 1 X 8 Pulse Width Modulator 1 1 0 0 X 0 1 X 16 Bit Pulse Width Modulator X Don t Care for n 2 0 to 4 PCAOCPMn PCAOCN PCAOMD P E CICIMT P E C C C C O eer 55 1 MIP NIn n n F 4 32 1 0 L E C 21110 6 n nin n K v Va Timer Overflow ee ECCFO P 0 EPCAO EA rn 4 x P eeu be D ERR a o 1 1 Decoder ECCF1 u Vo RIGGEN x oo ECCF2 PCA Module 2 mo CCF2 1 ECCF3 Y id ECCF4 PCA Module 4 xu CCF4 1 Figure 22 3 PCA Interrupt Block Diagram e Rev 0 5 265 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 22 2 1 Edge triggered Capture Mode In this mode a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter timer and load it into the corresponding module s 16 bit capture compare register PCAOCPLn and PCAOCPHn CAPPn and CAPNn bits in the PCAOCPMn register are used to select the type of transi tion that triggers the capture low to high transition positive edge high to low transition
19. ADOTM 1 2 Track Convert Low Power Mode 4 5 6 7 8 9 10 11 SAR Clocks ADOTM 0 eed Convert Track Figure 5 4 10 Bit ADC Track and Conversion Example Timing 46 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 5 3 3 Settling Time Requirements When the ADCO input configuration is changed i e a different AMUXO selection is made a minimum tracking time is required before an accurate conversion can be performed This tracking time is determined by the AMUXO resistance the ADCO sampling capacitance any external source resistance and the accu racy required for the conversion Note that in low power tracking mode three SAR clocks are used for tracking at the start of every conversion For most applications these three SAR clocks will meet the mini mum tracking time requirements Figure 5 5 shows the equivalent ADCO input circuits for both Differential and Single ended modes Notice that the equivalent time constant for both input circuits is the same The required ADCO settling time for a given settling accuracy SA may be approximated by Equation 5 1 When measuring the Temperature Sensor output or Vpp with respect to GND AroraL reduces to Ryyy See Table 5 1 for ADCO minimum settling time requirements n 2 C 2 RrorALCSAMPLE Equation 5 1 ADCO Settling Time Requirements Where SA is the settling accuracy given as a fraction of an LSB for example 0 25 to set
20. Debug Circuitry The C8051F340 1 2 3 4 5 6 7 devices include on chip Silicon Labs 2 Wire C2 debug circuitry that pro vides non intrusive full speed in circuit debugging of the production part installed in the end application Silicon Labs debugging system supports inspection and modification of memory and registers break points and single stepping No additional target RAM program memory timers or communications chan nels are required All the digital and analog peripherals are functional and work correctly while debugging All the peripherals except for the USB ADC and SMBus are stalled when the MCU is halted during sin gle stepping or at a breakpoint in order to keep them synchronized The C8051F340DK development kit provides all the hardware and software necessary to develop applica tion code and perform in circuit debugging with the 8051 340 1 2 3 4 5 6 7 MCUs kit includes soft ware with a developer s studio and debugger 8051 assembler and linker evaluation C compiler and a debug adapter It also has a target application board with the C8051F340 MCU installed the necessary cables for connection to a PC and a wall mount power supply The development kit contents may also be used to program and debug the device on the production PCB using the appropriate connections for the programming pins The Silicon Labs IDE interface is a vastly superior developing and debugging configuration compared to stan
21. PCAOCPH4 8 bit Comparator Enable PCAOL Overflow 8 bit Adder 4 Write to Fnable PCAOCPH4 Figure 22 10 PCA Module 4 with Watchdog Timer Enabled Note that the 8 bit offset held in is compared to the upper byte of the 16 bit PCA counter This offset value is the number of PCAOL overflows before a reset Up to 256 PCA clocks may pass before the first PCAOL overflow occurs depending on the value of the PCAOL when the update is performed The total offset is then given in PCA clocks by Equation 22 4 where PCAOL is the value of the PCAOL register at the time of the update 272 Rev 0 5 6 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Offset 256 x PCAOCPL4 256 PCAOL Equation 22 4 Watchdog Timer Offset in PCA Clocks The WDT reset is generated when PCAOL overflows while there is a match between PCAOCPH4 and PCAOH Software may force WDT reset by writing 1 to the CCF4 flag PCAOCN 4 while the WDT is enabled 22 3 2 Watchdog Timer Usage To configure the WDT perform the following tasks 1 Disable the WDT by writing a 0 to the WDTE bit 2 Select the desired PCA clock source with the CPS2 CPSO bits 3 Load PCAOCPLA with the desired WDT update offset value 4 Configure the PCA Idle mode set CIDL if the WDT should be suspended while the CPU is in Idle mode 5 Enable the WDT by setting the WDTE bit to 1
22. 120 SFR Definition 13 2 EMIOCF External Memory Configuration 121 SFR Definition 13 3 EMIOTC External Memory Timing Control 126 SFR Definition 14 1 OSCICN Internal H F Oscillator Control 136 SFR Definition 14 2 OSCICL Internal H F Oscillator Calibration 137 Rev 0 5 13 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 14 3 OSCLCN Internal L F Oscillator Control 138 SFR Definition 14 4 OSCXCN External Oscillator Control 141 SFR Definition 14 5 CLKMUL Clock Multiplier Control 142 SFR Definition 14 6 CLKSEL Clock 144 SFR Definition 15 1 XBRO Port I O Crossbar Register 0 152 SFR Definition 15 2 XBR1 Port I O Crossbar Register 1 153 SFR Definition 15 3 XBR2 Port I O Crossbar Register 2 153 SFR Definition 15 4 PO Porto Latch 154 SFR Definition 15 5 POMDIN PortO Input Mode 154 SFR Definition 15 6 POMDOUT Porto Output Mode 155 SFR Definition 15 7 POSKIP PortO Skip 155 SFR Definition 15 8 P1 Portti Latch 156 SFR Definition 15 9 P1MDIN Port1 Input Mode 156 SFR Definitio
23. Figure 9 1 CIP 51 Block Diagram Rev 0 5 73 C8051F340 1 2 3 4 5 6 7 Performance The CIP 51 employs a pipelined architecture that greatly increases its instruction throughput over the stan dard 8051 architecture In a standard 8051 all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute and usually have a maximum system clock of 12 MHz By contrast the CIP 51 core executes 70 of its instructions in one or two system clock cycles with no instructions taking more than eight system clock cycles With the CIP 51 s maximum system clock at 25 MHz it has a peak throughput of 25 MIPS The CIP 51 has a total of 109 instructions The table below shows the total number of instructions that for execution time Clocks to Execute 1 2 2 4 3 3 5 4 5 4 6 6 8 Number of Instructions 26 50 5 10 7 5 2 1 2 1 Programming and Debugging Support In system programming of the Flash program memory and communication with on chip debug support logic is accomplished via the Silicon Labs 2 Wire Development Interface C2 Note that the re program mable Flash can also be read and changed a single byte at a time by the application software using the MOVC and MOVX instructions This feature allows program memory to be used for non volatile data stor age as well as updating program code under software control The on chip Silicon Labs 2 Wire C2 Development Interface all
24. 131 Figure 13 10 Multiplexed 8 bit MOVX with Bank Select Timing 132 Table 13 1 AC Parameters for External Memory 133 14 Oscillators Figure 14 1 Oscillator Dia Grant iura da AE XR aac 135 Table 14 1 Oscillator Electrical 000 145 15 Port Input Output Figure 15 1 Port I O Functional Block Diagram Port 0 through Port 3 147 Figure 15 2 Port I O Cell Block Diagram 148 Figure 15 3 Crossbar Priority Decoder with No Pins Skipped 149 Figure 15 4 Crossbar Priority Decoder with Crystal Pins Skipped 150 Table 15 1 Port I O DC Electrical 162 16 Universal Serial Bus Controller USBO Figure 16 1 USBO Block deiecit acier costo en o ndo beu 163 Table 16 1 Endpoint Addressing 044 164 10 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Figure 16 2 USBO Register Access 166 Table 16 2 USBO Controller Registers 169 Figure 16 22 USB FIFO AIlGOSllOl ois unn op kn 171 Table 16 3 FIFO Configurations 2 pred ure 172 Table 16 4 USB Transceiver Electrical
25. 49 SFR Definition 5 3 ADCOCF ADCO Configuration 50 SFR Definition 5 4 ADCOH ADCO Data Word MSB 50 SFR Definition 5 5 ADCOL ADCO Data Word LSB 50 SFR Definition 5 6 ADCOCN ADCO Control 51 SFR Definition 5 7 ADCOGTH ADCO Greater Than Data High Byte 52 SFR Definition 5 8 ADCOGTL ADCO Greater Than Data Low Byte 52 SFR Definition 5 9 ADCOLTH ADCO Less Than Data High Byte 53 SFR Definition 5 10 ADCOLTL ADCO Less Than Data Low Byte 53 SFR Definition 6 1 REFOCN Reference 58 SFR Definition 7 1 CPTOCN ComparatorO Control 62 SFR Definition 7 2 CPTOMX MUX Selection 63 SFR Definition 7 3 CPTOMD ComparatorO Mode Selection 64 SFR Definition 7 4 CPT1CN Comparator1 Control 65 SFR Definition 7 5 CPT1MX Comparator1 MUX Selection 66 SFR Definition 7 6 CPT1MD Comparator1 Mode Selection 67 SFR Definition 8 1 REGOCN Voltage Regulator Control 72 SFR Definition 9 1 DPL Data Pointer Low Byte 85 SFR Definition 9 2 DPH Data Pointer High Byte 85 SFR Definition 9 3 SP Stack
26. Parameter Conditions Min Typ Max Units Digital Supply Voltage 2 7 3 3 3 6 V Digital Supply Current with CPU Vpp 3 3 V Clock 24 MHz 15 mA active Vpp 3 8 V Clock 1 MHz 0 7 mA Vpp 3 3 V Clock 32 kHz 74 uA Digital Supply Current with CPU Vpp 3 3 V Clock 24 MHz TBD mA active and USB active Full or Vpp 3 3 V Clock 6 MHz TBD mA Low Speed Digital Supply Current with CPU Vpp 3 3 V Clock 24 MHz 9 mA inactive not accessing Flash Vpp 3 3 V Clock 1 MHz 0 5 mA Vpp 3 3 V Clock 32 kHz 74 uA Digital Supply Current suspend Oscillator not running lt 0 1 uA mode or shutdown mode Digital Supply RAM Data Reten 1 5 V tion Voltage SYSCLK System Clock C8051F340 1 2 3 0 48 MHz C8051F344 5 6 7 0 25 Tsvsu SYSCLK High Time C8051F340 1 2 3 50 MHz 9 ns C8051F344 5 6 7 18 SYSCLK Low Time C8051F340 1 2 3 50 MHz 9 ns C8051F344 5 6 7 18 Specified Operating Tempera 40 85 Notes 1 USB Requires 3 0 V Minimum Supply Voltage 2 SYSCLK must be at least 32 kHz to enable debugging Other electrical characteristics tables are found in the data sheet section corresponding to the associated peripherals For more information on electrical characteristics for a specific peripheral refer to the page indicated in Table 3 2 SILICON LABORATORIES Rev 0 5 31 C8051F340 1 2 3 4 5 6 7 Table 3 2 Index to Electrical Characteristics Tables
27. TF3LEN TSCE T3SPLIT TR3 T3CSS 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0x91 Bit7 TF3H Timer 3 High Byte Overflow Flag Set by hardware when the Timer 3 high byte overflows from OxFF to 0x00 In 16 bit mode this will occur when Timer 3 overflows from OxFFFF to 0x0000 When the Timer 3 interrupt is enabled setting this bit causes the CPU to vector to the Timer 3 interrupt service routine TF3H is not automatically cleared by hardware and must be cleared by software Bit6 TF3L Timer 3 Low Byte Overflow Flag Set by hardware when the Timer 3 low byte overflows from OxFF to 0x00 When this bit is set an interrupt will be generated if is set and Timer interrupts are enabled will set when the low byte overflows regardless of the Timer 3 mode This bit is not automat ically cleared by hardware Bit5 TF3LEN Timer 3 Low Byte Interrupt Enable This bit enables disables Timer 3 Low Byte interrupts If TF3LEN is set and Timer 3 inter rupts are enabled an interrupt will be generated when the low byte of Timer 3 overflows This bit should be cleared when operating Timer 3 in 16 bit mode 0 Timer 3 Low Byte interrupts disabled 1 Timer 3 Low Byte interrupts enabled Bit4 T3CE Timer 3 Capture Enable 0 Capture function disabled 1 Capture function enabled The timer is in capture mode with the capture event selected by bit T3CSS Each time a capture event is received th
28. 4 Timer 0 Overflow 0 oo PCAOH PCAOL Overflow y To PCA Interrupt System SYSCLK CF External Clock 8 gt To PCA Modules Figure 22 2 PCA Counter Timer Block Diagram 264 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 22 2 Capture Compare Modules Each module can be configured to operate independently in one of six operation modes Edge triggered Capture Software Timer High Speed Output Frequency Output 8 Bit Pulse Width Modulator or 16 Bit Pulse Width Modulator Each module has Special Function Registers SFRs associated with it in the CIP 51 system controller These registers are used to exchange data with a module and configure the module s mode of operation Table 22 2 summarizes the bit settings the PCAOCPMnh registers used to select the PCA capture com pare module s operating modes Setting the ECCFn bit in a PCAOCPMn register enables the module s CCFn interrupt Note PCAO interrupts must be globally enabled before individual CCFn interrupts are rec ognized PCAO interrupts are globally enabled by setting the EA bit and the EPCAO bit to logic 1 See Figure 22 3 for details on the PCA interrupt configuration Table 22 2 PCAOCPM Register Settings for PCA Capture Compare Modules
29. Note Applies only to external oscillator sources e Rev 0 5 145 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 NOTES 146 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 15 Port Input Output Digital and analog resources are available through 40 I O pins C8051F340 1 4 5 or 25 VO pins C8051F342 3 6 7 Port pins are organized as shown in Figure 15 1 Each of the Port pins can be defined as general purpose I O GPIO or analog input Port pins 0 7 can be assigned to one of the internal digital resources as shown in Figure 15 3 The designer has complete control over which functions are assigned limited only by the number of physical O pins This resource assignment flexibility is achieved through the use of a Priority Crossbar Decoder Note that the state of a Port I O pin can always be read in the corresponding Port latch regardless of the Crossbar settings The Crossbar assigns the selected internal digital resources to the pins based on the Priority Decoder Figure 15 3 and Figure 15 4 The registers XBRO XBR1 and XBR2 defined in SFR Definition 15 1 SFR Definition 15 2 and SFR Definition 15 3 are used to select internal digital functions All Port Os are 5 V tolerant refer to Figure 15 2 for the Port cell circuit The Port O cells are configured as either push pull or open drain the Port Output Mode registers PRMDOUT where n 0 1 2 3 4 Com plete Electrical Specificat
30. C8051F340 1 2 3 4 5 6 7 SFR Definition 21 14 TMR3RLL Timer 3 Reload Register Low Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0x92 Bits 7 0 TMR3RLL Timer 3 Reload Register Low Byte TMR8RLL holds the low byte of the reload value for Timer 3 when operating in auto reload mode or the captured value of the TMR3L register when operating in capture mode SFR Definition 21 15 TMRSRLH Timer 3 Reload Register High Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0x93 Bits 7 0 TMRBRLH Timer Reload Register High Byte The TMRBRLH holds the high byte of the reload value for Timer 3 when operating in auto reload mode or the captured value of the TMR3H register when operating in capture mode SFR Definition 21 16 TMR3L Timer 3 Low Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0x94 Bits 7 0 TMR3L Timer Low Byte In 16 bit mode the TMR3L register contains the low byte of the 16 bit Timer 3 In 8 bit mode TMR3L contains the 8 bit low byte timer value SFR Definition 21 17 TMR3H Timer 3 High Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0x95 Bits 7 0 Ti
31. Crossbar A SYNCHRONIZER i X GND CPn I DT I Ds I 54 Port connection options vary with E package 32 pin or 48 pin E CPnFIE gt n CPnMD1 CPnMDO SILICON LABORATORIES Figure 1 10 Comparator0 Block Diagram Rev 0 5 29 C8051F340 1 2 3 4 5 6 7 2 Absolute Maximum Ratings Table 2 1 Absolute Maximum Ratings Parameter Conditions Min Typ Max Units Ambient temperature under bias 55 125 Storage Temperature 65 150 Voltage on any Port I O Pin or RST with 0 3 5 8 V respect to GND Voltage on Vpp with respect to GND 0 3 4 2 V Maximum Total current through Vpp and 500 mA GND Maximum output current sunk by RST or any 100 mA Port pin Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability 30 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 3 Global DC Electrical Characteristics Table 3 1 Global DC Electrical Characteristics 40 to 85 25 MHz System Clock unless otherwise specified ture Range
32. packet is successfully transferred to the host 2 Software writes 1 to the FLUSH bit EINCSRL 3 when the target FIFO is not empty 3 Hardware generates a STALL condition 16 12 1 Endpoints1 3 IN Interrupt or Bulk Mode When the ISO bit EINCSRH 6 0 the target endpoint operates in Bulk or Interrupt Mode Once an end point has been configured to operate in Bulk Interrupt IN mode typically following an Endpointo SET INTERFACE command firmware should load an IN packet into the endpoint IN FIFO and set the INPRDY bit EINCSRL 0 Upon reception of an IN token hardware will transmit the data clear the INPRDY bit and generate an interrupt 184 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Writing 1 to INPRDY without writing any data to the endpoint FIFO will cause a zero length packet to be transmitted upon reception of the next IN token A Bulk or Interrupt pipe can be shut down or Halted by writing 1 to the SDSTL bit EINCSRL 4 While SDSTL 1 hardware will respond to all IN requests with a STALL condition Each time hardware gener ates a STALL condition an interrupt will be generated and the STSTL bit EINCSRL 5 set to 1 The STSTL bit must be reset to 0 by firmware Hardware will automatically reset INPRDY to 0 when a packet slot is open in the endpoint FIFO Note that if double buffering is enabled for the target endpoint it is possible for firmware to load two
33. 3 0 V Bias Generators ADC Bias Generator BIASE 4 100 Reference Bias Generator 40 58 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 7 Comparators C8051F340 1 2 3 4 5 6 7 devices include two on chip programmable voltage Comparators A block dia gram of the comparators is shown in Figure 7 1 where n is the comparator number 0 or 1 The two Comparators operate identically with the following exceptions 1 Their input selections differ and 2 ComparatorO can be used as a reset source For input selection details refer to SFR Definition 7 2 and SFR Definition 7 5 Each Comparator offers programmable response time and hysteresis an analog input multiplexer and two outputs that are optionally available at the Port pins a synchronous latched output CPO CP1 or an asynchronous raw output CP1A The asynchronous signal is available even when the system clock is not active This allows the Comparators to operate and generate an output with the device in STOP mode When assigned to a Port pin the Comparator outputs may be configured as open drain or push pull see Section 15 2 Port I O Initialization on page 151 ComparatorO may also be used as a reset source see Section 11 5 Comparator0 Reset on page 104 The Comparator0 inputs are selected in the CPTOMX register SFR Definition 7 2 The 1 bits select the ComparatorO p
34. Bytes in Flash memory can be written one byte at a time or in groups of two The FLBWE bit in register PFEOCN SFR Definition 10 1 controls whether a single byte or a block of two bytes is written to Flash during a write operation When FLBWE is cleared to 0 the Flash will be written one byte at a time When FLBWE is set to 1 the Flash will be written in two byte blocks Block writes are performed in the same amount of time as single byte writes which can save time when storing large amounts of data to Flash memory During a single byte write to Flash bytes are written individually and a Flash write will be per formed after each MOVX write instruction The recommended procedure for writing Flash in single bytes is Step 1 Disable interrupts Step 2 Clear the FLBWE bit register PFEOCN to select single byte write mode Step 3 Set the PSWE bit register PSCTL Step 4 Clear the PSEE bit register PSCTL Step 5 Write the first key code to FLKEY OxA5 Step 6 Write the second key code to FLKEY OxF1 Step 7 Using the MOVX instruction write a single data byte to the desired location within the 512 byte sector Step 8 Clear the PSWE bit Step 9 Re enable interrupts Steps 5 7 must be repeated for each byte to be written For block Flash writes the Flash write procedure is only performed after the last byte of each block is writ ten with the MOVX write instruction A Flash write block is two bytes long from even addresses to
35. Notes on Registers Operands and Addressing Modes Rn Register RO R7 of the currently selected register bank Ri Data RAM location addressed indirectly through RO or R1 rel 8 bit signed two s complement offset relative to the first byte of the following instruction Used by SJMP and all conditional jumps direct 8 bit internal data location s address This could be a direct access Data RAM location 0x00 0x7F or an SFR 0x80 0xFF data 8 bit constant data16 16 bit constant bit Direct accessed bit in Data RAM or SFR addr11 11 bit destination address used by ACALL and AJMP The destination must be within the same 2K byte page of program memory as the first byte of the following instruction addr16 16 bit destination address used by LCALL and LJMP The destination may be anywhere within the 8K byte program memory space There is one unused opcode 0xA5 that performs the same function as NOP All mnemonics copyrighted Intel Corporation 1980 78 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 9 2 Memory Organization The memory organization of the CIP 51 System Controller is similar to that of a standard 8051 There are two separate memory spaces program memory and data memory Program and data memory share the same address space but are accessed via different instruction types The CIP 51 memory organization is shown in Figure 9 2 PROGRAM DATA MEMORY DATA MEMO
36. Setting the TRO bit TCON 4 enables the timer when either GATEO TMOD 3 is logic 0 or the input signal INTO is active as defined by bit INOPL in register INTO1CF see SFR Definition 9 13 Setting GATEO to 1 allows the timer to be controlled by the external input signal INTO see Section 9 3 5 Interrupt Register Descriptions on page 89 facilitating pulse width measurements TRO GATEO INTO Counter Timer 0 X X Disabled 1 0 X Enabled 1 1 0 Disabled 1 1 1 Enabled X Don t Care Setting TRO does not force the timer to reset The timer registers should be loaded with the desired initial value before the timer is enabled TL1 and TH1 form the 13 bit register for Timer 1 in the same manner as described above for TLO and THO Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0 The input signal INT1 is used with Timer 1 the INT1 polarity is defined by bit INTPL in register INTO1CF see SFR Definition 9 13 INTO1CF T 3 M 1 1 111 0 0 0 0 H P S S S P S S s L L L L L LIE IL 2 1 o 21110 Pre scaled Clock 0 Y 0 SYSCLK 1 TI a1 ty 1 To TED TLO THO 9 Interrupt 1 X TRO DD 5 bits 8 bits TL Y gt Crossbar TCON
37. 14 Oscillators on page 135 for more details on internal oscillator configuration including the Suspend mode feature of the internal oscillator USBO exits Suspend mode when any of the following occur 1 Resume signaling is detected or gener ated 2 Reset signaling is detected or 3 a device or USB reset occurs If suspended the internal oscil lator will exit Suspend mode upon any of the above listed events Resume Signaling USBO will exit Suspend mode if Resume signaling is detected on the bus A Resume interrupt will be generated upon detection if enabled RESINTE 1 Software may force a Remote Wakeup by writing 1 to the RESUME bit POWER 2 When forcing a Remote Wakeup software should write RESUME 0 to end Resume signaling 10 15 ms after the Remote Wakeup is initiated RESUME 1 ISO Update When software writes 1 to the ISOUP bit POWER 7 the ISO Update function is enabled With ISO Update enabled new packets written to an ISO IN endpoint will not be transmitted until a new Start Of Frame SOF is received If the ISO IN endpoint receives an IN token before a SOF USBO will transmit a zero length packet When ISOUP 1 ISO Update is enabled for all ISO endpoints USB Enable USBO is disabled following a Power On Reset POR USBO is enabled by clearing the USBINH bit POWER 4 Once written to 0 the USBINH can only be set to 1 by one of the following 1 a Power On Reset
38. 6 optional Lock the WDT prevent WDT disable until the next system reset by setting the WDLCK bit to 1 The PCA clock source and Idle mode select cannot be changed while the WDT is enabled The watchdog timer is enabled by setting the WDTE or WDLCK bits in the PCAOMD register When WDLCK is set the WDT cannot be disabled until the next system reset If WDLCK is not set the WDT is disabled by clearing the WDTE bit The WDT is enabled following any reset The PCAO counter clock defaults to the system clock divided by 12 PCAOL defaults to 0x00 and PCAOCPLA defaults to 0x00 Using Equation 22 4 this results in a WDT timeout interval of 256 PCA clocks Table 22 3 lists some example timeout intervals for typical system clocks Table 22 3 Watchdog Timer Timeout Intervals System Clock Hz PCAOCPL4 Timeout Interval ms 12 000 000 255 65 5 12 000 000 128 33 0 12 000 000 32 8 4 24 000 000 255 32 8 24 000 000 128 16 5 24 000 000 32 4 2 1 500 000 255 524 3 1 500 000 128 264 2 1 500 000 32 67 6 32 768 255 24 000 32 768 128 12 093 75 32 768 32 3 093 75 Notes 1 Assumes SYSCLK 12 as the PCA clock source and a PCAOL value of 0x00 at the update time 2 System Clock reset frequency s Rev 0 5 273 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 22 4 Register Descriptions for PCA Following are detailed descriptions of the special function registers related
39. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0xB9 Bit7 MULEN Clock Multiplier Enable 0 Clock Multiplier disabled 1 Clock Multiplier enabled Bit6 MULINIT Clock Multiplier Initialize This bit should be a 0 when the Clock Multiplier is enabled Once enabled writing a 1 to this bit will initialize the Clock Multiplier The MULRDY bit reads 1 when the Clock Multiplier is stabilized Bit5 MULRDY Clock Multiplier Ready This read only bit indicates the status of the Clock Multiplier 0 Clock Multiplier not ready 1 Clock Multiplier ready locked Bits4 2 Unused Read 000b Write don t care Bits1 0 MULSEL Clock Multiplier Input Select These bits select the clock supplied to the Clock Multiplier MULSEL Selected Clock 00 Internal Oscillator 01 External Oscillator 10 External Oscillator 2 11 RESERVED 142 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 14 5 System and USB Clock Selection The internal oscillator requires little start up time and may be selected as the system or USB clock immedi ately following the OSCICN write that enables the internal oscillator External crystals and ceramic resona tors typically require a start up time before they are settled and ready for use The Crystal Valid Flag XTLVLD in register OSCXCN is set to 1 by hardware when the external oscillator is settled To avoid reading a false XTLVLD in crysta
40. FOSE Flash One shot Enable This bit enables the Flash read one shot When the Flash one shot disabled the Flash sense amps are enabled for a full clock cycle during Flash reads At system clock freguen cies below 10 MHz disabling the Flash one shot will increase system power consumption 0 Flash one shot disabled 1 Flash one shot enabled RESERVED Read 00b Must Write 00b FLRT FLASH Read Time This bit should be programmed to the smallest allowed value according to the system clock speed 0 SYSCLK 25 MHz 1 SYSCLK lt 48 MHz Bits3 0 RESERVED Read 0000b Must Write 0000b e Rev 0 5 115 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 NOTES 116 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 13 External Data Memory Interface and On Chip XRAM 4k Bytes C8051F340 2 4 6 or 2k Bytes C8051F341 3 5 7 of RAM are included on chip and mapped into the external data memory space XRAM The 1k Bytes of USB FIFO space can also be mapped into XRAM address space for additional general purpose data storage Additionally an External Memory Inter face EMIF is available on the C8051F340 1 4 5 devices which can be used to access off chip data mem ories and memory mapped devices connected to the GPIO ports The external memory space may be accessed using the external move instruction MOVX and the data pointer DPTR or using the MOVX indirect addressing mode using RO or R1 If the MOVX ins
41. Multiplier Oscillator Clock Low Freq Recover Oscillator z y Analog Peripherals Y VREF lt USB Peripheral VDD vaer 0 D 2 Comparators x Full Low Controller Speed 10 bit AINO AIN20 i 200 VBUS Transceiver 4 KB RAM ABO SPs Z Low Frequency Oscillator option not available on C8051F346 7 Figure 1 2 C8051F342 3 6 7 Block Diagram 20 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 1 1 CIP 51 Microcontroller Core 1 1 1 Fully 8051 Compatible The C8051F340 1 2 3 4 5 6 7 family utilizes Silicon Labs proprietary CIP 51 microcontroller core The CIP 51 is fully compatible with the MCS 51 instruction set standard 803x 805x assemblers and compil ers can be used to develop software The CIP 51 core offers all the peripherals included with a standard 8052 including four 16 bit counter timers two full duplex UARTs with extended baud rate configuration an enhanced SPI port up to 4352 Bytes of on chip RAM 128 byte Special Function Register SFR address space and up to 40 I O pins 1 1 2 Improved Throughput The CIP 51 employs a pipelined architecture that greatly increases its instruction throughput over the stan dard 8051 architecture In a standard 8051 all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute with a maximum system clock of 12 to 24 MHz By contrast the CIP 51 core exe cutes 70 of its instructions in one or two system clock cyc
42. Reset Value Variable Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito This read only register returns the 8 bit revision ID C2 Register Definition 23 4 FPCTL C2 Flash Programming Control Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bits7 0 FPCTL Flash Programming Control Register This register is used to enable Flash programming via the C2 interface To enable C2 Flash programming the following codes must be written in order 0x02 0x01 Note that once C2 Flash programming is enabled a system reset must be issued to resume normal operation C2 Register Definition 23 5 FPDAT C2 Flash Programming Data Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bits7 0 FPDAT C2 Flash Programming Data Register This register is used to pass Flash commands addresses and data during C2 Flash accesses Valid commands are listed below Code Command 0x06 Flash Block Read 0x07 Flash Block Write 0x08 Flash Page Erase 0x03 Device Erase 280 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 23 2 C2 Pin Sharing The C2 protocol allows the C2 pins to be shared with user functions so that in system debugging and Flash programming functions may be performed This is possible because C2 communication is typically performed when the device is
43. SBREET I lt EIE U li ORB cam TX Holding SYSCLK Pre Scaler ac JA dhIOA Register Timer 16 bit EN 1 4 12 48 Write to SBUF1 T Es SBUF1 p SE Control Status k Read of SBUF1 5 ee SCONT RX FIFO 8 po l 3 Deep SBCON1 P Logic lt d Interrupt Figure 19 1 UART1 Block Diagram s Rev 0 5 219 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 19 1 Baud Rate Generator The 1 baud rate is generated by a dedicated 16 bit timer which runs from the controller s core clock SYSCLK and has prescaler options of 1 4 12 or 48 The timer and prescaler options combined allow for a wide selection of baud rates over many SYSCLK frequencies The baud rate generator is configured using three registers SBCON1 SBRLH1 and SBRLL1 The UART1 Baud Rate Generator Control Register SBCON1 SFR Definition 19 4 enables or disables the baud rate generator and selects the prescaler value for the timer The baud rate generator must be enabled for UART1 to function Registers SBRLH1 and SBRLL1 contain 16 bit reload value for the dedi cated 16 bit timer The internal timer counts up from the reload value on every clock tick On timer over flows OxFFFF to 0x0000 the timer is reloaded For reliable UART operation it is recommended that the UART baud rate is not configured for baud rates faster than SYSCLK 16 baud rate for UART1 is defined in Equation 1
44. 12 Flash Mem ory on page 109 for further details Table 9 1 CIP 51 Instruction Set Summary Clock Mnemonic Description Bytes Cycles Arithmetic Operations ADD A Rn Add register to A 1 1 ADD A direct Add direct byte to A 2 2 ADD A Ri Add indirect RAM to A 1 2 ADD A data Add immediate to A 2 2 ADDC A Rn Add register to A with carry 1 1 ADDC A direct Add direct byte to A with carry 2 2 ADDC A Ri Add indirect RAM to A with carry 1 2 ADDC A data Add immediate to A with carry 2 2 SUBB A Rn Subtract register from A with borrow 1 1 SUBB A direct Subtract direct byte from A with borrow 2 2 SUBB Ri Subtract indirect RAM from A with borrow 1 2 SUBB A data Subtract immediate from A with borrow 2 2 INC A Increment A 1 1 INC Rn Increment register 1 1 INC direct Increment direct byte 2 2 INC Increment indirect RAM 1 2 DECA Decrement A 1 1 DEC Hn Decrement register 1 1 DEC direct Decrement direct byte 2 2 DEC Decrement indirect RAM 1 2 INC DPTR Increment Data Pointer 1 1 MUL AB Multiply A and B 1 4 DIV AB Divide A by B 1 8 DAA Decimal adjust A 1 1 Logical Operations ANL A Rn AND Register to A 1 1 ANL A direct AND direct byte to A 2 2 ANL A Ri AND indirect RAM to A 1 2 ANL A data AND immediate to A 2 2 ANL direct A AND A to direct byte 2 2 ANL direct data AND immediate to direct byte 3 3 OR
45. 13 5 2 Non multiplexed Configuration In Non multiplexed mode the Data Bus and the Address Bus pins are not shared An example of a Non multiplexed Configuration is shown in Figure 13 3 See Section 13 7 1 Non multiplexed Mode on page 127 for more information about Non multiplexed operation Figure 13 3 Non multiplexed Configuration Example 13 6 Memory Mode Selection The external data memory space can be configured in one of four modes shown in Figure 13 4 based on the EMIF Mode bits in the EMIOCF register SFR Definition 13 2 These modes are summarized below More information about the different modes can be found in Section 13 7 Timing on page 125 EMIOCF 3 2 00 EMIOCF 3 2 01 EMIOCF 3 2 10 EMIOCF 3 2 11 OxFFFF OxFFFF OxFFFF OxFFFF On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM On Chip XRAM 0x0000 0x0000 0x0000 0x0000 Figure 13 4 EMIF Operating Modes s Rev 0 5 123 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 13 6 1 Internal XRAM Only When EMIOCF 3 2 are set to 00 all MOVX instructions will target the internal XRAM space on the device Memory accesses to addresses beyond the populated space will wrap on 2k or 4k boundaries depending on the RAM available on the device As an example the addresses 0x1000 and 0x2000 both evaluate to address 0x0000 in on chip XRAM space e 8 bit MOVX operations use the contents of EMIOC
46. 21 Timers on page 243 1 THighMin TtowMin m f ClockSourceOverflow Equation 17 1 Minimum SCL High and Low Times The selected clock source should be configured to establish the minimum SCL High and Low times as per Equation 17 1 When the interface is operating as a master and SCL is not driven or extended by any other devices on the bus the typical SMBus bit rate is approximated by Equation 17 2 ClockSourceOverflow 3 Equation 17 2 Typical SMBus Bit Rate BitRate 198 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Figure 17 4 shows the typical SCL generation described by Equation 17 2 Notice that is typically twice as large as ow The actual SCL output may vary due to other devices on the bus SCL may be extended low by slower slave devices or driven low by contending master devices The bit rate when operating as a master will never exceed the limits defined by equation Equation 17 1 Timer Source Overflows SCL T SCL High Timeout Low High Figure 17 4 Typical SMBus SCL Generation Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line The minimum SDA setup time defines the absolute minimum time that SDA is stable before SCL transitions from low to high The minimum SDA hold time defines the ab
47. ADOWINT ADOWINT 1 not affected VREF 0x8000 Figure 5 9 ADC Window Compare Example Left Justified Differential Data e Rev 0 5 55 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 5 1 ADCO Electrical Characteristics Vpp 3 0 V VREF 2 40 V 40 to 85 unless otherwise specified Parameter Conditions Min Typ Max Units DC Accuracy Resolution 10 bits Integral Nonlinearity 0 5 1 LSB Differential Nonlinearity Guaranteed Monotonic 0 5 1 LSB Offset Error 0 LSB Full Scale Error 1 LSB Offset Temperature Coefficient 10 ppm C Dynamic Performance 10 kHz sine wave Single ended input 1 dB below Full Scale 200 ksps Signal to Noise Plus Distortion 51 52 5 dB Total Harmonic Distortion Up to the 5 harmonic 67 dB Spurious Free Dynamic Range 78 dB Conversion Rate SAR Conversion Clock 3 MHz Conversion Time in SAR Clocks 10 clocks Track Hold Acquisition Time 300 ms Throughput Rate 200 ksps Analog Inputs ADC Input Voltage Range Single Ended AIN GND 0 VREF V Differential AIN AIN VREF VREF V COND Pin volage witndespect Single Ended or Differential 0 V Input Capacitance 5 pF Temperature Sensor Linearity 0 1 Slope mV C Offset Temp 0 C Ros mV Power Specifications pp SUP Operating Mode 200 ksps 400 900 Power Supply Rejection 0 3 mV V
48. Bits6 5 S1PT 1 0 Parity Type 00 Odd 01 Even 10 Mark 11 Space Bit4 PE1 Parity Enable This bit activates hardware parity generation and checking The parity type is selected by bits S1PT1 0 when parity is enabled 0 Hardware parity is disabled 1 Hardware parity is enabled Bits3 2 S1DL 1 0 Data Length 00 5 bit data 01 6 bit data 10 7 bit data 11 8 bit data Bit1 XBE1 Extra Bit Enable When enabled the value of TBX1 will be appended to the data field 0 Extra Bit Disabled 1 Extra Bit Enabled Bito SBL1 Stop Bit Length 0 Short Stop bit is active for one bit time 1 Long Stop bit is active for two bit times data length 6 7 or 8 bits or 1 5 bit times data length 5 bits s Rev 0 5 225 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 19 3 SBUF1 UART1 Data Buffer R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address OxD3 Bits7 0 SBUF1 7 0 Serial Data Buffer Bits 7 0 MSB LSB This SFR is used to both send data from the UART and to read received data from the UART1 receive FIFO Write Writing a byte to SBUF1 initiates the transmission When data is written to SBUF1 it first goes to the Transmit Holding Register where it is held for serial transmission When the transmit shift register is available data is transferred into the shift register and SBUF1 may be written again Read Reading SBUF1 retr
49. CKPHA 1 235 Figure 20 8 SPI Master Timing CKPHA 0 239 Figure 20 9 SPI Master Timing 1 239 Rev 0 5 11 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Figure 20 10 SPI Slave Timing 0 240 Figure 20 11 SPI Slave Timing CKPHA 1 240 Table 20 1 SPI Slave Timing Parameters 40442221 241 21 Timers Figure 21 1 TO Mode 0 Block 244 Figure 21 2 TO Mode 2 Block 1 245 Figure 21 3 TO Mode Block 246 Figure 21 4 Timer 2 16 Bit Mode Block Diagram 251 Figure 21 5 Timer 2 8 Bit Mode Block Diagram 252 Figure 21 6 Timer 2 Capture Mode T2SPLIT 0 253 Figure 21 7 Timer 2 Capture Mode T2SPLIT 1 254 Figure 21 8 Timer 3 16 Bit Mode Block Diagram 257 Figure 21 9 Timer 8 Bit Mode Block Diagram 258 Figure 21 10 Timer Capture Mode T3SPLIT 0 22222 222 259 Figure 21 11 Timer Capture Mode T3SPLIT 1
50. Enable Timer 0 Interrupt This bit sets the masking of the Timer 0 interrupt 0 Disable all Timer 0 interrupt 1 Enable interrupt requests generated by the TFO flag Bito Enable External Interrupt 0 This bit sets the masking of External Interrupt O 0 Disable external interrupt 0 1 Enable interrupt requests generated by the INTO input 90 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 R W SFR Definition 9 8 IP Interrupt Priority R W R W R W R W R W R W R W Reset Value PSPIO PT2 50 PT1 PX1 PTO PXO 10000000 Bit7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address bit addressable 0xB8 UNUSED Read 1 Write don t care PSPIO Serial Peripheral Interface SP10 Interrupt Priority Control This bit sets the priority of the SPIO interrupt 0 SPIO interrupt set to low priority level 1 SPIO interrupt set to high priority level PT2 Timer 2 Interrupt Priority Control This bit sets the priority of the Timer 2 interrupt 0 Timer 2 interrupt set to low priority level 1 Timer 2 interrupts set to high priority level 50 UARTO Interrupt Priority Control This bit sets the priority of the UARTO interrupt 0 UARTO interrupt set to low priority level 1 UARTO interrupts set to high priority level PT1 Timer 1 Interrupt Priority Control This bit sets the
51. In most cases the output modes of all EMIF pins should be configured for push pull mode s Rev 0 5 119 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 13 1 EMIOCN External Memory Interface Control R W R W R W R W R W R W R W R W Reset Value PGSEL7 PGSEL6 PGSEL5 PGSEL4 PGSEL3 PGSEL2 PGSEL1 PGSELO 00000000 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address OxAA Bits7 0 PGSEL 7 0 XRAM Page Select Bits The XRAM Page Select Bits provide the high byte of the 16 bit external data memory address when using an 8 bit MOVX command effectively selecting a 256 byte page of RAM 0x00 0x0000 to OxOOFF 0x01 0x0100 to 0x01FF OxFE OxFEO0 to OxFEFF OxFF OxFFOO to OxFFFF 120 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 13 2 EMIOCF External Memory Configuration R W R W R W R W R W R W R W R W Reset Value USBFAE EMD2 EMD1 EMDO EALE1 EALEO 00000011 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0x85 Bit7 Unused Read Ob Write don t care Bit6 USBFAE USB FIFO Access Enable 0 USB FIFO RAM not available through MOVX instructions 1 USB FIFO RAM available using MOVX instructions The 1k of USB RAM will be mapped in XRAM space at addresses 0x0400 to 0x07FF The USB clock must be active to access this area with MOVX instructions Bit5 Unused Read Ob Write don t care Bit4 EMD2 EMIF
52. RETI will be the instruction immediately following the one that set the Idle Mode Select bit If Idle mode is terminated by an internal or external reset the CIP 51 performs a normal reset sequence and begins program execution at address 0x0000 If enabled the Watchdog Timer WDT will eventually cause an internal watchdog reset and thereby termi nate the Idle mode This feature protects the system from an unintended permanent shutdown in the event of an inadvertent write to the PCON register If this behavior is not desired the WDT may be disabled by software prior to entering the Idle mode if the WDT was initially configured to allow this operation This pro vides the opportunity for additional power savings allowing the system to remain in the Idle mode indefi nitely waiting for an external stimulus to wake up the system Refer to Section 11 6 PCA Watchdog Timer Reset on page 104 for more information on the use and configuration of the WDT 9 4 2 Stop Mode Setting the Stop Mode Select bit PCON 1 causes the CIP 51 to enter Stop mode as soon as the instruc tion that sets the bit completes execution In Stop mode the internal oscillator CPU and all digital peripher als are stopped the state of the external oscillator circuit is not affected Each analog peripheral including the external oscillator circuit may be shut down individually prior to entering Stop Mode Stop mode can only be terminated by an internal or external reset
53. SILICON LABORATORIES Rev 0 5 89 C8051F340 1 2 3 4 5 6 7 SFR Definition 9 7 IE Interrupt Enable R W R W R W R W R W R W R W R W Reset Value EA ESPIO ET2 ESO ET1 EX1 ETO EXO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit SFR Address bit addressable OxA8 Bit7 EA Enable All Interrupts This bit globally enables disables all interrupts It overrides the individual interrupt mask set tings 0 Disable all interrupt sources 1 Enable each interrupt according to its individual mask setting Bit6 ESPIO Enable Serial Peripheral Interface SPIO Interrupt This bit sets the masking of the SPIO interrupts 0 Disable all SPIO interrupts 1 Enable interrupt requests generated by SPIO Bit5 ET2 Enable Timer 2 Interrupt This bit sets the masking of the Timer 2 interrupt 0 Disable Timer 2 interrupt 1 Enable interrupt requests generated by the TF2L or TF2H flags Bit4 ESO Enable UARTO Interrupt This bit sets the masking of the UARTO interrupt 0 Disable UARTO interrupt 1 Enable UARTO interrupt Bit3 ET1 Enable Timer 1 Interrupt This bit sets the masking of the Timer 1 interrupt 0 Disable all Timer 1 interrupt 1 Enable interrupt requests generated by the TF1 flag Bit2 EX1 Enable External Interrupt 1 This bit sets the masking of External Interrupt 1 0 Disable external interrupt 1 1 Enable interrupt requests generated by the INT1 input Bit1 ETO
54. USBCLK Selected Clock 000 4x Clock Multiplier 001 Internal Oscillator 2 010 External Oscillator 011 External Oscillator 2 100 External Oscillator 3 101 External Oscillator 4 110 RESERVED 111 RESERVED Bit3 Unused Read 0b Write don t care Bits2 0 CLKSL2 0 System Clock SelectThese bits select the system clock source CLKSL Selected Clock 000 Internal Oscillator as determined by the IFCN bits in register OSCICN 001 External Oscillator 010 4x Clock Multiplier 2 011 4x Clock Multiplier 100 Low Frequency Oscillator 101 111 RESERVED Note This option is only available on 48 MHz devices 144 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 14 1 Oscillator Electrical Characteristics Vpp 2 7 to 3 6 V 40 to 85 unless otherwise specified Parameter Conditions Min Typ Max Units Internal High Frequency Oscillator Using Factory Calibrated Settings Oscillator Frequency IFCN 11b 11 82 12 00 12 18 MHz Oscillator Supply Current 24 C Vpp 3 0 V _ 685 _ UA from Vpp OSCICN 7 1 Internal Low Frequency Oscillator Using Factory Calibrated Settings Oscillator Frequency OSCLD 11b 72 80 99 kHz Oscillator Supply Current 24 C Vpp 3 0 V 70 As UA from Vpp OSCLCN 7 1 External USB Clock Requirements Full Speed Mode 47 88 48 48 12 USB Clock Frequency MHz Low Speed Mode 5 91 6 6 09
55. the completion of the next instruction 9 3 1 MCU Interrupt Sources and Vectors The MCU supports multiple interrupt sources Software can simulate an interrupt by setting any inter rupt pending flag to logic 1 If interrupts are enabled for the flag an interrupt request will be generated and the CPU will vector to the ISR address associated with the interrupt pending flag MCU interrupt sources associated vector addresses priority order and control bits are summarized in Table 9 4 on page 89 Refer to the datasheet section associated with a particular on chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt pending flag s 9 3 2 External Interrupts The INTO and INT1 external interrupt sources are configurable as active high or low edge or level sensi tive The INOPL INTO Polarity and IN1PL INT1 Polarity bits in the ITO1CF register select active high or active low the ITO and IT1 bits in TCON Section 21 1 Timer 0 and Timer 1 on page 243 select level or edge sensitive The following table lists the possible configurations s Rev 0 5 87 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 ITO INOPL INTO Interrupt IT1 INT1 Interrupt 1 0 Active low edge sensitive 1 0 Active low edge sensitive 1 1 Active high edge sensitive 1 1 Active high edge sensitive 0 0 Active low level sensitive 0 0 Active low level se
56. 011 ADCO conversion initiated on overflow of Timer 1 100 ADCO conversion initiated on rising edge of external CNVSTR 101 ADCO conversion initiated on overflow of Timer 3 11x Reserved When ADOTM 1 000 Tracking initiated on write of 1 to ADOBUSY and lasts 3 SAR clocks followed by conversion 001 Tracking initiated on overflow of Timer 0 and lasts 3 SAR clocks followed by conversion 010 Tracking initiated on overflow of Timer 2 and lasts 3 SAR clocks followed by conversion 011 Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks followed by conversion 100 ADCO tracks only when CNVSTR input is logic low conversion starts on rising CNVSTR edge 101 Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks followed by conversion 11x Reserved e Rev 0 5 51 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 5 4 Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADCO conversion results to user programmed limits and notifies the system when a desired condition is detected This is especially effective in an interrupt driven system saving code space and CPU bandwidth while delivering faster sys tem response times The window detector interrupt flag ADOWINT in register ADCOCN can also be used in polled mode The ADCO Greater Than ADCOGTH ADCOGTL and Less Than ADCOLTH ADCOLTL registers hold the comparison values The window detector flag ca
57. 1 R W R W R W R W R W R W R W PCP1 PCPO PADCO PWADCO PUSBO PSMBO Bit7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito Bite Bit5 Bit4 Bit3 Bit2 Bit Bito PT3 Timer 3 Interrupt Priority Control This bit sets the priority of the Timer 3 interrupt 0 Timer 3 interrupts set to low priority level 1 Timer 3 interrupts set to high priority level PCP1 Comparator1 CP 1 Interrupt Priority Control This bit sets the priority of the CP1 interrupt 0 CP1 interrupt set to low priority level 1 CP1 interrupt set to high priority level PCPO Interrupt Priority Control This bit sets the priority of the CPO interrupt 0 CPO interrupt set to low priority level 1 CPO interrupt set to high priority level PPCAO Programmable Counter Array PCAO Interrupt Priority Control This bit sets the priority of the PCAO interrupt 0 PCAO interrupt set to low priority level 1 PCAO interrupt set to high priority level PADCO ADCO Conversion Complete Interrupt Priority Control This bit sets the priority of the ADCO Conversion Complete interrupt 0 ADCO Conversion Complete interrupt set to low priority level 1 ADCO Conversion Complete interrupt set to high priority level PWADCO ADCO Window Comparator Interrupt Priority Control This bit sets the priority of the ADCO Window interrupt 0 ADCO Window interrupt set to low priority level 1 ADCO Window interru
58. 1 Source of last reset was a WDT timeout Bit2 MCDRSF Missing Clock Detector Flag 0 Read Source of last reset was not a Missing Clock Detector timeout Write Missing Clock Detector disabled 1 Read Source of last reset was a Missing Clock Detector timeout Write Missing Clock Detector enabled triggers a reset if a missing clock condition is detected Bit PORSF Power On Vpp Monitor Reset Flag This bit is set anytime a power on reset occurs Writing this bit selects deselects the Vpp monitor as a reset source Note writing 1 to this bit before the Vpp monitor is enabled and stabilized can cause a system reset See register VDMOCN SFR Definition 11 1 0 Read Last reset was not a power on or Vpp monitor reset Write Vpp monitor is not a reset source 1 Read Last reset was a power on or Vpp monitor reset all other reset flags indeterminate Write Vpp monitor is a reset source Bito PINRSF HW Pin Reset Flag 0 Source of last reset was not RST pin 1 Source of last reset was RST pin Note For bits that act as both reset source enables on a write and reset indicator flags on a read read modify write instructions read and modify the source enable only This applies to bits USBRSF CORSEF SWRSF MCDRSF PORSF 106 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 11 1 Reset Electrical Characteristics 40 to 85 unless otherwise specified
59. 6 Figure 13 10 Multiplexed 8 bit MOVX with Bank Select Timing 132 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 13 1 AC Parameters for External Memory Interface Parameter Description Min Max Units TAcs Address Control Setup Time 0 X TsySCLK ns TACW Address Control Pulse Width 1 16 Ins TACH Address Control Hold Time 0 3 x ns TALEH Address Latch Enable High Time 1 X TsySCLK 4 X Tevsci k ns TALEL Address Latch Enable Low Time 1X 4 X ns Twos Write Data Setup Time 1x Tsvscik 19 x TgySCLK ns TWDH Write Data Hold Time 0 X TsySCLK ns TRDS Read Data Setup Time 20 ns TRDH Read Data Hold Time 0 ns Note is equal to one period of the device system clock SYSCLK e Rev 0 5 133 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 NOTES 134 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 14 Oscillators C8051F340 1 2 3 4 5 6 7 devices include a programmable internal high frequency oscillator a program mable internal low frequency oscillator C8051F340 1 2 3 4 5 an external oscillator drive circuit and a 4x Clock Multiplier The internal high frequency and low frequency oscillators can be enabled disabled and adjusted using the special function registers as shown in Figure 14 1 The system clock SYSCLK can be derived from either of
60. 7 18 1 Enhanced Baud Rate Generation The UARTO baud rate is generated by Timer 1 in 8 bit auto reload mode The TX clock is generated by TL1 the RX clock is generated by a copy of TL1 shown as RX Timer in Figure 18 2 which is not user accessible Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates The RX Timer runs when Timer 1 is enabled and uses the same reload value TH1 However an RX Timer reload is forced when a START condition is detected on the RX pin This allows a receive to begin any time a START is detected independent of the TX Timer state LEE NN TL1 EUM 2 p TXClock TH1 5 4 RX Timer Lid 2 RX Clock Figure 18 2 UARTO Baud Rate Logic Timer 1 should be configured for Mode 2 8 bit auto reload see Section 21 1 3 Mode 2 8 bit Counter Timer with Auto Reload on page 245 The Timer 1 reload value should be set so that overflows will occur at two times the desired UART baud rate frequency Note that Timer 1 may be clocked by one of six sources SYSCLK SYSCLK 4 SYSCLK 12 SYSCLK 48 the external oscillator clock 8 or an exter nal input T1 For any given Timer 1 clock source the UARTO baud rate is determined by Equation 18 1 1 B R xr UartBaudRate 256 TIH 2 Equation 18 1 UARTO Baud Rate Where Tic k is the frequency of t
61. 7 1 0 respectively Port pins configured as analog inputs have their weak pull up digital driver and digital receiver disabled 0 Corresponding P1 n pin is configured as an analog input 1 Corresponding P1 n pin is not configured as an analog input SFR Definition 15 10 PIMDOUT Port1 Output Mode R W R W R W R W R W R W Reset Value 00000000 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address OxA5 Bits7 0 Output Configuration Bits for P1 7 P1 0 respectively ignored if corresponding bit in regis ter PIMDIN is logic 0 0 Corresponding P1 n Output is open drain 1 Corresponding P1 n Output is push pull 156 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 15 11 P1SKIP Port1 Skip R W R W Reset Value 00000000 Bit Bito SFR Address 0xD5 Bits7 0 P1SKIP 7 0 Porti Crossbar Skip Enable Bits These bits select Port pins to be skipped by the Crossbar Decoder Port pins used as ana log inputs for ADC or Comparator or used as special functions VREF input external oscil lator circuit CNVSTR input should be skipped by the Crossbar 0 Corresponding P1 n pin is not skipped by the Crossbar 1 Corresponding P1 n pin is skipped by the Crossbar SFR Definition 15 12 P2 Port2 Latch R W R W R W R W R W R W Reset Value P2 5 P2 4 P2 3 P2 2 P2 1 P2 0 11111111 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address bit addressable
62. 7 31 11 D I O or Port 2 7 A In P3 0 30 D I O or Port 3 0 See Section 15 for a complete description of Port Aln 3 P3 1 29 D I O or Port 3 1 A In P3 2 28 D I O or Port 3 2 A In 34 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 4 1 Pin Definitions for the C8051F340 1 2 3 4 5 6 7 Continued Pin Numbers Type Description 48 32 27 D I O or Port 3 3 A In P3 4 26 D I O or Port 3 4 A In P3 5 25 D I O or Port 3 5 A In P3 6 24 D I O or Port 3 6 A In P3 7 23 D I O or Port 3 7 A In P4 0 22 D I O or Port 4 0 See Section 15 for a complete description of Port Aln 4 P4 1 21 D I O or Port 4 1 A In P4 2 20 D I O or Port 4 2 A In P4 3 19 D I O or Port 4 3 A In P4 4 18 D or Port 4 4 A In P4 5 17 D I O or Port 4 5 A In P4 6 16 D I O or Port 4 6 A In P4 7 15 D I O or Port 4 7 A In SILICON LABORATORIES Rev 0 5 35 C8051F340 1 2 3 4 5 6 7 c T n 2 2 2 3 2 4 P25 P2 6 C8051F340 1 4 5 P2 7 Top View P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 X N O Figure 4 1 TQFP 48 Pinout Diagram Top View 36 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7
63. ADCOCN slo al lo 3 Elal le 555565 21215 22 8588555 lt lt lt lt lt lt lt lt 2 2 lt lt lt pm 1 up X Port I O Pins VDD Sai 000 ADOBUSY W i Conversion 001 Timer 0 Overflow VDD Y 010 Timer 2 Overflow 011 Timer 1 Overflow 100 CNVSTR Input Temp 101 Timer 3 Overflow Sensor Vv Port I O Pins VREF ADOWINT GND 1 Window n Compare S x ziziziziz Logic 2 2 2 2 2 2 2 2 3 ADCOLTH 15 5 5 5 a alalala a lt lt lt lt lt lt lt lt lt lt lt 21 Selections on 32 pin package AMXON ADCOCF ADCOGTH ADCOGTL 20 Selections on 48 pin package Figure 5 1 ADCO Functional Block Diagram Rev 0 5 41 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 5 1 Analog Multiplexer AMUXO selects the positive and negative inputs to the ADC The positive input AIN can be connected to individual Port pins the on chip temperature sensor or the positive power supply Vpp The negative input AIN can be connected to individual Port pins VREF or GND When GND is selected as the neg ative input ADCO operates in Single ended Mode at all other times ADCO operates in Differential Mode The ADCO input channels are selected in the AMXOP and AMXON registers as described in SFR Definition 5 1 and SFR Definition 5 2 The conversion code format diffe
64. Crossbar Registers when XBARE 1 0 Logic Low Output 1 Logic High Output high impedance if corresponding POMDOUT n bit 0 Read Always reads 0 if selected as analog input in register POMDIN Directly reads Port pin when configured as digital input 0 PO n pin is logic low 1 PO n pin is logic high SFR Definition 15 5 POMDIN Porto Input Mode R W R W R W R W R W R W Reset Value 11111111 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address OxF1 Bits7 0 Analog Input Configuration Bits for PO 7 P0 0 respectively Port pins configured as analog inputs have their weak pull up digital driver and digital receiver disabled 0 Corresponding PO n pin is configured as an analog input 1 Corresponding PO n pin is not configured as an analog input 154 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 15 6 POMDOUT Porto Output Mode R W R W R W R W R W R W R W Reset Value 00000000 Bit6 Bit5 Bit4 Bit2 Bit Bito SFR Address Ox A4 Bits7 0 Output Configuration Bits for PO 7 P0 0 respectively ignored if corresponding bit in regis ter POMDIN is logic O 0 Corresponding PO n Output is open drain 1 Corresponding PO n Output is push pull Note When SDA and SCL appear on any of the Port I O each are open drain regardless of the value of POMDOUT SFR Definition 15 7 POSKIP PortO Ski
65. Each capture compare module can be configured to operate in one of six modes Edge Triggered Capture Software Timer High Speed Output 8 or 16 bit Pulse Width Modulator or Frequency Output Additionally Capture Compare Module 4 offers watchdog timer WDT capabilities Following a system reset Module 4 is configured and enabled WDT mode The PCA Capture Compare Module and External Clock Input may be routed to Port I O via the Digital Crossbar SYSCLK 12 SYSOLK 4 Timer 0 Overflow b 16 Bit Counter Timer SYSCLK External Clock 8 Capture Compare Capture Compare Capture Compare Capture Compare Capture Compare Module 0 Module 1 Module 2 Module 3 Module 4 WDT m o Q Q Q o m m m x N Az Crossbar a sen ete ere ee Port I O Figure 1 8 PCA Block Diagram 0 5 27 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 1 9 10 Bit Analog to Digital Converter The C8051F340 1 2 3 4 5 6 7 devices include an on chip 10 bit SAR ADC with a true differential input mul tiplexer With a maximum throughput of 200 ksps the ADC offers true 10 bit linearity with an INL of 1LSB The ADC system includes a configurable analog multiplexer
66. Flag MODF SPIOCN 5 is set to logic 1 when SPIO is configured as a master and for multi master mode and the NSS pin is pulled low When a Mode Fault occurs the MSTEN and SPIEN bits in SPIOCN are set to logic 0 to disable SPIO and allow another master device to access the bus 4 The Receive Overrun Flag RXOVRN SPIOCN 4 is set to logic 1 when configured as a slave and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer The new byte is not transferred to the receive buffer allowing the previously received data byte to be read The data byte which caused the overrun is lost e Rev 0 5 233 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 20 5 Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPIO Configuration Register SPIOCFG The CKPHA bit SPIOCFG 5 selects one of two clock phases edge used to latch the data The CKPOL bit SPIOCFG 4 selects between an active high or active low clock Both master and slave devices must be configured to use the same clock phase and polarity SPIO should be disabled by clearing the SPIEN bit SPIOCN O when changing the clock phase or polarity The clock and data line relationships for master mode are shown in Figure 20 5 For slave mode the clock and data relationships are shown in Figure 20 6 and Figure 20 7 The SPIO Clock Rate Register SPIOCKR as shown in SFR Definiti
67. Mates etr th AM tA 281 Contact Information P M 282 Rev 0 5 7 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 NOTES 8 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 List of Figures and Tables 1 System Overview Table 1 1 Product Selection ete pee ettet ba teet Figure 1 1 C8051F340 1 4 5 Block Figure 1 2 C8051F342 3 6 7 Block Figure 1 3 On Chip Clock and Reset re o e o dete eeiam ene Figure 1 4 On Chip Memory Map for 64kB Devices C8051F340 2 4 6 Figure 1 5 USB Controller Block Figure 1 6 Digital Crossbar Diagram oni anne Figure 1 7 PCA Block Didgf alti seres Figure 1 8 PGA Block DIagralnr iode e oio E P ED a od ERE Figure 1 9 10 Bit ADC Block 2224000 00 Figure 1 10 ComparatorO Block 0 2 Absolute Maximum Ratings Table 2 1 Absolute Maximum 3 Global DC Electrical Characteristics Table 3 1 Global DC Electrical Characteristics Table 3 2 Index to Electrical Characteristics Tables 4 Pinout and Package De
68. Mode Interconnect Diagram Rev 0 5 215 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 18 1 SCONO Serial Port 0 Control R W R R W R W R W R W R W R W Reset Value SOMODE MCEO RENO TB80 RB80 TIO RIO 01000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito Ad SFR Address 0x98 Bit7 SOMODE Serial Port 0 Operation Mode This bit selects the UARTO Operation Mode 0 8 bit UART with Variable Baud Rate 1 9 bit UART with Variable Baud Rate Bit6 UNUSED Read 1b Write don t care Bit5 MCEO Multiprocessor Communication Enable The function of this bit is dependent on the Serial Port 0 Operation Mode SOMODE 0 Checks for valid stop bit 0 Logic level of stop bit is ignored 1 RIO will only be activated if stop bit is logic level 1 SOMODE 1 Multiprocessor Communications Enable 0 Logic level of ninth bit is ignored 1 RIO is set and an interrupt is generated only when the ninth bit is logic 1 Bit4 RENO Receive Enable This bit enables disables the UART receiver 0 UARTO reception disabled 1 UARTO reception enabled Bit3 TB80 Ninth Transmission Bit The logic level of this bit will be assigned to the ninth transmission bit in 9 bit UART Mode It is not used in 8 bit UART Mode Set or cleared by software as required Bit2 RB80 Ninth Receive Bit 80 is assigned the value of the STOP bit in Mode 0 it is assigned the value of the 9th data bit in Mode 1 B
69. Mode without Bank 124 13 6 3 Split Mode with Bank o eer lubit 125 19 54 isi NE 125 DONIS Pr EET 125 13 7 1 Non multiplexed Mode ui irte e eftt 127 13 7 2 Multiplexed els eee AL dc LA 130 4 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 WA M 135 14 1 Programmable Internal High Frequency H F Oscillator 136 14 1 1 Internal H F Oscillator Suspend 136 14 2 Programmable Internal Low Frequency L F Oscillator 137 14 2 1 Calibrating the Internal L F 244 4 4 8 1001 137 14 3 External Oscillator Drive Circuit euentu tne 139 14 3 1 Clocking Timers Directly Through the External Oscillator 139 14 3 2 External Crystal Example sse 139 14 3 3 External Example uer md oret t a 140 14 3 4 External Capacitor Example ree rc eden 140 14 4 4x Clock epe AN 142 14 5 System and USB Clock Selection cesses 143 14 5 1 System Glock Selection aic buses rcr a 143 14 5 2 USB Clock Selection beet btc ebat 143 15 Port Input OUE T ai anxii K
70. Move immediate to direct byte MOV Ri A Move A to indirect RAM MOV direct Move direct byte to indirect RAM MOV Ri data Move immediate to indirect RAM MOV DPTR data16 Load DPTR with 16 bit constant MOVC A A DPTR Move code byte relative DPTR to A MOVC A A PC Move code byte relative PC to A MOVX A Ri Move external data 8 bit address to A MOVX Ri A Move A to external data 8 bit address MOVX A DPTR Move external data 16 bit address to A MOVX DPTR Move A to external data 16 bit address N DOP O NI N GD N CO NI NI NI N N N NI NI W CO W PY NI N I NI PO PO PO NINI N PUSH direct Push direct byte onto stack POP direct Pop direct byte from stack XCH A Rn Exchange Register with A XCH A direct Exchange direct byte with A 76 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 9 1 CIP 51 Instruction Set Summary Continued m Clock Mnemonic Description Bytes Cycles XCH A Ri Exchange indirect RAM with A 1 2 XCHD A Ri Exchange low nibble of indirect RAM with A 1 2 Boolean Manipulation CLRC Clear Carry 1 1 CLR bit Clear direct bit 2 2 SETBC Set Carry 1 1 SETB bit Set direc
71. Multiplex Mode Select 0 EMIF operates in multiplexed address data mode 1 EMIF operates in non multiplexed mode Separate address and data pins Bits3 2 EMD1 0 EMIF Operating Mode Select These bits control the operating mode of the External Memory Interface 00 Internal Only MOVX accesses on chip XRAM only All effective addresses alias to on chip memory space 01 Split Mode without Bank Select Accesses below the 8k boundary are directed on chip Accesses above the 8k boundary are directed off chip 8 bit off chip MOVX operations use the current contents of the Address High port latches to resolve upper address byte Note that in order to access off chip space EMIOCN must be set to a page that is not contained in the on chip address space 10 Split Mode with Bank Select Accesses below the 8k boundary are directed on chip Accesses above the 8k boundary are directed off chip 8 bit off chip MOVX operations use the contents of EMIOCN to determine the high byte of the address 11 External Only MOVX accesses off chip XRAM only On chip XRAM is not visible to the CPU 51 0 EALE1 0 ALE Pulse Width Select Bits only has effect when EMD2 0 00 ALE high and ALE low pulse width 1 SYSCLK cycle 01 ALE high and ALE low pulse width 2 SYSCLK cycles 10 ALE high and ALE low pulse width 3 SYSCLK cycles 11 ALE high and ALE low pulse width 4 SYSCLK cycles 67 Rev 0 5 121 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7
72. Port input mode selection 14 3 1 Clocking Timers Directly Through the External Oscillator The external oscillator source divided by eight is a clock option for the timers Section 21 Timers on page 243 and the Programmable Counter Array PCA Section 22 Programmable Counter Array PCAO on page 263 When the external oscillator is used to clock these peripherals but is not used as the system clock the external oscillator frequency must be less than or equal to the system clock fre quency In this configuration the clock supplied to the peripheral external oscillator 8 is synchronized with the system clock the jitter associated with this synchronization is limited to 0 5 system clock cycles 14 3 2 External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU the circuit should be configured as shown in Figure 14 1 Option 1 The External Oscillator Frequency Control value XFCN should be chosen from the Crystal column of the table in SFR Definition 14 4 OSCXCN register For example a 12 MHz crystal requires an setting of 111b When the crystal oscillator is first enabled the oscillator amplitude detection circuit requires a settling time to achieve proper bias Introducing a delay of 1 ms between enabling the oscillator and checking the XTLVLD bit will prevent a premature switch to the external oscillator as the system clock Switching to the external oscillator
73. R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0x8B Bits 7 0 TL1 Timer 1 Low Byte The TL1 register is the low byte of the 16 bit Timer 1 SFR Definition 21 6 THO Timer 0 High Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0x8C Bits 7 0 THO Timer 0 High Byte The THO register is the high byte of the 16 bit Timer O SFR Definition 21 7 TH1 Timer 1 High Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0x8D Bits 7 0 TH1 Timer 1 High Byte The TH1 register is the high byte of the 16 bit Timer 1 250 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 21 2 Timer 2 Timer 2 is a 16 bit timer formed by two 8 bit SFRs TMR2L low byte and TMR2H high byte Timer 2 may operate in 16 bit auto reload mode split 8 bit auto reload mode USB Start of Frame SOF capture mode or Low Frequency Oscillator LFO Falling Edge capture mode The Timer 2 operation mode is defined by the T2SPLIT TMR2CN 3 T2CE TMR2CN 4 bits and T2CSS TMR2ON 1 bits Timer 2 may be clocked by the system clock the system clock divided by 12 or the external oscillator source divided by 8 The external clock mode is ideal for real time clock RTC functionality where the i
74. R W Reset Value SCR6 SCR5 SCR4 SCR3 SCR2 SCRO 00000000 Bit6 Bit5 Bit4 Bit3 Bit2 BitO SFR Address 2 Bits 7 0 SCR7 SCRO0 SPIO Clock Rate These bits determine the frequency of the SCK output when the SPIO module is configured for master mode operation The SCK clock frequency is a divided version of the system clock and is given in the following equation where SYSCLK is the system clock frequency and SPIOCKR is the 8 bit value held in the SPIOCKR register SYSCLK SCK 2x SPIOCKR 1 for 0 lt SPIOCKR lt 255 Example If SYSCLK 2 MHz and SPIOCKR 0x04 ferme 2000000 5 2x 4 1 fsck 200kHz SFR Definition 20 4 SPIODAT SPIO Data R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit BitO SFR Address OxA3 Bits 7 0 SPIODAT SPIO Transmit and Receive Data The SPIODAT register is used to transmit and receive SPIO data Writing data to SPIODAT places the data into the transmit buffer and initiates a transfer when in Master Mode A read of SPIODAT returns the contents of the receive buffer 238 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 vosi SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 Figure 20 8 SPI Master Timing CKPHA 0 i SCK is shown for CKPOL 0 SCK is the oppos
75. Read This bit always reads 0 Bit5 STSTL Sent Stall Hardware sets this bit to 1 when a STALL handshake signal is transmitted The FIFO is flushed and the INPRDY bit cleared This flag must be cleared by software Bit4 SDSTL Send Stall Software should write 1 to this bit to generate a STALL handshake in response to an IN token Software should write 0 to this bit to terminate the STALL signal This bit has no effect in ISO mode Bit3 FLUSH FIFO Flush Writing a 1 to this bit flushes the next packet to be transmitted from the IN Endpoint FIFO The FIFO pointer is reset and the INPRDY bit is cleared If the FIFO contains multiple pack ets software must write 1 to FLUSH for each packet Hardware resets the FLUSH bit to 0 when the FIFO flush is complete Bit2 UNDRUN Data Underrun The function of this bit depends on the IN Endpoint mode ISO Set when a zero length packet is sent after an IN token is received while bit INPRDY 0 Interrupt Bulk Set when a NAK is returned in response to an IN token This bit must be cleared by software Bit1 FIFONE FIFO Not Empty 0 The IN Endpoint FIFO is empty 1 The IN Endpoint FIFO contains one or more packets Bito INPRDY In Packet Ready Software should write 1 to this bit after loading a data packet into the IN Endpoint FIFO Hardware clears INPRDY due to any of the following 1 A data packet is transmitted 2 Double buffering is enabled DBIEN 1
76. Registers 82 Table 9 4 Interrupt SUuMMary s eoe eere ve eo iere pecu 89 10 Prefetch Engine 11 Reset Sources Figure 11 1 Reset SOUIGS P ion ee pite qe 101 Figure 11 2 Power On and VDD Monitor Reset Timing 102 Table 11 1 Reset Electrical 2222 4 21 107 12 Flash Memory Table 12 1 Flash Electrical 040001 111 Figure 12 1 Flash Program Memory Map and Security 112 13 External Data Memory Interface and On Chip XRAM Figure 13 1 USB FIFO Space and XRAM Memory Map with USBFAE set to 1 118 Figure 13 2 Multiplexed Configuration 122 Figure 13 3 Non multiplexed Configuration 123 Figure 13 4 EMIF Operating 123 Figure 13 5 Non multiplexed 16 bit MOVX 127 Figure 13 6 Non multiplexed 8 bit MOVX without Bank Select Timing 128 Figure 13 7 Non multiplexed 8 bit MOVX with Bank Select Timing 129 Figure 13 8 Multiplexed 16 bit 130 Figure 13 9 Multiplexed 8 bit MOVX without Bank Select Timing
77. SFR Definition 22 3 PCAOCPMn PCA Capture Compare Mode R W R W R W R W R W R W R W R W Reset Value PWM16n ECOMn CAPPn CAPNn MATn TOGn PWMn EECFn 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address OxDA 0xDB OxDC OxDD OxDE PCAOCPMn Address PCAOCPMO n 0 PCAOCPM1 OxDB n 1 2 0xDC 2 OxDD n 3 PCAOCPM4 OxDE n 4 Bit7 16 16 bit Pulse Width Modulation Enable This bit selects 16 bit mode when Pulse Width Modulation mode is enabled PWMn 1 0 8 bit PWM selected 1 16 bit PWM selected Bit6 ECOMn Comparator Function Enable This bit enables disables the comparator function for PCA module n 0 Disabled 1 Enabled Bit5 CAPPn Capture Positive Function Enable This bit enables disables the positive edge capture for PCA module n 0 Disabled 1 Enabled Bit4 CAPNn Capture Negative Function Enable This bit enables disables the negative edge capture for PCA module n 0 Disabled 1 Enabled Bit3 MATn Match Function Enable This bit enables disables the match function for PCA module n When enabled matches of the PCA counter with a module s capture compare register cause the CCFn bit in PCAOMD register to be set to logic 1 0 Disabled 1 Enabled Bit2 TOGn Toggle Function Enable This bit enables disables the toggle function for PCA module n When enabled matches of the PCA counter with a mod
78. SUSPEND IFCN1 IFCNO 10000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address OxB2 Bit7 IOSCEN Internal H F Oscillator Enable Bit 0 Internal H F Oscillator Disabled 1 Internal H F Oscillator Enabled Bit6 IFRDY Internal H F Oscillator Frequency Ready Flag 0 Internal H F Oscillator is not running at programmed frequency 1 Internal H F Oscillator is running at programmed frequency Bit5 SUSPEND Force Suspend Writing a 1 to this bit will force the internal H F oscillator to be stopped The oscillator will be re started on the next non idle USB event i e RESUME signaling or VBUS interrupt event see SFR Definition 8 1 Bits4 2 UNUSED Read 000b Write don t care 51 0 IFCN1 0 Internal H F Oscillator Frequency Control 00 SYSCLK derived from Internal H F Oscillator divided by 8 01 SYSCLK derived from Internal H F Oscillator divided by 4 10 SYSCLK derived from Internal H F Oscillator divided by 2 11 SYSCLK derived from Internal H F Oscillator divided by 1 136 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 14 2 OSCICL Internal H F Oscillator Calibration R W R W R W R W R W R W R W R W Reset Value OSCCAL Variable Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0xB3 Bits4 0 OSCCAL Oscillator Calibration Value These bits determine the internal H F oscillator period When set to 00000b the oscillator operates at its fastest se
79. TOM1 TOMO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit Address 0x89 Bit7 GATE1 Timer 1 Gate Control 0 Timer 1 enabled when TR1 1 irrespective of INT1 logic level 1 Timer 1 enabled only when TR1 1 AND is active as defined by bit INTPL in regis ter INTO1CF see SFR Definition 9 13 Bit6 C T1 Counter Timer 1 Select 0 Timer Function Timer 1 incremented by clock defined by T1M bit CKCON 4 1 Counter Function Timer 1 incremented by high to low transitions on external input pin T1 Bits5 4 T1M1 T1MO Timer 1 Mode Select These bits select the Timer 1 operation mode T1M1 T1MO Mode 0 0 Mode 0 13 bit counter timer 0 1 Mode 1 16 bit counter timer 1 0 Mode 2 8 bit counter timer with auto reload 1 1 Mode 3 Timer 1 inactive Bit3 GATEO Timer 0 Gate Control 0 Timer 0 enabled when TRO 1 irrespective of INTO logic level 1 Timer 0 enabled only when TRO 1 AND INTO is active as defined by bit INOPL in regis ter INTO1CF see SFR Definition 9 13 Bit2 C TO Counter Timer Select 0 Timer Function Timer 0 incremented by clock defined by TOM bit CKCON 3 1 Counter Function Timer 0 incremented by high to low transitions on external input pin TO Bits1 0 TOM1 TOMO Timer 0 Mode Select These bits select the Timer 0 operation mode TOM1 TOMO Mode 0 0 Mode 0 13 bit counter timer 0 1 Mode 1 16 bit counter timer 1 0 Mode 2 8 bit counter timer wi
80. These bits can be used to test the USBO transceiver PHYTST 1 0 Mode D D 00b Mode 0 Normal non test mode X X 01b Mode 1 Differential 1 Forced 1 0 10b Mode 2 Differential 0 Forced 0 1 11b Mode 3 Single Ended 0 Forced 0 0 Bit2 DFREC Differential Receiver The state of this bit indicates the current differential value present on the D and D lines when PHYEN 1 0 Differential 0 signaling on the bus 1 Differential 1 signaling on the bus Biti Dp D Signal Status This bit indicates the current logic level of the D pin 0 D signal currently at logic 0 1 D signal currently at logic 1 Bito Dn D Signal Status This bit indicates the current logic level of the D pin 0 D signal currently at logic O 1 D signal currently at logic 1 e Rev 0 5 165 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 16 3 USB Register Access The USBO controller registers listed in Table 16 2 are accessed through two SFRs USBO Address USBOADR and USBO Data USBODAT The USBOADR register selects which USB register is targeted by reads writes of the USBODAT register See Figure 16 2 Endpoint control status registers are accessed by first writing the USB register INDEX with the target end point number Once the target endpoint number is written to the INDEX register the control status registers associated with the target endpoint may be accessed See the Indexed Registers s
81. VBUS 12 8 DIn VBUS Sense Input This pin should be connected to the VBUS signal of a USB network A 5 V signal on this pin indi cates a USB network connection D DIO USB D D DIO USB D PO O D I O or Port 0 0 See Section 15 for a complete description of Port Aln 0 PO 1 5 1 D I O or Port 0 1 A In PO 2 4 32 D I O or Port 0 2 A In PO 3 3 31 D I O or Port 0 3 A In PO 4 2 30 D I O or Port 0 4 A In PO 5 1 29 DO or Port 0 5 A In PO 6 48 28 DO or Port 0 6 A In PO 7 47 27 D I O or Port 0 7 A In s Rev 0 5 33 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 4 1 Pin Definitions for the C8051F340 1 2 3 4 5 6 7 Continued Pin Numbers Name Type Description 48 pin 32 pin P1 0 46 26 DO or 1 0 See Section 15 for a complete description of Port A In 1 P1 1 45 25 D I O or Port 1 1 A In P1 2 44 24 D I O or Port 1 2 A In P1 3 43 23 D I O or Port 1 3 A In P1 4 42 22 D I O or Port 1 4 A In P1 5 41 21 D I O or Port 1 5 A In P1 6 40 20 D I O or Port 1 6 A In P1 7 39 19 D I O or Port 1 7 A In P2 0 38 18 DO or Port 2 0 See Section 15 for a complete description of Port Aln 12 P2 1 37 17 D I O or Port 2 1 A In P2 2 36 16 D I O or Port 2 2 A In P2 3 35 15 D I O or Por 2 3 A In P2 4 34 14 D I O or Port 2 4 A In P2 5 33 13 D I O or 2 5 A In P2 6 32 12 D I O or Port 2 6 A In P2
82. VBUS Detection When the USB Function Controller is used see section Section 16 Universal Serial Bus Controller 05 0 on page 163 the VBUS signal should be connected to the VBUS pin The VBSTAT bit register REGOCN indicates the current logic level of the VBUS signal If enabled a VBUS interrupt will be gener ated when the VBUS signal matches the polarity selected by the VBPOL bit in register REGOCN The VBUS interrupt is level sensitive and has no associated interrupt pending flag The VBUS interrupt will be active as long as the VBUS signal matches the polarity selected by VBPOL See Table 8 1 for VBUS input parameters Important Note When USB is selected as a reset source a system reset will be generated when the VBUS signal matches the polarity selected by the VBPOL bit See Section 11 Reset Sources on page 101 for details on selecting USB as a reset source Table 8 1 Voltage Regulator Electrical Specifications 40 to 85 unless otherwise specified Parameter Conditions Min Typ Max Units Input Voltage Range 2 7 5 25 V Output Voltage Vpp Output Current 1 to 100 mA 3 0 3 3 3 6 V Output Current 100 mA VBUS Detection Input Threshold 1 0 1 8 4 0 V Bias Current Normal Mode REGMOD 07 90 TBD A Low Power Mode REGMOD 1 60 TBD H IDD 1 mA 1 3 Dropout Voltage Vno IDD 100 mA 100 mV mA Notes 1 Input range specified for regulation When an external regulator is us
83. X ns SCK Sample Edge to MOSI Change 2 X ns Tsou SCK Shift Edge to MISO Change 4xTsyscik ns Taig Last SCK Edge to MISO Change CKPHA 1 Shake Cris Note is equal to one period of the device system clock SYSCLK SILICON LABORATORIES Rev 0 5 241 C8051F340 1 2 3 4 5 6 7 NOTES 242 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 21 Timers Each MCU includes four counter timers two are 16 bit counter timers compatible with those found in the standard 8051 and two are 16 bit auto reload timer for use with the ADC SMBus USB frame measure ments Low Frequency Oscillator period measurements or for general purpose use These timers can be used to measure time intervals count external events and generate periodic interrupt requests Timer 0 and Timer 1 are nearly identical and have four primary modes of operation Timer 2 and Timer 3 offer 16 bit and split 8 bit timer functionality with auto reload Timer 0 and Timer 1 Modes Timer 2 Modes Timer 3 Modes 1200 counter 16 bit timer with auto reload 16 bit timer with auto reload 16 bit counter timer 8 bit counter timer with auto reload Two 8 bit timers with Two 8 bit timers with Two 8 bit counter timers Timer 0 only auto reload auto reload Timers 0 and 1 may be clocked by one of five sources determined by the Timer Mode Select bits T1M TOM an
84. an increased external oscillator supply cur rent 7 0 1 MHz 100 kHz 14 3 4 External Capacitor Example If a capacitor is used as an external oscillator for the MCU the circuit should be configured as shown in Figure 14 1 Option 3 The capacitor should be no greater than 100 pF however for very small capacitors the total capacitance may be dominated by parasitic capacitance in the PCB layout To determine the required External Oscillator Frequency Control value XFCN in the OSCXCN Register select the capaci tor to be used and find the frequency of oscillation from the equations below Assume Vpp 3 0 V and C 50 pF KF KF I cx Vpp 50x3 MHz 150 MHz If a frequency of roughly 150 kHz is desired select the K Factor from the table in SFR Definition 14 4 as 22 22 f 150 Therefore the XFCN value to use in this example is 011b 0 146 MHz or 146 kHz 140 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 14 4 OSCXCN External Oscillator Control R R W R W R W R R W R W R W Reset Value XTLVLD XOSCMD2 XOSCMD1 XOSCMDO XFCN2 XFCN1 XFCNO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0xB1 Bit7 XTLVLD Crystal Oscillator Valid Flag Read only when XOSCMD 11x 0 Crystal Oscillator is unused or not yet stable 1 Crystal Oscillator is running and stable 56 4 XOSCMD2 0 External Oscillator Mode Bits 00x External Oscillator
85. and must be manually cleared by software T2XCLK SYSCLK 12 External Clock 8 Interrupt TMRoRLL 2604 SYSCLK p TCLK To ADC TMR2L gt SMBus Figure 21 5 Timer 2 8 Bit Mode Block Diagram 252 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 21 2 3 Timer 2 Capture Modes USB Start of Frame or LFO Falling Edge When T2CE 1 Timer 2 will operate in one of two special capture modes The capture event be selected between a USB Start of Frame SOF capture and a Low Frequency Oscillator LFO Falling Edge capture using the T2CSS bit The USB SOF capture mode can be used to calibrate the system clock or external oscillator against the known USB host SOF clock The LFO falling edge capture mode can be used to calibrate the internal Low Frequency Oscillator against the internal High Frequency Oscillator or an external clock source When T2SPLIT Timer 2 counts up and overflows from OxFFFF to 0x0000 Each time a capture event is received the contents of the Timer 2 registers TMR2H TMR2L are latched into the Timer 2 Reload registers TMR2RLH TMR2RLL A Timer 2 interrupt is generated if enabled SYSCLK 12 TL2 To SMBus Overflow TR2 TCLK To ADC External Clock 8 m TMR2L TMR2H 9 SMBus SYSCLK USB Start of Frame SOF TMR2RLL TMR2RLH Low Frequency Oscillator Fa
86. as shown in Table 22 1 When the counter timer overflows from OxFFFF to 0x0000 the Counter Overflow Flag CF in PCAOMD is set to logic 1 and an interrupt request is generated if CF interrupts are enabled Setting the ECF bit in PCAOMD to logic 1 enables the CF flag to generate an interrupt request The CF bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by soft ware Note PCAO interrupts must be globally enabled before CF interrupts are recognized PCAO inter rupts are globally enabled by setting the EA bit IE 7 and the EPCAO bit in EIE1 to logic 1 Clearing the CIDL bit in the PCAOMD register allows the PCA to continue normal operation while the CPU is in Idle mode Table 22 1 PCA Timebase Input Options CPS2 CPS1 CPSO Timebase 0 0 0 System clock divided by 12 0 0 1 System clock divided by 4 0 1 0 Timer 0 overflow 0 1 1 High to low transitions on max rate system clock divided by 4 1 0 0 System clock 1 0 1 External oscillator source divided by 8 Note External oscillator source divided by 8 is synchronized with the system clock IDLE Ov PCAOMD c c 110 0 D T L 5 5 5 L E C 2 1 0 0 TO To SFR Bus PCAOL read Snapshot Register SYSCLK 12 5
87. be read from the OUT endpoint FIFO FIFO pointer is reset and the OPRDY bit is cleared If the FIFO contains multiple packets software must write 1 to FLUSH for each packet Hardware resets the FLUSH bit to 0 when the FIFO flush is complete Note If data for the current packet has already been read from the FIFO the FLUSH bit should not be used to flush the packet Instead the entire data packet should be read from the FIFO manually Bit3 DATERR Data Error In ISO mode this bit is set by hardware if a received packet has a CRC or bit stuffing error It is cleared when software clears OPRDY This bit is only valid in ISO mode Bit2 OVRUN Data Overrun This bit is set by hardware when an incoming data packet cannot be loaded into the OUT endpoint FIFO This bit is only valid in ISO mode and must be cleared by software 0 No data overrun 1 A data packet was lost because of a full FIFO since this flag was last cleared Bit1 FIFOFUL OUT FIFO Full This bit indicates the contents of the OUT FIFO If double buffering is enabled for the end point DBIEN 1 the FIFO is full when the FIFO contains two packets If DBIEN 0 the FIFO is full when the FIFO contains one packet 0 OUT endpoint FIFO is not full 1 OUT endpoint FIFO is full Bito OPRDY OUT Packet Ready Hardware sets this bit to 1 and generates an interrupt when a data packet is available Soft ware should clear this bit after each data packet is
88. be shared with user functions allowing in system debugging with out occupying package pins Each device is specified for 2 7 5 25 V operation over the industrial temperature range 40 to 85 C For voltages above 3 6 V the on chip Voltage Regulator must be used A minimum of 3 0 V is required for USB communication The Port I O and RST pins are tolerant of input signals up to 5 V C8051F340 1 2 3 4 5 6 7 are available in a 48 pin TQFP or a 32 pin LQFP package s Rev 0 5 17 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 1 1 Product Selection Guide obeyed 10 Bojeuy oouaJ9JoH Josueg eunje1eduuo OQV Sdsx002 119 01 v v v 2 LQFP32 v 2 LQFP32 v v v 2 LQFP32 v v v 2 LQFP32 JIIN3 eoeneiu eu491X3 SO uod e15IG 25 25 25 25 19 uno 19 91 saw 4 A 4 Ao A v SLAV N 1 1 1 1 145 OcI SngiNS JoyeinBay eBeyoA Ajddng 1utodpu3 gsn v V 0 V Vivi viv Jo e IOSEQ AouenbeiJ 1018 1060 EUJEJU s914g Aiowayy USEJJ 488d SdIW JequinN C8051F340 GQ 48 64k 4352 v v v V 2 4 v 40O v v IY Y 2 TQFPA8 C8051F341 GQ 48 32k 2304 v v v v v v 2 4 v
89. before the crystal oscillator has stabilized can result in unpredictable behavior The rec ommended procedure is Step 1 Enable the external oscillator Step 2 Wait at least 1 ms Step 3 Poll for XTLVLD gt 1 Step 4 Switch the system clock to the external oscillator Important Note on External Crystals Crystal oscillator circuits are quite sensitive to PCB layout The crystal should be placed as close as possible to the XTAL pins on the device The traces should be as short as possible and shielded with ground plane from any other traces which could introduce noise or interference e Rev 0 5 139 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 14 3 3 External RC Example If an RC network is used as an external oscillator source for the MCU the circuit should be configured as shown in Figure 14 1 Option 2 The capacitor should be no greater than 100 pF however for very small capacitors the total capacitance may be dominated by parasitic capacitance in the PCB layout To deter mine the required External Oscillator Frequency Control value XFCN in the OSCXCN Register first select the RC network value to produce the desired frequency of oscillation If the frequency desired is 100 kHz let R 246 and C 50 pF 12300 123 10 RC 246 x 50 Referring to the table in SFR Definition 14 4 the required XFCN setting is 010b Programming XFCN to a higher setting in RC mode will improve frequency accuracy at
90. bus error recognition as defined by the SMBOCF configuration register e START STOP timing detection and generation M Bus arbitration Interrupt generation e Status information SMBus interrupts are generated for each data byte or slave address that is transferred When transmitting this interrupt is generated after the ACK cycle so that software may read the received ACK value when receiving data this interrupt is generated before the ACK cycle so that software may define the outgoing ACK value See Section 17 5 SMBus Transfer Modes on page 204 for more details on transmission sequences Interrupts are also generated to indicate the beginning of a transfer when a master START generated or the end of a transfer when a slave STOP detected Software should read the SMBOCN SMBus Control register to find the cause of the SMBus interrupt The SMBOON register is described in Section 17 4 2 SMBOCN Control Register on page 201 Table 17 4 provides a quick SMBOCN decoding refer ence 196 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SMBus configuration options include Timeout detection SCL Low Timeout and or Bus Free Timeout e SDA setup and hold time extensions Slave event enable disable e Clock source selection These options are selected in the SMBOCF register as described in Section 17 4 1 SMBus Configura tion Register on page 198 s Rev 0 5 197 SILICON LABORATORIE
91. by IT1 is detected It can be cleared by software but is automatically cleared when the CPU vectors to the External Inter rupt 1 service routine if IT1 1 When IT1 0 this flag is set to 1 when INT1 is active as defined by bit INTPL in register INTO1CF see SFR Definition 9 13 IT1 Interrupt 1 Type Select This bit selects whether the configured INT1 interrupt will be edge or level sensitive INT1 is configured active low or high by the IN1PL bit in the ITO1CF register see SFR Definition 9 13 0 INT1 is level triggered 1 INT1 is edge triggered 0 External Interrupt 0 This flag is set by hardware when an edge level of type defined by ITO is detected It can be cleared by software but is automatically cleared when the CPU vectors to the External Inter rupt 0 service routine if ITO 1 When ITO 0 this flag is set to 1 when INTO is active as defined by bit INOPL in register INTO1CF see SFR Definition 9 13 ITO Interrupt O Type Select This bit selects whether the configured INTO interrupt will be edge or level sensitive INTO is configured active low or high by the INOPL bit in register ITO1CF see SFR Definition 9 13 0 INTO is level triggered 1 INTO is edge triggered e Rev 0 5 247 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 21 2 TMOD Timer Mode R W R W R W R W R W R W R W R W Reset Value GATE1 C T1 T1M1 T1MO GATEO C TO
92. by software CCF2 PCA Module 2 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF2 interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software CCF1 PCA Module 1 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF 1 interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software CCFO PCA Module 0 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCFO interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software 274 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 22 2 PCAOMD PCA Mode RW R W R W R W R W R W R W R W Reset Value CIDL WDTE WDLCK CPS2 CPS1 50 01000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address OxD9 Bit7 CIDL PCA Counter Timer Idle Control Specifies PCA behavior when CPU is in Idle Mode 0 PCA continues to function normally while the system controller is in Idle Mode 1 PCA operation is suspended while the system controller is in Idle Mode Bit6 WDTE Watchdog T
93. characteristics 12 1 Programming The Flash Memory The simplest means of programming the Flash memory is through the C2 interface using programming tools provided by Silicon Labs or a third party vendor This is the only means for programming a non initial ized device For details on the C2 commands to program Flash memory see Section 23 C2 Interface on page 279 To ensure the integrity of Flash contents the Monitor must be enabled before writing and or erasing Flash memory from software If a write or erase attempt is made while the Vpp monitor is disabled it will cause a Flash Error device reset 12 1 1 Flash Lock and Key Functions Flash writes and erases by user software are protected with a lock and key function The Flash Lock and Key Register FLKEY must be written with the correct key codes in sequence before Flash operations may be performed The key codes 5 OxF1 The timing does not matter but the codes must be written in order If the key codes are written out of order or the wrong codes are written Flash writes and erases will be disabled until the next system reset Flash writes and erases will also be disabled if a Flash write or erase is attempted before the key codes have been written properly The Flash lock resets after each write or erase the key codes must be written again before a following Flash operation can be per formed The FLKEY register is detailed in SFR Definition 12 2 12 1 2
94. drain 1 Corresponding P4 n Output is push pull Note P4 is only available on 48 pin devices e Rev 0 5 161 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 15 1 Port O DC Electrical Characteristics Vpp 2 7 to 3 6 V 40 to 85 C unless otherwise specified Parameters Conditions Min Typ Max Units 3 mA Port I O push pull Vpp 0 7 Output High Voltage 710 pA Port I O push pull Vpp 0 1 V 10 mA Port I O push pull Vpp 0 8 lol 8 5 mA 0 6 Output Low Voltage lo 10 pA 0 1 V lo gt 25 mA 1 0 Input High Voltage 2 0 V Input Low Voltage 0 8 V i Lus Weak Pull up Off 1 A NPT SAE Hen Weak Pull up On Vy 2 0 V 25 50 162 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 16 Universal Serial Bus Controller USBO C8051F340 1 2 3 4 5 6 7 devices include a complete Full Low Speed USB function for USB peripheral implementations The USB Function Controller USBO consists of a Serial Interface Engine SIE USB Transceiver including matching resistors and configurable pull up resistors 1k FIFO block and clock recovery mechanism for crystal less operation No external components are required The USB Function Controller and Transceiver is Universal Serial Bus Specification 2 0 compliant Transceiver Data Transfer Control Serial Interface Engine SIE EndpointO IN OUT Endpoint2 Endpoin
95. enabled to use Ports PO P1 P2 and as standard Port I O in output mode These Port output drivers are disabled while the Crossbar is disabled Port 4 always func tions as standard GPIO s Rev 0 5 151 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 15 1 XBRO Port I O Crossbar Register 0 R W R W R W R W Reset Value CP1E CPOAE CPOE SYSCKE 00000000 Bit6 Bit5 Bit4 Bit3 SFR Address OxE1 CP1AE Comparator1 Asynchronous Output Enable 0 Asynchronous CP1 unavailable at Port pin 1 Asynchronous CP1 routed to Port pin CP1E Comparator1 Output Enable 0 CP1 unavailable at Port pin 1 CP1 routed to Port pin CPOAE ComparatorO Asynchronous Output Enable 0 Asynchronous unavailable at Port pin 1 Asynchronous CPO routed to Port pin CPOE ComparatorO Output Enable 0 CPO unavailable at Port pin 1 routed to Port pin SYSCKE SYSCLK Output Enable 0 SYSCLK unavailable at Port pin 1 SYSCLK output routed to Port pin SMBOE SMBus Enable 0 SMBus unavailable at Port pins 1 SMBus O routed to Port pins SPIOE SPI O Enable 0 SPI O unavailable at Port pins 1 SPI O routed to Port pins URTOE UARTO I O Output Enable 0 UARTO I O unavailable at Port pins 1 UARTO TXO RXO routed to Port pins P0 4 and 0 5 152 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 15 2 XBR1
96. in the halt state where all on chip peripherals and user software are stalled In this halted state the C2 interface can safely borrow the C2CK RST and C2D P3 0 pins In most applications external resistors are required to isolate C2 interface traffic from the user application A typi cal isolation configuration is shown in Figure 23 1 C8051 Fxxx Reset a Input b C2D Output c C2 Interface Master Figure 23 1 Typical C2 Pin Sharing The configuration in Figure 23 1 assumes the following 1 The user input b cannot change state while the target device is halted 2 RST on the target device is used as an input only Additional resistors may be necessary depending on the specific application e Rev 0 5 281 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 CONTACT INFORMATION Silicon Laboratories Inc 4635 Boston Lane Austin TX 78735 Tel 1 512 416 8500 Fax 1 512 416 9669 Toll Free 1 877 444 3032 Email MCUinfo silabs com Internet www silabs com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice Silicon Laboratories assumes no responsibility for errors and omissions and disclaims responsibility for any consequences resulting from the use of information included herein Additionally Silicon Laboratories assumes no responsibility for the function ing of undescribed f
97. low byte of the reload value for Timer 2 when operating in auto reload mode or the captured value of the TMR2L register in capture mode SFR Definition 21 10 TMR2RLH Timer 2 Reload Register High Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address OxCB Bits 7 0 TMR2RLH Timer 2 Reload Register High Byte The TMR2RLH holds the high byte of the reload value for Timer 2 when operating in auto reload mode or the captured value of the TMR2H register in capture mode SFR Definition 21 11 TMR2L Timer 2 Low Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0xCC Bits 7 0 TMR2L Timer 2 Low Byte In 16 bit mode the TMR2L register contains the low byte of the 16 bit Timer 2 In 8 bit mode TMR2L contains the 8 bit low byte timer value SFR Definition 21 12 TMR2H Timer 2 High Byte RW R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit BitO SFR Address OxCD Bits 7 0 TMR2H Timer 2 High Byte In 16 bit mode the TMR2H register contains the high byte of the 16 bit Timer 2 In 8 bit mode TMR2H contains the 8 bit high byte timer value 256 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 21 3 Timer 3 Timer 3 is a 16 bit timer formed by two 8 bit SFRs TMR3L low byte and TMR3H high byte Timer 3 may operate in 16 bit auto
98. negative edge or either transition positive or negative edge When a capture occurs the Capture Compare Flag CCFn in PCAOCN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine and must be cleared by software If both CAPPn and CAPNn bits are set to logic 1 then the state of the Port pin associated with CEXn can be read directly to determine whether a rising edge or falling edge caused the capture PCA Interrupt gt PCAOCPMn uh PCAOCN C C C C C C C F 1 F F F 432 PCAOCPLn PCAOCPHn to CCFn Port I O XH Crossbar LCEXn Je s b PCAOL PCAOH Figure 22 4 PCA Capture Mode Diagram Note The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the hardware 266 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 22 2 2 Software Timer Compare Mode In Software Timer mode the PCA counter timer value is compared to the module s 16 bit capture compare register PCAOCPHn and PCAOCPLn When a match occurs the Capture Compare Flag CCFn in PCAOCN is set to logic 1 and an interrupt request is generated if CCF interrupts are enabled The CCFn bit is not automatically cl
99. oscillator while the internal oscillator drives the sys tem clock The PCA is configured and controlled through the system controller s Special Function Regis ters The PCA block diagram is shown in Figure 22 1 Important Note The PCA Module 4 may be used as a watchdog timer WDT and is enabled in this mode following a system reset Access to certain PCA registers is restricted while WDT mode is enabled See Section 22 3 for details SYSOLK 12 SYSOLK 4 Timer 0 Overflow p 16 Bit Counter Timer SYSCLK External Clock 8 Capture Compare Module 0 Capture Compare Module 1 Capture Compare Module 2 Capture Compare Module 3 Capture Compare Module 4 WDT 103 0X49 X30 2X40 Figure 22 1 PCA Block Diagram s Rev 0 5 263 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 22 1 PCA Counter Timer The 16 bit PCA counter timer consists of two 8 bit SFRs PCAOL and PCAOH PCAOH is the high byte MSB of the 16 bit counter timer and PCAOL is the low byte LSB Reading PCAOL automatically latches the value of PCAOH into a snapshot register the following PCAOH read accesses this snapshot register Reading the PCAOL Register first guarantees an accurate reading of the entire 16 bit PCAO counter Reading PCAOH or PCAOL does not disturb the counter operation The CPS2 CPSO bits in the PCAOMD register select the timebase for the counter timer
100. packet from the endpoint FIFO and reset the OPRDY bit to 0 If a data packet is received when there is no room in the endpoint FIFO an interrupt will be generated and the OVRUN bit EOUTCSRL 2 set to 1 If USBO receives an ISO data packet with a CRC error the data packet will be loaded into the endpoint FIFO OPRDY will be set to 1 an interrupt if enabled will be gen erated and the DATAERR bit EOUTCSRL 3 will be set to 17 Software should check the DATAERR bit each time a data packet is unloaded from an ISO OUT endpoint FIFO 188 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 USB Register Definition 16 21 EOUTCSRL USBO OUT Endpoint Control Low Byte W R W R W R W R R W R R W Reset Value CLRDT STSTL SDSTL FLUSH DATERR OVRUN FIFOFUL OPRDY 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito USB Address 0x14 Bit7 CLRDT Clear Data Toggle Write Software should write 1 to this bit to reset the OUT endpoint data toggle to 0 Read This bit always reads 0 Bit6 STSTL Sent Stall Hardware sets this bit to 1 when a STALL handshake signal is transmitted This flag must be cleared by software Bit5 SDSTL Send Stall Software should write 1 to this bit to generate a STALL handshake Software should write 0 to this bit to terminate the STALL signal This bit has no effect in ISO mode Bit4 FLUSH FIFO Flush Writing a 1 to this bit flushes the next packet to
101. packets into the IN FIFO at a time In this case hardware will reset INPRDY to 0 immediately after firmware loads the first packet into the FIFO and sets INPRDY to 1 An interrupt will not be generated in this case an interrupt will only be generated when a data packet is transmitted When firmware writes 1 to the FCDT bit EINCSRH 3 the data toggle for each IN packet will be toggled continuously regardless of the handshake received from the host This feature is typically used by Inter rupt endpoints functioning as rate feedback communication for Isochronous endpoints When FCDT 0 the data toggle bit will only be toggled when an ACK is sent from the host in response to an IN packet 16 12 2 Endpoints1 3 IN Isochronous Mode When the ISO bit EINCSRH 6 is set to 1 the target endpoint operates Isochronous ISO mode Once an endpoint has been configured for ISO IN mode the host will send one IN token data request per frame the location of data within each frame may vary Because of this it is recommended that double buffering be enabled for ISO IN endpoints Hardware will automatically reset INPRDY EINCSRL O to 0 when a packet slot is open in the endpoint FIFO Note that if double buffering is enabled for the target endpoint it is possible for firmware to load two packets into the IN FIFO at a time In this case hardware will reset INPRDY to 0 immediately after firm ware loads the first packet into
102. priority of the Timer 1 interrupt 0 Timer 1 interrupt set to low priority level 1 Timer 1 interrupts set to high priority level PX1 External Interrupt 1 Priority Control This bit sets the priority of the External Interrupt 1 interrupt 0 External Interrupt 1 set to low priority level 1 External Interrupt 1 set to high priority level PTO Timer 0 Interrupt Priority Control This bit sets the priority of the Timer 0 interrupt 0 Timer 0 interrupt set to low priority level 1 Timer 0 interrupt set to high priority level PXO External Interrupt 0 Priority Control This bit sets the priority of the External Interrupt 0 interrupt 0 External Interrupt 0 set to low priority level 1 External Interrupt 0 set to high priority level 67 Rev 0 5 91 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 R W SFR Definition 9 9 EIE1 Extended Interrupt Enable 1 R W R W R W R W R W R W R W ET3 ECP1 ECPO EADCO EWADCO EUSBO ESMBO Bit7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito Bite Bit5 Bit4 Bit3 Bit2 Bit Bito Reset Value 00000000 SFR Address OxE6 ET3 Enable Timer 3 Interrupt This bit sets the masking of the Timer 3 interrupt 0 Disable Timer 3 interrupts 1 Enable interrupt requests generated by the TF3L or TF3H flags ECP1 Enable Comparator1 CP1 Interrupt This bit s
103. t care Bits6 0 EOCNT Endpoint 0 Data Count This 7 bit number indicates the number of received data bytes in the Endpoint 0 FIFO This number is only valid while bit OPRDY is a 1 16 11 Configuring Endpoints1 3 Endpoints1 3 are configured and controlled through their own sets of the following control status registers IN registers EINCSRL and EINCSRH and OUT registers EOUTCSRL and EOUTCSRH Only one set of endpoint control status registers is mapped into the USB register address space at a time defined by the contents of the INDEX register USB Register Definition 16 4 Endpoints1 3 can be configured as IN OUT or both IN OUT Split Mode as described in Section 16 5 1 The endpoint mode Split Normal is selected via the SPLIT bit in register EINCSRH When SPLIT 1 the corresponding endpoint FIFO is split and both IN and OUT pipes are available When SPLIT 0 the corresponding endpoint functions as either or OUT the endpoint direction is selected by the DIRSEL bit in register EINCSRH 16 12 Controlling Endpoints1 3 IN Endpoints1 3 IN are managed via USB registers EINCSRL and EINCSRH All IN endpoints can be used for Interrupt Bulk or Isochronous transfers Isochronous ISO mode is enabled by writing 1 to the ISO bit in register EINCSRH Bulk and Interrupt transfers are handled identically by hardware An Endpoint1 3 IN interrupt is generated by any of the following conditions 1
104. that selects both positive and negative ADC inputs Twenty 48 pin package or twenty one 32 pin package of the Port I O pins can be used as analog inputs to the ADC Additionally the on chip Temperature Sensor output and the power supply voltage Vpp are available as ADC inputs User firmware may shut down the ADC to save power Conversions can be started in six ways a software command an overflow of Timer 0 1 2 or 3 or an external convert start signal This flexibility allows the start of conversion to be triggered by software events a periodic signal timer overflows or external HW signals Conversion completions are indicated by a status bit and an interrupt if enabled The resulting 10 bit data word is latched into the ADC data SFRs upon completion of a conversion Window compare registers for the ADC output data can be configured to interrupt the controller when ADC data is either within or outside of a specified range The ADC can monitor a key voltage continuously in background mode but not interrupt the controller unless the converted data is within outside the specified range Analog Multiplexer 21 Selections on 32 pin package Configuration Control and Data Registers 20 Selections on 48 pin package eur 000 ADOBUSY W Port VO Conversion 901 Timer 0 Overflow Pins 010 Timer 2 Overflow 011 Timer 1 Overflow VDD 100 H CN
105. the FIFO and sets INPRDY to 1 An interrupt will not be generated in this case an interrupt will only be generated when a data packet is transmitted If there is not a data packet ready in the endpoint FIFO when USBO receives an IN token from the host USBO will transmit a zero length data packet and set the UNDRUN bit EINCSRL 2 to 1 The ISO Update feature see Section 16 7 can be useful in starting a double buffered ISO IN endpoint If the host has already set up the ISO IN pipe has begun transmitting IN tokens when firmware writes the first data packet to the endpoint FIFO the next IN token may arrive and the first data packet sent before firmware has written the second double buffered data packet to the FIFO The ISO Update feature ensures that any data packet written to the endpoint FIFO will not be transmitted during the current frame the packet will only be sent after a SOF signal has been received s Rev 0 5 185 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 USB Register Definition 16 19 EINCSRL USBO IN Endpoint Control Low Byte R W R W R W R W R W R W R W Reset Value CLRDT STSTL SDSTL FLUSH UNDRUN FIFONE INPRDY 00000000 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bito USB Address 0x11 Bit7 Unused Read 0 Write 2 don t care Bit6 CLRDT Clear Data Toggle Write Software should write 1 to this bit to reset the IN Endpoint data toggle to 0
106. the internal oscillators the external oscillator circuit or the 4x Clock Multiplier divided by 2 The USB clock USBCLK can be derived from the internal oscillator external oscillator or 4x Clock Multiplier Oscillator electrical specifications are given in Table 14 1 I 1 1 1 OSCICL OSCICN OSCLCN CLKSEL I 1 ZW e Seg wr Io un gt 2 US dd pap o Cc 0 OoB Goooooo mmm SSNS EE O00 Option 2 gs E VDD Option3 DD 1 L 1 7 n XTAL2 Y x M 1 v z Programmable High IOSC tn XTAL2 Frequency Oscillator 1 _ EE LZ J TN ide i v zu n gt Programmable Low Frequency Oscillator Option 1 l C8051F340 1 2 3 4 5 r SYSCLK XTAL1 7 gt ai r Input EXOSC m Ex Circuit EE A XTAL2 24 05 I 1 gt E EXOSC x2 x2 Option 4 7 UV BAD IOSC 2 A EXOSC 2 Clock Multiplier M LEY Y 3 m xc 1 o 2 EXOSC 2 Bess beo Bes 7 255 5 3 P gt gt EXOS
107. the source an interrupt request is generated when the interrupt pending flag is set As soon as execution of the current instruction is complete the CPU generates an LCALL to a prede termined address to begin execution of an interrupt service routine ISR Each ISR must end with an RETI instruction which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred If interrupts are not enabled the interrupt pending flag is ignored by the hardware and program execution continues as normal The interrupt pending flag is set to logic 1 regard less of the interrupt s enable disable state Each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in an SFR IE EIE2 However interrupts must first be globally enabled by setting the EA bit IE 7 to logic 1 before the individual interrupt enables are recognized Setting the EA bit to logic 0 disables all interrupt sources regardless of the individual interrupt enable settings Some interrupt pending flags are automatically cleared by the hardware when the CPU vectors to the ISR However most are not cleared by the hardware and must be cleared by software before returning from the ISR If an interrupt pending flag remains set after the CPU completes the return from interrupt RETI instruction a new interrupt request will be generated immediately and the CPU will re enter the ISR after
108. to 0x00 T3XCLK SYSCLK 12 To ADC TR3 TCLK External Clock 8 TMRSL TMRSH SYSCLK E iT TMRBRLL TMR3RLH Reload Figure 21 8 Timer 3 16 Bit Mode Block Diagram Interrupt TMR3CN s Rev 0 5 257 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 21 3 2 8 bit Timers with Auto Reload When T3SPLIT is 1 and T3CE 0 Timer operates as two 8 bit timers TMR3H and TMR3L Both 8 bit timers operate in auto reload mode as shown in Figure 21 5 TMRS3RLL holds the reload value for TMR3L TMRBRLH holds the reload value for TMR3H The TR3 bit in TMR3CN handles the run control for TMR3H TMR3L is always running when configured for 8 bit Mode Each 8 bit timer may be configured to use SYSCLK SYSCLK divided by 12 or the external oscillator clock source divided by 8 The Timer 3 Clock Select bits T3MH and T3ML in CKCON select either SYSCLK or the clock defined by the Timer 3 External Clock Select bit T3XCLK as follows T3MH T3XCLK TMR3H Clock Source T3ML T3XCLK TMR3L Clock Source 0 0 SYSCLK 12 0 0 SYSCLK 12 0 1 External Clock 8 0 1 External Clock 8 1 X SYSCLK 1 X SYSCLK The TF3H bit is set when TMR3H overflows from OxFF to 0x00 the bit is set when TMR3L overflows from OxFF to 0x00 When Timer 3 interrupts are enabled an interrupt is generated each time TMR3H over flows If Timer
109. to the four upper bits of SMBOCN MASTER TXMODE STA and STO Note that the shown response options are only the typical responses application specific procedures are allowed as long as they conform to the SMBus specification Highlighted responses are allowed but do not conform to the SMBus specification 208 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 17 4 SMBus Status Decoding Values Read Mode Status Vector ACKRQ Current SMbus State Typical Response Options STA Values Written STo ACK o ARBLOST ACK 1110 A master START was generated Load slave address R W into SMBODAT A master data or address byte was transmitted NACK received Set STA to restart transfer Abort transfer 1100 Master Transmitter A master data or address byte was transmitted ACK received Load next data byte into SMBODAT End transfer with STOP End transfer with STOP and start another transfer Send repeated START o X xx x Switch to Master Receiver Mode clear SI without writ ing new data to SMBODAT 1000 110 Master Receiver A master data byte was received ACK requested Acknowledge received byte Read SMBODAT Send NACK to indicate last byte and send STOP Send NACK to indicate last byte and send STOP fol lowed by START Send ACK followed by r
110. to the operation of the PCA R W SFR Definition 22 1 PCAOCN PCA Control R W R W R W R W R W R W R W Reset Value CF CR CCF4 CCF2 CCF1 CCFO 00000000 Bit7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address bit addressable OxD8 CF PCA Counter Timer Overflow Flag Set by hardware when the PCA Counter Timer overflows from OxFFFF to 0x0000 When the Counter Timer Overflow CF interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software CR PCA Counter Timer Run Control This bit enables disables the PCA Counter Timer 0 PCA Counter Timer disabled 1 PCA Counter Timer enabled UNUSED Read 0b Write don t care CCF4 PCA Module 4 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF4 interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared by software CCF3 PCA Module 3 Capture Compare Flag This bit is set by hardware when a match or capture occurs When the CCF3 interrupt is enabled setting this bit causes the CPU to vector to the PCA interrupt service routine This bit is not automatically cleared by hardware and must be cleared
111. use under software control Bito PARITY Parity Flag This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even SFR Definition 9 5 ACC Accumulator R W R W R W R W R W R W R W R W Reset Value ACC 7 ACC 6 ACC 5 ACC 4 ACC 3 ACC 2 ACC 1 ACC O 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address bit addressable OxEO Bits7 0 ACC Accumulator This register is the accumulator for arithmetic operations 86 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 9 6 B B Register R W R W R W R W R W R W R W R W Reset Value B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address bit addressable OxFO Bits7 0 B B Register This register serves as a second accumulator for certain arithmetic operations 9 3 Interrupt Handler The CIP 51 includes an extended interrupt system supporting multiple interrupt sources with two priority levels The allocation of interrupt sources between on chip peripherals and external inputs pins varies according to the specific version of the device Each interrupt source has one or more associated inter rupt pending flag s located in an SFR When a peripheral or external source meets a valid interrupt condi tion the associated interrupt pending flag is set to logic 1 If interrupts are enabled for
112. 0 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bit Bito USB Address 0x0C Bits7 0 Frame Number Low This register contains bits7 0 of the last received frame number USB Register Definition 16 10 FRAMEH USBO Frame Number High R R R R R R R R Reset Value Frame Number High 00000000 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bit Bito USB Address 0x0D Bits7 3 Unused Read 0 Write don t care Bits2 0 Frame Number High Byte This register contains bits10 8 of the last received frame number 16 8 Interrupts The read only USBO interrupt flags are located in the USB registers shown in USB Register Definition 16 11 through USB Register Definition 16 13 The associated interrupt enable bits are located in the USB registers shown in USB Register Definition 16 14 through USB Register Definition 16 16 A USBO interrupt is generated when any of the USB interrupt flags is set to 1 The USBO interrupt is enabled via the EIE1 SFR see Section 9 3 Interrupt Handler on page 87 Important Note Reading a USB interrupt flag register resets all flags in that register to 0 176 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 USB Register Definition 16 11 IN1INT USBO IN Endpoint Interrupt R R R R R R R 2 Reset Value 00000000 Bit7 Bits7 4 Bit3 Bit2 Bit Bito USB Address 0x02 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Unu
113. 0 USB Register Definition 16 24 EOUTCNTH USBO OUT Endpoint Count High 190 SFR Definition 17 1 SMBOCF SMBus Clock Configuration 200 SFR Definition 17 2 SMBOCN SMBus Control 202 SFR Definition 17 3 SMBODAT SMBus Data 204 SFR Definition 18 1 SCONO Serial Port 0 Control 216 SFR Definition 18 2 SBUFO Serial UARTO Port Data Buffer 217 SFR Definition 19 1 SCON1 UART1 Control 224 SFR Definition 19 2 SMOD1 UART1 Mode 225 SFR Definition 19 3 SBUF1 UARTI Data Buffer 226 SFR Definition 19 4 SBCON1 UART1 Baud Rate Generator Control 226 SFR Definition 19 5 SBRLH1 UART1 Baud Rate Generator High Byte 227 SFR Definition 19 6 SBRLL1 UART1 Baud Rate Generator Low Byte 227 SFR Definition 20 1 SPIOCFG SPIO Configuration 236 SFR Definition 20 2 SPIOCN SPIO Control 237 SFR Definition 20 3 SPIOCKR SPIO Clock Rate 238 SFR Definition 20 4 SPIODAT SPIO Data 238 SFR Definition 21 1 TCON Timer Control eee 247 SFR Definition 21 2 TMOD Timer Mode 248 SFR Definition 21 3 CKCON Clock Control 249 SF
114. 0 in register ADCOCN Conversions may be initiated by one of the fol lowing Writing a 1 to the ADOBUSY bit of register ADCOCN A Timer 0 overflow i e timed continuous conversions A Timer 2 overflow A Timer 1 overflow A rising edge on the CNVSTR input signal A Timer 3 overflow Writing a 1 to ADOBUSY provides software control of ADCO whereby conversions are performed on demand During conversion the ADOBUSY bit is set to logic 1 and reset to logic 0 when the conver sion is complete The falling edge of ADOBUSY triggers an interrupt when enabled and sets the ADCO interrupt flag ADOINT Note When polling for ADC conversion completions the ADCO interrupt flag ADOINT should be used Converted data is available in the ADCO data registers ADCOH ADCOL when bit ADOINT is logic 1 Note that when Timer 2 or Timer 3 overflows are used as the conversion source Low Byte overflows are used if Timer 2 3 is in 8 bit mode High byte overflows are used if Timer 2 8 is in 16 bit mode See Section 21 Timers on page 243 for timer configuration Important Note About Using CNVSTR The CNVSTR input pin also functions as a Port pin When the CNVSTR input is used as the ADCO conversion source the associated Port pin should be skipped by the Digital Crossbar To configure the Crossbar to skip a pin set the corresponding bit in the PnSKIP register to 1 See Section 15 Port Input Output on page 147 for details on P
115. 0 transition of the NSS signal disables the master function of SPIO so that multiple master devices can be used on the same SPI bus 3 NSSMDI1 0 1x 4 Wire Master Mode SPIO operates in 4 wire mode and NSS is enabled as an output The setting of NSSMDO determines what logic level the NSS pin will output This configuration should only be used when operating SPIO as a master device See Figure 20 2 Figure 20 3 and Figure 20 4 for typical connection diagrams of the various operational modes Note that the setting of NSSMD bits affects the pinout of the device When in 3 wire master or 3 wire slave mode the NSS pin will not be mapped by the crossbar In all other modes the NSS signal will be mapped to a pin on the device See Section 15 Port Input Output on page 147 for general purpose port O and crossbar information 230 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 20 2 SPIO Master Mode Operation A SPI master device initiates all data transfers on a SPI bus SPIO is placed in master mode by setting the Master Enable flag MSTEN SPIOCN 6 Writing a byte of data to the SPIO data register SPIODAT when in master mode writes to the transmit buffer If the SPI shift register is empty the byte in the transmit buffer is moved to the shift register and a data transfer begins The SPIO master immediately shifts out the data serially on the MOSI line while providing the serial clock on SCK The SPIF SPIOCN 7 fla
116. 00 D1 7 00 a e 0 80 9 00 32 E1 7 00 PIN 1 IDENTIFIER 1 A2 AJ pi A 1 A1 b e SILICON LABORATORIES Figure 4 4 LQFP 32 Package Diagram Rev 0 5 39 C8051F340 1 2 3 4 5 6 7 NOTES 40 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 5 10 Bit ADC ADCO The ADCO subsystem for the C8051F340 1 2 3 4 5 6 7 consists of two analog multiplexers referred to col lectively as AMUXO and a 200 ksps 10 bit successive approximation register ADC with integrated track and hold and programmable window detector The AMUXO data conversion modes and window detector are all configured under software control via the Special Function Registers shown in Figure 5 1 ADCO operates in both Single ended and Differential modes and may be configured to measure voltages at port pins the Temperature Sensor output or Vpp with respect to a port pin VREF or GND The connec tion options for AMUXO are detailed in SFR Definition 5 1 and SFR Definition 5 2 The ADCO subsystem is enabled only when the ADOEN bit in the ADCO Control register ADCOCN is set to logic 1 The ADCO sub system is in low power shutdown when this bit is logic 0 AMXOP
117. 13 5 Multiplexed and Non multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non multiplexed mode depending on the state of the EMD2 EMIOCF 4 bit 13 5 1 Multiplexed Configuration In Multiplexed mode the Data Bus and the lower 8 bits of the Address Bus share the same Port pins AD 7 0 In this mode an external latch 74HC373 or equivalent logic gate is used to hold the lower 8 bits of the RAM address The external latch is controlled by the ALE Address Latch Enable signal which is driven by the External Memory Interface logic An example of a Multiplexed Configuration is shown in Figure 13 2 In Multiplexed mode the external MOVX operation can be broken into two phases delineated by the state of the ALE signal During the first phase ALE is high and the lower 8 bits of the Address Bus are pre sented to AD 7 0 During this phase the address latch is configured such that the Q outputs reflect the states of the D inputs When ALE falls signaling the beginning of the second phase the address latch outputs remain fixed and are no longer dependent on the latch inputs Later in the second phase the Data Bus controls the state of the AD 7 0 port at the time RD or WR is asserted See Section 13 7 2 Multiplexed Mode on page 130 for more information Figure 13 2 Multiplexed Configuration Example 122 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7
118. 23 d TIR CONG TG Y N ESO IE 4 PSO TF2H TMR2CN 7 Timer 2 Overflow 0x002B 5 TF2L TMR2CN 6 Y 2 5 PT2 IP 5 SPIF SPIOCN 7 WCOL SPIOCN 6 ESPIO PSPIO ero 0085 6 MODF SPIOCN 5 Y IP 6 RXOVRN SPIOCN 4 ESMBO PSMBO SMBO 0x003B 7 SI SMBOCN 0 NERIO EUSBO USBO 0x0043 8 Special N N EIET 1 EIP1 1 ADCO Window ADOWINT EWADCO PWADCO Compare 9 0049 9 ADCOCN 3 Y N l E2 1 2 ADCO Conversion EADCO PADCO 2 0x0053 10 ADOINT ADCOCN S Y N gies Programmable Counter CF PCAOCN 7 EPCAO 0x005B 11 locen pcaocn n Y EIEf 4 4 CPOFIF CPTOCN 4 ECPO PCPO Comparatorg 0x0063 12 l oPoRIF CPTOCN 5 N M 15 5 CPIFIF CPTICN 4 ECP PCP1 comparator 0x006B 13 CP4RIF CPT1CN 5 N N 16 1 6 TMR3CN 7 PT3 0x0073 14 6 EIEL 7 7 EVBUS PVBUS VBUS Level 0x007B 15 N A NA eie EIP2 0 SCONT 0 ESI PSI 2008 N 21 EIP2 1 9 3 5 Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below Refer to the datasheet section associated with a particular on chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt pending flag s
119. 25 ms as a timeout condition Devices that have detected the timeout condition must reset the communi cation no later than 10 ms after detecting the timeout condition When the SMBTOE bit in SMBOCF is set Timer 3 is used to detect SCL low timeouts Timer 3 is forced to reload when SCL is high and allowed to count when SCL is low With Timer 3 enabled and configured to overflow after 25 ms and SMBTOE set the Timer 3 interrupt service routine can be used to reset disable and re enable the SMBus in the event of an SCL low timeout 17 3 4 SCL High SMBus Free Timeout The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 us the bus is designated as free When the SMBFTE bit in SMBOCF is set the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods If the SMBus is waiting to generate a Master START the START will be generated following this timeout Note that a clock source is required for free timeout detection even in a slave only implementation 17 4 Using the SMBus The SMBus can operate in both Master and Slave modes The interface provides timing and shifting con trol for serial transfers higher level protocol is determined by user software The SMBus interface provides the following application independent features Byte wise serial data transfers e Clock signal generation SCL Master Mode only and SDA data synchronization e Timeout
120. 3 interrupts are enabled and TF3LEN TMR3CN 5 is set an interrupt is generated each time either TMR3L or TMRSH overflows When TFSLEN is enabled software must check the TF3H and flags to determine the source of the Timer interrupt The TF3H and interrupt flags are not cleared by hardware and must be manually cleared by software T3XCLK SYSCLK 12 m gt ADC External Clock 8 Interrupt TMR3CN vv SYSCLK TCLK TMRSL HERI Figure 21 9 Timer 3 8 Bit Mode Block Diagram 258 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 21 3 3 USB Start of Frame Capture When T3CE 1 Timer 3 will operate in one of two special capture modes The capture event can be selected between a USB Start of Frame SOF capture and a Low Frequency Oscillator LFO Rising Edge capture using the T3CSS bit The USB SOF capture mode can be used to calibrate the system clock or external oscillator against the known USB host SOF clock The LFO rising edge capture mode can be used to calibrate the internal Low Frequency Oscillator against the internal High Frequency Oscillator or an external clock source When T3SPLIT Timer 3 counts up and overflows from OxFFFF to 0x0000 Each time a capture event is received the contents of the Timer registers TMRSH TMR3L are latched into the Timer Reload registers TMR3RLH TMR
121. 3RLL A Timer interrupt is generated if enabled X C CKCON L T T TITITITIS S 3 3 2 2 1 o c C H L H L lalo 0 SYSCLK 12 J The TAK TMR3L TMR3H To ADC External Clock 8 SYSCLK USB Start of Frame SOF Capture gt TMR3RLL TMRSRLH Low Frequency Oscillator Falling Edge dis Enable Interrupt Figure 21 10 Timer 3 Capture Mode T3SPLIT 0 s Rev 0 5 259 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 When T3SPLIT 1 the Timer 3 registers TMR3H and TMR3L act as two 8 bit counters Each counter counts up independently and overflows from OxFF to 0x00 Each time a capture event is received the con tents of the Timer registers are latched into the Timer Reload registers TMRSRLH and TMRS3RLL Timer 3 interrupt is generated if enabled Troma Capture Enable Interrupt SYSCLK 12 External Clock 8 I To ADC Capture USB Start of Frame SOF Low Frequency Oscillator 1 Falling Edge T3CSS Figure 21 11 Timer 3 Capture Mode T3SPLIT 1 260 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 21 13 TMR3CN Timer 3 Control R W R W R W R W R W R W R W R W Reset Value
122. 4 INOPL Figure 21 1 TO Mode 0 Block Diagram 21 1 2 Mode 1 16 bit Counter Timer Mode 1 operation is the same as Mode 0 except that the counter timer registers use all 16 bits The counter timers are enabled and configured in Mode 1 in the same manner as for Mode 0 244 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 21 1 3 Mode 2 8 bit Counter Timer with Auto Reload Mode 2 configures Timer 0 and Timer 1 to operate as 8 bit counter timers with automatic reload of the start value TLO holds the count and THO holds the reload value When the counter in TLO overflows from all ones to 0x00 the timer overflow flag TFO TCON 5 is set and the counter in TLO is reloaded from THO If Timer 0 interrupts are enabled an interrupt will occur when the TFO flag is set The reload value in THO is not changed TLO must be initialized to the desired value before enabling the timer for the first count to be correct When in Mode 2 Timer 1 operates identically to Timer 0 Both counter timers are enabled and configured in Mode 2 in the same manner as Mode 0 Setting the TRO bit TCON 4 enables the timer when either GATEO TMOD 3 is logic 0 or when the input signal INTO is active as defined by bit INOPL in register INTO1CF see Section 9 3 2 External Interrupts on page 87 for details on the external input signals INTO and INT1 Pre scaled Clock 0 SYSCLK Interrupt Cro
123. 4 5 6 7 13 7 2 Multiplexed Mode 13 7 2 1 16 bit MOVX EMIOCF 4 2 001 010 or 011 Muxed 16 bit WRITE ADDR 15 8 AD 7 0 ALE P1 3 P1 3 4 1 6 Twn i lacs gt lt TACW Tch gt WR 1 7 1 7 RD P1 6 1 6 Muxed 16 bit READ ADDR 15 8 AD 7 0 ALE X gt o gt z v gt I y LoT T T AD Pte P16 WR PU Figure 13 8 Multiplexed 16 bit MOVX Timing 130 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 13 7 2 2 8 bit MOVX without Bank Select EMIOCF 4 2 4001 or 011 Muxed 8 bit WRITE Without Bank Select ADDR 15 8 P3 AD 7 0 ALE B T Y T MR P17 P17 AD Pie P16 Muxed 8 bit READ Without Bank Select ADDR 15 8 P3 AD 7 0 ALE RD WR M7 Y a7 Figure 13 9 Multiplexed 8 bit MOVX without Bank Select Timing s Rev 0 5 131 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 13 7 2 3 8 bit MOVX with Bank Select EMIOCF 4 2 010 Muxed 8 bit WRITE with Bank Select ADDR 15 8 AD 7 0 ALE P1 3 Muxed 8 bit READ with Bank Select ADDR 15 8 AD 7 0 AE m3 gt gt v o TI Y RD 1 6 P1
124. 40 v v IY Y 2 TQFPA8 8051 342 90 48 64k 4352 V v v v v v C8051F343 GQ 48 32k 2304 v v v v v v C8051F344 GQ 25 64k 4352 v v v v v 2 4 v 40O v v IY Y 2 TQFPA8 C8051F345 GQ 25 32k 2304 v v v v v v 2 4 v 40 v v IY 2 TQFPA8 C8051F346 GQ 25 64k 4352 v C8051F347 GQ 25 32k 2304 v Rev 0 5 18 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 C2D Port I O Configuration Debug Programming 3 Hardware RE 54 P0 0 C2CK RST Digital Peripherals Ba 04 Po Reset Ee _ UARTO 0 51 8051 UART nyers Bq Po 5 Dx P0 6 XTAL1 Power On Controller Core M PO 7 XTAL2 Reset Timers 0 1 04 m 64 32k Byte ISP FLASH 2 3 Priority pi Supply Program Memory Crossbar gt on Ed Pi 4CNVSTR Monitor Decoder rivers M PCA WDT zl 256 Byte RAM Y SMBus Voltage SPI Port 2 VREG Regulator 4 2k Byte XRAM Drivers Crossbar Control GND 7 SFR System Clock Setup 1 Bus External Memory Port 3 External Interface Pl A Drivers a Oscillator Clock Control X 6 i M pop Multiplier Address 2 EM Oscillato
125. 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 13 3 EMIOTC External Memory Timing Control R W R W R W R W R W R W R W R W Reset Value EAS1 EASO ERW3 EWR2 EWR1 EWRO EAH1 EAHO 11111111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0x84 Bits7 6 51 0 EMIF Address Setup Time Bits 00 Address setup time 0 SYSCLK cycles 01 Address setup time 1 SYSCLK cycle 10 Address setup time 2 SYSCLK cycles 11 Address setup time 3 SYSCLK cycles Bits5 2 EWR3 0 EMIF WR and RD Pulse Width Control Bits 0000 WR and RD pulse width 1 SYSCLK cycle 0001 WR and RD pulse width 2 SYSCLK cycles 0010 WR and RD pulse width 3 SYSCLK cycles 0011 WR and RD pulse width 4 SYSCLK cycles 0100 WR and RD pulse width 5 SYSCLK cycles 0101 WR and RD pulse width 6 SYSCLK cycles 0110 WR and RD pulse width 7 SYSCLK cycles 0111 WR and RD pulse width 8 SYSCLK cycles 1000 WR and RD pulse width 9 SYSCLK cycles 1001 WR and RD pulse width 10 SYSCLK cycles 1010 WR and RD pulse width 11 SYSCLK cycles 1011 WR and RD pulse width 12 SYSCLK cycles 1100 WR and RD pulse width 13 SYSCLK cycles 1101 WR and RD pulse width 14 SYSCLK cycles 1110 WR and RD pulse width 15 SYSCLK cycles 1111 WR and RD pulse width 16 SYSCLK cycles Bits1 0 EAH1 0 EMIF Address Hold Time Bits 00 Address hold time 0 SYSCLK cycles 01 Address hold time 1 SYSCLK cy
126. 6 Bit5 Bit4 Bito SFR Address 0 06 57 0 P2SKIP 7 0 Port2 Crossbar Skip Enable Bits These bits select Port pins to be skipped by the Crossbar Decoder Port pins used as ana log inputs for ADC or Comparator or used as special functions VREF input external oscil lator circuit CNVSTR input should be skipped by the Crossbar 0 Corresponding P2 n pin is not skipped by the Crossbar 1 Corresponding P2 n pin is skipped by the Crossbar 158 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 15 16 P3 Port3 Latch R W R W R W Reset Value P3 4 P3 1 P3 0 11111111 Bit4 Bit1 Bito SFR Address bit addressable 0xBO Bits7 0 P3 7 0 Write Output appears I O pins 0 Logic Low Output 1 Logic High Output high impedance if corresponding PSMDOUT n bit 0 Read Always reads 0 if selected as analog input in register PSMDIN Directly reads Port pin when configured as digital input 0 P3 n pin is logic low 1 pin is logic high Note P3 1 3 7 are only available on 48 pin devices SFR Definition 15 17 P3MDIN Port3 Input Mode R W R W R W R W R W R W R W Reset Value 11111111 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address OxF4 Bits7 0 Analog Input Configuration Bits for P3 7 P3 0 respectively Port pins configured as analog inputs have t
127. 6 clock cycles to execute the RETI 8 clock cycles to complete the DIV instruction and 5 clock cycles to execute the LCALL to the ISR If the CPU is executing an ISR for an interrupt with equal or higher priority the new interrupt will not be serviced until the current ISR completes including the RETI and following instruction Note that the CPU is stalled during Flash write erase operations and USB FIFO MOVX accesses see Section 13 2 Accessing USB FIFO Space on page 118 Interrupt service latency will be increased for interrupts occurring while the CPU is stalled The latency for these situations will be determined by the standard interrupt service procedure as described above and the amount of time the CPU is stalled 88 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 9 4 Interrupt Summary S F Interrupt Priority 9 g Enable Priority Interrupt Source Vector Order Pending Flag Flag Control ME amp o Reset 0x0000 Top N A NIA p Enabled Rong Interrupt O 9x0003 o IEO TCON 1 Y Y EXO IE 0 PXO IP O Timer 0 Overflow 0x000B i TFO0 TCONS Y Y ETO PTO nen interrupt 1 x0b13 2 IEt TCON 3 Y Y EX1 IE 2 PX1 IP 2 Timer 1 Overflow 0x001B 3 TCON 7 Y Y ET PT1 RIO SCONO 0 UARTO 0x00
128. 7 and there is an open FIFO packet slot 3 If the endpoint is in Isochronous Mode ISO 1 and ISOUD 1 INPRDY will read 0 until the next SOF is received An interrupt if enabled will be generated when hardware clears INPRDY as a result of a packet being transmitted 186 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 USB Register Definition 16 20 EINCSRH USBO IN Endpoint Control High Byte R W R W R W R R W R W R R Reset Value DBIEN ISO DIRSEL FCDT SPLIT 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito USB Address 0x12 Bit7 DBIEN IN Endpoint Double buffer Enable 0 Double buffering disabled for the selected IN endpoint 1 Double buffering enabled for the selected IN endpoint Bit6 ISO Isochronous Transfer Enable This bit enables disables isochronous transfers on the current endpoint 0 Endpoint configured for bulk interrupt transfers 1 Endpoint configured for isochronous transfers Bit5 DIRSEL Endpoint Direction Select This bit is valid only when the selected FIFO is not split SPLIT 0 0 Endpoint direction selected as OUT 1 Endpoint direction selected as IN Bit4 Unused Read 0 Write don t care Bit3 FCDT Force Data Toggle 0 Endpoint data toggle switches only when an ACK is received following a data packet transmission 1 Endpoint data toggle forced to switch after every data packet is transmitted regardless of ACK reception Bit2 SPLIT F
129. 9 1 SYSCLK 7 1 1 65536 SBRLHI SBRLL1 2 Prescaler Equation 19 1 UART1 Baud Rate A quick reference for typical baud rates and system clock frequencies is given in Table 19 1 Baud Rate Table 19 1 Baud Rate Generator Settings for Standard Baud Rates Target Baud Actual Baud Baud Rate Oscillator B1PS 1 0 Reload Value in Rate bps Rate bps Error Divide Prescaler Bits SBRLH1 SBRLL1 Factor 230400 230769 OxFFE6 115200 115385 OxFFCC 57600 57692 OxFF98 28800 28846 0xFF30 14400 14388 OxFESF 9600 9600 OxFD8F 2400 2400 OxF63C 1200 1200 OxEC78 230400 230769 115200 115385 OxFF98 57600 57692 0xFF30 28800 28777 OxFESF 14400 14406 OxFCBF 9600 9600 1 2400 2400 0xEC78 1200 1200 5 OxD8FO 230400 230769 169 OxFF98 115200 115385 57600 57554 OxFESF 28800 28812 OxFCBF 14400 14397 OxF97D 9600 9600 OxF63C 2400 2400 i OxD8FO 1200 1200 0xB1E0 220 Rev 0 5 e SILICON LABORATORIES SYSCLK 12 MHz N I gt S N SYSCLK 48 MHz SYSCLK C8051F340 1 2 3 4 5 6 7 19 2 Data Format UART1 has a number of available options for data formatting Data transfers begin with a start bit logic low followed by the data bits sent LSB first a parity or extra bit if selected and end with one or two stop bits logic high The data length is variable between 5 and 8
130. ADOWINT interrupt will be generated if the ADCO conversion word is outside of the range defined by the ADCOGT and ADCOLT registers if ADCOH ADCOL lt OxFFFF 1d or ADCOH ADCOL gt 0x0040 64d Figure 5 9 shows an example using left justified data with equivalent ADCOGT and ADCOLT register set tings ADCOH ADCOL ADCOH ADCOL Input Voltage Input Voltage Px x Px x Px x Px x VREF x 511 512 0x01FF VREF x 511 512 ADOWINT not affected ADOWINT I 0x0041 VREF x 64 512 0x0040 ADCOLTH ADCOLTL VREF x 64 512 0x0040 4 ADCOGTH ADCOGTL oor 2 2 2 0x003F ADOWINT 1 ADOWINT 0x0000 not affected VREF x 1 512 OxFFFF I ADCOGTH ADCOGTL VREF x 1 512 OxFFFF 4 ADCOLTH ADCOLTL OxFFFE ADOWINT ADOWINT 1 not affected VREF 0x0200 Figure 5 8 ADC Window Compare Example Right Justified Differential Data ADCOH ADCOL ADCOH ADCOL Input Voltage Input Voltage Px x Px x Px x Px y VREF x 511 512 Ox7FCO VREF x 511 512 ADOWINT not affected ADOWINT 1 0x1040 VREF x 64 512 0x1000 I ADCOLTH ADCOLTL VREF x 64 512 0x1000 I ADCOGTH ADCOGTL 7 Lay _ O S S S IU ADOWINT 1 ADOWINT 0x0000 not affected VREF x 1 512 OxFFCO 4 ADCOGTH ADCOGTL VREF x 1 512 OxFFCO ADCOLTH ADCOLTL OxFF80
131. C 4 OSCXCN CLKMUL e S g I I m 5 Figure 14 1 Oscillator Diagram s Rev 0 5 135 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 14 1 Programmable Internal High Frequency H F Oscillator All C8051F340 1 2 3 4 5 6 7 devices include a programmable internal oscillator that defaults as the system clock after a system reset The internal oscillator period can be programmed via the OSCICL register shown in SFR Definition 14 2 The OSCICL register is factory calibrated to obtain a 12 MHz internal oscil lator frequency Electrical specifications for the precision internal oscillator are given in Table 14 1 on page 145 Note that the system clock may be derived from the programmed internal oscillator divided by 1 2 4 or 8 as defined by the IFCN bits in register OSCICN The divide value defaults to 8 following a reset 14 1 1 Internal H F Oscillator Suspend Mode The internal high frequency oscillator may be placed in Suspend mode by writing 1 to the SUSPEND bit in register OSCICN In Suspend mode the internal H F oscillator is stopped until a non idle USB event is detected Section 16 or VBUS matches the polarity selected by the VBPOL bit in register REGOCN Sec tion 8 2 Note that the USB transceiver can still detect USB events when it is disabled SFR Definition 14 1 OSCICN Internal H F Oscillator Control R W R R W R R W R W R W R W Reset Value IOSCEN IFRDY
132. CON LABORATORIES C8051F340 1 2 3 4 5 6 7 SCK i i i i i i i i CKPOL 0 0 aii LI SCK j CKPOL 1 0 LI LI it LI MOSI MISO mua y mz y X Bo X NSS 4 Wire Mode Figure 20 6 Slave Mode Data Clock Timing CKPHA 0 SCK CKPOL 0 CKPHA 1 CKPOL 1 CKPHA 1 l i i i MOSI MISO NSS 4 Wire Mode Figure 20 7 Slave Mode Data Clock Timing CKPHA 1 s Rev 0 5 235 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 20 6 SPI Special Function Registers SPIO is accessed and controlled through four special function registers in the system controller SPIOCN Control Register SPIODAT Data Register SPIOCFG Configuration Register and SPIOCKR Clock Rate Register The four special function registers related to the operation of the SPIO Bus are described in the following figures SFR Detinition 20 1 SPIOCFG SPIO Configuration R R W R W R W R R R R Reset Value SPIBSY MSTEN CKPHA CKPOL SLVSEL NSSIN SRMT RXBMT 00000111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0xA1 Bit 7 SPIBSY SPI Busy read only This bit is set to logic 1 when a SPI transfer is in progress Master or slave Mode Bit 6 MSTEN Master Mode Enable 0 Disable master mode Operate in slave mode 1 Enable master mode Operate as a master Bit 5 C
133. D O2 OD HlSlololalziale 55562206 NN E SPI CONTROL LOGIC SPI IRQ Data Path Pin Interface Control Control Tx Data MOSI gt ZON Y SPIODAT SCK R Transmit Data Buffer 1 1 Pin IS Control 5 Port I O Shift Register Logic MI 7 6 5 4 3 2 10 4 ee A UR Receive Data Buffer NSS ZN Read L vt otitis 2 SFRBus Figure 20 1 SPI Block Diagram s Rev 0 5 229 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 20 1 Signal Descriptions The four signals used by SPIO MOSI MISO SCK NSS are described below 20 1 1 Master Out Slave In MOSI The master out slave in MOSI signal is an output from a master device and an input to slave devices It is used to serially transfer data from the master to the slave This signal is an output when SPIO is operat ing as a master and an input when SPIO is operating as a slave Data is transferred most significant bit first When configured as a master MOSI is driven by the MSB of the shift register in both 3 and 4 wire mode 20 1 2 Master In Slave Out MISO The master in slave out MISO signal is an output from a slave device and an input to the master device It is used to serially transfer data from the slave to the master This signal is an input when SPIO is operat ing as a master and an output when SPIO is operating as a slave Da
134. DCOCN ADCO Control R W R W R W R W R W R W R W Reset Value ADOTM ADOINT ADOBUSY ADOWINT ADOCM2 ADOCM1 ADOCMO 00000000 Bit6 Bit5 Bit4 Bit3 Bit2 Bit SFR Address bit addressable OxE8 ADOEN ADCO Enable Bit 0 ADCO Disabled ADCO is in low power shutdown 1 ADCO Enabled ADCO is active and ready for data conversions ADOTM ADCO Track Mode Bit 0 Normal Track Mode When ADCO is enabled tracking is continuous unless a conversion is in progress 1 Low power Track Mode Tracking Defined by ADOCM2 0 bits see below ADOINT ADCO Conversion Complete Interrupt Flag 0 ADCO has not completed a data conversion since the last time ADOINT was cleared 1 ADCO has completed a data conversion ADOBUSY ADCO Busy Bit Read 0 ADCO conversion is complete or a conversion is not currently in progress ADOINT is set to logic 1 on the falling edge of ADOBUSY 1 ADCO conversion is in progress Write 0 No Effect 1 Initiates ADCO Conversion if ADOCM2 0 000b ADOWINT ADCO Window Compare Interrupt Flag 0 ADCO Window Comparison Data match has not occurred since this flag was last cleared 1 ADCO Window Comparison Data match has occurred ADOCM2 0 ADCO Start of Conversion Mode Select When ADOTM 0 000 ADCO conversion initiated on every write of 1 to ADOBUSY 001 ADCO conversion initiated on overflow of Timer 0 010 ADCO conversion initiated on overflow of Timer 2
135. DOSC2 ADOSCI ADOSCO ADOLJST 11111000 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bito SFR Address OxBC Bits7 3 ADOSC4 0 ADCO SAR Conversion Clock Period Bits SAR Conversion clock is derived from system clock by the following equation where ADOSC refers to the 5 bit value held in bits ADOSC4 0 SAR Conversion clock requirements are given in Table 5 1 ADOSC 1 CLK AR Bit2 ADOLJST ADCO Left Justify Select 0 Data in ADCOH ADCOL registers are right justified 1 Data in ADCOH ADCOL registers are left justified Bits1 0 UNUSED Read 00b Write don t care SFR Definition 5 4 ADCOH ADCO Data Word MSB R W R W R W R W R W R W R W Reset Value 00000000 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address OxBE Bits7 0 ADCO Data Word High Order Bits For ADOLJST 0 Bits 7 2 are the sign extension of Bit1 Bits 1 0 are the upper 2 bits of the 10 bit ADCO Data Word For ADOLJST 1 Bits 7 0 are the most significant bits of the 10 bit ADCO Data Word SFR Definition 5 5 ADCOL ADCO Data Word LSB R W R W Reset Value 00000000 Bit1 Bito SFR Address OxBD Bits7 0 ADCO Data Word Low Order Bits For ADOLJST 0 Bits 7 0 are the lower 8 bits of the 10 bit Data Word For ADOLJST 1 Bits 7 6 are the lower 2 bits of the 10 bit Data Word Bits 5 0 will always read 0 50 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 5 6 A
136. ES C8051F340 1 2 3 4 5 6 7 21 2 2 8 bit Timers with Auto Reload When T2SPLIT 1 and T2CE 0 Timer 2 operates as two 8 bit timers TMR2H and TMR2L Both 8 bit timers operate in auto reload mode as shown in Figure 21 5 TMR2RLL holds the reload value for TMR2L TMR2RLH holds the reload value for TMR2H The TR2 bit in TMR2CN handles the run control for TMR2H TMR2L is always running when configured for 8 bit Mode Each 8 bit timer may be configured to use SYSCLK SYSCLK divided by 12 or the external oscillator clock source divided by 8 The Timer 2 Clock Select bits T2MH and T2ML in CKCON select either SYSCLK or the clock defined by the Timer 2 External Clock Select bit T2XCLK in TMR2CN as follows T2MH T2XCLK TMR2H Clock Source T2ML T2XCLK TMR2L Clock Source 0 0 SYSCLK 12 0 0 SYSCLK 12 0 1 External Clock 8 0 1 External Clock 8 1 X SYSCLK 1 X SYSCLK The TF2H bit is set when TMR2H overflows from OxFF to 0x00 the TF2L bit is set when TMR2L overflows from OxFF to 0x00 When Timer 2 interrupts are enabled an interrupt is generated each time TMR2H over flows If Timer 2 interrupts are enabled and TF2LEN TMR2ON 5 is set an interrupt is generated each time either TMR2L or TMR2H overflows When TF2LEN is enabled software must check the TF2H and TF2L flags to determine the source of the Timer 2 interrupt The TF2H and TF2L interrupt flags are not cleared by hardware
137. FR Definition 9 4 PSW Program Status Word R W R W R W R W R W R W R W R Reset Value CY AC FO RS1 RSO OV F1 PARITY 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit SFR Address bit addressable OxDO Bit7 CY Carry Flag This bit is set when the last arithmetic operation resulted in a carry addition or a borrow subtraction It is cleared to logic 0 by all other arithmetic operations Bit6 AC Auxiliary Carry Flag This bit is set when the last arithmetic operation resulted in a carry into addition or a borrow from subtraction the high order nibble It is cleared to logic 0 by all other arithmetic operations Bit5 FO User Flag 0 This is a bit addressable general purpose flag for use under software control Bits4 3 RS1 RSO Register Bank Select These bits select which register bank is used during register accesses RS1 RSO Register Bank Address 0 0 0 0x00 0x07 0 1 1 0x08 OxOF 1 0 2 0x10 0x17 1 1 3 0x18 0x1F Bit2 OV Overflow Flag This bit is set to 1 under the following circumstances An ADD ADDC or SUBB instruction causes a sign change overflow AMUL instruction results in an overflow result is greater than 255 A DIV instruction causes a divide by zero condition The OV bit is cleared to 0 by the ADD ADDC SUBB MUL and DIV instructions in all other cases Bit F1 User Flag 1 This is a bit addressable general purpose flag for
138. Flash Erase Procedure The Flash memory can be programmed by software using the MOVX write instruction with the address and data byte to be programmed provided as normal operands Before writing to Flash memory using MOVX Flash write operations must be enabled by 1 Writing the Flash key codes in sequence to the Flash Lock register FLKEY and 2 Setting the PSWE Program Store Write Enable bit PSCTL O to logic 1 this directs the MOVX writes to target Flash memory The PSWE bit remains set until cleared by software A write to Flash memory can clear bits to logic 0 but cannot set them only an erase operation can set bits to logic 1 in Flash A byte location to be programmed must be erased before a new value is written The Flash memory is organized in 512 byte pages The erase operation applies to an entire page setting all bytes in the page to OxFF To erase an entire 512 byte page perform the following steps Step 1 Disable interrupts recommended Step 2 Write the first key code to FLKEY OxA5 Step 3 Write the second key code to FLKEY OxF1 Step 4 Set the PSEE bit register PSCTL Step 5 Set the PSWE bit register PSCTL Step 6 Using the MOVX instruction write a data byte to any location within the 512 byte page to be erased Step 7 Clear the PSWE bit register PSCTL Step 8 Clear the PSEE bit register PSCTI e Rev 0 5 109 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 12 1 3 Flash Write Procedure
139. IFO Split Enable When SPLIT 1 the selected endpoint FIFO is split The upper half of the selected FIFO is used by the IN endpoint the lower half of the selected FIFO is used by the OUT endpoint Bits1 0 Unused Read 00b Write don t care 16 13 Controlling Endpoints1 3 OUT Endpoints1 3 OUT are managed via USB registers EOUTCSRL and EOUTCSRH All OUT endpoints can be used for Interrupt Bulk or Isochronous transfers Isochronous ISO mode is enabled by writing 1 to the ISO bit in register EOUTCSRH Bulk and Interrupt transfers are handled identically by hardware An Endpoint1 3 OUT interrupt may be generated by the following 1 Hardware sets the OPRDY bit EINCSRL 0 to 1 2 Hardware generates a STALL condition 16 13 1 Endpoints1 3 OUT Interrupt or Bulk Mode When the ISO bit EOUTCSRH 6 0 the target endpoint operates in Bulk or Interrupt mode Once an endpoint has been configured to operate in Bulk Interrupt OUT mode typically following an EndpointO SET INTERFACE command hardware will set the OPRDY bit EOUTCSRL O to 1 and generate interrupt upon reception of an OUT token and data packet The number of bytes in the current OUT data packet the packet ready to be unloaded from the FIFO is given in the EOUTCNTH and EOUTCNTL reg isters In response to this interrupt firmware should unload the data packet from the OUT FIFO and reset the OPRDY bit to 0 s Rev 0 5 187
140. KPHA SPIO Clock Phase This bit controls the SPIO clock phase 0 Data centered on first edge of SCK period 1 Data centered on second edge of SCK period Bit 4 CKPOL SPIO Clock Polarity This bit controls the SPIO clock polarity 0 SCK line low in idle state 1 SCK line high in idle state Bit 3 SLVSEL Slave Selected Flag read only This bit is set to logic 1 whenever the NSS pin is low indicating SPIO is the selected slave It is cleared to logic 0 when NSS is high slave not selected This bit does not indicate the instantaneous value at the NSS pin but rather a de glitched version of the pin input Bit 2 NSSIN NSS Instantaneous Pin Input read only This bit mimics the instantaneous value that is present on the NSS port pin at the time that the register is read This input is not de glitched Bit 1 SRMT Shift Register Empty Valid in Slave Mode read only This bit will be set to logic 1 when all data has been transferred in out of the shift register and there is no new information available to read from the transmit buffer or write to the receive buffer It returns to logic O when a data byte is transferred to the shift register from the transmit buffer or by a transition on SCK NOTE SRMT 1 when in Master Mode Bit 0 RXBMT Receive Buffer Empty Valid in Slave Mode read only This bit will be set to logic 1 when the receive buffer has been read and contains no new information If there is new information available i
141. L A Rn OR Register to A 1 1 SILICON LABORATORIES Rev 0 5 75 C8051F340 1 2 3 4 5 6 7 Table 9 1 CIP 51 Instruction Set Summary Continued e Clock Mnemonic Description Bytes Cycles ORL A direct OR direct byte to A 2 2 ORL A Ri OR indirect RAM to A 1 2 ORL A data OR immediate to A 2 2 ORL direct A OR A to direct byte 2 2 ORL direct data OR immediate to direct byte 3 3 XRL A Rn Exclusive OR Register to A 1 1 XRL A direct Exclusive OR direct byte to A 2 2 XRL A Ri Exclusive OR indirect RAM to A 1 2 XRL A data Exclusive OR immediate to A 2 2 XRL direct A Exclusive OR A to direct byte 2 2 XRL direct data Exclusive OR immediate to direct byte 3 3 CLRA Clear A 1 1 CPLA Complement A 1 1 RLA Rotate A left 1 1 RLC A Rotate A left through Carry 1 1 RRA Rotate A right 1 1 RRC A Rotate A right through Carry 1 1 SWAP A Swap nibbles of A 1 1 Data Transfer MOV A Rn Move Register to A MOV A direct Move direct byte to A MOV A Ri Move indirect RAM to A MOV A data Move immediate to A MOV Rn A Move A to Register MOV direct Move direct byte to Register MOV Rn data MOV direct A Move immediate to Register Move A to direct byte MOV direct Rn Move Register to direct byte MOV direct direct Move direct byte to direct byte MOV direct Ri Move indirect RAM to direct byte MOV direct data
142. LTL 0x003F ADOWINT ADOWINT 1 not affected 0 0x0000 Figure 5 6 ADC Window Compare Example Right Justified Single Ended Data ADCOH ADCOL ADCOH ADCOL Input Voltage Input Voltage Px x GND Px x GND VREF x 1023 1024 OxFFCO VREF x 1023 1024 ADOWINT not affected ADOWINI A 0x2040 VREF x 128 1024 0x2000 m ADCOLTH ADCOLTL VREF x 128 1024 0x2000 4 ADCOGTH ADCOGTL OdFCO ADOWINT 1 ADOWINT 0x1040 not affected VREF x 64 1024 0x1000 ADCOGTH ADCOGTL VREF x 64 1024 0x1000 I ADCOLTH ADCOLTL OxOFCO ADOWINT ADOWINT 1 not affected 0 0x0000 Figure 5 7 ADC Window Compare Example Left Justified Single Ended Data 54 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 5 4 2 Window Detector In Differential Mode Figure 5 8 shows two example window comparisons for right justified differential data with ADCOLTH ADCOLTL 0x0040 64d and ADCOGTH ADCOGTH OxFFFF 1d In differential mode the measurable voltage between the input pins is between VREF and VREF 511 512 Output codes are rep resented as 10 bit 2 s complement signed integers In the left example an ADOWINT interrupt will be gen erated if the ADCO conversion word ADCOH ADCOL is within the range defined by ADCOGTH ADCOGTL and ADCOLTH ADCOLTL if OXFFFF 1d ADCOH ADCOL 0x0040 64d In the right example an
143. MO in the Counter Timer Mode register TMOD Each timer can be configured independently Each operating mode is described below 21 1 1 Mode O0 13 bit Counter Timer Timer 0 and Timer 1 operate as 13 bit counter timers in Mode 0 The following describes the configuration and operation of Timer 0 However both timers operate identically and Timer 1 is configured in the same manner as described for Timer 0 The THO register holds the eight MSBs of the 13 bit counter timer TLO holds the five LSBs in bit positions TLO 4 TLO 0 The three upper bits of TLO TLO 7 TLO 5 are indeterminate and should be masked out or ignored when reading As the 13 bit timer register increments and overflows from Ox1FFF all ones to 0x0000 the timer overflow flag TFO TCON 5 is set and an interrupt will occur if Timer 0 interrupts are enabled s Rev 0 5 243 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 The C TO bit TMOD 2 selects the counter timer s clock source When C TO is set to logic 1 high to low transitions at the selected Timer 0 input pin TO increment the timer register Refer to Section 15 1 Priority Crossbar Decoder on page 149 for information on selecting and configuring external pins Clearing C T selects the clock defined by the TOM bit CKCON 3 When TOM is set Timer 0 is clocked by the system clock When TOM is cleared Timer 0 is clocked by the source selected by the Clock Scale bits in CKCON see SFR Definition 21 3
144. Memory udin eut DI xe ex ia Ani 109 12 1 Programming The Flash Memory siue dea ae tod ener 109 12 1 1 Flash Lock and Key 109 12 1 2 Flash Erase Procedure ce atus 109 12 1 3 Flash Write 110 12 2 Non volatile Data 0 0 111 12 9 99 Ifi crie acta ak valet a oe tue ead et 111 13 External Data Memory Interface and On Chip XRAM 117 13 T Accessind stu E aep eic celu ab n 117 13 1 1 16 Bit MOVX Examples i o a xod reet ades tts 117 13 1 2 8 Bit MOVX Example sido irte 117 13 2 Accessing USB FIFO Space ieu pee 118 13 3 Configuring the External Memory Interface 119 TEAL Port iot eo et EM Ve ir 119 13 5 Multiplexed and Non multiplexed 122 13 5 T Multiplexed ConflgUtallori 2 eio hr IRA ERE PR pince EAS 122 13 5 2 Non multiplexed 22 224 4 00000 123 13 6 Memory Mode 123 13 6 1 Internal XRAM 2 24 004400000000 124 13 6 2 Split
145. Monitor turn on time The Vpp Monitor is enabled fol lowing all POR resets 0 Vpp Monitor Disabled 1 Vpp Monitor Enabled Bit6 VppSTAT Vpp Status This bit indicates the current power supply status Vpp Monitor output 0 Vpp is at or below the Vpp monitor threshold 1 Vpp is above the Vpp monitor threshold 55 0 Reserved Read Variable Write don t care e Rev 0 5 103 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 11 3 External Reset The external RST pin provides a means for external circuitry to force the device into a reset state Assert ing an active low signal on the RST pin generates a reset an external pull up and or decoupling of the RST pin may be necessary to avoid erroneous noise induced resets See Table 11 1 for complete RST pin specifications The PINRSF flag RSTSRC 0 is set on exit from an external reset 11 4 Missing Clock Detector Reset The Missing Clock Detector MCD is a one shot circuit that is triggered by the system clock If more than 100 us pass between rising edges on the system clock the one shot will time out and generate a reset After a MCD reset the MCDRSF flag RSTSRC 2 will read 1 signifying the MCD as the reset source otherwise this bit reads 0 Writing a 1 to the MCDRSF bit enables the Missing Clock Detector writing a 0 disables it The state of the RST pin is unaffected by this reset 11 5 0 Reset Compara
146. N to determine the high byte of the effective address and RO or R1 to determine the low byte of the effective address e 16 bit MOVX operations use the contents of the 16 bit DPTR to determine the effective address 13 6 2 Split Mode without Bank Select When EMIOCF 3 2 are set to 01 the XRAM memory map is split into two areas on chip space and off chip space Effective addresses below the internal XRAM size boundary will access on chip XRAM space Effective addresses above the internal XRAM size boundary will access off chip space e 8 bit MOVX operations use the contents of EMIOCN to determine whether the memory access is on chip or off chip However in the No Bank Select mode an 8 bit MOVX operation will not drive the upper 8 bits A 15 8 of the Address Bus during an off chip access This allows the user to manipulate the upper address bits at will by setting the Port state directly via the port latches This behavior is in contrast with Split Mode with Bank Select described below The lower 8 bits of the Address Bus A 7 0 are driven determined by RO or R1 e 16 bit MOVX operations use the contents of DPTR to determine whether the memory access is on chip or off chip and unlike 8 bit MOVX operations the full 16 bits of the Address Bus A 15 0 are driven during the off chip transaction 124 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 13 6 3 Split Mode with Bank Select When EMIOCF 3 2 ar
147. N2 CMX1NO Comparator Negative Input MUX Select These bits select which Port pin is used as the Comparator1 negative input CMX1N2 CMX1N1 CMX1NO Negative Input Negative Input 32 pin Package 48 pin Package 0 0 0 P1 3 P2 3 0 0 1 P1 7 P3 1 0 1 0 P2 3 P4 0 0 1 1 P2 7 P4 6 1 0 0 PO 5 P1 2 Bit3 UNUSED Read 0b Write don t care Bits2 0 CMX1P1 CMX1PO Comparator1 Positive Input MUX Select These bits select which Port pin is used as the Comparator1 positive input CMX1P2 CMX1P1 CMX1PO Positive Input Positive Input 32 pin Package 48 pin Package 0 0 0 P1 2 P2 2 0 0 1 P1 6 P3 0 0 1 0 P2 2 P3 7 0 1 1 P2 6 P4 5 1 0 0 PO 4 P 1 1 Note that the port pins used by the comparator depend on the package type 32 pin or 48 pin 66 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 7 6 CPT1MD Comparator1 Mode Selection R W R W R W R W R W R W R W R W Reset Value CP1RIE CP1FIE CP1MD1 CP1MDO 00000010 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0x9C Bits7 6 UNUSED Read 00b Write don t care Bit5 CP1RIE Comparator1 Rising Edge Interrupt Enable 0 Comparator1 rising edge interrupt disabled 1 Comparator1 rising edge interrupt enabled Bit4 CP1FIE Comparator1 Falling Edge Interrupt Enable 0 Comparator1 falling edge interrupt disabled 1 Comparator1 falling edge int
148. O for the corresponding endpoint Reading from the FIFO address unloads data from the OUT FIFO for the corresponding endpoint 172 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 16 6 Function Addressing The FADDR register holds the current USBO function address Software should write the host assigned 7 bit function address to the FADDR register when received as part of a SET ADDRESS command A new address written to FADDR will not take effect USBO will not respond to the new address until the end of the current transfer typically following the status phase of the SET ADDRESS command transfer The UPDATE bit FADDR 7 is set to 1 by hardware when software writes a new address to the FADDR regis ter Hardware clears the UPDATE bit when the new address takes effect as described above USB Register Definition 16 7 FADDR USBO Function Address R R W R W R W R W R W R W R W Reset Value Update Function Address 00000000 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bit Bito USB Address 0x00 Bit7 Update Function Address Update Set to 1 when software writes the FADDR register USBO clears this bit to 0 when the new address takes effect 0 The last address written to FADDR is in effect 1 The last address written to FADDR is not yet in effect Bits6 0 Function Address Holds the 7 bit function address for USBO This address should be written by software when the SET ADDRESS standard device request is recei
149. O0 0x8000 Important Note About ADCO Input Configuration Port pins selected as ADCO inputs should be config ured as analog inputs and should be skipped by the Digital Crossbar To configure a Port pin for analog input set to the corresponding bit in register PnMDIN for n 0 1 2 3 To force the Crossbar to skip a Port pin set to 1 the corresponding bit in register PnSKIP for n 0 1 2 See Section 15 Port Input Output on page 147 for more Port I O configuration details 42 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 5 2 Temperature Sensor The temperature sensor transfer function is shown in Figure 5 2 The output voltage is the positive ADC input when the temperature sensor is selected by bits AMXOP4 0 in register AMXOP Values for the Offset and Slope parameters can be found in Table 5 1 Vtemp Slope x Tempo Offset Tempe Vremp Offset Slope Slope V deg C Voltage Dn lt Offset V at 0 Celsius Temperature Figure 5 2 Temperature Sensor Transfer Function The uncalibrated temperature sensor output is extremely linear and suitable for relative temperature mea surements see Table 5 1 for linearity specifications For absolute temperature measurements offset and or gain calibration is recommended Typically a 1 point offset calibration includes the following steps Step 1 Control measure the ambient
150. ODAT 6 Repeat from Step 2 Step 2 may be skipped when reading the same USBO register Step 3 may be skipped when the AUTORD bit USBOADR 6 is logic 1 168 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 16 2 USBO Controller Registers USB Register USB Register Description Page Number Name Address Interrupt Registers IN1INT 0x02 EndpointO and Endpoints1 3 IN Interrupt Flags 177 OUT1INT 0x04 Endpoints1 3 OUT Interrupt Flags 177 CMINT 0x06 Common USB Interrupt Flags 178 IN1IE 0x07 EndpointO and Endpoints1 3 IN Interrupt Enables 179 OUT1IE 0x09 Endpoints1 3 OUT Interrupt Enables 179 CMIE 0x0B Common USB Interrupt Enables 180 Common Registers FADDR 0x00 Function Address 173 POWER 0x01 Power Management 175 FRAMEL 0x0C Frame Number Low Byte 176 FRAMEH 0x0D Frame Number High Byte 176 INDEX 0x0E Endpoint Index Selection 169 CLKREC OxOF Clock Recovery Control 170 FIFOn 0 20 0 23 Endpoints0 3 FIFOs 172 Indexed Registers EOCSR 0x11 EndpointO Control Status 183 EINCSRL Endpoint IN Control Status Low Byte 186 EINCSRH 0x12 Endpoint IN Control Status High Byte 187 EOUTCSRL 0x14 Endpoint OUT Control Status Low Byte 189 EOUTCSRH 0x15 Endpoint OUT Control Status High Byte 190 EOCNT 0x16 Number of Received Bytes in EndpointO FIFO 184 EOUTCNTL Endpoint OUT Packet Count Low Byte 190 EOUTCNTH 0x17 Endpoint OUT
151. OHYN1 0 01 2 5 10 mV Negative Hysteresis 3 CPOHYN1 0 10 7 10 20 mV Negative Hysteresis 4 1 0 11 15 20 30 mV nU VUE eer 0 25 reS N Input Capacitance 3 pF Input Bias Current 0 001 nA Input Offset Voltage 5 5 mV Power Supply Power Supply Rejection 0 1 mV A Power up Time 10 us Mode 0 7 6 Supply Current at DC poe PUE 2 1 3 Mode 3 0 4 68 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 8 Voltage Regulator REGO C8051F340 1 2 3 4 5 6 7 devices include a voltage regulator REGO When enabled the REGO output appears on the Vpp pin and can be used to power external devices REGO can be enabled disabled by software using bit REGEN in register REGOCN See Table 8 1 for REGO electrical characteristics Note that the VBUS signal must be connected to the VBUS pin when using the device in a USB network The VBUS signal should only be connected to the REGIN pin when operating the device as a bus powered function REGO configuration options are shown in Figure 8 1 Figure 8 4 8 1 Regulator Mode Selection REGO offers a low power mode intended for use when the device is in suspend mode In this low power mode the REGO output remains as specified however the REGO dynamic performance response time is degraded See Table 8 1 for normal and low power mode supply current specifications The REGO mode selection is controlled via the REGMOD bit in register REGOCN 8 2
152. OPL INTO Polarity 0 INTO interrupt is active low 1 INTO interrupt is active high INTOSL2 0 INTO Port Pin Selection Bits These bits select which Port pin is assigned to INTO Note that this pin assignment is inde pendent of the Crossbar INTO will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar The Crossbar will not assign the Port pin to a peripheral if itis configured to skip the selected pin accomplished by setting to 1 the corresponding bit in register POSKIP INOSL2 0 INTO Port Pin 000 0 0 001 PO 1 010 PO 2 011 PO 3 100 PO 4 101 PO 5 110 0 6 111 0 7 SILICON LABORATORIES Rev 0 5 95 C8051F340 1 2 3 4 5 6 7 9 4 Power Management Modes The CIP 51 core has two software programmable power management modes Idle and Stop Idle mode halts the CPU while leaving the peripherals and clocks active In Stop mode the CPU is halted all inter rupts are inactive and the internal oscillator is stopped analog peripherals remain in their selected states the external oscillator is not affected Since clocks are running in Idle mode power consumption is depen dent upon the system clock frequency and the number of peripherals left in active mode before entering Idle Stop mode consumes the least power Figure 1 15 describes the Power Control Register PCON used to control the CIP 51 s power manag
153. On reset the CIP 51 performs the normal reset sequence and begins program execution at address 0x0000 If enabled the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode The Missing Clock Detector should be disabled if the CPU is to be put to in STOP mode for longer than the MCD timeout of 100 usec 96 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 9 14 PCON Power Control R W R W R W R W R W R W R W R W Reset Value GF5 GF4 GF3 GF2 GF1 GFO STOP IDLE 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0x87 Bits7 2 GF5 GFO General Purpose Flags 5 0 These are general purpose flags for use under software control Bit1 STOP Stop Mode Select Setting this bit will place the CIP 51 in Stop mode This bit will always be read as 0 1 CPU goes into Stop mode internal oscillator stopped Bito IDLE Idle Mode Select Setting this bit will place the CIP 51 in Idle mode This bit will always be read as 0 1 CPU goes into Idle mode Shuts off clock to CPU but clock to Timers Interrupts Serial Ports and Analog Peripherals are still active e Rev 0 5 97 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 NOTES 98 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 10 Prefetch Engine The C8051F340 1 2 3 4 5 6 7 family of devices incorporate a 2 byte prefetch engine Because the access time of the FLASH memory
154. Overflow 11 TMR2L Overflow yvy v vy SCL SMBUS CONTROL LOGIC lt FILTER e e Arbitration Interrupt e SCL Synchronization SCL fi C Request e SCL Generation Master Mode Control gt 5 E IR e SDA Control o e IRQ Generation Sn n mE s S Port I O BI R Y MEM SMBODAT 7 6 5 4 3 2 1 0 4 FILTER e SDA le mtd gt gt ls Figure 17 1 SMBus Block Diagram s Rev 0 5 193 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 17 1 Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents 1 The I2C Bus and How to Use lt including specifications Philips Semiconductor 2 The I2C Bus Specification Version 2 0 Philips Semiconductor 3 System Management Bus Specification Version 1 1 SBS Implementers Forum 17 2 SMBus Configuration Figure 17 2 shows a typical SMBus configuration The SMBus specification allows any recessive voltage between 3 0 V and 5 0 V different devices on the bus may operate at different voltage levels The bi direc tional SCL serial clock and SDA serial data lines must be connected to a positive power supply voltage through a pull up resistor or similar circuit Every device connected to the bus must have an open drain or open collector output for both the SCL and SDA lines so that both are pulled high recessive state when the bus is free The maximu
155. OxEE PCA Capture 3High 278 PCAOCPH4 OxFE PCA Capture 4 High 278 PCAOCPLO 0xFB PCA Capture 0 Low 277 PCAOCPL1 0xE9 PCA Capture 1 Low 277 2 0xEB PCA Capture 2 Low 277 PCAOCPL3 OxED PCA Capture 3 Low 277 PCAOCPL4 0xFD PCA Capture 4 Low 277 PCAOCPMO 0xDA PCA Module 0 Mode Register 276 1 0xDB PCA Module 1 Mode Register 276 2 0xDC PCA Module 2 Mode Register 276 PCAOCPM3 0xDD PCA Module 3 Mode Register 276 PCAOCPM4 0xDE PCA Module 4 Mode Register 276 PCAOH OxFA PCA Counter High 277 PCAOL OxF9 PCA Counter Low 277 PCAOMD OxD9 PCA Mode 275 PCON 0x87 Power Control 97 PFEOCN OxAF Prefetch Engine Control 99 PSCTL 0x8F Program Store R W Control 114 PSW OxDO Program Status Word 86 REFOCN OxD1 Voltage Reference Control 58 REGOCN 0xC9 Voltage Regulator Control 72 RSTSRC OxEF Reset Source Configuration Status 106 SBCON1 OxAC UART1 Baud Rate Generator Control 226 SBRLH1 0xB5 UART1 Baud Rate Generator High 227 SBRLL1 0 4 UART1 Baud Rate Generator Low 227 SBUF1 OxD3 UART1 Data Buffer 226 SCON1 0xD2 UART1 Control 224 672 Rev 0 5 83 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 9 3 Special Function Registers Continued SFRs are listed in alphabetical order All undefined SFR locations are reserved Register Address Description Page SBUFO 0x99 UARTO Data Buffer 217 SCONO 0x98 UAR
156. P4 4 P4 3 P4 2 P4 1 P4 0 11111111 Bit6 Bit5 Bit4 Bit3 Bit Bit Bito SFR Address 0x07 Bits7 0 P4 7 0 Write Output appears on I O pins 0 Logic Low Output 1 Logic High Output high impedance if corresponding PAMDOUT n bit 0 Read Always reads 0 if selected as analog input in register PAMDIN Directly reads Port pin when configured as digital input 0 P4 n pin is logic low 1 P4 n pin is logic high Note P4 is only available on 48 pin devices 160 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 15 21 PAMDIN Port4 Input Mode R W R W R W R W R W R W R W Reset Value 11111111 Bit6 Bit5 Bit4 Bit2 Bit Bito SFR Address 0xF5 Bits7 0 Analog Input Configuration Bits for P4 7 P4 0 respectively Port pins configured as analog inputs have their weak pull up digital driver and digital receiver disabled 0 Corresponding P4 n pin is configured as an analog input 1 Corresponding P4 n pin is not configured as an analog input Note P4 is only available on 48 pin devices SFR Definition 15 22 PAMDOUT Port4 Output Mode R W R W R W R W R W R W R W Reset Value 00000000 Bit6 Bit5 Bit4 Bit2 Bit Bito SFR Address OxAE Bits7 0 Output Configuration Bits for P4 7 P4 0 respectively ignored if corresponding bit in regis ter PAMDIN is logic O 0 Corresponding P4 n Output is open
157. Packet Count High Byte 190 USB Register Definition 16 4 INDEX USBO Endpoint Index R R R R R W R W R W R W Reset Value EPSEL 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito USB Address OxOE Bits7 4 Unused Read 0000b Write don t care Bits3 0 EPSEL Endpoint Select These bits select which endpoint is targeted when indexed USBO registers are accessed INDEX Target Endpoint 0x0 0 0x1 1 0x2 2 0x3 3 0 4 0 Reserved SILICON LABORATORIES Rev 0 5 169 C8051F340 1 2 3 4 5 6 7 16 4 USB Clock Configuration USBO is capable of communication as a Full or Low Speed USB function Communication speed is selected via the SPEED bit in SFR USBOXCN When operating as a Low Speed function the USBO clock must be 6 MHz When operating as a Full Speed function the USBO clock must be 48 MHz Clock options are described in Section 14 Oscillators on page 135 The USBO clock is selected via SFR CLKSEL see SFR Definition 14 6 Clock Recovery circuitry uses the incoming USB data stream to adjust the internal oscillator this allows the internal oscillator and 4x Clock Multiplier to meet the requirements for USB clock tolerance Clock Recovery should be used in the following configurations Communication Speed USB Clock 4x Clock Multiplier Input Full Speed 4x Clock Multiplier Internal Oscillator Low Speed Internal Oscillator 2 N A When operating USBO as a Low
158. PnMDIN register where a 1 indicates a digital input and a 0 indicates an analog input All pins default to digital inputs on reset The output driver characteristics of the I O pins are defined using the Port Output Mode registers PnMD OUT Each Port Output driver can be configured as either open drain or push pull This selection is required even for the digital resources selected in the XBRn registers and is not automatic The only exception to this is the SMBus SDA SCL pins which are configured as open drain regardless of the PnMDOUT settings When the WEAKPUD bit in XBR1 is 0 a weak pull up is enabled for all Port I O con figured as open drain WEAKPUD does not affect the push pull Port I O Furthermore the weak pull up is turned off on an output that is driving a 0 to avoid unnecessary power dissipation Registers XBRO and XBR1 must be loaded with the appropriate values to select the digital I O functions required by the design Setting the XBARE bit in XBR1 to 1 enables the Crossbar Until the Crossbar is enabled the external pins remain as standard Port I O in input mode regardless of the XBRn Register settings For given XBRn Register settings one can determine the I O pin out using the Priority Decode Table as an alternative the Configuration Wizard utility of the Silicon Labs IDE software will determine the Port I O pin assignments based on the XBRn Register settings Important Note The Crossbar must be
159. Port I O Crossbar Register 1 R W R W R W R W R W R W R W R W Reset Value WEAKPUD XBARE TIE TOE EGIE PCAOME 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xE2 Bit7 WEAKPUD Port O Weak Pull up Disable 0 Weak Pull ups enabled except for Ports whose are configured as analog input or push pull output 1 Weak Pull ups disabled Bit6 XBARE Crossbar Enable 0 Crossbar disabled all Port drivers disabled 1 Crossbar enabled Bit5 T1E T1 Enable 0 T1 unavailable at Port pin 1 T1 routed to Port pin Bit4 TOE TO Enable 0 TO unavailable at Port pin 1 TO routed to Port pin Bit3 ECIE External Counter Input Enable 0 ECI unavailable at Port pin 1 ECI routed to Port pin Bits2 0 PCAOME PCA Module Enable Bits 000 All PCA I O unavailable at Port pins 001 CEXO routed to Port pin 010 CEXO CEX1 routed to Port pins 011 CEXO CEX1 CEX2 routed to Port pins 100 CEXO CEX1 CEX2 CEX3 routed to Port pins 101 CEXO CEX1 CEX2 CEX3 CEXA routed to Port pins 110 Reserved 111 Reserved SFR Definition 15 3 XBR2 Port I O Crossbar Register 2 R W R W R W R W R W R W R W R W Reset Value URT1E 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address OxES Bits7 1 RESERVED Always write to 0000000b Bito URTIE UART1 I O Output Enable C8051F340 1 4 5 Only 0 UART1 I O unavailable at Port pins 1 UART1 TX1 R
160. R Definition 21 4 TLO Timer 0 Low 250 SFR Definition 21 5 TL1 Timer 1 Low 250 SFR Definition 21 6 THO Timer 0 High Byte 250 SFR Definition 21 7 TH1 Timer 1 High Byte 250 SFR Definition 21 8 TMR2CN Timer 2 255 SFR Definition 21 9 TMR2RLL Timer 2 Reload Register Low Byte 256 SFR Definition 21 10 TMR2RLH Timer 2 Reload Register High Byte 256 SFR Definition 21 11 TMR2L Timer 2 Low 256 SFR Definition 21 12 TMR2H Timer 2 High Byte 256 SFR Definition 21 13 TMR3CN Timer 3 261 SFR Definition 21 14 TMR3RLL Timer 3 Reload Register Low Byte 262 SFR Definition 21 15 TMR3RLH Timer Reload Register High Byte 262 SFR Definition 21 16 TMR3L Timer Low Byte 262 SFR Definition 21 17 TMR3H Timer High 262 SFR Definition 22 1 PCAOCN PCA Control 274 SFR Definition 22 2 PCAOMD PCA Mode 275 SFR Definition 22 3 PCAOCPMn PCA Capture Compare Mode 276 SFR Definition 22 4 PCAOL PCA Counter Timer Low Byte 277 SFR Definition 22 5 PCAOH PCA Counter Time
161. R W R R W R W R W R W R W R W Reset Value CP1EN CP1OUT CP1RIF CP1FIF CP1HYP1 CP1HYPO CP1HYN1 CP1HYNO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit Bito SFR Address Ox9A Bit7 CP1EN Comparator1 Enable Bit 0 Comparator1 Disabled 1 Comparator1 Enabled Bit6 CP1OUT Comparator1 Output State Flag 0 Voltage on CP1 CP1 1 Voltage on CP1 gt CP1 Bit5 CP1RIF Comparator1 Rising Edge Flag 0 No Comparator1 Rising Edge has occurred since this flag was last cleared 1 Comparator1 Rising Edge has occurred Bit4 CP1FIF Comparator1 Falling Edge Flag 0 No Comparator1 Falling Edge has occurred since this flag was last cleared 1 Comparator1 Falling Edge has occurred Bits3 2 CP1HYP1 0 Comparator1 Positive Hysteresis Control Bits 00 Positive Hysteresis Disabled 01 Positive Hysteresis 5 mV 10 Positive Hysteresis 10 mV 11 Positive Hysteresis 20 mV 51 0 CP1HYN1 0 Comparator1 Negative Hysteresis Control Bits 00 Negative Hysteresis Disabled 01 Negative Hysteresis 5 mV 10 Negative Hysteresis 10 mV 11 Negative Hysteresis 20 mV e Rev 0 5 65 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 7 5 CPT1MX Comparator1 MUX Selection R W R W R W R W R W R W R W R W Reset Value CMX1N2 CMX1N1 CMX1NO CMX1P2 CMX1P1 CMX1P0 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit Bito SFR Address 0x9E Bit7 UNUSED Read 0b Write don t care Bits6 4 CMX1
162. RO or R1 e 16 bit MOVX operations use the contents of DPTR to determine the effective address A 15 0 The full 16 bits of the Address Bus A 15 0 are driven during the off chip transaction 13 7 Timing The timing parameters of the External Memory Interface can be configured to enable connection to devices having different setup and hold time requirements The Address Setup time Address Hold time RD and WR strobe widths and in multiplexed mode the width of the ALE pulse are all programmable in units of SYSCLK periods through EMIOTC shown in SFR Definition 13 3 and EMIOCFT 1 0 The timing for an off chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing parameters defined by the EMIOTC register Assuming non multiplexed operation the minimum execution time for an off chip XRAM operation is 5 SYSCLK cycles 1 SYSCLK for RD or WR pulse 4 SYSCLKs For multiplexed operations the Address Latch Enable signal will require a minimum of 2 additional SYSCLK cycles Therefore the minimum execution time for an off chip XRAM operation in multiplexed mode is 7 SYSCLK cycles 2 for ALE 1 for RD or WR 4 The programmable setup and hold times default to the maximum delay settings after a reset Table 13 1 lists the AC parameters for the External Memory Interface and Figure 13 5 through Figure 13 10 show the timing diagrams for the different Exter nal Memory Interface modes and MOVX operations s Rev 0 5 12
163. RY RAM FLASH INTERNAL DATA ADDRESS SPACE OxFFFF RESERVED OxFF Upper 128 RAM Special Function OxFCOO Indirect Addressing Register s OxFBFF 0x80 Only Direct Addressing Only Ox7F Direct and Indirect Addressing Lower 128 RAM FLASH 0x30 Direct and Indirect 0x2F Addressin In System 0x20 9 Programmable in 512 0x1F Byte Sectors 0x00 EXTERNAL DATA ADDRESS SPACE 0x0000 OxFFFF Off Chip XRAM Available only on devices with EMIF 0x1000 OxOFFF 0x07FF 0x0400 0x0000 Figure 9 2 Memory Map 9 2 1 Program Memory The CIP 51 core has a 64k byte program memory space The C8051F340 1 2 3 4 5 6 7 implements 64k or 32k bytes of this program memory space as in system re programmable Flash memory Note that on the C8051F340 2 4 6 64k version addresses above OxFBFF are reserved Program memory is normally assumed to be read only However the CIP 51 can write to program memory by setting the Program Store Write Enable bit PSCTL 0 and using the MOVX instruction This feature pro vides a mechanism for the CIP 51 to update program code and use the program memory space for non volatile data storage Refer to Section 12 Flash Memory on page 109 for further details e Rev 0 5 79 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 9 2 2 Data Memory The CIP 51 includes 256 of internal RAM mapped into the data memory space from 0x00 through OxFF The lower 128 bytes of data memory are use
164. Rates Using The Internal Oscillator Target Baud Rate bps Actual Baud Rate bps Baud Rate Error Oscillator Divide Factor Timer Clock Source 5 1 5 0 pre scale select T1M Timer 1 Reload Value hex 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 2400 1200 230400 115200 57600 28800 14400 9600 2400 X Dont care Note SCA1 SCAO and T1M define the Timer Clock Source Bit definitions for these values can be found in Section 21 1 230769 115385 57692 28846 14423 9615 2404 SYSCLK SYSCLK SYSCLK SYSCLK 4 SYSCLK 4 SYSCLK 12 SYSCLK 48 SYSCLK 12 MHz 115385 57692 28846 14423 9615 2404 1202 230769 115385 57692 28846 14388 9615 2404 SYSCLK SYSCLK SYSCLK 4 SYSCLK 4 SYSCLK 12 SYSCLK 48 SYSCLK 48 SYSCLK SYSCLK SYSCLK 4 SYSCLK 4 SYSCLK 12 SYSCLK 12 SYSCLK 48 N I z S N 48 MHz SYSCLK O O 00 O so 00 O O 0 O O O SYSCLK 218 Rev 0 5 gt SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 19 UART1 C8051F340 1 4 5 Only UARTI is an asynchronous full duplex serial port offering a variety of data formatting options A dedicated baud rate generator with a 16 bit timer and selectable prescaler is included which can generate a wide range of ba
165. S C8051F340 1 2 3 4 5 6 7 17 4 1 SMBus Configuration Register The SMBus Configuration register SMBOCF is used to enable the SMBus Master and or Slave modes select the SMBus clock source and select the SMBus timing and timeout options When the ENSMB bit is set the SMBus is enabled for all master and slave events Slave events may be disabled by setting the INH bit With slave events inhibited the SMBus interface will still monitor the SCL and SDA pins however the interface will NACK all received addresses and will not generate any slave interrupts When the INH bit is set all slave events will be inhibited following the next START interrupts will continue for the duration of the current transfer Table 17 1 SMBus Clock Source Selection SMBCS1 SMBCSO SMBus Clock Source 0 0 Timer 0 Overflow 0 Timer 1 Overflow 1 0 Timer 2 High Byte Overflow 1 1 Timer 2 Low Byte Overflow The SMBCS1 0 bits select the SMBus clock source which is used only when operating as a master or when the Free Timeout detection is enabled When operating as a master overflows from the selected source determine the absolute minimum SCL low and high times as defined in Equation 17 1 Note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times For example Timer 1 overflows may generate the SMBus and UART baud rates simultaneously Timer configuration is covered in Section
166. SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 A Bulk or Interrupt pipe can be shut down or Halted by writing 1 to the SDSTL bit EOUTCSRL 5 While SDSTL 1 hardware will respond to all OUT requests with a STALL condition Each time hardware gen erates a STALL condition an interrupt will be generated and the STSTL bit EOUTCSRL 6 set to 1 The STSTL bit must be reset to 0 by firmware Hardware will automatically set OPRDY when a packet is ready in the OUT FIFO Note that if double buff ering is enabled for the target endpoint it is possible for two packets to be ready in the OUT FIFO at a time In this case hardware will set OPRDY to 1 immediately after firmware unloads the first packet and resets OPRDY to 0 A second interrupt will be generated in this case 16 13 2 Endpoints1 3 OUT Isochronous Mode When the ISO bit EOUTCSRH 6 is set to 1 the target endpoint operates in Isochronous ISO mode Once an endpoint has been configured for ISO OUT mode the host will send exactly one data per USB frame the location of the data packet within each frame may vary however Because of this it is recom mended that double buffering be enabled for ISO OUT endpoints Each time a data packet is received hardware will load the received data packet into the endpoint FIFO set the OPRDY bit EOUTCSRL O to 1 and generate an interrupt if enabled Firmware would typically use this interrupt to unload the data
167. SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Full Speed USB Flash MCU Family Analog Peripherals 10 Bit ADC Up to 200 ksps Built in analog multiplexer with single ended and differential mode VREF from external pin internal reference or Vpp Built in temperature sensor External conversion start input option Two comparators internal voltage reference Brown out detector and POR Circuitry USB Function Controller USB specification 2 0 compliant Full speed 12 Mbps or low speed 1 5 Mbps operation Integrated clock recovery no external crystal required for full speed or low speed Supports eight flexible endpoints 1kB USB buffer memory Integrated transceiver no external resistors required On Chip Debug On chip debug circuitry facilitates full speed non intru sive in system debug No emulator required Provides breakpoints single stepping inspect modify memory and registers Superior performance to emulation systems using ICE chips target pods and sockets Voltage Supply Input 2 7 to 5 25 V Voltages from 3 6 to 5 25 V supported using On Chip Voltage Regulator High Speed 8051 uC Core Pipelined instruction architecture executes 70 of Instructions in 1 or 2 system clocks 48 MIPS and 25 MIPS versions available Expanded interrupt handler Memory 4852 or 2304 Bytes RAM 640r 32 kB Flash In system programmable in 512 byte sectors Digital Peripherals 40 25 Port I O 5
168. Speed function with Clock Recovery software must write 1 to the CRLOW bit to enable Low Speed Clock Recovery Clock Recovery is typically not necessary in Low Speed mode Single Step Mode can be used to help the Clock Recovery circuitry to lock when high noise levels are present on the USB network This mode is not required or recommended in typical USB environments USB Register Definition 16 5 CLKREC Clock Recovery Control R W R W R W R W R W R W R W R W Reset Value CRE CRSSEN CRLOW Reserved 00001001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito USB Address OxOF Bit7 CRE Clock Recovery Enable This bit enables disables the USB clock recovery feature 0 Clock recovery disabled 1 Clock recovery enabled Bit6 CRSSEN Clock Recovery Single Step This bit forces the oscillator calibration into single step mode during clock recovery 0 Normal calibration mode 1 Single step mode Bit5 CRLOW Low Speed Clock Recovery Mode This bit must be set to 1 if clock recovery is used when operating as a Low Speed USB device 0 Full Speed Mode 1 Low Speed Mode Bits4 0 Reserved Read Variable Must Write 01001b Note The USB transceiver must be enabled before enabling Clock Recovery 170 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 16 5 FIFO Management 1024 bytes of on chip XRAM are used as FIFO space for USBO This FIFO space is split between EndpointsO 3 as sh
169. TO Control 216 SMBOCF 0 1 SMBus Configuration 200 SMBOCN 0xC0 SMBus Control 202 SMBODAT 0xC2 SMBus Data 204 SMOD1 OxE5 UART1 Mode 225 SP 0x81 Stack Pointer 85 SPIOCFG OxA1 SPI Configuration 236 SPIOCKR 2 SPI Clock Rate Control 238 SPIOCN OxF8 SPI Control 237 SPIODAT SPI Data 238 TCON 0x88 Timer Counter Control 247 THO 0x8C Timer Counter 0 High 250 TH1 0x8D Timer Counter 1 High 250 TLO 0x8A Timer Counter 0 Low 250 TL1 0x8B Timer Counter 1 Low 250 TMOD 0x89 Timer Counter Mode 248 TMR2CN 0xC8 Timer Counter 2 Control 255 TMR2H OxCD Timer Counter 2 High 256 TMR2L OxCC Timer Counter 2 Low 256 TMR2RLH 0 Timer Counter 2 Reload High 256 TMR2RLL OxCA Timer Counter 2 Reload Low 256 TMR3CN 0x91 Timer Counter 3Control 261 TMR3H 0x95 Timer Counter 3 High 262 TMR3L 0x94 Timer Counter 3Low 262 TMRS3RLH 0 93 Timer Counter 3 Reload High 262 TMR3RLL 0x92 Timer Counter 3 Reload Low 262 VDMOCN OxFF Vpp Monitor Control 103 USBOADR 0x96 USBO Indirect Address Register 167 USBODAT 0x97 USBO Data Register 168 USBOXON 0 07 USBO Transceiver Control 165 XBRO OxE1 Port I O Crossbar Control 0 152 XBR1 OxE2 Port I O Crossbar Control 1 153 XBR2 OxE3 Port I O Crossbar Control 2 153 All Other Addresses Reserved 84 Rev 0 5 67 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 9 2 7 Register Descriptions Following are descriptions of SFRs related to the operation of the CIP 51 System Controller Reserved bits should not b
170. This allows fast context switching when entering subroutines and interrupt service routines Indirect addressing modes use registers RO and H1 as index registers 9 2 4 Bit Addressable Locations In addition to direct access to data memory organized as bytes the sixteen data memory locations at 0x20 through Ox2F are also accessible as 128 individually addressable bits Each bit has a bit address from 0x00 to Ox7F Bit O of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0x07 Bit 7 of the byte at Ox2F has bit address Ox7F A bit access is distinguished from a full byte access by the type of instruction used bit source or destination operands as opposed to a byte source or destina tion The MCS 517M assembly language allows an alternate notation for bit addressing of the form XX B where XX is the byte address and B is the bit position within the byte For example the instruction MOV C 522113 moves the Boolean value at 0x13 bit 3 of the byte at location 0x22 into the Carry flag 9 2 5 Stack A programmer s stack can be located anywhere in the 256 byte data memory The stack area is desig nated using the Stack Pointer SP 0x81 SFR The SP will point to the last location used The next value pushed on the stack is placed at SP 1 and then SP is incremented A reset initializes the stack pointer to location 0x07 Therefore the first value pushed on the stack is placed at location 0x08 which is also t
171. V tolerant with high sink current Hardware enhanced SPI SMBus and one or two enhanced UART serial ports A Four general purpose 16 bit counter timers 16 bit programmable counter array PCA with five cap ture compare modules External Memory Interface EMIF Clock Sources Internal Oscillator 0 2596 accuracy with clock recovery enabled Supports all USB and UART modes External Oscillator Crystal RC C or clock 1 or 2 Pin modes Low Frequency 80 kHz Internal Oscillator Can switch between clock sources on the fly Packages 48 pin TQFP C8051F340 1 4 5 82 pin LQFP C8051F342 3 6 7 Temperature Range 40 to 85 C SENSOR VREF VREG PRECISION INTERNAL OSCILLATORS UARTI SPI 48 Pin Only CROSSBAR Ext Memory I F 64 32 kB 8051 CPU ISP FLASH 48 25 MIPS FLEXIBLE DEBUG WDT INTERRUPTS CIRCUITRY Rev 0 5 1 06 Copyright 2006 by Silicon Laboratories C8051F34x This information applies to a product under development Its characteristics and specifications are subject to change without notice C8051F340 1 2 3 4 5 6 7 NOTES 2 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table Of Contents 1 SYSTEM OVErvieW 17 1 1 CIP 51 Microcontroller 5 eina iple e tee op e dee eb etia aet 21 1 1 1 Fully 8051 Compatible rece iore rrr titre tere tt
172. VSTR Input I Timer Overflow Temp Sensor 2 L ADC Data Registers Port I O Pins VREF Window Window Compare Compare End of Logic Interrupt GND Conversion Interrupt Figure 1 9 10 Bit ADC Block Diagram 28 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 1 10 Comparators C8051F340 1 2 3 4 5 6 7 devices include two on chip voltage comparators that are enabled disabled and configured via user software Port I O pins may be configured as comparator inputs via a selection mux Two comparator outputs may be routed to a Port pin if desired a latched output and or an unlatched asyn chronous output Comparator response time is programmable allowing the user to select between high speed and low power modes Positive and negative hysteresis are also configurable Comparator interrupts may be generated on rising falling or both edges When in IDLE mode these inter rupts may be used as a wake up source ComparatorO may also be configured as a reset source Figure 1 10 shows the ComparatorO block diagram CPnEN CPNOUT 4 z CPnRIF Q CPnFIF CPnHYP1 RENDUM O cPnHvPo LI CPn 2 CMXnNO Interrupt CPnHYN1 blo CPnHYNO LI CMXnP2 CMXnP1 Rising edge Falling edge X ZN I D Interrupt 1 CPnRIE t S Logic CPnFIE pea 1 gt l CPn E x
173. X1 routed to Port pins e Rev 0 5 153 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 15 3 General Purpose Port I O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general purpose Ports 3 0 are accessed through corresponding special function registers SFRs that are both byte addressable and bit addressable Port 4 C8051F340 1 4 5 only uses an SFR which is byte addressable When writing to a Port the value written to the SFR is latched to maintain the output data value at each pin When reading the logic levels of the Port s input pins are returned regardless of the XBRn settings i e even when the pin is assigned to another signal by the Crossbar the Port register can always read its corresponding Port I O The exception to this is the execution of the read modify write instructions The read modify write instructions when operating on a Port SFR are the following ANL ORL XRL JBC CPL INC DEC DJNZ and MOV CLR or SETB when the destination is an individual bit in a Port SFR For these instructions the value of the register not the pin is read modified and written back to the SFR SFR Definition 15 4 PO 10 Latch R W R W R W R W R W R W R W Reset Value PO 6 P0 5 P0 4 P0 3 P0 2 1 PO O 11111111 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address bit addressable 0x80 Bits7 0 7 0 Write Output appears on I O pins per
174. YN bits As shown in Figure 7 2 various levels of negative hysteresis can be programmed or negative hysteresis can be disabled In a similar way the amount of positive hysteresis is determined by the setting the CPnHYP bits Comparator interrupts can be generated on both rising edge and falling edge output transitions For Inter rupt enable and priority control see Section 9 3 Interrupt Handler on page 87 The CPnFIF flag is set to 1 upon a Comparator falling edge and the CPnRIF flag is set to 1 upon the Comparator rising edge Once set these bits remain set until cleared by software The output state of the Comparator can be obtained at any time by reading the CPnOUT bit The Comparator is enabled by setting the CPnEN bit to 1 and is disabled by clearing this bit to 0 s Rev 0 5 61 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 7 1 CPTOCN ComparatorO Control R W R R W R W R W R W R W R W CPOEN CPOOUT CPORIF CPOFIF CPOHYP1 CPOHYPO CPOHYN1 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bito Bit7 CPOEN ComparatorO Enable Bit 0 ComparatorO Disabled 1 ComparatorO Enabled Bit6 CPOOUT ComparatorO Output State Flag 0 Voltage on CP0 lt 1 Voltage on CP0 gt Bit5 CPORIF ComparatorO Rising Edge Flag 0 No ComparatorO Rising Edge has occurred since this flag was last cleared 1 ComparatorO Rising Edge has occurr
175. a is invalid Bit6 AUTORD USBO Register Auto read Flag This bit is used for block FIFO reads 0 BUSY must be written manually for each USBO indirect register read 1 The next indirect register read will automatically be initiated when software reads USBODAT USBADDR bits will not be changed 55 0 USBADDR USBO Indirect Register Address These bits hold a 6 bit address used to indirectly access the USBO core registers Table 16 2 lists the USBO core registers and their indirect addresses Reads and writes to USBODAT will target the register indicated by the USBADDR bits e Rev 0 5 167 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 16 3 USBODAT USBO Data R W R W R W R W R W R W R W R W Reset Value USBODAT 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0x97 This SFR is used to indirectly read and write USBO registers Write Procedure 1 Poll for BUSY USB OADR 7 gt 0 2 Load the target USBO register address into the USBADDR bits in register USBOADR 3 Write data to USBODAT 4 Repeat Step 2 may be skipped when writing to the same USBO register Read Procedure 1 Poll for BUSY USB OADR 7 gt 0 2 Load the target USBO register address into the USBADDR bits in register USBOADR 3 Write 1 to the BUSY bit in register USBOADR steps 2 and 3 can be performed in the same write 4 Poll for BUSY USB OADR 7 gt 0 5 Read data from USB
176. abled and not configured as a master it will operate as a SPI slave As a slave bytes are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK sig nal A bit counter in the SPIO logic counts SCK edges When 8 bits have been shifted through the shift reg ister the SPIF flag is set to logic 1 and the byte is copied into the receive buffer Data is read from the receive buffer by reading SPIODAT A slave device cannot initiate transfers Data to be transferred to the master device is pre loaded into the shift register by writing to SPIODAT Writes to SPIODAT are dou ble buffered and are placed in the transmit buffer first If the shift register is empty the contents of the transmit buffer will immediately be transferred into the shift register When the shift register already con tains data the SPI will load the shift register with the transmit buffer s contents after the last SCK edge of the next or current SPI transfer When configured as a slave SPIO can be configured for 4 wire or 3 wire operation The default 4 wire slave mode is active when NSSMD1 SPIOCN 3 0 and NSSMDO SPIOCN 2 1 In 4 wire mode the NSS signal is routed to a port pin and configured as a digital input SPIO is enabled when NSS is logic 0 and disabled when NSS is logic 1 The bit counter is reset on a falling edge of NSS Note that the NSS sig nal must be driven low at least 2 system clocks before the first active edge
177. active OUT1 OUT Endpoint 1 Interrupt pending Flag This bit is cleared when software reads the OUT1INT register 0 OUT Endpoint 1 interrupt inactive 1 OUT Endpoint 1 interrupt active Unused Read 0 Write 2 don t care Rev 0 5 177 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 USB Register Definition 16 13 CMINT USBO Common Interrupt R R R R R R R R Reset Value SOF RSTINT RSUINT SUSINT 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito USB Address 0x06 Bits7 4 Unused Read 0000b Write don t care Bit3 SOF Start of Frame Interrupt Set by hardware when a SOF token is received This interrupt event is synthesized by hard ware an interrupt will be generated when hardware expects to receive a SOF event even if the actual SOF signal is missed or corrupted This bit is cleared when software reads the CMINT register 0 SOF interrupt inactive 1 SOF interrupt active Bit2 RSTINT Reset Interrupt pending Flag Set by hardware when Reset signaling is detected on the bus This bit is cleared when software reads the CMINT register 0 Reset interrupt inactive 1 Reset interrupt active Bit1 RSUINT Resume Interrupt pending Flag Set by hardware when Resume signaling is detected on the bus while USBO is in suspend mode This bit is cleared when software reads the CMINT register 0 Resume interrupt inactive 1 Resume interrupt active Bito SUSINT Suspend Interrupt pending Flag When Suspend de
178. al inter face or a byte that has just been received on the SMBus serial interface The CPU can read from or write to this register whenever the SI serial interrupt flag SMBOCN 0 is set to logic 1 The serial data in the register remains stable as long as the SI flag is set When the SI flag is not set the system may be in the process of shifting data in out and the CPU should not attempt to access this register 17 5 SMBus Transfer Modes The SMBus interface may be configured to operate as master and or slave At any particular time it will be operating in one of the following four modes Master Transmitter Master Receiver Slave Transmitter or Slave Receiver The SMBus interface enters Master Mode any time a START is generated and remains in Master Mode until it loses an arbitration or generates a STOP An SMBus interrupt is generated at the end of all SMBus byte frames however note that the interrupt is generated before the ACK cycle when operat ing as a receiver and after the ACK cycle when operating as a transmitter 17 5 1 Master Transmitter Mode Serial data is transmitted on SDA while the serial clock is output on SCL The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direction bit In this case the data direction bit R W will be logic O WRITE The master then transmits one or more bytes of serial data After each byte is transmitted an a
179. ased if it is unlocked Reading the contents of the Lock Byte is always permitted Locking additional pages changing 1 s to 0 in the Lock Byte is always permitted Unlocking FLASH pages changing 0 to 1s in the Lock Byte requires the C2 Device Erase command which erases all FLASH pages including the page containing the Lock Byte and the Lock Byte itself 7 The Reserved Area cannot be read written or erased DARN Accessing FLASH from user firmware executing on an unlocked page Any unlocked page except the page containing the Lock Byte may be read written or erased 2 Locked pages cannot be read written or erased 3 The page containing the Lock Byte cannot be erased It may be read or written only if it is unlocked 4 Reading the contents of the Lock Byte is always permitted 5 Locking additional pages changing 1s to 0 in the Lock Byte is always permitted 6 Unlocking FLASH pages changing Us to 1s in the Lock Byte is not permitted 7 The Reserved Area cannot be read written or erased Any attempt to access the reserved area or any other locked page will result in a FLASH Error device reset Accessing FLASH from user firmware executing on a locked page Any unlocked page except the page containing the Lock Byte may be read written or erased Any locked page except the page containing the Lock Byte may be read written or erased The page containing the Lock Byte cannot be era
180. bit is logic 1 in a data byte the ninth bit is always set to logic O Setting the MCEO bit SCONO 5 of a slave processor configures its UART such that when a stop bit is received the UART will generate an interrupt only if the ninth bit is logic 1 RB80 1 signifying an address byte has been received In the UART interrupt handler software will compare the received address with the slave s own assigned 8 bit address If the addresses match the slave will clear its MCEO bit to enable interrupts on the reception of the following data byte s Slaves that weren t addressed leave their MCEO bits set and do not generate interrupts on the reception of the following data bytes thereby ignoring the data Once the entire message is received the addressed slave resets its MCEO bit to ignore all transmis sions until it receives the next address byte Multiple addresses can be assigned to a single slave and or a single address can be assigned to multiple slaves thereby enabling broadcast transmissions to more than one slave simultaneously The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master slave role is temporarily reversed to enable half duplex transmission between the original master slave s 214 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Slave Device Master Slave Slave Device Device Device Figure 18 6 UART Multi Processor
181. bits A parity bit can be appended to the data and automatically generated and detected by hardware for even odd mark or space parity The stop bit length is selectable between short 1 bit time and long 1 5 or 2 bit times and a multi processor com munication mode is available for implementing networked UART buses All of the data formatting options can be configured using the SMOD1 register shown in SFR Definition 19 2 Figure 19 2 shows the timing for a UART1 transaction without parity or an extra bit enabled Figure 19 3 shows the timing for a UART1 transaction with parity enabled PE1 1 Figure 19 4 is an example of a UART1 transaction when the extra bit is enabled XBE1 1 Note that the extra bit feature is not available when parity is enabled and the second stop bit is only an option for data lengths of 6 7 or 8 bits MARK START SPACE BIT 1 BIT2 BIT TIMES Optional N bits N 2 5 6 7 or8 Figure 19 2 UART1 Timing Without Parity or Extra Bit MARK START SPACE BIT 1 BIT 2 BIT TIMES Optional N bits N 2 5 6 7 or8 Figure 19 3 UART1 Timing With Parity STOP STOP BIT 1 BIT2 MARK START a X SPACE BIT TIMES N bits N 25 6 7 or8 Figure 19 4 UART1 Timing With Extra Bit s Rev 0 5 221 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 19 3 Configuration and Operation UART1 provides standard a
182. can be calcu lated The OSCLF bits can then be adjusted to produce the desired oscillator period s Rev 0 5 137 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 R W SFR Definition 14 3 OSCLCN Internal L F Oscillator Control R R W R R W R W R W R W Reset Value OSCLEN OSCLRDY OSCLF3 OSCLF2 OSCLF1 OSCLFO OSCLD1 OSCLDO 00vvvv00 Bit7 Bit7 Bit6 Bits5 2 Bits1 0 Bit6 Bit5 Bit4 Bit2 Bit Bito SFR Address 0x86 OSCLEN Internal L F Oscillator Enable 0 Internal L F Oscillator Disabled 1 Internal L F Oscillator Enabled OSCLRDY Internal L F Oscillator Ready Flag 0 Internal L F Oscillator freguency not stabilized 1 Internal L F Oscillator freguency stabilized OSCLF 3 0 Internal L F Oscillator Frequency Control bits Fine tune control bits for the internal L F Oscillator frequency When set to 0000b the L F oscillator operates at its fastest setting When set to 1111b the L F oscillator operates at its slowest setting OSCLD 1 0 Internal L F Oscillator Divider Select 00 Divide by 8 selected 01 Divide by 4selected 10 Divide by 2 selected 11 Divide by 1 selected 138 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 14 3 External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal ceramic resonator capacitor or RC network A CMOS clock may also provide a
183. ce is distributed among Endpoints0 3 Endpoint1 3 FIFO slots can be configured as IN OUT or both IN and OUT split mode The maximum FIFO size is 512 bytes Endpoint3 USBO can be operated as a Full or Low Speed function On chip 4x Clock Multiplier and clock recovery cir cuitry allow both Full and Low Speed options to be implemented with the on chip precision oscillator as the USB clock source An external oscillator source can also be used with the 4x Clock Multiplier to generate the USB clock The CPU clock source is independent of the USB clock The USB Transceiver is USB 2 0 compliant and includes on chip matching and pull up resistors The pull up resistors can be enabled disabled in software and will appear on the D or D pin according to the software selected speed setting Full or Low Speed Transceiver Serial Interface Engine SIE Endpointo IN OUT USB Data Control CIP 51 Core Transfer Engpoint1 Status and Control Endpoint Interrupt Endpoint3 Registers CE USB FIFOs 1k RAM Figure 1 5 USB Controller Block Diagram 24 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 1 4 Voltage Regulator C8051F340 1 2 3 4 5 6 7 devices include a voltage regulator REGO When enabled the REGO output appears on the Vpp pin and can also be used to power other external devices REGO can be enabled dis abled by software 1 5
184. ches the polarity selected by the VBPOL bit in register REGOCN See Section 8 Voltage Regulator REGO on page 69 for details on the VBUS detection circuit The USBRSF bit will read 1 following a USB reset The state of the RST pin is unaffected by this reset s Rev 0 5 105 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 11 2 RSTSRC Reset Source R W R R W R W R R W R W R Reset Value USBRSF FERROR CORSEF SWRSF WDTRSF MCDRSF PORSF PINRSF Variable Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit SFR Address OxEF Bit7 USBRSF USB Reset Flag 0 Read Last reset was not a USB reset Write USB resets disabled 1 Read Last reset was a USB reset Write USB resets enabled Bit6 FERROR Flash Error Indicator 0 Source of last reset was not a Flash read write erase error 1 Source of last reset was a Flash read write erase error Bit5 CORSEF ComparatorO Reset Enable and Flag 0 Read Source of last reset was not Comparator0 Write Comparatoro is not a reset Source 1 Read Source of last reset was Comparator0 Write Comparator0 is a reset source active low Bit4 SWRSF Software Reset Force and Flag 0 Read Source of last reset was not a write to the SWRSF bit Write No Effect 1 Read Source of last was a write to the SWRSF bit Write Forces a system reset Bit3 WDTRSF Watchdog Timer Reset Flag 0 Source of last reset was not a WDT timeout
185. circuit off 010 External CMOS Clock Mode 011 External CMOS Clock Mode with divide by 2 stage 100 RC Oscillator Mode 101 Capacitor Oscillator Mode 110 Crystal Oscillator Mode 111 Crystal Oscillator Mode with divide by 2 stage Bit3 RESERVED Read 0 Write don t care Bits2 0 XFCN2 0 External Oscillator Frequency Control Bits 000 111 See table below XFCN Crystal XOSCMD 11x RC XOSCMD 10x XOSCMD 10x 000 f lt 32 kHz f lt 25 kHz K Factor 0 87 001 32 kHz f x 84kHz 25 kHz f x 50 kHz K Factor 2 6 010 84 kHz f x 225 kHz 50 kHz f lt 100 kHz K Factor 7 7 011 225 kHz lt f lt 590 kHz 100 kHz f x 200 kHz K Factor 22 100 590 kHz fx 1 5 MHz 200 kHz f x 400 kHz K Factor 65 101 1 5 MHz lt f lt 4 MHz 400 kHz f x 800 kHz K Factor 180 110 4 MHz f x 10 MHz 800 kHz f lt 1 6 MHz K Factor 664 111 10 MHz fx 30 MHz 1 6 MHz lt f lt 3 2 MHz K Factor 2 1590 CRYSTAL MODE Circuit from Figure 14 1 Option 1 XOSCMD 11x Choose XFCN value to match crystal or resonator frequency RC MODE Circuit from Figure 14 1 Option 2 XOSCMD 10x Choose XFCN value to match frequency range f 1 23 103 x C where f frequency of clock in MHz C capacitor value in pF R Pull up resistor value in C MODE Circuit from Figure 14 1 Option 3 XOSCMD 10x Choose K Factor KF for the oscillation frequency desired
186. cknowledge bit is generated by the slave The transfer is ended when the STO bit is set and a STOP is generated Note that the interface will switch to Master Receiver Mode if SMBODAT is not written following a Master Transmitter interrupt Figure 17 5 shows a typical Master Transmitter sequence Two transmit data bytes are shown though any number of bytes may be transmitted Notice that the data byte transferred interrupts occur after the ACK cycle in this mode 204 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 s SLA W A Data Byte A Data Byte Received by SMBus S START Interface P STOP W WRITE Transmitted by SMBus Interface SLA Slave Address Figure 17 5 Typical Master Transmitter Sequence amp Rev 0 5 205 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 17 5 2 Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the data direc tion bit In this case the data direction bit R W will be logic 1 READ Serial data is then received from the slave on SDA while the SMBus outputs the serial clock The slave transmits one or more bytes of serial data After each byte is received ACKRQ is set to 1 and an interrupt is generated Software must write the ACK bit SMBOCN 1 to define the outgoing ackno
187. cle 10 Address hold time 2 SYSCLK cycles 11 Address hold time 3 SYSCLK cycles 126 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 13 7 1 Non multiplexed Mode 13 7 1 1 16 bit MOVX EMIOCF 4 2 101 110 or 111 Nonmuxed 16 bit WRITE ADDR 15 8 P2 P2 ADDR 7 0 P3 P3 DATA 7 0 P4 P4 Nonmuxed 16 bit READ ADDR 15 8 ADDRI7 0 DATA 7 0 Figure 13 5 Non multiplexed 16 bit MOVX Timing s Rev 0 5 127 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 13 7 1 2 8 bit MOVX without Bank Select EMIOCF 4 2 101 or 1117 Nonmuxed 8 bit WRITE without Bank Select ADDR 15 8 P2 ADDRI7 0 DATA 7 0 ANR RD Nonmuxed 8 bit READ without Bank Select ADDR 15 8 P2 ADDRI7 0 DATA 7 0 RD ANR Figure 13 6 Non multiplexed 8 bit MOVX without Bank Select Timing 128 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 13 7 1 3 8 bit MOVX with Bank Select EMIOCF 4 2 110 Muxed 8 bit WRITE with Bank Select ADDR 15 8 P3 P3 AD 7 0 P4 P4 ALE P1 3 P1 3 os T ow gt AD Pme P16 P1 7 Muxed 8 bit READ with Bank Select ADDR 15 8 AD 7 0 ALE RD PI Figure 13 7 Non multiplexed 8 bit MOVX with Bank Select Timing s Rev 0 5 129 SILICON LABORATORIES C8051F340 1 2 3
188. cleared by hardware It must be cleared by software Bit 4 RXOVRN Receive Overrun Flag Slave Mode only This bit is set to logic 1 by hardware and generates a SPIO interrupt when the receive buffer still holds unread data from a previous transfer and the last bit of the current transfer is shifted into the SPIO shift register This bit is not automatically cleared by hardware It must be cleared by software Bits 3 2 NSSMD1 NSSMDO Slave Select Mode Selects between the following NSS operation modes See Section 20 2 SPIO Master Mode Operation on page 231 and Section 20 3 SPIO Slave Mode Operation on page 233 00 3 Wire Slave or 3 wire Master Mode NSS signal is not routed to a port pin 01 4 Wire Slave or Multi Master Mode Default NSS is always an input to the device 1x 4 Wire Single Master Mode NSS signal is mapped as an output from the device and will assume the value of NSSMDO Bit 1 TXBMT Transmit Buffer Empty This bit will be set to logic O when new data has been written to the transmit buffer When data in the transmit buffer is transferred to the SPI shift register this bit will be set to logic 1 indicating that it is safe to write a new byte to the transmit buffer Bit 0 SPIEN SPIO Enable This bit enables disables the SPI 0 SPI disabled 1 SPI enabled s Rev 0 5 237 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 20 3 SPIOCKR SPIO Clock Rate R W R W R W R W R W
189. clock input For a crystal or ceramic resonator configuration the crystal resonator must be wired across the XTAL1 and XTAL2 pins as shown in Option 1 of Figure 14 1 A 10 MO resistor also must be wired across the XTAL1 and XTAL2 pins for the crystal resonator configuration In RC capacitor or CMOS clock configuration the clock source should be wired to the XTAL2 pin as shown in Option 2 3 or 4 of Figure 14 1 The type of external oscillator must be selected in the OSCXCN register and the frequency control bits XFCN must be selected appropriately see SFR Definition 14 4 Important Note on External Oscillator Usage Port pins must be configured when using the external oscillator circuit When the external oscillator drive circuit is enabled in crystal resonator mode Port pins PO 2 and PO 3 are used as XTAL1 and XTAL2 respectively When the external oscillator drive circuit is enabled in capacitor RC or CMOS clock mode Port pin PO 3 is used as XTAL2 The Port I O Crossbar should be configured to skip the Port pins used by the oscillator circuit see Section 15 1 Priority Cross bar Decoder on page 149 for Crossbar configuration Additionally when using the external oscillator cir cuit in crystal resonator capacitor or RC mode the associated Port pins should be configured as analog inputs In CMOS clock mode the associated pin should be configured as a digital input See Section 15 2 Port O Initialization on page 151 for details on
190. ct protocol errors and send a STALL condition in response Firmware may force a STALL condition to abort the current transfer When a STALL condition is generated the STSTL bit will be set to 1 and an interrupt generated The following conditions will cause hardware to generate a STALL condition 1 The host sends an OUT token during a OUT data phase after the DATAEND bit has been set to 1 2 The host sends an IN token during an IN data phase after the DATAEND bit has been set to T 3 The host sends a packet that exceeds the maximum packet size for EndpointO 4 The host sends a non zero length DATA1 packet during the status phase of an IN transaction Firmware sets the SDSTL bit EOCSR 5 to 1 16 10 1 EndpointO SETUP Transactions All control transfers must begin with a SETUP packet SETUP packets are similar to OUT packets contain ing an 8 byte data field sent by the host Any SETUP packet containing a command field of anything other than 8 bytes will be automatically rejected by USBO An EndpointO interrupt is generated when the data from a SETUP packet is loaded into the EndpointO FIFO Software should unload the command from the EndpointO FIFO decode the command perform any necessary tasks and set the SOPRDY bit to indicate that it has serviced the OUT packet 16 10 2 EndpointO IN Transactions When a SETUP request is received that requires USBO to transmit data to the host one or more IN requests will be sent by th
191. ctional Block Diagram Table 6 1 Voltage Reference Electrical 7 Comparators Figure 7 1 Comparator Functional Block Diagram Figure 7 2 Comparator Hysteresis 0 Table 7 1 Comparator Electrical Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 8 Voltage Regulator REGO Table 8 1 Voltage Regulator Electrical 69 Figure 8 1 REGO Configuration USB 70 Figure 8 2 REGO Configuration USB 5 70 Figure 8 3 REGO Configuration USB Self Powered Regulator Disabled 71 Figure 8 4 REGO Configuration No USB 71 9 CIP 51 Microcontroller Figure 9 1 CIP 51 Block Diagram oooooooo nn 00 73 Table 9 1 CIP 51 Instruction Set 75 Figure 9 2 Memory e Lect 79 Table 9 2 Special Function Register SFR Memory 81 Table 9 3 Special Function
192. d rapisee 147 15 T Priority Crossbar eel ethan n rodean rene hme te 149 POM IMAL ZA OV T A 151 15 3 General Purpose Poft YO UE o petto oh ob za 154 16 Universal Serial Bus Controller USBO esses 163 1 Addressing ees ter e doceret ni 164 16 2 USB ratis eI VBl Ec Pp e ect 164 16 3 USB Register ACCESS conie editio or Ese e eR E undae tees 166 16 4 USB Glock onset rto e recae es done neh nse idee ney 170 16 5 FIFO Management etu titur 171 16 5 1 FIFO Split MOG 2 utet ettet tete tes 171 16 5 2 FIFO Double 172 UG FECA CCOSS MR 172 16 6 55 soci o oe os rod 173 16 7 Function Configuration and ns 173 16 9 Iber TUIS Sanne crea uU t os 176 16 9 The Serial Interface Engine isis ecd ess 180 16 T0 c Pr ORNA 180 16 10 1 EndpointO SETUP 181 16 10 2 EndpointO INCTEAFISACHOTIS nu
193. d 3 above The SIE will transmit a NAK in response to an IN token if there is no packet ready in the IN FIFO INPRDY s Rev 0 5 181 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 16 10 3 EndpointO OUT Transactions When a SETUP request is received that requires the host to transmit data to USBO one or more OUT requests will be sent by the host When an OUT packet is successfully received by USBO hardware will set the OPRDY bit EOCSR O to 1 and generate an EndpointO interrupt Following this interrupt firmware should unload the OUT packet from the EndpointO FIFO and set the SOPRDY bit EOCSR 6 to 1 If the amount of data required for the transfer exceeds the maximum packet size for EndpointO the data will be split into multiple packets If the requested data is an integer multiple of the maximum packet size for EndpointO as reported to the host the host will send a zero length data packet signaling the end of the transfer Upon reception of the first OUT token for a particular control transfer EndpointO is said to be in Receive Mode In this mode only OUT tokens should be sent by the host to 0 The SUEND bit EOCSR 4 is set to 1 SETUP or IN token is received while EndpointO is in Receive Mode EndpointO will remain in Receive mode until 1 The SIE receives a SETUP or IN token 2 The host sends a packet less than the maximum EndpointO packet size 3 The host sends a zero l
194. d be erased before writing data 0 Writes to Flash program memory disabled 1 Writes to Flash program memory enabled the MOVX write instruction targets Flash memory SFR Definition 12 2 FLKEY Flash Lock and Key R W R W R W R W R W R W Reset Value 00000000 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0xB7 FLKEY Flash Lock and Key Register Write This register must be written to before Flash writes or erases can be performed Flash remains locked until this register is written to with the following key codes 0xA5 OxF1 The timing of the writes does not matter as long as the codes are written in order The key codes must be written for each Flash write or erase operation Flash will be locked until the next System reset if the wrong codes are written or if a Flash operation is attempted before the codes have been written correctly Read When read bits 1 0 indicate the current Flash lock state 00 Flash is write erase locked 01 The first key code has been written 0xA5 10 Flash is unlocked writes erases allowed 11 Flash writes erases disabled until the next reset 114 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 12 3 FLSCL Flash Scale R W R W R W R W R W R W R W R W Reset Value FOSE Reserved Reserved FLRT Reserved Reserved Reserved Reserved 10000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0xB6
195. d for general purpose registers and scratch pad memory Either direct or indirect addressing may be used to access the lower 128 bytes of data memory Locations 0x00 through Ox1F are addressable as four banks of general purpose registers each bank consisting of eight byte wide registers The next 16 bytes locations 0x20 through Ox2F may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode The upper 128 bytes of data memory are accessible only by indirect addressing This region occupies the same address space as the Special Function Registers SFR but is physically separate from the SFR space The addressing mode used by an instruction when accessing locations above Ox7F determines whether the CPU accesses the upper 128 bytes of data memory space or the SFRs Instructions that use direct addressing will access the SFR space Instructions using indirect addressing above Ox7F access the upper 128 bytes of data memory Figure 9 2 illustrates the data memory organization of the CIP 51 9 2 3 General Purpose Registers The lower 32 bytes of data memory locations 0x00 through 0x1F may be addressed as four banks of gen eral purpose registers Each bank consists of eight byte wide registers designated RO through R7 Only one of these banks may be enabled at a time Two bits in the program status word RS0 PSW 3 and RS1 PSW 4 select the active register bank see description of the PSW in SFR Definition 9 4
196. d the Clock Scale bits SCA1 SCAO The Clock Scale bits define a pre scaled clock from which Timer 0 and or Timer 1 may be clocked See SFR Definition 21 3 for pre scaled clock selection Timer 0 1 may then be configured to use this pre scaled clock signal or the system clock Timer 2 and Timer 3 may be clocked by the system clock the system clock divided by 12 or the external oscillator clock source divided by 8 Timer 0 and Timer 1 may also be operated as counters When functioning as a counter a counter timer register is incremented on each high to low transition at the selected input pin TO or T1 Events with a fre quency of up to one fourth the system clock s frequency can be counted The input signal need not be peri odic but it should be held at a given level for at least two full system clock cycles to ensure the level is properly sampled 21 1 Timer 0 and Timer 1 Each timer is implemented as a 16 bit register accessed as two separate bytes a low byte TLO or TL1 and a high byte THO or TH1 The Counter Timer Control register TCON is used to enable Timer 0 and Timer 1 as well as indicate status Timer 0 interrupts can be enabled by setting the ETO bit in the IE register Section 9 3 5 Interrupt Register Descriptions on page 89 Timer 1 interrupts can be enabled by setting the ET1 bit in the IE register Section 9 3 5 Both counter timers operate in one of four primary modes selected by setting the Mode Select bits T1M1 TO
197. dard MCU emulators that use on board ICE Chips and require the MCU in the application board to be socketed Silicon Labs debug paradigm increases ease of use and preserves the performance of the precision analog peripherals e Rev 0 5 25 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 1 6 Programmable Digital O and Crossbar C8051F340 1 4 5 devices include 40 I O pins five byte wide Ports C8051F342 3 6 7 devices include 25 I O pins three byte wide Ports and a 1 bit wide Port The C8051F340 1 2 3 4 5 6 7 Ports behave like typ ical 8051 Ports with a few enhancements Each Port pin may be configured as an analog input or a digital I O pin Pins selected as digital l Os may additionally be configured for push pull or open drain output The weak pull ups that are fixed on typical 8051 devices may be globally disabled providing power savings capabilities The Digital Crossbar allows mapping of internal digital system resources to Port I O pins See Figure 1 6 On chip counter timers serial buses HW interrupts comparator outputs and other digital signals in the controller can be configured to appear on the Port I O pins specified in the Crossbar Control registers This allows the user to select the exact mix of general purpose Port I O and digital resources needed for the end application XBRO XBR1 XBR2 PnMDOUT PnSKIP Registers PnMDIN Registers Priority Decoder Highest 2 Priority 2 2 VO M sel
198. ddress byte differs from a data byte in that its extra bit is logic 1 in a data byte the extra bit is always set to logic 0 Setting the MCE1 bit SMOD1 7 of a slave processor configures its UART such that when a stop bit is received the UART will generate an interrupt only if the extra bit is logic 1 RBX1 1 signifying an address byte has been received In the UART interrupt handler software will compare the received address with the slave s own assigned address If the addresses match the slave will clear its MCE1 bit to enable interrupts on the reception of the following data byte s Slaves that weren t addressed leave their MCE1 bits set and do not generate interrupts on the reception of the following data bytes thereby ignoring the data Once the entire message is received the addressed slave resets its MCE1 bit to ignore all trans missions until it receives the next address byte Multiple addresses can be assigned to a single slave and or a single address can be assigned to multiple slaves thereby enabling broadcast transmissions to more than one slave simultaneously The master processor can be configured to receive all transmissions or a protocol can be implemented such that the master slave role is temporarily reversed to enable half duplex transmission between the original master and slave s Slave Device Master Slave Slave Device Device Device TX RX TX Figure 19 6 UART Multi Processor Mode Intercon
199. ds the high byte MSB of the 16 bit PCA Counter Timer SFR Definition 22 6 PCAOCPLn PCA Capture Module Low Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address OxFB OxE9 OxEB OxED OxFD PCAOCPLn Address PCAOCPLO OxFB n 0 PCAOCPL1 0 9 n 1 PCAOCPL2 OxEB 2 OxED n 3 PCAOCPL4 OxFD n 4 Bits7 0 PCAOCPLn PCA Capture Module Low Byte The PCAOCPLn register holds the low byte LSB of the 16 bit capture module n s Rev 0 5 277 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 22 7 PCAOCPHn PCA Capture Module High Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address OxFC OxEA OxEC OxEE OxFE PCAOCPHn Address OxFC 0 PCAOCPH1 OxEA n 1 PCAOCPH2 OxEC n 2 PCAOCPH3 OXEE n 3 OxFE n 4 Bits7 0 PCAOCPHn PCA Capture Module High Byte The PCAOCPHn register holds the high byte MSB of the 16 bit capture module n 278 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 23 C2 Interface C8051F340 1 2 3 4 5 6 7 devices include an on chip Silicon Labs 2 Wire C2 debug interface to allow Flash programming and in system debugging with the production part installed in the end application The C2 in
200. e Rev 0 5 53 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 5 4 1 Window Detector In Single Ended Mode Figure 5 6 shows two example window comparisons for right justified single ended data with ADCOLTH ADCOLTL 0x0080 128d and ADCOGTH ADCOGTL 0x0040 64d In single ended mode the input voltage can range from 0 to VREF x 1023 1024 with respect to GND and is represented by a 10 bit unsigned integer value In the left example an ADOWINT interrupt will be generated if the ADCO conversion word ADCOH ADCOL is within the range defined by ADCOGTH ADCOGTL and ADCOLTH ADCOLTL if 0x0040 ADCOH ADCOL 0x0080 In the right example and ADOWINT interrupt will be generated if the ADCO conversion word is outside of the range defined by the ADCOGT and ADCOLT registers if ADCOH ADCOL 0x0040 or ADCOH ADCOL gt 0x0080 Figure 5 7 shows an exam ple using left justified data with equivalent ADCOGT and ADCOLT register settings ADCOH ADCOL ADCOH ADCOL Input Voltage Input Voltage Px x GND Px x GND VREF x 1023 1024 0x03FF VREF x 1023 1024 ADOWINT not affected ADONIS 0x0081 VREF x 128 1024 0x0080 4 ADCOLTH ADCOLTL VREF x 128 1024 0x0080 4 ADCOGTH ADCOGTL rr 7 0x007F ADOWINT 1 not affected ROT 224 14 0 0041 TERM VREF x 64 1024 0x0040 4 ADCOGTH ADCOGTL VREF x 64 1024 0x0040 ADCOLTH ADCO
201. e RI1 flag will be set Note when MCE1 1 RI1 will only be set if the extra bit was equal to 1 Data can be read from the receive FIFO by reading the SBUF1 register The SBUF1 register represents the oldest 222 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 byte in the FIFO After SBUF1 is read the next byte in the FIFO is loaded into SBUF1 and space is made available in the FIFO for another incoming byte If enabled an interrupt will occur when RI1 is set If the extra bit function is enabled XBE1 1 and the parity function is disabled PE1 0 the extra bit for the oldest byte in the FIFO can be read from the RBX1 bit SCON1 2 If the extra bit function is not enabled the value of the stop bit for the oldest FIFO byte will be presented in RBX1 When the parity func tion is enabled PE1 1 hardware will check the received parity bit against the selected parity type selected with S1PT 1 0 when receiving data If a byte with parity error is received the PERR1 flag will be set to 17 This flag must be cleared by software Note when parity is enabled the extra bit function is not available 19 3 3 Multiprocessor Communications UART1 supports multiprocessor communication between a master processor and one or more slave pro cessors by special use of the extra data bit When a master processor wants to transmit to one or more slaves it first sends an address byte to select the target s An a
202. e SPI mode the NSS signal may or may not be routed to a Port pin 150 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 15 2 Port I O Initialization Port I O initialization consists of the following steps Step 1 Select the input mode analog or digital for all Port pins using the Port Input Mode register PnMDIN Step 2 Select the output mode open drain or push pull for all Port pins using the Port Output Mode register PAMDOUT Step Select any pins to be skipped by the I O Crossbar using the Port Skip registers PnSKIP Step 4 Assign Port pins to desired peripherals XBRO XBR1 Step 5 Enable the Crossbar XBARE 17 All Port pins must be configured as either analog or digital inputs Any pins to be used as Comparator or ADC inputs should be configured as an analog inputs When a pin is configured as an analog input its weak pull up digital driver and digital receiver are disabled This process saves power and reduces noise on the analog input Pins configured as digital inputs may still be used by analog peripherals however this practice is not recommended To configure a Port pin for digital input write 0 to the corresponding bit in register PAMDOUT and write 1 to the corresponding Port latch register Pn Additionally all analog input pins should be configured to be skipped by the Crossbar accomplished by setting the associated bits in PnSKIP Port input mode is set in the
203. e address is ignored slave interrupts will be inhibited until a START is detected If the received slave address is acknowledged data should be written to SMBODAT to be transmitted The interface enters Slave Transmitter Mode and trans mits one or more bytes of data After each byte is transmitted the master sends an acknowledge bit if the acknowledge bit is an ACK SMBODAT should be written with the next data byte If the acknowledge bit is a NACK SMBODAT should not be written to before SI is cleared Note an error condition may be gener ated if SMBODAT is written following a received NACK while in Slave Transmitter Mode The interface exits Slave Transmitter Mode after receiving a STOP Note that the interface will switch to Slave Receiver Mode if SMBODAT is not written following a Slave Transmitter interrupt Figure 17 8 shows a typical Slave Transmitter sequence Two transmitted data bytes are shown though any number of bytes may be trans mitted Notice that the data byte transferred interrupts occur after the ACK cycle in this mode S SLA RIA Data Byte A Data Byte Interrupt Interrupt Interrupt Received by SMBus S START Interface P STOP N NACK R READ Transmitted by SLA Slave Address SMBus Interface Figure 17 8 Typical Slave Transmitter Sequence 17 6 SMBus Status Decoding The current SMBus status can be easily decoded using the SMBOCN register In the table below STATUS VECTOR refers
204. e contents of the Timer 3 registers TMR3H and TMR3L are latched into the Timer 3 reload registers TMR3RLH and TMR3RLH and a Timer 3 interrupt is generated if enabled Bit3 TSSPLIT Timer 3 Split Mode Enable When this bit is set Timer 3 operates as two 8 bit timers with auto reload 0 Timer 3 operates in 16 bit auto reload mode 1 Timer 3 operates as two 8 bit auto reload timers Bit2 TR3 Timer 3 Run Control This bit enables disables Timer 3 In 8 bit mode this bit enables disables TMR3H only TMR3L is always enabled in this mode 0 Timer 3 disabled 1 Timer 3 enabled Bit1 T3CSS Timer 3 Capture Source Select This bit selects the source of a capture event when bit T3CE is set to 1 0 Capture source is USB SOF event 1 Capture source is rising edge of Low Frequency Oscillator Bito T3XCLK Timer 3 External Clock Select This bit selects the external clock source for Timer 3 If Timer 3 is in 8 bit mode this bit selects the external oscillator clock source for both timer bytes However the Timer 3 Clock Select bits T3MH and T3ML in register CKCON may still be used to select between the external clock and the system clock for either timer 0 Timer 3 external clock selection is the system clock divided by 12 1 Timer 3 external clock selection is the external clock divided by 8 Note that the external oscillator source divided by 8 is synchronized with the system clock e Rev 0 5 261 SILICON LABORATORIES
205. e device family The 64 k FLASH devices C8051F340 2 4 6 have 4 of XRAM space The 32 Flash devices C8051F341 3 5 7 have 2 k of XRAM space A separate 1 k Bytes of USB FIFO RAM is also included on all devices See Figure 1 4 for the MCU system memory map of the 64k Flash devices Note that on the 64k devices 1024 bytes at loca tions OXFCOO to OxFFFF are reserved PROGRAM DATA MEMORY DATA MEMORY RAM FLASH INTERNAL DATA ADDRESS SPACE OxFFFF OxFF Upper 128 RAM Special Function OxFCOO Indirect Addressing Register s OxFBFF 0x80 Only Direct Addressing Only Ox7F Direct and Indirect Addressing Lower 128 RAM FLASH 0x30 Direct and Indirect Ox2F Addressing In System P ble in 512 Oxa0 rogrammabie In 0x1F Byte Sectors 0x00 EXTERNAL DATA ADDRESS SPACE 0x0000 OxFFFF Off Chip XRAM Available only on devices with EMIF 0x1000 OxOFFF 0x07FF 0x0400 Figure 1 4 On Chip Memory Map for 64kB Devices C8051F340 2 4 6 0x0000 s Rev 0 5 23 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 1 3 Universal Serial Bus Controller The Universal Serial Bus Controller USBO is a USB 2 0 compliant Full or Low Speed function with inte grated transceiver and endpoint FIFO RAM A total of eight endpoint pipes are available a bi directional control endpoint EndpointO and three pairs of IN OUT endpoints Endpoints1 3 IN OUT A 1k Byte block of RAM is used for USB FIFO space This FIFO spa
206. e host For the first IN transaction firmware should load an IN packet into the Endpointo FIFO and set the INPRDY bit EOCSR 1 An interrupt will be generated when an IN packet is transmitted successfully Note that no interrupt will be generated if an IN request is received before firm ware has loaded a packet into the EndpointO FIFO If the requested data exceeds the maximum packet size for EndpointO as reported to the host the data should be split into multiple packets each packet should be of the maximum packet size excluding the last residual packet If the requested data is an inte ger multiple of the maximum packet size for EndpointO the last data packet should be a zero length packet signaling the end of the transfer Firmware should set the DATAEND bit to 1 after loading into the EndpointO FIFO the last data packet for a transfer Upon reception of the first IN token for a particular control transfer EndpointO is said to be in Transmit Mode In this mode only IN tokens should be sent by the host to EndpointO The SUEND bit EOCSR 4 is set to 1 ifa SETUP or OUT token is received while EndpointO is in Transmit Mode EndpointO will remain in Transmit Mode until any of the following occur 1 USBO receives an EndpointO SETUP or OUT token 2 Firmware sends a packet less than the maximum EndpointO packet size 3 Firmware sends a zero length packet Firmware should set the DATAEND bit EOCSR 3 to 1 when performing 2 an
207. e set to 10 the XRAM memory map is split into two areas on chip space and off chip space Effective addresses below the internal XRAM size boundary will access on chip XRAM space Effective addresses above the internal XRAM size boundary will access off chip space e 8 bit MOVX operations use the contents of EMIOCN to determine whether the memory access is on chip or off chip The upper 8 bits of the Address Bus A 15 8 are determined by EMIOCN and the lower 8 bits of the Address Bus A 7 0 are determined by RO or R1 All 16 bits of the Address Bus A 15 0 are driven in Bank Select mode e 16 bit MOVX operations use the contents of DPTR to determine whether the memory access is on chip or off chip and the full 16 bits of the Address Bus A 15 0 are driven during the off chip trans action 13 6 4 External Only When 3 2 are set to 11 all MOVX operations are directed to off chip space On chip XRAM is not visible to the CPU This mode is useful for accessing off chip memory located between 0x0000 and the internal XRAM size boundary 8 bit MOVX operations ignore the contents of EMIOCN The upper Address bits A 15 8 are not driven identical behavior to an off chip access in Split Mode without Bank Select described above This allows the user to manipulate the upper address bits at will by setting the Port state directly The lower 8 bits of the effective address A 7 0 are determined by the contents of
208. e set to logic I Future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0 selecting the feature s default state Detailed descriptions of the remaining SFRs are included in the sections of the datasheet associated with their corresponding sys tem function SFR Definition 9 1 DPL Data Pointer Low Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit Bito SFR Address 0x82 Bits7 0 DPL Data Pointer Low The DPL register is the low byte of the 16 bit DPTR DPTR is used to access indirectly addressed memory SFR Definition 9 2 DPH Data Pointer High Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0x83 Bits7 0 DPH Data Pointer High The DPH register is the high byte of the 16 bit DPTR DPTR is used to access indirectly addressed memory SFR Definition 9 3 SP Stack Pointer Bits7 0 SP Stack Pointer The Stack Pointer holds the location of the top of the stack The stack pointer is incremented before every PUSH operation The SP register defaults to 0x07 after reset e Rev 0 5 SILICON LABORATORIES R W R W R W R W R W R W R W R W Reset Value 00000111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit Bito SFR Address 0x81 85 C8051F340 1 2 3 4 5 6 7 S
209. eared by hardware when the CPU vectors to the interrupt service routine and must be cleared by software Setting the ECOMn and bits in the register enables Software Timer mode Important Note About Capture Compare Registers When writing a 16 bit value to the PCAO Capture Compare registers the low byte should always be written first Writing to PCAOCPLn clears the ECOMn bit to 0 writing to PCAOCPHn sets ECOMn to 1 Write to PCAOCPLn Reset Write to PCAOCPHn PCA Interrupt mp 7 PCAOCN w cle lclelc cic M PCAOCPLn PCAOCPHn FIR 1 F F F F F 6 43 2 1 0 n x100 00x Enabl vo m gt 16 bit Comparator Maton o o CA gt PCAOL PCAOH Timebase Figure 22 5 PCA Software Timer Mode Diagram e Rev 0 5 267 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 22 2 3 High Speed Output Mode In High Speed Output mode a module s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module s 16 bit capture compare register PCAOCPHn and PCAOCPLn Setting the TOGn MATn and ECOMn bits in the PCAOCPMn register enables the High Speed Output mode Important Note About Capture Compare Registers When writing a 16 bit value to the PCAO Capture Compare registers the low byte should always be written first Writing to PCAOCPLn clear
210. eatures or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Silicon Laboratories products are not designed intended or authorized for use in applications intended to support or sustain life or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holders 282 Rev 0 5 SILICON LABORATORIES
211. ection of Table 16 2 for a list of endpoint control status registers Important Note The USB clock must be active when accessing USB registers 8051 USB Controller aA Interrupt Registers SFRs FIFO Access Common Registers Register EndpointO Control Status Registers Endpoint1 Control Status Registers Endpoint2 Control Status Registers Figure 16 2 USBO Register Access Scheme Endpoint3 Control Status Registers 166 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 16 2 USBOADR USBO Indirect Address R W R W R W R W R W R W R W R W Reset Value BUSY AUTORD USBADDR 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bit SFR Address 0x96 Bits7 BUSY USBO Register Read Busy Flag This bit is used during indirect USBO register accesses Software should write 1 to this bit to initiate a read of the USBO register targeted by the USBADDR bits USBOADR 5 0 The target address and BUSY bit may be written in the same write to USBOADR After BUSY is set to 1 hardware will clear BUSY when the targeted register data is ready in the USBODAT register Software should check BUSY for 0 before writing to USBODAT Write 0 No effect 1 A USBO indirect register read is initiated at the address specified by the USBADDR bits Read 0 USBODAT register data is valid 1 USBO is busy accessing an indirect register USBODAT register dat
212. ed Bit4 CPOFIF ComparatorO Falling Edge Flag 0 No Falling Edge has occurred since this flag was last cleared 1 ComparatorO Falling Edge Interrupt has occurred Bits3 2 CPOHYP1 0 ComparatorO Positive Hysteresis Control Bits 00 Positive Hysteresis Disabled 01 Positive Hysteresis 5 mV 10 Positive Hysteresis 10 mV 11 Positive Hysteresis 20 mV 51 0 1 0 ComparatorO Negative Hysteresis Control Bits 00 Negative Hysteresis Disabled 01 Negative Hysteresis 5 mV 10 Negative Hysteresis 10 mV 11 Negative Hysteresis 20 mV Reset Value 00000000 SFR Address 0x9B 62 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 7 2 CPTOMX Comparator0 MUX Selection R W R W R W R W R W R W R W Reset Value CMXON2 CMXON1 CMXONO 2 CMXOP1 CMXOPO 00000000 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address Ox9F Bit7 UNUSED Read 0b Write don t care Bits6 4 CMXON2 CMXONO ComparatorO Negative Input MUX Select These bits select which Port pin is used as the ComparatorO negative input CMXON1 CMXON1 CMXONO Negative Input Negative Input 32 pin Package 48 pin Package P1 1 P2 1 P1 5 P2 6 P2 1 P3 5 P2 5 P4 4 PO 1 0 4 Bit3 UNUSED Read 0b Write don t care Bits2 0 2 ComparatorO Positive Input MUX Select These bits select
213. ed should be tied to Vpp 2 Output current is total regulator output including any current required by the C8051F34x 3 The minimum input voltage is 2 70 V or VDD max load whichever is greater e Rev 0 5 69 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 From VBUS VBUS Sense 5 V In Voltage Regulator REGO 3 V Out To3V Power Net Device Power Net From VBUS VBUS Sense From5V Power Net 5 V In Voltage Regulator REGO 3 V Out To3V Power Net Device Power Net Figure 8 2 REGO Configuration USB Self Powered 70 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 From VBUS VBUS Sense 5 V In Voltage Regulator REGO 3 V Out From 3 V Power Net Device Power Net VBUS Sense From 5 V Power Net 5VIn Voltage Regulator REGO 3 V Out To3V Power Net Device Power Net Figure 8 4 REGO Configuration No USB Connection s Rev 0 5 71 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 8 1 REGOCN Voltage Regulator Control R W R R W R W R W R W R W R W Reset Value REGDIS VBSTAT VBPOL REGMOD Reserved Reserved Reserved Reserved 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0xC9 Bit7 REGDIS Voltage Regulator Disable 0 Voltage Regulator Enabled 1 Voltage Regulator Disabled Bit6 VBSTAT VBUS Signal Status 0 VBUS signal currently absent device not attached t
214. ei Ex a eo E I it 181 16 10 3 EndpointO OUT Transactloris gt iino cr rar een oit E Rc 182 16 1 T Gotifig ririd Endpolnts T 3 RD IS B IM MEE 184 16 12 Controllng Endpoinis 1 9 184 16 12 1 Endpoints1 3 IN Interrupt or Bulk 184 16 12 2 Endpoints1 3 IN Isochronous 185 16 13 Controlling Endpoints1 3 OUT isi nm doter ta eeu ib coreano ine 187 16 13 1 Endpoints1 3 OUT Interrupt or Bulk 187 16 13 2 Endpoints1 3 OUT Isochronous 188 17 SMBUS S 193 17 1 Supporting Documents orci Aou oderit e Imo pictus 194 17 2 5 5 COMMU ANON se eso ta btc torte on 194 Rev 0 5 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 17 3 SMBus ODSIalOl eerte eerte pe ian roe obch Zana i 194 d ed c AIO A 195 17 3 2 Glosk LOW Goes neo Xt in nec du rede lak 196 17 9 3 OGL LOW TIMEOUT nra et uo o oet Erde 196 17 3 4 SCL High SMBus Free 196 17 4 Usa the SMBUS i irae ett kr 196 17 4 1 SMBus Configura
215. ement modes Although the CIP 51 has Idle and Stop modes built in as with any standard 8051 architecture power management of the entire MCU is better accomplished through system clock and individual peripheral management Each analog peripheral can be disabled when not in use and placed in low power mode Digital peripherals such as timers or serial buses draw little power when they are not in use Turning off the oscillators lowers power consumption considerably however a reset is required to restart the MCU The internal oscillator can be placed in Suspend mode see Section 14 Oscillators on page 135 In Suspend mode the internal oscillator is stopped until a non idle USB event is detected or the VBUS input signal matches the polarity selected by the VBPOL bit in register REGOCN SFR Definition 8 1 9 4 1 Idle Mode Setting the Idle Mode Select bit 0 causes the CIP 51 to halt the CPU and enter Idle mode as soon as the instruction that sets the bit completes execution All internal registers and memory maintain their original data All analog and digital peripherals can remain active during Idle mode Idle mode is terminated when an enabled interrupt is asserted or a reset occurs The assertion of an enabled interrupt will cause the Idle Mode Selection bit 0 to be cleared and the CPU to resume operation The pending interrupt will be serviced and the next instruction to be executed after the return from interrupt
216. ength packet Firmware should set the DATAEND bit EOCSR 3 to 1 when the expected amount of data has been received The SIE will transmit a STALL condition if the host sends an OUT packet after the DATAEND bit has been set by firmware An interrupt will be generated with the STSTL bit EOCSR 2 set to 1 after the STALL is transmitted 182 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 USB Register Definition 16 17 EOCSR USBO EndpointO Control R W R W R W R R W R W R W R Reset Value SSUEND SOPRDY SDSTL SUEND DATAEND STSTL INPRDY OPRDY 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito USB Address 0x11 Bit7 SSUEND Serviced Setup End Write Software should set this bit to 1 after servicing a Setup End bit SUEND event Hardware clears the SUEND bit when software writes 1 to SSUEND Read This bit always reads 0 Bit6 SOPRDY Serviced OPRDY Write Software should write 1 to this bit after servicing a received EndpointO packet The OPRDY bit will be cleared by a write of 1 to SOPRDY Read This bit always reads 0 Bit5 SDSTL Send Stall Software can write 1 to this bit to terminate the current transfer due to an error condition unexpected transfer request etc Hardware will clear this bit to 0 when the STALL hand shake is transmitted Bit4 SUEND Setup End Hardware sets this read only bit to 1 when a control transaction ends before s
217. epeated START Send NACK to indicate last byte and send repeated START Send ACK and switch to Master Transmitter Mode write to SMBODAT before clearing SI Send NACK and switch to Master Transmitter Mode write to SMBODAT before clearing SI SILICON LABORATORIES Rev 0 5 209 C8051F340 1 2 3 4 5 6 7 Table 17 4 SMBus Status Decoding Continued Values Values Read Written 8 a Current SMbus State Typical Response Options s 32 lt o x S9 5 mia 559 gt ololo A slave byte was transmitted No action reguired expect ollox NACK received ing STOP condition A slave byte was transmitted Load SMBODAT with next E 5 2 93009 ED ACK received data byte to transmit Bai al 0 1X A Slave byte was transmitted No action required expect 0lolx error detected ing Master to end transfer 01001 1 X X A STOP was detected while an No action required transfer ollox addressed Slave Transmitter complete Acknowledge received 01011 slave address was received address 110 X ACK reguested Do not acknowledge received address Acknowledge received 01011 0010 address Lost arbitration as master slave Do not acknowledge 01010 1 1 X Jaddress received received address requested Reschedule failed transfer do not ack
218. erated 9 3 3 Interrupt Priorities Each interrupt source can be individually programmed to one of two priority levels low or high A low prior ity interrupt service routine can be preempted by a high priority interrupt A high priority interrupt cannot be preempted Each interrupt has an associated interrupt priority bit in an SFR IP or EIP2 used to configure its priority level Low priority is the default If two interrupts are recognized simultaneously the interrupt with the higher priority is serviced first If both interrupts have the same priority level a fixed priority order is used to arbitrate given in Table 9 4 9 3 4 Interrupt Latency Interrupt response time depends on the state of the CPU when the interrupt occurs Pending interrupts are sampled and priority decoded each system clock cycle Therefore the fastest possible response time is 6 system clock cycles 1 clock cycle to detect the interrupt and 5 clock cycles to complete the L CALL to the ISR If an interrupt is pending when a RETI is executed a single instruction is executed before an LCALL is made to service the pending interrupt Therefore the maximum response time for an interrupt when no other interrupt is currently being serviced or the new interrupt is of greater priority occurs when the CPU is performing an RETI instruction followed by a DIV as the next instruction In this case the response time is 20 system clock cycles 1 clock cycle to detect the interrupt
219. errupt enabled Bits1 0 CP1MD1 CP1MDO Comparator1 Mode Select These bits select the response time for Comparator1 Mode CP1MD1 CP1MDO CP1 Response Time 0 0 0 Fastest Response 1 0 2 1 0 3 1 1 Lowest Power See Table 7 1 for response time parameters e Rev 0 5 67 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 7 1 Comparator Electrical Characteristics Vpp 3 0 V 40 to 85 C unless otherwise noted All specifications apply to both Comparator0 and Comparator1 unless otherwise noted Note Vcm is the common mode voltage on CP0 and CPO Parameter Conditions Min Typ Max Units Response Time CPO CPO 100 mV 100 ns Mode 0 Vem 1 5 V CP0 CPO 100 mV 250 ns Response Time CPO CPO 100 mV 175 ns Mode 1 Vcm 1 5 V 0 CPO 100 mV 500 ns Response Time CPO CPO 100 mV 320 ns Mode 2 Vcm 1 5 V 0 CPO 100 mV 1100 ns Response Time CPO CPO 100 mV 1050 ns Mode 3 Vem 1 5 V CPO CPO 100 mV 5200 ns E mee Rejection 15 4 mV V Positive Hysteresis 1 CPOHYP1 0 00 0 1 mV Positive Hysteresis 2 CPOHYP 1 0 01 2 5 10 mV Positive Hysteresis 3 1 0 10 7 10 20 mV Positive Hysteresis 4 CPOHYP1 0 11 15 20 30 mV Negative Hysteresis 1 1 0 00 0 1 mV Negative Hysteresis 2 CP
220. ets the masking of the CP1 interrupt 0 Disable CP1 interrupts 1 Enable interrupt requests generated by the CP1RIF or CP1FIF flags ECPO Enable Comparator0 Interrupt This bit sets the masking of the CPO interrupt 0 Disable CPO interrupts 1 Enable interrupt requests generated by the CPORIF or CPOFIF flags EPCAO Enable Programmable Counter Array PCAO Interrupt This bit sets the masking of the PCAO interrupts 0 Disable all PCAO interrupts 1 Enable interrupt requests generated by PCAO EADCO Enable ADCO Conversion Complete Interrupt This bit sets the masking of the ADCO Conversion Complete interrupt 0 Disable ADCO Conversion Complete interrupt 1 Enable interrupt requests generated by the ADOINT flag EWADCO Enable Window Comparison ADCO Interrupt This bit sets the masking of ADCO Window Comparison interrupt 0 Disable ADCO Window Comparison interrupt 1 Enable interrupt requests generated by ADCO Window Compare flag ADOWINT EUSBO Enable USBO Interrupt This bit sets the masking of the USBO interrupt 0 Disable all USBO interrupts 1 Enable interrupt requests generated by USBO ESMBO Enable SMBus SMBO Interrupt This bit sets the masking of the SMBO interrupt 0 Disable all SMBO interrupts 1 Enable interrupt requests generated by SMBO 92 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 R W PT3 SFR Definition 9 10 EIP1 Extended Interrupt Priority
221. evice In multi mas ter mode slave devices can be addressed individually if needed using general purpose I O pins Figure 20 2 shows a connection diagram between two master devices in multiple master mode 3 wire single master mode is active when NSSMD1 SPIOCN 3 0 and NSSMDO SPIOCN 2 0 In this mode NSS is not used and is not mapped to an external port pin through the crossbar Any slave devices that must be addressed in this mode should be selected using general purpose I O pins Figure 20 3 shows a connection diagram between a master device in 3 wire master mode and a slave device 4 wire single master mode is active when NSSMD1 SPIOCN 3 1 In this mode NSS is configured as an output pin and can be used as a slave select signal for a single SPI device In this mode the output value of NSS is controlled in software with the bit NSSMDO SPIOCN 2 Additional slave devices can be addressed using general purpose pins Figure 20 4 shows a connection diagram for a master device in 4 wire master mode and two slave devices e Rev 0 5 231 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Figure 20 2 Multiple Master Mode Connection Diagram Figure 20 3 3 Wire Single Master and Slave Mode Connection Diagram Figure 20 4 4 Wire Single Master Mode and Slave Mode Connection Diagram amp 232 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 20 3 SPIO Slave Mode Operation When SPIO is en
222. f KF C x Vpp where f frequency of clock in MHz C capacitor value the XTAL2 pin in pF Vpp gt Power Supply on MCU in volts Rev 0 5 141 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 14 4 4x Clock Multiplier The 4x Clock Multiplier allows a 12 MHz oscillator to generate the 48 MHz clock required for Full Speed USB communication see Section 16 4 USB Clock Configuration on page 170 A divided version of the Multiplier output can also be used as the system clock See Section 14 5 for details on system clock and USB clock source selection The 4x Clock Multiplier is configured via the CLKMUL register The procedure for configuring and enabling the 4x Clock Multiplier is as follows Reset the Multiplier by writing 0x00 to register CLKMUL Select the Multiplier input source via the MULSEL bits Enable the Multiplier with the MULEN bit CLKMUL 0x80 Delay for gt 5 us Initialize the Multiplier with the MULINIT bit CLKMUL 0 0 Poll for MULRDY gt 1 Important Note When using an external oscillator as the input to the 4x Clock Multiplier the exter nal source must be enabled and stable before the Multiplier is initialized See Section 14 5 for details on selecting an external oscillator source SFR Definition 14 5 CLKMUL Clock Multiplier Control R W R W R R W R W R W R W R W Reset Value MULEN MULINIT MULRDY MULSEL 00000000
223. finitions Table 4 1 Pin Definitions for the C8051F340 1 2 3 4 5 6 7 Figure 4 1 TQFP 48 Pinout Diagram Top Table 4 2 TQFP 48 Package Figure 4 2 TOFP 48 Package Diagram wisi ciere ce rn recen Figure 4 3 LQFP 32 Pinout Diagram Top View Table 4 3 LQFP 32 Package Dimensions esses Figure 4 4 LQFP 32 Package 5 10 Bit ADC ADCO Figure 5 1 ADCO Functional Block Figure 5 2 Temperature Sensor Transfer Figure 5 3 Temperature Sensor Error with 1 Point Calibration VREF 2 40 V Figure 5 4 10 Bit ADC Track and Conversion Example Timing Figure 5 5 ADCO Equivalent Input Circuits sss Figure 5 6 ADC Window Compare Example Right Justified Single Ended Data Figure 5 7 ADC Window Compare Example Left Justified Single Ended Data Figure 5 8 ADC Window Compare Example Right Justified Differential Data Figure 5 9 ADC Window Compare Example Left Justified Differential Data Table 5 1 ADCO Electrical Characteristics sess 6 Voltage Reference Figure 6 1 Voltage Reference Fun
224. g is set to logic 1 at the end of the transfer If interrupts are enabled an interrupt request is generated when the SPIF flag is set While the SPIO master transfers data to a slave on the MOSI line the addressed SPI slave device simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full duplex operation Therefore the SPIF flag serves as both a transmit complete and receive data ready flag The data byte received from the slave is transferred MSB first into the master s shift register When a byte is fully shifted into the register it is moved to the receive buffer where it can be read by the processor by reading SPIODAT When configured as a master SPIO can operate in one of three different modes multi master mode 3 wire single master mode and 4 wire single master mode The default multi master mode is active when NSSMD 1 SPIOCN 3 0 and NSSMDO SPIOCN 2 1 In this mode NSS is an input to the device and is used to disable the master SPIO when another master is accessing the bus When NSS is pulled low in this mode MSTEN SPIOCN 6 and SPIEN SPIOCN 0 are set to 0 to disable the SPI master device and a Mode Fault is generated MODF SPIOCN 5 1 Mode Fault will generate an interrupt if enabled SPIO must be manually re enabled in software under these circumstances In multi master systems devices will typically default to being slave devices while they are not acting as the system master d
225. hdog Timer is enabled with the system clock divided by 12 as its clock source Section 22 3 Watchdog Timer Mode on page 272 details the use of the Watchdog Timer Program execution begins at location 0x0000 VDD Supply Monitor Enable m D 7 Reset o RST KA Comparator 0 wired OR ox gt gt X CORSEF V Missing gt gt Clock Detector shot WDT Software Reset SWRSF EN Errant EN FLASH Internal LF Operation o Oscillator d als Els Oc Os 215 z5 Internal HF Oscillator i System Clock USB VBUS NIS CIP 51 Controller Transition A Microcontroller System Reset xrALiDX 94 Eternal Core Oscillator Clock Select XTAL2 Xk Brive Extended Interrupt Handler Figure 11 1 Reset Sources s Rev 0 5 101 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 11 1 Power On Reset During power up the device is held in a reset state and the RST pin is driven low until Vpp settles above Vast Power On Reset delay TpoRpelay occurs before the device is released from reset this delay is typically less than 0 3 ms Figure 11 2 plots the power on and Vpp monitor reset timing On exit from a power on reset the PORSF flag RSTSRC 1 is set by hardware to logic 1 W
226. he first register RO of register bank 1 Thus if more than one register bank is to be used the SP should be initialized to a location in the data memory not being used for data storage The stack depth can extend up to 256 bytes 80 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 9 2 6 Special Function Registers The direct access data memory locations from 0x80 to OxFF constitute the special function registers SFRs The SFRs provide control and data exchange with the CIP 51 s resources and peripherals The CIP 51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub systems unique to the MCU This allows the addition of new functionality while retaining compatibility with the MCS 51 instruction set Table 9 2 lists the SFRs imple mented in the CIP 51 System Controller The SFR registers are accessed anytime the direct addressing mode is used to access memory locations from 0x80 to OxFF SFRs with addresses ending in 0x0 or 0x8 e g PO TCON SCONO IE etc are bit addressable as well as byte addressable All other SFRs are byte addressable only Unoccupied addresses in the SFR space are reserved for future use Accessing these areas will have an indeterminate effect and should be avoided Refer to the corresponding pages of the datasheet as indicated in Table 9 3 for a detailed description of each register Table 9 2 Special F
227. he clock supplied to Timer 1 and T1H is the high byte of Timer 1 reload value Timer 1 clock frequency is selected as described in Section 21 Timers on page 243 A quick reference for typical baud rates using the internal oscillator is given in Table 18 1 Note that the internal oscillator may still generate the system clock if an external oscillator is driving Timer 1 18 2 Operational Modes UARTO provides standard asynchronous full duplex communication The UART mode 8 bit or 9 bit is selected by the SOMODE bit SCONO 7 Typical UART connection options are shown below 212 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 C8051Fxxx TX C8051Fxxx RX Figure 18 3 UART Interconnect Diagram 18 2 1 8 Bit UART 8 Bit UART mode uses a total of 10 bits per data byte one start bit eight data bits LSB first and one stop bit Data are transmitted LSB first from the TXO pin and received at the RXO pin On receive the eight data bits are stored in SBUFO and the stop bit goes into RB80 SCONO 2 Data transmission begins when software writes a data byte to the SBUFO register The TIO Transmit Inter rupt Flag SCONO 1 is set at the end of the transmission the beginning of the stop bit time Data recep tion can begin any time after the RENO Receive Enable bit SCONO 4 is set to logic 1 After the stop bit is received the data byte w
228. heir weak pull up digital driver and digital receiver disabled 0 Corresponding P3 n pin is configured as an analog input 1 Corresponding P3 n pin is not configured as an analog input Note P3 1 3 7 are only available on 48 pin devices SFR Definition 15 18 PSMDOUT Port3 Output Mode R W R W Reset Value 00000000 Bit1 Bito SFR Address OxA7 Bits7 0 Output Configuration Bits for P3 7 P3 0 respectively ignored if corresponding bit in regis ter PSMDIN is logic 0 0 Corresponding P3 n Output is open drain 1 Corresponding P3 n Output is push pull Note P3 1 3 7 are only available on 48 pin devices s Rev 0 5 159 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 15 19 P3SKIP Port3 Skip R W R W R W R W R W R W R W Reset Value 00000000 Bit6 Bit5 Bit4 Bit2 Bit Bito SFR Address OxDF Bits7 0 P3SKIP 3 0 Port3 Crossbar Skip Enable Bits These bits select Port pins to be skipped by the Crossbar Decoder Port pins used as ana log inputs for ADC or Comparator or used as special functions VREF input external oscil lator circuit CNVSTR input should be skipped by the Crossbar 0 Corresponding P3 n pin is not skipped by the Crossbar 1 Corresponding P3 n pin is skipped by the Crossbar Note P3 1 3 7 are only available on 48 pin devices SFR Definition 15 20 P4 Port4 Latch R W R W R W R W R W R W R W Reset Value P4 6 P4 5
229. hen PORSF is set all of the other reset flags in the RSTSRC Register are indeterminate PORSF is cleared by all other resets Since all resets cause program execution to begin at the same location 0x0000 software can read the PORSF flag to determine if a power up was the cause of reset The content of internal data mem ory should be assumed to be undefined after a power on reset The Vpp monitor is enabled following a power on reset Software can force a power on reset by writing 1 to the PINRSF bit in register RSTSRC 2 70 2 4 2 0 Logic HIGH T PORDelay Logic LOW 242222 VDD Power On Monitor Reset Reset Figure 11 2 Power On and Vpp Monitor Reset Timing 102 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 11 2 Power Fail Reset Vpp Monitor When a power down transition or power irregularity causes Vpp to drop below Vpsr the power supply monitor will drive the RST pin low and hold the CIP 51 in a reset state see Figure 11 2 When Vpp returns to a level above Vpsr the CIP 51 will be released from the reset state Note that even though inter nal data memory contents are not altered by the power fail reset it is impossible to determine if Vpp dropped below the level required for data retention If the PORSF flag reads 1 the data may no longer be valid The Vpp monitor is enabled after power on resets however its defined state enabled disabled is not al
230. ieves data from the receive FIFO When read the oldest byte in the receive FIFO is returned and removed from the FIFO Up to three bytes may be held in the FIFO If there are additional bytes available in the FIFO the RI1 bit will remain at logic 1 even after being cleared by software SFR Definition 19 4 SBCON1 UART1 Baud Rate Generator Control R W R W R W R W R W R W R W R W Reset Value Reserved SB1RUN Reserved Reserved Reserved Reserved SB1PS1 SB1PSO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito Ad SFR Address OXAC Bit7 RESERVED Read 0b Must write Ob Bit6 SB1RUN Baud Rate Generator Enable 0 Baud Rate Generator is disabled UART1 will not function 1 Baud Rate Generator is enabled Bits5 2 RESERVED Read 0000b Must write 0000b Bits1 0 SB1PS 1 0 Baud Rate Prescaler Select 00 Prescaler 12 01 Prescaler 4 10 Prescaler 48 11 Prescaler 1 226 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 19 5 SBRLH1 UART1 Baud Rate Generator High Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address OxB5 Bits7 0 SBRLH 1 7 0 High Byte of reload value for UART1 Baud Rate Generator SFR Definition 19 6 SBRLL1 UART1 Baud Rate Generator Low Byte R W R W R W R W R W R W R W R W Reset Value 00000000
231. ift register and the THRE1 bit will be set to 1 If a transmission is in progress the data will remain in the Transmit Holding Register until the current transmission is complete The TI1 Transmit Interrupt Flag SCON1 1 will be set at the end of any transmission the beginning of the stop bit time If enabled an interrupt will occur when T11 is set If the extra bit function is enabled XBE1 1 and the parity function is disabled PE1 0 the value of the TBX1 SCON1 3 bit will be sent in the extra bit position When the parity function is enabled PE1 1 hardware will generate the parity bit according to the selected parity type selected with S1PT 1 0 and append it to the data field Note when parity is enabled the extra bit function is not available 19 3 2 Data Reception Data reception can begin any time after the REN1 Receive Enable bit 5 1 4 is set to logic 1 After the stop bit is received the data byte will be stored in the receive FIFO if the following conditions are met the receive FIFO 3 bytes deep must not be full and the stop bit s must be logic 1 In the event that the receive FIFO is full the incoming byte will be lost and a Receive FIFO Overrun Error will be generated 1 in register SCON1 will be set to logic 1 If the stop bit s were logic 0 the incoming data will not be stored in the receive FIFO If the reception conditions are met the data is stored in the receive FIFO and th
232. ill be loaded into the SBUFO receive register if the following conditions are met RIO must be logic 0 and if MCEO is logic 1 the stop bit must be logic 1 In the event of a receive data over run the first received 8 bits are latched into the SBUFO receive register and the following overrun data bits are lost If these conditions are met the eight bits of data is stored in SBUFO the stop bit is stored in RB80 and the RIO flag is set If these conditions are not met SBUFO and RB80 will not be loaded and the RIO flag will not be set An interrupt will occur if enabled when either TIO or RIO is set MARK START DO D1 D2 D3 D4 D5 D6 D7 STOP SPACE BIT BIT Jd M 9 3H ___ _____4____ ___ ___ GERE REANO AIE BITSAMPLING i i Figure 18 4 8 Bit UART Timing Diagram s Rev 0 5 213 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 18 2 2 9 Bit UART 9 bit UART mode uses a total of eleven bits per data byte a start bit 8 data bits LSB first a programma ble ninth data bit and a stop bit The state of the ninth transmit data bit is determined by the value in TB80 SCONO 3 which is assigned by user software It can be assigned the value of the parity flag bit P in reg ister PSW for error detection or used in multiprocessor communications On receive the ninth data bit goes into RB80 SCONO 2 and the stop bit is ignored Data transmission begins
233. imer 2 high byte overflows from OxFF to 0x00 In 16 bit mode this will occur when Timer 2 overflows from OxFFFF to 0x0000 When the Timer 2 interrupt is enabled setting this bit causes the CPU to vector to the Timer 2 interrupt service routine TF2H is not automatically cleared by hardware and must be cleared by software Bit6 TF2L Timer 2 Low Byte Overflow Flag Set by hardware when the Timer 2 low byte overflows from OxFF to 0x00 When this bit is set an interrupt will be generated if TF2LEN is set and Timer 2 interrupts are enabled TF2L will set when the low byte overflows regardless of the Timer 2 mode This bit is not automat ically cleared by hardware Bit5 TF2LEN Timer 2 Low Byte Interrupt Enable This bit enables disables Timer 2 Low Byte interrupts If TF2LEN is set and Timer 2 inter rupts are enabled an interrupt will be generated when the low byte of Timer 2 overflows 0 Timer 2 Low Byte interrupts disabled 1 Timer 2 Low Byte interrupts enabled Bit4 T2CE Timer 2 Capture Enable 0 Capture function disabled 1 Capture function enabled The timer is in capture mode with the capture event selected by bit T2CSS Each time a capture event is received the contents of the Timer 2 registers TMR2H and TMR2L are latched into the Timer 2 reload registers TMR2RLH and TMR2RLH and a Timer 2 interrupt is generated if enabled Bit3 T2SPLIT Timer 2 Split Mode Enable When this bit is set Timer 2 operates as two 8 bit timers with aut
234. imer Enable If this bit is set PCA Module 4 is used as the watchdog timer 0 Watchdog Timer disabled 1 PCA Module 4 enabled as Watchdog Timer Bit5 WDLCK Watchdog Timer Lock This bit enables and locks the Watchdog Timer When WDLCK is set to 1 the Watchdog Timer may not be disabled until the next system reset 0 Watchdog Timer unlocked 1 Watchdog Timer enabled and locked Bit4 UNUSED Read 06 Write don t care Bits3 1 CPS2 CPS0 PCA Counter Timer Pulse Select These bits select the timebase source for the PCA counter CPS2 CPS1 CPSO Timebase 0 0 0 System clock divided by 12 0 0 1 System clock divided by 4 0 1 0 Timer 0 overflow 0 1 1 High to low transitions on max rate system clock divided by 4 1 0 0 System clock 1 0 1 External clock divided by 8 1 1 0 Reserved 1 1 1 Reserved Note External oscillator source divided by 8 is synchronized with the system clock Bito ECF PCA Counter Timer Overflow Interrupt Enable This bit sets the masking of the PCA Counter Timer Overflow CF interrupt 0 Disable the CF interrupt 1 Enable a PCA Counter Timer Overflow interrupt request when CF 7 is set Note When the WDTE bit is set to 1 the PCAOMD register cannot be modified To change the contents of the PCAOMD register the Watchdog Timer must first be disabled e Rev 0 5 275 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7
235. interrupt the processor when a complete data packet has been received appropriate handshaking signals are automat ically generated by the SIE When transmitting data the SIE will interrupt the processor when a complete data packet has been transmitted and the appropriate handshake signal has been received The SIE will not interrupt the processor when corrupted erroneous packets are received 16 10 EndpointO EndpointO is managed through the USB register EOCSR USB Register Definition 16 17 The INDEX reg ister must be loaded with 0x00 to access the EOCSR register An Endpointo interrupt is generated when 1 2 A data packet OUT or SETUP has been received and loaded into the EndpointO FIFO The OPRDY bit EOCSR 0 is set to 1 by hardware An IN data packet has successfully been unloaded from the EndpointO FIFO and transmitted to the host INPRDY is reset to 0 by hardware An IN transaction is completed this interrupt generated during the status stage of the transac tion Hardware sets the STSTL bit EOCSR 2 after a control transaction ended due to a protocol violation Hardware sets the SUEND bit EOCSR 4 because a control transfer ended before firmware 180 sets the DATAEND bit EOCSR 3 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 The EOCNT register USB Register Definition 16 18 holds the number of received data bytes in the EndpointO FIFO Hardware will automatically dete
236. ions for Port O are given in Table 15 1 on page 162 XBRO XBR1 XBR2 PnMDOUT PnSKIP Registers PnMDIN Registers Priority Decoder Highest Priority 2 VO c Outputs T P1 0 Digital 8 si CP1 2 Crossbar Cells oi Outputs AX PU ai ai SYSCLK al et 2 P2 0 oi 6 vO M 2 i O Lowest 7 2 e Priority UART1 Cells P3 7 Note P3 1 P3 7 and UART1 only available on 48 pin package Port Latches Figure 15 1 Port O Functional Block Diagram Port 0 through Port 3 s Rev 0 5 147 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 WEAK PULLUP PUSH PULL DE WEAK PORT OUTENABLE Dx PORT PAD PORT OUTPUT H OCH Us 0 zi U Analog Select PORT INPUT ANALOG INPUT Figure 15 2 Port I O Cell Block Diagram amp 148 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 15 1 Priority Crossbar Decoder The Priority Crossbar Decoder Figure 15 3 assigns a priority to each I O function starting at the top with UARTO When a digital resource is selected the least significant unassigned Port pin is assigned to that resource excluding UARTO which is always at pins 4 and 5 If a Port pin is assigned the Crossbar skips that pin when assigning the next selected resource Additionally the Crossbar will skip Port pins whose associated bits in the PnSKIP registe
237. ip pull up resistor if enabled appears on the D pin Bits4 0 of register USBOXCN can be used for Transceiver testing as described in SFR Definition 16 1 The pull up resistor is enabled only when VBUS is present see Section 8 2 VBUS Detection on page 69 for details on VBUS detection Important Note The USB clock should be active before the Transceiver is enabled 164 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 16 1 USBOXCN USBO Transceiver Control R W R W R W R W R W R R R Reset Value PREN PHYEN SPEED PHYTST1 PHYTSTO DFREC Dp Dn 00000000 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0xD7 Bit7 PREN Internal Pull up Resistor Enable The location of the pull up resistor D or D is determined by the SPEED bit 0 Internal pull up resistor disabled device effectively detached from the USB network 1 Internal pull up resistor enabled when VBUS is present device attached to the USB net work Bit6 PHYEN Physical Layer Enable This bit enables disables the USBO physical layer transceiver 0 Transceiver disabled suspend 1 Transceiver enabled normal Bit5 SPEED USBO Speed Select This bit selects the USBO speed 0 USBO operates as a Low Speed device If enabled the internal pull up resistor appears on the D line 1 USBO operates as a Full Speed device If enabled the internal pull up resistor appears on the D line Bits4 3 PHYTST1 0 Physical Layer Test
238. is 40 ns and the minimum instruction time is roughly 20 ns the prefetch engine is necessary for full speed code execution Instructions are read from FLASH memory two bytes at a time by the prefetch engine and given to the CIP 51 processor core to execute When running linear code code without any jumps or branches the prefetch engine allows instructions to be executed at full speed When a code branch occurs the processor may be stalled for up to two clock cycles while the next set of code bytes is retrieved from FLASH memory The FLRT bit FLSCL 4 determines how many clock cycles are used to read each set of two code bytes from FLASH When operating from a system clock of 25 MHz or less the FLRT bit should be set to 0 so that the prefetch engine takes only one clock cycle for each read When operating with a system clock of greater than 25 MHz up to 48 MHz the FLRT bit should be set to 1 so that each prefetch code read lasts for two clock cycles SFR Detinition 10 1 PFEOCN Prefetch Engine Control R R R W R R R R R W Reset Value PFEN FLBWE 00100000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address OxAF Bits 7 6 Unused Read 00b Write Don t Care Bit 5 PFEN Prefetch Enable This bit enables the prefetch engine 0 Prefetch engine is disabled 1 Prefetch engine is enabled Bits 4 1 Unused Read 0000b Write Don t Care Bit 0 FLBWE FLASH Block Write Enable This bit allows block writes to FLASH mem
239. is detected If STA is set by software as an active Master a repeated START will be generated after the next ACK cycle Read 0 No Start or repeated Start detected 1 Start or repeated Start detected STO SMBus Stop Flag Write 0 No STOP condition is transmitted 1 Setting STO to logic 1 causes a STOP condition to be transmitted after the next ACK cycle When the STOP condition is generated hardware clears STO to logic 0 If both STA and STO are set a STOP condition is transmitted followed by a START condition Read 0 No Stop condition detected 1 Stop condition detected if in Slave Mode or pending if in Master Mode ACKRQ SMBus Acknowledge Request This read only bit is set to logic 1 when the SMBus has received a byte and needs the ACK bit to be written with the correct ACK response value ARBLOST SMBus Arbitration Lost Indicator This read only bit is set to logic 1 when the SMBus loses arbitration while operating as a transmitter A lost arbitration while a slave indicates a bus error condition ACK SMBus Acknowledge Flag This bit defines the out going ACK level and records incoming ACK levels It should be writ ten each time a byte is received when ACKRQ 1 or read after each byte is transmitted 0 A not acknowledge has been received if in Transmitter Mode OR will be transmitted if in Receiver Mode 1 An acknowledge has been received if in Transmitter Mode OR will be transmitted if in Receive
240. isabled 1 SDA Extended Setup and Hold Times enabled SMBTOE SMBus SCL Timeout Detection Enable This bit enables SCL low timeout detection If set to logic 1 the SMBus forces Timer 3 to reload while SCL is high and allows Timer 3 to count when SCL goes low Timer 3 should be programmed to generate interrupts at 25 ms and the Timer 3 interrupt service routine should reset SMBus communication SMBFTE SMBus Free Timeout Detection Enable When this bit is set to logic 1 the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods SMBCS1 SMBCS0 SMBus Clock Source Selection These two bits select the SMBus clock source which is used to generate the SMBus bit rate The selected device should be configured according to Equation 17 1 SMBCS1 SMBCSO 0 0 SMBus Clock Source Timer 0 Overflow 0 1 Timer 1 Overflow 1 0 Timer 2 High Byte Overflow 1 1 Timer 2 Low Byte Overflow 200 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 17 4 2 SMBOCN Control Register SMBOON is used to control the interface and to provide status information see SFR Definition 17 2 The higher four bits of SMBOCN MASTER TXMODE STA and STO form a status vector that can be used to jump to service routines MASTER and TXMODE indicate the master slave state and transmit receive modes respectively STA and STO indicate that a START and or STOP has been detected
241. it in register EMIOCF must be set to 1 When this bit is set the USB FIFO space is mapped into XRAM space at addresses 0x0400 to 0x07FF The normal XRAM on chip or external at the same addresses cannot be accessed when the USBFAE bit is set to 1 Important Note The USB clock must be active when accessing FIFO space OxFFFF 0x0800 0x07FF 0x07C0 0x07BF 0x0740 0x073F USB FIFO Space USB Clock Domain 0x0640 0x063F 0x0440 0x043F 0x0400 Ox03FF 0x0000 Figure 13 1 USB FIFO Space and XRAM Memory Map with USBFAE set to 1 118 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 13 3 Configuring the External Memory Interface Configuring the External Memory Interface consists of five steps 1 Configure the Output Modes of the associated port pins as either push pull or open drain push pull is most common and skip the associated pins in the crossbar 2 Configure Port latches to park the EMIF pins in a dormant state usually by setting them to logic 1 3 Select Multiplexed mode or Non multiplexed mode 4 Select the memory mode on chip only split mode without bank select split mode with bank select or off chip only 5 Setup timing to interface with off chip memory or peripherals Each of these five steps is explained in detail in the following sections The Port selection Multiplexed mode selection and Mode bits are located in the EMIOCF register show
242. it1 TIO Transmit Interrupt Flag Set by hardware when a byte of data has been transmitted by UARTO after the 8th bit in 8 bit UART Mode or at the beginning of the STOP bit in 9 bit UART Mode When the UARTO interrupt is enabled setting this bit causes the CPU to vector to the UARTO interrupt service routine This bit must be cleared manually by software Bito RIO Receive Interrupt Flag Set to 1 by hardware when a byte of data has been received by UARTO set at the STOP bit sampling time When the UARTO interrupt is enabled setting this bit to 1 causes the CPU to vector to the UARTO interrupt service routine This bit must be cleared manually by soft ware 216 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 18 2 SBUFO Serial UARTO Port Data Buffer R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0x99 Bits7 0 SBUFO 7 0 Serial Data Buffer Bits 7 0 MSB LSB This SFR accesses two registers a transmit shift register and a receive latch register When data is written to SBUFO it goes to the transmit shift register and is held for serial transmis sion Writing a byte to SBUFO initiates the transmission A read of SBUFO returns the con tents of the receive latch e Rev 0 5 217 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 18 1 Timer Settings for Standard Baud
243. ite polarity for CKPOL 1 Figure 20 9 SPI Master Timing CKPHA 1 amp Rev 0 5 239 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Tse oku EM CHEM S 7 MOSI mi SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 Figure 20 10 SPI Slave Timing CKPHA 0 NSS A Tse gt oku 7 SCK CEN E T I gt sis 1 M SCK is shown for CKPOL 0 SCK is the opposite polarity for CKPOL 1 Figure 20 11 SPI Slave Timing CKPHA 1 240 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 20 1 SPI Slave Timing Parameters ONLY Parameter Description Min Max Units Master Mode Timing See Figure 20 8 and Figure 20 9 TuckH SCK High Time 1 X ns TMCKL SCK Low Time 1 X Tsvscik ns Tuis MISO Valid to SCK Shift Edge 1 Tsvscik 20 ns TMIH SCK Shift Edge to MISO Change 0 ns Slave Mode Timing See Figure 20 10 and Figure 20 11 TSE NSS Falling to First SCK Edge 2 X TsySCLK ns Tsp Last SCK Edge to NSS Rising 2 X Tsvscik ns NSS Falling to MISO Valid 4x TsyscLk ns Tspz NSS Rising to MISO High Z 4 ns TckH SCK High Time 9 X TSYSCLK ns SCK Low Time 5 X ns Tsis MOSI Valid to SCK Sample Edge 2
244. itting device will read a NACK not acknowl edge which is a high SDA during a high SCL 194 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 The direction bit R W occupies the least significant bit position of the address byte The direction bit is set to logic 1 to indicate a READ operation and cleared to logic 0 to indicate a WRITE operation All transactions are initiated by a master with one or more addressed slave devices as the target The master generates the START condition and then transmits the slave address and direction bit If the trans action is a WRITE operation from the master to the slave the master transmits the data a byte at a time waiting for an ACK from the slave at the end of each byte For READ operations the slave transmits the data waiting for an ACK from the master at the end of each byte At the end of the data transfer the master generates a STOP condition to terminate the transaction and free the bus Figure 17 3 illustrates a typical SMBus transaction a Oo SDA SLA6 D 5 0 R W D7 D6 0 START Slave Address R W ACK Data Byte NACK STOP Figure 17 3 SMBus Transaction 17 3 1 Arbitration A master may start a transfer only if the bus is free The bus is free after a STOP condition or after the SCL and SDA lines remain high for a specified time see Section 17 3 4 SCL High SMBus Free Timeout on page 196 In the event that tw
245. l mode software should delay at least 1 ms between enabling the external oscillator and checking XTLVLD RC and C modes typically require no startup time 14 5 1 System Clock Selection The CLKSL 1 0 bits in register CLKSEL select which oscillator source is used as the system clock CLKSL 1 0 must be set to 01b for the system clock to run from the external oscillator however the exter nal oscillator may still clock certain peripherals timers PCA USB when the internal oscillator is selected as the system clock The system clock may be switched on the fly between the internal oscillator external oscillator and 4x Clock Multiplier so long as the selected oscillator is enabled and has settled 14 5 2 USB Clock Selection The USBCLK 2 0 bits in register CLKSEL select which oscillator source is used as the USB clock The USB clock may be derived from the 4x Clock Multiplier output a divided version of the internal oscillator or a divided version of the external oscillator Note that the USB clock must be 48 MHz when operating USBO as a Full Speed Function the USB clock must be 6 MHz when operating USBO as a Low Speed Function See SFR Definition 14 6 for USB clock selection options Some example USB clock configurations for Full and Low Speed mode are given below Internal Oscillator Clock Signal Input Source Selection Register Bit Settings USB Clock Clock Multiplier USBCLK 000b Clock Multiplier Input Internal Oscillato
246. les with only four instructions taking more than four system clock cycles The CIP 51 has a total of 109 instructions The table below shows the total number of instructions listed by the required execution time Clocks to Execute 1 2 2 3 3 3 4 4 4 5 5 8 Number of Instructions 26 50 5 14 7 3 1 2 1 1 1 3 Additional Features The C8051F340 1 2 3 4 5 6 7 SoC family includes several key enhancements to the CIP 51 core and peripherals to improve performance and ease of use in end applications The extended interrupt handler provides 16 interrupt sources into the CIP 51 as opposed to 7 for the stan dard 8051 allowing numerous analog and digital peripherals to interrupt the controller An interrupt driven system requires less intervention by the MCU giving it more effective throughput The extra interrupt sources are very useful when building multi tasking real time systems Nine reset sources are available power on reset circuitry POR an on chip Vpp monitor forces reset when power supply voltage drops below as given in Table 11 1 on page 107 the USB controller USB bus reset or a VBUS transition a Watchdog Timer a Missing Clock Detector a voltage level detec tion from ComparatorO a forced software reset an external reset and an errant Flash read write pro tection circuit Each reset source except for the POR Reset Input Pin or Flash error may be disabled by the user in s
247. lit Mode double buffering may be enabled for the IN Endpoint and or the OUT endpoint When Split Mode is not enabled double buffering may be enabled for the entire endpoint FIFO See Table 16 3 for a list of maximum packet sizes for each FIFO configuration Table 16 3 FIFO Configurations Endpoint Split Mode Maximum IN Packet Size Dou Maximum OUT Packet Size Number Enabled ble Buffer Disabled Enabled Double Buffer Disabled Enabled 0 N A 64 1 N 128 64 Y 64 32 64 32 2 N 256 128 Y 128 64 128 64 3 N 512 256 Y 256 128 256 128 16 5 1 FIFO Access Each endpoint FIFO is accessed through a corresponding FIFOn register A read of an endpoint FIFOn register unloads one byte from the FIFO a write of an endpoint FIFOn register loads one byte into the end point FIFO When an endpoint FIFO is configured for Split Mode a read of the endpoint FIFOn register unloads one byte from the OUT endpoint FIFO a write of the endpoint FIFOn register loads one byte into the IN endpoint FIFO USB Register Definition 16 6 FIFOn USBO Endpoint FIFO Access R W R W R W R W R W R W R W R W Reset Value FIFODATA 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito USB Address 0x20 0x23 USB Addresses 0 20 0 23 provide access to the 4 pairs of endpoint FIFOs IN OUT Endpoint FIFO USB Address 0 0x20 1 0x21 2 0x22 3 0x23 Writing to the FIFO address loads data into the IN FIF
248. lling Edge 51 Enable Interrupt Figure 21 6 Timer 2 Capture Mode T2SPLIT 0 e Rev 0 5 253 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 When T2SPLIT 1 the Timer 2 registers TMR2H and TMR2L act as two 8 bit counters Each counter counts up independently and overflows from OxFF to 0x00 Each time a capture event is received the con tents of the Timer 2 registers are latched into the Timer 2 Reload registers TMR2RLH and TMR2RLL A Timer 2 interrupt is generated if enabled TMR2CN T 2 L 2 2 2 5 L E P 1 SYSCLK 12 External Clock 8 009p O v H gt 0 SYSCLK TCLK USB Start of Frame SOF Low Frequency Oscillator Falling Edge Capture P p Enable Interrupt I To SMBus Capture SMBus T2CSS Figure 21 7 Timer 2 Capture Mode T2SPLIT 1 254 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 21 8 TMR2CN Timer 2 Control SILICON LABORATORIES R W R W R W R W R W R W R W R W Reset Value TF2H TF2L TF2LEN T2CE T2SPLIT TR2 T2CSS T2XCLK 00000000 Bit7 Bite Bit5 Bit4 Bit3 Bit2 Bito SFR Address bit addressable 0xC8 Bit7 TF2H Timer 2 High Byte Overflow Flag Set by hardware when the T
249. m number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns respectively VDD 5 VDD 3V VDD 5V VDD 3V Master Device Slave Device 2 Slave Device 1 SDA SCL Figure 17 2 Typical SMBus Configuration 17 3 SMBus Operation Two types of data transfers are possible data transfers from a master transmitter to an addressed slave receiver WRITE and data transfers from an addressed slave transmitter to a master receiver READ The master device initiates both types of data transfers and provides the serial clock pulses on SCL The SMBus interface may operate as a master or a slave and multiple master devices on the same bus are supported If two or more masters attempt to initiate a data transfer simultaneously an arbitration scheme is employed with a single master always winning the arbitration Note that it is not necessary to specify one device as the Master in a system any device who transmits a START and a slave address becomes the master for the duration of that transfer A typical SMBus transaction consists of a START condition followed by an address byte Bits7 1 7 bit slave address Bit0 R W direction bit one or more bytes of data and a STOP condition Each byte that is received by a master or slave must be acknowledged ACK with a low SDA during a high SCL see Figure 17 3 If the receiving device does not ACK the transm
250. mer 3 High Byte In 16 bit mode the TMR3H register contains the high byte of the 16 bit Timer In 8 bit mode TMR3H contains the 8 bit high byte timer value 262 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 22 Programmable Counter Array PCAO The Programmable Counter Array PCAO provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter timers The PCA consists of a dedicated 16 bit counter timer and five 16 bit capture compare modules Each capture compare module has its own associated I O line CEXn which is routed through the Crossbar to Port I O when enabled See Section 15 1 Priority Crossbar Decoder on page 149 for details on configuring the Crossbar The counter timer is driven by a programmable timebase that can select between six sources system clock system clock divided by four system clock divided by twelve the external oscillator clock source divided by 8 Timer 0 overflow or an external clock signal on the ECI input pin Each capture compare module may be configured to operate independently in one of six modes Edge Triggered Capture Software Timer High Speed Output Fre quency Output 8 Bit PWM or 16 Bit PWM each mode is described in Section 22 2 Capture Compare Modules on page 265 The external oscillator clock option is ideal for real time clock RTC functionality allowing the PCA to be clocked by a precision external
251. mode with no system clock active When dis abled the Comparator output if assigned to a Port I O pin via the Crossbar defaults to the logic low state and supply current falls to less than 100 nA See Section 15 1 Priority Crossbar Decoder on page 149 for details on configuring Comparator outputs via the digital Crossbar Comparator inputs can be externally driven from 0 25 V to Vpp 0 25 V without damage or upset The complete Comparator elec trical specifications are given in Table 7 1 Comparator response time may be configured in software via the CPTnMD registers see SFR Definition 7 3 and SFR Definition 7 6 Selecting a longer response time reduces the Comparator supply current See Table 7 1 for complete timing and supply current specifications 60 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 OUT VIN CIRCUIT CONFIGURATION Positive Hysteresis Voltage Programmed with CPOHYP Bits VIN INPUTS Negative Hysteresis Voltage Programmed by CPOHYN Bits VIN OUTPUT Negative Hysteresis L Maximum Disabled Negative Hysteresis deci ve Positive Hysteresis Figure 7 2 Comparator Hysteresis Plot Comparator hysteresis is programmed using Bits3 0 in the Comparator Control Register CPTNCN shown in SFR Definition 7 1 and SFR Definition 7 4 The amount of negative hysteresis voltage is determined by the settings of the CPnH
252. multiplier Internal low frequency oscillator for additional power savings Up to 64 kB of on chip Flash memory Up to 4352 Bytes of on chip RAM 256 4 kB e External Memory Interface EMIF available on 48 pin versions lt 5 2 up to 2 UARTs and Enhanced SPI serial interfaces implemented in hardware Four general purpose 16 bit timers e Programmable Counter Timer Array PCA with five capture compare modules and Watchdog Timer function e On chip Power On Reset Vpp Monitor and Missing Clock Detector Up to 40 Port I O 5 V tolerant With on chip Power On Reset Vpp monitor Voltage Regulator Watchdog Timer and clock oscillator C8051F340 1 2 3 4 5 6 7 devices are truly stand alone System on a Chip solutions The Flash memory can be reprogrammed in circuit providing non volatile data storage and also allowing field upgrades of the 8051 firmware User software has complete control of all peripherals and may individually shut down any or all peripherals for power savings The on chip Silicon Labs 2 Wire C2 Development Interface allows non intrusive uses no on chip resources full speed in circuit debugging using the production MCU installed in the final application This debug logic supports inspection and modification of memory and registers setting breakpoints single stepping run and halt commands All analog and digital peripherals are fully functional while debugging using C2 The two C2 interface pins can
253. n ARBLOST is cleared by hardware each time SI is cleared The SI bit SMBus Interrupt Flag is set at the beginning and end of each transfer after each byte frame or when an arbitration is lost see Table 17 3 for more details Important Note About the SI Bit The SMBus interface is stalled while SI is set thus SCL is held low and the bus is stalled until software clears SI Table 17 3 lists all sources for hardware changes to the SMBOON bits Refer to Table 17 4 for SMBus sta tus decoding using the SMBOCN register e Rev 0 5 201 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Detinition 17 2 SMBOCN SMBus Control Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito R R R W R W R R R W R W Reset Value MASTER TXMODE STA STO ACKRQ ARBLOST SI 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito o E SFR Address OXCO MASTER SMBus Master Slave Indicator This read only bit indicates when the SMBus is operating as a master 0 SMBus operating in Slave Mode 1 SMBus operating in Master Mode TXMODE SMBus Transmit Mode Indicator This read only bit indicates when the SMBus is operating as a transmitter 0 SMBus in Receiver Mode 1 SMBus in Transmitter Mode STA SMBus Start Flag Write 0 No Start generated 1 When operating as a master a START condition is transmitted if the bus is free If the bus is not free the START is transmitted after a STOP is received or a timeout
254. n 15 10 PIMDOUT Port1 Output 156 SFR Definition 15 11 PTSKIP Port SKP iie y ELE RE rrara eee oes ee 157 SFR Definition 15 12 P2 Porte Latch 157 SFR Definition 15 13 P2MDIN Port2 Input Mode 157 SFR Definition 15 14 PAMDOUT Port2 Output 158 SFR Definition 15 15 P2SKIP Port2 Skip 158 SFR Definition 15 16 P3 Pons Latch 159 SFR Definition 15 17 P3MDIN Port3 Input Mode 159 SFR Definition 15 18 PSMDOUT Port3 Output 159 SFR Definition 15 19 PSSKIP Port3 Skip 160 SFR Definition 15 20 P4 Latch 160 SFR Definition 15 21 PAMDIN Port4 Input Mode 161 SFR Definition 15 22 PAMDOUT Port4 Output 161 SFR Definition 16 1 USBOXCN USBO Transceiver Control 165 SFR Definition 16 2 USBOADR USBO Indirect Address 167 SFR Definition 16 3 USBODAT USBO Data 168 USB Register Definition 16 4 INDEX USBO Endpoint Index 169 USB Register Definition 16 5 CLKREC Clock Recovery Control 170 USB Register Definition 16 6 FIFOn USBO Endpoin
255. n be programmed to indicate when mea sured data is inside or outside of the user programmed limits depending on the contents of the ADCO Less Than and ADCO Greater Than registers The Window Detector registers must be written with the same format left right justified signed unsigned as that of the current ADC configuration left right justified single ended differential SFR Definition 5 7 ADCOGTH ADCO Greater Than Data High Byte R W R W R W R W R W R W R W Reset Value 11111111 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0xC4 Bits7 0 High byte of ADCO Greater Than Data Word SFR Definition 5 8 ADCOGTL ADCO Greater Than Data Low Byte R W R W R W R W R W Reset Value 11111111 Bit6 Bit5 Bit4 Bit BitO SFR Address OxC3 Bits7 0 Low byte of ADCO Greater Than Data Word 52 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 5 9 ADCOLTH ADCO Less Than Data High Byte R W R W R W R W R W R W R W Reset Value 00000000 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0xC6 Bits7 0 High byte of ADCO Less Than Data Word SFR Definition 5 10 ADCOLTL ADCO Less Than Data Low Byte R W R W R W R W R W R W R W Reset Value 00000000 Bite Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0xC5 Bits7 0 Low byte of ADCO Less Than Data Word
256. n in SFR Definition 13 2 13 4 Port Configuration The External Memory Interface appears on Ports 4 3 2 and 1 when it is used for off chip memory access When the is used the Crossbar should be configured to skip over the control lines P1 7 WR P1 6 RD and if multiplexed mode is selected P1 3 ALE using the P1SKIP register For more information about configuring the Crossbar see Section Figure 15 1 Port O Functional Block Diagram Port 0 through Port 3 on page 147 The External Memory Interface claims the associated Port pins for memory operations ONLY during the execution of an off chip MOVX instruction Once the MOVX instruction has completed control of the Port pins reverts to the Port latches or to the Crossbar settings for those pins See Section 15 Port Input Output on page 147 for more information about the Crossbar and Port operation and configuration The Port latches should be explicitly configured to park the External Memory Interface pins in a dor mant state most commonly by setting them to a logic 1 During the execution of the MOVX instruction the External Memory Interface will explicitly disable the driv ers on all Port pins that are acting as Inputs Data 7 0 during a READ operation for example The Output mode of the Port pins whether the pin is configured as Open Drain or Push Pull is unaffected by the External Memory Interface operation and remains controlled by the PnMDOUT registers
257. n reet tornei 21 1 1 2 Improved Throlghipilssu sestra aepo rt ence reas 21 1 13 Additiorial FO AUIS sacs VP nem aves i pan 21 1 2 MECH Memory s uo ce S unu Rer 23 1 3 Universal Serial Bus 20220 4 000 24 1 4 Voltage Regulatori ier DH suasit tutus 25 1 5 On Chip Debug retient fos 25 1 6 Programmable Digital and 26 rm 27 1 8 Programmable Counter Array ret eua etre estie O ax Ri EUR 27 1 9 10 Bit Analog to Digital 28 Eomae qa uie bant us dp tct 29 2 Absolute Maximum Ratings enne nn 30 3 Global DC Electrical Characteristics 1 nn 31 4 Pinout and Package nn nn 33 5 10 BUADG AD GO PAPE 41 5 1 Analog see I 42 5 2 Temperature Sensor ous ede ded ee tnb artius rn 43 5 3 Modes of Operation siinaznzin nsn lsn viskozkh pb an ini pink pn ni neuen PER n deter tra us 45 Dost Starting ik 45 5 3 2 Tracking MOGOGS cer Puto e Pas eH 46 5 9 3 Settling Time Requlremietits xr redeem EP RE ies 47 5 4 Programmable Window
258. n the receive buffer that has not been read this bit will return to logic 0 NOTE RXBMT 1 when in Master Mode FNote In slave mode data on MOSI is sampled in the center of each data bit In master mode data on MISO is sampled one SYSCLK before the end of each data bit to provide maximum settling time for the slave device See Table 20 1 for timing parameters 236 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 20 2 SPIOCN SPIO Control R W R W R W R W R W R W R R W Reset Value SPIF WCOL RXOVRN NSSMD1 NSSMDO SPIEN 00000110 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Ad ke SFR Address OxF8 Bit 7 SPIF SPIO Interrupt Flag This bit is set to logic 1 by hardware at the end of a data transfer If interrupts are enabled setting this bit causes the CPU to vector to the SPIO interrupt service routine This bit is not automatically cleared by hardware It must be cleared by software Bit 6 WCOL Write Collision Flag This bit is set to logic 1 by hardware and generates a SPIO interrupt to indicate a write to the SPIO data register was attempted when the transmit buffer was full It must be cleared by software Bit 5 MODF Mode Fault Flag This bit is set to logic 1 by hardware and generates a SPIO interrupt when a master mode collision is detected NSS is low MSTEN 1 and NSSMD 1 0 01 This bit is not auto matically
259. nect Diagram s Rev 0 5 223 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 19 1 SCON1 UART1 Control R W R W R R W R W R W R W R W Reset Value OVR1 PERR1 THRE1 REN1 TBX1 RBX1 TH RI 00100000 Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito Addressable SFR Address 2 Bit7 OVR1 Receive FIFO Overrun Flag This bit is used to indicate a receive FIFO overrun condition 0 Receive FIFO Overrun has not occurred 1 Receive FIFO Overrun has occurred an incoming character was discarded due to a full FIFO This bit must be cleared to 0 by software Bit6 PERR1 Parity Error Flag When parity is enabled this bit is used to indicate that a parity error has occurred It is set to 1 when the parity of the oldest byte in the FIFO does not match the selected Parity Type 0 Parity Error has not occurred 1 Parity Error has occurred This bit must be cleared to by software Bit5 THRE1 Transmit Holding Register Empty Flag 0 Transmit Holding Register not Empty do not write to SBUF1 1 Transmit Holding Register Empty it is safe to write to SBUF1 Bit4 REN1 Receive Enable This bit enables disables the UART receiver When disabled bytes can still be read from the receive FIFO 0 UART1 reception disabled 1 UART1 reception enabled Bit3 TBX1 Extra Transmission Bit The logic level of this bit will be assigned to the extra transmission bit when XBE1 is set to 1 This bi
260. ng 214 Figure 18 6 UART Multi Processor Mode Interconnect Diagram 215 Table 18 1 Timer Settings for Standard Baud Rates Using The Internal Oscillator i ed bic c paced 218 19 UART1 C8051F340 1 4 5 Only Figure 19 1 UART1 Block beet ND 219 Table 19 1 Baud Rate Generator Settings for Standard Baud Rates 220 Figure 19 2 UART1 Timing Without Parity or Extra 221 Figure 19 3 UART1 Timing With Parity 221 Figure 19 4 UART1 Timing With Extra 221 Figure 19 5 Typical UART Interconnect 222 Figure 19 6 UART Multi Processor Mode Interconnect Diagram 223 20 Enhanced Serial Peripheral Interface SPIO Figure 20 1 SPI Block Diagram 229 Figure 20 2 Multiple Master Mode Connection Diagram 232 Figure 20 3 3 Wire Single Master and Slave Mode Connection Diagram 232 Figure 20 4 4 Wire Single Master Mode and Slave Mode Connection Diagram 232 Figure 20 5 Master Mode Data Clock 234 Figure 20 6 Slave Mode Data Clock Timing CKPHA 0 235 Figure 20 7 Slave Mode Data Clock Timing
261. nowledge received 1 0 0 address 5 0010 o 1 Fostarbitration while attempting a Abort failed transfer 0 X 9 repeated START Reschedule failed transfer 1 0 X v 111lx Lost arbitration while attempting a No action required transfer 01010 8 STOP complete aborted ololx A STOP was detected while an action required transfer 0lolx 0001 addressed slave receiver complete Lost arbitration due to a detected Abort transfer 0 X 0111X STOP Reschedule failed transfer 1 0 X Acknowledge received byte 01011 1 o x JA slave byte was received Read SMBODAT requested Do not acknowledge 0 01 0 0000 received byte 4 4 x Lost arbitration while transmitting Abort failed transfer data byte as master Reschedule failed transfer 1 0 0 210 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 18 UARTO UARTO is an asynchronous full duplex serial port offering modes 1 and 3 of the standard 8051 UART Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates details in Section 18 1 Enhanced Baud Rate Generation on page 212 Received data buffering allows UARTO to start reception of a second incoming data byte before software has finished reading the previous data byte UARTO has two associated SFRs Serial Control Register 0 SCONO and Serial Data Buffer 0 SBUFO The single SBUFO location provides access to both tran
262. nsitive 0 1 Active high level sensitive 0 1 Active high level sensitive INTO and INT1 are assigned to Port pins as defined in the ITO1CF register see SFR Definition 9 13 Note that INTO and INTO Port pin assignments are independent of any Crossbar assignments INTO and INT1 will monitor their assigned Port pins without disturbing the peripheral that was assigned the Port pin via the Crossbar To assign a Port pin only to INTO and or INT1 configure the Crossbar to skip the selected pin s This is accomplished by setting the associated bit in register XBRO see Section 15 1 Priority Crossbar Decoder on page 149 for complete details on configuring the Crossbar IEO TCON 1 and IE1 TCON 3 serve as the interrupt pending flags for the INTO and INT1 external interrupts respectively If an INTO or INT1 external interrupt is configured as edge sensitive the corre sponding interrupt pending flag is automatically cleared by the hardware when the CPU vectors to the ISR When configured as level sensitive the interrupt pending flag remains logic 1 while the input is active as defined by the corresponding polarity bit INOPL or IN1PL the flag remains logic 0 while the input is inac tive The external interrupt source must hold the input active until the interrupt request is recognized It must then deactivate the interrupt request before execution of the ISR completes or another interrupt request will be gen
263. nternal oscillator drives the system clock while Timer 2 and or the PCA is clocked by an external preci sion oscillator Note that the external oscillator source divided by 8 is synchronized with the system clock 21 2 1 16 bit Timer with Auto Reload When T2SPLIT and T2CE Timer 2 operates as a 16 bit timer with auto reload Timer 2 can be clocked by SYSCLK SYSCLK divided by 12 or the external oscillator clock source divided by 8 As the 16 bit timer register increments and overflows from OxFFFF to 0x0000 the 16 bit value in the Timer 2 reload registers TMR2RLH and TMR2RLL is loaded into the Timer 2 register as shown in Figure 21 4 and the Timer 2 High Byte Overflow Flag TMR2CN 7 is set If Timer 2 interrupts are enabled an interrupt will be generated on each Timer 2 overflow Additionally if Timer 2 interrupts are enabled and the TF2LEN bit is set TMR2CN 5 an interrupt will be generated each time the lower 8 bits TMR2L overflow from OxFF to 0x00 CKCON T T T T T T S S 3 3 212 1 01 T2XCLK i HILIHIL 110 To ADC SYSCLK 12 SMBus SMBus Overflow TR2 TCLK External Clock 8 TMR2L TMR2H gt m Interrupt LTE2LEN A 2 SYSCLK Shas z m2 gt T2CSS 2XCLK TMRZRLL TMR2RLH Reload Figure 21 4 Timer 2 16 Bit Mode Block Diagram s Rev 0 5 251 SILICON LABORATORI
264. o USB network 1 VBUS signal currently present device attached to USB network Bit5 VBPOL VBUS Interrupt Polarity Select This bit selects the VBUS interrupt polarity 0 VBUS interrupt active when VBUS is low 1 VBUS interrupt active when VBUS is high Bit4 REGMOD Voltage Regulator Mode Select This bit selects the Voltage Regulator mode When REGMOD is set to 1 the voltage regu lator operates in low power suspend mode 0 USBO Voltage Regulator in normal mode 1 USBO Voltage Regulator in low power mode Bits3 0 Reserved Read 0000b Must Write 00000 72 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 9 CIP 51 Microcontroller The MCU system controller core is the CIP 51 microcontroller The CIP 51 is fully compatible with the MC S 517M instruction set standard 803x 805x assemblers and compilers can be used to develop soft ware The MCU family has a superset of all the peripherals included with a standard 8051 Included are four 16 bit counter timers see description in Section 21 an enhanced full duplex UART see description in Section 18 an Enhanced SPI see description in Section 20 256 bytes of internal RAM 128 byte Special Function Register SFR address space Section 9 2 6 and 25 Port I O see description in Sec tion 15 The CIP 51 also includes on chip debug hardware see description in Section 23 and interfaces directly with the analog and digital subsystems providing a com
265. o or more devices attempt to begin a transfer at the same time an arbi tration scheme is employed to force one master to give up the bus The master devices continue transmit ting until one attempts a HIGH while the other transmits a LOW Since the bus is open drain the bus will be pulled LOW The master attempting the HIGH will detect a LOW SDA and lose the arbitration The win ning master continues its transmission without interruption the losing master becomes a slave and receives the rest of the transfer if addressed This arbitration scheme is non destructive one device always wins and no data is lost s Rev 0 5 195 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 17 3 2 Clock Low Extension SMBus provides a clock synchronization mechanism similar to I2C which allows devices with different speed capabilities to coexist on the bus A clock low extension is used during a transfer in order to allow slower slave devices to communicate with faster masters The slave may temporarily hold the SCL line LOW to extend the clock low period effectively decreasing the serial clock frequency 17 3 3 SCL Low Timeout If the SCL line is held low by a slave device on the bus no further communication is possible Furthermore the master cannot force the SCL line high to correct the error condition To solve this problem the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than
266. o reload 0 Timer 2 operates in 16 bit auto reload mode 1 Timer 2 operates as two 8 bit auto reload timers Bit2 TR2 Timer 2 Run Control This bit enables disables Timer 2 In 8 bit mode this bit enables disables TMR2H only TMR2L is always enabled in this mode 0 Timer 2 disabled 1 Timer 2 enabled Bit1 T2CSS Timer 2 Capture Source Select This bit selects the source of a capture event when bit T2CE is set to 1 0 Capture source is USB SOF event 1 Capture source is falling edge of Low Frequency Oscillator Bito T2XCLK Timer 2 External Clock Select This bit selects the external clock source for Timer 2 If Timer 2 is in 8 bit mode this bit selects the external oscillator clock source for both timer bytes However the Timer 2 Clock Select bits T2MH and T2ML in register CKCON may still be used to select between the external clock and the system clock for either timer 0 Timer 2 external clock selection is the system clock divided by 12 1 Timer 2 external clock selection is the external clock divided by 8 Note that the external oscillator source divided by 8 is synchronized with the system clock Rev 0 5 255 C8051F340 1 2 3 4 5 6 7 SFR Definition 21 9 TMR2RLL Timer 2 Reload Register Low Byte RW R W R W RW R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address OxCA Bits 7 0 TMR2RLL Timer 2 Reload Register Low Byte TMR2RLL holds the
267. odd addresses Writes must be performed sequentially i e addresses ending in Ob and 1b must be written in order The Flash write will be performed following the MOVX write that targets the address ending in 1b If a byte in the block does not need to be updated in Flash it should be written to OXFF The recommended procedure for writing Flash in blocks is Step 1 Disable interrupts Step 2 Set the FLBWE bit register PFEOCN to select block write mode Step 3 Set the PSWE bit register PSCTL Step 4 Clear the PSEE bit register PSCTL Step 5 Write the first key code to FLKEY 0 5 Step 6 Write the second key code to FLKEY OxF1 Step 7 Using the MOVX instruction write the first data byte to the even block location ending in Ob Step 8 Write the first key code to FLKEY OxA5 Step 9 Write the second key code to FLKEY OxF1 Step 10 Using the MOVX instruction write the second data byte to the odd block location ending in 1b Step 11 Clear the PSWE bit Step 12 Re enable interrupts Steps 5 10 must be repeated for each block to be written 110 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 12 1 Flash Electrical Characteristics Parameter Conditions Min Typ Max Units C8051F340 2 4 6 65536 Bytes Flash Size C8051F341 3 5 7 32768 Bytes Endurance 20k 100k Erase Write Erase Cycle Time 25 MHz System Clock 10 15 20 ms Write Cycle Time 25 MHz Sy
268. of SCK for each byte transfer Figure 20 4 shows a connection diagram between two slave devices in 4 wire slave mode and a master device 3 wire slave mode is active when NSSMD1 SPIOCN 3 0 and NSSMDO SPIOCN 2 0 NSS is not used in this mode and is not mapped to an external port pin through the crossbar Since there is no way of uniquely addressing the device in 3 wire slave mode SPIO must be the only slave device present on the bus It is important to note that in 3 wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received The bit counter can only be reset by disabling and re enabling SPIO with the SPIEN bit Figure 20 3 shows a connection diagram between a slave device in 3 wire slave mode and a master device 20 4 SPIO Interrupt Sources When SPIO interrupts are enabled the following four flags will generate an interrupt when they are set to logic 1 Note that all of the following bits must be cleared by software 1 The SPI Interrupt Flag SPIF SPIOCN 7 is set to logic 1 at the end of each byte transfer This flag can occur in all SPIO modes 2 The Write Collision Flag WCOL SPIOCN 6 is set to logic 1 if a write to SPIODAT is attempted when the transmit buffer has not been emptied to the SPI shift register When this occurs the write to SPIODAT will be ignored and the transmit buffer will not be written This flag can occur in all SPIO modes 3 The Mode Fault
269. oftware The WDT may be permanently enabled in software after a power on reset during MCU initialization The high speed internal oscillator is factory calibrated to 12 MHz 1 5 A clock recovery mechanism allows the internal oscillator to be used with the 4x Clock Multiplier as the USB clock source in Full Speed mode the internal oscillator can also be used as the USB clock source in Low Speed mode External oscil lators may also be used with the 4x Clock Multiplier An internal low frequency oscillator is also included to aid applications where power savings are critical Also included is an external oscillator drive circuit which allows an external crystal ceramic resonator capacitor RC or CMOS clock source to generate the system clock The system clock may be configured to use ether of the internal oscillators an external oscillator or the Clock Multiplier output divided by 2 If desired the system clock source may be switched on the fly between oscillator sources The low frequency internal oscillator or an external oscillator can be useful in low power applications allowing the MCU to run from a slow power saving external clock source while periodically switching to a higher speed clock source when fast throughput is necessary s Rev 0 5 21 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 VDD Supply Monitor Enable 4 Power jul Reset 9 Dx RST
270. oftware has written 1 to the DATAEND bit Hardware clears this bit when software writes 1 to SSUEND Bit3 DATAEND Data End Software should write 1 to this bit 1 When writing 1 to INPRDY for the last outgoing data packet 2 When writing 1 to INPRDY for a zero length data packet 3 When writing 1 to SOPRDY after servicing the last incoming data packet This bit is automatically cleared by hardware Bit2 STSTL Sent Stall Hardware sets this bit to 1 after transmitting a STALL handshake signal This flag must be cleared by software Bit1 INPRDY IN Packet Ready Software should write 1 to this bit after loading a data packet into the EndpointO FIFO for transmit Hardware clears this bit and generates an interrupt under either of the following conditions 1 The packet is transmitted 2 The packet is overwritten by an incoming SETUP packet 3 The packet is overwritten by an incoming OUT packet Bito OPRDY OUT Packet Ready Hardware sets this read only bit and generates an interrupt when a data packet has been received This bit is cleared only when software writes 1 to the SOPRDY bit s Rev 0 5 183 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 USB Register Definition 16 18 EOCNT USBO Endpoint 0 Data Count R R R R R R R R Reset Value EOCNT 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito USB Address 0x16 Bit7 Unused Read 0 Write don
271. ompare Registers When writing a 16 bit value to the PCAO Capture Compare registers the low byte should always be written first Writing to PCAOCPLn clears the ECOMn bit to 0 writing to PCAOCPHn sets ECOMn to 1 _ 256 PCAOCPHn DutyCycle Ic A Equation 22 2 8 Bit PWM Duty Cycle Using Equation 22 2 the largest duty cycle is 100 PCAOCPHn 0 and the smallest duty cycle is 0 3996 PCAOCPHn OxFF A 0 duty cycle may be generated by clearing the ECOMn bit to 0 Write to PCAOCPLn 0 PCAOCPHn Reset Write to PCAOCPHn 1 PCAOCPLn Enable 8 bit Comparator UE PCAOL PCA Timebase 9f Overflow Figure 22 8 PCA 8 Bit PWM Mode Diagram 270 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 22 2 6 16 Bit Pulse Width Modulator Mode A PCA module may also be operated in 16 Bit PWM mode In this mode the 16 bit capture compare mod ule defines the number of PCA clocks for the low time of the PWM signal When the PCA counter matches the module contents the output on CEXn is asserted high when the counter overflows CEXn is asserted low To output a varying duty cycle new value writes should be synchronized with PCA CCFn match inter rupts 16 Bit PWM Mode is enabled by setting the ECOMn PWMn and PWM16n bits in the PCAOCPMn register For a varying duty cycle match interru
272. omplement number represented by the Security Lock Byte Note that the page containing the Flash Security Lock Byte is also locked when any other Flash pages are locked See example below Security Lock Byte 11111101b 1 s Complement 00000010b Flash pages locked 3 2 Flash Lock Byte Page First two pages of Flash 0x0000 to 0x03FF Addresses locked Flash Lock Byte Page 0 00 to OxFBFF for 64k devices 0x7E00 to Ox7FFF for 32k devices s Rev 0 5 111 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 C8051F340 2 4 6 Reserved OxFCOO0 Locked when any other FLASH pages OxFAOO are locked C8051F341 3 5 7 FLASH memory organized in 512 byte pages Unlocked FLASH Pages Access limit set Unlocked FLASH Pages according to the FLASH security lock byte 0x0000 0x0000 Figure 12 1 Flash Program Memory Map and Security Byte 112 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 The level of FLASH security depends on the FLASH access method The three FLASH access methods that can be restricted are reads writes and erases from the C2 debug interface user firmware executing on unlocked pages and user firmware executing on locked pages Accessing FLASH from the C2 debug interface Any unlocked page may be read written or erased Locked pages cannot be read written or erased The page containing the Lock Byte may be read written or er
273. on 20 3 controls the master mode serial clock frequency This register is ignored when operating in slave mode When the SPI is configured as a master the maximum data transfer rate bits sec is one half the system clock frequency or 12 5 MHz whichever is slower When the SPI is configured as a slave the maximum data transfer rate bits sec for full duplex operation is 1 10 the system clock frequency provided that the master issues SCK NSS in 4 wire slave mode and the serial input data synchronously with the slave s system clock If the master issues SCK NSS and the serial input data asynchronously the maximum data transfer rate bits sec must be less than 1 10 the system clock frequency In the special case where the master only wants to transmit data to the slave and does not need to receive data from the slave i e half duplex operation the SPI slave can receive data at a maximum data transfer rate bits sec of 1 4 the system clock frequency This is provided that the master issues SCK NSS and the serial input data synchronously with the slave s system clock SCK CKPOL 0 CKPHA 0 EN L LI EN EN L SCK i i i i i i i i CKPOL 0 1 _ LI LI LI LI LI LI LI L SCK CKPOL 1 CKPHA 0 SCK CKPOL 1 CKPHA 1 MIBOIMOSI MARY NSS Must Remain High in Multi Master Mode Figure 20 5 Master Mode Data Clock Timing 234 Rev 0 5 e SILI
274. ontains the lower 8 bits of DPTR 13 1 2 8 Bit MOVX Example The 8 bit form of the MOVX instruction uses the contents of the EMIOCN SFR to determine the upper 8 bits of the effective address to be accessed and the contents of RO or R1 to determine the lower 8 bits of the effective address to be accessed The following series of instructions read the contents of the byte at address 0x1234 into the accumulator A MOV EMIOCN 12h load high byte of address into EMIOCN MOV RO 34h load low byte of address into RO or R1 MOVX a RO load contents of 0x1234 into accumulator A s Rev 0 5 117 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 13 2 Accessing USB FIFO Space The C8051 F340 1 2 3 4 5 6 7 include 1k of RAM which functions as USB FIFO space Figure 13 1 shows an expanded view of the FIFO space and user XRAM FIFO space is normally accessed via USB FIFO registers see Section 16 5 FIFO Management on page 171 for more information on accessing these FIFOs The MOVX instruction should not be used to load or modify USB data in the FIFO space Unused areas of the USB FIFO space may be used as general purpose XRAM if necessary The FIFO block operates on the USB clock domain thus the USB clock must be active when accessing FIFO space Note that the number of SYSCLK cycles required by the MOVX instruction is increased when accessing USB FIFO space To access the FIFO RAM directly using MOVX instructions The USBFAE b
275. or 2 an asynchronous USBO reset generated by writing 1 to the USBRST bit POWER 3 Software should perform all USBO configuration before enabling USBO The configuration sequence should be performed as follows Step 1 Select and enable the USB clock source Step 2 Reset USBO by writing USBRST 1 Step 3 Configure and enable the USB Transceiver Step 4 Perform any USBO function configuration interrupts Suspend detect Step 5 Enable USBO by writing USBINH 0 174 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 USB Register Definition 16 8 POWER USBO Power R W R W R W R W R W R W R R W Reset Value ISOUD USBINH USBRST RESUME SUSMD SUSEN 00010000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit Bito USB Address 0x01 Bit7 ISOUD ISO Update This bit affects all IN Isochronous endpoints 0 When software writes INPRDY 1 USBO will send the packet when the next IN token is received 1 When software writes INPRDY 1 USBO will wait for a SOF token before sending the packet If an IN token is received before a SOF token USBO will send a zero length data packet Bits6 5 Unused Read 00b Write don t care Bit4 USBINH USBO Inhibit This bit is set to 1 following a power on reset POR or an asynchronous USBO reset see Bit3 RESET Software should clear this bit after all USBO and transceiver initialization is complete Softwa
276. or generated since the last SMBus interrupt STA and STO are also used to generate START and STOP conditions when operating as a mas ter Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START when the bus becomes free STA is not cleared by hardware after the START is generated Writing a 1 to STO while in Master Mode will cause the interface to generate a STOP and end the current transfer after the next ACK cycle If STO and STA are both set while in Master Mode a STOP followed by a START will be generated As a receiver writing the ACK bit defines the outgoing ACK value as a transmitter reading the ACK bit indicates the value received on the last ACK cycle ACKRQ is set each time a byte is received indicating that an outgoing ACK value is needed When is set software should write the desired outgoing value to the ACK bit before clearing SI A NACK will be generated if software does not write the ACK bit before clearing SI SDA will reflect the defined ACK value immediately following a write to the ACK bit however SCL will remain low until SI is cleared If a received slave address is not acknowledged further slave events will be ignored until the next START is detected The ARBLOST bit indicates that the interface has lost an arbitration This may occur anytime the interface is transmitting master or slave A lost arbitration while operating as a slave indicates a bus error condi tio
277. ored slave interrupts will be inhibited until the next START is detected If the received slave address is acknowledged zero or more data bytes are received Software must write the ACK bit after each received byte to ACK or NACK the received byte The interface exits Slave Receiver Mode after receiving a STOP Note that the interface will switch to Slave Transmitter Mode if SMBODAT is written while an active Slave Receiver Figure 17 7 shows a typical Slave Receiver sequence Two received data bytes are shown though any number of bytes may be received Notice that the data byte transferred interrupts occur before the ACK cycle in this mode S SLA W A Data Byte A Data Byte A Received by SMBus S START Interface P STOP A ACK W WRITE Transmittediby SLA Slave Address SMBus Interface Figure 17 7 Typical Slave Receiver Sequence s Rev 0 5 207 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 17 5 4 Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL When slave events are enabled INH 0 the interface enters Slave Receiver Mode to receive the slave address when a START followed by a slave address and direction bit READ in this case is received Upon entering Slave Transmitter Mode an interrupt is generated and the ACKRQ bit is set Software responds to the received slave address with an ACK or ignores the received slave address with a NACK If the received slav
278. ort I O configuration s Rev 0 5 45 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 5 3 2 Tracking Modes The ADOTM bit in register ADCOCN controls the ADCO track and hold mode In its default state the ADCO input is continuously tracked except when a conversion is in progress When the ADOTM bit is logic 1 ADCO operates in low power track and hold mode In this mode each conversion is preceded by a track ing period of 3 SAR clocks after the start of conversion signal When the CNVSTR signal is used to ini tiate conversions in low power tracking mode ADCO tracks only when CNVSTR is low conversion begins on the rising edge of CNVSTR see Figure 5 4 Tracking can also be disabled shutdown when the device is in low power standby or sleep modes Low power track and hold mode is also useful when AMUX set tings are frequently changed due to the settling time requirements described in Section 5 3 3 Settling Time Requirements on page 47 A ADCO Timing for External Trigger Source CNVSTR ADOCM 2 0 100 SAR Clocks ADOTM 1 LOW Power track Convert Low Power or Convert Mode ADOTM 0 Track or Convert Convert Track BOBO Y B ADCO Timing for Internal Trigger Source Timer 0 Timer 2 Timer 1 Timer 3 Overflow 4 ADOCM 2 0 000 001 010 011 101 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SAR Clocks
279. ory from software 0 Each byte of a software FLASH write is written individually 1 FLASH bytes are written in groups of two s Rev 0 5 99 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 NOTES 100 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 11 Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition On entry to this reset state the following occur e 51 halts program execution e Special Function Registers SFRs are initialized to their defined reset values e External Port pins are forced to a known state Interrupts and timers are disabled All SFRs are reset to the predefined values noted in the SFR detailed descriptions The contents of internal data memory are unaffected during a reset any previously stored data is preserved However since the stack pointer SFR is reset the stack is effectively lost even though the data on the stack is not altered The Port I O latches are reset to OxFF all logic ones in open drain mode Weak pull ups are enabled dur ing and after the reset For Vpp Monitor and Power On Resets the RST pin is driven low until the device exits the reset state On exit from the reset state the program counter PC is reset and the system clock defaults to the inter nal oscillator Refer to Section 14 Oscillators on page 135 for information on selecting and configuring the system clock source The Watc
280. ositive input the CMXON1 CMXONO bits select the ComparatorO negative input The Comparator inputs are selected in the CPT1MX register SFR Definition 7 5 The CMX1P1 CMX1P0 bits select the Comparator1 positive input the CMX1N1 CMX1NO bits select the Comparator1 negative input Important Note About Comparator Inputs The Port pins selected as Comparator inputs should be con figured as analog inputs in their associated Port configuration register and configured to be skipped by the Crossbar for details on Port configuration see Section 15 3 General Purpose Port I O on page 154 s Rev 0 5 59 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 CPnOUT x 2 CMXnNO aa orz Interrupt CPTnCN PTn CPnHYNO CPn CPn Rising edge Falling edge Interrupt 1 CPnRIE Logic CPnFIE SYNCHRONIZER Im Reset Decision Tree Comprator 0 Only Port I O connection options vary with B CPnRIE gt 2 32 48 E CPnFIE BL ERE CPnMD1 CPnMDO Figure 7 1 Comparator Functional Block Diagram Comparator outputs can be polled in software used as an interrupt source and or routed to a Port pin When routed to a Port pin Comparator outputs are available asynchronous or synchronous to the system clock the asynchronous output is available even in STOP
281. own in Figure 16 3 FIFO space allocated for Endpoints1 3 is configurable as IN OUT or both Split Mode half IN half OUT 0x07FF 0x07C0 0x07BF 0 0740 0x073F Configurable as IN OUT or both Split Mode 0x0640 0x063F 0x0440 0x043F 0x0400 USB Clock Domain System Clock Domain OxOSFF 0x0000 Figure 16 3 USB FIFO Allocation 16 5 1 FIFO Split Mode The FIFO space for Endpoints1 3 can be split such that the upper half of the FIFO space is used by the IN endpoint and the lower half is used by the OUT endpoint For example if the Endpoint3 FIFO is configured for Split Mode the upper 256 bytes 0x0540 to Ox063F are used by Endpoint3 IN and the lower 256 bytes 0x0440 to 0x053F are used by Endpoint3 OUT If an endpoint FIFO is not configured for Split Mode that endpoint IN OUT pair s FIFOs are combined to form a single IN or OUT FIFO In this case only one direction of the endpoint IN OUT pair may be used at a time The endpoint direction IN OUT is determined by the DIRSEL bit in the corresponding endpoint s EINCSRH register see SFR Definition 16 20 s Rev 0 5 171 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 16 5 2 FIFO Double Buffering FIFO slots for Endpoints1 3 can be configured for double buffered mode In this mode the maximum packet size is halved and the FIFO may contain two packets at a time This mode is available for Endpoints1 3 When an endpoint is configured for Sp
282. ows non intrusive uses no on chip resources full speed in circuit debugging using the production MCU installed in the final application This debug logic supports inspection and modification of memory and registers setting breakpoints single stepping run and halt commands All analog and digital peripherals are fully functional while debugging using C2 The two C2 interface pins can be shared with user functions allowing in system debugging with out occupying package pins C2 details can be found in Section 23 C2 Interface on page 279 The CIP 51 is supported by development tools from Silicon Labs and third party vendors Silicon Labs pro vides an integrated development environment IDE including editor debugger and programmer The IDE s debugger and programmer interface to the CIP 51 via the C2 interface to provide fast and efficient in system device programming and debugging An 8051 assembler linker and evaluation C compiler are included in the Development Kit Many third party macro assemblers and C compilers are also available which can be used directly with the IDE 9 1 Instruction Set The instruction set of the CIP 51 System Controller is fully compatible with the standard 5 51 instruc tion set Standard 8051 development tools can be used to develop software for the CIP 51 CIP 51 instructions are the binary and functional equivalent of their MCS 51 counterparts including opcodes addressing modes and effec
283. p R W R W R W R W R W R W R W Reset Value 00000000 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address 0 04 57 0 POSKIP 7 0 PortO Crossbar Skip Enable Bits These bits select Port pins to be skipped by the Crossbar Decoder Port pins used as ana log inputs for ADC or Comparator or used as special functions VREF input external oscil lator circuit CNVSTR input should be skipped by the Crossbar 0 Corresponding PO n pin is not skipped by the Crossbar 1 Corresponding PO n pin is skipped by the Crossbar s Rev 0 5 155 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 15 8 P1 Port1 Latch R W R W R W R W R W R W R W Reset Value P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 11111111 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address bit addressable 0x90 Bits7 0 P1 7 0 Write Output appears on I O pins per Crossbar Registers when XBARE 1 0 Logic Low Output 1 Logic High Output high impedance if corresponding P1MDOUT n bit 0 Read Always reads 0 if selected as analog input in register P1MDIN Directly reads Port pin when configured as digital input 0 P1 n pin is logic low 1 P1 n pin is logic high SFR Definition 15 9 PIMDIN Port1 Input Mode R W R W R W R W Reset Value 11111111 Bit5 Bit4 Bit Bito SFR Address OxF2 Analog Input Configuration Bits for 1
284. plete data acquisition or control system solution in a single integrated circuit The CIP 51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability see Figure 9 1 for a block diagram The CIP 51 includes the following features Fully Compatible with MCS 51 Instruction Set 0 to 48 MHz Clock Frequency 256 Bytes of Internal RAM Extended Interrupt Handler Reset Input Power Management Modes On chip Debug Logic 25 Port I O Program and Data Memory Security DATA BUS 8 amp amp ACCUMULATOR B REGISTER STACK POINTER m S TMP1 TMP2 lt SRAM PSW ADDRESS 0 REGISTER 8 o co 8 a 2 DATA BUS SFR ADDRESS BUFFER DE SFR SFR_CONTROL B DATA POINTER 1 De SFR WRITE DATA SFR READ DATA PC INCREMENTER N MEM_ADDRESS PROGRAM COUNTER PC MEM_CONTROL ADDRESS REG lt 216 INTERFACE MEM WRITE DATA a MEM READ DATA PIPELINE 55 RESET CONTROL LOGIC YSTEM IR ctock SYSTEM INTERRUPT Lo NI INTERFACE STOP c6 EMULATION IRQ D POWER CONTROL d REGISTER SILICON LABORATORIES
285. pt set to high priority level PUSBO USBO Interrupt Priority Control This bit sets the priority of the USBO interrupt 0 USBO interrupt set to low priority level 1 USBO interrupt set to high priority level PSMBO SMBus Interrupt Priority Control This bit sets the priority of the SMBO interrupt 0 SMBO interrupt set to low priority level 1 SMBO interrupt set to high priority level s Rev 0 5 SILICON LABORATORIES Reset Value 00000000 SFR Address OxF6 93 C8051F340 1 2 3 4 5 6 7 SFR Definition 9 11 EIE2 Extended Interrupt Enable 2 R W R W Reset Value ES1 EVBUS 00000000 Bit1 Bito SFR Address OxE7 UNUSED Read 000000b Write don t care ES1 Enable UART1 Interrupt This bit sets the masking of the UART1 interrupt 0 Disable UART1 interrupt 1 Enable UART1 interrupt EVBUS Enable VBUS Level Interrupt This bit sets the masking of the VBUS interrupt 0 Disable all VBUS interrupts 1 Enable interrupt requests generated by VBUS level sense SFR Definition 9 12 EIP2 Extended Interrupt Priority 2 R W R W R W R W R W R W R W R W Reset Value PS1 PVBUS 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit Bito SFR Address OxF7 Bits7 2 UNUSED Read 000000b Write don t care Bit1 PS1 UARTI Interrupt Priority Control This bit sets the priority of the UARTI interrupt 0 UARTI interrupt set to low prio
286. pts should be enabled ECCFn 1 AND MATn 1 to help synchronize the capture compare register writes The duty cycle for 16 Bit PWM Mode is given by Equation 22 3 Important Note About Capture Compare Registers When writing a 16 bit value to the PCAO Capture Compare registers the low byte should always be written first Writing to PCAOCPLn clears the ECOMn bit to 0 writing to PCAOCPHn sets ECOMn to 1 65536 PCAOCPn DutyCycle 65536 Equation 22 3 16 Bit PWM Duty Cycle Using Equation 22 3 the largest duty cycle is 100 PCAOCPn 0 and the smallest duty cycle is 0 001596 PCAOCPn OxFFFF A 0 duty cycle may be generated by clearing the ECOMn bit to 0 Write to POA0CPUn 0 ens Write to a ZA 1 yPCAOCPMn PIEICI C M T P E CIAJA AJO WC Ms eibi PCAOCPHn PCAOCPLn 1 MP NIn n n F 6 n n n n n tiae NN ee pu RES 7 8 16 bit Comparator match s QL SEX crossbar DX Port vo li fi RaT PCA Timebase 4 POAOH PCAOL Overflow Figure 22 9 PCA 16 Bit PWM Mode s Rev 0 5 271 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 22 3 Watchdog Timer Mode A programmable watchdog timer WDT function is available through the PCA Module 4 The WDT is used to generate a reset if the time between writes to the WDT update register PCAOCPH4 e
287. r P4 M Data gt Port4 Beas Clock Low Freq Drivers 0 P4 4 Recovery Oscillator P Analog Peripherals E P Y VREF dq USB Peripheral UD vrer 2 Uo m s 2 Comparators Full Low Controller Speed Transceiver 1k Byte RAM Figure 1 1 C8051F340 1 4 5 Block Diagram D AINO AIN19 VBUS Rev 0 5 19 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 2 Port O Configurati Debug Programming 9 n Hardware lt gt Poo C2CK RST B Digital Peripherals K 9 PO 2 XTALI Reset UARTO Port 0 PO 3 XTAL2 T P0 4 CIP 51 8051 Drivers 438 pos PO 6 CNYSTI Power On Controller Core _ j POTIVREE Reset Timers 0 1 4 P1 0 O 64 32 KB ISP FLASH 2 3 Priority I3 n2 Supply Program Memory Crossbar gt Port 1 bits Monitor PCAWDT Decoder Drivers pun an 1 6 i 256 Byte RAM M 17 Net SMBus E cu REC Voltage SPI Port 2 Pes X Regulator 4 2 kB XRAM Drivers 6 28 P24 Crossbar Control PS ec GND E SFR 4 53 P27 V B P3 0 C2D System Clock Setup us XTAL1 External L I XTAL2 Oscillator Clock Internal
288. r Temp Sensor 11111 Vpp Vpp 48 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 5 2 AMXON AMUXO Negative Channel Select R R W R W R W R W R W Reset Value AMXON4 AMXON3 AMXON2 AMXON1 AMXONO 00000000 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Address OxBA Bits7 5 UNUSED Read 000b Write don t care 54 0 4 0 AMUXO Negative Input Selection Note that when GND is selected as the Negative Input ADCO operates in Single ended mode For all other Negative Input selections ADCO operates in Differential mode AMXON4 0 ADCO Negative Input ADCO Negative Input 32 pin Package 48 pin Package 00000 P1 0 P2 0 00001 P1 1 P2 1 00010 P1 2 P2 2 00011 1 3 P2 3 00100 P1 4 P2 5 00101 P1 5 P2 6 00110 P1 6 P3 0 00111 P1 7 P3 1 01000 P2 0 P3 4 01001 P2 1 P3 5 01010 P2 2 P3 7 01011 P2 3 P4 0 01100 P2 4 P4 3 01101 P2 5 P4 4 01110 P2 6 P4 5 01111 P2 7 P4 6 10000 P3 0 RESERVED 10001 PO O PO 3 10010 PO 1 PO 4 10011 PO 4 P 1 1 10100 PO 5 P1 2 10101 11101 RESERVED RESERVED 11110 VREF VREF 11111 GND Single Ended Mode GND Single Ended Mode SILICON LABORATORIES Rev 0 5 49 C8051F340 1 2 3 4 5 6 7 SFR Definition 5 3 ADCOCF ADCO Configuration R W R W R W R W R W R W R W R W Reset Value ADOSC4 ADOSC3 A
289. r MULSEL 00b Internal Oscillator Divide by 1 IFCN 11b External Oscillator Clock Signal Input Source Selection Register Bit Settings USB Glock Clock Multiplier USBCLK 000b Clock Multiplier Input External Oscillator MULSEL 01b External Oscillator Crystal Oscillator Mode XOSCMD 110b 12 MHz Crystal XFCN 111b Note Clock Recovery must be enabled for this configuration Internal Oscillator Clock Signal Input Source Selection Register Bit Settings USB Clock Internal Oscillator 2 USBCLK 001b Internal Oscillator Divide by 1 IFCN 11b External Oscillator Clock Signal USB Clock Input Source Selection External Oscillator 4 Register Bit Settings USBCLK 101b External Oscillator Crystal Oscillator Mode 24 MHz Crystal XOSCMD 110b 111b SILICON LABORATORIES Rev 0 5 143 C8051F340 1 2 3 4 5 6 7 SFR Definition 14 6 CLKSEL Clock Select R W R W R W R W R W R W R W R W Reset Value USBCLK CLKSL 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address OxA9 Bit 7 Unused Read 0b Write don t care Bits6 4 USBCLK2 0 USB Clock Select These bits select the clock supplied to USBO When operating USBO in full speed mode the selected clock should be 48 MHz When operating USBO in low speed mode the selected clock should be 6 MHz
290. r High Byte 277 SFR Definition 22 6 PCAOCPLn PCA Capture Module Low Byte 277 SFR Definition 22 7 PCAOCPHn PCA Capture Module High Byte 278 C2 Register Definition 23 1 CZADD C2 Address 279 Rev 0 5 15 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 C2 Register Definition 23 2 DEVICEID C2 Device ID ana 279 C2 Register Definition 23 3 REVID C2 Revision ID 280 C2 Register Definition 23 4 FPCTL C2 Flash Programming Control 280 C2 Register Definition 23 5 FPDAT C2 Flash Programming Data 280 16 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 1 System Overview C8051F340 1 2 3 4 5 6 7 devices are fully integrated mixed signal System on a Chip MCUs Highlighted features are listed below Refer to Table 1 1 for specific product feature selection e High speed pipelined 8051 compatible microcontroller core up to 48 MIPS e In system full speed non intrusive debug interface on chip Universal Serial Bus USB Function Controller with eight flexible endpoint pipes integrated trans ceiver and 1 kB FIFO RAM Supply Voltage Regulator e True 10 bit 200 ksps differential single ended ADC with analog multiplexer e On chip Voltage Reference and Temperature Sensor e On chip Voltage Comparators 2 e Precision internal calibrated 12 MHz internal oscillator and 4x clock
291. r Mode SI SMBus Interrupt Flag This bit is set by hardware under the conditions listed in Table 17 3 SI must be cleared by software While SI is set SCL is held low and the SMBus is stalled 202 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 17 3 Sources for Hardware Changes to SMBOCN Bit Set by Hardware When Cleared by Hardware When MASTER A START is generated STOP is generated Arbitration is lost START is generated A START is detected TXMODE SMBODAT is written before the start of an Arbitration is lost SMBus frame SMBODAT is not written before the start of an SMBus frame STA A START followed by an address byte is Must be cleared by software received A STOP is detected while addressed as a A pending STOP is generated STO slave Arbitration is lost due to a detected STOP A byte has been received and an ACK After each ACK cycle ACKRQ response value is needed repeated START is detected as a MASTER Each time SI is cleared when STA is low unwanted repeated START SCL is sensed low while attempting to gener ate STOP or repeated START condition SDA is sensed low while transmitting a 1 excluding ACK bits ACK incoming ACK value is low ACKNOWL The incoming ACK value is high NOT EDGE ACKNOWLEDGE A START has been generated Must be cleared by software Lost arbi
292. re cannot set this bit to 1 0 USBO enabled 1 USBO inhibited USB traffic is ignored Bit3 USBRST Reset Detect Writing 1 to this bit forces an asynchronous USBO reset Reading this bit provides bus reset status information Read 0 Reset signaling is not present on the bus 1 Reset signaling detected on the bus Bit2 RESUME Force Resume Software can force resume signaling on the bus to wake USBO from suspend mode Writing a 1 to this bit while in Suspend mode SUSMD 1 forces USBO to generate Resume sig naling on the bus a remote Wakeup event Software should write RESUME 0 after 10 ms to15 ms to end the Resume signaling An interrupt is generated and hardware clears SUSMD when software writes RESUME 0 Bit1 SUSMD Suspend Mode Set to 1 by hardware when USBO enters suspend mode Cleared by hardware when soft ware writes RESUME 0 following a remote wakeup or reads the CMINT register after detection of Resume signaling on the bus 0 USBO not in suspend mode 1 USBO in suspend mode Bito SUSEN Suspend Detection Enable 0 Suspend detection disabled USBO will ignore suspend signaling on the bus 1 Suspend detection enabled USBO will enter suspend mode if it detects suspend signaling on the bus e Rev 0 5 175 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 USB Register Definition 16 9 FRAMEL USBO Frame Number Low R R R R R R R R Reset Value Frame Number Low 0000000
293. reload mode split 8 bit auto reload mode USB Start of Frame SOF capture mode or Low Frequency Oscillator LFO Rising Edge capture mode The Timer 3 operation mode is defined by the T3SPLIT TMR3CN 3 T3CE 4 bits and T3CSS 1 bits Timer 3 may be clocked by the system clock the system clock divided by 12 or the external oscillator source divided by 8 The external clock mode is ideal for real time clock RTC functionality where the internal oscillator drives the system clock while Timer 3 and or the PCA is clocked by an external preci sion oscillator Note that the external oscillator source divided by 8 is synchronized with the system clock 21 3 1 16 bit Timer with Auto Reload When T3SPLIT TMR3CN 3 is 0 and T3CE Timer 3 operates as a 16 bit timer with auto reload Timer 3 can be clocked by SYSCLK SYSCLK divided by 12 or the external oscillator clock source divided by 8 As the 16 bit timer register increments and overflows from OxFFFF to 0x0000 the 16 bit value in the Timer reload registers TMRSRLH and TMSRLL is loaded into the Timer register as shown in Figure 21 4 and the Timer 3 High Byte Overflow Flag TMR3CN 7 is set If Timer 3 interrupts are enabled an interrupt will be generated on each Timer 3 overflow Additionally if Timer 3 interrupts are enabled and the TF3LEN bit is set TMR3CN 5 an interrupt will be generated each time the lower 8 bits TMR3L over flow from OxFF
294. rity level 1 UARTI interrupts set to high priority level Bito PVBUS VBUS Level Interrupt Priority Control This bit sets the priority of the VBUS interrupt 0 VBUS interrupt set to low priority level 1 VBUS interrupt set to high priority level 94 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 9 13 ITO1CF INTO INT1 Configuration R W R W R W R W R W R W R W R W Reset Value IN1PL INTSL2 IN1SL1 IN1SLO INOPL INOSL2 INOSL1 INOSLO 00000001 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0 4 Note Refer to SFR Definition 21 1 for INTO 1 edge or level sensitive interrupt selection Bit7 IN1PL INT1 Polarity 0 INT1 input is active low 1 INT1 input is active high IN1SL2 0 INT1 Port Pin Selection Bits These bits select which Port pin is assigned to INT1 Note that this pin assignment is inde pendent of the Crossbar INT1 will monitor the assigned Port pin without disturbing the peripheral that has been assigned the Port pin via the Crossbar The Crossbar will not assign the Port pin to a peripheral if itis configured to skip the selected pin accomplished by setting to 1 the corresponding bit in register POSKIP Bits6 4 IN1SL2 0 000 001 INT1 Port Pin 0 0 PO 1 Bit3 Bits2 0 010 PO 2 011 100 PO 3 PO 4 101 PO 5 110 0 6 111 0 7 IN
295. rs are set The PnSKIP registers allow software to skip Port pins that are to be used for analog input dedicated functions or GPIO Important Note on Crossbar Configuration If a Port pin is claimed by a peripheral without use of the Crossbar its corresponding PnSKIP bit should be set This applies to the VREF signal external oscillator pins XTAL1 XTAL2 the ADC s external conversion start signal CNVSTR EMIF control signals and any selected ADC or Comparator inputs The PnSKIP registers may also be used to skip pins to be used as GPIO The Crossbar skips selected pins as if they were already assigned and moves to the next unas signed pin Figure 15 3 shows the Crossbar Decoder priority with no Port pins skipped Figure 15 4 shows Crossbar example with pins PO 2 and PO 3 skipped POSKIP 0x0C NSS is only pinned out i SYSCLK Only i n Package 000000 0 00 0 ojo 0 0 0 0 0 POSKIP 0 7 P1SKIP 0 7 P2SKIP 0 7 P3SKIP 0 7 Port pin potentially available to peripheral SSESignals Special Function Signals are not assigned by the Crossbar When these signals are enabled the Crossbar must be manually configured to skip their corresponding port pins Figure 15 3 Crossbar Priority Decoder with No Pins Skipped 62 Rev 0 5 149 SILICON LABORATORIES
296. rs between Single ended and Differential modes The registers ADCOH and ADCOL contain the high and low bytes of the output conversion code from the ADC at the completion of each conversion Data can be right justified or left justified depending on the setting of the ADOLJST bit ADCOCN 0 When in Single ended Mode conversion codes are represented as 10 bit unsigned integers Inputs are measured from 0 to VREF x 1023 1024 Example codes are shown below for both right justi fied and left justified data Unused bits in the ADCOH and ADCOL registers are set to 0 Input Voltage Right Justified ADCOH ADCOL Left Justified ADCOH ADCOL Single Ended ADOLJST 0 ADOLJST 1 VREF x 1023 1024 Ox03FF OxFFCO VREF x 512 1024 0x0200 0x8000 VREF x 256 1024 0x0100 0x4000 0 0x0000 0x0000 When in Differential Mode conversion codes are represented as 10 bit signed 2 s complement numbers Inputs are measured from VREF to VREF x 511 512 Example codes are shown below for both right jus tified and left justified data For right justified data the unused MSBs of ADCOH are a sign extension of the data word For left justified data the unused LSBs in the ADCOL register are set to 0 Input Voltage Right Justified ADCOH ADCOL Left Justified ADCOH ADCOL Differential ADOLJST 0 ADOLJST 1 VREF x 511 512 0x01FF Ox7FCO VREF x 256 512 0x0100 0x4000 0 0x0000 0x0000 VREF x 256 512 0 000 VREF OxFEO
297. rtet beet 85 Rev 0 5 3 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 9 3 Interrupt Handler ERR c 87 9 3 1 MCU Interrupt Sources and 87 95 2 External Interr piss thea ote ent ems o et 87 9 3 3 Interrupt PHOTOS e eure ere ta aea pma eee 88 9 3 4 Interrupt LatenCy 88 9 3 5 Interrupt Register 89 9 4 Power Management 96 9 4 1 Idle MOG sc oem teste dva ead vt 96 9 4 2 Stop MGO ride qe deii cedet obe et reus Dea vx aa Ede dede et 96 TO Prefete M E Nd N ioci buka denotes vb iron art ess bolus 99 11 Reset Sorc S neta Xx Za 101 11 1 Power On ROSE x pei ot M e n ek Gu qd tun bI Eu 102 11 2 Power Fail Reset VDD 103 RESET EO tie ieu 104 11 4 Missing Clock Detector Reset 104 11 5 Gomparatoro ReSOl uo ete eb a eb n node eee wees 104 11 6 PCA Watchdog Timer ta rene aede e rarae 104 ll reto er test bo ite d tete bb iet 104 11 8 Software ior ru iet Rabe 105 11 9 USB RSO T 105 12 Flash
298. s DX P07 gi CPO 2 Si lt gt 5 Outputs Digital 8 P1 DX P1 0 CP1 2 C 9 b e si rossbar o Outputs cce P s SYSCLK i A vo Ed PCA Cells S P2 7 2 TO T1 z DX P3 0 B Lowest 2 Priority VARTI Cells DX Note P3 1 P3 7 and UART1 only available on 48 pin package Port Latches Figure 1 6 Digital Crossbar Diagram 26 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 1 7 Serial Ports The C8051F340 1 2 3 4 5 6 7 Family includes an SMBus I2C interface full duplex UARTs and an Enhanced SPI interface Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP 51 s interrupts thus requiring very little CPU intervention 1 8 Programmable Counter Array An on chip Programmable Counter Timer Array PCA is included in addition to the four 16 bit general pur pose counter timers The PCA consists of a dedicated 16 bit counter timer time base with five programma ble capture compare modules The PCA clock is derived from one of six sources the system clock divided by 12 the system clock divided by 4 Timer 0 overflows a dedicated External Clock Input ECI the sys tem clock or the external oscillator clock source divided by 8 The external clock source selection is useful for real time clock functionality where the PCA may be clocked by an external source while the internal oscillator drives the system clock
299. s set to 1 anda MOVX write operation is attempted above address Ox3DFF A Flash read is attempted above user code space This occurs when a MOVC operation is attempted above address Ox3DFF A Program read is attempted above user code space This occurs when user code attempts to branch to an address above Ox3DFF AFlash read write or erase attempt is restricted due to a Flash security setting see Section 12 3 Security Options on page 111 A Flash Write or Erase is attempted when the Vpp monitor is not enabled The FERROR bit RSTSRC 6 is set following a Flash error reset The state of the RST pin is unaffected by this reset 104 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 11 8 Software Reset Software may force a reset by writing a 1 to the SWRSF bit RSTSRC 4 The SWRSF bit will read 1 fol lowing a software forced reset The state of the RST pin is unaffected by this reset 11 9 USB Reset Writing 1 to the USBRSF bit in register RSTSRC selects USBO as a reset source With USBO selected as a reset source a system reset will be generated when either of the following occur 1 RESET signaling is detected on the USB network The USB Function Controller USBO must be enabled for RESET signaling to be detected See Section 16 Universal Serial Bus Con troller 05 0 on page 163 for information on the USB Function Controller 2 The voltage on the VBUS pin mat
300. s the ECOMn bit to 0 writing to PCAOCPHn sets ECOMn to 1 Write to PCAOCPLn Reset PCAOCPHn 1 Write to HA PCAOCPLn PCAOCPHn PCAOCPMn PIE CI CMT C AJAJAJO MOJPIP TIG 1 MIP N n n 6 n n n 0x 00 5 moom E PCA Interrupt PCAOCN Timebase 16 bit Comparator p PCAOL PCAOH Figure 22 6 PCA High Speed Output Mode Diagram 268 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 22 2 4 Frequency Output Mode Frequency Output Mode produces a programmable frequency square wave on the module s associated CEXn pin The capture compare module high byte holds the number of PCA clocks to count before the out put is toggled The frequency of the square wave is then defined by Equation 22 1 F Z Fpca CEXn 2 x PCAOCPHn Note A value of 0x00 in the PCAOCPHn register is equal to 256 for this equation Equation 22 1 Square Wave Frequency Output Where Fpca is the frequency of the clock selected by the CPS2 0 bits in the PCA mode register PCAOMD The lower byte of the capture compare module is compared to the PCA counter low byte on a match CEXn is toggled and the offset held in the high byte is added to the matched value in PCAOCPLn Fre quency Output Mode is enabled by setting the ECOMn TOGn and PWMn bits in the PCAOCPMn register Write to
301. sed It may only be read or written Reading the contents of the Lock Byte is always permitted Locking additional pages changing 1s to 0 in the Lock Byte is always permitted Unlocking FLASH pages changing 0 s to 1 s in the Lock Byte is not permitted The Reserved Area cannot be read written or erased Any attempt to access the reserved area or any other locked page will result in a FLASH Error device reset s Rev 0 5 113 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Detinition 12 1 PSCTL Program Store R W Control R W R W R W R W R W R W R W Reset Value Reserved PSEE PSWE 00000000 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address 0x8F Unused Read 00000b Write 2 don t care Reserved Read Ob Must Write Ob PSEE Program Store Erase Enable Setting this bit in combination with PSWE allows an entire page of Flash program memory to be erased If this bit is logic 1 and Flash writes are enabled PSWE is logic 1 a write to Flash memory using the MOVX instruction will erase the entire page that contains the loca tion addressed by the MOVX instruction The value of the data byte written does not matter 0 Flash program memory erasure disabled 1 Flash program memory erasure enabled PSWE Program Store Write Enable Setting this bit allows writing a byte of data to the Flash program memory using the MOVX write instruction The Flash location shoul
302. sed Read 0000b Write don t care IN3 IN Endpoint 3 Interrupt pending Flag This bit is cleared when software reads the IN1INT register 0 IN Endpoint 3 interrupt inactive 1 IN Endpoint 3 interrupt active IN2 IN Endpoint 2 Interrupt pending Flag This bit is cleared when software reads the IN1INT register 0 IN Endpoint 2 interrupt inactive 1 IN Endpoint 2 interrupt active IN1 IN Endpoint 1 Interrupt pending Flag This bit is cleared when software reads the IN1INT register 0 IN Endpoint 1 interrupt inactive 1 IN Endpoint 1 interrupt active EPO Endpoint 0 Interrupt pending Flag This bit is cleared when software reads the IN1INT register 0 Endpoint 0 interrupt inactive 1 Endpoint 0 interrupt active USB Register Definition 16 12 OUT1INT USBO Out Endpoint Interrupt R R R R R R R OUT3 OUT2 OUT1 Bit7 Bits7 4 Bit3 Bit2 Bit1 Bito Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Reset Value 00000000 USB Address 0x04 Unused Read 0000b Write 2 don t care OUT3 OUT Endpoint Interrupt pending Flag This bit is cleared when software reads the OUT1INT register 0 OUT Endpoint 3 interrupt inactive 1 OUT Endpoint 3 interrupt active OUT2 OUT Endpoint 2 Interrupt pending Flag This bit is cleared when software reads the OUT1INT register 0 OUT Endpoint 2 interrupt inactive 1 OUT Endpoint 2 interrupt
303. smit and receive registers Writes to SBUFO always access the Transmit register Reads of SBUFO always access the buffered Receive register it is not possible to read data from the Transmit register With UARTO interrupts enabled an interrupt is generated each time a transmit is completed TIO is set in SCONO or a data byte has been received RIO is set in SCONO The UARTO interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine They must be cleared manually by software allowing software to determine the cause of the UARTO interrupt transmit complete or receive complete UARTO Baud Rate Generator 2 SFRBus Write to SZ SBUFO TB80 M SBUFO TX Shift OX o eee 1 Zero Detector Stop Bit Shift Start Tx Clock Tx Control Tx IRQ SOMODE TIO RIO o eo 1 Send TIO RIO p Rx Clock Start Rx IRQ Rx Control Shift Ox1FF RB80 Load SBUFO Input Shift Register 9 bits Read SBUFO SFR Bus C 9 Load SBUFO SBUFO RX Latch Serial Port Interrupt Figure 18 1 UARTO Block Diagram Port I O Rev 0 5 211 SILICON LABORATORIES C8051F340 1 2 3 4 5 6
304. solute minimum time that the current SDA value remains stable after SCL transitions from high to low EXTHOLD should be set so that the minimum setup and hold times meet the SMBus Specification requirements of 250 ns and 300 ns respectively Table 17 2 shows the min imum setup and hold times for the two EXTHOLD settings Setup and hold time extensions are typically necessary when SYSCLK is above 10 MHz Table 17 2 Minimum SDA Setup and Hold Times EXTHOLD Minimum SDA Setup Time Minimum SDA Hold Time Tiow 4 system clocks 0 OR 3 system clocks 1 system clock s w delay 1 11 system clocks 12 system clocks Note Setup Time for ACK bit transmissions and the MSB of all data transfers The s w delay occurs between the time SMBODAT or ACK is written and when SI is cleared Note that if SI is cleared in the same write that defines the outgoing ACK value s w delay is zero With the SMBTOE bit set Timer 3 should be configured to overflow after 25 ms in order to detect SCL low timeouts see Section 17 3 3 SCL Low Timeout on page 196 The SMBus interface will force Timer 3 to reload while SCL is high and allow Timer 3 to count when SCL is low The Timer 3 interrupt service rou tine should be used to reset SMBus communication by disabling and re enabling the SMBus SMBus Free Timeout detection can be enabled by setting the SMBFTE bit When this bit is set the bus will be considered free if SDA and SCL remain high for more
305. ssbar Reload Exc Figure 21 2 TO Mode 2 Block Diagram s Rev 0 5 245 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 21 1 4 Mode 3 Two 8 bit Counter Timers Timer 0 Only In Mode 3 Timer 0 is configured as two separate 8 bit counter timers held in TLO and THO The counter timer in TLO is controlled using the Timer 0 control status bits in TCON and TMOD TRO C TO GATEO and TFO TLO can use either the system clock or an external input signal as its timebase The THO register is restricted to a timer function sourced by the system clock or prescaled clock THO is enabled using the Timer 1 run control bit TR1 THO sets the Timer 1 overflow flag TF1 on overflow and thus controls the Timer 1 interrupt Timer 1 is inactive in Mode 3 When Timer 0 is operating in Mode 3 Timer 1 can be operated in Modes 0 1 or 2 but cannot be clocked by external signals nor set the TF1 flag and generate an interrupt However the Timer 1 overflow can be used to generate baud rates for the SMBus and or UART and or initiate ADC conversions While Timer 0 is operating in Mode 3 Timer 1 run control is handled through its mode set tings To run Timer 1 while Timer 0 is in Mode 3 set the Timer 1 Mode as 0 1 or 2 To disable Timer 1 configure it for Mode 3 CKCON TMOD 5 5 G C T T G C T T 3 3 2 2 1 0 1 1 T T MM T TIMIM 1 1 0 0 1 0 1 0
306. stem Clock 40 55 70 us Note 1024 bytes at location OXFCOO to OxFFFF are reserved 12 2 Non volatile Data Storage The Flash memory can be used for non volatile data storage as well as program code This allows data such as calibration coefficients to be calculated and stored at run time Data is written using the MOVX write instruction and read using the MOVC instruction Note MOVX read instructions always target XRAM 12 3 Security Options The CIP 51 provides security options to protect the Flash memory from inadvertent modification by soft ware as well as to prevent the viewing of proprietary program code and constants The Program Store Write Enable bit PSWE in register PSCTL and the Program Store Erase Enable bit PSEE in register PSCTL bits protect the Flash memory from accidental modification by software PSWE must be explicitly set to 1 before software can modify the Flash memory both PSWE and PSEE must be set to 1 before software can erase Flash memory Additional security features prevent proprietary program code and data constants from being read or altered across the C2 interface A Security Lock Byte located at the last byte of Flash user space offers protection of the Flash program memory from access reads writes or erases by unprotected code or the C2 interface The Flash security mechanism allows the user to lock n 512 byte Flash pages starting at page 0 addresses 0x0000 to 0x01FF where n is the 1 s c
307. synchronous full duplex communication It can operate in a point to point serial communications application or as a node on a multi processor serial interface To operate in a point to point application where there are only two devices on the serial bus the MCE1 bit in SMOD1 should be cleared to 0 For operation as part of a multi processor communications bus the MCE1 and XBE1 bits should both be set to 1 In both types of applications data is transmitted from the microcontrol ler on the TX1 pin and received on the RX1 pin The TX1 and RX1 pins are configured using the crossbar and the Port I O registers as detailed in Section 15 Port Input Output on page 147 In typical UART communications The transmit TX output of one device is connected to the receive RX input of the other device either directly or through a bus transceiver as shown in Figure 19 5 RS232 LEVEL Ax _ C8051Fxxx TRANSLATOR TX TX MCU gt lt C8051Fxxx RX RX Figure 19 5 Typical UART Interconnect Diagram 19 3 1 Data Transmission Data transmission is double buffered and begins when software writes a data byte to the SBUF1 register Writing to SBUF1 places data in the Transmit Holding Register and the Transmit Holding Register Empty flag THRE1 will be cleared to 0 If the UARTS shift register is empty i e no transmission is in progress the data will be placed in the sh
308. t FIFO Access 172 USB Register Definition 16 7 FADDR USBO Function Address 173 USB Register Definition 16 8 POWER USBO Power 175 USB Register Definition 16 9 FRAMEL USBO Frame Number Low 176 USB Register Definition 16 10 FRAMEH USBO Frame Number High 176 USB Register Definition 16 11 INTINT USBO IN Endpoint Interrupt 177 USB Register Definition 16 12 OUT1INT USBO Out Endpoint Interrupt 177 USB Register Definition 16 13 CMINT USBO Common Interrupt 178 USB Register Definition 16 14 IN1IE USBO IN Endpoint Interrupt Enable 179 USB Register Definition 16 15 OUT1IE USBO Out Endpoint Interrupt Enable 179 USB Register Definition 16 16 CMIE USBO Common lnterrupt Enable 180 USB Register Definition 16 17 EOCSR USBO EndpointO Control 183 USB Register Definition 16 18 EOCNT USBO Endpoint 0 Data Count 184 USB Register Definition 16 19 EINCSRL USBO IN Endpoint Control Low Byte 186 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 USB Register Definition 16 20 EINCSRH USBO IN Endpoint Control High Byte 187 USB Register Definition 16 21 EOUTCSRL USBO OUT Endpoint Control Low Byte 189 USB Register Definition 16 22 EOUTCSRH USBO OUT Endpoint Control High Byte 190 USB Register Definition 16 23 EOUTCNTL USBO OUT Endpoint Count Low 19
309. t High Byte EOCH holds the upper 2 bits of the 10 bit number of data bytes in the last received packet in the current OUT endpoint FIFO This number is only valid while OPRDY 1 190 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 Table 16 4 USB Transceiver Electrical Characteristics Vpp 3 0 to 3 6 V 40 to 85 C unless otherwise specified Parameters Symbol Conditions Min Typ Max Units Transmitter Output High Voltage VoH 2 8 V Output Low Voltage VoL 0 8 V Output Crossover Point Vcns 1 3 2 0 V Driving High 38 Output Impedance 2 Driving Low 38 Full Speed D Pull up Pull up Resistance Rpu 1 425 1 5 1 575 ko Low Speed D Pull up Low Speed 75 300 Output Rise Time TR ns Full Speed 4 20 Low Speed 75 300 Output Fall Time TF ns Full Speed 4 20 Receiver Differential Input i Vpi D D9 0 2 V Sensitivity Differential Input Common V Mode Range PM We 29 s Input Leakage Current IL Pullups Disabled lt 1 0 Note Refer to the USB Specification for timing diagrams and symbol definitions e Rev 0 5 191 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 NOTES 192 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 17 SMBus The SMBus O interface is a two wire bi directional serial bus The SMBus is compliant with the System Management Bus Specification version 1 1 and compa
310. t bit 2 2 CPL C Complement Carry 1 1 CPL bit Complement direct bit 2 2 ANL C bit AND direct bit to Carry 2 2 ANL C bit AND complement of direct bit to Carry 2 2 ORL C bit OR direct bit to carry 2 2 ORL C bit OR complement of direct bit to Carry 2 2 MOV bit Move direct bit to Carry 2 2 MOV bit C Move Carry to direct bit 2 2 JC rel Jump if Carry is set 2 2 4 JNC rel Jump if Carry is not set 2 2 4 JB bit rel Jump if direct bit is set 3 3 5 JNB bit rel Jump if direct bit is not set 3 3 5 JBC bit rel Jump if direct bit is set and clear bit 3 3 5 Program Branching ACALL addr11 Absolute subroutine call 2 4 LCALL addr16 Long subroutine call 3 5 RET Return from subroutine 1 6 RETI Return from interrupt 1 6 AJMP addr11 Absolute jump 2 4 LJMP addr16 Long jump 3 5 SJMP rel Short jump relative address 2 4 JMP A DPTR Jump indirect relative to DPTR 1 4 JZ rel Jump if A equals zero 2 2 4 JNZ rel Jump if A does not equal zero 2 2 4 CJNE A direct rel Compare direct byte to A and jump if not equal 3 3 5 CJNE A data rel Compare immediate to A and jump if not equal 3 3 5 CJNE Rn data rel Compare immediate to Register and jump if not equal 3 3 5 CJNE Chi data rel Compare immediate to indirect and jump if not equal 3 4 6 DJNZ Rn rel Decrement Register and jump if not zero 2 2 4 DJNZ direct rel Decrement direct byte and jump if not zero 3 3 5 NOP No operation 1 1 s Rev 0 5 77 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7
311. t is not used when Parity is enabled Bit2 RBX1 Extra Receive Bit RBX1 is assigned the value of the extra bit when XBE1 is set to 1 If XBE1 is cleared to 0 RBX1 will be assigned the logic level of the first stop bit This bit is not valid when Parity is enabled Bit1 TI1 Transmit Interrupt Flag Set to a 1 by hardware after data has been transmitted at the beginning of the STOP bit When the UARTI interrupt is enabled setting this bit causes the CPU to vector to the UARTI interrupt service routine This bit must be cleared manually by software Bito RI1 Receive Interrupt Flag Set to 1 by hardware when a byte of data has been received by UARTI set at the STOP bit sampling time When the UART1 interrupt is enabled setting this bit to 1 causes the CPU to vector to the UART1 interrupt service routine This bit must be cleared manually by soft ware 224 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 19 2 SMOD1 UART1 Mode R W R W R W R W R W R W R W R W Reset Value MCE1 S1PT1 S1PTO PE1 S1DL1 S1DLO XBE1 SBL1 100001100 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito Ad SFR Address OXE5 Bit7 MCE1 Multiprocessor Communication Enable 0 RI will be activated if stop bit s are 1 1 RI will be activated if stop bit s and extra bit are 1 extra bit must be enabled using XBE1 Note This function is not available when hardware parity is enabled
312. t on PSW flags However instruction timing is different than that of the stan dard 8051 9 1 1 Instruction and CPU Timing In many 8051 implementations a distinction is made between machine cycles and clock cycles with machine cycles varying from 2 to 12 clock cycles in length However the CIP 51 implementation is based solely on clock cycle timing All instruction timings are specified in terms of clock cycles Due to the pipelined architecture of the CIP 51 most instructions execute in the same number of clock cycles as there are program bytes in the instruction Conditional branch instructions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken Table 9 1 is the 74 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 CIP 51 Instruction Set Summary which includes the mnemonic number of bytes and number of clock cycles for each instruction 9 1 2 MOVX Instruction and Program Memory The MOVX instruction is typically used to access external data memory Note the C8051F340 1 2 3 4 5 6 7 does not support off chip data or program memory In the CIP 51 the MOVX write instruction is used to accesses external RAM XRAM and the on chip program memory space implemented as re programma ble Flash memory The Flash access feature provides a mechanism for the CIP 51 to update program code and use the program memory space for non volatile data storage Refer to Section
313. t3 CD USB Control CIP 51 Core Status and Interrupt Registers USB FIFOs 1k RAM Figure 16 1 USBO Block Diagram Important Note This document assumes a comprehensive understanding of the USB Protocol Terms and abbreviations used in this document are defined in the USB Specifi cation We encourage you to review the latest version of the USB Specification before pro ceeding Note The C8051F340 1 2 3 4 5 6 7 cannot be used as a USB Host device SILICON LABORATORIES Rev 0 5 163 C8051F340 1 2 3 4 5 6 7 16 1 Endpoint Addressing A total of eight endpoint pipes are available The control endpoint EndpointO always functions as a bi directional IN OUT endpoint The other endpoints are implemented as three pairs of IN OUT endpoint pipes Table 16 1 Endpoint Addressing Scheme Endpoint Associated Pipes USB Protocol Address Ordo GUT 0x00 tem ERU S Epona oo EGER OUT 0x03 16 2 USB Transceiver The USB Transceiver is configured via the USBOXCN register shown in SFR Definition 16 1 This configu ration includes Transceiver enable disable pull up resistor enable disable and device speed selection Full or Low Speed When bit SPEED 1 USBO operates as a Full Speed USB function and the on chip pull up resistor if enabled appears on the D pin When bit SPEED 0 USBO operates as a Low Speed USB function and the on ch
314. ta is transferred most significant bit first The MISO pin is placed in a high impedance state when the SPI module is disabled and when the SPI operates in 4 wire mode as a slave that is not selected When acting as a slave in 3 wire mode MISO is always driven by the MSB of the shift register 20 1 3 Serial Clock SCK The serial clock SCK signal is an output from the master device and an input to slave devices It is used to synchronize the transfer of data between the master and slave on the MOSI and MISO lines SPIO gen erates this signal when operating as a master The SCK signal is ignored by a SPI slave when the slave is not selected NSS 1 in 4 wire slave mode 20 1 4 Slave Select NSS The function of the slave select NSS signal is dependent on the setting of the NSSMD1 and NSSMDO bits in the SPIOCN register There are three possible modes that can be selected with these bits 1 NSSMDf 1 0 00 3 Wire Master or 3 Wire Slave Mode SPIO operates in 3 wire mode and NSS is disabled When operating as a slave device SPIO is always selected in 3 wire mode Since no select signal is present SPIO must be the only slave on the bus in 3 wire mode This is intended for point to point communication between a master and one slave 2 NSSMD 1 0 01 4 Wire Slave or Multi Master Mode SPIO operates in 4 wire mode and NSS is enabled as an input When operating as a slave NSS selects the SPIO device When operating as a master a 1 to
315. tection is enabled bit SUSEN in register POWER this bit is set by hard ware when Suspend signaling is detected on the bus This bit is cleared when software reads the CMINT register 0 Suspend interrupt inactive 1 Suspend interrupt active 178 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 USB Register Definition 16 14 IN1IE USBO IN Endpoint Interrupt Enable R W R W R W R W R W INSE R W IN2E R W IN1E R W EPOE Bit7 Bit3 Bit2 Bit Bito Bits7 4 Bit6 Bit5 Bit4 Bit3 Unused Read 0000b Write don t care INSE IN Endpoint 3 Interrupt Enable 0 IN Endpoint 3 interrupt disabled 1 IN Endpoint 3 interrupt enabled IN2E IN Endpoint 2 Interrupt Enable 0 IN Endpoint 2 interrupt disabled 1 IN Endpoint 2 interrupt enabled IN1E IN Endpoint 1 Interrupt Enable 0 IN Endpoint 1 interrupt disabled 1 IN Endpoint 1 interrupt enabled EPOE Endpoint 0 Interrupt Enable 0 Endpoint 0 interrupt disabled 1 Endpoint 0 interrupt enabled Bit2 Bit Bito Reset Value 00001111 USB Address 0x07 USB Register Definition 16 15 OUT11E USBO Out Endpoint Interrupt Enable R W R W R W R W R W R W R W R W OUTSE OUT2E OUTIE Bit7 Bits7 4 Bit3 Bit2 Bit1 Bito e Rev 0 5 Bit6 Bit5 Bit4 Bit3 Unused Read 0000b Write don t care OUTSE OUT Endpoint 3 In
316. temperature this temperature must be known Step 2 Power the device and delay for a few seconds to allow for self heating Step 3 Perform an ADC conversion with the temperature sensor selected as the positive input and GND selected as the negative input Step 4 Calculate the offset characteristics and store this value in non volatile memory for use with subsequent temperature sensor measurements Figure 5 3 shows the typical temperature sensor error assuming a 1 point calibration at 25 C Note that parameters which affect ADC measurement in particular the voltage reference value will also affect temperature measurement s Rev 0 5 43 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 5 0 5 0 0 0 4 0 4 0 0 0 3 0 3 0 0 Error degrees C 3 00 3 00 4 00 4 00 5 00 5 00 Temperature degrees C Figure 5 3 Temperature Sensor Error with 1 Point Calibration VREF 2 40 V 44 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 5 3 Modes of Operation ADCO has a maximum conversion speed of 200 ksps The ADCO conversion clock is a divided version of the system clock determined by the ADOSC bits in the ADCOCF register system clock divided by ADOSC 1 for 0 lt ADOSC lt 31 5 3 1 Starting a Conversion A conversion can be initiated in one of five ways depending on the programmed states of the ADCO Start of Conversion Mode bits ADOCM2
317. tered by any other reset source For example if the Vpp monitor is enabled and a software reset is performed the Vpp monitor will still be enabled after the reset Important Note The Vpp monitor must be enabled before it is selected as a reset source Selecting the Vpp monitor as a reset source before it is enabled and stabilized will cause a system reset The procedure for configuring the Vpp monitor as a reset source is shown below Step 1 Enable the Vpp monitor VDMOCN 7 41 Step 2 Wait for the Vpp monitor to stabilize see Table 11 1 for the Vpp Monitor turn on time Step 3 Select the Vpp monitor as a reset source RSTSRC 1 117 See Figure 11 2 for Vpp monitor timing See Table 11 1 for complete electrical characteristics of the Vpp monitor SFR Definition 11 1 VDMOCN Vpp Monitor Control R W R R R R R R R Reset Value VDMEN VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved Variable Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address OxFF Bit7 VDMEN Vpp Monitor Enable This bit turns the Vpp monitor circuit on off The Vpp Monitor cannot generate system resets until it is also selected as a reset source in register RSTSRC SFR Definition 11 2 The Vpp Monitor must be allowed to stabilize before it is selected as a reset source Selecting the Vpp monitor as a reset source before it has stabilized will generate a system reset See Table 11 1 for the minimum Vpp
318. terface uses a clock signal C2CK and a bi directional C2 data signal C2D to transfer information between the device and a host system See the C2 Interface Specification for details on the C2 protocol 23 1 C2 Interface Registers The following describes the C2 registers necessary to perform Flash programming functions through the C2 interface All C2 registers are accessed through the C2 interface as described in the C2 Interface Spec ification C2 Register Definition 23 1 C2ADD C2 Address Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Bits7 0 The C2ADD register is accessed via the C2 interface to select the target Data register for C2 Data Read and Data Write commands Address Description 0x00 Selects the Device ID register for Data Read instructions 0x01 Selects the Revision ID register for Data Read instructions 0x02 Selects the C2 Flash Programming Control register for Data Read Write instructions OxAD Selects the C2 Flash Programming Data register for Data Read Write instructions C2 Register Definition 23 2 DEVICEID C2 Device ID Reset Value 00001111 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito This read only register returns the 8 bit device ID OxOF C8051F340 1 2 3 4 5 6 7 s Rev 0 5 279 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 C2 Register Definition 23 3 REVID C2 Revision ID
319. terrupt Enable 0 OUT Endpoint 3 interrupt disabled 1 OUT Endpoint 3 interrupt enabled OUT2E OUT Endpoint 2 Interrupt Enable 0 OUT Endpoint 2 interrupt disabled 1 OUT Endpoint 2 interrupt enabled OUT1E OUT Endpoint 1 Interrupt Enable 0 OUT Endpoint 1 interrupt disabled 1 OUT Endpoint 1 interrupt enabled Unused Read 0 Write don t care SILICON LABORATORIES Bit2 Bit1 Bito Reset Value 00001110 USB Address 0x09 179 C8051F340 1 2 3 4 5 6 7 USB Register Definition 16 16 CMIE USBO Common Interrupt Enable R W R W R W R W R W R W R W R W Reset Value SOFE RSTINTE RSUINTE SUSINTE 00000110 Bit7 Bits7 4 Bit3 Bit2 Bit1 Bito Bite Bit5 Bit4 Bit3 Bit2 Bito USB Address 0x0B Unused Read 0000b Write don t care SOFE Start of Frame Interrupt Enable 0 SOF interrupt disabled 1 SOF interrupt enabled RSTINTE Reset Interrupt Enable 0 Reset interrupt disabled 1 Reset interrupt enabled RSUINTE Resume Interrupt Enable 0 Resume interrupt disabled 1 Resume interrupt enabled SUSINTE Suspend Interrupt Enable 0 Suspend interrupt disabled 1 Suspend interrupt enabled 16 9 The Serial Interface Engine The Serial Interface Engine SIE performs all low level USB protocol tasks interrupting the processor when data has successfully been transmitted or received When receiving data the SIE will
320. th auto reload 1 1 Mode 3 Two 8 bit counter timers 248 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 21 3 CKCON Clock Control R W R W R W R W Reset Value T2MH T2ML SCA1 SCAO 00000000 Bit5 Bit4 Bit Bito SFR Address Ox8E T3MH Timer 3 High Byte Clock Select This bit selects the clock supplied to the Timer 3 high byte if Timer 3 is configured in split 8 bit timer mode T3MH is ignored if Timer 3 is in any other mode 0 Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN 1 Timer 3 high byte uses the system clock T3ML Timer 3 Low Byte Clock Select This bit selects the clock supplied to Timer 3 If Timer 3 is configured in split 8 bit timer mode this bit selects the clock supplied to the lower 8 bit timer 0 Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN 1 Timer 3 low byte uses the system clock T2MH Timer 2 High Byte Clock Select This bit selects the clock supplied to the Timer 2 high byte if Timer 2 is configured in split 8 bit timer mode T2MH is ignored if Timer 2 is in any other mode 0 Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN 1 Timer 2 high byte uses the system clock T2ML Timer 2 Low Byte Clock Select This bit selects the clock supplied to Timer 2 If Timer 2 is configured in split 8 bit timer mode this bit selects the clock supplied to the lower 8 bit
321. than 10 SMBus clock source periods see Figure 17 4 When a Free Timeout is detected the interface will respond as if a STOP was detected an interrupt will be generated and STO will be set s Rev 0 5 199 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 R W SFR Definition 17 1 SMBOCF SMBus Clock Configuration R W R R W R W R W R W R W ENSMB INH BUSY EXTHOLD SMBTOE SMBFTE SMBCS1 SMBCSO Bit7 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bits1 0 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito Reset Value 00000000 SFR Address OxC 1 ENSMB SMBus Enable This bit enables disables the SMBus interface When enabled the interface constantly mon itors the SDA and SCL pins 0 SMBus interface disabled 1 SMBus interface enabled INH SMBus Slave Inhibit When this bit is set to logic 1 the SMBus does not generate an interrupt when slave events occur This effectively removes the SMBus slave from the bus Master Mode interrupts are not affected 0 SMBus Slave Mode enabled 1 SMBus Slave Mode inhibited BUSY SMBus Busy Indicator This bit is set to logic 1 by hardware when a transfer is in progress It is cleared to logic 0 when a STOP or free timeout is sensed EXTHOLD SMBus Setup and Hold Time Extension Enable This bit controls the SDA setup and hold times according to 0 SDA Extended Setup and Hold Times d
322. tible with the I2C serial bus Reads and writes to the interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial transfer of the data Data can be transferred at up to 1 10th of the system clock as a master or slave this can be faster than allowed by the SMBus specification depending on the system clock used A method of extending the clock low duration is available to accommodate devices with different speed capabilities on the same bus The SMBus interface may operate as a master and or slave and may function on a bus with multiple mas ters The SMBus provides control of SDA serial data SCL serial clock generation and synchronization arbitration logic and START STOP control and generation Three SFRs are associated with the SMBus SMBOCF configures the SMBus SMBOCN controls the status of the SMBus and SMBODAT is the data register used for both transmitting and receiving SMBus data and slave addresses SMBOCN SMBOCF MITISISIAIAIAIS E I IBIEISISISIS A X T T CIRIC NINIU XIMMM M SIMIAIOIKIBIK SHIS T RIL IYIHIT F CIC E D OIOITISIS RIE S L EE 1 0 E D AAAAAAAA A LJ 4 00 TO Overflow 01 T1 Overflow 10 TMR2H
323. timer 0 Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN 1 Timer 2 low byte uses the system clock T1M Timer 1 Clock Select This select the clock source supplied to Timer 1 T1M is ignored when C T1 is set to logic 1 0 Timer 1 uses the clock defined by the prescale bits SCA1 SCAO 1 Timer 1 uses the system clock TOM Timer 0 Clock Select This bit selects the clock source supplied to Timer 0 TOM is ignored when C TO is set to logic 1 0 Counter Timer 0 uses the clock defined by the prescale bits SCA1 SCAO 1 Counter Timer 0 uses the system clock SCA1 SCAO Timer 0 1 Prescale Bits These bits control the division of the clock supplied to Timer 0 and or Timer 1 if configured to use prescaled clock inputs SCA1 5 0 Prescaled Clock 0 0 System clock divided by 12 0 1 System clock divided by 4 1 0 System clock divided by 48 1 1 External clock divided by 8 Note External clock divided by 8 is synchronized with the System clock s Rev 0 5 249 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 21 4 TLO Timer 0 Low Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bito SFR Address Ox8A Bits 7 0 TLO Timer 0 Low Byte The TLO register is the low byte of the 16 bit Timer 0 SFR Definition 21 5 TL1 Timer 1 Low Byte R W R W R W R W R W R W R W
324. tion 198 17 4 2 SMBOCN Control 201 14 4 3 Data Registe ipei Eb bp needs bb 204 17 5 SMBus Trasie MOUOUGS s La dia 204 17 5 T Master Transmitter MOGd6 coi rn o qp ore ERO n paene eU 204 17 5 2 Master Receiver 24 4 40 206 17 5 3 Slave Receiver a 207 17 5 4 Slave Transmitter MOGOG iei te tides 208 17 6 9MB s Status Decodlrig on 208 18 VARTO 211 18 1 Enhanced Baud Rate 212 18 2 Operational Modes eee paa ect he ns 212 18 2148 BIE UABUT our ko r 213 18 2 9 BIEDIAEBUE ro 214 18 3 Multiprocessor Communications x eee hnan 214 19 UART1 C8051F340 1 4 5 Only ra cotra a a ona 219 19 T Baud Rate Generator uio are eee bok hod to deme eie 220 19 2 Data Format si oi ade cetera abba 221 19 3 Configuration and 222 19 3 1 Data Transmission Hte 222 19 32 Data ROCODIUOFP eit pte xeu esee Ueda ewe 222 19 3 3 Multiprocessor Communications eese 223 20 Enhanced Serial Peripheral Interface SPlIO
325. tle within 1 4 LSB tis the required settling time in seconds is the sum of the AMUXO resistance and any external source resistance nis the ADC resolution in bits 10 Differential Mode Single Ended Mode MUX T MUX Select Px x Px x 5k 5k Csamp e CsympLe Csaupie 5k MUX Select Figure 5 5 ADCO Equivalent Input Circuits s Rev 0 5 47 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 5 1 AMXOP AMUXO Positive Channel Select R R W R W R W R W R W AMXOP4 AMXOP2 AMXOP1 AMXOPO Bite Bit5 Bit4 Bit3 Bit2 Bit Bito Reset Value 00000000 SFR Address OxBB Bits7 5 UNUSED Read 000b Write don t care Bits4 0 4 0 AMUXO Positive Input Selection 4 0 ADCO Positive Input 32 pin Package P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 P2 0 P2 1 P2 2 P2 3 P2 4 P2 5 P2 6 P2 7 P3 0 P0 0 PO 1 PO 4 PO 5 ADCO Positive Input 48 pin Package P2 0 P2 1 P2 2 P2 3 P2 5 P2 6 P3 0 P3 1 P3 4 P3 5 P3 7 P4 0 P4 3 P4 4 P4 5 P4 6 RESERVED PO 3 PO 4 P1 1 P1 2 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 11101 RESERVED RESERVED 11110 Temp Senso
326. tor Calibration 137 OSCICN 0xB2 Internal Oscillator Control 136 OSCLCN 0x86 Internal Low Freguency Oscillator Control 138 OSCXCN OxB1 External Oscillator Control 141 PO 0x80 Port 0 Latch 154 POMDIN OxF1 Port 0 Input Mode Configuration 154 POMDOUT 0 4 Port 0 Output Mode Configuration 155 POSKIP 0xD4 Port 0 Skip 155 P1 0x90 Port 1 Latch 156 82 Rev 0 5 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFRs are listed in alphabetical order All undefined SFR locations are reserved Table 9 3 Special Function Registers Continued Register Address Description Page P1MDIN OxF2 Port 1 Input Mode Configuration 156 P1MDOUT 0 5 Port 1 Output Mode Configuration 156 P1SKIP 0xD5 Port 1 Skip 157 P2 0 0 Port 2 Latch 157 P2MDIN 0xF3 Port 2 Input Mode Configuration 157 P2MDOUT 0 6 Port 2 Output Mode Configuration 158 P2SKIP 0xD6 Port 2 Skip 158 P3 0 0 Port 3 Latch 159 PSMDIN 0xF4 Port 3 Input Mode Configuration 159 P3MDOUT 0 Port 3 Output Mode Configuration 159 P3SKIP OxDF Port 3Skip 160 P4 0xC7 Port 4 Latch 160 P4MDIN OxF5 Port 4 Input Mode Configuration 161 PAMDOUT Port 4 Output Mode Configuration 161 PCAOCN OxD8 PCA Control 274 0xFC PCA Capture 0 High 278 PCAOCPH1 0 PCA Capture 1 High 278 PCAOCPH2 0 PCA Capture 2 High 278
327. torO be configured as a reset source by writing a 1 to the CORSEF flag RSTSRC 5 ComparatorO should be enabled and allowed to settle prior to writing to CORSEF to prevent any turn on chatter on the output from generating an unwanted reset The ComparatorO reset is active low if the non inverting input voltage on CPO is less than the inverting input voltage on CPO a system reset is generated After a Comparator0 reset the CORSEF flag RSTSRC 5 will read 1 signifying Comparator0 as the reset source otherwise this bit reads 0 The state of the RST is unaffected by this reset 11 6 PCA Watchdog Timer Reset The programmable Watchdog Timer WDT function of the Programmable Counter Array PCA can be used to prevent software from running out of control during a system malfunction The PCA WDT function can be enabled or disabled by software as described in Section 22 3 Watchdog Timer Mode on page 272 the WDT is enabled and clocked by SYSCLK 12 following any reset If a system malfunction prevents user software from updating the WDT a reset is generated and the WDTRSF bit RSTSRC 5 is set to 1 The state of the RST pin is unaffected by this reset 11 7 Flash Error Reset If a Flash read write erase or program read targets an illegal address a system reset is generated This may occur due to any of the following A Flash write or erase is attempted above user code space This occurs when PSWE i
328. tration A byte has been transmitted and an ACK SI NACK received A byte has been received A START or repeated START followed by a slave address R W has been received A STOP has been received s Rev 0 5 SILICON LABORATORIES 203 C8051F340 1 2 3 4 5 6 7 17 4 3 Data Register The SMBus Data register SMBODAT holds a byte of serial data to be transmitted or one that has just been received Software may safely read or write to the data register when the SI flag is set Software should not attempt to access the SMBODAT register when the SMBus is enabled and the SI flag is cleared to logic 0 as the interface may be in the process of shifting a byte of data into or out of the register Data in SMBODAT is always shifted out MSB first After a byte has been received the first bit of received data is located at the MSB of SMBODAT While data is being shifted out data on the bus is simultaneously being shifted in SMBODAT always contains the last data byte present on the bus In the event of lost arbi tration the transition from master transmitter to slave receiver is made with the correct data or address in SMBODAT SFR Definition 17 3 SMBODAT SMBus Data R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address 0xC2 Bits7 0 SMBODAT SMBus Data The SMBODAT register contains a byte of data to be transmitted on the SMBus seri
329. trol R W R W R W R W R W Reset Value TEMPE BIASE REFBE 00000000 Bit5 Bit4 Bit2 Bit Bito SFR Address OxD1 UNUSED Read 00000b Write don t care REFSL Voltage Reference Select This bit selects the source for the internal voltage reference 0 VREF pin used as voltage reference 1 Vpp used as voltage reference TEMPE Temperature Sensor Enable Bit 0 Internal Temperature Sensor off 1 Internal Temperature Sensor on BIASE Internal Analog Bias Generator Enable Bit 0 Internal Bias Generator off 1 Internal Bias Generator on REFBE Internal Reference Buffer Enable Bit 0 Internal Reference Buffer disabled 1 Internal Reference Buffer enabled Internal voltage reference driven on the VREF pin Table 6 1 Voltage Reference Electrical Characteristics Vpp 3 0 V 40 to 85 Unless Otherwise Specified Parameter Conditions Min Typ Max Units Internal Reference REFBE 1 Output Voltage 25 C ambient 2 38 2 44 2 50 V VREF Short Circuit Current 10 mA VREF Temperature Coeffi 15 pom C cient Load Regulation Load 0 to 200 to GND 1 5 ppm uA VREF Turn on Time 1 p ms 0 1 UF ceramic 2 f VREF Turn on Time 2 0 1 ceramic bypass 20 Us VREF Turn on Time 3 no bypass cap 10 us Power Supply Rejection 140 ppm V External Reference REFBE 0 Input Voltage Range 0 V Input Current Sample Rate 200 ksps VREF 12
330. truction is used with an 8 bit address operand such as QR1 then the high byte of the 16 bit address is provided by the External Memory Interface Con trol Register EMIOCN shown in SFR Definition 13 1 Note the MOVX instruction can also be used for writing to the FLASH memory See Section 12 Flash Memory on page 109 for details The MOVX instruction accesses XRAM by default 13 1 Accessing XRAM The XRAM memory space is accessed using the MOVX instruction The MOVX instruction has two forms both of which use an indirect addressing method The first method uses the Data Pointer DPTR a 16 bit register which contains the effective address of the XRAM location to be read from or written to The sec ond method uses RO or R1 in combination with the EMIOCN register to generate the effective XRAM address Examples of both of these methods are given below 13 1 1 16 Bit MOVX Example The 16 bit form of the MOVX instruction accesses the memory location pointed to by the contents of the DPTR register The following series of instructions reads the value of the byte at address 0x1234 into the accumulator A MOV DPTR 1234h load DPTR with 16 bit address to read 0x1234 MOVX A DPTR load contents of 0x1234 into accumulator A The above example uses the 16 bit immediate MOV instruction to set the contents of DPTR Alternately the DPTR can be accessed through the SFR registers DPH which contains the upper 8 bits of DPTR and DPL which c
331. tting When set to 11111b the oscillator operates at is slowest set ting The contents of this register are factory calibrated to produce a 12 MHz internal oscilla tor frequency Note The contents of this register are undefined when Clock Recovery is enabled See Section 16 4 USB Clock Configuration on page 170 for details on Clock Recovery 14 2 Programmable Internal Low Frequency L F Oscillator The C8051F340 1 2 3 4 5 devices include a programmable internal oscillator which operates at a nominal frequency of 80 kHz The low frequency oscillator circuit includes a divider that can be changed to divide the clock by 1 2 4 or 8 using the OSCLD bits in the OSCLCN register see SFR Definition 14 3 Addi tionally the OSCLF bits OSCLCN5 2 can be used to adjust the oscillator s output frequency 14 2 1 Calibrating the Internal L F Oscillator Timers 2 and 3 include capture functions that can be used to capture the oscillator frequency when run ning from a known time base When either Timer 2 or Timer 3 is configured for L F Oscillator Capture Mode a falling edge Timer 2 or rising edge Timer 3 of the low frequency oscillator s output will cause a capture event on the corresponding timer As a capture event occurs the current timer value TMRnH TMRnL is copied into the timer reload registers TMRnRLH TMRnRLL By recording the differ ence between two successive timer capture values the low frequency oscillator s period
332. ud rates details in Section 19 1 Baud Rate Generator on page 220 A received data FIFO allows UART1 to receive up to three data bytes before data is lost and an overflow occurs UART1 has six associated SFRs Three are used for the Baud Rate Generator SBCON1 SBRLH1 and SBRLL1 two are used for data formatting control and status functions SCON1 SMOD1 and one is used to send and receive data SBUF1 The single SBUF1 location provides access to both the transmit holding register and the receive FIFO Writes to SBUF1 always access the Transmit Holding Register Reads of SBUF1 always access the first byte of the Receive FIFO it is not possible to read data from the Transmit Holding Register With UART1 interrupts enabled an interrupt is generated each time a transmit is completed is set in SCON 1 or a data byte has been received RI1 is set in SCON1 The UART1 interrupt flags are not cleared by hardware when the CPU vectors to the interrupt service routine They must be cleared manually by software allowing software to determine the cause of the UARTI interrupt transmit complete or receive complete Note that if additional bytes are available in the Receive FIFO the RI1 bit cannot be cleared by software TX Dx Baud Rate Generator Logic TXI SBREHT
333. ule s capture compare register cause the logic level on the CEXn pin to toggle If the PWMn bit is also set to logic 1 the module operates in Frequency Output Mode 0 Disabled 1 Enabled Bit1 PWMn Pulse Width Modulation Mode Enable This bit enables disables the PWM function for PCA module n When enabled a pulse width modulated signal is output on the CEXn pin 8 bit PWM is used if PWM16n is cleared 16 bit mode is used if PWM16n is set to logic 1 If the TOGn bit is also set the module operates in Frequency Output Mode 0 Disabled 1 Enabled Bito ECCFn Capture Compare Flag Interrupt Enable This bit sets the masking of the Capture Compare Flag CCFn interrupt 0 Disable CCFn interrupts 1 Enable a Capture Compare Flag interrupt request when CCFn is set 276 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 22 4 PCAOL PCA Counter Timer Low Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito SFR Address OxF9 Bits 7 0 PCAOL PCA Counter Timer Low Byte The PCAOL register holds the low byte LSB of the 16 bit PCA Counter Timer SFR Definition 22 5 PCAOH PCA Counter Timer High Byte R W R W R W R W R W R W R W R W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bito SFR Address OxFA Bits 7 0 PCAOH PCA Counter Timer High Byte The PCAOH register hol
334. unction Register SFR Memory Map F8 SPIOCN PCAOL PCAOH PCAOCPL4 PCAOCPHA4 VDMOCN FO B POMDIN P1MDIN P2MDIN P3MDIN P4MDIN EIP1 EIP2 E8 ADCOCN PCAOCPL1 PCAOCPH1 2 2 RSTSRC EO ACC XBRO 1 XBR2 ITO1CF SMOD1 EIE1 EIE2 D8 PCAOCN PCAOMD 1 2 4 P3SKIP DO PSW REFOCN SCON1 SBUF1 POSKIP P1SKIP P2SKIP USBOXCN C8 TMR2CN REGOCN TMR2RLL TMR2RLH TMR2L TMR2H 0 SMBOCN SMBOCF SMBODAT ADCOGTL ADCOGTH ADCOLTL ADCOLTH P4 B8 IP CLKMUL AMXON AMXOP ADCOCF ADCOL ADCOH BO P3 OSCXCN OSCICN OSCICL SBRLL1 SBRLH1 FLSCL FLKEY A8 IE CLKSEL EMIOCN SBCON1 P4MDOUT PFEOCN AO P2 SPIOCFG SPIOCKR SPIODAT POMDOUT PIMDOUT POMDOUT PSMDOUT 98 SCONO SBUFO CPTICN CPTOCN CPT1MD CPTOMD CPTIMX CPTOMX 90 P1 TMRS3CN TMR3RLL TMRSRLH TMR3L TMR3H USBOADR USBODAT 88 TCON TMOD TLO TL1 THO TH1 CKCON PSCTL 80 PO SP DPL DPH EMIOTC EMIOCF OSCLCN PCON 0 8 1 9 2 A 3 B 4 C 5 D 6 E 7 F bit addressable s Rev 0 5 81 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFRs are listed in alphabetical order All undefined SFR locations are reserved Table 9 3 Special Function Registers
335. unloaded from the OUT endpoint FIFO s Rev 0 5 189 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 USB Register Definition 16 22 EOUTCSRH USBO OUT Endpoint Control High Byte R W R W R W R W R R R R Reset Value DBOEN ISO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito USB Address 0x15 Bit7 DBOEN Double buffer Enable 0 Double buffering disabled for the selected OUT endpoint 1 Double buffering enabled for the selected OUT endpoint Bit6 ISO Isochronous Transfer Enable This bit enables disables isochronous transfers on the current endpoint 0 Endpoint configured for bulk interrupt transfers 1 Endpoint configured for isochronous transfers Bits5 0 Unused Read 000000b Write don t care USB Register Definition 16 23 EOUTCNTL USBO OUT Endpoint Count Low R R R R R R R R Reset Value EOCL 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito USB Address 0x16 Bits7 0 EOCL OUT Endpoint Count Low Byte EOCL holds the lower 8 bits of the 10 bit number of data bytes in the last received packet in the current OUT endpoint FIFO This number is only valid while OPRDY 1 USB Register Definition 16 24 EOUTCNTH USBO OUT Endpoint Count High R R R R R R R R Reset Value EOCH 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit Bito USB Address 0x17 Bits7 2 Unused Read 00000 Write don t care 51 0 EOCH OUT Endpoint Coun
336. ved EndpointO The new address takes effect when the device request completes 16 7 Function Configuration and Control The USB register POWER SFR Definition 16 8 is used to configure and control USBO at the device level enable disable Reset Suspend Resume handling etc USB Reset The USBRST bit POWER 3 is set to 41 by hardware when Reset signaling is detected on the bus Upon this detection the following occur 1 The USBO Address is reset FADDR 0x00 2 Endpoint FIFOs are flushed 3 Control status registers are reset to 0x00 EOCSR EINCSRL EINCSRH EOUTCSRL EOUTCSRH 4 USB register INDEX is reset to 0x00 5 USB interrupts excluding the Suspend interrupt are enabled and their corresponding flags cleared 6 AUSB Reset interrupt is generated if enabled Writing a 1 to the USBRST bit will generate an asynchronous USBO reset All USB registers are reset to their default values following this asynchronous reset Suspend Mode With Suspend Detection enabled SUSEN 1 USBO will enter Suspend Mode when Suspend signaling is detected on the bus An interrupt will be generated if enabled SUSINTE 1 The Suspend Interrupt Service Routine ISR should perform application specific configuration tasks such as disabling appropriate peripherals and or configuring clock sources for low power modes See Section s Rev 0 5 173 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7
337. when an instruction writes a data byte to the SBUFO register The TIO Transmit Interrupt Flag SCONO 1 is set at the end of the transmission the beginning of the stop bit time Data reception can begin any time after the RENO Receive Enable bit SCONO 4 is set to 1 After the stop bit is received the data byte will be loaded into the SBUFO receive register if the following conditions are met 1 RIO must be logic 0 and 2 if MCEO is logic 1 the 9th bit must be logic 1 when MCEO is logic 0 the state of the ninth data bit is unimportant If these conditions are met the eight bits of data are stored in SBUFO the ninth bit is stored in RB80 and the RIO flag is set to 1 If the above conditions are not met SBUFO and RB80 will not be loaded and the RIO flag will not be set to 1 A UARTO interrupt will occur if enabled when either TIO or RIO is set to 1 MARK START ar D Y b gt X os o jy o o gt Jj 08 STOP BIT SPACE pir times Pf fp pp o O fF 0 d 04 0 d d 1 Figure 18 5 9 Bit UART Timing Diagram 18 3 Multiprocessor Communications 9 Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit When a master processor wants to transmit to one or more slaves it first sends an address byte to select the target s An address byte differs from a data byte in that its ninth
338. which Port pin is used as the Comparator0 positive input CMXOP1 1 CMXOPO Positive Input Positive Input 32 pin Package 48 pin Package P1 0 P2 0 P1 4 P2 5 P2 0 P3 4 P2 4 P4 3 0 0 PO 3 Note that the port pins used by the comparator depend on the package type 32 pin or 48 pin e Rev 0 5 63 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 7 3 CPTOMD Comparator0 Mode Selection R W R W R W R W R W R W R W R W Reset Value CPORIE CPOFIE CPOMD1 CPOMDO 00000010 Bit7 Bit6 Bit5 Bit4 Bit3 Bit Bito SFR Address 0x9D Bits7 6 UNUSED Read 00b Write don t care Bit5 CPORIE ComparatorO Rising Edge Interrupt Enable 0 Comparatoro rising edge interrupt disabled 1 Comparator0 rising edge interrupt enabled Bit4 CPOFIE Falling Edge Interrupt Enable 0 Comparator0 falling edge interrupt disabled 1 Comparatoro falling edge interrupt enabled Bits3 2 UNUSED Read 00b Write don t care Bits1 0 CPOMD1 CPOMDO Comparator0 Mode Select These bits select the response time for ComparatorO Mode CPOMD1 CPOMDO CPO Response Time 0 0 0 Fastest Response 1 0 2 1 0 3 1 1 Lowest Power See Table 7 1 for response time parameters 64 Rev 0 5 e SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 7 4 CPT1CN Comparator1 Control
339. wledge value Note writing a 1 to the ACK bit gen erates an ACK writing a 0 generates a NACK Software should write a 0 to the ACK bit after the last byte is received to transmit a NACK The interface exits Master Receiver Mode after the STO bit is set and a STOP is generated Note that the interface will switch to Master Transmitter Mode if SMBODAT is written while an active Master Receiver Figure 17 6 shows a typical Master Receiver sequence Two received data bytes are shown though any number of bytes may be received Notice that the data byte transferred interrupts occur before the ACK cycle in this mode S SLA R A Data Byte A Data Byte N P Interrupt Received by SMBus S START Interface STOP N Transmitted by READ SMBus Interface SLA Slave Address Figure 17 6 Typical Master Receiver Sequence 206 Rev 0 5 s SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 17 5 3 Slave Receiver Mode Serial data is received SDA and the clock is received SCL When slave events are enabled INH 0 the interface enters Slave Receiver Mode when a START followed by a slave address and direction bit WRITE in this case is received Upon entering Slave Receiver Mode an interrupt is generated and the ACKRQ bit is set Software responds to the received slave address with an ACK or ignores the received slave address with a NACK If the received slave address is ign
340. xceed a specified limit The WDT can be configured and enabled disabled as needed by software With the WDTE and or WDLCK bits set to 1 in the PCAOMD register Module 4 operates as a watchdog timer WDT The Module 4 high byte is compared to the PCA counter high byte the Module 4 low byte holds the offset to be used when WDT updates are performed The Watchdog Timer is enabled on reset Writes to some PCA registers are restricted while the Watchdog Timer is enabled 22 3 1 Watchdog Timer Operation While the WDT is enabled e counter is forced on e Writes to PCAOL and PCAOH are not allowed e clock source bits CPS2 CPSO are frozen Idle control bit CIDL is frozen e Module 4 is forced into Watchdog Timer mode Writes to the Module 4 mode register PCAOCPMA are disabled While the WDT is enabled writes to the CR bit will not change the PCA counter state the counter will run until the WDT is disabled The PCA counter run control CR will read zero if the WDT is enabled but user software has not enabled the PCA counter If a match occurs between PCAOCPH4 and PCAOH while the WDT is enabled a reset will be generated To prevent a WDT reset the WDT may be updated with a write of any value to Upon a PCAOCPHA write PCAOH plus the offset held in PCAOCPLA is loaded into PCAOCPH4 See Figure 22 10 PCAOMD su CEDE Tas S S S F 2 1 0 PCAOCPL4
341. xternal precision reference can be configured as a GPIO Port pin When using an external voltage refer ence or the on chip reference the VREF pin should be configured as analog pin and skipped by the Digital Crossbar To configure the VREF pin for analog mode set the corresponding bit in the PnMDIN register to 0 To configure the Crossbar to skip the VREF pin set the corresponding bit in register PnSKIP to 1 Refer to Section 15 Port Input Output on page 147 for complete Port I O configuration details The temperature sensor connects to the ADCO positive input multiplexer see Section 5 1 Analog Multi plexer on page 42 for details The TEMPE bit in register REFOCN enables disables the temperature sensor While disabled the temperature sensor defaults to a high impedance state and any ADCO mea surements performed on the sensor result in meaningless data i I I I I I I ADOEN ADC Internal Oscillator IOSCEN dur VDD External 9 Voltage Reference EN To Analog Mux R1 Circuit VREF 5 PS I A VREF to ADC GND ui VDD 1 CLKMUL Enable EN _ To Clock Multiplier Temp Sensor REFBE I I v I EN Internal 4 Reference Figure 6 1 Voltage Reference Functional Block Diagram s Rev 0 5 57 SILICON LABORATORIES C8051F340 1 2 3 4 5 6 7 SFR Definition 6 1 REFOCN Reference Con

Silicon Laboratories C8051F340 User's Manual

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