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Silicon Image SiliconDrive SSD-DXXX(I)-4210 User's Manual

1. Operation D De Ds D D3 Do D Do Feature X Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head 1 LBA 1 Drive X Command X ATA COMMAND SET Table 28 ATA Command Set Class Command Name commana pega Son Code FR SC SN CY DH LBA 1 Check Power Mode 98h E5h D 1 Execute Drive 90h D Diagnostics 1 Erase Sector COh Y Y Y Y Y 2 Format Track 50h Y Y Y Y 1 Identify Drive ECh D 1 Idle 97h E3h Y D 1 Idle Immediate 95h E1h l D 1 Initialize Drive 91h Y Y Parameters 1 Read Buffer E4h D 1 Read DMA C8h Y Y Y Y Y 1 Read Multiple C4h Y Y Y Y Y This document and the information contained within it is confidential and proprietary to SiliconSystems Inc 4210D 03DSR SiLICONSYsTEMS PROPRIETARY All unauthorized use and or reproduction is prohibited PAGE 40 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Table 28 ATA Command Set Continued Class Command Name commana GE Code FR SC SN CY DH LBA 1 Read Long Sector 22h 23h Y Y Y Y 1 Read Sector s 20h 21h Y Y Y Y 1 Read Verify Sector s 40h 41h l Y Y Y Y Y 1 Recalibrate 1Xh Y 1 Request Sense 03h D 1 Seek 7Xh Y Y Y Y 1 Set Features EFh Y D 1 Set Multiple Mode C6h Y D
2. protocol Note This function does not apply to SiliconDrive EPs that have DMA disabled Table 39 Read DMA C8h Register D De Ds D3 D3 Do D Do Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16 Drive Head 1 LBA 1 Drive Head Number LBA27 24 Command C8h SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 54 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Read Multiple C4h The Read Multiple command executes similarly to the Read Sector command with the exception that interrupts are issued only when a block containing the counts of sectors defined by the Set Multiple command is transferred Table 40 Read Multiple C4h Register D Dg D5 D Dg D2 Dy Do Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16 Drive Head 1 LBA 1 Drive Head Number LBA27 24 Command C4h SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc
3. 00h No error detected 01h Self test is OK no error 09h Miscellaneous error 20h Invalid command 21h Invalid address requested head or sector invalid 2Fh Address overflow address too large 35h 36h Supply or generated voltage out of tolerance 11h Uncorrectable ECC error 18h Corrected ECC error 05h 30h 32h 37h 3Eh Self test of diagnostic failed 10h 14h ID not found 3Ah Spare sectors exhausted 1Fh Data transfer error aborted command OCh 38h 3Bh 3Ch 3Fh Computed media format 03h Write erase failed SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 71 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Translate Sector 87h The Translate Sector command is not currently supported by the SiliconSystems SiliconDrive EP If the host issues this command the device responds with OxOOh in the data register Table 59 Translate Sector 87h Register D Dg D5 Da D3 D2 Dy Do Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16 Drive Head 1 LBA 1 Drive Head Number LBA27 24 Command 87h SiLICONSYsTEMS P
4. SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 24 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET Table 13 UDMA Data Burst Timing Requirements Continued Symbol Mode 0 Min Max Min Mode 1 Max Mode 2 Min Max Mode 3 Min Max Mode 4 Min Max Comment see Notes 1 and 2 Units ipvs 70 48 30 20 6 Data valid setup time at sender from data valid until STROBE edge see Note 4 ns tovH Data valid hold time at sender from STROBE edge until data may become invalid see Note 4 ns trs 230 200 170 130 120 First STROBE time for device to first negate DSTROBE from STOP during a data in burst LT 150 150 150 100 100 Limited interlock time see Note 3 tMLI 20 20 20 20 20 Interlock time with minimum see Note 3 ns tui Unlimited interlock time see Note 3 ns taz 10 10 10 10 10 Maximum time allowed for output drivers to release from asserted or negated ns tZaH 20 20 20 20 20 Minimum delay time required for output ns tzap Drivers to assert or negate from released tenv 20
5. 12 PAS CON ANACI SIS c 13 True IDE PIO Mode Read Write Access Timing eeeeeeeeeeeeeeeesessssrrrrrrrrrrrrrrnne 13 True IDE Multiword DMA Read Write Access Timing eeeeeeeeeeeeesesereerrereeree 15 Ultra DMA Data Burst Timing Reourements 17 ATA and True IDE Register Decoding eeeeeeeeeeereeeeeeeeeeernnnn 27 Task File Register Specification D 27 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE III FEBRUARY 2 2009 TABLE OF CONTENTS SSD Dxxx I 4210 DATA SHEET ATA Registers Eeer 28 Data Eeer 28 Ee 28 Feat re REgISte e e 29 vl nes Pe 30 Sector uiii Mec RC 31 Cylinder Low d c lcge 32 Cylinder pressi pe T 33 By dale We EE 34 iugi e D alee ee 35 orani E E 36 Alternate Status Register em m 37 Device Control REGIStEr M 38 BINH E 39 ATA Command Block and Set Description eeeeeeeeeeeeeees 40 ATA Command Set arn pasan est 40 Check Power Mode 98h E5PI i eee term editae tea Pega e non tera umts 42 Executive Drive Diagnostic SOLI iae t
6. 7 Busy BSY Set when the drive is busy and unable to process any new ATA commands 6 Data Ready DRDY Set when the device is ready to accept ATA commands from the host 5 Drive Write Fault DWF Always set to 0 4 Drive Seek Complete DSC Set when the drive heads have been positioned over a specific track 3 Data Request DRQ Set when a device is ready to transfer a word or byte of data to or from the host and the device 2 Corrected Data CORR Always set to 0 Index IDX Always set to 0 0 Error ERR Set when an error occurs during the previous ATA command SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 35 FEBRUARY 2 2009 ATA REGISTERS SSD Dxxx I 4210 DATA SHEET COMMAND REGISTER The Command register specifies the ATA command code being issued to the drive by the host Execution of the command begins immediately following the issuance of the command register code by the host Table 23 Command Register Operation D De Ds D D3 Do D Do Read Write ATA Command Code See ATA Command Block and Set Description on page 40 for a listing of the supported ATA commands SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthoriz
7. The Drive Head register is used by the host to specify one of a pair of ATA drives present in the platform Bit s Description 6 LBA Selects between CHS 0 and LBA 1 addressing mode 4 Drive Address DRV Indicates the drive number selected by the host either O or 1 3 0 HS3 to 0 Indicates bits 3 0 of the head number in CHS addressing mode or LBA bits 27 24 in LBA mode CHS to LBA conversion LBA C x HpC H x SpH S 1 LBA to CHS conversion o C LBA HpC x SpH o H LBA SpH mod HpC o S LBA mod SpH 1 Where C is the cylinder number H is the head number S is the sector count HpC is the head count per cylinder count SpH is the sector count per head count track oO 0 Oo Q SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 34 FEBRUARY 2 2009 ATA REGISTERS SSD Dxxx I 4210 DATA SHEET STATUS REGISTER The Status register provides the device s current status to the host The status register is an 8 bit read only register When the contents of the register are read by the host the IREQ bit is cleared Table 22 Status Register Operation D De Ds D4 D3 Do D Do Read Write BSY DRDY DWF DSC DRQ CORR IDX ERR Default Value 0 0 0 0 0 0 0 0 Bit s Description
8. Erase Sector s COh The Erase Sector s command is issued prior to the issuance of a Write Sector s or Write Multiple w o Erase command Table 56 Erase Sector s COh Register D7 Dg Ds D4 D3 Do D Do Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16 Drive Head X LBA X Drive Head Number LBA27 24 Command COh SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 70 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Request Sense 03h The Request Sense command identifies the extended error codes generated by the preceding ATA command The Request Sense command must be issued immediately following the detection of an error via the Error register Table 57 Request Sense 03h Register D7 be Geer cb Seck e oN Feature Sector Count Sector Number Cylinder Low Cylinder High X X OX xx Drive Head 1 X 1 Drive X Command 03h The extended error codes are defined in the following table Table 58 Extended Error Codes Extended Error Codes Description
9. PAGE II FEBRUARY 2 2009 TABLE OF CONTENTS SSD Dxxx I 4210 DATA SHEET TABLE OF CONTENTS egg me T P HH i l i PROVISION tir M I List gae ce E VI List Of Table VII Physical Specifications iius dac uuka auus sacr d Xa dx od dn du Cor ica aS LE ada EE EE aeaaea FEAR RA dE E EE CE cans 1 Physical E SIONS e ut 1 Pin Location S cee Pe cc a pce On Rebus aE uM Dun Ned iB uc e ut 2 J mper Settings Memes 2 Product Sp cific tio MSsir i CnnidutRa ad ExEM Had CERO v xd URINE adanadan anaosha NEN RU du CE EM Vd 3 System REN ee ce etm 3 System Power RequireMentS cccccccccccccesseeeeeccceeccececeeeeeceeeeceeneseneeeeeeetsneesessseeserses 3 e cachet tec Sete dace 4 Projected Operational Life Span uocatus uan deeg erageet gie gef 4 Product Capacity SPS CHICANOINS aisi aad bx ERR IRA OUR APER DUREE U EE QU Add ax RR at ON pa ur ene 5 Environmental Specifications EI 5 Electrical SpecMICallOn iuiiiiaaicszccankvbkca si mE abu d vM RU eENE GE be IS FASES ONE RP ME MS raean nanana Nanananana 6 Ee ll 6 Signal PS SC OOS scsi coats E ai ieie 7 Absolute Maximum RAN e CN 11 DC CH eanAC IONS CS L
10. Table 51 Write Buffer E8h Register D Dg Ds D4 D3 Do D D Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head X X X Drive X Command E8h X X OX xx SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 65 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Write DMA CAh The Write DMA command allows the host to write data using the DMA transfer protocol Note This function does not apply to SiliconDrive EPs that have DMA disabled Table 52 Write DMA CAh Register D Dc Ds D3 D3 Do D Do Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16 Drive Head X LBA X Drive Head Number LBA27 24 Command CAh SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 66 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Write Multiple C5h The Write Multiple command operates in the same manner
11. 3Ch The Write Verify command verifies each sector immediately after it is written This command performs identically to the Write Sector s command with the added feature of verifying each sector written Table 63 Write Verify 3Ch Register D Dg Ds D4 D3 Dg Dy Do Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16 Drive Head X LBA X Drive Head Number LBA27 24 Command 3Ch SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 76 FEBRUARY 2 2009 SALES AND SUPPORT SSD Dxxx I 4210 DATA SHEET SALES AND SUPPORT To order or obtain information on pricing and delivery contact your SiliconSystems Sales Representative PART NUMBERING NOMENCLATURE The following table defines the SiliconDrive EP 2 5 PATA Drive part numbering scheme Table 64 Part Numbering Nomenclature SSD D YYY I T 4210 Part number suffix contact your SiliconSystems Sales Representative Temperature Range Blank Commercial Industrial Interface Blank Parallel ATA PATA Capacity 16G 16GB to 64G 64GB Form Factor D 2 5 Drive SiliconSystems
12. If the tgp timing is not satisfied the host may receive zero one or two more data words from the device SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc 4210D 03DSR All unauthorized use and or reproduction is prohibited PAGE 18 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET host STOP host device DD 15 0 DMARQ w device tuu gt DMACK N H tack tu tu 4 tu tack MK tack DAO DA1 DA2 CSO CS1 HDMARDY host tss bone DSTROBE Figure 9 Device Terminating a UDMA Data In Burst Note The definitions for the DIOW STOP DIOR HDMARDY HSTROBE and IORDY DDMARDY DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated 4210D 03DSR SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited PAGE 19 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET DMARQ device DMACK host STOP host HDMARDY host t tu DSTROBE7 ci wW ss device M tack DAO DA1 DA2 CSO CS1 Figure 10 Host Terminating a UDMA Data In Burst Note
13. Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 ATA Command SCT series crassa casos Russ ius eg 40 Check Power Mode 98h Eh 42 Executive Drive Diagnostic 90Oh sessseeseeeeeeeeee 43 Format Irack 50h rc reece 44 Identify Drive ECH T Eaa 45 Identify Drive Drive Attribute Data 46 e e 97m EE 49 Idle Immediate 95h CN EE 50 Initialize Drive Parameters 91h siwsininsnauiganansendnsnaxtcanssonaatad ck ni sida idu 51 Recalibrate TXR EE 52 aii EE M eege EE 53 Read DB LP M 54 Read Multiple e m m 55 Read Geclof 20h 2 IB EE 56 Read Long Sector s 22h 23h iuiee entere reet ntn tadit dent nudius 57 Read Verify Sector s 40h Ah 58 Desk JL AE eit n p bata va E ae eee 59 Set Features d E H 60 Set Features Attributes EEN 60 Set Multiple Mode CGM ca sass certains nnne nnn neee 61 Set Sleep Mode 99h E6h iet ornan diee Ee iia aiie AEE EES 62 Standby NN E 63 Standby Immediate 94h EOh nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnn 64 Write Bu
14. EFh Register D7 Dg Ds D4 D3 Do D Do Feature Feature Sector Count X Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive X Command EFh Table 46 Set Features Attributes Feature Operation 01h Enable 8 bit data transfer 66h Disable reverting to power on defaults 81h Disable 8 bit data transfer BBh 4 bytes of data apply on Read Write Long commands CCh Enable revert to power on defaults On power up or following a hardware reset the device is set to the default mode 81h SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc 4210D 03DSR All unauthorized use and or reproduction is prohibited PAGE 60 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Set Multiple Mode C6h The Set Multiple Mode command allows the host to access the drive via Read Multiple and Write Multiple ATA commands Additionally the command sets the block count i e the number of sectors within the block for the Read Write Multiple command The sector count per block is set in the Sector Count register Table 47 Set Multiple Mode C6h Register D Dg Ds D4 Ds Do D Do Feature X Sector Count Sector Count Sector Number X Cylinder Low X Cylinder High X Drive Head X
15. the data bus The rising edge of IORD latches data at the host The host does not act on the data until it is latched DDMARDY When UDMA mode DMA write is active in UDMA write all modes this signal is asserted by the protocol device during a data burst to indicate that active the device is ready to receive UDMA data out bursts The device may negate DDMARDY to pause a UDMA transfer DSTROBE When UDMA mode DMA read is active in UDMA read all modes this signal is the data in strobe protocol generated by the device Both the rising active and falling edge of DSTROBE cause data to be latched by the host The device may stop generating DSTROBE edges to pause a UDMA data in burst JIOWR 23 Device I O Write This is the write strobe True IDE signal from the host The rising edge of mode IOWR Z latches data from the data bit signals The device does not act on the data until it is latched HDMARDY When UDMA mode DMA read is active in UDMA read all modes this signal is asserted by the protocol host to indicate that the host is ready to active receive UDMA data in bursts The host may negate HDMARDY to pause a UDMA transfer 4210D 03DSR SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited PAGE 10 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET Table
16. with the exception that it transfers requested data sectors and ECC data The long instruction ECC byte transfer for Long commands is a byte transfer at a fixed length of 4 bytes Table 42 Read Long Sector s 22h 23h Register D Dg Ds Dg D3 Dg Dy Do Feature X Sector Count X Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16 Drive Head 1 LBA 1 Drive Head Number LBA27 24 Command 22h or 23h SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 57 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Read Verify Sector s 40h 41h The Read Verify Sector s command operates similarly to the Read Sector s command with the exception that is does not set the DRQ bit and does not transfer data to the host When the requested sectors are verified the onboard controller clears the BSY bit and issues an interrupt Table 43 Read Verify Sector s 40h 41h Register D De D5 Da D3 D2 Dy Do Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder Hig
17. 1 Set Sleep Mode 99h E6h D 1 Standby 96h E2h D 1 Standby Immediate 94h EOh l D 1 Translate Sector 87h Y Y Y Y Y 1 Wear Level F5h Y 2 Write Buffer E8h D 1 Write DMA CAh Y Y Y Y Y 2 Write Long Sector 32h 33h Y Y Y Y 3 Write Multiple C5h Y Y Y Y Y 3 Write Multiple w o CDh Y Y Y Y Y Erase 2 Write Sector s 30h 31h Y Y Y Y Y 2 Write Sector s wo 38h Y Y Y Y Y Erase 3 Write Verify 3Ch Y Y Y Y Y This function does not apply to SiliconDrive EPs that have DMA disabled Notes e CY Cylinder SC Sector Count DH Drive Head SN Sector Number FR Feature LBA LBA bit of the Drive Head register D denotes that only the drive bit is used SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc 4210D 03DSR All unauthorized use and or reproduction is prohibited PAGE 41 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Check Power Mode 98h E5h The Check Power Mode command verifies the device s current power mode When the device is configured for standby mode or is entering or exiting standby the BSY bit is set the Sector Count register set to 00h and the BSY bit is cleared In idle mode BSY is set and the Sector Count register is set to FFh The BSY bit is then cleared and an interrupt is issued Table 29 Check Power M
18. 1 ns register 8 bit toi IORD IOWR Recovery 70 25 25 20 1 ns Time minimum t3 IOWR Data Setup 60 45 30 30 20 20 15 ns minimum t4 IOWR Data Hold 30 20 15 10 10 5 5 ns minimum ts IORD Data Setup 50 35 20 20 20 15 10 ns minimum te IORD Data Hold 5 5 5 5 5 5 5 ns minimum tez IORD Data Tristate 30 30 30 30 30 20 20 2 ns maximum t Address Valid to IOCS16 90 50 40 N A N A N A N A 4 ns Assertion maximum tg Address Valid to lOCS16 60 45 30 N A N A N A N A 4 ns Released maximum ty IORD IOWR to 20 15 10 10 10 10 10 ns Address Valid Hold trp Read Data Valid to 0 0 0 0 0 0 0 ns IORDY Active minimum if IORDY is initially low after t4 ta IORDY Setup Time 35 35 35 35 35 N A N A 3 ns tg IORDY Pulse Width 1250 1250 1250 1250 1250 N A5 N A ns maximum tc IORDY Assertion to 5 5 5 5 5 N A N A ns Release maximum Notes 1 The symbol tg is the minimum total cycle time to is the minimum command active time and t is the minimum command recovery time or command inactive time The actual cycle time equals the sum of the actual command active time and the actual command inactive time The three timing requirements of to t2 and La must be met The minimum total cycle time requirement is greater than the sum of t and t This means a host implementation can lengthen either or both t or tz to ensure that to is equal to or greater than the value reported in the
19. 8 Signal Descriptions Continued Signal Name Pin s Type Description HDSTROBE When UDMA mode DMA write is active in UDMA write all modes this signal is the data out strobe protocol generated by the host Both the rising and active falling edge of HSTROBE cause data to be latched by the device The host may stop generating HSTROBE edges to pause an UDMA data out burst KEY 20 Key Reserved for the Connector Key STOP While the UDMA mode protocol is active in UDMA all modes the assertion of this signal protocol causes the termination of the UDMA data active burst PDIAG 34 UO Pass Diagnostic This open drain signal is asserted by the slave to indicate to the master that it has passed its diagnostics RESET 1 Device Reset An active low signal When active this signal sets all internal registers to their default state This signal is held asserted until at least 25us after power has been stabilized during the device power on Vcc 41 42 Device Power Supply The device power 3 3V 5V signal ABSOLUTE MAXIMUM RATINGS Table 9 Absolute Maximum Ratings Symbol Parameter Minimum Maximum Units Ts Storage Temperature 55 125 C TA Operating Temperature 40 85 aC Voc Vcc with Respect to GND 0 5 Voc 05 V VIN Input Voltage 0 3 Veco 0 3 V Vout Output Voltage 6 0 V 4210D 03DSR SiLICONSYsTEMS PROPRIETARY This document and the information contained within it
20. Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 32 FEBRUARY 2 2009 ATA REGISTERS SSD Dxxx I 4210 DATA SHEET CYLINDER HIGH REGISTER The Cylinder High register is set by the host to specify the cylinder number high byte Following an ATA command the content of the register is set internally by the device identifying the cylinder number high byte In LBA mode the 8 bit register maintains the contents of the Logical Block number address bits A23 A16 Table 20 Cylinder High Register Operation Dz De Ds D3 D3 Do Di Do Read Write Cylinder Number Low Byte CHS Addressing Logical Block Number bits A23 A16 LBA Addressing Default Value 0 0 0 0 0 0 0 0 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 33 FEBRUARY 2 2009 ATA REGISTERS SSD Dxxx I 4210 DATA SHEET DRIVE HEAD REGISTER The Drive Head register is used by the host and the device to select the type of addressing CHS or LBA the drive letter and either bits 3 0 of the head number in CHS mode or logical block number bits 27 24 in LBA mode Table 21 Drive Head Register Operation D De Ds D4 D3 Do D Do Read Write 1 LBA 1 DRV HS3 HS2 HS1 HSO LBA27 LBA26 LBA25 LBA24 Default 1 0 1 0 0 0 0 0 Value
21. RELIABILITY Table 3 Reliability MTBF 25 C 4 000 000 hours Bit Error Rate 1 non recoverable error in 1014 bits read PROJECTED OPERATIONAL LIFE SPAN Table 4 Operational Life Span SiliconDrive Part Capacity Service Life GB Written per Day SSD D64G 4210 64GB 17 9 Years 978 5GB SSD D32G 4210 32GB 9 0 Years 978 5GB SSD D16G 4210 16GB 4 5 Years 978 5GB There are unlimited read cycles Service life is determined using SiliconSystems LifeEst calculation at 100 duty cycle with 25 write cycles LifeEst is a comprehensive measurement that considers numerous factors to determine the projected life span of a SiliconDrive A white paper that describes the benefits of LifeEst and how to calculate it can be found at http www siliconsystems com resources Documents Whitepaper SiliconSystems_NAND_Evolution pdf The actual life of a SiliconDrive is dependant on the customer usage model SISMART is a patented technology of SiliconSystems that enables host systems to monitor actual usage of a SiliconDrive in real time SISMART measures and reports the remaining life of a SiliconDrive For more information on SiSMART refer to the Eliminating Unscheduled Downtime by Forecasting Useable Life white paper at http www siliconsystems com technology pdfs SiliconDrive_SiSMART pdf SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems
22. STROBE edge to ns negation of DMARQ or assertion of STOP when the sender terminates a burst Notes 1 Timing parameters are measured at the connector of the sender or receiver to which the parameter applies Both STROBE and DMARDY timing measurements are taken at the sender s connector Example For example the sender stops generating STROBE edges tgprs after the negation of DMARDY 2 All timing measurement switching points low to high and high to low are taken at 1 5V 3 The symbols ty Iw and tj indicate sender to recipient or recipient to sender interlocks e either the sender or recipient is waiting for the other to respond with a signal before proceeding The symbol ty is an unlimited interlock that has no maximum time value ty is a limited time out that has a defined minimum and tj is a limited time out that has a defined maximum 4 The test load for tpys and tpy are a lumped capacitor load with no cable or receivers Timing for tpys and ru are met for all capacitive loads from 15pF to 40pF where all signals have the same capacitive load value 5 The symbol tziogpy may be greater than tgyy since the device has a pull up on IORDY giving it a known state when released SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 26 FEB
23. The definitions for the DIOW STOP DIOR HDMARDY HSTROBE and IORDY DDMARDY DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 20 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET DMARQ 5 8 device bi DMAE O O O O O O O O OUOU OA host STOP host DDMARDY device HSTROBE host DD 15 0 host tack DAO DA1 DA2 CSO CS1 Figure 11 Initiating a UDMA Data Out Burst Note The definitions for the DIOW STOP IORDY DDMARDY DSTROBE and DIOR HDMARDY HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted HSTROBE at host g ele De NY ele wg SY d KOK EE at host HSTROBE at device JOCO COX EE DD 15 0 at device Figure 12 Sustained UDMA Data Out Burst Note DD 15 0 and HSTROBE signals are shown at both the device and the host to emphasize that the cable settling time as well as cable propagation delay does not allow the data signals to be considered stable at the device until some time after they are driven by the host SILICONSYSTEMS PROPRIETARY This document and the information contained within it is
24. acknowledgement Other listed names and brands are trademarks or registered trademarks of their respective owners Copyright 2009 by SiliconSystems Inc All rights reserved No part of this publication may be reproduced without the prior written consent of SiliconSystems SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 79 FEBRUARY 2 2009
25. an I O Read cycle to the device The host does not initiate an I O Read cycle while DMARQ is asserted by the device In True IDE mode DMARQ is not driven when the device is not selected in the Drive Head register While a DMA operation is in progress CS0 CE1 and CS1 CE2 are held negated and the width of the transfers is 16 bits If there is no hardware support for True IDE DMA mode in the host this output signal is not used and should not be connected at the host In this case the BIOS must report that DMA mode is not supported by the host so that device drivers do not attempt the DMA mode operation GND 2 19 22 Ground The device ground signal 24 26 30 40 43 INTRQ 31 O Interrupt Request This signal is an active high interrupt request to the host SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 9 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET Table 8 Signal Descriptions Continued Signal Name Pin s Type Description IORDY 27 UO Channel Ready The signal is negated True IDE to extend the host transfer cycle of any host mode register access IORD 25 Device I O Read This is the read strobe True IDE signal from the host The falling edge of mode IORD enables data from the device onto
26. as the Write Sector command When issued the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors The DRQ bit is set at the beginning of a block transfer Table 53 Write Multiple C5h Register D Dg Ds Dg D3 Dg Dy Do Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16 Drive Head X LBA X Drive Head Number LBA27 24 Command C5h SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 67 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Write Sector s 30h 31h The Write Sector s command writes from 1 to 256 sectors as specified in the Sector Count register A sector count of 0 requests 256 sectors When issued the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors The DRQ bit is set at the beginning of a block transfer Table 54 Write Sector s 30h 31h Register D De Ds D4 D3 D2 Dy Do Feature X Sector Count Sector Count Sector Number Sector Number L
27. is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited PAGE 11 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET DC CHARACTERISTICS Table 10 DC Characteristics 5V 10 Symbol Parameter Units Minimum Maximum li Input Leakage 1 Current 10 uA lio Output Leakage 1 Current 10 uA ICCcR Icc Read Current 100 mA lccw Icc Write Current 200 mA lccs lcc Standby Current 15 mA SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 12 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET AC CHARACTERISTICS True IDE PIO Mode Read Write Access Timing to ADDR valid A02 A01 A00 CS0 CS1 See note 1 IORD IOWR Write Data D15 D00 4 Ft ey eset See note 2 Read Data D15 D00 7 4 See note 2 IOCS16 Seenote3 i IORDY See note 4a IORDY See note 4b IORDY See note 4c Figure 4 True IDE PIO Mode Read Write Access Timing Diagram Notes 1 The device address consists of CSO CS1 and A 02 00 2 The data consists of D 15 00 16 bit or D 07 00 8 bit 3 IOCS16 is shown for PIO
28. modes 0 1 and 2 For other modes this signal is ignored 4 The negation of IORDY by the device is used to extend the PIO cycle The determination of whether the cycle is to be extended is made by the host after t4 from the assertion of IORD or IOWR The assertion and negation of IORDY is described in the following three cases a b The device never negates IORDY no wait is generated The device starts to drive IORDY low before ta but causes IORDY to be asserted before t4 no wait generated The device drives IORDY low before t4 wait generated The cycle completes after IORDY is reasserted For cycles where a wait is generated and IORD is asserted the device places read data on D15 DOO for tgp before causing IORDY to be asserted SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc 4210D 03DSR All unauthorized use and or reproduction is prohibited PAGE 13 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET Table 11 True IDE PIO Mode Read Write Access Timing Symbol Item Moden Mode1 Mode2 Mode3 Mode4 Mode5 Mode6 Note Units to Cycle Time minimum 600 383 240 180 120 100 80 1 ns t Address Valid to 70 50 30 30 25 15 10 ns IORD IOWR Setup minimum to IORD IOWR minimum 165 125 100 80 70 65 55 1 ns to IORD IOWR minimum 290 290 290 80 70 65 55
29. of the register describe the Logical Block Number bits A 7 0 Following an ATA command the device loads the register with the LBA block number resulting from the last ATA command Table 18 Sector Number Register Operation D7 De Ds D4 D3 Do D4 Do Read Write Sector Number CHS Addressing Logical Block Number bits A07 A00 LBA Addressing Default Value 0 0 0 0 0 0 0 1 SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 31 FEBRUARY 2 2009 ATA REGISTERS SSD Dxxx I 4210 DATA SHEET CYLINDER LOW REGISTER The Cylinder Low register is set by the host to specify the cylinder number low byte Following an ATA command the content of the register is written by the device identifying the cylinder number low byte In LBA mode the 8 bit register maintains the contents of the Logical Block number address bits A15 A08 Table 19 Cylinder Low Register Operation D De Ds D D3 D2 Di Do Read Write Cylinder Number Low Byte CHS Addressing Logical Block Number bits A15 A08 LBA Addressing Default Value 0 0 0 0 0 0 0 0 SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems
30. 70 20 70 20 70 20 55 20 55 Envelope time from DMACK to STOP and HDMARDY during data in burst initiation and from DMACK to STOP during data out burst initiation ns tsR 50 30 20 NA NA STROBE to DMARDY time if DMARDY is negated before this long after STROBE edge the recipient receives no more than one additional data word ns tRFs 75 70 60 60 60 Ready to final STROBE time no STROBE edges are sent this long after negation of DMARDY ns trp 160 125 100 100 100 Minimum time to assert STOP or negate DMARQ ns Hoppe 20 20 20 20 20 Maximum time before releasing IORDY ns tzioRDY Minimum time before driving STROBE see note 5 ns tack 20 20 20 20 20 Setup and hold times for DMACK before assertion or negation ns 4210D 03DSR SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited PAGE 25 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET Table 13 UDMA Data Burst Timing Requirements Continued Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Comment see Notes 1 and 2 Units Symbol Min Max Min Max Min Max Min Max Min Max tss 50 50 50 50 50 Time from
31. ARQ 40 40 35 35 35 ns Delay maximum tu CS 1 0 Valid to 50 30 25 10 5 ns IORD IOWR tn CS 1 0 Hold 15 10 10 10 10 ns tz DMACK 20 25 25 25 25 ns Note 1 The symbol tg is the minimum total cycle time and tp is the minimum command active time while tka and tkw are the minimum command recovery times or command inactive times for input and output cycles respectively The actual cycle time equals the sum of the actual command active time and the actual command inactive time The three timing requirements of to tp tkr and tkw must be met The minimum total cycle time requirement is greater than the sum of tp and txr or tkw for input and output cycles respectively This means a host implementation can lengthen either or both of tp and either of tkp and tkw as needed to ensure that to is ern to or greater than the value reported in the device s identify device ata SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc 4210D 03DSR All unauthorized use and or reproduction is prohibited PAGE 16 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET Ultra DMA Data Burst Timing Requirements The following figures and table describe the requirements for the Ultra DMA UDMA data burst timing DMARQ device tu 3 DMACK A host t gt tack tenv gt t S
32. All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 55 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Read Sector 20h 21h The Read Sector command allows the host to read sectors 1 to 256 as specified in the Sector Count register If the sector count is set to Oh all 256 sectors of data are made available When the command code is issued and the first sector of data has been transferred to the buffer the DRQ bit is set The Read Sector command is terminated by writing the cylinder head and sector number of the last sector read in the task file On error the read operation is aborted in the errant sector Table 41 Read Sector 20h 21h Register D Dc Ds D D3 Do D Do Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16 Drive Head 1 LBA 1 Drive Head Number LBA27 24 Command 20h or 21h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 56 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Read Long Sector s 22h 23h The Read Long Sector s command operates similarly to the Read Sector s command
33. BA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16 Drive Head X LBA X Drive Head Number LBA27 24 Command 30h or 31h SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 68 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Write Long Sector s 32h 33h The Write Long Sector s command operates in the same manner as the Write Sector command when issued the device sets the BSY bit within 400ns and generates an interrupt at the completion of a transferred block of sectors The DRQ bit is set at the beginning of a block transfer Table 55 Write Long Sector s 32h 33h Register D Dg D5 D4 Dg D2 Dy Do Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16 Drive Head X LBA X Drive Head Number LBA27 24 Command 32h or 33h SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 69 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET
34. Cable Select This internally pulled up signal is used to configure this device as a master or a slave when the jumper configuration is in CSEL mode When this pin is Grounded by the host this device is configured as a master Open this device is configured as a slave D15 DO 18 16 I O Data Inputs Outputs This is the 8 bit or 14 12 16 bit bidirectional interface between the 10 8 6 host and device The lower eight bits are 4 3 5 7 used for 8 bit register transfers 9 11 13 15 17 DMACK 29 DMA Acknowledge This signal is used by the host in response to DMARQ to initiate DMA transfers The DMARQ DMACK handshake is used to provide flow control during the transfer When DMACK is asserted CS0 and CS1 are not asserted and transfers are 16 bits wide DASP 39 UO Disk Active Slave Present This open drain output signal is asserted low any time the drive is active In a master slave configuration this signal is used by the slave to inform the master that a slave is present SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 7 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET Table 8 Signal Descriptions Continued Signal Name Pin s Type Description DMARQ 21 O DMA Request This signal
35. Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16 Drive Head X LBA X Drive Head Number LBA27 24 Command CDh SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 74 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Write Sector s w o Erase 38h The Write Sector s w o Erase command functions similar to the Write Sector command with the exception that the implied pre erase i e Erase Sector s command is not issued prior to writing the sectors Table 62 Write Sector s w o Erase 38h Register D Dg D5 D D3 Dg Dy Do Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16 Drive Head X LBA X Drive Head Number LBA27 24 Command 38h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 75 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Write Verify
36. Format Track 50h Register D Dc Ds D3 D3 Do D Do Feature X Sector Count Sector Count Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16 Drive Head 1 LBA 1 Drive Head Number LBA27 24 Command 50h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 44 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Identify Drive ECh Issued by the host the Identify Drive command provides 256 bytes of drive attribute data i e sector size count and so on The identify drive data structure is detailed in the following table Table 32 Identify Drive ECh Register D De D5 D D3 Do D4 Do Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head X X X Drive X Command ECh Xp X OX xx SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 45 FEBRUARY 2 2009 ATA COMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Identify Drive Drive Attribute Da
37. GS The following diagram defines the SiliconDrive EP 2 5 PATA Drive jumper settings gt Cable Select C Master Slave Oo No Jumper Jumper A B Jumper D B D B Figure 3 Jumper Settings c Bl o Ni gt SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 2 FEBRUARY 2 2009 PRODUCT SPECIFICATIONS SSD Dxxx I 4210 DATA SHEET PRODUCT SPECIFICATIONS Note All SiliconDrive EP 2 5 PATA Drive values quoted are typical at 25 C and nominal supply voltage SYSTEM PERFORMANCE Table 1 System Performance Reset to Ready Startup Time Typical Maximum 200ms 400ms Read Transfer Rate Typical 50MBps Write Transfer Rate Typical 50MBps Burst Transfer Rate 66MBps Controller Overhead Command to DRQ 2ms maximum SYSTEM POWER REQUIREMENTS Table 2 System Power Requirements DC Input Voltage 5 0 10 Sleep Standby Current 100mA Read Peak 200mA Write Peak 300mA SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 3 FEBRUARY 2 2009 PRODUCT SPECIFICATIONS SSD Dxxx I 4210 DATA SHEET
38. Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 4 FEBRUARY 2 2009 PRODUCT SPECIFICATIONS SSD Dxxx I 4210 DATA SHEET PRODUCT CAPACITY SPECIFICATIONS Table 5 Product Capacity Specifications Product Capacity Number of Numberof Number Huren 3 Sectors Capacity Bytes Sectors Cylinders of Heads T rack 16GB 16 391 208 960 32 014 080 16 383 16 63 32GB 32 782 417 920 64 028 160 16 383 16 63 64GB 65 564 835 840 128 056 320 16 383 16 63 All IDE drives 8GB and larger use 16383 cylinders 16 heads and 63 sectors track due to interface restrictions ENVIRONMENTAL SPECIFICATIONS Table 6 Environmental Specifications Temperature 0 C to 70 C Commercial 40 C to 85 C Industrial Humidity 8 to 95 non condensing Vibration 16 3gRMS MIL STD 810F Method 514 5 Procedure Category 24 Shock 1000G Half sine 0 5ms Duration 50g Pk MIL STD 810F Method 516 5 Procedure Altitude 80 000ft MIL STD 810F Method 500 4 Procedure II SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 5 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET ELECTRICAL SPECIFICATION PIN ASSIGNMENTS The following table describes the SiliconDrive EP 2 5 PATA Drive 44 pin IDE connector si
39. ROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 72 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Wear Level F5h The Wear Level command is supported as an NOP command for the purposes of backward compatibility with the ANSI AT attachment standard This command sets the Sector Count register to OxOOh Table 60 Wear Level F5h Register D De D5 D D3 Do D Do Feature X Sector Count Completion Status Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive Flag Command F5h SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 73 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Write Multiple w o Erase CDh The Write Multiple w o Erase command functions identically to the Write Multiple command with the exception that the implied pre erase i e Erase Sector s command is not issued prior to writing the sectors Table 61 Write Multiple w o Erase CDh Register D Dg Ds D4 D3 Dg Dy Do
40. RUARY 2 2009 ATA AND TRUE IDE REGISTER DECODING SSD Dxxx I 4210 DATA SHEET ATA AND TRUE IDE REGISTER DECODING SiliconDrive EP can be configured as either a a memory mapped or an an I O devices As noted earlier communication to and from the drive is accomplished using the ATA Command Block TASK FILE REGISTER SPECIFICATION The Task File registers are used for reading and writing the storage data in the SiliconDrive EP The decoded addresses are as shown in the following table Table 14 Task File Register Specification CSO CS1 DAO2 DAO1 DAOO DIOR L DIOW L 0 1 0 0 0 Data Data 0 1 0 0 1 Error Feature 0 1 0 1 0 Sector Count Sector Count 0 1 0 1 1 Sector Number Sector Number 0 1 1 0 0 Cylinder Low Cylinder Low 0 1 1 0 1 Cylinder High Cylinder High 0 1 1 1 0 Drive Head Drive Head 0 1 1 1 1 Status Command 0 0 X X X Invalid Invalid 1 1 X X X High Z Not Used 1 0 0 X X High Z Not Used 1 0 1 0 X High Z Not Used 1 0 1 1 0 Alternate Status Device Control 1 0 1 1 1 Device Address Not Used SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 27 FEBRUARY 2 2009 ATA REGISTERS SSD Dxxx I 4210 DATA SHEET ATA REGISTERS DATA REGISTER The Data register is a 16 bit register used to transfer data blocks between th
41. SILICON SYSTEMS The Future of Storage Today DATA SHEET SILICONDRIVE EP 2 5 PATA DRIVE SSD Dxxx I 4210 OVERVIEW The SiliconDrive EP 2 5 PATA Drive is an optimal time to market replacement for hard drives and flash cards or in host systems that require low power and scalable storage solutions SiliconDrive EP technology is engineered exclusively for the high performance high reliability and multi year product lifecycle requirements of the Enterprise System OEM market Typical end market applications include broadband data and voice networks military systems flight system avionics medical equipment industrial control systems video surveillance storage networking VoIP wireless infrastructure and interactive kiosks Every SiliconDrive EP is integrated with SiliconSystems patented PowerArmor and patent pending SiSMART to virtually eliminate storage systems failures PowerArmor prevents data corruption and loss from power disturbances by integrating patented technology into every SiliconDrive EP SISMART acts as an early warning system to eliminate unscheduled downtime by constantly monitoring and reporting the exact amount of remaining storage system useful life Numerous SiliconSystems patented and patent pending application specific technology can be integrated into SiliconDrive EP to safeguard application data and software IP Application notes detailing these performance enhancing options a
42. SiliconDrive PART NUMBERS The following table lists the SiliconDrive EP s part numbers Table 65 Part Numbers Part Number Capacity SSD D64G l 4210 64GB SSD D32G l 4210 32GB SSD D16G I 4210 16GB SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 77 FEBRUARY 2 2009 PART NUMBERING SSD Dxxx I 4210 DATA SHEET ROHS 6 or 6 PRODUCT LABELING PB FREE IDENTIFICATION LABEL The Pb free identification label indicates that the enclosed components devices and or assemblies do not contain any lead i e they are lead free as defined in RoHS directive 2002 95 ED The above symbol is on all ROHS 6 of 6 compliant product labels as seen in Figure 16 SAMPLE LABEL Standard Back Label with Front Label Lot Code Information UT e SiliconSystems Inc SiliconDrive EP er 64GB Lot Code MANI 0025 4210 e Mfg Date 07 09 Pat 6 8565 56 Figure 16 Sample Label SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 78 FEBRUARY 2 2009 RELATED DOCUMENTATION SSD Dxxx I 4210 DATA SHEET RELATED DOCUMENTATION For more information visi
43. TOP et E host tes gt t t HDMARDY ENY host opp DSTROBE mmm device DD 15 0 lack DAO DA1 DA2 CSO0 CS1 Figure 6 Initiating a UDMA Data In Burst Note The definitions for the DIOW STOP DIOR HDMARDY HSTROBE and IORDY DDMARDY DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 17 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET tacyc DSTROBE at device DD 15 0 at device DSTROBE at host DD 15 0 WW SS SY ee URS at ho st KXKKXKX X XXX KKK KK XXX Figure 7 Sustained UDMA Data In Burst Note DD 15 0 and DSTROBE signals are shown at both the host and the device to emphasize that the cable settling time as well as cable propagation delay does not allow the data signals to be considered stable at the host until some time after they are driven by the device DMARQ device DMACK host STOP J I se TS host HDMARDY host DSTROBE device DD 15 0 device Figure 8 Host Pausing a UDMA Data In Burst Notes 1 The host may assert STOP to request termination of the UDMA burst no sooner than tgp after HDMARDY is negated
44. Table 13 UDMA Data Burst Timing Requirements eeeeeeeeeeeeeesssssrrerrrrrrerrrrrrenns 24 Table 14 Task File Register Specification eee secans 27 Table 15 zoe dini E 28 RR Fe AUS FR SNS e EE T m om o mmm 29 Table 17 Sector Count Register n pnt noreobU cubi be b bi RE RxE Enn ERR ERES 30 Table 18 Sector Number Register 2 s sseeeeeeceeceeeeeceeeceecceeeceeeeesenseneeeeneeseesseseees 31 Table 19 Cylinder Low e E 32 Table 20 Cylinder High Register oret estu uu epu SE mu bEx Bembo n bU EP u nuce ance RE dud pue 33 Table 21 Drive Head Register seen nirunc ucc eee neteedt erenneren 34 Table 22 Status e EE 35 Table 23 Command Reglsler eerie eame deefe Semen bd te pop se a e d MEM ASA MEME EUUE 36 Table 24 Alternate Status Register eee eeeeeeeeeececee eee n ennt natn e Renee 37 Table 25 Device Control Register cesses cese ne nee nn nnne an ne nar n Rue 38 Table 26 Device Address Register eee eeeceisiiseeeenn nn 39 Table 27 ATA Command Block and Set Description nannnnnnnnnnnnneneeeeeenrennnnnnnnnnennneee 40 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE VII FEBRUARY 2 2009 LisT OF TABLES SSD Dxxx I 4210 DATA SHEET
45. X X Drive X Command C6h SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 61 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Set Sleep Mode 99h E6h The Set Sleep Mode command allows the host to set the device in sleep mode When the onboard controller transitions to sleep mode it clears the BSY bit and issues an interrupt The device interface then becomes inactive Sleep mode can be exited by issuing either a hardware or software reset Table 48 Set Sleep Mode 99h E6h Register D De Ds D D3 Do D4 Do Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head X X X Drive X Command 99h or E6h Xp X OX xx SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 62 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Standby 96h E2h When the Standby command is issued by the host it transitions the device into standby mode If the Sector Count register is set to a value other than Oh the Auto Powerdown function is enabled and the device r
46. authorized use and or reproduction is prohibited 4210D 03DSR PAGE 38 FEBRUARY 2 2009 ATA REGISTERS SSD Dxxx I 4210 DATA SHEET DEVICE ADDRESS REGISTER The Device Address register is used to maintain compatibility with ATA disk drive interfaces Table 26 Device Address Register Operation D Dg Ds Dy D D Dy D Read Write nWTG nHS3 nHS2 nHS1 nHSO nDS1 nDSO Default Value 0 0 1 1 1 1 1 0 Bit s Description 7 Reserved bit 6 Write Gate nWTG Low when a write to the device is in process 5 2 nHS3 to nHSQ The negated binary address of the currently selected head 1 nDS1 Low when drive 1 is selected and active 0 nDSO Low when drive 0 is selected and active SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc 4210D 03DSR All unauthorized use and or reproduction is prohibited PAGE 39 FEBRUARY 2 2009 ATA COMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET ATA COMMAND BLOCK AND SET DESCRIPTION In accordance with the ANS ATA Specification the device implements seven registers that are used to transfer instructions to the device by the host These commands follow the ANSI standard ATA protocol A description of the ATA command block is provided in the following table Table 27 ATA Command Block and Set Description
47. confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 21 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET DMARQ device DMACK host STOP host DDMARDY N device HSTROBE host DD 15 0 host Figure 13 Device Pausing a UDMA Data Out Burst Notes 1 The device may negate DMARQ to request termination of the UDMA burst no sooner than trp after DDMARDY is negated 2 If the tsp timing is not satisfied the host may receive zero one or two more data words from the host SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 22 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET DMARQ device DMACK host STOP host tu tionpyz DDMARDY device HSTROBE e host X rere S tovs tov DD 15 0 host AE CRE E M tack DAO DA1 DA2 CSO CS1 Figure 14 Host Terminating a UDMA Data Out Burst Note The definitions for the DIOW STOP IORDY DDMARDY DSTROBE and DIOR HDMARDY HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated SILICONSYSTEMS PROPRIETARY This document and the information contained with
48. device s identify device data 2 This parameter specifies the time from the negation edge of IORD to the time that the data bus is no longer driven by the drive tristate SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 14 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET 3 4 5 The delay from the activation of IORD or IOWR until the state of IORDY is first sampled If IORDY is inactive then the host waits until IORDY is active before the PIO cycle can be completed If the drive is not driving IORDY negated at t4 after the activation of IORD or IOWR then t5 must be met and tgp is not applicable If the drive is driving IORDY negated at the time ty after the activation of IORD or IOWR then tgp must be met and ts is not applicable The symbols t and tg apply only to modes 0 1 and 2 For other modes this signal is not valid IORDY is not supported in this mode True IDE Multiword DMA Read Write Access Timing This function does not apply to SiliconDrive EPs that have DMA disabled CSO CS1 mg t N DMARQ See Note 1 t L DMACK See Note 2 IORD IOWR Read Data F 7 d D1S D00 7 MESES Write Data D15 D00 Figure 5 True IDE Multiword DMA Read Write Access Timing N
49. e s internal controller sets the BSY bit enters the Idle mode clears the BSY bit and generates an interrupt If the sector count is non zero it is interpreted as a timer count with each count being 5ms and the automatic power down mode is enabled If the sector count is zero the automatic power down mode is disabled Table 34 Idle 97h E3h Register D7 Dg Ds D4 Ds Do D Do Feature X Sector Count Timer Count 5ms increments Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive X Command 97h or E3h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 49 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Idle Immediate 95h Eth When issued by the host the device s internal controller sets the BSY bit enters Idle Mode clears the BSY bit and issues an interrupt The interrupt is issued whether or not the Idle mode is fully entered Table 35 Idle Immediate 95h Eth Register D7 De Ds D D3 Do D4 Do Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head X X X Drive X Command 95h or E1h Xp X OX xx SiLICONSYsTEMS PROPRIETARY This document and
50. e host and drive buffers The register may set to 8 bit mode by using the Set Features Command defined in Seek 7Xh on page 59 ERROR REGISTER The Error register contains the error status if any generated from the last executed ATA command The contents are qualified by the ERR bit being set in Status Register on page 35 Table 15 Error Register Operation D7 Dc D5 D D3 D2 Di Do Read BBK UNC MC IDNF MCR ABRT TKNOF AMNF Default 0 0 0 0 0 0 0 0 Value Bit s Description 7 Bad Block Detected BBK Set when a bad block is detected 6 Uncorrectable Data Error UNC Set when an uncorrectable error is encountered 5 Media Changed MC Set to 0 4 ID Not Found IDNF Set when the sector ID is not found 3 MCR Media Change Request Set to 0 2 Aborted Command ABRT Set when a command is aborted due to a drive error 1 Track 0 Not Found TKONF Set when the execute drive diagnostic command is executed 0 Address Mark Not Found AMNF Set in the case of a general error SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc 4210D 03DSR All unauthorized use and or reproduction is prohibited PAGE 28 FEBRUARY 2 2009 ATA REGISTERS SSD Dxxx I 4210 DATA SHEET FEATURE REGISTER The Feature register is command specific and used to enable and disable interface features Th
51. e offered in an industry standard 2 5 PATA Drive form factor See Part Numbering on page 77 for details regarding 2 5 PATA Drive capacities PHYSICAL DIMENSIONS This section provides diagrams that describe the physical dimensions for the 2 5 PATA Drive itn itu tt M3 TAP 8MM DEEP 8 PLACES Q a Lg H s T Tus P Leg P E P be 4 a Lr u N 3 TAP TO INTERSECT v M3 TAP TO INTERSEC DCH v CENTERED 8 PLACES Figure 1 Physical Dimensions Dimension Millimeters Tolerance mm Dimension Millimeters Tolerance mm A 100 00 0 25 L 69 85 0 25 B 90 60 0 125 M 2 00 40 125 C 73 03 0 125 N 9 40 0 10 D 34 93 40 125 P 6 00 40 125 E 14 00 40 125 Q 11 57 40 125 F 4 08 40 125 R 32 10 40 125 G 61 70 0 125 S 14 93 0 125 H 4 68 0 125 T 11 00 0 125 64 42 40 125 U 4 65 40 125 J 10 14 0 51 V 4 00 40 125 K 3 99 0 43 W 6 15 0 125 4210D 03DSR SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited PAGE 1 FEBRUARY 2 2009 PHYSICAL SPECIFICATIONS SSD Dxxx I 4210 DATA SHEET PIN LOCATIONS The following diagram identifies the pin locations of the 2 5 PATA Drive 43 19 1 CA 44 KEY 2 DB Figure 2 Pin Locations JUMPER SETTIN
52. ed use and or reproduction is prohibited 4210D 03DSR PAGE 36 FEBRUARY 2 2009 ATA REGISTERS SSD Dxxx I 4210 DATA SHEET ALTERNATE STATUS REGISTER The Alternate Status register is a read only register indicating the status of the device following the previous ATA command See Status Register on page 35 for specific details Table 24 Alternate Status Register Operation D De Ds D D3 Do D Do Read Write BSY DRDY DWF DSC DRQ CORR IDX ERR Default Value 0 0 0 0 0 0 0 0 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 37 FEBRUARY 2 2009 ATA REGISTERS SSD Dxxx I 4210 DATA SHEET DEVICE CONTROL REGISTER The Device Control register is used to control the interrupt request and issue ATA software resets Table 25 Device Control Register Operation D Dg Ds D4 D3 D D Do Write 1 SRST nIEN 0 Bits Description 7 4 Reserved bits 3 Always set to 1 2 Software Reset SRST When set resets the ATA software 1 Interrupt Enable nIEN When set device interrupts are disabled There is no function in the memory mapped mode 0 Always set to 0 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All un
53. eturns to Idle mode Table 49 Standby 96h E2h Register D7 Dc D5 D D3 Do D4 Do Feature X Sector Count Timer Count 5ms x Timer Count Sector Number X Cylinder Low X Cylinder High X Drive Head X X X Drive X Command 96h or E2h SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 63 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Standby Immediate 94h EOh When the Standby Immediate command is issued by the host it transitions the device into standby mode Table 50 Standby Immediate 94h EOh Register D Dg Ds D4 D3 Do D D Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head X X X Drive X Command 94h or EOh Xp X OX xx SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 64 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Write Buffer E8h The Write Buffer command allows the host to rewrite the contents of the 512 byte data buffer with the wanted data
54. ffer EBD E 65 Write DMA CT ipt E 66 Write Multiple E 67 Write Sector s 30h 31h sass seteec castes eee ceeteereed eet cee aeereeeatlcndane 68 Write Long Sector s 32h 33h x cscscicnnadavesasceseseeusdesouradetenemebsnenteeneseanedeeenees 69 Erase Sector s 0 Ec 70 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE VIII FEBRUARY 2 2009 LisT OF TABLES SSD Dxxx I 4210 DATA SHEET Table 57 Request Sense e DD EE 71 Table 58 Extended Error e TEE 71 Table 59 Translate Sector 9 h EEN 72 Table 60 Wear E KE EE 73 Table 61 Write Multiple w o Erase CD 74 Table 62 Write Sector s w o Erase 29 75 Tabl 63 Write VND ELO CE 76 Table 64 Part Numbering Nomenclature sss 77 Table 55 Part NUMBG TS us ai odo tib n a aud RAM IRAN MORE Coe aan aM quan Du aca aa Prio 77 Table 66 Related Documentation eebe dSeEdNeESEEdNENEKeNENE doaaundassncieudeacsuns slc cune pna ge 79 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE IX FEBRUARY 2 2009 PHYSICAL SPECIFICATIONS SSD Dxxx I 4210 DATA SHEET PHYSICAL SPECIFICATIONS The SiliconDrive EP 2 5 PATA Drive products ar
55. gnals Table 7 Pin Assignments Pin IDE ATA Ultra DMA Pin IDE ATA Ultra DMA 1 RESET RESET 2 GND GND 3 D7 D7 4 D8 D8 5 D6 D6 6 D9 D9 7 D5 D5 8 D10 D10 9 D4 D4 10 D11 D11 11 D3 D3 12 D12 D12 13 D2 D2 14 D13 D13 15 D1 D1 16 D14 D14 17 DO DO 18 D15 D15 19 GND GND 20 KEY KEY 21 DMARQ DMARQ 22 GND GND 23 IOWR STOP 24 GND GND HDSTROBE 25 IORD HDMARDY 26 GND GND DDSTROBE 27 IORDY DDMARDY 28 CSEL CSEL 29 DMACK DMACK 30 GND GND 31 INTRQ INTRQ 32 lOCS16 lOCS16 33 A1 A1 34 PDIAG PDIAG 35 AO AO 36 A2 A2 37 CSO CSO 38 CS1 CS1 39 DASP DASP 40 GND GND 4210D 03DSR SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited PAGE 6 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET SIGNAL DESCRIPTIONS Table 8 Signal Descriptions Signal Name Pin s Type Description A2 A0 36 33 35 Address Inputs These signals are asserted by the host to access the task registers in the device CS0 CS1 37 38 In the true IDE mode CSO is the chip select for the task file registers while CS1 is used to select the Alternate Status register and the Device Control register CSEL 28
56. h LBA23 16 Drive Head 1 LBA 1 Drive Head Number LBA27 24 Command 40h or 41h SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 58 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Seek 7Xh The Seek command seeks and picks up the head to the tracks specified in the task file When the command is issued the solid state memory chips do not need to be formatted After an appropriate amount of time the DSC bit is set Table 44 Seek 7Xh Register D Dg D5 D4 Dg D2 Dy Do Feature X Sector Count X Sector Number Sector Number LBA7 0 Cylinder Low Cylinder Low LBA15 8 Cylinder High Cylinder High LBA23 16 Drive Head 1 LBA 1 Drive Head Number LBA27 24 Command 7Xh SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 59 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Set Features EFh The Set Features command allows the host to configure the feature set of the device according to the attributes listed in Table 46 Table 45 Set Features
57. horized use and or reproduction is prohibited 4210D 03DSR PAGE 47 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Table 33 Identify Drive Drive Attribute Data Continued HM Data Default Bytes Data Description 62 0000h 2 Single word DMA modes supported 63 0007h 2 2 Multiword DMA mode 2 supported e 1 Multiword DMA mode 1 supported e 0 Multiword DMA mode 0 supported 64 0003h 2 7 0 Advanced PIO modes supported 65 0078h 2 15 0 Multiword DMA cycle time in nanoseconds 66 0078h 2 15 0 Multiword DMA transfer cycle time in nanoseconds 67 0078h 2 15 0 PIO mode cycle time without flow control 68 0078h 2 15 0 PIO mode cycle time with IORDY flow control 80 O003Eh 2 5 ATA ATAPI 5 supported 4 ATA ATAPI 4 supported 3 ATA 3 supported 2 ATA 2 supported 1 ATA 2 supported 0 Reserved 88 001Fh 2 4 UDMA mode 4 supported 3 UDMA mode 3 supported 2 UDMA mode 2 supported e 1 UDMA mode 1 supported e 0 UDMA mode 0 supported 163 0002h 2 2 Multiword DMA mode and PIO mode 6 supported SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 48 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Idle 97h E3h When issued by the host the devic
58. in it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited FEBRUARY 2 2009 4210D 03DSR PAGE 23 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET DMARQ device DMACK host N M ty tmu Fu tack STOP T host Me trap hopp DDMARDY device HSTROBE St o host ei Sat tovs DD 15 0 os _ 2QOOOX DOOOOOOOOOCOK CR M tack DAO DA1 DA2 CSO CS1 Figure 15 Device Terminating a UDMA Data Out Burst tovH Note The definitions for the DIOW STOP IORDY DDMARDY DSTROBE and DIOR HDMARDY HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Table 13 UDMA Data Burst Timing Requirements Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Comment see Notes 1 and Symbol 2 Units Min Max Min Max Min Max Min Max Min Max tocyctyp 240 160 120 90 60 Typical sustained average ns two cycle time tcvc 112 73 54 39 25 Cycle time allowing for ns asymmetry and clock variations from STROBE edge to STROBE edge tocvc 230 154 115 86 57 Two cycle time allowing for ns clock variations from rising edge to next rising edge or from falling edge to next falling edge of STROBE tps 15 10 7 7 5 Data setup time at recipient ns toy 5 5 5 5 5 Data hold time at recipient ns
59. is register supports only either odd or even byte data transfers Table 16 Feature Register Operation D7 De D5 D D3 Do Di Do Read Write Feature Byte SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 29 FEBRUARY 2 2009 ATA REGISTERS SSD Dxxx I 4210 DATA SHEET SECTOR COUNT REGISTER The Sector Count register is used to read or write the sector count of the data for which an ATA transfer has been made Table 17 Sector Count Register Operation D De Ds D4 D3 Do D Do Read Write Sector Count Default Value 0 0 0 0 0 0 0 1 SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited PAGE 30 4210D 03DSR FEBRUARY 2 2009 ATA REGISTERS SSD Dxxx I 4210 DATA SHEET SECTOR NUMBER REGISTER The Sector Number register is set by the host to specify the starting sector number associated with the next ATA command to be executed Following a qualified ATA command sequence the device sets the register value to the last sector read or written as a result of the previous AT command When Logical Block Addressing LBA mode is implemented and the host issues a command the contents
60. is used for DMA transfers between the host and device DMARQ is asserted by the device when the device is ready to transfer data to from the host The direction of data transfer is controller by IORD and IOWR This signal is used in a handshake manner with DMACK i e the device waits until the host asserts DMACK before negating DMARQ and reasserts DMARQ if there is more data to transfer The DMARQ DMACK handshake is used to provide flow control during the transfer SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc 4210D 03DSR All unauthorized use and or reproduction is prohibited PAGE 8 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET Table 8 Signal Descriptions Continued Signal Name Pin s Type Description DMARQ This signal is a DMA request that is used UDMA for DMA data transfers between the host protocol and device This signal is asserted by the active device when it is ready to transfer data to or from the host For Multiword DMA transfers the direction of data transfer is controlled by IORD and IOWR This signal is used in a handshake manner with DMACK i e the device waits until the host asserts JDMACK before negating DMARQ and reasserts DMARQ if there is more data to transfer In PCMCIA I O mode the DMARQ is ignored by the host while the host is performing
61. ode 98h E5h Reg ister D7 Dg Ds D4 D3 D D Do Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head X X X Drive Command 98h or E5h Xp X X xx SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 42 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Executive Drive Diagnostic 90h The Executive Drive Diagnostic performs an internal read write diagnostic test using AA55h and 55AAh If an error is detected in the read write buffer the Error register reports the appropriate diagnostic code Table 30 Executive Drive Diagnostic 90h Register D7 De Ds D3 D3 Do D4 Do Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head X X X Drive Command 90h Xp X OX xx SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 43 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Format Track 50h The Format Track command formats the common solid state memory array Table 31
62. or Count Sector Number Cylinder Low Cylinder High Drive Head 1 LBA 1 Drive X Command 1Xh XI X OX xx SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 52 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Read Buffer E4h The Read Buffer command allows the host to read the contents of the sector buffer When issued the device sets the BSY bit and sets up the sector buffer data in preparation for the read operation When the data is ready the DRQ bit is set and the BSY bit in the Status register are set and cleared respectively Table 38 Read Buffer E4h Register D De Ds D D3 Do D Do Feature Sector Count Sector Number Cylinder Low Cylinder High Drive Head X X X Drive X Command E4h Xp X OX xx SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 53 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Read DMA C8h The Read DMA command allows the host to read data using the DMA transfer
63. otes d 2 If the drive cannot sustain continuous minimum cycle time DMA transfers it may negate DMARQ within the time specified from the start of a DMA transfer cycle to suspend the DMA transfers in progress and reassert the signal at a later time to continue the DMA operation This signal may be negated by the host to suspend the DMA transfer in progress SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc 4210D 03DSR All unauthorized use and or reproduction is prohibited PAGE 15 FEBRUARY 2 2009 ELECTRICAL SPECIFICATION SSD Dxxx I 4210 DATA SHEET Table 12 True IDE Multiword DMA Read Write Access Timing Symbol Item Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Note Units to Cycle Time minimum 480 150 120 100 80 1 ns tp IORD IOWR 215 80 70 65 55 1 ns Asserted Width minimum te IORD Data Access 150 60 50 50 45 ns maximum tr IORD Data Hold 5 5 5 5 5 ns minimum tc IORD IOWR Data 100 30 20 15 10 ns Setup minimum ty IOWR Data Hold 20 15 10 5 5 ns minimum ti DMACK to IORD 0 0 0 0 0 ns IOWR Setup minimum ty IORD IOWR to 20 5 5 5 5 ns DMACK Hold minimum Dep IORD Negated Width 50 50 25 25 20 1 ns minimum tkw IOWR Negated Width 215 50 25 25 20 1 ns minimum tLR IORD to DMARQ 120 40 35 35 35 ns Delay maximum tiw IOWR to DM
64. quest Sense OI M 71 Translate Sector d EE 72 Wear Level TI EE 73 Write Multiple w o Erase CD 74 Write Sector s w o Erase 29 75 Write Venfy 3C TC 76 Sales and SUD DOM TE 77 Part Numbaerind uicina iibi xuna kiwi coa bx es cr A FAR ERR C MAR do EEN 77 legia mr 77 Part Mine 77 RoHS 6 of 6 Product Labeling Pb Free Identification Label 78 Sample Label eM PET T 78 iieri HHE 79 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE V FEBRUARY 2 2009 LisT OF FIGURES SSD Dxxx I 4210 DATA SHEET LisT OF FIGURES Figure 1 Physical BirtieliSlor S oss oon Se esses rene dealer Up d Eur ee 1 Repeat Pin LC ANON RR 2 Figure 3 Jumper SettiNgS eieiei 2 Figure 4 True IDE PIO Mode Read Write Access Timing Diagram 13 Figure 5 True IDE Multiword DMA Read Write Access Timing 15 Figure 6 Initiating a UDMA Data In Buret errre rressssssssrrrrrrrrrrrrrrreeen 17 Figure 7 Sustained UDMA Datta In PBuret A 18 Figure 8 Host Pausing a UDMA Data In PBuret 18 Figure 9 Device Terminating a UDMA Data In Buret sees 19 Fig
65. re available under NDA FEATURES RoHS 6 of 6 compliant e Integrated PowerArmor and SISMART technology Capacity range 16GB to 64GB e Supports 5V interface MTBF 4 000 000 hours ATA 5 compliant Industry standard 2 5 Drive form factor e Supports UDMA modes 0 4 Speak toan Email Us Engineer Click here Click here SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 26840 ALISO VIEJO PARKWAY ALISO VIEJO CA 92656 PHONE 949 900 9400 e FAX 949 900 9500 http www siliconsystems com 4210D 03DSR FEBRUARY 2 2009 REVISION HISTORY SSD Dxxx I 4210 DATA SHEET REVISION HISTORY Document No Release Date Changes 4210D 03DSR February 2 2009 Updated e System Reliability table and changed the name to Reliability Related Documentation table Added Projected Operational Life Span 4210D 02DSR December 15 2008 External release with internal updates 4210D 01DSR PRELIMINARY September 25 2008 Internal updates 4210D 00DSR PRELIMINARY September 16 2008 Initial internal release 4210D 03DSR SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited
66. ribute Data Continued HN Data Default Bytes Data Description 20 0001h 2 Buffer type 0000h Not specified 0001h A single ported single sector buffer e 0002h A dual ported multisector buffer e 0003h A dual ported multisector buffer with a read caching 21 0001h 2 Buffer size in 512 byte increments 22 0004h 2 Number of ECC bytes passed on read write long commands 23 26 XXXXh 8 Firmware revision eight ASCII characters 27 46 XXXXh 40 Model number 40 ASCII characters 47 8001h 2 15 8 Maximum number of sectors that can be transferred with a Read Write Multiple command per interrupt 48 0000h 2 Double word 32 bit not supported 49 OfOOh 2 11 IORDY supported 9 LBA supported e 8 DMA supported 50 0000h 2 Reserved 51 0200h 2 15 8 PIO data transfer cycle timing 52 0000h 2 15 8 DMA data transfer cycle timing 53 0007h 2 2 Word 88 is valid e 1 Words 64 70 are valid 0 Words 54 58 are valid 54 XXXXh 2 Current number of cylinders 55 XXXXh 2 Current number of heads 56 XXXXh 2 Current sectors per track 57 58 XXXXh 4 Current capacity in sectors 59 010Xh 2 7 0 Current sectors can be transferred with a Read Write Multiple command per interrupt 60 61 XXXXh 4 Total number of sectors addressable in LBA mode SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unaut
67. t www siliconsystems com or contact your SiliconSystems Sales Representative Table 66 Related Documentation SiliconDrive EP Application Specific Description Document Number Technology PowerArmor Eliminates drive corruption WP 007 0xR SISMART Calculates remaining useful life WP 008 0xR SiliconSystems performance tests ratings and product specifications are measured using specific computer systems and or components and reflect the approximate performance of SiliconSystems products as measured by those tests Any difference in system hardware or software design or configuration as well as system use may affect actual test results ratings and product specifications SiliconSystems welcomes user comments and reserves the right to revise this document and or make updates to product specifications products or programs described without notice at any time SiliconSystems makes no representations or warranties regarding this document The names of actual companies and products mentioned herein are the trademarks of their respective owners SiliconSystems SiliconDrive SiliconDrive II SiSecure SiliconDrive EP9 PowerArmor SiSMART SiKey SiZone SiProtect SiSweep SiPurge SiScrub SiliconDrive USB Blade SolidStor and the SiliconSystems logo are trademarks or registered trademarks of SiliconSystems Inc and may be used publicly only with the permission of SiliconSystems and require proper
68. ta Table 33 Identify Drive Drive Attribute Data Word Address Data Default Bytes Data Description 0 045Ah 2 General configuration bit information 15 Non magnetic disk 14 Formatting speed latency permissible gap needed 13 Track Offset option supported 12 Data Strobe Offset option supported 11 Over 0 5 rotational speed difference 10 Disk transfer rate gt 10Mbps 9 10Mbps gt disk transfer rate gt 5Mbps 8 5Mbps gt disk transfer rate 7 Removable cartridge drive 6 Fixed drive 5 Spindle Motor Control option executed 4 Over 15ys changing head time 3 Non MFM encoding 2 Soft sector allocation 1 Hard sector allocation 0 Reserved XXXXh Number of cylinders 0000h Reserved 00XXh Number of heads 0000h Number of unformatted bytes per track XXXXh Number of unformatted bytes per sector XXXXh Number of sectors per track I CO XXXXh Number of sectors per device c Jl Oo Ou ki Goal M i gt 0000h N AIN N N NNN Reserved e A c XXXXh N O Serial number 4210D 03DSR SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited PAGE 46 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Table 33 Identify Drive Drive Att
69. te t ertt ecu ra ne cuat dudes deseas 43 zen m mios E 44 identify Drive IN T 45 Identify Drive Drive Attribute Data 46 Ide e EI m 49 Idle Immediate 95h CL 50 Initialize Drive Parameters 91h eceeee eere nene cc ecc n eene 51 Recalibrate d tete m 52 i es i dad e 53 Read DMA LIP E 54 Read Multiple CA inca 55 Read Sector ge E ln EEN 56 SILICONSYSTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE IV FEBRUARY 2 2009 TABLE OF CONTENTS SSD Dxxx I 4210 DATA SHEET Read Long Sector s 22h Et ebtkeueteeEueteee CES 57 Read Verify Sector s 40h A1b cecceeeeeceeceeeeeseeeeeeeeeeeeaeeeeeeeeeeeeeeneeeeees 58 Seek Xic EP T PM 59 S t Features mig me Rm 60 Set Multiple Mode GSI eege EECH 61 Set Sleep Mode 99h EDI esae tesis es occ eebe EES 62 Standby EE 63 Standby Immediate 94h EDDY EE 64 Vine Sulle EBD emis adis n dA aa a tree ba Ui Dd ada idit 65 mcis Phe A Me acetate 66 Write E ec E 67 Write Sector s le PES qr C 68 Write Long Sectors 32h 33D asia a pope ee Gees neem denen Sees 69 Erase Sector s COR 70 Re
70. the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 50 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Initialize Drive Parameters 91h Initialize Drive Parameters allows the host to set the sector counts per track and the head counts per cylinder to 1 Fixed Upon issuance of the command the device sets the BSY bit and associated parameters clears the BSY bit and issues an interrupt Table 36 Initialize Drive Parameters 91h Register D Dc Ds D D3 Do D Do Feature X Sector Count Sector Count Number of Sectors Sector Number X Cylinder Low X Cylinder High X Drive Head X 0 X Drive Head Number Number of Heads 1 Command 91h SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE 51 FEBRUARY 2 2009 ATA CoMMAND BLOCK AND SET DESCRIPTION SSD Dxxx I 4210 DATA SHEET Recalibrate 1Xh The Recalibrate command sets the cylinder low and high head number to Oh and sector number to 1h in CHS mode In LBA mode i e LBA 1 the sector number is set to Oh Table 37 Recalibrate 1Xh Register D7 Dc Ds D D3 Do D Do Feature Sect
71. ure 10 Host Terminating a UDMA Data In Buret ne 20 Figure 11 Initiating a UDMA Data Out Burst ccc cece cece e eee eeeeeeneeeteeeeeeeeeeeeeeeeeeees 21 Figure 12 Sustained UDMA Data Out Buret cece cece eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 21 Figure 13 Device Pausing a UDMA Data Out Buste 22 Figure 14 Host Terminating a UDMA Data Out Buste 23 Figure 15 Device Terminating a UDMA Data Out Burst esses 24 Figure 16 Sample abel it steep cece eevee ansaid eue nanaii 78 SiLICONSYsTEMS PROPRIETARY This document and the information contained within it is confidential and proprietary to SiliconSystems Inc All unauthorized use and or reproduction is prohibited 4210D 03DSR PAGE VI FEBRUARY 2 2009 LisT OF TABLES SSD Dxxx I 4210 DATA SHEET LisT OF TABLES Table 1 System en EE 3 Table 2 System Power Heourements EE 3 Table dii l i 4 Table 4 Operational Life Spice amu otn un SUO PaVEPUPGU MUCH ENECR 4 Table 5 Product Capacity Specifications ugedoe ENNER 5 Table 6 Environmental Gpechhcatons EEN 5 Table 7 Pin Assignments cee 6 Table 8 Signal Descriptions RI T T 7 Table 9 Absolute Maximum Ratings eee eeeeeeen enne nereeeren 11 Tabl 10 DC Char cteiStiCS T 12 Table 11 True IDE PIO Mode Read Write Access Tummmg 14 Table 12 True IDE Multiword DMA Read Write Access Timing 16

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