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Siemens SPC3 User's Manual

1. a 5 cik SPC3 48 MHz M 1K 8oj XINTIMOT CLK2 2 uC 36_ RESET XDATAEX o 13 uC XSPC3CS 14 XCS XREADY 14 XREADY um gt M 1K 23 1 MODE uc M ik 24 ALE XINT PS XEXIN Te gt l XWRL 20 XWR pe XRD AJ XRD P5 At 34 XTESTO XCTS p 33 1K P5 At 359 XTESTI 5Vor 1 DIVIDER RXD 30 RXD R5485 ground RTS 27 RTS T RS485 gt ABO 44 0 TXD 26 TXD pue gt ABI 43 AB2 4 19 ol 11 DBO AB3 40 3 1 12 D I AB4 37 14 2 15 DB2 AB5 42 5 o 3 16 DB3 AB6 32 6 4 19 DB4 AB7 31 17 51 20 DBS AB8 29 18 6 21 DB6 2 7 22 DB7 AB 0 10 e E if 7 uC The pull up 7 pull down resistances in the drawing above are only relevant for a in circuit tester Dual Port RAM Controller The internal 1 5k RAM of the SPC3 is a Single Port RAM Due to an integrated Dual Port RAM controller the controller however permits an almost simultaneous access of both ports bus interface and microsequencer interface When there is a simultaneous access of both ports the bus interface has priority This provides for the shortest possible access time If SPC3 is connected to a microcontroller with an asynchronous interface SPC3 can evaluate the Ready signal Page 42 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003
2. Low Cost System with 80C32 Pulse Generator 48MHz DIVIDER 12 24 MHz y a E WR gt xwp PR RD gt XRD x INTO WM X INT RTS DB 7 0 TxD Ir Port 0 AID 7 0 SE ly 80C32 DB 7 0 RxD C501 ALE Address Latch 1K Port 2 AB 15 8 0000 00XX BIN GND Reset GND VDD 80C32 System with Ext Memory C32 Mode Pulse Generator 48 MHz 12 24 MHz DIVIDER CLK WR caler 2 4 RD INTO PX 80C32 2016M Hz j i Address Porto A D 7 0 Latch Port2 AB 15 8 0000 OOXXBIN PSEN AB 15 0 Reset ja Address EPROM RAM le Decoder 64kB 32kB j 1 1K HR dk che eoe o RD WR GND VDD SPC3 Hardware Description V1 3 Page 39 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S 80286 System X86 Mode Clock Generator 48 MHz DIVIDER 12 24 MHz XWR XRD X INT XREADY 80286 Buscontr DB K DB 15 0 DB 7 0 82288 82244 AB 23 0 AB 12 1 GND RD WA Reset ET Driver Control logic XCS Mode Reset 4CSRAM Address ekg RAM CSEPROW Decoder 64kB 32kB GND Page 40 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface
3. Parameter Des Min Max unit AMI Vers ST Vers AMI Vers ST Vers Input leakage current l 1 1 1 1 uA Tristate output leakage loz 10 10 10 10 uA current Tabelle 8 5 Leakage current of the output drivers 8 4 AC Specification for the Output Drivers Signal lineeitung Driver type Driver power TI Unit kap Last sero hr l ST Vers O DB 7 0 Tristate 8 83 mA 100pF TXD Tristate 8 8 mA 50pF XINT Triste 8 m OF XREADY XDSACK _ Tristate 8 4 mA Soe CLKOUT2 4 Tristate 8 amp ma op Hint The output power of the AMI drivers is entspricht 8mA under the circumstances described in Tabel 8 3 Tabel 8 6 AC Specifikation of the output drivers SPC3 Hardware Description V1 3 Page 45 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S 8 5 Timing Characteristics The following is generally applicable All signals beginning with X are low active All signal runtimes are based on the capacitive loads specified in the table above 8 5 1 SYS Bus Interface Clock Pulse Ne Paani Sid WK Clock pulse 48 Mhz Clock High Time 6 25 14 6 Clock Low Time 6 25 14 6 A GS TS E p FalTime ns Clock Pulse Timing CLK Distortions in the clock pulse signal are permitted up to a ratio of 40 60 At a threshold of 1 5 or 3 5 V Interrupts REENEN merirem S
4. New Slave Address LL TI TTT ident Number High St E NS dent Number Low FT No Add Chg za 243 Rem_Slave_Data additional application specific data Figure 6 4 Data Format for the Set_Slave_Address Telegram SPC3 Hardware Description V1 3 Page 29 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S 6 2 2 Set_Param SAP61 6 2 2 1 Parameter Data Structure SPC3 evaluates the first seven data bytes without user prm data or the first eight data bytes with user prm data The first seven bytes are specified according to the standard The eighth byte is used for SPC3 specific characteristics The additional bytes are available to the application SE FJeTeJslefetiTe WD User Prm Data Spec User Prm _Byte Default State Dis Startbit The start bit monitoring in the Dis Startbit 1 receiver is switched off with this bit that is start bit monitoring is switched off rie Stopbit Stop bit monitoring in the receiver is Dis_Stopbit 0 switched off with this bit that is stop bit monitoring is not switched off an Base This bit specifies the time base used WD_Base 0 to clock the watchdog that is the time base is 10 ms WD_Base 0 time base 10 ms WD Base 1 time base 1 ms 3 7 Jee tobeparameterizedwithO JO Figure 6 5 Data Format for the Set_Param_Telegram 6 2 2 2 Parameter Data Processing Sequence In the case of a positive validatati
5. SI E M E N S SPC3 PROFIBUS Interface Center 4 2 Processor Parameters Latches Register These cells can be either read only or written only SPC3 carries out address swapping for an access to the address area 00H 07H word register in the Motorola mode That is the SPC3 exchanges address bit 0 generated from an even address one uneven and vice versa The following sections more clearly explain the significance of the individual registers Address Name Bit Significance Read Access Intel 7 Motorla No i SR Reg Interrupt Controller Register 01H OOH Ce ELT 15 8 03H 02H Tai Reg 15 8 04H OSH _ Status Reg Status Register 7 0 05H 04H _ Status Reg 15 8 Reserved DP_Din_Buffer_State Machine mr ROR Bacon tra oF on EE 1 0 the N state O e E en on 7 0 DP_Dout_Puffer_State Machine Wann Jee 1 0 state DP_Diag_Puffer_State Machine g Pec ee rea OF ra Lt the SPC3 Oe e Kee 1 0 parameter setting data of a Set_Param Telegram O r a E en 1 0 parameter setting data of a Set_Param Telegram En rc IT data of a Check Config Telegram data of a Check Config Telegram S T Ren eienableettobutter agai and enables the buffer and enables Me Suter agin _________ ISH Reserved Figure 4 2 Assignment of the Internal Parameter Latches for READ SPC3 Hardware Description V1 3 Page 13 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E
6. 3 Diagnostics 2 Parameter setting data 1 Configuration data 2 Auxiliary buffer 2 SSA buffer 1 Figure 4 1 SPC3 Memory Area Distribution Caution The HW prohibits overranging the address area That is if a user writes or reads past the memory end 400H is subtracted from this address and the user therefore accesses a new address This prohibits overwriting a process parameter In this case the SPC3 generates the RAM access violation interrupt If the MS overranges the memory end due to a faulty buffer initialization the same procedure is executed Data In is the input data from PROFIBUS slave to master Data out is the output data from PROFIBUS master to slave SPC3 Hardware Description V1 3 Page 11 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S The complete internal RAM of the SPC 3 is divided logically into 192 segments Each segment consists of 8 bytes For more informations about the contents of the 3 memory areas see previous chapter The physical address is build by multiplikation with 8 internal SPC 3 RAM 1 5 kByte Segment 0 Segment 1 Segment 2 8 Bit Segmentaddresses 7 0 Pointer to the buffers Segment 190 Segment 191 Page 12 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved
7. Data Reset 7 0 Clock Timeout Detect EX R Address Bit Position Control KE 11 Register 01H Bail OUT i New_ New_ a New_GC Int Req Reg 7 Intel Puffer_ Prm_ Cfg_ SSA_ Com 15 8 Changed Data Data Data mand S Page 22 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center setting the Go_Offline bit or through a RAM access violation Bit 1 Go Leave DATA EX The DP SM has entered or exited the DATA EX state Bit 2 Baudrate Detect The SPC3 has exited the Baud Search state and found a baud rate Bit 3 VVD DP Control Timeout The watchdog timer has run out in the DP Control WD state User Timer Clock The time base for the User Timer Clocks has run out 1 10ms For additional functions For additional functions For additional functions Bit 8 New GC Command The SPC3 has received a Global Control telegram with a changed GC Command Byte and this byte is stored in the R GC Command RAM cell New SSA Data in the SSA buffer Nevv Cfg Data The SPC3 has received a Check_Cfg telegram and made the data available in the Cfg Nevv Prm Data The SPC3 has received a Get Param telegram and made the data available in the Diag Puffer Changed and again made the old buffer available to the user Bit13 DS OUT The SPC3 has received a VVrite Read Data telegram and made the new output data Bit 0 MAC Reset After it processes
8. If the user is still supposed to enlarge the output data buffer after the Check_Config telegram the user must delete this delta in the N buffer himself possible only during the power up phase in the VVait Cfg state If Diag Sync_Mode 1 the D buffer is filled but not exchanged with the Write_Read_Data Telegram but rather exchanged at the next Sync or Unsync SPC3 Hardware Description V1 3 Page 33 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S The user can read the buffer management state with the following codes for the four states Nil Dout_Puf_Ptr1 3 The pointer for the current data is in the N state Address Bit Position Designation Control 7 5 4 3 2 Register D Dout Puffer MPJ X Xe Xt x2 1 xi x2 Xt x2 Re below for coding KA O 1 Dout Puf Pti i y 1 0 Dout_Puf_Ptr2 Dout_Puf_Ptr3 Figure 6 11 Dout_Buffer Management When reading the Next_Dout_Buffer_Cmd the user gets the information which buffer U buffer belongs to the user after the change or whether a change has taken place at all Address a Tia ej Control K Ka Kal i Next Dout But Cmd SA Buffer Cleared Ei O 1 Dout But Pr 14 1 Dout pu Pr3 o NonewUbuffer_ ier snare Figure 6 12 Next_Dout_Puffer_Cmd The user must delete the U buffer during initialization so that defined deleted data can be sent for a He
9. The DDB utility is disabled by the already described initialization of the RAM cells The DP_SAP buffer structure is displayed in Figure 6 1 The user configures all buffers length and buffer beginning in the offline state During operation the buffer configuration must not be changed except for the length of the Dout Din buffers The user may still adapt these buffers in the Wait_Cfg state after the configuration telegram Check_Config Only the same configuration may be accepted in the DATA_EX state The buffer structure is divided into the data buffer diagnostics buffer and the control buffer Both the output data and the input data have three buffers each available with the same length These buffers function as change buffers One buffer is assigned to the D data transfer and one buffer is assigned to the U user The third buffer is either in a Next N state or Free F state whereby one of the two states is always unoccupied Two diagnostics buffers that can have varying lengths are available for diagnostics One diagnostics buffer is always the D assigned to SPC3 for sending The other diagnostics buffer belongs to the user for preparing new diagnostics data U The SPC3 first reads the different parameter setting telegrams Set Slave Address and Set Param and the configuring telegram Check_Config into Aux Puffer1 or Aux Puffer 2 Page 26 V1 3 SPC3 Hardware Description
10. a 12 10 16 Be 0 0 7 7 ye 0 1 5 9 G 0 13 0 20 H 1 95 J 0 30 0 30 K 0 40 2H Footprint 2 3 90 3 90 8 5 8 Processing Instructions ESD protective measures must be maintained for all electronic components SPC3 is a cracking endangered component that must be handled as such A drying process must be carried out before SPC3 is processed The component must be dried at 1250 C for 24 hours and then be processed within 48 hours This drying process may be carried out once only because the component is soldered It must also be ensured that the SPC3 s connections are not bent Flawless processing can be guaranteed only if a planity of less than 0 1 mm is ensured SPC3 is released for infrared soldering with a soldering profile according to CECC00802 V1 3 SPC3 Hardware Description Page 56 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center 9 PROFIBUS Interface 9 1 Pin Assignment The data transmission is performed in RS 485 operating mode i e physical RS 485 The SPC3 is connected via the following signals to the galvanically isolated interface drivers Output RTS Output Request to send TXD Output Sending data RXD Input Receiving data The PROFIBUS interface is a 9 vvay sub D plug connector vvith the follovving pin assignment Pin 1 Free Pin 2 Free Pin 3 B line P
11. independent of the interrupt masks Event signals not masked out in the IMR generate the X INT interrupt via a sum network The user can set each event in the IRR for debugging Each interrupt event the processor processed must be deleted via the IAR except for New_Prm_Data New_DDB_Prm_Data and New_Cfg_Data Log 1 must be written on the relevant bit position If a new event and an acknowledge from the previous event are present at the IRR at the same time the event remains stored If the processor subsequently enables a mask it must be ensured that no prior input is present in the IRR For safety purposes the position in the IRR must be deleted prior to the mask enable Prior to exiting the interrupt routine the processor must set the end of interrupt signal E01 1 in the mode register The interrupt cable is switched to inactive with this edge change If another event must be stored the interrupt output is not activated again until after an interrupt inactive time of at least 1 usec or 1 2 ms This interrupt inactive time can be set via EOI_Timebase This makes it possible to again come into the interrupt routine when an edge triggered interrupt input is used The polarity for the interrupt output is parameterized via the INT_Pol mode bit After the hardware reset the output is low active Address Bit Position Designation Control a 3 Register OO Bag WD DP Baud Go Leave MAC nt Req Reg Intel Timer_ Mode rate
12. log 0 Asynchronous Motorola Mode Processor VVrite Timing AB 10 0 69 62 Da 7 0 RSR D D bo S al ze AS RW Be I L AT 8 XCS e e P normal e D I e a early E_Clock log 0 SPC3 Hardware Description V1 3 Page 53 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S 8 5 6 Serial Bus Interface Pulse 48 MHz 1 RTS to TxD Setup Time 4T 2 RTS J to TxD Hold Token AT T Clock pulse cycle 48MHz RTS TxD Page 54 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center 8 5 7 Housing PQFP 44 Housing INDICATOR SEE DETAIL A Ti Alo i y AT L lt SEATING PLANE 0 10 SPC3 Hardware Description V1 3 Page 55 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SIE MENS G DETAIL A Symbol Min Typ Max AMI Vers ST Vers AMI Vers ST Vers AMI Vers ST Vers A 2 13 2 35 2 45 A1 0 10 0 25 0 15 0 25 A2 1 95 1 90 2 00 2 00 2 10 2 10 D 13 65 13 65 13 90 13 90 14 15 14 15 D1 9 90 9 90 10 00 10 00 10 10 10 10 E 13 65 13 65 13 90 13 90 14 15 14 15 E1 9 90 9 90 10 00 10 00 10 10 10 10 L 0 65 0 78 0 80 0 88 0 95 1 03 e BASIC 0 80 0 80 B 0 30 0 30 0 35 0 45 0 40 c 0 13 0 23 0 17
13. 16Bit values are shown in the Motorola format For example Buffer pointer high byte Buffer pointer 1 low byte Page 64 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved Siemens AG Division Automation Engineering Combination Engineering Siemens AG PO Box 23 55 D 90713 Fuerth Germany Subject to change without prior notice SIEMENS Aktiengesellschaft Printed in the Fed Rep of Germany
14. 2003 04 Copyright C Siemens AG 2003 All rights reserved SIEMENS D Nis changed by SPC 3 SPC3 D N gt lt e gt gt PROFIBUS Interface Center N U is changed by the user U UART gt lt Aux1 2 buffer gt gt Aux1 2 buffer v gt Figure 6 1 DP_SAP Buffer Structure Dout buffer Din buffer Diagnostics buffer Read Config buffer Ay User Config buffer SSA buffer Param buffer Data exchanged with the corresponding target buffer SSA buffer Prm buffer and Cfg buffer Each of the buffers to be exchanged must have the same length The user defines which Aux_buffers are to be used for the above named telegrams in the R_Aux_Puf_Sel parameter cell The Aux bufferi must always be available The Aux buffer2 is optional If the data profiles of these DP telegrams are very different such as the data amount in the Set_Param telegram is significantly larger than for the other telegrams it is suggested to make an Aux Buffer2 available Aux_Sel_Set_Param 1 for this telegram The other telegrams are then read via Aux Buffer 1 Aux_Sel_ 0 If the buffers are too small SPC3 responds with no resources SPC3 Hardware Description Copyright C Siemens AG 20
15. All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center 7 1 6 Interface Signals The data bus outputs are high resistance during the reset phase All outputs are switched to high resistance in the test mode See block test RT GR EE AB 10 has a pull down resistor MODE io S tting syn asyncinterface i O IXWR E_CLOCK I 1 Intel Write Motorola E Clk __ _ i O XRD RW UI TI Intel Read Motorola Read Write O CRU 1 Chip Select ChipSelect 1 JALE AS D CT CC Intel Motorola Address Latch Enable UJ DIVIDER Sealing factor 2 4 for CLKOUT 2 4 UJ XINT_ JO Tristate Polarity programmable XRDY XDTACK O Tristate Intel Motorola Ready Signal __ etk BM XINTMOT I JSetting Intel Motorola y CLKOUT2 4 O Tristate 12412 MHz _ _ S y RESET I SehmittTrigger Minimum of 4 clock pulse cycles Figure 7 2 Microprocessor Bus Signals 7 2 UART The transmitter converts the parallel data structure into a serial data flow Request to Send RTS is generated before the first character The XCTS input is available for connecting a modem After RTS active the transmitter must hold back the first telegram character until the XCTS modem activates The receiver converts the serial data flow into the parallel data structure The receiver scans the serial data flow with the four fold transmission speed Stop bit testing can be switched off for test purposes DIS_STOP_CONTROL 1 in mode register 0 or Se
16. M E N S SPC3 PROFIBUS Interface Center The request for a read access to SPC3 is derived from the positive edge of the E clock in addition XCS 0 RW 1 The request for a write access is derived from the negative edge of the E clock in addition XCS 0 R VV 0 TEST SS ns 40 E Clock Pulse VVidth ST 74 2 Address ABio o Setuptime to E_Clock T Address AB ol Holdtime after E_Clock 4 E ClockT to Data Active Delay 17 E ClockT to Data valid Zugriff auf RAM AT 45 88 3 E ClockT to Data valid Zugriff auf die Register AT 18 101 3 Data Holdtime after E Clock 4 6 3 H VV Setuptime to E Clock T H VV Holdtime after E Clock J XCS Setuptime to E Clock T XCS Holdtime after E Clock 4 Data Setuptime to E Clock 4 Data Holdtime after E Clock 4 Explanations T Clock pulse cycle 48MHz TBD to be defined S Access to the RAM P 8 Access to the registers latches e For T 48 MHz Synchronous Motorola Mode Processor Read Timing E_Clock AB 10 0 0807 0 SS XCS AS log 1 SPC3 Hardware Description V1 3 Page 51 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S Synchronous Motorola Mode Processor Write Timing E_Clock AB 10 0 DB 7 0 R_W XCS AS log 1 8 5 5 Timing in the Asynchronous Motorola Mode for example 68HC16 In the asynchronous Motorola mode the SPC3 acts like memory with Ready logic whereby the
17. Meaning of the bits is specified manufacturer specific 10 1 0 0 0 1 0 1 Identifier related diagnostics T 1 Identification number 0 has diagnostics S e EA 41 Identification number 18 has diagnostics i1jojojo 1 1 0 0 Channel related diagnostics identification number 12 10 0 0 0 0 1 1 0 Channel 6 PETI Upper limit evalue xceeded channel organized vvord by vvord Status If the Bit EXT_DIAG is set to 0 data is viewed as status info from the system view f e cancellation of the error triggering the diagnostics Page 62 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center 11 2 3 EXT_DIAG_OVERFLOW This bit is set if more diagnostics data is present than will fit in the available diagnostics data area For example more channel diagnostics could be present than the send buffer or the receive buffer makes possible 11 3 Diagnostics Processing from the System View Inasmuch as it is bus specific the diagnostics information of the slaves is managed solely by the master interface for example IM308B All diagnostics from the application are made available to the S6 program via corresponding data bytes If the External Diagnostics bit is set the slaves to be diagnosed can already be evaluated in the diagnostics overview Then a special error routine can be called up whereby the standard diagnost
18. N S Intel No Motorola Interrupt Controller Register 7 0 15 8 7 0 15 8 TN Reg 15 8 06H ne Rego Setting parameters for individual bits 15 8 7 0 Mode U ln R 7 U ln 7 0 LE 7 0 OCH x i ODH Reserved Va DEI Pe OFH pt 10H pt 11H Oooo y 12H C 13H Oooo y 14H Oooo y 15H Doo O Figure 4 3 Assignment of the Internal Parameter Latches for WRITE Page 14 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center 4 3 Organizational Parameters RAM The user stores the organizational parameters in RAM under the specified addresses These parameters can be written and read SPC3 Hardware Description V1 3 Page 15 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S Address Name Bit No Significance Motorola 7 0 Pointer to a RAM address which is presetted with OFFH 18H 19H JR User Wd Value Based on an internal 16 bit vvachdog timer the user is 7 0 monitored in the DP Mode R User VVd Value 15 8 for example SSA Buf Prm Buf Cfg Buf Read Cfg Buf 29H R Len Cntrl Puf2 Length of Aux Buffer 2 and the control buffer belonging to it for example SSA Buf Prm Buf Cfg Buf Read Cfg Buf 2AH R Aux Puf Sel Bit array in which the assignments of the Aux buffers Ve are defined to the control buffers SSA Buf Prm Buf Cfg Buf e again be changed at
19. Wat Co state 10 DATA EX state 11 Not possible VVatchdog State Machine state 00 Baud Search state 01 Baud Control state 10 DP Control state 11 Not possible Baud rate3 0 8 9 10 11 12 MBaud 6 MBaud 3 MBaud 1 5 MBaud 500 kBaud 187 5 kBaud 93 75 kBaud 45 45 kBaud 19 2 kBaud 9 6 kBaud Not possible SPC3 Release3 0 Release no for SPC3 0000 Release 0 Rest Not possible Bits VVD State1 0 6 7 Figure 5 3 Status Register Bit15 0 readable SPC3 Hardware Description V1 3 Page 21 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S 5 3 Interrupt Controller The processor is informed about indication messages and various error events via the interrupt controller Up to a total of 16 events are stored in the interrupt controller The events are carried out on an interrupt output The controller does not have a prioritization level and does not provide an interrupt vector not 8259A compatible The controller consists of an Interrupt Request Register IRR an Interrupt Mask Register IMR an Interrupt Register IR and an Interrupt Acknowledge Register IAR uP uP uP SEP_INT VAY e zs gt S gt X INT S IRR IMR 5 FF gt uF gt R R INT_Pol IAR e uP Each event is stored in the IRR Individual events can be suppressed via the IMR The input in the IRR is
20. XRD XWR J to XRDY J Early Ready ns XREADY Holdtime after XRD or XWR ns Data Setuptime to XWR T ns Data Holdtime after XWR T ns XW R Pulse Width ns XRD XWR Cycletime ns last XRD V to XCS x ns XCS T to next XWR ns XWR to next XWR XCS don t care ns Explanations T Clock pulse cycle 48MHz TBD to be defined a Access to the RAM 2 Access to the registers latches E For T 48 MHz SPC3 Hardware Description V1 3 Page 49 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S Asynchronous Intel Mode Processor Read Timing BEM Data out 1 gt XRD XCS XREADY normal XREADY early XWR log 1 Asynchronous Intel Mode Processor Write Timing AB 10 0 VALID Go 22 Der a DOTTED ED fl 3 XWR G9 os me mE kep 24 Te XREADY Li normal B i early O XRD log 1 8 5 4 Timing in the Synchronous Motorola Mode E_Clock Mode for example 68HC11 For a CPU clockline through the SPC3 the output clock pulse CLKOUT2 4 must be 4 times larger than the E CLOCK That is a clock pulse signal must be present at the CLK input that is at least 10 times larger than the desired system clock pulse E_CLOCK The Divider Pin must be placed on lt log 0 gt divider 4 This results in an E CLOCK of 3MHz Page 50 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E
21. a later time point 3DH R_Len_Spec_Prm_buf If parameters are set for the Spec_Prm_Buffer_Mode see mode register 0 this cell defines the length of the param buffer Figure 4 4 Assignment of the Organizational Parameters Page 16 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center 5 ASIC Interface The registers that determine both the hardware function of the ASIC as well as telegram processing are described in the following 5 1 Mode Register Parameter bits that access the controller directly or which the controller directly sets are combined in two mode registers 0 and 1 in the SPC3 5 1 1 Mode Register 0 Setting parameters for Mode Register 0 takes place in the offline state only for example after switching on The SPC3 may not exit offline until Mode Register 0 all processor parameters and organizational parameters are loaded START SPC3 1 Mode Register 1 conto TT KA ECH Control SSES 06H Freeze_ ES E EA il D Mode BEE Intel SE Support RDY POL MinTSDR STOP START_ 7 9 CON CON TROL TROL Address SEH Position e Control 14 11 Register 07H Spec_Cle all Prm_ WD User Bet e eh Rego Intel ari OS Puf _ T Test Time Time Mode 13 8 base base When Spec Clear Mode Fail Safe Mode 1 the SPC3 will accept data telegramm with a data unit 0 in he state Data Exchange The reaction to the outputs can
22. access times depend on the type of accesses The request for an access of SPC3 is generated from the positive edge of the AS signal in addition XCS 0 R_W 1 The request for a write access is generated from the positive edge of the AS signal in addition XCS 0 RLW 0 i JEZA Parameter 60 Address Setuptime to AS 1 0 0 ns AS J to Data valid Zugriff auf RAM 3T 45 2 108 AS J to Data valid Zugriff auf die Register AT 22 9 106 2 Address AB o o Holdtime after AS T H VV J Setuptime to AS 4 AS Puls VVidth Read Data Holdtime after AS T AS Inactive Time R_W Holdtime after AS T XCS J Setuptime to AS 4 XCS Holdtime after AS T AS to XDSACK J Read Normal Ready AS to XDSACK J Read Early Ready XDSACK Holdtime after AS T AS Cycletime Data Setuptime to AS T Data Holdtime after AS T AS Pulse Width Write last AS V Read to XCS A XCS T to next AS T Write AS T to next AS Write XCS don t care Explanations Page 52 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center T Pulse cycle 48MHz TBD To Be Defined Access to the RAM Access to the register latches S For T 48MHz Asynchronous Motorola Mode Processor Read Timing AB 10 0 VALID 62 DB 7 0 K Data out AS E 66 See Pd RW O Ge Sn XCS LS SCENE D l norma CO e XDSACK early 73 E Clock
23. assigned to SPC3 no Puffer Diag_Puf1 Diag_Puf2 Page 32 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center Address Bit Position Designation Kg Register ODH polo o o o yt New Des ema SS o o no Puffer SSS COD Puff SSS o Diag Put SSCS Figure 6 9 Coding Diag_Puffer_SM New_Diag_Cmd 6 2 4 2 Structure of the Diagnostics Buffer The user transfers the diagnostics buffer displayed in the figure below to SPC3 The first 6 bytes are space holders except for the three least significant bit positions in the first byte The user stores the diagnostics bits Diag Ext_Diag Diag Stat Diag and Diag Ext Diag Overflovv in these three bit positions The remaining bits can be assigned in any order When sending SPC3 pre processes the first six bytes corresponding to the standard DR Bit Position Kee ha ee oe TEREA Stat Ext_ Be GE Diag Diag SSES TI _ Spaceholder ee ce 3 Jf ft Jf LL Spaceholder 4 LI Spaceholder S Sf I fF Tt it Spacehoider 5 The user must input Ext_Diag_Data n max 243 Figure 6 10 Structure of the Diagnostics Buffer for Transfer to the SPC3 The Ext Diag_Data the user must enter into the buffers follow after the SPC3 internal diagnostics data The three different formats are possible here device related ID related and port relate
24. program memory the addresses must once again be latched off for the external memory The connection schematic in the next figure is applicable for all Intel Siemens processors that offer asynchronous bus timing and evaluate the ready signal Notes If the SPC3 is connected to an 80286 processor or others it must be taken into consideration that the processor carries out word accesses That is either a swapper is necessary that switches the characters out of the SPC3 at the relevant byte position of the 16 bit data bus during reading or the least significant address bit is not connected and the 80286 must read word accesses and evaluate only the lower byte as displayed in the figure SPC3 Hardware Description V1 3 Page 37 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S XINT MO MODE The SPC3 interface supports the following processors microcontrollers i synchron ous Motorola 1 asynchron ous Motorola 0 synchron ous Intel i 0 Motorola microcontroller vvith the follovving characteristics e Synchronous rigid bus timing without evaluation of the XREADY signal e 8 bit non multiplexed bus DB7 0 AB10 0 The following can be connected e HC11 types K N M F1 e HC16 und HC916 types with programmable E clock timing e All other HC11 types with a multiplexed bus must select addresses AB7 0 externally from DB7 0 data The address decoder is switche
25. same place The Bus Interface Unit BIU and the Dual Port RAM Controller DPC that controls accesses to the internal RAM belong to the processor interface of the SPC3 In addition a clock rate divider is integrated that the clock pulse of an external clock pulse generator divided by 2 Pin DIVIDER High Potential or 4 Pin DIVIDER Low Potential makes available on the pin CLKOUT2 4 as the system clock pulse so that a slower controller can be connected without additional expenditures in a low cost application SPC3 is supplied with a clock pulse rate of 48MHz 7 1 2 Bus Interface Unit BIU The BIU forms the interface to the connected processor microcontroller This is a synchronous or asynchronous 8 bit interface with an 11 bit address bus The interface is configurable via 2 pins XINT MOT MODE The connected processor family bus control signals such as XWR XRD or R_W and the data format is specified with the XINT MOT pin Synchronous rigid or asynchronous bus timing is specified with the MODE pin Various Intel system configurations are displayed in the figures in Section 7 1 3 The internal address latch and the integrated decoder must be used in the C32 mode One figure displays the minimum configuration of a system with SPC3 whereby the block is connected to an EPROM version of the controller Only a pulse generator is necessary as an additional block in this configuration If a controller is to be used without an integrated
26. the User VVD Timers 1 SPC3 again sets the User Wd Timer to the parameterized value User Wd Value15 0 After this action SPC3 sets Res User VVd to log 0 Figure 5 2 Mode Registeri S and Mode Register1 R Bit7 0 writable SPC3 Hardware Description V1 3 Page 19 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S 5 2 Status Register The status register mirrors the current SPC3 status and can be read only Address Bit Position Control 7 5 4 3 2 1 Register 04H WD_State DP_State RAM Diag_ FDL_ Offline ee Reg Intel access Flag IND_ST Passive 7 Q violation Idle 1 0 1 0 Address Designation _ Register 05H SPC3 Release Baud Rate Status Reg Intel 15 8 2 1 0 Page 20 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center Bit 0 0 SPC3 is in offline 1 SPC is in passive idle Bit 1 0 No FDL indication is temporarily buffered 1 No FDL indication is temporarily buffered Bit 2 0 The DP master fetches the diagnostics buffer 1 The DP master has not yet fetched the diagnostics buffer RAM Access Violation Memory access gt 1 5kByte O No address violation 1 For addresses gt 1536 bytes 1024 is subtracted from the current address and there is access to this nevv address Bits DP State1 0 4 5 DP State Machine state 00 Wat Pro state 01
27. to the transmitted data To minimize the capacity of the bus lines the user should avoid additional capacities The typical capacity of a bus station should be 15 25 pF Page 58 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SIEMENS SPC3 10 Appendix 10 1 Addresses PROFIBUS User Organisation PNO Office Mr Dr Wenzel Haid und Neu StraBe 7 76131 Karlsruhe Tel 0721 9658 590 Technical contact person at ComDeC in Germany Siemens AG A amp D SE RD73 Mr Putschky Address Postfach 2355 90713 Furth Tel 0911 750 2078 Fax 0911 750 2100 email Gerd Putschky osiemens com PROFIBUS Interface Center Technical contact person at the PROFIBUS Interface Center in the United States PROFIBUS Interface Center One Internet Plaza PO Box 4991 Johnson City TN 37602 4991 Fax 423 262 2103 Your Partner Ron Mitchell Tel 423 262 2687 email Ron Mitchell sea siemens com SPC3 Hardware Description Copyright C Siemens AG 2003 All rights reserved V1 3 Page 59 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S 10 2 General Definition of Terms ASPC2 Advanced Siemens PROFIBUS Controller 277 generation SPC2 Siemens PROFIBUS Controller 277 generation SPC3 Siemens PROFIBUS Controller 27 generation SPM2 Siemens PROFIBUS Multiplexer 2 generation LSPM2 Lean Siemens PROFIBUS Multiplexer SS generation DP Distributed I Os FMS F
28. 03 All rights reserved V1 3 Page 27 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S Address Bit Position Designation Register 2AH Set Check 1 Set R Aux Puf Sel Slave_ Cfg Prm Adr See below for coding Coding 0 Aux_Buffert Aux_Buffer2 Figure 6 2 Aux Buffer Management The user makes the configuration data Get_Config available in the Read_Cfg buffer for reading The Read_Cfg buffer must have the same length as the Cig butter The Read_Input_Data telegram is operated from the Din buffer in the D state and the Read_Output_Data telegram is operated from the Dout buffer in the U state All buffer pointers are 8 bit segment addresses because the SPC3 internally has only 8 bit address registers For a RAM access SPC3 adds an 8 bit offset address to the segment address shifted by 3 bits result 11 bit physical address As regards the buffer start addresses this results in an 8 byte graunularity from this specification Page 28 V1 3 2003 04 SPC3 Hardware Description Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center 6 2 Description of the DP Services 6 2 1 Set Slave Address SAP55 6 2 1 1 Sequence for the Set Slave Address Utility The user can disable this utility by setting the R SSA Puf Ptr OOH buffer pointer The slave address must then be determined for example by reading a switch and written in the R TG Adr RAM re
29. 2 mode data bus address CPU memory bus multiplexed IOC C165 mode data address bus separate 17 yss O VSS PO EL aaa ae EE en 19 DB4 C32 mode data bus address E SE lee ieee leger bus separate Ea as ea 22 jpB7 Leg 23 MODE lt log gt 0 80C166 Data bus address bus separated ready signal System lt log gt 1 80632 data bus address bus multiplexed fixed timing C165 mode lt log gt 0 aa A ere C165 mode address bus CPU C165 memory Serial send port RS 485 sender Request to Send RS 485 sender 26 O par GR 28 WE E a C165 Mode address bus 30 JRXO TI l sid Seialreceiveport e LD 485 receiver 31 JAB7 T Addresshs Leien CL O 32 JAB8 TI 9 Addresshs Leem U O 33 xcTS l Cleartosend lt log gt O sendenable L kmoiem 34 XTESTO l Pinmustbe placed fixed at VDD o o O 35 XTEST1 l _ Pin mustbe placed fixed at VDD o o O 86 RESET ICS Connect reset input with CPU s port pin el 37 JAB4 9 Addresshs Leem CL O 38 DES SSES DREES 39 vod LI 40 asas LL 8 Address bus System CPU Figure 3 1 SPC3 Pin Assignment 15 16 17 18 20 21 22 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 S Note e All signals that begin with X are LOW active e VDD 5V VSS GND Input levels Ir CMOS I CS CMOS Schmitt trigger SPC3 Hardware Description V1 3 Page 9 Co
30. Baud_Control WD_On 0 or there is a delay in DP_Control WD_On 1 depending on the enabled response time monitoring WD_On 0 SPC3 Hardware Description V1 3 Page 25 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S 6 PROFIBUS DP Interface 6 1 DP_Buffer Structure The DP mode is enabled in the SPC3 with DP Mode 1 see mode Registero In this process the following SAPS are fixed reserved for the DP mode Default SAP Data exchange Write_Read_Data SAP53 reserved SAP55 Changing the station address Set_Slave_Address SAP56 Reading the inputs Read_Inputs SAP57 Reading the outputs Read_Outputs SAP58 Control commands to the DP Slave Global_Control SAP59 Reading configuration data Get Config SAP60 Reading diagnostics information Slave_Diagnosis SAP61 Sending parameter setting data Set_Param SAP 2 Checking configuration data Check Config The DP Slave protocol is completely integrated in the SPC3 and is handled independently The user must correspondingly parameterize the ASIC and process and acknowledge transferred messages Except for the default SAP SAP56 SAP57 and SAP58 all SAPS are always enabled The remaining SAPS are not enabled until the the DP Slave Machine DP_SM goes into the DATA EX state The user has the possibility of disabling SAP55 The relevant buffer pointer R SSA Puf Pir must be set to OOH for this purpose
31. Center 7 1 4 Application with the 80 C 32 5jek SPC3 48 MHz MIK Boj XINTIMOT CLK pl p uC Pxx 36 RESET XHOLDT pA13 P5 3k3 loj xcs XREADY CJ P5 3k3 23 MODE AB10 p10 1k Hm uc 24 ALE xINT PX A TE gt T XWR 24 XWR ES XRD 4 XRD P5 3k3 340 XTESTO XCTS A 1K P5 3k3 350 XTEST1 5Vor 3 DIVIDER FAD SH RXD RS485 GND RTS 27 RTS RS485 gt AB8 44 10 TXD 26 TXD RS485 gt 43 4 A 5 0 11 ADBO 40 3 11 12 ADB1 1 6 37 4 2 15 ADB2 42 5 z o 2 16 ADB 32 e 4 19 ADB4 ADB 8 15 31 17 5 20 ADB5 M T 29 8 6 21 ADB6 M me 25 10 zl 22 ADB7 pB 0 7 The pull up pull down resistances in the drawing above are only relevant for a in circuit tester The internal chip select logic is activated when the address pins A 11 A 15 are set to 0 In the example above the starting address of the SPC3 is set to 0x1000 lt Processor ALE ADO 7 1 5 kByte RA inthe SPC 3 A8 10 A11 15 SPC3 Hardware Description V1 3 Page 41 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S 7 1 5 Application with th 80 C 165
32. FIBUS Interface Center 5 4 Watchdog Timer 5 4 1 Automatic Baud Rate Identification The SPC3 is able to identify the baud rate automatically The baud search state is located after each RESET and also after the watchdog WD timer has run out in the Baud_Control_ state As a rule SPC3 begins the search for the set rate with the highest baud rate If no SD1 telegram SD2 telegram or SD3 telegram was received completely and without errors during the monitoring time the search continues with the next lowest baud rate After identifying the correct baud rate SPC3 switches to the Baud Control state and monitors the baud rate The monitoring time can be parameterized VVD Baud Control Val The watchdog works with a clock of 100 Hz 10 msec The watchdog resets each telegram received with no errors to its own station address If the timer runs out SPC3 again switches to the baud search state 5 4 2 Baud Rate Monitoring The located baud rate is constantly monitored in Baud Control The watchdog is reset for each error free telegram to its own station address The monitoring time results from multiplying both WD_Baud_Control_Val user sets the parameters by the time base 10 ms If the monitoring time runs out WD_SM again goes to Baud_Search If the user carries out the DP protocol DP_Mode 1 see Mode register 0 with SPC3 the watchdog is used for the DP Control state after a Set Param telegram was
33. S Interface Center 7 1 6 Interface Signals 7 2 UART 7 3 ASIC Test 8 TECHNICAL DATA 8 1 Maximum Limit Values 8 2 Permitted Operating Values 8 3 DC Specifikation of the I O Drivers 8 4 AC Specification for the Output Drivers 8 5 Timing Characteristics 8 5 1 SYS Bus Interface 8 5 2 Timing in the Synchronous C32 Mode 8 5 3 Timing in the Asynchronous Intel Mode X86 Mode 8 5 4 Timing in the Synchronous Motorola Mode E_Clock Mode for example 68HC11 8 5 5 Timing in the Asynchronous Motorola Mode for example 68HC16 8 5 6 Serial Bus Interface 8 5 7 Housing 8 5 8 Processing Instructions 9 PROFIBUS INTERFACE 9 1 Pin Assignment 9 2 Example for the RS 485 Interface 10 APPENDIX 10 1 Addresses 10 2 General Definition of Terms 10 3 Ordering of ASICs 10 3 1 SPC3 AMI 10 3 2 SPC3 ST 11 APPENDIX A DIAGNOSTICS PROCESSING IN PROFIBUS DP 11 1 Introduction 11 2 Diagnostics Bits and Expanded Diagnostics 11 2 1 STAT DIAG 11 2 2 ENT DIAG 11 2 3 ENT DAG OVERFLOW 11 3 Diagnostics Processing from the System View 12 APPENDIX B USEFUL INFORMATION 12 1 Data format in the Siemens PLC SIMATIC SPC3 Hardware Description V1 3 Copyright C Siemens AG 2003 All rights reserved 43 43 43 44 44 44 44 57 57 58 59 59 60 60 60 64 64 Page 5 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S Page 6 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights rese
34. SIMATIC NET SPC3 Siemens PROFIBUS Controller Hardware Description Date 2003 04 09 SIEMENS SIMATIC NET SPC3 Hardware Description Siemens PROFIBUS Controller according to IEC 61158 Version 1 3 Date 2003 04 PROFIBUS Interface Center Page 2 2003 04 SPC3 SIEMENS Liability Exclusion We have tested the contents of this document regarding agreement with the hardware and software described Nevertheless there may be deviations and we don t guarantee complete agreement The data in the document is tested periodically however Required corrections are included in subsequent versions We gratefully accept suggestions for improvement Copyright Copyright Siemens AG 2003 All Rights Reserved Unless permission has been expressly granted passing on this document or copying it or using and sharing its content are not allowed Offenders will be held liable All rights reserved in the event a patent is granted or a utility model or design is registered Subject to technical changes V1 3 SPC3 Hardware Description Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center Versions Release Date Changes V1 1 12 23 99 Chapter 8 2 Current consumption without bus accesses Chapter 10 1 Contact persons V 1 2 09 25 02 Included the specification of the different manufacturers in Chap 8 1 8 3 8 5 and 10 3 Order numbers chap 10 1 contact persons V1 3 2003 04 Incl
35. Temperate Tou S qo f 1 q EE Tabel 8 1 Maximum Limit Values 8 2 Permitted Operating Values Parameter Designation Min S Max EE EE wues Lens ane enee tj Sunny votes oo JU as M q P oss f es CT Input High Voltage Vec 0 7 Voo o7Vo ka Vo v EE EE input igh Vonage erue e FA oa woo a 7 input Low Voltage Va Vuc g e 1 ka ka v EE a a JI input High Votage Vv a a 2 v input Low Voltage V Vae o7 o6 ka ra v Hysteresis Voltage Vv oa ra ka ma v Tabel 8 2 Permitted Operating Values 8 3 DC Specifikation of the VO Drivers Parameter ___ Design _ ___Conditien JE Nin esp linit po LAMIE Vers AMI Vers AMI Vers ST Vers Output High Voltage Von Voo 45V KA Voo05 Vop 05 ka ka Suput Figh Vonage va Worcs o e Cea Output Low Voltage Vo _ Von 4 5V ka ka ka or 04 v Output Low Voltage Vo Voo 4 5V KA KA ka 055 o4 v at an output load of 4mA at an output load of 8mA Page 44 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center Tabel 8 3 DC Specifikation of the VO Drivers po AM Vers AMI Vers AMI Vers ST Vers Input capacity EIN nc E s 70 ne ne p EE capacity COUT ne ne 5 f 0 ne fne f p Co nce oe IS 10 nc nc pF C J Tabel 8 4 Capacity of the I O drivers
36. acknowledge register The SPC3 has a common interrupt output The integrated Watchdog Timer is operated in three different states Baud Search Baud_Control and DP_Control The Micro Sequencer MS controls the entire process Procedure specific parameters buffer pointer buffer lengths station address etc and the data buffer are contained in the integrated 1 5kByte RAM that a controller operates as Dual Port RAM In UART the parallel data flow is converted into the serial data flow or vice versa The SPC3 is capable of automatically identifying the baud rates 9 6 kBd 12 MBd The Idle Timer directly controls the bus times on the serial bus cable Page 8 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center 3 Pin Description The SPC3 has a 44 pin PQFP housing with the following signals Signal Name In Out Source Destination EE ee een C165 Mode CS Signal CPU 800165 i low potential means divided through 4 SS DEENEN 7 CLKOUT2 4 TI O Clockpulsedividedby2or4 sd Systems CPU XINT MOT lt log gt 0 Intel interface System fe ener lt log gt 1 Motorola interface 8 XINT O Untemg PU Interrupt Contr I C165 mode address bus C165 Mode Data address bus separated 13 XDATAEXCH __ O Data Exchange state for PROFIBUSDP I n JI 14 JXREADYIKDTACK O Readyfor external CPU System CPU DB2 IOC Data bus C3
37. ad Output Telegram before the first data cycle 6 2 5 2 Reading Inputs SPC3 sends the input data from the D buffer Prior to sending SPC3 fetches the Din buffer from N to D If no new buffer is present in N there is no change The user makes the new data available in U With the Nevv Din buffer Cmd the buffer changes from U to N If the users preparation cycle time is shorter than the bus cycle time not all new input data are sent but just the most current At a 12 Mbd baud rate it is more probable however that the user s preparation cycle time is larger than the bus cycle time Then SPC3 sends the same data several times in succession During start up SPC3 first goes to DATA EX after all parameter telegrams and configuration telegrams are acknowledged and the user then makes the first valid Din buffer available in N with the New_Din_Buffer_Cmd If Diag Freeze_Mode 1 there is no buffer change prior to sending The user can read the status of the state machine cell with the following codings for the four states Nil Dout_Puf_Ptr1 3 See Figure 3 13 The pointer for the current data is in the N state Page 34 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center Address Bit Position Designation Control 7 5 4 3 2 Register 1 D Din BuffelSM X Xe Xt x2 1
38. be parameterized f e in the parameterization telegram only available from version Step C When using a big number of parameters to be transmitted from the PROFIBUS Master to the slave the Auxiliary buffer Ve has to have the same size like the Parameterization buffer Sometimes this could reach the limit of the available memory space in the SPC3 When Spec_Prm_Puf_Mode 1 the parameterization data are processed directly in this special buffer and the Auxiliary buffers can be held compact SPC3 Hardware Description V1 3 Page 17 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S Bit 0 DIS_START_CONTROL Monitoring the following start bit in UART Set Param Telegram overwrites this memory cell in the DP mode Refer to the user specific data 0 Monitoring the following start bit is enabled 1 Monitoring the following start bit is switched off Bit 1 DIS_STOP_CONTROL Stop bit monitoring in UART Set Param telegram overwrites this memory cell in the DP mode Refer to the user specific data 0 Stop bit monitoring is enabled 1 Stop bit monitoring is switched off Bit 2 EN FDL DDB Reserved 0 The FDL_DDB receive is disabled Bit 3 MinTSDR Default setting for the MinTSDR after reset for DP operation or combi operation 0 Pure DP operation default configuration 1 Combi operation Bit 4 INT POL N Polarity of the interrupt output O The interrupt output is low a
39. changed at the last received Global Control telegram SPC3 additionally generates the New GC Command interrupt During initialization SPC3 presets the R GC Command RAM cell with OOH The user can read and evaluate this cell So that Sync and Freeze can be carried out these functions must be enabled in the mode register 6 2 7 Read Inputs SAP56 SPC3 fetches the input data like it does for the VVrite Read Data Telegram Prior to sending N is shifted to D if new input data are available in N For Diag Freeze Mode 1 there is no buffer change 6 2 8 Read Outputs SAP57 SPC3 fetches the output data from the Dout buffer in U The user must preset the output data with 0 during start up so that no invalid data can be sent here If there is a buffer change from N to U through the Next_Dout_Buffer_Cmd between the first call up and the repetition the new output data is sent during the repetition 6 2 9 Get_Config SAP59 The user makes the configuration data available in the Read_Cfg buffer For a change in the configuration after the Check_Config telegram the user writes the changed data in the Cfg buffer sets EN Change Co buffer 1 see Mode Register1 and SPC3 then exchanges the Cfg buffer for the Read_Cfg buffer See Section 3 2 3 If there is a change in the configuration data for example for the modular DP systems during operation the user must return with Go Offline see Mod
40. ctive 1 The interrupt output is high active Bit 5 EARLY_RDY Moved up ready signal O Ready is generated when the data are valid read or when the data are accepted write 1 Ready is moved up by one clock pulse Bit 6 Sync_Supported Sync_Mode support O Sync_Mode is not supported Bit 7 Freeze_Supported Freeze Mode support O Freeze_Mode is not supported Freeze Mode is supported Bit 8 DP_MODE N DP Mode enable O DP Modeis disabled 1 DP Modeis enabled SPC3 sets up all DP SAPs Bit 9 EOI Time base Time base for the end of interrupt pulse O The interrupt inactive time is at least 1 usec long 1 The interrupt inactive time is at least 1 ms long O The User_Time_Clock Interrupt occurs every 1 ms 1 The User Time Clock Interrupt occurs every 10 ms Bit10 JUser Time base Time base for the cyclical User Time Clock Interrupt O The WD runs in the function mode 1 Not permitted Bit 12 O No special parameter buffer 1 Special parameter buffer mode Parameterization data will be stored directly in the special parameter buffer Bit 13 Special Clear Mode Fail Safe Mode O No special clear mode 1 Special clear mode SPC3 will accept datea telegramms with data unit 0 Figure 5 1 Mode Register 0 Bit 12 0 can be written to can be changed in offline only Page 18 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Cent
41. d In addition to the Ext_Diag_Data the buffer length also includes the SPC3 diagnostics bytes R_Len_Diag_Puf1 R_Len_Diag_Puf2 6 2 5 Write_Read_Data Data_Exchange Default_SAP 6 2 5 1 Writing Outputs SPC3 reads the received output data in the D buffer After error free receipt SPC3 shifts the newly filled buffer from D to N In addition the DX_Out_Interrupt is generated The user now fetches the current output data from NI The buffer changes from N to U with the Next_Dout_Buffer_Cmd so that the current data of the application can be sent back for the master s Read Outputs If the user s evaluation cycle time is shorter than the bus cycle time the user does not find any new buffers with the next Next Dout Butter Cmd in N Therefore the buffer exchange is omitted At a 12 Mbd baud rate it is more likely however that the user s evaluation cycle time is larger than the bus cycle time This makes new output data available in N several times before the user fetches the next buffer It is guaranteed however that the user receives the data last received For Power_On Leave_Master and the Global Control Telegram Clear SPC3 deletes the D buffer and then shifts it to N This also takes place during the power up entering into Wait_Prm If the user fetches this buffer he receives the U_buffer cleared display during the Next_Dout_Buffer_Cmd
42. d off in the SPC3 The CS signal is fed to SPC3 e For microcontrollers with chip select logic K F1 HC16 and HC916 the chip select signals are programmable as regards the address range the priority the polarity and the window width in the write cycle or read cycle For microcontrollers without chip select logic N and M and others an external chip select logic is required This means additional hardware and a fixed assignment Condition e The SPC3 output clock CLKOUT2 4 must be four times larger than the E CLOCK The SPC3 input clock CLK must be at least 10 times larger than the desired system clock E_Clock The divider pin must be placed at low divider 4 and it results in an E CLOCK of 3 MHz Motorola microcontroller with the following characteristics e Asychronous bus timing with evaluation of the XREADY signal e 8 bit non multiplexed bus DB7 0 AB10 0 The following can be connected e HC16 and HC916 types e All other HC11 types with a multiplexed bus must externally select addresses AB7 0 from data DB7 0 The address decoder is switched off in SPC3 The CS signal is fed into SPC3 e Chip select logic is available and programmable in all microcontrollers Intel microcontroller CPU basis is 80C51 52 32 microcontrollers from various manufacturers e Sychronous rigid bus timing without evaluation of the XREADY signal e 8 bit multiplexed bus ADB7 0 The following can be connected e Microcontroller
43. e Register1 to Wait_Prm to SPC3 Page 36 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center 7 Hardware Interface 7 1 Universal Processor Bus Interface 7 1 1 General Description SPC3 has a parallel 8 bit interface with an 11 bit address bus SPC3 supports all 8 bit processors and microcontrollers based on the 80C51 52 80C32 from Intel the Motorola HC11 family as well as 8 16 bit processors or microcontrollers from the Siemens 80C166 family X86 from Intel and the HC16 and HC916 family from Motorola Because the data formats from Intel and Motorola are not compatible SPC3 automatically carries out byte swapping for accesses to the following 16 bit registers interrupt register status register and mode register0 and the 16 bit RAM cell R User VVd Value This makes it possible for a Motorola processor to read the 16 bit value correctly Reading or writing takes place as usual through two accesses 8 bit data bus Due to the 11 bit address bus SPC3 is no longer fully compatible to SPC2 10 bit address bus However AB 10 is located on the XINTCI output of the SPC2 that was not used until now For SPC3 the AB 10 input is provided with an internal pull down resistor If SPC3 is to be connected into existing SPC2 hardware the user can use only 1 kByte of the internal RAM Otherwise the AB 10 cable on the modules must be moved to the
44. er 5 1 2 Mode Register 1 Mode REG1 writable Some control bits must be changed during operation These control bits are combined in Mode Register 1 and can be set independently of each other Mode_Reg_S or can be deleted independently of each other Mode_Reg_R Various addresses are used for setting and deleting Log 1 must be written to the bit position to be set or deleted Address Bit Position Control 7 5 4 3 2 1 Register 08H Res_ EN_ User_ Do EOI START_ Mode Reg_S User_WD Change Leave_ Offline SPC3 7 0 E Cfg Master Sp Puffer 09H Res EN User_ Do EOI START_ Mode Reg_R User_WD Change Leave_ Offline SPC3 7 0 Cfg_ Master Puffer Bito START_SPC3 Exiting the Offline state 1 SPC8 exits offline and goes to passive idle In addition the idle timer and Wd timer are started and Go_Offline 0 is set Bit 1 EOI End of Interrupt 1 End of Interrupt SPC3 switches the interrupt outputs to inactive and again sets EOI to log 0 Bit 2 Go_ Offline Going into the offline state sets Go_Offline to log 0 Bit 3 User_Leave_Master Request to the DP_SM to go to VVait Prm 1 The user causes the DP SM to go to VVait Prm After this action SPC3 sets User Leave Master to log 0 Bit 4 O Mith User Cig Data Okay Cmd the Cfg buffer may not be exchanged for the Read Cig buffer 1 With User Co Data Okay Cmd the Cfg buffer must be exchanged for the Read Cig buffer Bit 5 Res User VVd Resetting
45. families from Intel Siemens and Philips for example The address decoder is switched on in SPC3 The CS signal is generated for SPC3 internally e The lower address bits AB7 0 are stored with the ALE signal in an internal address latch The internal CS decoder is activated in SPC3 that generates its own CS signal from the AB10 0 addresses The internal address decoder is fixed wired so that SPC3 must always be addressed under the fixed addresses AB7 0 00000xxxb SPC3 selects relevant address window from the AB2 0 signals In this mode the CS Pin XCS must be located at VDD high potential Intel and Siemens 16 8 bit microcontroller families e Asychronous bus timing with evaluation of the XREADY signal e 8 bit non multiplexed bus DB7 0 AB10 0 e Microcontroller families from Intel x86 and Siemens 80C16x for example Address decoder is switched off in SPC3 The CS signal is fed in to the SPC3 e External address decoding is always necessary e External chip select logic if the microcontroller is not present Figure 7 1 Bus Interface Page 38 2003 04 V1 3 SPC3 Hardware Description Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center 7 1 3 Switching Diagram Principles
46. fer_Changed Interrupt When the buffers are exchanged the internal Diag_Flag is also set For an activated Diag Flag SPC3 responds during the next Write_Read_Data with high priority response data that signal the relevant master that new diagnostics data are present at the slave Then this master fetches the new diagnostics data with a Slave_Diagnosis telegram Then the Diag_Flag is reset again If the user signals Diag Stat_Diag 1 however static diagnosis see the structure of the diagnostics buffer then Diag_Flag still remains activated after the relevant master has fetched the diagnosis The user can poll the Diag_Flag in the status register to find out whether the master has already fetched the diagnostics data before the old data is exchanged for the new data Status coding for the diagnostics buffers is stored in the Diag_bufferSM processor parameter The user can read this cell with the possible codings for both buffers User SPC3 or SPC3 Send Mode Address Bit Position Designation Control ee oj OCH o 0 DPufa D Puf Diag Puffer SM ea el ae See below for coding 0 0 Eachforthe D Buf2orD Bufi PO 1 User IT 1 0 SP3 i Figure 6 8 Diag_Buffer Assignment The Nevv Diag Cmd is also a read access to a defined processor parameter with the signal as to which diagnostics buffer belongs to the user after the exchange or whether both buffers are currently
47. gister The user must make a retentive memory possibility available for example EEPROM to support this utility It must be possible to store the station address and the Real No Add Change True FFH parameter in this external EEPROM After each restart caused by a power failure the user must again make these values available to SPC3 in the R_TS_Adr und R_Real_No_Add_Change RAM register If SAP55 is enabled and the Set_Slave_Address telegram is correctly accepted SPC3 enters all net data in the Aux Puffer1 2 exchanges the Aux buffer1 2 for the SSA buffer stores the entered data length in R_Len_SSA_Data generates the New_SSA_ Data interrupt and internally stores the new station address and the new Real No Add Change parameter The user does not need to transfer this changed parameter to SPC3 again After the user has read the buffer the user generates the SSA Puffer Free Cmd read operation on address 14H This makes SPC3 again ready to receive an additional Set Slave Address telegram such as from another master SPC3 reacts independently when there are errors Address Bit Position Designation regi ITT Ee Ae of of of o TD SSA Putter Free Grd SSA_Puffer_Free_Cmd don t care Figure 6 3 Coding SSA Buffer Free Cmd 6 2 1 2 Structure of the Set Slave Address Telegram The net data are stored as follovvs in the SSA buffer Byte Bit Position Designation BESCH SEE ARSENE DI
48. gnostics The user specific diagnostics can be filed in three different formats Device Specific Diagnostics The diagnostics information can be coded as required PBK Bit jBitso __ S O Header Byte o Oo Block length in bytes including header Diagnostics Field Coding of diagnostics is device specific Can be specified as required SPC3 Hardware Description V1 3 Page 61 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S Identifier Related Diagnostics For each identifier byte assigned during configuration for example O x 10 for 1 byte input a bit is reserved In the case of a modular system with an identifier byte each per module module specific diagnostics can be indicated One bit respectively will then indicate diagnostics per module LEIT Bte _ Bit 5 0 MO eee eee Header Byte CSC Block length in bytes including header Bit Structure EE ft Identifier Byte 7 has etc ft Identifier Byte 0 has diagnostics diagnostics Channel Related Diagnostics In this block the diagnosed channels and the diagnostics cause are entered in sequence Three bits are required per entry Sd Bte Bit5 JBit4 0 Header Byte E Identification Number Input Output Channel Type Error Type Coding of the error type is in part manufacturer specific other codings are specified in the Standard Example 10 0 00 jo jt 0 0 Device related diagnostics
49. i me X INT D EOI a After acknowledging an interrupt with EO1 a min of 1 us or 1 ms is expected in SPC3 before a new interrupt is output Page 46 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center Reset SPC3 requires a minimum of 400 clock pulse cycles during the reset phase so that it can be reset correctly Reset 8 5 2 Timing in the Synchronous C32 Mode If SPC3 is operated at 48MHz an 80C32 with a maximum clock pulse rate of 20MHZz can be connected In the C32 mode SPC3 saves the least significant addresses with the negative edge of ALE At the same time SPC3 expects the more significant address bits on the address bus SPC3 generates a chipselect signal from the more significant address bits The request for an access to SPC3 is generated from the negative edge of the read signal and from the positive edge of the write signal BES Address to ALE J Setuptime Address ABs 15 Holdtime after XRD T or XWR T XRD J to Data Out Zugriff auf RAM AT 5 3T442 5 88 3 105 XRD J to Data Out Zugriff auf die Register AT 18 4T 20 2 101 3 103 5 ALE J to XRD J Data Holdtime after XRD T 6 10 2 Data Holdtime after XWR T Data Setuptime to XWR T XRD to ALE T XRD Pulse Width XW R Pulse Width Address Holdtime after ALE 1 ALE Puls Width XRD XWR Cycletime ALE J to XWR 4 XWR to ALE T Explanations T Clock p
50. ics information and the user specific information can be evaluated After eliminating the current diagnostics situation this can be signalled as a status message from the slave without setting the external diagnostics bit With the COM ET200 a comfortable diagnostics tool is available on line At the present time identification related diagnostics information can be displayed with it in plain text In later phases channel related diagnostics will also be supported User specific diagnostics are only displayed if the EXT_DIAG bit is set The figure below shows a screen during data processing for example Set Program File C PNO4 ET 200 SIMATIC S5 COM ET 200 SINGLE DIAGNOSTICS Station Number 30 Station Type ET 200U COMBI Station Designation Station4 Station Status Slave not ready for data exchange External diagnostics Configuration error Device Related Diagnostics Identification Related Diagnostics In the type file for the COM ET200 and in the GSD device master data file fields are already provided for referencing device specific bits and pertinent plain text messages for example Bit 7 1 have had it good night SPC3 Hardware Description V1 3 Page 63 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S 12 Appendix B Useful Information 12 1 Data format in the Siemens PLC SIMATIC The SPC3 always sends data from the beginning of the buffer till the end
51. ieldbus Message Specification MS MicroSequenzer SM State Machine 10 3 Ordering of ASICs For Ordering SPC3 ASICs please refer to your contact person in the Siemens local branch office and use one of the ordering numbers depending on the amount you want to order 10 3 1 SPC3 AMI ASIC SPC 3 6ES7 195 OBD02 0XA0 Small amount 5 STEP C 6ES7 195 0BD12 0XA0 Single Tray 96 6ES7 195 0BD22 0XA0 Tray Box 576 6ES7 195 0BD32 0XA0 8 Tray Box 4608 6ES7 195 0BD42 0XA0 17 Tray Box 9792 10 3 2 SPC3 ST ASIC SPC 3 6ES7 195 0BD01 0XA0 Kleinverpack 5 STEP C 6ES7 195 0BD11 0XA0 Einzel Tray 96 6ES7 195 0BD21 0XA0 Tray Box 576 6ES7 195 0BD31 0XA0 8 Tray Box 4608 6ES7 195 0BD41 0XA0 17 Tray Box 9792 Page 60 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center 11 Appendix A Diagnostics Processing in PROFIBUS DP 11 1 Introduction PROFIBUS DP offers a convenient and multi layer possibility for processing diagnostics messages on the basis of error states As soon as a diagnostics request is required the slave will respond in the current data exchange with a high priority reply message In the next bus cycle the master then requests a diagnostics from this slave instead of executing normal data exchange Likewise any master not only the assigned master can request a diagnostics from the slave The diagnostics information of the DP slave consists of standa
52. in 4 Request to send RTS Pin 5 Ground 5V M5 Pin 6 Potential 5V floating P5 Pin 7 Free Pin 8 A line Pin 9 Free The cable shield must be connected to the plug connector housing The free pins are described as optional in EN 50170 Vol 2 If used they should conform to the specifications in DIN192453 CAUTION The designations A and B of the lines on the plug connector refer to the designations in the RS 485 standard and not the pin designation of driver ICs Keep the cable from driver to connector as short as possible Use of higher baud rates i e 3 to 12 Mbaud requires the use of new plug connectors These connectors compensate for line interferences on all possible combinations of cables 6ES7 972 0BB10 0XA0 with PG socket 6ES7 972 0BA10 0XA0 without PG socket SPC3 Hardware Description V1 3 Page 57 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S 9 2 Example for the RS 485 Interface 2M r a A o x 5 sz 0 Qs 2 2E 5 2 8 2G ES ES D aa D 2 0 Important electrical isolation to bus P5 and 2P5 Layout lines must be kept as short as possible 74HC132 2 2 22nF 500 V HCPLO601 7721 0721 HCPL7101 HCPL7101 Explanations of the circuitry The bus driver input EN2 has to be connected to low potential to ensure that after transmission of a telegram the ASIC is able to listen
53. inter can be positioned at any segment in the memory Therefore all buffers must always be located at the beginning of a segment If the SPC3 carries out a DP communication the SPC3 automatically sets up all DP SAPs The various telegram information is made available to the user in separate data buffers for example parameter setting data and configuration data Three change buffers are provided for data communication both for the output data and for the input data A change buffer is always available for communication Therefore no resource problems can occur For optimal diagnostics support SPC3 has two diagnostics change buffers into which the user inputs the updated diagnostics data One diagnostics buffer is always assigned to SPC3 in this process The bus interface is a parameterizable synchronous asynchronous 8 bit interface for various Intel and Motorola microcontrollers processors The user can directly access the internal 1 5k RAM or the parameter latches via the 11 bit address bus After the processor has been switched on procedural specific parameters station address control bits etc must be transferred to the Parameter Register File and to the mode registers The MAC status can be scanned at any time in the status register Various events various indications error events etc are entered in the interrupt controller These events can be individually enabled via a mask register Acknowledgement takes place by means of the
54. its are changed and there is branching to Wait_Prm For a correct configuration the transition to DATA_EX takes place immediately if no Din_buffer is present R_Len_Din_Puf OOH and trigger counters for the parameter setting telegrams and configuration telegrams are at 0 Otherwise the transition does not take place until the first New_DIN_Puffer_Cmd with which the user makes the first valid N buffer available When entering into DATA_EX SPC3 also generates the Go Leave_Data_Exchange Interrupt If the received configuration data from the Cfg buffer are supposed to result in a change of the Read Cfg buffer the change contains the data for the Get_Config telegram the user must make the new Read_Cfg data available in the Read Cfg buffer before the User_Cfg_Data_Okay_Cmd acknowledgement After receiving the acknowledgement SPC3 exchanges the Cfg buffer with the Read Cig buffer if EN Change Co buffer 1 is set in mode register During the acknowledgement the user receives information about whether there is a conflict or not If an additional Check_Config telegram was supposed to be received in the meantime the user receives the Cfg_Conflict signal during the acknowledgement of the first Check_Config telegram whether positive or negative Then the user must repeat the validation because SPC3 has made a new Cfg buffer available The User_Cfg_Data_Okay_Cmd and User Cig Data Not Oka
55. on for more than seven data bytes SPC3 carries out the following reaction among others SPC3 exchanges Aux Puffer1 2 all data bytes are input here for the Prm buffer stores the input data length in R_Len_Prm_Data and triggers the New_Prm_Data Interrupt The user must then check the User_Prm_Data and either reply with the User_Prm_Data_Okay_Cmd or with User_Prm_Data_Not_Okay_Cmd The entire telegram is input in the buffer that is application specific parameter data are stored beginning with data byte 8 only The user response User_Prm_Data_Okay_Cmd or User_Prm_Data_Not_Okay_Cmd again takes back the New_Prm_Data interrupt The user may not acknowledge the New_Prm_Data interrupt in the IAR register The relevant diagnostics bits are set with the User_Prm_Data_Not_Okay_Cmd message and are branched to Wait_Prm The User_Prm_Data_Okay and User_Prm_Data_Not_Okay acknowledgements are reading accesses to defined registers with the relevant signals e User_Prm_Finished No additional parameter telegram is present e Prm Conllict An additional parameter telegram is present processing again e Not Allowed Access not permitted in the current bus state Page 30 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center Address Bit Position Designation HN AKSES ESE Registe
56. ower up the user must also set Res User VVd 1 so that the User VVd Timer is even set at its parameterized value 6 2 6 Global Control SAP58 SPC3 itself processes the Global Control Telegrams in the manner already described In addition this information is available to the user The first byte of a valid Global Control command is stored in the R GC Comand RAM cell The second telegram byte Group Select is processed internally Address Bit Position Designation RAM 4 3 2 Cell 3CH Sync Un Freeze Un Clear_ R_GC_Command sync freeze Data SPC3 Hardware Description V1 3 Page 35 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S 0 Reserved JI WESSEN Clear Data With this command the output data is deleted in D and is changed to N With Unfreeze freezing input data is cancelled 3 Freeze The input data is fetched from N to D and frozen New input data is not fetched again until the master sends the next Freeze command 5 Sync The output data transferred with a WRITE_READ_DATA telegram is changed from D to N The following transferred output data is kept in D until the next Sync command is given 6 7 Reserved The Reserved designation specifies that these bits are reserved for future function expansions Figure 6 15 Data Format for the Global Control Telegram If the Control Comand byte
57. pyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S CPD CMOS with pull down TS TTLt Schmitt trigger Page 10 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center 4 Memory Allocation 4 1 Memory Area Distribution in the SPC3 The figure displays the division of the SPC3 1 5k internal address area The internal latches register are located in the first 21 addresses The internal latches register either come from the controller or influence the controller Certain cells can be only read or written The internal work cells to which the user has no access are located in RAM at the same addresses The organizational parameters are located in RAM beginning with address 16H The entire buffer structure for the DP SAPS is written based on these parameters In addition general parameter setting data station address Ident no etc are transferred in these cells and the status displays are stored in these cells global control command etc Corresponding to the parameter setting of the organizational parameters the user generated buffers are located beginning with address 40H All buffers or lists must begin at segment addresses 48 bytes segmentation 000H Processor parameters internal vvork cells Latches register 22 bytes 016H SE parameters 42 bytes 040H ES buffer Data In 3 Data Out
58. r OEH polo o o jt U UserPrmDataOkay 0 0 User Prm Finished O 1 PRM Conflict Address Bit Position Designation Control A ci OFH po of oto 4 U User Prm_Data Not Okay 0 0 User Prm Finished 0 1 PRM Conflict Figure 6 6 Coding User_Prm_Data_Not _Okay_Cmd If an additional Set Param telegram is supposed to be received in the meantime the signal Prm_Conflict is is returned for the acknowledgement of the first Set_Param telegram whether positive or negative Then the user must repeat the validation because the SPC3 has made a new Prm buffer available 6 2 3 Check Config SAP62 The user takes on the evaluation of the configuration data After SPC3 has received a validated Check_Config Telegram SPC3 exchanges the Aux Puffer1 2 all data bytes are entered here for the Cfg buffer stores the input data length in R_Len_Cfg Data and generates New_Cfg_Data Interrupt The user must then check the User_Config_Data and either respond with User Cig Data Okay Cmd or with User_Cfg_Data_Not_Okay_Cmd acknowledgement to the Cfg_SM The net data is input in the buffer in the format regulation of the standard The user response User Cfg Data Okay Cmd or the User Cfg Data Not Okay Cmd response again takes back the New Cfg Data interrupt and may not be acknowledged in the IAR If an incorrect configuration is signalled back various diagnostics b
59. rd diagnostics information 6 bytes and can be supplemented by user specific diagnostics information In the case of the ASICs SPM2 and LSPM2 extensive diagnostics is possible through corresponding wiring In the case of the intelligent SPCx solution adapted and convenient diagnostics processing can be carried out through programming 11 2 Diagnostics Bits and Expanded Diagnostics Parts of the standard diagnostics information are permanently specified in the firmware and in the micro program of the ASICs through the state machine Request diagnostics only once update_diag if an error is present or changes By no means should diagnostics be requested cyclically in the data exchange state otherwise the system will be burdened by redundant data Three information bits can be influenced by the application 11 2 1 STAT DIAG Because of a state in the application the slave can t make valid data available Consequently the master only requests diagnostics information until this bit is removed again The PROFIBUS DP state is hovvever Data Exchange so that immediately after the cancellation of the static diagnostics data exchange can start Example failure of supply voltage for the output drivers 11 2 2 EXT_DIAG If this bit is set a diagnostics entry must be present in the user specific diagnostics area If this bit is not set a status message can be present in the user specific diagnostics area User Specific Dia
60. received with an enabled response time monitoring WD_On 1 The watchdog timer remains in the baud rate monitoring state when there is a switched off WD_On 0 master monitoring The PROFIBUS DP state machine is also not reset when the timer runs out That is the slave remains in the DATA_EXchange state for example 5 4 3 Response Time Monitoring The DP Control state serves response time monitoring of the DP master Master Add The set monitoring times results from multiplying both watchdog factors and multiplying the result with the momentarily valid time base 1 ms or 10 ms Twp 1 ms or 10 ms WD_Fact_1 WD_Fact_2 See byte 7 of the parameter setting telegram The user can load the two watchdog factors VVD Fact 1 and WD Fact 2 and the time base that represents a measurement for the monitoring time via the Set_Param telegram with any value between 1 and 255 EXCEPTION The WD_Fact_1 WD_Fact_2 1 setting is not permissible The circuit does not check this setting Monitoring times between 2 ms and 650 s independent of the baud rate can be implemented with the permisible watchdog factors If the monitoring time runs out the SPC3 goes again to Baud_Control and the SPC3 generates the WD_DP_Control_Timeout Interrupt In addition the DP State machine is reset that is generates the reset states of the buffer management If another master accepts SPC3 then there is either a switch to
61. rved SI E M E N S SPC3 PROFIBUS Interface Center 1 Introduction For simple and fast digital exchange between programmable logic controllers Siemens offers its users several ASICs These ASICs are based on and are completely handled on the principles of the EN 50170 Vol 2 of data traffic between individual programmable logic controller stations The following ASICs are available to support intelligent slave solutions that is implementations with a microprocessor The ASPC2 already has integrated many parts of Layer 2 but the ASPC2 also requires a processor s support This ASIC supports baud rates up to 12 Mbaud In its complexity this ASIC is conceived primarily for master applications Due to the integration of the complete PROFIBUS DP protocol the SPC3 decisively relieves the processor of an intelligent PROFIBUS slave The SPC3 can be operated on the bus with a baud rate of up to 12 MBaud However there are also simple devices in the automation engineering area such as switches and thermoelements that do not require a microprocessor to record their states There are two additional ASICs available with the designations SPM2 Siemens Profibus Multiplexer Version 2 and LSPM2 Lean Siemens PROFIBUS Multiplexer for an economical adaptation of these devices These blocks work as a DP slave in the bus system according to DIN E 19245 T3 and work with baud rates up to 12 Mbaud A master addresses these blocks by means of Layer 2 of
62. t_Param Telegram for DP One requirement of the PROFIBUS protocol is that no rest states are permitted between the telegram characters The SPC3 transmitter ensures that this specification is maintained This following start bit test is switched off with the parameter setting DIS START CONTROL 1 in mode register 0 or Set_Param telegram for DP Specified by the four fold scan a maximum distortion of the serial input signal of X 47 to y 22 is permissible 7 3 ASIC Test All output pins and I O pins can be switched in the high resistance state via the XTESTO test pin An additional XTEST1 input is provided more information upon request to test the block internally with test automatic devices not in the target hardware environment Pin No Name Function Jl 34 XTESTO VSS GND All outputs high resistance VDD 5V Normal SPC3 function 35 XTEST1 VSS GND VDD 5V Normal SPC3 function Figure 7 3 Test Support XTESTO and XTEST1 must be placed on Von 5V via external pull up resistors SPC3 Hardware Description V1 3 Page 43 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S 8 Technical Data 8 1 Maximum Limit Values Parameter Designation Min We Unit po AMVers ST Vers AMI Vers ST Vers _ Supply Voltage Vp 3 05 6 J 7 V Input Voltage vv os os voos voos v _ EE KA 10 kA ma Storage
63. the 7 layer model After these blocks have received an error free telegram they independently generate the required response telegrams The LSPM2 has the same functions as the SPM2 but the LSPM2 has a decreased number of I O ports and diagnostics ports SPC3 Hardware Description V1 3 Page 7 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S 2 Function Overview The SPC3 makes it possible to have a price optimized configuration of intelligent PROFIBUS DP slave applications The processor interface supports the following processors Intel 80C31 80X86 Siemens 80C166 165 167 Motorola HC11 HC16 HC916 types In SPC3 the transfer technology is integrated Layer 1 except for analog functions RS485 drivers the FDL transfer protocol Fieldbus Data Link for slave nodes Layer 2a a support of the interface utilities Layer 2b some Layer 2 FMA utilities and the complete DP slave protocol USIF User Interface which makes it possible for the user to have access to Layer 2 The remaining functions of Layer 2 software utilities and management must be handled via software The integrated 1 5k Dual Port RAM serves as an interface between the SPC3 and the software application The entire memory is subdivided into 192 segments with 8 bytes each Addressing from the user takes place directly and from the internal microsequencer MS by means of the so alled base pointer The base po
64. the current request the SPC3 has arrived at the offline state through available in the N buffer For a Povver On or for a Leave Master the SPC3 deletes the N buffer and also generates this interrupt For additional functions For additional functions Figure 5 4 Interrupt Request Register IRR Bit 15 0 vvritable and readable SPC3 Hardware Description V1 3 Page 23 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S The other interrupt controller registers are assigned in the bit positions like the IRR Address Register ______ Reset State 02H Interrupt Register Readable All bits deleted ae 03H IR only 04H Interrupt Mask Writable can All bits set Bit Mask is set and the interrupt 05H Register be changed 1 is disabled IMR during Mask is deleted and the operation interrupt is enabled Register during unchanged IAR operation 02H Interrupt Writable can All bits deleted The IRR bit is deleted 03H Acknowledge be changed The IRR bit remains Figure 5 5 Additional Interrupt Registers The New_Prm_Data New_Cfg_Data inputs may not be deleted via the Interrupt Acknowledge Register The relevant state machines delete these inputs through the user acknowledgements for example User_Prm_Data_Okay etc Page 24 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PRO
65. uded the specification of the different manufacturers in Chap 8 1 8 3 8 5 and 10 3 e a SPC3 Hardware Description V1 3 Page 3 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 Directory 1 INTRODUCTION 2 FUNCTION OVERVIEW 3 PIN DESCRIPTION 4 MEMORY ALLOCATION 41 Memory Area Distribution in the SPC3 4 2 Processor Parameters Latches Register 4 3 Organizational Parameters RAM 5 ASIC INTERFACE 5 1 Mode Register 5 1 1 Mode Register 0 5 1 2 Mode Register 1 Mode REG1 writable 5 2 Status Register 5 3 Interrupt Controller 5 4 Watchdog Timer 5 4 1 Automatic Baud Rate Identification 5 4 2 Baud Rate Monitoring 5 4 3 Response Time Monitoring 6 PROFIBUS DP INTERFACE 61 DP Butter Structure 6 2 Description of the DP Services 6 2 1 Set_Slave_Address SAP55 6 2 2 Set Param SAP61 6 2 3 Check_Config SAP62 6 2 4 Slave_Diagnosis SAP60 6 2 5 Write_Read_Data Data Exchange Default SAP 6 2 6 Global Control SAP58 6 2 7 Read Inputs SAP56 6 2 8 Read Outputs SAP57 6 2 9 Get Config SAP59 7 HARDWARE INTERFACE 7 1 Universal Processor Bus Interface 7 1 1 General Description 7 1 2 Bus Interface Unit BIU 74 38 Switching Diagram Principles 7 1 4 Application with the 80 C 32 7 1 5 Application with th 80 C 165 Page 4 V1 3 2003 04 SIEMENS 11 11 13 15 SPC3 Hardware Description Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBU
66. ulse cycle 48MHz TBD to be defined Access to the RAM s Access to the registers latches e for T 48MHz SPC3 Hardware Description V1 3 Page 47 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S Synchronous Intel Mode Processor Read Timing XRD XWR log 1 XWR XRD log 1 Page 48 V1 3 SPC3 Hardware Description 2003 04 Copyright C Siemens AG 2003 All rights reserved SI E M E N S SPC3 PROFIBUS Interface Center 8 5 3 Timing in the Asynchronous Intel Mode X86 Mode In 80X86 operation SPC3 acts like memory with ready logic The access times depend on the type of accesses The request for an access to SPC3 is generated from the negative edge of the read signal or the positive edge of the write signal SPC3 generates the Ready signal synchronously to the fed in pulse The Ready signal is reset when the read signal or write signal is deactivated The data bus is switched to the Tristate with XRD 1 Cid ST Vers Parameter Min vax Min Address Setuptime to RXD 4 or XWR L ns XRD J to Data valid Zugriff auf RAM ST442 5 ns 105 XRD J to Data valid Zugriff auf die Register 47T 20 2 ns 103 5 Address AB o o Holdtime after XRD or XWR T ns XCS J Setuptime to XRD 4 or XWR 4 ns XRD Puls Width ns Data Holdtime after XRD T i i ns Read Write Inactive Time ns XCS Holdtime after XRD T or XWR T ns XRD XWR J to XRDY J Normal Ready ns
67. xi x2 Xt x2 A Dee below for coding DIN Lo 1 Din pu Pti IT 1 0 Din Buf Pra i Figure 6 13 Din_Buffer Management When reading the New_Din_Buffer_Cmd the user gets the information which buffer U buffer belongs to the user after the change Din Buf Pir 1 3 Address Bit Position Designation Control 5 4 3 fal GC 09H IT Po 1 Din But Pari 1 10 Din But Ptr Din Buf E Figure 6 14 Next Din Butter Cmd 6 2 5 3 User Watchdog Timer After power up DATA EX state it is possible that SPC3 continually answers VVrite Read Data telegrams without the user fetching the received Din buffers or making new Dout buffers available If the user processor hangs up the master would not receive this information Therefore a User VVatchdog Timer is implemented in SPC3 This User Wd Timer is an internal 16 bit RAM cell that is started from a R User Wd Value15 0 value the user parameterizes and is decremented with each received VVrite Read Data telegram from SPC3 If the timer attains the 0000hex value SPC3 transitions to the Wait_Prm state and the DP GM carries out a Leave Master The user must cyclically set this timer to its start value Therefore Res User VVd 1 must be set in mode register 1 Upon receipt of the next Write_Read_Data telegram SPC3 again loads the User VVd Timer to the parameterized value H User Wd Value15 0 and sets Res User Wd 0 Mode Register 1 During p
68. y Cmd acknowledgements are read accesses to defined memory cells see Section 2 2 1 with the relevant Not_Allowed User_Cfg_Finished or Cfg_Conflict signals see Figure 3 7 If the New_Prm_Data and New_Cfg_Data are supposed to be present simultaneously during power up the user must maintain the Set_Param and then the Check_Config acknowledgement sequence SPC3 Hardware Description V1 3 Page 31 Copyright C Siemens AG 2003 All rights reserved 2003 04 PROFIBUS Interface Center SPC3 SI E M E N S Address Bit Position Designation Control GE Ee Lo lo o o jt U User Cfg Data Okay 0 0 User Cfg Finished Lo 1 Cfg Conflict Address Bit Position Designation Control EECH Lo ojo oj jo o jt User Cig Data Not Okay 1 0 0 User Cfg Finished Lo 1 Cfg Conflict JT Figure 6 7 Coding of the User_Cfg_Data_Not _Okay_Cmd 6 2 4 Slave_Diagnosis SAP60 6 2 4 1 Diagnostics Processing Sequence Two buffers are available for diagnostics The two buffers can have varying lengths SPC3 always has one diagnostics buffer assigned to it which is sent for a diagnostics call up The user can pre process new diagnostics data in parallel in the other buffer If the new diagnostics data are to be sent now the user uses the New Dag Cmd to make the request to exchange the diagnostics buffers The user receives confirmation of the exchange of the buffers with the Diag_Puf

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