Home

Samsung S3F80JB User's Manual

1. 1 External Interrupt Stop Stop Release Figure 1 5 Pin Circuit Type 1 Port 0 and Port2 1 10 ELECTRONICS S3F80JB PIN CIRCUITS Continued Data Open Drain Output Disable Normal Input Pull up gt Enable VDD Pull up Resistor 55kQ Typ Figure 1 6 Pin Circuit Type 2 Port 1 Port4 P3 4 and P3 5 ELECTRONICS PRODUCT OVERVIEW PRODUCT OVERVIEW S3F80JB PIN CIRCUITS Continued Pull up Resistor 55kQ Typ Pull up Enable P3CON 2 Port 3 0 Data o TO P3 0 TOPWM TOCAP T1CAP T2CAP Open Drain o Output Disable o P3 0 Input o P3CON 2 6 7 TOCAP T1CAP T2CAP Noise filter Figure 1 7 Pin Circuit Type 3 P3 0 1 12 ELECTRONICS S3F80JB PRODUCT OVERVIEW PIN CIRCUITS Continued VDD Pull up Resistor 55kQ Typ Pull up Enable M 5 Port 3 1 Data 0 34 Data M Carrier On Off P3 7 U CACON 2 X P3 1 REM TOCK Open Drain Output Disable P3 1 Input o P3CON 5 6 7 Figure 1 8 Pin Circuit 4 P3 1 VDD Pull up Resistor 55kQ Typ INPUT Input lt P3CON 2 6 7 TOCK P3 2 T1CAP T2CAP P3 3 Figure 1 9 Pin Circuit Type 5 P3 2 and P3 3 ELECTRONICS PRODUCT OVERVIEW S3F80JB PIN CIRCUITS Continued Pull up Resistor 500kQ Typ nRESET Figure 1 10 Pin Circuit Type
2. 8 5 8 5 Timing Diagram for Internal Power On Reset 8 6 8 6 Reset Timing Diagram for The S8F80JB in STOP mode by IPOR 8 7 8 7 Block Diagram for Back up nemen 8 10 8 8 Timing Diagram for Back up Mode Input and Released by LVD 8 10 9 1 SSF80JB I O Port Data Register 9 5 9 2 Pull up Resistor Enable Registers Port 0 and Port 2 only 9 6 10 1 Basic Timer Control Register 10 2 10 2 Timer 0 Control Register 10 5 10 3 Timer 0 DATA Register TODATA 08 10 5 10 4 Simplified Timer 0 Function Diagram Interval Timer Mode 10 6 10 5 Simplified Timer 0 Function Diagram PWM 10 7 10 6 Simplified Timer 0 Function Diagram Capture Mode 10 8 10 7 Basic Timer and Timer 0 Block Diagram eee 10 9 11 1 Simplified Timer 1 Function Diagram Capture Mode 11 2 11 Simplified Timer 1 Function Diagram Interval Timer Mode 11 3 11 3 Timer 1 Block Diagram x efi aite dette peret ettet t iere Rede
3. 2 12 Addressing the Common Working Register Area 2 16 Standard Stack Operations Using PUSH and 2 21 Chapter 8 Reset To Enter STOP MOG Etes eet roe Bact ostio eei Sok 8 10 Chapter 10 Basic Timer and Timer 0 Configuring the Basic nece t desideret deett epe ete Pete te Al eet endet 10 11 Programming Timer O resa redde ERR LS sue dads 10 12 Chapter 12 Counter A To Generate 38 kHz 1 3duty Signal Through P3 1 ssssssssssssssssseseeeeen enne 12 6 To Generate a one Pulse Signal Through 12 7 Chapter 15 Embedded Flash Memory Interface Sector Erase Pe PI 15 10 Programmitig NL Cd ge Re HERRERA a edv ed 15 15 prj MET 15 17 Hard Lock Protection S3F80JB MICROCONTROLLER xvii List of Register Descriptions Register Full Register Name Page Identifier Number BTCON Basic Timer Control 4 5 CACON Counter A Control 4 6 CLKCON System Clock Control 4 7 CMOD Comparator Mode Reglister drerit deu REG 4 8 CMPSEL Comparator Input Selection 4 9 EMT External Memory Timing 4 10 FLAGS System Flags Regis
4. o 13 2 Timer 2 Capture Interrupt x nee ierit 13 2 Timer 2 Match Iriterr pL s ri emt CH tene eater hae aa 13 3 Timer 2 Control Register T2CON cccceecceceeeeeeceeeeeeaeeeeeeeeaneeeeeeaeeeeeeeseaeeesecaaeeeeeseeaeeeeesneeeeeeeaees 13 5 Chapter 14 Comparator EANET AYA 14 1 Comparator Operation idees do c ecd eo nr s 14 3 viii S3F80JB MICROCONTROLLER Table of Contents continued Chapter 15 Embedded Flash Memory Interface cu PO dehy 15 1 ISP On Board Programming Sector ics 15 3 ISP Reset Vector and ISP Sector 5 15 5 Flash Memory Control Registers User Program emere 15 6 Flash Memory Control Register 2 15 6 Flash Memory User Programming Enable Register FMUSR 15 6 Flash Memory Sector Address Registers nennen nennen nenne 15 7 Sector Eraso PE 15 8 99 9 2 0 d a cays tua aded rei idt ditate 15 12 15 17 Hard Lock Protection be tenete Die e i
5. 1 5 1 4 Pin Assignment Diagram 44 Pin QFP 1 6 1 5 Pin Circuit Type 1 Port 0 and 1 10 1 6 Pin Circuit Type 2 Port 1 Port4 P3 4 and 5 1 11 1 7 Pin Gircult Type 3 B3 0 ire P Debe dehet 1 12 1 8 Pin Circuit Type 4 P3 1 5 eek cote evel tie ee ite tee cine pe shoes 1 13 1 9 Pin Circuit Type 5 P3 2 and 3 3 1 13 1 10 Pin Circuit Type 6 nRESET ree Ie ted p 1 14 2 1 Program Memory Address ee nene eren 2 2 2 2 Smart ere DP te Pp Pe oak denen te edet hens 2 3 2 3 Internal Register File Organization eee 2 6 2 4 Register Page Pointer 2 7 2 5 Set 1 Set 2 and Prime Area Register 2 9 2 6 8 Byte Working Register Areas 2 10 2 7 Contiguous 16 Byte Working Register 2 11 2 8 Non Contiguous 16 Byte Working Register 2 12 2 9 16 Bit Register Pair 3 ide eite eite rh tenete 2 13 2 10 Register File 8 8 2 14 2 11 Common Working Register 2 15 2 12 4 Bit Working Register Addressing sene
6. Program Memory Register File 8 bit register file address dst OPERAND OPCODE binis diui register in register One Operand file Instruction Example Value used in instruction execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register address Figure 3 1 Register Addressing Register File MSB Points to RPO ot RP1 RPO or RP1 Selected RP points to start abit 22 register Program Memory Working Magistar block OPCODE Points to the OPERAND a woking register Two Operand 4 1 of 8 po Instruction Example Sample Instruction ADD R1 R2 Where R1 and R2 are registers in the curruntly selected working register area Figure 3 2 Working Register Addressing 3 2 ELECTRONICS S3F80JB ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space if implemented see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Remember however that locations in set 1 cannot be accessed using Indirect Register addressing mode Pr
7. H 2 2 Register Architecture cci esteem end iota nc dori tto ctl cid hee edet hae erate eet ese ded 2 5 Register Page Pointer a ied ete i eco eu iei t 2 7 Register Set e R 2 8 Register Sot 2 e EY 2 8 Prime Register Space 2 oue eie e e en ed edes 2 9 WorkingiRegistersis etie aae pide eee 2 10 Using the Register Pointers 2 11 Register Addressing 25 er Eee ped qe bebe erre De entier eerte abes 2 13 Common Working Register Area 2 15 4 Bit Working Register 0 2 nemen 2 16 8 Bit Working Register 2 18 eee OP ede ied PR tee ely Ret teenie e E den 2 20 Chapter 3 Addressing Modes OVGIVIOW te eie edu per ade tee te di tei de 3 1 Register Addressing Mode R eese eene enne nennen nennen 3 2 Indirect Register Addressing Mode 3 3 Indexed Addressing Mode 3 7 Direct Address Mode nae s 3 10 Indirect Address Mode 3 12 Relative Address Mode RA trie cab caus ede e
8. I O port with bit programmable pin Configurable to input mode push pull output mode or n channel open drain output mode Input mode with a pull up resistor can be assigned by software This port 3pin has high current drive capability Also P3 1 can be assigned individually as an output pin for REM In the tool mode P3 1 is assigned as serial MTP interface pin SCLK P3 2 P3 3 C MOS Input port with a pull up resistor 18 2 P3 4 P3 5 I O port with bit programmable pins Configurable to input mode or output mode Pin circuits are either push pull or n channel open drain type Pull up resistors can be assigned by software P4 0 P4 7 I O port with bit programmable pins Configurable to input mode or output mode Pin circuits are either push pull or n channel open drain type Shared Functions TOCK T1 CAP T2CAP Xin System clock input and output pins nRESET System reset signal input pin and back up mode input Test signal input pin for factory use only must be connected to Vas Power Bem ELECTRONICS 1 9 PRODUCT OVERVIEW S3F80JB PIN CIRCUITS VDD Pull Up Resistor 55kQ typ Pull up Enable Data o INPUT OUTPUT Output Disable o 2 4 2 7 CMPSEL 0 3 i External REF P2 7 only i Comparator
9. 4 2 4 2 Mapped Registers Bank1 4 3 4 3 Each Function Description and Pin Assignment of P3CON in 42 44 Pin Package 4 32 5 1 SSF80JB Interrupt Vectors 5 6 5 2 Interrupt Control Register 5 7 5 3 Vectored Interrupt Source Control and Data 4 2 5 9 6 1 Instruction Group 6 2 6 2 Flag Notation 6 8 6 3 Instruction Set Symbols 6 8 6 4 Instruction Notation nennen 6 9 6 5 Opcode Quick Reference cies eee cn inte ite dice acts He 6 10 6 6 Condition Codes tst ee e Pede eene 6 12 8 1 Reset Condition in STOP Mode When IPOR LVD Control Bit is 1 always EMVD Onmn s eee iii ete inet ete ie fdas dade sei e lieta 8 8 8 2 Reset Condition in STOP Mode When IPOR LVD Control Bit is O 8 8 8 3 Set 1 Bank 0 Register Values After Reset 8 15 8 4 Set 1 Bank 1 Register Values After 8 17 8 5 Reset Generation According to the Condition of Smart Option 8 18 8 6 Guideline for Unused Pins to Reduced Power 8 19 8 7 Summary of Each Mode 1 4 3 c tu cadre detener e dite te do
10. 4 28 P2PND Port 2 External Interrupt Pending Register eene 4 29 Port 3 Control Register crine tt eet Xe eee 4 31 P345CON Port3 4 5 Control eene 4 33 P4CON Port 4 Control Register crt esee e eine dete ede VEREOR e 4 34 P4CONH Port 4 Control Register High Byte esee enne 4 35 P4CONL Port 4 Control Register Low 4 36 PP Register Page Pointer avsi esses nd eren eei de ete ent ne 4 37 RPO Register Pointer 0 i i edle Ie Re cpt fool anes bends Eee ug re 4 38 RP1 Register Pointer f cn are creen nee ae eade des 4 38 SPL Stack Pointer LOW Byte 2 iei cep deca lah xe e extet ore by 4 39 STOPCON Stop Control 4 4 2 4 39 SYM System Mode Register cic detect e ipe ian ave das 4 40 T1CON Timer 1 Control Register 4 42 T2CON Timer 2 Control Register ete ie eae eis 4 43 S3F80JB MICROCONTROLLER xix Instruction Mnemonic ADC ADD AND BAND BCP BITC BITR BITS BOR BTJRF BTJRT BXOR CALL CCF CLR COM CP CPIJE CPIJNE DA DA DEC DECW DIV DJNZ ENTER EXIT IDLE INC INCW IRET JP JR LD LD LDB LDC LDE LDC LDE LDCD LDED LDCI LDEI LDCPD LDEPD L
11. LS IS td 8 4 Internal Power On eie nett e 8 5 External Interrupt Reset iri iere eret Eee tek eoe eu Ue Teo Fe Ded deuce 8 7 Stop Error Detection amp Recovety ied ED eee Dade eee di 8 8 Power DowniMOdes nonet dd e stude ee 8 9 Idle Mode tee 8 9 Back up mode 2 2 Lie d Eee enna alah Sees 8 10 SIOp MOS teen PL d ge e c ve ue EY i i s POE edd 8 11 Sources to Release Stop 8 12 System Reset Operation PERPE 8 14 Hardware Reset Values ce x E RAO HERI EIS 8 15 Recommendation for Unusued Pins 2 24 0 0 1010 8 19 Summary Table of Back Up Mode Stop Mode and Reset 8 20 Chapter 9 Ports OVOLVIGW rem ad maii ete tats 0 9 1 Port Data Registers io eicere eed Eee ute oru du eode ue ged co aet ea teo 9 4 Pull Up Resistor Enable Registers 1i ir rco eg REN dene deed 9 5 S3F80JB MICROCONTROLLER vii Table of Contents continued Chapter 10 Basic Timer and Timer 0 eM EM 10 1 Basic Timer BT ore eed ese te edt ea foede een 10 1 Timer
12. Vreset lt Vin No system reset Vpp lt Vivp Transition from No system reset Vreset lt Vi to Vi lt Vreset Standstill Vpp 2 Vi yp Transition from Reset pin System reset occurs gt Vreset lt Vj to Vi lt Vreset NOTE IPOR LVD control bit is included in smart option at address 003 SFH 7 0 4 Vpp Vpp Vpp gt Vi yp Vreset lt Vin o No system reset 8 8 ELECTRONICS S3F80JB RESET POWER DOWN MODES The power down mode of S3F80JB are described following that Idle mode Back up mode Stop mode IDLE MODE Idle mode is invoked by the instruction IDLE op code 6FH In Idle mode CPU operations are halted while some peripherals remain active During Idle mode the internal clock signal is gated away from the CPU and from all but the following peripherals which remain active Interrupt logic Basic Timer Timer 0 Timer 1 Timer 2 Counter Comparator I O port pins retain the state input or output they had at the time Idle mode was entered IDLE Mode Release You can release Idle mode in one of two ways 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slowest clock 1 16 because of the hardware reset value for the CLKCON register If all interrupts are masked in the IMR re
13. 3 v 24 FM mezoetw 9 zm a _ v Psewmamengp _ sp Po4etmamenm _ 25 Poseemimemp moe 3 vV jP2etmamenn _ 7v me onoma _ 1 Pooetmamenp o me DM P2rextemalinenpt ma v me _ v me mM Psexmameng _ v m b Padextemalinterut O 7 24 P23exemdmemp ma v az om j Pzetmamenn 2 mo om J 1 me jPostmamenm o v NOTES 1 Interrupt priorities are identified in inverse order 0 is highest priority 1 is the next highest and so on 2 If two or more interrupts within the same level content the interrupt with the lowest vector address usually has priority over one with a higher vector address The priorities within a given level are fixed in hardware 3 Reset Basic timer overflow or POR interrupt vector address can be changed by smart option Refer to Table 15 3 or Figure 2 2 5 6 ELECTRONICS S3F80JB INTERRUPT STRUCTURE ENABLE DISABLE INTERRUPT INSTRUCTIONS DI Executing the Enable Interrupts El instruction globally enables the interrupt structure All interrupts are then serviced as they occur and according to the est
14. 6 60 NOP Vereor EE 6 61 OR Logica QOR teet eee datei eie Ma 6 62 POP Pop From stack sx emu ide arie aia de 6 63 POPUD Pop User Stack Decrementing eene 6 64 POPUI Pop User Stack Incrementing eene 6 65 PUSH Push TO Stack is cx redeem eiie red deci dites 6 66 PUSHUD Push User Stack Decrementing 6 67 PUSHUI Push User Stack Incrementing sse 6 68 RCF Reset jade p 6 69 RET ai 6 70 RL Rotate S 6 71 RLC Rotate Left Through Carry 1 e Pet Renee prre E Ce es 6 72 RR Rotate Er 6 73 RRC Rotate Right Through 6 74 SBO Select Bank 4 dede dede queue euim du ene diee dede 6 75 SB1 Select Bank e Ede E d ONE 6 76 SBC Subtract With Carry Ieras oraa odit net sete 6 77 SCF Set Garry Flag sciente e i Naa 6 78 SRA Shift Right Arithirrielic denied eite a 6 79 SRP SRPO SRP 1 Set Register etre eae gee ceeds 6 80 STOP Stop Operation coi ah cases Mek Sess ceed eee eaves ie Meee bnt eio 6 81 SUB Eier ER 6 82 SWAP SWap NIbDIGS 1 5 12 ede e ete ee de E 6 83 TCM Test Complement Under Mask enne 6 84 TM Test Under Mask ie ieu been 6 85 WFI WaitiEor Interr pt eim inee a nbi RP op Ea piedi 6 86 XOR Logical Exclusive OR nieder tt idt erit dit
15. Register File MSB Points to RPO or RP1 rn eee gt RPO or RP1 Selected RP points N to start of working register block NEXT 2 BITS TPaintto Working Feaister 9 Pair Register Pair 1 of 4 16 Bit address added to ne gt Program Memory offset LSB Selects or 8 Bit Data Memory 16 Bit Value used in Instruction OPERAND 16 Bit The values in the program address RR2 04H are loaded into register R4 Identical operation to LDC example except that external data memory is accessed LDE command is not available because an external interface is not implemented Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 ELECTRONICS S3F80JB ADDRESSING MODES INDEXED ADDRESSING MODE Continued Register File oe mmm RPO or RP1 purse ues RPO or RP1 1 Selected i RP points Program Memory RA 1 to start of working OFFSET register block EWG OFFSET NEXT 2 BITS 4 bit Working dst src epu Register Register Address Point to Working Pair 16 Bit address i added to PT Program Memory offset LSB Selects or Data Memory 16 Bit OPERAND Value used in 16 Bit Pos Instruction Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation
16. external interrupt pending when read 0 3 external interrupt is pending when read 2 PO 2 External Interrupt INT2 Pending Flag Bit 0 No PO 2 external interrupt pending when read 1 P0 2 external interrupt is pending when read 1 P0 1 External Interrupt INT1 Pending Flag Bit Lo No P0 1 external interrupt pending when read 1 external interrupt is pending when read 0 0 0 External Interrupt INTO Pending Flag Bit Lo No P0 0 external interrupt pending when read 0 0 external interrupt is pending when read NOTE To clear an interrupt pending condition write a 0 to the appropriate pending flag bit Writing a 1 to an interrupt pending flag 7 0 has no effect 4 22 ELECTRONICS S3F80JB CONTROL REGISTERS POPUR Porto Pull up Resistor Enable Register E7H Seti BankO Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P0 7 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 6 0 6 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 5 0 5 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor A P0 4 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 3 0 3 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up r
17. NOTE A timer 1 overflow interrupt pending condition is automatically cleared by hardware However the timer 1 match capture interrupt IRQ1 vector F6H must be cleared by the interrupt service routine S W 4 42 ELECTRONICS S3F80JB CONTROL REGISTERS T2CON Timer 2 Control Register E8H Seti Bank1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 and 6 Timer 2 Input Clock Selection Bits ofo fst 000 oft foss o ee Internal clock counter A flip flop T FF 5 and 4 Timer 2 Operating Mode Selection Bits lolo Interval timer mode counter cleared by match signal Capture mode rising edges counter running OVF can occur EN Capture mode falling edges counter running OVF can occur 1 1 Capture mode rising and falling edges counter running OVF can occur 3 Timer 2 Counter Clear Bit EN No effect when write Clear T2 counter T2CNT when write 2 Timer 2 Overflow Interrupt Enable Bit note EN Disable T2 overflow interrupt Enable T2 overflow interrupt 1 Timer 2 Match Capture Interrupt Enable Bit Disable 2 match capture interrupt Enable T2 match capture interrupt 0 Timer 2 Match Capture Interrupt Pending Flag Bit No T2 match capture interrupt pending when read Clear T2 match capture interrupt pending condition when write No effect when write T2 match capture interrupt
18. 1 and 0 P2 4 INT9 Mode Selection Bits fo fo C MOS input mode interrupt on falling edges ofa C MOS input mode interrupt on rising and falling edges ERES Push pull output mode 1 C MOS input mode interrupt on rising edges NOTES 1 Pull up resistors can be assigned to individual port2 pins by making the appropriate settings to the P2PUR control register location set 1 banko 2 Analog comparator inputs CINO CINS for P2 4 P2 7 can be assigned to individual port 2 pins by making the appropriate settings to the CMPSEL register location EBH set 1 bank1 If an analog comparator input is selected by the CMPSEL register normal I O inputs for P2 4 P2 7 are disconnected regardless of P2CONH register s setting value 4 26 ELECTRONICS S3F80JB CONTROL REGISTERS P2CONL Port 2 Contro Register Low Byte EDH Seti Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 6 P2 3 INT8 Mode Selection Bits fo fo C MOS input mode interrupt on falling edges C MOS input mode interrupt on rising edges and falling edges Push pull output mode C MOS input mode interrupt on rising edges 5 and 4 P2 2 INT7 Mode Selection Bits 79 cMOSmetmodemempronamgedees Fo 1 input interrupt on rising edges and taling edges Pr 0 Puso oups 0 7 3 and 2 P2 1 INT6 Mode Selection Bits 79
19. FLAGS prime is copied automatically back to the FLAGS register The fast interrupt status bit in FLAGS is cleared automatically 9 Programming Guidelines Remember that the only way to enable disable a fast interrupt is to set clear the fast interrupt enable bit in the SYM register SYM 1 Executing an El or DI instruction globally enables or disables all interrupt processing including fast interrupts If you use fast interrupts remember to load the IP with a new start address when the fast interrupt service routine ends 5 18 ELECTRONICS S3F80JB INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers There are 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide No special I O instructions I O control data registers are mapped directly into the register file Decimal adjustment included in binary coded decimal BCD operations 16 bit word data can be incremented and decremented Flexible instructions for bit addressing rotate and shift operations Data Types The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered f
20. Figure 11 3 Timer 1 Block Diagram ELECTRONICS S3F80JB TIMER 1 TIMER 1 CONTROL REGISTER T1CON The Timer 1 control register T1CON is located in Set 1 FAH and is read write addressable T1CON contains control settings for the following T1 functions Timer 1 input clock selection Timer 1 operating mode selection Timer 1 16 bit down counter clear Timer 1 overflow interrupt enable disable Timer 1 match or capture interrupt enable disable Timer 1 interrupt pending control read for status write to clear A reset operation clears T1CON to OOH selecting fosc divided by 4 as the T1 clock configuring Timer 1 asa normal interval Timer and disabling the Timer 1 interrupts Timer 1 Control Register T1 CON FAH Set 1 Bank 0 R W Timer 1 Input Clock Selection Bits Timer 1 Interrupt Pending Bit 00 fosc 4 0 No interrupt pending 01 fosc 8 0 Clear pending bit when write 10 fosc 16 1 Interrupt is pending 11 Internal clock T F F Timer 1 Interrupt Match capture Enable Bit 0 Disable interrupt 1 Enable interrupt Timer 1 Operating Mode Selection Bits 00 Interval mode 01 Capture mode capture on rising edge counter running OVF can occur 10 Capture mode capture on falling edge Timer 1 Overflow Interrupt Enable Bit counter running OVF can occur 0 Disable overflow interrupt 11 Capture mode capture on rising and 1 Enable overfl
21. No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc 3 12 D2 Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 03H and register 03H 04H CPIJNER1 R2 SKIP R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value and general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 00000010B Because the result of the comparison is non equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS S3F80JB INSTRUCTION SET DA Decimal Adjust DA dst Operation dst lt DA dst The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table indicates the operation performed The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits Instruction Carry Bits 4 7 H Flag Bits 0 3 Number Added Carry Before DA Value Hex Before DA Value Hex to Byte After DA 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 0 0 9 1
22. 0 Interrupt Enable Disable TOCON 1 77 Interrupt Enable Disable TOCON 2 overflow 8 bit Counter Pending gt RQO TOOVF TOCNT 0 8 bit Comparator Bl High level when data gt counter Low level when data lt counter TOCON 5 TOCON 4 Buffer Register Match Signal TOCON 3 TOOVF TimerO Data Register TODATA Figure 10 5 Simplified Timer 0 Function Diagram PWM Mode ELECTRONICS 10 7 BASIC TIMER and TIMER 0 S3F80JB Capture Mode In capture mode a signal edge that is detected at the TOCAP pin opens a gate and loads the current counter value into the TO data register You can select rising or falling edges to trigger this operation Timer 0 also gives you capture input source the signal edge at the TOCAP pin You select the capture input by setting the value of the timer 0 capture input selection bit in the port 3 control register PSCON 2 set 1 bank 0 When P3CON 2 is 1 the TOCAP input is selected When P3CON 2 is set to 0 normal I O port P3 0 is selected Both kinds of timer 0 interrupts can be used in capture mode the timer 0 overflow interrupt is generated whenever a counter overflow occurs the timer 0 match capture interrupt is generated whenever the counter value is loaded into the TO data register By reading the captured data value in TODATA and assuming a specific value for the timer 0 clock frequency you can c
23. 1 a E E 2 8 IOH mA VDD V Figure 17 5 Typical High Side Driver Source Characteristics P3 0 and P2 0 2 3 TYPICAL VDD VOH VDD 3 3V TYPICAL VDD VOH VS VDD IOH 1mA gt 9 a gt g 0 05 1 8V 2 3 2 8 3 3 3 8 IOH mA VDD V Figure 17 6 Typical High Side Driver Source Characteristics Port0 Port1 P2 4 2 7 P3 4 P3 5 and Port4 NOTE Figure 17 5 and 17 6 are characterized and not tested on each device ELECTRONICS 17 7 ELECTRICAL DATA 4MHz Stop Mode Data Retention Mode A Execution of STOP Instrction EXT INT 53 80 Mode Basic Timer Active lt gt gt Normal Operating Mode Figure 17 7 Stop Mode Release Timing When Initiated by an External Interrupt Stop Mode Oscillation Stabilization Time Operating Mode 5 Execution of STOP Insirction nRESET NOTE twarr is the same as 4096 x 16 x 1 fosc Figure 17 8 Stop Mode Release Timing When Initiated by a Reset 17 8 ELECTRONICS S3F80JB ELECTRICAL DATA 4MHz Reset Occur Stop Mode lt gt gt Normal Operating Mode Oscillation Stabilization Time Back up Mode Execution of STOP Instrction Data Retention Time NOTE twar is the same as 4096 x 16 x 1 fosc Figure 17
24. 1 and VDD is changed in condition for LVD operation in stop mode stop mode is released and reset occurs Using an External Interrupt to Release STOP Mode External interrupts can be used to release stop mode When IPOR LVD Control Bit smart option bit 7 is set to 0 and external interrupt is enabled SSF80JB is released stop mode and generated reset signal On the other hand when IPOR LVD Control Bit smart option bit 7 is set 1 S3F80JB is only released stop mode and isn t generated reset signal To wake up from stop mode by external interrupt from INTO to INT9 external interrupt should be enabled by setting corresponding control registers or instructions Please note the following conditions for Stop mode release lf you release Stop mode using an external interrupt the current values in system and peripheral control registers are unchanged f you use an external interrupt for Stop mode release you can also program the duration of the oscillation stabilization interval To do this you must make the appropriate control and clock settings before entering Stop mode Ifyou use an interrupt to release Stop mode the bit pair setting for CLKCON 4 CLKCON 3 remains unchanged and the currently selected clock value is used 8 12 ELECTRONICS S3F80JB RESET Stop Error Detect and Recovery The Stop Error Detect amp Recovery circuit is used to release stop mode and prevent
25. Register OOH 08H register 01H OBFH OR 00H 02H gt Register OOH OAH In the first example if working register RO contains the value 15H and register R1 the value 2AH the statement OR RO R1 logical ORs the RO and R1 register contents and stores the result 3FH in destination register RO The other examples show the use of the logical OR instruction with the various addressing modes and formats ELECTRONICS S3F80JB INSTRUCTION SET POP Pop From Stack POP Operation Flags Format Examples dst dst SP SP lt SP 1 The contents of the location addressed by the stack pointer are loaded into the destination The stack pointer is then incremented by one No flags affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 50 R 51 IR Given Register 00H 01H register 01H 1BH SPH 0D8H 00H SPL OD9H OFBH and stack register OFBH 55H POP 00H gt Register 00H 55H SP 00FCH POP 00H gt Register 00H 01H register 01H 55H SP OOFCH In the first example general register 00H contains the value 01H The statement POP 00H loads the contents of location OOFBH 55H into destination register OOH and then increments the stack pointer by one Register then contains the value 55H and the SP points to location OOFCH ELECTRONICS 6 63 INSTRUCTION SET S3F80JB POPUD Pop User Stack Decrementing POPUD Operation Flags Format
26. Rising edge detected VDD gt VLVD Low level detect voltage Reset Pulse generated oscillation starts Falling edge detected oscillation stop VDD lt VLVD Normal Operation Back up Mode Normal Operation NOTES 1 When the rising edge is detected by LVD circuit Back up mode is relesased VLVD VDD 2 When the falling edge is detected by LVD circuit Back up mode is activated VLVD gt VDD Figure 8 8 Timing Diagram for Back up Mode Input and Released by LVD 8 10 ELECTRONICS S3F80JB STOP MODE RESET STOP mode is invoked by executing the instruction STOP after setting the stop control register STOPCON In STOP mode the operation of the CPU and all peripherals is halted That is the on chip main oscillator stops and the current consumption can be reduced All system functions stop when the clock freezes but data stored in the internal register file is retained STOP mode can be released in one of two ways by a system reset or by an external interrupt After releasing from STOP mode the value of stop control register STOPCON is cleared automatically PROGRAMMING TIP To Enter STOP Mode This example shows how to enter the stop mode ORG JP ENTER STOP LD STOP NOP NOP NOP RET ORG JP ORG START LD MAIN NOP ELECTRONICS 0000H Reset address T START STOPCON 0A5H 0100H 3 T START 0100H Reset address BTCON 03 Clear basic timer counter ENTER
27. 1 to T1CON 3 you can clear reset the 16 bit counter value at any time during program operation TIMER 1 CAPTURE INTERRUPT Timer 1 can be used to generate a capture interrupt IRQ1 vector F6H whenever a triggering condition is detected at the P3 0 pin for 32 pin package and P3 3 pin for 44 pin package The T1CON 5 and T1CON 4 bit pair setting is used to select the trigger condition for capture mode operation rising edges falling edges or both signal edges In capture mode program software can poll the Timer 1 match capture interrupt pending bit T1 CON O to detect when a Timer 1 capture interrupt pending condition exists T1CON 0 1 When the interrupt request is acknowledged by the CPU and the service routine starts the interrupt service routine for vector F6H must clear the interrupt pending condition by writing a 0 to TT CON O T1CON 2 16 Bit Up Counter gt gt IRQ1 T1OVF Pending T1CON 0 LUNES i Interrupt Enable Disable T1CON 1 T1CON 5 Timer 1 Data 4 NOTE P3 0is assigned as T1CAP function for 32 pin package P3 3 is assigned as T1CAP function for 44 pin package Figure 11 1 Simplified Timer 1 Function Diagram Capture Mode 11 2 ELECTRONICS S3F80JB TIMER 1 TIMER 1 MATCH INTERRUPT Timer 1 can also be used to generate a match interrupt IRQ1 vector F6H whenever the 16 bit counter value matches the value that is written to the Timer 1 re
28. 2 25 0 80 200 aa 0 60 150 3 ANNI TAL p 99 d 100 T gt 75 Umm 0 20 m 0 00 TERCIO TE _ 1 800V 2 400V 3 000V 3 600V IOL mA vai Figure 17 2 Typical Low Side Driver Sink Characteristics P3 0 and P2 0 2 3 NOTE Figure 17 1 and 17 2 are characterized and not tested on each device ELECTRONICS ELECTRICAL DATA 4MHz 53 80 TYPICAL VOL vs IOL VDD 3 3V TYPICAL VOL VS VDD IOL 2mA 85 85 25 C wont 25 25 25 80 60 40 20 0 1 800V 2 400V 3 000V 3 600V IOL mA VDD V Figure 17 3 Typical Low Side Driver Sink Characteristics Port0 Port1 P2 4 2 7 P3 4 P3 5 and Port4 TYPICAL VDD VOH VDD 3 3V TYPICAL VDD VOH VS VDD IOH 6mA e X 85 25 25 C e o e a e VDD VOH V o x o gt gt e e a e 2 8 IOH mA VDD V Figure 17 4 Typical High Side Driver Source Characteristics P3 1 only NOTE Figure 17 3 and 17 4 are characterized and not tested on each device 17 6 ELECTRONICS S3F80JB ELECTRICAL DATA 4MHz TYPICAL VDD VOH VDD 3 3V TYPICAL VDD VOH VS VDD IOHz 2 2mA 85 25 25 3 s 5 5 gt gt
29. 200mV at 4MHz Operating Temperature Range e 25 C to 85 Operating Voltage Range e 1 95V 3 6V at 8MHz Package Types e 32 pin SOP 44 pin QFP ELECTRONICS S3F80JB PRODUCT OVERVIEW BLOCK DIAGRAM 32 PIN PACKAGE 0 0 3 INTO INT3 P0 4 PO 7 INT4 P1 0 1 7 HU Counter A 4 lEST 4 nHESET VDD p20 23 INT5 INT8 IPOR note 9 Port and Interrupt Port2 4 P24 27 Main Control 4 gt INT9 lt gt 2 gt CINO CIN3 8 Bit Basic Timer P3 0 TOPWM TOCAP 8 Bit Port3 SDAT T1CAP T2CAP TimerO 64K byte Counter 4 272 lt gt P3 1 REM TOCK SCLK FLASH 16 Bit Memory Register File Timer1 Counter 16 Bit Timer2 Counter Comparator Carrier Generator Comparator NOTE Figure 1 1 Block Diagram 32 pin IPOR can be enabled or disabled by IPOR LVD control bit in the smart option Refer to Figure 2 2 ELECTRONICS 1 3 PRODUCT OVERVIEW S3F80JB BLOCK DIAGRAM 44 PIN PACKAGE 0 0 3 INTO INT3 P0 4 P0 7 INT4 P1 0 1 7 Porto Port1 TEST RESET LVD P2 0 2 3 INT5 INT8 IPOR note Port and Interrupt P2 4 2 7 XIN Main L Control INT9 Xour OSC CINO CIN3 8 Bit Basic SAM8RC CPU Timer P3 0 TOPWM TOCAP SDAT lt gt P3 1 REM SCLK orl lt P3 2 TOCK 64K byte P3 3 T1CAP T2CAP Counter 272 byte L P3 4 P3 5
30. Flags Format Examples dst C dst 0 dst 7 lt dst 0 dst n lt dst n 1 0 6 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag C C Set if the bit rotated from the least significant bit position bit zero was 1 Z Set ifthe result is 0 cleared otherwise S Set ifthe result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 EO R 4 E1 IR Given Register 00H register 01H 02H and register 02H 17H RR 00H gt Register 00H 98H C 1 RR 01H gt Register 01H 02H register 02H 8BH C 1 In the first example if general register OOH contains the value 00110001B the statement RR OOH rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and overflow flag are also set to 1 ELECTRONICS 6 73 INSTRUCTION SET S3F80JB RRC Rotate Right Through Carry RRC Operation dst dst 7 lt C dst 0 dst n lt dst n 1 0 6 The contents of the destination o
31. LD TOCON 4BH Write 00100101B Input clock is fosc 256 Interval timer mode Enable the timer 0 interrupt Disable the timer 0 overflow interrupt LD TODATA 5DH Set timer interval to 4 milliseconds 6 MHz 256 93 1 0 25 kHz 4 ms SRP 0COH Set register pointer gt El Enable interrupts TOINT PUSH RPO Save RPO to stack SRPO 60H RPO lt 60H INC RO RO lt RO 1 ADD R2 RO R2 lt R24 ADC R3 R2 R3 lt R3 R2 Carry ADC R4 RO R4 lt R4 RO Carry Continued on next page ELECTRONICS 10 11 BASIC TIMER and TIMER 0 S3F80JB PROGRAMMING TIP Programming Timer 0 Continued CP RO 32H 50 4 200 ms JR ULT NO_200MS_SET BITS R12 Bit setting 61 2H NO 200MS SET LD TOCON 42H Clear pending bit POP RPO Restore register pointer 0 value TOOVER IRET Return from interrupt service routine 10 12 ELECTRONICS S3F80JB TIMER 1 11 OVERVIEW The S3F80JB microcontroller has a 16 bit timer counter called Timer 1 T1 For universal remote controller applications Timer 1 can be used to generate the envelope pattern for the remote controller signal Timer 1 has the following components control register T1CON FAH Set 1 R W Two 8 bit counter registers T1CNTH and T1CNTL F6H and F7H Set 1 Read only Two 8 bit reference data registers T1DATAH and T1DATAL F8H and F9H Set 1 R W One 16 bit compara
32. you must follow these steps 1 Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs 4 When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR 5 Execute an IRET Depending on the application you may be able to simplify the above procedure to some extent INSTRUCTION POINTER IP The instruction pointer IP is used by all S8C8 S3F8 series microcontrollers to control the optional high speed interrupt processing feature called fast interrupts The IP consists of register pair IPH DAH and IPL DBH Seti The IP register names are IPH high byte IP15 IP8 and IPL low byte IP7 IPO FAST INTERRUPT PROCESSING The feature called fast interrupt processing lets you specify that an interrupt within a given level be completed in approximately six clock cycles instead of the usual 22 clock cycles To select a specific interrupt level for fast interrupt processing you write the appropriate 3 bit value to SYM 4 SYM 2 Then to enable fast interrupt processing for the selected level you set SYM 1 to 1 ELECTRONICS 5 17 INTERRUPT STRUCTURE S3F80JB FAST INTERR
33. 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR Program Memory Next OPCODE e Address Used Cm 5c Value S Displacement Current Instruction OPCODE Signed Po Displacement Value Sample Instructions JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing ELECTRONICS 3 13 ADDRESSING MODES 53 80 IMMEDIATE MODE IM In Immediate IM mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The operand value is in the instruction Sample Instruction LD RO 0AAH Figure 3 14 Immediate Addressing 3 14 ELECTRONICS S3F80JB CONTROL REGISTERS CONTROL REGISTERS OVERVIEW In this section detailed descriptions of the S3F80JB control registers are presented in an easy to read
34. 18 5 Typical High Side Driver Source Characteristics P3 0 2 0 2 3 esseere een 18 7 18 6 Typical High Side Driver Source Characteristics Porto Porti P2 4 2 7 P3 4 P3 5 and Port4 ssssssssssosssssossssssssssssssssssssossssssosssssssssenss 18 7 18 7 Stop Mode Release Timing When Initiated by an External Interrupt 18 8 18 8 Stop Mode Release Timing When Initiated by a Reset 18 8 18 9 Stop Mode Release Timing When Initiated by a LVD 18 9 18 10 Input Timing for External Interrupts Port 0 and Port 2 m 18 10 18 1 1 Input Timing for Reset nRESET Pin MZasasssEassarssEausasausEa s 18 1 0 18 12 Operating Voltage Range of S3F80JB ssasaananauasasuanasanananausanasuanausananauasananananasansananananans 18 13 19 1 32 Pin SOP Package 19 1 19 2 44 Pin QFP Package Dimension eene 19 2 20 1 TB80JB Target Board Configuration 20 2 20 2 50 Pin Connector Pin Assignment for TB80JB 20 5 20 3 TB80JB Adapter Cable for 44 QFP Package L TCC T Cre Terre c rer 20 5 S3F80JB MICROCONTROLLER xiii List of Tables Table Title Page Number Number 1 1 Pin Descriptions of 32 S OP oed cedet ide 1 7 1 2 Pin Descriptions 44 1 8 2 1 SSF80JB Register Type 2 5 4 1 Mapped Registers 0 Set1
35. Connection for Pins POCONH lt or OFFH POCONL lt or OFFH ePOPUR lt 0FFH P1CONH lt 55H lt 55H P1 lt 00H 2 lt P2CONL lt P2 lt 00H eP2PUR lt 00H lt 11010010B lt 00H P3 2 P3 3 P3 4 P3 5 Set Push pull Output mode e Set P3 4 and P3 5 Data Register to 00H Connection for Pins Set Push pull Output mode e Set P4 Data Register to No Connection for Pins connection P345CON lt lt 00H lt PACONL lt 4 lt 00H Port 4 TEST ELECTRONICS e Connect to Vas 8 19 RESET SUMMARY TABLE OF BACK UP MODE STOP MODE AND RESET STATUS For more understanding please see the below description Table 8 7 Approach Condition Port status Control Register Releasing Condition Table 8 7 Summary of Each Mode Item Mode Back up Reset Status Stp External nRESET pin is low level state is lower than Vivo All I O port is floating status except for P3 2 and P3 3 All port becomes input mode but is blocked Disable all pull up resister except for P3 2 and P3 3 control register and System register are initialized as list of Table 8 3 External nRESET pin is high rising edge rising
36. Example 6 64 dst src dst lt src IR lt IR 1 This instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst sre opc SIC dst 3 8 92 R IR Given Register 00H 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H 00H gt Register OOH 41H register 02H 6FH register 42H 6FH If general register 00H contains the value 42H and register 42H the value 6FH the statement POPUD 02H 900H loads the contents of register 42H into the destination register 02H The user stack pointer is then decremented by one leaving the value 41H ELECTRONICS S3F80JB INSTRUCTION SET POPUI Pop User Stack Incrementing POPUI Operation Flags Format Example dst src dst lt src IR lt IR 1 The POPUI instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 8 93 R IR Given Register 00H 01H and register 01H 70H POPUI 02H 00H gt Register OOH 02H register 01H 70H register 02H 70H
37. Figure 8 4 Internal Power On Reset Circuit ELECTRONICS 8 5 RESET S3F80JB Voltage V Typp 1ms Rising Time VDD 0 85 VDD ViL 0 4 VDD Reset Pulse Width Reset pulse Time Figure 8 5 Timing Diagram for Internal Power On Reset Circuit NOTE The system reset operation depends on the interlocking work of the reset pin LVD circuit and Internal POR The LVD circuit can be disabled and enabled in the stop mode by smart option If 3FH 7 is 1 LVD circuit is always enabled In this case the system reset by LVD circuit occurs in stop mode But if 3FH 7 is 0 the system reset by LVD circuit doesn t occur in stop mode Refer to page 2 3 relating to the smart option The rising time of VDD must be less than 1ms If not IPOR can t detect power on reset ELECTRONICS S3F80JB RESET If Vreset VIH the operating status is in STOP mode and IPOR LVD control bit of smart option is 0 LVD circuit is disabled in the S3F80JB VDD ee 0 85VDD VLVD ooo Reset Pulse Width NOTE Vais a schmitt trigger input signal of internal power on reset IPOR a System reset is not occurred b System reset is occurred by internal POR circuit Figure 8 6 Reset Timing Diagram for The S3F80JB in STOP mode by IPOR EXTERNAL INTERRUPT RESET When IPOR LVD Control Bit smart option bit 7 is set to O and chip is in stop mode i
38. IP7 IPO The upper byte of the IP address is located in the IPH register DAH ELECTRONICS 4 15 CONTROL REGISTERS S3F80JB IPR Interrupt Priority Register FFH Seti BankO Bit Identifier 5 4 3 2 1 0 Reset Value X X X X X Xx X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 and 1 Priority Control Bits for Interrupt Groups A B and C 0 Group priority undefined 0 0 1 B C 5A A gt B gt C 10 1 1 gt gt 1 0 0 gt gt 1 0 1 gt 1 1 0 gt gt 1 Group priority undefined 6 Interrupt Subgroup C Priority Control Bit 0 IRQ6 gt IRQ7 IRQ7 gt IRQ6 5 Interrupt Group C Priority Control Bit 0 5 gt IRQ6 IRQ7 IRQ6 IRQ7 gt IRQ5 3 Interrupt Subgroup B Priority Control Bit See Note 0 IRQ3 gt IRQ4 IRQ4 gt IRQ3 2 Interrupt Group B Priority Control Bit See Note 0 IRQ2 gt IRQ3 IRQ4 IRQ4 gt IRQ2 0 Interrupt Group A Priority Control Bit 0 gt IRQ1 IRQ1 gt IRQO NOTE The SSF80JB interrupt structure uses eight levels IRQO IRQ7 4 16 ELECTRONICS S3F80JB CONTROL REGISTERS IRQ Interrupt Request Register DCH Seti Reset Value 0 0 0 0 0 0 0 0 Read Write R R R R Addressing Mode Register addressing mode only 7 Level 7 IRQ7 Request Pending Bit External Interrupts 0 7 0 4 Not
39. Instruction Pointer Low Byte c Interrupt Request Register Read Only L Interrupt Mask Register L l E I Register Page Pointer zE Port 0 Data Register Port 1 Data Register ojojo Port 2 Data Register System Mode Register SYM PL PH PL R YM P PO P1 P2 P3 P4 I ojo ELECTRONICS 8 15 RESET S3F80JB Table 8 3 Set 1 Bank 0 Register Values After Reset Continued Dec Hex 7 6 54 3 2 1 0 Port 1 Control Register Low Byte PICONL 235 2 Control Register High Byte P2OONH 206 EcH o o o o o o Port 2 Control Register Low Byte P2CONL 237 EDH Port 2 Pull up Enable Register P2PUR 238 EEH Pot3ComiRegdser 29 eu o o o o o o o Port 4 Control Register P4CON 240 Counter A Data Register High Byte CADATAH 244 Counter A Data Register Low Byte CADATAL 245 Timer 1 Counter Register High Byte T1CNTH 246 STOP Register sToPcon esr Fea o o o o o o o o
40. Intended Application Product Model Number Customer Risk Order Agreement We hereby request SEC to produce the above named product in the quantity stated below We believe our risk order product to be in full compliance with all SEC production specifications and to this extent agree to assume responsibility for any and all production risks involved Order Quantity and Delivery Schedule Risk Order Quantity PCS Delivery Schedule Delivery Date s Quantity Comments Signatures Person Placing the Risk Order SEC Sales Representative For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book FLASH APPLICATION NOTES S3F80JB Programming By Tool S3F80JB TOOL PROGRAMMING OF S3F80JB To read write erase by OTP MTP writer the following six pins are used Table 1 Descriptions of Pins Used to Read Write Erase the Flash in Tool Program Mode Normal Chip During Programming Pin pin Name Pin No Function P3 0 SDAT 3 30 Serial data pin Output port when reading and input port when writing SDAT P3 0 can be assigned as an input or push pull output port P3 1 SCLK 4 31 Serial clock pin Input only pin TEST TEST 9 4 Tool mode selection when TEST pin sets Logic value 1 If user uses the flash writer tool mode
41. Locations FCH is not mapped For factory test External Memory Timing Register EMT 254 Interrupt Priority Register IPR 255 NOTES 1 Although the SYM register is not used SYM 5 should always be 0 If you accidentally write a 1 to this bit during normal operation a system malfunction may occur 2 Except for TOCNTL IRQ T2CNTH T2CNTL and BTCNT which are read only all registers in set 1 are read write addressable 3 You cannot use a read only register as a destination field for the instructions OR AND LD and LDB 8 16 ELECTRONICS S3F80JB RESET Table 8 4 Set 1 Bank 1 Register Values After Reset Register Name Bit Values After Rese o P erc y Te e e e Regs LOGON ze eon e Port 4 Control Register Low Byte E3H 1 1 1 Timer 2 Counter Register Low Byte T2cnTL 229 O 0 0 0 Timer 2 Data Register High Byte T2DATAH 230 E6H 1 1 1 1 1 1 1 1 Timer 2 Data Register Low Byte T2DATAL E7H 1 1 1 eH Comparison Result Register OMPREG 234 ean o o o o o 0 o Comparator Input Selection Register OMPSEL 235 0 Flash Memory Sector Address ECH 0 Register
42. R1 R2 C R34C R4 C R5 C The sum of these six registers 6FH is located in the register RO 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD ADC ADC ADC ADC 80H 81H 80H 82H 80H 83H 80H 84H 80H 85H 80H 80H 80H 80H 80H 4 4 4 OOO00 Now the sum of the six registers is also located in register 80H However this instruction string takes 15 bytes of instruction code instead of 12 bytes and its execution time is 50 cycles instead of 36 cycles ELECTRONICS S3F80JB ADDRESS SPACES REGISTER ADDRESSING The S3C8 series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time With Register R addressing mode in which the operand value is the content of a specific register or register pair you can access all locations in the register file except for set 2 With working register addressing you use a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the
43. Repeating mode 11 fosc 8 Counter A Interrupt Time Selection Bits 00 Elapsed time for low data value 01 Elapsed time for high data value 10 Elapsed time for low and high data values 11 Invalid setting Counter A Start Stop Bit 0 Stop counter A 1 Start counter A Counter A Interrupt Enable Bit 0 Disable interrupt 1 Enable interrupt Figure 12 2 Counter A Control Register CACON Counter A Data High Byte Register CADATAH F4H Set 1 Bank 0 R W MSB 7 e s 4 2 a Jue Reset Value FFH Counter A Data Low Byte Register CADATAL F5H Set 1 Bank 0 R W Reset Value FFH Figure 12 3 Counter A Registers ELECTRONICS 12 3 COUNTER 53 80 COUNTER A PULSE WIDTH CALCULATIONS HIGH aig tLOW To generate the above repeated waveform consisted of low period time 4 and high period time tyigy When CAOF 0 ti ow CADATAL 2 x 1 Fx lt CADATAL lt 100H where Fx the selected clock 2 x 1 Fx lt lt 100H where Fx the selected clock When CAOF 1 ti gw 2 x 1 Fx lt lt 100H where Fx the selected clock tuigH CADATAL 2 x 1 Fx lt CADATAL lt 100H where Fx the selected clock To make tj ow 24 us and tyigh 15 us fosc 4 MHz FX 4 MHz 4 1 MHz Method 1 When CAOF 0 tLow 24 us CADATAL
44. Table 6 6 Condition Codes Binary Mnemonc Description FagsSe 0000 F Always false 1000 Always true 0111 note Carry C 1 1111 note NC No carry C20 0110 note 7 Zero 2 1 1110 note 7 Not zero Z 0 1101 PL Plus 56 0 0101 Minus S 1 0100 OV Overflow V 1 1100 NOV No overflow V 0 0110 note EQ Equal Z 1 1110 note NE Not equal Z 0 1001 GE Greater than or equal S XOR V 0 0001 LT Less than S XOR V 1 1010 GT Greater than Z OR S V 20 0010 LE Less than or equal Z OR S XOR V 21 1111 note UGE Unsigned greater than or equal C 0 0111 note ULT Unsigned less than C 1 1011 UGT Unsigned greater than C 0 AND 7 0 1 0011 ULE Unsigned less than or equal C OR Z 1 NOTES 1 It indicates condition codes that are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z would probably be used after a CP instruction however EQ would probably be used 2 For operations involving unsigned numbers the special condition codes UGE ULT UGT and ULE must be used 6 12 ELECTRONICS S3F80JB INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set Information is arranged in a consistent format for improved readability and for fast referencing The following information is inclu
45. Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 80 RR 8 81 IR Given RO 12H R1 R2 register OFH and register 21H DECW RRO gt RO 12H R1 33H DECW R2 Register 30H OFH register 31H 20H In the first example destination register RO contains the value 12H and register R1 the value The statement DECW RRO addresses RO and the following operand R1 as a 16 bit word and decrements the value of R1 by one leaving the value 33H A system malfunction may occur if you use a Zero flag FLAGS 6 result together with a DECW instruction To avoid this problem we recommend that you use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS S3F80JB INSTRUCTION SET DI Disable Interrupts DI Operation Flags Format Example SYM 0 lt 0 Bit zero of the system mode control register SYM 0 is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled No flags are affected Bytes Cycles Opcode Hex opc 1 4 8F Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending and
46. ex spw2 etc user should connect TEST pin to Vpp SSF80JB supplies high voltage 12 5V by internal high voltage generation circuit NRESET nRESET 12 7 Chip Initialization Vpp Vpp 5 32 Power supply pin for logic circuit Vss Vss 6 1 Vpp should be tied to 3 3 V during programming When writing or erasing using OTP MTP writer user must check the following Vdd Voltage The maximum operating voltage of SSF80JB is 3 6V Refer to the electrical data of SSF80JB manual The selection flag of Vdd must be set to 3 3V as like a figure on next page Test Pin Voltage The TEST pin on socket board for OTP MTP writer must be connected to Vdd 3 3V The TEST pin on socket board must not be connected Vpp 12 5V which is generated from OTP MTP Writer So the specific socket board for S3F80JB must be used when writing or erasing using OTP MTP writer ELECTRONICS 1 S3F80JB This is only an example for setting Vdd This is SPW2 which is one of OPT MTP Writers SPW2plus V2 05 Blank Check DVC Checksur Make HEX file of DVC Checksum bate duis Read Protection LDC Protection Hard Lock Smart option will be written 2 ELECTRONICS Important Note Subject Toggling phenomenon when serial writing programming on the S3F80JB Important Note S3F80JB 1 ANALYSIS RESULT When serial writing programming on S3F80JB only port1 4 1 5 1 6 1 7 are affected by SDAT sign
47. fosc 256 at8 MHz 5 External Reference Selection Bit Internal reference CINO 3 Analog input 1 External reference CINO 2 Analog input CIN3 Reference input 4 Not used for SSF80JB 3 0 Reference Voltage Selection Bits Selected VREF Vpp x N 0 5 1 6 N 0to15 NOTE You can select the number of analog input pin for your purpose by setting the CMPSEL 4 8 ELECTRONICS S3F80JB CONTROL REGISTERS CMPSEL Comparator Input Selection Register Seti Banki Reset Value 0 0 0 0 Read Write R W R W R W R W Addressing Mode Register addressing mode only 7 4 Not used for S3F80JB 3 P2 7 Function Selection Bit Normal I O selection Alternative function enable CIN3 2 P2 6 Function Selection Bit Normal I O selection Alternative function enable CIN2 4 P2 5 Function Selection Bit Normal I O selection Alternative function enable CIN1 0 P2 4 Function Selection Bit 0 Normal I O selection Alternative function enable CINO NOTE If abit of CMPSEL is set to 1 Comparator input is selected the port pin is operated as comparator input regardless of the P2CONH settings ELECTRONICS 4 9 CONTROL REGISTERS S3F80JB EMT external Memory Timing Register NOTE FEH Seti Reset Value 0 1 1 1 1 1 0 Read Write R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 External WAIT Input Function Enable B
48. owOSmetmodemempronangedees Lo 71 emos input mode interupton rising edges and taling edges 0 CS 1 and 0 P2 0 INT5 Mode Selection Bits fo fo C MOS input mode interrupt on falling edges ofa C MOS input mode interrupt on rising edges and falling edges Push pull output mode 1 C MOS input mode interrupt on rising edges NOTE Pull up resistors can be assigned to individual port 2 pins by making the appropriate settings to the P2PUR control register location set 1 0 ELECTRONICS 4 27 CONTROL REGISTERS S3F80JB P2INT Port 2 External Interrupt Enable Register E5H Seti BankO Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P2 7 External Interrupt INT9 Enable Bit Disable interrupt Enable interrupt 6 P2 6 External Interrupt INT9 Enable Bit 0 Disable interrupt 1 Enable interrupt 5 P2 5 External Interrupt INT9 Enable Bit Disable interrupt Enable interrupt 4 P2 4 External Interrupt INT9 Enable Bit Disable interrupt 1 Enable interrupt 3 P2 3 External Interrupt INT8 Enable Bit 0 Disable interrupt Enable interrupt 2 P2 2 External Interrupt INT7 Enable Bit Disable interrupt Enable interrupt 4 P2 1 External Interrupt INT6 Enable Bit 0 Disable interrupt 1 Enable interrupt 0 P2 0 External Interrupt INT5 Enable Bit Disable interrupt Ena
49. ra XOUT C2 External Clock Xi input frequency 1 8 2 External XIN Clock Open Pin Xo ELECTRONICS 18 11 ELECTRICAL DATA 8MHz 53 80 Table 18 9 Oscillation Stabilization Time TA 25 C to 85 C Vpp 3 6 V Oscillator Test Condition Main crystal fosc gt 400 kHz Main ceramic Oscillation stabilization occurs when Vpp is equal to the minimum oscillator voltage range External clock Xiy input High and Low width tyy t main system Oscillator twarr when released by a reset 1 stabilization wait time twart when released by an interrupt 2 x ms NOTES 1 fosc is the oscillator frequency 2 The duration of the oscillation stabilization time when it is released by an interrupt is determined by the setting in the basic timer control register BTCON 18 12 ELECTRONICS S3F80JB ELECTRICAL DATA 8MHz fosc Main Oscillator Frequency Minimun Instruction 250 kHz 1kHz 400 kHz L1 1 JD LL L Supply Voltage V Minimun Instruction Clock 1 4n x oscillator frequency n 1 2 8 or 16 A 1 95 V 8 MHz Figure 18 12 Operating Voltage Range of S3F80JB Table 18 10 AC Electrical Characteristics for Internal Flash ROM 25 C to 85 C Parameter Symbol Conditions Max Unit Programming Time 1 Fip Ls Chip Erasing Time 3 100 mS Data Access Time Ftrs Vpp 2 0 ns Number of Pu PER ES 000 i Data Retention
50. 0 3 06 0 ADD 0 A F 0 0 9 60 1 ADC 0 9 F 0 A F 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A F 66 1 1 0 3 1 0 3 66 1 0 0 9 0 0 9 00 00 0 SUB 0 0 8 1 6 F FA 06 0 SBC 1 7 0 0 9 AO 60 1 1 6 F 1 6 F 9A 66 1 Flags C Setifthere was a carry from the most significant bit cleared otherwise see table Z Setif result is 0 cleared otherwise S Set if result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 40 R 41 IR ELECTRONICS 6 33 INSTRUCTION SET S3F80JB DA Decimal Adjust DA Example 6 34 Continued Given Working register RO contains the value 15 BCD working register R1 contains 27 BCD and address 27H contains 46 BCD ADD _ RtRO C lt 0 lt 0 Bits 4 7 3 bits 0 3 C R1 lt 3CH DA R1 R1 3CH 06 If addition is performed using the BCD values 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0001 0101 15 0010 0111 27 0011 1100 The DA instruction adjusts this result so that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 42 Assuming the same values given above the statements SUB 27H RO C lt lt 0 Bits 4 7 3 bits 0 3 1 DA R1 R1 lt 31 0 leave the value 31 BCD in address
51. 07H and register 01H 05H BAND R1 01H 1 E R1 06H register 01H 05H BAND 01H 1 R1 gt Register 01H 05H R1 07H In the first example source register 01H contains the value 05H 00000101B and destination working register R1 contains 07H 00000111B The statement BAND R1 01H 1 ANDs the bit 1 value of the source register 0 with the bit O value of register R1 destination leaving the value 06H 00000110B in register R1 ELECTRONICS 6 17 INSTRUCTION SET S3F80JB BCP sit Compare BCP Operation Flags Format Example 6 18 dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared The contents of both operands are unaffected by the comparison Unaffected Set if the two bits are the same cleared otherwise Cleared to 0 Undefined Unaffected Unaffected IOZONO Bytes Cycles Opcode Addr Mode Hex dst src opc esibio sr 3 6 17 0 Rb NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 01H R1 01H 1 gt R1 07H register 01H 01H If destination working register R1 contains the value 07H 000001 11B and the source register 01H contains the value 01H 000000
52. 1 Because an external interface is not implemented for the S3F80JB SYM 7 must always be 0 2 Although the SYM register is not used SYM 5 should always be 0 If you accidentally write a 1 to this bit during normal operation a system malfunction may occur You can select only one interrupt level at a time for fast interrupt processing Setting SYM 1 to 1 enables fast interrupt processing for the interrupt level currently selected by SYM 2 SYM 4 5 Following a reset you must enable global interrupt processing by executing an El instruction not by writing a 1 to SYM 0 Bo 4 40 ELECTRONICS S3F80JB CONTROL REGISTERS TOCON Timer 0 Control Register D2H Set1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 Timer 0 Input Clock Selection Bits and 4 3 Timer 0 Counter Clear Bit No effect when write Clear TO counter TOCNT when write 2 Timer 0 Overflow Interrupt Enable Bit note Disable TO overflow interrupt Enable TO overflow interrupt 4 Timer 0 Match Capture Interrupt Enable Bit Disable TO match capture interrupt Enable TO match capture interrupt 0 Timer 0 Match Capture Interrupt Pending Flag Bit No match capture interrupt pending when read Clear match capture interrupt pending condition when write TO match capture interrupt is pending when read No effect when w
53. 2 2 external interrupt P2INT P2 1 external interrupt P2PND P2 0 external interrupt NOTES 1 Because the timer 0 timer1 and timer 2 overflow interrupts are cleared by hardware the TOCON T1CON and T2CON registers control only the enable disable functions The TOCON T1CON and T2CON registers contain enable disable and pending bits for the timer 0 timer1 and timer2 match capture interrupts respectively 2 Ifa interrupt is un mask Enable interrupt level in the IMR register the pending bit and enable bit of the interrupt should be written after a DI instruction is executed ELECTRONICS 5 9 INTERRUPT STRUCTURE S3F80JB SYSTEM MODE REGISTER SYM The system mode register SYM DEH Set 1 is used to globally enable and disable interrupt processing and to control fast interrupt processing See Figure 5 5 A reset clears SYM 7 SYM 1 and SYM 0 to 0 The 3 bit value SYM 4 SYM 2 is for fast interrupt level selection and undetermined values after reset SYM 6 and SYM5 are not used The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit 0 value of the SYM register An Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation in order to enable interrupt processing Although you can manipulate SYM 0 directly to enable and disable interrupts during normal operation we recommend using the El and DI instructions f
54. 200mV After power on LVD block is always enabled LVD block is only disable when executed STOP instruction with a smart option setting The LVD block of S3F80JB consists of two comparators and a resistor string One of comparators is for LVD detection and the other is for 0 FLAG detection LVD LVD circuit supplies two operating modes by one comparator back up mode input and system reset input The SSF80JB can enter the back up mode and generate the reset signal by the LVD level note1 detection using LVD circuit When LVD circuit detects the LVD level note1 in falling power SSF80JB enters the Back up mode Back up mode input automatically creates a chip stop state When LVD circuit detects the LVD level note1 in rising power the system reset occurs When the reset pin is at a high state and the LVD circuit detects rising edge of Vpp on the point V yp the reset pulse generator makes a reset pulse and system reset occurs This reset LVD circuit is one of the SSF80JB reset sources Refer to the page 8 3 for more LVD FLAG The other comparator s output makes LVD indicator flag bit 1 or 0 That is used to indicate low voltage level note2 When the power voltage is below the LVD FLAG level the bit 0 of LVDCON register is set 1 When the power voltage is above the LVD FLAG level the bit 0 of LVDCON register is set 0 automatically LVDCON O can be used flag bit to indicate low battery in IR application o
55. 31 223 6611 FAX 82 31 223 6613 e E mail openice aijisystem com e URL http www aijisystem com GW PRO2 Gang Programmer for One time PROM device e 8 devices programming at one time e Fast programming speed 1 2Kbyte sec e PC based control operation mode e Full Function regarding OTP program Read Program Vertify Protection blank e Data back up even at power break After setup in Desgin Lab it can be moved to the factory site Key Lock protecting operator s mistake Good Fail quantity displayed and memorized Buzzer sounds after programming User friendly single menu operation PC Operation mode displayed in LCD pannel Stand alone mode C amp A Technology TEL 82 2 2612 9027 FAX 82 2 2612 9044 E mail caat unitel co kr URL http www cnatech com International Sale SEMINIX e TEL 82 2 539 7891 FAX 82 2 539 7819 e E mail cindy seminix com e URL http www seminix com ELECTRONICS S3C8 SERIES MASK ROM ORDER FORM Product description Device Number S3C80JB S3F80JB S3C8 write down the ROM code number Product Order Form Package Pellet Wafer Package Type Package Marking Check One Standard Custom Custom B Max 10 chars Max 10 chars each line SEC YWW YWW Device Name Device Name Assembly site code Y Last number of assembly year WW Week of assembly Deli
56. 9 S3F80JB ADDRESS SPACES WORKING REGISTERS Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields When 4 bit working register addressing is used the 256 byte register file can be seen by the programmer as consisting of 32 8 byte register groups or slices Each slice consists of eight 8 bit registers Using the two 8 bit register pointers RP1 and RPO two working register slices can be selected at any one time to form a 16 byte working register block Using the register pointers you can move this 16 byte register block anywhere in the addressable register file except for the set 2 area The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces working register slice is 8 bytes eight 8 bit working registers RO R7 or R8 R15 working register block is 16 bytes sixteen 8 bit working registers R0 R15 All of the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one of the 24 slices in the register file The base addresses for the two selected 8 byte register slices are contained in register pointers RPO and RP1 After a reset RPO and always point to the 16 byte common area in set 1 COH CFH Slice 32 11111XXX RP1 Registe
57. C 10 P2 6 INT9 CIN2 C 11 P3 1 REM SCLK C4 Figure 1 4 Pin Assignment Diagram 44 Pin QFP Package 1 6 ELECTRONICS S3F80JB Table 1 1 Pin Descriptions of 32 SOP PRODUCT OVERVIEW open drain output mode Input mode with a pull up resistor can be assigned by software This port 3 pin has high current drive capability Also P3 1 can be assigned individually as an output pin for REM In the tool mode P3 1 is assigned as serial MTP interface pin SCLK System clock input andoutputpins System clock input andoutputpins input and output pins ee eee reset signal input pin and back up mode nRESET ee eee TEST Test signal input pin for factory use only must be connected to Vss VDD Power __ input pd ELECTRONICS Pin Pin Description con d Shared Type Functions P0 0 PO 7 I O port with bit programmable pins Configurable E Ext INT to input or push pull output mode Pull up resistors INTO INT3 are assignable by software Pins can be assigned 4 individually as external interrupt inputs with noise filters interrupt enable disable and interrupt pending control SED amp R note circuit built in PO for STOP releasing P1 0 P1 7 I O port with bit programmable pins Configurable to input mode or output mode Pin circuits either push pull or n channel open drain type P2 0 P2 3 port with bit programmable pins Configurable Ext INT P2 4
58. CAOF high LD P3 80H Set P3 7 Carrier On Off to high Pulse_out LD CACON 00000101B Start Counter A operation to make the pulse at this point After the instruction is executed 0 75 ms is required before the falling edge of the pulse starts ELECTRONICS 12 7 S3F80JB TIMER 2 TIMER 2 OVERVIEW The S3F80JB microcontroller has a 16 bit timer counter called Timer 2 T2 For universal remote controller applications timer 2 can be used to generate the envelope pattern for the remote controller signal Timer 2 has the following components One control register T2CON E8H Set 1 Bank1 R W Two 8 bit counter registers T2CNTH and T2CNTL E4H and E5H Set1 Bank1 Read only Two 8 bit reference data registers T2DATAH and T2DATAL E6H and E7H Set 1 Bank1 R W One 16 bit comparator You can select one of the following clock sources as the timer 2 clock Oscillator frequency divided by 4 8 or 16 Internal clock input from the counter A module counter A flip flop output You can use Timer 2 in three ways As anormal free run counter generating a timer 2 overflow interrupt IRQ3 vector FOH at programmed time intervals To generate a timer 2 match interrupt IRQ3 vector F2H when the 16 bit timer 2 count value matches the 16 bit value written to the reference data registers generate a timer 2 capture interrupt IRQ3 vector F2H when a triggering condition e
59. Circuit Emulator OPENice i500 System TEL 82 31 223 661 1 e FAX 82 331 223 6613 e E mail openice aijisystem com e URL http Awww aijisystem com SMART Kit C amp A Technology e TEL 82 2 2612 9027 e FAX 82 2 2612 9044 e E mail caat unitel co kr e URL http www cnatech com 20 6 ELECTRONICS S3F80JB OTP MTP PROGRAMMER WRITER DEVELOPMENT TOOLS DATA SPW2 Single PROM OTP FLASH MTO Programmer e Download Upload and data edit function e PC based operation with RS232C port e Full function regarding OTP programmer Read Program Verify Blank Protection Fast programming speed 1Kbyte sec Support all of SAMSUNG OTP devices Low cost Download the files from the 3rd party link shown below C amp A Technology TEL 82 2 2612 9027 FAX 82 2 2612 9044 E mail caat unitel co kr URL http www cnatech com International Sale SEMINIX e TEL 82 2 539 7891 FAX 82 2 539 7819 e E mail cindy seminix com e URL http www seminix com Jul 2002 USER s Manual fev 0 aiji Systems Co Liat BlueChips Combi BlueChips combi is a programmer for all Samsung MCU It can program not only all Samsung OTP MTP Flash MCU but also the popular E E PROMs New devices will be supported just by adding device files or upgrading the software It is connected to host PC s serial port and controlled by the software System TEL 82
60. D e EE eile neon 15 18 Chapter 16 Low Voltage Detector OVGIVIOW 5o grad rim anat ditaatat turae fatte elio aaepe erm diis 16 1 Buo 16 1 EVD Flag ete eere Dore e pe qubd ee o be ee n tbe xen 16 1 Low Voltage Detector Control Register 16 3 Chapter 17 Electrical Data 4MHz I ERR 17 1 Chapter 18 Electrical Data 8MHz NIC HDD 18 1 Chapter 19 Mechanical Data Overview RERRRARRRRRARARARRRRARARARRRRRARARARARRARARRARARRRRARARARRRRRARARARARARRARARARARARARARARARARRRARARARARRARARARAR RRGRRRARARRZRARARARARRGRARARRARRRRARARAR 19 1 Chapter 20 Development Tools Data Overview RRRRARRARRARARARARRARARARRRRSRARARARARARRRARARSARRRSRSRARARARRRRARARARARRRRARARARRRRRARARASARRRARARARARARRRRARARARRRARARARARRRRARARARRRRORARARRARRRRRRARAR 20 1 oid a 20 1 Programming Socket 20 1 TB80JB Target Bo rd 1 1 engem edite dira estes 20 2 OTP MTP Programmer Wirter ii acu ceret idee teret cai ette tate cuan Ca ka n ea 20 7 S3F80JB MICROCONTROLLER List of Figures Figure Title Page Number Number 1 1 Block Diagram 2 gt ade ame a 1 3 1 2 Block Diagram 44 1 4 1 3 Pin Assignment Diagram 32 Pin SOP Package
61. Dico o Hector dete E dete dite 10 1 Basic Timer Control Register BTCON c ecccceeeeeeeeeeeeeeeeeeeeeneeeeesaneeeeeeseaeeeeeseaeeeeeseeneeeeeseneeeees 10 2 Basic Timer Function Description oie hp r tet ertet i pce er depo rtp exe re rage 10 3 Timer 0 Control Register cccccseeceeeeeeeeeeeeeeeeeeeeeeeaeeeeecaaeeeeeescaeeesesnaeeeeesesaaeeeescineeesenaees 10 4 Timer O Function Description iei Rte EP dbi nm 10 6 Chapter 11 Timer 1 OVGIVIGW c qe odi egere s i e P a d ui 11 1 Timer 1 Overflow interrupts sc 2 eoi edere aaa 11 2 Timer T Capt re Interrupt a i im die ap OP don abuses 11 2 Timer 1 Match interrupt i coe eterne ec doe Te ar dete weet cute civ ede EUR Ee e PETER ete 11 3 Timer 1 Control Register T1 CON re a r ea r rar a Aa aa Ep TE A a ar e e aa sar ae 11 5 Chapter 12 Counter A OEE citu cet tc E or etre et oe t E 12 1 Counter A Control Register CACON 2 c ccceseeeeeeeeeceeeeeceeeeeeeeeaeeeeeeeaeeeeseseaaeeeeeeaeeeeeseeeeeeeeeeneeeess 12 3 Counter A Pulse Width 12 4 Chapter 13 Timer 2 Ver VIOW rating e te tee uet eee a Hi E odi ie Lees o E eder Pee eae Ee 13 1 Timer 2 Overflow Interr pt iode e crine te eire dea ae eU
62. IRQ4 IRIRA IRQ5 Interrupt Level Enable Bits 7 0 IRQ7 IRQ6 0 Disable mask interrupt 1 Enable un mask interrupt NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended Figure 5 6 Interrupt Mask Register IMR ELECTRONICS 5 11 INTERRUPT STRUCTURE S3F80JB INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR FFH Set 1 Bank 0 is used to set the relative priorities of the interrupt levels used in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine When more than one interrupt source is active the source with the highest priority level is serviced first If both sources belong to the same interrupt level the source with the lowest vector address usually has priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 GroupA _IRQO IRQ1 GroupB 2 IRQ3 IRQ4 GroupC IRQ5 IRQ6 IRQ7 B22 IRQ1 IRQ2 IRQ4 IRQ5 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of
63. Interrupt Enable Disable T2CON 1 16 Bit Up Counter P3 0 or P3 3 16 Bit Comparator Timer 2 High Low T2CON 5 Buffer Register T2CON 4 Match Signal T2CON 3 Timer 2 Data High Low Buffer Register Figure 13 2 Simplified Timer 2 Function Diagram Interval Timer Mode ELECTRONICS 13 3 TIMER 2 53 80 2 7 6 T2CON 2 RQ3 OVF CAOF T F F H fosc 4 16 Bit Up Counter R Clear T2CON 3 fosc 8 Read Only BE 16 Bit Compatator Timer 2 High Low cll 5 4 T1CON 0 0 IRQ3 Buffer Register T1CON 3 Match Signal T2OVF Timer 2 Data High Low Register Data Bus Match signal is occurrd only in interval mode Figure 13 3 Timer 2 Block Diagram 13 4 ELECTRONICS S3F80JB TIMER 2 TIMER 2 CONTROL REGISTER T2CON The timer 2 control register T2CON is located in address E8H Bank1 Set 1 and is read write addressable T2CON contains control settings for the following T2 functions Timer 2 input clock selection Timer 2 operating mode selection Timer 2 16 bit down counter clear Timer 2 overflow interrupt enable disable Timer 2 match or capture interrupt enable disable Timer 2 interrupt pending control read for status write to clear A reset operation clears T2CON to OOH selecting fosc divided by 4 as the T2 clock configuring timer 2 as a normal interval ti
64. LDCPI LDEPI Operation Flags Format Examples dst src m 1 dst lt src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes Irr an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src src dst 2 14 F3 Irr r Given RO 7FH R6 21H and R7 OFFH LDCPI RR6 RO RR6 RR6 1 7FH contents of RO is loaded into program memory location 2200H 21FFH 1H RO 7FH R6 22H R7 00H LDEPI GRReRO RR6 lt RR6 1 contents of RO is loaded into external data memory location 2200H 21FFH 1H RO 7FH R6 22H R7 OOH ELECTRONICS 6 57 INSTRUCTION SET S3F80JB LDW Load Word LDW Operation Flags Format Examples 6 58 dst src dst lt src The contents of the source a word are loaded into the destination The contents of the source are unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst sre opc SIC dst 3 8 C4 RR RR C5 RR IR opc dst src 4 8 C6 RR IML Gi
65. MULT MULT IR1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 RL POPUD POPUI DIV DIV DIV IR1 IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 INCW CP C CP CP C IR1 r1 r2 r1 lr2 R2 R1 IR2 R1 R1 IM CLR XOR XOR XOR XOR XOR IR1 r1 r2 r1 lr2 R2 R1 IR2 R1 R1 IM RRC CPIJE LDC LDW LDW LDW IR1 Ir r2 RA r1 lrr2 RR2 RR1 IR2 RR1 RR1 IML SRA CPIJNE LDC CALL LD IR1 Irr r2 RA r2 lrr1 IA1 IR1 IM RR LDCD LDCI LD LD LD IR1 r1 lrr2 r1 lrr2 R2 R1 R2 IR1 R1 IM SWAP LDCPD LDCPI CALL LD CALL IR1 r2 lrr1 ra lrr1 IRR1 IR2 R1 DA1 7 BOR ro Rb BCP r1 b R2 BXOR ro Rb BTJR r2 b RA LDB ro Rb BITC r1 b BAND ro Rb BIT r1 b LD r1 x r2 LD r2 x r1 LDC r1 Irr2 xL LDC r2 Irr2 xL LD r1 Ir2 LD Ir1 r2 LDC r1 Irr2 xs LDC r2 xs ELECTRONICS S3F80JB LD r1 R2 ELECTRONICS Table 6 5 Opcode Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX INSTRUCTION SET RET IRET RCF SCF CCF NOP INSTRUCTION SET S3F80JB CONDITION CODES The op code of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equal after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions
66. Memory Sector Address Register FMSECH Flash Memory Sector Address Register FMSECL EDH Set1 Bank 1 R W Don t Care Flash Memory Sector Address Low Byte NOTE The Low Byte flash memory sector address pointer value is the lower eight bits of the 16 bit pointer address Figure 15 6 Flash Memory Sector Address Register FMSECL ELECTRONICS 15 7 EMBEDDED FLASH MEMORY INTERFACE 53 80 SECTOR ERASE User can erase a flash memory partially by using sector erase function only in user program mode The only unit of flash memory to be erased in the user program mode is a sector The program memory of SSF80JB 64Kbytes flash memory is divided into 512 sectors Every sector has all 128 byte sizes So the sector to be located destination address should be erased first to program a new data one byte into flash memory Minimum 10ms delay time for the erase is required after setting sector address and triggering erase start bit 0 Sector erase is not supported in tool program modes MDS mode tool or programming tool Sector 511 128 byte Sector 510 128 byte Sector 127 128 byte Sector 11 128 byte Sector 10 128 byte Sector 0 9 128 byte x 10 Figure 15 7 Sector Configurations in User Program Mode 15 8 ELECTRONICS S3F80JB EMBEDDED FLASH MEMORY INTERFACE The Sector Erase Procedure in User Program Mode 1 2 3 4 Set Flash Memory User Programming Enable Registe
67. Operating 25 to 85 Temperature Storage Tera 65 to 150 V Table 17 2 D C Electrical Characteristics 25 Cto 85 Vpp 1 7 V to 3 6 V Lowe conto mn ont Operating Voltage Fosc 4 MHz Input High Voltage All input pins except Vi and Vis nRESET Input Low Voltage All input pins except Vij Vito nRESET Output High Vpp 2 1 V 1 0 Voltage Port 3 1 only P3 0 and P2 0 2 3 PortO Porti P2 4 2 7 P3 4 3 5 and Port4 17 2 ELECTRONICS S3F80JB ELECTRICAL DATA 4MHz Table 17 2 D C Electrical Characteristics Continued TA 25 C to 85 Vpp 1 7 V to 3 6 V Symbol Conditions Output Low Vout Vpp 2 1 V Io 12mA Voltage Port 3 1 only Vpp 2 1 V Io SMA P3 0 and P2 0 2 3 Voi3 Vpp 2 35 V lop 1mA Port1 P2 4 2 7 P3 4 3 5 and Port4 Input High lim Vin Voo Leakage Current All input pins except ijo and XouT Voo Xin Input Low Vin OV Leakage Current All input pins except i XouT Vin OV Xin Output High Vout Vpp Leakage Current All output pins Output Low Vout 9 V Leakage Current All output pins Pull Up Vn 0 V Vpp 2 1 V Resistors Ta 25 C Ports 0 4 Vn OV Vpp 2 1 V 25 nRESET Resistor 25 Xy ELECTRONICS 17 3 ELECTRICAL DATA 4MHz 53 80 Table 17
68. RESET OPERATION System reset starts the oscillation circuit synchronize chip operation with CPU clock and initialize the internal CPU and peripheral modules This procedure brings the S3F80JB into a known operating status To allow time for internal CPU clock oscillation to stabilize the reset pulse generator must be held to active level for a minimum time interval after the power supply comes within tolerance The minimum required reset operation for a oscillation stabilization time is 16 oscillation clocks All system and peripheral control registers are then reset to their default hardware values See Tables 8 3 In summary the following sequence of events occurs during a reset operation All interrupts are disabled The watch dog function Basic Timer is enabled Port 0 2 3 are set to input mode and all pull up resistors are disabled for the I O port pin circuits Peripheral control and data register settings are disabled and reset to their default hardware values See Table 8 3 The program counter PC is loaded with the program reset address in the ROM 0100H When the programmed oscillation stabilization time interval has elapsed the instruction stored in reset address is fetched and executed NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to
69. RF Bit Test Jump Relative on False BTJRF Operation Flags Format Example dst src b If src b is a 0 then PC lt PC dst The specified bit within the source operand is tested If it is a 0 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRF instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA NOTE the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRF SKIP R1 3 gt PC jumps to SKIP location If working register R1 contains the value 07H 00000111B the statement BTJRF SKIP R1 3 tests bit 3 Because it is O the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 23 INSTRUCTION SET S3F80JB BTJ RT Bit Test Jump Relative on True BTJRT Operation Flags Format Example 6 24 dst src b If src b is a 1 then PC lt PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is no
70. Register addressing mode only P1 3 Mode Selection Bits 0 0 CMOS inputmode 0 1 Open drain outputmode S Push pull output mode C MOS input with pull up mode P1 2 Mode Selection Bits fo o owosmumd SS i fo Pusnputouputmode P1 1 Mode Selection Bits Lo o i fo SSCS P1 0 Mode Selection Bits 9 Openainouputmeds EEE Push pull output mode 1 C MOS input with pull up mode 4 25 CONTROL REGISTERS 53 80 P2CONH Port 2 Control Register High Byte Seti BankO Bit Identifier 7 6 5 4 2 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 6 P2 7 INT9 Mode Selection Bits fo fo C MOS input mode interrupt on falling edges C MOS input mode interrupt on rising and falling edges Push pull output mode C MOS input mode interrupt on rising edges 5 and 4 P2 6 INT9 Mode Selection Bits Coe input mode interaptonfaling edges Fo oMOSimutmode nemuptonrengandaingedges Fr o memmtowumze CS 3 and 2 P2 5 INT9 Mode Selection Bits 79 input mode interaptonfaling edges Fo input moder interupton rising and taling edges Push pulouputmode 7
71. San 24 Nongseo Dong Giheung Gu Yongin City Gyunggi Do Korea C P O Box 37 Korea 446 711 TEL 82 31 209 5238 FAX 82 31 209 6494 Home Page URL Http www samsungsemi com Printed in the Republic of Korea Preface The SSF80JB Microcontroller User s Manual is designed for application designers and programmers who are using SSF80JB microcontroller for application development It is organized in two main parts Part Programming Model Part II Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has six chapters Chapter 1 Product Overview Chapter 4 Control Registers Chapter 2 Address Spaces Chapter 5 Interrupt Structure Chapter 3 Addressing Modes Chapter 6 Instruction Set Chapter 1 Product Overview is a high level introduction to SSF80JB with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 2 also describes working register addressing as well as system stack and user defined stack operations Chapter 3 Addressing Modes contains detailed descriptions of the addressing modes that are supported by the S3C8 series CPU Chapter 4 Control Registers contains overview tables
72. W R W R W R W R W Addressing Mode Register addressing mode only 7 and 6 P4 3 Mode Selection Bits 0 0 CMOS inputmode 0 1 Open drain outputmode 0 0 ilo Push pull output mode C MOS input with pull up mode 5 and 4 P4 2 Mode Selection Bits Lo o owosmumd 3 and 2 P4 1 Mode Selection Bits Lo o cwosmumd Fo rjowmemnowptmok SSS 1 and 0 P4 0 Mode Selection Bits 0 0 jCMOSmutmde 0 JOpendriouputmode ERES Push pull output mode 1 C MOS input with pull up mode NOTE After CPU reset P4 3 P4 0 will be C MOS input with pull up mode by the reset value of PACONL register 4 36 ELECTRONICS S3F80JB CONTROL REGISTERS PP Register Page Pointer DFH Seti Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Destination Register Page Selection Bits 0 o Destination page o 3 0 Source Register Page Selection Bits 0 0 Source page o seen NOTE In the S3F80JB microcontroller a paged expansion of the internal register file is not implemented For this reason only page 0 settings are valid Register page pointer values for the source and destination register page are automa
73. W R W R W R W R W R W Register addressing mode only Package Selection and Alternative Function Select Bits 32 pin package P3 0 TOPWM TOCAP T1CAP T2CAP P3 1 REM TOCK Others 42 44 pin package P3 0 TOPWM TOCAP P3 3 TT CAP T2CAP P3 1 REM P3 2 TOCK P3 1 Function Selection Bit Normal I O selection Alternative function enable REM TOCK P3 1 Mode Selection Bits fo fo Schmitt trigger input mode ERES Open drain output mode Push pull output mode Schmitt trigger input with pull up resistor Function Selection Bit for P3 0 amp P3 3 Normal I O selection Alternative function enable P3 0 TOPWM TOCAP P3 3 TT CAP T2CAP P3 0 Mode Selection Bits Fo fo Schmitt trigger input mode ofa Open drain output mode 1 0 Push pull output mode Schmitt trigger input with pull up resistor 4 31 CONTROL REGISTERS S3F80JB NOTES 1 The port data register at location E3H set1 bankO contains seven bit values which correspond to the following Port pin functions bit 6 is not used for the 5 8 a Port3 bit 7 carrier signal on 1 or off 0 b Port3 bit 1 0 P3 1 REM TOCK pin bit 0 P3 0 TOPWM TOCAP T1CAP pin C Port3 bit 3 2 P3 3 P3 2 are selected only to input pin with pull up resistor automatically Port3 bit 5 4 P3 5 P3 4 are selected into digital I O by setting P345CON register at E1H Set1 Bank1 2 The alternative function enable disable
74. abnormal stop mode that can be occurred by battery bouncing It executes two functions in related to the internal logic of PO and P2 4 P2 7 One is releasing from stop status by switching the level of input port PO or P2 4 P2 7 and the other is keeping the chip from the stop mode when the chip is in abnormal status Releasing from stop mode When IPOR LVD Control Bit smart option bit 7 is set to 0 if falling edge input signal enters in through PortO or P2 4 P2 7 S3F80JB is released stop mode and generate reset signal On the other hand when IPOR LVD Control Bit smart option bit 7 is set to 1 SSF80JB is only released stop mode Reset doesn t occur When the falling edge of a pin on PortO and P2 4 P2 7 is entered the chip is released from stop mode even though external interrupt is disabled Keeping the chip from entering abnormal stop mode This circuit detects the abnormal status by checking the port PO and P2 4 P2 7 status If the chip is in abnormal status it keeps from entering stop mode NOTE In case of P2 0 2 3 SED amp R circuit isn t implemented So although 4pins P2 0 2 3 have the falling edge input signal in stop mode if external interrupt is disabled the stop state of S3F80JB is unchanged Do not use stop mode if you are using an external clock source because Xin input must be cleared internally to VSS to reduce current leakage ELECTRONICS 8 13 RESET S3F80JB SYSTEM
75. dst 3 6 A4 R R A5 R IR opc dst src 3 6 A6 R IM Examples 1 Given R1 02H and R2 CP R1 R2 gt Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are wA 2 Given R1 05H and R2 OAH CP R1R2 JP UGE SKIP INC 1 SKIP LD R3 R1 In this example destination working register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement CP R1 R2 generates C 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in working register R3 6 30 ELECTRONICS S3F80JB CPIJE CPIJE Operation Flags Format Example INSTRUCTION SET Compare Increment and Jump on Equal dst src RA Ifdst src 0 PC lt PC Ir Ir 1 The source operand is compared to subtracted from the destination operand If the result is 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is
76. each four bits Given The carry flag 1 and LABEL_X 1FF7H JR C LABEL X PC 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL_X will pass control to the statement whose address is now in the PC Otherwise the program instruction following the JR would be executed ELECTRONICS S3F80JB INSTRUCTION SET LD Load LD dst src Operation dst lt src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src r8 r R r OtoF D7 Ir r E5 R IR opc dst src 3 6 E6 R IM D6 IR IM Fr xH xo ELECTRONICS 6 49 INSTRUCTION SET LD Load LD Continued S3F80JB Examples Given RO 01H R1 OAH register 00H 01H register 01H 20H register 02H 02H LOOP and register OFFH LD LD LD LD LD LD LD LD LD LD LD LD 6 50 0 10 gt 0 01 gt 01H RO I R1 RO gt RO R1 gt 00H 01H gt 02H 00H gt 0 gt 00H 10H gt 00H 02H gt RO LOOP R1 gt LOOP RO R1 gt RO 10H RO Register 01H R1 20H RO 20H register 01H 20H 01H RO 01H 01H RO 01H R1 OAH register 01H OAH Register OOH Register 02H Register OOH Register OOH Register OOH 20H register 01H 20H register OOH OAH 01H reg
77. ee Interrupt Priority Vector Register Interrupt Cycle IRQO IRQ7 Interrupts Interrupt Mask Register Global Interrupt Control El DI or SYM 0 manipulation Figure 5 4 Interrupt Function Diagram 5 8 ELECTRONICS S3F80JB INTERRUPT STRUCTURE PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by that peripheral See Table 5 3 Table 5 3 Vectored Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s in Set 1 Bank Timer 0 match capture or TOCON see Note D2H Timer 0 overflow TODATA D1H Timer 1 match capture or IRQ1 T1CON see Note FAH Timer 1 overflow T1DATAH T1DATAL F8H F9H Counter A IRQ2 CACON F3H CADATAL F4H F5H Timer 2 match capture or IRQ3 T2CON see Note E8H Bank1 Timer 2 overflow T2DATAH T2DATAL E6H E7H PO 7 external interrupt IRQ7 POCONH E8H 0 6 external interrupt POINT F1H PO 5 external interrupt POPND F2H 0 4 external interrupt 0 3 external interrupt POCONL E9H P0 2 external interrupt POINT F1H P0 1 external interrupt POPND F2H 0 external interrupt P2 7 external interrupt IRQ5 P2CONH ECH P2 6 external interrupt P2INT E5H P2 5 external interrupt P2PND E6H P2 4 external interrupt P2 3 external interrupt IRQ4 P2CONL
78. etie D eekly 3 13 Irnmediate Mode IM iiir dto eerta Seen dt to ire Ge a ieee 3 14 Chapter 4 Control Registers OVENVIOW p PL 4 1 Table of Contents continued Chapter 5 Interrupt Structure 5 1 Interrupt Types entente deci ecce sento tended nd d edet ak aed et eee de oe as 5 2 Interrupt Vector Addresses e tete eram eee emet tos 5 5 Enable Disable Interrupt Instructions El 5 7 System Level Interrupt Control 5 7 Interrupt Processing Control 5 8 Peripheral Interrupt Control Registers 5 9 System Mode Register 5 5 10 Interrupt Mask Register IMR esee enne nennen nennen 5 11 Interrupt Prierity Register IPR accion eno ote ere ode 5 12 Interrupt Request Register IRQ cccccceeseceeeeeeeeeeeeeeaeceeeeeeseneeeeneeeseeeeeeeceeseneeseaeeeseseeessaeeseneeneeees 5 14 Interrupt Pending Function nennen nnn enn rennen nennen 5 15 Interrupt Source Polling 5 16 Interrupt Service ROULINGS dieran Le ente red dee 5 16 Generating interrupt Vector Addresses 5 17 Nesting
79. has no subsystem clock the 3 bit signature code CLKCON 2 CLKCON 0 is no meaning Figure 7 3 System Clock Circuit Diagram 7 2 ELECTRONICS S3F80JB CLOCK CIRCUITS SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register is located in address D4H Set1 Banko It is read write addressable and has the following functions Oscillator frequency divide by value The CLKCON 7 5 and CLKCON 2 0 Bit are not used in S3F80JB After a reset the main oscillator is activated and the 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed to fosc foscio foscis or foscA 6 System Clock Control Register CLKCON D4H Set 1 Bank 0 R W Not used Divide by selection bits for CPU clock frequency Not used 00 fosc 16 01 fosc 8 10 fosc 2 11 fosc non divided Figure 7 4 System Clock Control Register CLKCON ELECTRONICS 7 3 S3F80JB RESET RESET OVERVIEW Resetting the MCU is the function to start processing by generating reset signal using several reset schemes During reset most control and status are forced to initial values and the program counter is loaded from the reset vector In case of S3F80JB reset vector can be changed by smart option Refer to the page 2 3 or 15 5 RESET SOURCES The S3F80JB has six different system reset sources as following The External Reset Pin nRES
80. in RP1 10101B become the five high order bits of the register address The three low order bits of the register address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address OABH 10101011B RPO RP1 Selects RPO or RP1 These address Address bits indicate register addressing sens OD TITSTS T TT T 26 d Three low Register pointer order bits provides five high order bits 1111111 4 8 bit physical address Figure 2 14 8 Bit Working Register Addressing 2 18 ELECTRONICS S3F80JB ADDRESS SPACES 8 bit address from instruction LD R11 R2 Specifies working register addressing Register address OABH Figure 2 15 8 Bit Working Register Addressing Example ELECTRONICS 2 19 S3F80JB ADDRESS SPACES SYSTEM AND USER STACKS S3C8 series microcontrollers use the system stack for subroutine calls and returns and to store data The PUSH and POP instructions are used to control system stack operations The S3F80JB architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the conten
81. indicates a positive number and a logic one indicates a negative number Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is also cleared to 0 following logic operations Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is seldom accessed directly by a program Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed Bank Address Flag FLAGS 0 The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected bank 0 or bank 1 The BA flag is cleared to 0 select bank 0 when you execute the SBO instruction and is set to 1 select bank 1 wh
82. interrupt groups A B and C For example the setting 001B for these bits would select the group relationship B gt C gt A the setting 101B would select the relationship C gt B gt A The functions of the other IPR bit settings are as follows 5 controls the relative priorities of group C interrupts Interrupt group B has a subgroup to provide an additional priority relationship between for interrupt levels 2 3 and 4 IPR 3 defines the possible subgroup B relationships IPR 2 controls interrupt group B 0 controls the relative priority setting of IRQO and IRQ1 interrupts 5 12 ELECTRONICS S3F80JB INTERRUPT STRUCTURE Interrupt Priority Register IPR FEH Set 1 Bank 0 R W Group Priority D7 D4 D1 0 IRQO gt IRQ1 1 IRQO lt IRQ1 0 Undefined Group B 1 gt gt 0 IRQ2 gt IRQ3 IRQ4 0 A gt B gt C 1 IRQ2 lt IRQ3 IRQ4 1 B gt A gt C Subgroup B see note 0 gt gt 0 IRQ3 gt IRQ4 1 gt gt 1 IRQ3 lt IRQ4 0 A gt C gt B Group C 1 Undefined 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 0 0 0 0 1 1 1 1 Figure 5 8 Interrupt Priority Register IPR ELECTRONICS 5 13 INTERRUPT STRUCTURE S3F80JB INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ DCH Set 1 to monitor interrupt request status for all levels in the
83. interrupt source control register be sure DI state ELECTRONICS 6 37 INSTRUCTION SET S3F80JB DIV Divide Unsigned DIV dst src Operation dst src dst UPPER lt REMAINDER dst LOWER lt QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destination The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect Both operands are treated as unsigned integers Flags C Set if the V flag is set and quotient is between 28 and 29 1 cleared otherwise Z Set if divisor or quotient 0 cleared otherwise S Set if MSB of quotient 1 cleared otherwise V Set if quotient is gt 28 or if divisor 0 cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src opc SIC dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Examples Given RO 10H R1 03H R2 40H register 40H 80H DIV RRO R2 gt RO R1 40H DIV RRO R2 gt RO R1 20H DIV RRO 20H gt RO R1 80H In the first example destination working register pair RRO contains the values 10H RO and 03H R1 and register R2 contains th
84. is pending when read NOTE A timer 2 overflow interrupt pending condition is automatically cleared by hardware However the timer 2 match capture interrupt IRQS vector F2H must be cleared by the interrupt service routine S W ELECTRONICS 4 43 S3F80JB INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 S3F8 series interrupt structure has three basic components levels vectors and sources The SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a specific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals and I O blocks can issue interrupt requests In other words peripheral and I O operations are interrupt driven There are eight possible interrupt levels IRQO IRQ7 also called level 0 level 7 Each interrupt level directly corresponds to an interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3F80JB interrupt structure recognizes eight interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are simply identifiers for the interrupt levels that are recognized by the CPU The relative priority of different inte
85. means start operation and is not cleared even though next instruction is executed So user should be careful to set FMUSR when executing sector erase for no effect on other flash sectors ELECTRONICS 15 9 EMBEDDED FLASH MEMORY INTERFACE PROGRAMMING TIP Sector Erase Case1 Erase one sector ERASE_ONESECTOR ERASE_STOP FMUSR 0A5H FMSECH 40H FMSECL 00H FMCON 10100001B FMUSR 00H 53 80 User program mode enable Set sector address 4000H sector 128 among sector 0 511 Select erase mode enable amp Start sector erase User program mode disable Case2 Erase flash memory space from Sector n to Sector n m Pre define the number of sector to erase ERASE 15 10 LD SecNumH 00H LD SecNumL 128 LD R6 01H LD R7 7DH LD R2 SecNumH LD R3 SecNumL CALL SECTOR_ERASE XOR P44H1111111B INCW RR2 LD SecNumH R2 LD SecNumL R3 DECW RR6 LD R8 R6 OR R8 R7 CP R8 00H JP NZ ERASE_LOOP Set sector number Selection the sector128 base address 4000H Set the sector range m to erase into High byte R6 and Low byte R7 Display ERASE_LOOP cycle ELECTRONICS S3F80JB SECTOR_ERASE LD NOCARRY ERASE_START ERASE_STOP ELECTRONICS R12 SecNumH LD R14 SecNumL MULT RR12 80H MULT RR14 80H ADD 13 14 LD R10 R13 LD R11 R15 LD FMUSR 0A5H LD FMSECH R10 LD FMSECL R11 LD FMCON 10100001B LD FMUSR 00H EMBEDDED FLASH M
86. of Vectored Interr pts 2 2 taie dne vie a asa hac nar qoi Hed ds 5 17 Instruction Pointer IP irrito i E EEE i E EE a ak E 5 17 Fast Interrupt Pro6essitig x coop ker io xD Ug e tg Re ge ga e qe Ege er pen eek 5 17 Chapter 6 Instruction Set OVGIVIOW i e met iae epe p bed 6 1 Flags Register FLAGS recuerde patel 6 6 Flag Descriptions iser 6 7 InstructionSet erri ineo eet yeas dro nde ns tant eec 6 8 Condition Codes aree idiot e du te ieri eerie 6 12 Instruction Descriptions recreo ria edet eater ee eee e Pangan 6 13 Chapter 7 Clock Circuit OVENI OWS en o e a I 7 1 System Cl cK CIrCUult eca ith Ee eee dete Dt het oin 7 1 Clock Status During Power Down 7 2 System Clock Control Register 7 3 vi S3F80JB MICROCONTROLLER Table of Contents continued Chapter 8 RESET EE 8 1 Reset SOUICOS hne edt ec vei eh ne ade egeta rendo 8 1 Heset 3 teer edet eid A 8 4 External Reset E T 8 4 Watch Dog Timer FIeset 2 eid rrt exter ep recede ap ee ite pror eg 8 4 UE RE ER
87. or lt 128 3 Decimal Adjust Flag Bit D 0 Add operation completed 1 Subtraction operation completed 2 Half Carry Flag Bit H No carry out of bit 3 or no borrow into bit 3 by addition or subtraction Addition generated carry out of bit 3 or subtraction generated borrow into bit 3 4 Fast Interrupt Status Flag Bit FIS Interrupt return IRET in progress when read Fast interrupt service routine in progress when read 0 Bank Address Selection Flag Bit BA 0 Bank 0 is selected Bank 1 is selected ELECTRONICS 4 11 CONTROL REGISTERS S3F80JB FMCON riash Memory Control Register EFH Seti Bank1 Reset Value 0 0 0 0 0 Read Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Flash Memory Mode Selection Bits Programming mode Erase mode Hard Lock mode NOTE Not used for S3F80JB 3 1 Not used for S3F80JB 0 Flash Operation Start Bit available for Erase Hard Lock mode only Operation stop Operation start auto clear bit NOTE Hard Lock mode is one of the flash protection modes Refer to page 15 18 4 12 ELECTRONICS S3F80JB CONTROL REGISTERS FMSECH Flash Memory Sector Address Register High Byte Seti Bank1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory Sector Address High Byte Note The high byte flash memory sec
88. programmable pins Configurable to input mode or output mode Pin circuits are either push pull or n channel open drain type I O port with bit programmable pins Configurable to input or push pull output mode Pull up resistors can be assigned by software Pins can be assigned individually as external interrupt inputs with noise filters interrupt enable disable and interrupt pending control SED amp R note circuit built in P2 4 P2 7 for STOP releasing Also P2 4 P2 7 can be assigned individually as analog input pins for Comparator Circuit 44 Pin Shared Type No Functions 30 37 Ext INT INTO INT3 INT4 Ext INT 5 8 9 CINO CIN3 I O port with bit programmable pin Configurable to input mode push pull output mode or n channel open drain output mode Input mode with a pull up resistor can be assigned by software This port 3pin has high current drive capability Also P3 0 can be assigned individually as an output pin for TOPWM or input pin for TOCAP In the tool mode P3 0 is assigned as serial MTP interface pin SDAT TOPWM TOCAP SDAT NOTE SED amp R means STOP Error Detect amp Recovery The Stop Error Detect amp Recovery Circuit is used to release stop mode and prevent abnormal stop mode Refer to page 8 11 1 8 ELECTRONICS S3F80JB PRODUCT OVERVIEW Table 1 2 Pin Descriptions of 44 QFP Continued Pin Pin Description Circuit 44 Pin Names
89. protection disable Before execution the program memory code user can set the smart option bits according to the hardware option for user to want to select ROM Address 003CH Not used ROM Address 003DH Not used ROM Address 003EH ISP Reset Vector Change Bit pru used ISP Protection Size 0 OBP Reset vector address Selection Bits 9 1 Normal vector address 100H 00 256 bytes 01 512 bytes ISP Reset Vector Address Selection Bits 2 10 1024 bytes 00 200H ISP Area size 256 bytes 11 2048 bytes 01 300H ics Area size 512 bytes SP Protection Enable Disable Bit 9 10 500H ISP Area size 1024 bytes 0 Enable Not erasable 11 900H ISP Area size 2048 bytes 1 Disable Erasable ROM Address 003FH Frequency Selection Bits Operating Frequency Range IPOR LVD Control Bit 111110 1MHz 4MHz IPOR enable 11111 1MHz 8MHz LVD disable in the stop mode 9 1 disable LVD enable in the stop mode 9 Figure 2 2 Smart Option ELECTRONICS 2 3 2 4 S3F80JB ADDRESS SPACES NOTES By setting ISP Reset Vector Change Selection Bit 3EH 7 to 0 user can have the available ISP area If ISP Reset Vector Change Selection Bit 3EH 7 is 1 SEH 6 and 3EH 5 are meaningless If ISP Reset Vector Change Selection Bit 3EH 7 is 0 user must change ISP reset vector address from 0100H to some address which user want to set reset address 0200H 0
90. the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of register 1BH from OFH to 10H ELECTRONICS S3F80JB INSTRUCTION SET INCW Increment Word INCW Operation Flags Format Examples NOTE dst dst dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 AO RR Al IR Given RO 1AH R1 02H register 02H OFH and register 03H OFFH INCW RRO gt RO 1AH R1 03H INCW gt Register 02H 10H register O3H 00H In the first example the working register pair RRO contains the value 1AH in register RO and 02H in register R1 The statement INCW RRO increments the 16 bit destination by one leaving the value in register R1 In the second example the statement NCW R1 uses Indirect Register IR addressing mode to increment the contents of general register 03H from OFFH to 00H and register 02H from OFH to 10H A system malfunction may occur if you use a Zero Z flag FLAGS 6 result together with an INCW instruction To avoid this problem we recomm
91. to LDC example except that external data memory is accessed NOTE LDE command is not available because an external interface is not implemented for the S3F80JB Figure 3 9 Indexed Addressing to Program or Data Memory ELECTRONICS 3 9 ADDRESSING MODES 53 80 DIRECT ADDRESS DA In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external data memory LDE if implemented Program or Data Memory Memory Address Program Memory Used Upper Address Byte Lower Address Byte as OPCODE LSB Selects Program Memory or Data Memory 0 Program Memory 1 Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 Identical operation to LDC example except that external data memory is accessed LDE R5 1234H NOTE LDE command is not available because an external interface is not implemented for the SSF80JB Figure 3 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS ADDRESSING MODES S3F80JB DIRECT ADDRESS MODE Conti
92. to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation ELECTRONICS S3F80JB INSTRUCTION SET TM Test Under Mask TM Operation Flags Format Examples dst src dst AND src This instruction tests selected bits in the destination operand for a logic zero value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 73 r Ir opc src dst 3 6 74 R R 75 R IR opc dst src 3 6 76 R IM Given RO OC7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H TM RO R1 RO 0C7H R1 02H Z 0 TM RO R1 gt RO 0C7H R1 02H register 02H 23H Z 0 00H01H gt Register 00H 2BH register 01H 02H 2 0 00H 01H Register 00H 2BH register 01H 02H register 02H 23H Z 0 00H f54H gt Register 00 2BH Z 1 In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement TM RO R1 tests
93. upper slice and RP1 to the lower slice Because a register pointer can point to the either of the two 8 byte slices in the working register block you can define the working register area very flexibly to support program requirements PROGRAMMING TIP Setting the Register Pointers SRP 70H RPO lt 70H RP1 lt 78H SRP1 48H RPO lt nochange RP1 lt 48H SRPO RPO lt RP1 lt nochange CLR RPO RPO lt OOH RP1 lt nochange LD RP1 0F8H RPO lt nochange RP1 lt OF8H Register File Contains 32 8 Byte Slices 00001XXX OFH R15 8 Byte Slice 16 byte 08H contiguous 07H working 00000XXX 8 Byte Slice register block BU 00H RO Figure 2 7 Contiguous 16 Byte Working Register Block ELECTRONICS 2 11 S3F80JB 11110XXX RPO 00000XXX RP1 8 Byte Slice mE Register File Contains 32 8 Byte Slices 07H R15 00H RO ADDRESS SPACES 16 byte non contiguous working register block Figure 2 8 Non Contiguous 16 Byte Working Register Block PROGRAMMING Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H 85H using the register pointer The register addresses 80H through 85H contains the values 10H 11H 12H 13H 14H and 15 H respectively SRPO ADD ADC ADC ADC ADC 80H RO R1 RO R2 RO R3 RO R4 RO R5 RPO lt 80H RO 5 TT 4
94. use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON But we recommend you should use it to prevent the chip malfunction 8 14 ELECTRONICS S3F80JB RESET HARDWARE RESET VALUES Tables 8 3 list the reset values for CPU and system registers peripheral control registers and peripheral data registers following a reset operation The following notation is used to represent reset values 1 0 shows the reset bit value as logic one or logic zero respectively means that the bit value is undefined after a reset Adash means that the bit is either not used or not mapped but a 0 is read from the bit position Table 8 3 Set 1 Bank 0 Register Values After Reset 2 Clock Control Register 1 Register Pointer 0 x ojijloijoij jo I ojo k Register Pointer 1 Location D8H SPH is not mapped Stack Pointer Low Byte IM S P x Instruction Pointer High Byte D 223 D Port 3 Data Register E4 Port 2 Interrupt Enable Register P2INT Port 2 Interrupt Pending Register P2PND 230 Port 0 Pull up Enable Register POPUR 231 E7H Port 0 Control Register High Byte POCONH 232 E8H Port 0 Control Register Low Byte POCONL E9H
95. value In the example working register R1 contains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECTRONICS 6 39 INSTRUCTION SET S3F80JB El Enable Interrupts Operation Flags Format Example 6 40 SYM 0 lt 1 An El instruction sets bit zero of the system mode register SYM 0 to 1 This allows interrupts to be serviced as they occur assuming they have highest priority If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the El instruction No flags are affected Bytes Cycles Opcode Hex opc 1 4 9F Given SYM OOH El If the SYM register contains the value OOH that is if interrupts are currently disabled the statement El sets the SYM register to 01H enabling all interrupts SYM 0 is the enable bit for global interrupt processing ELECTRONICS S3F80JB INSTRUCTION SET ENTER Enter ENTER Operation SP lt SP 2 SP lt IP IP lt lt IP IP lt 2 This instruction is useful when implementing threaded code languages The contents of the instruction pointer are pushed to the stack The program counter PC
96. versa Flags C Unaffected Z Setif the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to 0 D H Unaffected Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 60 R 61 IR Examples Given R1 07H and register 07H OF1H COM Ri gt R1 OF8H COM QR gt R1 07H register 07H OEH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value OF8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of destination register 07H 11110001B leaving the new value OEH 00001 110B ELECTRONICS 6 29 INSTRUCTION SET S3F80JB CP Compare CP dst src Operation dst src The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison Flags C Setif a borrow occurred src dst cleared otherwise Z Setifthe result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src opc dst src 2 4 A2 r r A3 r Ir opc SIC
97. 0 IRQ7 Interrupt Priority Register R W Controls the relative processing priorities of the interrupt levels The eight levels of the S3F80JB are organized into three groups A B and C Group A is IRQO and IRQ1 group B is IRQ2 IRQ3 and IRQ4 and group C is IRQ5 IRQ6 and IRQ7 Interrupt Request Register This register contains a request pending bit for each interrupt level System Mode Register SYM R W A dynamic global interrupt processing enables disables fast interrupt processing and external interface control an external memory interface is not implemented the S8F80JB microcontroller ELECTRONICS 5 7 INTERRUPT STRUCTURE S3F80JB INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by a specific interrupt level and source The system level control points in the interrupt structure are therefore Global interrupt enable and disable by El and DI instructions or by a direct manipulation of SYM 0 Interrupt level enable disable settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing the part of your application program that handles the interrupt processing be sure to include the necessary register file address register pointer information El S Q Interrupt Request Register Polling Read onl nRESET 7 R
98. 01B the statement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values are not identical the zero flag bit Z is cleared in the FLAGS register OD5H ELECTRONICS S3F80JB INSTRUCTION SET BITC Complement BITC Operation Flags Format Example dst b dst b lt NOT dst b This instruction complements the specified bit within the destination without affecting any other bits in the destination Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected IOZONO Bytes Cycles Opcode Addr Mode Hex dst dst b 0 2 4 57 rb NOTE n the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITC o R1 05H If working register R1 contains the value 07H 000001 11B the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 00000101 in register R1 Because the result of the complement is not 0 the zero flag Z in the FLAGS register OD5H is cleared ELECTRONICS 6 19 INSTRUCTION SET S3F80JB BITR sit Reset BITR Operation Flags Format Example 6 20 dst b dst b 0 The BITR instruction clears the specified bit within the destination without affecting an
99. 03DH and is used as smart option ROM cell If you use the vector address area to store program code be careful to avoid overwriting vector addresses stored in these locations The program memory address at which program execution starts after reset is 0100H default If you use ISPTM sectors as the ISPTM software storage the reset vector address can be changed by setting the Smart Option Refer to Figure 2 2 Decimal 65 536 384 256 128 byte Internal RAM Internal Program S3F80JB 64Kbyte Memory 01FFH 02FFH 04 08FFH OFFH 03CH Figure 2 1 Program Memory Address Space NOTES 1 The size of ISP sector can be varied by Smart Option Refer to Figure 2 2 According to the smart option setting related to the ISP ISP reset vector address can be changed one of addresses to be select 200H 300H 500H or 900H 2 ISPTM sector can store On Board Program Software Refer to chapter 15 Embedded Flash Memory Interface 2 2 ELECTRONICS S3F80JB ADDRESS SPACES SMART OPTION Smart option is the program memory option for starting condition of the chip The program memory addresses used by smart option are from 003CH to 003FH The 53 80 only use 003EH and 003FH User can write any value in the not used addresses 003CH and 003DH The default value of smart option bits in program memory is OFFH IPOR disable LVD enable in the stop mode Normal reset vector address 100H ISP
100. 16 x 1 fosc Figure 18 9 Stop Mode Release Timing When Initiated by a LVD Table 18 5 Input Output Capacitance Ta 25 C to 85 C Capacitance Vpp 0 V unmeasured pins Output Cour are connected to Vas Capacitance Capacitance Table 18 6 A C Electrical Characteristics TA 25 to 85 Parameter Symbol Conditions Typ Max Unit Interrupt Input tiNTH P0 0 P0 7 2 0 2 7 300 m ns High Low Width tINTL Vpp 3 6 V nRESET Input Input 1000 Low Width 3 6 V ELECTRONICS 18 9 ELECTRICAL DATA 8MHz 53 80 NOTE unit tcPU means one CPU clock period Figure 18 10 Input Timing for External Interrupts Port 0 and Port 2 Reset Occur Back up Mode Normal Normal Operating Mode Stop Mode Operating Y 4 Mode Oscillation Stabilization Time nRESET NOTE twarr is the same as 4096 x 16 x 1 fosc Figure 18 11 Input Timing for Reset nRESET Pin 18 10 ELECTRONICS S3F80JB ELECTRICAL DATA 8MHz Table 18 7 Comparator Electrical Characteristics 25 C to 85 Vpp 1 95 V to 3 6 V Vss 0 V V Input voltage range Reference voltage range Input voltage Internal Accuracy External Table 18 8 Oscillation Characteristics TA 25 C to 85 Crystal CPU clock oscillation 1 MHz frequency 1 8 MHz Ceramic CPU clock oscillation XIN frequency
101. 2 FX CADATAL 2 ius CADATAL 22 tuigH 15 us 2 FX 2 x 1us 13 Method 2 When CAOF 1 ligu 15 us CADATAL 2 FX CADATAL 2 1us CADATAL 13 ti ow 24 us 2 FX 2 x 1us 22 12 4 ELECTRONICS S3F80JB OH 100H 200H Counter A Clock CAOF 0 CADATAL 01 FFH CADATAH 00H CAOF 0 CADATAL 00H CADATAH 01 FFH CAOF 0 CADATAL 00H CADATAH 00H CAOF 1 CADATAL 00H CADATAH 00H OH 100H 200H Counter A Clock CAOF 1 CADATAL DEH CADATAH 1EH CAOF 0 CADATAL DEH CADATAH 1EH CAOF 1 CADATAL 7EH CADATAH 7EH CAOF 0 CADATAL 7EH CADATAH 7EH Figure 12 4 Counter A Output Flip Flop Waveforms in Repeat Mode ELECTRONICS COUNTER A 12 5 COUNTER 53 80 PROGRAMMING To generate 38 kHz 1 3duty signal through P3 1 This example sets Counter A to the repeat mode sets the oscillation frequency as the Counter A clock source and CADATAH and CADATAL to make a 38 kHz 1 3 Duty carrier frequency The program parameters are IP 17 59 us mm 37 9 kHz 1 3 duty Counter A is used in repeat mode Oscillation frequency is 4 MHz 0 25 us 8 795 us 0 25 us 35 18 CADATAL 17 59 us 0 25 us 70 36 Set P3 1 C MOS push pull out
102. 2 D C Electrical Characteristics Continued TA 25 Cto 4 85 C Vpp 1 7 V to 3 6 V Parameter Conditions Max Unit mA Supply Current Ipp1 Operating Mode note Vpp 3 6 V 4 MHz crystal Ipp2 Idle Mode 2 5 4 MHz crystal Ipps Stop Mode 1 6 LVD OFF Vpp 3 6 V Stop Mode 20 LVD ON Vpp 3 6 V NOTE Supply current does not include current drawn through internal pull up resistors or external output current loads Table 17 3 Characteristics of Low Voltage Detect Circuit 25 C to 85 Symbol Hysteresys voltage of LVD AV Slew Rate of LVD Low level detect voltage for LVD back up mode Low level detect voltage for LVD_FLAG 1 95 2 15 flag indicator NOTE The voltage gap between LVD and LVD FLAG is 250mV Table 17 4 Data Retention Supply Voltage in Stop Mode TA 25 C to 85 C Parameter Data retention supply voltage Data retention supply current Stop Mode 17 4 ELECTRONICS S3F80JB ELECTRICAL DATA 4MHz TYPICAL VOL vs IOL VDD 3 3V TYPICAL VOL VS VDD IOL 12mA 85 sama 25 won 25 C 150 100 50 0 1 800V 2 400V 3 000V VDD V 3 600V IOL mA Figure 17 1 Typical Low Side Driver Sink Characteristics P3 1 only TYPICAL VOL vs IOL VDD 3 3V TYPICAL VOL VS VDD IOL 5mA 1 00 250 85
103. 2 17 2 13 4 Bit Working Register Addressing Example ee 2 17 2 14 8 Bit Working Register Addressing eee 2 18 2 15 8 Bit Working Register Addressing Example nee 2 19 2 16 Stack Operations inito RD ora Top PD 2 20 3 1 Register Addressilig ied er eee divin eee obs dete eoe 3 2 3 2 Working Register 3 2 3 3 Indirect Register Addressing to Register 22200 11 3 3 3 4 Indirect Register Addressing to Program Memory 3 4 3 5 Indirect Working Register Addressing to Register 3 5 3 6 Indirect Working Register Addressing to Program or Data 3 6 3 7 Indexed Addressing to Register 3 7 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 3 9 Indexed Addressing to Program or Data 3 9 3 10 Direct Addressing for Load 3 10 3 11 Direct Addressing for Call and Jump Instructions 3 11 3 12 Indirect Addressing deeds rte ot Lieder ates See 3 12 3 13 Relative Addressing dede 3 13 3 14 I
104. 237 Flash Memory User Programming Enable Register FMUSR 238 Flash Memory Control Register FMCON 239 Not mapped in address FOH to OFFH NOTE You cannot use a read only register as a destination for the instructions OR AND LD or LDB ELECTRONICS 4 CONTROL REGISTERS S3F80JB Bit number s that is are appended to the register name for bit addressing Register address Register pus i n Register address d address it or bit function mnemonic Full register name Hexadecimal Bank FLAGS System Flags Register D5H Seti Bit Identifier Reset Value Read Write Carry Flag Bit C 0 Operation dose not generate a carry or borro 1 Operation generates carry out or borrow into high order bit7 Zero Flag Bit Z 0 Operation result is a non zero value 1 Operation result is zero Sign Flag Bit S 0 Operation generates positive number MSB 1 Operation generates negative number MSB R Read only Description of the RESET value notation W Write only effect of specific Not used R W Read write bit settings x Undetermind value Not used 0 2 Logic zero 1 Logic one Addressing mode or Bit number modes you can use to MSB Bit 7 modify register values LSB Bit 0 Figure 4 1 Register Description Format 4 4 ELECTRONICS S3F80JB CONTROL REGISTERS BTCON Basic Timer Control Register Seti Reset Val
105. 27H QR1 ELECTRONICS S3F80JB DEC Decrement DEC Operation Flags Format Examples dst dst lt 051 1 The contents of the destination operand are decremented by one C Unaffected Z Set ifthe result is 0 cleared otherwise S Set if result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D H Unaffected Unaffected Bytes Cycles opc dst 2 Given R1 03H and register 03H 10H DEC Ri gt R1 02H DEC QR gt Register 03H OFH INSTRUCTION SET Opcode Hex 00 01 Addr Mode dst R IR In the first example if working register R1 contains the value the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements the value contained in the destination register by one leaving the value OFH ELECTRONICS INSTRUCTION SET S3F80JB DECW Decrement Word DECW Operation Flags Format Examples NOTE 6 36 dst dst lt dst 1 The contents of the destination location which must be an even address the operand following that location are treated as a single 16 bit value that is decremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H
106. 3 6 V Oscillator Test Condition Main crystal fosc gt 400 kHz Main ceramic Oscillation stabilization occurs when Vpp is equal to the minimum oscillator voltage range External clock Xiy input High and Low width tyy t main system Oscillator twarr when released by a reset 1 stabilization wait time twart when released by an interrupt 2 x ms NOTES 1 fosc is the oscillator frequency 2 The duration of the oscillation stabilization time when it is released by an interrupt is determined by the setting in the basic timer control register BTCON 17 12 ELECTRONICS S3F80JB ELECTRICAL DATA 4MHz fosc Main Oscillator Frequency Minimun Instruction Clock 2 MHz 8 MHz 1 5MHz 6 MHz 1MHz 4 MHz 500 kHz 2 MHz 1 MHz 400 kHz Supply Voltage V Minimun Instruction Clock 1 4n x oscillator frequency n 1 2 8 or 16 A 1 7 V 4 MHz Figure 17 12 Operating Voltage Range of S3F80J9 Table 17 9 AC Electrical Characteristics for Internal Flash ROM Ta 25 C to 85 C Fash Witerrase Votage Fash Read Votage Fw Pegenmire me Fe 3m IE DR nm Daa neenon 9 NOTES 1 The programming time is the time during which one byte 8 bit is programmed 2 The Sector erasing time is the time during which all 128 bytes of one sector block is erased 3 In the case of 53 80 9 the chip erasi
107. 3 are respectively stored in CMPREGO CMPREG1 CMPREG2 and CMPREG3 Figure 14 1 Comparator Block Diagram for The S3F80JB 14 2 ELECTRONICS S3F80JB COMPARATOR COMPARATOR OPERATION The comparator compares input analog voltage at CINO CING with an external or internal reference voltage Vggrp that is selected by the register The result is written to the comparison result register CMPREG at address EAH Seti Bank1 The comparison result at internal reference is calculated as follows If 1 Analog input voltage 150 mV If 0 Analog input voltage lt 150 mV To obtain a comparison result the data must be read out from the CMPREG register after Vage is updated by changing the CMOD value after a conversion time has elapsed Analog Input Voltage CINO 3 Reference Voltage VREF Comparision Time CMPCLK x8 gt Comparator Clock fosc 16 fosc 128 Comparision Comparision Start End Comparision Result CMPREG Unknown _ gt 1 14 Unknown __ 0 _ gt Figure 14 2 Conversion Characteristics ELECTRONICS 14 3 COMPARATOR 53 80 Comparator Mode Register E9H Set1 Bank 1 R W 5 4 3 2 0 LSB Not used for S3F80JB Reference Voltage Selection Bits Selected Vref Vdd x N 0 5 16 n 0 to 15 External Internal Reference Selection Bit 0 Internal reference CINO 3 a
108. 300H 0500H or 0900H If the reset vector address is 0200H the ISP area can be assigned from 0100H to 01FFH 256bytes If 0300H the ISP area be assigned from 0100H to O2FFH 512bytes If 0500H the ISP area can be assigned from 0100H to O4FFH 1024bytes If 0900H the ISP area can be assigned from 0100H to O8FFH 2048bytes If ISP Protection Enable Disable Bit is 0 user can t erase or program the ISP area selected by 3EH 1 and 3EH 0 in flash memory User can select suitable ISP protection size by 3EH 1 and 0 If ISP Protection Enable Disable Bit SEH 2 is 1 3EH 1 and 3EH 0 are meaningless If IPOR LVD Control Bit 3FH 7 is 0 IPOR is enabled regardless of operating mode and LVD block is disabled in the STOP mode So the current consumption in the stop mode can be decreased by setting IPOR LVD Control Bit 3FH 7 to 0 Although LVD block is disabled IPOR can make power on reset on the behalf of LVD When CPU wakes up by any interrupts or reset sources CPU comes back normal operating mode and LVD block is re enabled automatically But user can t disable LVD in the normal operating mode If IPOR LVD Control Bit 8FH 7 is 1 LVD block will not be disabled in the STOP mode In this case LVD can make power on reset and IPOR is disabled in the normal operating and STOP mode If Frequency Selection Bits 3FH 6 2 are 11110 operating max frequency is from 1MHz to 4MHz and operating voltage range i
109. 4 FLASH 16 Bit Memory Timer1 Counter Register File 16 Bit P4 0 P4 7 Timer2 Counter Carrier Generator Comparator Counter A Figure 1 2 Block Diagram 44 pin NOTE IPOR can be enabled or disabled by IPOR LVD control bit in the smart option Refer to Figure 2 2 1 4 ELECTRONICS S3F80JB PIN ASSIGNMENTS VSS XOUT XIN TEST P2 5 INT9 CIN1 P2 6 INT9 CIN2 nRESET P2 7 INT9 CIN3 ELECTRONICS P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 Figure 1 3 Pin Assignment Diagram 32 Pin SOP Package o 13 14 LY S3F80JB Top View 32 SOP VDD 31 30 29 P2 4 INT9 CINO 28 P2 3 INT8 27 P2 2 INT7 26 P2 1 INT6 25 P2 0 INT5 PO 7 INT4 PO 6 INT4 PO 5 INT4 PO 4 INT4 PO 3 INT3 PO 2 INT2 PO 1 INT1 PO 0 INTO P3 1 REM TOCK SCLK P3 0 TOPWM TOCAP T1CAP T2CAP SDAT PRODUCT OVERVIEW 1 5 PRODUCT OVERVIEW S3F80JB PIN ASSIGNMENTS Continued PO 3 INT3 PO 2 INT2 P0 1 INT1 PO O INTO PO 4 INT4 P1 3 PO 5 INT4 P1 2 PO 6 INT4 P1 1 PO 7 INT4 S3F80JB 4 7 P4 3 Top View P3 3 T1CAP T2CAP P4 2 P3 2 TOCK P4 1 P1 0 P4 0 44 QFP P2 7 INT9 CIN3 P2 0 INT5 P3 5 P2 1 INT6 P3 4 P2 2 INT7 nRESET a P2 3 INT8 C 1 VDD C 5 Vss 16 XouT 47 XIN C38 TEST CJ 9 P2 4 INT9 CINO CH 2 P3 0 TOPWM TOCAP SDAT C 3 P2 5 INT9 CIN1
110. 5 2 Smart Option 15 4 ELECTRONICS S3F80JB EMBEDDED FLASH MEMORY INTERFACE NOTES 1 By setting ISP Reset Vector Change Selection Bit 3EH 7 to 0 user can have the available ISP area If ISP Reset Vector Change Selection Bit 7 is 1 3EH 6 and 5 are meaningless 2 If ISP Reset Vector Change Selection Bit 3EH 7 is 0 user must change ISP reset vector address from 0100H to some address which user want to set reset address 0200H 0300H 0500H or 0900H If the reset vector address is 0200H the ISP area can be assigned from 0100H to 01FFH 256bytes If 0300H the ISP area can be assigned from 0100H to 2 512bytes If 0500H the ISP area can be from 0100H to O4FFH 1024bytes If 0900H the ISP area be from 0100H to O8FFH 2048bytes 3 If ISP Protection Enable Disable Bit is 0 user can t erase or program the ISP area selected by 3EH 1 and 0 in flash memory 4 User select suitable ISP protection size by 1 and 3EH O If ISP Protection Enable Disable Bit SEH 2 is 1 SEH 1 and 3EH 0 are meaningless Table 15 2 ISP Sector Size Smart Option 003EH ISP Size Selection Bit Area of ISP Sector ISP Sector Size Bit 0 0 100H 1FFH 256 Bytes 256 Bytes 512 Bytes O 100H 4FFH 1024 Bytes 1024 Bytes 2048 Bytes NOTE The area of the ISP sector selected by smart option bit 2 3EH 0 can t be erased and programmed by LDC ins
111. 5 98 2000 XP as its operating system can be used A sophisticated debugging tool is provided both in hardware and software the powerful in circuit emulator OPENice i500 for the S3C7 53 9 and S3C8 microcontroller families Samsung also offers supporting software that includes debugger an assembler and a program for setting options TARGET BOARDS Target boards are available for all the S3C8 S3F8 series microcontrollers All the required target system cables and adapters are included on the device specific target board TB80JB is a specific target board for the 53 80 development PROGRAMMING SOCKET ADAPTER When you program S3F80JB s flash memory by using an emulator OTP MTP writer you need a specific writer socket adapter for SSF80JB In case of SSF80JB there are SA 44QFP and SA 32SOP socket adapters for it s 44 QFP and 32 SOP packages respectively Refer to Flash Application Notes ELECTRONICS 20 1 DEVELOPMENT TOOLS DATA S3F80JB 22 TB80JB TARGET BOARD The TB80JB target board is used for the S8F80JB microcontrollers It is supported by OPENice i500 In Circuit Emulator TB80JBRevi i CABLEs For CONNECTION ok To Open ice500 To Yser nRESET IDLE STOP a gt u5 zaon 473 o God wb we OOO SSS JP10 Y1 SQ EM oo VDDMCU Boarn VDD SS 25 MDS 4 VDD REG 5 Y 2 2222
112. 6 nRESET 1 14 ELECTRONICS S3F80JB ADDRESS SPACE ADDRESS SPACE OVERVIEW The S3F80JB microcontroller has two types of address space Internal program memory Flash memory Internal register file A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addresses and data between the CPU and the register file The S3F80JB has a programmable internal 64 Kbytes Flash ROM An external memory interface is not implemented There are 333 mapped registers in the internal register file Of these 272 are for general purpose use This number includes a 16 byte working register common area that is used as a scratch area for data operations a 192 byte prime register area and a 64 byte area Set 2 that is also used for stack operations Twenty two 8 bit registers are used for CPU and system control and 39 registers are mapped peripheral control and data registers ELECTRONICS 2 1 S3F80JB ADDRESS SPACES PROGRAM MEMORY Program memory Flash memory stores program code or table data The S3F80JB has 64 Kbyte of internal programmable Flash memory The program memory address range is therefore 0000H FFFFH of Flash memory See Figure 2 1 The first 256 bytes of the program memory are reserved for interrupt vector addresses Unused locations 0000H OOFFH except 03CH 03DH O3EH and OSFH in this address range can be used as normal program memory The location
113. 7 00 50 Data Memory 22 Data Memory Stack Stack ELECTRONICS S3F80JB INSTRUCTION SET IDLE idie Operation IDLE Operation Flags Format Example The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src 1 4 6F The instruction IDLE stops the CPU clock but not the system clock ELECTRONICS 6 43 INSTRUCTION SET S3F80JB INC ncrement INC Operation Flags Format Examples 6 44 dst dst dst 1 The contents of the destination operand are incremented by one C Unaffected Z Setif the result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst opc 1 4 rE r r 0toF opc dst 2 4 20 R 21 IR Given RO 1BH register 00H OCH and register 1BH OFH INC RO gt RO 1CH INC OOH gt Register INC RO gt RO 1BH register 01H 10H In the first example if destination working register RO contains the value 1BH the statement INC RO leaves the value 1CH in that same register The next example shows the effect an INC instruction has on register OOH assuming that it contains
114. 9 Stop Mode Release Timing When Initiated by a LVD Table 17 5 Input Output Capacitance Ta 25 C to 85 C Capacitance Vpp 0 V unmeasured pins Output Cour are connected to Vas Capacitance Capacitance Table 17 6 A C Electrical Characteristics TA 25 to 85 Parameter Symbol Conditions Typ Max Unit Interrupt Input tiNTH P0 0 P0 7 2 0 2 7 300 m ns High Low Width tINTL Vpp 3 6 V nRESET Input Input 1000 Low Width 3 6 V ELECTRONICS 17 9 ELECTRICAL DATA 4MHz 53 80 NOTE unit tcPU means CPU clock period Figure 17 10 Input Timing for External Interrupts Port 0 and Port 2 Reset Occur Back up Mode Normal Normal Operating Mode Stop Mode Operating Y 4 Mode Oscillation Stabilization Time nRESET NOTE twarr is the same as 4096 x 16 x 1 fosc Figure 17 11 Input Timing for Reset nRESET Pin 17 10 ELECTRONICS S3F80JB Table 17 7 Oscillation Characteristics TA 25 C to 85 C Oscillator Crystal CPU clock oscillation XIN frequenc C1 3 y co XOUT C2 Ceramic CPU clock oscillation XIN frequency C1 XOUT C2 External Clock Xy input frequency External XIN Clock Open Pin Xo ELECTRONICS ELECTRICAL DATA 4 2 17 11 ELECTRICAL DATA 4MHz 53 80 Table 17 8 Oscillation Stabilization Time Ta 25 to 85 C Vpp
115. B ADDRESS SPACES Selects RPO or RP1 Address OPCODE IIT 4 bit address procides three Register pointer low order bits provides five high order bits TT ETT Together they create 8 bit register address Figure 2 12 4 Bit Working Register Addressing RP1 01110 000 01111 000 Selects RPO R6 OPCODE Instruction poe ee INC R6 Register address 76H Figure 2 13 4 Bit Working Register Addressing Example ELECTRONICS 2 17 S3F80JB ADDRESS SPACES 8 BIT WORKING REGISTER ADDRESSING You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100B This 4 bit value 1100B indicates that the remaining four bits have the same effect as 4 bit working register addressing As shown in Figure 2 13 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RPO or RP1 which then supplies the five high order bits of the final address The three low order bits of the complete address are provided by the original instruction Figure 2 14 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 4 1 selects RP1 and the five high order bits
116. CABLE Connect I Between Target Board Connect Board J1A JP2 100 Pin Connector TA SAM 8 8 MAIN_MODE EVA_MODE 144 QFP S3E80JB EVA Chip USER MODE e J3 00000 amp Bo Hoo 95 o c JP3 EEE SMDS2 SMDS2 1 50 Pin Connector 50 26 Figure 20 1 TB80JB Target Board Configuration NOTE 1 S3E80JB should be supplied 3 3V So jumpers and switches in both OPENice i500 connect board and target board of S3E80JB TB80JB should be set as like this description In that case regulator in TB80JB is not used 2 The symbol 4 marks start point of jumper signals 20 2 ELECTRONICS S3F80JB DEVELOPMENT TOOLS DATA Table 20 1 Components Consisting of S3F80JB Target Board Block Symbols OPEN i500 Connector JIA Connection debugging signals between emulator and 80JB EVA target board TEST Board Connector J2 Connection between target board and remocon application board RESET Block RESET Push Switch Generation low active reset signal of 80JB EVA chip POWER Block VCC GND S Generation 3 3V with 5V power inserted from external nRESET LED power source or open ice recommend STOP IDLE Display IDLE STOP LED Indicate the status of STOP or IDLE FLASH Serial Writing J3 Signal for writing flash ROM in tool mode Don
117. CTION SET CCF Complement Carry Flag CCF Operation Flags Format Example C lt NOT C The carry flag C is complemented If C 1 the value of the carry flag is changed to logic zero if 0 the value of the carry flag is changed to logic C Complemented No other flags are affected Bytes Cycles Opcode Hex opc 1 4 EF Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register OD5H changing its value from logic zero to logic one ELECTRONICS 6 27 INSTRUCTION SET CLR clear CLR dst Operation dst lt 0 Flags Format Examples 6 28 The destination location is cleared to 0 No flags are affected Bytes Cycles Opcode Hex dst 2 4 BO B1 Given Register 00 4FH register 01H 02H and register 02H 5EH CLR OOH gt Register 00H 00H CLR 01H gt Register 01H 02H register 02H OOH S3F80JB Addr Mode dst R IR In Register R addressing mode the statement CLR OOH clears the destination register OOH value to OOH In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to 00H ELECTRONICS S3F80JB INSTRUCTION SET COM Complement COM dst Operation dst lt NOT dst The contents of the destination location are complemented one s complement all 1s are changed to Os and vice
118. DCPI LDEPI LDW MULT S3F80JB MICROCONTROLLER List of Instruction Descriptions Full Register Name Page Number Add With Carry Ala an Solana Sala ee ini ii 6 14 AGG Em 6 15 5i mrt ee etae deett eie dees acer 6 16 BIUAND 23 553 dier eee died cehtiedida dio ditio is 6 17 Bit COmpaLte unie edt eret e de ei eie aede a etes ie 6 18 Bit Complemeht 5 2 5 time pora dim teurer iere niei ien 6 19 BitReS Cte ici iod deed oce uei der iio leere bp din ien 6 20 Bit do i Pee ee var Pe e eo a ee ee rot 6 21 Bit OR m 6 22 Bit Test Jump Relative on 6 23 Bit Test Jump Relative on eene emen 6 24 po 6 25 Call Proced te 2 2 Ere e ree ete eee ee he D o eee 6 26 Complement Carry Flag i pre PLE rp eec ES n 6 27 M AL 6 28 Complement aes 1 td annnm epe edu edis 6 29 n dei epe p e EO deep EP Er ER 6 30 Compare Increment and Jump on 6 31 Compare Increment and Jump on 6 32 Decimal AdJUst terum dte cedente ash edt Led teaser esee ciui eicit ee 6 33 Decimal AdjUsb 2 2 1 i Al oder 6 34 6 35 Decrement Word oi necem presta em H
119. ECL lt Low Address of Sector Set Secotr Base Address R n 4 High Address to Write Low Address to Write Set Address and Data R data 4 8 bit Data FMUSR 0A5H User Program Mode Enable FMCON 01010000 Mode Select LDC lt lt RRi n R data Write data at flash FMUSR 00H User Program Mode Disable SBO Select BankO Finish 1 BYTE Writing Figure 15 9 Byte Program Flowchart in a User Program Mode ELECTRONICS 15 13 EMBEDDED FLASH MEMORY INTERFACE 53 80 FMSECH lt High Address of Sector FMSECL Low Address of Sector R n lt High Address to Write R n 1 lt Low Address to Write R data 4 8 bit Data FMUSR 0A5H 01010000 lt 3 LDC 4 RR n R data YES Write again NO NO FMUSR 4 00H YES Select 0 NO ontinuous address Finish Writing YES INC R n 1 YES R data lt New 8 bit Data Select Bank1 Set Secotr Base Address Set Address and Data User Program Mode Enable Mode Select Write data at flash User Program Mode Disable User Program Mode Disable Check Sector 5 Check Address 5 Increse Address Update Data to Write Figure 15 10 Program Flowchart in a User Program Mode 15 14 ELECTRONICS S3F80JB EMBEDDED FLASH MEMORY INTERFACE PROGRAMMING TIP Programming Case1 1 Byte Programming
120. ECTRONICS S3F80JB COMPARATOR COMPARATOR OVERVIEW P2 4 P2 5 P2 6 and P2 7 can be used as analog input pins for a comparator The reference voltage for the 4 channel comparator can be supplied either internally or externally at P2 7 When an internal reference voltage is used four channels P2 4 P2 7 are used for analog inputs and the internal reference voltage is varied in 16 levels If an external reference voltage is input at P2 7 the other P2 4 P2 5 and 2 6 pins are used for analog inputs When a conversion is completed the result is saved in the comparison result register CMPREG EAH Sett Bank1 Read only The initial values of the CMPREG are undefined and the comparator operation is disabled by a reset The comparator module has the following components Comparator Internal reference voltage generator 4 bit resolution External reference voltage source at P2 7 Comparator mode register CMOD Comparison result register CMPREG Comparison input selection register CMPSEL ELECTRONICS 14 1 COMPARATOR S3F80JB Internal BUS P2 4 CINO P2 5 CIN1 O Comparison P2 6 CIN2 O P2 7 CIN3 Q Result Register CMPREG Ref CMPSEL 0 CMPSEL 1 External CMPSEL 2 CMPSEL 3 Ref Internal VDD 1 2R NOTES 1 INT occurs only for digital input selecting If an analog input any INT doesn t occur 2 The comparison results of CINO CIN1 CIN2 and CIN
121. EMORY INTERFACE Calculation the base address of a target sector The size of one sector is 128 bytes FLAGS 7 NOCARRY INC R12 User program mode enable Set sector address Select erase mode enable amp Start sector erase User program mode disable 15 11 EMBEDDED FLASH MEMORY INTERFACE 53 80 PROGRAMMING A flash memory is programmed in one byte unit after sector erase The write operation of programming starts by LDC instruction The program procedure in user program mode 1 QUO Ie Must erase target sectors before programming Set Flash Memory User Programming Enable Register FMUSR to 10100101B Set Flash Memory Control Register FMCON to 0101000XB Set Flash Memory Sector Address Register FMSECH and FMSECL to the sector base address of destination address to write data Load a transmission data into a working register Load a flash memory upper address into upper register of pair working register Load a flash memory lower address into lower register of pair working register Load transmission data to flash memory location area on LDC instruction by indirectly addressing mode Set Flash Memory User Programming Enable Register FMUSR to 00000000B NOTE In programming mode it doesn t care whether FMCON 0 s value is 0 or 1 15 12 ELECTRONICS S3F80JB EMBEDDED FLASH MEMORY INTERFACE Select Bank1 FMSECH High Address of Sector FMS
122. EMORY INTERFACE FLASH MEMORY SECTOR ADDRESS REGISTERS There are two sector address registers for the erase or programming flash memory The FMSECL Flash Memory Sector Address Register Low Byte indicates the low byte of sector address and FMSECH Flash Memory Address Sector Register High Byte indicates the high byte of sector address The FMSECH is needed for SSF80JB because it has 512 sectors One sector consists of 128 bytes Each sector s address starts XXOOH or XX80H that is a base address of sector is XXOOH or XX80H So bit 6 0 of FMSECL don t mean whether the value is 1 or 0 We recommend that it is the simplest way to load the sector base address into FMSECH and FMSECL register When programming the flash memory user should program after loading a sector base address which is located in the destination address to write data into FMSECH and FMSECL register If the next operation is also to write one byte data user should check whether next destination address is located in the same sector or not In case of other sectors user should load sector address to FMSECH and FMSECL Register according to the sector Refer to page 15 16 PROGRAMMING TIP Programming Flash Memory Sector Address Register FMSECH ECH Set1 Bank 1 R W Flash Memory Sector Address High Byte NOTE High Byte flash memory sector address pointer value is the higher eight bits of the 16 bit pointer address Figure 15 5 Flash
123. ET NOP No Operation NOP Operation Flags Format Example No action is performed when the CPU executes this instruction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration No flags are affected Bytes Cycles Opcode Hex ope 1 4 FF When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ELECTRONICS 6 61 INSTRUCTION SET S3F80JB OR Logical OR OR Operation Flags Format Examples 6 62 dst src dst lt dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination The contents of the source are unaffected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a 0 is stored C Unaffected Z Setif the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 43 r Ir opc SIC dst 3 6 44 R R 45 R IR opc dst src 3 6 46 R IM Given RO 15H R1 2AH R2 01H register 00H 08H register 01H 37H and register 08H OR RO R1 gt RO 3FH R1 2AH OR R0 R2 gt RO 37H R2 01H register 01H 37H OR 00H 01H gt Register OOH 3FH register 01H 37H OR 01H 00H
124. ET When the nRESET pin transiting from VIL low input level of reset pin to VIH high input level of reset pin the reset pulse is generated on the condition of VDD VLVD in any operation mode Watch Dog Timer WTD When watchdog timer enables in normal operating a reset is generated whenever the basic timer overflow occurs Low Voltage Detect LVD When IPOR LVD Control Bit smart option bit 7 O3FH is set to 1 and VDD is changed in condition for LVD operation regardless of operation mode reset occurs Although IPOR LVD Control Bit smart option bit 7 O3FH is set to 0 if the operation mode is not in STOP mode reset signal is generated by LVD Internal Power ON Reset IPOR When IPOR LVD Control Bit smart option bit 7 is set to 0 and VDD is changed in condition for IPOR operation in STOP Mode a reset is generated External Interrupt INTO INT9 When IPOR LVD Control Bit smart option bit 7 O O3FH is set to 0 and chip is in stop mode if external interrupt is enabled external interrupts by PO and P2 generate the reset signal STOP Error Detection amp Recovery SED amp R When IPOR LVD Control Bit smart option bit 7 is set to 0 and chip is in stop or abnormal state the falling edge input of PO or P2 4 P2 7 generates the reset signal regardless of external interrupt enable disable ELECTRONICS 8 1 RESET S3F80JB STO IPOR LVD Contorl Bit 1 smar
125. H 02H gt SUB 01H 90H gt SUB 01H 65H gt R1 OFH R2 03H R1 08H R2 03H Register 01H Register 01H Register 01H Register 01H register 02H 17H register 02H 91H S and V 1 OBCH 5 1 V 0 In the first example if working register R1 contains the value 12H and if register R2 contains the value 03H the statement SUB R1 R2 subtracts the source value 03H from the destination value 12H and stores the result OFH in destination register R1 ELECTRONICS S3F80JB INSTRUCTION SET SWAP swap Nibbles SWAP Operation Flags Format Examples dst dst 0 3 lt gt dst 4 7 The contents of the lower four bits and upper four bits of the destination operand are swapped C Undefined Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 FO R F1 IR Given Register 00H 3EH register 02H 03H and register O3H OA4H SWAP 00H gt Register OOH OE3H SWAP 02H gt Register 02H 03H register 03H 4AH In the first example if general register OOH contains the value 3EH 00111110B the statement SWAP 00H swaps the lower and upper four bits nibbles in the OOH register leaving the value OE3H 11100011B ELECTRONICS 6 83 INSTRUCTION SET S3F80JB TCM rest Complem
126. High Byte Flash Memory Sector Address EDH 0 Register Low byte FMUSR 238 Enable Register ms em o o 9 9 l0 NOTES P345CON will be initialized as 50H to set P3 4 and P3 5 into open drain output mode after reset operation S3F80JB has PACONH P4CONL and P4CON as port4 control registers PACONH and P4CONL will be initialized as the C MOS input with pull up mode after reset On the other hand PACON will be initialized as open drain output mode After reset status of port4 is decided by P345CON 0 bit So port4 reset status will be initialized as open drain output mode po ELECTRONICS 8 17 RESET S3F80JB Table 8 5 Reset Generation According to the Condition of Smart Option Mode Reset Source Smart option7th bit 3FH 1 0 Reset Pin O Reset O Reset Watch Dog Timer Enable O Reset O Reset Normal IPOR X Continue X Continue Operating LVD O Reset O Reset External Interrupt El PO and P2 X External ISR X External ISR External Interrupt DI PO and X Continue X Continue P2 Reset Pin O Reset O Reset Watch Dog Timer Enable X STOP X STOP IPOR X STOP O STOP Release and Stop Reset Mode LVD O STOP Release and X STOP Reset External Interrupt El Enable PO X STOP Release and O STOP Release and and P2 External ISR Reset SED amp R PO amp P2 4 2 7 X STOP Release and O STOP R
127. INDIRECT REGISTER ADDRESSING MODE Continued 53 80 Register File MSB Points to RPO or RP1 RPO or RP1 Selected RP points to start of working register block Program Memory 4 bit Working Register Address Register Pair Next 2 bit Point to Working Register Pair 1 of 4 dst OPCODE Example Instruction References either Program Memory or Data Memory 16 Bit address points to program memory or data memory Program Memory or Data Memory LSB Selects Value used in OPERAND Instruction Sample Instructions LCD R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 External data memory access NOTE LDEcommand is not available because an external interface is not implemented for the S3F80JB Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS S3F80JB ADDRESSING MODES INDEXED ADDRESSING MODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory if implemented You cannot however access locations COH FFH in set 1 using indexed addressing In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integ
128. IP THOU 6 36 Divide Unsighed see eoe prete eer te ott eth 6 38 Decrement and Jump if 7 2 eene 6 39 Enable Interrupts eii eiie t aed tetti 6 40 pipe tepido I iim aam 6 41 A 6 42 Idle Operation PC 6 43 Incremieht 0 4 tli bac alii ee ale aot Alden dant dete dde ee Tito ide 6 44 Iricrement ge oC pee Legi DO D 6 45 Pe cre Pe REP 6 46 AD 6 47 Jump Relative act cite epe eel pie Ee ote 6 48 6 49 6 50 E6ad BIt iie eee eda utet ede deii detti desee cdd 6 51 M usa dre CET 6 52 Load MOTITIOEy tesa cad est cal af 6 53 Load Memory and nennen 6 54 Load Memory and Increment esee nennen 6 55 Load Memory with 4 6 56 Load Memory with Pre Increment sse rennen 6 57 LOA niei emu abe eain E 6 58 Multiply Unsigned 1 12 21 ceed fdas cede crx ere bee i RS knee 6 59 xxi List of Instruction Descriptions Continued Instruction Full Register Name Page Mnemonic Number NEXT MI testes Sha Ag ee ae ea E
129. If general register OOH contains the value 01H and register 01H the value 70H the statement POPUI 02H 00H loads the value 70H into the destination general register 02H The user stack pointer register 00H is then incremented by one changing its value from 01H to 02H ELECTRONICS 6 65 INSTRUCTION SET S3F80JB PUSH Push To Stack PUSH Operation Flags Format Examples 6 66 src SP lt SP 1 QSP lt src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the decremented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register 4FH OAAH SPH OOH and SPL OOH PUSH 40H gt Register 40H 4FH stack register OFFH 4FH SPH OFFH SPL OFFH PUSH 40H gt Register 40H 4FH register 4 OAAH stack register OFFH OAAH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value OOOOH and general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of register 40H into location OFFFFH and adds this new value to the top of the stack ELECTRONICS S3F80JB INSTRUCTION SET PUSHUD Pu
130. L 237 R W RIW RIW RIW Port 0 Interrupt Pending Register 2 R W I ITI ITI N Az I m I T E m Im rm 221 222 223 224 225 226 227 228 229 230 231 232 233 34 m UJ as Port 1 Control Register I mim mjm E 2 2 2 2 38 39 40 41 42 N I 4 2 ELECTRONICS S3F80JB CONTROL REGISTERS Table 4 1 Mapped Registers Continued Register Name mnemonic Hex nw Location FCH is not mapped Interrupt Priority Register 255 RW NOTE You cannot use a read only register as a destination for the instructions OR AND LD or LDB Table 4 2 Mapped Registers Bank1 Set1 Register Name Mnemonic Decimal Hex RW LVD Control Register LVDCON 224 Port 3 4 5 Control Register P345CON 225 Port 4 Control Register High Byte P4CONH 226 Port 4 Control Register Low Byte P4CONL 227 E3 R W Timer 2 Counter Register High Byte T2CNTH 228 Timer 2 Counter Register Low Byte T2CNTL 229 Timer 2 Data Register High Byte T2DATAH 230 Timer 2 Data Register Low Byte T2DATAL 231 Timer 2 Control Register T2CON 232 E8 R W Comparator Mode Register CMOD 233 Comparison Result Register CMPREG 234 Comparator Input Selection Register CMPSEL 235 EB R W Flash Memory Sector Address Register High Byte FMSECH 236 Flash Memory Sector Address Register Low Byte FMSECL
131. Mode Hex dst src opc src dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Given Register 00H 20H register 01H register 02H 09H register 03H 06H MULT 00H 02H gt Register OOH 01H register 01H 20H register 02H 09H MULT 00H 01 Register OOH OOH register 01H OCOH MULT 00H 30H gt Register OOH 06H register 01H OOH In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register OOH of the register pair OOH 01H by the source register 02H operand 09H The 16 bit product 0120H is stored in the register pair OOH 01H ELECTRONICS 6 59 INSTRUCTION SET S3F80JB NEXT Next NEXT Operation Flags Format Example Address PC lt Q IP IP lt IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two No flags are affected Bytes Cycles Opcode Hex opc 1 10 OF The following diagram shows one example of how to use the NEXT instruction Before After Address Data 0045 Data Address Data Address Data PC 0120 43 Address H 01 PC 0130 43 Address 44 AddressL 10 44 Address L 45 Address H 45 Address H 120 Next 130 Routine Memory Memory 6 60 ELECTRONICS S3F80JB INSTRUCTION S
132. NSTRUCTION SET S3F80JB RLC Rotate Left Through Carry RLC Operation dst dst 0 lt C C dst 7 dst n 1 lt dst n n 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C the initial value of the carry flag replaces bit zero Flags Format Examples 6 72 C Setif the bit rotated from the most significant bit position bit 7 was 1 Z Setifthe result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 10 R 4 11 IR Given Register 00H OAAH register 01H 02H and register 02H 17H C 0 RLC 00H gt Register 00H 54H C 1 RLC 01H gt Register 01H 02H register 02H 2EH C 0 In the first example if general register 00H has the value OAAH 10101010B the statement RLC 00H rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H leaving the value 55H 01010101B The MSB of register OOH resets the carry flag to 1 and sets the overflow flag ELECTRONICS S3F80JB INSTRUCTION SET RR Rotate Right RR Operation
133. OL VDD 3 3V 250 TYPICAL VOL VS VDD IOL 5mA 1 00 85 ais 22590 0 80 200 25 C 0 60 180 0 40 100 6 DEMNM lt 75 5 0 2 2 0 20 50 bod 3 gt 0 00 0 10 20 30 40 1 800V 2 400V 3 000V 3 600V IOL mA VDD V Figure 18 2 Typical Low Side Driver Sink Characteristics P3 0 and P2 0 2 3 NOTE Figure 18 1 and 18 2 are characterized and not tested on each device ELECTRONICS 18 5 ELECTRICAL DATA 8MHz 53 80 TYPICAL VOL vs IOL VDD 3 3V TYPICAL VOL VS VDD IOL 12mA 1 800V 2 400V 3 000V 3 600V IOL mA VDD V Figure 18 3 Typical Low Side Driver Sink Characteristics Port0 Port1 P2 4 2 7 P3 4 P3 5 and Port4 TYPICAL VDD VOH VDD 3 3V TYPICAL VDD VOH VS VDD IOHz 6mA IOH mA VDD V Figure 18 4 Typical High Side Driver Source Characteristics P3 1 only NOTE Figure 18 3 and 18 4 are characterized and not tested on each device 18 6 ELECTRONICS S3F80JB ELECTRICAL DATA 8MHz TYPICAL VDD VOH VDD 3 3V TYPICAL VDD VOH VS VDD IOH 2 2mA 48 VDD V Figure 18 5 Typical High Side Drive
134. P2 7 to input or push pull output mode Pull up resistors INT5 INTS8 can be assigned by software Pins can be INT9 assigned individually as external interrupt inputs CINO CIN3 with noise filters interrupt enable disable and interrupt pending control SED amp R note circuit built in P2 P2 7 for STOP releasing Also P2 4 P2 7 can be assigned individually as analog input pins for Comparator P3 0 I O port with bit programmable pin Configurable to TOPWM TOCAP input mode push pull output mode or n channel SDAT open drain output mode Input mode with a pull up resistor can be assigned by software This port 3 pin has high current drive capability Also P3 0 can be assigned individually as an output pin for TOPWM or input pin for TOCAP In the tool mode P3 0 is assigned as serial MTP interface pin SDAT P3 1 I O port with bit programmable pin Configurable to REM input mode push pull output mode or n channel SCLK 1 7 PRODUCT OVERVIEW P0 0 P0 7 P1 0 P1 7 P2 0 P2 3 P2 4 P2 7 53 80 Table 1 2 Pin Descriptions of 44 QFP Pin Description I O port with bit programmable pins Configurable to input or push pull output mode Pull up resistors can be assigned by software Pins can be assigned individually as external interrupt inputs with noise filters interrupt enable disable and interrupt pending control SED amp R note circuit built in PO for STOP releasing I O port with bit
135. PO SRP1 set Register Pointer SRP SRPO SRP1 Operation Flags Format Examples 6 80 src src src If src 1 1 and src 0 Othen RPO 3 7 lt 3 7 If src 1 src 0 1 then RP1 3 7 lt 3 7 If src 1 Oandsrc 0 Othen RPO 4 7 lt 4 7 RPO 3 lt 0 4 7 src 4 7 RP1 3 e 1 The source data bits one and zero LSB determine whether to write one or both of the register pointers RPO and Bits 3 7 of the selected register pointer are written unless both register pointers are selected RPO 3 is then cleared to logic zero and RP1 3 is set to logic one No flags are affected Bytes Cycles Opcode Addr Mode Hex src opc src 2 4 31 IM The statement SRP 40H sets register pointer 0 RPO at location OD6H to 40H and register pointer 1 RP1 at location OD7H to 48H The statement SRPO 50H sets RPO to 50H and the statement SRP1 68H sets RP1 to 68H ELECTRONICS S3F80JB INSTRUCTION SET STOP Stop Operation STOP Operation The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the
136. R2 register 01H 21H register 02H register OAH AND R1 R2 gt R1 02H R2 03H AND R1 R2 gt R1 02H R2 03H AND 01H 02H gt Register 01H 01H register 02H AND 01H 02H gt Register 01H OOH register 02H 03H AND 01H 25H gt Register 01H 21H In the first example destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in register R1 ELECTRONICS S3F80JB INSTRUCTION SET BAND Bit AND BAND BAND Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 AND src b or dst b lt dst b AND src 0 The specified bit of the source or the destination is logically ANDed with the zero bit LSB of the destination or source The resultant bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected IO cO0NO Bytes Cycles Opcode Addr Mode Hex dst src opc dst 3 6 67 Rb ro NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1
137. RAMMING TIP Configuring the Basic Timer This example shows how to configure the basic timer to sample specifications ORG 0100H RESET DI Disable all interrupts LD BTCON 0AAH Disable the watchdog timer LD CLKCON 18H Non divided clock CLR SYM Disable global and fast interrupts CLR SPL Stack pointer low byte O Stack area starts at OFFH SRP 0 Set register pointer EI Enable interrupts MAIN LD BTCON 52H Enable the watchdog timer Basic timer clock fpsc 4096 Clear basic timer counter NOP NOP JP T MAIN 10 10 ELECTRONICS S3F80JB BASIC TIMER and TIMER 0 PROGRAMMING Programming Timer 0 This sample program sets timer 0 to interval timer mode sets the frequency of the oscillator clock and determines the execution sequence which follows a timer 0 interrupt The program parameters are as follows Timer 0 is used in interval mode the timer interval is set to 4 milliseconds Oscillation frequency is 6 MHz General register 60H page 0 60H 61H 62H 63H 64H page 0 is executed after a timer 0 interrupt VECTOR 00FAH TOOVER Timer 0 overflow interrupt VECTOR 00FCH TOINT Timer 0 match capture interrupt ORG 0100H RESET DI Disable all interrupts LD BTCON 0AAH Disable the watchdog timer LD CLKCON 18H Select non divided clock CLR SYM Disable global and fast interrupts CLR SPL Stack pointer low byte 0 Stack area starts at OFFH
138. RR6 1 R8 OCDH R6 10H R7 34H LDEI R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 34H ELECTRONICS 6 55 INSTRUCTION SET S3F80JB LDCPD LDEPD Load Memory with Pre Decrement LDCPD LDEPD Operation Flags Format Examples 6 56 dst src rm m 1 dst lt src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first decremented The contents of the source location are then loaded into the destination location The contents of the source are unaffected LDCPD refers to program memory and LDEPD refers to external data memory The assembler makes Irr an even number for program memory and an odd number for external data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst sre opc src dst 2 14 F2 Irr r Given RO 77H R6 30H and R7 OOH LDCPD RR6 RO RR6 lt RR6 1 77H contents of RO is loaded into program memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 OFFH LDEPD RR6 RO RR6 RR6 1 77H contents of RO is loaded into external data memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 OFFH ELECTRONICS S3F80JB INSTRUCTION SET LDCPI LDEPI Load Memory with Pre Increment
139. Register LVDCON EOH Set1 Bank 1 R W Not used for S8F80J9 S3F80J5 LVD Indicator Flag Bit 0 Vy gt LVD Flag Voltage 12 lt LVD Flag Voltage NOTE LVD Flag Voltage is 2 3V at 8MHz and 2 15V at 4MHz Figure 16 2 Low Voltage Detect Control Register LVDCON ELECTRONICS 16 3 S3F80JB ELECTRICAL DATA 4MHz OVERVIEW ELECTRICAL DATA 4MHz In this section S3F80JB electrical characteristics are presented in tables and graphs The information is arranged in the following order Absolute Maximum Ratings D C Electrical Characteristics Characteristics of Low Voltage Detect Circuit Data Retention Supply Voltage in Stop Mode Stop Mode Release Timing When Initiated by an External Interrupt Stop Mode Release Timing When Initiated by a Reset Stop Mode Release Timing When Initiated by a LVD Input Output Capacitance A C Electrical Characteristics Input Timing for External Interrupts Input Timing for Reset Oscillation Characteristics Oscillation Stabilization Time Operating Voltage Range A C Electrical Characteristics for Internal Flash ROM ELECTRONICS 17 1 ELECTRICAL DATA 4MHz 53 80 Table 17 1 Absolute Maximum Ratings TA 25 C Parameter Conditions Rag Unt mue Yoo tov 999 ve88 Y vo Momas 3 Y pins active eoo O Output Current Low One I O pin active mA All O pins active
140. Retention 1 The programming time is the time during which one byte 8 bit is programmed 2 The Sector erasing time is the time during which all 128 bytes of one sector block is erased 3 In the case of SSF80JB the chip erasing is available in Tool Program Mode only ELECTRONICS 18 13 ELECTRICAL DATA 8MHz 53 80 NOTES 18 14 ELECTRONICS S3F80JB MECHANICAL DATA MECHANICAL DATA OVERVIEW The S3F80JB microcontroller is currently available in a 32 pin SOP and 44 pin QFP package 8 amp 5 o 32 SOP 450A e 0 10 0 25 0 05 8 3 20 30 MAX 2 x E a gt 19 90 0 20 S o N ai a A 7 a 0 10 MAX 2 0 43 0 40 0 10 1 27 e 5 NOTE Dimensions millimeters Figure 19 1 32 Pin SOP Package Dimension ELECTRONICS MECHANICAL DATA 53 80 13 20 0 30 DUNT 44 QFP 1010B 20 10 MAX 2 a o N co bie 0 80 0 20 e 0 80 en 2 05 010 2 30 MAX NOTE Dimensions are in millimeters Figure 19 2 44 Pin QFP Package Dimension 19 2 ELECTRONICS S3F80JB DEVELOPMENT TOOLS DATA DEVELOPMENT TOOLS DATA OVERVIEW Samsung provides a powerful and easy to use development support system on a turnkey basis The development support system is composed of a host system debugging tools and supporting software For a host system any standard computer that employs Win9
141. S3F80JB 8 BIT CMOS MICROCONTROLLERS USER S MANUAL Revision 1 1 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages S3F80JB 8 Bit CMOS Microcontrollers User s Manual Revision 1 1 Publication Number 21 1 S3F 80JB 032006 2006 Samsung Electronics Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical e
142. SET INTO INT9 PO amp P2 INTO INT9 gt 0 P2 4 P2 7 Falling Edgd SED amp R Circuit STOPCO STO IPOR LVD Control Bit 1 smart option bit 7 Figure 8 2 RESET Block Diagram of The S3F80JB ELECTRONICS 8 3 RESET S3F80JB RESET MECHANISM The interlocking work of reset pin and LVD circuit supplies two operating modes back up mode input and system reset input Back up mode input automatically creates a chip stop state when the reset pin is set to low level or the voltage at Vpp is lower than yp When the reset pin is at a high state and the LVD circuit detects rising edge of Vpp on the point yp the reset pulse generator makes a reset pulse and system reset occurs When the operating mode is in STOP mode and IPOR LVD control bit of smart option is 0 the LVD circuit is disabled to reduce the current consumption under 6uA instead of 20uA at Vpp 3 6 V Therefore although the voltage at Vpp is lower than yp the chip doesn t go into back up mode when the operating state is in stop mode and reset pin is High level Vreset gt Vip EXTERNAL RESET PIN When the nRESET pin transiting from Vi low input level of reset pin to Vy high input level of reset pin the reset pulse is generated on the condition of Vpp yp WATCH DOG TIMER RESET The watchdog timer that can recover to normal operation from abnormal function is built in S3F80JB Watchdog timer generat
143. STERS P345CON Port3 4 5 Control Register E1H Seti Bank1 1 0 1 0 Reset Value 0 Read Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 and 6 P3 5 Mode Selection Bits 5 and 4 P3 4 Mode Selection Bits C MOS input mode Open drain output mode Push pull output mode C MOS input with pull up mode 3 and 1 Not used for S3F80JB 0 Port 4 Control Register Selection Bit P4CON Register selection P4CONH P4CONL Register selection NOTE After CPU reset P3 4 and P3 5 will be Open drain output mode by the reset value of P345CON register at E1H Set1 Bank1 P345CON will be initialized as 50h to set P3 4 into the open drain output mode after reset operation Port4 control register P4CON will be selected by the reset value of P345CON 0 bit If you use the Port4 input and output mode set P345CON 0 to 1 ELECTRONICS 4 33 CONTROL REGISTERS S3F80JB PACON Port 4 Control Register FOH Seti BankO Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P4 7 Mode Selection Bit Open drain output mode Push pull output mode 6 P4 6 Mode Selection Bit 0 Open drain output mode 1 Push pull output mode 5 P4 5 Mode Selection Bit Open drain output mode Push pull output mode 4 P4 4 Mode Selection Bit Open drain output mode 1 Push pull output mode 3 P4 3 Mode Sel
144. STOP Enter the STOP mode BTCON 4Z02H Clear basic timer counter T MAIN RESET S3F80JB SOURCES TO RELEASE STOP MODE Stop mode is released when following sources go active System Reset by external reset pin nRESET System Reset by Internal Power On Reset IPOR Low Voltage Detector LVD External Interrupt INTO INT9 SED amp R circuit Using nRESET Pin to Release STOP Mode Stop mode is released when the system reset signal goes active by nRESET Pin all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained When the oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in reset address Using IPOR to Release STOP Mode Stop mode is released when the system reset signal goes active by internal power on reset IPOR IPOR is enabled when IPOR LVD Control Bit is set to 0 and chip status is in stop mode by executing STOP instruction All system and peripheral control registers are reset to their default hardware values and contents of all data registers are unknown states When the oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in reset address Using LVD to Release STOP Mode When IPOR LVD Control Bit smart option bit 7 O3FH is set to
145. T P2 5 INT9 CIN1 P2 6 INT9 CIN2 RESET P3 4 P3 5 P2 7 INT9 CIN3 P1 0 P3 2 TOCK P3 3 T1CAP T2CAP P4 7 P1 1 P1 2 P1 3 N C N C N C NOTE N C means No Connection J2 for 44 QFP o 3 3 o did 06 DEVELOPMENT TOOLS DATA P2 2 INT7 P2 1 INT6 P2 0 INT5 P4 0 P4 1 P4 2 P4 3 PO 7 INT4 PO 6 INT4 PO 5 INT4 PO 4 INT4 PO 3 INT3 PO 2 INT2 PO 1 INT1 PO 0 INTO P4 4 P4 5 P4 6 P1 7 P1 6 P1 5 P1 4 N C N C N C Figure 20 2 50 Pin Connector Pin Assignment for TB80JB Target Board J2 Target System Joj9euuo 06 JOJDSUUOD Uld 0S Figure 20 3 TB80JB Adapter Cable for 44 QFP Package ELECTRONICS 20 5 DEVELOPMENT TOOLS DATA S3F80JB SAMSUNG provides a complete line of development tools for SAMSUNG s microcontroller With long experience in developing MCU systems our third parties are leading companies in the tool s technology SAMSUNG In circuit emulator solution covers a wide range of capabilities and prices from a low cost ICE to a complete system with an OTP MTP programmer Series In Circuit Emulator OPENice i500 SMART Kit OTP MTP Programmer SPW 2 BlueChips Combi GW PRO2 Development Tools Suppliers Please contact our local sales offices on how to get MDS tools Or contact the 3rd party tool suppliers directly as shown below 8 bit In
146. TER AREA COH CFH After a reset register pointers RPO and RP1 automatically select two 8 byte register slices in set 1 locations COH CFH as the active 16 byte working register block RPO COH C7H RP1 C8H CFH This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations FFH Set 1 Page 0 FOH EOH Set 2 DOH COH COH BFH Page 0 Following hareware reset register pointers RPO and RP1 point to the common working register area locations COH CFH Prime Area RPo 1100 0000 1 1100 1000 00H Figure 2 11 Common Working Register Area ELECTRONICS 2 15 S3F80JB ADDRESS SPACES 55 PROGRAMMING Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations COH CFH using working register addressing mode only Example 1 LD 0C2H 40H Invalid addressing mode Use working register addressing instead SRP 0 LD R2 40H R2 C2H lt the value in location 40H Example 2 ADD 0C3H 45H Invalid addressing mode Use working register addressing instead SRP 0COH ADD R3 45H R3 C3H lt R3 45H 4 BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8
147. TRONICS 15 15 EMBEDDED FLASH MEMORY INTERFACE 53 80 Case3 Programming to the flash memory space located in other sectors WR INSECTOR2 LD RO 40H LD R1 40H SB1 LD FMUSR 0A5H User program mode enable LD FMCON 01010000B Selection programming mode and Start programming LD FMSECH 01H Set the base address of sector located in target address to write data LD FMSECL 00H The sector 2 s base address is 100H LD R9 0CCH Load data CCH to write LD R10 01H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair working register CALL WR_BYTE LD RO 40H WR_INSECTORS0 LD FMSECH 19H Set the base address of sector located in target address to write data LD FMSECL 00H The sector 50 s base address is 1900H LD R9 55H Load data 55H to write LD R10 19H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair working register CALL WR_BYTE WR_INSECTOR128 LD FMSECH 40H Set the base address of sector located in target address to write data LD FMSECL 00H The sector 128 s base address is 4000H LD R9 0A3H Load data to write LD R10 40H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair workin
148. U clock as determined by the current CLKCON register setting divided by 4096 as the BT clock A reset is generated whenever the basic timer overflow occurs During normal operation the application program must prevent the overflow and the accompanying reset operation from occurring To do this the BTCNT value must be cleared by writing a 1 to BTCON 1 at regular intervals If a system malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter BTCNT is always broken by a BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when Stop mode has been released by an external interrupt In Stop mode whenever a reset or an external interrupt occurs the oscillator starts The BTCNT value then starts increasing at the rate of fOSC 4096 for reset or at the rate of the preset clock source for an external interrupt When BTCNT 3 overflows a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation In summa
149. UPT PROCESSING Continued Two other system registers support fast interrupt processing The instruction pointer IP contains the starting address of the service routine and is later used to swap the program counter values and When afast interrupt occurs the contents of the FLAGS register are stored in an unmapped dedicated register called FLAGS FLAGS prime NOTE For the S3F80JB microcontroller the service routine for any one of the eight interrupt levels 0 can be selected for fast interrupt processing Procedure for Initiating Fast Interrupt To initiate fast interrupt processing follow these steps 1 Load the start address of the service routine into the instruction pointer IP 2 Load the interrupt level number IRQn into the fast interrupt selection field SYM 4 SYM 2 3 Write a 1 to the fast interrupt enable bit in the SYM register Fast Interrupt Service Routine When an interrupt occurs in the level selected for fast interrupt processing the following events occur The contents of the instruction pointer and the PC are swapped The FLAG register values are written to the FLAGS FLAGS prime register The fast interrupt status bit in the FLAGS register is set The interrupt is serviced Ov m co Assuming that the fast interrupt status bit is set when the fast interrupt service routine ends the instruction pointer and PC values are swapped back The content of FLAGS
150. WR_BYTE Write data AAH to destination address 4010H SB1 LD FMUSR 0A5H User program mode enable LD FMCON 01010000B _ Selection programming mode LD FMSECH 40H Set the base address of sector 4000H LD FMSECL 00H LD R9 0AAH Load data AA to write LD R10 40H Load flash memory upper address into upper register of pair working register LD R11 10H Load flash memory lower address into lower register of pair working register LDC QRR10 R9 Write data AAH at flash memory location 4010H LD FMUSR 00H User program mode disable SBO Case2 Programming in the same sector WR_INSECTOR RR10 gt Address copy R10 high address R11 low address LD R0 4 40H SB1 LD FMUSR 0A5H User program mode enable LD FMCON 01010000B _ Selection programming mode and Start programming LD FMSECH 40H Set the base address of sector located in target address to write data LD FMSECL 00H The sector 128 s base address is 4000H LD R9 33H Load data 33H to write LD R10 40H Load flash memory upper address into upper register of pair working register LD R11 40H Load flash memory lower address into lower register of pair working register WR_BYTE LDC RR10 R9 Write data 33H at flash memory location INC R11 Reset address in the same sector by INC instruction DJNZ RO WR BYTE Check whether the end address for programming reach 407FH or not LD FMUSR 00H User Program mode disable SBO ELEC
151. able 18 2 D C Electrical Characteristics Continued Ta 25 to 85 C Vpp 1 95 V to 3 6 V Parameter Symbol Conditions i Max Unit Supply Current Ipp1 Operating Mode 9 note Vpp 3 6 V mA 8 MHz crystal Ipp2 Idle Mode 2 5 Vpp 3 6 V 8 MHz crystal Stop Mode 1 6 LVD OFF Vpp 3 6 V uA Stop Mode 10 20 LVD ON Vpp 3 6 V NOTE Supply current does not include current drawn through internal pull up resistors or external output current loads Table 18 3 Characteristics of Low Voltage Detect Circuit Ta 25 C to 85 C Parameter Symbol Conditions Min Typ Max Unit Hysteresis Voltage of LVD 100 300 mV Slew Rate of LVD Low Level Detect Voltage LVD 1 95 2 15 2 35 V For Back Up Mode Low Level Detect Voltage LVD FLAG 2 1 2 3 2 5 V For Flag Indicator NOTE The voltage gap between LVD and LVD FLAG is 150mV Table 18 4 Data Retention Supply Voltage in Stop Mode TA 25 C to 85 C Data Retention Supply Vpppn E 1 5 3 6 V Voltage Data Retention Supply IpppR Vpppn 1 5 V 1 Current Stop Mode 18 4 ELECTRONICS S3F80JB TYPICAL VOL vs IOL VDD 3 3V IOL mA ELECTRICAL DATA 8 2 TYPICAL VOL VS VDD IOL 12mA 1 800V 2 400V 3 000V VDD V 3 600V Figure 18 1 Typical Low Side Driver Sink Characteristics P3 1 only TYPICAL VOL vs I
152. ablished priorities NOTE The system initialization routine that is executed following a reset must always contain an instruction to globally enable the interrupt structure During normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The El and DI instructions change the value of bit 0 in the SYM register Although you can manipulate SYM 0 directly to enable or disable interrupts we recommend that you use the El and DI instructions instead SYSTEM LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources four system level registers control interrupt processing The interrupt mask register IMR enables un masks or disables masks interrupt levels The interrupt priority register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register RW Function Description Interrupt Mask Register IMR R W Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels IRQ
153. ack Pointer Low Byte Seti Banko Bit Identifier 5 4 3 2 a 9 Reset Value X X X X X x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address Low Byte The SP value is undefined following a reset STOPCON Stop Control Register Seti Bit Identifier 7 6 5 4 3 2 1 0 Reset Value 0 0 0 0 0 0 0 0 Read Write W W W W W W Addressing Mode Register addressing mode only 7 0 Stop Control Register Enable Bits 1 0 1 0 0 1 0 1 Enable STOP Mode Other value Disable STOP Mode NOTES 1 Togetinto STOP mode stop control register must be enabled just before STOP instruction 2 When STOP mode is released stop control register STOPCON value is cleared automatically 3 It is prohibited to write another value into STOPCON ELECTRONICS 4 39 CONTROL REGISTERS S3F80JB SYM System Mode Register DEH Seti BankO Reset Value 0 x x x 0 0 Read Write R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Tri State External Interface Control Bit 1 0 Normal operation disable tri state operation 1 Set external interface lines to high impedance enable tri state operation 6 and 5 Not used for S3F80JB 2 4 2 4 Enable fast interrupt processing 0 Global Interrupt Enable Bit 5 Disable global interrupt processing Enable global interrupt processing NOTES
154. al This phenomenon is only port1 4 1 5 1 6 1 7 issues and in normal operating mode it never be occurred 2 ANALYSIS OF PHENOMENON 2 1 FOR SERIAL PROGRAMMING MODE The S3F80JB 9 is needed to nRESET pin O GND amp TEST pin 1 VDD BICONE When nRESET pin O GND amp TEST 1 VDD In the Figure 1 SDAT signal effects to outdis and data signal See 1 But because MUX level is unknown See 2 outdis and data is toggling This toggling phenomenon is only occurred to port1 4 1 5 1 6 1 7 on SSF80JB ELECTRONICS 1 S3F80JB Important Note 2 2 FOR NORMAL OPERATING MODE The S3F80JB 9 is needed to nRESET pin 1 VDD amp TEST pin GND When nRESET pin 1 VDD amp TEST pin O GND In the Figure 2 because TEST signal is low Logic level 0 outdis and data signal is same to MUX 0 signal So in normal operation port1 7 doesn t occurred to toggling phenomenon because of SDAT changing Timing Diagram of Figure1 Figure2 2 ELECTRONICS Important Note S3F80JB 3 DIFFERENCE S3F80JB AND S3F80J9 3 1 WHEN TEST PIN 1 VDD This is Fabrication Test mode For Design team amp PE Design team amp PE team tested S3F80JB by using ADVAN equipment When testing S3F80JB p
155. alculate the pulse width duration of the signal that is being input at the TOCAP pin See Figure 10 6 Interrupt Enable Disable TOCON 2 8 bit Counter cem 1 ending IRQ TOOVF Pending 1 gt IRQO TOINT Interrupt Enable Disable Timer 0 Data Register TOCON 1 TOCON 5 TODATA TOCON 4 P3 0 TOCAP _ Figure 10 6 Simplified Timer 0 Function Diagram Capture Mode 10 8 ELECTRONICS S3F80JB BASIC TIMER and TIMER 0 RESET or STOP Bits 3 2 JJ Basic Timer Control Register a Bus Write 1010xxxxB to disable Dat Clear t 1 4096 Y 8 Bit Up Counter MIX BTONT Read Only When BTONT 4 is set after releasing from RESET or STOP mode CPU clock starts OVF IRQO Timer 0 Overflow 8 Bit Up Counter p XIN gt TOCNT P3 1 TOCK or P3 2 TOCK E IRQO note 3 Timer 0 Match P3 0 TOCAP Match Signal A lt TOCON 3 TOOVF Timer 0 Data Register TODATA Basic Timer Control Register Data Bus Timer 0 Control Register NOTES During a power on reset operation the CPU is idle during the required oscillation stabilization interval until bit 4 of the basic timer counter overflows It is available only in using internal mode The external clock source is P3 1 TOCK in 32 pin package or P3 2 TOCK in 42 44 pin package Figure 10 7 Basic Timer and Timer 0 Block Diagram ELECTRONICS 10 9 BASIC TIMER and TIMER 0 S3F80JB PROG
156. alue C Setto 1 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 DF The statement SCF sets the carry flag to logic one ELECTRONICS S3F80JB INSTRUCTION SET SRA Shift Right Arithmetic SRA dst Operation dst 7 lt dst 7 C dst 0 dst n lt dst n 1 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is unchanged and is shifted into bit position 6 Flags C Setifthe bit shifted from the LSB position bit zero was 1 Z Setifthe result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 DO R D1 IR Examples Given Register 00H 9AH register 02H register OBCH and C 1 SRA 00H gt Register 00H OCD C 0 SRA 02H gt Register 02H register 03H C 0 In the first example if general register OOH contains the value 9AH 10011010B the statement SRA OOH shifts the bit values in register OOH right one bit position Bit zero 0 clears the C flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value 11001101B in destination register ELECTRONICS 6 79 INSTRUCTION SET S3F80JB SRP SR
157. are after the interrupt service routine is acknowledged and executed the other type must be cleared by the interrupt service routine Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and clears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software In the SSF80JB interrupt structure the timer 0 overflow interrupt IRQO the timer 1 overflow interrupt IRQ1 the timer 2 overflow interrupt IRQ3 and the counter A interrupt IRQ2 belong to this category of interrupts whose pending condition is cleared automatically by hardware Pending Bits Cleared by the Service Routine The second type of pending bit must be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt Subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register In the S3F80JB interrupt structure pending conditions for all interrupt sources except the timer 0 overflow interrupt the timer 1 overflow interrupt the timer 2 overflow inter
158. are electrical mechanical MTP and development tools data It has 14 chapters Chapter 7 Clock Circuits Chapter 15 Embedded Flash Memory Interface Chapter 8 RESET Chapter 16 Low Voltage Detector Chapter 9 Ports Chapter 17 Electrical Data 4MHz Chapter 10 Basic Timer and Timer 0 Chapter 18 Electrical Data 8MHz Chapter 11 Timer 1 Chapter 19 Mechanical Data Chapter 12 Counter A Chapter 20 Development Tools Data Chapter 13 Timer 2 Chapter 14 Comparator Two order forms are included at the back of this manual to facilitate customer order for SSF80JB microcontrollers the Flash Factor Writing Order Form You can photocopy these forms fill them out and then forward them to your local Samsung Sales Representative S3F80JB MICROCONTROLLER iii Table of Contents Part Programming Model S3F80JB MICROCONTROLLER Chapter 1 Product Overview S3C8 S3F8 Series Microcontrollers nnne enne 1 1 S3F80JB Microcontroller ess cese aa entre Poterie dene ERR Recto Ie reto dee de tero e Bo Lo ace ERE e Le ed ce ge 1 1 FOALS pL 1 2 Block Diagram 32 pin package eios 1 3 Block Diagram 44 pin 2 1 4 Pin AssIgnimibents EU Rp QURE Ug re OE RO DERI Dg Nee Hd ce Ege pu dali aan 1 5 Pil GirCuits edere tet epe Grn e EB e Dope RE eee ae 1 10 Chapter 2 Address Spaces OI P CP 2 1 MOIMONY
159. are enabled in accordance with function selection bit bit5 and bit2 3 In case of 42 44pin package the pin assign for alternative functions can be selectable relating to mode selection bit bitO 1 2 3 4 and 5 4 Following Table is the specific example about the alternative function and pin assignment according to the each bit control of PSCON in 42 44pin package Table 4 3 Each Function Description and Pin Assignment of P3CON in 42 44 Pin Package P3CON Each Function Description and Assignment to P3 0 P3 3 B4 B3 BO P3 0 P3 1 P3 2 P3 3 Normal I O Normal I O Normal Input Normal Input pope pe e fo how rea Pope px nomaro nora nut THCAPNomal nou Pape fe fo x Tock Nomal put 1 0 1 X Normal I O REM TOCK Normal Input 1 1 0 X x Normal I O REM TOCK Normal Input 1 0 TO CAP Normal Input TOCK Normal Input T1CAP Normal Input TO CAP Normal Input TOCK Normal Input T1CAP Normal Input e Lo o x TOPWM TOCK Normal Input T1CAP Normal Input acoso pese to TOPWM TOCK Normal Input T1CAP Normal Input 1 0 Tow Normal Input TOCK Normal Input T1CAP Normal Input Lac pem ae doses TOPWM Normal Input TOCK Normal Input T1CAP Normal Input 1 0 1 1 0 0 TO CAP REM TOCK Normal Input T1CAP Normal Input 1 1 0 1 1 1 TO CAP REM TOCK Normal Input T1CAP Normal Input 4 32 ELECTRONICS S3F80JB CONTROL REGI
160. atement RET pops the contents of stack pointer location OOFCH 10H into the high byte of the program counter The stack pointer then pops the value in location OOFEH 1AH into the PC s low byte and the instruction at location 101AH is executed The stack pointer now points to memory location OOFEH ELECTRONICS S3F80JB INSTRUCTION SET RL Rotate Left RL Operation dst C lt dst 7 dst 0 lt dst 7 dst 1 lt dst n n 0 6 The contents of the destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag Flags Format Examples C Set if the bit rotated from the most significant bit position bit 7 was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 90 R 4 91 IR Given Register 00H OAAH register 01H 02H and register 02H 17H RL 00H gt Register OOH 55H C 1 RL 01H gt Register 01H 02H register 02H 2bEH C 0 In the first example if general register OOH contains the value OAAH 10101010B the statement RL 00H rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry and overflow flags ELECTRONICS 6 71 I
161. b r0 NOTE In the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H 00000111B and register 01H 03H 00000011B BXOR R1 01H 1 E R1 06H register 01H BXOR 01 2 1 gt Register 01H 07H R1 07H In the first example destination working register R1 has the value 07H 00000111B and source register 01H has the value 03H 00000011B The statement BXOR R1 01H 1 exclusive ORs bit one of register 01H source with bit zero of R1 destination The result bit value is stored in bit zero of R1 changing its value from 07H to 06H The value of source register 01H is unaffected ELECTRONICS 6 25 INSTRUCTION SET S3F80JB CALL call Procedure CALL Operation Flags Format Examples 6 26 dst SP lt SP 1 SP lt PCL SP lt SP 1 SP lt PCH PC lt dst The current contents of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back into the program counter No flags are af
162. bit one the destination register for a 0 value Because the mask value does not match the test bit the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONICS 6 85 INSTRUCTION SET S3F80JB WEI wait For Interrupt WFI Operation Flags Format Example 6 86 The CPU is effectively halted until an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including fast interrupt No flags are affected Bytes Cycles Opcode Hex opc 1 4n 3F n 1 2 3 The following sample program structure shows the sequence of operations that follow a WFI statement Main program El Enable global interrupt WFI Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET m Service routine completed ELECTRONICS S3F80JB INSTRUCTION SET Logical Exclusive OR XOR dst src Operation dst lt dst XOR src The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different otherwise a O bit is stored Flags C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwis
163. ble interrupt 4 28 ELECTRONICS S3F80JB CONTROL REGISTERS P2PND Port 2 External Interrupt Pending Register E6H Seti BankO Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P2 7 External Interrupt INT9 Pending Flag Bit see Note No P2 7 external interrupt pending when read 1 P2 7 external interrupt is pending when read 6 P2 6 External Interrupt INT9 Pending Flag Bit EN No P2 6 external interrupt pending when read P2 6 external interrupt is pending when read 5 P2 5 External Interrupt INT9 Pending Flag Bit Lo No P2 5 external interrupt pending when read P2 5 external interrupt is pending when read 4 P2 4 External Interrupt INT9 Pending Flag Bit No P2 4 external interrupt pending when read 1 P2 4 external interrupt is pending when read 3 P2 3 External Interrupt INT8 Pending Flag Bit 0 No P233 external interrupt pending when read P2 3 external interrupt is pending when read 2 P2 2 External Interrupt INT7 Pending Flag Bit Lo No P2 2 external interrupt pending when read P2 2 external interrupt is pending when read 1 P2 1 External Interrupt INT6 Pending Flag Bit Lo No P2 1 external interrupt pending when read P2 1 external interrupt is pending when read 0 2 0 External Interrupt INT5 Pending Flag Bit 0 No P2 0 external interrupt pending when read P2 0 external interrupt is pending
164. ble pins 82 SOP Carrier Frequency Generator e 8 bit counter with auto reload function and one shot or repeat control Counter A S3F80JB Basic Timer and Timer Counters e programmable 8 bit basic timer BT for oscillation stabilization control or watchdog timer software reset function e 8 bit timer counter Timer 0 with three operating modes Interval mode Capture and PWM mode e 16 bit timer counter Timer1 with two operating modes Interval and Capture mode e 16 bit timer counter Timer2 with two operating modes Interval and Capture mode Back up Mode When Vpp is lower than V yp the chip enters Back up mode to block oscillation and reduce the current consumption In SSF80JB this function is disabled when operating state is STOP mode e Whenreset pin is lower than Input Low Voltage Vii the chip enters Back up mode to block oscillation and reduce the current consumption Analog Voltage Comparator e 4 bit resolution 16 step variable reference voltage 150mV Input Voltage Accuracy worst case e 4channel mode CINO 3 Internal reference voltage generator e 3 channel mode CINO 2 External reference voltage source CIN3 supply Low Voltage Detect Circuit e Low voltage detect to get into Back up mode and Reset 2 15V Typ 200mV at 8MHz 1 90V Typ 200mV at 4MHz e Low voltage detect to control LVD Flag bit 2 30V Typ 200mV at 8MHz 2 15V Typ
165. ble the watch dog timer function It is located in Set 1 and address and is read write addressable using register addressing mode A reset clears BTCON to 00H This enables the watch dog function and selects a basic timer clock frequency of fOSC 4096 To disable the watch dog function you must write the signature code 1010 to the basic timer register control bits BTCON 7 BTCON 4 For improved reliability using the watch dog timer function is recommended in remote controllers and hand held product applications Basic Timer Control Register BTCON D3H Set 1 Bank 0 R W s a s ef Watch dog Timer Enable Bits Divider Clear Bit for BT and TO 1010B Disable watch dog function 0 No effect Others Enable watch dog function 1 Clear both dividers Basic Timer Counter Clear Bits 0 No effect 1 Clear BTCNT Basic Timer Input Clock Selection Bits 00 fosc 4096 01 fosc 1024 10 fosc 128 11 Invalid selection Figure 10 1 Basic Timer Control Register BTCON 10 2 ELECTRONICS S3F80JB BASIC TIMER and TIMER 0 BASIC TIMER FUNCTION DESCRIPTION Watch dog Timer Function You can program the basic timer overflow signal BTOVF to generate a reset by setting 7 4 to any value other than 1010B The 1010B value disables the watch dog function A reset clears BTCON to 00H automatically enabling the watch dog timer function A reset also selects the CP
166. byte slice of working register space The address information stored in a register pointer serves as an addressing window that makes it possible for instructions to access working registers very efficiently using short 4 bit addresses When an instruction addresses a location in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address The high order bit of the 4 bit address selects one of the register pointers 0 selects RPO 1 selects RP1 The five high order bits in the register pointer select an 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 11 the result of this operation is that the five high order bits from the register pointer are concatenated with the three low order bits from the instruction address to form the complete address As long as the address stored in the register pointer remains unchanged the three bits from the address will always point to an address in the same 8 byte register slice Figure 2 12 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC R6 is 0 which selects RPO The five high order bits stored in RPO 01110B are concatenated with the three low order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110B 2 16 ELECTRONICS S3F80J
167. d 8 20 9 1 SSF80JB Port Configuration Overview 44 QFP 9 2 9 3 SSF80JB Port Configuration Overview 32 5 9 3 9 4 Port Data Register Summary eese nennen nenne 9 4 S3F80JB MICROCONTROLLER List of Tables Continued Table Title Page Number Number 15 1 Descriptions of Pins Used to Read Write the Flash in Tool Program Mode 15 2 15 2 ISP S6ectOr S126 2 eee See tvnc bes Pep 15 5 15 3 Reset Vector Add ess etl eee need 15 5 17 1 Absolute Maximum Ratings sese rennen mre enne 17 2 17 2 DG Electrical GharacteristiCs 2 45 mte ne rende dires 17 2 17 3 Characteristics of Low Voltage Detect Circuit 17 4 17 4 Data Retention Supply Voltage in Stop 17 4 17 5 Input Output Capacitance Doe dete potes 17 9 17 6 A C Electrical Characteristics 17 9 17 7 Comparator Electrical 17 11 17 8 Oscillation 17 11 17 9 Oscillation Stabilization 17 12 17 10 AC Electrical Characteristics for Internal Flash 17 13 18 1 Absolute Maximum Ratings sesssssssassuseussssssusssusssu
168. de OVF interrupt can occur NOTE The external clock source of timer 0 is P3 1 TOCK in 32 pin package or P3 2 TOCK in 44 pin package Figure 10 2 Timer 0 Control Register TOCON Timer 0 Data Register TODATA Seti Bank 0 R W Reset Value FFH Figure 10 3 Timer 0 DATA Register TODATA ELECTRONICS 10 5 BASIC TIMER and TIMER 0 S3F80JB TIMER 0 FUNCTION DESCRIPTION Timer 0 Interrupts IRQO Vectors FAH and FCH The timer 0 module can generate two interrupts the timer 0 overflow interrupt TOOVF and the timer 0 match capture interrupt TOINT TOOVF is interrupt with level IRQO and vector FAH TOINT also belongs to interrupt level IRQO but is assigned the separate vector address FCH A timer 0 overflow interrupt TOOVF pending condition is automatically cleared by hardware when it has been serviced The TOINT pending condition must however be cleared by the application s interrupt service routine by writing a 1 to the TOCON O interrupt pending bit Interval Timer Mode In interval timer mode a match signal is generated when the counter value is identical to the value written to the TO reference data register TODATA The match signal generates a timer 0 match interrupt TOINT vector FCH and clears the counter If for example you write the value 10H to TODATA OBH to TOCON the counter will increment until it reaches 10H At this point the TO interrupt request is generat
169. ded 64K byte memory has two operating features as below User Program Mode Tool Program Mode Flash ROM Configuration The S3F80JB flash memory consists of 512sectors Each sector consists of 128bytes So the total size of flash memory is 512x128 bytes 64KB User can erase the flash memory by a sector unit at a time and write the data into the flash memory by a byte unit at a time 64Kbyte Internal flash memory Sector size 128 Bytes 10years data retention Fast programming Time Sector Erase 10ms min Byte Program 32us min Byte programmable User programmable by LDC instruction Sector 128 Bytes erase available External serial programming support Endurance 10 000 Erase Program cycles min Expandable OBPTM On Board Program ELECTRONICS EMBEDDED FLASH MEMORY INTERFACE 53 80 User Program Mode This mode supports sector erase byte programming byte read and one protection mode Hard Lock Protection The S3F80JB has the internal pumping circuit to generate high voltage Therefore 12 5V into Vpp TEST pin is not needed To program a flash memory in this mode several control registers will be used There are four kind functions in user program mode programming reading sector erase and one protection mode Hard lock protection Tool Program Mode This mode is for erasing and programming full area of flash memory by external programming tools The 6 pins of SSF80JB are connected to a programming tool a
170. ded in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction ELECTRONICS 6 13 INSTRUCTION SET S3F80JB ADC Add with carry ADC Operation Flags Format Examples 6 14 dst src dst dst src The source operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed In multiple precision arithmetic this instruction permits the carry from the addition of low order operands to be carried into the addition of high order operands C Set if there is a carry from the most significant bit of the result cleared otherwise Z Setifthe result is 0 cleared otherwise S Setifthe result is negative cleared otherwise V Setif arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to O H Setifthere is a carry from the most significant bit of the low order four bits of the result cleared o
171. deren 11 4 11 4 Timer 1 Control Register T1CON cecssccceeseeeeeeeeeeeeeeeeecneeeeesaeeeeesesneeeeeesneeeees 11 5 11 5 Timer 1 Registers TI CNTH T1DATAH 1 11 6 S3F80JB MICROCONTROLLER xi List of Figures Continued Figure Title Page Number Number 12 1 Counter A Block Diagram ied a inate te eee 12 2 12 2 Counter A Control Register 12 3 12 3 Counter A ftegisters dipende 12 3 12 4 Counter A Output Flip Flop Waveforms in Repeat 12 5 13 1 Simplified Timer 2 Function Diagram Capture Mode 13 2 13 2 Simplified Timer 2 Function Diagram Interval Timer Mode 13 3 13 3 Timer 2 Block Diagram eoru cec eee e tee eae a 13 4 13 4 Timer 2 Control Register 2 02 0 0000 13 5 13 5 Timer 2 Registers T2CNTH T2CNTL T2DATAH 2 13 6 14 1 Comparator Block Diagram for The 8 14 2 14 2 Conversion Characteristics 14 3 14 3 Comparator Mode Register 14 4 14 4 Comparator Input Selection Register 14 4 14 5 Com
172. disable register POINT and pending control register POPND Pull up resistors can be assigned to individual PO pins using POPUR register settings This port is dedicated for key input in IR controller application 8 bit general purpose I O port Input without or with pull up open drain output or push pull output This port is dedicated for key output in IR controller application Port 1 Port 2 P3 0 P3 1 8 bit general purpose port Input or push pull output The P2 pins 2 0 2 7 can be used as external interrupt inputs and have noise filters The P2INT register is used to enable disable interrupts and P2PND bits can be polled by software for interrupt pending control Pull up resistors can be assigned to individual P2 pins using P2PUR register settings Also P2 4 P2 7 can be assigned individually as analog input pin for comparator 2 bit I O port P3 0 and P3 1 are configured input functions Input mode with or without pull up for TOCK TOCAP or T1CAP or output functions push pull or open drain output mode or for REM and TOPWM P3 1 is dedicated for IR drive pin and P3 0 can be used for indicator LED drive P3 7 is not configured for I O pin and it only used to control carrier signal on off ELECTRONICS 9 3 PORTS S3F80JB PORT DATA REGISTERS Table 9 4 gives you an overview of the register locations of all four SSF80JB I O port data registers Data registers for ports 0 1 2 and 4 have the general format sh
173. e BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit OR BXOR dst src Bit XOR TCM dst src Test complement under mask TM dst src Test under mask 6 4 ELECTRONICS S3F80JB INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Mnemonic Operands Instruction Rotate and Shift Instructions RL dst Rotate left RLC dst Rotate left through carry RR dst Rotate right RRC dst Rotate right through carry SRA dst Shift right arithmetic SWAP dst Swap nibbles CPU Control Instructions CCF Complement carry flag DI Disable interrupts EI Enable interrupts IDLE Enter Idle mode NOP No operation RCF Reset carry flag SBO Set bank 0 SB1 Set bank 1 SCF Set carry flag SRP SIC Set register pointers SRPO SIC Set register pointer 0 SRP1 SIC Set register pointer 1 STOP Enter Stop mode ELECTRONICS 6 5 INSTRUCTION SET S3F80JB FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits that describe the current status of CPU operations Four of these bits FLAGS 7 FLAGS 4 can be tested and used with conditional jump instructions two others FLAGS 3 and FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to indicate whether bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the fla
174. e V Always reset to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 2 4 B2 r r 6 B3 r Ir opc src dst 3 6 B4 R R B5 R IR opc dst src 3 6 B6 R IM Examples Given RO OC7H R1 02H R2 18H register 00H 2BH register 01H 02H and register 02H 23H XOR RO R1 gt RO 0C5H R1 02H XOR R0 R1 gt RO 0E4H R1 02H register 02H 23H XOR 00H 01H gt Register OOH 29H register 01H 02H XOR 00H 01H gt Register OOH 08H register 01H 02H register 02H 23H XOR 00H 54H gt Register 00H 7FH In the first example if working register RO contains the value 0C7H and if register R1 contains the value 02H the statement RO R1 logically exclusive ORs the R1 value with the RO value and stores the result 0C5H in the destination register RO ELECTRONICS 6 87 S3F80JB CLOCK CIRCUITS CLOCK CIRCUITS OVERVIEW The clock frequency for the S3F80JB can be generated by an external crystal or supplied by an external clock Source The clock frequency for the SSF80JB can range from 1MHz to 8 MHz The maximum CPU clock frequency as determined register is 8 MHz The Xi and pins connect the external oscillator or clock source to the on chip clock circuit SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal or ceramic resonator oscillation source or an external clock Oscillator stop and wake up
175. e Bit Disable interrupt Enable interrupt Counter A Start Bit Stop counter A Start counter A Counter A Mode Selection Bit 0 One shot mode Repeating mode Counter A Output Flip Flop Control Bit 0 Flip Flop Low level T FF Low Flip flop High level T FF High ELECTRONICS S3F80JB CONTROL REGISTERS CLKCON System Clock Control Register D4H Seti 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 5 Not used for S3F80JB Aand 3 CPU Clock System Clock Selection Bits 1 2 0 Subsystem Clock Selection Bits 2 1 o t Notused for S3F80JB Select main system clock MCLK NOTES 1 After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 2 These selection bits CLKCON O 1 2 are required only for systems that have a main clock and a subsystem clock The S3F80JB uses only the main oscillator clock circuit For this reason the setting 101B is invalid ELECTRONICS 4 7 CONTROL REGISTERS S3F80JB CMOD Comparator Mode Register E9H Set1 Bank1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only Comparator Enable Bit Comparator operation disable Comparator operation enable 6 Conversion Timer Control Bit 8 x 27
176. e echec 6 87 xxii S3F80JB MICROCONTROLLER S3F80JB PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8 S3F8 SERIES MICROCONTROLLERS Samsung s S3C8 S3F8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and various flash memory ROM sizes Important CPU features include Efficient register oriented architecture Selectable CPU clock sources dle and Stop power down mode release by interrupts Built in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt sources and vectors Fast interrupt processing within a minimum four CPU clocks can be assigned to specific interrupt levels S3F80JB MICROCONTROLLER The S3F80JB single chip CMOS microcontroller is fabricated using a highly advanced CMOS process and is based on Samsung s newest CPU architecture The SSF80JB is the microcontroller which has 64 Kbyte Flash Memory ROM Using a proven modular design approach Samsung engineers developed S3F80JB by integrating the following peripheral modules with the powerful SAM8 RC core Internal LVD circuit and 16 bit programmable pins for external interrupts One 8 bit basic timer for oscillation stabilization and watchdog function system reset One 8 bit Timer counter with three operating modes Two 16 bit timer counters with selectable
177. e initialization routine Stack address OFEH lt Stack address OFDH lt RPO Stack address OFCH lt 1 Stack address OFBH lt R3 R3 Stack address OFBH Stack address OFCH RPO Stack address OFDH PP Stack address OFEH S3F80JB ADDRESSING MODES ADDRESSING MODES OVERVIEW The program counter is used to fetch instructions that are stored in program memory for execution Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 S3F8 series instruction set supports seven explicit addressing modes Not all of these addressing modes are available for each instruction Register R Indirect Register IR Indexed X Direct Address DA Indirect Address IA Relative Address RA Immediate IM ELECTRONICS 3 1 ADDRESSING MODES 53 80 REGISTER ADDRESSING MODE R In Register addressing mode the operand is the content of a specified register or register pair see Figure 3 1 Working register addressing differs from Register addressing because it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2
178. e interrupt 5 0 5 External Interrupt INT4 Enable Bit Disable interrupt Enable interrupt 4 P0 4 External Interrupt INT4 Enable Bit Disable interrupt 1 Enable interrupt 3 0 3 External Interrupt INT3 Enable Bit 0 Disable interrupt Enable interrupt 2 P0 2 External Interrupt INT2 Enable Bit Disable interrupt Enable interrupt 1 PO 1 External Interrupt INT1 Enable Bit 0 Disable interrupt 1 Enable interrupt 0 P0 0 External Interrupt INTO Enable Bit Disable interrupt Enable interrupt ELECTRONICS 4 21 CONTROL REGISTERS S3F80JB POPND Port 0 External Interrupt Pending Register F2H Seti 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P0 7 External Interrupt INT4 Pending Flag Bit See Note Lo No P0 7 external interrupt pending when read 0 7 external interrupt is pending when read 6 0 6 External Interrupt INT4 Pending Flag Bit Lo No 6 external interrupt pending when read 0 6 external interrupt is pending when read 5 0 5 External Interrupt INT4 Pending Flag Bit 0 No PO 5 external interrupt pending when read 1 PO 5 external interrupt is pending when read 4 0 4 External Interrupt INT4 Pending Flag Bit No P0 4 external interrupt pending when read 0 4 external interrupt is pending when read 3 0 3 External Interrupt INT3 Pending Flag Bit Lo No
179. e value 40H The statement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 6 38 ELECTRONICS S3F80JB INSTRUCTION SET DJNZ Decrement and Jump if Non Zero DJNZ Operation Flags Format Example r dst rer i If r z0 PC dst The working register being used as a counter is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement NOTE Incase of using DJNZ instruction the working register being used as a counter should be set at the one of location to OCFH with SRP SRPO or SRP1 instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 jump taken 8 jump r OtoF Given R1 02H and LOOP is the label of a relative address SRP 0COH DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is used as the destination operand instead of a numeric relative address
180. ection Bit 0 Open drain output mode Push pull output mode 2 P4 2 Mode Selection Bit Open drain output mode Push pull output mode 4 P4 1 Mode Selection Bit 0 Open drain output mode 1 Push pull output mode 0 P4 0 Mode Selection Bit Open drain output mode Push pull output mode 4 34 ELECTRONICS S3F80JB CONTROL REGISTERS PACONH Port 4 Control Register High Byte E2H Set Bank1 Reset Value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 6 P4 7 Mode Selection Bits 0 0 jCMOSmutmde 0 1 Open drain outputmode Push pull output mode C MOS input with pull up mode 5 and 4 P4 6 Mode Selection Bits fo o cwosmumd For Pusnputouputmode ooo 3 and 2 P4 5 Mode Selection Bits Lo o cwosmumd Po open drain 1 and 0 P4 4 Mode Selection Bits Co o cwosmumd o i Push pull output mode 1 C MOS input with pull up mode NOTE After CPU reset P4 7 P4 4 will be C MOS input with pull up mode by the reset value of PACONH register ELECTRONICS 4 35 CONTROL REGISTERS 53 80 PACONL Port 4 Control Register Low Byte E3H Seti Bank1 Bit Identifier 7 e 5 3 2 j 9 Reset Value 1 1 1 1 1 1 1 1 Read Write R W R W R W R
181. ed And after the counter value is reset counting resumes With each match the level of the signal at the timer 0 output pin is inverted See Figure 10 4 IRQO TOINT 0 Interrupt Enable Disable TOCON 1 TOCNT R Clear Match 8 Bit Comparator ll P3 0 TOCAP TOCON 5 Buffer Register TOCON 4 Match Signal TOCON 3 0 Data Register TODATA Figure 10 4 Simplified Timer 0 Function Diagram Interval Timer Mode 10 6 ELECTRONICS S3F80JB BASIC TIMER and TIMER 0 Pulse Width Modulation Mode Pulse width modulation PWM mode lets you program the width duration of the pulse that is output at the TOPWM pin As in interval timer mode a match signal is generated when the counter value is identical to the value written to the timer 0 data register In PWM mode however the match signal does not clear the counter Instead it runs continuously overflowing at FFH and then continues incrementing from OOH Although you can use the match signal to generate a timer 0 overflow interrupt interrupts are not typically used in PWM type applications Instead the pulse at the TOPWM pin is held to low level as long as the reference data value is less than or equal to x the counter value and then the pulse is held to high level for as long as the data value is greater than gt the counter value One pulse width is equal to x 256 See Figure 10 5 IRQO TOINT
182. ed with 100H again and the program counter to jump back to the main program Now the next interrupt can occur and the IP is still correct at 100H OH FFH 100H Interrupt Service Routine JP to FFH FFFFH In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last two instructions The IRET cannot be immediately proceeded by a clearing of the interrupt status as with a reset of the IPR register ELECTRONICS S3F80JB INSTRUCTION SET JP Jump JP JP Operation Flags Format 1 Examples cc dst Conditional dst Unconditional If cc is true PC lt dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC No flags are affected Bytes Cycles Opcode Addr Mode 2 Hex dst dst 3 8 ccD DA cc 2 0to F opc dst 2 8 30 IRR NOTES 1 The 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 Inthe first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Given The carry flag C 1 regis
183. edge of LVD circuit is generated External nRESET pin is on rising edge rising edge at VDD is detected by LVD circuit When VDD gt Vivo Watch dog timer overflow signal is activated All I O port is floating status except P3 2 and P3 3 e Disable all pull up resister except P3 2 and P3 3 All control register and System register are initialized as list of Table 8 3 After passing an oscillation warm up time S3F80JB STOPCON lt ASH STOP LD STOPCON 0A5H STOP All port is keep the previous status Output port data is not changed External interrupt or reset SED amp R Circuit Others 8 20 There is no current consumption in chip There can be input leakage current in chip It depends on control program ELECTRONICS S3F80JB PORTS l O PORTS OVERVIEW The S3F80JB microcontroller has two kinds of package and different I O number relating to the package type 44 QFP package has five bit programmable I O ports and P4 Four ports PO P2 and P4 are 8 bit ports and P3 is a 6 bit port This gives a total of 38 I O pins 32 SOP package has four bit programmable I O ports PO P3 Three ports PO P2 8 bit ports and is a 2 bit port This gives a total of 26 I O pins Each port is bit programmable and can be flexibly configured to meet application design requirements The CPU accesses ports by di
184. elease and Continue Reset P2 0 2 3 X STOP X STOP NOTES 1 X means that a corresponding reset source don t generate reset signal means that a corresponding reset source generates reset signal Reset means that reset signal is generated and chip reset occurs Continue means that it executes the next instruction continuously without ISR execution External ISR means that chip executes the interrupt service routine of generated external interrupt Source means that the chip is in stop state STOP Release and External ISR means that chip executes the external interrupt service routine of generated external interrupt source after STOP released 7 STOP Release and Continue means that executes the next instruction continuously after STOP released 8 18 ELECTRONICS S3F80JB RECOMMENDATION FOR UNUSUED PINS RESET To reduce overall power consumption please configure unused pins according to the guideline description Table 8 6 Table 8 6 Guideline for Unused Pins to Reduced Power Consumption Set Input mode Enable Pull up Resister Connection for Pins Set Open Drain Output mode e Set P1 Data Register to Disable Pull up Resister Connection for Pins Set Push pull Output mode Set P2 Data Register to 00H Disable Pull up resister Connection for Pins Set Push pull Output mode Set P3 Data Register to 00H
185. en you execute the SB1 instruction ELECTRONICS 6 7 INSTRUCTION SET INSTRUCTION SET NOTATION 6 8 0 lt ONAN Table 6 2 Flag Notation Conventions Description Carry flag Zero flag Sign flag Overflow flag Decimal adjust flag Half carry flag Cleared to logic zero Set to logic one Set or cleared according to operation Value is unaffected Value is undefined Table 6 3 Instruction Set Symbols Description Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register D5H Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode S3F80JB ELECTRONICS S3F80JB INSTRUCTION SET Table 6 4 Instruction Notation Conventions cc Condition code See list of condition codes in Table 6 6 Working register only Rn n 0 15 Bit b of working register Rn b n 0 15 b 0 7 Bit 0 LSB of working register Rn n 2 0 15 Working register pair RRp 0 2 4 14 Register or working register reg or Rn reg 0 255 n 0 15 Bit b of register or working register reg b reg 0 255 b 0 7 Register pair or working register pair reg or RRp reg 0 254 even number only where 0 2 14 Indirect addressing mode addr addr 0 254 even number only Indirect working register only Rn n 0 15 Indirect register or indirect work
186. end that you use INCW as shown in the following example LOOP INOCW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONICS 6 45 INSTRUCTION SET S3F80JB IRET Interrupt Return IRET Operation Flags Format Example NOTE 6 46 IRET Normal IRET Fast FLAGS lt SP PC o IP SP lt SP 1 FLAGS lt FLAGS PC SP FIS 0 SP lt SP 2 SYM 0 1 This instruction is used at the end of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS bit one of the FLAGS register OD5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine All flags are restored to their original settings that is the settings before the interrupt occurred IRET Bytes Cycles Opcode Hex Normal 1 10 internal stack BF 12 internal stack IRET Bytes Cycles Opcode Hex Fast opc 1 6 BF In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine normally is a jump to IRET at address FFH This causes the instruction pointer to be load
187. ent Under Mask TCM Operation Flags Format Examples 6 84 dst src NOT dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operand which is then ANDed with the source mask The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 63 r Ir opc src dst 3 6 64 R R 65 R IR opc dst src 3 6 66 R IM Given RO OC7H R1 02H R2 12H register 00H 2BH register 01H 02H and register 02H 23H TCM RO R1 TCM RO R1 TCM 00H 01H TCM 00H 01H RO OC7H R1 02H Z 1 RO 0C7H R1 02H register 02H 23H Z 0 Register 00H 2BH register 01H 02H Z 1 Register 00H 2BH register 01H 02H register 02H 23H Z 1 TCM 00H 34 gt Register 00H 2BH Z 0 25 2 3 In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement TCM R0O R1 tests bit one in the destination register for a 1 value Because the mask value corresponds
188. er in the range 128 to 127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to the base address see Figure 3 9 The only instruction that supports indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support indexed addressing mode for internal program memory and for external data memory if implemented Register File MSB Points to RPO or RP1 RPO or RP1 Selected RP Value used in points to Instruction OPERAND Start or working register block Program Memory Base Address dst src Two Operand_ Instruction Points to one of the Example OPCODE Woking Registers 1 of 8 Sample Instruction LD BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Register File ELECTRONICS 3 7 ADDRESSING MODES INDEXED ADDRESSING MODE Continued 53 80 Program Memory OFFSET 4 bit Working dst src x Register Address X OPCODE Sample Instructions LDC R4 04H RR2 LDE R4 4 04H RR2 NOTE for the S3F80JB
189. eristics 25 C to 85 Vpp 1 95 V to 3 6 V Lowe mn Tm um Operating Voltage Fosc 8 MHz Input High Voltage All input pins except Vi and Vis nRESET Input Low Voltage All input pins except Vij Vito nRESET Output High Vpp 2 35 V 6MA 0 7 Voltage Port 3 1 only P3 0 and P2 0 2 3 PortO Porti P2 4 2 7 P3 4 3 5 and Port4 18 2 ELECTRONICS S3F80JB ELECTRICAL DATA 8MHz Table 18 2 D C Electrical Characteristics Continued TA 25 C to 85 Vpp 1 95 V to 3 6 V Symbol Conditions Min Typ Max Unit 0 4 0 5 Output Low Voltage Vou Vpp 2 35 V Io 12mA Port 3 1 only Voie Vpp 2 35 V Io 5mA P3 0 and P2 0 2 3 Vois Vpp 2 35 V Io 2mA PortO Port1 P2 4 2 7 P3 4 3 5 and Port4 Input High Lin Vin Vpp Leakage Current All input pins except juo and Xour liM Vin Vpp Xin Input Low Leakage Current Nit Vin 0V All input pins except and Xour Vin 0 V Xin Output High Vout Vpp Leakage Current All output pins Output Low Vout 0 Leakage Current All output pins Pull Up Resistors R4 Vin 0 V Vpp 2 35 V 25 Ports 0 4 Feedback Resistor 2 Vin 0 Vpp 2 35 V 200 500 1000 T4 25 nRESET TA 25 C ELECTRONICS 18 3 ELECTRICAL DATA 8MHz 53 80 T
190. es a system reset signal if Basic Timer Counter BTCNT isn t cleared within a specific time by program For more understanding of the watchdog timer function please see the chapter 11 Basic Timer and LVD RESET The Low Voltage Detect Circuit LVD is built on the SSF80JB product to generate a system reset when IPOR LVD Control Bit of smart option is set to 1 regardless of operation mode So if IPOR LVD Control Bit of smart option is set to 1 and the operating status is stop mode LVD can make a system reset When the voltage at is falling down and passing V yp the chip go into back up mode at the moment yp And the voltage at Vpp is rising up the reset pulse is occurred at the moment Vpp gt IPOR LVD Control Bit smart option bit 7 O3FH note 1 Reset STOPCON note 2 STOP Instruction Figure 8 3 RESET Block Diagram by LVD for The S3F80JB in Stop Mode 8 4 ELECTRONICS S3F80JB RESET NOTES 1 IPOR LVD Control Bit is one of smart option bits assigned address User can enable disable LVD in the stop mode by manipulating this bit When the value is 1 LVD always operate in the normal and stop mode When the value is 0 LVD is disabled in the stop mode But LVD is enabled in the normal operating mode 2 CPU enter stop mode by setting STOPCON Stop Control Register into 0A5H before execution STOP instruction 3 This
191. esistor 2 P0 2 Pull up Resistor Enable Bit 0 Disable pull up resistor Enable pull up resistor P0 1 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 0 P0 0 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor ELECTRONICS 4 23 CONTROL REGISTERS S3F80JB P1CONH Port 1 Control Register High Byte EAH Seti Reset Value 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 and 6 P1 7 Mode Selection Bits 0 0 CMOS inputmode 0 1 Open drain outputmode 0 0 ilo Push pull output mode C MOS input with pull up mode 5 and 4 P1 6 Mode Selection Bits o o cwosmumd 2277 Fo rjowmemnowptmok 3 and 2 P1 5 Mode Selection Bits Lo o cwosmumd o i Pi o Pushpullouputmode SSCS 1 and 0 P1 4 Mode Selection Bits 0 0jCMOSmutmde 0 1 Open drain output mode 0 ERES Push pull output mode 1 C MOS input with pull up mode 4 24 ELECTRONICS S3F80JB CONTROL REGISTERS P1CONL Por 1 Control Register Low Byte Seti Bit Identifier Reset Value Read Write Addressing Mode 7 and 6 5 and 4 3 and 2 1 and 0 ELECTRONICS 7 6 s 4 3 2 4 j 9 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W
192. executed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src dit 2 Cc cr m NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 and register 02H R1 R2 SKIP gt R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The statement CPIJE R1 R2 SKIP compares the R2 value 02H 00000010B to 02H 00000010B Because the result of the comparison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS 6 31 INSTRUCTION SET S3F80JB CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Flags Format Example 6 32 dst src RA If dst src 0 lt PC RA Ir Ir 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the CPIJNE instruction is executed In either case the source pointer is incremented by one before the next instruction
193. f external interrupt is occurred by among the enabled external interrupt sources from INTO to INTS reset signal is generated ELECTRONICS 8 7 RESET S3F80JB STOP ERROR DETECTION amp RECOVERY When IPOR LVD Control Bit smart option bit 7 is set to O and chip is in stop or abnormal state the falling edge input of PO and P2 4 P2 7 generates the reset signal Refer to following table and figure for more information Table 8 1 Reset Condition in STOP Mode When IPOR LVD Control Bit is 1 always LVD On Condition Reset System Reset Slope of Vpp Vpp The voltage level of reset pin Source Vreset Rising up from VppZViyp Vreset Vy LVD circuit System reset occurs No system reset Vpp lt Vi vp Vpp2 Vreset lt Vpp lt Transition from No system reset Vreset lt Vi to Vi lt Vreset Standstill 2 Transition from Reset pin System reset occurs Vpp 2 Vi Vreset Vi to Viu lt Vreset Table 8 2 Reset Condition in STOP Mode When IPOR LVD Control Bit is 0 Condition Reset System Reset Slope of Vpp The voltage level of reset pin Source Vreset Rising up from Vpp 2 Vi yp Vreset gt Vi No system reset V LVD E Vpp lt Vi yp Transition from No system reset Vreset lt Vi to Vi lt Vreset Rising up from Vpp 2 Vi yp Vreset gt Internal POR System reset occurs Vpp lt 0 4Vpp Vpp gt
194. fected Bytes Cycles Opcode Addr Mode Hex dst opc dst 3 14 F6 DA dst 2 12 F4 IRR dst 2 14 D4 Given RO 35H R1 24H 1A47H and SP 0002H CALL 3521H gt SP 0000H Memory locations 0000H 0001H where 4AH is the address that follows the instruction CALL RRO gt SP 0000H 0000H 0001H 49H CALL 40H gt SP 0000H 0000H 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location OOOOH The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and stack pointer are the same as in the first example the statement CALL RRO produces the same result except that the 49H is stored in stack location 0001H because the two byte instruction format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program counter and stack pointer are the same as in the first example if program address 0040H contains 35H and program address 0041H contains 21H the statement CALL 40H produces the same result as in the second example ELECTRONICS S3F80JB INSTRU
195. ference data registers T1DATAH and T1DATAL When a match condition is detected by the 16 bit comparator the match interrupt is generated the counter value is cleared and up counting resumes from 00H In match mode program software can poll the Timer 1 match capture interrupt pending bit T1 CON O to detect when a Timer 1 match interrupt pending condition exists T1CON 0 1 When the interrupt request is acknowledged by the CPU and the service routine starts the interrupt service routine for vector F6H must clear the interrupt pending condition by writing a 0 to 0 IRQ1 T1INT Pending T1CON 0 Interrupt Enable Disable T1CON 1 CLK 16 Bit Up Counter 16 Bit Comparator CTL P3 0 or P3 3 Timer 1 High Low T1CON 5 Buffer Register T1CON 4 Match Signal T1CON 3 Timer 1 Data High Low Buffer Register Figure 11 2 Simplified Timer 1 Function Diagram Interval Timer Mode ELECTRONICS 11 3 TIMER 1 T1CON 7 6 CAOF T F F fosc 4 fosc 8 fosc 16 OVF T1CON 3 R T1CON 1 T1CON 0 IRQ1 16 Bit Up Counter 4 Clear Read Only Match note 16 Bit Compatator Timer 1 High Low Buffer Register T1CON 3 T1CON 5 4 53 80 Match Signal T1OVF High Low Register Timer 1 Data NOTE Match signal is occurrd only in interval mode
196. first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register the least significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing because it uses a register pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space MSB LSB n Even address Rn Rn 1 Figure 2 9 16 Bit Register Pair ELECTRONICS 2 13 S3F80JB ADDRESS SPACES Special Purpose Registers General Purpose Registers gt A gt Bank 1 Bank 0 Control Registers Registers System CFH Register Pointers Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RPO points to locations COH C7H and RP1 to locations C8H CFH that is to the common working register area NOTE In the SSF80JB microcontroller only 0 is implemented Page0 containsall of the addressable registers in the internal register file Page 0 Page 0 Register Addressing Only Indirect Addressing Register Modes Indexed A Addressing Can be Pointed by Register Pointer Modes Figure 2 10 Register File Addressing 2 14 ELECTRONICS S3F80JB ADDRESS SPACES COMMON WORKING REGIS
197. for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to read alphabetically organized register descriptions as a quick reference source when writing programs Chapter 5 Interrupt Structure describes the SSF80JB interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part Il Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3F8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program A basic familiarity with the information in Part will help you to understand the hardware module descriptions in Part Il If you are not yet familiar with the S38F8 series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters 4 5 and 6 Later you can reference the information in Part as necessary Part Il hardware Descriptions has detailed information about specific hardware components of the S3F80JB microcontroller Also included in Part Il
198. format You can use this section as a quick reference source when writing application programs Figure 4 1 illustrates the important features of the standard register description format Control register descriptions are arranged in alphabetical order A Z according to the register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual Data and counter registers are not described in detail in this reference section More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part Il of this manual ELECTRONICS 4 1 CONTROL REGISTERS S3F80JB Table 4 1 Mapped Registers Set1 Register Name mnemonic Decima Hex nw RW Register Poimero Re a om w Register Pointer 1 RP1 215 D7H R W Location D8H is not mapped Stack Pointer Low Byte Instruction Pointer Low Byte 219 DBH R W 220 DCH R NOTE DDH R W Interrupt Request Register IPL Interrupt Mask Register IMR PPP Po P4 R W R W R W R W R W R W R W R W R W R W R W R W m Port 4 Data Register Port 2 Interrupt Enable Register P2INT Port 2 Interrupt Pending Register P2PND Port 0 Pull up Resistor Enable Register 2 RW Low Byte P1CONL 235 R W Port 2 Control Register High Byte P2CONH 236 R W Port 2 Control Register Low Byte P2CON
199. functions Programmable frequency divider for the CPU clock fosc divided by 1 2 8 or 16 Clock circuit control register CLKCON AN External Clock Open Pin 1 C2 XOUT XOUT Figure 7 1 Main Oscillator Circuit Figure 7 2 External Clock Circuit External Crystal or Ceramic Resonator ELECTRONICS 7 1 CLOCK CIRCUITS 53 80 CLOCK STATUS DURING POWER DOWN MODES The two power down modes Stop mode and Idle mode affect the system clock as follows In Stop mode the main oscillator is halted When stop mode is released the oscillator starts by a reset operation or by an external interrupt To enter the stop mode STOPCON STOP Control Register has to be loaded with value before STOP instruction execution After recovering from the stop mode by a reset or an external interrupt STOPCON register is automatically cleared Idle mode the internal clock signal is gated away from the CPU but continues to be supplied to the interrupt structure timer 0 timer 1 counter A and so on Idle mode is released by a reset or by an interrupt external or internally generated STOP STOPCON Instruction CLKCON 3 4 Oscillator Stop CPU CLOCK Oscillator Wake up Noise Filter INT Pin NOTES 1 An external interrupt with RC delay noise filter for the SSF80JB INTO 9 is fixed to release stop mode and wake up the main oscillator 2 Because the S3F80JB
200. g register WR_BYTE1 LDC RR10 R9 Write data A3H at flash memory location INC R11 DJNZ R1 WR_BYTE1 LD FMUSR 00H User Program mode disable SBO WR_BYTE LDC RR10 R9 Write data written by R9 at flash memory location INC R11 DJNZ RO WR_BYTE RET 15 16 ELECTRONICS S3F80JB EMBEDDED FLASH MEMORY INTERFACE READING The read operation starts by LDC instruction The program procedure in user program mode 1 Load a flash memory upper address into upper register of pair working register 2 Load a flash memory lower address into lower register of pair working register 3 Load receive data from flash memory location area on LDC instruction by indirectly addressing mode 5 PROGRAMMING Reading LD R2 03H Load flash memory s upper address to upper register of pair working register LD R3 00H Load flash memory s lower address to lower register of pair working register LOOP LDC RO RR2 Read data from flash memory location Between 300H and 3FFH INC R3 CP R3 0FFH JP NZ LOOP ELECTRONICS 15 17 EMBEDDED FLASH MEMORY INTERFACE 53 80 HARD LOCK PROTECTION User can set Hard Lock Protection by writing 0110B in FMCON7 4 This function prevents the changes of data in a flash memory area If this function is enabled the user cannot write or erase the data in a flash memory area This protection can be released by the chip erase execution in the tool program mode In terms of user program m
201. gic circuit Vss Vss 6 1 Vpp should be tied to 3 3 V during programming NOTE means 32SOP package 5 2 ELECTRONICS S3F80JB EMBEDDED FLASH MEMORY INTERFACE ISP ON BOARD PROGRAMMING SECTOR ISP sectors located in program memory area can store On Board Program Software Boot program code for upgrading application code by interfacing with I O port pin The ISP sectors can t be erased or programmed by LDC instruction for the safety of On Board Program Software The ISP sectors are available only when the ISP enable disable bit is set 0 that is enable ISP at the Smart Option If you don t like to use ISP sector this area can be used as a normal program memory can be erased or programmed by LDC instruction by setting ISP disable bit 1 at the Smart Option Even if ISP sector is selected ISP sector can be erased or programmed in the tool program mode by serial programming tools The size of ISP sector can be varied by settings of smart option Refer to Figure 2 2 and Table 15 2 You can choose appropriate ISP sector size according to the size of On Board Program Software Decimal HEX 65 536 FFFFH 384 256 128 byte Internal RAM FE80H Internal Program Memory Flash E 01FFH 02FFH 04FFH 08FFH ISP Sector 25b bo ibe ee ceu OFFH Interrupt Vector Area Smart Option ROM Cell 03CH 0 00H Figu
202. gister a reset is the only way you can release Idle mode 2 Activate any enabled interrupt internal or external When you use an interrupt to release Idle mode the 2 bit CLKCON 4 CLKCON 3 value remains unchanged and the currently selected clock value is used The interrupt is then serviced When the return from interrupt condition IRET occurs the instruction immediately following the one which initiated Idle mode is executed NOTE Only external interrupts built in to the pin circuit can be used to release stop mode To release Idle mode you can use either an external interrupt or an internally generated interrupt ELECTRONICS 8 9 RESET S3F80JB BACK UP MODE For reducing current consumption S3F80JB goes into Back up mode If external reset pin is low state or a falling level of Vpp is detected by LVD circuit on the point of Vj yp chip goes into the back up mode Because CPU and peripheral operation were stopped due to oscillation stop the supply current is reduced In back up mode chip cannot be released from stop state by any interrupt The only way to release back up mode is the system reset operation by interactive work of reset pin and LVD circuit The system reset of watchdog timer is not occurred in back up mode Rising Edge LVD Detector Falling Edge Detector V lt Back Up Mode nRESET H gt H buds reset Figure 8 7 Block Diagram for Back up Mode Voltage V Slope of nRESET amp Vpp Pin
203. gister 04H 2AH PUSHUI 00H 01H gt Register OOH 04H register 01H register 04H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONICS S3F80JB INSTRUCTION SET RCF Reset Carry Flag RCF Operation Flags Format Example RCF C 0 The carry flag is cleared to logic zero regardless of its previous value C Cleared to 0 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 CF Given C 1 or 0 The instruction RCF clears the carry flag C to logic zero ELECTRONICS 6 69 INSTRUCTION SET S3F80JB RET Return RET Operation Flags Format Example 6 70 PC SP SP lt SP 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement that is executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex opc 1 8 internal stack AF 10 internal stack Given SP OOFCH SP 101AH and PC 1234 RET gt PC 101AH SP OOFEH The st
204. gs such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneously two write will occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H Set 1 R W cary tag o Zero flag 2 status flag FIS Sign flag S Half carry flag H Overflow V Decimal adjust flag D Figure 6 1 System Flags Register FLAGS 6 6 ELECTRONICS S3F80JB INSTRUCTION SET FLAG DESCRIPTIONS C FIS BA Carry Flag FLAGS 7 The C flag is set to 1 if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Zero Flag FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero For operations that test register bits and for shift and rotate operations the Z flag is set to 1 if the result is logic zero Sign Flag FLAGS 5 Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero
205. he P1CONH P1CONL PACONH and PACONL You can assign a pull up resistor to the port 3 pins P3 0 P3 1 P3 4 and P3 5 in the input mode using basic port configuration setting in the and P345CON registers P3 2 P3 3 are configured only input pins with pull up resistor Pull up Register Enable Registers PnPUR where n 0 2 Set 1 E7H Banko R W Pn 4 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor NOTES 1 Pull up resistors can be assigned to the port 3 pins P3 0 and P3 1 by making the appropriate setting the port 3 control register 2 Pull up resistors can be assigned to the port 3 pins P3 4 and P3 5 by making the appropriate setting the port 3 4 5 and port3 6 7 control register P345CON Pull up resistors can be assigned to the P1 and P4 pins by making the appropriate setting the port 1 control register PI CONL P1CONH and the port 4 control register PACONL P4CONH respectively Figure 9 2 Pull up Resistor Enable Registers Port 0 and Port 2 only ELECTRONICS 9 5 S3F80JB BASIC TIMER and TIMER 0 BASIC TIMER and TIMER 0 OVERVIEW The S3F80JB has two default timers the 8 bit basic timer and the 8 bit general purpose timer counter The 8 bit timer counter is called timer 0 BASIC TIMER BT You can use the basic timer BT in two different ways As a watch dog timer to provide an automatic reset mechanism in the event of a system
206. he destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected TOSONO Bytes Cycles Opcode Addr Mode Hex dst sre opc src 3 6 07 ro Rb opc sro b 11 dst 3 6 07 Rb ro NOTE the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Given R1 07H and register 01H 03H BOR 1 01H 1 gt R1 07H register 01H BOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example destination working register R1 contains the value 07H 00000111B and source register 01H the value 03H 00000011B The statement BOR R1 01H 1 logically ORs bit one of register 01H source with bit zero of R1 destination This leaves the same value 07H in working register R1 In the second example destination register 01H contains the value 03H 00000011B and the source working register R1 the value 07H 00000111B The statement BOR 01H 2 R1 logically ORSs bit two of register 01H destination with bit zero of R1 source This leaves the value 07H in register 01H ELECTRONICS S3F80JB INSTRUCTION SET BTJ
207. ing register Rn or reg reg 0 255 n 0 15 Indirect working register pair only RRp p 0 2 14 Indirect register pair or indirect working RRp or reg reg 0 254 even only where register pair 0 2 14 Indexed addressing mode reg Rn reg 0 255 n 0 15 Indexed short offset addressing mode addr RRp addr range 128 to 127 where p 0 2 14 Indexed long offset addressing mode addr RRp addr range 0 65535 where 0 2 14 Direct addressing mode addr addr range 0 65535 Relative addressing mode addr addr number in the range 127 to 128 that is an offset relative to the address of the next instruction Immediate addressing mode data data 0 255 Immediate long addressing mode data data range 0 65535 ELECTRONICS 6 9 INSTRUCTION SET Table 6 5 Opcode Quick Reference S3F80JB OPCODE MAP LOWER NIBBLE HEX cp ow x om cow f cm pce DEC ADD ADD ADD ADD ADD IR1 r1 r2 r1 lr2 R2 R1 IR2 R1 R1 IM RLC ADC ADC ADC ADC ADC IR1 r1 r2 r1 lr2 R2 R1 IR2 R1 R1 IM INC SUB SUB SUB SUB SUB IR1 r1 r2 r1 lr2 R2 R1 IR2 R1 R1 IM SRP 0 1 SBC SBC SBC SBC SBC IM r1 r2 r1 lr2 R2 R1 IR2 R1 R1 IM DA OR OR OR OR O IR1 r1 r2 r1 lr2 R2 R1 IR2 R1 R1 IM POP AND AND AND AND AND IR1 r1 r2 r1 lr2 R2 R1 IR2 R1 R1 IM COM TCM TCM TCM TCM TCM IR1 r1 r2 12 R2 R1 IR2 R1 R1 IM PUSH TM TM TM TM TM IR2 r1 r2 r1 lr2 R2 R1 IR2 R1 R1 IM DECW PUSHUD PUSHUI MULT
208. ion Bits fo fo C MOS input mode interrupt on falling edges Fo C MOS input mode interrupt on rising and falling edges Push pull output mode C MOS input mode interrupt on rising edges 5 and 4 P0 2 INT2 Mode Selection Bits 79 input moder interaptonfaling edges Fo oMOSimtmode nemuptonrengandaingedges Fr o memmtowumze CS 3 and 2 0 11 1 Mode Selection Bits 79 owOSmetmosemempronangedes Fo oMOSimutmode nemuptonrengandtaingedges Push puloupwtmode CS 1 and 0 0 01 0 Mode Selection Bits fo fo C MOS input mode interrupt on falling edges ofa C MOS input mode interrupt on rising and falling edges ERES Push pull output mode 1 C MOS input mode interrupt on rising edges NOTES 1 The INT3 INTO external interrupts at PO 3 P0 0 are interrupt level IRQ6 Each interrupt has a separate vector address 2 Youcan assign pull up resistors to individual port O pins by making the appropriate settings to the POPUR register POPUR 3 POPUR O 4 20 ELECTRONICS S3F80JB CONTROL REGISTERS POINT Port 0 External Interrupt Enable Register F1H Seti BankO Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P0 7 External Interrupt INT4 Enable Bit Disable interrupt Enable interrupt 6 0 6 External Interrupt INT4 Enable Bit 0 Disable interrupt 1 Enabl
209. ion Register Page Seleciton Bits Source Register Page Selection Bits 0000 Destination page 0 0000 Source page 0 NOTE A hardware reset operation writes the 4 bit destination and source values shown above to the register page pointer These values should not be modified to address other pages Figure 2 4 Register Page Pointer PP ELECTRONICS 2 7 S3F80JB ADDRESS SPACES REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file locations The upper 32 byte area of this 64 byte space EOH FFH is divided into two 32 byte register banks bank 0 and bank 1 The set register bank instructions SBO or SB1 are used to address one bank or the other In the S3F80JB microcontroller bank 1 is implemented The set register bank instructions SBO or SB1 are used to address one bank or the other A hardware reset operation always selects bank 0 addressing The upper two 32 byte area of set 1 bank 0 EOH FFH contains 31mapped system and peripheral control registers Also the upper 32 byte area of set1 bank1 EOH FFH contains 16 mapped peripheral control register The lower 32 byte area contains 15 system registers DOH DFH and a 16 byte common working register area COH CFH You can use the common working register area as a scratch area for data operations being performed in other areas of the register file Registers in set 1 locations are directly accessible at all times using the Regi
210. ion register leaving 04H in general register 00H ELECTRONICS 6 51 INSTRUCTION SET LDC LDE Load Memory LDC LDE Operation Flags Format 6 52 10 dst src dst lt src S3F80JB This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes or rr values an even number for program memory odd an odd number for data memory No flags are affected dst src src dst opc dst src XS opc src dst XS opc dst src XL XL opc src dst XL XLy opc dst 0000 DA DAY opc 0000 DA DA opc dst 0001 DAL DA opc src 0001 DA DA NOTES Cycles 10 10 12 12 14 14 14 14 14 14 Opcode Hex C3 D3 E7 F7 7 B7 A7 B7 7 B7 Addr Mode dst src r Irr Irr r r XS rr XS rr r r XL rr XL rr r r DA DA r r DA DA r 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 For formats and 4 the destination address XS rr and the source address XS rr are each one byte 3 For formats 5 and 6 the destination address rr and the source address rr are each two bytes 4 The DA andr source values for formats 7 and 8 are used to address program memory the
211. ister SYM 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch the address of the service routine Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC and status flags and sets SYM 0 to 1 allowing the CPU to process the next interrupt request ELECTRONICS S3F80JB INTERRUPT STRUCTURE GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM except smart option ROM Cell 003 003DH 003EH 003FH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence Push the program counter s low byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the vector location Fetch the service routine s low byte address from the vector location one Branch to the service routine specified by the concatenated 16 bit vector address NOTE A 16 bit vector address always begins at an even numbered ROM address within the range OOH FFH NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced To do this
212. ister 01H 01H register 01H RO OFFH R1 OAH Register OAH RO 01H R1 OAH 20H 01H 10H 02 register 02H 02H ELECTRONICS S3F80JB INSTRUCTION SET LDB Load Bit LDB LDB Operation Flags Format Examples dst src b dst b src dst 0 lt src b or dst b lt src 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits of the destination are affected The source is unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc src 3 6 47 ro Rb opc 3 6 47 Rb r0 NOTE In the second byte of the instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given RO 06H and general register OOH 05H LDB R000H2 gt RO 07H register 05H LDB 00H 0 R0 gt RO 06H register OOH 04H In the first example destination working register RO contains the value 06H and the source general register OOH the value 05H The statement LD R0 00H 2 loads the bit two value of the OOH register into bit zero of the RO register leaving the value 07H in register RO In the second example is the destination register The statement LD 00H 0 R0 loads bit zero of register RO to the specified bit bit zero of the destinat
213. it Disable WAIT input function for external device Enable WAIT input function for external device 6 Slow Memory Timing Enable Bit 0 Disable slow memory timing 1 Enable slow memory timing and 4 Program money Automatic Wait Control Bits 3 and 2 Data Memory Automatic Wait Control Bits 1 wat wo ees 4 Stack Area Selection Bit 0 Select internal register file area Select external data memory area 0 Not used for S3F80JB NOTE The EMT register is not used for S3F80JB because an external peripheral interface is not implemented in the S3F80JB The program initialization routine should clear the EMT register to 00H following a reset Modification of EMT values during normal operation may cause a system malfunction 4 10 ELECTRONICS S3F80JB CONTROL REGISTERS FLAGS System Flags Register D5H Seti BankO Reset Value x 0 0 Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only 7 Carry Flag Bit C Operation does not generate carry or borrow condition Operation generates a carry out or borrow into high order bit 7 6 Zero Flag Bit Z 0 Operation result is a non zero value 1 Operation result is zero 5 Sign Flag Bit S Operation generates a positive number MSB 0 Operation generates a negative number MSB 1 4 Overflow Flag Bit V EN Operation result is lt 127 or gt 128 Operation result is gt 127
214. ld be faster than count A clock ELECTRONICS 12 1 COUNTER 53 80 6 7 MUX CLK 16 Bit Down Counter yer To Other Block P3 1 REM Repeat CACON 3 Control Interrupt caren gt IRQ2 Control i INT GEN CAINT ji 1 Counter A Data Low Byte Register O CACON 2 CACON 4 5 fosc Counter A Data High Byte Register Data Bus The value of the CADATAL register is loaded into the 8 bit counter when the operation of the counter A stars If a borrow occurs the value of the CADATAH register is loaded into the 8 bit counter However if the next borrow occurs the value of the CADATAL register is loaded into the 8 bit counter Figure 12 1 Counter A Block Diagram 12 2 ELECTRONICS S3F80JB COUNTER A COUNTER A CONTROL REGISTER CACON The counter A control register CACON is located in F3H Set 1 Bank 0 and is read write addressable CACON contains control settings for the following functions See Figure 12 2 Counter A clock source selection Counter A interrupt enable disable Counter A interrupt pending control read for status write to clear Counter A interrupt time selection Counter A Control Register CACON F3H Set 1 Bank 0 R W Counter A Input Clock Selection Bits Counter A Output Flip Flop Control Bit CAOF 00 fosc 0 T F F is low 01 fosc 2 1 T F F is high 10 fosc 4 Counter A Mode Selection Bit 0 One shot mode 1
215. malfunction To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release The functional components of the basic timer block are Clock frequency divider fosc divided by 4096 1024 or 128 with multiplexer 8 bit basic timer counter BTCNT FDH Set 1 Read only Basic timer control register BTCON Set 1 R W TIMER 0 Timer 0 has three operating modes one of which you select using the appropriate TOCON setting Interval timer mode Capture input mode with a rising or falling edge trigger at the P3 0 pin PWM mode Timer 0 has the following functional components Clock frequency divider fosc divided by 4096 256 or 8 with multiplexer External clock input pin TOCK 8 bit timer 0 counter TOCNT 8 bit comparator and 8 bit reference data register TODATA O pins for capture input or match output Timer 0 overflow interrupt IRQO vector FAH and match capture interrupt IRQO vector FCH generation Timer 0 control register D2H Set 1 R W NOTE The CPU clock should be faster than basic timer clock and timer 0 clock ELECTRONICS 10 1 BASIC TIMER and TIMER 0 S3F80JB BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disa
216. mer and disabling the timer 2 interrupts Timer 2 Control Register T2CON E8H Set 1 Bank 1 R W Timer 2 Input Clock Selection Bits Timer 2 Interrupt Pending Bit 00 fosc 4 0 No interrupt pending 01 fosc 8 0 Clear pending bit when write 10 fosc 16 1 Interrupt is pending 11 2 Internal clock T F F Timer 2 Interrupt Match capture Enable Bit 0 Disable interrupt Timer 2 Operating Mode Selection Bits 1 Enable interrupt 00 Interval mode 01 Capture mode capture on rising edge counter running OVF can occur L Timer 2 Overflow Interrupt Enable Bit 10 Capture mode capture on falling edge 0 Disable overflow interrupt counter running OVF can occur 1 Enable overflow interrupt 11 Capture mode capture on rising and falling edge counter running OVF can occur Timer 2 Counter Clear Bit 0 No effect 1 Clear the timer 0 counter when write Figure 13 4 Timer 2 Control Register T2CON ELECTRONICS 13 5 TIMER 2 53 80 Timer2 Counter High Byte Register T2CNTH E4H Set 1 Bank 1 Read only Reset Value 00H Timer 2 Counter Low Byte Register T2CNTL E5H Set 1 Bank 1 Read only Reset Value 00H Timer 2 Data High Byte Register T2DATAH E6H Set 1 Bank 1 R W Reset Value FFH Timer 2 Data Low Byte Register T2DATAL E7H Set 1 Bank 1 R W Reset Value FFH Figure 13 5 Timer 2 Registers T2CNTH T2CNTL T2DATAH T2DATAL 13 6 EL
217. microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bit 0 to IRQO bit 1 to IRQ1 and so on A 0 indicates that no interrupt request is currently being issued for that level a 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH Set 1 Bank 0 Read only IR IRQ2 zi IRQ3 IRQ4 IRQ6 IS IRQ7 Interrupt Level Request Enable Bits 0 Interrupt level is not pending 1 Interrupt level is pending Figure 5 9 Interrupt Request Register IRQ 5 14 ELECTRONICS S3F80JB INTERRUPT STRUCTURE INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits One type is automatically cleared by hardw
218. mmediate Addressing 1 0 8 ormai apart 3 14 4 1 Register Description 4 4 S3F80JB MICROCONTROLLER List of Figures Continued Figure Title Page Number Number 5 1 S3C8 S3F8 Series Interrupt emen 5 2 5 2 SSF80JB Interrupt Structure eese nennen emen 5 4 5 8 ROM Vector Address Area sese eene nnn 5 5 5 4 Interr pt Function Diagraim 3 50 ian ob pe ied tendi ei 5 8 5 5 System Mode Register 5 5 10 5 6 Interrupt Mask Register IMR esee emen 5 11 5 7 Interrupt Request Priority 5 12 5 8 Interrupt Priority Register mn 5 13 5 9 Interrupt Request Register 5 14 6 1 System Flags Register 5 6 6 7 1 Main Oscillator Circuit External Crystal or Ceramic Resonator 7 1 7 2 External Glock CIIGUID s nilo dete tected i eene E e Re 7 1 7 8 System Clock Circuit Diagram essen eem emen 7 2 7 4 System Clock Control Register CLKCON sese 7 3 8 1 RESET Sources of The S3F80JB eese 8 2 8 2 RESET Block Diagram of The 5 8 8 3 8 3 RESET Block Diagram by LVD for The S3F80JB IN STOP MODE 8 4 8 4 Internal Power On Reset
219. mory location 1033H OCDH and external data memory location 1033H ODDH LDCD R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is decremented by one R8 R6 10H R7 32H RR6 lt 6 1 LDED R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one RR6 6 1 R8 ODDH R6 10H R7 32H ELECTRONICS S3F80JB INSTRUCTION SET LDCI LDEI Load Memory and Increment LDCI LDEI Operation Flags Format Examples dst src dst lt src m x 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the source are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Irr even for program memory and odd for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory locations 1033H OCDH and 1034H OC5H external data memory locations 1033H ODDH and 1034H OD5H LDCI R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt
220. nable Bit External Interrupts P2 7 P2 4 Disable mask Enable un mask 4 Interrupt Level 4 IRQ4 Enable Bit External Interrupts 2 3 2 0 Disable mask 1 Enable un mask 3 Interrupt Level 3 IRQ3 Enable Bit Timer 2 Match or Overflow Disable mask Enable un mask 2 Interrupt Level 2 IRQ2 Enable Bit Counter Interrupt 0 Disable mask 1 Enable un mask 4 Interrupt Level 1 IRQ1 Enable Bit Timer 1 Match or Overflow Disable mask Enable un mask 0 Interrupt Level 0 IRQO Enable Bit Timer 0 Match or Overflow Disable mask 1 Enable un mask 4 14 ELECTRONICS S3F80JB CONTROL REGISTERS IPH instruction Pointer High Byte DAH Seti Reset Value X X X X X x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 1 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address IP15 IP8 The lower byte of the IP address is located in the IPL register DBH IPL instruction Pointer Low Byte DBH Seti Bit Identifier 7 6 5 4 3 2 1 0 Reset Value X X X X X X X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address
221. nal data memory location 0105H 01H 0104H RO contents of program memory location 1104H 1000H 0104H RO 88H R2 01H 04H RO lt contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H 04H RO lt contents of program memory location 1104H RO 88H RO contents of external data memory location 1104H RO 98H 11H contents of RO is loaded into program memory location 1105H 1105H lt 11H 11H contents of RO is loaded into external data memory location 1105H 1105H lt NOTE These instructions are not supported by masked ROM type devices ELECTRONICS INSTRUCTION SET S3F80JB LDCD LDED Load Memory and Decrement LDCD LDED dst rc Operation Flags Format Examples 6 54 dst lt src r lt m 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD references program memory and LDED references external data memory The assembler makes Irr an even number for program memory and an odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program me
222. nalog input 1 External reference CINO 2 analog input CIN3 reference input Conversion Timer Control Bit 0 8x2 fosc 256us at 8MHz 1 8x24 fosc 32us at 8MHz Comparator Enale Disable Bit 0 Comparator operation disable 1 Comparator operation enable Figure 14 3 Comparator Mode Register CMOD Comparator Input Selection Register CMPSEL EBH Set1 Bank 1 R W 6 s 4 2 P2 4 Function Selection Bit 0 Normal I O selection 1 Alternative function enable CINO P2 5 Function Selection Bit Not used for S3F80JB 0 Normal I O selection 1 Alternative function enable CIN1 P2 6 Function Selection Bit 0 Normal I O selection 1 Alternative function enable CIN2 P2 7 Function Selection Bit 0 Normal I O selection 1 Alternative function enable CIN3 Figure 14 4 Comparator Input Selection Register CMPSEL 14 4 ELECTRONICS S3F80JB COMPARATOR Comparator Result Register CMPREG EBH Set1 Bank 1 R Not used for S3F80JB Comparator Result Data Figure 14 5 Comparator Result Register CMPREG ELECTRONICS 14 5 S3F80JB EMBEDDED FLASH MEMORY INTERFACE EMBEDDED FLASH MEMORY INTERFACE OVERVIEW The S3F80JB has an on chip flash memory internally instead of masked ROM The flash memory is accessed by instruction LDC This is a sector erasable and a byte programmable flash User can program the data in a flash memory area any time you want The S3F80JB s embed
223. nd then internal flash memory of S3F80JB be programmed by Serial OTP MTP Tools SPW2 plus single programmer or GW PRO2 gang programmer and so on The other modules except flash memory module are at a reset state This mode doesn t support the sector erase but chip erase all flash memory erased at a time and two protection modes Hard lock protection Read protection The read protection mode is available only in tool program mode So in order to make a chip into read protection you need to select a read protection option when you write a program code to a chip in tool program mode by using a programming tool After read protect all data of flash memory read 00 This protection is released by chip erase execution in the tool program mode Table 15 1 Descriptions of Pins Used to Read Write the Flash in Tool Program Mode Normal Chip During Programming Pin Name Pin Name Pin No y o Function P3 0 SDAT 3 30 Serial data pin Output port when reading input port when writing SDAT P3 0 can be assigned as an input or push pull output port P3 1 SCLK 4 31 Serial clock pin Input only pin TEST TEST 9 4 Tool mode selection when TEST pin sets Logic value 1 If user uses the flash writer tool mode ex spw2 etc user should connect TEST pin to Vpp S3F80UB supplies high voltage 12 5V by internal high voltage generation circuit nRESET nRESET 12 7 Chip Initialization Vpp Vpp 5 32 Power supply pin for lo
224. ng is available in Tool Program Mode only ELECTRONICS 17 13 S3F80JB ELECTRICAL DATA 8MHZ OVERVIEW ELECTRICAL DATA 8 2 In this section S3F80JB electrical characteristics are presented in tables and graphs The information is arranged in the following order Absolute Maximum Ratings D C Electrical Characteristics Characteristics of Low Voltage Detect Circuit Data Retention Supply Voltage in Stop Mode Typical Low Side Driver Sink Characteristics Typical High Side Driver Source Characteristics Stop Mode Release Timing When Initiated by an External Interrupt Stop Mode Release Timing When Initiated by a Reset Stop Mode Release Timing When Initiated by a LVD Input Output Capacitance A C Electrical Characteristics Input Timing for External Interrupts Input Timing for Reset Comparator Electrical Characteristics Oscillation Characteristics Oscillation Stabilization Time Operating Voltage Range A C Electrical Characteristics for Internal Flash ROM ELECTRONICS 18 1 ELECTRICAL DATA 8MHz 53 80 Table 18 1 Absolute Maximum Ratings TA 25 C Parameter Conditions Rag Unt Yoo Y A vo 3 V All O pins active 6 m Output Current Low lot One I O pin active All O pins active Operating 25 to 85 Temperature Storage Tera 65 to 150 V Table 18 2 D C Electrical Charact
225. nued Program Memory Next OPCODE lt Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions ELECTRONICS ADDRESSING MODES 53 80 INDIRECT ADDRESS Indirect Address IA mode the instruction specifies an address located the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory only an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory Next Instruction LSB Must be Zero dst Current Instruction gt OPCODE Lower Address Byte Program Memory Upper Address Byte 4 Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONICS S3F80JB ADDRESSING MODES RELATIVE ADDRESS MODE RA In Relative Address RA mode a two s complement signed displacement between
226. ode the procedure of setting Hard Lock Protection is following that In tool mode the manufacturer of serial tool writer could support Hardware Protection Please refer to the manual of serial program writer tool provided by the manufacturer The program procedure in user program mode 1 Set Flash Memory User Programming Enable Register FMUSR 10100101B 2 Set Flash Memory Control Register FMCON 01100001B 3 Set Flash Memory User Programming Enable Register FMUSR 00000000B PROGRAMMING TIP Hard Lock Protection SB1 LD FMUSR 0A5H User program mode enable LD FMCON 01100001B Select Hard Lock Mode and Start protection LD FMUSR 00H User program mode disable SBO 15 18 ELECTRONICS S3F80JB LOW VOLTAGE DETECTOR LOW VOLTAGE DETECTOR OVERVIEW The S3F80JB micro controller has a built in Low Voltage Detector LVD circuit which allows LVD and LVD_FLAG detection of power voltage The S3F80UB has two options in LVD and LVD FLAG voltage level according to the operating frequency to be set by smart option Refer to the page 2 4 Operating Frequency 4MHz e Low voltage detect level for Backup Mode and Reset LVD 1 9V Typ 200mV e Low voltage detect level for Flash Flag Bit FLAG 2 15V 200mV Operating Frequency 8MHz e Low voltage detect level for Backup Mode and Reset LVD 2 15V Typ 200mV e Low voltage detect level for Flash Flag Bit L_VD_FLAG 2 3V Typ
227. ode only 6 0 7 1 4 Mode Selection Bits fo fo C MOS input mode interrupt on falling edges C MOS input mode interrupt rising and falling edges Push pull output mode C MOS input mode interrupt on rising edges 5 and 4 PO 6 INT4 Mode Selection Bits 79 input moder interaptonfalingedges Fo emos input moder interupton rising and taling sages 7119 Push putouputmode 7 3 and 2 P0 5 INT4 Mode Selection Bits 79 input modeinteraptonfalingedges Fo input mode interupton rising and taling sages 1 and 0 P0 4 INT4 Mode Selection Bits fo C MOS input mode interrupt on falling edges ofa C MOS input mode interrupt on rising and falling edges KERJ Push pull output mode 1 C MOS input mode interrupt on rising edges NOTES 1 INT4 external interrupts at the 0 7 0 4 pins share the same interrupt level IRQ7 and interrupt vector address E8H 2 You can assign pull up resistors to individual port 0 pins by making the appropriate settings to the POPUR register POPUR 7 POPUR 4 ELECTRONICS 4 19 CONTROL REGISTERS S3F80JB POCONL Port 0 Control Register Low Byte E9H Seti BankO Bit Identifier 7 e 5 3 2 j 9 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 6 P0 3 INT3 Mode Select
228. og input pin for comparator P3 0 is configured input functions Input mode with or without pull up for normal input or TOCAP or output functions push pull or open drain output mode for normal output or TOPWM P3 1 is configured input functions Input mode with or without pull up for normal input or output functions push pull or open drain output mode for normal output or REM function P3 1 is dedicated for IR drive pin and P3 0 can be used for indicator LED drive P3 2 is configured only input pin with pull up resistor for normal input or TOCK function P3 3 is configured only input pin with pull up resistor for normal input T1CAP function or T2CAP function P3 3 can be used for IR signal capture pin with T1CAP function or T2CAP function 2 bit general purpose I O port Input without or with pull up open drain output or push pull output P3 7 9 2 P3 7 is not configured for I O pin and it only used to control carrier signal on off 8 bit general purpose I O port Input without or with pull up open drain output or push pull output This port is dedicated for key output in IR controller application ELECTRONICS S3F80JB PORTS Table 9 3 S3F80JB Port Configuration Overview 32 SOP Pot Configuration Options 8 bit general purpose I O port Input or push pull output external interrupt input on falling edges rising edges or both edges all PO pin circuits have noise filters and interrupt enable
229. ogram Memory Register File 8 bit register file address N dst ADDRESS OPCODE Fontso register in register One Operand file Instruction Example Address of operand used by instruction Value used in OPERAND instruction execution Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File ELECTRONICS 3 3 ADDRESSING MODES 53 80 INDIRECT REGISTER ADDRESSING MODE Continued Register File Program Memory Example es Instruction dst 1 air References OPCODE Points to Program Register Pair Address Points to Program Memory Program Memory Sample Instructions Value used gt OPERAND GALL anne Loc NENNT JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS S3F80JB ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE Continued Register File MSB Points to RPO or RP1 poene RPO or RP1 i Selected RP points Program Memory to start of woking register 4 bit bo S Working m ip 9 ESBS oe Register s Address Point to the ADDRESS DPOUDE Woking Register 2 1 of 8 Sample Instruction Value used in 4 OPERAND OR R3 R6 instruction Figure 3 5 Indirect Working Register Addressing to Register File ELECTRONICS 3 5 ADDRESSING MODES
230. onnect SW2 Smart option at address 3EH Dip switch for smart option These 1byte are mapped address 3EH for special function Refer to the page 2 3 SW3 Smart option at address 3FH Dip switch for smart option These 1byte are mapped address 3FH for special function Refer to the page 2 3 Y1 External clock source Connecting point for external clock source like a crystal J3 Header for flash serial To program an internal flash connect the signals with J3 programming signals flash writer tool To Target System is supplied Target Board is not supplied Target Board is supplied Join 2 3 User Vcc Vpp Vpp to Target System Vpp to Target System NOTE S3F80JB Target board consists of 74HC11N regulator and other components In case of 74HC11N typical operating voltage is 5V So 80jb target board includes a regulator for 3 3V generation As you know SSF80JB typical operating voltage is 3 3V Although open i500 supports 3 3 V for target board s power source we recommend that you connect jumper of open i500 power source to 5V Check the interface board s jumper status between emulator and target board nRESET LED This LED is OFF when the Reset switch is ON IDLE LED This is LED is ON when the evaluation chip S3E80JB is in idle mode STOP LED This LED is ON when the evalution chip S3E80JB is in stop mode 20 4 ELECTRONICS S3F80JB P2 3 INT8 P2 4 INT9 CINO P3 0 TOPWM TOCAP SDAT P3 1 REM SCLK VDD Vss XOUT XIN TES
231. operating modes 4 bit analog voltage comparator with four three channels internal external reference 8 bit counter with auto reload function and one shot or repeat control The S3F80JB is a versatile general purpose microcontroller which is especially suitable for use as remote transmitter controller It is currently available in a 32 pin SOP and 44 pin QFP package ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES CPU SAM8 RC CPU core Memory e Program memory 64 Kbyte Internal Flash Memory Sector size 128Bytes 10years data retention Fast Programming Time Sector Erase 10ms Byte Program 32us Byte Programmable User programmable by LDC instruction Sector 128 bytes Erase available External serial programming support Endurance 10 000 Erase Program cycles Expandable OBPTM On Board Program Data memory 272 byte general purpose RAM Instruction Set e 78 instructions e IDLE and STOP instructions added for power down modes Instruction Execution Time 500 ns at 8 MHz fosc minimum Interrupts e 24 interrupt sources with 18 vectors and 8 levels Ports e Four 8 bit I O ports 2 P4 and 6 bit port P3 for a total of 38 bit programmable pins 44 QFP e Four 8 bit I O ports PO P2 P4 and 4 bit port P3 for a total of 36 bit programmable pins 42 SDIP e Three 8 bit I O ports 2 and one 2 bit I O port P3 for a total of 26 bit programma
232. or this purpose System Mode Register SYM DEH Set 1 Bank 0 R W External Interface Tri state Enable Bit Global Interrupt Enable 0 Normal operation Bit Tri state disabled Not used Fast Interrupt Level 0 Disable all 1 High impedance Selection Bits 1 Enable all Tri state enabled Fast Interrupt Enable Bit IRQO 0 Disable fast IRQ1 1 Enable fast IRQ2 IRQS IRQ4 IRQ5 IRQ6 IRQ7 0000 3230 000 NOTE In case of 53 80 an external memory interface is not implemented Figure 5 5 System Mode Register SYM 5 10 ELECTRONICS S3F80JB INTERRUPT STRUCTURE INTERRUPT MASK REGISTER IMR The interrupt mask register IMR DDH Set 1 is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1and Banko Bit values can be read and written by instructions using the register addressing mode Interrupt Mask Register IMR DDH Set 1 Bank 0 R W IRQO IRQ1 IRQ2
233. ort1 0 1 7 is set to address port and data port for chip test So output disable signal of Port1 0 1 7 is toggling to Input Output mode gt When S3F80JB Address amp Data port Part 1 0 Advan equipment S3F80JB Port1 0 1 7 is used to address amp data port between Advan equipment and S3F80JB When Advan equipment sends data to S3F80JB port1 0 1 7 is input mode And when Advan equipment receives next address to SSF80JB port1 0 1 7 is output mode l e port1 0 1 7 is toggling to Input Output mode during chip test ELECTRONICS 3 S3F80JB Important Note gt When S3F80J9 Address amp Data port Port1 0 Port1 2 Port1 3 Port2 6 Port2 7 e On S3F80J9 address amp data port is different from S3F80JB Because the 28 SOP type doesn t have port1 4 1 7 port1 0 1 3 and port2 4 2 7 are used to address amp data port S3F80J9 is supported to 32 SOP 28 SOP type 4 NOTICE When serial writing programming on S3F80JB port1 4 1 5 1 6 1 7 should be floating node or not connected to any device effected to damage by toggling 4 ELECTRONICS
234. ow interrupt falling edge counter running OVF can occur Timer 1 Counter Clear Bit 0 No effect 1 Clear the timer 0 counter when write Figure 11 4 Timer 1 Control Register T1CON ELECTRONICS 11 5 TIMER 1 53 80 Timer1 Counter High byte Register T1CNTH F6H Set 1 Bank 0 R Reset Value 00H Timer 1 Counter Low byte Register T1CNTL F7H Set 1 Bank 0 R 7 6 5 4 3 2 4 0 LSB Reset Value 00H Timer 1 Data High byte Register T1 DATAH F8H Set 1 Bank 0 R W vss 7 6 5 4 3 2 4 0 LSB Reset Value FFH Timer 1 Data Low byte Register T1DATAL F9H Set 1 Bank 0 R W Reset Value FFH Figure 11 5 Timer 1 Registers T1CNTH T1CNTL T1DATAH T1DATAL 11 6 ELECTRONICS S3F80JB COUNTER A COUNTER OVERVIEW The S3F80JB microcontroller has one 8 bit counter called counter A Counter A which can be used to generate the carrier frequency has the following components See Figure 12 1 Counter A control register CACON 8 bit down counter with auto reload function Two 8 bit reference data registers CADATAH and CADATAL Counter A has two functions As anormal interval timer generating a counter A interrupt IRQ2 vector at programmed time intervals supply a clock source to the 16 bit timer counter module Timer 1 for generating the Timer 1 overflow interrupt NOTE The CPU clock shou
235. own in Figure 9 1 NOTE The data register for port 3 contains 6 bits for 0 5 and an additional status bit P3 7 for carrier signal on off Table 9 4 Port Data Register Summary Register Name Mnemonic Decimal Hex Location R W i P3 P4 Port 3 data register Set 1 Bank 0 R W Port 4 data register Set 1 Bank 0 R W Because port is a 6 bit I O port the port data register only contains values for P3 0 P3 5 The register also contains a special carrier on off bit P3 7 See the port3 description for details All other I O ports are 8 bit Because port 3 is a 6 bit I O port the port data register only contains values for P3 0 P3 5 The P3 register also contains a special carrier on off bit P3 7 See the port 3 description for details All other S3F80JB I O ports are 8 bit Figure 9 1 S3F80JB I O Port Data Register Format 9 4 ELECTRONICS S3F80JB PORTS PULL UP RESISTOR ENABLE REGISTERS You can assign pull up resistors to the pin circuits of individual pins in and port2 To do this you make the appropriate settings to the corresponding pull up resistor enable registers POPUR and P2PUR These registers are located in set 1 bank 0 at locations E7H and EEH respectively and are read write accessible using Register addressing mode You can assign a pull up resistor to the port 1 and port 4 pins using basic port configuration setting in t
236. parator Result Register CMPREG sse nemen 14 5 15 1 Program Memory Address 15 3 15 2 Smart e ee P tem ee eet 15 4 15 3 Flash Memory Control Register 15 6 15 4 Flash Memory User Programming Enable Register 15 6 15 5 Flash Memory Sector Address Register FMSECH 15 7 15 6 Flash Memory Sector Address Register 5 15 7 15 7 Sector Configurations in User Program Mode 15 8 15 8 Sector Erase Flowchart in User Program 15 9 15 9 Byte Program Flowchart in a User Program 15 13 15 10 Program Flowchart in a User Program 15 14 16 1 Low Voltage Detect LVD Block Diagram sassssssssssssssusssusscunsessussensscusseunsaussesssessenseunes 16 2 16 2 Low Voltage Detect Control Register LVDCON sssnssssssssssssusssusssusssusscunsasesascussensseuses 1 6 3 17 1 Typical Low Side Driver Sink Characteristics P3 1 only mm 17 5 17 2 Typical Low Side Driver Sink Characteristics P3 0 and P2 0 2 3 6 17 5 17 3 Typical Low Side Driver Sink Characteristics Porto Porti P2 4 2 7 P3 4 P3 5 and Port4 ssssssssssssssssss
237. pending Pending 6 Level 6 IRQ6 Request Pending Bit External Interrupts 0 3 0 0 0 Not pending 1 Pending 5 Level 5 IRQ5 Request Pending Bit External Interrupts P2 7 P2 4 Not pending Pending 4 Level 4 IRQ4 Request Pending Bit External Interrupts P2 3 P2 0 Not pending 1 Pending 3 Level 3 IRQ3 Request Pending Bit Timer 2 Match Capture or Overflow 0 Not pending Pending 2 Level 2 IRQ2 Request Pending Bit Counter A Interrupt Not pending Pending 4 Level 1 IRQ1 Request Pending Bit Timer 1 Match Capture or Overflow 0 Not pending 1 Pending 0 Level 0 IRQO Request Pending Bit Timer 0 Match Capture or Overflow Not pending Pending ELECTRONICS 4 17 CONTROL REGISTERS S3F80JB LVDCON control Register EOH Seti Banki Reset Value 0 Read Write x R W Addressing Mode Register addressing mode only 7 1 Not used for S3F80JB 0 LVD Flag 2 3V Indicator Bit Vpop gt LVD_FLAG Level 2 3V Vpp lt LVD_FLAG Level 2 3V NOTE 4 18 When LVD detects LVD_FLAG level 2 3V LVDCON O flag bit is set automatically When VDD is upper 2 3V LVDCON O flag bit is cleared automatically ELECTRONICS S3F80JB CONTROL REGISTERS POCONH Port 0 Control Register High Byte E8H Seti Bit Identifier 6 5 3 2 j a 9 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing m
238. perand and the carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carry flag the initial value of the carry flag replaces bit 7 MSB LH Flags Format Examples 6 74 C Setif the bit rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Setifthe result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 CO R C1 IR Given Register 00H register 01H 02H register 02H 17H and C 0 RRC 00H gt Register 00H 2AH C 1 RRC 01H gt Register 01H 02H register 02H OBH C 1 In the first example if general register OOH contains the value 55H 01010101B the statement RRC OOH rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2AH 00101010B in destination register The sign flag and overflow flag are both cleared to 0 ELECTRONICS S3F80JB INSTRUCTION SET SBO Select Bank 0 SBO Operation BANK lt 0 The SBO instruction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting bank 0 registe
239. put and CAOF mode 44 pin package ORG 0100H Reset address START DI LD CADATAL 70 2 Set 17 5 ms LD CADATAH 35 2 Set 8 75 ms LD P3CON 11110010B Set P3 to C MOS push pull output Set P3 1 to REM output LD CACON 00000110B Clock Source Fosc Disable Counter A interrupt Select repeat mode for Counter A Start Counter A operation Set Counter A Output Flip flop CAOF high LD P3 80H Set P3 7 Carrier On Off to high This command generates 38 kHz 1 3duty pulse signal through P3 1 12 6 ELECTRONICS S3F80JB COUNTER A PROGRAMMING TIP To generate a one pulse signal through P3 1 This example sets Counter A to the one shot mode sets the oscillation frequency as the Counter A clock source and CADATAH and CADATAL to make a 40 us width pulse The program parameters are MEM Counter A is used in one shot mode Oscillation frequency is 4 MHz 1 clock 0 25 us 40 us 0 25 us 160 CADATAL 1 Set 1 C MOS push pull output and CAOF mode 44 pin package ORG 0100H Reset address START DI LD CADATAH 160 2 Set 40 ms LD CADATAL 1 Set any value except 00H LD P3CON 11110010B Set P3 to C MOS push pull output Set P3 1 to REM output LD CACON 00000001B Clock Source Fosc Disable Counter A interrupt Select one shot mode for Counter A Stop Counter A operation Set Counter A Output Flip Flop
240. r FMUSR to 10100101B Set Flash Memory Sector Address Register FMSECH and FMSECL Set Flash Memory Control Register FMCON to 10100001B Set Flash Memory User Programming Enable Register FMUSR to 00000000B SB1 Select Bank1 FMUSR 4 0 5 User Programimg Mode Enable FMSECH High Address of Sector lt Low Address of Sector FOOL SCIO BaSe Address 110100001 FMCON FMUSR 00H Mode Select amp Start Erase User Prgramming Mode Disable Select BankO Finish One Sector Erase Figure 15 8 Sector Erase Flowchart in User Program Mode NOTES 1 If user erases a sector selected by Flash Memory Sector Address Register FMSECH and FMSECL FMUSR should be enabled just before starting sector erase operation And to erase a sector Flash Operation Start Bit of FMCON register is written from operation stop 0 to operation start 1 That bit will be cleared automatically just after the corresponding operation completed In other words when S3F80UB is in the condition that flash memory user programming enable bits is enabled and executes start operation of sector erase it will get the result of erasing selected sector as user s a purpose and Flash Operation Start Bit of FMCON register is also clear automatically 2 If user executes sector erase operation with FMUSR disabled 0 bit Flash Operation Start Bit remains high which
241. r Source Characteristics P3 0 P2 0 2 3 TYPICAL VDD VOH VDD 3 3V TYPICAL VDD VOH VS VDD IOH 1mA 1 20 850 1 00 252 rau 25C 0 80 0 60 0 40 5 5 CO 020 o 0 05 lt f lt 0 00 Q m a 0 1 2 3 4 5 6 2 18V 2 3 2 8 3 3 3 8 5 T VDD V Figure 18 6 Typical High Side Driver Source Characteristics 10 Port1 P2 4 2 7 P3 4 P3 5 and Port4 NOTE Figure 18 5 and 18 6 are characterized and not tested on each device ELECTRONICS 18 7 ELECTRICAL DATA 8 2 Stop Mode Data Retention Mode A Execution of STOP Instrction EXT INT lt gt 53 80 Idle Mode Basic Timer Active gt Normal Operating Mode Figure 18 7 Stop Mode Release Timing When Initiated by an External Interrupt Stop Mode 4 Execution of STOP Instrction nRESET NOTE twarr is the same as 4096 x 16 x 1 fosc Oscillation Stabilization Time Mode Figure 18 8 Stop Mode Release Timing When Initiated by a Reset 18 8 ELECTRONICS S3F80JB ELECTRICAL DATA 8MHz Reset Occur Stop Mode lt gt gt Normal Operating Mode Oscillation Stabilization Time Back up Mode Execution of STOP Instrction Data Retention Time NOTE twar is the same as 4096 x
242. r addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The statement SBO clears FLAGS 0 to 0 selecting bank 0 register addressing ELECTRONICS 6 75 INSTRUCTION SET S3F80JB SB1 Select Bank 1 SB1 Operation BANK lt 1 The SB1 instruction sets the bank address flag in the FLAGS register FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the register file Bank 1 is not implemented in some KS88 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 5F Example The statement SB1 sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented 6 76 ELECTRONICS S3F80JB INSTRUCTION SET SBC subtract With Carry SBC Operation Flags Format Examples dst src dst dst src c The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands Set if a borrow occurred src gt dst cleared otherwi
243. r others ELECTRONICS 16 1 LOW VOLTAGE DETECTOR S3F80JB NOTES 1 When smart option bit is set 1 operating frequency is selected 8MHz and LVD voltage level is 2 3V On the other hand when smart option bit is set 0 operating frequency is selected 4MHz and LVD voltage level is 2 15V 2 When smart option bit is set 1 operating frequency is selected 8MHz and LVD FLAG voltage level is 2 15V On the other hand when smart option bit is set 0 operating frequency is selected 4MHz and LVD FLAG voltage level is 1 9V 3 Aterm of LVD is a symbol of parameter that means Low Level Detect Voltage for Back Up Mode 4 Aterm of LVD FLAG is a symbol of parameter that means Low Level Detect Voltage for Flag Indicator 5 Incase of 8MHz operating frequency the voltage gap between LVD and LVD_FLAG is 150mV In case of 4MHz operating frequency the voltage gap between LVD and LVD_ FLAG is 250mV Resistor String IPOR LVD Control Bit LVD smart option 7 03FH BackupMode Reset STOP LVDCON 0 LVD Flag Bit BANDGAP Figure 16 1 Low Voltage Detect LVD Block Diagram 16 2 ELECTRONICS S3F80JB LOW VOLTAGE DETECTOR LOW VOLTAGE DETECTOR CONTROL REGISTER LVDCON LVDCON 0 is used flag bit to indicate low battery in IR application or others When LVD circuit detects LVD FLAG LVDCON O flag bit is set automatically The reset value of LVDCON is 00H Low Voltage Detect Control
244. re 15 1 Program Memory Address Space ELECTRONICS 15 3 EMBEDDED FLASH MEMORY INTERFACE S3F80JB SMART OPTION Smart option is the program memory option for starting condition of the chip The program memory addresses used by smart option are from 003CH to 003FH The S3F80JB only use 003EH and 003FH User can write any value in the not used addresses 003CH and 003DH The default value of smart option bits in program memory is OFFH IPOR disable LVD enable in the stop mode Normal reset vector address 100H ISP protection disable Before execution the program memory code user can set the smart option bits according to the hardware option for user to want to select ROM Address 003CH Not used ROM Address 003DH Not used ROM Address 003EH ISP Reset Vector Change Selection Bit Note1 Not used ISP Protection Size Selection Bits Nete4 0 OBP Reset vector address 00 256 bytes 1 Normal vector address 100H 01 512 bytes 10 1024 bytes ISP Reset Vector Address Selection Bits Nete2 11 2048 bytes 00 200H ISP Area size 256 bytes 01 300H ISP Area size 512 bytes 10 500H ISP Area size 1024 bytes 11 900H ISP Area size 2048 bytes ISP Protection Enable Disable Bit Note3 0 Enable Not erasable 1 Disable Erasable ROM Address 003FH Reserved IPOR LVD Control Bit 0 IPOR enable LVD disable in the stop mode 1 disable LVD enable in the stop mode Figure 1
245. rectly writing or reading port registers No special I O instructions are required For IR applications portO port1 and port2 are usually configured to the keyboard matrix and port 3 is used to IR drive pins Table 9 1 9 2 and 9 3 give you a general overview of 53 80 I O port functions ELECTRONICS 9 1 PORTS 53 80 Table 9 1 S3F80JB Port Configuration Overview 44 QFP Port Configuration Options 8 bit general purpose I O port Input or push pull output external interrupt input on falling edges rising edges or both edges all PO pin circuits have noise filters and interrupt enable disable register POINT and pending control register POPND Pull up resistors can be assigned to individual PO pins using POPUR register settings This port is dedicated for key input in IR controller application 8 bit general purpose I O port Input without or with pull up open drain output or push pull output This port is dedicated for key output in IR controller application P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 8 bit general purpose port Input or push pull output The P2 pins 2 0 2 7 can be used as external interrupt inputs and have noise filters The P2INT register is used to enable disable interrupts and P2PND bits can be polled by software for interrupt pending control Pull up resistors can be assigned to individual P2 pins using P2PUR register settings Also P2 4 P2 7 can be assigned individually as anal
246. red Format Bytes Cycles Opcode Addr Mode Hex dst src opc 2 4 02 6 03 r Ir opc src dst 3 6 04 R R 05 R IR opc dst src 3 6 06 R IM Examples Given R1 12H R2 register 01H 21H register 02H register OAH ADD R1 R2 gt R1 15H R2 03H ADD R1 R2 gt R1 1CH R2 03H ADD 01H 02H gt Register 01H 24H register 02H 03H ADD 01H 02H gt Register 01H 2BH register 02H 03H ADD 01H 25H gt Register 01H 46H In the first example destination working register R1 contains 12H and the source working register R2 contains 03H The statement ADD R1 R2 adds 03H to 12H leaving the value 15H in register R1 ELECTRONICS INSTRUCTION SET S3F80JB AND Logical AND AND Operation Flags Format Examples 6 16 dst src dst lt dst AND src The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation results in a 1 bit being stored whenever the corresponding bits in the two operands are both logic ones otherwise a 0 bit value is stored The contents of the source are unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 53 r Ir opc SIC dst 3 6 54 R R 55 R IR opc dst src 3 6 56 R IM Given R1 12H
247. required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 7F Example The statement STOP halts all microcontroller operations ELECTRONICS 6 81 INSTRUCTION SET SUB subiract SUB Operation Flags Format Examples 6 82 dst src dst lt dst src S3F80JB The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand Always set to 1 SONO set otherwise indicating a borrow dst SIC opc SIC dst opc dst src Set if a borrow occurred cleared otherwise Set if the result is 0 cleared otherwise Set if the result is negative cleared otherwise Set if arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise Bytes Cycles Opcode Hex 2 4 22 6 23 3 6 24 25 3 6 26 Addr Mode dst src r r r Ir R R R IR R IM Cleared if there is a carry from the most significant bit of the low order four bits of the result Given R1 12H R2 register 01H 21H register 02H register OAH SUB R1 R2 gt SUB R1 R2 gt SUB 01H 02H gt SUB 01
248. rite NOTE A timer 0 overflow interrupt pending condition is automatically cleared by hardware However the timer 0 match capture interrupt IRQO vector FCH must be cleared by the interrupt service routine S W ELECTRONICS 4 41 CONTROL REGISTERS S3F80JB T1CON Timer 1 Control Register FAH Seti 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 and 6 Timer 1 Input Clock Selection Bits 00 ee ee Internal clock counter A flip flop T FF 5 and 4 Timer 1 Operating Mode Selection Bits Interval timer mode counter cleared by match signal Capture mode rising edges counter running OVF can occur Capture mode falling edges counter running OVF can occur 1 1 Capture mode rising and falling edges counter running OVF can occur 3 Timer 1 Counter Clear Bit ES No effect when write Clear T1 counter T1 CNT when write 2 Timer 1 Overflow Interrupt Enable Bit note EN Disable T1 overflow interrupt Enable T1 overflow interrupt 1 Timer 1 Match Capture Interrupt Enable Bit EN Disable T1 match capture interrupt Enable T1 match capture interrupt 0 Timer 1 Match Capture Interrupt Pending Flag Bit No T1 match capture interrupt pending when read Clear T1 match capture interrupt pending condition when write ing No effect when write T1 match capture interrupt is pending when read
249. rom 7 to 0 where bit 0 is the least significant right most bit Register Addressing To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data or 16 bit program memory or data memory addresses For detailed information about register addressing please refer to Section 2 Address Spaces Addressing Modes There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Section 3 Addressing Modes ELECTRONICS 6 1 INSTRUCTION SET S3F80JB Table 6 1 Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst src Load LDB dst src Load bit LDE dst src Load external data memory LDC dst src Load program memory LDED dst src Load external data memory and decrement LDCD dst src Load program memory and decrement LDEI dst src Load external data memory and increment LDCI dst src Load program memory and increment LDEPD dst src Load external data memory with pre decrement LDCPD dst src Load program memory with pre decrement LDEPI dst src Load external data memory with pre increment LDCPI dst src Load program memory with pre increment LDW dst src Load word POP dst Pop from stack POPUD dst src Pop user
250. rrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR register settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for S8C8 S3F8 series devices is always much smaller If an interrupt level has more than one vector address the vector priorities are set in hardware The SSF80JB uses eighteen vectors Two vector addresses are shared by four interrupt sources Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow for example Each vector can have several interrupt sources In the S3F80JB interrupt structure there are 24 possible interrupt sources When a service routine starts the respective pending bit is either cleared automatically by hardware or is must be cleared manually by program software The characteristics of the source s pending mechanism determine which method is used to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE S3F80JB INTERRUPT TYPES The three components of the S3C8 SSF8 series interrupt structure described above levels vectors and sources are combined to determine the interrupt s
251. rs R8 R15 Each register pointer points to one 8 byte slice of the register space selecting a total 16 byte working register block 00000XXX RPO Registers RO R7 Figure 2 6 8 Byte Working Register Areas Slices 2 10 ELECTRONICS S3F80JB ADDRESS SPACES USING THE REGISTER POINTERS Register pointers RPO and RP1 mapped to addresses D6H and D7H in set 1 are used to select two movable 8 byte working register slices in the register file After a reset they point to the working register common area RPO points to addresses COH C7H and points to addresses C8H CFH To change a register pointer value you load a new value to RPO and or RP1 using an SRP or LD instruction see Figures 2 6 and 2 7 With working register addressing you can only access those two 8 bit slices of the register file that are currently pointed to by RPO and RP1 You cannot however use the register pointers to select a working register space in set 2 COH FFH because these locations can be accessed only using the Indirect Register or Indexed addressing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline we recommend that RPO point to the lower slice and RP1 point to the upper slice see Figure 2 6 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 7 RPO points to the
252. rupt and the counter A borrow interrupt must be cleared by the interrupt service routine ELECTRONICS 5 15 INTERRUPT STRUCTURE S3F80JB INTERRUPT SOURCE POLLING SEQUENCE The BD OL gt dme interrupt request polling and servicing sequence is as follows A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that source The CPU checks the interrupt level of source The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request can be serviced the following conditions must be met If all Interrupt processing must be globally enabled El SYM 0 1 The interrupt level must be enabled IMR register unmask The interrupt level must have the highest priority if more than one level is currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register of the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates an interrupt machine cycle that completes the following processing sequence 1 2 3 4 Reset clear to 0 the interrupt enable bit in the SYM reg
253. ry the following events occur when Stop mode is released 1 During Stop mode a power on reset or an external interrupt occurs to trigger the Stop mode release and oscillation starts 2 If a power on reset occurred the basic timer counter will increase at the rate of fos 4096 If an external interrupt is used to release Stop mode the BTCNT value increases at the rate of the preset clock source Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows When a BTCNT 3 overflow occurs normal CPU operation resumes ELECTRONICS 10 3 BASIC TIMER and TIMER 0 S3F80JB TIMER 0 CONTROL REGISTER TOCON You use the timer 0 control register TOCON to Select the timer 0 operating mode interval timer capture mode or PWM mode Select the timer 0 input clock frequency Clear the timer 0 counter TOCNT Enable the timer 0 overflow interrupt or timer 0 match capture interrupt Clear timerO match capture interrupt pending conditions is located Set 1 at address D2H and is read write addressable using register addressing mode A reset clears to 00H This sets timer 0 to normal interval timer mode selects an input clock frequency of fOSC 4096 and disables all timer 0 interrupts You can clear the timer 0 counter at any time during normal operation by writing a 1 to TOCON 3 The timer 0 overflow interrupt TOOVF is interrupt le
254. s T2CON 0 1 When the interrupt request is acknowledged by the CPU and the service routine starts the interrupt service routine for vector F2H must clear the interrupt pending condition by writing a 0 to T2CON O T2CON 2 16 Bit Up Counter gt RQ3 T20VF Pending T2CON 0 IRQS T2INT P3 0 or P3 3 L Interrupt Enable Disable Timer 2 Data T2CON 5 T2CON 4 NOTE P3 0 is assigned as T2CAP function for 32 pin package and P3 3 is assigned as T2CAP function for 42 44 pin package Figure 13 1 Simplified Timer 2 Function Diagram Capture Mode 13 2 ELECTRONICS S3F80JB TIMER 2 TIMER 2 MATCH INTERRUPT Timer 2 can also be used to generate a match interrupt IRQ3 vector F2H whenever the 16 bit counter value matches the value that is written to the timer 2 reference data registers T2DATAH and T2DATAL When a match condition is detected by the 16 bit comparator the match interrupt is generated the counter value is cleared and up counting resumes from OOH In match mode program software can poll the timer 2 match capture interrupt pending bit T2CON O to detect when a timer 2 match interrupt pending condition exists T2CON 0 1 When the interrupt request is acknowledged by the CPU and the service routine starts the interrupt service routine for vector F2H must clear the interrupt pending condition by writing a 0 to T2CON O IRQ3 T2INT Pending T2CON 0
255. s from 1 7V to 3 6V If Frequency Selection Bits 3FH 6 2 are 11111 operating max frequency is from 1MHz to 8MHz and operating voltage range is from 1 95V to 3 6V ELECTRONICS S3F80JB ADDRESS SPACES REGISTER ARCHITECTURE In the S3F80JB implementation the upper 64 byte area of register files is expanded two 64 byte areas called set 1 and set 2 The upper 32 byte area of set 1 is further expanded two 32 byte register banks bank 0 and bank 1 and the lower 32 byte area is a single 32 byte common area In case of S3F80JB the total number of addressable 8 bit registers is 333 Of these 333 registers 22 bytes are for CPU and system control registers 39 bytes are for peripheral control and data registers 16 bytes are used as shared working registers and 272 registers are for general purpose use The extension of register space into separately addressable areas sets banks is supported by various addressing mode restrictions the select bank instructions SBO and SB1 Specific register types and the area occupied in the S3F80JB internal register space are summarized in Table 2 1 Table 2 1 The Summary of S3F80JB Register Type Register Type Number of Bytes General purpose registers including the 16 byte common 272 working register area the 64 byte set 2 area and 192 byte prime register area of page 0 CPU and system control registers 22 Mapped clock peripheral and I O control and data registers 39 bank 0 27 regis
256. se Set if the result is 0 cleared otherwise Setifthe result is negative cleared otherwise Setif arithmetic overflow occurred that is if the operands were of opposite sign and the sign of the result is the same as the sign of the source cleared otherwise Always set to 1 Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow lt 0 IU Bytes Cycles Opcode Addr Mode Hex dst src opc 2 4 32 6 33 r Ir opc src dst 3 6 34 R R 35 R IR opc dst src 3 6 36 R IM Given R1 10H R2 03H C 1 register 01H 20H register 02H 03H and register 03H OAH SBC R1 R2 SBC R1 R2 SBC 01H 02H SBC 01H 02H SBC 01H 8AH gt R1 OCH R2 03H R1 05H R2 register 03H OAH Register 01H 1CH register 02H 03H Register 01H 15H register 02H register OAH Register 01H 95H C S and V 1 gt gt gt In the first example if working register R1 contains the value 10H and register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in register R1 ELECTRONICS 6 77 INSTRUCTION SET S3F80JB SCF set Carry Flag SCF Operation Flags Format Example 6 78 C lt 1 The carry flag C is set to logic one regardless of its previous v
257. second set of values used in formats 9 and 10 are used to address data memory ELECTRONICS S3F80JB LDC LDE Load Memory LDC LDE Continued Examples Given RO 11H R1 0103H 4FH 0104H INSTRUCTION SET 34H R2 01H R3 04H Program memory locations 1A 0105H 6DH and 1104H 88H External data memory locations 0103H 5FH 0104H 2AH 0105H 7DH 1104H 98H LDC LDE LDC note LDE LDC LDE LDC note LDE LDC LDE LDC LDE LDC note LDE RO RR2 RO RR2 RR2 RO RR2 RO RO 01H RR2 RO 01H RR2 01H RR2 RO 01H RR2 RO RO 1000H RR2 RO 1000H RR2 R0 1104H 0 1104 1105 0 1105H RO B RO lt contents of program memory location 0104H RO 1AH R2 01H R3 04H RO lt contents of external data memory location 0104H RO 2AH R2 01H R3 04H 11H contents of RO is loaded into program memory location 0104H RR2 working registers RO R2 no change 11H contents of RO is loaded into external data memory location 0104H RR2 working registers RO R2 no change RO contents of program memory location 0105H 01H RR2 RO 6DH R2 01H R3 04H RO contents of external data memory location 0105H 01H RR2 RO 7DH R2 01H R3 04H 11H contents of RO is loaded into program memory location 0105H 01H 0104H 11H contents of RO is loaded into exter
258. sh User Stack Decrementing PUSHUD Operation Flags Format Example dst src IR IR 1 dst lt src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst sre opc dst src 3 8 82 IR R Given Register 00H register 01H 05H and register 02H PUSHUD 00H 01H gt Register OOH 02H register 01H 05H register 02H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUD 00H 01H decrements the user stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer ELECTRONICS 6 67 INSTRUCTION SET S3F80JB PUSHUI Push user Stack Incrementing PUSHUI Operation Flags Format Example 6 68 dst src IR lt IR 1 dst lt src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst sre opc dst src 3 8 83 IR R Given Register 00H register 01H 05H and re
259. signal is output of IPOR LVD Control Bit setting So that is one of two cases one is LVD enable in STOP mode the other is LVD disable in STOP mode 4 This signal is output relating to STOP mode If STOPCON has 0A5H and STOP instruction is executed that output signal makes S3F80JB enter STOP mode So that is one of two statuses one is STOP mode the other is not STOP mode 5 In SSF80JB one between LVD and IPOR is selected as reset source by IPOR LVD Control Bit setting value of smart option in the stop mode If the setting value is 0 LVD can be disabled by STOP instruction Instead of L VD IPOR is enabled If the setting value is 1 LVD is enabled regardless of executing STOP instruction and IPOR is disabled INTERNAL POWER ON RESET The power on reset circuit is built on the S3F80JB product During a power on reset the voltage at Vpp goes to high level and the schmitt trigger input of POR circuit is forced to low level and then to high level The power on reset circuit makes a reset signal whenever the power supply voltage is powering up and the schmitt trigger input senses the low level This on chip POR circuit consists of an internal resistor an internal capacitor and a schmitt trigger input transistor IPOR can be enabled by setting IPOR LVD control bit of smart option to 0 System Reset C J Schmitt Trigger Inverter Vss R 3000kQ On Chip Internal Resistor 340pF On Chip Internal Capacitor
260. sssonussscusseusseussausenseenseusssussusscussenseuseuns 18 2 18 2 D C Electrical Characteristics sassssssnsssnsssusasssaussusscunscunsaussaussessenseusseussausssusenseuusousssusses 18 2 18 3 Characteristics of Low Voltage Detect Circuit sassssssusssssssusasuscussascunscunscuuseussaussaueuseseuso 18 4 18 4 Data Retention Supply Voltage in Stop Mode sassasssnsssnssunsasussunsascunscusseussaussasssausenseunes 18 4 18 5 Input Output Capacitance ssasassanasasasuaananauausananasausausananauausananausanassenanauausanasasaussananananane 1 8 9 18 6 A C Electrical Characteristics sassssssssssssssusssussussssssusscusscusseussonsssscusssusscussessusseusscusseunes 18 9 18 7 Comparator Electrical Characteristics 18 1 1 18 8 Oscillation Characteristics ssssussuusssusassunesunscunssunsensusseusscussessseusenscusseunsausssusunseussesssaussos 18 1 1 18 9 Oscillation Stabilization Time sasssssansssnssssssasssassuseussaussesssusssussensssssusssusscussessesscunscunseunes 18 12 18 10 AC Electrical Characteristics for Internal Flash ROM emn 18 13 20 1 Components Consisting of S3F80JB Target Board sassasssasssssssusssusssussususascusscussenssousse 20 3 20 2 Default Setting of the Jumper S3F80JB Target Board m 20 4 xvi S3F80JB MICROCONTROLLER List of Programming Tips Description Page Number Chapter 2 Address Spaces Setting the Register POINtCES s enit c ede de edite edet 2 11 Using the RPs to Calculate the Sum of a Series of
261. ssssssssssssssssssssssssssssssssssssssss 17 6 17 4 Typical High Side Driver Source Characteristics P3 1 only mm 17 6 17 5 Typical High Side Driver Source Characteristics P3 0 and P2 0 2 3 7 17 7 17 6 Typical High Side Driver Source Characteristics Porto Porti P2 4 2 7 P3 4 P3 5 and Port4 sssssssssosssssssssssssssssssssssssssssssssssssssossssssns 17 7 17 7 Stop Mode Release Timing When Initiated by an External Interrupt 8 17 8 17 8 Stop Mode Release Timing When Initiated by a Reset 17 8 17 9 Stop Mode Release Timing When Initiated by a LVD ssssusssusssusasusaussssssssssussussucssuascnas 17 9 17 10 Input Timing for External Interrupts Port 0 and Port 2 m 17 10 17 1 1 Input Timing for Reset nRESET Pin sasssensnsssssssssssssssssusssusscususssusscusscunscusseusssssenseusees 1 7 1 0 17 12 Operating Voltage Range of S3F80J9 sssasassananasassananauansanaananasausananasanausanassnusanssananasanano 1 7 13 xii S3F80JB MICROCONTROLLER List of Figures Continued Figure Title Page Number Number 18 1 Typical Low Side Driver Sink Characteristics P3 1 only 18 5 18 2 Typical Low Side Driver Sink Characteristics P3 0 and 2 0 2 3 18 5 18 3 Typical Low Side Driver Sink Characteristics Porto Porti P2 4 2 7 P3 4 P3 5 and Port4 sssssssssossssssssssssssssssssssssssssssssssssssssssssssss 18 6 18 4 Typical High Side Driver Source Characteristics P3 1 only 18 6
262. st vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next 8 bit value to concatenate the full 16 bit address and the service routine is executed ELECTRONICS 5 3 INTERRUPT STRUCTURE S3F80JB Levels 8 Vectors 18 Sources 24 Reset Clear RESET 100H 1 Basic timer overflow H W FCH Timer 0 match capture S W FAH Timer 0 overflow H W IRQO Timer 1 match capture S W Timer 1 overflow H W IRQ2 Counter A H W Timer 2 match capture S W IRQ1 IRQ3 FOH Timer 2 overflow H W D6H P2 3 external interrupt S W D4H 2 2 external interrupt S W P2 1 external interrupt S W DOH P2 0 external interrupt S W P2 7 external interrupt S W P2 6 external interrupt S W P2 5 external interrupt S W P2 4 external interrupt S W P0 3 external interrupt S W PO 2 external interrupt S W P0 1 external interrupt S W 0 external interrupt S W PO 7 external interrupt S W PO 6 external in
263. stack decrementing POPUI dst src Pop user stack incrementing PUSH Src Push to stack PUSHUD dst src Push user stack decrementing PUSHUI dst src Push user stack incrementing 6 2 ELECTRONICS S3F80JB INSTRUCTION SET Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ELECTRONICS 6 3 INSTRUCTION SET S3F80JB Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jump relative on false BTJRT dst src Bit test and jump relative on true CALL dst Call procedure CPIJE dst src Compare increment and jump on equal CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compar
264. ster addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations COH FFH is logically duplicated to add another 64 bytes of register space This expanded area of the register file is called set 2 The set 2 locations COH FFH is accessible on page 0 in the S3F80UB register space The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions You can use only Register addressing mode to access set 1 locations to access registers in set 2 you must use Register Indirect addressing mode or Indexed addressing mode The set 2 register area is commonly used for stack operations 2 8 ELECTRONICS S3F80JB ADDRESS SPACES PRIME REGISTER SPACE The lower 192 bytes of the 256 byte physical internal register file OOH BFH are called the prime register space or more simply the prime area You can access registers in this address using any addressing mode In other words there is no addressing mode restriction for these registers as is the case for set 1 and set 2 registers The prime register area on page 0 is immediately addressable following a reset Bank 1 CPU and system control Prime Register Area Figure 2 5 Set 1 Set 2 and Prime Area Register Map ELECTRONICS 2
265. t option bit 7 03FH IPOR LVD Contorl Bit 1 smart option bit 7 03FH STOP RESET El external interrupt enable smart option bit 7 03FH IPOR LVD Contorl Bit 1 smart option bit 7 O03FH IPOR LVD Contorl Bit 1 Figure 8 1 RESET Sources of The S3F80JB 1 When IPOR LVD Control Bit of smart option is set to 1 the rising edge detection of LVD circuit while rising of VDD passes the level of VL VD 2 When IPOR LVD Control Bit of smart option is set to 0 and mode is in STOP Mode reset is generated by internal power on reset 3 Basic Timer over flow for watchdog timer See the chapter 11 Basic Timer and Timer 0 for more understanding 4 The reset pulse generation by transiting of reset pin nRESET from low level to high level on the condition that VDD is higher level state than VLVD Low level Detect Voltage 5 When IPOR LVD Control Bit smart option bit 7 is set to 0 and chip is in stop mode external interrupt input by PO and P2 regardless of external interrupt enable disable generates the reset signal 8 2 ELECTRONICS S3F80JB RESET Falling Edge Detector Back up Mode Enable Disable IPOR LVD Control Bit 1 smart option bit 7 Rising Edge Detector Disable Enable BT fosc WDT Noise Reset Pulse gt Generator IPOR LVD Control Bit 1 smart option bit 7 0 RE
266. t use these in user mode MODE Selection JP1 JP2 Selection of Flash tool user mode and Eva Main chip mode ELECTRONICS DEVELOPMENT TOOLS DATA S3F80JB Table 20 2 Default Setting of the Jumper S3F80JB Target Board JP Description 1 2 connection 2 3 connection Setting 1 Target board power source Open ice power Join 1 2 JP1 Target board mode selection H Main Mode L EVA Mode Join 2 3 JP2 Operation Mode H User Mode L Test Mode Join 1 2 JP3 MDS version SMDS2 SMDS2 Join 2 3 JP5 Board peripheral power Board peripheral power connection Connect connection JP6 When supplied 5V in target In case of selection 3 3V In case of selection 5V Join 2 3 board generation of 3 3V between open ice powers between open ice powers using regulator connect core without a step connect regulator to of regulation generate 3 3V JP8 80JB Vpp power connection 80JB Vpp power connection Connect JP10 Clock source selection When using the internal clock source which is generated from OPENice i500 join connector 2 3 and 4 5 pin If user wants to use the external clock source like a crystal user should change the jumper setting from 1 2 to 5 6 and connect Y1 to an external clock source JP11 Regulator 3 3 Volt Out Connection between regulator out voltage and 80JB s connection Power Vpp when using the regulator When debugging with Openice i500 JP11 don t need to be c
267. ter ceased tee edid dede dete deed 4 11 FMCON Flash Memory Control eene 4 12 FMSECH Flash Memory Sector Address Register High Byte 4 13 FMSECL Flash Memory Sector Address Register Low Byte 4 13 FMUSR Flash Memory User Programming Enable 4 13 IMR Interrupt Mask Reglster en n eec ERR 4 14 IPH Instruction Pointer High Byte enne 4 15 IPL Instruction Pointer Low Byte 4 15 IPR Interrupt Priority 4 16 LVDCON LVD Control Register ee ee e De e d mete 4 18 POCONL Port 0 Control Register Low Byte 4 20 POINT Port 0 External Interrupt Enable 4 21 POPND Port 0 External Interrupt Pending Register esee 4 22 POPUR Port 0 Pull up Resistor Enable Register 4 23 P1CONH Port 1 Control Register High 4 24 P1CONL Port 1 Control Register Low 4 25 P2CONH Port 2 Control Register High 4 26 P2CONL Port 2 Control Register Low Byte ene 4 27 P2INT Port 2 External Interrupt Enable
268. ter 00 01H and register 01 20H JP C LABEL W LABEL W 1000H PC 1000H JP 00H gt PC 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement JP C LABEL_W replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement JP 00 replaces the contents of the PC with the contents of the register pair OOH and 01H leaving the value 0120H ELECTRONICS 6 47 INSTRUCTION SET S3F80JB JR Jump Relative JR Operation Flags Format Example 6 48 cc dst If cc is true lt PC dst If the condition specified by the condition code cc is true the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See list of condition codes The range of the relative address is 127 128 and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement No flags are affected Bytes Cycles Opcode Addr Mode Hex dst dst 2 6 ccB RA cc 0 to F NOTE Inthe first byte of the two byte instruction format the condition code and the opcode are
269. terrupt S W PO 5 external interrupt S W P0 4 external interrupt S W Figure 5 2 S3F80JB Interrupt Structure NOTE Reset interrupt vector address Basic timer overflow can be varied by smart option 5 4 ELECTRONICS S3F80JB INTERRUPT STRUCTURE INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the SSF80JB interrupt structure are stored in the vector address area of the internal program memory ROM 00H FFH See Figure 5 3 You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H Reset address can be changed by smart option Refer to Table 15 3 or Figure 2 2 Decimal 65 536 64 Kbyte Internal Program Memory Flash Memory 01FFH 02FFH 04FFH or 8 00FFH 003FH 003CH 0000H Figure 5 3 ROM Vector Address Area ELECTRONICS 5 5 INTERRUPT STRUCTURE S3F80JB Table 5 1 S3F80JB Interrupt Vectors Vector Address Interrupt Source Request Reset Clear Value Value Level Level 7 28 _ BasictimeroverfowPor Reser 5 259 TimerOmatchicape mo 3 v mo FM J o CY FH Tmerrmachesur 1 24 FM 9 me to joweA m v me Fe
270. ters bank 1 12 registers Total Addressable Bytes 333 ELECTRONICS 2 5 S3F80JB Bank 0 System and Peripheral Control Register Register Addressing Mode System Register Register Addressing Mode Working Register Working Register Addressing only General Purpose Data Register Indirect Register or Indexed Addressing Modes or Stack Operations Prime Data Register All Addressing Mode ADDRESS SPACES Figure 2 3 Internal Register File Organization 2 6 ELECTRONICS S3F80JB ADDRESS SPACES REGISTER PAGE POINTER PP The S3C8 S3F8 series architecture supports the logical expansion of the physical 333 byte internal register files using an 8 bit data bus into as many as 16 separately addressable register pages Page addressing is controlled by the register page pointer PP DFH Set 1 In the SSF80JB microcontroller a paged register file expansion is not implemented and the register page pointer settings therefore always point to page 0 Following a reset the page pointer s source value lower nibble and destination value upper nibble are always 0000 automatically Therefore S3F80JB is always selected page 0 as the source and destination page for register addressing These page pointer PP register settings as shown in Figure 2 4 should not be modified during normal operation Register Page Pointer PP DFH Set 1 R W Destinat
271. therwise Bytes Cycles Opcode Addr Mode Hex dst src 6 13 r Ir opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Given R1 10H R2 C flag 1 register 01H 20H register 02H and register 03H OAH ADC R1 R2 gt R1 14H R2 03H ADC R1 R2 gt 1 1BH R2 03H ADC 01H 02H gt Register 01H 24H register 02H 03H ADC 01H 02H gt Register 01H 2BH register 02H ADC 01H 11H gt Register 01H 32H In the first example destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value The statement ADC R1 R2 adds 03H and the carry flag value 1 to the destination value 10H leaving 14H in register R1 ELECTRONICS S3F80JB ADD ADD dst src Operation dst lt dst src INSTRUCTION SET The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed Flags C Set if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to 0 Set if a carry from the low order nibble occur
272. tically set to 0000B following a hardware reset These values should not be changed curing normal operation ELECTRONICS 4 37 CONTROL REGISTERS S3F80JB RPO Register Pointer 0 D6H Seti BankO Bit Identifier 8 4 3 2 1 o Reset Value 1 1 0 0 0 Read Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 248 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RPO points to address in register set 1 bankO selecting the 8 byte working register slice COH C7H 2 0 Not used for SSF80JB RP1 Register Pointer 1 D7H Seti Reset Value 1 1 0 0 1 Read Write R W R W R W R W R W Addressing Mode Register addressing mode only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 248 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset points to address in register set 1 selecting the 8 byte working register slice Not used for S3F80JB N 4 38 ELECTRONICS S3F80JB CONTROL REGISTERS SPL st
273. tomatically just after erase operation Not used for S3F80JB Figure 15 3 Flash Memory Control Register FMCON The bit 0 of FMCON register 0 is a bit for the operation start of Erase and Hard Lock Protection Therefore operation of Erase and Hard Lock Protection is activated when you set FMCON O to 1 If you write FMCON O to 1 for erasing CPU is stopped automatically for erasing time min 10ms After erasing time CPU is restarted automatically When you read or program a byte data from or into flash memory this bit is not needed to manipulate FLASH MEMORY USER PROGRAMMING ENABLE REGISTER FMUSR The FMUSR register is used for a safe operation of the flash memory This register will protect undesired erase or program operation from malfunctioning of CPU caused by an electrical noise After reset the user programming mode is disabled because the value of FMUSR is 00000000B by reset operation If necessary to operate the flash memory can use the user programming mode by setting the value of FMUSR to 10100101B The other value of 10100101B user program mode is disabled Flash Memory User Programming Enable Register FMUSR Set Bank 1 R W Flash Memory User Programming Enable Bits 10100101 Enable user programming mode Other values Disable user programming mode Figure 15 4 Flash Memory User Programming Enable Register FMUSR 15 6 ELECTRONICS S3F80JB EMBEDDED FLASH M
274. tor You can select one of the following clock sources as the Timer 1 clock Oscillator frequency divided by 4 8 or 16 Internal clock input from the counter A module counter A flip flop output You can use Timer 1 in three ways As anormal free run counter generating a Timer 1 overflow interrupt IRQ1 vector at programmed time intervals generate a Timer 1 match interrupt IRQ1 vector F6H when the 16 bit Timer 1 count value matches the 16 bit value written to the reference data registers generate a Timer 1 capture interrupt IRQ1 vector F6H when a triggering condition exists at the P3 2 pin for 44 package at the P3 0 for 32 package You can select a rising edge a falling edge or both edges as the trigger In the S3F80JB interrupt structure the Timer 1 overflow interrupt has higher priority than the Timer 1 match or capture interrupt NOTE The CPU clock should be faster than timer 1 clock ELECTRONICS 11 1 TIMER 1 53 80 TIMER 1 OVERFLOW INTERRUPT Timer 1 can be programmed to generate an overflow interrupt IRQ1 F4H whenever an overflow occurs in the 16 bit up counter When you set the Timer 1 overflow interrupt enable bit T1CON 2 to 1 the overflow interrupt is generated each time the 16 bit up counter reaches FFFFH After the interrupt request is generated the counter value is automatically cleared to OOH and up counting resumes By writing a
275. tor address pointer value is the higher eight bits of the 16 bit pointer address FMSECL Flash Memory Sector Address Register Low Byte EDH Set1 Bank1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory Sector Address Low Byte Note The low byte flash memory sector address pointer value is the lower eight bits of the 16 bit pointer address FMUSR Flash Memory User Programming Enable Register Seti Bank1 Bit Identifier 6 5 4 3 2 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory User Programming Enable Bits 1 0 1 0 0 1 0 1 Enable user programming mode Other values Disable user programming mode NOTES 1 To enable flash memory user programming write 10100101B to FMUSR 2 To disable flash memory operation write other value except 10100101B into FMUSR ELECTRONICS 4 13 CONTROL REGISTERS S3F80JB IMR Interrupt Mask Register DDH Seti BankO Reset Value X X X X X x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Enable Bit External Interrupts 0 7 0 4 Disable mask Enable un mask 6 Interrupt Level 6 IRQ6 Enable Bit External Interrupts 0 3 0 0 0 Disable mask 1 Enable un mask 5 Interrupt Level 5 IRQ5 E
276. truction in user program mode ISP RESET VECTOR AND ISP SECTOR SIZE If you use ISP sectors by setting the ISP enable disable bit to O and the reset vector selection bit to O at the smart option you can choose the reset vector address of CPU as shown in Table 15 3 by setting the ISP reset vector address selection bits Refer to Figure 2 2 Smart Option Table 15 3 Reset Vector Address Smart Option 003EH Reset Vector Usable Area for ISP Sector Size ISP Reset Vector Address Selection Bit Address after POR ISP Sector 256 Bytes 512 Bytes 1024 Bytes 2048 Bytes NOTE The selection of the ISP reset vector address by Smart Option 003EH 7 003EH 5 is not dependent of the selection of ISP sector size by Smart Option 003EH 2 003EH 0 ELECTRONICS 15 5 EMBEDDED FLASH MEMORY INTERFACE S3F80JB FLASH MEMORY CONTROL REGISTERS USER PROGRAM MODE FLASH MEMORY CONTROL REGISTER FMCON FMCON register is available only in user program mode to select the flash memory operation mode sector erase byte programming and to make the flash memory into a hard lock protection Flash Memory Control Register FMCON Bank1 R W Flash Erase or Hard Lock Protection Flash Memory Mode Selection Bits 0101 Programming mode Operation Stant Bit 1010 Erase mode 0 Operation stop 0110 Hard lock mode 1 Operation start others Not used for S3F80JB This bit will be cleared au
277. tructure of an individual device and to make full use of its available interrupt logic There are three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt Sources assigned to each level See Figure 5 1 Type 1 One level IRQn one vector V4 one source S1 Type 2 One level IRQn one vector V4 multiple sources S1 Sn Type 3 One level IRQn multiple vectors V4 Vn multiple sources S1 Sn 1 Snim In the S8F80JBmicrocontroller all three interrupt types are implemented Levels Vectors Sources Type 1 IRQn _ 81 51 2 IRQn _ S2 5 5 51 3 IROn 82 NOTE The number of Sn and Vn value is expandable Figure 5 1 S3C8 S3F8 Series Interrupt Types 5 2 ELECTRONICS S3F80JB INTERRUPT STRUCTURE The S3F80JB microcontroller supports twenty four interrupt sources Sixteen of the interrupt sources have a corresponding interrupt vector address the remaining eight interrupt sources share by two vector address Eight interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowe
278. ts of the PC and the FLAGS registers are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address value is always decreased by one before a push operation and increased by one after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 15 High Address PCL PCH Flags Stack contents Stack contents after a call after an instruction interrupt Low Address Figure 2 16 Stack Operations User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL Register location D9H contains the 8 bit stack pointer SPL that is used for system stack operations After a reset the SPL value is undetermined Because only internal memory 256 byte is implemented in The S3F80JB the SPL must be initialized to an 8 bit value in the range 00 FFH 2 20 ELECTRONICS S3F80JB ADDRESS SPACES PROGRAMMING TIP Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD PUSH PUSH PUSH PUSH POP POP POP POP ELECTRONICS SPL ZOFFH PP RPO RP1 R3 R3 RP1 RPO SPL lt FFH Normally the SPL is set to OFFH by th
279. ue 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Watchdog Timer Function Enable Bits for System Reset Disable watchdog timer function Any other value Enable watchdog timer function 3 and 2 Basic Timer Input Clock Selection Bits 4 Basic Timer Counter Clear Bit 1 No effect Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer and Timer 0 2 No effect Clear both block frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to OOH Immediately following the write operation the BTCON 1 value is automatically cleared to O 2 When you write 1 to BTCON O the corresponding frequency divider is cleared to O0H Immediately following the write operation the BTCON O value is automatically cleared to 0 ELECTRONICS 4 CONTROL REGISTERS S3F80JB CACON counter A Control Register F3H Seti BankO Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 and 6 5 and 4 4 6 Register addressing mode only Counter A Input Clock Selection Bits Counter A Interrupt Timing Selection Bits fo fo Elapsed time for Low data value Elapsed time for High data value Elapsed time for combined Low and High data values Not used for S3F80JB Counter A Interrupt Enabl
280. value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 TE Example The diagram below shows one example of how to use an ENTER statement Before After Address Address Data IP 0043 Address Address Data PC 40 Enter 0110 40 Enter 1F 41 Address 41 Address H 01 42 Address L 42 AddressL 10 sp 43 Address SP 0020 43 Address 20 IPH 00 110 Routine 21 IPL 50 22 Data 22 Data Memory Stack Stack ELECTRONICS 6 41 INSTRUCTION SET S3F80JB EXIT exit EXIT Operation IP lt SP SP lt SP 2 lt IP IP IP 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 internal stack 2F 16 internal stack Example The diagram below shows one example of how to use an EXIT statement Before After Address Data Address Data IP PC SP 20 21 22 6 42 0052 Address Data Address Data PC 0060 50 60 Main 51 SP 0022 140 IPH
281. vel IRQO and has the vector address FAH When a timerO overflow interrupt occurs and is serviced by the CPU the pending condition is cleared automatically by hardware To enable the timer 0 mach capture interrupt IRQO vector FCH you must write TOCON 1 to 1 To detect a match capture interrupt pending condition the application program polls 0 When a 1 is detected timerO match or capture interrupt is pending When the interrupt request has been serviced the pending condition must be cleared by software by writing a 0 to the timerO interrupt pending bit 0 10 4 ELECTRONICS S3F80JB BASIC TIMER and TIMER 0 Timer 0 Control Register TOCON D2H Set 1 R W Timer 0 Interrupt Pending Bit 0 No interrupt pending Timer 0 Input Clock Selection Bits 0 Clear pending bit when write 00 fosc 4096 1 Interrupt is pending 01 fosc 256 10 fosc 8 11 External clock NOTE Timer 0 Interrupt Match capture Enable Bit 0 Disable interrupt 1 Enable interrupt Timer 0 Overflow Interrupt Enable Bit 0 Disable overflow interrupt 1 Enable overflow interrupt Timer 0 Counter Clear Bit 0 No effect 1 Clear the timer 0 counter when write Timer 0 Operating Mode Selection Bits 00 Interval mode 01 Capture mode capture on rising edge counter running OVF can occur 10 Capture mode capture on falling edge counter running OVF can occur 11 PWM mo
282. ven R4 06H R5 1CH R6 05H R7 02H register 00H 1AH register 01H 02H register 02H and register 03H OFH LDW RR6 RR4 R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H gt Register OOH 03H register 01H OFH register 02H register OFH LDW RR2 R7 R2 03H R3 OFH LDW 04H 01H gt Register 04H 03H register 05H LDW RR6 1234H R6 12H R7 34H LDW 02H 0FEDH gt Register 02H OFH register 03H OEDH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H 03H into the destination word OOH 01H This leaves the value 03H in general register OOH and the value OFH in register 01H The other examples show how to use the LDW instruction with various addressing modes and formats ELECTRONICS S3F80JB INSTRUCTION SET MULT MULT Operation Flags Format Examples Multiply Unsigned dst src dst lt dst x src The 8 bit destination operand even register of the register pair is multiplied by the source operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are treated as unsigned integers C Setifresultis 255 cleared otherwise Z Setif the result is 0 cleared otherwise S Set if MSB of the result is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Bytes Cycles Opcode Addr
283. very Dates and Quantities Deliverable Required Delivery Date Comments ROM code Not applicable See ROM Selection Form Omwmesm Risk order See Risk Order Sheet Please answer the following questions For what kind of product will you be using this order New product Upgrade of an existing product Replacement of an existing product Other If you are replacing an existing product please indicate the former product name What are the main reasons you decided to use a Samsung microcontroller in your product Please check all that apply Price Product quality Features and functions Development system Technical support Delivery on time Used same micom before Quality of documentation Samsung reputation Mask Charge US Won Customer Information Company Name Telephone number Signatures Person placing the order Technical Manager For duplicate copies of this form and for additional ordering information please contact your local Samsung sales representative Samsung sales offices are listed on the back cover of this book S3F8 SERIES REQUEST FOR PRODUCTION AT CUSTOMER RISK Customer Information Company Name Department Telephone Number Fax Date Risk Order Information Device Number S3F8 write down the ROM code number Package Number of Pins Package Type
284. w in the PC otherwise the instruction following the BTJRT instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA NOTE n the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 000001 11B the statement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONICS S3F80JB INSTRUCTION SET BXOR Bit xor BXOR BXOR Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 src b or dst b lt dst b XOR src 0 The specified bit of the source or the destination is logically exclusive ORed with bit zero LSB of the destination or source The result bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Setifthe result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc src 3 6 27 ro Rb opc seibit dst 3 6 27 R
285. when read NOTE Toclear an interrupt pending condition write a 0 to the appropriate pending flag bit Writing a 1 to an interrupt rending flag 2 0 7 has no effect ELECTRONICS 4 29 CONTROL REGISTERS S3F80JB P2PUR Port 2 Pull up Resistor Enable Register Seti BankO Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 2 7 Pull up Resistor Enable Bit Disable pull up resistor Enable pull up resistor 6 P2 6 Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 5 P2 5 Pull up Resistor Enable Bit Disable pull up resistor Enable pull up resistor 4 P2 4 Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 3 P2 3 Pull up Resistor Enable Bit 0 Disable pull up resistor Enable pull up resistor 2 P2 2 Pull up Resistor Enable Bit Disable pull up resistor Enable pull up resistor 4 P2 1 Pull up Resistor Enable Bit O Disable pull up resistor 1 Enable pull up resistor 0 P2 0 Pull up Resistor Enable Bit Disable pull up resistor Enable pull up resistor 4 30 ELECTRONICS S3F80JB CONTROL REGISTERS P3CON Port 3 Control Register EFH Seti BankO Bit Identifier Reset Value Read Write Addressing Mode 7 and 6 and 3 1 and 0 ELECTRONICS 7 6 s j 4 3 2 4 j 9 0 0 0 0 0 0 0 0 R W R W R
286. xists at the P3 2 pin for 44 package at the P3 0 for 32 package You can select a rising edge a falling edge or both edges as the trigger In the S3F80JB interrupt structure the timer 2 overflow interrupt has higher priority than the timer 2 match or capture interrupt NOTE The CPU clock should be faster than timer 2 clock ELECTRONICS 13 1 TIMER 2 53 80 TIMER 2 OVERFLOW INTERRUPT Timer 2 can be programmed to generate an overflow interrupt IRQ3 FOH whenever an overflow occurs in the 16 bit up counter When you set the timer 2 overflow interrupt enable bit T2CON 2 to 1 the overflow interrupt is generated each time the 16 bit up counter reaches FFFFH After the interrupt request is generated the counter value is automatically cleared to OOH and up counting resumes By writing a 1 to T2CON 3 you can clear reset the 16 bit counter value at any time during program operation TIMER 2 CAPTURE INTERRUPT Timer 2 can be used to generate a capture interrupt IRQ3 vector F2H whenever a triggering condition is detected at the P3 0 pin for 32 pin package and P3 3 pin for 44 pin package The T2CON 5 and T2CON 4 bit pair Setting is used to select the trigger condition for capture mode operation rising edges falling edges or both signal edges In capture mode program software can poll the timer 2 match capture interrupt pending bit T2CON O to detect when a timer 2 capture interrupt pending condition exist
287. xperts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics objectives Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM24653 All semiconductor products are designed and manufactured in accordance with the highest quality standards and Samsung Electronics Co Ltd
288. y other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITR o Ri 05H If the value of working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101B ELECTRONICS S3F80JB INSTRUCTION SET BITS Bit Set BITS Operation Flags Format Example dst b dst b 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE n the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BITS R13 gt R1 OFH If working register R1 contains the value 07H 000001 11B the statement BITS R1 3 sets bit three of the destination register R1 to 1 leaving the value OFH 00001 111B ELECTRONICS 6 21 INSTRUCTION SET S3F80JB BOR sit or BOR BOR Operation Flags Format Examples 6 22 dst src b dst b src dst 0 lt dst 0 OR src b or dst b lt dst b OR 0 The specified bit of the source or t

Samsung S3F80JB User's Manual

Contents

Download Pdf Manuals

Related Search

Related Contents