Renesas REJ06B0732-0100 User's Manual
Contents
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4. RENESAS ___aruicarion nore SH7211 Group Data Transfer between On chip RAM Areas with DMAC Cycle Stealing Mode Introduction This application note describes the operation of the DMAC and is intended for reference to help in the design of user software Target Device SH7211 Contents Vi MAO GUCHON Enea E E EE E E cactus bos ecudupcasadhwaxdh venusbde EE E vestuntanccseadeecdSsaasscadetaaohebcuievdatenec 2 2 Description of Sample Application ccccccccececeee cesses eeeeeeceaeeeeeaeeseneeeseaeeesaaesseaeeseeeeessaeeseaeeseaeeees 3 3 Documents of Reference cic cece cece ccccceceeeeececeseeeceaueeseseseeueuauaueseeeeseeaeauaedseseeeueeauensedeeeeneeananees 11 REJ06B0732 0100 Rev 1 00 March 2008 Page 1 of 13 i 2 SH7211 Group a E N ESAS Data Transfer between On chip RAM Areas with DMAC Cycle Stealing Mode 1 Introduction 1 1 Specification e DMAC channel 0 is used e Auto request mode is used as the interrupt source for activating DMA transfer e Cycle stealing mode is used as the bus mode 1 2 Used Module e Direct memory access controller DMAC channel 0 1 3 Applicable Conditions e Microcontroller SH7211 e Operating Frequency Internal clock 160 MHz Bus clock 40 MHz Peripheral clock 40 MHz e C Compiler SuperH RISC engine family C C compiler package Ver 9 01 from Renesas Technology REJ06B0732 0100 Rev 1 00 March 2008 Page 2 of 13 SH7211 Group H lt N ESAS Data Transfer between On
5. a certain rate and malfunctions under certain use conditions Please be sure to implement safety measures to guard against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other applicable measures Among others since the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you 11 In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed the risk of accident such as swallowing by infants and small children is very high You should implement safety measures so that Renesas products may not be easily detached from your products Renesas shall have no liability for damages arising out of such detachment 12 This document may not be reproduced or duplicated in any form in whole or in part without prior written approval from Renesas 13 Please contact a Renesas sales office if you have any questions regarding the information contained in this document Renesas semiconductor products or if you have any other inquiries 2008 Renesas Technology Corp All rights reserved REJ06B0732 0100 Rev 1 00 March 2008 Page 13 of 13
6. al module request and auto request SCIF 8 sources IIC3 two sources A D converter one source MTU2 five sources CMT two sources Bus mode Cycle stealing mode normal mode and intermittent mode and burst mode Priority level Channel priority fixed mode and round robin mode Interrupt request An interrupt request to the CPU is made when half or all of a transfer process is completed External request detection DREQ input low high level detection rising falling edge detection Transfer request acknowledge signal transfer end signal Active levels for DACK and TEND can be set independently REJ06B0732 0100 Rev 1 00 March 2008 Page 3 of 13 SH7211 Group L zE N ESAS Data Transfer between On chip RAM Areas with DMAC Cycle Stealing Mode In the normal mode of cycle stealing bus mastership is given to another bus master after each DMA transfer of one transfer unit byte word longword or 16 byte unit When a subsequent transfer request occurs bus mastership is obtained from the other bus master and transfer proceeds for one transfer unit When that transfer ends the bus mastership is passed to another bus master This is repeated until the transfer end condition is satisfied The cycle stealing normal mode can be used in transfer across any interval regardless of the requesting source source and destination of the transfer DREQ a Bus mastership returned to CPU once rA Bus cycle R
7. chip RAM Areas with DMAC Cycle Stealing Mode 2 Description of Sample Application In this sample application the direct memory access controller DMAC is set to auto request mode to transfer 512 Kbtyte data stored in the on chip RAM to another address 2 1 Operation of Modules Used When a DMA transfer request is made the DMAC starts to transfer data in accordance with the priority order of channels and continues the transfer operation until the transfer end condition is met Transfer requests for the DMAC are of three kinds auto requests external requests and on chip peripheral module requests The bus mode is selectable as burst mode or cycle stealing mode For details on the DMAC refer to the section on the direct memory access controller in the SH7211 Group Hardware Manual An overview of the DMAC is given in table 1 Examples of DMA transfer in cycle stealing mode and burst mode are shown in figures 1 and 2 respectively In addition a block diagram of the DMAC is shown in figure 3 Table 1 Overview of DMAC Item Number of channels Description 8 CHO to CH7 Only 4 CHO to CH3 can receive external requests Address space 4 Gbytes Length of transfer data Byte word 2 bytes longword 4 bytes and 16 bytes longword x 4 Maximum transfer count 16 777 216 24 bits transfers Address mode Single address mode and dual address mode Transfer request External request on chip peripher
8. ead Write Read Write Figure 1 DMA Transfer Example in Cycle Stealing Normal Mode Dual Address DREQ Low Level Detection In burst mode once the DMAC has obtained bus mastership it continues to perform transfer without releasing the bus until the transfer end condition is satisfied In external mode however when the DREQ signal is being level detected and changes to the non active level even if the tranfer end condition has not been satisfied bus mastership is passed to another bus master on completion of the DMA transfer request for which the request has already been accepted DREQ ny Bus cycle Read Write Read Write Figure 2 DMA Transfer Example in Burst Mode Dual Address DREQ Low Level Detection REJ06B0732 0100 Rev 1 00 March 2008 Page 4 of 13 i l SH7211 Group L E N ESAS Data Transfer between On chip RAM Areas with DMAC Cycle Stealing Mode DMAC module m RDMATCR_n Iteration y control p DMATCR_n o gt RSAR_n Do E o gt SAR_n On chip peripheral module Register control o gt RDAR_n y e gt DAR_n Internal bus Start up control Peripheral bus DMA transfer request signal CHCR_n DMA transfer acknowledge signal Request o gt HEln priority DMAOR Interrupt controller DEIn control e gt DMARSO to DMARS3 Exte
9. fer DE B 1 enables DMA transfer H 8000 4410 When disabling DMA transfer DE B 0 disables DMA transfer DMA operation register H FFFE1200 H 0000 0001 DME B 1 enables DMA transfer on all the DMAOR channels REJ06B0732 0100 Rev 1 00 March 2008 Page 10 of 13 i gt d SH7211 Group L E N ESAS Data Transfer between On chip RAM Areas with DMAC Cycle Stealing Mode 3 Documents for Reference e Software Manual SH 2A SH2A FPU Software Manual The most up to date version of this document is available on the Renesas Technology Website e Hardware Manual SH7211 Group Hardware Manual The most up to date version of this document is available on the Renesas Technology Website REJ06B0732 0100 Rev 1 00 March 2008 Page 11 of 13 gt d SH7211 Group a E N ESAS Data Transfer between On chip RAM Areas with DMAC Cycle Stealing Mode Website and Support Renesas Technology Website http www renesas com Inquiries http www renesas com inquiry csc renesas com Revision Record Description Rev Date Page Summary 1 00 Mar 21 08 First edition issued All trademarks and registered trademarks are the property of their respective owners REJ06B0732 0100 Rev 1 00 March 2008 Page 12 of 13 l SH7211 Group L E N ESAS Data Transfer between On chip RAM Areas with DMAC Cycle Stealing Mode Notes regarding these materials 1 This document is provided for reference purposes only so
10. he channel control register CHCR_0 Set TC to B 1 transfer data for the count specified in DMATCR Set RLD to B 0 disable the reload function Set RSJ 3 0 resource selector to B 0100 auto request Set DM 1 0 to B 01 increment the destination address Set SM 1 0 to B 00 fix the source address Set TB to B 0 cycle steal mode Set IE to B 0 disable interrupts Set the DMA operation register DMAOR Read from the AE and MNIF bits and clear them to 0 Clear the address error flag Set the DME bit to 1 after clearing the flags Enable DMA transfer on all the channels Figure 6 Flowchart of Initializing DMAC REJ06B0732 0100 Rev 1 00 March 2008 Page 8 of 13 i 2 SH7211 Group a E N ESAS Data Transfer between On chip RAM Areas with DMAC Cycle Stealing Mode 2 4 Register Settings for Sample Program 2 4 1 Clock Pulse Generator CPG The settings of the clock pulse generator for the sample program are described in table 5 Table 5 Settings of Clock Pulse Generator Register Name Address Setting Value Description Frequency control H FFFE0010 H 1303 CKOEN B 1 output clocks register FRQCR STC 1 0 B 00 frequency multiplication ratio of PLL circuit x 1 IFC 2 0 B 000 internal clock x 1 PFC 2 0 B 011 peripheral clock x 1 4 2 4 2 Standby Control Register The settings of the standby control register for the sample program are described in table 6 Table 6 Sett
11. ings of Standby Control Register Register Name Address Setting Value Description Standby control H FFFE0018 H 00 MSTP8 B 0 the DMAC operates register 2 STBCR2 REJ06B0732 0100 Rev 1 00 March 2008 Page 9 of 13 2CENESAS 2 4 3 Direct Memory Access Controller DMAC SH7211 Group Data Transfer between On chip RAM Areas with DMAC Cycle Stealing Mode The settings of DMAC registers for the sample program are described in table 7 Table 7 Settings of DMAC Registers Register Name Address Setting Value Description DMA source address H FFFE1000 WH FFF81000 Transfer source start address register 0 SAR DMA destination address H FFFE1004 WH FFF82000 Transfer destination start address register 0 DAR DMA transfer count H FFFE1008 D 128 DMA transfer count register 0 DMATCR 128 transfers DMA channel control H FFFE100C H 0000 0000 Before DMA initialization register 0 CHCR DE B 0 disables DMA transfer H 8000 4410 DMA initialization TC B 1 transfers data for the count specified in DMATCR for each transfer request DM 1 0 B 01 increments the destination address SM 1 0 B 00 fixes the source address RS 3 0 B 0100 auto request TB B 0 cycle stealing mode TS 1 0 B 10 longword 4 bytes unit IE B 0 disables interrupt requests DE B 0 disables DMA transfer H 8000 4411 When enabling DMA trans
12. nnel 0 512 byte Initialization 3 Initialize the transfer destination 2 completed 3 Clear a 512 byte area to 0 4 Enable DMA transfer DMACO CHCR BIT DE 1 4 M Set DMA enable flag S No HARSI St OMI 5 Perform DMA transfer end processing gt 5 Disable DMA transfer after confirmation of the tranfer end DMACO CHCR BIT DE 0 In this sample application sleep processing is performed after the main routine is complete Figure 5 Flowchart of Sample Program REJ06B0732 0100 Rev 1 00 March 2008 Page 7 of 13 2 CENESAS SH7211 Group Data Transfer between On chip RAM Areas with DMAC Cycle Stealing Mode DMAC_init Set DMA channel control register CHCR_0O 1 Set DMA source SAR_0 address register 2 y Set DMA destination address register DAR_0 3 Set DMA transfer count register 4 DMATCR_0 Set DMA channel control register 5 CHCR_0 Set DMA operation register 6 DMAOR END 1 2 3 4 5 6 Disable DMA transfer Set the DE DMA enable bit to 0 Disable DMA transfer Set the DMA transfer source address SAR_0 Specify the DMA transfer source address Set the DMA transfer destination address DAR_0 Specify the DMA transfer destination address Specify the DMA transfer count DMATCR_0 Set the DMA transfer count to 128 Set t
13. pt request Disable an interrupt request to the CPU at the end of a transfer On chip RAM Transfer source address H OxFFF81000 512 byte data DMA transfer i Transfer destination address H O0xFFF82000 PIREA ROE RAER 512 byte data SAR Source address register a Legend DAR Destination address register Figure 4 Operation of Sample Program REJ06B0732 0100 Rev 1 00 March 2008 Page 6 of 13 i l SH7211 Group L E N ESAS Data Transfer between On chip RAM Areas with DMAC Cycle Stealing Mode 2 3 Procedure for Setting Modules This section describes the procedure for making initial settings when the DMAC is to be used to transfer data between locations within the on chip RAM Auto request mode is used for the transfer requests By default the on chip peripheral modules of this MCU are in module standby mode Whenever any of these modules is to be used be sure to take it out of module standby mode before making the initial settings Although processing to delete the end of DMA transfer is typically handled by interrupts polling is used in this sample application A flowchart of the sample program is shown in figure 5 In addition a flowchart of DMAC initialization is shown in figure 6 For details on registers refer to the SH7211 Group Hardware Manual main 1 Cancel module standby mode STB CR2 BIT _DMAC 0 1 Activate the DMAC DMAC_init 2 2 Initialize the DMAC cha
14. rnal ROM Bus interface External RAM it U UUL External device memory mapped Bus state controller External device with acknowledge DREQO to DREQ3 DACKO to DACK3 TENDO TENDI Legend RDMATCR DMA reload transfer count register CHCR DMA channel control register DMATCR DMA transfer count register DMAOR DMA operation register RSAR DMA reload source address register DMARSO to DMARS3 DMA extension resource selectors 0 to 3 SAR DMA source address register HEIn DMA transfer half end interrupt request to the CPU RDAR DMA reload destination address register DElIn DMA transfer end interrupt request to the CPU DAR DMA destination address register n 0 1 2 3 4 5 6 7 Figure 3 Block Diagram of DMAC REJ06B0732 0100 Rev 1 00 March 2008 Page 5 of 13 QE NESANS SH7211 Group Data Transfer between On chip RAM Areas with DMAC Cycle Stealing Mode 2 2 Operational Description of Sample Program The settings of the DMAC for the sample program are listed in table 4 Also the operation of the sample program is illustrated in figure 4 Table 4 Settings of DMAC DMA transfer condition Auto request mode Channel CHO Length of transfer data 4 bytes Maximum transfer count 128 transfers 128 x data length of 4 bytes 512 byte data Address mode Dual address mode Bus mode Cycle stealing mode Priority level Channel priority level fixed mode Interru
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