Home

NXP Semiconductors TFA9812 User's Manual

1. 25 010aaa492 25 010aaa493 Po Po W chan W chan 20 20 1 1 15 2 15 2 3 10 3 10 4 5 4 5 0 0 8 10 12 14 16 18 20 8 10 12 14 16 18 20 Vp V Vp V 1 Power limiter 0 dB 1 Power limiter 0 dB 2 Power limiter 2 1 5 dB 2 Power limiter 1 5 dB 3 Power limiter 3 dB 3 Power limiter 3 dB 4 Power limiter 2 4 5 dB 4 Power limiter 2 4 5 dB a Vp 12V BL 2 x6 Q fi 1 kHz THD 1 96 b Vp 12 V RL 2 x6 Q fi 1 kHz THD 10 25 010aaa494 25 010aaa495 Po Po W chan W chan 1 15 15 2 2 3 10 10 3 3 4 5 4 5 0 0 8 10 12 14 16 18 20 8 10 12 14 16 18 20 Vp V Vp V 1 Power limiter 0 dB 1 Power limiter 0 dB 2 Power limiter 2 1 5 dB 2 Power limiter 1 5 dB 3 Power limiter 3 dB 3 Power limiter 3 dB 4 Power limiter 2 4 5 dB 4 Power limiter 2 4 5 dB C Vp 15V RL 2x8 Q fi 1 kHz THD 1 96 d Vp 15 V RB 2 x 8 Q fi 1 kHz THD 10 96 Fig 24 Output power as a function of supply voltage TFA9812_2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 59 of 66 NXP Semiconductors TFA9812 BTL stereo Class D audio amplifier with I2S input
2. 10 102 103 104 105 fi Hz Vp 12 V Viippie 500 mV RMS reference to ground No input signal 1 R 80 2 RL 62 Fig 21 SVRR as a function of frequency 010aaa489 100 S N dB 1 90 80 70 60 50 10 2 10 1 1 10 102 Po W channel Vp 15 V 20 kHz AES17 filter 1 RL 2x82 2 RL 2x62 Fig 22 S N ratio as a function of output power 010aaa490 25 W chan 20 9 120 240 360 480 600 time s a Vp IDN Ri 2x6 Q BTL fi 1 kHz 1 Tact th fold 125 C 2 Tact th fold 105 C 3 Team we 90 C Fig 23 Output power as a function of time 25 010aaa491 Po W chan 20 1 15 2 10 3 5 0 0 120 240 360 480 600 time s b Vp 20 V R 2 x 8 Q BTL fi 1 kHz TFA9812_2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 58 of 66 NXP Semiconductors TFA9812 BTL stereo Class D audio amplifier with I2S input
3. 3 010aaa496 P W 2 1 2 1 0 10 2 10 1 1 10 102 Po W channel Vp 12 V f 1 kHz Power dissipation in junction only 1 RL 2x6Q 2 RL 2x8Q 100 010aaa497 NPO 80 60 40 20 Vp 12 V fi 1 kHz npo 2 x Po 2 x Po Pa 1 RL 2x62 2 RL 2x82 8 10 Po W channel Fig 25 Power dissipation as a function of output Fig 26 Efficiency as a function of output power power 0 010aaa498 Ocs dB 20 40 1 Loot 100 10 102 Vp 12V Po 1W 1 RL 2x6Q 2 RL 2x8Q Fig 27 Channel separation as a function of frequency 103 104 f Hz 105 TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 60 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input 15 Package outline HVQFN48 plastic thermal enhanced very thin quad flat package no leads 48 terminals body 7 x 7 x 0 85 mm SOT619 8 terminal 1 index area detail X terminal 1 index are
4. 6 Block diagram TEST1 TEST2 AVOL PHASED REGISTER LOCKED ADDRESS LOOP HEX 01 XTALIN 4 CLOCK XTALOUT 2 OSCILLATOR eno TON UFP MCLK 47 OFP IBP THERMAL FOLDBACK BCK 46 WS 45 VOLUME INTER PARAMETRIC CONTROL POLATION l AND SOFT FILTER AND EQUALIZER MUTE DE EMPHASIS SERIAL AUDIO DATA 44 INTERFACE POWERUP 31 ENABLE GAIN CSEL ADSEL2 PLIM2 ADSEL1 PLIM1 SCL SFOR SDA MS be H N CONTROL UVP INTERFACE Fig 1 TFA9812 block diagram Voppi3v3 VDDA 3V3 TFA9812 VpDA BOOT1P VDDP DRIVER HIGH CONTROL OUTIP LOGIC DRIVER EOW VssP2 PWM CONTROLLER BOOTIN DRIVER HIGH CONTROL OUT1N LOGIC DRIVER LOW VssP1 STAB1 BOOT2P DRIVER HIGH OUT2P CONTROL LOGIC CONTROL LOGIC PWM CONTROLLER DRIVER LOW BOOT2N OUT2N STAB2 DIAG CDELAY STABD REFD STABA REFA EXPOSED DIE PADDLE Vss Vss2 010aaa217 indui Szi uu JaIyI dwe oipne q sse D 0919 S 118 cL86V4J L SJ10 1o9npuooiulesS dXN NXP Semiconductors TFA9812 BTL stereo Class D audio amplifier with I2S input Figure 1 shows the block diagram of the TFA9812 For a detailed description of the audio signal path see Section 8 1 7 Pinning information 7 1 Pinning 2 P tC n 2X x i H a 1 z i sw SERS RHEE P885 XTALIN ADSEL2 PLIM2 XTALOUT C
5. ENABLE pin value Function 0 Output stages in 3 state mode 1 Switching enabled D 1 Can be overruled by a forced 3 state in Sleep or Fault mode 8 7 Protection mechanisms The TFA9812 has a wide range of protection mechanisms to facilitate optimal and safe application All of these are active in both 12C and Legacy control modes The following protections are included in the TFA9812 Thermal Foldback TF OverTemperature Protection OTP e OverCurrent Protection OCP OverVoltage Protection OVP UnderVoltage Protection UVP Window Protection WP Lock Protection LP UnderFrequency Protection UFP e OverFrequency Protection OFP Invalid BCK Protection IBP DC blocking ESD The reaction of the device to the different fault conditions differs per protection TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 23 of 66 NXP Semiconductors TFA981 2 8 7 1 8 7 2 8 7 3 8 7 4 8 7 5 TFA9812 2 BTL stereo Class D audio amplifier with I2S input Thermal foldback If the junction temperature of the TFA9812 exceeds the programmable Thermal foldback threshold temperature the gain of the amplifier is decreased gradually to a level where the combination of dissipation P and the thermal resistance from junction to ambient Rn a results in a junction temperature around the threshold temperature This means that the device will n
6. 9 12S master slave modes and MCLK BCK clock modes 10 Power up power down 13 POWOI UD i E REX EE FS 13 Power down 14 Digital audio data input 14 Digital audio data format support 14 Digital audio data format control 16 Digital signal processing features 16 EGQUaAllZer z 2 5 3 bee actes bie eer 16 Equalizer options 16 Equalizer band function 16 Equalizer band control 18 Digital volume Control 20 Soft mute and mute 21 Output signal and word select polarity control 21 Gain boost and clip level control 21 Output power limiter n n anaana naaa 22 PWM control for performance improvement 22 Class D amplification 23 Protection mechanisms 23 Thermal foldback 24 Overtemperature protection 24 Overcurrent protection 24 Overvoltage protection 24 Undervoltage protections 24 Overdissipation protection 25 Window protection 25 Lock porotechon s anana annae 25 Underfrequency protection 25 BTL stereo Class D audio amplifier with I2S input 8 7 10 8 7 11 8 7 12 8 7 13 9 9 1 9 2 9 3 9 4 9 5 9 5 1 9 5 2 9 5 3 9 5 4 9 5 5 9 5 6 9 5 7 9 5 8 9 5 9 9 5 10 9 6 10 11 12 13 13 1 13 2 13 3 14 14 1 14 2 14 3 14 4 14 4 1 14 4 2
7. un Cc BUS TFA9812 BTL stereo Class D audio amplifier with IS input Rev 02 22 January 2009 Preliminary data sheet 1 General description 2 Features The TFA9812 is a high efficiency Bridge Tied Load BTL stereo Class D audio amplifier with a digital 12S audio input It is available in a HVQFN48 package with exposed die paddle The exposed die paddle technology enhances the thermal and electrical performances of the device The TFA9812 features digital sound processing and audio power amplification It supports 12C control mode and Legacy mode In Legacy mode 12C involvement is not needed because the key features are controlled by hardware pin connections A continuous time output power of 2 x 12 W R 8 Q Vppp 15 V is supported without an external heat sink Due to the implementation of a programmable thermal foldback even for high supply voltages higher ambient temperatures and or lower load impedances the device operates without sound interrupting behavior TFA9812 is designed in such a way that it starts up easily no special power up sequence required It features various soft and hard impact protection mechanisms to ensure an application that is both user friendly and robust A modulation technique is applied for the TFA9812 which supports common mode choke approach 1 common mode choke only per BTL amplifier stage This minimizes the number of external components 2 1 Genera
8. BTL stereo Class D audio amplifier with I2S input Fig 9 Eee ee Left out HEHEHE 2x5or2x10 Right in Right out Equalizer configuration and register location mapping III 2x5or2x10 010aaa404 TFA9812 2 Table 38 Bit description of registers xxh 04 06 2A Bit 15 14 to 4 3to0 Symbol Eyy t Eyy_k1 10 0 Eyy_k1 3 0 Description The filter configuration bit t4 see Section 8 5 1 2 The 11 mantissa bits of the filter parameter k4 see The four exponent bits of the filter parameter k see Section 8 5 1 2 Table 39 Bit description of registers xxh z 05 07 2B Bit 15 14 to 11 10 to 8 7 to 1 Symbol Eyy t Eyy kem 3 0 Eyy kee 2 0 Evy ko 6 0 Eyy s Description The filter configuration bit t see Section 8 5 1 2 The four mantissa bits of the filter parameter k see Section 8 5 1 2 The three exponent bits of the filter parameter ko see Section 8 5 1 2 The seven bits of the filter gain parameter ko see The filter scale factor bits see Section 8 5 1 2 0 No scaling applied 12 6 dB amplification enabled NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 34 of 66 NXP Semiconductors TFA9812 BTL stereo Class D audio amplifier with I2S input Table 40 Default configuration equalizer for f 44 1 kHz Band A1 B1 A2 B2 A
9. VDDP 13 14 16 17 20 21 23 24 Vssp1 Vssp2 010aaa468 VDDA A SH Vss1 Vss1 010aaa469 VDDA 2pA 30 4 200nA 5ko J DISCHARGE Mee 010aaa470 VDDA 31 h Oy 250 nA Vss1 010aaa471 33 34 35 36 37 43 Pull down 4 50 pA ESD ADSEL2 PLIM2 ADSEL1 PLIM1 TEST2 Vss1 Vss2 REFA REFD Exposed die paddle 010aaa472 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 41 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input Table 52 Internal circuitry continued Pin Symbol Equivalent circuitry 38 SCL SFOR gt 38 44 Vss1 Vss2 REFA REFD Exposed die paddle 010aaa473 39 SDA MS 39 ESD Vss1 Vss2 REFA REFD Exposed die paddle 010aaa474 45 WS V 46 BCK DDD 3V3 47 MCLK m 45 46 47 gt zi VSS1 VSS2 REFA REFD Exposed die paddle 010aaa475 11 Limiting values Table 53 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Conditions Min Max Unit VbpA analog supply voltage Vss DI 0 3 24 V Vppp power supply voltage Vsspx X 1 2 0 3 24 V VDDA 3V3 analog supply voltage 3 3 V Vss DI 0 3 4 6 V VppD 3v3 digital supply voltage 3 3 V Vss DI 0 3 44 6 V Tj junction temperature 150 C Tag storage temperature 55 150 C
10. TFA9812 2 BTL stereo Class D audio amplifier with I2S input Table 17 GAIN pin functionality GAIN pin value Function 0 0 dB gain 1 24 dB gain The I C controls for selecting the 24 dB gain can be found in Section 9 5 6 The GAIN pin has no function In 12C mode The TFA9812 features also specific gain settings which are related to lt 0 5 96 10 96 20 or 30 clipping at the output of the TFA9812 These clipping values are only valid under the following conditions e The volume control is set to 0 dB The gain boost is set to 0 dB A 0 dBFs IS input signal is obtained The 2C controls for selecting a specific clip level can be found in Section 9 5 6 In Legacy mode the clip level is set to 10 96 Output power limiter Output power can be limited to three discrete levels with respect to the maximum power The maximum power output value is determined by the value of the high voltage supply Clipping levels see Section 8 5 5 still apply to the maximum levels of reduced output voltage swings In DC control mode the same output power limiting levels can be selected see Section 9 5 6 In Legacy control mode two pins can be used to select the output power limit level as shown in Table 18 Table 18 Legacy mode output power limiter control Pin value Function ADSEL2 PLIM2 ADSEL1 PLIM1 0 0 Maximum power 0 1 Maximum power 1 5 dB 1 0 Maximum power 3 0 dB 1 1 Maximum power 4 5 dB PWM control f
11. 010aaa477 indu Szi uu Jeiyijduie oipne q ssej oeieis 118 SIOJONPUODIWIIBS dXN cL86V4J L jeeus ejep Aseuwijaid c0 Ae 600z Menuer zz 99 JO pS 2 c186v4L peniesei siuDu Iv 6002 A A dXN 14 4 3 S master mode and Legacy control mode DIAGNOSTIC RVDDA 4 gt VPA POWERUP 100 gt DC VOLUME CONTROL Vp 8 V to 20 V gt POWER IN gt gt VP ENABLE tL CvppP 220 uF 25V GND E CDELAY CSTAB 1nF 100 nF 36 33 32 31 30 29 28 27 26 25 e z Az lt a E z o be e oi E z Q o o a ka 2 2 i CBOOT 37 is nF ADSEL1 PLIM1 SCL SFOR Rsn 102 OUT1N Lic 3 3 V 39 spams ow qu dig vil BOOT2P T 470p OO 680 n OO ee ES D 601080 2 sde CSN _ F 1 un DE o Vopp gt VpDD 3V3 OUT2P see 42 pF T 680 nF 4 To Rgn 100 I STABD OUT2P H Cvddd CSTABD VP 100 nF 1 uF 42 pero pete CVDDP TEST2 Vor 2 FES DATA DATA OUTIP 5 COBOOT SWS 45 snf Pen l gt WS OUT1P T Lic sal ag rare 5 46 CSN rT 680 nF OUT2 Ep BOR BCK BOOTIP T E E CSN S1 F1 CLC 601080 12S MLCK optional 47 470 pF 7 15H 680 nF S MCLK OUT2N j 599 48 RSN 100 Vss2 OUT2N CBOOT m 15 nF EXPOSED DIE PADDLE E z 3 amp a x o SS g x gt a 1 2 3 4
12. 124 dB in steps of 0 5 dB The last step of the volume control is mute Table 16 shows the various settings and their related channel suppression NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 20 of 66 NXP Semiconductors TFA981 2 8 5 3 8 5 4 8 5 5 TFA9812 2 BTL stereo Class D audio amplifier with I2S input Table 16 Volume control channel suppression table 7 0 control value hexadecimal Gain dB 00 0 01 0 5 is steps of 0 5 dB F7 123 5 F8 124 F9 mute Section 9 shows the 12C address locations for the digital gain control for both channels In Legacy mode the pin AVOL 32 can be used to control the volume Voltage levels of 0 8 V to 2 8 V correspond linearly to control values of 00h 0 dB to F9h mute See Table 16 An external pull up resistor connected to the Vppp sva can be applied to provide a default volume of 0 dB Pin AVOL has no function in 12C mode Soft mute and mute Soft mute is available in I2C and in Legacy control modes hard mute can be enabled only in 12C control mode In DC control mode the soft mute function smoothly reduces the gain setting for both channels to mute level over a duration of 128 f seconds The smooth shape is implemented as a raised cosine function Soft demute results in a similar gain increase This implementation avoids audible plops A different soft mute and soft demute function is implemented
13. Operating mode active Fig 3 twake ta on Power up power down timing td mute_off ta soft_mute 010aaa219 8 3 1 Power up TFA9812 2 Figure 3 and Table 10 describe the power up timing while Table 11 shows the pin control for initiating a power up reset Table 10 Power up power down timing Symbol lwake ld on ld mute off ld soft mute Parameter wake up time turn on delay time mute off delay time Soft mute delay time Conditions 12C control 12C control legacy controll Min 70 Typ 15 Max 135 128 f 128 f Unit ms ms ms 1 Mute in Legacy mode is controlled by AVOL pin NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 13 of 66 NXP Semiconductors TFA981 2 8 3 2 8 4 8 4 1 TFA9812 2 BTL stereo Class D audio amplifier with I2S input In 12C control mode communication is enabled after 4 ms The preferred 12C settings can be made within 66 ms before the PLL starts running Finally the output stages are enabled and the audio level is increased via a demute sequence if mute has previously been disabled Remark In 12C mode soft mute is enabled by default It can be disabled at any time while I2C communication is valid In order to prevent audio clicks volume control default setting is 0 dB should be set before soft mute is disabled Remark For a proper
14. OverTemperature Protection OTP thermal protection activation temperature OverVoltage Protection OVP Tact th prot overvoltage 20 22 3 protection supply voltage UnderVoltage Protections UVP VP ovp VP uvp undervoltage UVP on VppA 7 7 5 protection supply UVP on VppA 3v3 1 6 2 2 voltage OverCurrent Protection OCP lo ocp overcurrent DI 3 0 3 3 protection output current Window Protection WP Vo output voltage high level VppA 1 low level REFA 1 OverFrequency Protection OFP forp Overfrequency At PLL output frequency 4 100 140 protection frequency UnderFrequency Protection OFP furp Underfrequency At PLL output frequency DI 30 45 protection frequency Max Unit 132 C 160 C 24 V V 3 0 V 3 6 A V V 185 MHz 60 MHz 1 Ip is the current through the analog supply voltage Vppa pin added to the current through the power supply voltage Vppp pin 2 Thermal foldback temperature sensor is not located at hottest spot Hottest spot is 12 C higher 3 Current limiting concept in overcurrent condition no interruption of the audio signal in case of impedance drop 4 PLL output frequency not external available TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 46 of 66 NXP Semiconductors TFA9812 BTL stereo Class D audio amplifier with I2S input 13 2 AC characteristics Table 56 AC charact
15. 0x23 0x5040 R W Section 9 5 5 Equalizer D4 word 2 0x24 0x0534 R W Section 9 5 5 Equalizer A5 word 1 0x25 0x4B40 R W Section 9 5 5 Equalizer A5 word 2 0x26 0x0534 RAN Section 9 5 5 Equalizer B5 word 1 0x27 0x4B40 R W Section 9 5 5 Equalizer B5 word 2 0x28 0xD961 R W Section 9 5 5 Equalizer C5 word 1 0x29 0x4840 R W Section 9 5 5 Equalizer C5 word 2 Ox2A OxD961 RAN Section 9 5 5 Equalizer D5 word 1 0x2B 0x4840 R W Section 9 5 5 Equalizer D5 word 2 0x2C 0x0005 R W Section 9 5 6 PWM signal control Ox2D 0x000E R W Section 9 5 7 Digital in clock configuration Ox2E 0x0000 R W Section 9 5 8 Thermal foldback control Ox2F R Section 9 5 9 TFA9812 temperature 0x30 R Section 9 5 10 Miscellaneous status Reserved registers or bits will be indicated by RSD NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 30 of 66 NXP Semiconductors TFA9812 BTL stereo Class D audio amplifier with I2S input 9 5 1 Interpolator settings and soft mute Table 28 Register address 00h miscellaneous IC interpolator settings Bit 15 14 13 12 11 10 9 8 Symbol RSD RSD RSD RSD RSD RSD RSD RSD Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol RSD INV_POL ROFF1 ROFFO FDEMP2 FDEMP1 FDEMPO S MUTE Default 0 0 1 0 0 0 0 1 0 Table 29 Bit description of register 00h miscellaneous PC interpolator settings Bit Symbol Description 6 INV POL Enable polarity inversi
16. 5 6 HIR 10 11 12 XTALL 3 3V VPA ro oe CXTALL CXTALL CVDDA RSTABA b CSTAB CVPA CSTAB 18 pF 18 pF Tor 1kQ E E Le Fig 15 Simplified application diagram for IS master mode and Legacy control mode 010aaa478 indui Szi ui jeiyijduie oipne q ssej oeieis 118 cL86V4J L SIOJONPUODIWIIBS dXN jeeus ejep Aseutwijaid c0 Ae 600z 1enuer zz 99 Jo SG 2 cI86v4L Doug siuDu UN 6002 A A dXN 14 4 4 I S master mode and I2C control mode DIAGNOSTIC POWERUP gt ENABLE gt S 7 5 S E S S w e Ww D 77 a ADSEL1 PLIM1 12C SCL gt SCL SFOR 2 SE SDA MS VDDD Vppp 3v3 D DATA gt CVDDD 100 nF STABD CSTABD 1uF REFD TFA9812 TEST2 DATA Ps WS E 2 I BCK WSs BCK CS MLCK MCLK Vss2 EXPOSED DIE PADDLE XTALOUT 3 3 V CXTALL CVDDA 100 nF pulum Fig 16 Simplified application diagram for IPS master mode and I C control mode RVDDA gt VPA 100 Vp 8V to 20V POWER IN T gt VP CL CvppP T 220uF 25V GND BOOT1N OUTIN Rsn 102 OUTIN Lic F2 S2 CSN A OA Tus e OUT T 470 berg 680 nl BOOT2P a ER pem eames DC v OUT2P ceoor 9F Sut Te
17. In case of any inconsistency or conflict between information in this document and such terms and conditions the latter will prevail No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights 18 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus logo is a trademark of NXP B V For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 64 of 66 NXP Semiconductors TFA9812 20 Contents TFA9812 2 General description 1 Features 2 22 ite Eee ES ds 1 General features 1 DSP features 2 Audio data input interface format support 2 Applications 0 cece eee 2 Quick reference data 3 Ordering information Lee 4 Block diagram 5 Pinning information lesse 6 PINNING EEN 6 Functional description 8 General ll a ig E AE AE ue 8 Functional modes sesanan annann 9 Control modes 9 Key operating modes
18. No UVP has been detected 1 A UVP has been detected since the last read out of the register 2 DIAG Diagnostic pin flagging statusl 0 Diagnostic pin has not been flagged low 1 Diagnostic pin has been flagged low since the last read out of the register 1 LP PLL lock protection indicator 0 PLL is in locked status 1 PLL is not in locked status 0 MUTE Soft mute status 0 No soft mute or soft mute demute in progress 1 Audio signal muted as result of a soft mute 1 The diagnostic pin 30 DIAG is flagged when several protection mechanisms have been active see Section 8 7 Overview of functional control in each control mode Table 51 shows the control level supported by either 1 C or Legacy control mode for all functions described in Section 9 It summarizes the information provided in the detailed description of each function Table 51 Functional control support in EC and Legacy control modes D fixed control setting determined by default PC register setting N not supported Y fully supported i e all options implemented in the TFA9812 Control function Reference 12C mode Legacy mode 12C register content Section 9 Y N D Sleep mode enable Section 8 2 2 Y Y Operating mode enable Section 8 2 2 Y Y 3 state mode enable Section 8 2 2 Y Y Master Slave I S Section 8 2 3 Y Y MCLK BCK master input clock selection Section 8 2 3 Auto Auto Digital audio input format selection Section 8 4 Y Subset Selection f 8 kH
19. Tamb ambient temperature 40 85 C P power dissipation 5 W TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 42 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input Table 53 Limiting values continued In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Conditions Min Max Unit Vss 0 3 Vss 12 V Vss 0 3 VppA 0 3 V Vss 0 5 Vss 5 5 V Vy voltage on pin x DIAG POWERUP ENABLE GAIN CSEL ADSEL2 PLIM2 ADSEL2 PLIM1 SCL SFOR SDA MS DATA WS BCK MCLK AVOL DI Vss 0 5 Vss 4 6 V Vesd electrostatic discharge voltage according to the human body model STAB1 and STAB2 with 1750 1750 V respect to other pins all other pins 2 2 kV according to the charge 500 4500 V device model 1 Vas Vssi Vss2 REFA REFD 12 Thermal characteristics Table 54 Thermal Characteristics Symbol Parameter Condition Min Typ Max Unit Rih a thermal resistance No air flow JEDEC board pua 42 KW from junction to No air flow typical 4L board in 2 36 K W ambient the NXP 4L reference application No air flow typical 2L board in HI 42 KW the NXP 2L reference application Rih c thermal resistance B5 K W from junction to case Rih lead thermal resistance Worst case pin 5 K W from junction to lead 1 Measured in a JEDEC high K factor test b
20. The BD modulation provides a high signal to noise performance and eliminates clock jitter noise Via four differential comparators the PWM signals are amplified by two BTL power output stages By default the left audio signal is connected to channel 1 and the right audio signal to channel 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 8 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input The block control defines the operational control settings of the TFA9812 in line with the actual I C settings and the pin controlled settings The PLL block creates the system clock and can take the I2S BCK the MCLK or an external crystal as reference source The following protections are built into the TFA9812 Thermal Foldback TF e OverTemperature Protection OTP OverCurrent Protection OCP OverVoltage Protection OVP UnderVoltage Protection UVP Window Protection WP Lock Protection LP UnderFrequency Protection UFP e OverFrequency Protection OFP Invalid BCK Protection IBP e DC blocking ElectroStatic Discharge ESD 8 2 Functional modes 8 2 1 8 2 2 TFA9812 2 Control modes The two control modes of the TFA9812 are I C and legacy n I C mode the I C format control is enabled n Legacy mode a pin based subset of the control options is available The control settings for features which are n
21. V P 1 soft mute mode with load 38 45 mA filter and snubbers connected sleep mode n 160 270 pA operating mode 12S slave mode 2 4 mA 12S master mode 4 6 mA sleep mode VppA Vppp 12 V 120 uA Vppa Vopp 1 V 40 70 uA operating mode 12S slave mode 15 25 mA 12S master mode 25 40 mA sleep mode 4 30 uA DATA WS BCK MCLK 20V Continuous time output power per channel THD 10 96 Di 8O M Vppp 12 V as Ww Vona Vppp 13 5 V 10 Ww Vor Vppp 15 V 12 Ww Short time lt 10 s output power per channel THD 10 RL 8Q Vppa Vppp 17 V 15 Ww RL 8Q Po RMS 8 3 W a 88 1 Ipis the current through the analog supply voltage Vppa pin added to the current through the power supply voltage Vppp pin TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 3 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input 5 Ordering information Table 2 Ordering information Type number Package Name Description Version TFA9812HN HVQFN48 plastic thermal enhanced very thin quad flat package no leads SOT619 8 48 terminals body 7 x 7 x 0 85 mm TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 4 of 66 yooys eyep Aseulwijeid c0 Ae 600z Menuer zz 99 Jo G Z e186v4L peAJese Syu e 6002 8 dXN
22. called MCLK clock mode The 2S input BCK signal on the BCK pin called BCK clock mode The I S master or slave mode can be selected In DC control mode by selecting the right 12C setting In legacy control mode by selecting the right setting on the SDA MS pin NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 10 of 66 NXP Semiconductors TFA9812 BTL stereo Class D audio amplifier with I2S input Table 6 S master slave mode selection Pin value Clock mode 1S mode CSEL SDA MS 0 0 legacy slave 0 1 legacy master 1 12C slave or master 1 Under these conditions the mode is enabled by the appropriate DC setting In 12S slave mode selection between BCK and MCLK clock modes is automatic MCLK clock mode is given higher priority than BCK If the MCLK clock is judged valid by the protection circuit then MCLK clock mode is enabled BCK clock mode is enabled when the MCLK clock is invalid e g not available and the BCK clock is judged valid by the protection circuit see Section 8 7 11 Table 7 shows the supported crystal frequencies in 12S master mode Table 8 shows the supported MCLK frequencies in MCLK mode I S slave mode Table 9 shows the supported BCK frequencies in BCK mode 12S slave mode Table 7 Valid crystal frequencies in I2S master mode Control mode fs KHz Crystal frequency MHz 12C 8 16 32 64 128 8 192 11 025 22 05
23. in Legacy mode This works via the analog gain control under the control of pin AVOL The analog volume control input signal is first order low pass filtered with a time constant of 10 ms in the digital domain Suddenly switching on or switching off volume by setting the control voltage to 2 8 Vor 0 8 V respectively will result in a fading which lasts approximately 15 ms switching between 0 V and 3 3 V at AVOL In Legacy mode the soft demute function that is part of the automatic power up sequence is similar to the 12C mode soft demute function described above The 12C control for the soft and hard mute functions can be found In Section 9 Output signal and word select polarity control In DC control mode the TFA9812 can switch the polarity of the stereo output signal The effect is a 180 degree phase shift of both output signals The TFA9812 also has the option of switching the polarity of the WS signal Without polarity inversion the left audio signal is connected to channel 1 and the right audio signal is connected to channel 2 The 12C control for the polarity switch can be found in Section 9 5 1 Gain boost and clip level control An additional gain boost of 24 dB can be selected in the TFA9812 In Legacy mode this feature can be selected with the GAIN pin see Table 17 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 21 of 66 NXP Semiconductors TFA981 2 8 5 6 8 5 7
24. protection OFP sets the output stages to 3 state mode when the clock input source is too high The PWM controller can become unstable when the clock input source is higher than specified Without OFP peripheral devices in an application might be damaged The status of the OFP is shown in DC reading register see Section 9 5 10 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 25 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input 8 7 11 Invalid BCK protection The BCK clock signal is verified as being at one of the allowed relative frequencies 32 fs 48 fs or 64 fg If itis not at one of these frequencies the TFA9812 will set the output stages to 3 state mode to prevent audible effects The MCLK clock signal is also verified as being valid see Section 8 2 3 Detection of violation results in an automatic internal overruling of the MCLK assignment to BCK 8 7 12 DC blocking The TFA9812 features a high pass filter after the I2S input to block DC signals DC values at the output can damage the peripheral devices The high pass filter is always enabled 8 7 13 Overview protections Table 21 shows the overview of the protections Table 21 Overview protections Protections Symbol Conditions DIAG Pc Output Recovering pin flag TF programmable Floating Switching Automatic increasing max T gt 125 C volume control back to volume s
25. sheet Rev 02 22 January 2009 17 of 66 NXP Semiconductors TFA981 2 8 5 1 3 TFA9812 2 BTL stereo Class D audio amplifier with I2S input Kj G K cosQ 5 K 2Q sin 20 sino Bus The ranges of the TFA9812 parametric equalizer settings for each band are e The Gain G is from 30 dB to 12 dB e The center frequency f is from 0 0004 fs to 0 49 fg The quality factor Q is from 0 001 to 8 Using 12C control filter coefficients need to be entered for each filter stage to configure it as desired Figure 6 Figure 7 and Figure 8 show some of the possible transfer functions of the equalizer bands The relations are symmetrical for the suppression and amplification functions A skewing effect can be observed for the higher frequencies Different configurations are available for the same filter transfer function thus allowing optimum numerical noise performance The binary filter configuration parameters t and t2 control the actual configuration and should be chosen according to Equation 6 1 Kid 0 kj 0 6 t 2 k 0 7 W lt 1 2 fj A maximum of 12 dB amplification per equalizer stage can be achieved with respect to the input signal Each band of the equalizer is provided with a 6 dB amplification so in order to prevent numerical clipping for some filter settings with over 6 dB of amplification band filters can be scaled by 0 dB or 6 dB For optimum numerical noise performa
26. start up in IG master mode and EC mode the following sequence should be followed 1 The I S master setting should be set and keep the default sample rate setting active 2 Next another sample rate setting than the default one should be selected 3 Finally when the default sample rate is used the default sample rate setting should be selected again Power down Figure 3 includes the power down timing while Table 11 shows the pin control for enabling power down Table 11 Power up power down selection Power up pin Description value 0 Power down Sleep mode 1 Power up Putting the TFA9812 into power down is equivalent to enabling Sleep mode see Section 8 2 2 This mode is entered immediately and no additional clock cycles are required In order to prevent audible clicks soft mute should be enabled at least Ta sort mute seconds before enabling Sleep mode The specified low current and power conditions in Table 1 are valid within 10 us after enabling Sleep mode Digital audio data input Digital audio data format support The TFA9812 supports a commonly used range of GG and I S like digital audio data input formats These are listed in Table 12 Table 12 Supported digital audio data formats BCK frequency Interface format MSB first Supported in IPC Supported in Legacy control mode control mode 32 f 12S up to 16 bit data yes yes 32 f MSB justified 16 bit data yes yes 32 f LSB justified 16 bit data yes yes 4
27. with I2S input 10 010aaa484 THD N 1 1071 10 2 10 102 103 104 105 f Hz a Vp 2 12V BL 22x69 Po21W Fig 18 Total harmonic distortion plus noise as a function of frequency 10 010aaa485 THD N 1 107 10 2 10 102 103 104 10 f Hz b Vp 12V RL 2x8Q P 1W 010aaa486 10 102 103 104 105 Vp 12V Po 1W 1 RL 269 15 uH 680 uF 2 RL 8Q 15 uH 680 uF Fig 19 Gain as a function of frequency 010aaa487 100 120 0 0 5 1 1 5 2 2 5 3 AVOL V Vp 12V R 8 Q fi 1 kHz 1 0dB 2 24 dB gain boost Fig 20 Gain as a function of AVOL TFA9812_2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 57 of 66 NXP Semiconductors TFA9812 BTL stereo Class D audio amplifier with I2S input 010aaa488
28. 14 4 3 14 4 4 14 5 15 16 17 18 18 1 18 2 18 3 Overfrequency protection 25 Invalid BCK protection 4 26 DC blocking 0c eee eee eee 26 Overview protections 26 PC bus interface and register settings 27 2C bus interface 0 0 2 eee 27 12C bus TFA9812 device addresses 27 IC write cycle description 28 IC read cycle description 28 Top level register map 29 Interpolator settings and soft mute 31 Volume Control 31 Digital input format 32 Equalizer configuration 32 Equalizer settings onana aaau 33 PWM signal contre 35 Digital in clock configuration 36 Thermal foldback control 36 TFA9812 temperature 37 Miscellaneous status 37 Overview of functional control in each control mode 38 Internal circuitry 39 Limiting values esee 42 Thermal characteristics 43 Characteristics seslsesee 44 DC Characteristics nnana anann 44 AC characteristics 47 TMN WEE 48 Application information 49 Output power estimation 49 Output current limiting 50 Speaker configuration and impedance 51 Typical application schematics 51 12S slave mode and Legacy control mode 52 12S sla
29. 2 January 2009 NXP Semiconductors TFA9812 18 Legal information 18 1 Data sheet status BTL stereo Class D audio amplifier with I2S input Document status Product statusi Definition Objective short data sheet Development Preliminary short data sheet Qualification Product short data sheet Production This document contains data from the objective specification for product development This document contains data from the preliminary specification This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 18 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type n
30. 3 B3 A4 B4 A5 B5 C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 Frequency 31 63 125 250 500 1000 2000 4000 8000 16000 Hz Q factor 1 1 1 1 1 1 1 1 1 1 Gain dB 0 0 0 0 0 0 0 0 0 0 9 5 6 PWM signal control Table 41 Register 2Ch PWM signal control Bit 15 14 13 12 11 10 9 8 Symbol RSD RSD RSD RSD RSD RSD RSD RSD Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol RSD PLIM1 PLIMO PW OFF PW SF1 PW SFO PW CL1 PW CLO Default 0 0 0 0 0 1 0 1 Table 42 Bit description address 2Ch Bit Symbol Description 7 GAIN 24 dB gain boost 0 Gain boost 0 dB 1 Gain boost 24 dB 6to5 PLIM 1 0 Output power limitation 0 Maximum power 1 Maximum power 1 5 dB 2 Maximum power 3 0 dB 3 Maximum power 4 5 dB 4 PW OFF Hard mute control 0 No hard mute 1 Hard mute enabled implemented by PWM signal with 50 96 duty cycle 3 to 2 PW_SF 1 0 PWM switching frequency 0 350 kHz 1 400 kHz 2 700 kHz 3 750 kHz 1to0 PW CL 1 0 PWM clip level 0 lt 0 5 THD 1 10 THD 2 20 THD 3 30 THD TFA9812_2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 35 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input 9 5 7 Digital in clock configuration Table 43 Register 2Dh digital in clock configuration Bit 15 14 13 12 11 10 9 8 Symbol RSD RSD RSD RSD RSD RSD RSD RSD Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol RSD RSD RSD FSUB3 FSUB2 FSUB1 FS
31. 44 1 88 2 11 2896 176 4 12 24 48 96 192 12 288 Legacy 32 8 192 44 1 11 2896 48 12 288 Table 8 Valid MCLK frequencies in IS slave mode Control mode fs KHz MLCK frequency MHz 12C 8 16 32 64 128 8 192 12 288 32 18 432 576 fs 11 025 22 05 44 1 88 2 11 2896 116 4 16 9344 44 1 25 4016 576 fs 12 24 48 96 192 12 288 18 432 48 27 648 576 fe NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 11 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input Table8 Valid MCLK frequencies in I2S slave mode Control mode fs KHz MLCK frequency MHz Legacy 32 8 192 12 288 18 432 576 fs 44 1 11 2896 16 9344 25 4016 576 fs 48 12 288 18 432 27 648 576 fs Table 9 Valid BCK frequencies in I2S slave mode Control mode fs KHz BCK x f input 12C 8 to 19201 32 fs 8 to 19211 48 fs 8 to 19211 64 f Legacy 32 44 1 48 32 fs 32 44 1 48 48 fs 32 44 1 48 64 fs 1 The valid sample frequencies are shown in Section 9 5 7 TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 12 of 66 NXP Semiconductors TFA9812 BTL stereo Class D audio amplifier with I2S input 8 3 Power up power down external voltage supplies POWERUP pin ENABLE pin 12C available soft mute setting in 12C mode AVOL pin in Legacy mode PWM outputs
32. 7 of 66 NXP Semiconductors TFA981 2 9 3 9 4 TFA9812 2 BTL stereo Class D audio amplifier with I2S input I C write cycle description Table 25 shows the cycle required for writing data to the PC registers of the TFA9812 The byte size is 8 bits The I C registers of the TFA9812 store two data bytes Data is always written in pairs of two bytes Data transfer is always MSB first The cycle format for writing to the TFA9812 using SDA is as follows 1 The microcontroller asserts a start condition S 2 The microcontroller sends the device address 7 bits of the TFA9812 followed by the R W bit set to 0 3 The TFA9812 asserts an acknowledge A 4 The microcontroller writes the 8 bit TFA9812 register address to which the first data byte will be written 5 The TFA9812 asserts an acknowledge 6 The microcontroller sends the first byte This is the most significant byte of the register 7 The TFA9812 asserts an acknowledge 8 The microcontroller sends the second byte 9 The TFA9812 asserts an acknowledgement 10 The microcontroller can either assert the stop condition P or continue with a further pair of data bytes repeating step 6 In the latter case the targeted register address will have been auto increased by the TFA9812 Table 25 12C write cycle Start TFA9812 R IW TFA9812 first MS LS More Stop Address register address databyte databyte data S 11010A2A 0 A ADDR A MSi A LS1 lt a gt P
33. 8 fs 12S up to 24 bit data yes yes 48 fs MSB justified up to 24 bit data yes yes NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 14 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input Table 12 Supported digital audio data formats BCK frequency Interface format MSB first Supported in EC Supported in Legacy control mode control mode 48 fs LSB justified 16 bit data yes no 48 fs LSB justified 18 bit data yes no 48 fs LSB justified 20 bit data yes no 48 fs LSB justified 24 bit data yes yes 64 fs 12S up to 24 bit data yes yes 64 fs MSB justified up to 24 bit data yes yes 64 fs LSB justified 16 bit data yes no 64 fs LSB justified 18 bit data yes no 64 fs LSB justified 20 bit data yes no 64 fs LSB justified 24 bit data yes no Remark Only MSB first formats are supported 1 2 3 1 2 3 ec V V V NF NT NT Fee NNN NN Zo o Ca XX usse E Y XX D use sr X MSB JUSTIFIED FORMAT ws Sones LEFT A Dem f 16 15 2 1 16 15 1 sx WAUAUAUAUAUAUAU RU RU VIVIVIVI WAVAUAUAUAUAUAUAUAU BRU RUA DATAX AMS gg X CO E UT Iueget GD E LSB JUSTIFIED FORMAT 16 BITS NE cm LEFT EE AX P NN A 18 17 16 15 2 1 18 17 16 15 2 1 sx WAV ME WAUAUAUAUAUAUAU AU AU NNI NINI LLL WAVAUAUAUAUAUAUAUAU UV E C3 CJ CX RENN E E LSB JUSTIFIED FORMAT 18 BITS ws ET NL RIGHT n 20 19 18 17 16 15 2 1 20 19 18 17 16 15 2 1 sx VVV VVVVUVVVV_ VVV VUV LLL UVUVVVVVVVUV
34. At loj 3 mA 400 mV voltage ENABLE GAIN CSEL ADSEL2 PLIM2 ASEL1 PLIM1 pin Vin HIGH level input With respect to Vss2 0 7xVppp va V voltage Vit LOW level input With respect to Vaso E 0 3 x Vppp 3v3 V voltage Vhys i input hysteresis With respect to Vss2 0 1 x Vpppava V voltage li input current 50 93 uA Regulators Vo output voltage STAB1 Vss1 10 11 12 V STAB2 Vssi 10 11 12 V STABA REFA 1 65 1 8 1 95 V STABD REFD 1 65 1 8 1 95 V CDELAY pin VCDELAY voltage on pin Relative to positive Vppa 1 V CDELAY analog power supply Crystal pins Vo xtal p p peak to peak crystal With respect to Vss2 1 8 V oscillator output voltage AVOL pin Vi input voltage Mute level with respect 0 77 0 8 0 83 V to Vss2 0 dB level with respect 2 74 2 8 2 86 V to Vss2 li input current 1 uA TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 45 of 66 NXP Semiconductors TFA9812 BTL stereo Class D audio amplifier with I2S input Table 55 DC characteristics continued Unless specified otherwise Vppa Vppp 12 V Vssp1 Vssp2 20V VppA 3v3 Vppb sva 3 3 V Vegi Vss2 REFD REFA 0 V Tam 25 C R 89 f 1 KHz fs 44 1 kHz foy 400 kHz 24 bit 2S input data MCLK clock mode typical application diagram Figure 13 Symbol Parameter Condition Min Typ Thermal Foldback TF Tacit fog thermal foldback D 118 125 activation temperature
35. I 100nF CBOOT Sege Day 10 re s Lcc Er SA 680 nF OUT LL PARS i E Fi me 601080 470 pF 15 uH SR 680 nF L Rsn 102 BOOT T 15nF 010aaa476 indu Szi uu Jeiyijduie oipne q ssej ooeieis 118 SJ10 1o9npuooiulesS dXN cL86V4J L jeeus ejep Aseulwijaid c0 Ae 600z Menuer zz 99 Jo G 2 cI86V4L Doug siuDu Iv 6002 8 dXN 14 4 2 12S slave mode and HRC control mode DIAGNOSTIC POWERUP ENABLE E 5 i a T E S E S 9 o n a ADSEL1 PLIM1 I c SCL D SCL SFOR 12C SDA E SDA MS VDDD VoDD 3V3 TABD CVDDD CSTABD d 100 nF T 1uF REFD TFA9812 TEST2 e IS DAIA DATA 2 25 WS ws 2 Fp BCK BCK 2 EQ MECK MCLK Fig 14 Simplified application diagram for I2S slave mode and EC control mode Vss2 EXPOSED DIE PADDLE XTALOUT BOOT1N BOOT2N RVDDA gt VPA 102 Vp 8V to 20V POWER IN T gt VP CL CvppP T 220uF 25V OUTIN Rsn 102 OUTIN Lic F2 2 CSN EE Tus OUT BOOT2P T 470 pF Aor 680 nF e Low x 51 Fi mar 601080 S OUT2P T ou ma T 820 nF Le Ren 100 OUT2P VppP Eu VppP Lesen OUTIP Rsn 102 T SUE re sd oe OUT BOOTIP Ti cum d 2 l ET EU ccv 690820 OUT2N 15 uH ye nF Rsn 102 OUT2N
36. I C read cycle description Table 26 shows the cycle required for reading data from the 12C registers of the TFA9812 The byte size is 8 bits The 12C registers of the TFA9812 store two data bytes Data is always read in pairs of two bytes Data transfer is always MSB first The read cycle format for writing to the TFA9812 using SDA is as follows 1 The microcontroller asserts a start condition S 2 The microcontroller sends the device address 7 bits of the TFA9812 followed by the R W bit set to 0 3 The TFA9812 asserts an acknowledge A 4 The microcontroller writes the 8 bit TFA9812 register address from which the first data byte will be read 5 The TFA9812 asserts an acknowledge 6 The microcontroller asserts a repeated start Sr 7 The microcontroller resends the device address 7 bits of the TFA9812 followed by the R IW bit set to 1 8 The TFA9812 asserts an acknowledge NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 28 of 66 TFA9812 BTL stereo Class D audio amplifier with I2S input NXP Semiconductors 9 The TFA9812 sends the first byte This is the most significant byte of the register 10 The microcontroller asserts an acknowledge 11 The TFA9812 sends the second byte 12 The microcontroller asserts either an acknowledge or a negative acknowledge NA Ifthe microcontroller has asserted an acknowledge the targeted register address is aut
37. P and OUT2N IVo offset l output offset voltage soft mute mode 5 mV Power up pin Vin HIGH level input With respect to Vss1 2 1 Vobpb 3v3 V voltage Vu LOW level input With respect to Ves 0 3 0 8 V voltage li input current 0 1 20 uA MCLK BCK WS DATA pin Vin HIGH level input With respect to Vss2 0 7 x Vpppava V voltage Vit LOW level input With respect to Vss2 0 3 x Vpppava V voltage Ci input capacitance 3 pF TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 44 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input Table 55 DC characteristics continued Unless specified otherwise Vppa Vppp 12 V Vssp1 Vssp2 0V VDDA 3v3 Vppp 3v3 3 3 V Ween Vss2 REFD REFA 0 V Tamp 25 C R 8 Q f 1 kHz fs 44 1 kHz fsw 400 kHz 24 bit IPS input data MCLK clock mode typical application diagram Figure 13 Symbol Parameter Condition Min Typ Max Unit Vou HIGH level output At lou 0 4 mA Vppp v3 0 4V 7 V voltage VoL LOW level output At lol 4 mA 400 mV voltage CL load capacitance 50 pF SDA MS SCL SFOR pin Vin HIGH level input With respect to Vss2 0 7 x Vppp 3v3 5 5 V voltage Vit LOW level input With respect to Vss2 0 3 0 3 x Vpppava V voltage Vhys i input hysteresis With respect to Vss2 0 1 x Vpppavs V voltage Ci input capacitance 2 5 pF VoL LOW level output
38. SD k Vss1 Vss2 REFA REFD Exposed die paddle 010aaa459 STABA pw Vss1 Vss2 REFA REFD Exposed die paddle 010aaa460 Vss1 Vss2 REFA REFD Exposed die paddle 010aaa461 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 39 of 66 NXP Semiconductors TFA9812 Table 52 BTL stereo Class D audio amplifier with I2S input Internal circuitry continued Pin 4 41 28 10 11 18 19 26 27 12 15 22 25 TFA9812 2 Symbol Equivalent circuitry STABA V V STABD DDA 3V3 VDDD 3V3 4 41 ule ESD Vss1 Vss2 REFA REFD Exposed die paddle 010aaa462 REFA 6 VDDA 24V 5 Vss1 REFD Vss2 Exposed die paddle 010aaa463 TEST1 VDDA A 7 4 13 kQ A AN Vss1 010aaa464 STAB2 V STAB1 ids 9 28 un 12V Vssi 010aaa465 Ter 18 19 VppP VssP1 SC 10 11 26 27 010aaa466 BOOT2N 12 15 22 2 BOOT1P Pee BOOT2P 12V BOOT1N OUT2N OUT1P OUT2P OUT1N 010aaa467 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 40 of 66 NXP Semiconductors TFA9812 Table 52 Internal circuitry BTL stereo Class D audio amplifier with I2S input continued Pin 13 14 16 17 20 21 23 24 29 30 31 33 34 35 36 37 43 TFA9812 2 Symbol OUT2N OUT1P OUT2P OUT1N DIAG CDELAY POWERUP ENABLE GAIN CSEL Equivalent circuitry
39. SEL VDDA 3V3 GAIN STABA ENABLE REFA AVOL xem 5 INN te Vssi 8 DIAG STAB2 STAB1 VssP2 VssP1 VssP2 VssP1 BOOT2N 12 BOOTIN LEE mn eM m SS ae i Transparent top view i Fig 2 Pin configuration transparent top view Table 3 Pinning description TFA9812 Pin Symbol Type Description 1 XTALIN l Crystal oscillator input 2 XTALOUT O Crystal oscillator output 3 VDDA 3V3 P Analog supply voltage 3 3 V 4 STABA O 1 8 V analog stabilizer output 5 REFA P Analog reference voltage 6 VppA P Analog supply voltage 8 V to 20 V 7 TEST1 Test signal input 1 For test purposes only connect to Vss 8 Vssi P PCB ground reference 9 STAB2 O Decoupling of internal 11 V regulator for channel 2 drivers 10 Vssp2 P Negative power supply voltage for channel 1 and channel 2 11 Vssp2 P Negative power supply voltage for channel 1 and channel 2 12 BOOT2N O Bootstrap high side driver negative PWM output channel 2 13 OUT2N O Negative PWM output channel 2 TFA9812_2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 6 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input Table 3 Pinning description TFA9812 continued Pin Symbol Type Description 14 OUT2N O Negative PWM output channel 2 15 BOOT1P O Bootstrap high side driver positive PWM output channel 1 16 OUT1P O Positive PWM output channel 1 17 OUT1P O Positive PWM output channel 1 18 VDDP P Positive power su
40. Symbol 15108 VOL L 15 8 7100 VOL R 7 0 Description See Table 16 for suppression levels on left channel as function of data byte setting See Table 16 for suppression levels on right channel as function of data byte setting 9 5 3 Digital input format Table 32 Register address 02h digital input format Bit 15 14 13 12 11 10 9 8 Symbol RSD RSD RSD RSD RSD RSD RSD RSD Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol RSD RSD RSD RSD DI FOR2 DI FOR1 DI FORO WS POL Default 0 0 0 0 0 1 1 0 Table 33 Bit description of register 02h digital input format Bit Symbol Description 3to 1 DI FOR 2 0 Digital audio input format 0 RSD 1 RSD 2 MSB justified data up to 24 bits 3 ES data up to 24 bits 4 LSB justified 16 bit data 5 LSB justified 18 bit data 6 LSB justified 20 bit data 7 LSB justified 24 bit data 0 WS_POL Enable WS signal polarity inversion 0 No WS signal polarity inversion 1 WS signal polarity inversion enabled 9 5 4 Equalizer configuration Table 34 Register address 03h equalizer configuration Bit 15 14 13 12 11 10 9 8 Symbol RSD RSD RSD RSD RSD RSD RSD RSD Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol RSD RSD RSD RSD RSD RSD EQ_BP EQ_BND Default 0 0 0 0 0 0 1 0 TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 32 of 66 NXP Semiconductors TFA9812 BTL stereo Class D audio amplifier wi
41. TEMPS TEMP4 TEMP3 TEMP2 TEMP1 TEMPO Default Table 48 Bit description of register 2Dh digital in clock configuration Bit Symbol Description 9 to 0 TEMPT 9 0 Temperature of the TFA9812 which can be calculated in C using Temp TFA9812 1023 TEMP 9 0 2 4552 9 5 10 Miscellaneous status Table 49 Register 30h miscellaneous status Bit 14 13 12 11 10 9 8 Symbol RSD RSD RSD RSD RSD RSD RSD RSD Default Bit 6 5 4 3 2 1 0 Symbol RSD OFP UFP UVP1V8 UVP3V3 DIAG LP MUTE Default TFA9812 2 Preliminary data sheet Table 50 Bit description of register 30h miscellaneous status Bit Symbol Description 6 OFP PLL frequency over range indicator 0 PLL frequency in supported range 1 PLL frequency exceeds highest supported frequency value 5 UFP PLL frequency under range indicator 0 PLL frequency in supported range 1 PLL frequency below lowest supported frequency value 4 UVP1V8 Undervoltage detector for pins 4 and 41 0 No UVP has been detected 1 A UVP has been detected since the last read out of the register NXP B V 2009 All rights reserved Rev 02 22 January 2009 37 of 66 NXP Semiconductors TFA981 2 TFA9812 2 9 6 BTL stereo Class D audio amplifier with I2S input Table 50 Bit description of register 30h miscellaneous status continued Bit Symbol Description 3 UVP3V3 Undervoltage detector for pins 3 and 40 0
42. UBO DI MS Default 0 0 0 0 1 1 1 0 Table 44 Bit description of register 2Dh digital in clock configuration Bit Symbol Description 4 to 1 FSUB 3 0 Sample frequency fs of digital in signal 0 8 kHz 1 11 025 kHz 2 12 kHz 3 16 kHz 4 22 05 kHz 5 24 kHz 6 32 kHz 7 44 1 kHz 8 48 kHz 9 64 kHz 10 88 2 kHz 11 96 kHz 12 128 kHz 13 176 4 kHz 14 192 kHz 15 RSD 0 DI MS TFA9812 digital in Master Slave mode selection 0 Slave mode 1 Master mode 9 5 8 Thermal foldback control Table 45 Register 2Eh thermal foldback control Bit 15 14 13 12 11 10 9 8 Symbol RSD RSD RSD RSD RSD RSD TP THR9 TP THR8 Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol TP THR7 TP_THR6 TP THR5 TP THRA TP_THR3 TP THR2 TP THR1 TP THRO Default 0 0 0 0 0 0 0 0 TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 36 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input Table 46 Bit description of register 2Dh digital in clock configuration Bit Symbol Description 9 to 0 TP THR 9 0 Reduction on the maximum temperature of 125 C The reduction can be calculated by reduction INTEGER HETERO C 2 4552 9 5 9 TFA9812 temperature Table 47 Register 2Fh TFA9812 temperature Bit 14 13 12 11 10 9 8 Symbol RSD RSD RSD RSD RSD RSD TEMP9 TEMP8 Default Bit 6 5 4 3 2 1 0 Symbol TEMP7 TEMP6
43. V soft mute mode 70 E uV hard mute mode 30 uV Parms 1 W aggressor channel 50 54 dB fi 1 kHz Vripple 2 Von fripple 100 Hz 55 60 dB Ri 8 Q Povams 8 3 W B 88 926 Ri 6 Q Porms 9 7 W Ba 83 96 155 ms NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 47 of 66 NXP Semiconductors TFA9812 Table 56 AC characteristics continued BTL stereo Class D audio amplifier with I2S input Unless specified otherwise Vppa Vppp 12 V VppA 3V3 Vppp ava 8 8 V Tamp 25 C Rs lt 0 1 Qu R 8Q 1 kHz fg 44 1 kHz fey 400 kHz 24 bit PS input data MCLK clock mode typical application diagram Figure 13 Symbol Parameter tpp propagation delay PWM output t rise time tr fall time tw min minimum pulse width Rpson drain source on state resistance max maximum duty factor Condition fs 8 kHz 11 025 kHz 12 kHz 16 kHz 22 05 kHz 24 kHz 32 kHz 44 1 kHz 48 kHz 64 kHz 88 2 kHz 96 kHz 128 kHz 176 4 kHz 192 kHz lo 0A lo 0A lo 0A per output MOSFET for low and high side Min Typ Max Unit 3 6 ms 2 58 ms 2 39 ms 1 78 ms 1 3 E ms 1 18 ms 892 us 664 us 600 us 458 us 320 us 306 us 67 2 us 48 us 40 8 us 10 ns 10 D ns 40 ns 0 28 035 Q 0 96 1 2 13 3 Timing Table 57 Characteristics 12C bus interface Rs is the series resistance of inductor of low
44. VVV VVL DATAX fsa ES X83 X24 ES C e beste X83 X84 X85 X86 E A LSB JUSTIFIED FORMAT 20 BITS ws EFT B RIGHT 2 24 23 22 21 20 19 18 17 16 15 2 1 24 23 22 21 20 19 18 17 16 15 2 1 sx AA WU __ VV DATAy _______ sa 82 X 83 me es Xes X 57 Xes Keo ymroy XeasXissX_ wise e2 Yes X84 X85 X Bs XE XE E En ee 010aaa458 LSB JUSTIFIED FORMAT 24 BITS Fig 4 Serial interface input and output formats TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 15 of 66 NXP Semiconductors TFA981 2 8 4 2 8 5 8 5 1 8 5 1 1 8 5 1 2 TFA9812 2 BTL stereo Class D audio amplifier with I2S input In I2C control mode the following sample frequency f can be used 8 kHz 11 025 kHz 12 kHz 16 kHz 22 05 kHz 24 kHz 32 kHz 44 1 kHz 48 kHz 64 kHz 88 2 kHz 96 kHz 128 kHz 176 4 kHz or 192 kHz The I C control for f selection can be found in Section 9 5 7 In Legacy control mode the following sample frequencies f can be used 32 kHz 44 1 kHz or 48 kHz Digital audio data format control The BCK to WS and MCLK to WS frequency ratios are automatically detected so no control settings need to be configured for these In DC control mode all the formats listed in Table 12 are supported The appropriate IC controls for selecting the supported formats can be found in Section 9 In the Legacy control mode only a subset of the supported formats can be used These are show
45. Window Protection is only checked at power up 9 1 C bus interface and register settings 9 1 9 2 TFA9812 2 I2C bus interface The TFA9812 supports the 400 kHz I C bus microcontroller interface mode standard This can be used to control the TFA9812 and to exchange data with it when in DC control mode see Section 8 2 1 The TFA9812 can operate in 12C slave mode only as slave receiver or a slave transmitter The serial hardware interface involves the pins of the TFA9812 as described in Table 22 Table 22 C pins in I C control mode Pin name Description SCL SFOR IC bus clock input SDA MS IC bus data input and output ADSEL2 PLIM2 12C bus device address bit A2 ADSEL1 PLIM1 12C bus device address bit A1 Voltage values applied to the I2C bus device address pins are interpreted as described in Table 23 Table 23 1 C pin voltages in I2C control mode Logic value Voltage A2 A1 0 lt Vu 1 gt Vin I2C bus TFA9812 device addresses Table 24 shows the register address options for the TFA9812 as part of the 8 bit byte that contains the device address as well as the bit indicator read write not R IW The TFA9812 supports four different addresses each of which can be configured using the pins ADSEL1 PLIM1 and ADSEL2 PLIM2 see Table 22 Table 24 12C bus device address MSB Bit LSB 1 1 0 1 0 A2 Al R IW NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 2
46. a DIMENSIONS mm are the original dimensions AQ max UNIT Ay b c D Dn EG Eh m 1 0 05 0 30 0 2 734 575 74 5 75 0 00 0 18 6 9 5 45 6 9 5 45 Note 1 Plastic or metal protrusions of 0 075 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC JEITA PROJECTION SOT619 8 pi MO 220 iun E a Fe p ISSUE DATE Fig 28 Package outline SOT619 8 HVQFNA8 TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 61 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input 16 Handling information It is advisable to abide by the normal precautions appropriate to handling MOS devices TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 62 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input 17 Revision history Table 59 Revision history Document ID Release date Data sheet status TFA9812 2 20090122 Modifications Change notice Supersedes Preliminary data sheet TFA9812 1 Table 55 DC characteristics Vu maximum value updated TFA9812 1 2008 10 30 Preliminary data sheet TFA9812 2 NXP B V 2009 All rights reserved 63 of 66 Preliminary data sheet Rev 02 2
47. al into a standard internal stereo audio stream The 10 band parametric equalizer can optionally equalize the stereo audio stream Both channels have separate equalization streams It can be used for speaker transfer curve compensation to optimize the audio performance of applied speakers Volume control in the TFA9812 is done by attenuation The attenuation depends on the volume control settings and the thermal foldback value Soft mute is also arranged at this part In Legacy mode the volume control is done by an on board Analog to Digital Converter ADC which measures the analog voltage on pin 32 The interpolation filter interpolates from 1 fs to the PWM controller sample rate 2048 fs at 44 1 kHz by cascading FIR filters The gain block can boost the signal with O dB or 24 dB Four specific gain settings are also provided in this block These specific gain settings are related to maximum clip levels of lt 0 5 96 10 96 20 or 30 THD at the TFA9812 output These maximum clip levels are only valid with the gain boost set to 0 dB and a 0 dBFS input signal The power limiter limits the maximum output signal of the TFA9812 The power limiter settings are 0 dB 1 5 dB 3 dB and 4 5 dB This function can be used to reduce the maximum output power delivered to the speakers at a fixed supply voltage and speaker impedance The PWM controller block transforms the audio signal into a BD modulated PWM signal
48. amplifier with I2S input In the above equation f is the center frequency and f is the sample frequency The definition of the quality factor is the center frequency divided by the 3 dB bandwidth see Equation 1 In parametric equalizers this is only valid when the gain is set very small 30 dB A f 20 tel 2 3dB f f K i i 1 Q UE o Ay 1 iz 20 GE 508 Est fe Each band filter can be programmed to perform a band suppression G lt 1 ora band amplification G gt 1 function around the center frequency Each band of the TFA9812 equalizer has a second order Regalia Mitra all pass filter structure The structure is shown in Figure 5 P T ee 010aaa406 Fig 5 Regalia filter flow diagram The transfer function of this all pass filter is shown in Equation 2 H z 1 2 1 A 2 Ko 2 1 A z 2 A z is the second order filter structure The transfer function of A z is shown in Equation 3 ed 22 K K 1 K Z Z A z 4 __ ___ _ 3 1 K K Z K Z The relationship between the programmable parameters Ko K4 and K3 and the filter parameters G Q is shown in Equation 4 and Equation 5 Use Equation 4 to calculate band suppression G 1 functions LE K cosQ 4 K 20 G sin 2Q G sino T lt Use Equation 5 to calculate band amplification G gt 1 functions NXP B V 2009 All rights reserved Preliminary data
49. cations of the controls for various bands of the equalizer 12 010aaa222 Gan Q1 0 27 dB Ta Q2 0 61 8 HL D Q3 1 65 4 0 10 10 103 104 105 Frequency Hz Fig 6 Transfer functions for several quality factors Q NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 19 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input 010aaa223 Gain dB 0 101 102 103 104 105 Frequency Hz Fig 7 Transfer functions for several center frequencies fe 010aaa224 Gain dB 12 101 102 103 104 105 Frequency Hz Fig8 Transfer functions for several gain factors G 8 5 2 Digital volume control TFA9812 2 In 12C control mode both audio channels have separate digital volume control In Legacy control mode the volume control of both channels is common and the volume control setting depends on the supply voltage on the pin AVOL 32 8 bit volume control is available per channel This is dB linear down to
50. conditions are both changed to false Overdissipation is flagged by a low DIAG pin and by a high DIAG I C status bit see Section 9 5 10 Under normal conditions thermal foldback prevents overdissipation protection from being triggered I C settings remain valid Window protection Window protection is a feature for protecting the device against shorts from the outputs to the ground or supply lines If during power up one of the outputs is shorted to Vssp or Vppp power up does not proceed any further The trigger levels for these conditions are e OUTxx gt VppA 1 V or e OUTxx lt REFA 1 V The WP alarm is flagged by a low DIAG pin and by a high DIAG IC status bit see Section 9 5 10 Lock protection When the selected clock input source MCLK BCK or crystal stops running the TFA9812 is able to detect this and set the output stages to 3 state mode Without this protection peripheral devices in an application might be damaged The PLL lock indication is an I2C reading and will be false in the event of a clock interruption see Section 9 5 10 Underfrequency protection UFP sets the output stages to 3 state mode when the clock input source is too low The PWM switching frequency can becomes critically low when the clock input source is lower than specified Without UFP peripheral devices in an application might be damaged The status of the UFP is shown in I C reading register see Section 9 5 10 Overfrequency
51. el 1 20 a 30 2 2 10 3 19 H 0 0 8 12 16 20 24 8 12 16 20 24 Vp V Vp V 1 6 1 62 2 890 2 89 3 162 3 160 Fig 11 BTL Po 0 5 96 as a function of Vp Fig 12 BTL Po 10 as a function of Vp 14 2 Output current limiting The peak output current is internally limited above a level of 3 A minimum During normal operation the output current should not exceed this threshold level of 3 A otherwise the output signal will be distorted The peak output current in BTL can be estimated using Equation 12 Vp I lt 12 Se R 2 Roson Rs l Where Vp supply voltage V Vppp Vssp R load impedance Q Rpson On resistance power switch Q Rs series resistance output inductor Q TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 50 of 66 NXP Semiconductors TFA981 2 14 3 BTL stereo Class D audio amplifier with I2S input Remark A 4 8 speaker 6 Q speaker with 20 spread in BTL configuration can be used up to a supply voltage of 17 V without running into current limiting Current limiting clipping will avoid audio holes but it causes a distortion comparable to voltage clipping Speaker configuration and impedance For a flat frequency response second order Butterworth filter it is necessary to change the low pass filter components L c and C c according to the speaker configuration and im
52. en 15nF R 100 OUT2P T SN VDDP Vope LETS VDDP Vor Fone OUTIP OUTIP T new a Lic ogy d kal Za oum BOOTIP Ti EE Ei FI cc 601080 470 pF T OUT2N P 15 uH T nF Rsn 102 OUT2N DN E o fe a 010aaa479 indu Szi uu Jeiyijduie oipne q ssej oeieis 118 SIOJONPUODIWIIBS dXN cL86V4J L NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input 14 5 Curves measured in typical application 10 010aaa480 10 010aaa481 THD4N THD N 1 1 10 1 10 1 10 2 1072 10 2 10 1 1 10 102 10 2 10 1 1 10 102 Po W channel Po W channel 1 fj 2 6 kHz 1 fi 6 kHz 2 fi 1 kHz 2 fi 1 kHz 3 fi 100 Hz 3 fi 100 Hz a Vp 12V RL 2x6Q b Vp 12V R 2x8Q 10 010aaa482 10 010aaa483 THD N THD N 1 1 2 1 10 1 10 1 3 1072 10 2 10 2 1071 1 10 10 10 2 10 1 1 10 102 Po W channel Po W channel 1 fi 2 6kHz 1 fj 2 6kHz 2 fi 1 kHz 2 fi 1 kHz 3 fi 100 Hz 3 fi 100 Hz c Vp 15V R 2x6Q d Vp 15V RL 2x8Q Fig 17 Total harmonic distortion plus noise as a function of output power TFA9812_2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 56 of 66 NXP Semiconductors TFA9812 BTL stereo Class D audio amplifier
53. eristics Unless specified otherwise Vppa Vppp 12 V VpbA 3V3 Vppb sva 8 8 V Tamp 25 C Rs 0 1 oft R 89 1 kHz fs 44 1 kHz fey 400 kHz 24 bit PS input data MCLK clock mode typical application diagram Figure 13 Symbol Parameter Output power per channel Po RMS RMS output power Performance THD N total harmonic distortion plus noise S N signal to noise ratio Vn o output noise voltage Dee channel separation SVRR supply voltage ripple rejection Npo output power efficiency Power up times and delay times la on TFA9812 2 turn on delay time Condition Min Typ Max Unit Continuous time output power per channel THD 1 R 26 Q Vppa Vppp 12 V 79 Ww VppA Vppp 15 V 12 W Continuous time output power per channel THD 10 R 26 Q VppA Vppp 12 V 9 7 Ww Short time lt 10 s output power per channel THD 10 R 2 6 Q VppA Vppp 15 V 15 W Continuous time output power per channel THD 1 R 8 Q Vppa Vppp 12 V 6 6 WwW Vppa Vppp 15 V 10 WwW Continuous time output power per channel THD 10 RL 8 Q Vppa Vppp 12 V 8 3 W VppA Vppp 13 5 V 10 W Vppa Vppp 15 V 12 W Short time lt 10 s output power per channel THD 10 R 8 Q Vppa Vppp 17 V 15 W Po 1 W AES17 brick wall filter 0 07 0 1 96 Vo 10 V A weighted 103 dB MCLK clock jitter 200 ps AES17 brick wall filter operating mode 70 u
54. etting OTP Tj 160 C LOW DIAG Floating Automatic after 1 us and Tj lt 160 C OCP lo gt lonm LOW DIAG Floating Automatic after 1 us and lo lt lorm OVP Vppa gt 20 V LOW DIAG Floating Restart fault to operating when Vppa gt 8 V and Vppa ava gt 3 V UVP VppA lt 8 V or LOW DIAG Floating Restart fault to operating VppA ava lt 3 V when VppA 8 V and VppA ava gt 3 V ODP Tj gt 140 C and lo gt lornm LOW DIAG Floating Restart fault to operating when T 140 C or IO lt lorm WPI OUTX gt VppA 1 V or LOW DIAG Floating Restart fault to operating OUTX lt REFA A 1 V when OUTX lt VppA 1 V and OUTX gt Vssa 1 V LP PLL out of lock Floating LP Floating Restart fault to operating when PLL is in lock UFP PLL frequency lt 45 MHz Floating UFP Floating Restart fault to operating when PLL frequency gt 45 MHz TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 26 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input Table 21 Overview protections continued Protections Symbol Conditions DIAG 12C Output Recovering pin flag OFP PLL frequency gt 140 MHz Floating OFP Floating Restart fault to operating when PLL frequency 140 MHz IBP BCK WS is not 32 2 Floating Floating Restart fault to operating 48 20r64 2 when BCK WS is 32 2 48 2 or 64 2 1 See Section 9 5 10 2
55. l features 3 3 V and 8 V to 20 V external power supply High efficiency and low power dissipation Speaker outputs fully short circuit proof across load to supply lines and ground Pop noise free at power up power down and sample rate switching Low power Sleep mode Overvoltage and undervoltage protection on the 8 V to 20 V power supply Undervoltage protection on the 3 3 V power supply Overcurrent protection no audible interruptions Overdissipation protection Thermally protected and programmable thermal foldback Clock error protection 12C mode control or Legacy mode i e no 12C control Four different IC addresses supported Internal Phase Locked Loop PLL without using external components founded by Philips NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input No high system clock required PLL is able to lock on BCK No external heat sink required 5 V tolerant digital inputs Supports dual coil inductor application Easy application and limited external components required 2 2 DSP features Digital parametric 10 band equalizer Digital volume control per channel Selectable 24 dB gain boost Analog interface to digital volume control in Legacy mode Digital clip level control Soft and hard mute Thermal foldback threshold temperature control De emphasis Output power limiting control Polarity switch Four Pulse Width Modulation PWM switching frequency settings 2 3 Audio data input i
56. n in Table 12 and the required pin control is given in Table 13 See Section 8 2 1 for details of how to enable Legacy control mode Table 13 Digital audio data format selection in Legacy control mode SCL SFOR pin value Interface formats MSB first 0 2S 1 MSB justified Digital signal processing features Equalizer Equalizer options The equalizer function can be bypassed and the equalizer can be configured to either a 5 band or 10 band function These settings are for both audio channels simultaneously There are 20 bands in the equalizer These are distributed as follows Bands A1 to A5 are bands 1 to 5 of output 1 used in 5 band and 10 band configuration Bands B1 to B5 are bands 1 to 5 of output 2 used in 5 band and 10 band configuration Bands C1 to C5 are bands 6 to 10 of output 1 used in 10 band configuration only Bands D1 to D5 are bands 6 to 10 of output 2 used in 10 band configuration only In DC control mode each band can be configured separately using DC register settings In Legacy control mode the equalizer is bypassed Equalizer band function The shape of each parametric equalizer band is determined by the three filter parameters e Relative center frequency o 2n f f Quality factor Q Gain factor G NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 16 of 66 NXP Semiconductors TFA981 2 TFA9812 2 BTL stereo Class D audio
57. nce steps of 6 dB amplification should be applied to the highest possible sections that are still within scale signal processing safeguards Band filters can be scaled with the binary parameters listed in Table 14 Table 14 Equalizer scale factor coding s scale factor dB 0 0 1 6 Equalizer band control For compact representation with positive signed parameters parameters k and k are introduced in Equation 7 The parameters ko Kaka t4 t2 and s must be combined in two 16 bit control words word1 and word2 and must fit within the representation given in Table 15 Parameters ki and ka are unsigned floating point representations in Equation 8 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 18 of 66 NXP Semiconductors TFA981 2 TFA9812 2 BTL stereo Class D audio amplifier with I2S input l k cdm k A 7 kk t 0 iy l k t 0 Ik Gs E k M2 8 In Equation 8 M is the unsigned mantissa and E the negative signed exponent For example in word2 bits 14 8 0111 010 represent ka 7 24 x 2 2 1 09375 10 Table 15 Equalizer control word construction Word Section Data word1 15 ty word1 14 4 11 mantissa bits of ky word1 3 0 Four exponent bits of ky word2 15 to word2 14 11 Four mantissa bits of ko word2 10 8 Three exponents bits of ko word2 7 1 ko word2 0 S Section 9 5 4 shows the 12C address lo
58. nterface format support 3 Applications Master or slave Master Clock MCLK Bit Clock BCK and Word Select WS signals Philips 12S standard 12S Japanese DG Most Significant Bit MSB justified Sony 12S Least Significant Bit LSB justified Sample rates from 8 kHz to 192 kHz TFA9812 2 Digital in Class D audio amplifier applications CRT and flat panel television sets Flat panel monitors Multimedia systems Wireless speakers Docking stations for MP3 players NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 2 of 66 NXP Semiconductors TFA9812 4 Quick reference data Table 1 BTL stereo Class D audio amplifier with I2S input Quick reference table Unless specified otherwise Vppa Vppp 12 V Vssp1 Vssp2 0 V Vppa ava Vppp ava 3 3 V Vss1 Vss2 REFD REFA 0 V Tamb 25 C FL 8Q f 1 kHz fs 44 1 kHz fey 400 kHz 24 bit BS input data MCLK clock mode typical application diagram Figure 13 Symbol General VppA VppP Vppa 3v3 Voppzva Ip IDDA 3v3 Ippp 3v3 Po RMS Npo Parameter analog supply voltage power supply voltage analog supply voltage 3 3 V digital supply voltage 3 3 V supply current analog supply current 3 3 V digital supply current 3 3 V RMS output power output power efficiency Conditions Min Typ Max Unit 8 12 20 V 8 12 20 V 3 0 3 3 3 6 V 3 0 3 3 3 6
59. o increased by the TFA9812 and steps 9 to 12 are repeated fthe microcontroller has asserted a negative acknowledge the TFA9812 frees the 12C bus and the microcontroller generates a stop condition P Table 26 1 C read cycle Start TFA9812 R W First TFA9812 R W MS LS More More Stop address register address data data data data address byte byte S 11010A2A 0 A ADDR A Sr 11010A2A 1 A MS1 A LS1 A lt gt NA P 9 5 Top level register map Table 27 describes the assignments of the various register addresses to the functional control or status areas at top level There are 47 control registers and 2 status registers The following subsections give the individual register interpretations and bit level details Table 27 Top level register map Access See TFA9812 2 Register Default hex address hex 0x00 0x0020 Legacy mode 0x0021 EC mode 0x01 0x0000 0x02 0x0006 0x03 0x0002 0x04 0x0058 0x05 Ox4F40 0x06 0x0058 0x07 Ox4F40 0x08 0x0A63 0x09 0x4240 0x0A 0x0A63 0x0B 0x4240 0x0C 0x00B7 0x0D 0x4E40 Ox0E 0x00B7 OxOF Ox4E40 0x10 0x14A2 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Description Interpolator settings and soft mute Volume control Format digital in Equalizer configuration Equalizer A1 word 1 word 1 for equalizer band A1 see Section 8 5 1 2 Equalizer A1 word 2 see Equalizer B1 word 1 Equalizer B1 word 2 Equalize
60. oard standard EIA JESD 51 7 2 Measured in free air with natural convection 3 Strongly depends on where measurement is made on the case worst case value stated TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 43 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input 13 Characteristics 13 1 DC Characteristics Table 55 DC characteristics Unless specified otherwise Vppa Vppp 12 V Vssp1 Vssp2 0V Vppa3v3 Vppp 3v3 3 3 V Ween Vss2 REFD REFA 0 V Tamp 25 C R 8 Q f 1 kHz fs 44 1 kHz fsw 400 kHz 24 bit IPS input data MCLK clock mode typical application diagram Figure 13 Symbol Parameter Condition Min Typ Max Unit Supply voltage VDDA analog supply 8 12 20 V voltage Vppp power supply voltage 8 12 20 V VppA 3V3 analog supply 3 0 3 3 3 6 V voltage 3 3 V Vppb av3 digital supply voltage 3 0 3 3 3 6 V 8 3 V Ip supply current soft mute mode with i 38 45 mA load filter and snubbers connected sleep mode 0l 160 270 uA IppA 3v3 analog supply operating mode current 3 3 V 12S slave mode 2 4 mA 2S master mode 4 6 mA sleep mode VppA Vppp 12V 120 uA VppA Vppp 21V 40 70 uA Ippp 3v3 digital supply current operating mode 3 3 V 12S slave mode 15 25 mA 12S master mode 25 40 mA sleep mode 4 30 uA DATA WS BCK MLCK 0V Amplifier output pins pins OUT1P OUT1N OUT2
61. on 0 No polarity inversion left audio signal connected to channel 1 right signal to channel 2 1 Polarity inversion enabled 5 to 4 ROFF 1 0 Filter roll off sharpness 0 Slow filter roll off 2 to 8 fs 2 stop band gt 0 7619 fs 1 Slow filter roll off 2 to 8 fs 2 stop band gt 0 7619 fs 2 Fast filter roll off 2 to 8 fs 2 stop band gt 0 6094 f 3 Fast filter roll off 2 to 8 fs 2 stop band gt 0 6094 f 3 to 1 FDEMP 2 0 Digital de emphasis setting 0 No digital de emphasis 1 Digital de emphasis for f 32 kHz 2 Digital de emphasis for fs 44 1 kHz 3 Digital de emphasis for f 48 kHz 4 Digital de emphasis for f 96 kHz 5 to 8 No digital de emphasis 0 S MUTE Soft mute 0 Soft mute disabled using raised cosine default in Legacy control mode 1 Soft mute enabled using raised cosine default in 12C control mode 9 5 2 Volume control Table 30 Register address 01h volume control Bit 15 14 13 12 11 10 9 8 Symbol VOL L7 VOL L6 VOL L5 VOL L4 VOL L3 VOL L2 VOL L1 VOL LO Default 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Symbol VOL R7 VOL R6 VOL R5 VOL R4 VOL R3 VOL R2 VOL R1 VOL RO Default 0 0 0 0 0 0 0 0 TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 31 of 66 NXP Semiconductors TFA9812 BTL stereo Class D audio amplifier with I2S input Bit description of register 00h miscellaneous DC interpolator settings Table 31 Bit
62. on input in Legacy mode 40 Vppp 3v3 P Digital supply voltage 3 3 V 41 STABD O 1 8 V digital stabilizer output 42 REFD P Digital reference voltage 43 TEST2 Test signal input 2 for test purposes only connect to Vss 44 DATA I2S bus data input 45 WS UO 12S bus word select input I2S slave mode or output 12S master mode 46 BCK UO 12S bus bit clock input 12S slave mode or output 12S master mode TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 7 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input Table 3 Pinning description TFA9812 continued Pin Symbol Type Description 47 MCLK UO Master clock input I S slave mode or output I2S master mode 48 Vss2 P PCB ground reference Exposed P PCB ground reference die paddle 8 Functional description 8 1 General TFA9812 2 The TFA9812 is a high efficiency stereo BTL Class D amplifier with a digital I S audio input It supports all commonly used 12S formats Figure 1 shows the functional block diagram which includes the key function blocks of the TFA9812 In the digital domain the audio signal is processed and converted to a pulse width modulated signal using BD modulation A BTL configured power comparator carries out power amplification The audio signal processing path is as follows 1 The Digital Audio Input DAI block translates the IS like input sign
63. or performance improvement The PWM switching frequency of the TFA9812 is dependent on e The sampling frequency fs e The sampling frequency setting fs selected see Section 9 5 7 e The PWM switching frequency setting fs selected see Section 9 5 6 Equation 9 shows the relationship between these settings and the PWM carrier frequency fs free e m d ewtyenenindi 9 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 22 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input The selected PWM switching frequency is 400 kHz by default and can be set to 350 kHz 700 kHz and 750 kHz in 12C control mode In Legacy mode 400 kHz is the only option and this scales linearly if 32 kHz or 48 kHz is used as fs Remark The selected sample frequency fs selected must be equal to the sample frequency fs in 12C control mode Remark The performance of AM radio reception can sometimes be improved by selecting non interfering frequencies for the PWM signal 8 6 Class D amplification The Class D power amplification of the PWM signal is carried out in two BTL power stages The output signal voltage level is determined by the values on the Vppp pins The power amplifiers can be explicitly put into 3 state mode by using the pin ENABLE as shown in Table 19 The ENABLE pin is functional in Legacy mode and in 12C mode Table 19 ENABLE pin functionality
64. ot available in Legacy mode are set to the default IC register settings The control mode is selected via pin CSEL as shown in Table 4 Table 4 Control mode selection CSEL Pin value Control mode 0 Legacy no 12C 1 12C In the functional descriptions below the control for the various functions will be described for each control mode Section 9 6 summarizes the support given by each control mode for the various TFA9812 functions Key operating modes There are six key operating modes n Sleep mode the voltage supplies are present but power consumption for the whole device is reduced to the minimum level The output stages in Sleep mode are 3 state and I2C communication is disabled NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 9 of 66 NXP Semiconductors TFA981 2 8 2 3 TFA9812 2 BTL stereo Class D audio amplifier with I2S input In Soft mute mode the IS input signal is overruled with a soft mute In Legacy control mode the analog input pin AVOL controls Soft mute mode n EC control mode 12C control can be used to enable an automatic soft mute function See also Section 8 5 3 In Hard mute mode the PWM controller is overruled with a 50 96 duty cycle square pulse The Hard mute mode is only available in IC control mode In Operating mode the TFA9812 amplifies the DG audio input signal in line with the actual control setting In 3 state mode the outp
65. ot completely switch off but remains operational at lower output power levels Especially with music output signals this feature enables high peak output power while still operating without any external heat sink other than the printed circuit board area If the junction temperature still increases due to external causes the OTP switches the amplifier to 3 state mode Under 12C control the Thermal foldback threshold temperature value can be lowered see Section 9 5 8 In Legacy control mode the default threshold value of 125 C is fixed Overtemperature protection This is a hard protection to prevent heat damage to the TFA9812 The overtemperature threshold level is the 160 C junction temperature When the threshold temperature is exceeded the output stages are set to 3 state mode The temperature is then checked at 1 us intervals and the output stages will operate normally again once the temperature has dropped below the threshold level OTP is flagged by a low DIAG pin The TFA9812 temperature is an I C reading see Section 9 5 9 Under normal conditions thermal foldback prevents the overtemperature protection from being triggered Overcurrent protection The output current of the power amplifiers is current limited When an output stage exceeds a current of 3 A typical the output stages are set to 3 state mode and after 1 us the stages will start operating normally again These interruptions are not audible OCP is flagged by a lo
66. pass LC filter in the application see Figure 10 Output power measured across the loudspeaker load This is based on indirect measurement of Rpson Vppb ava VppA sva 2 7 V to 3 6 V Vppa Vopr 8 V to 20 V Tamb 20 C to 85 C all voltages referenced to ground unless otherwise specified Symbol Parameter fscL SCL clock frequency How LOW period of the SCL clock tHIGH HIGH period of the SCL clock tr rise time tr fall time tHD STA hold time repeated START condition tsu sTa set up time for a repeated START condition TFA9812 2 Conditions Min 1 3 0 6 20 0 1 Cp 20 0 1 Cp 0 6 SDA and SCL signals SDA and SCL signals 0 6 Typ Max Unit 400 kHz p us us ns ns us us NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 48 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input Table 57 Characteristics DC bus interface see Figure 10 continued Vppb ava VpDA sva 2 7 V to 3 6 V Vopa Vopr 8 V to 20 V Tamp 20 C to 85 C all voltages referenced to ground unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit tsu sTo set up time for STOP condition 0 6 us tBuF bus free time between a STOP and 1 3 us START condition tsu DAT data set up time 100 ns tHD DAT data hold time 0 S us tsp pulse width of spikes that must be BI o 50 ns sup
67. pedance Table 58 Filter component values Impedance Q Lic uH Cic nF 6 15 680 8 18 560 16 47 330 14 4 Typical application schematics TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 51 of 66 jeeus ejep Aseulwijaid c0 9H 600z 1enuer zz 99 Jo ZS 2 c186v4L pansasal siuDu UN 6002 8 dXN 14 4 1 12S slave mode and Legacy control mode DIAGNOSTIC EI POWERUP gt DC VOLUME CONTROL gt ENABLE gt D DATA 2S WS D 2 VS BCK CS MLCK optional ADSEL2 PLIM2 24 dB GAIN ENABLE POWERUP ADSEL1 PLIM1 SCL SFOR SDA MS Voppzva STABD REFD TFA9812 TEST2 DATA ws BCK MCLK Vss2 EXPOSED DIE PADDLE XTALOUT CSTAB 100 nF BOOT1N BOOT2N Fig 13 Simplified application diagram for I2S slave mode and Legacy control mode OUTIN OUTIN BOOT2P OUT2P OUT2P VppP VppP OUTIP OUTIP BOOT1P OUT2N OUT2N RVDDA gt VPA 100 Vp 8 Vto 20V POWER IN VP VL CvppP T 220 uF 25V GND CBOOT T 15 nF Rsn 102 Lic uito d OUT ze Ve WR ae p n z lea L 51 m L 60180 e i we T 15H D I CBoor 4208 I 1 Test nF T 15 nF ReN 10 2 a VP CVDDP 100 nF CVDDP
68. pply voltage 8 V to 20 V 19 Vppp P Positive power supply voltage 8 V to 20 V 20 OUT2P O Positive PWM output channel 2 21 OUT2P O Positive PWM output channel 2 22 BOOT2P O Bootstrap high side driver positive PWM output channel 2 23 OUT1N O Negative PWM output channel 1 24 OUT1N O Negative PWM output channel 1 25 BOOT1N O Bootstrap high side driver negative PWM output channel 1 26 VssP1 P Negative power supply voltage for channel 1 and channel 2 27 VssP1 P Negative power supply voltage for channel 1 and channel 2 28 STAB1 O Decoupling of internal 11 V regulator for channel 1 drivers 29 DIAG O Fault mode indication output open drain pin 30 CDELAY l Timing reference 31 POWERUP Power up pin to switch between Sleep and other operational modes 32 AVOL Analog volume control Legacy mode 33 ENABLE Enable input to switch between 3 state and other operational modes 34 GAIN Gain selection input to select between 0 dB and 24 dB gain Legacy mode 35 CSEL Control selection input to select between Legacy mode no 12C bus control and 12C bus control 36 ADSEL2 PLIM2 Address selection in IC mode input 2 power limiter selection input 2 in Legacy mode 37 ADSEL1 PLIM1 Address selection in IC mode input 1 power limiter selection input 1 in Legacy mode 38 SCL SFOR IC bus clock input in 12C mode DG serial data format selection input in Legacy mode 39 SDA MS y o 12C bus data input and output in IC mode master slave selecti
69. pressed by the input filter Cp capacitive load for each bus line 400 pF 1 Cy is the total capacitance of one bus line in pF The maximum capacitive load for each bus line is 400 pF 2 After this period the first clock pulse is generated 3 To be suppressed by the input filter SDA SCL tHD STA l l HD DAT iHiGH su bar SUSSTAI l LPI S Sr Rd 010aaa225 Fig 10 Timing 14 Application information 14 1 Output power estimation The output power just before clipping can be estimated using Equation 10 Qn enims ri max r Po 0 5 os L 10 Where Vp supply voltage V Vopp Vssp R load impedance Q Rpson On resistance power switch Q Rs Series resistance output inductor Q TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 49 of 66 NXP Semiconductors TFA981 2 BTL stereo Class D audio amplifier with I2S input max Maximum duty factor 0 96 The output power at 10 THD can be estimated using Equation 11 Po 10 1 25 P o 0 5 11 Figure 11 and Figure 12 show the estimated output power at THD 0 5 and THD 10 as a function of BTL supply voltage for different load impedances 30 010aaa347 45 010aaa348 Po 0 5 96 Po 10 W channel W chann
70. pts no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Quick reference data The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document and as such is not complete exhaustive or legally binding Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 may cause permanent damage to the device Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied Exposure to limiting values for extended periods may affect device reliability Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms including those pertaining to warranty intellectual property rights infringement and limitation of liability unless explicitly otherwise agreed to in writing by NXP Semiconductors
71. r C1 word 1 Equalizer C1 word 2 Equalizer D1 word 1 Equalizer D1 word 2 Equalizer A2 word 1 Equalizer A2 word 2 Equalizer B2 word 1 Equalizer B2 word 2 Equalizer C2 word 1 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 29 of 66 NXP Semiconductors TFA9812 TFA9812 2 BTL stereo Class D audio amplifier with I2S input Table 27 Top level register map continued Register Default hex Access See Description address hex 0x11 0x7A40 R W Section 9 5 5 Equalizer C2 word 2 0x12 0x14A2 R W Section 9 5 5 Equalizer D2 word 1 0x13 0x7A40 R W Section 9 5 5 Equalizer D2 word 2 0x14 0x0156 R W Section 9 5 5 Equalizer A3 word 1 0x15 0x4D40 R W Section 9 5 5 Equalizer A3 word 2 0x16 0x0156 RAN Section 9 5 5 Equalizer B3 word 1 0x17 0x4D40 R W Section 9 5 5 Equalizer_B3 word 2 0x18 0x2871 R W Section 9 5 5 Equalizer C3 word 1 0x19 0x7140 R W Section 9 5 5 Equalizer C3 word 2 Ox1A 0x2871 RAN Section 9 5 5 Equalizer D3 word 1 0x1B 0x7140 R W Section 9 5 5 Equalizer D3 word 2 0x1C 0x02A5 R W Section 9 5 5 Equalizer A4 word 1 Ox1D 0x4C40 R W Section 9 5 5 Equalizer A4 word 2 Ox1E 0x02A5 RAN Section 9 5 5 Equalizer B4 word 1 Ox1F 0x4C40 R W Section 9 5 5 Equalizer B4 word 2 0x20 0x4A80 R W Section 9 5 5 Equalizer C4 word 1 0x21 0x5040 R W Section 9 5 5 Equalizer C4 word 2 0x22 0x4A80 R W Section 9 5 5 Equalizer D4 word 1
72. th I2S input Table 35 Bit description of register 03h equalizer configuration Bit Symbol Description 1 EQ BP Equalizer bypass enable 0 Equalizer not bypassed 1 Equalizer bypassed 0 EQ BND Equalizer 10 band or 5 band configuration selection 0 10 band equalizer configuration enabled 1 5 band equalizer configuration enabled 9 5 5 Equalizer settings Table 36 Register addresses xxh 04 06 2A For word for equalizer yy see Figure 9 Bit 15 14 13 12 11 10 9 8 Symbol Eyy t Evy Kuel Evy Kei Eyy_kim8 Eyy_kim7 Eyy_kim6 Eyy_kim5 Eyy_kim4 Default Bit 7 6 5 4 3 2 1 0 Symbol Eyy ke Eyy_Kim2 Eu kal Eu ke Eu ke Eu ke Eyy kel Eu bei Default 1 Default settings are shown in Table 27 The corresponding equalizer configuration is shown in Table 40 Table 37 Register addresses xxh z 05 07 2B For word for equalizer yy see Figure 9 Bit 15 14 13 12 11 10 9 8 Symbol Eyy t Eyy kom3 Eyy kom2 Eug kan Eyy kal Eyy Koe2 Eyy Koel Eyy Kaell Default Bit 7 6 5 4 3 2 1 0 Symbol Eyy ko6 Eyy ko5 Eyy ko4 Eyy ko3 Eyy ko2 Eyy ko1 Eyy_ko0 Eyy s Default 1 Default settings are shown in Table 27 The corresponding equalizer configuration is shown in Table 40 TFA9812 2 NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 33 of 66 NXP Semiconductors TFA9812
73. umber s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail 18 3 Disclaimers General Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in medical military aircraft space or life support equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental 19 Contact information damage NXP Semiconductors acce
74. ut stages are switched off Fault mode is entered when a fault condition is detected by one or more of the protection mechanisms implemented in the TFA9812 In Fault mode the actual device configuration depends on the fault detected see Section 8 7 for more information Fault mode is for a subset of the faults flagged on the DIAG output pin When the DIAG pin is flagged the output stages will be forced to enter 3 state mode In Sleep mode the DIAG pin will not flag fault modes Table 5 Operational mode selection Pin DIAG Output Operational mode selected POWERUP ENABLE CSEL AVOL 0 floating Sleep mode 1 0 floating Fault mode enabled by system 1 1 1 floating Soft mute mode in IC control model 1 1 0 0 8V floating Soft mute in Legacy control mode 1 0 floating 3 state mode 1 1 floating Operational mode 1 Clocking faults do not trigger DIAG output 2 Under these conditions soft mute still has to be enabled by the appropriate 12C setting 12S master slave modes and MCLK BCK clock modes The I S interface can be set in master or in slave In 12S master mode the PLL locks to the output signal of the internal crystal oscillator circuit which uses an external crystal The BCK WS and MCLK signals are generated by the TFA9812 On the MCLK pin the TFA9812 delivers a master clock running at the crystal frequency In IPS slave mode the PLL can lock to The external MCLK signal on the MCLK pin
75. ve mode and BC control mode 53 12S master mode and Legacy control mode 54 12S master mode and I2C control mode 55 Curves measured in typical application 56 Package outline 61 Handling information 62 Revision history lese 63 Legal information 64 Data sheet status unuon naana 64 Definitions 64 Disclaimers se iii masa Re RR 64 continued gt gt NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 65 of 66 NXP Semiconductors TFA9812 18 4 Tradematks 5 vere wales wade 19 Contact information LL 20 Contents rss x xn RR DR DR ano ROAD founded by BTL stereo Class D audio amplifier with I2S input Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2009 All rights reserved For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 22 January 2009 Document identifier TFA9812 2
76. w DIAG pin and by a high DIAG 12C status bit see Section 9 5 10 12C settings remain valid Overvoltage protection The supply for the power stages Vppa Vppp is protected against overvoltage When a supply voltage exceeds 20 V the device will enter Sleep mode When the supply voltage has fallen below 20 V again the power up sequence is started OVP is flagged by a low DIAG pin and by a high DIAG C status bit see Section 9 5 10 12C settings remain valid Undervoltage protections The supplies are protected against undervoltage When this is detected the device will enter Sleep mode When the supply voltage has risen to a sufficient level again the power up sequence is started Table 20 shows the UVP trigger levels for the Vppa and Vppa ava supplies NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 24 of 66 NXP Semiconductors TFA981 2 8 7 6 8 7 7 8 7 8 8 7 9 8 7 10 TFA9812 2 BTL stereo Class D audio amplifier with I2S input Table 20 Undervoltage trigger levels Pin name UVP level DIAG pin protection active Min Max VppA gt 7V lt 8V LOW VppA 3v3 21 6V 3v Overdissipation protection When the output current of the power amplifiers exceeds a current value of 3 A and the temperature is above 140 C overdissipation protection is activated and the device enters Sleep mode A restart will be initiated automatically when the two overdissipation
77. z to192 kHz Section 8 4 1 Y pi Equalizer enable and configuration Section 8 5 1 Y DEI Detailed equalizer settings Section 8 5 1 Y N Digital volume control per channel Section 8 5 2 Y N Analog volume control shared for two channels Section 8 5 3 N Y De emphasis for subset of allowed fs Section 8 5 3 Y N Soft mute Section8 5 3 Y YB Hard mute Section 8 5 3 Y N Polarity switch enable Section 8 5 4 Y N 24 dB gain boost Section 8 5 6 Y Y NXP B V 2009 All rights reserved Preliminary data sheet Rev 02 22 January 2009 38 of 66 NXP Semiconductors TFA9812 BTL stereo Class D audio amplifier with I2S input Table 51 Functional control support in PC and Legacy control modes continued D fixed control setting determined by default DC register setting N not supported Y fully supported i e all options implemented in the TFA9812 Control function Clip level control Output power limit level control PWM signal frequency selection Thermal foldback threshold temperature control Section 8 7 1 Reference 12C mode Legacy mode Section8 5 5 Y Dl Section 8 5 6 Y Y Section 8 5 7 Y DIS Y N 1 32 kHz 44 1 kHz and 48 kHz supported 2 Bypass 3 Special Legacy mode implementation 4 10 clip level 5 400 kHz 10 Internal circuitry Table 52 Internal circuitry Pin Symbol 1 XTALIN 32 AVOL 2 XTALOUT 3 VpDA 3V3 40 Vppp 3v3 TFA9812 2 Equivalent circuitry 1 32 gt E

NXP Semiconductors TFA9812 User's Manual

Contents

Download Pdf Manuals

Related Search

Related Contents