Home

NEC uPD75P3116 User's Manual

1. U u 56 APPENDIX C RELATED DOCUMENTS u u nnne ne nnn nnne nnn nnn nnn 65 Data Sheet U11369EJ3VODS 3 NEC uPD75P3116 1 PIN CONFIGURATION TOP VIEW 64 pin plastic QFP 14 x 14 uPD75P3116GC AB8 64 pin plastic LQFP 12 x 12 uPD75P3116GK 8A8 64 pin plastic LQFP 14 x 14 uPD75P3116GC 8BS 64636261605958575655545352515049 BIAS 1 48 O S12 VLCO 2 Q 47 S13 VLC1 3 46 O 814 VLC2 4 45 515 P30 LCDCL MDO 5 44 P93 S16 P31 SYNC MD1 6 43 P92 S17 P32 MD2 7 42 P91 S18 P33 MD3 8 41 P90 S19 Vss 9 40 P83 S20 P50 D4 39 P82 S21 P51 D5 38 P81 S22 P52 D6 37 P80 S23 P53 D7 36 P23 BUZ P60 KRO DO 35 P22 PCL PTO2 P61 KR1 D1 34 P21 PTO1 P62 KR2 D2 P20 PTOO O O O O O OOO lt PN X XZ zoboozztt SSOBSHEX gt cooperta e on a z lt N Note Always connect the VPP pin directly to Voo during normal operation 4 Data Sheet U11369EJ3VODS NEC uPD75P3116 PIN IDENTIFICATIONS POO to Port 0 COMO to Common output 0 to 3 P10 to P13 Port 1 Vico to Vice LCD power supply 0 to 2 P20 to P23 Port 2 BIAS LCD power supply bias control P30 to P33 Port 3 LCDCL LCD clock P50 to P53 Port 5 SYNC LCD synchronization P60 to P63 Port 6 TIO to TI2 Timer input 0 to 2 P80 to P83 Port 8 PTOO
2. Supply voltage V Data Sheet U11369EJ3VODS 37 NEC 75 3116 Serial Transfer Operation 2 wire and 3 wire serial I O mode SCK Internal clock output Ta 40 to 85 C Vpp 1 8 to 5 5 V Parameter Test Conditions SCK cycle time Voo 2 7 to 5 5 V 1300 1 8 to 5 5 V 3800 SCK high low level width 2 7 to 5 5 V 1 2 50 Voo 1 8 to 5 5 V 1 2 150 SINete1 setup time to SCKT Voo 2 7 to 5 5 V 150 1 8 to 5 5 V 500 51 1 hold time from SCKT Voo 2 7 to 5 5 V 400 1 8 to 5 5 V 5 output delay time from SCKL R 1 kQ C 100 2 2 7 to 5 5 V 1 8 to 5 5 V Notes 1 n 2 wire serial mode read this parameter as SBO or SB1 instead 2 are the load resistance and load capacitance of the SO output lines respectively 2 wire and 3 wire serial I O mode SCK External clock input TA 40 to 85 C Vpp 1 8 to 5 5 V Parameter SCK cycle time 2 7 to 5 5 V Test Conditions 1 8 to 5 5 V SCK high low level width tkL2 tkH2 2 7 to 5 5 V 1 8 to 5 5 V SINote1 setup time to SCKT 2 7 to 5 5 V 1 8 to 5 5 V SI ete hold time from SCKT 2 7 to 5 5 V 1 8 to 5 5 V
3. 1 8 to 5 5 V Operating ambient temperature Ta 40 to 85 C Package 80 pin plastic QFP 14 20 80 pin plastic QFP 14 x 14 80 pin plastic TQFP Fine pitch 12 x 12 64 pin plastic QFP 14 x 14 64 pin plastic LQFP 12x 12 64 pin plastic TQFP 12 12 64 plastic LQFP 14 x 14 64 pin plastic QFP 14 x 14 64 pin plastic LOFP 12 x 12 64 pin plastic LOFP 14 x 14 Data Sheet U11369EJ3VODS 55 APPENDIX B DEVELOPMENT TOOLS NEC uPD75P3116 The following development tools have been provided for system development using the wPD75P31 16 In the 75XL Series a common relocatable assembler is used in combination with a device file dedicated to each model RA75X relocatable assembler Device file Host Machine OS Supply Medium Part Number Product Name PC 9800 Series 5 57 Ver 3 30 to J Ver 6 2Note 3 5 2HD uS5A13RA75X IBM or compatibles Host Machine Refer to OS for IBM PCs 3 5 2HC OS Supply Medium 87 13 75 Part Number Product Name PC 9800 Series MS DOS Ver 3 30 to Ver 6 2Note 3 5 2HD US5A13DF753108 IBM PC AT or compatibles Refer to OS for IBM PCs 3 5 2HC uS7B13DF753108 Note Ver 5 00 and later include a task swapping function but this function cannot be used in this software Remark
4. lt 1 IME IPS 3 0 control IExxx lt 0 lt PORTn 0 to 3 5 6 8 9 lt PORTn 1 PORTn n 8 IExxx NNote 1 A PORTn XA PORTn OUT PORTn A PORTn XA PORTn lt n 2 to 3 5 6 8 9 PORTn 1 PORTn n 8 Set HALT Mode PCC 2 1 Set STOP Mode PCC 3 lt 1 CPU control N 2 1 N N II N DM PY No Operation RBS lt n n 0 to 3 MBS lt n n 0 1 15 Special N N N GETIN es 3 When using TBR instruction PC13 0 lt taddr 5 0 taddr 1 When using TCALL instruction SP 4 SP 1 SP 2 lt PC11 0 SP 3 MBE 13 12 PC13 0 lt taddr 5 0 taddr 1 When using instruction other than Determined by TBR or TCALL referenced Execute taddr taddr 1 instructions instruction When using TBR instruction PC13 0 lt taddr 5 0 taddr 1 When using TCALL instruction SP 6 SP 3 SP 4 lt PC11 0 5 lt 0 0 PC13 12 2 lt X X MBE PC13 0 lt taddr 5 0 taddr 1 When using instruction other than Determined by TBR or TCALL referenced Execute taddr taddr 1 instructions instruction Notes 1 Setting MBE 0 or MBE 1 MBS 15 is required during the execution of the IN or OUT instruction 2 The TBR and TCALL instructions are ass
5. 1 output delay time from SCKL Notes 1 n 2 wire serial I O mode read this parameter as SBO or SB1 instead 2 and are the load resistance and load capacitance of the SO output lines respectively 38 R 1 C 100 2 2 7 to 5 5 V 1 8 to 5 5 V Data Sheet U11369EJ3VODS NEC uPD75P3116 SBI mode SCK Internal clock output master Ta 40 to 85 C Voo 1 8 to 5 5 V Parameter SCK cycle time Voo 2 7 to 5 5 V Test Conditions 1300 1 8 to 5 5 V 3800 SCK high low level width 2 7 to 5 5 V 2 50 1 8 to 5 5 V 2 150 580 1 setup time to SCKT Voo 2 7 to 5 5 V 150 1 8 to 5 5 V 500 580 1 hold time from SCKT tkcva 2 SBO 1 output delay time from SCK R 1 100 pFNete 2 7 to 5 5 V 0 1 8 to 5 5 V 0 580 14 from SCKT SCK from SBO 11 SBO 1 low level width 580 1 high level width Note RL and C are the load resistance and load capacitance of the SBO and 581 output lines respectively SBI mode SCK External clock input slave TA 40 to 85 C Vpp 1 8 to 5 5 V Parameter SCK cycle time Voo 2 7 to 5 5 V Test Conditions 800 1 8 to 5 5 V 3200 SCK high l
6. When set to Mk II mode 753104 753106 and 753108 Caution The MkII mode supports a program area exceeding 16 KB for the 75X and 75XL Series Therefore this mode is effective for enhancing software compatibility with products that have a program area of more than 16 KB With regard to the number of stack bytes during execution of subroutine call instructions the usable area increases by 1 byte per stack compared to the mode when the Mk II mode is selected However when the CALL addr and CALLF faddr instructions are used the machine cycle becomes longer by 1 machine cycle Therefore if more emphasis is placed on RAM use efficiency and processing performance than on software compatibility the Mk mode should be used 14 Data Sheet U11369EJ3VODS NEC uPD75P3116 4 2 Setting of Stack Bank Selection SBS Register Use the stack bank selection register to switch between the mode Mk II mode Figure 4 1 shows the format of the stack bank selection register The stack bank selection register is set using a 4 bit memory manipulation instruction When using the mode be sure to initialize the stack bank selection register to 100xB at the beginning of the program When using the Mk II mode be sure to initialize it to 000 Note Set the desired value for x Figure 4 1 Format of Stack Bank Selection Register Address 3 2 1 0 Symbol 3833 8882 5851 5850 585 Stac
7. 32 Data Sheet U11369EJ3VODS NEC uPD75P3116 Main System Clock Oscillator Characteristics Ta 40 to 85 C Vpp 1 8 to 5 5 V Resonator Ceramic resonator Recommended Constant Parameter Test Conditions Oscillation 6 QNote 2 frequency fx Nete 1 Oscillation After reaches oscil stabilization timeNete lation voltage range MIN Crystal resonator Oscillation 6 QNote 2 frequency fx Nete 1 Oscillation Voo 4 5 to 5 5 V 10 stabilization timeNete 3 1 8 to 5 5 V 30 External clock Notes 1 2 Caution X1 input 6 0 2 frequency fx Nete 1 X1 input high low level width txt Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time When the power supply voltage is 1 8 V lt lt 2 7 V and the oscillation frequency is 4 19 MHz lt fx 6 0 MHz setting the processor clock control register 0011 makes 1 machine cycle less than the required 0 95 us Therefore set PCC to a value other than 0011 The oscillation stabilization time is necessary for oscillation to stabilize after applying Vpp or releasing the STOP mode When using the main system clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wir
8. D H L X H L DE HL DE HL BC DE XA BC DE HL XA BC DE HL BC DE HL XA BC DE HL HL HL HL DE DL DE DL 4 bit immediate data or label 8 bit immediate data or label 8 bit immediate data or labelNete 2 bit immediate data or label FBOH to FBFH FFOH to FFFH immediate data or label FCOH to FFFH immediate data or label 0000H to 3FFFH immediate data or label 0000H to 3FFFH immediate data or label Mk Il mode only 12 bit immediate data or label 11 bit immediate data or label 20H to 7FH immediate data however bit 0 0 or label Port 0 to Port 3 Port 5 Port 6 Port 8 Port 9 IEBT IECSI IETO to IET2 IEO to IE2 IE4 IEW RBO to RB3 MBO MB1 MB15 Note When processing 8 bit data only even numbered addresses can be specified Data Sheet U11369EJ3VODS 19 NEC uPD75P3116 2 Operation conventions A A register 4 bit accumulator B B register C C register D D register E E register H H register L L register X X register XA Register pair XA 8 bit accumulator BC Register pair BC DE Register pair DE HL Register pair HL XA Expansion register pair XA BC Expansion register pair BC DE Expansion register pair DE HL Expansion register pair HL PC Program counter SP Stack pointer CY Carry flag bit accumulator PSW Program status wor
9. MD2 P32 68 MD3 P33 46 Data Sheet U11369EJ3VODS NEC uPD75P3116 10 CHARACTERISTIC CURVES REFERENCE VALUES lob vs Main System Clock 6 0 MHz Crystal Resonator Ta 25 C 5 0 PCC 0011 0010 0001 PCC 0000 Main system clock HALT mode 32 kHz oscillation 0 5 e Subsystem clock operation mode SOS 1 0 Main system clock STOP mode 32 kHz oscillation 0 05 SOS 1 0 and subsystem clock HALT mode SOS 1 0 Main system clock STOP mode 32 kHz oscillation 505 1 1 and subsystem clock HALT mode SOS 1 1 Supply current mA 0 01 0 005 XT2 Crystal resonator 32 768 kHz 0 001 Supply voltage Voo V Data Sheet U11369EJ3VODS 47 NEC 75 116 loo vs Voo Main System Clock 4 19 MHz Crystal Resonator Ta 25 C 10 5 0 PCC im 0010 PCC 0001 PCC 0000 1 0 Main system clock 0 5 mode 32 kHz oscillation 0 1 Subsystem clock operation mode 505 1 0 Supply current lop mA Subsystem clock HALT mode main system clock STOP mode 32 kHz oscillation SOS 1 0 Main system clock STOP mode 32 kHz oscillation 505 1 1 and
10. A reg1 lt regi rp lt gt rp Table XA PCDE lt PC13 8 DE ROM reference XA PCXA lt PC13 8 XA ROM XA QBCDE ete lt BCDE ROM XA QBCXANete lt BCXA ROM Note Only the lower 3 bits in the register are valid 22 Data Sheet U11369EJ3VODS NEC uPD75P3116 Instruction Group Bit transfer Mnemonic Operand CY fmem bit Machine Cycle Operation CY lt fmem bit Addressing Area Skip Condition CY pmem QL CY lt pmem7 2 L3 2 bit L1 0 CY H mem bit CY lt H mems 0 bit fmem bit CY fmem bit lt CY pmem L CY pmem7 2 L3 2 bit L1 0 CY H mem bit CY H mems o bit CY Arithmetic A n4 lt 4 8 lt 8 A HL A lt A HL XA rp lt rp 1 lt 1 A HL A CY A HL CY XA rp lt XA rp CY rp rp 1 CY lt 1 A HL lt A HL borrow XA rp XA lt XA rp borrow 1 1 lt rp1 XA borrow A HL A lt A HL CY XA rp lt 1 rp 1 lt rp1 XA CY A n4 lt 4 A G HL A A HL XA rp lt XA rp
11. 1 XA 1 lt 1 XA A n4 A Avn4 A HL A A v HL XA rp XA lt XA v rp 1 XA 1 lt rp 1 v XA A n4 G HL A A v HL XA rp XA lt v rp 1 XA 1 lt 1 v XA Accumulator manipulation A CY c Ao lt CY 1 A lt Increment decrement reg lt reg 1 reg 0 lt 1 1 1 00H HL HL 1 HL 2 0 mem lt 1 0 reg lt reg 1 reg FH rp lt 1 Data Sheet U11369EJ3VODS rp 23 Instruction Group Comparison Mnemonic Operand reg n4 Machine Cycle Operation Skip if reg n4 Addressing Area NEC uPD75P3116 Skip Condition HL n4 Skip if HL n4 A HL Skip if A HL XA HL Skip if XA HL A reg Skip if A reg XA rp Skip if XA rp Carry flag manipulation CY CY 1 CY CY 0 CY Skip if CY 1 CY CY lt CY Memory bit manipulation 24 mem bit mem bit lt 1 fmem bit fmem bit 1 pmem 91 pmem7 2 L3 2 bit L1 0 lt 1 H mem bit mem bit mem bit 0 fmem bit fmem bit 0 pmem 91 pmem7 2 L3 2 bit L1 0 0 H mem
12. 0 303 10 02 0 394 P 14 92 0 587 Q 111 0 437 R 1 45 0 057 S 1 45 0 057 T 4 01 3 4 00 051 U 1 8 0 071 5 0 0 197 w 95 3 0 209 x 4 C 1 0 4 C 0 039 Y 93 55 0 140 7 0 9 00 035 62 Data Sheet U11369EJ3VODS NEC uPD75P3116 Notes on Target System Design The following shows a diagram of the connection conditions between the emulation probe conversion connector and conversion socket or conversion adapter Design your system making allowances for conditions such as the form of parts mounted on the target system as shown below Table B 1 Distance Between In Circuit Emulator and Conversion Socket Emulation Probe Conversion Socket Distance Between In Circuit Emulator Conversion Adapter and Conversion Socket or Conversion Adapter EP 753108GC R EV 9200GC 64 EP 753108GK R TGK 064SBW Figure B 4 Distance Between In Circuit Emulator and Conversion Socket or Conversion Adapter 1 In circuit emulator IE 75001 R d Target system TS a a 0 Emulation probe 70 03 F LE Conversion socket EV 9200GC 64 DIN connector CN5 Figure B 5 Distance Between In Circuit Emulator and Conversion Socket or Conversion Adapter 2 In circuit emulator IE 75001 R 700 mm Target system p E Emulation probe EP 753108GK R Conversion adapter TGK 064SBW DIN connector CN5 Dat
13. 4 0 1 0 125 0 075 5 5 Z r Ax lt Ts gt 1 7 MAX P64GK 65 8A8 3 NEC 64 PLASTIC LQFP 14x14 uPD75P3116 detail of lead end rS NOTE Each lead centerline is located within 0 20 mm of its true position T P at maximum material condition Data Sheet U11369EJ3VODS ITEM MILLIMETERS A 17 2 0 2 14 0 0 2 14 0 0 2 17 2 0 2 1 0 1 0 0 08 0 37507 0 20 0 8 T P 1 6 0 2 0 8 0 03 0 1779 06 0 10 1 4 0 1 0 127 0 075 4 3 3e 1 7 MAX 0 25 C I GO TS o m 0 886 0 15 P64GC 80 8BS 51 NEC uPD75P3116 12 RECOMMENDED SOLDERING CONDITIONS The uPD75P3116 should be soldered and mounted under the conditions recommended in the table below For details of recommended soldering conditions refer to the information document Semiconductor Device Mounting Technology Manual C10535E For soldering methods and conditions other than those recommended below contact an NEC Sales representative Table 12 1 Surface Mounting Type Soldering Conditions 1 2 1 uPD75P3116GC AB8 64 pin plastic QFP 14 x 14 Soldering Soldering Conditions Recommended Method Condition Symbol Infrared reflow Package peak temperature 235 C
14. 65 RH or less for the allowable storage period Caution Do not use different soldering methods together except for partial heating 52 Data Sheet U11369EJ3VODS NEC uPD75P3116 Table 12 1 Surface Mounting Type Soldering Conditions 2 2 3 uPD75P3116GC 8BS 64 pin plastic LQFP 14 x 14 Soldering Soldering Conditions Recommended Method Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max at 210 C or higher IR35 00 2 Count Twice or less VPS Package peak temperature 215 C Time 40 seconds max at 200 C or higher VP15 00 2 Count Twice or less Wave soldering Solder bath temperature 260 C max Time 10 seconds max Count Once WS60 00 1 Preheating temperature 120 C max package surface temperature Partial heating Pin temperature 300 C max Time 3 seconds max per pin row Caution Do not use different soldering methods together except for partial heating Data Sheet U11369EJ3VODS 53 NEC uPD75P3116 APPENDIX A LIST OF 75308 753108 AND 75P3116 FUNCTIONS Parameter uPD75308B 753108 uPD75P3116 Program memory Mask ROM 0000H to 1F7FH 8064 x 8 bits Mask ROM 0000H to 1FFFH 8192 x 8 bits One time PROM 0000H to 3FFFH 16384 x 8 bits Data memory 000H to 1FFH 512 x 4 bits CPU 75X Standard 75XL CPU Instruction execution When main system clock is selected 0 95 1 91 15 3
15. NEC uPD75P3116 6 MEMORY CONFIGURATION Figure 6 1 Program Memory Map 1 1 0000H Internal reset start address higher 6 bits Internal reset start address lower 8 bits 0002H INTBT INT4 start address higher 6 bits INTBT INT4 start address lower 8 bits CALLF faddr instruction 0004H INTO start address higher 6 bits entry address INTO start address lower 8 bits 0006H INT1 start address higher 6 bits INT1 start address lower 8 bits BRCB 0008H INTCSI start address higher 6 bits INTCSI start address lower 8 bits Branch addresses for 000AH INTTO start address higher 6 bits TO E NES INTTO start address lower 8 bits 000 INTT1 INTT2 start address higher 6 bits CALLA laddr1Nete BR BCDE INTT1 INTT2 start address lower 8 bits BR BCXA Reference table for GETI instruction Branch call address by GETI QNSE e BR addr instruction 0020H 007FH 0080H relative branch address 715 to 1 42 to 16 0800H US secu tte ee A Y 1000H BRCB Icaddr instruction branch address WEE E EIE 2 7 0 Y 2000H BRCB Icaddr instruction branch address 2FFFH S S S S S S LLL Y 3000H BRCB instruction branch address 3FFFH Y Note Can only be used in the Mk II mode Remark Forinstructions ot
16. Retention Timing Standby Release Signal STOP Mode Release by Interrupt Signal STOP mode STOP instruction execution HALT mode m 4 Operating mode retention mode e Standby release signal Interrupt request 44 Data Sheet U11369EJ3VODS NEC uPD75P3116 DC Programming Characteristics Ta 25 5 C Voo 6 0 0 25 V VPP 12 5 0 3 V Vss 0 V Parameter Input voltage high Test Conditions Except X1 and X2 pins X1 X2 Input voltage low Except X1 and X2 pins X1 X2 Input leakage current Vin Vit or Output voltage high lou 1 mA Output voltage low lo 1 6 mA Voo power supply current power supply current Cautions 1 Do not exceed 13 5 V for VPP including the overshoot MDO MD1 Vin 2 must be applied before VPP and cut after VPP AC Programming Characteristics TA 25 5 C 6 0 10 25 V 12 5 10 3 V Vss 0 Parameter Address setup timeNete to MDOJ Test Conditions MD1 setup time to MDOJ Data setup time to MDOL Address hold timeNete from MDOT Data hold time from MDOT Data output float delay time from MDOT VPP setup time to MD3T Voo setup time to MD37 Initial program pulse width Additional program pulse width MDO setup time to MD1
17. Time 30 seconds max at 210 C or higher IR35 00 3 Count Three times or less VPS Package peak temperature 215 C Time 40 seconds max at 200 C or higher VP15 00 3 Count Three times or less Wave soldering Solder bath temperature 260 C max Time 10 seconds max Count Once WS60 00 1 Preheating temperature 120 C max package surface temperature Partial heating Pin temperature 300 C max Time 3 seconds max per pin row Caution Do not use different soldering methods together except for partial heating 2 uPD75P3116GK 8A8 64 pin plastic LQFP 12 x 12 Soldering Soldering Conditions Recommended Method Condition Symbol Infrared reflow Package peak temperature 235 C Time 30 seconds max at 210 C or higher IR35 107 2 Count Twice or less Exposure limit 7 days e after that prebake at 125 C for 10 hours Package peak temperature 215 C Time 40 seconds max at 200 C or higher VP15 107 2 Count Twice or less Exposure limit 7 daysNe e after that prebake at 125 C for 10 hours Wave soldering Solder bath temperature 260 C max Time 10 seconds max Count Once WS 60 107 1 Preheating temperature 120 C max package surface temperature Exposure limit 7 daysNe e after that prebake at 125 C for 10 hours Partial heating Pin temperature 300 C max Time 3 seconds max per pin row Note After opening the dry pack store it at 25 C or less and
18. bit H mems o bit lt 1 H mems o bit 0 mem bit Skip if mem bit 1 mem bit 1 fmem bit Skip if fmem bit 1 fmem bit 1 pmem L Skip if pmem7 2 L3 2 bit L1 0 1 pmem L 1 H mem bit Skip if H mems o bit 1 H mem bit mem bit Skip if mem bit 0 fmem bit Skip if fmem bit 0 fmem bit 0 pmem L Skip if pmem7 2 L3 2 bit L1 0 0 pmem L H mem bit Skip if H mems o bit 0 mem bit H mem bit SKTCLR fmem bit Skip if fmem bit 1 and clear fmem bit 1 pmem L Skip if pmem7 2 L3 2 bit L1 0 1 and clear H mem bit Skip if H mems o bit 1 and clear pmem 21 1 H mem bit CY fmem bit CY lt CY A fmem bit CY pmem L CY H mem bit lt CY pmem7 2 L3 2 bit L1 0 lt CY a H mema o bit CY fmem bit CY lt CY v fmem bit CY pmem L CY H mem bit CY lt v pmem7 2 L3 2 bit L1 0 CY lt CY v H mems 0 bit CY fmem bit CY lt CY fmem bit CY pmem QL CY lt v pmem7 2 L3 2 bit L1 0 CY H mem bit NI N N N N CY lt CY v H mems 0 bit Data Sheet U11369EJ3VODS NEC uPD75P3116 Instruction Mnemonic Operand Machine Operation Addressing Skip Cycle Area Conditi
19. grade as indicated below Customers must check the quality grade of each semiconductor product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster Systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC semiconductor products is Standard unless otherwise expressly specified in NEC s data sheets or data books etc If customers wish to use NEC semiconductor products in applications not intended by NEC they must contact an NEC sales representative in advance to determine NEC s willingness to support a given application Note 1 NEC as used in this statement means NEC Corporation and also includes its majority owned subsidiaries 2 NEC semiconductor products means any semiconductor product developed or manufactured by or for NEC as defined above 8 00 4
20. screening Storage Temperature NEC offers QTOP microcontrollers for which one time PROM writing marking screening and verification are provided at additional cost For further details contact an NEC sales representative Data Sheet U11369EJ3VODS 31 NEC 75 116 9 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Ta 25 C Parameter Test Conditions Power supply voltage 0 3 to 7 0 PROM power supply 0 3 to 13 5 voltage Input voltage Except port 5 0 3 to 0 3 Port 5 N ch open drain 0 3 to 14 Output voltage 0 3 to 0 3 Output current high Per pin 10 Total of all pins 30 Output current low Per pin 30 Total of all pins 220 Operating ambient 40 to 85Note temperature Storage temperature 65 to 150 Note When LCD is driven in normal mode Ta 10 to 85 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter That is the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded Capacitance Ta 25 C 0 Test Conditions Input capacitance f 1 MHz Output capacitance Unmeasured pins returned to 0 V capacitance
21. to PTO2 Programmable timer output 0 to 2 P90 to P93 Port 9 BUZ Buzzer clock KRO to KR3 Key return 0 to PCL Programmable clock SCK Serial clock INTO 1 4 External vectored interrupt 0 1 4 SI Serial input INT2 External test input 2 SO Serial output X1 X2 Main system clock oscillation 1 2 SBO SB1 Serial data bus 0 1 XT1 XT2 Subsystem clock oscillation 1 2 RESET Reset VPP Programming power supply to Mode selection 0 to 3 Positive power supply DO to D7 Data bus 0 to 7 Vss Ground 50 to S23 Segment output 0 to 23 Data Sheet U11369EJ3VODS 5 NEC 2 BLOCK DIAGRAM INTW interval timer watchdog timer TIO P130 PTOO P20 o 8 bit timer event counter 0 INTTO TOUTO INTT1 11 12 8 bit P12 INT2 timer event Cascaded 1 210 1 counter 1 16 bit L timer PTO2 PCL P22 SI SB1 P03 0 Clocked SO SBO0 P02 o serial SCK P01 o interface INTCSI TOUTO INT1 INTO P100 1 11 4 Interrupt 2 12 1 2 control P60 KRO to P63 KR3 Bit sequential buffer 16 Program counter 14 General purpose register Program memory PROM Decode 16384 x 8 bits and control memory RAM 512 x 4 bits Port 0 4 Port 1 4 Port 2 4 Port 3 4 Port 5 4 Port 6 4 Port 8 4 Port 9 4
22. 00GC 64 Package Drawing For Reference Only A F HNO x E 10 1 lt E No 1 pin index LP EV 9200GC 64 G0E ITEM MILLIMETERS INCHES A 18 8 0 74 B 14 1 0 555 C 14 1 0 555 D 18 8 0 74 E 4 C 3 0 4 C 0 118 F 0 8 0 031 G 6 0 0 236 H 15 8 0 622 18 5 0 728 9 6 0 0 236 K 15 8 0 622 L 18 5 0 728 M 8 0 0 315 N 7 8 0 307 2 5 0 098 2 0 0 079 Q 1 35 0 053 R 0 35 0 1 0 014 0 005 s 2 3 90 091 T 91 5 90 059 60 Data Sheet U11369EJ3VODS NEC uPD75P3116 Figure B 2 EV 9200GC 64 Recommended Footprint For Reference Only EV 9200GC 64 P1E ITEM MILLIMETERS INCHES A 19 5 0 768 B 14 8 0 583 C 0 850 02 x 15 12 0 0 05 0 031 000 x 0 591 0 47270 002 D 0 8 0 02 x 15 12 0 0 05 0 031 000 x 0 591 0 47210 003 E 14 8 0 583 F 19 5 0 768 G 6 0050 08 0 236 2 003 H 6 00 0 08 0 23609 0 5 0 02 0 197 0007 J 2 36 0 03 90 093090 K 2 2 0 1 0 087 0005 L 1 57 0 03 0 062 9 9 Caution Dimensions of mount pad for EV 9200 and that for target DEVICE Data Sheet U11369EJ3VODS device QFP may be different in some parts For the recommended mount pad dimensions for QFP refer to SE
23. 1 SP 2 PC11 0 SP 3 lt MBE PC13 12 PC13 0 lt 000 faddr SP lt SP 4 SP 6 SP 3 SP 4 lt PC11 0 SP 5 lt 0 0 PC13 12 2 lt X X MBE PC13 0 lt 000 faddr SP lt SP 6 RETNete MBE PC13 12 lt SP 1 PC11 0 lt SP SP 3 SP 2 SP SP 4 X X MBE lt SP 4 PC11 0 SP SP 3 SP 2 0 0 PC13 12 SP 1 SP lt SP 6 RETSNete MBE PC13 12 SP 1 Unconditional 11 lt SP SP 3 SP 2 SP lt 4 then skip unconditionally X X MBE lt SP44 PC11 0 lt SP SP 3 SP 2 0 0 PC13 12 lt SP 1 SP lt SP 6 then skip unconditionally RETINete MBE PC13 12 SP 1 PC11 0 lt SP SP 3 SP 2 PSW lt SP 4 SP 5 SP SP 6 0 0 PC13 12 lt SP 1 PC11 0 lt SP SP 3 SP 2 PSW lt SP 4 SP 5 SP SP 6 Note The sections in double boxes are only supported in the Mk II mode The other sections are only supported in the mode 26 Data Sheet U11369EJ3VODS NEC PD75P3116 Instruction Mnemonic Operand Machine Operation Addressing Skip Group Cycle Area Condition Subroutine SP 1 SP 2 lt rp SP lt SP 2 stack control SP 1 MBS SP 2 RBS SP SP 2 lt SP 1 SP SP lt SP 2 MBS lt SP 1 RBS SP SP SP 2 IME IPS 3 1 Interrupt
24. 6 C1 C2 22 pF HALT mode 5 0 V 10 3 0 V 10 32 768 kHz ete Low voltage 3 0 10 Crystal oscillation modeNete 8 2 0 V 10 Voo 3 0 V Ta 25 C Low current Voo 3 0 V 10 consumption modeNete 9 3 0 V TA225 C 3 0 V 210 HALT mode ow voltage 2 0 V 10 modeNete 8 Vo 3 0 V Ta 25 C Low 3 0 V 10 current consump Voo 3 0 V tion mode _ 25 C Note 9 XT1 0 VNete 10 Vpp 5 0 V 10 STOP mode 8 0 V 40 to 85 C TUS Ta 25 Notes 1 Set to VACO 0 when the low current consumption mode and the stop mode are used If VACO 1 is set the current increases for approx 1 uA 2 The voltage deviation is the difference from the output voltage corresponding to the ideal value of the segment and common outputs Vicpn n 0 1 2 3 Not including currents flowing through on chip pull up resistors 4 Including oscillation of the subsystem clock 5 Whenthe processor clock control register PCC is set to 0011 and the device is operated in the high speed mode 6 When PCC is set to 0000 and the device is operated in the low speed mode 7 When the system clock control register SCC is set to 1001 and the device is operated on the subsystem clock with main system clock oscillation stopped 8 When the s
25. DATA SHEET MOS INTEGRATED CIRCUIT uPD75P3116 4 BIT SINGLE CHIP MICROCONTROLLER The uPD75P3116 replaces the 753108 5 internal mask ROM with a one time PROM and features expanded ROM capacity Because the uPD75P3116 supports programming by users it is suitable for use in evaluation of systems in the development stage using the 753104 753106 or 753108 and for use small scale production Detailed information about functions is provided in the following User s Manual Be sure to read it before designing 753108 User s Manual U10890E FEATURES Compatible with 753108 Memory capacity PROM 16384 x 8 bits RAM 512 x 4 bits Can be operated in same power supply voltage range as the mask version uPD753108 e 1 8 to 5 5 V On chip LCD controller driver Q QTOP microcontroller Remark QTOP microcontrollers are microcontrollers with on chip one time PROM that are totally supported by NEC This support includes writing application programs marking screening and verification ORDERING INFORMATION Part Number Package uPD75P3116GC AB8 64 pin plastic QFP 14 x 14 LPD75P3116GK 8A8 64 pin plastic LQFP 12 x 12 uPD75P3116GC 8BS 64 plastic LQFP 14 x 14 Caution This device does not provide an internal pull up resistor connection function by means of mask option The information in this document is subject to change without notice Before using this document p
26. MICONDUCTOR TECHNOLOGY MANUAL C10535E MOUNTING 61 NEC uPD75P3116 Package Drawing of Conversion Adapter TGK 064SBW Figure B 3 TGK 064SBW Package Drawing For Reference Only A RI K Ss 1 i t H Bee MES e 9 qp G F E D1 HI J 4 Si oe 4 4 Z H 1 a m 9 2 5 am Kt ji h TT TTT u LEET di il ZEN bi LED HE J ITEM MILLIMETERS INCHES ITEM MILLIMETERS INCHES A 18 4 0 724 a 0 3 0 012 B 0 65x15 9 75 0 02610 591 0 384 b 1 85 0 073 0 65 0 026 3 5 0 138 D 7 75 0 305 d 2 0 0 079 E 10 15 0 400 e 3 9 0 154 F 12 55 0 494 f 1 825 0 052 G 14 95 0 589 g 1 825 0 052 H 0 65x15 9 75 0 026x0 591 0 384 h 5 9 0 232 I 11 85 0 467 i 0 8 0 031 J 18 4 0 724 j 24 0 094 K C 2 0 C 0 079 k 27 0 106 L 12 45 0 490 TGK 064SBW G1E M 10 25 0 404 N 77
27. Operation of the assembler and device file is guaranteed only when using the host machine and OS described above 56 Data Sheet U11369EJ3VODS NEC PROM Write Tools Hardware PG 1500 uPD75P3116 This is a PROM writer that can program a single chip microcontroller with PROM in stand alone mode or under the control of a host machine when connected with the supplied accessory board and optional programmer adapter It can also program typical PROMs in capacities ranging from 256 Kb to 4 Mb PA 75P3116GC This is a PROM programmer adapter for the uPD75P3116GC AB8 It can be used when connected to the PG 1500 PA 75P3116GK This is a PROM programmer adapter for the uPD75P3116GK 8A8 It can be used when connected to the PG 1500 PA 75P3116GC 8BS This is a PROM programmer adapter for the uPD75P3116GC 8BS It can be used when connected to the PG 1500 Software PG 1500 controller Connects the PG 1500 to the host machine via serial and parallel interfaces and controls the PG 1500 on the host machine Host machine Part number Product name Supply medium PC 9800 Series MS DOS 3 5 2HD Ver 3 30 to Ver 6 2Nete LS5A138PG1500 IBM PC AT or compatible Refer to OS for IBM PCs 3 5 2HD HS7B13PG1500 Note Ver 5 00 and later include a task swapping function but this function cannot be used in this software Remark Operation of the PG 1500 controller is guaranteed only when us
28. Pins 1 2 Pin Name Alternate Function Status Circuit Function After Reset TypeNete P13 External event pulse input to timer event counter P12 INT2 TI2 P12 INT2 TI1 P20 Timer event counter output P21 P22 PCL P22 PTO2 Clock output P23 Frequency output for buzzer or system clock trimming SCK P01 Serial clock I O K SO SBO P02 Serial data output Serial data bus I O SI SB1 Serial data input Serial data bus I O INT4 POO Edge detection vectored interrupt input valid for detecting both rising and falling edges INTO P10 Edge detection vectored interrupt With noise eliminator input detection edge is selectable asynchronous is INTO P10 can be used to select a selectable limi INT1 P11 Asynchronous INT2 12 11 2 Rising edge detection testable input Asynchronous KRO to P60 to P63 Parallel falling edge detection testable input X1 Ceramic crystal resonator connection for main system clock oscillation If using an external clock input the signal 2 to X1 and input the inverted signal to X2 XT1 Crystal resonator connection for subsystem clock oscillation If using an external clock input the signal to XT1 and input XT2 the inverted signal to XT2 XT1 can be used as a 1 bit test input RESET System reset input low level active MDO to P30 to P33 Mode selection for program memory PROM write
29. Se fx 2N CPU clock System clock Clock generator Standby divider Sub control Clock output control fLCD RM O O O PCL PTO2 P22 X1 X2 XT1XT2 Data Sheet U11369EJ3V0DS s o 2 o z 5 o Vss VPP RESET PD75P3116 POO to P10 to P20 to P23 P30 MDO to P33 MD3 P50 D4 to P53 D7 P60 DO to P63 D3 P80 to P83 P90 to P93 SO to S15 S16 P93 to 519 90 S20 P83 to S23 P80 COMO to COM3 OBIAS O VLCO O VLC1 O VLC2 SYNC P31 LCDCL P30 NEC PD75P3116 3 PIN FUNCTIONS 3 1 Port Pins 1 2 Pin Name yo Alternate Function i Status Circuit Function After Reset Type ete INT4 4 bit input port Port 0 Connection of an internal pull up resistor can be SCK specified by a software setting in 3 bit units SO SBO SI SB1 INTO 4 bit input port Port 1 Connection of an internal pull up resistor can be INT1 specified by a software setting in 4 bit units P10 INTO can be used to select a noise eliminator TH TI2 INT2 a 10 P13 TIO P20 PTOO 4 bit port Port 2 P23 P30 Connection of an internal pull up resistor can be PTO1 specified by a software setting in 4 bit units PCL PTO2 BUZ LCDCL MDO Programmable 4 bit I O port Port 3 Input and output can be specified in 1 bit units SYNC MD1 Connection of an internal pu
30. T Data output delay time from tov 01 Vit MD1 hold time from MDOT MD1 recovery time from MDOJ 1 1 twin gt 50 us Program counter reset time tPcR X1 input high low level width tx X1 input frequency fx Initial mode set time ti setup time to MD1T hold time from MD1J setup time to MDOJ During program memory read Data output delay time from Address ete During program memory read Data output hold time from AddressNete During program memory read MD3 hold time from MDOT During program memory read Data output float delay time from During program memory read Note The internal address signal is incremented by 1 at the rising edge of the fourth X1 input is not connected to a pin Data Sheet U11369EJ3VODS 45 NEC uPD75P3116 Program Memory Write Timing xi DO P60 to D3 P60 D4 P50 to D7 P53 Data input 2 Data output tos MDO P30 MD1 P31 MD2 P32 MD3 P33 Program Memory Read Timing tves amp _ xi fe tx D4 P50 to D7 P53 Data output Data output lE toFR t a MD0 P30 MD1 P31 P WA iPcR
31. U12622bE Language U12385E Structured Assembler Preprocessor 012598 Documents Related to Development Tools Hardware User s Manuals Document Name Document No 75000 75001 In Circuit Emulator EEU 1455 IE 75300 R EM Emulation Board U11354E EP 753108GC R EP 753108GK R Emulation Probe EEU 1495 Documents Related to PROM Writing User s Manuals Document Name Document No PG 1500 PROM Programmer U11940E PG 1500 Controller PC 9800 Series MS DOS Based EEU 1291 IBM PC Series PC DOS Based U10540E Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document for designing Data Sheet U11369EJ3VODS 65 NEC uPD75P3116 Other Related Documents Document Name Document No SEMICONDUCTOR SELECTION GUIDE Products amp Packages X13769E Semiconductor Device Mounting Technology Manual C10535E Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge ESD 11892 Caution The related documents listed above are subject to change without notice Be sure to use the latest version of each document for designing 66 Data Sheet U11369EJ3VODS NEC uPD75P3116 MEMO Data Sheet U11369EJ3VODS 67 NEC uPD75P3116 NOTES FOR CMOS DE
32. VICES D PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins itis possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Inputlevels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to or GND with a resistor if it is considered to have a possibility of being an output pin All handli
33. a Sheet U11369EJ3VODS 63 uPD75P3116 NEC Figure B 6 Connection Conditions of Target System 1 64 pin GC EP 753108GC R Iig 2 TIT In circuit emulator 75001 External sense clips Conversion socket EV 9200GC 64 Target system Figure B 7 Connection Conditions of Target System 2 Ground clip 7 A A 22 64 pin GK A EP 753108GK R III Mi Z 4 2 8 8 In circuit emulator 9 mm 1 I I IE 75001 R External sense clips Notch Conversion adapter TGK 064SBW Fd n JE 13 8 mm J y 34 mm Pe d 18 4 mm 34 mm Notch Target system Data Sheet U11369EJ3VODS 64 NEC uPD75P3116 APPENDIX C RELATED DOCUMENTS The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Documents Related to Devices Document Name Document No 753104 753106 753108 Data Sheet U10086E uPD75P3116 Data Sheet This document 753108 User s Manual U10890E 75XL Series Selection Guide U10453E Documents Related to Development Tools Software User s Manuals Document Name Document No RA75X Assembler Package Operation
34. a registered trademark or a trademark of Microsoft Corporation in the United States and or other countries IBM DOS PC AT and PC DOS are trademarks of International Business Machines Corporation The export of this product from Japan is regulated by the Japanese government To export this product may be prohibited without governmental license the need for which must be judged by the customer The export or re export of this product from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative The information in this document is current as of November 2001 The information is subject to change without notice For actual design in refer to the latest publications of NEC s data sheets or data books etc for the most up to date specifications of NEC semiconductor products Not all products and or types are available in every country Please check with an NEC sales representative for availability and additional information No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC NEC assumes no responsibility for any errors that may appear in this document NEC does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of s
35. bytes Mask ROM 4096 Mask ROM 6144 Mask ROM 8192 One time PROM 16384 Data memory x 4 bits 512 Mask options Pull up resistor for Port 5 Split resistor for LCD driving power supply Available On chip not on chip can be specified Not available Not on chip Wait time after RESET Available Selectable between 2 7 fx and 215 fx Nete Not available Fixed to 215 fx Nete Feedback resistor of subsystem clock Available Use not use can be selected Not available Enable Pin configuration Pins 5 to 8 P30 to P33 P30 MDO to P33 MD3 Pins 10 to 13 P50 to P53 P50 D4 to P53 D7 Pins 14 to 17 P60 KRO to P63 KR3 P60 KRO DO to P63 KR3 D3 Pin 21 IC VPP Note Noise resistance and noise radiation may differ due to the different circuit sizes and mask layouts 2 21 8 ms at 6 0 MHz operation 31 3 ms at 4 19 MHz operation 2 5 fx 5 46 ms at 6 0 MHz operation 7 81 ms at 4 19 MHz operation Caution There are differences in the amount of noise tolerance and noise radiation between flash memory versions and mask ROM versions When considering changing from a flash memory version to a mask ROM version during the process from experimental manufacturing to mass production make sure to sufficiently evaluate commercial samples CS not engineering samples ES of the mask ROM versions 16 Data Sheet U11369EJ3VODS
36. chine cycles required for skipping skip specified instructions The value of S varies as shown below Note 3 byte instructions BR addr BRA addr1 CALL addr and CALLA addr1 Caution The GETI instruction is skipped for one machine cycle One machine cycle equals one cycle tcv of the CPU clock Use the PCC setting to select from among four cycle times Data Sheet U11369EJ3VODS 21 NEC uPD75P3116 Instruction Mnemonic Operand Machine Operation Addressing Skip Group Cycle Area Condition Transfer A n4 Ac n4 String effect A regi n4 reg1 n4 XA 408 lt n8 String effect 18 HL n8 String effect B n8 lt n8 A HL A HL A HL A lt HL then L L 1 A HL A lt HL then L amp L 1 A 1 lt rpat HL HL HL A HL lt HL XA HL XA A mem A mem XA mem mem lt lt rp lt reg XA rp reg1 A 1 XA A QG HL A HL XA HL HL reg1 A m m m j rnmj rnmij rnmj rnmj rnm j rm N N IPNI 1 lt XA lt HL then L 1 1 HL then L L 1 lt mem mem
37. current high X1 XT1 13 V Port 5 N ch open drain Input leakage VN 20V Pins other than X1 XT1 and Port 5 current low X1 XT1 Port 5 N ch open drain When another instruction than input instruction is executed Port 5 Voo 1 8 to 5 5 V N ch open drain When input 5 0 V instruction is executed Voo 3 0 V Output leakage Vout SO SBO SB1 Ports 2 3 6 8 and 9 current high Vout 13 V Port 5 N ch open drain Output leakage Vout 0 V current low On chip pull up resistor Vn 0 V Ports 0 1 2 3 6 8 and 9 Excluding pin Data Sheet U11369EJ3VODS 35 NEC 75 3116 DC Characteristics TA 40 to 85 1 8 to 5 5 V Parameter Test Conditions LCD drive voltage Ta 40 to 85 C Ta 10 to 85 C VACO 1 currentNete 1 VACO 1 2 0 V 10 LCD output voltage lo 1 0 uA Vicpo 2 common Vicbi Vico x 2 3 LCD output voltage lo 0 5 uA Vicp2 Vico x 1 3 deviation ete segment 1 8 V Vico lt Supply currentNete 3 6 00 MHzNete 4 5 0 V 10 Notes Crystal oscillation 3 0 V 10 Note C1 C2 22 pF HALT mode 5 0 V 10 Voo 3 0 V 10 4 19 MHzNete 4 5 0 V 10 Note 5 Crystal oscillation 3 0 V 4109606
38. d MBE Memory bank enable flag RBE Register bank enable flag PORTn Port n n 0 to 3 5 6 8 9 IME Interrupt master enable flag IPS Interrupt priority selection register Interrupt enable flag RBS Register bank selection register MBS Memory bank selection register PCC Processor clock control register Delimiter for address and bit xx Data addressed with xx xxH Hexadecimal data 20 Data Sheet U11369EJ3VODS NEC uPD75P3116 3 Description of symbols used in addressing area MB MBE MBS MBS 0 1 15 MB 0 000H to 07FH Data memory MB 15 F80Hto FFFH addressing MB MBS MBS 0 1 15 MB 15 fmem FBOH to FBFH FFOH to FFFH MB 15 pmem FCOH to FFFH addr 0000H to SFFFH addr addr1 Current PC 15 to Current PC 1 Current PC 2 to Current PC 16 caddr 0000H to OFFFH PCs 12 00B 1000H to 1FFFH PC13 12 01B Program memory 2000H to 2FFFH PC13 12 10B or addressing 3000H to 3FFFH PC13 12 11B faddr 0000H to 07FFH taddr 0020H to 007FH addr1 0000H to II mode only Remarks 1 MB indicates access enabled memory banks 2 In area 2 MB 0 for both MBE and MBS 3 In areas 4 and 5 MB 15 for both MBE and MBS 4 Areas 6 to 11 indicate corresponding address enabled areas 4 Description of machine cycles S indicates the number of ma
39. e following operation modes can be specified by setting pins MDO to MD3 as shown below Operation Mode Specification Operation Mode MDO MD1 MD2 Zero clear program memory address Write mode Verify mode Program inhibit mode x Lor H 28 Data Sheet U11369EJ3VODS NEC uPD75P3116 8 2 Program Memory Write Procedure Program memory can be written at high speed using the following procedure 1 Pull down unused pins to Vss via resistors Set the X1 pin to low 2 Supply 5 V to the Voo and Vr pins 3 Wait 10 us 4 Select the program memory address zero clear mode 5 Supply 6 V to and 12 5 V to 6 Write data in the 1 ms write mode Select the verify mode If the data is written go to 8 and if not repeat 6 and 7 8 Additional write X Number of write operations from 6 and 7 x 1 ms 9 Apply four pulses to the X1 pin to increment the program memory address by one Repeat 6 to 9 until the end address is reached Select the program memory address zero clear mode Return the Voo and Ver pin voltages to 5 V 7 1 i j lt He 0 1 2 3 Turn off the power The following figure shows steps 2 to 9 X repetitions Additional Address Write Verify write increment VPP pK LL OO VPP VDD 1 T T C 1 1 0 1 Vpp VDD X1 0 00 60 to D3 P63 Data D4 P50 to D7 P53 2 Data input gt ob
40. e potential as Vpp Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator The subsystem clock oscillator is designed as alow amplification circuitto provide low consumption current and is more liable to misoperation by noise than the main system clock oscillator Special care should therefore be taken regarding the wiring method when the subsystem clock is used 34 Data Sheet U11369EJ3VODS NEC uPD75P3116 DC Characteristics TA 40 to 85 C 1 8 to 5 5 V Parameter Test Conditions Output current low Per pin Total of all pins Input voltage high Ports 2 3 8 and 9 2 7 lt lt 5 5 V 1 8 lt Voo lt 2 7 V Ports 0 1 6 RESET 2 7 lt 5 5 V 1 8 lt Voo lt 2 7 V Port 5 2 7 lt 5 5 V N ch open drain 1 8 lt Vop 2 7 V X1 XT1 Input voltage low Ports 2 3 5 8 and 9 2 7 lt lt 5 5 V 1 8 lt 2 7 V Ports 0 1 6 RESET 2 7 lt 5 5 V 1 8 lt Voo lt 2 7 V X1 XT1 Output voltage high SCK SO Ports 2 3 6 8 and 9 lou 1 0 mA Output voltage low SCK SO Ports 2 3 5 6 8 9 lo 15 mA 4 5 to 5 5 V lt lt lt lt lt lt lt lt lt lt lt lt lt lt lo 1 6 mA When N ch open drain pull up resistor 2 1 Input leakage Pins other than X1 XT1
41. ed for future system expansion Currently only P30 and P31 are used 10 Data Sheet U11369EJ3VODS N E PD75P3116 3 3 Pin I O Circuits The circuits for the uPD75P3116 s pins are shown in abbreviated form below VDD Id Data H P ch OUT disable 777 Push pull output that can be set to high impedance output CMOS standard input buffer with both P ch and N ch OFF p 4E Data IN OUT Output disable Schmitt triggered input with hysteresis characteristics P U R Pull Up Resistor P U R P U R enable H P U R lt enable Data IN OUT Output disable O lt Type B P U R Pull Up Resistor P U R Pull Up Resistor Continued Data Sheet U11369EJ3VODS 11 NEC Output disable po P Data Output disable 12 P U R enable p 4E VDD ag P ch Output disable N gt P U R Pull Up Resistor IN OUT Data Output disable Output disable D75P3116 Continued IN OUT O PE P ch N ch HK P U R f gt Pech 777 P U R Pull Up Resistor N ch 13 V withstand ing voltage Voltage controller 413 V IN OUT o r _ IN OUT withstanding voltage Note Pull up resistor that operates only w
42. embler quasi directives for the GETI instruction table definitions 3 The sections in double boxes are only supported in the Mk Il mode The other sections are only supported in the Mk mode Data Sheet U11369EJ3VODS 27 NEC uPD75P3116 8 ONE TIME PROM PROGRAM MEMORY WRITE AND VERIFY The program memory contained in the uPD75P3116 is a 16384 x 8 bit one time PROM that can be electrically written one time only The pins listed in the table below are used for this PROM s write verify operations Clock input from the X1 pin is used instead of address input as a method for updating addresses Function VPP Pin where program voltage is applied during program memory write verify usually Vpp potential X1 X2 Clock input pins for address updating during program memory write verify Input the X1 pin s inverted signal to the X2 pin to Operation mode selection pin for program memory write verify DO P60 to D3 P63 8 bit data pins for program memory write verify lower 4 bits D4 P50 to D7 P53 higher 4 bits VDD Pin where power supply voltage is applied Apply 1 8 to 5 5 V in normal operation mode and 6 V for program memory write verify Caution Pins not used for program memory write verify should be connected to Vss 8 1 Operation Modes for Program Memory Write Verify When 6 V is applied to the Vpp pin and 12 5 V to the VPP the uPD75P3116 enters the program memory write verify mode Th
43. er 4 4 1 13 4 xe 4 SCK tsik3 4 gt SBO 1 tksos 4 Command signal transfer SCK tsik3 4 gt SBO 1 4 Interrupt input timing INTL 1 2 4 KRO to 7 RESET input timing tRSL RESET 42 Data Sheet U11369EJ3VODS NEC uPD75P3116 Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics Ta 40 to 85 Symbol Test Conditions Release signal set time Oscillation stabilization Release by RESET wait timeNete 1 Release by interrupt request Notes 1 Theoscillation stabilization wait time is the time during which the CPU operation is stopped to prevent unstable operation at the start of oscillation 2 Depends on the basic interval timer mode register BTM settings see the table below BTM2 BTM1 Wait Time fx 2 4 19 MHz 220 fx approx 2 fx approx 175 ms 2 7 fx approx 2 fx approx 21 8 ms 2 5 fx approx 2 5 fx approx 5 46 ms 2 3 fx approx 2 3 fx approx 1 37 ms Data Sheet U11369EJ3VODS 43 NEC Data Retention Timing STOP Mode Release by RESET Internal reset operation HALT mode STOP instruction execution uPD75P3116 STOP mode _ Data retention mode gt lt gt gt Operating mode RESET N Data
44. hen an input instruction is executed The current flows from to a pin when the pin is at low level Data Sheet U11369EJ3VODS NEC uPD75P3116 3 4 Recommended Connection of Unused Pins Table 3 1 List of Unused Pin Connections POO INT4 Recommended Connection Connect to Vss or VDD 1 5 P02 SO SBO Input Independently connect Vss or Vpp via a resistor Output Leave open POS SI SB1 Connect to Vss P10 INTO and P11 INT1 12 1 2 2 P13 TIO Connect to Vss or VDD P20 PTOO P21 PTO1 P22 PTO2 PCL P23 BUZ P30 LCDCL MDO P31 SYNC MD1 P32 MD2 P33 MD3 Input Independently connect Vss or Vpp via a resistor Output Leave open P50 D4 to P53 D7 Connect to Vss Connect to Vss Input Output P60 KRO0 DO to P63 KR3 D3 Input Output Independently connect Vss or via a resistor Leave open SO to 515 COMO to COM3 Leave open S16 P93 to S19 P90 S20 P83 to S23 P80 Input Independently connect Vss via a resistor Output Leave open Vico to 2 Connect to Vss BIAS Connect Vss only when of or Vic2 is used In other cases leave open XT1 Note Connect to Vss XT2Nete Leave open Note When the subsystem resistor not used Always connect Vo
45. her than those noted above the BR PCDE and BR PCXA instructions can be used to branch to addresses with changes in the PC s lower 8 bits only Data Sheet U11369EJ3VODS 17 NEC uPD75P3116 Figure 6 2 Data Memory Map Data memory Memory bank 000H uc a General purpose register area 01FH 020H Stack areaNote Data area static RAM OFFH 512 x 4 100H 1DFH 1E0H Display data memory 1F7H 1F8H Y Y 1FFH Not incorporated F80H 22400 Peripheral hardware area 128x4 15 Y FFFH Y Note Memory bank 0 or 1 can be selected as the stack area 18 Data Sheet U11369EJ3VODS NEC uPD75P3116 7 INSTRUCTION SET 1 Representation and coding formats for operands In the instruction s operand area use the following coding format to describe operands corresponding to the instruction s operand representations for further details refer to the RA75X Assembler Package Language User s Manual U12385E When there are several codes select and use just one Codes that consist of uppercase letters and or symbols are keywords that should be entered as they are For immediate data enter an appropriate numerical value or label Enter register flag symbols as label descriptors instead of mem fmem bit etc for further details refer to the User s Manual The number of labels that can be entered for fmem and pmem are restricted Representation Coding Format X
46. ing the host machine and OS described above Data Sheet U11369EJ3VODS 57 NEC uPD75P3116 Debugging Tools An in circuit emulator 75001 is provided as a program debugging tool for the uPD75P3116 The system configuration using this in circuit emulator is shown below Hardware IE 75001 R The 75001 is emulator to be used for hardware and software debugging during development of application systems using the 75X or 75XL Series products The IE 75001 R is used in combination with an emulation board IE 75300 R EM and emulation probe EP 753108GC R or EP 753108GK R both sold separately Highly efficient debugging can be performed when connected to the host machine and PROM programmer IE 75300 R EM This is an emulation board for evaluating application systems using the uPD75P3116 It is used in combination with the IE 75001 R EP 753108GC R This is an emulation probe for the wPD75P3116GC When being used it is connected with the IE 75001 R and the IE 75300 R EM EV 9200GC 64 It includes a 64 pin conversion socket EV 9200GC 64 to facilitate connection with the target system EP 753108GK R This is an emulation probe for the PD75P3116GK When being used it is connected with the IE 75001 R and the IE 75300 R EM TGK 064SBW Itincludes a 64 pin conversion adapter TGK 064SBW to facilitate connection with the target Note 1 system Software IE control program This p
47. ing with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the same potential as Do not ground the capacitor to a ground pattern through which a high current flows Do not fetch signals from the oscillator Data Sheet U11369EJ3VODS 33 NEC uPD75P3116 Subsystem Clock Oscillator Characteristics TA 40 to 85 Vpp 1 8 to 5 5 V Resonator Recommended Constant Parameter Test Conditions Crystal Oscillation resonator frequency fxr Nete 1 Oscillation Voo 4 5 to 5 5 V stabilization timeNete 2 1 8 to 5 5 External XT1 input frequency clock fxr Nete 1 XT1 input high low level width txrL Notes 1 Indicates only oscillator characteristics Refer to AC Characteristics for instruction execution time 2 The oscillation stabilization time is necessary for oscillation to stabilize after applying Caution Whenusing the subsystem clock oscillator wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance Keep the wiring length as short as possible Do not cross the wiring with the other signal lines Do not route the wiring near a signal line through which a high fluctuating current flows Always make the ground point of the oscillator capacitor the sam
48. k area specification F84H Memory bank 0 Memory bank 1 Setting prohibited 0 Be sure to enter 0 for bit 2 Mode selection specification Mk II mode mode Caution SBS3is set to 1 after RESET input and consequently the CPU operates in the mode When using instructions for the Mk Il mode set 5853 to 0 and set the Mk II mode before using the instructions Data Sheet U11369EJ3VODS 15 5 DIFFERENCES BETWEEN 4PD75P3116 AND uPD753104 753106 753108 NEC uPD75P3116 The uPD75P3116 replaces the internal mask ROM the 753104 753106 and 753108 with a one time PROM and features expanded ROM capacity The uPD75P31 16 s Mk I mode supports the Mk mode in the uPD753104 753106 and 753108 and the uPD75P3116 s Mk 1 mode supports the Mk II mode in the uPD753104 753106 and 753108 Table 5 1 lists differences between the 75 116 and the uPD753104 753106 and 753108 Be sure to check the differences between these products before using them with PROMs for debugging or prototype testing of application systems or later when using them with a mask ROM for full scale production For details of the CPU functions and internal hardware refer to the User s Manual Table 5 1 Differences Between uPD75P3116 and 753104 753106 and 753108 Program counter uPD753104 12 bits uPD753106 13 bits 753108 75 116 14 bits Program memory
49. lease confirm that this is the latest version Not all devices types available in every country Please check with local NEC representative for availability and additional information Document U11369EJ3VODSO0 3rd edition Date Published March 2002 N CP K The mark shows major revised points Printed in Japan Corporation 1994 FUNCTION OUTLINE NEC uPD75P3116 Item Function Instruction execution time 0 95 1 91 3 81 15 3 us main system clock 4 19 MHz 0 67 1 33 2 67 or 10 7 us main system clock 6 0 MHz 122 us subsystem clock O 32 768 kHz Internal memory PROM 16384 x 8 bits RAM 512 x4 bits General purpose registers ports CMOS input 4 bit manipulation 8 x 4 banks 8 bit manipulation 4 x 4 banks Internal pull up resistor connection can be specified by software setting 7 CMOS I O N ch open drain I O Internal pull up resistor connection can be specified by software setting 12 Shared with segment pins 8 13 V withstanding voltage Total LCD controller driver Segment number selection 16 20 24 segments switchable to CMOS I O ports in a batch of 4 pins max 8 pins Static 1 2 duty 1 2 bias 1 3 duty 1 2 bias 1 3 duty 1 3 bias 1 4 duty 1 3 bias Display mode selection 5 channels 8 bit timer event counter 3 channels Can be used as 16 bit timer event counter carrier generator and timer wi
50. ll up resistor can be specified by a software setting in 4 bit units MD2 P33 MD3 P5ONote 2 D4 N ch open drain 4 bit port Port 5 High When set to open drain the withstanding voltage impedance 2 Notes 1 Circuit types enclosed in angle brackets indicate Schmitt triggered input 2 The low level input leakage current increases when input instructions or bit manipulation instructions are executed Data Sheet U11369EJ3VODS 7 NEC uPD75P3116 3 1 Port Pins 2 2 Pin Name Alternate Function Status Circuit Function After Reset TypeNete KRO DO Programmable 4 bit I O port Port 6 Input and output can be specified in 1 bit units KR1 D1 Connection of an internal pull up resistor can be specified by a software setting in 4 bit units KR2 D2 KR3 D3 S23 4 bit I O port Port 8 Connection of an internal pull up resistor can be 522 specified by a software setting in 4 bit 2 S21 S20 519 Programmable 4 bit I O port Port 9 Connection of an internal pull up resistor can be 518 specified by a software setting in 4 bit unitsNete2 517 516 Notes 1 Circuit types enclosed angle brackets indicate Schmitt triggered input 2 Do not connect an internal pull up resistor by software when these pins are used as segment signal outputs 8 Data Sheet U11369EJ3VODS NEC PD75P3116 3 2 Non Port
51. ng related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function 68 Data Sheet U11369EJ3VODS NEC uPD75P3116 Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify Device availability e Ordering information Product release schedule Availability of related technical literature Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to coun
52. o directly clock is not used select 505 0 1 on chip feedback Data Sheet U11369EJ3VODS 13 4 MkIAND Mk II MODE SELECTION FUNCTION NEC uPD75P3116 Setting the stack bank selection SBS register for the 75 116 enables the program memory to be switched between the Mk mode Mk II mode This function is applicable when using the uPD75P3116 to evaluate the 753104 753106 or 753108 When bit 3 of SBS is set to 1 Sets the Mk mode supports the Mk mode for the 753104 753106 and 753108 When bit 3 of SBS is set to 0 Sets the Mk II mode supports the Mk II mode for the 753104 753106 and 753108 4 1 Differences Between Mode and Mk Il Mode Table 4 1 lists the differences between the mode and the Mk II mode for the uPD75P31 16 Table 4 1 Differences Between Mode and Mk Il Mode Item Mk Mode Mk II Mode Program counter PC13 0 Program memory bytes 16384 Data memory bits 512x4 Stack Stack bank Selectable via memory banks 0 and 1 No of stack bytes 2 bytes 3 bytes BRA addr1 instruction CALLA addr1 instruction Instruction Not available Available Instruction CALL addr instruction 3 machine cycles 4 machine cycles execution time CALLF faddr instruction 2 machine cycles 3 machine cycles Supported mask ROM products When set to Mk mode 753104 753106 753108
53. on Group BRNetet PC13 0 lt addr Use the assembler to select the most appropriate instruction among the following BR addr BRCB caddr BR addr PC12 0 lt addr1 Use the assembler to select the most appropriate instruction among the following BRA addr1 BR addr BRCB caddr BR addr1 laddr 3 0 addr addr 3 0 lt addr addr1 3 0 lt PCDE 3 0 lt PC13 84 DE PCXA 3 0 lt PC13 8 XA 3 0 lt 3 0 lt BCXAwNete2 BRA e1 laddr1 3 0 lt addr1 BRCB Icaddr 3 0 lt PC13 12 caddr11 0 Notes 1 The sections in double boxes are only supported in the Mk Il mode The other sections are only supported in the MK I mode 2 Only the lower two bits in the B register are valid Data Sheet U11369EJ3VODS 25 NEC uPD75P3116 Instruction Mnemonic Operand Machine Operation Addressing Skip Group Cycle Area Condition Subroutine CALLANete SP 6 SP 3 SP 4 lt PC11 0 stack control 5 lt 0 0 PC13 12 SP 2 lt X X MBE PC13 0 lt addr1 SP lt SP 6 CALL Note SP 4 SP 1 SP 2 PC11 0 3 lt MBE PC13 12 PC13 0 lt addr SP lt SP 4 SP 6 SP 3 SP 4 lt 1 0 5 lt 0 0 PC13 12 SP 2 X X MBE RBE PC13 0 lt addr SP lt SP 6 SP 4 SP
54. ow level width Voo 2 7 to 5 5 V 400 1 8 to 5 5 V 1600 SBO 1 setup time to SCKT Voo 2 7 to 5 5 V 100 1 8 to 5 5 V 150 580 1 hold time from SCKT tkcv4 2 SBO 1 output delay time from SCKL R 1 100 pFNete 2 7 to 5 5 V 0 1 8 to 5 5 V 0 580 14 from SCKT from SBO 14 580 1 low level width 580 1 high level width Note RL and C are the load resistance and load capacitance of the SBO and SB1 output lines respectively Data Sheet U11369EJ3VODS 39 NEC uPD75P3116 AC Timing Test Points Excluding X1 XT1 Input MIN MIN MAX MAX MIN MIN Vo MAX Vor MAX Clock Timing 1 fx a tx X1 input vc UM 0 1V a 1 fxr input 0 1V TIO 1 TI2 Timing 1 fn tri TIO TH 40 Data Sheet U11369EJ3VODS NEC uPD75P3116 Serial Transfer Timing 3 wire serial I O mode tkcy1 2 SCK tsik1 2 tksi1 2 SI 2 wire serial I O mode tkcy1 2 tkL1 2 2 lt SCK tksi1 2 580 1 tkso1 2 Data Sheet U11369EJ3VODS 41 NEC uPD75P3116 Serial Transfer Timing Bus release signal transf
55. resistor for LCD driver 54 3 channels Basic interval timer 1 channel 8 bit timer event counter 1 channel Watch timer 1 channel Data Sheet U11369EJ 5 channels Basic interval timer watchdog timer 1 channel 8 bit timer event counter 3 channels can be used as 16 bit timer event counter Watch timer 1 channel 3VODS NEC Parameter Clock output PCL uPD75308B 524 262 65 5 kHz Main system clock during 4 19 MHz operation uPD75P3116 uPD753108 uPD75P3116 524 262 65 5 kHz Main system clock during 4 19 MHz operation 750 375 93 8 kHz Main system clock during 6 0 MHz operation BUZ output BUZ 2 kHz Main system clock during 4 19 MHz operation 2 4 32 kHz Main system clock during 4 19 MHz operation or subsystem clock during 32 768 kHz operation 2 98 5 86 46 9 kHz Main system clock during 6 0 MHz operation Serial interface 3 modes are available e 3 wire serial I O mode MSB LSB can be selected for transfer first bit 2 wire serial I O mode SBI mode SOS register Feedback resistor cut flag SOS 0 None Contained Sub oscillator current cut flag SOS 1 None Contained Register bank selection register RBS None Yes Standby release by INTO Vectored interrupts No External 3 Internal 3 Yes External 3 Internal 5 Supply voltage Vpp 2 0 to 6 0 V
56. rogram can control the IE 75001 R on a host machine when connected to the IE 75001 R via an RS 232C or Centronics interface Host machine Part number Product name OS Supply medium PC 9800 Series MS DOS 3 5 2HD LS5A13IE75X Ver 3 30 to Ver 6 2Note 2 IBM PC AT Refer to OS for 3 5 2HC uS7B13IE75X or compatible IBM PCs Notes 1 This is a product of TOKYO ELETECH CORPORATION Contact Daimaru Kogyo Ltd Tokyo Electronic Department TEL 81 3 3820 7112 Osaka Electronic Department TEL 81 6 6244 6672 2 Ver 5 00 and later include a task swapping function but this function cannot be used in this software Remarks 1 Operation of the IE control program is guaranteed only when using the host machine and OS described above 2 The uPD753104 753106 753108 and 75P3116 generically called the uPD753108 Subseries 58 Data Sheet U11369EJ3VODS NEC OS for IBM PCs The following operating systems for IBM PCs are supported PC DOS Version Ver 3 1 to 6 3 J6 1 V ete to J6 3 VNote MS DOS Ver 5 0 to 6 2 5 0 VNet to 6 2 V Note IBM DOS J5 02 VNote Note Only English mode is supported uPD75P3116 Caution Ver 5 0 and later include a task swapping function but this function cannot be used in this software Data Sheet U11369EJ3VODS 59 NEC uPD75P3116 Package Drawing and Recommended Footprint of Conversion Socket EV 9200GC 64 Figure B 1 EV 92
57. subsystem clock HALT mode SOS 1 1 0 01 0 005 Crystal resonator 32 768 25 330 0 001 0 Supply voltage Voo V 48 Data Sheet U11369EJ3VODS NEC uPD75P3116 11 PACKAGE DRAWINGS 64 PIN PLASTIC 14x14 detail of lead end rS e NIS ITEM MILLIMETERS Each lead centerline is located within 0 15 mm of A 17 6 0 4 its true position T P at maximum material condition B 14 0 0 2 14 0 0 2 17 6 0 4 1 0 1 0 0 08 0 3779 07 0 15 0 8 T P 1 8 0 2 0 8 0 2 0 08 0 1779 07 ro nT 0 10 2 55 0 1 0 1 0 1 b xb 2 85 MAX P64GC 80 AB8 5 lt Data Sheet U11369EJ3VODS 49 NEC x 64 PIN PLASTIC LQFP 12x12 NOTE Each lead centerline is located within 0 13 mm of its true position T P at maximum material condition 50 Data Sheet U11369EJ3VODS detail of lead end gt uPD75P3116 ITEM MILLIMETERS 14 8 0 4 12 0 0 2 12 0 0 2 14 8 0 4 1 125 1 125 0 32 0 08 0 13 0 65 1 4 0 2 0 6 0 2 0 08 0 177007 0 10 1
58. th gate Basic interval timer watchdog timer 1 channel Watch timer 1 channel Serial interface Bit sequential buffer BSB 3 serial I O mode MSB LSB first switchable 2 wire serial I O mode SBI mode 16 bits Clock output PCL 524 262 and 65 5 kHz main system clock 4 19 MHz 750 375 and 93 8 kHz main system clock 9 6 0 MHz Buzzer output BUZ 2 4 and 32 kHz main system clock 4 19 MHz or subsystem clock 32 768 kHz 2 93 5 86 46 9 kHz main system clock 6 0 MHz Vectored interrupts External 3 Internal 5 Test inputs External 1 Internal 1 System clock oscillator Standby function Ceramic crystal oscillator for main system clock Crystal oscillator for subsystem clock STOP HALT mode Power supply voltage 1 8 to 5 5 64 pin plastic QFP 14 x 14 64 pin plastic LQFP 12 x 12 64 pin plastic LQFP 14 x 14 Data Sheet U11369EJ3VODS NEC uPD75P3116 CONTENTS 1 PIN CONFIGURATION TOP 4 22 BLOCK DIAGRAM Pese E TRUM 6 3 PIN FUNCTIONS mE 7 PortiPinS u EE 7 3 2 Non Port PIDS L 586545 Ra 9 3 3 Pin VO EA 11 3 4 Recommended Connection of Unused Pins I U U u u uuu uu u
59. try NEC Electronics Inc U S Santa Clara California Tel 408 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC do Brasil S A Electron Devices Division Guarulhos SP Brasil Tel 11 6462 6810 Fax 11 6462 6829 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65 03 01 Fax 0211 65 03 327 e Branch The Netherlands Eindhoven The Netherlands Tel 040 244 58 45 Fax 040 244 45 80 Branch Sweden Taeby Sweden Tel 08 63 80 820 Fax 08 63 80 388 NEC Electronics France S A V lizy Villacoublay France Tel 01 3067 58 00 Fax 01 3067 58 99 NEC Electronics France S A Representacion en Espana Madrid Spain Tel 091 504 27 87 Fax 091 504 28 60 NEC Electronics Italiana S R L Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 Data Sheet U11369EJ3VODS NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 6841 1138 Fax 021 6841 1137 NEC Electronics Taiwan Lid Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 253 8311 Fax 250 3583 J02 3 69 NEC uPD75P3116 QTOP is a trademark of NEC Corporation MS DOS is either
60. ub oscillator control register SOS is set to 0000 9 When SOS is set to 0010 10 When SOS is set to 00x1 and the feedback resistor of the sub oscillator is not used x Don t care 36 Data Sheet U11369EJ3VODS NEC uPD75P3116 AC Characteristics TA 40 to 85 C Vpp 1 8 to 5 5 V Parameter Test Conditions CPU clock cycle Operating on Vpp 2 7 to 5 5 V timeNete 1 main system clock 1 8 to 5 5 V Min instruction execution Operating on subsystem clock time 1 machine cycle TIO TI1 TI2 input 2 7 to 5 5 V frequency Voo 1 8 to 5 5 V TIO TI2 input trig tin 2 7 to 5 5 V high low level width Von 1 8 to 5 5 V Interrupt input high tintH INTO low level width INT1 2 4 KRO to KR7 RESET low level width Notes 1 Thecycletime minimum instruction execution time of the CPU clock is determined by the oscillation frequency of the connected resonator and external clock the system clock control register SCC and the processor clock control Guaranteed operation register PCC The figure on the range right indicates the cycle time tcy versus supply voltage characteristics with the main system tcv vs Main system clock operation clock operating Cycle time tcv us 2 2icvor 128 fx is set by setting the interrupt mode register IMO
61. uch products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC or others Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of customer s equipment shall be done under the full responsibility of customer NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features NEC semiconductor products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to semiconductor products developed based on a customer designated quality assurance program for a specific application The recommended applications of a semiconductor product depend on its quality
62. us during 4 19 MHz operation 0 95 1 91 3 81 15 3 us during 4 19 MHz operation 0 67 1 33 2 67 10 7 us during 6 0 MHz operation ume When subsystem clock is selected SBS register 122 us during 32 768 kHz o None peration SBS 3 1 Mk I mode selection 585 3 0 II mode selection Stack area 000H to 000H to 1FFH Subroutine call instruc tion stack operation 2 byte stack When Mk mode When II mode 2 byte stack 3 byte stack BRA addr1 CALLA Instruction MOVT XA BCDE MOVT XA BCXA BR BCDE BR BCXA Unavailable When Mk mode When II mode Unavailable Available Available CALL addr 3 machine cycles Mk mode II mode 3 machine cycles 4 machine cycles CALLF faddr 2 machine cycles Mk mode II mode 2 machine cycles 3 machine cycles ports CMOS input 8 CMOS Bit port output N ch open drain I O Total LCD controller driver Segment selection 24 28 32 can be changed to CMOS port in 4 bit units max Segment selection 16 20 24 segments can be changed to CMOS I O port in 4 bit units max 8 8 Display mode selection Sta tic 1 2 duty 1 2 bias 1 3 duty 1 2 bias 1 3 duty 1 8 bias 1 4 duty 1 3 bias On chip split resistor for LCD driver can be specified by using mask option No on chip split
63. uu uuu u T J 13 4 MkIAND Mk Il MODE SELECTION FUNCTION 14 4 1 Differences Between Mk Mode and Mk Il 14 4 2 Setting of Stack Bank Selection SBS Register U u u uuu uuu uu uuu u 15 5 DIFFERENCES BETWEEN 4PD75P3116 AND 753104 753106 753108 16 6 MEMORY CONFIGURATION 17 7 INSTRUCTION SET u ll ee ea nen ERO Ck utente cp aaepe kes iya 19 8 ONE TIME PROM PROGRAM MEMORY WRITE AND VERIFY 28 8 1 Operation Modes for Program Memory Write Verify U U u uuu uu uu u 28 8 2 Program Memory Write Procedure 29 8 3 Program Memory Read Procedure 30 8 4 One Time PROM Screening sinn s stus 31 9 ELECTRICAL SPECIFICATIONS 32 10 CHARACTERISTIC CURVES REFERENCE VALUES 47 11 PACKAGE DRAWINGS educ e ck 49 12 RECOMMENDED SOLDERING CONDITIONS 52 APPENDIX LIST OF 75308 753108 AND 75P3116 54 APPENDIX B DEVELOPMENT TOOLS
64. verify DO to D3 P60 KRO to P63 KR3 Data bus for program memory PROM write verify D4 to D7 P50 to P53 VppNote 2 Programmable power supply voltage applied for program memory PROM write verify During normal operation connect directly to Apply 12 5 V for PROM write verify Positive power supply Ground potential Notes 1 Circuit types enclosed in angle brackets indicate Schmitt triggered input 2 The VPP pin does not operate correctly when it is not connected to the Vpp pin during normal operation Data Sheet U11369EJ3VODS 9 NEC PD75P3116 3 2 Non Port Pins 2 2 Pin Name y o Alternate Function Status Circuit Function After Reset Type S0 to 515 Segment signal output 16 to 519 P93 to P90 Segment signal output S20 to S23 P83 to P80 Segment signal output COMO to COM3 Output Common signal output Vico to 2 Power supply for driving LCD BIAS Output for external split resistor cut LCDCLNete 3 Output P30 MDO Clock output for driving external expansion driver Output P31 MD1 Clock output for synchronization of external expansion driver Notes 1 Vicx X 0 1 2 is selected as the input source for the display outputs as shown below 50 to S23 Vici COMO to 2 Vice COM3 Vico 2 When the split resistor is incorporated Low level When the split resistor is not incorporated High impedance 3 These pins are provid
65. wbs F input X 7 X 7 N lt lt lt K N N MD1 P31 N n s MD2 P32 MD3 P33 lt Data Sheet U11369EJ3V0DS 29 NEC uPD75P3116 8 3 Program Memory Read Procedure The uPD75P3116 can read program memory contents using the following procedure 1 Pull down unused pins to Vss via resistors Set the X1 pin to low Supply 5 V to the and VPP pins Wait 10 us 4 Select the program memory address zero clear mode Supply 6 V to and 12 5 V to VPP Selectthe verify mode Apply four pulses to the X1 pin The data stored in one address will be output every four clock pulses 7 Select the program memory address zero clear mode 8 Return the Voo and Vre pin voltages to 5 V 9 Turn off the power The following figure shows steps 2 to 7 VPP VPP VDD 1 Vpp VDD xi N NININININININININGAN D0 P60 to D3 P63 Data output D4 P50 to D7 P53 Dale output 00 0 N SS MD1 P31 MD2 P32 Y MD3 P33 N 30 Data Sheet U11369EJ3VODS NEC uPD75P3116 8 4 One Time PROM Screening Due to its structure the one time PROM cannot be fully tested before shipment NEC Therefore NEC recommends that after the required data is written and the PROM is stored under the temperature and time conditions shown below the PROM should be verified via

NEC uPD75P3116 User's Manual

Contents

Download Pdf Manuals

Related Search

Related Contents