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NEC PD750008 User's Manual

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1. 62 Carry Flag Manipulation INStruCuOns x eo ete 63 Information Indicated by the Interrupt Status Flag 64 Register Bank to Be Selected with the RBE and 66 Typos and Features OF EE a un eid 68 I O Pin Manipulation Instructions ones edo teta rte eoo ren ede ena esu edo du edes Ee nts 78 Operations by I O Port Manipulation 80 Specification of Built in Pull Up Resistors 81 Maximum Time Required to Change the System Clock and CPU Clock 94 Resolution and Longest Setup nennen nnns 117 Serial Clock Selection and Application In the Three Wire Serial 1 0 Mode 140 Serial Clock Selection and Application In the Two Wire Serial I O Mode 148 Serial Clock Selection and Application In the SBI 160 Various Signals Used in the SBI 165 IVETE SOU CCS coca ar techie 185 Set Signals for Interrupt Request 888 188 Interrupt Processing Statuses of ISTO and 5 1 194 Identifying Interrupt Sharing Vector Table Address
2. 198 FESC OONO M n 210 Signals Setting Test Request 05 8 210 Table No 7 1 7 2 8 1 10 1 LIST TABLES 2 2 Title Page Operation Statuses in the Standby 216 Selection Walt Ume wih B EM 219 Status of the Hardware after a 226 selecindgVlask ODUOD OF PIN Fm koc 235 X MEMO CHAPTER 1 GENERAL The 0750004 uPD750006 uPD750008 and uPD75P0016 are 75XL series 4 bit single chip microcom puters The 75XL series is a successor of the 75X series consisting of many products These uPD750004 uPD750006 uPD750008 and uPD75P0016 are collectively called the uPD750008 subseries The 75XL series takes over the CPUs of the 75X series realizing a wide range of operating voltages and high speed operation In addition to having upward compatibility with existing products the 75XL series is best suited for battery driven applications The 0750004 uPD750006 0750008 uPD75P0016 have the following features Operable on low voltage Vpp 2 2 to 5 5 V Switchable instruction execution times useful for high speed operation and power saving 0 95 us 1 91 us 3 81 us 15 3 Us at 4 19 MHz 0 67 us 1 33 us 2 67 us 10 7 us at 6 0 MHz 122 us at 32 768 kHz Enhanced timers 4 c
3. its de 230 92 WRITING TO THE PROGRAM MEMORY 230 9 3 READING THE PROGRAM MEMORY 232 9 4 SCREENING OF ONE TIME 233 CHAPTER 10 MASK OPTION tices catacacseacsescenddtevventwcawanvereussvdndeesscatveceustasneucsacadewteatsinwastataraieeeds 235 i XN LI Ae ee eon 235 10 2 MASK OPTION OF STANDBY 235 10 3 MASK OPTION FOR FEEDBACK RESISTOR OF SUBSYSTEM CLOCK 236 CHAPTER 11 INSTRUCTION SET ES Co Ra FEES 237 tbi SNIOUEINSIRUCOGTIONS 5 dian diga aset i ias ansa adiu De pde seein 237 GETLINSTUCUOM e sciet iius taies 237 11 1 2 Bit Manipulation Instructions 238 TLAS Sting Effect InstEelloriS dat audio vest 238 11 1 4 Number System Conversion Instructions 239 11 1 5 Skip Instructions and the Number of Machine Cycles Required Wee 240 11 2 INSTRUCTION SEF AND OPERATION 241 11 3 INSTRUCTION CODES OF EACH INSTRUCTION 258 11 4 FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONS 264 S suus Sassi 264 11 4 2 Table Refer
4. 1 4 4 5 5 1 1 lt lt L L 3 3 3 3 c c 248 In struc Mne Operand Branch Address Machine Operation ing cycle area CHAPTER 11 INSTRUCTION SET Skip condition PD750004 6 PC11 0 addr The assembler selects the most adequate instruction from instructions below BR addr BR addr BRCB caddr uPD750006 PD750008 12 0 lt The assembler selects the most adequate instruction from instructions below BR addr BRCB caddr BR addr uPD75P0016 13 0 lt addr The assembler selects the most adequate instruction from instructions below BR addr BRCB caddr BR addr uPD750004 PC44 9 addr The assembler selects the most adequate instruction from instructions below BRA 1 BR addr BRCB caddr BR addr1 11 pPD750006 pPD750008 12 0 lt The assembler selects the most adequate instruction from instructions below BRA addr1 BR addr BRCB caddr BR addr1 pnPD75P0016 PC 43 9 addr The assembler selects the most adequate instruction from instructions below BRA addr1 BR addr BRCB caddr BR addr1 Note The shaded portion is supported in Mk mode only 249 uPD750008 USER S MANUAL In Address str
5. E 154 Acknowledge 155 BUSY and Ready ooa ub dE 156 Operations of RELT CMDT RELD and CMDD Master 161 Operations of RELT CMDT RELD and CMDD Slave 161 _ FOL AGIAN M S 162 Operauom oL AGRE er ee ete ree eee eee 162 Operator OT 18 48 ade 163 Operation Se ates ea edo 164 PIP CG OMNGUI all OM scat E 167 Address Transfer Operation from Master Device to Slave Device WUP 1 169 Command Transfer Operation from Master Device to Slave Device 170 Data Transfer Operation from Master Device to Slave Device 171 Data Transfer Operation from Slave Device to Master 172 Example of Serial Bus Configurati M Mages qu ase veste sepa dosi 174 Transfer Format of the READ Command 175 Transfer Format of the WRITE and END 5 176 Transfer Format of the STOP 176 Transfer Format of the STATUS 177 Status Format of the STATUS Command 2 177 Transfer Format or t
6. dU 21 3 1 2 Data Memory Addressing Modes 23 3 2 GENERAL REGISTER BANK CONFIGURATION 34 3 3 WIEMOBY MAPPED VO a utes dd 39 CHAPTER 4 INTERNAL CPU FUNCTIONS 2 4 44222644442 22 45 41 MkI MODE Mk MODE SWITCH 5 45 4 1 1 Differences between Mk Mode and Mk II Mode 45 4 1 2 Setting of the Stack Bank Selection Register 585 46 42 PROGRAM COUNTER to itd 47 43 PROGRAM MEMORY DOM 5 Ein 48 Aa DATA MEMORY IRAN mad 53 4 4 4 Data Memory Configuration ccccccccccccccssecceeeseeeeeeesseeeeeeseseeeeeessaeeeees 53 4 4 2 Specification of a Data Memory 54 A5 uitia atu ons duke 56 4 6 ACCUMULATOR ei 57 4 7 STACK POINTER SP AND STACK BANK SELECT REGISTER SBS 58 4 8 PROGRAM STATUS WORD 5 62 49 BANK SELECT REGISTER 65 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 2 2 2
7. EE detta ha ber ein 96 Format of the Clock Output Mode Register 97 Application to Remote Control 440044000 98 Block Diagram of the Basic Interval Timer Watchdog Timer 99 Format of the Basic Interval Timer Mode Register 100 Format of the Watchdog Timer Enable 101 Block Diagram ol the CIOCK TIME de teo a sesto ed odd octo 106 Clock Mode Register Formal 25 d a a ante 107 Block Diagram of the Timer Event Counter Channel 0 109 Block Diagram of the Timer Counter Channel 1 110 Timer Event Counter Mode Register Channel 0 Format 112 Timer Counter Mode Register Channel 1 113 Timer Event Counter Output Enable Flag Format 114 Timer Event Counter Mode Register 115 Timer Event Counter Output Enable Flag 116 Gontiguration of Timer Event Counte i 118 Counbp Operation TIMIN 119 Error attihe startol the T Wet s copter tte case tatus assis 120 Example of the SBI System Confi
8. Qaia te 14 2 2 8 SO SBO 1 5 1 tette tenente 14 229 idtm denne tuni od exui dede 14 22 10 NETS e 14 15 ZONE 455 652 castles n 15 dre E Em 15 15 ERE 16 16 2 20 Mu 16 2212 c 16 2 2 18 IC for the uPD750004 uPD750006 and PD750008 only 17 2 2 19 Vop orine UPD 75R0016 Only 17 2 2 20 MDO MD3 for the UPD75P0016 17 29 PIN INPUT OUTPUT GIRGUVlES netos teda 18 24 abies 20 CHAPTER FEATURES OF THE ARCHITECTURE AND MEMORY 21 3 1 DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES 21 ST Data Memory Bank oo
9. MkII mode only 0000H 17FFH immediate data or label uPD750006 0000H 1FFFH immediate data or label uPD750008 0000H 3FFFH immediate data or label uPD75P0016 caddr 12 bit immediate data or label faddr 11 bit immediate data or label taddr 20H 7FH immediate data bit O 0 or label PORTn PORTO PORT8 IExxx IEBT IETO IET1 IEO IE2 IE4 IECSI IEW RBn RBO RB3 MBn MBO MB1 MB15 Note For mem only even addresses can be coded for 8 bit data processing 241 uPD750008 USER S MANUAL 2 Legend A A register 4 bit accumulator B B register C C register D D register E E register H H register L L register X X register XA Register pair XA 8 bit accumulator BC Register pair BC DE Register pair DE HL Register pair HL XA Extended register pair XA BC Extended register pair BC DE Extended register pair DE HL Extended register pair HL PC Program counter SP Stack pointer CY Carry flag bit accumulator PSW Program status word MBE Memory bank enable flag RBE Register bank enable flag PORTn Port n n 0 to 8 IME Interrupt master enable flag IPS Interrupt priority specification register Interrupt enable RBS Register bank select register MBS Memory bank select register PCC Processor clock control register M Address bit delimiter xx Contents addressed by xx xxH Hexadecimal data 242 CHAPTER 11 INSTRUCTION SET 3 Explanation of
10. 12 13 0 lt 000 faddr SP lt SP 6 uPD750004 11 lt SP SP 3 SP 2 MBE RBE 0 0 lt SP 1 SP lt SP 4 UPD750006 0750008 PC11 0 lt SP SP 3 SP 2 MBE RBE 0 lt SP 1 SP SP 4 uPD75P0016 PC11 0 lt SP SP 3 SP 2 MBE RBE PC45 PC4o lt SP 1 SP SP 4 uPD750004 x X MBE RBE SP 4 0 0 0 0 lt SP 1 PC41 9 lt SP SP 3 SP 2 SP lt SP 6 uPD750006 PD750008 x X MBE RBE lt SP 4 MBE 0 0 12 SP 1 PC11 0 lt SP SP 3 SP 2 SP lt SP 6 uPD75P0016 x x MBE RBE SP 4 0 0 PC43 12 SP 1 PC11 0 lt SP SP 3 SP 2 SP lt SP 6 Note The shaded portion is supported in Mk II mode only The other portions are supported Mk mode only 253 uPD750008 USER S MANUAL In Address struc Mne Operand Machine Operation ing Skip condition tion monic cycle area RETSNote 1 3 5 uPD750004 MBE RBE 0 0 lt SP 1 PC11 0 lt SP SP 3 SP 2 SP lt SP 4 Then skip unconditionally e PD750006 pPD750008 MBE 0 0 PC4o lt SP 1 PC11 0 lt SP SP 3 SP 2 SP lt SP 4 Then skip unconditionally e 75 16 MBE RBE PC45 12 lt SP 1 PC11 0 lt SP SP 3 SP 2 SP lt SP 4 Then skip unconditionally 3 5 uPD750004 0 0 0 0 SP 1 lt SP SP 3 SP 2 x X MBE RBE SP 4 SP lt SP 6 Then
11. 314 APPENDIX E HARDWARE INDE X a aa saath et wae neus cra pa E A 317 1 HARDWARE INDEX ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE 317 E 2 HARDWARE INDEX ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE SYMBOLY 319 APPENDIX F BEVISION HISTORY semi 321 Figure No 2 1 3 1 3 2 3 3 3 4 3 5 3 6 3 7 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 4 10 4 11 4 12 4 13 4 14 4 15 4 16 4 17 5 1 5 2 5 3 5 4 5 5 5 6 5 5 8 LIST OF FIGURES 1 4 Title Page Pin eet P tm 18 Use of MBE 0 Mode and MBE 1 22 Data Memory Organization and Addressing Range of Each Addressing Mode 24 Updating Static RAM Addresses doce etg deme iua 28 Example of Register Bank Selection 35 General Register Configuration 4 bit 37 General Register Configuration 8 bit Processing 38 MPD 750008 DO MD et estu olii eet ce qued 40 Stack Bank Selection Register 46 Program counter Organization 2 nu tute M ana 47 Program Memory
12. ____ _ _ _ me e e a MP MO MP MS CO NO NO 245 uPD750008 USER S MANUAL In struc Mne Operand Machine Operation tion monic cycle MOVT XA PCDE 1 3 uwPD750004 XA lt PC44 g9 DE RoM e PD750006 PD750008 XA 12 2 75 0016 XA 1 9 pPD750004 XA lt 11 e 750006 PD750008 XA lt PC12 83 XA ROM pPD75P0016 XA 3 XA Rom mem prp ef a hm o few e fas pacas e je Jan _ bw wee wok 2 eem Table reference Bit transfer is O c lt lox roy Note Set register B to 0 in the uPD750004 Only the LSB is valid in register B in the uPD750006 and uPD750008 Only the low order two bits are valid the uPD75P0016 246 CHAPTER 11 INSTRUCTION SET In Address struc Mne Operand Machine Operation ing Skip condition tion Monic cycle area m pss bape e awe ww e 2 i fefe hean T e ibe _ wa ame 0 a n MH Arithmetic logical no n9 wm e acm ox Jele wee i Pe lile
13. A rpa1 XA HL A mem XA mem 245 268 245 268 245 268 245 268 245 268 245 269 245 269 245 269 A reg1 245 269 XA rp 245 269 Table reference instructions MOVT XA PCDE 246 270 MOVT MOVT MOVT XA PCXA 246 271 XA BCDE 246 272 XA BCXA 246 272 Bit transfer instructions MOV1 MOV1 MOV1 MOV1 MOV1 MOV1 CY fmem bit 246 273 CY omem L 246 273 CY H mem bit 246 273 fmem bit CY 246 273 pmem L CY 246 273 H mem bit CY 246 273 Arithmetic logical instructions ADDS ADDS ADDS ADDS ADDS ADDC ADDC ADDC SUBS SUBS SUBS SUBC SUBC SUBC AND AND AND AND OR A n4 246 273 XA n8 246 274 A HL 246 274 XA rp 246 274 rp 1 XA 246 274 A HL 246 274 XA rp 246 275 rp 1 XA 246 275 A HL 246 275 XA rp 246 275 rp 1 XA 246 276 A HL 246 276 XA rp 246 276 rp 1 XA 246 276 A n4 247 276 A HL 247 277 XA rp 247 277 rp 1 XA 247 277 4 247 277 311 PD750008 USER S MANUAL OR A HL 247 277 OR XA rp 247 277 OR rp 1 XA 247 278 XOR A n4 247 278 XOR A HL 247 278 XOR XA rp 247 278 XOR rp 1 XA 247 278 Accumulator manipulation instructions RORC A 247 279 NOT A 247 279 Increment decrement instructions INCS reg 247 279 INCS
14. 50004 a ga a vo 49 Program Memory in 750006 50 Program Memory in 0750008 51 Program Memory 7 0016 52 54 General REGISter 56 RT P 57 ACC IMU AVON A EE 57 Format of Stack Pointer and Stack Bank Select Register 59 Data Saved to the Stack Memory Mk 59 Data Restored from the Stack Memory Mk 60 Data Saved to the Stack Memory Mk 60 Data Restored from the Stack Memory Mk 61 Program Status Word FORMAL saei 62 Bank Select HegISlSl Es aes de qoc Na 65 Data Memory Addresses of Digital 67 COnmlGurations 01 POrS O and eei ecu 69 C onfig ratioris or POMS tede toin 70 Configurations of Ports and 6n n 0 to 3 71 POrS 4 dEd D A domu ete ie
15. 103 105 5 4 1 Configuration of the Clock Timer 2 106 542 Clock Mode Register ascen eee cee ee ee 106 5 5 JTIMEH BVENT COUNTER xiii 108 5 5 1 Configuration of Timer Event Counter 108 5 5 2 8 Bit Timer Event Counter Mode Operation 114 5 5 3 Notes on Timer Event Counter 120 D6 INTERFACE eraen uisus 123 561 Serial Interiace FUNCIONS sias iv oes TU ama co ted dudes 123 5 6 2 Configuration of Serial Interface 124 9 63 celi A T E T ULT TU 127 5 6 4 Operation Halt nennen nennen nnn nnn nnns 135 5 6 5 Three Wire Serial Mode Operations 137 5 6 0 Two Wire Serial VFO MOQ a en ee ra 144 567 SBLMode ODeFallOD eio eios 150 5 6 8 Manipulation of SCK Pin Output eene 179 57 SEQUENTIAL BUPRER eee oe 181 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 183 61 CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT 183 6 2 TYPES OF INTERRUPT SOURCES AND VECTOR
16. Connect the IC pin to the Vpp pin keeping the wiring as short as possible Keep the wiring as short as possible VPP 2 2 19 for the uPD75P0016 only This is a program voltage input pin for program memory PROM write verify operation For normal use connect this pin to Vpp keeping the wiring as short as possible shown above 112 5 V is applied for PROM write verify operation 2 2 20 MDO MD3 for the pPD75P0016 only 1 0 Pins Used Also for Port MDO to MD3 select a mode for program memory PROM write verify operation 17 PD750008 USER S MANUAL 2 3 PIN INPUT OUTPUT CIRCUITS Figure 2 1 shows schematic diagrams of the I O circuitry of the uPD750008 Figure 2 1 Pin Input Output Circuits 1 2 P U R P U R P ch E enable CMOS input buffer P U R Pull Up Resistor ee OUT O disable Output k N ch IT Schmitt trigger input with hysteresis E Push pull output which can be set to high impedance output off for both P ch and N ch 18 CHAPTER 2 PIN FUNCTIONS Figure 2 1 Pin Input Output Circuits 2 2 Type M C P U R P U R ae enable IN OUT Es IN OUT O Output Data n disable Output disable P U R Pull Up Resistor P U R Pull Up Resistor Vpp Type M D PUR Input instruction We P ch P U R 67 Note P U R enable g
17. Remark Function in this section is applicable to the uPD750008 whose program counter consists 13 bits addr OOOOH to 1FFFH However this is also applicable to the uPD750004 whose program counter consists of 12 bits addr OOOOH to OFFFH the uPD750006 whose program counter consists of 13 bits addr OOOOH to 17FFH and the uPD75P0016 whose program counter consists of 14 bits addr OOOOH to 3FFFH 287 uPD750008 USER S MANUAL C 2 BR BCDE Function For the uPD750008 PC425 9 BCDE Branches to the address specified by the program counter whose bits have been replaced with the contents of the Bo C D and E registers Function For the uPD750008 12 lt BCXA Branches to the address specified by the program counter whose bits have been replaced with the contents of the Bo C X and A registers C D TBR addr Function Assembler pseudo instruction of the GETI instruction for table definition This instruction is used to replace a 3 byte BR instruction with a 1 byte GETI instruction The 12 bit address data must be coded in addr For detailed information refer to RA75X Assembler Package User s Manual Language EEU 1363 Remark Function in this section is applicable to the uPD750008 whose program counter consists of 13 bits addr OOOOH to 1FFFH However this is also applicable to the uPD750004 whose program counter consists of 12 bits addr OOOOH to OFFFH the PD750006 whose program cou
18. SCK LI LE LELIELEIE LI lef lel LE LI pP m SBO SB1 The acknowledge signal is one shot pulse output phase with the falling edge of SCK after 8 bit data transfer This signal may be synchronized with any clock of SCK The transmitter checks if the receiver returns the acknowledge signal after 8 bit data transfer If the acknowledge signal is not returned after a specified period of time the transmitter can assume that the reception failed 155 PD750008 USER S MANUAL f Busy signal BUSY and ready signal READY The busy signal informs the master that a slave is getting ready for data transfer The ready signal informs the master that a slave is ready for data transfer Figure 5 59 Busy and Ready Signals lJli LILI LI LU SBO SB1 X MCK BUSY READY In the SBI mode a slave notifies the master of the busy state by changing SBO or SB1 from high to low The busy signal is output following the acknowledge signal output by the master or a slave The busy signal is set and released in phase with the falling edge of SCK The master automatically terminates output of serial clock SCK when the busy signal is released The master can transfer the next data when the busy signal is released and a slave enters the state in which the ready signal is to be output 3 Register setting To set the SBI mode manipulate the following two registers Serial operation mode register CSIM Serial bus inter
19. not cleared 55 PD750008 USER S MANUAL 4 5 GENERAL REGISTER 8 x 4 BITS x 4 BANKS The general registers are mapped to particular addresses in data memory Four banks of registers are provided with each bank consisting of eight 4 bit registers B C D E H L X and A The register bank RB to be enabled at the time of instruction execution is determined by RB RBE RBS RBS 0 to Each general register allows 4 bit manipulation In addition BC DE HL or XA serves as a register pair for 8 bit manipulation DL also makes a register pair as well as DE and HL These three register pairs can be used as data pointers In 8 bit manipulation the register pairs in the register banks 0 lt gt 1 2 3 that have the inverted value of bit 0 of the register bank RB address can be specified as BC DE HL and XA in addition to the register pairs BC DE HL and XA See Section 3 2 A general register area can be addressed and accessed as normal RAM regardless of whether it is used as a register Figure 4 8 General Register Format Data memory 3 0 Register bank 0 Address OOOH 008H Same as bank 0 Register bank 1 010 Same as bank 0 Register bank 2 017H 018 Same as bank 0 Register bank 3 01FH 56 CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4 9 Register Pair Format One bank 4 6 ACCUMULATOR In the uPD750008 the A register and XA register
20. t 82768 iz XT1 pin input level bit test only WM3 D Input to the XT1 pin is low level Input to the XT1 pin is high level Clock operation enable disable bit WM2 m Disables clock operation clears the frequency dividing circuit Enables clock operation Operation mode selection bit WM 1 m Normal clock mode 20 sets IRQW at 0 5 seconds Advanced clock mode sets IRQW at 3 91 ms Count clock fw selection bit WMO m Selects divided system clock output Selects subsystem clock fxr 107 PD750008 USER S MANUAL 5 5 TIMER EVENT COUNTER The uPD750008 has one timer event counter channel channel 0 and one timer counter channel channel 1 Figures 5 28 and 5 29 show the configuration of these channels In this section the timer event counter and timer counters are referred to as timer event counters When you read this section for description of channel 1 take timer event counter as timer counter The timer event counter has the following functions a Programmable interval timer operation 6 Square wave output of any frequency to the PTOn pin c Event counter operation Channel 0 only d Divides the frequency of signal input the TIO pin to 1 Nth of the original signal and outputs the divided frequency to the PTOO pin frequency divider operation Channel 0 only e Supplies the serial shift clock to the serial interface circuit Channel 0 only f Calls the
21. y uo 195 S SOOHI L dNM USUM YOS eui jo eui uo Jes s 590 0 dNM YAUM L Se1ON PD750008 USER S MANUAL 19 SEUJ JO 5 pesseoouJd indino Bulag jeubls AWO Jou eufiis 13H 19ujeu 406 eseud ul peueJsuel 19 8 indjno jou euis 13H JASEN SI Ajuo o e s 0 Jeye YOS eseud 09 20 pue SUOIOSIIG Ul p9JJeJSUEJ EEP 10 8 anwo 7384 LgS indjno jeubis 2 085 CID pue 13H enas UO Jeye YOS eseud Ov ZV 5 JO 5 10 8 152 SseJppv Se o 9 9 151 Guunp 1ndino si isenbe yes ejep pueululoo ssaJppy 19JSUe4 uo os pue ASng Go 105 9155 jeubis snq yOo o OIS YOV jenas uo 1ndino 116 Jo Pulsu 5 MOS UO 195 S 6 uonnoox 10 snouoJuou g J9 Se N jeueg indjno Bulueayy 10 uonipuoo yeyo uoniuJeq indino eujeu jeus 185 9u1 sjeuB
22. 1 If INTO is set when interrupts are disabled the interrupt request flag is held 2 When the interrupt is enabled by the El instruction the INTO interrupt service program starts 3 Same as 1 4 When the held INTCSI flag is enabled the INTCSI interrupt service program starts 206 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 5 Execution of held interrupts two interrupts with lower priority occur concurrently lt Main program gt Reset El IETO El IEO EI INTO service program INTTO lt 2 gt lt INTTO service routine gt RETI lt 1 gt When INTO and INTTO with the lower priority occur concurrently during execution of the same instruction INTO with a higher priority is executed first INTTO is held lt 2 gt When the INTO interrupt service program has been executed the RETI instruction is executed to start the interrupt service program for INT TO which has been held 207 uPD750008 USER S MANUAL 6 Executing pending interrupt interrupt occurs during interrupt processing INTBT has higher priority and INTTO and INTCSI have lower priority 208 Main program Reset El El El IECSI MOV A 9 MOV IPS A INTTO lt 1 gt INTBT lt INTBT service program gt PUSH rp 2 INTCSI POP rp 3 RETI INTCSI service program 4 RETI INTTO service program RETI 1 When INTBT with the higher p
23. 250 287 BCDE 250 288 BCXA 251 288 BRA laddri 251 285 BRCB Icaddr 251 286 TBR addr 256 288 Subroutine stack control instructions CALLA laddr1 251 289 CALL laddr 252 289 CALLF Ifaddr 252 290 TCALL laddr 256 290 RET 253 291 HETS 254 291 RETI 254 292 PUSH rp 255 292 PUSH BS 255 293 POP rp 255 293 POP BS 255 293 Interrupt control instructions El 255 293 EI IExxx 255 293 DI 255 293 DI IExxx 255 294 instructions IN A PORTn 255 294 IN XA PORTn 255 294 OUT PORTn A 255 294 OUT PORTn XA 255 294 CPU control instructions HALT 255 295 STOP 255 295 NOP 255 295 Special instructions SEL RBn 256 295 SEL MBn 256 295 GETI taddr 256 296 APPENDIX D INSTRUCTION INDEX 313 PD750008 USER S MANUAL D 2 INSTRUCTION INDEX ALPHABETICAL ORDER A ADDC ADDC ADDC ADDS ADDS ADDS ADDS ADDS AND AND AND AND AND1 AND1 AND1 B BR BR BR BR BR BR BR BR BR BRA BRCB C CALL CALLA CALLF CLR1 CLR1 314 A HL 246 274 rp 1 XA 246 275 XA rp 246 275 A n4 246 273 A HL 246 274 rp 1 246 274 XA rp 246 274 XA n8 246 274 A n4 247 276 A HL 247 277 rp 1 XA 247 277 XA rp 247 277 CY fmem bit 248 284 CY omem L 248 284 CY H mem bit 248
24. 3107 XA SBO PO02 N ch input Transfer starting with MSB pay I O P02 input SB1 P03 N ch open drain Serial clock selection bit W CSIM1 CSIMO Serial clock SCK pin mode ow Timer event counter output TOUTO Output Remark The value at 4 19 MHz is indicated in parentheses b Serial bus interface control register SBIC To use the two wire serial I O mode set SBIC as shown below For details SBIC format see 2 in Section 5 6 3 SBIC is manipulated using a bit manipulation instruction When the RESET signal is input SBIC is set to OOH In the figure below the hatched portions indicate the bits used in the two wire serial I O mode 7 6 5 4 3 2 1 0 Address FE2H BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT SBIC Do not use these bits in the two wire serial I O mode Bus release trigger bit W Command trigger bit W Remark W Write only Command trigger bit W Control bit for command signal CMD trigger output By setting CMDT 1 the SO latch is cleared Then the CMDT bit is automatically cleared 146 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Bus release trigger bit W Control bit for bus release signal REL trigger output By setting RELT 1 the SO latch 15 set to 1 Then the RELT bit automatically cleared to 0 Caution Never use bits other than RELT and CMDT the two wire serial I O mode 2 Communication operation The tw
25. P21 Built in pull up resistors can be connected P22 by software in units of 4 bits P23 P30Note 2 O Programmable 4 bit I O port PORTS P31Note 2 I O can be specified bit by bit P32Note 2 Built in pull up resistors can be connected P33Note 2 by software in units of 4 bits Notes 1 circuits enclosed in circles have Schmitt triggered input 2 An LED can be driven directly 3 uyPD75P0016 PD750008 USER S MANUAL P40 P43Note 2 4 P50 P53Note 2 4 P60 P61 P62 P63 P70 P71 P72 P73 P80 P81 Notes 1 2 3 4 5 10 Table 2 1 Digital I O Port Pins 2 2 8 bit Upon ae unction I O reset CIrcul typeNote 1 N ch open drain 4 bit I O port PORTA High level when M D Withstand voltage is 13 V in open drain a pull up resistor M E Note 3 mode is provided or A pull up resistor can be provided bit high impedance by bit mask option Note 5 Data input output pins for writing verifying lower 4 bits of program memory PROM N ch open drain 4 bit I O port PORT5 High level when M D Withstand voltage is 13 V in open drain a pull up resistor M E Note 3 mode is provided or A pull up resistor can be provided bit high impedance by bit mask option Note 5 Data input output pins for writing verifying higher 4 bits of program memory PROM connected by software in units of 4 bits 2 bit input port PORTS Built in pull up r
26. 175 PD750008 USER S MANUAL When the slave receives a transmission data count if it has data enough for transmitting the specified number of bytes of data the slave returns ACK If the slave does not have enough data for transmission an error occurs ACK is not returned in this case The master sends ACK to the slave each time it receives one byte 2 WRITE command END command STOP command These commands write data to a slave One to 256 bytes of data can be written The data length is specified in a parameter by the master When 00H is specified as the data length the 256 byte data transfer is assumed Figure 5 73 Transfer Format of the WRITE and END Commands Command Data Data Data Command Remark M Output by the master S Output by the slave If the slave has an enough area for storing receive data of the specified length the slave returns ACK If the slave does not have an enough area an error occurs ACK is not returned in this case The master transmits an END command when all data have been transferred The END command informs the slave that all data have been transferred correctly The slave accepts an END command even before data reception is uncompleted In this case the data received just before the acceptance of the END command becomes valid The master compares the contents of SIO before transfer with the contents of SIO after transfer to check whether the data has been output onto the bus correctly If the
27. MD3 P33 232 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY PROM 9 4 SCREENING OF ONE TIME PROM Because of its structure it is difficult for NEC to completely test the one time PROM product before shipment It is therefore recommended that screening be performed to verify the PROM contents after the necessary data has been written to the PROM and the product has been stored under the following conditions Storage Temperature Storage Time 125 C 24 hours 233 PD75008 USER S MANUAL MEMO 234 CHAPTER 10 MASK OPTION 10 1 The pins of the uPD750008 have the following mask options Table 10 1 Selecting Mask Option of Pin Mask Option A Pull up resistor be connected in 1 bit units P53 P40 through P43 port 4 or P50 through P53 port 5 can be connected with pull up resistors by mask option The mask option can be specified in 1 bit units If the pull up resistor is connected by mask option port 4 or 5 goes high on reset If the pull up resistor is not connected the port goes into a high impedance state on reset The ports of the uPD75P0016 do not have a mask option and is always open 10 2 MASK OPTION OF STANDBY FUNCTION The standby function of the uPD750008 allows you to select wait time by using a mask option The wait time is required for the CPU to return to the normal operation mode after the standby function has been released by the RESET sig
28. OOOOH to 17FFH and the uPD75P0016 whose program counter consists of 14 bits addr OOOOH to 3FFFH 286 CHAPTER 11 INSTRUCTION SET T BR PCDE Function For the PD750008 lt 12 DE 7 4 lt D PC3 9 E Branches to the address specified by the program counter whose low order 8 bits PC7 9 have been replaced with the contents of the DE register pair The high order bits of the program counter are not affected Caution The BR PCDE instruction usually causes a branch within the page containing the instruction However if the first byte of the instruction code is located at address xxFEH or xxFFH a branch to the next page instead of that page occurs Program memory Page 2 2 02FFH If the BR PCDE instruction is located at a or b in the figure above a branch to page 3 instead of page 2 occurs jumping to the low order 8 bits of the address specified by the contents of the DE register pair 2 2 Function For the uPD750008 2 0 lt PC42 8 XA 7 4 lt PC3 9 lt A Branches to the address specified by the program counter whose low order 8 bits PC7 9 have been replaced with the contents of the XA register pair The high order bits of the program counter are not affected Caution As with the BR PCDE instruction if the first byte is located at address xxFEH or xxFFH branch to the next page instead of the page containing the instruction occurs
29. SVA is manipulated using an 8 bit manipulation instruction When the RESET signal is generated the value of SVA is undefined However the value of SVA is preserved when the RESET signal is generated in the standby mode SVA has the following two functions CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS a Slave address detection In the SBI mode SVA is used when the PD750008 is connected as a slave device to the serial bus SVA is an 8 bit register for a slave to set its slave address number assigned to it The master outputs a slave address to the connected slaves to select a particular slave Two data values a slave address output from the master and the value of SVA are compared with each other by the address comparator a match is found the slave is selected At this time bit 6 COI of serial operation mode register CSIM is set to 1 If a match with received address data is not found the bus release detection flag RELD is cleared to 0 When WUP 1 wake up state detection IRQCSI is set only when a match is found With this interrupt request the uPD750008 can be informed of a communication request transmitted from the master b Error detection In the two wire serial mode or SBI mode SVA detects an error when addresses commands or data is transferred with the uPD750008 operating as the master or when data is transferred with the uPD750008 operating as a slave For details see 6 in Section 5 6
30. Subp I O mode registers PMGA PMGB PMGC Pull up resistor specification register POGA POGB Bit sequential buffers BSBO to BSB3 Undefined 227 PD750008 USER S MANUAL MEMO 228 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY PROM The program memory in the uPD75P0016 consists of a one time PROM 16384 x 8 bits Writing to and verifying the contents of the one time PROM is accomplished by using the pins shown in the table below Note that address inputs are not used instead the address is updated using the clock input from the X1 pin Pin name Function Voltage is applied to this pin when writing to the program memory or verifying its contents normally Vpp electric potential Vpp X1 X2 Address update clock inputs used when writing to the program memory or verifying its contents The X2 pin is used to input the inverted signal of the X1 pin input MDO MD3 Operation mode selection pins used when writing to the program memory or verifying its contents P40 to P43 I O pins for 8 bit data used when writing to the program memory or verifying low order four bits its contents P50 to P53 high order four bits Power voltage is applied to this pin During normal operation 2 2 to 5 5 V should be applied 6 V should be applied when writing to the program memory or verifying its contents Cautions 1 The pPD75P0016CU GB does not have an erasure window so the erasing with ultraviolet rad
31. USER S MANUAL uPD750008 4 BIT SINGLE CHIP MICROCOMPUTER uPD750004 uPD750006 PD750008 uPD75P0016 Document U10740EJ2VOUMOO 2nd edition Previous No IEU 1421 Date Published April 1996 P NEC Corporation 1995 Printed in Japan GENERAL PIN FUNCTIONS FEATURES OF THE ARCHITECTURE AND MEMORY MAP INTERNAL CPU FUNCTIONS PERIPHERAL HARDWARE FUNCTIONS INTERRUPT AND TEST FUNCTIONS STANDBY FUNCTION RESET FUNCTION WRITING TO AND VERIFYING PROGRAM MEMORY PROM MASK OPTION INSTRUCTION SET FUNCTIONS OF THE pPD75008 pPD750008 AND pPD75P0016 DEVELOPMENT TOOLS MASK ROM ORDERING PROCEDURE INSTRUCTION INDEX HARDWARE INDEX RIVISION HISTORY The export of this product from Japan is regulated by the Japanese government To export this product may be prohibited without governmental license the need for which must be judged by the customer The export or re export of this product from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative The information in this document is subject to change without notice No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rig
32. uPD750008 USER S MANUAL 4 Explanation of the machine cycle column o represents the number of machine cycles required when a skip instruction with the skip function performs a skip operation S assumes one of the following values e When no skip operation is performed S 0 When a 1 byte instruction or 2 byte instruction is skipped S 1 e When a 3 byte instructionNote is skipped S 2 Note 3 byte instruction BR addr BRA laddr1 CALL addr and CALLA addr1 instructions Caution The GETI instruction is skipped in one machine cycle One machine cycle is equal to one cycle tc y of the CPU clock and four different machine cycles available for selection according to the PCC setting See Figure 5 12 244 CHAPTER 11 INSTRUCTION SET In Address struc Mne Operation Machine Operation ing Skip condition tion monic cycle area mov jade __ 1 1 faem _ 2 2 2 2 nm __ Stringettect A HL 2 2 Stringettect mas 2 2 __ _____ o f pem ___ lt HL then L lt Lo 111 asmen xem 2 2 pasem ___ o o ema 1 a emxa 2 2 _____ Amm __ 2 2 JAemem IN IN CO mema 2 2 3 am fe e acme hw fa fa 14 wma 2 e _ ewm remm 3 Dem pem 3 mm a 2 eem f 9 Damm
33. 247 279 INCS HL 247 279 INCS mem 247 280 DECS reg 247 280 DECS 247 280 Compare instructions SKE reg n4 247 280 SKE HL n4 247 280 SKE A HL 247 280 SKE XA HL 247 281 SKE A reg 247 281 SKE XA rp 247 281 Carry flag manipulation instructions SET1 CY 247 281 CLR1 CY 247 281 SKT CY 247 281 NOT1 CY 247 282 Memory bit manipulation instructions SET1 mem bit 248 282 SET1 fmem bit 248 282 312 SET1 SET1 CLR1 CLR1 CLR1 CLR1 SKT SKT SKT SKT SKF SKF SKF SKF SKTCLR SKTCLR SKTCLR AND1 AND1 AND1 OR1 OR1 OR1 XOR1 pmem L 248 282 H mem bit 248 282 mem bit 248 282 fmem bit 248 282 pmem L 248 282 H mem bit 248 282 mem bit 248 283 fmem bit 248 283 pmem L 248 283 H mem bit 248 283 mem bit 248 283 fmem bit 248 283 pmem L 248 283 H mem bit 248 283 fmem bit 248 283 pmem L 248 283 H mem bit 248 283 CY fmem bit 248 284 CY omem L 248 284 CY H mem bit 248 284 CY fmem bit 248 284 CY omem L 248 284 CY H mem bit 248 284 CY fmem bit 248 284 CY omem L 248 284 CY H mem bit 248 284 Branch instructions BR BR BR BR BR BR BR BR BR addr 249 284 addr1 249 285 laddr 250 285 addr 250 285 addr1 250 285 PCDE 250 287 PCXA
34. 284 addr 249 284 addr1 249 285 BCDE 250 288 BCXA 251 288 PCDE 250 287 PCXA 250 287 laddr 250 285 addr 250 285 addr1 250 285 laddr1 251 285 Icaddr 251 286 laddr 252 289 laddri 251 289 252 290 CY 247 281 fmem bit 248 282 CLR1 mem bit 248 282 CLR1 pmem L 248 282 CLR1 H mem bit 248 282 D DECS reg 247 280 DECS 247 280 01 255 293 DI IExxx 255 294 E El 255 293 EI IExxx 255 293 G GETI taddr 256 296 H HALT 255 295 IN IN INCS INCS INCS INCS M MOV MOV MOV MOV MOV MOV A PORTn 255 294 XA PORTn 255 294 mem 247 280 reg 247 279 rp1 247 279 OHL 247 279 A mem 245 266 A reg 245 267 A n4 245 264 A HL 245 265 A HL 245 265 A HL 245 265 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVT MOVT MOVT MOVT MOV1 MOV1 MOV1 MOV1 MOV1 MOV1 N NOP NOT NOT1 0 OR OR OR OR OR1 OR1 1 245 265 HL n8 245 265 245 267 mem XA 245 267 reg1 A 245 268 1 14 245 265 rp 1 XA 245 268 rp2 n8 245 265 XA mem 245 267 XA rp 245 267 XA n8 245 265 XA HL 245 266 HL A 245 266 HL XA 245 266 XA BCDE 246 272 XA BCXA 246 272 XA
35. 67 SS DIGITAL VO usd cis iacens d 67 5 1 1 Types Features and Configurations of Digital I O Ports 68 52 74 5 1 3 Digital Port Manipulation Instructions 2042 76 Digital VO Por DSi ain sce 79 5 1 5 Specification of Bilt in Pull Up Resistors 81 516 VO Timing or Digital VO et n 82 52 CLOCK GENERAMUOR i oiii a 84 5 2 1 Clock Generator Configuration 84 5 2 2 Functions and Operations of the Clock Generator 85 5 2 3 System Clock and CPU Clock Setting 94 Ive dO OP mei 96 5 3 BASIC INTERVAL TIMER WATCHDOG TIMER 000021 99 5 3 1 Configuration of the Basic Interval Timer Watchdog Timer 99 5 3 2 Basic Interval Timer Mode Register BTM 99 5 3 3 Watchdog Timer Enable Flag 101 5 3 4 Operation of the Basic Interval Timer 101 5 3 5 Operation of the Watchdog 2 102 9920 OME FUNCIONS enan
36. CYv bit specified in operand ORs the content of the carry flag with the bit in data memory specified by bit manipulation addressing fmem bit pmem 2L H mem bit then sets the result in the carry flag C 2 XOR1 CY pmem L C 7 xoRi cv H mem bit Function CY CY bit specified in operand Exclusive ORs the content of the carry flag with the bit in data memory specified by bit manipulation addressing fmem bit pmem L H mem bit then sets the result in the carry flag 11 4 40 Branch Instructions C15 BR addr Function For the 750008 lt addr addr 0000H 1FFFH Branches to the address specified by the immediate data addr This instruction is an assembler pseudo instruction and the assembler automatically replaces this instruction with the BR addr instruction BRCB caddr instruction or BR addr instruction as required at assembly time 284 CHAPTER 11 INSTRUCTION SET Cu BR addr1 Function For the PD750008 lt addr1 addr1 0000H 1FFFH Branches to the address specified by the immediate data addr1 This instruction is an assembler pseudo instruction and the assembler automatically replaces this instruction with the BRA addr1 instruction BR addr instruction BRCB caddr instruction or BR addr1 instruction as required at assembly time Remark Function in this section is applicable to the uPD750008 whose program counter consists 13 bits addr OOOOH to 1FFFH Ho
37. Error at the Start of the Timer TLL 2 120 Timer start Timer start Notes on the start of the timer Usually when the timer is started bit 3 of the is set the count register 0 and the interrupt request flag IRQTO are cleared However when the timer is placed in the operation mode and the setting of IRQTO andthe start of the timer occur at the same time IRQTO may not cleared This causes no problem if IRQTO is used for a vectored interrupt However if IRQTO is being tested a problem arises because IRQTO is set even if the timer is started Accordingly in a situation where the timer is started on such timing that IRQTO may set the timer must be restarted after itis once stopped bit 2 of the TMO is cleared to 0 or timer start operation must be performed twice Example The timer is started on such timing that IRQTO may be set SEL MB15 MOV XA 0 MOV TMO XA otop the timer MOV XA 4CH MOV TMO XA Restart Or SEL MB15 SET1 TMO 3 SET1 TMO 3 Restart CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 3 Error in reading the count register The contents of the count register can be read using an 8 bit data memory manipulation instruction at any time During operation by such an instruction all count pulse changes are held not to change the count register This means that count pulse signal source is applied to the TIO input as many count pulses as corresponding to the time required to execute
38. MB 15 When MBE 1 MB MBS 8 bit direct Address specified by MB and mem mem even address addressing When MBE 0 and mem 00H 7FH MB 0 mem 80H FFH MB 15 1 5 4 bit register Address specified by MB and HL indirect In this case MB 5 addressing HL automatically increments the L register after addressing HL automatically decrements the L register after addressing Address specified by DE in memory bank 0 Address specified by DL in memory bank 0 8 bit register Address specified by MB and HL Contents of the L register is indirect an even address addressing In this case MB MBE MBS Bit fmem bit Bit specified by bit at the address specified by fmem manipulation In this case addressing fmem FBOH FBFH interrupt related hardware FFOH FFFH I O ports Bit specified by the low order two bits of the L register at the address specified by the high order 10 bits of pmem and the high order two bits of the L register In this case FCOH FFFH H mem bit Bit specified by bit at the address specified by MB H and the low order four bits of mem In this case MB MBE MBS Stack addressing ERE Address specified by the SP in memory bank selected by the SBS 25 PD750008 USER S MANUAL 2 3 26 4 bit direct addressing mem In this addressing mode the operand of an instruction directly specifies any area the data
39. PC4 SP 3 PC7 PC4 PSW SP 1 CY 15 215 115 0 2 2 T 2 Note 12 and PC13 0 in the uPD750004 PC13 is 0 in the uPD750006 and 0750008 59 PD750008 USER S MANUAL Figure 4 13 Data Restored from the Stack Memory Mk Mode POP instruction RET or RETS instruction RETI instruction Stack Stack Stack Note Note Note zi 1 Upper bits of pair register SP 1 MBE RBE 2 MBE RBE IPC13IPC12 SP 2 SP 2 PC3 PCO SP 3 PC7 PC4 PC7 PC4 o STI MBE REE PSW 5 CY 15 215 115 0 9 V 2475 Note PC12 and PC13 are 0 in the uPD750004 PC13 is 0 in the PD750006 and uPD750008 Figure 4 14 Data Saved to the Stack Memory Mk II Mode PUSH instruction CALL CALLA or CALLF instruction Interrupt Stack Stack Stack i Note 1 Note 1 i i Note 1 Note 1 0 0 1 12 0 1 0 2 t PSW CY SK2 SK1 SKO Notes 1 12 and PC13 are 0 in the PD750004 PC13 is 0 in the uPD750006 and uPD750008 2 PSW bits other than MBE and RBE are not saved or restored Remark indicates an undefined bit 60 CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4 15 Data Restored from the Stack Memory Mk II Mode POP instruction RET or RETS instruction RETI instruction Stack Stack Stack SPD Lower bits of pair register PC11
40. PC8 PC11 PC8 1 Note1 j 1 1 SP 1 Upper bits of pair register 0 0 12 0 0 2 SP 2 PCO PCO NE Notes 1 PC12 and PC13 0 in the uPD750004 PC13 is 0 in the PD750006 and uPD750008 2 PSW bits other than MBE and RBE are not saved or restored Remark indicates an undefined bit 61 PD750008 USER S MANUAL 4 8 PROGRAM STATUS WORD PSW 8 BITS The program status word PSW consists of various flags closely associated with processor operations The PSW is mapped to addresses FBOH and FB1H in data memory space Four bits at address FBOH can be manipulated with a memory manipulation instruction Figure 4 16 Program Status Word Format Address ee Symbol pen See ee Cannot be manipulated Can be manipulated Can be manipulated by an instruction specifically provided for controlling this flag Table 4 3 PSW Flags Saved Restored in Stack Operation Saved restored flag Restore MBE and RBE are restored 1 Carry flag CY The carry flag is a 1 bit flag used to store information about an overflow or underflow that occurs when an arithmetic operation with a carry ADDC SUBC is executed The carry flag functions as a bit accumulator and therefore can be used to store the result of a Boolean algebra operation performed on the CY and a bit at a specified data memory bit address The carry flag is manipulated using special in
41. PCDE 246 270 XA PCXA 246 271 CY fmem bit 246 273 CY omem L 246 273 CY H mem bit 246 273 fmem bit CY 246 273 pmem L CY 246 273 H mem bit CY 246 273 255 295 A 247 279 CY 247 282 A n4 247 277 A HL 247 277 rp 1 XA 247 278 XA rp 247 277 CY fmem bit 248 284 CY omem L 248 284 APPENDIX D INSTRUCTION INDEX OR1 CY H mem bit 248 284 OUT 255 294 OUT 255 294 BS 255 293 rp 255 293 PUSH BS 255 293 PUSH rp 255 292 R RET 253 291 RETI 254 292 RETS 254 291 RORC S SEL SEL SET1 SET1 SET1 SET1 SET1 SKE SKE SKE SKE SKE SKE SKF SKF SKF SKF SKT SKT SKT 247 279 MBn 256 295 RBn 256 295 CY 247 281 fmem bit 248 282 mem bit 248 282 pmem L 248 282 H mem bit 248 282 A reg 247 281 A HL 247 280 reg n4 247 280 XA rp 247 281 XA HL 247 281 HL n4 247 280 fmem bit 248 283 mem bit 248 283 pmem L 248 283 H mem bit 248 283 247 281 fmem bit 248 283 mem bit 248 283 315 PD750008 USER S MANUAL SKT pmem L 248 283 SKT H mem bit 248 283 SKTCLR fmem bit 248 283 SKTCLR pmem L 248 283 SKTCLR H mem bit 248 283 STOP 255 295 SUBC A HL 246 276 SUBC rp 1
42. SBIC Tousethe SBI mode set SBIC as shown below For details on SBIC format see 2 inSection 5 6 3 SBIC is manipulated using a bit manipulation instruction When the RESET signal is input SBIC is set to OOH In the figure below hatched portions indicate the bits used in the SBI mode Address FE2H SBIC 7 6 5 4 3 2 1 0 BSYE ACKT CMDD RELT Bus release trigger bit W Command trigger bit W Bus release detection R Command detection flag R Acknowledge trigger bit W Acknowledge enable bit R W Acknowledge detection flag R Busy enable bit R W Remark Read only W Write only R W Read write Busy enable bit R W lt 1 gt The busy signal is automatically disabled lt 2 gt Busy signal output is stopped in phase with the falling edge of SCK immediately after clear instruction execution The busy signal is output after the acknowledge signal in phase with the falling edge of SCK 158 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Acknowledge detection flag R Condition for being cleared ACKD 0 Condition for being set ACKD 1 lt 1 gt The transfer operation is started The acknowledge signal ACK is detected lt 2 gt The RESET signal is entered in phase with the rising edge of SCK Acknowledge enable bit R W ACKE EE ELE Disables automatic output of the acknowledge signal Ou
43. W Write only Serial interface operation enable disable specification bit W Shift register operation Serial clock counter IRQCSI flag SO SBO and SI SB1 pins CSIEO Shift operation disabled Used only for port 0 Serial clock selection bit W The 01 5 pin assumes the following state according to the setting of CSIMO and CSIM1 CSIM1 CSIMO P01 SCK pin state High level output When clearing CSIE during serial transfer use the following procedure lt 1 gt Disable interrupts by clearing the interrupt enable flag IECSI lt 2 gt Clear CSIE 3 Clear the interrupt request flag IRQCSI 136 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5 6 5 Three Wire Serial Mode Operations The three wire serial mode is compatible with other modes used in the 75 XL series 75X series uPD7500 series and 87AD series Communication is performed using three lines Serial clock SCK serial output SO and serial input 51 Figure 5 43 Example of Three Wire Serial 1 0 System Configuration 3 wire serial 3 wire serial Master CPU Slave CPU PD750008 Remark The uPD750008 can also be used as a slave CPU 1 Register setting To set the three wire serial I O mode manipulate the following two registers Serial operation mode register CSIM Serial bus interface control register SBIC a Serial operation mode register CSIM To use the three
44. XA rp Transfers the contents of register pair ro XA HL DE BC XA HL DE BC to the XA register pair Example The contents of the XA register pair are transferred to the XA register pair MOV XA XA 267 uPD750008 USER S MANUAL C 2 MOV reg1 A Function reg1 A Transfers the contents of the A register to register reg1 X H L D E B C C 2 MOV rp 1 XA Function rp Transfers the contents of the XA register pair to register pair HL DE BC XA HL DE BC C 2 XCH A HL C 2 XCH A HL 2 XCH A HL C gt XCH A rpat Function lt gt Register pair specified by the operand When HL is specified for the register pair Skip if L 0 When HL is specified for the register pair Skip if FH Exchanges the contents of the A register with the data at the data memory location addressed by the specified register pair HL HL HL DE DL When HL automatic increment is specified for the register pair automatically increments the contents of the L register by one after the data exchange and continues the operation until the contents are set to 0 Then skips the immediately following instruction When HL automatic decrement is specified for the register pair automatically decrements the contents of the L register by one after the data exchange and continues the operation until the contents are set to FH Then skips the immediately following
45. bu e oron oroli ion o rmn o rororotoliiiot rrr _ wx EMEK EKEK EREKE C 10011001 NEN _ be rrr wk orerere toroo rrr hex _ 261 uPD750008 USER S MANUAL Instruction code eu roosrootfoovooere w __ PPro Instruction monic Me lerra Mew roooooo0o ex sereve rsoiiooi reno eee spo mobe 1901 2 pereriis e 262 CHAPTER 11 INSTRUCTION SET Instruction code addr1 O 0 0 0 Ag Ao Ay 16 to 2 me oorreos pooooooo wo foo ooote1 _ ame esrross pssovsoi wer ro rri io 0 uli mes cass Jo r o mm ee Mne Operand monic Instruction m eseeespeesssrii 5 __ emm ii ii WANN Dem re reso ro iiti poma wenn _ ie 2 263 uPD750008 USER S M
46. specified in BRCB Icaddr instruction 17FFH Note be used only in the MkII mode Remark In addition to the above the BR PCDE and BR instructions can cause a branch to an address with only the 8 low order bits of the PC changed 50 0020H 007FH 0080H 07FFH 0800H OFFFH 1000H Note Can be used only in the MkII mode Remark Figure 4 5 Program Memory Map in pPD750008 INTBT INT4 start address INTO start address INT1 start address INTCSI start address INTTO start address INTT1 start address 7 6 0 Internal reset start address high order 6 bits Internal reset start address INTBT INT4 start address high order 6 bits low order 8 bits low order 8 bits INTO start address high order 6 bits low order 8 bits INT1 start address high order 6 bits low order 8 bits INTCSI start address high order 6 bits low order 8 bits INTTO start address high order 6 bits low order 8 bits INTT1 start address high order 6 bits low order 8 bits GETI instruction reference table Entry address specified in CALLF Ifaddr instruc Branch tion address specified in BRCB Icaddr instruc tion Y Y A Branch address specified in BRCB Icaddr instruction CHAPTER 4 INTERNAL CPU FUNCTIONS Branch address specified in BR addr BR BCDE BR BCXA BRA addr1 Nee CALL or CALLA laddr1
47. the string instructions following an executed instruction are processed as NOP instructions Examples 1 The data OBH is set in the accumulator MOV A 0BH 2 Data to be output to port 3 is selected from O to 2 AO MOV A 0 A1 MOV A 1 A2 MOV A 2 OUT PORT3 A 264 CHAPTER 11 INSTRUCTION SET T MOV reg1 n4 Function regi n4 n4 13 0 0 FH Transfers the 4 bit immediate data n4 to A register reg1 X H L D E B D Mov XA n8 Function XA n8 n8 17 9 OOH FFH Transfers the 8 bit immediate data n8 to register pair XA The string effect can be utilized When two or more of this instruction are executed in succession or when MOV 4 instruction is located continguously the string instructions following an executed instruction are processed as NOP instructions T MOV HL n8 Function HL n8 n8 17 9 00H FFH Transfers the 8 bit immediate data n8 to register pair HL The string effect can be utilized When two or more of this instruction are executed in succession the string instructions following an executed instruction are processed as NOP instructions C 7 MOV rp2 n8 Function 2 n8 8 17 0 OOH FFH Transfers the 8 bit immediate data 8 to register pair ro2 BC DE C mov A HL x C 7 MOV A HL C Mov A HL x C MOV A rpat Function A lt Register pair specified by the operand When HL is specified for the register pair Skip if L 0 When HL is sp
48. uPD750008 USER S MANUAL The column of interrupt priority in Table 6 1 indicates a priority assigned when multiple interrupt requests occur concurrently or are held A vector table contains interrupt processing start addresses and MBE and RBE setting values during interrupt processing An assembler pseudo instruction VENTn is used to set a vector table Example A vector table is set for INTBT INTA VENT1 MBE 0 RBE 0 GOTOBT PPD GPT Vector table at MBE RBE setting value Symbol for indicating address 0002 in interrupt service routine an interrupt service routine start address Caution The vector table specified by VENTn n 1 to 6 is located at address 2n Example Vector tables are set for INTBT INT4 and INTTO VENTI MBE 0 RBE 0 GOTOBT VENTS MBE 0 RBE 1 GOTOTO 186 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 6 3 VARIOUS DEVICES TO CONTROL INTERRUPT FUNCTIONS 1 Interrupt request flags and interrupt enable flags The following seven interrupt request flags IRQxxx corresponding to the interrupt sources are provided INTO interrupt request IRQO Serial interface interrupt request flag IRQCSI INT1 interrupt request flag IRQ1 Timer event counter interrupt request flag IRQTO INT4 interrupt request flag IRQ4 Timer counter interrupt request flag IRQT1 BT interrupt request flag IRQBT An interrupt request flag is to 1 by an interrupt request and is a
49. 13 bits addr 2 0000H to 17FFH and the uPD75P0016 whose program counter consists of 14 bits addr OOOOH to 3FFFH 289 uPD750008 USER S MANUAL CALLF faddr Function For the PD750008 Mk mode SP 1 lt PC7 4 SP 2 lt 5 3 lt MBE RBE 0 PC42 SP 4 lt 11 8 SP lt SP 4 PC12 9 00 4 faddr faddr OOOOH 07FFH Mk mode 5 2 lt x x MBE RBE 5 3 lt PC7 4 SP 4 lt 0 5 5 lt 0 0 0 PC42 SP 6 lt 11 8 SP SP 6 PC12 9 00 faddr faddr OOOOH 07FFH Saves the contents of the program counter PC Return address memory bank enable flag MBE and register bank enable flag RBE to the data memory location stack addressed by the stack pointer SP then branches to the location addressed by the 11 bit immediate data faddr after decrementing SP Only the address range 0000H 07FFH 0 2047 can be called C 2 TCALL addr Function Assembler pseudo instruction of the GETI instruction for table definition This instruction is used to replace a 3 byte CALL addr instruction with a 1 byte GETI instruction The 12 bit address data must be coded in addr For detailed information refer to RA75X Assembler Package User s Manual Language EEU 1363 Remark Function in this section is applicable to the uPD750008 whose program counter consists of 13 bits addr OOOOH to 1FFFH However this is also applicable t
50. 15 set to 1 the basic interval timer watchdog timer functions as a watchdog timer An internal reset signal is generated when the basic interval timer BT overflows No reset signal however is generated during the oscillation wait time following the STOP instruction has been released WDTM cannot be cleared without using reset BT is constantly incremented by the clock supplied from the clock generator It cannot be stopped from counting In the watchdog timer mode program crashes are detected using the intervals at which BT overflows The interval can be selected from among four values depending on bits 2 to 0 of BTM see Figure 5 24 Select an interval for detecting crashes according to the user system Alarge program should be divided into modules each of which can be executed within the set interval Include an instruction which clears BT at the end of each module If execution does not reach the instruction which clears BT within the set interval in which case a program error leading to a program crash may have occurred BT overflows and an internal reset signal is generated to forcibly terminate the program The occurrence of internal reset possibly means that a program crash has occurred A crash can thus be detected Set the watchdog timer as follows lt 1 gt and lt 2 gt can be performed with the same instruction lt 1 gt Set the interval in BTM lt 2 gt Set 1 in bit 3 of BTM Initial settings lt 3 gt Set 1 in WDTM 4 Af
51. 2 Test functions a Whether test request flags IRQxxx are issued can be checked with software b Release of the standby mode A test source to be released can be selected with test enable flags 6 1 CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT Figure 6 1 shows the configuration of the interrupt control circuit Each hardware item is mapped to a data memory space 183 uPD750008 USER S MANUAL eq gpueis 5 esiou 30N GINI O 4d 4UM O09d 08M 40 09 9 jeubis ZOHI 95 OZ d ZINI Duisiu CI MANI g LOUI LUNI CI OLOUI OLLNI Jojeouo d ISODUI ISOLNI e qe1 10129A i LOul O LE d LLNI 1 a OOLd OLNI o6p3 JOuA xxx3 ejqeue euJeju N3119 0410025 JO 2 71 9 184 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 6 2 TYPES OF INTERRUPT SOURCES AND VECTOR TABLES Table 6 1 lists the types of interrupt sources and Figure 6 2 shows vector tables Table 6 1 Interrupt Source
52. 210 Interrupt status flag 63 194 INTO edge detection mode register 193 INTO interrupt enable flag 187 INTO interrupt request flag 187 INT1 edge detection mode register 193 INT1 interrupt enable flag 187 INT1 interrupt request flag 187 INT2 edge detection mode register 213 INT2 interrupt enable flag 210 INT2 interrupt request flag 210 INT4 interrupt enable flag 187 INT4 interrupt request flag 187 K Key interrupt input 211 M Memory bank enable flag 21 64 Memory bank select register 21 65 P Port 0 to port 8 68 Port mode register group 75 Port mode register group B 75 Port mode register group C 75 Processor clock control register 86 Program counter 47 Program status word 62 Pull up resistor specification register group A 82 Pull up resistor specification register group B 82 317 PD750008 USER S MANUAL R IW Register bank enable flag 34 64 Wake up function specification bit 128 Register bank select register 34 65 Watchdog timer enable flag 101 S serial bus interface control register 131 Serial interface interrupt enable flag 187 Serial interface interrupt request flag 187 Serial interface operation enable disable specification bit 128 Serial operation mode register 127 Shift register 134 Signal from address comparator 128 Skip flag 63 Sl
53. 3AS8 peuBis snououuou Ag SARIS jeubis Apeoy Asna jeubis Asng s uondeooJ jenas Jaye 405 euo uoidoeooi JO S SI MOV lt g gt Lgs 10 045 uo Indino sejeoipu JOS SI QMOV lt 1 gt euDis hindino ASng snououuou AS MOV jeubis 2 JOSEN 5 Indino Bulag 10 jeuBls 739 ered I 85 085 5 s 1ndino NIS jeuBis 13H Jaye MOS U8UM 185 1 Jes s QdINO 195 1 LAND 10 085 10 Dui eJ GINO 19152 ejep sseJppe Las 085 S pe Bs Due SMO OJ jeubis JE9 D SI GAWD ADS YOS Lgs AWO ey 195 SIQ 14d 195 51 17199 10 095 10 138 Je1se N euDis eseo oJ sng uomneJedo indjno JO indino eujeu yeyo uonuyeq 2 1 SPOW 185 9u1 sjeuBis snoueA 01 5 IALL 165 S S 215 AQ Vau eui Joye 5 5 ASN eur UI 72 VAS Ja1si6e1 SARIS y ui Bu ssaJppe y YOS 10
54. 6 171 PD750008 USER S MANUAL CIO V uoissiusueJ ac jee 5 indino read BuisseooJd ASNA 185 10 085 YOS JOJSUBL a enas uondeoei eues 58 BuisseooJd E 2 TAA 05 Buisseooud Je1se N 991A9Qq 1 SEN uonejedo ejeq 0 6 e1nBiJ 172 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 10 Transfer start Serial transfer is started by writing transfer data in shift register SIO provided that the following two conditions are satisfied The serial interface operation enable disable bit CSIE is set to 1 The internal serial clock is not operating after 8 bit serial transfer or SCK is high Cautions 1 Transfer cannot be started by setting CSIE to 1 after writing data to the shift register 2 The N ch transistor needs to be turned off when data is received So FFH must be written to SIO beforehand However when the wake up function specification bit WUP is set to 1 the N ch transistor is always off So FFH need not be written to SIO beforehand for reception 3 If data is written to SIO when the slave is busy the dat
55. Automatic HL decrement 4 bit DECSL manipulation 8 bit manipulation DE 4 bit transfer Direct addressing Bit manipulation 4 bit transfer 8 bit transfer Automatic increment H mem bit Bit manipulation CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP 5 8 bit register indirect addressing HL In this addressing mode the data pointer HL register pair indirectly specifies any area in the data memory space in units of eight bits The 4 bit data at the address determined with bit O of the data pointer bit O of the L register set to 0 and the 4 bit data at the address incremented by 1 are processed as a pair on an 8 bit basis with the 8 bit accumulator XA register pair A memory bank is specified in the same way as the 4 bit register indirect addressing with the HL register specified In this case MB 5 This addressing mode can be applied to the MOV XCH and SKE instructions Examples 1 A comparison is made to determine whether the value of the count register TO of timer event counter 0 is equal to the data at addresses 30H and 31H DATA EQU 30H CLR1 MBE MOV HL DATA MOV XA TO XA lt Count register 0 SKE XA HL XA HL 2 The data memory of OOH to is cleared to 0 CLR1 CLR1 MBE MOV XA 00H MOV HL 04H LOOP MOV QHL XA HL lt INCS HL INCS HL BR LOOP 6 Bit manipulation addressing This addressing mode is used to perform bit m
56. BR MOV MOV CLR1 RETI AA MOV MOV SUBC INCS MOV MOV SUBC MOV XA BT BC XA XA BT A C LOOP A X A B LOOP 0 00 17 AA NO XA Store data in data memory BUFF XA FLAG First read Store data Second read Clear data presence flag HL BUFF A C A HL L A B A HL B A CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS MOV XA BC MOV BUFF XA Store data SET1 FLAG Set data presence flag RETI 5 4 CLOCK TIMER The 0750008 contains one clock timer which has the following functions a The clock timer sets the test flag IRQW every 0 5 seconds The IRQW can release the standby mode b Either the main system clock or the subsystem clock can be used to produce 0 5 second intervals Use a main system clock of 4 194304 MHz c The fast forward mode produces an interval 128 times faster 3 91 ms which is useful for program debugging and testing d Any of the frequencies 2 048 kHz 4 096 kHz and 32 768 kHz can be output to the P23 BUZ pin so that it can be used for sounding the buzzer and for system clock frequency trimming e The frequency divider can be cleared to start the clock from zero second 105 PD750008 USER S MANUAL 5 4 1 Configuration of the Clock Timer Figure 5 26 shows the configuration of the clock timer Figure 5 26 Block Diagram of the Clock Timer 256 Hz 3 91 ms Frequency divider E fx INTW Selector IR
57. Bits 2 and 1 are FB7H System clock control register SCC R W ael fixed to 0 FB8H EM IRQ4 IRQBT R W fmem bit me Le FCOH Bit sequential buffer 0 BSBO olo Bit sequential buffer 1 BSB1 mem bit pmem L FC2H Bit sequential buffer 2 8582 R W FC3H Bit sequential buffer 3 8583 R W Remarks 1 Interrupt enable flag 2 IRQxxx Interrupt request flag Notes 1 Only bit 3 can be manipulated by an EI DI instruction 2 Bits 3 and 2 can be manipulated bit by bit by a STOP HALT instruction 42 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3 7 pgPD7500068 I O Map 4 5 Number of bits that can be Hardware name symbol manipulated Bit R W manipulation Remarks Pull up resistor specification register group A POGA Pull up resistor specification register group B POGB Whether this location is read R W mem bit or write accessible de pends on the bit Note Whether a bit can be read or written depends on the bit 43 PD750008 USER S MANUAL 44 Figure 3 7 pPD750008 I O Map 5 5 ard bol Number of bits that can be ardware name symbol manipulated Bit Address R W suus Remarks R R W 8 Note 2 Gn Note 2 Notes 1 Bit 1 be read or written only serial operation enable mode It be read when fou
58. CHAPTER 1 GENEBADE aa dun 1 Pd FUNCTION OVERVIEW enean ed 2 t2 ORDERING INFORMATION 3 1 3 DIFFERENCES AMONG SUBSERIES 5 4 Ld IBEORCK sanded 5 1 5 lt 6 CHAPTER 2 PIN FUNCTIONS 5i aired udine a reote 9 500085 9 22 JPINGRUING TIONS eeiam 12 2220 POOPOS PORTO 12 OAR WOM de 12 222 P20 P23 PORT2 nidi 13 RSO PS To eee e 13 P40 P43 PORT4 P50 P53 PORTS 13 P60 P63 PORTO 7 ptus quee 13 229 Peo PST PORTS ta tutt auris e 13 2a MO m 13 P ZEE GUN MEO TC t 13 2205 IPOs ductu 14 221 BUZ
59. CY PORT5 0 CY OCY P50 OR1 CY PORT4 1 CY lt CY V P41 SKT BR CLRP PORT6 1 P61 lt 1 CLRP CLRI PORT6 P61 lt 0 4 bit manipulation instructions All 4 bit memory manipulation instructions including the IN OUT MOV XCH ADDS and INCS instructions can be used However before these instructions can be executed memory bank 15 must Examples 1 The contents of the accumulator are output to port 3 SEL MB15 or CLR1 MBE OUT PORTS A The value of the accumulator is added to the data output on port 5 then the result is output SET1 MBE SEL MB15 MOV HL ZPORT5 ADDS A QHL 5 NOP MOV HL A PORT5 lt 3 Whether the data on port 4 is greater than the value of the accumulator is tested SET1 MBE SEL MB15 MOV HL PORT4 SUBS A HL PORTA BR NO NO YES CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 3 8 bit manipulation instructions The MOV XCH and SKE instructions as well as the IN and OUT instructions can be used for ports 4 and 5 that allow 8 bit manipulation As with 4 bit manipulation memory bank 15 must be selected in advance Example data contained in the BC register pair is output on the output port specified by 8 bit data applied to ports 4 and 5 MBE SEL 15 IN XA PORT4 XA lt ports 5 4 MOV HL XA HL lt XA MOV _ XA BC lt BC MOV QHL XA Port L XA 77 PD750008
60. GETI instruction also has the string effect of the same group the string effect of the referenced instruction remains valid and the next instruction is skipped 297 uPD750008 USER S MANUAL Example 298 MOV HL 00H MOV XA FFH are replaced with GETI instructions CALL SUB1 BR SUB2 ORG 20H HLOO MOV HL 00H XAFF MOV XA FFH CSUB1 TCALL SUBI BSUB2 TBR SUB2 GET HLOO HL 00H 85082 SUB GETI CSUB1 CALL SUB GETI XAFF XA FFH APPENDIX A FUNCTIONS OF THE pPD75008 pPD750008 AND pPD75P0016 1 2 Program memory Masked ROM Masked ROM One time PROM 0000H 1F7FH 0000H 1FFFH 0000H 3FFFH 8064 x 8 bits 8192 x 8 bits 16384 x 8 bits Data memory 000H 1FFH 512 x 4 bits 75X standard CPU 75XL CPU equivalent to the 75X high end CPU Oscillation settling time 31 3 ms 215 fx 217 fx select Fixed to 21 fy able by a mask option When selecting the main 0 95 1 91 15 3 us 0 95 1 91 3 81 15 3 uis when operating at 4 19 system clock when operating at MHz 4 19 MHz 0 67 1 33 2 67 10 7 us when operating at 6 0 MHz When selecting the subsys 122 us when operating at 32 768 kHz tem clock E CU Instruction execution time 4 CU P21 PTO1 E P33 P30 P33 MD3 P30 MDO 23 26 GB 26 SBS register Not provided Provided SBS 3 1 Mk mode selection mal 3 0 Mk II mode selection c
61. MBE 0 memory bank 0 or 15 is automatically selected according to the addressing mode Locations in a bank is addressed by 8 bit immediate data or a register pair For details on the selection of a memory bank and addressing see Section 3 1 For how to use the particular data memory areas see the following sections and chapter General register area Section 4 5 e Stack memory area Section 4 7 Peripheral hardware area Chapter 5 Figure 4 7 Data Memory Map Data memory Memory bank Area for 000H general register 01FH 020H Data area Stack static RAM 512 x 4 100H 1FFH Not contained foo Peripheral hardware area 128 x 4 15 Note Memory bank 0 or 1 can be selected as the stack area 54 CHAPTER 4 INTERNAL CPU FUNCTIONS Data memory is undefined when it is reset For this reason it is to be initialized to zero RAM clear usually at the start of a program Remember to perform this initialization Otherwise unexpected bugs may occur Example The following program clears data at addresses 000H to 1FFH in RAM SET1 MBE SEL MBO MOV XA 00H MOV HL 04H MOV HL A Clear 04H to FFHNote INCS L BR RAMCO INCS H H lt H 1 BR RAMCO SEL MB1 RAMC1 MOV HL A Clear 100H to 1FFH INCS L L lt L 1 BR 1 INCS H 1 Note Data memory locations at OOOH to are allocated to general registers XA and HL so these
62. O O c A S Stack area Stack area 0 nOOH nFFH n 0 1 ss Stack operation for a 2 byte stack Mk mode 2 byte stack subroutine call instruction Mk mode 3 byte stack BRA addr1 Not available Mk Not available CALLA addr1 Mk II Available XA BCDE Available MOVT XA 5 BR BCDE CALL addr 3 machine cycles Mk mode 3 machine cycles Mk mode 4 machine cycles CALLF faddr 2 machine cycles Mk mode 2 machine cycles Mk Il mode machine cycles 299 PD750008 USER S MANUAL 2 2 3 channels 4 channels Basic interval timer 1 Basic interval timer watchdog timer 1 Timer event counter 1 Timer event counter 1 Clock timer 1 Timer counter 1 Clock timer 1 Clock output PCL 524 262 65 5 kHz 524 262 65 5 kHz when the main system when the main system clock operates at 4 19 MHz clock operates at 4 19 750 375 93 7 kHz MHz when the main system clock operates at 6 0 MHz BUZ output BUZ 2 4 32 kHz when the main system clock operates at 4 19 MHz 2 86 5 72 45 8 kHz when the main system clock operates at 6 0 MHz Serial interface 3 modes supported e Three wire serial mode First transferred bit switchable between the LSB and MSB e Two wire serial mode SBI mode Feedback resistor cut Can incorporate feedback Incorporated flag 505 0 resistors that are
63. O port is set by the port mode register as shown in Figure 5 7 The I O modes of ports and 6 can be set bit by bit by port mode register group A PMGA The I O modes of ports 2 4 5 and 7 can be set in units of four bits by port mode register group B PMGB The I O mode of port 8 can be set in units of two bits by port mode register group C Each port functions as an input port when the corresponding bit of the port mode register is set to 0 and functions as an output port when the same corresponding bit is set to 1 When the output mode is selected by the port mode register the contents of the output latch appear on the output pins and so the contents of the output latch must be changed to a desired value before the output mode is set An 8 bit memory manipulation instruction is used to set port mode register group A B or C A RESET signal clears all bits of each port mode register to O This means that the output buffers are set off and all ports are placed in the input mode Example P30 P31 P62 and P63 are used as input pins and P32 P33 P60 and P61 used as output pins CLR1 MBE SEL MB15 MOV 74 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 7 Formats of Port Mode Registers 81 Contents of specification Input mode Output buffer off Output mode Output buffer on Port mode register group A Address 7 6 Symbol 5 4 3 2 1 0 FE8H PM63 PM62
64. P PC 47 PCC 86 PMGA 75 PMGB 75 PMGC 75 POGA 82 POGB 82 PORTO PORTS 68 PSW 62 R RBE 34 64 RBS 34 65 RELD 133 RELT 133 319 PD750008 USER S MANUAL S SBIC 131 SBS 46 58 SCC 88 SIO 134 SKO SK1 SK2 63 SOS 93 SP 58 SVA 134 T 109 T1 110 TOEO 114 TOE1 114 TMO 112 TM1 113 TMODO 109 TMOD I 110 W WDTM 101 WM 106 WUP 128 320 APPENDIX F REVISION HISTORY Major revisions in this edition are shown below The revised chapters refer to this edition Major revisions from previous edition Revised chapters Second The 44 pin plastic QFP package was changed from All uPD750008GB xxx 3B4 to uPD750008GB xxx 3BS MTX The pPD75P0016 under development has been changed to the already developed uPD75P0016 The input withstand voltage at ports 4 and 5 during open drain was changed from 12 V to 13 V English version document numbers was added to Related Preface documents The format of the table in Section 1 3 was changed Chapter 1 The caution in using Mk mode was added in Table 4 1 Chapter 4 Differences between Mk Mode and Mk II Mode The description for the mask option when using the feedback resistor Chapter 5 was added in the section Sub oscillator control register The description for the interrupt enable flag was added in Section 6 3 Chapter 6 VARIOUS
65. PM61 PM60 PM32 PM31 PM30 PMGA P30 I O specification P31 I O specification P32 I O specification P33 I O specification P60 I O specification P61 I O specification P62 I O specification P63 I O specification Port mode register group B Address Symbol 7 6 5 4 3 2 1 0 Pw ms ewe ewe FECH PMGB Port 2 P20 P23 I O specification Port 4 P40 P43 I O specification Port 5 P50 P53 I O specification Port 7 P70 P73 I O specification Port mode register group C Address 7 6 Symbol 5 4 3 2 1 0 Port 8 P80 P81 I O specification 75 PD750008 USER S MANUAL 5 1 3 Digital I O Port Manipulation Instructions All I O ports contained in the uPD750008 are mapped to data memory space so that all data memory manipulation instructions can be used Table 5 3 lists the instructions that are particularly useful for I O pin manipulation and their application ranges 1 Bit manipulation instructions 2 76 For digital I O ports PORTO to PORTS specific address bit direct addressing fmem bit and specific address bit register indirect addressing ob mem L can be used This means that bit manipulation can be freely performed for these ports regardless of MBE and MBS settings P50 is ORed with P41 then the result is output to P61 SET1 CY CY lt 1 AND1
66. SB1 BUSY The bus release signal and command signal are output by the master BUSY is output by a slave ACK is output by either the master or a slave Normally the device which received 8 bit data outputs ACK The master continues to output the serial clock from when 8 bit data transfer starts to when BUSY is released 152 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS a Bus release signal REL When the SCK line is high the serial clock is not output the SBO or SB1 line changes from low to high This signal is called the bus release signal and is output by the master Figure 5 52 Bus Release Signal SCK SBO SB1 e This signal indicates that the master is to send an address to slave Slaves contain hardware to detect the bus release signal b Command signal CMD When the SCK line is high the serial clock is not output the SBO or SB1 line changes from high to low This signal is called the command signal which is output by the master Figure 5 53 Command Signal SCK SBO SB1 a Slaves contain hardware to detect the command signal c Address An address is 8 bit data and is output by the master to connected slaves to select a particular slave Figure 5 54 Address SCK SBO SB1 Address Bus release signal Command signal The 8 bit data following the bus release signal or command signal is defined as an address A slave detects the condi
67. SBO SI SI SB1 SO 143 PD750008 USER S MANUAL lt Sample program gt master side CLR1 MBE MOV XA 10000011B MOV CSIM XA Set transfer mode MOV XA TDATA MOV SIO XA oet transfer data and start transfer LOOP SKTCLR IRQCSI Test IRQCSI BR LOOP MOV XA SIO Read in receive data 5 6 6 Two Wire Serial Mode The two wire serial mode can be made compatible with any communication format by programming In this mode communication is basically performed using two lines Serial clock SCK and serial data input output SBO or SB1 Figure 5 47 Example of Two Wire Serial I O System Configuration 2 wire serial 2 wire serial I O Master CPU Slave CPU uPD750008 SBO SB1 Remark The 0750008 can also be used as a slave CPU 1 Register setting To set the two wire serial I O mode manipulate the following two registers Serial operation mode register CSIM Serial bus interface control register SBIC 144 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS a Serial operation mode register CSIM To use the two wire serial I O mode set CSIM as shown below For details CSIM format see 1 in Section 5 6 3 CSIM is manipulated using an 8 bit manipulation instruction Bits 7 6 and 5 of CSIM can be manipulated bit by bit When the RESET signal is input CSIM is set to OOH In the figure below hatched portions indicate the bits used in the two wire serial I O
68. The N ch open drain I O port pins of the uPD75P0016 are not connected to pull up resistors by mask option and are always open 1 2 ORDERING INFORMATION Part number uPD750004CU xxx uPD750004GB xxx 3BS MT XNote uPD750006CU xxx uPD750006GB xxx 3BS MTXNote uPD750008CU xxx uPD750008GB xxx 3BS MT XNote uPD75P0016CU uPD75P0016GB 3BS MT XNote Package 42 pin plastic shrink DIP 600 mil 44 pin plastic QFP 10 x 10 mm 42 pin plastic shrink DIP 600 mil 44 pin plastic QFP 10 x 10 mm 42 pin plastic shrink DIP 600 mil 44 pin plastic QFP 10 x 10 mm 42 pin plastic shrink DIP 600 mil 44 pin plastic QFP 10 x 10 mm Note Code orders on and after April 1 1996 can be accepted Remark xxx is a ROM code number CHAPTER 1 GENERAL On chip ROM Masked ROM Masked ROM Masked ROM Masked ROM Masked ROM Masked ROM One time PROM One time PROM PD750008 USER S MANUAL 1 3 DIFFERENCES AMONG SUBSERIES PRODUCTS Item uPD750004 uPD750006 uPD750008 uPD75P0016 Program counter 12 bits 13 bits 14 bits Program memory byte Masked ROM Masked ROM Masked ROM One time PROM 4096 6144 8192 16384 Data memory x 4 bits 512 Mask Pull up resistors at Incorporated None option ports 4 and 5 Whether to incorporate pull up resistors can Cannot be be specified incorporated Wait time during Available Not available RESET Can be selected from 217 fy or 215 fy Note Fixed to 215 fx Selection to use Yes NO feedback resis
69. The register bank select register specifies a register bank to be used as general registers a register bank can be selected from register banks 0 to 3 The RBS is set by the SEL RBn instruction n 0 to 3 A RESET signal initializes the RBS to 0 65 66 D750008 USER S MANUAL Table 4 6 Register Bank to Be Selected with the RBE and RBS RBS RBS __ RBE Register bank 2 1 0 ENEXENEXES Bank 0 is selected FIXES Bank 2 is selected Bank 3 is selected 0 0 Bankoisselected 0 t Bank tisselected Eri n 0 x Don t care CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 51 DIGITAL I O PORTS The uPD750008 employs the memory mapped I O method Thus all input output ports are mapped on the data memory space Figure 5 1 Data Memory Addresses of Digital Ports Address 3 2 1 0 FFOH PORT 0 FF1H PORT 1 FF2H PORT 2 cran PORT cran PORT 4 FFSH PORTS ro Pes Pez Peo Ponte FF7H PORT 7 par peo roars Remark Some parts can be used as static RAM Input output port manipulation instructions are as listed in Table 5 2 Ports 4 to 7 can be manipulated not only in 4 bit units but also in 8 bit or 1 bit units so that these ports can be controlled in various ways Example 1 testthe condition of P13 and output different values to ports 4 and 5 according to the test result SKT PORT1 3 Skips if bit 3 of port 1 is 1 MOV XA XA
70. This section describes an example of application which performs serial data communication in the SBI mode In the example the uPD750008 can be used as either the master CPU or a slave CPU on the serial bus The master can be switched to another CPU with a command a Serial bus configuration In the serial bus configuration used for the example of this section a uPD7500068 is connected to the bus line as a device on the serial bus Two pins on the uPD750008 are used serial data bus SBO 581 and serial clock SCK P01 Figure 5 71 shows an example of the serial bus configuration Figure 5 71 Example of Serial Bus Configuration Vpop Master CPU Slave CPU PD750008 PD750008 580 SB1 t SB 581 Address 1 SCK SCK Slave CPU SBO SB1 Address 2 Slave IC SBO SB1 Address N SCK 174 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS b Explanation of commands i Types of commands This example uses the following commands lt 1 gt READ command Transfers data from slave to master 2 WHITE command Transfers data from master to slave lt 3 gt END command Informs slave of WRITE command completion lt 4 gt STOP command Informs slave of WRITE command interruption 5b STATUS command Reads slave status 6 RESET command Sets currently selected slave as non selected slave 7 CHGMST command Passes master authority to slave ii Protocol The following protocol is us
71. USER S MANUAL Table 5 2 Pin Manipulation Instructions PORT PORT PORT PORT PORT PORT PORT PORT PORT PORT 0 1 2 3 4 5 6 7 8 A PORTn Note 1 roma e 9 we 9 9 l senrormer MOV1 PORTn LNote 2 Notes 1 MBE 0 or MBE 1 MBS 15 must be set before execution 2 low order two bits of an address and bit address are indirectly specified using the L register 78 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5 1 4 Digital Port Operation When data memory manipulation instruction is executed for a digital I O port the operation of the port and pins depends on the I O mode setting Table 5 3 This is because data taken in on the internal bus is the data input from the pins in the input mode or the output latch data in the output mode as obvious from the configurations of I O ports 1 2 Operation when the input mode is set Data from each pin is manipulated when atest instruction such as the SKT instruction a bit input instruction such as MOV1 or an instruction for taking in port data on the internal bus in units of four or eight bits such as an IN OUT arithmetic logical or comparison instruction is executed When an instruction the OUT or MOV instruction is executed to tran
72. When IRQn is set earlier than the last machine cycle of the instruction being executed In this case after executing the instruction being executed an interrupt processing of three machine cycles is executed then the interrupt service routine is started An instruction other than interrupt control instruction A is set C Interrupt processing 3 machine cycles D Interrupt service routine is executed 201 uPD750008 USER S MANUAL 6 8 EFFECTIVE USE OF INTERRUPTS The interrupt function can be used more effectively in the ways described below 1 2 3 6 9 MBE 0 is set for the interrupt service routine By allocating addresses to 7FH as data memory used by the interrupt service routine and specifying MBE 0 in an interrupt vector table the user can code a program without being concerned with a memory bank If a program must use memory bank 1 for some reason save the memory bank select register using the PUSH BS instruction before selecting memory bank 1 Use different register banks for the normal routine and interrupt routine The normal routine uses register banks 2 and 3 with RBE 1 and RBS 2 If the interrupt routine is for one nested interrupt use register bank 0 with RBE 0 so that you do not have to save or restore the registers When two or more interrupts are nested set RBE to 1 save the register bank by using the PUSH BS instruction and set RBS to 1 to selec
73. XA 246 276 SUBC XA rp 246 276 SUBS A HL 246 275 SUBS rp 1 XA 246 276 SUBS XA rp 246 275 T TBR addr 256 288 TCALL laddr 256 290 X XCH A mem 245 269 XCH A reg1 245 269 XCH A HL 245 268 XCH A HL 245 268 XCH A HL 245 268 XCH 1 245 268 XCH XA mem 245 269 XCH XA rp 245 269 XCH XA HL 245 269 XOR A n4 247 278 XOR A HL 247 278 XOR rp 1 XA 247 278 XOR XA rp 247 278 1 CY fmem bit 248 284 1 CY omem L 248 284 XOR1 CY H mem bit 248 284 316 APPENDIX E HARDWARE INDEX E 1 HARDWARE INDEX ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE NAME A Acknowledge detection flag 132 Acknowledge enable bit 132 Acknowledge trigger bit 132 B Bank select register 65 Basic interval timer 99 Basic interval timer mode register 99 Bit sequential buffer 181 BT interrupt enable flag 187 BT interrupt request flag 187 Bus release detection flag 133 Bus release trigger bit 133 Busy enable bit 132 C Carry flag 62 Clock mode register 106 Clock output mode register 97 Command detection flag 132 Command trigger bit 133 E Edge detection mode register 193 213 I Interrupt enable flag for clock timer 210 Interrupt master enable flag 189 Interrupt request flag for clock timer
74. an assembler pseudo instruction TCALL TBR is used Only an even address can be specified as taddr 296 CHAPTER 11 INSTRUCTION SET Caution All 2 byte instructions except the BRCB instruction and CALLF instruction set in the reference table must be 2 machine cycle instructions Pairs of 1 byte instructions can be set as indicated in the table below First byte instruction Second byte instruction INCS L MOV A HL DECS L MOV HL A INCS H XCH A HL DECS H INCS HL INCS E MOV A DE DECS E INCS D XCH A DE DECS D INCS DE MOV A DL INCS L DECS L XCH A DL INCS D DECS D The PC is not incremented during execution of a GETI instruction so that after a reference instruction is executed execution is resumed starting at the address immediately after the GETI instruction If the instruction immediately preceding a GETI instruction has the skip function the GETI instruction is skipped as with other 1 byte instructions If an instruction referenced with a GETI instruction has the skip function the instruction immediately following the GETI instruction is skipped If a GETI instruction references instruction having a string effect the following processing is performed e Ifthe instruction immediately preceding the GETI instruction also has the string effect in the same group the execution of the GETI instruction cancels the string effect and the referenced instruction is not skipped ftheinstruction immediately following the
75. and only the RBS needs to be saved and restored for the level two interrupt processing thus speeding up interrupt processing Table 3 3 Recommended Use of Register Banks with Normal Routines and Interrupt Routines Normal processing Use register banks 2 and 3 with RBE 1 Level one interrupt processing Use register bank 0 with RBE 0 Level two interrupt processing Use register bank 1 with RBE 1 In this case the RBS needs to be saved and restored Multiple triple or more interrupt processing Save and restore the registers with PUSH or POP 34 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3 4 Example of Register Bank Selection lt Main program gt SET1 RBE SEL RB2 gt Level one interrupt lt Level two interrupt lt Level three interrupt RBE O the RBE 1 in the 0 the vector table vector table vector table PUSH BS PUSH r SEL RB1 P 0 RB 1 RB 0 RETI POP BS POP rp RETI RETI The setting of the RBS can be modified for subroutine processing or interrupt processing by saving or restoring the RBS with the PUSH or POP instruction The RBE is set using the SET1 or CLR1 instruction The RBS is set using the SEL instruction Example SEL SET1 RBE RBE lt 1 CLR1 RBE lt 0 RBO RBS 0 RB3 RBS lt 3 SEL The general register area of the PD750008 can be used not only on a 4 bit basis but also on an 8 bit basis with register pair
76. be used to terminate main system clock generation A RESET signal clears the SCC to 0 Figure 5 13 Format of the System Clock Control Register Address 3 2 1 0 Symbol SCC3 EXE SCCO SCC SCC3 SCCO CPU clock frequency Main system clock operation Main system clock Can oscillate Subsystem clock 1 Not to be set Subsystem clock Oscillation stopped Cautions 1 A time period of up to 1 is needed to change the system clock This means that to terminate main system clock generation bit 3 of the SCC must be set to 1 when the machine cycles indicated in Table 5 4 or more have elapsed after the clock is switched from the main system clock to the subsystem clock 2 When the main system clock is used for operation setting bit 3 of the SCC to stop clock generation does not enter the normal STOP mode 3 When the is set to 0001B f4 16 do not set SCC 0 to 1 Before switch ing the main system clock to the subsystem clock be sure to manipulate the PCC so other than 0001B is set When the system operates on the subsystem clock the PCC must also be other than 0001B 4 When SCC 3 is set to 1 the X1 input pin is connected to Vss ground electric potential to prevent leakage in the crystal oscillator When an external clock is used as the main system clock never set SCC 3 to 1 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 3 System clock oscillator The main system clock oscillator operates wit
77. bit for command signal CMD trigger output By setting CMDT 1 the SO latch is cleared Then the CMDT bit is automatically cleared Bus release trigger bit W Control bit for bus release signal REL trigger output By setting RELT 1 the SO latch 15 set to 1 Then the RELT bit automatically cleared to 0 Caution Never use bits other than RELT and CMDT in the three wire serial I O mode 2 Communication operation The three wire serial 1 0 mode transfers data with eight bits as one block Data is transferred bit by bit in phase with the serial clock The shift register performs shift operation on the falling edge of the serial clock SCK Send datais latched on the SO latch and is output on the SO pin Receive data applied to the SI pin is latched in the shift register on the rising edge of SCK When eight bits have been transferred shift register operation automatically terminates setting the interrupt request flag IRQCSI 139 PD750008 USER S MANUAL Figure 5 44 Timing of Three Wire Serial Mode SCK 14 2 3 4 5 6 7 8 s KEE SO IRQCSI Completion of transfer Transfer operation is started in phase with falling edge of SCK Execution of instruction that writes data to SIO Transfer start request The SO pin becomes a CMOS output and outputs the state of the SO latch So the output state of the SO pin can be manipulated by setting the RELT bit and CMDT bit However this manipulation must
78. bit or 8 bit memory manipulation instruction Each bit may or may not allow read and or write operation Figure 5 41 When the RESET signal is generated all bits are cleared to 0 Caution Only the following bits can be used in the three wire and two wire serial I O modes Bus release trigger bit RELT Sets the SO latch Command trigger bit CMDT Clears the SO latch Figure 5 41 Format of Serial Bus Interface Control Register SBIC 1 3 Address Symbol 6 5 4 3 2 1 0 FE2H BSYE ACKT CMDD RELD RELT SBIC Bus release trigger bit W Command trigger bit W Bus release detection flag R Command detection flag R Acknowledge trigger bit W Acknowledge enable bit R W Acknowledge detection flag R Busy enable bit R W Remarks 1 R Read only 2 W Write only 3 R W Read write 131 PD750008 USER S MANUAL Figure 5 41 Format of Serial Bus Interface Control Register SBIC 2 3 Busy enable bit R W lt 1 gt The busy signal is automatically disabled lt 2 gt Busy signal output is stopped in phase with the falling edge of SCK immediately after clear instruction execution The busy signal is output after the acknowledge signal in phase with the falling edge of SCK Acknowledge detection flag R Condition for being cleared ACKD 0 Condition for being set ACKD 1 lt 1 gt The transfer operation is starte
79. bit set and reset instructions SET1 and CLR1 and bit test instructions SKT and SKF Example FLAG is set FLAG2 is reset and whether FLAGS is zero is tested FLAG EQU OSFH 1 Bit 1 at address FLAG2 EQU 087H 2 Bit 2 at address 87H FLAGS EQU OA7H 0 Bit O at address A7H SET1 MBE MBE lt 1 SEL MBO MBS lt 0 SET1 FLAG1 FLAG1 lt 1 CLR1 FLAG2 FLAG2 lt 0 SKF FLAGS FLAGS 0 23 PD750008 USER S MANUAL 24 Figure 3 2 Data Memory Organization and Addressing Range of Each Addressing Mode mem HL DE Memory bank enable flag pss 2 A 000H Area for general register 020H 07FH Data area Static RAM memory bank 0 OFFH 100 Data area Static RAM memory bank 1 1FFH Not provided F80H Peripheral hardware area FCOH memory bank 15 FFFH Remark Don t care 77 N Stack address fmem bit pmem L ing BE EKKO AS 25500000 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Table 3 1 Addressing Modes Representation Addressing mode format Specified address 1 bit direct mem bit Bit specified by bit at the address specified by MB and mem addressing When MBE 0 and mem 00H 7FH 0 mem 80H FFH MB 15 1 5 4 bit direct Address specified by MB and mem addressing When MBE 0 and mem 00H 7FH 0 mem 80H FFH
80. bits 7 to O Undefined Bit 6 at address 0000H in and bit 7 is set in MBE Stack bank selection register SBS 1000B 1000B Stack pointer SP Undefined Undefined Data memory RAM Undefined General registers X A H L D E B C Bank selection register MBS RBS Basic Counter BT interval Mode register BTM Watchdog timer enable flag g WDTM Timer Counter event counter TOEO TOUT flip flop Mode register Counter T1 Timer counter E Oui Undefined Undefined Undefined Modulo registers TMOD1 Mode register TM1 TOUT flip flop OO Mode register WM OO ft Shift register SIO Undefined Serial interface Operation mode register CSIM SBI control register SBIC o Slave address register SVA Undefined Note Data of address OF8H to OFDH of the data memory becomes undefined when the RESET signal is generated 226 CHAPTER 8 RESET FUNCTION Table 8 1 Statuses of the Hardware after a Reset 2 2 Generation of a RESET Generation of a RESET Hardware i signal in a standby mode signal during operation Clock Processor clock control register generator PCC clock System clock control register output SCC circuit d Clock output mode register CLOM Sub oscillator control register SOS interrupt Interrupt request flag enable flag aT registers IMO IM1 IM2
81. by specifying an operand 3 Interrupt status flag IST1 ISTO The interrupt status flag is a 2 bit flag used to store the status of processing being performed See Table 6 3 for details 63 PD750008 USER S MANUAL Table 4 5 Information Indicated by the Interrupt Status Flag IST1 ISTO Status of processing Processing and interrupt control being performed 0 Status 0 Normal program processing is being performed Any interrupts are acceptable 0 1 Status 1 A lower or higher priority interrupt is being serviced Higher priority interrupts are acceptable 1 Status 2 A higher priority interrupt is being serviced No interrupts are acceptable 1 1 Not to be set The interrupt priority control circuit Figure 6 1 checks this flag to control multiple interrupts The contents of the IST1 and ISTO are saved as part of the PSW to stack memory if an interrupt is accepted then are automatically set to a one step higher status The RETI instruction restores the contents present before an interrupt occurs The interrupt status flag can be manipulated using a memory manipulation instruction and the status of processing being performed can be changed by program control Caution The user must always disable interrupts with the DI instruction before manipulating this flag and must enable interrupts with the El instruction after manipulating this flag 4 Memory bank enable flag MBE The memory bank enable flag is a 1 bit flag used t
82. counting status C d SA gt e 5 5 1 Configuration of timer event counter Figures 5 28 and 5 29 shows the configuration of the timer event counter 108 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS jeubis lt OLOUI 13534 jeubis Wels ms ae 0108 8 4 151 a OLLNI Jang E C g soyeuedwog pues 0 8 19481691 ojnpoy l ZOWL SOWL SOWL son eiqeue OL 19 c 0 1 OWL 8 0 jauueyyd ADJUNOD 1u9 3 1oUul y jo 12019 8 6 ni X d IN J01eJouoD yoojo UJOJ J lt lt 011 1ndu JONG 109 PD750008 USER S MANUAL jeubis 1104 19534 Wels uonejedo 195 vai Joyesauab 90 9 I 108 8 1 uno Bus jndino iiid LOLd LZd 45 C E 8 soyesredwio5 bey 8 4 1 1 c LHALIEEHAL TEHALISLEN L om OL LeLdOd GDWd 10 c 1 Jouueu2 eu YOO G 62 6 110 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 1 Timer event counter mode register TM1 The mode register is an 8 bit register which
83. input KRO KR3 KR4 KR7 Note Provided only in the uPD75P0016 Port 3 is a large current output Ports 4 and 5 are N ch open drain intermediate withstand voltage 13 V large current output These ports can directly drive the LED An mode is selected by the port mode register The I O mode of port m m 2 4 5 and 7 can be selected in units of 4 bits and the I O mode of ports 3 and 6 can be selected bit by bit Port n can be connected with built in pull up resistors in units of 4 bits by software This can be done by manipulating pull up resistor specification register group A POGA For ports 4 and 5 the use of built in pull up resistors can be specified bit by bit by mask option Ports 4 and 5 and ports 6 and 7 can be paired respectively for 8 bit I O A RESET input clears the output latches in the ports places port n in the input mode output high impedance state and drives ports 4 and 5 high if pull up resistors are provided or causes ports 4 and 5 to go into a high impedance state 2 2 3 P80 P81 PORTS These pins are the I O pins of the 2 bit I O ports with output latches Port 8 Port 8 can be connected with built in pull up resistors in units of 2 bits by software This can be done by manipulating pull up resistor specification register group B POGB 2 2 4 Input Pin Used Also for Port 1 This is an external event pulse input pin for the programmable timer event counter A Schmitt triggered input is used for
84. instruction codes in the operand field indicates that there are three types of bit manipulation addressing fmem bit pmem L and H mem bit The table below lists the second byte of an instruction code corresponding to the above addressing Second byte of instruction code Accessible bits fmem bit Bo Fo F Fo FBOH FBFH manipulatable bits Bo F5 Fo Fy Fo FFOH FFFH manipulatable bits pmem L 1 0 Go Go FCOH FFFH manipulatable bits H mem bit D D Do Manipulatable bits of accessible memory bank Br Immediate data for bit Immediate data for Low order four bits of address Gn Immediate data for pmem Bits 2 to 5 of address Di Immediate data for mem Low order four bits of address 259 uPD750008 USER S MANUAL Instruction code Mne Instruction Operand monic aon ees e s eua Damm 101 0 09 0 Do mma 10 01001 7 ao r o11 00 01111 mmm 7 me reverevelerer nmm e a wm mes ire i mem 0 0 0 0 0 0200 7 me revererelereeenmnl _ ewe wee ire io io 260 CHAPTER 11 INSTRUCTION SET Instruction code Instruction monic
85. lt 18H MOV XA XA lt 14H SEL 15 Or CLR1 MBE OUT PORTA XA Port 5 4 XA otring effect instructions 2 SET1 PORTA L Sets the bit s specified by the L register in ports 4 to 7 to 1 67 PD750008 USER S MANUAL 5 1 1 Types Features and Configurations of Digital Ports Table 5 1 lists the types of digital I O ports Figures 5 2 to 5 6 show the configurations of the ports Table 5 1 Types and Features of Digital Ports Port name 4 bit 1 O Allows read and test at any timeregard Also used as INT4 SCK SO SBO less of the operation modes of another and 5 581 functions assigned to these pins PORT 1 Also used as INTO to INT2 and TIO PORTSNote 1 4 bit I O Allows input or output mode setting bit Also used as MDO to MD3Note 2 by bit PORT6 Also used as KRO to KR3 PORT2 Ports 6 and 7 can be paired allowing Also used as PTOO PTO1 PCL data in units of 8 bits Allows input and BUZ or output mode setting in units of 4 bits PORT7 Also used as KR4 to KH7 PORT4Note 1 4 pit I O Allows input or output mode setting in Whether to use pull up resistors PORT5Note 1 N ch open drain units of 4 bits Ports 4 and 5 be can be specified bit by bit with a can withstand paired allowing data I O in units of mask optionNote 3 13V 8 bits PORTS 2 bit I O Allows input or output mode setting in units of 2 bits Notes 1 Can directly drive the LED 2 Only for th
86. manipulated by specifying BSBO or BSB2 181 PD750008 USER S MANUAL Example output 16 bit data of BUFF1 and BUFF2 serially from bit 0 of port CLR1 MBE MOV XA BUFF1 MOV BSBO XA Set BSBO and 5 1 MOV XA BUFF2 MOV BSB2 XA Set BSB2 and BSB3 MOV 0 LOOPO SKT BSBO L Tests the specification bit of BSB BR LOOP 1 NOP Dummy For timing adjustment SET1 PORTS3 0 Sets bit 0 of port BR LOOP2 LOOP1 PORT3 0 Clears bit 0 of port NOP Dummy For timing adjustment NOP LOOP2 INCS L lt 1 BR LOOPO RET 182 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS The uPD750008 has seven vectored interrupt sources and two test inputs allowing a wide range of applications In addition the interrupt control circuitry of the uPD750008 has the following features for very high speed interrupt processing 1 Interrupt functions a Hardware controlled vectored interrupt function which can control whether or not to accept an interrupt using the interrupt flag IExxx and interrupt master enable flag IME b The interrupt start address can be set arbitrarily c Multiple interrupt function which can specify the priority by the interrupt priority specification register IPS d Test function of an interrupt request flag IRQxxx The software can confirm that an interrupt occurred e Release of the standby mode Interrupts released by an interrupt enable flag can be selected
87. manual is intended for engineers who want to learn the capabilities of the uPD750004 uPD750006 uPD750008 and uPD75P0016 to develop application systems based on them The purpose ofthis manual isto help users understand the hardware capabilities shown below of the uPD750004 uPD750006 uPD750008 and 075 0016 This manual is roughly divided as follows General Pin functions Architecture feature and memory map Internal CPU functions Peripheral hardware functions Interrupt and test functions Standby function Reset function Writing to and verifying program memory PROM Mask option Instruction set Readers of this manual should have general knowledge of the electronics logical circuit and microcomputer fields e For users who have used the uPD75008 gt See Appendix A to check for any difference in the functions and read the explanation of those differences o check the functions of an instruction in detail when the reader knows its mnemonics See the instruction index in Appendix D To check the functions of specific internal circuits etc See Appendix E To understand the overall functions of the uPD750004 uPD750006 uPD750008 and uPD75P0016 Head through all chapters sequentially Notation Data bit significance Active low Memory map address Note Caution Remark Important and emphasized matter Numeric value Higher order bits
88. memory is used for storing programs an interrupt vector table GETI instruction reference table table data and so forth The uPD750004 uPD750006 and uPD750008 are provided with mask programmable ROM as the program memory and the uPD75P0016 is provided with a one time PROM Figures 4 3 to 4 6 show the program memory maps Program memory is addressed by the program counter Table data can be referenced using the table reference instruction MOVT Figures 4 3 to 4 6 also show the allowable branch address ranges for the branch instructions and subroutine call instructions The relative branch instruction BR addr allows a branch to addresses contents of the PC less 15 to one or plus two to 16 regardless of block The program memory is located at following addresses 0000H to OFFFH 0000H to 17FFH 0000H to 1FFFH e 0000H to 3FFFH uPD750004 uPD750006 uPD750008 uPD75P0016 The following addresses are assigned to special functions All areas excluding 0000H and 0001H can be used as normal program memory 0000H to 0001H Vector address table for holding the RBE and MBE values and program start address when a RESET signal is issued allowing a reset start at an arbitrary address 0002H to 000DH Vector address table for holding the RBE and MBE values and program start address for each vectored interrupt allowing interrupt processing to be started at an arbitrary address 0020H to 007FH Table area referenc
89. mode allows full duplex transmission so data transfer can be performed at higher speed The user can choose 8 bit data transfer starting with the MSB or LSB so devices starting with either the MSB or LSB can be connected The three wire serial mode enables connections to be made with the 75XL series 78K series and many other types of peripheral I O devices Two wire serial mode In this mode 8 bit data is transferred through two lines Serial clock SCK and serial data bus SBO or SB1 By controlling output levels on the two lines by software communication with multiple devices is enabled The output levels of SCK and SBO or SB1 can be controlled by software so the user can match an arbitrary transfer format This means thata line that has been required for handshaking to connect multiple lines can be eliminated for more efficient input output port utilization Serial bus interface SBI mode In this mode communication with multiple devices can be performed using two lines Serial clock SCK and serial data bus SBO or SB1 This mode conforms to the NEC serial bus format In this mode the transmitter can output on the serial data bus an address for selecting a device subject to serial communication commands directed to the remote device and data The receiver can identify an address commands and data from received data by hardware This function enables more efficient input output port utilization as in the case of
90. normal serial clock output The number of SCK pulses can be software set arbitrarily by manipulating the PO1 output latch The SO SBO PO2 or SI SB1 P03 pin is controlled by manipulating the RELT and CMDT bits of SBIC The procedure for manipulating output is explained below lt gt Set serial operation mode register CSIM SCK pin output mode When serial transfer is halted SCK from the serial clock control circuit is set to 1 2 Manipulate the output latch by using a bit manipulation instruction 179 PD750008 USER S MANUAL Example To output one 5 1 pin clock cycle by software SEL MOV MOV CLR1 SET1 5 gt To internal circuit MB15 or CLR1 MBE 10000011 SCK fy 23 output mode CSIM XA OFFOH 1 01 lt 0 OFFOH 1 SCK P01 lt 1 Figure 5 80 SCK P01 Pin Circuit Configuration Address FFOH 1 From the serial clock control circuit SCK SCK pin output mode The output latch is mapped to bit 1 of address FFOH A RESET signal sets the 01 output latch to Cautions 1 180 During normal serial transfer the P01 output latch must be set to 1 2 The P01 output latch cannot be addressed by specifying PORTO 1 as described below The address of the latch OFFOH 1 must be coded in the operand of an instruction directly However MBE 0 or MBE 1 MBS 15 must be specified before the instruction is execu
91. not be performed during serial transfer The output level of the SCK be controlled by manipulating the P01 output latch in the output mode internal system clock mode See Section 5 6 8 3 Serial clock selection To select the serial clock manipulate bits 0 and 1 of serial operation mode register 0 CSIM The serial clock can be selected out of the following four clocks Table 5 7 Serial Clock Selection and Application In the Three Wire Serial Mode Timing for shift register R W and CSIM CSIM Masking of Application External Automatically In the operation halt mode Slave CPU SCK masked when CSIE 0 8 bit data When the serial clock is 1 TOUT transfer is masked after 8 bit transfer Half duplex asyn flip flop completed When SCK is high chronous transfer software control 1 fx 24 Middle speed serial transfer 1 1 fx 23 High speed serial transfer 140 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 4 Signals Figure 5 45 shows operations of RELT and CMDT Figure 5 45 Operations of RELT and CMDT SO latch RELT C CMDT 5 Switching between MSB and LSB as the first transfer bit The three wire serial I O mode has a function that can switch between the MSB and LSB as the first bit of transfer Figure 5 46 shows the configuration of shift register SIO and internal bus As shown in Figure 5 46 read or write operation can be performed by switching between the MSB and LSB This switching c
92. release trigger bit W Control bit for bus release signal REL trigger output By setting RELT 1 the SO latch is set to 1 Then the RELT bit automatically cleared to 0 Caution Never clear SBO or SB1 during serial transfer Be sure to clear SBO or SB1 before or after serial transfer 4 Serial clock selection To select the serial clock manipulate bits 0 and 1 of serial operation mode register CSIM The serial clock can be selected out of the following four clocks Table 5 9 Serial Clock Selection and Application In the SBI Mode Timing for shift register R W and T CSIM CSIM Masking of Application External Automatically In the operation halt mode Slave CPU SCK masked when CSIE 0 8 bit data When the serial clock is TOUT transfer is masked after 8 bit transfer Arbitrary speed flip flop completed When SCK is high serial transfer 1 fx 24 Middle speed serial transfer 1 1 1 23 High speed serial transfer When the internal system clock is selected SCK is internally terminated when the 8th clock has been output and is externally counted until the slave enters the ready state 5 Signals Figures 5 60 to 5 65 show signals to be generated in the SBI mode and flag operations on the SBIC Table 5 10 lists signals used in the SBI mode 160 SIO SCK SO latch RELT CMDT RELD CMDD SIO SCK SO latch RELT Master CMDT Master RELD CMDD CHAPTER 5 PERIPHERAL HARDWA
93. specified with the mask option Sub oscillator current cut Not provided Incorporated flag SOS 1 Register bank selection register Not provided Provided RBS Number of vectored interrupts External 3 internal 3 External 3 internal 4 Processor clock control register Available when PCC is 0 Available when PCC is 0 to 3 2 3 Power supply voltage 2 7 to 6 0 V 2 2 to 5 5 V Operating ambient temperature Ta 40 to 85 C Package 42 pin plastic shrink DIP 600 mil 44 pin plastic QFP 10 x 10 mm SOS register 300 APPENDIX B DEVELOPMENT TOOLS The following development tools are provided for the development of a system which employs the uPD750008 In the 75XL series use the common relocatable assembler together with a device file of each model RA75X relocatable assembler Part number Distribution media PC 9800 series MS DOS 3 5 inch 2HD US5A13RA75X Ver 3 30 to 5 25 inch 2HD uS5A10RA75X Ver 6 2Note PC AT and See OS for IBM 3 5 inch 2HC US7B13RA75X compatibles PC 5 25 2HC 157 10 75 Device file Part number IUS PC 9800 series MS DOS 3 5 inch 2HD uS5A13DF750008 Ver 3 30 to 5 25 inch 2HD uS5A10DF750008 Ver 6 2Note PC AT and See OS for IBM 3 5 inch 2HC US7B13DF750008 compatibles PC 5 25 inch 2HC uS7B10DF750008 Note These software products cannot use the task swap function which is available in MS DOS Ver 5 00 or la
94. symbols used for the addressing area column MB MBE MBS MBS 0 1 15 MB 0 MBE 0 MB 0 00H 7 15 F80H FFFH Data memory addressing MBE 1 MB MBS MBS 0 1 15 MB 15 fmem FBOH FBFH FFOH FFFH MB 15 pmem FCOH FFFH uPD750004 addr addri 0000H OFFFH uPD750006 addr addr1 OOOOH 17FFH uPD750008 addr addr1 OOOOH 1FFFH UPD75P0016 addr addr1 0000H 3FFFH addr addr1 Current PC 15 to Current PC 1 Current PC 2 to Current PC 16 uPD750004 caddr 0000H OFFFH uPD750006 caddr 0000H OFFFH PCi2 0 or 1000H 17FFH 1 uPD750008 caddr 0000H OFFFH 2 0 or 1000H 1FFFH PC 1 uPD75P0016 caddr 0000H OFFFH PCs PC12 008 1000H 1FFFH PC s PC12 018 Program memory addressing 2000H 2FFFH PCi3 PC12 108 3000H PCi3 PCi2 118 faddr OOOOH 07FFH taddr 0020H 007FH For MkII mode only 0000H OFFFH uPD750004 OOOOH 17FFH uPD750006 0000H 1FFFH uPD750008 OOOOH 3FFFH uPD75P0016 Remarks 1 MB represents an accessible memory bank 2 For 2 MB 0 regardless of the setting of MBE and MBS 3 For 4 and 5 MB 15 regardless of the setting of MBE and MBS 4 Each of 6 to 10 indicates an addressable area 243
95. system clock operates at 4 19 MHz 0 67 1 33 2 67 10 7 us when the main system clock operates at 6 0 MHz 122 us when the subsystem clock operates at 32 768 kHz 4096 x 8 bits uPD750004 6144 x 8 bits uPD750006 8192 x 8 bits uPD750008 16384 x 8 bits UPD75P0016 512 x 4 bits When operating in 4 bits 8 x 4 banks When operating in 8 bits 4 x 4 banks 34 CMOS input pins Can incorporate 25 pull up resistors 18 CMOS I O pins that are specified with the software Four pins can directly drive the LED N ch open drain I O pins Eight pins can directly drive the LED Can withstand 13 V Can incorporate pull up resistors that are specified with the mask option Note 4 Timer event counter 1 channel Timer counter 1 channel Basic interval timer watchdog timer 1 channel Clock timer 1 channel e Three wire serial mode switchable between the start LSB and the start MSB Two wire serial mode SBI mode 16 bits 524 kHz 262 kHz 65 5 kHz when the main system clock operates at 4 19 MHz 750 kHz 375 kHz 93 7 kHz when the main system clock operates at 6 0 MHz External 3 Internal 4 External 1 Internal 1 Ceramic or crystal oscillator for the main system clock Crystal oscillator for the subsystem clock STOP HALT mode 40 to 85 C Vpp 2 2 to 5 5 V 42 pin plastic shrink DIP 600 mil 44 pin plastic QFP 10 x 10 mm Note
96. wire serial mode a Data is transferred starting with the MSB on a transfer clock of 262 kHz during 4 19 MHz operation Master operation lt Sample program gt CLR1 MBE MOV XA 10000010B MOV CSIM XA Set transfer mode MOV XA TDATA TDATA is transfer data storage address MOV SIO XA Set transfer data and start transfer Caution A second or subsequent transfer can be started by setting data SIO MOV SIO XA or XCH XA SIO uPD750008 uPD7225G LCD controller driver etc SCK SCK SO SBO SI In this case the SI SBI pin on the uPD750008 be used as an input 142 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS b Data is transmitted and received starting with the LSB on an external clock slave operation In this case the function of inverting the MSB LSB is used for shift register read write operation 750008 Other microcomputers PO1 SCK x SCK SI SB1 SO SO SBO gt SI Sample program Main routine CLR1 MBE MOV XA 84H MOV CSIM XA Serial operation halt MSB LSB invert mode external clock MOV XA TDATA MOV SIO XA Set transfer data and start transfer El IECSI El Interrupt routine MBE 0 MOV XA TDATA XCH XA SIO Start to transfer receive data and transmit data MOV RDATA XA Save receive data RETI c Data is transmitted and received at high speed by using a transfer clock of 524 kHz during 4 19 MHz operation uPD750008 master uPD75206 etc SCK SCK SO
97. wire serial I O mode set CSIM as shown below For details on CSIM format see 1 in Section 5 6 3 CSIMO is manipulated using an 8 bit manipulation instruction Bits 7 6 and 5 of CSIM can be manipulated bit by bit When the RESET signal is input CSIM is set to OOH In the figure below hatched portions indicate the bits used in the three wire serial I O mode Address FEOH 7 6 5 4 3 2 0 CSIE CSIM3 CSIM2 CSIM O _ Serial clock selection bit W Serial interface operation mode selection bit W Wake up function specification bit W Match signal from address comparator R Serial interface operation enable disable specification bit W Remark R Read only W Write only 137 PD750008 USER S MANUAL Serial interface operation enable disable specification bit W Wien Shift register operation Serial clock counter IRQCSI flag SO SBO and 8151 pins and SI SB1 pins CSIE Shift operation enabled Count operation Can be set Used in each mode as well as for port O Signal from address comparator R CO Note Condition for being cleared COI 0 Condition for being set COI 1 When the slave address register SVA When the slave address register SVA does not match the data of the shift register matches the data of the shift register Note can be read only before serial transfer is started or after serial transfer is completed A
98. 0 0 12 SP 2 x x MBE RBE 12 0 taddr 4 9 taddr 1 SP SP 6 When an instruction other than the TBR or TCALL instruction is used Execution of taddr taddr 1 instruction Depends on the referenced instruction e uPD75P0016 When the TBR instruction is used PC43 9 taddr s5 9 taddr 1 When the TCALL instruction is used SP 6 SP 3 SP 4 lt 11 SP 5 lt 0 0 PC45 12 5 2 lt x x MBE RBE PC43 9 taddr s5 9 taddr 1 SP SP 6 When an instruction other than the TBR or TCALL instruction is used Execution of taddr taddr 1 instruction Depends on the referenced instruction The other portions are The TBR and TCALL instructions are assembler pseudo instructions to define tables used for 257 uPD750008 USER S MANUAL 11 3 INSTRUCTION CODES OF EACH INSTRUCTION 1 Explanations of the symbols for the instruction codes rp u O mt X gt addressing reg pair pe o m a ede I Immediate data for n4 n8 Dn Immediate data for mem Bn Immediate data for bit Immediate data for n or IExxx Th Immediate data for taddr x 1 2 Immediate data for the address 2 to 16 relative to branch destination address minus one Sn Immediate data for the one s complement of the address 15 to 1 relative to the branch destination address 258 CHAPTER 11 INSTRUCTION SET 2 Bit manipulation addressing
99. 008 The items in the figure have the following meanings Symbol Name representing incorporated hardware which can be coded in the operand field of an instruction R W Indicates whether the hardware allows read write operation R W Both read and write operations possible R Read only W Write only Number of manipulatable bits Indicates the number of bits that can be processed at a time in hardware manipulation O Bit manipulation is possible in units of the indicated number of bits 1 4 or 8 bits D Particular bits can be manipulated For these bits see Remarks Bit manipulation is impossible units of the indicated number of bits 1 4 or 8 bits Bit manipulation addressing Bit manipulation addressing applicable in hardware bit manipulation 39 PD750008 USER S MANUAL Figure 3 7 0750008 I O 1 5 Number of bits that can be Hardware name symbol manipulated Bit Address manipulation Remarks F80H Bit 0 is fixed to 0 E Stack pointer SP Register bank selection register RBS F83H Memory bank selection register MBS F85H Basic interval timer mode register BTM pw a of memi d 2 Ett Clock mode register WM Notes 1 Can be manipulated separately as the RBS and MBS in 4 bit units Can also be manipulated as the BS in 8 bit units Use SEL MBn and SEL RBn instructions to write data to MBS and RBS respectively 2 WDTM Watchdog timer enable flag W canno
100. 1 c2 c3 lt 4 gt Commercial ON line voltage OFF pin voltage oid RESET signal Wait Note 1 System clock Y f x fx f xr f x 10 7 ps 0 67 us 122us 0 67 5 Internal reset fx 6 00 MHz operation fxt 32 768 kHz A RESET signal starts CPU operation at the lowest speed of the main system clock 10 7 us at 6 00 MHz 15 3 us at 4 19 MHz after a wait timeNote 1 for stable oscillation The PCC is rewritten for highest speed operation after a time elapse which is sufficient for the voltage on the Vpp pin to be high enough for highest speed operation The removal of commercial current is detected using for example an interrupt inputNote 2 then bit 0 of the SCC is set to 1 to operate with the subsystem clock In this case subsystem clock generation must have been started After a time 46 machine cycles required to switch to the subsystem clock elapses bit 3 of the SCC is set to 1 to terminate main system clock generation After detecting the input of commercial current by using an interrupt bit 3 of the SCC is cleared to start main system clock generation After a time required for stable generation bit 0 of the SCC is cleared to 0 to operate at the highest speed Notes 1 The following two wait times can be selected by a mask option 217 f 21 8ms at 6 00 MHz 31 3ms at 4 19 MHz 215 fy 5 46ms at 6 00 MHz 7 81ms at 4 19 MHz However the uPD75P0016 does not have a mask option and its wa
101. 1 PD750008 USER S MANUAL 2 Application of the HALT mode at fy 4 19 MHz Intermittent operation under the following conditions The main system clock is switched to the subsystem clock on the falling edge of INT4 The oscillation of the main system clock is stopped and HALT mode is set Inthe standby mode intermittent operation is performed at intervals of 0 5 5 e The subsystem clock is switched back to the main system clock on the rising edge of 4 INTBT is not used lt Timing chart gt Voltage on POO INT4 Intermittent operation Operating mode Operating mode HALT mode low speed operation low speed high speed Operating mode 3 CPU operation INT4 INT4 222 lt Sample program gt Initialization Main routine MAIN MOV MOV MOV MOV El El El SKT HALT NOP SKTCLR BR CALL INT4 service routine VINT4 WAIT 1 PDOWN WAIT2 SKT BR CLR1 MOV MOV SKT BR SKT BR CLR1 SET1 MOV INCS BR SET1 A 0011B PCC A XA 05 4 IEW PORTO O IRQW MAIN WATCH PORTO O PDOWN SCC 3 A 8 BIM A IRQBT WAIT 1 0 PDOWN SCC 0 SCC 0 A 6 WAIT2 SCC 3 CHAPTER 7 STANDBY FUNCTION High speed mode Subsystem clock Enable interrupt Power normal Power down mode Power normal Flag set for 0 5 second Clock subroutine Power n
102. 2 Timer event counter time setting Timer setup time cycle is found by dividing modulo register contents 1 by count pulse CP frequency selected by setting the mode register n4 1 T sec n 1 resolution T sec Timer setup time seconds fcp Hz Count pulse frequency Hz n Modulo register content n 0 Once the timer is set interrupt request signal IRQTn is generated at the intervals set in the timer Table 5 6 lists the resolution and longest setup time time when is in the modulo register for each count pulse to the timer event counter Table 5 6 Resolution and Longest Setup Time a When timer event counter channel 0 Mode register At 6 00 MHz At 4 19 MHz 06 05 04 Longest setup time Longest setup time 6 When timer counter channel 1 Mode register At 6 00 MHz At 4 19 MHz TM15 TM14 setup time Longest setup time 117 PD750008 USER S MANUAL 3 118 Timer event counter operation The timer event counter operates as follows Figure 5 35 shows the configuration of the timer event counter lt 1 gt The count pulse CP is selected by setting the mode register TMn and is input to the count register Tn lt 2 gt The Tn is compared with the modulo register TMODn and if they are equal a match signal is generated and the interrupt request flag IRQTn is set Atthe same time the timer o
103. 4 bit data at the address incremented by 1 are processed as a pair on an 8 bit basis with the 8 bit accumulator XA register pair A memory bank is specified in the same way as the 4 bit direct addressing This addressing mode can be applied to the MOV XCH IN and OUT instructions Example 1 Eight bit data from port 4 and port 5 is transferred to addresses 20H and 21H DATA EQU 020H CLR1 MBE MBE lt 0 IN XA PORT4 X lt PORT5 A lt PORTA MOV DATA XA 21H lt X 20H lt 4 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Example 2 Eight bit data is latched into the serial interface shift register SIO and the transfer data is set at the same time SEL MB15 MBS 15 XCH XA SIO XA lt gt SIO 4 bit register indirect addressing rpa In this addressing mode the pointer general register pair specified in the operand of an instruction indirectly specifies a data memory space in units of four bits There are three types of data pointers One is the HL register pair which can specify any area in the data memory space when MB 5 15 specified The other two are the DE register pair and DL register pair with which memory bank 0 is always used regardless of how the MBE and MBS are specified More efficient programming is possible by selecting a data pointer according to a data memory bank to be used When the HL register pair is specified the L register can be incremented or dec
104. 6 and 8 in Section 5 6 7 5 6 4 Operation Halt Mode The operation halt mode is used when serial transfer is not performed This mode reduces power consumption The shift register does not perform shift operation in this mode so the shift register can be used as anormal 8 bit register When the RESET signal is entered the operation halt mode is set The P02 SO SBO pin and PO3 SI SBI pin function as input only port pins The 01 5 pin can be used as an input port pin by setting the serial operation mode register 1 Register setting To set the operation halt mode manipulate serial operation mode register CSIM For details on CSIM format see 1 in Section 5 6 3 CSIM is manipulated with an 8 bit manipulation instruction Only the CSIE bit of CSIM can be independently manipulated CSIM can also be manipulated using the name of each bit When the RESET signal is entered CSIM is set to 00H In the figure below hatched portions indicate bits used in the operation halt mode 135 PD750008 USER S MANUAL Address FEOH 7 6 5 4 3 2 1 0 CSIE CSIM3 CSIM2 CSIM1 CSIMO CSIM e ea Serial clock selection bit W Note Serial interface operation mode selection bit W Wake up function specification bit W Match signal from address comparator R Serial interface operation enable disable specification bit W Note The status of the 01 5 pin is selectable Remark R Read only
105. 72 POL sions Esci iod das 73 Formats of Port Mode 75 Pull Up Resistor Specification Register 82 Figure No 5 9 5 10 5 11 5 12 5 13 5 14 5 15 5 16 5 17 5 18 5 19 5 20 5 21 5 22 5 23 5 24 5 25 5 26 5 27 5 28 5 29 5 30 5 31 5 32 5 33 5 34 5 35 5 36 5 37 5 38 5 39 5 40 5 41 5 42 5 43 5 44 LIST OF FIGURES 2 4 Title Page O Timing Ghart of Digital OP OMS macase cot aD eset 82 ON Timing Chart of Built in Pull Up Resistor Connected by Software 83 Block Diagram of the Clock Generator 84 Format of the Processor Clock Control 87 Format of the System Clock Control 88 External Circuit for the Main System Clock Oscillator 89 External Circuit for the Subsystem Clock 89 Examples of Oscillator Connections Which Should Be Avoided 90 Subsystem Glock OSCILO 92 Sub Oscillator Control Register SOS 93 Changing the System Clock and CPU 95 Gonfig raton of the Glock Output
106. 74HC04 H xe Crystal or ceramic resonator Standard frequency 4 194304 or 6 0 MHz 15 PD750008 USER S MANUAL 2 2 14 XT1 XT2 These pins are used for connection to a crystal for subsystem clock oscillation An external clock can also be applied a Crystal oscillation b External clock uPD750008 0750008 External XT1 clock XT2 Crystal Standard frequency 5 768 kHz 2 2 15 RESET This is the pin for active low reset input The RESET input is asynchronous When a signal with certain low level width is applied to the pin a RESET signal is generated to cause a system reset which has priority over any other operations The RESET signal is used for normal CPU initialize start operation and is also used to release the standby STOP or HALT mode A Schmitt triggered input is used for the RESET input pin 2 2 16 Vpp This is the positive power supply pin 2 2 17 Vss This is the ground pin 16 CHAPTER 2 PIN FUNCTIONS 2 2 18 IC for the 0750004 0750006 and 750008 only The internally connected IC pin is used to set the uPD750008 to test mode for inspection prior to shipping In normal operation connect the IC pin to the Vpp pin keeping the writing as short as possible When the wiring between the IC pin and the Vpp pin is too long or noise is generated on the IC pin a potential difference may occur between the IC pin and the Vpp pin This may cause your program to malfunction
107. A n4 Function A 4 04 13 0 Exclusive ORs the contents of the A register with the 4 bit immediate data n4 then sets the result in the A register Example The high order four bits of an accumulator is inverted XOR A 1000B C XOR A HL Function A lt v HL Exclusive ORs the contents of the A register with the data at the data memory location addressed by the HL register pair then sets the result in the A register C 2 XOR XA rp Function XA lt XA vrp Exclusive ORs the contents of the XA register pair with the contents of register pair ro XA HL DE BC XA HL DE BC then sets the result in the XA register pair C 2 rp 1 XA Function 1 XA Exclusive ORs the contents of register pair 1 HL DE BC XA HL DE BC with the contents of the XA register pair then sets the result in register pair rp 1 278 CHAPTER 11 INSTRUCTION SET 11 4 5 Accumulator Manipulation Instructions RORC A Function CY lt Ag lt An lt CY n 1 3 Rotates the contents of the A register 4 bit accumulator through the carry flag one bit position to the right A C 2 1 0 3 Before 1 execution of lt NA S RORC A 2224 Function A A Obtains the one s complement of the A register 4 bit accumulator that is inverts each bit of the A register 11 4 6 Increment Decrement Instruc
108. ANUAL 11 4 FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONS This section explains functions and applications of the instructions For the uPD750004 0750006 uPD750008 and uPD75P0016 usable instructions and their functions Mk mode are different from those in Mk Il mode Read the following explanation How to read C 2 Can be used in both Mk I mode and Mk II mode for the uPD750004 uPD750006 uPD750008 and uPD75P0016 CD Can be used in only Mk mode for the PD750004 PD750006 PD750008 and uPD75P0016 Ci Can be used in only Mk II mode for the uPD750004 uPD750006 uPD750008 and uPD75P0016 Can be used in both Mk I mode and Mk II mode for the uPD750004 uPD750006 uPD750008 and uPD75P0016 However Mk mode is different from Mk mode in the functions Read the explanation of Mk mode for Mk mode and the explanation of Mk mode for Mk II mode as required Remark Function in this section is applicable to the uPD750006 and PD750008 whose program counters consist of 13 bits each This is also applicable to the PD750004 whose program counter consists of 12 bits and the uPD75P0016 whose program counter consists of 14 bits however 11 4 4 Transfer Instructions C 2 MOV A n4 Function A n4 4 15 0 Transfers the 4 bit immediate data n4 to the A register 4 bit accumulator The string effect group A can be utilized When MOV A 14 and or MOV n8 instructions are located contiguously
109. BUSY signal is output until the next falling edge of the serial clock SCK appears after release of BUSY is directed Before setting WUP 1 be sure to confirm that pin SBO or SB1 is high after releasing BUSY 128 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 40 Format of Serial Operation Mode Register CSIM 3 4 Serial interface operation mode selection bit W Operation Bit order of SO pin 51 3 wire 5105 0 lt gt XA SO P02 serial Transfer start CMOS output I O mode with MSB 510 7 lt gt Transfer starting with LSB SBI mode 5107 lt gt XA SBO P02 input Transfer starting N ch open drain I O with MSB P02 input SB1 P03 N ch open drain 5105 0 lt gt XA SBO P02 input Transfer starting N ch open drain 1 0 with MSB P02 input SB1 P03 N ch open drain 1 0 Remark x Don t care Serial clock selection bit W Serial clock __ _ __ am SCK pin mode 3 wire serial mode SBI mode 2 wire serial mode 0 input clock externally applied to SCK pin Timer event counter output TOUTO Output fy 24 375 kHz at 6 00 MHz fy 26 93 8 kHz at 6 00 MHz 2 kHz at 4 19 MHz 65 47 kHz at 4 19 MHz fx 23 750 kHz at 6 00 MHz Ss kHz at 4 19 MHz Remarks 1 Each mode can be selected using CSIE CSIM3 and CSIM2 CSIE CSIM3 CSIM2 Operation mode Operation halt mode Three wire serial I O mode SBI mode T
110. Before this instruction can be executed MBE 0 or MBE 1 MBS 15 must be set Only 4 or 6 can be specified as 11 4 14 CPU Control Instructions C D HALT Function PCC 2 1 Sets the HALT mode This instruction is used to set bit 2 of the processor clock control register Caution The instruction immediately following a HALT instruction must be a NOP instruction C 2 stop Function PCC 3 1 Sets the STOP mode This instruction is used to set bit 3 of the processor clock control register Caution The instruction immediately following a STOP instruction must be a NOP instruction 7 Function Uses one machine cycle without performing an action 11 4 15 Special Instructions D SELRBn Function RBS n n WNj 9 0to3 Sets the 2 bit immediate data n in the register bank select register RBS D SELMBn Function MBS lt n n 0 0 1 15 Transfers the 4 bit immediate data n to the memory bank select register MBS Only 0 1 or 15 can be specified as n 295 uPD750008 USER S MANUAL taddr Function taddr T5 9 0 20H 7FH For the PD750008 Mk mode When a table defined by the TBR instruction is referenced PC12 9 taddr 4 9 taddr 1 When a table defined by the TCALL instruction is referenced SP 1 lt PC7 4 5 2 lt SP 3 lt MBE RBE 0 12 SP 4 lt PC41 g PC12 9 lt taddr 4 9 taddr 1 SP lt SP 4 When a table defi
111. C High current A signal is taken directly from f The signal lines of the main system the resonator clock and subsystem clock are parallel and adjacent to each other uPD750008 uPD750008 2 1 are wired parallel Remark When wiring the subsystem clock read X1 and 2 as 1 2 respectively In this case a resistor must be added to XT2 in series 91 PD750008 USER S MANUAL 4 Frequency divider The frequency divider divides the output fx of the main system clock oscillator to generate various clocks 5 Control functions of subsystem clock oscillator The subsystem clock oscillator of the PD750008 subseries has two control functions to decrease the supply current The function to select with the software whether to use the built in feedback resistor The function to suppress the supply current by reducing the drive current of the built in inverter when the operating supply voltage is high Vpp 2 7 V Each function can be used by switching bits O and 1 in the sub oscillator control register SOS See Figure 5 17 Figure 5 17 Subsystem Clock Oscillator Feedback resistor Inverter gt uPD750008 XT1 XT2 92 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 6 Sub oscillator control register SOS The SOS register specifies whether to use the built in feedback register and controls the d
112. CKE 1 period is too short The ACK signal is not ACKE lt 4 When ACKE is set or cleared during this period and ACKE 0 at the falling edge of SCK Figure 5 64 Operation of ACKD 1 2 a When ACK signal is output during the ninth SCK clock Transfer start request SIO X Transfer start SCK 6 7 8 9 D ACKD b When ACK signal is output after the ninth SCK clock Transfer start request SO _______________ __ gt Transfer start SCK 6 7 8 9 ACKD 163 PD750008 USER S MANUAL 164 Figure 5 64 Operation of ACKD 2 2 c Clear timing for case where start of transfer is directed during BUSY Transfer start request SIO SCK SBO 581 ACKD SCK SBO SB1 se LLL WKY gt When BSYE 1 at this point i When reset operation is executed during this period and BSYE 0 at the falling edge of SCK CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5 ueis 49JSU J OIS SI 2195 Jaye JO panels s 0 uononJisul 2 2195 Dejqeue s 10 c 85 10 085 UO 1ndino 21195 yey 0 3 lt I gt ___ ea 85 ogs jeuBbls 55 ui si od eu amp is 95 085 DuisseooJd 185 10 08S pe qesip si MOS uo 1ndino euDis MOT 21196 yey L
113. Connect this emulation probe to the IE 75000 R or IE 75001 R and the IE 75300 R EM IE control program This program enables the host machine to control the IE 75000 R or IE 75001 R through the RS 232 C and Centronics interface 5 005 2HD US5A13IE75X Ver 3 3010 5 25 inch 2HD wS5A10IE75X PC AT and See OS for 3 5 inch 2HC 157 131 75 compatibles IBM 5 25 inch 2HC uS7B101E75X Notes 1 Maintenance service only 2 To be ordered 3 These software products cannot use the task swap function which is available in MS DOS Ver 5 00 or later Hardware Part number Software PC 9800 series Ver 6 2Note 3 Remark Operation of the IE control program is guaranteed only on the above host machines and OSs 303 PD750008 USER S MANUAL OS for IBM PC The following IBM PC OSs are supported Ver 3 1 to Ver 6 3 J6 1 VNote to J6 3 VNote Ver 5 0 to Ver 6 22 5 0 VNote to J6 2 VNote IBM DOSTM J5 02 VNote Note Only English version is supported Caution These software products cannot use the task swap function which is available in MS DOS Ver 5 00 or later 304 APPENDIX B DEVELOPMENT TOOLS 00026 4 Z 2 oi 4 4 00292 3 eui p JOU OP 5 94 71 S9JON Ja quiasse 0091 9 goeroods
114. DEVICES TO CONTROL INTERRUPT FUNCTIONS Table 6 4 Identifying Interrupt Sharing Vector Table Address was added in Section 6 6 PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS The description for the screening of one time PROM was added Chapter 9 The description for the mask option was added Chapter 10 The operand rpa was changed to rpai in Chapter 11 Chapter 11 INSTRUCTION SET 1 was added in the table in item 1 Operand identifier and description in Section 11 2 INSTRUCTION SET AND OPERATION The title of Section 11 4 FUNCTIONS AND APPLICATIONS OF THE INSTRUCTIONS was changed to conform to that of Section 11 2 INSTRUCTION SET AND OPERATION Supported OS versions were upgraded Appendix B 321 PD750008 USER S MANUAL MEMO 322
115. ET command The RESET command changes the currently selected slave to a non selected slave When a RESET command is transmitted any slave can be placed in the non selected state Figure 5 77 Transfer Format of the RESET Command M S RESET ACK Command Remark M Output by the master S Output by the slave lt 5 gt CHGMST command The CHGMST command passes the master authority to the currently selected slave Figure 5 78 Transfer Format of the CHGMST Command M S S S Command Data Remark M Output by the master 5 Output by the slave When the slave receives a CHGMST command the slave returns one of the following data to the master after checking whether the slave can receive the master authority OFFH Master changeable e OOH Master not changeable The slave compares the contents of SIO before transfer with the contents of SIO after transfer If the contents of SIO disagree with each other an error occurs ACK is not returned in this case If the master receives OFFH the master returns ACK to the slave and starts to operate as slave The slave which transmitted OFFH starts to operate as the master when it receives ACK iv Error occurrence If a communication error occurs the operation described below is performed The slave reports the occurrence of an error by not returning ACK to the master If an error occurs during reception of data the slave sets the status bit for indicating error occurrence and cancels al
116. F jm prse me es fom ss mom Me We e es wee aw Dew sw fx fs sire fv 33e nw l3 lovee _ Increment decrement c e Q c Oo 9 cj gt c 247 uPD750008 USER In Struc tion o gt c gt monic Operation Skip condition 2 2 __ 4 H mem bit H mem3 9 bit 1 membt 2 2 lt 44 _ pmem L 7 2 1 3 201 1 0 0 H mem bit H mem3 9 bit 0 pmem L 245 Skip if pmemz a Ls bit L4 9 21 omem L 1 H mem bit Skip if H mems3_ 9 bit 1 fmem bit Skip if fmem bit 0 z H mem bit gt SKTCLR fmem bit Skip if fmem bit 1 and clear 4 fmem bit 1 omem L 2 6 Skip if pmemza Laa bit L4 o gt pmem QL 1 1 and clear H mem bit 2 2 5 Skip if H mems3 bit 1 1 H mem bit 1 and clear CY fmem bit 2 2 CY lt CYA fmem bit 4 CY pmem L 2 2 CY CYA 5 pmem 2 L3 bit L1 0 obit CY H mem bit 2 2 CY CYAY H mems3 9 bit CY fmem bit CY lt CYv fmem bit CY pmem L 2 2 CY lt pmemM7 9 L3 9 bit Ly 9 lt CYv CY fmem bit CY lt CY v fmem bit CY pmem L 2 2 CY lt CY v pmem 2 L3 2 bit L4 9
117. Figure 6 6 b shows the format of IM1 A bit manipulation instruction is used to set IM1 A RESET signal clears all bits to 0 and a rising edge is specified to be detected c As shown in Figure 6 4 c the INT4 circuit accepts an external interrupt at its rising and falling edges CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Figure 6 4 Configurations of the INTO INT1 and INT4 Circuits a Configuration of the INTO circuit INTO 3 R Edge detection es j D circuit set signal INTO P10 Noise eliminator 02 00 01 Detection edge IMO specification fx 64 Sampling clock selection Input buffer Internal bus b Configuration of the INT1 circuit INT1 P11 Edge detection circuit set signal Detection edge specification Input buffer V Internal bus c Configuration of the INT4 circuit INT4 INT4 P00 edis M 2 detection circuit set signal Input buffer Internal bus 191 uPD750008 USER S MANUAL Figure 6 5 I O Timing of a Noise Eliminator 15 15 tsMP gt lt gt lt 25 gt lt 1 Shorter than sampling cycle tsmp INTO Shaped output lt 2 gt 1 to2 times a INTO Shaped output b INTO Shaped output 3 Longer than 2 times INTO Shaped output L Remark tcy or 64 fx 192 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Figure 6 6 Form
118. H 3000H Branch address specified in BRCB Icaddr instruction Note be used only in the mode Remark In addition to the above the BR PCDE and BR instructions can cause a branch to an address with only the 8 low order bits of the PC changed 52 CHAPTER 4 INTERNAL CPU FUNCTIONS 4 4 DATA MEMORY RAM 512 WORDS x 4 BITS The data memory consists of a data area and peripheral hardware area as shown in Figure 4 7 The data memory consists of the following memory banks with each bank made of 256 words x 4 bits Memory banks 0 and 1 data area Memory bank 15 peripheral hardware area 4 4 4 Data Memory Configuration 1 Data area The data area consists of a static RAM and is used for storing program data and as stack memory for subroutine and interrupt execution Battery backup enables the memory to hold data for a long time even if the CPU is stopped in the standby mode The data area can be manipulated with memory manipulation instructions The static RAM is mapped to memory banks 0 and 1 with each made up of 256 x 4 bits Bank 0 is used as a data area but can also be used as a general register area OOOH to 01FH and stack areaNote 000H to 1FFH Whole locations in memory banks 0 1 2 and OOOH to 3FFH can be used as a stack area The static RAM has a configuration of four bits per address However the memory can be manipulated in 8 bit units using an 8 bit memory manipulati
119. IE 75000 RNete 1 The IE 75000 R is an in circuit emulator used to debug hardware and software when developing an application system using the 75X series and 75XL series Use this emulator together with optional emulation board IE 75300 R EM and emulation probe to develop application systems of the uPD750008 subseries For efficient debugging connect the emulator to the host machine and a PROM programmer The IE 75000 R contains emulation board IE 75000 R EM The board is connected to the IE 75000 R IE 75001 R The IE 75001 R is an in circuit emulator used to debug hardware and software when developing an application system using the 75X series and 75XL series Use this emulator together with optional emulation board IE 75300 R EM and emulation probe For efficient debugging connect the emulator to the host machine and a PROM programmer IE 75300 R EMNete 2 The IE 75300 R EM is an emulation board used to evaluate an application system using the uPD750008 subseries Use this board together with the IE 75000 R or IE 75001 R EP 75008GB R The EP 75008GB R is an emulation probe for the uPD75008GB and uPD750008GB Connect this emulation probe to the IE 75000 R or IE 75001 R and the IE 75300 R EM EV 9200G 44 A 44 pin conversion socket the EV 9200G 44 supplied with this probe facili tates the connection of the probe to the target system EP 75008CU R The EP 75008CU R is an emulation probe for the uPD75008CU and uPD750008CU
120. ITECTURE AND MEMORY MAP The 75XL series architecture of the uPD750008 has the following features Internal RAM of up to 4K words x 4 bits 12 bit address Peripheral hardware expansibility To provide these features the following are used 1 Data memory bank structure 2 General register bank structure 3 Memory mapped This chapter explains these topics 3 1 DATA MEMORY BANK STRUCTURE AND ADDRESSING MODES 3 1 1 Data Memory Bank Structure In the uPD750008 addresses OOOH to 1FFH in data memory space are assigned to static RAM 512 words x 4 bits and addresses F80H to are assigned to peripheral hardware such as 1 0 ports and timers To address a 12 bit location in this data memory space 4K x 4 bits the uPD750008 uses such a memory bank structure that the low order eight bits are specified with an instruction directly or indirectly and the high order four bits are used to specify a memory bank To specify a memory bank MB two hardware items are incorporated e Memory bank enable MBE e Memory bank select register MBS The MBS is a register used to select a memory bank and the register can be set to 0 1 or 15 The MBE is a flag used to determine whether the memory bank selected using the MBS is valid As shown in Figure 3 1 when the MBE is set to 0 a certain memory bank is always selected regardless of the setting of the MBS When the MBE is set to 1 memory bank selection depends on the
121. LHM C lt i Z29d ZH INDIO 9d EY M 5009 lt OZd vuM L4d SUM 195 2991 101 e lt dLld 9Y lt 4d 4UM lt i Bulsiy SHn24I2 01 0H ZLNI 94 42019 01 9 212 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Figure 6 11 Format of INT2 Edge Detection Mode Register IM2 Address Symbol 9 2 1 0 re o wa we we IM21 IM20 INT2 interrupt source Interrupt input pin Specifies rising edge of INT2 pin input INT2 1 KR4 KR7 4 Specifies falling edge of any of KRx pin KR2 KR7 6 Inputs KRO KAT 8 Cautions 1 When the edge detection mode register is modified test request flags may be set in some cases So disable test inputs before modifying the edge detection mode register Then clear the test request flags using a CLR1 instruction before enabling test inputs 2 Whenalow level signal is applied to any of the pins subjected to falling edge detection IRQ2 is not set when a falling edge is detected on another pin 213 uPD750008 USER S MANUAL MEMO 214 CHAPTER 7 STANDBY FUNCTION The uPD750008 provides a standby function to reduce the power consumption by the system The standby function is available in the two modes the STOP mode and HALT mode 1 2 Differences between these two modes are as fo
122. MHz 7 81 ms at 4 19 MHz However the uPD75P0016 dose not have a mask option and its wait time is fixed to 219 fy 225 PD750008 USER S MANUAL Table 8 1 Status of the Hardware after a Reset 1 2 Hardware Generation of a RESET signal in a standby mode Program counter PC uPD750004 4 low order bits at address 0000H in program memory are set in PC bits 11 to 8 and the data at address 0001H are set in PC bits 7 to O 5 low order bits at address 0000H in program memory are set in PC bits 12 to 8 and the data at address 0001H are set in PC bits 7 to O uPD75P0016 5 low order bits at address 0000H in program memory are set in PC bits 13 to 8 and the data at address 0001H are set in PC bits 7 to O uPD750006 uPD750008 PSW Carry flag CY Skip flags SKO to SK2 Interrupt status flags ISTO IST1 71 Bank enable flags MBE RBE Bit 6 at address OOOOH in and bit 7 is set in MBE program memory is set in RBE program memory is set in RBE Generation of a RESET signal during operation 4 low order bits at address OOOOH in program memory are set in PC bits 11 to 8 and the data at address 0001H are set in PC bits 7 to O 5 low order bits at address 0000H in program memory are set in PC bits 12 to 8 and the data at address 0001H are set in PC bits 7 to O 5 low order bits at address 0000H in program memory are set in PC bits 13 to 8 and the data at address 0001H are set in PC
123. NM 21 SARIS 5 5 sseJppyv 9 6 e1nBiJ 169 PD750008 USER S MANUAL _ EE m See uondeoei jeueg LLIN IV ER A O 19718991 BuisseooJd eoi ep lt gt y mmm YOS eul doe UOISSILUSUB EOS 19JSU 1 jenos 1X9U uomejedaad DI pon DuisseooJud 6uisseooud JelseJ N 991A9q ALIS 5 1ejsue1 99 6 170 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS ASDg 5004 jindino lindino eues uoneJedo ASNd 1e9 2 __ BuisseooJd ppop soo DOO J8JSUEJ Ays ij uoissiuisueJl EOS uonejedo 01 les 2 jenas 1X9U JO DuisseooJd GuisseooJd 8914p Je1se N VARIS 921A9q 5 5 ejeq 69
124. NUAL 1 2 3 4 5 6 7 8 Serial operation mode register 0 CSIM CSIM is an 8 bit register which specifies a serial interface operation mode serial clock wake up function and so forth See 1 in Section 5 6 3 for details Serial bus interface control register SBIC SBIC is an 8 bit register consisting of bits for controlling the serial bus and flags for indicating the states of input data from the serial bus SBIC is used mainly in the SBI mode See 2 in Section 5 6 3 for details Shift register SIO SIO is an 8 bit register which converts 8 bit serial data to parallel data and 8 bit parallel data to serial data SIO performs transfer shift in phase with the serial clock Transfers operations are controlled by writing data to SIO See 3 in Section 5 6 3 for details SO latch SO is a latch to hold the levels of pins SO and SBO or SI and SB1 which can be controlled directly by software In the SBI mode SO is set when the eighth clock of SCK has been output See 2 in Section 5 6 3 for details Serial clock selector The serial clock selector selects the serial clock to be used Serial clock counter The serial clock counter counts the serial clock to be output or input during transfer and checks whether 8 bit data has been transferred Slave address register SVA and address comparator e n the SBI mode SVA is used when the PD750008 is used as a slave device A slav
125. Nete a Branch call address by GETI Relative branch address specified in BR addr instruction 15 to 1 2 10 16 In addition to the above the BR PCDE and BR instructions can cause branch to address with only the 8 low order bits of the PC changed 51 D750008 USER S MANUAL Figure 4 6 Program Memory pPD75P0016 74 6 0 INTBT INT4 start address low order 8 bits Entry address 0004H INTO start address high order 6 bits specified in CALLF INTO start address low order 8 bits lfaddr instruc Branch 0006H INT1 start address high order 6 bits tion address INT1 start address low order 8 bits 182 0008H INTCSI start address high order 6 bits 2 INTCSI start address low order 8 bits tion 000AH INTTO start address high order 6 bits Branch address specified in INTTO start address low order 8 bits BR BR BCDE 000CH INTT1 start address high order 6 bits BR BCXA BRA laddr1Nete INTT1 start address low order 8 bits CALL adadr or CALLA laddr1Nete p ad Branch call Punt address by GETI instruction reference table GETI 007FH 0080H Relative branch address specified in O7FFH L BR addr 0800H instruction 15 to 1 2 to 16 OFFFH 1000H 3FFFH Branch address specified in BRCB Icaddr instruction Branch address specified in BRCB Icaddr instruction 2FFF
126. ORTn 0 8 Transfers the contents of the port specified by PORTn n 0 8 to the register Caution Before this instruction can be executed MBE 0 or MBE 1 MBS 15 must be set A number from 0 to 8 can be specified as n Depending on I O mode specification output latch data in the output mode or pin data in the input mode are transferred C 2 IN XA PORTn Function A lt PORTn X PORT Naso 4 6 Transfers the contents of the port specified by PORTn n 4 or 6 to the A register then transfers the contents of the next port to the X register Caution Only the number 4 or 6 can be specified as n Before this instruction can be executed MBE 0 or MBE 1 MBS 15 must be set Depending on I O mode specification output latch data in the output mode or pin data in the input mode are transferred 7 OUT PORTn A Function PORTn A 2 8 Transfers the contents of the A register to the output latch of the port specified by PORTn n 2 8 Caution Before this instruction can be executed MBE 0 or MBE 1 MBS 15 must be set A number from 2 to 8 can be specified as n C 2 OUT PORTn XA Function PORTn lt A lt X 4 6 Transfers the contents of the A register to the output latch of the port specified by PORTn n 4 6 then transfers the contents of the X register to the output latch of the next port 294 CHAPTER 11 INSTRUCTION SET Caution
127. Operating mode Operating mode Oscillation Clock Note The following two wait times can be selected by a mask option 217 fx 21 8 ms at 6 00 MHz 31 3 ms at 4 19 MHz 215 fy 5 46 ms at 6 00 MHz 7 81 ms at 4 19 MHz However the uPD75P0016 dose not have a mask option and its wait time is fixed to 215 fy Remark The dashed line indicates the case where the interrupt request that releases the standby mode is accepted When the STOP mode is released by the occurrence of an interrupt a wait time is determined by the basic interval timer mode register BTM See Table 7 2 A time required for stable oscillation varies with the type of resonator used and the supply voltage at the time of STOP mode release Accordingly a wait time is to be selected according to each application and BTM is to be set before the STOP mode is set 218 CHAPTER 7 STANDBY FUNCTION Table 7 2 Selection of a Wait Time with BTM BIM BTM2 BTM1 BTM 5 M indicates the value for fy indicates the value for fy 6 00 MHz 4 19 MHz ode 0 D Approx 220 fy Approx 175 ms Approx 220 fy Approx 250 ms P 1 1 Approx 217 fx Approx 21 8 ms Approx 217 fy Approx 31 3 ms Se Approx 215 fx Approx 5 46 ms Approx 215 fx 7 81 ms Other than above Not to be set Note This time does not include the time from the release of the STOP mode to the start of oscillation Caution The wait times used when
128. P63 is reset SKTCLR IRQTO IRQTO 1 BR NO CLR1 PORT6 3 YES 3 If both P30 and P41 are set to 1 P53 is reset MOV1 CY PORT3 0 CY lt P30 AND1 CY PORT4 1 CY P41 NOT1 CY CY lt CY MOV1 PORT5 3 CY P53 lt CY CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP b Specific address bit register indirect addressing pmem oL In this addressing mode the bits of peripheral hardware 1 0 ports are indirectly specified using register to allow continuous manipulations This addressing mode can be applied to data memory addresses FCOH to FFFH In this addressing mode the high order 10 bits of a 12 bit data memory address is directly specified in the operand and the low order two bits and bit address are indirectly specified using the L register Thus the use of the L register enables 16 bits four ports to be continuously manipulated This addressing mode again enables bit manipulation regardless of MBE and MBS setting Example Pulses are output on the bits in the order from port 4 to port 7 MOV L 0 LOOP SET1 PORT4 L Bits L4 9 of ports 4 to 7 lt 1 CLHR1 PORT4 L Bits L4 9 of ports 4 to 7 0 INCS L NOP BR LOOP 31 PD750008 USER S MANUAL 32 c Specific 1 bit direct addressing H mem bit This addressing mode enables any bit in the data memory space to be manipulated In this addressing mode the high order four bits of the data memory address in the memory bank specif
129. QW set signal fw 128 32 768 kHz From the 32 768 kHz ack Selector generator f P Hz 4 kHz 2 kHz i 5 E 32 768 kHz Clear signal Output buffer gt di P23 BUZ PORT2 3 Bit 2 of PMGB WM P23 output Port 2 input bw o ws ne ws wee wae wo Bit test instruction Internal bus The values in parentheses for fy 4 194304 MHz and fxr 32 768 kHz 5 4 2 Clock Mode Register The clock mode register WM is an 8 bit register which controls the clock timer Figure 5 27 shows the format of the clock mode register All bits except bit 3 of the clock mode register are controlled by an 8 bit manipulation instruction Bit 3 is for testing the XT1 pin input level The input level of the XT1 pin can be tested by bit test operation No data can be written to this register When the RESET signal is generated all bits except bit 3 of this register are cleared to 0 106 Example Time is set using the main system clock 4 19 MHz and buzzer output is enabled Remark CLR1 MBE MOV XA 84H MOV WM XA CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Sets WM Figure 5 27 Clock Mode Register Format Address 7 roo vo we for fw 32 768 kHz 0 Symbo BUZ output enable disable bit WM7 Disables BUZ output Enables BUZ output BUZ output frequency selection bit BUZ output frequency fw TE kH 33 4 096 kHz Deje
130. RE FUNCTIONS Figure 5 60 Operations of RELT CMDT RELD and CMDD Master Transfer start request 2 1 LI ooo Figure 5 61 Operations of RELT CMDT RELD and CMDD Slave Transfer start request Write to SIO h V When address match is found When address mismatch is found 161 PD750008 USER S MANUAL Figure 5 62 Operation of ACKT When ACKT is set after transfer completion SCK 6 7 8 9 ACK signal is output during the first clock SBO 581 D2 X D1 X Do cycle immediately after ACKT is set ACKT When set during this period Caution Do not set the ACKT until the transfer is completed Figure 5 63 Operation of ACKE 1 2 a When ACKE 1 at time of transfer completion SCK 2 l 7 8 9 NX Jor X The ACK signal is output during the ninth clock cycle AL When ACKE 1 at this point b When ACKE is set after transfer completion SCK 7 lef lof LJ LILI SBO SB1 D2 X Di X Do ACK The ACK signal is output during the first clock cycle immediately after ACKE is set ACKE gt When is set during this period 1 at the falling edge of the next SCK c When ACKE 0 at time of transfer completion SCK 1 2 l 7 8 9 The ACK signal is not A When ACKE 0 at this point 162 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 63 Operation of ACKE 2 2 d When A
131. SET Vpp Note 3 Notes 1 The program counter for the PD750004 consists of 12 bits 13 bits for the uPD750006 and uPD750008 and 14 bits for the uPD75P0016 2 The ROM capacity depends on the product 3 wPD75P0016 PD750008 USER S MANUAL 1 5 CONFIGURATION TOP VIEW 1 42 pin plastic shrink DIP 600 mil uPD750004CU XXX uPD750006CU XXX uPD750008CU XXX uPD75P0016CU SI SB1 P03 SO SBO0 P02 INT4 POO TIO P13 INT2 P12 INT1 P11 INTO P10 Vpp Note 1 2 3 4 5 6 7 8 P53 P60 KRO P61 KR1 P62 KR2 P63 KR3 P70 KR4 P71 KR5 P72 KR6 P73 KR7 P20 PTOO P21 PTO1 P22 PCL P23 BUZ Note Connect IC Vpp to Vpp keeping the wiring as short as possible Remark uPD75P0016 2 44 pin plastic QFP 10 x 10 mm uPD750004GB XXX 3BS MTX uPD750006GB XXX 3BS MTX uPD750008GB XXX 3BS MTX UPD75P0016GB 3BS MTX O P73 KR7 A P72 KR6 P71 KR5 P70 KR4 P63 KR3 P62 KR2 P61 KR1 P60 KRO P53 P52 P51 P50 1 2 3 4 5 6 7 8 9 v e NO NC O P20 PTOO O P21 PTO1 O P22 PCL O P23 BUZ O 2 P40 Vss IC Vep Note P10 INTO P11 INT XT1 XT2 O RESET CHAPTER 1 GENERAL O P12 INT2 O NC P13 TIO POO INT4 01 5 P02 SO SBO P03 SI SB1 CROP eer ee Ome U 1 X2 Note Connect IC Vpp to Vpp keeping
132. SP lt SP 2 MBS SP 1 RBS SP SP lt SP 2 IME IPS 3 lt 1 SS Eee gt mees _ l bem e mu _ swmrwaexr s me esonero eoe Note 1 The shaded portion is supported II mode only The other portions supported in Mk mode only 2 MBE 0 or MBE 1 and MBS 15 must be set when an IN OUT instruction is executed O O 4 B 42 gt OQ 2 no n5 Interrupt control i I O CPU control NO 255 uPD750008 USER S MANUAL In Address struc Mne Operand Machine Operation ing Skip condition tion monic cycle area GETINote taddr e uPD750004 When the TBR instruction is used PC11 0 lt taddr 3_9 taddr 1 When the TCALL instruction is used SP 4 SP 1 SP 2 lt 11 SP 3 lt MBE RBE 0 0 PC144 9 lt taddr 3 9 taddr 1 When an instruction other than Depends on the the TBR or TCALL instruction is referenced used instruction Execution of taddr taddr 1 instruction e 750006 pPD750008 When the TBR instruction is used 12 0 lt taddr 4 taddr 1 When the TCALL instruction is used SP 4 SP 1 SP 2 lt 11 5 3 lt MBE RBE 0 PC42 PC12 9 taddr 4 taddr 1 SP lt SP 4 When an instruction other than Depends on the the TBR or TCALL instruc
133. SP 4 lt 11 0 5 5 lt 0 0 0 0 11 0 addr SP lt 5 6 uPD750006 uPD750008 SP 2 lt x x MBE RBE SP 6 SP 3 SP 4 lt SP 5 0 0 0 PC 19 9 lt addr SP lt SP 6 pPD75P0016 SP 2 x x MBE RBE SP 6 SP 3 SP 4 lt 11 0 SP 5 lt 0 0 13 12 PC 43 0 addr SP lt SP 6 e uPD750004 5 3 lt MBE RBE 0 0 5 4 5 1 6 2 lt PC44 0 PC11 0 0 faddr SP lt SP 4 pPD750006 uPD750008 SP 3 lt MBE RBE 0 PC42 SP 4 SP 1 SP 2 lt PC42 9 lt 00 faddr SP lt SP 4 e pPD75P0016 SP 3 lt MBE RBE PC45 12 5 4 1 5 2 lt PC 44 9 0 lt 000 faddr SP lt SP 4 Note The shaded portion is supported in II mode only The other portions are supported in Mk mode only 252 In struc Mne Operand RETNote 1 3 3 O c O O x 9 c gt O gt o cycle CHAPTER 11 INSTRUCTION SET Skip condition PD750004 SP 2 x x MBE RBE SP 6 SP 3 SP 4 lt PC11 0 SP 5 lt 0 0 0 0 PC41 9 lt O faddr SP lt SP 6 uPD750006 PD750008 SP 2 x x MBE RBE SP 6 SP 3 SP 4 lt PC11 0 SP 5 lt 0 0 0 12 PC42 9 00 faddr SP lt SP 6 e uPD75P0016 SP 2 lt x x MBE RBE SP 6 SP 3 SP 4 lt PC44 0 SP 5 lt 0 0
134. TABLES 185 6 3 VARIOUS DEVICES TO CONTROL INTERRUPT FUNCTIONS 187 64 INTERRUPT SEQUENCE Beds aen tua dame 195 65 MULTIPLE INTERRUPT PROCESSING 196 6 6 PROCESSING OF INTERRUPTS SHARING VECTOR ADDRESS 198 6 7 MACHINE CYCLES FOR STARTING INTERRUPT PROCESSING 200 6 8 EFFECTIVE USE OF INTERRUPTS e euius 202 69 INTERRUPT APPLICATION S mne tuis 202 610 TEST FUNG TION t N 210 GIOT PEST SOURCES baud dde 210 6 10 2 Hardware to Control Test Functions 210 CHAPTER 7 STANDBY FUNCTION iiio aue E uec he oou eects a a cae 215 7 1 SETTING OF STANDBY MODES AND OPERATION STATUS 216 7 2 RELEASE OF THE STANDB Y MODES a a at edes 217 7 3 OPERATION AFTER A STANDBY MODE IS RELEASED 219 54 SELECTION OF Ai MASK OPTION attt Ed tti tx Eta 220 7 5 APPLICATIONS OF THE STANDBY MODES ies 220 CHAPTER S HESET FUNGTIONR 225 CHAPTER 9 WRITING AND VERIFYING PROGRAM MEMORY PROM 229 91 OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY 1i
135. Time When the STOP Mode Is Released 219 onfig ratlon ol Reser FUrGllOFriS s oor 225 Reset Operation by Generation of RESET Signal 225 Drawings of the EV 9200G 44 306 Recommended Pattern on Boards for the EV 9200G 44 Reference 307 Table No 1 1 2 1 2 2 2 3 3 1 3 2 3 3 3 4 4 1 4 2 4 3 4 4 4 5 4 6 5 1 5 2 5 3 5 4 5 5 5 6 5 5 8 5 9 5 10 6 1 6 2 6 3 6 4 6 5 6 6 LIST OF TABLES 1 2 Title Page oL 1 Digtal m TU NUT 9 11 Connection or Unused PIS 20 Addressipg WIG GSS d ea iesu dude 25 Register Bank to Be Selected with RBE and 34 Recommended Use of Register Banks with Normal Routines and AST PUNO t ROUINO PRETIO 34 Addressing Modes Applicable to Peripheral Hardware 39 Differences between Mk Mode and Mk 45 Stack Area to Be Selected by the 5 5 58 PSW Flags Saved Restored in Stack Operation
136. XANote uPD750004 Wl PC11 0 lt addr uPD750006 PD750008 PC42 9 addr uPD75P0016 t CALLANote 2 e pPD750004 11 SP 2 x x MBE RBE SP 6 SP 3 SP 4 lt PC44 9 5 5 lt 0 0 0 0 PC11 0 lt addr SP lt SP 6 e uPD750006 uPD750008 SP 2 x x MBE RBE SP 6 SP 3 SP 4 lt 11 0 5 5 0 0 0 PC4 12 0 addr SP lt 5 6 uPD75P0016 SP 2 x x MBE RBE SP 6 SP 3 SP 4 lt PC11 0 O O O O 42 c 2 O gt o SP 5 lt 0 0 PC45 PC42 PC43 9 lt addr1 SP lt SP 6 Note 1 The shaded portion is supported in Mk mode only 2 shaded portion is supported in Mk mode only The other portions are supported in Mk mode only 251 uPD750008 USER S MANUAL In struc Mne Operand tion monic 3 3 CALLFNote faddr 2 2 Subroutine stack control Address Machine Operation ing cycle area Skip condition e uPD750004 5 3 lt MBE RBE 0 0 5 4 5 1 6 2 lt PC44 0 PC11 0 lt addr SP lt SP 4 uPD750006 uPD750008 SP 3 lt MBE RBE 0 5 4 5 1 6 2 lt PC44 0 2 0 lt addr SP lt 4 e pPD75P0016 5 3 lt MBE RBE PC45 12 5 4 1 5 2 lt 11 0 PC45 9 lt addr1 SP lt SP 4 750004 SP 2 lt x x MBE RBE SP 6 SP 3
137. a is not lost Transfer is started when the busy state is released and input to SBO or SB1 goes high When eight bits have been transferred serial transfer automatically terminates setting the interrupt request flag IRQCSI Example When RAM data specified by the HL register is transferred to SIO from which data is loaded into the accumulator at the same time and serial transfer is started MOV XA QHL Extracts transmit data from RAM SEL MB15 CLR1 MBE XA SIO Exchanges transmit data with receive data and startstransfer 11 Notes on the SBI mode a Whether a slave is selected is determined by detecting a match for a slave address received after bus release in the state of RELD 1 An address match is detected usually using an address match interrupt IRQCSI generated when WUP is 1 So detect selection nonselection state by slave address when WUP is set to 1 b When determining whether a slave is selected without using an interrupt when WUP 0 do not use the address match detection method Instead use transfer of commands set in advance in a program c When WUP is setto 1 during BUSY signal output BUSY is not released In the SBI mode after release of BUSY is directed the BUSY signal is output until the next falling edge of the serial clock SCK appears Before setting WUP to 1 be sure to confirm that the SBO or SB1 pin is high after releasing BUSY 173 PD750008 USER S MANUAL 12 SBI mode
138. able flag is set by the El instruction At this stage INTO and INTTO are enabled 4 An interrupt enable flag is cleared by the DI IExxx instruction to disable INTO 5 The DI instruction disables all interrupts 203 uPD750008 USER S MANUAL 2 Example of using INTBT INTO falling edge active and INTTO without multiple interrupt processing c1 c2 c3 lt 4 gt lt 5 gt lt Main program gt lt 1 gt Reset 1 1 0 lt 2 gt A 1 MOV IMO A CLR1 IRQO lt 3 gt El IEBT Status 0 lt INTO service program gt Be RBE 0 EI lt 4 gt INTO Status 1 5b RETI A RESET signal disables all interrupts setting status O INTO is set to be falling edge active Interrupts are enabled by the El and EI IExxx instructions On the falling edge of INTO the INTO interrupt service program is started status is set to 1 and all interrupts are disabled Control is returned from the interrupts by the RETI instruction status 0 is set again and interrupts are enabled Remark lf all the interrupts are used as having the lower priority as shown in this example saving or 204 restoring the register bank is not necessary if RBE 1 and RBS 2 for the main program and register banks 2 and 3 are used and RBE 0 for the interrupt service program and register banks 0 and 1 are used CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 3 Nesting of interrupt
139. an be specified using bit 2 of serial operation mode register CSIM Figure 5 46 Transfer Bit Switching Circuit Internal bus _ eS tft MSB first Read write gate E E E SI Shift resister SIO gt SO latch SO SCK The first bit is switched by changing the order of data bits written to shift register SIO The shift operation order of SIO is always the same Accordingly the first bit must be switched between the MSB and LSB before writing data to the shift register 141 PD750008 USER S MANUAL 6 Transfer start Serial transfer is started by writing transfer data into shift register SIO provided that the following two conditions are satisfied The serial interface operation enable disable specification bit CSIE is set to 1 The internal serial clock 15 not operating after 8 bit serial transfer or SCK is high Caution Setting CSIE after writing data to the shift register does not start transfer When eight bits have been transferred serial transfer automatically terminates setting the interrupt request flag IRQCSI Example To transfer the RAM data specified with the HL register to SIO load the SIO data to the accumulator and start serial transfer MOV XA HL Fetch transmit data from RAM SEL MB15 CLR1 MBE XCH XA SIO Exchange transmit data and receive data and start transfer 7 Application of the three
140. and number system conversion instructions for increased program efficiency Table reference instructions suitable for successive references 1 byte relative branch instructions NEC standard mnemonics designed for clarity and readability 1 2 3 4 5 6 7 8 See Section 3 2 for the addressing modes applicable to data memory manipulation and register banks used for instruction execution 11 1 UNIQUE INSTRUCTIONS This section outlines the unique instructions among the PD750008 instruction set 11 1 1 Instruction The GETI instruction converts any of the following instructions to a 1 byte instruction a Subroutine call instruction for the entire space b Branch instruction for the entire space c Arbitrary 2 byte instruction operating with two machine cycles Except the BRCB and CALLF instructions d A combination of two 1 byte instructions The GETI instruction references the table located at addresses 0020H to 007FH in program memory and executes referenced 2 byte data as an instruction of a b c or d above This means that 48 instructions consisting of a to d can be converted to 1 byte instructions Thus the GETI instruction can be used to convert frequently used instructions of a to d to 1 byte instructions to reduce the number of program bytes significantly 237 uPD750008 USER S MANUAL 11 1 2 Bit Manipulation Instructions With the uPD750008 a variety of instructions are availab
141. anipulations such as Boolean operations and bit transfer for each bit in the data memory space The 1 bit direct addressing mode can be applied only to the set reset and test instructions On the other hand the bit manipulation addressing enables a wide variety of bit manipulations such as Boolean operations using the AND1 OR1 and 1 instructions bit transfers using the MOV1 instruction and test and reset operations using the SKTCLR instruction There are three types of bit manipulation addressing The user can choose from these options according to the data memory address used 29 PD750008 USER S MANUAL 30 a Specific address bit direct addressing fmem bit In this addressing mode peripheral equipment that frequently performs bit manipulations involving for example I O ports and interrupt flags can be processed at all times regardless of memory bank setting Accordingly the data memory addresses that allow this addressing mode to be used are FFOH to FFFH where I O ports are mapped and FBOH to FBFH where interrupt related hardware is mapped Hardware mapped to these data memory areas can freely perform bit manipulations in the direct addressing mode at any time regardless of MBS and MBE setting Examples 1 Value input to PO2 is inverted and the result is output on P33 MOV1 2 NOT1 CY MOV1 PORT3 3 CY 2 Thetimer 0 interrupt request flag IRQTO is tested The request flag if set is cleared and
142. at of Edge Detection Mode Registers a INTO edge detection mode register IMO Address Symbol 3 2 1 0 FB4H IMO IMO1 Wo Detection edge specification 0 0 Spedtiesnsingede 0 jSmofestingedge 00002 9 Specifies both rising and faling edges Ignored No interrupt request flag is set IM02 Noise eliminator selection bit Sampling Standby mode Selects noise eliminator Enabled Cannot be released Does not select a noise eliminator Disabled Can be released IMO3 Sampling clock E 0 67 us 1 33 us 2 67 us and 10 7 us at 6 00 MHz X 1077 us at 6 00 MHz b INT1 edge detection mode register IM1 Address Symbol 3 2 1 0 IM10 Detection edge specification Specifies rising edge Specifies falling edge Caution Changing the edge detection mode register may set an interrupt request flag So disable the interrupts before changing the edge detection mode register Then clear the interrupt request flag with CLR1 instruction and enable the interrupts When 1 64 is selected as a sampling clock pulse in changing IMO wait for 16 machine cycles after changing the mode register and clear the interrupt request flag 193 uPD750008 USER S MANUAL 4 Interrupt status flags The interrupt status flags ISTO and IST1 which are contained in the PSW indicate the status of processing currently executed by the CPU By usi
143. ata in the next page is referenced instead of table data in the page containing that instruction Program memory 270 CHAPTER 11 INSTRUCTION SET For example if MOVT XA PCDE 15 located at a as shown above the table data in page 3 specified by the contents of the DE register pair is transferred to the XA register pair instead of that in page 2 Example The 16 byte data at addresses xxFOH xxFFH in program memory is transferred to addresses 30H 4FH in data memory SUB SEL MBO MOV HL 30H HL lt 30H MOV DE 0FOH DE lt LOOP MOVT XA PCDE XA lt table data MOV HL lt INCS HL HL lt HL 2 INCS HL INCS E 1 LOOP RET ORG xxFOH DB xxH xxH Table data C 2 MOVT XA PCXA Function For the uPD750006 and PD750008 XA ROM 12 2 Transfers the low order four bits of the table data in program memory to the A register and the high order four bits to the X register The table data is addressed by the program counter PC with its low order eight bits PCz 9 exchanged with the contents of the XA register pair The table address is determined by the contents of the program counter present when this instruction is executed The table area must have necessary data loaded by an assembler pseudo instruction DB instruction The program counter is not affected by the execution of this instruction Caution As with MOVT XA PCDE when the inst
144. ate bits 0 and 1 of serial operation mode register CSIM The serial clock can be selected out of the following four clocks Table 5 8 Serial Clock Selection and Application In the Two Wire Serial I O Mode Mode register Serial clock Timing for shift register R W and SRST CSIM CSIM Masking of Application External Automatically lt 1 gt In the operation halt mode Slave CPU SCK masked when CSIE 0 8 bit data lt 2 gt When the serial clock is TOUT transfer is masked after 8 bit transfer Arbitrary speed flip flop completed 3 When SCK is high serial transfer serial transfer 4 Signals Figure 5 49 shows operations of RELT and CMDT Figure 5 49 Operations of RELT and CMDT SO latch RELT D CMDT p 5 Transfer start Serial transfer starts by writing transfer data into shift register SIO provided that the following two conditions are satisfied The serial interface operation enable disable specification bit CSIE is set to 1 The internal serial clock is not operating after 8 bit serial transfer or SCK is high Cautions 1 Setting CSIE to 1 after writing data to the shift register does not start transfer 2 When data is received the N ch transistor must be turned off so FFH must be written to SIO beforehand When eight bits have been transferred serial transfer automatically terminates setting the interrupt request flag IRQCSI 148 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 6 Error det
145. ave address register 134 Stack bank select register 46 58 Stack pointer 58 Sub oscillator control register 93 System clock control register 88 T Timer counter 1 interrupt enable flag 187 Timer counter 1 interrupt request flag 187 Timer counter 1 mode register 111 Timer counter 1 modulo register 110 Timer counter 1 output enable flag 114 Timer counter count 1 register 110 Timer event counter 0 count register 109 Timer event counter O interrupt enable flag 187 Timer event counter O interrupt request flag 187 Timer event counter 0 mode register 111 Timer event counter 0 modulo register 109 Timer event counter O output enable flag 114 318 APPENDIX E HARDWARE INDEX E 2 HARDWARE INDEX ALPHABETICAL ORDER WITH RESPECT TO THE HARDWARE SYMBOL A ACKD 132 ACKE 132 ACKT 132 B BS 65 5 0 5 181 BSYE 132 BT 99 BTM 99 C CLOM 97 CMDD 132 CMDT 133 COI 128 CSIE 128 CSIM 127 CY 62 I IEO 187 IE1 187 IE2 210 IE4 187 IEBT 187 IECSI 187 IETO 187 1 187 IEW 210 IMO 193 IM2 213 IME 189 IRQO 187 IRQ1 187 IRQ2 210 IRQA 187 IRQBT 187 IRQCSI 187 IRQTO 187 IRQT1 187 IRQW 210 ISTO 63 194 IST1 63 194 K KRO KR7 211 M MBE 21 64 MBS 21 65
146. by the stack pointer SP then increments the contents of SP This instruction is used when control is returned from an interrupt service routine Remark Function in this section is applicable to the uPD750008 whose program counter consists of 13 bits addr OOOOH to 1FFFH However this is also applicable to the uPD750004 whose program counter consists of 12 bits addr OOOOH to OFFFH the PD750006 whose program counter consists of 13 bits addr OOOOH to 17FFH and the uPD75P0016 whose program counter consists of 14 bits addr OOOOH to 3FFFH C 2 PUSH rp Function SP 1 lt SP 2 lt SP lt SP 2 Saves the contents of register pair rp XA HL DE BC to the data memory location stack addressed by the stack pointer SP then decrements SP The high order part of a register pair roy X H D B is saved to the stack location addressed by SP 1 and the low order part L E C is saved to the stack location addressed by SP 2 292 CHAPTER 11 INSTRUCTION SET C 2 PUSH BS Function SP 1 lt MBS SP 2 lt RBS SP lt SP 2 Saves the contents of the memory bank select register MBS and the register bank select register RBS to the data memory location stack addressed by the stack pointer SP then decrements SP E POP rp Function rp lt SP lt SP 1 SP lt SP 2 Restores register pair ro XA HL DE BC with the data at the data memory
147. can be set to select the subsystem clock for very low speed low current operation 122 us at 32 768 kHz The value in the PCC does not affect the CPU clock When the subsystem clock is selected main system clock generation can be stopped with the SCC In addition the HALT mode can be used but the STOP mode cannot be used Subsystem clock generation cannot be stopped The clock to be supplied to peripheral hardware is produced by frequency dividing the main system clock signal The subsystem clock can directly be supplied only to the clock timer This enables the clock function and the buzzer output function to continue operating even in the standby state When the subsystem clock 15 selected the clock timer can continue to operate normally The serial interface timer event counter and timer counter can continue to operate when the external clock is selected However other hardware cannot be used when the main system clock is stopped because they operate with the main system clock Notes 1 At fy 4 19 MHz 15 3 us 2 At fy 4 19 MHz 0 95 us 1 91 us 3 81 us and 15 3 us 85 PD750008 USER S MANUAL 1 Processor clock control register PCC 86 The PCC is a 4 bit register for selecting a CPU clock with the low order two bits and for controlling the CPU operation mode with the high order two bits see Figure 5 12 When bit 3 or bit 2 is set to 1 the standby mode 15 set When the standby mode 15 released by the standby relea
148. ck frequency 1 machine cycle CPU clock frequency 1 machine cycle 0 0 93 7 KHz fx 64 93 7 kHz 10 7 us 4 8 192 kHz 122 us olif fx 16 375 kHz 2 67 us fx 8 750 kHz 1 33 us fx 4 1 5 MHz 0 67 us Operation with f x 4 19 MHz SCC3 SCCO 00 SCC3 SCCO 01 or 11 is actual frequency at fx 4 19 MHz is actual frequency at 32 768 kHz tom viii sere _ Remarks 1 fx Output frequency from the main system clock oscillator 2 fxt Output frequency from the subsystem clock oscillator CPU operation mode control bits Normal operation mode IE HALT mode STOP mode Not to be set 87 PD750008 USER S MANUAL 2 System clock control register SCC 88 The SCC is a 4 bit register for selecting CPU clock with the least significant bit and for controlling the termination of main system clock generation with the most significant bit see Figure 5 13 Bits 0 and 3 of the SCC are located at the same data memory address but both bits cannot be changed at the same time Accordingly bits 0 and 3 of the SCC are set using bit manipulation instructions Bits 0 and 3 of the SCC can be manipulated regardless of MBE setting Main system clock generation can be terminated by setting bit 3 of the SCC only when the subsystem clock is used for operation The STOP instruction must
149. ck output Figure 5 21 Format of the Clock Output Mode Register Address 3 2 1 0 Symbol FDOH CLOMS CLOM1 CLOMO CLOM Clock output frequency selection bit fx 6 00 MHz EXE output 1 5 MHz 750 kHz 375 kHz 93 8 kHz fx 2 output 750 kHz cary fx 2 output 375 kHz 5 28 output 93 8 kHz fx 4 19 MHz output 1 05 MHz 524 kHz 262 kHz 65 5 kHz fx 2 output 524 kHz fx 2 output 262 kHz FALS fx 2 output 65 5 kHz Note is the CPU clock selected by Clock output enable disable bit pod Output disable Output enable Caution Be sure to write a O in bit 2 of the CLOM 97 PD750008 USER S MANUAL 4 Application to remote control output 98 The clock output function of the uPD750008 is applicable to remote control output The frequency of the carrier for remote control output is selected by the clock frequency select bit of the clock output mode register Pulse output is enabled or disabled by controlling the clock output enable disable bit by software The clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling clock output Figure 5 22 Application to Remote Control Output Bit 3 of CLOM at GST OJ GN E r 15 1 1 PCL pin output CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5 3 BASIC INTERVAL TIMER WATCHDOG TIMER The uPD750008 contains 8 bit basic inte
150. contents of SIO disagree with each other the master interrupts data transfer by transmitting a STOP command Figure 5 74 Transfer Format of the STOP Command M S M S Data Data check error occurs Data transfer interruption Remark M Output by the master S Output by the slave When the slave receives a STOP command the slave invalidates the most recently received one byte 176 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS lt 3 gt STATUS command The STATUS command reads the status of the current slave Figure 5 75 Transfer Format of the STATUS Command M S 5 5 Data Command Remark M Output by the master S Output by the slave The slave returns the status in the format shown in Figure 5 78 Figure 5 76 Status Format of the STATUS Command MSB LSB Status Aa Bit indicating whether there is data ready for transmission 5 0 No transmit data 1 Transmit data of one byte or more Bit indicating whether the device is ready for data reception 0 No receive data storage area 1 Receive data storage area not smaller than one byte is present Bit indicating whether an error occurred 0 No error 1 Error occurred during previous transfer Bit indicating whether master can be changed or not 0 Master cannot be changed 1 Master can be changed When the master receives a status it returns ACK to the current slave 177 PD750008 USER S MANUAL lt 4 gt RES
151. controls the timer event counter Its format is shown in Figures 5 30 and 5 31 The timer event counter mode register is set by an 8 bit memory manipulation instruction Bit 3 is a start bit and can be operated bit wise It is automatically reset to 0 when the timer operation starts All the bits of the timer event counter mode register are cleared to 0 by a RESET signal generation Examples 1 Start the timer in the interval timer mode of CP 5 86 kHz during 6 00 MHz operation SEL MB15 or CLR1 MBE MOV XA 01001100B MOV TMn XA TMn lt ACH 2 Restart the timer according to the setting of the timer event counter mode register SEL MB15 or CLR1 MBE SET1 TMn 3 TMn bit3 lt 1 111 PD750008 USER S MANUAL Figure 5 30 Timer Event Counter Mode Register Channel 0 Format Address Symbol FADH II Toa Ez Two Count pulse CP selection bit E fx z 6 00 MHz TM06 05 04 Count pulse TIO rising edge TIO falling edge 0 0 fx 2 5 86 kHz 0 1 fx 29 23 4 kHz 1 0 4 26 93 8 kHz 1 1 fx 24 375 kHz Other than above Not to be set When fx 4 19 MHz 06 05 TMO4 Count pulse CP 0 0 0 TIO rising edge 0 0 1 TIO falling edge 1 0 0 fx 2 4 09 kHz 1 0 1 fx 2 16 4 kHz 1 1 0 fx 29 65 5 kHz fx 2 262 kHz Other than above Not to be set Timer start indication bit TMOS3 W
152. d The acknowledge signal ACK is detected lt 2 gt The RESET signal is generated in phase with the rising edge of SCK Acknowledge enable bit R W ACKE 0 Disables automatic output of the acknowledge signal ACK Output by ACKT is possible 1 When set before transfer ACK is output in phase with the 9th clock of SCK When set after transfer ACK is output in phase with SCK immediately following the set instruction execution Acknowledge trigger bit W When set after transfer ACK is output in phase with the next SCK After ACK signal output this bit is automatically cleared to O Cautions 1 Never set ACKT before or during serial transfer 2 ACKT cannot be cleared by software 3 Before setting ACKT set ACKE 0 Command detection flag R Condition for being cleared CMDD 0 Condition for being set CMDD 1 The transfer start instruction is executed The command signal CMD is detected The bus release signal REL The RESET signal is generated CSIE 0 Figure 5 40 132 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 41 Format of Serial Bus Interface Control Register SBIC 3 3 Bus release detection flag R Condition for being cleared RELD 0 Condition for being set RELD 1 The transfer start instruction is executed The bus release signal REL is detected The RESET signal is generated CSIE 0 Figure 5 40 SVA does not match SIO when an address is received Co
153. d I O which maps peripheral hardware such as timers and I O ports to addresses F80H to FFFH in data memory space as shown in Figure 3 2 This means that there is no particular instruction to control peripheral hardware but all peripheral hardware is controlled using memory manipulation instructions Some mnemonics for hardware control are available to make programs readable To manipulate peripheral hardware the addressing modes listed in Table 3 4 can be used Table 3 4 Addressing Modes Applicable to Peripheral Hardware Operation Applicable addressing mode Applicable hardware Direct addressing mode specifying mem bit with All hardware manipulation MBE 0 MBE 1 MBS 15 allowing bit manipulation Direct addressing mode specifying fmem bit regardless of IST1 ISTO MBE RBE MBE and MBS setting IExxx IRQxxx PORTn x Indirect addressing mode specifying pmem L regardless of BSBn x MBE and MBS setting PORTn x Direct addressing mode specifying mem with All hardware allowing 4 bit manipulation MBE 0 or MBE 1 MBS 15 manipulation Register indirect addressing mode specifying HL with MBE 1 MBS 15 Direct addressing mode specifying mem even address with All hardware allowing 8 bit manipulation MBE 0 or MBE 1 MBS 15 manipulation Register indirect addressing mode specifying HL with the L register containing an even number with MBE 1 and MBS 15 Figure 3 7 summarizes the I O map of the uPD750
154. d in Output latch data is incremented by 1 INCS the output latch SET1 The output latch data of a specified bit is The output pin state is modified according CLR1 rewritten but the output latch data of the to the instruction MOV 1 other bits is undefined SKTCLR 1 Represents an addressing mode PORTn bit or PORTnN L 80 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5 1 5 Specification of Bilt in Pull Up Resistors A pull up resistor can be contained at each port pin of the uPD750008 except for POO Whether to use the pull up resistor can be specified by software for some pins or a mask option for the other pins Table 5 4 shows how a built in pull up resistor is specified for each port pin The built in pull up resistor is connected by software in the format shown in Figure 5 8 Table 5 4 Specification of Built in Pull Up Resistors Port pin name Pull up resistor incorporation specification method Bit of POGA Bit of POGB Port 0 P01 P03 Note Connection specification by software in 3 bit units opto Port 1 P10 P13 Connection specification by software in 4 bit units Bit 1 Port 4 P40 P43 Incorporation specification by mask option in 1 bit Port 5 P50 P53 Port 8 P80 P81 Connection specification by software in 2 bit units Bto Note The POO pin cannot specify connection of a built in pull up resistor Remark The port pins of the uPD75P0016 are not connected to a
155. ddress comparator R Serial interface operation enable disable specification bit W Remarks 1 R Read only 2 W Write only 127 PD750008 USER S MANUAL Figure 5 40 Format of Serial Operation Mode Register CSIM 2 4 Serial interface operation enable disable specification bit W Shift register Serial clock IRQCSI SO SBO and operation counter flag SI SB1 pins a operation Cleared Held Used only for port 0 Shift nem Count operation Can be set Used in each mode as well nem as for port O Signal from address comparator R CO Note Condition for being cleared COI 0 Condition for being set COI 1 When the data in the slave address When the data in the slave address register register SVA does not match the data SVA matches the data in the shift in the shift register register Note can be read only before serial transfer is started or after serial transfer is completed An undefined value may result during transfer data written by an 8 bit manipulation instruction is ignored Wake up function specification bit W WUP Em Sets IRQCSI each time serial transfer is completed in each mode Used in the SBI mode only to set IRQCSI only when an address received after bus release matches the data in the slave address register wake up state SBO or SB1 goes to high impedance state Caution When WUP z 1 is set during BUSY signal output BUSY is not released In the SBI mode the
156. e HL register pair functions mainly as a data pointer and the DE and DL register pairs function as an auxiliary data pointer Examples 1 INCS HL HL lt HL 1 skip at HL OOH ADDS XA BC XA BC skip at carry SUBC DE XA DE lt DE XA MOV XA XA XA MOVT XA PCDE XA lt PC42 g DE ROM reference table SKE XA BC Skip if BC 2 he value of the count register TO for timer event counter 0 is tested until it becomes greater than the value of the BC register pair CLR1 MBE NO MOV XA T0 Read count register SUBS XA BC BC BR YES YES BR NO CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3 5 General Register Configuration 4 bit Processing 02H Register bank 0 RBS 0 05055 07H EE OAH Register bank 1 RBE RBS 1 D ODH OFH X 11H 13H Register bank 2 RBE RBS 2 15H B 17H 19H H 1AH Register bank 3 RBE RBS 3 D 37 38 D750008 USER S MANUAL Figure 3 6 General Register Configuration 8 bit Processing When RBE RBS 0 When RBE RBS 2 When RBE RBS When RBE RBS 18H CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP 3 3 MEMORY MAPPED I O The PD750008 employs memory mappe
157. e serial output SO or serial data bus SBO or 581 In receive operation data is read from the serial input SI or 580 or 581 into SIO Data can be read from or written to SIO by using an 8 bit manipulation instruction When the RESET signal is generated during operation the value of SIO is undefined When the RESET signal is generated in the standby mode the value of SIO is preserved Shift operation is stopped after 8 bit send or receive operation is completed Figure 5 42 Peripheral Hardware of Shift Register RELT CMDT SO latch comparator Shift register 4 gt SET CLR A Shift clock BUSY ACK N ch open drain output The timing for reading SIO and start of serial transfer writing to SIO is as follows When the serial interface operation enable disable bit CSIE 1 However the case where CSIE is set to 1 after data is written to the shift register is excluded When the serial clock is masked after 8 bit serial transfer e SCK is high When reading from or writing to SIO make sure that SCK is high In the two wire serial mode and SBI mode the pins specified for the data bus are used for both input and output Because the configuration of output pins is N ch open drain write FFH in SIO for devices that are to receive data Slave address register SVA The slave address register SVA is an 8 bit register for a slave to set its slave address number assigned to it
158. e sets the number assigned to it slave address in SVA The master outputs a slave address to select a particular slave Two data values a slave address output from the master and the value of SVA are compared with each other by the address comparator If a match is found the slave is selected e n the two wire serial I O mode or SBI mode SVA detects an error when data is transferred with the uPD750008 operating as the master or a slave See 4 in Section 5 6 3 for details INTCSI control circuit The INTCSI control circuit controls interrupt request processing The circuit issues an interrupt request INTCSI and set an interrupt request flag IRQCSI in the following cases See Figure 6 1 e In the three wire or two wire serial I O mode An interrupt request is issued whenever eight serial clocks are counted n the SBI mode When WUP7Note 0 an interrupt request is issued whenever eight serial clocks are counted When WUP 1 an interrupt request is issued when values of SVA and SIO match after an address is received Note WUP Wake up function specification bit bit 5 of CSIM 126 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 9 Serial clock control circuit The serial clock control circuit controls the serial clock to be supplied to the shift register or controls the clock to be output to the SCK pin when the internal system clock is used 10 Busy acknowledge output circuit and bus release command acknowledge detection circu
159. e transmission is regarded as successful If the result is 0 the occurrence of a transmission error is assumed Communication operation In the SBI mode the master usually selects a slave device to communicate with from multiple devices by outputting the address of the slave to the serial bus After selecting a device to communicate with the master exchanges commands and data with the slave device thus establishing serial communication Figures 5 67 to 5 70 show the timing charts of data communication operations In the SBI mode the shift register performs shift operation on the falling edge of the serial clock 5 Transmit data is held on the SO latch and is output on the SBO PO2 or SB1 PO03pin starting with the MSB Receive data applied to the 580 or 581 pin is latched in the shift register on the rising edge of SCK CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS OIS VAS ASNd MOV ISoOul E aawolaawo 189 2 indino indino eues eal eos BuisseooJd ASNd n 95 10 085 YOS ane xd E uoissiusueJ ELAS 2 jenas 1xeu JO I eh ee DuisseooJud Buisseooud 1 L d
160. e uPD75P0016 3 Ihe uPD75P0016 does not have a mask option and cannot be connected with a pull up resistor P10 is also used as an external vectored interrupt input pin This input is provided with a noise eliminator See Section 6 3 for details When the RESET signal is generated output latches of ports 2 to 8 are cleared to 0 and the output buffer is turned off so that these ports are in the input mode 68 Internal bus CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 2 Configurations of Ports 0 and 1 SI SCK INT4 SO Internal A A SCK output ue latch Pull up Sel elector Selector 8 gt E P02 SO SBO M M gt V lt f O POO INT4 lt e lt PO1 SCK lt lt Input buffer Input buffer lt O P03 SI SB1 N ch Output buffer which can open drain be switched to either Vop push pull output or N ch open drain output Pull up resistor Selector Noise P10 INTO seen ES lt O P12 INT2 TIO 51 O P13 TIO Y INT2 INTI INTO Input buffer with hysteresis 69 PD750008 USER S MANUAL Figure 5 3 Configurations of Ports 2 and 7 Pull up resistor P ch Bit m of gt 1 POGA Key interru
161. ecified for the register pair Skip if L 2 FH Transfers the data at the data memory location addressed by the specified register pair HL HL HL DE DL to the A register When HL automatic increment is specified for the register pair automatically increments the contents of the L register by one after the data transfer and continues the operation until the contents are set to O 265 uPD750008 USER S MANUAL Then skips the immediately following instruction When HL automatic decrement is specified for the register pair automatically decrements the contents of the L register by one after the data transfer and continues the operation until the contents are set to FH Then skips the immediately following instruction C MOV XA HL Function A lt HL X lt HL 1 Transfers the data at the data memory location addressed by the HL register pair to the A register and transfers the data at the next data memory address to the X register However if the contents of the L register are odd numbered an address with the low order bit ignored is specified Example The data at addresses 3EH and 3FH are transferred to the XA register pair MOV HL 3EH MOV XA HL C 7 MOV HL A Function HL A Transfers the contents of the A register to the data memory location addressed by the HL register pair C 2 MOV HL XA Function HL A HL 1 lt X Transfers the contents of the A register to the data memor
162. ection In the two wire serial I O mode the state of serial bus SBO or SB1 being used for communication is loaded into the shift register SIO of the transmitting device So a transmission error can be detected by the methods described below a Comparing SIO data before start of transmission with SIO data after start of transmission With this method the occurrence of a transmission error is assumed when two SIO values disagree with each other b Using the slave address register SVA Transmit data is set in SVA as well before the data is transmitted On completion of transmission the COI bit match signal from the address comparator of serial operation mode register CSIM is tested If the result is 1 the transmission is regarded as successful If the result is 0 the occurrence of a transmission error is assumed 7 Application of two wire serial I O mode A serial bus is configured and multiple devices are connected to it Example system is configured with a uPD7500068 as the master to which uPD75104 uPD75402A and uPD7225G are connected as slaves pPD750008 master pyPD7225G Port SCK SO SBO uPD75104 To configure the bus as shown above connect the SI pin and SO pin Then writes FFH to the shift register to make the SO pin high except when serial data is output and free the bus by setting off the output buffer The SO pin of the uPD75402A cannot go into a high impeda
163. ed by the GETI instructionNote Note The GETI instruction can represent an arbitrary two byte or three byte instruction or two one byte instructions in one byte and is used to reduce the number of program bytes SeeSection 11 1 1 48 0000H 0002H 0004H 0006H 0008H 000AH 000CH 0020H 007FH 0080H 07FFH 0800H OFFFH Figure 4 3 Program Memory in PD750004 MBE Internal reset start address high order 6 bits Internal reset start address low order 8 bits MBE INTBT INT4 start address INTBT INT4 start address MBE INTO start address INTO start address MBE INT1 start address INT1 start address MBE INTCSI start address INTCSI start address MBE INTTO start address INTTO start address MBE INTT1 start address INTT1 start address high order 6 bits low order 8 bits high order 6 bits low order 8 bits high order 6 bits low order 8 bits high order 6 bits low order 8 bits high order 6 bits low order 8 bits high order 6 bits low order 8 bits GETI instruction reference table Note be used only in the MkII mode Remark Entry address specified in CALLF lfaddr instruc tion Branch address specified in BRCB Icaddr instruc tion CHAPTER 4 INTERNAL CPU FUNCTIONS Branch address specified in BR addr BR BCDE BR BCXA BRA laddr1Nete CALL laddr or CALLA Branch call address by GETI Relative branch address spec
164. ed for communication between the master and slaves lt gt The address of a slave with which the master intends to communicate is transmitted to select the slave chip select This starts communication The slave that has received the address returns ACK to engage in communication with the master The state of the slave is changed from the non selected state to selected state 2 Commands and data are transferred between the master and the slave selected in 1 c3 Command and data are transferred between the master and the selected slave on a one to one basis so the other slaves must be placed in the non selected state Communication is completed when the selected slave is placed in the non selected state This state is caused in the following cases The selected slave is placed in the non selected state when the slave receives a RESET command from the master e The device that is switched from the master to a slave with a CHGMST command is placed in the non selected state iii Command format The transfer format of each command is described below c1 READ command The READ command reads data from a slave One to 256 bytes of data can be read The data length is specified in a parameter by the master When OOH is specified as the data length the 256 byte data transfer is assumed Figure 5 72 Transfer Format of the READ Command Command Data Data Data Remark M Output by the master 5 Output by the slave
165. ed up to the last one An instruction preceded by the interrupt control instruction executed last is executed and an interrupt processing of three machine cycles is executed then the interrupt service routine is started When DI instruction is executed in the period during which is set A in the figure or in the immediately following period the interrupt request of the set IRQn is held until an El instruction is executed CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 2 When IRQn is set during an instruction other than that described in 1 a When IRQn is set at the last machine cycle of the instruction being executed In this case an instruction preceded by the instruction being executed is executed and an interrupt processing of three machine cycles is executed then the interrupt service routine is started An instruction other than interrupt control instruction IRQn is set The next instruction is executed 1 to 3 machine cycles to the instruction Interrupt processing 3 machine cycles Interrupt service routine is executed CREE E d Caution When one or more interrupt control instructions follow an instruction preceded by the interrupt control instructions is executed and an interrupt processing of three machine cycles is executed then the interrupt service routine is started When an instruction to be executed after setting IRQn is a DI instruction the interrupt request of the set IRQn is held b
166. edge of INT4 INTBT is not used All I O ports have a high impedance The INTO and INTTO interrupts are used for the program but are not used to release the STOP mode After the STOP mode is released interrupts are enabled After the STOP mode is released the lowest speed CPU clock is used for operation Then the CPU clock is changed to the high speed one after 250 ms A wait time used when the STOP mode is released is about 31 3 ms After the STOP mode is released another wait time of 31 3 ms is used for stable power supply operation The POO INT4 pin is checked twice to remove chattering CHAPTER 7 STANDBY FUNCTION lt Timing chart gt 2 Voltage on POO INT4 Low speed High speed Wait operation operation Operating mode STOP mode Y CPU operation A 131 3 ms 31 3 ms INT4 INT4 STOP instruction lt Sample program gt INT4 service program MBE 0 VSUB4 SKT PORTO 0O POO 1 BR PDOWN Power down SET1 BTM 3 Power on WAIT SKT IRQBT Wait for 31 3 ms BR WAIT SKT PORTO O Chattering check BR PDOWN MOV A 0011B MOV PCC A Set high speed mode XA XXH Set port mode register MOV PMGm XA El IEO EI IETO RETI PDOWN MOV A 0 Lowest speed mode MOV PCC A MOV XA 00H MOV PMGA XA l O port high impedance MOV PMGB XA DI IEO Disable INTO and INTTO DI IETO MOV A 1011B MOV Wait time 31 3 ms STOP Set STOP mode NOP RETI 22
167. emory location addressed by the HL register pair then sets the result in the A register AND XA rp Function XA rp ANDs the contents of the XA register pair with the contents of register pair ro XA HL DE BC XA DE BC then sets the result in the XA register pair p AND rp 1 XA Function rp 1 XA ANDs the contents of register pair rp 1 HL DE BC XA HL DE BC with the contents of the XA register pair then sets the result in the specified register pair dub OR A n4 Function lt Av4 4 13 0 0 FH ORs the contents of the A register with the 4 bit immediate data n4 then sets the result in the A register Example The low order three bits of an accumulator are set to 1 OR A 0111B C 2 OR A HL Function A Av HL ORs the contents of the A register with the data at the data memory location addressed by the HL register pair then sets the result in the A register C 7 OR XA rp Function XA lt XA v rp ORs the contents of the XA register pair with the contents of register pair ro XA HL DE BC XA HL DE BC then sets the result in the XA register pair 277 uPD750008 USER S MANUAL C 2 OR rp 1 XA Function v XA ORs the contents of register pair rp 1 HL DE BC XA HL DE BC with the contents of the XA register pair then sets the result in register pair rp 1 C 2
168. en skip unconditionally Mk mode _ PC44 g lt SP 0 0 0 PCy SP 1 0 lt SP 2 PC7 4 lt SP 3 x X MBE RBE SP 4 SP lt SP 6 Then skip unconditionally Restores the program counter PC memory bank enable flag MBE and register bank enable flag RBE with the data at the data memory location stack addressed by the stack pointer SP then skips unconditionally after incrementing the contents of SP Caution The program status word PSW is not restored except MBE and RBE 291 uPD750008 USER S MANUAL Remark Function in this section is applicable to the uPD750008 whose program counter consists of 13 bits addr OOOOH to 1FFFH However this is also applicable to the uPD750004 whose program counter consists of 12 bits addr OOOOH to OFFFH the uPD750006 whose program counter consists of 13 bits addr OOOOH to 17FFH and the uPD75P0016 whose program counter consists of 14 bits addr OOOOH to 3FFFH RETI Function For the uPD750008 Mk mode 11 8 lt SP MBE RBE 0 12 lt SP 1 lt SP 2 PC7 4 lt SP 3 PSW lt SP 4 PSWy SP 5 SP lt SP 6 Mk mode 11 8 lt SP 0 0 0 12 lt SP 1 PC5 9 lt SP 2 lt SP 3 PSW lt SP 4 PSWy lt SP 5 SP lt SP 6 Restores the program counter PC and program status word with the data at the data memory location stack addressed
169. enable flag Figure 7 1 shows how the STOP and HALT modes are released Figure 7 1 Standby Mode Release Operation 1 2 a Release of the STOP mode by RESET signal STOP instruction Wait Note a RESET signal Operating Operating mode STOP mode HALT mode mode J gt Oscillation No oscillation Oscillation Clock gt 6 Release of the STOP mode by the occurrence of an interrupt Wait Time set by BTM STOP instruction Standby release signal ee Operating Operating mode STOP mode HALT mode mode gt Oscillation No oscillation Oscillation Clock Note The following two wait times can be selected by a mask option 217 21 8 ms at 6 00 MHz 31 3 ms at 4 19 MHz 215 f 5 46 ms at 6 00 MHz 7 81 ms at 4 19 MHz However the uPD75P0016 does not have a mask option and its wait time is fixed to 215 fx Remark The dashed line indicates the case where the interrupt request that releases the standby mode is accepted 217 PD750008 USER S MANUAL Figure 7 1 Standby Mode Release Operation 2 2 c Release of the HALT mode by RESET signal Wait Note HALT instruction 23 TETTE RESET signal Operating Operating mode HALT mode mode gt lt lt Oscillation Clock d Release of the HALT mode by the occurrence of an interrupt HALT instruction HALT mode Standby release signal
170. ence 270 1143 Bib Transter eet tio antenas 273 11 4 4 Arithmetic Logical Instructions 273 11 4 5 Accumulator Manipulation 279 11 4 6 Increment Decrement Instructions 0 279 13 4 7 Compa e Instruci n uses ns one cess d 280 11 4 8 Flag Manipulation Instructions 281 11 4 9 Memory Bit Manipulation Instructions 282 132410 Branch eget teresa 284 11 4 11 Subroutine Stack Control Instructions 289 11 4 12 Interrupt Control Instructions 2 293 VALE AS TO InsttchOoUS idonei O E 294 11214 OPU Control InSttHouofiS Pot 295 1124 15 Special InStrUGlloliS initia ced ooo astute Sup 295 APPENDIX A FUNCTIONS OF THE pPD75008 pPD750008 AND pPD75P0016 299 APPENDIX B DEVELOPMENT TOOLS RE aaraa aeaa aaea aaau aea 301 APPENDIX C MASKED ROM ORDERING PROCEDURE essere nnne nnns 309 APPENDIX D INSTHUGTION INDEX epe die us 311 D 1 INSTRUCTION INDEX BY FUNCTION nei a R 311 D 2 INSTRUCTION INDEX ALPHABETICAL ORDER
171. ent or NEC s Sales Department otherwise the ordered products may be delivered with delay Preparation of media for ordering Use three UV EPROMs having the same contents or 3 5 or 5 25 inch IBM format floppy disk in ordering a masked ROM Prepare a mask option information sheet describing the mask option data Preparation of the required documents Prepare the following documents when ordering a masked ROM Masked ROM order sheet Masked ROM order check sheet Mask option information sheet Ordering Send a set of the media created in lt 2 gt and the documents created in lt 3 gt to a special agent or NEC s Sales Department by the date indicated in the advance notice 309 PD750008 USER S MANUAL MEMO 310 D 1 APPENDIX D INSTRUCTION INDEX INSTRUCTION INDEX BY FUNCTION Transfer instructions A n4 245 264 MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV XCH XCH XCH XCH XCH XCH XCH XCH XCH reg1 n4 XA n8 HL n8 rp2 n8 A HL A HL A HL A rpa1 XA HL HL A HL XA A mem XA mem mem A mem XA 245 265 245 265 245 265 245 265 245 265 245 265 245 265 245 265 245 266 245 266 245 266 245 266 245 267 245 267 245 267 A reg 245 267 XA rp 245 267 reg1 A 245 268 rp 1 A QHL A HL A HL
172. esistor is not used Cut flag for the sub oscillator current Drive current is high 1 8 V lt 1 Drive current is low 2 7 V lt Bits 2 and 3 of SOS must be set to O Remark f the subsystem clock is not required the XT1 and XT2 pins and SOS register must be treated as follows XT1 Connected to Vss or Vpp XT2 Open SOS 0001B 93 PD750008 USER S MANUAL 5 2 3 System Clock and CPU Clock Setting 1 Time required to change the system clock and CPU clock The system clock and CPU clock can be changed by using the least significant bit of the SCC and the low order two bits of the PCC This switching is not performed immediately after the contents of the registers are rewritten but the system operates with the previous clock for some machine cycles Accordingly after this time period the STOP instruction must be executed to terminate main system clock generation Table 5 5 Maximum Time Required to Change the System Clock and CPU Clock Setting before switching aae ao Pe genes eros er ae 1 machine 1 machine 1 machine fx 64fxt machine cycle cycle cycles 3 machine cycles Setting after switching 4 machine 4 machine 4 machine Not to be set cycles cycles cycles 8 machine 8 machine 8 machine fx 8fxt machine cycles cycles cycles cycles 23 machine cycles 16 machine 16 machine 16 machine fx 4fxt machine cycles cycles cycles cyc
173. esistors can be connected by software in units of 2 bits I O circuits enclosed in circles have a Schmitt triggered input An LED can be driven directly uPD75P0016 When pull up resistors that can be specified with the mask option are not incorporated when pins are used as N ch open drain input ports the input leak low current increases when an input instruction or bit operation instruction is executed These pins of the uPD75P0016 are not provided with pull up resistors by mask option and are always open CHAPTER 2 PIN FUNCTIONS Table 2 2 Non Port Pin Functions Pin used Function circuit output He typeNote 1 Input P13 _ Inputs external event pulse to the timer event C PTOO I O Timer event counter output Input E B 1 co Timer counter output POL E B BUZ I O P23 Fixed frequency output Input E B o ayem sock inmin O SOK 50 580 SI SB1 I O Serial data input or serial data bus I O 4 Input Edge detection vectored interrupt input Either a rising or falling edge is detected The INTO P10 pin has a noise eliminating function INTO Input Edge detection vectored interrupt input HTT pit ee detec Archos _ INT2 Rising edge detection testable input Asynchronouus KRO KRS P A KR4 KR7 Parallel falling edge detection testable input 1 X2 Input Connection pin
174. face control register SBIC a Serial operation mode register CSIM To use the SBI mode set CSIM as shown below For details on CSIM format see 1 in Section 5 6 3 CSIM is manipulated using an 8 bit manipulation instruction Bits 7 6 and 5 of CSIM can be manipulated bit by bit When the RESET signal is input CSIM is set to OOH In the figure below hatched portions indicate the bits used in the SBI mode Address FEOH 7 6 5 4 3 2 0 CSIE CSIV CSIM _ Serial clock selection bit W Serial interface operation mode selection bit W Wake up function specification bit W Match signal from address comparator R Serial interface operation enable disable specification bit W Remark R Read only W Write only 156 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Serial interface operation enable disable specification bit W Shift register operation Shift register operation operation Serial clock counter clock counter flag flag SO SBO and SI SB1 pins and SI SB1 SO SBO and SI SB1 pins CSIE Shift operation enabled Count Can be set Used in each mode as well as for port O Signal from address comparator R CO Note Condition for being cleared COI 0 Condition for being set COI 1 When the slave address register SVA When the slave address register SVA does not match the data of the shift
175. gnal lt 1 gt lt 2 gt 2171 21 8 ms at 6 00 MHz 31 3 ms at 4 19 MHz 215 f 5 46 ms at 6 00 MHz 7 81 ms at 4 19 MHz However the uPD75P0016 dose not have a mask option and its wait time is fixed to 219 fy 7 5 APPLICATIONS OF THE STANDBY MODES When the standby modes are used the following steps are used c1 c2 c3 lt 4 gt lt 5 gt lt 6 gt lt gt Detect a standby mode setting factor such as power removal on an interrupt input or port input INT4 is useful for power removal detection Configure I O ports for minimum current drain Specify interrupts for releasing a standby mode INT4 is useful All interrupt enable flags not used for release are to be cleared Specify an operation to be performed after release IME is to be manipulated according to whether interrupt processing is performed or not Specify a CPU clock to be used after release If the CPU clock is changed required machine cycles must elapse before the standby mode is set Select a wait time to be used when a standby mode is released Set a standby mode using a STOP or HALT instruction A standby mode when combined with the system clock switch function enables a lower power consumption and lower voltage operation 1 Application of the STOP mode at fy 4 19 MHz 220 lt Use of the STOP mode under the following conditions gt The STOP mode is set on the falling edge of INT4 and is released on the rising
176. guration 124 Block Diagram of the Serial 125 Format of Serial Operation Mode Register CSIM 127 Format of Serial Bus Interface Control Register SBIC 131 Peripheral Hardware of Shift Register 134 Example of Three Wire Serial System 137 Timing of Three Wire Serial l O 140 vil Figure No 5 45 5 46 5 47 5 48 5 49 5 50 5 51 5 52 5 53 5 54 5 55 5 56 5 57 5 58 5 59 5 60 5 61 5 62 5 63 5 64 5 65 5 66 5 6 5 68 5 69 5 70 5 71 5 72 5 73 5 74 5 5 5 76 5 77 5 78 5 79 5 80 LIST OF FIGURES 3 4 Title Page Operations Of REE GM DET 141 Transter Bit Switching Cire s aceti ee nei 141 Example of Two Wire Serial I O System Configuration 2 144 Timing of Two Wire Serial 147 Operations OF RELY and GMD 148 Example of SBI System Configuration 0 ccsccseececsccseescccccseesensceseseeesecseeeessccseres 150 C T 152 Buseleaseigrial 153 COMMIS ele mL ERE 153 Addr ESS EE 153 Slave Selection Using an 0 154 Sosa oe T T m mE 154 M
177. h a crystal resonator or ceramic resonator connected to the X1 and X2 pins An external clock can also be input Input the clock signal to the X1 pin and the reversed signal to the X2 pin Figure 5 14 External Circuit for the Main System Clock Oscillator a Crystal ceramic oscillation b External clock uPD750008 PD750008 External clock gt X1 Crystal or ceramic resonator Standard frequency 6 0 or 4 19 MHz The subsystem clock oscillator operates with a crystal resonator 32 768 kHz standard connected to the XT1 and XT2 pins An external clock can also be input Input the clock signal to the XT1 pin and leave the XT2 pin open The state of the XT1 pin is tested by bit 3 of the clock mode register WM Figure 5 15 External Circuit for the Subsystem Clock Oscillator a Crystal oscillation b External clock 0750008 0750008 Vss External XT clock Co XT2 Open XT2 Crystal Standard frequency 32 768 kHz Cautions 1 When the external clock is used as the main system clock or subsystem clock the STOP mode cannot be set This is because the X1 pin is connected to Vss in the STOP mode 2 When the main system clock or subsystem clock oscillator is used conform to the following guidelines when wiring enclosed in broken lines of Figures 5 14 and 5 15 to eliminate the influence of the stray capacitance around the wiring The wiring must be as short as possible Other signa
178. hannels e Easy replacement The functions and instructions of the uPD75008 are taken over The 75XL series comes in four models according to the size and type of program memory see Table 1 1 Table 1 1 Features of the Products Model Program memory ROM Remarks uPD750004 4096 x 8 bits Masked ROM uPD750006 6144 x 8 bits uPD750008 8192 x 8 bits uPD75P0016 16384 x 8 bits One time PROM The 075 0016 having the electrically programmable one time PROM is pin compatible with the uPD750004 uPD750006 and uPD750008 It is suitable for small scale production or prototype production in system development Applications Consumer electronics VCR audio equipment such as CD players remote controller etc Others Telephone camera etc Remark This manual will explain only the uPD750008 when the uPD750008 uPD750004 uPD750006 and uPD75P0016 are functionally the same Users of the 0750004 uPD750006 or UPD75P0016 should read uPD750008 as referring to 750004 uPD750006 or uPD75P0016 1 1 PD750008 USER S MANUAL Item Instruction execution time Internal memory ROM RAM General register I O port Timer Serial interface Bit sequential buffer Clock output Vectored interrupt Test input System clock oscillator Standby function Operating ambient temperature Supply voltage Package FUNCTION OVERVIEW Function 0 95 1 91 3 81 15 3 us when the main
179. he RBE to the state of bit 6 at program memory address 0 When a vectored interrupt occurs the RBE is automatically set to the state of bit 6 in the vector address table for servicing the interrupt Usually the RBE is set to 0 in interrupt processing Register bank 0 is used for 4 bit processing and register banks 0 and 1 are used for 8 bit processing 4 9 BANK SELECT REGISTER BS The bank select register BS consists of a register bank select register RBS and memory bank select register MBS which specify a register bank and memory bank to be used respectively The RBS and MBS are set using the SEL RBn instruction and SEL MBn instruction respectively The contents of the BS can be saved to or restored from a stack memory eight bits at a time by using the PUSH BS POP BS instruction 1 2 Figure 4 17 Bank Select Register Format Address F83H TOT F8 H Symbol F82H MBS3 MBS2 MBS1 MBSO RBS1 RBSO BS Memory bank select register MBS The memory bank select register is a 4 bit register used to store the high order four bits of a 12 bit data memory address The contents of this register specify a memory bank to be accessed The 0750008 allows memory banks 0 1 and 15 only to be specified The MBS 15 set with the SEL instruction n 0 1 15 Figure 3 2 shows the range of addressing using MBE and MBS settings A RESET signal initializes the MBS to 0 Register bank select register RBS
180. he RESET ani eee 178 Transfer Format of the CHGMST 178 Master and Slave Operation in Case of Error 179 SCK PO1 Pin Circuit exeo 180 Vili Figure No 5 81 6 1 6 2 6 3 6 4 6 5 6 6 6 6 8 6 9 6 10 6 11 7 1 7 2 8 1 8 2 1 2 LIST OF FIGURES 4 4 Title Page Format of the Bit Sequential 181 Block Diagram of Interrupt Control 184 Vector 185 Interrupt Priority Specification Register 189 Configurations of the INTO INT1 and INT4 Circuits 1 191 VO Timing Of a Noise un oso oerte esr ede nate 192 Format of Edge Detection Mode Registers 193 aoi nte a Du dab uae 195 Multiple Interrupt Processing by a High Order 196 Multiple Interrupt Processing by Changing the Interrupt Status Flags 197 Block Diagram of the INT2 and KRO to KR7 212 Format of INT2 Edge Detection Mode Register 1 2 213 Standby Mode Release 218 Wait
181. hen 1 is written into the bit the counter and IRQTO flag are cleared If bit 2 is set to 1 count operation is started Operation mode Count operation Stop retention of count contents Count operation 112 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 31 Timer Counter Mode Register Channel 1 Format Address Symbol FA8H ER TM15 TM14 TM13 TM12 BT TM1 Count pulse CP select bit When fx 6 00 MHz TM16 TM15 TM14 Count pulse CP fx 2 1 46 kHz fx 2 5 86 kHz fx 2 23 4 kHz fx 29 93 8 kHz Not to be set fx 2 2 1 02 kHz fx 2 4 09 kHz fx 28 16 4 kHz fx 29 65 5 kHz Other than above Not to be set Timer start indication bit TM13 When 1 is written into the bit the counter and IRQT1 flag are cleared If bit 2 is set to 1 count operation is started Operation mode Count operation Stop retention of count contents 1 Count operation 113 PD750008 USER S MANUAL 2 Timer event counter output enable TOEO TOE1 The timer event counter output enable flag TOEO TOE1 controls the output enable disable to the PTOO and PTO 1 pins in the timer out flip flop TOUT flip flop status The timer out flip flop is inverted by the match signal sent from the comparator When bit 3 of the timer event counter mode register 1 is set to 1 the timer out flip flop is cleared to 0 TOEO TOE1 and timer o
182. her with the carry flag to the contents of the A register in binary If the addition generates a carry the carry flag is set If no carry is generated the carry flag is reset If the execution of this instruction generates a carry when this instruction is immediately followed by the ADDS 4 instruction the ADDS A n4 instruction is skipped If no carry is generated the ADDS A n4 instruction is executed and the skip function of the ADDS A n4 instruction is disabled Accordingly a combination of these instructions can be used for number system conversion See Section 11 1 274 CHAPTER 11 INSTRUCTION SET ADDC XA rp Function XA CY lt Adds the contents of register pair ro XA HL DE BC XA HL DE BC together with the carry flag to the contents of the XA register pair in binary If the addition generates a carry the carry flag is set If no carry is generated the carry flag is reset Co ADDC rp 1 XA Function 1 CY lt rp 1 XA CY Adds the contents of the XA register pair together with the carry flag to the contents of register pair rp 1 HL DE BC XA HL DE BC in binary If the addition generates a carry the carry flag is set If no carry is generated the carry flag is reset CD SUBS A HL Function A lt A HL Skip if borrow Subtracts the data at the data memory location addressed by the HL register pair from the contents of the A register
183. hts of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customer must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the quality grade of each device before using it in a particular application standard Computers office equipment communications equipment testand measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster syste
184. iation cannot be performed 2 Handle the pins not used for writing to or verifying the program memory as follows Pins other than XT2 Connect these pins to Vss through pull down resistors XT2 pin Open 229 PD75008 USER S MANUAL 9 1 OPERATING MODES WHEN WRITING TO AND VERIFYING THE PROGRAM MEMORY If 6 V is applied to the pin and 12 5 V is applied to the Vpp pin the uPD75P0016 enters program memory write verify mode The specific operating mode is then selected by the setting of the MDO through MD3 pins as listed in the table below arcu mode specification Operating mode 412 5 6V pues Program memory address clear mode L Remark X indicates L or H 9 2 WRITING TO THE PROGRAM MEMORY The procedure for writing to program memory is described below high speed write is possible 1 Pull low all unused pins to Vss by means of resistors Bring X1 to low level Apply 5 V to Vpp and to Vpp Wait 10 us Select program memory address clear mode Apply 6 V to Vpp and 12 5 V to Vpp Select program inhibit mode Select write mode for 1 ms duration and write data Select program inhibit mode 9 Select verify mode If write is successful proceed to step 10 If write fails repeat steps 7 to 9 Perform additional write for Number of repetitions of steps 7 to 9 x 1 ms duration Select program inhibit mode Increment the p
185. ied by MB MBE MBS are indirectly specified using the H register and the low order four bits and bit address are directly specified in the operand This addressing mode enables a wide variety of manipulations for each bit in the entire data memory space Example Bit 2 at address 32H FLAGS is reset if both bit at address FLAG1 and bit at address FLAG2 are set to 0 or 1 FLAGS FLAG2 FLAG1 EQU 30H 3 FLAG2 EQU 31H 0 FLAG3 EQU 32H 2 SEL MBO MOV H FLAG1 SHR 6 MOV1 CY H FLAG1 CY FLAG XOR1 CY H FLAG2 CY lt CY V FLAG2 MOV1 H FLAGS CY FLAGS CY CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP 7 Stack addressing This addressing mode is used for save restoration operation in interrupt processing or subroutine processing In this addressing mode the address indicated by the stack pointer 8 bits of data memory bank 0 is specified This addressing mode can be used for register save restoration operation using the PUSH or POP instruction as well as save restoration operation in interrupt and subroutine processing Examples 1 A register is saved and restored in subroutine processing SUB PUSH XA PUSH HL PUSH BS Save MBS and RBS POP BS POP HL POP XA RET 2 The contents of the HL register pair are transferred to the DE register pair PUSH HL POP DE DE HL 3 A branch is made to the address indicated by the XABC register PUSH BC PUSH XA RET B
186. ified in BR addr instruction 15 to 1 2 to 16 In addition to the above the BR PCDE and BR instructions can cause a branch 10 address with only the 8 low order bits of the PC changed 49 PD750008 USER S MANUAL Figure 4 4 Program Memory in PD750006 7 6 0 0000H Internal reset start address high order 6 bits Internal reset start address low order 8 bits 0002H INTBT INT4 start address high order 6 bits INTBT INT4 start address low order 8 bits Entry address 0004H INTO start address high order 6 bits specified in CALLF INTO start address low order 8 bits Ifaddr instruc Branch 0006H INT1 start address high order 6 bits tion address specified INT1 start address low order 8 bits ICE 0008 INTCSI start address high order 6 bits INTCSI start address low order 8 bits tion 000AH INTTO start address high order 6 bits Branch address specified in INTTO start address low order 8 bits BR addr BR BCDE 000CH INTT1 start address high order 6 bits BR BCXA BRA laddr1Nete INTT1 start address low order 8 bits CALL addr or CALLA laddr1Ne e 0020H address by GETI instruction reference table 007FH 0080H Relative branch address specified in OFER eee eee ee ee BR addr 0800H instruction 715 to 1 2 to 16 Mata te at ee eet ee rie 1000H Branch address
187. ine For this determination the DI instruction is to be executed at the start of the interrupt service routine and the interrupt request flags are checked with the SKTCLR instruction If both the request flags are set when this request flag is tested or cleared the interrupt request remains even if one of the request flags is cleared If this interrupt is selected as having the higher priority nesting processing is started by the remaining interrupt request Consequently the interrupt request not tested is processed first If the selected interrupt has the lower priority the remaining interrupt is kept pending and therefore the interrupt request tested is processed first Therefore an interrupt sharing a vector address with another interrupt is identified differently depending whether it has the higher priority as shown in Table 6 4 Table 6 4 Identifying Interrupt Sharing Vector Table Address With higher priority Interrupt is disabled and interrupt request flag of interrupt that takes precedence is tested With lower priority Interrupt request flag of interrupt that takes precedence is tested 198 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Examples 1 To use both INTBT and INT4 as having the higher priority and give priority to INT4 DI SKTCLR IRQ4 IRQ4 1 BR _ VSUBBT Processing routine El of INT4 RETI VSUBBT IRQBT Processing routine of INTBT El RETI 2 To use both INTBT and INT4 as having the lower pri
188. ins When a bit output instruction is executed the specified bit of the output latch is rewritten and is output on the pin 79 PD750008 USER S MANUAL Table 5 3 Operations by I O Port Manipulation Instructions Port and pin operation Instruction Input mode Output mode SKT Pin data is tested Output latch data is tested SKF MOV1 CY Pin data is transferred to CY Output latch data is transferred to CY CY An operation is performed on pin data and An operation is performed CY GY on output latch data and CY CY A PORTn Pin data is transferred to the accumulator Output latch data is transferred to the XA PORTn accumulator A HL XA HL A HL An operation is performed on pin data and An operation is performed ADDC A HL the accumulator on output latch data and the accumulator SUBS A HL SUBC A HL AND A HL OR A HL XOR A HL SKE A HL Pin data is compared with the Output latch data is com SKE XA HL accumulator pared with the accumulator PORTn A Accumulator data is transferred to the Accumulator data is transferred to the PORTn XA output latch with the output buffers kept output latch and is output on the pins HL A off HL XA Pin data is transferred to the accumulator Data is exchanged between the output and accumulator data is transferred to the latch and accumulator output latch with the output buffers kept off INCS PORTn Pin data incremented by 1 is latche
189. instruction Example The data at addresses 20H 2FH are exchanged with the data at addresses 30H 3FH SEL MBO MOV D 2 MOV HL 30H LOOP XCH A HL A lt gt XCH A DL A lt gt 2x XCH A HL A lt gt 3x BR LOOP 268 CHAPTER 11 INSTRUCTION SET T XCH XA HL Function A lt gt HL X lt gt HL 1 Exchanges the contents of the A register with the data at the data memory location addressed by the HL register pair and exchanges the contents of the X register with the data at the next memory address However if the contents of the L register are odd numbered an address with the low order bit ignored is specified lt gt XCH A mem Function A lt gt mem mem 05 0 00H FEH Exchanges the contents of the A register with the data at the data memory location addressed by the 8 bit immediate data mem C 2 XCH XA mem Function lt gt mem X lt gt mem 1 Dz g 00H FEH Exchanges the contents of the A register with the data at the data memory location addressed by the 8 bit immediate data mem and exchanges the contents of the X register 1 with the data at the next memory address An even address can be specified with mem C 2 A reg1 Function lt gt reg1 Exchanges the contents of the A register with register reg1 X H L D E B C C 2 XCH XA rp Function XA lt gt Exchanges the contents of the XA register pair with the content
190. is snoueA 01 5 IALL 166 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 6 Pin configuration The configurations of serial clock pin SCK and serial data bus pin 580 581 are as follows SCK Pin for serial clock I O lt 1 gt Master CMOS push pull output lt 2 gt Slave Schmitt input b 580 581 Pin for serial data I O Output to SBO or SB1 is an N ch open drain output and input is Schmitt input for both the master and a slave The serial data bus line must be externally pulled up because it has originally an N ch open drain output Figure 5 66 Pin Configuration Slave device Master device LI LI NUN Clock output Clock output O gt O gt Clock input Serial clock Clock input N ch open drain SBO 58 _ SB1 N ch open drain 50 gt Serial data bus H 50 TTT TTT Caution When data is received the N ch transistor must be turned off so must be written to SIO beforehand The N ch open drain output can be turned off at any time during transfer However when the wake up function specification bit WUP is set to 1 the N ch transistor is always off so there is no need to write FFH to SIO before reception 167 PD750008 USER S MANUAL 7 8 9 168 Address match detection method In the SBI mode communication starts when the master selects a particular slave device by outputting an address An address ma
191. it is set to 1 the BT is cleared and the basic interval Itimer watchdog timer interrupt request flag IRQBT is also cleared to start the basic interval timer watchdog timer A RESET signal clears the interval timer to 0 and the longest interrupt request signal generation interval time 15 set Figure 5 24 Format of the Basic Interval Timer Mode Register Address Symbol F85H BTM 2 1 0 BTM3 BTM2 BTM1 BTMO fx 6 00 MHz ti Input clock specification dea wait time for releasing standby fx 2 1 46 kHz 2200175 ms fx 2 11 7 kHz 2 7 fx 21 8 ms fx 2 46 9 kHz 2 5 fx 5 46 ms fx 2 188 kHz 2 5 fx 1 37 ms fx 2 1 02 kHz 2 9 fx 250 ms fx 2 8 18 kHz 21 31 3 ms 27 32 768 kHz 2 5 x 7 82 ms fx 2 131 kHz 2 fx 1 95 ms Other than above Not to be set Basic interval timer watchdog timer start control bit When 1 is written to this bit the basic interval timer watchdog timer operation starts the counter and the interrupt request flag are cleared When the operation starts this bit is automatically reset to O 100 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5 3 3 Watchdog Timer Enable Flag WDTM WDTM when set is a flag for enabling the generation of the reset signal when the basic interval timer overflows WDTM is set by a bit manipulation instruction It cannot be cleared by an instruction Example Set the watchdog timer function SEL 15
192. it The busy acknowledge output circuit and bus release command acknowledge detection circuit output and detect control signals generated in the SBI mode These circuits do not operate in the three wire or two wire serial I O mode 11 P01 output latch The P01 output latch generates serial clock by software after the eighth serial clock has been output When the RESET signal is entered this latch is set to 1 To select the internal system clock as the serial clock set the P01 output latch to 1 5 6 3 Register Functions 1 Serial operation mode register CSIM Figure 5 40 shows the format of serial operation mode register CSIM CSIM is an 8 bit register which specifies a serial interface operation mode serial clock wake up function and so forth CSIM is manipulated using an 8 bit memory manipulation instruction The higher three bits can be manipulated bit by bit Each bit can be manipulated using its name Each bit may or may not allow read and or write operation seeFigure 5 40 Bit 6 allows bit test operation only any data written to this bit is invalid When the RESET signal is generated all bits are cleared 10 0 Figure 5 40 Format of Serial Operation Mode Register CSIM 1 4 Address Symbol 7 6 5 4 3 2 1 0 FEoH CSIE CSIM3 csim2 csIM Serial clock selection bit W Serial interface operation mode selection bit W Wake up function specification bit W Signal from a
193. it time is fixed to 215 fy 2 INT4 is useful 95 PD750008 USER S MANUAL 5 2 4 Clock Output Circuit 1 Configuration of the clock output circuit Figure 5 20 shows the configuration of the clock output circuit 2 Functions of the clock output circuit The clock output circuit outputs a clock pulse signal on the P22 PCL pin to output remote control signals or to supply clock pulses to a peripheral LSI device The procedure for outputting a clock pulse signal is as follows a Select a clock output frequency and disable clock output b Write a in the P22 output latch c Set the output mode for port 2 d Enable clock output Figure 5 20 Configuration of the Clock Output Circuit From the clock generator Output f x 2 buffer Selector 4 f x 2 PCL P22 f x 2 Port 2 input CLOM3 CLOM1 cLoM 5 MR output mode aic specification bit 4 Internal bus Remark The clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling clock output 96 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 3 Clock output mode register CLOM The CLOM is a 4 bit register to control clock output The CLOM is set by a 4 bit memory manipulation instruction No read operation is allowed on this register Example CPU clock is output on the PCL P22 pin SEL MB15 CLR1 MBE MOV A 1000B MOV CLOM A A RESET signal clears the CLOM to 0 disabling clo
194. k is A RESET input clears IMO and IM1 to 0 selecting rising edge active The INT1 pin can also be used to release the STOP and HALT modes but the INTO pin cannot Schmitt triggered inputs are used for the INTO and INT1 pins 2 211 INT2 Input Pin Used Also for Port 1 This is a rising edge active external test input pin When INT2 is selected with the edge detection mode register IM2 or when the signal applied to this pin goes high the internal test flag IRQ2 is set INT2 is an asynchronous input and can accept a signal with some high level width regardless of the operating clock of the CPU A RESET signal clears IM2 to 0 In this case the test flag IRQ2 is set by a rising edge on the INT2 pin The INT2 pin can also be used to release the STOP and HALT modes A Schmitt triggered input is used for this pin 2 2 12 KRO KR3 Input Pins Used Also for Port 6 KR4 KR7 Input Pins Used Also for Port 7 KRO to KR7 are key interrupt input pins An interrupt is caused when parallel falling edges are detected on them The interrupt format can be specified with the edge detection mode register IM2 A RESET signal places these pins in the port 6 and 7 input modes 2 2 13 X1 X2 These pins are used for connection to a crystal or ceramic resonator for main system clock generation An external clock can also be applied a Crystal ceramic oscillation b External clock 0750008 0750008 External clock u PD
195. l command processing being performed When the transmission of one byte is completed the master checks for ACK from the slave 178 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS If ACK is not returned from the slave within a predetermined period after transmission completion the occurrence of an error is assumed the master outputs the ACK signal as a dummy Figure 5 79 Master and Slave Operation in Case of Error Processing by slave Reception is completed Error is assumed and processing is halted SBO SB1 Erroneous data ACK ACK wait time Processing by master ACK from slave is checked Transfer is completed Error is assumed ACK check is started ACK 15 output The following errors may occur Error that may occur on the slave side lt 1 gt Invalid command transfer format lt 2 gt Reception of an undefined command lt 3 gt Insufficient number of transfer data bytes for a READ command lt 4 gt Insufficient area to contain data for WRITE command lt 5 gt Change in data during transmission of a READ STATUS or CHGMST command If any of the above types of errors occurs ACK is not returned Error that may occur on the master side If data transmitted with a WRITE command changes during transmission the master transmits a STOP command to the slave 5 6 8 Manipulation of SCK Pin Output The 5 01 pin has a built in output latch so that this pin allows static output by software manipulation in addition to
196. l lines must not run in these areas 89 PD750008 USER S MANUAL 90 Any line carrying a high pulsating current must be kept away as far as possible The grounding point of the capacitor of the oscillator must have the same potential as that of Vss It must not be grounded to a grounding pattern carry ing a high current No signal must be taken directly from the resonator The subsystem clock oscillator has low amplification to minimize current con sumption For this reason more malfunctions can occur due to noise than the main system clock oscillator So pay special attention to wiring when using the subsystem clock Figure 5 16 gives examples of oscillator connections which should be avoided Figure 5 16 Examples of Oscillator Connections Which Should Be Avoided 1 2 a The wiring is too long b The signal lines cross PORTn n 0 to 8 uPD750008 uPD750008 Remark When wiring the subsystem clock read X1 and X2 as XT1 and XT2 respectively In this case a resistor must be added to XT2 in series CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 16 Examples of Oscillator Connections Which Should Be Avoided 2 2 c A high pulsating current is too d The current flows through the ground close to the signal line line of the oscillator The potential at points A B and C fluctuates uPD750008 UPD750008 High current E I B
197. le for bit manipulation a Bit setting SET1 mem bit SET1 mem bit b Bit clearing CLR1 mem bit CLR1 mem bit c Bit testing SKT mem bit SKT mem bit d Bit testing SKF mem bit SKF mem bit e Bit testing and clearing SKTCLR mem bit f Boolean operation AND1 CY mem bit OR1 CY mem bit XOR1 CY mem bit mem bit represents a bit address addressed by using a bit manipulation addressing mode fmem bit pmem L or H mem bit Particularly all of these bit manipulation instructions can be used for the I O ports so that I O port manipulation can be performed in a very efficient manner 11 1 3 String Effect Instructions With the uPD750008 two types of string effect instructions are available a MOV A n4 or MOV XA n8 b MOV HL n8 String effect means the locating of these two types of instructions at contiguous addresses Example AO MOV A 0 A1 MOV A 1 XA7 MOV XA 07 When string effect instructions are arranged as in this example if execution starts at address AO the following two instructions are replaced with an NOP instruction If execution starts at address A1 the following one instruction is replaced with an NOP instruction That is only the instruction first executed is valid and any following instructions are processed as an NOP instruction By using string effect instructions a constant can be set in an accumulator the A register or the XA register pair or data pointer the HL register pair
198. les 46 machine cycles 1 machine Not to be 1 machine 1 machine cycle set cycle cycle Remarks 1 Time indicated in parentheses is required when fx 6 00 MHz and 32 768 kHz 2 X Dont care 3 CPU clock is supplied to the CPU of the uPD750008 The reciprocal of this frequency is a minimum instruction time defined as one machine cycle in this manual Cautions 1 When the PCC is set to 0001B fy 16 do not set SCC 0 to 1 Before switching the main system clock to the subsystem clock be sure to manipulate the PCC so other than 0001B is set When the system operates on the subsystem clock the PCC must also be other than 0001B 2 The fluctuation of the ambient temperature around an oscillator and the performance of a load capacity change fy and fxr In particular when fy is higher than the nominal value is lower than the nominal value the machine cycles calculated by fy 64fy7 fx 8fy7 and fy 4fy7 in Table 5 5 are longer than the machine cycle calculated by the nominal values of fy and fxr Therefore the wait time required to change the system clock and CPU clock should be longer than the machine cycle calculated by the nominal values of fy and fxr 94 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 2 Procedure for changing the system clock and CPU clock The procedure for changing the system clock and CPU clock is explained using Figure 5 19 Figure 5 19 Changing the System Clock and CPU Clock power c
199. llows STOP mode In the STOP mode the main system clock oscillator is stopped and the entire system stops The current used by the CPU is reduced to quite a low level In addition the contents of data memory can be preserved with a low supply voltage of down to Vpp 1 8V that is this mode is effective to retain data memory with a very low current The STOP mode of the uPD750008 can be released by an interrupt request to enable intermittent operations However when the STOP mode is released a wait time is needed for stable oscillation Select the HALT mode when processing must be started immediately after an interrupt request HALT mode In the HALT mode the CPU clock is stopped but the oscillation of the system clock oscillator continues In this mode the system uses more current than in the STOP mode However the HALT mode is suitable for starting processing immediately after an interrupt request or for intermittent operations such as watch operation In either mode all contents of the registers flags and data memory that are present immediately before the standby mode is set are preserved In addition the states of the output latches of the I O ports and the states of the output buffers are also preserved so that the states of the I O ports are to be processed to minimize the power consumption of the entire system Cautions 1 The STOP mode can be used only for the main system clock Subsystem clock generation cannot be te
200. location stack addressed by the stack pointer SP then increments SP The low order part of a register pair rp A L E C is restored from the contents of SP and the high order part X D B is restored with the contents of SP 7 PoPss Function RBS SP MBS SP 1 SP lt SP 2 Restores the register bank select register RBS and the memory bank select register MBS with the data at the data memory location stack addressed by the stack pointer SP then increments SP 11 4 12 Interrupt Control Instructions Oe Function IME IPS 3 1 Sets the interrupt master enable flag bit 3 of the interrupt priority specification register to 1 to enable interrupts Whether to accept an interrupt is controlled with the corresponding interrupt enable flag EI IExxx Function 1 xxx Ns Noo Sets an interrupt enable flag IExxx to 1 to enable an interrupt xxx BT CSI TO T1 W 0 1 2 4 Oo Function IME IPS 3 0 Resets the interrupt master enable flag bit 3 of the interrupt priority specification register to O to disable all interrupts regardless of the states of the interrupt enable flags 293 uPD750008 USER S MANUAL C DI IExxx Function 0 xxx Ns Resets an interrupt enable flag IExxx to 0 to disable an interrupt xxx BT CSI TO T1 W 0 1 2 4 11 4 13 Instructions 7 INA PORTn Function lt P
201. match the contents of register pair XA HL DE BC XA HL DE BC 11 4 8 Carry Flag Manipulation Instructions C 2 SET1 CY Function CY lt 1 Sets the carry flag T CLR1 CY Function CY lt 0 Clears the carry flag C 2 SKT CY Function Skip if CY 1 Skips the immediately following instruction if the carry flag is set to 1 281 uPD750008 USER S MANUAL 2 Function CY CY Inverts the carry flag If it is O it is set to 1 or vice versa 11 4 9 Memory Bit Manipulation Instructions C 2 SET1 mem bit Function mem bit 1 mem Dz g OOH FFH bit 0 3 Sets the bit specified by the 2 bit immediate data bit at the address specified by the 8 bit immediate data mem Function Bit specified in operand lt 1 Sets the bit in data memory specified by bit manipulation addressing fmem bit 01 H mem bit CLR1 mem bit Function mem bit c 0 mem 05 0 OOH FFH bit 0 0 3 Clears the bit specified by the 2 bit immediate data bit at the address specified by the 8 bit immediate data mem C 2 CLR1 QH mem bit Function Bit specified in operand lt 0 Clears the bitin data memory specified by bit manipulation addressing fmem bit H mem bit SKT mem bit Function Skip if mem bit 1 mem D 7 9 OOH FFH bit 0 3 282 CHAPTER 11 INSTRUCTION SET Skips the immediately following instruction if the bi
202. memory space in units of four bits As with the 1 bit direct addressing mode in the MBE 0 mode a fixed space consisting of the static RAM area ranging from 000H to 07FH and the peripheral hardware area ranging from F80H to FFFH can be addressed In the MBE 1 mode MB MBS and specifiable data memory space can be expanded to the entire space This addressing mode can be applied to the MOV XCH INCS IN and OUT instructions Caution Less efficient program processing results if data associated with an I O port is stored in the static RAM area of bank 1 as in Example 1 The modification of the MBS as contained in Example 2 becomes unnecessary in the programming if data associated with an I O port is stored at addresses 00H to 7FH of bank O Examples 1 data contained in BUFF is output on port 5 BUFF EQU 11AH BUFF located at address 11AH SET1 MBE MBE 1 SEL 1 MBS lt 1 A BUFF A lt BUFF SEL MB15 MBS 15 OUT PORT5 A 5 lt 2 Data on port 4 is entered and is saved in DATA1 DATA1 EQU 5FH DATA located at address CLR1 MBE MBE lt 0 IN A PORTA A PORTA MOV DATA1 A 1 lt 8 bit direct addressing mem In this addressing mode the operand of an instruction directly specifies any area in the data memory space in units of eight bits The operand can specify an even address The 4 bit data at the address specified in the operand and the
203. mmand trigger bit W Control bit for command signal CMD trigger output By setting CMDT 1 the SO latch is cleared Then the CMDT bit is automatically cleared to 0 Caution Never clear SBO or SB1 during serial transfer Be sure to clear SBO or SB1 before or after serial transfer Bus release trigger bit W Control bit for bus release signal REL trigger output By setting RELT 1 the SO latch is set to 1 Then the RELT bit is automatically cleared to 0 Caution Never clear SBO or SB1 during serial transfer Be sure to clear SBO or SB1 before or after serial transfer Examples 1 A command signal is output SEL MB15 CLR1 MBE SET1 CMDT 2 RELD and CMDD are tested to identify the types of received data and the types of processing accordingly By setting WUP 1 this interrupt routine is processed only when an address match is found SEL MB15 SKF RELD RELD test BR IADRS SKT CMDD CMDD test BR IDATA BR ICMD Command analysis DATA Data processing Address decode 133 PD750008 USER S MANUAL 3 4 134 Shift register SIO Figure 5 42 shows the configuration of peripheral hardware of shift register SIO is an 8 bit register which performs parallel serial conversion and serial transfer shift operation in phase with the serial clock Serial transfer is started by writing data to SIO In transmission data written to SIO is output on th
204. mode 7 6 5 4 3 2 1 0 CSIE CSIM4 CSIM3 CSIM2 CSIMO CSIM pp Serial clock selection bit W Address FEOH Serial interface operation mode selection bit W Wake up function specification bit W Match signal from address comparator R Serial interface operation enable disable specification bit W Remark R Read only W Write only Serial interface operation enable disable specification bit W Shift register operation Serial clock counter clock counter IRQCSI ROCSI flag SO SBO SI SB1 pins and SI SB1 pins CSIE Shift operation enabled Count operation Can be set Used in each mode as well as for port O Signal from address comparator R CO Note Condition for being cleared COI 0 Condition for being set COI 1 When the slave address register SVA When the slave address register SVA does not match the data of the shift register matches the data of the shift register Note be read only before serial transfer is started or after serial transfer is completed An undefined value may be read during transfer COI data written by an 8 bit manipulation instruction is ignored Wake up function specification bit W WUP Sets IRQCSI each time serial transfer is completed 145 PD750008 USER S MANUAL Serial interface operation mode selection bit W CSIM4 CSIM3 CSIM2 Shift register sequence SO pin function SI pin function
205. more efficiently 238 CHAPTER 11 INSTRUCTION SET 11 1 4 Number System Conversion Instructions An application may need to convert the result of a 4 bit data addition or subtraction performed in binary to a decimal number A time related application may require sexagesimal conversion For this reason the instruction set of the uPD750008 contains number system conversion instructions for converting the result of a 4 bit data addition or subtraction to a number in an arbitrary number system a Number system conversion for addition b Let m desired number system after conversion The following combination of instructions adds the contents of an accumulator to data in memory HL then converts the result of the addition to number system m ADDS A 16 m ADDC A HL A CY A HL ADDS A m An overflow is set in the carry flag If the execution of the instruction ADDC A HL generates a carry the next instruction ADDS A n4 is skipped If no carry is generated ADDS A n4 is executed In this case the skip function of this instruction ADDS A n4 is disabled so that even if this addition generates a carry the instruction following this instruction is not skipped Accordingly programs can be written after ADDS A n4 Example An accumulator is added to memory data in decimal ADDS A 6 ADDC A HL A CY lt A HL CY ADDS A 10 Number system conversion for subtraction Let m be a desired n
206. ms anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircrafts aerospace equipment submersible repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC devices in Standard unless otherwise specified in NEC s Data Sheets or Data Books If customers intend to use NEC devices for applications other than those specified for Standard quality grade they should contact NEC Sales Representative in advance Anti radioactive design is not implemented in this product M7 94 11 Major Changes The 44 pin plastic QFP package has been changed from uPD750008GB xxx 3B4 to uPD750008GB xxx 3BS MTX The uPD75P0016 under development has been changed to the already developed uPD75P0016 The input withstand voltage at ports 4 and 5 during open drain has been changed from 12 V to 13 V Preface English version document numbers have been added to Related documents p 4 The format of the table in Section 1 3 has been changed p 45 The caution in using Mk II mode has been added in Section 4 1 1 p 85 The description for the mask option when using the feedback resistor has been added in 6 in Section 5 2 2 p 301 Appendix B Supported OS versions have been upgraded p 321 Appendix F has been added The mark shows major revised points Readers Purpose Configuration Guidance PREFACE This
207. n On the other hand a wait time can be selected by setting when releasing the STOP mode with an interrupt occurrence In this case the wait times are the same as the interval times shown in Figure 5 24 must be set before the STOP mode is set For details see Chapter 7 Example Set the wait time 5 46 ms at 6 00 MHz in releasing the STOP mode with an interrupt SET1 MBE SEL MB15 MOV A 1101B MOV BTM A Set wait time SIOP oet STOP mode NOP 103 PD750008 USER S MANUAL 2 104 Reading the count The count status of the basic interval timer BT can be read by using an 8 bit manipulation instruction No data can be loaded to the timer Caution When reading the count value of BT execute a read instruction twice so that unstable data which has been counted will not be read If the two read values are reasonable use the second one as the result If the two read values are far apart retry from the beginning Examples 1 Read the count value of BT SET1 SEL MOV MOV MOV MOV SKE BR LOOP MBE MB15 HL BT XA HL BC XA XA HL XA BC LOOP Set the BT address in HL First read Second read 2 Set the high level width of pulses applied to the INT4 interrupt pin both edges detected The pulse width is assumed not to exceed the value 5 46 ms or longer at 6 00 MHz set in the BTM lt 4 interrupt routine MBE 0 LOOP MOV MOV MOV SKE BR MOV SKE BR SKT
208. n undefined value may be read during transfer COI data written by an 8 bit manipulation instruction is ignored Wake up function specification bit W WUP 0 Sets IRQCSI each time serial transfer is completed Serial interface operation mode selection bit W CSIM2 Shift CSIM2 Shift register sequence sequence SO pin function SI pin function Me XA SO P02 SI P03 Transfer starting with Me CMOS output Input 5100 7 Transfer starting with LSB Remark x Don t care Serial clock selection bit W CSIM1 CSIMO Serial clock SCK pin mode External clock applied to SCK pin x qq Timer event counter output TOUTO Output Note fx 4 19 MHz 138 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS b Serial bus interface control register SBIC To use the three wire serial mode set SBIC as shown below For details on SBIC format see 2 in Section 5 6 3 SBIC is manipulated using a bit memory manipulation instruction When the RESET signal is input SBIC is set to OOH In the figure below hatched portions indicate the bits used in the three wire serial I O mode Address FE2H 7 6 5 4 3 2 1 0 BSYE ACKT CMDD RELD CMDT SBIC Do not use these bits in the three wire serial mode Bus release trigger bit W Command trigger bit W Remark W Write only Command trigger bit W Control
209. nal for details see Section 7 2 The following two wait times can be selected lt gt 2 fx 21 8 ms at fy 6 00 MHz 31 3 ms at fx 4 19 MHz 2 215 f 5 46 ms at fy 6 00 MHz 7 81 ms at fy 4 19 MHz uPD75P0016 does have mask option and its wait time is fixed to 2154 235 PD750008 USER S MANUAL 10 3 MASK OPTION FOR FEEDBACK RESISTOR OF SUBSYSTEM CLOCK For the subsystem clock of the uPD 750008 whether to enable the feedback resistor is selected by the mask option lt 1 gt Enable the feedback resistor switches on or off by software lt 2 gt Disable the feedback resistor cuts by hardware To use the feedback resistor after selecting lt 1 gt turn the feedback resistor by setting 505 0 to 0 for details see 6 in Section 5 2 2 Select 1 to use the subsystem clock For the uPD75P0016 the mask option need not be set use of the feedback resistor is factory set 236 CHAPTER 11 INSTRUCTION SET The instruction set of the uPD750008 is an improved and extended version of the 75X series instruction set This instruction set takes over the instruction set of the 75X series having the following features 1 2 3 4 5 6 7 8 Bit manipulation instructions allowing a wide variety of applications Efficient 4 bit manipulation instructions Eight bit instructions comparable to 8 bit microcomputers GETI instruction for reducing program sizes otring effect instructions
210. nals Setting Test Request Flags Test request flag Signals setting test request flags Test enable flag ROW M Detection of the rising edge of INT2 P12 input signal the first falling edge of the signals input to the KRO P60 to KR7 P73 pins The detection edge is selected with the INT2 edge detection mode register IM2 210 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 2 INT2 and key interrupt KRO to KR7 hardware Figure 6 10 shows the configuration of INT2 and KRO to KH7 The IRQ2 set signal is output in either of the following edge detection modes which is selected with the INT2 edge detection mode register IM2 a Detection of a rising edge on the INT2 input pin IRQ2 15 set when rising edge 15 detected on the INT2 input pin b Detection of a falling edge on any of the KRO to KR7 input pins key interrupt One of the pins KRO to is selected to be used for interrupt input with the INT2 edge detection mode register IM2 When a falling edge of one of input signals applied to the selected pin is detected IRQ2 is set Figure 6 11 shows the format of IM2 IM2 is set using a 4 bit manipulation instruction When the RESET signal is generated all bits are cleared to 0 and the rising edge on INT2 is specified 211 uPD750008 USER S MANUAL snq ZNI Nf AAAA indul lt lt 9 lt lt L9d
211. nce state so that a transistor must connected as shown in the figure to make open collector output appear on the pin When data 15 input OOH must be set beforehand in the shift register to set the transistor off The timing of data output by each microcomputer must be predetermined 149 PD750008 USER S MANUAL The uPD750008 which is the master microcomputer outputs serial clock and all slave microcomputers operate with an external clock 5 6 7 SBI Mode Operation The SBI serial bus interface is a high speed serial interface that conforms to the NEC serial bus format Toallow communication with multiple devices on a single master and high speed serial bus using two signal lines the SBI has a bus configuration function added to the clock synchronous serial I O method So the SBI can reduce ports and wires on boards when multiple microcomputers and peripheral ICs are used to configure a serial bus The master can output on the serial data bus an address for selecting a device subject to serial communication commands directed to the remote device and data A slave can identify an address commands and data from received data by hardware This function simplifies the serial interface control portion of an application program The SBI function is available with devices such as the 75X series 75XL series and 78K series 8 16 bit single chip microcomputers Figure 5 50 is an example of the SBI system configuration when the CPU wi
212. ned by an instruction other than the TBR or TCALL instruction is referenced An instruction using taddr taddr 1 as its operation code is executed Mk Il mode When a table defined by the TBR instruction is referenced PC12 9 lt taddr 4 9 taddr 1 When a table defined by the TCALL instruction is referenced 2 lt x x MBE RBE SP 3 lt PC7 4 SP 4 lt PC3 9 SP 5 lt 0 0 0 SP 6 lt PC12 9 lt taddr 4 9 taddr 1 SP SP 6 When a table defined by an instruction other than the TBR or TCALL instruction is referenced An instruction using taddr taddr 1 as its operation code is executed Remark Function in this section is applicable to the uPD750008 whose program counter consists of 13 bits addr OOOOH to 1FFFH However this is also applicable to the uPD750004 whose program counter consists of 12 bits addr OOOOH to OFFFH the PD750006 whose program counter consists of 13 bits addr OOOOH to 17FFH and the uPD75P0016 whose program counter consists of 14 bits addr OOOOH to 3FFFH The 2 byte data at the program memory addresses specified by taddr and taddr 1 is referenced and executed as an instruction Addresses 0020H to 007FH are used as a reference table area Data must be written to this area beforehand When a 1 byte instruction or 2 byte instruction is written its mnemonic can be used directly For a 3 byte call instruction or 3 byte branch instruction
213. ng the content of these flags the interrupt priority control circuit controls multiple interrupts as indicated in Table 6 3 A 4 bit manipulation instruction or bit manipulation instruction can be used to set and reset ISTO and 1511 so that multiple interrupts are enabled by changing the current status of execution ISTO and IST1 can be manipulated on a single bit basis at any time regardless of MBE setting Before ISTO or IST1 is manipulated the DI instruction must be executed to disable interrupts then the El instruction must be executed to enable interrupts IST1 and ISTO as well as the other PSW bits are saved in the stack memory when an interrupt is accepted and the status of ISTO and IST1 changes to a status one level higher When a RETI instruction is executed the former values of IST1 and ISTO are resumed Inputting a RESET signal clears the content of the flag to O Table 6 3 Interrupt Processing Statuses of ISTO and IST1 p i Interrupts that After acceptance isT1 8 CPU operation ii status can be accepted IST1 ISTO Status 0 Is processing the normal program ___ 1 1 Status 1 Is processing a low or high order Only high order 0 interrupt interrupts Status 2 Is processing a high order interrupt No Not to be set 194 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 6 4 INTERRUPT SEQUENCE When an interrupt occurs it is processed using the procedure shown in Figure 6 7 Figure 6 7 Interru
214. nput INT2 External event pulse input TIO for timer event counter Input is always enabled for each pin of ports 0 and 1 regardless of the operation status of the other function of the pin Schmitt triggered inputs are used for the input pin of port 0 and pins of port 1 to prevent malfunction due to noise In addition a noise eliminator is provided for P10 See 3 of Section 6 3 Port 0 can be connected with built in pull up resistors in units of 3 bits PO1 to by software Port 1 can be connected with built in pull up resistors in units of 4 bits P10 to P13 by software This is done by manipulating pull up resistor specification register group A POGA A RESET signal input places these pins in the input port mode 12 CHAPTER 2 PIN FUNCTIONS 2 2 2 20 23 PORT2 1 0 Pins Used Also for PTOO PTO1 PCL BUZ P30 P33 I O Pins Used Also for MDO MD3Note P40 P43 PORT4 P50 P53 PORT5 N ch Open Drain Intermediate Withstand Voltage 13 V Large Current Output P60 P63 PORT6 P70 P73 PORT7 Tristate I O These pins are the I O pins of the 4 bit I O ports with output latches Ports 2 to 7 Port n 2 6 and 7 functions as I O ports and also have the following functions 1 Port 2 Timer event counter PTOO PTO1 Clock output PCL Fixed frequency output BUZ 2 Port 3 Mode selection for program memory PROM write verify operation MDO MD3 Note 3 Ports 6 and 7 Key interrupt
215. nstruction is followed by the ADDS A n4 instruction the ADDS A n4 instruction is skipped If a borrow is generated the ADDS A n4 instruction is executed and the skip function of the ADDS A 14 instruction is disabled Accordingly a combination of these instructions can be used for number system conversion See Section 11 1 C 2 SUBC XA rp Function XA CY lt XA rp CY Subtracts the contents of register pair ro XA HL DE BC XA HL DE BC together with the carry flag from the contents of the XA register pair then sets the result in the XA register pair If the subtraction generates a borrow the carry flag is set If no borrow is generated the carry flag is reset C 2 SUBC rp 1 XA Function rp 1 CY rp 1 XA CY Subtracts the contents of the XA register pair together with the carry flag from the contents of register pair rp1 HL DE BC XA HL DE BC then sets the result in register pair rp 1 If the subtraction generates a borrow the carry flag is set If no borrow is generated the carry flag is reset C 2 AND A n4 Function A A n4 n4 13 0 ANDs the contents of the A register with the 4 bit immediate data n4 then sets the result in the A register Example The high order two bits of an accumulator are set to O AND A 0011B 276 CHAPTER 11 INSTRUCTION SET C 2 AND A GHL Function A A HL ANDs the contents of the A register with the data at the data m
216. nter consists of 13 bits addr OOOOH to 17FFH and the uPD75P0016 whose program counter consists of 14 bits addr 0000H to 3FFFH 288 CHAPTER 11 INSTRUCTION SET 11 4 11 Subroutine Stack Control Instructions Cu CALLA addr1 Function For the PD750008 5 2 lt x x MBE SP 3 lt 5 4 lt 5 5 0 0 0 12 SP 6 lt 11 8 12 0 addr1 SP SP 6 CALL addr Function For the 750008 Mk mode 5 1 lt 7 4 SP 2 lt PC3 9 5 3 lt MBE RBE 0 PC42 5 4 lt PC44 8 2 0 lt addr SP lt SP 4 addr 0000H 1FFFH Mk mode SP 2 lt x x MBE RBE 5 3 PC7 4 SP 4 lt PC3 0 5 5 lt 0 0 0 PC42 SP 6 lt 118 12 0 lt addr SP lt SP 6 addr 0000H 1FFFH Saves the contents of the program counter return address memory bank enable flag MBE and register bank enable flag RBE to the data memory location stack addressed by the stack pointer SP then branches to the location addressed by the 14 bit immediate data addr after decrementing SP Remark Function in this section is applicable to the uPD750008 whose program counter consists 13 bits addr OOOOH to 1FFFH However this is also applicable to the uPD750004 whose program counter consists of 12 bits addr OOOOH to OFFFH the uPD750006 whose program counter consists of
217. o specify the address information generation mode for the high order four bits of a 12 bit data memory address The MBE can be set or reset any time with a bit manipulation instruction regardless of memory bank setting When the MBE is set to 1 the data memory address space is expanded allowing all data memory space to be addressed When the MBE is reset to 0 the data memory address space is fixed regardless of MBS setting See Figure 3 2 A RESET signal automatically initializes the MBE by setting the MBE to the content of bit 7 at program memory address O In vectored interrupt processing the MBE is automatically set to the content of bit 7 in the vector address table for servicing the interrupt Usually the MBE is set 0 in interrupt processing and static RAM in memory bank 0 is used 5 Register bank enable flag RBE The register bank enable flag is a 1 bit flag used to determine whether to expand the general register bank configuration The RBE can be set or reset any time with a bit manipulation instruction regardless of memory bank setting When the RBE is set to 1 a set of general registers can be selected from register banks 0 to 3 depending on the setting of the register bank select register RBS 64 CHAPTER 4 INTERNAL CPU FUNCTIONS When the RBE is reset to 0 register bank 0 is always selected as general registers regardless of the setting of the RBS A RESET signal automatically initializes the RBE by setting t
218. o the uPD750004 whose program counter consists of 12 bits addr OOOOH to OFFFH the PD750006 whose program counter consists of 13 bits addr OOOOH to 17FFH and the uPD75P0016 whose program counter consists of 14 bits addr OOOOH to 3FFFH 290 CHAPTER 11 INSTRUCTION SET Cn RET Function For the PD750008 Mk mode 11 8 lt SP MBE RBE 0 PCy SP 1 PC3 9 lt SP 2 PCz 4 lt SP 3 SP SP 4 Mk mode 11 8 lt SP X X X 12 lt SP 1 PC3 9 lt SP 2 PCz 4 SP 3 x X MBE RBE SP 4 SP SP 6 Restores the program counter PC memory bank enable flag MBE and register bank enable flag RBE with the data at the data memory location stack addressed by the stack pointer SP then increments the contents of SP Caution The program status word PSW is not restored except MBE and RBE Remark Function in this section is applicable to the uPD750008 whose program counter consists 13 bits addr OOOOH to 1FFFH However this is also applicable to the uPD750004 whose program counter consists of 12 bits addr OOOOH to OFFFH the uPD750006 whose program counter consists of 13 bits addr 2 0000H to 17FFH and the uPD75P0016 whose program counter consists of 14 bits addr OOOOH to 3FFFH 5 Function For the PD750008 Mk mode PC41 g lt SP MBE 0 0 PC lt SP 1 PC3 9 lt SP 2 PCz 4 SP 3 SP lt SP 4 Th
219. o wire serial mode transfers data with eight bits as one block Data is transferred bit by bit in phase with the serial clock The shift register performs shift operation on the falling edge of the serial clock 5 Transmit data is latched on the SO latch and is output on the SBO PO2 pin or SB1 P03 pin starting with the MSB Receive data applied to the SBO pin or SB1 pin is latched in the shift register on the rising edge of SCK When eight bits have been transferred shift register operation automatically terminates setting the interrupt request flag IRQCSI Figure 5 48 Timing of Two Wire Serial I O Mode SCK SBO SB1 IRQCSI A Completion of transfer Transfer operation is started in phase with falling edge of SCK Execution of instruction that writes date to SIO Transfer start request The SBO or SB1 pin becomes an N ch open drain I O when specified as the serial data bus so the voltage level on that pin must be pulled up externally The state of the SO latch is output on the SBO or SB1 pin so the SBO or SB1 pin output states can be controlled by setting the RELT or CMDT bit However this operation must not be performed during serial transfer The output state of the SCK can be controlled by manipulating the output latch in the output mode internal system clock mode See Section 5 6 8 147 PD750008 USER S MANUAL 3 Serial clock selection To select the serial clock manipul
220. ock control register One clock cycle tcy of the CPU clock is equal to one machine cycle of an instruction Figure 5 11 Block Diagram of the Clock Generator Basic interval timer BT Timer event counter Timer counter Serial interface Clock timer INTO noise eliminator Clock output circuit Frequency divider CPU INTO noise eliminator Clock output circuit Wait release signal from BT o RESET signal Standby release signal from interrupt control circuit CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5 2 2 Functions and Operations of the Clock Generator The clock generator generates the following clocks and controls the CPU operation modes such as the standby mode e Main system clock fy e Subsystem clock CPU clock Clock to peripheral hardware The operation of the clock generator is determined by the processor clock control register PCC and system clock control register SCC The function and operation of the clock generator are described in a to g below a b c d A RESET signal selects the lowest speed mode 10 7 us at 6 00 MHz Note 1 for the main system clock PCC 0 SCC 0 When the main system clock is selected the PCC can be set to select one of four CPU clocks 0 67 us 1 33 us 2 67 us and 10 7 us at 6 00 MHz Note 2 When the main system clock is selected the two standby modes STOP mode and HALT mode are available The SCC
221. on instruction and in bit units using a bit manipulation instruction Note that an even address must be specified in an 8 bit manipulation instruction Note Memory bank 0 or 1 can be selected as the stack area General register area The general register area can be manipulated with either general register manipulation instructions or memory manipulation instructions Up to eight 4 bit registers are available Of the 8 general registers registers not used by the program can be used as a data area or stack area See Section 4 5 Stack memory area The stack memory area is set by the instruction This area can be used as a save area for subroutine or interrupt execution See Section 4 7 2 Peripheral hardware area The peripheral hardware area is mapped at addresses F80H to FFFH of memory bank 15 Memory manipulation instructions are used to manipulate the peripheral hardware area as well as the static RAM area Note that however the number of bits to be manipulated at a time varies according to the individual addresses Addresses to which no peripheral hardware is assigned cannot be accessed since such address locations contain no data memory See Figure 3 7 53 PD750008 USER S MANUAL 4 4 2 Specification of a Data Memory Bank If the memory bank enable flag MBE enables bank specification MBE 1 a memory bank is specified with the 4 bit memory bank select register MBS 0 1 15 If the MBE disables bank specification
222. on the left side Lower order bits on the right side xxx Pin and signal names are overscored Low order address on the upper side High order address on the lower side Explanation of an indicated part of text Information requesting the user s special attention eupplementary information Described in bold face gt XXXX or xxxxB Related documents Some documents are preliminary editions but they are not so specified in the tables below Documents related to devices Document Number uPD750004 750006 750008 Data Sheet U10738J 3647 Document uPO750008 msrucion ts _ 75XL Series Selection Guide U10453E Documents related to development tools Document Number Document Name Software RA75X Assembler Package User s Series PC DOS Base Other documents Document Number Package Manual IEI 635 IEI 1213 Semiconductor Device Mounting Technology Manual IEI 616 IEI 1207 Document Name Quality Grade on NEC Semiconductor Devices Reliability and Quality Control of NEC Semiconductor Devices Electrostatic Discharge ESD Test MEM539 Semiconductor Device Quality Guarantee Guide DC Microcontroller Related Products Guide by third parties MEI 604 Caution The above related documents are subject to change without notice Be sure to use the latest edition when you design your system MEMO CONTENTS
223. or CLR1 MBE SET1 WDTM SET1 BTM 3 oet bit 3 of BTM to 1 The generation of a RESET signal clears WDTM to O Figure 5 25 Format of the Watchdog Timer Enable Flag WDTM Address F8BH 3 WDTM BT mode Sets IRQBT when the basic interval timer BT overflows WT mode Generates an internal reset signal when the basic interval timer BT overflows 5 3 4 Operation of the Basic Interval Timer When WDTM is set to O the basic interval timer BT functions as an interval timer An interrupt request flag IRQBT is set when the timer overflows BT is constantly incremented by the clock supplied from the clock generator So it is impossible to stop the timer from incrementing One of four interrupt generation intervals can be selected by setting BTM See Figure 5 24 BT and IRQBT can be cleared by setting bit 3 of BTM to 1 instruction for starting as an interval timer The count status of BT can be read by an 8 bit manipulation instruction No data can be loaded to the timer Perform the timer operation as follows lt 1 gt and 2 can be performed with the same instruction 1 Set the interval in BTM 2 Set 1 in bit 3 of BTM Example Generate an interrupt at intervals of 1 37 ms at 6 00 MHz SET1 MBE SEL MB15 MOV A 1111B MOV oet the interval and start processing El Enable interrupt El IEBT Enable BT interrupt 101 PD750008 USER S MANUAL 5 3 5 Operation of the Watchdog Timer When WDTM
224. order interrupt specified by the interrupt priority specification register IPS is enabled when the processing status is O or 1 Other interrupts interrupts lower than the specified high order interrupt are enabled only when the status is 0 See Figure 6 8 and Table 6 3 When only one interrupt is used as a level two interrupt using this method saves the user the trouble of enabling or disabling interrupts during an interrupt processing and holds down the number of nesting levels to two Figure 6 8 Multiple Interrupt Processing by a High Order Interrupt Normal Low or high order High order processing interrupt processing interrupt Status 0 Status 1 processing Status 2 Interrupt is disabled IPS setting Interrupt is enabled High order interrupt Low or high order occurrence Interrupt occurrence CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 2 Multiple interrupt processing by changing the interrupt status flags Changing the interrupt status flags with the program causes multiple interrupts to be enabled That is when the interrupt processing program changes both IST1 and ISTO to 0 status 0 multiple interrupt processing is enabled This method is used when two or more interrupts are to be enabled at a time or when the processing of three or more interrupts is to be performed When changing IST1 and ISTO interrupts must be disabled beforehand with a DI instruction Figure 6 9 Multiple Interrupt P
225. ority and give priority to INT4 SKTCLR IRQ4 IRQ4 1 VSUBBT Processing routine of INT4 RETI VSUBBT CLR1 IRQBT Processing routine of INTBT RETI 199 uPD750008 USER S MANUAL 6 7 MACHINE CYCLES FOR STARTING INTERRUPT PROCESSING With the uPD750008 series the following machine cycles are used to start the execution of the interrupt service routine after an interrupt request flag IRQn is set 1 When IRQn is set during execution of an interrupt control instruction When IRQn is set during execution of an interrupt control instruction an instruction preceded by that instruction is executed and an interrupt processing of three machine cycles is executed then the interrupt service routine is started Interrupt control instruction A IRQn is set B The next instruction is executed 1 to 3 machine cycles according to the instruction C Interrupt processing 8 machine cycles D Interrupt service routine is executed Remarks 1 Cautions 1 200 An interrupt control instruction manipulates hardware address FBxH in data memory which handles interrupt processings There are two types of interrupt control instruction a DI instruction and an instruction Three machine cycles required for the interrupt processing include the time to manipulate the stack when an interrupt is accepted When interrupt control instructions are contiguous these interrupt control instructions are execut
226. ormal MBE 0 Start main system clock oscillation Wait 250 ms Chattering check Switch to main system clock Switch to subsystem clock Wait for 32 machine cycles Stop main system clock oscillation Caution Before the system clock is changed from the main system clock to the subsystem clock a wait time sufficient for stable subsystem clock generation is required 223 PD750008 USER S MANUAL MEMO 224 CHAPTER 8 RESET FUNCTION The uPD750008 is reset with the external reset signal RESET or the reset signal received from the basic interval timer watchdog timer When either reset signal is input the internal reset signal is generated Figure 8 1 shows the configuration of the reset circuit Figure 8 1 Configuration of Reset Functions RESET O gt m Internal reset signal Reset signal from basic interval timer watchdog timer WDTM Internal bus When the RESET signal is generated all hardware is initialized as indicated in Table 8 1 Figure 8 2 shows the reset operation timing Figure 8 2 Reset Operation by Generation of RESET Signal Wait Note RESET signal is generated Operating mode or standby mode HALT mode Operating mode gt lt gt gt lt Internal reset operation Note The following two wait times can be selected by a mask option 217 f 21 8 ms at 6 00 MHz 31 3 ms at 4 19 MHz 215 fy 5 46 ms at 6 00
227. pair function as accumulators The A register is mainly used for 4 bit data processing instructions and the XA register pair is mainly used for 8 bit data processing instructions For a bit manipulation instruction the carry flag CY functions as a bit accumulator Figure 4 10 Accumulator Bit accumulator 8 bit accumulator 57 PD750008 USER S MANUAL 4 7 STACK POINTER SP AND STACK BANK SELECT REGISTER SBS The 0750008 uses static RAM as stack memory LIFO scheme and the 8 bit register holding the start address of the stack area is the stack pointer SP The stack area is located at addresses to 1FFH in memory banks 0 and 1 One memory bank is selected according to the value of the 2 bit SBS See Table 4 2 Table 4 2 Stack Area to Be Selected by the SBS Stack area Memory bank 0 Memory bank 1 Other than above Not to be set The SP is decremented before a write Save operation to stack memory and is incremented after a read restoration operation from stack memory Figures 4 12 to 4 15 show data saved to and restored from stack memory in these stack operations To place the stack area at a given location the SP can be initialized with an 8 bit memory manipulation instruction and the SBS can be initialized with a 4 bit memory manipulation instruction Both can be read from as well When the SP is initialized to OOH a stack operation starts at the high order address nFFH of memory bank n
228. pt Sequence Interrupt INTxxx occurrence IRQxxx setting No gt Hold until IExxx is set Yes Corresponding VRQn occurrence No Hold until IME is set Yes Is Hold until process ing being executed VRQn high order PO is finished interrupt Yes Note 1 NO Note 1 IST1 0 00 or 01 IST1 0 00 Yes If two or more VRQns occur select one VRQn according to Table 6 1 Selected VRQn Note 2 Remaining VRQns Save contents of PC and PSW in stack memory and set data in vector table corresponding to activated VRQn to PC RBE and MBE Change contents of ISTO and IST1 from 00 to 01 or from 01 to 10 Reset accepted IRQxxx E Section 6 6 when those Ad sources share vector address Jump to the start address for processing the interrupt service program Notes 1 ISTO and IST1 are the interrupt status flags bits and 2 of the PSW See Table 6 3 2 An interrupt service program start address and MBE and RBE setting values at the start of interrupt are stored in each vector table 195 uPD750008 USER S MANUAL 6 5 MULTIPLE INTERRUPT PROCESSING CONTROL The 0750008 can handle multiple interrupts by either of the following methods 1 196 Multiple interrupt processing by a high order interrupt In this method the uPD750008 selects an interrupt source among multiple interrupt sources enabling double interrupt processing That is the high
229. ptNete 0 A Input buffer E M X PMm 1 di Input buffer with hysteresisNote o 2 Q 5 gt 2 gt latch ea 4 OPm2 e OPm3 Output buffer x Bits 2 and 7 of port mode register group B m 2 7 Note For port 7 only 70 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 4 Configurations of Ports 3n and 6n n 0 to 3 Key interruptNete Input buffer with hysteresisNete Input buffer Pull up 1 resistor P ch o 2 2 E Pmn Corresponding bits of m 3 6 port mode register group A 0103 Note For port 6n only T1 PD750008 USER S MANUAL 72 Internal bus Figure 5 5 Configurations of Ports 4 and 5 Pull up resistor 5 5 Input buffer Mask option 0 PMm 1 N N NZN O PmO Pm1 O Pm2 O Pm3 N ch open drain output buffer PMm Corresponding bits of port mode register group B m 4 5 o 2 c CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 6 Configuration of Port 8 Pull up resistor ap Input buffer 0 Ouput latch gt P81 PM8 1 Output buffer O P80 PM8 Corresponding bit of port mode register group C 73 PD750008 USER S MANUAL 5 1 2 I O Mode Setting The I O mode of each I
230. pull up resistor by mask option and are always open 81 PD750008 USER S MANUAL Figure 5 8 Pull Up Resistor Specification Register Format Specification contents Built in pull up resistor not connected Built in pull up resistor connected Pull up resistor specification register group A Address Symbol 7 6 5 4 3 2 1 0 pos Poo FDCH POGA Port 0 P01 Port 1 P10 P13 LL Bort 2 P20 P23 Port 3 P30 P33 Port 6 P60 P63 Port 7 P70 P73 Pull up resistor specification register group B Address 7 6 Symbol 5 4 3 2 1 0 em oe Poe Port 8 P80 P81 5 1 6 Timing of Digital I O Ports Figure 5 9 shows the timing of data output to an output latch and the timing of taking in pin data or output latch data on the internal bus Figure 5 10 shows an ON timing chart when a built in pull up resistor is connected to a port pin by software Figure 5 9 I O Timing Chart of Digital I O Ports 1 2 a When data is input by a 1 machine cycle instruction 1 machine cycle Instruction TE Manipulation instruction execution Input timing lt gt 82 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 9 I O Timing Chart of Digital I O Ports 2 2 b When data is input by a 2 machine cycle instruction 2 machine cycles Instr
231. r bit manipulation is performed 2 KRO to KR7 can be read R bit by bit When inputting 4 bits at a time specify PORT6 or PORT7 CHAPTER 4 INTERNAL CPU FUNCTIONS 4 1 Mk I MODE Mk MODE SWITCH FUNCTIONS 4 1 1 Differences between Mk I Mode and Mk II Mode The CPU of the uPD750008 subseries has two modes Mk mode and Mk II mode and which mode is used is selectable Bit 3 of the stack bank selection register SBS determines the mode e Mk I mode This mode has the upward compatibility with the uPD75008 subseries It can be used in the 75XL CPUs having a ROM of up to 16KB e Mk Il mode This mode is not compatible with the uPD75008 subseries It can be used in all 75XL CPUS including those having a ROM of 16KB or more Table 4 1 shows the differences between Mk mode and Mk II mode Table 4 1 Differences between Mk Mode and Mk II Mode Number of stack bytes in a subroutine instruction 2 9 3byes 000000 BRA addr1 instruction Undefined operation Normal operation CALLA addr1 instruction CALL addr instruction 3 machine cycles 4 machine cycles faddr instruction 2 machine cycles 3 machine cycles Caution Il mode is for maintaining a software compatibility with products in the 75X series or 75XL series whose program memory is more than 24K bytes Therefore Mk mode is recommended for applications with a focus on the ROM efficiency or speed 45 PD750008 USER S MANUAL 4 1 2 Setting of the S
232. r subroutine processing or interrupt processing by saving or restoring the MBS with the PUSH or POP instruction The MBE is set using the SET1 or CLR1 instruction The MBS is set using the SEL instruction Examples 1 The MBE is cleared and a fixed memory bank is used CLR1 MBE MBE 0 2 Memory bank 1 is selected SET1 MBE MBE lt 1 SEL MB1 MBS lt 1 22 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP 3 1 2 Data Memory Addressing Modes With the architecture of the uPD750008 seven addressing modes summarized in Figures 3 2 and 3 3 Table 3 1 are available to address data memory space efficiently for each bit length of data to be processed These addressing modes enable more efficient programming 1 1 bit direct addressing mem bit In this addressing mode the operand of an instruction can directly specify any bit in the entire data memory space A particular memory bank MB is always used in this addressing mode In the MBE 0 mode when an address from OOH to 7FH is specified in the operand memory bank 0 MB 0 is always used When an address from 80H to FFH is specified memory bank 15 MB 15 is always used Accordingly both the data area ranging from OOOH to and the peripheral hardware area ranging from F80H to FFFH can be addressed in the MBE 0 mode In the MBE 1 mode MB MBS and specifiable data memory space can be expanded This addressing mode can be applied to four instructions
233. ranch to address XABC 33 PD750008 USER S MANUAL 3 2 GENERAL REGISTER BANK CONFIGURATION The uPD750008 contains four register banks each consisting of eight general registers X A B C D and L These registers are mapped to addresses OOH to 1FH in memory bank 0 of the data memory see Figure 3 5 To specify a general register bank a register bank enable flag RBE and a register bank select register RBS are contained The RBS is a register used to select a register bank and the RBE is a flag used to determine whether a register bank selected using the RBS is to be enabled The register bank RB enabled at instruction execution is determined as RBE RBS Table 3 2 Register Bank to Be Selected with the RBE and RBS ERNENLTUIT HN __ Lt Always 0 Remark x Don t care The contents of the RBE are automatically saved or restored at the beginning or end of subroutine processing so that the RBE can be freely modified during subroutine processing In interrupt processing the RBE is automatically saved or restored and when interrupt processing is started the contents of the RBE can be specified for the interrupt processing by setting the interrupt vector table Therefore as indicated in Table 3 3 by selecting a register bank depending on whether the processing is normal or interrupt the general register need not be saved and restored for the level one interrupt processing
234. ree types Address command and data b Address based chip select function The master selects a chip for a slave by address transfer c Wake up function A slave can easily check address reception for chip select identification with the wake up function This function can be set or released by software When the wake up function is set an interrupt IRQCSI is generated when a match address is received For this reason in communication with multiple devices a CPU other than a selected slave can operate independently of serial communication d Acknowledge signal ACK control function The acknowledge signal which is used to confirm the reception of serial data can be controlled e Busy signal BUSY control function The busy signal which is used to post the busy state of a slave can be controlled 151 PD750008 USER S MANUAL 2 SBI definition The format of serial data and signal used in the SBI mode are described below Serial data to be transferred in the SBI mode is classified into three types Address command and data Serial data forms one frame as shown below Figure 5 51 is a timing chart for transferring address command and data Figure 5 51 Timing of SBI Transfer Address transfer SCK LI LILI LILLIE LI le lel LE LE LI LIL SBO 581 Bus release signal Command transfer Command signal SCK LI LILI LELELELELIE de UUL SBO 581 Data transfer SCK LI LILI LILI LI lel LE LIE UI LI SBO
235. register matches the data of the shift register Note can be read only before serial transfer is started or after serial transfer is completed An undefined value may be read during transfer COI data written by an 8 bit manipulation instruction is ignored Wake up function specification bit W Sets IRQCSI each time serial transfer is completed in each mode Used in the SBI mode only to set IRQCSI only when an address received after bus release matches the data in the slave address register wake up state SBO or SB1 goes to high impedance state Caution When WUP 1 is set during BUSY signal output BUSY is not released In the SBI mode the BUSY signal is output until the next falling edge of the serial clock SCK appears after release of BUSY is directed Before setting WUP 1 be sure to confirm that the SBO or 581 pin is high after releasing BUSY Serial interface operation mode selection bit W CSIM4 CSIM3 CSIM2 Shift register sequence SO pin function SI pin function 3107 XA SBO PO02 N ch input Transfer starting with MSB uae I O 02 input SB1 P03 N ch open drain 157 PD750008 USER S MANUAL Serial clock selection bit W CSIM1 CSIMO Serial clock SCK pin mode 779 Extemat clock applied to SCK pin Timer event counter output TOUTO Output Remark The value at 4 19 MHz is indicated in parentheses b Serial bus interface control register
236. remented by one in the automatic increment or automatic decrement mode each time an instruction is executed thus simplifying the program step Example The data at 50H to 57H is transferred to 110H to 117H DATA1 EQU 57H DATA2 EQU 117H MBE MBE lt 1 SEL X MB MBS lt 1 MOV _ D DATA1 SHR4 D 5 MOV HL ZDATA2 AND _ HL lt 17H LOOP MOV A DL A DL A QHL lt gt HL L lt L 1 BR LOOP The addressing mode using the HL register pair as the data pointer finds a wide range of operations such as data transfer operations comparison and I O The addressing mode using the DE register pair or DL register pair is applied to the MOV and XCH instructions This addressing mode combined with an increment decrement instruction for a general register or register pair enables data memory space addresses to be freely updated as shown in Figure 3 3 Example 1 The data at 50H to 57H is compared with the data at 110H to 117H DATA1 EQU 57H DATA2 EQU 117H SET1 MBE SEL MB1 MOV D DATA1 SHR4 MOV HL DATA2 AND OFFH LOOP MOV A DL SKE A HL A HL BR NO NO DECS YES L lt L 1 BR LOOP 27 PD750008 USER S MANUAL 28 Example 2 The data memory of OOH to FFH is cleared to 0 CLR1 CLR1 MOV MOV LOOP MOV INCS BR RBE MBE XA 00H HL 04H QHL A HL A HL HL lt HL 1 LOOP Figure 3 3 Updating Static RAM Addresses DL 4 bit transfer
237. riority and INTTO with the lower priority occur at the same time the processing of the interrupt with the higher priority is started if there is no possibility that an interrupt with the higher priority occurs while another interrupt with the higher priority is processed DI IExx is not necessary 2 When an interrupt with the lower priority occurs while the interrupt with the higher priority is executed the interrupt with the lower priority is kept pending 3 When the interrupt with the higher priority has been processed INTCSI with the higher priority of the pending interrupts is executed 4 When the processing of INTCSI has been completed the pending INTTO is processed CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 7 Enabling of level two interrupts enabling level two INTTO and INTO interrupts with INTCSI and INTA handled as level one interrupts c1 c2 c3 lt 4 gt lt 5 gt EI EI EI EI EI Main program Reset IETO IEO IECSI IE4 lt 1 gt INTCSI Status 0 lt INTCSI service program gt A lt 2 gt DI Status 1 CLR1 ISTO DI IECSI DI 4 Status 0 EI INTTO service program Status 0 3 0 2 _ Status 1 4 Status 0 lt 5 gt IECSI El 4 RETI When an INTCSI interrupt not allowed to be level two interrupt occurs the INTCSI service program starts and status 1 is set Status 0 is set b
238. rive current of the built in inverter See Figure 5 18 Inputting a RESET signal clears all bits of the SOS register The functions of each flag in the SOS register are described below a SOS 0 feedback resistor cut flag To use the feedback resistor of the subsystem clock the mask option setup and switching SOS 0 by software are required Set 505 0 to 0 to turn on the feedback circuit When the resonator is not used set SOS 0 to 1 The feedback circuit is turned off reducing the current drain To use the resonator be sure to select Enable the feedback resistor upon setting the mask option Then set 505 0 to 0 feedback circuit is turned on b SOS 1 drive capability switch flag The built in inverter in the subsystem clock oscillator of the uPD750008 subseries has a large drive current because it can be used at low supply voltage Vpp 1 8 V so that the supply current becomes too high to use at high supply voltage Vpp 2 7 V To reduce the supply current set SOS 1 to 1 so as to reduce the drive current of the inverter However if SOS 1 is set to 1 when Vpp is less than 2 7 V the oscillation may stop for insufficient drive current Set this flag to O when Vpp is less than 2 7 V Figure 5 18 Sub Oscillator Control Register SOS Format Address Symbol 3 2 1 0 sost soso sos Ex Cut flag for feedback resistor of the sub oscillator ET Built in feedback resistor is used Built in feedback r
239. rminated The HALT mode can be used for either the main system clock or the subsystem clock 2 Ifthe STOP mode is set when main system clock fy is used for clock timer operation the clock stops operating For continued operation the clock must be changed to subsystem clock fxr before the STOP mode is set 3 A lower power consumption and lower voltage operation are enabled by switching standby modes or switching CPU and system clocks However a switching time as described in Section 5 2 3 is required before operation is started with a new clock after the clock is selected with the control register For this reason when the clock switching function is used together with a standby mode the standby mode must be set after a time needed for switching elapses 4 Configure I O ports for minimum power consumption in the stand by mode Be sure to connect signals which are high or low to input ports 215 PD750008 USER S MANUAL 71 SETTING OF STANDBY MODES AND OPERATION STATUS Table 7 1 Operation Statuses in the Standby Mode STOP mode HALT mode Instruction for setting STOP instruction HALT instruction System clock for setting Can be set only when operating on Can be set either with the main the main system clock system clock or the subsystem clock Operation Clock oscillator Only the main system clock stops its Only the CPU clock F stops its status operation operation oscillation continues Basic interval Does no
240. rocessing by Changing the Interrupt Status Flags Normal processing Single interrupt Dual interrupts status 0 Interrupt is disabled IPS setting Status 1 Interrupt is enabled ee Modification of IST Low or high order Interrupt is Interrupt occurrence enabled Status 0 Status 1 Low or high order interrupt occurrence Status 0 197 uPD750008 USER S MANUAL 6 6 PROCESSING OF INTERRUPTS SHARING A VECTOR ADDRESS Interrupt sources INTBT and INT4 share a vector table so an interrupt source is selected as described below 1 Using only one interrupt The interrupt enable flag for desired one of the two interrupt sources sharing a vector table is set to 1 and the interrupt enable flag for the other is cleared to 0 In this case the enabled IExxx 1 interrupt source causes an interrupt request When the interrupt request is accepted the interrupt request flag is reset 2 Using both interrupts The interrupt enable flags corresponding to the two interrupt sources are both set to 1 In this case the logical sum of the interrupt request flags for the two interrupt sources is used as an interrupt request In this case even if an interrupt request or interrupt requests caused by the setting of one or both of the interrupt request flags are accepted the interrupt request flag or flags are not reset Accordingly which of the two interrupt sources caused the interrupt needs to be determined using the interrupt service rout
241. rogram memory address by inputting four pulses on the X1 pin Repeat steps 7 to 12 until the last address 15 reached Select program memory address clear mode Apply 5 V to Vpp and to Vpp Turn the power off 230 CHAPTER 9 WRITING TO AND VERIFYING PROGRAM MEMORY PROM The timing for steps 2 to 12 is shown below Repeat x times Address Write ac gt Verify _ Additional write i RE AMAT NY epe Data Data inp P30 MD1 P31 MD2 P32 d MD3 231 PD75008 USER S MANUAL 9 3 READING THE PROGRAM MEMORY The procedure for reading the contents of program memory is described below The read is performed in the verify mode 1 Pull low all unused pins to Vss by means of resistors Bring X1 to low level 2 Apply 5 V to Vpp and Vpp 3 Wait 10 us 4 Select program memory address clear mode 5 Apply 6 V to Vpp and 12 5 V to Vpp 6 Select program inhibit mode 7 Select verify mode Data is output sequentially one address at a time for each cycle of four clock pulses appearing on the X1 pin Select program inhibit mode 9 Select program memory address clear mode 10 Apply 5 V to Vpp and to Vpp 11 Turn the power off N The timing for steps 2 to 9 is shown below P40 P43 P50 P53 Data output Data output y MDO P30 MD1 P31 MD2 P32
242. ruction is located at address xxFFH table data in the next page is transferred Remark Function in this section is applicable to the PD750006 and 0750008 whose program counters consist of 13 bits each This is also applicable to the PD750004 whose program counter consists of 12 bits and the uPD75P0016 whose program counter consists of 14 bits however 271 uPD750008 USER S MANUAL C 2 MOVT XA GBCXA Function For the uPD750006 and pPD750008 XA lt BCXA ROM Transfers the low order four bits of the table data eight bits in program memory to the A register and the high order four bits to the X register The table data is addressed by the low order one bit of the B register and the contents of the C X and A registers The table area must have necessary data loaded by an assembler pseudo instruction DB instruction The program counter is not affected by the execution of this instruction Table data H Table data L 12 11 87 43 0 C 2 MOVT XA GBCDE Function For the uPD750006 and pPD750008 XA lt BCDE pom Transfers the low order four bits of the table data eight bits in program memory to the A register and the high order four bits to the X register The table data is addressed by the low order three bits of the B register and the contents of the C D and E registers The table area must have necessary data loaded by an assembler pseudo instruction DB instruction The program counter i
243. rval timer watchdog timer which has the following functions a b C d Interval timer operation which generates a reference timer interrupt Operation as a watchdog timer for detecting program crashes and resetting the CPU Selection of a wait time for releasing the standby mode and counting Reading the count value m gt eee 5 3 1 Configuration of the Basic Interval Timer Watchdog Timer Figure 5 23 shows the configuration of the basic interval timer watchdog timer Figure 5 23 Block Diagram of the Basic Interval Timer Watchdog Timer From the clock generator Clear signal Clear signal 2 gt gt Basic interval timer BT interrupt 8 bit frequency divider request flag 9 Vectored 127 gt interrupt request f 2 A IRQBT signal B Internal Wait release reset signal signal for standby release e BIM3 BTM2 BTM1 BTMO SETI 4 Internal bus Note Instruction execution 5 3 2 Basic Interval Timer Mode Register BTM The BTM is a 4 bit register for controlling operation of the basic interval timer BT A 4 bit memory manipulation instruction is used to set the BTM Bit 3 can be independently manipulated using a bit manipulation instruction Example The interrupt generation interval is set to 1 37 ms at 6 00 MHz SEL 15 or CLR1 MBE MOV A 1111B MOV BIM A BTM lt 11118 99 PD750008 USER S MANUAL When b
244. s Int T Interrupt Vectored interrupt request priorityNote vector table address INTBT Reference time interval signal VRQ1 0002H basic interval timer wactchdog ea INT4 boo of both rising and falling edges INTO m edge slr VRQ2 VRQ2 0004H detection specification INTCSI Serial data transfer completion signal VRQ4 0008 INTTO Match signal between the count In 5 VRQ5 000AH register of timer event counter 0 and modulo register INTT1 Match signal between the count In VRQ6 000CH register of timer counter 1 and modulo register Note The interrupt priority is used to determine the priority when two or more interrupts are simultaneously generated Figure 6 2 Interrupt Vector Table Address 0000H RBE Internal reset start address high order 6 bits Internal reset start address low order 8 bits 0002H INTBT INT4 start address high order 6 bits INTBT INT4 start address low order 8 bits 0004H INTO start address high order 6 bits INTO start address low order 8 bits 0006H BE INT1 start address high order 6 bits INT1 start address low order 8 bits 0008H HBE INTCSI start address high order 6 bits INTCSI start address low order 8 bits 000AH HBE INT TO start address high order 6 bits INT TO start address low order 8 bits 000CH HBE INTT1 start address high order 6 bits INTT1 start address low order 8 bits 185
245. s This enables users to perform transfers arithmetic logical operations comparisons and increments and decrements at a speed comparable to that of an 8 bit microcomputer and thereby enables to program using mainly general registers 1 When used as a 4 bit register When the general register area is used on a 4 bit basis eight general registers the X A B C D E H and L registers are available the register bank specified with RB RBE RBS as shown in Figure 3 5 TheA register functions as a 4 bit accumulator which performs transfers arithmetic logical operations and comparisons Theother general registers perform transfers comparisons and increments decrements with the accumulator 35 PD750008 USER S MANUAL 2 When used as an 8 bit register 36 When the general register area is used on an 8 bit basis the register pairs in the register bank specified RBE RBS can be specified as XA BC DE and HL as shown in Figure 3 6 and the register pairs in the register bank that has the inverted value of bit O of the register bank RB can be specified as XA BC DE and HL thus providing up to eight 8 bit registers The XA register pair functions as an 8 bit accumulator which performs transfers arithmetic logical operations comparisons and increments decrements of 8 bit data The other register pairs perform transfers arithmetic logical operations comparisons and increments decrements with the accumulator Th
246. s not affected by the execution of this instruction 12 11 87 4 3 0 Remark Function in this section is applicable to the uPD750006 and PD750008 whose program counters consist of 13 bits each This is also applicable to the PD750004 whose program counter consists of 12 bits and the uPD75P0016 whose program counter consists of 14 bits however 272 CHAPTER 11 INSTRUCTION SET 11 4 3 Bit Transfer Instructions C 2 MOV1 CY fmem bit C 2 MOV1 CY pmem Gl C 2 MOV1 CY H mem bit Function CY lt bit specified in operand Transfers the data memory bit specified by bit manipulation addressing fmem bit 2 H mem bit to the carry flag CY Function bit specified in operand CY Transfers the carry flag CY bit to the data memory bit specified by bit manipulation addressing fmem bit pmem L H mem bit Example flag bit 3 at address in data memory is set in bit 2 of port FLAG EQU 3FH 3 SEL MBO MOV H FLAG SHR6 H lt high order 4 bits of FLAG MOV1 CY H FLAG CY lt FLAG MOV1 PORT3 2 CY P32 lt 11 4 4 Arithmetic Logical Instructions C 2 ADDS A n4 Function A A n4 Skip if carry n4 13 0 O FH Adds the 4 bit immediate data n4 to the contents of the A register in binary then skips the next instruction if the addition generates a carry The carry flag is not affected This instruction when combined with the ADDC A HL or SUBC A HL instruction f
247. s of 13 bits addr 0000H to and the uPD75P0016 whose program counter consists of 14 bits addr 0000H to 3FFFH C 2 BRCB caddr Function For the uPD750008 PC42 9 12 n000H nFFFH PC41o 0 1 Branches to the address specified by the program counter whose low order 12 bits PC44 9 have been replaced with the 12 bit immediate data caddr 44 0 Since the program counter of the uPD750004 consists of 11 bits this instruction enables a branch to any location in the program memory space In the uPD750006 and 0750008 cannot be changed so no branch occurs beyond the block Similarly the uUPD75P0016 12 and PC45 cannot be changed so no branch occurs beyond the block Caution The BRCB caddr instruction usually causes a branch within the block containing the instruction However if the first byte is located at address OFFEH or OFFFH a branch to block 1 instead of block 0 occurs Program memory Block 0 OFFEH OFFFH If the BRCB caddr instruction is located at a or b in the figure above a branch to block 1 instead of block 0 occurs Remark Function in this section is applicable to the uPD750008 whose program counter consists of 13 bits addr OOOOH to 1FFFH However this is also applicable to the uPD750004 whose program counter consists of 12 bits addr OOOOH to OFFFH the PD750006 whose program counter consists of 13 bits addr
248. s of register pair ro XA HL DE BC XA HL DE BC 269 uPD750008 USER S MANUAL 11 4 2 Table Reference Instructions D MOVT XA PCDE Function For the uPD750006 and PD750008 XA lt ROM PCj9 3 DE Transfers the low order four bits of the table data in program memory to the A register and the high order four bits to the X register The table data is addressed by the program counter PC with its low order eight bits exchanged with the contents of the DE register pair The table address is determined by the contents of the program counter PC present when this instruction is executed The table area must have necessary data loaded by an assembler pseudo instruction DB instruction The program counter is not affected by the execution of the pseudo instruction This instruction is useful for consecutive table data references Example For the 0750006 and 0750008 Program memory 7 43 0 Table Table data H data L Table address Remark Function in this section is applicable to the uPD750006 and PD750008 whose program counters consist of 13 bits each This is also applicable to the PD750004 whose program counter consists of 12 bits and the uPD75P0016 whose program counter consists of 14 bits however Caution The MOVT XA PCDE instruction usually references table data in the page containing that instruction However when the instruction is located at address xxFFH table d
249. s with higher priority INTBT has higher priority and INTTO and INTCSI have lower priority lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt Reset 1 0 SEL RB2 El IEBT El IETO El IECSI 1 MOV A 9 MOV IPS A Status 0 lt INTTO service program gt 0 lt INTBT service program gt Status 1 E S 2 INTTO a 24 gt SEL lt 3 gt INTBT 7 Status 2 5 SEL RB2 RETI Status 1 Status 0 RETI INTBT is specified as having the higher priority by setting of IPS and the interrupt is enabled at the same time INTTO service program is started when INTTO with the lower priority occurs Status 1 is set and the other interrupts with the lower priority are disabled RBE 0 to select register bank 0 INTBT with the higher priority occurs The level two interrupts occurs The status is changed to 0 and all the interrupts are disabled RBE 1 and RBS 1 to select register bank 1 only the registers used may be saved by the PUSH instruction RBS is returned to 2 and execution returns to the main program The status is returned to 1 205 uPD750008 USER S MANUAL 4 Execution of held interrupts interrupt requests when interrupts are disabled Main program Reset gt El lt gt INTO lt 2 gt El lt 4 gt EI IECSI INTO service program 3 INTCSI RETI INTCSI service program RETI
250. same time 121 PD750008 USER S MANUAL Re set instruction Re set instruction Clock A specified Clock B specified Clock A specified Clock B lt 1 gt lt 2 gt SVS 5 Operation after the modulo register is changed The contents of the modulo register are changed when an 8 bit data memory manipulation instruction is executed CP Modulo register n X m Re set instruction Count register n Match signal Match signal If the new value of the modulo register is less than the value of the count register the count register continues count operation until it overflows then it restarts count operation from 0 Accordingly if the new value m of the modulo register is less than the value n before it is changed the timer must be restarted after the contents of the modulo register are changed CP Modulo register n X m Count register 122 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5 6 SERIAL INTERFACE 5 6 1 Serial Interface Functions The PD750008 contains a clock synchronous 8 bit serial interface which has four modes The functions of the four modes are outlined below 1 Operation halt mode This mode is used when serial transfer is not performed This mode reduces power consumption 2 Three wire serial I O mode 3 4 In this mode 8 bit data is transferred through three lines Serial clock SCK serial output SO and serial input SI The three wire serial I O
251. se signal these bits are automatically cleared to return to the normal operation mode See Chapter 7 for details A 4 bit memory manipulation instruction is used to set the low order two bits of the PCC The high order two bits are set to 0 Bit 3 and bit 2 are set to 1 using the STOP instruction and HALT instruction respectively The STOP instruction and HALT instruction can always be executed regardless of MBE setting The CPU clock can be selected only while the processor is operated by the main system clock When the processor is operated by the subsystem clock the low order 2 bits of the PCC are invalidated and fy7 4 is automatically set The STOP instruction can be executed only when the processor is operated by the main system clock Examples 1 The machine cycle is entered in highest speed mode 0 67 us at fy 6 00 MHz SEL MB15 MOV A 0011B MOV PCC A 2 The machine cycle is set to 1 91 us at fx 4 19 MHz SEL MB15 MOV A 0010B MOV PCC A 3 The STOP mode is set A STOP instruction or HALT instruction must always be followed by an NOP instruction SIOP NOP A RESET signal clears the PCC to O CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 12 Format of the Processor Clock Control Register Address Symbol 3 0 FB3H PCCO CPU clock selection bit Operation with fx 6 0 MHz SCCO 00 SCC3 SCCO 01 or 11 is actual We an at fx 6 0 MHz is actual frequency at fxt 32 768 kHz CPU clo
252. setting of the MBS thus enabling data memory space expansion In addressing data memory space the MBE is usually set to 1 MBE 1 and data memory in the memory bank specified in the MBS is operated However the MBE 0 mode or MBE 1 mode can be selected for each step of processing for more efficient programming 21 PD750008 USER S MANUAL Applicable program processing Effect MBE 0 mode e Interrupt processing MBS save restoration becomes unnecessary Processing that repeats internal MBS modification becomes unnecessary hardware and static RAM operations e Subroutine processing MBS save restoration becomes MBE 1 mode Usual program processing Figure 3 1 Use of MBE 0 Mode and MBE 1 Mode lt Main program gt lt Subroutine gt MBE 1 CLR1 MBE MBE 0 Internal hardware EMEN and static RAM MBE RET Interrupt processing operations are repeated SET1 MBE gt MBE 0 is to be in the vector table MBE 0 RETI The contents of the MBE are automatically saved or restored at the time of subroutine processing so that the MBE can be freely modified during subroutine processing In interrupt processing the MBE is automatically saved or restored and when interrupt processing is started the contents of the MBE can be specified for the interrupt processing by setting the interrupt vector table This speeds up interrupt processing The setting of the MBS can be modified fo
253. sfer the contents of the accumulator to a port in units of four or eight bits the data of the accumulator is latched in the output latch with the output buffers kept off When the XCH instruction is executed the data on each pin is loaded into the accumulator and the data in the accumulator is latched in the output latch with the output buffers kept off When the INCS instruction is executed the 4 bit data existing on the pins plus 1 is latched in the output latch with the output buffers kept off Whenan instruction such as the SET1 CLR1 or SKTCLR instruction is executed to rewrite a data memory bit the output latch data of the specified bit can be rewritten according to the instruction but the states of the other output latch bits are undefined Operation when the output mode is set When a test instruction or instruction for taking in port data on the internal bus in units of four or eight bits is executed output latch data is manipulated When an instruction is executed to transfer the contents of the accumulator in units of four or eight bits the output latch data is rewritten and is output on the pins When the XCH instruction is executed the output latch data is transferred to the accumulator The contents of the accumulator are latched in the output latches and are output on the pins When the INCS instruction is executed the contents of the output latch incremented by 1 are latched in the output latch and are output on the p
254. shown in Table 5 5 to the time when the CPU clock signal is changed When changing an operation clock pulse before the standby mode or a CPU clock signal after the standby mode is released it is necessary to rewrite PCC and set the standby mode after as many machine cycles as required to change the CPU clock pulse have elapsed In a standby mode the contents of all registers and data memory that are stopped during the standby mode including general registers flags mode registers and output latches are retained Caution 1 When the STOP mode is set the X1 input is internally connected to Vss ground potential to suppress leakage at the crystal oscillator circuitry This means that the STOP mode cannot be used with a system that uses an external clock 216 CHAPTER 7 STANDBY FUNCTION Caution 2 Reset all the interrupt request flags before setting the standby mode If an interrupt source whose interrupt request flag and interrupt enable flag are both set exists the initiated standby mode is released immediately after it is set see Figure 6 1 When the STOP mode is set however the PD750008 enters the HALT mode immediately after the STOP instruction is executed then returns to the operation mode after the wait time specified by the BTM register has elapsed 7 2 RELEASE OF THE STANDBY MODES The STOP mode and HALT mode are released by a RESET signal or the generation of an interrupt request signal that is enabled with the interrupt
255. skip unconditionally e uPD750006 pPD750008 0 0 0 12 SP 1 PC11 0 S SP SP 3 SP 2 x X MBE RBE SP 4 SP lt SP 6 Then skip unconditionally e uPD75P0016 0 0 PC45 12 SP 1 PC41 9 lt SP SP 3 SP 2 x X MBE RBE SP 4 SP lt SP 6 Then skip unconditionally RETINote 1 3 WPD750004 Unconditionally MBE RBE 0 0 SP 1 11 lt SP SP 3 SP 2 PSW lt SP 4 SP 5 SP lt SP 6 750006 uPD750008 MBE 0 PCy SP 1 PC11 0 e SP SP 3 SP 2 PSW lt SP 4 SP 5 SP lt SP 6 uPD75P0016 MBE HBE PC4o SP 1 PC11 0 lt SP SP 3 SP 2 PSW lt SP 4 SP 5 SP lt SP 6 Note The shaded portion is supported in II mode only The other portions are supported Mk mode only Unconditionally Subroutine stack control 254 CHAPTER 11 INSTRUCTION SET Address on Operand Machine Operation ing Skip condition tion monic cycle area RETINote 1 1 3 uPD750004 0 0 0 0 lt SP 1 PC11 0 lt SP SP 3 SP 2 PSW SP 4 SP 5 SP lt SP 6 uPD750006 PD750008 0 0 0 12 SP 1 PC11 0 lt SP SP 3 SP 2 PSW lt SP 4 SP 5 SP lt SP 6 uPD75P0016 0 0 PC45 12 SP 1 PC11 0 lt SP SP 3 SP 2 EEr lt SP 4 SP 5 SP lt SP 1 SP 2 rp SP SP 2 SP 1 lt MBS 5 2 RBS _ lt SP 2 1 1 lt SP 1 SP
256. specified with the SBS A stack area must be within the memory bank specified with the SBS If a stack operation exceeds address the operation returns to address nFFH in the same bank Linear stacking beyond memory bank boundaries is enabled only by resetting the SBS A RESET signal causes the contents of the SP to be undefined and causes the contents of the SBS to be 1000B Remember to initialize the SP and SBS to a desired value at the start of a program 58 CHAPTER 4 INTERNAL CPU FUNCTIONS Figure 4 11 Format of Stack Pointer and Stack Bank Select Register Address Symbol sr Tee Tor F84H 5853 0 9851 sBso SBS SBS Memory bank 0 SP Memory bank 1 SP Note The Mk I mode and Mk II mode be switched by bit 3 of SBS The stack bank selection function can be used in both Mk mode and Mk Il mode See Section 4 1 for details Example SP initialization Specify memory bank 1 as a stack area to start stack operation at address 1FFH SEL MB15 or CLR1 MBE MOV A 1 MOV SBS A Specify memory bank 1 as a stack area MOV XA 00H MOV SP XA SP lt 00H Figure 4 12 Data Saved to the Stack Memory Mk 1 Mode PUSH instruction CALL or CALLF instruction Interrupt Stack Stack Stack sea sp 6 pcr Note Note Note Note mee Ree 5 sp 2 Pcs Pco seca Pos Upper bits of pair register SP 1 PC7
257. struction When changing the low order three bits of the IPS interrupts must be disabled IME 0 beforehand Example Disable interrupts CLR1 MBE MOV A 1011B MOV IPS A Assign a higher priority to INT1 then enable interrupts A RESET signal clears all bits to O Caution Disable interrupts before setting the IPS 188 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS Figure 6 3 Interrupt Priority Specification Register Address Symbol 3 2 1 0 FB2H IPS3 IPS2 IPS1 IPSO IPS High order interrupt selection All low order interrupt VRQ1 The listed vectored INTBT INT4 interrupts are treated as high order interrupts 1 VRQ2 INTO 1 4 INT1 VRO4 INTCSI VRQ5 INTTO VRQ6 INTT1 Not to be set Interrupt master enable flag IME All interrupts are disabled and no vectored interrupt is activated 1 The interrupt enable flag corresponding to an interrupt request flag controls interrupt enabling disabling 189 uPD750008 USER S MANUAL 3 Configurations of the INTO INT1 and INT4 circuits 190 a As shown in Figure 6 4 a the INTO circuit accepts an external interrupt at its rising or falling edge The edge to be detected can be selected The INTO circuit has a noise elimination function see Figure 6 5 called a noise eliminator using a sampling clock which removes pulses shorter than two sampling clock cyclesNote as noise The INTO circuit ma
258. structions independently of the other PSW bits A RESET signal causes the carry flag to be undefined 62 CHAPTER 4 INTERNAL CPU FUNCTIONS Table 4 4 Carry Flag Manipulation Instructions Instruction mnemonic Carry flag operation processing Instruction dedicated to carry SET1 CY Sets CY to 1 flag manipulation CLR1 CY Clears CY to 0 NOT1 CY Inverts the state of CY SKT CY Skips if CY is 1 Bit transfer instruction MOV1 mem bit CY Transfers the state of CY to a specified bit MOV 1 CY mem bit Transfers the state of a specified bit to CY Bit Boolean instruction AND 1 CY mem bit ANDs ORs or XORs CY with a specified bit OR1 CY mem bit then sets the result in CY XOR1 CY mem bit Interrupt handling Interrupt execution Saves CY and all other PSW bits to stack memory in parallel RETI Restores CY together with the other PSW bits from stack memory in parallel Remark mem bit represents the following bit addressing fmem bit e pmem L e H mem bit Example Bit 3 at address 3FH is ANDed with P33 then the result is set in P50 MOV H 3H Set the high order 4 bits of the address in H register MOV1 CY H 0FH 3 CY lt bit 3 at AND1 CY PORT3 3 CY lt CY P33 MOV1 PORT5 0 CY P50 lt CY 2 Skip flags SK2 SK1 SKO The skip flags are used to store skip status and are automatically set or reset when the CPU executes an instruction The user cannot directly manipulate these flags
259. structions described in a above 1 machine cycle 240 CHAPTER 11 INSTRUCTION SET 11 2 INSTRUCTION SET AND OPERATION 1 Operand identifier and description The operand field of an instruction must contain an operand coded according to the description rule for the operand identifier of the instruction Refer to RA75X Assembler Package User s Manual Language EEU 1343 for detailed information When there are multiple descriptions for an identifier one item is to be selected The uppercase letters and and signs are keywords which must be coded as they appear For immediate data a proper numeric value or label must be coded The abbreviations for register flags shown in Figure 3 7 can be coded as labels in place of mem fmem and bit However not all labels can be coded for the fmem and pmem For details see Table 3 1 and Figure 3 7 Representation format Description method reg X A B C D E H L reg1 X B C D E H L rp XA BC DE HL DE HL rp2 BC DE rp XA BC DE HL XA BC DE HL rp 1 BC DE HL XA BC DE HL rpa HL HL HL DE DL 1 DE DL n4 4 bit immediate data or label n8 8 bit immediate data or label mem 8 bit immediate data or labelNote bit 2 bit immediate data or label fmem FBOH FBFH and FFOH FFFH immediate data or label pmem FCOH FFFH immediate data or label addr OOOOH OFFFH immediate data or label uPD750004
260. t P ch Mask ODIO NOUT Data IN OUT Data ype Output Output 13 V disable disable P U R Pull Up Resistor Input buffer with an intermediate withstand voltage of 13 V P U R Pull Up Resistor Note Pull up resistor that operates only when an input instruction is excuted valid at low voltage Type M E Input instruction P ch P U R enable Note Output disable IN OUT P ch Data IN OUT EE voltage 13 V Data 29 25 disable 9 Output N ch disable Output disable Input buffer with an intermediate N ch withstand voltage of 13 V b Note Pull up resistor that operates only when an input P U R Pull Up Resistor instruction is executed valid at low voltage 19 PD750008 USER S MANUAL 2 4 CONNECTION OF UNUSED PINS 20 Table 2 3 Connection of Unused Pins Pin name POO INT4 01 5 P02 SO SBO 03 51 5 1 P10 INTO P12 INT2 P13 TIO P20 PTOO P21 PTO1 P22 PCL P23 BUZ P30 MDO P33 MD3 Note P40 P43 P50 P53 P60 P63 P70 P73 P80 P81 XT 1 XT2 Vpp Note Note uPD75P0016 Recommended connection To be connected to Vss To be connected to Vss or Vpp To be connected to Vss Input state To be connected to Vss or Vpp through a resistor Output state To be left open To be connected to Vss or Vpp To be left open To be connected directly to Vpp CHAPTER 3 FEATURES OF THE ARCH
261. t TMO5 TMO4 Count pulse CP TIO rising edge TIO falling edge fx 219 fx 28 fx 2 fx 2 Other than above Not to be set Timer start indication bit When 1 is written into the bit the counter and IRQTO flag are cleared If bit 2 is set to 1 count operation is started Operation mode Count operation Stop retention of count contents 1 Count operation 115 PD750008 USER S MANUAL Figure 5 33 Timer Event Counter Mode Register Setup 2 2 b In the case of timer counter channel 1 Address 7 6 5 4 3 2 1 0 Symbol FA8H TM16 TM15 14 TM13 12 1 Count pulse CP selection bit Count pulse CP fx 28 Other than above Not to be set Timer start indication bit When 1 is written to the bit the counter and IRQT1 flag are cleared If bit 2 is set to 1 count operation is started Operation mode Count operation Stop retention of count contents Count operation b Timer event counter output enable flag TOEn The TOEn is manipulated by a bit manipulation instruction The TOEn is cleared to 0 by an internal reset signal Figure 5 34 Timer Event Counter Output Enable Flag Setup Address FA2H Channel 0 Timer event counter output enable flag W FAAH Channel 1 Disabled outputs the low level signal Enabled 116 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
262. t be cleared by an instruction 40 CHAPTER 3 FEATURES OF THE ARCHITECTURE AND MEMORY MAP Figure 3 7 0750008 I O 2 5 Number of bits that can be Hardware name symbol manipulated Bit Address manipulation Remarks Bit write manipu FAOH A mem bit lation is enabled Timer event counter mode register R W R W d for bit 3 FA4H Timer event counter count register 0 FA6H EL Timer event counter modulo register R W Bit write manipu FA8H mem bit lation is enabled Timer counter mode register TM1 R W for bit 3 mae 9 FACH EN Timer counter count register T1 FAEH Timer counter modulo register TMOD1 R W Notes 1 TOEO Timer event counter output enable flag W 2 TOE1 Timer counter output enable 41 PD750008 USER S MANUAL Figure 3 7 0750008 I O Map 3 5 Number of bits that can be Hardware name symbol manipulated Bit Address manipulation Remarks FBOH Manipulation in R W R W bit units i T status word rus ET 6 for reading fmem bit FB2H Interrupt priority select register IPS ERA Lo FB3H Processor clock control register PCC fof FB4H INTO edge detection mode register IMO o mM 3 2 and 1 are fixed to O Bits 3 and 2 are 0 FB5H INT1 edge detection mode register IM1 paw FB6H INT2 edge detection mode register IM2 paw A
263. t operate Can operate only at main system timer watchdog clock oscillation IRQBT is set at timer reference time intervals Serial interface Can operate only when the external Can operate only when external SCK SCK input is selected for the serial input is selected as the serial clock or clock at main system clock oscillation Timer event Can operate only when the TIO pin Can operate only when TIO pin input counter input is selected for the count clock is specified as the count clock or at main system clock oscillation Clock timer Can operate when fxr is selected as Can operate the count clock External interrupt INT1 INT2 and INT4 can operate Only INTO cannot operate Note 2 Release signal An interrupt request signal from hardware whose operation is enabled by the interrupt enable flag or the generation of a RESET signal Notes 1 Operation is possible only when the main system clock operates 2 Operation is possible only when the noise eliminator is not selected by bit 2 of the edge detection mode register IMO when 02 1 A STOP instruction is used to set the STOP mode and a HALT instruction is used to set the HALT mode A STOP instruction sets bit 3 of PCC and a HALT instruction sets bit 2 of PCC STOP instruction or HALT instruction must always be followed by an NOP instruction When changing a CPU operation clock pulse with the low order two bits of PCC a time lag may occur from the time when PCC is rewritten as
264. t register bank 1 Use of a software interrupt for debugging Setting an interrupt request flag using an instruction has the same effect as the occurrence of an interrupt Debug operation for irregular interrupts or concurrently occurring interrupts can be performed more efficiently by setting the interrupt request flags using an instruction INTERRUPT APPLICATIONS To use the interrupt function a main program must a Set a desired interrupt enable flag using the El IExxx instruction b Select an active edge when INTO or INT1 is used set IMO or IM1 c To use nesting of an interrupt with the higher priority set IPS IME can be set at the same time d Set the interrupt master enable flag IME using the El instruction In the interrupt routine MBE and RBE are set by the vector table However when the interrupt specified as having the higher priority is processed the register bank must be saved and set To return from the interrupt routine use the RETI instruction 202 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS 1 Interrupt enable disable lt Main program gt lt 1 gt Reset gt lt 2 gt El IEO Interrupt disabled El IETO lt 3 gt El INTO and INTTO enabled lt 4 gt DI IEO INTTO enabled b DI Interrupt disabled 1 A RESET signal disables all interrupts 2 Interrupt enable flags are set by the El IExxx instruction At this stage all interrupts are disabled 3 he interrupt master en
265. t specified by the 2 bit immediate data bit at the address specified by the 8 bit immediate data mem is 1 Function Skip if bit specified in operand 1 Skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing fmem bit omem L H mem bit is set to 1 C 2 SKF mem bit Function Skip if mem bit 0 mem D7 9 OOH FFH bit 1 0 0 3 Skips the immediately following instruction if the bit specified by the 2 bit immediate data bit at the address specified by the 8 bit immediate data mem is 0 C 2 SKF fmem bit D SKF pmem L C 2 SKF GH mem bit Function Skip if bit specified in operand 0 Skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing fmem bit onem L H mem bit is 0 Function Skip if bit specified in operand 1 then clear Skips the immediately following instruction if the bit in data memory specified by bit manipulation addressing fmem bit omem L H mem bit is 1 then clears the bit to 0 283 uPD750008 USER S MANUAL C 2 AND1 CY pmem L 7 AND1 CY H mem bit Function CY CYA bit specified in operand ANDs the content of the carry flag with the bit in data memory specified by bit manipulation addressing fmem bit pnem L H mem bit then sets the result in the carry flag 2 CY fmem bit 7 CY pmem L 7 ORI CY H mem bit Function CY lt
266. t to 01008 to select maximum set time 43 7 ms at fx 6 00 MHz The low order four bits of the mode register are set to 1100B The modulo register is set to the following value 30 ms 171 us 175 4 AFH lt Sample program gt SEL MOV MOV MOV MOV El El MB15 XA 0AEH TMODO XA Set the modulo register XA 01001100B TMO XA oet the mode register and start the timer Enable an interrupt IETO Enable a timer interrupt Remark In this application the TIO pin can be used as an input pin b An interrupt is caused when the number of pulses active high applied to the TIO pin reaches 100 he high order four bits of the mode register are set to 0000 to select the rising edge The low order four bits of the mode register are set to 1100B e The modulo register is set to 99 100 1 119 PD750008 USER S MANUAL lt Sample program gt SEL MB15 MOV XA 100 1 MOV TMODO XA Set the modulo register MOV XA 00001100B MOV TMO XA oet the mode register EI EI IETO Enable INTTO 5 5 3 Notes on Timer Event Counter Applications 1 Time error at the start of the timer A maximum error of one count pulse CP cycle from a value calculated according to Section 5 5 2 2 occurs in a time period from the start of the timer bit 3 of the TMO is set to the generation of a match signal This is because the count register TO is cleared not in phase with the CP as shown in Figure 5 37 Figure 5 37
267. tack Bank Selection Register SBS The Mk mode and Mk II mode are switched by stack bank selection register Figure 4 1 shows the register configuration The stack bank selection register is set with a 4 bit memory operation instruction To use the CPU in Mk mode initialize the register to 10xxBNote at the beginning of the program To use the CPU in Mk mode initialize it to OOxxBNote 46 Figure 4 1 Stack Bank Selection Register Format Address 3 0 Symbol 2 1 893 SBS L 1 Stack area designation EXE Memory bank 0 Memory bank 1 Other settings are inhibited Bit 2 must be set to 0 Mode switching designation o Mk 1 mode Mk mode Note Specify the desired value in xx Caution The CPU operates in Mk mode after the RESET signal is issued because bit of SBS is set to 1 Set bit 3 of SBS to 0 Mk II mode to use the CPU in Mk Il mode CHAPTER 4 INTERNAL CPU FUNCTIONS 4 2 PROGRAM COUNTER PC 12 BITS uPD750004 13 BITS uPD750006 AND pPD750008 14 BITS uPD75P0016 The program counter is a binary counter which retains the address data of the program memory The program counter consists of 12 bits in the uPD750004 see Figure 4 2 a 13 bits in the uPD750006 and uPD750008 see Figure 4 2 b and 14 bits in the uPD75P0016 see Figure 4 2 c Figure 4 2 Program Counter Organization a pPD750004 b PD750006 and pPD750008 c uPD75P0016 Usually each time an ins
268. tch is detected by hardware The slave address register SVA is available In the wake up state WUP 1 IRQCSI is set only when the address transmitted by the master and the value held in SVA match Cautions 1 Whether a slave is selected is determined by detecting a match for a slave ad dress received after bus release in the state of RELD 1 An address match is detected usually using an address match interrupt IRQCSI generated when WUP is set to 1 So detect selection nonselection state by slave address when WUP is set to 1 2 When determining whether a slave is selected without using an interrupt when WUP is 0 do not use the address match detection method Instead use transfer of commands set in advance in a program Error detection In the SBI mode the state of serial bus SBO or SB1 being used for communication is loaded into the shift register SIO of the transmitting device So a transmission error can be detected by the methods described below a Comparing SIO data before start of transmission with SIO data after start of transmission With this method the occurrence of a transmission error is assumed if two SIO values disagree with each other b Using the slave address register SVA Transmit data is set in SIO and SVA as well before the data is transmitted On completion of transmission the COI bit match signal from the address comparator of serial operation mode register CSIM is tested If the result is 1 th
269. ted CLR1 SET1 CLR1 SET1 PORTO 1 one Not allowed PORTO 1 OFFOH 1 Alidwad OFFOH 1 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 5 7 BIT SEQUENTIAL BUFFER 16 BIT The bit sequential buffer BSB is special data memory for bit manipulations In particular the buffer allows bit manipulations to be performed very easily by sequentially changing address and bit specifications So the buffer is useful in processing long data bit by bit This data memory consists of 16 bits and allows pmem L addressing with a bit manipulation instruction This addressing uses the L register for indirect bit specification In this case only by incrementing or decrementing the L register in a program loop the bit to be manipulated can be sequentially shifted for continued processing Figure 5 81 Format of the Bit Sequential Buffer Address FC2H FC1H FCOH Bit Symbol L register L CH L BH L 8H L 7H gt DECSL INCS L 5 Remarks 1 With pmem L addressing bit specification is shifted according to the L register 2 With pmem L addressing BSB can be manipulated at any time regardless of MBE MBS specification Data can also be manipulated by direct addressing The buffer can be used for applications such as continuous 1 bit data input or output operations by combining direct 1 bit 4 bit and 8 bit addressing with pmem L addressing In 8 bit manipulation the higher eight bits or lower eight bits are
270. ter Remark The operations of the assembler and device file are guaranteed only on the above host machines and OSs 301 PD750008 USER S MANUAL PROM programming tools Hardware PG 1500 The PG 1500 PROM programmer is used together with an accessory board and optional program adapter It allows the user to program a single chip microcomputer containing PROM from a standalone terminal or a host machine The PG 1500 can be used to program typical 256K bit to 4M bit PROMs PA 75P008CU The PA 75P008CU is a PROM programmer adapter provided for the 075 008 0 GB and puPD75P0016CU GB It is used in conjunction with the PG 1500 Software PG 1500 This program enables the host machine to control the PG 1500 through the serial and controller parallel interfaces Part number Distribution media PC 9800 series MS DOS 3 5 inch 2HD US5A13PG1500 Ver 3 30 to 5 25 inch 2HD US5A10PG1500 Ver 6 2Note and See OS for IBM 3 5 inch 2HD 157 13 01500 PC 5 25 inch 2HC uS7B10PG1500 Note These software products cannot use the task swap function which is available in MS DOS Ver 5 00 or later compatibles Remark Operation of the PG 1500 controller is guaranteed only on the above host machines and OSs 302 APPENDIX B DEVELOPMENT TOOLS Debugging Tools The in circuit emulators IE 75000 R and IE 75001 R are provided to debug programs used for the uPD750008 The following system is shown below
271. ter 1 to 3 are set set 1 in bit 3 of BIM within each interval Example Use the basic interval watchdog timer as a watchdog timer with 5 46 ms interval at 6 00 MHz A program is divided into several modules each of which can be executed within the interval set in BTM 5 46 ms BT is cleared at the end of each module If a program crash occurs BT overflows and an internal reset signal is generated because BT is not cleared within the set interval Initial setting MBE MB15 A 1101B Specifies a time interval and starts processing Enables the watchdog timer From now on 1 is set in bit 3 of BTM at intervals of 5 46 ms 102 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Module 1 Processing completes within 5 46 ms Module 2 Processing completes within 5 46 ms 5 3 6 Other Functions The basic interval timer watchdog has the following functions regardless of whether it operates as a basic interval timer or watchdog timer 1 lt 1 gt Selecting and counting the wait time after the standby mode is released lt 2 gt Reading the count Selecting and counting the wait time after the STOP mode is released To allow the system clock to stabilize after releasing the STOP mode a wait function is available which stops the operation of the CPU until the basic interval timer BT overflows The wait time after generation of a RESET signal is fixed as specified by a mask optio
272. th a serial interface conforming to SBI or peripheral ICs are used Figure 5 50 Example of SBI System Configuration Master CPU Slave CPU uPD750008 uPD750008 SBO SB1 SBO SB1 Address 1 SCK SCK Slave CPU SBO SB1 Address 2 AF Slave IC SBO SB1 Address N 150 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Cautions 1 In the SBI mode the serial data bus pin SBO or SB1 is an open drain output So the serial data bus line is placed in the wired OR state A pull up resistor is required for the serial data bus line 2 To switch between the master and slave a pull up resistor is required also for the serial clock line SCK because SCK input output switching is performed between the master and slave asynchronously 1 SBI functions Conventional serial 1 0 methods provide only data transfer functions Therefore many ports and wires are required to identify chip select signals commands and data and to detect busy states when the serial bus is configured with multiple devices Also these processes are too burdensome to be controlled by software The SBI method can configure a serial bus with two signal lines Serial clock SCK and serial data bus SBO or SB1 For this reason the number of ports on a microcomputer can be reduced and the wiring on a circuit board can be simplified SBI functions are described below a Address command data identification function Serial data is classified into th
273. the STOP mode is released do not include the time a in Figure7 2 required before clock oscillation is started following the release of the STOP mode regardless of whether the STOP mode is released by a RESET signal or the generation of an interrupt Figure 7 2 Wait Time When the STOP Mode Is Released STOP mode release Waveform at the X1 pin 7 3 OPERATION AFTER A STANDBY MODE IS RELEASED 1 If a standby mode is released by a RESET signal normal reset operation is performed 2 Ifastandby mode is released by the occurrence of an interrupt request the contents of the interrupt master enable flag IME determines whether to perform a vectored interrupt when the CPU resumes instruction execution a When IME 0 If a standby mode is released execution restarts with the instruction immediately following the instruction used to set the standby mode The interrupt request flag is held b When IME 1 If a standby mode is released a vectored interrupt is executed after the two instructions are executed However if the standby mode is released by INT2 or INTW testable input no vectored interrupt occurs and the same processing as a above is performed 219 PD750008 USER S MANUAL 7 4 SELECTION A MASK OPTION For the standby function of the uPD750008 either of the following two values can be selected by a mask option as the wait time during which the start of oscillation deferred from the generation of a RESET si
274. the TIO pin 2 2 5 PTOO PTO1 Output Pin Used Also for Port 2 This is the output signal pin of the programmable timer event counter and programmable timer counter Square wave pulses appear on this pin To output a signal from the programmable timer event counter and programmable timer counter the output latch P20 or P21 must be cleared to 0 and the bit for port 2 in the port mode register must be set to 1 output mode The output is cleared to 0 by the timer start instruction 13 PD750008 USER S MANUAL 2 2 6 PCL Output Pin Used Also for Port 2 This is the programmable clock output pin It is used to supply the clock pulse to a peripheral LSI circuit such as a slave microcomputer or A D converter A RESET signal clears the clock mode register CLOM to 0 disabling clock output then the pin is placed in the normal mode to function as a normal port 2 2 7 BUZ Output Pin Used Also for Port 2 An arbitrary frequency 2 048 4 096 or 32 768 kHz output on this pin can be used for sounding the buzzer or trimming the system clock frequency This pin is used also as the P23 pin and can be used only when bit 7 WM 7 of the clock mode register WM is set to 1 A RESET signal places this pin in the normal operation mode as a general port see Section 5 4 2 for details 2 2 8 SCK SO SBO SI SB1 Tristate I O Pins Used Also as Port 0 These are I O pins for serial interface They operate according to the setting of the serial opera
275. the instruction are cut When an internal clock is used for the count pulse signal this problem does not occur because of synchronization with the instruction Accordingly in an attempt to read the contents of the count register with a count pulse signal applied to TIO the signal must have a pulse wide enough to avoid incorrect counting even if count pulses are cut That is the contents of the count register are held by a read instruction for one machine cycle so that a signal applied to the TIO pin must have a pulse wider than that Read instruction External clock TIO Instruction CP Count register A change in a count A count pulse is canceled pulse is placed on hold by the instruction by the instruction 4 Notes on changing the count pulse When the count pulse is changed by rewriting the contents of the timer event counter mode register this takes effect immediately after the rewrite instruction is executed Re set instruction Re set instruction Clock A specified EN Clock A specified Clock B N N S CX IX SX F XJ X A combination of clocks used for changing count pulse signals can generate a spike lt 1 gt or lt 2 gt count pulse as shown in the figure below In this case an incorrect count operation may occur or the contents of the count register may be destroyed So when the count pulse is changed bit 3 of the timer event counter mode register must be set to 1 and the timer must be restarted at the
276. the two wire serial I O mode In addition this function can simplify the serial interface control portion of an application program 123 PD750008 USER S MANUAL Figure 5 38 Example of the SBI System Configuration Master CPU Serial clock Slave CPU SCK SCK 1 Address 1 SBO SB1 580 581 Address Command L Data Slave IC SCK N Address N SBO SB1 5 6 2 Configuration of Serial Interface Figure 5 39 shows the block diagram of the serial interface 124 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS MOS 3 J9 UNOD 01710 2 4 Jo oeJes Qe K ISoOul ISO LNI Asng 1591 8 eueg Jejunoo 1ndino LOd ISOLNI yoo d uono9 op aps tel Gawd 134 sng OIS 490181694 44S ssaJppy jeubis Yoel 1789 8 13481691 sseuppe yg 99 JO 2 6 e1nBiJ A O 39S L0d AV O 095 005 0 95 015 60 125 PD750008 USER S MA
277. the wiring as short as possible Remark uPD75P0016 PD750008 USER S MANUAL Pin name P10 P13 P20 P23 P30 P33 P40 P43 P50 P53 P60 P63 P70 P73 P80 P81 KRO KR7 SCK SI SO SBO 1 Port 0 RESET Port 1 TIO Port 2 PTOO 1 Port 3 BUZ Port 4 PCL Port 5 INTO 1 4 Port 6 INT2 Port 7 X1 2 Port 8 XT1 2 Key return NC Serial clock IC Serial input Serial output Vss Serial bus 0 1 Vpp MDO MD3 Reset input Timer input O Programmable timer output O 1 Buzzer clock Programmable clock External vectored interrupt 0 1 4 External test input 2 Main system clock oscillation 1 2 Subsystem clock oscillation 1 2 No connection Internally connected Positive power supply Ground Programming power supply Mode selection 0 3 CHAPTER 2 PIN FUNCTIONS 2 1 PIN FUNCTIONS OF THE pPD750008 Table 2 1 Digital I O Port Pins 1 2 Input Also 8 bit Upon T Pin PU used Function IJO circuit 4 bit input port PORTO Input For built in pull up resistors F A P02 can be connected by software in units of F B E 3 bits 10 Input 4 bit input port PORT1 Input 11 PINT INT Built in pull up resistors can be connected P12 INT2 by software in units of 4 bits Only the P13 m P10 INTO pin is provided with noise elimination function P20 4 bit I O port PORT2
278. then sets the resultin the A register If the subtraction generates a borrow the immediately following instruction is skipped The carry flag is not affected C 2 SUBS XA rp Function XA lt XA rp Skip if borrow Subtracts the contents of register pair ro XA HL DE BC XA HL DE BC from the contents of the XA register pair then sets the result in the XA register pair If the subtraction generates a borrow the immediately following instruction is skipped The carry flag is not affected Example Data memory is compared with register pair rp MOV XA mem SUBS XA rp mem mem lt 275 uPD750008 USER S MANUAL C 2 SUBS rp 1 XA Function lt 1 Skip if borrow Subtracts the contents of the XA register pair from the contents of register pair rp 1 HL DE BC XA HL DE BC then sets the result in register pair rp 1 If the subtraction generates a borrow the immediately following instruction is skipped The carry flag is not affected C 2 SUBC A HL Function A CY lt A HL CY Subtracts the data at the data memory location addressed by the HL register pair together with the carry flag from the contents of the A register then sets the result in the A register If the subtraction generates a borrow the carry flag is set If no borrow is generated the carry flag is reset If the execution of this instruction generates no borrow when this i
279. there is no interrupt request a vectored interrupt is executed in the same way as when an interrupt is requested Inputting a RESET signal clears the interrupt request and interrupt enable flags to 0 disabling all interrupts 187 uPD750008 USER S MANUAL Table 6 2 Set Signals for Interrupt Request Flags Interrupt S Interrupt request flag et signals for interrupt request flags enable flag IRQBT Set by a reference time interval signal from the basic interval timer watchdog timer IRQ4 Set by a detected rising or falling edge of an INT4 POO pin input signal 4 Set by a detected edge of INTO P10 pin input signal The detection edge is specified by the INTO edge detection mode register IMO IRQ1 Set by a detected edge of an INT1 P11 pin input signal The detection edge is specified by the INT1 edge detection mode register IM1 IRQCSI Set by a serial data transfer completion signal for the serial interface IRQTO Set by a match signal from timer event counter 0 IRQT1 Set by a match signal from the timer counter 2 Interrupt priority specification register IPS The interrupt priority specification register selects an interrupt with a higher priority from multiple interrupts using the low order three bits Bit 3 interrupt master enable flag IME specifies whether to disable all interrupts The IPS is set using a 4 bit memory manipulation instruction Bit 3 is set by an El instruction and reset by a DI in
280. tion for the addresses by hardware and checks whether the 8 bit data matches the number assigned to the slave slave address If the 8 bit data matches the slave address that slave is selected The selected slave continues to communicate with the master until disconnection is directed by the master 153 PD750008 USER S MANUAL Figure 5 55 Slave Selection Using an Address E Transmits address for slave 2 L Slave 2 Selected gt Slave 4 Not selected d Command and data The master sends commands to the slave selected by sending an address The master also transfers data to or from the slave Figure 5 56 Command SCK 1 2 3 4 Lo Le 7 Le 5 0 58 K C6 KCSKC4KC3 C2 A C1 CO Command signal Command Figure 5 57 Data SCK 1 2 13 4 5 lel 17 8 SBO 581 07 X D6 X D5 X D4 X D3 X D2 A D1 DO Data The 8 bit data following the command signal is defined as a command The 8 bit data without the command signal is defined as data The usage of commands or data can be selected optionally according to the communication specifications e Acknowledge signal ACK The acknowledge signal confirms the reception of serial data between the transmitter and the receiver 154 CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 58 Acknowledge Signal When output in phase with the 11th clock of SCK SCK 8 lel Hol 11 SBO SB1 CK When output in phase with the 9th clock of SCK
281. tion is referenced used instruction Execution of taddr taddr 1 instruction e uPD75P0016 When the TBR instruction is used PC15 0 lt taddr 5 taddr 1 When the TCALL instruction is used SP 4 SP 1 SP 2 lt PC41 0 SP 3 MBE RBE PC45 PCy PC43 0 lt taddr 5_9 taddr 1 SP lt SP 4 When an instruction other than Depends on the the TBR or TCALL instruction is referenced used instruction Execution of taddr taddr 1 instruction Note The TBR and TCALL instructions are assembler pseudo instructions to define tables used for GETI instructions Special 256 CHAPTER 11 INSTRUCTION SET In struc Mne Operand Notes 1 Special Machine cycle 3 The shaded portion is supported in Mk II mode only supported in Mk mode only GETI instructions Address ing area Skip condition uPD750004 When the TBR instruction is used PC41 9 lt taddr 3 9 taddr 1 When the TCALL instruction is used SP 6 SP 3 SP 4 lt PC 44 9 SP 5 lt 0 0 0 0 SP 2 x x MBE RBE PC41 9 lt taddr 3_9 taddr 1 SP lt 5 6 When instruction other than the TBR or TCALL instruction is used Execution of taddr taddr 1 instruction Depends on the referenced instruction e PD750006 PD750008 When the TBR instruction is used PC42 9 lt taddr 4 9 taddr 1 When the TCALL instruction is used SP 6 SP 3 SP 4 lt 11 SP 5 lt 0
282. tion mode registers CSIM A RESET signal stops serial interface operation and places these pins in the input port mode A Schmitt triggered input is used for each pin 2 2 9 INT4 Input Pin Used Also as Port 0 INT4 is an external vectored interrupt input pin which is rising edge active as well as falling edge active When a signal applied to this pin goes from low to high or from high to low the interrupt request flag is set INT4 is an asynchronous input and can accept a signal with some high level width or low level width regardless of what the CPU clock is The INT4 pin can also be used to release the STOP and HALT modes A Schmitt triggered input is used for this pin 2 2 10 INTO INT1 Input Pins Used Also for Port 1 These are edge detection vectored interrupt input pins INTO has a noise eliminator The edge to be detected can be selected using the edge detection mode registers IMO IM1 1 INTO bits 0 and 1 of IMO a Rising edge active b Falling edge active c Both rising and falling edges active d External interrupt signal input disabled 2 INT1 bit 0 of IM1 a Rising edge active b Falling edge active 14 CHAPTER 2 PIN FUNCTIONS INTO has a noise eliminator Two different sampling clocks for noise elimination can be switched The acceptable width of a signal depends on the CPU clock INT1 is an asynchronous input and can accept a signal with some high level width regardless of what the CPU cloc
283. tions C 2 INCS reg Function reg lt reg 1 Skip if reg 0 Increments the contents of register reg X A H L D E B C If the result of increment produces reg 0 the immediately following instruction is skipped C 2 INCS rp1 Function 1 1 Skip if rp1 OOH Increments the contents of register pair rp1 HL DE BC If the result of increment produces rp1 00H the immediately following instruction is skipped C 2 INCS HL Function HL lt HL 1 Skip if HL 0 Increments the data at the data memory location addressed by the HL register pair If the result of increment produces data that is O the immediately following instruction is skipped 279 uPD750008 USER S MANUAL C 2 INCS mem Function mem lt mem 1 Skip if mem 0 mem 0 00H FFH Increments the data at the data memory location addressed by the 8 bit immediate data mem If the result of increment produces data that is 0 the immediately following instruction is skipped C 2 DECS reg Function reg lt reg 1 Skip if reg FH Decrements the contents of register reg X A H L D E B C If the result of decrement produces reg FH the immediately following instruction is skipped C 2 DECS rp Function lt rp 1 Skip if ro FFH Decrements the contents of register pair rp XA HL DE BC XA HL DE BC If the result of decrement produces the immediatel
284. to a crystal ceramic resonator for main system clock generation When external clock is used it is input to X1 and its inverted signal is input to 2 XT1 Input Connection pin to a crystal for subsystem clock generation XT2 When external clock is used it is input to XT1 and EH XT2 is left open RESET Input Systomresetinput YC CNote 2 Internally connected BEEN Connect to Vpp keeping the wiring as short as possible Ed Postvepowersupy Ves GNDpoea VppNote 2 Program voltage application for program memory PROM write verify operation 12 5 V is applied for PROM write verify operation Connect to Vpp keeping the wiring as short as possible MD3Note 3 write verify operation NC No connection Notes 1 The circuits enclosed in circles have a Schmitt triggered input 2 Used as the Vpp pin for the uPD75P0016 3 Provided only in the uPD75P0016 11 PD750008 USER S MANUAL 2 2 PIN FUNCTIONS 2 2 1 P00 P03 PORTO Input Pins Used Also for INT4 SCK SO SBO and SI SB1 P10 P13 PORT1 Input Pins Used Also for INTO INT2 and TIO These are the input pins of the 4 bit input ports Ports 0 and 1 Ports 0 and 1 function as input ports and also have the functions described below 1 Port 0 Vectored interrupt input INT4 Serial interface I O SCK SO SBO SI SB1 2 Port 1 Vectored interrupt input INTO INT1 Edge detection test i
285. tors Whether to enable feedback resistors can Use of feedback for subsystem clock specified resistors is factory set Pin 6 9 CU P33 30 P33 MD3 P30 MDO connection 59 26 ag 23 26 GB 000 26 rr RN u Others Noise immunity and noise radiation vary with the circuit scale and mask layout Note 2 7 fy 21 8 ms at 6 0 MHz 31 3 ms at 4 19 MHz 215 fx 5 46 ms at 6 0 MHz 7 81 ms at 4 19 MHz Caution The noise immunity and noise radiation of the PROM model differ from those of the mask ROM model If you replace the PROM model with the ROM model of the course of experimental production to mass production perform thorough evaluation by using the CS model not ES model of the mask ROM model CHAPTER 1 GENERAL 1 4 BLOCK DIAGRAM Port 0 m POO Basic interval timer Porto watchdog timer Dm gram Port 1 P10 P13 counterNote 1 TIO O Timer event PTOO O CN Ponz P20 P23 TOUTO Y INTTO P30 P33 Leere KE s ROMNote 2 INTT1 Decode and program E P40 P43 memory control ome KE data memory suz o wei gt e Port 5 P50 P53 INTW 5 581 Y P60 P63 SO SBO Clocked serial SCK O interface TOUTO Y INTCSI 2 CPU clock KD eres Clock generator Sek P lock vcr a ze Sub Main Interrupt 0 27 P80 P81 control Bit sequential buffer 16 PCL P22 XT1 XT2 X1 X2 ic Vss RE
286. tput by ACKT is possible 1 When set before transfer set before transfer ACK is output in phase with the 9th clock of SCK When set after transfer ACK is output in phase with SCK immediately following the set instruction execution Acknowledge trigger bit W When set after transfer ACK is output in phase with the next SCK After ACK signal output this bit is automatically cleared to O Cautions 1 Never set ACKT before or during serial transfer 2 ACKT cannot be cleared by software 3 Before setting ACKT set ACKE 0 Command detection flag R Condition for being cleared CMDD 0 Condition for being set CMDD 1 The transfer start instruction The command signal CMD is detected is executed The bus release signal REL The RESET signal is entered CSIE 0 Figure 5 40 Bus release detection flag R Condition for being cleared RELD 0 Condition for being set RELD 1 The transfer start instruction is executed The bus release signal REL is detected The RESET signal is entered CSIE 0 Figure 5 40 SVA does not match SIO when an address is received Command trigger bit W Control bit for command signal CMD trigger output By setting CMDT 1 the SO latch is cleared Then the CMDT bit is automatically cleared Caution Never clear SBO or SB1 during serial transfer Be sure to clear SBO or SB1 before or after serial transfer 159 PD750008 USER S MANUAL Bus
287. truction is executed the program counter is automatically incremented according to the number of bytes in the instruction When a branch instruction BR BRA BRCB is executed immediate data indicating the branch destination and the contents of a register pair are set in all or some bits of the program counter When a subroutine call instruction CALL CALLA CALLF is executed or a vectored interrupt occurs the current contents of the program counter already incremented return address for fetching the next instruction are saved in the stack memory data memory indicated by the stack pointer then the jump destination address is loaded When a return instruction RET RETS RETI is executed the contents of the stack memory are set in the program counter When the RESET signal is issued the program counter is initialized to the contents of the program memory at addresses 000H and 001H The program can be started from any address according to the contents uPD750004 PC41 PCg lt OOOH 3 0 PC7 PCo lt 001 7 0 UPD750006 uPD750008 1 gt lt OOOH 4 0 PCz POg lt 001 7 0 uPD75P0016 PC43 POg lt OOOH 5 9 lt 001H 7 0 47 PD750008 USER S MANUAL 4 3 PROGRAM MEMORY ROM 4096 WORDS x 8 BITS PD750004 MASKED ROM 6144 WORDS x 8 BITS uPD750006 MASKED ROM 8192 WORDS x 8 BITS PD750008 MASKED ROM 16384 WORDS x 8 BITS uPD75P0016 ONE TIME PROM The program
288. uc Mne Operand Machine Operation ing Skip condition tion Monic cycle area laddr Pere 0 lt addr uPD750008 0 lt addr 75 0016 0 lt addr addr 1 uPD750004 PC 0 addr uPD750006 0750008 PC 190 9 addr uPD75P0016 PC15 0 addr 0750004 PCDE 2 3 uPD75P0016 PC43 9 lt DE PCXA 2 3 uPD750004 PC11 0 lt 4 uPD750006 0750008 12 0 lt 12 8 uPD75P0016 0 lt 13 8 BCDE pPD750004 PC44 9 BCDENote 1 Note 1 Setregister B to O 2 Only the LSB is valid in register B 3 Only the low order two bits are valid in register B PC11 0 lt uPD750006 uPD750008 PC42 9 addr1 uPD75P0016 PC43 9 addr1 pPD750004 PC11 0 lt PC41 8 DE Branch e 1 1 1 1 0750006 750008 12 0 lt PC4o 1 0750006 uPD750008 PC40 9 lt BCDENote 2 UPD75P0016 PC43 9 BCDENote 250 CHAPTER 11 INSTRUCTION SET In struc Mne Operand Te BRANote 1 laddr1 3 3 PC15 0 addr1 BRCB Icaddr 2 2 uPD750004 8 PC11 0 lt 11 uPD750006 uPD750008 12 0 lt uPD75P0016 13 0 lt PC13 12 11 Operation cycle ie 11 PC44 9 BCXANote 1 pPD750006 PD750008 PC12 9 BCXANote 2 e uPD75P0016 PC43 9 BC
289. uction Manipulation instruction execution Input timing lt gt When data is latched by 1 machine cycle instruction P Instruction Manipulation instruction execution Output latch output pin d When data is latched by a 2 machine cycle instruction Instruction Manipulation instruction execution Output latch output pin Figure 5 10 ON Timing Chart of Built in Pull Up Resistor Connected by Software 2 machine cycles Instruction Built in pull up resistor setting instruction execution Pull up resistor specification register 83 PD750008 USER S MANUAL 5 2 CLOCK GENERATOR 5 2 1 Remarks 1 fy 84 The clock generator supplies various clock signals to the CPU and peripheral hardware to control the CPU operation mode Clock Generator Configuration Figure 5 11 shows the configuration of the clock generator Main system clock generator Oscillator disable signal Subsystem clock generator Clock timer 1 1 to 1 4096 Frequency divider 1 2 1 4 1 16 Internal bus HALT flip flop PCC2 PCC3 clear signal Note STOP flip flop Instruction execution Ci Main system clock frequency 2 fyt Subsystem clock frequency e CPU clock PCC Processor clock control register SCC System cl
290. umber system after conversion The following combination of instructions subtracts data in memory HL from the contents of an accumulator then converts the result of the subtraction to number system m SUBC A HL ADDS A m An underflow is set in the carry flag If the execution of the instruction SUBC A HL generates no borrow the next instruction ADDS A n4 is skipped If a borrow is generated the instruction ADDS A n4 is executed In this case the skip function of this instruction ADDS A n4 is disabled so that even if this addition generates a carry the instruction following this instruction is not skipped Accordingly programs can be written after ADDS A n4 239 uPD750008 USER S MANUAL 11 1 5 Skip Instructions and the Number of Machine Cycles Required for a Skip The instruction set of the uPD750008 is designed to organize a program by testing a condition with the skip function When a skip instruction satisfies the skip condition the immediately following instruction is skipped to execute the instruction immediately after the skipped instruction A skip requires the following number of machine cycles a When the instruction to be skipped immediately following the skip instruction is a 3 byte instruction that is the BR addr BRA addr1 CALL addr CALLA addr1 instruction 2 machine cycles b When the instruction to be skipped immediately following the skip instruction is an instruction other than the in
291. unctions as a number system conversion instruction See Section 11 1 273 uPD750008 USER S MANUAL C 2 ADDS XA n8 Function XA lt XA n8 Skip if carry n8 15 0 OOH FFH Adds the 8 bit immediate data n8 to the contents of the XA register pair in binary then skips the next instruction if the addition generates a carry The carry flag is not affected C 2 ADDS A HL Function A A HL Skip if carry Adds the data at the data memory location addressed by the HL register pair to the contents of the A register in binary then skips the next instruction if the addition generates a carry The carry flag is not affected ADDS XA rp Function XA lt Skip if carry Adds the contents of register pair rp XA HL DE BC XA HL DE BC to the contents of the XA register pair in binary then skips the next instruction if the addition generates a carry The carry flag is not affected C 2 ADDS rp 1 XA Function rp lt rp 1 XA Skip if carry Adds the contents of the XA register pair to the contents of register pair HL DE BC XA HL DE BC in binary then skips the next instruction if the addition generates a carry The carry flag is not affected Example The register pair is left shifted MOV XA rp 1 ADDS rp XA NOP C 2 ADDC A HL Function A CY lt A HL CY Adds the data at the data memory location addressed by the HL register pair toget
292. ut flip flop TOUT flip flop is inverted Figure 5 36 is a timing chart of the timer event counter The timer event counter normally begins operation in the following procedure 1 Set a count in the TMODn 2 Set the operating mode count pulse and start indication in the TMn Caution Set a value other than 00H in the modulo register TMODn When using the timer event counter output pin PTOn set the dual function pin P2n as follows 1 Clear the output latch of P2n 2 Set port 2 to the output mode 3 Make a status wherein the internal pull up resistor is not connected in port 2 4 Set the timer event counter output enable flag TOEn to 1 Figure 5 35 Configuration of Timer Event Counter INTTn IRQTn set signal TIQNete C Modulo register TMODn Comparator Internal MPX i clock Tas 5 Count register Tn aa To serial interfaceNete PTOn TOUTO TOUT flip flop Note Channel 0 of the timer event counter only Count pulse CP Modulo register TMODn Count register Tn TOUT F F CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 36 Count Operation Timing UUUUUUUUUUUUUL n DEREN foto eis Y Match Match Heset Jj C Lo 0 Timer start indication 4 Applications of the timer event counter a Timer event counter is used as an interval timer that generates interrupts at intervals of 30 ms The high order four bits of the mode register are se
293. ut flip flop are cleared to 0 by a RESET signal generation Figure 5 32 Timer Event Counter Output Enable Flag Format Address FA2H Channel 0 FAAH Channel 1 Timer event counter output enable flag W 0 Disabled 1 Enabled 5 5 2 8 bit timer event counter mode operation It is used as an 8 bit timer event counter in this mode It performs an 8 bit programmable interval timer and event counter operation channel 0 only 1 114 Register setting The following three registers and one flag are used in the 8 bit timer event counter mode Timer event counter mode register TMn Timer event counter count register Tn e Timer event counter modulo register TMODn Timer event counter output enable flag TOEn a Timer event counter mode register TMn When the 8 bit timer event counter mode is used TMn must be set as shown in Figure 5 33 For the format of the TMn see Figures 5 30 and 5 31 The TMn is manipulated by an 8 bit manipulation instruction Bit 3 is a timer start indication bit and can be manipulated bit wise and is automatically cleared to O when the timer starts The TMn is cleared to 00H when an internal reset signal is generated CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS Figure 5 33 Timer Event Counter Mode Register Setup 1 2 a In the case of timer event counter channel 0 Address 7 0 Symbol FAOH TMO 6 5 4 3 2 1 06 05 04 TMOS 02 Count pulse CP selection bi
294. utomatically cleared to 0 when interrupt processing is performed However IRQBT and IRQ4 are cleared in a different way because these flags share a vector address See Section 6 6 The following seven interrupt enable flags IExxx corresponding to the interrupt request flags are provided INTO interrupt enable flag IEO Serial interface interrupt enable flag IECSI INT1 interrupt enable flag IE1 Timer event counter interrupt enable flag IETO INT4 interrupt enable IE4 Timer counter interrupt enable flag IET1 BT interrupt enable flag IEBT An interrupt enable flag set to 1 enables the corresponding interrupt and an interrupt enable flag set to 0 disables the corresponding interrupt Whenan interrupt request flag and the interrupt enable flag are setto 1 a vectored interrupt request VRQn occurs This condition is also used to release a standby mode A bit manipulation instruction or 4 bit memory manipulation instruction is used to manipulate an interrupt request flag and interrupt enable flag A bit manipulation instruction allows direct manipulation regardless of MBE setting An interrupt enable flag can be manipulated using an EI IExxx instruction or DI IE instruction The SKTCLR instruction is usually used to test an interrupt request flag Example El IEO Enable INTO DI IE 1 Disable INT1 SKTCLR IRQCSI okip and clear IRQCSI when it is set to 1 When an interrupt request flag is set using an instruction even if
295. wever this is also applicable to the PD750004 whose program counter consists of 12 bits addr OOOOH to OFFFH the uPD750006 whose program counter consists of 13 bits addr 0000H to 17FFH and the uPD75P0016 whose program counter consists of 14 bits addr OOOOH to 3FFFH BRA Function For the uPD750008 20 lt addr1 C1 BR adar Function For the uPD750008 J PC42 9 lt addr addr 0000H 1FFFH Transfers the immediate data addr to the program counter PC then branches to the location addressed by the program counter CD BR addr Function For the PD750008 lt addr addr 15 to 1 PC 2 to PC 16 Relative branch instruction with branch ranges of 15 to 1 and 2 16 from the current address The instruction is not affected by page or block boundaries I BR Function For the PD750008 lt addr1 addr 15 to 1 PC 2 to PC 16 Relative branch instruction with branch ranges of 15 to 1 and 2 to 16 from the current address The instruction is not affected by page or block boundaries 285 uPD750008 USER S MANUAL Remark Function in this section is applicable to the uPD750008 whose program counter consists of 13 bits addr OOOOH to 1FFFH However this is also applicable to the PD750004 whose program counter consists of 12 bits addr OOOOH to OFFFH the uPD750006 whose program counter consist
296. wo wire serial I O mode 129 PD750008 USER S MANUAL 130 Figure 5 40 Format of Serial Operation Mode Register CSIM 4 4 Remarks 2 The P01 SCK pin assumes any of the following states according to the state of CSIE CSIM1 and CSIMO CSIM1 CSIMO 01 5 pin state High level output Serial clock output High level output 3 When clearing CSIE during serial transfer use the following procedure 1 Disable interrupts by clearing the interrupt enable flag IECSI lt 2 gt Clear CSIE lt 3 gt Clear the interrupt request flag IRQCSI Examples 1 fy 24 is selected as the serial clock serial interrupt IRQCSI is generated each time serial transfer is completed and serial transfer is performed in the SBI mode with the SBO pin used as the serial data bus SEL MB15 CLR1 MBE MOV XA 10001010B MOV CSIM XA CSIM 10001010B 2 Serial transfer dependent on the contents of CSIM is enabled SEL 15 CLR1 MBE CSIE CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS 2 Serial bus interface control register SBIC Figure 5 41 shows the format of the serial bus interface control register SBIC SBIC is an 8 bit register consisting of bits for controlling the serial bus and flags for indicating the states of input data from the serial bus SBIC is used mainly in the SBI mode SBIC is manipulated using a bit manipulation instruction SBIC cannot be manipulated using a 4
297. y accept pulses which are longer than one sampling clock cycle and shorter than two cycles as interrupts depending on the sampling timing seeFigure 6 4 a Thecircuitis sure to accept pulses equal to or longer than two sampling clock cycles as interrupts The INTO pin is supplied with sampling clock or fy 64 whichever is selected by bit 3 IMO3 of the INTO edge detection mode register IMO Bit 0 IMOO and bit 1 IMO1 of the INTO edge detection mode register IMO are used to select a detection edge Figure 6 6 a shows the format of IMO A 4 bit memory manipulation instruction is used to set IMO A RESET signal clears all bits to 0 and a rising edge is specified to be detected Note When the frequency of a sampling clock is these cycles are equal to 2tcy When the frequency of a sampling clock is fy 64 these cycles are equal to 128 fy Cautions 1 Inputapulse widerthan two sampling clock cycles to the INTO P10 pin Otherwise the pulse is suppressed as noise by a noise eliminator when the pin is used as a port 2 When the noise eliminator is selected IMO2 is set to 0 INTO does not operate in standby mode because INTO requires a clock for sampling Do not select the noise eliminator when using INTO to release standby mode set 02 to 1 As shown in Figure 6 4 b the INT1 circuit accepts an external interrupt at its rising or falling edge The INT1 edge detection mode register IM1 is used to select a detection edge
298. y clearing ISTO INTCSI and INT4 not allowed to be level two interrupts are disabled When INTTO allowed to be a level two interrupt occurs the level two interrupt is executed and status 1 is set to disable all interrupts When INTTO processing is completed status 0 is set again INTCSI and INT4 which have been disabled are enabled then control returns 209 uPD750008 USER S MANUAL 6 10 TEST FUNCTION 6 10 1 Test Sources The uPD750008 has two test sources INT2 provides two types of edge detection test inputs Table 6 5 Test Source Test source Internal external INT2 detection of the rising edge of the signal input to the INT2 pin or that of External the first falling edge of the signals input to KRO to KR7 INTW signal from clock timer Internal 6 10 2 Hardware to Control Test Functions 1 Test request flags test enable flags Test request flags IRQxxx are set to 1 when the corresponding test requests are issued Clear the test request flags to O with the software once the test processing has been executed Test enable flags IExxx correspond to test request flags The test enable flags enable the standby release signal when they are set to 1 They disables the standby release signal when they are set to O When both a test request flag and the corresponding test enable flag are set to 1 the standby release signal is generated Table 6 6 shows the signals which set test request flags Table 6 6 Sig
299. y following instruction is skipped 11 4 7 Compare Instructions C 2 SKE reg Zn4 Function Skip if reg 4 4 13 0 0 Skips the immediately following instruction if the contents of register reg X A H L D E B C match the 4 bit immediate data n4 C 2 SKE HL n4 Function Skip if HL n4 n4 130 Skips the immediately following instruction if the data at the data memory location addressed by the HL register pair match the 4 bit immediate data n4 C SKE A HL Function Skip if A HL Skips the immediately following instruction if the contents of the A register match the data at the data memory location addressed by the HL register pair 280 CHAPTER 11 INSTRUCTION SET C 2 SKE XA HL Function Skip if A HL and X HL 1 Skips the immediately following instruction if the contents of the A register match the data at the data memory location addressed by the HL register pair and the contents of the X register match the data at the next address in data memory However if the contents of the L register are odd numbered an address with the lowest order bit ignored 15 specified C 2 SKE A reg Function Skip if A reg Skips the immediately following instruction if the contents of the A register match the contents of register reg X AH L D E B C SKE XA rp Function Skip if XA rp Skips the immediately following instruction if the contents of the XA register pair
300. y location addressed by the HL register pair and transfers the contents of the X register to the next memory address However if the contents of the L register are odd numbered an address with the low order bit ignored is specified MOV A mem Function A mem mem 07 0 00H FFH Transfers the data at the data memory location addressed by the 8 bit immediate data mem to the A register 266 CHAPTER 11 INSTRUCTION SET C 2 MOV XA mem Function A lt mem X mem 1 Dz g 00H FEH Transfers the data the data memory location addressed by the 8 bit immediate data mem to the A register and transfers the data at the next address to the X register An even address can be specified with mem Example The data at addresses 40H and 41H are transferred to the XA register pair MOV XA 40H C 2 MOV mem A Function mem c mem 05 0 00H FFH Transfers the contents of the A register to the data memory location addressed by the 8 bit immediate data mem C 7 MOV Function mem lt A 1 X 05 0 00H FEH Transfers the contents of the A register to the data memory location addressed by the 8 bit immediate data mem and transfers the contents of the X register to the next memory address An even address can be specified with mem C 2 MOV A reg Function A reg Transfers the contents of register reg X A H L D E B C to the A register C 2 MOV XA rp Function
301. zadr n129L00dS4adrl Jauweiboid Buiurejuoo 009 4 5508 si gs oroquiAs 5 5 0086 Od ISOH wealksAs Jobe 101009 J 9 00292 31 898005 9 Z 2 SH 2 7 m 8 71080092 34 D m 004 we 27 0 eqoud 5 10 00062 91 m 305 PD750008 USER S MANUAL Drawings of the Conversion Socket EV 9200G 44 and Recommended Pattern on Boards Figure B 1 Drawings of the EV 9200G 44 Reference EV 9200G 44 GO0 306 APPENDIX B DEVELOPMENT TOOLS Figure B 2 Recommended Pattern on Boards for the EV 9200G 44 Reference EV 9200G 44 P0 Caution Dimensions of mount pad for EV 9200 and that for target device QFP may be different in some parts For the recommended mount pad dimensions for QFP refer to SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL IEI 1207 307 PD750008 USER S MANUAL MEMO 308 APPENDIX C MASKED ROM ORDERING PROCEDURE After program development is completed the masked ROM is ordered by the following procedure lt 1 gt lt 2 gt lt 3 gt lt 4 gt Advance notice of an order for masked ROM Give advance notice of masked ROM ordering to a special ag

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