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MiTAC MITAC 8050D User's Manual

Contents

1. 97108 MEMA_MDO 25 E22 MAO 26 0020 M MEMA MAT KwwDAp 63 10 MEMA_MD2 22 MEMA MD3 DaA2 MAS MEMA TAM MEMA _MD4 jpg MAAS MEMA MA4 AM MEMA MDS 8 MEMA MAS 7 10 MEMA NDS MAAS E22 MEMA MAG MEMA _DOM 0 R108 0402 VDOMA 0 MEMA MD7 DGAS MAAS E21 MEMA PAN MEMA DOMAT R93 1 amp 2 0402 MEMA NDE aan MAA MEMA XXXV ASA E 002 MEMA 9 DGAS MARS MEMA MAS MEMA R107 2 0402 VDOMAf3 poa 209 MAAS MEMA MATO MEMA DOME I3 o 0402 VDOMARA MEMA_MDit DGAIO 10 A25 MEMA MATT TAN DOMAS R729 1 amp 2 0402 MEMA DOAT MAA11 E21 MEMA MATZ AM MEMA DOMI In 3 AY Nex VDQMARE MEMA 14073 00 12 12 B2
2. m 2 5 8 DDR 1 25 DDR P 18703 716 4 1 2012 SHORT SMT4 1202 100 1 0010 0402 10 50V GND 4 799 PILI 100 1210 JP 25 4 20 X5R L 2 l Poze4 10 2675 0 010 100 796 Sov 1000 0402 1210 100 vA GND 0402 lt 10 25V 1210 GND 10 50V 20 X5Rd 25V PR109 PR110 50 1 4 88100056017 1 47 a 47 GND 0603 7 0603 GND 1 awse 0 23 H 111 PC67 515 1 x 0 T 0402 100 JP 4 x ev 404900 d 4 D SOS 1206 poss 04 Pose d 01U 82 010 PU709A 1000P 0805 50 0805 D 0402 10 PU 10 m E GE G Ek ka LTC3728L s HVQFN32_1 2 41 EI 8 gt 899554 42 515 DDR P PR742 PL715 a aj 1 5 PR744 0 4 Hix 6 sw2 HS 4 1 1 T O41 28V DDR P PU708B 27 14 0 008
3. DDR SODIMM NB 63 _ 69 2 NB MDO R10621 30 0402 MDO MDO 1 16 NB MD1 R1061 1 A 0402 MDI MD4 LANEN ANDOR NE R108591 AA 2 902 MDI 3 14 42 5VS_DDR 42 5VS_DDR Riosa 1 2 0402 05 4 18 NB MD4 910011 0402 MD4 DASO s 1 NB MDS 910001 0402 05 DMO 11 DDR_VREF DDR_VREF NB MDS R998 1 0402 10 NB MD7 R997 1 0402 _ 7 MDE a NE MDE R1087 1 AYN 2 0402 MDE MD3 1 RR 16 NE 10561 AA 2 0402 MD7 18 NB 1 810541 0402 MDE 3 14 _ 11 1053 1 ANA MDi2 4 13 MDO MDT NB 0128996 1 0402__ 12 9 5 1 MDT MDTGR995 1 0402 MDIS 013 6 11 14 993 0402_ 14 0051 10 0050 0050 0188902 1 0402 MDIS DMI 8 a MD2 MD2 NB 01881052 0402 MD16 1 RY 16 2 N
4. o 13161718 0 31 lt lt 2713 ADI7 PCLINTD m nx Dc 8 9 REQ2 GNT2 R100714 11 1 arra pus Pus 9 MINIPCI R10031 VELA 4 ian LED1_GRNN LED2 YELN 14 LOADS 18 cHSGND RESERVED4 18 P INTB 5V1 ra Mt a 810681 RA A 0402 8 Coo 18 24 TOUCHPAD 10 13 17 24 PCI_INTF 3 MINIPCLLPCDROF RESERVEDO RESERVEDS 27 910771 0402 5 MINIPCI PCIRST poIRSTE PCICLK MINIPCI 1079 1 10781 0402 5 h MINIPCI GPORESET 11 PCICLK MINIPCI gt V E RST 4 1 21 GRouND1 28 LATINA 1324 poi 2 81083 MINI 29 30 R10801 AAA 2 0402 5 1324 3 3V 1 GROUNDS 10 PCI 1 34 PCI 3V 507 PCI 29 35 0131 LPCAD DPMINIPC _PMEH 13 9
5. em NB_MONTARA GME 2 2 NB 6 4 1 35 42 5VS_DDR 9 5 mem U714E NB NB S gt NB_MDIO 63 6 T T T VCCSM 0 28 vss o vss E18 SMA 1 2 SHAT 18 1 VCCSM 1 58 1 vss 92 6 6 5 2 lt lt 09 VCC 2 VCCSM 2 55 2 vss 18 NB 5098 NE MDS VCC 3 VCCSM 3 vss 3 VSS 94 5 5 SMAS spala NE MDT VCC 4 VCCSM 4 VSS 4 VSS 95 6 SMA A 5 SMAS 500041 NE MDS VCC 5 VCCSM 5 vss 5 VSS 96 NB SMAIS 5098 NE MDE VCC 6 VCCSM 6 VSS 6 VSS 97 6 NB MAG NBCMAT SMA 6 5096 VCCSM 7 vss_7 VSS 98 6 7 NE MAS SMA 500 7 A15 voc 8 VCCSM 8 A VSS 8 VSS 99 6 NB 500 8 NE MDS VCC 9 VCCSM 9 vos 9 VSS 100 5 6 MAS NE MAIT SMA 9 5098 NE MDIO VCC 10 VCCSM 10 5 VSS 10 VSS 101 6 NB MATO NE MAIT SMA 10 spa toj NE MDTT VCCSM 1 28 vss 1 VSS 102 AAI 6 NB SMA 11 1 NE MDIZ 2 VCCSM 12 2228 vss 12 vss 103 14 6 NB 12 SMA 12 5 0 12 513 VCC 13 VCCSM 13 ADI
6. 1 2V 1 0V_M10 DVMAIN 15707 718 ld ginny s s 2012 SHORT SMT4 1202 100 an 4 4 PJLIO 04 4 Pcaoa l 804 0 10 100 100 100 RIE 50 010 1210 1210 1210 4 GND 0402 ej 25V 25 25V 10 20 20 X5R 20 XSR 50V 1000 0402 10 GND us PR72 1M GND 0402 GND H 5 EI PR100 9 1 10 0402 0725 ectoasos 4 0402 4 80 20 50 pn 16V GND PR108 S 47 0603 57 PR125 oW GND 0402 1 A 4 4 2526282931 PWRON_SUSB Abr q 4 010 PU710 a 59 5 Sis800DY 0402 PUIG 508 ej 80 20 50V BST in 41 2V 1 0V M10 2 H 4 o 3 vout ux H2 T tt VDDP sS 26006 DL 2 PL719 AGND PGND 1 15 BC DES 5 1470 82K TO 2 2UH 0402 D IHLPSOSOCE 01 4 4 9 20 78 PC79 il J 0 010 010 4 288204410010 PCB14 7343 PD726 0402 0402 330U NA av 10 80 20 7 B 50V 50V s av Post Pzvssc2va na l 3300 010 TS 7343 0402 PD727 aV 190204 EC31QS04 TE12LINA Tr DC2010 Js 4 1 4 4 4 4 SHORT SMT1 X
7. suspend then resume 1394 AVCC 1 unknow us suspend VT6307L power ay ALL Capacator must close to power IDSEL AD21 1 PCI 1 1 1 1394 AVCC C917 9 e 3VS 9 PCI GNT1 1 OU 1743 9 1746 9 i 0402 1c name 3 i 4 4 5 PCI 1 n 80 20 21 1 1202 100 1202100 E a al a 50 C923 C922 C925 2012 sl 2012 C931 C954 C924 C916 0 1U 0 1U 0 1U avs C921 010 010 010 0402 0402 0402 9 1742 Fi E 0402 0402 0402 0402 480 204 280 204 80 20 80 20 1 C955 80 20 80 294 50 50 50 1202 100 0805 1739 220 50 2012 1202 100 80 20 0402 ac d 0805 80 20 GND Ne GND 50v d GND 13164719 AD O 31 i 4 ADI gaS AD2 22222555 SES 555 888 PHYPC2 83 AD3 999 SSS gt 56 ADA gt gt 82 ADS R1112 ADG AD7 12CEEENA 48 _ 1 43V ADB I2CFAST 48 ADS AD10 CARDBUSENA 42 ADI ADI2 013 25 ADI4 XTPAOP 22 1 6307 ADS 21 TPB 5307 AD16 ADI7 4 d AD18 1 80x AD19 1 29 bs uan AD20 X
8. REVISION TAPEOUT DAY HISTORY PCI DEVICE INTERRUPT REQ GNT IDSEL 2003 8 26 LAN PCL PCI ADIS 8050D R01 PCLGNT3 ROA 2003 10 09 1 CHANGE CARDBUS CARD READER CONTROLLER FROM CARDBUS PCLINTB PCLREQO AD20 Hoppe TR PROJECT CODE G113 PCB P N 316680900001 SENI 2 USE 1 94 CONTROLLER VT6307 INSTEAD OF PRODUCT CODE 6827 ASSY P N 411682700001 IEEE1394 PCLINTG PCLREQI AD21 896322 PAGE 1 TITLE PELGNTM 3 ADD SPDIF FUNCTION M i ss cometon rom 3 NT SIDE TO SOLDER SIDE PAGE 4 NB MONTARA GME 1 2 5 CHANGE MDC AND CONNECTORS PLACEMENT FROM PAGE 5 NB MONTARA GME 2 2 SOLDER SIDE TO COMPONENT SIDE PAGE 6 DDR DIMM EMI 7 10 1 4 TP44 TP46 PAGE 8 VGA M10 2 4 TES ET zod3712797 i TOUCHPAD METAL10 TOUCHPAD METAL10 TOUCHPAD_METAL10 TOUCHPAD METAL10 3 11 0 PAGE 9 10 3 4 TOUGHPADSMETAR 10 10 4 4 4 4 4 TOUCHPAD_METAL10 TOUCHPAD METAL10 CLOCK SYNTHERIZER TV ENCODER ROL 2003 12 16 1 EXCHANGE TV CONNECTOR PIN 6 AND PIN 7 PAGE12 CRT LCD M A Mx e 342672400007 342672400007 2 CONSUMPTION SAVING CIRCUIT BUT RESERVE PAGEI3 SOU
9. 129 8 13 Mini PCI Test gt 42 131 8 14 Card Bus amp Reader Test 133 8 15 IEEE1394 Test Failure 44 5 29 135 9 Spare Parts List soo Wee 137 10 System Exploded ene 148 IH Circuit Diagram EUR VE EN VF d exa ETE 149 I2 Reference Material co ope eere Kee MUI Qui kso nu des mere PEDE ee Fra coe sea pQU Tal vales es 183 80500 N B Maintenance 1 Engineer Hardware Specification 1 1 Introduce The MiTAC 8050D model is designed for Intel Banias processor with 400MHz FSB with Micro FCPGA package It can support Banias 1 5G 1 9GHz Dothan 2 0GHz and above This system is based on PCI architecture and is fully compatible with IBM PC AT specification which has standard hardware peripheral interface The
10. PQ707 4407 PF703 PL708 8 PL710 PL709 PD713 From chapter 8 1 1 TR 3216FF 3A BEAD 1202 100 i 33UH 3 0UH EC31QS04 Reference chapter 8 1 1 ADINP LVN ES VYY gt gt G PR87 215 P 9 75 n PD714 PD709 1000 JOK EC31QS04 2 55 15 PR89 PR86 0 100K PR74 13 7K PQI3 V V DTA144WK PR76 249K PDS e AN e BAS32L PQ14 From 1 16 12 26 2 7002 27002 CHARGING gt 11 8 V V P33 12 16 21N 21IN PR78 13 10 R483 0 ICTRL 0 PR79 124K 2 PU7 TL594C U16 15 BATT_DEAD WINBOND KB DVMAIN VDD5 c Reference chapter 8 1 2 78 PR69 PROS PR70 77 100K 590K 3 3K E sarr 5 1257 2 EE 039 8 56 DEAD 7 4 DTC144TKA 6 4 111 PUS 7 LMV393M 4 SCK431LCSK 5 PC36 PR63 PC33 0 010 80 6K 0 1U 80500 N B Maintenance 8 3 No Display There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known good No Display Monitor or LCD module OK Board level Troubleshooting Make sure that CPU module Replace monitor or LCD DIMM memory are installed P ly PODER Replace Motherboard Using debug card depending on the error codes to make sure which parts maybe faulty 1
11. PF703 PL708 PL708 0713 12 65 1 12 _ La 14 1 5 1 K 32 ADINP gt o N o wean 32 TR 3216FF 3A 08050 0310504 al 4 3 0UH DC2010 PC747 PC748 PC745 L 756 1 758 gt PD709 oni 0010 0010 100 100 0010 30 0402 0402 1210 1210 0402 1 1 RLZ20C NA 4 1 10 25V 25V 19 PR75 MLL34B PD714 20K 1000P 0402 EC310S04 0402 01 2222 062010 sov 288202222019 7 1 GND PR76 1 PR74 gt 249K 137K amp 0402 4 PREG BAS32L 0402 1 0 0 1 1206 5 M 1 1 DTA144WK PC49 1 0 01U NA 0402 E 50 J Para 80 20 Put IS SOT 1 1 oPENsMTA 22 CHARGING PUT MN E1 Ci e 2 GND 4 1 4 22 CHARGING lt 1402 RT 6 1 PRES 12 vec er o t 1 13 4 0402 12 REF FEEDBACK T 1 5 2 16 214 T 2IN 9010 GND 594 0402 5016 1 T 80 20 PC46 PR83 10 100K 1000 7 5 0805 0402 0402 0402 PR79 i ill 4 tov 5 lt 10 5 124K 50V 0402 1 q 1 0 010 2 0402 PR22 10K 50V 1 1 0402 80 20 ii T 1 PCAA PR81 02 ill 1 2512 REF 4 44 4 6 19K PR77 0402 0402 2 49K GND GNoB 0402 16 0402 50 10 1 80 20
12. 112 8 5 Memory Test Error 114 8 6 Keyboard Touch pad Test Error 24 4 25 4 249205 6 116 8 7 USB Port Test 66 118 8 8 Hard Disk Drive Test e eee eee se Re 120 8 9 CD ROM Test Error 6 66 006 6 006 122 8 10 Audio Test Failure cce ee cerea eee eee ehe 124 8 11 LAN Test Error e eee ee uto sees eese 127 8 12 Modem Test
13. uss CardBus amp s me 9 SHORT SMT4 CB710 CARD GND C1 187 IDSEL AD20 Reader CB710 mm PCI 0 Kaoz PCI GNTO CARD_VCC T e R1189 154 PCI 3V 43 2K 930 1 INTC VPPDI 0402 0402 VPPDO 10 SHORT SMT4 16V GND JS8 V7 CARD PCIRST Ri1901 73 NE GND 1 as 04 GND CADO 1 35 58 CCD1 SF SHORT SI 4 312 36 CAD2 c4 GND 3 aoa 0727 CCLKRUN CAD3 213 37 Tag CADS 5 t 52 39 CADS 5 58858858822 5 8989888858325 858 EM COSE 84 CADE 99999999900 222222222205 2 lol 252525225296 gt 555555555525 CADS 817 4 CADIO lo gt SX CADIT 9 42 43 CVS1 4SD MSVDD CADIZ 10 2 44 CADIS 13 16 18 19 PCIADp 31 Hin 45 HS SE ADO SD SD_PWREN CPAR 12 46 a R2 AB SD_PWREN 91191 5 CPERRE 14 18 47 CBLOCKF SO_CLKIN SD 040 CGNT 15 14 48 ag CSTOPH AD3 SD SD VPPOUT CINTA 16115 49 50 CDEVSELF AD4 SD_CMD SD WPF 18 116 so 20 ADS SD_WP SDCDF 12117 51 ro 06 SD CDf w14 50 18 18 52 CTRDY i H AGT SD_LED Twas SDO coss coss 19 53 54 CFRAMEF ADB SD DATO 501 0 2 11120 54 55 CAD17 AD9 80 DAT wig SD2 0402 0402 CADIS 21 55 56 CADIS AD10 SD_DAT2 303 10 10 CAD20 22 56 CVS
14. ITP R87i 1 49 9 NA 0402 FS2 FSi FSO 3V66 5 01 HOLK CPU 893 71 499 0402 j MCH amp R891 1 499 0402 x 0 0 166 66 66 66 33 33 CPU RB70 1 49 9 NA_ 040 001 x 0 100 00 66 66 33 33 CPU R892 1 499 0402 h MCH R890 71 499 0402 x 1 200 00 66 66 33 33 C834 1 0402 TOPINA 50V 71 1 133 33 56 66 33 33 Layout note Place crystal within C838 1 0402 SEG TOPINA 50V 71 50 5 Mid o Tristate Tristate Tristate CEDE Ben C830 1 0402 alg M 7 50V 10 0 1 TCLK 2 TCLK 2 TCLK 2 9712 R895 2 23 10402 5 SIO 48M 19 3V 3VCLKCPU mia o Reservea Reserved Reserved 3 use He fend SSUSECLCIOH 14 Tus wow i i eserve eserved Reserved eda Despre tte 1 1 p Mid T Reserved Reserved Reserved 4 DEFSSCLK 50 ox GND 4 4 4 0804 1 _ 5 28 spata R859 1 A 3 _2 pace 14 CODEC 20 cazo _1_ 19 1 239 0207 He 4 40 20 secik 1 14M ICH 18 oiu 220 1 3 3V 0402 TXC8X4 040p 858 33 0402 5 0402 0402 0603 5 5 FS0 54 10 10 4 10 FSi 65 52 R861 1 0400 ITP CPU 1 RBj 0402 5 FSZ 40 FS GPUCLKTO 8872 33 1 0402 HCLK OMA eee
15. CPU_THRMDA CPU_THRMDC LCD PANEL 816 484 CLK ITP CPU 100MHZ XGA HCLK CPU 100MHZ CPU DEBUG CARD ONLY INTEL LVDS 552 ic Shawnie BANIAS DOTHANB ____ ___ ___ ______ NH CLOCK GENERATOR HOST BATT Adapter 1 5950810 14M CODEC one RGB D D Power CRT LTC3728L ea eee 25 1 25 9D 100MHZ North Bridge 0 0 EHE ERI _ LTC3734 DREFCLK_48MHZ MAX4173F DIMM1 DIMMO crk 2 1 _ ACD 4 D D Power CLK_DDR1 A LTC3728L CLK_DDRO VGA M10 CH7011 C3728 3V 5V CLK_DDR3 SUE I LIMIT CLK_DDR4 S CLK_DDR5 Prose m L DDR 266 1 5V 1 05V 66 0 0 Power D D Power 66M_ICH 66MHZ SC1470 LTC3728L USBCLK ICH 48MH7 penaz MUS CDROM 1 2V 1 0V 1 8V 1 35V PCICLK_ICH 33 USB 0 2 AC Adapter 14M ICH Sourth Bridge x3 16 4 D D m SECONDARY IDE SIE 4 HDD Ble PRIMARY IDE NS 14M_CODEC CLK GEN 97 no d La o 5 ADT7460 LPC BUS 5 24 576 2 25MHZ AUDIO PETOLE RTL8100CL MDC CODEC n MODULE 5 ALC655 wa H NK PH163112 PCMCIA AMPLIFIER Keyboard BIOS 1394 CARD READER H H SYSTEM CP2211 TPA0212 WINBOND EXT LINE BIOS VIA MIC IN W83L950D VT6307L
16. veri 3 2855 2 0554 ADD R798 DEL R857 R1104 57 6872 512 57 1 HD 32 teas 1 menma DVOCDH js 855_DVOCDS ae Be 2 10 35 OE ivgprs DVOCDIS E INODE 57 GREQ 57 HREQ 4 HD 339 HDif34 ICLKAM _ pi4 DVOCDIS H1 855 DVOCD7 123 35 TCLKAP CLKAM DVOCDI7 H4 855 DVOCDS 2 HADSTB O D22 0836 o i DVOCDIB H4 855 DVOCDS 2 5 1 7 TP30 1 Fig DVOCDISI 855 DVOCDiO E24 HD 38 0402 DVOCD 0 G3 855 855 MDDCCLK 0402 R2 i AS HXRCOMP B20 HOD D24 HD 39 y 1 DVOGDII 1 855 MDDCCDATA 04021 1 HXSWING Big HD 40 ay oc 90 7 855 DVODETECT R832 855 040 1 HXSWING 40 41 1 een VOVREF GCLKIN DVODETEGT 0402 1 40 855 MDVIDATA 0402 1 HYSWING HYRCOMP 42 7 Heda UEF DVORGOMP 855 DVOCFLDSTL dne HYSWING 823 HDf43 0402 855 855 2 0402 RINJ 2 10 5 44 2 HDSTBP 0 3 lt lt 14 HUB_HI 0 10 855 DVOCHSYNC voci 1 2 16
17. DESCRIPTION disable add in rom card decode PCI return config and no video look for PCI bridge device search IDE controllers on the PCI bus start of cardbus config Enable Verify R W Status Runtime Data Get Verrify R W Stattus NVRAM data area Resolve System Nodes with the CMOS settings Init var in the PNP BIOS Runtime Data area copy setup PnP Install Check in 0000 seg Allow the OEM any Last Minute Hooks Write protect RTData Area amp NVRAM Copy Buffer return from pnp init proc 97 80500 N B Maintenance 8 Trouble Shooting 1 8 1 No Power 8 2 Battery Can not Be Charged EL 8 3 No Display 8 4 External Monitor No Display 1 8 5 Memory Test Error L 8 6 Keyboard Touch pad Test Error L 8 7 USB Port Test Error 8 8 Hard Disk Drive Test Error 8 9 CD ROM Driver Test Error 8 10 Audio Failure 8 11 LAN Test Error 8 12 Modem Test Error 8 13 MINI PCI Test Error 8 14 Card Bus amp Reader Test Error 8 15 IEEE 1394 Failure 98 80500 N B Maintenance 8 1 No Power When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up P32 P32 Pas Q13 Pas 1 1 PD702 UII PLI PL2 701 n70 F3 U13 Pos Q5LL71 Pos 06 Pos 701 PD704 VDD3 VDD3S VDD1 5 Q43 P2 Pos PD703 JS711 JS713 JS71 17707 0701 1746 ADINP gt Dv
18. Mere 100 100 100 100 100 100 100 M 0805 0805 0805 0805 0805 0805 0805 VCCP 12 VSS 158 VSS 14 VSS 87 EE Ec EE env EE Ec Sov VCCP 13 VSS 159 VSS 15 VSS 8B VCCP 14 VSS 160 VSS 16 VSS 88 15 VSS 161 1H 5 17 VSS 90 16 VSS 162 VSS 18 55 91 4 4 17 VSS_163 Z 85 19 VSS 92 E ig Er EUR Erg 18 VSS 164 VSS 20 VSS 93 US QUE pun ME VCCP 19 VSS 165 55 21 VSS 94 SN ENV SN EV VCCP 20 VSS 166 5 vss 22 VSS 95 D cc c VCCP 21 VSS 167 8 vss 23 VSS 98 VCCP 22 VSS 168 1 vss 24 VSS 87 WZ LI 408 VCCP 23 VSS 169 VSS 25 VSS 98 ab VCCP 24 VSS 170 VSS 26 VSS 99 Mec ORE VSS 171 VSS 27 100 VSS 172 Z vss 28 VSS 101 Fa D 18 Tou TOU 1 1 1 1 cose VSS 175 55 31 VSS 104 D 0805 0805 100 100 100 100 100 17 VSS 32 63V 63V 0805 osos osos osos 0805 VCCA2 VSS 177 BIZ vss 33 VSS 106 1 gl EN CN CN VSS 178 019 vss 34 vSS 107 126 VSS 179 VSS 35 VSS 108 VSS 180 D23 ves 36 vss 109 8 VSS 110 T 1 1 L cies ype MERI cu eed MER 100 100 100 100 tou 100 100 8 0805 0805 0805 0805 0805 0805 0805 4 184 VSS 40 55 118 63V 63V 63V 63V 63V 63V 63V 31 4 VIDS VSS 185 041 vss 41 VSS 114 2 a a VS
19. TXIM AGP8X_DET TXIP TM anded for RASET GND RESET Teka 11 SCN tuna c if TXCP E ATEDELUMA e ATI TV A2 9 GND 3V E 11 ATI TV B DDC2CLK 2 13 H2SYNG DDC2DATA 14 gt 24 V2SYNC 4 8 FL 1 T DCN iot 0402 5 1711 R765 fee ATL RED 1202100 8 2K 9 DDC3DATA CRT RED 12 E ATI CRT GREEN RED 12 2012 ode B BLUE 12 E i i BIO 1A A 2 0402 ssi HSYNC ATLCRT HSYNC 12 b J J J 1 p 0402 25 1 VSYNC ATLCRT VSYNG 12 C123 c110 1 c128 L H26 R764 1 Jl J J 0 T I qr ge 1 Al H28 B6 TU OU E 4 diim ARR Test HS 1 dioz T Bite 23 X R774 NA 2 0402 0402 48020 10 R776 LARA A429 xrALOUT 5 10v 16V DDC1DATA Lars g CRT DDDA 12 uni DDC1CLK 12 040736 R102 E 109 SUS_STAT AUXWIN 428 LA 2 o 8V 2 MODOUT osc SPREAD AGP T 4 JP 10K 0402 5 5 B 27 2 C774 0603 770 7 R777 R101 p 508 GND 0608 40 4 0402 10 6 4 10 1 10 20K 16V 50V T L oz L ot L ou
20. 1 02 1 02 10 GPIO2 R738 1 20 0402 R120 M10 GPIO11 1 02 Mi0_GPIOT2 0402 35 100 6737 1 IKA 2 0402 M10 GPIOS 1 424 AGP ADS U710A Mi0 GPIOS AGP ADO H29 M10_GPIO0 ADT 00 GPIOO Ahs M0 GPIOT M10 GPIO3 R734 1 2064 2 0402 i VREF LAM M10 GPIOZ a M10 GPIOS R110 cus 4 ADS gios M10_GPIO4 315 R733 1 IKA 2 0402 1 02K C149 10U ADS Gros M10 GPIOS 0402 9 Ali Mi0 GPIOS 1 0010 E AGP AD GPIOS Mi0_GPIO7 wz For MEM_ID 7 lt 0402 10 Nee 07 Aa 0_6 8 U703A sav AGP ADI 08 10 9 9 AO Ao pa 109 gt swiss m ___ ADIZ MI0 GPIO12 867 1 KNA 2 0402 NT ADI3 ADI2 GPIO12 Fag Mi0 GPIO13 7AAHCIA V GND 21 AGP ADi4 ADS GPIO13 GPIO14 55 14 NC Tan ADIS A014 GPIQ4 ars GND 015 GPIO15 H ADIS N OSC SPREAD ADIT a A018 IDA 25 AFB E E 019 20 0402 AD20 LCDDATAO 34 PANEL 100 121424 UCET 8 AD22 ZV LCDDATA2 jAK PANEL 102 121424 1 e
21. 75 5 3 Intel 82801 IDBM I O Controller Hub 4 Mobile ICH4 M South Bridge 84 6 System Block 92 7 Maintenance Diagnostics 93 FN MIDI TS DTE TII ITI 93 12 Debu RE REDE EP DE EISE NE 94 7 3 Error 22 95 80500 N B Maintenance Contents 5 Trouble Shooting eI CE M UM ERE EFE 98 8 1 No Power 99 8 2 Battery Can not Be Charged eese 104 8 3 No Display 585822 0000 106 8 4 External Monitor Display e
22. S 10 10 10 GND R831 ve 50 sov 50 50 10K 42 _1 3VCLKANA 0402 8 IREF 9 5 1722 1 2_1202 100 160 GND oe 4 T i 284595081201 0402 4 4 4 4 4 31 CORE_CLKEN CAN 0402 5 1 caos cso9 cet 1 010 010 220 ARA 66 DEFSSCLK 4 owe do PCIOK 1394 8828 1 33 2 0402 i 18 10 10 10 4 10 KBC_R817 0402 1 TEE 1 aue ome ome 22 GNO 4 RB20 0 0402 5 30P NA 10 10 WHEN USE INTEGRATE VGA R887 NA 0402 0402 0402 1 109 10 10 3 13 91 STOP amp pagg 0402 5 af 50 50V of 50v 1 _PCI_STOP 13 STOP C urs 0402 5 GND GND GND TV ENCODER bi Rea 9 TV 3 0805 DVOVREF R807 10K NA i 0402 u2 11 4 Place near 3 San gt DVOCDO 1 4 DVOVREF VREF B Sy S 010 5 to 7011 4 MI2CCLK 8 gg 988 8 Dit 4 DVOCCLK 22 222 8 E 8 2702 288 COM eT 4 DVOCCLK SS ODER Wb 0 sav 2N7002 NA 4 4 4 DVOCHSYNG 5 0 5 288227002006 Bl GND a sy 75INAS 7 855 TV bid E 0402 0402 952 1 855 LUMA 3 R53 9 5 5 5 T vie DIS amp 2KNA R68 3
23. 42012 p Hae a BID dads 13 17 18 19 PCI PAR 2 par NC 8 i 7 mus 1317181924 PCI_PERR 0 PERRB m eu y 0402 2 voae 1 1 56 Tall 1 NU RE CM 58 Se7e 0o dooocoooo px NC g 18 PJRX MDO2 415 1741819 0292002200 22222222 202222 bet 3 18 LAN_PCIRST PCIRSTE 2626220022 55555555 2525555 PMD a PIRE 1 3 sl 1 4212 4 RTLB100CL 1 R107 PQFPIZBA 0 500 E SMS n MODEMP 20 nni Crystal should be placed JENA x PMD 19 c MEM MODEMN 1 2 8712 far away from I O port and E nurum peg anor cup Tx Rx power magnetics ADD if use RTL8110S oe GND2 GND 0010 2 DAC 4 1 MCT2 0402 TI 7 LAN XTAL1 GND NU i PMDI3 MDO3 Coo ee NE Jor17 JO716 JO715 40714 LAN XTAL2 MDO3 LAN XTAL2 Bidet GND 45 GND 45 0010 2 DAC 1 2 MCTI 0402 d 4 4 4 R943 0402 1 AVDDL V DAC m H5007 NA 6 Add thease caps when H500x t use RTL8110S and 77 25MHZ 4 0805 879 change to 0 010 GND 45 cara 5 915 27 274012500415 P Add AVDDL to V DAC when 002 change to RTL81108 L719 o 9 3VS 0603 777 pmpio 7 Thy PJTXI GND 45
24. we ET x SDATA_OUT Interface i REXT2 RNG 100 RNG2 Interface GPIOB A QEZ PCT303A PCT303W 1 3 9 IEEE1394 VT6307L Option 1 3 9 1 Overview The VT6307 IEEE 1394 OHCI Host Controller provides high performance serial connectivity It implements the Link and Phy layers for IEEE 1394 1995 High Performance Serial Bus specification release 1 0 and 1394a 2000 It is compliant with 1394 Open HCI 1 0 and 1 1 with DMA engine support for high performance data transfer via a 32 bit bus master PCI host bus interface The VT6307 supports 100 200 and 400 M bit sec transmission via an 25 80500 N B Maintenance integrated 2 port PHY The VT6307 services two types of data packets asynchronous and isochronous real time The 1394 link core performs arbitration requesting packet generation and checking and bus cycle master operations It also has root node capability and performs retry operations The VT6307 is ready to provide industry standard IEEE 1394 peripheral connections for desktop and mobile PC platforms Support for the VT6307 is built into Microsoft Windows 98 Windows ME Windows 2000 and Windows XP 1 3 9 2 Features gt 32 bit CRC generator and checker for receive and transmit data gt On chip isochronous and asynchronous receive and transmit FIFOs for packets 2K for general receive plus 2K for isochronous transmit plus 2K for asynchronous transmit 8 isochronous transmit conte
25. 1 402 2 8 2KINA fi 02 855 ADDIDi 330NA 1 0402 2 HENRY pg BNR 100 855 DDCK DDCADATR AC15 8 2KNA 9105040 855 ADDIDZ 330NA 1 0402 2 HBPRI BPRI 0402 pape DDCACLK RCVENOUT 8 2KINA RIS dino 852 ADDIDS 330A 1 0402 2 DBSY Y22 HAVREF 380 204 480 208 80 20 1 9 BY Sos DDCPCLK 8 2K NA EIAS 855 ADDID4 330 NA 1 0402 Pomme SM HCCVREF 50V 50V 50V 8 2K NA 917040 855 ADDIDS 330NA 1 0402 NOH EUM 1 5V 8 2KINA RIP dino 892 ADDIDS 390A 1 0402 615 f __855 RED 2 ucpurste V a CPURST RED 145002 855 ADDIT IKNA 1 2 0402 lt R PUREE Maximum length less than 855 GREEN cal Net 855GM GME 1 0 5 f R59 GND 0 5 from pin to voltage pem D8 GREEN NC 3 b divider News A28 recommend 002 i A 2X 1K ohm DVOVREF 855 HSYNC H10 7 resistor 355 VSYNC 48 vsvNG 9 42 135 ov 888 2 Rt 2 o opersscuK Rcoue BXRCOMP 8 HYRCOMP should be 4 W SSC s DEL ALL RESISTOR route with 18 mil width 28 TEN ui EE i 12 855 CRT Dopa KSSS ORT DODA R331 1 0402 _ 855 DDDA IYAPO R350 1 0402 0402 n 374 CHANGE TO 0402 i CHANGE 2 855 qe 855 DDCK R1166 0402
26. O45VS P 012 40UH 59000 PL702 2010 D124C T RUNES RUNS Se 40UH 012 1 20 5 Pd p NC SEA E D124C 2010 1 508 j SENSE1 SENSE2 20 1 Pona SENSE 10 719 Io 32 8 2 Pu7o1B 72 150U NA 1500 p l M SOSENGES Poo 100 FTS 7343 4 x 7343 i 2 ls 508 1210 6 3V PD708 63V 25 5 2 11 PD707 pers 5 21 z lt 010 10001 20 ScND4 2338 z 8 BZV55B5V6 NA 4 0402 0402 senos gt 5 0402 PC725 ej 80 20 ej 10 480 20 1500 L 150U NA 50 50 Hoed ajid ded 4 50V 1 7343 gt 7343 1000P BND 63V 6 3V 0402 Pete 50 1 SENSESV m SENSEB 10 PR35 11 1 SENSESV 1 4 1000 1 25 0402 i 2524 1809 107K 50V t 4 1 1 4 0402 pios 0402 vs PRA2 PR46 0402 10 1 63 4K 2K 10 50V 02 GND oso2 0402 5 1 PRS V R41 2001 2008 0402 0402 PR36 10 402 1 1 19 8 sov q 4 0402 1 4 4 GND PR48 SGNDO PRA7 10K 0402 0402 5 En 1 kpe 19 aN7o02 PQ4 2N7002 4 005 d o 005 al NZ PRQ sGNDO 56 00 100K 0402 1 247002 2N7002 PR28 1 2226 H8 PWRON gt 0405 PWRON 22 26 eon lt 13 22 26 O TU NA 0402 80 20 50V SGNDO Title 8050D MOTHER B D PCB 316680900001 ASSY 411682700001 lumber Date Wedne
27. qna pu rx R922 GND b 5 R436 RSTDRVI RSTDRV2 J708 43 E 5 07 42142 Prey 20 CDROM LEFT S 3 2 H GDROM RIGHT Koprom RIGHT 20 4 D 0 15 i10KNA 5 40 39 PODIO R919 20 CDROM_COMM RSTDAV2 5 3 par SD 08 Z D4 FEES PD Dii 10KINA gt R927 A SD D7 B 5 50 09 GND 5 03 34 36 a PD Diz 0402 0402 5 SD D6 9 10 SD Dio PD D2 34 83 PD Di3 5 14 50 210 151 50 05 1119 10 4 SD Dii 30122 3 29 _014 50 04 1 11 12 4 50 012 PD 00 B a PD Dis R909 SD D3 1 18 16 SD Di3 PDDREQ djs 25 9 88 SD DIS 4 18 0 24 23 0402 9 20 81085 1424 _ IDERST 5 50 20 1420 22 2 E PIORDY 18120 19 1 705 SDIOW 23 24 56 16118 17155 144 SIORDY 25 26 SDDACK 18014 14116 15 470 5 NA TROIS 27 28 30 ziu HOG 0402 GND SDAT S 1 TP706 10112 111 PDA2 SDAO ajl 32 34 552 B 10 5 PDCSSF SDCSTF 35 21 n SDCS3F 23 HDD LEDE lt 5 23 co Lens 5010 3738 38 45V HDD 4 sp O45V HDD pi 40 4 0 8V_CDROM T E R476 5V_CDROM a eM 44 10k R836 46 HDR FMI22PX2 2MM 0402 a 1 ar 7 AcETAZ026 57 D Qai ME 0402 GND 288202240001 SPEED PCIRST O 13 25 PCIRST 0 gt DTC144TKA 45V 288202240001 SDDREO 4 SDDREQ PDDREQ 8295 1 6 D 00 1 45V
28. gt SI 5 e S oo gt gt ci c yai aE 9 CAP 33U 10 10 0603 X7R SMT CAP 1U_ CR 16V 10 0603 X7R SM 17 272072104402 CAP 1U_ CR 16V 10 0603 X7R SM 27207222340 27207282440 0220 16 10 0603 X7R SMT 06 C117 C120 C128 C132 C13 0820 16V 10 0603 X7R SMT CR25V 1095 0603 X7R PR C22 C7 272105104701 10 16V 80 20 0402 SMT C1000 C102 C103 C104 C105 C10 27207310440 27207322340 27207510140 C 50V 10 0603 COG SMT 20 C21 257 10 0603 X7R S o 9 7 7 6 13 272105181403 CAP 180P 50V 1095 0402 SMT PC24 PC25 PC61 PC63 PC738 272105220402 CAP 22P 50 10 0402 0 5 C447 C450 C765 C766 C855 C861 gt gt gt gt ex e gt 5 5 5 QO gt gt 5 6 20 86 ES gt gt 272075101404 27207510340 2010 CR 50V 10 0603 7 C13 C8 27207510340 2010 CR 50V 10 0603 X7R S 11 3 272075103408 CAP 0 1U CR 50V 10 0603 X7R S 10 11 12 15 3 5 06 7 8 272105221403 220 CR 50V 10 0402 7 5 165 1 73 734 75 272105222501 CAP 2200P 50V 20 0402 X7R S 470 494 509 728 869 CR SOV 10 0603 XTR 272105103702 010 50 80 20 0402 5 272105270303 CAP 27P 50 5 0
29. Apos 2v LODDATAS 1 PANELID3 12 14 24 nuu AD25 w26 4028 By LODDATA 4 J J SW_HDS402 AGP 26 W25 025 IV LODDATAR C734 C733 C68 27 O OTUINA O 01U NA O OTUINA O 01U NA AD28 ADSL ZV LCDDATA 0402 0402 0402 0402 AD28 ZV LCDDATAB 80 20 80 20 80 20 80 20 7 11 2412 7913 29 G 20 80 20 20 80 20 OP ADIO AD29 ZV LCDDATAS Ax 507 ov tov tov Pl 1 5 0 0 64M Samsung K4D263238E GL36 1 0 Psa Reservd AS AGP OBEND S 2 SUBEN EV TODDATATS 19 xX Infineon 250128323 13 6 Av ieoDATAIS 1 0 Reserved 64M EtroTech EM6A9320B1 3 6M 4 1 2 22 R778 1 a 52 0402 ue 1 078 LLL 0802 LT 80V xli SA LEDDATAIT d 0 1 Reserve 64 Hynix ee ee ae 1 630 aca RT 1 39 Av gis a Ga 2 AER B7B 1 0402 T 2 41284 EtroTech H230904RAT309A 13 ATLPCIRST 0202 5 928 ZV LCDDATA19 url 0402 5 REQ ZV_LCDDATA20 3V 026 R405 ZVIT 5 AGP_GNT GNT ZV_LCDDATA2t x 2 94 M25 R406 2 12 R72 R79 PAR 25 ZV LCDDATA22 Pus A NIS y 221K 4 STOP ZV_LCDDATA23 ES 4 AGP_DEVSEL DEVSEL T 9 9 98 4 AGP_TRDY
30. l vende yoa 4 20 80 20 BV 100 RH SM VDDC 26 VDDRI 5 4 20 4 80 20 04 380204 GB 0805 0402 0402 55 18 55 94 VDDC 27 VDDRi d 6 3V 480 20 480 2091 5519 55 95 10 50V 50 VSS 20 VSS_96 VDDC 29 VDDR1 8 cb Ee y vss 22 VDDC 30 VDDR1_9 VDDC 31 VDDR1 10 1 if Bi J T Mrs IR VDDC 32 VDDRI 11 2012 Ci27 29 55 100 VDDC 33 VDDRI1 12 100 010 040 TRA VSS 101 VDDC 34 VDDRI 13 0 1U 0805 0402 0402 VSS_26 VSS_102 NODO IS 0402 _ M 63V 480204 80 20 VSS 27 VSS 103 1802 10 50V 50V VSS 28 VSS 104 BEEN VDDC 37 VDDRI1 16 1 1555 1 2 1 0 VDDC 38 VDDR1 17 1v VSS 106 VDDC 38 VODR1_18 on am B J 1 Wem VSS 107 9 VDDC 40 VDDR1 19 C138 C136 VSS_108 Tonni a VDD MEM IO 100 oou VSS 33 VSS 109 VDDC15 0 VDDR1 21 0805 0402 0402 55_34 35 110 VDDCIS 1 VODR1_22 63V 480208 480 205 VSS 35 85 111 1 10 50V 50 3 1 55 36 VSS 112 VDDCI5 3 VDDRI 24 1000P oou oiy Di2 55 37 5313 1202 100 VDDCi5 4 VDDR1 25 1 20 Me 04 100 pis 55 38 14 2012 Pa j E 1992 0803 Di amp 55 39 VSS 115 VDDC15 6 VDDRI 27 Say p D21 VSS 40 vss 116 VDDCIS 7 VDDR1 28 GND Ves 0 wae am ciso C140 WSs 42 VSS_118 1 30 1 1 T 9 C97 cna 1 VDDR1 31 1000P 0 01U
31. 1 63 4K NA 0402 Pust 5 PR78 gt 8 seco did SHORT SMT3 0402 VDD5 DVMAIN 9 9 PR7O 3 3K H 0402 PRES 5 590K 0402 1 155 5 DEAD 22 Patt T 8 56 4 LMV393M SCK431LCSK 5 M SSoP8 6 PRES 0010 SOT23N 010 80 6K 0402 0402 0402 10 80 20 5 50V 50 of n 4 4 GND GND 80500 MOTHER B D 316680900001 ASSY 411682700001 lumber Date Wednesday December 31 2003 33 o 34 1 PDF created with FinePrint pdfFactory trial version http www fineprint com 5 3 VGA_THRMDA VGA_THRMDC 8050 BLOCK DIAGRAM
32. PMDI2 MDI3 PMDI3 X pu ae ee 2 5VS_DDR when 10 10 10 10 ADI use RIL8110S 16 16 16 16 S 1 50 8 8 8 50 4 4 ADM 1517 7 7 7 x 2 11 1 4avs AVDDH AD16 equal length i 1736 9 rb LAN_XTAL1 3 Not to use via 20Z 10 1 20Z 109W NA 20Z 109W NA 018 25200 i 25200 ORE _ 25200 4 AD20 XrAL2 122 1202 100M NA C890 por PMDIO PMD __ PMDI2 PMDIS 2012 0 1U NA AD22 ADD if use RTL8110S gage gage e R304 0603 R297 0603 R278 0603 R263 0603 16 16 ADD if use RTL8110S 25 CTALI8 t AD26 NC 13 co AD27 CTRL25 168 AD28 ik AD29 RSET NAA 8 Deno AD30 4 pr Change to 2 49K when 13171849 PCI_C BE 0 3 gt 81181105 CBEB2 LEpo P 5 TE 2 LED 113 LEDS 11 PCICLK LAN PCICLK NC 14 1 13 17 1924 PCLKRUN S81 CLKRUNB gt lt 1317181924 PCI DEVSEL 90 88 DEVSELB 1317181924 90 81 Frames It S NA when gt lt 1 1_sone dias 30 181105 DVDD Use H1285 for RTL8100C 1 20720 E PCI AD18 Rs ACAD 0402 46 ipse NC 1511 L735 7 5 1324 PCI INTER INTAB AVDD25 Hi 1 aiei d sd gt 131718 19 24 PCI_IRDY 8 Z2 4 J709 13171819 24 PCI_TRDY
33. SC PWRSEN pig SC PWR3ENF 1 402 NS Vee VCODOR SC_PWRGEN ADONA 0402 R1198 VCCD1 SC BI 3V SD_CLK1 4 SD_CLK n 5610 poe A T 11 PCICLK CARD A10 SC_RST 0402 20 CARDSPK 815 SPKROUT SC_CD 5 ieee 13 CARDBUS lt 51500 RI SC TED 1322 23 25 SUSB gt CARD POIRSTE SUSPEND SC 0 Mo 13 CARD PCIRST PRST 5 5 13 24 PCLGNTo 55 SC C4 X SV 1324 5 cr 5 PWRENE 2716 13 16 18 19 24 PCI FRAME MS_PWREN Luig Msaki _ 13 16 18 19 24 PCL_IRDY IRDY MS_SCLK MS CKI 1 AA 1 se 13 16 18 19 24_PCLTRDY 6 82 trpv MS_CLKIN WS BS DES 5 GND 402 gt 4 0 ND 13 16 18 19 24_PCI_DEVSEL lt lt 7 pevse Ms E i 5 q SD CLK 500 E Fr Rig MS_LEDR _ Ll cess 13 16 18 19 24 PCI STOP MS_LED MS INSE E 557 2 I SD7 131681924 PCI_PERR 8 Perry 12 Teo Mo 503 rm 1 MS BS 13161924 PCLSERR 46 B SERRI BLL 5 5DI0 5 ME SDIG 13618 9 PAR 0 06 PAR X SV 1 sp MSVDD 13464819 C BERO 46 ao BEI Eres 13161819 PCI 1 lt A GPios 17 10 x 7 18161819 90 108 GPiog 918 lt a
34. VRMPWRGD signals DPSLP Deeper Sleep This signal is asserted by the ICH4 to the processor When the signal is low the processor enters the Deeper Sleep state by gating off the processor Core clock inside the processor When the signal is high default the processor is not in the Deeper Sleep state This signal behaves identically to the STP_CPU signal but at the processor voltage level SMBus Interface Signals Signal Name Type Description SMBDATA VOD SMBus Data External pull up is required SMBCLK VOD SMBus Clock External pull up is required SMBALERT I SMBus Alert This signal is used to wake the system or generate GPIO 11 SME If not used for SMBALERTH it can be used as a System Management Interface Signals Signal Name Type Description INTRUDER Intruder Detect Can be set to disable system if box detected open This signal s status is readable so it can be used like a GPI if the Intruder Detection is not needed SMLINK 1 0 VOD System Management Link SMBus link to optional external system management ASIC or LAN controller External pull ups are required Note that SMLINK 0 corresponds to an SMBus Clock signal and corresponds to an SMBus Data signal Real Time Clock Interface Signals Signal Name Type Description RTCX1 Special Crystal Input 1 This signal is connected to the 32 768 kHz crystal RTC
35. MEMA MD38 Eig MEMA WE MEMA MAS VMAS MEMA_MD39 DGAse WEM VMAS MEMA _MD40 017 DOAS9 E20 MEMA 50 AM MEMA MAS VMAS DQMO MAT MAT MEMA MD42 E20 MEMA 51 MEMA MAS VMAS MEMA_MD43 09442 VCKEA MEMA MD44 Cia 20443 Big AM ae MEMA_MD45 EKER 14046 MEMA CLKO R761 1 40 5 2 0402 VCLKAO RY _ 47 29448 c20 MEMACLROAR7S9 1 209 2 0402 veikan g Veto ii MEMA MD48 49 DOME MEMA CLKi R757 1 20 5 2 0402 VCLKA1 DOA49 aka oo EE VCLKAT 10 MEMA MOST NENA CURTERTSS a 2 0402 AER RN MEMA_CAS BRI a VCASA 052 DQAS 0 MEMA_RAS VRASAF SS VCASA 10 MEMA MD53 0 52 DIMA 0 Bia DIMA 2508 amp VCSAR VRASA 10 MEMA_MD54 DQA53 DIMA 1 MEMA WEF 5 VWEAF SS 10 MEMA MDS DQAS4 VWEA 10 MEMA MD56 810 09455 ES 00456 PLLTEST BE28 i o _ 58 8787 5 E Basse RSTB MSK Lore GND R DIMAO R89 2 0402 0 60 AGA 45 1 1 2 0402 DIMA 1 8746 1 0402 VOIMA 1 VREFG A 943 MEMA CSIF R80 1 0402 M 15 3 Eg 62 DVOVMODE D 1 0402 Dew Danes DMINUS THERMDC AM DPLUS THERMDA 22 B26 R98 1 5 DBL LO NAE j OAGP_VDDQ R97 1 5 MOBILITY M10 P 02028
36. 148 PDF created with FinePrint pdfFactory trial version http www fineprint com G H s PART NO DESCRIPTION Q TY TYPE REMARK 322680900001 CABLE 8050 PART 2 340680900002 SPEAKER ASSY L 8050 ASSEMBLY 3 340680900003 SPEAKER ASSY R 8050 ASSEMBLY 4 340680900004 COVER ASSY 8050 ASSEMBLY 5 340680900005 HOUSING ASSY 8050 ASSEMBLY 6 340680900006 BRACKET ASSY SYSTEM 8050 ASSEMBLY 1 340680900008 SHIELDING ASSY COVER 8050 ASSEMBLY 8 340680900009 BRACKET ASSY TP 8050 ASSEMBLY 9 340680900010 COVER ASSY HDD 8050 ASSEMBLY 0 340680900029 COVER ASSY MINIPCI 8050 ASSEMBLY AI 340680900034 SPEAKER ASSY WOOFER NEW 8050 ASSEMBLY AI 340680900035 HEATSI ASSY DESCRETE UNP 8050 ASSEMBLY 13 340683400029 HEATS ASSY NORTHBRIDGE 8050F ASSEMBLY 4 341671000002 SPRING SCREW HEATSINK LYNX 3 PART 5 341680900001 SPC SCREW 4 1 4 8050 2 PARI d 6 342683400005 SPRING HEATSINK VGA 8050F PART 1 344680900009 COVER REAR R 8050 PART 8 344680900010 COVER REAR L 8050 PART 9 344680900011 COVER 8050 PART 20 344680900015 COVER CPU 8050 PART 21 344680900016 COVER DDR 8050 ARI 22 344680900048 DUMMY CARD PCMCIA 8050 PART 23 344680900049 COVER HINGE L 8050 PART 24 370102010303 SPC SCREW M2L3 NIW K HD NYLO 4 PART 25 310102010409 5 5 2 4 K HD t0 3 NIB NL 4 26 310102010607 SPC SCREW M2L6 K HD NIW NLK H 2 PART 3 21 31010203030 SPC SCRE
37. 100K Poli MMBT3904L ae 2 5VS_DDR PR50 PRI9 13 3K 15 100P 28 5 R251 220K us IM o 229 2N7002 5 7 28 0 257002 3300 e 285 56 2 8 PUI5 PWRON_SUSB 13M 9 DIC V V e 28 499K 11 10 RUN SS 17 12 7 gt To Pin12 111 80500 N B Maintenance 8 4 External Monitor No Display There is no display or picture abnormal on CRT monitor but LCD can normally display External Monitor No Display Board level Troubleshooting Check if J702 are cold solder 1 Confirm monitor is good and check the cable are connected properly Re soldering 2 Try another known good monitor Check following parts and signals Display OK Replace faulty monitor Parts Signals Replace Motherboard CRT INZ DDCK DDDA HSYNC VCYNC RED GREEN BLUE 112 80500 N B Maintenance 8 4 External Monitor No Display There is no display or picture abnormal on CRT monitor but LCD can normally display 7 0710 ATI 10 5V_H R6 4 7K 112 257002 1202 100 ATI CRT DDCK p CHAGND GND 43V L gs ATI CRT DDDA R138 0 25 R804 8 2K 15 113 ig P13 BEAD_600Z 100M 5 _ y CRT IN Y Y R9 IK 5 9 gt gt 0715 P12 b ICH LH x 1202 100 ATI_CR
38. 10161 0402 MD48 MD35 1 16 NB_MD4SR1017 4 0402 049 14039 RAN 15 1 1 1 0058 DOSE NE 0581015 2 0402 MOBO MD40 73 14 1 1 caso l case 8 051810161 0402 MDB MD44 4 13 610 01U 1 2 6402 DBE MD41 5 1 0402 0402 0402 0402 MCB3 MCBS 0402 MD53 MD45 6 11 480 204 480 208 480 208 80 20 CKET ST 0402 MD54 DOSS 10 50V 50V 50v 50V MDSEROSS 1 0402 MD5S DMS a a CLK DDRZ CLK DDRS MDSERIO13 0402 MD56 MD42 1 RN 16 CLK DDR2F CLK 0102 0057 MDa HY CKEZ MDSERTOT01 0402 MD56 3 14 8 059910091 0402__ 59 MD47 774 13 CS 0 ST NE MDSGE2 1 2 0402 MD48 5 12 12 NB MAIZ NB MAT MDSSSD 1 20402 NB MAS NB NB 0628949 1 0402 062 NB 0638948 1 AA 0402 MD63 m RE MAT NE MAS NB 00510 71 1 25 DDR 5 2 NB 5 2 NB_Das o 7 0402 DOSO 9 SMAT 5 1 NB MAG 0402 DOS 0402 DOSZ NB MATO NB BAT 0402 0953 RAST NB NB RASE 0402 DOS4 WEF NB WEF NB_CAS 0055 0402 0055 0580 05 5 2 D NB DOSS RI0161 0402 DOSE NB 0057 810111 AA 0402 0057 11652 11655 NB_DM 0_7 MD33 MD37 MD33 MD37 NB_DM 0 7 27 NB DMO R999 1 10 0402 cce Eu m d NB DMZ R989 1 0402 DMZ NB DM3 R984 1 NB DM4 Rags 4 AY 2 0402 DN 11655 11655 11035 MD3S NB
39. 441680900031 LCD ASSY SAMSUNGXGA ISAPLTNIS ener BATT ASY 441681700002 BATT 441681700003 BATT ASSY IV44ABLICOREPA 441681710031 CONTACT PLATE ASY WAL2TTOISFU 442672600031 AC ADPT ASSY I9V3 16ADELTA06 442680900051 TOUCHPAD MODULE SYNAPTICSTMA2PU 147 365350000003 370102010409 370102010607 SPC SCREW M2L6 K HD NIW NLK H 370102030301 SPC SCREW M2L3 K HD 1 NIB 370102010502 SPC SCREW M2 LS NIB K HD t0 8 NL 370102610603 SPC SCREW M2 6L6 K HD NIB 370102610603 SPC SCREW M2 6L6 K HD NIB 370102610401 SPC SCREW M2 6L4 K HD t0 8 LK LK IB N LK LK 370103010405 373101712351 411680900019 370102611601 SPC SCREW M2 6 L16 NIB K HD 2n HE 370102030301 SPC SCREW M2L3 K HD 1 NIB N SY 80500 N B Maintenance 9 Spare Part List 12 T 015 016 680900002 F W ASSY KBD CTRL 8050 523430061010 COMBO DRIVE 24X10X8X24 SBW 2 523468090029 ASSY SBW 242B QSI 8050 526268270004 LTX 8050DA SACB 40H 9UI9 A5D3A X 531020237777 KBD 88 UI K011818A1 8050 BK 600100010009 SOLDER WIRE 63 37 0 8 CM N C PRC 600100010009 SOLDER WIRE 63 37 0 8 CM N C PRC 624200010140 LABEL 5 20 BLANK COMMON 523468090002 HDD ASSY 40GB MHT2040AT FUJIT SU 600100010009 SOLDER WIRE 63 37 0 8 CM N C PRC 523402379038 HD DRIVE 40GB 2 5 MHT2040AT 4
40. 655 is a 16 bit full duplex AC 97 2 3 compatible six channels audio CODEC designed for PC multimedia systems including host soft audio and AMR CNR based designs The ALC655 incorporates proprietary converter technology to meet performance requirements on PC99 2001 systems The ALC655 CODEC provides three pairs of stereo outputs with 5 Bitvolume controls a mono output and multiple stereo and mono inputs along with flexible mixing gain and mute functions to provide a complete integrated audio solution for PCs The digital interface circuitry of the ALC655 CODEC operates from a 3 3V power supply for use in notebook and PC applications The ALC655 integrates 5 0mW 20ohm headset audio amplifiers at Front Out and Surr Out built in 14 318M 24 576MHz PLL and generator those can save BOM costs The ALC655also supports the S PDIF input and output function which can offer easy connection of PCs to consumer electronic products such as AC3 decoder speaker and mini disk devices ALC655 supports host soft audio from Intel ICHx chipsets as well as audio controller based VIA SIS ALI AMD nVIDIA ATI chipset Bundled Windows series drivers Win XP ME 2000 98 NT EAX Direct Sound 3D I3DL2 A3D compatible sound effect utilities supporting Karaoke 26 kind of environment sound emulation 10 band equalizer HRTF 3D positional audio and Sensaura 3D optional provide an excellent entertainment package and game experience for PC users Besides ALC655
41. 8 0704 V 2 2 SB_PME Ad 0 34 5 x m 39 R895 33 SIO 48M R1137 0 121 U712 25 R816 33 PCICLK_MINIPCI R1079 0 ICS950810 133 80500 N B Maintenance 8 14 CardBus amp Reader Test Error An error occurs when a PC card device is installed 3V w R1201 E 1199 10K 2 5 EN 1 R180 E R212 hs R231 aa 2 20 1202 100 VCC3_EN 2 4CARD 17 51 PCI AD 0 31 VPPDO VPPDO VPPOUT 18 52 PCI_DEVSEL PCI_IRDY 5 VPPD1 14 PCLKRUN PCI FRAME amp PCI TRDY PCI PERR VPPDI U728 P17 e PCI GNTOR U715 P17 52211 PCI_REQO PCI_SERR SERIRQ R1121 16 ICH4 M R1129 8 SUSB R1200 4 7K U727 5 6 5V 10 09 J6 8 JL7 CARD PCIRST 9 PCI_C BE 0 3 CCBE O 3 7 1221 61 710 34 CCD2 CCD1 amp 36 67 PX2 1 CAD 0 31 2 63 27MM s 12 R826 33 PCICLK CARD CVS 1 2 43 57 0712 R2 A18 R2 02 R2 Di4 473240 1 5950810 CBLOCK CSTOP CDEVSEL 48 50 CPAR CGNT CTRDY 13 15 53 2027 29 iioi Z ae 1 Sere CSERR CAUDIO CSTSCHG 59 62 63 P17 2 14 6 SDCD _ SD WPK 50 CPERR CINT CIRD
42. J4 Touch pad Module Connector J5 Internal Key board Connector lt J6 PCMCIA Card Connector J7 Internal Right Speaker Connector sw4 15 SW2 Power Button 1 SW4 Button Switch of Touch pad J4 SUE lt SWS Right Button Switch of Touch pad 66 80500 N B Maintenance 3 Definition amp Location of Connectors Switches 3 2 Mother Board B 11706 T PJ701 AC Adaptor Connector J702 J704 J709 4 17017706 USB Port Connector 1702 CRT Connector nn ooo J701 701 J703 Battery Connector 4 1704 External VGA Connector J705 Internal Subwoofer Speaker 3 T 1707 FAN Connector 1708 CD ROM IDE Connector 17709 RJ45 amp Connector J710 RTC Battery Connector J711 amp J712 DDR SO DIMM Module Socket 4 J713 Mini PCI Connector T 4 1714 Hard Disk Driver Connector J705 P 67 80500 N B Maintenance 3 Definition amp Location of Connectors Switches 3 2 Mother Board B M 1 Continue From Previous Page 171587717 Modem Daughter Board Connector 7716 SD amp MS Card Socket nn ooo 4 J718 IEEE 1394 Connector 4 719 External Micro Phone Jack 4 J720 Line Out HP OPT Jack 4 J721 External Line in Jack 68 80500 N B Maintenance 4 Definition amp Locat
43. lt 747 j ds Ow aV BAWSGINA GND ACES 032 1 87151 1207 p P 291000141204 8 lt 0402 A R554 1 ORA 2 5 R465 0402 D33 When 8050N ADD J722 and DEL J4 1222 2 CL 190G When 8050 ADD 74 and DEL 7722 4 S 1222 BATT R R466 1 0402 1 8467 1 0402 OVDD3S 2 2207 19 225RVGC TR8 NA 5 R420 22 ing 0402 043V IDE LED 034 CL 190G R421 CAPE LApA2 102 A R556 1 2 5 8426 0402 035 22 SA 20402 CL 1906 R429 RRI 2 scmous SPOe iA 0402 BSS7 1 RA 2 5 D37 m err 1 0402 CL 190G R457 43VS 43VS 35 LED 0402 R468 12 BATT PoweRgg BATL POWER 1 a 2 0402 0720 PS pen 7 AHCIA V 74AHCIA V 7 AHCIA V 128520221900 TSSOP14 TSSOP14 TSSOP14 EAM 4 a 5 8 1 0404 22 BATT LED gt R1303 470 rie 0805 12 22 AC_POWER gt do 8050D MOTHER B D 316680900001 ASSY 411682700001 Rot j lumber R1140 180K 0402 5 Date Wednesday December 31 2002 Bhet 23 o 34 T PDF created with FinePrint pdfFactory trial version http www fineprint com 2 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K 8 2K PCI PULL HIGH INTA INTB INTC INTD INTE INTF INTG LOCK
44. 0402 0402 0402 0402 0402 0402 0402 0 0 0 i 1 0 1 612 190011 0 10 10 10 10 10 10 10 tev 5 167 8 0 1 1 1 1 596 1 9 01 0 0 1 0 0 0 1 580 1 0 1 0 0 0 1 068 D 8 0 1 864 1 8 1 8 0 1 12052 4 zt T zT i T T m 1 ca19 1 c181 l 2 71 casa 71 c182 1 242 71 c194 2 cioe 0 0 1 0 1 1 548 1 0 1 0 1 1 036 oU 010 020 0402 0402 0402 0402 0402 0402 0402 0402 0402 0 0 1 0 1 1 532 2 72020 10 10 10 10 10 10 10 10 10 5 5 vos S ups di tev T6V TV tev TeV te TeV Tb 167 0 0 1 1 0 0 1 516 1 0 1 1 0 0 1 004 5 GND 0 1 1 0 1 1 500 1 0 1 1 0 i 0 988 i 4 0 0 1 1 1 0 1 484 1 01 1 1 0 0 972 15 ans R400 E 1OK NA 9 0 0 1 1 1 1 1 468 I9 1 1 T 0 95 T id vega H 0 1 0 0 1 452 1 1 0 0 0 0 0 940 R401 a28 1 4 0768 1 4 3 1500 c231 6258 1 0 0 1 436 1 1 0 0 0 i 0 924 TRER 1202 100 C237 c201 C265 7343 100 100 H 014 GND H 2012 100 010 010 6 3V 0805 0805 0 1 0 0 1 0 1 420 1 1 0 0 1 0 0 908 1 0805 0402 0402 63V 63 62V 10 10 01001 1 1 404 11001 1 892 16 dev 045 BATS4 NA DEA 000 12988 TIESSEN 11 14 31 STOP_CPU 2 2N7002NA eb SNP DEC Wm n 1 1 0 1 0 i 0 860 0 1 0 i1 1 0 1 356 1 1 0 1 1 0 0 844 i GND 3 0 1 0 1 1 1 1 340 1 1
45. 10K cars RM 5 d 7532 0402 0402 100 4 R1150 0402 50728 5 10 1210 4 16V 80 20 30V 8452 caer ZL 10 166 VL 4 0 010 2200P 1202 100 0402 0402 AGND 1741 i 0402 2012 5 80 20 1 20 50V 1202 100 gt 50V CORE ACM2S20U Y CAGND AGND 4 GND AGND 4 2719 BEAD 6002 100 R1151 R1154 R1153 INT 187 1 06030 i AVDD 1 VREF 1 1 MIC EXT T 402 5 Ty T E 4 0402 4 911551 21 C968 C938 5 ACBITCLK 1744 0402 0402 0603 28J SB2014D3 80 20 80 20 6002 100 CAGND JACK 82014 50 50 80 20 291000920605 AGND AGND AGND ITE AGND Em men C974 LINE IN 1 0402 10V 80 20 22 0402 1 55 ss 224 C960 1 1U LINE IN R SPARKGAP 6 0402 10V 80 20 Rit57 AGND ACRST 1 C975 10 1 14 ACRST 99 ACSDOUT 0402 30V 80 20 m V 402 777 ESDOB0SA NA 1 ACSDINO 5 0 1 22 8 MIC2 117 AGND 06038 0805 CA ND 14 ACSDINO S ACSYNC 0402 TE SDATA IN mice lt lt 10V 339 805 14 ACSYNC 2 SYNC T DEF rar sc rrr m R88 1 Bircik 22 1 dU Q4 8547 1 6 8K 0402 5 CDROM RIGHT 15 S C507 1 10 UE p P538 4 6 8K 0402 5 CDROM LEFT KEDROM LEFT 15 FOR EMI REQUEST CHANGE TO 0 XTLIN 173 L88 R472 19 C515 0 220 8550
46. al 1 THEM CLK 1 TE S2SVINISMBALERT P TCO10 PSS11CET Kie 1 a SZ XR 297004010001 1 4 A amp CPU THERMDA 2 o _ VDD3 720 18 ewig H 2200P ome tt e E 120 7K 8 5 1 PWMe SMBALERT D1 H2 at ex SE THERMDO 2 PWM3 ADDRESS ENABLE 02 Hi T D THERMDA 9 C728 TP7i8 24007 T HER TACHI GND 4 S 4 20 THERMDC 9 MiTAC TP719 i A 5 50V 1425 _ lt TACHA ADDRESS SELECT THERM Title ADT 7460 lt 80 20 80500 MOTHER QSOP16B TE Sr 316680900001 ASSY 411682700001 Rot nb Number Date Wednesday December 31 2003 Bheet 22 of 34 1 PDF created with FinePrint pdfFactory trial version http www fineprint com 3 25 z I TOUCH_PAD 11 PCICLK FWH 13 FWH_PCIRST 25V R387 1 2 5 2 0402 71 ceo d 902 1716 F701 INE 010 0603 0402 0402 GND 63V
47. core well inputs This power may be shut off in 53 54 55 or G3 states HIREF Analog Input Expected voltages are 0 9 for HI 1 0 Normal Hub Interface Series Termination 350 mV for HI 1 5 Enhanced Hub Interface Parallel Termination This power is shut off in S3 S4 S5 and G3 states VCCSUS3 3 3 3 V supply for resume well I O buffers This power is not expected to be shut off unless the main battery is removed or completely drained and AC power is not available VCCSUSI 5 1 5 V supply for resume well logic This power is not expected to be shut off unless the main battery is removed or completely drained and AC power is not available VSREF SUS VCCLAN3 3 Reference for 5 V tolerance on resume well inputs This power is not expected to be shut off unless the main battery is removed or completely drained and AC power is not available 3 3 V supply for LAN Connect interface buffers This is a separate power plane that may or may not be powered in S3 S5 states depending upon the presence or absence of AC power and network connectivity This plane must be on in S0 and S1 M VCCLANI 5 1 5 V supply for LAN Controller logic This is a separate power plane that may or may not be powered in 53 55 states depending upon the presence or absence of AC power and network connectivity This plane must be on in 50 and 51 VCCRTC VCCPLL 3 3 V can drop to 2 0 V min in G3 state supply for the
48. 1 057 i i i MCH PSWING 855 MIZCCLK R162 0402 t i 855 MI2CDATA Hii 0402 di 2 i i i i E 855 DVOCFLDSTL 8150 1 ORE dd R910 855 DVOCHSYNC R125 1 0402 n i i 8793 i 100 855_DVOCVSYNC R157 1 0402 ENNS di 301 0402 i i i 0402 i 1 855_DVOCDO R146 0402DVOCDO 4 4 1 855 DVOCD1 111 1 0402DVOCD1 DVOCD 0 11 3 11 i HAVREF HCCVREF i i HXSWING HYSWING i 855 DVOCD2 1121 04020 0 02 855 DVOCD3 R126 1 0402DVOCD3 i i i J i GND 855_DVOCD4 R127 1 0402DVOCD4 1 i i R791 i 855 5 R148 04020 0 05 i S 855 R129 1 0402DVOCDG ER i i i 0402 0402 i REFSET 1 RAM 2 R163 855 DVOCD7 149 1 0402DVOCD7 5 e 802090 1 855 DVOCDS 8130 1 0402 07 0605 gt 50V 855 DVOCDS 8115 1 0402DVOCDS i i i i 855 0 010 R131 1 04020 0 010 7 855 DVOCD1 116 1 0402DVOCD11 8050D MOTHER BID i i GND GND E ize lev i 316680900001 ASSY 411682700001 Rot i i lumber _ Date Wednesday December 31 2003 Bheet 4 o 34 I 3 I T PDF created with FinePrint pdfFactory trial version http www fineprint com
49. 1755 6002 100 Connector AGND lt g 4 LOUT e L14 600Z 100M U524 HDR MA 2 9 LOUT 116 NVN 600 100 J3 _ J 155 y 6002 100 Q 2 AUDIO AMP C474 C489 1757 LED 2 474 1000 1 1000 600Z 100M F 5 R329 22 L80 VV 600Z 100M UY 7 0212 GND R528 22 L78_ Y Y _600Z 100M 1758 3V 600Z 100M GPIFD310TP 45V 9 Q711 DTA144WK DECT_HP R1158 DEVICE DECT OPT REMARK 10K R1185 Dis 10K 0 0 HP in BAWS6 i gt OPTIN 5 0 1 OPT in VA 1 0 No this condition 713 VDD3S 9 1 1 From Previous Page 0726 90 R906 rom Frevious l age 4 10K 0 D22 DEVICE EAPD BATS4C Q38 R477 a R905 P13 D SHUTDOWN 13 i e DEVICE_DECT ve Q23 0715 gt DTCIA4TKA M 027 D19 R445 0 KBC_MUTE gt RLS4148 V lt RLS4148 160 Va 019 C471 _ 1000 LMV822 R1122 2 1K From Previous Page U726 T io 3e 5 17 1125 2464_VREF zu RLS4148 0 5 P21 C496 0 220 502 8 2K gt 1 5 R26 0 Subwoofer 15 224K SUB OUTR P21 Speaker SUB gt 0150 R479 2H lt 8 R27 0 E p w Connector R510 22 1K 5 0725 HDR MA 2 TP 2 022U R496 A 82K 4 LMAS71 163 1207100 C490 0 150 R509 22 1K 6 SUB_OUTL SUB LEFT E 126 80500 N B Maintenance 8 11 LAN Test Error An error occurs when a LAN de
50. 4 amp 1 291000152603 Ute 0402 0 6 80 300 GP51 INT20 S0 CHa 5 12 18 mo lt 1 1 on 13923 LAD 3 M 69 501 GP47 SRDY1W S1 SSHs_PWRON 2627 14 6 82 502 H C94 R439 H8_HRCIN GP83 SD3 218439 1 9 A2 Ej oan msc 1 TRA 020 m 13 KBC_PCIRST PS 9 A2 4 Gpagisps prorsine T DATA 28 2590022001 d 13 923 LFRAMER lt 584 GPB7ISD7 P71 SQUT2 PWHBIN 1 1 SW GP72 SCLK2 L __ d 3707 era 3V LEVEL 25 SW 003 K BATT DEADF GP50 A0 GP7a SRDY2HINT21 8 SEK 23 in DUE d 021 A 52148 ADENE 18 GP52 INT30 R GP74 INT31 5 KH8_PWRON_SUSB 25 51930105 8020 0402 2532 ADEN gt LEARNING 4 GP53 INT40 W GP75 INT41 13 26 27 50V 5 LEARNING 5058 GPA2 INTO OBFOO H8 THRM m H8 SCi GP43 INT1 OBFO1 GP20 FDO LPCEN H8 WAKE UPF SUSB BV GPAG SCLKTOBF1 2 1 BATI GE ima Ii 9 GP22 FD2 SDA1 RXD1 12 10MIL GP23 FD3 SCL1 TXD1 1223 85205 0300 4 P s GP24 FD4 CAPE KEXTSMI 13 24 281000010303 57 ROS GP25 FD5 23 5 19 10K H8 ENABKL GP2SIFDG a SCHOLLE 5 hem 12 H8 ENABKL E CHARGI
51. ADES PCLADT apie 88 13161748 ADU 3 Tog ADG 81095 1 2 0402 5 PCI ADS 91 33 31 PCI AD4 ADISI AD A PCI AD2 PCI Ablo PCI Svo RESERVED wiPalo 98 A 20 2 0402 PD 1 ano 0 RESERVED WiPa r 200 lt DTC144TKA MINIPCI LPCADO asv o 1 18 GROUND14 502 4 288202240001 108 AC SYNC 104 x105 AC SDATA AC SDATA OUT 106 x L WIRELESS PD 14 24 107 AC CODEC 100 108 lt 108 AC CODEC 101 _ 10 lt oma 1 AUDIO MON RESERVED 0402 AUDIO GNDO GROUND15 4 4 40 1015 sys AUDIO OUT SYS AUDIO IN Htx gt HZ SYS_AUDIO_OUT_GND SYS_AUDIO_IN_GND PI 1 AUDIO GNDi AUDIO GND2 121 1 122 nous Res c amp MINIPCI 14 24 x 123 VCCSVA 3 8VAUXIT GND1 9501 1 291000251246 4 81096 1 0402 5 LPCADO SPEED B27 101 0038 cse 132223 LADI EE 040 PIN24 124 AUX_POWER Ran i 3 R1088 0402 5 80 20 13 22 23 LAD3 4 thy 81075 1 MINIPCI_LPCDRO X R18 1 0402 5 MINIPCI PCISERIRG GND R1091 1 0402 5 MINIPCI LPCFRAMER cb E prr 1137 1 0402 5 MINIPCI SIO4EM
52. BGAG44 64 1 VMDB O 63 U710C KVMDB 0 63 10 MEMB_MDO 1 B MEMB MD1 MABO M1 MEMB MEMB AM VMDBT MEMB MD2 post tee Ma MEMB MAZ MEMB MDZ 3 VMDB2 MEMB MD3 a MEMB MEMB 4 0083 15 MEMB MD4 1 MEMB MD5 MEMB MAS MEMB MD5 AN 5 7 10 MEMB MDS DQB5 5 MEMB MD6 3 6 MEMB_DOM 0 R40 04020 VDOMB 0 MEMB MD7 0988 MEMB MD7 4 VMDB7 MEMB R29 0402 1 MEMB MDE 0087 MAB7 MEMB MEMB 1 RN VMDBS MEMB DOM Z R38 1 0402 VDOMB 2 MEMB MDS n med MEMB MAS _ 9 VMDBS MEMB R35 0402 VDQMB 3 MEMB MD10 MEMB MATO MEMB 3 VMDB10 MEMB DOM 4 R724 0402 VDOMB 4 MEMB_MD11 09810 10 MEMB MD11 4 11 VDQMB 5 12 00811 11 MEMB MAT2 _ 12 1 RN VMDBTZ MEMB DOMIS R722 MEMB MDi3 12 pa MEMB MATS MEMB_MD13 VMDB13 MEMB_DOM 7 KVOSB 7 10 MEMB _MD14 P2 MEMB MD14 AM 4 MEMB MDi5 DUBIE _ 15 i 5 MEMB QSA0 R4i 1 244522 0402 VOSBO 8 _ 16 29815 MEMB DOM 0 MEMB_MD16 1 16 MEMB QSAi R30 1 ioe VOSBI _ 17 MEMB DOMFi MEMB_MD17 XV VMDB17 MEMB QSA2 R39 1 RASTETA VOSB2 MEMB MD18 pam7 j5 MEMB DOMP _ 18 3 VMDBTE MEMB Q
53. LCDIDO LCD_IDT 165152 PANEL 0 0 1 caso caso 1 0 1 0010 1000P 0402 0402 0 1 1 80 20 4 20 T o7 2 Sov 0 1 0 T ic DVMAIN 2012 1202 100M 480 2095 lt 80 20 50v 50 Ho 18 1 2012 1 1202100 t 2 ENABKL VGA C 1101 1202 100 3 eval S R16 BLADJO RB 04027 19 1 2 1608 4 FI 422 BLADJ gt pe A 120271008 a 1 2 o N o Bav aoe n 7 FPVEDEN R22 2A 0805 R370 4 FPVDEN gt FUSE 1206 80 20 9 gt 0402 1200HM 100MHZ uj 5 1 273000610025 5 5148350 2223 1 Bi f ENAVDD XA aY 898 2223 elo Iu MI IEEE UR iy ACES WHEN USE INTEGRATE 5 iv 1 87213 1100 ADD R22 1 t20z 100M ENABKL VGA 1 MN a ENABKL VGA C DEL R20 LI Q4 GND DTC144TKAINA 1 288202240001 ids TU R323 0402 gt 280204 1202 100 0402 10 2012 0 NE n R383 i 1 22 ENABKL EMAK When inverter use 5 ADD t To SB Q4 R398 R399 R4 and DEL R323 5 102 71424 WHEN USE INTEGRATE 7 1424 PANEL 0 7 n ADD R384 0402 38 aav Swi When inverter use 3V ADD R323 I m 1 71424 9 over Switch DEL R386 5 and DEL Q4 R398 R399 R4 TX 3 m PANEL IDO D2 4 TXCLK 4 1 17 4 ENABKL NB 384 1 a
54. t 049 SUSB E R476 Jor Ts Convert to 3V 041 S DTCI44TKA R909 pH Q37 U9A DTCIA44TKA d _ 113 Pine 25 8 ez 5 E RSTDRV2 7AAHCOS V o PN PCIRST 5 92 1394 PCIRST amp JLI Em 0724 3 i 1394 V V T6307L P17 4 yes e 5 2115 8 727 CARD_PCIRST JL7 5 pig qs 3 Sz 26 JL8 25 4 BZ a 35 46 LAN PCIRST P23 or JL9 1 2 FWH_PCIRST 015 4 8 BIOS P11 74AHCO8 V SST49LFOO4A b U2 4 13 TV_PCIRST JL10 TV CARD CH7011A P4 5 U714 NORTH BRIDGE 855GM GME P2 P3 U713 BANIAS HCPURST gt HPWRGD 22 016 64 4 WINBOND KBC m 27 0719 Controller RTL8100CL 108 8 3 Display 3 0710 10 80500 Maintenance Controller Checking _ 2 n R120 1 02 AGP VDDQ R16 1 ae 2A Say C146 C149 R110 10U 0 010 1 00K e Q9 4 SI4835DY mem R140 47K 3 RI9 G R104 10K gt Qu name R752 0 ENAVDD R20 0 Ca m
55. 2 Make sure all the drivers are installed lt Troubleshooting properly Yes Correct it No Try another known good speaker CD ROM Re test OK No Check following parts and signals Parts Signals 18 ROUT AMP_LEFT 17 ROUT AMP_RIGHT SBSPKR SUB_LEFT CARDSPK 0 RIGHT PC_BEEP AMP_SHUTDOWN AVDD ROUT ACRST ROUT ACSDOUT LOUT ACSDINO LOUT ACBITCLK 14M_CODEC MIC_VREF 2464_VREF U U U U U U U U Replace Motherboard Replace the faulty parts 124 80500 N B Maintenance 8 10 Audio Failure Audio Codec There is trouble with the sound from speaker or completely no sound 45V J719 EXTERNAL MIC JACK INTERNAL P20 P20 U18 22 017 2 x 0715 1734 BEAD 600Z 100M 2 OUT vcc A E SBSPKR R1150 0 Y SND 4 2 C458 010 CARDSPK Gs E D R1155 0 1 5205 5 NC7832 10 2 BEAD 600Z 100M PU LA R438 4 C467 10K U727 0 01U 1 66 CARD LIL L744 2 12024100M READER BEAD 6002 100 6456 710 1U 19 21 C975 10 R1157 0 227 43 9 2 20 J721 PC_BEEP 8535 0 R1154 4 7K R1153 0 Line
56. 64MB 8 Meg x 64 H 128MB 16 Meg x 64 H and 256MB 32 Meg x 64 HD 512MB 64 Meg x 64 HD VDD VDDQ 42 5V 40 2V VDDSPD 2 2V to 5 5V 2 5V SSTL 2 compatible Commands entered on each positive CK edge 28 ON WV 80500 N B Maintenance DQS edge aligned with data for READs center aligned with data for WRITEs Internal pipelined double data rate DDR architecture two data accesses per clock cycle Bidirectional data strobe DQS transmitted received with data i e source synchronous data capture Differential clock inputs CK and can be multiple clocks CK0 CK0 CK1 CK 12 etc Four internal device banks for concurrent operation Selectable burst lengths 2 4 or 8 Auto precharge option Auto Refresh and Self Refresh Modes 15 6us MT4VDDT864H MT8VDDT1664HD 7 8125us MTAVDDT1664H MT8VDDT3264HD MT8VDDT6464HD maximum average periodic refresh interval Serial Presence Detect SPD with EEPROM Fast data transfer rates PC2100 or PC1600 Selectable READ CAS latency for maximum compatibility Gold plated edge contacts 29 80500 N B Maintenance 1 3 12 PHY 3 3 V 10Base T 100Base TX Integrated PHY Ceiver The ICS1893 is a low power physical layer device PHY General The Realtek RTL8100C L is a highly integrated cost effective single chip Fast Ethernet controller that provides 32 bit performance PCI bus master capability and full compliance with IEE
57. 710 amz 512K LM4871 n z E LLLI i5 D SPEAKER SPEAKER lt 2 I LIMIT RJ45 RJ11 SUB WOOFER TOUCH 000 iTA C M X PAD PCMC IA CardReader Title Litt CARDBUS Transition 80500 MOTHER BD SLOT 316680900001 ASSY 411682700001 Bheet 34 of 34 5 3 Wednesday December 31 2003 1 PDF created with FinePrint pdfFactory trial version http www fineprint com REFERENCE MATERIAL Intel Mobile Pentium M Processor BANIAS Processor Intel INC Intel 8550 North Bridge Intel INC Intel ICH 4 South Bridge Intel INC WINBOND KBC WINBOND LTD Clock Syntherizer ICS INC VT6307L 1394 Host Controller AMPRO Computers INC System Explode View Technology Corp 8050D Hardware Specification Technology Corp SERVICE MANUAL FOR 80500 Sponsoring Editor Jesse Jan Author Grass Ren Assistant Editor Ping Xie Publisher MiTAC International Corp Address 1 R amp D Road 2 Hsinchu Science Based Industrial Hsinchu Taiwan R O C Tel 886 3 5779250 886 3 5781245 First Edition Mar 2004 E mail Willy Chen mic com tw Web http www mitac com http www mitacservice com
58. HDD spin down Suspend to DRAM The most chipset of the system is entering power down mode for more power saving In this mode the following is the status of each device gt Suspend to DRAM CPU off Y Intel 855GME Partial off 41 80500 N B Maintenance VGA Suspend PCMCIA Suspend Y Audio off Y SDRAM self refresh gt Suspend to HDD devices are stopped clock and power down System status is saved in HDD Allsystem status will be restored when powered on again 1 5 2 Other power management functions L HDD amp Video access System has the ability to monitor video and hard disk activity User can enable monitoring function for video and or hard disk individually When there is no video and or hard disk activity system will enter next PMU state depending on the application When the VGA activity monitoring is enabled the performance of the system will have some impact 42 80500 N B Maintenance 2 System View and Disassembly 2 1 System View 2 1 1 Front View 1394 Line Out Connector Line In Connector MIC In Connector SD Card Slot Top Cover Latch 2 1 2 Left side View e 9 VGA Port S Video Port USB Ports 1 Ventilation Openings RJ 11 Connector RJ 45 Connector PCMCIA Card Socket 43 80500 N B Maintenance 2 1 3 Right side View CD ROM DVD ROM Drive Kensington Lock 2 1 4 Rear
59. REQo REQI REQ2 REQ3 REQ4 GNTO GNT1 GNT3 GNT4 GNT2 FRAME SERR IRDY PERR DEVSEL TRDY STOP 743 1317 1317 1319 13 16 131718 1318 13 13 17 13 18 13 19 13 16 13 13 17 13 18 13 16 13 13 19 13 16 17 18 19 18 16 17 19 13 16 17 18 19 13 16 17 18 19 13 16 17 18 19 13 16 7 18 9 13 16 17 18 19 PULL HIGH GPIO PULL HIGH 1248 CRT IN amp 13 SB CARD lt lt 13 ICH GPI5 lt lt 4 713 AGPBUSY 13 22 KBD_US JP lt ICH GPl5 AGPBUSY KBD_US JP zas ave pared So vppss 313 0402 1 1322 EXTSMI 0402 1 36 2 10K SMBALERT 3 gt SMBALERT 0402 2 DAR 1 10K 1322 scu 2402 1 ROR 2 10K 13 22 WAKE 0402 1 RORQA 2 10K 13 0402 1 2 13161719 PCLKRUN 0402 1 2 82 043V GPIO27 0402 1 5 R284 04026 5 VDD3S R283 1 A 0402 o 13 GPIO27 5 HA aca GPIO28 0402 13 21 SPK OFF E 810981 20 14 19 WIRELESS gt 0402 Y 14 15 IDERST es 1 0402 5 10402 5 14 19 MINIPCLACT READ 1 0402 5 HM or R842 1710402 5 14 GPIO42 7 4 PANEL 71214 101 SS PANEL ID2 10K 402 71214 102 6 paNEL ID3 na 712 14 PANEL_ID3 9845 1 10 0402
60. 80 2084 10 10 80 20 6 80 2064 10 10 80 20 llc 50v 50v 50V Cmm or e 50V GND GND GND GND VDD MEM IO VDD MEM IO VDD MEM IO VDD MEM IO 9 9 9 9 8751 Res R713 R34 1K 1K 1K 1K 0402 0402 0402 0402 1 1 1 1 of DD MEM JOREF of DD MEM JOREF E DD MEM JOREF E DD MEM JOREF R753 C741 C740 R60 C65 C57 R712 C719 C722 R32 C27 C25 5 1K 0 1U 100 1K 0 1U 100 1K 0 1U 100 1K 100 0402 0402 0805 0402 0402 0805 0402 0402 0805 0402 0402 0805 1 10 e 62 1 10 63V 1 10 1 10 63V 36V 10 16V 10 16V 10 16 10 80500 MOTHER BD GND GND GND 316680900001 ASSY 411682700001 Rot Date Wednesday December 31 2003 Bheet 10 of 34 PDF created with FinePrint pdfFactory trial version http www fineprint com
61. IYBM 3 0 1 25 225 B differential data pair 3 0 output LVDS compliment 245 800 MHz Name Type Description DVOBD 11 0 DVOB Data This data bus is used to drive 12 bit RGB data on each edge of the differential clock signals DVOBCLK and DVOBCLK This provides 24 bits of data per clock period In dual channel mode this provides the lower 12 bits of pixel data DVOBD 11 0 should be left as left as NC Not Connected if not used DVOBHSYNC DVO Horizontal Sync HSYNC signal for the DVOB interface DVOBHSYNC should be left as left as NC Not Connected if not used DVOBVSYNC DVO Vertical Sync VSYNC signal for the DVOB interface DVOBVSYNC should be left as left as NC Not Connected if the signal is NOT used when using internal graphics device DVOBBLANK DVO Flicker Blank or Border Period Indication DVOBBLANKT is programmable output pin driven by the GMCH When programmed as a blank period indication this pin indicates active pixels excluding the border When programmed as a border period indication this pin indicates active pixel including the border pixels DVOBBLANK should be left as left as NC Not Connected if not used DVOBFLDSTL DVO TV Field and Flat Panel Stall Signal This input can be programmed to be either a TV Field input from the TV encoder or Stall input from the flat panel DVOB
62. NES cin 3 0UH 2512 SPC O8045 P Ye SPC 06708 92 4 gt d 308 30 SENSE1 SENSE2 H1 gt 4 PU7O9B 7 31 10 x 1 SENSE1 NCO jA 22 VOSENSE2 f m SGND x E av oc PC788 4 1 4 mH aa 29 PD724 0723 3300 s IL Pero 95229 PoBo TT 7343 100095 36404 85585585 Pon BZVSSC2VAINA BZV55C3V3 N av 0402 4 0402 SGND5 gt 5 0402 80 2 10 rd 04900 80 2b 1500 owes 50v 50V doled id dod 4 598 50V TTS 7243 1000P BND 63V 7343 0402 Para aV 50 SENSE1 25 d SENSH2 5 10 la 1 SENSE1 25 SENSE 5 1 d 1000P 4 po7s 476 116 0402 1 1 1 1 1 2209 1 118 50V 0402 O4p2 0402 1 PR118 PR124 10 0 1 43 2K 2K 507 804 0402 0402 al 1 28113 1 1 040 PRi2 20 5K RH 10 Pridi 15K 0402 OK 50V 1K 0402 1 402 0402 1 1 E 4 4 er V d PR120 am SGND1 0 0402 VDDS 5 9 E VDD5 4 1 2 INTVCCH 9 PR114 PR119 4 100K 10K 0402 0402 PR112 100K kpe poze 0402 1 2 7002 1 PQ20 4 2N7002 kpe 2 4 H 8369 1 2 7002 2227 H8_PWRON X er 4 PR123 S NDI 132227 SUSCHK X UNE 1M 0402 0402 21 80 20 1 8356 2 7002 0V 2528293031 PWRON_SUSB X gt mios 5 1 SGND1 n Title 8050D MOTHER B D 316680900001 ASSY 411682700001 Rot lumber Date Wednesday December 31 2003 Bheet
63. PD vad 221 OD MAIN POWER WELL PDD 13 SDD 13 i pua ix GPO 23 POWER WELL x 250 R852 0402 acd 6210124 1 0 RESUME POWER WELL PCLKRUN PDD9 009 1320 SBSPKR A z v2 erroe WE 8089 5 v2 GPIOUZS RESUME POWER WELL SPK_OFF POD7 5007 i ue EC wi 27 170 RESUME POWER WELL X PODS 5005 i 4 GPIO 28 1 0 RESUME POWER WELL X PDD3 SDD3 5 21 5 I WE 32d GPIOT321 170 MAIN POWER WELL WIRELESS PDF PDD1 8001 5 1 c I WELI PANEL ID GP10 33 1 0 MAIN POWER WELL PANEL ib Gio SINE doa cee GPIO 34 1 0 MAIN POWER WELL PANEL_ID1 15 PDDACK En Nt SDDACK SDDACK 15 r 15 PDDREQ lt A11 prea SDDREQ SDDREQ 15 1 0 MAIN POWER WELL PANEL ds Don enone SDIOR 18 STRAPPING RISING EDGE PWROK ABI2 170 MAIN POWER WELL PANEL_ID3 15 PIORDY PIORDY SIORDY SIORDY 15 STRAPPING PINS FUNCTIONS 170 MAIN POWER WELL MB_ID2 o 15 PDAO PDAO SDA2 SDA2 15 CSDOUi D ada 3 ABi3 1 ACSDOU 5 2 1 c T VER WELL DERST HABE e E DAT Tm 18 ACSDOUT MODE 23 GPIO 38 1 0 MAIN POWER WEL IDERST ok UA ra 5500 m EEDOUT RESERVED GPIO 38 MAIN POWER WELL MINIPCI AC 1
64. s cables from the system board and remove the two screws Then separate the bracket and free the system board Figure 2 31 e Figure 2 30 Remove four screws and disconnect the two cables Figure 2 31 Free the system board Reassembly 1 Fit the bracket and secure with two screws 2 Turn over the system board Reconnect the speaker s cords 3 Replace the system board back into the housing and secure with four screws then reconnect the cable 4 Replace the LCD assembly CD DVD ROM HDD keyboard and battery pack Refer to previous section reassembly 64 80500 N B Maintenance 2 2 13 Touch Pad Disassembly 1 Remove the battery pack keyboard hard disk drive and CD DVD drive See sections 2 2 1 2 2 2 2 2 4 and 2 2 5 Disassembly 2 Remove the top cover See steps 1 5 in section 2 2 9 Disassembly 3 Remove the two screws and free the touch pad Figure 2 32 Figure 2 32 Remove the two screws Reassembly 1 Replace the touch pad and secure the two screws 2 Replace the top cover Refer to the section in 2 2 9 reassembly 3 Replace the battery pack keyboard hard disk drive and CD DVD drive See sections 2 2 1 2 2 2 2 2 4 and 2 2 5 Disassembly 65 80500 N B Maintenance 3 Definition amp Location of Connectors Switches 3 1 Mother Board A 22 N un 4 Inverter Board Connector 2 J2 LCD panel connector J3 Internal Left Speaker Connector s
65. 80500 MOTHER B D lev 316680900001 ASSY 411682700001 lumber Date Wednesday December 31 2003 Bheet 19 of 34 PDF created with FinePrint pdfFactory trial version http www fineprint com 35V BEAD 6002 100M 1 10 1202 100 1734 06030 1 10 164 1 2012 ay 1701 06030 P 16 l cosa 6002100 u18 1 T 05 8 42 0 5 1 EM147TK lt gt 4 sssen mer jo 399115000046 1314 SBSPKR 1 u 4 apy EN 2 dois ila R438 me ESD0805A NA SPARKGAP 6 CARDSPKI 4 1 1 PC BEEP MIC5205BM5 0603 0805 C458
66. Correct it it Replace another good USB device Replace Motherboard Re test gt Yes Replace the faulty part Board level Troubleshooting Check following parts and signals Parts Signals 0715 5VS USBOCO 10793 SBPO VCC USB 0 U701 PIA M U7 1 2 SBPO VCC_USB 1 J701 SBPI VCC USB 2 L701 SEE L702 L2 SBP2 L5 118 80500 N B Maintenance 8 7 USB Port Test Error An error occurs when a USB I O device is installed 5VS 2 U701 E L702 R877 1 1207 100 USBCLK_ICH 33 39 E vino VOUTO e Y Y USB lt 0712 4 5 p15 VINI VOUTI EL vA T AU 1202 100M e 2 33K 150U AN 4VCC USB 1 Al T J701 USB_OCO V V 12 USBP0 90Z 100M 3 1 M A AJ S 5 USBPO 4 3 5 Q USBP1 907 100 lt 4 3 0715 USBPI 5 4 vs USB 4PX2 DIP 0705 1708 V 1202 100 VCC_USB_2 1 vino vouroH 4 15 5 E 169 5 R76 T 7 33K 150U J706 USB V V V 122 USBP2 90Z 100M 3 ES 4 3 5 USBP2 2 5 4 GNDI GND2 ee V USB 4PX1 119 8050 N B Maintenance 8 8
67. DVOCFLDSTL I TV Field and Flat Panel Stall Signal This input can be programmed to be either a TV Field input from the TV encoder or Stall input from the flat panel DVOC TV Field Signal When used as a Field input it synchronizes the overlay field with the TV encoder field when the overlay is displaying an interleaved source DVOC Flat Panel Stall Signal When used as the Stall input it indicates that the pixel pipeline should stall one horizontal line The signal changes during horizontal blanking The panel fitting logic when expanding the image vertically uses this DVOCFLDSTL needs to be pulled down if not used RED Red Analog Output Tied to ground Analog GREEN Green Analog Video Output This signal is a CRT analog video Analog from the internal color palette DAC The DAC is designed for a 37 5 8U equivalent load on each pin e g 75 8U resistor on the board in parallel with the 75 CRT load GREEN Analog Output Tied to ground Analog BLUE Blue Analog Video Output This signal is CRT Analog video Analog output from the internal color palette DAC The DAC is designed for a 37 5 8U equivalent load on each pin e g 75 ohm resistor on the board in parallel with the 75 8U CRT load Blue Analog Output Tied to ground Analog 82 80500 N B Maintenance 5 2 Intel 855GM GME North Bridge 9 GPIO Signal Descriptions GPIO S
68. JATE FCC and various country specific PTT specifications The programmable parameters of the PCT2303W chip set include AC termination DC termination ringer impedance and ringer threshold The PCT2303W chip set has been designed to meet stringent world wide requirements for out of band energy billing tone immunity lightning surges and safety requirements L Features Virtual com port with a DTE throughout up to 460 8Kbps G3 Fax compatible Auto dial and auto answer Ring detection Codec DAA Features AC97 2 1 compliant 86dB dynamic range TX RX paths 2 4 wire hybrid Integrated ring detector 23 80500 High voltage isolation of 4000V Support for Caller ID Compliant with FCC Part68 CTR21 Net4 and JATE Low power standby Low profile SOIC package 16 pins 10x3x1 55mm Low power consumption 10mA 3 3V operation 3 3V power down VV Integrated modem codec Standard Features gt Data ITU T V 90 56Kbps V 34 4 8Kbps TO 33 6 Kbps V 32 bits 4 8Kbps to 14 4Kbps V 22 bits 1 2 bps to 2 4 Kbps V 21 and Bell 103 and 212A 300 to 1200 bps modulation protocol Data Compression ITU T V 42bis MNP Class 5 Y Error Correction ITU T V 42 MNP 2 4 24 80500 N B Maintenance gt Fax ITU T 17 V 29 V 27ter V 21 Channel 2 Group 3 EIA Class I XOUT FILT FILT2 REF
69. TRDY LCDCNTLO W29 4 4 IRDY ZV LCDCNTLI 4 AGP_FRAME 9 2 1 2225 ZV_LCDGNTL2 43v 13 24 19 75 INTA ZV_LCDCNTL3 GND i M10 aor V YR 2 0402 5 GP AC26 WBF TXOUT_LON 4 R19 13 24 STP STR ACEH HAO TXOUT LOP ATI 4 P 1 4 1324 AGPBUSY AHS AGP BUSY TXOUT LIN TXOUTI AT 4 5 E22 ner TXOUT LIP TXOUTi amp AT 4 402 1 0402 4 ADSTBO AD STBFO TXOUT L2N TXOUT2 ATI 4 LVDS CH1 4 AGP_ADSTB1 25 AD TXOUT L2P TXOUT2 4 5 SBSTBE 88 STBF TXOUT L3N TXOUT3 AT 4 4 AGP SBA O 7 TXOUT LaP TXOUT3 4 IEEE SBAO TXCLK LN TXCLK AT 4 SBA1 TXCLK LP TXCW AT 4 3 SBA2 TXOUT UoN 418 w AE18 1 O 156 SBA4 TXOUT UIN 4617 1 O The SBAS Bourh HEU SBAG TXOUT U2N AE18 1 5 SBA7 TXOUT_U2p AE 1 0 1511 LVDS CH2 TXOUT_UGN 20 A T CN 5 STO E29 sto TXOUT UsP VE Se 5 AGP_STI D27 ST TXCLK UN AE18 1 O 1618 ST AE2B 511 TPi4 5 AGP_ST2 TXCLK UP 5 AGP SBSTBS 2828 sa sTBs DIGON 9 ENAVDD 12 4 AGP_ADSTBO 87880 BLON ENABKL 12 4 AGP_ADSTBI CE m V26 AD_STBS1 4 AGP VREF gt gt AGEVREF 0402 SOV 480 2 28 AGPREF
70. VGATE VRM Power Good VGATE VRMPWRGD is used for Intel SpeedStep technology support This is an output from the processor s voltage regulator to indicate that the voltage is stable This signal may go inactive during an Intel SpeedStep transition 80500 N B Maintenance 5 3 Intel 82801DBM Controller Hub 4 Mobile ICH4 M 6 Power Management Interface Signals Continued Signal Name Type Description DPRSLPVR Deeper Sleep Voltage Regulator This signal is used to lower the voltage of VRM during C4 and S1 M states When the signal is high the voltage regulator outputs the lower Deeper Sleep voltage When the signal is low default the voltage regulator outputs the higher Normal voltage During PCIRST the output driver is disabled and an internal pull down is enabled This is needed for implementing a strap on the pin When PCIRST deasserts the output driver is enabled To guarantee no glitches on the DPRSLPVR pin the pull down is disabled after the output driver is fully enabled NOTE DPRSLPVR is sampled at the rising edge of PWROK as a functional strap Processor Interface Signals Signal Name Type Description A20M Mask A20 A20M will go active based on either setting the appropriate bit in the Port 92h register or based on the 2 input being active Speed Strap During the reset sequence ICH4 drives A20M high if the corresponding bit is set in th
71. VSS TH14 VSS TH14 VSS TH14 VSS TH14 VSS TH15 VSS TH15 VSS TH15 VSS TH15 VSS TH16 VSS TH16 VSSTHI6 VSS TH16 vss 0 vss 0 vss 0 vss 0 vss 1 VDD 55 1 VDD 55 1 VDD vss 1 VDD vss 2 VDD 1 vss 2 VDD 1 vss 2 VDD 1 vss 2 VDD 1 vss 3 VDD 2 vss 3 VDD 2 vss 3 VDD 2 vss 3 VDD 2 vss_4 VDD 3 vss 4 VDD 3 55 4 VDD 3 55 4 VDD 3 65 5 VDD 4 vss 5 VDD 4 vss 5 VDD 4 vss 5 VDD 4 55 6 VDD 5 55 6 VDD 5 vss 6 VDD 5 vss 6 VDD 5 65 7 VDD 6 vss_7 VDD 6 VSS 7 VDD 6 5 7 VDD 6 vss 8 VDD 7 vss 8 VDD 7 vss 8 VDD 7 vss 8 VDD 7 Nee VDD MEM IO vee VDD MEM IO VDD MEM 10 nar VDD MEM 10 vssa 0 vssa o 0 vssa o 0 vssa o 0 859 1 VDDQ 1 vssa 1 VDDQ 1 vss 1 VDDQ 1 vssa 1 1 550 2 2 550 2 2 vssa 2 VDDQ 2 vssa 2 VDDQ 2 vssa 3 VDDQ 3 vssa 3 3 vssa 3 3 vssa 3 vssQ 4 vDDO 4 vssQ 4 4 vssa 4 vDDQ 4 vssQ 4 vDDQ 4 vssa 5 5 vssa s vpDQ 5 vssa 5 VDDQ 5 vsso 5 vDDQ 5 vssa 6 VDDQ 6 550 6 vDDO 6 vssa 6 VDDQ 6 vssa 6 VDDQ 6 vssa 7 vDDQ 7 5 7 VDDQ 7 8807 7 80 7 vDDQ 7 vssa vDDO 8 vssa vDDO 8 vssa 8 VDDQ 8 vssa 8 vssa 9 9 vssa 9 vbDQ 9 vssa 9 vDDO 9 vsso 9 9 550 10 VDDQ 10 vssa 10 VDDQ 10 vssa 10 VDDQ 10 550 10 VDDQ 10 vssQ 11 VDDQ 11 vssQ 11 11 vssQ 11 11 vssQ 11 11 vssa 12 12 vssa 12 12 vssa 12 VDDQ 12 550 12 VDDQ 12 vs
72. gt CLOSE MDC 5 5 85204 0200 7202100 F2 TP use 4pcs of 2kV 1000P cap 291000020206 Um 2 AW 1 012 A o v MINISMDCO14 2 US use 2pcs of 2kV 1000P 80500 MOTHER B D GND GND GND GND GND POLYSW MINISMDC110 UK use 4pes of 1000P cap pocument C Number 316680900001 ASSY 411682700001 Date Wednesday December 31 2003 Bheet 20 o 34 5 I E I T PDF created with FinePrint pdfFactory trial version http www fineprint com AUDIO AMPLIFIER DEVICE_DECTY _ REMARK 8477 100K 5 5 o i Me HP in 022 A 5 1 i 20 ED X MP OFF ix SHUTDOWN GPEiS E a38 1824 1 E no this condition DTC144TKA 288202240001 22 KBC_MUTE X doo L67 m RLS4148 5 BAWSG AMPVDD 4 OFF Q52 288100056017 0402 al 1202 100 2012 10V E piri S NE AU MN p 002 1000 10 10 63 1752 R322 R1183 36V 36V 2096 4 7K 10K R1302 1202 100 2012 1 0402 0402 5 6002 100 2720 AGND CA ND 152 DEVICE DECT
73. l mK 22 25 PUL ins vec D POS BS aie 27002 Stour GNDO lie 4 0010 MAX4173FEUT T 0402 PRI SOT26 10 10 50V xz 0402 GND 5 4 0402 GND 120 22 DTC144WK a 288202237002 PL705 1202 100 0805 2012 Xt ej 10 4 GND bd PF702 _7A 24VDC ND low o BE ES 4 PL704 PC720 1202 100 PR716 0 01U 2012 499K 0402 0402 0035 10 1 50V i VDD5 BAT V 22 X lt GND PR20 PC723 2 Os T 4 99K p 0 10 8 0402 0402 2 Hm i GNDB 1 80 20 4 50V PUSA 3 1 22 4 1 ari BI 4 550 1 21 Pci6 GND i 20K RIA 7P 2 5MM E 0402 SUYIN i 480 2095 NE 250233 MR007G123ZU 50v GND 7 SA GND PR23 E lt 22 0402 H 5 PR24 A lt 22 0 PD2 0402 2 2 167 BAV99 T 288100099012 BAV99 yV 288100099012 Jon SPARKGAP 6 SPARKGAP 6 GND di Mirac gt 80500 MOTHER B D 316680900001 ASSY 411682700001 lumber Date Wednesday December 31 2003 Bheet 32 of 34 1 PDF created with FinePrint pdfFactory trial version http www fineprint com CHARGING PQ707 AO4407
74. or start a PCI transaction by asserting FRAME 78 80500 N B Maintenance 5 2 Intel 855GM GME North Bridge 5 AGP PCI Signals Semantics Descriptions AGP Strobe Descriptions Signal Name Type Description Signal Name Type Description GFRAME T O G_FRAME Frame GADSTB 0 VO Address Data Bus Strobe 0 provides timing for 2x and 4x data on During PIPE and SBA Operation Not used AGP SBA and AGP AD 15 0 and C BE 1 0 signals The agent that is providing the PIPE operations data will drive this signal During Fast Write Operation Used to frame transactions as an GADSTB 0 VO Address Data Bus Strobe 0 Complement With AD STBO forms output during Fast Writes AGP differential strobe pair that provides timing information for the During FRAME Operation G_FRAME is an output when the AD 15 0 and C BE 1 0 signals The agent that is providing the GMCH acts as an initiator on the AGP Interface FRAME is data will drive this signal asserted by the GMCH to indicate the GADSTB 1 Io Address Data Bus Strobe 1 Provides timing for 2x and 4x data on beginning and duration of an access G FRAMEZ is an input when 31 16 and C BE 3 2 signals The agent that is providing the the GMCH acts as a FRAME based AGP target Asa data will drive this signal FRAME based AGP target the GMCH latches the C BE 3 0 and 1 Io Address Data Bus Strobe 1 Complement With AD 5 f
75. 0 01U 0805 0402 0402 3544 VSS1DI c79 1000P 010 0402 0402 0402 4 VSS 45 100 0402 0402 0402 2 VDDR1_32 20 280204 80 20 Sone WV 500207 0805 20 80 20 lt 80 2 00 MEM VDDCI 3 VDDR1 33 50 2 50V 50V VSS_46 lt 63 50 50V 507 VDDR1 24 lu 10 VDDR1_53 VDDR1 35 4 cu 58 48 T VDDR1 54 VDDR1 36 1709 1202 100 8 vee 49 VDDRi 55 VODRI 3 i SS 50 TXVSSR 0 Oea E 1 1 OVDD_MEMPLL1 8 VSS 51 TXVSSR 1 ato vss_1i9 VDDR1 38 VDD IO 2012 C736 c738 85 52 TAVSSR_2 VSS 120 VDDR1 40 100 Hi2 55 53 VSS_121 VDDR1 41 T 4 0805 0402 0402 H14 VSS_54 LVSSR_O VSS 122 VDDRI 42 63V 480208 480 205 4 vss 55 LVSSR 1 wae 4 J 4 4 10 50V 50 vss 56 LVSSR 2 VDD MCLK2 5 VDDRHO VDI C75 C76 C66 C118 C84 GND H21 VSS_57 LVSSR_3 RI 44 VDDRH1 VDDR1 45 0 10 1000P 0 010 0 10 100 85 58 MODE AD 0402 0402 0402 0402 0805 425V 10 23 55 59 LPVSS VDDDI 1 8 480 205 20 80 20 lt 80 20 63V 9 H27 vss 60 VDDRI 47 E ov thy E VDD2DI VDDR1 48 10 131 1202 100 VSS 61 PVSS VDDR1 49 41 x VSS 62 TPVSS VDD PNLIO1 8 TXVDDR 0 VDDR1 50 2012 1 VDD_DAC2 5 VSS_63 TXVDDR 1 VDDRI 51 o cna cns VSS_64 88 128 VDDR1_52 57 100 010 OU 23 vss 65 LVDDR 18 0 0805 0402 0402 kag 55 66 A2VSSN_0 LVDDR 18 1 VDDR3 0 e 63V 480208 80 20 Z vss 67 A2VSSN 1 eere 10 1 50V 50 K20 vss 68 LVDD
76. 1 0 0402 5 CDROM COMM covece Ki 1 allen xm CD GND 0402 18V 48020 1 amp CDROM COMM 15 1 1 REE A 16 C979 1 1 T T PC BEEP il soner 492 0402 10V 80 20 1 1 0402 4 6 C980 1 1 R546 2 R537 R549 1202 100 1202 100 naro 0402 10V 80 2096 6 8K gt 68 GND 2012 AGND GND 2012 AGND 14 C976 1 iu 0402 0402 2 AURA 0402 10V 80 2096 1 5 5 T C950 1 iu 31 18 C516 1 1U a 24 576 0402 10V 80 20 YEDA AUER 0402 10V 80 20 1 L65 L62 4 5 953 1 10 E 35 AOUT L ANN LANAS C477 274012457406 0402 10V 80 20 FRONT MI ERE OUTE AGND AGND AGND Jag Gana fm JV araa neo UNEQUPR ARR 1202 100 1202 100 0 C945 1 4 13 C519 P659 1 A QA MODEM SPK GND 2012 AGND GND 2012 AGND 50 50V T 0402 16V 10 FRONEMGI PHONE 0402 16V 10 040 X C937 1 OUT MONO OUT T 40 0402 16V 10 ME Neko 0939 10 Es R5607 44 1 0 csi8 45 SOUTL 802096 0402 10 1 1 0 1U NA SUB oun 508 oum R497 1 Oy 48 XTLSEL sour 41 00 1 10 1 10 0402 0402 0402 X iE 380 2096 0402 10V 50V 5 10 21 SUB QUTR R503 1 ON C962 1000P 1 16V 0402 21 0402 50 10 HI 30 C960 1 1000 AFILT2 0402 50V 10 1 AGND AGND AOUT L _ 11301 e __ 81351 21 za M 20mil 0402 9 9 9 811271 AAK 911281 2
77. 10 10 1202 100 O SA POLYSW 80 20 10 10v 2012 miniSMDCO50 us 771 xx E Deno 85 GND GND GND 8s 50V 80 20 138 1 J4 lt 22 T_DATA gt 12021100M TP_VDD 1608 TP DATA m 5 4 R427 0402 8364 1 0402 H 137 1 Y TP 3 422 0402 ATIRSV MODE 28 Aa 22 T CLK gt 1 t BAT AB RSV GNDA A n AS RSV veca 2 1608 R132 5 TP LEFT R408 0402 GND SW_LEFT iu 7 1 1 eno 28 INTR BIB 1 pee 5 19 AQIRSV 24 ACES AT RSV WE LFRAME KLFRAME 13 19 22 87151 0607 POREN no LADO DQO DaziRSv 21 TC010 PSS11CET 4 4 4 4 297004010001 14371 14471 1547 172 029 47 a7p a7p ATP 8 gt gt gt 1 0402 0402 0402 0402 d J 89 9222 4 10 44 10 44 10 lt 4 10 ESD0805A NA sov sov sov sov GND 88283928 3918 20207 SST49LFO04A WRIGHT GND LADO 3399 134922 LADO 131922 LADI 1019 T 3021 LADZ 131922 LAD2 E 131922 LAD3 a718 TC010 PSS11CET MMBT3904L GND 297004010001 SYS BIOS Vendor List GND R1073 288203904022 D23 TASLFOOAA 7490001 213 MMBraso4L 0402 288203904022 GND ul ESDOS05A NA GND TP RIGHT TP56 2 P 7 8 LED TP CLK TP DATA 25 0721 1 433 1 LED Laga t 220NA V 9 OVDD3S 5 X IDE LED te 4 416 1 0402 kd R553 1 5 15 HDD LEDE 12 18
78. 2 2 2N702 o32U T 3V 115 1207 100 12 3 e 5 ov 1207 100 23 RII RIA 10K 4 6 7 10 14 PANEL ID 0 3 TXCLK ATI R160 0 TXCLK 15 TXCLK ATI R161 0 TXCLK 13 2 TXOUTO _ATI R153 0 TXOUTO 28 TXOUTO ATI R154 0 TXOUTO 26 m TXOUTI ATI R158 0 TXOUTI 22 TXOUTI _ATI R159 0 TXOUTI 20 e TXOUT2 ATI R794 0 TXOUT2 27 2 TXOUT2 _ATI R795 0 TXOUT2 25 TXOUT3 ATI R796 0 TXOUT3 21 TXOUT3 _ATI R797 0 TXOUT3 19 66M_AGP R819 33 23 U712 CLK GEN 109 80500 N B Maintenance 8 3 No Display 4 Back Light amp Cover Switch Checking 3V 0715 in this page D2 BAT54 R386 0 7 43V gt 0710 PWROK DIS Kj 54 10 855GM DVMAIN R380 117 1207 100 12 ae YY VDD3S 118 y 120Z 100M 3 P12 27 H8 ENABKL R383 0 016 54 ENABKL R323 0 ENABKL_VGA_C 110 ___1202 100 4 p22 11 BLADJ R5 0 L9 ___1202 100 6 _ lt 35 BATT_R 8 1 s 36 BATT_G 7 L 2 9 79 AC_POWER 6 3 j BATT_POWER 5 n 4 11 016 R468 0 3V 3VS 3VS Pu 07030 0703 U703B Q720 0719 7AAHCIA V 74AHCIA 7AAHCIA V DTCIIATKA DTCIMTKA WINBOND 4 DP REM KBC in T U715 1152 R1140 180K 13 BATT_LED 4 PWROK 3VS R373 470K SWI 16 H8 LIDSW RIS 1M R3 e Y
79. 2 9 LCD ASSY Disassembly 1 Remove the battery pack keyboard CPU hard disk drive CD DVD drive and wireless card See sections 2 2 1 2 2 2 2 2 3 2 2 4 2 2 5 and 2 2 6 Disassembly 2 Remove the nineteen screws on the bottom of notebook Figure 2 18 3 Remove the four screws that secure the hinge cover Figure 2 19 Figure 2 18 Remove nineteen screws Figure 2 19 Remove four screws 57 80500 N B Maintenance 4 Remove the two screws and disconnect the touch pad s cable then free the top cover Figure 2 20 5 Remove the two hinge covers Figure 2 21 Figure 2 20 Free the Top cover Figure 2 21 Remove the hinge covers 58 80500 N B Maintenance 6 Disconnect the two cables and remove the four screws Figure 2 22 7 Remove the eight screws Figure 2 23 Figure 2 22 Remove the four screws and Disconnect the two cables Figure 2 23 Remove the eight screws 59 80500 N B Maintenance 8 Carefully pull the antenna wires out Now you can lift up the LCD ASSY from base unit Figure 2 24 Figure 2 24 Free the LCD ASSY Reassembly Attach the LCD assembly to the base unit and secure with four screws Rip the antenna wires back into Min PCI compartment Reconnect the two cables to the system board Screw the hinge covers by two screws Replace the shield and secure with eight screws Replace the top cover and secure with two screws And reconnect the touch pad s cable Upsi
80. 402 of PRI 22 0402 0402 1 1 3M 480 20 80 20 1 0402 Pcij 50V 50v 1 100 17 RS 22 1204 GND_A m 12 7K 4 10V 0402 402 ai 4 4 4 4 4 4 4 4 1 0 PR40 Js 1 2 vos 13 3K 499K 0 59 kea 0402 0402 RUN SS 0402 ViDS GND PR104 1 1 5 SHORT SMT1 0 0402 1 GND_A 5 4 PR53 1 337 amp VCCP PWRGD 28 0402 336 1 i BRIS o J 1 RO 0402 VDD3 0402 5 100 T 9 2 1 1 1 gt gt CORE_CLKEN 11 50V 02 PR64 7 PRS1 PR56 10 2 PR59 2KINA o 50V 0402 1M 0402 0402 H 1 0402 1 4 5 7 PR58 PRES GND_A 2N7002 4 12K 191KINA 205 50123 FET 0402 0402 3 00 5 a 1 M Pas E l 39041 gt gt PWROK 4 12 13 11 25 28820390402 PR73 71 uj PR49 RUN SS 21 1 Pato 0402 100K 1 PRES MMBT3904L 5 0402 80 6K GKD 288203904022 1 4 0402 43 2K 1 0402 kpe pas E 4 1 27002 1M 5 x zn SOT23_FET 0402 Nu 1 GND_A 0402 ej 38020 PR6t Paz 10V 2526282930 PWRON_SUSB SURE eer 28 GND_A C26 PREZ 3300 0402 1 0402 5 0402 0402 10 of 80 20 1 50V _ GND A PD4 Title 8050D MOTHER B D a 316680900001 ASSY 411682700001 Rot lumber BATS4C Date Wednesday December 31 2003 Bhe 3 o 34 I T PDF created with FinePrin
81. Bheet 28 o 34 PDF created with FinePrint pdfFactory trial version http www fineprint com 1 8 _ 1 35 _ DVMAIN 18706 PL712 14 2012 T SHORT SMT4 1202 100 X PJL7 JP 010 4 4 4 0402 774 779 10 777 0010 100 100 1000 0402 1210 1210 Ww 0402 10 E GND 10 50V 2O IXER 20 X5R PRO PR9O 50V 1 4 p88100056017 1 47 i 47 GND 0603 6 0603 GND 1 TEXT haue 1 OT23N PRe2 4518 1 have 2 0 T 0402 100 JP 5 16 4900 e E 4 506 1206 4 PC51 04 ZL 776 4 010 184294 010 PU707A 1000P 0805 50 0805 D 0402 lt 10 WZ ani 10 10 aw q 44414 LTC3728L HVQFN32 1 5289936 GND OG 8 G2 8 4900 ips Ub 714 PR741 aci La 4 5 1 swi 8 1 12 12 TG sw H 0E AR O4135V 2010 59006703 T 12 3 0UH 012 1 30 5 Nos
82. Disassembly 2 Remove one screw fastening the CD DVD ROM drive Figure 2 10 3 Push firmly to release the tray Then gently pull out the CD DVD ROM drive by holding the tray that pops out Figure 2 11 Figure 2 10 Remove one screw Figure 2 11 Remove the CD DVD ROM drive Reassembly 1 Push the CD DVD ROM drive into the compartment and secure with one screw 2 Replace the battery pack Refer to section 2 2 1 reassembly 53 80500 N B Maintenance 2 2 6 Wireless Card Disassembly 1 Carefully put the notebook upside down Remove the battery pack Refer to sections 2 2 1 Disassembly 2 Remove the two screws fastening the Mini PCI compartment cover Figure 2 12 3 Disconnect the wireless card s antennae first 0 Then pull the retaining clips outwards and remove the wireless card Figure 2 13 Figure 2 12 Remove two screws Figure 2 13 Remove the Wireless card Reassembly 1 To install the wireless card match the wireless 5 notched part with the socket s projected part and firmly insert it into the socket Then push down until the retaining clips lock the wireless card into position Then sure that the antennae fully populated 2 Tighten the screws to secure the wireless card compartment cover to the housing 3 Replace the battery pack Refer to section 2 2 1 reassembly 54 80500 N B Maintenance 2 2 7 Modem Card Disassembly 1 Carefully put the notebook upside down R
83. GND 10 0608 Bize pocument d o A20 GATE GND Number 316680900001 ASSY 411682700001 Rot Date Wednesday December 31 2003 Bheet 13 of 34 1 PDF created with FinePrint pdfFactory trial version http www fineprint com U715E av 4 15 USBPO 8185 5 04020 DES c20 Usep o 15 USBPO BITS 53 04026 DFS USBP 0 13171922 SERIRQ A 1 15 USBP1 HIS USBP 1 15 USBPI 04026 DFS USBP_1 A 18 TEL oe R205 5 04026 DFS User 2 He R907 10K 15 USBP2 USBP 2 HIS 13 16 SB_PME lt 0402 5 Qiu usBP Q 1 3i HI7 2 13 TES 06 usera 56 5 13 ICH LAN KOAN 88 TP24 e 179 USBP 4i 0402 R308 10K 0402 5 NZ vpp3s 9 TP28 user 5 HD R856 56 GND gama GND 0402 5 R929 1 47K SMLNKI 0402 5 lt 5 1 13 15 OCHO STBt HI STBF er HUB_STB 4 R940 1 47K SMLINKO STB HI 5785 HUB STB 4 4VCCP 0402 5 lt 5 13 15
84. Hard Disk Drive Test Error Either an error message is shown the drive motor spins non stop while reading data from or writing data to hard disk Hard Driver Test Board level Check the BIOS setup u 2 Replace another good hard driver or try again Check following parts and signals Re boot OK Parts Signals Replace the faulty parts U715 PCIRST 0 PDDREQ J714 PIORDY 14 037 PDD O 15 5V Replace 041 0 2 5V_HDD Check the system driver for proper tallati ERE Motherboard ae PDIOR installation DINE R492 R1081 R1074 PDDACK PDCS1 PDCS3 Re Test 80500 N B Maintenance 8 8 Hard Disk Drive Test Error Either an error message is shown or the drive motor spins non stop while reading data from or writing data to hard disk 3V R1081 R1074 5V 4 7K 8 2K 5V_HDD L733 1202 100 PD D 0 15 PDIOW PDIOR PIORDY 0715 PDDACK 16014 4 PDA 0 2 PDCS1 PDCS3 5V PCIRST 0 R492 10K RSTDRV1 44 R476 10K 041 DTC144TKA Q37 DTCI44TKA P15 J714 LOANNOOD 121 80500 N B Maintenance 9 CD ROM Test Error CD ROM driver can t run normally maybe an error message is shown when reading data from CD ROM CD ROM Driver Test Error Check the CD ROM driver for proper instal
85. L716 X H8 T 8 DATA 132 151 0 7 Replace Motherboard Replace the faulty Keyboard or Touch Pad 0 15 15 PWRBTN KBD_US IP 116 80500 N B Maintenance 8 6 Keyboard K B Touch Pad Test Error Error message of keyboard or touch pad failure is shown or any key does not work VDD3_AVREF 0 72 VDD3 71 1 C445 C448 C449 0 10 0 10 100 30 P11 4 17 R817 33 PCICLK_KBC 70 U712 CLKGEN 3V R392 8 2K 69 4 SERIRQ U715 09 LAD 0 3 65 6 13 64 UN LFRAME 63 ICH4 SUSB H8_SUSB V 049 DTC144TKA U16 WINBOND KBC KBD_US JP 25 F701 L716 0 SA POLYSW 1202 100 5V 6 4 T_DATA 136 1202 100 I 23 6 CLK 137 1202 00M 4 sw4 o 9 SW LEFT R132 0 3 JA e DT SW RIGHT _ 151 0 2 SWS5 1 Bc 2 7 V 4 GND 39 54 KO 0 15 1 16 D 22 29 KBC s R404 28 e e Js XI C447 8MHz C450 22 n R165 10K 117 80500 N B Maintenance 8 7 USB Port Test Error An error occurs when a USB I O device is installed USB Test Error Bp if the USB device is installed Bp Including charge board Yes gt
86. SOT23N Linney 2 2207 1000 T 855 CRT GREEN 4 CHAGND 1 APA 2_2202100 1 CRT RED 1 RA A 0402 CON RED f 4 i t 855 CRT RED 4 174 1608 1202100 1 4 7 a4 754 1 2 1 61 4 0402 1206 i 206 i 4 8 4 1 47 25V 410 A 1 0402 do FTT 47 25V 10 CHAGND 15 6 8 CHAGND ee E 4 GND ESD41A NA H CHAGN i k 80500 MOTHER B D CLOSE TO CRT CONNECTOR ize lev en PCB 316680900001 ASSY 411682700001 Rot lumber I I I I Date Wednesday December 31 2003 Bheet 12 of 34 5 z 3 z T PDF created with FinePrint pdfFactory trial version http www fineprint com SOUTHBRIDGE ICH4 M 1 2 2 aav U715A VCC3 U715B POL NT R Rigs PCI AD 0 31 16171819 woos INTAN PCI_INTB R854 INTB
87. TV Field Signal When used as a Field input it synchronizes the overlay field with the TV encoder field when the overlay is displaying an interleaved source Flat Panel Stall Signal When used as the Stall input it indicates that the pixel pipeline should stall one horizontal line The signal changes during horizontal blanking The panel fitting logic when expanding the image vertically uses this DVOBFLDSTL needs to be pulled down if not used 8l 80500 N B Maintenance 5 2 Intel 855GM GME North Bridge 8 DVOB and DVOC Port Common Signal Descriptions Digital Video Output C DVOC Port Signal Descriptions Name Type Description DVOBCINTR I DVOBC Interrupt This pin is used to signal an interrupt typically DVO __ used to indicate a hot plug or unplug of a digital display ADDID 7 0 I ADDID 7 0 These pins are used to communicate to the Video BIOS DVO Jwhen an external device is interfaced to the DVO port Note Bit 7 needs to be strapped low when an on board DVO device is present The other pins should be left as NC DVODETECT I DVODETECT This strapping signal indicates to the GMCH DVO whether a DVO device is present or not When a DVO device is connected then DVODETECT 0 Analog CRT Display Signal Descriptions Pin Name Type Description VSYNC CRT Vertical Synchronization This signal is used as the vertical CMOS sync signal HSYNC CRT Horizon
88. The integrated LAN Controller uses these signals to transfer data and control information to the LAN Connect component LAN_RSTSYNC LAN Reset Sync The LAN Connect component s Reset and Sync signals are multiplexed onto this pin Signal Name EEPROM Interface Signals Description EE_SHCLK EEPROM Shift Clock Serial shift clock output to the EEPROM EE_DIN I EEPROM Data In Transfers data from the EEPROM to the ICH3 This signal has an integrated pull up resistor EE_DOUT O EEPROM Data Out Transfers data from the ICH3 to the EEPROM EE_CS EEPROM Select Chip select signal to the EEPROM Firmware Hub Interface Signals Signal Name Type Description FWH 3 0 VO Firmware Hub Signals Muxed with LPC address signals LAD 3 0 4 IO LFRAME Firmware Hub Signals Muxed with LPC LFRAME LFRAME signal PCI Interface Signals Signal Name Type Description AD 31 0 PCI Address Data AD 31 0 is a multiplexed address data bus During the first clock of a transaction AD 31 0 contain a physical address 32 bits During subsequent clocks AD 31 0 contain data The ICH4 drives all 0s on AD 31 0 during the address phase of all PCI Special Cycles C BE 3 0 IO Bus Command and Byte Enables The command and byte enable signals are multiplexed on the same PCI pins During the address phase of a transaction C BE 3 0 define the bus command During the data
89. U712 1 5950810 P16 U719 LAN Controller RTL8100CL 3VS R1110 3 6K 11 8 5 109 EEDI 2 cen 108 EEDO e 3 0723 1U GND 106 EECS 4 po 93C46 1 MDI0 PMDIO 8 9 PJTX _ 1 P16 MOV WU 10 PJTXI 2 7709 3 VV YA 15 PIRX 2 MDIO PMDIO 7 16 PIRX 6 R152 RP27 0717 75 0 4 5 2 11 MCT4 4 gt 149 aad _ 5 3 75 a 3 14 MCT3 7 6 MDII PMDII 1 8 LF H80P 121 LAN XTALI 122 LAN XTAL2 R1101 IM X706 1 2 e 25MHZ C914 cis 27P 27P 128 80500 Maintenance 8 12 Modem Test Error An error occurs when run the modem MODEM Test Error 1 Check if the driver is installed properly 2 Check if the notebook connect with the Board level Troubleshooting phone LAN properly Check following parts and signals Yes J717 5V No J715 3VS R1132 pid Replace MONO_OUT Replace a known good modem Motherboard R498 ACSDOUT ACRST L69 R1131 ACBITCLK L724 ACSDINI F2 MODEMP MODEMN Re test Yes OK Correct it 129 80500 N B Maintenance 12 Modem Test Error An error occurs when run the m
90. USB COMP Hi coup B3 H VSWNG 22 VSWING WHEN USE INTEGRATE VGA HIVSWING R933 10 _ ICH BATLOW OCi5 Hiner 22 __ Y KICH BATLOW 13 ADD RP26 R269 0402 5 CLK66 56 R310 1 10 ICH _SYS_RESET 1924 WIRELESS GPIO 32 0402 0402 5 KICH_SYS RESET 13 7 1224 PANEL 100 GPIO 33 LANRXDO A10 x gt 71224 PANEL 101 GPIO 34 LANRXD1 49 lt R273 71224 PANEL 102 GPIO 35 LANRXD2 FALL R261 4 i 4 DOSE ET 71224 PANEL 103 GPIO 36 LANTXDO 10 x 2 CPU THRMTRIP OUT amp Lae KCPU_THRMTRIP 13 8 24 MB 102 GPIO 37 LANTXD1 10 5 1524 IDERST GPIO 38 LANTXD2 12 oe 1 1924 MINIPCI lt 22 GPIO 39 LANRSTSYNC EH 4 H MB 107 Hat 040 0402 5 020 R315 R318 R316 R317 Ww 288203904022 22 2 2K 10K 10K 24 GPIO42 POE GPIO 42 EE DIN 21 as MMBT3904L R266 0402 0402 4 0402 0402 24 GPIO43 23 GPIO 43 cs 210 5 5 5 5 EE_SHCLK 12 EEDOUT __ 11 USBCLK lt EE_DOUT EE pouT R812 0 0402 5 1 5 13 6 DATA K KSMBDATA 61 GR 1 NE NNA Bo usereias t ACSDOUT ACSDOUT 20 ACBITCLK ACBITCLK 20 4 4 R313 0402 5 i cergias ACRSTR ACRSTR 20 EIC R290 4 ACSDINO 20 cer 4 ACSDIN1 ACSDIN1 20 pis ACSDIN2 50V 5 13 smock X KsmBcLK 6
91. V DAC De Txc 11 __ TD 1 4 2 0710 PMDH 1 pp mao 218 L728 V DAC axe 14 __ 1 2 2 0 2 18 074 MDO2 0603 KicH 13 RD RX GND CL 190G NA 190G NA 4 1 LAN WAKE 0709 0 NC 33 R1097 R1109 7 Net NS 510 NA 510 NA DTC144TKA 22 288202240001 LF H80P 0402 0402 0402 5 SOXIG 1 1 Pull high at EC side R152 1 75 LEDO 0402 MCT3 R930 1 75 1000 042 3 LEDS cp MCT2 R262 1 2 75 1808 0402 lt 10 MCTI 9254 1 75 NA 0402 gt 80500 MOTHER BD GND 45 Bize B 316680900001 ASSY 411682700001 Rot lumber Date Wednesday December 31 2003 Bheet 16 of 34 PDF created with FinePrint pdfFactory trial version http www fineprint com
92. View Kensington Lock Power Connector USB Port 2 44 80500 N B Maintenance 2 1 5 Bottom View 2 1 6 View oo0Q9o0000c9 9 Hard Disk Drive DDR SDRAM Card Wireless Card CPU Battery Park Stereo Speaker Set LCD Screen Power Button Stereo Speaker Set Keyboard Device LED Indicators Touch Pad Hard Disk Drive Indicator Battery Power Charging Indicator Power Indicator 45 80500 N B Maintenance 2 2 System Disassembly The section discusses at length each major component for disassembly reassembly and show corresponding illustrations Use the chart below to determine the disassembly sequence for removing components from the notebook NOTE Before you start to install replace these modules disconnect all peripheral devices and make sure the notebook is not turned on or connected to AC power 2 2 1 Battery Pack 2 2 2 2 2 3 2 2 4 HDD Module 2 2 5 DVD ROM Drive 2 2 6 Wireless Card NOTEBOOK 2 2 7 Modem Card 2 2 8 DDR SDRAM 2 2 9 LCD Assembly LCD Assembly Components 2 2 10 LCD Panel 2 2 11 Inverter Board 2 2 12 System Board Base Unit Components 2 2 13 Modular Components 46 80500 N B Maintenance 2 2 1 Battery Pack Disassembly 1 Carefully put the notebook upside down 2 Slide the two release lever outwards to the unlock 7 position while take the battery pack out
93. X701 855_TV_COMPa9 prior 0402 8 2KINA 1 2 51 ag 5 Dir 5 0402 pen H xd R936 GND GND DDCK 18 REG 1 1 4 EO use st og He C ovont 4 ii n Mods XIN hs pt oat R54 IL 4 9 SZ 5 DDDA 10 sav 10 XVFIN NC 0402 0402 330 NA 71 GND 4 MI2CDATA 087 50V XOUT 42 xo 20 020 18020 0402 330 NA ven an WHEN USE INTEGRATE VGA v ae 5402 lt BAVOSINA cf 2N7002NA ADD R763 R766 U2 1240 PouTioeT amp f rour Nos SON B2KNA XH reser 2 T 288227002006 0402 RESET Nor GND 402 28V 104 m 9 2 T R37 1 NON 35 5 NC10 2704 anton TV 7 lt 8 28 1 c17 1 1240 2 0402855 AY DVOGFLOSTL lt lt Gaga Bco sz BL Sue Nee i 1 402 25V 10 R49 999 222 31 2 3 Lis LUMA 7 330 NA 22 G56 556 4 iB 1 1202100 1 R7 0402855 TV LUMA 0402 mo lt lt AGS Hn L20 Tx 7 5 4 4 CH7011A NA Ste 1 12021 0 PQFP64 0 5MM E I 19 1 2 0402855 0402 25 410 4 GND1 3852 1 Bh E cree cis ca c 21 754 GND 270 270 270 100P 100P 1206 7P RA 0
94. amp 175 1608 amp 1 6002 100 1608 2 AGND 175571 1608 4 i 20 RIGHT lt RIGHT 1 Ua 1 2_6002 1608 ACES 8002 100 10V 80 20 4 04 0200 3 0 1 ROUT x 291000020206 DECT L55 1 2 1608 i 497 1 RHEN ROUT 18 ROUT id 6002 1 00M H 0402 10V 80 20 SOUE 1608 C935 1 1 1 6002 100 _ 1608 1 L757 1 Driv 1 0402 10V 380 209 RIN PADO T ai 116 2 6002100 1608 HL cc xa AGND 14 18 4 91159 1 100k 0402 5 HDR MA 2 100P NA GP1FD310TP R1160 1 100 0402 5 3 4 1 0485 1 2 10 _ ACES 0402 SHARP AMPVDD R1161 1 3O0K 0402 5 GARI BYPASS 0402 TOV H 20 7T ios T 1000 85204 0200 P CONN_GP1FD310TP no AMPVDD 8391 4 TOKINA 0402 5 a T SA Hoe 291000020206 n 20 20 GND 1608 4 GNDO AGND LEFT 1 10 GNDI 6002 1000 AMP_LEFT amp 1 542 10V Bil Ewa 1 R329 1 0402 5 L80 sooznoom 1608 1 1U CH gt 528 1 0402 5 178 1 ww 2 6002100 608 23v R367 0402 10V ibreli 10K C493 1 10 10 tour 8 0711 4 0402 0402 10V 3 4 4 288221371002 DEVICE_DECT AGND 85 E R529 R328 ciso csos C354 cass persa a 1 AGND 32 57 92 1K 1K 100P 100P 100P NA OOPINA E 0402 0402 0402 0402 0402 0402 DEVICE_DECT 923 99 Ga 1 10 10
95. board CLK 1 0 are used as BCLK 1 0 references for a debug port implemented on an interposer If a debug port is implemented in the system CLK 1 0 are no connects These are not processor signals RS 2 0 Asserting the RESET signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents For a power on Reset RESET must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications On observing active RESET both system bus agents will deassert their outputs within two clocks All processor straps must be valid within the specified setup time before is deasserted RS 2 0 Response Status are driven by the response agent the agent responsible for completion of the current transaction and must connect the appropriate pins of both processor system bus agents RSVD These pins are RESERVED and must be left unconnected on the board However it is recommended that routing channels to these pins on the board be kept open for possible future use Please refer to the platform design guides for more details SLP SLP Sleep when asserted in Stop Grant state causes the processor to enter the Sleep state During Sleep state the processor stops providing internal clock signals to all units leaving only the Phase Locked Loop PLL still operating Processors in this state will not
96. bus HADSTB 1 0 VO Host Address Strobe HA 31 3 connects to the CPU address bus AGTL During CPU cycles the source synchronous strobes are used to transfer HA 31 3 and HREQ 4 0 at the 2x transfer rate Strobe Address Bits HADSTB 0 HA 16 3 HREQ 4 0 HADSTB 1 7 HA 31 17 HD 63 0 Vo Host Data These signals are connected to the CPU data bus AGTL HD 63 0 are transferred at 4x rate Note that the data signals inverted on the CPU bus AGTL Data Bus Busy Used by the data bus owner to hold the data bus for transfers requiring more than one cycle Defer GMCH will generate a deferred response as defined by the rules of the GMCH s Dynamic Defer policy The GMCH will also use the DEFER signal to indicate a CPU retry response 75 80500 N B Maintenance 5 2 Intel 855GM GME North Bridge 2 Host Interface Signal Descriptions Continued DDR SDRAM Interface Descriptions Signal Name Type Description SCS 3 0 Chip Select These pins select the particular DDR SDRAM SSTL 2 components during the active state NOTE There is one SCS per DDR SDRAM Physical SO DIMM device row These signals can be toggled on every rising System Memory Clock edge SCMDCLK SMA 12 0 Multiplexed Memory Address These signals are used to provide SSTL 2 multiplexed row and column address to the DDR SDRAM SBA 1 0 Bank Select Memory Bank Address
97. by AC adaptor Seven LED indicators System has seven status LED indicators at front side which to display system activity From left to right that indicate HARD DISK CD ROM NUM LOCK CAPS LOCK SCROLL LOCK Mini PCI and Card Reader 37 80500 N B Maintenance 1 4 5 Battery status Battery Warning System also provides Battery capacity monitoring and gives users a warning signal to alarm they to store data before battery dead This function also protects system from mal function while battery capacity is low Battery Warning Capacity below 1096 Battery Capacity LED flashes per second system beeps per 2 seconds System will Suspend to HDD after 2 Minutes to protect users data 1 Battery Low State gt After Battery Warning State and battery capacity 1 below 5 system will generate sound for twice per second L Battery Dead State gt When the battery voltage level reaches 11 5 volts system will shut down automatically in order to extend the battery packs life 38 80500 N B Maintenance 1 4 6 Fan power on off management FAN is controlled by W83L950D embedded controller using ADT7460 to sense CPU temperature and PWM control fan speed Fan speed is depended on CPU temperature Higher CPU temperature faster Fan Speed 1 4 7 CMOS Battery CR2032 3V 220mAh lithium battery When AC in or system main battery inside CMOS battery will consume no power AC or main battery not exists CMOS batter
98. controller functions as a single slot PCI to Cardbus bridge and also PCI interface smart card and MS SD MMC flash card reader The 5 592 provide one Cardbus slot and all reader interface may operate simultaneously The CH7011A is a display controller device which accepts a digital graphics input signal and encodes and 80500 N B Maintenance transmits data to a TV output analog composite s video or RGB The device accepts data over one 12 bit wide variable voltage data port which supports five different data format including RGB and YcrCb The TV Out processor will perform non interlace to interlace conversion with scaling and flicker filters and encode the data into any of the NTSC or PAL video standards The scaling and flicker filter is adaptive and programmable to enable superior text display Eight graphics resolutions are supported up to 1024 X 768 with full vertical and horizontal underscan capability in all modes A high accuracy low jitter phase locked loop is integrated to create outstanding video quality Support is provided for Macrovision and RGB bypass mode which enable driving a VGA CRT with the input data The W83L950D is a high performance micro controller on chip supporting functions optimized for embedded control These include ROM RAM four types of timers a serial communication interface optional bus interface host interface A D converter D A converter I O ports and other functions needed in control system con
99. in the final data phase FRAMEZ is an input to the ICH4 when the ICHA is the Target and FRAMEZ is an output from the ICH4 when the ICH4 is the Initiator FRAMEZ remains tri stated by the ICH4 until driven by an Initiator Initiator Ready IRDY indicates the ICH4 s ability as an Initiator to complete the current data phase of the transaction It is used in conjunction with TRDY data phase is completed on any clock that both IRDY and TRDY are sampled asserted During a write IRDY indicates the ICH4 has valid data present on AD 31 0 During a read it indicates the ICH4 is prepared to latch data IRDY is an input to the ICH4 when the ICH4 is the Target and an output from the ICH4 when the ICH4 is an Initiator IRDY remains tri stated by the ICH4 until driven by an Initiator Signal Name Type Description STOP Stop STOP indicates that the ICH4 as Target is requesting the Initiator to stop the current transaction STOP causes the ICH4 as an Initiator to stop the current transaction STOP is an output when the ICH4 is a Target and an input when the ICH4 is an Initiator STOP is tri stated from the leading edge of PCIRST STOP remains tri stated until driven by the ICH4 PERR yo Parity Error An external PCI device drives PERR when it receives data that has a parity error The ICH4 drives PERR when it detects a parity error The ICH4 can either generate an NMI upon detectin
100. internal pull up resistor RE Ring Indicate This signal is an input from the modem interface It can be enabled as a wake event and this is preserved across power failures SYS System Reset This pin forces an internal reset after being debounced The 4 will reset immediately if the SMBus is idle otherwise it will wait up to 25 ms 2 ms for the SMBus to idle before forcing a reset on the system RSMRST Resume Well Reset This signal is used for resetting the resume power plane logic Signal Name Type Description LAN_RST LAN Reset This signal must be asserted at least 10 ms after the resume well power VccLAN3 3 and VecLAN1_5 is valid When deasserted this signal is an indication that the resume well power is stable SUS_STAT LPCPD Suspend Status This signal is asserted by the ICH4 to indicate that the system will be entering a low power state soon This can be monitored by devices with memory that need to switch from normal refresh to suspend refresh mode It can also be used by other peripherals as an indication that they should isolate their outputs that may be going to powered off planes This signal is called LPCPD on the LPC I F C3_STAT C3_STAT This signal will typically be configured as C3_STAT It is used for indicating to an AGP device that a C3 state transition is beginning or ending If C3_STAT functionality is not required this sig
101. oe SAS 20408 18161818 anor iiaa 1 VA 0402 1 ___5 REP anier R435 1 AR 0402 4 13141922 SERIRQ gt SERIRQ Rasen GPlos 0175 3 2K 1 0402 1 SM D Rada 1 0402 5 3 FLX I eon 432K 1 RI 0402 1 MS BS T 32K 31 0402 1 5 SDO 32K 4 0402 1 MS SCLK C465 C463 35 245 RO aK 4 0402 1 SM_LVD 0 100 S br d 2506 0402 0805 G pg s scctoro s2oonbseces 63 sr shsBLB28523 888f 58 S SIRERERSS GOSRERSOCOCS Aw 0 204 04255 lt 295 25 4 amp 1212 5505050500 008520050555555555550 90 2065065598 4255669 566 99 94039585 500 253920909000009095 FREAK ORO 15 2 5 10K NA EE AGES 0402 BB585858554004929z22z222242244B8850B8 2 gt 444 2 AGES m SD_MSVDD 291000013027 C989 GND e BGA GHK 209 0714 154 DTC144WKINA 8 E Q24 1202 100 an R552 H 0402 5 2012 K 1 73 16V 273000150013 Ne 10 036 Multi Function pin need pull up 0 1808 P Pa R1214 0716 35 9 m 44243 2531 PWROK 2N7002 010 0402 CARD 02029 0402 10 R1217 d CCLIKRUN 16V 0 R1220 1 471 040
102. of the compartment Figure 2 1 ECCO 9 Figure 2 1 Remove the battery pack Reassembly 1 Replace the battery pack into the compartment The battery pack should be correctly connected when you hear a clicking sound 2 Slide the release lever to the lock position 47 80500 N B Maintenance 2 2 2 Keyboard Disassembly 1 Remove the battery pack Refer to section 2 2 1 Disassembly 2 Open the top cover 3 Loosen the four latches locking the keyboard Figure 2 2 4 Slightly lift up the keyboard and disconnect the cable from the mother board then separate the keyboard Figure 2 3 Figure 2 2 Loosen the four latches Figure 2 3 Disconnect the cable Reassembly 1 Reconnect the keyboard cable and fit the keyboard back into place with four latches 2 Replace the battery pack Refer to section 2 2 1 reassembly 48 80500 N B Maintenance 2 2 3 CPU Disassembly 1 Remove the battery pack Refer to section 2 2 1 Disassembly 2 Remove three screws fastening the heatsink cover Figure 2 4 3 Remove three spring screws that secure the heatsink upon the CPU and disconnect the fan s power cord from system board Figure 2 5 Figure 2 4 Remove three screws Figure 2 5 Free the heatsink 49 80500 N B Maintenance 4 To remove the existing CPU Loosen the screw by a flat screwdriver upraise the CPU socket to unlock the CPU Figure 2 6 Figure 2 6 Remove the CPU Reasse
103. of many enabled hardware or software events STPCLK Stop Clock Request STPCLK is an active low output synchronous to PCICLK It is asserted by the ICH4 in response to one of many hardware or software events When the processor samples STPCLK asserted it responds by stopping its internal clock RCIN Keyboard Controller Reset CPU The keyboard controller can generate INIT to the processor This saves the external OR gate with the ICH4 s other sources of INIT When the ICH4 detects the assertion of this signal INIT is generated for 16 PCI clocks NOTE The ICH4 ignores RCIN assertion during transitions to the 1 53 54 and 55 states A20GATE A20 Gate A20GATE is from the keyboard controller The signal acts as an alternative method to force the 2 signal active It saves the external OR gate needed with various other PClsets 89 80500 N B Maintenance 5 3 Intel 82801DBM Controller Hub 4 Mobile ICH4 M 7 Processor Interface Signals Continued Signal Name Type Description CPUPWRGD OD CPU Power Good This signal should be connected to the processor s PWRGOOD input To allow for Intel SpeedStep technology support this signal is kept high during an Intel SpeedStep technology state transition to prevent loss of processor context This is an open drain output signal external pull up resistor required that represents a logical AND of the ICH4 s PWROK and
104. phase C BE 3 0 define the Byte Enables 3 0 0000 Interrupt Acknowledge 0001 Special Cycle 0010 Read 0011 Write 0110 Memory Read 0111 Memory Write 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1110 Memory Read Line 1111 Memory Write and Invalidate All command encodings not shown are reserved The ICH4 does not decode reserved values and therefore will not respond if a PCI master generates a cycle using one of the reserved values DEVSEL vO Device Select The ICH4 asserts DEVSEL to claim a PCI transaction As an output the ICH4 asserts DEVSEL when a PCI master peripheral attempts an access to an internal ICH4 address or an address destined for the hub interface main memory or AGP As an input DEVSEL indicates the response to an ICH4 initiated transaction on the PCI bus DEVSEL is tri stated from the leading edge of PCIRST DEVSEL remains tri stated by the ICH4 until driven by a Target device 84 80500 N B Maintenance 5 3 Intel 82801DBM Controller Hub 4 Mobile ICH4 M 2 PCI Interface Signals Continued Signal Name Description PCI Interface Signals Continued FRAME Cycle Frame current Initiator drives FRAME to indicate the beginning and duration of a PCI transaction While the Initiator asserts FRAMEZ data transfers continue When the Initiator negates the transaction is
105. power management complies with Advanced Configuration and Power Interface ACPI 2 0 It also provides easy configuration through CMOS setup which is built in system BIOS software and can be pop up by pressing F2 key at system start up or warm reset System also provides icon LEDs to display system status such as AC Power indicator Battery Power indicator Battery status indicator HDD CD ROM NUM LOCK CAP LOCK SCROLL LOCK RF on off Card Reader indicator It also equipped with LAN 56K Fax MODEM 3 USB port S Video and audio line in out external microphone function The memory subsystem supports two expansion DDR SDRAM slot with unbuffered 1600 2100 DDR SDRAM The Montara GME GMCH Host Memory Controller integrates a high performance host interface for Intel Banias processor a high performance 2D 3D Graphic Engine a high performance memory controller Digital Video port DVOB amp DVOC interface and Intel Hub interface Technology connecting with Intel 82801DBM ICH4 M The Intel ICH4 M integrates three Universal Serial Bus 2 0 Host Controllers Interface UHCI the Audio Controller with AC97 interface the Ethernet includes a 32 bit PCI controller the IDE Master Slave controllers and Intel Hub interface technology 80500 N B Maintenance The MOBILITY M10 provides one of the fastest and most advanced 2D 3D and multimedia graphics performance for notebooks It s architecture introduces the latest achievements in the graphics
106. read data then it is not required to implement this signal During FRAME Operation This signal is not used during AGP FRAME operation Signal Name Type Description Signal Name Type GST 2 0 Status Provides ST 2 0 Meaning GRBF I AGP information from AGP the arbiter to 000 Previously requested low priority AGP Master on read data is being returned to the what it may do master arbiter to an AGP ST 2 0 only have meaning to the master when 15 001 Previously requested high priority read data is being returned to the GNT is aster GWBF 1 deasseried 010 The master is to provide low priority AGP these signals have no meaning and must be gnored write data for a previously queued write command 011 The master is to provide high priority write data for a previously queued write command Write Buffer Full indicates if the master is ready to accept Fast Write data from the GMCH When WBF is asserted the GMCH is not allowed to drive Fast Write data to the AGP master WBF is only sampled at the beginning of a cycle If the AGP master is always ready to accept fast write data then it is not required to implement this signal During FRAME Operation This signal is not used during AGP FRAME operation 100 Reserved 101 Reserved 110 Reserved 111 The master has been given permission to start a bus transaction The master may queue AGP requests by asserting PIPE
107. rz EET EU gt 48 0402 3 48 E 2 3 HOSTBN O E18 HL LCLKCTLA 002 RY av Be HOSTEN HDSTBN O HD S0 DEST HLIS WHEN USE INTEGRATE p E uec ha pap oe DEL R206 lt 5 5 19 HL S umm R206 2 HDINVH O 3 HD 54 855 MDDCCLK _____ DINV O 55 MDDCCLK 77 S55 MDDCCDATA m dd DINV 1 56 p19 HD 57 4VCCP a MDDCDATA 7 855 MDVICLK 0402 DINV 2 HD S7 14 STB HLSTB MDVICLK 855 MDVIDATA 5 A16 ogee 14 HUB_STB Ve 5 MDVIDATA Mo E16 MI2CCLK _______ 28 HUB VREF w1 855 ____ Pm y CERES OW ets _ VM amp HD 62 499 2 HDRDY DRDY 218 pss 0402 202 WHEN USE INTEGRATE 2 HDEFER S M25 DEFER HO 63 1 PANELBKLTCTL 4203 UNA BLADJ 1222 ADD R181 2 HHITM 2 HDVREF 13 PCIRST RSTIN PANELBKLTEN 8801 ENABKL NB 12 2 HHIT HDVREF 0 REGEL FA nEFSET PANELVDDEN FPVDEN 12 2 HLOCK 27 HDVREF 1 PSWING M23 2 R279 8 2KINA 14540402 855 ADDIDO 330 NA 1 1 2 0402 S HOMME Nos BREQO R208 855 DDDA PSWING
108. their outputs and latch their inputs BNR BNR Block Next Request is used to assert a bus stall by any bus agent that is unable to accept new bus transactions During a bus stall the current bus owner cannot issue any new transactions BPM 2 0 3 3 0 Breakpoint Monitor are breakpoint and performance monitor signals They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance BPM 3 0 should connect the appropriate pins of all Intel Pentium M processor system bus agents This includes debug or performance monitoring tools Signal Name Type Description BPRI I BRO TO Bus Priority Request is used to arbitrate for ownership of the processor system bus It must connect the appropriate pins of both processor system bus agents Observing BPRI active as asserted by the priority agent causes the other agent to stop issuing new requests unless such requests are part of an ongoing locked operation The priority agent keeps BPRI asserted until all of its requests are completed then releases the bus by deasserting BPRI BRO is used by the processor to request the bus The arbitration is done between the Intel Pentium M processor Symmetric Agent and the MCH M High Priority Agent of the Intel 855PM or Intel 855GM chipset COMPP3 0 Analog COMP 3 0 must be terminated on the s
109. vss 13 VSS 104 14 6 SMAB 1 2 309113 NE MDT4 AND voc 14 VCCSM 14 VSS 14 VSS 105 SMAB 4 5 SMAB T 5 0 14 NE MDIS VCC 15 VCCSM 15 58 15 VSS 106 6 SMAB 4 5 SMAB4 SMAB 2 0915 NE MDTE VCC 16 VCCSM 16 VSS 16 VSS 107 5 SDQI16 NE MDI VCCSM 17 VSS 17 vss 108 SMAB S 50017 NE MDIE VCCSM 18 VSS 18 VSS 109 B NE MDIS 1 35V VCCHL 0 VCCSM 19 VSS 19 vss 110 HN 6 NB E AD25 swey 099 NE MD2O VCCHL 1 VCCSM 20 VSS 20 vss_111 HE 6 NB CASE 2 scas 309120 NE MD T VCCHL 2 VCCSM 21 VSS 21 VSS 112 6 NB RAS AG 30921 NB MD22 VCCHL 3 VCCSM 22 VSS 22 VSS 113 509122 NB MD23 VCCHL 4 VCCSM 23 VSS 23 VSS 114 6 NB 500123 NB MDo4 VCCHL 5 VCCSM 24 VSS 24 VSS 115 6 NB BAT S AD20 0924 025 VCCHL 6 VCCSM 25 VSS 25 VSS 116 309125 NE MD2S VCCHL 7 VCCSM 26 VSS 26 VSS 117 6 CS40 2 sosto 09125 NB MD27 VCCSM 27 VSS 27 VSS 118 6 3 D26 scsi 09127 NB MD28 EE VCCDVO 0 VCCSM 28 VSS 28 VSS 119 6 542 gt 22 Sapa AGU NB MD29 VCCDVO 1 VCCSM 29 VSS 29 VSS 120 6 543 025 sesja 0929 4212 VCCDVO 2 VCCSM 30 VSS 30 VSS 121 309130 AEL3 VCCDVO 3 VCCSM 31 4 vss 3t vss 122 HH 6 CKEO sckE o 309131 VCCDVO 4 VCCSM 32 4 vss 32 vss 123 6 gt ABZ scKe 1 509132 VCCDVO 5 VCCSM 33 124 vss 33 vss_124 6 CKE2 9 5 2 309133 VCCDVO 6 VCCSM 34 4
110. vss 34 126 MO 6 10 scke a 509184 VCCDVO 7 VCCSM 35 M24 vss 35 vss 125 309135 VCCDVO 8 VCCSM 36 24 vss 36 vss 127 509136 VCCDVO 9 24 55 37 VSS 128 6 NB CLK SCK O 309137 VCCDVO 10 VCCTXLVDS E24 VSS 38 VSS 129 NB CLK DDRO 309138 VCCDVO 11 VCCTXLVDS 0 824 vss 39 VSS 130 6 NB CLK DDR1 SCK 1 309139 VCCDVO 12 VCCTXLVDS 1 AJ23 vss 40 85 131 6 NB CLK 309140 VCCDVO 13 VCCTXLVDS 2 55 41 VSS 132 6 NB CLK DDR2 SCK 2 50041 EE VCCDVO 14 VCCTXLVDS 3 23 vss 42 VSS 133 6 NB CLK DDR2 500 42 4 4 VCCDVO 15 023 vss 43 VSS 134 6 NB CLK 0083 SCK 3 500 43 VITHE 0 23 vSS 44 55 135 6 NB DDR3 sekje 509144 dupe pd VCCDLVDS 0 vrne o MVrrHE L AE22 vss 45 VSS_136 6 NB DDR4 SCK 4 30945 VCCDLVDS 1 vrrHE 3 pMES w22 vss 46 VSS 137 6 NB CLK DDR4 309146 i VCCDLVDS 2 vrrHE 2 Hea VEE IMA u22 vss 47 VSS 138 6 NB CLK 0085 SCK S 3097 VCCDLVDS 3 3 24 VEE B22 vss 48 VSS 139 6 NB 50048 e VITHF 4 4 N22 55 49 VSS 140 309149 VCCADAC 0 VSS 50 VSS 141 SMVSWINGH 509150 VCCADAC 1 0 VSS 51 VSS 142 asv pog 2 2422 SMVSWINGL 309151 VILE 1 VSS 52 VSS 143 o 509152 VCCASM 5 0 VILE 2 VSS 53 VSS 144 309153 VCCASM 1 3 VSS 54 VSS 145 4 500 54 VTTLF 4 VSS 55 VSS 146 4 3
111. 0 TRANSAO4410 N MOSFET ID 18A 0 0 PUI L PUI2 PUI3 PUT712 291000622007 CON DIMM R A 200P 6 H9 2 REVERS 28820440900 5 04409 50 8 MSL 03 05 291000256843 CON IC CARD 68P UP 5 0 0 291000811008 JACK 2 IN 1 7 0MM ALLT 288204900001 A04900 DUAL N MOSFET WITH PU4 PU6 PU702 PU705 PU707 P 294011200069 LEDGREEN 9 21VGOTRALED CLIQ 294011200069 LEDGREEN IO 21VGCTRALED CLIQ 295000010140 FUSE FAST 2A 63VDC 1206 SMT 0433 144 N 288221371002 TRANSMUN2137T1 PNP SMT ON 013 0711 291000251246 SOCKET 124P R A 0 8MM H 291000920605 5 JACK 6P W9 5 33184000 719 721 294011200016 LED GREEN H0 8 0603 CL 190G SMT D32 D33 D34 D35 D36 D37 D38 288227002006 TRANS2N7002LT1 N CHANNEL FET ES 1 012 014 016 017 01 291000000029 CON MINI 4 IN 1 SOCKET CONNECTOR J2 ON 291000000706 CON BATTERY 7P MA 2 5MM R A C103 291000010209 CON HDR MA 2P 1 1 25MM H4 2 ST S 288204435003 T SFDM4435 P MOSFET 35mOHM SO Q9 U704 U707 288204800001 T S SI4800DY N MOS 0185OHM SO PU710 U7 HDR 291000010308 291000010619 CONHDRMA 6P ACESS7151 06075M ____ 291000013025 connor Ma 1sP 2AcEss8107 3000 _____ 5 291000000203 CON HDR MA 2P 1 3 5MM R A SMT SM 2 80500 N B Maintenance 9 Spare Part List 9 escription FUSE FAST 3A 32 VDC 1206 SMT 0433 FUSE NORMAL 7A 24 VDC 0433007 120 FUSE FAST 1 7
112. 0 1 1 1 0 828 1 0 0 1 1 0 0 0 1 324 1 1 1 0 0 0 0 812 011001 1 308 iva 2 9 X 0 796 0 1 1 0 1 0 1 292 111 9 1 0 0 780 6 CP 1 1 9 Y 1 476 111 0 1 1 0 764 0 1 1 1 0 0 1 260 111 1 0 0 0 748 01110 1 1 244 111 1 3 0 732 D 1 232 111113 0 700 80500 MOTHER B D lev PCB 316680900001 ASSY 411682700001 Rot lumber Date Wednesday December 31 2003 Bheet 3 o 34 I PDF created with FinePrint pdfFactory trial version http www fineprint com AD O 31 855 DVOBHSYNC PAGP 0 31 724 DVOBVSYNC U714B 6 855_ADDIDO ES pa 855 DVOBOLK 2 31 6 2 855 ADDIDT 5 ADDIDIO DVOBCLK p4 855 855 DVODETECT H27 HD
113. 0 Bg BY S gt AMP_RIGHT 21 aha 300 aa 22 VREFOUT mo L Cl 77 1 4 1 655 010 10 AGND R1126 R1129 POFP48_0 5MM 0402 0402 27KIN 27KINA R1124 1 af 10 of 80 20 0402 0402 16V tov 5 5 rien lt lt G D AGND FTT 21 sprout MIC VREF AGND 5 8532 1 2464 VREF Kaioa mer 2 273000130006 RN BEAD 6002 100M sran LINE IN 1 L53 1 0603D 4 tA ate LINE IN R i s 1 55 176 1 A 6030 3A at aha f T 1 J BEAD_600Z 100M C159 C499 4 100P NA 2 R325 2 520 8 RA D6 6P 0402 0402 22K 22K 100 25 58201403 41 10 410 5 0402 0402 040 CONN 682014 5 50 yon 291000920605 MDC E 2717 MONO_OUT 1 AGND T a 4 1 811341 MODEM SPK 73 5 6 0402 5 if kr d 1202 100 RT 1608 AGND 10 1 C913 CAGND 43V 36 1 2 010 4 91132 0404 0402 1 18 1 10 1 1 1 18 4fR E NZ 10 1202 100 L 19 0 1 L725 V 1 2012 1 ACSDOUT 71 22 542 0402 A SDINT 5 5 tj 1211 0402 KACSDINI C148 1 1808 1000P 2 10 8 1 1 9 30 81120 1 5 2 0402ACBITCLK 715 R849 C806 1 1808 10006 2 10 927 560 2010 NA 010 VOMM 4 4 1 1724 0805 MODEMP oe WERA T aas TS au o 18 0 10V 30V 1K HDRMA 2 4 4 GND_45 0402 0402 ACES
114. 0 MEMA MATS MEMA DOMIS Rita 3 A Nese 0405 VOMAR 014 0013 LANA 7 10 9 15 DGATE MANUS TAN MEMA QSA0 109 1 24 5 2 0402 VOSAO MEMA 11016 DOAIS 25 MEMA DOM O AM 0402 VOSAT MEMA 14077 00 16 E29 MEMA DOMEI MEMA OSA PaT NN 02 VOSAS MEMA MDI 17 DOMAH E25 MEMA DOMP MEMA OSAS RI0S 0402 VOSAS MEMA MD18 00418 2 DOMS 0544 R720 1 A e Dd VSN 14020 19 Pie MEMA DOMA AM MEMA QSA5 _ 8731 1 0402 VOSAS MEMA_MD21 F23 G15 DOM MEMA QSA6 R732 1 PAN 0402 VOSAS MEVA 122 Daha MEVA 00086 MEMA QSA7 R717 1 39 2 0402 VOSAT E11 MEMA DOMI MEMA MD24 7 AM 127 MEMA _ MEA MDA 00425 EST MEMA OSAT _ 27 DOA26 V 13 _ Bag 00427 MEMA OSAS AM vmaA o 13 10 MEMA_MD29 Dane MEMA 5 4 MEMA 12 12 _ 30 29 95 _ MEMA 13 MATS MEMA_MD31 DGASO GSAS MEMA 5 TAN MEMA MAD MEMA MD32 Daas QSA6 E10 MEMA AM MEMA H MEMA MD33 DGAsa MEMA_MD34 Dass A19 MEMA RAS _ VMATO MEMA MD35 DGA RASAK VMAS MEMA_MD36 Eig MEMA CAS AM MEMA MEMA_MD37 DGASE
115. 02 VT6307L 18020 3 E PQFP128A 0 5MM 7 2 2 0 4 wire EEPROM interface Default EE 1 2 wire I2C EEPROM interface A E 274012457 using SCL SDA GND 1394 AGND C932 C929 I2CFAST I2C EEPROM Fast Mode 10 10p 0402 0402 0 Disable Default 5 P 1 Enable GND GND CARDBUSENA CardBus Mode 0 Disable PCI Default 1 Enable PHYCMC Programmable Contender Bus Manager Capable High specifies that the node is capable of being a bus manager 81149 1 0402 5 1740 1202 100M T CORE 25200 1 TPBs 6307 TPES 3 2 x 1 343 1148 1 ANA A 2 0402 5 413 R543 1 2 0402 5 ERA TPA 6307 1 E E TPA D28 0711 0706 4PX1 0 8MM MA 6307 4 MOLEX 12027100M 1 3053 4048 JOS2 1049 54030 0411 2012 183 202805 ESDOB0SA NA 331000004008 1202 100 187 CORE_ACM2520U d 4 4 GND 1894 AGND 1202 1 0 2 2012 Because of notice change LAMA 1 x 1394 GND GND L547 to 0 ohm 0805 1384_GND X M 1384 GND 80500 MOTHER B D Bie lev 316680900001 ASSY 411682700001 lumber Date Wednesday December 31 2003 Bheet 18 of 34 PDF created with FinePrint pdfFactory trial version http www fineprint com MINI PCI FROM LYNX AMD
116. 02 R24 8P JRPILRPIZRPISAPITARPISAPI 271611750301 RP 75 4 1 16W 5 0612 SMT 272001475701 140 Part Number Description Location S 271071127011 RES 127 1 16W 1 0603 SMT R163 271071131101 JRES 130 1 16W 1 0603 SMT 271071152302 1 5 1 L6W 5 0603 5 271071152302 1 5 1 16 5 0603 5 6W 1 0603 SMT 6W 1 0603 SMT 301K 1 16W 1 0603 SMT 6W 5 0603 5 6W 5 0603 SMT 6W 5 0603 SMT 16W 5 0603 SMT 1 16W 5 0603 SMT N fe 8 3 N gt alala W eer ES lt 2 amp gt 6W 5 0603 SMT 271071362101 RES3 6K 1 16 1 0603 5 271071374812 RES37 4 1 16W 195 0603 SMT R898 RES 4 32K 1 16W 1 0603 5 yo RES43 2K 1 16W 196 0603 5 271071472302 RES 4 7K 1 16W 5 0603 SMT 271071478101 RES4 7 1 16W 1 0603 SMT PR108 PR109 PRI10 PR2 PR3 PR 271071487011 RESA87 1 16W 1 0603 SMT MUS RES 48 7 1 16W 1 0603 5 271071499011 RESA99_ 1 16W 1 0603 SMT RES 499K 1 16W 1 0603 SMT RESS6K 1 161 19 0603 SMT RES 620 1 16W 5 0603 5 ZI gt gt gt 4 110 R10 17 6 80500 N B Maintenance 9 Spare Part List 5 escription CAP 100P 2KV 5 1206 NPO
117. 09155 LA VCCGPIO 0 VILE 5 VSS 56 VSS 147 9328 MCH SMRCOMP 506156 VCCGPIO_1 6 VSS 57 VSS 148 DU SESTA sMRCOMP 309157 VILE T VSS 58 vss 149 M 80 20 50058 E 0 VITLE 8 121 vss 59 VSS 150 50 50059 5 _1 9 VSS 60 VSS 151 SDQ 60 VTTLF 10 jr VSS 61 VSS 152 9ND 50061 VCCADPLLA VITLE 11 821 55 62 vss 153 0 me BE 509162 VCCADPLLE VITLF 12 021 vss 63 vss_154 08 Tra 50063 VIILF 13 821 vss 64 55 155 8 nsvpre 506164 14 120 vss 65 53 156 Reyna 500 65 eh 029 VGCAHPLL 15 2 1 vss 66 VSS 157 O 1 _7 nsvp 4 509165 VCCALVDS 15 D vss 67 VSS 158 309167 VecaLvps VITLE 17 0 vss 68 vss_159 i 509 68 M VTTLF 18 o D vss 69 VSS 160 4 500169 P db d E 19 ves 70 vss_161 AC4 7 GCBE2 s 50070 Dus n VSSALVDS VITLF 20 3 vss 71 vss 162 Ph SbQ 71 pe 4 9 5 72 vss 163 W 7 0510 _ 4 NB 0990 8 SVO yssapac case caos 019 vss 75 vss 164 14 7 GSTI e 500510 OT dev dev VSS 74 VSS 165 7 GST2 2 02 6512 Sbos i 855GM GME Peer tone VSS 75 55 166 4 5005 2 GNB VSSADAC BGA707_25 VSS 76 VSS 167 7 GSBSTB RSVD 6 50098 S 58 77 VSS 168 7 GSBSTBA Fi RSVD 7
118. 09701001 IC RT9701 POWER DISTRISW SOT23 0701705 284508100009 IC RTL8100CL LAN CONTROLLER LQEP 021 284582801044 82801 4 421 0715 28636922930 oaoa o 288100032013 DIODE BAS32L VRRM75V MELF SOD 80 D24 D7 PD5 288100054001 143 284583950002 IC W83L950D Ver C LPC_KBC LQFP 8 284595081201 ICIICS950812 CK408 CLOCK GEN TSS 286002040001 IC BQ2040 GAS GAUGE SO 16P SMT 736100212001 286100393004 286100822002 ICLMV822 0P AMP DUAL CMOS MSOP 286104173001 ICMAXA173E I SENSE AMP SOT23 6P 286104871002 ns 286300431014 ICSCASILCSK 5 5 ADIREGSOT 286300594001 IC TLS94C PWM 5016 286300690001 CIRCUIT 293VS 3 286300710002 IC CB710 CARDBUS CARD READER LFG 286300812002 IC S 812C DECECT OR SOT 89 PRC 286301117021 IC AMS1117 VOL REGULAT OR 1A SOT U6 286301414001 IC MM1414 PROTECTION TSOP 20A PR IC4 80500 N B Maintenance 9 Spare Part List 8 Q12 023 026 027 029 031 0324 TRANS RA RA RA 291000013027 291000020204 CONHDRMA2P I3SMMRASMTSM 291000020206 291000021105 CON HDR MA 11P 1 ACES87213 1100 HDR HDR HDR 291000021105 CON HDR MA 1 IP 1 ACES 87213 1100 291000023011 CON HDR MA 15P 2 88031 3000 ACES 291000152603 CON FPC FFC 26P 1MM R A KBD SMT 0 D 291000023008 CON FM 15P 2 0 8MM HS R A SM D 291000614793 IC SOCKET UPGA479M 479P MOLEX 28820441001
119. 1 0402 CASE NB CASE 11555 11562 11062 5 NB_CAS NB RASARS70 1 AP 0402 RAS RAS 14058 1063 14063 Fed NB BAD 10371 AYANA 2 0402 BAO 65 5 NB BAT NB BAT 871 p 2 0402 BAT 1114 SMBDATA 3 Sepa TA EY 5 SMAI 11 14 SMBCLK 5 CS 5 SMA2 H 5 4 MCBS RN 5 SMA4 Hex 0 6MM 200P H9 2 0 6MM 200P H5 2 5 SMAB2 5 NB DDR1 QUASAR QUASAR 5 CAQ145 200N01 CA0115 200N01 5 SMAB4 0 EMABS L3 5 NB CLK DDRI 5 SMABS 5 NB_CLK DDR2 5 5 NB CLK_DDR2 5 1 5 NB DDR3 Ed EA 5 CKE2 NE MAE 5 NB CLK 5 5 0084 5 4 55 3 5 NB CLK 0094 5 5 1 1 pn C E 5 NB DDRS 5 5 2 20 CSHB NB MATO G 1 25 DDR 1 1 4 1 5 NB NE EAT 25V ii y a case TL caas TL EF 1 3 9 T 0805 osos 0402 0402 0402 gt 2 amp 1 C401 63V 63v 28020 8020 8020 4 2 d 51 1 cass 389 Caso cage C391 0402 R3407 C346 0 01 0 01 0 01 0 01 0 010 0 010 80 20 0 10 DDR_VREF GND 0402 0402 0402 0402 0402 0402 50 480 208 80204 280204 80206 280204 80 20 80 20 Per xj GE 50 0010 C394 C397 C400 C403 C409 C408 0402 a 0 0107 0 010 0 0107 0 010 0 010 0 010 180209 C384 0402 0402 0402 0402 0402 0402
120. 1 4 4 LED Indicators Three LED indicators at front side From left to right that indicate BATTERY POWER BATTERY STATUS and AC POWER ACPOWER This LED lights green when the notebook was powered by AC power line Flashes on 1 second off 1 second when entered suspend to RAM state with AC powered The LED is off when the notebook is in power off state or powered by battery BATTERY POWER This LED lights green when the notebook is being powered by Battery and flashes on 1 second off 1 second when entered suspend to RAM state with AC powered The LED is off when the notebook is in power off state or powered by AC adapter 36 80500 N B Maintenance gt BATTERY STATUS During normal operation this LED stays off as long as the battery is charged When the battery charge drops to 10 of capacity the LED lights red flashes per 1 second and beeps per 2 second When AC is connected this indicator glows green if the battery pack 15 fully charged or orange amber if the battery is being charged AC POWER This LED lights green when is powering the notebook and flash on 1 second off 1 second when Suspend to RAM no matter using AC power or Battery power The LED is off when the notebook is off or powered by battery BATTERY POWER This LED lights green when the notebook is being powered by Battery and flash on 1 second off 1 second when Battery is low The LED is off when the notebook is off or powered
121. 1 5 for future support GND pocument 316680900001 ASSY 411682700001 Rot lumber Date Wednesday December 31 2003 Bheet 2 of 34 1 PDF created with FinePrint pdfFactory trial version http www fineprint com CPU BANIAS 2 2 1 05V 2 4 9 4 sach US cese cas7 c220 187 1 l E 100 100 100 100 100 100 100 1 057 07130 Noon 5 73 za 0805 0805 0805 0805 0805 0805 0805 mus 188 74 63 lt 63 63 d 63V of 63V of 63V 63V VCCP 1 VSS 147 55 3 vss 76 VCCP 2 VSS 148 VSS 4 vss 77 VCCP 3 VSS 149 58 5 vss 78 AND VCCP 4 VSS 150 VSS 6 vss 79 26 pe 56 2 VCCP 5 VSS 151 66 7 VSS 80 VCCP 6 VSS 152 VSS 8 vss ei H VCCP 7 VSS 153 vss e VSS 82 VCCP 8 VSS 154 VSS 10 vss as 1 1 55 84 L 1 1 cies I L
122. 1 C385 0 1U 30V 0 1A 110 8 3 Display 5 CPU Core does not exist 80500 N B Maintenance DD_CPU 2 PLS n 51 DVMAIN VAGAVDO 1202 100M 51 S p YS o PL4 120Z 100M nag PUO 1 51 i FDS6694 FDS6694 24 A G 5VS_P H PR5 10 29 2 5 740 T PR4 10K 31 0 68UH dodi VCC_CORE e e E le oe P31 PUI2 PUI3 STOP_CPU m 0 4 FDS6694 FDS6694 FDS6694 21 G kH A PD718 5 5 EC31QS04 TE12L 5 lo E VIDO PR52 0 13 23 PR44 0 14 22 12 i PRI04 0 5 LTC3734 ie vos 0713 VID2 PR40 0 15 45VS P e 3 VID3 PR34 0 17 VID4 PR33 0 18 BANIAS VID5 PR31 0 19 9 VCC_PWRGD PRT MMBT3904L 59 PR57 gt h 18 A 43V PU703 1000P 100K LTC3728L 3 PR28 576K Vos PR731 PR29 2K 3 R831 D pn 133K ss 1 28 R821 PR56 5 S 7 0712 0 0 PD4 81 CLK V BATS4C 5 L 58 7 PCM GEN 4 12K 2 gt 10 1000P PR60 i 51 EE e 1 5950810 43 2K 1 DVMAIN POIO gt PR49
123. 10 e 10 C978 G10 G5 50V 50V 50V 50V DTC144TKA ES 1U NA 288202240001 0402 AGND TSSOP24 0102 aoe 10V AGND AGND _ AGND AGND 80 20 CAGND C GND 0713 AGND DTC144TKA 288202240001 DECT_HP OPT DEVICE 45VS SUBAMP 45V 9 Lea C471 1 2 0603 ST 1202 100M 1000P 10 2012 06 1 SUB OUTR od ee ESDO603 NA R112214 20 4 SUB OUTL 1 0603 4 AGND k gt 4 C487 E 1 3010 B521 1 4 FN T BYPASS 7 1 2N7002 NA SHUTDOWN __017 K 251 SHOWN 1U NA R471 28 0 ND m 10V 1MNNA 5 2 0402 RLS4148 05 0805 0402 Rast DEVICE DECT Dig k 1 ER 5 04 RLS4148 J a Guns ESD0603 NA J705 AGND AGND SUN co417 T i 144871 2 0402 AJU LLPBA 80 20 80 20 80 20 F Nv 10V 0805 R26 1 0805 HDRIMA 2 AGND R27 31 0805 ACES H 85204 0200 2464VREF1 3 291000020204 R509 SUB_OUTL AGND 20 SUB LEFT i AGND AGND 22 1K 0402 1 U19A E LMV822 MSOP8 R510 DTC144TKAINA 20 zasa VREF Y 1 2 0402 1 2464VREF1 22 0402 1 036 AGND 2N7002 NA 2464VREF2 9 1 042 22 1K 0402 1 8459 6 SUB OUTR SUB LEFT R491 1 2 0402 5 SUB OUTL DE amp sUB OUTL 20 EE SUB OUTR S bRGHT RIN 2464 SUB_RIGHT R512 1 2 0402 5 SUB OUTR SUB 20 MiTAC 4 LMV822 MSOP8 rie 80500 MOTHER B D Brze 316680900001
124. 10 100 0010 7 142 53 DDR 425VS DDR 16V 0402 16V 0402 i 1206 80 20 1206 80 20 i 50V 507 CHANGE TO 0402 CHANGE TO 0402 Gu ne i R945 R942 010 GND GND i 604 150 0402 i 0603 0402 80 20 i 1 1 50V i Clock config bit GST 1 0 _ SMVSWINGL 4 SMVSWINGH swmcowP 255 DDR 2 5 3 DDR i PSB Sys Mem Core GFX Core 1 C857 R946 cass C846 s CCTXLVDS 1 CHANGE 0402 0 10 f 142 1729 0402 CHANGE 0402 0402 1202 100 4 2 5 10 1202 100 J 80 20 80 20 80 20 c227 C860 C859 3 1 00 def 400 266 200 133 200 1 50v 50v 50v 1 10U 10U 0 010 470 0 010 gt 16V 0805 0402 1730 0603 0402 1 400 200 200 100 200 1206 63V 80 20 1202 100 63 of 80 20 GND GND GND 10 sov 80 20 50V 8050D MOTHER B D 10 400 200 133 100 133 i 6 Document steseos00001 ASSY 411682700001 E 1 GND GND Number Date Wednesday December 31 2003 Bheet 5 of 34 PDF created with FinePrint pdfFactory trial version http www fineprint com
125. 100 R846 1 10 ____0402 9232 1 00 0 Reas 1 30K NA 0402 R215 4 2 0402 M D R221 1 106 0402 14 100 lt I 14 MB ID1 lt lt 14 102 ao 0402 1 ROPE 2 1 0402 R906 1 aAa 2 042 AGP PULL HIGH WHEN USE INTEGRATE VGA DEL ALL RESISTOR 1 5V 9 100K 827 0402 5 AD30 47 100K 1 R8BAGa 2 0402 5 amp AGP AD13 47 GND 2 5VS_DDR 2 5VS_DDR_P 9 9 45708 SHORT SMT4 45709 SHORT SMT4 JS710 e SHORT SMT4 3VS 3VS_P 9 9 1 25V_DDR 1 25V_DDR_P 18711 9 9 1 lt gt 2 4511 SHORT SMT4 lt gt T JS713 SHORT SMT4 4512 T D SHORT SMT4 45715 SHORT SMT4 e SHORT SMT4 1 8V 1 8V_P 9 9 48716 55 45VS P T lt gt 1 9 9 SHORT SMT4 JS717 JS718 1 lt gt SHORT SMT4 SHORT SMT4 45719 1 4 2 1 35V 4135V P o o SHORT SMT4 48720 5721 1 T 1 lt gt SHORT SMT4 SHORT SMT4 45722 e SHORT SMT4 1 2V 1 0V_M10 VGA 1 2 1 0 415V 9 9 48723 18724 1 lt gt 2 SHORT SMT4 SHORT SMT4 48725 18726 1 de SHORT SMT4 SHORT SMT4 JS727 1 05 9 9 SHORT SMT4 1 05 18728 SHORT SMT4 45729 SHORT SMT4 JS730 gt SHORT SMT4 Mitac gt 80500 MOTHER B D C PCB 316680900001 ASSY 411682700001 Date Wednesday December 31 2003 Bheet 24 34 PDF created with FinePrint pdfFactor
126. 100U 6 3V M 9 3 3 6 55 105 466 474 489 951 CP 47P 4 8P 50V 10 1206 NPO S FERRITE CHIP 1200HM 100MHZ 1608 9 L20 L38 L42 L43 L45 L56 L L MHZ 2A 1 L13 L14 L16 L50 L52 L53 L55 L3 L J gt 273000150307 FERRITE BEAD 120 OHM 100MHZ 3A 0 273000150313 CHOKE COIL 900HM 100MHZ 20 2012 273000500092 CHOKE COIL 2 2UH_ 20 16A 3 5MM 273000500115 CHOKE COIL 400uH MIN 120mQ 273000610025 FERRITE ARRAY 1200HM 100MHZ ONLY 273000620001 FERRITE ARRAY 6000HM 100MHZ 2520 273000990021 INDUCTOR 33uH CDRH124 SUMIDA SMT 273000990054 INDUCTOR 10UH D124C 20 T OKO 283467540002 IC EEPROM M93C46 WMN6T 64 16 BIT U722 U723 283767540001 IC K4D263238E DDR SDRAM 4MX32 BG U1 U3 U708 U709 142 80500 N B Maintenance 9 Spare Part List 7 Part Number Location S 283767540002 IC EM6A9320BI 3 6M DDR SDRAM AMX 283767630002 IC HY8250128323 DDR SDRAM 4MX32 286301470001 286303107001 IC AMS3107C 3 3V 1 VOL REGULATO 286303728002 IC LTC3728LX PWM CTRL LTC 5X5 QF PU14 PU15 PU2 PU703 284500522001 IC 855GME GMCH NORTH BRIDGE BGA 284500655003 IC ALC655 AUDIO CODEC LQFP 48P S 284501014001 MOBILITY M10 P A14 AGP BG 710 284502779001 IC P2779A EMI REDUCTION SO8 711 284506307001 IC VT6307L PCI 1394 2PORT LQFP 1 0724 286303734001 IC LTC3734 PWM CONT ROLLER 32 QFN PU3 286309167001 ICRT9167 47CB200MA LDOREGULAT 08 284507460002 IC ADT 7460 TEMPERATURE MTR QSOP 2863
127. 11 18 2 T YW 0402 R810 DO THERM ERR 2225 257962 1 10 R314 0402 5 271061180101 0402 5 lt gt VDD3S GND GPIO CHARACTERISTIC LIST NAME POWER PLANE CURRENT DEFINE R809 10K 5 certo T MAIN POWER WELL CRT_INF 0402 5 A6 GPITIT MAIN POWER WELL SB_CARD_PMEF 21 MAIN POWER WELL 1_1 USBOC4 D7 ceris MAIN POWER WELL PCI INTFK usBocsi t ePri4l MAIN POWER WELL PCI_INTGF 1 5V 1 5V GPI 5 I MAIN POWER WELL PI STRAPPING GPI S MAIN POWER WELL AGPBUSY R883 b T 1 GP MAIN POWER WELL KBD US JPf 15 487 130 0608 43V i GPITS RESUME POWER WELL R900 1 1 9 1 VSWING R1113 0402 i AAS GPI 11 I RESUME POWER WELL SMBALERT Pull high only ACSDOUT 4 47KNA 5 5 12 RESUME POWER WELL SCI 487 R884 R92 150 150 EE DOUT w3 GPI 13 I RESUME POWER WELL WAKE 0402 0402 1 OD ot i 1 1 R813 47K NA 0402 5 16 MAIN POWER WELL x i cs 17 o MAIN POWER WELL x GND GND 2 8 MAIN POWER WELL STOP_P VHLICH R275 0402 9 1 620119 POWER WELL SUSA 1 47KIN 5 Wid 620120 o MAIN POWER WELL STOP CPUS U715C 1331 DPRSLPVR 1 POET 1 ibas m PET CERE MAIN POWER WELL C3_STAT
128. 2 CARD ACT 5 R1221 32K 1 RI 0402 1 SDCD R377 94028083 10K 2 4 0402 1 SD SD_PWREN 10K 0402 32K 4 0402 1 MS_INS 0402 SD LED 2K 1 0402 SM MS_PWREN E xav e B 9728 82 1 0402 SM WPOF 43k MS LED VCCD1 VDDPO 4CARD VCC oa 14 3 3VB AVCCA 4VPPOUT xd 2 SV AVCCB 9 5VB avecc Hi o GND AVPP 4 SD MSVDD 1 d 52 550916 4 _ 1 RY 0402 1 sos casa coos 1 coas 1 coos 1 E C1001 C1002 1 0402 1 SD 01U 010 0 10 0402 0402 286302211006 22U e dU 32KNA 1 0402 1 SD CLK 0402 0402 0402 0402 0402 0402 0402 0402 lt 10 10 7 0603 0402 10 10 10 10 10 10 10 10 16V 36V 10 80 20 4 RH 0402 1 500 36V 16 36V 16V 16V 16V 1 16V 16V 10V E 2K 1 0402 1 501 80500 MOTHER GND GND GND GND 3 2K 31 0402 1 502 GND 316680900001 ASSY 411682700001 Rot lumber Date Wednesday December 31 2003 Bheet 17 of 34 PDF created with FinePrint pdfFactory trial version http www fineprint com 1394_AVCC Because of TEEE1394 VT6307L
129. 2 ADI1 SD_DAT3 16V 16 CAD21 23 57 Teg 012 CAD22 5 24 58 Teg CSERAF Anis PEPER ETE SM PWRSEN Rii922 1 1 0402 CAD23 25 59 eo CREOF Hio SM RI241 17040 24 015 SM_WPD CAD25 27 61 6 CAUDIO 016 SM SM_WP TP707 CAD26 28 623 CSTSCHG 017 SM SM CER CAD27 29 63 Teg CAD28 018 SM CAD29 31 30 64 Tee CAD30 Hi Ri2422 1 040 R2 D2 5 66 CAD31 SM CDF COCLKRUNS 33 amp 2 AD21 SM SM REF mE 67 AD22 SM K14 34 58 AD23 SM wes K18 024 SM i ND 1 RH AD25 S GND2 026 SM_CLE HUM so AD27 SM DO SM SD en GND4 1324 poi 21 14788 11931 2 5 AD28 SM Di SM 502 GNDs 29 SM D2 SM 503 ES GND6 AD30 smps Mia S op tO GND PCI INTC SM 504 8 19 26 poi iT S MIS sM 9 3 5555 1 1275 13 19 24 PCI 1 2 0402 CARD __ 12 MFUNCI 18 S557 1 6 176 SERIRQ nus cis MEUNCS SM_D7 V MF 291000000008 EUR E14 ca Nor N14 291000256843 GND PCLKRUNE 048 SC_PWRSEN 1196 13161924 PCLKRUN VOCE ENI
130. 2 PC75 PC750 PC754 753 757 PC752 po7si 3 3 STOP_CPU 0 41 100 100 100 100 100 100 0 010 PJL9 4 abe 1000P 1210 1210 1210 1210 1210 1210 0402 NET20 PR32 59 0402 25V 25 25 25 25 25V 10 20 20 1 20 4 20 1 20 1 20 2 20 SV H 0402 PC9 50V 5 0805 VA PC58 m 1 ill XR GND 1000P IL pois i GND 0402 100P PR30 PC18 ej 20 0402 100 1000 Nr 50V lt 410 0402 0402 4 GND_A E E 7 50 vosi 1 58 Pott dd 80 20 220P k i ined GND PROB 0402 Saou EF SERS B D Pus D PUB Puto PRIS 576K 10 8 8 FDS6694 FDS6694 NA FDS6694 1 0402 50V ug 508 s 508 508 1 1l uoa 24 4 4 4 VOA sw 23 4 OAQUT PVCC 4 SGND 20 EA SENSE H2 pi d tet qa 4 vipa H 0 68UH RDPRSLP H IHLP 5050CE 0402 PR39 29 b dada d 15 51 7 1 2 32K 2 Sera 4 44 51 7 0402 4 D 12 p 5 l 2200 7243 0402 1 3 m UM FDS7788 FDS7788 FDS1788 1 7243 2V za aa 4 PR31 5 508 8 508 8 508 gt J 4444444 5 all IH 0402 4 2200 5 7243 GND_A s s E PD718 2v PRIS 4 44 4 NEP 062010 x 1 wks 0402 Rad 4 SES TS BZVESCVA NA IL pcie 2V 2V A
131. 24 0024 GND 0024 GND 0024 0025 2 0025 VMIDASS nea 0025 VMIDB26 9 4 0925 S12 5 0926 ol 0026 VMIDASS 2810 nes 0026 VAIDB27 910 nics 0026 Gi SS 9 NC6 6027 12 9 0027 VADASI 9 VDIMB X KHH nce 27 812 9 VDIMB 1 X nce 27 812 A9 dj amp 28 0028 VMDAGT 0028 VAIDE29 poze 9 Ee NCB 0029 Fag VMDA30 poss 62 veses NOB 0029 __ veses NOB 0929 _ VMDB62 9 vesaii S gt YESAHT 0930 d 9 0830 88 yupaes 9 voss 8 13 0030 25 9 55 5586 13 Nco 0030 A7 VMDB63 DOS Faia VOSAS DOS Faia VOSA7 DOS Faia VOSB3 0931 a12 VOSB7 VSSITHt 0053 5 1 0053 1 0053 VSSTHt 0953 VSS TH2 VSS TH2 VSS TH2 VSS TH2 VSS TH3 12 1 8 VSS TH3 Ai2iREU VSS TH3 12 1 8x VSS TH3 AiziREut 8x VSS TH4 BA2 RFU2 19 VSS TH4 BA2 RFU 1 VSSITHA BA2 RFU2 Hx VSSITHA BA2 RFU2 Hx VSS THS VSS THS VSS THS VSSTHS VSS TH6 VSS TH6 VSS TH6 VSS TH6 VSS TH7 VSS TH7 VSS TH7 VSS TH7 VSS THB VSS THB VSS TH8 VSS TH8 VSS TH9 VSS TH9 VSS TH9 VSS TH9 VSS TH10 VSS TH10 VSS TH10 VSS TH10 VSS TH11 VSS TH11 VSS TH11 VSS TH11 VSS TH12 VSS TH12 VSS TH12 VSS TH12 VSS TH13 VSS TH13 VSS TH13 VSS TH13
132. 26 of 34 PDF created with FinePrint pdfFactory trial version http www fineprint com P 3VS_P 5VS_P 1574 PL701 ld anne 2012 T SHORT SMT4 1202 100 L 0010 0402 10 1 4 GND 4 1 100 70 1210 100 JP 0010 25 1210 4 4 0402 20 X5R 25V 1 PC708 PC705 10 20558 PC706 0010 100 50v 1000P 0402 1210 GND 0402 lt 10 25 10 50V 20 XER PRS GNO PR2 50V 1 056017 1 lt d 47 47 brd GND 0603 0603 GND Awss 1 2 H PR PCB m 58 PO 1 1 H 0402 JP gt dev 4900 4 4 SOS Pedo 1206 4 Tol 4 4 04 PC707 4 8020 0 1U 0805 50 0805 D PU701A 0402 10 4 10 AO4914 w GND 44 8444 LTC3728L s 508 E HVQFN32 1 4 z GND 45899324 KET PRIM a E PR707 savs_p 97 T T T 8 swt Neus tA 5 2 703 LI swa H
133. 31 5 28 97 120 gt 32 _1394 2 SK 0722 PCI AD21 R1117 100 108 31 EEDI 1394 3 DI m 93C46 P13 _ 0 3 4 15 107 122 P18 30 EEDO 1394 4 123 126 PCI FRAME PCI DEVSEL PCI TRDY PCI IRDY 0715 4 PCI 1 PCLINTG PCLSTOP PCI gt PCI PAR 3 ICH4 4 0724 4 PCI_PME 37 70 6307 1 _ 3 JL2 1394_PCIRST DIN 3 ALAS P18 2 1740 1202 100 71 _6307 2 1 2 7718 VT6307L gt 72 _6307 e 3 5 P11 3 4 m 16 R828 33 PCICLK_1394 93 LAA Ke 183 25 0712 2 NVVA 1 1202 1007 73 6307 416 1 5950810 60 R1143 R1144 54 9 54 9 R1116 61 R1142 R1141 54 9 54 9 C965 R1148 X707 270P 4 99K 1 1 V V 24 576 7 C939 C932 74 TPBIAS e 10 10 136 80500 N B Maintenance 9 Spare Part List 1 Description Location S CARTON BATTERY CAIMAN PWR PARTITION BATTERY MARLIN CAIMAN PARTITION TOP BT M BATTERY MARLIN CARTON N B 8060 Part Number 600020252 600050218 242600000439 LABEL 25 6 HI TEMP COMMON Po _ 242600000482 JABELBLANKTMMIMMORC 242600000452 LABEL BLANK IMMIMMPRC 22664800013 ABELCAUTIONINVERTBDAITCHNG 24266300028 LABELGYTMMOLYESTERFIEMHOPE 242669600005 LABELLOTNUMBERRAcE 242669900009 242670800113 BF WORIDMARKAVINNPTSSIN jTMHNTELCENT
134. 37 0 SIO48M gt s R877 33 USBCLK_ICH cc 7 R824 33 PCICLK_ICH p P14 R858 33 14M_ICH gt 0715 56 R859 33 R472 0 14M_CODEC P20 12 R826 33 PCICLK_CARD gt P17 0727 13 R827 33 PCICLK_LAN gt 16 0719 SMBCLK 29 30 SMBDATA J711 16 R828 33 PCICLK 1394 gt PIs U724 10 6825 33 PCICLK_FWH gt 223 015 17 R817 33 PCICK_KBC gt 222 016 MINI PCI 4 AUDIO CODEC CARDBUS READER LAN DDR SODIMM IEEE 1394 BIOS SYS WINBOND KBC 107 VDD3 8 3 No Display 2 80500 N B Maintenance 3989989 System Reset Check 010 25 MAXS09 sw2 R7 3VS 43V IK A PWRBTN 1 18 H8 PWRON 26 P27 P31 o e PWROK 9 gt e gt www Convert e P22 s Power 5 Module 1 010 5511 016 PWROK LTC3728L V R301 330 V z 1 ICH_PWRBTN Q31 amp HPWRGD U21 2 255 RSMRST P13 811 225 eS B gt 10K 3 3 MN __ 2 H8 25 ko Q42 RESET e S H8 RSMRST FDV30IN SUS VRMPWRGD 0715 W83L950D 5V Q V ICH_PWRBTN gt 4 M 2H 44 RSTDRV14 e 292 HK
135. 37 C346 29 75 0010 0 1U 56 8 gt NB_MD 0 63 R948 R949 10 MD 0 63 a P6 NB_DQS 0 7 1011 81016 10 0510 7 NB_DM 0 7 R950 R955 10 DM 0 7 NB CB 0 7 R977 R978 10 MCB 0 7 NB R972 R975 NB MA 6 12 R1032 R1036 10 MA 6 12 J711 NB R969 R971 CAS 0714 RAS amp NB BA 0 1 R1030 1031 10 RAS 0 1 amp SMA 12 5 12 SMA 4 5 SMAB 4 5 J712 NB CKE 0 3 CS 0 1 855GM NB_DM8 R979 10 NB_DM8 058 1040 10 NB_DQS8 8 NB DDR 0 5 R335 R338 8319 R359 NB DDR 0 5 E NB DDR 0 5 R1103 R1106 R320 R360 10 12 NB_CLK_DDR 0 5 5 2 P11 lt 29 SMBDATA 193 gt 0712 30 SMBCLK e 195 CLOCK GENERATOR VDD3S TV R315 R318 R316 R317 P13 22K 22K 021 10K 10K 8 27002 3 SMB_DATA 2 U715 29 A 0 6MM 200P 4 SMB_CLK e H5 2 115 80500 N B Maintenance 8 6 Keyboard K B Touch Pad T P Test Error Error message of keyboard or touch pad failure is shown or any key does not work Keyboard or Touch Pad Test Error Check U16 J4 J5 for cold solder Yes Re soldering Is K B or T P cable connected to notebook properly Board level Troubleshooting No ose Check following parts and signals Try another known good Keyboard or Touch pad Parts Signals 016 VDD3 0715 VDD_AVREF F701 KBC X
136. 4 E41 47 VDQMBR3 aji E41 VMDBIS VDOMBg7 p11 DOM 0914 VMDB47 0015 f G12 VASAT 0015 f G12 VOSAS VRASBH 0015 G12 VOSBI VRASBH 0015 f G12 VOSBS 9 BAS 0051 9 VRASA 0051 9 VRASB RAS 0051 9 VRASB BAS 0051 9 VCASAK CAS 9 VCASA VCASBt CAS 9 VCASB CAS EE 2 unmas 2 vune A 2 9 VCSA40 CS 0017 VMDATS 9 DQ17 VMDASO 9 5 0 1 5 9 VCSB 0 tics 0017 VMDBSO 9 VCLKAO PCK 0018 VMDATS 9 VCLKAT 0018 VMDAST 9 VCLKBO 20 VCLKBRO p ck 0018 VAIDBTS 9 VCLKB 20 veLKEHT PCK 0018 VMDBST 9 VCLKA 0 0919 VMDAZo 9 1 1 0019 VMDASZ 9 VOLKBIO 2 op CK 0019 VMIDBZO 9 VCLKBH 55 op CK 0019 VMDBBZ 9 0020 2 9 VCKEAt 0020 VMDASS 9 VCKEB M11 CKE 0020 VMIDB2T 9 M11 CKE 0020 VMDBES pazi VMDA22 VMDA54 VDD IORERM12 0921 VMDB22 VDD MEM IORERM12 baat 54 0022 VMIDA23 0022 VMIDASS 2 VREF 0022 VAIDB23 2 VREF 0022 VAIDBSS MCL 0023 FG VasA2 0023 2 MCL 0023 42 582 MCL Does ae NC1 0052 Dose 0052 G1 9882 2 0052 01__ 0586_ 2 gt lt BX 2 gt BAY 212 VMDA24 ___ LDig __ 56 ___ 3 00
137. 4 PCILLOCK PLOCK DNA re open 4 17 16 17 1924 PCI SE SERR BER PM POr CBE A Wee 14 16 SB PMER PME PCL OBER E 0018 PCIRST 0 11 POLK ICH lt E je KMINIPCLPCIRST 19 5 VCCHIT BGA360_25_36 V OES 2 PST 23 PCI PME amp R920 1 5 ARDBUS gt gt CARDBUS_PME 17 id JL10 29 5 E amp SINCCSUSI 5 oe GND 11 a VCCLAN1_5 VCCSUS1_5 2 T T T T VCCSUS1 5 2 co24 68 81 5 C285 dU dU tou 9402 0402 0402 0402 herr 43V 2 of 16 ej 16V 16V Eis 07150 080 VCCSUS1 5 10 VCCSUS1_5 519 ApiccLK 6 as re KAGPBUSYE 4724 GND vem ais APICD 0 GPIO 7 D4 1 Y IR 196 APICD 1 GPIO 8 EXTSMit 2224 5 2 ___ VSREF SUS VSREF SUS __ 5 2 HSTPCLK STPCLKH GPIO 12 Bis g 2224 VEREF SUS 2 HAZOM A20M GPIO 13 WAKE 2224 v cpu io 2 CPUSLP oe eee v 2 INTR 1 GPIO 19 PW 18 M C304 C853 2 HNMI NMI STP CPUIr GPIO 20 STATE STO PU Rae U 310402 C274 2 C3 21 1 KSTPLAGPH 724 VCCPLL 9 greece ba No m
138. 402 0402 0402 0402 0402 SUYIN al 0 bi 2 0 zi 0 R704 1 0 X 0 is 330078 07T1 C 0 1 1 4 2 331870007007 T 1 x I si 4 xl 4 J 3l 3VO 1267 100MNA 2014 T 57 C70 C42 4 4 ND GND GND c38 O TU NAT 0 1U NA 0 1U NAT 0 TU NAL C73 C40 C61 0402 0402 0402 0402 c39 O 1U NA 0 1U NA 2 1004 480 2084 __ 80 2094 280204 280204 100 0402 0402 lt 50V 63 280 2094 80 20 0805 0805 50 507 an8 GND bid 80500 MOTHER B D GND 316680900001 ASSY 411682700001 Rot lumber Date Wednesday December 31 2003 Bheet 11 of 34 PDF created with FinePrint pdfFactory trial version http www fineprint com 1 ID 15
139. 402 COG SMT C794 C804 C914 C915 272105271403 CAP 270P 50V 10 0402 X7R SMT 15 21 770 782 965 141 80500 N B Maintenance 9 Spare Part List 6 Part Number Description 272105332402 CAP 3300P 50V 10 0402 SMT 272105470402 47 50V 10 0402 5 272105471403 CAP 470P 50V 10 0402 X7R SMT i Part Number Description Location S 272431157507 CAP 150U TPC 6 3V 20 H1 9 7343 C701 C713 C743 C768 PC712 PC 273000990127 INDUCTORTHLPSOSOCE 01 0 68uH VI 273001050069 rewgORMER TUO o 28251413200 283450040001 ICFLASH S12 8FWHMSOFWOM0KLPL o 283467490001 IC FLASH 512K 8 FWH SST49LF004A 283467490002 IC FLASH 512K 8 FWH W39V040FAP P 283467530001 IC EEPROM S24CC02A 2K S08 SMT ON 283467540001 24 02 6 2 508 5 IC2 qe 52 gt T gt 272431157512 CAP 150U 6 3V 20 H2 8 PT NCC 272431227402 CAP 220U 2V 35 10 HI 9 8 SP C 272431227504 CAP 220U 4V 20 7343 POSCAP SM 272431337506 CAP 330U 4V 20 7343 SMT 272601107506 272625470401 273000130001 273000130006 FERRITE CHIP 6000HM 10 273000130015 FERRITE CHIP 2200HM 100MHZ 1608 273000130039 FERRITE CHIP 1300HM 100MHZ 1608 273000150002 FERRIET CHIP 1200HM 100MHZ 2012 273000150013 FERRITE CHIP 1200HM 100MHZ 2012 273000150033 PHASEOUT FERRITE CHIP 1200HM 100 EC
140. 5 PDCSI 7005 spcsi 50051 15 TY JP BLOCK SWAP OVERRIDE 5 401 WELI MB ID miei socs SWAP OVERRIDE CZIKI 176 MAIN POWER WELL DPRSLPVR HUB INTER TERMINATION SCHEME GPIO 1 1 0 MAIN POWER WELL MB_IDI 18014 18014 15 24 6515142 5 I WELI 11614 ARIS 18 HUB_ICH_COMP HUB INTERFACE SCHEME 1 0 OR 1 5 F24 1 421 170 MAIN POWER WELL X ICHA M SBSPKR NO REBOOT 23 GPIO 43 170 MAIN POWER WELL X BGA360 25 36 80500 MOTHER B D lev C pce 316680900001 ASSY 411682700001 gt Number Date Wednesday December 31 2003 Bheet 14 of 34 1 PDF created with FinePrint pdfFactory trial version http www fineprint com HDD PRIMARY IDE CONNECTOR CDROM SECONDARY IDE CONNECTOR
141. 5 POIRSTHO 5 1 1206 4 286203107001 GND GND GND GND u10 H 9 9 SOT23N 286300690001 vec RESET 442 18 7 81 PWROK X PWROK 4 12 13 17 31 2 1 013 326 5 prs 51230105 JT 949 5 9230108 VDD5S 0402 th E 10 J gt B T 4 0036 202092400 THERM ERR NA 2d 1 25 TEMA OM 288202240008 1 1 S gt THERM_ERR 1422 EA 172 944 318 0035 VDD5 0 R28 4 35 12021 00M NA 9 0402 GND GND 100K 220 2012 0402 0603 4 1 5 10 R456 R358 R375 R531 AJKNAO 10K 10K 0402 0402 0402 0402 A 5 5 5 5 u21 L 4 MN RESET a 4 gt RSMRSTH 1322 T KADENH 2592 BAS2L cue m DTC144TKA NA BAS32L 4 22 a 4 3VS 050 C506 IMP811 294K NA case 012 Rl R551 5 6010 501143 R508 0402 TOU NA WM Dn 2 Sie 40 gt 5 KKBC_PWRON VDD3S 22 0402 100 1 0805 OAL OFS 80 20 0402 63V DTCI44TKA 50V 5 10 4avs 5VS DTC144TKA 288202240001 288202240001 Nr GND GND VDD3S GND R366 P GND R362 2 8368 0402 10K A 5 0402 0402 5 5 PWRON SUSB 1 M 8355 1 0402 ats 5 R480 1 5 PWRON 80588 22 H8_PWRON SUSB gt KPWRON_SUSB 26 28 29 30 31 13172223 SUSB gt B548 1 RR 2 0402 45VS 1704 45V H 45V 48VS 0707 43V 42 5V8 DDR For ATI VRAM 42 5V 10 9 4403 9 For La
142. 5 R701 R706 amp ua 271061390501 RES 39 1 16W 5 0402 5 271061391103 390 1 16 1 0402 SMT R876 271061402011 RES402 1 16W 1 0402 SMT RESA IK 1 1 6W 1 0402 SMT RES 75 1 16W 1 0402 SMT RES 80 6K 1 16W 1 0402 SMT RESS 2K 1 16W 5 0402 SMT 139 271061432212 RES43 2K 1 16W 1 0402 SMT PR118 PR60 R1187 R1189 R1205 271061470501 47 1 16 5 0402 SMT R750 271061472501 RES 4 7K 1 16W 5 0402 SMT ax S c oo eS gt gt N 27106147450 470 5 0402 5 PR702 R373 271061499012 49 9 1 16W 1 0402 SMT R1082 R1086 R1087 R1090 R209 271061499212 RES 4 99K 1 16W 1 0402 SMT PR20 R1148 2 un gt gt 2 5 5 271061471501 RES470 1 16 5 0402 SMT R1085 R553 R554 R558 271061510303 RESS1 1 16W 5 0402 SMT 271061549011 RES 54 9 1 16W 1 0402 SMT 271061560501 RES 56 1 16 5 0402 SMT 271061562102 RESS 6K 1 16W 1 0402 SMT 271061499411 RES 499K 1 16W 1 0402 SMT PR43 PR716 27106147350 5 0402 5 R140 R442 R443 R702 R708 R929 80500 N B Maintenance 9 Spare Part List 4 271072287011 RES 287 1 10W 1 0603 SMT 271072474101 RES470K 1 10W 1 0603 5 271571000301 amp 0 8 16 1 16W 5 1606 SM 271611220301 RP 22 4 1 16W 5 0612 SMT 2716112403
143. 50 ER 380204 8020 8020 580200 80206 480 20 0402 D 50 D 50 50 4 80 20 507 caog l caos caos l 1 1 0 01U 0 01U 0 01U 0 01U 0 01U 0 010 80500 MOTHER B D Sao 4o wo 6402 6402 280204 80204 280204 80206 480 2081 80 20 1 lev GND eer 316680900001 ASSY 411682700001 GND Date Wednesday December 31 2003 Bheet 6 o 34 PDF created with FinePrint pdfFactory trial version http www fineprint com Bus configuration straps I 10 4 1 5V AGP4X ID 16 A I P 1 8742 1 Xp 0402 M10 GPIO4 Bei 1 0402 ARA MIO GPIOS R57 4 0402 ee ee ee ee ee M0 GPIOS R735 4 0402 M10 GPIOi 8744 01 0402 o mone R779 777 R739 1 2 0402
144. 5005 4 a VSS 78 VSS 169 5005 5 5 VSS 79 VSS 170 7 GRBF RSVD_8 5095 6 AGIZ vss 80 vss 174 B 7 GWBF 2 1 9 50057 17 vss gt vss_172 A 5005 8 2 vss 82 VSS 173 7 GGNT RSVD_10 gt gt NB_DM 0 8 6 Riz VSS 83 VSS 174 7 GREQ 0 83 11 SDM 0 VSS VSS 175 0 15 VCOADAC issu o LN 2 vss 85 VSS 176 1202 100 1202 100 A17 85 86 VSSCUT SDMS 4 4 4 4 4 4 AIT vss 87 VSS 178 SDM 4 C779 C786 Cas 850 C851 C848 8 vss aa 38 179 10 SD 0 010 10U 100 0010 a 55 68 85_179 15 0402 0402 16 0805 0402 6 8 18 Ee 480 208 80 20 VSSADAG 480 209 5 80 SDM 50 50 Sov 855GM GME GND 707 25 GND 855GMGME GND BGA707 25 GND 1 98V 1 VCCAHPLL 91 VCCAGPLL 91 vccaio 135V 0 229 T 145 1 1718 T 1202 100 1202 100 1202 100 C297 100 0010 OU 0805 0402 0402 0402 63V 80 20 80 20 80 20 50 VITHF 0 1 0402 C832 50 50 50V 80 20 GND GND GND VITHF 1 010 1 0402 T 50V 480 2075 EE VITHF 2 010 1 0402 25 50V 480 2076 2 VITHF 3 010 1 0402 50 80 20 0 5 with 15 mil wide VCCADPLLA aav oL VCCADPLLB VITHF 4 010 1 0402 138 1713 1 50 80 20 1202 100 71 166 1202 100 772 C785 42 515 DDR i 100 00
145. 59008045 T UNS 12 3 9UH 012 1 30 pon nee Senses 08045 2010 308 30 SENSEt SENSE2 H1 4 E 31 PUGB 30 PC748 SENSE Nco H2 E 32 nes VOSENSE2 Gm 7343 4 4 5 v Pc728 1 Senos 252 o8 2 amp 2200 E PC731 25 5eorZz 746 BZVSSC2V4 NA TT 7848 T 7 0 10 727 4 av av 0402 B EC eed 1000P 5 0402 74 BAVSSC2V4 INA ej 80 20 0402 04900 480 207 2200NA 50V 4444444 50 4 50V TT 7348 1000P BND PR721 10 av 0402 6 49 50V 0402 421 SENSE1 05 ENSEI 5 10 1 1 1 SENSE1 04 SENSE1 5 1 Lt 4 4 1 1 1 273 735 a 180P spor PR718 PR725 0402 02 krd 3VS 18K 2K o 10 50 5 10 J GND 0402 0402 25 7 V PR722 1 1 738 _ 28748 747 20K 1000P 72 1008 15K 15K 0402 0402 PR715 0402 0402 0402 1 10 100K 402 1098 1 1 50V 0402 50V 4 4 15701 1 iB 4 21 3 1 1 4 31 VccP PWRGD lt lt i 0 kl Nr GND 0402 PR723 SGND3 0402 7 5 en7oo2 005 4 INTVCCa 9 OOO PR724 4 10K sGND3 0402 28733 1 100K 0402 1 2N7002 4 PQ706 SW 25 26 29 30 31 PWRON SUSB gt SGNDS 4 cou PR730 1 0402 0402 80 2094 50V SGND3 Title 8050D MOTHER B D 316680900001 ASSY 411682700001 Rot lumber Date Wednesday December 31 2003
146. 5A 63 VDC 1206 SMT 0 22 4 FUSE FAST 1 A 63V 1206 THIN FILM SW PUSH BUTTOM SP SPST 12VDC 50m SW DIP SPST 4P 24VDC 025A SMT SW COVER SWITCH 0 1A 30V 4P T ME SWI THERMIST OR 10K 1 BN35 3H103F 18 PCB PWA 8050 M BD PCB PWA 8050 BATT PR AND GA BD PCB PWA 8050 Transition BD PCB PWA INVERTER BD DA 1A08 A CABLE FFC TP 8050 DDR SODIMM MODULE 256MB 77 10634 IC CP U BANIAS 1 5GHZ MICRO FCPGA CON HOLDER PCMCIA UP ST ANDOFF 0 CON IEEE1394 MA 4P 1 0 83MM RW A 3 3 3 331870007007 332110020165 332110020173 332110026150 WIRE 26AWGUL1007 1 208mm BLUE 332110026151 WIRE 26AWGULI007L 142mm YELL ons 3328 10000034 333050000117 335152000026 335152000085 FUSE 128 DC 7AS0V199Cony UC 335152000097 FUSE LR4 75XPOLY SWITCHPWR 338536010052 BATTERY LI3 7V 2 2AHLI8650SANY ___ woo speaker wwe speaker 340680900004 cover assv soso s4nssos0000s suspe racker assy sysrem soso 340680900008 SHIELDING AssY CoveR es 340680900009 racker assvtPs050 E 340680900012 cover _ 340680900020 BEZEL ASSY CoMBO QSLSBW242 8050 340680900026 supDGASYHDDA 145 3 3 CONNECTOR 7 PIN DIP ALLTOP C1034 331000008033 CON USB FM H15 64 R A 4P 2 2522A 331030044019 HDR FM 22P 2 R A ST ACE 1A2 310 310 CON HDR MA AP 1 H 5 9 R A USB DI CON HDR BTB R A 0 8MM S TECHI507 DIMM SOCK
147. 71061103102 1 16W 1 0402 SMT PR102 PR119 PR127 PR129 PR4 271061104102 00K 1 16W 1 0402 SMT PRIO PRII2 PR114 PRI2 PRI30 K Sil S RES RES 1 5 27106110350 1 16W 5 0402 SMT R1007 R104 R1098 R11 R1103 R1 27106110550 1 16 5 0402 5 PR106 PR115 PR123 PR26 PR27 RES 10M_ 1 16W 5 0402 SMT R296 R938 PR35 107K 1 16W 1 0402 SMT 1 8K 1 16W 1 0402 SMT 3 3K 1 16W 1 0402 SMT PR 2 amp Ua N r2 gt 5 1 167 1 0402 513 7 1 N a 271061152302 27106115250 S S 24K 1 16W 196 0402 SMT amp N N RES 13 710611333 13 PR RES 13 80500 N B Maintenance 9 Spare Part List 3 Part Number Description 271061249312 RES 249K 1 16W 1 0402 SMT 271061270102 RES274 1 16W 1 0402 5 271061272102 RES 2 7K 1 16W 1 0402 SMT 271061301112 RES301 1 16W 1 0402 SMT 271061330501 RES33 1 16W 5 0402 SMT Part Number Description Location S 271061331304 RES 330 1 16W 5 0402 5 R1073 R1089 R301 562212 RESS6 2K U N6W 1 0402SMT_ PRIS 271061576411 271061590411 271061604011 271061619211 7106 271061634211 RES 6 34K 1 16W 1 0402 5 271061634214 RES63 4K 1 16W 1 0402 SMT 271061332312 RES3 3K 1 16W 5 6 0402 5 PR70 27106133350 1 16W 5 0402 SMT PR4
148. A IN 3VS P gt 3 5 P 304 AVCC PF703 PL708 1743 Pas 707 PHYVDD PL710 PD709 PD713 e Pis Ps 2 5 5 P m 55 VCC_USB_0 Charge 1701 P32 VCC_USB_1 U705 L708 Discharge 4VCC USB 2 U704 L70 3 Pas 0728 5 CARD VCC L704 010 NOTE 018 INT VA Page on M B board circuit diagram PU3 PU9 PU10 PUI1 Ty xVCC CORE PUI2 PUI3 PL711 PD718 PR740 To Next Page 99 80500 N B Maintenance 8 1 No Power When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up Continue To Previous Page Py DVMAIN JS706 PL712 PU705 PL713 PR739 Ps 1871 18717 Pu 4 1 8V P 1 8V PU707 PL714 PR741 JS72 JS722 Ps 1 35 m 1 35 Pos JS10 PL3 15728 15729 15730 PU6 PL707 PR732 1 05V_P VCCP PU4 PL706 PR719 e 1872 15725 Pa 1 5V_P 1 5V JS703 PL716 PU709 PL717 PR744 JS1 JS12 41 25V DDR gt 1 25V DDR Poe Pie L732 JS708 JS709 JS710 2 5VS_DDR P as 2 5VS_DDR DVDD PU708 PL715 PR742 100 80500 N B Maintenance 8 1 No Power When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up Check following parts and signals Parts Signals ALWAYS PLI DVMAIN PL2 ADEN PD702 DEAD PQ701 Connect AC adaptor or batte Notebook c
149. AD 29 RESERVEDS 38 Pci 027 T ag GROUNDE 0120 aa 1 L JJ 1 1 1 PCI AD25 41 AD28 C875 C888 C898 C901 42 nae PCI AD26 M 220 gay 010 gay 13161718 PCI CIBER X E 45 crees Anlaa POLARS 0603 0402 0402 0402 116 7 023 Rien 24 RIS PCI AD17 10 480 20 480 2096 80 20 49 50 0402 gt S50 S 50V PCI AD21 Hr GROUNDS GROUNDIG ln PCI AD22 PCI ADiS 2 peer 54 AD20 SNP 1 3 crounps PAR 3 EN PAR 13 16 7 18 PCI 017 Gnou AN PCI ADIB 45V 5 PCI 15 PCI 16 161718 PCI 2 COLE 59 6 4 4 4 13 16 17 18 24 PCI_IRDY IRDY GROUND11 2 4 C910 C892 C899 C909 63 64 PCI 01U 010 eciknuwe T 85 33 2 PCI_TRDY POLERAMER Sr ran gu 13 16 17 24 PCLKRUN CLKRUNI TRDY PCILTRDY 13 16 17 18 24 6 68 PCI STOP R558 o 80 20 98000 o 18020 beac 13161724 PCI SERRE SERR STOP 98 PCLSTOPR 1316171824 ms 50 0 50 50 PCI MIT Pc pEvseLe 0402 13 16 17 18 24 PCI Bes 1 PERRA DEVSEL KPCIDEVSEL 13 16 17 18 24 bes 13 16 17 18 PCI 1 GROUND12 248 4 ADIA UN zs PCI 015 a PCI ADIS 038 1487 GROUNDS 0181 PI ADT PLADI 8 2 AD 11 E li AD 10 GROUND13 2 1 PCI
150. ADER 8050 346680900005 INSULATOR INVERTER LCD 8050 346680900007 INSULATOR PCB ASSY L105 W12T 1 0 SU 346680900009 INSULATOR PCMCIA 8050 346680900010 INSULATOR DDR MINIPCI 8050 347105015007 1 05 015 007 05030025 GASKET 1 05 030 025 gt 344680900002 cover battery 8050 344680900003 344680900009 3 gt housing battery 8050 347105035020 GASKET 1 05 035 020 COVER REAR R805 108 247108030008 344680900010 347110003010 347110010010 361200001018 361400003003 JET MELT ADHESIVES 3478 Q 5 8in COVER REAR L 8050 344680900011 COVER HINGE R 8050 344680900015 COVER CPU 8050 344680900016 gt SU 346680900011 MYLAR COVER LCD 8050 346680900017 INSULATOR L16W8 5T0 05MM DIALAMY 346681800004 INSULATOR BATT ASSY L129W15T0 25 COVER DDR 8050 146 80500 N B Maintenance 9 Spare Part List 11 Part Number Description Location S 361400003005 ADHESIVE HEAT T RANSFER HT A 48 W 361400003021 SOLDER CREAM NOCLEAN P4020870980 Part Number Description Location S 4 361400003021 SOLDER CREAM NOCLEAN P4020870980 411681300003 JPWAPWALINVERTERBDSMT 41161300004 PWA PWA INVERTER BD SMT BOTA 411681710001 PWA PWA BATT BD LL44Ah2P3SBL 411652700001 411682700002 413000020388 422674300071 wire assvmpcenore 422680900003 WIRE CABLE SAM LTNISAX1 8050 ____ mew case KiT 050DATM 4167480032 contact PLATE
151. AG 4 13 MEMB_MD38 09837 Je MEMB MEMB_MD38 3 KAM VMDB38 MEMB MAS 5 1 VMB5 MEMB _MD39 DQB38 WEB MEMB _MD39 4 VMDB39 MEMB 6 11 MEMB_MD40 DQB39 ps MEMB CSO MEMB 040 1 RAY VMDB40 MEMB MAS MEMB 1 DQB40 CSBO MEMB MD41 VMDB41 MEMB 9 VCKEB MEMB MD42 26 MEMB cs1 _ 42 3 VMDB42 10 MEMB _MD43 MEMB MD43 VMDB43 MEMB 044 DQB43 MEMB MEMB_MD44 A VMDB44 MEMB_MD45 DGBAE SEB MEMB_MD45 VMDB45 MEMB_CAS BRI VCASB VoASBy MEMB_MD46 00845 R728 1 0 5 2 0402 1 VCLKBO rae 46 MEMB MD46 MEMB_RAS VRASBH VRASBH 10 MEMB 047 DQB46 CLKBO vy R727 1 2 0402 1 10 MEMB MD47 4 VMDB47 MEMB_CSO VCSBIO 40 MEMB_MD48 7 CLKBO MEMB_MD48 1 REY VMDB48 MEMB WEF b reds MEMB 049 I R50 0 5 2 0402 VCLKB1 MEMB _MD49 VMDB49 15 MEMB_MD50 00849 12 881 1 C e 0402 1 10 050 3 VMDESO MEMB MD5i 00850 CLKB1 RAK T 10 MEMB 51 2 VMDBST DIMB 0 BB 1 0402 VDIMB 0 52 00851 DIMB 0 _ 52 1 REY VMDB52 DIMB_1 R71 1 0402 VDIMB T s T MEMB MD53 00852 DIMB 0 DIMB 1 MEMB 5 VMDB53 MEMB CSIF R36 1 0402 VEM 1 MEMB MD54 aps 00858 DIME MEMB MD54 3 KAM VMDB54 MEMB MD55 AE4 09854 VDD MEM IO MEMB MD55 4 55 MEMB_MD56 MEMB_MD56 1 RAY VMDBS6 MEMB MD57 MV
152. ASSY 411682700001 Rot lumber Date Wednesday December 31 2003 Bheet 21 of 34 PDF created with FinePrint pdfFactory trial version http www fineprint com 5 C543 0402 1 KO1 100P 50V C542 1 0402 KO1 voos 2 vpps avrer Pull HIGH at Other End KO2 C541 1 0402 100P 50 a 161 100P 50 C540 1 0402 4 KOS Toe SV 098 5 KOs 202 100 3V 1 1202 10 koe 06874 DAZ TP E 25 ost PUL
153. B 17810511 0402 017 MD14 15 _ 1049 1 2 MDTE MDii 3 14 MDE NB AVAVA 2 0402 MDI5 4 13 NE 1 2 0402 DID MDI6 5 1 MDS MDE 2 0 1 2 0402 MD20 6 11 0051 0051 NE MDZRGES 2 0402 DIE 17 10 140238987 1 0402 MD23 MD21 a MDTO MD24R1047 0402 MD24 005271 RY 16 MOTT MDTT 0402 MD25 DM2 15 1402810441 2 0402 MDE MD18 3 14 DDRO CK DDRS NE 2 0402 027 MD22 4 13 CLK DDROF CLK DDR3F NE 1 2 0402 DIE MDIS 5 1 1 2 0402 DIS MD23 amp 11 NB MD3R983 1 0402 MD30 MD24 10 NB MD3IR982 T 0402 MD28 a MD16 MD16 NB 032810281 2 032 MD25 1 RN 16 MD17 MD17 NE 03107 2 0402 029 15 1904810251 2 0402 MDA 0063 73 14 0052 DOSE H 0402 MD3S DMS 74 13 MD18 MD18 0402 035 MD25 5 1 0402 7 MD30 6 11 11615 1615 MDSGSi 1 2 0402 UDSS MD27 10 MD24 MD24 NB 0361 AYN 2 002 MD3i 8 a 425VS DDR NE 0410233 2 0402 9040 MD32 1 RN 16 9 HES NB MD4181022 1 0402 MDAT MD36 15 1 s x MDA2H10201 TURA 0402 DAZ MD33 73 14 1 J 1 TEM ve Len eg m 4 5 1 OU 961 1 0402 MD4S 8 11 042 0402 0402 0402 140268959 0402 046 MD34 10 80 204 480204 280 204 80 20 11080 MD47R958 1 0402 MD47 MD38 78 9 50v 1 50 1 50v 50 MCBT MCBT
154. BLANK ADIS 855_ADDIDO HOHE 015 DVOBCCLKINT G5 855 855 DVOCDO AGP ADIS 855 ADDIDT eg 2N7002 IYAMO DVOBCINTRIF 855 DVOBFLDSTL BAT 855 DVOCDi AGP AD20 855 ADDIDZ 13 M2 DVOSECANIE A GND 5 2 7 2 p57 18 WAMI E15 DVOBFLDSTL 12 855 1 0402 855 2 AD2i 855 ADDID3 HA 21 18 2___ 1 DVOBBLANK 855 DVOCD3 AGP AD22 855 ADDID4 AG uA 22 HD 20 cia YAMI2 Te 855 DVOBHSYNC 855 DVOCD4 AD23 855 ADDIDS AOF OBAS 7 Hbfeojs HD amp 21 GND DVOBHSYNC 855 DVOBVSYNC 855 DVOCD7 AD24 855 ADDIDG Md 5 HA 24 E28 HD 22 1___ 14 DVOBVSYNC DVOCD amp 855 ADDID7 Wa D27 HD 23 IYAP2 C14 DVOCDS H 4 VAPS Bia 855 DVOCCLK HAI27I IYAP 3 DVOCCLK 57 GSBSTB SBSTBS 5 7 28 25 26 TPZ IYBM O 12 229 BY 57 GSBSTB SBSTBF 57 BABS HDI26 Gop HD27 21 2 Kg 855 DVOCDO DVOBCINTRE Ae WEE S EET d 38 4E 5 S 2 2 4 lt HD 29 m 1 006012 WHEN USE INTEGRAITE 57 GSTI 57 HREQIO
155. C 1 8VS 4avs 0402 L731 10 3 2 1202100 16V 1 mj z 1 E d USED IN 93656 2012 876 C865 C874 C886 C891 C906 3305 0402 0402 0402 0402 0402 0402 0402 1 2 10 10 10 10 10 10 10 10 0402 16V 1 16 4 36V 16V 16V 1 16V 16V 81110 8 1 3 6K 5 0603 ADD if use RTL8110 e EECS 1 8 1 Change DVDD to 1 8 5 DYDD DOPA EECK Ne 2 5 4 h 81105 1 ED DI Noo v C870 C867 when ase 33 AVDDL AVDDH EEDO 0402 80 20 80 20 MDI2 MDI3 i 100 010 GND 80 20 50V 50V 1 1 16V 0402 5 0402 92646 30V i 1206 16 08 i 10 283467540002 GND 1 GND R1006 i i 8 R1008 0402 u719 Orato g 1 i i ses 1314 SB_PME ISOLATES ATVI 9 40 SX EESK EE lololol PIA 09 GND LAN WAKE jos SOLATEB 8888888 BoE AUNEEDI EDO H LanwakE 25252560222 5888898 5525 EEDO ing EECS i Ede SE 55558 B EECS i i 43VS 13 17 18 19 0 31 ADO 1 1 Q 1737 ADI iov vv 2_1202100 25 i i 2012 i i 2 5VS_DDR AVDDL AD4 Q 1738 9 ADS 1 2_1207 100 s ADDL n 2012 1 1 J Aor R305 0608 R303 0603 1 R285 0603 R272 0603 895 cess 1_ 1_ ped PMDIO MDH
156. C TEL s well proven PCT2303W chipset and the HSP56TM MR software modem driver allows systems manufactures to implement modem functions in PCs at a lower bill of materials BOM while maintaining higher system performance PC TEL has streamlined the traditional modem into the Host Signal Processing HSP solution Operating with the Pentium class processors HSP becomes part of the host computer s system software It requires less power to operate and less physical space than standard modem solutions PC TEL s HSP modem 15 an easily integrated cost effective communications solution that is flexible enough to carry you into the future The PCT2303W chip set is an integrated direct access arrangement DAA and Codec that provides a programmable line interface to meet international telephone line requirements The PCT2303W chip set is available in two 16 pin small outline packages AC 97 interface on PCT303A and phone line interface on PCT303W The chip set eliminates the need for an AFE an isolation transformer relays opto isolators and 2 to 22 80500 N B Maintenance 4 wire hybrid The PCT2303W chip set dramatically reduces the number of discrete components and cost required to achieve compliance with international regulatory requirements The PCT2303W complies with AC 97 Interface specification Rev 2 1 The chip set is fully programmable to meet world wide telephone line interface requirements including those described by CTR21 NET4
157. CDROM E M E PDIOW 2 J T 1 12021 0 2012 9 1723 14 PDIOR Gare err cars 14 SIORDY 14 PIORDY pony Ri0811 42 av 04 100 14 SDDACK 14 PDDACK 0 enn 0402 0402 0805C 14 18015 7 cs16 l 1202 100 TROT 910741 2 A 10 10 10V ees 010 610 10U 2012 PDAT 0 7 16 16V 0402 0402 0805C Te TOM PDAO 5296 10 10 10V 14 PDAO 14 SDA2 Nw A Peers PDCSTE uc TE M 14 51 ROGET 14 SDCS3 14 PDCS3 55 55 9 U701 L702 9 1705 1708 1 34 vno 1 00058 0 1 34 vno vouto H 4 4 2 2 1 vom TE 1 vou 4 R701 0402 R706 0402 80 20 80 20 0402 1500 _ 150U NA 50 0402 1500 50 5 TX 7 4 5 5 LA EN EN 170 GND USB SN GND 0681 E VCC_USB 1 Gb GND 14 oco 6 58 000 ae d e 14 USB C704 R702 0402 R708 1000P 9 47 80 20 47K 0402 0402 50V 0402 20 5 Kb usa 5 50V 4 A 121 06030 06030 BEAD NA 14 USBP2 21 14 USBPO gt T uud J701 ae 12 4VCC USB j 90Z 100M use 2 1 vcc 902 100 1 2012 1 2e CHOKE 2012 1 2 Pe 1 Fu 4 GND 4 14 USBP2 41 1 9 GND1 14 USBPO 3 4 1 v GND2 1 2 Li 06030 A3 GNDI USB 4P
158. DM5 R960 1 0402 DM5 e 1040 MDa MDa0 1 044 NE 85 1 UA 2 002 DUE NB C8 o 7 0 ND 1421 30 2 0402 MODO MOBI 1 BRA 18 2 5VS_DDR NE CET 6402 UCET LAANET HES HES NB CB2 810491 2 0402 3 MANY 14 I NB R10881 0402 MCES MCB5 4 13 3 1 a 1 4__ 81 20402 MCEI DOSa 5 1 caas casa 1 cazo caas 1 casi TK DORTE CLK DDR NB CBS R980 1 AAA Adis MCES DMB 76 11 TU 01u 010 CLK DDR4 NB CB6 R978 1 0402__ 6 10 0402 042 0402 042 0402 NE CE7 1 2 0402 MOST B 18020000209 Cie reel Dam Di WOES NB MAO R972 1 20 0402 5 _ 1 16 3l Ri 3T T 2 5 __ 1033 1 0402 5 2 15 cart cas3 C352 C372 C336 5056 DME DME 5 NE R973 1 0402 MAS SMAS 73 14 1U 010 010 010 1U MD50 MD54 MD54 5 10341 2 0402 SMA2 4 13 0402 0402 0402 0402 0402 5 NB MAS R974 1 0402 NB MAIZ 5 1 d 80204 480 2004 80 208 80206 80 20 MIDST MDEE 055 NG MAS 2 0402 MAS NB MATT 6 T0 ES 50 tov 5 MDBO Mbso 5 NB NB MATO QA 6402 NB B NB MATI BOYS 2 0402 NB MAS 8 MD57 TEM NB MATZ 10361 A 0402 MATZ NB BAO 1 RN 5657 DU NB WEFRIOG01 AYNA 0402 WEE NB WEF NB 5 8969
159. DPSLP J J J aav 0805 DFS Ee M os Q R252 p11 R397 R164 010 25 TK Vppss u5 a aa i hs Ver e BATSS ius BAT54 L Wr 1 1 2 VSREF iie VSREF SUS MIN vopas 0805 DFS J ti 5 c228 0225 4 4 q 4 gt EN 1805 p cess ceto 71 H R233 4 9 C207 C221 1 Sors EMA d 1 BAV7OLT1 oe 537 o 10 10 10 ee ia 80 20 R926 0805C 3 16V 0402 0402 0402 0402 Taos AT IP 10 IP 10 10 80 20 0402 x D704 0402 GND 1 16V 1 16V 5 R288 GND SLP_S4 a E RATH susct 222627 GND GND GND GND GND 4 cas e IL 0 0470 5 0402 288100056017 1 vopas 0402 10 J E 1 1 1 10 SF 18V J Spacing other signal 25 mils coss 28 cars 2 E 1 X 1 a 4 4 4 1 GND usd 0402 0402 0402 0402 6245 213 l caos l 7 l caos RTC_VBIAS 31 vAMPwReD 12 ICH_VGATE 100 10 10 10 010 010 010 PWROK 13 16V 0402 0402 0402 0402 0402 125 5 2 J 10V 4 10 j 1 10 1 5 74AHCOB 0402 85205 0200 R296 TSSOPT4 5 GND 1 GND 0402 lt 7 5 ICH GND 855 22 0402 is 9 GND 9 1 T ov R311 1 0269 10 010 0 0402 0402 0402 VDD1 5 0805C DFS 71 coos 10V 10 10 R932 8245 C228 16V 16 10K 0805 0402 ilie 0402 0805 100 10 80500 MOTHER BD 5 16V
160. Description PWA MPDOG MINI PCI DOGKELLER CARD Note Order it from MIC TSSC 94 80500 N B Maintenance 7 3 Error Codes 1 Following is a list of error codes in sequent display on the debug board POST HEX DESCRIPTION oon a t stai n th sh sh oh oh Some Type Ortons Reset POST HEX 17H 18H 19H 1AH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH DESCRIPTION Dispatch To RAM Test checksum the ROM Initialize Video Adapter s Initialize Video 6845 Regs Initialize Color Adapter Initialize Monochrome Adapter Test 8237A Page Registers Test Keyboard Test Keyboard Controller Check If CMOS Ram Valid Test Battery Fail amp CMOS X SUM Test the DMA controllers Initialize 8237A Controller Initialize Int Vectors Protected mode entered safely RAM test completed Protected mode exit successful Setup Shadow 5 z D 8 5 z 5 5 8 73 o 3 un N ga Going To Initialize Video 95 80500 Maintenance 7 3 Error Codes 2 Following is a list of error codes in sequent display the debug board POST HEX ET ET ET sn im am n sin 52H FDH CAH 96 80500 Maintenance 7 3 Error Codes 3 Following is a list of error codes in sequent display on the debug board POST HEX E7H E9H A2H A3H A4H ASH
161. E ECC error detection is supported by the SDM 8 signal RCVENOUT Clock Output Reserved NC SSTL 2 RCVENIN Clock Input Reserved NC SSTL 2 5 contains two mechanisms to queue requests by the AGP master Note that the master can only use one mechanism The master not switch methods without a full reset of the system When PIPE is used to queue addresses the master isnot allowed to queue addresses using the SBA bus For example during configuration time if the master indicates that it can use either mechanism the configuration software will indicate which mechanism the master will use Once this choice has been made the master will continue to use the mechanism selected until the master is reset and reprogrammed to use the other mode This change of modes is not a dynamic mechanism but rather a static decision when the device is first being configured after reset T 80500 N B Maintenance 5 2 Intel 855GM GME North Bridge 4 AGP Flow Control Signals AGP Status Signal Descriptions Description Read Buffer Full Read buffer full indicates if the master is ready to accept previously requested low priority read data When RBF is asserted the GMCH is not allowed to initiate the return low priority read data That is the GMCH can finish returning the data for the request currently being serviced RBF is only sampled at the beginning of a cycle If the AGP master is always ready to accept return
162. E 802 3u 100Base T specifications and IEEE 802 3x Full Duplex Flow Control It also supports the Advanced Configuration Power management Interface ACPI PCI power management for modern operating systems that are capable of Operating System Directed Power Management OSPM to achieve the most efficient power management possible The RTL8100C L does not support CardBus mode as the RTL8139C does In addition to the ACPI feature the RTL8100C L also supports remote wake up including AMD Magic Packet LinkChg and Microsoft wake up frame in both ACPI and APM environments The RTL8100C L is capable of performing an internal reset through the application of auxiliary power When auxiliary power is applied and the main power remains off the RTL8100C L is ready and waiting for the Magic Packet or Link Change to wake the system up Also the LWAKE pin provides 4 different output signals including active high active low positive pulse and negative pulse The versatility of the RTL8100C L LWAKE pin provides motherboards with Wake On LAN WOL functionality The RTL8100C L also supports Analog Auto Power down that is the analog part of the RTL8100C L can be shut down temporarily according to user requirements or when the RTL8100C L is in a power down state with the wakeup function disabled In addition when the analog part is shut down and the Isolate B pin is low i e the main power is off then both the analog and digital parts stop functioning and th
163. ENASEE VGA F380 4 19 0 TXOUTI 4 0402 R37 R2 ESDOB0SAINA 1 10K URS 4 TXOUTS 1 TXOUTI 4 0402 I 4 7 ENABKL BATOS 5 Di6 R379 BC m O 4 meum 3 5 5 s 1 a 1 at 1 4 L 28 30 i3 4 1K 0402 5 BATS4 cass 0 0402 gay DT006 P11AA A X 15 2 5 22 upsws 18 0058 GND 88107 300x 4 13 17 25 31 PWROK gt gt o 54 Check Power Plane is 3VS 5VS 45V H R 5V_H RI 1 855 CRT DDCK 4 0 0702 2N7002 p 0402 CON DDDA 1 0805 1 L2 1 1202 100 1608 ov RA CH GND R703 a NA 4 A E i 2n7002 p 4 t Bi38 1 A 0402 CRT DDDA 7 77 CHAGND SMSOSC NA r 855 CHT DDDA 4 p 0805 GND aR cHAGND 7 4 Qe ESDA1AINA 1 4 Lan t 3 141324 1202110001 1608 27003 p Hi36 1 RA A 2 0402 d o SLVU2 BINA BEAD 02 100 a7 H SOT23N 100P 06030 0403 Meo 120271000 1608 2N7002 n pL An 2 04 AN CHAGND it E ddd ae 855 CHT HSYNC 4 i dnd 5 cpa KH a oreen cHAGND 2 y Bock 1206 WHEN USE INTEGRATE VGA DEL ART o 1 R785 R138 R136 R137 R139 R135 SOT23N o 4 o R783 CHAGND el CON HSYNC t a3 1 91 CON DDDA Jp Hu CON RED E Rm 2 CRT BLUE Riss 1 0402 AT ORT BLUE 7 2 1 i SLVU2 BINA 158 i CRT GREEN R135 1 RA A 2 0402
164. ET DDR SODIMM 200P 331710015016 CON D FM 15P 3ROW SUYIN 070912FR CON STEREO JACK 10P W SPDIF R A 80500 N B Maintenance 9 Spare Part List 10 Description Location S 340680900027 WLEN ASSY CABLE 8050 340680900028 WIRE ASSY INVERT ER 8050 Part Number sues sue 0 00 345677000018 CONDUCTIVE TAPE LCDLYNX 345677300001 RUBBER SILICONE RUBBER T 1 5mm D 346503100005 LATOR 5 BATTERY ASSY 7521Li I 35 346503200202 JINSULATOR BATT ASSY ONE ROUND BL 340680900029 COVER ASSY MINIPCI 8050 340680900034 SPEAKER ASSY WOOFER NEW 8050 340680900035 HEATSINK ASSY DESCRET E UNP 8050 340683400029 HEATSINK ASSY NORTHBRIDGE 8050F HE 1 7 341677000002 SPRING SCREW HEAT SINK LYNX Po 346677000016 SPONGERTC LYNX pu NS 346677300001 INSULATOR FIBERUL94V 0 D 17 5mm 341680900001 SPC SCREW 4 1 4 8050 342502900001 CONTACT PLATE W4L27T0 15 7068 342502900001 CONTACT PLATE W4L27T0 15 7068 342503200004 PLATE W4L63T0 15 1 4 T T 342672200010 BRACKET CD ROM 8500 342672400007 FINGER EMI GROUNDING SMD FINGER 45 48 50 342677000014 5 NUT A40M20 50 EMI STOP LYNX MTG701 MT G702 342680900005 HINGE R 8050 DA 342680900006 HINGE L 8050 342680900009 5 NUT A40M20 55 EMI STOP 8050 MTG703 MTG704 342683400005 SPRINGHEATSINK VGA 8050F 346680900001 INSULATOR MB 8050 SU 346680900002 INSULATOR CARD RE
165. FRAME based AGP target G_STOP is used for disconnect retry and abort sequences on the AGP interface GDEVSEL VO AGP DEVSEL Device Select During PIPE and SBA Operation This signal is not used during PIPE or SBA operation During FRAME Operation G_DEVSEL when asserted indicates that a FRAME based AGP target device has decoded its address as the target of the current access The GMCH asserts G_DEVSEL based on the DDR SDRAM address range being accessed by a PCI initiator As an input G DEVSELZ indicates whether the AGP master has recognized cycle to it GREQ AGP G_REQ Request During SBA Operation This signal is not used during SBA operation During PIPE and FRAME Operation G_REQ when asserted indicates that the AGP master is requesting use of the AGP interface to run a FRAME or PIPE based operation Signal Name Type Description GGNT O G_GNT Grant AGP During SBA PIPE and FRAME Operation G_GNT along with the information on the ST 2 0 signals status bus indicates how the AGP interface will be used next Refer to the AGP Interface Specification Revision 2 0 for further explanation of the ST 2 0 values and their meanings GAD 31 0 VO G AD 31 0 Address Data Bus AGP During PIPE and FRAME Operation The AD 31 0 signals are used to transfer both address and data information on the AGP interface During SBA Operation The AD 31 0 signals are us
166. IL cios L 2 Tl C787 63V 4802084 8020 cas C100 C106 C109 VDDC 4 10U 10U 0 10 0 010 1000 010 10 4 50 50V 0010 1000P 0 01U 0 10 MODE 0805 0805 0402 0402 0402 0402 1712 1202 100 LEN 0402 0402 0402 06 5 Mahon 63V 63V 480 208 480 208 20 480 209 1 U710E 80 480 20 lt 20 80 204 80 20 23 ho T 180 180 190 150 wore 10 10 50 50 50 50 T si T OVDD PLLI 8 VDDC 8 VDDP 8 2012 l c764 VSS_76 VDDC 9 VDDP 9 t 4 100 010 vest vsa 77 VDDC 10 VDDP 10 0805 0402 0402 vss 2 VSS 78 VDDC 11 VDDP 11 63V 480 2084 80 20 vss 3 55 79 t VEDO 12 7 10 50V 50 VSS 4 VSS 80 129 1202 100 Wes VSS 81 6 VSS 82 al 4 4 al 00 14 VDDP 14 1 4 OVDD PNLIO1 8 VSS_7 VSS 83 C82 c107 C101 VDDP 15 4 85 8 100 100 Q1U 3000P VDDC 16 VDDP 16 2012 C98 C86 Ci24 vss 84 0805 0805 0402 0402 0402 VDDC_17 VDDP 17 400 giu 040 ej of 63V of 180204 8020 4 20 VDDC 18 VDDP 18 pns 402 0402 yes 66 10 10 50V 50V 50V VDDC 19 VDDP 19 VDD MEM IO 63V 80 2004 480 2074 vss tt VSS 87 10 50V 50 24 55 12 VSS 88 VDDC 21 VDDRI 0 1710 1202 100 55 13 VSS 89 VDDC 22 VDDRI 1 4 4 1 VSS_14 vss 80 VDD CORE VDDC 23 VDDRI2 C108 c95 c125 0758 T F T T OVDD PNLPLLI 8 VSS 15 VSS 91 9 VDDC 24 VDDR1 3 ar oau w 2012
167. IPBIP 28 0402 6402 AD21 1 22 T AD22 AD23 XIPA2P 82x Ines XTPA2M 88 AD25 XTPB2P 88 lt AD26 XTPB2M 84 AD27 ____ 5__ _ AD28 XTPBIASO A AD29 XTPBIAS1 1 AD30 XTPBIAS2 88 AD31 58 1316719 XRES 13461719 PCI C BER 1 Jeo x 13161719 PCI 2 CBE2 x 1361719 PCI 1446 av 28 EECS 1394 EECSIEEAUTOR 2250185 S 5 1316 17 19 24 FRAME EEDO EEDI 1394 Sov R1147 3 1316 17 19 24 PCI_DEVSEL DEVSEL EEDISDA 5 EECK 1384 1K 0722 9 13186171924 PCLTRDY TRDY EECK SCLIEEFAST GND 0402 EECS 1394 13 16 17 19 24 PCLIRDY IRDY 5 EECK 1394 CS 1 1324 PCI PGNT 22 33 al 1394 SK NCI 4 13 24 1 PODA AT PREQ Eo 1893 0 nope CM AD2 RUTI 9 2 108 ipse moneo 43 DO doz 1324 PCLINTG INTA 22 ao 80 20 11 PCICLK 1394 PCICLK d Tov 13 1894 PCIRST so POIRST Noo 13 16 1719 PCI 40 293581540002 BND 13 16 17 19 24 PCI_PERR PERR 4 13 16 17 19 24 PCI_STOP STOP ory 5 5 Hix R1116 PHYRST e RKEZSS Noa FRE 85888885885 555 555588 Confi st 22222222222 222 222222 Nos 0402 core 65556555566 556 555565 82 N 04
168. In Jack s AVDD 25 38 2 2464 220 28 R532 0 2 Next Page 019 L76 Y 4 0999 R519 TY U726 10 BEAD 600Z 100M L53 e C974 R324 ca SBSPKR 24 1751 BEAD_600Z 100M 120Z 100M_ P14 ACRST 11 10 0 E V 4 AUDIO ACSDOUT 3 CODEC 45V U715 L67 120Z 100M 7 18 19 ACSDINO R530 2 8 ICH4 M 0 10 ALC655 55 L R1130 0 R1135 0 AMPLEFT e Cis 5 EIS C480 1U 6 ACBITCLK L69 R498 22 6 0524 36 AOUT R 1127 0 R1128 0 AMPRIGHT e C42 20 AMP C497 IU 23 TPA0212 GND 1720 TO NEXT 019 48 0712 56 R859 33 14M_CODEC R472 0 2 2 2 SPDIFOUT SUB LEFT TO NEXT PAGE D22 TO NEXT PAGE 019 CLKGEN 47 APD 2 SUB RIGHT 15950810 125 80500 N B Maintenance 8 10 Audio Failure Audio Amplifier amp Subwoofer There is trouble with the sound from speaker or completely no sound From Previous Page U726 7111 sppirour m DEVICE DECT 52 _ 21 ROUT e 152 6002 100 sii 47K 10K J720 16 ROUT L50 y y 6002 100M J7 Internal T 1754 6002 100 P21 Speaker 5
169. Intel Pentium M Banias Processor 2 Signal Name Description DPWR FERR PBE DPWR is a control signal from the Intel 855PM and Intel 855GM chipsets used to reduce power on the Intel Pentium M data bus input buffers FERR Floating point Error PBE Pending Break Event is multiplexed signal and its meaning is qualified by STPCLK When STPCLK is not asserted FERR PBE indicates a floating point when the processor detects an unmasked floating point error FERR is similar to the ERROR signal on the Intel 80387 coprocessor and is included for compatibility with systems using MS DOS type floating point error reporting When STPCLK is asserted an assertion of FERR PBE indicates that the processor has a pending break event waiting for service The assertion of FERR PBE indicates that the processor should be returned to the Normal state When FERR PBE is asserted indicating a break event it will remain asserted until STPCLK is deasserted Assertion of PREQ when STPCLK is active will also cause an FERR break event GTLREF GTLREF determines the signal reference level for AGTL input pins GTLREF should be set at 2 3 vcce GTLREF is used by the AGTL receivers to determine if a signal is a logical 0 or logical 1 HIT HITM VO Snoop Hit and HITM Hit Modified convey transaction snoop operation results Either system bus agent may assert both HIT an
170. L HIGH at SB END gt gt RSMRST 13 25 KO7 100P 50 536 1 0402 8 7 C535 1 0402 100P 50 9 KO9 100P 50 C534 1 0402 10 KO9 DTC144TKA gt sow KO10 C533 1 0402 100P 50 11 2 1 H8 RSMRST KO11 100P 50V C532 1 0402 1 KOI KBC CPUCORE VCC CORE 288202240001 032 2 C531 1 0402 100P 50 13 12 9 R SCI 042 KO13 100P 50 530 1 0402 14 1 H8 FDV301N C528 1 0402 100P 50 18 R424 1 C 30723 KO15 100P 50 C528 1 0402 18 15 0402 X DEAD DTCi44TKA i C827 1 0402 100P 50 1 C453 2 1 KIS 100P SOV C526 1 0402 18 0 1U 288202240001 C525 1 0402 100P 50 19 0402 GND 100P 50 C524 1 0402 Q Kid 80 20 J lt r 523 1 0402 100 50V 1 50v 33 BATT_DEAD zi 039 3VS GND VDD3S Kip 100P 50 C522 1 0402 GND p R925 DTCI44TKA C521 1 0402 100 50 KH 10K 1 Kio 100 50 C520 1 0402 4 oA 0402 288202240001 100P 50 026 Rasa 1324 sZ is 8 HRCINIK 144 GND 2 1 2 us 288202240001 9 frarino pa 1824 _ 3 7Sq 1 H8 WAKE 11 PCICLK 4 13 ICH PWRBTNs lt lt 85202 26 00 12144719
171. LKO 11 CLKCITP CPU 4 TP CLKt EZ THRMTRIP_OUT 14 BANIAS dew i i m amp HCOMP2 should be 5 route with 18 mil width R219 2 225 2 R220 2 R229 i R224 2 R228 2 R238 2 R243 gt 51 39 150 gt 1 HCOMPO 1 H 51 51 51 51 0402 5 0402 5 0402 lt 0402 i R133 274 0402 1 i i 0402 S 0402 S 0402 S 0402 5 1 1 5 i 1 2 HCOMP1 i 5 5 5 5 R142 549 0402 1 i i HPREQR i 1 2 HCOMP2 H HPRDY i R201 274 0402 1 i HBPMET 20 i i 2 HCOMP3 7 R300 549 0402 1 HIDO HIGNNE i i HTMS i V HTDI GND 4 HCPURST X 1 i CPU testi HTRST i R255 1 0402 5 i i HTCLK i 1 2 CPU TESTA 4 R143 1K NA 0402 5 R213 i HSTPCLK 1 1 2 CPU _ 1 274 R214 i R204 1K NA 0402 5 i 0402 680 i i i 1 0402 1 1 i 5 i i 1 0402 4 i 1 i 0402 E i 2 3 Don t overlay by CHOKE or vibrating signals 315 VCCA 9 1 R124 0805 2 caes cis cie L 7l crea TL cate C317 220 220 220 220 010 9608 0603 0603 0402 0402 0402 0402 10 of 10 of Ho 7109 4 10 10 10 10 R123 0 0805 Di rie 80500 MOTHER B D 1 8V 0 6 100 and 10nF each VCCA pin
172. MCH agent will also typically use PCIRST provided by the 4 as an input to reset its internal logic 80 80500 N B Maintenance 5 2 Intel 855GM GME North Bridge 7 Digital Video Output B DVOB Port Signal Descriptions Hub Interface Signals Signal Name Type Description HL 10 0 HLSTB Packet Data Data signals used for HI read and write operations Packet Strobe One of two differential strobe signals used to transmit or receive packet data over HI HLSTB Packet Strobe Complement One of two differential strobe signals used to transmit or receive packet data over HI Dedicated LVDS LCD Flat Panel Interface Signal Descriptions Name Type Voltage Description ICLKAP O 1 25 V 225 mV Channel A differential clock pair output true LVDS 245 800 MHz ICLKAM 1 25 Vx225 mV Channel A differential clock pair output LVDS compliment 245 800 MHz IYAP 3 0 1 25 225 Channel differential data pair 3 0 output true LVDS 245 800MHz TYAM 3 0 1 25 225 mV Channel A differential data pair 3 0 output LVDS compliment 245 800 MHz ICLKBP O 1 25 225 mV Channel B differential clock pair output true LVDS 245 800 MHz ICLKBM 1 25 225 mV Channel B differential clock pair output LVDS compliment 245 800 MHz IYBP 3 0 1 25 225 mV Channel B differential data pair 3 0 output true LVDS 245 800MHz
173. MTG24 MTG27 MTG2B MTG12 MTG32 1050075 10540075 1050075 1050075 1050075 FD2 FD4 MC MC MC MC Z 57 DOC i GND GND_45 MTG10 MTG22 MTG5 MTG31 i i 1020011 1020011 1030090 103 7 5 9 5 70 20704 20702 20701 i 15 FIDUGIALMARK _ FIDUCIAL MARK FIDUGIAL MARK FIDUCIAL MARK 103 009 0 1D3 0 0D9 0 1D3 00D9 0 i MTG118 RD354 N 30X12 MTG118 RD354 N 30X12 MTG118 RD354 N 30X12 f f i ji 7 DRAWN DESIGN CHECK ISSUES 80500 MOTHER B D oer 316680900001 ASSY 411682700001 Wednesday December 31 2003 Bheet 1 of 34 PDF created with FinePrint pdfFactory trial version http www fineprint com vec PROCESSOR CORE POWER SUPPLY VCCA ISOLATE POWER FOR INTERNAL PLL VCCP PROCESSOR I O POWER SUPPLY CI U BANIAS 1 2 VCCQ QUIET POWER SUPPLY FOR ON DIE COMP CKT HAd 31 HD 0 63 1 U713A HD 0 63 4 p oos Aia 07138 B15 pit A 11 HCLK CPU BCLKO aoe CORE ASH DES 11 HCLK_CPU B14 AGH paz B
174. NG GPAO XOUT PWM2 GP27 FD7 SCROLL 23 o bs 33 CHARGING GP41 XCINPWM3 VDD3_AVREF 2 1 lt 1 23 LED GP54 CNTRO GPSS DATIPWMOT 4 25 KBC_PWRON_VDD3S GPSS CNTRI GPS7 DA2 PWM 1 10 808 ______ Es ___ Li PWRBTNM ______ Wm Bun 0402 5 0402 GEVEAL 50 23 5 80 20 51 2 GP62 AN2 INT7 lt KAC_POWER 12 23 4 288100070006 BAT VOLT 50V KOF GP3 FA3 GP63 AN3 INT8 BAT TEMP BAT V 32 K98 4 GP64 AN4 INT9 4 BATT 32 Z Ko5 48 Ed Ed KOE 28 5 GERSIANSINTIO 18 HE PROCHOTE 3 E GPG FAG GPGG ANG INT 1 l caso D 32 58 GPG7 AN7 INT12 74 o KBC_CPUCORE kein m KOS 0402 0402 80 KOI 44 f H8_RESET 80 20 80 20 5 Hot Protection 880640 RESETA Pe moy o MM i Kom g 28 KBC X 4VCC CORE i KO13 41 G5 FA12 1 GPIS FATS KBC X VDD3 AVREF K818 16 14 V i GPIIFATS voD3 wos _ 0 _____________ 2 0 VREF For External 1 A T 3 Ed flash H8_PROCHOT 3 77 _ sai GPSSIFeTRLZ vcc 21 KHPROCHOT 2 Ki
175. R 25 0 VDDR3 2 85 69 LVDDR 25 1 VDDR3 3 L30 1202 100 4 ves 70 VDDR3_ La 71 AVSSN bass ses 22 1 1 OVDD PNLIO2 5 MiB vss 72 MEMPLL1 8 a VDDR3 6 2012 VSS_73 AVSSQ VDD_PLL1 8 O PVDD VDDR3 7 10U 010 0 10 VSS_74 VDD PNLPLL1 8 O AK12_ 0805 0402 0402 55 75 lt 63 48020 80 20 DAC2 5 o p 2821 A2VDD VDDR4 1 20 Bi Sov 50 A2VDD 1 VDDR4 2 0 _1 0 22 VDDR4 4 V _1 24 126 1202 100 MOBILITY MIO P 1 644 64 1 2012 T T T OVOD_MCLK25 C50 C54 105 tou 0805 0402 0402 25V VDD MEM IO 127 1202100 2012 1202 100 1 5V 140 120Z 100M 1202 100M NA Cw mon 133 1202 100M 2 OVDD_CORE1 5 Ciz 100 0 1U 010 lt 0805 0402 0402 63 2020 80 20 i d 80500 MOTHER B D R Document C Romper PCB 316680900001 ASSY 411682700001 Rot 5 1 I Paie Wednesday December 31 2008 heet 8 o 34 T PDF created with FinePrint pdfFactory trial version http www fineprint com
176. R AD30 PCI_INTC R805 yey INTOP PCI_INTD R823 jen 15V Moni PCI_INTE R192 ao 74AHCOB V INTER PCI_INTF R199 AD26 TSSOP14 ut 3 AD25 VCC3 ICH PIRQH GPIO 5 AD24 ave PCI REQ4 ADS GND peau Mardi PCI REQ4f 4 022 0402 vec a PCI_REQ3 3 AD21 al 16 PCI_REQ2 2 4020 43V a 1 9 9 ni PCI_REQO 0 0 aid 1 SB CARD 24 SB CARD PME CAT INF REQB REQS GPIO 1 016 E 2 cH 4 vDDas rom 1224 REQA GPIO 0 ADIs VECLANS SNCOBUSS PEL GNTS 45 vecsus3_3 24 PCI_GNT4 GNT 4 AD13 1624 PCI_GNT3 GNT 3 AD12 PCIRST KKBC_POIRST 22 ips 605 93 3 1924 PCI_GNT2 GNT 2 011 1724 POL GNTO GNT 0 p as 8 53_3 GNTB IGNTSHIGPIO 17 jeter gt 16 324 BicBt GNTA GPIO 16 A 1 Ez 00854 3 17 8 1924 PCI FRAME ADS v Eus vocsuss 35 17 18 1924 PCI_IRDY IRDY 1 1718 1924 PCI_TRDY TRDY AD3 1 171819 24 PCI_DEVSEL DEVSEL AD2 E vecis 1 17181924 PCI 2 store apt 9 16171819 PCI PAR PAR 0 PCI 3 pe 00128 1 718924 PCI_PERR PERR N4 _ 1 0 3 16 17 1819 2
177. REFD pa R747 5 MEMB_MD57 VMDB57 MEMB MD58 Eee MVREFS 04026 OFS 0402 5 MEMB 058 3 VMDB58 I mene Ht rd EEECEE MEMB MD61 MEMVMODE1 0402 5 MEMB_MD61 VMDB61 MEMB_MD62 _ 62 E MEMB MD63 09862 MEMB MD63 3 VMDBE3 lt lt a A AES ponga MEMTEST a 47 MOBILITY M10 P BGAG44 64 1 al 8050D MOTHER B D FOR 1 r 316680900001 ASSY 411682700001 Rot GND GND Date Wednesday December 31 2003 Bheet 9 o 34 I PDF created with FinePrint pdfFactory trial version http www fineprint com 63 IDA 63 9 VMDBJO 83 VDOMA 0 7 EEL Kwo ELLK ow 9 7 COMB HO 2 voamero 79 9 13 aK vase 9 13 8018 E VMDAO 2 VMBO E VMDBO VMBO E VMDB32 ___ m __ m __ m VMAT Ms 0 VMDAT 090 0 DOO lag VMDBi 0 000 as VMDB33 VMDAZ Bal 2 pal 2 2 pal VMDB34 VMA
178. RNONOTEBOOK ___ 242679900005 LABELBARCODE S IOMM2pes8 242680900001 LABEL AGENCY GLOBAL 8050 24260900002 ABELBATTILIVAAAIILISANYO 242680900007 LABEL ITaNSMMBLANKPWR 271002000301 RESO 1 10W 5 0805 SMT 271002472301 RES 4 7K 1 10W 5 0805 SMT 77100260401 27101200030 27103501271 27104410010 271045087101 RES 008 1W 1 2512 SMT 271061010101 RES 1 1 16W 1 0402 9MT 137 600050219 20003 40001 BOX AK 8060 oa N to ro N t2 ro o2 lt o w 50001 8060 50002 CARD BOARD FRAME PALLET 8060 50003 CARD BOARD TOP BTM P ALLET 8060 50004 222503220001 PE BUBBLE BAG BATTERY GRAMPUS 222670820003 PE BAG L560 W345 7521N 224670830002 PALLET 1250 1080 130 7521N TAPE NSULATING POLYESTER FILM ww AP rN gt N N o2 PARTITION PALLET 8060 225600000054 225600000061 226600030332 TAPE ADHENSIVE DOUBLE FACE W20 U SPONGE 320 290 10 CAIMAN PWR 227680900002 PAD LCD KB 8050 227680900003 END CAP NORMAL L R 8050 242600000001 LABEL PAL 20 5MM COMMON 242600000145 LABEL 10 10 BLANK COMMON 242600000145 LABEL 10 10 BLANK COMMON 242600000157 LABEL BAR CODE 125 65 COMMON 242600000232 LABEL 6 6MM GAL BLANK COMMON 242600000378 LABEL 27 7MM HI TEMP 260 C 242600000385 LABEL 27 10 LAN ID BAR CODE 242600000433 LABEL BLANK 11 5MM COMMON 80500 N B Maintenance 9 Spare Part List 2 Part Nu
179. RTC well This power 18 not expected to be shut off unless the battery is removed or completely drained NOTE Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low Clearing CMOS in an ICH4 based platform can be done by using a jumper RTCRST or or using SAFEMODE strap 1 5 V supply for core well logic This signal is used for the USB PLL This power may be shut off in S3 S4 S5 or G3 states VBIAS well bias voltage The DC reference voltage applied to this pin sets current that is mirrored throughout the oscillator and buffer circuitry V CPU IO Powered by the same supply as the processor I O voltage This supply is used to drive the processor interface outputs VSS Grounds 91 6 System Block Diagram J6 Card Reader Socket Mini PCI Card Socket IEEE 1394 HDD N CD ROM USB2 0 80500 N B Maintenance U727 PCMCIA CARD READER 710 DDR 266 0719 RTL8100CL PCI BUS U713 INTEL BANIAS DOTHAN Host 400MHZ U714 North Bridge 855GME 66MHZ U715 AC97 ICH4 M LPC BUS xe LN Amplifier 0212 0726 Speaker AUDIO 0524 Jack CODEC f ALC6SS Subwoofer Line In 016 Internal WINBOND Touch Pad W83L950D FAN 92 80500 N B Maintenance 7 Mainten
180. S 2 VMDAG Da VMDA3S 2 002 A4 VMDBS 2 202 VMDB35 VMAS 7 43 VMDA4 Dos VMDA36 7 43 pos 7 pos VMDB36 VMAS 44 004 VMDAS Dad VMDA37 AM 004 Top 5 a 004 cp VMDB37 VMAS 5 Das Das VMDA3B 5 Das 5 Das VMAT 6 7 096 D1 9 VMB7 6 096 VMB7 6 py VMDB39 VMAS AT 007 a1 VOSA 007 __VOSA4 007 Vaso 8 mio 7 007 VOSB4 VMAIZ 0050 0050 VMIBIZ 0950 VMIBIZ 0950 MAIS 4 BAO VMDAB VMDA40 VMB13 4 BAO 13 BAO VMDB40 VMAS BAT VMDAS Das 4 FAY VMDBS VMB 1 VMDB4T 9 Das VMDATO Das Hi2 VMDA4Z VMBIO 009 12 10 VMBIO 9 Das VMDB42 VMATI 10 Dato VMDATI 0910 VMDA43 11 f h11 11 Ato 0910 An Dan 2 Don VMDAd4 VDOMBRO Dan VMDBI2 VDOMBEA Dan VMDB44 VDQMAR 0912 VMDA4S VDQMBR DQMO VMDBI3 VDOMBHS 0912 VMDB45 VDQMAsZ Dats VMDA14 Dats VMDA46 VDOMB amp Z Dats VMDBi4 VDOMBHG DOM Dats VMDB4G VDQMA3 A11 20 2 DQ14 E41 VMDATS DQ1
181. S 186 21 vss 42 VSS 115 VSS 187 VSS 43 VSS 116 Ww VSS 188 g VSS_44 55 117 Fw ae VSS 189 45V 8 vss 45 vss 118 WS VSS 190 VSS 46 vss 119 2 EOM add ob mx VSSENSE VSS 191 VSS 47 VSS 120 23 1 1 1 1 1 Nee a WE DT cias cise L 157 1 158 IL cast E ar E RT T BET Be keil 5 15 cio 1006 63V 63V 63V 63V 63V H 582 25 220 220U NA 1 P VSS_54 VSS_127 TC 299 55 55 VSS 128 wv ud 4 4 4 4 4 C264 0198 1 249 cago L case 100 100 100 100 100 VSS 57 Tean 0805 0805 0805 0805 0805 9 58 VM NC 63V i 63V 63V 4 63V 63V 4 VSS 60 VSS 133 VSS 61 VSS 134 8 55 62 VSS 135 EA VSS 63 VSS 136 vin Aib 55 64 VSS 137 700 CORE b vss 65 VSS 138 5 VSS 66 VSS 139 1 1 Som 27 20 5 3 deu beo VSS 67 VSS 140 7 1 q 1 L 19 L czas l cass 7 2 7 cies 0 0 0 0 0 1 708 100000 255 i OU OU 01U yas 0402 0402 0402 0402 0402 0402 0402 0 0 0 0 0 1 1 692 I 0 4 z 10 10 10 10 10 10 4 vss 71 VSS 144 T6V eey ev TeV tev 15 0 0 0 0 1 0 1 676 001 0 SUME BANIAS 00 0 0 0 0 1 1 1 660 1 0 0 80 11 BGA479 SKT3 0 0 0 i 0 0 1 644 01 9090 1 1 1 q 1 1 al C268 C251 C280 C191 C178 C236 C200 0 0 0 i1 0 1 1 628 1 9 0 OU OU
182. SA3 R33 1 2 042 vases _ 19 basis DOMB 2 43 MEMB DOMIa MEMB_MD13 4 9 MEMB QSA4 R723 1 VOSBA MEMB MD20 20819 DOMB 3 We MEMB DOM 4 MEMB 14020 1 AN VMDB20 MEMB OSAS R709 1 IN 0402 VOSB5 _ 21 _ 5 MEMB_MD21 VMDB21 MEMB 5 R721 1 RYZ 0402 VOSES MEMB MD22 5 ace MEMB DOMH MEMB 022 3 VMDB22 MEMB QSA7 R715 1 0402 VOSB7 MEMB_MD23 AD2 MEMB DOMI MEMB MD23 AM VMDB23 MEMB MD24 MEMB MD24 VMDB24 MEMB MD25 DOB _ MEMB_MD25 1 VMDB25 MEMB MD26 00825 0580 B3 MEMB QSAT MEMB MD26 3 VMDB26 10 MEMB_MD27 DQB26 0581 MEMB 5 2 MEMB_MD27 4 27 oyy 15 VMB12 MEMB MD28 DQB27 QSB2 Gi MEMB 5 MEMB MD28 1 RN VMDB28 MEMB 3 8 14 1 MEMB_MD23 00828 0583 MEMB 5 4 MEMB_MD23 VMDB29 MEMB 4 13 VMBO MEMB MD30 DQB29 9584 W1 MEMB 5 5 MEMB MD30 3 VMDB30 5 1 2 MEMB MD31 09830 0585 MEMB QSA6 MEMB MD31 4 VMDB31 MEMB MAT 6 11 MEMB_MD32 pana MEMB QSA7 MEMB 2 1 RAY VMDB32 MEMB MATO 10 VMBIO MEMB _MD33 MEMB MD33 VMDB33 MEMB H MEMB_MD34 esi Ba MEMB MEMB 034 3 VMDB34 MEMB MAT 1 BREN 16 11 MEMB_MD35 MEMB MD35 4 VMDB35 MEMB MA4 oi 15 VMB4 MEMB_MD36 00835 Ts MEMB CAS MEMB_MD36 1 REY VMDB36 MEMB MAS 3 14 VMBS MEMB_MD37 09836 CASBit MEMB_MD37 VMDB37 MEMB M
183. SERVICE MANUAL FOR 8050D BY Grass Ren Repair Technology Research Department EDVD Mar 2004 MITAC 80500 N B Maintenance Contents 1 Hardware Engineering Specification 3 Li Introduce co eoe eee ee Uude aen aa wa see ais 46 E Velen deus 3 1 2 System Overview 0066 6 L3 System Hardware Parts 7 1 4 Other 34 40 2 System View amp Disassembly 43 2l Erro ca e EE AERE REP VET Re EO EPI 43 2 2 System Disassembly PN ai 46 3 Definition amp Location of Connectors Switches Setting 66 4 Definition amp Location of Major 69 5 Pin Description of Major 71 5 1 Intel Pentium M Bani s 71 5 2 Intel 855GM GME North
184. SMT CAP 100P 2KV 5 1206 NPO SMT MEE 272011106701 CAP 10U 10V 480 2096 1206 Y5V S 272012105401 CAP IU CR 16V 1096 1206 X7R S 272021106501 100 10V 20 1210 7 272023106502 CAP 10U 25V M 1210 T2 5MM XS5R SM 272023475502 CAP 4 7U CR25V 20 1210 7 5 272030050302 CAP 5P 3KV 5 1808 NP O SMT only __________ 272030102401 1000 2 10 1808 7 5 48 C327 C806 272070475701 CAP 4 7U CR 6 3V 80 20 0603 Y5 C860 C908 Part Number 272010101301 272010101302 Part Number 27207522240 272075223707 271054409 cap 0047 osx c 272102104401 0 C1002 C11 C160 C206 C210 C219 CH em cies css C C C 272071105403 10V 10 0603 XSR SMT C10 C4 27207115440 10V 0603 X7R SM C482 C490 0603 X5R C1001 C151 C161 C239 C24 C283 2 4 C 9 C 2 s UA c C lt x 272102473402 __27010 1401 257 005 272105101401 100 507 5 0402 065 50 C18 C20 C503 272105101402 CAP I00P 50V 10 0402 NPO S 10 330 455 498 520 521 272105102408 CAPI000P CR SOV IO 0402 X7RSM 0960 962 4 272105102501 CAP1000P 50V 4 209 0402X7RS 100 1006 1007 1008 101 0 27207122540 27207133240 272072104402 e 2 in N N Q lt gt x
185. SPC 06703 2010 S soa 20 SENSEt SENSE 11 PU707B Box SESS Me 32 VOSENSE2 56 p 15 4 1 sono 5 PD722 Ports 1500 5 5903 B Zn S9s Sew 9525 558 1 BZVESC2VA NA 63 0402 4 0402 39405 gt amp s 0402 PC7BP e 80 20 10 rd 04900 80 20 1500 lt BZV55C2V4 NA 50 SOV Meds sos 50V T 7343 1000P BND dom 63V 0402 50 SENSE1 2 8 10 11 1 SENSE 2 ENSE1 8 1 1000 2 TS P PC6t 180P E 180 0402 1 PROB PR101 0402 10 24 9K 2K ej 10 55 GND 43VS_P 0402 0402 50 poss 1 1 PRids PRIA 310 1000P 15K 15K V 0402 15222 0402 0402 0402 PR97 10 1 1054 1 1 lt 195 50V sov 4 0402 JS 19 1 4 4 4 PR93 100K SHORT SMT1 0402 Z 1 ul NE GND PR103 rod p SGND2 0402 31 i 5 0 0402 1 2 INTVCC2 5 102 10K 0402 1 VDD5 9 m kpe 2N7002 1 PROS 100K 0402 1 sGND2 i D Pate 1 2N7002 4 lie Pais R103 1 2 7002 25 26 28 30 31 PWRON_SUSB ar 4 Prids 1M ET 0402 E zo lt 80500 MOTHER B D sGND2 Doa 316680900001 ASSY 411682700001 lumber Date Wednesday December 31 2003 Bheet 29 5 I 7 I T PDF created with FinePrint pdfFactory trial version http www fineprint com
186. ST and Geyserville III Support for DPWR signal to Banias processor for PSB power management Memory System Directly supports one DDR channel 64 bits wide 72 b with ECC Supports 200 MHz and 266 MHz DDR devices with max of 2 Double Sided SO DIMMs 4 rows populated with unbuffered PC1600 PC2100 DDR with ECC gt Supports 128 Mb 256 Mb and 512 Mbit technologies providing maximum capacity of 1 GB with only x 80500 N B Maintenance 16 devices gt All supported devices have 4 banks gt Supports up to 16 simultaneous open pages gt Supports page sizes of 2KB 4KB 8KB and 16KB Page size is individually selected for every row gt UMA support only 1 System Interrupt Supports 8259 and Processor System Bus interrupt delivery mechanism Supports interrupts signaled as upstream Memory Writes from PCI and Hub interface MSI sent to the CPU through the system Bus From IOxAPIC in ICH4 M Provides redirection for upstream interrupts to the System Bus Video Stream Decoder Improved HW Motion Compensation for 2 format decoder 18 ATSC formats supported Dynamic Bob and Weave support for Video Streams Software DVD at 60 fields second and 30 frames second full screen Support for 720x480 pixel resolution DVD quality encoding low CPU utilization 80500 N B Maintenance Video Overlay Single high quality scalable ov
187. Sr GND sGND7 1 127 10K 0402 PR129 1 H 10K 0402 1 7 SW 1 5 125 9 1 1 PR130 4 100K ZL Pceo 0402 1 0402 lt 10 10V SGND7 S ND7 80500 MOTHER B D Document PCB 316680900001 ASSY 411682700001 Number Date Wednesday December 31 2003 Bheet 30 5 z I 3 I z I T PDF created with FinePrint pdfFactory trial version http www fineprint com z 3 I iis CPU CORE PRA PRS 10K 10 0402 0402 gt 1 1 PRE 1 6 22K D gt VAMPWRGD 13 1 0402 J 4 9 I 1 PR 1U 0402 0 DVMAIN PL5 x 0402 5 0402 PR710 1202 100 GND_A 10V 5 1 96K 2012 DD CPU 80 20 0402 Luana 79 1 P 43V 184 DPRSLPVR 1 4 1 o 1 PL4 PMPs 2 0402 PD706 1202 100 4 4 4 dl 4 d 5 PRI3 00504 E 201
188. T 855 ADDIDZ E3 peel DVOBCLK 855 MDDCCLK vr E Kas HD 2 855 ADDID3 E2 855 DVOBDO 855 MIZCDATA 24 HOFS 855_ADDID4 Gs ADDIDIS DVOBDIO 855 DVOBD1 855 MDVICLK AOE 4 855 ADDIDS Ea ADDID A DVOBD 1 Re 855 2 855 MIZCCLK pois c HD A l Gog 15V 855 ADDIDG qa DVOBDI2 R4 855 DVOBD3 855 MDVIDATA Hal 855_ADDID7 Eg 0010 6 DVOBDI3 Pe 855 DVOBD4 855 DVOBCLK AOL FDE T ADDID 7 DVOBD 4 52 55 0 0805 See 5 7 10 5 Ns 855 DVOBDG 855 _DVOBCLKE T 128 71324 AGPBUSYR acpausy DVOBDI6 B55 DVOBD 855 DVOCCIKF AGP_ADSTBO 7 12 BE HDFT 11 HCLK Z BCLK DVOBDI7 22 Fee DVOBCCLEINT 855 DVOBD7 X AGP_ADSTBI 7 17 655 DPMS pg BCLK 02 59 0 0809 855 DVOBFLDSTL 855 DVOBBLANKA amp AGP_CBE 0 7 HOAZ DPMS 008019 355 DVOBD I0 7 2 13 HDPSLP DPSLP DVOBD 10 HUPS 57 2 gt gt aGP_CBE 2 57 Kae HOFS ass peus 2 13 HORS 855 DVOBDI 855 DVOCVSYNC ADIS HOES HDifi4 0402 Bal DREFOUK 855 DVOCHSYNC AGP ADi7 855 DVOCDS ABE GAS T 26 DREFCLK 855 DVOBCCLKINT 855_DVOC
189. THBRIDGE ICH4 M 1 2 TP47 TP52 2 x 3 CHANGE BEAD TO 0 OHM IN AUDIO REGION 14 SOUTHBRIDGE ICH4 M 2 2 TOUCHPAD METAL10 TOUCHPAD METALIO TOUCHPAD METALIO METALS M GND 4 CHANGE so SISTOR AND CAPACITANCE TO INCREASE 4 SUBWOOFER GAIN PAGEI5 CDROM HDD USB CONNECTOR 9 5 DELETE SO ONENT AROUND TV ENCODER PAGEI6 LAN RTL8100CL 3l 7 zl 4 9 17 R5C811 841 ed 18 IEEE1394 an AND 955 19 k d PAGE20 AUDIO CODEC ALC655 PAGE21 AUDIO AMPLIFIER SUBWOOFER PAGE22 KBC W83L950D MDC CARDREADER EC ESD PAGE23 TOUCHP PAD FWH LED PAGE24 PULL HIGH MIB on WISI 20046 NOS 25 PERPHERIAL em hs TP722 TP723 PAGE26 42 5VS DDR P 1 25V DDR P WA Pm 5 TOUCHPAD TOUCHPAD METALIO PAGE27 3VS_P 5VS_P B 39008 48 PAGE28 1 5 _ 1 05 _ SHORTSMTK ae aon 25V 29 1 8 P 1 35V BND as 3 2501 0402 PAGE30 1 2V 1 0V_M10 77 L1 20205 CPUCORE ane PAGE32 ADAPTER VMAIN PAGE33 CHARGER DISCHARGER 0900011 moon 0900011 0900011 8050 MTGT18NRD433 3016B MTG118 RD433 N 30X16 MTG118 RD433 N 30X16 MTG118NRD433_3016A MTG118NRD433_3016A TP58 TP59 RDOBO 051 NA RDOBO 051 NA 45 Ten MTG13 MTG14 1D3 0 0D11 1D3 0 0D11 1D3 0 0D11 1D3 0 0D11 MTG118 RD433 N 30X16 MTG118NRD433_016A MTG118 RD433 N 20X16 MTG118NRD433_3016B
190. T_VSYNC R136 0 2N7002 PY Y 14 Q8 is J702 2N7002 120Z 100M ATI_CRT_HSYNC R137 0 13 ATI CRT RED R783 0 158 2207 100 1 2 as i 55 ATI CRT GREEN R135 0 159 2207100 L74 1202 100 2 R139 0 160 2207 100 67 816 17 77 CHAGND 113 80500 N B Maintenance 8 5 Memory Test Error Either on board or extend SDRAM is failure or system hangs up Memory Test Error 1 If your system installed with expansion SO DIMM module then check them for proper installation 2 Make sure that your SO DIMM sockets Board level Troubleshooting are OK 3 Then try another known good SO DIMM modules Parts U714 J711 J712 U712 Replace the faulty R979 Replace R1030 Replace the faulty SDRAM module Motherboard R1031 R1011 R1016 R948 R949 R950 R955 R340 C337 C346 If your system host bus clock running at 100MHZ then make sure that SO DIMM module meet require of DDR 333 Check following parts and signals Signals 63 SMBCLK SMBDATA 510 71 DM O 7 MCB O 7 MAO MA3 MA 6 12 WEZ CASH RASA BA 0 1 NB DMS8 NB 058 CLK DDR O 5 CLK DDR O0 5 4 114 80500 N B Maintenance 8 5 Memory Test Error Either on board or extend SDRAM is failure or system hangs up 3V 197 2 5VS_DDR 1 25V_DDR O R340 L C3
191. These signals define which SSTL 2 banks are selected within each DDR SDRAM row The SMA and SBA signals combine to address every possible location within a DDR SDRAM device SRAS DDR Row Address Strobe SRAS may be heavily loaded and 5571 2 jrequires tw0 DDR SDRAM clock cycles for setup time to the DDR SDRAMs Used with SCAS and SWE along with SCS to define the system memory commands SCAS DDR Column Address Strobe SCAS may be heavily loaded and SSTL 2 requires two clock cycles for setup time to the DDR SDRAMs Used with SRAS and SWE along with SCS to define the system memory commands SWE Write Enable Used with SCAS and SRAS along with SCS to SSTL 2 define the DDR SDRAM commands SWE is asserted during writes to DDR SDRAM SWE may be heavily loaded and requires two clock cycles for setup time to the DDR SDRAMs SDQ 71 0 VO Data Lines These signals are used to interface to the DDR SDRAM SSTL 2 data bus NOTE ECC error detection is supported by the SDQ 71 64 signals Signal Name Type Description HDSTBP 3 0 IO Differential Host Data Strobes The differential source synchronous HDSTBN 3 0 AGTL are used to transfer HD 63 0 and DINV 3 0 at the 4x transfer rate Strobe Data Bits HDSTBP 3 HDSTBN 3 HD 63 48 DINV 3 HDSTBP 2 HDSTBN 2 HD 47 32 DINV 2 HDSTBP 1 HDSTBN 1 HD 31 16 DINV 1 HDSTBP 0 HDSTBN 0 HD 15 0 DINV 0 HIT T O Hit Indicates tha
192. W M2L3 K HEAD I 3 PARI 28 31010261040 SPC SCREW M2 6L4 K HD 10 8 NIB ARI 29 310102610603 SPC SCREW M2 6L6 K HEAD NIB NL 25 ARI 30 31010261160 SPC SCREW M2 6L16 K HEAD NIB PARI 3l 311102010252 SCREW M2L2 5 K HEAD NIB NLK 0 PARI AN 32 311102610603 SCREW 2 616 FLNG PANC NIW NL 2 PART 33 41168270000 PWA PWA 8050D ATIM Al4 64M MOTHE ASSEMBLY 34 41267180000 ASSY FAXMODEM 56 2 PART 99 42261430007 WIRE ASSEMBLY 36 44168170000 8050 11 1V 4 1 IONCSANYO 2 ASSEMBLY 31 44268090005 TOUCH PAD SYNATICS 313 PART 4 38 45168090003 HDD ME KIT 8050 ASSEMBLY 39 451680900033 COMBO MEKIT KME UJDAT750 8050 ASSEMBLY 40 531082132029 KBD 87 US CHICONY 8050 PARI change heatsink cpu and nor fh bridge P N 0 451 680900072 LA A change woofer ond screw fix woofer 01 CONTENTS OF CHANGE E RVS 0 4 0 30 4 0 5 3 Technology mode name STRU 8050 file name HOUSING_KIT 8050D z
193. W Wee s 22 HRCIN RCIN CLKRUNHIGPIO 24 7102 9805 0402 vss 14 CPU FERRE FERR GPIOGT oV cn 223 HINIT INIT GPIO 27 GPIO27 24 4 vss E 040 AMS 5 Gro 27 wa 67028 Be vss 14171922 SERIRQ SERIRQ ans vss SOT23AN 15 Ves 192223 LFRAME amp LERAME FWH4 SLP_S3 Ksusar 17 22 2325 PE 19 iRDQU X LDRQO SLP_S4 vss 1 18 SPISS TN 2 vss 8915 S MINIPCI PMER 19 Lm LADO FWHO PWRBTN ICH_PWRBTN 22 vss ne LADI FWHI SYS_RESET ICH SYS RESET 14 9 vss 1 A 192223 1400 3 lt lt LAD2 FWH2 LANRST ICH LAN RST 14 vss LABDSEWHS BATLOWWTPLO SB 14 1 SB SUSST VSS SUSCLK SUS_STAT LPCPD ICH VGATE 0402 23 vee 480501 lt SUSCLIC VaATENRMPWRGS TET 8270 1 i0KNA LDROi amp vss sZ ae INTRUDER THERMTRIP lt 4 oe vss ib RTCRST THRM SB_THRM 22 2 4421725331 PWROK 5 PWROK a T 2225 RSMRST lt 1250 RSMRST SMILINK 0 ATE vaas ARH SMLINK 1 SMLINKI 14 b Gib VBAS ye umm mro SSMBOLK SME CLK n Voss HIC 2 RTCX2 SMBALERT GPIO 11 24 A SPKR 14 20 R287 10K 0402 5 45V 43V VDD5S VDD5 VDD3S M 1431 DPRSLPVR 4 1 0 2816 V20 pps pn 14 ICH n o B D nae 24 HDPSLPR
194. X1 06030 BEAD NA SUVIN 2545A 04GXT USB 4PX2 DIP SUYIN 2522 08 1 1016 J015 J014 16 304 405 106 303 107 08 06030 GND UsB 14 USBP1 gt T 4x 4 ae 4 m 1 E 7 Jos GND USBI SHORT SMT4 CHOKE_ACM2012 GND UsB GND USB ld J017 SHORT SMT4 eS y 30702 SHORT SMT4 L4 men 06030 BEAD NA SHORT SMT4 GND GND UsB 80500 MOTHER B D lev 316680900001 ASSY 411682700001 Date Wednesday December 31 2003 Bheet 15 of 34 1 PDF created with FinePrint pdfFactory trial version http www fineprint com LAN RTL8100CL RTL8110S 42 58 DDR DVDD 9 9 1732 1 cvv 2 1202100 DVDD 2012 Close to RTL8100
195. X2 Special Crystal Input 2 This signal is connected to the 32 768 kHz crystal Other Clock Signals Signal Name Type Description CLK14 I Oscillator Clock Used for 8254 timers It runs at 14 31818 MHz This clock is permitted to stop during S1 M or lower states CLK48 I 48 MHz Clock This clock is used to run the USB controller It runs at 48 MHz This clock is permitted to stop during S1 M or lower states CLK66 I 66 MHz Clock This is used to run the hub interface It runs at 66 MHz This clock is permitted to stop during 51 or lower states Miscellaneous Signals Signal Name Type Description SPKR Speaker SPKR signal is the output of counter 2 and is internally ANDed with Port 61h bit 1 to provide Speaker Data Enable This signal drives an external speaker driver device which in turn drives the system speaker Upon PCIRST its output state is 0 NOTE SPKR is sampled at the rising edge of PWROK as a functional strap RTCRST RTC Reset When asserted this signal resets register bits in the RTC well and sets the RTC_PWR_STS bit bit 2 in GEN_PMCONS register NOTES 1 Clearing CMOS in an ICH4 based platform can be done by using a jumper on RTCRST or GPL or using SAFEMODE strap Implementations should not attempt to clear CMOS by using a jumper to pull VccRTC low 2 Unless entering the XOR Chain Test Mode the RTCRST input must always be high when all othe
196. Y 14 16 20 8 11 5 0 3 716 0 3 CFRAME CRST CREQ 54 58 60 MA 15PX2 ST z R1203 10 MS_SCLK R1213 33 CCLK 19 Q 2 12 14 MS INS amp MS BS MS SDIO 134 80500 N B Maintenance 8 15 IEEE 1394 Test Failure An error occurs when a IEEE 1394 device is installed IEEE 1394 Fail 1 Check if the 1394 device is installed properly 2 Confirm 1394 driver 15 installed ok Check following parts and signals Board level Troubleshooting Parts Signals Yes Correct it 17724 PCI AD 0 31 1394 PCIRST 0722 PCI C BE 0 3 22 PCDEVSEL EECK 1394 PCI FRAME EEDI 1394 PCI IRDY EEDO 1394 Check if BIOS setup is ok PCI TRDY TPBIAS PCI STOP d Replace TPA 6307 Motherboard PEL YOR 6307 PCI PERR 6307 PCI REQIZ Re test 2 Correct it 4 M 3V 43VS tPHY VDD XO 135 80500 N B Maintenance 8 15 IEEE 1394 Test Failure An error occurs when a IEEE 1394 device is installed PHYVDD 1394 AVCC 3 3V 24 8 20 7 Q VCCRAM 43V AAA 39 49 8 vcc 1207 100 62 65 75 R211 3 L746 65 EUR 3VS 76 89 90 29 _1394 1 pig R212 e CS P18 R218 1207 100 8 2K 4 PCI AD 0
197. __855 DDCK R353 1 0402 0402 7 0603 Less than 0 5 i R914 357850 855 CHT RED 11671 0402 855 RED IYAPi R357 1 0402 gt 1 i 287 12 EE ORT OTON 0402 855 GREEN GND IYAMZ 1761 0402 z1 0402 7 0603 Era 855 CHT BLUE YAY I ANA 2 0402 855 2 R1177 0402 2 042 Place near to GMCH i 1 1 J IYAM3 11781 0402 0 Ried 1 2 0402 O TXOUT 7 1 HXRCOMP HUB VREF R11791 0402 Riot 1 0402 AA RA Sra 4 4 4 R78 R149 R144 L Snout 2 DVOVREF CHANGE 0402 m Len Los 75N 7 12 1 C843 33P NAT 33P NA7 33P NA 040 040 0402 L 22 TXOUT1 12 Fo HYRCOMP 0 01U NA 0402 0402 0402 1 1 1 i T 0402 10 _ 10 4 4 10 al iH 480208 80 20 25V NB CONNECT TO TV ENCORDER 4 80 20 CHANGE i 50V TXOUT2 12 E i Non SSC TXOUT3 12 t TXOUTS 12 t GND 040250 GND A 3 855 CRT HSYNC R345 855 HSYNC 12 855 SYNC C SS CRT VSYNG Rit d 855 135 WHEN USE INTEGRATE ADD ALL RESISTOR R361 0402 i i 936 1 Dy 0402 Maximum length less than 0 5 1 Less than 0 5 1 E DERE am 1 9402 DVOCCLK 11 eu 5405 TXCLK ATI 7 voltage divider DVOCCLK 11 H 7 i i i i 0603 855_DVOBCCLKINT 0402 pe 1 855 DVOBCINTR R117 1 0402 i
198. a c c c o 0402 1 as R874 33 0402 CPU HCLK CPU 2 GND B2KNA CLK PD ado CPUCLKT2 8 2KINA CLK PCI 51 R862 33 NA 1 0402 CPU 1 0402 5 3VCLKPC Eum HE WO 44 75 33 1 0402 HCLK_CPU uM 2 1 2 12021004 1608 R860 wi B 8 2K 0402 diniy 2 4 7K 5 5 PWRGD 28 jo R825 33 1 0402 6402 VIT_PWRGD 10 Baro a3 3 0402 FWH 23 sessi wo PCICLKt i Re26 33 4 0402 T MINIPCI 18 010 220 VDDREF PCICLK2 R827 33 1 0402 17 0402 0402 0603 3VCLKANA VDD48 1 PCICLK_LAN 16 5 m H FS1 wood roe PCICK 1354 2176796 C789 _ 0797 C790 10 10 ed 10 FS2 Beene E PCICK KBC 10 10 10 10 TV tev 1 402 402 402 0402 3VCLK66 VDD3V66 1 PCICLKG SAOS S HOY 40 m R69 sov 50 sov 50V VDDCPUO QNS peer VODCPUI Fo 8 x cpu VDDPCIO per pp 824 33 1 0402 GNE amp PCICLK ICH 13 4561 1202 100 168 1 3VCLKPC 9829 33 1 0202 71 GNO s 22 042 1 SEMI 14 T 220 819 33 1 0402 x M 0402 0402 0603 GND 43V NDS 0798 C782 _ 6799 C78 10 10 10 1 1 T 1 10 TV tev 1 GND4 aves 3 24 0402 0402 0402 0402 Eid
199. addressing is disabled these signals are isolated no external internal pull ups are required Signal Name Type Description SDQS 8 0 Io Data Strobes Data strobes are used for capturing data During SSTL 2 writes SDQS is centered on data During reads SDQS is edge aligned with data The following list matches the data strobe with the data bytes There is an associated data strobe DQS for each data signal DQ and check bit CB group SDQS 7 gt SDQ 63 56 SDQS 6 gt SDQ 55 48 SDQS 5 gt SDQ 47 40 SDQS 4 gt SDQ 39 32 SDQS 3 gt SDQ 31 24 SDQS 2 gt SDQ 23 16 SDQS 1 gt SDQ 15 8 SDQS 0 gt SDQ 7 0 NOTE ECC error detection is supported by the SDQS 8 signal SCKE 3 0 Clock Enable These pins are used to signal self refresh power SSTL 2 down command to the DDR SDRAM array when entering system suspend SCKE is also used to dynamically power down inactive DDR SDRAM rows There is one SCKE per DDR SDRAM row These signals can be toggled on every rising SCK edge 5 5 4 2 1 Memory Address Copies These signals identical to SSTL 2 8 5 4 2 11 and are used to reduce loading for selective CPC clock per command These copies are not inverted SDM S8 0 Data Mask When activated during writes the corresponding data SSTL 2 groups in the DDR SDRAM are masked There is SDM for every eight data lines SDM can be sampled on both edges of the data strobes NOT
200. ae HOAZ 2 0428 43 ADINVES DINV2 4 99 01 ua DINV3 4 QH Lock Dade 26 45 D45 VCCP R264 56 0402 ERE pec 5 4 Si KS 0478 DEAS 4 lt 4 DEFER 0498 JP 4 HTRDY QH Towe 050 5 0 051 52 voiet HRS 0 2 HRS 950 052 HD 53 4 HRS 0 2 6 9518 053 63 i com 2 2 T 13 HAZOM 20 056 VCC 66 14 5 FERRE 0578 4 HOFS VCC 67 4 DPWR D58 DHSS VCC 68 HSPE DBR 059 DEED VCC 69 13 HSLP amp lt Hs 060 1 70 PM PS 3 95 061 HD62 vec_71 HIGNNE AF26 13 IGNNE BANIAS 13 HSMI HPWHGD SM HDSTBN O 3 4 BGA479 SKT3 18 HPWRGD lt G2 PWRGOOD DSTBNO HDSTBNET HPROCHOT DSTBN NM 22 HPROCHOT 3 EHE T B17 PROCHOT DSTBN2 DSTBN3 amp HDSTBPA 3 4 _ HSTPCLKK 13 HSTPCLKI STPCLK DSTBPO 4 3 HDPSLPY 2 SPE B7 DPSLP DSTBP1 DSTBP2 pi 18 A LINTO DSTBP3 UDETEPRS 13 M DA uri HITS gs 45 E 4 1823 HINITH INIT DRDY HDRDY 4 477 HOPURST K lt B11_ RESETI THERMDA OPU THERMDA CPU THERMDA 22 THERMDC CPU THERMDC 22 11 CLK ITP CPU ITP_C
201. al is used as the DDC data signal between the LFP and the GMCH 83 80500 N B Maintenance 5 3 Intel 82801DBM Controller Hub 4 Mobile ICH4 M 1 Hub Interface Signals Signal Name Type Description HI 11 0 IO Hub Interface Signals HI STB HI STBS VO Hub Interface Strobe Hub Interface Strobe Second One of two differential strobe signals used to transmit and receive data through the hub interface Hub Interface 1 5 mode this signal is not differential and is the second of the two strobe signals HI_STB VO Hub Interface Strobe Complement Hub Interface Strobe First HI_STBF One of two differential strobe signals used to transmit and receive data through the hub interface Hub Interface 1 5 mode this signal is not differential and is the first of the two strobe signals HICOMP VO Hub Interface Compensation Used for hub interface buffer compensation HI_VSWING I Hub Interface Voltage Swing Analog input used to control the voltage swing and impedance strength of hub interface pins LAN Connect Interface Signals Signal Name Type Description LAN_CLK I LAN Clock Driven by the LAN Connect component Frequency range is 5 MHz to 50 MHz LAN RXD 2 0 I Received Data The LAN Connect component uses these signals to transfer data and control information to the integrated LAN Controller These signals have integrated weak pull up resistors LAN TXD 2 0 Transmit Data
202. ance Diagnostics 7 1 Introduction Each time the computer is turned on the system BIOS runs a series of internal checks on the hardware This power on self test post allows the computer to detect problems as early as the power on stage Error messages of post can alert you to the problems of your computer If an error is detected during these tests you will see an error message displayed on the screen If the error occurs before the display is initialized then the screen cannot display the error message Error codes or system beeps are used to identify a post error that occurs when the screen 15 not available The value for the diagnostic port is written at the beginning of the test Therefore if the test failed the user can determine where the problem occurred by reading the last value written to the port by the debug card plug at MINI PCI slot 93 80500 N B Maintenance 7 2 Diagnostic Tool for Mini PCI Slot The Mini PCI DOG killer card is a single step debug tool which utilizes Mini PCI interface Type HI A and is able to hold a PCI bus cycle so that address data and control bus states on PCI bus can be inspected Especially the tool can help an engineer trace address data bus for BIOS read cycles as soon as power on and debug open or short circuit problems easily Usually this sort of problem will make a PC motherboard fail to boot P N 411906900001
203. another known good CPU module DIMM module and BIOS 2 Remove all of I O device FDD HDD CD ROM motherboard except LCD or monitor Using circuit diagram check the faulty parts 1 Replace faulty part Display 2 Connect the yo device to the OK M B one at a time to find out which part is causing the problem 106 8 3 Display 1 80500 N B Maintenance System Clock Check 43V R860 47K FSO 54 FS1 R863 4 7K 55 FS2 R894 47K 40 e 43V 3 R863 8 2K 4 1722 y 1207 100 CLKANA 1 26 37 1726 1202 100 CLK66 19 32 143 1202 100 CLKCPU 46 50 1718 py 1202 100 CLKPCI 8 14 2 X703 14 318MHZ 3 C804 T 1 C794 3V 3V 27 27 PR731 R831 10K 2K PR56 R821 0 CORE_CLKEN 0 VTT_PWRGD 28 o gt 3VS_P 715 100K PQS Ped P28 2N7002 PR57 0 VCCP PWRGD PR717 0 27 0703 LTC3728L FS2 FS1 FSO 00 gt x 0 1 100 00 0 00 UNIT MHZ 1 3 3 0712 Generator ICS950810 R874 p2 P3 44 45 R875 3392 HCLK CPU HCLK_CPU 0713 35 38 R865 R872 48M DREFCLK 48 49 R873 878 334 66M DEFSSCLK HCLK_MCH P4 ps U714 11 R816 33 PCICLK_MINIPCI gt 39 R895 33 R11
204. ard re flash Support ACPI Hardware fast Gate 20 with software programmable 33 80500 N B Maintenance 1 4 Other Functions 1 4 1 Hot Key Function mur ee Qe pA mr mir Brightness down Decreases the LCD brightness Brightness up Increases the LCD brightness F10 Battery Low Beep On Off Battery Low Beep Fo Fll 1 Panel Off On Toggle Panel on off EM Suspend to DRAM HDD Force the computer into either Suspend to HDD or Suspend to DRAM mode depending on BIOS Setup 34 80500 N B Maintenance 1 4 2 Power on off suspend resume button APM mode At APM mode Power button is on off system power ACPI mode At ACPI mode Windows power management control panel set power button behavior You could set 22 standby power off or hibernate must enable hibernate function in power Management to power button function Continue pushing power button over 4 seconds will force system off at ACPI mode 1 4 3 Cover Switch System automatically provides power saving by monitoring Cover Switch It will save battery power and prolong the usage time when user closes the notebook cover At ACPI mode there are four functions to be chosen at windows power management control panel gt None gt Standby 35 80500 N B Maintenance gt Off gt Hibernate must enable hibernate function in power management
205. at Day 24 08 Dee HOES R198 5242 0 1 0402 R289 B20 HD 7 56 R287 0 0402 51 ad HD 8 0402 0402 B24 HD9 5 HTCLK A12 5 HTDI c12 of A13 D10 HD TI HPROCHOT HTDO A12 10 HBRO pe HTMS 100 AE Di2 Tp 13 R141 Bia TMS 16 HDf14 1K HPREG 5 An 0146 15 0402 HPRDY A10 PREQ 9 A18 D15 HOAS 1 PRDY A19 1 H HOAT 208 0178 HOHE A21 D18 5 sib 5 GTLREFO Foot Diop M2 Hong Close to as possible lt 0 E28 0402 A23 D20 15 27 81 GTLREF2 5 0218 HD 22 R134 GTLRERS E HD 23 2k HPWRGD 26k 023 HD 24 0402 HCOMPT COMPO AZ Dow HD 25 1 2 GOMPI 288 0258 425 26 COMP2 A29 D26 128 DED o ____ 1__ comps 4 0 41 lt lt po M press H26 HD 29 GND HREQ 0 D29 N HD 30 RSVD_0 ae 1 amp HCOMP3 should be 014 nsvp 2 REQ2 Daz X28 15 35 route with 5 mil width X GL nsvD 3 HREQ REGSH 039 REGAK HD 35 CPU TESTI 4 HADS amp ADS 036 TEST2 0378 HOPE SS TS G16 TESTS 4 ADSTBO D38 1535 HDINVA O 3 4 HADSTB 1 ADSTB1 D39 HDINVWo 3 lt lt HDINV O HBRO N4 D40 026 HD 41 DINVOR 4 HBRO BRO Dare u
206. ative Functionality GPIO 17 16 Fixed as Output only Main power well Can be used instead as PC PCI GNT A B GPIO 17 can also alternatively be used for PCI GNT 5 Integrated pull up resistor GPIO 15 14 I Not implemented GPIO 13 12 I Fixed as Input only Resume power well Unmuxed GPIO 11 I Fixed as Input only Resume power well Can be used instead as SMBALERT GPIO 10 9 I Not implemented GPIO 8 I Fixed as Input only Resume power well Unmuxed GPIO 7 I Fixed as Input only Main power well Unmuxed GPIO 6 I Not Implemented in Mobile Assign to Native Functionality GPIO 5 2 I Fixed as Input only Main power well Can be used instead as PIRQ E H GPIO 1 0 I Fixed as Input only Main power well Can be used instead as PC PCI REQ A B GPIO 1 can also alternatively be used for PCI REQ 5 NOTE Main power well GPIO are 5V tolerant except for GPIO 43 32 Resume power well GPIO are not 5V tolerant Power and Ground Signals Signal Name Description VCC3_3 3 3 supply for core well I O buffers This power may be shut off in 53 54 55 or G3 states 5 1 5 supply for core well logic This power may be shut off in 53 54 55 or G3 states 1 5 V supply for Hub Interface 1 5 logic 1 8 V supply for Hub Interface 1 0 logic This power may be shut off in 53 54 55 or G3 states 5 Reference for 5 tolerance
207. cal systems when in the 51 Powered On Suspend 53 Suspend To 54 Suspend to Disk or 55 Soft Off states SLP_S3 S3 Sleep Control SLP_S3 is for power plane control It shuts off power to all non critical systems when in 53 Suspend RAM S4 Suspend to Disk or S5 Soft Off states SLP_S4 54 Sleep Control SLP_S4 is for power plane control It shuts power to all non critical systems when in the 54 Suspend to Disk 55 Soft Off state SLP_SS S5 Sleep Control SLP_S5 is for power plane control The signal is used to shut power off to all non critical systems when in the S5 Soft Off states PWROK Power OK When asserted PWROK is an indication to the ICH4 that core power and PCICLK have been stable for at least 1 ms PWROK can be driven asynchronously When PWROK is negated the ICH4 asserts PCIRST NOTE PWROK must deassert for a minimum of 3 RTC clock periods for the ICH4 to fully reset the power and properly generate the PCIRST output PWRBTN Power Button The Power Button causes SMI or SCI to indicate a system request to go to a sleep state If the system is already in a sleep state this signal causes a wake event If PWRBTN is pressed for more than 4 seconds this causes an unconditional transition power button override to the S5 state with only the PWRBTN available as a wake event Override occurs even if the system is in the 51 54 states This signal has an
208. connector i e primary digital monitor This signal is tri stated during a hard reset MDVIDATA DVI DDC Data signal is used as the DDC data for a digital DVO display connector i e primary digital monitor This signal is tri stated during a hard reset MDDCDATA VO DVI DDC Clock The signal is used as the DDC data for a digital DVO display connector i e secondary digital monitor This signal is tri stated during a hard reset MDDCCLK TO DVI DDC Data The signal is used as the DDC clock for a digital DVO _ display connector i e secondary digital monitor This signal is tri stated during a hard reset PANELVDDEN SSC Chip Data Control Can be used to control an external clock chip for SSC control LVDS LCD Flat Panel Power Control This signal is used enable power to the panel interface PANELBKLTE N LVDS LCD Flat Panel Backlight Enable This signal is used to enable the backlight inverter BLI PANELBKLTC LVDS LCD Flat Panel Backlight Brightness Control This signal is used as the Pulse Width Modulated PWM control signal to control the backlight inverter CRT DDC Clock This signal is used as the DDC clock signal between the CRT monitor and the GMCH CRT DDC Data This signal is used as the DDC data signal between the CRT monitor and the GMCH Panel DDC Clock This signal is used as the DDC clock signal between the LFP and the GMCH Panel DDC Data This sign
209. ctive to inactive transition of RESET then the processor executes its Built in Self Test BIST LINT 1 0 Local APIC Interrupt must connect the appropriate pins of all APIC Bus agents When the APIC is disabled the LINTO signal becomes INTR a maskable interrupt request signal and LINT1 becomes NMI a nonmaskable interrupt INTR and NMI are backward compatible with the signals of those names on the Pentium processor Both signals are asynchronous Both of these signals must be software configured using BIOS programming of the APIC register space and used either as or LINT 1 0 Because the APIC is enabled by default after Reset operation of these pins as LINT 1 0 is the default configuration indicates to the system that transaction must occur atomically This signal must connect the appropriate pins of both processor system bus agents For a locked sequence of transactions LOCK is asserted from the beginning of the first transaction to the end of the last transaction When the priority agent asserts BPRI to arbitrate for ownership of the processor system bus it will wait until it observes LOCK deasserted This enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock Probe Ready signal used by debug tools to determine processor debug readiness Probe Request signal used by debug tools to request debu
210. cts to PCI devices that need to request clock re start or prevention of clock stopping NOTE An external pull up to the core power plane 15 required REQ A I PC PCI DMA Request A B This request serializes ISA like GPIO 0 DMA Requests for the purpose of running ISA compatible DMA cycles over the PCI bus This is used by devices such as PCI based REQ 5 7 Super I O or audio codecs which need to perform legacy 8237 DMA GPIO 1 but have no ISA bus When not used for PC PCI requests these signals can be used as General Purpose Inputs REQ B can instead be used as the 6th PCI bus request GNT A PC PCI DMA Acknowledges This grant serializes GPIO 16 ISA like DACK for the purpose of running DMA ISA Master GNT B cycles over the PCI bus This is used by devices such as PCI based GNT 5 Super IO or audio codecs which need to perform legacy 8237 DMA GPIO 17 but have no ISA bus When not used for PC PCI these signals can be used as General Purpose Outputs GNTB can also be used as the 6th PCI bus master grant output These signal have internal pull up resistors IDE Interface Signals Signal Name Type Description PDCS1 SDCS1 Primary and Secondary IDE Device Chip Selects for 100 Range For ATA command register block This output signal is connected to the corresponding signal on the primary or secondary IDE connector PDCS3 SDCS3 Primary and Secondary IDE De
211. d together to indicate that it requires a snoop stall which can be continued by reasserting HIT and HITM together IERR Internal Error is asserted by a processor as the result of an internal error Assertion of IERR is usually accompanied by a SHUTDOWN transaction on the processor system bus This transaction may optionally be converted to an external error signal e g NMI by system core logic The processor will keep IERR asserted until the assertion of RESET BINIT or INIT Signal Name Type Description DBSY VO DBSY Data Bus Busy is asserted by the agent responsible for driving data on the processor system bus to indicate that the data bus is in use The data bus is released after DBSY is deasserted This signal must connect the appropriate pins on both processor system bus agents 1 DEFER is asserted by agent to indicate that a transaction cannot be guaranteed in order completion Assertion of DEFER is normally the responsibility of the addressed memory or Input Output agent This signal must connect the appropriate pins of both processor system bus agents DINV 3 0 IO DINV 3 0 Data Bus Inversion are source synchronous and indicate the polarity of the D 63 0 signals The DINV 3 0 signals are activated when the data on the data bus is inverted The bus agent will invert the data bus signals if more than half the bits within the covered grou
212. d GP33 FCTRL3 ram remi ___ ZO n 1 029 4 57 GP34 BANKO 0402 0402 0805 005 L i KIS VSS 7a lt 8020 8020 63V 9 2E 65 AVSS 24 50V 50V 10 BAT CLK R419 1 1 0402 GFSTIOEF aS DATA 455 1 0402 WB3L950D C Version 284583950002 GND GND losed to CONN 5VS 284583950002 av 1 AKA 247002 ASSY 481677700002 aA 4 1 DATA 1 BAT DATA 0402 ao 4 27002 5 H8 THRM 1 n BaT DATA R482 2 10 0402 2 KBC 8445 1 R481 fe 1 0402 ob 21 16 1 KIS 8385 1 i i 0402 5 i 1 LIMIT R428 1 0402 H8 LIMIT 0 for external flash 32 LUMIT 25 CTRL 1 ANA 0402 CTR N 33 CTRL 412 BLADJ 4 BEAD 6002 100 C478 168 1 06030 H8 SCI R475 120 010 mE A H 0402 480 2095 GND 50V X H8AGND GND 38 H8 PROCHOT amp R413 INK Ape 1 0402 E THERMAL SENSOR FAN CONTROLLER o P 4 1 H8 ADEN ms POWER BUTTON H8 RSMRST 1 1 Qi 4 1206 9 5058 1 1 PWRBTN 25 5 DDR ICH PWRBTN 5 A 5 Snes swe _ P719 R1002 43VS PWRBTNE _ Winn H7 RPSOE 10 TH 042 5 _ o T To E 0706 1000P VDD3 91 1 Kit H8 THRM DATA 18 115 0402
213. d transfer cache enhanced floating point and multi media unit and Streaming SIMD Extensions 2 5522 The Streaming SIMD Extensions 2 SSE2 enable break through levels of performance in multimedia applications including 3 D graphics video decoding encoding and speech recognition Use Source Synchronous Transfer SST of address and data to improve performance by transferring data four times per bus clock Support Enhanced Intel Speed Step technology which enables real time dynamic switching of the voltage and frequency between two performance modes 1 3 2 Clock Generator System frequency synthesizer ICS950812 Programmable output frequency divider ratios output rise fall time output skew Programmable spread percentage for EMI control Watchdog timer technology to reset system if 80500 N B Maintenance system malfunctions Programmable watchdog safe frequency Support I2C Index read write and block read write operations Use external 14 318MHz crystal gt Provides standard frequencies and additional 5 and 10 over clocked frequencies gt Supports spread spectrum modulation No spread Center Spread 0 35 0 5 or 0 75 or Down Spread 0 5 1 0 or 1 5 Offers adjustable PCI early clock via latch inputs Selectable or 2X strength for REF via 2 interface Efficient power management scheme through PDZ CPU STOP and PCI STOP Uses external 14 318MHz crystal Stop clocks and functional co
214. de down the notebook secure the housing by nineteen screws and secure two screws in the rear Replace the Wireless card CD DVD ROM hard disk drive CPU keyboard and battery pack Refer to sections 2 2 6 2 2 5 2 2 4 2 2 3 2 2 2 and 2 2 1 reassembly NNN BW NN 60 80500 N B Maintenance 2 2 10 LCD Panel Disassembly 1 Remove the battery keyboard hard disk drive CD DVD ROM drive and LCD assembly Refer to section 2 2 1 2 2 2 2 2 4 2 2 5 and 2 2 9 Disassembly 2 Remove the two rubber pads and two screws on the corners of the panel Figure 2 25 3 Insert a flat screwdriver to the lower part of the LCD cover and gently pry the frame out Repeat the process until the cover is completely separated from the housing 4 Remove the twelve screws and disconnect the cable Figure 2 26 Figure 2 25 Remove LCD cover Figure 2 26 Remove twelve screws and disconnect the cable 61 80500 N B Maintenance 5 Remove the six screws that secure the LCD bracket Figure 2 27 6 Disconnect the cable to free the LCD panel Figure 2 28 Figure 2 27 Remove the six screws Figure 2 28 Free the LCD panel Reassembly Replace the cable to the LCD 2 Attach the LCD panel s bracket back to LCD panel and secure with six screws 3 Replace the LCD panel into LCD housing and reconnect two cables to inverter board and secure with two screws 4 Fasten the LCD panel by ten screws 5 Fit the LCD cover and secure wi
215. ded for JTAG specification support VSSSENSE VSSSENSE is an isolated low impedance connection to processor core VSS It can be used to sense or measure ground near the silicon with little noise TDO Test Data Out transfers serial test data out of the processor provides the serial output needed for specification support TESTI TESTI TEST2 and TEST3 must be left unconnected but should have a TEST2 stuffing option connection to V SS separately using 1 k pull down TEST3 resisitors THERMDA Thermal Diode Anode THERMDC Thermal Diode Cathode THERMTRIP The processor protects itself from catastrophic overheating by use of an internal thermal sensor This sensor is set well above the normal operating temperature to ensure that there are no false trips The processor will stop all execution when the junction temperature exceeds approximately 125 C This is signalled to the system by the THERMTRIP Thermal Trip pin TMS TMS Test Mode Select is a specification support signal used by debug tools TRDY TRDY Target Ready is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer TRDY must connect the appropriate pins of both system bus agents TRST I TRST Test Reset resets the Test Access Port TAP logic TRST must be driven low during power on Reset 74 80500 N B Maintenance 5 2 Intel 855GM GME Nor
216. e power consumption of the RTL8100C L will be negligible The RTL8100C L also supports an auxiliary power auto detect function and will auto configure related bits of their own PCI power management registers in PCI configuration space 30 80500 N B Maintenance 128 pin QFP LQFP Integrated Fast Ethernet MAC Physical chip and transceiver in one chip 10 Mb s and 100 Mb s operation Supports 10 Mb s and 100 Mb s N way Auto negotiation operation PCI local bus single chip Fast Ethernet controller Compliant to PCI Revision 2 2 S Supports PCI clock 16 75MHz 40MHz S Supports PCI target fast back to back transaction Provides PCI bus master data transfers and PCI memory space or I O space mapped data transfers of RTL8100C L s operational registers lt Supports PCI VPD Vital Product Data Supports ACPI PCI power management Supports 25MHz crystal or 25MHz OSC as the internal clock source The frequency deviation of either crystal or OSC must be within 50 PPM Compliant to PC99 PC2001 standard Supports Wake On LAN function and remote wake up Magic Packet LinkChg and Microsoft wake up frame 31 80500 N B Maintenance Supports 4 Wake On LAN WOL signals active high active low positive pulse and negative pulse Supports auxiliary power on internal reset to be ready for remote wake up when main power still remains off Supports auxiliary power auto detect and sets the related capability of power
217. e ATI RED s Tou oou bU USE 22P 5 ATI CRAT GREEN GND 0402 0805 0402 0402 ATI CRT BLUE 3 Es tero o 4 a m ui SAV 180208 28020 cb 23v 10 0 4 J J J R76 R76 8767 C761 C780 C759 75 75 75 47 47 47 040 040 0402 SE 0402 0402 0402 5 5 5 310 3 10 10 25 80500 MOTHER B D ize lev 316680900001 ASSY 411682700001 Rot lumber Date Wednesday December 31 2003 7 o 34 5 z 3 I z I T PDF created with FinePrint pdfFactory trial version http www fineprint com VGA 1 21 0 10 2 4 1 9 139 1202 100 07100 endi v OVDD CORE1 8 T 1 t t VDDC 0 VDDP 0 T 152 1 voc 1 VDDP 1 DC 2 VDDP 2 4 4 4 4 4 0402 4 4 4 4 VDDC 3 VDDP 3 114
218. e FREQ STRP register CPUSLP CPU Sleep This signal puts the processor into a state that saves substantial power compared to Stop Grant state However during that time no snoops occur The ICH4 can optionally assert the CPUSLP signal when going to the S1 M state FERR Numeric Coprocessor Error This signal is tied to the coprocessor error signal on the processor FERR is only used if the ICH4 coprocessor error reporting function is enabled in the General Control Register Device 31 Function 0 Offset DO bit 13 If FERRE is asserted the ICH4 generates an internal IRQ13 to its interrupt controller unit It is also used to gate the IGNNE signal to ensure that IGNNE is not asserted to the processor unless FERR is active FERR requires an external weak pull up to ensure a high level when the coprocessor error function is disabled NOTE FERR can be used in some states for notification by the processor of pending interrupt events This functionality is independent of the General Control Register bit setting CPU Interrupt INTR is asserted by the ICH4 to signal the processor that an interrupt request is pending and needs to be serviced It is an asynchronous output and normally driven low Speed Strap During the reset sequence ICH4 drives INTR high if the corresponding bit is set in the FREQ STRP register Processor Interface Signals Continued Signal Name Type Description IGNNE O Ignore N
219. ease change the faulty part then end R1091 PCI 131 80500 Maintenance 8 14 CardBus amp Reader Test Error An error occurs when a PC card device is installed PC Card Slot Failure 1 Check if the PCMCIA CARD device is installed properly Board level 2 Confirm PCMCIA card driver is installed ok Troubleshooting Yes Parts Signals 0727 Check following parts and signals AD O 31 PCIRST J716 C BE 0 3 P_GNTO U728 DEVSEL PIRQA Replace 16 FRAME SUSB Try another known good PCMCIA card device Motherboard 09 IRDY RIZ TRDY PCLK_CARD VCC5_EN VCC3_EN BAR VPPDO Re test SUM Change the faulty PERR VPPD1 OK part then end SERR VPPOUT P_REQO TV No SERIRQ TOM STOP 132 80500 N B Maintenance 13 Mini PCI Test Error An error message is shown after Mini PCI device is installed or the Mini PCI device does t work 3V 5V 18 97 R179 43V RIII R1007 10K 13 PCI_INTD PCI_GNT2 PCI REQ24 R1068 R1080 R1083 P13 P14 PCI PCI_STOP Ww PCLKRUN PCI WIRELESS 1424 PCLIRDY FRAM PCI PCI_TRDY U715 PCI AD 0 31 PCI ADI7 R1092 100 48 LAD 0 3 PCI_C BE 0 3 R1075 1091 LFRAME LRDQO LPCDRQ 3V 09 E PCIRST 9 i JL8 R1077 0 26 2 10 MEI 3V
220. ed to transfer data on the AGP interface GCBE 3 0 VO Command Byte Enable AGP During FRAME Operation During the address phase of a AGP transaction the G_CBE 3 0 signals define the bus command During the data phase the G_CBE 3 0 signals are used as byte enables The byte enables determine which byte lanes carry meaningful data The commands issued on the G_CBE signals during FRAME based AGP transactions are the same G_CBE command described in the PCI 2 2 specification During PIPE Operation When an address is enqueued using PIPE the C BE signals carry command information The command encoding used during PIPE based AGP is different than the command encoding used during FRAME based AGP cycles or standard PCI cycles on a PCI bus During SBA Operation These signals are not used during SBA operation Parity During FRAME Operation G_PAR is driven by the GMCH when it acts as a FRAME based AGP initiator during address and data phases for a write cycle and during the address phase for a read cycle G_PAR is driven by the GMCH when it acts as a FRAME based AGP target during each data phase of a FRAME based AGP memory read cycle Even parity is generated across AD 31 0 and G_CBE 3 0 During SBA and Operation This signal is not used during SBA and operation PCIRST from the 4 is assumed to be connected to RSTIN is used to reset interface logic within the G
221. eep the strobe active PDIOR or SDIOR on reads PDIOW RDY or SDIOW on writes longer than the minimum width It adds wait states to PIO transfers SIORDY Primary and Secondary Disk Read Strobe Ultra DMA Reads from Disk When reading from disk the ICH4 latches data on rising and SDRSTB SWDMA Ie RDY falling edges of this signal from the disk Primary Secondary Disk DMA Ready Ultra DMA Writes to Disk When writing to disk this is de asserted by the disk to pause burst data transfers Interrupt Signals Signal Name Type Description SERIRQ Io Serial Interrupt Request This pin implements the serial interrupt protocol PIRQ D A VOD PCI Interrupt Requests In Non APIC Mode the PIRQx signals can be routed to interrupts 3 4 5 6 7 9 10 11 12 14 or 15 as described in the Interrupt Steering section Each PIRQx line has separate Route Control Register In APIC mode these signals are connected to the internal I O APIC in the following fashion PIRQ A is connected to IRQ16 PIRQ B to IRQ17 PIRQ C to 18 and PIRQ D to IRQ19 This frees the legacy interrupts PIRQ H E VOD Interrupt Requests In Non APIC Mode the PIRQx signals GPIO 5 2 can be routed to interrupts 3 4 5 6 7 9 10 11 12 14 or 15 as described in the Interrupt Steering section Each PIRQx line has a separate Route Control Register In APIC mode these signals are connected to the internal I O APIC in the fol
222. emove the battery pack Refer to section 2 2 1 Disassembly 2 Remove two screws fastening modem card s compartment cover Refer to steps 1 2 of section 2 2 6 Disassembly 3 Remove two screws fastening the modem card Figure 2 14 4 Lift up the modem card and disconnect the cord Figure 2 15 Figure 2 14 Remove two screws Figure 2 15 Disconnect the cord Reassembly 1 Reconnect the cord and fit the modem card 2 Fasten the modem card by two screws 3 Replace the modem card s compartment cover by two screws Refer to step 2 of section 2 2 6 reassembly 4 Replace the battery pack Refer to section 2 2 1 reassembly 55 80500 N B Maintenance 2 2 8 DDR SDRAM Disassembly 1 Carefully put the notebook upside down And remove the battery pack See section 2 2 1 disassembly 2 Remove two screws fastening the DDR compartment cover to access the SO DIMM socket Figure 2 16 Figure 2 16 Remove the cover Figure 2 17 Remove the SO DIMM 3 Pull the retaining clips outwards and remove the SO DIMM Figure 2 17 Reassembly 1 To install the DDR match the DDR s notched part with the socket s projected part and firmly insert the SO DIMM into the socket at 20 degree angle Then push down until the retaining clips lock the DDR into position 2 Replace two screws to fasten the DDR compartment cover 3 Replace the battery pack See section 2 2 1 reassembly 56 80500 N B Maintenance 2
223. enabling more complex and realistic texture and lighting effects than ever before gt Significant improvement over first generation shaders introduced in DirectX 8 with a much more powerful and intuitive instruction set gt Offers full support for this feature OpenGL applications MOOTHVISION 2 0 Flexible Anti Aliasing and Anisotropic Filtering 2x 4x 6x full scene anti aliasing modes Adaptive algorithm with programmable sample patterns 2x 4x 8x 16x anisotropic filtering modes WV Adaptive algorithm with bi linear performance and tri linear quality options 80500 N B Maintenance High Performance Memory Support gt Incorporates support for DDR SDRAM SGRAM gt Features key items from ATI s third generation HYPER Z III technology that conserves memory bandwidth for improved performance in demanding applications Dual Display Support gt Leading edge technology fully optimized with HYDRA VISION flexibly supports multiple combinations of notebook LCD traditional CRT monitors flat panel displays and TV Features Dual Channel DVI support 230MHz LVDS transmitter supports LCD panels up to QXGA 2048x1536 resolution Integrated 165MHz TMDS transmitter supports external flat panels up to UXGA 1600x1200 resolution WV High performance DAC speeds of 400MHz Features in Detail 1 VIDEO Acceleration gt MIO allows the integration of industry leading digital v
224. erlay and second Sprite to support second overlay Multiple overay functionality provided via Arithmetic Stretch Blt Direct YUV from Overlay to TV out Independent Gamma Correction Independent Brightness Contrast Saturation Independent Tint Hue support Destination Color keying Source Chromakeying Maximum source resolution of 1920x1080 pixels Maximum overlay clock of 133 MHz 200 MHz provides a pixel resolution up to 1600x1200 60Hz or 1280x1024 85 Hz Display gt Analog Display Support 350 MHz integrated 24 bit RAMDAC that can drive a standard progressive scan analog monitor up to 1800x1350 85 Hz accompanying I2C and DDC channels provided through multiplexed interface hot plug and display support Dual independent pipe with single display support Simultaneous Same images and native display timings on 80500 N B Maintenance each display device gt DVO DVOB support gt Digital video out port DVOB with 165 MHz dot clock 12 bit interface Variety of DVO devices channel Compliant with DVI Specification 1 0 thereby providing support for flat panel up to 2048x1536 pixel resolution or digital CRT up to 1920x1080 pixel resolution 1 3 4 I O Controller Hub INTEL 82801DBM The INTEL 82801DBM ICHA M integrates three Universal Serial Bus 2 0 Host Controllers the Audio Controller with AC 97 Interface the IDE Master Slave controllers and Intel I O Hub architecture The PCI to LPC Bridge Advanced P
225. figurations so that compact high performance systems can be implemented easily A full set of software drivers and utilities are available to allow advanced operating systems such as Windows ME Windows 2000 and Windows XP to take full advantage of the hardware capabilities Features such as bus mastering IDE Plug and Play Advanced Power Management APM with application restart software controlled power shutdown Following chapters will have more detail description for each individual sub systems and functions 80500 N B Maintenance 1 2 System Overview Mobile Pentium M Processor 1 56 1 9GHz Dothan 2 0GHz and above Thermal spec 35W TDP Core logie Intel 855GME ICH4 M chipset VGA Control ATi M10 System BIOS ST39SF040 Memory DDR RAM Apacer 77 11021 460 Samsung 16 16 256MB Ist Apacer 77 11021 580 Winbond 16 16 256MB 2nd A DATA 256MB Video Memory Share memory 32Mb Clock Generator ICS 950812 Audio System AC97 CODEC Advance Logic Inc ALC655 AC97 Link MDC Mobile Daughter Card Askey V1456VQL P1 INT PU AN 80500 N B Maintenance 1 3 System Hardware Parts 1 3 1 Intel Banias Processors in Micro FCPGA Package Intel Banias Processors with 478 pins Micro FCPGA package The first Intel mobile processor with the Intel Net Burst micro architecture which features include hyper pipelined technology a rapid execution engine a 400 system an execution trace cache advanced dynamic execution advance
226. g a parity error either detected internally or reported via the PERR signal T O Target Ready TRDY indicates the ICH4 s ability as a Target to complete the current data phase of the transaction TRDY is used in conjunction with IRDY A data phase is completed when both TRDY and IRDY are sampled asserted During a read TRDY indicates that the ICH4 as a Target has placed valid data on AD 31 0 During a write TRDY indicates that the ICH4 as a Target is prepared to latch data TRDY is an input to the ICH4 when the ICH4 is the Initiator and an output from the ICH4 when the ICH4 is a Target TRDY 15 tri stated from the leading edge of PCIRST TRDY remains tri stated by the ICH4 until driven by a target 4 0 5 GPIO 1 PCI Requests The 4 supports up to 6 masters on the PCI bus REQ 5 is muxed with PC PCI REQ B must choose one or the other but not both If not used for PCI or PC PCI REQ 5 REQ B J can instead be used as GPIO 1 NOTE REQ 0 is programmable to have improved arbitration latency for for supporting PCI based 1394 controllers GNT 4 0 5 GNT B GPIO 17 PCI Grants The ICH4 supports up to 6 masters on the PCI bus GNT 5 is muxed with PC PCI GNT B must choose one the other but not both If not needed for PCI or PC PCI GNT 5 can instead be used as a GPIO Pull up resistors are not required on these signals If pu
227. g operation of the processor Processor Hot will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature This indicates that the processor Thermal Control Circuit has been activated if enabled This signal may require voltage translation on the motherboard Processor Power Status Indicator signal This signal is asserted when the processor is in a lower state Deep Sleep and Deeper Sleep Signal Name Type Description PWRGOOD PWRGOOD Power Good is a processor input The processor requires this signal as a clean indication that the clocks and power supplies are stable and within their specifications Clean implies that the signal will remain low capable of sinking leakage current without glitches from the time that the power supplies are turned on until they come within specification The signal must then transition monotonically to a high state PWRGOOD can be driven inactive at any time but clocks and power must again be stable before a subsequent rising edge of PWRGOOD The PWRGOOD signal must be supplied to the processor it is used to protect internal circuits against voltage sequencing issues It should be driven high throughout the boundary scan operation ITP CLK 1 0 ITP CLK 1 0 are copies of BCLK that are used only in processor systems where no debug port is implemented on the system
228. he IDE DMA acknowledge PDDAK or SDDAK Primary and Secondary Disk Stop Ultra DMA ICH4 asserts this signal to terminate a burst 86 80500 N B Maintenance 5 3 Intel 82801DBM Controller Hub 4 Mobile ICH4 M 4 IDE Interface Signals Continued LPC Interface Signals Signal Name Type Description LAD 3 0 VO LPC Multiplexed Command Address Data For the LAD 3 0 FWH 3 0 signals internal pull ups are provided LFRAME LPC Frame LFRAME indicates the start of an LPC cycle or an FWH 4 abort LDRQ 1 0 I LPC Serial DMA Master Request Inputs LDRQ 1 0 are used to request DMA or bus master access These signals are typically connected to an external Super I O device An internal pull up resistor is provided on these signals USB Interface Signals Signal Name Type Description USBPOP IO Universal Serial Bus Port 1 0 Differential These differential USBPON pairs are used to transmit data address command signals for ports 0 USBPIP and 1 These ports can be routed to USB UHCI Controller 1 or the USBPIN USB EHCI Controller NOTE No external resistors are required on these signals The ICH4 integrates 15 k pull downs and provides an output driver impedance of 45 which requires no external series resistor Signal Name Type Description PIORDY I Primary and Secondary I O Channel Ready PIO This signal PDRSTB PWDMA will k
229. ideo features including advanced de interlacing algorithms for unprecedented video quality and integrated digital TV decode capability Includes programmable independent gamma control for the video overlay gt New FULLSTREAM technology removes blocky artifacts from streaming and Internet video and 80500 N B Maintenance provides sharper image quality gt Integrated general purpose engine capable of performing both forward and inverse discrete cosine transform and motion compensation MC support for the acceleration of MPEG encoding and decoding as well as DV digital video encoding and decoding 1 3 6 CardBus CB710 L Features gt 3 3V operation with 5V tolerant gt 208 pin LQFP 209 ball LFBGA package for CB710 gt 328 ball LFBGA package for CB720 gt PCI Interface compliant with PCI Local Bus Specification Revision 2 2 PCI Bus Power Management Interface Specification Revision 1 1 PCI Mobile Design Guide Version 1 1 Advanced Configuration and Power Interface Specification Revision 1 0 CardBus Interface OE CE Compliant with PC Card Standard 8 0Support Standardized Zoomed Video Register Model 13 amp 3 1 1012110592051 RK 8050D N B Maintenance Support CardBay PC card interface Smart Card Interface Compliant with PC SC Specification 1 0 Support ISO7816 0 and 1 asynchronous communication protocols Two power enable pins to support 5V and 3V smart cards Support programmab
230. ignal Descriptions Continued GPIO I F Total Type Comments GPIO I F Total Type Comments RSTIN I Reset Primary Reset Connected to PCIRST of ICH4 M CMOS PWROK I Power OK Indicates that power to GMCH is stable CMOS AGPBUSY AGPBUSY Output of the GMCH IGD to the ICH4 M which CMOS indicates that certain graphics activity is taking place It will indicate to the ACPI software not to enter the C3 state It will also cause a C3 C4 exit if C3 C4 was being entered or was already entered when AGPBUSY went active Not active when the IGD is in any ACPI state other than DO External Thermal Sensor Input This signal is an active low input to the GMCH and is used to monitor the thermal condition around the system memory and is used for triggering a read throttle The GMCH can be optionally programmed to send a SERR SCI or SMI message to the ICH4 M upon the triggering of this signal SSC Chip Clock Control Can be used to control an external clock chip with SSC control MDCCLK Uo DVO I2C Clock This signal is used as the 2 for a digital DVO _ display i e TV Out Encoder TMDS transmitter This signal is tri stated during a hard reset MDCDATA DVO I2C Data This signal is used as the DC DATA for a digital display i e TV Out Encoder TMDS transmitter This signal is tri stated during a hard reset MDVICLK DVI DDC Clock This signal is used as the DDC clock for a digital display
231. includes Realtek s impedance sensing techniques that makes device load on outputs and inputs can be detected 20 80500 N B Maintenance Meets performance requirements for audio on PC99 2001 systems Meets Microsoft WHQL WLP 2 0 audio requirements 16 bit Stereo full duplex CODEC with 48KHz sampling rate Compliant with 97 2 3 specifications 14 318MHz 24 576MHz PLL to save crystal 12 288MHz BITCLK input can be consumed Integrated PCBEEP generator to save buzzer Y Interrupt capability Three analog line level stereo inputs with 5 bit volume control LINE IN CD AUX High quality differential CD input Two analog line level mono input PCBEEP PHONE IN Two software selectable MIC inputs applications software selectable Boost preamplifier for MIC input 50mW 20 amplifier External Amplifier Power Down EAPD capability Power management and enhanced power saving features Stereo MIC record for AEC BF application 21 80500 N B Maintenance gt Supports Power Off CD function gt Adjustable VREFOUT control Supports double sampling rate 96K Hz of DVD audio playback gt Support 48KHz of S PDIF output is compliant with AC 97 rev2 3 specification gt Power support Digital 3 3V Analog 3 3V 5V 1 3 8 MDC PCTEL MODEM DAUGHTER CARD PCT2303W ASKEY V1456VQL P1 The PCT2303W chipset is designed to meet the demand of this emerging worldwide AMR MDC market The combination of P
232. industry which enable the use of the progressive new features in upcoming applications but without compromising performance ATIs support of support of DirectX 9 features highly optimized Open GL support and flexible memory configurations allow implementations targeted at the gaming enthusiast consumer business and workstation platforms The Realtek RTL8100C L is a highly integrated cost effective single chip Fast Ethernet controller that provides 32 bit performance PCI bus master capability and full compliance with IEEE 802 3u 100Base T specifications and IEEE 802 3x Full Duplex Flow Control It also supports the Advanced Configuration Power management Interface ACPI The VT6307L is a single chip PCI Host Controller for IEEE 1394 1995 Release 1 0 and IEEE 1394a P2000 It implements the Link and PHY layers for IEEE 1394 1995 High Performance Serial Bus specification release 1 0 and 1394a P2000 It is compliant with 1394 Open HCI 1 0 and 1 1 with DMA engine support for high performance data transfer via a 32 bit bus master PCEI host bus interface The VT6307L supports 100 200 and 400 Mbit sec transmission via an integrated 2 port PHY The VT6307L services two types of data packets asynchronous and isochronous real time The 1394 link core performs arbitration requesting packet generation and checking and bus cycle master operations It also has root node capability and performs retry operations The RICOH R5C592 CardBus Media Reader
233. insert wait states after each 32 byte block is transferred 79 80500 N B Maintenance 5 2 Intel 855GM GME North Bridge 6 AGP PCI Signals Semantics Descriptions Continued ATP PCI Signals Semantics Descriptions Continued Signal Name Type Description GTRDY IO AGP G_TRDY Target Ready During PIPE and SBA Operation Not used while enqueueing requests via AGP SBA and PIPEZ but used during the data phase of and SBA transactions During FRAME Operation G_TRDY is an input when the GMCH acts as an AGP initiator and is an output when the GMCH acts as a FRAMEZ based AGP target The assertion of G_TRDY indicates the target s ability to complete the current data phase of the transaction During Fast Write Operation In Fast Write mode G_TRDY indicates the AGP compliant target is ready to receive write data for the entire transaction when the transfer size is less than or equal to 32 bytes or is ready to transfer the initial or subsequent block 32 bytes of data when the transfer size is greater than 32 bytes The target 15 allowed to insert wait states after each block 32 bytes is transferred on write transactions GSTOP VO AGP G_STOP Stop During PIPE and SBA Operation This signal is not used during PIPE or SBA operation During FRAME Operation G_STOP is an input when the GMCH acts as a FRAME based initiator and is an output when the GMCH acts as a
234. into the receiving buffers by ADSTB 1 0 Address signals are used as straps which are sampled before is deasserted A20M ADS If A20M Address 20 Mask is asserted the processor masks physical address bit 20 A207 before looking up a line in any internal cache and before driving a read write transaction on the bus Asserting 20 emulates the 8086 processor s address wrap around at the 1 Mbyte boundary Assertion of 20 is only supported in real mode A20Mf 1 an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction ADS Address Strobe is asserted to indicate the validity of the transaction address on the A 31 3 and REQ 4 0 pins bus agents observe the ADS activation to begin parity checking protocol checking address decode internal snoop or deferred reply ID match operations associated with the new transaction ADSTB 1 0 VO Address strobes are used to latch A 31 3 and REQ 4 0 on their rising and falling edges Strobes are associated with signals as shown below Signals Associated Strobe 4 0 A 16 3 ADSTB 0 A 31 17 ADSTB 1 BCLK 1 0 The differential pair BCLK Bus Clock determines the system bus frequency All processor system bus agents must receive these signals to drive
235. ion of Major Components 4 1 Mother Board A 015 0524 0 15 8 016 PU2 PU3 a PUI4 PU2 3VS 5VS Voltage Generator CPU Core Voltage Generator PU14 1 8V 1 35V Voltage Generator PUI15 2 5VS 1 25V Voltage Generator U2 TV Encoder Controller U15 SYS BIOS Controller U16 WINBOND KBC Controller U524 TPA02012 Audio Amplifier 69 80500 N B Maintenance 4 Definition amp Location of Major Components 4 2 Mother Board B U710 u706 0714 0715 0706 0710 0713 0714 0715 0719 0724 0725 0726 0727 Thermal Sensor Fan Controller ATI M10 P Intel BANIAS CPU Intel 855GM GME North Bridge Intel 4 South Bridge LAN RTL8100CL Controller 1394 Controller SUBWOOFER AMP Controller Audio CODEC ALC655 CB710 Card Bus Reader Controller 70 80500 N B Maintenance 5 Pin Descriptions of Major Components 5 1 Intel Pentium M Banias Processor 1 Signal Name Type Description A 31 3 VO 31 3 Address define 2 32 byte physical memory address space In sub phase 1 of the address phase these pins transmit the address of a transaction In sub phase 2 these pins transmit transaction type information These signals must connect the appropriate pins of both agents the Intel Pentium M processor system bus 31 3 are source synchronous signals and are latched
236. lation Board level Troubleshooting Check following parts and signals Parts Signals 17715 PCIRST 0 CDROM_COMM J708 RSTDRV2 Q37 SIORDY 041 SDD 0 15 R492 SDA O 2 476 SDIOR R909 SDIOW 2833 SDDACK 2834 SDCS1 L723 SDCS3 SDDREQ 15 5V 5V_CDROM CDROM_LEFT CDROM_RIGHT Yes Replace Motherboard Re Test Yes Replace OK the faulty parts 122 80500 N B Maintenance 9 CD ROM Test Error CD ROM driver can t run normally maybe an error message is shown when reading data from CD ROM 3V 5V_CDROM L723 45V 120Z 100M 38 42 R833 R834 YY 47K 82K SD D 0 15 6 21 5 SDIOW 25 SDIOR 1 5 SIORDY 9 27 0715 SDDACK 28 18015 29 e J708 ICH4 SDA O 2 31 33 34 50 51 35 SDCS3 5 F 2 PCIRST 0 UK o R909 0 RSTDRV2 5 2 R476 10K 041 DTC144TKA E P20 18 C507 e 53 6 8K LEFT 1 4 037 20 C513 10 R547 68K _CDROM_RIGHT 2 DTCI44TKA U726 M 19 C515 022 R550 0 DROM COMM 3 AUDIO E CODEC R549 R546 gt R537 6 8 6 8K gt 6 8K 123 80500 N B Maintenance 10 Audio Failure There is trouble with the sound from speaker or completely no sound Audio Failure 1 Check if speaker cables are connected properly Board level
237. le RESET PCIRST from ICH4 M is asserted and for approximately 1 ms after 15 deasserted The CPURST allows the processor to begin execution in a known state Note that the ICH4 M must provide CPU strap set up and hold times around CPURST This requires strict synchronization between GMCH CPURST deassertion and ICH4 M driving the straps Signal Name Type Description DINV 3 0 VO Dynamic Bus Inversion Driven along with the HD 63 0 signals AGTL Indicates if the associated signals are inverted or not DINV 3 0 are asserted such that the number of data bits driven electrically low low voltage within the corresponding 16 bit group never exceeds 8 DINV Data Bits DINV 3 HD 63 48 DINV 2 HD 47 32 DINV 1 HD 31 16 DINV 0 HD 16 0 DPSLP I Deep Sleep This signal comes from the ICH4 M device providing CMOS an indication of C3 and C4 state control to the CPU Deassertion of this signal is used as an early indication for C3 and C4 wake up to active HPLL Note that this is a low voltage CMOS buffer operating on the FSB VTT power plane DRDY TO Data Ready Asserted for each cycle that data is transferred AGTL HA 31 3 Vo Host Address Bus HA 31 3 connects to the CPU address bus AGTL During processor cycles the 31 3 are inputs GMCH drives HA 31 3 during snoop cycles on behalf of Hub interface HA 31 3 are transferred at 2x rate Note that the address is inverted on the CPU
238. le card clock frequencies Programmable F and D parameters to support different data rates One traffic LED pin Secure Digital Interface Compliant with SD Memory Card Specification Version 1 0 Support 4 parallel data lines Has an optional reference clock source to control the operating clock frequency of SD card Up to 1OMByte sec Read Write rate when the optional reference clock source is used Contains 16 Bytes of data buffer to regulate the data flow between PCI interface and the SD card interface Support Write Protect Switch Support Card Detect either by DAT3 or by dedicated Card Detect Switch One Traffic LED pin gt gt 80500 N B Maintenance One power enable pin Memory Stick Interface Compliant with Memory Stick Standard Format Specification Version 1 3 Has an optional reference clock source to control the operating clock frequency of Memory Stick Up to 2 5MByte sec Read Write rate when the optional reference clock source is used Stick interface One Traffic LED pin One power enable pin Smart Media Interface One traffic LED pin Interrupt configuration Supports CLKRUN protocol Supports SUSPEND Supports D3STATE 4 Supports Zoomed Video port lt Power Switch Interface P Misc Control Logic 80500 N B Maintenance Supports socket activity LED Supports 12 GPIOs and GPE Supports PCI LOCK 1 3 7 97 AUDIO SYSTEM Advance Logic Inc ALC655
239. ll ups are used they should be tied to the Vec3_3 power rail GNT B Z GNT 5 Z GPIO 17 has an internal pull up PAR T O Calculated Checked Parity PAR uses even parity calculated on 36 bits AD 31 0 plus C BE 3 0 Even parity means that the ICH4 counts the number of 1s within the 36 bits plus PAR and the sum is always even The ICH4 always calculates PAR on 36 bits regardless of the valid byte enables The ICH4 generates PAR for address and data phases and only guarantees PAR to be valid one PCI clock after the corresponding address or data phase The ICH4 drives and tri states PAR identically to the AD 31 0 lines except that the ICH4 delays PAR by exactly one PCI clock PAR is an output during the address phase delayed one clock for all ICH4 initiated transactions PAR is an output during the data phase delayed one clock when the ICH4 is the Initiator of a PCI write transaction and when it is the Target of a read transaction ICH4 checks parity when it is the Target of a PCI write transaction If a parity error is detected the ICH4 will set the appropriate internal status bits and has the option to generate NMI PCICLK PCI Clock This is a 33 MHz clock PCICLK provides timing for all transactions on the PCI Bus NOTE This clock does not stop based on STP_PCI signal PCICLK only stops based SLP_S1 SLP S37 PCIRST PCI Reset ICH4 asserts PCIRST to reset device
240. lowing fashion PIRQ E is connected to IRQ20 PIRQ F to IRQ21 PIRQ G to IRQ22 and PIRQ H to IRQ23 This frees the legacy interrupts If not needed for interrupts these signals can be used as GPIO IRQ 14 15 I Interrupt Request 14 15 These interrupt inputs are connected to the IDE drives IRQ14 is used by the drives connected to the Primary controller and IRQ15 is used by the drives connected to the Secondary controller APICCLK I APIC Clock This clock operates up to 33 33 MHz APICD 1 0 IOD APIC Data These bi directional open drain signals are used to send and receive data over the APIC bus As inputs the data is valid on the rising edge of APICCLK As outputs new data is driven from the rising edge of the APICCLK USBP2P Universal Serial Bus Port 3 2 Differential These differential USBP2N pairs are used to transmit data address command signals for ports 2 USBP3P and 3 These ports can be routed to USB UHCI Controller 2 or the USBP3N USB EHCI Controller NOTE No external resistors are required on these signals The integrates 15 k pull downs and provides an output driver impedance of 45 which requires no external series resistor USBP4P IO Universal Serial Bus Port 5 4 Differential These differential USBPAN pairs are used to transmit data address command signals for ports 4 USBPSP and 5 These ports can be routed to USB UHCI Controller 3 or the USBP4N USB EHCI Controller NOTE No external resi
241. management registers in PCI configuration space gt Includes a programmable PCI burst size and early Tx Rx threshold Supports a 32 bit general purpose timer with the external PCI clock as clock source to generate timer interrupt Contains two large 2Kbyte independent receive and transmit FIFOs Advanced power saving mode when LAN function or wakeup function is not used Uses 93C46 64 16 bit EEPROM to store resource configuration ID parameter and VPD data Supports LED pins for various network activity indications Supports loop back capability Half Full duplex capability Supports Full Duplex Flow Control IEEE 802 3x 32 80500 N B Maintenance 1 3 13 Keyboard System Winbond W83L950D The Winbond Keyboard controller architecture consists of a Turbo 51 core controller surrounded by various registers nine general purpose I O port 2k 256 bytes of RAM four timer counters dual serial ports 40K MTP ROM that is divided into four banks two SMBus interface for master and slave Support 4 PWM channels 2 D A and 8 A D converters 2 8051 uC based Keyboard Controller Embedded Controller Supply embedded programmable flash memory internal ROM size 40KB and RAM size is 2 KB Support 4 Timer 8 bit signal with 3 prescalers Support 2 PWM channels 2 D A and 8 A D converters Reduce Firmware burden by Hardware PS 2 decoding Support 72 useful GPIOs totally Support Flash utility for on bo
242. mber Description Location S 271061100102 RES 10 1 16W 1 0402 SMT PR37 PR38 PR5 i Part Number Description Location S 271061100501 RESO 1 16W 5 0402 SMT PRI PRIOO RI000 R1001 R1009 H 271061180101 RES 18 2 1 16W 176 0402 SMT 271061183102 RESISK 16W 19 0402 271061184302 RES 180K 1 16W 5 0402 5 271061196212 RES 1 96K 1 16W 1 0402 SMT be 271061196213 RES 19 6K 1 16W 1 0402 SMT 271061201101 RES200 1 16W 1 0402 5 271061202102 RES2K 1 16W 1 0402 SMT 271061203102 RES 20K 1 16W 1 0402 SMT 271061203701 RES 20K 1 16W 1 0402 SMT 271061204102 RES200K 1 16W 1 0402 5 271061205212 RES 20 5K 1 16W 1 0402 SMT 271061220102 RES 22 1 16W 1 0402 SMT Er 271061221212 RES 2 21K 1 16W 1 0402 SMT 271061221312 RES22 1K 1 16W 1 0402 5 271061221313 RES220 1 16W 5 0402 5 271061222101 RES2 2K 1 16W 1 0402 SMT RES 2 2K 1 16W 5 0402 SMT 271061223102 RES 22K 1 16W 1 0402 5 0402 SMT 6 1940400 1500402 271061240302 RES 24 1 16W 5 0402 SMT 271061249211 RES2 49K 1 16W 1 0402 SMT 271061249212 RES24 9K 1 16W 1 0402 SMT z d ZI 271061101103 100 1 16W 1 0402 SMT R1092 R1117 R1202 R208 R257 R 271061102211 RES 1 02K 1 16W 1 0402 SMT R110 R120 271061102105 RESIK 1 16 1 0402 SMT PR121 PR53 R1006 R14 1 R32 R3 271061102312 RES 10 2K 1 16W 1 0402 SMT R496 R502 2
243. mbly 1 Carefully align the arrowhead corner of the CPU with the beveled corner of the socket then insert CPU pins into the holes Tighten the screw by a flat screwdriver to locking the CPU 2 Connect the fan s power cord to the system board fit the heatsink upon the CPU and secure with three spring screws 3 Replace the CPU cover and secure with three screws 4 Replace the battery pack Refer to section 2 2 1 reassembly 50 80500 N B Maintenance 2 2 4 HDD Module Disassembly 1 Carefully put the notebook upside down Remove the battery pack Refer to section 2 2 1 Disassembly 2 Remove two screws fastening the HDD compartment cover Figure 2 7 3 Remove the one screw and slide the HDD module out of the compartment Figure 2 8 Figure 2 7 Remove the HDD compartment cover Figure 2 8 Remove HDD module 51 80500 N B Maintenance 4 Remove four screws to separate the hard disk drive from the bracket remove four screws Figure 2 9 Figure 2 9 Remove hard disk drive Reassembly 1 Attach the bracket to hard disk drive and secure with four screws 2 Slide the HDD module into the compartment and secure with one screw 3 Place the HDD compartment cover and secure with two screws 4 Replace the battery pack Refer to section 2 2 1 reassembly 52 80500 N B Maintenance 2 2 5 CD DVD ROM Drive Disassembly 1 Carefully put the notebook upside down Remove the battery pack Refer to section 2 2 1
244. n 4403 9 e 9 1703 120Z 100M 8 1707 1202 100 ua Las a a 1 1 T T T T 1 SOURCES DRAINS T T 1 2012 2012 1202 100 SOURCE2 DRAIN rm 1 1 1704 12020100 T 1 1706 12027100 2012 1 2012 T L 3j 147 1 cos 10 100 220 iu 010 6715 220 10 C284 220 0402 4 0402 0805 0603 0402 4 0402 0603 0402 SI4788CYINA 1202 100 0603 ej 38020 R15 e 480 20 2 Riza 107 10 80 20 R705 e 80 20 100 4 10 e 80 20 508 2012 100 10 10V 1 50V 30V 1 50v R1249 6 3V tov 6 3V 0805 0605 A 57 0805 GND 3l GND 0805 40 GND 508 GND 10 100K 100K GND GND GND 0402 R21 0402 R707 a 5 1K 5 1K 0402 0402 5 0721 5 of FS au 51230105 dn DVMAIN H 4 1 s caia 4 9 SI23010S NA DVMAIN if E 4 1 4 gis s 005 er 0 0470 0603 DTA144WKINA 1 GND p 4 2 5670 1 c16 D j kea 25 8 003 GND x 1 ka 0402 220K 480 20 042 57 T 50V 5 GND R260 4 gi 1 GND 5 PWRON SUSB ky o 3 5 P aNz002 4 PWRON_SUSB GND PWRON_SUSB 80500 MOTHER B D 316680900001 ASSY 411682700001 Rot lumber Date Wednesday December 31 2003 Bheet 25 o 34 1 PDF created with FinePrint pdfFactory trial version http www fineprint com
245. nal may be used as a GPO NOTE This signal will be asserted in S1 M on the ICH4 M SUSCLK Suspend Clock Output of the RTC generator circuit to use by other chips for refresh clock AGPBUSY AGP Bus Busy To support the C3 state This signal is an indication that the AGP device is busy When this signal is asserted the BM_STS bit will be set If this functionality is not needed this signal may be configured as a GPI STP_PCI Stop PCI Clock This signal is an output to the external clock generator for it to turn off the PCI clock Used to support PCI CLKRUN protocol If this functionality is not needed This signal can be configured as a GPO STP_CPU Stop CPU Clock Output to the external clock generator for it to turn off the processor clock Used to support the C3 state If this functionality is not needed this signal can be configured as a GPO BATLOW Battery Low This signal is an input from the battery to indicate that there is insufficient power to boot the system Assertion will prevent wake from 51 55 state Can also be enabled to cause an SMI when asserted CPUPERF OD CPU Performance CPUPERF is used for Intel SpeedStep technology support The signal selects which power state to put the processor in SSMUXSEL SpeedStep Mux Select SSMUXSEL is used for Intel SpeedStep technology support The signal selects the voltage level for the processor VGATE VRMPWRGD
246. not light up PD704 BAV7OLTI Di PWR VDDIN 20704 4 04407 ERED D 100K PF702 PL705 s 13 VDD3S 7A 24VDC 1202 100 T V 2 DVMAIN 1 YY gt PL704 120Z 100M PR716 i PRO 499K pc722 L APRES RP45 PR45 p32 J703 PR714 22 4 33K 2 1006 8 78 5 gt 6 5 V P22 5 lt gt 7 77 2 S S PQS 2 016 14 ADEN gt 2N7002 t 3 2 S WINBOND 1 KBC s PR23 0 BAT C 6 2 PR24 0 BAT D 5 3 PD2 99 gt VDD3 PD3 ki 99 D 103 80500 N B Maintenance 8 2 Battery Can not Be Charged There are problems in charging the battery Battery can not Charge Board level Troubleshooting notebook connected to power AC adaptor No Connect AC adaptor Check following parts and signals Motherboard PESUS ADINP CHANGING PL710 PATI PD713 BAT_V PD714 BAT T PD709 PQ13 D PQ 14 BATT_DEAD I CTRL 1 Make sure that the battery is good 2 Make sure that the battery is installed properly PU7 PQ15 PD5 PR65 Yes Please replace the faulty Battery 104 80500 N B Maintenance 8 2 Battery Can not Be Charged There are problems in charging the battery
247. nterrupts with both Serial and FSB interrupt delivery modes is supported The integrated power management module incorporates the ACPI 1 0b compliance functions the APM 1 2 compliance functions and the PCI bus power management interface spec v1 1 Numerous power up events and power down events are also supported 21 general purposed I O pins are provided to give an easy to use logic for specific application In addition the INTEL 82801 DBM ICH4 M supports Deeper Sleep power state for Intel Mobile processor A high bandwidth and mature Intel I O Hub architecture is incorporated to connect Montara and Intel 82801 DBM ICH4 M Hub interface together Intel I O Hub architecture is developed 1 3 5 VGA Control Introducing MOBILITY M10 80500 N B Maintenance The MOBILITY M10 provides one of the fastest and most advanced 2D 3D and multimedia graphics performance for notebooks Its architecture introduces the latest achievements in the graphics industry which enable the use of the progressive new features in upcoming applications but without compromising performance ATI s support of DirectX 9 features highly optimized OpenGL support and flexible memory configurations allow implementations targeted at the gaming enthusiast consumer business and workstation platforms SMARTSHADER 2 0 Advanced Shader Technology gt Provides complete hardware accelerated support for the new DirectX 9 programmable shader model
248. ntrol available through 1 3 3 Montara GME GMCH IGUI 3D Graphic DDR SDR Chipset Montara GME GMCH IGUI Host Memory Controller integrates a high performance host interface for Intel Banias processor a high performance 2D 3D Graphic Engine high performance memory controller an AGP 4Xinterface and Intel I O Hub architecture INTEL 82801DBM ICH4 M Montara GME GMCH Host Interface features the AGTL amp AGTL compliant bus driver technology with integrated on die termination to support Intel Banias processors Montara GME GMCH provides a 12 deep In 80500 N B Maintenance Order Queue to support maximum outstanding transactions up to 12 It integrated a high performance 2D 3D Graphic Engine Video Accelerator and Advanced Hardware Acceleration MPEGI MPEGII Video Decoder for the Intel Banias series based PC systems It also integrates a high performance 2 1GB s DDR266 Memory controller to sustain the bandwidth demand from the integrated GUI or external AGP master host processor as well as the multi I O masters In addition to integrated GUI Montara GME GMCH also can support external AGP slot with AGP 1X 2X 4X capability and Fast Write Transactions A high bandwidth and mature Intel I O Hub architecture is incorporated to connect Montara GME GMCH and INTEL 82801DBM ICH4 M together Intel Hub architecture is developed into three layers the Multi threaded I O Link Layer delivering 1 2GB bandwidth to connect embedded DMA Master device
249. ntrol floating point instruction if a previous floating point instruction caused an error IGNNE has no effect when the NE bit in control register 0 CRO is set is an asynchronous signal However to ensure recognition of this signal following an Input Output write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction REQ 4 0 VO REQ 4 0 Request Command must connect the appropriate pins of both processor system bus agents They are asserted by the current bus owner to define the currently active transaction type These signals are source synchronous to ADSTB O 72 80500 N B Maintenance 5 1 Intel Pentium M Banias Processor 3 Signal Name Type Description INIT INIT Initialization when asserted resets integer registers inside the processor without affecting its internal caches or floating point registers The processor then begins execution at the power on Reset vector configured during power on configuration The processor continues to handle snoop requests during INIT assertion INIT is an asynchronous signal However to ensure recognition of this signal following an Input Output Write instruction it must be valid along with the TRDY assertion of the corresponding Input Output Write bus transaction INIT must connect the appropriate pins of both processor system bus agents If INIT is sampled active on the a
250. odem 5V 10 18 17 3 220 33V 21 d 1132 4 7K 16 37 C937 010 MONO_OUT 1 1717 720 5 ACSDOUT 23 0726 ACRST 25 25 ALC555 ACSYNC vias Qm E Ee 6 R498 22 169 VYN R1120 22 ACBITCLK 30 Pid 0715 R1131 22 ACSDINI 24 C148 1000 806 1000 Phone Lan 220 MODEME 22 Pie Lan Connector JP use 4pcs of 2kV 1000P Connector 1 Ud US use 2pcs of 2kV 1000P cap aL YY S RJ11 2P HDR MA 2 8 RJ45 8P UK use 4pcs of 1000 MINISMDCO014 2 130 80500 N B Maintenance 13 Mini PCI Test Error An error message is shown after Mini PCI device is installed or the Mini PCI device does t work Mini PCI Test Error 1 Please check if the Mini PCI device is installed properly Board level Troubleshooting 2 Confirm Mini PCI device driver is installed ok Check following parts and signals Parts Signals Yes 0715 PCI AD 0 31 CLKRUN PCI REQ2 LAD 0 3 PCI FRAME LFRAME PCL IRDY LRDQO PCL TRDY WIRELESS PD PCL DEVSEL MINIPCI PME STOP SIO_48M PCL INTD R1077 PCI R1075 PCI 2 U712 09 0704 1137 R1079 R1007 Please replace Please try another known good Mini PCI device Motherboard Pl
251. onnected to power Either AC adaptor Yes Where From Power Source Problem First use AC to power it BATTERY Please replace the faulty AC adaptor or Battery Check following parts and signals Parts Signals J703 BATT PF702 PQ6 PQ704 Board level PL704 Troubleshooting PL705 101 80500 N B Maintenance 8 1 No Power 1 When the power button is pressed nothing happens no fan activity is heard and power indicator is not light up 1202100 PD702 BAVT7OLTI PJ701 PWR VDDIN TA 24VDC PL2 120Z 100M PR701 01 A 5 8 I 5 PD701 PD704 BUZZED BAV7OLTI To chapter 8 2 e F ADINP V PQ701 04407 PD703 SBMI040 i 2 gt H PUL 4 gt 3 RS 5 RS 1 PR720 100K o 76 H8 I LIMIT R428 0 LLIMIT PRI 10 6 i OUT PR703 S 100K a P22 fro lo 5 V PQ702 Re PQ704 23 LEARNING 2N7002 226K e JE 404407 D o aoe U16 PR705 PR45 33K BATT WINBOND KBC D21 RLS4148 PQ6 14 e 2N7002 PQ24 DTCI44WK 102 80500 N B Maintenance 8 1 No Power 2 When the power button is pressed nothing happens no fan activity is heard and power indicator is
252. orms a the AD 31 0 signals on the first clock edge on which AGP differential strobe pair that provides timing information for the GMCH samples FRAME active AD 15 0 and C BE 1 0 signals in 4X mode The agent that is GIRDY Vo Initiator Ready providing the data will drive this signal AGP During PIPE and SBA Operation Not used while enqueueing GSBSTB I Sideband Strobe Provides timing for 2x and 4x data on the requests via AGP SBA and PIPE but used during the data phase of AGP SBA 7 0 bus It is driven by the AGP master after the system has PIPE and SBA transactions been configured for 2x or 4x sideband address mode During FRAME Operation G_IRDY is an output when GMCH GSBSTB I Sideband Strobe Complement The differential complement to the acts as a FRAME based AGP initiator and an input when the GMCH AGP SB_STB signal It is used to provide timing 4x mode acts as a FRAME based AGP target The assertion of G IRDY indicates the current FRAME based AGP bus initiator s ability to complete the current data phase of the transaction During Fast Write Operation In Fast Write mode G IRDY indicates that the AGP compliant master is ready to provide all write data for the current transaction Once G_IRDY is asserted for a write operation the master is not allowed to insert wait states The master is never allowed to insert a wait state during the initial data transfer 32 bytes of a write transaction However it may
253. p would change level in the next cycle DINV 3 0 Assignment To Data Bus Bus Signal Data Bus Signals DINV 3 D 63 48 DINV 2 D 47 32 DINV 1 D 31 16 DINV 0 D 15 0 DPSLP I DPSLP when asserted on the platform causes the processor to transition from the Sleep state to the Deep Sleep state In order to return to the Sleep state DPSLP must be deasserted DPSLP is driven by the ICH4 M component and also connects to the MCH M component of the Intel 855PM or Intel 855GM chipset DRDY IO DRDY Data Ready is asserted by the data driver on each data transfer indicating valid data on the data bus In a multi common clock data transfer DRDY may be deasserted to insert idle clocks This signal must connect the appropriate pins of both processor system bus agents DSTBN 3 0 IO Data strobe used to latch in D 63 0 Signals Associated Strobe D 15 0 DINV 0 DSTBN 0 Z D 31 16 DINV 1 Z DSTBN 1 D 47 32 DINV 2 DSTBN 2 D 63 48 DINV 3 Z DSTBN 3 DSTBP 3 0 IO Data strobe used to latch in D 63 0 Associated Strobe Signals D 15 0 DINV O DSTBP 0 Z D 31 16 Z DINV 1 DSTBP 1 D 47 32 DINV 2 DSTBP 2 D 63 48 DINV 3 DSTBP 3 IGNNE IGNNE Ignore Numeric Error is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating point instructions If IGNNE is deasserted the processor generates an exception on a nonco
254. p Clock when asserted causes the processor to enter a low power Stop Grant state The processor issues a Stop Grant Acknowledge transaction and stops providing internal clock signals to all processor core units except the system bus and APIC units The processor continues to snoop bus transactions and service interrupts while in Stop Grant state When STPCLK is deasserted the processor restarts its internal clock to all units and resumes execution The assertion of STPCLK has no effect on the bus clock STPCLK is an asynchronous input VCCSENSE VCCSENSE is an isolated low impedance connection to processor core power VCC It can be used to sense or measure power near the silicon with little noise VID 5 0 VID 5 0 Voltage ID pins are used to support automatic selection of power supply voltages Vcc Unlike some previous generations of processors these are CMOS signals that are driven by the Intel Pentium M processor The voltage supply for these pins must be valid before the VR can supply to the processor Conversely the VR output must be disabled until the voltage supply for the VID pins becomes valid The VID pins are needed to support the processor voltage specification variations TCK I TCK Test Clock provides the clock input for the processor Test Bus also known as the Test Access Port TDI I TDI Test Data In transfers serial test data into the processor TDI provides the serial input nee
255. r DIOW is a DMA data transfer cycle This signal is used in conjunction with the PCI bus master IDE function and are not associated with any AT compatible DMA channel PDIOR Primary and Secondary Disk I O Read PIO Non Ultra PDWSTB PRDMA DMA This is the command to the IDE device that it may drive RDY data onto the PDD or SDD lines Data is latched by the ICH4 on the deassertion edge of PDIOR or SDIOR The IDE device is SDIOR selected either by the ATA register file chip selects PDCS1 or SDWSTB SRDMA SDCS1 PDCS3 or SDCS3 and the PDA or SDA lines or the RDY IDE DMA acknowledge PDDAK or SDDAK Primary and Secondary Disk Write Strobe Ultra DMA Writes to Disk This is the data write strobe for writes to disk When writing to disk ICH4 drives valid data on rising and falling edges of PDWSTB or SDWSTB Primary and Secondary Disk DMA Ready Ultra DMA Reads from Disk This is the DMA ready for reads from disk When reading from disk ICH4 deasserts PRDMARDY SRDMARDY to pause burst data transfers PDIOW Primary and Secondary Disk I O Write PIO Non Ultra PDSTOP This is the command to the IDE device that it may latch data from the PDD or SDD lines Data is latched by the IDE device SDIOW on the deassertion edge of PDIOW or SDIOW The IDE device is SDSTOP selected either by the ATA register file chip selects PDCS1 or SDCS1 PDCS3 or SDCS3 and the PDA or SDA lines or t
256. r RTC power planes are on 90 80500 N B Maintenance 5 3 Intel 82801DBM Controller Hub 4 Mobile ICH4 M 8 AC 97 Link Signals Signal Name Type Description AC_RST 97 Reset This signal is a master hardware reset to external Codec s AC_SYNC 97 Sync This signal is a 48 kHz fixed rate sample sync to the Codec s AC BIT CLK I 97 Bit Clock This signal is a 12 288 MHz serial data clock generated by the external Codec s This signal has an integrated pull down resistor AC SDOUT AC97 Serial Data Out Serial TDM data output to the Codec s NOTE AC_SDOUT is sampled at the rising edge of PWROK as a functional strap AC_SDIN 1 0 I AC97 Serial Data In 2 0 These signals are Serial TDM data inputs from the three Codecs NOTE An integrated pull down resistor on AC_BIT_CLK is enabled when either The ACLINK Shutoff bit in the AC 97 Global Control Register is set to 1 or Both Function 5 and Function 6 of Device 31 are disabled Otherwise the integrated pull down resistor is disabled General Purpose I O Signals Signal Name Type Description GPIO 43 32 Uo Can be input or output Main power well GPIO 31 29 Not implemented GPIO 28 27 VO Can be input or output Resume power well Unmuxed GPIO 26 VO Not implemented GPIO 25 Uo Can be input or output Resume power well Unmuxed GPIO 24 18 Uo Not Implemented in Mobile Assign to n
257. recognize snoops or interrupts The processor will recognize only assertion of the RESET signal deassertion of SLP and removal of the BCLK input while in Sleep state If SLP is deasserted the processor exits Sleep state and returns to Stop Grant state restarting its internal clock signals to the bus and processor core units If DPSLP is asserted while in the Sleep state the processor will exit the Sleep state and transition to the Deep Sleep state 73 80500 N B Maintenance 5 1 Intel Pentium M Banias Processor 4 Signal Name Type Description Signal Name Type Description SMI I SMI System Management Interrupt is asserted asynchronously by system logic On accepting a System Management Interrupt the processor saves the current state and enter System Management Mode SMM An SMI Acknowledge transaction is issued and the processor begins program execution from the SMM handler If SMI is asserted during the deassertion of RESET the processor will tristate its outputs VCC I Processor core power supply VCCA 3 0 VCCA provides isolated power for the internal processor core PLL s VCCP Processor I O Power Supply 0 1 1 1 Quiet power supply for on die COMP circuitry These pins should be connected to VCCP on the motherboard However these connections should enable addition of decoupling on the VCCQ lines if necessary STPCLK I STPCLK Sto
258. response 010 Deferred response 011 Reserved not driven by GMCH 100 Hard Failure not driven by GMCH 101 No data response 110 Implicit Write back 111 Normal data response 76 80500 N B Maintenance 5 2 Intel 855GM GME North Bridge 3 DDR SDRAM Interface Descriptions Continued AGP Addressing Signal Descriptions Signal Name Type Description GPIPE I AGP Pipelined Read This signal is asserted by the AGP master to indicate a full width address is to be enqueued on by the target using the AD bus One address is placed in the AGP request queue on each rising clock edge while PIPE is asserted When PIPE is deasserted no new requests are queued across the AD bus During SBA Operation This signal is not used if SBA Side Band Addressing is selected During FRAME Operation This signal is not used during AGP FRAME operation is a sustained tri state signal from masters graphics controller and is an input to the GMCH GSBA 7 0 AGP Side band Address These signals are used by the AGP master graphics controller to pass address and command to the GMCH The SBA bus and AD bus operate independently That is transactions can proceed on the SBA bus and the AD bus simultaneously During PIPE Operation These signals are not used during PIPE operation During FRAME Operation These signals are not used during AGP operation NOTE When sideband
259. rogrammable Interrupt Controller legacy system I O and legacy power management functionalities are integrated as well The integrated Universal Serial Bus Host Controllers features Dual Independent UHCI Compliant Host controllers with six USB ports delivering 480 Mb s bandwidth and rich connectivity Besides Legacy USB devices as well as over current detection are also implemented The Integrated AC97 v2 3 compliance Audio Controller that features a 7 channels of audio speaker out and HSP v 90 modem support Additionally the AC97 interface supports 4 separate SDATAIN pins that is capable of supporting multiple audio codecs with one separate modem codec 80500 N B Maintenance The integrated IDE Master Slave controllers features Dual Independent IDE channels supporting PIO mode transfers up to 16 Mbytes sec and Ultra DMA 33 66 100 It provides two separate data paths for the dual IDE channels that sustain the high data transfer rate in the multitasking environment INTEL 82801DBM ICHA M supports 6 PCI masters and complies with PCI 2 2 specification It also incorporates the legacy system I O like two 82C37 compatible DMA controllers Channels 0 3 are hardwired to 8 bit three 8254 compatible programmable 16 bit counters channels 5 7 hardwired keyboard controller and PS2 mouse interface not use in 8050 model Real Time clock with 512Bytes CMOS SRAM and two 82C59 compatible Interrupt controllers Besides the I O APIC managing up to 14 i
260. s and external PCI masters to interface to Multi threaded I O Link layer the Multi threaded I O Link Encoder Decoder in INTEL 82801DBM ICH4 M to transfer data w 533 MB s bandwidth from to Multi threaded I O Link layer to from Montara GME GMCH and the Multi threaded Link Encoder Decoder Montara GME GMCH to transfer data w 533 MB s from to Multi threaded I O Link layer to from INTEL 82801DBM ICH4 M An Unified Memory Controller supporting DDR266 DRAM is incorporated delivering a high performance data transfer to from memory subsystem from to the Host processor the integrated graphic engine or external AGP master or the I O bus masters The memory controller also supports the Suspend to RAM function by retaining the CKE pins asserted in ACPI S3 state in which only AUX source deliver power The Montara GME GMCH adopts the Shared Memory Architecture eliminating the need and thus the cost of the frame buffer memory by organizing the frame buffer in the system memory The frame buffer size can be allocated from 8MB to 64MB 80500 N B Maintenance Features 1 Processor Host Bus Support Intel Banias processor 2X Address 4X data Support host bus Dynamic Bus Inversion DBI Supports system bus at 400 100 MHz Supports 64 bit host bus addressing 8 deep In Order Queue AGTL bus driver technology with integrated GTL termination resistors and low voltage operation 1 05V Supports Enhanced Intel Speed Step TM Technology EI
261. s that reside on the PCI bus The ICH4 asserts PCIRST during power up and when S W initiates a hard reset sequence through the RC CF9h register The ICH4 drives PCIRST inactive a minimum of 1 ms after PWROK is driven active The ICH4 drives PCIRST active a minimum of 1 ms when initiated through the RC register PLOCK PCI Lock This signal indicates an exclusive bus operation and may require multiple transactions to complete ICH4 asserts PLOCK when it performs non exclusive transactions on the PCI bus Devices on the PCI bus other than the ICH4 are not permitted to assert the PLOCK signal SERR VOD System Error SERR can be pulsed active by any PCI device that detects a system error condition Upon sampling SERR active the ICH4 has the ability to generate an NMI or interrupt 85 80500 N B Maintenance 5 3 Intel 82801DBM Controller Hub 4 Mobile ICH4 M 3 PCI Interface Signals Continued Signal Name Type Description PME VOD PCI Power Management Event PCI peripherals drive PME to wake the system from low power states 51 55 PME assertion can also be enabled to generate an SCI from the SO state In some cases the ICH4 may drive PME active due to an internal wake event The ICH4 will not drive PME high but it will be pulled up to VecSus3_3 by an internal pull up resistor CLKRUN Io PCI Clock Run Used to support PCI Clock Run protocol Conne
262. sa 13 VDDQ 13 vssa 13 VDDQ 13 vssa 13 VDDQ 13 vssa 13 VDDQ 13 vssQ 14 VDDQ 14 vssQ 14 VDDQ 14 550 14 VDDQ 14 550 14 VDDQ 14 550 15 VDDQ 15 vssa 15 VDDQ 15 vssa 15 VDDQ 15 vssa 15 VDDQ 15 vssa 16 vssa 16 vssa 16 vssa 16 550 17 550 17 550 17 550 17 vssa 18 vssa 18 vssa 18 vssa 18 vssa 19 vssa 19 vssa 19 vssa 19 HYSDUB32222F HYSDUB32222F HYSDUB32222F HYSDUB32222F 7 BGA144F_08MM_1 BGA144F_08MM_1 BGA144F_08MM_1 BGA144F_08MM_1 GND GND GND 425V MIO 425V 10 425V 10 5 gt 55 tmm 5 7 C724 1 c723 L c720 l 727 c32 C28 c36 C33 100 TU 0010 100 10 0010 100 iu OU 0010 100 10 0010 0805 0402 0402 0402 0805 0402 0402 0402 0805 0402 0402 0402 0805 0402 0402 0402 63V 480 208 10 480 20 63V 480 200 10 480 2095 63V 480 208 10 480 2094 63V 480 208 10 480 2094 a 50V a 50 50V T 50 GND GND GND GND VDD MEM IO VDD MEM IO VDD MEM IO VDD MEM 10 9 9 9 9 55 gt gt C754 52 l c749 cag cst L cres cree C30 cas c29 C34 100 iu 0 10 0010 100 10 0010 100 10 010 0 10 6 010 100 10 0010 0805 0402 0402 0402 0402 0805 0402 0402 0402 0402 0805 0402 0402 0402 0402 0805 0402 0402 0402 0402 6 380 208 10 10 80 20 63V 280 204 10 10 80 20 6
263. sday December 31 2003 Bheet 27 5 I T PDF created with FinePrint pdfFactory trial version http www fineprint com 1 5V_P 1 05V_P DVMAIN 1810 1 1 7 17 72 T SHORT SMT4 1202 100 IL 0402 10 507 GND 1 PJLS 100 x ees 120 JP E 20 X5R PC32 74 10 0010 100 100 sov 7 0402 1210 1210 Ww GND 10 25 25 GND 50V 20 X5R 20 58 PR708 PR708 4 4 88100056017 1 H 47 47 sz GND 0603 07050608 GND 1 EC OT23N PR713 PC716 5 3 Lag E TA 0402 Ti T3 100 JP BV AO4900 B 4 1206 4 0 4 4 L 715 04 26714 PC30 4 8020 940 0805 50 0805 D 0402 ej 10 10 9 PU703 4 10 GND 44 4 44414 11037281 HVQFN32 1 4 55898285 SV P PR719 PL706 s d 4 294900 1 s PL707 PR732 s I000 1 sii uci LS Em 6 swe 18 T 1 A 1 T O 1 05V_P 2010
264. stors are required on these signals The ICH4 integrates 15 k pull downs and provides an output driver impedance of 45 which requires no external series resistor 5 0 VO Overcurrent Indicators These signals set corresponding bits in the USB controllers to indicate that an overcurrent condition has occurred USBRBIAS USB Resistor Bias Analog connection point for an external resistor to ground USBRBIAS should be connected to USBRBIAS as close to the resistor as possible USBRBIAS I USB Resistor Bias Complement Analog connection point for an external resistor to ground USBRBIAS should be connected to USBRBIAS as close to the resistor as possible 87 80500 N B Maintenance 5 3 Intel 82801DBM Controller Hub 4 Mobile ICH4 M 5 Power Management Interface Signals Continued Power Management Interface Signals Signal Name Description THRM Thermal Alarm This is an active low signal generated by external hardware to start the hardware clock throttling mode The signal can also generate an SMI or an SCI THRMTRIP Thermal Trip When low THRMTRIP indicates that a thermal trip from the processor occurred the ICH4 will immediately transition to a S5 state The ICH4 will not wait for the processor stop grant cycle since the processor has overheated SLP_S1 S1 Sleep Control SLP_S1 provides Clock Synthesizer or Power plane control Optional use is to shut off power to non criti
265. t a caching agent holds an unmodified version of the AGTL requested line Also driven in conjunction with HITM by the target to extend the snoop window HITM T O Hit Modified Indicates that a caching agent holds a modified version AGTL ofthe requested line and that this agent assumes responsibility for providing the line Also driven in conjunction with HIT to extend the snoop window HLOCK T O Host Lock All CPU bus cycles sampled with the assertion of AGTL HLOCK and ADS until the negation of HLOCK must be atomic i e no Hub interface snoopable access to system memory is allowed when is asserted by the CPU HREQ 4 0 Lo Host Request Command Defines the attributes of the request AGTL HREQ 4 0 are transferred at 2x rate Asserted by the requesting agent during both halves of the Request Phase In the first half the signals define the transaction type to a level of detail that is sufficient to begin a snoop request In the second half the signals carry additional information to define the complete transaction type The transactions supported by the GMCH Host Bridge are defined in the Host Interface section of this document HTRDY Host Target Ready Indicates that the target of the processor AGTL _ transaction is able to enter the data transfer phase RS 2 0 Response Status Indicates the type of response according to the AGTL following the table RS 2 0 Response type 000 Idle state 001 Retry
266. t pdfFactory trial version http www fineprint com VMAIN DISCHARGE m PD702 PD704 Lb BAV70LT1 BAV7OLT 288100070006 288100070006 1202 100 2012 30701 1 m pa 20701 DVMAIN 404407 ADINP 33 PJ701 OPEN SMT4 20 5107 200 PFI 7A AVDC m 1 EAR iig p ____ PL2 PR701 5 1040 pose poss l Pcas poz 1 1 pose 4 1202 100 4 01 PCB18 PCB19 20 21 PR706 0010 0 01U 1000P 1000P 1000P 0010 0010 H JAck2P 1 2012 PC701 PC702 2512 0010 0010 1000P 1000P PR704 gt 4 7K 0402 0402 0402 0402 0402 0402 0402 331910002006 0 01U 10 0010 0402 0402 0402 0402 4 7K 0805 80 20 4 80 20 5 20 20 20 10 80 20 0402 0805 0402 8 2440 80 20 80 20 20 20 0805 PR720 50V 1 50V 50V J 50V 50V J 50V 50V 10 ej 25V 44 10 50V 50V 50V 50V T 50 50V Ae 1 100K ve ck 4 4 4 4 pos E 494407 J01 Jo2 100K 5 5 0402 226K SPARKGAP 6 SPARKGAP 6 GND 0402 4 1 EMS GND PR45 35 LEABNINS LEARNING 0701 E OPEN SMT 5
267. tal Synchronization This signal is used as the CMOS horizontal sync signal RED Red Analog Video Output This signal is CRT Analog video Analog from the internal color palette DAC The DAC is designed for a 37 5 U equivalent load on each pin e g 75 8U resistor on the board in parallel with the 75 8U CRT load Name Type Description DVOCD 11 0 DVOC Data This data bus is used to drive 12 bit RGB data each DVO _ edge of the differential clock signals DVOCCLK and DVOCCLK This provides 24 bits of data per clock period In dual channel mode this provides the upper 12 bits of pixel data DVOCD 11 0 should be left as left as NC Not Connected if not used DVOCHSYNC Horizontal Sync HSYNC signal for the DVOC interface DVO DVOCHSYNC should be left as left as NC Not Connected if not used DVOCVSYNC Vertical Sync VSYNC signal for interface DVO DVOCVSYNC should be left as left as NC Connected if the signal is NOT used when using internal graphics device DVOCBLANK Flicker Blank or Border Period Indication is a DVO programmable output pin driven by the GMCH When programmed as a blank period indication this pin indicates active pixels excluding the border When programmed as a border period indication this pin indicates active pixel including the border pixels DVOCBLANK should be left as left as NC Not Connected if not used
268. th Bridge 1 Host Interface Signal Descriptions Host Interface Signal Descriptions Continued Signal Name Type Description ADS vo Address Strobe The system bus owner asserts ADS to indicate the AGTL first of two cycles of a request phase The GMCH can assert this signal for snoop cycles and interrupt messages BNR TO Block Next Request Used to block the current request bus owner AGTL from issuing a new request This signal is used to dynamically control the CPU bus pipeline depth BPRI Bus Priority Request is the only Priority Agent on the AGTL system bus It asserts this signal to obtain the ownership of the address bus This signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the HLOCK signal was asserted Bus Request 0 The GMCH pulls the processor bus BREQO signal low during CPURST The signal is sampled by the processor on the active to inactive transition of CPURST The minimum setup time for this signal is 4 BCLKs The minimum hold time is 2 clocks and the maximum hold time is 20 BCLKs BREQO should be tristated after the hold time requirement has been satisfied During regular operation the GMCH will use BREQO as an early indication for FSB Address and Ctl input buffer and sense amp activation CPU Reset The CPURST pin is an output from the GMCH The GMCH asserts CPURST whi
269. th two screws and rubber pads 6 Replace the LCD assembly CD DVD ROM drive hard disk drive keyboard battery pack See sections 2 2 9 2 2 5 2 2 4 2 2 2 and 2 2 1 reassembly 62 80500 N B Maintenance 2 2 11 Inverter Board Disassembly 1 Remove the battery keyboard hard disk drive CD DVD ROM drive and LCD assembly Refer to section 2 2 1 2 2 2 2 2 4 2 2 5 and 2 2 9 Disassembly 2 Remove the LCD cover and LCD panel Refer to the steps 1 4 of section 2 2 10 Disassembly 3 Remove the one screw fastening the inverter board and disconnect the cable Then free the inverter board Figure 2 29 Figure 2 29 Free the inverter board Reassembly 1 Reconnect the cable Fit the inverter board back into place and secure with one screw 2 Replace the LCD Panel and LCD cover Refer to section 2 2 10 reassembly 3 Replace the LCD assembly Refer to section 2 2 9 reassembly 4 Replace the CD DVD ROM drive hard disk drive keyboard and battery pack Refer to sections 2 2 5 2 2 4 2 2 2 and 2 2 1 reassembly 63 80500 N B Maintenance 2 2 12 System Board Disassembly 1 Remove the battery keyboard hard disk drive CD DVD ROM drive Wireless card and LCD assembly Refer to sections 2 2 1 2 2 2 2 2 4 2 2 5 2 2 6 and 2 2 9 Disassembly 2 Remove the four screws that secure the system board and disconnect the two speaker s cables Then lift it up from the housing Figure 2 30 3 Disconnect the one speaker
270. umeric Error This signal is connected to the ignore error pin on the processor IGNNE is only used if the ICH4 coprocessor error reporting function is enabled in the General Control Register Device 31 Function 0 Offset DO bit 13 If FERR is active indicating a coprocessor error a write to the Coprocessor Error Register causes the IGNNE to be asserted IGNNE remains asserted until FERR is negated If FERR is not asserted when the Coprocessor Error Register is written the IGNNE signal is not asserted Speed Strap During the reset sequence ICH4 drives IGNNE high if the corresponding bit is set in the FREQ STRP register INIT Initialization INIT is asserted by the ICH4 for 16 PCI clocks to reset the processor ICH4 can be configured to support CPU BIST In that case INIT will be active when PCIRST is active NMI Non Maskable Interrupt NMI is used to force a non Maskable interrupt to the processor The ICH4 can generate an NMI when either SERR or IOCHK is asserted The processor detects an NMI when it detects a rising edge on NMI NMI is reset by setting the corresponding NMI source enable disable bit in the NMI Status and Control Register Speed Strap During the reset sequence ICH4 drives NMI high if the corresponding bit is set in the FREQ STRP register SMI System Management Interrupt is an active low output synchronous to PCICLK It is asserted by the ICH4 in response to one
271. vice Select for 300 Range For ATA control register block This output signal is connected to the corresponding signal on the primary or secondary IDE connector PDA 2 0 Primary and Secondary IDE Device Address These output SDA 2 0 signals are connected to the corresponding signals on the primary or secondary IDE connectors They are used to indicate which byte in either the ATA command block or control block is being addressed IDE Interface Signals Continued Signal Name Type Description PDD 15 0 Io Primary and Secondary IDE Device Data These signals directly SDD 15 0 drive the corresponding signals on the primary or secondary IDE connector There is a weak internal pull down resistor on PDD 7 and SDD 7 PDDREQ 1 Primary Secondary IDE Device DMA Request These input SDDREQ signals are directly driven from the DRQ signals on the primary or secondary IDE connector It is asserted by the IDE device to request a data transfer and used in conjunction with the PCI bus master IDE function and are not associated with any AT compatible DMA channel There is a weak internal pull down resistor on these signals PDDACK Primary Secondary IDE Device DMA Acknowledge These SDDACK signals directly drive the DAK signals on the primary and secondary IDE connectors Each is asserted by the ICH4 to indicate to IDE DMA slave devices that a given data transfer cycle assertion of DIOR o
272. vice is installed 1 Check if the driver is installed properly 2 Check if the notebook connect with the LAN properly Board level Check following parts and signals Troubleshooting Parts Signals U719 EECK AVDDL U717 EEDI DVDD U723 EEDO SB PMEZ J709 EECS PCLKRUN L732 PJRX PCI DEVSEL L735 PJRX PCI FRAME L737 PJTX1 PCI INTE 151 PJTX PCI REQ3 L49 LAN XTANLI PCI IRDY Q709 LAN XTANI2 PCI SERR X706 PCICLK LAN R1101 LAN WAKE R1111 PCI AD 0 31 R1115 PCI C BR 0 3 R907 PCL PAR R211 LAN _PCIRST R212 PCL STOP Correct it No Check if BIOS setup is ok Replace Motherboard Re test Correct it 127 80500 N B Maintenance 8 11 LAN Test Error An error occurs when a LAN device is installed as zu 1737 1207 100 3 7 16 20 2 5VS_DDR L732 DVDD 24 32 45 54 64 78 99 110 116 126 1207 100 1735 1202 100 12 003 3VS R907 211 8212 8241 10K 8 2K 11 SB_PME 31 PCLKRUN PCI_GNT3 _PCLDEVSEL PCI_INTE 65 68 61 29 25 PCI_TRDY PCI_PERR e PCI IRDY4 PCI SERR PCI STOP 63 67 70 75 69 4 PCI_REQ3 30 PCI_C BE 0 3 1_ 0 31 76 44 60 33 34 U715 LAN_PCIRST ICH4 M 1115 PCI ADI8 _ R947 100 10K Q709 R1111 0 DTCI44TKA b LAN WAKE 105 1 13 PCICLK_LAN 28
273. xts 4 isochronous receive context 3 deep physical post write queue 2 deep physical response queue Dual buffer mode enhancements Skip Processing enhancements Block Read Request handling Ack_tardy processing 26 80500 N B Maintenance 1 3 10 System Flash Memory BIOS Firmware Hub for Intel 810 810E 815 815E 815EP 820 840 850 Chipsets Flexible Erase Capability Uniform 4 K Byte Sectors Uniform 16 Byte overlay blocks for SSTA9LF002A Uniform 64 Byte overlay blocks for SST49LFO04ATop boot block protection 16 Byte for SSTA9LF002A 64 Byte for SSTA9LF004A Chip Erase for PP Mode Single 3 0 3 6V Read and Write Operations Superior Reliability Firmware Hub Hardware Interface Mode gt 5 signal communication interface supporting byte Read and Write gt 33 MHz clock frequency operation gt WP and TBL pins provide hardware write protect for entire chip and or top Boot Block 27 80500 N B Maintenance Block Locking Register for all blocks Standard SDP Command Set Data Polling and Toggle Bit for End of Write detection 5 GPI pins for system design flexibility 4 ID pins for multi chip selection 1 3 11 Memory System 1 3 11 1 64MB 128 256MB 512MB x64 200 Pin DDR SDRAM SODIMM WV JEDEC standard 200 pin small outline dual in line memory module SODIMM Utilizes 200 Mb s and 266 Mb s DDR SDRAM components
274. y life at less 220mAh 5 8uA 4 years 1 4 8 Port One Power Supply Jack One External CRT Connector For CRT Display Supports three USB port for all USB devices One MODEM RJ 11 phone jack for PSTN line One RJ 45 for LAN WV One 1394 port 39 80500 N B Maintenance gt Headphone Out Jack gt Microphone Input Jack gt Line in Jack 1 4 9 Battery current limit and learning Implanted H W current limit and battery learning circuit to enhance protection of battery 1 5 Power management The 8050D system has built in several power saving modes to prolong the battery usage for mobile purpose User can enable and configure different degrees of power management modes via ROM CMOS setup booting by pressing F2 key Following are the descriptions of the power management modes supported 1 5 1 System Management Mode Full on mode In this mode each device is running with the maximal speed CPU clock is up to its maximum 40 80500 N B Maintenance Doze Mode In this mode CPU will be toggling between on amp stop grant mode either The technology 15 clock throttling This can save battery power without loosing much computing capability The CPU power consumption and temperature is lower in this mode Standby mode For more power saving it turns of the peripheral components In this mode the following is the status of each device CPU Stop grant LCD backlight off
275. y trial version http www fineprint com Pwr vonin VDD3_AVREF PS tus 8J N 5 51230105 51230108 35 OUT T vDD1 5 p ie Se 6 7 T SHUTDN GND 14 1206 J Ji 4 PWR_VDDIN 5 1 2951 3 3 C383 C381 Uii R374 508 100 025 E 8 evap Li 10K NA 0805 0402 RLZ3GBNA D26 C517 2 0402 62 80 20 MLLS4B 7 XUDZS3 6BINA 470 SENSE OUT vour 5 10 50 500323 0805 ee Ene La 0402 1 80 20 SHUTDN GND 10 GND ADJ aN 9 S Lot Ed 1117 T s 508 ZN 100 1 GND GND GND GND GND 10K 2558 osos NU 507223 10 GND 0402 4 63V GND GND 5 10 1K NA pH meur _ 3 22 sw 87 003 R523 1 m m DTC144WK C 288202237002 GND GNDGND GND R253 5 200 355 AMS3107 8522 1 0402 0402 100 131
276. ystem board using precision 196 tolerance resistors Refer to the platform design guides for more implementation details D 63 0 T O D 63 0 Data are the data signals These signals provide a 64 bit data path between the processor system bus agents and must connect the appropriate pins on both agents The data driver asserts DRDY to indicate a valid data transfer D 63 0 are quad pumped signals and will thus be driven four times in a common clock period D 63 0 are latched off the falling edge of both DSTBP 3 0 and DSTBN 3 0 Each group of 16 data signals correspond to a pair of one DSTBP and one DSTBN The following table shows the grouping of data signals to data strobes and DINV Quad Pumped Signal Groups Data Group DSTBN DSTBP DINV D 15 0 0 0 D 31 16 1 1 D 47 32 2 2 D 63 48 3 3 Furthermore the DINV pins determine the polarity of the data signals Each group of 16 data signals corresponds to one DINV signal When the DINV signal is active the corresponding data group is inverted and therefore sampled active high DBR DBR Data Bus Reset is used only in processor systems where debug port is implemented on the system board DBR is used by a debug port interposer so that an in target probe can drive system reset If a debug port is implemented in the system DBR is a no connect is not a processor signal 71 80500 N B Maintenance 5 1

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