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LSI 53C810A User's Manual

1. Read Write 31 0 DSPS xX X xX X X X X X xX xXx x x x x x _ x xy x xy x xyx x xX DSPS DMA SCRIPTS Pointer Save 31 0 This register contains the second Dword of a SCRIPTS instruction It is overwritten each time a SCRIPTS instruction is fetched When a SCRIPTS interrupt instruction is executed this register holds the interrupt vector The power up value of this register is indeterminate 5 40 Operating Registers Registers 0x34 0x37 0xB4 0xB7 Scratch Register A SCRATCHA Read Write 31 0 SCRATCHA X xX X X xX X X X X xX xX xX x x x x x x x x x x x x x SCRATCHA Scratch Register A 31 0 This is a general purpose user definable scratch pad register Apart from CPU access only Register Read Write and Memory Moves into the SCRATCH register alter its contents The power up value of this register is indeterminate The LSI53C810A cannot fetch SCRIPTS instructions from this location Register 0x38 0xB8 DMA Mode DMODE Read Write 7 5 4 3 2 1 0 BL 1 0 SIOM DIOM ER ERMP BOF MAN 0 0 0 0 0 0 0 BL 1 0 Burst Length 7 6 These bits control the maximum number of transfers performed per bus ownership regardless of whether the transfers are back to back burst or a combination of both The LSI53
2. CLK LOW time SCLK LOW time CLK HIGH time SCLK HIGH time CLK slew rate SCLK slew rate 1 This parameter must be met to ensure SCSI timings are within specification 2 Duty cycle not to exceed 60 40 Figure 7 6 Clock Timing CLK SCLK 7 10 Electrical Characteristics Table 7 14 and Figure 7 7 provide reset input timing data Table 7 14 Reset Input Timing snd women Reset pulse width Reset deasserted setup to CLK HIGH Figure 7 7 Reset Input MAD X Valid Data X Data 1 When enabled Table 7 15 and Figure 7 8 provide interrupt output timing data Table 7 15 Interrupt Output Parameter CLK HIGH to IRQ LOW CLK HIGH to IRQ HIGH IRQ deassertion time Figure 7 8 Interrupt Output Waveforms t t t ele a ae IRQ CLK AC Characteristics 7 11 7 4 PCI Interface Timing Diagrams 7 12 Figure 7 9 through Figure 7 18 represent signal activity when the LSI53C810A accesses the PCI bus The timings for the PCI bus interface are listed on page 7 26 The following timing diagrams are included in this section Target Timing PCI Configuration Register Read PCI Configuration Register Write Target Read Target Write Initiator Timing OpCode Fetch Nonburst Burst Opcode Fetch Back to Back Read Back to Back Write Burst Read Burst Write Electrical Characteristics 7 4 1 Target Timing Figure 7 9 through Figure 7 12 des
3. Output low current 3 state leakage Table 7 10 Bidirectional Signals AD 31 0 C_BE 3 0 FRAME IRDY TRDY DEVSEL STOP PERR PAR Parameter i Test Conditions Vin Input high voltage 2 0 Vpp 0 5 V Vit Input low voltage Vss 0 5 0 8 V Vou Output high voltage 2 4 Vop V 16 mA VoL Output low voltage Vss 0 4 V 16 mA loH Output high current 8 mA Vpp 0 5 Note All the signals in this table have 100 uA pull ups that are enabled when TESTIN is low DC Characteristics 7 5 Table 7 11 Bidirectional Signals GPIOO_FETCH GPIO1_MASTER Parameter Test Conditions Vin Input high voltage 2 0 Vpp 0 5 V Vit Input low voltage Vss 0 5 0 8 V aa Vou Output high voltage 2 4 Vpp V 16 mA VoL Output low voltage Vss 0 4 V 16 mA loH Output high current 8 mA 2 4 V loL Output low current 16 mA 0 4 V lin Input leakage 10 10 uA loz 3 state leakage 10 10 uA Note All the signals in this table have 100 uA pull ups that are enabled when TESTIN is low 7 2 TolerANT Technology 7 6 The LSI53C810A features TolerANT technology which includes active negation on the SCSI drivers and input signal filtering on the SCSI receivers Active negation actively drives the SCSI Request Acknowledge Data and Parity signals HIGH rather than allowing them to be passively pulled up by terminators Table 7 12 provides electrical c
4. SCSI SDP Parity Signal 0 This bit represents the active high current status of the SCSI SDP parity signal 5 23 Register 0x0E 0Ox8E SCSI Status One SSTAT1 Read Only 7 4 3 2 1 0 FF 3 0 SDPL MSG C D 1O 0 0 0 0 x x x xX FF 3 0 FIFO Flags 7 4 These four bits define the number of bytes that currently reside in the LSI53C810A s SCSI synchronous data FIFO These bits are not latched and they will change as data moves through the FIFO The FIFO can hold up to 9 bytes Values over nine will not occur SDPL Latched SCSI Parity 3 This bit reflects the SCSI parity signal SDP corresponding to the data latched in the SCSI Input Data Latch SIDL It changes when a new byte is latched into the SCSI Input Data Latch SIDL register This bit is active high in other words it is set when the parity signal is active 5 24 Operating Registers MSG SCSI MSG Signal 2 C D SCSI C_D Signal 1 1 0 SCSI I_O Signal 0 These three SCSI phase status bits MSG C D and I O are latched on the asserting edge of SREQ when operating in either initiator or target mode These bits are set when the corresponding signal is active They are useful when operating in the low level mode Register 0x0F 0x8F SCSI Status Two SSTAT2 Read Only R Reserved 7 2 LDSC Last Disconnect 1 This bit is used in conjunction with the Connected CON bit in SCSI Control One SCNTL1 It allows the user to detect the case in which a ta
5. The LSI53C810A verifies that it is connected to the SCSI bus as an Initiator before executing this instruction The LSI53C810A waits for an unserviced phase to occur An unserviced phase is any phase with SREQ asserted for which the LSI53C810A has not yet transferred data by responding with a SACK Instruction Set of the I O Processor SCSIP 2 0 The LSI53C810A compares the SCSI phase bits in the DMA Command DCMD register with the latched SCSI phase lines stored in the SCSI Status One SSTAT1 register These phase lines are latched when SRE Q is asserted If the SCSI phase bits match the value stored in the SCSI SCSI Status One SSTAT1 register the LSI53C810A transfers the number of bytes specified in the DMA Byte Counter DBC register starting at the address pointed to by the DMA Next Address DNAD register lf the SCSI phase bits do not match the value stored in the SCSI Status One SSTAT1 register the LSI53C810A generates a phase mismatch interrupt and the instruction is not executed During a Message Out phase after the LSI53C810A has performed a select with Attention or SATN is manually asserted with a Set ATN instruction the LSI53C810A deasserts SATN during the final SREQ SACK handshake of the first move of Message Out bytes after SATN was set When the LSI53C810A is performing a block move for Message In phase it does not deassert the SACK signal for the last SREQ SACK hand
6. General Description 1 2 LSI53C810A Benefits Summary This section provides an overview of the LSI53C810A features and benefits It contains these topics SCSI Performance PCI Performance Integration Ease of Use Flexibility Reliability Testability 1 2 1 SCSI Performance To improve SCSI performance the LSI53C810A Complies with PCI 2 1 specification Supports variable block size and scatter gather data transfers Minimizes SCSI I O start latency Performs complex bus sequences without interrupts including restore data pointers Reduces Interrupt Service Routine ISR overhead through a unique interrupt status reporting method Performs fast SCSI bus transfers in SE mode up to 7 Mbytes s asynchronous 10 Mbytes s synchronous Increases performance of data transfers to and from the chip registers with new load and store SCRIPTS instruction Supports target disconnect and later reselect with no interrupt to the system processor Supports execution of multithreaded I O algorithms in SCSI SCRIPTS with fast I O context switching LS I53C810A Benefits Summary 1 3 1 2 2 PCI Performance To improve PCI performance the LSI53C810A 1 2 3 Integration 1 2 4 Ease of Use Bursts 2 4 8 or 16 Dwords across PCI bus with 80 byte DMA FIFO Prefetches up to 8 Dwords of SCRIPTS instructions Supports 32 bit word data bursts with variable burst lengths Bursts SCRIPTS opcode fetches across the PCI bus Performs zero wait
7. The SIGP bit is used in various ways to pass a flag to or from a running SCRIPTS instruction The only SCRIPTS instruction directly affected by the SIGP bit is Wait for Selection Reselection Setting this bit causes that instruction to jump to the alternate address immediately The instructions at the alternate jump address should check the status of SIGP to determine the cause of the jump The SIGP bit may be used at any time and is not restricted to the wait for selection reselection condition Semaphore 4 The SCRIPTS processor may set this bit using a SCRIPTS register write instruction An external processor may also set it while the LSI53C810A is executing a SCRIPTS operation This bit enables the LSI53C810A to notify an external processor of a predefined condition while SCRIPTS are running The external processor may 5 27 5 28 CON INTF SIP Note also notify the LSI53C810A of a predefined condition and the SCRIPTS processor may take action while SCRIPTS are executing Connected 3 This bit is automatically set any time the LSI53C810A is connected to the SCSI bus as an initiator or as a target It is set after successfully completing selection or when the LSI53C810A responds to a bus initiated selection or reselection It is also set after the LSI53C810A wins arbitration when operating in low level mode When this bit is clear the LSI53C810A is not connected to the SCSI bus Interrupt on the Fly 2 This bit is a
8. me aS i 100LD PLASTIC QUAD FLAT PACK f e DATUM PLANE COPPER SEAING CODE UD REV PLANE DWG NO JZ01 000375 00 2 SCALE SHEET 1 of 2 Important This drawing may not be the latest version For board layout and manufacturing obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code UD 7 34 Electrical Characteristics Figure 7 24 100 LD PQFP UD Mechanical Drawing Sheet 2 of 2 DETAIL B l J N WHA ae 0 40 MIN 2 0 10 oe SEATING PLANE 0 13 R MIN DATUM H 4 PLANE 0 13 0 30 R GAGE UNE 0 25 BSC DETAIL B 1 95 REF NOTES 1 ALL DIMENSIONS AND TOLERANCES CONFORM TO ANSI Y14 5M 1982 ZX DATUM PLANE H IS LOCATED AT THE MOLD PARTING LINE AND IS COINCIDENT WITH THE BOTTOM OF THE LEADS WHERE THE LEAD EXITS THE PLASTIC BODY A DATUMS A B AND D TO BE DETERMINED AT DATUM PLANE H AT BE DETERMINED AT SEATING PLANE C N A DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION ALLOWABLE PROTRUSION IS 25mm 010 PER SIDE DIMENSIONS F E 2 D1 AND E1 DO NOT INCLUDE MOLD MISMATCH AND ARE DETERMINED 4 AT DATUM PLANE H TE A DETAILS_OF PIN 1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCAT
9. 2 The LSI53C810A asserts the SCSI phase signals SMSG SC_D and SI_O as defined by the Phase Field bits in the instruction 3 If the instruction is for the command phase the LSI53C810A receives the first command byte and decodes its SCSI Group Code If the SCSI Group Code is either Group 0 Group 1 Group 2 or Group 5 then the LSI53C810A overwrites the DMA Byte Counter DBC register with the length of the Command Descriptor Block 6 10 or 12 bytes Block Move Instructions 6 9 If any other Group Code is received the DMA Byte Counter DBC register is not modified and the LSI53C810A will request the number of bytes specified in the DMA Byte Counter DBC register If the DMA Byte Counter DBC register contains 0x000000 an illegal instruction interrupt is generated The LSI53C810A transfers the number of bytes specified in the DMA Byte Counter DBC register starting at the address specified in the DMA Next Address DNAD register If the SATN signal is asserted by the Initiator or a parity error occurred during the transfer the transfer can optionally be halted and an interrupt generated The Disable Halt on Parity Error or ATN bit in the SCSI Control One SCNTL1 register controls whether the LSI53C810A halts on these conditions immediately or waits until completion of the current Move Initiator Mode OPC Instruction Defined 0 Reserved 1 MOVE These instructions perform the following steps 1
10. Additional Interface 4 1 PCI Bus Interface Signals The PCI signal definitions are organized into the following functional groups Power and Ground Signals System Signals Address and Data Signals Interface Control Signals Arbitration Signals and Error Reporting Signals 4 1 1 System Signals Table 4 2 Table 4 2 describes the System Signals group System Signals Name Pin No Type Description CLK 80 Clock provides timing for all transactions on the PCI bus and is an input to every PCI device All other PCI signals are sampled on the rising edge of CLK and other timing parameters are defined with respect to this edge Clock can optionally serve as the SCSI core clock but this may effect fast SCSI transfer rates RST 79 Reset forces the PCI sequencer of each device to a known state All T S and S T S signals are forced to a high impedance state and all internal logic is reset The RST input is synchronized internally to the rising edge of CLK The CLK input must be active while RST is active to properly reset the device PCI Bus Interface Signals 4 5 4 1 2 Address and Data Signals Table 4 3 Table 4 3 describes the Address and Data Signals group Address and Data Signals Description AD 81 0 85 86 88 89 T S Physical Dword Address and Data are multiplexed on the 91 92 94 95 same PCI pins During the first clock of a transaction 98 100
11. Bit 6 Set when the LSI53C810A as a PCI master detects a target device signaling a parity error during a data phase Master Data Parity Error Interrupt Enable 2 6 DMA Interrupt Enable DIEN Bit 6 Functional Description By clearing this bit a Master Data Parity Error does not cause assertion of IRQ but the status bit is set in the DMA Status DSTAT register Table 2 2 SCSI Parity Control Description Does not check for parity errors Parity is generated when sending SCSI data Asserts odd parity when sending SCSI data Does not check for parity errors Parity is generated when sending SCSI data Asserts even parity when sending SCSI data Checks for odd parity on SCSI data received Parity is generated when sending SCSI data Asserts odd parity when sending SCSI data Checks for odd parity on SCSI data received Parity is generated when sending SCSI data Asserts even parity when sending SCSI data 1 Key EPC Enable Parity Checking bit 3 SCSI Control Zero SCNTLO ASEP Assert SCSI Even Parity bit 2 SCSI Control One SCNTL1 Table 2 3 SCSI Parity Errors and Interrupts Description Halts when a parity error occurs in the target or initiator mode and does not generate an interrupt Halts when a parity error occurs in the target mode and generates an interrupt in target or initiator mode Does not halt in target mode when a parity error occurs until the e
12. Data Out 0 0 1 Data In 0 1 0 Command 0 1 1 Status 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Message Out 1 1 1 Message In RA Relative Addressing Mode 23 When this bit is set the 24 bit signed value in the DMA SCRIPTS Pointer Save DSPS register is used as a relative offset from the current DMA SCRIPTS Pointer DSP address which is pointing to the next instruction not the one currently executing The relative mode does not apply to Return and Interrupt SCRIPTS Jump Call an Absolute Address Start execution at the new absolute address Condition Codes Absolute Alternate Address Jump Call a Relative Address Start execution at the current address plus or minus the relative offset Command Condition Codes Don t Care Alternate Jump Offset The SCRIPTS program counter is a 32 bit value pointing to the SCRIPTS instruction currently under execution by the LSI53C810A The next address is formed by adding the 32 bit program counter to the 24 bit signed value of the last 24 bits of the Jump or Call instruction Because it is signed 2 s complement the jump can be forward or backward 6 32 Instruction Set of the I O Processor CT JMP A relative transfer can be to any address within a 16 Mbyte segment The program counter is combined with the 24 bit signed offset using addition or subtraction to form the new execution address SCRIPTS programs may contain a mixture of direct jumps and relative jumps t
13. Interrupt Status Zero SISTO clears the interrupt status Reading this register clears any bits that are set at the time the register is read but does not necessarily clear the register because additional interrupts may be pending the LSI53C810A stacks interrupts SCSI interrupt conditions may be individually masked through the SCSI Interrupt Enable Zero SIENO register When performing consecutive 8 bit reads of the DMA Status DSTAT SCSI Interrupt Status Zero SISTO and SCSI Interrupt Status One SIST1 registers in any order insert a delay equivalent to 12 CLK periods between the reads to ensure the interrupts clear properly Also if reading the registers when both the Interrupt Status ISTAT SIP and DIP bits may not be set read the SCSI Interrupt Status Zero SISTO and SCSI Interrupt Status One SIST1 registers the DMA Status DSTAT register to avoid missing a SCSI interrupt For more information on interrupts refer to Chapter 2 Functional Description M A Initiator Mode Phase Mismatch Target Mode SATN Active 7 In the initiator mode this bit is set if the SCSI phase asserted by the target does not match the instruction The phase is sampled when SREQ is asserted by the target In target mode this bit is set when the SATN signal is asserted by the initiator CMP Function Complete 6 This bit is set when an arbitration only or full arbitration sequence is completed 5 51 5 52 SEL RSL SGE UD
14. LSI53C810A It can be repeated during polling or should be called when the IRQ pin is asserted if hardware interrupts 1 Read Interrupt Status ISTAT If the INTF bit is set it must be written to a one to clear this status If only the SIP bit is set read SCSI Interrupt Status Zero SISTO and SCSI Interrupt Status One SIST1 to clear the SCSI interrupt condition and get the SCSI interrupt status The bits in the SISTO and SIST1 tell which SCSI interrupt s occurred and determine what action is required to service the interrupt s If only the DIP bit is set read the DMA Status DSTAT to clear the interrupt condition and get the DMA interrupt status The bits in DSTAT tell which DMA interrupts occurred and determine what action is required to service the interrupts If both the SIP and DIP bits are set read SCSI Interrupt Status Zero SISTO SCSI Interrupt Status One SIST1 and DMA Status DSTAT to clear the SCSI and DMA interrupt condition and get the interrupt status If using 8 bit reads of the SISTO SIST1 and DSTAT registers to clear interrupts insert a 12 CLK delay between the Interrupt Handling 2 21 consecutive reads to ensure that the interrupts clear properly Both the SCSI and DMA interrupt conditions should be handled before leaving the ISR It is recommended that the DMA interrupt is serviced before the SCSI interrupt because a serious DMA interrupt condition could influence how the SCSI interrupt is acted up
15. Register 0x46 0xC6 Memory Access Conirol MACNTL Read Write 7 4 3 2 1 0 TYP 3 0 DWR DRD PSCPT SCPTS 0 1 1 0 0 0 0 0 TYP 3 0 Chip Type 7 4 These bits identify the chip type for software purposes Bits 3 through 0 of this register are used to determine if an external bus master access is to local or far memory 5 55 5 56 DWR DRD PSCPT SCPTS When bits 3 through 0 are set the corresponding access is considered local and the MAC _TESTOUT pin is driven high When these bits are cleared the corresponding access is to far memory and the MAC _TESTOUT pin is driven low This function is enabled after a Transfer Control SCRIPTS instruction is executed DataWR 3 This bit is used to define if a data write is considered to be a local memory access DataRD 2 This bit is used to define if a data read is considered to be a local memory access Pointer SCRIPTS 1 This bit is used to define if a pointer to a SCRIPTS indirect or table indirect fetch is considered local memory access SCRIPTS 0 This bit is used to define if a SCRIPTS fetch is considered to be a local memory access Register 0x47 0xC7 General Purpose Pin Control GPCNTL Read Write 7 6 5 2 1 0 ME FE R GPIO 1 0 0 0 x 0 1 1 1 1 This register is used to determine if the pins controlled by the General Purpose GPREG register are inputs or outputs Bits 1 0 in General Purpose Pin Control GPCNTL correspond to bits 1
16. This function is useful for memory to register operations using the Memory Move instruction when the LSI53C810A is I O mapped Bits 4 and 5 of the Chip Test Two CTEST2 register are used to determine the configuration status of the LSI53C810A Enable Read Line 3 This bit enables a PCI Read Line command If PCI cache mode is enabled by setting bits in the PCI Cache Line Size register the chip issues a Read Line command on all read cycles if other conditions are met For more information on these conditions refer to Chapter 3 PCI Functional Description Operating Registers ERMP BOF MAN Enable Read Multiple 2 Setting this bit causes Read Multiple commands to be issued on the PCI bus after certain conditions have been met These conditions are described in Chapter 3 PCI Functional Description Burst Opcode Fetch Enable 1 Setting this bit causes the LSI53C810A to fetch instructions in burst mode if the Burst Disable bit Chip Test Four CTEST4 bit7 is cleared Specifically the chip bursts in the first two Dwords of all instructions using a single bus ownership If the instruction is a Memory to Memory Move type the third Dword is accessed in a subsequent bus ownership If the instruction is an indirect type the additional Dword is accessed in a subsequent bus ownership If the instruction is a table indirect block move type the chip accesses the remaining two Dwords in a subsequent bus ownership thereby fe
17. a byte count between zero and 80 Parity Options 2 9 2 10 Step 2 Read bit 7 in the SCSI Status Zero SSTATO register to determine if any bytes are left in the SCSI Input Data Latch SIDL register If bit 7 is set in SSTATO then the SCSI Input Data Latch SIDL register is full Synchronous SCSI Receive Step 1 Subtract the seven least significant bits of the DMA Byte Counter DBC register from the 7 bit value of the DMA FIFO DFIFO register AND the result with Ox7F for a byte count between zero and 80 Step 2 Read the SCSI Status One SSTAT1 register and examine bits 7 4 the binary representation of the number of valid bytes in the SCSI FIFO to determine if any bytes are left in the SCSI FIFO Figure 2 2 LSI53C810A Host Interface Data Paths PCI PCI PCI PCI Interface Interface Interface Interface DMA FIFO DMA FIFO DMA FIFO DMA FIFO 4 bytes x 20 4 bytes x 20 4 bytes x 20 4 bytes x 20 SODL Register SCSI Interface SIDL Register SCSI Interface SODR Register SCSI Interface Asynchronous Asynchronous SCSI Send SCSI Recei en Eat SCSI Interface Synchronous Synchronous SCSI Send SCSI Receive Functional Description 2 6 SCSI Bus Interface The LSI53C810A supports SE operation only All SCSI signals are active LOW The LSI53C810A contains the SE output drivers and can be connected directly to the SCSI bus Each output is isolated from the power supply to ensure that a powered
18. document Important Please include your name phone number fax number and company address so that we may contact you directly for Clarification or additional information Thank you for your help in improving the quality of our documents LSI53C810A PCI to SCSI I O Processor Reader s Comments Fax your comments to LSI Logic Corporation Technical Publications M S E 198 Fax 408 433 4333 Please tell us how you rate this document LS 53C810A PCI to SCSI I O Processor Technical Manual Place a check mark in the appropriate blank for each category Excellent Good Average Fair Poor Completeness of information Clarity of information Ease of finding information Technical content Usefulness of examples and illustrations Overall manual What could we do to improve this document If you found errors in this document please specify the error and page number If appropriate please fax a marked up copy of the page s Please complete the information below so that we may contact you directly for clarification or additional information Name Date Telephone Fax Title Department Mail Stop Company Name Street City State Zip Customer Feedback U S Distributors by State A E Avnet Electronics http www hh avnet com B M Bell Microproducts Inc for HAB s http www bellmicro com l E Insight Electronics http www insight elec
19. during selection 2 11 response to 2 11 selection or reselection time out bit 5 50 STO bit 5 54 selection response logic test bit 5 60 selection time out bits 5 58 SEM bit 5 27 semaphore bit 5 27 Index SERR 4 8 SFBR register 5 17 SGE bit 5 48 5 52 shadow register test mode bit 5 35 SI_O bit 5 20 SI_O status bit 5 20 SIDL bit 5 22 SIDL least significant byte full bit 5 22 SIDL register 5 65 SIENO register 5 48 SIEN1 register 5 50 signal process bit 5 27 5 31 SIGP bit 5 27 5 31 single step interrupt bit 5 21 5 44 single ended operation 2 11 single step mode bit 5 46 SIO 4 9 SIOM bit 5 42 SIP bit 5 28 SIR bit 5 21 5 44 SISO bit 5 61 SISTO register 5 51 SIST1 register 5 53 SLB bit 5 62 SLPAR register 5 54 SLT bit 5 60 SMSG 4 9 SMSG status bit 5 20 SOCL register 5 18 SODL least significant byte full bit 5 23 SODL register 5 66 SODR least significant byte full bit 5 22 software reset bit 5 27 SOM bit 5 61 source I O memory enable bit 5 42 SOZ bit 5 60 SRE bit 5 11 SREQ 4 9 SREQ status bit 5 20 SRST bit 5 27 SRST 4 9 SRTM bit 5 35 SSAID bits 5 60 SSEL 4 9 SSEL status bit 5 20 SSI bit 5 21 5 44 SSID register 5 19 SSM bit 5 46 SST bit 5 8 SSTATO register 5 22 SSTAT1 register 5 24 SSTAT2 register 5 25 stacked interrupts 2 19 START bit 5 4 start DMA operation bit 5 46 start SCSI transfer bit 5 8 start sequence bit 5 4 STD bit 5 46 STESTO register 5 60 STEST1
20. 2 7 1 3 Masking 2 18 A fatal interrupt as the name implies always causes SCRIPTS to stop running All nonfatal interrupts become fatal when they are enabled by setting the appropriate interrupt enable bit Interrupt masking is discussed in Section 2 7 1 3 Masking All DMA interrupts indicated by the DIP bit in ISTAT and one or more bits in DSTAT being set are fatal Some SCSI interrupts indicated by the SIP bit in the Interrupt Status ISTAT and one or more bits in SCSI Interrupt Status Zero SISTO or SCSI Interrupt Status One SIST1 being set are nonfatal When the LSI53C810A is operating in the Initiator mode only the Function Complete CMP Selected SEL Reselected RSL General Purpose Timer Expired GEN and Handshake to Handshake Timer Expired HTH interrupts are nonfatal When operating in the Target mode CMP SEL RSL Target mode SATWN active M A GEN and HTH are nonfatal Refer to the description for the Disable Halt on a Parity Error or SATN active Target Mode Only DHP bit in the SCSI Control One SCNTL1 register to configure the chip s behavior when the SATN interrupt is enabled during Target mode operation The Interrupt on the Fly interrupt is also nonfatal since SCRIPTS can continue when it occurs The reason for nonfatal interrupts is to prevent SCRIPTS from stopping when an interrupt occurs that does not require service from the CPU This prevents an interrupt when arbitration is comp
21. 2540 Clearwater l E Tel 727 524 8850 Fort Lauderdale A E Tel 954 484 5482 W E Tel 800 568 9953 Miami B M Tel 305 477 6406 Orlando A E Tel 407 657 3300 W E Tel 407 740 7450 Tampa W E Tel 800 395 9953 St Petersburg A E Tel 727 507 5000 Georgia Atlanta A E Tel 770 623 4400 B M Tel 770 980 4922 W E Tel 800 876 9953 E Tel 678 584 0812 A E Tel 800 851 2282 A E Tel 801 365 3800 W E Tel 801 974 9953 Illinois North South A E Tel 847 797 7300 Tel 314 291 5350 Chicago B M Tel 847 413 8530 W E Tel 800 853 9953 Schaumburg I E Tel 847 885 9700 Indiana Fort Wayne l E Tel 219 436 4250 W E Tel 888 358 9953 Indianapolis A E Tel 317 575 3500 lowa W E Tel 612 853 2280 Cedar Rapids A E Tel 319 393 0033 Kansas W E Tel 303 457 9953 Kansas City A E Tel 913 663 7900 Lenexa lE Tel 913 492 0408 Kentucky W E Tel 937 436 9953 Central Northern Western A E Tel 800 984 9503 Tel 800 767 0329 Tel 800 829 0146 Louisiana W E Tel 713 854 9953 North South A E Tel 800 231 0253 Tel 800 231 5575 Maine A E Tel 800 272 9255 W E Tel 781 271 9953 Maryland Baltimore A E Tel 410 720 3400 W E Tel 800 863 9953 Columbia B M Tel 800 673 7461 I E Tel 410 381 3131 Massachusetts Boston A E Tel 978 532 9808 W E Tel 800 444 9953 Burlingtonr LE Tel 781 270 9400 Marlborough B M Tel 508 480 9099 Woburn B M
22. 31 This 32 bit register contains the general purpose address pointer At the start of some SCRIPTS operations its value is copied from the DMA SCRIPTS Pointer Save DSPS register Its value may not be valid except in certain abort conditions The default value of this register is zero Registers 0x2C 0x2F 0xAC 0xAF DMA SCRIPTS Pointer DSP Read Write DSP 0 0 0 olo o o o o olololololololololololololo DSP DMA SCRIPTS Pointer 31 0 To execute SCSI SCRIPTS the address of the first SCRIPTS instruction must be written to this register In normal SCRIPTS operation once the starting address of 5 39 the first SCRIPTS instruction is written to this register SCRIPTS instructions are automatically fetched and executed until an interrupt condition occurs In single step mode there is a single step interrupt after each instruction is executed The DMA SCRIPTS Pointer DSP register does not need to be written with the next address but the Start DMA bit bit 2 DMA Control DCNTL register must be set each time the step interrupt occurs to fetch and execute the next SCRIPTS command When writing this register eight bits at a time writing the upper eight bits begins execution of the SCSI SCRIPTS The default value of this register is zero Registers 0x30 0x33 0xBO 0xB3 DMA SCRIPTS Pointer Save DSPS
23. 5 SEL Assert SCSI SEL Signal 4 ATN Assert SCSI ATN Signal 3 MSG Assert SCSI MSG Signal 2 C D Assert SCSI C_D Signal 1 1 0 Assert SCSI I_O Signal 0 This register is used primarily for diagnostic testing or programmed O operation It is controlled by the SCRIPTS processor when executing SCSI SCRIPTS SCSI Output Control Latch SOCL is used only when transferring data using programmed I O Some bits are set 1 or cleared 0 when executing SCSI SCRIPTS Do not write to the register once the LSI53C810A starts executing normal SCSI SCRIPTS Operating Registers Register Ox0A 0x8A SCSI Selector ID SSID Read Only 7 3 2 0 VAL R ENID 2 0 0 x Xx x 0 0 0 VAL SCSI Valid Bit 7 If VAL is asserted then the two SCSI IDs are detected on the bus during a bus initiated selection or reselection and the encoded destination SCSI ID bits below are valid If VAL is deasserted only one ID is present and the contents of the encoded destination ID are meaningless R Reserved 6 3 ENID 2 0 Encoded Destination SCSI ID 2 0 Reading the SSID register immediately after the LSI53C810A has been selected or reselected returns the binary encoded SCSI ID of the device that performed the operation These bits are invalid for targets that are selected under the single initiator option of the SCSI 1 specification This condition can be detected by examining the VAL bit above 5 19 5 20 Register 0x0B 0x8B SCSI Bus Conirol Lines SBC
24. 7 4 SEL 3 0 Minimum Timeout Minimum Timeout GEN 3 0 40 MHz 50 MHz 1 These values are correct if the CCF bits in the SCSI Control Three SCNTLS register are set according to the valid combinations in the bit description SEL Selection Time Out 3 0 These bits select the SCSI selection reselection time out period When this timing plus the 200 us selection abort time is exceeded the STO bit in the SCSI Interrupt Sta tus One SIST1 register is set For a more detailed explanation of interrupts refer to Chapter 2 Functional Description Register 0x49 0xC9 SCSI Timer One STIME1 Read Write 7 4 3 0 R GEN 3 0 Xx x x X 0 0 0 0 R Reserved 7 4 GEN 3 0 General Purpose Timer Period 3 0 These bits select the period of the general purpose timer The time measured is the time between enabling and disabling of the timer When this timing is exceeded the 5 58 Operating Registers Note GEN bit in the SCSI Interrupt Status One SIST1 register is set Refer to the table under SCSI Timer Zero STIMEO bits 3 0 for the available time out periods To reset a timer before it expires and obtain repeatable delays the time value must be written to zero first and then written back to the desired value This is also required when changing from one time value to another See Chapter 2 Functional Description for an explanation of how interrupts are generated when the timers expire Reg
25. 853 2280 Ohio Cleveland A E Tel 216 498 1100 W E Tel 800 763 9953 Dayton A E Tel 614 888 3313 I E Tel 937 253 7501 W E Tel 800 575 9953 Strongsville B M Tel 440 238 0404 Valley View I E Tel 216 520 4333 Oklahoma W E Tel 972 235 9953 Tulsa A E Tel 918 459 6000 l E Tel 918 665 4664 Oregon Beavertonr B M Tel 503 524 0787 l E Tel 503 644 3300 Portland A E Tel 503 526 6200 W E Tel 800 879 9953 Pennsylvania Mercer LE Tel 412 662 2707 Pittsburgh A E Tel 412 281 4150 W E Tel 440 248 9996 Philadelphia A E Tel 800 526 4812 B M Tel 215 741 4080 W E Tel 800 871 9953 Rhode Island A E 800 272 9255 W E Tel 781 271 9953 South Carolina A E Tel 919 872 0712 W E Tel 919 469 1502 South Dakota el 800 829 0116 A E T W E Tel 612 853 2280 Tennessee W E Tel 256 830 1119 East West A E Tel 800 241 8182 Tel 800 633 2918 A E Tel 512 219 3700 B M Tel 512 258 0725 I E Tel 512 719 3090 W E Tel 800 365 9953 Dallas A E Tel 214 553 4300 B M Tel 972 783 4191 W E Tel 800 955 9953 El Paso A E Tel 800 526 9238 Houston A E 713 781 6100 e B M Tel 713 917 0663 W E Tel 800 888 9953 Richardson l E Tel 972 783 0800 Rio Grande Valley A E Tel 210 412 2047 Stafford I E Tel 281 277 8200 Utah Centervil B M Tel 801 295 3900 Murray E Tel 801 288 9001 Salt Lake City A E Tel 801 365 3800 W E Tel 8
26. DSP 0x2C 0x2F 0xAC OxAF Read Write DMA SCRIPTS Pointer Save DSPS 0x30 0x33 0xB0 0xB3 Read Write DMA Status DSTAT 0x0C 0x8C Read Only General Purpose GPREG 0x07 0x87 Read Write General Purpose Pin Control GPCNTL 0x47 0xC7 Read Write Interrupt Status ISTAT 0x14 0x94 Read Write Memory Access Control MACNTL 0x46 0xC6 Read Write Response ID RESPID A 2 Register Summary 0x4A 0xCA Read Write Table A 2 SCSI Registers Register Name Scratch Byte Register SBR Address 0x3A 0xBA Read Write Read Write Scratch Register A SCRATCHA 0x34 0x37 0xB4 0xB7 Read Write SCSI Bus Control Lines SBCL 0x0B 0x8B Read Only SCSI Bus Data Lines SBDL 0x58 0xD8 Read Only SCSI Chip ID SCID 0x04 0x84 Read Write SCSI Control One SCNTL1 0x01 0x81 Read Write SCSI Control Three SCNTL3 0x03 0x83 Read Write SCSI Control Two SCNTL2 0x02 0x82 Read Write SCSI Control Zero SCNTLO 0x00 0x80 Read Write SCSI Destination ID SDID 0x06 0x86 Read Write SCSI First Byte Received SFBR 0x08 0x88 Read Write SCSI Input Data Latch SIDL 0x50 0xD0 Read Only SCSI Interrupt Enable One SIEN1 0x41 0xC1 Read Write SCSI Interrupt Enable Zero SIENO 0x40 0xC0 Read Write SCS
27. Enable 7 Setting this bit enables the active negation portion of TolerANT technology Active negation causes the SCSI Request Acknowledge Data and Parity signals to be actively deasserted instead of relying on external pull ups when the LSI53C810A is driving these signals Active deassertion of these signals occurs only when the 5 63 5 64 STR HSC DSI CSF LSI53C810A is in an information transfer phase TolerANT active negation should be enabled to improve setup and deassertion times at fast SCSI timings Active negation is disabled after reset or when this bit is cleared For more information on TolerANT technology refer to Chapter 1 General Description SCSI FIFO Test Read 6 Setting this bit places the SCSI core into a test mode in which the SCSI FIFO is easily read Reading the SCSI Output Data Latch SODL register causes the FIFO to unload Halt SCSI Clock 5 Asserting this bit causes the internal divided SCSI clock to come to a stop in a glitchless manner This bit is used for test purposes or to lower Ipp during a power down mode Disable Single Initiator Response 4 If this bit is set the LSI53C810A ignores all bus initiated selection attempts that employ the single initiator option from SCSI 1 In order to select the LSI53C810A while this bit is set the LSI53C810A s SCSI ID and the initiators SCSI ID must both be asserted Assert this bit in SCSI 2 systems so that a single bit error on the SCSI
28. ID Read Only 7 0 RID LSI53C810A eI Ee OP it I 8 0 0 0 1 0 1 0 0 RID Revision ID 7 0 This register specifies device and revision identifiers In the LSI53C810A the upper nibble is 0001b The lower nibble represents the current revision level of the device It should have the same value as the Chip Revision Level bits in the Chip Test Three CTEST3 register Register 0x09 Class Code Read Only cc Class Code 23 0 This register is used to identify the generic function of the device The upper byte of this register is a base class code the middle byte is a subclass code and the lower byte identifies a specific register level programming interface The value of this register is 0x010000 which indicates a SCSI controller Configuration Registers 3 15 3 16 Register 0x0C Cache Line Size Read Write 7 0 CLS 0 0 0 0 0 0 0 0 CLS Cache Line Size 7 0 This register specifies the system cache line size in units of 32 bit words Cache mode is enabled and disabled by the Cache Line Size Enable CLSE bit bit 7 in the DMA Control DCNTL register Setting this bit causes the LSI53C810A to align to cache line boundaries before allowing any bursting except during MMOVs in which the read and write addresses are Burst Size boundary misaligned For more information see Section 3 2 1 Support for PCI Cache Line Size Register page 3 3 Register 0x0D Latency Timer Read Write 7 0 LT 0 0 0 0 0 0 0 0 L
29. ISTAT register is set then a SCSl type interrupt has occurred and the SCSI Interrupt Status Zero SISTO and SCSI Interrupt Status One SIST1 registers should be read If the DIP bit in the Interrupt Status ISTAT register is set then a DMA type interrupt has occurred and the DMA Status DSTAT register should be read SCSl type and DMA type interrupts may occur simultaneously so in some cases both SIP and DIP may be set SISTO and SIST1 The SCSI Interrupt Status Zero SISTO and SCSI Interrupt Status One SIST1 registers contain the SCSl type interrupt bits Reading these registers determines which condition or conditions caused the SCSI type interrupt and clears that SCSI interrupt condition If the LSI53C810A is receiving data from the SCSI bus and a fatal interrupt condition occurs the LSI53C810A attempts to send the contents of the DMA FIFO to memory before generating the interrupt Functional Description If the LSI53C810A is sending data to the SCSI bus and a fatal SCSI interrupt condition occurs data could be left in the DMA FIFO Because of this the DMA FIFO Empty DFE bit in DMA Status DSTAT should be checked If this bit is cleared set the CLF Clear DMA FIFO and CSF Clear SCSI FIFO bits before continuing The CLF bit is bit 2 in Chip Test Three CTEST3 The CSF bit is bit 1 in SCSI Test Three STEST3 DSTAT The DMA Status DSTAT register contains the DMA type interrupt bits Reading this register
30. Interface Signals group Table 4 7 SCSI Bus Interface Signals Description SCSI Clock is used to derive all SCSI related timings The speed of this clock is determined by the application requirements In some applications SCLK may be sourced internally from the PCI bus clock CLK If SCLK is internally sourced tie the SCLK pin LOW SD 7 0 67 69 70 71 72 SCSI Data includes the following data lines and parity SDP 74 75 76 66 signals SD 7 0 8 bit SCSI data bus and SDP SCSI data parity bit SCTRL 57 55 60 56 62 SCSI Control includes the following signals 64 65 61 59 SCD SCSI phase line command data SIO SCSI phase line input output SMSG SCSI phase line message SREQ Data handshake signal from target device SACK Data handshake signal from initiator device SBSY SCSI bus arbitration signal busy SATN SCSI Attention the initiator is requesting a message out phase SRST SCSI bus reset SSEL SCSI bus arbitration signal select device SCSI Bus Interface Signals 4 9 4 2 2 Additional Interface Signals Table 4 8 describes the Additional Interface Signals group Table 4 8 Additional Interface Signals Description TESTIN Test In When this pin is driven LOW the LSI53C810A connects all inputs and outputs to an AND tree The SCSI control signals and data lines are not connected to the AND tree The output of the AND tree is connected to the Test Out pin Thi
31. LSI53C810A fetches the next instruction from the address pointed to by the 32 bit jump address field stored in the DMA Next Address DNAD register Manually set the LSI53C810A to Initiator mode when it is reselected If the CPU sets the SIGP bit in the SCSI Status Zero SSTATO register the LSI53C810A aborts the Wait Select instruction and fetches the next instruction from the address pointed to by the 32 bit jump address field stored in the DMA Next Address DNAD register Set Instruction When the SACK or SATN bits are set the corresponding bits in the SCSI Output Control Latch SOCL register are set Do not set SACK or SATN except for testing purposes When the target bit is set the corresponding bit in the SCSI Control Zero SCNTLO register is also set When the carry bit is set the corresponding bit in the Arithmetic Logic Unit ALU set None of the signals are set on the SCSI bus in Target mode is 6 15 Figure 6 3 illustrates the register bit values that represent an I O instruction Figure 6 3 I O Instruction Register lt DCMD Register DBC Register 31 30 29 28 27 26 25 24 23 22 21 20 19 1817 16 15 1413121110 9 8 7 PITT TL TT EENE E R R R R Set Clear ATN Set Clear ACK Set Clear Target Mode Set Clear Carry Encoded Destination ID 0 Encoded Destination ID 1 Encoded Destination ID 2 Reserved L____ Reserved Reserved L Reserved Reserve
32. Mbytes s and asynchronous transfer rates up to 7 Mbytes s on an 8 bit SCSI bus The SCSI core can be programmed with SCSI SCRIPTS making it easy to fine tune the system for specific mass storage devices or advanced SCSI requirements The SCSI core offers low level register access or a high level control interface Like first generation SCSI devices the LSI53C810A SCSI core can be accessed as a register oriented device The ability to sample and or assert any signal on the SCSI bus can be used in error recovery LSI53C810A PCI to SCSI I O Processor 2 1 and diagnostic procedures In support of loopback diagnostics the SCSI core can perform a self selection and operate as both an initiator and a target The SCSI core is controlled by the integrated SCRIPTS processor through a high level logical interface Commands controlling the SCSI core are fetched out of the main host memory or local memory These commands instruct the SCSI core to Select Reselect Disconnect Wait for a Disconnect Transfer Information Change Bus Phases and in general implement all aspects of the SCSI protocol The SCRIPTS processor is a special high speed processor optimized for SCSI protocol 2 1 1 DMA Core The DMA core is a bus master DMA device that attaches directly to the industry standard PCI bus The DMA core is tightly coupled to the SCSI core through the SCRIPTS processor which supports uninterrupted scatter gather memory operations The LSI53C810A
33. Operation page 2 13 Reserved 3 Clock Conversion Factor 2 0 These bits select the frequency of the SCLK for asynchronous SCSI operations The bit encoding is displayed in Table 5 2 All other combinations are reserved Operating Registers Table 5 2 Asynchronous Clock Conversion Factor Pe fe fe ware Pe fea sree Tee Persea ef Parsee Pee Tease Pe en een Register 0x04 0x84 SCSI Chip ID SCID Read Write 7 6 5 4 3 2 0 R RRE SRE R ENC 2 0 x 0 0 0 x 0 0 0 R Reserved 7 RRE Enable Response to Reselection 6 When this bit is set the LSI53C810A is enabled to respond to bus initiated reselection at the chip ID in the Response ID RESPID register Note that the LSI53C810A does not automatically reconfigure itself to initiator mode as a result of being reselected SRE Enable Response to Selection 5 When this bit is set the LSI53C810A is able to respond to bus initiated selection at the chip ID in the Response ID RESPID register Note that the LSI53C810A does not automatically reconfigure itself to target mode as a result of being selected 5 11 5 12 R Reserved 4 3 ENC 2 0 Encoded LSI53C810A Chip SCSI ID 2 0 These bits are used to store the LSI53C810A encoded SCSI ID This is the ID which the chip asserts when arbitrating for the SCSI bus The IDs that the LSI53C810A responds to when being selected or reselected are configured in the Response ID RESPID register The priority of the 8 poss
34. Tel 781 933 9010 Michigan Brighton I E Tel 810 229 7710 Detroit A E Tel 734 416 5800 W E Tel 888 318 9953 Minnesota Champlin B M Tel 800 557 2566 Eden Prairie B M Tel 800 255 1469 Minneapolis A E Tel 612 346 3000 W E Tel 800 860 9953 St Louis Park l E Tel 612 525 9999 Mississippi A E Tel 800 633 2918 W E Tel 256 830 1119 Missouri W E Tel St Louis A E Tel 314 291 5350 l E Tel 314 872 2182 630 620 0969 Montana A E Tel 800 526 1741 W E Tel 801 974 9953 Nebraska A E Tel 800 332 4375 W E Tel 303 457 9953 Nevada Las Vegas A E Tel 800 528 8471 W E Tel 702 765 7117 New Hampshire A E Tel 800 272 9255 W E Tel 781 271 9953 New Jersey North South A E Tel 201 515 1641 Tel 609 222 6400 Mt Laurel l E Tel 609 222 9566 Pine Brook W E Tel 800 862 9953 Parsippany l E Tel 973 299 4425 Wayne W E Tel 973 237 9010 New Mexico W E Tel 480 804 7000 Albuquerque A E Tel 505 293 5119 U S Distributors by State Continued New York Hauppauge RE Tel 516 761 0960 Long Island A E Tel 516 434 7400 W E Tel 800 861 9953 Rochester A E Tel 716 475 9130 lE Tel 716 242 7790 W E Tel 800 319 9953 Smithtown B M Tel 800 543 2008 Syracuse A E Tel 315 449 4927 North Carolina Raleigh A E Tel 919 859 9159 l E Tel 919 873 9922 W E Tel 800 560 9953 North Dakota A E Tel 800 829 0116 W E Tel 612
35. Timing Diagrams 7 4 1 Target Timing 7 4 2 Initiator Timing PCI Interface Timing SCSI Timings Package Drawings Register Summary Index Customer Feedback Contents 6 13 6 22 6 23 6 23 6 23 6 23 6 24 6 27 6 27 6 35 6 36 6 38 6 38 6 38 6 39 6 39 6 40 6 41 7 6 7 10 7 12 7 13 7 17 7 26 TA 7 33 Figures g 12 2 1 2 2 2 3 2 4 4 1 4 2 Sd 6 1 6 2 6 3 6 4 6 5 6 6 6 7 Tal ra 7 3 7 4 72 7 6 Le 7 8 Ta 7 10 A T12 7 13 7 14 FAS 7 16 Eg 7 18 7 19 7 20 LSI53C810A System Diagram LSI53C810A Chip Block Diagram DMA FIFO Sections LSI53C810A Host Interface Data Paths Active or Regulated Termination Determining the Synchronous Transfer Rate LSI53C810A Pin Diagram Functional Signal Grouping Register Address Map SCRIPTS Overview Block Move Instruction Register I O Instruction Register Read Write Register Instruction Transfer Control Instruction Memory to Memory Move Instruction Load and Store Instruction Format Rise and Fall Time Test Conditions SCSI Input Filtering Hysteresis of SCSI Receiver Input Current as a Function of Input Voltage Output Current as a Function of Output Voltage Clock Timing Reset Input Interrupt Output Waveforms PCI Configuration Register Read PCI Configuration Register Write Target Read Target Write OpCode Fetch Nonburst Burst Opcode Fetch Back to Back Read Back to Back Write Burst Read Burst Write Initiator Asynchronous Send I
36. Zero SISTO and SCSI Interrupt Status One SIST1 registers DIP DMA Interrupt Pending 0 This status bit is set when an interrupt condition is detected in the DMA portion of the LSI53C810A The following conditions cause a DMA interrupt to occur e A PCI parity error is detected e A bus fault is detected e An abort condition is detected e A SCRIPTS instruction is executed in single step mode e A SCRIPTS interrupt instruction is executed e An illegal instruction is detected To determine exactly which condition s caused the interrupt read the DMA Status DSTAT register Register 0x18 0x98 Chip Test Zero CTESTO Read Write FMT Byte Empty in DMA FIFO 7 0 This was a general purpose read write register in previous LSI53C8XX family chips Although it is still a read write register LSI Logic reserves the right to use these bits for future LSI53C8XX family enhancements 5 29 5 30 Register 0x19 0x99 Chip Test One CTEST1 Read Only FMT 3 0 Byte Empty in DMA FIFO 7 4 These bits identify the bottom bytes in the DMA FIFO that are empty Each bit corresponds to a byte lane in the DMA FIFO For example if byte lane three is empty then FMT3 will be set Since the FMT flags indicate the status of bytes at the bottom of the FIFO if all FMT bits are set the DMA FIFO is empty FFL 3 0 Byte Full in DMA FIFO 3 0 These status bits identify the top bytes in the DMA FIFO that are full Each bit corresponds
37. bit data start address for the Block Move instruction The value is loaded into the chip s address register and incremented as data is transferred The address of data to be moved is in the second Dword of this instruction When set the 32 bit user data start address for the Block Move is the address of a pointer to the actual data buffer address The value at the 32 bit start address is loaded into the chip s DMA Next Address DNAD register using a third Dword fetch 4 byte transfer across the host computer bus Direct Addressing The byte count and absolute address are Command Byte Count Address of Data Indirect Addressing Use the fetched byte count but fetch the data address from the address in the instruction Command Byte Count Address of Pointer to Data Once the data pointer address is loaded it is executed as when the chip operates in the direct mode This indirect feature allows a table of data buffer addresses to be specified Using the SCSI SCRIPTS assembler the table offset is placed in the SCRIPTS file when the program is assembled Then at the actual data transfer time the offsets are added to the base address of the data address table by the external processor The logical I O driver builds a structure of addresses for an I O rather than treating each address individually This feature makes it possible to locate SCSI SCRIPTS in a PROM 6 6 Instruction Set of the I O Processor Note Do n
38. bit is set the 24 bit signed value in the DMA Byte Counter DBC register is added to the value in the Data Structure Address DSA register and used as an offset relative to the value in the Data Structure Address DSA register The SCSI Control Three SCNTL3 value SCSI ID synchronous offset and synchronous period are loaded from this address Prior to the start of an I O load the Data Structure Address DSA with the base address of the I O data structure Any address on a Dword boundary is allowed After a Table Indirect opcode is fetched the Data Structure Address DSA is added to the 24 bit signed offset value from the opcode to generate the address of the required data Both positive and negative offsets are allowed A subsequent fetch from that address brings the data values into the chip SCRIPTS can directly execute operating system I O data structures saving time at the beginning of an I O operation The I O data structure can begin on any Dword boundary and may cross system segment boundaries There are two restrictions on the placement of data in system memory e The I O data structure must lie within the 8 Mbytes above or below the base address 6 19 e An I O command structure must have all four bytes contiguous in system memory as shown below The offset period bits are ordered as in the SCSI Transfer SXFER register The configuration bits are ordered as in the SCSI Control Three SCNTL3 register Use this bi
39. cycles the LSI53C810A registers are located on the 256 byte block boundary defined by the base address assigned through the configured register LSI53C810A PCI to SCSI I O Processor 3 1 The LSI53C810A operating registers are available in both the upper and lower 128 byte portions of the 256 byte space selected At initialization time each PCI device is assigned a base address for memory and I O accesses In the case of the LSI53C810A the upper 24 bits of the address are selected On every access the LSI53C810A compares its assigned base addresses with the value on the Address Data bus during the PCI address phase If the upper 24 bits match the access is for the LSI53C810A and the low order eight bits define the register being accessed A decode of C_BE 3 0 determines which registers and what type of access is to be performed I O Space The PCI specification defines I O space as a contiguous 32 bit I O address that is shared by all system resources including the LSI53C810A Base Address Zero I O determines which 256 byte I O area this device occupies Memory Space The PCI specification defines memory space as a contiguous 32 bit memory address that is shared by all system resources including the LSI53C810A Base Address One Memory determines which 256 byte memory area this device occupies 3 1 2 PCI Bus Commands and Functions Supported Bus commands indicate to the target the type of transaction the master is reques
40. data in a single bus ownership The number of cache lines to read is determined by the DMA Mode DMODE burst size bits In other words the chip switches its normal operating burst size to reflect the DMA Mode DMODE burst size settings for the Read Multiple command For example if the cache line size is 4 and the DMA Mode DMODE burst size is 16 the chip switches the current burst size from 4 to 16 and issues a Read Multiple After the transfer the chip switches the burst size back to the normal operating burst size of 4 Read Multiple with Read Line Enabled When both the Read Multiple and Read Line modes are enabled the Read Line command is not issued if the above conditions are met Instead a Read Multiple command is issued even though the conditions for Read Line are met If the Read Multiple mode is enabled and the Read Line mode is disabled Read Multiple commands are issued if the Read Multiple conditions are met 3 2 5 Unsupported PCI Commands 3 8 The LSI53C810A does not respond to reserved commands special cycle dual address cycle or interrupt acknowledge commands as a slave It never generates these commands as a master PCI bus commands and encoding types appear in Table 3 1 PCI Functional Description Table 3 1 C_BE 3 0 0b0000 PCI Bus Commands and Encoding Types Command Type Supported as Master Supported as Slave Interrupt Acknowledge No 0b0001 Special Cycle No 0b0010 I O
41. is re enabled allowing bursts in increments specified by the Cache Line Size register as explained above If the Cache Line Size register is not set default 0x00 the DMODE burst size is automatically used as the cache line size 3 2 3 1 MMOV Misalignment The LSI53C810A does not operate in a cache alignment mode when a MMOV instruction is issued and the read and write addresses are different distances from the nearest cache line boundary For example if the read address is 0x21F and the write address is 0x42F and the cache line size is eight 8 the addresses are byte aligned but they are not the same distance from the nearest cache boundary The read address is 1 byte from the cache boundary 0x220 and the write address is 17 bytes from the cache boundary 0x440 In this situation the chip does not align to cache boundaries and operates as an LSI53C810 3 4 PCI Functional Description 3 2 3 2 Memory Write and Invalidate Command The Memory Write and Invalidate command is identical to the Memory Write command except that it additionally guarantees a minimum transfer of one complete cache line that is to say the master intends to write all bytes within the addressed cache line in a single PCI transaction unless interrupted by the target This command requires implementation of the PCI Cache Line Size register at address 0x0C in PCI configuration space The LSI53C810A enables Memory Write and Invalidate cycles when bit 0 WRIE in the C
42. loaded with the base address of the I O data structure The address may be any address on a Dword boundary After a Table Indirect opcode is fetched the DSA is added to the 24 bit signed offset value from the opcode to generate the address of the required data both positive and negative offsets are allowed A subsequent fetch from that address brings the data values into the chip For a MOVE instruction the 24 bit byte count is fetched from system memory Then the 32 bit physical address is brought into the LSI53C810A Execution of the move begins at this point 6 8 Instruction Set of the I O Processor SCRIPTS can directly execute operating system I O data structures saving time at the beginning of an I O operation The I O data structure can begin on any Dword boundary and may cross system segment boundaries There are two restrictions on the placement of pointer data in system memory e the eight bytes of data in the MOVE instruction must be contiguous as shown below and e indirect data fetches are not available during execution of a Memory to Memory DMA operation 00 Byte Count Physical Data Address OpCode 27 This 1 bit field defines the instruction to be executed as a block move MOVE Target Mode OPC _ Instruction Defined 0 MOVE 1 Reserved These instructions perform the following steps 1 The LSI53C810A verifies that it is connected to the SCSI bus as a Target before executing this instruction
43. ni Ea Se Tain ae nd He tapes ES ONS es eee este A Alle fe So oO i i i i l x i A Se go g3 ES Te Gee Ge tee Se So ae ae OS ws us 22 SO Is mS os As AL O s ug Eo er ct OMe dood A Da A cor cs ES ans a H Q O Te oG oQ onm o Ee ne gt S Lg lt 9 S Z Lg go 2 go 9 gt gt W s oo Sto 19 Fj 19 9 D 1B bP Q amp rs ng On GH n v ne a ne n S 5 5 rt Oc a S a4 ai as ad Q Q Q SB ab B amp gt 3 BP 3 gt amp oO Q O xe Q Q Q c c c fa cca c cc c gt D D D D D D D D 2 2 2 2 2 i 2 2 a a a a a a a a a Electrical Characteristics 7 22 Figure 7 17 Burst Read Cont CLK Se SS ges I lt a m Os Wo E5 FS Lu M2 LO lt 9 S 2 of 2 Sa Je oS Os og ag c Oc D D 2 2 a6 Driven by LSI53C810A a Se S we aha a S a AE OA AAS z ai os T wi ALT D 2 SS lt 3 m 5 Zr zA aS lt TO Os gt oO OD a 19 e 5 q ge Z gt gt So a pa 23 s lt 2 Z EE Eye ek See E T Cep ST S asd IF S os As L o8 ug 2A 5 Fa Fo Qa O os o FE OF ria B BS 6 Fay Fey ag D ne n c S c Doo e Se te xe aS 6 a a a c c a a a S S Z Q a a 7 23 PCI Interface Timing Diagrams Figure 7 18 Burst Write CLK ET AA So Srg 5 amp S I 2 ia Q c A D 2 a GPIO1_ MASTER Driven by LSI53C810A Driven by LSI53C810A GNT Driven by Arbiter Driven by LSI53C810A AD Driven by LSI53C810A gt ae
44. of execution allows the LSI53C810A to make decisions based on the status of the SCSI bus which offloads the microprocessor from servicing the numerous interrupts inherent in I O operations Given the rich set of SCSI oriented features included in the instruction set and the ability to re enter the SCSI algorithm at any point this high level interface is all that is required for both normal and exception conditions Switching to low level mode for error recovery should never be required The following types of SCRIPTS instructions are implemented in the LSI53C810A as shown in Table 6 1 Instruction Set of the I O Processor Table 6 1 SCRIPTS Instructions Instruction Description Block Move Block Move instruction moves data between the SCSI bus and memory I O or Read Write I O or Read Write instructions cause the LSI53C810A to trigger common SCSI hardware sequences or to move registers Transfer Control Transfer Control instruction allows SCRIPTS instructions to make decisions based on real time SCSI bus conditions Memory Move Memory Move instruction causes the LSI53C810A to execute block moves between different parts of main memory Load and Store Load and Store instructions provide a more efficient way to move data to from memory from to an internal register in the chip without using the Memory Move instruction Each instruction consists of two or three 32 bit words The first 32 bit word is always load
45. or SACK n wk t t Lat Spel a Send Data 3 5 SDI7 0 SDP tes Bg ts lt tg Receive Data SDP 1 0 7 30 Electrical Characteristics Table 7 21 SCSI 1 Transfers SE 5 0 Mbytes s Parameter Send SREQ or SACK assertion pulse width Send SREQ or SACK deassertion pulse width Receive SREQ or SACK assertion pulse width Receive SREQ or SACK deassertion pulse width Send data setup to SREQ or SACK asserted Send data hold from SREQ or SACK asserted Receive data setup to SREQ or SACK asserted Receive data hold from SREQ or SACK asserted Parameter Send SREQ or SACK assertion pulse width Send SREQ or SACK deassertion pulse width Receive SREQ or SACK assertion pulse width Receive SREQ or SACK deassertion pulse width Send data setup to SREQ or SACK asserted Send data hold from SREQ or SACK asserted Receive data setup to SREQ or SACK asserted Receive data hold from SREQ or SACK asserted SCSI Timings 7 31 Table 7 23 SCSI 2 Fast Transfers 10 0 Mbytes s 8 Bit Transfers 50 MHz Clock Parameter Send SREQ or SACK assertion pulse width Send SREQ or SACK deassertion pulse width Receive SREQ or SACK assertion pulse width Receive SREQ or SACK deassertion pulse width Send data setup to SREQ or SACK asserted Send data hold from SREQ or SACK asserted Recei
46. place Move RegA SHR RegA Received SFBR register the result in the register Syntax Move RegA SHR Syntax Move SFBR SHR SFBR RegA 6 26 Instruction Set of the I O Processor Table 6 2 Operator Read Write Instructions Opcode 111 Read Modify Write Opcode 110 Move to SFBR Opcode 101 Move from SFBR 110 Add data to register without carry and place the result in the same register Syntax Move RegA data8 to RegA Add data to register with carry and place the result in the same register Syntax Move RegA data8 to RegA with carry Add data to register without carry and place the result in the SCSI First Byte Received SFBR register Syntax Move RegA data8 to SFBR Add data to register with carry and place the result in the SCSI First Byte Received SFBR register Syntax Move RegA data8 to SFBR with carry Add data to SFBR without carry and place the result in the register Syntax Move SFBR data8 to RegA Add data to SFBR with carry and place the result in the register Syntax Move SFBR data8 to RegA with carry 1 Data is shifted through the Carry bit and the Carry bit is shifted into the data byte Miscellaneous Notes Substitute the desired register name or address for RegA in the syntax examples data8 indicates eight bits of data 6 6 Transfer Control Instructions The Transfer Control or Conditiona
47. register 5 61 STEST2 register 5 62 STESTS register 5 63 STIMEO register 5 57 STIME1 register 5 58 STO bit 5 50 stop 4 7 IX 7 Storage Device Management System SDMS 2 3 Z STR bit 5 64 STW bit 5 65 ZMOD bit 5 35 SXFER register 5 12 ZSD bit 5 35 synchronous clock conversion factor bits 5 9 synchronous data transfer rate 2 13 synchronous operation 2 13 SZM bit 5 62 T target mode SATN active 5 51 target mode bit 5 5 target ready 4 7 TE bit 5 63 TEMP register 5 33 temporary register 5 33 TEOP bit 5 31 termination 2 11 testability 1 6 timer test mode bit 5 64 timing diagrams 7 12 PCI interface 7 26 SCSI timings 7 27 timings PCI 7 26 SCSI 7 27 TolerANT 1 2 enable bit 5 63 extend SREQ SACK filtering bit 5 63 totem pole output 4 3 TP 2 0 bits 5 12 transfer control instructions 6 27 prefetch unit flushing 2 4 transfer rate 1 3 clock conversion factor bits 5 10 synchronous 2 13 synchronous clock conversion factor bits 5 9 TRDY 4 7 TRG bit 5 5 TTM bit 5 64 TYP 3 0 bits 5 55 U UDC bit 5 49 5 52 unexpected disconnect bit 5 49 5 52 V VAL bit 5 19 VDD 4 3 VDD C 4 3 VSS 4 3 VSS C 4 3 VSS S 4 3 WwW WATN bit 5 4 WOA bit 5 23 won arbitration bit 5 23 IX 8 Index Customer Feedback We would appreciate your feedback on this document Please copy the following page add your comments and fax it to us at the number shown If appropriate please also fax copies of any marked up pages from this
48. showing the connections of the LSI53C810A in a PCI system is pictured in Figure 1 1 A block diagram of the LSI53C810A is pictured in Figure 1 2 General Description Figure 1 1 LSI53C810A System Diagram SCSI Connection Vss SCSI Term Connection VDD SCSI Bus PCI Bus LSI53C810A Peripheral 40 MHz Oscillator or Optional Internal Connection to PCI Bulkhead Bus Clock CPU Baseboard CPU Box LSI53C810A Benefits Summary 1 7 1 8 Figure 1 2 LSI53C810A Chip Block Diagram PCI PCI Master and Slave Control Block SCSI Operating Configuration SCRIPTS Registers Registers SCSI FIFO and SCSI Control Block TolerANT Technology Drivers and Receivers SE SCSI Bus General Description Chapter 2 Functional Description Chapter 2 is divided into the following sections e Section 2 1 SCSI Core e Section 2 2 SCRIPTS Processor e Section 2 3 Prefetching SCRIPTS Instructions e Section 2 4 PCI Cache Mode e Section 2 5 Parity Options e Section 2 6 SCSI Bus Interface e Section 2 7 Interrupt Handling The LSI53C810A contains three functional blocks the SCSI Core the DMA Core and the SCRIPTS Processor The LSI53C810A is fully supported by the SDMS a complete software package that supports the LSI Logic product line of SCSI processors and controllers 2 1 SCSI Core The SCSI core supports synchronous transfer rates up to 10
49. state bus master data bursts faster than 110 Mbytes s 33 MHz Supports PCI Cache Line Size register Features of the LSI53C810A which ease integration include 3 3 V 5 V PCI interface Full 32 bit PCI DMA bus master DMA controller using Memory to Memory Move instructions High performance SCSI core Integrated SCRIPTS processor Compact 100 pin PQFP packaging The LSI53C810A provides Direct PCl to SCSI connection Reduced SCSI development effort Support for the ASPI software standard using SDMS software Compatibility with existing LS153C7XX and LSI53C8XX family SCRIPTS Direct connection to PCI and SCSI SE bus Development tools and sample SCSI SCRIPTS Maskable and pollable interrupts General Description 1 2 5 Flexibility Three programmable SCSI timers Select Reselect Handshake to Handshake and General Purpose The time out period is programmable from 100 us to greater than 1 6 seconds SDMS software for complete PC based operating system support Support for relative jump New SCSI Selected As ID SSAID bits for use when responding with multiple IDs The LSI53C810A provides 1 2 6 Reliability High level programming interface SCSI SCRIPTS Support for execution of tailored SCSI sequences from main system RAM Flexible programming interface to tune I O performance or to adapt to unique SCSI devices Flexibility to accommodate changes in the logical I O interface definition Low level access to all regi
50. status of the LSI53C810A s internal TEOP signal The TEOP signal acknowledges the completion of a transfer through the SCSI portion of the LSI53C810A When this bit is set TEOP is active When this bit is clear TEOP is inactive Data Request Status 1 This bit indicates the status of the LSI53C810A s internal Data Request signal DREQ When this bit is set DREQ is active When this bit is clear DREQ is inactive Data Acknowledge Status 0 This bit indicates the status of the LSI53C810A s internal Data Acknowledge signal DACK When this bit is set DACK is inactive When this bit is clear DACK is active 5 31 5 32 Register 0x1B 0x9B Chip Test Three CTESTS3 Read Write V 3 0 FLF CLF FM WRIE V 38 0 FLF CLF FM x x 0 0 0 0 Chip Revision Level 7 4 These bits identify the chip revision level for software purposes Flush DMA FIFO 3 When this bit is set data residing in the DMA FIFO is transferred to memory starting at the address in the DMA Next Address DNAD register The internal DMAWR signal controlled by the Chip Test Five CTEST5 register determines the direction of the transfer This bit is not self clearing clear it once the data is successfully transferred by the LSI53C810A Polling of FIFO flags is allowed during flush operations Clear DMA FIFO 2 When this bit is set all data pointers for the DMA FIFO are cleared Any data in the FIFO is lost After the LSI53C810
51. the LSI53C810A to automatically assert SATN when it detects a parity error while operating as an initiator Enable Parity Checking SCSI Control Zero SCNTLO Bit 3 Enables the LSI53C810A to check for parity errors The LSI53C810A checks for odd parity Assert Even SCSI Parity SCSI Control One SCNTL1 Bit 2 Determines the SCSI parity sense generated by the LSI53C810A to the SCSI bus Disable Halt on SATN or a Parity Error Target Mode Only SCSI Control One SCNTL1 Bit 5 Causes the LSI53C810A not to halt operations when a parity error is detected in target mode Enable Parity Error Interrupt SCSI Interrupt Enable Zero SIENO Bit 0 Determines whether the LSI53C810A generates an interrupt when it detects a SCSI parity error Parity Error SCSI Interrupt Status Zero SISTO Bit 0 This status bit is set whenever the LSI53C810A detects a parity error on the SCSI bus Status of SCSI Parity Signal SCSI Status Zero SSTATO Bit 0 This status bit represents the active HIGH current state of the SCSI SDPO parity signal Latched SCSI Parity SCSI Status One SSTAT1 Bit 3 This bit reflects the SCSI odd parity signal corresponding to the data latched into the SCSI Input Data Latch SIDL register Master Parity Error Enable Chip Test Four CTEST4 Bit 3 Enables parity checking during master data phases Master Data Parity Error DMA Status DSTAT
52. write move 0x07 and SCNTL2 to SCNTL2 before the SCSI core expects a disconnect to occur normally prior to sending an Abort Abort Tag Bus Device Reset Clear Queue or Release Recovery message or before deasserting SACK after receiving a Disconnect command or Command Complete message R Reserved 6 0 Register 0x03 0x83 SCSI Control Three SCNTL3 Read Write 7 6 4 3 2 0 R SCF 2 0 R CCF 2 0 0 0 0 0 x 0 0 0 R Reserved 7 SCF 2 0 Synchronous Clock Conversion Factor 6 4 These bits select the factor by which the frequency of SCLK is divided before being presented to the synchronous SCSI control logic The bit encoding is displayed in Table 5 1 For synchronous receive the output of this divider is always divided by 4 and that value 5 9 5 10 Note R CCF 2 0 determines the transfer rate For example if SCLK is 40 MHz and the SCF value is set to divide by one then the maximum synchronous receive rate is 10 Mbytes s 40 1 4 10 For synchronous send the output of this divider gets divided by the transfer period XFERP bits in the SCSI Transfer SXFER register and that value determines the transfer rate For valid combinations of the SCF and XFERP see Table 5 2 Table 5 1 Synchronous Clock Conversion Factor Pe pepe sax Te Pe sor ef Pe eames a e e O pe e sos eee era For additional information on how the synchronous transfer rate is determined Section 2 6 3 Synchronous
53. zero Any bits marked as reserved should always be written to zero mask all information read from them Reserved bit functions may be changed at any time Unless otherwise indicated all bits in registers are active high that is the feature is enabled by setting the bit The bottom row of every register diagram shows the default register values which are enabled after the chip is powered on or reset Note The only register that the host CPU can access while the LSI53C810A is executing SCRIPTS is the Interrupt Status ISTAT register Attempts to access other registers interferes with the operation of the chip However all operating registers are accessible with SCRIPTS All read data is synchronized and stable when presented to the PCI bus The LSI53C810A cannot fetch SCRIPTS instructions from the operating register space Fetch instructions from system memory LSI53C810A PCI to SCSI I O Processor 5 1 Figure 5 1 Register Address Map 31 1615 0 Mem I O Config SCNTL3 SCNTL2 SCNTL1 SCNTLO 0x00 0x80 GPREG SDID SXFER SCID 0x04 0x84 SBCL SSID SOCL SFBR 0x08 0x88 SSTAT2 SSTAT1 SSTATO DSTAT 0x0C 0x8C DSA 0x10 0x90 Reserved ISTAT 0x14 0x94 CTEST3 CTEST2 CTEST1 Reserved 0x18 0x98 TEMP 0x1C 0x9C CTEST6 CTEST5 CTEST4 DFIFO 0x20 OxA0O DCMD DBC 0x24 OxA4 DNAD 0x28 0xA8 DSP 0x2C OxAC DSPS 0x30 OxBO SCRATCH A 0x34 0xB4 DCNTL SBR DIEN DMODE 0x38 0xB8 ADDER 0x3C
54. 0 in the General Purpose GPREG register When the bits are enabled as inputs an internal pull up is also enabled ME Master Enable 7 The internal bus master signal is presented on GPIO1 if this bit is set regardless of the state of bit 1 GPIO1_EN Operating Registers FE Fetch Enable 6 The internal opcode fetch signal is presented on GPIOO if this bit is set regardless of the state of bit 0 GPIOO_EN R Reserved 5 GPIO_EN 1 0 GPIO Enable 1 0 These bits power up set causing the GPIO1 and GPIOO pins to become inputs Resetting these bits causes GPIO 1 0 to become outputs Register 0x48 0xC8 SCSI Timer Zero STIMEO Read Write HTH 3 0 Handshake to Handshake Timer Period 7 4 These bits select the handshake to handshake time out period the maximum time between SCSI handshakes SREQ to SREQ in target mode or SACK to SACK in initiator mode When this timing is exceeded an interrupt is generated and the HTH bit in the SCSI Interrupt Status One SIST1 register is set The following table contains time out periods for the Handshake to Handshake Timer the Selection Reselection Timer bits 3 0 and the General Purpose Timer SCSI Timer One STIME1 bits 3 0 For a more detailed explanation of interrupts refer to Chapter 2 Functional Description HTH 7 4 SEL 3 0 Minimum Timeout Minimum Timeout GEN 3 0 40 MHz 50 MHz 0000 Disabled Disabled 0001 125 us 100 us 5 57 HTH
55. 00 477 9953 o Vermont A E Tel 800 272 9255 W E Tel 716 334 5970 Virginia A E Tel 800 638 5988 W E Tel 301 604 8488 Washington Kirkland KE Tel 425 820 8100 Seattle A E Tel 425 882 7000 W E Tel 800 248 9953 West Virginia A E Tel 800 638 5988 Wisconsin Milwaukee A E Tel 414 513 1500 W E Tel 800 867 9953 Wauwatosa LE Tel 414 258 5338 Wyoming A E Tel 800 332 9326 W E Tel 801 974 9953 Direct Sales Representatives by State Component and Boards E A Earle Associates Ex L Electrodyne UT GRP Group 2000 l S Infinity Sales Inc ION ION Associates Inc R A Rathsburg Associ ates Inc SGY Synergy Associates Inc Arizona Tempe E A Tel 480 921 3305 California Calabasas l S Tel 818 880 6480 Irvine l S Tel 714 833 0300 San Diego E A Tel 619 278 5441 Illinois Elmhurst R A Tel 630 516 8400 Indiana Cicero R A Tel Ligonier R A Tel Plainfield R A Tel 317 984 8608 219 894 3184 317 838 0360 Massachusetts Burlington SGY Tel 781 238 0870 Michigan Byron Center R A Tel 616 554 1460 Good Rich R A Tel 810 636 6060 Novi R A Tel 810 615 4000 North Carolina Cary GRP Tel 919 481 1530 Ohio Columbus R A Tel 614 457 2242 Dayton R A Tel 513 291 4001 Independence R A Tel 216 447 8825 Pennsylvania Somerset R A Tel 814 445 6976 Texas Austin ION Te Arlington ION
56. 0xBC SIST1 SISTO SIEN1 SIENO 0x40 0xCO GPCNTL MACNTL Reserved SLPAR 0x44 0xC4 Reserved RESPID STIME1 STIMEO 0x48 0xC8 STEST3 STEST2 STEST1 STESTO 0x4C O0xCC Reserved SIDL 0x50 0xDO Reserved SODL 0x54 0xD4 Reserved SBDL 0x58 0xD8 SCRATCH B 0x5C 0xDC Register 0x00 0x80 SCSI Control Zero SCNTLO Read Write 7 6 5 4 3 2 1 0 ARB 1 0 START WATN EPC R AAP TRG 1 1 0 0 0 x 0 0 5 2 Operating Registers ARB 1 0 Arbitration Mode Bits 1 and 0 7 6 1 ARB1 ARBO Arbitration Mode Simple arbitration pi o Reserved Full arbitration selection reselection Simple Arbitration The LSI53C810A waits for a bus free condition to occur It asserts SBSY and its SCSI ID contained in the SCSI Chip ID SCID register onto the SCSI bus If the SSEL signal is asserted by another SCSI device the LSI53C810A deasserts SBSY deasserts its ID and sets the Lost Arbitration bit bit 3 in the SCSI Status Zero SSTATO register After an arbitration delay the CPU should read the SCSI Bus Data Lines SBDL register to check if a higher priority SCSI ID is present If no higher priority ID bit is set and the Lost Arbitration bit is not set the LSI53C810A wins arbitration Once the LSI53C810A wins arbitration SSEL must be asserted using the SCSI Output Control Latch SOCL for a bus clear plus a bus settle delay 1 2 us before a low level selection is performed Full Arbitration Selection Reselection 1 2 The LSI53C
57. 1 2 4 AD 31 0 contain a physical byte address During subsequent 6 7 8 23 24 clocks AD 31 0 contain data A bus transaction consists of 25 27 29 30 an address phase followed by one or more data phases PCI 31 33 35 36 supports both read and write bursts AD 7 0 define the least 38 39 41 42 significant byte and AD 31 24 define the most significant 44 45 byte C_BE 8 0 96 10 21 34 T S Bus Command and Byte Enables are multiplexed on the same PCI pins During the address phase of a transaction C_BE 3 0 define the bus command During the data phase C_BE 3 0 are used as byte enables The byte enables determine which byte lanes carry meaningful data C_BE 0 applies to byte 0 and C_BE 3 to byte 3 PAR 20 T S Parity is the even parity bit that protects the AD 31 0 and C_BE 3 0 lines During address phase both the address and command bits are covered During data phase both data and byte enables are covered 4 6 Signal Descriptions 4 1 3 Interface Control Signals Table 4 4 Table 4 4 describes the Interface Control Signals group Interface Control Signals Description FRAME S T S Cycle Frame is driven by the current master to indicate the beginning and duration of an access FRAME is asserted to indicate that a bus transaction is beginning While FRAME is asserted data transfers continue While FRAME is deasserted either the transaction is in the final data phase or the bus is id
58. 1 SCSI control one register 5 6 SCSI control register two 5 9 SCSI control three 5 9 SCSI control zero 5 2 SCSI destination ID 5 15 SCSI first byte received 5 17 SCSI input data latch 5 65 SCSI interrupt enable one 5 50 SCSI interrupt enable zero 5 48 SCSI interrupt status one 5 53 SCSI interrupt status zero 5 51 SCSI longitudinal parity 5 54 SCSI output control latch 5 18 SCSI output data latch 5 66 SCSI selector ID 5 19 SCSI status one 5 24 SCSI status two 5 25 SCSI status zero 5 22 SCSI test one 5 61 SCSI test three 5 63 SCSI test two 5 62 SCSI test zero 5 60 SCSI timer one 5 58 SCSI timer zero 5 57 SCSI transfer 5 12 temporary stack 5 33 ORF bit 5 22 P PAR 4 6 PAR bit 5 49 5 53 parity 2 5 4 6 assert even SCSI parity bit 5 7 assert SATN on parity error bit 5 5 disable halt on parity error bit 5 6 enable parity checking bit 5 5 master data parity error bit 5 44 master parity error enable bit 5 35 parity error bit 5 53 SCSI parity error bit 5 49 parity error 4 8 parity error bit 5 53 PCI bus commands and functions supported 3 2 PCI bus commands and functions supported 3 2 PCI cache mode 2 4 3 3 cache line size enable bit 5 45 cache line size register 3 16 enable read line bit 5 42 enable read multiple bit 5 43 memory read line command 3 6 memory read multiple command 3 7 memory write and invalidate command 3 5 write and invalidate mode bit 3 12 PCI commands 3 2 PCI configuration registers 3 9 tO 3 19 base addre
59. 10 kQ pull up resistor Note These values are guaranteed by periodic characterization they are not 100 tested on every device TolerANT Technology 7 7 Figure 7 1 Rise and Fall Time Test Conditions 47 Q 20 pF P 2 5V Figure 7 2 SCSI Input Filtering t REQ or ACK Input VTH Note t4 is the input filtering period Figure 7 3 Hysteresis of SCSI Receiver Receiving Logic Level Input Voltage Volts 7 8 Electrical Characteristics Figure 7 4 Input Current as a Function of Input Voltage 40 D 20 D Qa E lt E 5 O 2 OUTPUT 2 20 ACTIVE 40 4 0 4 8 12 16 Input Voltage Volts Figure 7 5 Output Current as a Function of Output Voltage 3 0 g 100 o oO Q 3 80 amp 200 s z z 60 g 400 g N 8 6 40 5 600 N 3 aa f 5 2 O 800 3 0 0 1 2 3 4 5 0 1 2 3 4 5 Output Voltage Volts Output Voltage Volts TolerANT Technology 7 9 7 3 AC Characteristics The AC characteristics described in this section apply over the entire range of operating conditions refer to Section 7 1 DC Characteristics Chip timings are based on simulation at worst case voltage temperature and processing Timings were developed with a load capacitance of 50 pF Table 7 13 and Figure 7 6 provide clock timing data Table 7 13 Clock Timing Parameter Bus clock cycle time SCSI clock cycle time SCLK
60. 100 are considered I O instructions Refer to Table 6 2 for field definitions Operator 26 24 These bits are used in conjunction with the opcode bits to determine which instruction is currently selected Refer to Table 6 2 for field definitions Register Address A 6 0 22 16 It is possible to change register values from SCRIPTS in read modify write cycles or move to from SFBR cycles A 6 0 select an 8 bit source destination register within the LSI53C810A Destination Address 31 0 This field contains the 32 bit destination address where the data is to move 6 5 3 Read Modify Write Cycles During these cycles the register is read the selected operation is performed and the result is written back to the source register Read Write Instructions 6 23 The Add operation is used to increment or decrement register values or memory values if used in conjunction with a Memory to Register Move operation for use as loop counters 6 5 4 Move To From SFBR Cycles 6 24 All operations are read modify writes However two registers are involved one of which is always the SFBR The possible functions of this instruction are Write one byte value contained within the SCRIPTS instruction into any chip register Move to from the SFBR from to any other register Alter the value of a register with AND OR ADD XOR SHIFT LEFT or SHIFT RIGHT operators After moving values to the SFBR the compare and jump call or similar inst
61. 2 11 10 9 8 7 6 5 4 3 2 1 0 Memory Move Instructions 6 37 The DMA SCRIPTS Pointer Save DSPS and Data Structure Address DSA registers are additional holding registers used during the Memory Move However the contents of the Data Structure Address DSA register are preserved 6 7 1 First Dword IT 1 0 R NF Note TC 23 0 6 7 2 Second Dword 6 7 3 Third Dword Instruction Type Memory Move Instruction 31 30 Reserved 29 25 These bits are reserved and must be zero If any of these bits is set an illegal instruction interrupt occurs No Flush 24 When this bit is set the LSI53C810A performs a Memory Move MMOV without flushing the prefetch unit NFMMOV When this bit is cleared the Memory Move instruction automatically flushes the prefetch unit Use the NFMMOV if the source and destination are not within four instructions of the current MMOV instruction This bit has no effect unless the Prefetch Enable bit in the DMA Control DCNTL register is set For information on SCRIPTS instruction prefetching see Chapter 2 Func tional Description Transfer Count 23 0 The number of bytes to transfer is stored in the lower 24 bits of the first instruction word DSPS Register 31 0 These bits contain the source address of the Memory Move TEMP Register 31 0 These bits contain the destination address for the Memory Move 6 38 Instruction Set of the I O Processor 6 7 4 Read Write System Memory fro
62. 3 Setting this bit places all the open drain 48 mA SCSI drivers into a high impedance state This is to allow internal loopback mode operation without affecting the SCSI bus 5 62 Operating Registers R Reserved 2 EXT Extend SREQ SACK Filtering 1 LSI Logic TolerANT SCSI receiver technology includes a special digital filter on the SREQ and SACK pins which causes the disregarding of glitches on deasserting edges Setting this bit increases the filtering period from 30 ns to 60 ns on the deasserting edge of the SREQ and SACK signals Note Never set this bit during fast SCSI greater than 5 megatransfers per second operations because a valid assertion could be treated as a glitch LOW SCSI Low level Mode 0 Setting this bit places the LSI53C810A in low level mode In this mode no DMA operations occur and no SCRIPTS execute Arbitration and selection may be performed by setting the start sequence bit as described in the SCSI Control Zero SCNTLO register SCSI bus transfers are performed by manually asserting and polling SCSI signals Clearing this bit allows instructions to be executed in SCSI SCRIPTS mode Note Itis not necessary to set this bit for access to the SCSI bit level registers SCSI Output Data Latch SODL SCSI Bus Control Lines SBCL and input registers Register Ox4F OxCF SCSI Test Three STESTS3 Read Write 7 6 5 4 3 2 1 0 TE STR HSC DSI R TTM CSF STW 0 0 0 0 x 0 0 0 TE TolerANT
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64. 51 MACNTL register 5 55 MAN bit 5 43 manual start mode bit 5 43 MASR bit 5 37 master control for set or reset pulses bit 5 37 master data parity error bit 5 21 MDPE bit 5 44 master enable bit 5 56 master parity error enable bit 5 35 max SCSI synchronous offset bits 5 14 max_lat ML 7 0 3 19 MDPE bit 5 21 memory access control register 5 55 memory move instructions 6 36 and SCRIPTS instruction prefetching 2 3 no flush option 6 38 memory read line command 3 6 memory read multiple command 3 7 memory write and invalidate command 3 5 write and invalidate mode bit 3 12 min_gnt MG 7 0 3 19 move to from SFBR cycles 6 24 MPEE bit 5 35 MSG bit 5 18 5 20 5 25 N NFMMOV instruction 6 38 no flush memory to memory move 6 38 0 OLF bit 5 23 opcode fetch bursting 2 4 operating registers adder sum output 5 47 chip test five 5 36 chip test four 5 34 chip test one 5 30 chip test six 5 37 chip test three 5 32 chip test two 5 30 chip test zero 5 29 data structure address 5 26 DMA byte counter 5 38 DMA command 5 39 DMA control 5 45 DMA FIFO 5 33 DMA interrupt enable 5 44 DMA mode 5 41 DMA next address 5 39 DMA SCRIPTS pointer 5 39 DMA SCRIPTS pointer save 5 40 DMA status 5 20 general information 5 1 general purpose 5 16 general purpose pin control 5 56 interrupt status 5 26 memory access control 5 55 response ID zero 5 59 scratch register A 5 41 SCSI bus control lines 5 20 IX 3 SCSI bus data lines 5 66 SCSI chip ID 5 1
65. 7 GPREG register 5 16 grant 4 8 H halt SCSI clock bit HSC bit 5 64 handshake to handshake timer expired bit 5 50 5 54 handshake to handshake timer period bits 5 57 header type HT 7 0 3 17 high impedance mode bit 5 35 HTH bit 5 50 5 54 VO bit 5 25 I O instructions 6 13 _O bit 5 18 IARB bit 5 7 IDSEL 4 7 IID bit 5 22 5 44 illegal instruction detected bit 5 22 5 44 immediate arbitration bit 5 7 initialization device select 4 7 initiator mode phase mismatch 5 51 initiator ready 4 7 input 4 3 instructions block move 6 5 VO 6 13 load and store 6 39 memory move 6 36 read write 6 23 transfer control 6 27 interrupt line 3 18 pin IP 7 0 3 18 interrupt status register 5 26 interrupt on the fly bit 5 28 interrupts fatal vs nonfatal interrupts 2 18 halting 2 20 IRQ disable bit 2 17 5 46 masking 2 18 polling vs hardware 2 15 registers 2 16 stacked interrupts 2 19 INTF bit 5 28 IRDY 4 7 IRQ disable bit 5 46 IRQ mode bit 5 46 IRQD bit 5 46 IRQM bit 5 46 ISTAT register 5 26 L last disconnect bit 5 25 latched SCSI parity bit 5 24 latency timer LT 7 0 3 16 LDSC bit 5 25 LOA bit 5 23 load and store instructions 6 39 no flush option 6 40 prefetch unit and store instructions 2 4 6 41 lost arbitration bit 5 23 LOW bit 5 63 LSI53C700 family compatibility bit 5 47 LSI53C810A ease of use 1 4 flexibility 1 5 integration 1 4 performance 1 3 reliability 1 5 testability 1 6 Index M A bit 5 48 5
66. 7 0 DF 0 0 0 0 0 0 0 0 DF DMA FIFO 7 0 Writing to this register writes data to the appropriate byte lane of the DMA FIFO as determined by the FBL bits in the Chip Test Four CTEST4 register Reading this register unloads data from the appropriate byte lane of the DMA FIFO as determined by the FBL bits in the Chip Test Four CTEST4 register Data written to the FIFO is loaded into the top of the FIFO Data read out of the FIFO is taken from the bottom To prevent DMA data from being corrupted this register should not be accessed before starting or restarting SCRIPTS operation Write this register only when testing the DMA FIFO using the 5 37 23 Chip Test Four CTEST4 register Writes to this register while the test mode is not enabled produces unexpected results Registers 0x24 0x26 OxA4 0xA6 DMA Byte Counter DBC Read Write DBC X X X X X X X X X X X X X X X X X X X 5 38 DBC DMA Byte Counter 23 0 This 24 bit register determines the number of bytes transferred in a Block Move instruction While sending data to the SCSI bus the counter is decremented as data is moved into the DMA FIFO from memory While receiving data from the SCSI bus the counter is decremented as data is written to memory from the LSI53C810A The DMA Byte Counter DBC counter is decremented each time that data is transferred on the PCI bus It is decremented b
67. 8 7 6 5 4 3 2 1 0 R SE R EPER R WIE R EBM EMS EIS 0 0 0 0 0j 0 0 0 0 0 0 0 1 0 0 0 0 The Command register provides coarse control over a device s ability to generate and respond to PCI cycles When a zero is written to this register the LSI53C810A is logically disconnected from the PCI bus for all accesses except configuration accesses In the LSI53C810A bits 3 5 7 and 9 are not implemented Bits 10 through 15 are reserved Configuration Registers 3 11 3 12 SE EPER WIE EBM EMS Reserved 15 9 SERR Enable 8 This bit enables the SERR driver SERR is disabled when this bit is cleared The default value of this bit is zero This bit and bit 6 must be set to report address parity errors Reserved 7 Enable Parity Error Response 6 This bit allows the LSI53C810A to detect parity errors on the PCI bus and report these errors to the system Only data parity checking is enabled The LSI53C810A always generates parity for the PCI bus Reserved 5 Write and Invalidate Mode 4 This bit when set will cause Memory Write and Invalidate cycles to be issued on the PCI bus after certain conditions have been met For more information on these conditions refer to Section 3 2 3 2 Memory Write and Invalidate Command To enable Write and Invalidate Mode bit 0 in the Chip Test Three CTEST3 register operating registers must also be set Reserved 3 Enable Bus Mastering 2 This bit control
68. 810A waits for a bus free condition It asserts SBSY and its SCSI ID the highest priority ID stored in the SCSI Chip ID SCID register onto the SCSI bus If the SSEL signal is asserted by another SCSI device or if the LSI53C810A detects a higher priority ID the LSI53C810A deasserts BSY deasserts its ID and waits until the next bus free state to try arbitration again 5 3 5 4 START WATN 4 The LSI53C810A repeats arbitration until it wins control of the SCSI bus When it wins the Won Arbitration bit is set in the SCSI Status Zero SSTATO register bit 2 5 The LSI53C810A performs selection by asserting the following onto the SCSI bus SSEL the targets ID stored in the SCSI Destination ID SDID register and the LSI53C810A s ID stored in the SCSI Chip ID SCID register 6 After a selection is complete the Function Complete bit is set in the SCSI Interrupt Status Zero SISTO register bit 6 7 Ifa selection time out occurs the Selection Time Out bit is set in the SCSI Interrupt Status One SIST1 register bit 2 Start Sequence 5 When this bit is set the LSI53C810A starts the arbitration sequence indicated by the Arbitration Mode bits The Start Sequence bit is accessed directly in low level mode during SCSI SCRIPTS operations this bit is controlled by the SCRIPTS processor Do not start an arbitration sequence if the connected CON bit in the SCSI Control One SCNTL1 register bit 4 indicate
69. A Byte Counter DBC register values The second Dword contains the DMA SCRIPTS Pointer Save DSPS value This is either the actual memory location of where to Load and Store or the offset from the Data Structure Address DSA depending on the value of bit 28 DSA Relative A maximum of 4 bytes may be moved with these instructions The register address and memory address must have the same byte alignment and the count set such that it does not cross Dword boundaries The destination memory address in the Store instruction and the source address in the Load instruction may not map back to the Load and Store Instructions 6 39 operating register set of the chip If it does a PCI illegal read write cycle occur the chip issues an interrupt Illegal Instruction Detected immediately following Bits A1 AO 00 Number of Bytes Allowed to Load Store One two three or four One two or three One or two One The SIOM and DIOM bits in the DMA Mode DMODE register determine whether the destination or source address of the instruction is in Memory space or I O space The Load and Store utilizes the PCI commands for I O read and I O write to access the I O space 6 8 1 First Dword 6 40 IT 2 0 DSA NF Instruction Type 31 29 These bits should be 111 indicating the Load and Store instruction DSA Relative 28 When this bit is cleared the value in the DMA SCRIPTS Pointer Save DSPS is the actual 32 bit memo
70. A successfully clears the appropriate FIFO points and registers this bit automatically clears This bit does not clear the data visible at the bottom of the FIFO Fetch Pin Mode 1 When set this bit causes the FETCH pin to deassert during indirect and table indirect read operations FETCH is only active during the opcode portion of an instruction fetch This allows the storage of SCRIPTS in a PROM while data tables are stored in RAM If this bit is not set FETCH is asserted for all bus cycles during instruction fetches Operating Registers 31 WRIE Write and Invalidate Enable 0 This bit when set causes issuing of Memory Write and Invalidate commands on the PCI bus whenever legal These conditions are described in more detail in Chapter 3 PCI Functional Description Registers 0x1C 0x1F 0x9C 0x9F Temporary TEMP Read Write TEMP XIXIXIXIX XIXIXIXXI X XI X X X X X X XIX TEMP Temporary 31 0 This 32 bit register stores the Return instruction address pointer from the Call instruction The address pointer stored in this register is loaded into the DMA SCRIPTS Pointer DSP register when a Return instruction is executed This address points to the next instruction to execute Do not write to this register while the LSI53C810A is executing SCRIPTS During any Memory to Memory Move operati
71. C Selected 5 This bit is set when the LSI53C810A is selected by another SCSI device The Enable Response to Selection bit must be set in the SCSI Chip ID SCID register and the Response ID RESPID register must hold the chip s ID for the LSI53C810A to respond to selection attempts Reselected 4 This bit is set when the LSI53C810A is reselected by another SCSI device The Enable Response to Reselection bit must be set in the SCSI Chip ID SCID register and the Response ID RESPID register must hold the chip s ID for the LSI53C810A to respond to reselection attempts SCSI Gross Error 3 This bit is set when the LSI53C810A encounters a SCSI Gross Error Condition The following conditions can result in a SCSI Gross Error Condition e Data Underflow reading the SCSI FIFO register when no data is present e Data Overflow writing too many bytes to the SCSI FIFO or the synchronous offset causes overwriting the SCSI FIFO e Offset Underflow the LSI53C810A is operating in target mode and a SACK pulse is received when the outstanding offset is zero e Offset Overflow the other SCSI device sends a SREQ or SACK pulse with data which exceeds the maximum synchronous offset defined by the SCSI Transfer SXFER register e A phase change occurs with an outstanding synchronous offset when the LSI53C810A is operating as an initiator e Residual data in the synchronous data FIFO a transfer other than synchron
72. C810A asserts the Bus Request REQ output when the DMA FIFO can accommodate a transfer of at least one burst size of data Bus Request REQ is also asserted during start of transfer and end of transfer cleanup and alignment even though less than a full burst of transfers is performed The LSI53C810A inserts a fairness delay of four CLKs between burst length transfers as set in BL 1 0 during normal operation The fairness delay is not inserted during PCI retry cycles This gives the CPU and other bus master devices the opportunity to access the PCI bus between bursts 5 41 5 42 SIOM DIOM ERL poo e buat Co es on o 16 transfer burst Source I O Memory Enable 5 This bit is defined as an I O Memory Enable bit for the source address of a Memory Move or Block Move Command If this bit is set then the source address is in I O space and if cleared then the source address is in memory space This function is useful for register to memory operations using the Memory Move instruction when the LSI53C810A is I O mapped Bits 4 and 5 of the Chip Test Two CTEST2 register are used to determine the configuration status of the LSI53C810A Destination I O Memory Enable 4 This bit is defined as an I O Memory Enable bit for the destination address of a Memory Move or Block Move Command If this bit is set then the destination address is in I O space and if cleared then the destination address is in memory space
73. CK BBCK R MASR DDIR R 0 0 x 0 0 x x Xx ADCK Clock Address Incrementor 7 Setting this bit increments the address pointer contained in the DMA Next Address DNAD register The DMA Next Address DNAD register is incremented based on the DNAD contents and the current DMA Byte Counter DBC value This bit automatically clears itself after incrementing the DMA Next Address DNAD register BBCK Clock Byte Counter 6 Setting this bit decrements the byte count contained in the 24 bit DMA Byte Counter DBC register It is decremented based on the DMA Byte Counter DBC Operating Registers contents and the current DNAD value This bit automatically clears itself after decrementing the DMA Byte Counter DBC register R Reserved 5 MASR Master Control for Set or Reset Pulses 4 This bit controls the operation of bit 3 When this bit is set bit 3 asserts the corresponding signals When this bit is cleared bit 3 deasserts the corresponding signals Do not change this bit and bit 3 in the same write cycle DDIR DMA Direction 3 Setting this bit either asserts or deasserts the internal DMA Write DMAWR direction signal depending on the current status of the MASR bit in this register Asserting the DMAWR signal indicates that data is transferred from the SCSI bus to the host bus Deasserting the DMAWR signal transfers data from the host bus to the SCSI bus R Reserved 2 0 Register 0x23 0xA3 Chip Test Six CTEST6 Read Write
74. D to this register The SCSI ID is defined by the user in a SCRIPTS Select or Reselect instruction The value written should be the binary encoded ID value The priority of the 8 possible IDs in descending order is Highest Lowest 7 6 5 4 3 2 11 0 5 15 5 16 Register 0x07 0x87 General Purpose GPREG Read Write 7 2 1 0 R GPIO 1 0 x x x x x 0 0 R Reserved 7 2 GPIO 1 0 General Purpose 1 0 These bits are programmed through the General Purpose Pin Control GPCNTL register as inputs outputs or to perform special functions These signals can also be programmed as live inputs and sensed through a SCRIPTS register to register Move Instruction GPIO 1 0 default as inputs When configured as inputs an internal pull up is enabled LSI Logic SDMS software uses the GPIO 0 pin to toggle SCSI device LEDs turning on the LED whenever the LSI53C810A is connected to the SCSI bus SDMS software drives this pin low to turn on the LED or drives it high to turn off the LED The GPIO 1 0 pins are used in SDMS software to access serial NVRAM When used for accessing serial NVRAM GPIO 1 is used as a clock with the GPIO 0 pin serving as data Operating Registers Register 0x08 0x88 SCSI First Byte Received SFBR Read Write 7 0 IB 0 0 0 0 0 0 0 0 This register contains the first byte received in any asynchronous information transfer phase For example when the a LSI53C810A is operating in ini
75. ED WITHIN THE ZONE INDICATED 7 CONTROLLING DIMENSION MILLIMETER A DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL BE 08mm 003 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION DAMBAR EVEN LEAD SIDES CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT MINIMUM SPACING BETWEEN ADJACENT LEADS TO BE 0 10mm 9 MARKING AREA MUST BE FREE FROM PACKAGE SURFACE PROTRUSION OR INTRUSION 10 PLATING THICKNESS INCLUDED PLATING THICKNESS TO BE 0 005mm MINIMUM 0 020mm MAXIMUM i AB D A LSI LOGIC CORPORATION L 48580 KATO ROAD FREMONT CA 94539 TIME 100LD PLASTIC QUAD FLAT PACK ODD LEAD SIDES COPPER CODE UD DETAIL A DWG NO J701 000375 00 Sera SCALE SHEET 2of2 Important This drawing may not be the latest version For board layout and manufacturing obtain the most recent engineering drawings from your LSI Logic marketing representative by requesting the outline drawing for package code UD Package Drawings 7 35 7 36 Electrical Characteristics Appendix A Register Summary Table A 1 lists the LSI53C810A configuration registers by register name Table A 1 Configuration Registers Register Name Address Read Write Base Address One Memory Read Write Base Address Zero I O Read Write Cache Line Size Read Write Class Code Rea
76. Examples of Synchronous Transfer Periods and Rates for SCSI 1 Cont SCF XFERP SXFER Bits 7 5 Synch Send Rate Mbytes s Synch Send Period ns Synch Receive Rate Mbytes s Synch Receive Period ns Table 5 4 4 4 4 4 Examples of Synchronous Transfer Periods and Rates for Fast SCSI sce Synch SCLK SCNTL3 Send Rate MHz Bits 6 4 Mbytes s 5 50 4 5 4 4 9 35 106 67 4 8 33 120 25 4 16 67 4 4 17 240 4 17 240 R Reserved 4 MO 3 0 Max SCSI Synchronous Offset 3 0 These bits describe the maximum SCSI synchronous offset used by the LSI53C810A when transferring synchronous SCSI data in either the initiator or target mode Table 5 5 describes the possible combinations and their relationship to the synchronous data offset used by Operating Registers the LSI53C810A These bits determine the LSI53C810A s method of transfer for Data In and Data Out phases only all other information transfers occur asynchronously Table 5 5 SCSI Synchronous Offset Values Reserved es Register 0x06 0x86 SCSI Destination ID SDID Read Write eee COT o l io i R Reserved 7 3 ENC 2 0 Encoded destination SCSI ID 2 0 Writing these bits sets the SCSI ID of the intended initiator or target during SCSI reselection or selection phases respectively When executing SCRIPTS the SCRIPTS processor writes the destination SCSI I
77. F 3 19 encoded chip SCSI ID bits 5 12 register bits abort operation 5 26 aborted 5 21 5 44 arbitration in progress 5 23 arbitration mode 5 3 arbitration priority encoder test 5 60 assert even SCSI parity 5 7 assert SATN on parity error 5 5 assert SCSI ACK 5 18 assert SCSI ATN 5 18 assert SCSI BSY 5 18 assert SCSI C_D 5 18 assert SCSI data bus 5 6 assert SCSI _O 5 18 assert SCSI MSG 5 18 assert SCSI REQ signal 5 18 assert SCSI RST signal 5 7 assert SCSI SEL 5 18 burst disable 5 34 burst length 5 41 burst mode fetch enable 5 43 bus fault 5 44 byte empty in DMA FIFO 5 30 byte full in DMA FIFO 5 30 byte offset counter 5 33 cache line size enable 5 45 chip revision level 5 32 chip type 5 55 clear DMA FIFO 5 32 clear SCSI FIFO 5 64 clock address incrementor 5 36 clock byte counter 5 36 clock conversion factor 5 10 Index configured as I O 5 31 configured as memory 5 31 connected 5 7 5 28 DACK 5 31 data transfer direction 5 30 dataRD 5 56 dataWR 5 56 destination I O memory enable 5 42 disable halt on parity error 5 6 disable single initiator response 5 64 DMA direction 5 37 DMA FIFO 5 37 DMA FIFO empty bit 5 21 DMA interrupt pending 5 29 DREQ 5 31 enable parity checking 5 5 enable read line 5 42 enable read multiple 5 43 enable response to reselection 5 11 enable response to selection 5 11 encoded destination ID 5 15 encoded destination SCSI ID 5 19 extend SREQ SACK filterin
78. Houston ION Te Utah Salt Lake C E L Wiscons Muskego R A Saukville R A Te e e in e 512 794 9006 817 695 8000 281 376 2000 ity 801 264 8050 414 679 8250 414 268 1152 Sales Offices and Design Resource Centers LSI Logic Corporation Corporate Headquarters Tel 408 433 8000 Fax 408 433 8989 NORTH AMERICA California Costa Mesa Mint Technology Tel 949 752 6468 Fax 949 752 6868 Irvine Tel 949 809 4600 Fax 949 809 4444 Pleasanton Design Center Tel 925 730 8800 Fax 925 730 8700 San Diego Tel 858 467 6981 Fax 858 496 0548 Silicon Valley Tel 408 433 8000 Fax 408 954 3353 Wireless Design Center Tel 858 350 5560 Fax 858 350 0171 Colorado Boulder Tel 303 447 3800 Fax 303 541 0641 Colorado Springs Tel 719 533 7000 Fax 719 533 7020 Fort Collins Tel 970 223 5100 Fax 970 206 5549 Florida Boca Raton Tel 561 989 3236 Fax 561 989 3237 Georgia Alpharetta Tel 770 753 6146 Fax 770 753 6147 Illinois Oakbrook Terrace Tel 630 954 2234 Fax 630 954 2235 Kentucky Bowling Green Tel 270 793 0010 Fax 270 793 0040 Maryland Bethesda Tel 301 897 5800 Fax 301 897 8389 Massachusetts Waltham Tel 781 890 0180 Fax 781 890 6158 Burlington Mint Technology Tel 781 685 3800 Fax 781 685 3801 Minnesota Minneapolis Tel 612 921 8300 Fax 612 921 8399 New Jersey Red Bank Tel 732 9
79. I Interrupt Status One SIST1 0x43 0xC3 Read Only SCSI Interrupt Status Zero SISTO 0x42 0xC2 Read Only SCSI Longitudinal Parity SLPAR 0x44 0xC4 Read Write SCSI Output Control Latch SOCL 0x09 0x89 Read Write SCSI Output Data Latch SODL 0x54 0xD4 Read Write SCSI Selector ID SSID Ox0A 0x8A Read Only SCSI Status One SSTAT1 OxOE 0x8E Read Only SCSI Status Two SSTAT2 OxOF Ox8F Read Only SCSI Status Zero SSTATO Ox0D 0x8D Read Only SCSI Test One STEST1 0x4D 0xCD Read Write SCSI Test Three STEST3 Register Summary Ox4F OxCF Read Write A 3 Table A 2 SCSI Registers Register Name SCSI Test Two STEST2 Address Ox4E OxCE Read Write Read Write SCSI Test Zero STESTO 0x4C OxCC Read Only SCSI Timer One STIME1 0x49 0xC9 Read Write SCSI Timer Zero STIMEO 0x48 0xC8 Read Write SCSI Transfer SXFER 0x05 0x85 Read Write Temporary TEMP A 4 Register Summary 0x1C Ox1F 0x9C 0x9F Read Write Index Symbols AD 31 0 4 6 BARO 31 0 3 17 BARZ 31 0 3 17 CLS 7 0 3 16 FMT 5 29 HT 7 0 3 17 IL 7 0 3 18 IP 7 0 3 18 LT 7 0 3 16 MGI7 0 3 19 ML 7 0 3 19 Numerics encoded chip SCSI ID bits 5 12 3 3 5 volt PCI interface 2 5 3 state 4 3 A AAP bit 5 5 abort oper
80. I53C810A registers that are not supported are not writable and return all zeros when read Only those registers and bits that are currently supported by the LSI53C810A are described in this chapter Table 3 2 contains a list of the PCI configuration registers supported in the LSI53C810A Addresses 0x40 through 0x7F are not defined Table 3 2 PCI Configuration Register Map 31 1615 0 Vendor 1D 0x00 Not Supported Base Address Zero 1 0 Base Address One Memory Not Supported Not Supported Not Supported Not Supported O 0x20 Reserved Reserved Reserved Reserved Reserved 0x38 Interrupt Pin Interrupt Line 1 I O Base is supported 2 Memory Base is supported Note Addresses 0x40 to 0x7F are not defined All unsupported registers are not writable and return all zeros when read Reserved registers also return zeros when read o A 3 10 PCI Functional Description Register 0x00 Vendor ID Read Only 15 0 VID 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 VID Vendor ID 15 0 This field identifies the manufacturer of the device The Vendor ID is 0x1000 Register 0x02 Device ID Read Only 15 0 DID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DID Device ID 15 0 This field identifies the particular device The LSI53C810A device ID is 0x0001 Register 0x04 Command Read Write 15 9
81. IPTS Pointer DSP register leaving the instruction pointer unchanged Call Instruction The LSI53C810A can do a true false comparison of the ALU carry bit or compare the phase and or data as defined by the Phase Compare Data Compare and True False bit fields If the comparisons are true then it loads the DMA SCRIPTS Pointer DSP register with the contents of the DMA SCRIPTS Pointer Save DSPS register and that address value becomes the address of the next instruction When the LSI53C810A executes a Call instruction the instruction pointer contained in the DMA SCRIPTS Pointer DSP register is stored in the Temporary TEMP register Since the TEMP register is not a stack and can only hold one Dword nested call instructions are not allowed Instruction Set of the I O Processor If the comparisons are false the LSI53C810A fetches the next instruction from the address pointed to by the DMA SCRIPTS Pointer DSP register and the instruction pointer is not modified Return Instruction The LSI53C810A can do a true false comparison of the ALU carry bit or compare the phase and or data as defined by the Phase Compare Data Compare and True False bit fields If the comparisons are true then it loads the DMA SCRIPTS Pointer DSP register with the contents of the DMA SCRIPTS Pointer Save DSPS register That address value becomes the address of the next instruction When a Return instruction is executed the value stored
82. L Read Only I O This register returns the SCSI control line status A bit is set when the SREQ Status SACK Status SBSY Status SSEL Status SATN Status SMSG Status SC_D Status SI_O Status N oOo a a O N corresponding SCSI control line is asserted These bits are not latched they are a true representation of what is on the SCSI bus at the time the register is read The resulting read data is synchronized before being presented to the PCI bus to prevent parity errors from being passed to the system This register is used for diagnostics testing or operation in low level mode Register 0x0C 0x8C DMA Status DSTAT Read Only 7 6 5 DFE MDPE BF ABRT 1 0 0 Reading this register clears any bits that are set at the time the register is read but does not necessarily clear the register in case additional interrupts are pending the LSI53C810A stacks interrupts The DIP bit Operating Registers in the Interrupt Status ISTAT register is also cleared It is possible to mask DMA interrupt conditions individually through the DMA Interrupt Enable DIEN register When performing consecutive 8 bit reads of the DMA Status DSTAT SCSI Interrupt Status Zero SISTO and SCSI Interrupt Status One SIST1 registers in any order insert a delay equivalent to 12 CLK periods between the reads to ensure that the interrupts clear properly See Chapter 2 Functional Description for more information on
83. LSI53C810A can attach directly to a 3 3 V or a 5 V PCI interface due to separate Vpp pins for the PCI bus drivers This allows the devices to be used on the universal board recommended by the PCI Special Interest Group 2 4 3 Loopback Mode The LSI53C810A loopback mode allows testing of both initiator and target functions and in effect lets the chip communicate with itself When the Loopback Enable bit is set in the SCSI Test Two STEST2 register bit 4 the LSI53C810A allows control of all SCSI signals whether the chip is operating in the initiator or target mode For more information on this mode of operation refer to the SCS SCRIPTS Processors Programming Guide 2 5 Parity Options The LSI53C810A implements a flexible parity scheme that allows control of the parity sense allows parity checking to be turned on or off and has the ability to deliberately send a byte with bad parity over the SCSI bus to test parity error recovery procedures Table 2 1 defines the bits that are involved in parity control and observation Table 2 2 describes the parity control function of the Enable Parity Checking and Assert SCSI Even Parity bits in the SCSI Control Zero SCNTLO register Table 2 3 describes the options available when a parity error occurs Parity Options 2 5 Table 2 1 Bit Name Location Bits Used for Parity Control and Observation Description Assert SATN on Parity Errors SCSI Control Zero SCNTLO Bit 1 Causes
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85. Memory Read during all PCI read cycles Otherwise it issues a normal Memory Read command 3 2 4 Memory Read Multiple Command This command is identical to the Memory Read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting The LSI53C810A supports PCI Read Multiple functionality and issues Read Multiple commands on the PCI bus when the Read Multiple Mode is enabled This mode is enabled by setting bit 2 ERMP of the DMA Mode DMODE register The command is issued when certain conditions are met If cache mode is enabled a Read Multiple command is issued on all read cycles except opcode fetches when the following conditions are met 1 The CLSE bit Cache Line Size Enable bit 7 DMA Control DCNTL register and the ERMP bit Enable Read Multiple bit 2 DMA Mode DMODE register are set 2 The Cache Line Size register contains a legal burst size value 2 4 8 or 16 and that value is less than or equal to the DMA Mode DMODE burst size 3 The number of bytes to be transferred at the time a cache boundary is reached is equal to or greater than the DMA Mode DMODE burst size 4 The chip is aligned to a cache line boundary PCI Cache Mode 3 7 When these conditions are met the chip issues a Read Multiple command instead of a Memory Read during all PCI read cycles Burst Size Selection The Read Multiple command reads in multiple cache lines of
86. NOWLEDGMENT The LSI Logic logo design TolerANT SDMS and SCRIPTS are registered trademarks or trademarks of LSI Logic Corporation All other brand and product names may be trademarks of their respective companies Audience Organization Preface This book is the primary reference and technical manual for the LSI Logic LSI53C810A PCI to SCSI I O Processor It contains a complete functional description for the product and includes complete physical and electrical specifications This manual provides reference information on the LSI53C810A PCI to SCSI I O processor It is intended for system designers and programmers who are using this device to design a SCSI port for PCl based personal computers workstations or embedded applications This document has the following chapters and appendix Preface Chapter 1 General Description includes general information about the LSI53C810A and other members of the LSI53C8XX family of PCI to SCSI I O processors Chapter 2 Functional Description describes the main functional areas of the chip in more detail including the interfaces to the SCSI bus Chapter 3 PCI Functional Description describes the chip s connection to the PCI bus including the PCI commands and configuration registers supported Chapter 4 Signal Descriptions contains the pin diagrams and definitions of each signal Chapter 5 Operating Registers describes each bit in the operating registers organized by addres
87. Read Yes 0b0011 1 0 Write Yes 0b0100 Reserved N A 0b0101 Reserved N A 0b0110 Memory Read Yes 0b0111 Memory Write Yes 0b1000 Reserved N A 0b1001 Reserved N A 0b1010 Configuration Read Yes 0b1011 Configuration Write Yes 0b1100 Memory Read Multiple No defaults to 0110 0b1101 Dual Address Cycle DAC No 0b1110 Memory Read Line No defaults to 0110 0b1111 Memory Write and Invalidate No defaults to 0111 3 3 Configuration Registers The Configuration registers are accessible only by system BIOS during PCI configuration cycles and are not available to the user at any time No other cycles including SCRIPTS operations can access these registers The lower 128 bytes hold configuration data while the upper 128 bytes hold the LSI53C810A operating registers which are described in Chapter 5 Operating Registers The operating registers can be accessed by SCRIPTS or the host processor Configuration Registers 3 9 Note The configuration register descriptions are provided for general information only to indicate which PCI configuration addresses are supported in the LSI53C810A For detailed information refer to the PCI Specification All PCl compliant devices such as the LSI53C810A must support the Vendor ID Device ID Command and Status registers Support of other PCl compliant registers is optional In the LS
88. S SACK 4 9 SACK status bit 5 20 SATN 4 9 SATN active bit 5 51 SATN status bit 5 20 SBCL register 5 20 SBDL register 5 66 SBSY 4 9 SBSY status bit 5 20 SC_D status bit 5 20 SCD 4 9 SCE bit 5 62 SCF 2 0 bits 5 9 SCID register 5 11 SCLK 4 9 SCLK bit 5 61 SCNTLO register 5 2 SCNTL1 register 5 6 SCNTL2 register 5 9 SCNTLS3 register 5 9 SCPTS bit 5 56 SCRATCHA register 5 41 SCRIPTS sample operation 6 3 SCRIPTS bit 5 56 SCRIPTS instruction prefetching no flush memory move instruction 6 38 prefetch enable bit 5 45 prefetch flush bit 5 45 SCRIPTS interrupt instruction received bit 5 21 5 44 SCRIPTS processor 2 2 performance 2 2 SCSI termination 2 11 SCSI ATN condition target mode 5 48 SCSI bus control lines register 5 20 SCSI bus data lines register 5 66 SCSI bus interface 2 11 tO 2 12 SCSI C_D signal 5 25 SCSI chip ID register 5 11 SCSI clock 4 9 SCSI control 4 9 SCSI control enable bit 5 62 SCSI control one register 5 6 SCSI control three register 5 9 SCSI control two register 5 9 SCSI control zero register 5 2 SCSI core 2 1 SCSI data high impedance bit 5 35 SCSI destination ID register 5 15 SCSI disconnect unexpected bit 5 9 SCSI FIFO test read bit 5 64 SCSI FIFO test write bit 5 65 SCSI first byte received register 5 17 SCSI gross error bit 5 48 5 52 SCSI high impedance mode bit 5 62 SCSI I_O bit 5 25 SCSI input data latch register 5 65 SCSI instructions block move 6 5 VO 6 13 load store 6 39 me
89. T Latency Timer 7 0 The Latency Timer register specifies in units of PCI bus clocks the value of the Latency Timer for this PCI bus master The LSI53C810A supports this timer All eight bits are writable allowing latency values of 0 255 PCI clocks Use the following equation to calculate an optimum latency value for the LSI53C810A Latency 2 Burst Size typical wait states 1 Values greater than optimum are also acceptable PCI Functional Description Register Ox0E Header Type Read Only 7 0 HT 0 0 0 0 0 0 0 0 HT Header Type 7 0 This register identifies the layout of bytes 0x10 through Ox3F in configuration space and also whether or not the device contains multiple functions The value of this register is 0x00 Register 0x10 Base Address Zero I O Read Write BARZ ffx ff eff efx fff xf fe ff eff fe ff ff ee BARZ Base Address Register Zero I O 31 0 This 32 bit register has bit zero hardwired to one Bit 1 is reserved and must return a zero on all reads and the other bits are used to map the device into I O space Register 0x14 Base Address One Memory Read Write BARO xf ff efx efx ff xf fe ff eff x fe ff ff ee cf ex x 0 BARO Base Address Register One 31 0 This register has bit O hardwired to zero For detailed information on the operation of this register refer to the PCI Specification Configuration Registers 3 17 3 18 Register 0x3C Interrupt Line Re
90. TECHNICAL MANUAL LSI53C810A PCI to SCSI I O Processor Version 2 1 March 2001 LSITKe e S14067 This document contains proprietary information of LSI Logic Corporation The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation LSI Logic products are not intended for use in life support appliances devices or systems Use of any LSI Logic product in such applications without written consent of the appropriate LSI Logic officer is prohibited Document DB14 000168 00 First Edition March 2001 This document describes the LSI Logic LSI53C810A PCI to SCSI I O Processor and will remain the official reference source for all revisions releases of this product until rescinded by an update To receive product literature visit us at http www Isilogic com LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice LSI Logic does not assume any responsibility or liability arising out of the application or use of any product described herein except as expressly agreed to in writing by LSI Logic nor does the purchase or use of a product from LSI Logic convey a license under any patent rights copyrights trademark rights or any other of the intellectual property rights of LSI Logic or third parties Copyright 1995 2001 by LSI Logic Corporation All rights reserved TRADEMARK ACK
91. ad Write 7 0 IL 0 0 0 0 0 0 0 0 IL Interrupt Line 7 0 This register is used to communicate interrupt line routing information POST software writes the routing information into this register as it initiates and configures the system The value in this register tells which input of the system interrupt controller s the device s interrupt pin is connected to Values in this register are specified by system architecture Register 0x3D Interrupt Pin Read Only 7 0 IP 0 0 0 0 0 0 0 1 IP Interrupt Pin 7 0 This register indicates which interrupt pin the device uses Its value is set to 0x01 for the INTA signal PCI Functional Description Register Ox3E Min_Gnt Read Only 7 0 MG 0 0 0 1 0 0 0 1 MG Min_Gnt 7 0 This register is used to specify the desired settings for Latency Timer values Min_Gnt is used to specify how long a burst period the device needs The value specified in this register is in units of 0 25 microseconds Values of zero indicate that the device has no major requirements for the settings of Latency Timers The LSI53C810A sets the Min_Gnt register to 0x11 Register 0x3F Max_Lat Read Only 7 0 ML 0 1 0 0 0 0 0 0 ML Max_Lat 7 0 This register is used to specify the desired settings for Latency Timer values Max_Lat is used to specify how often the device needs to gain access to the PCI bus The value specified in these registers is in units of 0 25 microseconds Values of zero ind
92. and DSTAT After the first interrupt is cleared by reading the appropriate register the IRQ pin is deasserted for a minimum of three CLKs the stacked interrupts move into SISTO SIST1 or DSTAT and the IRQ pin is asserted once again Since a masked nonfatal interrupt does not set the SIP or DIP bits interrupt stacking does not occur A masked nonfatal interrupt still posts the interrupt in SISTO but does not assert the IRQ pin Since no interrupt is generated future interrupts move into SCSI Interrupt Status Zero SISTO or SCSI Interrupt Status One SIST1 instead of being stacked behind another interrupt When another condition occurs that generates an interrupt the bit corresponding to the earlier masked nonfatal interrupt is still set A related situation to interrupt stacking is when two interrupts occur simultaneously Since stacking does not occur until the SIP or DIP bits are set there is a small timing window in which multiple interrupts can occur but are not stacked These could be multiple SCSI interrupts SIP set multiple DMA interrupts DIP set or multiple SCSI and multiple DMA interrupts both SIP and DIP set As previously mentioned DMA interrupts do not attempt to flush the FIFOs before generating the interrupt It is important to set the Clear DMA FIFO CLF and Clear SCSI FIFO CSF bits if a DMA interrupt occurs and the DMA FIFO Empty DFE bit is not set This is because any future SCSI interrupts are not poste
93. ate leakage Table 7 5 Input Signals CLK SCLK GNT IDSEL RST TESTIN Parameter i Test Conditions Vin Input high voltage 2 0 Vpp 0 5 V Vit Input low voltage Vss 0 5 0 8 V lin Input leakage 1 0 1 0 uA Note CLK SCLK GNT and IDSEL have 100 uA pull ups that are enabled when TESTIN is low TESTIN has a 100 uA pull up that is always enabled DC Characteristics 7 3 Table 7 6 Capacitance Input capacitance of input pads Input capacitance of I O pads Table 7 7 Output Signals MAC _TESTOUT REQ Parameter Test Conditions Vou Output high voltage 2 4 Vpp V 16 mA VoL Output low voltage Vss 0 4 V 16 mA loH Output high current 8 mA Vpp 0 5 V loL Output low current 16 mA 0 4 V loz 3 state leakage 10 10 uA Note REQ has a 100 pA pull up that is enabled when TESTIN is low Table 7 8 Output Signal IRQ Parameter Test Conditions Vou Output high voltage 2 4 Vpp V 8 mA VoL Output low voltage Vss 0 4 V 8 mA loH Output high current 4 i mA Vpp 0 5 V lot Output low current 8 mA 0 4 V loz 3 state leakage 10 10 uA S Note IRQ has a 100 uA pull up that is enabled when TESTIN is low IRQ can be enabled with a register as an open drain with an internal 100 LA pull up 7 4 Electrical Characteristics Table 7 9 Output Signal SERR Parameter i Test Conditions Output low voltage
94. ation 5 61 SCSI loopback mode 5 62 SCSI low level mode 5 63 SCSI MSG signal 5 25 SCSI parity error 5 49 SCSI phase mismatch or SCSI ATN condition 5 48 SCSI reset condition 5 49 SCSI RST received 5 53 SCSI RST signal 5 23 SCSI SDP signal 5 23 SCSI selected as ID 5 60 SCSI synchronous offset maximum 5 61 SCSI synchronous offset zero 5 60 SCSI synchronous transfer period 5 12 SCSI true end of process 5 31 SCSI valid 5 19 select with SATN on a start sequence 5 4 selected 5 48 5 52 selection or reselection time out 5 50 5 54 selection response logic test 5 60 selection time out 5 58 semaphore 5 27 shadow register test mode 5 35 SI_O status 5 20 SIDL full 5 22 signal process 5 27 5 31 single step interrupt 5 21 5 44 single step mode 5 46 SMSG status 5 20 SODL full 5 23 SODR full 5 22 software reset 5 27 source I O memory enable 5 42 SREQ status 5 20 SSEL status 5 20 start DMA operation 5 46 start SCSI transfer 5 8 start sequence 5 4 synchronous clock conversion factor bits 5 9 target mode 5 5 unexpected disconnect 5 49 5 52 WATN 5 4 won arbitration 5 23 reliability 1 5 REQ bit 5 18 5 20 REQ 4 8 request 4 8 reselect during reselection 2 11 response to 2 11 reselected bit 5 48 5 52 reset 4 5 reset SCSI offset bit 5 62 RESPIDO register 5 59 response ID zero register 5 59 IX 6 Index revision level bits 5 32 ROF bit 5 62 RRE bit 5 11 RSL bit 5 48 5 52 RST bit 5 7 5 49 5 53 RST 4 5 RST bit 5 23
95. ation bit 5 26 aborted bit 5 21 5 44 ABRT bit 5 21 5 26 5 44 AC characteristics 7 10 ACK bit 5 18 5 20 ADB bit 5 6 ADCK bit 5 36 ADDER register 5 47 adder sum output register 5 47 AESP bit 5 7 AIP bit 5 23 ARB 1 0 bits 5 3 arbitration arbitration mode bits 5 3 in progress bit 5 23 mode bits 5 3 priority encoder test bit 5 60 ART bit 5 60 assert even SCSI parity force bad parity bit 5 7 assert SATN on parity error bit 5 5 assert SCSI ACK bit 5 18 assert SCSI ATN bit 5 18 assert SCSI BSY bit 5 18 assert SCSI C_D bit 5 18 assert SCSI data bus bit 5 6 assert SCSI _O bit 5 18 assert SCSI MSG bit 5 18 assert SCSI REQ signal bit 5 18 assert SCSI RST signal bit 5 7 assert SCSI SEL bit 5 18 ATN bit 5 18 5 20 base address register one BARO 31 0 3 17 zero I O BARZ 31 0 3 17 BBCK bit 5 36 BDIS bit 5 34 benefits summary 1 3 BF bit 5 21 5 44 bidirectional 4 3 BL 1 0 bits 5 41 block move instructions 6 5 BO 6 0 bits 5 33 BOF bit 5 43 BSY bit 5 18 5 20 burst disable bit 5 34 burst length bits 5 41 burst mode fetch enable bit 5 43 bus command and byte enables 4 6 bus fault bit 5 21 5 44 byte empty in DMA FIFO FMT 5 29 byte empty in DMA FIFO bits 5 30 byte full in DMA FIFO bits 5 30 byte offset counter bits 5 33 Cc C_BE 3 0 4 6 C_D bit 5 18 5 20 5 25 cache line size CLS 7 0 3 16 cache line size enable bit 5 45 cache mode see PCI cache mode 3 3 CCF 2 0 bits 5 10 chip revision
96. bles 7 17 through 7 23 and Figures 7 19 through 7 23 describe the LSI53C810A SCSI timing data Table 7 17 Initiator Asynchronous Send 5 Mbytes s Parameter SACK asserted from SREQ asserted SACK deasserted from SREQ deasserted Data setup to SACK asserted Data hold from SREQ deasserted Figure 7 19 Initiator Asynchronous Send SREQ SACK so aes a SCSI Timings 7 27 Table 7 18 Initiator Asynchronous Receive 5 Mbytes s Parameter SACK asserted from SREQ asserted SACK deasserted from SREQ deasserted Data setup to SREQ asserted Data hold from SACK asserted SREQ SACK ae van EK vo 7 28 Electrical Characteristics Table 7 19 Target Asynchronous Send 5 Mbytes s Parameter SACK asserted from SREQ asserted SACK deasserted from SREQ deasserted Data setup to SREQ asserted Data hold from SACK asserted Figure 7 21 Target Asynchronous Send SREQ SACK a a as Gc SCSI Timings 7 29 Table 7 20 Target Asynchronous Receive 5 Mbytes s Parameter SREQ deasserted from SACK asserted SREQ asserted from SACK deasserted Data setup to SREQ asserted Data hold from SACK asserted Figure 7 22 Target Asynchronous Receive SREQ SACK ogo wae XX Figure 7 23 Initiator and Target Synchronous Transfers t t le 1 gt a 2 gt SREQ
97. bus is not interpreted as a single initiator response Reserved 3 Timer Test Mode 2 Setting this bit facilitates testing of the selection time out general purpose and handshake to handshake timers by greatly reducing all three time out periods Setting this bit starts all three timers and if the respective bits in the SCSI Interrupt Enable One SIEN1 register are set the LSI53C810A generates interrupts at time out This bit is intended for internal manufacturing diagnosis and should not be used Clear SCSI FIFO 1 Setting this bit causes the full flags for the SCSI FIFO to be cleared This empties the FIFO This bit is self clearing In addition to the SCSI FIFO pointers the Operating Registers STW SCSI Input Data Latch SIDL SCSI Output Data Latch SODL and SODR full bits in the SCSI Status Zero SSTATO register are cleared SCSI FIFO Test Write 0 Setting this bit places the SCSI core into a test mode in which the FIFO is easily written While this bit is set writes to the SCSI Output Data Latch SODL register cause the entire word contained in this register to be loaded into the FIFO Writing the least significant byte of the SCSI Output Data Latch SODL register causes the FIFO to load Register 0x50 0xDO SCSI Input Data Latch SIDL Read Only 15 Q SIDL x x X X X X X X x X X X x X SIDL SCSI Input Data Latch 15 0 This register is used p
98. ccurs in the case of an unexpected disconnect This condition only occurs in initiator mode It happens when the target to which the LSI53C810A is connected disconnects from the SCSI bus unexpectedly See the SCSI Disconnect Unexpected bit in the SCSI Control Two SCNTL2 register for more information on expected versus unexpected disconnects Any disconnect in low level mode causes this condition SCSI Reset Condition 1 This bit controls whether an interrupt occurs when the SRST signal is asserted by the LSI53C810A or any other SCSI device Note that this condition is edge triggered so that multiple interrupts cannot occur because of a single SRST pulse SCSI Parity Error 0 This bit controls whether an interrupt occurs when the LSI53C810A detects a parity error while receiving or sending SCSI data See the Disable Halt on Parity Error or SATN Condition bits in the SCSI Control One SCNTL1 register for more information on when this condition is actually raised 5 49 5 50 Register 0x41 0xC1 SCSI Interrupt Enable One SIEN1 Read Write 7 3 2 1 0 R STO GEN HTH x x xX x 0 0 0 This register contains the interrupt mask bits corresponding to the interrupting conditions described in the SCSI Interrupt Status One SIST1 register An interrupt is masked by clearing the appropriate mask bit For more information on interrupts refer to Chapter 2 Functional Description R STO GEN HTH Reserved 7 3 Selecti
99. cessor must continually loop and read a register until it detects a bit set that indicates an interrupt This method is the fastest but it wastes CPU time Interrupt Handling 2 15 2 7 1 1 Registers 2 16 that could be used for other system tasks The preferred method of detecting interrupts in most systems is hardware interrupts In this case the LSI53C810A asserts the Interrupt Request IRQ line that interrupts the microprocessor causing the microprocessor to execute an interrupt service routine A hybrid approach would use hardware interrupts for long waits and use polling for short waits The registers in the LSI53C810A that are used for detecting or defining interrupts are the Interrupt Status ISTAT SCSI Interrupt Status Zero SISTO SCSI Interrupt Status One SIST1 DMA Status DSTAT SCSI Interrupt Enable Zero SIENO SCSI Interrupt Enable One SIEN1 DMA Control DCNTL and DMA Interrupt Enable DIEN ISTAT The ISTAT is the only register that can be accessed as a slave during SCRIPTS operation Therefore it is the register that is polled when polled interrupts are used It is also the first register that should be read after the IRQ pin is asserted in association with a hardware interrupt The INTF Interrupt on the Fly bit should be the first interrupt serviced It must be written to one to be cleared This interrupt must be cleared before servicing any other interrupts If the SIP bit in the Interrupt Status
100. cribe target timing Figure 7 9 PCI Configuration Register Read CLK Driven by System FRAME N t i Driven by System i i l a t2 AD lt mils ea S a LL LSI53C810A Data c 7 gt gee PE i i l i BE a Driven by Master cm Byte Enable 2 s PAR gt i Driven by Master Addr LSI53C810A Data IRDY Driven by Master TRDY Driven by LSI53C810A STOP Driven by LSI53C810A DEVSEL Driven by LSI53C810A PCI Interface Timing Diagrams 7 13 Figure 7 10 PCI Configuration Register Write CLK Driven by System FRAME Driven by Master AD Driven by Master C_BE Driven by Master PAR Driven by Master IRDY Driven by Master TRDY Driven by LSI53C810A STOP Driven by LSI53C810A DEVSEL Driven by LSI53C810A IDSEL Driven by Master 7 14 Electrical Characteristics Figure 7 11 Target Read CLK Driven by System FRAME Driven by Master Byte Enable Driven by Master Addr LSI53C810A Data C_BE Driven by Master PAR tean Sa gt gt Le Fs gt a I lt Sa ag aS 53 W S tO ao 2 ov Fr Or Doan 8 foe gt a 5 lt O 20 QO 25 gt lop oO rans a is is es So s Zo a 2 D a gt Bo Z 2 OB co a Z o D D D Z 2 2 2 a a a 7 15 PCI Interface Timing Diagrams Figure 7 12 Target Write CLK Driven by System FRAME Driven by Master o L n
101. ction reselection occurs during a DMA register to register operation This bit is not affected by a software reset Register 0x3C 0x3F 0xBC OxBF Adder Sum Output ADDER Read Only XIXIXIXIX XIX xX xX xXx xX xX xX xX xX xX xXx x x x Adder Sum Output 31 0 This register contains the output of the internal adder and is used primarily for test purposes The power up value for this register is indeterminate 5 47 Register 0x40 0xCO SCSI Interrupt Enable Zero SIENO Read Write 7 6 5 4 3 2 1 0 M A CMP SEL RSL SGE UDC RST PAR 0 0 0 0 0 0 0 0 This register contains the interrupt mask bits that correspond to the interrupting conditions described in the SCSI Interrupt Status Zero SISTO register An interrupt is masked by clearing the appropriate mask bit For more information on interrupts see Chapter 2 Functional Description M A SCSI Phase Mismatch Initiator Mode SCSI ATN Condition Target Mode 7 In the initiator mode this bit is set when the SCSI phase asserted by the target and sampled during SREQ does not match the expected phase in the SCSI Output Control Latch SOCL register This expected phase is automatically written by SCSI SCRIPTS In target mode this bit is set when the initiator asserts SATN See the Disable Halt on Parity Error or SATN Condition bit in the SCSI Cont
102. ctive state occurs when the signal is at a LOW voltage When the slash is absent the signal is active at a HIGH voltage Signal Descriptions Signals are assigned a type There are four signal types l Input a standard input only signal Oo Output a standard output driver typically a Totem Pole Output T S 3 state a bidirectional 3 state input output signal S T S Sustained 3 state an active LOW 3 state signal owned and driven by one and only one agent at a time Table 4 1 describes the Power and Ground Signals group Table 4 1 Power and Ground Signals Pin No Description 5 9 13 18 22 26 32 37 43 87 93 99 Power supplies to the PCI I O pins 3 16 28 40 90 Power supplies to the PCI I O pins 58 63 68 73 Power supplies to the SCSI bus I O pins 54 77 Power supplies to the SCSI bus I O pins 50 81 Power supplies to the internal logic core Power supplies to the internal logic core 1 These pins can accept a Vpp source of 3 3 or 5 V All other Vpp pins must be supplied 5 V 4 3 Figure 4 2 Functional Signal Grouping System Address and Data Interface Control Arbitration Error Reporting 4 4 CLK RST AD 31 0 C_BE 3 0 PAR FRAME TRDY IRDY STOP DEVSEL IDSEL REQ GNT PERR SERR Signal Descriptions SCLK SD 7 0 SDP SCTRL TESTIN GPIOO_FETCH GP1IO1_MASTER MAC _TESTOUT IRQ SCSI
103. d Select with ATN Table Indirect Mode Relative Address Mode L Opcode Bit 0 Opcode Bit 1 Opcode Bit 2 L 1 Instruction Type I O 0 Instruction Type I O Second 32 bit Word of the I O Instruction DSPS Register 31 30 29 28 27 26 25 24 23 22 21 2019 1817 16 15 14 13 12 11 10 9 8 76543 210 LETTE TET EE ETT 32 bit Jump Address 6 16 Instruction Set of the I O Processor Note VO Instruction Clear Instruction When the SACK or SATN bits are cleared the corresponding bits are cleared in the SCSI Output Con trol Latch SOCL register Do not set SACK or SATN except for testing purposes When the target bit is cleared the corresponding bit in the SCSI Control Zero SCNTLO register is cleared When the carry bit is cleared the corresponding bit in the ALU is cleared None of the signals are cleared on the SCSI bus in Target mode Initiator Mode OPC2 OPC1 OPCO Instruction Defined 0 0 0 Select 0 0 1 Wait Disconnect 0 1 0 Wait Reselect 0 1 1 Set 1 0 0 Clear Select Instruction 1 The LSI53C810A arbitrates for the SCSI bus by asserting the SCSI ID stored in the SCS Chip ID SCID register If it loses arbitration it tries again during the next available arbitration cycle without reporting any lost arbitration status 2 If the LSI53C810A wins arbitration it attempts to select the SCSI device whose ID is defined in the destination ID field of the instruction Once the LSI53C810A wins arbit
104. d Only Command Read Write Device ID Read Only Header Type Read Only Interrupt Line Read Write Interrupt Pin Read Only Latency Timer Read Write Max_Lat Read Only Min_Gnt Read Only Revision ID Read Only Status Read Write Vendor ID Read Only LSI53C810A PCI to SCSI I O Processor A 1 Table A 2 lists the LSI53C810A SCSI registers by register name Table A 2 SCSI Registers Register Name Adder Sum Output ADDER Address 0x3C 0x3F 0xBC OxBF Read Write Read Only Chip Test Five CTESTS5 0x22 OxA2 Read Write Chip Test Four CTEST4 0x21 OxA1 Read Write Chip Test One CTEST1 0x19 0x99 Read Only Chip Test Six CTEST6 0x23 0xA3 Read Write Chip Test Three CTEST3 0x1B 0x9B Read Write Chip Test Two CTEST2 Ox1A 0x9A Read Only Chip Test Zero CTESTO 0x18 0x98 Read Write Data Structure Address DSA 0x10 0x13 0x90 0x93 Read Write DMA Byte Counter DBC 0x24 0x26 0xA4 0xA6 Read Write DMA Command DCMD 0x27 0xA7 Read Write DMA Control DCNTL 0x3B 0xBB Read Write DMA FIFO DFIFO 0x20 0xA0 Read Write DMA Interrupt Enable DIEN 0x39 0xB9 Read Write DMA Mode DMODE 0x38 0xB8 Read Write DMA Next Address DNAD 0x28 0x2B OxA8 OxAB Read Write DMA SCRIPTS Pointer
105. d until the DMA FIFO is cleared of data These locked out SCSI interrupts are posted as soon as the DMA FIFO is empty 2 7 1 5 Halting in an Orderly Fashion When an interrupt occurs the LSI53C810A attempts to halt in an orderly fashion e If the interrupt occurs in the middle of an instruction fetch the fetch is completed except in the case of a Bus Fault Execution does not begin but the DMA SCRIPTS Pointer DSP points to the next instruction since it is updated when the current instruction is fetched 2 20 Functional Description If the DMA direction is a write to memory and a SCSI interrupt occurs the LSI53C810A attempts to flush the DMA FIFO to memory before halting Under any other circumstances only the current cycle is completed before halting so the DFE bit in DMA Status DSTAT should be checked to see if any data remains in the DMA FIFO SCSI SREQ SACK handshakes that have begun are completed before halting The LSI53C810A attempts to clean up any outstanding synchronous offset before halting In the case of Transfer Control Instructions once instruction execution begins it continues to completion before halting If the instruction is a JUMP CALL WHEN IF lt phase gt the DMA SCRIPTS Pointer DSP is updated to the transfer address before halting All other instructions may halt before completion 2 7 1 6 Sample Interrupt Service Routine The following is a sample of an interrupt service routine for the
106. determines which condition or conditions caused the DMA type interrupt and clears that DMA interrupt condition The DFE bit bit 7 in DSTAT is purely a status bit it will not generate an interrupt under any circumstances and will not be cleared when read DMA interrupts flush neither the DMA nor SCSI FIFOs before generating the interrupt so the DFE bit in the DMA Status DSTAT register should be checked after any DMA interrupt If the DFE bit is cleared then the FIFOs must be cleared by setting the CLF Clear DMA FIFO and CSF Clear SCSI FIFO bits or flushed by setting the FLF Flush DMA FIFO bit SIENO and SIEN1 The SCSI Interrupt Enable Zero SIENO and SCSI Interrupt Enable One SIEN1 registers are the interrupt enable registers for the SCSI interrupts in SCSI Interrupt Status Zero SISTO and SCSI Interrupt Status One SIST1 DIEN The DMA Interrupt Enable DIEN register is the interrupt enable register for DMA interrupts in DMA Status DSTAT DCNTL When bit 1 in the DMA Control DCNTL register is set the IRQ pin is not asserted when an interrupt condition occurs The interrupt is not lost or ignored but merely masked at the pin Clearing this bit when an interrupt is pending immediately causes the IRQ pin to assert As with any register other than ISTAT this register cannot be accessed except by a SCRIPTS instruction during SCRIPTS execution Interrupt Handling 2 17 2 7 1 2 Fatal vs Nonfatal Interrupts
107. down LSI53C810A has no effect on an active SCSI bus CMOS voltage feed through phenomena TolerANT technology provides signal filtering at the inputs of SREQ and SACK to increase immunity to signal reflections 2 6 1 Terminator Networks The terminator networks provide the biasing needed to pull signals to an inactive voltage level and to match the impedance seen at the end of the cable with the characteristic impedance of the cable Terminators must be installed at the extreme ends of the SCSI chain and only at the ends No system should ever have more or less than two terminators installed and active SCSI host adapters should provide a means of accommodating terminators There should be a means of disabling the termination SE cables can use a 220 Q pull up resistor to the terminator power supply Term Power line and a 330 Q pull down to ground Because of the high performance nature of the LSI53C810A regulated or active termination is recommended Figure 2 3 shows a Unitrode active terminator TolerANT active negation can be used with any ANSI approved termination network For additional information refer to the SCSI 2 specification 2 6 2 Select Reselect During Selection Reselection In multithreaded SCSI I O environments it is not uncommon to be selected or reselected while trying to perform selection reselection This situation may occur when a SCSI controller operating in the initiator mode tries to select a target and
108. e the third Dword is accessed in a separate ownership If the instruction is an indirect type the additional Dword is accessed in a subsequent bus ownership If the instruction is a Table Indirect Block Move the chip uses two accesses to obtain the four Dwords required in two bursts of two Dwords each Note This feature can only be used if SCRIPTS prefetching is disabled 2 4 PCI Cache Mode 2 4 The LSI53C810A supports the PCI specification for an 8 bit Cache Line Size register located in PCI configuration space The Cache Line Size register provides the ability to sense and react to nonaligned addresses corresponding to cache line boundaries In conjunction with the Cache Line Size register the PCI commands Read Line Read Multiple and Functional Description Write and Invalidate are each software enabled or disabled to allow the user full flexibility in using these commands For more information on PCI cache mode operations refer to Chapter 3 PCI Functional Description 2 4 1 Load and Store Instructions The LSI53C810A supports the Load and Store instruction type which simplifies the movement of data between memory and the internal chip registers It also enables the LSI53C810A to transfer bytes to addresses relative to the Data Structure Address DSA register For more information on the Load and Store instructions refer to Chapter 6 Instruction Set of the I O Processor 2 4 2 3 3 V 5 V PCI Interface The
109. e SCSI First Byte Received SFBR register one bit to the left and place the result in the register Syntax Move SFBR SHL RegA OR data with register and place the result in the same register Syntax Move RegA data8 to RegA XOR data with register and place the result in the same register Syntax Move RegA XOR data8 to RegA AND data with register and place the result in the same register Syntax Move RegA amp data8 to RegA OR data with register and place the result in the SCSI First Byte Received SFBR register Syntax Move RegA data8 to SFBR XOR data with register and place the result in the SCSI First Byte Received SFBR register Syntax Move RegA XOR data8 to SFBR AND data with register and place the result in the SCSI First Byte Received SFBR register Syntax Move RegA amp data8 to SFBR OR data with SFBR and place the result in the register Syntax Move SFBR data8 to RegA XOR data with SFBR and place the result in the register Syntax Move SFBR XOR data8 to RegA AND data with SFBR and place the result in the register Syntax Move SFBR amp data8 to RegA 101 Shift register one bit to the Shift register one bit to the Shift the SCSI First Byte right and place the resultin right and place the result in Received SFBR register the same register Syntax the SCSI First Byte one bit to the right and
110. e Size Register 3 3 wee Selection of Cache Line Size 3 4 3 2 3 Alignment 3 4 3 2 4 Memory Read Multiple Command 3 7 3 2 5 Unsupported PCI Commands 3 8 3 3 Configuration Registers 3 9 Chapter 4 Signal Descriptions 4 1 PCI Bus Interface Signals 4 5 4 1 1 System Signals 4 5 4 1 2 Address and Data Signals 4 6 4 1 3 Interface Control Signals 4 7 4 1 4 Arbitration Signals 4 8 4 1 5 Error Reporting Signals 4 8 4 2 SCSI Bus Interface Signals 4 9 4 2 1 SCSI Bus Interface Signals 4 9 4 2 2 Additional Interface Signals 4 10 Chapter 5 Operating Registers Chapter 6 Instruction Set of the I O Processor 6 1 Low Level Register Interface Mode 6 1 6 2 SCSI SCRIPTS 6 2 6 2 1 Sample Operation 6 3 6 3 Block Move Instructions 6 5 6 3 1 First Dword 6 6 6 3 2 Second Dword 6 12 6 4 I O Instruction 6 13 viii Contents Chapter 7 Appendix A 6 5 6 6 6 7 6 8 6 4 1 First Dword 6 4 2 Second Dword Read Write Instructions 6 5 1 First Dword 6 5 2 Second Dword 6 5 3 Read Modify Write Cycles 6 5 4 Move To From SFBR Cycles Transfer Control Instructions 6 6 1 First Dword 6 6 2 Second Dword Memory Move Instructions 6 7 1 First Dword 6 7 2 Second Dword 6 7 3 Third Dword 6 7 4 Read Write System Memory from a SCRIPTS Instruction Load and Store Instructions 6 8 1 First Dword 6 8 2 Second Dword Electrical Characteristics rA 7 2 ia 7 4 5 7 6 ia DC Characteristics TolerANT Technology AC Characteristics PCI Interface
111. e logic and the LSI53C810A monitors the cache line size using the DMA Mode DMODE register PFF Prefetch Flush 6 Setting this bit will cause the prefetch unit to flush its contents The bit clears after the flush is complete PFEN Prefetch Enable 5 Setting this bit enables the prefetch unit if the burst size is equal to or greater than four For more information on SCRIPTS instruction prefetching see Chapter 2 Func tional Description 5 45 5 46 SSM IRQM STD IRQD Single Step Mode 4 Setting this bit causes the LSI53C810A to stop after executing each SCRIPTS instruction and generate a single step interrupt When this bit is cleared the LSI53C810A does not stop after each instruction It continues fetching and executing instructions until an interrupt condition occurs For normal SCSI SCRIPTS operation keep this bit clear To restart the LSI53C810A after it generates a SCRIPTS Step interrupt read the Interrupt Status ISTAT and DMA Status DSTAT registers to recognize and clear the interrupt Then set the START DMA bit in this register IRQ Mode 3 When set this bit enables a totem pole driver for the IRQ pin When reset this bit enables an open drain driver for the IRQ pin with a internal weak pull up This bit is reset at power up Start DMA Operation 2 The LSI53C810A fetches a SCSI SCRIPTS instruction from the address contained in the DMA SCRIPTS Pointer DSP register when this bit is set This bit is req
112. ed against the SCSI First Byte Received SFBR register These bits are used in conjunction with the Data Compare Mask Field to test for a particular data value Instruction Set of the I O Processor 6 6 2 Second Dword Jump Address 31 0 This 32 bit field contains the address of the next instruction to fetch when a jump is taken Once the LSI53C810A has fetched the instruction from the address pointed to by these 32 bits this address is incremented by 4 loaded into the DMA SCRIPTS Pointer DSP register and becomes the current instruction pointer Transfer Control Instructions 6 35 6 7 Memory Move Instructions 6 36 This SCRIPTS instruction allows the LSI53C810A to execute high performance block moves of 32 bit data from one part of main memory to another In this mode the LSI53C810A is an independent high performance DMA controller irrespective of SCSI operations Since the registers of the LSI53C810A can be mapped into system memory this SCRIPTS instruction also moves an LSI53C810A register to or from memory or another LSI53C810A register For Memory Move instructions bits 5 and 4 SIOM and DIOM in the DMA Mode DMODE register determine whether the source or destination addresses reside in memory or I O space By setting these bits appropriately data may be moved within memory space within I O space or between the two address spaces The Memory Move instruction is used to copy the specified number of bytes from the so
113. ed into the DMA Command DCMD and DMA Byte Counter DBC registers the second into the DMA SCRIPTS Pointer Save DSPS register The third word used only by Memory Move instructions is loaded into the Temporary TEMP shadow register In an indirect I O or Move instruction the first two 32 bit opcode fetches are followed by one or two more 32 bit fetch cycles 6 2 1 Sample Operation This sample operation describes execution of a SCRIPTS instruction for a Block Move instruction e The host CPU through programmed I O gives the DMA SCRIPTS Pointer DSP register in the Operating register file the starting address in main memory that points to a SCSI SCRIPTS program for execution e Loading the DMA SCRIPTS Pointer DSP register causes the LSI53C810A to request use of the PCI bus to fetch its first instruction from main memory at the address just loaded SCSI SCRIPTS 6 3 6 4 e The LSI53C810A typically fetches two Dwords 64 bits and decodes the high order byte of the first Dword as a SCRIPTS instruction If the instruction is a Block Move the lower three bytes of the first Dword are stored and interpreted as the number of bytes to be moved The second Dword is stored and interpreted as the 32 bit beginning address in main memory to which the move is directed e For a SCSI send operation the LSI53C810A waits until there is enough space in the DMA FIFO to transfer a programmable size block of data For a SCSI receive operation
114. ed on the SCSI bus this bit must be cleared and the chip must be connected to at least a 40 MHz external SCLK SISO SCSI Isolation Mode 6 This bit allows the LSI53C810A to put the SCSI bidirectional and input pins into a low power mode when the SCSI bus is not in use When this bit is set the SCSI bus inputs are logically isolated from the SCSI bus R Reserved 5 0 5 61 Register Ox4E OxCE SCSI Test Two STEST2 Read Write 7 6 5 4 3 2 1 0 acs cs Cara o o o o ole SCE SCSI Control Enable 7 Setting this bit allows assertion of all SCSI control and data lines through the SCSI Output Control Latch SOCL and SCSI Output Data Latch SODL registers regardless of whether the LSI53C810A is configured as a target or initiator Note Do not set this bit during normal operation since it could cause contention on the SCSI bus It is included for diagnostic purposes only ROF Reset SCSI Offset 6 Setting this bit clears any outstanding synchronous SREQ SACK offset Set this bit if a SCSI gross error condition occurs and to clear the offset when a synchronous transfer does not complete successfully The bit automatically clears itself after resetting the synchronous offset R Reserved 5 SLB SCSI Loopback Mode 4 Setting this bit allows the LSI53C810A to perform SCSI loopback diagnostics That is it enables the SCSI core to simultaneously perform as both the initiator and the target SZM SCSI High Impedance Mode
115. egister 5 45 DMA core 2 2 DMA direction bit 5 37 DMA FIFO 2 8 DMA FIFO bits 5 37 DMA FIFO empty bit 5 21 DMA FIFO register 5 33 DMA interrupt enable register 5 44 DMA interrupt pending bit 5 29 DMA mode register 5 41 DMA next address register 5 39 DMA SCRIPTS pointer register 5 39 DMA SCRIPTS pointer save register 5 40 DMA status register 5 20 IX 2 Index DMODE register 5 41 DNAD register 5 39 DRD bit 5 56 DREQ bit 5 31 DSA register 5 26 DSI bit 5 64 DSP register 5 39 DSPS register 5 40 DSTAT register 5 20 E ease of use 1 4 enable parity checking bit 5 5 enable read line bit 5 42 enable read multiple bit 5 43 enable response to reselection bit 5 11 enable response to selection bit 5 11 encoded destination SCSI ID bits 5 15 5 19 EPC bit 5 5 ERL bit 5 42 EXC bit 5 6 EXT bit 5 63 extend SREQ SACK filtering bit 5 63 extra clock cycle of data setup bit 5 6 F FBL 2 0 bits 5 36 fetch enable bit 5 57 fetch opcode bursting 2 4 FF 3 0 bits 5 24 FFL 3 0 bits 5 30 FIFO byte control bits 5 36 FIFO flags bits 5 24 FMT 3 0 bits 5 30 FRAME 4 7 function complete bit 5 48 5 51 G GEN bit 5 50 5 54 GEN 3 0 bits 5 58 general purpose bits 5 16 general purpose pin control register 5 56 general purpose register 5 16 general purpose timer expired bit 5 50 5 54 general purpose timer period bits 5 58 GNT 4 8 GPCNTL register 5 56 GPIO enable bits 5 57 GPIO 1 0 bits 5 16 GPIO_EN 1 0 bits 5 5
116. egisters 0x58 0xD8 SCSI Bus Data Lines SBDL Read Only 15 0 SBDL x x x X X x X x X X x X x X x X SBDL SCSI Bus Data Lines 15 0 This register contains the SCSI data bus status Even though the SCSI data bus is active low these bits are active high The signal status is not latched and is a true representation of exactly what is on the data bus at the time the register is read This register is used when receiving data using programmed I O This register can also be used for diagnostic testing or in low level mode The power up value of this register is indeterminate Operating Registers Chapter 6 Instruction Set of the I O Processor This chapter is divided into the following sections e Section 6 1 Low Level Register Interface Mode e Section 6 2 SCSI SCRIPTS e Section 6 3 Block Move Instructions e Section 6 4 I O Instruction e Section 6 5 Read Write Instructions e Section 6 6 Transfer Control Instructions e Section 6 7 Memory Move Instructions e Section 6 8 Load and Store Instructions After power up and initialization the LSI53C810A can be operated in the low level register interface mode or using SCSI SCRIPTS 6 1 Low Level Register Interface Mode With the low level register interface mode the user has access to the DMA control logic and the SCSI bus control logic An external processor has acce
117. enerated Encoded SCSI Destination ID 18 16 This 3 bit field specifies the destination SCSI ID for an I O instruction Set Clear Carry 10 This bit is used in conjunction with a Set or Clear instruction to set or clear the Carry bit Setting this bit with a Set instruction asserts the Carry bit in the ALU Setting this bit with a Clear instruction deasserts the Carry bit in the ALU Set Clear Target Mode 9 This bit is used in conjunction with a Set or Clear instruction to set or clear Target mode Setting this bit with a Set instruction configures the LSI53C810A as a target device this sets bit 0 of the SCSI Control Zero SCNTLO register Clearing this bit with a Clear instruction configures the LSI53C810A as an Initiator device this clears bit O of the SCSI Control Zero SCNTLO register 6 21 6 4 2 Second Dword 6 22 ACK ATN R SA Set Clear SACK 6 Set Clear SATN 3 These two bits are used in conjunction with a Set or Clear instruction to assert or deassert the corresponding SCSI control signal Bit 6 controls the SCSI SACK signal Bit 3 controls the SCSI SATN signal Setting either of these bits sets or resets the corresponding bit in the SCSI Output Control Latch SOCL register depending on the instruction used The Set instruction is used to assert SACK and or SATN on the SCSI bus The Clear instruction is used to deassert SACK and or SATN on the SCSI bus Since SACK and SATW are Initiator s
118. er from the 7 bit value of the DMA FIFO DFIFO register AND the result with 0x7F for a byte count between zero and 80 Read bit 5 in the SCSI Status Zero SSTATO register to determine if any bytes are left in the SCSI Output Data Latch SODL register If bit 5 is set in SSTATO then the SODL register is full Synchronous SCSI Send Step 1 Step 2 Step 3 Look at the DMA FIFO DFIFO and DMA Byte Counter DBC registers and calculate if there are bytes left in the DMA FIFO To make this calculation subtract the seven least significant bits of the DMA Byte Counter DBC register from the 7 bit value of the DMA FIFO DFIFO register AND the result with 0x7F for a byte count between zero and 80 Read bit 5 in the SCSI Status Zero SSTATO register to determine if any bytes are left in the SCSI Output Data Latch SODL register If bit 5 is set in SSTATO then the SCSI Output Data Latch SODL register is full Read bit 6 in the SCSI Status Zero SSTATO register to determine if any bytes are left in the SODR register If bit 6 is set in SSTATO then the SODR register is full Asynchronous SCSI Receive Step 1 Look at the DMA FIFO DFIFO and DMA Byte Counter DBC registers and calculate if there are bytes left in the DMA FIFO To make this calculation subtract the seven least significant bits of the DMA Byte Counter DBC register from the 7 bit value of the DMA FIFO DFIFO register AND the result with 0x7F for
119. er performs a bytewise longitudinal parity check on all SCSI data received or sent through the SCSI core If one of the bytes received or sent usually the last is the set of correct even parity bits SCSI Longitudinal Parity SLPAR should go to zero assuming it started at zero AS an example suppose that the following three data bytes and one check byte are received from the SCSI bus all signals are shown active HIGH Operating Registers Data Bytes Running SLPAR 7 00000000 1 11001100 11001100 XOR of word 1 2 01010101 10011001 XOR of word 1 and 2 3 00001111 10010110 XOR of word 1 2 and 3 Even parity gt gt gt 10010110 4 10010110 00000000 A one in any bit position of the final SCSI Longitudinal Parity SLPAR value would indicate a transmission error The SCSI Longitudinal Parity SLPAR register is also used to generate the check bytes for SCSI send operations If the SCSI Longitudinal Parity SLPAR register contains all zeros prior to sending a block move it contains the appropriate check byte at the end of the block move This byte must then be sent across the SCSI bus Note Writing any value to this register resets it to zero The longitudinal parity checks are meant to provide an added measure of SCSI data integrity and are entirely optional This register does not latch SCSI selection reselection IDs under any circumstances The default value of this register is zero
120. g 5 63 extra clock cycle of data setup 5 6 fetch enable 5 57 fetch pin mode 5 32 FIFO byte control 5 36 FIFO flags 5 24 flush DMA FIFO 5 32 function complete 5 48 5 51 general purpose timer expired 5 50 5 54 general purpose timer period 5 58 GPIO enable 5 57 GPIO 1 0 5 16 halt SCSI clock 5 64 handshake to handshake timer expired 5 50 5 54 handshake to handshake timer period 5 57 high impedance mode 5 35 illegal instruction detected 5 22 5 44 immediate arbitration 5 7 interrupt on the fly 5 28 IRQ disable 5 46 IRQ mode 5 46 last disconnect 5 25 latched SCSI parity 5 24 lost arbitration 5 23 LSI53C700 family compatibility 5 47 manual start mode 5 43 master control for set or reset pulses 5 37 master data parity error 5 21 5 44 master enable 5 56 master parity error enable 5 35 max SCSI synchronous offset 5 14 parity error 5 53 phase mismatch or SATN active 5 51 pointer SCRIPTS 5 56 prefetch enable 5 45 prefetch flush 5 45 reselected 5 48 5 52 reset SCSI offset 5 62 SACK status 5 20 SATN status 5 20 SBSY status 5 20 SC_D status 5 20 SCLK 5 61 SCRIPTS 5 56 IX 5 SCRIPTS interrupt instruction received 5 21 5 44 SCSI C_D signal 5 25 SCSI control enable 5 62 SCSI data high impedance 5 35 SCSI disconnect unexpected 5 9 SCSI FIFO test read 5 64 SCSI FIFO test write 5 65 SCSI gross error 5 48 5 52 SCSI high impedance mode 5 62 SCSI _O signal 5 25 SCSI interrupt pending 5 28 SCSI isol
121. g this bit aborts the current operation being executed by the LSI53C810A If this bit is set and an interrupt is received clear this bit before reading the DMA Status DSTAT register to prevent further aborted interrupts from being generated The sequence to abort any operation is 1 Set this bit 2 Wait for an interrupt Operating Registers SRST SIGP SEM 3 Read the Interrupt Status ISTAT register 4 If the SCSI Interrupt Pending bit is set then read the SCSI Interrupt Status Zero SISTO or SCSI Interrupt Status One SIST1 register to determine the cause of the SCSI Interrupt and go back to Step 2 5 If the SCSI Interrupt Pending bit is clear and the DMA Interrupt Pending bit is set then write 0x00 value to this register 6 Read the DMA Status DSTAT register to verify the aborted interrupt and to see if any other interrupting conditions have occurred Software Reset 6 Setting this bit resets the LSI53C810A All operating registers are cleared to their respective default values and all SCSI signals are deasserted Setting this bit does not assert the SCSI RST signal This reset does not clear the LSI53C700 family compatibility bit or any of the PCI configuration registers This bit is not self clearing it must be cleared to clear the reset condition a hardware reset also clears this bit Signal Process 5 SIGP is a R W bit that is writable at any time and polled and reset using Chip Test Two CTEST2
122. generate parity errors to test error handling functions Immediate Arbitration 1 Setting this bit causes the SCSI core to immediately begin arbitration once a Bus Free phase is detected following an expected SCSI disconnect This bit is useful for multithreaded applications The ARB 1 0 bits in SCSI Control Zero SCNTLO register are set for full arbitration and selection before setting this bit Arbitration is retried until won At that point the LSI53C810A holds BSY and SEL asserted and waits for a select or reselect sequence The Immediate Arbitration 5 7 5 8 SST bit is cleared automatically when the selection or reselection sequence is completed or times out Interrupts do not occur until after this bit is reset An unexpected disconnect condition clears ARB without it attempting arbitration See the SCSI Disconnect Unexpected bit SCSI Control Two SCNTL2 bit 7 for more information on expected versus unexpected disconnects It is possible to abort an immediate arbitration sequence First set the Abort bit in the Interrupt Status ISTAT register Then one of two things eventually happens e The Won Arbitration bit SCSI Status Zero SSTATO bit 2 will be set In this case the Immediate Arbitration bit needs to be cleared This completes the abort sequence and disconnects the LSI53C810A from the SCSI bus If it is not acceptable to go to Bus Free phase immediately following the arbitration phase it is possible
123. gle step mode or automatically executing SCSI SCRIPTS Any of the following conditions during instruction execution also set this bit e The LSI53C810A is executing a Wait Disconnect instruction and the SCSI REQ line is asserted without a disconnect occurring e A Move Chained Move or Memory Move command with a byte count of zero is fetched e A Load Store memory address maps back into chip register space Register 0x0D 0x8D SCSI Status Zero SSTATO Read Only 7 6 5 4 3 2 1 0 ILF ORF OLF AIP LOA WOA RST SDP 0 0 0 0 0 0 0 0 ILF SIDL Full 7 This bit is set when the SCSI Input Data Latch SIDL register contains data Data is transferred from the SCSI bus to the SCSI Input Data Latch register before being sent to the DMA FIFO and then to the host bus The SCSI Input Data Latch SIDL register contains SCSI data received asynchronously Synchronous data received does not flow through this register ORF SODR Full 6 This bit is set when the SCSI Output Data Register SODR a hidden buffer register which is not accessible contains data The SODR register is used by the SCSI logic as a second storage register when sending data synchronously It is not readable or writable by the user It is possible to use this bit to determine how many bytes reside in the chip when an error occurs 5 22 Operating Registers OLF AIP LOA WOA RST SDP SODL Full 5 This bit is set when SCSI Output Data Latch SODL contain
124. gt a D 2 a Byte Enable Driven by Master PAR Driven by Master IRDY Driven by Master TRDY Driven by LSI53C810A STOP Driven by LSI53C810A a gt ws CS Wwe Aw N il p gt a C oO 2 a Electrical Characteristics 7 16 7 4 2 Initiator Timing Figure 7 13 through Figure 7 18 describe initiator timing Figure 7 13 OpCode Fetch Nonburst CLK E o g D gt n gt a ic D 2 IT Oo lu 8 LG of So A OF oO 2 a GPIO1_MASTER Driven by LSI53C810A REQ Driven by LSI53C810A GNT Driven by Arbiter FRAME Driven by LSI53C810A ats lu Lon m vQ o oo Be D Ir E a3 at cx 2 a Driven by LSI53C810A io ow Bo L oO ro 6 2 ne J z ae 25 si a Driven by LSI53C810A Driven by Target Driven by Target DEVSEL Driven by Target 7 17 PCI Interface Timing Diagrams Figure 7 14 Burst Opcode Fetch CLK Driven by System gt _ I lt Os Lig L9 ef Sa o gt Os i D 2 a cx tk x zg 219 0 o as Oc D 2 a REQ Driven by LSI53C810A Driven by Arbiter FRAME Driven by LSI53C810A AD Driven by LSI53C810A Addr Target Data C_BE Driven by LSI53C810A PAR lt x S Q QO oO 19 N gt a p D S T o Q o oO D c Ke pe lt Driven by LSI53C810A Dr
125. haracteristics for SE SCSI signals Figure 7 1 through Figure 7 5 show the effect of TolerANT technology on the DC characteristics of the chip Electrical Characteristics Table 7 12 TolerANT Technology Electrical Characteristics Parameter Output high voltage Test Conditions lou 2 5 mA Output low voltage loL 48 mA Input high voltage Input low voltage Referenced to Vss Input clamp voltage Vpp 4 75 I 20 mA Threshold HIGH to LOW Threshold LOW to HIGH Hysteresis Output high current Voy 2 5 V Output low current VoL 0 5 V Short circuit output high current Output driving low pin shorted to Vpp supply Short circuit output low current Output driving high pin shorted to Vss supply Input high leakage 0 5 lt Vpp lt 5 25 Vpn 2 7 V Input low leakage 0 5 lt Vpp lt 5 25 Vpin 0 5 V Input resistance Capacitance per pin SCSI pins PQFP Rise time 10 to 90 Figure 7 1 Fall time 90 to 10 Figure 7 1 Slew rate LOW to HIGH Figure 7 1 Slew rate HIGH to LOW Figure 7 1 Electrostatic discharge MIL STD 883C 3015 7 Latch up Filter delay Figure 7 2 Extended filter delay Figure 7 2 1 Active negation outputs only Data Parity SREQ SACK 2 Single pin only irreversible damage may occur if sustained for one second 3 SCSI RESET pin has
126. he Interrupt Status ISTAT is set but the IRQ pin is not asserted When the chip is initialized enable all fatal interrupts if you are using hardware interrupts If a fatal interrupt is disabled and that interrupt condition occurs the SCRIPTS halt and the system never knows it unless it times out and checks the ISTAT after a certain period of inactivity If you are polling the ISTAT instead of using hardware interrupts then masking a fatal interrupt makes no difference since the SIP and DIP bits in the Interrupt Status ISTAT inform the system of interrupts not the IRQ pin Masking an interrupt after IRQ is asserted does not cause deassertion of IRQ 2 7 1 4 Stacked Interrupts The LSI53C810A will stack interrupts if they occur one after the other If the SIP or DIP bits in the ISTAT register are set first level then there is already at least one pending interrupt and any future interrupts are stacked in extra registers behind the SCSI Interrupt Status Zero SISTO SCSI Interrupt Status One SIST1 and DMA Status DSTAT registers second level When two interrupts have occurred and the two levels of the stack are full any further interrupts set additional bits in the extra registers behind SCSI Interrupt Status Zero SISTO SCSI Interrupt Status One SIST1 and DMA Status DSTAT When the first level of Interrupt Handling 2 19 interrupts are cleared all the interrupts that came in afterward move into SISTO SIST1
127. hip Test Three CTESTS3 register and bit 4 WIE in the PCI Command register are set When the following conditions are met Memory Write and Invalidate commands are issued e The CLSE bit Cache Line Size Enable bit 7 DMA Control DCNTL register WRIE bit Write and Invalidate Enable bit 0 Chip Test Three CTESTS register and PCI configuration Command register bit 4 are set e The Cache Line Size register contains a legal burst size 2 4 8 or 16 value AND that value is less than or equal to the DMA Mode DMODE burst size e The chip has enough bytes in the DMA FIFO to complete at least one full cache line burst e The chip is aligned to a cache line boundary When these conditions are met the LSI53C810A issues a Write and Invalidate command instead of a Memory Write command during all PCI write cycles Multiple Cache Line Transfers When multiple cache lines of data have been read in during a MMOV instruction see the description for the Read Multiple command the LSI53C810A issues a Write and Invalidate command using the burst size necessary to transfer all the data in one transfer For example if the cache line size is 4 and the chip read in 16 Dwords of data using a Read Multiple command the chip switches the burst size to 16 and issues a Write and Invalidate to transfer all 16 Dwords in one bus ownership Latency In accordance with the PCI specification the latency timer is ignored when issuing a Write a
128. ible IDs in descending order is Highest Lowest 7 6 5 4 3 2 1 0 Register 0x05 0x85 SCSI Transfer SXFER Read Write 7 5 4 3 0 TP 2 0 R MO 3 0 0 0 0 x 0 0 0 0 When using Table Indirect I O commands bits 7 0 of this register are loaded from the I O data structure Note For additional information on how the synchronous transfer rate is determined refer to Chapter 2 Functional Descrip tion TP 2 0 SCSI Synchronous Transfer Period 7 5 These bits determine the SCSI synchronous transfer period XFERP used by the LSI53C810A when sending synchronous SCSI data in either the initiator or target mode These bits control the programmable dividers in the chip Operating Registers ee ee ae Use the following formula to calculate the synchronous send and receive rates Table 5 3 and Table 5 4 show examples of possible bit combinations Synchronous Send Rate SCLK SCF XFERP Synchronous Receive Rate SCLK SCF 4 Where SCLK SCSI clock SCF Synchronous Clock Conversion Factor SCNTLS3 register bits 6 4 XFERP Transfer period SXFER register bits 7 5 Table 5 3 Examples of Synchronous Transfer Periods and Rates for SCSI 1 Synch SCF XFERP Synch Synch Receive Synch SCLK SCNTL3 SXFER_ Send Rate Send Rate Receive MHz Bits 6 4 Bits 7 5 Mbytes s Period ns Mbytes s Period ns 66 67 3 4 5 55 180 5 55 180 3 5 4 5 5 13 Table 5 3
129. icate that the device has no major requirements for the settings of Latency Timers The LSI53C810A sets the Max_Lat register to 0x40 Configuration Registers 3 19 3 20 PCI Functional Description Chapter 4 Signal Descriptions This chapter presents the LSI53C810A pin configuration and signal definitions using tables and illustrations Figure 4 1 is the pin diagram and Figure 4 2 is a functional signal grouping The pin definitions are presented in Table 4 1 through Table 4 8 The LSI53C810A is pin for pin compatible with the LSI53C810 This chapter is divided into the following sections e Section 4 1 PCI Bus Interface Signals e Section 4 2 SCSI Bus Interface Signals LSI53C810A PCI to SCSI I O Processor 4 1 Figure 4 1 LSI53C810A Pin Diagram AD21 80 EA CLK AD20 RST PA l SERR AD19 77 c pp 8 a 76 spo ADI8 5 sp1 AD17 5 sp2 AD16 73 Vss S me 5 sp3 C_BE2 Soe FRAME ne IRDY ee ey LSI53C810A spy ay 100 pin 5 spp L satiny oes Quad Flat Pack h sesy Vee 63 EI Vg S PERR Sy PAR 5 SRST C_BE1 Sein eS ae 5 ssev AD15 peepee ea AD14 pe AD13 56 5 SREQ a 55 sio AD12 T ve MAC _TESTOUT AD11 5 TESTIN AD10 1 SCLK a rTAMTNORDMROKYTANTNONWDADS MOMMOMMNNMNMNNANYTTTTTTTTTTO TOSTAAT O AFP 2 YBE58 204 488 aLI IMt qt tVMecOcqvedq GLOW Y gt gt gt gt a Ee gt Wa gt oO we o2 Or ao Ooo o A slash at the end of the signal name indicates that the a
130. ied code directly into memory To make sure that the chip executes all recent modifications the prefetch unit flushes its contents and loads the modified code every time a MMOV instruction is issued To avoid inadvertently flushing Prefetching SCRIPTS Instructions 2 3 the prefetch unit contents use the No Flush Memory to Memory Move NFMMOV instruction for all MMOV operations that do not modify code within the next 4 to 8 Dwords For more information on this instruction refer to Chapter 6 Instruction Set of the I O Processor e On every Store instruction The Store instruction may also be used to place modified code directly into memory To avoid inadvertently flushing the prefetch unit contents use the No Flush option for all Store operations that do not modify code within the next 8 Dwords e On every write to the DMA SCRIPTS Pointer DSP register e On all Transfer Control instructions when the transfer conditions are met This is necessary because the next instruction to execute is not the sequential next instruction in the prefetch unit e When the Prefetch Flush bit DMA Control DCNTL bit 6 is set The unit flushes whenever this bit is set The bit is self clearing 2 3 1 Opcode Fetch Burst Capability Setting the Burst Opcode Fetch Enable bit bit 1 in the DMA Mode DMODE register 0x38 causes the LSI53C810A to burst in the first two Dwords of all instruction fetches If the instruction is a Memory to Memory Mov
131. ignals they are not asserted on the SCSI bus unless the LSI53C810A is operating as an Initiator or the SCSI Loopback Enable bit is set in the SCSI Test Two STEST2 register The Set Clear SCSI ACK ATN instruction is used after message phase Block Move operations to give the Initiator the opportunity to assert attention before acknowledging the last message byte For example if the initiator wishes to reject a message it issues an Assert SCSI ATN instruction before a Clear SCSI ACK instruction Reserved 2 0 Start Address 31 0 This 32 bit field contains the memory address to fetch the next instruction if the selection or reselection fails If relative or table relative addressing is used this value is a 24 bit signed offset relative to the current DMA SCRIPTS Pointer DSP register value Instruction Set of the I O Processor 6 5 Read Write Instructions The Read Write instruction type moves the contents of one register to another or performs arithmetic operations such as AND OR XOR Addition and Shift 6 5 1 First Dword IT 1 0 OPC 2 0 O 2 0 A 6 0 6 5 2 Second Dword Instruction Type Read Write Instruction 31 30 The Read Write instruction uses operator bits 26 through 24 in conjunction with the opcode bits to determine which instruction is currently selected OpCode 29 27 The combinations of these bits determine if the instruction is a Read Write or an I O instruction Opcodes 0b000 through 0b
132. in the Temporary TEMP register is returned to the DMA SCRIPTS Pointer DSP register The LSI53C810A does not check to see whether the Call instruction has already been executed It does not generate an interrupt if a Return instruction is executed without previously executing a Call instruction Transfer Control Instructions 6 29 Figure 6 5 illustrates the register bit values that represent a Transfer Control instruction Figure 6 5 Transfer Control Instruction lt DCMD Register DBC Register 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 1413121110 9 8 7 6 5 4 3 2 1 Mask for Compare Data to be compared with the SCSI First Wait for Valid Phase Byte Received Compare Phase Compare Data Jump if True 1 False 0 Interrupt on the Fly Carry Test 0 Reserved Relative Addressing Mode VO C D MSG Opcode Bit 0 Opcode Bit 1 Opcode Bit 2 1 Instruction Type Transfer Control 0 Instruction Type Transfer Control DSPS Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 543 210 6 30 Instruction Set of the I O Processor SCSIP 2 0 If the comparisons are false the LSI53C810A fetches the next instruction from the address pointed to by the DMA SCRIPTS Pointer DSP register and the instruction pointer is not modified Interrupt Instruction The LSI53C810A can do a true false comparison of the ALU carry bit or compare the phase and
133. ingle memory cycle The Read Line Mode function in the LSI53C810A takes advantage of the PCI 2 1 specification regarding issuing this command The functionality of the Enable Read Line bit bit 3 in DMA Mode DMODE resembles the Write and Invalidate mode in terms of conditions that must be met before a Read Line command is issued However the Read Line option operates exactly like the previous LSI53C8XX chips when cache mode has been disabled by a CLSE bit reset or when certain conditions exist in the chip explained below The Read Line mode is enabled by setting bit 3 in the DMA Mode DMODE register If cache mode is disabled Read Line commands are issued on every read data transfer except opcode fetches PCI Functional Description If cache mode is enabled a Read Line command is issued on all read cycles except opcode fetches when the following conditions are met e The CLSE Cache Line Size Enable bit 7 DMA Control DCNTL register and ERL Enable Read Line bit 3 DMA Mode DMODE register bits are set e The Cache Line Size register must contain a legal burst size value 2 4 8 or 16 and that value is less than or equal to the DMA Mode DMODE burst size e The number of bytes to be transferred at the time a cache boundary is reached must be equal to or greater than a full cache line size e The chip is aligned to a cache line boundary When these conditions are met the chip issues a Read Line command instead of a
134. interrupts DFE DMA FIFO Empty 7 This status bit is set when the DMA FIFO is empty It is possible to use it to determine if any data resides in the FIFO when an error occurs and an interrupt is generated This bit is a pure status bit and does not cause an interrupt MDPE Master Data Parity Error 6 This bit is set when the LSI53C810A as a master detects a data parity error or a target device signals a parity error during a data phase This bit is completely disabled by the Master Parity Error Enable bit bit 3 of Chip Test Four CTEST4 BF Bus Fault 5 This bit is set when a PCI bus fault condition is detected A PCI bus fault can only occur when the LSI53C810A is bus master and is defined as a cycle that ends with a Bad Address or Target Abort Condition ABRT Aborted 4 This bit is set when an abort condition occurs An abort condition occurs when a software abort command is issued by setting bit 7 of the Interrupt Status ISTAT register SSI Single Step Interrupt 3 If the Single Step Mode bit in the DMA Control DCNTL register is set this bit is set and an interrupt is generated after successful execution of each SCRIPTS instruction SIR SCRIPTS Interrupt Instruction Received 2 This status bit is set whenever an Interrupt instruction is evaluated as true 5 21 R Reserved 1 IID Illegal Instruction Detected 0 This status bit is set any time an illegal instruction is detected whether the LSI53C810A is operating in sin
135. is reselected by another The Select SCRIPTS instruction has an alternate address to which the SCRIPTS will jump when this situation occurs The analogous situation for target devices is being selected while trying to perform a reselection SCSI Bus Interface 2 11 2 12 Once a change in operating mode occurs the initiator SCRIPTS should start with a Set Initiator instruction or the target SCRIPTS should start with a Set Target instruction The Selection and Reselection Enable bits SCSI Chip ID SCID bits 5 and 6 respectively should both be asserted so that the LSI53C810A may respond as an initiator or as a target If only selection is enabled the LSI53C810A cannot be reselected as an initiator There are also status and interrupt bits in the SCSI Interrupt Status Zero SISTO and SCSI Interrupt Enable Zero SIENO registers respectively indicating that the LSI53C810A has been selected bit 5 or reselected bit 4 Figure 2 3 Active or Regulated Termination UC5601QP gt 2 REG_OUT JER SDO J1 2 TERML2 SD1 J1 4 TERML3 SD2 J1 6 C1 C2 TERML4 SD3 J1 8 TERML5 SD4 J1 10 S TERML6 SD5 J1 12 TERML7 SD6 J1 14 TERML8 SD7 J1 16 TERML9 SD8 J1 18 TERML10 3 ATN J1 32 TERML11 4 BSY J1 36 TERML12 5 ACK J1 38 TERML13 6 RST J1 40 TERML14 7 MSG J1 42 TERML15 8 SEL J1 44 TERML17 10 REQ J1 48 V TERML18 11 1O J1 50 Note 1 C1 10 uF SMT 2 C2 0 1 yF SMT 3 J1 68 pin high density P connect
136. ister Ox4A OxCA Response ID RESPID Read Write RESPID Response ID 7 0 This register contains the IDs that the chip responds to on the SCSI bus Each bit represents one possible ID with the most significant bit representing ID 7 and the least significant bit representing ID 0 The SCSI Chip ID SCID register still contains the chip ID used during arbitration The chip can respond to more than one ID because more than one bit can be set in the Response ID RESPID register However the chip can arbitrate with only one ID value in the SCSI Chip ID SCID register 5 59 5 60 Register Ox4C OxCC SCSI Test Zero STESTO Read Only SSAID SLT ART SOZ SOM SLT ART SOZ x x 0 x 1 1 Reserved 7 SCSI Selected As ID 6 4 These bits contain the encoded value of the SCSI ID that the LSI53C810A is selected or reselected as during a SCSI selection or reselection phase These bits are read only and contain the encoded value of 0 7 possible IDs that could be used to select the LSI53C810A During a SCSI selection or reselection phase when a valid ID has been put on the bus and the LSI53C810A responds to that ID the selected as ID is written into these bits Selection Response Logic Test 3 This bit is set when the LSI53C810A is ready to be selected or reselected This does not take into account the bus settle delay of 400 ns This bit is used for functional test and fault purposes Arbitration Priority E
137. ister returns the status of the various interrupt conditions whether they are enabled in the SCSI Interrupt Enable One SIEN1 register or not Each bit that is set indicates an occurrence of the corresponding condition Reading the SCSI Interrupt Status One SIST1 register clears the interrupt condition 5 53 5 54 STO GEN HTH Reserved 7 3 Selection or Reselection Time out 2 When the SCSI device which the LSI53C810A is attempting to select or reselect does not respond within the programmed time out period See the description of the SCSI Timer Zero STIMEO register bits 3 0 for more information on the time out timer General Purpose Timer Expired 1 This bit is set when the general purpose timer expires The time measured is the time between enabling and disabling of the timer See the description of the SCSI Timer One STIME1 register bits 3 0 for more information on the general purpose timer Handshake to Handshake Timer Expired 0 This bit is set when the handshake to handshake timer expires The time measured is the SCSI Request to Request target or Acknowledge to Acknowledge initiator period See the description of the SCSI Timer Zero STIMEO register bits 7 4 for more information on the handshake to handshake timer Register 0x44 0xC4 SCSI Longitudinal Parity GLPAR Read Write 7 0 SLPAR X XxX X x x x X SLPAR SCSI Longitudinal Parity 7 0 This regist
138. it waits until enough data is collected in the DMA FIFO for transfer to memory At this point the LSI53C810A requests use of the PCI bus again to transfer the data e When the LSI53C810A is granted the PCI bus it executes as a bus master a burst transfer programmable size of data decrements the internally stored remaining byte count increments the address pointer and then releases the PCI bus The LSI53C810A stays off the PCI bus until the FIFO can again hold for a write or has collected for a read enough data to repeat the process The process repeats until the internally stored byte count has reached zero The LSI53C810A releases the PCI bus and performs another SCRIPTS instruction fetch cycle using the incremented stored address maintained in the DMA SCRIPTS Pointer DSP register Execution of SCRIPTS instructions continues until an error condition occurs or an interrupt SCRIPTS instruction is received At this point the LSI53C810A interrupts the host CPU and waits for further servicing by the host system It can execute independent Block Move instructions specifying new byte counts and starting locations in main memory In this manner the LSI53C810A performs scatter gather operations on data without requiring help from the host program generating a host interrupt or requiring an external DMA controller to be programmed Figure 6 1 illustrates a SCRIPTS Initiator Write operation which uses several Block Move instructions I
139. ite 7 6 5 4 3 2 0 BDIS ZMOD ZSD SRTM MPEE FBL 2 0 0 0 0 0 0 0 0 0 BDIS Burst Disable 7 When set this bit causes the LSI53C810A to perform back to back cycles for all transfers When this bit is cleared back to back transfers for opcode fetches and burst transfers for data moves are performed The handling of opcode fetches is dependent on the setting of the Burst Opcode Fetch bit in the DMA Mode DMODE register Operating Registers ZMOD ZSD SRTM MPEE High Impedance Mode 6 Setting this bit causes the LSI53C810A to place all output and bidirectional pins into a high impedance state In order to read data out of the LSI53C810A clear this bit This bit is intended for board level testing only Do not set this bit during normal system operation SCSI Data High Impedance 5 Setting this bit causes the LSI53C810A to place the SCSI data bus SD 7 0 and the parity line SDP in a high impedance state In order to transfer data on the SCSI bus clear this bit Shadow Register Test Mode 4 Setting this bit allows access to the shadow registers used by Memory to Memory Move operations When this bit is set register accesses to the Temporary TEMP and Data Structure Address DSA registers are directed to the shadow copies STEMP Shadow TEMP and SDSA Shadow DSA The registers are shadowed to prevent them from being overwritten during a Memory to Memory Move operation The DSA and Temporary TEMP registers contain the base add
140. iven by Target Driven by Target DEVSEL Driven by Target Electrical Characteristics 7 18 Figure 7 15 Back to Back Read CLK eo re o OC mn Fo E oy oe o 2 g3 S a2 2 Oc a S a Iae oy rac fet a lt cs gs E amp om 2 OS S 19 4 OF 5 aoc S og a a 3 DT ots 22 lt 8 Q Io oT lt 8 33 gt LW wo aie xe a a c a a 5 a3 c ce a g g i a a hje C_BE Driven by LSI53C810A Driven by LSI53C810A gt lt AS Q ee oO g g EI gt no Ss a D 2 Z a as Sg mg gt D 0 2 cy Fe D5 rls Oe fh T ne Cc g g fa g 7 19 PCI Interface Timing Diagrams Figure 7 16 Back to Back Write CLK Driven by System 355 Fa Eo LG ow O as O 2 ay l me gt a N gt z gt lt x T an o gt F mS GS 78 5 25 oS 5 5S 58 SB BB Eo mo ORs Lon lo Oo cs F OF no Q z co O OQ O FAO FE YO gt A Q L op op op op z Lu s 2 1 gt ne re ie ne o re gt As 12 n 2 n n n n n oa rl a c l pa l l a c 5 OF Fey 5 5 rey 5 Foy 2 g 2 T 2 2 G8 g a g S g S g z aq a fa a fa fa fa Electrical Characteristics 7 20 This page intentionally left blank PCI Interface Timing Diagrams 7 21 CLK Figure 7 17 Burst Read e ON EAE E STNA ee g oy y Soe Sie E E aE ESEE REEE ical NS ded Neotel Dore apa eae ee ete adeg i j i ME cen Sell eee EEA
141. l Jump instruction allows you to write SCRIPTS that make decisions based on real time conditions on the SCSI bus such as phase or data This instruction type includes Jump Call Return and Interrupt instructions 6 6 1 First Dword IT 2 0 OPC 2 0 Instruction Type Transfer Control Instruction OpCode 31 30 29 27 This 3 bit field specifies the type of transfer control instruction to execute All transfer control instructions can be conditional They can be dependent on a true false comparison of the ALU Carry bit or a comparison of the SCSI information transfer phase with the Phase field and or a comparison of the First Byte Received with the Data Compare field Each instruction can operate in Initiator or Target mode Transfer Control Instructions 6 27 6 28 OPC2 OPC1 OPCO Instruction Defined 0 0 0 Jump 0 0 1 Call 0 1 0 Return 0 1 1 Interrupt 1 x x Reserved Jump Instruction The LSI53C810A can do a true false comparison of the ALU carry bit or compare the phase and or data as defined by the Phase Compare Data Compare and True False bit fields If the comparisons are true then it loads the DMA SCRIPTS Pointer DSP register with the contents of the DMA SCRIPTS Pointer Save DSPS register The DMA SCRIPTS Pointer DSP register now contains the address of the next instruction If the comparisons are false the LSI53C810A fetches the next instruction from the address pointed to by the DMA SCR
142. l filtering on the SCSI receivers Active negation actively drives the SCSI Request Acknowledge Data and Parity signals HIGH rather than allowing them to be passively pulled up by terminators Active negation is enabled by setting bit 7 in the SCSI Test Three STESTS register TolerANT receiver technology improves data integrity in unreliable cabling environments where other devices would be subject to data corruption TolerANT receivers filter the SCSI bus signals to eliminate unwanted transitions without the long signal delay associated with RC type input filters This improved driver and receiver technology helps eliminate double clocking of data the single biggest reliability issue with SCSI operations The TolerANT input signal filtering is a built in feature of all LSI Logic fast SCSI devices On the LSI53C8XX family products the user may select a filtering period of 30 or 60 ns with bit 1 in the SCSI Test Two STEST2 register The benefits of TolerANT technology include increased immunity to noise when the signal is going HIGH better performance due to balanced duty cycles and improved fast SCSI transfer rates In addition TolerANT SCSI devices do not cause glitches on the SCSI bus at power up or power down so other devices on the bus are also protected from data corruption TolerANT technology is compatible with both the Alternative One and Alternative Two termination schemes proposed by the American National Standards Institute
143. le TRDY S T S Target Ready indicates the target agent s selected device s ability to complete the current data phase of the transaction TRDY is used with IRDY A data phase is completed on any clock when used with IRDY A data phase is completed on any clock when both TRDY and IRDY are sampled asserted During a read TRDY indicates that valid data is present on AD 31 0 During a write it indicates that the target is prepared to accept data Wait cycles are inserted until both IRDY and TRDY are asserted together IRDY S T S Initiator Ready indicates the initiating agent s bus master s ability to complete the current data phase of the transaction IRDY is used with TRDY A data phase is completed on any clock when both IRDY and TRDY are sampled asserted During a write IRDY indicates that valid data is present on AD 31 0 During a read it indicates that the master is prepared to accept data Wait cycles are inserted until both IRDY and TRDY are asserted together STOP S T S Stop indicates that the selected target is requesting the master to stop the current transaction DEVSEL S T S Device Select indicates that the driving device has decoded its address as the target of the current access As an input it indicates to a master whether any device on the bus has been selected IDSEL 97 Initialization Device Select is used as a chip select in place of the up
144. lete CMP set when the LSI53C810A is selected or reselected SEL or RSL set when the initiator asserts ATN target mode SATN active or when the General Purpose or Handshake to Handshake timers expire These interrupts are not needed for events that occur during high level SCRIPTS operation Masking an interrupt means disabling or ignoring that interrupt Interrupts can be masked by clearing bits in the SCSI Interrupt Enable Zero SIENO and SCSI Interrupt Enable One SIEN1 for SCSI interrupts registers or the DMA Interrupt Enable DIEN for DMA interrupts register How the chip responds to masked interrupts depends on Functional Description whether polling or hardware interrupts are being used whether the interrupt is fatal or nonfatal and whether the chip is operating in the Initiator or Target mode If a nonfatal interrupt is masked and that condition occurs the SCRIPTS do not stop the appropriate bit in the SCSI Interrupt Status Zero SISTO or SCSI Interrupt Status One SIST1 is still set the SIP bit in the Interrupt Status ISTAT is not set and the IRQ pin is not asserted See Section 2 7 1 2 Fatal vs Nonfatal Interrupts for a list of the nonfatal interrupts If a fatal interrupt is masked and that condition occurs then the SCRIPTS still stop the appropriate bit in the DMA Status DSTAT SCSI Interrupt Status Zero SISTO or SCSI Interrupt Status One SIST1 register is set and the SIP or DIP bits in t
145. level bits 5 32 chip test five register 5 36 chip test four register 5 34 chip test one register 5 30 chip test six register 5 37 chip test two register 5 30 chip test zero register 5 29 chip type bits 5 55 CIO bit 5 31 clear SCSI FIFO bit 5 64 CLK 4 5 clock 4 5 LSI53C810A PCI to SCSI I O Processor IX 1 clock address incrementor bit 5 36 clock byte counter bit 5 36 clock conversion factor bits 5 10 CLSE bit 5 45 CM bit 5 31 CMP bit 5 48 5 51 COM bit 5 47 CON bit 5 7 5 28 configured as I O bit 5 31 configured as memory bit 5 31 connected bit 5 7 5 28 CSF bit 5 64 CTESTO register 5 29 CTEST1 register 5 30 CTEST2 register 5 30 CTEST4 register 5 34 CTEST5 register 5 36 CTEST6 register 5 37 cycle frame 4 7 D DACK bit 5 31 data acknowledge status bit 5 31 data path 2 8 data request status bit 5 31 data structure address register 5 26 data transfer direction bit 5 30 dataRD bit 5 56 dataWR bit DWR bit 5 56 DBC register 5 38 DC characteristics 7 1 DCMD register 5 39 DCNTL register 5 45 DDIR bit 5 30 5 37 destination I O memory enable bit 5 42 determining the data transfer rate 2 13 device select 4 7 DEVSEL 4 7 DF 7 0 bits 5 37 DFE bit 5 21 DFIFO register 5 33 DHP bit 5 6 DIEN register 5 44 DIFFSENS SCSI signal 7 3 DIOM bit 5 42 DIP bit 5 29 disable halt on parity error or ATN bit 5 6 disable single initiator response bit 5 64 DMA byte counter register 5 38 DMA command register 5 39 DMA control r
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147. lution in PC environments with SDMS software SDMS software provides BIOS and driver support for hard disk tape and removable media peripherals for the major PC based operating systems SDMS software includes a SCSI BIOS to manage all SCSI functions related to the device It also provides a series of SCSI device drivers that support most major operating systems SDMS software supports a multithreaded I O application programming interface API for user developed SCSI applications SDMS software supports both the ASPI and CAM SCSI software specifications 2 3 Prefetching SCRIPTS Instructions When enabled by setting the Prefetch Enable bit bit 5 in the DMA Control DCNTL register the prefetch logic in the LSI53C810A fetches 4 or 8 Dwords of instructions The prefetch logic automatically determines the maximum burst size that it can perform based on the burst length as determined by the values in the DMA Mode DMODE register and the PCI Cache Line Size register if cache mode is enabled If the unit cannot perform bursts of at least 4 Dwords it disables itself The LSI53C810A may flush the contents of the prefetch unit under certain conditions listed below to ensure that the chip always operates from the most current version of the software When one of these conditions apply the contents of the prefetch unit are automatically flushed e On every Memory Move instruction The Memory Move MMOV instruction is often used to place modif
148. m a SCRIPTS Instruction By using the Memory Move instruction single or multiple register values may be transferred to or from system memory Because the LSI53C810A responds to addresses as defined in the Base Address Zero I O or Base Address One Memory registers it can be accessed during a Memory Move operation if the source or destination address decodes to within the chip s register space If this occurs the register indicated by the lower seven bits of the address is taken to be the data source or destination In this way register values are saved to system memory and later restored and SCRIPTS can make decisions based on data values in system memory The SCSI First Byte Received SFBR is not writable using the CPU and therefore not by a Memory Move However it can be loaded using SCRIPTS Read Write operations To load the SFBR with a byte stored in system memory first move the btye to an intermediate LSI53C810A register for example a SCRATCH register and then to the SFBR The same address alignment restrictions apply to register access operations as to normal memory to memory transfers 6 8 Load and Store Instructions The Load and Store instruction provide a more efficient way to move data from to memory to from an internal register in the chip without using the normal memory move instruction The load and store instructions are represented by two Dword opcodes The first Dword contains the DMA Command DCMD and DM
149. mory move 6 36 read write 6 23 SCSI interrupt enable one register 5 50 SCSI interrupt enable zero register 5 48 SCSI interrupt pending bit 5 28 SCSI interrupt status one register 5 53 SCSI interrupt status zero register 5 51 SCSI isolation bit 5 61 SCSI longitudinal parity register 5 54 SCSI loopback mode bit 5 62 SCSI low level mode 5 63 SCSI MSG bit 5 25 SCSI output control latch register 5 18 SCSI output data latch register 5 66 SCSI parity error bit 5 49 SCSI phase mismatch initiator mode bit 5 48 SCSI reset condition bit 5 49 SCSI RST received bit 5 53 SCSI RST signal bit 5 23 SCSI SCRIPTS operation 6 2 SCSI SDP0 parity signal bit 5 23 SCSI selected as ID bits 5 60 SCSI selector ID register 5 19 SCSI status one register 5 24 SCSI status two register 5 25 SCSI status zero register 5 22 SCSI synchronous offset maximum bit 5 61 SCSI synchronous offset zero bit 5 60 SCSI synchronous transfer period bits 5 12 SCSI test one register 5 61 SCSI test three register 5 63 SCSI test two register 5 62 SCSI test zero register 5 60 SCSI timer one register 5 58 SCSI timer zero register 5 57 SCSI timings 7 27 SCSI transfer register 5 12 SCSI true end of process bit 5 31 SCSI valid bit 5 19 SCTRL 4 9 SD 15 0 4 9 SDID register 5 15 SDP bit 5 23 SDP 1 0 4 9 SDPL bit 5 24 SDU bit 5 9 SEL bit 5 18 5 20 5 48 5 52 SEL bits 5 58 select with SATN on a start sequence bit 5 4 selected bit 5 48 5 52 selection during reselection 2 11
150. n be received this rate must not exceed 50 MHz The receive rate is one fourth of the divider output For example if SCLK is 40 MHz and the SCF value is set to divide by one then the maximum rate at which data can be received is 10 Mbytes s 40 1 4 10 For synchronous send the output of the SCF divider is divided by the transfer period XFERP bits in the SCSI Transfer SXFER register For valid combinations of the SCF and the XFERP see Table 5 3 and Table 5 4 under the description of the XFERP bits 7 5 in the SCSI Transfer SXFER register SCSI Bus Interface 2 13 2 6 3 3 SCNTL3 Register Bits 2 0 CCF 2 0 The CCF 2 0 bits select the frequency of the SCLK for asynchronous SCSI operations To meet the SCSI timings as defined by the ANSI specification these bits need to be set properly 2 6 3 4 SXFER Register Bits 7 5 TP 2 0 The TP 2 0 divider XFERP bits determine the SCSI synchronous send rate in either initiator or target mode This value further divides the output from the SCF divider 2 6 3 5 Achieving Optimal SCSI Send Rates 2 14 To achieve optimal synchronous SCSI send timings the SCF divisor value should be set high to divide the clock as much as possible before presenting the clock to the TP divider bits in the SCSI Transfer SXFER register The TP 2 0 divider value should be as low as possible For example with 40 MHz clock to achieve a Mbytes s send rate the SCF bits can be set to divide b
151. ncoder Test 2 This bit is always set when the LSI53C810A exhibits the highest priority ID asserted on the SCSI bus during arbitration It is primarily used for chip level testing but it may be used during low level mode operation to determine if the LSI53C810A won arbitration SCSI Synchronous Offset Zero 1 This bit indicates that the current synchronous SREQ SACK offset is zero This bit is not latched and may change at any time It is used in low level synchronous SCSI operations When this bit is set the LSI53C810A functioning as an initiator is waiting for the target to request data transfers If the LSI53C810A is a target then the initiator has sent the offset number of acknowledges Operating Registers SOM SCSI Synchronous Offset Maximum 0 This bit indicates that the current synchronous SREQ SACK offset is the maximum specified by bits 3 0 in the SCSI Transfer SXFER register This bit is not latched and may change at any time It is used in low level synchronous SCSI operations When this bit is set the LSI53C810A as a target is waiting for the initiator to acknowledge the data transfers If the LSI53C810A is an initiator then the target has sent the offset number of requests Register 0x4D OxCD SCSI Test One STEST1 Read Write SCLK SCSI Clock 7 When set this bit disables the external SCLK SCSI Clock pin and the chip uses the PCI clock as the internal SCSI clock If a transfer rate of 10 Mbytes s is desir
152. nd Invalidate command such that when a latency time out occurs the LSI53C810A continues to transfer up until a cache line boundary At that point the chip relinquishes the bus and PCI Cache Mode 3 5 finish the transfer at a later time using another bus ownership If the chip is transferring multiple cache lines it continues to transfer until the next cache boundary is reached PCI Target Retry During a Write and Invalidate transfer if the target device issues a retry STOP with no TRDY indicating that no data was transferred the LSI53C810A relinquishes the bus and immediately tries to finish the transfer on another bus ownership The chip issues another Write and Invalidate command on the next ownership in accordance with the PCI specification PCI Target Disconnect During a Write and Invalidate transfer if the target device issues a disconnect the LSI53C810A relinquishes the bus and immediately tries to finish the transfer on another bus ownership The chip does not issue another Write and Invalidate command on the next ownership 3 2 3 3 Memory Read Line Command 3 6 This command is identical to the Memory Read command except that it additionally indicates that the master intends to fetch a complete cache line This command is intended for use with bulk sequential data transfers where the memory system and the requesting master might gain some performance advantage by reading up to a cache line boundary rather than a s
153. nd of the transfer An interrupt is not generated Does not halt in target mode when a parity error occurs until the end of the transfer An interrupt is generated Key DHP Disable Halt on SATN or Parity Error bit 5 SCSI Control One SCNTL1 PAR Parity Error bit 0 SCSI Interrupt Enable Zero SIENO This table only applies when the Enable Parity Checking bit is set Parity Options 2 7 2 5 1 DMA FIFO The DMA FIFO is divided into four sections each one byte wide and 20 transfers deep The DMA FIFO is illustrated in Figure 2 1 Figure 2 1 DMA FIFO Sections __ i i _ 32 bits Wide __ 20 Bytes Deep 8 bits 8 bits 8 bits 8 bits Byte Lane 3 Byte Lane 2 Byte Lane 1 Byte Lane 0 2 5 1 1 Data Paths 2 8 The data path through the LSI53C810A is dependent on whether data is being moved into or out of the chip and whether SCSI data is being transferred asynchronously or synchronously Figure 2 2 shows how data is moved to from the SCSI bus in each of the different modes The following steps determine if any bytes remain in the data path when the chip halts an operation Functional Description Asynchronous SCSI Send Step 1 Step 2 Look at the DMA FIFO DFIFO and DMA Byte Counter DBC registers and calculate if there are bytes left in the DMA FIFO To make this calculation subtract the seven least significant bits of the DMA Byte Counter DBC regist
154. nitiator Asynchronous Receive Contents te 1 8 2 8 2 10 2 12 2 15 4 2 4 4 Dee 6 5 6 8 6 16 6 25 6 30 6 37 6 42 7 8 7 8 7 8 7 5 7 9 7 10 7 11 Fee 7 13 7 14 715 7 16 7 17 7 18 7 19 7 20 7 22 7 24 7 27 7 28 Tables 4 21 7 22 7 23 7 24 2 1 2 2 2 3 3 1 3 2 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 5 1 Se 5 3 5 4 5 5 6 1 6 2 Ll LE ia 7 4 id 7 6 Lel 7 8 7 9 Target Asynchronous Send Target Asynchronous Receive Initiator and Target Synchronous Transfers 100 LD PQFP UD Mechanical Drawing Sheet 1 of 2 Bits Used for Parity Control and Observation SCSI Parity Control SCSI Parity Errors and Interrupts PCI Bus Commands and Encoding Types PCI Configuration Register Map Power and Ground Signals System Signals Address and Data Signals Interface Control Signals Arbitration Signals Error Reporting Signals SCSI Bus Interface Signals Additional Interface Signals Synchronous Clock Conversion Factor Asynchronous Clock Conversion Factor Examples of Synchronous Transfer Periods and Rates for SCSI 1 Examples of Synchronous Transfer Periods and Rates for Fast SCSI SCSI Synchronous Offset Values SCRIPTS Instructions Read Write Instructions Absolute Maximum Stress Ratings Operating Conditions SCSI Signals SD 7 0 SDP SREQ SACK SCSI Signals SMSG SI_O SC_D SATN SBSY SSEL SRST Input Signals CLK SCLK GNT IDSEL RST TESTIN Capacitance Outpu
155. nstruction Set of the I O Processor Figure 6 1 SCRIPTS Overview System Processor System Memory Write DSP SCSI Initiator Write Example x Select ATN 0 alt_addr x Move from identify_msg_buf when MSG_OUT x Move from cmd_buf when CMD x Move from data_buf when DATA_OUT x Move from stat_in_buf when STATUS x Move from msg_in_buf when MSG_IN x Move SCNTL2 amp 7F to SCNTL2 x Clear ACK x Wail disconnect alt2 x Int 10 Fetch SCRIPTS 1 S153C810A Nco 2mMaAvn lt w Data Structure Message Buffer Command Buffer Data Buffer Status Buffer 6 3 Block Move Instructions The Block Move SCRIPTS instruction is used to move data between the SCSI bus and memory For a Block Move instruction the LSI53C810A operates much like a chaining DMA device with a SCSI controller attached Figure 6 2 illustrates the register bit values that represent a Block Move instruction In Block Move instructions bits 5 and 4 SIOM and DIOM in the DMA Mode DMODE register determine whether the source destination address resides in memory or I O space When data is being moved onto the SCSI bus SIOM controls whether that data comes from I O or memory space When data is being moved off of the SCSI bus DIOM controls whether that data goes to I O or memory space Block Move Instructions 6 5 6 3 1 First Dword IT 1 0 IA Instruction Type Block Move 31 30 Indirect Addressing 29 When this bit is cleared user data is moved to or from the 32
156. nterrupt stacking begins when either the Interrupt Status ISTAT SIP or DIP bit is set The IRQ output is latched Once asserted it will remain asserted until the interrupt is cleared by reading the appropriate status register Masking an interrupt after the IRQ output is asserted does not cause deassertion of IRQ For more information on interrupts see Chapter 2 Functional Description R Reserved MDPE Master Data Parity Error BF Bus Fault ABRT Aborted SSI Single Step Interrupt SIR SCRIPTS Interrupt Instruction Received R Reserved IID Illegal Instruction Detected Operating Registers N oO a a Oo N Register 0x3A 0xBA Scratch Byte Register SBR Read Write 7 0 SBR 0 0 0 0 0 0 0 0 SBR Scratch Byte Register 7 0 This is a general purpose register Apart from CPU access only register Read Write and Memory Moves into this register alters its contents The default value of this register is zero This register is called the DMA Watchdog Timer on previous LSI53C8XX family products Register 0x3B OxBB DMA Control DCNTL Read Write 7 6 5 4 3 2 1 0 CLSE PFF PFEN SSM IRQM STD IRQD COM 0 0 0 0 0 0 0 0 CLSE Cache Line Size Enable 7 Setting this bit enables the LSI53C810A to sense and react to cache line boundaries set up by the DMA Mode DMODE or PCI Cache Line Size register whichever contains the smaller value Clearing this bit disables the cache line siz
157. o nonaligned addresses corresponding to cache line boundaries In conjunction with the Cache Line Size register the PCI commands Read Line Read Multiple and Write and Invalidate are each software enabled or disabled to allow the user full flexibility in using these commands 3 2 1 Support for PCI Cache Line Size Register The LSI38C810A supports the PCI specification for an 8 bit Cache Line Size register in PCI configuration space It can sense and react to nonaligned addresses corresponding to cache line boundaries PCI Cache Mode 3 3 3 2 2 Selection of Cache Line Size The cache logic selects a cache line size based on the values for the burst size in the DMA Mode DMODE register and the PCI Cache Line Size register Note The LSI53C810A does not automatically use the value in the PCI Cache Line Size register as the cache line size value The chip scales the value of the Cache Line Size register down to the nearest binary burst size allowed by the chip 2 4 8 or 16 compares this value to the DMODE burst size then selects the smallest as the value for the cache line size The LSI53C810A uses this value for all burst data transfers 3 2 3 Alignment The LSI53C810A uses the calculated burst size value to monitor the current address for alignment to the cache line size When it is not aligned the chip disables bursting allowing only single Dword transfers until a cache line boundary is reached When the chip is aligned bursting
158. o provide maximum versatility when writing SCRIPTS For example major sections of code can be accessed with far calls using the 32 bit physical address then local labels can be called using relative transfers If a SCRIPT is written using only relative transfers it does not require any run time alteration of physical addresses and could be stored in and executed from a PROM Carry Test 21 When this bit is set decisions based on the ALU carry bit can be made True False comparisons are legal but Data Compare and Phase Compare are illegal Interrupt on the Fly 20 When this bit is set the Interrupt instruction does not halt the SCRIPTS processor Once the interrupt occurs the Interrupt on the Fly bit Interrupt Status ISTAT bit 2 is asserted Jump If True False 19 This bit determines whether the LSI53C810A branches when a comparison is true or when a comparison is false This bit applies to phase compares data compares and carry tests If both the Phase Compare and Data Compare bits are set then both compares must be true to branch on a true condition Both compares must be false to branch on a false condition Result of Bit 19 Compare Action 0 False Jump Taken 0 True No Jump 1 False No Jump 1 True Jump Taken Transfer Control Instructions 6 33 6 34 CD CP WVP DCM DCV Compare Data 18 When this bit is set the first byte received from the SCSI data bus contained in SCSI First Byte Received SFBR registe
159. ointer DSP register 3 If the CPU sets the SIGP bit in the Interrupt Status ISTAT register the LSI53C810A aborts the Wait Reselect instruction and fetches the next instruction from the address pointed to by the 32 bit jump address field stored in the DMA Next Address DNAD register Set Instruction When the SACK or SATN bits are set the corresponding bits in the SCSI Output Control Latch SOCL register are set When the target bit is set the corresponding bit in the SCSI Control Zero SCNTLO register is also set When the Carry bit is set the corresponding bit in the ALU is set Instruction Set of the I O Processor RA TI V O Instruction Clear Instruction When the SACK or SATWN bits are cleared the corresponding bits are cleared in the SCSI Output Con trol Latch SOCL register When the target bit is cleared the corresponding bit in the SCSI Control Zero SCNTLO register is cleared When the Carry bit is cleared the corresponding bit in the ALU is cleared Relative Addressing Mode 26 When this bit is set the 24 bit signed value in the DMA Next Address DNAD register is used as a relative displacement from the current DMA SCRIPTS Pointer DSP address Use this bit only in conjunction with the Select Reselect Wait Select and Wait Reselect instructions The Select and Reselect instructions can contain an absolute alternate jump address or a relative transfer address Table Indirect Mode 25 When this
160. on 6 When using polled interrupts go back to Step 1 before leaving the ISR in case any stacked interrupts moved in when the first interrupt was cleared When using hardware interrupts the IRQ pin will be asserted again if there are any stacked interrupts This should cause the system to re enter the ISR 2 22 Functional Description Chapter 3 PCI Functional Description Chapter 3 is divided into the following sections e Section 3 1 PCI Addressing e Section 3 2 PCI Cache Mode e Section 3 3 Configuration Registers 3 1 PCI Addressing There are three types of PCl defined address space e Configuration space e Memory space e 1 0 space 3 1 1 Configuration Space Configuration space is a contiguous 256 byte set of addresses dedicated to each slot or stub on the bus Decoding C_BE 3 0 determines if a PCI cycle is intended to access the configuration register space The IDSEL bus signal is a chip select that allows access to the configuration register space only Any attempt to access configuration space is ignored unless IDSEL is asserted The eight lower order address lines and byte enables select a specific 8 bit register The host processor uses this configuration space to initialize the LSI53C810A The lower 128 bytes of the LSI53C810A configuration space hold system parameters while the upper 128 bytes map into the LSI53C810A operating registers For all PCI cycles except configuration
161. on the contents of this register are preserved The power up value of this register is indeterminate Register 0x20 OxA0 DMA FIFO DFIFO Read Write 7 0 R BO 6 0 x 0 0 0 0 0 0 0 R Reserved 7 BO 6 0 Byte Offset Counter 6 0 These bits indicate the amount of data transferred between the SCSI core and the DMA core It may be used to determine the number of bytes in the DMA FIFO 5 33 5 34 when an interrupt occurs These bits are unstable while data is being transferred between the two cores once the chip has stopped transferring data these bits are stable The DMA FIFO DFIFO register counts the number of bytes transferred between the DMA core and the SCSI core The DMA Byte Counter DBC register counts the number of bytes transferred across the host bus The difference between these two counters represents the number of bytes remaining in the DMA FIFO The following steps determine how many bytes are left in the DMA FIFO when an error occurs regardless of the transfer direction 1 Subtract the seven least significant bits of the DMA Byte Counter DBC register from the 7 bit value of the DMA FIFO DFIFO register 2 AND the result with 0x7F for a byte count between zero and 64 Note To calculate the total number of bytes in both the DMA FIFO and SCSI logic see Section 2 5 1 1 Data Paths in Chapter 2 Functional Description Register 0x21 0xA1 Chip Test Four CTEST4 Read Wr
162. on Parity Error 1 When this bit is set the LSI53C810A automatically asserts the SATN signal upon detection of a parity error SATWN is only asserted in the initiator mode The SATN signal is asserted before deasserting SACK during the byte transfer with the parity error Also set the Enable Parity Checking bit for the LSI53C810A to assert SATN in this manner A parity error is detected on data received from the SCSI bus If the Assert SATN on Parity Error bit is cleared or the Enable Parity Checking bit is cleared SATN is not automatically asserted on the SCSI bus when a parity error is received TRG Target Mode 0 This bit determines the default operating mode of the LSI53C810A The user must manually set the target or initiator mode This is done using the SCRIPTS language SET TARGET Or CLEAR TARGET When this bit is set the chip is a target device by default When this bit is cleared the LSI53C810A is an initiator device by default zZ D Writing this bit while not connected may cause the loss of a selection or reselection due to the changing of target or initiator modes 5 5 5 6 Register 0x01 0x81 SCSI Control One SCNTL1 Read Write 5 4 3 2 1 0 DHP CON RST AESP IARB SST 0 0 0 0 0 0 ADB DHP Extra Clock Cycle of Data Setup 7 When this bit is set an extra clock period of data setup is added to each SCSI data transfer The extra data setup time can pro
163. on or Reselection Time out 2 This bit controls whether an interrupt occurs when the SCSI device which the LSI53C810A was attempting to select or reselect did not respond within the programmed time out period See the description of the SCSI Timer Zero STIMEO register bits 3 0 for more information on the time out timer General Purpose Timer Expired 1 This bit controls whether an interrupt occurs when the general purpose timer is expired The time measured is the time between enabling and disabling of the timer See the description of the SCSI Timer One STIME1 register bits 3 0 for more information on the general purpose timer Handshake to Handshake timer Expired 0 This bit controls whether an interrupt occurs when the handshake to handshake timer is expired The time measured is the SCSI Request to Request target or Acknowledge to Acknowledge initiator period See the description of the SCSI Timer Zero STIMEO register bits 7 4 for more information on the handshake to handshake timer Operating Registers Register 0x42 0xC2 SCSI Interrupt Status Zero SISTO Read Only 7 6 5 4 3 2 1 0 M A CMP SEL RSL SGE UDC RST PAR 0 0 0 0 0 0 0 0 Reading the SCSI Interrupt Status Zero SISTO register returns the status of the various interrupt conditions whether they are enabled in the SCSI Interrupt Enable Zero SIENO register or not Each bit set indicates an occurrence of the corresponding condition Reading the SCSI
164. on with the GPIOO pin When this signal is used as a clock for serial EEPROM access the GPIO1 pin serves as data and the pin is controlled from PCI configuration register 0x35 4 10 Signal Descriptions Table 4 8 MAC _ TESTOUT Additional Interface Signals Cont Description Memory Access Control This pin can be programmed to indicate local or system memory accesses non PCl applications It is also used to test the connectivity of the LSI53C810A signals using an AND tree scheme The MAC _TESTOUT pin is only driven as the Test Out function when the TESTIN pin is driven LOW Interrupt This signal when asserted LOW indicates that an interrupting condition has occurred and that service is required from the host CPU The output drive of this pin is programmed as either open drain with an internal weak pull up or optionally as a totem pole driver Refer to the description of DMA Control DCNTL register bit 3 for additional information SCSI Bus Interface Signals 4 11 4 12 Signal Descriptions Chapter 5 Operating Registers This chapter describes all LSI53C810A operating registers Table 5 1 the register map lists registers by operating and configuration addresses The terms set and assert are used to refer to bits that are programmed to a binary one Similarly the terms deassert clear and reset are used to refer to bits that are programmed to a binary
165. or Functional Description 2 6 3 Synchronous Operation The LSI53C810A can transfer synchronous SCSI data in both the initiator and target modes The SCSI Transfer SXFER register controls both the synchronous offset and the transfer period It may be loaded by the CPU before SCRIPTS execution begins from within SCRIPTS using a Table Indirect I O instruction or with a Read Modify Write instruction The LSI53C810A can receive data from the SCSI bus at a synchronous transfer period as short as 80 ns or 160 ns with a 50 MHz clock regardless of the transfer period used to send data The LSI53C810A can receive data at one fourth of the divided SCLK frequency Depending on the SCLK frequency the negotiated transfer period and the synchronous clock divider the LSI53C810A can send synchronous data at intervals as short as 100 ns for fast SCSI 2 and 200 ns for SCSI 1 2 6 3 1 Determining the Data Transfer Rate Synchronous data transfer rates are controlled by bits in two different registers of the LSI53C810A Following is a brief description of the bits Figure 2 4 illustrates the clock division factors used in each register and the role of the register bits in determining the transfer rate 2 6 3 2 SCNTL3 Register Bits 6 4 SCF 2 0 The SCF 2 0 bits select the factor by which the frequency of SCLK is divided before being presented to the synchronous SCSI control logic The output from this divider controls the rate at which data ca
166. or 7 1 Table 7 1 Absolute Maximum Stress Ratings Parameter Storage temperature Test Conditions Supply voltage Input voltage Latch up current Electrostatic discharge 1 2V lt Vpn lt 8 V 2 SCSI pins only MIL STD 883C Method 3015 7 Note Stresses beyond those listed above may cause permanent damage to the device These are stress ratings only functional operation of the device at these or any other conditions beyond those indicated in the Operating Conditions section of the manual is not implied Table 7 2 Operating Conditions Parameter Supply voltage Test Conditions Supply current dynamic Supply current static Operating free air Thermal resistance junction to ambient air 1 Average operating supply current is 50 mA Note Conditions that exceed the operating limits may cause the device to function incorrectly 7 2 Electrical Characteristics Table 7 3 SCSI Signals SD 7 0 SDP SREQ SACK Parameter i Test Conditions Input high voltage Input low voltage Output high voltage Output low voltage Input leakage 3 state leakage 1 TolerANT active negation enabled Table 7 4 SCSI Signals SMSG SI_O SC_D SATN SBSY SSEL SRST Parameter i Test Conditions Input high voltage Input low voltage Output low voltage Input leakage SRST only 3 st
167. or data as defined by the Phase Compare Data Compare and True False bit fields If the comparisons are true then the LSI53C810A generates an interrupt by asserting the IRQ signal The 32 bit address field stored in the DMA SCRIPTS Pointer Save DSPS register can contain a unique interrupt service vector When servicing the interrupt this unique status code allows the ISR to quickly identify the point at which the interrupt occurred The LSI53C810A halts and the DMA SCRIPTS Pointer DSP register must be written before starting any further operation Interrupt on the Fly Instruction The LSI53C810A can do a true false comparison of the ALU carry bit or compare the phase and or data as defined by the Phase Compare Data Compare and True False bit fields If the comparisons are true and the Interrupt on the Fly bit is set bit 2 the LSI53C810A asserts the Interrupt on the Fly bit SCSI Phase 26 24 This 3 bit field corresponds to the three SCSI bus phase signals which are compared with the phase lines latched when SREQ is asserted Comparisons can be performed to determine the SCSI phase actually being driven on the SCSI bus The following table describes the possible combinations and their corresponding SCSI phase These bits are only valid when the LSI53C810A is operating in Initiator mode Clear these bits when the LSI53C810A is operating in Target mode Transfer Control Instructions 6 31 MSG C D I O SCSI Phase 0 0 0
168. ot use indirect and table indirect addressing simultaneously use only one addressing method at a time TIA Table Indirect Addressing 28 When this bit is set the 24 bit signed value in the start address of the move is treated as a relative displacement from the value in the Data Structure Address DSA register Both the transfer count and the source destination address are fetched from this location Use the signed integer offset in bits 23 0 of the second four bytes of the instruction added to the value in the Data Structure Address DSA register to fetch first the byte count and then the data address The signed value is combined with the data structure base address to generate the physical address used to fetch values from the data structure Sign extended values of all ones for negative values are allowed but bits 81 24 are ignored Command Not Used Don t Care Table Offset Block Move Instructions 6 7 Figure 6 2 Block Move Instruction Register a DCMD Register gt C D MSG Opcode Table Indirect Addressing L 0 Instruction Type Block Move 0 Instruction Type Block Move DBC Register gt 24 bit Block Move Byte Counter L Indirect Addressing LSI53C700 Family Compatible DSPS Register 31 30 29 28 27 26 25 24 23 22 21 2019 1817 1615 14131211109 8 7 6 5 4 3 2 1 0 Prior to the start of an I O the Data Structure Address DSA register should be
169. ous data receive is started with data left in the synchronous data FIFO Unexpected Disconnect 2 This bit is set when the LSI53C810A is operating in the initiator mode and the target device unexpectedly disconnects from the SCSI bus This bit is only valid Operating Registers when the LSI53C810A operates in the initiator mode When the LSI53C810A operates in low level mode any disconnect causes an interrupt even a valid SCSI disconnect This bit is also set if a selection time out occurs it may occur before at the same time or stacked after the STO interrupt since this is not considered an expected disconnect RST SCSI RST Received 1 This bit is set when the LSI53C810A detects an active SRST signal whether the reset was generated external to the chip or caused by the Assert SRST bit in the SCSI Control One SCNTL1 register This SCSI reset detection logic is edge sensitive so that multiple interrupts are not generated for a single assertion of the SRST signal PAR Parity Error 0 This bit is set when the LSI53C810A detects a parity error while receiving SCSI data The Enable Parity Checking bit bit 3 in the SCSI Control Zero SCNTLO register must be set for this bit to become active The LSI53C810A always generates parity when sending SCSI data Register 0x43 0xC3 SCSI Interrupt Status One SIST1 Read Only 7 3 2 1 0 R STO GEN HTH x x x X x 0 0 0 Reading the SCSI Interrupt Status One SIST1 reg
170. per 24 address lines during configuration read and write transactions PCI Bus Interface Signals 4 7 4 1 4 Arbitration Signals Table 4 5 describes the Arbitration Signals group Table 4 5 Arbitration Signals Strength Description REQ 200 A4 O 16 mA PCI Request indicates to the system arbiter that this agent desires use of the PCI bus This is a point to point signal Every master has its own REQ signal GNT 199 B5 N A Grant indicates to the agent that access to the PCI bus has been granted This is a point to point signal Every master has its own GNT signal 4 1 5 Error Reporting Signals Table 4 6 describes the Error Reporting Signals group Table 4 6 Error Reporting Signals Description Parity Error may be pulsed active by an agent that detects a data parity error PERR can be used by any agent to signal data corruption However on detection of a PERR pulse the central resource may generate a nonmaskable interrupt to the host CPU which often implies the system is unable to continue operation once error processing is complete System Error is an open drain output used to report address parity errors 4 8 Signal Descriptions 4 2 SCSI Bus Interface Signals The SCSI signal definitions are organized into the following functional groups SCSI Bus Interface Signals and Additional Interface Signals 4 2 1 SCSI Bus Interface Signals Table 4 7 describes the SCSI Bus
171. r is compared with the Data to be Compared Field in the Transfer Control instruction The Wait for Valid Phase bit controls when this compare occurs The Jump if True False bit determines the condition true or false to branch on Compare Phase 17 When the LSI53C810A is in Initiator mode this bit controls phase compare operations When this bit is set the SCSI phase signals latched by SREQ are compared to the Phase Field in the Transfer Control instruction If they match the comparison is true The Wait for Valid Phase bit controls when the compare occurs When the LSI53C810A is operating in Target mode and this bit is set it tests for an active SCSI SATN signal Wait For Valid Phase 16 If the Wait for Valid Phase bit is set the LSI53C810A waits for a previously unserviced phase before comparing the SCSI phase and data If the Wait for Valid Phase bit is cleared the LSI53C810A compares the SCSI phase and data immediately Data Compare Mask 15 8 The Data Compare Mask allows a SCRIPTS instruction to test certain bits within a data byte During the data compare if any mask bits that are set the corresponding bit in the SCSI First Byte Received SFBR data byte is ignored For instance a mask of 0601111111 and data compare value of 0b1XXXXXXX allows the SCRIPTS processor to determine whether or not the high order bit is set while ignoring the remaining bits Data Compare Value 7 0 This 8 bit field is the data to be compar
172. ration it fetches the next instruction from the address pointed to by the DMA SCRIPTS Pointer DSP register This way the SCRIPTS can move to the next instruction before the selection completes It continues executing SCRIPTS until a SCRIPT that requires a response from the Target is encountered 3 If the LSI53C810A is selected or reselected before winning arbitration it fetches the next instruction from the address pointed to by the 32 bit jump address 6 17 field stored in the DMA Next Address DNAD register Manually set the LSI53C810A to Initiator mode if it is reselected or to Target mode if it is selected 4 If the Select with SATN field is set the SATN signal is asserted during the selection phase Wait Disconnect Instruction 1 The LSI53C810A waits for the Target to perform a legal disconnect from the SCSI bus A legal disconnect occurs when SBSY and SSEL are inactive for a minimum of one Bus Free delay 400 ns after the LSI53C810A has received a Disconnect Message or a Command Complete Message Wait Reselect Instruction 1 If the LSI53C810A is selected before being reselected it fetches the next instruction from the address pointed to by the 32 bit jump address field stored in the DMA Next Address DNAD register Manually set the LSI53C810A to Target mode when it is selected 2 If the LSI53C810A is reselected it fetches the next instruction from the address pointed to by the DMA SCRIPTS P
173. ress used for table indirect calculations and the address pointer for a call or return instruction respectively This bit is intended for manufacturing diagnostics only and should not be set during normal operations Master Parity Error Enable 3 Setting this bit enables parity checking during master data phases A parity error during a bus master read is detected by the LSI53C810A A parity error during a bus master write is detected by the target and the LSI53C810A is informed of the error by the PERR pin being asserted by the target When this bit is cleared the LSI53C810A does not interrupt if a master parity error occurs This bit is cleared at power up 5 35 5 36 FBL 2 0 FIFO Byte Control 2 0 rue rots ovo Byte pus FBL2 FBL1 FBLO Byte Lane Px x x J sata wa o jo o o oro o fo fo e fonsa a E E a SE These bits steer the contents of the Chip Test Six CTEST6 register to the appropriate byte lane of the 32 bit DMA FIFO If the FBL2 bit is set then FBL1 and FBLO determine which of four byte lanes can be read or written When cleared the byte lane read or written is determined by the current contents of the DMA Next Address DNAD and DMA Byte Counter DBC registers Each of the four bytes that make up the 32 bit DMA FIFO is accessed by writing these bits to the proper value For normal operation FBL2 must equal zero Register 0x22 OxA2 Chip Test Five CTEST5 Read Write 7 6 5 4 3 2 0 AD
174. rget device disconnects and then some SCSI device selects or reselects the LSI53C810A If the Connected bit is asserted and the LDSC bit is asserted a disconnect is indicated This bit is set when the Connected bit in SCSI Control One SCNTL1 is cleared This bit is cleared when a Block Move instruction is executed while the Connected bit in SCSI Control One SCNTL1 is on R Reserved 0 5 25 31 Registers 0x10 0x13 0x90 0x93 Data Structure Address DSA Read Write DSA 31 0 DSA Data Structure Address 31 0 This 32 bit register contains the base address used for all table indirect calculations The DSA register is usually loaded prior to starting an I O but it is possible for a SCRIPTS Memory Move to load the DSA during the I O During any Memory to Memory Move operation the contents of this register are preserved The power up value of this register is indeterminate Register 0x14 0x94 Interrupt Status ISTAT Read Write 7 6 5 4 3 2 1 0 ABRT SRST SIGP SEM CON INTF SIP DIP 0 0 0 0 0 0 0 0 This register is accessible by the host CPU while a LSI53C810A is executing SCRIPTS without interfering in the operation of the function It is used to poll for interrupts if hardware interrupts are disabled Read this register after servicing an interrupt to check for stacked interrupts For more information on interrupt handling refer to Chapter 2 Functional Description J ABRT Abort Operation Settin
175. rimarily for diagnostic testing programmed O operation or error recovery Data received from the SCSI bus can be read from this register Data can be written to the SCSI Output Data Latch SODL register and then read back into the LSI53C810A by reading this register to allow loopback testing When receiving SCSI data the data flows into this register and out to the host FIFO This register differs from the SCSI Bus Data Lines SBDL register SCSI Input Data Latch SIDL contains latched data and the SCSI Bus Data Lines SBDL always contains exactly what is currently on the SCSI data bus Reading this register causes the SCSI parity bit to be checked and causes a parity error interrupt if the data is not valid The power up values are indeterminate 5 65 5 66 Registers 0x54 0xD4 SCSI Output Data Latch SODL Read Write 15 0 SODL X X X X X X X X X X X X X X X X SODL SCSI Output Data Latch 15 0 This register is used primarily for diagnostic testing or programmed I O operation Data written to this register is asserted onto the SCSI data bus by setting the Assert Data Bus bit in the SCSI Control One SCNTL1 register This register is used to send data using programmed I O Data flows through this register when sending data in any mode It is also used to write to the synchronous data FIFO when testing the chip The power up value of this register is indeterminate R
176. rol One SCNTL1 register for more information on when this status is actually raised CMP Function Complete 6 Indicates full arbitration and selection sequence is completed SEL Selected 5 Indicates the LSI53C810A is selected by a SCSI target device Set the Enable Response to Selection bit in the SCSI Chip ID SCID register for this to occur RSL Reselected 4 Indicates the LSI53C810A is reselected by a SCSI initiator device Set the Enable Response to Reselection bit in the SCSI Chip ID SCID register for this to occur SGE SCSI Gross Error 3 This bit controls whether an interrupt occurs when the LSI53C810A detects a SCSI Gross Error The following conditions are considered SCSI Gross Errors 5 48 Operating Registers UDC RST PAR e Data underflow reading the SCSI FIFO when no data was present e Data overflow writing to the SCSI FIFO while it is full e Offset underflow receiving a SACK pulse in target mode before the corresponding SREQ is sent e Offset overflow receiving an SREQ pulse in the initiator mode and exceeding the maximum offset defined by the MOJ3 0 bits in the SCSI Transfer SXFER register e A phase change in the initiator mode with an outstanding SREQ SACK offset e Residual data in SCSI FIFO starting a transfer other than synchronous data receive with data left in the SCSI synchronous receive FIFO Unexpected Disconnect 2 This bit controls whether an interrupt o
177. ructions may be used to check the value A Move to SFBR followed by a Move from SFBR is used to perform a register to register move Instruction Set of the I O Processor Figure 6 4 illustrates the register bit values that represent a Read Write instruction Figure 6 4 Read Write Register Instruction lt DCMD Register DBC Register 31 30 29 28 27 26 25 24123 22 21 20 19 1817 16 15 1413121110 9 8 7 6 5 4 3 2 1 Immediate Data Reserved must be 0 AO A1 A2 Register L A3 Address A4 A5 T A6 0 Reserved Operator 0 Operator 1 Operator 2 Opcode Bit 0 Opcode Bit 1 Opcode Bit 2 1 Instruction Type R W 0 Instruction Type R W DSPS Register 31 30 29 28 27 26 25 24 23 22 21 2019 18171615 1413121110 9 8 7 6 543 210 Read Write Instructions 6 25 Table 6 2 Operator Read Write Instructions Opcode 111 Read Modify Write Opcode 110 Move to SFBR Opcode 101 Move from SFBR 000 Move data into register Syntax Move data8 to RegA Shift register one bit to the left and place the result in the same register Syntax Move RegA SHL RegA Move data into SCSI First Byte Received SFBR register Syntax Move data8 to SFBR Shift register one bit to the left and place the result in the SCSI First Byte Received SFBR register Syntax Move RegA SHL SFBR Move data into register Syntax Move data8 to RegA Shift th
178. ry address used to perform the Load and Store to from When this bit is set the chip determines the memory address to perform the Load and Store to from by adding the 24 bit signed offset value in the DMA SCRIPTS Pointer Save DSPS to the Data Structure Address DSA Reserved 27 26 No Flush Store instruction only 25 When this bit is set the LSI53C810A performs a Store without flushing the prefetch unit When this bit is cleared the Store instruction automatically flushes the prefetch unit Use No Flush if the source and destination are not within four instructions of the current Store instruction Instruction Set of the I O Processor Note This bit has no effect unless the Prefetch Enable bit in the DMA Control DCNTL register is set For information on SCRIPTS instruction prefetching see Chapter 2 Func tional Description LS Load and Store 24 When this bit is set the instruction is a Load When cleared it is a Store R Reserved 23 RA 6 0 Register Address 22 16 A 6 0 select the register to Load and Store to from within the LSI53C810A Note Itis not possible to load the SCSI First Byte Received SFBR register although the SFBR contents may be stored in another location R Reserved 15 3 BC Byte Count 2 0 This value is the number of bytes to Load and Store 6 8 2 Second Dword Memory lO Address DSA Offset 31 0 This is the actual memory location of where to Load and Store or the offse
179. s iii e Chapter 6 Instruction Set of the I O Processor defines all of the SCSI SCRIPTS instructions that are supported by the LSI53C810A e Chapter 7 Electrical Characteristics contains the electrical characteristics and AC timings for the chip e Appendix A Register Summary is a register summary Related Publications For background please contact ANSI 11 West 42nd Street New York NY 10036 212 642 4900 Ask for document number X3 131 199X SCSI 2 Global Engineering Documents 15 Inverness Way East Englewood CO 80112 800 854 7179 or 303 397 7956 outside U S FAX 303 397 2740 Ask for document number X3 131 1994 SCSI 2 or X3 253 SCSI 3 Parallel Interface ENDL Publications 14426 Black Walnut Court Saratoga CA 95070 408 867 6642 Document names SCS Bench Reference SCSI Encyclopedia SCSI Tutor Prentice Hall 113 Sylvan Avenue Englewood Cliffs NJ 07632 800 947 7700 Ask for document number ISBN 0 13 796855 8 SCSI Understanding the Small Computer System Interface LSI Logic World Wide Web Home Page www lsil com Preface PCI Special Interest Group 2575 N E Katherine Hillsboro OR 97214 800 433 5177 503 693 6232 International FAX 503 693 8344 SCSI SCRIPTS Processors Programming Guide Order Number 14044 A Conventions Used in This Manual The word assert means to drive a signal true or active The word deassert means to drive a signal false or inacti
180. s gt c S lt S AT BB as S D 5 v eS sf ro Ae EE oO oO Q gt 10 10 B xe Bi Gy ees gt gt z 2 a xe Q 5 COo Z lt S aq a a fe de OS a9 l Om W Fa 92 ne rf g a Cc Co 2 Driven by Target Electrical Characteristics 7 24 Figure 7 18 Burst Write Cont Driven by System i i i i i i i i GPIO0_ r 1 1 1 1 1 1 1 FETCH Driven by LSI53C 810A Lan GPIO1_ i MASTER Driven by LSI53C810A REQ 7 l Driven by LSI53C810A i GN a n S Driven by Arbiter 1 i 1 i 1 FRAME l Driven by LSI53C810A i AD DataV Data Addr V Data Driven by LSI53C810A Out A Out Out A Out C_BE Driven by LSI53C810A PAR Driven by LSI53C810A IRDY Driven by LSI53C810A TRDY Driven by Target STOP Driven by Target DEVSEL iam Driven by Target ee ae coche eames Ge m Ny a gt PCI Interface Timing Diagrams 7 25 7 5 PCI Interface Timing Table 7 16 describes the PCI timing data for the LSI53C810A Table 7 16 PCI Timing Parameter Shared signal input setup time Shared signal input hold time CLK to shared signal output valid Side signal input setup time Side signal input hold time CLK to side signal output valid CLK high to FETCH low CLK high to FETCH high CLK high to MASTER low CLK high to MASTER high 7 26 Electrical Characteristics 7 6 SCSI Timings Ta
181. s allows manufacturers to verify chip connectivity and determine exactly which pins are not properly attached When the TESTIN pin is driven LOW internal pull ups are enabled on all input output and bidirectional pins all outputs and bidirectional signals will be 3 stated and the MAC _TESTOUT pin will be enabled Connectivity can be tested by driving one of the LSI53C810A pins LOW The MAC _TESTOUT pin should respond by also driving LOW GPIOO_ General Purpose I O pin Optionally when driven LOW this pin FETCH indicates that the next bus request will be for an opcode fetch This pin powers up as a general purpose input This pin has two specific purposes in the LSI Logic SDMS software SDMS software uses it to toggle SCSI device LEDs turning on the LED whenever the LSI53C810A is on the SCSI bus SDMS software drives this pin LOW to turn on the LED or drives it HIGH to turn off the LED This signal can also be used as data I O for serial EEPROM access In this case it is used with the GPIOO pin which serves as a clock and the pin can be controlled from PCI configuration register 0x35 or observed from the General Purpose GPREG operating register at address 0x07 GPIO1_ General Purpose I O pin Optionally when driven LOW indicates that MASTER the LSI53C810A is bus master This pin powers up as a general purpose input LSI Logic SDMS software supports use of this signal in serial EEPROM applications when enabled in combinati
182. s data The SCSI Output Data Latch SODL register is the interface between the DMA logic and the SCSI bus In synchronous mode data is transferred from the host bus to the SCSI Output Data Latch SODL register and then to the SCSI Output Data Register SODR a hidden buffer register which is not accessible before being sent to the SCSI bus In asynchronous mode data is transferred from the host bus to the SCSI Output Data Latch SODL register and then to the SCSI bus The SODR buffer register is not used for asynchronous transfers It is possible to use this bit to determine how many bytes reside in the chip when an error occurs Arbitration in Progress 4 Arbitration in Progress AIP 1 indicates that the LSI53C810A has detected a Bus Free condition asserted BSY and asserted its SCSI ID onto the SCSI bus Lost Arbitration 3 When set LOA indicates that the LSI53C810A has detected a bus free condition arbitrated for the SCSI bus and lost arbitration due to another SCSI device asserting the SEL signal Won Arbitration 2 When set WOA indicates that the LSI53C810A has detected a Bus Free condition arbitrated for the SCSI bus and won arbitration The arbitration mode selected in the SCSI Control Zero SCNTLO register must be full arbitration and selection for this bit to be set SCSI RST Signal 1 This bit reports the current status of the SCSI RST signal and the SRST signal bit 6 in the Interrupt Status ISTAT register
183. s receiving data any data residing in the DMA FIFO is sent to memory before halting Operating Registers CON RST AESP IARB When this bit is set the LSI53C810A does not halt the SCSI transfer when SATN or a parity error is received Connected 4 This bit is automatically set any time the LSI53C810A is connected to the SCSI bus as an initiator or as a target It is set after the LSI53C810A successfully completes arbitration or when it has responded to a bus initiated selection or reselection This bit is also set after the chip wins simple arbitration when operating in low level mode When this bit is cleared the LSI53C810A is not connected to the SCSI bus The CPU can force a connected or disconnected condition by setting or clearing this bit This feature is used primarily during loopback mode Assert SCSI RST Signal 3 Setting this bit asserts the SRST signal The SRST output remains asserted until this bit is cleared The 25 us minimum assertion time defined in the SCSI specification must be timed out by the controlling microprocessor or a SCRIPTS loop Assert Even SCSI Parity force bad parity 2 When this bit is set the LSI53C810A asserts even parity It forces a SCSI parity error on each byte sent to the SCSI bus from the LSI53C810A If parity checking is enabled then the LSI53C810A checks data received for odd parity This bit is used for diagnostic testing and is cleared for normal operation It is useful to
184. s that the LSI53C810A is already connected to the SCSI bus This bit is automatically cleared when the arbitration sequence is complete If a sequence is aborted check bit 4 in the SCSI Control One SCNTL1 register to verify that the LSI53C810A is not connected to the SCSI bus Select with SATN on a Start Sequence 4 When this bit is set and the LSI53C810A is in the initiator mode the SATN signal is asserted during selection of a SCSI target device This is to inform the target that the LSI53C810A has a message to send If a selection time out occurs while attempting to select a target device SATWN is deasserted at the same time SSEL is deasserted When this bit is cleared the SATN signal is not asserted during selection When executing SCSI SCRIPTS this bit is controlled by the SCRIPTS processor but manual setting is possible in low level mode Operating Registers EPC Enable Parity Checking 3 When this bit is set the SCSI data bus is checked for odd parity when data is received from the SCSI bus in either the initiator or target mode If a parity error is detected bit 0 of the SCSI Interrupt Status Zero SISTO register is set and an interrupt may be generated If the LSI53C810A is operating in the initiator mode and a parity error is detected assertion of SATN is optional but the transfer continues until the target changes phase When this bit is cleared parity errors are not reported R Reserved 2 AAP Assert SATN
185. s the ability of the LSI53C810y to act as a master on the PCI bus A value of zero disables the device from generating PCI bus master accesses A value of one allows the LSI53C810A to behave as a bus master The LSI53C810A must be a bus master in order to fetch SCRIPTS instructions and transfer data Enable Memory Space 1 This bit controls the ability of the LSI53C810A to respond to Memory Space accesses A value of zero disables the device response A value of one allows the LSI53C810A to respond to Memory Space accesses at the address specified by Base Address One Memory PCI Functional Description EIS Enable I O Space 0 This bit controls the LSI53C810A s response to I O space accesses A value of zero disables the response A value of one allows the LSI53C810A to respond to I O space accesses at the address specified in Base Address Zero I O Register 0x06 Status Read Write 14 1 7 0 15 3 12 11 10 9 8 ope sse rmalnra R omo feer RO foto o o G o o o an a a a The Status register is used to record status information for PCI bus related events In the LSI53C810A bits 0 through 4 are reserved and bits 5 6 7 and 11 are not implemented Reads to this register behave normally Writes are slightly different in that bits can be cleared but not set A bit is cleared whenever the register is written and the data in the corresponding bit location is a one For instance to clear bit 15 and not affect any other bits
186. shake Clear the SACK signal using the Clear SACK I O instruction SCSI Phase 26 24 This 3 bit field defines the desired SCSI information transfer phase When the LSI53C810A operates in Initiator mode these bits are compared with the latched SCSI phase bits in the SCSI Status One SSTAT1 register When the LSI53C810A operates in Target mode the LSI53C810A asserts the phase defined in this field The following table describes the possible combinations and the corresponding SCSI phase Block Move Instructions 6 11 TC 23 0 6 3 2 Second Dword MSG C D LO SCSI Phase 0 0 0 Data Out 0 0 1 Data In 0 1 0 Command 0 1 1 Status 1 0 0 Reserved Out 1 0 1 Reserved In 1 1 0 Message Out 1 1 1 Message In Transfer Counter 23 0 This 24 bit field specifies the number of data bytes to be moved between the LSI53C810A and system memory The field is stored in the DMA Byte Counter DBC register When the LSI53C810A transfers data to from memory the DMA Byte Counter DBC register is decremented by the number of bytes transferred In addition the DMA Next Address DNAD register is incremented by the number of bytes transferred This process is repeated until the DMA Byte Counter DBC register has been decremented to Zero At that time the LSI53C810A fetches the next instruction If bit 28 is set indicating table indirect addressing this field is not used The byte count is instead fetched from a table pointed to by the Data S
187. ss one memory 3 17 base address zero I O 3 17 cache line size 3 16 class code 3 15 command 3 11 device ID 3 11 header type 3 17 IX 4 Index interrupt line 3 18 interrupt pin 3 18 latency timer 3 16 max_lat 3 19 min_gnt 3 19 revision ID 3 15 status 3 13 vendor ID 3 11 PCI configuration space 3 1 PCI I O space 3 2 PCI memory space 3 2 PERR 4 8 PFEN bit 5 45 PFF bit 5 45 phase mismatch bit 5 51 physical dword address and data 4 6 pointer SCRIPTS bit PSCPT bit 5 56 prefetch enable bit 5 45 prefetch flush bit 5 45 R read multiple commands enable read multiple bit 5 43 read write instructions 6 23 read modify write cycles 6 26 register addresses operating registers 0x00 5 2 0x01 0x02 0x03 5 0x04 5 0x05 5 0x06 5 0x07 5 0x08 5 0x09 5 Ox0A 5 19 0x0B 5 20 0x0C 5 20 0x0D 5 22 0x0E 5 24 0x0F 5 25 0x10 0x13 5 26 0x14 5 26 0x18 5 29 0x19 5 30 0x1A 5 30 0x1C Ox1F 5 33 0x20 5 33 0x21 5 34 0x22 5 36 0x23 5 37 0x24 0x26 5 38 0x27 5 39 0x28 0x2B 5 39 Ox2C Ox2F 5 39 0x30 0x33 5 40 0x34 0x37 5 41 0x38 5 41 0x39 5 44 0x3B 5 45 Ox3C Ox3F 5 47 0x40 5 48 0x41 5 50 0x42 5 51 0x43 5 53 0x44 5 54 0x46 5 55 0x47 5 56 0x48 5 57 0x49 5 58 0x4A 5 59 0x4C 5 60 0x4D 5 61 Ox4E 5 62 Ox4F 5 63 0x50 5 65 0x54 5 66 0x58 5 66 PCI configuration registers 0x00 3 11 0x02 3 11 0x04 3 11 0x06 3 13 0x08 3 15 0x09 3 15 Ox0C 3 16 Ox0D 3 16 OxOE 3 17 0x10 3 17 0x14 3 17 0x3C 3 18 0x3D 3 18 Ox3E 3 19 Ox3
188. ss to the SCSI bus signals and the low level DMA signals which allows creation of complicated board level test algorithms The low level interface is useful for backward compatibility with SCSI devices that require certain unique timings or bus sequences to operate properly Another feature allowed at the low level is loopback testing In loopback mode the SCSI core can be directed to talk to the DMA core to test internal data paths all the way out to the chip s pins LSI53C810A PCI to SCSI I O Processor 6 1 6 2 SCSI SCRIPTS 6 2 To operate in the SCSI SCRIPTS mode the LSI53C810A requires only a SCRIPTS start address The start address must be at a Dword four byte boundary This aligns subsequent SCRIPTS at a Dword boundary since all SCRIPTS are 8 or 12 bytes long All instructions are fetched from external memory The LSI53C810A fetches and executes its own instructions by becoming a bus master on the host bus and fetching two or three 32 bit words into its registers Instructions are fetched until an interrupt instruction is encountered or until an unexpected event such as a hardware error causes an interrupt to the external processor Once an interrupt is generated the LSI53C810A halts all operations until the interrupt is serviced Then the start address of the next SCRIPTS instruction may be written to the DMA SCRIPTS Pointer DSP register to restart the automatic fetching and execution of instructions The SCSI SCRIPTS mode
189. sserted by an INTFLY instruction during SCRIPTS execution SCRIPTS programs do not halt when the interrupt occurs This bit can be used to notify a service routine running on the main processor while the SCRIPTS processor is still executing a SCRIPTS program If this bit is set when the Interrupt Status ISTAT register is read it is not automatically cleared To clear this bit write it to a one The reset operation is self clearing If the INTF bit is set but SIP or DIP is not set do not attempt to read the other chip status registers An Interrupt on the Fly interrupt must be cleared before servicing any other interrupts indicated by SIP or DIP This bit must be written to one in order to clear it after it has been set SCSI Interrupt Pending 1 This status bit is set when an interrupt condition is detected in the SCSI portion of the LSI53C810A The following conditions cause a SCSI interrupt to occur e A phase mismatch initiator mode or SATN becomes active target mode e An arbitration sequence completes e A selection or reselection time out occurs e The LSI53C810A is selected e The LSI53C810A is reselected Operating Registers e A SCSI gross error occurs e An unexpected disconnect occurs e A SCSI reset occurs e A parity error is detected e The handshake to handshake timer is expired e The general purpose timer is expired To determine exactly which condition s caused the interrupt read the SCSI Interrupt Status
190. sters and all SCSI bus signals Fetch Master and Memory Access control pins Support for indirect fetching of DMA address and byte counts so that SCRIPTS can be placed in a PROM Separate SCSI and system clocks Selectable IRQ pin disable bit Ability to route system clock to SCSI clock Enhanced reliability features of the LSI53C810A include 2 kV ESD protection on SCSI signals Typical 300 mV SCSI bus hysteresis Average operating supply current of 50 mA Protection against bus reflections due to impedance mismatches LS I53C810A Benefits Summary 1 5 1 2 7 Testability Controlled bus assertion times reduces RFI improves reliability and eases FCC certification Latch up protection greater than 150 mA Voltage feed through protection minimum leakage current through SCSI pads High proportion gt 25 of pins power and ground Power and ground isolation of I O pads and internal chip logic TolerANT technology which provides Active negation of SCSI Data Parity Request and Acknowledge signals for improved fast SCSI transfer rates Input signal filtering on SCSI receivers improves data integrity even in noisy cabling environments The LSI53C810A provides improved testability through Access to all SCSI signals through programmed O SCSI loopback diagnostics SCSI bus signal continuity checking Support for single step mode operation Test mode AND tree to check pin continuity to the board A system diagram
191. struction 6 13 6 14 Reselect Instruction 1 The LSI53C810A arbitrates for the SCSI bus by asserting the SCSI ID stored in the SCSI Chip ID SCID register If it loses arbitration it tries again during the next available arbitration cycle without reporting any lost arbitration status 2 If the LSI53C810A wins arbitration it attempts to reselect the SCSI device whose ID is defined in the destination ID field of the instruction Once the LSI53C810A wins arbitration it fetches the next instruction from the address pointed to by the DMA SCRIPTS Pointer DSP register This way the SCRIPTS can move on to the next instruction before the reselection completes It continues executing SCRIPTS until a SCRIPT that requires a response from the Initiator is encountered 3 If the LSI53C810A is selected or reselected before winning arbitration it fetches the next instruction from the address pointed to by the 32 bit jump address field stored in the DMA Next Address DNAD register Manually set the LSI53C810A to Initiator mode if it is reselected or to Target mode if it is selected Disconnect Instruction The LSI53C810A disconnects from the SCSI bus by deasserting all SCSI signal outputs Instruction Set of the I O Processor Note IO Instruction Wait Select Instruction 1 If the LSI53C810A is selected it fetches the next instruction from the address pointed to by the DMA SCRIPTS Pointer DSP register If reselected the
192. supports 32 bit memory and automatically supports misaligned DMA transfers An 80 byte FIFO allows 2 4 8 or 16 Dword bursts across the PCI bus interface to run efficiently without throttling the bus during PCI bus latency 2 2 SCRIPTS Processor 2 2 The SCSI SCRIPTS processor allows both DMA and SCSI commands to be fetched from host memory Algorithms written in SCSI SCRIPTS control the actions of the SCSI and DMA cores and are executed from 32 bit system RAM The SCRIPTS processor executes complex SCSI bus sequences independently of the host CPU The SCRIPTS processor can begin a SCSI I O operation in approximately 500 ns This compares with 2 8 ms required for traditional intelligent host adapters Algorithms may be designed to tune SCSI bus performance to adjust to new bus device types such as scanners communication gateways etc or to incorporate changes in the SCSI 2 or SCSI 3 logical bus definitions without sacrificing I O performance SCSI SCRIPTS are hardware independent so they can be used interchangeably on any host or CPU system bus Functional Description A complete set of development tools is available for writing custom drivers with SCSI SCRIPTS For more information on SCSI SCRIPTS instructions supported by the LSI53C810A see Chapter 6 Instruction Set of the I O Processor 2 2 1 SDMS Software The Total SCSI Solution For users who do not need to develop custom drivers LSI Logic provides a total SCSI so
193. t Signals MAC _TESTOUT REQ Output Signal IRQ Output Signal SERR Contents 7 29 7 30 7 30 7 34 2 6 27 27 3 9 3 10 4 3 4 5 4 6 4 7 4 8 4 8 4 9 4 10 5 10 5 11 5 13 xi xij 7 10 7 11 7 13 7 14 7 15 7 16 Fal Za 7 19 7 20 7 21 7 22 A 1 A 2 Bidirectional Signals AD 31 0 C_BE 3 0 FRAME IRDY TRDY DEVSEL STOP PERR PAR Bidirectional hale Ora FETCH GPIO1_MASTER TolerANT fashion Electrical Characteristics Clock Timing en oe rs SE 5 0 Mbytes s ansfers 10 0 Mbytes s 40 MHz Clock SCSI MHz Clock tion Registers CSI Registers Contents 8 Bit Transfers 2 Fast Transfers 10 0 Mbytes s 8 Bit Transfers 7 7 6 rere 7 10 7 11 7 11 7 26 7 27 7 28 7 29 7 30 7 31 7 31 7 32 A 1 Chapter 1 General Description Chapter 1 is divided into the following sections e Section 1 1 TolerANT Technology e Section 1 2 LSI53C810A Benefits Summary The LSI53C810A PCI to SCSI I O processor brings high performance O solutions to host adapter workstation and general computer designs making it easy to add SCSI to any PCI system The LSI53C810A is a pin for pin replacement for the LSI53C810 PCI to SCSI I O processor It performs fast SCSI transfers in Single Ended SE mode and improves performance by optimizing PCI bus utilization The LSI53C810A integrates a high performance SCSI core a PCI b
194. t from the Data Structure Address DSA register value Load and Store Instructions 6 41 Figure 6 7 illustrates the register bit values that represent a Load and Store instruction Figure 6 7 Load and Store Instruction Format lt DCMD Register DBC Register 31 30 29 28 27 26 25 24123 22 21 20 19 18 17 16 15 1413121110 9 8 7 5432 1 0 Reserved Byte Count must be 0 Number of bytes AO to load store A1 A2 Register L A3 Address A4 A5 A6 0 Reserved Load Store No Flush 0 Reserved 0 Reserved DSA Relative 1 Instruction Type Load and Store DSPS Register Memory I O Address DSA Offset 31 30 29 28 27 26 25 24 23 22 21 2019 18 17 16 15 14131211109 8 7 6 543 210 6 42 Instruction Set of the I O Processor Chapter 7 Electrical Characteristics This chapter specifies the LSI53C810A electrical and mechanical characteristics It is divided into the following sections Section 7 1 Section 7 2 Section 7 3 Section 7 4 Section 7 5 Section 7 6 Section 7 7 7 1 DC Characteristics DC Characteristics TolerANT Technology AC Characteristics PCI Interface Timing Diagrams PCI Interface Timing SCSI Timings Package Drawings This section of the manual describes the LSI53C810A DC characteristics Table 7 1 through Table 7 11 give the current and voltage specifications LSI53C810A PCI to SCSI I O Process
195. t only in conjunction with the Select Reselect Wait Select and Wait Reselect instructions Use bits 25 and 26 individually or in combination to produce the following conditions Bit 25 Bit 26 Direct 0 0 Table Indirect 0 1 Relative 1 0 Table Relative 1 1 Direct Uses the device ID and physical address in the instruction Command ID Not Used Not Used Absolute Alternate Address Table Indirect Uses the physical jump address but fetches data using the table indirect method Command Table Offset Absolute Jump Offset Relative Uses the device ID in the instruction but treats the alternate address as a relative jump Command ID Not Used Not Used Absolute Jump Offset 6 20 Instruction Set of the I O Processor Sel ENDID cc TM V O Instruction Table Relative Treats the alternate jump address as a relative jump and fetches the device ID synchronous offset and synchronous period indirectly The value in bits 23 0 of the first four bytes of the SCRIPTS instruction is added to the data structure base address to form the fetch address Command Table Offset Absolute Jump Offset Select with ATN 24 This bit specifies whether SATN is asserted during the selection phase when the LSI53C810A is executing a Select instruction When operating in Initiator mode set this bit for the Select instruction If this bit is set on any other I O instruction an illegal instruction interrupt is g
196. tching the four Dwords required in two bursts of two Dwords each Manual Start Mode 0 Setting this bit prevents the LSI53C810A from automatically fetching and executing SCSI SCRIPTS when the DMA SCRIPTS Pointer DSP register is written When this bit is set the Start DMA bit in the DMA Control DCNTL register must be set to begin SCRIPTS execution Clearing this bit causes the LSI53C810A to automatically begin fetching and executing SCSI SCRIPTS when the DMA SCRIPTS Pointer DSP register is written This bit normally is not used for SCSI SCRIPTS operations 5 43 5 44 Register 0x39 0xB9 DMA Interrupt Enable DIEN Read Write 7 6 5 4 3 2 1 0 R MDPE BF ABRT SSI SIR R IID x 0 0 0 0 0 x 0 This register contains the interrupt mask bits corresponding to the interrupting conditions described in the DMA Status DSTAT register An interrupt is masked by clearing the appropriate mask bit Masking an interrupt prevents IRQ from being asserted for the corresponding interrupt but the status bit is still set in the DMA Status DSTAT register Masking an interrupt does not prevent setting the ISTAT DIP All DMA interrupts are considered fatal therefore SCRIPTS stops running when a DMA interrupt occurs whether or not the interrupt is masked Setting a mask bit enables the assertion of IRQ for the corresponding interrupt A masked nonfatal interrupt does not prevent unmasked or fatal interrupts from getting through i
197. tiator mode this register contains the first byte received in Message In Status phase Reserved In and Data In When a Block Move instruction is executed for a particular phase the first byte received is stored in this register even if the present phase is the same as the last phase The first byte received value for a particular input phase is not valid until after a MOVE instruction is executed This register is also the accumulator for register read modify writes with the SCSI First Byte Received SFBR as the destination This allows bit testing after an operation The SCSI First Byte Received SFBR cannot be written using the CPU and therefore not by a Memory Move Additionally the Load instruction cannot be used to write to this register However it can be loaded using SCRIPTS Read Write operations To load the SCSI First Byte Received SFBR with a byte stored in system memory the byte must first be moved to an intermediate LSI53C810A register such as the SCRATCH register and then to the SCSI First Byte Received SFBR This register also contains the state of the lower eight bits of the SCSI data bus during the Selection phase if the COM bit in the DMA Control DCNTL register is clear 5 17 5 18 Register 0x09 0x89 SCSI Output Control Latch SOCL Read Write 7 6 5 4 3 2 1 0 REQ ACK BSY SEL ATN MSG C D 1O 0 0 0 0 0 0 0 0 REQ Assert SCSI REQ Signal 7 ACK Assert SCSI ACK Signal 6 BSY Assert SCSI BSY Signal
198. ting Bus commands are encoded on the C_BE 3 0 lines during the address phase PCI bus commands and encoding types appear in Table 3 1 3 1 2 1 1 0 Read Command The I O Read command reads data from an agent mapped in I O address space All 32 address bits are decoded 3 1 2 2 1 0 Write Command The I O Write command writes data to an agent when mapped in I O address space All 32 address bits are decoded 3 2 PCI Functional Description 3 1 2 3 3 1 2 4 3 1 2 5 3 1 2 6 3 1 2 7 Memory Read Command The Memory Read reads data from an agent mapped in memory address space All 32 address bits are decoded Memory Read Multiple Command The Memory Read Multiple command reads data from an agent mapped in memory address space All 32 address bits are decoded Memory Read Line Command The Memory Read Line command reads data from an agent mapped in memory address space All 32 address bits are decoded Memory Write Command The Memory Write command writes data to an agent when mapped in memory address space All 32 address bits are decoded Memory Write and Invalidate Command The Memory Write and Invalidate command writes data to an agent when mapped in memory address space All 32 address bits are decoded 3 2 PCI Cache Mode The LSI53C810A supports the PCI specification for an 8 bit Cache Line Size register located in PCI configuration space The Cache Line Size register provides the ability to sense and react t
199. to a byte lane in the DMA FIFO For example if byte lane three is full then FFL3 is set Since the FFL flags indicate the status of bytes at the top of the FIFO if all FFL bits are set the DMA FIFO is full Register 0x1A 0x9A Chip Test Two CTEST2 Read Only 7 6 5 4 3 2 1 0 DDIR SIGP clo CM R TEOP DREQ DACK 0 0 x x 0 0 0 1 DDIR Data Transfer Direction 7 This status bit indicates which direction data is being transferred When this bit is set the data will be transferred from the SCSI bus to the host bus When this bit is clear the data is transferred from the host bus to the SCSI bus Operating Registers SIGP clo CM DREQ DACK Signal Process 6 This bit is a copy of the SIGP bit in the Interrupt Status ISTAT register bit 5 The SIGP bit is used to signal a running SCRIPTS instruction When this register is read the SIGP bit in the Interrupt Status ISTAT register is cleared Configured as I O 5 This bit is defined as the Configuration I O Enable Status bit This read only bit indicates if the chip is currently enabled as I O space Both bits 4 and 5 may be set if the chip is dual mapped Configured as Memory 4 This bit is defined as the configuration memory enable status bit This read only bit indicates if the chip is currently enabled as memory space Both bits 4 and 5 may be set if the chip is dual mapped Reserved 3 SCSI True End of Process 2 This bit indicates the
200. to perform a low level selection instead e The abort completes because the LSI53C810A loses arbitration This is detected by clearing the Immediate Arbitration bit Do not use the Lost Arbitration bit SCSI Status Zero SSTATO bit 3 to detect this condition In this case take no further action Start SCSI Transfer 0 This bit is automatically set during SCRIPTS execution and should not be used It causes the SCSI core to begin a SCSI transfer including SREQ SACK handshaking The determination of whether the transfer is a send or receive is made according to the value written to the I O bit in SCSI Output Control Latch SOCL This bit is self clearing Do not set it for low level operation Writing to this register while not connected may cause the loss of a selection reselection by clearing the Connected bit Operating Registers Register 0x02 0x82 SCSI Control Two SCNTL2 Read Write SDU R 0 x x x x x x x SDU SCSI Disconnect Unexpected 7 This bit is valid in the initiator mode only When this bit is set the SCSI core is not expecting the SCSI bus to enter the Bus Free phase If it does an unexpected disconnect error is generated see the Unexpected Disconnect bit in the SCSI Interrupt Status Zero SISTO register bit 2 During normal SCRIPTS mode operation this bit is set automatically whenever the SCSI core is reselected or successfully selects another SCSI device The SDU bit should be cleared with a register
201. tronics com W E Wyle Electronics http www wyle com Alabama Daphne lE Tel Huntsville A E Tel 256 837 8700 lE Tel 256 830 1222 W E Tel 800 964 9953 334 626 6190 Alaska A E Tel 800 332 8638 Arkansas W E Tel 972 235 9953 Arizona Phoenix A E Tel 480 736 7000 B M Tel 602 267 9551 W E Tel 800 528 4040 Tempe l E Tel Tucson A E Tel 480 829 1800 520 742 0515 California Agoura Hills B M Tel 818 865 0266 Irvine A E Tel 949 789 4100 M Tel 949 470 2900 E Tel 949 727 3291 Tel 800 626 9953 os Angeles m A E Tel 818 594 0404 W E Tel 800 288 9953 Sacramento A E Tel 916 632 4500 W E Tel 800 627 9953 San Diego A E Tel 858 385 7500 B M Tel 858 597 3010 LE Tel 800 677 6011 W E Tel 800 829 9953 San Jose A E Tel 408 435 3500 B M Tel 408 436 0881 l E Tel 408 952 7000 Santa Clara W E Tel 800 866 9953 Woodland Hills A E Tel 818 594 0404 Westlake Village L Tel 818 707 2101 Colorado Denver A E Tel 303 790 1662 B M Tel 303 846 3065 W E Tel 800 933 9953 Englewood e l E 303 649 1800 Connecticut Cheshire A E Tel 203 271 5700 I E Tel 203 272 5843 Wallingford W E Tel 800 605 9953 Delaware North South A E Tel 800 526 4812 Tel 800 638 5988 B M Tel 302 328 8968 W E Tel 856 439 9110 Florida Altamonte Springs B M Tel 407 682 1199 l E Tel 407 834 6310 Boca Raton l E Tel 561 997
202. tructure Address DSA register Start Address 31 0 This 32 bit field specifies the starting address of the data to be moved to from memory This field is copied to the DMA Next Address DNAD register When the LSI53C810A transfers data to or from memory the DMA Next Address DNAD register is incremented by the number of bytes transferred When bit 29 is set indicating indirect addressing this address is a pointer to an address in memory that points to the data location When bit 28 is set indicating table 6 12 Instruction Set of the I O Processor indirect addressing the value in this field is an offset into a table pointed to by the Data Structure Address DSA The table entry contains byte count and address information 6 4 I O Instruction The I O SCRIPTS instruction causes the LSI53C810A to trigger common SCSI hardware sequences such as Set Clear ACK Set Clear ATN Set Clear Target Mode Select With ATN or Wait for Reselect 6 4 1 First Dword IT 1 0 Instruction Type I O Instruction 31 30 OPC 2 0 OpCode 29 27 The following OpCode bits have different meanings depending on whether the LSI53C810A is operating in initiator or target mode Note OpCode selections 101 111 are considered Read Write instructions and are described Section 6 5 Read Write Instructions Target Mode OPC2 OPC1 OPCO Instruction Defined 0 0 0 Reselect 0 0 1 Disconnect 0 1 0 Wait Select 0 1 1 Set 1 0 0 Clear IO In
203. uired if the LSI53C810A is in one of the following modes e Manual start mode Bit 0 in the DMA Mode DMODE register is set e Single step mode Bit 4 in the DMA Control DCNTL register is set When the LSI53C810A is executing SCRIPTS in manual start mode the Start DMA bit needs to be set to start instruction fetches This bit remains set until an interrupt occurs When the LSI53C810A is in single step mode set the Start DMA bit to restart execution of SCRIPTS after a single step interrupt IRQ Disable 1 Setting this bit 3 states the IRQ pin Clearing the bit enables normal operation When bit 1 in this register is set the IRQ pin is not asserted when an interrupt condition occurs The interrupt is not lost or ignored but merely masked at the pin Clearing this bit when an interrupt is pending immediately causes the IRQ pin to Operating Registers 31 COM assert As with any register other than Interrupt Status ISTAT this register cannot be accessed except by a SCRIPTS instruction during SCRIPTS execution LSI53C700 Family Compatibility 0 When this bit is cleared the LSI53C810A behaves in a manner compatible with the LSI53C700 family selection reselection IDs are stored in both the SCSI Selector ID SSID and SCSI First Byte Received SFBR registers When this bit is set the ID is stored in the SCSI Selector ID SSID register protecting the SCSI First Byte Received SFBR from being overwritten if a sele
204. urce address to the destination address Allowing the LSI53C810A to perform memory moves frees the system processor for other tasks and moves data at higher speeds than available from current DMA controllers Up to 16 Mbytes may be transferred with one instruction There are two restrictions e Both the source and destination addresses must start with the same address alignment A 1 0 If source and destination are not aligned then an illegal instruction interrupt occurs e Indirect addresses are not allowed A burst of data is fetched from the source address put into the DMA FIFO and then written out to the destination address The move continues until the byte count decrements to zero then another SCRIPTS instruction is fetched from system memory Instruction Set of the I O Processor Figure 6 6 illustrates the register bit values that represent a Memory Move instruction Figure 6 6 Memory to Memory Move Instruction lt DCMD Register DBC Register 31 30 29 28 27 26 25 24123 22 21 20 19 1817 16 15 1413121110 9 8 7 6 5 4 3 2 1 No Flush 0 Reserved 24 bit Memory Move Byte Counter 0 Reserved 0 Reserved 0 Reserved L 0O Reserved L 1 Instruction Type Memory Move L 1 Instruction Type Memory Move DSPS Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEMP Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 1
205. us master DMA core and the LSI Logic SCSI SCRIPTS processor to meet the flexibility requirements of SCSI 1 SCSI 2 and future SCSI standards It is designed to implement multithreaded I O algorithms with a minimum of processor intervention solving the protocol overhead problems of previous intelligent and nonintelligent adapter designs The LSI53C810A is fully supported by the LSI Logic Storage Device Management System SDMS a software package that supports the Advanced SCSI Protocol Interface ASPI SDMS software provides BIOS and driver support for hard disk tape removable media products and CD ROM under the major PC operating systems The LSI53C810A is packaged in a compact rectangular 100 pin Plastic Quad Flat Pack PQFP package to minimize board space requirements It operates the SCSI bus at 5 Mbytes s asynchronously or 10 Mbytes s synchronously and bursts data to the host at full PCI speeds The LSI53C810A increases SCRIPTS performance and reduces PCI bus overhead by allowing instruction prefetches of 4 or 8 Dwords LSI53C810A PCI to SCSI I O Processor 1 1 Software development tools are available to developers who use the SCSI SCRIPTS language to create customized SCSI software applications The LSI53C810A allows easy firmware upgrades and is supported by advanced SCRIPTS commands 1 1 TolerANT Technology The LSI53C810A features TolerANT technology which includes active negation on the SCSI drivers and input signa
206. ve Hexadecimal numbers are indicated by the prefix Ox for example Ox32CF Binary numbers are indicated by the prefix Ob for example 0b0011 0010 1100 1111 Revision Record Revision Remarks First version Revised technical manual All product names changed from SYM to LSI Preface v vi Preface Chapier 1 Chapter 2 Contents General Description 1 1 12 TolerANT Technology LSI53C810A Benefits Summary 1 2 1 SCSI Performance 12 2 PCI Performance 1 2 3 Integration 1 2 4 Ease of Use 1 2 5 Flexibility 1 2 6 Reliability Lar Testability Functional Description 21 2 2 2 3 2 4 2 5 2 6 SCSI Core 2 1 1 DMA Core SCRIPTS Processor 2 2 1 SDMS Software The Total SCSI Solution Prefetching SCRIPTS Instructions 2 3 1 Opcode Fetch Burst Capability PCI Cache Mode 2 4 1 Load and Store Instructions 2 4 2 3 3 V 5 V PCI Interface 2 4 3 Loopback Mode Parity Options 25d DMA FIFO SCSI Bus Interface 2 6 1 Terminator Networks 2 6 2 Select Reselect During Selection Reselection 2 6 3 Synchronous Operation Contents 1 2 1 3 1 3 1 4 1 4 1 5 1 5 1 6 21 2 11 zi 2 11 2 13 vii 2 7 Interrupt Handling 2 15 2 7 1 Polling and Hardware Interrupts 2 15 Chapter 3 PCI Functional Description 3 1 PCI Addressing 3 1 3 1 1 Configuration Space 3 1 3 12 PCI Bus Commands and Functions Supported 3 2 3 2 PCI Cache Mode 3 3 EA Support for PCI Cache Lin
207. ve data setup to SREQ or SACK asserted Receive data hold from SREQ or SACK asserted 7 32 Electrical Characteristics 7 7 Package Drawings Figure 7 24 illustrates the mechanical drawing for the LSI53C810A Package Drawings 7 33 Figure 7 24 100 LD PQFP UD Mechanical Drawing Sheet 1 of 2 ESA LED SS DESCRIPTION DATE REV SEE DOCUMENT CONTROL TITLE PAGE 3 19 97 2 A A ii 20 c A B OD pl 20 c A B Op 03 5 A 8 DIMENSIONS IN MM SYM MIN NOM MAX NOTE Se ai a gt S A 3 40 4 At 0 25 i ATT i Ha t Se m B 0 22 0 38 8 10 BI 0 22 0 33 C 0 14 0 23 810 ca REI 0 17 i i D 2365 23 90 2415 4 D1 19 90 20 00 20 10 5 D3 18 85_REF e 0 65 TYP a IE E 17 65 17 90 1815 4 1 E AlA El 13 90 14 00 1410 5 AET E EA e E E E3 12 35 REF fees 8 EE L 0 73 0 88 1 03 i he K 1 95 REF N 100 a SEE DETAIL A a a 7 Dt el 0 i l e2 5 16 ee 83 5 16 a La coa 0 10 M 4 W rr 12345 20 c Ja Op 20 c a B OD 1 05 A B LSI LOGIC CORPORATION A A2 C BASE PLANE 48580 KATO ROAD FREMONT CA 94539 A H ma TE
208. vide additional system design margin though it affects the SCSI transfer rates Clearing this bit disables the extra clock cycle of data setup time Setting this bit only affects SCSI send operations Assert SCSI Data Bus 6 Wher this bit is set the LSI53C810A drives the contents of the SCSI Output Data Latch SODL register onto the SCSI data bus When the LSI53C810A is an initiator the SCSI I O signal must be inactive to assert the SCSI Out put Data Latch SODL contents onto the SCSI bus When the LSI53C810A is a target the SCSI I O signal must be active to assert the SCSI Output Data Latch SODL contents onto the SCSI bus The contents of the SCSI Output Data Latch SODL register can be asserted at any time even before the LSI53C810A is connected to the SCSI bus Clear this bit when executing SCSI SCRIPTS It is normally used only for diagnostics testing or operation in low level mode Disable Halt on Parity Error or ATN Target Only 5 The DHP bit is only defined for target mode When this bit is cleared the LSI53C810A halts the SCSI data transfer when a parity error is detected or when the SATWN signal is asserted If SATN or a parity error is received in the middle of a data transfer the LSI53C810A may transfer up to three additional bytes before halting to synchronize between internal core cells During synchronous operation the LSI53C810A transfers data until there are no outstanding synchronous offsets If the LSI53C810A i
209. write the value 0x8000 to the register DPE Detected Parity Error from Slave 15 This bit is set by the LSI53C810A whenever it detects a data parity error even if parity error handling is disabled SSE Signaled System Error 14 This bit is set whenever a device asserts the SERR signal RMA Master Abort from Master 13 A master device should set this bit whenever its transaction except for Special Cycle is terminated with master abort All master devices should implement this bit Configuration Registers 3 13 RTA Received Target Abort from Master 12 A master device should set this bit whenever its transaction is terminated with a target abort All master devices should implement this bit R Reserved 11 DT 1 0 DEVSEL Timing 10 9 These bits encode the timing of DEVSEL 0b00 Fast 0b01 Medium 0b10 Slow 0b11 Reserved These bits are read only and should indicate the slowest time that a device asserts DEVSEL for any bus command except Configuration Read and Configuration Write The LSI53C810A supports 0b01 DPR Data Parity Reported 8 This bit is set when the following three conditions are met e The bus agent asserted PERR itself or observed PERR asserted e The agent setting this bit acted as the bus master for the operation in which the error occurred e The Parity Error Response bit in the Command register is set R Reserved 7 0 3 14 PCI Functional Description Register 0x08 Revision
210. y 1 and the TP bits to divide by 8 or the SCF bits can be set to divide by 2 and the TP bits set to divide by 4 Use the second option to achieve optimal SCSI timings Functional Description Figure 2 4 Determining the Synchronous Transfer Rate SCF2 SCF1 SCFO SCF TP2 TP1 TPO XFERP Divisor Divisor 0 0 1 1 0 0 0 4 0 1 0 1 5 0 0 1 5 0 1 1 2 0 1 0 6 1 0 0 3 0 1 1 E 0 0 0 3 1 0 0 8 1 0 1 9 1 1 0 1 il 1 1 1 This point must not exceed 50 MHz SCF Divider CCF Divider Divide by 4 Synchronous Divider Send Clock gt to SCSI Bus Asynchronous SCSI Logic This point ee ae must not CCF2__CCF1 CCFO _ SCSI Clock MHz aca 0 0 0 50 1 66 00 0 0 1 16 67 25 00 Example 0 1 0 25 01 37 50 SCLK 40 MHz SCF 1 1 XFERP 0 4 0 1 37 51 50 00 CCF 3 37 51 50 00 MHz 1 0 0 50 01 66 00 Synchronous send rate SCLK SCF XFERP 40 1 4 10 Mbytes s Synchronous receive rate SCLK SCF 4 40 1 4 10 Mbytes s 2 7 Interrupt Handling The SCRIPTS processor in the LSI53C810A performs most functions independently of the host microprocessor However certain interrupt situations must be handled by the external microprocessor This section explains all aspects of interrupts as they apply to the LSI53C810A 2 7 1 Polling and Hardware Interrupts The external microprocessor is informed of an interrupt condition by polling or hardware interrupts Polling means that the micropro
211. y an amount equal to the number of bytes that are transferred The maximum number of bytes that can be transferred in any one Block Move command is 16 777 215 bytes The maximum value that can be loaded into the DMA Byte Counter DBC register is OxFFFFFF If the instruction is a Block Move and a value of 0x000000 is loaded into the DMA Byte Counter DBC register an illegal instruction interrupt occurs if the LSI53C810A is not in target mode Command phase The DMA Byte Counter DBC register is also used to hold the least significant 24 bits of the first Dword of a SCRIPTS fetch and to hold the offset value during table indirect O SCRIPTS For a complete description see Chapter 6 Instruction Set of the I O Processor The power up value of this register is indeterminate Operating Registers 31 Register 0x27 0xA7 DMA Command DCMD Read Write 7 0 DCMD X X X X X X X DCMD DMA Command 7 0 This 8 bit register determines the instruction for the LSI53C810A to execute This register has a different format for each instruction For a complete description see Chapter 6 Instruction Set of the I O Processor Registers 0x28 0x2B 0xA8 OxAB DMA Next Address DNAD Read Write DNAD 0 0 0 olo o o o o olololololololololololololo DNAD DMA Next Address 31 0

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