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Kane Industries C6713CPU User's Manual

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1. M 14 2 3 5 UART RS 232 Interface re ashes pee Reve aac cuta ENEE EE Vet 14 2 3 6 Temperature Sensor ccccecccecccecccececeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeeeeeeeeeeeeettegss 14 2 3 7 Reset Generator KE ee E 15 cr MES uico cibiuk a MP e 15 2 3 9 Power Supply of the Board 15 PA E dU E n A 15 2 4 1 User Programmable LED s PLD E 16 2 4 2 User Programmable LED FPGA E 16 2 5 DSP peripherals ee ee ee eee eee 16 2 5 1 Multichannel Audio Serial Ports MGAGP AAA 16 2 5 2 External Memory Interface EMIF 2o ti etn em Rie a 16 2 5 3 Inter Integrated Circuit CH Interfaces eerte tenentes 17 2 5 4 General Purpose Input Output Pins GPIO Hee 17 2 5 5 Multi channel Buffered Serial Ports McbGb AA 17 290 TME EE 18 Zo H st Por Interface Eege 18 2 904 IMENU See sats Ee ee e 18 29 9 DMA E 19 3 MEMORY MAPS AND DESCRIPTION OF THE PLD REGISTERS 20 31 TMS32066713 Memory Map rantur noms utate uu ck nasa cma an nk rn antera eua Ee EEGEN 20 3 2 GOTISCPU Address Map reote nce k aues EES EE 21 LOS Date 28 November 2005 KJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU iE EXER EIE ee S04 S4 n0EnnnnnXA Tt 21 3 4 DSP Peripherals mee
2. 21 3 5 External SDRAM ML 21 3 6 Flash ub C I C 21 3 7 TEE 22 3 8 EMIF C nfigurati N c ee 23 3 8 1 Default EMIF contig ratio EE 23 3 9 Description of the PLD Board Registers esses nnne 23 3 10 Description of the PLD Registers s s eeseeeeseeeensesnenseeeeeseenseeseeeeneneeseseeeennsnnenoneees 24 3 10 1 Hardware Configuration Register HWCFG eeeseeeeeene nennen 24 3 10 2 FPGA Control Register FG EE 25 3 10 3 LED Control Register DEED ieri idis iantit het eEdSEECEes 25 3 10 4 Module Control Register MCR iiia eidelen EE es 26 3 10 5 APC Bus Control Register 12C iet tree 26 3 10 6 External Flag Register tine mm 27 3 10 7 Watchdog Register EE 27 3 10 8 Version Register AEN 28 4 BOOT PROCESS AND DEFAULT SETUP OF THE C67130CPU 29 5 USING THE FLASH FILE SYSTEM erugeet 30 6 DESCRIPTION OF THE MICRO LINE BOARD CONNECTORS 31 6 1 Location of the Connectors eiuse e etenida erii eta Sec DE suo Isaac nnmnnn annnm nnne 31 6 2 Connector OVERVIEW uicem YEAR TIER EEN 32 6 3 Pinout Tables of the micro line Connector eseeeeseesese nene rnnt retener nnns 32 6 4 Pinout of the JTAG CornneC OL eeeeeniei terrena sec e kcu de tan nan aan ca ha un uas R 4D anna nnmnnn nnen nnna 35 6 5 Function of the micro
3. 1 5 Hevision History Changes ORSYS internal preliminary version April 2005 First public preliminary version May 2005 R ee Block diagram completed 1 0 Flash File System short description only reference to separate user s guide Mentioned that HPI usage requires FPGA Minor corrections to signal descriptions series resistors RESETOUT pull up default state of RTS recommended usage of D19 D21 SCLO SDAO usage HPI driver direction control Values for typical power consumption added Dimensions of connector pins revised 1 1 Added note about RS 232 usage with Win 2k and XP Board dimensions board and connector height added LS Date 28 November 2005 KJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU por 2 Hardware Overview The micro line C6713CPU is a high performance DSP board that combines several key technologies for high speed data processing e aTMS320C6713 DSP with 256 KB internal fast SRAM and 225MHz or 300MHz CPU clock 1800 MIPS 1350 MFLOPS or 2400 MIPS 1800 MFLOPS e aXilinx Spartan 3 FPGA with up to 1M gates 32 64 MB SDRAM in standard versions and 128 MB on request 2 MB flash memory for non volatile program data and FPGA design storage The C6713CPU is available in different versions regarding processor speed and memory size Please contact ORSYS or ORSYS distributors for the newest product list For proper operation of the micro line C6713CP
4. n Date 28 November 2005 fy HARDWARE REFERENCE GUIDE Doc no C6713CPU HRG iJ Iss Rev 1 1 orsys Page 1 Hardware Reference Guide micro line C6713CPU High performance DSP FPGA board P Kane Computing Ltd 7 Theatre Court London Road Northwich Cheshire CW9 SHB UK Tel 44 0 1606 351006 Fax 44 031606 35100778 Email sales kanecomputing com Web www kanecomputing co uk Orsys Orth System GmbH Am Stadtgraben 25 88677 Markdorf Germany http www orsys de LOS Date 28 November 2005 KJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU pO Contents 1 PREFACE EE 6 1 1 Document Organlzatlon rre tintas check a davsaeescenenteesexsansusseeanancneseseusseeeiie 6 1 2 Documentation Overview ee 6 1 3 Notational COMVEMUUONS uso iria UR aas PAY aant Dc Sei n D E d at cn E 6 MEI E E A 7 15 Revision HISIOLV auiicniskanbxiarbniszEAKE c DOOJIRERERAEXRREERERRKUIE S aXRUXRRU PURA UN SASE ER ULUU KU EEAANEER NI NMAUIER 8 2 HARDWARE IN EE Nee geed dE dE 9 2 1 Block Diagram of the C6713U PU eessen tisse dn Seege EENS SEENEN 10 2 2 0 1 o E 12 e 12 KC WEE MEET Ee 12 2 3 Interfaces and Hardware COMPONENUG ccccceeeeeeesseeeeeeeeeeeeeeeeeeeneeseeneeeeeeeenseeeeeeeeeeeeeaeeeas 12 E Ne E 12 2 3 2 External Memory on board SDRAM i ssicciccccatsssatscosseceteeacesvisecencocnienaseasavasneeceeedsanniadencetaenns 13 239 3 Fash TE 14 234 NL NP
5. ccssescccccccceeeeeeeeeeseeeceeeeeeneesseseeceneeeeeees 48 7 3 2 Output Voltage Levels for non FPGA Signals AAA 48 7 3 3 Allowed Output Loads AA 48 T A S pply Voltage M 49 N urge tug gere ees ce cas cca cao eaaa EAE Raa 49 EG FRE UU ER 49 Ff Ambient TemperalUFre ues coni ini a RUE EM A ARA ASQ dA OCDE GIA EQUUM LU DUX RID NER RUHK E da EE 49 2 Ambient e tr e 49 L9 Dimensions of the Board siissivcsscicsssisnasiecsscisssareseaseasasessacnenciasasnsstsnevedcereseasniienesasniesaanienesnnnsas 50 7 10 Spare micro line Connectors essere rennen nennt tenete ttn setenta atrae sean 52 8 LIST OF ABBREVIATIONS USED IN THIS DOCUMENT eene 53 9 LITERATURE REFERENCES iiisesobrbxin bonis Gre pln cand S Uwe ple du aw x Cbr SUVS ERE CN EG 54 LO Date 28 November 2005 KJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU E List of Tables Table 1 Memory map of the prorceseor emnes 20 Table 2 Memory map of the C6713CPU sssssssssssssee een e nennen nen nn nenn nnns 21 Table 3 default initialization values for the FPGA related CE space registers 23 Table 4 CE2 default configuration eegene 23 Table 5 CE3 default ComiQurationisaccccidvcaieecedsccnedexcarextandcerentscartecaadsbhencbecceubeeeebese siethecataereudveabateueds 23 Table 6 PLD and UART registers of the CG T2CHP
6. e f configured for McBSP usage this pin is the receiver clock input or output of McBSPO The receiver clock signal can be either supplied by an external clock or can be provided internally and then supplied to the pin If the receiver port function is not needed CLKRO can also be used as general purpose UO pin e f configured for McASP usage this pin is the receive bit clock of McASPO CLKRO has a 22R series resistor How to use this pin is described in 4 6 and 7 CLKXO0 ACLKXO This pin has a dual function e f configured for McBSP usage this pin is the transmitter clock output or input of McBSPO This transmitter clock can either be supplied by an external clock or can be provided internally and then supplied to the pin If the transmitter port function is not needed CLKXO can also be used as general purpose UO pin e If configured for McASP usage this pin is the transmit bit clock of McASPO CLKXO has a 22R series resistor How to use this pin is described in 4 6 and 7 LOS Date 28 November 2005 e HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG OFSYS MICRO LINE C6713CPU RARE FSRO0 AFSRO This pin has a dual function e If configured for McBSP usage this pin is the receiver frame sync input or output of McBSPO If frame synchronization is provided by an external device FSRO is an input If the frame synchronization signals are generated internally by processors sample rate gener
7. C6713CPU FPGA Programming Guide 22 ce713cPu reca pg pat Describes how to develop customized FPGA designs Part of the FPGA development kit Micro line Power Supply Kit 23 Pewex suppiy pat Describes the micro line Power Supply board Reference documents that contain further information are listed in chapter 9 Literature References References to these documents are given in square brackets throughout this document 1 3 Notational conventions Names of registers bit fields and single bits are written in capital letters Example HWCFG Names of signals are also given in capital letters active low signals are marked with a at the beginning of the name Example RESETIN LS Date 28 November 2005 iJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU oo Configuration parameters function names path names and file names are written in italic typeface Example dev_id Source code examples are given in a small fixed width typeface Example int a 10 Menus and commands from menus and submenus are enclosed in double quotes Example Create a new project using the Create Project command from the File menu The members of a bit field or a group of signals are numbered starting at zero which is the least significant bit Example CFG 4 0 identifies a group of five signals where CFGO is the least significant bit and CFGA is the most significant bit If neces
8. 2 5 5 Multi channel Buffered Serial Ports McBSP The TMS320C6713 DSP provides two independent McBSPs Each port can communicate a full duplex continuous data stream at rates up to 75 Mbps These ports can be used for inter processor communication as well as for connecting industry standard peripheral devices like audio codecs A D or D A devices etc An implemented multi channel protocol which provides up to 128 channels additionally opens a variety of applications such as T1 E1 framers MVIP framers etc The McBSPs are compatible to other standard synchronous serial interfaces from Texas Instruments TMS320C2000 or C5000 DSP families and can be programmed to be compatible with many other vendors synchronous serial interfaces They consist of the signals DRx data receive DXx data transmit CLKRx clock receive CLKXx clock transmit FSRx frame sync receive and FSXx frame sync transmit Additionally the TMS320C6713 DSP supports a CLKSx clock source signal The x in the signal names represent the port number and are O or 1 for McBSPO or McBSP 1 respectively The above mentioned signals can also be used as software controllable digital general purpose inputs or outputs Possible general purpose inputs are DRx CLKRx CLKXx FSRx FSXx and CLKSx Possible general purpose outputs are DXx CLKRx CLKXx FSRx and FSXx On the TMS320C6713 DSP the McBSP peripherals share signals with e McASP 0 e PCH On the C6713CPU board all McBSP
9. 5 6 7 8 kel d kel c 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Texas Instruments website at www ti com Xilinx website at www xilinx com TMS320C6000 Technical Brief Tl spru197 TMS320C6713 floating point digital signal processor data sheet Tl seRs186 TMS320C6000 CPU and instruction set reference Tl sPRU189 TMS320C6000 peripherals reference guide Tl sprui90 TMS320C6000 DSP Multichannel Audio Serial Port McASP Reference Guide Tl spruo41 TMS320C6000 DSP Software Programmable Phase Locked Loop PLL Controller Reference Guide Tl spru233 TMS320C6000 DSP Inter Integrated Circuit I2C Module Reference Guide Tl spru175 TMS320C6713 Errata Sheet Tl sprzi91 Manual Update Sheet for TMS320C6000 Peripherals Reference Guide SPRU190 Tl sprzi22 application report Applications Using the TMS320C6000 Enhanced DMA Tl seRAes6 application report 7MS320C621x TMS320C671x EDMA Queue Management Guidelines Tl SPRA720 How to Begin Development Today With the TMS320C6713 Floating Point DSP Tl sprasos Optimizing C Compiler user s guide Tl spruis7 TMS320C 6000 Assembly Language Tools User s Guide Tl spruise TMS320C62x C67x Programmer s Guide Tl spruigs TMP100 temperature sensor data sheet Tl spos231 MX29LV160CT CB 16 Megabit Flash Memory Macronix pmiise C6713CPU DSP Development Kit User s Guide Orsys cez13cPu Dep Devkit ug C6713CPU micro line
10. In contrast to previous micro line CPU boards the C6713CPU does not allow stacking other boards on top of it However peripheral boards are stackable PCB NENNEN m 6 0mm 2 54mm 0 635mm Figure 14 C6713CPU connector pins The tables below give part number examples for spare micro line connectors that can be used to build customized carrier boards or peripheral boards Manufacturer fischer Elektronik www fischerelektronik de xx 7 number of pins 1 32 for single row 2 64 for double row Connector type CPU board not stackable SL LP 1 112 xx G double mom SL LP2 112 xx G Carrier board not stackable BL1 xx or BL 5 xx BL 2 xx or BL 6 xx peripheral board stackable Manufacturer Preci DIP www precidip ch xx number of pins 1 32 for single row 2 64 for double row Connector type CPU board not stackable double row Carrier board not stackable single row 801 pp xx 10 001001 803 pp xx 10 001001 peripheral board stackable 801 pp xx 53 001001 803 pp xx 53 001001 C Date 28 November 2005 HARDWARE REFERENCE GUIDE Doc no C6713CPU HRG orsys MICRO LINE C6713CPU or oe 8 List of abbreviations used in this document BSP CCS CPU DMA DSP e g yEM EMIF board support package a combination of software and FPGA design that provides further functionality to the C6713CPU Code Composer Studio Tl s development environment Central Processing Unit processor direct
11. fgetc etc are executable by the application program on the micro line C6713CPU using the RS 232 interface as a communication channel e g to transfer measurement results to a host system or to control a connected peripheral device Another common usage of the RS232 interface is to output debugging information during testing The interface consists of the signals TxD transmit data RxD receive data RTS request to send and CTS clear to send These signals are available at the micro line connector Please refer to chapter 6 1 for details The CTS input signal can also be configured in a way to generate a system reset on the C6713CPU board The UART of the default micro line busmaster BSP can operate at programmable baud rates up to 1Mbaud The RS 232 line driver can be switched into shutdown mode to reduce power consumption Please see chapter 3 10 4 for details Please note When using the RS 232 interface in conjunction with a PC that runs Windows 2000 or XP the transmit buffer settings of the PC s COM port must be changed on the PC as described for the Flash File System installation in 24 2 3 6 Temperature Sensor The C6713CPU has an onboard temperature sensor with a serial I C Bus interface in order to determine the board temperature during operation The sensor can measure a temperature range from 25 C up to 85 C with an accuracy of 2 degrees and 55 C up to 125 C with an accuracy of 3 degrees If the C6713CPU is
12. the DSP boots from the first address of the flash memory The DSP internal boot loader copies the first 1 KB to internal memory to address 0 and executes it Further loading is realized by a secondary loader program The C6713CPU is always shipped with the Flash File System installed It handles all flash memory programming and management of stored data The Flash File System is automatically booted after reset or power up It first initializes the system then looks for commands from a host on the RS 232 interface See 24 for a description of the host side utilities and then loads the FPGA s and a user program that are selected for auto boot Since RS 232 usage on the C6713CPU requires a loaded FPGA design the Flash File System already contains a startup FPGA design which is loaded during system startup Later on it will be overwritten when the on board auto boot FPGA is loaded 2 3 4 PLD The PLD contains some necessary glue logic of the board It provides all necessary resources to run the DSP without a loaded FPGA It also contains some register that configure board operation See chapter 3 10 for a description of the PLD registers 2 3 5 UART RS 232 Interface The RS 232 interface is realized inside the FPGA and is connected to a RS 232 line driver Therefore to use the RS 232 interface an appropriate FPGA design must be loaded The RS 232 interface can be used as general purpose communication interface Functions like fprintf and
13. 56 8000 0002h 34 8000 0003h 12 LN Date 28 November 2005 J HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU p 3 8 EMIF Configuration All accesses to off DSP chip peripherals such as on board SDRAM the UART or the FPGA are performed by the DSP s external memory interface EMIF The timings and interface type for these accesses can be software programmed separately for each CE space see Table 2 for an overview of the CE space usage 3 8 1 Default EMIF configuration When the C6713CPU is reset or powered on it automatically boots the Flash File System which initializes the EMIF to a safe timing This timing can be used for many applications so that no further EMIF initialization is necessarily required However I O performance can be optimized by application software by faster accesses to the FPGA and off board peripherals This can be done by modifying the timing settings for the CE2 and CE3 address spaces Examples for this can be found in the software examples that are shipped with the C6713CPU CE space configuration register 32 bit initialization value 32B3 8A23 32B3 8A13 Table 3 default initialization values for the FPGA related CE space registers ma Read hold time Write set up time Write strobe time Write hold time Table 5 CE3 default configuration 3 9 Description of the PLD Board Registers The PLD board registers
14. LED controlled by the FPGA LOS Date 28 November 2005 e HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG OFSYS MICRO LINE C6713CPU a 2 4 4 User Programmable LED s PLD These LED s are controlled by PLD registers see chapter 3 10 They can be switched on and off by application software to display certain events or states Examples for software controlled usage of the LED s are e displaying an error condition by the red LED e checking software activity by toggling one of the LED each time the main loop is executed e DSP load indicator flashing the LED during interrupt handlers or calculations Furthermore the green LED can automatically be driven by other hardware activities e CE1 is active PLD or UART is accessed e Flash is accessed default 2 4 2 User Programmable LED FPGA A yellow LED is directly connected to the FPGA The function is defined by the respective FPGA design or BSP and is described in the BSP documentation 2 5 DSP peripherals The TMS320C6713 DSP has a number peripheral interfaces integrated on the chip These interfaces are described briefly in this chapter Hardware and programming details can be found in the respective literature from Texas Instruments 6 to 9 Some of the DSP peripheral interfaces share pins with others Therefore care must be taken when using multiple peripherals to ensure that all interfaces are available at the same time 2 5 4 Multichannel Audio Serial Por
15. and 5 At the TMS320C6713 DSP hardware interrupt lines are shared with GPIO signals and McASP ports On the C6713CPU board the DSP interrupt lines EXT_INT4 and EXT_INT5 are directly connected to the micro line connectors EXT_INT4 EXT_INT5 as well as to the FPGA The remaining interrupt lines EXT_INT6 EXT_INT7 and NMI are only connected to the FPGA Therefore EXT_INT6 EXT_INT7 and NMI are typically used for on board interrupt sources while EXT_INT4 and EXT_INT5 can be used for both off board and on board interrupt sources Care must be taken that EXT_INT4 and EXT_INT5 are only driven by a single source that is either the FPGA or an external hardware on the micro line bus The default micro line busmaster BSP provides programmable interrupt polarity and routes EXT INT 7 6 and NMI to the external connectors sot that EXT INT 7 4 and NMI are available at the micro line connectors For proper interrupt operation application software must set up the interrupt configuration so that EXT INT 7 4 are falling edge triggered this can be done either by writing to the EXTPOL register or by using an appropriate DSP BIOS configuration file see 20 LOS Date 28 November 2005 KJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU E 2 5 9 DMA The TMS320C6713 DSP provides an enhanced DMA EDMA controller with 16 channels and 16 possible synchronization events It can be used to tra
16. are e digital control line for external hardware e digital input for reading the status of external hardware 7 6 5 4 3 XF1_DIR XF1 DATA XFO DIR XFO DATA RESERVED r w O r w r w 0 rw XF1 DIR controls the direction of the XF1 pin If XF1 DIR is set to 1 XF1 is an output In this case XF1 DATA is read and writeable The XF1 pin reflects the status of XF1 DATA GEI DATA 1 sets the XF1 pin to 3 3 V If XF1 DIR is set to 0 XF1 is an input In this case XF1 DATA is read only and reflects the status of the XF1 pin XF1 gt 2 0 V XF1 DATA 1 XF1 0 8 V XF1 DATA 0 XFO DIR and XFO DATA have the same functionality but for the XFO pin Both the XF1 pin and the XFO pin are configured as inputs after reset or power up 3 10 7 Watchdog Register WDG This register controls operation of the watchdog timer Application software can enable the watchdog timer to reset the whole system if the system is no longer working properly 7 6 5 4 3 RESERVED WDG RST WDG EN RESERVED r 00 w 0 r WU LN Date 28 November 2005 KJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU E WDG RST The WD RST pin of the PLD is connected to the watchdog input of the reset generator If the watchdog is enabled the WD RST pin must be set to 1 at least once per second This must be done by writing a 1 to the WDR RST bit of this register The WDR RST bit is self
17. are mapped into the DSP s CE1 address space Table 6 lists the address map of all board registers The register mnemonics are used in this documentation as well as in the software that is shipped together with the board 1 These initialization values are only valid for an EMIF clock setting of 90MHz If another EMIF clock is used these settings may be different Ly Date 28 November 2005 AJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU E Page 9010 0000h Hardware configuration register HWCFG 9011 0000h FPGA control register 9012 0000h LED control register MCR MCR Watchdog register 9017 0000h PLD version register VER Table 6 PLD and UART registers of the C6713CPU 3 10 Description of the PLD Registers The PLD registers are all 8 bit wide and can be accessed as 8 or 16 bits All writeable bits can be read back so they can be modified without keeping a shadow register copy in memory Bits O 3 of all PLD registers are reserved The read back value of these reserved bits is not defined Name Address Bit 7 Bit 6 Bit 5 Bit 4 HWCFG 90100000 RAMSIZE CPUSPEED RESERVED FLASH A19 90110000 PROG DONE CFG EN RESERVED 90120000 LED RED LED GREEN CTS RESET EN XF VER SCL STAT 90150000 XEO DIR WDG RST Jupe EN VER eo170000 VERSION Table 7 PLD register quick reference 3 10 1 Hardware Configuration Register HWCFG This register provides information ab
18. clearing Application software should access this bit from within a function that must be periodically usually the main loop It should not be accessed from an interrupt service routine WDG EN If the WDG EN is set to 1 the on board watchdog is enabled A reset will be generated whenever the watchdog timer expires This bit is set to O after a hardware reset and can only be set but not be cleared by application software Thus if the watchdog is enabled there is no way to disable it 3 10 8 Version Register VER This register contains the PLD version The version number is encoded as a four bit number and is read only It may be updated due to changes of the PLD code or changes of the C6713CPU hardware Application software can read the version number in order to determine the version of the PLD code 7 4 3 0 VERSION RESERVED VERSION Applies to Comment reserved for internal use reserved for internal use First public release n a reserved for future versions of this board Table 8 Version register encoding Ly Date 28 November 2005 iJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG i Orsys MICRO LINE C6713CPU Been Page 4 Boot Process and Default Setup of the C6713CPU After reset or power up the C6713CPU boots the Flash File System from flash memory The Flash File System first checks if a command from a host PC on the RS 232 interface is pending If a command is p
19. interface usage If this pin is used for IC interface 1 then a hardware pull up resistor is required Please refer to chapter 7 2 6 for details CLKS1 has a 22R series resistor How to use this pin is described in 4 and 6 and 9 TINP1 AHCLKXO This pin has a dual function e f configured for timer usage this pin is the external clock input of timer1 Low to high transitions or high to low transitions if INVINP 1 will increment the timer counter The actual state of the TINP pin can be read by accessing the DATIN bit This makes TINP1 also usable as general purpose input pin e f configured for McASP usage this pin is the transmit high frequency master clock of McASPO TINP1 has a 22R series resistor How to use this pin is described in 4 6 and 7 TINPO AXRO 3 This pin has a dual function e f configured for timer usage this pin is the external clock input of timer 0 Low to high transitions or high to low transitions if INVINP 1 will increment the timer counter The actual state of the TINP pin can be read by accessing the DATIN bit This makes TINP1 also usable as general purpose input pin e f configured for McASP usage this pin is a bi directional data line of McASPO TINPO has a 22R series resistor How to use this pin is described in 4 6 and 7 CLKSO AHCLKRO This pin has a dual function e f configured for McBSP usage this pin is the external input of the internal sample rate ge
20. memory access a fast data transfer method Digital Signal Processor exempli gratia Latin for example electromagnetic interference external memory interface a peripheral of the TMS320C6713 DSP field programmable gate array host port interface a peripheral of the TMS320C6713 DSP id est Latin that is inter integrated circuit a low speed interface between integrated circuits 1024 byte light emitting diode least significant bit 1024 KB 1048576 byte most significant bit multi channel audio serial port a peripheral of the TMS320C6713 DSP multi channel buffered serial port a peripheral of the TMS320C6713 DSP not available not applicable not connected programmable logic device random access memory read only memory static random access memory synchronous dynamic random access memory to be changed value not 10096 tested and may change in future to be defined value is not yet specified Texas Instruments universal asynchronous receiver transmitter LO Date 28 November 2005 WS orsys MICRO LINE C6713CPU oe HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG 9 Li terature references Further information that is not covered in this user s guide can be found in the documents listed below References to this list are given in square brackets throughout this document The documents are listed by title author and literature number or file name 1 2 3 4
21. operated in an environment where it is exposed to high temperatures the temperature sensor can be used to detect over temperature conditions The LN Date 28 November 2005 iJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU E DSP internal temperature is roughly 15 degrees Celsius above the temperature measured by the sensor Software drivers for the temperature sensor are included in the development kits see 20 for details Further information can be found in 18 The temperature sensor is connected to the PLD by a separate DC interface It does not use the l C interfaces of the DSP The temperature sensor can be accessed by the lC bus control register see chapter 3 10 5 2 3 7 Reset Generator and Watchdog The C6713CPU board provides a triple voltage supervising reset generator which generates a defined reset pulse in case of one or more of the following events power up software reset via the module control register see chapter 3 10 the RESETIN pin is active low one of the supply voltages drops below a certain limit the reset generator s watchdog timer is enabled and has expired The reset function of the RS232 CTS line is activated and CTS is active During the reset pulse the micro line signals RESETOUT and RESETOUT are activated The reset generator circuit has a watchdog timer that causes a reset if it is not reset periodically by software The watchdog timer is disabl
22. the PLD registers Chapter 4 describes the boot process and the default settings of the board Chapter 5 gives a brief introduction to the Flash File System of the board Chapter 6 describes externally available signals and connector pinouts Chapter 7 lists environmental conditions such as voltage levels temperature range etc Chapter 9 lists documents that contain further information Chapter 8 explains the abbreviations that are used throughout this document 1 2 Documentation Overview This chapter lists the documentation from ORSYS that is shipped together with the C6713CPU Further documents from other vendors may also be listed in chapter 9 and are referenced throughout this document in square brackets C6713CPU DSP Development Kit User s Guide 20 cez13sceu ps pevkit ug p t This document describes software development for the C6713CPU board using DSP BIOS and the C6713CPU board library The board library is a collection of low level drivers that allow to access hardware on the C6713CPU such as loading the FPGA reading the temperature sensor etc This makes working with the C6713CPU easier C6713CPU micro line busmaster BSP User s Guide 21 cez13ceu mi bm ug pat Describes the micro line busmaster board support package BSP This BSP adds an asynchronous parallel bus peripheral interface an UART and HPI accessibility to the C6713CPU The user guide includes FPGA register description and FPGA register programming documentation
23. 1 0 DSP address lines A 23 0 digital signal ground En DSP host port interface D Power supply control signals for peripheral boards RS 232 interface DSP peripherals Table 10 Connector overview 6 3 Pinout Tables of the micro line Connector On the C6713CPU some signals have fixed functions others marked with FPGA can be used individually by a board support package such as 21 or by a customized FPGA design A detailed signal description can be found in chapter 6 5 i Connector Pin xe eue cm esu mE dE dE Ens FPGA FPGA HDO UO Power GND I FPGA FPGA FPGA HD1 I O Z Power GND I FPGA HD2 I O Z Power GND I FPGA HD3 I O Z Power GN FA D3 D I FPGA 5 1 CLKX1 OO Hbi4 OZ IL FPGA X FSX1 OZ E FPGA INT4 I FPGA INT5 I AXRO 3 OO 18 HCNTL1 1 P I CLKSO 1 AXRO 0 UO 20 FPGA HRW I AXRO 1 170 2 FPGA HWR_HSTRB I FSRO I O Z FSXO OO 2 FPGA Signal GND 2 FPGA Signal GND 28 FPGA Signal GND i Aa 23 2 N NIDA A wv ho J O E k lb aib Ib lba oy BR O hM o Signal GND FPGA Signal GND FPGA SCLO FPGA HOLD I FPGA FPGA Signal GND FPGA SDAO FPGA HOLDA O Signal GND Table 11 Pinout of the micro line connectors oe oe ee n5 N ol dc N LN Date 28 November 2005 AJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713
24. 32 line driver in shut down mode see chapter 3 10 4 RTS This pin is the ready to send output of the RS 232 interface Output voltage is either 5 5 V typical or 5 5 V typical This output can be disabled by putting the RS 232 line driver in shut down mode see chapter 3 10 4 RTS is set to 5 5 V by a pull up resistor on the line driver input when the FPGA is not loaded RXD This pin is the receive data input of the RS 232 interface This pin accepts RS 232 signal levels from 10 V to 10 V An internal 5kQ pull down resistor to GND is integrated in the line receiver CTS This pin is the clear to send input of the RS 232 interface This pin accepts RS 232 signal levels from 10 V to 10 V An internal 5kO pull down resistor to GND is integrated in the line receiver The CTS pin can also be used as a reset input The reset generation is controlled by the PLD see chapter 3 10 4 Pin D30 This signal is routed to the FPGA Usage of the signal requires either an ORSYS board support package or a custom FPGA design In default hardware configuration this signal is pulled high by a 4 7KQ pull up resistor Hardware configuration can also be changed to a pull down resistor see chapter 7 2 4 for details HOLD pin D31 This signal is routed to the FPGA and to the HOLD pin of the DSP If this signal is driven by the FPGA it should not simultaneously be driven by an external source via the micro line pin The C6713CPU board pro
25. Busmaster Board Support Package Orsys cez13cPu wn BM ug C6713CPU FPGA Programming Guide Orsys ce713ceu rFPGA pg Power Supply Board OrSys power supply Flash File System User s Guide Orsys zez ug
26. CPU E Default shared with signal name Interface signal McASPO AXRO O E20 Keele ERE McASPO CLKS1 SCL1 E16 Table 12 Pinout summary for the McBSP interfaces Default shared with micro line connector signal name interface signal eae emer TOUTO McASPO AXRO 2 TINPO TOUT1 TINP1 AHCLKXO Table 13 Pinout summary for the timers Default shared with micro line connector signal name interface signal GE o T G Table 14 Pinout summary for the UC interfaces TI TI TI TI SEEKSIESEREIERE DIA gt X A EE gt m e o e e em e NJ LJ y HARDWARE REFERENCE GUIDE orsyS MICRO LINE C6713CPU Date 28 November 2005 Doc no C6713CPU_HRG Iss Rev 1 1 Page 34 interface signal AXRO 7 McBSP AXRO 5 RO 4 Timer ROL RO 2 TOUTO E28 DRO E20 FSRO AFSXO AMUTEO interrupt EXT INT5 HPI AXR1 6 AXR1 5 AXR1 4 AXR1 3 AXR1 2 AXR1 1 R1 0 ACLKR1 AHCLKR1 AFSR1 ACLKX1 AHCLKX1 AFSX1 AMUTE1 GPIO GP4 D17 interrupt EXT INT4 Table 15 Pinout summary and signal routing for the McASP interfaces 25 ARRE EE ell EE oX DoS z SA ACLKXO AHCLKXO AFSXO AMUTEO AMUTEINO AXR1 7 AXR1 6 AXR1 5 AXR1 4 AXR1 3 AXR1 2 AXR1 1 ACLKR1 AHCLKR1 AFSR1 ACLKX1 AHCLKX1 AFSX1 AMUTE1 AMUTEIN1 Ly Date 28 November 2005 iJ HARDWARE REFERENCE GUIDE Doc
27. CPU p 7 6 5 4 3 SDA STAT SDA CTL SCL STAT SCL CTL RESERVED r 1 r W 1 r 1 r w 1 SDA STAT retrieves the current state of the SDA line If this bit is read as 1 the SDA line is in a logic high state and no device pulls the line low If O is read from this bit the SDA line is pulled low by either the PLD SDA_CTL bit or the temperature sensor SDA CTL controls the SDA line If this bit is set to 0 the SDA line is pulled low by the PLD If this bit is set to 1 the SDA line is not driven by the PLD In this case the SDA line may be at logic high level if the temperature sensor does not drive this signal line is then pulled high by a pull up resistor or at logic low level if the temperature sensor pulls SDA low SCL STAT retrieves the current state of the SCL line Since the PLD is the only clock source of the local DC bus it will always reflect the status of the SCL_CTL bit SOL CIE controls the SCL line If this bit is set to 0 the SCL line is pulled low by the PLD If this bit is set to 1 the SCL line will be released so it will become high by its pull up resistor 3 10 6 External Flag Register XF The C6713CPU provides two digital I O pins called external flags XFO XF1 These I O pins are available at the micro line connectors They are controllable by the external flag register Each XF pin can be programmed to be either an input or an output Application software can use the XF pins for any I O purposes Examples
28. DWARE REFERENCE GUIDE Doc no C6713CPU HRG Iss Rev 1 1 orsys MICRO LINE C6713CPU ee 2 1 Block Diagram of the C6713CPU TMS320C6713 DSP micro line connector on chip peripherals JTAG connector host port control host port data EMIF Xilinx Spartan 3 200k 400k 1M gates PLD temperature sensor converter user LEDs power supply Figure 1 Block diagram of the C6713CPU LY orsys HARDWARE REFERENCE GUIDE MICRO LINE C6713CPU Date 28 November 2005 Doc no C6713CPU_HRG Iss Rev 1 1 Page 211 green LED PLD red LED PLD yellow LED FPGA JTAG connector micro line connectors flash memory FPGA o Fama z TE Re P x um oH Lo B Sur PD S geb zz mmm G Ze el cm eee DSP temperature SDRAM sensor Figure 2 Top side of the C6713CPU micro line connectors SDRAM Figure 3 Bottom side of the C6713CPU 16 bit HPI data bus transceiver LS Date 28 November 2005 KJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU p 2 2 Connectors 2 2 1 micro line Connectors The micro line connectors are the main I O connectors of the C6713CPU They provide access to all signals that are needed for a wide range of I O connectivity The signals on the micro line connectors can be grouped into the following categories e power supply e DSP and board specifi
29. FSYS MICRO LINE C6713CPU a e CEO is used for on board SDRAM e CE1 is used for on board flash memory PLD and FPGA registers e CE2 and CE3 are used for the FPGA Please refer to chapter 3 for further descriptions of the CE spaces and their address ranges 2 5 3 Inter Integrated Circuit lC Interfaces The TMS320C6713 DSP provides two IC interfaces These 2 wire interfaces can be used for accessing peripherals like temperature sensors EEPROMS A D and D A converters etc The I C interfaces are described in detail in 4 and 9 At the TMS320C6713 DSP the signals of DC interface 1 are shared with signals of the McBSP interface 1 Chapter 6 3 shows the shared signals By default the C6713CPU board only provides the l C interface 1 of the TMS320C6713 DSP If the DC interface 0 is also needed for a certain application a slight hardware reconfiguration of the C6713CPU board is necessary In this case please contact ORSYS 2 5 4 General Purpose Input Output Pins GPIO At the TMS320C6713 DSP a couple of GPIO pins are shared with the Host Port Interface HPI The HPI is enabled by default therefore the GPIO signals are not available Instead of DSP GPIO pins a number of other software programmable digital I O pins can be used e External flags XFO SEI e Timer signals TINPO TINP1 TOUTO TOUT1 e McBSP signals see 6 chapter McBSP Pins as General Purpose I O e Free FPGA pins requires a BSP or custom FPGA design
30. SRAM can be accessed simultaneously 3 4 DSP Peripherals The DSP peripherals are briefly explained in chapter 2 5 Their addresses are defined in 4 3 5 External SDRAM The external SDRAM of the C6713CPU is mapped into the processor s CEO address space This memory can be used for user applications and or data storage The external SDRAM address space starts at address 8000 0000h regardless of the memory size and ends at 8000 0000h SDRAM size The upper 1400h bytes of the SDRAM are reserved for usage by the Flash File System and should not be used for initialized sections text cinit etc of user applications The external SDRAM is typically used for large buffers and code or data that is not extremely time critical For time critical code or data internal fast SRAM should be used Please note that using the cache speeds up external SDRAM accesses significantly 3 6 Flash Memory The Flash memory is mapped into the processor s CE1 address space together with PLD and FPGA registers The flash size is 2 MB however the address space for the flash memory is divided into 2 parts each of them holds 1 MB of data The upper and lower segment can be accessed with the FLASH A19 bit in the MCR register as described in chapter 3 10 The flash memory can be programmed in units of sectors most of them are of 64 KB size with exception of the first 4 sectors See 19 for details The C6713CPU is shipped with the Flash File System software instal
31. Sep EA n m H SES SR Sami a ru ZE ESE e H E E F we WI PE Hm rir 54 m 0 2 54 CH Ww wo dg e io CH m te maximum heigh of components Figure 12 Dimensions of the C6713CPU in millimeters In case of a customized carrier design it is recommended to reserve some more space additionally to the existing micro line connectors of the C6713CPU This space does not necessarily need to be mounted with connectors It is only recommended not to place components into this region This allows to mount micro line peripheral boards and or future micro line processor boards in the same socket The full micro line footprint is listed below Recommended keep out areas are connector rows A B BB C D E for CPU boards and A B BB C D E EGND 1 4 P X1 X10 for peripheral boards Rows EE 1394 1 1394 2 EGND5 and X11 16 are very unlikely to be used and can therefore be used for placing components Date 28 November 2005 LF y HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU po MEZANI 78 14 571 254 5 08 7 62 1394 2 1394 1 EGND 15 24 17 78 17 78 Figure 13 Complete micro line footprint 66 04 Ly Date 28 November 2005 iJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU or ia 7 10 Spare micro line Connectors The C6713CPU uses square connectors with 0 1 inch 2 54 mm spacing
32. System see chapter 2 3 3 This FPGA design leaves all external pins passive except the RS 232 interface For a more detailed description of the FPGA signals please refer to the documentation of the micro line busmaster BSP 21 or FPGA development 22 2 3 2 External Memory on board SDRAM The C6713CPU uses 32 bit wide SDRAM with 32 or 64 MB in standard off the shelf versions and up to 128 MB on request This provides a large memory space for storage of program code or data The memory access timings are based on the EMIF clock which is initialized to 90 MHz 225 MHz CPU clock or 100 MHz 300MHZ CPU clock by the Flash File System The EMIF clock LOS Date 28 November 2005 e HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG OFSYS MICRO LINE C6713CPU ee can be software reconfigured by PLL settings It can also be generated by the FPGA allowing any clock frequency up to 100 MHz Compared to the internal fast SRAM of the DSP chip the on board SDRAM is significantly slower Therefore it is strongly recommended to use the internal memory of the DSP whenever it is possible The internal memory can be used as memory for time critical code and data as well as L2 cache See 4 for details 2 3 3 Flash Memory The C6713CPU uses an MX29LV160BT flash memory for non volatile storage The flash memory is 16 bit wide and can hold up to 2 MB It is used for permanent storage of software and FPGA code After reset or power up
33. TOUTO can also be used as general purpose output e f configured for McASP usage this pin is a bi directional data line of McASPO See also chapter 7 2 TOUTO has a 22R series resistor How to use this pin is described in 4 6 and 7 TOUT AXRO 4 This pin has a dual function e f configured for timer usage this pin is the output of timer 1 The timer output can e g trigger an external A D converter to start a conversion If the timer clock output function is not needed the TOUT1 can also be used as general purpose output e If configured for McASP usage this pin is a bi directional data line of McASPO See also chapter 7 2 TOUT1 has a 22R series resistor How to use this pin is described in 4 6 and 7 Ly d HARDWARE REFERENCE GUIDE e orsyS MICRO LINE C6713CPU Date 28 November 2005 Doc no C6713CPU_HRG Iss Rev 1 1 Page A3 Pins E30 and E31 These signals are routed to the FPGA Usage of these signals requires either an ORSYS board support package or a custom FPGA design These signals are pulled up by the FPGA as long as the FPGA is not loaded and have 22R series resistors Signal GND This is one further signal ground pin of the micro line connector orsys HARDWARE REFERENCE GUIDE MICRO LINE C6713CPU Date 28 November 2005 Doc no C6713CPU_HRG Iss Rev 1 1 Page 44 7 Environment 7 1 Minimum Connections This chapter shows ho
34. The Flash File System supports storage and boot sequence management for both FPGA code and DSP applications For correct operation of the Flash File System it is recommended that the CTS reset feature is enabled in the PLD see chapter 3 10 4 for details This allows the Flash File System to interrupt the currently running program and to connect to the C6713CPU If the CTS reset feature is disabled the C6713CPU must be reset manually A detailed description of the Flash File System is given in 24 fy orsys HARDWARE REFERENCE GUIDE MICRO LINE C6713CPU Date 28 November 2005 Doc no C6713CPU_HRG Iss Rev 1 1 Page 31 6 Description of the micro line Board Connectors 6 1 Location of the Connectors For the micro line connectors Pin 1 is marked by a black square in Figure 6 connector A connector B connector BB X JTAG connector connector D connector E Figure 6 Connector locations W LN Date 28 November 2005 AJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU ot ia 6 2 Connector Overview Table 10 gives an overview about usage of the micro line connectors including the classic usage as peripheral interface as used with previous CPU boards The classic peripheral interface is implemented in the micro line busmaster BSP which is described in 21 Connector Default micro line bus usage DSP data lines D 3
35. U HH 24 Table 7 PLD register quick reference sssssssssssssseee nne 24 Table 8 Version register BOO GING dcnctidamcassnaachtiet dated bana dunchcecendeandip sete nbtetaniniastelssepbcebeldduaadguadeetieis 28 Table 9 Default clock and EMIF settings of the C6713CPU ccc cccceeeeeseeeeneeeeeeeeeeeeeeeteneeeeeeees 29 Table 10 Connector OVErViCW cccccecceeccceceeeeeeceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeceeeeeeeeseeeeeeeeeeeeeneeteess 32 Table 11 Pinout of the micro line connectors ssssseseeeee enne 32 Table 12 Pinout summary for the MCBSP mtertaces 33 Table 13 Pinout summary for the timers est idet ape nti pant tts aua aont ud A a a run rU a A pad RM a d Meg 33 Table 14 Pinout summary for the l C interfaces tentent ces 33 Table 15 Pinout summary and signal routing for the McASP interfaces sssssssssss 34 Table 16 Pinout of the JTAG connector sssssssssssssseee mener 35 Table 17 Factory default configuration summary essen 46 Table 18 Voltage limits for the CpG 2CHU Hee 49 Table 19 Power consumption of the CG 12CHRU nennen nnn nnns 49 Table ZOE Reset timiNg EE 49 List of Figures Figure 1 Block diagram of the LE enges artt torna pa il ern t egeereR eege 10 Figure 2 Top side of the C57 Eege eebe gebeten RM Ds EES 11 Figure 3 Bottom side Of the Cor T9 PLI uu deiectis ated te daxb tentant th dpa brikaad Adae dE Resa a ge
36. U ORSYS recommends the desk carrier micro line PowerSupply board which provides 3 3 V regulated power supply for the C6713CPU a 9 Pin SUB D connector for the RS 232 interface a reset button Two isolated x15 V DC DC converters for peripheral I O power supply optional ORSYS furthermore offers complete development packages including Code Composer Studio XDS510 JTAG emulator debugger or equivalent types and all necessary accessories like cables power supplies and software libraries This documentation describes the basic features of the C6713CPU It does not include details of the FPGA or the DSP For further information about the FPGA please refer to Xilinx 2 For further information about the DSP please refer to Texas Instruments 1 A good starting point is also the chapter documentation support in 4 Many operational features of the C6713CPU require the use of a specific FPGA design which is provided by an according board support package BSP The FPGA of the C6713CPU can be used either with the default BSP from ORSYS which is pre installed when the C6713CPU is shipped or with individual custom designs using the FPGA development option The default BSP from ORSYS allows to operate the C6713CPU as a standard micro line DSP board In this case it is logically upward compatible to other existing micro line products such as the C6711CPU if the C6711CPU is operated with 3 3V only my Date 28 November 2005 AU HAR
37. ad the FPGA Application software does not need to access this register The FPGA can be loaded at any time and it is also possible to reload it during runtime with a different design 7 6 5 4 3 0 PROG DONE CFG EN RESERVED RESERVED r w O r 0 r w O r 0 PROG This bit controls the PROG_B input line of the FPGA This bit only has an effect if CFG_EN is set to 1 Please refer to the FPGA development kit documentation for details During reset the PROG B signal of the FPGA is active independent of the state of the PROG bit This clears the FPGA on reset PROG PROG pin O driven high idle has no effect on the FPGA driven low FPGA is cleared DONE This bit allows to read back the status of the FPGA DONE output line Please refer to the FPGA development kit documentation for details O the FPGA isn t configured yet CFG_EN This bit switches the dedicated configuration signals of the FPGA to idle states so that no current flows from the 3 3V PLD into the 2 5V configuration inputs of the FPGA The user must set this bit to 1 before starting the configuration of the FPGA and reset it to O after completion of the configuration process Please refer to the FPGA development kit documentation for details CFG_EN 0 FPGA configuration isn t possible FPGA configuration signals are driven 3 10 3 LED Control Register LED This register can be used by application software to control the tw
38. ator FSRO is an output If the receiver port function is not needed FSRO can also be used as general purpose UO pin e f configured for McASP usage this pin is the receive frame sync or left right clock of McASPO FSRO has a 22R series resistor How to use this pin is described in 4 6 and 7 FSX0 AFSX0 This pin has a dual function e f configured for McBSP usage this pins is the transmitter frame sync output or input of McBSPO If frame synchronization is provided by an external device FSXO is an input If the frame synchronization signals are generated internally by the processor s sample rate generator FSXO is an output If the transmitter port function is not needed FSXO can also be used as general purpose UO pin e f configured for McASP usage this pin is the transmit frame sync or left right clock of McASPO FSXO has a 22R series resistor How to use this pin is described in 4 6 and 7 XFO XF1 These pins are dedicated general purpose digital input output pins of the micro line bus They can be programmed separately in order to function as outputs or inputs For further information refer to the description of the external flag register in chapter 3 10 6 TOUTO AXRO 2 This pin has a dual function e f configured for timer usage This pin is the output of timer 0 The timer output can e g trigger an external A D converter to start a conversion If the timer clock output function is not needed the
39. ay damage the board Board type minimum allowed supply voltage maximum allowed supply voltage C6713CPU 3 25 V 3 35 V Table 18 Voltage limits for the C6713CPU 7 5 Power Consumption The typical power consumption is shown in the following table Please note that the power consumption strongly depends on I O pin usage and the FPGA design Typical power consumption Toggle led 1 example any board FPGA loaded 460 mA Toggle led fpga example any board FPGA loaded 470 mA Table 19 Power consumption of the C6713CPU 7 6 Heset Timing Parameter Min Typ Mex RESETIN pulse width i 1 U RESETOUT pulse width Watchdog timeout fis Table 20 Reset timing 7 7 Ambient Temperature Storage temperature 25 85 C Operating temperature 0 70 C Extended temperature versions are available on request 7 8 Ambient Humidity Storage with up to 90 humidity non condensing Operating with up to 85 humidity non condensing LN Date 28 November 2005 iJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU E LED 7 9 Dimensions of the Board Figure 12 shows the dimensions of the C6713CPU When the C6713CPU is stacked with other modules board spacing is 14mm 97 54 90 17 78 74 m m Se Ell m Hi LU ER ep us ZEN 2 S DR EN Z E SH Hx ZS m z at MIL Koo Im mm ES wa NH NE QD O W 1 OO WE NN
40. c interfaces such as timers and serial ports e FPGA specific signals their function depend on the respective FPGA design Historically without FPGA the micro line connectors carried the following signals e power supply e DSP and board specific interfaces such as timers and serial ports e the micro line peripheral interface which allowed straightforward access to peripherals Today with FPGA technology onboard many of the micro line UO signals can be individually hardware configured for nearly any application This is possible by building an individual application specific FPGA design which exactly covers the application s requirements Nevertheless the micro line standard peripheral interface is still available as a board support package the micro line busmaster BSP It is the default configuration when the C6713CPU board is shipped from ORSYS The pinning of the micro line connectors without any particular FPGA design loaded is described in chapter 6 The pinning and functionality of the micro line busmaster BSP is described in 21 2 2 2 JTAG Connector The JTAG connector is used during development of application software or FPGA designs It contains two separate JTAG interfaces one for the DSP and one for the FPGA The DSP JTAG interface is used for debugging and application software download during development together with Texas Instruments Code Composer Studio and an XDS510 or similar emulator After the softwar
41. cro line connectors is at a voltage of 3 to 10 V Setting CTS RESET EN to 0 enables normal usage of the CTS signal as a RS232 handshake signal The CTS reset feature is used by the Flash File System commands to interrupt normal operation and to connect to the C6713CPU Note When CTS RESET ENiis set to 1 and the C6713CPU board is connected to a terminal the terminal may cause periodic resets In this case either disconnect the terminal or disable the CTS reset function for normal operation RS232 DRV EN This bit controls the RS232 driver If this bit is set to 1 the RS232 line driver is enabled 3 10 5 I C Bus Control Register I2C The on board temperature sensor is connected to the system by a local DC bus interface which is implemented in the PLD none of the DSP DC interfaces is used The DC bus control register controls the local IC bus The lC bus consists of a clock line SCL and a data line SDA which are pulled to a high level by resistors and which can be pulled low by any TC bus members Details on how to program the IC bus and how to use the temperature sensor are in However application software usually does not access this register directly but uses the appropriate board library functions 20 A software driver for the temperature sensor is included in the development kits LOS Date 28 November 2005 KJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713
42. e connector pins The user is no longer restricted to a fixed I O logic The FPGA has access to the following signal groups DSP EMIF data bus address bus control signals micro line connectors JTAG interface DSP interrupts RS232 line driver The figure below gives an overview how the FPGA is connected on the C6713CPU board The numbers shows the number of signals for each connection The description of the micro line connectors in parentheses show the classic functions as they are implemented by the micro line busmaster BSP see 21 and also by classic micro line CPU and peripheral boards without FPGA TMS320C6713 DSP micro line connector BB HPI coal D peripheral interface FPGA CPU clock Xilinx Spartan 3 200K 1M gates EMIF data A peripheral interface data BB HPI EMIF address B peripheral interface addr E board specific EMIF control D peripheral interface UART clock d D RS 232 flash ready busy p Figure 4 FPGA connections overview After power up or hardware reset the FPGA is automatically cleared and has to be loaded before it starts operation This can be done manually by application software or automatically by the Flash File System of the C6713CPU The FPGA can be loaded at any time and can also be reloaded with a different configuration during runtime without the need to power off or reset the whole board During system startup a FPGA design is loaded by the Flash File
43. e FPGA Usage of these signals requires either an ORSYS board support package or a custom FPGA design These signals are pulled up by the FPGA as long as the FPGA is not loaded SCLO This signal is only routed to the FPGA in default hardware configuration therefore SCLO is not available by default In this case SCLO can be used for any purpose by an ORSYS board support package or a custom FPGA design Optionally SCLO can additionally be connected to the DSP s lC interface 0 see chapter 7 2 5 for details When connected SCLO has a 10KQ pull up resistor If the board is configured for I2C 0 usage then the FPGA may only pull this signal low according to the rules of the l C standard SDAO This signal is only routed to the FPGA in default hardware configuration therefore SDAO is not available by default In this case SDAO can be used for any purpose by an ORSYS board support LOS Date 28 November 2005 e HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG OFSYS MICRO LINE C6713CPU E package or a custom FPGA design Optionally SDAO can additionally be connected to the DSP s l C interface 0 see chapter 7 2 5 for details When connected SDAO has a 10KQ pull up resistor If the board is configured for I2C 0 usage then the FPGA may only pull this signal low according to the rules of the l C standard 6 5 4 Connector D Power GND These four pins are the power supply ground pins of the C6713CPU board Only the po
44. e development is finalized the user application software can be downloaded from the development PC to the C6713CPU s flash memory via RS232 for permanent storage This is managed by the Flash File System which is permanently installed on the C6713CPU The FPGA JTAG interface can be used to quickly download and test FPGA designs during development without permanent storage on the C6713CPU After the FPGA development is finalized the FPGA design can be downloaded from the development PC via RS232 to the C6713CPU s flash memory for permanent storage This is managed by the Flash File System which is permanently installed on the C6713CPU In order to connect a standard DSP JTAG emulator or a standard FPGA download cable to the C6713CPU a JTAG adapter is used which is included in C6713CPU development kits The JTAG adapter is described in chapter 6 4 2 3 Interfaces and Hardware Components 2 3 1 FPGA The default FPGA design for the C6713CPU can be used for standard micro line bus compatible applications Alternatively the FPGA can be individually programmed by the user This is possible by using an optional FPGA development package from ORSYS together with standard FPGA development tools from Xilinx FPGA technology allows flexible internal logic and individual I O fy Date 28 November 2005 A HARDWARE REFERENCE GUIDE Doc no C6713CPU HRG orsys MICRO LINE C6713CPU E interfacing over for the majority of the micro lin
45. eE AR 11 Figure 4 FPGA connections E 13 Figure 5 Data representation in memory in little endian configuration sssssss 22 Figure 6 Connector IOCAUOMS Per Em 31 Figure 7 JTAG adapter for the C67130PU sesecivcstiiccntectatntiatetdacuncennatenexenasniceatgeassixaadatenekiennelansyreads 35 Figure 8 Supplying the C6713CPU with power cccccccccececeeeeeeeeseeeeeceeeeeeeeeeeeeeeeeeeeeeeeeeeseneneee 44 Figure 9 Connecting the serial interface RS 232 to a PC 45 Figure 10 Location of configuration elements top aide 46 Figure 11 Location of configuration elements bottom side ssseeeeeeeese 47 Figure 12 Dimensions of the C6713CPU in millimeters eessse 50 Figure 13 Complete micro line footprint 51 Figure 14 Cor 13 C PU connector E 52 LS Date 28 November 2005 iJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU p 1 Preface This document describes the hardware of the C6713CPU board It is intended to get an overview of the board and its features Detailed information about programming usage of the FPGA and the DSP is described in other documents that will be referenced throughout this document 1 1 Document Organization This document is organized as follows e Chapter 2 gives an overview of the whole system and its interfaces Chapter 3 gives an overview of the memory maps and describes
46. ed by default thus no resets will be generated and the watchdog timer does not need to be reset by software Enabling the watchdog timer and resetting it is described in chapter 3 10 7 2 3 8 External Flags XF signals The C6713CPU provides two dedicated general purpose I O pins that can be configured as either inputs or outputs When configured as an output the user can write to a PLD register to control the state driven on the output pin When configured as an input the user can detect the state of the input by reading the state of a PLD register Please refer to chapter 3 10 for a description on how to control the XF pins Please note that also some of the on chip interfaces of the DSP such as the McBSP can be used as general purpose UC 2 3 9 Power Supply of the Board The C6713CPU must be supplied with a voltage of 3 3 V It is not designed for 5V supply Please refer to chapter 7 1 for connection details CAUTION The C6713CPU is not protected against reversed voltage Please be careful when connecting the power supply to the board Applying reversed voltage will damage the board The following voltages are generated internally on the C6713CPU by highly efficient switched mode voltage regulators e 1 4 V supply voltage for the processor core e 1 25 V supply voltage for the FPGA core 2 4 Status LED s On the C6713CPU there are two groups of LED s e two user programmable LED s controlled by the PLD e one user programmable
47. eded DX1 can also be used as general purpose output e f configured for McASP usage this pin is a bi directional data line of McASPO DX1 has a 22R series resistor How to use this pin is described in 4 6 and 7 CLKR1 AXRO 6 This pin has a dual function e f configured for McBSP usage this pin is the receiver clock output or input of McBSP1 The receiver clock signal can be either supplied by an external clock or can be provided internally and then supplied to the pin If the receiver port function is not needed CLKR1 can also be used as general purpose UO pin e If configured for McASP usage this pin is a bi directional data line of McASPO CLKR1 has a 22R series resistor How to use this pin is described in 4 and 6 and 7 CLKX1 AMUTEO This pin has a dual function e If configured for McBSP usage this pin is the transmitter clock output or input of McBSP1 This transmitter clock can either be supplied by an external clock or can be provided internally and then supplied to the pin If the transmitter port function is not needed CLKX1 can also be used as general purpose UO pin e If configured for McASP usage this pin is the mute output of McASPO CLKX1 has a 22R series resistor How to use this pin is described in 4 and 6 and 7 FSR1 AXRO 7 This pin has a dual function e If configured for McBSP usage this pin is the receiver frame sync input or output of McBSP1 If frame synchronization is pr
48. ending if performs the desired function see 24 If no command is present it looks for files that are marked as auto boot FPGA and a file that is marked as auto boot application program All of them are loaded and started The Flash File System already sets up clock and EMIF settings of the TMS320C6713 DSP The default settings can be used by the user application so the user does not need to change the settings The default settings are listed below Table 9 Default clock and EMIF settings of the C6713CPU In case of multiple FPGA peripheral systems the C6713CPU is also capable to boot up to 1023 off board FPGAs with a defined booting sequence In that case each off board FPGA is marked with individual boot address and handshake information as well as a certain boot sequence number ep orsys HARDWARE REFERENCE GUIDE MICRO LINE C6713CPU Date 28 November 2005 Doc no C6713CPU_HRG Iss Rev 1 1 Page 30 5 Using the Flash File System The Flash File System of the C6713CPU consists of three parts e A target resident boot loader which initializes the C6713CPU at startup looks for commands on the RS 232 interface and then either loads auto boot FPGA s application or loads a Flash File System command executable over RS 232 e DSP side executables which perform the desired function e PC side utilities that connect to the C6713CPU upload the DSP side executables and perform the desired function
49. er and are described in the subsequent paragraphs For changing other settings please contact ORSYS Function default setting DSP clock speed same as DSP speed grade HPI McASP1 micro line pin D30 termination 4 7KQ pull up l C 0 FPGA I O FPGA I O CLKS1 SCL1 termination 10KQ pull down FPGA IO without FPGA loaded FPGA internal pull up Table 17 Factory default configuration summary 7 2 4 Location of modifiable components WI mut R81 R65 R67 Figure 10 Location of configuration elements top side Ly Date 28 November 2005 iJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU E L DW DW R64 DR DR m R66 ri R72 R73 Figure 11 Location of configuration elements bottom side 7 2 2 Configuring DSP Clock Speed R81 controls the setting of the CPUSPEED bit in the PLD s HWCFG register The Flash File System takes this bit to decide between 225 MHz and 300 MHz initialization Application software can also read this bit to determine the current setting Please note that a 300 MHz DSP can be configured for 225 MHz or 300 MHz operation whereas a 225 MHz DSP can only be operated at 225 MHz CPU clock _ EMIF clock mounted with 10kQ 225 MHz 90 MHz not mounted default 300 MHz 100 MHz 7 2 3 Configuring for HPI or McASP1 Usage Using the McASP1 interface of the TMS320C6713 DSP is only possible when the HPI is disabled and vice versa The decision which interface
50. eripheral devices should use this ground as reference Power supply ground should not be directly connected to these pins to avoid switching regulator ripple on the signal ground Power supply ground should be connected to the GND pins on connector D 6 5 3 Connector BB HD 15 0 These signals are connected over a 16 bit bus transceiver to the DSP s HPI data bus The bus transceiver is controlled by the FPGA Therefore usage of these signals requires either an ORSYS board support package or a custom FPGA design For HPI booting or McASP GPIO operation the 16 bit bus transceiver can be replaced by resistor arrays which provide direct connections between the BB 16 1 and the DSP HHWIL HCNTL 1 0 HAS HR W HCS HRD HSTRB HWR HSTRB HRDY HINT These signals are routed to the DSP s HPI control lines and have a pull up resistor provided by the DSP Additionally HRDY has a 4 7kQ pull down resistor and HAS has a 10kQ pull up resistor HINT and HRDY also have 229 series resistors The function of these signals is described in 6 HR W directly controls the direction of the HPI data driver The signals HR W HCS HRD_HSTRB and HWR HSTRB are also connected to the FPGA and are used by the FPGA for enabling the HPI data driver These signals are inputs to the DSP The FPGA should must not drive these signals if they are driven from an external host processor at the micro line bus Pins BB27 through BB30 The signals are routed to th
51. h 10k SCL1 7 2 7 Configuring FPGA I O Behavior When FPGA is not Loaded Before the FPGA is loaded all FPGA I O pins are pulled high by default The HSWAP_EN input of the FPGA determines whether or not weak pull up resistors are enabled in an unloaded state HSWAP_EN 1 disables the pull up resistors while HSWAP_EN 0 default enables the pull up resistors The default setting is to have pull up resistors enabled and is required by the Flash File System Please contact ORSYS if this setting has to be changed 7 3 Signal Levels and Loads 7 3 4 Input Voltage Levels for non FPGA Signals All digital logic input signal levels are 0 to 0 8V for logic low and 2 0V to 3 3V for logic high and can be driven by an output of one of the following logic standards e 3 3VLVTTL e 2 5V CMOS Exceptions are the RS 232 interface signals Their voltage levels are listed in the individual pin description chapter 6 5 4 CAUTION Do not apply voltages higher than 3 3V to any pin of the micro line connector except RS 232 pins 7 3 2 Output Voltage Levels for non FPGA Signals All output signals of the C6713CPU except the RS 232 interface typically drive a logic high signal level of 3 3V They can drive inputs of one of the following logic standards e 3 3VLVTTL e 2 5V CMOS 7 3 8 Allowed Output Loads The maximum output load on the micro line connector depends on the type of the output The micro line pins can be divided into four categor
52. he external devices are located at different CE Chip Enable spaces The EMIF bus timing of each CE space can be individually set up The complete memory map is shown in Table 1 For a more detailed memory map of the DSP please refer to 4 Table 1 Memory map of the processor 3C20 0000 7FFF FFFF 1GB 62MB LN Date 28 November 2005 iJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU oe 3 2 C6713CPU Address Map The table below shows how the C6713CPU uses the four CE address spaces of the processor address range hex size bytes 8000 0000 83FF FFFF CEO 128MB external RAM SDRAM Sae EEA 0000 8FFF FFFF 128MB reserved mirrored SDRAM 9000 0000 900F FFFF flash memory upper or lower half 9010 0000 9017 FFFF 512K 9018 0000 901F FFFF 512K 9020 0000 9FFF FFFF 254M Table 2 Memory map of the C6713CPU 3 3 Internal fast SRAM The TMS320C6713 DSP provides a total of 256 KB of internal fast SRAM The upper 64 KB can partially or fully be used as level 2 cache Please refer to 4 for details about cache memory usage The lower 192 KB can be used for any purpose The DSP internal memory should be used for application software parts that need very fast memory access The DSP internal SRAM can be accessed via 256 bit bus width whereas all accesses to on board memory are limited to 32 bit bus width External SDRAM via EMIF and DSP internal
53. ies regarding source buffered or non buffered 1 The non buffered outputs are directly connected to the DSP The output pins are on micro line connectors E10 E25 and E28 E29 McBSP McASP DC and timer interfaces For these sensitive signals please refer to the recommended operating conditions in 4 2 Outputs driven by the PLD RESETOUT RESETOUT XFO XF1 These outputs should not drive loads higher than 200pF and 8mA 3 FPGA signals For these signals please refer to the BSP or FPGA development documentation 4 Signals buffered by bus drivers HDO to HD15 These outputs can drive loads of 24mA high level and 48mA low level and typically 40pF Loads above 80pF should be avoided The maximum load should be limited to not more than 5 signals LN Date 28 November 2005 AJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU EU 7 4 Supply Voltage The C6713CPU must be supplied with a voltage of nominal 43 3 V The integrated switching voltage regulators generate all necessary on board voltages CAUTION The C6713CPU is not protected against reversed voltage Please be careful when connecting power supply to the board Applying reversed voltage will damage the board CAUTION The power up voltage ramp time must be at least 0 6 ms The ramp time is measured from 10 to 90 of the full nominal voltage swing Direct plugging a 3 3V power cable into a working 3 3V power supply m
54. igh reset signal Pins D10 through D16 These signals are routed to the FPGA Usage of these signals requires either an ORSYS board support package or a custom FPGA design These signals are pulled up by the FPGA as long as the FPGA is not loaded EXT INT 5 4 These signals are routed to the respective interrupt inputs of the DSP as well as to the FPGA and have a 10kO pull up resistor These signals can be used as interrupt inputs even when the FPGA is not loaded They can either be driven by an appropriate FPGA design or by an external source but care must be taken that they are never driven by both sources simultaneously Please note that the DSP must be configured for falling edge triggered interrupts as mentioned in chapter 2 5 8 Pins D19 through D25 These signals are routed to the FPGA Usage of these signals requires either an ORSYS board support package or a custom FPGA design These signals are pulled up by the FPGA as long as the FPGA is not loaded Further all of these signals with exception of D24 have a 10kQ pull up resistor D19 through D21 are intended as additional interrupt inputs however this usage is not mandatory LOS Date 28 November 2005 e HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG OFSYS MICRO LINE C6713CPU E TXD This pin is the transmit data output of the RS 232 interface Output voltage is either 5 5 V typical or 5 5 V typical This output can be disabled by putting the RS 2
55. is active is controlled by different components and is not available for modification by the user Default setting is to use the HPI If McASP1 is to be used please contact ORSYS 7 24 Configuring micro line Pin D30 Termination By default this pin has a 4 7kQ pull up resistor R72 This is necessary for using pin D30 as an active high RDY input with the micro line busmaster BSP Alternatively a pull down resistor R73 can be mounted for usage of pin D30 as an active low e g RDY input usage of pin D30 mounted with 4 7kQ default not mounted default Input with pull up e g RDY mounted with 4 7kQ input with pull down e g RDY 7 2 5 Configuring for lC interface 0 Operation By default the IC interface 0 is disabled by hardware and the corresponding two micro line connector pins can be used for FPGA I O If usage of lC 0 is required R64 and R66 have to be mounted with OO In this case the FPGA design must not drive these signals LN Date 28 November 2005 iJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG 2 rsys MICRO LINE C6713CPU ES 7 2 06 Configuring CLKS1 SCL1 Termination By default a 10kQ pull down resistor R65 is installed for CLKS1 operation This configuration is suitable for McBSP 1 operation For usage of l C interface 1 R65 must be removed and R67 must be mounted with a 10kO pull up resistor mounted with 10kQ default not mounted default CLKS1 mounted wit
56. led Therefore accesses to the flash memory are handled by the Flash File System and corresponding utilities see chapter 5 and 24 Direct accesses to the flash memory from application software are not recommended After reset or power up the DSP boots from flash memory During the boot process the Flash File System software is loaded The Flash File System software then loads the FPGA s and application software that is marked as auto start application and executes it x orsys HARDWARE REFERENCE GUIDE MICRO LINE C6713CPU Date 28 November 2005 Doc no C6713CPU_HRG Iss Rev 1 1 Page 22 3 7 Endianness When data is transferred between the C6713CPU board and external hardware over the micro line connector it is important to know how data is stored in memory The C6713CPU is configured for little endian operation This means less significant bytes are stored first at lower addresses 8 bit write to memory Data to be stored 16 bit write to memory Data to be stored 12 34 32 bit write to memory Data to be stored 12 34 56 78 C code char 0x8000000 0x12 E i C code short 0x8000000 0x1234 C code int 0x8000000 0x12345678 MA Figure 5 Data representation in memory in little endian configuration result in memo 8000 0000h result in memory 8000 0000h 34 8000 0001h result in memory 8000 0000h 78 8000 0001h
57. line Connector Pins retener tentent tenens 36 0 5 1 Connector i c tae CR RR EVER AN AR RR a EY a E a c E c a HT E ER e EC D A IE KR P 36 6 5 2 Connector B ETT 36 6 5 3 Connector E 36 6 5 4 Connector PT 37 6 9 0 EIDEL Eeer 38 ra cdlusdz gae 44 7 1 Minimum Connections e 44 7 2 Changing the Board Configuration cccssseccceseseeeeeeeeeeeneeesseeneesesseeeeeseseneneeeeeeeneeeeenees 46 7 2 1 Location of modifiable components eene nnne 46 7 2 2 Configuring DSP Clock Speed incisacecpeecaatetsntinanceqrmancseaunsinabiatadendtetndnaicceduidhetegdnun butliadeusnass 47 LOS Date 28 November 2005 KJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU pU 7 2 3 Configuring Tor HPI or MCASP1 Usage iudicii rh earn dro o Eo ERR prado eben ear hmi rRn e orb eras 47 7 2 4 Configuring micro line Pin D30 Termination ccccsesesssesesestscstscsescsescsessseseetseeesseceeess 47 7 2 5 Configuring for DC interface 0 Operation c ccccccesssssssesssessscstecstscseecseseaeseetseetsestesecetess 47 7 2 6 Configuring CLKS1 SCL1 ut Ce EE 48 7 2 7 Configuring FPGA I O Behavior When FPGA is not Loaded 48 7 3 Signal Levels and Loads is acs rete eee etti bic atc dapes ee eae ect eat irira ste cane 48 7 3 1 Input Voltage Levels for non FPGA Sigmials
58. nerator used for McBSPO If the transmitter and the receiver port function is not needed CLKSO can also be used as general purpose input pin e If configured for McASP usage this pin is the receive high frequency master clock of McASPO CLKSO has a 22R series resistor How to use this pin is described in 4 6 and 7 LOS Date 28 November 2005 KJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU pU DRO AXRO 0 This pin has a dual function e If configured for McBSP usage this pin is the data receive input of McBSPO All incoming data from devices connected to the McBSP is communicated via this input pin If the receiver port function is not needed DRO can also be used as general purpose input e If configured for McASP usage this pin is a bi directional data line of McASPO DRO has a 22R series resistor How to use this pin is described in 4 6 and 7 DXO AXRO 1 This pin has a dual function e f configured for McBSP usage this pin is the data transmit output of McBSPO All outgoing data to devices connected to the McBSP is communicated via this output pin If the transmitter port function is not needed DXO can also be used as general purpose output e f configured for McASP usage this pin is a bi directional data line of McASPO DXO has a 22R series resistor How to use this pin is described in 4 6 and 7 CLKRO ACLKRO This pin has a dual function
59. no C6713CPU_HRG OFSYS MICRO LINE C6713CPU EI Page 6 4 Pinout of the JTAG Connector FPGA TMS FPGA FPGA TDI FPGA TDO FPGA TCK Usually the JTAG connector is used with an adapter that is part of the development kits This adapter provides connectors that are mechanically compatible with the standard development tools e JTAG emulators e g XDS510 PP Plus XDS510 USB XDS560 e the Xilinx parallel download cable Pin Table 16 Pinout of the JTAG connector ENEHEEEEEHEERE MER 4 33V GND TCK TDO TDI TMS FPGA JAG connector EES Teil D amp JAG connector fits T emulator POD top view Figure 7 JTAG adapter for the C6713CPU LOS Date 28 November 2005 KJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU p 6 5 Function of the micro line Connector Pins 6 5 1 Connector A Pins A1 through A32 These signals are routed to the FPGA Usage of these signals requires either an ORSYS board support package or a custom FPGA design These signals are pulled up by the FPGA as long as the FPGA is not loaded 6 5 2 Connector B Pins B1 through B24 These signals are routed to the FPGA Usage of these signals requires either an ORSYS board support package or a custom FPGA design These signals are pulled up by the FPGA as long as the FPGA is not loaded Signal GND These are the signal ground pins of the micro line connector P
60. nsfer data between two locations anywhere in the address range of the C6713CPU EDMA transfers can be triggered by software internal events such as timers or serial ports or by hardware interrupt lines DMA operations can be chained that means the end of one transfer starts the next transfer This provides a powerful flexible way to perform continuous data flow without CPU intervention as well as scatter gather transfers The enhanced DMA can perform element transfers with single cycle throughput in the case that the source and destination are on two different internal buses and each provides a single cycle throughput In this case a maximum data throughput of 300 MWords per second can be achieved Furthermore there is another more simplified DMA register set available the QDMA quick DMA QDMA transfers can be set up within five CPU clock cycles register accesses and can be re started with one a single register access At the TMS320C6713 DSP the DMA is the only way to perform fast block transfers from or to non cached locations Detailed information can be found in 4 6 12 and 13 LN Date 28 November 2005 KJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU EO 3 Memory Maps and Description of the PLD Registers 3 1 TMS320C6713 Memory Map The memory map of the TMS320C67 13 is divided into several sections e internal memory e DSP peripherals e EMIF CE spaces CEO CE3 T
61. o LED s connected to the PLD There are different possible sources to switch on the green LED Ly Date 28 November 2005 iJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG rsys MICRO LINE C6713CPU E 7 6 5 4 3 0 RED LED GREEN LED RESERVED r w 00 r w 11 RED LED RED LED Oo E 012 on l others l reserved GREEN LED RED LED Encoding on when CE1 active that is when Flash PLD or FPG registers are accessed on when Flash is accessed 3 10 4 Module Control Register MCR 7 6 5 4 3 0 SW RESET RESERVED CTS RESET EN RS232 DRV EN RESERVED w 0 r 0 rw 0 r w 1 SW RESET SW RESET provides the possibility to reset the board and connected peripherals by application software This bit is always read as a O Setting this bit to 1 triggers the on board reset generator A hardware reset pulse is generated which resets all components of the C6713CPU The reset pulse is also asserted on the micro line signals RESETOUT and RESETOUT SW RESET can be used to restart the system after a fatal error condition after a flash memory software update etc The SW RESET bit is automatically cleared to O CTS RESET EN Setting this bit to 1 enables the board reset function of the CTS line of the RS232 interface When the board reset function is enabled an external device may reset the C6713CPU over the CTS line of the RS232 interface CTS is considered active when CTS line of the mi
62. ound in 4 and 6 2 5 7 Host Port Interface HPI The TMS320C6713 DSP provides a 16 bit wide Host Port Interface HPI which can be used by a host processor to directly access the memory of the DSP Here the host device accesses the HPI as a master and the DSP acts as a slave The host processor and the DSP can exchange information via DSP internal and on board memory The host also has direct access to memory mapped peripheral registers Connectivity to the DSP memory space is automatically provided by a background DMA mechanism The host device controls the HPI transfers via dedicated HPI address and data registers which are not accessible for the DSP Here the DMA auxiliary channel connects the HPI to the DSP memory space On the TMS320C6713 DSP the HPI peripherals shares signals with e McASP1 e GPIO HPI booting is not supported by default If HPI booting is required please contact ORSYS HPI operation requires an appropriate FPGA to be loaded such as 21 Further information about the HPI can be found in 4 and 6 HPI operation is enabled in default hardware configuration see chapter 7 2 2 5 8 Interrupts Four maskable and one non maskable interrupt hardware input lines allow on board and off board hardware devices to interrupt a running program and jump into a dedicated interrupt service routine DMA transfers can also be triggered by hardware interrupt lines Detailed information about interrupts can be found in 4 6
63. out several hardware settings of the board and the controls the highest address bit of the flash memory Application software can read this register to determine e g the size of the SDRAM The value of RAMSIZE and CPUSPEED are determined by the hardware configuration of the C6713CPU Please refer to chapter 7 2 for configuration details 7 6 5 4 3 0 RAMSIZE CPUSPEED RESERVED FLASH A19 RESERVED r 0 r 0 r O r w O RAMSIZE This bit can be used by application software to determine the available memory size RAMSIZE SDRAM size 0 82MB 1 04 M all PLD registers are mirrored within a range of 64K bytes Date 28 November 2005 HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG fy KJI MICRO LINE C6713CPU apu rsys CRO Page 25 CPUSPEED This bit can be used by application software to determine the DSP speed version and to program the DSP s PLL accordingly CPUSPEED _ CPU clock frequency FLASH A19 This bit represents the highest address line of the flash memory When FLASH A19 is 0 the lower 1 MB of the flash memory is selected When FLASH A19 is 1 the upper 1 MB of the flash memory is selected Application software usually does not need to access this bit but use the provided functions for runtime flash memory access from the board library see 20 3 10 2 FPGA Control Register FCR The FPGA control register is used by the Flash File System and the board library to lo
64. ovided by an external device FSR1 is an input If the frame synchronization signals are generated internally by processors sample rate generator FSR1 is an output If the receiver port function is not needed FSR1 can also be used as general purpose UO pin e f configured for McASP usage this pin is a bi directional data line of McASPO FSR1 has a 22R series resistor How to use this pin is described in 4 6 and 7 FSX1 This pins is the transmitter frame sync output or input of McBSP1 If frame synchronization is provided by an external device FSX1 is an input If the frame synchronization signals are generated internally by the processor s sample rate generator FSX1 is an output If the transmitter port function is not needed FSX1 can also be used as general purpose UO pin FSX1 has a 22R series resistor How to use this pin is described in 4 and 6 LOS Date 28 November 2005 KJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU E CLKS1 SCL1 This pin has a dual function e f configured for McBSP usage this pin is the external input of the internal sample rate generator used for McBSP1 If the transmitter and the receiver port function is not needed CLKS1 can also be used as general purpose input pin e If configured for I C usage this pin is the open collector clock line of 1 C interface 1 By default this pin has a 10K pull down resistor which is needed for McBSP
65. sary numbers are represented with a suffix that specifies their base Example 12AB46 is a hexadecimal number base 16 hexadecimal and is equal to 477940 The bit fields of a register are displayed with the most significant bit to the left Below each bit field is a description of its read write accessibility and its default value meme mmm 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A B C D E F G H l J K L N O r w Q r w 0 r w 0 r w 0 r w 0 r w 0 r w 0102 r 0 r wc 0 w r w 0 rc 0 r w 0 r w 0 accessibility and default value legend r bit is readable rc this bitis cleared after a read rw bit is readable and writeable reading yields the previously written value unless otherwise specified W bit is writeable read value is undefined wc writing a 1 to this bit clears it w 0 bitis write only reading always yields 0 0 default value 1 4 Trademarks Tl Code Composer DSP BIOS and TMS320C6000 are registered trademarks of Texas Instruments Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and or other countries Hypterterminal is a trademark of Hilgraeve Inc All other brand or product names are trademarks or registered trademarks of their respective companies or organizations LN Date 28 November 2005 KJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU po
66. signals are routed to micro line connectors Chapter 6 3 contains a detailed listing of connector pin assignments as well as a list of shared signals Detailed information how to use the McBSPs can be found in 4 and 6 LOS Date 28 November 2005 e HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG OFSYS MICRO LINE C6713CPU Eoo 2 5 6 Timers The TMS320C6713 DSP provides two independent 32 bit general purpose timers The timers support two signaling modes and can be clocked by an internal or an external source Each timer has a separate input pin and an output pin Using an internal clock for example the timer can trigger an external A D converter to start a conversion or it can trigger the DMA controller to start a data transfer If connected to an external digital signal source the timer can count external events and interrupt the DSP after a specified number of events Each timer input pin TINPO or TINP1 can either work as timer clock input or be configured for general purpose digital input Each timer output pin TOUTO or TOUT1 can either work as clock output or be configured for general purpose digital output At the TMS320C6713 DSP the timer signals are shared with the McASPO port On the C6713CPU board the timer signals are routed to micro line connectors Chapter 6 3 contains a detailed listing of connector pin assignments as well as a list of shared signals Detailed information how to use the timers can be f
67. ts McASP The McASPs are serial ports optimized for the needs of multi channel audio applications Two McASP ports are available on the TMS320C6713 The McASP ports are described in 4 and 7 in detail The signals of the McASP ports are shared with signals of other DSP peripherals like McBSPs Timers GPIO 5 EXT INT5 GPIO A EXT INTA Host Port Interface At the C6713CPU board the McASPO port is available at micro line connectors Chapter 6 3 contains detailed tables of shared signals Further information can also be found in 4 By default the McASP1 port is disabled by hardware and the Host Port Interface HPI is enabled therefore If McASP1 is needed for a certain application a slight hardware reconfiguration on the C6713CPU board is necessary In this case please contact ORSYS Further details about McASP 1 configuration are also described in chapter 7 2 2 5 2 External Memory Interface EMIF The EMIF is the main on board 32 bit bus interface between the DSP and other components It is connected to e on board memory SDRAM flash memory e on board peripherals PLD e FPGA The EMIF can also be used to access off board hardware by using an appropriate FPGA design This can either be a standard BSP from ORSYS or a custom FPGA design The EMIF is mapped into the DSP s address space separated into four areas called CE spaces LOS Date 28 November 2005 e HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG O
68. vides a 10KQ pull up resistor on this signal HOLDA pin D32 This signal is routed to the FPGA and to the HOLDA pin of the DSP This signal is driven by the DSP so it may not be driven by the FPGA or from the micro line pin The C6713CPU board provides a 10KO pull up resistor on this signal 6 5 5 Connector E Pins E1 through E9 These signals are routed to the FPGA Usage of these signals requires either an ORSYS board support package or a custom FPGA design These signals are pulled up by the FPGA as long as the FPGA is not loaded DH1 SDA1 This pin has a dual function e If configured for McBSP usage this pin is the data receive input of McBSP1 All incoming data from devices connected to the McBSP1 is communicated via this input pin If the receiver port function is not needed DR1 can also be used as general purpose input e If configured for IC interface usage this pin is the open collector data line for 1 C interface 1 DR1 has a 10KQ pull up resistor and a 22R series resistor How to use this pin is described in 4 6 and 9 LOS Date 28 November 2005 e HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG OFSYS MICRO LINE C6713CPU Eo DX1 AXRO 5 This pin has a dual function e f configured for McBSP usage this pin is the data transmit output of McBSP1 All outgoing data to devices connected to the McBSP1 is communicated via this output pin If the transmitter port function is not ne
69. w to set up the C6713CPU for use without a micro line Power Supply carrier board Please refer to chapter 7 4 for the supply voltage limits Voltage Regulator m m 3 3 ZE NESSES D Figure 8 Supplying the C6713CPU with power CAUTION The C6713CPU is not protected against reversed voltage Please be careful when connecting power supply to the board Applying reversed voltage will damage the board CAUTION The power up voltage ramp time must be at least 0 6 ms The ramp time is measured from 10 to 90 of the full nominal voltage swing Direct plugging a 3 3V power cable into a working 3 3V power supply may damage the board Date 28 November 2005 Doc no C6713CPU_HRG Iss Rev 1 1 Page 45 LJ y HARDWARE REFERENCE GUIDE orsys MICRO LINE C6713CPU EC SS me MM CTS connect to PC s RTS standard PC RS 232 connector Sub D 9pin socket fits directly into a PC front view RxD connect to PC s TxD RTS connect to PC s CTS TxD connect to PC s RxD GND Figure 9 Connecting the serial interface RS 232 to a PC LN Date 28 November 2005 iJ HARDWARE REFERENCE GUIDE Doc no C6713CPU_HRG orsys MICRO LINE C6713CPU E ae 7 2 Changing the Board Configuration This chapter shows the different hardware board configurations The factory defaults are listed below Some configuration settings may be changed by the us
70. wer supply should be connected here Signal ground should be connected to the ground pins of connector B 3 3V These two pins provide the power supply for the C6713CPU board All necessary internal voltages are generated from this input voltage Please refer to chapter 7 4 for voltage limits and recommended operating conditions RESETIN This input pin can be used for an external reset button or for a reset output signal from external hardware When RESETIN is driven low all components of the C6713CPU are reset Furthermore RESETOUT and RESETOUT are activated so that connected peripheral components will also get a defined reset signal The RESETIN signal does not need to be de bounced The C6713CPU board provides a 10kQ pull up resistor on this input RESETOUT This is an active low reset output pin It allows external hardware to get a defined reset and exactly be started together with the C6713CPU board RESETOUT always becomes active if the C6713CPU board is reset There is no difference whether the reset was caused manually by RESETIN power on a watchdog event software or a under voltage condition In all cases the reset condition is asserted by a 200ms typical pulse A 10kQ pull up resistor is provided on this signal for cases where the C6713CPU is hardware configured for future use as a slave peripheral board where RESETOUT is an input to the board RESETOUT This is an inverted RESETOUT signal that means an active h

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