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Intel SE7520JR2 User's Manual

1. eeeeeeee 36 3200 JRTG Lur rc NN 36 3 2 3 9 General Purpose WO SPIO ves id 36 3 2 3 10 Enhanced Power Managertrient iic atte cae ler bc e pa ge Hina ph 36 3 2 3 11 System Management Bus SMBUS 2 0 36 3 3 Memory SUD YSU Ii tec occas lads te te scen doute xic fle tto roads 37 3 3 1 Memo A ests peer hai diete etia test tpe iul cea xac 37 3 3 2 Memory PODUIALIOM Em 38 3 3 3 EGG Memory Initialization eet ii 40 3 3 4 Memory Te is ir idas 40 3 3 5 Memory Monitoring ss nec Aan tn A A A dod 41 3 3 6 Memory RASUM Features colonos dada Rata atk acid dees cade id Resa cada pos 42 3 3 6 1 DRAM ECC Intel x4 Single Device Data Correction x4 SDDOC 42 3 3 6 2 Integrated Memory Scrub Engine sustancia eli dni 42 3 3 0 9 Retry on Uncorrectable Error uiscera ertt ioc e i rk pe sedendo betonen 43 3 3 6 4 Integrated Memory Initialization Engine seeeeeeme 43 3 3 6 5 DIMM Sparing Pundit 44 3 3 6 6 Memory Mirroring coccccccccnccnnncnnncnnnnnnnnnnnnnnnnonnnononnnonnnnnnnnnnnnnnnnnnnnnnnnnnnnnninnininins 45 3 3 6 7 Logging Memory RAS Information to the SEL rrrvrernrrrrnnnnvrvrnnnnrnrrnnnnrrrrnnnnnnennn 47 3 4 VO SUES SUSI Lassen 47 3 4 1 POISIBSYS ET E 47 3 4 1 1 P32 A 32 bit 33 MHz PCI Subsystem rrrrnnnnrnnnnnnnvnvrnnnnrrrnnnnnnnnennnnrrrrennnrenenn 48 3 4 1 2 P64 A and P64 B 64 bit 100MHz PCI Subsystem sse 48 3 4 1 3 P64 Express Dual x4 PC
2. N m TNT Mirror Primar Primar Mirror EE c I5 z lt 0U z EU gt Mm UN gt U Figure 7 Six DIMM Memory Mirror Configuration DDR2 Only These symmetry requirements are a side effect of the hardware mechanism for maintaining two copies of all main memory data while ensuring that each channel has a full copy of all data in preparation for fail down to single channel operation Every write to memory is issued twice once to the primary location and again to the mirror location and the data interleaved across the channel pair are swapped for the second write 1A is a copy of 2B 1B is a copy of 2A etc The resulting memory image has two full copies of all data and a complete copy available on each channel Hardware in the MCH tracks which DIMM slots are primaries and which are mirrors such that data may be internally realigned to correctly reassemble cache lines regardless of which copy is retrieved There are four distinct cases for retrieval of the even and odd chunks of a cache line of data e Interleaved dual channel read to the primary DIMM with even data on channel A e Interleaved dual channel read to the mirror DIMM with even data on channel B e Non interleaved single channel read pair to channel A with even data on the primary DIMM e Non interleaved
3. oe ll C BE 5H V VO 3 3V or 1 5V V V ND D me exo Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Connectors and Jumper Blocks JEn Signal Side A Signal n 23 ND 2 EE z 20 18 18 VO ESAS 7 fa gt gt Se B 0 2 13 i ob 14 14 AD 44 13 ME KEYWAY ei KEYWAY gt i Am e AD 41 pew jew AD AE vao V 1 0 3 3V or 1 5V AD 36 ADS Ry ADEN Gp Ag 12 ES foot AD 39 s 8 E Cri re E 5V 12 120r6 amps 3 slots needs 6 amps for 3 10W boards 3 3V 19 19 or 9 5 amps 3 slots needs 9 amps for 3 10W boards 202 pin connector length 139 45mm 5 49 T 2 2 Full Height PCI X Riser Slot The full height length riser slot is implemented using a 280 pin connector and utilizes Intel Adaptive Slot Technology capable of supporting both PCI X and PCI Express riser cards On a given riser card the PCI add in slot closest to the baseboard will always have device ID 17 On a three slot riser card the middle PCI add in slot will have device ID 18 and the top slot will have device ID 19 The interrupts on the PCI add in slots should be rotated following the PCI bridge specification 1 0 The following table provides the pinout for the Full Height riser slot Revision 1 0 179 C78844 002 Connectors and Jumper Blocks Table 86 Full height Riser Slot Pinout Intel Server Board SE7520JR2
4. 4 4 2 3 4 Removable Drive Sub menu Selections Table 35 BIOS Setup Removable Drives Sub menu Selections Options Help Text Removable Drives 1st Drive Varies Specifies the boot sequence from the available Varies based on system configuration devices Specifies the boot sequence from the available Varies based on system configuration devices 4 4 2 3 5 ATAPI CDROM drives sub menu selections Table 36 BIOS Setup CD DVD Drives Sub menu Selections Feature Options Help Text CD DVD Drives Specifies the boot sequence from the available Varies based on system configuration devices Revision 1 0 97 C78844 002 System BIOS Intel Server Board SE7520JR2 Specifies the boot sequence from the available Varies based on system configuration devices 4 4 2 4 Security Menu Table 37 BIOS Setup Security Menu Options Feature Options Help Text Security Settings Administrator N A Install Not installed Informational display Password is Install Not installed Informational display N A Set Admin Set or clear Admin password Pressing enter twice will clear the Password password This option is grayed our when entering setup with a user password Set User Password N A Set or clear User password Pressing enter twice will clear the password User Access Level No Access LIMITED allows only limited fields This node is grayed out and View Only to be changed such as Date beco
5. 6 5 5 Bootblock Recovery Code Checkpoint The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because the user has forced the update or the BIOS checksum is corrupt The following table describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS Table 77 Bootblock Recovery Code Checkpoint Diagnostic LED Decoder Description Checkpoint G Green R Red A Amber MSB LsB Initialize the floppy controller in the super I O Some interrupt vectors EO OFF are initialized DMA controller is initialized 8259 interrupt controller is initialized L1 cache is enabled Set up floppy controller and data Attempt to read from floppy E9 A G DM y Determine information about root directory of recovery media EA A A OFF Enable ATAPI hardware Attempt to read from ARMD and ATAPI CD ROM Determine information about root directory of recovery media EB p WW R ae Ge Disable ATAPI hardware Jump back to checkpoint E9 Read error occurred on media Jump back to checkpoint EB E ee Search for pre defined recovery file name in root directory A Ann Recovery file not found a file not found Start reading FAT table and analyze FAT to find the clusters occupied by the even file feer sa re ee esta A Revision 1 0 171 C78844 002 Error Reporting and Handling Intel Server Board SE7520JR2 Diagnostic LED Decoder Description Chec
6. T 3 2 ICMB Header A white 5 pin header J1D1 located on the left side of the baseboard near the internal SCSI connector cutout Table 88 ICMB Header Pin out J1D1 Pin Signal Name Transmit Enable UART signals Jes es 7 3 3 IPMB Header When either the Professional or Advanced management modules are installed the yellow 3 pin IPMB connector J3F1 can be used to access the IPMB bus Note There is no IPMB bus available with standard on board platform instrumentation Revision 1 0 187 C78844 002 Connectors and Jumper Blocks Intel Server Board SE7520JR2 Table 89 IPMB Connector Pin out J3F1 Pin Signal Name Local I2C SDA BMC IMB 5 V STNDBY Data Line Local I2C SCL BMC IMB 5 V STNDBY Clock Line 188 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 7 3 4 OEM RMC Connector J3B2 A white eight pin connector J3B2 used for OEM specific management cards Connectors and Jumper Blocks Table 90 OEM RMC Connector Pinout J3B2 Pin Signal Name PERIPH I2C 3VSB SCL 5 CEN GROUND 5V STBY ICH5 SYS RST L 8 FP_PWR_BTN_RMC 7 4 Control Panel Connectors The Server Board SE7520JR2 provides three control panel interconnects a high density 100 pin connector for use in the Intel Server Chassis SR1400 1U and SR2400 2U with backplane installed a 50 pin control panel connector used in Intel s chassis with no backplane installed and a SSI standard 34 pin c
7. NO LLL CINE CN 88 FAN LEDER N C FAN_TACH8 FAN_TACH signal to monitor the FAN speed FAN_TACH4 FAN_TACH signal to monitor the FAN speed 7 FAN_TACH7 FAN_TACH signal to monitor the FAN speed FAN_TACH3 FAN_TACH signal to monitor the FAN speed FAN_TACH6 FAN_TACH signal to monitor the FAN speed 10 FAN TACH2 FAN TACH signal to monitor the FAN speed 11 FAN TACH5 FAN TACH signal to monitor the FAN speed 12 FAN_TACH1 FAN_TACH signal to monitor the FAN speed 16 GROUND GROUND FAN SPEED CNTL 2 Power supplied through fan speed control circuitry FAN SPEED CNTL 1 Power supplied through fan speed control circuitry FAN SPEED CNTL 2 Power supplied through fan speed control circuitry FAN SPEED CNTL 2 Power supplied through fan speed control circuitry 17 18 19 20 BB FAN LED5 R BB FAN LED8 R 22 23 n Revision 1 0 199 C78844 002 Connectors and Jumper Blocks Intel Server Board SE7520JR2 EME JMN The 1x3 fan header J3K3 is used to control a system fan in the Intel Server Chassis SR1400 The pinout for this connector is found in the following table Table 108 3 Pin Fan Speed Controlled Fan Header J3K3 Pin Signal Name FAN TACH signal is connected to the BMC to monitor the FAN speed Fan Speed Cntl1 Power supplied through fan speed control circuitry GROUND is the power supply ground 7 7 Misc Headers and Connectors 7 7 1 Chassis Intrusion Header A 1x2 pin header
8. Power Supply Status 2 SR2400 Power Nozzle Power Supply 1 Power Nozzle Power Supply 2 Power Gauge V1 rail 12v Power Supply 1 Power Supply 08h Current 03h Current 03h Other Units OBh Power Gauge V1 rail 12v Power Supply 2 Power Gauge aggregate power Power Supply 1 Power Gauge aggregate power Power Supply 2 Other Units OBh Module Board Processor Missing 15h System ACPI Power State 22h System ACPI Power State Revision 1 0 Event Reading Type Digital Discrete 06h Digital Discrete Event Offset Triggers Assert Deassert Performance Met or Lags Performance Met or Lags Digital Discrete 06h Digital Discrete 06h Performance Met or Lags Performance Met or Lags Presence Sensor Specific 6Fh Failure Predictive Fail A C Lost Presence Sensor Specific 6Fh Failure Predictive Fail A C Lost Current Threshold Current Threshold fu nr c nc Threshold 01h Threshold 01h Threshold 01h Threshold 01h Digital Discrete 03h S fu nr c nc fu nr c nc u nr c nc State Asserted State Deasserted Sensor Specific 6Fh S5 G2 G3 Mechanical Off C78844 002 Platform Management i Trig Offset Trig Offset R R R R R Readable Value Offsets LAN E z 3 Trig Offset Trig Offset 145 Platform Management Intel Server Board SE7520JR2 Sensor Event
9. oooconocononcccncccconcconnnannnncnnnnnnnnnnnnns 115 5 1 1 A A 116 5 1 2 IPMI Messaging Commands and Abstractions XXX ooooooooococcconcconcnoncnnononononnnnns 116 5 1 3 IPMISensor Model p Ire teer bp kuna 117 5 1 4 Private Management BUSSES version iere terrier nta 118 5 1 5 Management Controller e iuit bt ft ie detto leet Midtgen 118 5 2 On Board Platform Management Features and Functionality 121 5 2 1 Server Management IC BUSES cccccccscessessececscscscscseseecseeaseestecstecseeeatsestseatees 122 5 2 2 Power Control Interfaces ssssssssssssssssssssssseemeem emen 122 5 2 3 External Interface to the mBMC oooooooccococoncconononcnoncnonononcnoncnnncnnnnnnnnnnnnnnonnnnnnnnnnos 122 5 3 mBMC Hardware Architecture rrrnnnnnnnnnnnnnnnnnnnnnnnnnnn nn nn nn nn nn nrnn nn enn nnnn 123 5 3 1 Power Supply Interface SIMA Sci sr 124 5 3 2 Power Control SOUNCES ciao a AA e foe 126 5 3 3 Power up Sequence sarannnannnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnsnnnnennnennsennsennsennsrnnsrnnsrensenne 126 5 3 4 Power down Sequence annrnnnnnnnnnnnnnnnnnnnnnnnnnnnsnnnnnnnnennnennsrnnsennsennsrnnsennsennsenne 126 5 3 5 System Reset Cooler 126 5 3 5 1 Reset Signal OuUtpUt ooccccccccciccnccinicinnnnnoninnninnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnineninnnnss 126 5 3 5 2 Reset Control Sources ooccccccnncnoncnnninnnennnennnennnnnnnonnnnnnnnnnnnnnnnnnnnnnnnnnnnninnninnnnss 127 5 3 5
10. Description When enabled allows the host System to complete the boot process without a password The keyboard will remain locked until a password is entered A password is required to boot from diskette Disabled Enabled Secure Mode Boot Diskette Write Protect Disabled Enabled Disable diskette write protection when Secure mode is activated A password is required to unlock the system Disabled Enabled Blank video when Secure mode is activated A password is required to unlock the system This option controls the embedded video controller only Video Blanking Power Switch Inhibit Disabled Enabled Disable the Front Panel Power Switch when Secure mode is activated A password is required to unlock the system This node is grayed out if a user password is not installed This node is grayed out if a user password is not installed This node is hidden if the Intel Management Module is not present This node is grayed out if a user password is not installed This node is hidden if the Intel Management Module is not present This node is grayed out if a user password is not installed This node is hidden if the Intel Management Module is not present NMI Control Disabled Enable disable NMI control for Enabled the front panel NMI button 4 4 2 5 Server Menu Table 38 BIOS Setup Server Menu Selections Feature Options Help Text System management Event Event Log configura
11. 5V 12V1 2 5VSB 50mVp p 50mVp p 120mVp p 120mVp p 50mVp p 208 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Design and Environmental Specifications 8 2 11 Soft Starting The power supply shall contain control circuit that provides monotonic soft start for its outputs without overstress of the AC line or any power supply components at any specified AC line or load conditions There is no requirement for rise time on the 5V Standby but the turn on off shall be monotonic 8 2 12 Zero Load Stability Requirements When the power subsystem operates in a no load condition it does not need to meet the output regulation specification but it must operate without any tripping of over voltage or other fault circuitry When the power subsystem is subsequently loaded it must begin to regulate and source current without fault Each output voltage may not be internally diode isolated At the same time failure in the primary side of one power supply doesn t cause the other to shut down 8 2 13 Timing Requirements These are the timing requirements for the power supply operation The output voltages must rise from 10 to within regulation limits Tout rise within 5 to 70ms except for 5VSB it is allowed to rise from 1 0 to 70ms The 3 3V 5V and 12V output voltages should start to rise approximately at the same time All outputs must rise monotonically The 5V output needs to be greater than the 3 3V output during any point of the volt
12. Disabled Enabled Configure S ATA as RAID Disabled Enabled S ATA Ports Definition A1 3 M A2 4 M A1 4 M A2 3 M Mixed P ATA S ATA Primary IDE Master Primary IDE Slave Secondary IDE Master Secondary IDE Slave 88 Disabled disables the integrated P ATA Controller Primary enables only the Primary P ATA Controller Secondary enables only the Secondary P ATA Controller Both enables both P ATA Controllers Disabled disables the integrated S ATA Controller Enabled enables the integrated S ATA Controller When enabled the S ATA channels are reserved to be used as RAID Defines priority between S ATA channels Lets you remove a P ATA and replace it by S ATA in a given channel Only 1 channel can be S ATA While entering setup BIOS auto detects the presence of IDE devices This displays the status of auto detection of IDE devices While entering setup BIOS auto detects the presence of IDE devices This displays the status of auto detection of IDE devices While entering setup BIOS auto detects the presence of IDE devices This displays the status of auto detection of IDE devices While entering setup BIOS auto detects the presence of IDE devices This displays the status of auto detection of IDE devices C78844 002 Controls state of integrated P ATA controller Controls state of integrated S ATA controller Default set the S ATA Port0 to 3 IDE Maste
13. J1A1 is used in chassis that support a chassis intrusion switch This header is monitored by the mBMC The pinout definition for this header is found in the following table Table 109 Chassis Intrusion Header J1A1 Pin Signal Name fz ene SY 7 7 2 Hard Drive Activity LED Header A 1x2 pin header J1A2 provides hard drive controller add in cards an interface to the control panel Hard Drive Activity LED The pinout definition for this header is found in the following table Table 110 Hard Drive Activity LED Header J1A2 Pin _ Signal Name 3 3V 2 Jr 200 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Connectors and Jumper Blocks 7 8 Jumper Blocks The baseboard has several jumper blocks used to configure or enable disable various features This section describes the usage and settings of each Table 111 Jumper Block Definitions Reference Name Description Settings ID J1H2 A CMOS Clear Clears CMOS settings CMOS Clear by BMC Pins 1 2 Default CMOS Clear Force Erase Pins 2 3 J1H2 B BIOS Forces the system to boot into BIOS Normal Boot Pins 1 2 Default Recovery Boot Recovery mode A bootable Recovery Enabled Pins 2 3 BIOS Floppy disk must be in Drive A for this operation J1H2 C Password Clears Administrator and User Password Clr Protect Pins 1 2 Default Clear passwords as set in BIOS Setup Password Clr Erase Pins 2 3 J1A4 Rolling BIOS Sets the BIOS flash dev
14. Server Board SE7520JR2 Sensor Event Event Offset Assert Readable Sensor Name Sensor Type Reading E Value EventData Number Triggers Deassert Type Offsets Fan Threshold Fan Threshold Fan Threshold Fan Threshold Fan Threshold Fan Threshold Fan Threshold Tach Fan 8 C Tach Fan 9 Tach Fan 10 Tach Fan 11 EE i 4 4 4 4 4 4 4 4 4 4 4 Trig Offset Trig Offset Digital a Discrete ola Met As amp De 06h 9 Digital dn Discrete oes Met As amp De 06h 9 Digital Sn Discrete eee Mel As amp De 06h 9 Digital Fan Discrete Performance Met As amp De Trig Offset 04h 06h or Lags Trig Offset Digital Fan 3 Digital Fan 4 Digital Fan 2 Trig Offset Digital Fan 5 Digital Fan 6 i Trig Offset Digital Art Discrete Tr Met As amp De 06h 9 Digital Digital Fan 7 Fan Discrete Performance M t As amp De 04h or Lags 06h Digital Digital Fan 8 pan Discrete Performance Met As amp De 04h or Lags 06h Digital Digital Fan 9 Fan Discrete F erormance Met As amp De 04h 06h or Lags 144 Revision 1 0 C78844 002 Trig Offset Trig Offset Digital Digital Fan 1 50h FAD Discrete Performance Met Nak De 04h or Lags 06h 58h Trig Offset Intel Server Board SE7520JR2 Sensor Sensor Name Sensor Type Digital Fan 10 Digital Fan 11 LVDS SCSI channel 1 terminator fault LVDS SCSI channel 2 terminator fault Terminator 1Ch Terminator 1Ch Power Supply Status 1 Power Supply 08h
15. and same VID No mixing of product families is supported Processors run at a fixed speed and cannot be programmed to operate at a lower or higher speed 3 1 3 Processor Module Presence Detection Logic is provided on the baseboard to detect the presence and identity of installed processors In dual processor configurations the on board mini Baseboard Management Controller mBMC must read the processor voltage identification VID bits for each processor before turning on the VRD If the VIDs of the two processors are not identical then the mBMC will not turn on the VRD Prior to enabling the embedded VRD circuitry on the baseboard ensures that the following criteria are met e In auni processor configuration CPU 1 is installed e Only supported processors are installed in the system to prevent damage to the MCH e In dual processor configurations both processors support the same FSB frequency 3 1 4 GTL2006 The GTL2006 is a 13 bit translator designed for 3 3V to GTL GTL translations to the system bus The translator incorporates all the level shifting and logic functions required to interface between the processor subsystem and the rest of the system Revision 1 0 27 C78844 002 Functional Architecture Intel Server Board SE7520JR2 3 1 5 Common Enabling Kit CEK Design Support The baseboard has been designed to comply with Intel s Common Enabling Kit CEK processor mounting and heat sink retention solution The baseboard will
16. eeesseeeesesssseseeen n 30 3 1 8 GPU Thermal Sensors ete en Dt en da 31 3 1 9 Processor Thermal Control Sensor esee 31 3 1 10 Processor Thermal Trip Shutdown oooooooccoccccocnocononononn nono nononnn nono nono nono nnnnnnnnnnnnnnnns 31 311 ProcessorlERR noe tte A ba 31 3 2 Intel E7520 Chlpsel rester a REIR eR ato adan 31 3 2 1 Memory Controller Hub MOM itti teer sia 32 S T Front Se BE ESB masete eden adr 32 3 2 1 2 MCH Memory Sub System OvervieWw rrrrrrrrrnnnrnnnnnnnnrnrrnnnnrrrrnnnnrrrrnnnnrrrrennnnernn 32 32 1535 PEIEXPreSS 3n rto teed oa a AER 32 3 2 1 4 Hub Interface ii dida 33 iv Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Table of Contents 3 2 2 PAG HUb CP 2 33 da Ful height RISEN lOs lbn 33 2 22 2 LOW Profile Riset Oe a 33 3223 OMAP IC CONTO aaa 34 3224 SMBus Interface eine FR ho e cie 34 3 2 3 VO Controller Hub ICH5 R ein di ta pet ch ea ada ete 34 A A Rae ete O Eb telas 34 3 2 3 2 IDE Interface Bus Master Capability and Synchronous DMA Mode 34 3 2 9 9 SATA Controller A sted apatite eu A A SERES S creed 35 3 2 3 4 Low Pin Count LPC Interface iuis aeo cuero tas denas tro tenent ays oe 35 3 2 3 5 Compatibility Modules DMA Controller Timer Counters Interrupt Controller 35 3 2 3 6 Advanced Programmable Interrupt Controller APIC esses 36 3 2 3 7 Universal Serial Bus USB Controller
17. message is typically displayed when the BIOS is trying to Revision 1 0 157 C78844 002 Error Reporting and Handling Intel Server Board SE7520JR2 Message Displayed Description detect and configure IDE ATAPI devices in POST Primary Slave Hard Disk Error The IDE ATAPI device configured as Primary Slave could not be properly initialized by the BIOS This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST Secondary Master Hard Disk Error The IDE ATAPI device configured as Secondary Master could not be properly initialized by the BIOS This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST Secondary Slave Hard Disk Error The IDE ATAPI device configured as Secondary Slave could not be properly initialized by the BIOS This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST 3 Master Hard Disk Error The IDE ATAPI device configured as Master in the g IDE controller could not be properly initialized by the BIOS This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST 3 Slave Hard Disk Error The IDE ATAPI device configured as Slave in the 3 IDE controller could not be properly initialized by the BIOS This message is typically displayed when the BIOS is try
18. s sw 7 5 8 Keyboard and Mouse Connector Two stacked PS 2 ports are provided to support both a keyboard and a mouse Either PS 2 port can support a mouse or keyboard The following table details the pin out of the PS 2 connector Table 102 Stacked PS 2 Keyboard and Mouse Port Pin out 7 Test point keyboard mouse 10 11 12 E 15 16 17 4 emo 7 5 9 USB Connector The following table details the pin out of the external USB connectors found on the back edge of the server board Table 103 External USB Connector Pin out Pin SignalName DATALO Differential data line paired with DATAHO i DATAHO Differential data line paired with DATALO Revision 1 0 197 C78844 002 Connectors and Jumper Blocks Intel Server Board SE7520JR2 One internal 1x10 connector on the baseboard J1F1 provides an option to support an additional two USB 2 0 ports This connector is used in both the Intel Server Chassis SR1400 1U and SR2400 2U bringing USB support to the control panel The pin out of the connector is detailed in the following table Table 104 Internal 1x10 USB Connector Pin out J1F 1 Pin Signal name 1 USB_PWR 2 USB P2 L 6 USB_PWR 3 USB P3 L USB_P3 s foom For third party reference chassis an internal 2x5 connector J1G 1 is supplied to provide an additional two USB ports The pinout for this connector is found in the following table Table 1
19. 00A9h Interrupt Controller 2 aliased O0ACh 00ADh Interrupt Controller 2 aliased 00BOh 00B1h Interrupt Controller 2 aliased 67 Numere Coprocessor U 00F8h OOFFh X87 Numeric Coprocessor 01FOh 01F7h Primary Fixed Disk Controller IDE 0200h 0207h Game I O Port 0220h 022Fh Serial Port A EAN ees pM pO AA PA SOON 03B4h 03Bah Monochrome Display Port MEE Parallel Por 1 Primary ASA osco ocn Video Display Contaller O O SSS O S SOS O5DA OSDah Color Graphics Controle 5 et 3 Ru EI ac 03E8h O3Efh Serial Port A O3FOh O3F5h Floppy Disk Controller 03F6h 03F7h Primary IDE Sec Floppy Revision 1 0 77 C78844 002 Functional Architecture Intel Server Board SE7520JR2 Address es Resource Notes tsren 0arrn Serioa Hay A 0400h 043Fh DMA Conte 1 Extended Made Regs J oo CO ESTI SC oasen DA High Page Register O oaCon O4CFH DMA Contoler 2 High Base Register GDO OiDim memgtCanmole and 2ConvolRegiter DADA O4D7R DWACenwolerztxendedWojeRegsr amoa Reseed A OaEOH O4FFH DNA Channel Sp Regatas O CO EII CS 0878 087AN Parla PO EGP O CA E onoo Paine Ucr JmGiGoNFGADDRESSRe CS OCF9h Intel Server Board SE7520JR2 Turbo and Reset Control OCFCh PCI CONFIG_DATA Register Po 3 5 3 Accessing Configuration Space All PCI devices con
20. 01 Internal error IERR Processor 02 Internal error IERR Processor 01 Thermal Trip error Processor 02 Thermal Trip error C78844 002 Error Reporting and Handling Response Pause Not an error Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause Pause 163 Intel Server Board SE7520JR2 m o A D Lo o 2 Q E a I amp 3 a 3 Q Error Code Error Message 8130 Processor 01 disabled 8131 Processor 02 disabled 8140 Processor 01 failed FRB 3 timer 8141 Processor 02 failed FRB 3 timer 8150 Processor 01 failed initialization on last boot 8151 Processor 02 failed initialization on last boot 8160 Processor 01 unable to apply BIOS update 8161 Processor 02 unable to apply BIOS update 8170 Processor 01 failed BIST 8171 Processor 02 failed BIST 8180 BIOS does not support current stepping for Processor 1 8181 BIOS does not support current stepping for Processor 2 8190 Watchdog timer failed on last boot 8198 OS boot watchdog timer failure 8300 BaseBoard Management Controller failed Self Test 8301 Not enough space in Runtime area SMBIOS data will not be available 8305 Primary Hot swap Controller failed to function 84F1 BIST failed for all available processors 84F2 BaseBoard Management Controller failed to respond 84F3 BaseBoard Management Controller in Update Mode 84F4 Sensor Data Record Empty 84FF System Event Log Full 8500 Bad or missing memory in sl
21. 1 yo ney RT Faultled 4 0 0 0 0 0 0 0 BB 12V o pare gt 1 1 1 1 1 1 1 1 BB 12V Fault LED ra o 3 2 gt a Action DE MCH Vi T o gt a c Oo 02h 01h Action Revision 1 0 139 C78844 002 Platform Management Intel Server Board SE7520JR2 Sensor Event Event Offset Assert Readable PEF Sensor Name Reading Event Data 3 Type Type Triggers Deassert Value Offsets Action Tach Fan 6 Fan Threshold u c nc Analog Hed 01h Fan Threshold Fault LED Fan Threshold Fault LED Fan Threshold Fault LED Processor Sensor Proc1 IERR Specific IERR Trig Offset 97h 6Fh o N o N Processor Sensor Fault LED Proc1 Thermal trip 07h Specific Thermal Trip Trig Offset action 6Fh Sensor Fault LED Proc2 Thermal trip Specific Thermal Trip Trig Offset Action 6Fh Threshold Fault LED Threshold Fault LED Diagnostic Interrupt Critical Button Interrupt Specific FP NMI Button Trig Offset NMI Pulse Sate Chassis Identify Deasserted As amp De Trig Offset ID LED any State Assert Action Fan Threshold Fault LED Threshold Fault LED Threshold Fault LED Processor Sensor Proc2 IERR Specific IERR Trig Offset om 6Fh Threshold Fault LED CPU Configuration Processor Generic State Asserted As amp De Discrete Fault LED Error 03h EUN o o 140 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Platform Manageme
22. 375ma per slot and 3 slots Two slots 4 amps Description 1 amp per pin FL 3GIO Slot 1 DIF4P FL 3GIO Slot 1 DIF4N Pin Side PCI Spec Description Pin Side PCI Spec B Signal A Signal 138 138 GND 137 137 3 3VAux 136 136 135 GND 135 134 REFCLK2 FL 3GIO Slot 2 PXH DIF5P 134 T 133 REFCLK2 FL 3GIO Slot 2 PXH DIF5N 133 PERST N 132 GND 132 GND 131 GND 131 REFCLK1 130 HSOp 0 130 REFCLK1 129 HSOn 0 129 128 128 HSIp 0 127 GND 127 HSIn 0 126 HSOp 1 126 GND 125 HSOn 1 125 GND 124 GND 124 HSIp 1 123 GND 123 HSIn 1 122 HSOp 2 122 GND 121 HSOn 2 121 GND 120 GND 120 HSIp 2 119 GND 119 HSIn 2 118 HSOp 3 118 GND 117 HSOn 3 117 116 GND 116 HSIp 3 115 GND 115 HSIn 3 114 HSOp 4 114 GND 113 HSOn 4 113 112 GND 112 HSIp 4 111 GND 111 HSIn 4 110 HSOp 5 110 GND 109 HSOn 6 109 108 GND 108 HSIp 5 107 GND 107 HSIn 5 106 HSOp 6 106 105 HSOn 6 105 104 GND 104 HSIp 6 103 GND 103 HSIn 6 102 HSOp 7 102 GND 180 C78844 002 Revision 1 0 Intel Server Board SE7520JR2 Connectors and Jumper Blocks Pin Side PCI Spec B Signal 101 HSOn 7 100 GND 99 5V 98 INTB 97 INTD 96 5V 95 Reserved 94 5V 93 IOP INTA 92 IOP INTB 91 GND 90 CLK3 59 88 CLK2 87 GND 86 REQ2 85 GND 8i 83 GND KEY 82 81 GND 80 CLK1 73 78 REQ1 Revision 1 0 Description Pin Side A 101 100 99 This pin will be connected on 98 the 2U riser to INT_B of the bottom PCI slo
23. 5 3 17 3 Request Response Protocol ocococccicicicicnccnnnenncnnnninnninnninnnnnnnnnnnnnnnninnninnninnness 134 5 3 17 4 Host to mBMC Communication Interface rsrrrnnnnnnnnonnnnrrrrnnnnnnnnnnnnnvnvnnnnnnn 134 531 00 EAN Interface ci eerte ee 135 5 3 18 Event Filtering and Alerting 222 c cccccesescesecceteeeeneeseseececeeeeeeeseneseceteecesteeeseeecen 136 5 3 18 1 Platform Event Filtering PEF 5 reet Itt erae dena 136 5 3 18 2 Alert over LAN cd cccsiccacesiccangecbaacscaatsactncataaesslacnsdtsdaanccesagetezacceagegctancctbanciabontads 137 5 3 19 mBMG Sensor S pport z retta A a dela ee Lees 137 5 3 20 IMM BMC Sensor Support srnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnrnnnennnennnennnsnnnsnnnsnnnsnnne 142 5 4 Wired For Management WFM ccccceesseeneceeeeeeeeeeesseceeeeeeeeeeneeseeeeeneneetenee 148 5 5 Vital Product Data VPD iio ti 148 5 6 System Management BIOS SMBIOS ssssseem 148 6 Error Reporting and Handling ennvvvvnnnnnnnnnnnnnvnnvnnnnnnnnnnnnnnnnennnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnvnnennnnnr 149 6 1 Fault Resilient Booting FRB erit inn 149 6 1 1 FRB1 BSP Self Test Failures ooooooooocoonnconoconcconcnoncnonnnnnnnnnnnnonnnonnnonnnonnnnnnos 149 6 1 2 ERB2 BSPPOST Pallures ai MERE 149 6 1 3 FRB3 BSP Reset Failures ooooooooocoonoconcconcconcnoncnoncnnnnononononnnnnnnnnnnnnnnnnnonnnonnnos 150 6 1 4 P dd a IC 151 6 1 5 Treatment of Fa
24. 5 Option ROM Disabled PCI X 64 133 Visible only when installed Enabled riser supports this slot Slot 6 Option ROM Disabled PCI X 64 133 Visible only when installed Enabled riser supports this slot 4 4 2 2 7 Memory Configuration Sub menu This sub menu provides information about the DIMMs detected by the BIOS The DIMM number is printed on the baseboard next to each device Table 30 BIOS Setup Memory Configuration Sub menu Selections Feature Options HelpText Description System Memory Settings DIMM 1A Installed Not Installed Disabled Mirror Spare DIMM 1B Installed Informational display Not Installed Disabled Mirror Spare Informational display Informational display DIMM 2A Installed Not Installed Disabled Mirror Spare DIMM 2B Installed Not Installed Disabled Mirror Spare Informational display 94 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 System BIOS Feature Options Help Text DIMM 3A Installed Informational display Not Installed Disabled Mirror Spare DIMM 3B Installed Informational display Not Installed Disabled Mirror Spare Extended Memory Test 1 MB Settings for extended memory test 1 KB Every Location Disabled Memory Retest Disabled If Enabled BIOS will activate and Enabled retest all DIMMs on the next system boot This option will automactically reset to Disabled on the next system boot Memory Remap Feature Di
25. 5V Standby is used by the following onboard management devices e Management Controller BMC and or mBMC and associated RAM Flash and SEEPROM which are used to monitor the various system power control sources including the front panel Power Button the baseboard RTC alarm signal and power on request messages from the auxiliary IPMB connector and PCI SMBus e On board NICs that support IPMI over LAN and LAN Alerting Wake On LAN and Magic Packet operation e Emergency management port e IPMB e PCI SMBus in addition to certain logic and private busses used for power control e ICMB Transceiver card if present e IPMB isolation circuit e System Status LED on the front panel e System Identify LED 5 1 2 IPMI Messaging Commands and Abstractions xxx The IPMI specification defines a standardized abstracted message based interface between software and the platform management subsystem and a common set of messages commands for performing operations such as accessing temperature voltage and fan sensors setting thresholds logging events controlling a watchdog timer etc IPMI also includes a set of records called Sensor Data Records SDRs that make the platform management subsystem self descriptive to system management software The SDRs include software information such as how many sensors are present what type they are and what events they generate The SDRs also include information such as minimum and maximum ranges sensor type
26. 79 3 6 Clock Generation and Distribution nn 79 4 System BIOS ais oda adi 80 4 1 BIOS Identification Strings ioa a cede dtr hs poat i atat serte 80 4 2 Flash Architecture and Flash Update Utility sees 81 vi Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Table of Contents 4 3 BIOS Power On Self Test POST Lusliasa eusosiale 81 4 3 1 Bcc 81 4 3 1 1 System Activity WIndOW icr n cento dett re n chee Ihe eve date id 82 4 3 1 2 Splash Screen Diagnostic Window eseeem ee 82 4 2 1 3 POSTA MY VVIDCOW s aie tene Ait nee ee Gee Queene eg ds ats 83 4 3 2 BIOS Boot Popup Menu sarrien a e a Aai 83 4 4 BIOS Setup Ulla inania A AE 84 4 4 1 EOCANZA LON arias RTT ELS 84 4 4 2 Entenng BIOS Setup eslora cnt 85 442 Mam Mel ais A ra apnoea rd A E 85 4422 Advanced Menu coincidir 86 44 2 3 Boot Menus e ede ado di 95 44 24 Secunty Menu underslekter Daa Daaka AET iaaa A hino Re dte sup GTGT 98 4425 Server Me ni ire n cc Ua Ru diia 99 4425 EXEC uie dito telo pe lr ed le AS 102 4 5 Rolling BIOS and On line Updates cccccccceceeeeeenecceeeeenenseeseeeneeeeeeeeetseeeeeees 102 4 5 1 Flash Update Utilice o ER ERE ented endian 103 45 1 1 WlasW BIOS se E one ae 103 45 1 2 User Binary AEA uo oodd reip e Putent usto Gh pietate funt 103 455 123 Recovery Mode Lus cort tede A 103 4514 BIOS ROGGEN udekket etas e dDued 104 4 5 2 Configuration Reset e ettet aod ir e e ERE
27. BIOS before it can be used The BIOS must initialize all memory locations before using them The BIOS uses the auto initialize feature of the MCH to initialize ECC ECC memory initialization cannot be aborted and may result in a noticeable delay in the boot process depending on the amount of memory installed in the system 3 3 4 Memory Test System memory is classified as base and extended memory Base memory is memory that is required for POST Extended memory is the remaining memory in the system Extended memory may be contiguous or may have one or more holes The BIOS memory test accesses all memory except for memory holes Memory testing consists of separate base and extended memory tests The base memory test runs before video is initialized to verify memory required for POST The BIOS enables video as early as possible during POST to provide a visual indication that the system is functional At some time after video output has been enabled BIOS executes the extended memory test The 40 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture status of the extended memory test is displayed on the console The status of base and extended memory tests are also displayed on an LCD control panel if present The extended memory test is configured using the BIOS Setup Utility The coverage of the test can be configured to one of the following e Test every location Extensive e Test one interleave width per kilo byt
28. BIOS modules OFF ru R Initialize Initialize System Management Interrupt Management Interrupt OFF Initializes different devices ESI a DIM See DIM Code Checkpoints section of document for more information OFF insta different devices Detects and initializes the video adapter OFF insta in the system that have optional ROMs o a Allocate memory for ADM module and uncompress it Give control to ADM module for initialization Initialize language and font modules for ADM Activate ADM module OFF OFF Initializes the silent boot module Set the window for displaying text information Displaying sign on message CPU information setup key message and any OEM specific information 38 G OFF Initializes different devices through DIM See DIM Code Checkpoints section of document for more information Spore ap R Initialize RTC Initialize RTC datetime OFF LI ES for total memory installed in the system Also Check for DEL or ESC keys to limit memory test Display total memory in the system ete te Mid POST initialization of chipset registers Detect different devices Parallel ports serial ports and coprocessor 40 OFF OFF OFF in CPU etc successfully installed in the system and update the BDA EBDA etc 50 OFF OFF Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed 52 OFF G Updates CMOS memory size from memory found in
29. CPUID of the processor Cache L3 N A N A Displays cache L3 size Visible only if the processor contains an L3 cache CPU 2 CPUID N A N A Displays the CPUID of the processor Cache L3 N A N A Displays cache L3 size Visible only if the processor contains an L3 cache Processor Retest Disabled If enabled all processors will Rearms the processor sensors Enabled be activated and retested on Only displayed if the Intel the next boot This option will Management Module is be automatically reset to present disabled on the next boot Max CPUID Value Limit Disabled This should be enabled in Enabled order to boot legacy OSes that cannot support processors with extended CPUID functions Hyper Threading Technology Disabled Enable Hyper Threading Controls Hyper Threading state Enabled Technology only if OS Primarily used to support older supports it Operating Systems that do not support Hyper Threading Intel amp Speed Step Tech Auto Select disabled for maximum Note This option may not be Disabled CPU speed Select enabled present in early Beta releases to allow the OS to reduce power consumption Revision 1 0 87 C78844 002 System BIOS 4 4 2 2 2 Intel Server Board SE7520JR2 IDE Configuration Sub menu Table 22 BIOS Setup IDE Configuration Menu Options Feature Options Help Text IDE Configuration Onboard P ATA Channels Disabled Primary Secondary Both Onboard S ATA Channels
30. Card Revision 1 0 57 C78844 002 Functional Architecture Intel Server Board SE7520JR2 3 4 4 SCSI Support The SCSI sub system consists of the LSI 53C1030 Dual Channel Ultra320 SCSI controller one internal 80 pin connector SCSI Channel A one external high 80 pin density SCSI connector SCSI channel B and on board termination for both SCSI channels 3 4 4 1 LSI 53C1030 Dual Channel Ultra320 SCSI Controller The LSI53C1030 is a PCI X to Dual Channel Ultra320 SCSI Multifunction Controller that supports the PCI Local Bus Specification Revision 2 2 and the PCI X Addendum to the PCI Local Bus Specification Revision 1 0a The LSI53C1030 supports up to a 64 bit 133 MHz PCI X bus DT clocking enables the LSI53C1030 to achieve data transfer rates of up to 320 megabytes per second MB s on each SCSI channel for a total bandwidth of 640 MB s on both SCSI channels SureLINK Domain Validation detects the SCSI bus configuration and adjusts the SCSI transfer rate to optimize bus interoperability and SCSI data transfer rates SureLINK Domain Validation provides three levels of domain validation assuring robust system operation The LSI53C1030 integrates two high performance SCSI Ultra320 cores and a 64 bit 133 MHz PCI X bus master DMA core The LSI53C1030 employs three ARM ARM966E S processors to meet the data transfer flexibility requirements of the Ultra320 SCSI PCI and PCI X specifications Separate ARM processors support each SCSI c
31. Core EPS for IPMI based Systems e Sahalee Core BMC EPS for IPMI v1 5 These documents are not publicly available and must be ordered by your local Intel representative 1 1 Chapter Outline This document is divided into the following chapters e Chapter 1 Introduction e Chapter 2 Product Overview e Chapter 3 Board Architecture e Chapter 4 System BIOS e Chapter 5 Platform Management Architecture e Chapter 6 Error Reporting and Handling e Chapter 7 Connector Pin out and Jumper Blocks e Chapter 8 Environmental Specifications e Chapter 9 Miscellaneous Board Information e Appendix A Integration and Usage Tips Revision 1 0 19 C78844 002 Introduction Intel Server Board SE7520JR2 1 2 Server Board Use Disclaimer Intel Corporation server boards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel ensures through its own chassis development and testing that when Intel server building blocks are used together the fully integrated system will meet the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the ser
32. D R D R S R E D R S R Table 4 Supported DDR 333 DIMM Populations MCH Bank 3 DIMMs 3A 3B Bank 2 DIMMs 2A 2B2 Bank 1 DIMMs 1A 1B S R S R S R E S R S R E E S R Revision 1 0 C78844 002 39 Functional Architecture Intel Server Board SE7520JR2 E D R D R E E D R D R S R S R E D R S R Table 5 Supported DDR2 400 DIMM Populations Bank 3 DIMMs 3A 3B Bank 2 DIMMs 2A 2B Bank 1 DIMMs 1A 1B S R S R S R E S R S R E E S R MCH E D R D R E E D R E S R D R S R S R D R Note On the Server Board SE7520JR2 when using all dual rank DDR 333 or DDR2 400 DIMMs a total of four DIMMs can be populated Configuring more than four dual rank DDR 333 or DDR2 400 DIMMs will result in the BIOS generating a memory configuration error Note Memory between 4GB and 4GB minus 512MB will not be accessible for use by the operating system and may be lost to the user because this area is reserved for BIOS APIC configuration space PCI adapter interface and virtual video memory space This means that if 4GB of memory is installed 3 5GB of this memory is usable The chipset should allow the remapping of unused memory above the 4GB address but this memory may not be accessible to an operating system that has a 4GB memory limit 3 3 3 ECC Memory Initialization ECC memory must be initialized by the
33. Dual rank DIMMs are populated before single rank DIMMs C A maximum of four DIMMs can be populated when all four DIMMs are dual rank DDR2 400 DIMMs e Onthe Server Board SE7520JR2 when using all dual rank DDR 333 or DDR2 400 DIMMs a total of four DIMMs can be populated Configuring more than four dual rank DDR 333 or DDR2 400 DIMMs will result in the BIOS generating a memory configuration error e The DIMM Sparing feature requires that the spare DIMM be at least the size of the largest primary DIMM in use e Itis possible for a Memory RASUM feature to be initiated without notification that the action has occurred when using standard on board platform instrumentation e AZCR card is only supported on the full height riser slot When installing the card it MUST be populated in the PCI X add in slot furthest from the baseboard e The Server Board SE7520JR2 has support for Zero Channel RAID ZCR which follows the RUBI2 standard It will not have support for zero channel RAID cards that follow the RADIOS standard Revision 1 0 221 C78844 002 Glossary Intel Server Board SE7520JR2 Glossary This appendix contains important terms used in the preceding chapters For ease of use numeric entries are listed first e g 82460GX with alpha entries following e g AGP 4x Acronyms are then entered in their respective place with non acronyms following LI 5 Chassis bridge controller A microcontroller connected to one or more o
34. Functional Architecture 3 4 10 2 Serial Ports The baseboard provides two serial ports an external RJ45 Serial B port and an internal DH10 Serial A header The following sub sections provide details on the use of the serial ports 3 4 10 2 1 Serial Port A Serial A is an optional port accessed through a 9 pin internal DH 10 header A standard DH10 to DB9 cable is used to direct Serial A out the back of a given chassis The Serial A interface follows the standard RS232 pin out as defined in the following table Table 14 Serial A Header Pin out Pin Signal Name Serial Port A Header Pin out DCD DSR RX RTS TX CTS DTR RI GND Ed GOG D J n w DOLO CO CO NI DI OI By VI N gt 3 4 10 2 2 Serial Port B Serial B is an external 8 pin RJ45 connector that is located on the back edge of the baseboard For serial devices that require a DB 9 connector an appropriate RJ45 to DB9 adapter is necessary 3 4 10 2 3 Serial Port Multiplexer Logic The Server Board SE7520JR2 has a multiplexer to connect the rear RJ45 connector to either Serial Port A or Serial Port B This facilitates the routing of Serial Port A to the rear RJ45 connector if Serial Port B is used for Serial Over LAN SOL This serial port selection can be done through the BIOS setup option The figure below shows the serial port mux functionality Revision 1 0 67 C78844 002 Functional Architecture Intel
35. Hard disk drive The action taken on timeout is 15 minutes determined by the OS Watchdog 20 minutes Timer policy setting 10 minutes PXE OS Boot Timeout Disabled This controls the time limit 5 minutes allowed for booting an operating i system using PXE boot The 10 minutes action taken on timeout is 15 minutes determined by OS Watchdog 20 minutes Timer policy setting OS Watchdog Timer Policy Stay On Controls the policy upon timeout Reset Stay on action will take no overt action Reset will force the Power Off system to reset Power off will force the system to power off Platform Event Filtering Disabled Disable trigger for system sensor Enabled events 4 4 2 5 1 System Management Sub menu Selections Table 39 BIOS Setup System Management Sub menu Selections Help Text Field contents varies Field contents varies oe oe Board Part Number AAA gt Field contents varies Chassis Part Number Field contents varies Field contents varies Field contents varies Field contents varies NA o Field contents varies contents varies BIOS ID string the build time and date Field contents varies Chassis Serial Number Serial Number HSC FW Revision HSBP Field contents varies Field contents varies Firmware revision of the Hot swap controller Displays n a if the controller is not present 100 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 System BIOS 4 4 2 5 2 Serial Console Featu
36. Intel Xeon 800 MHz 3 6 GHz 3 1 6 1 Processor Mis population Detection The processors must be populated in the correct order for the processor front side bus to be correctly terminated CPU socket 1 must be populated before CPU socket 2 Baseboard logic will prevent the system from powering up if a single processor is present but it is not in the correct socket This protects the logic against voltage swings or unreliable operation that could occur on an incorrectly terminated front side bus If processor mis population is detected when using standard on board platform instrumentation the mBMC will log an error against processor 1 to the System Event Log Configuration Error and the baseboard hardware will illuminate both processor error LEDs If an IMM Professional or Advanced editions is used in systems the Sahalee BMC will generate a series of beep codes when this condition is detected and the BMC will illuminate the processor 1 fault LED 3 1 6 2 Mixed Processor Steppings For optimum system performance only identical processors should be installed in a system Processor steppings within a common processor family can be mixed in a system provided that there is no more than a 1 stepping difference between them If the installed processors are more than 1 stepping apart an error is reported Acceptable mixed steppings are not reported as errors by the BIOS 3 1 6 3 Mixed Processor Models Processor models cannot be mixed in a sy
37. Mirroring mode Table 57 Memory Error Handling mBMC vs Sahalee Server with mBMC When Sparing or Mirroring occurs BIOS will not report memory RAS configuration to mBMC BIOS will light the faulty DIMM LED DIMMs which go off line during OS runtime will be back online on the next system reboot without user intervention Sparing and Mirroring states are not sticky across system reset Server with IMM Sahalee BMC When Sparing or Mirroring occurs BIOS will report memory RAS configuration to BMC BIOS will light the faulty DIMM LED DIMMs which go off line during OS runtime will not be back online on the next system reboot Sparing and Mirroring states are sticky across system reset Setting Memory Retest option in BIOS Setup will re enable off line DIMMs Note BIOS does not support Memory Data Scrubber Error 6 2 2 Memory Error Handling in non RAS Mode If memory RAS features are not enabled in BIOS Setup BIOS will apply 10 SBE errors in one hour implementation Enabling of this implementation and RAS features are mutually exclusive and automatically handled by system BIOS In non RAS mode BIOS maintains a counter for Single Bit ECC SBE errors If ten SBE errors occur within an hour BIOS will disable SBE detection in the chipset to prevent the System Event Log SEL from being filled up and the OS from being halted Revision 1 0 153 C78844 002 Error Reporting and Handling Intel
38. Rate Test Capacitive Load See note 2 12V1 12V2 12V3 20 0A 0 25 A usec 2200 uF Notes 1 Step loads on each 12V output may happen simultaneously 2 ForLoad Range 2 light system loading the tested step load size should be 60 of those listed 3 The 12V should be tested with 1000uF evenly split between the three 12V rails Revision 1 0 207 C78844 002 Design and Environmental Specifications Capacitive Loading The power supply shall be stable and meet all requirements with the following capacitive loading ranges Table 120 Capacitve Loading Conditions Output MIN MAX Units 3 3V 250 6 800 uF 5V 400 4 700 uF 12V 1 2 3 500 each 11 000 uF 12V 1 350 uF 5VSB 20 350 uF Closed Loop Stability Intel Server Board SE7520JR2 The power supply shall be unconditionally stable under all line load transient load conditions including capacitive load ranges A minimum of 45 degrees phase margin and 10dB gain margin is required Closed loop stability must be ensured at the maximum and minimum loads as applicable 8 2 9 Common Mode Noise The Common Mode noise on any output shall not exceed 350mV pk pk over the frequency band of 10Hz to 30MHz 8 2 10 Ripple Noise The maximum allowed ripple noise output of the power supply is defined in the following table This is measured over a bandwidth of OHz to 20MHz at the power supply output connectors Table 121 Ripple and Noise
39. Server Board SE7520JR2 Serial B Bus SIO l Exchange BMC Serial A 2 to 1 Mux Level Level Shifter shifter Rear Header RJ45 Figure 12 Serial Port Mux Logic 3 4 10 2 4 Rear RJ45 Serial B Port Configuration The rear RJ45 Serial B port is a fully functional serial port that can support any standard serial device Using an RJ45 connector for a serial port gives direct support for serial port concentrators which are widely used in the high density server market For server applications that use a serial concentrator to access the server management features of the baseboard a standard 8 pin CAT 5 cable from the serial concentrator is plugged directly into the rear RJ45 serial port To support either of two serial port configuration standards which require either a DCD or DSR signal a jumper block J7A1 located near the back IO ports is used to configure the RJ45 serial port to the desired standard The following diagram shows the jumper block location and its jumper settings 3 4 SIE 1 2 Pins 1 amp 3 DCD to DTR Pins 2 amp 4 DSR to DTR Factory Default Figure 13 RJ45 Serial B Port Jumper Block Location and Setting 68 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture Note The appropriate RJ45 to DB9 adapter should match the configuration of the serial device used One of two pin out configurations is used depen
40. System BIOS 4 7 1 Operating Model Intel Server Board SE7520JR2 The following table summarizes the operation of security features supported by the BIOS Some security features require the Intel Management Module IMM to be installed These include Diskette Write Protect Entry Method Event Secure boot Power On Reset Power On Reset Password on boot Fixed disk boot sector Power On Reset 106 Table 43 Security Features Operating Model Entry Criteria Exit Criteria After Exit User Password and Secure Boot Enabled User Password set and password on boot enabled and Secure Boot Disabled in setup Set feature to Write Protect in Setup User Password Admin Password Prompts for password if booting from drive A Enters secure mode just before scanning option ROMs as indicated by flashing LEDs on the keyboard Disables the NMI switch on the front panel if enabled in Setup Accepts no input from PS 2 mouse or PS 2 keyboard however the Mouse driver is allowed to load before a password is required If booting from drive A and the user enters correct password the system boots normally If the IMM module is installed and the options are enabled in Setup the system also blanks on board video disables floppy writes and disables the power and reset switches on the front panel System halts for user Password before scanning option ROMs The system is not in secure
41. Update to the CPU This message only applies to INTEL CPUs The message is most likely to appear when a brand new CPU is installed in a motherboard with an outdated BIOS In this case the BIOS must be updated to include the Microcode Update for the new CPU NVRAM Checksum Bad NVRAM Cleared There was an error in while validating the NVRAM data This causes POST to clear the NVRAM data Resource Conflict More than one system device is trying to use the same non shareable resources Memory or I O NVRAM Ignored The NVRAM data used to store Plug n Play PnP data was not used for system configuration in POST NVRAM Bad The NVRAM data used to store Plug n Play PnP data was not used for system configuration in POST due to a data error Static Resource Conflict Two or more Static Devices are trying to use the same resource space usually Memory or 1 0 PCI I O conflict A PCI adapter generated an I O resource conflict when configured by BIOS POST PCI ROM conflict A PCI adapter generated an I O resource conflict when configured by BIOS POST PCI IRQ conflict A PCI adapter generated an I O resource conflict when configured by BIOS POST PCI IRQ routing table error BIOS POST DIM code found a PCI device in the system but was unable to figure out how to route an IRQ to the device Usually this error is causing by an incomplete description of the PCI Interrupt Routing of the
42. When Blue Off Ok Blink Identify button pressed or Chassis Identify command executed 5 3 5 5 Control Panel Inputs The mBMC monitors the control panel switches and other chassis signals The control panel input buttons are momentary contact switches which are de bounced by the mBMC processor firmware The de bounce time is 25 ms Revision 1 0 129 C78844 002 Platform Management Intel Server Board SE7520JR2 5 3 5 5 1 Chassis Intrusion Some platforms support chassis intrusion detection On those platforms the mBMC monitors chassis intrusion by polling the server input output SIO device The state of the chassis intrusion input is provided by the status register of the SIO device A Chassis Intrusion event is logged in the System Event Log when a change in the input state is detected 5 3 5 5 2 Power Button The Power Button signal is used to toggle system power The Power Button signal to the mBMC is activated by a momentary contact switch on the control panel assembly The mBMC de bounces the signal After de bouncing the signal the mBMC routes it directly to the chipset via the Power Button signal If the chipset has been initialized by the BIOS the chipset responds to the assertion of the signal It reacts to the press of the switch not the release of it If the system is in Secure Mode or if the Power Button is forced protected then when the power switch is pressed a Platform Security Violation Attempt event message is gen
43. a generic message indicating the BIOS could not boot from a particular device This message is usually followed by other information concerning the device Invalid Boot Diskette A diskette was found in the drive but it is not configured as a bootable diskette Drive Not Ready The BIOS was unable to access the drive because it indicated it was not ready for data transfer This is often reported by drives when no media is present A Drive Error The BIOS attempted to configure the A drive during POST but was unable to properly configure the device This may be due to a bad cable or faulty diskette drive B Drive Error The BIOS attempted to configure the B drive during POST but was unable to properly configure the device This may be due to a bad cable or faulty diskette drive Insert BOOT diskette in A The BIOS attempted to boot from the A drive but could not find a proper boot diskette Reboot and Select proper Boot device or Insert Boot Media in selected Boot device BIOS could not find a bootable device in the system and or removable media drive does not contain media NO ROM BASIC This message occurs on some systems when no bootable device can be detected Table 61 Storage Device BIOS Messages Message Displayed Description Primary Master Hard Disk Error The IDE ATAPI device configured as Primary Master could not be properly initialized by the BIOS This
44. accuracy and tolerance etc that guides software in interpreting and presenting sensor data Together IPMI Messaging and the SDRs provide a self descriptive abstracted platform interface that allows management software to automatically configure itself to the number and types of platform management features on the system In turn this enables one piece of management software to be used on multiple systems Since the same IPMI messages are used over the serial modem and LAN interfaces a software stack designed for in band local management access can readily be re used as an out of band remote management stack by changing the underlying communications layer for IPMI messaging 116 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Platform Management 5 1 3 IPMI Sensor Model An IPMI compatible Sensor Model is used to unify the way that temperature voltage and other platform management status and control is represented and accessed The implementation of this model is done according to command and data formats defined in the Intelligent Platform Management Interface Specification The majority of monitored platform elements are accessed as logical Sensors under this model This access is accomplished using an abstracted message based interface IPMI messages Instead of having system software access the platform monitoring and control hardware registers directly it sends commands such as the Get Sensor Reading c
45. and displays it in SMBIOS structures and in BIOS Setup 5 6 System Management BIOS SMBIOS The BIOS provides support for the SMBIOS specification to create a standardized interface for manageable attributes that are expected to be supported by DMI enabled computer systems The BIOS provides this interface via data structures through which the system attributes are reported Using SMBIOS a system administrator can obtain the types capabilities operational status installation date and other information about the system components Refer to the SE7520JR2 BIOS EPS for detail describing access methods to the SMBIOS structure tables 148 C78844 002 Revision 1 0 Intel Server Board SE7520JR2 Error Reporting and Handling 6 Error Reporting and Handling This section defines how errors are handled Also discussed is the role of the BIOS in error handling and the interaction between the BIOS platform hardware and server management firmware with regard to error handling In addition error logging techniques are described and beep codes and POST messages are defined Note The generic term BMC may be used throughout this secton when a feature and or function being described is common to both the mBMC and the Sahalee BMC If a described feature or function is unique the specific management controller will be referenced 6 1 Fault Resilient Booting FRB Fault Resilient Booting FRB is a set of BIOS and BMC algorithms and ha
46. and perform the following functions Boot Input Device Initialization function 3 Function 3 searches for and configures PCI input devices and detects if system has standard keyboard controller PL Device Initialization function 4 Function 4 searches for and configures all PnP and PCI boot devices General Device Initialization function 5 Function 5 configures all onboard peripherals that are set to an automatic configuration and configures all remaining PnP and PCI devices 172 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Error Reporting and Handling 6 5 7 ACPI Runtime Checkpoints ACPI checkpoints are displayed when an ACPI capable operating system either enters or leaves a sleep state The following table describes the type of checkpoints that may occur during ACPI sleep or wake events Table 79 ACPI Runtime Checkpoints Checkpoint First ASL check point Indicates the system is running in ACPI mode System is running in APIC mode 01 02 03 04 05 Entering sleep state S1 S2 S3 S4 or S5 10 20 30 40 50 Waking from sleep state S1 S2 S3 S4 or S5 6 5 8 POST Progress FIFO Professional Advanced only With SE7520JR2 based platforms that utilize either the Professional or Advanced management modules the Sahalee BMC will maintain a RAM FIFO of the last 16 post progress codes that it has received Accompanying this FIFO is a timestamp that indicates when the last code was received By d
47. any form or by any means without the express written consent of Intel Corporation Intel Corporation server boards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non operating limits Intel Pentium Itanium and Xeon are trademarks or registered trademarks of Intel Corporation Other brands and names may be claimed as the property of others Copyright Intel Corporation 2004 Revision 1 0 iii C78844 002 Table of Contents Intel Server Board SE7520JR2 Table of Contents 1 Ut AU CE ON e 19 1 1 Chapter Outlines diss ii Wiens ete aoe LENGE Ra ioc cave dci 19 1 2 Server Board Use Disclaimer ccccccccccccccececececeeeceeeceeeeceeeeeeeeeeeeeeeeeeseeeeeeeeeeees 20 2 Server Board Overview e cerei nani rin t nien rir Eae eR ERE eara rr Ren ska Fr aen ERE ka E rS Eye ERR RR ERR RA E
48. are Sensor Type code 13h Critical Interrupt and Sensor Specific offset Oh 5 3 5 5 5 Chassis Identify Button The chassis identify button on the control panel toggles the state of the Chassis ID LED If the Chassis ID LED is off pressing this button causes the LED to blink for 15 seconds After this 130 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Platform Management time the LED will turn off If the LED is on a button press or IPMI Chassis Identify command turns off the LED Upon assertion of the chassis identify button a SEL event is generated by the chassis identity sensor button The event attributes are Sensor Type code 14h Button and Sensor Specific offset 1h 5 3 6 Secure Mode Operation The mBMC handles the secure mode feature which allows the control panel power and reset buttons to be protected against unauthorized use or access Secure mode is a signal from the keyboard controller and is asserted when the keyboard controller is in a locked state Power and reset buttons are locked and a security violation event is generated if these buttons are pressed while secure mode is active Secure Mode state is cleared whenever the System is powered down the Set Chassis Capabilities command is issued to change the Secure Mode state or the FP_LOCK signal is de asserted 5 3 7 Baseboard Fan Control Fan control is performed by two pulse width modulator PWM outputs on the LM93 The 3 pin CPU fan heade
49. both bits are clear then the LED is off In the below example BIOS sends a value of ACh to the Diagnostic LED decoder The LEDs are decoded as follows e Red bits 1010b Ah e Green bits 1100b Ch Since the red bits correspond to the upper nibble and the green bits correspond to the lower nibble the two are concatenated to be ACh Table 74 POST Progress Code LED Example LEDs Red Green Red Green Red Green Red Green EEE Revision 1 0 167 C78844 002 Error Reporting and Handling Intel Server Board SE7520JR2 Diagnostic LEDs Back edge of baseboard Figure 24 Location of Diagnostic LEDs on Baseboard 6 5 3 POST Code Checkpoints Table 75 POST Code Checkpoints Diagnostic LED Decoder Description Checkpoint G Green R Red A Amber G Green R Red A Amber Green R Red A Amber Disable NMI parity video for EGA and DMA controllers Initialize BIOS POST Run time data area Initialize BIOS modules on POST entry and GPNV area Initialized CMOS as mentioned in the Kernel Variable wCMOSFlags Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK Verify CMOS checksum manually by reading storage area If the CMOS checksum is bad update CMOS with OFF power on default values and clear passwords Initialize status register A Initializes data variables that are based on CMOS setup questions Initializes both the 8259 compatible PICs in the system O
50. by a configurable set of platform events The mBMC supports the following IPMI PEF actions e Power down e Soft shutdown pulse ACPI power button signal e Power cycle e Reset e Diagnostic Interrupt e Alert In addition the mBMC supports the following OEM actions e Fault LED action e Identification LED action e Device feedback Generate specified transaction on peripheral SMBus or change level of DEIO pins The power down soft shutdown power cycle and reset actions can be delayed by a specified number of 100ms up to the maximum PEF delay defined in the IPMI 1 5 specification The mBMC maintains an Event Filter table with 30 entries that are used to select which actions to perform and one fixed read only Alert Policy Table entry No alert strings are supported Note All Fault Status LED and ID LED behaviors are driven off of PEF PEF should not be disabled and the default entry configuration should not be modified or else those behaviors will be changed Each time the PEF module receives an event message either externally or internally generated it compares the event data against the entries in the Event Filter table The mBMC scans all entries in the table and determines a set of actions to be performed according to the entries that were matched Actions are then executed in order of priority If there is a combination of power 136 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Platform Management down power
51. capabilities sensor types locations event generation and access information The SDR Repository is stored in the non volatile storage area flash of the mBMC The SDR Repository is accessible via all channels This way out of band interfaces can be used to access SDR Repository information while the system is down See Table 25 and Table 26 for additional sensor support The mBMC supports 2176 bytes of storage for SDR records The SDR defines the type of sensor thresholds hysteresis values and event configuration The mBMC supports up to six threshold values for threshold based full sensor records and up to 15 events for non threshold based full and compact sensor records The mBMC supports both low going and high going sensor devices If an Intel Management Module is installed in the server the mBMC SDRs are not accessible and are replaced by the Intel Management Module SDRs 5 3 11 1 Initialization Agent The mBMC implements the internal sensor initialization agent functionality specified in the Intelligent Platform Management Interface Specification Version 1 5 When the mBMC is initialized or a system is rebooted the initialization agent scans the SDR repository and configures the mBMC sensors referenced by the SDRs This includes setting sensor thresholds enabling disabling sensor event message scanning and enabling disabling sensor event messages 132 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Platform Manageme
52. cards that follow the RADIOS standard See the SE7520JR2 Tested Hardware and OS list for a list of supported ZCR cards Zero channel RAID ZCR capabilities enable the LSI 53C1030 to respond to accesses from a PCI RAID controller card or chip that is able to generate ZCR cycles The LSI53C1030 s ZCR functionality is controlled through the ZCR_EN and the IOPD GNT signals Both of these signals have internal pull ups and are active LOW The ZCR EN signal enables ZCR support on the LSI53C 1030 Pulling ZCR_EN LOW enables ZCR operation When ZCR is enabled the LSI53C1030 responds to PCI configuration cycles when the IOPD GNT and IDSEL signal are asserted Pulling ZCR EN HIGH disables ZCR support on the LS153C1030 and causes the LSI53C1030 to behave as a normal PCI X to Ultra320 SCSI controller When ZCR is disabled the IOPD GNT signal has no effect on the LSI53C1030 operation The IOPD GNT pin on the LSI53C1030 should be connected to the PCI GNT signal of the external I O processor This allows the I O processor to perform PCI configuration cycles to the LSI53C1030 when the I O processor is granted the PCI bus This configuration also prevents the system processor from accessing the LSI53C1030 PCI configuration registers On the Server Board SE7520JR2 a ZCR card is only supported on the full height riser slot When installing the card it MUST be populated in the PCI X add in slot furthest from the baseboard No other add in card slot has suppo
53. command issued from one of the command interfaces Use of this command will not cause an event to be logged in the SEL e Detecting that the control panel Diagnostic Interrupt button has been pressed Use of this command will cause a button event to be logged into the SEL Type code 13h Critical Interrupt Sensor Specific offset 6Fh e A PEF table entry matching an event where the filter entry has the NMI action indicated e Watchdog timer pre timeout expiration with NMI pre timeout action enabled Once an NMI has been generated by the mBMC the mBMC will not generate another until the system has been reset or powered down 5 3 14 SMI Generation The mBMC can be configured to generate an SMI due to Watchdog timer pre timeout expiration with SMI pre timeout interrupt specified 5 3 15 Event Message Reception The mBMC supports externally e g BIOS generated events via the Platform Event Message command Events received via this command will be logged to the SEL and processed by PEF Revision 1 0 133 C78844 002 Platform Management Intel Server Board SE7520JR2 5 3 16 mBMC Self Test The mBMC performs various tests as part of its initialization If a failure is determined e g corrupt mBMC FRU SDR or SEL the mBMC stores the error internally 5 3 17 Messaging Interfaces This section describes the supported mBMC communication interfaces e Host SMS Interface via SMBus interface e LAN interface using the LOM SMBus The
54. in the channel becomes defective DIMM sparing and memory mirroring are mutually exclusive e Hardware periodic memory scrubbing including demand scrub support e Retry on uncorrectable memory errors e xA SDDC for memory error detection and correction of any number of bit failures in a single x4 memory device 3 2 1 3 PCI Express The E7520 MCH is the first Intel chipset to support the new PCI Express high speed serial I O interface for superior I O bandwidth The scalable PCI Express interface complies with the PCI Express Interface Specification Rev 1 0a On the Server Board SE7520JR2 two of the three available x8 PCI Express interfaces are used each with a maximum theoretical bandwidth of 4 32 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture GB s One x8 interface is used as the interconnect between the MCH and PXH while the other is configured as two separate x4 interfaces to the full height riser slot The E7520 MCH is a root class component as defined in the PCI Express Interface Specification Rev 1 0a The PCI Express interfaces of the MCH support connection to a variety of bridges and devices compliant with the same revision of the specification Refer to the Server Board SE7520JR2 Tested Hardware and OS List for the add in cards tested on this platform 3 2 1 4 Hub Interface The MCH interfaces with the Intel 82801ER I O Controller Hub 5 R ICH5 R via a dedicated Hub Interface which sup
55. jumper J1H2 labeled RCVR BOOT to pins 2 3 e Damaging the ROM image which will cause the system to enter recovery and update the system ROM without the boot block Revision 1 0 103 C78844 002 System BIOS Intel Server Board SE7520JR2 4 5 1 4 BIOS Recovery The BIOS has a ROM image size of 2 MB A standard 1 44MB floppy diskette cannot hold the entire ROM file due to the large file size To compensate for this a Multi disk recovery method is available for BIOS recovery The BIOS contains a primary and secondary partition and can support rolling BIOS updates The recovery process performs an update on the secondary partition in the same fashion that the normal flash update process updates the secondary partition After recovery is complete and the power is cycled to the system the BIOS partitions switch and the code executing POST will be the code that was just flashed from the recovery media The BIOS is made up of a boot block recovery section a main BIOS section an OEM logo user binary section and an NVRAM section The NVRAM section will either be preserved or destroyed based on a hot key press during invocation of the recovery All the other sections of the secondary BIOS will be updated during the recovery process If an OEM wishes to preserve the OEM section across an update it is recommended that the OEM modify the provided AMIBOOT ROM file with the user binary or OEM logo tools before performing the recovery A BI
56. keep track of which timer expired early FRB2 late FRB2 or OS Watchdog and display the appropriate error message to the user All of the user options are intended to allow a system administrator to set up a system such that during a normal boot no gap exists during POST that is not covered by the watchdog timer Options are provided by the BIOS to control the policy applied to OS Watchdog timer failures By default an OS Watchdog Timer failure will not cause any action Other options provided by the BIOS are for the system to reset or power off watchdog timer failure However it should be noted that these failures will NOT result in a processor being disabled as could happen with an FRB2 failure 6 1 5 AP Failures In systems configured with an Intel Management Module the BIOS and Sahalee BMC implement additional safeguards to detect and disable the application processors AP in a multiprocessor system If an AP fails to complete initialization within a certain time it is assumed to be nonfunctional If the BIOS detects that an AP has failed BIST or is nonfunctional it requests the Sahalee BMC to disable that processor Processors disabled by the Sahalee BMC are not available for use by the BIOS or the operating system Since the processors are unavailable they are not listed in any configuration tables including SMBIOS tables 6 1 6 Treatment of Failed Processors All the failures FRB3 FRB2 FRB1 and AP failures including the fail
57. permits software independent entrance to low power states The ICH5 R contains full support for the Advanced Configuration and Power Interface ACPI Specification Revision 2 0b 3 2 3 11 System Management Bus SMBus 2 0 The ICH5 R contains an SMBus host interface that allows the processor to communicate with SMBus slaves This interface is compatible with most I C devices Special C commands are implemented The ICH5 R s SMBus host controller provides a mechanism for the processor to initiate communications with SMBus peripherals slaves 36 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture The ICH5 R supports slave functionality including the Host Notify protocol Hence the host controller supports eight command protocols of the SMBus interface Quick Command Send Byte Receive Byte Write Byte Word Read Byte Word Process Call Block Read Write and Host Notify See the System Management Bus SMBus Specification Version 2 0 for more information 3 3 Memory Sub System The MCH provides an integrated memory controller for direct connection to two channels of registered DDR 266 DDR 333 or DDR2 400 memory stacked or unstacked Peak theoretical memory data bandwidth using DDR266 technology is 4 26 GB s and 5 33 GB S for DDR333 technology For DDR2 400 technology this increases to 6 4 GB s The MCH supports a burst length of four whether in single or dual channel mode In dual channel mode this re
58. regard to error handling In addition error logging techniques are described and beep codes for errors are defined One of the major requirements of server management is to correctly and consistently handle system errors System error sources can be categorized as follows e PCI bus e Memory multi bit errors single bit errors are not logged e Sensors e Processor internal errors bus address errors thermal trip errors temperatures and voltages and GTL voltage levels e Errors detected during POST logged as POST errors Sensors are managed by the mBMC The mBMC is capable of receiving event messages from individual sensors and logging system events 6 3 1 SMI Handler The SMI handler handles and logs system level events that are not visible to the server management firmware If SEL error logging is disabled in the BIOS Setup utility no SMI signals are generated on system errors If error logging is enabled the SMI handler preprocesses all system errors even those that are normally considered to generate an NMI The SMI handler sends a command to the BMC to log the event and provides the data to be logged For example The BIOS programs the hardware to generate an SMI on a single bit memory error and logs the location of the failed DIMM in the system event log 6 3 2 PCI Bus Error The PCI bus defines two error pins PERR and SERR for reporting PCI parity errors and system errors respectively The BIOS can be instructed to enab
59. regions using registers The Intel E7520 chipset supports 64GB of host addressable memory space and 64KB 3 of host addressable I O space The Server Board SE7520JR2 supports only the main memory up to 24GB for DDR 266 or up to 16GB for DDR333 DDR2 400 64GB Upper Memory Ranges 4GB Lo PCI Memory Space Range Top of Low Memory TOLM Main Memory Address Range 16MB 15MB 1MB 640KB DOS Legacy Address Range 512KB 0 Figure 14 Intel Xeon Processor Memory Address Space 70 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture 3 5 1 1 DOS Compatibility Region The first region of memory below 1 MB was defined for early PCs and must be maintained for compatibility reasons The region is divided into sub regions as shown in the following figure OFFFFFh 1MB System BIOS 0FO0000h OEFFFFh 960KB Extended System BIOS 0E0000h ODFFFFh 896KB Add in Card BIOS and Buffer Area 0C0000h OBFFFFh 768KB 0A0000h O9FFFFh 640KB 080000h 512KB LI Shadowed in main memory 07FFFFh L Mappable to PCI or ISA memory DOS Area LI Main memory only 0 000000h PCI only Figure 15 DOS Compatibility Region Revision 1 0 71 C78844 002 Functional Architecture Intel Server Board SE7520JR2 3 5 1 1 1 DOS Area The DOS region is 512 KB in the address range 0 to O7FFFFh This region is fixed and all accesses go to main memory 3 5 1 1 2 ISA Window Memory The ISA Window Memory is 128 KB betwee
60. supports both CRT and LCD monitors up to 100 Hz vertical refresh rate Video is accessed using a standard 15 pin VGA connector found on the back edge of the server board Video signals are also made available through either of two control panel connectors allowing for an optional video connector to be present on the platform s control panel Video is routed to the rear video connector by default Circuitry on the baseboard disables the rear video connector when a monitor is plugged in to the control panel video connector Hot plugging the video while the system is still running is supported On board video can be disabled using the BIOS Setup Utility or when an add in video card is installed System BIOS also provides the option for dual video operation when an add in video card is configured in the system 3 4 7 1 Video Modes The Rage XL chip supports all standard IBM VGA modes The following table shows the 2D 3D modes supported for both CRT and LCD 62 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture Table 11 Video Modes 2D Mode Refresh Rate Hz 2D Video Mode Support 8 bpp 16 bpp 24 bpp 32 bpp 640x480 60 72 75 90 100 Supported Supported Supported Supported 800x600 60 70 75 90 100 Supported Supported Supported Supported 1024x768 60 72 75 90 100 Supported Supported Supported S
61. system Timer Error Indicates an error while programming the count register 160 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Error Reporting and Handling Message Displayed Description of channel 2 of the 8254 timer This may indicate a problem with system hardware Interrupt Controller 1 error BIOS POST could not initialize the Master Interrupt Controller This may indicate a problem with system hardware Interrupt Controller 2 error BIOS POST could not initialize the Slave Interrupt Controller This may indicate a problem with system hardware Table 64 CMOS BIOS Messages Message Displayed Description CMOS Date Time Not Set The CMOS Date and or Time are invalid This error can be resolved by readjusting the system time in AMIBIOS Setup CMOS Battery Low CMOS Battery is low This message usually indicates that the CMOS battery needs to be replaced It could also appear when the user intentionally discharges the CMOS battery CMOS Settings Wrong CMOS settings are invalid This error can be resolved by using AMIBIOS Setup CMOS Checksum Bad CMOS contents failed the Checksum check Indicates that the CMOS data has been changed by a program other than the BIOS or that the CMOS is not retaining its data due to malfunction This error can typically be resolved by using AMIBIOS Setup Table 65 Miscellaneou
62. system date and time to the BMC during POST and logs a boot event This record does not indicate an error and software that parses the event log should treat it as such 6 4 Error Messages and Error Codes The BIOS indicates the current testing phase during POST by writing a hex code to I O location 80h If errors are encountered error messages or codes will either be displayed to the video screen or if an error has occurred prior to video initialization errors will be reported through a series of audio beep codes 6 4 1 POST Error Messages Table 59 Memory BIOS Messages Message Displayed Description 156 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Error Reporting and Handling Gate20 Error The BIOS is unable to properly control the motherboard s Gate A20 function which controls access of memory over 1 MB This may indicate a problem with the motherboard Multi Bit ECC Error This message will only occur on systems using ECC enabled memory modules ECC memory has the ability to correct single bit errors that may occur from faulty memory modules A multiple bit corruption of memory has occurred and the ECC memory algorithm cannot correct it This may indicate a defective memory module Parity Error Fatal Memory Parity Error System halts after displaying this message Table 60 Boot BIOS Messages Message Displayed Description Boot Failure This is
63. that along with the bus number cause the assertion of IDSEL for a particular device during configuration cycles The following table shows the correspondence between IDSEL values and PCI device numbers for the PCI bus The lower five bits of the device number are used in CONFIG_ADDRESS bits 15 11 50 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture Table 8 PCI Configuration IDs and Device Numbers PCI Device IDSEL Bus Device Function MCH host HI bridge DRAM controller ie il 00 00 0 MCH DRAM Controller Error Reporting E il 00 00 1 MCH DMA controller pn 00 01 00 MCH EXP Bridge AO p 00 02 00 MCH EXP Bridge A1 00 03 00 MCH EXP Bridge BO En 00 04 00 MCH EXP Bridge B1 00 05 00 MCH EXP Bridge CO 00 06 00 MCH EXP Bridge C1 MCH Extended Configuration ICH5R Hub interface to PCI bridge ICH5R PCI to LPC interface HERE ICHSR IDE controller 00 31 01 ICH5R Serial ATA mm 00 31 02 00 07 00 00 08 00 00 30 00 00 31 00 LCHSRUSBUHCIGmmwerWi foor THER USB URCIeontoter forar mrss TCS LPC fom mresa m mweddw TT LSI53C1030 Ultra 320 SCSI w dual P1A_AD21 05 0 1 channel ATI Rage XL PCI VGA PC_AD28 12 0 Note Bus Numbers may change depending on the type of riser card used Revision 1 0 51 C78844 002 Functional Architecture Intel Server Board SE7520JR2 3 4 1 8 Resource Assignment Th
64. the BIOS is trying to detect and configure IDE ATAPI devices in POST 3 Slave Drive ATAPI Incompatible The IDE ATAPI device configured as Slave in the 3 IDE controller failed an ATAPI compatibility test This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST 4 Master Drive ATAPI Incompatible The IDE ATAPI device configured as Master in the go IDE controller failed an ATAPI compatibility test This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST 4 Slave Drive ATAPI Incompatible The IDE ATAPI device configured as Slave in the 4 IDE controller failed an ATAPI compatibility test This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST 5 Master Drive ATAPI Incompatible The IDE ATAPI device configured as Master in the 5m IDE controller failed an ATAPI compatibility test This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST 5 Slave Drive ATAPI Incompatible The IDE ATAPI device configured as Slave in the 5 IDE controller failed an ATAPI compatibility test This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST 6 Master Drive ATAPI Incompatible The IDE ATAPI device configured as Master in the e IDE controller fail
65. the system board the board may be faulty 6 4 4 Boot Block Error Beep Codes The following table defines beep codes that may occur if a failure occurs while performing a BIOS Boot Block Update Table 72 Boot Block Error Beep Codes Number of Beeps Description 1 Insert diskette in floppy drive A 2 AMIBOOT ROM file not found in root directory of diskette in A 3 Base Memory error 4 Flash Programming successful 5 Floppy read error 6 Keyboard controller BAT command failed 7 No Flash EPROM detected 8 Floppy controller failure 9 Boot Block BIOS checksum error 10 Flash Erase error 11 Flash Program error 12 AMIBOOT ROM file size error 13 BIOS ROM image mismatch file layout does not match image present in flash device 1 long beep Insert diskette with AMIBOOT 001 File for Multi Disk Recovery 6 4 5 BMC Generated Beep Codes Professional Advanced only The Sahalee BMC generates beep codes upon detection of the failure conditions listed in the following table Each digit in the code is represented by a sequence of beeps whose count is equal to the digit 166 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Error Reporting and Handling Table 73 BMC Beep Code Reason for Beep Front panel CMOS clear initiated 1 5 1 1 FRB failure processor failure 1 5 2 1 No processors installed or processor socket 1 is empty 1 5 2 3 Processor configuration error e g mi
66. the system to hang at POST generating a CMOS error Should the system exhibit POST hangs due to BIOS corruption you should Option 1 cycle power This option will perform 1 of 2 possible operations The reboot may clear possible BIOS corruption with the Primary BIOS image and the system will boot normally If the Primary BIOS image is non correctable the system will perform an Auto Recovery which loads the secondary or backup BIOS image If this option is not successful and your system continues to exhibit CMOS corruption errors you can attempt option 2 Option 2 e Obtain BIOS Update Package From the following Intel Web Site http support intel com support motherboards server se7520jr2 e Turn off the system e Verify the jumper on jumper block J1A4 is set to Pins 1 2 e Build Recovery Storage Media using files compressed in the RECOVERY ZIP file e Recovery from USB Disk on key or other large media o Prepare a formatted and bootable storage media device such as a USB DISK ON KEY o Copy AMIBOOT ROM to it 218 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Miscellaneous Board Information e Recovery from multiple floppy disks o O O Prepare 2 blank disks The first disk disk0 must be made bootable Copy amiboot 000 to disk0 and amiboot 001 to disk1 e Execute BIOS Recovery o O o set Recovery Boot Jumper by moving jumper J1H2 row B from Pins 1 2 to Pins 2 3 Insert the recovery media to th
67. to the BMC in use In addition using Professional or Advanced IMMs the BIOS communicates this failure to the Sahalee BMC so that it can be incorporated in the BMC s DIMM sensor state DIMM presence and failure states are stored persistently by the Sahalee BMC In all management levels the BIOS is responsible for DIMM FRU LED management and illuminates the LEDs associated with failed or disabled DIMMs Correctable memory errors are non critical errors that do not cause the system to fail They are detected by the BIOS and are logged as IPMI SEL events when either the Professional or Advanced IMMs are installed Logging is throttled by error frequency If more than a certain number of correctable errors occur in an hour logging is turned off Revision 1 0 41 C78844 002 Functional Architecture Intel Server Board SE7520JR2 Uncorrectable memory errors are critical errors that may cause the system to fail The BIOS normally detects and logs these errors as IPMI SEL events for all management levels except in the case described below It is possible that a critical hardware error uncorrectable memory or bus error may prevent the BIOS from running reporting the error and restarting the system In Professional and Advanced management models the Sahalee BMC monitors the SMI signal which if it stays asserted for a long period of time is an indication that BIOS cannot run In this case the Sahalee BMC logs an SMI Timeout event and probe
68. ttt ann DV ROME tad 62 3 4 6 2 Intel RAID Technology Option ROM seeem 62 3 4 7 MIO SUPPOM se iet ete Os re re ere PER PERS ERN RN ERE gr fe ae te ER 62 2 4 7 1 Video Modes anarki dida 62 3 4 7 2 Video Memory Interface Lavrans ee Rettar d 63 SAB Dual video ree fe tee eoa ed een t Pavese eee Ee de ede 64 3 4 8 Network Interface Controller NIC esee nnne 64 3 4 8 1 NIC Connector and Status LEDS cuina diete exacti iedue e hene 65 3 4 9 USB 2 0 SUppoOrtx ie RR its 65 3 4 10 Super VO Chi pice iore dert ete decd A deed Tea YET as 65 9 410 T OPIOS code Bde EU dsd 65 SES NAME E A AAT 67 3 4 10 3 Removable Media Driv6s tetris tn pa nio bread 69 3410 4 Floppy Disk Support riter tee i i ee Peer a 69 3 4 10 5 Keyboard and Mouse Support ccccccccecceeccececeeeceeeeeeeeeeeeceeeeeeseeeeeeeeeeeteeeess 69 3 4 10 6 Wake up Control cnoe a a ae ee nen nnn nen nennen a 69 Sam BOS TS CE 69 3 5 Configuration and InitializatiON ooonnnnnnnnnnnncnnnnnnnnnnnconnncccncnnnnnonnnnnnn nn 70 3 5 1 Menn PACO iia ri ca 70 3 9 14 DOS Compatibility REGION oir adi 71 3 5 1 2 Extended Memory cuina 73 3 5 1 3 Memory ShadOowilhg err rrr e 74 3 5 1 4 System Management Mode Handling cccccccnnnccconcncccccnnncncnoncnnnncnnnananannncccnnnnn 75 3 5 2 MOM ea cetera p NP EU 76 3 5 3 Accessing Configuration Space iii ti lid 78 3 5 3 1 GONFIG ADDRESS R gsten musa iria ie
69. 05 Internal 2x5 USB Connector J1G1 Pin Signalname USB PWR 5 USB PWR 4 USB BCK4 L USB BCK5 L USB BCK4 s uses s Ga S No Connect 7 6 Fan Headers The baseboard provides for several different system fan headers for use in Intel chassis as well as custom and third party reference chassis 198 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Connectors and Jumper Blocks There are two SSI compliant processor fan headers CPU1 J7F1 and CPU2 J5F2 which are not fan speed controlled They are powered by a constant 12V The pinout for these two connector is defined in the following table Table 106 CPU1 CPU2 Fan Connector Pin out J5F2 J7F1 Pin Signal Name FAN_TACH signal is connected to the BMC to monitor the FAN speed GND GROUND is the power supply ground The fan headers at J3K3 and J3K6 have fan speed control Fan control is performed by two pulse width modulator PWM outputs on the LM93 The mBMC initializes the LM93 to control fan speeds based on temperature measurements according to a built in table The table itself is loaded as part of the SDR package according to which system configuration is used The 2x12 fan header J3K6 is used to control system fans in both the Intel Server Chassis SR1400 and SR2400 The pinout for this connector is found in the following table Table 107 Intel Server Chassis Fan Header Pin out J3K6 Pin SignalName Typ Description
70. 1 1 The Low Pin Count LPC bridge function of the ICH5 R resides in PCI Device 31 Function 0 In addition to the LPC bridge interface function D31 FO contains other functional units including DMA interrupt controllers timers power management system management GPIO and RTC 3 2 3 5 Compatibility Modules DMA Controller Timer Counters Interrupt Controller The DMA controller incorporates the logic of two 82C37 DMA controllers with seven independently programmable channels Channels 0 3 are hardwired to 8 bit count by byte transfers and channels 5 7 are hardwired to 16 bit count by word transfers Any two of the seven DMA channels can be programmed to support fast Type F transfers The ICH5 R supports two types of DMA LPC and PC PCI LPC DMA and PC PCI DMA use the ICH5 R s DMA controller The PC PCI protocol allows PCl based peripherals to initiate DMA cycles by encoding requests and grants via two PC PC REQZ GNT pairs LPC DMA is handled through the use of the LDRQ lines from peripherals and special encoding on LAD 3 0 from the host Single Demand Verify and Increment modes are supported on the LPC interface Channels 0 3 are 8 bit channels Channels 5 7 are 16 bit channels Channel 4 is reserved as a generic bus master request The timer counter block contains three counters that are equivalent in function to those found in one 82C54 programmable interval timer These three counters are combined to provide the system timer
71. 15 82546GB 1 P64A IRQ6 82546GB 2 P64A IRQ7 SCSI Controller 1 P64B IRQ2 SCSI Controller 2 P64B IRQ1 FL Riser TOK amp TCO P64A IRQO P64A IRQ3 P64A IRQ5 P64A IRQ4 3 4 3 2 APIC Interrupt Routing For APIC mode the Server Board SE7520JR2 interrupt architecture incorporates three Intel I O APIC devices to manage and broadcast interrupts to local APICs in each processor The Intel I O APICs monitor each interrupt on each PCI device including PCI slots in addition to the ISA compatibility interrupts IRQ 0 15 When an interrupt occurs a message corresponding to the interrupt is sent across a three wire serial interface to the local APICs The APIC bus minimizes interrupt latency time for compatibility interrupt sources The I O APICs can also supply greater than 16 interrupt levels to the processor s This APIC bus consists of an APIC clock and two bidirectional data lines Revision 1 0 53 C78844 002 Functional Architecture Intel Server Board SE7520JR2 3 4 3 3 Legacy Interrupt Sources The table below recommends the logical interrupt mapping of interrupt sources on the Server Board SE7520JR2 The actual interrupt map is defined using configuration registers in the ICH5 R Table 10 Interrupt Definitions Interrupt ROO Tmericounter HPET 0 in legacy replacement Mode In APIC mode cascade fom 8259 controller iT ROS CN RG ROS Ra Genere oons O O ROT RO ROS PIRA e E AN PRAD PIRQE Option for SCI TCO HPE
72. 18 AWG Color Black Green Black Table 114 P2 Processor Power Connector Pin Signal 18 AWG Color Pin Signal 18 AWG Color Y com Bax J Tei vew 2 cow Bak s rui viw CON Bak r Hava Yelow Srp ER i cow Bax 8 ve velowBlack Stine C78844 002 Revision 1 0 Intel Server Board SE7520JR2 P3 Power Signal Connector e Connector housing 5 pin Molex 50 57 9705 or equivalent e Contacts Molex 16 02 0087 or equivalent Table 115 P3 Baseboard Signal Connector P4 Peripheral Connectors e Connector housing AMP 24AWGColor AWG Color Clock White Green Stripe I2C Data White Yellow Stripe Aen 3 3RS White Brown Stripe VO P N is 770827 1 or equivalent e Contact Amp 61314 1 contact or equivalent Table 116 Peripheral Power Connectors P7 Hard Drive Back Plane P e Connector housing 6 pin Molex Mini Fit Jr PN 39 01 2065 or equivalent e Contact Molex Mini Fit HCS female crimp 44476 or equivalent Table 117 P7 Hard Drive Power Connector 8 2 2 Grounding The ground of the pins of the power supply output connector provides the power return path The output connector ground pins shall be connected to safety ground power supply Revision 1 0 Pin Signal 18 AWG Color Ho reve vetewBue Stipe z fom Bak a ewe ms ower Connector Pin Signal 18AWGColor Ground Ha 7 2 Ground fee 5V 3
73. 2 Connectors and Jumper Blocks Pin FMM_RI_BUF_N Ring Indicator from the EMP serial port on the baseboard RST_PWRGD_PS 101 Power good signal from power subsystem In typical system this signal is connected to PWR_OK signal on power supply This signal is monitored by the FMM to detect a Power Supply failure LAN_SMBALERT_N Alert signal from the motherboard NIC LOM ICH SLP S4 N Power Off request from the Chipset ICH SMI BUFF N SMI signal from Chipset This signal is monitored by the FMM to detect an SMI Time out condition If this signal is asserted for longer than a predefined SMI Time out timer an event is logged and the FMM interrogates the chipset for further data such as fatal errors CHPSET ERR ALERT N 106 When available from chipset indicates that a error occurred and FMM will need interrogate Chipset for further data such as fatal errors If not available leave as NC FP RST BTN N 109 Front panel Reset Button input ICH RST BTN N 110 Passthrough of front panel Reset button to the chipset FMM chassis control command will also use this FP PWR BTN N Front panel power button input FMM IRQ SMI N FMM might use this signal to generate an SMI to the system FMM PRES N 120 When FMM is present this signal is asserted This signal can be used to notify BIOS that a module is present via routing to GPIO as well as to control any logic which behaves differently when FMM is present such as the FML mux if supported etc
74. 2 Programming FRU and SDR Data Regardless of which platform management option is being used On board Platform Instrumentation or Intel Management Module the baseboard must have the proper Sensor Data Records SDR and Field Replaceable Unit FRU data programmed to the board The FRUSDR Update Utility is an application used to program the platform management sub system to monitor the proper platform sensors This application is provided on the Intel Server Deployment Toolkit CDROM that comes with the baseboard or can be downloaded from the following Intel Website http support intel com support motherboards server se7520jr2 The FRUSDR Update Utility should be run prior to loading any OS or Server Management Software The FRUSDR Update Utility determines which chassis the baseboard is integrated into which FRUs are present and programs the Platform Management Sub system to monitor the proper platform sensors accordingly The FRUSDR Update Utility must be run when the board is first integrated into a platform and must be run when the system configuration is changed as follows e Adding Removing an IMM 216 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Miscellaneous Board Information e Replacing a bad baseboard e Adding Removing a Redundancy Feature IMM Systems Only o Redundant Power Supplies o Redundant Fans e Adding Removing a CPU fan IMM Systems Only Failure to run the FRUSDR Update Utility may cause the platfor
75. 3 3V or 1 5V 181 Connectors and Jumper Blocks Intel Server Board SE7520JR2 Pin Side PCI Spec Description Pin Side PCI Spec Description B Signal A Signal 77 3 3V Was Vio 3 3V or 1 5V 77 GNT1 Lowest PCI slot SLOT1 76 PME2 active riser only PME needed 76 Ground per PCI segment reserved for passive riser 39 AD 03 39 Ground 75 AD 31 75 PME1 for passive slots on both passive and active riser 74 AD 29 74 PME3 active riser only PME needed per PCI segment reserved for passive riser 73 73 ADI30 AD 31 m un 72 71 AD 25 71 AD 28 70 70 AD 26 69 C BE 3 69 68 ADI23 68 AD 24 67 67 RSVRD Reserved s ADU 66 65 AD 19 65 AD 22 64 64 AD 20 63 ADIT 63 62 C BE 2 t 62 AD 18 61 61 AD 16 60 IRDY 60 59 59 FRAME 58 DEVSEL 58 57 PCI XCAP 57 TRDY 56 LOCK 56 55 PERR 55 STOP 53 SERR 53 SMBD Daisy chain to all slots 52 52 SMBCLK Daisy chain to all slots 51 C BE 1 51 50 AD 14 50 PAR 49 49 AD 15 aora E 47 AD 10 47 AD 13 46 M66EN 46 AD 11 oe 43 AD 08 43 C BE O a ADT 2 41 41 AD 06 40 AD 05 40 AD 04 182 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Connectors and Jumper Blocks Pin Side PCI Spec Description Pin Side PCI Spec Description B Signal A Signal 38 38 AD 02 37 AD 01 37 AD 00 36 Was Vio 3 3V or 1 5V 36 Was Vio 3 3V or 1 5V 35 ACK64 35 REQ64 34 5V 34 5V 33 5V 33 5V 32 32 5
76. 3 Control Panel System Reset 127 5 3 5 4 Control Panel Indicators 128 5 3 5 5 Control Panel ImputS ocococcncncnoccnoncnonenononinoninnnnnonnnnnnnonononnnnnnnnnnnnnnnonineninnnnss 129 5 3 6 Secure Mode Operation rnnnnnnnnnnn nn nn nnn tnne tantra rtnn rrnnnnnnnn eee 131 5 3 7 Baseboard Fan Control sse mener 131 5 3 8 mBMC Peripheral SMBUs rnnnnnnnnnnnnnnnnnnnnn nn nnnnrnnn nn nn nnnnnn nn nn nn rnn nn rn 131 5 3 9 Watchdog Timer vicio it 131 5 3 10 System Event Log SEL isis 131 5 39 10 T SEL Erasure ic oia 132 5 3 10 2 Timestamp ClOCK ii A e re PET denn 132 5 3 11 Sensor Data Record SDR Repository sssssssssssssssse 132 S TET iIpitiatizationi AGE e a cuantos i ones oct ette Ta a stata sene 132 5 3 12 Field Replaceable Unit FRU Inventory Devices rrnnrrnnrrnnrrnnrrnnrrnnrrnnnnnnnnnnn 133 5 3 12 1 mBMC FRU Inventory Area Format ccccccccceeccceeeeeeeeseeeeneeeeeteeeeeseeneeneee 133 5 3 13 RES 133 5 3 14 SME Generations ii ee eh ere bee e e e A te t b a ERR 133 5 3 15 Event Message Reception ec eraat eed cn ara kai 133 5 3 16 mBMC Self Test enne ene en een nem nnnm en eren nennen nnne 134 9 94 Messaging drntertaces cia io eei gef 134 5 3 17 1 Channel Management ccccccccccecccecccececeeeeeeeeeeeeeeeeeeeeeeeeeeeceeeseeeeseeseneenaas 134 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Table of Contents IA A TP 134
77. 71 Troubleshooting BIOS Beep Codes sss 166 Table 72 Boot Block Error Beep Codes seem 166 Table 73 BMC Beep Code sse eene enne nennen nnne nennen nennen nennen nnns 167 Table 74 POST Progress Code LED Example sss 167 Table 75 POST Code Checkpoints asrnnnnnnnrnnnrnnnrnnnnnnnnnnnennnnnnnnnnnsnnnrnnnsnnnsennsennsenneennsennsenne 168 Table 76 Bootblock Initialization Code Checkpoints esse 170 Table 77 Bootblock Recovery Code Checkpoint eeeeeeeneeneee 171 Table 78 DIM Code Checkpoint esses nemen eem mene 172 Table 79 ACPI Runtime Checkpoints sse 173 Table 80 Memory Error COdGS ius A al 173 Table 81 Power Connector Pin out sess emen erem 175 Table 82 12V Power Connector 1 oria s Caste ad 175 Table 83 Power Supply Signal Connector J1G1 rrrnrnrnnnnnnnvrrrnnnnnnnnannnnrrrrnnnnnnnnrrrrrnnvnnnnnn 176 Table 84 IDE Power Connector Pinout U2E1 esseeee 176 Table 85 Low Profile Riser Slot Pinout srrnnrnnnrrnnnnnnnrnnnrnnnrnnnrnnnnnnnnnnnsnnnsnnnsnnnsnnnennnsnnnsennr 176 Table 86 Full height Riser Slot Pinout eese eene nenntnnnnn nn tnmen 180 Table 87 IMM Connector Pinout 4 TG 1 stent 184 Table 88 ICMB Header Pinout ID usina m ee Poenos Edo She teet Dre itus 187 Table 89 IPMB Conne
78. B and it is not remapped Table 15 SMM Space Table Global Enable High Enable TSEG Enable Compatible High H TSEG T G SMRAME H SMRAME TSEG EN C Range Range Range o x X see Disable Disebie pp 8 Emi pane Diae FG Jo p fee e Ene Revision 1 0 75 C78844 002 Functional Architecture 3 5 2 Intel Server Board SE7520JR2 I O Map The baseboard I O addresses are mapped to the processor bus or through designated bridges in a multi bridge system Other PCI devices including the ICH5 R have built in features that support PC compatible I O devices and functions which are mapped to specific addresses in I O space On SE7520JR2 the ICH5 R provides the bridge to ISA functions The I O map in the following table shows the location in I O space of all direct I O accessible registers PCI configuration space registers for each device control mapping in I O and memory spaces and other features that may affect the global I O map Table 16 I O Map DMA Controller 1 Address es Resource Notes k 0000h 000Fh 0010h 001Fh DMA Controller 2 Aliased from 0000h 000Fh 0020h 0021h Interrupt Controller 1 AAA Interrupt Controller 1 Aliased from 0020 0021h Interrupt Controller 1 Aliased from 0020h 0021h Interrupt Controller 1 Super I O SIO index and Data ports AAN Interrupt Controller 1 Aliased from 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027
79. Board SE7520JR2 provides two RJ45 NIC connectors oriented side by side on the back edge of the board The pin out for each connector is identical and is defined in the following table Table 95 RJ 45 10 100 1000 NIC Connector Pin out Pin Signal Name fe s mmn 3 LAN_MID1P 5 LAN_MID2P 5 UNMDN anm LAN MID3N P2V5 NIC 7 5 3 SCSI Connectors The Server Board SE7520JR2 provides two SCSI connectors one for each channel of the embedded LSI53C1030 SCSI controller The external connector is routed to SCSI channel B is a high density connector and is found on the back edge of the server board The internal connector is routed to SCSI channel A is a standard 68 pin connector and is located in the cut out on the edge of the server board The pin out for each connector is identical and is defined in the following table Table 96 Internal External 68 pin VHDCI SCSI Connector Pin out Pin Signal Name Signal Name Pin 080 ES C Revision 1 0 193 C78844 002 Connectors and Jumper Blocks Signal Name DB 13 DB 14 DB 15 DB P1 ATN GROUND BSY ACK RST MSG SEL C D REQ 1 O DB 8 DB 9 DB 10 DB 11 Signal Name DB 13 DB 14 DB 15 DB P DB 0 DB 1 DB 2 DB 4 DB 5 DB 6 DB 7 DB P 1 DB 3 ROR GROUND 5 RESERVED 5 RESERVED 5 RESERVED 5 GROUND 5 ATN GROUND BSY ACK RS
80. CC N 82 Indicates that a Processor is in the primary processor socket If this socket is detected empty and there s an attempt to power up the system the FMM will output an Error Beep Code and prevent the System from turning on FMM SOUT 85 EMP SOL Serial Data Out This is the Serial Port data output from FMM and should be connected to the SIN signal in the SIO3 device FMM SIN EMP SOL Serial Data In This is the Serial Port data input into the FMM and should be connected to the SOUT signal in the SIO3 device FMM DCD N 87 EMP SOL Data Carrier Detect This is the Serial Port Data Carrier Detect input into the FMM and should be connected to the DCD signal in the SIO3 device FMM RTS N 88 EMP SOL Request to Send This is the Serial Port Request to Send output from FMM and should be connected to the CTS Clear to Send signal in the SIO3 device FMM DTR N EMP SOL Data Terminal Ready This is the Serial Port Data Terminal Ready output from FMM and should be connected to the DSR Data Set Ready signal in the SIO3 device FMM CTS N EMP SOL Clear to Send This is the Serial Port Clear to Send input into the FMM and should be connected to the RTS Ready to Send signal in the SIO device ICMB RX Inter Chassis Communication Management Bus receive data ICMB TX Inter Chassis Communication Management Bus transmit data ICMB TX EN 96 Inter Chassis Communication Management Bus transceiver enable 186 Revision 1 0 C78844 002 Intel Server Board SE7520JR
81. Conformity seen 215 8 4 4 Taiwan Declaration of Conformity BSMI sseee 215 8 4 5 Korean Compliance REL ode ee dera to Meere teer tes pecus Lori eR pox Ea ae 215 9 Miscellaneous Board Information vvvrrrnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnnnnne 216 9 1 Updating the System SOftWeLFe eiui eain a vde 216 9 2 Programming FRU and SDR Data de editieren tre pre dnsseane 216 9 3 Cleaning EMO is a r ee 217 9 3 1 CMOS Clear Using J1H2 Jumper Block seeeem 217 9 3 2 CMOS Clear using Control Panel ceccceccceeeeeeeeeeseeeeeeeeeeeeeenesssseeeeneneetenes 217 9 4 BIOS Recovery Operator da a aed AE aE 218 Revision 1 0 xi C78844 002 Table of Contents Intel Server Board SE7520JR2 Appendix A Integration and Usage Tips seen 221 EIL ANY Pme A es 222 Reference Documents tiet ente anaa amata ncsvesnsvescootevertewerssiecesiewstessrecsesuseceatevanteseweses 225 xii Revision 1 0 C78844 002 Intel Server Board SE7520JR2 List of Figures List of Figures Figure 1 SE7520JR2 Board Layout tacita ltda enn 23 Figure 2 Server Board Dimensions eccooconsniioocoronerns strain 25 Figure 3 Server Board SE7520JR2 Block DiagraM ooccooocccoccccccccconcnonannncnnnnnnnnnnnnnnnnonnnnnnncnnnnnns 26 Figure 4 CEK Processor Mounting dais A des dede duce ded ert ete Penne e deut 28 Figu
82. Corporation Intelligent Platform Management Interface Specification Version 2 0 Intel Corporation Hewlett Packard Company NEC Corporation Dell Computer Corporation Platform Management FRU Information Storage Definition 1998 Intel Corporation Hewlett Packard Company NEC Corporation Dell Computer Corporation http developer intel com design servers ipmi spec htm The I C Bus and How to Use It January 1992 Phillips Semiconductors e Power Supply Management Interface PSMI Revision 1 4 2003 Intel Corporation Revision 1 0 225 C78844 002
83. E NIR ES 3 CPU2 FI PXH IOAPIC 2 s gt 3 RS ES ES Figure 8 Interrupt Routing Diagram ICH5 R Internal Revision 1 0 55 C78844 002 Functional Architecture 56 Super I O Timer Keyboard Cascade Serial Serial gt ISA gt Floppy lS gt SA gt RTC gt SCI ISA gt ISA ISA Mouse IS _ gt Coprocessor P IDE IS gt Not Used gt and SATA USB 1 1 Controller 2 Option for SCI TCO HPET O 1 2 Option for SCI TCO HPET O 1 2 Option for SCI TCO HPET O 1 2 USB 2 0 EHCI Controller 1 Option for SCI TCO HPET 0 1 2 USB 1 1 Controller 1 and 4 Video USB 1 1 Controller 43 Native IDE eoeyieju OHI pezijeues Intel amp Server Board SE7520JR2 Bunnog 1dnuueju Y GHO Figure 9 Interrupt Routing Diagram C78844 002 Revision 1 0 Intel Server Board SE7520JR2 Functional Architecture Zero Channel RAD Slot for FH 3 PCI X LP PCI X Riser Bus B X IDSEL 4D23 24 25 IDSEL ADAT 18 19 RECUGNT pair 41 23 RE QIGNT pair 1 23 Ud Figure 10 PCI Interrupt Mapping Diagram Top sict3 Active 2U FL Riser Middle Slot 2 Zero Channel RAID Slot Bus A and B IDSEL 4D17 REQ GNT pair 0 APTEX Riser Bus A IDSEL 4D17 18 19 RE Q GNT pair 1 23 TDI 7 MROMB PRESENT N Figure 11 PCI Interrupt Mapping Diagram for 2U Active Riser
84. E pe ee deri ua 104 4 6 OEM Binay oio itat iii fi ds tese eia Dd tosca 105 4 7 refe 105 4 7 1 Operating Model mis terr rre eere e ci 106 4 7 2 Password Clear Jumper srannnnnnrnnnrnnnrnnnnnnnnnnnnnnnsnnnsnnnnnnnsnnnsennsennsennsennsennsennsenne 108 4 8 Extensible Firmware Interface EFI ccce 108 4 8 1 A temet desc LACER MAC cet oai d 108 4 9 Operating System Boot Sleep and Wake rrrnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnrnnnnnnnnnr 108 4 9 1 Microsoft Windows Compatibility ssssssseseennn no 108 4 9 2 Advanced Configuration and Power Interface ACPI rrrrrnnnnnnnnnnnnnrrrrnnnnnnnnnnnn 109 4921 Sleep and Wake Functional veas rd 109 4 9 22 Power Switch Off tO Ocotal ii cid neueste es gud 110 49 23 Ono Off OS absent o ctos tete eerte one aene enda dur tp ego Loue 110 4924 CONTO OI OS present oot eet o oe 110 49 25 Onto Sleep AGPI iiio n xb hebt ute ea De aae bic ki uet peret x aeba dels 110 492 5 Sleep tO On AO P aske us eto See ee snp bte e S RAN EAD 111 49 27 System Sleep SEES cordc ctae uii ate ipai etu ues teta tta bs ai 111 4 10 EXE BIOS SiO Lus ett eee 112 4 11 Console Redire cuoc n xcii ea eec i room tu n a ee es 112 5 Platform Manage Medi A Dx VR Ga FER ERR VA A RR ERN BRE ER VY XR 113 Revision 1 0 vii C78844 002 Table of Contents Intel Server Board SE7520JR2 5 1 Platform Management Architecture Overview
85. Event Offset Assert Readable Sensor Name Sensor Type Reading E Value EventData Number Triggers Deassert Type Offsets os OEM System Boot Event Hard System Event asn YstemEvent Specific Recan Trig Offset 6Fh PEF Action Sensor Power Button Button 84h Specific Sleep Button Trig Offset 6Fh Reset Button Digital State Asserted SMI Timeout 85h SD Tusen Discrete Trig Offset FSh 03h State Deasserted 12C device not OEM found sen SensorFailure Sensor e device error Trig Offset F6h Specific detected 73h 12C Bus Timeout Digital State A ted 87h OEM Discrete dC HE COh State Deasserted 03h OEM Digital State Asserted SMI Signal State 88h Discrete COh 03h State Deasserted Oh Sensor Failure NMI Signal State DIMM Sparing Redundancy DIMM Sparing Enabled Entity Presence Sensor y Specific Entity Present Trig Offset 25h 6Fh Fully Redundant Non red Suff res Availability Status Discrete from redund Trig Offset OBh OBh Non red Suff res 9 from insuff res Non red Insuff res Entity Presence Sensor y Specific Entity Present Trig Offset 25h GFh IERR Thermal Trip 4 B Sensor FRB1 FRB2 rocessor 9 rocessor Specific FRB3 Trig Offset Status 07h 6Fh Config Error Presence Disabled 146 Revision 1 0 C78844 002 Memory Mirroring Redundancy Memory Mirroring Enabled Fully Redundant Non red Suff res Availability Status Discrete from redund Trig Offset A OBh OBh Non red Suff res 19 fro
86. FF OFF Initializes the interrupt controlling hardware generally PIC and interrupt vector table Do R W test to CH 2 count reg Initialize CH 0 as system timer Install the POSTINT1Ch handler Enable IRQ 0 in PIC for system timer OFF G G OFF interrupt Traps INT1Ch vector to POSTINT1ChHandlerBlock Initializes the CPU The BAT test is being done on KBC Program the OFF OFF keyboard controller command byte is being done after Auto detection of KB MS using AMI KB 5 co R R OFF OFF Early CPU Init Start Disable Cache Init Local APIC IRA Ao Set up boot strap processor Information DEE R A oF G Enumerate and set up application processors 168 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Error Reporting and Handling Kerr LED Decoder Description Checkpoint G Green R Red A Amber Green R Red A Amber russ te ce R A G OFF Re enable cache for boot strap processor Initializes the 8042 compatible Key Board Controller EN ME Detects the presence of PS 2 mouse joc qe G OFF ORF Detects the presence of Keyboard in KBC port Testing and initialization of different Input Devices Also update the Kernel Variables Traps the INTO9h vector so that the POST INTO9h handler gets control for IRQ1 Uncompress all available language BIOS logo and Silent logo modules 13 POR OE G A Early POST initialization of chipset registers AA Uncompress and initialize any platform specific
87. I Bus Segment see 48 34 4 O desee bete emat t edes ide ee E 48 ado PGI Gel Ordena E 49 3 4 1 6 PCI Bus Nuthbering e teet vor A lA AAA 49 3 4 1 7 Device Number and IDSEL Mapping cccccccccicocinnninenineninonineninnninininnnininininininns 50 3 41 8 Resource Assignment esconde 52 3 4 1 9 Automatic IRQ Assignment eeeeeeeeceeeeee nene eerie intente 52 3 4 1 10 Option ROM Support ssssssssm Rennes 52 SATT NS fed 52 3 4 2 Split Opio ROM vass Pints Sites ast drakk am tet AE a itudites usminkede 52 Revision 1 0 v C78844 002 Table of Contents Intel Server Board SE7520JR2 3 4 3 Meru R UING si te nente oett oe evaded tet tiges eee nee pda en APR see 52 JA Legacy Interrupt ROUN sirean nerian ese at t ocio aea EAN 52 3432 APIC Interr pt ROUEN itd e Pete ii ad 53 3 4 3 3 Legacy Interrupt Sources go emeret a e a ds 54 3 4 8 4 Serialized IRQ Support oocccccccinicicicicinennnnnnnennnnnnnnnnnnonononnnnnnnnnnnnnnnnnnnnnnnnnnnininins 54 3 4 3 5 IRQ Scan for POUR ainia did 55 3 4 4 SCSI SUP POM ss 7 ntiistae ia eter sd 58 3 4 4 1 LSI 53C1030 Dual Channel Ultra320 SCSI Controller 58 3 4 4 2 Zero Channel RAID risie e eia ia e ii i E 60 3 4 5 IDE Support a Oh A devil A EE E A 60 5 UAA TA OO aS 61 3 4 5 2 IDE a ai PA LO IAE Eaa EE TE E E 61 3 4 6 SATA SUDDOE sitit tht et th a ti beri ct ub af eee A ede 61 3 4 0 1 POA RAID iii iri SA M ao
88. IMMS that utilize x4 devices Bits from x4 parts are presented in an interleaved fashion such that each bit from a particular part is represented in a different ECC word DIMMs that use x8 devices can use the same algorithm but will not have x4 SDDC protection since at most only four bits can be corrected with this method The algorithm does provide enhanced protection for the x8 parts over a standard SEC DED implementation With two memory channels either ECC method can be utilized with equal performance although single channel mode only supports standard SEC DED When memory mirroring is enabled x4 SDDC ECC is supported in single channel mode when the second channel has been disabled during a fail down phase The x4 SDDC ECC is not supported during single channel operation outside of DIMM mirroring fail down as it does have significant performance impacts in that environment 3 3 6 2 Integrated Memory Scrub Engine The Intel E7520 MCH includes an integrated engine to walk the populated memory space proactively seeking out soft errors in the memory subsystem In the case of a single bit correctable error this hardware detects logs and corrects the data except when an incoming write to the same memory address is detected For any uncorrectable errors detected the scrub 42 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture engine logs the failure Both types of errors may be reported via multiple alternate mec
89. Intel Server Board SE7520JR2 Technical Product Specification Revision 1 0 a i ntel October 2004 Enterprise Platforms and Services Marketing Revision History Intel Server Board SE7520JR2 Revision History Revision Modifications Number December 2003 Preliminary Release June 2004 Memory Sub system rewrite BIOS Chapter Updated Management Chapter re write Error Handling chapter re write several changes made to better reflect final design October 2004 First non NDA release Updated IRQ routing diagrams Updated mBMC Sensor tables Updates to Regulatory Information Updated Sensor data tables ii Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Disclaimers Disclaimers Information in this document is provided in connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including liability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptio
90. J1H4 CMOS Clear Jumper 10 Stacked PS 2 Keyboard and Mouse Ports 31 Legacy ATA 100 connector 11 Intel Management Module Connector 32 50 pin Control Panel Header 12 CMOS Battery 33 100 pin Control Panel Floppy IDE Connector 13 Full Height Riser Card Slot 34 Legacy Floppy Connector 14 Low Profile Riser Card Slot 35 SSI 34 pin Control Panel Header 15 DIMM Slots 36 8 Pin AUX Power Connector 16 68 pin SCSI Channel A Connector 37 24 Pin Main Power Connector 17 LSI 53C1030 SCSI Controller 38 SSI System Fan Header 18 MCH Chipset Component 39 SR1400 SR2400 System Fan Header 19 1x10 USB Header 40 Processor Voltage Regulator Circuitry 20 2x5 USB Header 21 ATI RageXL Video Controller 24 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Server Board Overview The following mechanical drawing shows the physical dimensions of the baseboard Li E E 7 040 DH dz ra t a050 084 Et h LU PIT Eric Eric et p AA a Bm Figure 2 Server Board Dimensions Revision 1 0 25 C78844 002 Functional Architecture Intel Server Board SE7520JR2 3 Functional Architecture This chapter provides a high level description of the functionality associated with the architectural blocks that make up the Intel Server Board SE7520JR2 Note This document describes the features and functionality of the Server Board SE7520JR2 when using standard on board platform instrumentation Some functionality and feature descriptions c
91. MM give the capability of having software issue a reset system configuration request Software can send a specific OEM command to the Sahalee BMC to indicate the request 104 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 System BIOS 4 6 OEM Binary System customers can supply 16 KB of code and data for use during POST and at run time Individual platforms may support a larger user binary User binary code is executed at several defined hook points during POST The user binary code is stored in the system flash If no run time code is added the BIOS temporarily allocates a code If run time code is present the BIOS shadows the entire block as though it were an option ROM The BIOS leaves this region writeable to allow the user binary to update any data structures it defines System software can locate a run time user binary by searching for it like an option ROM The system vendor can place a signature within the user binary to distinguish it from other option ROMs Refer to the SE7520JR2 BIOS EPS for further details 4 7 Security The BIOS provides a number of security features This section describes the security features and operating model The BIOS uses passwords to prevent unauthorized tampering with the system Once secure mode is entered access to the system is allowed only after the correct password s has been entered Both user and administrator passwords are supported by the BIOS To set a user password an adminis
92. Multi Sector Disabled Disabled The Data transfer from The Auto setting should work in Transfer Mode Auto and to the device occurs one sector most cases at a time Auto The data transfer from and to the device occurs multiple sectors at a time if the device supports it PIO Mode Auto Select PIO Mode The Auto setting should work in 0 most cases 1 2 3 4 Select DMA Mode The Auto setting should work in SWDMAO 0 Auto Auto detected most cases SWDMA SinglewordDMAn SWDMAO 1 MWDMA MultiwordDMAn SWDMAO 2 UWDMA UltraDMAn MWDMAO 0 MWDMAO 1 MWDMAO 2 UWDMAO 0 UWDMAO 1 UWDMAO 2 UWDMAO 3 UWDMAO 4 UWDMAO0 5 Auto Self Monitoring Analysis and The Auto setting should work in Disabled Reporting Technology most cases Enabled 32Bit Data Transfer Disabled Enable Disable 32 bit Data Transfer Enabled 90 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 System BIOS 4 4 2 2 3 Floppy Configuration Sub menu Table 25 BIOS Setup Floppy Configuration Sub menu Selections Feature Options Help Tex Floppy Configuration Floppy A Disabled Select the type of floppy drive Note Intel no longer 720 KB 3 1 2 connected to the system validates 720Kb amp 4 44 MB 3 1 2 2 88Mb drives 2 88 MB 3 1 2 Onboard Floppy Controller Disabled Allows BIOS to Enable or Enabled Disable Floppy Controller 4 4 2 2 4 Super I O Configuration Sub menu Table 26 BIOS Setup Super I O Configuration Sub menu Feature Optio
93. OS recovery can be accomplished from one of the following devices a standard 1 44 or 2 88 MB floppy drive an USB Disk On Key an ATAPI CD ROM DVD an ATAPI ZIP drive or a LS 120 LS 240 removable drive The recovery media must include the BIOS image file AMIBOOT ROM The recovery mode procedure is as follows 1 Insert or plug in the recovery media with the AMIBOOT ROM file 2 Power on the system When progress code E9 is displayed on port 80h the system will detect the recovery media if there is no image file present the system will cycle through progress code F1 to EF 3 When F3 is displayed on port 80h the system will read the BIOS image file Note Three different hot keys can be invoked e Ctri Home Recovery with CMOS destroyed and NVRAM preserved e lt CtrltPageDown gt Recovery with both CMOS and NVRAM preserved e lt CtrltPageUp gt Recovery with both CMOS and NVRAM destroyed 4 5 2 Configuration Reset Setting the Clear CMOS jumper board location J1H2 jumper Row C produces a reset system configuration request When a request is detected the BIOS loads the default system configuration values during the next POST In systems configured with an Intel Management Module the CMOS can be cleared without opening the chassis Using the control panel the user can hold the reset button for 4 seconds and then press the power button while still pressing the reset button In addition I
94. On board Platform Instrumentation architecture and details of it features and functionality including BIOS interactions and support Refer to the Technical Product Specification for the Professional and Advanced modules for detailed description of their features and functionality Note The generic term BMC may be used throughout this section when a feature and or function being described is common to both the mBMC and the Sahalee BMC If a described feature or function is unique the specific management controller will be referenced 114 C78844 002 Revision 1 0 Intel Server Board SE7520JR2 Platform Management 5 1 Platform Management Architecture Overview CPU CFG ERR N Sg FPIDBINN GLEN p CPU SEL gt D FP_RST_BTN CPU2 SEL e i cum ES FP PAR BIN I ee M4 o FP NM BIN in 5 9 FP ID LED N ICH RST ETN p _ S 3 PAR 2 FP_SYS FLT LED A JOH PAR BIN A ASA 9 FP SYS FLT LED C PP PSS ATIC 9 SYS NM SECURE MODE KB i eee A SYS SM FREG TMR HALT N AA Seren PS PAR GD Figure 19 On Board Platform Management Architecture Revision 1 0 115 C78844 002 Platform Management Intel Server Board SE7520JR2 5 1 1 5V Standby The power supply must provide a 5V Standby power source for the platform to provide any management functionality 5V Standby is a low power 5V supply that is active whenever the system is plugged into AC power
95. PCI X 66 100MHz PCI X cards o Riser Slot 2 Using Intel adaptive slot technology and different riser cards this slot is capable of supporting full height PCI X 66 100 133 or PCI Express cards e Six DIMM slots supporting DDR2 400MHz DIMMs or DDR 266 333 MHz DIMMs e Dual channel LSI 53C1030 Ultra320 SCSI Controller with integrated RAID 0 1 support SCSI SKU only e Dual Intel 82546GB 10 100 1000 Network Interface Controllers NICs e Onboard ATI Rage XL video controller with 8MB SDRAM e On board platform instrumentation using a National PC87431M mini BMC e External lO connectors o Stacked PS2 ports for keyboard and mouse 1 The use of DDR2 400 MHz or DDR 266 333 MHz DIMMs is dependant on which board SKU is used DDR 2 DIMMs cannot be used on a board designed to support DDR DDR DIMMs cannot be used on boards designed to support DDR 2 Revision 1 0 21 C78844 002 Server Board Overview Intel Server Board SE7520JR2 Oo 0 0 O O RJ45 Serial B Port Two RJ45 NIC connectors 15 pin video connector Two USB 2 0 ports U320 High density SCSI connector Channel B SCSI SKU only Internal IO Connectors Headers O 0 0 OO 0 0 O O Two onboard USB port headers Each header is capable of supporting two USB 2 0 ports One 10 pin DH10 Serial A Header One Ultra320 68 pin SCSI Connector Channel A SCSI SKU only Two SATA connectors with integrated chipset RAID 0 1 support One ATA100 connector One floppy conn
96. PCI slot SLOT1 u 3 3V Pin Side A 96 95 Connectors and Jumper Blocks PCI Spec Description Signal INTA This pin will be connected on the 2U riser to INT_A of the bottom PCI slot INT_D of the middle slot and INT_C of the top slot INTC This pin will be used by 1U 2U riser to bring the INT_C interrupt on the bottom PCI slot down to the baseboard PE Der dE oro n REQ3 Highest PCI Slot SLOT3 am GNT3 Highest PCI Slot SLOT3 RW Em Es GN RS Was VIO 3 3V or 1 5V GNT1 Lowest PCI slot SLOT1 GND Revision 1 0 C78844 002 177 Connectors and Jumper Blocks Pin PCI Spec Side Signal B IRDY Description KEYWAY KEYWAY 3 3V 50 PCI XCAP LOCK PERR 5 3 3V SERR C BE 1 43 42 s ANO ao 8 5 3 3 AD 01 ND 3 3V 5V 5V 37 Was Vio 3 3V or 1 5V 6 ACK64 4 33 RSVD V O 3 3Vor1 5V m Q 2 3 3 3 32 31 30 29 28 27 26 25 178 Pin Side A 62 61 Intel amp Server Board SE7520JR2 Signal FRAMER ow key 3 s 7 3 3V SMBD Daisy chain to all slots SMBCLK Daisy chain to all slots s PAR ECCO Sa pe E p Meee CN Mp CN GND m md 5 Was Vio 3 3V or 1 5V C BE O 3 3V 3 3V LN IS ECC6 m mv G om
97. Pins K 3 and Power Stat Signal LAN on a E Motherboard E SMBus Host N LOM E SMBus Interfaces 9 NV ChipSet Interface Processor mBMC ASIC Figure 20 mBMC in a Server Management System Revision 1 0 121 C78844 002 Platform Management Intel Server Board SE7520JR2 5 2 1 Server Management I C Buses The table below describes the server management lC bus assignments and lists the devices that are connected to the indicated bus The column labeled I C Bus ID represents the physical I C bus connected to the mBMC Only the Peripheral SMBus is available for use with the Write Read I C IPMI command Table 46 Server Management I C Bus ID Assignments IC Bus ID Devices Connected E Host SMBus SMBus PCI slots ICH5 mBMC DIMM FRU Peripheral SMBus SMLink ICH5 mBMC SIO 3 LM93 control panel PDB p Baseboard Temp Sensor BMC FRU Private Bus 4 PB4 Network Interface Chipset 5 2 2 Power Control Interfaces The mBMC is placed between the power button and the chipset so it can implement the Secure Mode feature of disabling the power button and add additional power control sources to the system In addition to the mandatory chassis controls such as power down and power up the mBMC supports power cycle and pulse diagnostic interrupt The mBMC Chassis Control command supports the following power behavior e Power down 0h Chassis Control command This option asserts a 4s override to the ch
98. RES Ew 21 2 1 Server Board SE7520JR2 SKU Availability oooonnoonnnncnnnnnnnnnnccccccocncnnnnnnnnnnns 21 2 2 Server Board SE7520JR2 Feature Set eee 21 3 Functional ArchiftectUre eei idad amada 26 3 1 Processor SUB SyStem RET 27 3 1 1 Processor Voltage Regulators cisma at si n 27 3 1 2 Reset Configuration Logie visi a 27 3 1 3 Processor Module Presence Detection esses 27 3 1 4 STL2006 AAA AO AAN Cei oN ihe NANI E 27 3 1 5 Common Enabling Kit CEK Design Support ssseeeeee 28 3 1 6 Processor Support 5 5 m erra rte ee YER ee eset deere 28 3 1 6 1 Processor Mis population Detection sssssssss HH 29 3 1 6 2 Mixed Processor Steppings ssssssse Hee 29 3 1 6 3 Mixed Processor Models ens 29 3 1 6 4 Mixed Processor Families sssssss eee 29 3 1 6 5 Mixed Processor Cache Sizes sssssssssssee eee 29 3 1 6 6 Jumperless Processor Speed Settings cccccceccceccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeneeees 29 IMA Microcode iet teer ret Dae dd fu t beber te gd xe ix i evt Po de 30 3 1 0 8 Processor Cache inet s eee Ee eec e DIR Hoe Eus 30 3 1 6 9 Hyper Ihreading Teshnology cito tute bn ora di i toot ette 30 3 1 6 10 Intel SpeedStep Technology 111i ener 30 3 1 6 11 EM64T Technology Support munnet tr lette eee e dee 30 3 1 7 Multiple Processor Initialization
99. Reporting and Handling Intel Server Board SE7520JR2 Message Displayed Description when it detects an imminent failure This message can be reported by an ATAPI device using the S M A R T error reporting standard S M A R T failure messages may indicate the need to replace the hard disk Table 62 Virus Related BIOS Messages Message Displayed Description BootSector Write The BIOS has detected software attempting to write toa drive s boot sector This is flagged as possible virus activity This message will only be displayed if Virus Detection is enabled in AMIBIOS setup VIRUS Continue Y N If the BIOS detects possible virus activity it will prompt the user This message will only be displayed if Virus Detection is enabled in AMIBIOS setup Table 63 System Configuration BIOS Messages Message Displayed Description DMA 2 Error Error initializing secondary DMA controller This is a fatal error often indication a problem with system hardware DMA Controller Error POST error while trying to initialize the DMA controller This is a fatal error often indication a problem with system hardware Checking NVRAM Update Failed BIOS could not write to the NVRAM block This message appears when the FLASH part is write protected or if there is no FLASH part System uses a PROM or EPROM Microcode Error BIOS could not find or load the CPU Microcode
100. Revision 1 0 C78844 002 Intel Server Board SE7520JR2 System BIOS Key Option Description PES Select Menu The left and right arrow keys are used to move between the major menu pages The keys have no affect if a sub menu or pick list is displayed Tab Select Field The Tab key is used to move between fields For example Tab can be used to move from hours to minutes in the time item in the main menu Change Value The minus key on the keypad is used to change the value of the current item to the previous value This key scrolls through the values in the associated pick list without displaying the full list Change Value The plus key on the keypad is used to change the value of the current menu item to the next value This key scrolls through the values in the associated pick list without displaying the full list On 106 key Japanese keyboards the plus key has a different scan code than the plus key on the other keyboard but will have the same effect 9 Setup Defaults Pressing F9 causes the following to appear Load Setup Defaults OK Cancel If OK is selected and the Enter key is pressed all setup fields are set to their default values If Cancel is selected and the Enter key is pressed or if the ESC key is pressed the user is returned to where they were before F9 was pressed without Discard Changes OK Cancel If OK is selected and the Enter key is pressed all changes are not sav
101. SB Mass Storage Configure the USB Mass Storage Class Selects submenu Device Configuration Devices with USB Device enable a USB Mass Storage Device Configuration Sub menu Table 28 BIOS Setup USB Mass Storage Device Configuration Sub menu Selections Feature Options Help Text USB Mass Storage Device Configuration USB Mass Storage Number of seconds POST waits for the USB Reset Delay mass storage device after start unit command Device 1 Only displayed if a device is detected includes a DevicelD string returned by the USB device Emulation Type Auto If Auto USB devices less than 530MB will be Floppy emulated as Floppy and remaining as hard drive Forced FDD Forced FDD option can be used to force a HDD Hard Disk formatted drive to boot as FDD Ex ZIP drive CDROM 92 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 System BIOS Feature Device n N A N A Only displayed if a device is detected includes a DevicelD string returned by the USB device Emulation Type Auto If Auto USB devices less than 530MB will be Floppy emulated as Floppy and remaining as hard drive Forced FDD Forced FDD option can be used to force a HDD Hard Disk formatted drive to boot as FDD Ex ZIP drive CDROM 4 4 2 2 6 PCI Configuration Sub menu This sub menu provides control over PCI devices and their option ROMs If the BIOS is reporting POST error 146 use this menu to disable option ROMs that are not requ
102. Server Board SE7520JR2 In non RAS mode BIOS will assert a Non Maskable Interrupt NMI on the first Double Bit ECC DBE error Table 58 Memory Error Handling in non RAS mode Non RAS mode Server with mBMC Server with IMM Sahalee BMC Single Bit ECC SBE error events will not be SBE error events will be logged in SEL SBE errors logged On the 10th SBE error BIOS will On the 10th SBE error BIOS will Disable SBE detection in chipset Disable SBE detection in chipset Light the faulty DIMM LED Light the faulty DIMM LED Log a SBE termination record to SEL Double Bit ECC On the 1st DBE error BIOS will On the 1st DBE error BIOS will DBE errors Log DBE record to SEL Log DBE record to SEL Light the faulty DIMM LED Light the faulty DIMM LED Generate NMI Generate NMI 6 2 3 DIMM Enabling Setting the Memory Retest option to Enabled in BIOS Setup will bring all DIMM s back on line regardless of current states After replacing faulty DIMM s the Memory Retest option must be set to Enabled Note this step is not required if faulty DIMM s were not taken off line 6 2 4 Single bit ECC Error Throttling Prevention The system detects corrects and logs correctable errors As long as these errors occur infrequently the system should continue to operate without a problem Occasionally correctable errors are caused by a persistent failure of a single component For example a b
103. Sources and Actions N Yes O O O O Watchdog timer configured for reset PEF action Optional 5 3 5 3 Control Panel System Reset The reset button is a momentary contact button on the control panel Its signal is routed through the control panel connector to the mBMC which monitors and de bounces it The signal must be stable for at least 25 ms before a state change is recognized If Secure Mode is enabled or the button is forced protected the reset button does not reset the system A Platform Security Violation Attempt event message is instead generated Control Panel User Interface When an optional Intel Management Module is not present the mBMC acts as the control panel controller processing signals from the control panel switches and LEDs When the flexible management connector is populated the mBMC stops acting on the control panel reset and power button inputs This becomes the responsibility of the Intel Management Module The mBMC supports three control panel events e Power button assertion A low level signal at PWBTIN indicates that the power button is being pressed This input is bridged to the PWBTOUT output if Control Panel Lockout is disabled The Control Panel Power Button pressed event is logged in the SEL e Reset button assertion A low level signal at RSTIN indicates that the reset button is being pressed This input is bridged to the RSTOUT output if Control Panel Lockout is disabled The Contro
104. T MSG SEL C D REQ 1 0 DB 8 DB 9 DB 10 DB 11 Intel Server Board SE7520JR2 Em ca a CE e EN E pd Ea psu pus 7 5 4 ATA 100 Connector The Server Board SE7520JR2 provides one legacy ATA 100 40 pin connector J3K1 The pin out is defined in the following table Its signals are not tied to the ATA functionality embedded into the high density 100 pin front panel connector Each connector is configured to a separate ATA port embedded in the ICH5 R Table 97 ATA 100 40 pin Connector Pin out J3K1 Pin SignalName Pin SignalName 194 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Connectors and Jumper Blocks Signal Name Pin Signal Name Pin Signal Name 5 IDE PDD 6 PDD 7 IDE_PDD 5 PDD IDE PDD 9 IDE PDD 10 2 IDE PDD 7 4 IDE PDD 8 6 8 17 IDE PDD O IDE PDIOW L 24 IDE PDIOR L 26 IDE PIORDY 28 IDE PDDACK L 30 IDE PDCS1 L 38 IDE PRI HD ACT L 40 7 5 5 SATA Connectors The Server Board SE7520JR2 provides two SATA Serial ATA connectors SATA 0 J1H1 and SATA 1 J1H5 for use with an internal SATA backplane The pin configuration for each connector is identical and is defined in the following table Y ND ND ND ND ND D Table 98 SATA Connector Pin out J1H1 and J1H5 Pin Signal Name 1 GND1 S ATAf TX P S_ATAH TX N 4 GND2 5 S ATARRKP GND3 S Jone e Jens 7 5 6 Floppy Controller Connector
105. T 0 1 2 Option for SCI TCO HPET 0 1 2 Option for SCI TCO HPET 0 1 2 PIRQH USB 2 0 EHCI controller 1 option for SCI TCO HPET 0 1 2 Ser IRQ SIO3 3 4 3 4 Serialized IRQ Support The Server Board SE7520JR2 supports a serialized interrupt delivery mechanism Serialized Interrupt Requests SERIRQ consists of a start frame a minimum of 17 IRQ data channels and a stop frame Any slave device in quiet mode may initiate the start frame While in continuous mode the start frame is initiated by the host controller 54 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture 3 4 3 5 IRQ Scan for PCIIRQ The IRQ data frame structure includes the ability to handle up to 32 sampling channels with the standard implementation using the minimum 17 sampling channels The Server Board SE7520JR2 has an external PCI interrupt serializer for PCIIRQ scan mechanism of ICH5 R to support 16 PCIIRQs ICH5 R EARARARRAARARAARARARAA HI1 5 IRQO lt 0 INTERFACE IRQ1 OB ro Z EE IRQ3 L TT E IRQ4 Ras 3 m na IRQ7 SS ICHS R ICH5 R IRQs 3 re 8259PIC IRQ9 A Raro daa IRQ11 IRQ12 IRQ13 gt gt IRQ14 LT ras gt IRQ16 IRO17 IRQO gt ra TI PCI E INTERFACE IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 gt PXH IRQ8 IRQ9 gt j IOAPIC 1 IRQ10 IRQ11 IRQ12 I IR IRQ13 IRQ14 IRQ15 I CPU1 IRQ16 IRQ17 MCH ES HI 1 5 gt PCI E INTERFAC
106. The following table details the pin out of the 34 pin legacy floppy drive connector J3K2 These signals are common to those used in the high density 100 pin Front Panel connector Concurrent use of these connectors is not supported Revision 1 0 195 C78844 002 Connectors and Jumper Blocks Intel Server Board SE7520JR2 Table 99 Legacy 34 pin Floppy Drive Connector Pin out J3K2 Signal Name Pin Signal Name Pin Signal Name 2 GND 4 Test Point KEY 6 FD_DENSEL1 Test Point FD_DIR_L 7 5 7 Serial Port Connectors The Server Board SE7520JR2 provides one external RJ45 Serial B port and one internal 9 pin Serial A header The following tables define the pinouts for each Table 100 External RJ 45 Serial B Port Pin out Pin Signal Name Description 3 Transmit Data EJ Rois 5 835 feet 8 Jers Germsmd Note 1 A jumper block on the server board will determine whether DSR or DCD is routed to pin 7 The board will have the jumper block configured with DSR enabled at production Table 101 Internal 9 pin Serial A Header Pin out J1A3 Pin Signal Name DCD carrier detect DSR data set ready 196 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Connectors and Jumper Blocks RXD receive data RTS request to send TXD Transmit data 6 CTS clear to send A 7 DTR Data terminal ready 8 RI Ring Indicate
107. V Was gnd 31 31 C BE 7 30 C BE 6 H 30 C BE 5 29 C BE 4 29 Was VIO 28 28 PAR64 27 AD 63 27 AD 62 26 AD 61 26 Was GND 25 25 AD 60 24 AD 59 24 AD 58 3 ADEET 23 22 22 AD 56 21 AD 55 21 AD 54 20 ADE 20 19 19 AD 52 18 ADI51 18 AD 50 7 aus 7 16 16 AD 48 15 AD 47 15 ADI46 4 abus L 13 13 AD 44 12 AD 43 12 AD 42 KEY jT Reversed PCI Express KEY EE KEY Di ra Reversed PCI Express KEY EE 11 AD 41 11 V 10 10 AD 40 9 AD 39 9 AD 38 s son a 7 7 066 6 AD 35 6 AD 34 5 ora 5 4 a LIE 3 Type1 Type 1 0 3 PXH RST Input to reset the PXH on the 1U 00 PCI Express N active Riser 1U 01 PCI 1U 10 N A 1U 11 N A 2 Type0 2U 00 2xPCI Express PCI 2 Revision 1 0 C78844 002 Connectors and Jumper Blocks Intel Server Board SE7520JR2 Pin Side PCI Spec Description Pin Side PCI Spec Description B Signal A Signal 2U 01 3x PCI 2U 10 PXH 3 PCI X D 2U 11 No Riser 1 Size 0 1U 1 2U 1 PXH PWR Input to indicate to PXH on active OK riser that baseboard power is OK 7 3 System Management Headers The baseboard provides several access points to the management buses built into the baseboard The following table provides the pinouts for each connector 7 3 1 Intel Management Module Connector A 120 pin connector J1C1 is included on the baseboard to support the optionally installed Professional or Advanced Management modules Table 87 IMM Connector Pi
108. a good processor The process of cycling through all the processors is repeated upon system reset or power cycle Soft resets do not affect the FRB3 timer The duration of the FRB3 timer is set by system firmware The mBMC also supports the algorithm described above with the exception that it does not disable the processor and it will be logged as an FRB2 failure 6 1 4 OS Watchdog Timer Operating System Load Failures The OS Watchdog Timer feature is designed to allow watchdog timer protection of the operating system load process This is done in conjunction with an operating system present device driver or application that will disable the watchdog timer once the operating system has successfully loaded If the operating system load process fails the BMC will reset the system The BIOS shall disable the OS Watchdog Timer before handing control to the OS loader if it is determined to be booting from removable media or the BIOS cannot determine the media type If the BIOS is going to boot to a known hard drive it will read a user option for the OS Watchdog Timer for HDD Boots If this is disabled the BIOS will ensure the watchdog timer is disabled and boot Otherwise the BIOS will read the enabled time value from the option and set the OS Watchdog timer for that value 5 10 15 or 20 minutes before trying to load the operating system If the OS Watchdog Timer is enabled the timer is repurposed as an OS Watchdog timer and is referred to by tha
109. a remote console application to access the mBMC and perform the following operations e Chassis Control e g get chassis status reset chassis power up chassis power down chassis e Get system sensor status e Get and set system boot options e Get Field Replaceable Unit FRU information e Get System Event Log SEL entries e Get Sensor Data Records SDR e Set Platform Event Filtering PEF e Set LAN configurations In addition the mBMC supports LAN alerting in the form of SNMP traps that conform to the IPMI Platform Event Trap PET format Table 53 LAN Channel Capacity LAN Channel Capability Options Number of Users 1 Revision 1 0 135 C78844 002 Platform Management Intel Server Board SE7520JR2 Privilege Levels User Operator Administrator LAN Channel Capability Options Authentication Types None Straight Password MD5 Number of LAN Alert Destinations Address Resolution Protocol ARP Gratuitous ARP 5 3 18 Event Filtering and Alerting The mBMC implements most of the IPMI 1 5 alerting features The following features are supported e PEF e Alert over LAN 5 3 18 1 Platform Event Filtering PEF The mBMC monitors platform health and logs failure events into the SEL The Platform Event Filtering PEF feature provides a configurable mechanism to allow events to trigger alert actions PEF provides a flexible general mechanism that enables the mBMC to perform selectable actions triggered
110. add in cards the add in cards must be installed starting with the slot furthest from the baseboard le When using a three slot passive riser a single PCI X add in card must be installed in the top PCI slot A second add in card must be installed in the middle slot and so on These population rules must be followed to maintain the signal integrity of the bus On a baseboard with no integrated SCSI the P64 A bus is capable of supporting a bus speed of up to 133MHz when a 1U single slot riser card is used Intel also makes available an active three slot PCI X riser which utilizes a separate on board PXH chip This riser is capable of supporting up to two PCI X 133MHz cards in addition to a third PCI X 100MHz card If used in a baseboard with no on board SCSI controller the third add in slot can also operate at 133MHz When configured with a riser card supporting PCI Express technology the full height riser slot can support riser cards that have either one x 8 PCI Express card or two x 4 PCI Express cards Intel makes available a 1U single slot x8 riser card and a 2U three slot riser card which provides two x8 connectors each supporting x4 data widths The third slot is a PCI X slot Using a baseboard configured with an integrated SCSI controller the PCI X add in slot is capable of supporting a bus speed of up to 100MHz Installed in a baseboard with no integrated SCSI controller this PCI X add in slot is capable of supporting a bus speed of up t
111. aded state Pause The message is displayed on the screen and the boot process is paused until the appropriate input is given to either continue the boot process or take corrective action Halt The message is displayed on the screen an error is logged to the SEL and the system cannot boot unless the error is corrected The error codes are defined by Intel and whenever possible are backward compatible with error codes used on earlier platforms All POST error codes are logged in the System Event Log Table 68 Error Codes and Messages Error Message Wiles Erte CMOS Battery Low CMOS Settings Wrong CMOS Checksum Bad Unlock Keyboard PS2 Keyboard not found KBC BAT Test failed CMOS memory size different RAM R W test failed A Drive Error B Drive Error Floppy Controller Failure 162 Revision 1 0 C78844 002 5 et D o D lt D W o g o o m N c N e c A N Error Code 0012 0014 0040 0041 0042 0043 0044 0045 0046 0047 0048 0049 004A 004B 004C 004D 004E 004F 0050 0055 0056 0057 0058 0059 005B 005D 005E 0120 0146 0150 0160 0161 0180 0181 0192 0193 0194 0195 0196 0197 5120 5121 5122 8104 8105 8110 8111 8120 8121 D o lt Q o 2 o Error Message CMOS time not set PS2 Mouse not found Refresh timer test failed Display memory test failed CMOS Display Type Wrong lt INS gt Pressed DMA Controller Error DMA 1 Error DMA 2 Erro
112. age rise The 5V output must never be greater than the 3 3V output by more than 2 25V Each output voltage shall reach regulation within 50ms Tyout on of each other during turn on of the power supply Each output voltage shall fall out of regulation within 400msec Tout or of each other during turn off The following figures show the timing requirements for the power supply being turned on and off via the AC input with PSON held low and the PSON signal with the AC input applied Table 122 Output Voltage Timing Item Description Minimum Maximum Units Tyout_rise Output voltage rise time from each main output 5 0 70 msec Tyout_on All main outputs must be within regulation of each 50 msec other within this time T vout off All main outputs must leave regulation within this 400 msec time Note The 5VSB output voltage rise time shall be from 1 0ms to 25 0ms Revision 1 0 209 C78844 002 Design and Environmental Specifications Intel Server Board SE7520JR2 VA V i T gt Tyout rise lt lt Tvout off le gt Tyout_on Figure 28 Output Voltage Timing Table 123 Turn On Off Timing Item Description Minimum Maximum Units Tsb_on_delay Delay from AC being applied to 5VSB being within regulation 1500 msec T ac on delay Delay from AC being applied to all output voltages being 2500 msec within regulation Tyout_holdup Time all output
113. al Advanced Instrumentation IPMI Messaging Commands and Abstractions Baseboard Management Controller BMC Yes Sensor Data Records SDRs and SDR Repository Sion Evert Log SE BMC Watchdog Timer covering BIOS and run time software Revision 1 0 113 C78844 002 Platform Management IPMI Channels and Sessions EMP Emergency Management Port IPMI Messaging over Serial Modem This feature is also referred to as DPC Direct Platform Control over serial modem Serial Modem Paging Serial Modem Alerting over PPP using the Platform Event Trap PET format DPC Direct Platform Control IPMI Messaging over LAN available via both on board network controllers LAN Alerting using PET Platform Event Filtering PEF ICMB Intelligent Chassis Management Bus IPMI Messaging between chassis PCI SMBus support Fault Resilient Booting BIOS logging of POST progress and POST errors Integration with BIOS console redirection via IPMI v2 0 Serial Port Sharing Access via web browser SNMP access Telnet access DNS support DHCP support dedicated NIC only Memory Sparing Mirroring sensor support Alerting via Email Keyboard Video Mouse KVM redirection via LAN High speed access to dedicated NIC Intel Server Board SE7520JR2 On Board Platform Instrumentation Errors Only Intel Management Module Professional Intel Management Module Advanced This chapter will provide an overview of the
114. al notifies the host that the PC87431x has data to provide When the system main power is off PWRGD signal is low the host interface signals are in TRI STATE to perform passive bus isolation between the mBMC SCLH SDAH and SMBAH signals and the SMBus controller signals The passive bus isolation can be disabled by host SMBus isolation control offset 05h to support various system designs The mBMC is a slave device on the bus The host interface is designed to support polled operations Host applications can optionally handle an SMBus alert interrupt in case the mBMC is unable to respond immediately to a host request In this case Not Ready is indicated in one of two ways e The host interface bandwidth is limited by the bus clock and mBMC latency To meet the device latency the mBMC slows the bus periodically by extending the SMBus clock low interval SCLH It is recommended to have a point to point connection between the host and mBMC e Ifthe mBMC is in the middle of a LAN or peripheral device communication or if a response to the host request is not yet ready the mBMC does not acknowledge the device address NACK This forces the host software to stop and restart the session The minimum interval between two sessions should be 500 microseconds 5 3 17 5 LAN Interface The IPMI Specification v1 5 defines how IPMI messages encapsulated in RMCP packet format can be sent to and from the mBMC This capability allows
115. also contains firmware for certain embedded devices These images are supplied by the device manufacturers and are not specified in this document The system BIOS includes the following components 4 1 IA 32 Core The IA 32 core contains standard services and components such as the PCI Resource manager ACPI support POST and runtime functionality Manageability Extensions Intel servers build server management into the BIOS through the Intelligent Platform Management Interface IPMI and baseboard management hardware Extensible Firmware Interface EFI provides an abstraction layer between the operating system and system hardware Processor Microcode BIOS includes microcode for the latest processors Option ROMs BIOS includes option ROMs to enable on board devices during boot BIOS Identification String The BIOS Identification string is used to uniquely identify the revision of the BIOS being used on the system The string is formatted as illustrated in the following figure BoardId OEMID BuildType Major Minor BuildID BuildDateTime Mod Dxx Development Xxx Power On Axx 7 Alpha BIOS Bxx Beta BIOS P Production Three characters N character ID 86A Intel DPG AN430TX etc 86B Intel EPG 10A Some OEM etc 80 two digits RCxx Release Candidate xx 2 digit number N A for Production two digits Four digits Increment on each build Figure 17 BIOS Ident
116. anagement Modules Professional and Advanced 142 Table 57 Memory Error Handling mBMC vs Sahalee rrrrnnnnnnnrrrrnnnnnnnnnnnnrrrrnnnnnnnnnnrrrnnnrnnnnnn 153 Table 58 Memory Error Handling in non RAS MOd8 ooooccccccccnnonononcnonicononananannncnnonnnnnnnnnnnanonnos 154 Table 59 Memory BIOS Messages eene enne nmecmnk tenni nni ite dd a nan iba nnna 156 Table 60 Boot BIOS Message se ox eise leise ish atit to Palati ESI A opes 157 Table 61 Storage Device BIOS Messages eeeeeee essentiae 157 Table 62 Virus Related BIOS Messages cccseceecccteeeeeeeeeceeceeeceeeeeneneedencedeeeeeeeeneeseesnenee 160 Table 63 System Configuration BIOS Messages sssssssssss e 160 Table 64 CMOS BIOS Messages er e eee ete te Sr ber puli br taeda 161 Table 65 Miscellaneous BIOS Messages 2 ceecceceeeeeeeeeceeeeeceeeesennenesseeseeeeeeeeesenenensenes 161 Table 66 USB BIOS Error Messages ue po laa 161 Table 67 SMBIOS BIOS Error Messages eeeseeeseeeeneeneeene eene nnne nnn terns 162 Revision A C78844 002 List of Tables Intel Server Board SE7520JR2 Table 68 Error Codes and Messages ccccccccssssseseecceeeeeensceeceeeeeeeesenseceseeeseneeeeseeseneeennenee 162 Table 69 Error Codes Sent to the Management Module oooooooccoccccccccccccccconanccononcconononannnnnnno 164 Table 70 BIOS Generated Beep Codes 2 sse 165 Table
117. ard SE7520JR2 6 4 2 Di amp griostic BEDS ike et tt e teta 167 6 4 3 POST Code Checkpoints sse eee 168 6 4 4 Bootblock Initialization Code Checkpoints sss 170 6 4 5 Bootblock Recovery Code Checkpoint eene nnnc 171 6 4 6 DIM Code Checkpoints esses eene mener 172 6 4 7 ACPI Runtime Checkpoints oooocccccccccconcconcnoncnoncnoncnnnnononnnnnnnonnnnnnnnnnnnnnnnnnnnnnos 173 6 4 8 POST Progress FIFO Professional Advanced only ssssessssss 173 6 4 9 Memory Error Codes ester te eti e bt tende Re te IR RR I EUR EUER DER RU M p hade 173 6 5 Light Guided Diagnostics sirio alene ne 174 7 Connectors and Jumper Blocks oooooooccconcconoconoconoconnconncnnnnnnnnnnnnnnnncn cnn 175 7 1 Power Connectors ee 175 7 2 Riser Slots mE 176 7 2 1 Low Profile PCI X Riser Slot annnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnsnnnnrnnsennsrnnsrenseenennne 176 7 2 2 Full Height PCI X Riser Slot rrrrrrrrrrrrrrrrrrrrrrrrrerrrerrrerrrenssensrrrsrresrresssesssesnsnnn 179 7 3 System Management Headers annnnnvnrrvnnnnnnnnnnvvvnnennnndnrnnnvennnnnnvesdnnnnnnnanevenevennn 184 7 3 1 Intel Management Module Connector ooocccccccnnccoconcccnncccnonanonancncnnnnnnonnnnnnnnnnnnos 184 7 3 2 IGMB Header citas aia 187 7 3 3 PMB Header coccion aii iia 187 7 3 4 OEM RMC Connector J3B2 ccecceeccee cece cece cece cette nrnnnrnnnrnn nn nn rnnnnn
118. ation e IPMI v2 0 Management Controller Initialization Agent function Professional and Advanced systems only e Emergency Management Port EMP Serial Modem platform management interface Professional and Advanced systems only e Dedicated Network Interface Controller NIC and full TCP IP software stack Advanced systems only 120 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Platform Management 5 2 On Board Platform Management Features and Functionality The National Semiconductor PC87431M mini Baseboard Management Controller mBMC is an Application Specific Integrated Circuit ASIC with a Reduced Instruction Set Computer RISC based processor and many peripheral devices embedded into it It is targeted for a wide range of remote controlled platforms such as servers workstations hubs and printers The mBMC contains the logic needed for executing the firmware controlling the system monitoring sensors and communicating with other systems and devices via various external interfaces The following figure illustrates the block diagram of the mBMC as it is used in a server management system The external interface blocks to the mBMC are the discrete hardware peripheral device interface modules shown as blocks outside of the mBMC ASIC General Flash I N Bus Interface la Purpose Output Memory o Unit GPIO Pins KV and Digital Input A 1 p Front Panel Sensor devices JF SMBus Interrupt
119. atory Compliance Country al UL Mark USA Canada Is device les with Part 15 of the Rules Operation FCE Manna rudes Uu device is subject to the following two conditions This device may nol cause harmful interference and 3 This device must accept any interference received including interference that may cause undesired operation Manufactured by Intel Corporation EMC Marking Class A Canada CANADA ICES 003 CLASS A CANADA NMB 003 CLASSE A BSMI Marking Class A Taiwan Y SAAS ER P RE AE I FEE ERTER ER gt TAE FEN HETE ABRA AES ABRIL RRL MIC Mark Korea Revision 1 0 213 C78844 002 Design and Environmental Specifications Intel Server Board SE7520JR2 8 4 Electromagnetic Compatibility Notices 84 1 X FCC USA This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 this device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation For questions related to the EMC performance of this product contact Intel Corporation 5200 N E Elam Young Parkway Hillsboro OR 97124 6497 1 800 628 8686 This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipme
120. attributes for that memory area are set to read only so that all writes are forwarded to the expansion bus 74 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture 3 5 1 4 System Management Mode Handling The chipset supports System Management Mode SMM operation in one of three modes System Management RAM SMRAM provides code and data storage space for the SMI_L handler code and is made visible to the processor only on entry to SMM or other conditions that can be configured using Intel Lindenhurst PF chipset The MCH supports three SMM options e Compatible SMRAM C SMRAM e High Segment HSEG e Top of Memory Segment TSEG Three abbreviations are used later in the table that describes SMM Space Transaction Handling SMM Space Transaction Address Space DRAM Space DRAM Enabled Adr Compatible C A0000h to BFFFFh A0000h to BFFFFh High H OFEDAO0000h TO OFEDBFFFFh A0000h to BFFFFh TSEG T TOLM TSEG SZ to TOLM TOLM TSEG SZ to TOLM Note High SMM is different than in previous chipsets In previous chipsets the high segment was the 384KB region from A 0000h to F FFFFh However C 0000h to F FFFFh was not useful so it is deleted in MCH Note TSEG SMM is different than in previous chipsets In previous chipsets the TSEG address space was offset by 256MB to allow for simpler decoding and the TSEG was remapped to directly under the TOLM In the MCH the TSEG region is not offset by 256M
121. been added to the initialization engine to support high speed population and verification of a programmable memory range with one of four known data patterns 0 F A 5 3 C and 6 9 This function facilitates a limited very high speed memory test as well as provides a BIOS accessible memory zeroing capability for use by the operating system Revision 1 0 43 C78844 002 Functional Architecture Intel Server Board SE7520JR2 3 3 6 5 DIMM Sparing Function To provide a more fault tolerant system the Intel E7520 MCH includes specialized hardware to support fail over to a spare DIMM device in the event that a primary DIMM in use exceeds a specified threshold of runtime errors One of the DIMMs installed per channel greater than or equal in size than all installed will not be used but kept in reserve In the event of significant failures in a particular DIMM it and its corresponding partner in the other channel if applicable will over time have its data copied over to the spare DIMM s held in reserve When all the data has been copied the reserve DIMM s will be put into service and the failing DIMM will be removed from service Only one sparing cycle is supported If this feature is not enabled then all DIMMs will be visible in normal address space Note The DIMM Sparing feature requires that the spare DIMM be at least the size of the largest primary DIMM in use Hardware additions for this feature include the implementation of trackin
122. bus segments e APCI 33MHz 32 bit bus segment P32 A is controlled through the ICH5 R e Two PCI X 100MHz 64 bit bus segments P64 A and P64 B are controlled through PXH PCI bridge e One dual x4 PCI Express P64 Express bus segment is controlled from the MCH The table below lists the characteristics of the four PCI bus segments Revision 1 0 47 C78844 002 Functional Architecture Intel Server Board SE7520JR2 Table 7 PCI Bus Segment Characteristics PCI Bus Segment Voltage Width Speed Type PCI I O Card Slots P32 A 32 bits 33 MHz None Internal component use only hi d Common riser slot capable of supporting full e Ores c MU MH pe length PCI X or PCI E add in cards P64 B 64 bits 100 MHz PCI X One riser slot supporting only low profile add in cards P64 Express Differential 64 bits Dualx4 PCI E Common riser slot capable of supporting full length PCI X or PCI E add in cards 3 4 1 1 P32 A 32 bit 33 MHz PCI Subsystem All 32 bit 33 MHz PCI I O is directed through the ICH5 R The 32 bit 33 MHz PCI segment provided by the ICH5 R is known as the P32 A segment The P32 A segment supports the following embedded devices e 2D 3D Graphics Accelerator ATI Rage XL Video Controller e SIO Chip National Semiconductor PC87417 Super I O e Hardware monitoring sub system SMBUS 3 4 1 2 P64 A and P64 B 64 bit 100MHz PCI Subsystem Two peer 64 bit PCI X bus segments are directed through the PXH PCI Br
123. cessor and status LEDs for 5 volt stand by and system state Operation of some of these LEDs is dependant upon whether an IMM is installed or not With on board platform instrumentation there is limited diagnostic LED support 174 In systems configured with an IMM the CPU 1 or CPU 2 led is lit to indicate the processor is disabled DC Off or AC Cycle will cause the LED to turn off CPU 1 and 2 LEDs are both lit to indicate the baseboard HW has discovered a configuration error If processor mis population is detected when using standard on board platform instrumentation baseboard hardware will illuminate both processor error LEDs If an IMM Professional or Advanced editions is used the Sahalee BMC will generate a series of beep codes when this condition is detected and will illuminate the processor 1 fault LED An AC cycle will cause the LEDs to turn off DIMM fault LEDs are lit by BIOS whenever BIOS disables a specific DIMM The 5 Volt stand by LED is always lit when 5 volt stand by is present The Status LED displays the state of the system It mirrors the state of the Control Panel Status LED Valid states include Solid Green Blinking Green Blinking Amber Solid Amber and Off Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Connectors and Jumper Blocks 7 Connectors and Jumper Blocks 7 1 Power Connectors The main power supply connection is obtained using a SSI Compliant 2x12 pin connector In addition there are t
124. compatible Intel host system For information on compatible host system s refer to Intel s Server Builder Web site or contact your local Intel representative e FCC ICES 003 Emissions USA Canada Verification e CISPR 22 Emissions International e EN55022 Emissions Europe e EN55024 Immunity Europe e CE EMC Directive 89 336 EEC Europe e AS NZS 3548 Emissions Australia New Zealand e BSMI CNS13438 Emissions Taiwan e GOST R 29216 91 Emissions Listed on one System License Russia e GOST R 50628 95 Immunity Listed on one System License Russia e Belarus License Listed on one System License Belarus e RRL MIC Notice No 1997 41 EMC amp 1997 42 EMI Korea 212 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Design and Environmental Specifications 8 3 3 Certifications Registrations Declarations e UL Certification US Canada e CE Declaration of Conformity CENELEC Europe e FCC ICES 003 Class A Attestation USA Canada e C Tick Declaration of Conformity Australia e MED Declaration of Conformity New Zealand e BSMI Certification Taiwan e GOST Listed on one System License Russia e Belarus Listed on one System License Belarus e RRL Certification Korea e Ecology Declaration International 8 3 4 Product Regulatory Compliance Markings This product is marked with the following Product Certification Markings Table 124 Product Certification Markings Regul
125. ct to the mBMC Peripheral I F SIO Heceta Front panel header A level shifted version of this bus 5V Standby should connect to the Power Supply header PERIPH I2C 3VSB SCL This bus should connect to the mBMC Peripheral I F SIO Heceta Front panel 7 PERIPH I2C 3VSB SDA This bus should connect to the Northbridge and I O bridge MCH and PXH respectively in the LH chipset In a system that supports PCI Hot Plug this bus should also connect to the Power control devices if possible such as the MIC2591 for PCI Express for example This bus should connect to the Northbridge and I O bridge MCH and PXH header A level shifted version of this bus 5V Standby should connect to the MCH I2C 3V SDA Power Supply header MCH I2C 3V SCL respectively in the LH chipset In a system that supports PCI Hot Plug this bus should also connect to the Power control devices if possible such as the MIC2591 for PCI Express for example LAN I2C 3VSB SDA LAN usage Revision 1 0 185 C78844 002 Connectors and Jumper Blocks Intel Server Board SE7520JR2 FMC Signal Name Description Pin LAN I2C 3VSB SCL LAN usage HDD FLT LED N 64 Drive Fault LED output driven when FMM detects a bad drive from the Hot Swap controller on the Hot Swap disk Drive sub system FMM PS PWR ON N Power On Request to the system Power Supply COOL FLT LED N Cool Fault LED output driven when FMM detects a bad Fan if SSI front panel is detect FMM CPU VRD EN This sig
126. ctor Pin out J3F 1 tnnt nnne 188 Table 90 DEM RMC Connector Pinout J3B2 usos 189 Table 91 100 Pin Flex Cable Connector Pin out For Intel Chassis w Backplane J2J1 189 Table 92 50 Pin Control Panel Connector Intel Chassis w No Backplane J1J2 190 Table 93 Control Panel SSI Standard 34 Pin Header Pin out rennnnnnannnnvrrrnnnnnnnnnnrrrnnnrrnnnnnn 191 Table 94 VGA Connector Pin out esses emnes 192 Table 95 RJ 45 10 100 1000 NIC Connector Pin out cccccccononononcncnicccinonanaannnnnnnnnnnnannnnnnnnnnnns 193 Table 96 Internal External 68 pin VHDCI SCSI Connector Pin out sssssse 193 Table 97 ATA 100 40 pin Connector Pin out J3K1 ess 194 Table 98 SATA Connector Pin out J1H1 and J1H5 occcccccnnnccononcnonininonananancncnnnnncnnnnnnannnnnnnos 195 Table 99 Legacy 34 pin Floppy Drive Connector Pin out J3K2 ssssssssss 196 Table 100 External RJ 45 Serial B Port Pin out sss 196 Table 101 Internal 9 pin Serial A Header Pin out J1A3 sseeeeeeeee 196 Table 102 Stacked PS 2 Keyboard and Mouse Port Pin out sss 197 xvi Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Table 103 Table 104 Table 105 Table 106 Table 107 Table 108 Table 109 Table 110 Table 111 Table 112 Table 113 Table 114 Table 115 Table 116 Table 117 Table 118 Tab
127. cture 3 1 Processor Sub system The support circuitry for the processor sub system consists of the following e Dual 604 pin zero insertion force ZIF processor sockets e Processor host bus AGTL support circuitry e Reset configuration logic e Processor module presence detection logic e BSEL detection capabilities e CPU signal level translation e Common Enabling Kit CEK CPU retention support 3 1 1 Processor Voltage Regulators The baseboard has two VRDs Voltage Regulator Devices providing the appropriate voltages to the installed processors Each VRD is compliant with the VRD 10 1 specification and is designed to support Intel Xeon processors that require up to a sustained maximum of 105 AMPs and peak support of 120A The baseboard supports the current requirements and processor speed requirements defined in the Flexible Mother Board FMB specification for all 800 MHz FSB Intel Xeon processors FMB is an estimation of the maximum values the 800 MHz FSB versions of the Intel Xeon processors will have over their lifetime The value is only an estimate and actual specifications for future processors may differ At present the current demand per FMB is a sustained maximum of a 105 Amps and peak support of 120 Amps 3 1 2 Reset Configuration Logic The BIOS determines the processor stepping cache size etc through the CPUID instruction All processors in the system must operate at the same frequency have the same cache sizes
128. cycle and or reset actions the actions are performed according to PEF Action Priorities Note An action that has changed from delayed to non delayed or an action whose delay time has been reduced automatically has higher priority The mBMC can be configured to log PEF actions as SEL events Table 54 PEF Action Priorities Delayed Type Note jPowe Down E PEF Action Action Y shutdown OEM PEF Action Not executed if a power down action was also selected Power cycle PEF Action Not executed if a power down action was also selected Reset 4 Yes PEF Action Not executed if a power down action was also selected Diagnostic Interrupt PEF Action Not executed if a power down action was also selected PET Alert PEF Action When selected always occurs immediately after detection of a critical event Sensor feedback 7 No OEM PEF Action When selected always occurs immediately after detection of a critical event IPMB message event No OEM PEF Action When selected always occurs immediately after detection of a critical event Fault LED action No OEM PEF Action When selected always occurs immediately after detection of a critical event and is stopped after the de assertion of all critical events that requested LED blinking Identification LED action 10 No OEM PEF Action When selected always occurs immediately after detection of a critical event 5 3 18 2 Alert over LAN LAN alerts are sent as SNMP traps in ASF for
129. d write test error Motherboard timer not operational Processor error 8042 Gate A20 test error cannot switch to protected mode General exception error processor exception error Display memory error system video adapter ROM checksum error CMOS shutdown register read write error 2 dq o O O1 RON o Cache memory test failed Revision 1 0 165 C78844 002 Error Reporting and Handling Intel Server Board SE7520JR2 Table 71 Troubleshooting BIOS Beep Codes Number of Beeps Troubleshooting Action Reseat the memory or replace with known good modules 4 7 9 11 Fatal error indicating a serious problem with the system Consult your system manufacturer Before declaring the motherboard beyond all hope eliminate the possibility of interference by a malfunctioning add in card Remove all expansion cards except the video adapter If the beep codes are generated even when all other expansion cards are absent the motherboard has a serious problem Consult your system manufacturer If the beep codes are not generated when all other expansion cards are absent one of the add in cards is causing the malfunction Insert the cards back into the system one at a time until the problem happens again This will reveal the malfunctioning add in card If the system video adapter is an add in card replace or reseat the video adapter If the video adapter is an integrated part of
130. d information to locate sensors in order to poll them interpret and present their data readings adjust thresholds interpret SEL entries and alter event generation settings In Professional and Advanced management models SDRs also provide a mechanism for extending the baseboard management with additional chassis or OEM value added monitoring and events The baseboard monitoring can be extended by implementing an IPMI compatible management controller connecting it to the IPMB and adding new SDRs describing that controller and its sensors to the SDR Repository System Management Software can then read the SDRs and use them to automatically incorporate the additional sensors Revision 1 0 117 C78844 002 Platform Management Intel Server Board SE7520JR2 5 1 4 Private Management Busses A Private Management Bus is a single master 1 C bus that is controlled by the management controller Access to any of the devices on the Private Management Bus is accomplished indirectly via commands to the management controller via the IPMB or system interfaces Private Management busses are a common mechanism used for accessing temperature sensors system processor information and other baseboard monitoring devices that are located in various locations in the system The devices on the Private Management Bus are isolated from traffic on the IPMB Since devices such as temperature sensors are polled by the management controller this gets the p
131. d to the System Event Log SEL e System Event Log SEL Non volatile storage for platform health events Events can be autonomously logged by the BMC or by sending Event Messages via the system interface or IPMB to the BMC This enables BIOS software and add in cards to also log events e Sensor Data Record SDR Repository Non volatile storage holding records describing the number and type of management sensors on the baseboard and in the chassis Includes write support for OEM specific records and sensors e SDR SEL Timestamp Clock A clock internally maintained by the management controller that is used for time stamping events and recording when SDR and SEL contents have changed e Intelligent Platform Management Bus IPMB The IPMB is a two wire multi master serial bus that provides a point for extending the baseboard management to include chassis management features and for enabling add in cards to access the baseboard management subsystem Professional and Advanced systems only e Watchdog Timer with selectable timeout actions power off power cycle reset or NMI and automatic logging of timeout event e Direct Platform Control DPC LAN Remote Management Connection e LAN Alerting via PET Platform Event Trap format SNMP trap e Serial Modem Remote Management Connection Professional and Advanced systems only e Serial Modem Event Paging Alerting Professional and Advanced systems only Revision 1 0 119 C78844 002 Plat
132. d together the fully integrated system will meet the intended thermal requirements of these components It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non operating limits 8 2 Power Supply Requirements Note The information provided in this section was derived from Intel s 500W power supply specification designed for use in the Server Chassis SR1400 The figures provided and the values in the tables are meant for reference purposes only and are based on a 1U rack server configuration Variations in system configurations may produce different values 8 2 1 Output Connectors Listed or recognized component appliance wiring material AVLV2 CN rated min 105 C 300Vdc shall be used for all output wiring 202 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Design and Environmental Specifications Note The following diagram shows the power harness spec drawing as defined for use in Intel server chassis Reference chassis designs may or may not require all of the connectors shown and different wiring material may be needed to meet specific platform requir
133. ding on whether the serial device requires a DSR or DCD signal The final adapter configuration should also match the desired pin out of the RJ45 connector as it can also be configured to support either DSR or DCD 3 4 10 3 Removable Media Drives The BIOS supports removable media devices including 1 44MB floppy removable media devices and optical devices such as a CD ROM drive or DVD drive read only The BIOS supports booting from USB mass storage devices connected to the chassis USB port such as a USB key device The BIOS supports USB 2 0 media storage devices that are backward compatible to the USB 1 1 specification 3 4 10 4 Floppy Disk Support The floppy disk controller FDC in the SIO is functionally compatible with floppy disk controllers in the DP8473 and N844077 All FDC functions are integrated into the SIO including analog data separator and 16 byte FIFO On the Server Board SE7520JR2 floppy controller signals are directed to two separate connectors When the baseboard is used with any of the backplanes designed for either the Server Chassis SR1400 or SR2400 the floppy signals are directed through the 100 pin backplane connector J2J1 If no backplane is present a floppy drive can be attached to the on board legacy 36 pin connector J3K2 Note Using both interfaces in a common configuration is not supported 3 4 10 5 Keyboard and Mouse Support Dual stacked PS 2 ports located on the back edge of the baseboard are prov
134. e appropriate drive or USB interface Power on system The System will automatically boot to the media and start the BIOS recovery operation During multi disk recovery operation system will beep 1sec continuously to notify user to insert disk1 When the update has completed the system will beep 4 times followed by an endless beep Turn off the system and unplug it set jumper J1H2 back to Normal mode J1H2 B 1 2 e Recovery operation complete Revision 1 0 219 C78844 002 Intel Server Board SE7520JR2 Appendix A Integration and Usage Tips Appendix A Integration and Usage Tips The following Integration and Usage Tips are provided to assist with answering miscellaneous questions about the Server Board SE7520JR2 or as a guide to assist with troubleshooting common errors e The use of DDR2 400 MHz or DDR 266 333 MHz DIMMs is dependant on which board SKU is used DDR 2 DIMMs cannot be used on a board designed to support DDR DDR DIMMs cannot be used on boards designed to support DDR 2 e DDR 266 amp DDR 333 DIMM population rules are as follows A DIMM banks must be populated in order starting with the slots furthest from MCH B Single rank DIMMs must be populated before dual rank DIMMs C A maximum of four DIMMs can be populated when all four DIMMs are dual rank DDR 333 DIMMs e DDR2 400 DIMM population rules are as follows A DIMMs banks must be populated in order starting with the slots furthest from MCH B
135. e for Numlock EM On PS 2 Mouse Support Disabled Select support for PS 2 mouse Enabled Auto POST Error Pause Disabled If enabled the system will wait for user intervention Enabled on critical POST errors If disabled the system will boot with no intervention if possible Hit F2 Message Display Disabled Displays Press F2 to run Setup in POST Enabled Scan User Flash Area Disabled Allows BIOS to scan the Flash ROM for user Enabled binaries 96 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 System BIOS 4 4 2 3 2 Boot Device Priority Sub menu Selections Table 33 BIOS Setup Boot Device Priority Sub menu Selections Options Help Text Boot Device Priority 1st Boot Device Varies Specifies the boot sequence from the Number of entries will vary based on available devices system configuration A device enclosed in parenthesis has been disabled in the corresponding type menu nth Boot Device Specifies the boot sequence from the available devices A device enclosed in parenthesis has been disabled in the corresponding type menu 4 4 2 3 3 Hard Disk Drive Sub menu Selections Table 34 BIOS Setup Hard Disk Drive Sub Menu Selections Feature Options Help Text Hard Disk Drives 1st Drive Varies Specifies the boot sequence from the available Varies based on system configuration devices Specifies the boot sequence from the available Varies based on system configuration devices
136. e memory control hardware will cause a single full resubmission of the entire cache line request from memory to verify the existence of corrupt data This feature is expected to greatly reduce or eliminate the reporting of false or transient uncorrectable errors in the DRAM array Note that any given read request will only be retried a single time on behalf of this error detection mechanism If the uncorrectable error is repeated it will be logged and escalated as directed by device configuration In the memory mirror mode the retry on an uncorrectable error will be issued to the mirror copy of the target data rather than back to the devices responsible for the initial error detection This has the added benefit of making uncorrectable errors in DRAM fully correctable unless the same location in both primary and mirror happens to be corrupt This RASUM feature may be enabled and disabled via configuration 3 3 6 4 Integrated Memory Initialization Engine The Intel E7520 MCH provides hardware managed ECC auto initialization of all populated DRAM space under software control Once internal configuration has been updated to reflect the types and sizes of populated DIMM devices the MCH will traverse the populated address space initializing all locations with good ECC This not only speeds up the mandatory memory initialization step but also frees the processor to pursue other machine initialization and configuration tasks Additional features have
137. e of memory Sparse e Test one interleave width per mega byte of memory Quick The interleave width of a memory subsystem is dependent on the chipset configuration By default both the base and extended memory tests are configured to the Disabled setting The extended memory test can be aborted by pressing the lt Space gt key during the test 3 3 5 Memory Monitoring Both the baseboard management controller and BIOS provide support for memory inventory memory failure LEDs and failure state transition events Memory monitoring features are supported differently depending on which level of server management is used The following table shows how each feature is supported by management level Table 6 Memory Monitoring Support by Server Management Level Memory Feature On board Professional Advanced Inventory No Yes Yes Correctable Error Reporting No Yes Yes Uncorrectable Error Reporting Yes Yes Yes With either Professional or Advanced IMMs installed the Sahalee BMC maintains one sensor per DIMM The sensor is IPMI type 21h Slot Connector The Sahalee BMC directly detects the presence or absence of each DIMM and records this in offset 2 of these sensors DIMM failure can be detected at BIOS POST or during system operation POST detected DIMM failures or mis configuration incompatible DIMM sizes speeds etc cause the BIOS to disable the failed affected DIMMs and generate IPMI SEL events which are sent
138. e resource manager assigns the PIC mode interrupt for the devices that will be accessed by the legacy code The BIOS configures the PCI Base Address Registers BAR and the command register of each device Software must not make assumptions about the scan order of devices or the order in which resources are allocated to them The BIOS supports the INT 1Ah PCI BIOS interface calls 3 4 1 9 Automatic IRQ Assignment The BIOS automatically assigns IRQs to devices in the system for legacy compatibility No method is provided to manually configure the IRQs for devices 3 4 1 10 Option ROM Support The BIOS dispatches the option ROMs to available memory space in the address range 0c0000h 0e7fffh Given the limited space for option ROMs the BIOS allows for disabling of legacy ROM posting via the BIOS Setup Onboard and per slot option ROM disable options are also available in BIOS Setup The option to disable the onboard video option ROM is not available The option ROM space is also used by the console redirection binary if enabled and the user binary if present and configured for runtime usage The SE7520JR2 BIOS integrates option ROMs for the Intel 82546GB the ATI Rage XL and the LSI 53C1030 SCSI controller 3 4 1 11 PCI APIs The system BIOS supports the INT 1Ah AH B1h functions as defined in the PCI BIOS Specification The system BIOS supports the real mode interfaces and does not support the protected mode interfaces 3 4 2 Sp
139. e serial and parallel ATA ports The MAP register provides the ability to share PCI functions When sharing is enabled all decode of I O is done through the SATA registers A software write to the Function Disable Register D31 FO offset F2h bit 1 causes Device 31 Function 1 IDE controller to hidden and its configuration registers are not used The SATA Capability Pointer Register offset 34h will change to indicate that MSI is not supported in combined mode The ICH5 R SATA controller features two sets of interface signals that can be independently enabled or disabled Each interface is supported by an independent DMA controller The ICH5 R SATA controller interacts with an attached mass storage device through a register interface that is equivalent to that presented by a traditional IDE host adapter The host software follows existing standards and conventions when accessing the register interface and follows standard command protocol conventions SATA interface transfer rates are independent of UDMA mode settings SATA interface transfer rates will operate at the bus s maximum speed regardless of the UDMA mode reported by the SATA device or the system BIOS Revision 1 0 61 C78844 002 Functional Architecture Intel Server Board SE7520JR2 3 4 6 1 SATA RAID The Intel RAID Technology solution available with the 82801ER ICH5 R ICH5R offers data striping for higher performance RAID Level 0 alleviating disk bottlenecks by taki
140. e through either a locally attached monitor or through remote console redirection 4 3 1 User Interface During the system boot up POST process there are two types of consoles used for displaying the user interface graphical or text based Graphics consoles are in 640x480 mode text consoles use 80x25 mode The console output is partitioned into three windows the System Activity State Splash Screen Diagnostic and POST Activity The POST Activity window displays information about the current state of the system The Splash Screen Diagnostic window displays the OEM splash screen or a diagnostic information screen The POST Activity window displays information about the currently executing portion of POST as well as user prompts and status messages Revision 1 0 81 C78844 002 System BIOS Intel Server Board SE7520JR2 Svstem Activitv State Splash Screen Diagnostic Screen POST Activity Figure 18 POST Console Interface 4 3 1 1 System Activity Window The top row of the screen is reserved for the system state window On a graphics console the window is 640x48 On a text console the window is 80x2 The system state window may be in one of three forms either an activity bar that scrolls while the system is busy a progress bar that measures percent complete for the current task or an attention required bar The attention bar is useful for tasks that require user attention to continue 4 3 1 2 Splash Screen Diagnostic W
141. e video memory interface signals Table 12 Video Memory Interface Signal Name 1 O Type CASH iO Column Address Select Revision 1 0 63 C78844 002 Functional Architecture Intel Server Board SE7520JR2 eke JO Clock Enable for Memory CS 1 0 O Chip Select for Memory DQM 7 0 Memory Data Byte Mask Memory Special Function Enable HCLK Memory Clock MD 31 0 RAS Memory Data Bus Row Address Select Write Enable 6 rg eed mo o MemAdWesE fo p 3 4 7 3 Dual video The BIOS supports single and dual video modes The dual video mode is enabled by default e In single mode Dual Monitor Video Disabled the onboard video controller is disabled when an add in video card is detected e In dual mode Onboard Video Enabled Dual Monitor Video Enabled the onboard video controller is enabled and will be the primary video device The external video card will be allocated resources and is considered the secondary video device BIOS Setup provides user options to configure the feature as follows A E YT Disabled Dual Monitor Video Enabled Shaded if onboard video is set 3 4 8 Network Interface Controller NIC The Intel 82546GB dual channel gigabit network interface controller supplies the baseboard with two network interfaces The 82546GB is a highly integrated PCI LAN controller in a 21 mm PBGA package Each channel is capable of supporting 10 100 1000 operation and alert on LAN functional
142. ecause of incorrect data structure This condition occur if the USB host controller needs 64 Revision 1 0 161 C78844 002 Error Reporting and Handling Intel Server Board SE7520JR2 Message Displayed Description bit data structure while the USB is ported with 32 bit data structure Table 67 SMBIOS BIOS Error Messages Message Displayed Description Not enough space in Runtime area SMBIOS data will This message is displayed when the size of the SMBIOS not be available data exceeds the available SMBIOS runtime storage size 6 4 2 POST Error Codes During POST after the video has been initialized the BIOS outputs the current boot progress codes on the video screen Progress codes are 32 bit quantities plus optional data The 32 bit numbers include class subclass and operation information Class and subclass point to the type of the hardware that is being initialized Operation represents the specific initialization activity Based on the data bit availability to display the progress code a progress code can be customized to fit the data width The higher the data bit higher the granularity of allowable information Progress codes may be reported by system BIOS or option ROMs The response section in the following table is divided into three types e Warning The message is displayed on screen and the error is logged to the SEL The system will continue booting with a degr
143. ector SSI compliant 34 pin and custom control panel headers 50 pin and 100 pin SSI compliant 24 pin main power connector This supports ATX 12V standard in the first 20 pins Intel Management Module IMM connector supporting both Professonal Edition and Advanced Edition management modules Intel Light Guided Diagnostics on all FRU devices processors memory power Port 80 Diagnostic LEDs displaying POST codes The following figure shows the board layout of the Server Board SE7520JR2 Each connector and major component is identified by number and is identified in Table 1 22 Revision 1 0 C78844 002 Server Board Overview Intel Server Board SE7520JR2 Figure 1 SE7520JR2 Board Layout 23 Revision 1 0 C78844 002 Server Board Overview Intel Server Board SE7520JR2 Table 1 Baseboard Layout Reference Ref Description Ref Description J1A1 2 Pin Chassis Intrusion Header 1 J1A2 2 Pin Hard Drive Act LED Header 22 CPU 2 Fan Header J1A4 Rolling BIOS Jumper 2 10 Pin DH10 Serial A Header 23 CPU 1 Fan Header 3 Ext SCSI Channel B Connector 24 5 pin Power Sense Header 4 USB Port 2 25 PXH Chipset Component 5 USB Port 1 26 CPU 2 Socket 6 Video Connector 27 CPU 1 Socket 7 NIC 2 28 ICH5 R Chipset Component 8 NIC 1 29 SATA Ports J1H2 Recovery Boot Jumper 9 RJ 45 Serial B Port 30 J1H3 Password Clear Jumper
144. ed an ATAPI compatibility test This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST 6 Slave Drive ATAPI Incompatible The IDE ATAPI device configured as Slave in the 6 IDE controller failed an ATAPI compatibility test This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST S M A R T Capable but Command Failed The BIOS tried to send a S M A R T message to a hard disk but the command transaction failed This message can be reported by an ATAPI device using the S M A R T error reporting standard S M A R T failure messages may indicate the need to replace the hard disk S M A R T Command Failed The BIOS tried to send a S M A R T message to a hard disk but the command transaction failed This message can be reported by an ATAPI device using the S M A R T error reporting standard S M A R T failure messages may indicate the need to replace the hard disk S M A R T Status BAD Backup and Replace A S M A R T capable hard disk sends this message when it detects an imminent failure This message can be reported by an ATAPI device using the S M A R T error reporting standard S M A R T failure messages may indicate the need to replace the hard disk S M A R T Capable and Status BAD A S M A R T capable hard disk sends this message Revision 1 0 159 C78844 002 Error
145. ed and setup is exited If Cancel is selected and the Enter key is pressed or the ESC key is pressed F affecting any existing field values F7 Discard Changes Pressing F7 causes the following message to appear the user is returned to where they were before F7 was pressed without affecting any existing values F 10 Save Changes and Pressing F10 causes the following message to appear Exit Save configuration changes and exit setup OK Cancel If OK is selected and the Enter key is pressed all changes are saved and setup is exited If Cancel is selected and the Enter key is pressed or the ESC key is pressed the user is returned to where they were before F10 was pressed without affecting any existing values 4 4 2 Entering BIOS Setup The BIOS Setup utility is accessed by pressing the F2 hotkey during POST 4 4 2 1 Main Menu The first screen displayed when entering the BIOS Setup Utility is the Main Menu selection screen This screen displays the major menu selections available The following tables describe the available options on the top level and lower level menus Default values are shown in bold text Table 19 BIOS Setup Main Menu Options Feature Options Help Text Revision 1 0 85 C78844 002 System BIOS Intel Server Board SE7520JR2 Feature Options Help Text System Overview AMI BIOS time and date Processor Count N A N A Detected number of physical processors Syste
146. efault the Sahalee BMC rejects duplicate codes that are received however the command interface allows BIOS to explicitly indicate that the code should be stored regardless of whether the previous code was a duplicate A corresponding command allows system software to be able to retrieve the contents of the FIFO This command can be executed via the internal and external interfaces to the Sahallee BMC The POST Progress FIFO is volatile It is cleared whenever the system loses AC power is powered down ACPI S4 or S5 or is reset 6 5 9 Memory Error Codes Table 80 Memory Error Codes 001h MEM_ERR_CHANNEL_B_OFF DIMM mismatch forced Channel B disabled 002h MEM_ERR_CK_PAIR_OFF Slow DIMM s forced clock pair disabled OE 1h MEM ERR NO DEVICE 7 immer ns OE3h MEM ERR UNSUPPORTED DIMM nsaponsvomntner OE4h MEM_ERR_CHL_MISMATCH Revision 1 0 173 C78844 002 Error Reporting and Handling Intel Server Board SE7520JR2 Tpoint OEAh MEM_ERR_TIMING OEBh MEM_ERR_INST_ORDER_ERR OFOh SYS_FREQ_ERR Flag for Unsupported System Bus Freq 0F1h DIMM_ERR_CFG_MIX OF2h DQS_FAILURE OF3h MEM_ERR_MEM_TEST_FAILURE Error code for unsuccessful Memory Test OF4h MEM_ERR_ECC_INIT_FAILURE Error code for unsuccessful ECC and Memory Initialization 6 6 Light Guided Diagnostics The baseboard provides system fault status LEDs in many areas of the board There are fault LEDs for each DIMM slot and for each pro
147. em is loaded the following can cause the system to wake up the PME RTC or Wake On LAN Table 44 Supported Wake Events Wake Event Supported via ACPI by sleep state Supported Via Legacy Wake Power Button Always wakes system Always wakes system Ring indicate from Serial A Wakes from S1 and S4 Ring indicate from Serial B Wakes from S1 and S4 If Serial B COM2 is used for Emergency Management Port Serial B wakeup is disabled RTC Alarm Wakes from S1 Always wakes the system up from S4 Wakes fom ST Keyboard Wakes from S1 Wakes fom ST Revision 1 0 111 C78844 002 System BIOS Intel Server Board SE7520JR2 4 10 PXE BIOS Support The BIOS will support PXE compliant implementations that e Locate and configure all PXE capable boot devices UNDI Option ROMs in the system both built in and add ins e Supply a PXE according to the specification if the system includes a built in network device e Meet the following specifications System Management BIOS SMBIOS Reference Specification v2 2 or later The requirements defined in Sections 3 and 4 of the BIOS Boot Specification BBS v1 01or later to support network adapters as boot devices Also supply a valid UUID and Wake up Source value for the system via the SMBIOS structure table 4 11 Console Redirection The BIOS supports redirection of both video and keyboard via a serial link Serial A or Serial B When console redirection is enabled the local hos
148. ement Sub menu Selections cece 100 Table 40 BIOS Setup Serial Console Features Sub menu Selections 101 Table 41 BIOS Setup Event Log Configuration Sub menu Selections 101 Table 42 BIOS Setup Exit Menu Selections sssssssssssssss e 102 Table 43 Security Features Operating Model ssssssssssssssem 106 Table 44 Supported Wake Events ccccccccscsesseeeeceeeeeeeseeeeececeeeesseseeeeueseeeeessaeaeaeaseeseeeeeaees 111 Table 45 Suppoted Management Features by Tier sssssssssssssse 113 Table 46 Server Management I C Bus ID Assignments ssssssseeeeeenee 122 Table 47 Power Control Initiators essem eee eene enne 126 Table 48 System Reset Sources and Actions sss 127 Table 49 SSI Power LED Operation sse eem eee 128 Table 50 Fault status BED etri A SR sees 129 Table 51 Chassis ID LED esci tri Rin Ce dave AN E e RR E RS determined de o nn 129 Table 52 Suported Channel Assignments 2 2 cc20 eeceeeeeeeeeseeceeeeteeeetedeeeedseneeeteeeeeeneneenenneee 134 Table 53 LAN Channel Capacitan 135 Table 54 PEF Action Priorities eese nennen nennen enne nen 137 Table 55 Platform Sensors for On Board Platform Instrumentation sssssus 138 Table 56 Platform Sensors for Intel M
149. ements rnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnsnnnsnnnsennsennsennsennsennr 202 8 2 1 Output Cornnaectors 5 tree ae ni gere gen ere E RENE ER Xe a a 202 8 2 2 GrOUMGING tc 205 8 2 3 KES EE itin M D teet M I Ma M Codi LUE MEUSE 206 8 2 4 Standby OQUIDUls avd eSak keen 206 825 Voltage Reg lat Om Hale eanet 207 8 2 6 Bi eee 207 8 2 7 Capacitive Lodi 208 8 2 8 Closed Loop SIabIlIDy oso AGE 208 8 2 9 Common Mode NoiSe tnit eor eres retro qo o dieses 208 8 2 10 Ripple NOISE iie e lis 208 82711 S ft Startihg sensata 209 8 2 12 Zero Load Stability Requirements c ccccceceeeeesesenecteeeeeeeseeedeeeneeeeereeeeeeeees 209 82 13 TIMINDOREQUIS metis ua Ra 209 8 2 14 Residual Voltage Immunity in Standby Mode oooooccconnoncconcccccccnonananoncncnncncnnnnnnns 211 8 3 Product Regulatory Compliance eeeceeeee eene ener nnecen 212 8 3 1 Product Safety Compliance ciii paite it edite bisou 212 8 3 2 Product EMC Compliance Class A Compliance sss 212 8 3 3 Certifications Registrations Declarations wxxrrrrrrnnnvrrrrnnnnnnnnnnnnnrrrrnnnnnnnnnnnn 213 8 3 4 Product Regulatory Compliance Markings e 213 8 4 Electromagnetic Compatibility Notices ooooonnonccnncccnnnnnnncccononcccnnnnnnnnnnnana no nnnos 214 8 4 1 FOG USA ae 214 8 4 2 Industry Canada ICES 003 us eee reden 214 8 4 3 Europe CE Declaration of
150. ements 20 0 RU ov NU 210 0 110 Ref 8 27 4 3 400 0 240 0 100 0 325 0 15 77 Jl i Figure 27 Power Harness Specification Drawing Notes ALL DIMENSIONS ARE IN MM ALL TOLERANCES ARE 10 MM 0 MM INSTALL 1 TIE WRAP WITHIN 12MM OF THE PSU CAGE MARK REFERENCE DESIGNATOR ON EACH CONNECTOR TIE WRAP EACH HARNESS AT APPROX MID POINT TIE WRAP P1 WITH 2 TIES AT APPROXIMATELY 15M SPACING P4 HARNESS IS ARESERVED FOR THE FUTURE ONLY NO PLEMENTATION IS NEEDED CURRENTLY TIE WRAP P1 AND P2 TOGETHER AT THIS POINT OMNOA PWN D gt Revision 1 0 203 C78844 002 Design and Environmental Specifications P1 Main Power Connector Connector housing 24 pin Molex Mini Fit Jr 39 01 2245 or equivalent Contact Molex Mini Fit HCS female crimp 44476 or equivalent Intel Server Board SE7520JR2 Table 113 P1 Main Power Connector 18 AWG Color Pin Signal 3 COM e ewe COM PWR OK 12V3 Yellow Blue Stripe 12V3 Yellow Blue Stripe Notes 5V Remote Sense Double Crimped into pin 4 3 3V Locate Sense Double Crimped into pin 2 P2 Processor Power Connector Connector housing 8 pin Molex 39 01 2085 or equivalent 204 Contact Molex 44476 1111 or equivalent 3 3 VDC 12 VDC COM COM Reserved 5 VDC 5 VDC 5 VDC COM Signal
151. ent eiu tant veces 124 Figure 23 Power Supply Control Signals 5 1 e aec oreet gebeten er de Pe a ites died due 125 Figure 24 Location of Diagnostic LEDs on Baseboard sssssseeee 168 Figure 25 34 Pin SSI Compliant Control Panel Header ssee 192 Figure 26 System Configuration J1H2 Jumper Block Settings ssssssesesssse 201 Figure 27 Power Harness Specification Drawing sene 203 Figure 29 Ourput Voltage Timing cursis 210 Figure 29 Turn On Off Timing Power Supply SigNalS ooooccnnnnncnoncccnnncccccnnnanacancnnnoncnnnnannnos 211 Revision 1 0 xiii C78844 002 List of Tables Intel Server Board SE7520JR2 List of Tables Table 1 Baseboard Layout Reference 22 cccccceceeesesenseneeeeeteneeseeceteeeeeeeeeeseeeneeneeeeeeeeeseneneseatie 24 Table 2 Processor Support Matrix esses nennen nennen 28 Table 3 Supported DDR 266 DIMM Populations ccccccccccccononcnnonccccnnococononennnnnonononencnnnnononnn 39 Table 4 Supported DDR 333 DIMM Populations ccccccccccccononcnnnnccnncnnnonononennnnnonononeneninnononnn 39 Table 5 Supported DDR2 400 DIMM Populations cccccccccccoccncncnncnnococnononononnnnnonononencninneninnn 40 Table 6 Memory Monitoring Support by Server Management Level uuususuuus 41 Table 7 PCI Bus Segment Characteristics tenes eenemen eren nnn ni
152. erated No power control action is taken In the case of simultaneous button presses the Power Button action takes priority over all other buttons Due to the routing of the de bounced Power Button signal to the chipset the power signal action overrides the action of the other switch signals 5 3 5 5 3 Reset Button An assertion of the control panel Reset signal to the mBMC causes the mBMC to start the reset and reboot process This is immediate and without the cooperation of any software or operating system running on the system The reset button is a momentary contact button on the control panel Its signal is routed through the control panel connector to the mBMC which monitors and de bounces it If Secure Mode is enabled or if the button is forced protected the reset button does not reset the system but instead a Platform Security Violation Attempt event message is generated 5 3 5 5 4 Diagnostic Interrupt Button Control Panel NMI As stated in the PMI 1 5 Specification a diagnostic interrupt is a non maskable interrupt or signal for generating diagnostic traces and core dumps from the operating system The mBMC generates NMIs and can be used for an OEM specific diagnostic control panel interface The diagnostic interrupt button is connected to the mBMC through the control panel connector A diagnostic interrupt button press causes the mBMC to generate a SEL entry that will trigger an NMI PEF OEM action The event attributes
153. erying the Device host and or device Table 23 Mixed P ATA S ATA Configuration with only Primary P ATA Options Help Text Mixed P ATA S ATA First ATA P ATA M S Configure this channel to P ATA or S ATA Defines the S ATA Channel S ATA M S P ATA Parallel ATA Primary channel device for this channel If the S ATA Serial ATA Second ATA is assigned S ATA this option reverts to P ATA Second ATA P ATA M S Configure this channel to P ATA or S ATA Defines the S ATA Channel S ATA M S P ATA Parallel ATA Primary channel device for this channel If the First ATA is assigned S ATA this option reverts to P ATA 3rd amp 4th ATA A1 3 M A2 4 M Configure this channel to P ATA or S ATA Display only If the Channels A1 A M A2 39M P ATA Parallel ATA Primary channel First ATA or Second ATA is assigned S None S ATA Serial ATA ATA this option reverts to None S ATA Serial ATA Revision 1 0 89 C78844 002 System BIOS Intel Server Board SE7520JR2 Table 24 BIOS Setup IDE Device Configuration Sub menu Selections Display S M A R T support Type Not Installed Select the type of device connected The Auto setting should work in Auto to the system most cases CDROM ARMD LBA Large Mode Disabled Disabled Disables LBA Mode The Auto setting should work in Auto Auto Enabled LBA Mode if the most cases device supports it and the device is not already formatted with LBA Mode disabled Block
154. ess space from addresses 0100000h to FFFFFFFh as shown in the following figure PCI memory space can be remapped to top of memory TOM 64GB Extended Intel E7520 chipset region Top Of Memory TOM FFFFFFFFh FFE00000h PCI Memory Space FECOFFFFh FECO00000h Top of Low Memory TOLM Depends on installed DIMMs 512KB Extended System Management RAM 16MB Optional Fixed Memory 15MB Main Memory Address Region 100000h Figure 16 Extended Memory Map Revision 1 0 73 C78844 002 Functional Architecture Intel Server Board SE7520JR2 3 5 1 2 1 Main Memory All installed memory greater than 1MB is mapped to local main memory up to 8GB of physical memory Memory between 1MB to 15MB is considered to be standard ISA extended memory 1MB of memory starting at 15MB can be optionally mapped to the PCI bus memory space The remainder of this space up to 8GB is always mapped to main memory unless TBSG SMM is used which is just under TOLM The range can be from 128KB till 1MB 1MB depends on the BIOS setting C SMRAM is used which limits the top of memory to 256MB The BIOS occupies 512KB for the 32 bit SMI handler 3 5 1 2 2 PCI Memory Space Memory addresses below the 4GB range are mapped to the PCI bus This region is divided into three sections High BIOS APIC configuration space and general purpose PCI memory The General purpose PCI memory area is typically used memory mapped I O to PCI devices The memory address space f
155. evice Bit 7 1 select a specific register in the configuration space of the selected device or function on the bus 3 6 Clock Generation and Distribution All buses on the baseboard operate using synchronous clocks Clock synthesizer driver circuitry on the baseboard generates clock frequencies and voltage levels as required including the following e 200MHz differential clock at 0 7V logic levels For Processor 0 Processor 1 Debug Port and MCH e 100MHz differential clock at 0 7V logic levels on CK409B For DB800 clock buffer e 100MHz differential clock at 0 7 Vlogic levels on DB800 For PCI Express Device it is the MCH PXH and full length riser which includes x4 PCI Express Slot For SATA it is the ICH5 R e 66MHz at 3 3V logic levels For MCH and ICH5 R e 48MHz at 3 3V logic levels For ICH5 R and SIO e 33MHz at 3 3V logic levels For ICH5 R Video BMC and SIO e 14 318MHz at 2 5V logic levels For ICH5 R and video e 10Mhz at 5V logic levels For mBMC The PCI X slot speed on the full length riser card and on the low profile riser card is determined by the riser card in use Revision 1 0 79 C78844 002 System BIOS 4 System BIOS Intel Server Board SE7520JR2 The BIOS is implemented as firmware that resides in the Flash ROM It provides hardware specific initialization algorithms and standard PC compatible basic input output I O services and standard Intel Server Board features The Flash ROM
156. f and the BIOS has not initialized the chipset Non ACPI System power is on but the BIOS has not yet initialized the chipset 128 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Platform Management 5 3 5 4 2 Fault Status LED The following table shows mapping of sensors faults to the LED state Table 50 Fault Status LED Color Condition When Ea Solid System ready Blink System ready but degraded CPU disabled Aber Solid Critical failure critical fan voltage or temperature state Blink Non critical failure non critical fan voltage or temperature state Off Solid System not ready POST error NMI event CPU or terminator missing Critical Condition Any critical or non recoverable threshold crossing associated with the following events e Temperature voltage or fan critical threshold crossing e Critical Event Logging errors including System Memory Uncorrectable ECC errors and FSB Bus errors Non Critical Condition e Temperature voltage or fan non critical threshold crossing e Chassis intrusion Degraded Condition e One or more processors are disabled by Fault Resilient Boot FRB 5 3 5 4 3 Chassis ID LED The Chassis ID LED provides a visual indication of a system being serviced The state of the Chassis ID LED is toggled by the chassis ID button or it can be controlled by the Chassis Identify command Table 51 Chassis ID LED Color Condition
157. form Management Intel Server Board SE7520JR2 e Platform Event Filtering PEF e Keyboard Controller Style KCS IPMI System Interface Professional and Advanced systems only e SMBus IPMI System Interface On board Platform Instrumentation systems only e Intelligent Chassis Management Bus ICMB support Professional and Advanced systems only e Remote Boot Control e Local and Remote Power On Off Reset Control e Local and Remote Diagnostic Interrupt NMI Control e Fault Resilient Booting e Control Panel LED Control e Platform Management Interrupt Routing Professional and Advanced systems only e Power Distribution Board PDB monitoring Professional and Advanced systems only e Updateable BMC Firmware e System Management Power Control including providing Sleep Wake and power push button interfaces e Platform Event Filtering PEF e Baseboard Fan Speed Control and Failure Monitoring e Speaker Beep Capability used to indicate conditions such as FRB failure Professional and Advanced systems only e Baseboard FRU Information interface e Diagnostic Interrupt Control Panel NMI Handling e SMI NMI status monitor Professional and Advanced systems only e System interface to the IPMB via System Interface Ports Professional and Advanced systems only e System interface to the PCI SMBus via System Interface Ports Professional and Advanced systems only e Secure Mode Control front panel lock unlock initi
158. function and speaker tone The 14 31818 MHz oscillator input provides the clock source for these three counters The ICH5 R provides an ISA compatible Programmable Interrupt Controller PIC that incorporates the functionality of two 82C59 interrupt controllers The two interrupt controllers are cascaded so 14 external and two internal interrupts are possible In addition the ICH5 R supports a serial interrupt scheme All of the registers in these modules can be read and restored This is required to save and restore the system state after power has been removed and restored to the platform Revision 1 0 35 C78844 002 Functional Architecture Intel Server Board SE7520JR2 3 2 3 6 Advanced Programmable Interrupt Controller APIC In addition to the standard ISA compatible PIC described in the previous section the ICH5 R incorporates the Advanced Programmable Interrupt Controller APIC 3 2 3 7 Universal Serial Bus USB Controller The ICH5 R contains an Enhanced Host Controller Interface EHCI for Universal Serial Bus Revision 1 0 compliant host controller that supports USB high speed signaling The high speed USB 2 0 allows data transfers up to 480 Mb s which is 40 times faster than full speed USB The ICH5 R also contains four Universal Host Controller Interface UHCI controllers that support USB full speed and low speed signaling On the Server Board SE7520JR2 the ICH5 R provides six USB 2 0 ports All six ports are high speed f
159. g register per DIMM to maintain a history of error occurrence and a programmable register to hold the fail over error threshold level The operational model is straightforward if the fail over threshold register is set to a non zero value the feature is enabled and if the count of errors on any DIMM exceeds that value fail over will commence The tracking registers themselves are implemented as leaky buckets such that they do not contain an absolute cumulative count of all errors since power on rather they contain an aggregate count of the number of errors received over a running time period The drip rate of the bucket is selectable by software so it is possible to set the threshold to a value that will never be reached by a healthy memory subsystem experiencing the rate of errors expected for the size and type of memory devices in use The fail over mechanism is slightly more complex Once fail over has been initiated the MCH must execute every write twice once to the primary DIMM and once to the spare The MCH will also begin tracking the progress of its built in memory scrub engine Once the scrub engine has covered every location in the primary DIMM the duplicate write function will have copied every data location to the spare At that point the MCH can switch the spare into primary use and take the failing DIMM off line Note that this entire mechanism requires no software support once it has been programmed and enab
160. g through Dual Address Cycles DAC Provides a theoretical 1066 Mbytes s zero wait state transfer rate Complies with the PCI Local Bus Specification Revision 2 2 Complies with the PCI X Addendum to the PCI Local Bus Specification Revision 1 0a Complies with the PCI Power Management Interface Specification Revision 1 1 Complies with the PC2001 System Design Guide Offers unmatched performance through the Fusion MPT architecture Provides high throughput and low CPU utilization to off load the host processor Presents a single electrical load to the PCI Bus True PCI Multifunction Device Uses SCSI Interrupt Steering Logic SISL to provide alternate interrupt routing for RAID applications Revision 1 0 59 C78844 002 Functional Architecture Intel Server Board SE7520JR2 e Reduces Interrupt Service Routine ISR overhead with interrupt coalescing e Supports 32 bit or 64 bit data bursts with variable burst lengths e Supports the PCI Cache Line Size register e Supports the PCI Memory Write and Invalidate Memory Read Line and Memory Read Multiple commands e Supports the PCI X Memory Read Dword Split Completion Memory Read Block and Memory Write Block commands e Supports up to 8 PCI X outstanding split transactions e Supports Message Signaled Interrupts MSI 3 4 4 2 Zero Channel RAID The Server Board SE7520JR2 has support for Zero Channel RAID ZCR which follows the RUBI2 standard It will not have support for zero channel RAID
161. h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh 0040h 0043h 0044h 004Fh 0050h 0053F 0054h 005Fh 0060h 0064h 0061h 0063h 0065h 0067h 0070h 0072h 0074h 0076h NMI Mask bit 7 amp RTC address bits 6 0 76 Aliased from 0020h 0021h Interrupt Controller 1 Aliased from 0020h 0021h Interrupt Controller 1 Aliased from 0020h 0021h Interrupt Controller 1 Aliased from 0020h 0021h Programmable Timers Keyboard Controller Keyboard chip select from 87417 NMI Status amp Control Register NMI Status amp Control Register NMI Status amp Control Register NMI Status amp Control Register NMI Mask bit 7 amp RTC address bits 6 0 PP NMI Mask bit 7 amp RTC address bits 6 0 Aliased from 0070h NMI Mask bit 7 amp RTC address bits 6 0 Aliased from 0070h Aliased from 0070h Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture Address es Resource Notes 0090h 0091h DMA Low Page Register aliased 0092h System Control Port A PC AT control Port this port not aliased in DMA range 0093h 009Fh DMA Low Page Register aliased 0094h Video Display Controller O00AO0h 00A1h Interrupt Controller 2 S 00A4h 00A5h Interrupt Controller 2 aliased A 00A8h
162. hange when using either the Professional Edition or Advanced Edition Intel Management Modules Functional changes when either of these two options are used are described in a separate document 2U Riser Card Configuration Option 3 100 66 PCI X BEE BEE am A 1U Riser Card Configuration Option 1 100 66 PCI X Dual GBe 10 10 1000 Intel 82546GB Low Profile ior m Channel A 3414 2A M 1A Arr e 2 PCI X Controller Hub Intel E7520 DDR 2 400 MHz LSI 53C1030 Memo or PXH ry Uttra320 Controller Hub DDR 266 333 MHz Channel B r HL 15 f 8 bit 266 MB s Full Height Riser Slot ys u ee ED A BD Wm 2U Riser Card configuration Options SATA 150 Option 1 3 100 66 PCI X Passive SAW RAID 1 0 ICH5 R I Option 2 1 100 2 133 PCI X Active I VO Controller Option 3 1 100 PCLX 2 PCLE x4 a 1U Riser Card Configuration Options OO Option 1 1 100 133 PCI X i Option 2 1 PCI E x8 a ean ae a dl ATIRage xL 13233 PCI SME Video 128 MB s LPC Management Peripheral SMBus a O keyboard Si 7 National d e cr e cr er e Q Serial Port Semiconductor d Intel Management Module Options I H PC87427 Option 1 Intel Management Module Professional BIOS Super l O Option 2 Intel Managment Module Advanced i Figure 3 Server Board SE7520JR2 Block Diagram 26 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Archite
163. hanisms under configuration control The scrub hardware will also execute demand scrub writes when correctable errors are encountered during normal operation on demand reads rather than scrub initiated reads This functionality provides incremental protection against time based deterioration of soft memory errors from correctable to uncorrectable Using this method a 16GB system can be completely scrubbed in less than one day The effect of the scrub writes do not cause any noticeable degradation to memory bandwidth although they will cause a greater latency for that one very infrequent read that is delayed due to the scrub write cycle Note that an uncorrectable error encountered by the memory scrub engine is a speculative error This designation is applied because no system agent has specifically requested use of the corrupt data and no real error condition exists in the system until that occurs It is possible that the error resides in an unmodified page of memory that will be simply dropped on a swap back to disk Were that to occur the speculative error would simply vanish from the system undetected without adverse consequences 3 3 6 3 Retry on Uncorrectable Error The Intel E7520 MCH includes specialized hardware to resubmit a memory read request upon detection of an uncorrectable error When a demand fetch as opposed to a scrub of memory encounters an uncorrectable error as determined by the enabled ECC algorithm th
164. hannel and the PCI PCI X interface These processors implement the LSI Logic Fusion MPT architecture a multithreaded I O algorithm that supports data transfers between the host system and SCSI devices with minimal host processor intervention Fusion MPT technology provides an efficient architecture that solves the protocol overhead problems of previous intelligent and non intelligent adapter designs LVDlink technology is the LSI Logic implementation of Low Voltage Differential LVD SCSI LVDlink transceivers allow the LSI53C1030 to perform either Single Ended SE or LVD transfers The LSI 53C1030 SCSI controller implements a regular SCSI solution or a RAID On MotherBoard ROMB solution This RAID functionality is included in the LSI option rom and allows the user to select either Integrated Mirroring IME or Integrated Striping IS RAID mode The system BIOS provides a setup option to allow the user to select one of these two modes The LSI Logic BIOS Configuration Utility or the IM DOS Configuration Utility is used to configure the IME and IS firmware attributes Using the LSI Logic BIOS and drivers adds support of physical device recognition for the purpose of Domain Validation and Ultra320 SCSI expander configuration Host based status software monitors the state of the mirrored drives and reports error conditions as they arise 3 4 4 1 1 53C1030 Summary of Features The Ultra320 SCSI features for the LSI53C1030 include e Double transi
165. he capability of correcting specific errata through the loading of an Intel supplied data block i e microcode update The BIOS is responsible for storing the update in non volatile memory and loading it into each processor during POST The BIOS allows a number of microcode updates to be stored in the flash limited by the amount of free space available The BIOS supports variable size microcode updates The BIOS verifies the signature prior to storing the update in the flash 3 1 6 8 Processor Cache The BIOS enables all levels of processor cache as early as possible during POST There are no user options to modify the cache configuration size or policies The largest and highest level cache detected is reported in BIOS Setup 3 1 6 9 Hyper Threading Technology Intel Xeon processors support Hyper Threading Technology The BIOS detects processors that support this feature and enables the feature during POST BIOS Setup provides an option to selectively enable or disable this feature The default behavior is Enabled The BIOS creates additional entries in the ACPI MP tables to describe the virtual processors The SMBIOS Type 4 structure shows only the physical processors installed It does not describe the virtual processors because some operating systems are not able to efficiently utilize the Hyper Threading Technology 3 1 6 10 Intel SpeedStep Technology Intel Xeon processors support the Geyserville3 GV3 whether Ge
166. he following algorithm BIOS configures the memory controller of the MCH to run in either dual channel mode or single channel mode 1 If 1 or more fully populated DIMM banks are detected the memory controller is set to dual channel mode Otherwise go to step 2 2 If DIMM 1A is present set memory controller to single channel mode A Otherwise go to step 3 3 If Channel 1B DIMM is present set memory controller to single channel mode B Otherwise generate a memory configuration error DDR 266 amp DDR 333 DIMM population rules are as follows 1 DIMM banks must be populated in order starting with the slots furthest from MCH 2 Single rank DIMMs must be populated before dual rank DIMMs 3 A maximum of four DIMMs can be populated when all four DIMMs are dual rank DDR 333 DIMMs DDR2 400 DIMM population rules are as follows 1 DIMMs banks must be populated in order starting with the slots furthest from MCH 2 Dual rank DIMMs are populated before single rank DIMMs 3 A maximum of four DIMMs can be populated when all four DIMMs are dual rank DDR2 400 DIMMs The following tables show the supported memory configurations e s r single rank e d r dual rank e E Empty Table 3 Supported DDR 266 DIMM Populations MCH Bank 3 DIMMs 3A 3B Bank 2 DIMMs 2A 2B Bank 1 DIMMs 1A 1B S R S R S R E S R S R E E S R D R D R D R E D R D R E E D R D R S R S R
167. hey are used on the Server Board SE7520JR2 Later sections in this chapter provide more detail on the implementation of the sub systems 3 2 1 Memory Controller Hub MCH The MCH integrates four functions into a single 1077 ball FC BGA package e Front Side Bus e Memory Controller e PCI Express Controller e Hub Link Interface 3 2 1 1 Front Side Bus FSB The E7520 MCH supports either single or dual processor configurations using 800MHz FSB Intel Xeon processors The MCH supports a base system bus frequency of 200 MHz The address and request interface is double pumped to 400 MHz while the 64 bit data interface parity is quad pumped to 800 MHz This provides a matched system bus address and data bandwidths of 6 4 GB s 3 2 1 2 MCH Memory Sub System Overview The MCH provides an integrated memory controller for direct connection to two channels of registered DDR 266 DDR 333 or DDR2 400 memory stacked or unstacked Peak theoretical memory data bandwidth using DDR266 technology is 4 26 GB s and 5 33 GB S for DDR333 technology For DDR2 400 technology this increases to 6 4 GB s Several RASUM Reliability Availability Serviceability Usability and Manageability features are provided by the E7520 MCH memory interface e Memory mirroring allows two copies of all data in the memory subsystem to be maintained one on each channel e DIMM sparing allows one DIMM per channel to be held in reserve and brought on line if another DIMM
168. hree additional power related connectors one SSI compliant 2x4 pin power connector J4J1 providing support for additional 12V one SSI compliant 1x5 pin connector J1G1 providing IC monitoring of the power supply and one 1x2 pin IDE power connector U2E1 providing power to support IDE flash devices The following tables define their pin outs Table 81 Power Connector Pin out Pin Signal Color Pin Signal Color 1 3 3Vdc Orange 13 3 3Vdc Orange 2 3 3Vdc Orange 14 12Vdc Blue 3 GND Black 15 GND Black 4 5Vdc Red 16 PS_ONF Green 5 GND Black 17 GND Black 6 5Vdc Red 18 GND Black 7 GND Black 19 GND Black 8 PWR_OK Gray 20 RSVD_ 5V White 9 5VSB Purple 21 5Vdc Red 10 12Vdc Yellow 22 5Vdc Red 11 12Vdc Yellow 23 5Vdc Red 12 3 3Vdc Orange 24 GND Black Table 82 12V Power Connector J4J1 CI 4 PONDER TG LIU NET fs Sm WA 7 me ve o Revision 1 0 175 C78844 002 Connectors and Jumper Blocks Intel Server Board SE7520JR2 Table 83 Power Supply Signal Connector J1G1 Color 1 5VSB_SCL PS ALTERI Notused Red Table 84 IDE Power Connector Pinout U2E1 7 2 Riser Slots The baseboard provides two riser slots one providing PCI X signals to a riser capable of supporting Low Profile add in cards and the other implementing Intel Adaptive Slot Technology providing both PCI X and PCI Express signals to risers capable of su
169. ialize the CPU s before boot which includes the programming of the MTRR s A8 A OFF R OFF Prepare CPU for operating system boot including final MTRR values A F R 6 Wait for user input at config display if needed AA A OFF A OFF Uninstall POST INT1Ch vector and INTO9h vector Deinitializes the ADM module AC A G R F End of POST initialization of chipset registers B1 R OF R A Save system context for ACPI 00 OFF OFF OFF OFF Passes control to OS Loader typically INT 19h 6 5 4 Bootblock Initialization Code Checkpoints The Bootblock initialization code sets up the chipset memory and other components before system memory is available The following table describes the type of checkpoints that may occur during the bootblock initialization portion of the BIOS Table 76 Bootblock Initialization Code Checkpoints Diagnostic LED Decoder Description Checkpoint G Green R Red A Amber MsB 188 Before D1 Early chipset initialization is done Early super I O initialization is done including RTC and keyboard controller NMI is disabled Perform keyboard controller BAT test Check if waking up from power D1 OFF A management suspend state Save power on CPUID value in scratch CMOS Go to flat mode with 4GB limit and GA20 enabled Verify the OFF bootblock checksum D2 G Disable CACHE before memory detection Execute full memory sizing module Verify that flat mode is enabled If memory si
170. ice to boot from Normal Operation Pins 1 2 Default Configuration either the upper or lower banks of the Force to lower bank Pins 2 3 flash device J7A1 Serial B Configures Pin 7 of the RJ45 Serial B DCD Select Pins 1 3 Configuration port to support either a DCD or DSR DSR Select Pins 2 4 Default signal J1H2 C QD Oi CMOS Clear B LO O BIOS Recovery Boot A O_O Password Clear 1 2 3 Figure 26 System Configuration J1H2 Jumper Block Settings Revision 1 0 201 C78844 002 Design and Environmental Specifications Intel Server Board SE7520JR2 8 Design and Environmental Specifications 8 1 Server Board SE7520JR2 Design Specification Operation of the Server Board SE7520JR2 at conditions beyond those shown in the following table may cause permanent damage to the system Exposure to absolute maximum rating conditions for extended periods may affect system reliability Table 112 Board Design Specifications Trapezoidal 50 g 170 inches sec Shock Packaged amp 40 bs to lt 80 bs Vibration Unpackaged 5 Hz to 500 Hz 3 13 g RMS random Note 1 Chassis design must provide proper airflow to avoid exceeding Intel Xeon processor maximum case temperature Disclaimer Note Intel Corporation server boards contain a number of high density VLSI and power delivery components that need adequate airflow to cool Intel ensures through its own chassis development and testing that when Intel server building blocks are use
171. ided for keyboard and mouse support Either port can support a mouse or keyboard Neither port will support Hot Plugging or connector insertion while the system is turned on The system can boot without a keyboard If present the BIOS detects the keyboard during POST and displays the message Keyboard Detected on the POST Screen 3 4 10 6 Wake up Control The Super I O contains functionality that allows various events to control the power on and power off the system 3 4 11 BIOS Flash The BIOS supports the Intel 28F320C3B flash part The flash part is a 4 MB flash ROM with 2MB programmable The flash ROM contains system initialization routines setup utility and runtime support routines The exact layout is subject to change as determined by Intel A 128 KB block is available for storing OEM code user binary and custom logos Revision 1 0 69 C78844 002 Functional Architecture Intel Server Board SE7520JR2 3 5 Configuration and Initialization This section describes the initial programming environment including address maps for memory and I O techniques and considerations for programming ASIC registers and hardware options configuration 3 5 1 Memory Space At the highest level the Intel Xeon processor address space is divided into four regions as shown in the following figure Each region contains the sub regions that are described in following sections Attributes can be independently assigned to regions and sub
172. idge The first PCI X segment P64 A supports the interface for the on board LSI 53C1030 Ultra320 SCSI controller in addition to supporting up to three PCI X add in cards from the full height PCI riser slot The second PCI X segment P64 B supports the interface to the on board Intel 82546GB dual port Gigabit network controller in addition to up to three PCI X add in cards from the low profile PCI riser slot 3 4 1 3 P64 Express Dual x4 PCI Bus Segment The full height riser slot supports both X4 and X8 PCI E type widths In a 2U system the baseboard supports two x4 PCI E slots In a 1U system the baseboard supports one x8 PCI E slot The BIOS performs link training with PCI E devices during boot and checks the resulting status If it detects that a port is not connected to a PCI E device it disables the port 3 4 1 4 PCI Riser Slots The Server Board SE7520JR2 has two riser slots capable of supporting riser cards for both 1U and 2U system configurations Because of board placement resulting in different pin orientations and expanded technology support associated with the full height riser the riser slots are proprietary and require different riser cards The low profile riser slot J5F1 utilizes a 202 pin connector It is capable of supporting up to three low profile PCI X add in cards depending on the riser card used The P64 B bus can support bus speeds of up to 100MHz with up to two PCI X 100MHz cards installed The bus speed w
173. ification String C78844 002 Build Date and time in MMDDYYYYHHMM format One digit non zero if any Separately Updateable Module has been updated Revision 1 0 Intel Server Board SE7520JR2 System BIOS As such the BIOS ID for this platform takes the following form e SE7520JR2 supporting DDR memory SE7520JR22 86B P 01 00 0002 081320031156 e SE7520JR2 supporting DDR2 memory SE7520JR23 86B P 01 00 0002 081320031156 4 2 Flash Architecture and Flash Update Utility The flash ROM contains system initialization routines the BIOS Setup Utility and runtime support routines The exact layout is subject to change as determined by Intel A 64 KB user block is available for user ROM code or custom logos The flash ROM also contains initialization code in compressed form for onboard peripherals like SCSI NIC and video controllers It also contains support for the rolling single boot BIOS update feature 4 3 BIOS Power On Self Test POST The BIOS Power On Self Test POST begins when the system is powered on During POST the BIOS initializes and tests various sub systems sets up all major system operating parameters and gives the opportunity for any optionally installed add in cards to execute setup code When complete and if no errors are encountered BIOS turns control of the system over to the installed operating system As video is initialized during POST the opportunity to view and alter the POST process is made availabl
174. ig Offset A Revision 1 0 147 C78844 002 Platform Management Sensor Slot Connector 21h Slot Connector 21h Slot Connector 21h Event Reading Event Offset Triggers Fault Status Asserted Device Installed Disabled Fault Status Asserted Device Installed Disabled Fault Status Asserted Device Installed Disabled 5 4 Wired For Management WFM Wired for Management WMF is an industry wide initiative that increases the overall manageability and reduces the total cost of ownership WFM allows a server to be managed over a network The system BIOS supports the SMBIOS to help higher level instrumentation software meet the WFM requirements Higher level software can use the information provided by SMBIOS to instrument the desktop management interface DMI that are specified in the WFM specification 5 5 Vital Product Data VPD Vital Product Data VDP is product specific data used for product and product component identification It is stored in non volatile memory and preserved through power cycles The VPD contains information such as Product Serial Number Product Model Number Manufacturer Identification etc Intel amp Server Board SE7520JR2 EventData Trig Offset Assert Readable Value Offsets Trig Offset Trig Offset The VPD is programmed during manufacturing A user can update certain user specific VPD information by using the Flash Update utility The BIOS uses this data
175. iled ProceSSOrs cc ccccceceeeesecccceeeeeeeeeeeeseecneeedeeeeeseeeesenanseeeeeens 151 6 1 6 Memory Error Handling in RAS Mode sese 152 6 1 7 Memory Error Handling in non RAS Mode sse 153 6 1 8 DIMM Enabling pP etel i rU a ES 154 6 1 9 Single bit ECC Error Throttling Prevention eene 154 6 2 Ero LOGIA re XE 155 6 2 1 1 POL BUS Error aaa 155 6 2 1 2 Processor Bus Error sssssssssssssee enne nennen eren 155 621 9 Memory Bus EMO uei eerta tee sebo ec ed inte E NS ERN eden 156 0 214 System Erit ETFOF ioo Sotto n eee etg oes thie anda tamer ton a ah ela deh n 156 6 2 1 5 Processor Fall ita cite eoe e atr ede a eer eme 156 6 2 1 6 Boot EVEN sire D cH eode eds 156 6 3 Error Messages and Error Codes eese nnne innen 156 6 3 1 POST Error Messages nenesie triti tecti pa 156 6 3 2 POST Error Codes x d d eee eee e eb dee eee DERE E e e dua 162 6 3 3 BIOS Generated POST Error Beep Codes ccecceecceeeeeeeeeeeeeeeeeeeeeeeeeeneeeneeees 165 6 3 4 Boot Block Error Beep Codes rannnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnsnnnsrnnsennnrnnsrnnsennsenne 166 6 3 5 BMC Generated Beep Codes Professional Advanced only 166 6 4 CheCckpolnits 4 545 AO 167 6 4 1 System ROM BIOS POST Task Test Point Port 80h Code 167 Revision 1 0 C78844 002 Table of Contents Intel Server Bo
176. ill drop to G6MHz when three PCI X 100MHz cards are installed or will match the card speed of the lowest speed card on the bus le If any of the add cards installed on the P64B bus 48 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture supports a maximum of 66MHz the entire bus will throttle down to 66MHz to match the supported frequency of that card When populating add in cards the add in cards must be installed starting with the slot furthest from the baseboard le When using a three slot riser a single PCI X add in card must be installed in the top PCI slot A second add in card must be installed in the middle slot and so on These population rules must be followed to maintain the signal integrity of the bus The full height riser slot implements Intel Adaptive Slot Technology This 280 pin connector is capable of supporting riser cards that meet either the PCI X or PCI Express technology specifications As a PCI X only bus using a baseboard with integrated SCSI and passive riser card the P64 A bus can support bus speeds of up to 100MHz with up to two PCI X 100MHz cards installed The bus speed will drop to 66MHz when three PCI X 100MHz cards are installed or will match the card speed of the lowest speed card on the bus le If any of the add cards installed on the P64A bus supports a maximum of 66MHz the entire bus will throttle down to 66MHz to match the supported frequency of that card When populating
177. indow The middle portion of the screen is reserved for either a splash screen or diagnostic screen On a graphics console the window is 640x384 On a text console the window is 80x20 In the BIOS Setup Utility The Quiet Boot option is used to select which of the two screens is displayed If Quiet Boot is set to Enabled a splash screen programmed into the BIOS is displayed hiding any POST progress information If the Quiet Boot option is Disabled all POST progress information will be displayed to the screen The factory default is to have the Quiet Boot option enabled displaying the Splash Screen However if during the POST process the lt ESC gt key is pressed while the Splash Screen is being displayed the view will change to the diagnostic screen for the current boot only 4 3 1 2 1 System Diagnostic Screen The diagnostic screen is the console where boot information options and detected hardware information are displayed 82 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 System BIOS The Static Information Display area presents the following information e Copyright message e BIOSID e Current processor configuration e Installed physical memory size 4 3 1 2 2 Quiet Boot OEM Splash Screen The BIOS implements Quiet Boot providing minimal startup display during BIOS POST System start up must only draw the end user s attention in the event of errors or when there is a need for user action By default the system m
178. ing processor are recorded into the system event log SEL The FRB 3 failure is recorded automatically by the BMC while the FRB2 FRB1 and AP failures are logged to the SEL by the BIOS In the case of an FRB2 failure some systems will log additional information into the OEM data byte fields of the SEL entry This additional data indicates the last POST task that was executed before the FRB2 timer expired This information may be useful for failure analysis The Sahalee BMC maintains failure history for each processor in non volatile storage This history is used to store a processor s track record Once a processor is marked failed it remains failed until the user forces the system to retest the processor by entering BIOS Setup and selecting the Processor Retest option The BIOS reminds the user about a previous processor failure during each boot cycle until all processors have been retested and successfully pass the FRB tests or AP initialization If all the processors are bad the system Revision 1 0 151 C78844 002 Error Reporting and Handling Intel Server Board SE7520JR2 does not alter the BSP and attempts to boot from the original BSP Error messages are displayed on the console and errors are logged in the event log of a processor failure If the user replaces a processor that has been marked bad by the system the system must be informed about this change by running BIOS Setup and selecting that processor to be retes
179. ing to detect and configure IDE ATAPI devices in POST 4 Master Hard Disk Error The IDE ATAPI device configured as Master in the 4th IDE controller could not be properly initialized by the BIOS This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST 4 Slave Hard Disk Error The IDE ATAPI device configured as Slave in the 4th IDE controller could not be properly initialized by the BIOS This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST 5 Master Hard Disk Error The IDE ATAPI device configured as Master in the 5th IDE controller could not be properly initialized by the BIOS This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST 5 Slave Hard Disk Error The IDE ATAPI device configured as Slave in the 5th IDE controller could not be properly initialized by the BIOS This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST 6 Master Hard Disk Error The IDE ATAPI device configured as Master in the 6th IDE controller could not be properly initialized by the BIOS This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST 6 Slave Hard Disk Error The IDE ATAPI device configured as Slave in the 6th IDE controller could not be proper
180. iolation As General Chassis Intrusion LAN Leash Lost Intrusion LAN Leash Lost POST error As C78844 002 Intel Server Board SE7520JR2 Sensor Sensor Name Number Critical Inerrupt Sensor Event Reading Type Sensor Specific 6Fh Sensor Specific 6Fh Sensor Type Critical Interrupt 13h Sensor Specific 6Fh Event Logging Disabled 10h Event Logging Disabled Session Audit OAh BB 1 2V Vtt BB 1 2V NIC Core BB 1 5V Sensor Specific 6Fh Session Audit 2Ah 10h 11h 12h 3h I SCSI Core BB Vbat BB Temp Front Panel Temp 32h Drive Backplane Temp Digital on age Discrete 05h 15h 17h 18h 19h 1Ah 1Bh 1Ch 30h h 35 Revision 1 0 eos nee u Il nr c nc a Temp Threshold doas x i aii nias Tem Threshold 01h p u nr c nc As amp De Analog Temp Threshold MN i j i adis Platform Management Readable Value Offsets Event Offset Triggers Assert Deassert As EventData Front Panel NMI Trig Offset Bus Error Uncorrectable ECC Trig Offset Correctable Memory Error Logging Disabled Trig Offset Log Area Reset Cleared Session Activation As defined Session by IPMI Deactivation R T R T R T R T R T R T R T R T R T R T R T R T Limit Not Exceeded Limit Exceeded 2 R T R T R T Ee se ea e ee ee eee Pe ee el eer 143 C78844 002 Platform Management Intel
181. ion BIOS updates are diverted to the secondary partition After the update is complete a notification flag is set During the subsequent boot following the BIOS update the system continues to attempt to boot from the primary BIOS partition On determining that a BIOS update occurred in the previous boot the system then attempts to boot from the new BIOS Ifa failure happens while booting to the new BIOS the specialized hardware on the system switches back to the primary BIOS partition thus affecting a Roll Back 4 5 1 Flash Update Utility Server platforms support a DOS based firmware update utility This utility loads a fresh copy of the BIOS into the flash ROM The BIOS update may affect the following items e The system BIOS including the recovery code setup utility and strings e Onboard video BIOS SCSI BIOS and other option ROMS for the devices embedded on the server board e OEM binary area e Microcode updates 4 5 1 1 Flash BIOS An afuXXX AMI Firmware Update utility such as afudos AFUWIN afulnx Or AFUEFT is required for a BIOS update 4 5 1 2 User Binary Area The baseboard includes an area in flash for implementation specific OEM add ons This OEM binary area can be updated as part of the system BIOS update or it can be updated independent of the system BIOS 4 5 1 3 Recovery Mode Three conditions can cause the system to enter recovery mode e Pressing a hot key e Setting the recovery
182. ion Revision 2 3 with support for 33 MHz PCI operations e ACPI power management logic support e Enhanced DMA controller interrupt controller and timer functions e Integrated IDE controller with support for Ultra ATA100 66 33 e Integrated SATA controller e USB host interface with support for eight USB ports four UHCI host controllers one EHCI high speed USB 2 0 host controller e System Management Bus SMBus Specification Version 2 0 with additional support for I C devices e Low Pin Count LPC interface e Firmware Hub FWH interface support Each function within the ICH5 R has its own set of configuration registers Once configured each appears to the system as a distinct hardware controller sharing the same PCI bus interface 3 2 3 1 PCI Interface The ICH5 R PCI interface provides a 33 MHz Revision 2 3 compliant implementation All PCI signals are 5 V tolerant except PME The ICH5 integrates a PCI arbiter that supports up to six external PCI bus masters in addition to the internal ICH5 requests On the Server Board SE7520JR2 this PCI interface is used to support on board PCI devices including the ATI video controller Super I O chip and hardware monitoring sub system 3 2 3 2 IDE Interface Bus Master Capability and Synchronous DMA Mode The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks and ATAPI devices Each IDE device can have independent timings The IDE interface suppor
183. ion 1 0 Intel Server Board SE7520JR2 Revision 1 0 Pins Signal Name LAN ACT BL PS I2C 5VSB SDA PS I2C 5VSB SCL FP CHASSIS INTRU LAN LINKA L SPB EN L SPB SOUT SPB CTS L SPB DCD L TEMP PWM R GND GND GND GND GND Connectors and Jumper Blocks Pin Signal Name 20 22 24 26 28 30 32 34 36 40 42 44 46 48 50 Table 93 Control Panel SSI Standard 34 Pin Header Pin out Signal Name Pin FP PWR LED L P5V 9 HDD LED ACT R FP PWR BTN L GND Reset Button GND FP SLP BTN L GND FP NMI BTN L P5V STBY FP ID LED L FP ID BTN L GND 2 4 6 Pin C78844 002 191 Connectors and Jumper Blocks Intel Server Board SE7520JR2 Control Panel Pinout O O Power LED O Cool Fault Oo o HDD LED Oo O System Fault Oo oO Power Buttof O O LANA Link 4 Oo oO Reset Button O O SMBus O O Sleep Button O o Intruder Oo oO LAN B Link NMI Oo oO ID LED 0 O O ID Button 970 O O Figure 25 34 Pin SSI Compliant Control Panel Header 7 5 I O Connectors 7 5 1 VGA Connector The following table details the pin out definition of the VGA connector Table 94 VGA Connector Pin out Pin SignalName GND CI e CI EMI 192 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Connectors and Jumper Blocks Signal Name Pin DDCDAT HSYNC horizontal sync VSYNC vertical sync DDCCLK 7 5 2 NIC Connectors The Server
184. ipset e Soft Shutdown 5h Chassis Control command This option generates a 200ms pulse of the chipset power button 5 2 3 External Interface to the mBMC The following figure shows the data control flow to and within the functional modules of the mBMC External interfaces namely the host system Lan On Motherboard LOM and peripherals interact with the mBMC through the corresponding interface modules Power supply control functions and control panel control functions are built into the mBMC The mBMC communicates with the internal modules using its private SMBus External devices and sensors interact with the mBMC using the peripheral SMBus LOM communicates through the LOM SMBus 122 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Platform Management SMBus Sensor Devices mBMC Front Panel j Ethernet Figure 21 External Interfaces to mBMC 5 3 mBMC Hardware Architecture The following figure shows an example of the internal functional modules of the mBMC in a block diagram The mBMC controls various server management functions such as the system power reset control a variety of types of sensor monitoring system initialization fault resilient booting FRB The memory subsystem consists of flash memory to hold the mBMC operation code firmware update code System Event Log SEL Sensor Data Record SDR repository and mBMC persistent data A private SMBus provides the mBMC with access to various sen
185. ired to boot the system Table 29 BIOS Setup PCI Configuration Sub menu Selections PCI Configuration Onboard Video Disabled Enable Disable on board VGA Enabled Controller Dual Monitor Video Disabled Select which graphics controller to use Grayed out if Onboard Enabled as the primary boot device Enabled Video is set to Disabled selects the on board device Onboard NIC 1 Left Disabled ee fem Ao eme ffs Enabled disabled Onboard NIC 2 Right Disabled MT ee Et Enabled disabled Onboard SCSI Disabled ee femmes Onboard SCSI ROM Disabled femmes Onboard SCSI Mode IM IME IM IME Integrated After OS installation with a IS Mirroring Integrated Mirroring selected SCSI RAID mode Enhanced only change this mode IS Integrated Striping selection if prepared to rebuild RAID array Changing the mode could Before changing modes back up damage current OS array data and delete existing arrays installation on RAID volume if any Otherwise loss of all data may Grayed out if device is ae disabled Grayed out if device is disabled Revision 1 0 93 C78844 002 System BIOS Intel Server Board SE7520JR2 Slot 1 Option ROM Disabled PCI X 64 133 O ES MEME Slot 2 Option ROM Disabled PCI X 64 133 Slot 3 Option ROM Disabled PCI X 64 133 Visible only when installed Enabled riser supports this slot Slot 4 Option ROM Disabled PCI X 64 133 Visible only when installed Enabled riser supports this slot Slot
186. ise cere a ERE FOX EXER XXE RR EXER ee E Eee Erde ka dae 208 Output voltage TIMIN arista pat tete corned att des 209 Eve ierat nme 210 Product Certification Markings eese 213 xvii C78844 002 List of Tables Intel Server Board SE7520JR2 lt This page intentionally left blank gt xviii Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Introduction 1 Introduction This Technical Product Specification TPS provides detail to the architecture and feature set of the Intel Server Board SE7520JR2 The target audience for this document is anyone wishing to obtain more in depth detail of the server board than what is generally made available in the board s Users Guide It is a technical document meant to assist people with understanding and learning more about the specific features of the board This is one of several technical documents available for this server board All of the functional sub systems that make up the board are described in this document However some low level detail of specific sub systems is not included Design level information for specific sub systems can be obtained by ordering the External Product Specification EPS for a given sub system The EPS documents available for this server board include the following e Intel Server Board SE7520JR2 BIOS EPS e Intel Server Board SE7520JR2 Baseboard Management Controller EPS e mini Baseboard Management Controller nBMC
187. ity Both channels can be disabled by using the BIOS Setup utility which is accessed during POST The 82546GB supports the following features e 64 bit PCI X Rev 1 0 master interface e Integrated IEEE 802 3 10Base T 100Base TX and 1000Base TX compatible PHY e IEEE 820 3ab auto negotiation support e Full duplex support at 10 Mbps 100Mbps and 1000 Mbps operation e Integrated UNDI ROM support e MDI MDI X and HWI support e Low power 3 3 V device 64 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture 3 4 8 1 NIC Connector and Status LEDs The 82546GB drives the two LEDs that are located on each network interface connector The link activity LED to the left of the connector indicates network connection when on and transmit receive activity when blinking The speed LED to the right of the connector indicates 1000Mbps operations when amber 100Mbps operations when green and 10 Mbps when off 3 4 9 USB 2 0 Support The USB controller functionality integrated into ICH5 R provides the baseboard with the interface for up to six USB 2 0 ports Two external connectors are located on the back edge of the baseboard Two 10 pin internal on board headers are provided which are each capable of supporting an additional two optional connectors Legacy USB The BIOS supports PS 2 emulation of USB 1 1 keyboards and mice During POST the BIOS initializes and configures the root hub ports and then searches for a keyboard and mo
188. kpoint G Green R Red A Amber msg LsB Check the validity of the recovery file configuration to the current FA A A i configuration of the flash part Make flash write enabled through chipset and OEM specific method Detect proper flash part Verify that the found flash part size equals the recovery file size CRA SA oa 4 8 Em emma fe be pi see Tk Tai TET The flash has been pe successfully Make flash write disabled Disable ATAPI hardware Restore CPUID value back into register Give control to F000 ROM at F000 FFFOh 6 5 6 DIM Code Checkpoints The Device Initialization Manager DIM module gets control at various times during BIOS POST to initialize different Buses The following table describes the main checkpoints where the DIM module is accessed Table 78 DIM Code Checkpoints checkpoint Description Initialize different buses and perform the following functions Reset Detect and Disable function 0 Function O disables all device nodes PCI devices and PnP ISA cards It also assigns PCI bus numbers Static Device Initialization function 1 Function 1 initializes all static devices that include manual configured onboard peripherals memory and I O decode windows in PCI PCI bridges and noncompliant PCI devices Static resources are also reserved Boot Output Device Initialization function 2 Function 2 searches for and initializes any PnP PCI or AGP video devices Initialize different buses
189. l Panel Reset Button pressed event is logged in the SEL 2 The Intel amp Local Control Panel with LCD is not supported with on board platform management Either an IMM Professional Editaion or Advanced Edition must be installed to support this chassis option Revision 1 0 127 C78844 002 Platform Management Intel Server Board SE7520JR2 e Combined power and reset button assertion If DC power is off an assertion of the PWBTIN while the RSTIN is asserted generates an OEM specific Control Panel event to PEF The event attributes are Sensor Type code 14h Button and Sensor Specific offset 07h This PEF action initiates a BIOS CMOS clear request to the system BIOS The user interface of the control panel consists of the following indicators e Power LED e Fault Status LED e Chassis ID LED For user input the standard control panel can provide the following buttons switches e Reset button e Power button e NMI SDI button e Chassis ID button e Chassis intrusion switch optional 5 3 5 4 Control Panel Indicators The mBMC is capable of supporting three control panel indicators Power LED Fault Status LED and Chassis ID LED The states of these indicators and how they relate to the mBMC chassis state are detailed below 5 3 5 4 1 Power LED The BIOS controls the control panel Power LED as described in the table below Table 49 SSI Power LED Operation Power Mode LED Description Non ACPI OFF System power is of
190. le 119 Table 120 Table 121 Table 122 Table 123 Table 124 Revision 1 0 List of Tables External USB Connector Pin out reiner datada cado 197 Internal 1x10 USB Connector Pin out J1F 1 cece ee eeeneneeeeeeeteeeeeeeneeeeeeeeeeees 198 Internal 2x5 USB Connector J1G1 sese nme enne 198 CPU1 CPU2 Fan Connector Pin out J5F2 J7F1 eeeeeeeess 199 Intel Server Chassis Fan Header Pin out J3K6 rrrrsrnnnnnrrnnnnnnnrnrrnnnnrrrrnnnnnnnnennn 199 3 Pin Fan Speed Controlled Fan Header J3K3 sessseesseess 200 Chassis Intrusion Header MA excesses tont roter tette tbt atout tete tla ottartedes 200 Hard Drive Activity LED Header J1A2 ssssseennem 200 Jumper Block Definitions 2srnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnennnnennernnsennsennernnsennsenne 201 Board Design Specifications ii ciel Ae ln ha f oiu ase eae E cede ee 202 P1 Main Power Conriector eerie ee riada 204 P2 Processor Power Connectors suos eb tei iia 204 P3 Baseboard Signal Cohrector iure ht Pd cedente ici 205 Peripheral Power Connectors occcccccccccccncnnncnnncnnnnnnnnnnnnnnnnnnnnnonnnonononnnonnnnnnnnncnnnnnos 205 P7 Hard Drive Power Connectors etae door li 205 Voltage Regulation Eimits 3 inde 207 Transient Load Requirements sss eem 207 Capacitve Loading CONOS it t Ee op ore Ei beet ol eu ei dtes 208 Ripple and No
191. le or disable reporting the PERR and SERR through NMI Disabling NMI for PERR and or SERR also disables logging of the corresponding event In the case of PERR the PCI bus master has the option to retry the offending transaction or to report it using SERR All other PCl related errors are reported by SERR All the PCI to PCI bridges are configured so that they generate a SERR on the primary interface whenever there is a SERR on the secondary side if SERR has been enabled through Setup The same is true for PERR 6 3 3 Processor Bus Error If the chipset supports ECC on the processor bus then the BIOS enables the error correction and detection capabilities of the processors by setting appropriate bits in the processor model specific register MSR and appropriate bits inside the chipset In the case of irrecoverable errors on the host processor bus proper execution of the asynchronous error handler usually SMI cannot be guaranteed and the handler cannot be relied upon to log such conditions The handler will record the error to the SEL only if the system has not experienced a catastrophic failure that compromises the integrity of the handler Revision 1 0 155 C78844 002 Error Reporting and Handling Intel Server Board SE7520JR2 6 3 4 Memory Bus Error The hardware is programmed to generate an SMI on single bit data errors in the memory array if ECC memory is installed The SMI handler records the error and the DIMM location to
192. led until the threshold detection has been triggered to request a data copy Hardware will detect the threshold initiating fail over and escalate the occurrence of that event as directed signal an SMI generate an interrupt or wait to be discovered via polling Whatever software routine responds to the threshold detection must select a victim DIMM in case multiple DIMMs have crossed the threshold prior to sparing invocation and initiate the memory copy Hardware will automatically isolate the failed DIMM once the copy has completed The data copy is accomplished by address aliasing within the DDR control interface thus it does not require reprogramming of the DRAM row boundary DRB registers nor does it require notification to the operating system that anything has occurred in memory The memory mirroring feature and DIMM sparing are exclusive of each other only one may be activated during initialization The selected feature must remain enabled until the next power cycle There is no provision in hardware to switch from one feature to the other without rebooting nor is there a provision to back out of a feature once enabled without a full reboot 44 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture 3 3 6 6 Memory Mirroring The memory mirroring feature is fundamentally a way for hardware to maintain two copies of all data in the memory subsystem such that a hardware failure or uncorrectable err
193. lit Option ROM The BIOS supports the split option ROM algorithm per the PCI 3 0 specification 3 4 3 Interrupt Routing The Server Board SE7520JR2 interrupt architecture accommodates both PC compatible PIC mode and APIC mode interrupts through use of the integrated I O APICs in the ICH5 R 3 4 3 1 Legacy Interrupt Routing For PC compatible mode the ICH5 R provides two 82C59 compatible interrupt controllers The two controllers are cascaded with interrupt levels 8 15 entering on level 2 of the primary interrupt controller standard PC configuration A single interrupt signal is presented to the processors to which only one processor will respond for servicing The ICH5 R contains configuration registers that define which interrupt source logically maps to I O APIC INTx pins 52 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture Both PCI and IRQ types of interrupts are handled by the ICH5 R The ICH5 R translates these to the APIC bus The numbers in the table below indicate the ICH5 R PCI interrupt input pin to which the associated device interrupt INTA INTB INTC INTD is connected The ICH5 R I O APIC exists on the I O APIC bus with the processors Table 9 PCI Interrupt Routing Sharing Interrupt INTA INT B INT C INT D Video ICH5R_PIRQB IDE RAID ICH5R_PIRQC NIC 10 100 Not used on ICH5R_PIRQD SE7520JR2 SIO ICH5R_SERIRQ Legacy IDE ICH5R_PIRQ14 Legacy IDE ICH5R_PIRQ
194. ly initialized by the BIOS This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST Primary Master Drive ATAPI Incompatible The IDE ATAPI device configured as Primary Master failed an ATAPI compatibility test This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST Primary Slave Drive ATAPI Incompatible The IDE ATAPI device configured as Primary Slave failed an ATAPI compatibility test This message is typically displayed when the BIOS is trying to detect and 158 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Error Reporting and Handling Message Displayed Description configure IDE ATAPI devices in POST Secondary Master Drive ATAPI Incompatible The IDE ATAPI device configured as Secondary Master failed an ATAPI compatibility test This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST Secondary Slave Drive ATAPI Incompatible The IDE ATAPI device configured as Secondary Slave failed an ATAPI compatibility test This message is typically displayed when the BIOS is trying to detect and configure IDE ATAPI devices in POST 3 Master Drive ATAPI Incompatible The IDE ATAPI device configured as Master in the gr IDE controller failed an ATAPI compatibility test This message is typically displayed when
195. m Memory Size N A N A Amount of physical memory detected System Time Use ENTER TAB or SHIFT Configures the system time on a 24 TAB to select a field hour clock Default is 00 00 00 Use or to configure system Time System Date DAY MM DD YYYY Use ENTER TAB or SHIFT Configures the system date TAB to select a field Default is Build Date Day of the Use or to configure system week is automatically calculated Date Language English Select the current Select the current default language French default language used used by BIOS German by the BIOS Italian Spanish 4 4 2 2 Advanced Menu Table 20 BIOS Setup Advanced Menu Options Advanced Settings WARNING Setting wrong values in below sections may cause system to malfunction Processor Configuration Configure processors Selects submenu IDE Configuration Configure the IDE device s Selects submenu pepe 86 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 System BIOS 4 4 2 2 1 Processor Configuration Sub menu Table 21 BIOS Setup Processor Configuration Sub menu Options Feature Options Help Text Configure Advanced Processor Settings Manufacturer Intel N A Displays processor manufacturer string Brand String N A N A Displays processor brand ID string Frequency N A N A Displays the calculated processor speed FSB Speed N A N A Displays the processor front side bus speed CPU 1 CPUID N A N A Displays the
196. m insuff res Non red Insuff res Intel Server Board SE7520JR2 Platform Management Event Readable Sensor Name sensor Sensor Type Reading Event Offset Assert Value EventData Triggers Deassert Offsets Number Type IERR Thermal Trip Sensor FRB1 FRB2 Processor 2 Processor FRB3 Specific Status 07h E 6Fh Config Error Presence Disabled Processor 1 Core Temp Threshold Trig Offset Processor 2 12v Voltage Threshold Processor 1 Tem Digital Transitioned to COh p Discrete Non Critical from As amp De Trig Offset Thermal Control 01h 07h OK Digital Transitioned to Discrete Non Critical from Trig Offset 07h OK Digital Transitioned to Discrete Non Critical from Trig Offset 07h OK Digital Transitioned to Discrete Non Critical from As amp De Trig Offset M 07h OK Processor 1 Vcc DOh s ee u nr c nc As 8 De Awes RT a Processor 2 Vcc D1h Hed U ROM u I nr c nc As amp De CPU Configuration D8h Processor Generic State Asserted As amp De Discrete R T A Error 07h 03h Fault Status Slot Connector Sensor Asserted Specific gt 21h 6Fh Device Installed Disabled Fault Status Sensor Slot Connector Specific Asserted 21h p Device Installed 6Fh Disabled Fault Status Slot Connector d Asserted 21h p Device Installed 6Fh Disabled Processor 2 Cth Temp Thermal Control 01h Processor 1 VRD C8h Temp Over Temp 01h Processor 2 VRD C9h Temp Over Temp 01h Trig Offset A Trig Offset A Tr
197. m management sub system to report false errors causing your platform to operate erratically Note It is highly recommended that you update your Server Board SE7520JR2 with the latest system software including the FRUSDR Update Utility These can be downloaded from the following Intel web site http support intel com support motherboards server se7520jr2 9 3 Clearing CMOS Depending on which System Management level is used on the server there are three possible methods that can be used to clear the system CMOS e System Configuration Jumper Block J1H2 A CMOS Clear Jumper Supported with all management levels e Control Panel CMOS clear sequence IMM Professional and Advanced system only e CMOS Clear state asserted via BMC CMOS Clear Options command allows remote clear operation Professional and Advanced systems Only 9 3 1 CMOS Clear Using J1H2 Jumper Block All three management levels support clearing the CMOS using by moving the CMOS Clear jumper of the System Config jumper block J1H2 A from the default position pins 1 2 to pin position 2 3 This method requires the following procedure to be followed The power be removed from the system The J1H2 jumper is moved The system is rebooted BIOS Setup options are saved System is powered down and AC is removed Jumper J1H2 is moved back to default position AC is restored System is rebooted SAP Ree YS 9 3 2 CMOS Clear using Control Panel In systems configured wi
198. matted Platform Event Traps PET to a specified alert destination The Alert over LAN feature is used to send either PET alerts or directed events to a remote system management application regardless of the state of the host s operating system LAN alerts may be sent over any of the LAN channels supported by a platform LAN alerts can be used by PEF to send out alerts to selected destination whenever an event matches an event filter table entry For more information on LAN alerts see the PMI specifications v1 5 5 3 19 mBMC Sensor Support The following tables are for the built in and the external sensors for the platform There is a management controller locator record as a built in SDR besides the given below Revision 1 0 137 C78844 002 Platform Management Intel Server Board SE7520JR2 mBMC sensors 01h 08h are internal sensors to the mBMC and are used for event generation only These sensors are not for use with the Get Sensor Reading IPMI command and may return an error when read Table 55 Platform Sensors for On Board Platform Instrumentation Event Readable Sensor Type Reading sl gg ke iab Value EventData Type 99 Offsets LAN Leash Mill Trig Offset Trig Offset Trig Offset Trig Offset Trig Offset Trig Offset Trig Offset Sensor Name Physical Sensor Security Specific LAN Leash Lost 05h 6Fh Physical Security Violation Platform Security Sensor Out of band Violation Pecific access pa
199. memory test Allocates memory for Extended BIOS Data Area from base memory 600 OFF R R OFF Initializes NUM LOCK status and programs the KBD typematic rate 75 OREA RE Al Initialize Int 13 and prepare for IPL detection 78 E A Re Initializes IPL devices controlled by BIOS and option ROMs 7A AAA Initializes remaining option ROMs pes DE Tox I ORE Generate and write contents of ESCD in NVRam 84 R G OFF OFF Log errors encountered during POST 8 R G oF G Display errors to the user and gets the user response for error He AAA Execute BIOS setup if needed requested Revision 1 0 169 C78844 002 Error Reporting and Handling Intel Server Board SE7520JR2 Description Checkpoint msg LsB 8D A 6 F Build ACPI tables if ACPI is supported 9 R OFF OFF R Late POST initialization of system management interrupt AD R OFF R OFF Check boot password if installed A1 R F Re Gu Clean up work needed before booting to operating system Takes care of runtime image preparation for different BIOS modules A2 OFF A OFF Fill the free area in FOOOh segment with OFFh Initializes the Microsoft IRQ Routing Table Prepares the runtime language module Disables the system configuration display if needed Program the peripheral parameters Enable Disable NMI as selected A4 R G R F Initialize runtime language module A7 G A G Displays the system configuration screen if enabled Init
200. mes active only when Admin and Time password is set Limited Full Access NO ACCESS prevents User access to the Setup Utility VIEW ONLY allows access to the Setup Utility but the fields can not be changed FULL allows any field to be changed Clear User Immediately clears the user Admin uses this option to clear Password password User password Admin password is used to enter setup is required This node is gray if Administrator password is not installed Fixed disk boot Disabled Enable Disable Boot Sector Virus sector protection Enabled Protection Password On Boot Disabled If enabled requires password This node is grayed out if a user Enabled entry before boot password is not installed Secure Mode Timer 1 minute Period of key PS 2 mouse This node is grayed out if a user 2 minutes inactivity specified for Secure password is not installed Mode to activate A password is required for Secure Mode to 10 minutes function Has no effect unless at 20 minutes least one password is enabled 5 minutes 60 minutes 120 minutes Secure Mode Hot Key assigned to invoke the secure This node is grayed out if a user Key Ctrl Alt mode feature Cannot be enabled password is not installed unless at least one password is enabled Can be disabled by entering a new key followed by a backspace or by entering delete 98 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 System BIOS Options HelpText
201. mode No mouse or keyboard input is accepted except the password Will write protect the User Password Admin Password Set feature master boot record of the to Normal in IDE hard drives only if the Setup system boots from a floppy The BIOS will also write protect the boot sector of the drive C if it is an IDE drive C78844 002 Video Blanking and Power Switch inhibit Floppy writes are re enabled Front panel Switches are re enabled PS 2 Keyboard and PS 2 mouse inputs are accepted System attempts to boot from drive A If the user enters correct password and drive A is bootable the system boots normally Front Panel switches are re enabled PS 2 Keyboard and PS 2 mouse inputs are accepted The System boots normally Boot sequence is determined by setup options Hard drive will behave normally Revision 1 0 Intel Server Board SE7520JR2 Administrator User Passwords and F2 Setup Usage Model Notes e Visible option string is active and changeable e Hidden option string is inactive and not visible e Shaded option string is gray out and view only There are three possible password scenarios Scenario 1 System BIOS Administrator Password Is Not Installed User Password Is Not Installed Login Type N A Set Admin Password visible Set User Password visible User Access Level Full shaded Clear User Password hidden User Access Level optio
202. n detection of the NMI 4 9 2 2 Power Switch Off to On The chipset may be configured to generate wakeup events for several different system events Wake on LAN PCI Power Management Interrupt PMI and Real Time Clock Alarm are examples of these events The operating system will program the wake sources before shutdown A transition from either source results in the mBMC starting the power up sequence Since the processors are not executing the BIOS does not participate in this sequence The hardware receives power good and reset from the mBMC and then transitions to an ON state 4 9 2 3 On to Off OS absent The SCI interrupt is masked The firmware polls the power button status bit in the ACPI hardware registers and sets the state of the machine in the chipset to the OFF state The mBMC monitors power state signals from the chipset and de asserts PS_PWR_ON to the power supply As a safety mechanism the mBMC automatically powers off the system in 4 5 seconds if the BIOS fails to service the request 4 9 2 4 On to Off OS present If an operating system is loaded the power button generates a request via SCI to the OS to shutdown the system The OS retains control of the system and OS policy determines what sleep state if any the system transitions into 4 9 2 5 On to Sleep ACPI If an operating system is loaded the sleep button generates a request via SCI to the OS to place the system in sleep mode The OS retains control
203. n the address of 080000h to O9FFFFh This area can be mapped to the PCI bus or main memory 3 5 1 1 3 Video or SMM Memory The 128 KB Graphics Adapter Memory region at 0A0000h to OBFFFFh is normally mapped to the VGA controller on the PCI bus This region is also the default region for SMM space 3 5 1 1 4 Add in Card BIOS and Buffer Area The 128 KB region between addresses OCO000h to ODFFFFh is divided into eight segments of 16 KB segments mapped to ISA memory space each with programmable attributes for expansion cards buffers Historically the 32 KB region from 0CO000h to OC7FFFh has contained the video BIOS location on the video card 3 5 1 1 5 Extended System BIOS This 64 KB region from OE0000h to OEFFFFh is divided into four blocks of 16 KB each and may be mapped with programmable attributes to map to either main memory or to the PCI bus Typically this area is used for RAM or ROM This region can also be used extended SMM space 3 5 1 1 6 System BIOS The 64 KB region from 0F0000h to OFFFFFh is treated as a single block By default this area is normally read write disabled with accesses forwarded to the PCI bus Through manipulation of read write attributes this region can be shadowed into main memory 72 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture 3 5 1 2 Extended Memory Extended memory is defined as all address space greater than 1MB Extended Memory region covers 8GB maximum of addr
204. n will be Full and Shaded as long as the administrator supervisor password is not installed Scenario 2 Administrator Password Is Installed User Password Is Installed Login Type Admin Supervisor Set Admin Password visible Set User Password visible User Access Level Full visible Clear User Password visible Login Type User Set Admin Password hidden Set User Password visible User Access Level Full Shaded Clear User Password hidden Scenario 3 Administrator Password Is Installed User Password Is Not Installed Login Type Supervisor Set Admin Password visible Revision 1 0 C78844 002 107 System BIOS Intel Server Board SE7520JR2 Set User Password visible User Access Level Full visible Clear User Password hidden Login Type lt Enter gt Set Admin Password hidden Set User Password visible User Access Level Full Shaded Clear User Password hidden 4 7 2 Password Clear Jumper If the user or administrator password s is lost or forgotten moving the password clear jumper board location J1H3 to the clear position will clear both passwords The BIOS determines if the password clear jumper is in the clear position during BIOS POST and clears any passwords if present The password clear jumper must be restored to its original position before a new password s can be set 4 8 Extensible Firmware In
205. nal is driven by the FMM to enable the CPU VRDs and allow the VRD power good chain to complete This signal can also be used to keep the system in reset for an extended time beyond what the chipset RST BTN N can provide FMM SCI N SCI event request If ACPI EC is supported by FMM this signal is used for ACPI interrupts ICH PWR BTN N FMM pass through of Front panel power button to chipset FMM SPKR N FMM uses this to create Beep Codes on the system audible alarm This signal is configured as an Open Drain buffer in the FMM and must be pulled up to 3 3V Standby on the motherboard FP NMI BTN N NMI Diagnostic interrupt from front panel Actual NMI generated by SMBUS command to mBMC FP SLP BTN N Front panel Sleep Button input if used FP ID BTN N Front panel ID button will cause the ID light to toggle SYS PWR GD 76 Signal from the end of the baseboard VRD Power good chain This signal should be the last VRD power good indication generated on the baseboard Usually this would be the signal feeding the Chipset Power OK input Used by FMM in conjunction with RST PWRGD PS to determine if all critical VRDs have successfully reached their nominal value CPU2 SKTOCC N 80 Indicates that a Processor is in the application processor socket CLK 32K RTC 81 This signal is used for Synchronized clock with system RTC FMM can synchronize own RTC with system RTC IPMI define synchronized method clock comes from the Chipset RTC function CPU1 SKTO
206. nce to radio and TV reception 8 4 2 Industry Canada ICES 003 Cet appareil num rique respecte les limites bruits radio lectriques applicables aux appareils num riques de Classe A prescrites dans la norme sur le mat riel brouilleur Apparelis Num riques NMB 003 dictee par le Ministre Canadian des Communications 214 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Design and Environmental Specifications This digital apparatus does not exceed the Class A limits for radio noise emissions from digital apparatus set out in the interference causing equipment standard entitled Digital Apparatus ICES 003 of the Canadian Department of Communications 8 4 3 Europe CE Declaration of Conformity This product has been tested in accordance too and complies with the Low Voltage Directive 73 23 EEC and EMC Directive 89 336 EEC The product has been marked with the CE Mark to illustrate its compliance 8 4 4 Taiwan Declaration of Conformity BSMI EH rede en EE TAREKAT AEREA ERAS ME KE The BSMI Certification Marking and EMC warning is located on the outside rear area of the product 8 4 5 Korean Compliance RRL 2219 JJ TA 1 71 2 Ol Que g rH TE 4 A 5 Xl EN ME English translation of the notice above on Type of Equipment Model Name On License and Product Certification No On RRL certificate Obtain certificate from local Intel representative Name of Certification Reci
207. nd SEL so System Management Software can poll and retrieve the present status of the platform The contents of the log can be retrieved post mortem in order provide failure analysis information to field service personnel It is also accessible by System Management Software such as Intel Server Management ISM running under the OS The management controller includes the ability to generate a selectable action such as a system power off or reset when a match occurs to one of a configurable set of events This capability is called Platform Event Filtering or PEF The management controller includes recovery control functions that allow local or remote software to request actions such as power on off power cycle and system hard resets plus an IPMI Watchdog Timer that can be used by BIOS andr run time management software as a way to detect software hangs The management controller provides out of band remote management interfaces providing access to the platform health event log and recovery control features via LAN all tiers IMM based systems also allow access via serial modem IPMB PCI SMBus and ICMB interfaces 118 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Platform Management These interfaces remain active on standby power providing a mechanism where the SEL SDR and recovery control features can be accessed even when the system is powered down Because the management controller operates independen
208. ng advantage of the dual independent SATA controllers integrated in the ICH5R There is no loss of PCI resources request grant pair or add in card slot Intel RAID Technology functionality requires the following items e CH5 R e Intel RAID Technology Option ROM must be on the platform Intel Application Accelerator RAID Edition drivers most recent revision e Two SATA hard disk drives Intel RAID Technology is not available in the following configurations e The SATA controller in compatible mode e Intel RAID Technology has been disabled 3 4 6 2 Intel RAID Technology Option ROM The Intel RAID Technology for SATA Option ROM provides a pre OS user interface for the Intel RAID Technology implementation and provides the ability for an Intel RAID Technology volume to be used as a boot disk as well as to detect any faults in the Intel RAID Technology volume s attached to the Intel RAID controller 3 4 7 Video Support The Server Board SE7520JR2 provides an ATI Rage XL PCI graphics accelerator along with 8 MB of video SDRAM and support circuitry for an embedded SVGA video subsystem The ATI Rage XL chip contains a SVGA video controller clock generator 2D and 3D engine and RAMDAC in a 272 pin PBGA One 2Mx32 SDRAM chip provides 8 MB of video memory The SVGA subsystem supports a variety of modes up to 1600 x 1200 resolution in 8 16 24 32 bpp modes under 2D and up to 1024 x 768 resolution in 8 16 24 32 bpp modes under 3D It also
209. ng the next reboot This policy can be overridden to prevent BSP from ever being disabled due to the FRB2 failure or a policy resulting in disabling the BSP after three consecutive FRB2 failures can be selected These options may be useful in systems that experience fatal errors during POST that are not indicative of a bad processor Selection of this policy should be considered an advanced feature and should only be modified by a qualified system administrator The mBMC does not support the option to disable the BSP 6 1 3 FRB3 BSP Reset Failures The BIOS and firmware provide a feature to guarantee that the system boots even if one or more processors fail during POST The Sahalee BMC contains two watchdog timers that can be configured to reset the system upon time out The first timer FRB3 starts counting down whenever the system comes out of hard reset With no Intel Management Module only one watchdog timer is present If the BSP successfully resets and begins executing the BIOS disables the FRB 3 timer in the BMC and the system continues executing POST If the timer expires because of the BSP s failure to fetch or execute BIOS code the Sahalee BMC resets the system and disables the failed processor The Sahalee BMC continues to change the bootstrap processor until the BIOS successfully disables the FRB3 timer The BMC generates beep codes on the system speaker if it fails to find a good processor It will continue to cycle until it finds
210. nout J1C1 FMC Signal Name Description Pin DVI_TX1M Green TMDS differential DVI output of graphics chip DVI_TXOM Blue TMDS differential DVI output of graphics chip DVI_TX1P Green TMDS differential DVI output of graphics chip DV KROM 8 TDS diferential DVI cock output of graphies eg 7 SIO MS DAT KVM mouse data from SIO SIO KB DAT KVM keyboard data from SIO DVI TXOP Blue TMDS differential DVI output of graphics chip 5 SIO MS CLK KVM mouse clock from SIO SIO KB CLK KVM keyboard clock from SIO PS2 MS DAT KVM passthrough mouse data from PS2 connector KVM passthrough mouse dala rom PS2 commedo CE RA FML_SDA 25 Fast Management Link Data In This signal is driven by the FML Slave i e NIC controller FML_MCL_I2CSCL 26 Fast Management Link Clock Out This signal is driven by the FML Master i e FMM When not configured as FML this signal is used as 12C clock 184 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Connectors and Jumper Blocks FMC Signal Name Description Pin FML_SINTEX 27 Fast Management Link Slave Interrupt Clock Extension This signal is driven by the FML Slave and has a dual usage Used as an Alert signal for the slave to notify master that data is ready to be read from slave Used as a clock Extension Stretching for the slave to indicate to the master to extend its low period of the clock FML_MDA_I2CSDA 28 Fast Management Link Data Out This signal is driven by the FML Master When n
211. nrnn senn nn 189 7 4 Control Panel COnmectors cccccceccceeceeeeceeeeeeeeeeeeeeeeeeeeeeeeeneeeeeeeneeseeeeeseeeseeeees 189 7 5 VO Connectors oor conte ett e RR RO YER E Taaa aa Aa a aE ETE dai 192 7 5 1 VGA Conecta pter nire int n TR ERR TER M CHEN and 192 7 5 2 NIC Connectors 5 ree eet ae iere eere re d er oes 193 7 5 3 SCSI CONNCCIOMS Ln 193 7 5 4 ATA 100 Gorinector i t re IT Ae eee 194 7 5 5 SATA CODneCIOrS ii davis ERI caos 195 7 5 6 Floppy Controller Connector eeessessssesssssssssssssssse ene enr 195 7 5 7 Serial Port ConnectotS aere aeter ae ara ea aaea Ea EE E R EEE 196 7 5 8 Keyboard and Mouse Connector essen ede nennen nennen 197 7 5 9 USB GCOnhector ie Ptr epo qe a ett Ernte Fats Me ia 197 7 6 Fan Headers ette et ten hn idet 198 7 1 Misc Headers and Connectors rrnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnsennnrnnsrnnsrnnsrensnensenn 200 7 7 1 Chassis Intrusion Header nieee aeea e E Eaa Ea eene 200 7 7 2 Hard Drive Activity LED Headel 2 cccccceeeeeceseeceeneceeeeeeeessceneeceeteeeeeeecenacees 200 7 8 JUMPEr BIOGkSs 5 ceteris a etd Ein RRE 201 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Table of Contents 8 Design and Environmental SpecificationS rrrrrnnnnnnnnnnnnvnnnnnnnnnnnnnnnnvnnnnnnnnnnnnnnnvnnnnnnnnnr 202 8 1 Server Board SE7520JR2 Design Specification sesesessss 202 8 2 Power Supply Requir
212. ns Feature Options Help Text Event Log Configuration Clear All Event Logs Disabled Setting this to Enabled will clear the System Enabled Event Log during the next boot Revision 1 0 101 C78844 002 System BIOS Intel Server Board SE7520JR2 Help Text BIOS Event Logging Disabled Select enabled to allow logging of BIOS Enables BIOS to log events Enabled events to the SEL This option controls BIOS events only Critical Event Logging Disabled If enabled BIOS will detect and log events for Enable SMM handlers to Enabled system critical errors Critical errors are fatal detect and log events to to system operation These errors include SEL PERR SERR ECC ECC Event Logging Disabled Enables or Disables ECC Event Logging Grayed out if Critical Event Enabled Logging option is disabled PCI Error Logging Disabled Enables or Disables PCI Error Logging Grayed out if Critical Event Enabled Logging option is disabled FSB Error Logging Disabled Enables or Disables Front Side Bus Error Grayed out if Critical Event Enabled Logging Logging option is disabled Hublink Error Logging Disabled Enables or Disables Hublink Error Logging Grayed out if Critical Event Enabled Logging option is disabled 4 4 2 6 Exit Menu Table 42 BIOS Setup Exit Menu Selections Options Help Text Exit Options Save Changes N A Exit system setup after saving the changes and Exit F10 key can be used for this operation Discard E
213. ns HelpTet Description Configure Nat42x Super IO Chipset Serial Port A Address Disabled Allows BIOS to Select Serial Port A Option that is used by other serial port 3F8 IRQ4 Base Addresses is hidden to prevent conflicting 2F8 IRQ3 settings 3E8 IRQ4 2E8 IRQ3 Serial Port B Address Disabled Allows BIOS to Select Serial Port B Option that is used by other serial port 3F8 IRQ4 Base Addresses is hidden to prevent conflicting 2F8 IRQ3 settings 3E8 IRQ4 2E8 IRQ3 Revision 1 0 91 C78844 002 System BIOS Intel Server Board SE7520JR2 4 4 2 2 5 USB Configuration Sub menu Table 27 BIOS Setup USB Configuration Sub menu Selections USB Configuration USB Devices N A N A List of USB Enabled devices detected by BIOS USB Function Disabled Enables USB HOST controllers When set to Enabled disabled other USB options are grayed out Legacy USB Support Disabled Enables support for legacy USB AUTO option Keyboard only disables legacy support if no USB devices are A connected If disabled USB Legacy Support will uto not be disabled until booting an OS Keyboard and Mouse Port 60 64 Emulation Disabled Enables I O port 60 64h emulation support Enabled This should be enabled for the complete USB keyboard legacy support for non USB aware OSes USB 2 0 Controller Disabled N A Enabled USB 2 0 Controller FullSpeed Configures the USB 2 0 controller in HiSpeed mode dico 480Mbps or FullSpeed 12Mbps U
214. ns at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them This document contains information on products in the design phase of development Do not finalize a design with this information Revised information will be published when the product is available Verify with your local sales office that you have the latest datasheet before finalizing a design The Intel Server Board SE7520JR2 may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the license The information in this manual is furnished for informational use only is subject to change without notice and should not be construed as a commitment by Intel Corporation Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document Except as permitted by such license no part of this document may be reproduced stored in a retrieval system or transmitted in
215. nstalled then BIOS can only notify the user that the BIST failed no processors will be disabled The BIST failure is displayed during POST and an error is logged to the SEL 6 1 2 FRB2 BSP POST Failures A second timer FRB2 is set to several minutes by BIOS and is designed to guarantee that the system completes POST The FRB2 timer is enabled just before the FRB3 timer is disabled to prevent any unprotected window of time Near the end of POST the BIOS disables the FRB2 timer If the system contains more than 1 GB of memory and the user chooses to test every DWORD of memory the watchdog timer is extended before the extended memory test starts because the memory test can exceed the timer duration The BIOS will also disable the watchdog timer before prompting the user for a boot password If the system hangs during POST before the BIOS disables the FRB2 timer the Sahalee BMC generates an asynchronous Revision 1 0 149 C78844 002 Error Reporting and Handling Intel Server Board SE7520JR2 system reset ASR The Sahalee BMC retains status bits that can be read by the BIOS later in the POST for the purpose of disabling the previously failing processor logging the appropriate event into the System Event Log SEL and displaying an appropriate error message to the user Options are provided by the BIOS to control the policy applied to FRB2 failures By default an FRB2 failure results in the failing processor being disabled duri
216. nt 5 3 12 Field Replaceable Unit FRU Inventory Devices An enterprise class system typically has FRU information for each major system board processor board memory board I O board etc The FRU data includes information such as serial number part number model and asset tag This information can be accessed in two ways through IPMI FRU commands or by using Master Write Read commands The mBMC provides FRU device command access to its own FRU device The mBMC implements the interface for logical FRU inventory devices as specified in the Intelligent Platform Management Interface Specification Version 1 5 This functionality provides commands used for accessing and managing the FRU inventory information associated with the mBMC FRU ID 0 These commands can be delivered over the Host and LAN channel interfaces 5 3 12 1 mBMC FRU Inventory Area Format The mBMC FRU inventory area format follows the Platform Management FRU Information Storage Definition See the Platform Management FRU Information Storage Definition Version 1 0 for details The mBMC provides only low level access to the FRU inventory area storage It does not validate or interpret the data that is written This includes the common header area Applications cannot relocate or resize any FRU inventory areas 5 3 13 NMI Generation The mBMC generated NMI pulse duration is 200 ms The following may cause the mBMC to generate an NMI pulse e Receiving a Chassis Control
217. nt Revision 1 0 141 C78844 002 Platform Management 5 3 20 IMM BMC Sensor Support Intel Server Board SE7520JR2 The following tables are for the built in and the external sensors for the platform when either an Intel Management Module Professional or Advanced is installed Table 56 Platform Sensors for Intel Management Modules Professional and Advanced Sensor Power Unit Power Unit Generic Event Reading Type Sensor Specific 6Fh Power Unit Status Power Unit Redundancy Sensor Specific 6Fh Watchdog2 Watchdog 23h Sensor Specific 6Fh Platform Security Violation Attempt 06h Platform Security Violation Sensor Specific 6Fh Physical Security Violation Physical Security 05h Sensor Specific 6Fh POST error POST Error OFh 142 Readable Value Offsets Event Offset Triggers Assert Deassert EventData Power Off Power Cycle A C Lost Soft Power Control Fault Power Unit Failure Predictive Failure Redundancy Regained Redundancy lost Redundancy Degraded Non red Suff res from redund Trig Offset Trig Offset Trig Offset Trig Offset POST Code Revision 1 0 Non red Suff res from insuff res As Non red Insuff res Redundancy Degraded from full redundancy Redundancy Degraded from non redundant Timer Expired Hard Reset Power Down Power Cycle Timer Interrupt Secure mode violation attempt Out of band access password v
218. nt S ATA controllers present the same register interface as the P ATA controllers Hot plugging of S ATA drives during the boot process is not supported by the BIOS and may result in undefined behavior 3 4 5 1 Ultra ATA 100 The IDE interfaces of the ICH5R DMA protocol redefines signals on the IDE cable to allow both host and target throttling of data and transfer rates of up to 100MB s 3 4 5 2 IDE Initialization The BIOS supports the ATA ATAPI Specification version 6 or later The BIOS initializes the embedded IDE controller in the chipset ICH5 R and the IDE devices that are connected to these devices The BIOS scans the IDE devices and programs the controller and the devices with their optimum timings The IDE disk read write services that are provided by the BIOS use PIO mode but the BIOS programs the necessary Ultra DMA registers in the IDE controller so that the operating system can use the Ultra DMA Modes 3 4 6 SATA Support The integrated Serial ATA SATA controller of the ICH5 R provides two SATA ports on the baseboard The SATA ports can be enabled disabled and or configured by accessing the BIOS Setup Utility during POST The SATA function in the ICH5 R has dual modes of operation to support different operating system conditions In the case of native IDE enabled operating systems the ICH5 R has separate PCI functions for serial and parallel ATA To support legacy operating systems there is only one PCI function for both th
219. nt generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures e Reorient or relocate the receiving antenna e Increase the separation between the equipment and the receiver e Connect the equipment to an outlet on a circuit other than the one to which the receiver is connected e Consult the dealer or an experienced radio TV technician for help Any changes or modifications not expressly approved by the grantee of this device could void the user s authority to operate the equipment The customer is responsible for ensuring compliance of the modified product Only peripherals computer input output devices terminals printers etc that comply with FCC Class A or B limits may be attached to this computer product Operation with noncompliant peripherals is likely to result in interference to radio and TV reception All cables used to connect to peripherals must be shielded and grounded Operation with cables connected to peripherals that are not shielded and grounded may result in interfere
220. o 133MHz 3 4 1 5 PCI Scan Order The BIOS assigns PCI bus numbers in a depth first hierarchy in accordance with the PCI Local Bus Specification When a bridge device is located the bus number is incremented in exception of a bridge device in the chipsets Scanning continues on the secondary side of the bridge until all subordinate buses are defined PCI bus numbers may change when PCI PCI bridges are added or removed If a bridge is inserted in a PCI bus all subsequent PCI bus numbers below the current bus are increased by one 3 4 1 6 PCI Bus Numbering PCI configuration space protocol requires that all PCI buses in a system be assigned a bus number Bus numbers must be assigned in ascending order within hierarchical buses Each PCI bridge has registers containing its PCI bus number and subordinate PCI bus number which must be loaded by POST code The subordinate PCI bus number is the bus number of the last Revision 1 0 49 C78844 002 Functional Architecture Intel Server Board SE7520JR2 hierarchical PCI bus under the current bridge The PCI bus number and the subordinate PCI bus number are the same in the last hierarchical bridge 3 4 1 7 Device Number and IDSEL Mapping Each device under a PCI bridge has its IDSEL input connected to one bit out of the PCI bus address data signals AD 31 11 for the PCI bus Each IDSEL mapped AD bit acts as a chip select for each device on PCI The host bridge responds to a unique PCI device ID value
221. oard Command Bar Options Key Option Description Enter Execute Command The Enter key is used to activate sub menus pick lists or to select a sub field If a pick list is displayed the Enter key will select the pick list highlighted item and pass that selection in the parent menu ESC Exit The ESC key provides a mechanism for backing out of any field This key will undo the pressing of the Enter key When the ESC key is pressed while editing any field or selecting features of a menu the parent menu is re entered When the ESC key is pressed in any sub menu the parent menu is re entered When the ESC key is pressed in any major menu the exit confirmation window is displayed and the user is asked whether changes can be discarded If No is selected and the Enter key is pressed or if the ESC key is pressed the user is returned to where they were before ESC was pressed without affecting any existing any settings If Yes is selected and the Enter key is pressed setup is exited and the BIOS continues with POST T Select Item The up arrow is used to select the previous value in a pick list or the previous options in a menu item s option list The selected item must then be activated by pressing the Enter key 4 Select Item The down arrow is used to select the next value in a menu item s option list or a value field s pick list The selected item must then be activated by pressing the Enter key 84
222. of the system and OS policy determines what sleep state if any the system transitions into 110 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 System BIOS 4 9 2 6 Sleep to On ACPI If an operating system is loaded the sleep button generates a wake event to the ACPI chipset and a request via SCI to the OS to place the system in the On state The OS retains control of the system and OS policy determines what sleep state if any and sleep sources the system can wake from 4 9 2 7 System Sleep States The platform supports the following ACPI System Sleep States e ACPI SO working state e ACPI S1 sleep state e ACPI S4 suspend to disk state e ACPI S5 soft off state The platform supports the following wake up sources in an ACPI environment As noted above the OS controls the enabling and disabling of these wake sources e Devices that are connected to all USB ports such as USB mice and keyboards can wake the system up from the S1 sleep state e PS 2 keyboards and mice can wake up the system from the S1 sleep state e Both serial ports can be configured to wake up the system from the S1 sleep state e PCI cards such as LAN cards can wake up the system from the S1 or S4 sleep state Note that the PCI card must have the necessary hardware for this to work e As required by the ACPI Specification the power button can always wake up the system from the S1 or S4 state 2 Additionally if an ACPI operating syst
223. olling traffic off the public IPMB bus This also increases the reliability of access to the information since issues with IPMB bus arbitration and message retries are avoided Furthermore placing managed l C devices on the private management bus frees up the IC addresses that those devices would have used up on the IPMB 5 1 5 Management Controllers At the heart of platform management is a management controller To support the tiered management model the Server Board SE7520JR2 supports two different management controllers the PC87431M mini Baseboard Management Controller mBMC from National Semiconductor and Intel s Sahalee BMC The Professional and Advanced modules electrically replace the mBMC with the more full featured Sahalee microcontroller Sahalee is a custom ARM7 TDMI based microcontroller designed for baseboard management applications on Intel Server baseboards The management controller is a microcontroller that provides the intelligence at the heart of the Intelligent Platform Management architecture The primary purpose of the management controller is to autonomously monitor system sensors for system platform management events such as over temperature out of range voltages etc and log their occurrence in the non volatile System Event Log SEL This includes events such as over temperature and over voltage conditions fan failures etc The management controller also provides the interface to the sensors a
224. ommand for sensor access The message based interface isolates software from the particular hardware implementation System Management Software discovers the platform s sensor capabilities by reading the Sensor Data Records from a Sensor Data Record Repository managed by the management controller Sensor Data Records provide a list of the sensors their characteristics location type and associated Sensor Number for sensors in a particular system The Sensor Data Records also hold default threshold values if the sensor has threshold based events factors for converting a sensor reading into the appropriate units mV rpm degrees Celsius etc and information on the types of events that a sensor can generate Sensor Data Records also provide information on where Field Replaceable Unit FRU information is located and information to link sensors with the entity and or FRU they re associated with Information in the SDRs is also used for configuring and restoring sensor thresholds and event generation whenever the system powers up or is reset This is accomplished via a process called the initialization agent The BMC reads the SDRs and based on bit settings writes the threshold data Then it enables event generation for the various sensors it monitors and in management controllers on the IPMB for systems based on the Standard or Advanced management models System Management Software uses the data contained in the Sensor Data Recor
225. onnector for use in third party reference chassis The following tables provide the pinouts for each connector Table 91 100 Pin Flex Cable Connector Pin out For Intel Chassis w Backplane J2J1 Revision 1 0 Pin Signal Name GND V IO RED CONN FP V IO GREEN CONN FP A4 V IO BLUE CONN FP A5 VIDEO_IN_USE A6 SPB_DTR_L SPB RTS L SPB SIN SPB DSR FP NMI BTN L GND FP ID BTN L P5V STBY FP RST BTN L HDD FAULT LED L FP PWR BTN L HDD LED ACT L P3V3 A19 IPMB I2C 5VSB SDA C78844 002 Pin Signal Name B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 LAN LINKB R FP CHASSIS INTRU PS I2C 5VSB SCL 189 Connectors and Jumper Blocks 190 Pin Signal Name A21 P5V_STBY A22 RST IDE L 23 FD DSKCHG L FD WPD L 25 FD TRKO L 26 FD WGATE L 27 FD DIR L FD DSO L 29 GND 30 IDE SDD 7 31 IDE SDD 6 IDE SDD 5 33 IDE SDD 4 34 IDE SDD 3 35 IDE SDD 2 IDE SDD 1 37 IDE SDD 0 38 GND IDE SDDACK L IDE SDA 1 41 IDE SDA 0 42 IDE SDCS1 L IDE SEC HD ACT L GND 45 FAN TACH5 46 FAN TACH6 FAN TACH7 FAN TACH8 A49 FAN SPEED CNTL2 A50 P5V_STBY Intel Server Board SE7520JR2 Table 92 50 Pin Control Panel Connector Intel Chassis w No Backplane J1J2 Signal Name PWR LCD 5VSB TP J1H5 3 FP STATUS LED1 L FP STATUS LED2 L 5VSTBY FP ID LED L LAN LINKB L C78844 002 Revis
226. or each device is set using PCI configuration registers 3 5 1 2 3 High BIOS The top 1MB of extended memory under 4GB is reserved for the system BIOS extended BIOS for PCI devices and A20 aliasing by the system BIOS The Intel Xeon processor begins executing from the high BIOS region after reset 3 5 1 2 4 High Memory Gap Reclaiming The BIOS creates a region immediately below 4 GB to accommodate memory mapped I O regions for the system BIOS Flash APIC memory and 32 bit PCI devices Any system memory in this region is remapped above 4GB 3 5 1 2 5 I O APIC Configuration Space A 64KB block located 20MB below 4GB 0FEC00000 to OFECOFFFFh is reserved for the I O APIC configuration space The first I O APIC is located at FECO0000h The second I O APIC is located at FEC80000h The third I O APIC is located at FEC80100h 3 5 1 2 6 Extended Intel Xeon Processor Region above 4GB An Intel Xeon processor based system can have up to 64 GB of addressable memory With the chipset only supporting 16GB of addressable memory the BIOS uses an extended addressing mechanism to use the address ranges 3 5 1 3 Memory Shadowing System BIOS and option ROM can be shadowed in main memory Typically this is done to allow ROM code to execute more rapidly out of RAM ROM is designated read only during the copy process while RAM at the same address is designated write only After copying the RAM is designated read only After the BIOS is shadowed the
227. or is no longer fatal to the system When an uncorrectable error is encountered during normal operation hardware simply retrieves the mirror copy of the corrupted data and no system failure will occur unless both primary and mirror copies of the same data are corrupt simultaneously Mirroring is supported on dual channel DIMM populations symmetric both across channels and within each channel As a result on the Server Board SE7520JR2 there are two supported configurations for memory mirroring e Four DIMM population of completely identical devices two per channel Refer to Figure 6 DIMMs labeled 1A 2A 1B and 2B must all be identical l L GN lt D D D D Ij M M MM M M M M 313 1 NI A B A B MC L JL pe J Empt Mirror Primar Figure 6 Four DIMM Memory Mirror Configuration e Six DIMM population with identical devices in slot pairs 1 and 2 3 on each channel DIMM slots labeled 1A 1B must be populated with identical dual ranked DIMMs while DIMMs in the remaining slots must be identical single rank DIMMs DIMMs between the two groups do not have to be identical This configuration is only valid with DDR2 memory DDR266 333 mirrored memory configurations are only capable of supporting 2 DIMMs per channel Revision 1 0 45 C78844 002 Functional Architecture Intel Server Board SE7520JR2 AA Ti JL JU 2
228. ory RAS Information to the SEL In systems configured with either a Professional or Advanced IMM the system BIOS is responsible for sending the current memory RAS configuration to the Sahalee BMC in accordance with Sahalee BMC spec Note The operation of the memory RASUM features described is supported regardless of the platform management model used However with no Intel Management Module installed the system has limited memory monitoring and logging capabilities It is possible for a RASUM feature to be initiated without notification that the action has occurred when using standard on board platform instrumentation BIOS will send the initial memory RAS state during POST memory configuration using the SMS commands BIOS will update the memory RAS state when memory errors occur that affect the RAS state using the SMM commands 3 4 1 0 Sub System The I O sub system is made up of several components e The MCH provides the PCI Express interface to the full height riser slot e The PXH provides the PCI X interfaces for the two riser slots the on board SCSI controller and on board Ethernet controllers e The ICH5 R provides the interface for the onboard video controller super IO chip and management sub system This section describes the function of each I O interface and how they operate on the Server Board SE7520JR2 3 4 1 PCI Subsystem The primary I O interface for the Server Board SE7520JR2 is PCI with four independent PCI
229. ot 3A 8501 Bad or missing memory in slot 2A 8502 Bad or missing memory in slot 1A 8504 Bad or missing memory in slot 3B 8505 Bad or missing memory in slot 2B 8506 Bad or missing memory in slot 1B 8600 Primary amp Secondary BIOS ID s don t match 8601 Override Jumper is set to force boot from lower bank of flash ROM 8602 WatchDog Timer Expired Secondary BIOS maybe bad 8603 Secondary BIOS CheckSum fail The following table indicates error codes that are sent to the Management Module for error logging as a BMC pass through command All commands are of Error type The syntax of error logging with the management module and SEL is different The same error is logged differently in the SEL than with the Management Module Table 69 Error Codes Sent to the Management Module Error code Error messages 161 Bad CMOS Battery 301 Keyboard failure 102 System Board failure Timer tick 2 test failure 106 Diskette Controller Failure 604 Diskette Drive failure 163 Time of the day not set 01298000 The BIOS does not support the current stepping of Processor PO 01298001 The BIOS does not support the current stepping of Processor P1 164 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Error Reporting and Handling Error code Error messages 196 Processor cache mismatch detected 198 Processor speed mismatch detected 00019700 P
230. ot configured as FML this signal is used as I2C data ICH_LCLK LPC 33Mhz clock input USB_M Reserved for future use as USB input Baseboard can leave as NC FMM_SYSIRQ KCS interrupt signal from FMM Card USB_P Reserved for future use as USB input Baseboard can leave as NC ICH_LAD1 LPC Address data bus Bit 1 FMM_RSMRST_N 36 When this signal is asserted the FMM is held in reset This is a Standby reset indication and should be driven by a Standby monitor device such as the Heceta7 or Dallas DS1815 ICH_LFRAME_N LPC Cycle Framing ICH_LADO LPC Address data bus Bit 0 ICH_LAD3 LPC Address data bus Bit 3 ICH_LPCPD_N LPC Power down indication ICH_LAD2 LPC Address data bus Bit 2 FMM_LPCRST_N 40 LPC bus reset Must be properly buffered on motherboard to ensure monotonicity DFP_CLK 46 Serial clock signal for DFP EDID device Must connect to DFP_CLK pin on the graphics chip DFP_DAT Serial data signal for DFP EDID device Must connect to DFP_DAT pin on the Graphics chip IPMB I2C 5VSB SDA Connects to IPMB header IPMB I2C 5VSB SCL Connects to IPMB header SMB_I2C_3VSB_SDA 1 This bus should connect to the PCI slots ICH and mBMC host I F An isolated version of this bus non Standby should connect to the DIMMs and clock buffer s SMB I2C 3VSB SCL This bus should connect to the PCI slots ICH and mBMC host I F An isolated version of this bus non Standby should connect to the DIMMs and clock buffer s This bus should conne
231. oth PCI X signals from the PXH and PCI Express signals from the MCH routed to it Depending on the riser card used the slot is able to support both PCI X and or PCI Express add in cards The board placement of this slot allows risers to support full height full length add in cards 3 2 2 2 Low Profile Riser Slot The low profile riser slot is a standard 202 pin slot connector supporting PCI X signals from the PXH Because of available board clearances riser cards can only support low profile add in cards with this slot Revision 1 0 33 C78844 002 Functional Architecture Intel Server Board SE7520JR2 3 2 2 3 I OxAPIC Controller The PXH contains two I OxAPIC controllers both of which reside on the primary bus The intended use of these controllers is to have the interrupts from PCI bus A connected to the interrupt controller on device 0 function 1 and have the interrupts on PCI bus B connected to the interrupt controller on device 0 function 3 3 2 2 4 SMBus Interface The SMBus interface can be used for system and power management related tasks The interface is compliant with System Management Bus Specification Revision 2 0 The SMBus interface allows full read write access to all configuration and memory spaces in the PXH 3 2 3 O Controller Hub ICH5 R The ICH5 R is a multi function device providing an upstream hub interface for access to several embedded I O functions and features including e PCI Local Bus Specificat
232. ough the system from standby output up to 500mV There shall be no additional heat generated nor stress of any internal components with this voltage applied to any individual output and all outputs simultaneously It also should not trip the protection circuits during turn on The residual voltage at the power supply outputs for no load condition shall not exceed 100mV when AC voltage is applied Revision 1 0 211 C78844 002 Tpwok off Tpson_pwok Design and Environmental Specifications Intel Server Board SE7520JR2 8 3 Product Regulatory Compliance 8 3 1 Product Safety Compliance The Server Board SE7520JR2 complies with the following safety requirements e UL60950 CSA 60950 USA Canada e EN60950 Europe e EC60950 International e CB Certificate amp Report IEC60950 report to include all country national deviations e GOST R 50377 92 Listed on one System License Russia e Belarus License Listed on System License Belarus e CE Low Voltage Directive 73 23 EEE Europe e IRAM Certification Argentina 8 3 2 Product EMC Compliance Class A Compliance Note Legally the product is required to comply with Class A emission requirements as it is intended for a commercial type market place Intel targets 10db margin to Class A Limits The Server Board SE7520JR2 has been has been tested and verified to comply with the following electromagnetic compatibility EMC regulations when installed a
233. p Super I O Configuration Sub menu esses 91 Table 27 BIOS Setup USB Configuration Sub menu Selections sess 92 Table 28 BIOS Setup USB Mass Storage Device Configuration Sub menu Selections 92 Table 29 BIOS Setup PCI Configuration Sub menu Selections sssssuuuss 93 Table 30 BIOS Setup Memory Configuration Sub menu Selections uuuus 94 Table 31 BIOS Setup Boot Menu SelectiONS ococccccccccccoconcncnonnncnononencncnnonnnnononencnnnnoninononos 95 Table 32 BIOS Setup Boot Settings Configuration Sub menu Selections 96 xiv Revision 1 0 C78844 002 Intel Server Board SE7520JR2 List of Tables Table 33 BIOS Setup Boot Device Priority Sub menu Selections ssssssss 97 Table 34 BIOS Setup Hard Disk Drive Sub Menu SelectionsS oooconoccncnccnnocononincnnnnnnnnnns 97 Table 35 BIOS Setup Removable Drives Sub menu SelectiONS ooococccnccnncccononencnnnnoncnnn 97 Table 36 BIOS Setup CD DVD Drives Sub menu SelectiONS cccccooconoccncnncnnoconenincnnnnnnnnnns 97 Table 37 BIOS Setup Security Menu OptiONS ooooococccccococococonononononnnronno nono nnnn nono nnnnnnnnnnnnn naar 98 Table 38 BIOS Setup Server Menu SelectiONS cccccccccccococoncccnncnnonononencncnnononnnnoncncononnnnnononos 99 Table 39 BIOS Setup System Manag
234. paired with DIMMs on channel B to configure 2 way interleaving Each DIMM pair is referred to as a bank The bank can be further divided into two rows based on single sided or double sided DIMMs If both DIMMs in a bank are single sided only one row is said to be present For double sided DIMMs both rows are said to be present The Server Board SE7520JR2 has six DIMM slots or three DIMM banks Both DIMMs in a bank should be identical same manufacturer CAS latency number of rows columns and devices timing parameters etc Although DIMMs within a bank must be identical the BIOS supports various DIMM sizes and configurations allowing the banks of memory to be different Memory sizing and configuration is guaranteed only for qualified DIMMs approved by Intel m 3 M 2 NA 1 Figure 5 Identifying Banks of Memory The BIOS reads the Serial Presence Detect SPD SEEPROMs on each installed memory module to determine the size and timing of the installed memory modules The memory sizing algorithm determines the size of each bank of DIMMs The BIOS programs the Memory Controller in the chipset accordingly The total amount of configured memory can be found using BIOS Setup 3 3 2 Memory Population Mixing of DDR 266 and DDR 333 DIMMs is supported between banks of memory However when mixing DIMM types DDR 333 will run at DDR 266 speeds 38 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture Using t
235. pecification over the full range of voltage drops from the power supply s output connector to the remote sense points 8 2 4 Standby Outputs The 5VSB output shall be present when an AC input greater than the power supply turn on voltage is applied 206 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Design and Environmental Specifications 8 2 5 Voltage Regulation The power supply output voltages must stay within the following voltage limits when operating at steady state and dynamic loading conditions These limits include the peak peak ripple noise All outputs are measured with reference to the return remote sense signal ReturnS The 5V 12V1 12V2 12V3 12V and 5VSB outputs are measured at the power supply connectors referenced to ReturnS The 3 3V is measured at it remote sense signal 3 3VS located at the signal connector Table 118 Voltage Regulation Limits Parameter Tolerance Minimum Nominal Maximum Units V EIE 8 2 6 Dynamic Loading The output voltages shall remain within limits specified for the step loading and capacitive loading specified in the table below The load transient repetition rate shall be tested between 50Hz and 5kHz at duty cycles ranging from 1096 9096 The load transient repetition rate is only a test specification The A step load may occur anywhere within the MIN load to the MAX load conditions Table 119 Transient Load Requirements A Step Load Size Load Slew
236. pient Intel Corporation Date of Manufacturer Refer to date code on product Manufacturer Nation Intel Corporation Refer to country of origin marked on product Revision 1 0 215 C78844 002 Miscellaneous Board Information Intel Server Board SE7520JR2 9 Miscellaneous Board Information 9 1 Updating the System Software To ensure your Server Board SE7520JR2 has the latest board fixes it is highly recommended to load the latest system software These include System BIOS mBMC firmware and FRUSDR Utility It may also include Intel Management Module IMM BMC Firmware if installed and Hot Swap Controller HSC firmware if the baseboard is installed into an Intel server chassis with a backplane The latest system software for the Server Board SE7520JR2 can be downloaded from the following Intel web site http support intel com support motherboards server se7520jr2 You can use the Server Menu in the lt F2 gt BIOS Utility to verify what versions of system software are installed on your server If you determine that an update is necessary the system software should be updated in the following order e HSC firmware If Applicable e mBMC Firmware e IMM BMC Firmware If Applicable e FRUSDR Utility e System BIOS It is highly recommended to read the README TXT file that accompanies each update package for complete install instructions and release notes before attempting to update the system software onto your server board 9
237. ports a peak bandwidth of 266MB s using a x4 base clock of 66 MHz 3 2 2 PCI X Hub PXH The PXH provides the data interface between the MCH and two PCI X bus segments over a high speed PCI Express x8 link The PCI Express interface is compliant with the PCI Express Base Specification rev 1 0 and provides a maximum realized bandwidth of 2GB s in each direction simultaneously for an aggregate of 4 GB s The PCI X interfaces of the PXH comply with the following e PCI X Addendum to the PCI Local Bus Specification Revision 1 0b e Mode 1 of the PCI X Electrical and Mechanical Addendum to the PCI Local Bus Specification Revision 2 0a e PCI X Protocol Addendum to the PCI Local Bus Specification Revision 2 0a For conventional PCI Mode the PXH supports PCI bus frequencies of 66 MHz 100 MHz and 133 MHz On the Server Board SE7520JR2 each of the two PCI X interfaces PCI Bus A and PCI Bus B is independently controlled to operate in either a conventional PCI or PCI X mode PCI Bus A is routed to control I O from the full height riser slot and the LSI 53C1030 Dual Channel SCSI controller and is capable of supporting both PCI X Mode 1 and Mode 2 interfaces depending on the riser card used PCI Bus B is routed to control I O from the low profile riser slot and the 82546GB Dual GB Ethernet controllers 3 2 2 1 Full height Riser Slot Using Intel Adaptive Slot Technology the full height riser slot is a proprietary 280 pin slot connector with b
238. pporting full height add in cards The following tables show the pin out for each riser slot 7 2 1 Low Profile PCI X Riser Slot The low profile riser slot pin assignments are shown below On a given riser card the PCI add in slot closest to the baseboard will always have device ID 17 On a three slot riser card the middle PCI add in slot will have device ID 18 and the top slot will have device ID 19 The interrupts on the PCI add in slots should be rotated following the PCI bridge specification 1 0 To prevent anyone from putting a PCI add in card directly into the riser slot the connector has been pined out so that Pin 1 is furthest from the board edge Side B should be closest to the memory DIMMs Table 85 Low Profile Riser Slot Pinout Pin PCI Spec Description PCI Spec Description Side Signal Signal B 100 RSVD 12V 8 fam 176 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Pin PCI Spec Side Signal B 5V Description This pin will be connected on the 2U riser to INT_B of the bottom PCI slot INT_A of the middle slot and INT_D of the top slot This pin will be used by 1U 2U riser to bring the INT_D interrupt on the bottom PCI slot down to the baseboard Boe Highest PCI Slot SLOT3 w jew jaa CLK2 Middle PCI Slot SLOT2 REQ2 Middle PCI Slot SLOT2 GND 86 GND GND CLK1 Lowest PCI slot SLOT 1 3 3V Was 3 3V or 1 5V C BE 3 8 us ss fond LAN LN Lowest
239. r Unknown BIOS error Error code 147 this is really a PMM MEM ALLOC ERR Password check failed Unknown BIOS error Error code 149 this is really SEGMENT REG ERR Unknown BIOS error Error code 14A this is really ADM MODULE ERR Unknown BIOS error Error code 14B this is really LANGUAGE MODULE ERR Keyboard Interface Error Primary Master Hard Disk Error Primary Slave Hard Disk Error Secondary Master Hard Disk Error Secondary Slave Hard Disk Error Primary Master Drive ATAPI Incompatible Primary Slave Drive ATAPI Incompatible Secondary Master Drive ATAPI Incompatible Secondary Slave Drive ATAPI Incompatible Third Master Device Error Fourth Master Device Error S M A R T Status BAD Backup and Replace Password check failed Thermal Trip Failure Insufficient Memory to Shadow PCI ROM BSP Processor failed BIST Processor missing microcode PO Processor missing microcode P1 BIOS does not support current stepping PO BIOS does not support current stepping P1 L2 cache size mismatch CPUID Processor stepping are different CPUID Processor family are different Front side bus mismatch CPUID Processor Model are different Processor speeds mismatched CMOS Cleared By Jumper Password cleared by jumper CMOS Cleared By BMC Request Warning Port 60h 64h emulation is not supported by this USB Host Controller Warning EHCI controller disabled It requires 64bit data support in the BIOS Processor
240. r button The power button is a request that is forwarded by the mBMC to the ACPI power state machines in the chipset It is monitored by the mBMC and does not directly control power on the power supply Revision 1 0 109 C78844 002 System BIOS Intel Server Board SE7520JR2 The BIOS supports a control panel sleep button The sleep button may not be provided on all control panel designs On systems where the sleep button is optional a system configuration option will be provided to enable or disable the sleep button The ACPI tables will be updated to indicate the presence or absence of the sleep button Removal of the sleep button does not prevent an ACPI OS from entering a sleep state The sleep button has no effect unless an operating system is running If the OS is running pressing the sleep button causes an event The OS will cause the system to transition to the appropriate ACPI system state depending on the current user settings The platform supports a control panel reset button The reset button is a request that is forwarded by the mBMC to the chipset The BIOS does not affect the behavior of the reset button The BIOS supports a control panel NMI button The NMI button may not be provided on all control panel designs The NMI button is a request that causes the mBMC to generate an NMI non maskable interrupt The NMI is captured by the BIOS during Boot Services time or the OS during Runtime The BIOS will simply halt the system upo
241. r channel amp Port1 to 4 IDE Master channel Otherwise set S ATA Port0 to 4 IDE Master channel amp Port1 to 3 IDE Master channel Selects submenu for configuring mixed P ATA and S ATA Selects submenu with additional device details Selects submenu with additional device details Selects submenu with additional device details Selects submenu with additional device details Revision 1 0 Intel Server Board SE7520JR2 System BIOS Options HelpText Description Third IDE Master While entering setup BIOS auto Selects submenu with additional detects the presence of IDE device details devices This displays the status of auto detection of IDE devices Fourth IDE Master While entering setup BIOS auto Selects submenu with additional detects the presence of IDE device details devices This displays the status of auto detection of IDE devices Hard Disk Write Disabled Disable Enable device write Primarily used to prevent Protect Enabled protection This will be effective unauthorized writes to hard only if device is accessed drives through BIOS IDE Detect Time Out Select the time out value for Primarily used with older IDE Sec detecting ATA ATAPI device s devices with longer spin up times ATA PI 80Pin Cable Host amp Device Select the mechanism for The 80 pin cable is required for Detection Host detecting 80Pin ATA PI Cable UDMA 66 and above BIOS detects the cable by qu
242. r outputs a digital signal that is monitored by the baseboard management sub system A thermal trip is a critical condition and indicates that the processor may become damaged if it continues to run To help protect the processor the management controller automatically powers off the system In addition the System Status LED will change to Amber and the error condition will be logged to the System Event Log SEL If either the Intel Management Module Professional Edition or Advanced Edition is present in the system the Fault LED fro the affected processor will also be illuminated 3 1 11 Processor IERR The IERR signal is asserted by the processor as the result of an internal error The mBMC configures the LM93 device to monitor this signal When this signal is asserted the mBMC generates a processor IERR event 3 2 Intel E7520 Chipset The architecture of the Server Board SE7520JR2 is designed around the Intel E7520 chipset The chipset consists of three components that together are responsible for providing the interface between all major sub systems found on the baseboard including the processor memory and I O sub systems These components are Revision 1 0 31 C78844 002 Functional Architecture Intel Server Board SE7520JR2 e Memory Controller Hub MCH e I O Controller Hub ICH5 R e PCI X Hub PXH The following sub sections provide an overview of the primary functions and supported features of each chipset component as t
243. rdware support that allow a multiprocessor system to boot in case of failure of the bootstrap processor BSP under certain conditions FRB functionality will differ depending on whether standard onboard platform instrumentation is used MBMC or whether an Intel Management Module is used With on board platform instrumentation should a processor failure be detected during POST the mBMC does not have the ability to disable the failed or failing processor Therefore the system may or may not continue to boot A FRB 2 error will be generated to the System Event Log SEL and an error will be displayed at POST FRB2 is a BIOS based algorithm that uses the mBMC IPMI watchdog timer to protect against BIOS hangs during the POST process On systems that have an Intel Management Module installed several different levels of FRB are supported FRB1 FRB2 FRB3 and OS Watchdog Timer The FRB algorithms detect BSP failures and take steps to disable that processor and reset the system so another processor will run as the BSP 6 1 1 FRB1 BSP Self Test Failures The BIOS provides an FRB1 timer Early in POST the BIOS checks the Built in Self Test BIST results of the BSP If the BSP fails BIST the BIOS requests the Sahalee BMC to disable the BSP The Sahalee BMC disables the BSP selects a new BSP and generates a system reset If there is no alternate processor available the Sahalee BMC generates a beep code and halts the system If the Sahalee BMC is not i
244. re 5 Identifying Banks of Memory 2 ccceeeesscceeenceteeeeeeedseeedeeneeeeceseeeeceeteeeeeeeceteeeesens 38 Figure 6 Four DIMM Memory Mirror Configuration ssseseeeennm 45 Figure 7 Six DIMM Memory Mirror Configuration DDR2 Only ssseeee 46 Figure 8 Interrupt Routing Diagram ICH5 R Internal seeee 55 Figure 9 Interrupt Routing Diagram s iae deese pestem nomad lila 56 Figure 10 PCI Interrupt Mapping Diagram eeeeecenneneeneeeen ennt nnne nnne 57 Figure 11 PCI Interrupt Mapping Diagram for 2U Active Riser Card sessssssss 57 Figure 12 Serial Port MUX L ge rto peor it ias 68 Figure 13 RJ45 Serial B Port Jumper Block Location and Setting 68 Figure 14 Intel Xeon Processor Memory Address Space 70 Figure 15 DOS Compatibility Region ius da ras a vase veio 71 Figure 16 Extended Memory Map cosa iii 73 Figure 17 BIOS Identification SU trate 80 Figure 18 POST Console Interface irren eren idad 82 Figure 19 On Board Platform Management Architecture oooooncicononccccnncccccnnnnnannncnnnccncnanannnos 115 Figure 20 mBMC in a Server Management SysSteM ooooonococcccccccccccnonaannnoncnnnnnnnnnananonnnnncnnnnnnnns 121 Figure 21 External Interfaces to mBMC eese neeeenkee nennen nece 123 Figure 22 mBMC Block Diagram uode tap Tto tete tent
245. reparing the machine to boot the operating system At boot time the system is in virtual wire mode and the BSP alone is programmed to accept local interrupts INTR driven by programmable interrupt controller PIC and non maskable interrupt NMI As a part of the boot process the BSP enables the application processor When enabled the AP programs its Memory Type Range Registers MTRRs to be identical to those of the BSP The AP executes a halt instruction with its local interrupts disabled If the BSP determines that an AP exists that is a lower featured processor or that has a lower value returned by the CPUID function the BSP switches to the lowest featured processor in the system 3 1 8 CPU Thermal Sensors The CPU temperature will be indirectly measured via thermal diodes These are monitored by the LM93 sensor monitoring device The mBMC configures the LM93 to monitor these sensors The temperatures are available via mBMC IPMI sensors 3 1 9 Processor Thermal Control Sensor The Intel Xeon processors generate a signal to indicate throttling due to a processor over temp condition The mBMC implements an IPMI sensor that provides the percentage of time a processor has been throttled over the last 1 46 seconds Baseboard management forces a thermal control condition when reliable system operation requires reduced power consumption 3 1 10 Processor Thermal Trip Shutdown If a thermal overload condition exists thermal trip the processo
246. res Sub menu Selections Table 40 BIOS Setup Serial Console Features Sub menu Selections Feature Options Help Text Serial Console Features BIOS Redirection Port Disabled If enabled BIOS uses the specified serial When the Intel Serial A port to redirect the console to a remote ANSI Management Module is terminal Enabling this option disables Quiet present the help text Boot directs the user to select Serial B for Serial Over LAN Serial B If enabled BIOS uses the specified serial port to redirect the console to a remote ANSI terminal Enabling this option disables Quiet Boot For Serial Over LAN select Serial B Baud Rate Flow Control No Flow Control If enabled it will use the Flow control CTS RTS selected XON XOFF CTS RTS Hardware CTS RTS CD XON XOFF Software CTS RTS CD Hardware Carrier Detect for modem use Terminal Type PC ANSI VT100 selection only works for English as VT100 the selected language VT UTF8 uses Unicode PC ANSI is the standard PC type VT UTF8 terminal ACPI Redirection port Disabled Enable Disable the ACPI OS Headless Serial A Console Redirection Serial B Serial Port Connector Serial A Selects which serial port will be routed to the Serial B serial port connector on the back of the chassis Serial A selects UARTA and Serial B selects UARTB 4 4 2 5 3 Event Log Configuration Sub menu Selections Table 41 BIOS Setup Event Log Configuration Sub menu Selectio
247. rm Management Intel Server Board SE7520JR2 5 3 10 1 SEL Erasure It can take up to one minute to clear a System Event Log based upon other concurrent mBMC operations 5 3 10 2 Timestamp Clock The mBMC maintains a four byte internal timestamp clock used by the SEL and SDR subsystems This clock is incremented once per second and is read and set using the Get SEL Time and Set SEL Time commands respectively The Get SDR Time command can also be used to read the timestamp clock These commands are specified in the Intelligent Platform Management Interface Specification Version 1 5 The mBMC SEL timestamp is initialized by the BIOS prior to booting to the operating system using the IPMI command Set SEL Time After a mBMC reset the mBMC sets the initial value of the timestamp clock to 0x00000000 It is incremented once per second after that A SEL event containing a timestamp from 0x00000000 to 0x140000000 has a timestamp value that is relative to mBMC initialization During POST the BIOS tells the mBMC the current real time clock RTC time via the Set SEL Time command The mBMC maintains this time incrementing it once per second until the mBMC is reset or until the time is changed via another Set SEL Time command System Management Software is responsible for keeping the mBMC and system time synchronized 5 3 11 Sensor Data Record SDR Repository The mBMC includes built in Sensor Data Records SDRs that provide platform management
248. rocessor PO failed BIST 00019701 Processor P1 failed BIST 00150100 Multi bit error occurred forcing NMI DIMM 00150100 Multi bit error occurred forcing NMI DIMM DIMM could not isolate 289 DIMM D is Disabled 00150900 SERR PERR Detected on PCI bus no source found 00151100 MCA Recoverable Error Detected Proc 00151200 MCA Unrecoverable Error Detected Proc 00151300 MCA Excessive Recoverable Errors Proc 00151350 Processor MachineCheck Data a Bank APIC ID CR4 2 00151351 Processor MachineCheck Data b Address 272 2222 222 Time Stamp 2777 2222 2222 00151352 Processor MachineCheck Data b Status 2297 2222 222 00151500 Excessive Single Bit Errors Detected 00151720 Parity Error Detected on Processor bus 00151730 IMB Parity CRC Error 00151700 Started Hot Spare memory Copy Failed row rows and copied to spare row rows and used on CMIC HE box 00151710 Completed Hot Spare memory Copy Failed row rows and copied to spare row rows and used on CMIC HE box 6 4 3 BIOS Generated POST Error Beep Codes The following table lists POST error beep codes Prior to system video initialization the BIOS uses these beep codes to communicate error conditions Table 70 BIOS Generated Beep Codes Number of Beeps Description Memory refresh timer error Parity error in base memory first 64KB block Base memory rea
249. roken data line on a DIMM would exhibit repeated errors until replaced Although these errors are correctable continual calls to the error logger can throttle the system preventing any further useful work For this reason the system counts certain types of correctable errors and disables reporting if they occur too frequently Correction remains enabled but calls to the error handler are disabled This allows the system to continue running despite a persistent correctable failure The BIOS adds an entry to the event log to indicate that logging for that type of error has been disabled Such an entry indicates a serious hardware problem that must be repaired at the earliest possible time The system BIOS implements this feature for two types of errors correctable memory errors and correctable bus errors If ten errors occur in a single wall clock hour the corresponding error handler disables further reporting of that type of error A unique counter is used for each type of error e an overrun of memory errors does not affect bus error reporting The BIOS re enables logging and SMIs the next time the system is rebooted 154 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Error Reporting and Handling 6 3 Error Logging This section defines how errors are handled by the system BIOS Also discussed is the role of the BIOS in error handling and the interaction between the BIOS platform hardware and server management firmware with
250. rs J5F2 J7F1 are not controlled These operate at a constant speed The mBMC initializes the LM93 to control fan speeds based on temperature The LM93 controls the actual fan speeds based on temperature measurements according to a built in table The table itself is loaded as part of the SDR package according to which system configuration is used In addition BIOS passes in certain temperature data to the LM93 during POST 5 3 8 mBMC Peripheral SMBus The mBMC implements a single private SMBus called the peripheral SMBus The mBMC supports master only mode for this SMBus External agents must use the mBMC s Master Write Read I C command if they require direct communication with a device on this bus 5 3 9 Watchdog Timer The mBMC implements a fully IPMI 1 5 compatible watchdog timer See the IPMI 1 5 specification for details on watchdog timer configuration 5 3 10 System Event Log SEL The mBMC implements the logical System Event Log SEL device as specified in the Intelligent Platform Management Interface Specification Version 1 5 The SEL is accessible via all channels In this way the SEL information can be accessed through out of band interfaces while the system is down The mBMC supports a maximum SEL size of 92 entries If an Intel Management Module is installed in the server the mBMC System Event Log is not accessible and is replaced by the Intel Management Module System Event Log Revision 1 0 131 C78844 002 Platfo
251. rt for a ZCR card 3 4 5 IDE Support Integrated IDE controllers of the ICH5 R provide two independent IDE channels Each is capable of supporting up to two devices A standard 40 pin IDE connector on the baseboard interfaces with one channel The signals of the second IDE channel are routed to the high density 100 pin backplane connector for use in either the Intel Server Chassis SR1400 1U chassis or the Intel Server Chassis SR2400 2U chassis Both IDE channels can be configured and enabled or disabled by accessing the BIOS Setup Utility during POST The BIOS supports the ATA ATAPI Specification version 6 It initializes the embedded IDE controller in the chipset south bridge and the IDE devices that are connected to these devices The BIOS scans the IDE devices and programs the controller and the devices with their optimum timings The IDE disk read write services that are provided by the BIOS use PIO mode but the BIOS will program the necessary Ultra DMA registers in the IDE controller so that the operating system can use the Ultra DMA Modes 60 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture The BIOS initializes and supports ATAPI devices such as LS 120 240 CDROM CD RW and DVD The BIOS initializes and supports S ATA devices just like P ATA devices It initializes the embedded the IDE controllers in the chipset and any S ATA devices that are connected to these controllers From a software standpoi
252. s BIOS Messages Message Displayed Description Keyboard Error Keyboard is not present or the hardware is not responding when the keyboard controller is initialized PS2 Keyboard not found PS2 Keyboard support is enabled in the BIOS setup but the device is not detected PS2 Mouse not found PS2 Mouse support is enabled in the BIOS setup but the device is not detected Keyboard Interface Error Keyboard Controller failure This may indicate a problem with system hardware Unlock Keyboard PS2 keyboard is locked User needs to unlock the keyboard to continue the BIOS POST System Halted The system has been halted A reset or power cycle is required to reboot the machine This message appears after a fatal error has been detected Table 66 USB BIOS Error Messages Message Displayed Description Warning Unsupported USB device found and disabled This message is displayed when a non bootable USB device is enumerated and disabled by the BIOS Warning Port 60h 64h emulation is not supported by this USB Host Controller This message is displayed to indicate that port 60h 64h emulation mode cannot be enabled for this USB host controller This condition occurs if USB KBC emulation option is set for non SMI mode Warning EHCI controller disabled It requires 64bit data support in the BIOS This message is displayed to indicate that EHCI controller is disabled b
253. s for errors If one is found it will log data against the IPMI type OCh Memory Sensor and will log against the IPMI 13h Critical Interrupt sensor for a bus error Both of these can include additional data in bytes 2 and 3 depending on the exact nature of the error and what the chipset reports to the Sahalee BMC 3 3 6 Memory RASUM Features The Intel E7520 MCH supports several memory RASUM Reliability Availability Serviceability Usability and Manageability features These features include the Intel x4 Single Device Data Correction x4 SDDC for memory error detection and correction Memory Scrubbing Retry on Correctable Errors Integrated Memory Initialization DIMM Sparing and Memory Mirroring The following sections describe how each is supported Note The operation of the memory RASUM features listed below is supported regardless of the platform management model used However with no Intel Management Module installed the system has limited memory monitoring and logging capabilities It is possible for a RASUM feature to be initiated without notification that the action has occurred when standard Onboard Platform Instrumentation is used 3 3 6 1 DRAM ECC Intel x4 Single Device Data Correction x4 SDDC The DRAM interface uses two different ECC algorithms The first is a standard SEC DED ECC across a 64 bit data quantity The second ECC method is a distributed 144 bit S4EC D4ED mechanism which provides x4 SDDC protection for D
254. sabled Enable Allow remapping of Enabled overlapped PCI memory above the total physical memory Disable Do not allow remapping of memory Memory Mirroring Sparing Disabled Disabled provides the most Sparing or Mirroring is Spare memory space Sparing reserves grayed out if the installed memory to replace failures DIMM configuration does Mirroring keeps a second copy of not support it memory contents Mirror 4 4 2 3 Boot Menu Table 31 BIOS Setup Boot Menu Selections Feature Options ept Desen Removable Drives Specifies the boot device priority sequence from Selects submenu available removable drives CD DVD Drives i Specifies the boot device priority sequence from Selects submenu available CD DVD drives i available hard drives Revision 1 0 95 C78844 002 System BIOS Intel Server Board SE7520JR2 4 4 2 3 1 Boot Settings Configuration Sub menu Selections Table 32 BIOS Setup Boot Settings Configuration Sub menu Selections Feature Options Help Text Boot Settings Configuration Quick Boot Disabled Allows BIOS to skip certain tests while booting This Enabled will decrease the time needed to boot the system Quiet Boot Disabled Disabled Displays normal POST messages Enabled Enabled Displays OEM Logo instead of POST this is messages conflict with previous words in this doc Based on my memory it is enabled by default Bootup Num Lock Select power on stat
255. se specifications are defined in the following subsections 5 3 17 1 Channel Management The mBMC supports two channels e System interface e 802 3 LAN Table 52 Suported Channel Assignments Channel ID Media Type Supports Sessions 5 3 17 2 User Model The mBMC supports one anonymous user null user name with a settable password The IPMI Set User Password command is supported 5 3 17 3 Request Response Protocol All of the protocols used in the above mentioned interfaces are Request Response protocols A Request Message is issued to an intelligent device to which the device responds with a Response Message As an example with respect to the IPMB interface both Request Messages and Response Messages are transmitted on the bus using SMBus Master Write transfers In other words a Request Message is issued from an intelligent device acting as an SMBus master and is received by an intelligent device as an SMBus slave The corresponding Response Message is issued from the responding intelligent device as an SMBus master and is received by the request originator as an SMBus slave 5 3 17 4 Host to mBMC Communication Interface The host communicates with the mBMC via the System Management Bus SMBus The interface consists of three signals e SMBus clock signal SCLH 134 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Platform Management e SMBus data signal SDAH e Optional SMBus alert signal SMBAH The sign
256. ship with a CEK spring snapped onto the bottom side of the board beneath each processor socket The CEK spring is removable allowing for the use of non Intel heat sink retention solutions Heatsink assembly with integrated hardware Thermal Interface Material TIM Baseboard gt CEK Spring gt Chassis gt Figure 4 CEK Processor Mounting 3 1 6 Processor Support The Server Board SE7520JR2 is designed to support one or two Intel Xeon processors utilizing an 800 MHZ front side bus with frequencies starting at 2 8 GHz Previous generations of Intel Xeon processor are not supported on the Server Board SE7520JR2 The server board is designed to provide up to 120A peak per processors Processors with higher current requirements are not supported Note Only Intel Xeon processors that support an 800MHz Front Side Bus are supported on the Server Board SE7520JR2 See the following table for a list of supported processors and their operating frequencies Table 2 Processor Support Matrix Processor Family FSB Frequency Support Intel Xeon 533 MHz 2 8 GHz No Intel Xeon 533 MHz 3 06 GHz No Intel Xeon TM 533 MHz 3 2 GHz No Intel Xeon TM 800 MHz 2 8 GHz Intel Xeon TM 800 MHz 3 0 GHz 28 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture Processor Family FSB Frequency Support Intel Xeon 800 MHz 3 2 GHz Intel Xeon 800 MHz 3 4 GHz
257. single channel read pair to channel B with even data on the mirror DIMM When mirroring is enabled via MCH configuration the memory subsystem maintains two copies of all data as described above and will retrieve requested data from either primary or mirror based on the state of system address bit 15 SA 15 Software may toggle which SA 15 polarity selects primary vs mirror via a configuration register bit setting SA 15 was chosen because it is the lowest system address bit that is always used to select the memory row address across all DRAM densities and technologies supported by the E7520 MCH The toggling of the primary read location based on an address bit will distribute request traffic across 46 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture the primary and mirror DIMMs thereby distributing the thermal image of the workload across all populated DIMM slots and reducing the chances of thermal based memory traffic throttling In the Mirrored operating state the occurrence of correctable and uncorrectable ECC errors are tracked and logged normally by the MCH and escalated to system interrupt events as specified by the configuration register settings associated with errors on the memory subsystem Counters implementing the leaky bucket function just described for on line DIMM sparing track the aggregate count of single bit and multiple bit errors on a per DIMM basis 3 3 6 7 Logging Mem
258. smatched VIDs Processor slot 1 is empty 1 5 4 2 Power fault DC power unexpectedly lost e g power good from the power supply was deasserted 1 5 4 3 Chipset control failure i 1 5 2 4 Front side bus select configuration error e g mismatched BSELs 1 5 4 4 Power control failure e g power good from the power supply did not respond to power request 6 5 Checkpoints 6 5 1 System ROM BIOS POST Task Test Point Port 80h Code The BIOS sends a 1 byte hex code to port 80 before each task The port 80 codes provide a troubleshooting method in the event of a system hang during POST Table 75 provides a list of the Port 80 codes and the corresponding task description 6 5 2 Diagnostic LEDs All port 80 codes are displayed using the Diagnostic LEDs found on the back edge of the baseboard The diagnostic LED feature consists of a hardware decoder and four dual color LEDs During POST the LEDs will display all normal POST codes representing the progress of the BIOS POST Each code will be represented by a combination of colors from the four LEDs The LEDs are capable of displaying three colors Green Red and Amber The POST codes are divided into two nibbles an upper nibble and a lower nibble Each bit in the upper nibble is represented by a Red LED and each bit in the lower nibble is represented by a green LED If both bits are set in the upper and lower nibbles then both Red and Green LEDs are lit resulting in an Amber color If
259. sors located in the server system Revision 1 0 123 C78844 002 Platform Management Intel Server Board SE7520JR2 Front Panel NMI Switch System Identify Button Reset Button Power Button Fault Status LED Identification LED BASEBOARD Front Panel Connectors PROCESSOR SOCKETS IERR 1 Aux IPMB l Connector PA Thermal Trip 1 Hot swap i Backplane LO CPU Voltage 1 Header H CPU Present 1 u o 2 gt a E Temperature Chip Set gt Sensor 5 A 2 FANS 6 PCI PME o FAN Pack To Power INTELLIGENT PLATFORM Connector S Distribution MANAGEMENT BUS IPMB o Board Y o a giga LAN 825510M Heceta L 18254161 PORO cad AEE Internal Flash NMI SDRs FRUs SEL Figure 22 mBMC Block Diagram 5 3 1 Power Supply Interface Signals The mBMC supports two power supply control signals Power On and Power Good The Power On signal connects to the chassis power subsystem through the chipset and is used to request power state changes asserted request Power On Power Good is a signal from the chassis power subsystem indicating current power state asserted power is on 124 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Platform Management The following figure shows the power supply control signals and their sources To turn on the system the mBMC asserts the Power On signal and waits for the Power Good signal to assert in response indicating tha
260. ssword Attempt 6Fh violation 06h Power On Off Sensor Power Unit Specific Power cycle 09h AC Lost 6Fh Platform Security Violation Power Unit Status Watchdog Initiated by power up Initiated by hard reset System boot Sensor Initiated Specific 1Dh 6Fh System Boot Initiated by warm reset Sensor Specific PEF Action 6Fh Sensor Platform Alert Platform Event Specific 6Fh System Event System PEF Event 12h Platform Allert 24h Trap generated Butt Sensor Power Button utton i id E Butt 04h Specifi 2 utton 14h peana Reset Button i 6Fh Timer Expired Sensor Hard Reset ER Ne ae Specific Power Down As 6Fh Power cycle Timer Interrupt 138 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Platform Management Event SDR Sensor Name Sensor Reading Event Offset Assert Readable Event Data PEF Record Type Type Triggers Deassert Value Offsets Action Type Physical Sensor General General Security Specific Chassis Chassis Trig Offset 02 05h 6Fh Intrusion Intrusion Pam nem mem vm wr iS Physical Security Violation CPU1 12v CPU2 12v BB 1 5V BB 1 8V BB 5V Voltage Threshold Fault LED Voltage Threshold Fault LED oh E e i Voltage Threshold Fault LED Voltage Threshold 02h 01h bn Voltage Threshold 02h 01h As amp De Analog R T ETEN Sg Action Voltage Threshold Fault LED Voltage Threshold Fault LED Voltage Threshold Fault LED BUCH Voltage Threshold
261. status 4 3 2 BIOS Boot Popup Menu The BIOS Boot Specification BBS provides for a Boot Menu Popup invoked by pressing the lt ESC gt key during POST The BBS Popup menu displays all available boot devices The list order in the popup menu is not the same as the boot order in BIOS setup it simply lists all the bootable devices from which the system can be booted Revision 1 0 83 C78844 002 System BIOS Intel Server Board SE7520JR2 Table 17 Sample BIOS Popup Menu Please select boot device 1 Floppy Hard Drives ATAPI CDROM LAN PXE EFI Boot Manager land to move selection Enter to select boot device ESC to boot using defaults 44 BIOS Setup Utility The BIOS Setup utility is provided to perform system configuration changes and to display current settings and environment information The BIOS Setup utility stores configuration settings in system non volatile storage Changes affected by BIOS Setup will not take effect until the system is rebooted The BIOS Setup Utility can be accessed during POST by using the lt F2 gt key 4 4 1 Localization The BIOS Setup utility uses the Unicode standard and is capable of displaying Setup screens in English French Italian German and Spanish The BIOS supports these languages for console strings as well Keyboard Commands While in the BIOS Setup utility the Keyboard Command Bar supports the keys specified in the following table Table 18 BIOS Setup Keyb
262. stem If this condition is detected an error 8196 is logged in the SEL An example of a faulty processor configuration may be when one installed processor supports a 533MHz front side bus while the other supports an 800MHz front side bus 3 1 6 4 Mixed Processor Families Processor families cannot be mixed in a system If this condition is detected an error 8194 is logged in the SEL 3 1 6 5 Mixed Processor Cache Sizes If the installed processors have mixed cache sizes an error 8192 will be logged in the SEL and an error 196 is reported to the Management Module The size of all cache levels must match between all installed processors Mixed cache processors are not supported 3 1 6 6 Jumperless Processor Speed Settings The Intel Xeon processor does not utilize jumpers or switches to set the processor frequency The BIOS reads the highest ratio register from all processors in the system If all processors are the same speed the Actual Ratio register is programmed with the value read from the High Ratio register If all processors do not match the highest common value between Revision 1 0 29 C78844 002 Functional Architecture Intel Server Board SE7520JR2 High and Low Ratio is determined and programmed to all processors If there is no value that works for all installed processors all processors not capable of speeds supported by the BSP are disabled and an error is displayed 3 1 6 7 Microcode IA 32 processors have t
263. stem power after one of the event occurrences the mBMC executes the following procedure 1 The mBMC asserts Power Supply PS Power On via the chipset and waits for the power subsystem to assert Power Good The system is reset 2 The mBMC initializes all sensors to their Power On initialization states The Init Agent is run 3 The mBMC attempts to boot the system by running the FRB algorithm if FRB is enabled 5 3 4 Power down Sequence To power down the system the mBMC effectively performs the sequence of power up steps in reverse order It occur as follows The mBMC asserts system reset 2 The mBMC de asserts the Power On signal via the chipset The power subsystem turns off system power upon de assertion of the Power On signal 5 3 5 System Reset Control 5 3 5 1 Reset Signal Output The mBMC asserts the System Reset signal on the baseboard to perform a system reset The mBMC asserts the System Reset signal before powering the system up After power is stable as indicated by the power subsystem Power Good signal the mBMC sets the processor enable state as appropriate and de asserts the System Reset signal taking the system out of reset The system reset signal responds to the control panel or IPMI commands 126 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Platform Management 5 3 5 2 Reset Control Sources The following table shows the reset sources and the actions taken by the system Table 48 System Reset
264. sults in eight 64 bit chunks 64 byte cache line from a single read or write In single channel mode two reads or writes are required to access a cache line of data 3 3 1 Memory Sizing The memory controller is capable of supporting up to 4 loads per channel for DDR 333 and DDR2 400 Memory technologies are classified as being either single rank or dual rank depending on the number of DRAM devices that are used on any one DIMM A single rank DIMM is a single load device ie Single Rank 1 Load Dual rank DIMMs are dual load devices ie Dual Rank 2 loads The Server Board SE7520JR2 provides the following maximum memory capacities based on the number of DIMM slots provided and maximum supported memory loads by the chipset e 24GB maximum capacity for DDR 266 e 16GB maximum capacity for DDR 333 and DDR2 400 The minimum memory supported with the system running in single channel memory mode is e 256MB for DDR 266 DDR 333 and DDR2 400 Supported DIMM capacities are as follows e DDR 266 Memory DIMM sizes include 256MB 512MB 1GB 2GB and 4GB e DDR 333 Memory DIMM sizes include 256MB 512MB 1GB 2GB and 4GB e DDR2 400 Memory DIMM sizes include 256MB 512MB 1GB 2GB and AGB DIMM Module Capacities SDRAM Parts SDRAM Technology Used 128Mb 256Mb 512Mb 1Gb Revision 1 0 37 C78844 002 Functional Architecture Intel Server Board SE7520JR2 X4 single row 256MB 512MB 1GB 2GB DIMMs on channel A are
265. t INT_A of the middle slot and INT_D of the top slot This pin will be used by 1U 2U 97 riser to bring the INT_B interrupt from the top and INT_C from the middle PCI slot down to the baseboard 96 SLOT ID FL not required as 95 the risers are unique 94 SCSI Interrupt A to ZCR This 93 pin will be used by 1U 2U riser to bring the INT C interrupt on the bottom PCI slot down to the baseboard SCSI Interrupt B to ZCR This 92 pin will be used by 1U 2U riser to bring the INT_D interrupt on the bottom PCI slot down to the baseboard 91 Highest PCI Slot SLOT3 90 89 Middle PCI Slot SLOT2 88 87 Middle PCI Slot SLOT2 86 85 84 83 End of x16 PCI Express connector 82 81 Lowest PCI slot SLOT1 80 79 Lowest PCI slot SLOT1 78 C78844 002 PCI Spec Signal GND HSIp 7 HSIn 7 GND Description ZCR_PRS From TDI of lowest slot only NT_L 5V 5V ZCR MSKI From TMS of lowest slot only ig r 5V INTA This pin will be connected on the 2U riser to INT_A of the bottom PCI slot INT_D of the middle slot and INT_C of the top slot INTC This pin will be used by 1U 2U riser to bring the INT_A interrupt from the top and INT_B from the middle PCI slot down to the baseboard Q Z REQ3 GND GNT3 GND RST GND Reserved KEY KEY Highest PCI Slot SLOT3 Highest PCI Slot SLOT3 5V Reserved GND GNT2 3 3V Was Vio 3 3V or 1 5V Middle PCI Slot SLOT2 Was Vio
266. t DC power is on gt mBMC PWR Button Y Power Good ChipSet Power Sub System PS ON Figure 23 Power Supply Control Signals The mBMC uses the Power Good signal to monitor whether the power supply is on and operational and to confirm whether the actual system power state matches the intended system on off power state that was commanded with the Power On signal De assertion of the Power Good signal generates an interrupt The mBMC uses this to detect either power subsystem failure or loss of AC power If AC power is suddenly lost the mBMC 1 Immediately asserts a system reset 2 Powers down the system 3 Waits for configured system off time then attempts to power the system back up depending on system power restore policy Revision 1 0 125 C78844 002 Platform Management Intel Server Board SE7520JR2 5 3 2 Power Control Sources The sources listed in the following table can initiate power up and or power down activity Table 47 Power Control Initiators External Signal Name or Capabilities Internal Subsystem P Power button Front control power button Turns power on or off mBMC Watchdog Timer Internal mBMC timer Turns power off or power cycle Platform Event Filtering Turns power off or power cycle Routed through command processor Turns power on or off or power cycle Power state retention Implemented via mBMC internal logic Turns power on when AC power returns 5 3 3 Power up Sequence When turning on the sy
267. t server keyboard input and video output are passed both to the local keyboard and video connections as well as to the remote console via the serial link Keyboard inputs from both sources are valid and video is displayed to both outputs As an option the system can be operated without a keyboard or monitor attached to the host system and can run entirely from the remote console Setup and any other text based utilities can be accessed through console redirection The BIOS will take the Setup values for Serial console redirection and map them to the ACPI SPCR tables The BIOS setup tokens for serial console will also read the BMC serial console values to sync up Text based console redirection is also supported over the Serial Over LAN SOL protocol SOL is built on top of the IPMI over LAN infrastructure specified in the IPMI 2 0 specification When the SOL feature is activated by establishing a LAN connection to the BMC and activating the SOL to be enabled the EMP based connectivity is disabled The IMM uses UDP datagrams to send SOL character data as SOL Messages The SOL Messages packet format follows that used for IPMI over LAN with extensions to support SOL Messages as a new message type SOL requires the support of the VT UTF 8 character set specified in the Microsoft Windows Net headless requirements from Microsoft The application displaying SOL data must be VT UTF 8 aware The console sends keystrokes in a UDP packet to the ser
268. t title as well WARNING The BIOS may incorrectly determine that a removable media is a hard drive if the media emulates a hard drive In this case the OS Watchdog timer will not be automatically disabled 150 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Error Reporting and Handling If the BIOS is going to boot to a known PXE compliant device then the BIOS reads a user option for OS Watchdog Timer for PXE Boots and either disables the timer or enables the timer with a value read from the option 5 10 15 or 20 minutes If the OS Watchdog Timer is enabled the timer is repurposed as an OS Watchdog Timer and is referred to by that title as well If the OS Watchdog Timer is enabled and if a boot password is enabled the BIOS will disable the OS Watchdog Timer before prompting the user for a boot password regardless of the OS Watchdog Timer option setting Also if the user has chosen to enter BIOS setup the timer will be disabled regardless of option settings Otherwise if the system hangs during POST before the BIOS disables the timer the BMC generates an asynchronous system reset ASR The BMC retains status bits that can be read by the BIOS later in the POST for the purpose of disabling the previously failing processor logging the appropriate event into the SEL and displaying an appropriate error message to the user If no IMM is present no processors will be disabled As the timer may be repurposed the BIOS and BMC will also
269. tain PCI configuration space accessed using mechanism 1 defined in the PCI Local Bus Specification If dual processors are used only the processor designated as the Boot Strap Processor BSP should perform PCI configuration space accesses Precautions must be taken to guarantee that only one processor performs system configuration Two Dword I O registers in the chipset are used for the configuration space register access e CONFIG_ADDRESS I O address OCF8h e CONFIG_DATA I O address OCFCh When CONFIG_ADDRESS is written to with a 32 bit value selecting the bus number device on the bus and specific configuration register in the device a subsequent read or write of CONFIG_DATA initiates the data transfer to from the selected configuration register Byte enables are valid during accesses to CONFIG_DATA they determine whether the configuration register is being accessed or not Only full Dword reads and writes to CONFIG_ADDRESS are recognized as a configuration access by the chipset All other I O accesses to CONFIG ADDRESS are treated as normal I O transactions 78 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture 3 5 3 1 CONFIG_ADDRESS Register CONFIG_ADDRESS is 32 bits wide and contains the field format shown in the following figure Bits 23 16 choose a specific bus in the system Bits 15 11 choose a specific device on the selected bus Bits 10 8 choose a specific function in a multi function d
270. ted If a bad processor is removed from the system the BMC automatically detects this condition and clears the status flag for that processor during the next boot Three states are possible for each processor slot e Processor installed status only indicates processor has passed BIOS POST e Processor failed The processor may have failed FRB2 FRB3 or BIST and it has been disabled e Processor not installed status only indicates the processor slot has no processor in it Additional information on the FRB may be found in the Sahalee Baseboard Management Controller EPS 6 2 Memory Error Handling The chipset will detect and correct single bit errors and will detect all double bit memory errors The chipset supports 4 bit single device data correction SDDC when in dual channel mode Both single bit and double bit memory errors are reported to baseboard management by the BIOS which handles SMI events generated by the MCH Memory Error Handling can be enabled or disabled in system BIOS Setup 6 2 1 Memory Error Handling in RAS Mode The MCH supports two memory RAS modes Sparing and Mirroring Enabling of Sparing or Mirroring feature are mutually exclusive Use system BIOS Setup to configure memory RAS mode 152 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Error Reporting and Handling The following table shows memory error handling with both a mBMC and Sahalee BMC Memory with RAS mode Sparing mode
271. tens 48 Table 8 PCI Configuration IDs and Device Numbers sess 51 Table 9 PCI Interrupt RQUUINO SHA Olesa aida 53 Table 10 Interrupt Definitions esses nennen nnne nnne 54 Table 11 Video Modes T senes en nne t nnne tenth nien nnen ener nnne 63 Table 12 Video Memory Interface eerta accetta rta o eee ia 63 Table 13 Super WO GPIO Usage Table n eter RR ete Ran RR ERR en n ER bn ser 65 Table 14 Serial A Header Pin out esses nennen 67 Table 15 SMM Space Table sss nee ensem 75 Mable 16 110 Ma picts EEUU EM 76 Table 17 Sample BIOS Popup Menu sse eene nennen nennen 84 Table 18 BIOS Setup Keyboard Command Bar Options sss 84 Table 19 BIOS Setup Main Menu Options esses nnne 85 Table 20 BIOS Setup Advanced Menu Options sse 86 Table 21 BIOS Setup Processor Configuration Sub menu Options ssussss 87 Table 22 BIOS Setup IDE Configuration Menu Options ccccccococononcncniccnananananrncnnnnnnnnnnnnnnnnnnos 88 Table 23 Mixed P ATA S ATA Configuration with only Primary P ATA seeeeees 89 Table 24 BIOS Setup IDE Device Configuration Sub menu Selections 90 Table 25 BIOS Setup Floppy Configuration Sub menu Selections suuuuusse 91 Table 26 BIOS Setu
272. terface EFI When EFI is selected as a boot option the BIOS will support an EFI Specification 1 10 compliant environment More details on EFI are available at http developer intel com technology efi index htm 4 8 1 EFI Shell The EFI Shell is a special type of EFI application that allows EFI commands and other EFI applications to be launched The BIOS implements an EFI shell in flash and the shell can be invoked from the BIOS provided EFI environment The EFI shell provided in flash implements all the commands specified in the EFI1 1ShellCommands pdf document that comes with the EFI sample implementation revision 1 10 14 62 available from http developer intel com technology efi main_sample htm 4 9 Operating System Boot Sleep and Wake The IPMI 1 5 specification chapter 22 10 and 22 11 has provisions for server management devices to set certain boot parameters by setting boot flags Among the boot flags which are parameter 5 in the IPMI specification the BIOS checks data 1 3 for forced boot options The BIOS supports force boots from PXE HDD FDD and CD On each boot the BIOS determines what changes to boot options have been set by invoking the Get System Boot Options Command takes appropriate action and clears these settings 4 9 1 Microsoft Windows Compatibility Intel Corporation and Microsoft Corporation co author design guides for system designers using Intel processors and Microsoft operating s
273. th an Intel Management Module Professional or Advanced CMOS can be cleared using buttons on the system Control Panel that will both assert the BMC CMOS Revision 1 0 217 C78844 002 Miscellaneous Board Information Intel Server Board SE7520JR2 Clear state and power the system up This feature can be enabled or disabled via the CMOS Clear Options command The following sequence of events must occur to invoke the Control Panel CMOS Clear feature 1 Standby power must be on system power must be off and the feature enabled 2 The control panel reset button must be pressed and held for at least 4 seconds 3 With the control panel reset button still pressed the control panel power button must be pressed The IMM Sahalee BMC produces a single beep through the system speaker to confirm the CMOS clear button sequence The Sahalee BMC does not assert the CMOS Clear hardware signal BIOS checks for BMC CMOS Clear state using the CMOS Clear Options command at each boot to determine if the Sahalee BMC is requesting a CMOS Clear operation The BMC CMOS Clear state remains active until one of the following events occurs It is forced off using a CMOS Clear Options command this is the normal operational case by BIOS The reset button is pressed The power button is pressed and released The system is powered off 9 4 BIOS Recovery Operation The BIOS Recovery Operation should be attempted if for any reason the BIOS gets corrupted causing
274. that console redirection is enabled it will read the current baud rate and pass this value to the appropriate management controller via the IPMB Through the redirection capabilities of the BMC on Intel platforms this serial port UART input output stream is further redirected and sent over a platform LAN device as a packetized serial byte stream This BMC function is called Serial over LAN or SOL and further optimizes space requirements and server management capability SOL is only supported by the IMM 5 Platform Management The Platform Management sub system on the Server Board SE7520JR2 consists of a micro controller communication buses sensors system BIOS and server management firmware It provides for three different levels of platform management On Board Platform Instrumentation based around the National Semiconductor PC87431M mini Baseboard Management Controller MBMC the Intel Management Module Professional Edition and the Intel Management Module Advanced Edition which are based on Intel s Sahalee BMC As shipped the baseboard comes standard with On Board Platform Instrumentation A 120 pin connector on the baseboard provides the interface to the optionally installed Intel Management Modules IMM The following table summarizes the supported features for each management level Table 45 Suppoted Management Features by Tier Intel Intel Management Management On Board Module Module Platform Profession
275. the system event log Double bit errors in the memory array are mapped to the SMI because the mBMC cannot determine the location of the bad DIMM The double bit errors may have corrupted the contents of SMRAM The SMI handler will log the failing DIMM number to the mBMC if the SMRAM contents are still valid The ability to isolate the failure down to a single DIMM may not be available on certain platforms and or during early POST 6 3 5 System Limit Error The BMC monitors system operational limits It manages the A D converter defining voltage and temperature limits as well as fan sensors and chassis intrusion Any sensor values outside of specified limits are fully handled by the BMC The BIOS does not generate an SMI to the host processor for these types of system events 6 3 6 Processor Failure The BIOS detects any processor BIST failures and logs the event The failed processor can be identified by the first OEM data byte field in the log For example if processor 0 fails the first OEM data byte will be 0 The BIOS depends upon the BMC to log the watchdog timer reset event If an OS device driver is using the watchdog timer to detect software or hardware failures and that timer expires an Asynchronous Reset ASR is generated which is equivalent to a hard reset The POST portion of the BIOS can query the BMC for a watchdog reset event as the system reboots and then log this event in the SEL 6 3 7 Boot Event The BIOS downloads the
276. ther CBCs Together they bridge the IPMB buses of multiple chassis Common Enabling Kit Challenge Handshake Authentication Protocol In terms of this specification this describes the PC AT compatible region of battery backed 128 bytes of memory which normally resides on the baseboard Direct Platform Control EEPROM Electrically erasable programmable read only memory EHCI Enhanced Host Controller Interface Emergency management port External Product Specification Intelligent Chassis Management Bus Internal error 222 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Glossary Term IFB I O and firmware bridge IMM Intel Management Module Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface In target probe 1024 bytes l Li L L L Media Access Control 1024 KB TP B CS LAN CD ED PC UN MAC MB MCH MD2 MD5 Ms Mux IC MI BF EM hm EF EP IA LD MI WM RAM mBMC National Semiconductor PC87431x mini BMC Memory Controller Hub Message Digest 2 Hashing Algorithm O O 0 RASUM Reliability availability serviceability usability and manageability SECC Single edge connector cartridge K K N N P P P P P P Revision 1 0 223 C78844 002 Glossary Intel Server Board SE7520JR2 LE SS S ART UDP UTC ID IF User Datagram Protocol Ur UTG Universalime coordi UART universal asynchrono
277. tion configuration Fi Gases overt onan event logging Selects submenu submenu vent toa EE NMI on SERR A a EU enabled NMI is generated on Enabled SERR and logged Assert NMI on PERR Disabled Enabled SERR option needs to be If enabled NMI is generated Grayed out if NMI on SERR is disabled enabled to activate this option Resume on AC Power Loss Stays Off Determines the mode of Last State is only FRB 2 Policy Revision 1 0 operation if a power loss occurs Stays off the system will remain off once power is restored Power On boots the system after power is restored Power On Last State Disable BSP Do not disable BSP Retry on Next Boot Disable FRB2 Timer This controls action if the boot processor will be disabled or not C78844 002 displayed if the Intel Management Module is present When displayed Last State is the default When set to Stays Off Power Switch Inhibit is disabled Disable BSP and Do not disable BSP are only displayed if the Intel Management Module is present 99 System BIOS Intel Server Board SE7520JR2 Options Help Text Late POST Timeout Disabled This controls the time limit for 5 minutes add in card detection The system is reset on timeout 10 minutes 15 minutes 20 minutes Hard Disk OS Boot Timeout Disabled This controls the time limit 5 minutes allowed for booting an operating system from a
278. tion DT clocking e Packetized protocol e Paced transfers 58 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture e Quick arbitrate and select QAS e Skew compensation Inter symbol interference ISI compensation e Cyclic redundancy check CRC Domain validation technology The LSI53C1030 contains the following SCSI performance features Supports Ultra320 SCSI Paced transfers using a free running clock 320 MB s data transfer rate on each SCSI channel Mandatory packetized protocol Quick arbitrate and select QAS Skew compensation with bus training Transmitter precompensation to overcome ISI effects for SCSI data signals Retained training information RTI Offers a performance optimized architecture Three ARM966E S processors provide high performance with low latency Two independent Ultra320 SCSI channels Designed for optimal packetized performance Uses proven integrated LVDlink transceivers for direct attach to either LVD or SE SCSI buses with precision controlled slew rates Supports expander communication protocol ECP Uses the Fusion MPT Message Passing Technology drivers to provide support for Windows Linux and NetWare operating systems The LSI53C1039 has a 133 MHz 64 bit PCI PCI X interface that supports the following PCI features Operates at 33 MHz or 66 MHz PCI Operates at up to 133 MHz PCI X Supports 32 bit or 64 bit data Supports 32 bit or 64 bit addressin
279. tly from the main processor s the management controller monitoring and logging functions and the out of band interfaces can remain operative even under failure conditions that cause the main processors OS or local system software to stop The management controller also provides the interface to the non volatile Sensor Data Record SDR Repository IPMI Sensor Data Records provide a set of information that system management software can use to automatically configure itself for the number and type of IPMI sensors e g temperature sensors voltage sensors etc in the system This information allows management software to automatically adapt itself to the particular system enabling the development of management software that can work on multiple platforms without requiring the software to be modified The following is a list of the major functions that are managed by either or both the mBMC and Sahalee BMC e Sensors and Sensor Polling e FRU Information Access FRU Field Replaceable Unit information is non volatile storage for serial number part number asset tag and other inventory information for the baseboard and chassis The FRU implementation on SE7520JR2 includes write support for OEM specific records e Autonomous Event Logging The management controller autonomously polls baseboard sensors and generates IPMI Platform Events also called Event Messages when an event condition is detected The events are automatically logge
280. to ACPI mode The BIOS responds by setting up all system chipset specific configuration required to support ACPI and sets the SCI_EN bit as defined by the ACPI specification The system automatically returns to legacy mode on hard reset or power on reset The BIOS supports SO S1 S4 and S5 states S1 and S4 are considered sleep states The ACPI specification defines the sleep states and requires the system to support at least one of them While entering the S4 state the operating system saves the context to the disk and most of the system is powered off The system can wake on a power button press or a signal received from a wake on LAN compliant LAN card or onboard LAN modem ring PCI power management interrupt or RTC alarm The BIOS performs complete POST upon wake up from S4 and initializes the platform The system can wake from the S1 state using a PS 2 keyboard mouse or USB device in addition to the sources described above The wake up sources are enabled by the ACPI operating systems with cooperation from the drivers the BIOS has no direct control over the wakeup sources when an ACPI operating system is loaded The role of the BIOS is limited to describing the wakeup sources to the operating system and controlling secondary control status bits via the DSDT table The S5 state is equivalent to operating system shutdown No system context is saved 4 9 2 1 Sleep and Wake Functionality The BIOS supports a control panel powe
281. trator password must be entered during system configuration using the BIOS setup menu The maximum length of the password is seven characters The password cannot have characters other than alphanumeric a z A Z 0 9 Once set a password can be cleared by entering the password change mode and pressing enter twice without inputting a string All setup fields can be modified when entering the administrator password The user access level setting in the BIOS setup Security menu controls the user access level The administrator can choose No Access to block the user from accessing any setup features Limited Access will allow only the date time fields and the user password to be changed View Only allows the user to enter BIOS setup but not change any settings Administrator has control over all fields in the setup including the ability to clear the user password If the user enters three wrong passwords in a row during the boot sequence the system will be placed into a halt state This feature makes it difficult to break the password by trial and error The BIOS Setup may provide an option for setting the EMP password However the EMP password is only utilized by the mBMC this password does not affect the BIOS security in any way nor does the BIOS security engine provide any validation services for this password EMP security is handled primarily through the mBMC and EMP utilities Revision 1 0 105 C78844 002
282. ts PIO IDE transfers up to 16 Mbytes sec and Ultra ATA transfers up 100 Mbytes sec It does not consume ISA DMA resources The IDE interface integrates 16x32 bit buffers for optimal transfers The ICH5 R s IDE system contains two independent IDE signal channels They can be electrically isolated independently They can be configured to the standard primary and secondary channels four devices The Server Board SE7520JR2 provides interfaces to both 34 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture IDE channels of the ICH5R One channel is accessed through the 40 pin connector on the baseboard The signals of the second channel are routed to the 100 pin backplane connector for use in either the Intel Server Chassis SR1400 or SR2400 when integrated with a backplane for slim line optical drive use 3 2 3 3 SATA Controller The SATA controller supports two SATA devices providing an interface for SATA hard disks and ATAPI devices The SATA interface supports PIO IDE transfers up to 16 Mb s and Serial ATA transfers up to 1 5 Gb s 150 MB s The ICH5 R s SATA system contains two independent SATA signal ports They can be electrically isolated independently Each SATA device can have independent timings They can be configured to the standard primary and secondary channels 3 2 3 4 Low Pin Count LPC Interface The ICH5 R implements an LPC Interface as described in the Low Pin Count Interface Specification Revision
283. ull speed and low speed capable ICH5 R s port routing logic determines whether a USB port is controlled by one of the UHCI controllers or by the EHCI controller 3 2 3 8 RTC The ICH5 R contains a Motorola MC 146818A compatible real time clock with 256 bytes of battery backed RAM The real time clock performs two key functions keeping track of the time of day and storing system data even when the system is powered down The RTC operates on a 32 768 KHz crystal and a separate 3 V lithium battery The RTC supports two lockable memory ranges By setting bits in the configuration space two 8 byte ranges can be locked to read and write accesses This prevents unauthorized reading of passwords or other system security information The RTC supports a date alarm that allows for scheduling a wake up event up to 30 days in advance 3 2 3 9 General Purpose I O GPIO Various general purpose inputs and outputs are provided for custom system design The number of inputs and outputs varies depending on the ICH5 R configuration All unused GPI pins are either pulled high or low so that they are at a predefined level and do not cause undue side effects 3 2 3 10 Enhanced Power Management The ICH5 R s power management functions include enhanced clock control local and global monitoring support for 14 individual devices and various low power suspend states such as Suspend to DRAM and Suspend to Disk A hardware based thermal management circuit
284. upported 1280x1024 43 60 Supported Supported Supported Supported 1280x1024 70 72 Supported Supported Supported 1600x1200 60 66 Supported Supported Supported Supported 1600x1200 76 85 Supported Supported Supported 3D Mode Refresh Rate Hz 3D Video Mode Support with Z Buffer Enabled 8 bpp 16 bpp 24 bpp 32 bpp 640x480 60 72 75 90 100 Supported Supported Supported Supported 800x600 60 70 75 90 100 Supported Supported Supported Supported 1024x768 60 72 75 90 100 Supported Supported Supported Supported 1280x1024 43 60 70 72 Supported Supported 1600x1200 60 66 76 85 Supported 3D Mode Refresh Rate Hz 3D Video Mode Support with Z Buffer Disabled 8 bpp 16 bpp 24 bpp 32 bpp 640x480 60 72 75 90 100 Supported Supported Supported Supported 800x600 60 70 75 90 100 Supported Supported Supported Supported 1024x768 60 72 75 90 100 Supported Supported Supported Supported 1280x1024 43 60 70 72 Supported Supported Supported 1600x1200 60 66 76 85 Supported Supported 3 4 7 2 Video Memory Interface The memory controller subsystem of the Rage XL arbitrates requests from direct memory interface the VGA graphics controller the drawing coprocessor the display controller the video scalar and hardware cursor Requests are serviced in a manner that ensures display integrity and maximum CPU coprocessor drawing performance The Server Board SE7520JR2 supports an 8MB 512Kx32bitx4 Banks SDRAM device for video memory The following table shows th
285. us receiver transmitter 224 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Reference Documents Reference Documents Refer to the following documents for additional information Intel Server Board SE7520JR2 Server Management External Architecture Specification EAS Intel Corporation Intel Server Board SE7520JR2 BIOS External Product Specification Intel Corporation Intel Server Board SE7520JR2 BMC External Product Specification Intel Corporation Mini Baseboard Management Controller mBMC Core External Product Specification Intel Corporation Silverwood Server Management Firmware External Architecture Specification EAS Intel Corporation Intel Server Chassis SR1400 and SR2400 Technical Product Specification Intel Corporation Sahalee Baseboard Management Controller Core External Product Specification Sahalee BMC Core EPS for IPMI 2 0 Systems Intel Corporation Sahalee Platform Information Area External Product Specification Sahalee PIA EPS ver 1 0 Intel Corporation Advanced Configuration and Power Interface Specification Intel Corporation Microsoft Corporation Toshiba Corporation Intelligent Chassis Management Bus ICMB Specification Version 1 0 Intel Corporation Hewlett Packard Company NEC Corporation Dell Computer Corporation Intelligent Platform Management Bus Communications Protocol Specification Version 1 0 1998 Intel Corporation Hewlett Packard Company NEC Corporation Dell Computer
286. use If detected the USB hub enables them 3 4 10 Super I O Chip Legacy I O support is provided by using a National Semiconductor PC87427 Super I O device This chip contains all of the necessary circuitry to control two serial ports one parallel port floppy disk and PS 2 compatible keyboard and mouse Of these the Server Board SE7520JR2 supports the following e GPIOs e Two serial ports e Floppy Controller e Keyboard and mouse controller e Wake up control 3 4 10 1 GPIOs The National Semiconductor PC87427 Super I O provides nine general purpose input output pins that the Server Board SE7520JR2 utilizes The following table identifies the pin and the signal name used in the schematic Table 13 Super I O GPIO Usage Table GPIO04 MDAT MS_DAT GPIO05 XRDY GPIO06 XIRQ BMC_SYSIRQ GPIO07 HFCKOUT SIO CLK 40M BMC GPIOE10 XA11 VO I E 1 XBUS A lt 11 gt Revision 1 0 65 C78844 002 Functional Architecture 66 Pin Name IO GPIO SETSz0JR2Use e eoe oe XSUS Ac S onm WOMEN esae 24 I O XBUS D lt 7 gt 7 1 0 I 2 GP1033 XD4 O XBUS_D lt 4 gt 28 GPIO34 XD3 XBUS_D lt 3 gt GMOsPWETNI io re femosrsioswit io TP 1 0 1 0 GPO60 XSTB2 XCNF2_L iO PU_XBUS_XCNF2 GPO61 XSTB1 XCNF1_L XBUS_XSTB1_L PU_SIO_ACBSA PU_SIO_CKIN48 GPO63 ACBSA GPO64 WDO_L CKIN48 or fo fo C78844 002 Intel Server Board SE7520JR2 Revision 1 0 Intel Server Board SE7520JR2
287. ust be configured so that the local screen does not display memory counts device status etc It must present a clean BIOS start up The only screen display allowed is the OEM splash screen and copyright notices The Quiet Boot process is controlled by a Setup Quiet Boot option If this option is set the BIOS displays an activity indicator at the top of the screen and a logo splash screen in the middle section of the screen on the local console The activity indicator measures POST progress and continues until the operating system gains control of the system The splash screen covers up any diagnostic messages in the middle section of the screen While the logo is being displayed on the local console diagnostic messages are being displayed on the remote text consoles Quiet Boot may be disabled by disabling the Setup Quiet Boot option or by the user pressing the lt Esc gt key while in Quiet Boot mode If Quiet Boot is disabled the BIOS displays diagnostic messages in place of the activity indicator and the splash screen With the use of an Intel supplied utility the BIOS allows OEMs to override the standard Intel logo with one of their own design 4 3 1 3 POST Activity Window The bottom portion of the screen is reserved for the POST Activity window On a graphics console the window is 640x48 On a text console the window is 80x2 The POST Activity window is used to display prompts for hot keys as well as provide information on system
288. v Red s mss mme C78844 002 Design and Environmental Specifications 205 Design and Environmental Specifications Intel Server Board SE7520JR2 enclosure This grounding must be designed to ensure passing the maximum allowed Common Mode Noise levels The power supply shall be provided with a reliable protective earth ground All secondary circuits shall be connected to protective earth ground Resistance of the ground returns to chassis shall not exceed 1 0 mQ This path may be used to carry DC current 8 2 3 Remote Sense The power supply has remote sense return ReturnS to regulate out ground drops for all output voltages 3 3V 5V 12V1 12V2 12V3 12V and 5VSB The power supply uses remote sense 3 3VS to regulate out drops in the system for the 3 3V output The 5V 12V1 12V2 12V3 12V and 5VSB outputs only use remote sense referenced to the ReturnS signal The remote sense input impedance to the power supply must be greater than 2009 on 3 3VS 5VS This is the value of the resistor connecting the remote sense to the output voltage internal to the power supply Remote sense must be able to regulate out a minimum of 200mV drop on the 3 3V output The remote sense return ReturnS must be able to regulate out a minimum of 200mV drop in the power ground return The current in any remote sense line shall be less than 5mA to prevent voltage sensing errors The power supply must operate within s
289. ver If the session ID of SOL matches the session ID in boot block info then the BIOS starts serial based redirection services If the session IDs do not match the BIOS follows the path specified in the IPMI section and launches LAN or serial console redirection services BIOS Console redirection terminates before giving control to an operating system The operating system is responsible for continuing the Console Redirection after that point BIOS console redirection is a text based console and any graphical data such as a logo is not redirected 112 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Platform Management BIOS Console Redirection is intended to accomplish the implementation of VT UTF8 console redirection support in Intel server BIOS products That implementation will meet the functional requirements set forth in the Microsoft Whistler WHQL requirements for headless operation of servers as well as maintain a necessary degree of backward compatibility with existing Intel server BIOS products and meet the architectural requirements of Intel server products currently in development The server BIOS has a console that is intended to interact with a display and keyboard combination The BIOS instantiates sources and sinks of input output data in the form of BIOS Setup screens Boot Manager screens Power On Self Test POST informational messages and hotkey escape sequence action requests If the BIOS determines
290. ver board does not operate correctly when used outside any of their published operating or non operating limits 20 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Server Board Overview 2 Server Board Overview The Intel Server Board SE7520JR2 is a monolithic printed circuit board with features that were designed to support the high density 1U and 2U server markets 2 1 Server Board SE7520JR2 SKU Availability In this document the name SE7520JR2 is used to describe the family of boards that are made available under a common product name The core features for each board will be common however each board will have the following distinctions Product Code Feature Distinctions SE7520JR2SCSID2 Onboard SCSI Onboard SATA RAID DDR2 400 MHz SE7520JR2SCSID1 Onboard SCSI Onboard SATA RAID DDR 266 333 MHz SE7520JR2ATAD2 Onboard SATA RAID DDR2 400 MHz SE7520JR2ATAD1 Onboard SATA RAID DDR 266 333 MHz Throughout this document all references to the Server Board SE7520JR2 will refer to all four board SKUs unless specifically noted otherwise The board you select to use may or may not have all the features described based on the listed board differences 2 2 Server Board SE7520JR2 Feature Set Dual processor slots supporting 800MHz Front Side Bus FSB Intel Xeon processors e Intel E7520 Chipset MCH PXH ICH5 R e Two PCI riser slots o Riser Slot 1 Supports low profile
291. voltages stay within regulation after loss of 21 msec AC Tpwok_holdup Delay from loss of AC to de assertion of PWOK 20 msec Tpson_on_delay Delay from PSON active to output voltages within regulation 5 400 msec limits T pson pwok Delay from PSON deactive to PWOK being de asserted 50 msec Tpwok_on Delay from output voltages within regulation limits to PWOK 100 1000 msec asserted at turn on T pwok_off Delay from PWOK de asserted to output voltages 3 3V 5V 1 msec 12V 12V dropping out of regulation limits Tpwok_low Duration of PWOK being in the de asserted state during an 100 msec off on cycle using AC or the PSON signal Tsb_vout Delay from 5VSB being in regulation to O Ps being in 50 1000 msec regulation at AC turn on TsvsB holdup Time the 5VSB output voltage stays within regulation after 70 msec loss of AC 210 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Design and Environmental Specifications AC Input le sy Tvout_holdup Tice Riu e A E gt Po i i Tsb_on_delay gt D N lt Tsb_on_delay PWOK j lt gt T svsB holdup i Tpson on delay lt AC turn on off cycle i PSON turn on off cycle gt Figure 29 Turn On Off Timing Power Supply Signals 8 2 14 Residual Voltage Immunity in Standby Mode The PS supply should be immune to any residual voltage placed on its outputs Typically a leakage voltage thr
292. xit system setup without saving any changes er and ESC key can be used for this operation xi Discard N A Discards changes done so far to any of the setup questions Changes F7 key can be used for this operation Load Setup N A Load Setup Default values for all the setup questions Defaults F9 key can be used for this operation Load Custom N A Load custom defaults Defaults Save Custom N A Save custom defaults Defaults 4 5 Rolling BIOS and On line Updates The Online Update nomenclature refers to the ability to update the BIOS while the server is online and in operation as opposed to taking the server out of operation while performing a BIOS update The rolling BIOS nomenclature refers to the capability of having two copies of BIOS the current one in use and a second BIOS to which an updated BIOS version can be written When ready the system can roll forward to the new BIOS In case of a failure with the new version the system can roll back to the previous version 102 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 System BIOS The BIOS relies on specialized hardware and additional flash space to accomplish online update rolling of the BIOS To this end the flash is divided into two partitions primary and secondary The active partition from which the system boots shall be referred to as the primary partition The AMI FLASH update suite and Intel Online updates preserve the existing BIOS image on the primary partit
293. yserville3 is an Intel internal code name feature of the Intel SpeedStep Technology This feature changes the processor operating ratio and voltage similar to the Thermal Monitor 2 TM2 feature It must be used in conjunction with the TM1 or TM2 feature The BIOS implements the GV3 feature in conjunction with the TM2 feature 3 1 6 11 EM64T Technology Support The system BIOS on the Server Board SE7520JR2 supports the Intel Extended Memory 64 technology EM64T of the Intel Xeon Processors There is no BIOS setup option to enable or disable this support The system will be in IA 32 compatibility mode when booting to an OS To utilize this feature a 64 bit capable OS and OS specific drivers are needed 3 1 7 Multiple Processor Initialization IA 32 processors have a microcode based bootstrap processor BSP arbitration protocol On reset all of the processors compete to become the BSP If a serious error is detected during its Built in Self Test BIST that processor does not participate in the initialization protocol A single processor that successfully passes BIST is automatically selected by the hardware as the 30 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Functional Architecture BSP and starts executing from the reset vector F000 FFFOh A processor that does not perform the role of BSP is referred to as an application processor AP The BSP is responsible for executing the BIOS power on self test POST and p
294. ystems These documents are updated yearly to address new requirements and current trends 108 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 System BIOS PC200x specifications are intended for systems that are designed to work with Windows 2000 and Windows XP class operating systems The Hardware Design Guide HDG for the Windows XP platform is intended for systems that are designed to work with Windows XP class operating systems Each specification classifies the systems further and has requirements based on the intended usage for that system For example a server system that will be used in small home office environments has different requirements than one used for enterprise applications The BIOS supports HDG 3 0 4 9 2 Advanced Configuration and Power Interface ACPI The BIOS is ACPI 2 0c compliant The primary role of the BIOS is to provide ACPI tables During POST the BIOS creates the ACPI tables and locates them in extended memory above 1MB The location of these tables is conveyed to the ACPl aware operating system through a series of tables located throughout memory The format and location of these tables is documented in the publicly available ACPI specification To prevent conflicts with a non ACPl aware operating system the memory used for the ACPI tables is marked as reserved As described in the ACPI specification an ACPl aware operating system generates an SMI to request that the system be switched in
295. zing module not executed start memory refresh and do D3 G A memory sizing in Bootblock code Do additional chipset initialization Re enable CACHE Verify that flat mode is enabled 170 Revision 1 0 C78844 002 Intel Server Board SE7520JR2 Error Reporting and Handling Diagnostic LED Decoder Description Checkpoint G Green R Red A Amber msg LsB D4 A OFF Test base 512KB memory Adjust policies and cache first 8MB Set stack D5 A OFF A Bootblock code is copied from ROM to lower system memory and control is given to it BIOS now executes out of RAM Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced Main BIOS checksum is tested If BIOS A G recovery is necessary control flows to checkpoint EO See Bootblock Recovery Code Checkpoints section of document for more information Restore CPUID value back into register The Bootblock Runtime D7 A G A interface module is moved to system memory and control is given to it Determine whether to execute serial flash OFF The Runtime module is uncompressed into memory CPUID information is stored in memory Store the Uncompressed pointer for future use in PMM Copying Main BIOS into memory Leaves all RAM below 1MB Read Write including E000 and F000 shadow areas but closing SMRAM Restore CPUID value back into register Give control to BIOS POST ExecutePOSTKernel See POST Code Checkpoints section of document for more information

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