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Intel SE7221BK1-E User's Manual

1. 1 2 Server Board OvervieW ii 2 2 1 SE7221BK1 E Feature Set e Rete E UU Ride EE MER RE Fu Eta Ud dus 2 9 Functional AFChITec tUe Dn Sar ry Ra 5 3 1 Processor SUDSVSIOITI OP Rte Eu b 5 3 1 1 Processor dll P 5 3 1 2 Reset Configuration Logic 5 3 1 3 Processor Module Presence Detection 5 3 1 4 Processor SUPPOR t 5 3 1 5 Interrupts and APIG ein per RR e ERR 6 3 2 Memory Subsystem dade ut addet iuc tum mo 6 4 The Intel E7221 ChlBSet cid octo dn mas tir iii etit yp up rn hom cod 9 4 1 1 GMCH Memory Architecture Overview 2 2 10 4 1 2 Graphics Memory Controller Hub m 10 4 1 3 VEG Patera te ET 11 4 2 13 4 2 1 Seal o 13 4 2 2 sies DE 14 4 2 3 System Health SUPPO pete opcra trip pU eie cte rond 14 5 J O SUDSVSIEID oie ite te duo 14 5 1 DOLSUDSySIQr He Sa 14 5 1 1 P32 A 32 bit 33 MHz PCI
2. 1 INTRUSION 9 0 WM Q 22 861 i 2 4 RENT lf 251 m i USB LN m w 1 17 Ad ii HD LED il I 5 148 L 1 T JUNPER 0 E T tines SATA SATA p ii MUT SEI FRONT PANEL 2X 8 094 i M 1 105 591 tiran e 233 08 ve 1 I SATA FLOPPI 3 8 4 PLACES 31 EEB x NAIN POWER 1 011 Fal FAN Figure 11 SE7221BK1 E Server Board Mechanical Drawing 81 SE7221BK1 E Technical Product Specification The following figures show the shield mechanical drawings for use in pedestal mount applications such as the Intel amp Server Chassis SC5200 for both sku s SE7221BK1 E and SE7221BK1 E LX 3 42 p 11 240 5 91 10 01 14 101 by 2 SECTION Figure 12 sku 1 Pedestal mount I O shield mechanical drawing 82 Revision 1 3 SE7221BK1 E Technical Product Specification ETAIL 41 122 08 4 41 SEE DETAIL 145 4 SECTION Figure 13 sku 2 Pedestal mount I O shield mechanical drawing 83 Glossary SE7221BK1 E Technical Product Specification Glossary This appendix contains important terms used in t
3. 444041 14 5 1 2 2 66 PCI X Subsystem SE7221BK1LX sku only 15 5 1 3 64 66 100 MHz PCI X 444 44 16 c ER 17 5 2 Video Go troller O P 17 5 3 Network Interface Controller 17 5 3 1 NIC Connector and Status 17 5 4 erc UU 18 5 4 1 Legacy Interrupt Routing 18 542 dd 18 54 37 Serialized IRQ SUPPO 19 Revision 1 3 7221 1 Technical Product Specification 5 5 a 19 6 AGPIEIniplementatlon reiniciar 23 6 1 7216141 E to un uh MEE ER M ceto o me 23 6 1 1 Front Panel 23 6 1 2 Wake up Sources ACPI and Legacy 24 1 A A ca ratione dro batur ra os roges 25 7 1 Main Power Connector rns kn eve Rabe Fer Pha RA De 25 7 2 lG FAA MORTUO TET 26 7 3 Front Panel
4. 45 BIOS Setup CDROM Drives Sub menu Selections 45 BIOS Setup CDROM Drives Sub menu Selections 46 BIOS Setup CDROM Drives Sub menu Selections 47 BIOS Setup Security Menu 47 BIOS Setup Server Menu 48 BIOS Setup System Management Sub menu Selections 49 BIOS Setup Serial Console Features Sub menu Selections 50 BIOS Setup Event Log Configuration Sub menu Selections 50 BIOS Setup Exit Menu Selections 51 POST Error Beep CodeS loei pd 56 SE7221BK1 E Technical Product Specification Table 68 BIOS Recovery Beep 57 Table 69 POST Error Messages and 57 Table 70 POST Gode Checkpoints e ER eel xev ap RE Eee e 58 Table 71 Bootblock Initialization Code 61 Table 72 Bootblock Recovery Code Checkpoints nr 62 Table 73 DIM Code Checkpoints 63 Table 74 ACPI Runtime Checkpoints
5. 79 Replacing the Back Up Battery ce eee ene tend oe 79 Calculated Mean Time Between Failures 80 Mechanical SpecrficallOnis Re e i 80 vii SE7221BK1 E Technical Product Specification List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 viii Processor Support ente ett planea 6 Memory Bank Labels DIMM Population 8 Characteristics of Dual Single Channel Configuration with without Dynamic Mode 9 oupported DDH2TOdUlBS oit Pet vette uA 10 PCI Bus Segment 0 4044440 nennen 14 Contig rauoriDS OR RE 15 P32 A Arbitration Connections 15 P32 B Configuration LM LE 15 P32 B Arbitration GCO
6. tere te do he 63 Table 75 POST Progress Code LED Example eese 64 Table 76 Boot Block POST Progress 04 00 4 64 Table 77 POST Erogress GOUdBS s ofc e e 65 Table 78 The Board Power Budgelt co erts e 68 Table 79 The Board Power Supply Voltage Specification 69 Table 80 Output Voltage Timing heparin diete RUNE 69 Table 81 Turn On Off Timing sauve eee 70 Table 82 Transient Load 71 Table 83 AC Line Sag Transient Performance 72 Table 84 AC Line Surge Transient 72 Table 85 Absolute Maximum Ratings uoce desee ren eee regt 73 Table 86 Monitored Component5s 73 Table 87 Product Certification 2 44 044 77 Table 88 MTBF o uet Gode e 80 Revision 1 3 7221 1 Technical Product Specification List of Figures Figure 1 Intel Server Board SE7221BK1 E Diagram 4 Figure 2 Memory Bank Label Definition nte eru d
7. Display Setup Message The new cursor position has been read and saved Displaying the Hit Setup message next Ensure Timer Keyboard Interrupts are on Revision 1 3 7221 1 Technical Product Specification 78h 7Ah 7Ch 7Eh 80h 82h 84h 86h 88h 8Ah 8Ch 8Eh 90h 92h 94h 96h 98h 9Ah 9Ch 9Eh AOh A2h A4h A6h A8h Aah Ach Aeh 000h Diagnostic LED Description Decoder G Green R Red A Amber Hi G G aH Low Extended background memory test start Disable parity and NMI reporting Test 8237 DMA Controller The DMA page register test passed Performing the Controller 1 base register test next A A Init 8237 DMA Controller The DMA controller 2 base register test passed Programming DMA controllers 1 and 2 next Enable Mouse and Keyboard The keyboard test has started Clearing the Off Off Off output buffer and checking for stuck keys Issuing the keyboard reset command 0 next Keyboard Interface Test A keyboard reset error or stuck key was found Issuing Off G Off the keyboard controller interface test command next G og Check Stuck Key Enable Keyboard The keyboard controller interface test completed Writing the command byte and initializing the circular buffer next G G Off Disable parity NMI The command byte was written and global data initialization has
8. 7221 1 Technical Product Specification 10 2 Power Supply Specifications This section provides power supply design guidelines for the baseboard including voltage and current specifications and power supply on off sequencing characteristics Table 79 The Board Power Supply Voltage Specification 10 2 1 Power Timing Requirements These are the timing requirements for the power supply operation The output voltages must rise from 10 to within regulation limits Tvout rise within 5 to 70ms except for 5VSB it is allowed to rise from 1 0 to 70ms The 3 3V and 12V output voltages should start to rise approximately at the same time All outputs must rise monotonically The 5 output needs to be greater than the 3 3 output during any point of the voltage rise The 5V output must never be greater than the 3 3V output by more than 2 25V Each output voltage shall reach regulation within 50ms Tvout of each other during turn on of the power supply Each output voltage shall fall out of regulation within 400msec Tvout off of each other during turn off Refer to the table below for the timing requirements for the power supply being turned on and off via the AC input with PSON held low and the PSON signal with the AC input applied Table 80 Output Voltage Timing Item Description MIN MAX UNITS Tvout rise Output voltage rise time from each main output 5 0 70 msec Tvout_on All
9. amp T ew Of G Off A Pass control to the uncompressed code in shadow RAM The initialization code is copied to segment 0 and control will be transferred to segment 0 Control is in segment 0 Verify the system BIOS checksum Off G G If the system BIOS checksum is bad go to checkpoint code EOh Otherwise going to checkpoint code D7h Off Pass control to the interface module Off Decompress of the main system BIOS failed Build the BIOS stack Disable USB controller Disable cache G Uncompress the POST code module Pass control to the POST code module Of Decompress the main system BIOS runtime code Pass control to the main system BIOS in shadow RAM Off Start of recovery BIOS Initialize interrupt vectors system timer DMA controller and interrupt controller 6 Of Off Try to boot floppy diskette If floppy boot fails intialize hardware Off Try booting from ATAPI CD ROM drive A Jump to boot sector Table 77 POST Progress Codes Description Low Diagnostic LED Decoder G Green R Red B Off Off Uncompress various BIOS Modules Off Off Verify password Checksum Off G R Off Verify CMOS Checksum Off Read Microcode updates from BIOS ROM G Off Off Initializing the processors Set up processor registers
10. 8 Figure 3 Interrupt Routing Diagram etta me tete etae nette udis deu d 20 Figure 4 ICH6R Interrupt Routing 21 Figure 5 PXH Interrupt Routing Diagram 22 Figure 6 System Recovery and Update Jumpers 1 2 33 Figure 7 BIOS Recovery washes et Raat cts te Aca de 56 Figure 8 Output Voltage Timing ve nud 70 Figure 9 Turn On Off Timing Power Supply 71 Figure 10 Fan Speed Control Block Diagram 75 Figure 11 SE7221BK1 E Server Board Mechanical 81 Figure 12 sku 1 Pedestal mount I O shield mechanical 2 82 Figure 13 sku 2 Pedestal mount I O shield mechanical drawing 83 xi 7221 1 Technical Product Specification 1 Introduction This Intel Server Board SE7221BK1 E Technical Product Specification TPS provides high level technical description for the Intel Server Board 5 7221 1 It details the architecture and feature set for all functional sub systems that make up the server board This document is divided into the following main categories Chap
11. 7221 1 Technical Product Specification Description CALCU ESC Exit The ESC key provides a mechanism for backing out of any field This key will undo the pressing of the Enter key When the ESC key is pressed while editing any field or selecting features of a menu the parent menu is re entered When the ESC key is pressed in any sub menu the parent menu is re entered When the ESC key is pressed in any major menu the exit confirmation window is displayed and the user is asked whether changes can be discarded If No is selected and the Enter key is pressed or if the ESC key is pressed the user is returned to where they were before ESC was pressed without affecting any existing any settings If Yes is selected and the Enter key is pressed setup is exited and the BIOS continues with POST Select Item The up arrow is used to select the previous value in a pick list or the previous options in a menu item s option list The selected item must then be activated by pressing the Enter key The down arrow is used to select the next value in a menu item s option list or a value pick list The selected item must then be activated by pressing the Enter key Menu The left and right arrow keys are used to move between the major menu pages The keys have no affect if a sub menu or pick list is displayed Tab Select Field The Tab key is used to move between fields For example Tab can be used to move from hour
12. us Eee e 26 7 4 OF TP OMT 0 at o E Coat Lata 27 7 5 NIG 6 01 10 19119 nae 27 7 6 28 7 7 SATA CODDSCIDI accede oi Q mm au SS u 29 7 8 USB COMMS CON ERE TI 29 7 9 141512110 e utr dieu dva has 30 7 10 Serial Port Connector 5 er ee eode te tup HR 30 7 11 Keyboard and Mouse Connector RR etre Rr 31 7 12 Miscellaneous nennen nennen 31 TAZA OCEANA hi is cinerea rn nested 31 PAZ 2 Intrusion Cable Connector 32 7 12 aa Hee 32 7 12 4 Rolling BIOS selection ertet doe cite gre 33 8 Contiguration UI ee 33 8 1 System Recovery and Update Jumpers 33 9 BIOS Setup t I 34 9 1 EE 34 9 2 Console Redirection 34 9 3 Config ration Reset 34 9 4 Keyboard Comririands tr aea e stet 34 9 5 Ente
13. The recovery disk must include the BIOS image file AMIBOOT ROM The 2 MB AMIBOOT ROM file may be used on a 2 88MB floppy media to go with a 2 88 MB legacy or USB floppy device a USB mass storage device i e a USB disk on key must be USB 1 1 or 2 0 compliant a USB CDROM USB 1 1 or 2 0 compliant an ATAPI mass storage device or an ATAPI CDROM or DVD The recovery mode procedure is as follows 1 Insert the Recovery media with AMIBOOT ROM into the system as appropriate based on whatever device is used 2 Power on system and when progress code E9 is displayed on port 80h the system will detect the disk if there is no image file present the system will cycle through progress code F1 to EF When F3 is displayed on port 80h the system will read the BIOS image file 4 The screen will display flash progress and show if NVRAM and CMOS have been destroyed 5 When recovery mode is complete the system will halt and the system can be powered off NOTE There are three different hot keys that can be invoked lt Ctrl Home gt Recovery with CMOS destroyed NVRAM preserved Ctrl PageDown Recovery with both CMOS NVRAM preserved lt Ctrl PageUp gt Recovery with both CMOS NVRAM destroyed Multi Disk Recovery With this new feature the System Recovery can be made from Multiple Floppy Disks to support ROM image greater than 1MB Usage 1 Use the SPLIT EXE utility to split the ROM image Execute the followi
14. and integrated hardware monitoring SSl compliant connectors for SSI interface support front panel and power connectors Support for up to four system fans and one processor fan 7221 1 Technical Product Specification A B C D EF G H E CPU BB AA Socket 2 4 Wh UT 5 55 op ep 55 Pm o mE OIG QIO L L TP01326 Figure 1 Intel Server Board SE7221BK1 E Diagram CPU Fan optional SATA 4 Connector A Chassis Intrusion Header L DIMM Sockets from left to W 34 pin Front Panel Connector right DIMM 1B DIMM 2B B PCISlot M DIMM Sockets two from leftto X Serial ATA SATA 2 Connector right DIMM 1A DIMM 2 C PCI X 100 SLOT N Front USB Header optional Y SATA 1 Connector D 100 SLOT O System Fan Headers for Intel Z BIOS Control Jumper Server Board SR1425BK1 E E or Riser Connector System Fan 4 AA BIOS Select Jumper Slot F 412v CPU Power Q S
15. 7221 1 Technical Product Specification I Feature Options Help Text Language English Use ENTER Up Arrow Down Select the current default language Arrow to select language used by BIOS French German Italian Spanish 9 5 2 Advanced menu Table 41 BIOS Setup Advanced Menu Options Options HeipTe Description Processor Configuration 9 5 2 1 Processor configuration sub menu Table 42 BIOS Setup Processor configuration sub menu options Feature Options Help Text Manufacturer N A Displays processor manufacturer string Intel Brand String Displays processor brand ID string Frequency N A N A Displays the calculated processor speed FSB Speed Displays the processor front side bus speed Cache L3 N A N A Displays cache L3 size Visible only if the processor contains L3 cache Processor Retest Enabled If enabled all processors will be Rearms the processor sensors Disabled activated and retested on the next Only displayed if the Intel amp boot This option will be Management Module is present automatically reset to disabled on the next boot Max CPUID Value Enabled This should be enabled in order to Limit Disabled boot legacy OSes that cannot support processors with extended CPUID functions 37 SE7221BK1 E Technical Product Specification Options HelpText Description Hyper Threading Enabled ENABLE
16. External 089 Serial A Port Pin out 8 1 044042221 30 9 pin Header Serial B Port Pin out J1B1 31 Keyboard and Mouse PS 2 Connectors Pin out KM9A1 31 Revision 1 3 SE7221BK1 E Technical Product Specification Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Three pin Fan Headers Pin out JP5J1 JP5J2 JP7A1 JP6A1 31 Eight pin Fan Header Pin out 4641 J6J2 J6J3 and 6 32 Intrusion Cable Connector 1 1 32 HDD LED Header J1E1 uoto EC EU 32 HDD LED Header IVE 1 PN OUTS 252 33 System Recovery and Update Jumper Options 33 BIOS Setup Keyboard Command Bar Options 34 BIOS Setup Main Menu 4 6400000 36 BIOS Setup Advanced Menu Options 1 37 BIOS Setup Processor c
17. Intel 4 Date of Manufacturer Marked on Product 5 Manufacturer Nation Intel 13 2 6 Australia New Zealand This product has been tested and complies with AS NZS 3548 The product has been marked with the C Tick mark to illustrate compliance 13 3 Replacing the Back Up Battery The lithium battery on the server board powers the for up to 10 years in the absence of power When the battery starts to weaken it loses voltage and the server settings stored in CMOS RAM in the RTC for example the date and time may be wrong Contact your customer service representative or dealer for a list of approved devices WARNING Danger of explosion if battery is incorrectly replaced Replace only with the same or equivalent type recommended by the equipment manufacturer Discard used batteries according to manufacturer s instructions ADVARSEL Lithiumbatteri Eksplosionsfare ved fejlagtig handtering Udskiftning m kun ske med batteri af samme fabrikat og type Lev r det brugte batteri tilbage til leveranderen ADVARSEL Lithiumbatteri Eksplosjonsfare Ved utskifting benyttes kun batteri som anbefalt av apparatfabrikanten Brukt batteri returneres apparatleveranderen VARNING Explosionsfara vid felaktigt batteribyte Anvand samma batterityp eller en ekvivalent typ som rekommenderas av apparattillverkaren Kassera batteri enligt fabrikantens instruktion VAROITUS Paristo voi rajahtaa jos se on virhee
18. Select least featured processor as the BSP G Off Go to Big Real Mode G R Off Decompress INT13 module G A Off Keyboard Controller Test The keyboard controller input buffer is free Next issuing the BAT command to the keyboard controller Keyboard Mouse port swap if needed Write Command Byte 8042 The initialization after the keyboard controller BAT command test is done The keyboard command byte will be written next 65 34h 36h 38h 3Ah 3Ch 3Eh 40h 42h 44h 46h 48h 4Ah 4Ch 4Eh 50h 52h 54h 56h 58h 5Ch 5Eh 60h 62h 64h 66h 68h 6Ah 6Ch 6Eh 70h 72h 74h 76h 66 Hi Off Off G G O Off Off Off gt Off Off Off gt a Off Off Off Off 0 Off Off Off gt f SE7221BK1 E Technical Product Specification Lg Lug E Diagnostic LED Description Decoder GzGreen R Red A Amber G G Off Chipset Initialization before CMOS initialization Init System Timer The 8254 timer test is over Starting the legacy memory refresh test next Check Refresh Toggle The memory refresh line is toggling Checking the 15 second on off time next Off Calculate CPU speed G G A A Enable USB controller in chipset Low the pin 23 and 24 blocking and unblocking commands R Disable 8259 R Detect Configuration Mode such as CMO
19. provides the interface for a 32 bit 33 MHz PCI bus The ICH6R can be both a master a target on that PCI bus The ICH6R also includes a USB 2 0 controller and an IDE controller The ICH6R is also responsible for much of the power management functions with ACPI control registers built in The ICH6R also provides a number of GPIO pins and has the LPC bus to support low speed legacy The GMCH and ICH6R chips provide the pathway between processor and I O systems The GMCH is responsible for accepting access requests from the host processor bus and directing all I O accesses to one of the PCI buses or legacy I O locations If the cycle is directed to one of the PCI E segments the GMCH communicates with the PCI E Devices add in card on board devices through the PCI E interface If the cycle is directed to the ICH6R the cycle is output on the GMCH s DMI bus All I O for the board including PCI and PC compatible is directed through the GMCH and then through the ICH6R provided PCI buses PXH PCI X Hub The PXH hub is peripheral chips that perform PCI bridging functions between the PCI Express interface and the PCI bus The PXH contains two PCI bus SE7221BK1 E Technical Product Specification interfaces that can be independently configured to operate in PCI 33 or 66 MHz PCI X Mode1 66 100 133 for either 32 or 64 bits 4 1 1 GMCH Memory Architecture Overview The GMCH supports a 72 bit wide memory sub system that can
20. 6 PCI configuration sub menu This sub menu provides control over PCI devices and their option ROM s If the BIOS is reporting POST error 146 use this menu to disable option ROM s that are not required to boot the system Table 49 BIOS Setup PCI Configuration Sub menu Selections Onboard Video Disabled Enabled Onboard NIC 1 Disabled Enabled ae Enable Disable on board VGA Controller Onboard NIC 1 ROM Disabled Enabled Onboard NIC 2 Disabled Enabled Onboard NIC 2 ROM Disabled Enabled Slot 1 Option ROM Enabled Disabled Slot 4 Option ROM Enabled Disabled Slot 5 Option ROM Enabled Disabled Slot 6 Option ROM Enabled Disabled 42 PCI X 100Mhz PCI X 100Mhz sss T Revision 1 3 7221 1 Technical Product Specification 9 5 2 7 Memory configuration sub menu This sub menu provides information about the DIMM s detected by BIOS The DIMM number is printed on the baseboard next to each device Table 50 BIOS Setup Memory Configuration Sub menu Selections ___ Featue Options Help Text DIMM 1A Installed Not Installed DIMM 1B Installed Not Installed DIMM 2A Installed Informational display Not Installed Informational display Informational display Informational display DIMM 2B Installed Not Installed Extended Memory Test 1 MB Settings for extended memory test 1KB Every Location Disabled Memory Retest Enabled If Enabled BIOS will activate and Disabled retest all DIM
21. BIOS Setup ATAPI CDROM Drives Sub menu Selections Options Help Text 54 Min 4 5 Seconds Select Timing for SLP_S4 pin 548 pin timing selection Assertion 3 4 Seconds 2 3 Seconds 1 2 Seconds 46 Revision 1 3 7221 1 Technical Product Specification PCI EX Port N A N A Title Configuration VC1 for Root Port Disabled Enable Disable VC1 feature VC1 feature setting on PCI Express Enabled Root port 9 5 4 3 PXH Bridge Configuration Table 60 BIOS Setup ATAPI CDROM Drives Sub menu Selections Feature Options Help Text Description PCI Bus frequency Auto Allows selection of the maximum Select Bus speed and operating 33Mhz PCI ME to frequency of bus coming out PXH efault will always be set to Auto 66Mhz PCI where Bus speed will be decided 66Mhz PCI X M1 based on the capabilities of the 100Mhz PCI X M1 device on the Bus 133 Mhx PCI X M1 66Mhz PCI X M2 100Mhz PCI X M2 133 Mhx PCI X M2 IO Port Decode 4K Decode Select the decode range for IO decode range 1K Decode RAS Sticky error Clear Errors Select the method of handling for RAS errors handing method selection handling Leave Errors sticky RAS errors VGA 16 Bit decode Disabled Enabled Disable decoding of VGA Enabled for devices behind PXH 9 5 5 Security menu Table 61 BIOS Setup Security Menu Options Feature Options Help Text Administrator Install Not installed Informational display
22. an upper nibble and a lower nibble Each bit in the upper nibble is represented by a Red LED and each bit in the lower nibble is represented by a green LED If both bits are set in the upper and lower nibbles then both Red and Green LEDs are lit resulting in an Amber color If both bits are clear then the LED is off In the below example BIOS sends a value of ACh to the Diagnostic LED decoder The LEDs are decoded as follows Red bits 1010b Ah Green bits 1100b Ch Since the red bits correspond to the upper nibble and the green bits correspond to the lower nibble the two are concatenated to be ACh Table 75 POST Progress Code LED Example 9 8 1 Diagnostic LED POST Progress Codes Table 76 Boot Block POST Progress Codes Diagnostic LED Description Decoder G Green R Red The NMI is disabled Start Power on delay Initialization code checksum verified Initialize the DMA controller perform the keyboard controller BAT test start memory refresh and enter 4 GB flat mode Get start of initialization code and check BIOS header Test base 512K of memory Return to real mode Execute any OEM patches and set up the stack 64 Revision 1 3 7221 1 Technical Product Specification 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch E8h E9h Eah Ebh Ech Eeh Efh 20h 22h 24h 26h 28h 2Ah 2Ch 2 30h 32h Diagnostic LED Description Decoder GzGreen R Red
23. and environmental conditions Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non operating limits The Intel Server Board SE7221BK1 E may contain design defects or errors known as errata which cause the product to deviate from published specifications Current characterized errata are available on request This document and the software described in it is furnished under license and may only be used or copied in accordance with the terms of the license The information in this manual is furnished for informational use only is subject to change without notice and should not be construed as a commitment by Intel Corporation Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document Except as permitted by such license no part of this document may be reproduced stored in a retrieval system or transmitted in any form or by any means without the express written consent of Intel Corporation Intel Pentium Itanium and Xeon are trademarks or registered trademarks of Intel Corporation Other brands and names may be claimed as the property of others Copyright Intel Corporation 2005 SE7221BK1 E Technical Product Specification Table of contents 1 duelli
24. any the system transitions to Reset Button The reset button will generate a hard reset to the system NMI Button The NMI button will force an NMI to the processors 6 1 2 Wake up Sources ACPI and Legacy The baseboard is capable of wake up from several sources under a non ACPI configuration such as when the operating system does not support ACPI The wake up sources are defined in the following table Table 15 Supported Wake Events Supported via ACPI Supported Via Legacy Wake by sleep state Always wakes system Always wakes system PME from PCI 32 33 51 54 SS PME from primary PCI 64 66 51 54 55 51 54 Mouse 51 Keyboard 51 USB S1 No Under ACPI the operating system programs the ICH6R and Super IO to wake up on the desired event but in legacy mode the BIOS enables disables wake up sources based on an option in BIOS Setup The operating system or a driver must clear any pending wake up status bits in the associated hardware such as the Wake on LAN status bit in the LAN application specific integrated circuit ASIC or PCI Power Management Event PME status bit in a PCI device The legacy wake up feature is disabled by default 24 Revision 1 3 7221 1 Technical Product Specification T Connectors 7 1 Main Power Connector The main power supply connection is obtained using the 24 pin connector The following table defines the pin outs of the connector Table 16 Power
25. completed Checking for a locked key next Display USB devices Verify RAM Size Checking for a memory size mismatch with CMOS RAM data next Lock out PS 2 keyboard mouse if unattended start is enabled Init Boot Devices The adapter ROM had control and has now returned control G G Off to BIOS POST Performing any required processing after the option ROM returned control Off Display IDE mass storage devices G Display USB mass storage devices Of Report the first set of POST Errors To Error Manager G G Boot Password Check The password was checked Performing any required programming before Setup next Float Processor Initialize Performing any required initialization before the gt gt gt gt Di T gt Dd gt coprocessor test next G Enable Interrupts 0 1 2 Checking the extended keyboard keyboard ID and NUM Lock key next Issuing the keyboard ID command next ot R Init FDD Devices Report second set of POST errors To Error messager G R Extended background memory test end Off Off Prepare And Run Setup Error manager displays and logs POST errors Waits for user input for certain errors Execute setup Set Base Expansion Memory Size Program chipset setup options build ACPI Tables build INT15h E820h table Display R Build SMBIOS table and MP tables Prepare USB controllers for operating system O
26. different BIOS modules Fill the free area in FOOOh segment with OFFh Initializes the Microsoft IRQ Routing Table Prepares the runtime language module Disables the system configuration display if needed Initialize runtime language module Displays the system configuration screen if enabled Initialize the CPU s before boot which includes the programming of the MTRR s Hg Wao ser contig play needed PA ut POST Th Yer and TON WEE DAT AB Prepare BBS for Int 19 boot eee BBS for Int 19 boot Rica f sera 7 0 End of POST initialization of chipset registers SwesmemsnWRrROR O Passes contro OS WT 60 1 3 7221 1 Technical Product Specification 9 7 3 2 Boot Block Initialization Code Checkpoints The Boot Block initialization code sets up the chipset memory and other components before system memory is available The following table describes the type of checkpoints that may occur during the boot block initialization Table 71 Bootblock Initialization Code Checkpoints Checkpoint Before D1 Early chipset initialization is done Early super initialization is done including RTC and keyboard controller NMI is disabled Perform keyboard controller BAT test Check if waking up from power management suspend state Save power on CPUID value in scratch CMOS Go to flat mode with 4GB limit and GA20 enabled Verify the bootb
27. sub menu selections Table 65 BIOS Setup Event Log Configuration Sub menu Selections Help Text Clear All Event Logs Disabled Setting this to Enabled will clear the DMI event log after Enabled system booting Event Logging Disabled Select enabled to allow logging of events Allow records Enabled to be sent to SEL Enable SMM handlers to detect and log events to SEL If enabled BIOS will detect and log events for system Critical Event Logging Disabled Enabled critical errors Critical errors are fatal to system operation These errors include PERR SERR ECC 50 Revision 1 3 7221 1 Technical Product Specification zg Feature Options HelpText ECC Event Logging Disabled Enables or Disables ECC Event Logging Grayed out if Enabled Critical Event Logging option is disabled PCI Error Logging Disabled Enables or Disables PCI Error Logging Grayed out if Enabled Critical Event Logging option is disabled 9 5 7 Exit menu Table 66 BIOS Setup Exit Menu Selections Feature Options Help Text Save Changes N A Exit system setup after saving the changes and Exit F10 key can be used for this operation Discard Exit system setup without saving any changes ESC key can be used for this operation xi Discard N A Discards changes done so far to any of the setup questions Changes F7 key can be used for this operation Load Setup Load Setup Default
28. values for all the setup questions Defaults F9 key can be used for this operation Load Custom custom defaults Defaults Save Custom custom defaults Defaults 9 6 Upgrading the BIOS 9 6 1 Preparing for the Upgrade Before you upgrade the BIOS prepare for the upgrade by recording the current BIOS settings obtaining the upgrade utility reviewing the release notes and making a copy of the current BIOS 9 6 1 1 Recording the Current BIOS Settings 1 Boot the computer and press F2 when you see the message Press F2 Key if you want to run SETUP 2 Write down the current settings in the BIOS Setup program or go to the Exit menu and choose to Save Custom Defaults Note Do not skip step 2 You will need these settings to configure your computer at the end of the procedure 51 7221 1 Technical Product Specification If you chose to Save Custom Defaults after the new BIOS is flashed you can restore your settings from the Load Custom Default option 9 6 1 2 Obtaining the Upgrade Utility You can upgrade to a new version of the BIOS using the new BIOS files and the BIOS upgrade utility You can obtain the BIOS upgrade file and the utility from the Intel Customer Support Web site http support intel com support motherboards server SE7221BK1 E 9 6 1 3 Creating a Bootable Diskette 1 Use DOS system to create the diskette 2 Insert a diskette in diskette drive A 3 Atthe C promp
29. 14B Unknown BIOS error Error code 14B this is really Warning 57 SE7221BK1 E Technical Product Specification Error Code Error Message Response LANGUAGE MODULE ERR 14D Primary Master Hard Disk Error Pause 14E Primary Slave Hard Disk Error Pause 14F Secondary Master Hard Disk Error Pause 150 Secondary Slave Hard Disk Error Pause 151 Primary Master Drive ATAPI Incompatible Pause 152 Primary Slave Drive ATAPI Incompatible Pause 153 Secondary Master Drive ATAPI Incompatible Pause 154 Secondary Slave Drive ATAPI Incompatible Pause 8100 Processor failed BIST Warning 8110 Processor Internal error IERR Warning 8120 Processor Thermal Trip error Warning 8160 Processor unable to apply BIOS update Pause 8170 Processor L2 cache Failed Pause 8180 BIOS does not support current stepping for Processor Pause 8190 Watchdog Timer failed on last boot Warning 8191 12 1 Core to bus ratio Processor Cache disabled Pause 8192 L2 Cache size mismatch Pause 8193 CPUID Processor Stepping are different Pause 8194 CPUID Processor Family are different Pause 8195 Front Side Bus Speed mismatch System Halted Pause 8197 CPU Speed mismatch Pause 8300 Baseboard Management Controller failed to function Pause 8301 Front Panel Controller failed to Function Pause 84F2 Server Management Interface Failed Pause 84 BMC in Update Mode Pause 84F4 Sensor Data Record Empty Pa
30. 28 95 Immunity Russia 13 1 3 Product Regulatory Compliance Markings This product is provided with the following product certification markings 76 Revision 1 3 SE7221BK1 E Technical Product Specification Table 87 Product Certification Markings UL Recognition Mark AY 5 C Russian GOST Mark 06 Australian C Tick Mark 232 BSMI DOC Marking D33023 BSMI EMC Warning ACS ATE F 86 EE SAR RRL MIC Mark 13 2 Electromagnetic Compatibility Notices 13 2 1 FCC USA This device complies with Part 15 of the FCC Rules Operation is subject to the following two conditions 1 this device may not cause harmful interference and 2 this device must accept any interference received including interference that may cause undesired operation For questions related to the EMC performance of this product contact Intel Corporation 5200 N E Elam Young Parkway Hillsboro OR 97124 1 800 628 8686 This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference in a residential installation This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instructions may cause harmful inter
31. 7 3 3 Boot Block Recovery Code Checkpoints The Boot block recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because the user has forced the update or the BIOS checksum is corrupt The following table describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS Table 72 Bootblock Recovery Code Checkpoints Checkpoint Initialize the floppy controller in the super Some interrupt vectors are initialized DMA controller is initialized 8259 interrupt controller is initialized L1 cache is enabled Set up floppy controller and data Attempt to read from floppy Enable ATAPI hardware Attempt to read from ARMD and ATAPI CDROM Disable ATAPI hardware Jump back to checkpoint E9 Read error occurred on media Jump back to checkpoint EB E9 or EA Determine information about root directory of recovery media Search for pre defined recovery file name in root directory Recovery file not found Start reading the recovery file cluster by cluster Disable L1 cache per d Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file FB Make flash write enabled through chipset and OEM specific method Detect proper flash part Verify that the found flash part size equals the recovery file size The recovery file size does not equal the found flash part size Erase the flash part P Program the flash part The flash has be
32. AN TACH signal is connected to the Super 96000 to monitor the FAN speed 8 Fan Power Power Fan Power with SPEED 1 Fan speed control 7 12 2 Intrusion Cable Connector Table 35 Intrusion Cable Connector J1A1 Pin Out Pin Signal Name 1 INTRUDER N 2 GND 7 12 3 HDD LED Header There is a 1x2 pin Header for HDD LED Connection This jumper reserves for PCI add in card which supports the SCSI or SATA interface with external HDD LED activity cable 32 Table 36 HDD LED Header J1E1 Pin Out Pin Signal Name 1 HDD LED ACT N 2 NC Revision 1 3 SE7221BK1 E Technical Product Specification 7 12 4 Rolling BIOS selection header There is a 1x3 pin Header that is used to configure the function of rolling BIOS The figure below shows the jumper pins and their functions The factory defaults are set to a primary BIOS mode for each function Table 37 HDD LED Header J1E1 Pin Out Function Pin Pin Function Description Rolling BIOS selection 1 2 BIOS Default Although some details of this feature are described 2 3 Secondary BIOS within this manual please refer to section 9 6 3 for complete details 8 Configuration Jumpers This section describes configuration jumper options on the Intel amp Server Board SE7221BK1 E 8 1 System Recovery and Update Jumpers An 11 pin Key in pin 4 8 Header J1F2 located just beside the PCI Slot 1 connectors provides a
33. C Slot 4 INTD Slot 6 INTB Slot 5 INTD Slot 5 INTA Slot 5 INTB Slot 5 INTC N A N A N A N A N A N A N A N A 22 SE7221BK1 E Technical Product Specification PCI X Interface PCI X Interface Figure 5 PXH Interrupt Routing Diagram Revision 1 3 7221 1 Technical Product Specification 6 ACPIImplementation 6 1 An operating system generates SMI to request that the system be switched into ACPI mode The BIOS responds to enable ACPI mode The system automatically returns to legacy mode upon hard reset or power on reset The SE7221BK1 E platform supports SO S1 S4 and S5 states When the system is operating in ACPI mode the OS retains control of the system and OS policy determines the entry methods and wake up sources for each sleep state Note Sleep entry and wake up event capabilities are provided by the hardware but are enabled by the operating system 50 Sleep State The 50 sleep state is when everything is on This is the state that no sleep is enabled S1 Sleep State 51 sleep state is a low wake up latency sleep state In this state no system context is lost Processor or chipset The system context is maintained by the hardware S4 Sleep State The S4 Non Volatile Sleep state NVS is a special global system state that allows system context to be saved and restored relatively slowly when power is lost to the baseboard If the system has been comman
34. CI device ID value for use in configuration cycles The following table shows the bit to which each IDSEL signal is attached for P32 B devices and corresponding device description Table 8 P32 B Configuration IDs 82541PLLAN NGA 5 1 2 2 P32 B Arbitration P32 B supports one PCI masters All PCI masters must arbitrate for PCI access using resources supplied by the PXH The host bridge PCI interface PXH arbitration lines REQx 15 SE7221BK1 E Technical Product Specification and GNTx are a special case in that they are internal to the host bridge The following table defines the arbitration connections Table 9 P32 B Arbitration Connections Uie PCIX NO Intel amp 82541 LAN NIC2 5 1 3 P64 C 66 100 MHz PCI X Subsystem One 64 bit PCI X bus segment is directed through the PXH This PCI X segment P64 C provides two 3 3V 64 bit PCI X slots or one 3 3V 64 bit PCI X riser slot SE7221BK1LX sku only capable of up to 100 MHz operation with 1 adapter either slot is capable of 100MHz only speeds of 66MHz are supported with two adapters populated and supports full length PCI and PCI X adapters 5 1 3 1 Device IDs IDSEL Each device under the PCI hub bridge has its IDSEL signal connected to one bit of AD 31 16 which acts as a chip select on the PCI bus segment in configuration cycles This determines a unique PCI device ID value for use in configuration cycles
35. Connector Pin out 1 Pin Signal 18 AWG Color Pin Signal 18 AWG Color 1 3 3VDC Orange 13 3 3VDC Orange 3 3V RS Orange 24AWG 14 12VDC Blue 2 3 3VDC Orange 15 COM Black 3 COM Black 16 PSON Green COM RS Black 24AWG 17 COM Black 4 5VDC Red 18 COM Black 5V RS Red 24AWG 19 COM Black 5 COM Black 20 Reserved N C 6 5VDC Red 21 5VDC Red 7 COM Black 22 5VDC Red 8 PWR OK Gray 23 5VDC Red 9 5 VSB Purple 24 COM Black 10 12V3 Yellow 11 12V3 Yellow 12 3 3VDC Orange Table 17 Auxiliary CPU Power Connector Pin out CN4B1 Pin Signal 18 AWG color Pin Signal 18 AWG Color 1 COM Black 5 12V1 White 2 COM Black 12V1 RS Yellow 24AWG 3 COM Black 6 12V1 White 4 COM Black 7 12V2 Brown 8 12V2 Brown 12V2 RS Yellow 24AWG SE7221BK1 E Technical Product Specification 7 2 1 Header Table 18 HSBP Header Pin out J1D1 Signal Name Description Gp HR SMB 5V CLK Clock Line 8ROUND Table 19 LCD Header Pin out J1C1 Signal Name HR SMB 5V DAT Data Line GROUND HR SMB 5V CLK Clock Line P5V_STBY POWER Table 20 LEGEND SE_LINK Header Pin out J2B1 GROUND MBMC SMC PHL CLK Clock Line 1 POWER 5 8 01 7 3 Front Panel Connector A standard SSI 34 pin header is provided to support a system front panel The header contains reset NMI power control buttons and LED indicators The following t
36. DE Slave While entering setup BIOS auto Selects submenu with additional detects the presence of IDE device details devices This displays the status of auto detection of IDE devices Secondary IDE While entering setup BIOS auto Selects submenu with additional Master detects the presence of IDE device details devices This displays the status of auto detection of IDE devices 38 Revision 1 3 7221 1 Technical Product Specification Secondary IDE Slave While entering setup BIOS auto Selects submenu with additional detects the presence of IDE device details devices This displays the status of auto detection of IDE devices Third IDE Master While entering setup BIOS auto Selects submenu with additional detects the presence of IDE device details devices This displays the status of auto detection of IDE devices Third IDE Slave While entering setup BIOS auto Selects submenu with additional detects the presence of IDE device details devices This displays the status of auto detection of IDE devices Hard Disk Write Disabled Disable Enable device write Primarily used to prevent Protect Enabled protection This will be effective unauthorized writes to hard only if device is accessed drives through BIOS IDE Detect Time Out Select the time out value for Primarily used with older IDE Sec detecting ATA ATAPI device s devices with longer spin up times ATA PI 80Pin Cable Host amp Device S
37. Enable CPU Controls Hyper Threading state Technology Disabled Hyperthreading for HT enabled Primarily used to support older processor s Operating Systems that do not support Hyper Threading DISABLE Disable CPU Hyperthreading for HT enabled processor s Controls Hyperthreading state Primarily used to support older Operating Systems that do not support Hyperthreading 9 5 2 2 IDE configuration sub menu Table 43 BIOS Setup IDE Configuration Menu Options Feature Options Help Text ATA IDE Disabled Disable SATA and PATA Controls state of integrated S configuration Compatible controller will be disabled ATA and P ATAcontroller Enhanced Legancy IDE Channel SATA Only SATA Only SATA controller This option will be hided when PATAPriSATA Sec enabled only ATA IDE configuration Disabled SATA PATA Pri SATA Sec PATA In compatible mode this item will PATA Only controller is primary SATA is be used secondary SATA Pri PATA Sec SATA controller is primary PATA is secondary PATA Only PATA controller enabled only Configure S ATAas IDE In Enhance mode this item will be RAID showed AHCI Stagger Spinup Disabled This item showed when Configure support Enabled S ATA as RAID AHCI Primary IDE Master While entering setup BIOS auto Selects submenu with additional detects the presence of IDE device details devices This displays the status of auto detection of IDE devices Primary I
38. IRQ21 IRQ22 IRQ23 ICH6 X8 connector SE7221BK1 E Technical Product Specification ICH6 IOAPIC 0 21111 L I II I II I III II L mis L 11 L 1L Dp i LLL LLLLLI L 41121111 L T ICH6 Po 1111 2111 8259 o L L 21111 LLLLI L TT Tt 111113 2111 X8 PCI E interface GMCH Figure 3 Interrupt Routing Diagram DMI INTERFACE CPU INTR Revision 1 3 7221 1 Technical Product Specification Super Timer Keyboard 9 Cascade Serial 215 Serial Port1 ISA ISA Floppy ISA ISA 50153 ISA Mouse ISA Coprocessor Error 75 Not Used SERIRQ INTEL 82541PI NIC1 Slot 1 INTC Slot 1 INTA Slot 1 INTB Slot 1 INTD Figure 4 ICH6R Interrupt Routing Diagram SERIRQ 1 4 1914 9H2I PIRQB PIRQC PIRQD PIRQE PIRQF PIRQG PIRQH 21 INTEL 82541 2 Slot 4 Slot 6 INTA Slot 4 INTB Slot 6 INTB Slot 4 Slot 6 INT
39. Intel Server Board SE7221BK1 E Technical Product Specification Intel order number C91860 001 Revision 1 3 ntel February 2005 Enterprise Platforms and Services Marketing SE7221BK1 E Technical Product Specification Revision History Number September 2004 08 Revised technical details of POT subsystem memorysuppotandGMCH Sepremberz04 09 Reisedcomedossedon a 2004 11 Corrected supported Jaruary 2005 12 Added Diagnostic LED codes to error handing and reporting section February 2005 13 Modified Diagnostic LED section Correct supported CPU 5 0 1 1 1 2 1 3 This product specification applies to the Intel Server Board SE7221BK1 E with BIOS identifier SE7221BK10 86B Changes to this specification will be published in the Intel amp Server Board SE7221BK1 E Specification Update before being incorporated into a revision of this document ii Revision 1 3 7221 1 Technical Product Specification Disclaimers Information in this document is provided in connection with Intel products No license express or implied by estoppels or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Conditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied warranty relating to sale and or use of Intel products including l
40. M See DIM Code Checkpoints section of document for more information Initializes DMAC 1 8 DMAC 2 Initialize RTC date time Test for total memory installed in the system Also Check for DEL or ESC keys to limit memory test Display total memory in the system Mid POST initialization of chipset registers Detect different devices Parallel ports serial ports and coprocessor in CPU etc successfully installed in the system and update the BDA EBDA etc Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed Updates CMOS memory size from memory found in memory test Allocates memory for Extended BIOS Data Area from base memory Initializes NUM LOCK status and programs the KBD typematic rate Initialize Int 13 and prepare for IPL detection Initializes IPL devices controlled by BIOS and option ROMs 38 39 3A 3B 3C 0 4 50 52 75 78 59 SE7221BK1 E Technical Product Specification Log eros encounired during POST ss Belay eros fo the user and gets the user response rem 87 Execute BIOS setup ineoded requesieg 111 0 POST ntaizaton of C SD supporeg SE Program ne peripheral parameters 0 Tate POST infazaton of system management nert Ap EE Clean up work needed before TUR to OS Takes care of runtime image preparation for
41. M s on the next System boot This option will automactically reset to Disabled on the next System boot 9 5 3 Boot menu Table 51 BIOS Setup Boot Menu Selections Feature Options Help Text Boot Settings Configuration Configure settings during system boot Selects submenu Boot Device Priority Specifies the boot device priority sequence Selects submenu Hard Disk Drives N A Specifies the boot device priority sequence from Selects submenu available hard drives Removable Drives N A Specifies the boot device priority sequence from Selects submenu available removable drives ATAPI CDROM Drives N A Specifies the boot device priority sequence from Selects submenu available ATAPI CD ROM drives 43 SE7221BK1 E Technical Product Specification 9 5 3 1 Boot settings configuration sub menu selections Table 52 BIOS Setup Boot Settings Configuration Sub menu Selections Feature Help Text EE Boot Allows BIOS to skip certain tests while booting This Enabled will decrease the time needed to boot the system Quiet Boot Disabled Disabled Displays normal POST messages Enabled Enabled Displays OEM Logo instead of POST messages Bootup Num Lock Select power on state for numlock PS 2 Mouse Support Disabled Select support for PS 2 mouse Enabled Auto POST Error Pause Disabled If enabled the system will wait for user intervention Enabled on critical POST errors If disabled the
42. N1 PIN 481 Monitors SYS FAN 1 JP6A1 SYS FAN 5B J6J1 Super IO FANIN2 PIN 77 Monitors SYS FAN J6J2 Super IO FANING PIN 76 Monitors SYS FAN 6B J6J2 Super IO FANIN4 PIN 75 Monitors SYS FAN 8A J6J4 Super IO 5 PIN 83 Monitors SYS FAN 8B J6J4 Super IO 6 PIN 36 Monitors SYS FAN 7A J6J3 Super IO FANIN7 PIN 9 Monitors SYS FAN 7B J6J3 Super IO Temperature H THEMP DA C Monitors processor temperature LM96000 Revision 1 3 7221 1 Technical Product Specification 12 2 Fan Speed Control 96000 PWM1 PWM2 1 2 Super IO PC87427 FANINO FANIN1 FANIN2 FANIN4 5 6 FANIN7 J7A11 FAN SPEED CNTL1 5 5 Mes pest 4 JP5J1 5 5 7 1 5 5 FAN1 SYS FAN5 A 6J1 B SYS 6 A 4642 SYS FAN8 A J6J4 B SYS FANI m Figure 10 Fan Speed Control Block Diagram 75 SE7221BK1 E Technical Product Specification 12 3 Chassis Intrusion The Intel amp Server Board SE7221BK1 E supports a chassis security feature that detects if the chassis cover is removed For the chassis intrusion circuit to function the chassis power supply must be connected to AC power The security feature uses a mechanical switch on the chassis that attaches to the chassis intrusion connector When the chassis cover is removed t
43. NK_UP_N LAN1_TRDNO 3 12 LAN1_ACT_N LAN1_TRDP1 4 LAN1_TRDP3 9 LAN1 TRDN1 5 13 LAN1 LINK100 N 27 SE7221BK1 E Technical Product Specification Signal Name Pin Pin Signal Name P1V8 STB LAN1 6 14 P3V3 STB LAN1 TRDP2 7 15 LAN1 LINK1000 N LAN1 TRDN2 8 16 LINK100 L Table 24 2 82541 10 100 1000 Connector Pin out J6A1 Signal Name Pin Pin Signal Name P1V8 STB LAN2 1 10 LAN2 TRDNO LAN2 TRDN2 2 11 LAN2 TRDPO LAN2 TRDP2 3 12 P1V8 STB LAN2 LAN2 4 13 LAN2 LINK100 LAN2 TRDN1 5 14 LAN2 LINK1000 N P1V8 STB LAN2 6 15 LAN2 LINK UP N P1V8 STB LAN2 7 16 LAN2 ACT N LAN2 TRDP3 8 17 GND CHASSIS LAN2 TRDNS 9 18 CHASSIS 7 66 Connector The board provides one 40 ATA 100 IDE connector Table 25 ATA 40 pin Connector Pin out J3J1 Pin Signal Name Pin Signal Name 1 RESET 2 GND 3 IDE_DD7 4 IDE_DD8 5 IDE_DD6 6 IDE_DD9 7 IDE DD5 8 IDE DD10 9 IDE DD4 10 IDE DD11 11 IDE DD3 12 IDE DD12 13 IDE DD2 14 IDE DD13 15 IDE DD1 16 IDE DD14 17 IDE DDO 18 IDE DD15 19 GND 20 KEY 21 IDE DMAREQ 22 GND 23 IDE 24 GND 25 IDE IOR 26 GND 27 IDE IORDY 28 GND 29 IDE_DMAACK 30 GND 31 IRQ IDE 32 Test Point 33 IDE A1 34 DIAG 35 IDE AO 36 IDE A2 37 IDE DCSO 38 IDE DCS1 39 IDE 40 GND 28 Revision 1 3 7221 1 T
44. NMECHONS 16 P64 C Configuration DS 16 P64 G Arbitration Connections 16 PCIKE Connections aeque te 17 PCI AND PCI X Interrupt Routing Sharing r 18 Interrupt Definition i co 19 Supported Wake 24 Power Connector Pin out 25 Auxiliary CPU Power Connector Pin out 25 HSBP Header Pin out 4101 cere eere 26 LCD Header Pin out 161 26 LEGEND SE LINK Header Pin out 2 1 26 Front Panel 34 Pin Header Pin out 41 71 26 VGA Connector Pin out JST iaa cic Eb Li 27 NIC1 82541P1 10 100 1000 Connector Pin out 27 2 82541 10 100 1000 Connector Pin out 1 28 40 pin Connector Pin out 341 28 SATA Connector Pin out J1G1 J1G2 J1J2 J2J1 29 USB Connectors Pin out J5A1 rx xem ders 29 Optional USB Connection Header Pin out 4 29 Legacy 34 pin Floppy Connector Pin out JP3J1 30
45. NSEL GND 3 4 Unused KEY 5 6 FDDRATEO GND 7 8 FDINDEX GND 9 10 FDMTRO GND 11 12 FDR1 GND 13 14 FDRO GND 15 16 FOMTR1 Unused 17 18 FDDIR GND 19 20 FDSTEP GND 21 22 FOWDATA GND 23 24 FDWGATE GND 25 26 FDTRKO 2 Unused 27 28 FLWP GND 29 30 FRDATA GND 31 32 FHDSEL GND 33 34 FDSKCHG 7 10 Serial Port Connector Two serial ports are provided on the Intel amp Server Board SE7221BK1 E A standard external 089 serial connector is located on the back edge of the baseboard to supply a Serial A interface This connector is combined with VGA connector J8A1 Serial B port is provided through 9 pin header J1B1 on the server board The following tables detail the pin outs of these two ports Table 30 External DB9 Serial A Port Pin out J8A1 Signal Name Pin Pin Signal Name DCD P T1 T6 DSR P RXD P T2 T7 RTS P TXD P 18 CTS P DTR P T4 T9 RI P GND T5 30 Revision 1 3 7221 1 Technical Product Specification Table 31 9 pin Header Serial B Port Pin out J1B1 Signal Name Pin Pin Signal Name DCDB 1 2 DSRB RXDB 3 4 RTSB TXDB 5 6 CTSB DTRB 7 8 RIB GND 9 10 Key 7 11 Keyboard and Mouse Connector Two PS 2 ports are provided for use by a keyboard and a mouse The following table details the pin out of the PS 2 connectors Table 32 Keyboard and Mous
46. Password is User Password is Install Not installed Informational display Set Admin Set or clear Admin password Set password to null to clear Password Set User Password N A Set or clear User password This node is grayed out until Admin password is installed Set password to null to clear User Access Level No Access LIMITED Allows only limited fields This node is grayed out and View Only to be changed such as Date and becomes active only when Admin Limited Time password is set NO ACCESS Prevents User Full Access access to the Setup Utility VIEW ONLY Allows access to the Setup Utility but the fields can be changed 47 SE7221BK1 E Technical Product Specification Feature Options Help Text Clear User Password Fixed disk boot sector protection Immediately clears the user password Admin uses this option to clear User password Admin password is used to enter setup is required This node is hidden if Administrator password is not installed Disabled Enable Disable Boot Sector Virus Enabled Protection Password On Boot Disabled If enabled requires password This node is grayed out if a Enabled entry before boot password is not installed Secure Mode Timer 1 minute 2 minutes 5 minutes 10 minutes 20 minutes 60 minutes 120 minutes Secure Mode Hot Key Ctrl Alt Disabled Enabled Secure Mode Boot Front Panel Switch Disabled Inhibit Enabled NMI Control Di
47. ROM drives sub menu selections Table 56 BIOS Setup ATAPI CDROM Drives Sub menu Selections Feature Options Help Text 1st Drive Varies Specifies the boot sequence from the available Varies based on system configuration devices nth Drive Varies Specifies the boot sequence from the available Varies based on system configuration devices 9 5 4 Chipset Menu Table 57 BIOS Setup ATAPI CDROM Drives Sub menu Selections Featue Options Help Text North Bridge N A Configure North Bridge features Opens sub screen to configure NB Configuration South Bridge N A Configure South bridge features Opens sub screen to configure SB Configuration Intel PCI Express N A Configure PXH device Opens sub screen to configure PCI X configuration PXH System management sub menu selections 9 5 4 1 North Bridge Chipset Configuration Table 58 BIOS Setup ATAPI CDROM Drives Sub menu Selections Feature Options Help Text DRAM Frequency AUTO DRAM frequency to be DRAM frequency selection 333Mhz programmed 400Mhz 533Mhz Configure DRAM Disabled Whether to read the DRAM Timing Timing by SPD Enabled paramaters from SPD or from User setup 45 SE7221BK1 E Technical Product Specification Feature Description DRAM CAS Select CAS latency to be used Greyed when DRAM timing Latency programming are done using SPD Selects the CAS latency value to be programmed
48. S Setup will not take effect until the system is rebooted The BIOS Setup Utility can be accessed when prompted during POST by using the F2 key 9 1 Localization The BIOS Setup utility uses the Unicode standard and is capable of displaying setup forms in English French Italian German and Spanish BIOS supports these languages for console strings as well 9 2 Console Redirection BIOS Setup is functional via console redirection over various terminal standards emulation This may limit some functionality for compatibility e g usage of colors or some keys or key sequences or support of pointing devices 9 3 Configuration Reset There are different mechanisms for resetting the system configuration to default values When a reset system configuration request is detected the BIOS will load the default system configuration values during the next POST A reset system configuration request can be generated by moving the Clear CMOS jumper 94 Keyboard Commands The Keyboard Command Bar supports the following keys Table 39 BIOS Setup Keyboard Command Bar Options Execute Command The Enter key is used to activate sub menus when the selected feature is a sub menu or to display a pick list if a selected option has a value field or to select a sub field for multi valued features like time and date If a pick list is displayed the Enter key will undo the pick list and allow another selection in the parent menu 34 Revision 1 3
49. S cear Off Off Off Off Off Initialize SMM handler Initialize USB emulation Validate NVRAM areas Restore from backup if corrupted Load defaults in CMOS RAM if bad checksum or CMOS clear jumper is G Off detected Of Of i G Of A Of G Of G Of Determine number of micro code patches present 2 Scan SMBIOS GPNV areas Load vi R Eaexeedmemoywss LOW R Beevor _ m 6 Enable 8042 Enable timer and keyboard IRQs Set Video Mode Initialization A Off before setting the video mode is complete Configuring the monochrome mode and color mode settings next A G Init PCI devices and motherboard devices Pass control to video BIOS Start serial console redirection IR Initialize memory test parameters A Off Initialize AMI display manager Module Initialize support code for headless System if no video controller is detected Start USB controllers in chipset Set up video parameters in BIOS data area Activate ADM The display mode is set Displaying the power on message next Off Initialize language module Display splash logo Display Sign on message BIOS ID and processor information Detect USB devices Reset IDE Controllers R Displaying bus initialization error messages
50. Technical Product Specification Glossary Term Definition Universal Serial Bus Video Graphic Adapter
51. The following table shows the bit to which each IDSEL signal is attached for P64 C devices and corresponding device description Table 10 P64 C Configuration IDs PCI Slot 4 64bit 66 100MHz PCI Slot 6 64bit 100MHz Riser SE7221BK1LX sku 18 only 18 PCI Slot 5 64bit 66 100MHz 5 1 3 2 P64 C Arbitration P64 C supports two PCI masters two PCI X slots or one riser slot All PCI masters must arbitrate for PCI access using resources supplied by the ICH6 The host bridge PCI interface ICH6 arbitration lines REQx and GNTx are a special case in that they are internal to the host bridge The following table defines the arbitration connections Table 11 P64 C Arbitration Connections Baseboard Signals PCI Slot 4 64bit 66M PCI Slot 6 64bit 100M Riser SE7221BK1LX sku REQ NO GNT NO only PCIX N1 GNT PCI Slot 5 64bit 66M 16 Revision 1 3 SE7221BK1 E Technical Product Specification 5 1 4 PCI E x8 In this board Lanes 0 7 are connected to a x8 PCI E connector directly It can support x1 x4 x 8 PCI E add in cards Table 12 PCI E x 8 Connections Lane 5016 PCT Express 52 Video Controller The Intel amp E7221 GMCH includes an integrated graphics engine that supports standard SVGA drivers with analog display capabilities 8 MB of memory is pre allocated in the main memory to support the internal graphical device when less than 4 GB of physical memory is installed Howev
52. able details the pin out of this header Table 21 Front Panel 34 Pin Header Pin out J1J1 Signal Name Pin Pin Signal Name P5V STB 1 2 P5V STB KEY 3 4 P5V STB FP PWR LED N 5 6 NC P5V 7 8 P5V_STB HDD_LED 9 10 FP_STATUS_LED2_N 26 Revision 1 3 7221 1 Technical Product Specification Signal Name Pin Pin Signal Name FP PWR BTN N 11 12 LAN1 ACT N GND 13 14 LAN1 LINK UP N FP RST BTN N 15 16 5 PHL5V DAT RESET switch GND 17 18 MBMC SMC PHL5V CLK NC 19 20 NC GND 21 22 LAN2 ACT N NMIswtcht 293 24 LAN2 LINK UP N Key 25 26 Key P5V STB 27 28 P5V STB FP ID LED N 29 30 FP STATUS LED1 N FP ID BTN N 31 32 P5V GND 33 34 NC Note NC No Connect in this project 7 44 Connector The following table details the pin out of the VGA connector This connector is combined with COM connector Table 22 VGA Connector Pin out J8A1 Signal Name Pin Pin Signal Name RED B1 B9 Fused 5V DDCDAT GND NC HSY VSY DDCCLK Note NC No Connect in this project 7 5 Connector The Intel Server Board SE7221BK1 E supports two NIC RJ45 connectors The following tables detail the pin out of the connector Table 23 NIC1 82541P1 10 100 1000 Connector Pin out J5A1 Signal Name Pin Pin Signal Name LGND_LAN1 1 10 LAN1_TRDN3 LAN1_TRDPO 2 11 LAN1_LI
53. andard DH 10 to DB9 cable can be used to direct serial B to an external connector on any given chassis The serial B interface follows the standard RS232 pin out The baseboard has a Serial B silkscreen label next to the connector and is located beside the PCI32 5V connector 4 2 1 3 Floppy Disk Controller The floppy disk controller FDC in the Super IO is functionally compatible with floppy disk controllers in the DP8473 and N844077 All FDC functions are integrated into the Super IO including analog data separator and 16 byte FIFO The baseboard provides a standard 34 pin interface for the floppy disk controller 4 2 1 4 Keyboard and Mouse Two external PS 2 ports located on the back of the baseboard are provided to access the keyboard or mouse functions 4 2 1 5 Fast X Bus extension for boot flash memory and The fast X bus Supports and memory read write operations and 8 bit data bus 28 bit addressing 13 SE7221BK1 E Technical Product Specification 4 2 1 6 Wake up Control The Super IO contains functionality that allows various events to control the power on and power off the system 4 2 2 BIOS Flash The board incorporates Intel 28F320C3 flash memory component The 28F320C3 is high performance 32 megabit memory component that provides 2096K x 16 of BIOS and non volatile storage space The flash device is connected through the X Bus from Super IO 4 2 3 System Health Support 2 interface t
54. ble 45 BIOS Setup Floppy Configuration Sub menu Selections Disabled Select the type of floppy drive Note Intel no longer 1 44 MB 3 1 2 connected to the system validates 720 Kb amp 2 88 Mb drives Onboard Floppy Controller Disabled Allows BIOS to Enable or Enabled Disable Floppy Controller 9 5 2 4 Super configuration sub menu Table 46 BIOS Setup Super Configuration Sub menu Serial Port Address Disabled Allows BIOS to Select Serial Port1 Option that is used by other serial port 3F8 IRQ4 Base Addresses is hidden to prevent conflicting 2F8 IRQ3 settings 3E8 IRQ4 2E8 IRQ3 40 Revision 1 3 7221 1 Technical Product Specification Serial Port 2 Address Disabled Allows BIOS to Select Serial Port2 Option that is used by other serial port 3F8 IRQ4 Base Addresses is hidden to prevent conflicting 2F8 IRQ3 settings 3E8 IRQ4 2E8 IRQ3 9 5 2 5 USB configuration sub menu Table 47 BIOS Setup USB Configuration Sub menu Selections Feature Help Text MC Devices List of USB Enabled devices detected by BIOS USB Function Disabled Enables USB HOST controllers When the item is 2 USB ports disabled Legacy Ports USB Support USB 2 0 Controller and USB 2 0 Controller mode will all disappear Legacy USB Support Disabled Enables support for legacy USB AUTO option disables Auto Enables port 60 64h emulation support This should Enabled be enabled for the compl
55. causes the following message to appear Save configuration changes and exit setup OK Cancel If OK is selected and the Enter key is pressed all changes are saved and setup is exited If Cancel is selected and the Enter key is pressed or the ESC key is pressed the user is returned to where they were before F10 was pressed without affecting any existing values 9 5 Entering BIOS Setup The BIOS Setup utility is accessed by pressing the F2 hotkey during POST 9 5 1 Main Menu The first screen displayed when entering the BIOS Setup Ultility is the Main Menu selection screen This screen displays the major menu selections available The following tables describe the available options on the top level and lower level menus Default values are shown in bold text Table 40 BIOS Setup Main Menu Options Feature Options Help Text NA time and date Peces NA NA me au Count Detected number of physical oo Sym Memory System Time d Use ENTER TAB or SHIFT Configures the system time on a 24 TAB to select a field hour clock Default is 00 00 00 Use or to configure system time System Date DAY MM DD YYYY Use ENTER TAB or SHIFT Configures the system date TAB to select a field Default is Tue 01 01 2002 Day of Use to configure System the week is automatically date calculated of physical memory detected 36 Revision 1 3
56. ches for and configures PCI input devices and detects if system has standard keyboard controller Function 4 searches for and configures all PnP and PCI boot devices Function 5 configures all onboard peripherals that are set to an automatic configuration and configures all remaining PnP and PCI devices 9 7 3 5 Runtime Checkpoints ACPI checkpoints are displayed when an ACPI capable operating system either enters or leaves a sleep state The following table describes the type of checkpoints that may occur during ACPI sleep or wake events Table 74 ACPI Runtime Checkpoints Checkpoint i First ASL check point Indicates the system is running in ACPI mode System is running in APIC mde is System is running in APIC mode in APIC mode 1 02 03 04 05 Entering sleep state S1 52 S3 54 55 10 20 30 40 50 Waking from sleep state S1 S2 S3 S4 or S5 63 SE7221BK1 E Technical Product Specification 9 8 Diagnostic LEDs All port 80 codes are displayed using the Diagnostic LEDs found on the back edge of the baseboard The diagnostic LED feature consists of a hardware decoder and four dual color LEDs During POST the LEDs will display all normal POST codes representing the progress of the BIOS POST Each code will be represented by a combination of colors from the four LEDs The LEDs are capable of displaying three colors Green Red and Amber The POST codes are divided into two nibbles
57. ded to enter the S4 sleep state the operating system will write the system context to a non volatile storage file and leave appropriate context markers S5 Sleep State S5 sleep state is similar to the S4 sleep state except the operating system does not save any context nor enable any devices to wake the system The system is in the soft off state and requires a complete boot when awakened 6 1 1 Front Panel Switches The baseboard supports two front panel buttons Power button Reset button Power Button Off to On The power button input J1J1 pin 11 13 provides PWR signal to the mBMC PC87431M mBMC will output a PWR signal to ICH6 If the PWRBTN signal of ICH6R is asserted the assertion causes a wake event And then the 53 signal of ICH6R will be not asserted The 53 signal will be passed to the PS ON signal of ATX power 23 SE7221BK1 E Technical Product Specification supply through an inverter and then transition to an ON state Power Button On to Off The ICH6 is configured to generate an SMI due to a power button Legacy event The BIOS services this SMI and sets the state of the machine in the ICH6 and Super IO to the OFF state Power Button On to Off ACPI operating system is loaded the power button switch ACPI generates a request via SCI to the OS to shutdown the system The OS retains control of the system and determines what sleep state if
58. dependent PCI Buses Segment A One PCI 32 bit 33 MHz 5 V connector supporting full length PCI add in cards and one embedded device Supports Specification Rev 2 3 One Intel 10 100 1000 82541 gigabit Ethernet Controller Segment B One PCI 32 bit 66 MHz embedded device SE7221BK1LX sku only One Intel 10 100 1000 82541 PI gigabit Ethernet Controller Segment C Two PCI X 64 bit 66 MHz 3 3 V slots supporting full length full height PCI PCI X add in cards or one 3 3V PCI X 64 bit 100 MHz slot with riser card SE7221BK1LX sku only Segment D One x8 PCI Express slot supporting x1 x2 x4 x8 PCI Express add in card or one PCI 55 slot with riser card SE7221BK1LX sku only Serial ATA host controller Four independent SATA ports supports data transfer rates up to 1 5 Gb s 150MB s per port IDE controller One IDE connector supporting up to two ATA 100 compatible devices Revision 1 3 7221 1 Technical Product Specification USB 2 0 Two external Universal Serial Bus USB ports with an additional internal header providing two optional USB ports for front panel support Supports wake up from sleeping states 51 54 Supports legacy Keyboard Mouse connections when using PS2 USB dongle LPC Low Pin Count bus segment with one embedded devices Super I O Super IO controller chip NS PC87427 providing all PC compatible I O floppy serial keyboard mouse two serial com port
59. does not exceed the Class A limits for radio noise emissions from digital apparatus set out in the interference causing equipment standard entitled Digital Apparatus ICES 003 of the Canadian Department of Communications Cet appareil num rique respecte les limites bruits radio lectriques applicables aux appareils num riques de Classe A prescrites dans la norme sur le mat riel brouilleur Apparelis Num riques NMB 003 dictee par le Ministre Canadian des Communications 13 2 3 Europe CE Declaration of Conformity This product has been tested in accordance to and complies with the Low Voltage Directive 73 23 and Directive 89 336 EEC The product has been marked with the CE Mark to illustrate its compliance 13 2 4 Taiwan Declaration of Conformity This product has been tested and complies with CNS13438 The product has been marked with the BSMI DOC mark to illustrate compliance 13 2 5 Korean RRL Compliance This product has been tested and complies with MIC Notices No 1997 41 and 1997 42 The product has been marked with the MIC logo to illustrate compliance 78 Revision 1 3 SE7221BK1 E Technical Product Specification 1 21719 2 01598 MIC 3 1582 6 4 51551424191 5 The English translation for the above is as follows 1 Type of Equipment Model Name SE7221BK1 E 2 Certification No Contact Intel Representative 3 Name of Certification Recipient
60. e 72 Bootblock Recovery Code Checkpoint 62 Table 73 DIM Gode m u 63 Table 74 ACPI Runtime Checkpoints U u u u 63 9 8 DiaghostIe LEDS steep 64 9 8 1 Diagnostic LED POST Progress Codes euet 64 Table 76 Boot Block POST Progress Codes 64 Table 77 POST Progress Codes teach ees 65 10 eS 68 10 1 Intel Server Board SE7221BK1 E Power Budget 68 10 2 Power Supply Specifications ose necp ee es cuius 69 10 2 1 Power Timing Requirements e eden ix per RR 69 10 2 2 Dynamic ob o ptio ette pi 71 10 23 Line Transient Specification 72 10 24 Line Fast Transient EFT Specification 72 11 Absolute Maximum Ratings riso ances Rea P LEE D NE 72 11 1 Mean Time Between Failures MTBF Test Results 73 12 Hard
61. e PS 2 Connectors Pin out KM9A1 PS 2 Connectors Pin Signal Name Keyboard K1 RKBDATA K2 NC K3 GND K4 P5V_KB_MS K5 RKBCLK K6 NC Mouse M1 MSEDATA M2 NC M3 GND M4 P5V_KB_MS M5 RMSCLK M6 NC 7 12 Miscellaneous Headers 7 12 1 Fan Header There are four 3 pin fan headers JP5J1 JP5J2 JP7A1 and JP6A1 These fan headers have the same pin out and are detailed below Table 33 Three pin Fan Headers Pin out JP5J1 JP5J2 JP7A1 JP6A1 speed Pin Signal Name Type Description 1 Ground Power GROUND is the power supply ground 2 Fan Power Power Fan Power with FAN_SPEED_CNTL1 Fan speed control 3 Fan Tach Out FAN_TACH signal is connected to the LM96000 to monitor the FAN 31 SE7221BK1 E Technical Product Specification There are also four 8 pin fan headers J6J1 J6J2 J6J3 J6J4 These fan headers have the same pin out and are detailed below Table 34 Eight pin Fan Header Pin out J6J1 J6J2 J6J3 and J6J4 Pin Signal Name Type Description 1 Fan Power Power Fan Power with SPEED Fan speed control 2 Fan Tach Out FAN TACH signal is connected to the Super IO LM96000 to monitor the FAN speed 3 Ground Power GROUND is the power supply ground 4 NC 5 Ground Power GROUND is the power supply ground 6 Ground Power GROUND is the power supply ground 7 Fan Tach Out F
62. e Transient Specification AC line transient conditions shall be defined as sag and surge conditions Sag conditions are also commonly referred to as brownout these conditions will be defined as the AC line voltage dropping below nominal voltage conditions Surge will be defined to refer to conditions when the AC line voltage rises above nominal voltage The power supply shall meet the requirements under the following AC line sag and surge conditions Table 83 AC Line Sag Transient Performance AC Line Sag Duration Sag Operating AC Voltage Line Frequency Performance Criteria Continuous 1096 Nominal AC Voltage ranges 50 60Hz No loss of function or performance 0 to 1 AC 10096 Nominal AC Voltage ranges 50 60Hz No loss of function or performance cycle 1 AC cycle gt 10 Nominal AC Voltage ranges 50 60 2 Loss of function acceptable self recoverable Table 84 AC Line Surge Transient Performance AC Line Surge Duration Surge Operating AC Voltage Line Frequency Performance Criteria Continuous 1096 Nominal AC Voltages 50 60Hz No loss of function or performance 0 to 1 2 AG 3096 Mid point of nominal AC 50 60Hz No loss of function or performance cycle Voltages 10 2 4 AC Line Fast Transient EFT Specification The power supply shall meet the EN61000 4 5 directive and any additional requirements in IEC1000 4 5 1995 and the Level 3 requirements for surge withsta
63. e allows direct connection with the PXH PXHD or PCI E devices Fully compliant to the PC Express Base Specification Rev 1 0a 4 1 3 3 PCI Bus Master IDE Interface The ICH6R acts as a PCl based Ultra ATA 100 66 33 IDE controller that supports programmed I O transfers and bus master IDE transfers The ICH6R supports one IDE channel supporting two drives each drives 0 and 1 The baseboard provides a 40 pin 2x20 IDE connector to access the IDE functionality The IDE interface supports Ultra ATA 100 66 33 Synchronous DMA Mode transfers on the 40 pin connector 4 1 3 4 USB Interface The ICH6R contains one EHCI USB 2 0 controller and four USB ports The USB controller moves data between main memory and up to four USB connectors All ports function identically and with the same bandwidth The Intel amp Server Board SE7221BK1 E implements four ports on the board The baseboard provides two external USB ports on the back of the server board The dual stack USB connector is located within the standard ATX I O panel area The Universal Serial Bus Specification Revision 1 1 defines the external connectors The third fourth USB port is optional and can be accessed by cabling from an internal 9 pin connector located on the baseboard to an external USB port located either in front or the rear of a given chassis 4 1 3 5 SATA interface The ICH6R contains four SATA ports The data transfer rates up to 150Mbyte s 4 1 3 6 Compatibility Interr
64. echnical Product Specification 7 7 SATA Connector ICH6R integrated SATA controller with four SATA ports output The pin out for these four connectors is listed below Table 26 SATA Connector Pin out J1G1 J1G2 J1J2 J2J1 Signal Name GND SATAO TX P SATAO TX N GND SATAO RX N GND O 1 7 88 USB Connector The following table provides the pin out for the dual external USB connectors This connector is combined with RJ45 connected to COM2 signals Table 27 USB Connectors Pin out J5A1 Pin Signal Name 0655 GND 064 header on the server board provides an option to support one additional USB connector pin out of the header is detailed in the following table Table 28 Optional USB Connection Header Pin out 1 Signal Name Pin Pin Signal Name Fused 5V over 1 2 Fused VCC 5V w over current monitor of both port 0 current monitor of both port 1 USB B2 N 3 USB B1 N USB B2 P 5 USB B1 P GND 7 8 GND Key 9 10 NC 29 SE7221BK1 E Technical Product Specification 7 9 Floppy Connector The board provides a standard 34 pin interface to the floppy drive controller The following tables detail the pin out of the 34 pin floppy connector Table 29 Legacy 34 pin Floppy Connector Pin out JP3J1 Signal Name Pin Pin Signal Name GND 1 2 FDDE
65. elect on the PCI bus segment in configuration cycles This determines a 14 Revision 1 3 7221 1 Technical Product Specification unique PCI device ID value for use in configuration cycles The following table shows the bit to which each IDSEL signal is attached for P32 A devices and the corresponding device description Table 6 P32 A Configuration IDs Intel 82541PI LAN PCI Slot 1 32b 33MHz 5 1 1 2 P32 A Arbitration P32 A supports two PCI devices the ICH6R and one PCI bus masters NIC All PCI masters must arbitrate for PCI access using resources supplied by the ICH6R The host bridge PCI interface ICH6R arbitration lines REQx GNTx are a special case in that they are internal to the host bridge The following table defines the arbitration connections Table 7 P32 A Arbitration Connections Baseboard Signals Device PCI 1 N GNT Intel 82541 LAN PCI REQO N GNT NO PCI Slot 1 32bit 33MHz 5 1 2 P32 B 66 MHz PCI X Subsystem SE7221BK1LX sku only One 32 bit PCI bus segment is directed through the PXH interface A This PCI segment 32 just has an embedded device Intel 82541 LAN NIC2 clocked at 66MHz SE7221BK1LX sku only 5 1 2 1 Device IDs IDSEL Each device under the PCI hub bridge has its IDSEL signal connected to one bit of AD 31 16 which acts as a chip select on the PCI bus segment in configuration cycles This determines a unique P
66. elect the mechanism for Detection Host detecting 80Pin ATA PI Cable Device Table 44 BIOS Setup IDE Device Configuration Sub menu Selections Feature Options Help Text 5 Display S M A R T support Type Not Installed Select the type of device connected The Auto setting should work in Auto to the system most cases CDROM ARMD LBA Large Mode Disabled Disabled Disables LBA Mode The Auto setting should work in Auto Auto Enabled LBA Mode if the most cases device supports it and the device is not already formatted with LBA Mode disabled 39 SE7221BK1 E Technical Product Specification Feature Options Help Text Block Multi Sector Disabled Disabled The Data transfer from The Auto setting should work in Transfer Auto and to the device occurs one sector most cases at a time Auto The data transfer from and to the device occurs multiple sectors at a time if the device supports it PIO Mode Auto Select PIO Mode The Auto setting should work in 0 most cases 1 2 3 4 DMA Mode Auto Selcet DMA Mode The Auto setting should work in SWDMAO0 2 Auto Auto detected most cases 2 SWDMA SinglewordDMAn UWDMAO 5 MWDMA MultiwordDMAn UWDMA UltraDMAn S M A R T Auto S M A R T stands for Self The Auto setting should work in Disabled Monitoring Analysis and Reporting most cases Enabled Technology ANA 111 Enabled 9 5 2 3 Floppy configuration sub menu Ta
67. emory made available to the operating system is significantly lower than 4 GB roughly 3200 MB THIS IS ONLY AN ISSUE WHEN 4 GB OF MEMORY IS USED A memory configuration of less than 4 GB will not be susceptible to this issue Please refer to Intel Technical Advisory TA 719 01 on the support web site located at http support intel com support motherboards server SE7221BK1E The minimum memory capacity is 256 MB 1 x 256 MB DIMM module 3 2 1 2 Memory Configuration The memory interface between the GMCH and the DIMMs is 64 bit non ECC 72 bit ECC wide interface There are two banks of DIMMs labeled 1 and 2 Bank 1 contains DIMM socket locations DIMM and DIMM 24A Bank 2 contains DIMM socket locations DIMM 1B and DIMM 2B The sockets associated with each bank or channel are located next to each other and the DIMM socket identifiers are marked on the baseboard silkscreen near the DIMM socket Bank 1 is associated with Memory Channel A while Bank 2 is associated with Memory Channel B When only two DIMM modules are being used the population order must be DIMM 14A DIMM 1B to ensure dual channel operating mode To reiterate In order to operate in Dual Channel Dynamic Paging Mode the following conditions must be met e 2identical DIMMs are installed one each in DIMM 1A and DIMM 1B 4identical DIMMs are installed one in each socket location Installing only 3 DIMMs is not supported Do not use DIMMs that are not
68. en updated successfully Make flash write disabled Disable ATAPI hardware Restore CPUID value back into register Give control to 000 ROM at FO 1 2 5 Check the validity of the recovery configuration to the current configuration of the flash part F4 FC FD FF F000 FFFOh 62 Revision 1 3 7221 1 Technical Product Specification 9 7 3 4 DIM Code Checkpoints The Device Initialization Manager Module gets control at various times during BIOS POST to initialize different BUSes The following table describes the main checkpoints where the DIM module is accessed Table 73 DIM Code Checkpoints Checkpoint Description 2A Initialize different buses and perform the following functions Reset Detect and Disable function 0 Static Device Initialization function 1 Boot Output Device Initialization function 2 Function 0 disables all device nodes PCI devices and PnP ISA cards It also assigns PCI bus numbers Function 1 initializes all static devices that include manual configured onboard peripherals memory and decode windows in PCI PCI bridges and noncompliant PCI devices Static resources are also reserved Function 2 searches for and initializes any PnP PCI or AGP video devices Initialize different buses and perform the following functions Boot Input Device Initialization function 3 IPL Device Initialization function 4 General Device Initialization function 5 Function 3 sear
69. enerations like the Intel Pentium 4 processor bus interface unit the hub interface unit and the DDR2 memory interface unit In addition the GMCH incorporates an integrated high performance graphics media accelerator and a PCI Express interface The PCI Express interface allows the GMCH to directly interface with the PCI Express devices like PXH PXHD The GMCH also increases the main memory interface bandwidth and maximum memory configuration with a 72 bit wide memory interface The GMCH integrates the following main functions 10 An integrated high performance main memory subsystem Revision 1 3 7221 1 Technical Product Specification A PCI Express bus which provides an interface to the PCI Express devices Fully compliant to the Express Base Specification Rev 1 0a ADMI which provides an interface to the ICH6R Other features provided by the GMCH include the following Full support of ECC on the processor bus Full support of Intel x4 SDDC on the memory interface with x4 DIMMs Twelve deep in order queue two deep defer queue Full support of un buffered DDR2 ECC DIMMs Support for 1 GB DDR2 memory modules Memory scrubbing 4 1 3 ICH6R The ICH6R is a multi function device housed 609 mBGA device providing a DMI bus a PCI 32 bit 33 MHz interface a IDE interface an integrated Serial ATA Host controller a USB controller a PCI E x4 interface and a power managemen
70. er when the maximum of 4 GB of memory is installed onboard system resources such as video consume a considerable amount of memory leaving just above 3 GB of available memory for the operating system Details of this issue have been communicated via the Technical Advisory TA 719 01 which can be found at http support intel com support motherboards server SE7221BK1 E The baseboard provides a standard 15 pin VGA connector at the rear of the system in the standard ATX I O opening area The video controller is disabled by default in BIOS Setup when an off board video adapter is detected in either the PCI E or PCI slots 5 3 Network Interface Controller NIC The Intel Server Board SE7221BK1 E supports two 10Base T 100Base 1000Base T 82541 controller network interfaces One is through ICH6R directly and another one is through PXH SE7221BK1LX sku only The Intel 82541 Gigabit Ethernet is a single compact component with an integrated Gigabit Ethernet Media Access Control MAC and physical layer PHY functions For desktop workstation and mobile PC Network designs with critical space constraints the Intel amp 82541 allows for a Gigabit Ethernet implementation in a very small area that is footprint compatible with current generation 10 100 Mbps Fast Ethernet designs The Intel 82541 integrates fourth generation gigabit MAC design with fully integrated physical layer circuitry to provide a standard IEEE 802 3 Ethernet in
71. er to which an updated BIOS version can be written When ready the system can roll forward to the new BIOS In case of a failure with the new version the system can roll back to the previous version While the exact nature of hardware changes for the support of on line update rolling BIOS are out of scope of this document BIOS relies on specialized hardware and additional flash space for this Flash is divided into two partitions viz primary and secondary The active partition from which the system boots shall be referred to as the primary partition The AMI FLASH update suite and Intel On line updates preserve the existing BIOS image on the primary partition BIOS updates are diverted to the secondary partition After the update a notification flag will be set During the subsequent boot following BIOS update system will continue to attempt to boot from primary BIOS partition On determining that a BIOS update occurred in the previous boot system will attempt to boot the new BIOS If a failure happens specialized hardware will switch back to the BIOS on the other partition thus affecting a Roll Back 53 SE7221BK1 E Technical Product Specification 9 6 3 1 Recovery Mode Three conditions can cause the system to enter recovery mode Pressing a hot key setting the recovery jumper and damage to both partitions of the ROM image will cause the system to enter recovery and update System ROM without the boot block 54 BIOS Recovery
72. erating systems Intel amp Celeron amp Processor currently does not support 64 3 1 1 Processor VRD The Intel amp Server Board SE7221BK1 E has a VRD Voltage Regulator Down to support one processor It is compliant with the VEM 10 1 DC DC Converter Design Guide Line and provides a maximum of 120A which is capable of supporting the requirements for Intel Pentium 4 and Intel Celeron D processors The board hardware must monitor the processor VTTEN Output enable for VTT pin before turning on the VRD If the VTTEN pin of the processors is not identical the Power ON Logic will not turn on the VRD 3 1 2 Reset Configuration Logic The BIOS determines the processor stepping cache size etc through the CPUID instruction The requirements are as follows Processors run at a fixed speed but can be programmed by BIOS to operate at a lower or higher speed The processor information is read at every system power on Note The processor speed is the processor power on reset default value No manual processor speed setting options exist either in the form of a BIOS setup option or jumpers 3 1 3 Processor Module Presence Detection SE7221BK1 E does not support this function 3 1 4 Processor Support The Intel amp Server Board SE7221BK1 E supports one processor in the LGA775 package The support circuitry on the server board consists of the following 7221 1 Technical Product Specification LGA775 processo
73. ete USB keyboard legacy support for non USB aware OS Disabled USB 2 0 Controller FullSpeed Configures the USB 2 0 controller in HiSpeed 480 Mbps When USB 2 0 mode HiSpeed or FullSpeed 12 Mbps Controller is disabled it will disappear USB Mass Storage N A Configures the USB Mass Storage Device Class Selects submenu Device Configuration with USB Device enable 9 5 2 5 1 USB mass storage device configuration sub menu Table 48 BIOS Setup USB Mass Storage Device Configuration Sub menu Selections Feature Options Help Text USB Mass Storage Number of seconds POST waits for the USB mass Reset Delay storage device after start unit command Device 1 N A N A Only displayed if a device is detected includes a DevicelD string returned by the USB device 41 Emulation Type Auto Floppy Forced FDD Hard Disk CDROM Device Emulation Type Auto Floppy Forced FDD Hard Disk CDROM SE7221BK1 E Technical Product Specification If Auto USB devices less than 530 MB will be emulated as Floppy and remaining as hard drive Forced FDD option can be user to force a HDD formatted drive to boot as FDD Ex ZIP drive Only displayed if a device is detected Includes a DevicelD string returned by the USB device If Auto USB devices less than 530 MB will be emulated as Floppy and remaining as hard drive Forced FDD option can be user to force a HDD formatted drive to boot as FDD Ex ZIP drive 9 5 2
74. ference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does 77 SE7221BK1 E Technical Product Specification cause harmful interference to radio or television reception which can be determined by turning the equipment off and on the user is encouraged to try to correct the interference by one or more of the following measures or relocate the receiving antenna Increase the separation between the equipment and the receiver Connect the equipment to an outlet on a circuit other than the one to which the receiver is connected Consult the dealer or an experienced radio TV technician for help Any changes or modifications not expressly approved by the grantee of this device could void the user s authority to operate the equipment The customer is responsible for ensuring compliance of the modified product Only peripherals computer input output devices terminals printers etc that comply with FCC Class A or B limits may be attached to this server product Operation with noncompliant peripherals is likely to result in interference to radio and TV reception All cables used to connect to peripherals must be shielded and grounded Operation with cables connected to peripherals that are not shielded and grounded may result in interference to radio and TV reception 13 2 2 INDUSTRY CANADA ICES 003 This digital apparatus
75. g in 50 1000 msec regulation at AC turn on T5VSB holdup Time the 5VSB output voltage stays within regulation 70 msec after loss of AC 70 Revision 1 3 7221 1 Technical Product Specification AC Input s le Tvout holdup Te gt PWOK 10 2 2 Tpwok_on Tpwok_holdup i 5 hoidup on off cycle s gt Tpwok_low Tac_ondelay _ i lt I H gt kK on delay Tpson on delay lt PSON turn on off cycle Figure 9 Turn On Off Timing Power Supply Signals Dynamic Loading The output voltages shall remain within limits specified for the step loading and capacitive loading specified in the table below The load transient repetition rate shall be tested between 50Hz and 5kHz at duty cycles ranging from 1096 9096 The load transient repetition rate is only a test specification The A step load may occur anywhere within the MIN load to the MAX load conditions 45V 12V 5VSB Notes Table 82 Transient Load Requirements A Step Load Size Load Slew Rate Test capacitive Load See note 2 1 Step loads on each 12V output may happen simultaneously 2 For Load Range 2 light system loading the tested step load size should be 60 of those listed i ED 71 SE7221BK1 E Technical Product Specification 10 2 3 AC Lin
76. he mechanical switch is in the closed position 13 Product Regulatory Compliance 13 1 1 Product Safety Compliance The SE7221BK1 E complies with the following safety requirements UL 1950 CSA 950 US Canada EN 60 950 European Union EC60 950 International CE Low Voltage Directive 73 23 EEC European Union EMKO TSE 74 SEC 207 94 Nordics GOST 50377 92 Russia 13 1 2 Product EMC Compliance The SE7221BK1 E has been has been tested and verified to comply with the following electromagnetic compatibility EMC regulations when installed in a compatible Intel host system For information on compatible host system s contact your local Intel representative FCC Class A Verification Radiated amp Conducted Emissions USA 5 003 Class A Radiated amp Conducted Emissions Canada CISPR 22 3 Edition Class A Radiated amp Conducted Emissions International EN55022 Class Radiated amp Conducted Emissions European Union EN55024 Immunity European Union CE ENC Directive 89 336 EEC European Union VCCI Class A Radiated amp Conducted Emissions Japan AS NZS 3548 Class A Radiated amp Conducted Emissions Australia New Zealand RRL Class Radiated amp Conducted Emissions Korea BSMI 513438 Class Radiated amp Conducted Emissions Taiwan GOST 29216 91 Class A Radiated amp Conducted Emissions Russia GOST R 506
77. he preceding chapters For ease of use numeric entries are listed first e g 82460GX with alpha entries following e g AGP 4x Acronyms are then entered in their respective place with non acronyms following BGA 8 bit quantity In terms of this specification this describes the PC AT compatible region of battery backed 128 bytes of memory which normally resides on the server board EPS is LCD Liquid crystal display Glossary SE7221BK1 E Technical Product Specification Tem i T n MBE Multi Bit Error milliseconds 5 Most Significant Bit lt o I MTBF Mean Time Between Failures Mux multiplexor 2 Private Management Bus MC Platform Management Controller E M Power Management Event Plug and Play li POST Power on Self Test PWM Pulse Width Modulator RAIDIOS RAID I O Steering AM Random Access Memory Ring Indicate RISC Reduced instruction set computing RMCP Remote Management Control Protocol RO Read Only Memory RTC Real Time Clock B Single Bit Error T E CI System Configuration Interrupt SDR Sensor Data Record L SDRAM se sema SERR su su 5 SNMP Ezra SPD Serial Presence Detect SI Server Standards Infrastructure S TP Technical Product Specification UART Universal asynchronous receiver and transmitter M 5 0 II Revision 1 3 SE7221BK1 E
78. iability or warranties relating to fitness for a particular purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them This document contains information on products in the design phase of development Do not finalize a design with this information Revised information will be published when the product is available Verify with your local sales office that you have the latest datasheet before finalizing a design Intel Corporation server baseboards contain a number of high density VLSI and power delivery components which need adequate airflow to cool Intel s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application
79. ility and performance of the board under extreme working conditions For the SE7221BK1 E server board MTBF was measured at 190 727 hours at 40 degrees Centigrade 12 Hardware Monitoring 12 1 Monitored Components The Intel amp Server Board SE7221BK1 E has an integrated LM96000 chip that is responsible for hardware monitoring The LM96000 chip provides basic server hardware monitoring which alerts a system administrator if a hardware problem occurs on the board The NS super IO PC87427 has implemented some FAN speed control monitor pins Below is a table of monitored headers and sensors on the board Table 86 Monitored Components Item Description Voltage PIN 24 Monitors processor voltage LM96000 P12V PIN 221 Monitors 12Vin for system 12V supply LM96000 1 8 PIN 22 Monitors 1 8V DDRII power LM96000 P5V PIN 20 Monitors 5 LM96000 Fan Speed PWM 24 Controlssystemfrontfans 1 96000 JP5J1 JP5J2 JP7A1 JP6A1 J6J3 J6J1 J6J4 J6J2 PWMe PIN 10 Controls CPU fans J7A1 LM96000 IPWM3 PINZI3 NA 1 96000 TACH1 PIN 11 Monitors CPU fan 74 1 96000 2 PIN 12 Monitors SYS FAN JP5J1 LM96000 PIN 49 Monitors SYS FAN 4 JP5J2 LM96000 7 SE7221BK1 E Technical Product Specification 74 FANINO PIN 66 Monitors SYS FAN 2 JP7A1 SYS FAN 5 J6J1 Super IO FANI
80. ith x4 DIMMs Memory can be implemented with either single sided one row or double sided two row DIMMs 3 2 1 1 Memory DIMM Support The board supports un buffered not registered DDR2 400 533 compliant ECC or Non ECC DIMMs operating at 400 533MT s Only DIMMs tested and qualified by Intel or a designated memory test vendor are supported on this board A list of qualified DIMMs is available at http support intel com support motherboards server SE7221BK1E Note that all DIMMs supported by design but only fully qualified DIMMs will be supported on the board The minimum supported DIMM size is 256 MB Therefore the minimum main memory configuration is 1 x 256 MB or 256 MB The largest size DIMM supported is 2 GB however the maximum main memory configuration is 4 GB implemented by 4 x 1 GB or 2 x 2 GB DIMMs Only un buffered DDR2 400 533 compliant ECC x8 and Non ECC x8 or x16 memory DIMMs are supported ECC single bit errors SBE will be corrected and multiple bit error MBE will be detected Intel Server Board SE7221BK1 E also supports Intel x4 SDDC with x4 DIMMs 6 Revision 1 3 SE7221BK1 E Technical Product Specification The maximum memory capacity is 4 GB Note Although the Intel amp Server Board SE7221BK1 E supports a maximum memory capacity of 4 GB system resources consume roughly 750 MB of physical memory in the maximum memory configuration As a result when 4 GB of memory is used the amount of m
81. ksum error does not occur during POST To manually initiate a BIOS recovery use the following steps 1 Power down and unplug the system from the AC power source 2 Move the recovery jumper at J1F2 from the storage position at pins 9 and 10 to cover pins 10 and 11 See the figure below 3 Insert the Crisis Recovery Diskette into the A diskette drive 4 Plug the system into the AC power source and power it on 5 A blue screen will be displayed and the recovery process will automatically run The system will continue to beep throughout the recovery process The recovery process is complete when the beeping stops 6 Remove the diskette 7 Power down and unplug the system from the AC power source 8 Move the BIOS recovery jumper at J1F2 back to the original position covering storage pins 9 and 10 55 7221 1 Technical Product Specification 9 Plug the system into the AC power source and power it up to confirm that the recovery was successful ELL ALAE LITE OEY OEE MINI JY wwe EE wee il gt 1100 2 7 5 9 7 Error Handling and Reporting 9 7 1 POST Error Beep Codes Table 67 POST Error Beep Codes Beeps Error Message POST Progress Code Description 1 Fatal error System halted because of a
82. latency time for compatibility interrupt sources The 1 APICs can also supply greater than 16 interrupt levels to the processor s This APIC bus consists of an APIC clock and two bidirectional data lines 5 4 2 1 Legacy Interrupt Sources The table below recommends the logical interrupt mapping of interrupt sources on the board The actual interrupt map is defined using configuration registers in the ICH6 18 Revision 1 3 7221 1 Technical Product Specification Table 14 Interrupt Definitions Desorption 0 5 4 3 Serialized IRQ Support The SE7221BK1 E server board supports a serialized interrupt delivery mechanism Serialized Interrupt Requests SERIRQ consists of a start frame a minimum of 17 IRQ data channels and a stop frame Any slave device in the quiet mode may initiate the start frame While in the continuous mode the start frame is initiated by the host controller 5 5 PCI Error Handling The PCI bus defines two error pins PERR and SERR for reporting PCI parity errors and system errors respectively In the case of PERR the PCI bus master has the option to retry the offending transaction or to report it using SERR All other PCl related errors are reported by SERR SERRE is routed to NMI if enabled by BIOS 19 20 IRQO IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 IRQ16 IRQ17 IRQ18 IRQ19 IRQ20
83. lects submenu Revision 1 3 7221 1 Technical Product Specification Featue Options Assert NMI on PERR Disabled Assert NMI on SERR Disabled Resume on AC Power Loss Stays Off Power On Help Text If enabled NMI is generated SERR option needs to be enabled to activate this option If enabled NMI is generated on SERR and logged Determines the mode of operation if a power loss occurs Stays off the system will remain off Description once power is restored Power On boots the System after power is restored Late POST Timeout This controls the time limit for add in card detection The system is reset on timeout Disabled 5 minutes 10 minutes 15 minutes 20 minutes Disabled 5 minutes 10 minutes 15 minutes 20 minutes Disabled 5 minutes 10 minutes 15 minutes 20 minutes Stay On Reset Power Off Hard Disk OS Boot Timeout This controls the time limit allowed fo booting an operating system from a Hard disk drive The action taken on timeout is determined by the OS Watchdog Timer policy setting PXE OS Boot Timeout This controls the time limit allowed for booting an operating system using PXE boot The action taken on timeout is determined by OS Watchdog Timer policy setting OS Watchdog Timer Policy Controls the policy upon timeout Stay on action will take no overt action Reset will force the System to reset Power off will force the system to power off Platform Event Filtering E
84. llisesti asennettu Vaihda paristo ainoastaan laitevalmistajan suosittelemaan tyyppiin H vit k ytetty paristo valmistajan ohjeiden mukaisesti 79 7221 1 Technical Product Specification 13 4 Calculated Mean Time Between Failures MTBF The MTBF Mean Time Between Failures for the Intel amp Server Board SE7221BK1 E as configured from the factory is shown in the table below Table 88 MTBF Data Product Code Calculated MTBF Operating Temperature SE7221BK1 TBD hours 35 degrees C SE7221BK1LX TBD hours 35 degrees C 13 5 Mechanical Specifications The following figure shows the Intel amp Server Board SE7221BK1 E mechanical drawing This drawing will be updated in a future revision of this document 80 Revision 1 3 SE7221BK1 E Technical Product Specification THIS DRAMIMG CONTAINS INTEL CORPORATION CONFIDENTIAL IMFORMATION IT 15 DISCLOSED IW CONFIDENCE AND ITS CONTENTS WEVPEAUM PST Lay WAY HOT BE DISCLOSED REPRODUCED DISPLAYED OA WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION PIN CPU MTE LX ADDITIONAL ET 8 SPIN FA ow 51 EEB jns 0 24 85 POWER 5455 es 1 400 40 005 Y dut 0 0 060 gt a ae a NS PAD 1 001 mr Ay M BOTH SIDES
85. lock checksum Disable CACHE before memory detection Execute full memory sizing module Verify that flat mode is enabled If memory sizing module not executed start memory refresh and do memory sizing in Bootblock code Do additional chipset initialization Re enable CACHE Verify that flat mode is enabled Test base 512KB memory Adjust policies and cache first 8MB Set stack Bootblock code is copied from ROM to lower system memory and control is given to it BIOS now executes out of RAM Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced Main BIOS checksum is tested If BIOS recovery is necessary control flows to checkpoint EO See Bootblock Recovery Code Checkpoints section of document for more information D2 3 D D4 5 D Restore CPUID value back into register The Bootblock Runtime interface module is moved to system memory and control is given to it Determine whether to execute serial flash The Runtime module is uncompressed into memory CPUID information is stored in memory Store the Uncompressed pointer for future use in PMM Copying Main BIOS into memory Leaves all RAM below 1MB Read Write including E000 and F000 shadow areas but closing SMRAM gt Restore CPUID value back into register Give control to BIOS POST ExecutePOSTKernel See POST Code Checkpoints section of document for more information 61 SE7221BK1 E Technical Product Specification 9
86. main outputs must be within regulation of each 50 msec other within this time T vout_off All main outputs must leave regulation within this 400 msec time e The 5VSB output voltage rise time shall be from 1 0ms to 25 0ms 69 V1 V2 V3 7221 1 Technical Product Specification lt Tvout_off l Tvout_rise 5 Tvout_on Figure 8 Output Voltage Timing Table 81 Turn On Off Timing Item Description MIN MAX UNITS Tsb on delay Delay from AC being applied to 5VSB being within 1500 msec regulation T ac on delay Delay from AC being applied to all output voltages 2500 msec being within regulation Tvout holdup Time all output voltages stay within regulation after 21 msec loss of AC Tpwok holdup Delay from loss of AC to de assertion of PWOK 20 msec Tpson on delay Delay from PSON active to output voltages within 5 400 msec regulation limits T pson pwok Delay from PSON deactive to being de 50 msec asserted Tpwok on Delay from output voltages within regulation limits to 100 1000 msec PWOK asserted at turn on T pwok off Delay from PWOK de asserted to output voltages msec 3 3V 5V 12V 12V dropping out of regulation 1 200 limits Tpwok low Duration of PWOK being in the de asserted state 100 msec during an off on cycle using AC or the PSON signal Tsb vout Delay from 5VSB being in regulation to O Ps bein
87. matched same type and speed Use of identical memory parts is always the preferred method See Table 2 and Figure 2 on the following page for reference The system design is free to populate or not to populate any rank on either channel including either degenerate single channel case DIMM and memory configurations must adhere to the following DDR2 400 533 un buffered DDR2 DIMM modules DIMM organization x72 ECC or x 64 Non ECC Pin count 240 DIMM capacity 256 MB 512 MB 1 GB DIMMs Serial PD JEDEC Rev 2 0 Voltage options 1 8 V Interface 55112 7221 1 Technical Product Specification Table 2 Memory Bank Labels and DIMM Population Order DIMM Label Population Order 3 ji A 5 mm 8 2 J8J1 J8J2 J9J2 J9J1 DIMM 1A DIMM 2A DIMM 1B DIMM 2B Channel A Channel B Bank 1 Bank 2 Figure 2 Memory Bank Label Definition Table 3 summarizes the characteristics of dual and single channel configurations with and without the use of Dynamic Mode 8 Revision 1 3 SE7221BK1 E Technical Product Specification Table 3 Characteristics of Dual Single Channel Configuration with without Dynamic Mode Throughput Level Configuration Characteristics Highest Dual Channel with Dynamic Paging Mode All DIMMs matched Dual Channel without Dynamic Paging Mode DIMMs matched from Channel A to Channel B DIMM
88. n unspecified fatal error that was detected 2 Processor error System halted because a fatal error related to a processor was detected 3 Memory error System halted because a fatal error related to the memory was detected 4 Motherboard error System halted because a fatal error related to the system motherboard hardware was detected 56 Revision 1 3 7221 1 Technical Product Specification Table 68 BIOS Recovery Beep Codes Beeps Error Message POST Progress Code Description 1 Recovery Started E9h Start of recovery process 2 Recovery Boot Error Flashing series of POST Unable to boot to floppy ATAPI or ATAPI codes EFh FAh FBh CD ROM Recovery process will retry F4h FCh FDh FFh Series of long Recovery Failed FDh Unable to process valid BIOS recovery low pitched images BIOS already passed control to single beeps operating system and flash utility 2 long high Recovery Complete FFh BIOS recovery succeeded ready for power pitched beeps down reboot 9 7 2 BIOS Event Log The BIOS will output the current boot progress codes on the video screen Progress codes are 32 bit quantities plus optional data The 32 bit numbers include Class subclass and Operation information Class and subclass point to the type of the hardware that is being initialized where as the Operation field represents the specific initialization activity Based upon the data bit a
89. nabled Disable trigger for system sensor events inside Applicable for all Disabled BMC BMCs 9 5 6 1 System management sub menu selections Table 63 BIOS Setup System Management Sub menu Selections Feature Options HepTet Description Chassis Serial Number Field contents varies N A BIOS Version BIOS ID string excluding the N A build time and date BMC Firmware Revision Field contents varies BMC Device Revision Field contents varies 49 PIA Revision N A SDR Revision N A 9 5 6 2 7221 1 Technical Product Specification N A Field contents varies N A Field contents varies Serial Console features sub menu selections Table 64 BIOS Setup Serial Console Features Sub menu Selections Description If enabled BIOS uses the specified serial port to redirect the console to a remote ANSI terminal Enabling this option disables Quiet Boot BIOS Redirection Port Baud Rate Flow Control Terminal Type Disabled Serial 1 Serial 2 No Flow Control CTS RTS XON XOFF CTS RTS CD PC ANSI VT100 VT UTF8 If enabled it will use the Flow control selected CTS RTS Hardware XON XOFF Software CTS RTS CD Hardware Carrier Detect for modem use VT100 selection only works for English as the selected language VT UTF8 uses Unicode PC ANSI is the standard PC type terminal 9 5 6 3 Event Log configuration
90. nd capability with the following conditions and exceptions e These input transients must not cause any out of regulation conditions such as overshoot and undershoot nor must it cause any nuisance trips of any of the power supply protection circuits e The surge withstand test must not produce damage to the power supply e The supply must meet surge withstand test conditions under maximum and minimum DC output load conditions 11 Absolute Maximum Ratings Operating the board at conditions beyond those shown in the following table may cause permanent damage to the system The table is provided for stress testing purposes only Exposure to absolute maximum rating conditions for extended periods may affect system reliability 72 1 3 7221 1 Technical Product Specification Table 85 Absolute Maximum Ratings Operating Temperature 5 C to 50 C Storage Temperature 55 C to 150 G Voltage on any signal with respect to ground 0 3 V to Vdd 0 3V 7 3 3 V Supply Voltage with Respect to ground 0 3 V to 9 63 V 5 V Supply Voltage with Respect to ground 0 3 V to 5 5 V Notes 1 Chassis design must provide proper airflow to avoid exceeding the processor maximum case temperature 2 VDD means supply voltage for the device 11 1 Mean Time Between Failures MTBF Test Results This section provides results of MTBF testing done by a 3 party testing facility MTBF is a standard measure for the reliab
91. ne Beep to indicate end of POST No beep if silent boot is enabled Off POST completed Passing control to INT 19h boot loader next gt gt gt gt D Di D D gt gt gt 67 SE7221BK1 E Technical Product Specification 10 Power Information 10 1 Intel amp Server Board SE7221BK1 E Power Budget The following table shows the power consumed on each supply line for the SE7221BK1 E baseboard that is configured with one processor 128W max This configuration includes four 1 GB DDR2 DIMMs stacked burst at 70 max The numbers provided in the table should be used for reference purposes only Different hardware configurations will produce different numbers The numbers in the table reflect a common usage model operating at a higher than average stress levels Table 78 The Board Power Budget Power Supply Rail Voltages Units Watts AMPS FUNCTIONAL 3 3 5 12 12V 5VSB UNIT VRM BASEBOARD INPUT 290 73W 6 26W 8 47W 6 38W 9 28W 0 05W 1 67 TOTALS BASEBOARD 5096 32 02W DISCRETE TOTALS BASEBOARD Efficiency 41 90W CONVERTERS BASEBOARD 246 80W 1 52 6 38 0 05 CONFIG TOTATLS SYSTEM 45 12W 2 40 2 76 COMPONENTS SYSTEM TOTALS 85W 10 87 88 3 3v 5v combined power Power Supply 300W 12V 12V Requirements VRM 1U r L 3 3V 5V m m 2Amin m combined power 12 12 20 68 Revision 1 3
92. ng command at the command prompt split File Name To Be Split New File File Size in For Example C split AMIBOOT ROM AMIBOOT 1024 2 The above command will create the files of sizes 1MB each 1024 KB with names AMIBOOT 000 001 and so on depending upon the AMIBOOT ROM file size 3 Load the first disk AMIBOOT 000 Revision 1 3 7221 1 Technical Product Specification 4 After reading the file it increments the file extension and then searches for 001 in the same floppy 5 If doesn t find the file in the floppy it will beep for once 1sec and search again 6 If it finds the first file and if it needs more files it will increment the file extension and searches again for AMIBOOT 002 this time it beeps 2 times each beep 1sec long and with 0 5sec gap 7 This continues until the total file size read is equal to the ROM image size Summary of Beep codes Beep Code List This uses the standard beep codes used by AMI Core8 for Recovery with some additional codes They are each beep is 1sec long with 0 5sec gap 1 1 long beep Insert for AMIBOOT 001 File 2 2 long beeps Insert for AMIBOOT 002 File 3 long beeps Insert for AMIBOOT 003 File Limitations 1 Maximum Files supported 1000 files AMIBOOT 000 to AMIBOOT 999 e Manually Recovering the BIOS A BIOS recovery can also be manually initiated This option would be used only when the BIOS is corrupt but the ROM chec
93. o LM96000 sensors Fan Monitor and Control FMC One PWM based fan controls Software or local temperature feedback control Chassis intrusion detection 5 Subsystem 51 PCI Subsystem The primary buses for the SE7221BK1 E are independent PCI bus segments 4 independent segments with SE7221BK1LX sku with PCI PCI E two PCI X buses The PCI buses comply with the Local Bus Specification Hev 2 3 The P32 A bus segment is directed through the ICH6R The P32 B and P64 C bus segment are independently configured to PXH that is through ICH6R by PCI Express x 4 interface The PCI E x8 bus is directed through the GMCH The table below lists the characteristics of the three PCI bus segments Table 5 PCI Bus Segment Characteristics Segment Voiage With Speed Type PONO Card Sot Sot PCI X 66 100MHz P64 C Slot 4 Slot 5 Slot 6 through riser POETE 5 1 1 P32 A 32 bit 33 MHz PCI Subsystem All 32 bit 33 MHz PCI I O for the board is directed through the ICH6R The 32 bit 33 MHz PCI segment created by the ICH6R is known as the P32 A segment The P32 A segment supports the following embedded devices and connectors 10 100 1000 T Network Interface Controller Intel 82541Pl Fast Ethernet Controller 5 1 1 1 Device IDs IDSEL Each device under the PCI hub bridge has its IDSEL signal connected to one bit of AD 31 16 which acts as a chip s
94. ogram NVRAM Destroy System CMOS lr registry path to store result of operation only for Windows version Program non critical block only 5 leave signature in BIOS silent execution h print help 9 6 2 Flash Architecture and Flash Update Utility The flash ROM contains system initialization routines the BIOS Setup Utility and runtime support routines The exact layout is subject to change as determined by Intel A 64 KB user block is available for user ROM code or custom logos The flash ROM also contains initialization code in compressed form for on board peripherals like SCSI NIC and video controllers The flash ROM also contains support for the Rolling single boot BIOS update feature The complete ROM is visible starting at physical address 4 GB minus the size of the flash ROM device The Flash Memory Update utility loads the BIOS image minus the recovery block to the secondary flash partition and notifies the BIOS that this image should be used on the next system re boot Because of shadowing none of the flash blocks are visible at the aliased addresses below 1 MB 9 6 3 Rolling BIOS and On line updates The Online Update nomenclature refers to the ability to update the BIOS while the server is online in operation as opposed to having to put the server out of operation while doing a BIOS update The Rolling BIOS nomenclature refers to the capability for having two copies of BIOS viz the one in use and the oth
95. onfiguration sub menu 37 BIOS Setup IDE Configuration Menu 38 BIOS Setup IDE Device Configuration Sub menu Selections 39 BIOS Setup Floppy Configuration Sub menu Selections 40 BIOS Setup Super I O Configuration 5 40 BIOS Setup USB Configuration Sub menu Selections 41 BIOS Setup USB Mass Storage Device Configuration Sub menu Selections 41 BIOS Setup PCI Configuration Sub menu Selections 42 BIOS Setup Memory Configuration Sub menu 43 BIOS Setup Boot Menu 2 2 1 4 nennen nnne 43 BIOS Setup Boot Settings Configuration Sub menu Selections 44 BIOS Setup Boot Device Priority Sub menu Selections 44 BIOS Setup Hard Disk Drive Sub Menu 44 BIOS Setup Removable Drives Sub menu 45 BIOS Setup CDROM Drives Sub menu Selections 45 BIOS Setup CDROM Drives Sub menu Selections
96. r socket supporting 800MHz FSB Intel Pentium 4 processor Processor host bus AGTL support circuitry Table 1 Processor Support Matrix Processor Family Package Type Front Side Bus LGA775 3 0 3 8 GHz 2MB L2 800MHz Pentium amp 4 LGA775 2 8 3 8 GHz 1MB L2 800MHz Celeron D LGA775 2 26 2 93 GHz 256K L2 533MHz Note The Pentium 4 Processor Extreme Edition IS NOT supported for use with the Intel Server Board SE7221BK1 E The board is designed to provide up to 120A of processor current Processors with higher current requirements are not supported For a complete list of all supported processors please visit the Intel Server Board SE7221BK1 E support site located at the following URL http support intel com support motherboards server sb CS 012690 htm In addition to the circuitry described above the processor subsystem contains the following Reset configuration logic Server management registers and sensors 3 1 5 Interrupts and APIC Interrupt generation and notification to the processor is done by the APICs in the ICH6R using messages on the front side bus 3 2 Memory Subsystem The baseboard supports up to four DIMM slots for a maximum memory capacity of 4 GB The DIMM organization is x72 which includes eight ECC check bits The memory interface runs at 400 533MT s The memory controller supports memory scrubbing single bit error correction and multiple bit error detection and Intel amp x4 SDDC support w
97. rap processor for POST Q e Enumerate and set up application processors Q Re enable cache for boot strap processor Early CPU Init Exit Initializes the 8042 compatible Key Board Controller o gt Detects the presence of PS 2 mouse N Detects the presence of Keyboard in KBC port Testing and initialization of different Input Devices Also update the Kernel Variables Traps the INTO9h vector so that the POST INTO9h handler gets control for IRQ1 Uncompress all available language BIOS logo and Silent logo modules Early POST initialization of chipset registers AR Uncompress and initialize any platform specific BIOS modules Initialize System Management Interrupt m gt Initializes different devices through DIM See DIM Code Checkpoints section of document for more information C Initializes different devices Detects and initializes the video adapter installed in the system that have optional ROMs Initializes all the output devices Allocate memory for ADM module and uncompress it Give control to ADM module for initialization Initialize language and font modules for ADM Activate ADM module Initializes the silent boot module Set the window for displaying text information Displaying sign on message CPU information setup key message and any OEM specific information m l Initializes different devices through DI
98. ring BIOS oe ust 36 9 5 1 Main MOT reden payan e er redeo 36 9 5 2 Advanced MENU a er eR 37 9 5 3 510168 MON 0 E DE ERR 43 9 54 Chipset oer a ra tus 45 9 5 5 Ia Dee SUME 47 SE7221BK1 E Technical Product Specification 9 5 6 aska m AE A AT ne Mt EE 48 9 5 7 per E E 51 9 6 Upgrading the BIOS oce 51 9 6 1 Preparing for the Upgrade rfe 51 9 6 2 Flash Architecture and Flash Update Ultility sss 53 9 6 3 Rolling BIOS and On line 53 9 7 Error Handling and Reporting redeem a b eme ote Ra ronds 56 9 7 1 POST Error etit el eh UP a Foe e Eu ER Eth 56 9 7 2 BIOS Event 22 52 48 55 rn ttes ve abd aps 57 9 7 3 POST Progress Codes and Messages 58 Table 70 POST Code Checkpoints 58 Table 71 Bootblock Initialization Code Checkpoints 61 Tabl
99. ry interrupt controller standard PC configuration A single interrupt signal is presented to the processors to which only one processor will respond for servicing The ICH6R contains configuration registers that define which interrupt source logically maps to I O APIC INTx pins The ICH6 handles both PCI and IRQ interrupts The ICH6R translates these to the APIC bus The numbers in the table below indicate the ICH6R PCI interrupt input pin to which the associated device interrupt INTA INTB INTC INTD INTE INTF INTG INTH for PCI bus and PXIRQO PXIRQ1 PXIRQ2 PXIRQ3 for PCI X bus is connected The ICH6R I O APIC exists on the I O APIC bus with the processors Table 13 AND PCI X Interrupt Routing Sharing INTA INT B INT C INTD Intel 82541 PIRQC PCI Slot 1 PCI 32b 33M PROF PIRQH PCI Slot 4 64b 66M Slot 6 nes PXIRQ1 PXIRQ2 64bit 1 0OOMHZz Riser SE7221BK1LX sku only POI Sio 5 64b 66M 5 4 2 APIC Interrupt Routing For mode the baseboard interrupt architecture incorporates three Intel I O APIC devices to manage and broadcast interrupts to local APICs in each processor The Intel I O APICs monitor each interrupt on each PCI device including PCI slots in addition to the ISA compatibility interrupts IRQ 0 15 When an interrupt occurs a message corresponding to the interrupt is sent across a three wire serial interface to the local APICs The APIC bus minimizes interrupt
100. s not matched within channels Single Channel with Dynamic Paging Mode Single DIMM or DIMMs matched with a channel Lowest Single Channel without Dynamic Paging DIMMs not matched Mode 4 The intel E7221 Chipset Intel amp Server Board SE7221BK1 E is designed around the Intel amp E7221 chipset The chipset provides an integrated 1 bridge and memory controller and a flexible subsystem core PCI Express The chipset consists of three primary components GMCH Graphics Memory Control Hub The GMCH accepts access requests from the host processor bus and directs those accesses to memory or to one of the PCI buses The GMCH monitors the host bus examining addresses for each request Accesses may be directed to a memory request queue for subsequent forwarding to the memory subsystem or to an outbound request queue for subsequent forwarding to one of the PCI buses The GMCH also accepts inbound requests from the ICH6R The GMCH is responsible for generating the appropriate controls to control data transfer to and from memory The Intel amp E7221 GMCH comes with an integrated high performance graphics media accelerator Intel amp GMA 900 and supports one x8 port configuration PCI E interface Maximum theoretical peak bandwidth on each x8 PCI Express interface of 2 5 GB s in each direction simultaneously for 5 GB s per port ICH6R I O Controller Hub The ICH6R controller has several components It
101. s to minutes in the time item in the main menu Change Value The minus key on the keypad is used to change the value of the current item to the previous value This key scrolls through the values in the associated pick list without displaying the full list Change Value The plus key on the keypad is used to change the value of the current menu item to the next value This key scrolls through the values in the associated pick list without displaying the full list On 106 key Japanese keyboards the plus key has a different scan code than the plus key on the other keyboard but will have the same effect Discard Changes Pressing F7 causes the following message to appear Discard Changes OK Cancel If OK is selected and the Enter key is pressed all changes are not saved and setup is exited If Cancel is selected and the Enter key is pressed the ESC key is pressed the user is returned to where they were before F7 was pressed without affecting any existing values Setup Defaults Pressing F9 causes the following to appear Load Setup Defaults OK Cancel If OK is selected and the Enter key is pressed all setup fields are set to their default values If Cancel is selected and the Enter key is pressed or if the ESC key is pressed the user is returned to where they were before F9 was pressed without affecting any existing field values 35 SE7221BK1 E Technical Product Specification Save Changes and Pressing F10
102. sabled Enabled 9 5 6 Server menu Period of key PS 2 mouse inactivity specified for Secure Mode to activate A password is required for Secure Mode to function Has no effect unless at least one password is enabled Key assigned to invoke the secure mode feature Cannot be enabled unless at least one password is enabled Can be disabled by entering a new key followed by a backspace or by entering delete When enabled allows the host system to complete the boot process without a password The keyboard will remain locked until a password is entered A password is required to boot from diskette Disables the Power Switch and the Reset Switch when Secure mode is activated A password is required to unlock the system This cannot be enabled unless at least one password is enabled This option is only present if the system includes an embedded video controller Enable disable NMI control through mBMC for the front panel NMI button This node is grayed out if a password is not installed This node is grayed out if a password is not installed This node is grayed out if a password is not installed This node is grayed out if a password is not installed Password is not required for this option Table 62 BIOS Setup Server Menu Selections Feature System management Serial Console Features Help Text Selects submenu Event Log configuration 48 Options Configures event logging Se
103. support a maximum of 4 GB of DDR2 memory using 1 GB DIMMs This configuration needs external registers for buffering the memory address and control signals The four chip selects are registered inside the GMCH and need no external registers for chip selects The memory interface runs at 400 533MT s The memory interface supports a 72 bit wide memory array It uses seventeen address lines BA 2 0 and MA 13 0 and supports 256 Mb 512 Mb 1 Gb DRAM densities The DDR DIMM interface supports memory scrubbing single bit error correction and multiple bit error detection and Intel x4 SDDC with x4 DIMMs 4 1 1 1 The DDR2 interface supports up to 4 GB of main memory and supports single and double density DIMMs The DDR2 can be any industry standard DDR2 The following table shows the DDR2 DIMM technology supported DDR2 Configurations Table 4 Supported DDR2 modules DDR2 400 and DDR2 533 Un buffered SDRAM Module Matrix DIMM DIMM SDRAM SDRAM SDRAM Address bits Capacity Organization Density Organization Devices rows Banks rows Banks column 256MB 32M x 72 256Mbit 32M x 8 9 4 13 2 10 512MB 64M x 72 256Mbit 32M x 8 18 2 4 13 2 10 512MB 64M x 72 512Mbit 64M x 8 9 1 4 14 2 10 1GB 128M x 72 512Mbit 64M x 8 18 2 4 14 2 10 1GB 128M x 72 1Gbit 128M x 8 9 1 8 14 3 10 4 1 2 Graphics Memory Controller Hub GMCH The GMCH is a 1210 ball FC BGA device and uses the proven components of previous g
104. system will boot with no intervention if possible Displays Press F2 to run Setup in POST Enabled DORT y Enabled binaries 9 5 3 2 Boot device priority sub menu selections Table 53 BIOS Setup Boot Device Priority Sub menu Selections Feature Options Help Text 1st Boot Device Varies Specifies the boot sequence from the Number of entries will vary based on available devices system configuration A device enclosed in parenthesis has been disabled in the corresponding type menu nth Boot Device Varies Specifies the boot sequence from the available devices A device enclosed in parenthesis has been disabled in the corresponding type menu 9 5 3 2 1 Hard disk drive sub menu selections Table 54 BIOS Setup Hard Disk Drive Sub Menu Selections Feature Options Help Text Specifies the boot sequence from the available Varies based on system configuration devices Specifies the boot sequence from the available Varies based on system configuration devices 44 Revision 1 3 7221 1 Technical Product Specification 9 5 3 2 2 Removable drive sub menu selections Table 55 BIOS Setup Removable Drives Sub menu Selections Feature Options Help Text Specifies the boot sequence from the available Varies based on system configuration devices Specifies the boot sequence from the available Varies based on system configuration devices 9 5 3 2 3 ATAPI CD
105. t for an unformatted diskette type format a s or for a diskette that has already been formatted type SyS a 4 Press Enters 9 6 1 4 Flash Update Utility The BIOS flash utility suite is compatible with DOS WIN NT 4 0 2000 XP and LINUX operating environments The afuXXX AMI Firmware Update Utilities are required for BIOS updates 1 In DOS 1 The flash bootable disk must have ROM image and afudos 2 Enter in DOS 3 Run AFUDOS i lt ROM filename n p b n c 2 In WIN NT 4 0 2000 XP 1 The flash disk must have ROM image AMIFLDRV SYS and AFUWIN EXE 2 Enter in WIN NT 4 0 2000 3 Run command AFUWIN i lt ROM filename n p b n c 3 In LINUX 1 The flash disk must have ROM image and AFULNX 2 Enter in linux and include floppy device 3 Run command afulnx filename n p b n c 4 In EFI Shell 1 The flash disk must have ROM image and AFUEFI 2 Boot to EFI Shell with the flash disk 3 Doa map r to obtain the file system on the disk 4 Change drive to the flash disk E g if the flash disk is 150 type 150 at the prompt 52 Revision 1 3 7221 1 Technical Product Specification Run command afuefi n p b n c ROM filename to perform the update The afuXXX utilities format and usage afuXXX i lt ROM filename n p b n c r registry path s k q h don t check ROM ID pbnc b Program Boot Block n Pr
106. t controller Each function within the ICH6R has its own set of configuration registers Once configured each appears to the system as a distinct hardware controller sharing the same PCI bus interface The primary role of the ICH6R is to provide the gateway to all PC compatible I O devices and features The board uses the following the ICH6R features PCI 32 bit 33MHz interface LPC bus interface PCI Express x4 DMI Direct Media Interface IDE interface with Ultra ATA 100 66 33 capability Integrated Serial ATA Host controller Universal Serial Bus USB 2 0 interface PC compatible timer counter and DMA controllers APIC and 82C59 interrupt controller Power management System RTC Supports Smbus 2 0 Specification General purpose GPIO The following are the descriptions of how each supported feature is used for ICH6R on the board 4 1 3 1 PCI Bus P32 A Subsystem The ICH6R provides a legacy 32 bit PCI subsystem and acts as the central resource on this PCI interface P32 A supports the following embedded devices and connectors One Intel 82541 network controller 11 SE7221BK1 E Technical Product Specification slots capable of supporting full length legacy PCI add in cards operating at 33 MHz 4 1 3 2 PCI Express X4 Subsystem The ICH6R supports one x4 lane PCI Express interface that can also be configured as a single or x4 lane port The PCI Express interfac
107. ter 2 Server Board Overview Chapter 3 Functional Architecture Chapter 4 The Intel amp E7221 Chipset Chapter 5 I O Subsystem Chapter ACPI Implementation Chapter 7 Connectors Chapter 8 Configuration Jumpers Chapter 9 BIOS Setup Utility Chapter 10 Absolute Maximum Ratings Chapter 11 Power Information Chapter 12 Hardware Monitoring Chapter 13 Product Regulatory Compliance Chapter 14 Glossary 2 2 1 SE7221BK1 E Technical Product Specification Server Board Overview SE7221BK1 E Feature Set The Intel amp Server Board SE7221BK1 E supports the following feature set Processor and Front Side Bus FSB support Supports single Intel Pentium 4 and Celeron processors an LGA775 package Capable of 800 MT s on system bus Supports Hyper Threading Technology Supports Intel Extended Memory System 64 Technology EM64T Intel E7221 chipset components GMCH integrated graphics controller in GMCH component Intel GMA 900 ICH6R I O controller PXH PCI X Hub 12 deep In Order Queue Memory System 4 DIMM sockets supporting 400 533 DDR2 DIMMs Data bandwidth per channel of 4 2GB s or 8 5GB s in dual channel when using DDR2 533MHz Support for up to two DDR2 channels for a total of 4 DIMMs 2 DIMMs Channel providing up to 4GB max memory capacity Support for 256MB 512MB 1GB and 2GB DRAM sizes Supports Performance Acceleration Technology PAT Subsystem Four in
108. terface for 1000BASE T 100BASE TX and 10BASE T applications 802 3 802 3u and 802 3ab The controller is capable of transmitting and receiving data at rates of 1000 Mbps 100 Mbps or 10 Mbps In addition to managing MAC and PHY layer functions the controller provides a 32 bit wide direct Peripheral Component Interconnect PCI 2 3 compliant interface capable of operating at 33 or 66MHz 5 3 1 NIC Connector and Status LEDs The NICs drive two LEDs located on each network interface connector For the NIC 1 connector the green LED indicates network connection when on and Transmit Receive activity when blinking The yellow LED indicates 1000 Mbps operation when lit the green LED indicates 100 Mbps operation when lit and 10 Mbps when off 17 SE7221BK1 E Technical Product Specification For the NIC 2 connector SE7221BK1LX sku only the yellow LED indicates network connection when on and Transmit Receive activity when blinking The orange LED indicates 1000 Mbps operation when lit the green LED indicates 100 Mbps operation when lit and 10 Mbps when off 5 4 Interrupt Routing The board interrupt architecture accommodates both PC compatible PIC mode and APIC mode interrupts through use of the integrated I O APICs in the ICH6 5 4 1 Legacy Interrupt Routing For PC compatible mode the ICH6 provides two 82C59 compatible interrupt controllers The two controllers are cascaded with interrupt levels 8 15 entering on level 2 of the prima
109. total of three 3 pin jumper blocks that are used to configure several system recovery and update options The figure below shows the jumper pins and their functions The factory defaults are set to a protected mode for each function Three jumpers are stored on six pins during normal operation Please refer to below figure for the detail function 1 11 CMOS CLEAR 1 2 mBMC control default 2 3 Force erase PASSWORD CLEAR 5 6 Protect default 6 7 Erase RECOVERY BOOT 9 10 Normal BOOT Default 10 11 Recovery BOOT Figure 6 System Recovery and Update Jumpers J1F2 The following table describes each jumper option Table 38 System Recovery and Update Jumper Options Function Pin Pin Function Description CMOS CLEAR 1 2 MBMC control These three pins are connected to of 33 SE7221BK1 E Technical Product Specification 2 3 Force erase SUPER IO The system BIOS reads these PASSWORD CLEAR 5 6 Protect GPls status and decides whether or not to j related task The clear CMOS status 6 7 Erase is reflected to ICH6 Defaults are in bold RECOVERY BOOT 9 10 Normal BOOT 10 11 I Recovery BOOT 9 BIOS Setup Utility The BIOS Setup utility is provided to perform system configuration changes and to display current settings and environment information The BIOS Setup utility stores configuration settings in system non volatile storage Changes affected by BIO
110. upt Controller The ICH6R provides the functionality of two cascaded 82C59 with 15 interrupts handling Support processor system bus interrupt 4 1 3 7 APIC The integrates an APIC capability with 24 interrupts 4 1 3 8 Power Management One of the embedded functions of the ICH6R is a power management controller This is used to implement ACPI compliant power management features The baseboard does support sleep states 50 S1 S4 and 55 12 Revision 1 3 7221 1 Technical Product Specification 4 2 Super I O National Semiconductor PC87427Super IO device contains all of the necessary circuitry to control two serial ports one parallel port floppy disk PS 2 compatible keyboard and mouse and hardware monitor controller The baseboard implements the following features GPIOs Two serial ports Floppy Keyboard and mouse Local hardware monitoring Wake up control System Health Support 4 2 1 Serial Ports The board provides two serial ports an external serial port and an internal serial header The following sections provide details on the use of the serial ports 4 2 1 1 Serial A Serial A is a standard 089 interface located at the rear I O panel of the server board below the video connector Serial A is designated by as Serial A on the silkscreen The reference designator is J8A1 4 2 1 2 Serial B Serial B is an optional port accessed through a 9 pin internal header J1B1 A st
111. use 84FF System Event Log Full Warning 9 7 3 POST Progress Codes and Messages 9 7 3 1 POST Code Checkpoints Table 70 POST Code Checkpoints Checkpoint Description Disable NMI Parity video for EGA and DMA controllers Initialize BIOS POST Runtime data area Also initialize BIOS modules on POST entry and GPNV area Initialized CMOS as mentioned in the Kernel Variable wCMOSFlags Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK Verify CMOS checksum manually by reading storage area If the CMOS checksum is bad update CMOS with power on default values and clear passwords Initialize status register A Initializes data variables that are based on CMOS setup questions Initializes both the 8259 compatible PICs in the system 58 Revision 1 3 7221 1 Technical Product Specification Checkpoint Description Initializes the interrupt controlling hardware generally PIC and interrupt vector table Do R W test to CH 2 count reg Initialize 0 as system timer Install the POSTINT1Ch handler Enable IRQ 0 in PIC for system timer interrupt Traps INT1Ch vector to POSTINT1ChHandlerBlock Initializes the CPU The BAT test is being done on KBC Program the keyboard controller command byte is being done after Auto detection of KB MS using AMI KB 5 Early CPU Init Start Disable Cache Init Local APIC Set up boot strap processor Information e N Set up boot st
112. vailability to display Progress Code a progress code can be customized to fit the data width The higher the data bit higher the granularity of information which could send on the progress port The progress codes may be reported by system BIOS or option ROMs The Response section in following table is divided in 3 different types e Warning The message is displayed on screen and error is logged SEL System will continue booting with degraded state User may want to replace erroneous unit Pause The message is displayed on screen and user input is required to continue User can take immediate corrective action or can choose to continue booting Halt System cannot boot unless error is resolved User needs to replace faulty part and restart the system Table 69 POST Error Messages and Handling Error Code Error Message Response 100 Timer Error Warning 103 CMOS Battery Low Warning 104 CMOS Settings Wrong Warning 105 CMOS Checksum Bad Warning 10B CMOS memory size different Warning 112 CMOS time not set Warning 140 Refresh timer test failed Halt 141 Display memory test failed Warning 142 CMOS Display Type Wrong Pause 147 Unknown BIOS error Error code 147 this is really a Halt PMM MEM ALLOC ERR 148 Password check failed Halt 149 Unknown BIOS error Error code 149 this is really SEGMENT REG Halt 14A Unknown BIOS error Error code 144A this is really ADM MODULE ERR Warning
113. ware Monitoring 73 12 1 Monitored Components les atas 73 12 2 Fan Speed m 75 12 3 Chassis ie ete 76 13 Product Regulatory 76 13 1 1 Product Safety Compliance eae 76 vi Revision 1 3 7221 1 Technical Product Specification 13 1 2 13 1 3 13 2 13 2 1 13 2 2 13 2 3 13 2 4 13 2 5 13 2 6 13 3 13 4 13 5 Glossary Product EMC Compliance caus 76 Product Regulatory Compliance 76 Electromagnetic Compatibility Notices 77 POG T 77 INDUSTRY CANADA ICES 003 78 Europe CE Declaration of Conformity 2 1000 78 Taiwan Declaration of Conformity ria ce 78 Korean RRL Compliance a 78 Australia New 2
114. when manual configuration of DRAM parameters are used DRAM RAS to 2 DRAM Clocks Select RAS to CAS delay Greyed when DRAM timing CAS Delay 3 DRAM Clocks programming are done using SPD RAS to CAS delay setting will be 4 DRAM Clocks programmed into DRAM timing 5 DRAM Clocks register when manual setting is selected DRAM RAS 2 DRAM Clocks Select RAS precharge Greyed when DRAM timing Precharge 3 DRAM Clocks programming are done using SPD RAS precharge setting will be 4 DRAM Clocks programmed into DRAM timing 5 DRAM Clocks register when manual setting is selected DRAM RAS 4 DRAM Clocks Select RAS Activate to precharge Greyed when DRAM timing Activate to 5 DRAM Clocks programming are done using SPD Precharge RAS activate to precharge setting 6 DRAM Clocks will be programmed into DRAM 7 DRAM Clocks timing register when manual 8 DRAM Clocks setting is selected 9 DRAM Clocks 10 DRAM Clocks 11 DRAM Clocks 12 DRAM Clocks 13 DRAM Clocks 14 DRAM Clocks 15 DRAM Clocks Boots Grapchics IGD Select which graphics controller to IGD Integrated Video has more Adapter priority PCI IGD be used as primary boot device priority PCI IGD Offboard video has more priority Internal Graphics Disabled Select the amount of memory used Enabled Disable internal graphics Mode Select Enabled 1MB by Internal Graphics device and Select the sieze of memory to Enabled 8MB be used 9 5 4 2 South Bridge Chipset Configuration Table 59
115. ystem Fan 3 optional BB HDD LED Header G System Fan 1 optional R Main Power Connector CC HSBP Header H Back Panel I O Connectors 5 Floppy Connector DD Battery System Fan 2 optional T IDE Connector EE Serial B Header J U K V CPU Socket SATA 3 Connector Revision 1 3 7221 1 Technical Product Specification 3 Functional Architecture This chapter provides a high level description of the functionality distributed between the architectural blocks of the Intel Server Board SE7221BK1 E 3 1 Processor Subsystem The Intel Server Board SE7221BK1 E supports Intel Pentium 4 and Celeron D processors in the 775 land package which is a follow on to Pentium 4 and Celeron amp D processors in the 478 pin package with enhancements to the Intel NetBurst amp micro architecture Intel Pentium 4 and Celeron D processors built on 90nm process technology in the 775 land package utilize Flip Chip Land Grid Array FC LGA4 package technology and plug into a 775 land LGA socket referred to as the LGA775 socket Pentium 4 and Celeron D processors in the 775 land package like their predecessors in the 478 pin package are based on the same Intel amp 32 bit micro architecture and maintain the tradition of compatibility with IA 32 software Specific models of the Pentium 4 Processor in the LGA775 package support Intel EM64T Extended Memory 64 Technology for 64bit native mode operation with 64bit op

Intel SE7221BK1-E User's Manual

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