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Intel MCS-4 User's Manual

1. CEOE E E E F E EE EE E E lt FIRST LINE NUMBER OF LINE t S S S S S S lt 8 9 10 11 12 13 14 15 xM18118345678 9 10 11 12 13 14 D 28 6 amp a e e sS S S S e S n G S sco S s S S lt S S S S S S ul z lt z gt gt rx o Eo 9 Z J 5 gt OZ lt 29 zo C o ul 2 uz uz gt c 50 1 13 s S S Se S s o S s S _ 495599999 9o 9 o9t 9979 e S S S S S S o o S 4 _ 9 S S S S S amp S Q S S lt S S S S S S n S S S S O S S S S S o o S S o 9 S c S S S S in n lt lt Q 9 e o e e S S 9 S Q O S r
2. The 4009 then transfers the eight bit instruction from program memory to the 4004 four bits at a time at M1 and M2 The command signal sent by the CPU activates the 4009 and initiates this transfer When the CPU executes an SRC Send Register Control instruction the 4008 responds by storing the 1 address in its eight bit SRC register The content of this SRC register is always transferred to the address lines AO through A7 and the chip select lines CO through C3 at X1 time The appropriate 1 port is then selected by decoding the chip select lines The IN and OUT lines of the 4009 indicate whether an input or output opera tion will occur The 4009 is primarily an instruction and 1 transfer de vice When the CPU executes an RDR Read ROM Port instruction the 4009 will send an input strobe pin 9 to enable the selected input port It also enables 1 input buffers to transfer the input data from the 1 bus to the data bus When the 4009 interprets a WRR Write ROM Port instruction it transfers output data from the CPU to the 1 bus and sends an output strobe pin 10 to enable the selected output port A formerly undefined instruction is now used in conjunction with the 4008 4009 to wr
3. S amp n S amp LEN s s gt S 9 Q O QW ee esse HV 28 28 8 8 n es u 5 Aen SeSSSSESHSSSTN CEES Figure 2 Memory Dump Input 6 00101008 2 00101001 3411101010 2011841 4218113008 1111 0000 600 x 2 9114 10 11 0 BPPNPNPPPF 41BNPNNPPPPF 81BNPNNPPPPF 123 11 BPPPPPPPNF S BPNNPNPPPF 9 13 BPPPPPPPPF 9 14 180 2 61BPPNPNPPNF 18 14 BPPPPPPPPF Figure 3 Miscellaneous Directives 151 3sBNNNPNPNPF 73BNNNPNPNPF 11 8 BPPPPPPPPF 15 3 BPPPPPPPPF BPNNPNPNNF F 0 FOUR BIT AND ROUTINE START FIM 0 4 LOAD ROM PORT ADDRESS 2 SRC 4P 7 SEND ROM PORT ADDRESS 3 RDR 4 READ INPUT 4 7 TO REGISTER 5 INC 8 4 LOAD ROM PORT 1 ADDRESS 6 5 7 SEND PORT ADDRESS 7 RDR READ INPUT B 8 XCH 1 TO REGISTER 1 9 JMS AND 7 EXECUTE AND 11 2 7 LOAD RESULT C 12 WMP STORE AT MEMORY PORT 13 JUN START 7 RESTART 15 NOP 16 104 104 SUBROUTINE 1943 AND CLB 7 CLEAR ACCUMULATOR AND CARRY 105 XCH 2 CLEAR REGISTER 2 106 LDM 4 LOAD LOOP COUNT LC 107 XCH 9 LOAD LC TO REGISTER 108 RAR 7 ROTATE
4. 2 5 uam 1 0 2 0 4001 2 VoL 1 0 OUTPUT LINES Vss 12 7 5 Vss 6 5 OUTPUT LOW VOLTAGE 4003 VoL3 OUTPUT LOW VOLTAGE 11 Vgs 7 5 Vgs 6 5 v 4001 2 RESISTANCE 12 18 LINES O LEVEL 4003 PARALLEL OUT PINS OUTPUT 400 750 RESISTANCE 0 LEVEL 4003 RoH4 SERIAL OUT OUTPUT 650 1200 RESISTANCE 0 LEVEL 1 Typical values are for TA 25 and Nominal Supply Voltages 3 For T2L compatibility on the I O lines the supply voltages should be 2 If non inverting input option is used Vi 6 5 Volts maximum Vpp 10V 5 Vss 5V 5 103 Typical D C Characteristics POWER SUPPLY CURRENT POWER SUPPLY CURRENT VS TEMPERATURE VS TEMPERATURE 4001 4002 t pw topi 400 nsec t p2 150 nsec t pw top1 400 nsec t p2 150 nsec POWER SUPPLY CURRENT Ipp POWER SUPPLY CURRENT mA 1602 AMBIENT TEMPERATURE C AMBIENT TEMPERATURE C POWER SUPPLY CURRENT POWER SUPPLY CURRENT VS TEMPERATURE VS TEMPERATURE 4003 4004 topw tapi 400 nsec top2 150 nsec POWER SUPPLY CURRENT mA Ipp3 POWER SUPPLY CURRENT mA Ippa AMBIENT TEMPERATURE C AMBIENT TEMPERATURE C OUTPUT CURRENT VS OUTPUT CURRENT VS OUTPUT VOLTAGE OUTPUT VOLTAGE 4001 4002 4003 Dp 1900 Vpp 15 0V 6 t t 400 nsec OPW 5501 twi twp 8 usec t p2 150 nsec m Mere N 8 5 gt pa lt
5. 5Svac ai 2300 x lt SIM4 01 Ze x PROM SOCHET 3 Ao 2 t 1 42 2 A3 V R A2 2 22 4 19 PRINTER CONTROL Az 02 7 78 A6 TAPE CONTROL v N E 42 6 42 5 wan 42 4 77 7 4 2 amp S Dz 6 27 7 29 8 25 gt 26 227 20 h 19 ECHIP SELECT 73 PROGLAM 72 vec Vec vas 29 Voo 23 p 106 Nore de DIOS ALE L ED EXCEPT AS MMCATED 2 Met RESISTORS ELLEPI AS MCB4 10 Schematic CAUTION Permanent damage may result to MP7 03 board and PROM to be programmed if the DC POWER is turned OFF BEFORE the PRGM AC is turned off The SIM4 01 and MP7 03 should never be inserted into their respective sockets with either the DC or AC power applied APPLY DC POWER BEFORE AC POWER AND REMOVE AC POWER BEFORE DC POWER 123 M CB4 20 T he MCB4 20 is a completely assembled interconnect display and control switch assembly which eliminates all hand wiring as isociated with an MP7 03 SIM4 02 setup With the additions noted below it becomes a self contained system featuring the following 1 2 3 4 Automatic PROM Programming with SIM4 02 PROM set 0540 0541 0543 7 03 powe
6. DATA BUS 1 O LINES CAPACITANCE DATA BUS LINES CAPACITANCE DATA LINES FOR 4001 4002 4004 SET TIME VS OUTPUT CAPACITANCE amp SYNC FOR 4004 CM ROM 4004 380 nsec 400 nsec tapw 380 nsec 7 150 nsec 400 nsec 40 nsec 2 150 nsec 2 tag tog 40 nsec gt Vbo 15 0V ts OUTPUT CAPACITANCE pF OUTPUT CAPACITANCE pF 106 Absolute Maximum Ratings Ambient Temperature Under Bias to 70 COMMENT Storage Temperature 559C to 1509 Stresses above those listed under Absolute Maximum Ratings Input Voltages and Supply Voltage may cause permanent damage to the device This is a stress rating With Respect to Ves 40 5 to 20V only and functional operation of the device at these or any other condition above those indicated in the operational sections of this Power Dissipation specification is not implied 4008 4009 D C and Operating Characteristics 0 to 709C Vss Vpp 15v 5 1 1 400ns 1402 150ns unless otherwise specified Input Leakage Current 4008 9 10 uA Vin Vss 16V Pins 1 8 4008 Pins 1 8 11 13 15 4009 Average Supply Current 4008 s 20 T 25 C Unloaded 4009 30 mA lu Viu Input High Voltage 4008 9 Vss V 1 5 0 3 V LC Clock Input Low Voltage 4008 9 Vpp 12 5 Ving Input Low Voltage 4008 9 Vpp Except I O 2 I O Inpu
7. failure to program F stopped If a location in the ROM will not program a new ROM must be inserted in the Programmer The system must be reset before continuing If erasable ROMs are being used the faulty ROM should be erased and reprogrammed PROGRAM LISTING After the programming is complete the complete content of the ROM or any portion may be listed on the teletype A duplicated programming tape may also be made using the teletype tape punch To list the ROM type L list command XXX initial address YYY final address EXAMPLE 5 Typed L by 000 User 10 Listed 000 BPPPPPPPPF 001 002 003 BPPPPPPPPF by 004 005 BNNPNNPPPF 006 BNPNNPNPPF 007 BPNPNPPPPF System 008 BNPNPPNPPF 009 BNNNNPPPNF 010 BPPNPPPPNF listing complete Note that this is a listing of the ROM programmed in Example 1 The listing feature may also be used to verify that a 1701 or 1702 is completely erased If the PROM is completely erased P s will be listed in every location 1701 1702 ERASING PROCEDURE The 1701 and 1702 may be erased by exposure to high intensity short wave ultraviolet light at a wavelength of 2537 The recommended integrated dose i e UV intensity x exposure time is 6W sec cm Example of ultraviolet sources which can erase the 1702A in 10 to 20 minutes is the
8. 2nd word OPR 2 A2 A2 A2 Symbolic PH PL 2 gt Stack PL A2 A2 2 A2 Pg Description The address of the next instruction in sequence following JMS return address is saved in the push down stack Program control is transferred to the instruction located at the 12 bit address AsA3yA3A3A2A2A2A2A1A1A1A1 Execu tion of a return instruction BBL will cause the saved address to be pulled out of the stack therefore program control is transferred to the next sequential instruction after the last JMS The push down stack has 4 registers of them is used as the program counter therefore nesting of JMS can occur up to 3 levels EXAMPLE Stack Stack ws man received gt received ENS Program Counter Program Counter Return address 1 Stack Stack gs TUS received Return address 2 Return address 1 Stack Program Counter Return address 3 gt Return address 2 Return address 1 Return address 4 Return address 3 BBL Return Address 3 Return address 2 Return Address 2 ed The deepest return addr 27 JMS 2 received Mnemonic JCN Jump conditional lst word 0001 1 2 3 4 2nd word OPR OPA A2A2A2A2 AJAJAJA Symbolic If C1C2C3C4 is true A2A2A2A2 gt PM gt PL unchanged if 1 2 3 4 is false
9. A0540 A0541 A0543 Connect teletype to TTY socket Connect 5V DC 10V DC and 115 Vrms Depress RESET Set PROG AC to ON Set DATA ENABLE to DATA ENABLE Set PROM SELECTOR to 1601A 1701A Place teletype in ON LINE mode Depress RESET 10 Insert PROM 11 Place paper tape reader and set reader to START 12 Type in program command P and beginning and ending address O O N _ Refer to section XIII for a complete description of the MCS 4 micro computer controlled programming system The PROM is then automatically programmed and checked for correct content x PROGRAMMER BOARD d P NOTE 1 signals are defined with respect to negative logic at the dual in line 1 socket i e True n logic 1 GND False n logic 0 45V 2 1 TTL Load Drive 1 6mA 4V 8888865 EXPANSION 8822808 PORT LOGIC COMPATIBILITY ROM Input Port True TTL In ROM Output Port False TTL Out RAM Output Port False TTL Out ce 2 8 2222 ovu 3 3 2 Micro COMPUTER Connector BOARD TEST RESET PROG AC MCB4 10 Interconnect and Control Module Printed Circuit Board B 122 OUTPUT CHIP BIT NI 9 2 DATA ovr ENABLE N Q rar COM ACA T ATA IN o or year COMPLEMENT DATA OUT s lt w TE N N 9 x
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11. Py PL 2 Py Description If the designated condition code is true program control is transferred to the instruction located at the 8 bit address 2 2 2 AJAJAJA on the same page ROM where JCN is located If the condition is not true the next instruction in sequence after JCN is executed The condition bits are assigned as follows 0 Do not invert jump condition Cj 1 Invert jump condition C2 1 Jump if the accumulator content is zero 1 Jump if the carry link content is 1 1 Jump if test signal pin 10 on 4004 is zero Example 0001 0110 Jump if accumulator is zero or carry 1 Several conditions can be tested simutaneously The logic equation describing the condition for a jump is give below JUMP Cy ACC 0 CY 1 C3 TEST C4 ACC 0 CY 1 TEST C4 EXCEPTIONS If JCN is located on words 254 and 255 of a ROM page when JCN is executed and the condition 15 true program control is transferred to the 8 bit address on the next page where JCN is located f Eee Mnemonic ISZ Increment index register skip if zero 156 word OPR 0111 RRRR 2nd word OPR OPA Symbolic RRRR 1 if result 0 Py gt gt Py 2 if result 0 PH 2 2 2 2 gt 1 1 1 1 PL Description content of the designated inde
12. ROM DATA OUTPUT 5 EXPANSION OUTPUT OUTPUT ROM DATA OUTPUT 6 EXPANSION ROM DATA OUTPUT 7 EXPANSION OUTPUT ROM MIDDLE ADDRESS SELECT EXPANSION ROM LOWER ADDRESS SELECT EXPANSION ROM UPPER ADDRESS SELECT EXPANSION DATA BUS O TTL COMPATIBLE DATA BUS 1 TTL COMPATIBLE DATA BUS 2 TTL COMPATIBLE DATA BUS 3 TTL COMPATIBLE 76 XII SAMPLE SIXTEEN DIGIT DECIMAL ADDITION PROGRAM WITH KEYBOARD and PRINTER INTERFACE Intel ROM Program Number A0700 MCS 4 program has been developed to demonstrate both the control and arithmetic features of this microcomputer system This program adds a sixteen digit integer to the content of the accumulator and prints the new content of the accumulator The programmed ROM may be used with either the SIM4 01 or SIM4 02 prototyping system Input output capability is provided by an ASR 33 teletype The prototyping system and the teletype should be connected as shown in Section XIII The TTY keyboard interrogation arithmetic operation and TTY Printer output are all controlled by the CPU 4004 using this special decimal addition program To use this program 1 Insert the ROM in ROM position zero in the prototype system and reset the system including the accumulator to zero 2 Enter from one to sixteen integers from the TTY keyboard 3 If fewer than sixteen digits are entered depress the key 4 T
13. ae ZAM 8 e in cip 2082907 CHIP O bp OUTPUT 5 22 0 aava 2117 ouTPuT 5 SANA 3 265 24 J2 Jz 62 5 esr 7404 J 105 gt TTY IN zTTY PRINTER Q9 TO TTY W 2 63 442 12 243014 c 604 612 1 914 FACTORY SELECTED tta 5 6 2 289 zu arao lov seg cs PERDER 9 mhi 1 i 5 5 oct dc V 201 NTE OL TTY TRANSMITTER IARNA odd TTY RECEIVER READER 22 4 2 BANA 2 32 3 2149 J 613 R aia 3014 gz 1 50 P4 2401 ens Loz en Eoi 4 22 10 70 71 gt _ 7 ALL SIGNALS REFERENCED TO NEGATIVE 206 B 42 49 4 A 9 12 1318 22 25 ARE TIED To e 5v a Jt SRI s 5 wi 920 LC 2301 gt pemg u Fu pd jp 54 E 7404 5 LI i f 48 5 3 a den BENE gue 0 1 gsx am ER isi gt gt i D 1 mona DM Osu us eet 8 ej t 44 rx e i 4 a m fer 5 F 1 m se z z y j rot p p 2 1 eb 52 D m Y gt lt j 12 D m ALB E j 6 74H04 0 pda 4
14. ee E Oe 4002 0 4002 40 U TW TT ATT RAM MA CM RAM3 Figure 34 Timing Diagram for the MCS 4 Evaluation Kit Using the 4001 0009 97 4001 0009 MCS 4 EXERCISER PROGRAM ROM ADDRESS MNEMONIC COMMENTS 0 Check accumulator and carry 1 Check stack content 2 Loan pointer 4002 1 1 3 from 5 Jump to LD subroutine This sub 214 221 5 routine is used to mark the progress of the program by sending out a pattern on the output lines of 4002 1 1 6 Jump to CK IDX subroutine 7 Checks the content of all index register locations 8 Load FIN address 9 10 Jump to CK FIN subroutine 11 Loads all index register locations with the data stored in location 254 12 13 14 Loads all index register locations 15 with the data stored in location 255 16 17 18 Restore pointer 4002 1 1 19 20 21 Location 255 contains NOP program 22 counter is incremented to 0 23 This portion of the program is used 26 to check JMS and JUN instructions 27 and load the stack with a checkerboard 28 29 30 31 32 33 34 35 36 37 38 Reset marker outputs on 4002 1 1 41 42 Send pointer to 4002 1 0 16 tines 44 Go to next character 45 46 47 This portion of the program is 4 times 48 used to load a checkerboard into 49 4002 1 0 50 51 52 53 INC 0 to nex
15. Features Microprogrammable General Purpose Computer Set 4 Bit Parallel CPU With 45 Instructions Instruction Set Includes Conditional Branching Jump to Subroutine and Indirect Fetching Binary and Decimal Arithmetic Modes Addition of Two 8 Digit Numbers in 850 Microseconds 1165 4 FOUR BIT PARALLEL MICRO COMPUTER SET m 2 Phase Dynamic Operation 10 8 Microsecond Instruction Cycle CPU Directly Compatible With MCS 4 ROMs and RAMs Easy Expansion One CPU can Directly Drive up to 32 768 Bits of ROM and up to 5120 Bits of RAM Unlimited Number of Output Lines Packaged in 16 Pin Dual In Line Configuration MCS 4 CAPABILITIES ARE EXPANDED BY THE ADDITION OF THE 4008 4009 THE STANDARD MEMORY AND INTERFACE SET Expanded Features Directly Compatible With 4004 CPU Interface 1702A PROMs Directly to 4004 CPU Completely Eliminates TTL Interface Permits Program Storage in Alterable Memory Execute MCS 4 Programs from any Mix of Standard Intel PROMs ROMs and RAMs Expanded Capability Each Port May be Both Input and Output Up to 16 4 bit Input Ports and 16 4 bit Output Ports Number of I O Ports is Independent of the Size of the Program Memory I O Ports and Control Lines are TTL Compatible New Instruction WPM Write Program Memory is Used for Loading Alterable Program Storage RAM CONTENTS Introduction A General Discussion B Applications for
16. 920 Atness Avenue Unit No 9 Downsview 416 661 9222 Toronto 392 Hamilton Avnet Electronics 6291 Dormain Rd No 19 416 677 7432 Mississauga Hamilton Avnet Electronics 880 Lady Ellen Place 613 725 3071 Ottawa QUEBEC Hamilton Avnet Electronics 935 Monte De Liesse 514 735 6393 St Laurent Montreal 377 Ordering Information Packaging Information The 4004 CPU is available in ceramic only and should be ordered as C4004 The 4001 ROM 4002 RAM and 4003 SR are presently available off the shelf in plastic only Standard devices should be ordered as follows P4001 Plastic Package P4002 1 Metal Option 1 Plastic Package P4002 2 Metal Option 2 Plastic Package P4003 Plastic Package 16 LEAD CERAMIC DUAL IN LINE PACKAGE OUTLINE The 4008 and 4009 standard memory and I O interface set are Bus available in plastic only 24 pin DIP They should be used as a e 830 set and ordered as P4008 and P4009 I Mask Programming of the 4001 The custom patterns chip numbers and 1 options including inverting and non inverting inputs or outputs and on chip resistor connected to either Vpp or Vss must be specified on a truth 055 a table for each 4001 ordered Blank custom truth tables are avail F 2 j able upon request from Intel SIM4 01 Prototyping System An interface board in which 1702 electrically programmable and erasable ROMs simulate the 4001 mask programmable ROMs provides a design to
17. RAM OUTPUT OUTPUT PORT BANK 3 RAM 3 OUTPUT R3 A 13 RAM OUTPUT PORT BANK 3 RAM 3 R3 A 14 OUTPUT RAM OUTPUT PORT BANK 3 RAM 3 R3 A 15 CM RAM OUTPUT RAM OUTPUT PORT BANK 3 RAM 3 RAM BANK 1 COMMAND LINE OUTPUT MOS COMPATIBLE RAM BANK 2 COMMAND LINE OUTPUT CM RAM RAM BANK 3 COMMAND LINE OUTPUT 3 SYNC TTL MACHINE CYCLE SYNCHRONIZATION SIG TTL LEVELS MOS EXPANSION OUTPUT CM ROM OUTPUT PORT BANK 2 RAM 2 TS TEST SWITCH CONTROL NORMALLY OPEN OUTPUT PORT BANK 2 RAM 2 TEST SWITCH CONTROL NORMALLY CLOSED OUTPUT PORT BANK 2 RAM 2 RESET SWITCH CONTROL NORMALLY OPEN OUTPUT PORT BANK 2 RAM 2 RESET SWITCH CONTROL NORMALLY CLOSED OUTPUT PORT BANK 2 RAM 3 OUTPUT PORT BANK 2 RAM 3 PHASE 1 CLOCK MOS COMPATIBLE OUTPUT PORT BANK 2 RAM 3 PHASE 2 CLOCK RESET SIGNAL FOR 4004 EXPANSION OUTPUT TEST SIGNAL FOR 4004 EXPANSION OUTPUT ROM INPUT PORT STROBE EXPANSION OUTPUT OUTPUT ROM OUTPUT PORT STROBE EXPANSION ROM DATA OUTPUT EXPANSION OUTPUT OUTPUT ROM DATA OUTPUT 1 EXPANSION ROM DATA OUTPUT 2 EXPANSION OUTPUT ROM DATA OUTPUT 3 EXPANSION OUTPUT QUTPUT ROM DATA OUTPUT 4 EXPANSION
18. 1 ROM command control CM ROM and fhe 4 RAM command control CM RAM output buffers d Reset flip flop During reset Reset pin low all RAM s and static FF s are cleared and the data bus is set to 0 After reset program control will start from 0 step and CM RAM is selected To completely clear all registers and RAM locations in the CPU the reset signal must be applied for at least 8 full instruction cycles 64 clock cycles to allow the index register refresh counter to scan all locations in memory 256 clock cycles for the 4002 RAM Instruction Repertoire The instruction repertoire of the 4004 consists of a 16 machine instructions 5 of which are double length b 14 accumulator group instructions c 15 input output and RAM instructions The instruction set and its format will be briefly described in the next section Section VII will then describe each instruction in detail CPU Instruction Set Format Index Register Organization and Operation of the Address Register and Command Lines 1 Instruction Set Format a Machine Instructions e l word instructions 8 bits wide and requiring 8 clock periods 1 instruction cycle 2 instructions 16 bits wide and requiring 16 clock periods 2 instruction cycles for execution A l word instruction occupies one location in ROM each location can hold one 8 bit word and a 2 word instruction occupies two successive loca tions in ROM Each instr
19. Description The 4 bits of status character 0 for the previously selected RAM register are transferred to the accumulator The carry link and the status character are unaffected Mnemonic RD1 Read RAM status character 1 OPR 1110 1101 Symbolic 51 ACC m M U Mnemonic RD2 Read RAM status characer 2 OPR 1110 1110 Symbolic Ms2 er Mnemonic RD3 Read RAM status character 3 OPR OPA 1110 1111 Symbolic Mg 3 ACC LrInH O ee Mnemonic RDR Read ROM port OPR OPA 1110 1010 Symbolic ROM input lines ACC Description The data present at the input lines of the previously selected ROM chip is transferred to the accumulator The carry link is unaffected If the I O option has both inputs and outputs within the same 4 1 0 lines the user can choose to have either 0 or 1 transferred to the accumulator for those I O pins coded as outputs when an RDR instruction is executed EXAMPLE Given a 4001 with I O coded with 2 inputs and 2 outputs when RDR is executed the transfer is as Shown below I3 02 01 IQ ACC 1 X X 0 UTA 1 1 0 1or0 0 gt Z Input Data User can choose Mnemonic WRM Write accumulator into RAM character OPR OPA 1110 0000 Symbolic ACC M Description The accumulator content is written into the previously selected RAM main memory charactfr location The
20. Pg unchanged Description The 8 bit content of the designated index register pair is loaded into the low order 8 positions of the program counter Program control is transferred to the instruc tion at that address on the same page same ROM where the JIN instruction is located The 8 bit content of the index register is unaffected EXCEPTIONS When JIN is located at the address Pg 1111 1111 pro gram control 18 transferred to the next page in sequence and not to the same page where the JIN instruction is located That is the next address is PH 1 RRRO RRR1 and not PH RRRO RRR1 Mnemonic SRC Send register control OPR OPA 0010 Symbolic RRRO X2 RRR1 DB X3 Description 8 bit content of the designated index register pair is sent to the RAM address register at and subsequent read write or I O operation of the RAM will utilize this address Specifically the first 2 bits of the address designate a RAM chip the second 2 bits desig nate 1 out of 4 registers within the chip the last 4 bits designate 1 out of 16 4 bit main memory characters within the register This command is also used to designate a ROM for a subsequent ROM 1 0 port operation The first 4 bits designate the ROM chip number to be selected The address in ROM or RAM is not cleared until the next SRC instruction is executed The 8 bit content of the index register is unaffected 26 Mnemonic FIN
21. lt 4 a c 3 5 gt hs 5 2 2 e 2 5 1 0 0 1 2 3 4 5 6 7 OUTPUT VOLTAGE V j OUTPUT VOLTAGE V 104 4001 4002 4004 Characteristics 09 to 709 Vpp 15V 5 Vss GND 4001 2 4 CLOCK PERIOD CLOCK WIDTH CLOCK DELA Y FROM 1 TO 2 CLOCK DELAY FROM 2 TO 1 phe DATAAN WRITE TIME DATA IN HOLD TIME SET TIME FOR DATA OUT SYNC CM ROM 2 cM 2 LINES TIME FOR DATA OUT SYNC CM ROM LINES RISE AND FALL CM WRITE TIME tHC CM HOLD TIME 1 0 INPUT LINES SET TIME 1 O INPUT LINES HOLD TIME 1 O OUTPUT LINES DELAY ON CLEAR tey twC 4001 4002 4004 Timing Diagram LIMIT PR ODUCT SYMBOL TEST MIN MAX UNIT CLOCK RISE AND FALL TIMES NNE NEM E TIMES FOR DATA OUT SYNC CM ROM CM RAM LINES 4001 2 OUTPUT LINES 600 DELAY w xe CONDITIONS 500pF for data lines 500pF for SYNC 160pF for CM ROM 50pF for CM RAM Court 500pF for data lines 500pF for SYNC 160pF for CM ROM 50pF for CM RAM Cour 20pF NOTES out SYNC CM ROM and CM RAM lines are clocked out with ythe trailing edge of the 2 clock 2 The CM ROM and the selected CM RAM lines are always activated during A3 time They are also activated during M time if and RAM instruction was fetched by the CPU and during X2 time if an 555
22. the 10th time when the contents of register 14 is incremented it goes to the value 0000 and the program skips to the next instruction in sequence and gets out of the loop Clock pulse streams of the type derived above are often used to drive groups of 4003 shift registers It may often be desirable to transfer the contents of a RAM register to a group of 4 shift registers via two output ports Fig 9 shows the connection used To operate this system it is necessary to fetch a character from RAM and present it at port 2 then issue the clock pulse at port 1 This sequence requires three SRC commands one for the RAM selection one for port 1 selection and one for port 2 selection 37 In addition the location in RAM must be incremented each time to pro vide selection of the next character 7 SEGMENT DISPLAY RAM PORT 1 RAM PORT 2 DP NOT USED Figure 9 RAM Output Ports Driving Groups of Shift Figure 10 Shift Registers Driving Seven Segment LED Registers Displays The main loop is then as follows Loop SRC Send address to selected RAM RDM Read selected RAM character into accumulator SRC Send address to 12 WMP Write contents of accumulator previously slected RAM ee character into Port 2 Send address to RAM 1 LDM 0 5 15 Set accumulator to O WMP ADD 15 Generate 1 clock pulse WMP INC Increment by 1 the contents of the register pair hol
23. 0543 and a modified teletype The teletype modification consists of the addition of simply relay network described by MCS 4 Users Manual or TTY application note The procedure for programming a PROM then is as follows Insert MP7 03 and SIM4 02 boards SIM4 02 loaded with PROM 40540 A0541 0543 Connect teletype to TTY socket using the flat cable provided Connect 5V DC 10V DC and 115V AC 220V AC Set DC Power switch to See Caution below Depress RESET Set PRGM AC to ON _ Set Data Out to Enable Set Data In and Data Out to desired position Set TTY switch to TTY Connect 10 Place teletype in ON LINE mode 11 Depress RESET 12 Insert an erased 1702A PROM into the PROM to be Programmed 24 pin zero force socket 13 Place paper tape in TT Y reader and set reader to START 14 Type in program comman P and beginning and ending addresses CONAMAWN The steps above are fully described in section XIII i the MCS 4 Users Manual The PROM is then automatically programmed and checked for correct content CAUTION Permanent damage may result to MP7 03 board and PROM to b programmed if the DC POWER is turned OFF BEFORE the AC is turned off The SIM4 02 and MP7 03 should never be inserted into their respective sockets with either the DC or AC power applied APPLY DC POWER BEFORE AC POWER AND REMOVE AC POWER
24. 10 P 64 SRC CLB WMP CLB LD 15 RAR JCN C1 OUP RAR JCN OUP RAR JCN C STOP FIM P 32 SRC P LD 11 WRR INC SRC PQ LD 18 WRR JUN COMP FIM P SRC CLB WMP JUN START FIM PB 32 SRC LD 11 WRR INC SRC LD 18 WRR JMS DLYTO CLB LD 15 RAR JCN Ci PGMA RAR JCN C1 PGM02 JUN STOP FIM PO 64 SRC LDM 2 WMP JMS LDM 2 WMP JUN FIM SRC LDM 4 WMP JMS LDM FIM SRC WMP JMS FIM FIM SRC RDR SRC WMP XCH 9 INC 2 LDM 4 ADD 2 XCH 2 SRC P RDR SRC WMP XCH 8 CLC LD 11 SUB 9 JCN AN NOCMP STORE ROM DATA L R11 SET SRC ROM 3 ROM DATA H SEND ROM 3 IP 3 READ ROM DATA H IP 3 COMPLEMENT DATA STORE ROM DATA R LE SET SRC RAM 1 ROM CS SEND RAM 1 CLEAR ROM CS BIT Z DISABLE ROM CS 213 CLEAR AC CY LOAD MODE SELECT 7 CHECK 17024 MODE JUMP IF 1 DUP AC Z CHECK 1702 MODE JUMP IF 1 DUP CHECK COMPARE MODE 7 JUMP IF CY STOP SET SRC ROM 2 ROM DATA L SEND ROM 2 IP 2 WRITE ROM DATA L SET SRC ROM 3 ROM DATA H SEND ROM 3 IP 3 Z WRITE ROM DATA L SET SRC RAM SEND 0 CLEAR START LAM P OFF 01 JUMP TO START SET SRC ROM 2 PROM DATA IN L SEND ROM 2 OP 2 LOAD ROM DATA L AC WRITE PROM DATA IN L OP 2 SET SRC ROM 3 PROM DATA IN H SEND ROM 3 O
25. Mnemonic Machine Language OPR OPA E 2 1101 0010 Select bank 2 T 1111 1101 FIM 4 0010 1000 13 6 11 0110 Select Chip 3 Register 1 Character 6 l4 3 s UJEN lt gt m 0010 Fetch the Mantissa sign 1110 1111 From status Character 3 to Register 10 in the CPU 10 1011 1010 Fetch the exponent sign k 1110 1110 from status character 2 XCH 11 1011 1011 to Register 11 in the CPU Fetch the exponent from 1110 1101 status Character 1 and 12 1011 1100 0 to Register 12 and 1110 1100 13 respectively in 13 1011 1101 Fetch the previously 1110 1001 selected main memory character 6 which stored the decimal digit 7 to the accumulator Example 8 Interpretive Mode Interpretive mode programming may be used to reduce the amount of ROM required to implement a particular system function this mode data words fetched from ROM or RAM are treated as instructions of a computer which might be quite different than the MCS 4 MCS 4 program interprets the data using it to call appropriate subroutines which simulate the instructions of the different computer In effect another computer architecture is simulated In the interpretive mode the instructions of the simulated com puter pseudo instructions may be derived from RAM or ROM The instructions are fetched from RAM via the normal RAM operations SRC RDM using
26. gs FOUR BIT AND ROUTINE START FIM LOAD ROM PORT ADDRESS 2 SRC 4P SEND ROM PORT ADDRESS 3 RDR READ INPUT A 4 XCH 0 TO REGISTER 0 5 INC 8 LOAD ROM PORT 1 ADDRESS 6 SRC 4P SEND ROM PORT ADDRESS 7 READ INPUT B 8 XCH 1 B TO REGISTER 1 9 JMS AND 7 EXECUTE AND 11 XCH 2 LOAD RESULT 12 WMP STORE AT MEMORY PORT 0 13 JUN START RESTART 15 NOP 16 2104 104 AND SUBROUTINE 104 AND CLB CLEAR ACCUMULATOR AND CARRY 105 XCH 2 CLEAR REGISTER 2 196 LDM LOAD LOOP COUNT LC 107 XCH LOAD LC TO REGISTER 0 108 RAR ROTATE LEAST SIGNIFICANT BIT TO CARRY 109 RETURN ROTATED REG 0 LC 110 JCN CZ ROTRI 7 JUMP TO IF CARRY ZERO 112 XCH 1 LOAD B LC TO ACCUMULATOR 113 RAR ROTATE LEAST SIGNIFICANT BIT TO CARRY 114 XCH 1 RETURN ROTATED B TO 1 LC TO 115 ROTR2 2 LOAD PARTIAL RESULT C LC TO REGISTER 2 116 RAR ROTATE CARRY INTO PARTIAL RESULT MSB 117 XCH 2 LOAD LC RETURN C TO REGISTER 2 118 DAC DECREMENT THE ACCUMULATOR LC 1193 JCN ANZ AND 3 LOOP IF LC NON ZERO 121 BBL 9 RETURN 122 ROTRI 1 LOAD B LC TO REGISTER 1 123 RAR ROTATE B 124 XCH 1 RETURN ROTATED 1 LC TO 125 CLC CLEAR CARRY 126 JUN ROTR2 RETURN LOOP 128 2 510 128 2 12 128 Figure 2 Pass 1 Listing 139 address a
27. ning with location n Spaces commas returns and linefeeds may occur with any frequency or pattern between the individual numbers Input is terminated by free standing letter F in the sequence ASCII SOH control A may be used to introduce a decimal number which like n becomes the new starting address for subsequent instruction bytes The program counter in the current stack level is altered by this directive Punch This directive will punch out in BNPF format with location numbers the contents of the simulated ROM beginning at location n decimal and ending with location m The currently selected program counter and the breakpoint regis ter are altered by this directive Four inches of leader and trailer are punched on the tape with an F after the last location If the BREAK key on the teletype is depressed between locations the typeout will be aborted with no trailer Both the breakpoint register and the program counter in the current stack level are altered by this directive Memory input This directive accepts a sequence of decimal numbers 0 15 and stores them sequentially in consecutive RAM loca tions beginning in register n decimal 0 63 and location i decimal 0 19 If the starting location is in main memory i less than 16 only main memory locations are filled The next number after the one which goes into register r digit 15 goes into register r 1 digit 0 If the starting location is a statu
28. 00036 00048 88218 20182 00241 00037 88233 00033 1235 00251 20224 00097 00101 00118 00055 00192 02208 00177 28208 00037 00224 00101 00113 00266 00192 00038 00066 00080 00235 00081 00033 00028 99973 00216 29185 00080 02235 9 00 38 909890 00081 87833 00020 00111 00038 00078 00081 00033 00020 60111 85838 02066 00081 00033 00020 02081 00038 00127 02081 00033 02028 02158 02065 00144 00052 89816 00035 00163 02245 00237 00245 09229 90236 82245 00228 00121 00083 20080 080235 00058 00070 00081 00053 00220 00189 00038 000 66 COMPR NEG ADDTN AD1 CLRAM CLEAR REPT 1 CONT FINAL CLC XCH SUB JCN CLC XCH SUB CLC JCN 8BL BBL FIM LOM XCH CLC SRC ROM SRC ADM DAA WRM INC INC ISZ BBL LOM XCH LDM SRC WRM INC 152 BBL FIM JMS JMS JCN LOM XCH JMS FIM JMS JCN FIM JMS JCN FIM JMS JCN FIM JMS JCN JUN FIM SRC LD 3 RAL RD1 RAL WRI RD RAL 152 JMS FIM JMS JCN DATA COMPARE ROUTINE NEG TEST FOR 15 NOT AN NEG IR O 29 IR 1 0 48 IR 4 3 1R 5 8 ovne AD1 e 5 1 CLEAR P3 66 IR 6 z4 18 7 2 B TTY CALL INPUT ROUTINE COMPR CALL FOR COMPARE ROUTINE AN REPT YEST FOR NONZERO AC 8 B DATA BITS wy LOOK FOR A DATA WORD P3 80 1R 6 5 IR 7 z0 P COMPR A2 CONT TEST FO
29. 05982 2583 0505 85 07 4508 509 0510 8511 0512 2513 0514 0515 0516 0518 0520 8521 8522 8523 0525 0527 0529 0551 8532 0533 0534 05 35 0536 0537 0538 0539 0540 8541 0542 05 44 0545 0546 0547 0548 0549 9551 0555 05 55 0557 0559 05 61 9563 0565 0566 9567 95 69 6571 0573 0574 0575 8576 9577 9578 0579 0588 9581 0582 9583 9584 9585 0586 0587 0588 0589 0590 8591 0592 0593 0594 0595 8596 9598 2628 6682 0604 8625 00033 008239 02138 92837 00231 00066 00006 00032 02816 09033 00238 00242 00232 89288 00178 00259 00130 002531 00065 88973 20032 00032 00033 00236 80246 20026 00015 09966 78898 02832 99016 00236 20032 70833 00257 39937 88226 09233 00256 70100 00237 20226 004227 20186 20038 00464 200 39 one 04200 12210 11225 00236 002000 22040 00211 20116 00041 82117 00041 00120 00241 00980 00164 00480 00171 00121 00041 02208 87225 000436 00128 29989 00164 00080 00164 20096 00096 00033 00254 99937 78225 82185 29212 92132 00180 00096 00033 00234 020357 89225 02182 00209 00176 00035 00236 80178 61237 00179 00081 88933 00020 00090 00266 80162 00032 20000 00233 00236 CONT2 SRCH CONT1 PRGRM DELY1 READ ADCHK SRC RDS ADD SRC JUN FIM SRC RD2 WR2 LDM XCH RD3 ADD WR 3 JUN FIM SRC RDB RAR JCN JUN
30. 1 the JCN instruction could be coded OPR C162C3C4 Location 2 0001 1001 Inverted jump condition oT Location 3 0001 0000 33 Im this case the invert condition bit C1 is used to indicate a jump is to be made a logic 1 on the test signal If more switches are required a ROM port may be used as shown in the next example EXAMPLE 2 Consider the case where it is desired to test the status of a switch connected to the port of ROM 2 To make access to the port it is necessary to execute and SRC instruction The SRC instruction utilizes the contents of a pair of registers which must contain the proper num bers to select the desired port Register pairs may be most easily loaded using the FIM instruction Thus the sequence Mnemonic Description FIM O Fetch immediate direct from ROM data 0010 0000 2 0 to index regiser pair O SRC 0 Send the contents of index register pair 0 to select a ROM The first 4 bits of data sent out at X gt time 0010 select ROM 2 RDR Read to contents of the previously selected ROM ROM 2 input port into the accumulator has the effect of loading the accumulator with the values appearing at ROM port 2 Individual bits may be tested by shifting them into the carry flip flop and using a jump on condition instruction In this manner up to 4 switches can be interrogated from one set of ROM input ports 4 of them EXAMPLE 3 Suppose a series of 10 clock
31. 29238 00246 80018 00247 002 32 20000 00033 00236 00185 29237 0 01 82 00096 20033 20238 g0179 00239 00178 00081 000 33 00428 00249 00054 00170 000280 00178 20852 020832 00209 80833 28238 00032 92088 00036 00016 02033 00238 00242 00037 00252 00208 92178 RBOUT FORMT PRINA FORM1 JMS COMPR JCN AZ REPTB FIM P3 127 ZIR 6 7 18 7 15 RO JMS COMPR JCN AN FORMT FORMAT ERROR FIM 16 SRC RD RAR WRB RD1 RAR 1 LD 9 DAC XCH 9 JUN DATA1 JMS CRLF POSITION CARRIAGE JMS FMER JMS PRINA FIM P5 32 ZIR 10 2 IR 11 0 LDM 1 SRC 5 WRB JUN STB CHIP REG 2 CHAR LDM 13 PRINT FMERROR ADDRESS XCH 12 18 12 213 FIM 5 53 ZIR 10 3 IR 11 z5 SRC P5 PRINT OUT ADDRESS RDM XCH 3 LOM 11 XCH 2 JMS PRINT LD 11 DAC XCH 11 CLC ISZ 12 FORMi BBL FIM P 16 SRC RD1 CMA WRI WRB FIM 32 ZIR 2 IR 1 z0 INIT ADR SRC RD2 RAR JCN CN CONT FIM 9 18 20 IR 1 20 ADR COMP SRC P9 RDJ RD1 XCH 6 INC 0 SRC RD2 XCH 3 ROS XCH 2 JMS COMPR JCN AN SRCH FIM P1 170 R C2 512 IR 3 z10 JMS PRINT FIM P6 3 IR CO 22 IR 1 0 LOM 1 Z SET INIT ADR FLAG SRC FIM 2 IR B 1 FIM P2 16 ZIR 4 1 IR 5 8 SRC PP SRC 2 WR2 LOM XCH 2 167 9498 0499 0500 0581
32. AAAAAAAA DDDDDDDD MODIFIERS none condition address register pair data register pair register pair register pair address address register register address register register register register data data none none none none none none none none none none none none none none none none none none none none none none none none none none none none none NOTE The MCS 4 Assembler is currently being modified to accept the WPM instruction associated with the 4008 4009 154 A register pair may be designated by including the numeric value corresponding to the even numbered register of the pair by a P followed immediately by the number f through 7 of the register pair in decimals or by a P followed immediately by a 3 bit binary code Examples of acceptable forms are g 2 1 Pl P7 register may be designated by including the register number or by the form R through R15 A condition code may be satisfied by the inclusion of a numeric value corresponding to the desired condition code or by using one of the condition codes shown in Table 2 Note that Table 2 does not include all possible condition codes for the JCN instruction A label is a tag attached to a particular line of code The label will take on value corresponding to the address assigned to that line of code by the assembler To associate a tag with a line of code the tag or label is made the first item
33. F Figure 2 2 Pass 2 Listing Assembly Language The assembler operates with the 64 character subset of ASCII generated by the ASR 33 teletype along with the control characters carriage return linefeed escape start of heading start of text and delete or rubout The 31 character subset containing the lower case letters are ignored by the assembler and are treated the same as the delete character Source instruction mnemonic statements include all of those specified in the MCS 4 Users Manual This set is augmented by extended mnemonics for conditional jumps and a pseudo operand used for equating labels to values or modification of the assembly address Symbolic addressing is provided for by definition of labels consisting of one or more characters The use of comment fields and transparent headers is also provided for by the assembler CONTROL CHARACTERS In the discussion to follow the following generic terms will be used freely Control Any of the first 32 codes in the full ASCII set obtained on the teletype by one of the special keys linefeed return or ESC or by holding down the CTRL key while typing a letter key Separator of the first 48 codes the full ASCII including the control space comma plus minus slash etc Any number of separators may be linked together wherever a separator is to be used but the other separators should normally be used singly Digit Any of the ten digits 0
34. FIM FIM SRC Rn1 SRC WRR SRC 808 INC SRC WRR LOM XCH FIM SRC NOP NOP LDM FIM FIM 152 152 152 JMS JMS 152 LDM WMP FIM JMS JMS INC INC SRC RDR SRC WMP XCH LOM ADD XCH INC SRC RDR SRC WMP XCH LDM XCH SRC RD2 XCH RD1 XCH JMS JCN JUN FIM SRC RDO Pg 2 P2 CONT1 P 16 1 1 IR 1 9 P INC INIT ADDRESS BY ONE 1 g 2 2 REPT P 32 IRC8 22 IR 1 0s8 P CHECK FORMAT ERROR EXIST CZ NOFE ADCHK P 16 IRC CO 21 IR 1 sQ P2 32 1RC4 22 IR 5 0 P WRITE DATA TO 1701 P2 LS 4 BITS DATA P 4 P2 MS 4 5 DATA 12 12 P3 64 YR O6224 18 7 8 P3 2 PULSING FOR 517 MSEC P2 0 1RCGD IR 20 P4 11 1RCB 20 IR 9 11 4 DELY1 5 DELY1 8 DELY1 SBR1 SBR2 9 DELY1 2 2 128 18 4 8 IR 5 0 SBR1 READ DELAY 5 6 MS SBR1 20 READ DELAY LS 4 8175 1701 OUTPUT DATA MS 48 1701 OUTPUT DATA 2 MS 4 BITS INPUT DATA 3 LS 4 BITS INPUT DATA COMPR A2 ADCHK RPRGM P P 0606 0607 0608 06 09 8618 0611 0612 0615 0615 0617 0619 0621 0623 0625 0626 0627 0628 0629 0630 0632 0634 0656 06 38 0640 0642 0643 0644 0645 0647 0649 0651 0652 0655 0654 0655 0656 0657 0658 659 0661 g663 8664 0665 0666 0667 9668 0669 0678 8671 0672 0674 0676 0678 0680 2682 0684 2800 8221 0022 0004 0026 0008 0009 0010 0011 0012
35. Fetch indirect from ROM OPR OPA 0011 RRRO Symbolic PH 0000 0001 ROM address OPR RRRO RRR1 Description The 8 bit content of the O index register pair 0000 0001 is sent out as an address in the same page where the FIN instruction is located The 8 bit word at that location is loaded into the designated index register pair The program counter is unaffected after FIN has been executed the next instruction in sequence will be addressed The content of the 0 index register pair is unaltered unless index register 0 was designated EXCEPTIONS a Although FIN is a l word instruction its execution requires two memory cycles 21 6 psec b When FIN is located at address 1111 1111 data will be fetched from the next page ROM in sequence and not from the same page ROM where the FIN instruction is located That is next address is PH 1 0000 0001 and not Pg 0000 0001 E Two Word Machine Instruction Mnemonic JUN Jump unconditional lst word OPR 0100 2nd word OPR OPA A9 A9 2 A2 Ay Aj Symbolic Aj gt PL A2 A2 A2 PM Description Program control is unconditionally transferred to the instruction locater at the address A2 A2 1 A n PU pU c IE ee LAN Mnemonic JMS Jump to Subroutine lst word OPR 0101
36. Subtract index register from accumulator with borrow OPR OPA 1001 RRRR er Synbolic ACC RRRR CY CY Description The 4 bit content of the designated index register is complemented ones complement and added to content of the accumulator with borrow and the result is stored in the accumulator If a borrow is generated the carry bit is set to 0 otherwise it is set to l The 4 bit content of the index register is unaffected Example Minuend Subtrahend ACC CY RRRR a3 Borrow 53 S9 51 50 lt Result Mnemonic INC Increment index register OPR 0110 RRRR Symbolic RRRR 1 RRRR Description The 4 bit content of the designated index register is incremented by 1 The index register is set to zero in case of overflow The carry link is unaffected Mnemonic BBL Branch back and load data to the accumulator OPR OPA 1100 DDDD Symbolic Stack gt Py PH DDDD ACC Description The program counter address stack is pushed down one level Program control transfers to the next instruction following the last jump to subroutine JMS instruction The 4 bits of data DDDD stored in the OPA portion of the instruction are loaded to the accumulator BBL is used to return from subroutine to main program Mnemonic JIN Jump indirect OPR 0011 Symbolic RRRO RRR1
37. Two different modes of operation are available 1 A complete program tape consisting of 256 data words in sequential order may be used a To program the complete ROM place the ROM to be programmed into the socket on the MP7 02 board and then type S 2 start command 000 init al address address 0 of the ROM 255 final address address 255 of the ROM Start the tape data words may also be entered in sequence manually The ROM will be programmed in all 256 locations b To skip a section of the ROM skipping the same number of data words on the tape and then program a section of the ROM while still keeping the addresses in sequential form on the complete tape type S start command XXX initial address YYY final address Start the tape The ROM will only be programmed in the specified locations Operate the TTY in the line position Depress the RETURN key after each manual data word entry When using the tape reader to enter the program data switch the reader to start after the final address is entered 85 EXAMPLE 1 Typed S start command by 005 P initial address User 010 final address BNPNPNPNNF BPPPPPPPPF BPPPPPPPPF 4 data words skipped on BPPNPPPNPF programming tape BPPPPPPPPF BNNPNNPPPF _ q4 programming begins BNPNNPNPPF BPNP
38. Waugaman Associates Inc 4643 Wadsworth Suite C 303 423 1020 TWX 910 938 0750 Wheatridge 80033 Direct Intel Sales Office 17401 trvine Blvd Suite K 714 838 1126 TWX 910 595 1114 Tustin 92680 FLORIDA Semtronic Associates 5100 DuPont Blvd Suite 8E DuPont Towers 305 782 1596 Ft Lauderdale 33310 Semtronic Associates 100 Maitland Avenue Suite 216 305 831 6851 Altamonte Springs 32701 ILLINOIS Mar Con Associates Inc 4836 Main Street 312 675 6450 Skokie 60076 MARYLAND Barnhill and Associates 1931 Greenspring Drive 301 252 5610 Timonium 21093 Barnhill and Associates P O Box 251 301 252 5610 Glen Arm 21057 MASSACHUSETTS Bill D Eramo 594 Marrett Road Suite 27 617 861 1136 Telex 92 3493 Lexington 02173 Datcom 7A Cypress Drive 617 273 2990 Burlington 01803 594 Marrett Road Suite 27 617 861 1136 Telex 92 3493 Lexington 02173 U S SALES OFFICES MICHIGAN Sheridan Assoc Inc 33708 Grand River Avenue 313 477 3800 Farmington 48024 MINNESOTA Carl Branger 800 Southgate Office Plaza 5001 West 78th Street 612 835 6722 Bloomington 55437 E C R Inc 4004 W 78th Street 612 927 4547 TWX 910 576 3153 Minneapolis 55435 MISSOURI Sheridan Assoc Inc 110 S Highway 140 Suite 10 314 837 5200 Florissant 63033 NEW JERSEY Addem Post Office Box 231 516 567 5900 Keasbey 08832 NEW YORK Ossmann Components Sales Corp 395 Cleveland Drive
39. When ordering a 4001 the following informa tion must specified 71 PIN 16 1 Chip number 1 2 All the metal options for each I O pin 3 ROM pattern to be stored in each of the 256 locations 2 L A blank customer truth table is available upon BL request from Intel A copy of this table is shown in the appendix 1 0 1 02 AND 1 0 2 1 FOLLOW THE SAME FORMAT Vss GND Figure 6 4001 Available Metal Options for Each 1 Pin 4002 320 BIT RAM AND 4 BIT OUTPUT PORT The 4002 performs two d stinct functions As a RAM it stores 320 bits arranged in 4 registers of twenty 4 bit characters each 16 main memory characters and 4 status characters As a vehicle of communication with peripheral devices it is provided with 4 output lines and associated control logic to perform output operations The block diagram is shown in Figure 7 In the RAM mode the operation is as follows When the CPU receives an SRC instruction it will send out the content of the designated index register pair during and X3 and will activate one CM RAM line at for the previously 1 selected RAM bank The data at and X4 is interpreted as shown below D5 D2 01 Do Main Memory Character No 0 through 15 92 Chip No through 3 D1 Do Register No 0 through 3 The status character location through 3 as well as the operation to be performed on it are selec
40. directive to hold all of this Suppose further that the program accesses only bank zero in RAM The directive would be something like this 016 0 127 Then the first 32 locations of the program tape read in using the directive entire tape may be read with no deleterious effects if that is convenient or an F may be typed in manually at the end of the first 32 locations worth of data Then the Q directive is used again to re assign the same locations to the next block of addresses 099 224 355 Note that the address limits been offset 32 to prevent the obliteration of the first 32 locations object tape may be read in again or at least that part of it which includes the next block of data or instructions Then the area is reassigned again O99 448 575 The process is repeated until the whole program is loaded To execute the O directive for the starting block of code is typed in again If the segments are placed correctly each time a jump is made to another segment an out of range interrupt occurs The Q directive for the segment jumped to is entered and the program may proceed This technique may also be used to relocate a program in ROM for example the following sequence of commands will effectively move shift a program up one position in ROM 00 0 255 10 program 1 256 1 256 JUMPS TO PAGE 0 Because of the nuisance of doing serial to parallel conversion and properly
41. fraction and a 2 digit exponent Consider the number 59 t 2 1 87406 10 137 me 7 x Mantissa 16 digits Exponent 2 digits Storage is required for both the sign of the mantissa in this case positive and the sign of the exponent in this case negative 16 digits of mantissa and 2 digits of exponent The 4 status characters of the register be used to hold the signs in this case a 1 re presents minus this definition is completely arbitrary and is com pletely up to the user and the 2 digit exponent The 16 main memory characters are used to hold the 16 digit mantissa This description of the operation of the address stack is equivalent to the description in Section IIIB 3 just looks at it from a different view point For example let s store the previously shown number in Bank 2 Chip number 3 register 1 It would be stored in the 4002 as follows Register 1 Decimal digit 6 Decimal digit O Decimal digit 4 Decimal digit 7 Decimal digit 8 Decimal digit 3 Decimal digit 7 Decimal digit 5 Main Memory Character Decimal digit 1 Decimal digit 4 Decimal digit 9 Decimal digit 9 Decimal digit 2 Decimal digit 7 Decimal digit 3 Decimal digit 1 Exponent Value J 59 Exponent Sign Negative Status Character Mantissa Sign Positive The following instructions would be used to fetch character 6 the signs and exponent value 41
42. i A gt ED b 1 mt 4 Y jg if 2 ES i Tape ze dis 2 1 m el p d d 455 apa x 4 5b 1 5 FT E ep ks gp el pel mt ie 5 za 7400 a peona De hp 2 5 irs a S ZR ap ry 9 EE CE L S U U Z U U U FERAM OE _ fa me i 7 eh a 21 h uc n m gt or oe 2 Le Bir sss K B WP 5 wow w i 5 2 Las E 2 324 1 SR um li H je eee 100 N 4 L T Boos ean fa a R 5 gt x 5 250 WP T m 252 i lt g 11 1 I P 4 45 Epp gens Pa 5 li 11 li 4 pp equo cU get nm 101 419 GG liaw f I 11 1 hw 7400 lea port aul 7400 1444 11 ss I l lili lli 5 Il Ill Er upbr ppp ERTES E 5 w ne 2 amp 5 4 i es l I 48 NET VL An NOTES UNLESS OTHERWISE SPECIFIED He Bu EN ALL DIODES ARE 11914 s 1400 CAE Pr 2 ALL TRANSISTOR A
43. without 4003 Unlimited I O with 4003 s Memory capacity expandable through bank switching 16 pin DIP package P channel Silicon Gate MOS Minimum system CPU and one ROM MCS 4 SYSTEM DESCRIPTION A General Description Each MCS 4 circuit constitues a basic standard building block which allows the design of many different types of systems which can be fabricated using the same parts The only custom part is the ROM chip which will store a microprogram defined by the user and requires a metal mask for each new program The MCS 4 micro computer set consists of the following packaged n a 16 pin DIP package 1 A Central Processor Unit Chip CPU 4004 2 A Read Only Memory Chip ROM 4001 3 A Random Access Memory Chip RAM 4002 4 A Shift Register Chip SR 4003 The CPU contains the control unit and the arithmetic unit of a general purpose microprogrammable computer The ROM stores microprograms and data tables the RAM stores data and instructions and the Shift Regis ter is used in conjunction with I O devices to effectively increase the number of I O lines The MCS 4 set has been designed for optimum interfaceability the CPU s 1 the RAM s and ROM s by means of 4 11 data bus This single data bus is used for all 1 mation Ha the chips except for control signals which sent to RAM and ROM over 5 additional lines One CPU controls up to 16 ROM s x 8 w
44. 0013 0014 0015 0017 0019 00179 98237 86178 02238 28183 00239 80182 80081 09033 00028 00124 002082 00226 00034 60878 20080 00178 88032 8032 20035 00208 00228 00229 00230 00036 00000 00081 09064 00864 00015 00036 002098 22881 00064 08032 88873 80233 80209 00224 00081 000246 88032 20002 998 36 90048 00218 00182 00433 00233 00037 00224 00297 00101 00118 88141 00032 00008 00033 00236 00242 00228 20208 00178 00237 09132 00229 20064 02085 99122 00168 29087 22135 20065 00162 00034 00164 82080 00178 97066 00030 209060 00002 00017 eggge 00046 00192 28932 29209 22033 00210 80225 00096 00033 00234 88191 00044 22220 200 32 20000 80233 STB INADR STOR1 RPRGM PRGMA START ROMAD XCH RD1 XCH RD2 XCH RD3 XCH JMS JCN JMS FIM JMS FIM SRC LOM WRO WR1 WR2 FIM JMS JUN FIM JMS FIM SRC LOM WRM JMS FIM FIM LOM XCH SRC ROM RC WRM INC INC 152 SRC WR LOM XCH ROL ADD WR1 JUN ISZ JMS JUN FIM JMS JUN G 6 COMPR AN INADR CRLF P1 70 18 2 4 18 3 5 PRINT 32 ADDRESS INCREMENT ZIR 0 sQ IR 1 3 18 4 3 18 5 0 2 2 PROMA 1 PRGMA ERROR PRINL IR 2 z10 IR 3 z4 P1 164 05 PRINT GRM 0686 0688 8698 8692 2694 9696 0698 0699 9721 0705 0705 0707 07 09 0717 0711 713 0714 97
45. 0040 0000 0044 0060 0320 0266 0361 0045 0351 0041 0353 9373 0340 0141 0145 0166 0007 0022 0025 0100 0310 0320 0272 0042 0330 0120 0536 9172 0027 0044 0000 0120 0454 0100 0310 ADi O VERFL XXX OVFL 1 16 DIGIT DECIMAL ADDITION ROUTINE FIM FIM L DM XCH CLC SRC RDM SRC ADM DAA WRM INC INC 152 JCN JUN LDM XCH FIM JMS ISZ FIM JMS JUN 0 lt 0 Pegi lt M 148 0 6 2 lt 1 5 63 AD XXX 3NEXT 10 1 lt 3216 3 PRINT 1030VFL1 2 lt 0 3 CLRRAM 3NEXT DUMMY ARGUMENTS CL RRAM 0300 0200 350 2 NEXT PRINT ASSEMBLY NEXT CAN BE THE N 45 IRCO 15220 IRC4 33 IRCS 0 LOAD TO AC EXCHANGE CCAC AND IRC6 CLEAR CARRY DEFINE RAM ADDRESS 61 READ RAM TO AC DEFINE RAM ADDRESS ADD CCRAM TO CARRY ENABLED DECIMAL ADDRESS ACC WRITE AC TO RAM INCREMENT IRC1 INCREMENT IRCS IRC6 IRC6 1 SKIP IF CC IR6 0 TEST CARRY JUMP IF 1 SEE NOTE C 2 LOAD AC WITH 0 EXCHANGE 16010 AND AC IRC1 83 IRC22213 X 19 1 10 13 SKIP IF IR 10 8 SET IRC4 5220 CLEAR RAM DATA SEE NOTE 2 1 RAM ADDRESSING DEFINE AS TO STANDARDS SPEC SHEET BITS NUMBERED FROM LEFT RIGHT MSB TO LSB 81234567 BITS 0 1 SELECT
46. 1 0223 112 9362 TEST 0036 ADI 0165 CLRRAM 0260 L1 0213 OVFLI 0244 SBRI 0271 ST 0030 ST 0330 WRITE 0112 81 2 0212 COMADD 0105 1 2 0302 PRINT 0307 SBR2 03090 STORE 0123 ST8 0334 XXX 0242 BEGIN 0000 CRLF 0367 NEXT 0017 REP 0012 SKIP 233 STI 0056 ST9 0360 XIII MCS 4 PROM PROGRAMMING SYSTEM A General System Description and Operating Instructions Intel has developed a low cost micro computer programming system for its electrically programmable ROMs Using Intel s eight bit micro computer system and a standard ASR 33 teletype TTY a complete low cost and easy to use ROM programming system may be assembled The system features the following functions 1 Memory loading 2 Format checking 3 ROM programming 4 Error checking 5 Program listing For specifications of the Intel PROMs refer to the Intel Data Catalog CONTROL PROGRAM ROM PROGRAMMING BOARD 1 2 e i 8 lt lt SIM4 01 OR SIM4 02 ROM SOCKETS PROM SOCKET Figure 27 MCS 4 PROM Programming System _ This programming system has four basic parts 1 The micro computer SIM4 01 or 51 4 02 This is the MCS 4 prototype board a complete micro computer which uses 1702A PROMs for the microprogram control The total system is controlled by the 4004 CPU 2 control program A0540 0541 A0543 These control ROMs contain the microprograms which control the bootstrap loading pro gramming format and error ch
47. 126 BPNPPPPPPF BPNNNPPNNF Figure 5 Programming Tape Listing 152 APPENDIX MCS 4 ASSEMBLER SIMULATOR SOFTWARE PACKAGE This appendix describes the use and operation of the assembler and simulator software package for the MCS 4 micro computer set This assembler simulator package is offered through Tymshare Inc G E Timeshare and AL COM nationwide computer timesharing services The software package allows the user to 1 prepare and edit his program 2 assemble these programs into MCS 4 compatible binary code 3 simulate the MCS 4 system s execution of this code and 4 generate tapes in a format suitable for programming 1602A or 1702A field programmable and erasable read only memories The output tapes so generated can also be delivered to Intel for preparation of masks for the 4001 mask programmed read only memory The assembler performs a number of error diagnostics checking for code overlapping invalid mnemonics illegal off page refer ences and several other common errors The simulator allows one to operate in a trace mode or to intro duce a break point in a program and to interrogate the contents of registers when the program arrives at the break point The MCS 4 Assembly Language Table 1 lists the instructions associated with the MCS 4 computer set Listed for each instruction is the standard mnemonic code used to describe that instruction to the assembler and its binary equivalent The number o
48. 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 Wirewrap Connector P N VPB01E36E00A1 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 108 6 4 2 Component Side of 7 03 Card Solder Connector P N 225 23621 101 123 4 5 6 7 8 9 101112 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Amphenot Wirewrap Connector P N 261 15636 2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 Wirewrap Connector P N VPBO1E36E00A1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Pin Definition Reverse Side of MP7 03 Card 9 R47 Vccs OUT 6 8K 5 Vccs OUT POWER SUPPLY REGULATOR 5 SN7486 DATA IN 1 23 10 8 9 8 R51 Ic 9 100 DATA IN 10 CONTROL SN7403 SN7486N 56 10 FILTER CAP ma 07 22 DATA 1 2 a RN 4 7 W MJE 1102 PIN 13 DATA OUT 1 32 ENS cz M 012 Ad 8 VR4 R7 oe DATA OUT R29 D U T 11 100 ENABLE ADDRESS 6 8K AC CR14 CONTROL 1N4002 se 2 MCR 106 3 OEA B n 018 A1 vRs 1K 330 PIN 2 13 5 1N5263A 25 m lt 6 8K 1N270 Vecs OUT PIN 12 DD 2 SN7486N 60 D U T 34 am 873 an 2 2 4 N 1N5258A DATA IN 330 PIN 1 1N4753A Qn PN
49. 9 Letter Any of the 26 capital letters of the alphabet Special significance is attached to the following characters by the assembler LINEFEED Source text lines are initiated by linefeed characters which are recognized by the assembler to condition the prefixing of the address value of the current location to be assembled SOH Start of Heading Control A If the first character after a linefeed is an SOH all characters following it until the next STX are ignored by the assembler and not printed on pass 1 of the assembly 130 STX Start of Text Control B Heading information initiated by an SOH is terminated by a STX Another SOH may follow the STX with more heading information which is in turn followed by another STX and so on as desired The assembler delimits the address counter typeout with an SOH STX pair so that its presence on the tape will not interfere with the subsequent use of the tape as source text input ESC Escape An erroneous line of input source text may be cancelled by an escape character or a cancel Control X if it is typed in before the terminal separator of the mnemonic or any required operands The assembler responds to an escape cancel by typing the up arrow then ringing the bell The line will be restarted after the next linefeed If the up arrow and bell response is not forthcoming the cancel has been ignored because either it is too late in the line i e the terminal delimiter ha
50. 9g 3e 0031 00 33 09 35 0036 00 37 00173 882 26 82096 00033 20172 202 26 00052 00064 22833 00216 00225 20080 00190 89832 80832 82833 20234 00244 FIM JMS FIM JMS FIM JMS BBL JMS FIM JMS FIM JMS LDM XCH FIM LDM JCN FIM JMS JUN FIM JMS XCH ISZ P1 198 18 2 12 18 3 6 PRINT P1 19 ZIR 2 12 IR 3 z5 E PRINT P1 160 ZIR 2 z1 IR 3 D SP PRINT PRINA Pi 160 71 23 218 IR 3 z0 SP PRINT P1 194 IR 2 212 1803 22 8 PRINT 14 18 P6 SET BIT COUNTER 48 JRC12 23 18 13 8 12 6 P6 14 CZ PRNTN P1 228 18 2 13 IR 3 9 PRINT NEXT 2 P1 226 IR 2 12 IR 3 14 N PRINT 14 6 LD 12 DAC XCH 152 FIM JMS FIM JMS 152 LOM XCH JMS JMS JUN FIM JMS FIM JMS JUN 12 10 SECON P1 198 18 2 12 18 3 26 F PRINT P1 187 1R G s11 IRGDs11 SC PRINT 15 AINC 12 15 CRLF LF ADCHK Pt 160 SPACE PRINT 166 SPACE PR INT ADCHK LD 13 7 LOAD ROM ADR L WRR 7 WRITE ROM ADR L INC SET SRC ROM 1 ROM ADR SRC 4 SEND ROM 1 OP 1 LD 12 7 LOAD ROM ADR H WR R 7 WRITE ROM ADR H OP 1 FIM P 64 SET SRC RAM 1 ROM CS SRC P Z SEND RAM 1 LDM 8 LOAD ROM CSBIT WMP Z ENABLE ROM CS 213 JMS DLYTO READ DELAY 10 MS FIM P 32 SET SRC ROM 2 ROM DATA L SRC SEND ROM 2 IP 2 RDR READ ROM D
51. BEFORE DC POWER 3 Automatic PROM Duplicating Comparing The 4 20 be used to duplicate or compare 1702 1702A PROMs by the use of the SIM4 02 MP7 03 external power supplies and A0544 The following procedure should be followed for duplicating or comparing 1702 1 702A PROMs 1 Insert SIM4 02 into the MCB4 20 Install 0544 PROM in SIM4 02 PROM socket 0 Insert MP7 03 into the MCB4 20 Connect external power supplies and AC power cord Turn DC Power switch on See Caution note Press Rest button Oo PD WN 125 7 Provide ground potential to ROM Input 0 3 socket J9 number accordance with desired operation a Duplicate 1702A PROMs GND J9 5 b Duplicate 1702 PROMs GND 49 6 c Compare 1702 1702A PROMs GND 49 7 8 Set Data Out control switch to ROM Duplicate for duplicate and compare 9 Set both Data In and Data Out switches to either True for exact duplicate or Complement for complement duplicate For compare always set the switches to True 10 Set TTY switch to TTY Disconnect 11 Press Reset button 12 Turn AC switch for duplicating ONLY 13 Insert REF PROM into Duplicating REF PROM socket and other PROM in PROM to be Programmed socket 14 Press Test button BANK 0 RAM 0 Bit 1 will light indicating Start 15 a If an error occurs during dupl
52. Bit 3 ROM 3 Bit ROM 3 Bit 1 ROM 3 Bit 2 ROM 3 Bit 3 Start Error Finish 1702A R W Control 1702 R W Control Prom DE REF ROM CS The complete program is shown in Appendix H 128 Status Control PROM to be PRGM Data Out PROM to be PRGM REF ROM Address PROM to be PRGM Data in REF ROM Data Out APPENDIX F SIM4 HARDWARE ASSEMBLER for SIM4 01 or SIM4 02 INTRODUCTION The SIM4 Hardware assembler is a program stored in Intel PROMs A0740 A0741 A0742 and A0743 which translates a symbolic assemibly language into bit patterns suitable for MCS 4 control storage programming It operates on the SIM4 01 or the SIM4 02 micro computer system with at least 3 RAMs and an ASR 33 teletype A block diagram is given in figure 1 1 The assembler accepts input source text from the teletype keyboard or paper tape reader on each of two required passes A name table and source listing are created on the first pass On the second pass the source text is reread and a programming paper tape and associated listing are generated The programming tape is suitable for programming of the Intel 1702A erasable PROM using the MP7 03 programmer system or for the Intel 4001 metal mask ROM ASSEMBLER ROMs MANUAL CONTROL POWER SUPPLY CHIP BANK 0 SIM4 01 TELETYPE SIM4 02 ASR 33 MEMORY Minimum Figure 1 1 Assembler Hardware Block Diagram DESCRIPTION Assembly Passes During pass 1 t
53. F PRE PUNCHED TAPE INPUT TRACE MODE IS INITIATED 0100101090 AFTER PROGRAM COUNTERS 2140101801 LOCATION COUNTER HAVE BEEN SET 3211101810 HAS ADVANCED TO R 0111 RDR INSTRUCTION IS 1119110020 20000 7 128 RESET TO 0 EXECUTED REOUEST 5101101000 0 0000 1 STACK IS 5 FOR DATA IS REPLIED SET TO 0 TO WITH 70111 ENTRY R 1 71110 FROM KEYBOARD se te BREAKPOINT IS LEFT AT 0 1041111100900 0 0000 105 10110010 9008 106311819188 0108 107118119000 0111 CONTENTS PAIR 4 DECIMAL 108 11110110 1 0011 1899310110000 1 0100 igid i OTO ACCUMULATOR BINARY 1122110110001 1 1110 113111110110 1111 1141101100081 2188 15 115 10110016 8 6008 4 116111110110 0 8000 2 117 10110010 9 0100 118 11111088 1 0011 119890011108 1 2011 197110110000 1 0011 3 108111110110 1 1001 109110110000 1 9011 9 CONTENTS OF REGISTER 1183002011010 1 0211 112810110001 1 1111 3 OPERATED ON DECIMAL 113311110110 1 1111 114310110001 1 0011 115 10110010 1 0000 116111110110 1000 TRACE MODE 117 10110010 9 0011 118111111009 1 0210 119 00011100 1 0010 FIRST BYTE 187319110888 1 1001 198 11110110 1 1100 OF INSTRUCTION 1899110110000 1 0010 110 00011018 1 2210 112 19110001 1 1111 113211110110 1 1111 114216110081 1 0910 115210110018 1 1000 116 11110110 0 1100 iua io B poio TO STOP TRACE MODE AT 116211111000 1 8901 POINT OTHER THAN
54. LD Load index register to Accumulator 1010 RRRR RRRR ACC The 4 bit content of the designated index register RRRR is loaded into the accumulator The previous contents of the accumulator are lost The 4 bit content of the index register and the carry link bit are unaffected Y rT M M M U Mnemonic OPR Symbolic Description XCH Exchange index register and accumlator 1011 RRRR ACC ACBR RRRR gt RRRR The 4 bit content of the designated index register is loaded into the accumulator The prior content of the accumulator is loaded into the designated register The carry link bit is unaffected MM ____________________________________ Mnemon c OPR Symbolic Description Example ADD Add index register to accumulator with carry 1000 RRRR RRRR ACC CY ACC CY The 4 bit content of the designated index register is added to the content of the accumulator with carry The result is stored in the accumlator The carry link is set to l if a sum greater than 1510 was generated to indicate a carry out otherwise the carry link is set to 0 The 4 bit content of the index register is un affected Augend Addend ACC CY RRRR a2 al co r3 r2 T rg CARRY gt C4 3 82 81 so lt SUM ACC 25 Mnemonic SUB
55. LEAST SIGNIFICANT BIT TO CARRY 109 XCH 9 4 RETURN ROTATED TO REG O0 LC TO 110 JCN CZ ROTRI 7 JUMP TO ROTRI IF CARRY ZERO 112 1 LOAD B LC ACCUMULATOR 113 RAR 7 ROTATE LEAST SIGNIFICANT BIT TO CARRY 114 XCH 1 4 RETURN ROTATED B TO REGet LC TO 115 ROTR2 2 LOAD PARTIAL RESULT C LC TO REGISTER 2 116 RAR 7 ROTATE CARRY INTO PARTIAL RESULT MSB 117 XCH 2 4 LOAD LC RETURN TO REGISTER 2 118 DAC 7 DECREMENT THE ACCUMULATOR LC 119 JCN ANZ 7 LOOP IF LC NON ZERO 121 BBL 0 7 RETURN 122 ROTR1 1 7 LOAD B LC TO REGISTER 1 193 RAR ROTATE 124 1 7 RETURN ROTATED TO 1 LC TO 125 CLC 4 CLEAR CARRY 126 JUN ROTR2 4 RETURN LOOP 128 CZ 2190 128sANZ 12 128 Figure 4 Pass 1 Listing BPPNPNPPPF BPPPPPPPNF 4 BNPNNPPPPF 8 BNPNNPPPNF 12 BNNNPPPPNF 16 104 104 BNNNNPPPPF 108 BNNNNPNNPF 112 BNPNNPPPNF 116 BNNNNPNNPF 124 BNPNNPPPNF 128 128 128 121 BNNPPPPPPF 5 BPNNPNPPPF 2 31BNNNPNPNPF 6 BPPNPNPPNF T BNNNPNPNPF 9 BPNNPNPPPF 13 BPNPPPPPPF BPPPPPPPPF 105 BNPNNPPNPF 1 1 BNPNNPPNPF L5 BPPPPPPPPF 106 BNNPNPNPPF 107 BNPNNPPPP 109 BNPNNPPPPF 110 BPPPNNPNPF BPNNNNPNPF 113 BNNNNPNNPF 114 BNPNNPPPNF 115 BNPNNPPNPF 117 BNPNNPPNPF 116 BNNNNNPPPF 119 BPPPNNNPPF 122 BNPNNPPPNF 123 BNNNNPNNPF 125 BNNNNPPPNF
56. O lines during X time A set of four RAM s is controlled by one of four command control lines from the CPU The address of a RAM chip register and character is stored in two index registers in the CPU and is transferred to the RAM during X X time when a RAM instruction is executed When the RAM output instr ction is received by the CPU the content of the CPU accumulator is transferred to the four RAM output lines The CPU RAM s and ROM s can be controlled by an external RESET line While RESET is activated the contents of the registers and flip flops are cleared After RESET the CPU will start from address O and CM is selected The interconnection of the MCS 4 system is shown in Figure 1 expanded configureation is shown The minimum system consists of one CPU 4004 and one ROM 4001 C MCS 4 Logic Definitions The MCS 4 devices operate with negative Logic Logic 1 is defined as the low voltage negative voltage Level and Logic 0 is defined as the high voltage Level Vgg This definition will be used throughout the manual D Basic System Timing For the correct operation of the system two non overlapping clock phases gt 0 must be externally supplied to the 4001 4002 and 4004 1 The 4004 will generate a SYNC signal every 8 clock periods and will send it to the 4001 s and 4002 s The SYNC signal marks the beginning of each instruction cycle The 4001 s and 4002 s will then generate interna
57. PROGRAMMING MP7 03 PIN Ag OUT DEVICE UNDER TEST 56 Ai 58 FUNCTION FUNCTION pP e 7 Ds CHIP SELECT OUT SN7407N LED PROGRAM OUT MV TUB OUT MONSANTO OUT OUT DEVICE UNDER TEST OUT Vpp OUT 4 62 OUT lt This is simple module that be built in the laboratory to interconnect the MP7 03 and the SIM4 02 The complete interconnection between the SIM4 02 and the MP7 03 is provided by the MCB4 20 system interface and control module Figure 29 MP7 03 SIM4 02 PROM Programming System 92 422 Cle e 8 224 225 ca yo 224 I C 12 236 C239 HO 240 241 Deste 247 O E45 Q 248 QC lt s OfRe2 O e QX 52 6 OX 58 0 O G lt 55 DO 7 03 R56 SOO es K 2570 Bere P P 3 ae 4 7 T qe h 4 2 0 Q 2 O O E pf o p 1 IV Fo i Solder Connector P N 225 23621 101 R PN K J HF ED CB AZ Y X W V UT S RP N ML E DC B A Amphenol Wirewrap Connector P N 261 15636 2 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41
58. ROM s AND RAM s BY ROM s AND RAM s Figure 4 Operation of the Command Control Lines Following is a detailed explanation of each step 1 Prior to execution of the DCL instruction the desired CM RAM code must be stored in the accumulator for example through an LDM instruction 2 During DCL the CM RAM code is transferred from the accumu lator to the command control register in the CPU CM RAM line is then activated selecting RAM bank during the next instruction which would be an SRC The CM RAM code remains in the command control register until a new DCL instruction is received Each time a new SRC instruction is executed it will operate on the same RAM bank This allows all RAM and I O instructions to be executed within the same RAM bank without the necessity of executing another DCL instruction each time DCL does not affect CM ROM Only the RAM on the designated command line will latch the SRC If up to 4 RAM chips are used in a system it is convenient to arrange them in a bank controlled by CM RAM This is because CM RAM is automatically selected after the appli cation of at least one RESET usually at start up time In this case DCL is unnecessary and Step 1 amp 2 are omitted 14 3 4 The SRC instruction specified an index register pair in the CPU whose content s an 8 bit address this 8 bit address has previously been stored in the register pair used to select a RAM chip regist
59. SYSTEMS Two number radices standard with the hardware simulation program binary decimal Index register values gram counter and instruction location values chip numbers and some pointers are handled in decimal for convenience ROM instructions the accumulator value and one bit indicators are handled in binary Any input number may be entered in either radix by prefixing it with a suitable indentifier D for decimal B for binary regardless of the expectations of the program Unless so identified however all input should be in the radix used in the corresponding typeout To facilitate working with program tapes in the format the hardware simulation program will accept binary num bers coded either as strings of ones and zeroes or as strings of P s and N s where the letter P is interpreted as a zero and the letter N is interpreted as a one All input numbers are right justified into the receiving register or field If the number is smaller than the receiving field leading zeroes are implied as necessary If the number is larger than the receiving field the excess bits are lost from the most significant end of the number Thus if it is attempted to load an index register with the value 20 the result will be 4 in the register This may be used to advantage in the event of an inadvertant error typein by typing in as many zeroes as there are bits in the receiving field then re typing
60. THE ACCUMULATOR 0007 00226 WRR WRITE ACCUMULATOR TO ROM OUTPUT PORT 0008 00025 JCN TI 3 JUMP PAST SCH IF RESULT TOO BIG 00011 0010 00180 XCH R4 SAVE RESULT IF NOT TOO BIG NOW REPEAT FOR 2ND HIGHEST BIT 0011 00212 LDM 4 LOAD ACCUMULATOR WITH 0100 0012 00132 ADD R4 ADD RESULT OF PREVIOUS TEST 0013 00226 WRR WRITE TO ROM OUTPUT PORT 0014 00025 JCN TI 3 JUMP PAST XCH IF RESULT TOO BIG 00017 0016 00180 XCH R4 SAVE CURRENT RESULT IF NOT TOO BIG REPEAT PROCEDURE FOR LAST TWO BITS OF THIS PORT 0017 11210 LDM 2 LOAD ACCUMULATOR WITH 0010 0018 00132 ADD R4 0019 00226 WRR 0020 00025 JCN TI 3 00023 0022 00180 XCH R4 0023 00209 LDM 1 LOAD ACCUMULATOR WITH 0001 0024 00132 ADD R4 0025 00226 WRR 0026 00025 JCN TI 3 00029 0028 00180 XCH R4 NOW WRITE FINAL RESULT TO ROM PORT 0029 00164 LD R4 LOAD FINAL RESULT TO ACCUMULATOR 0030 00226 WRR WRITE TO ROM OUTPUT PORT NEXT MOVE THESE 4 BITS TO R5 AND CLEAR R4 AND CLEAR R4 FOR NEXT PASS NOTE R5 INITIALLY CONTAINED ZERO 0031 00181 XCH R5 ACCUMULATOR TO R5 R5 TO ACCUMULATOR 0032 00180 XCH R4 CLEARS R4 IF END OF FIRST PASS 0033 00096 INC RO PREPARE FOR SELECTION OF NEXT ROM PORT 0034 00113 ISZ RI RETURN FOR SECOND PASS AFTER PASS 1 00004 AFTER PASS 2 PROGRAM CONTINUES PAST THIS POINT HIGH ORDER BITS OF RESULT WILL BE IN R4 LOW ORDER BITS IN R5 Program for Converter Using DAC and MCS 4 49 E MCS 4 SOFTWARE AND FIRMWARE LIBRARY
61. The MCS 4 simulator program SIM allows the user to simulate exe cution of programs which have been assembled by the assembler ASF4 ASF4 generates a file ROMAR DAT containing a packed image of the read only memory contents ROMAR DAT is read by SIM as an input Other files in the same format may be read prior to ROMAR DAT Each successive file overlays the data of preceeding files except where zeroes NOP s occur in the new file See below To run the simulator after having assembled a program type RUN 51 40 After typing a header message the simulator types FOR INSTRUCTION LIST TYPE Q If the user types the letter Q followed by a carriage return the program responds by typing a list of recognized commands The simulator indicates it is ready for input commands by typing an asterisk at the left side of the teletype page A command to the simulator consists of a letter or a letter followed by a 1 to 5 digit number The letter must be the first character typed Each letter corresponds to a different command Commands allow setting a starting address or a break point initializing a trace mode or interrogating registers The following commands are recognized by SIM4 An Set the program counter of the simulated MCS 4 to n and then return to command mode Bn Set the break point at n and return to command mode Call subroutine starting at ROM address n Continue cution until the subroutine exits with
62. and or alter the contents of the subroutine stack pointer The current loca tion counter is the one pointed to by this pointer This pointer is incremented by JMS instructions and decremented by BBL instructions Location Counter This directive may be used to display and or alter the contents of the current location counter Note that altering the value of the stack pointer will cause a different register to be current location counter Examine Everything This directive combines the display functions of the C A S L R and X directives All four program counters in the stack are displayed No modification is possible RAM ROM selection This directive may be used to display and or modify the simulated memory chip location selection A space or comma after the R types out an 11 bit binary number of which the most significant 3 bits represent the command line selection effected by the last DCL instruction and the least significant 8 bits represent the contents of the index pair as last used by an SRC instruction Breakpoint This directive may be used to display and or modify the contents of the breakpoint register The simulated execution will always be interrupted before processing the instruction pointed to by the breakpoint If the breakpoint points to the second byte of a two byte instruction no breakpoint action will occur during instruction simulation When This directive may be used to display and or alter the contents of the sim
63. be Do Di Us 03 To 4004 4001 5 TTY iM 3 4 8234 39 13 15 19 n S UNLESS OTHERWISE SPECIFIED ALL DIODES ARE 1 914 ALL TRANSISTOR ARE EN2907 RESISTOR VALUES ARE IN OHMS AW 5 Figure 16 Detail Drawing 4001 ROM Simulator Using 1701 1702 as Used on Both the SIM4 01 SIM4 02 Boards 62 63 D SIM4 01 Prototype System 4004 CPU COMMAND LINES TO RAM RAMo AM 402 1 4 OUTPUT Raw EI gt Il ROM INPUT PORTS BUFFERS AND 4 1702 ROM 1 ARRAY ADDR REG PORT L es I RAM OUTPUT PORT RAM 4002 PORT RAM OUTPUT DM PORT DATA 1 2 BUS MCS 4 System Using 1701 PROM i s 5 3 t 3 p TEST R IFEST RESET rry ECENLRATOR INTERFACE CLOCK GENERATOR ae m DETAIL SCHEMATIC 63 252 2 2 2 Figure 17 SIM4 01 System Block Diagram v v 2009 loo P E 5 22 n 240 EM 2901 3014 240 an 2901 TWO PHASE CLOCK 470 GENERATOR 5 6 51 E lt 15 14 dar 53 2 1o ES 4 1 9 5 So Pf 5 5 5 EM 2907 TEST TEST ANO RESET SIGNAL GENERATOR TO 4OO7 BAM CHIPI ouTPuT O TTY IN ITY KOD 14914 6 2K i0 FACTORY SELECTED 10 2N2907 390 n TO 4004 TO 4002 ZAM CHIP O TO 4002 CHIP
64. bits of display Data enable control switch which enables the MP7 03 output buffer A PROM selector switch which facilitates addition of a select function on the MP7 03 board for future use Two momentary pushbutton switches which drive the test and reset input lines on the SIM4 01 board Two transformers 115Vrms capacitors fuse holder and AC input jack wired to develop a raw supply and filtering for development of the programming voltage control switch for disabling the programming voltage 13 Input jacks for applying externally supplied 5V DC and 10V DC to the assembly Note Internal supplies are not included The setup for the PROM programming application requires an MP7 03 rear and a SIM4 01 board installed in the MCB4 10 Also shown are flat cables interfaced via two 16 pin DIP sockets to the system MCB4 10 MP7 03 SIM4 01 System 121 1 Micro Processor System When the MCB4 10 is used as a micro processor its features such as the display for the output ports and input ports may be utilized at the discretion of the user As an example consider the testing of SIM4 01 boards loaded with a PROM 1702 con taining the following program read ROM port and ROM port 1 add the two values and store the result at RAM ports 0 and 1 The test could be implemented by connecting 8 switches to the ROM input socket The actual switch circuit would consist of a single pole double throw switch wi
65. course is to write the program using the MCS 4 instruction set The result may be as shown in Figure B 1 FOUR BIT AND ROUTINE START FIM 7 LOAD ROM PORT ADDRESS SRC SEND PORT ADDRESS RDR 7 READ INPUT XCH TO REGISTER INC 8 LOAD ROM PORT 1 ADDRESS SRC SEND ROM PORT ADDRESS RDR READ INPUT B XCH 1 B TO REGISTER 1 JMS AND EXECUTE XCH 2 LOAD RESULT WMP STORE AT MEMORY PORT 0 JUN START RESTART NOP 2104 AND SUBROUTINE AND CLB 7 CLEAR ACCUMULATOR AND CARRY XCH 2 CLEAR REGISTER 2 LDM 4 LOAD LOOP COUNT LC XCH 9 LOAD LC TO REGISTER 0 RAR ROTATE LEAST SIGNIFICANT BIT TO CARRY XCH RETURN ROTATED TO REG LC TO JCN CZ ROTRI JUMP TO IF CARRY ZERO XCH 1 LOAD B LC TO ACCUMULATOR RAR ROTATE LEAST SIGNIFICANT BIT TO CARRY XCH 1 RETURN ROTATED B TO REGels LC TO ROTR2 XCH 2 LOAD PARTIAL RESULT C LC TO REGISTER 2 RAR ROTATE CARRY INTO PARTIAL RESULT MSB XCH 2 4 LOAD LC RETURN C TO REGISTER 2 DAC DECREMENT THE ACCUMULATOR LC JCN ANZ AND 3 LOOP IF LC NON ZERO BBL 0 RETURN ROTR1 1 7 LOAD LC REGISTER 1 ROTATE XCH 1 RETURN ROTATED B TO REG is LC CLC CLEAR CARRY JUN ROTR2 RETURN TO LOOP CZ 10 ANZ 12 Figure 1 Source Listing Figure B 1 was transcribed from a handwritten copy to a teletype print out and punched paper tape
66. directive If the first character after the O is a space or comma the current values are typed out Then or immediately after the three parameters separated by commas or spaces are required If any of the three parameters is omitted or if a RETURN is typed instead of the first parameter the current values will be unchanged r is the decimal RAM register number 0 63 which is used as the lowest in the black allocated to ROM The simulation program has no way of preventing the test program from accessing RAM loca tions allocated to simulated ROM so the user must use care in selecting a value for this parameter which will reduce the likelihood of improper access If r is greater than 63 the previous value is used s is the starting address of the ROM segment to be simulated Any attempt to execute an instruction with an address less than this number will result in an out of bounds interrupt e is the decimal ending address of the ROM segment to be simulated Any program access to ROM locations greater than this address will result i in an GUEOTDOUIHS interrupt This directive clears the option word to zeroes Zero This directive simulates the hardware reset function and clears to zero all simulated registers counters and all RAMs not allocated to program The O directive executes a Z each time the parameters are changed Input This directive accepts a sequence of binary and stores them in consecutive simulated ROM locations begin
67. hy ORIENT MARKETING HEADQUARTERS ORIENT DISTRIBUTORS JAPAN JAPAN Y Magami Pan Electron Inc Intel Japan 045 471 8321 Telex 781 4773 Han Ei 2nd Bldg 1 1 Shinjuku Shinjuku Ku 03 403 4747 Telex 781 28426 Tokyo 160 Yokohama 172 DISTRIBUTORS WEST ARIZONA Hamilton Avnet Electronics 1739 N 28th Avenue 602 269 1391 Phoenix 85009 Cramer Arizona 2816 N 16th Street 602 263 1112 Phoenix 85006 CALIFORNIA Hamilton Avnet Electronics 340 E Middlefield Road 415 961 7000 Mountain View 94041 Cramer San Francisco 695 Veterans Bivd 415 365 4000 Redwood City 94063 Hamilton Electro Sales 10912 W Washington Blvd 213 870 7171 Culver City 90230 Cramer Los Angeles 17201 Daimler Street 714 979 3000 Irvine 92705 Hamilton Avnet Electronics 8817 Complex Drive 714 279 2421 San Diego 92123 Cramer San Diego 7719 Convoy Court 714 279 6300 San Diego 92111 COLORADO Cramer Denver 5465 E Evans Place at Hudson 303 758 2100 Denver 80222 Hamilton Avnet Electronics 5921 N Broadway 303 534 1212 Denver 80216 NEW MEXICO Crarner New Mexico 137 Vermont N E 505 265 5767 Albuquerque 87108 OREGON Almac Stroum Electronics 8888 S W Canyon Road 503 292 3534 Portland 97225 UTAH Cramer Utah 391 W 2500 South 801 487 3681 Salt Lake City 84115 Hamilton Avnet Electronics 647 W Billinis Road 801 262 8451 Salt Lake City 84115 WASHINGTON Almac Stroum Electronics
68. in the stack This stack operates as follows 1 Each time a JMS is executed all addresses saved in the stack are pushed down 1 level The last value of the program counter is loaded into the top of the stack the program counter value corres ponds to the instruction immediately following the JMS 2 The BBL instruction raises every entry the stack one level with the top value in the stack entering the program counter In the example shown if the RAM register to be transferred to the dis play is different in different parts of the program the FIM which selects the RAM register should not be made part of the subroutine The subroutine would then include the three FIM instructions followed by the main loop and terminated by the BBL To display any register from any point in the program the programmer need use only 4 bytes of ROM FIM JMS The FIM selects the register and the JMS calls the subroutine Example 7 Storing and Fetching a floating point decimal number in the 4002 RAM How to use the Status and Main Memory Char acters in the 4002 RAM 4002 RAM has 4 registers each with twenty 4 bit characters sub divided into 16 main memory characters and 4 status characters 320 bits total Each register is capable of storing a 20 digit unsigned fixed point binary coded decimal BCD number A more practical usage for the register is the storage of a signed floating point BCD number having a 16 digit mantissa
69. is estimated to range from 2096 to 30 Since the micro computers are programmed by Intel PROMs Staid can produce point of sale terminals for the other types of businesses that have different requirements without redesign They simply change the PROMs to make the terminal perform according to the new cus tomer s requirements Obviously this saves a lot of money and enables them to deliver sys tems soon after receipt of order 170 Action Communication Systems of Dallas used Intel micro computers as front end processors in this high speed dial up communications con troller built for The Bekins Company Action adopted Intel micro computers in order to save both development time and system cost The Bekins system was fully developed and de livered only 90 days after Action decided to use Intel micro computers And Action estimates they saved about 10 000 in over all cost The Bekins controller located in Glendale California is the heart of a nationwide multi terminal system that carries administrative mes sages financial data shipping notices and cus tomer inquiries A micro computer on each of fives lines puts messages in a binary synchro nous format checks for errors and signals for re transmission when an error is detected Action used Intel s standard SIM4 02 micro computer boards in the system and did the final programming with Intel s electrically pro grammed PROMs Intel s Micro Computer Sys te
70. of the line and is followed by a comma Figure 1 below shows examples of labelled and unlabelled instructions Addresses as used with the JUN ISZ or JCN instructions and data as used with the FIM instruction can refer to these labels Labels attached to double word instructions always refer to the address of the first word Acceptable forms for use as addresses in this assembler are a numeric value a label or a label plus or minus a numeric value However when the form label plus or minus a numeric value is used the numeric value corresponds to the number of bytes displaced from the label not the number of instructions Thus one must remember which instructions occupy one byte and which occupy two bytes when using this displaced form The form plus or minus a numeric value refers to a displacement equal to the numeric value from the current address For more detailed descriptions of the functions of each of the instructions of the MCS 4 instruction set the user is referred to the MCS 4 Micro Computer Set User s Manual Pseudo Operators A number of pseudo operations are available in the MCS 4 assembler system For example the number system used with the MCS 4 assem bler is initially decimal However the user may change the number system to be used by inserting one of the three pseudo operators B for binary O letter O for octal D for decimal For example the pseudo operator B will signal the assembler to interp
71. pulses must be generated perhaps to drive the clock line of a 4003 port expander Let us assume that RAM 3 is to be used The high order 2 bits of data sent out at X2 time during an SRC instruction selects the RAM chip Hence 1100 binary equivalent of 12 is required at X2 to select RAM 3 Since we must select the port on RAM 3 we will require FIM 0 12 0 SRC 0 This pair of instructions sets up the desired port for use generate the clock pulses we must alternately write a 1 and an O into the appro priate port bit Let us assume that we will only use the high order bit of the port on RAM 3 and that it is initially set at zero so that the program does not have to reset it Furthermore let us assume that we do not care about the other three bits of the port 34 First let us set the accumulator to 0 LDM O Set accumulator to 0 We may then complement the high order bit of the accumulator by the sequence RAL Rotate left accumulator and carry CMC Complement carry RAR Rotate right accumulator and carry which achieves the operation by shifting the bit into the carry flip flop complementing it and shifting it back An alternate way to complement the high order bit is to add 8 binary 1000 to the accumulator We may set the contents of one register say register 15 to 8 by the sequence 8 Load data DDDD 1000 the accumulator XCH 15 Exchange contents of index register 15 and accumulator LDM
72. the MCS 4 Micro Computer Set C Features of the MCS 4 MCS 4 System Description A General Description B Basic System Operation C MCS 4 Logic Definitions D Basic System Timing 4 Bit Central Processor Unit CPU 4004 A Description B CPU Instruction Set Format Index Register Organization and Operation of the Address Register and Command Lines 1 Instruction Set Format 2 Index Register Organization 3 Operation of the Address Register 4 Operation of the Command Lines and the SRC Command C Basic Instruction Set 4001 256 x 8 Mask Programmable ROM and 4 Bit 1 Port 4002 320 Bit RAM and 4 Bit Output Port 4003 10 Bit Serial In Parallel Out Serial Out Shift Register Detailed Instruction Repertoire of the MCS 4 Instruction Format Symbols and Abbreviations Format for Describing Each Instruction One word Machine Instructions Two word Machine Instructions Input Output and RAM Instructions Accumulator Group Instructions An Introduction to Programming the MCS 4 Programming Examples A MCS 4 Program Routine Format Notes B 16 Digit Decimal Addition Routine C BCD to Binary Conversion D A D Converter Using DAC with MCS 4 E MCS 4 Software and Firmware Library Interface Design for the MCS 4 System A General Discussion B Keyboards C Display D Teletype Interface SIM4 01 SIM4 02 Prototyping System A General System Description B SIM4 01 SIM4 02 Specifications C MCS 4 Standard M
73. the following program read ROM port 0 and ROM port 1 add the two values and store the result at RAM ports 0 and 1 The test could be implemented by connecting eight switches to the ROM input socket The actual switch circuit would consist of a single pole double throw switch wired with one pole to ground and the wiper wired to the appropriate socket connector pin in accordance with the MCB4 20 schematic GND on input port equals a logic 1 The SIM4 02 is then inserted into the SIM4 02 connector and a bench supply connected to the 5V DC and 10V DC input jacks The actual test may now performed The DC power switch is turned on and the reset button is depressed clearing the system s memories and registers The program begins to execute The result appears at the LED display and may be verified for correctness The LED displays of interest are identified on the system s printed circuit board as OUTPUT PORTS RAM 0 RAM 1 BITS 0 1 2 and 3 2 Programming System Consider the actual programming in the hardware sense of the 1702A PROM in the example above The system can perform this function with the addition of an MP7 03 board inserted into the MP7 03 connector An automatic programming sys tem which allows data entry from a keyboard or papertape automatic verification listing of ROM contents and hands off programming is provided by the further addition of a SIM4 02 board with three pre programmed PROMs A0540 A0541
74. the line number or address may be off by one or two positions After typing the error message and the offending line of code the program prints a star After the star appears the user may type in a corrected line of code if he wishes This corrected line will be used by the assembler when generating the output listing Error messages in most cases appear before the listing is generated The most common types of errors are invalid characters within the input record invalid mnemonics or modifiers such as pair designators condition codes etc the use of incorrect or undefined labels or illegal off page references or the use of numbers which are invalid in the number system chosen Once the assembler has completed its assembly and generated a listing the assembler will type a message requesting whether or not a symbol or label table is required The user should 158 type a Y N immediately following the message and then the carriage return If a symbol table has been chosen it will be output on the user teletype The numeric value assigned to each label is also output with the symbol table The number system to be used for this numeric output is requested prior to typing the symbol table After the symbol table has been typed the assembler will type the message 1601 OUTPUT Y N This message requests whether the user wishes to generate tapes of a form compatible with pro gramming 1601 1602 1701 or 1702 field prog
75. the location of the lower address or the lower data fetched from the ROM SINGLE REGISTER ADDRESSING REGISTER PAIR ADDRESSING REGISTER NUMBER REGISTER PAIR NUMBER Table 111 Index Register Organization 3 Operation of the Address Register Program Counter and Stack The address register contains four 12 bit registers one register is used as the program counter and stores the instruction address the other 3 registers make up the push down stack Initially any one of the 4 registers can be used as the program counter to store the instruction address In a typical sequence the program counter is incremented by 1 after the last address is sent out This new address then becomes the effective address If a JMS Jump to Subroutine instruction is received by the CPU the program control is transferred to the address called out in JMS instruction This address is stored in the register just above the old program counter which now saves the address of the next instruction to be executed following the last JMs 3 This return address becomes the effective address following the BBL Branch back and load instruction at the end of the subroutine 1 In this case the instruction is executed on the 4 bit content addressed by RRRR 2 In this case the instruction is executed on the 8 bit content addressed by RRRX where X is specified for each instruction 3 Since the JMS instruction is a 2 word instruction the old effective a
76. the number system chosen it will indicate an error To set the starting address for a group of instructions the group may be preceded by a define origin pseudo operator This pseudo operator takes the form of an asterisk followed by the numeric value of the desired address This numeric value follows the number sytem conventions described above Figure 2 shows how number systems pseudo operators and comments are used with the assembler Any statements following a slash are interpreted as comments They do not alter or affect the other instructions in the system A comment line may stand alone or a comment may be appended at the end of a line No end statement is necessary The end of the file signifies the end of the program D 1024 DECIMAL 1024 STRT LDM 1101B BINARY 1101 DECIMAL 13 FIM P1gg 100 REGISTERS 8 9 DATA 100 DECIMAL THE NEXT PSEUDO OPERATOR CHANGES THE NUMBER SYSTEM TO BINARY B LD 1100 REGISTER 12 XCH REGISTER 4 Figure 2 Example of Pseudo Operators and Comments 157 Running the Assembly Once the source file with the MCS 4 assembly language code has been prepared it may be assembled into MCS 4 binary code by running the assembler To perform this operation the user should make sure he is in PDP 10 monitor mode He then types RUN ASF4 The system will then indicate that the assembler program is being loaded Once execution of the assembly begins the program will type the fol
77. time sharing service or directly from Intel MCB4 10 System Interconnect and Controi Module This module provides control display and 1 interconnect capa bility for the SIM4 01 In addition it provides complete inter connection between the SIM4 01 and the MP7 03 To order the interconnect module only specify MCB4 10 MCB4 20 System Interconnect and Control Module This module provides control display and 1 interconnect eapa bility for the SIM4 02 In addition it provides complete inter connection between the SIM4 02 and the MP7 03 To order the interconnect module only specify MCB4 20 050 D PIN 1 IDENTIFICATION 174 9 0 Those instructions preceded by an asterisk 2 word instructions that occupy 2 successive locations in ROM MACHINE INSTRUCTIONS OPR MNEMONIC 03020 Do D4 D gt D4 Do DESCRIPTION OF OPERATION 0000 No operation 0001 C C4C4C Jump to ROM address 2 2 2 2 A4 A1 within the same 1727374 ROM that contains this JCN instruction if condition A2 A2 A2 A2 A1 Ay is true otherwise skip go to the next instruction in sequence 0010 RRRO Fetch immediate direct from ROM Data 02 01 to index register pair Dz D gt D3 05 D4 0 0 D4 location RRR 2 SRC 0010 R RR 1 Send register control Send the address contents of index register pair RRR m to ROM and R
78. timing the bit frames in teletype input and output the simulation program is provided with an option to perform subroutine calls and unconditional jumps to ROM page 0 directly returning to simulation mode upon return ROM page 0 contains subroutines to perform teletype reader and keyboard input 7 bits wide the parity bit is ignored teletype output 8 bits wide binary to decimal conversion and output 145 the typing of some specialized sequences of characters partial decimal to binary conversion on input and 6 bit teletype char acter input with control character checking A test program may use these subroutines to facilitate checkout of complex programs or the ROM may be included in the final program if teletype interface and the same ancillary routines are needed The following is a summary of the subroutines and their calling parameters NAME ADDRESS X FUNCTION KEY 120 11 15 This routine inputs one 7 bit character from the teletype keyboard and returns it left justified in index registers 14 and 15 Index registers 12 and 13 are cleared to zero The least significant bit of register 11 determines whether the character is echoed back 0 yes 1 no The carry is set if the character typed in is printable TTI 117 11 15 This routine inputs one 7 bit character from the teletype paper tape reader or keyboard the reader control is enabled and is otherwise exactly the same as KEY TXX 234 10 11 14 15 This routine examine
79. 0 0 B 1 0 2 0 3 0 C 0 0 C 1 0 C 2 0 C 3 0 D 0 0 D 1 0 D 2 0 D 3 Figure 19 SIM4 01 Complete Schematic PC 114 C Solder Connector P N 225 23621 101 R PN MLK J HF ED CB AZ Y X W V UT 5 RE EP N ML KJ HF E DC B A 71 69 67 65 63 61 59 57 55 53 51 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 139 7 5 3 Wirewrap Connector P N 261 15636 2 Wirewrap Connector P N VPBO1E36E00A1 72 70 68 66 64 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 108 6 4 2 coc Figure 20 Component Side of SIM4 01 Board Solder Connector P N 225 23621 101 456 7 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Amphenol 8 wi 222250020222 Wirewrap Connector P N 261 15636 2 2 4 6 Wirewrap Connector P N VPBO1E36E00A1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Figure 21 Pin Definition Reverse Side of SIM4 01 Board PIN NO 1 3 5 37 45 41 53 49 53 55 69 71 51 57 67 65 64 63 66 61 59 57 68 72 39 17 13 9 15 19 1l 7 35 29 27 21 33 31 25 23 26 24 10 12 32 28 30 22 16 18 20 14 O 70 62 60 58 56 54 52 50 48 46 44 42 40 38 36 34 Pin numbers are shown for wirewrap connector All inputs and outputs are designated with respect to negative logic SYMBOL 10V GND 5V TS TR 851
80. 0 Load 0000 to accumulator The first instruction loads the binary number 1000 into the accumulator and the second places the contents of the accumulator into register 15 Since the prior contents of register 15 are also placed in the accumula tor an LDM instruction is then executed to clear the accumulator Now the operation ADD 15 will add the binary value 1000 to the accumula tor because Register 15 contains the value 8 Note the difference in how the LDM and the XCH and ADD instructions utilize the second half of the instruction The LDM loads the accumu lator with the value carried by the instruction i e in binary code LDM 8 appears as 1101 1000 and loads the accumulator with 1000 How ever the ADD and XCH select a register and the contents of the regis ter are used as data That is ADD 8 would add the contents of register 8 to the accumulator not the value 8 To generate the sequence of 10 clock pulses one could repeat the following 4 instructions 10 times ADD 15 Add contents of register 15 1000 previously stored in the register to accumulator WMP Write the contents of the accumu gne pulse lator into the previously selected generated RAM output port ADD 15 WMP However this would take some 40 instructions The indexing operation available with the ISZ instruction allows a program loop to be repeated 10 times The ISZ instruction increments a selected register If the register initially contained
81. 018 80176 200064 02017 82172 00242 20188 00218 29183 00064 00017 00034 002202 92835 00216 00225 00064 20002 INADR IRAH FIN SUBROUT INES 919g 0192 0193 0195 0196 0197 9199 0202 2202 g204 0206 2208 0218 9212 9214 0215 0217 8219 0220 0222 SYMBOL DLY 02 DLYA DLYTO DUP ERROR 00238 OLYTO 02000 0928 00119 00192 00002 000400 00118 00192 00192 00034 000200 20936 22011 00114 00204 88115 00204 00116 00204 092289 00190 29117 002074 00192 20932 00004 00113 00220 09192 000982 00200 00064 00217 TLT DLYA TLA DLY22 TL2 TARLE 20220 40122 80215 00200 88198 02078 00157 LD 1 508 CLC JCN JUN 152 FIM SRC LDM WMP JCN LOM WMP LNM XCH LD 1 CLC XCH JCN JUN LD 1 IAC XCH JCN JUN FIM SRC LDM WMP JUN FIM NOP 152 152 BBL FIM FIM 152 152 152 JMS ISZ BBL FIM 152 BBL JMS JUN FIN INADR IRAH MODE NOCMP PGM02 8 INADR 14 MODE 1 6 T2 WAIT 2 12 14 3 13 C1 IRAH ROMAO 2 12 Ci FIN ROMAD P1 0 P1 8 START P3 0 7 TLT DL YA TL2 80183 00168 02176 00049 00155 00110 00099 LOAD ROM DATA SUB PROM DATA OUT L CLEAR CY JUMP IF DATA H NO COMP JUMP INADR IF DATA COMP Z INC PASS CTR JUMP MOD
82. 04 noz pop wav Ojo sno SEMIWA I 04 155 8 9 samy Ov YaCs n ru PANYO 29 3710 id aL wond 5540 cad ino urd tan l J umne 5 amp Saby nO Osxinmnon lt a sago Gas Gr ac Boasiews cw Salen L wo 1264 nari wea n es Anami 9 od 1206 dnom ca anami noa 6 zed voa 7 Woe 1204 Anant 1 raod doo aw o Ldw oda 27 1 The following table lists the indicators used in the 0544 PROM Duplicator Comparator Program to provide pertinent status control address data in and data out information Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank Bank 2 Bank Bank Bit 1 Bit 2 Bit 3 Bit 1 Bit 2 Bit 3 Bit Bit 1 Bit 2 Bit 3 Bit Bit 1 Bit 2 Bit 3 ROM 0 Bit ROM Z Bit 1 ROM 2 Bit 2 ROM 4 Bit 3 ROM 1 Bit ROM 1 Bit 1 ROM 1 Bit 2 ROM 1 Bit 3 ROM 2 ROM 2 Bit 1 ROM 2 Bit 2 ROM 2
83. 1 TO 4002 CHIP 2 TO 4002 RAM CHIP 3 8 Die 4004 2 TO 400 RAN CHIP TO 4002 CHIP I TO 4002 RAM CHIP 2 TO 4002 CHIP 3 TO 4002 ZAM CHIP O OUTPUT 26 N2907 ATTY 390 TTY RECEIVER TAPE READER CONTROL TTY TRANSMITTER J MCS 4 AND TELETYPE INTERFACE CIRCUITS Figure 18 SIM4 01 Clock Generator Test Signal Reset Generator and Teletype Interface Detail Drawings 65 eM CA lt gt CAr RAM gt 59 EMRAN m7 e kie om 3014 QS 2405 41 jns 02 f rer Sek D Ld uM Ato 224 4 87 14 0 9 48907 7 u E 2 e 22 24 69 sort 220 2 J gt 47 2 CM RAM 7400 42 38 9 stom R Ale 34 Po ty 5 2 RESET NOTES Ds RUS 2 7 72 aie 390 777 PRINTER NS 77 24 10 12 32 28 Jo 22 6 78 20 4 N A3 42707 12 QZ we 390 56 oz TAPE READER CONTROL TTY 200 10 1 Pin numbers are shown for wirewrap connector 2 All 1 0 pins are designated with respect to negative logic Resistor Factory Selected 3 5V pin 5 10V 1 GND pin 3 67 RO A 0 57 0 0 0 1 0 2 0 A 3 0
84. 15 0716 0717 0718 0719 0721 8723 8725 0727 9729 0731 0732 0734 0735 736 0737 97 39 9741 0743 0745 0747 97 49 9759 0751 0753 0755 9757 8759 0761 0763 8765 00034 00198 287 00178 00034 88197 62082 09178 00034 00160 80280 00178 00192 00481 00171 020434 20160 00087 00178 00034 00194 90980 80178 00222 00186 00044 20048 09220 00182 20045 02234 00245 40190 00426 00215 00034 02208 00080 00178 00066 00219 02234 00206 00080 00178 2919 00118 82205 00172 00248 00188 00122 00201 00034 00198 20080 00178 00034 00187 00080 40178 00127 00245 88228 00191 09088 00226 00080 88238 20066 00090 80834 70168 29280 00178 00034 29160 070280 00178 00066 00092 LISTR SECON ROTAT PRNTN NEXT2 1 and ROM Duplication and Verification Program A0544 Refer to the MCB4 20 description Appendix E for a description of this program s use NOP NOP JCN FIM FIM SRC LDM WMP INC SRC ROR XCH FIM FIM SRC TZ START WAIT FOR TEST P 192 SET PASS 4 PO D Z SET SRC RAM P SEND RAM 2 LOAD STARTLAMP BIT START LAMP ON 001 B Z SET SRC ROM 1 SEND ROM 1 1 READ MODE SELECT 15 STORE MODE SELECT R15 P6 CLEAR ROM ADR REG P 8 SET SRC ROM ROM ADR L Z SEND ROM 0 0 168 8928 0021 022 00 23 0024 0025 0026 00 28 0029
85. 15636 2 2 If the use of the 24 pin socket on the MP7 03 is not desired the pin connections for external socket are as follows r EXTERNAL SOCKET PROGRAMMING 7 03 PIN Ag OUT DEVICE UNDER TEST 56 58 60 62 Ds 64 CHIP SELECT OUT 66 PROGRAM OUT SN7407N woop 68 OUT T MONSANTO 70 OUT OUT DEVICE UNDER TEST 77 Vgg OUT 69 Vpp OUT 67 2 OUT This is a simple module that can be built in the laboratory to interconnect e the MP7 03 and the SIM4 01 The complete interconnection between the 51 4 01 and the 7 03 is provided by the MCB4 10 system interface and control module FUNCTION FUNCTION pP e Figure 28 MP7 03 SIM4 01 PROM Programming System 91 5V GND 10V DATA IN MP7 03 ROM PROGRAMMER DATA OUT TTY PRINTER A 10 39052 25 2 V RMS 1 0A TTY T2 KEYBOARD OR 2 P 8180 TAPE READER 9 1702 9 STANCOR 3000 uf 75 100 VDC 3900 17024 5 1 SIM4 02 Connector Wire wrap type Amphenot 86 pin connector P N 261 10043 2 2 MP7 03 Connectors a Solder lug type Amphenol 72 pin connector P N 225 23621 101 b Wire wrap type Amphenol Shown above 72 pin connector P N 261 15636 2 3 the use of the 24 pin socket on the MP7 03 is not desired the pin connections for external socket are as follows Oy uc EXTERNAL SOCKET
86. 2 9045 0342 0144 0167 0212 0320 0275 8844 00609 0120 0260 0120 0367 9361 0221 9030 01290 0271 0042 2015 9161 0936 0041 0352 0364 9341 0120 0300 0040 0000 0320 0262 0320 2263 0330 0264 0120 0271 0361 0041 0352 0364 0341 0366 0242 0366 8262 0243 8366 0263 0120 0300 0164 0056 0337 455 44 0000 DECIMAL BEGIN NEXT 7 TEST TTY KBD INPUTS ST TEST STI PROPERTY L DM FIM SRC LDM 0 0 lt 0 FIM SRC WRR INC 4 3 310 2 ISZ 73REP LDM 0 XCH 13 FIM 2 lt 48 JMS CLRRAM JMS CLC 1 CRL F JCN TZ3ST JMS3 SBRI FIM 0 313 152 SRC RDR CMA 1 TEST O lt JMS3 SBR2 FIM 0 30 LDM 0 XCH L DM XCH L DM XCH JMS CLC SRC RDR CMA WM P RAR LD 2 RAR XCH 2 LD 3 RAR XCH 3 3 SBRI lt JMS SBR2 ISZ 4 5 1 LDM 15 OF INTEL CORP SANTA CLARA CALIFORNIA PROGRAM APE CO20 4 14004 16 DIGIT ADDING MACHINE W TTY KBD DRIVER PROGRAMMER PHIL TAI APPLICATIONS ENGINEERING DATE OCTOBER 27 1971 PALL IV ASSEMBLER e 60830 SET RAM PORT TO 111118 IRCa 5 0 Z IRCe6202031RC72 10 NN 78 SET DIGIT CNTR IRCI3D0 0 IRCA3 3 j1R05 0 CLEAR RAM POSITION CARRIAGE IR 0 0 1R 1 13 1 0 1 0 2 0 IRC3220 4 8 READ DATA INPUT STORE DATA IN CARRY LOAD ACzIR C2 TRANSFERE BIT RESTO
87. 2 Off page reference by JCN or ISZ instruction operand Normally no recovery is possible and the source program must be rearranged and re assembled to correct the error OUTPUT TAPE The assembler generates a ROM programming tape in the BNPF format required by the MP7 02 programmer system when connected to the SIM4 system It may also be used as mask development on the 4001 ROM The output tape is preceeded and followed by 12 inches of nulls and has an average of four locations per line Each instruction is identified with the address in decimal followed by a colon for correlation with the pass 1 listing Extensive use of pseudo ops which generate no object code but which punch an address anyway and cancelled lines will cause the listing of the object code to pile up on the right margin but this will not adversely affect the operation of the ROM programming PROGRAMMING SUGGESTIONS Users of the Fortran program ASM4 will find it convenient to limit their programming habits in some of the following ways to enhance compatibility between the two assemblers 1 Names should not exceed five characters in length and should be constructed only of letters and digits 2 Standard condition names and register identifier names should not be used for any other purpose 3 Instruction mnemonics should not be used as names 4 Labels should be terminated by a comma space 5 Operand fields should be delimited by spaces 6 All numeric val
88. 200 88187 XCH 4 SAVE INDEX REG 4 0201 000280 JMS SBR1 DELAY ROUTINE 1 80164 0203 00082 JMS SBR2 DELAY ROUTINE 2 00171 8285 80117 152 5 ST9 NUMBER OF ROTATIONS 00218 0207 02105 9 NUMBER DIGITS 0208 00000 9209 0212 09909 0211 AJAGA 212 00000 0213 00114 IS2 2 ST NUMBER OF 4 BIT WORDS 29195 0215 29229 LDM 1 0216 20225 WMP 021 0192 BRL 0218 20220 579 LOM 12 12 0219 00183 XCH 7 C 7 212 0220 00180 XCH 4 RESTORE SAVED 0221 00119 5712 IS 7 112 80221 0223 00246 RAR 0224 20064 JUN 518 00199 CR LF ROUTINE 0226 000454 FIM P1 141 1 2 8 IR 3 213 CR 00141 0228 000780 JMS PRINT 20178 0230 0200234 LF FIM Pi 138 lRC2 28 18 3 10 LF 00138 0232 00080 JMS PRINT 00178 0234 00192 BBL ROUTINES FOR PROGRAM TELETYPE INPUT HANOLER 0235 02299 TTY LOM 1 g236 200432 FIM P 64 08064 0238 00033 SRC PO 2239 00225 WMP 240 20017 ST JCN ST WAIT FOR START BIT 29240 0242 00032 FIM P 64 SET RAM 1 ADDRESS 22064 8244 00933 SRC P SEND RAM ADDRESS 0245 2392808 LOM 0 0246 9225 WM P STOP READER 0247 02080 JMS 5882 00171 0249 02032 FIM 0 20020 8251 40033 SRC 0252 00234 RDR 0253 00244 CMA 0254 00225 WM P 8255 00080 JMS 5881 1 00164 0257 70034 FIM P1 9 RESET DATA LOCATION 922800 8259 49216 LDM 8 0
89. 204 fas inem wuwa 8 1294 WYJ 3 Dinya i 3 s T 4 6 z ROTG 195 z wayq Andino 1 1 ed 1304 Lneine Andino 13204 anano viva SRG 22 1 3 wi al Is o n D 4 4 tA z z s s tA s tf 2 4 i D el f aZ ay 9 3 AWS 0305Y gama HOD 2 T3 3 4 9 n y 2 9 n a 5 8 S SI S 18 OTTS Taps 719 18 2 3 4 2 Ax 5 5 5 4 3 i 2 4 o 4 3 i 3 Ls s h i ve Brn indico inar 09 125 sra oeaaoov IGM woa 399aic andiro yg coreg wou e ano ean Mano dno ving vica 1304 lt nea 1303 inaano wos 7 wo 1294 409 09 amnya voza Ol noad wed WOR ru 77494 lt o3 12o
90. 225 0226 0227 0230 0231 0232 0233 0234 0235 0236 0237 0240 0241 0242 0243 0244 0245 0246 0247 0250 0251 0252 0253 0254 0255 0256 0257 0260 0261 0262 0263 0264 0265 0266 0267 0270 0271 0272 0273 0274 0275 0276 0277 0300 0301 0302 0303 0304 8385 0306 0387 0310 0311 0312 0313 8314 9315 0316 0317 320 0321 0322 0323 0324 0325 0326 9327 6034 0223 0022 0233 0263 0333 0262 0320 0045 0344 0120 0307 0255 0370 9275 0172 0212 0100 0017 0320 0212 0042 0330 0128 0307 9172 0244 0044 0228 0120 0260 0100 0017 0320 0261 0320 0045 0340 0145 0161 0262 0300 0040 0000 0160 0273 0161 0273 0300 0040 0010 0160 9302 0161 0302 0300 0040 0020 0327 0041 0340 0141 0263 0041 0340 0141 9262 0041 0340 0050 0020 9042 9320 NNN NNN JCN 35 7 TEST FOR JCN CN SKIP Z TEST FOR CA 1 5 XCH 3 LDM 11 XCH 2 LDM SRC 2 WR lt JMS jPRINT SKIPs LD 13 DAC XCH 13 ISZ 10 AD2 JUN NEXT XXX LDM 0 XCH 10 1 FIM 1 lt 2216 IRC01 8 1RC 2 13 CX JMS 154 1030VFL1 FIM 2 lt 3 JMS CLRRAM JUN 3NEXT CLRRAMs LDM 0 XCH 1 CLEAR LDM 0 SRC 2 WRM INC 5 152 135 CLEAR BBL SUBROUTINE NN SBRI FIM 0 lt 0 7 IR 0 0 1 Q 547 L1 152 L1 ISZ 134 1 BBL SBR 2 FIM 0 lt 8 7 1 0 8 Les 152 01 2 275 152 131 2 BBL PRINT RO
91. 260 00180 XCH 4 0261 00080 ST1 JMS SBR2 5 6 MSEC DELAY 80171 0263 00241 CLC IT TREATS REG PAIR 1 2 3 0264 00433 SRC PA AS IF WERE 1 8 BIT SHIFT 0265 00234 ROR REGISTER TO INPUT DATA 0266 00244 2267 00205 WMP 0268 002246 RAR COMPLEMENT DATA TO TRUE STATE 0269 09162 LD 2 AND LINK INTO REG 2 HIORD WORD 0270 002 46 RAR 0271 00178 XCH 2 9272 00163 LD 3 THEN LINK REG 2 OVERFLOW TO 0273 00246 RAR 0274 00179 XCH 3 LORD WORD TO COMPLETE SHIFT 0275 00080 JMS SBR1 00164 0277 00116 152 4 11 8 DATA 8175 ACCEPTED 000 5 0279 02080 JMS 1 00164 9281 00209 LDM 1 0282 00225 WMP RE SUPPRESS TELETYPE 02835 09162 LD 2 INPUT COMPLETE NOW 0284 04245 RAL 0285 00241 CL C ELIMINATE PARITY BIT 0286 00246 RAR 287 00178 XCH 2 0288 00192 BBL EXIT WITH DATA INT PAIR 1 2 3 gt Z COMPARE ROUTINE ACCEPTS INPUT IN PAIR 3 1 IF COMPARE 0289 8298 0291 8292 8294 8295 8296 8297 8298 30 0521 8382 0504 8386 6387 03508 0309 03510 0511 0312 0313 0314 8315 0316 0317 0319 8320 0321 0322 0323 0324 0325 8326 2328 N 8329 0331 0333 0335 0337 0338 0339 8341 0343 8345 8347 8349 8351 0353 8355 2357 0359 8361 9363 8365 8367 9369 6378 6371 8372 373 8374 0375 8376 0377 0378 8388 8382 2384 8386 0388 166 00241 09183 99147 29028 000445 88241 29182 99146 90241 00028 00045 00192 00195 90032 egaga
92. 5 respectively The contents in the corresponding characters of the registers are added there is a carry it will be added to the next char acter The subtotal is stored back into RAM register Index register 6 is used as a 4 bit binary digit counter Every time the corresponding digits in the registers are added IR 6 is incremented by one the l6th digits are added IR 6 is reset back to zero Then the program proceeds to check for overflow i e to check whether the carry is 1 If the carry is 1 the program will print out 16 x s clear RAM register 0 and jump to location NEXT of the main program that calls for the ADD routine Otherwise the program will jump directly to location NEXT The following flow chart further clarifies the sequence of the program SPECIFY RAM i j k 20 ik i RAM CHIP j AND 3 j RAM REG SET RAM CHARACTER SET DIGIT COUNTER 4 6 9 4 BIT BINARY CONTR INDEX REGISTER I k RAM 3 STORE I IN RAM 4 k IR 6 IR 6 1 k k 1 YES PRINT X X INDICATION OF OVERFLOW AND CLEAR RA k JUMP TO ROM ADDRESS NEXT Figure 11 Flow Chart for 16 Digit Decimal Routine 44 0000 0001 0092 2003 0004 0005 2006 8007 0010 0011 0012 0013 0014 0015 0016 0017 0020 0021 0822 0023 0024 0025 0026 0027 0030 9931 0082 2833 0034 9835 8036 0037 0040 0841 00 42
93. 5811 Sixth Avenue South 206 763 2300 Seattle 98108 Cramer Seattle 5602 6th Avenue South 206 762 5755 Seattle 98108 Hamilton Avnet Electronics 2320 Sixth Avenue 206 624 5930 Seattle 98121 Mt Prospect 60056 Hamilton Avnet Electronics 3901 North 25th Avenue 312 678 6310 Schiller Park 60176 INDIANA Sheridan Assoc Inc 4165 Millersville Road Suite DI C7 317 542 0661 Indianapolis 46205 KANSAS Hamilton Avnet Electronics 3500 W 75th Street Suite 106 913 362 3250 Prairie Village 66208 MICHIGAN Sheridan Assoc Inc 33708 Grand River Avenue 313 477 3800 Farmington 48024 Cramer Detroit 13193 Wayne Road 313 425 7000 Livonia 48150 Hamilton Avnet Electronics 13150 Wayne Road 313 522 4700 Livonia 48150 MINNESOTA Cramer Minneapolis 8053 Bloomington Freeway Suite 105 612 881 8678 Bloomington 55420 Crarner Bonn 7275 Bush Lake Road 612 941 4860 Edina 55435 Hamilton Avnet Electronics 4940 Viking Drive 612 854 4800 Minneapolis 55431 Industrial Components Inc 4004 West 78th Street 612 927 9991 Minneapolis 55431 MISSOURI Sheridan Assoc Inc 110 South Highway 140 Suite 10 314 837 5200 Florissant 63033 Hamilton Electro Sales 392 Brookes Lane 314 731 1144 Hazelwood 63042 OKLAHOMA Cramer Tulsa 6336 East 13th Street 918 836 3371 Tulsa 7411 2 U S DISTRIBUTORS MID AMERICA ILLINOIS OHIO Cramer Chicago Cramer Tri States Inc 1911 South Busse Road 666 Re
94. 716 832 4271 Buffalo 14215 Addem 37 Pioneer 516 567 5900 Huntington Station L I 11746 800 Southgate Office Plaza 5001 West 78th Street 612 835 6722 Bloomington 55437 NEW YORK Continued Ossmann Components Sales Corp 280 Metro Park 716 442 3290 Rochester 14623 Ossmann Components Sales Corp 1911 Vestal Parkway E 607 785 9949 Vestal 13850 lt 5 Components Sales Corp 132 Pickard Building 315 454 4477 Syracuse 13211 Ossmann Components Sales Corp 411 Washington Avenue 914 338 5505 Kingston 12401 NORTH CAROLINA Barnhill and Associates 6030 Bellow Street 703 846 4624 Raleigh 27602 OHIO Sheridan Assoc Inc 10 Knollcrest Drive 513 761 5432 TWX 810 461 2670 Cincinnati 15237 Sheridan Assoc Inc 7800 Wall Street 216 524 8120 Cleveland 44125 Sheridan Assoc Inc Shiloh Bldg Suite 250 5045 North Main Street 513 277 8911 Dayton 45405 PENNSYLVANIA Vantage Sales Company 21 Bala Avenue 215 667 0990 Bala Cynwyd 19004 John Kitzrow 21 Bala Avenue 215 664 6636 Bala Cynwyd 19004 Sheridan Assoc Inc 4268 North Pike North Pike Pavilion 412 373 1070 Monroeville 15146 TENNESSEE Barnhitl and Associates 206 Chicashaw Drive 703 846 4624 Johnson City 37601 TEXAS Evans and McDowell Assoc 13333 N Central Expressway Room 180 214 238 7157 Daltas 75222 Evans and McDowell Assoc 8814 Triola Lane 713 777 1282 Houston 77036 VIRGINIA Barnhill and Assoc
95. 8 4009 are com pletely compatible with other members of the 5 4 family All activity is still under control of the 4004 CPU One set of 4008 4009 and several TTL decoders is sufficient to interface to 4k words of program mem ory sixteen four bit input ports and sixteen four bit output ports It should be noted that in any MCS 4 system the pro gram memory is distinct from the read write data storage 4002 RAM Using the 4008 4009 programs can now be stored and executed from RAM memory but this RAM memory is distinct from the 4002 read write data storage RAM program memory will be organized in eight bit words and 256 word pages just like the memory array inside the 4001 Any combination of PROM ROM and RAM will be referred to as program memor y The accompanying diagrams show the internal organiza tion of both the 4008 and 4009 The 4008 is the address latch chip which interfaces the 4004 to standard PROMs ROMs and used for program memory The 4008 latches the eight bit program address sent out by the CPU during A1 and A2 time During A3 time it latches the ROM chip num ber from the 4004 The eight bit program address is then presented at pins AO through A7 and the four bit chip number also referred to as page number is present ed at pins CO through C3 These four bits must be de coded externally and one page of program memory is selected
96. 852 TTY R1 TTY R2 TTY T1 TTY X1 TTY X2 81 821 Do Di 02 D3 SYNC CM RAM CM RAM2 CM RAM3 TEST RESET I 0 I A 1 I A 2 I A 3 I 2 0 I B 1 I B 2 I B 3 I C O I C 1 I c 2 I C 3 I D 0 I D 1 I D 2 I D 3 0 a 0 0 A 1 A 2 0 A 3 8 0 0 8 1 0 8 2 5 8 3 0 C 0 1 0 0 2 02 0 D D 022 0 3 O O O O OF O O O OF Ol O 800020 1 RO A 2 RO A 3 RO B 0 RO B 1 RO B 2 RO B 3 RO C 0 RO C 1 RO C 2 RO C 3 RO D 0 RO D 1 RO D 2 RO D 3 DESCRIPTION 10VDC POWER SUPPLY Vpp ov TTL GROUND 5VDC POWER SUPPLY Vcc AND Vss TEST SWITCH CONTROL NORMALLY OPEN TEST SWITCH CONTROL NORMALLY CLOSED RESET SWITCH CONTROL NORMALLY OPEN RESET SWITCH CONTROL NORMALLY CLOSED TELETYPE KEYBOARD or TAPE READER CONNECTION 1 TELETYPE KEYBOARD or TAPE READER CONNECTION 2 TELETYPE TAPE READER CONTROL TELETYPE PRINTER CONNECTION 1 TELETYPE PRINTER CONNECTION 2 PHASE 1 CLOCK PHASE 2 CLOCK DATA BUS 0 DATA BUS 1 DATA BUS 2 DATA BUS 3 MACHINE CYCLE SYCHRONIZATION SIGNAL RAM BANK 1 COMMAND LINE RAM BANK 2 COMMAND LINE RAM BANK 3 COMMAND LINE TEST SIGNAL USED IN CONJUNCTION WITH JCN INSTR RESET SIGNAL USED TO CLEAR THE SYSTEM MOS COMPATIBLE OUT ROM INPUT PORT ROM O ROM INPUT PORT ROM O ROM INPUT PORT ROM 0 ROM INPUT PORT ROM O ROM INPUT P
97. A2A2A 2 JOC 0 0 0 1 0010 Jump carry 5 A2 A2 A2 A2 A1 000 1 0100 Jump if accumulator equalt to 5 A2A2A2A 2 0001 1100 Jump if accumulator non zero 5 2 0 00 1 1100 Jump if accumulator non zero 5 136 INPUT OUTPUT AND RAM INSTRUCTIONS The RAM s ROM s operated on in the I O and RAM instructions have been previously selected by the last SRC instruction executed D gt D Do DESCRIPTION OF OPERATION Write the contents of the accumulator into the previously selected 0000 RAM main memory character Write the contents of the accumulator into the previously selected RAM output port Output Lines i Write the contents of the accumulator into the previously selected 010 ROM output port 1 Lines Write the contents of the accumulator into the previously selected half byte of read write program memory for use with 4008 4009 only Write the contents of the accumulator into the previously selected RAM status character O i Write the contents of the accumulator into the previously selected RAM status character 1 Write the contents of the accumulator into the previously selected Write the contents of the accumulator into the previously selected accumulator with borrow Read the previously selected RAM main memory character into the accumulator 1 O Lines accumulator with carry x Read the previously selecte
98. AM at X and time in the Instruction Cycle FIN 0011 RRRO Fetch indirect from ROM Send contents of index register pair location 0 out as an address Data fetched is placed into register pair location RRR Jump indirect Send contents of register pair RRR out as an address at A1 and A time in the Instruction Cycle JUN 0100 Jum iti p unconditional to ROM address A4 A5 A4 Ag 272 JMS 10 1 Jump to subroutine ROM address A2 A1 save old address Up 1 level 2 2 stack 0110 Increment contents of register RRRR 3 Increment contents of register RRRR Go ROM address A2 1 within the same that contains this 152 instruction if result 0 otherwise skip go to the next instruction in sequence Add contents of register RRRR to accumulator with carry a Subtract contents of register RRRR to accumulator with borrow Load contents of register RRRR to accumulator Exchange contents of index register RRRR and accumulator Branch back down 1 level in stack and load 0000 accumulator Load data DDDD to accumulator INPUT OUTPUT AND RAM INSTRUCTIONS The RAM s and ROM s operated on in the I O and RAM instructions have been previously selected by the last SRC instruction executed DESCRIPTION OF OPERATION Write the contents of the accumulator into the previously selected RAM mai
99. ATA L IP 2 CMA Z COMPLEMENT DATA ge 38 98 39 0048 0041 0042 0043 2844 0846 0047 0048 2249 0250 2851 8852 0054 0055 0057 9058 00260 0062 0063 0064 0065 0066 00 67 0068 0069 0071 ge 73 0074 9875 2876 0078 0080 0081 0082 0083 0084 0085 0086 0087 0089 0090 0091 0092 0094 0095 0097 0099 0101 0102 2193 0104 8106 0107 0108 9112 2112 8113 8114 0115 0117 0118 0120 0121 0122 0124 0126 0128 0129 0150 0131 2132 0133 0154 0135 0136 0137 0138 01 39 0140 0141 0142 0143 2144 9145 0147 29187 90096 206 33 00234 82244 88186 82832 8 64 82833 00240 82225 00242 82175 00246 00018 08278 80246 22218 00078 290246 00026 82871 88832 80232 299033 29171 80226 00096 00033 00170 29226 00064 00122 00832 0000 00033 002 40 00225 00064 82282 00032 00032 00033 00171 00226 00096 00033 80179 00226 00080 00190 00240 88175 00246 20018 800 99 90246 88818 00110 29064 12871 200432 00064 80033 00210 00225 00088 00200 00208 00225 20064 80122 000232 00064 00033 00212 00225 20280 00215 00208 82832 00064 00033 00225 20089 20190 00032 00032 07034 00128 00033 99234 00035 0 02 25 00185 20096 80212 88138 00178 00033 00234 802 35 00225 88184 00241 88171 00153 00228 00155 00241 MODE STOP OUP PGMA PGM22 COMP XCH 11 INC 8 SRC ROR CMA XCH FIM
100. BITS 2 3 SELECT BITS 4 7 SELECT RAM CHIP 1 OF 4 RAM REGISTER 1 OF 4 REGISTER CHARACTER 1 OF 16 AND CLRRAM ARE ADDRESS TAGS USED FOR RETURN POINT OF THIS ROUTINE CLRRAM AND PRINT ARE ROUTINES CALLED BY THIS PROGRAM C BCD to Binary Conversion The following program converts BCD numbers 255 to its binary equivalent In this program it is assumed that a 3 digit BCD number is previously stored in character 0 1 and 2 of register 0 in RAM chip by the main program Then this program proceeds as follows First it sets index registers 0 1 2 3 and 4 to zero 0000 index register 5 to 10 1010 and index register 6 to 14 1110 Then the conversion begins by transfering the least significant digit which is the content of character 0 in the RAM into index register 3 IR 3 No conversion is made on this digit since it has the same bit pattern as its binary representation Now recall that each unit value of the second digit of the BCD number which is the content of character 1 in the RAM has a value of 10 Hence the program continues as follows Transfer the second digit to the accumulator AC and examine whether the digit is zero If the digit is not zero the content of the AC is decreased by one i e the value of the second digit is decreased by one and the result is stored back into the same location in the RAM Then the content of index register 3 is transfered to AC and the content of index register 5 which is 10 is adde
101. C after receiving the of an I O instruction CM RAM activated at will decode the instruction If the instruction is WMP the data present on the data bus during X2 02 will set the output flip flops associated with the I O pins That information will be available until next WMP for peripheral devices control An external signal RESET when applied to the chip will cause a clear of all output and control static flip flops and will clear the RAM array To completely clear the memory RESET must be applied for at least 32 instruction cycles 256 clock periods to allow the internal refresh counter to scan the mem ory During RESET the data bus output buffers are inhibited floating condition Figure 7 shows the block organization of the 4002 The RAM array uses a dynamic cell therefore it must be periodically refreshed refresh counter scans the memory array and the memory content is refreshed during an idle portion of the sys tem cycle M and M5 An address multiplexer allows loading the content of either the refresh counter or the address regis ter into the decoder 22 The RAM control is composed of an SRC flip flop chip selection logic an instruction register instruction decoder and I O con trol logic This block controls the loading of the address register the status and main memory decoder switching the gen eration of memory timing the enable of the data bus input output buffers the RAM read write o
102. D Figure 1 Relay Circuit Alternate 117 MODE SWITCH Figure 3 Mode Switch Rear View 118 Figure 4 Terminal Block Figure 5 Current Source Resistor 119 ALTERNATE RELAY CIRCUIT SEE 4 SEE FIG 1 vio 20 ma ae ruc eoe ex EL d x ciem M e ee CONNECTOR PIN NUMBER 2 WHEELOCK 3002101 RECEIVE J2 4 1 11 8 NOTES UNLESS OTHERWISE SPECIFIED a CUSTOMER EXTERNAL counectionsS TEMS WITHIN DASHED LINES BEPZESENTS L pin TERMINAL STZIF 15441 Ben geo wa WR BL wuT 2 ul Full DUPLEX amp YEL SCURZENT SOLECE SEE Fla 5 2 POTTER BRUMFIELD RELAY NO 2vDC 2 5 e IA 15 SEE Fic 9 CUSTOMER BEQUIZES MODIFICATIONS IM IS INTERNAL MODIFICATION EC IS EXTERNAL CONNECTION MODE SWITCH MOUNT REED RELAY CAPACITOR CURRENT SOURCE RESISTOR POWER SUPPLY TERMINAL STRIP Figure 6 Schematic KEY BOARD PRINTER UNIT DISTRIBUTOR TRIP MAGNET ASSEMBLY VIEW TELETYPE MODEL 33TC Figure 7 Block Diagram 120 W amp T RED SEE 4 ae i d DierTei amp uToec TRIP MAGNET SEE Fla 2 COMM mr EA CM MES oc MODE SWITCH FRONT view see s APPENDIX E SYST
103. D FOR THE 1602 1702 DURING PROGRAMMING DATA OUT 5 DATA OUT 6 DATA OUT 7 DATA OUT 8 11 MSB cs IMPORTANT It should be noted that the PROM s are described in the data sheet with respect to positive logic high level p logic 1 On the other hand the MCS 4 system is defined in terms of negative logic low level n logic 1 As a result when 1602 1702 ROM s are being programmed to simulate the 4001 characters should be defined as P high level n logic 0 or an N low level n logic 1 For instance consider the instruction code for ADM one of the 45 instructions for the MCS 4 11101011 When entering this code to the programmer it should be typed BNNNPNPNNF This is the code that will be put into the 4001 when the final system is defined OPERATING THE PROGRAMMER The SIM4 is used as the micro computer controller for the programming It presents data and addresses to the PROM to be programmed and controls the programming pulse The following steps must be followed when program ming a PROM Place control ROMs A0540 A0541 A0543 in SIM4 board Turn on system power Turn on TTY to line position Reset system Insert PROM into 03 Load data from TTY and program PROM Remove PROM from MP7 03 To prevent programming of unwanted bits never turn power on or off while the PROM is in the MP7 03 ADO Pwd 84 OPERATING THE PROGRAMMER PROGRAMMING
104. Data in and CP can be simultaneous To avoid race conditions CP is internally delayed Fig 8 shows the block organization of the 4003 CLOCK POWER PULSE INPUT 16 ENABLE INPUT ON CLEAR DATA 15 SERIAL OUT 147 18V PARALLEL 22 I 110 BIT SHIFT REGISTER OUTPUTS STATIC CELL I PARALLEL OUTPUTS PARALLEL OUTPUTS 10 BIT PARALLEL OUTPUT BUFFER m Wes 7l Qo 0 Qs Os Ag Ag Figure 8 4003 Shift Register Block Diagram 23 VII DETAILED INSTRUCTION REPERTOIRE THE 4 A Instruction Format As previously discussed the MCS 4 micro computer set has two types of instruction a 1 word instruction with an 8 bit code and an execution time of 10 8 usec b 2 word instruction with a l6 bit code and an execution time of 21 6 psec Due to the time multiplexed operation of the system the 8 bit in struction is fetched 4 bits at a time on two successive clock periods The first 4 bit code is called OPR the second 4 bit code is called The instruction formats were illustrated in Tables I and II Symbols and Abbreviations The following Symbols and abbreviations will be used thorughout the next few sections the content of is transferred to ACC Accumulator 4 bit CY Carry link Flip Flop ACBR Accumulator Buffer Register 4 bit RRRR Index register address RRR Index register pair address Py Low order program counter Field 4 bi
105. E IF NOT SET SRC RAM 8 ERROR LAMP SEND RAM LOAD ERROR LAMP ON BIT ERROR LAMP ON 002 CONTINUE IF TEST PRESSED LOAD ERROR LAMP BIT ERROR LAMP OFF 822 RESET PASS CTR 4 LOAD PASS CTR LOAD ROM ADR L CLEAR CARRY INC ROM ADR L Z STORE NEW ROM ADR L JUMP INC ROM ADR H IF OVFL 7 JUMP ROM ADR DATA Z LOAD ROM ADR H AC Z INC ROM ADR H STORE NEW ROM ADR L LOAD FINISH LAMP BIT FINISH LAMP ON 7 DELAY TIME OUT 9 08MS DELAY A 517 5 DELAY 2 5 6SEC LOOP SET 11 00017 00202 00671 92217 22204 80192 00162 ROMAD START STOP TL2 TLA TLT WAIT INTEL MICRO COMPUTERS DATA COMMUNICATIONS PROCESSING POINT OF SALE TERMINALS Staid Inc of Casselberry Florida is using Intel micro computers to build advanced point of sale terminals for a large chain of cafeterias in the Southeast Operated by the cashier the ter minal automatically enters item prices totals items adds taxes prints a sales slip dispenses change adjusts the inventory of each item as it is sold and transmits all this information to cor porate headquarters It can handle 100 separate items and is expandable to accommodate 200 Staid says the Intel micro computer on only two PC cards does the work of about a dozen cards of random logic and increases estimated relia bility by an order of magnitude Cost reduction compared to random logic
106. EM INTERFACE AND CONTROL MODULES MCB4 10 The MCB4 10 is a completely assembled interconnect display and control switch module which eliminates all hand wiring associated with an MP7 03 SIM4 01 setup With the additions noted below it becomes self contained system featuring the following 1 2 3 Automatic PROM Programming with SIM4 01 PROM set A0540 A0541 A0543 MP7 03 power supplies TTY General Purpose Micro Processor with 1 and Display with SIM4 01 power supplies Test System for checkout of PROMs with SIM4 01 power supplies The MCB4 10 includes the following 1 2 3 o All interconnect circuitry necessary to implement the programming system described section XIII of the MCS 4 Users Manual Connectors for the SIM4 01 and MP7 03 boards A zero insertion force 24 pin socket for PROMs to be programmed Appropriate connections to the MP7 03 connector are provided Teletype receive conditioning circuit transmit source circuit punch and reader control interface circuits Access to these signals is provided by a 16 pin socket Control switches 2 and logic necessary for complementation of programmer input or output data Breakout and buffering of computer signals to open sockets for ease of access This includes 16 ROM outputs 16 ROM inputs and 16 RAM outputs SIM4 01 ROM and RAM port binary display using light emitting diodes This includes 32
107. ESIRED LIST NUMBERS amp CIRCLE CONNECTIONS ON SCHEMATIC For T2L compatibility on the 1 0 lines the supply icu should be Vop 10V 5 Vss 45V 5 b If non inverting input option is used 6 5 Volts maximum not TTL 114 4001 CUSTOM ROM TRUTH TABLE Customer P O No Chip No Date The customer truth pattern should be placed in the blue screen area The white section above the screen area will be used by Intel to verify the customer pattern Based on the particular customer pattern the characters should be written as a for a high level output n logic 0 negative logic 0 or for a low level output n logic 1 negative logic 71 INSTRUCTION INSTRUCTION INSTRUCTION OPR OPA Word OPR OPA Word OPR OPA 0 01 Number 96 03020 0 0300 00 Number 0 0 0 0 D 0 0 0 97 INTEL CORP 3065 Bowers Avenue Santa Clara California 95051 408 246 7501 115 4001 CUSTOM ROM TRUTH TABLE Customer P O No Chip No Date The customer truth pattern should be placed in the blue screen area The white section above the screen area will be used by Intel to verify the customer pattern Based on the particular customer pattern the characters should be written as a for a high level output n logic 0 negative logic 0 or an for a low level output n l
108. G EXAMPLE coNTROL PROGRAM FOR PROM PROGRAMMING Intel tapes A0540 A0541 A0543 Listings are provided for reference only and may be used as examples when developing your own programs 0890 04209 START LOM 1 SUPPRESS TTY 0091 00932 FIM P 00090 9093 90053 SRC PO 0004 00225 WMP SEND TO RAM PORT 0005 00080 STA1 JMS CRLF POSITION POINTER 02 26 8087 00082 JMS ST RECIELVE INPUT DATA 00244 9809 88038 P3 71866 5 18 7 0 20080 0011 90281 JMS COMPR 00033 0013 00028 JCN AN LISTN 00032 0015 80832 2 32 ZIR 0 z2 12 0 808 32 0017 00209 LOM 1 0018 00033 SRC PO 9919 80238 WR2 8020 00064 JUN STA2 00045 0022 00038 NEXT FIM P3 83 71866 5 IR 7 3 S 40083 0024 00081 JMS COMPR 00033 26 00420 JCN AZ STA2 00045 0028 00080 JMS ERROR 20135 0030 00064 JUN STA1 00005 0032 00038 LISTN FIM P3 76 18 6 4 18 7 12 L 00076 0034 20081 JMS COMPR 00033 0836 00028 JCN AN NEXT 88022 0058 00220 LOM 12 0039 00191 15 IR 15 15 0040 00032 FIM 32 2 18 1 0 02032 0042 00209 LDM 1 0043 00033 SRC 0044 00229 WR1 0045 00080 STA2 JMS CRLF 00226 9847 00222 LOM 14 ENTER ADDRESS 0048 08186 C 10 18410 214 0049 80221 ADRS2 LDM 13 28050 80185 9 IR 9 13 0051 00080 ADRS1 JMS ST 00240 0053 20080 JMS STORE 00140 0055 00121 152 9 ADRS1 00051 0057 40080 JMS CRLF 00226 0059 00122 152 10 ADRS2 00249 0061 020080 JMS LF 20230 0063 00080 J
109. G PASS DESCRIPTION Ki 1 Duplicate label The value assigned on this line supercedes the previous value for all subsequent references If typing in source text manually recovery may be effected by equating this label to its former value then selecting a new name to restart the line For example 25 ABCSRC2 Original Label 43 ABCD 25 Old Value Reassigned 43 1 ADM New Line Restarted 96 1 Name table overflow May occur on pass 2 if the source text differs from that used in pass 1 a procedure not recommended The label so flagged has not been added to the name table and any reference to it will be flagged as undefined on pass 2 No remedy is possible except to add more 4002 RAM up to the limit of 16 RAMs or to remake the source program with fewer labels 1072 Unrecognized instruction mnemonic One byte with op code of zero and four bit operand is assembled The line may be cancelled before the terminal delimiter of the operand and re typed with the corrected mnemonic 2 Undefined name in an operand field The entire operand is assembled as a zero value to facilitate correction of a PROM any remaining terms are not examined and may be incorporated _ into a second operand field Since this flag is issued only on pass 2 reference must be made to the corresponding line of the pass 1 listing to determine by conjecture the offending name Unless the error is patchable re assembly is normally required amp
110. H 3 97 8DBN INC 1 29033 SRC 28233 881 RDM 000222 JCN A2 882 22138 00248 DAC 88224 WRM 00241 00163 LD 3 20133 ADD 5 00179 XCH 3 20162 LD 2 80132 ADD 4 00178 2 00264 JUN BB1 00116 02036 832 FIM P2 120 1RC4226 18 5 24 22100 82118 IS2 6 BDBN 20114 00192 BBL 00034 ERROR FIM 191 IRC2 211 18539415 2 00191 000280 JMS PRINT 22178 80192 BBL 88632 STORE FIM PQ 11 18 0 0 IR 1 11 00011 00036 2 53 IR 4 3 18 5 5 720053 20038 P3 52 1 6 3 18 7 24 88852 82839 REP1 SRC 00233 RDM 88837 SRC P2 00224 WRM 00165 LD 5 20248 00181 XCH 5 00241 CLC 00167 LD 7 00248 DAC 00183 XCH 7 00241 CLC 00113 IS2 1 00146 020163 LO 3 00037 SRC 2 00224 WRM 00192 BRL TIMING SUBROUTINES 09932 5881 FIM 18 0 1 0 09000 00112 L1 152 11 547 MEMORY CYCLES 20166 00113 ISZ 111 22166 00192 BBL 29032 SBR2 FIM 8 IR 0 28 18 1 020928 80112 2 152 8 2 275 00173 88113 152 1 12 00173 20192 BBL PRINT ROUTINE 82832 PRINT FIM P 16 IR B21 IR 1 z0 00016 88215 LDM 7 00933 SRC 00224 WRM 20097 INC 1 00179 XCH 3 00033 SRC P 02224 WRM 80297 INC 1 18178 2 82833 SRC 00224 WRM 5 26040 FIM P4 16 ZIR 8 1 18 9 20 22216 000234 FIM P1 208 Z IR 2 213 1R 3 0 88208 20036 577 FIM P2 12 18 4 0 18 59212 62012 00041 SRC 4 20233 RDM 00225 5718 WMP AND PAIR 1 WILL OUTPUT A FAILS 0
111. H ENABLE 1 dir EN2907 D U T 6 8K I SN7486N a 62 M a x i2 PIN 16 100 330 PIN 21 1N914 D U T R32 DUT 6 8K pd 25 3 36 dud SN7486N 64 15 ME R87 DATA OUT 031 A4 L D U T CONTROL 330 PIN 20 qs DUT 6 8K 10 28 K lt 547486 577403 65 SN7486N 66 1N914 1N914 Q9 29 A 11 R68 2907 100 713 Q25 9 20 330 PIN19 R12 PIN 24 D U T Q10 1N4002 DATA R34 E as 38 PIN 7 6 8K D U T SN7486N 168 e R69 PROGRAM PULSE TIMING D 18 AR 330 PIN 18 D U T 45 5 5 R35 6 8K bo Mid R63 48 R39 SN7486N 2 20K 3 25 us nza 100 i 5 20K 3 0ms 80V 8 013 PIN 17 cs CR10 330 9 9 2 2 uF SZ 1N914 R65 R62 R26 DATAS D U T R91 R92 4 7K 10K 4 7K NS 15K 15K T 1 14 iC ud 7 5 c4 t 1K 27K ADDRESS DRIVER 6 104F 01 uF 1 0 uF 16 E jr e hs 5 6 14 4 4 9602 0 SN7406 SN7403 61 10 13 9 50 R38 5 5 R21 IK nda 27K DATA 6 PIN 9 CR11 42 D U T 2 Vop T SN7405 A1 61 2 R16 A3 47K DATA OUT 1 2 gt SN7403 5 3 A5 SN7405 sz R37 2 A6 11 100 5 A7 6 R23 DATA 7 V 470 44 PIN 10 z Mi D U T DATA OUT 8 cs Vec PROGRAM SN7405 IC 11 DEVICE TO BE PROGRAMMED SN7486 SN7403 5 1 100 6 SN7403 SN7405 NOTES Unless otherwi
112. ITIATE TTY SET DATA COUNTER DELAY FOR 2 75 msec READ DATA BIT SEND BACK INTO TTY 10 TTY RECEIVER DELAY FOR 5 5 msec DATA COUNTER 8 STORE 8 5 DATA IN INDEX 42 amp 3 Figure 14 Flow Chart for Teletype Interface __ Figure 15 MCS 4 amp Teletype Interface Circuits 54 0201 0002 0903 0204 0085 0206 0097 0010 0211 0212 0013 0014 0015 0016 0017 0020 0921 2222 2023 0024 0095 0026 8827 9030 0031 0032 8833 0034 0035 0036 0037 0040 0041 0042 0243 0044 0045 0046 8047 0050 0451 8952 0053 0854 0055 0056 0057 9260 0261 0062 0463 0064 0065 0066 0967 09070 0071 0972 0073 9074 0075 2076 BATT AL GY 0101 9102 0337 BEGIN 0240 02000 0041 0341 0361 0021 8286 0120 2265 0048 0015 0161 0014 0041 0352 0364 0341 0120 0074 0040 0200 0320 262 0320 0263 0330 0264 0120 0065 0361 0041 0352 0364 0341 0366 9242 0366 0262 0243 0366 0263 0120 2074 0164 0034 0337 0040 0000 0841 0341 0190 0006 0049 0000 01660 0067 0161 0067 0300 0240 0160 8876 0161 BATE 0300 ST TEST STi NN N N N SN 5 Lil SBR2 L2 7 KEYBOARD ROUTINE L DM FIM SRC CLC JCN 4 5 FIM ISZ SRC CMA WMP 4 5 FIM L DM XCH L X CH L DM XCH JMS CLC SRC RDR CMA WMP RA
113. M4 02 Hardware Simulator is a program written for the MCS 4 series Micro Computer System This program will provide interactive control over the debugging of other 5 4 programs The minimum configuration required is a SIM4 02 prototype card with three 4002 RAMs and a Teletype When fully stuffed with 16 RAMs test programs up to 512 bytes locations in length may be accomodated The hardware simulation program itself occupies nine full ROMs The Hardware Simulation Program has two basic functions 1 To simulate the execution of a test program tracing its progress and apprehending gross errors 2 To allow the user to dynamically interact with and or modify his test program in order to facilitate the debugging process These two functions are implemented by means of a set of directives or commands which the user types in at the teletype keyboard Some of the directives call for typeouts by the simulator program some of the directives signal the input of data or program modifications and some of the directives involve both typeouts and input response A directive is identified by a single letter of the alphabet except the arithmetic conversion directives and If the directive is associated with output only the typing or punching will commence immediately f input is allowed or re quired with the directive the simulation program will enable the paper tape reader control and wait for valid input data NUMBER
114. MCS 4 Assembler and Simulator Software Package Intel now offers an assembler and simulator software package to help develop programs for micro computer systems built from Intel s MCS 4 set of integrated computer circuits The software is written in general Fortran IV for the PDP 10 computer and may be adapted for most other computers by minor modifications The package consists of a simulating routine which enables the computer to simulate the operation of an MCS 4 micro computer and an assembly routine used primarily as an aid to programming the simulated micro computer See Appendix H for complete details The routines may be procured from Intel on paper tape or punched cards Alternatively designers may contract three nation wide computer time sharing services AL COM G E and Tymshare for access to the programs SIM4 Hardware Assembler The SIM4 hardware assembler is a program which translates a symbolic assembly language into bit patterns suitable for MCS 4 control storage programming It operates on the SIM4 01 or the SIM4 02 micro computer system with an ASR 33 teletype The assembler accepts input source text from the teletype keyboard or paper tape reader on each of two required passes A name table and source listing are created on the first pass On the second pass the source text is re read and a programming paper tape and associated listing are generated The programming tape is suitable for programming of the 1702 PROM
115. MS LF 00230 0065 00081 JMS ADDTN 00046 3 0067 00032 FIM P 90006 0069 00080 JMS DBIN FINAL ADDRESS 691 05 0071 00163 LD 3 0072 00230 WR2 CCO RCB CH 2 LORD 4 8175 0073 20162 LO 2 8074 00231 C 0 R 0 CH 3 HIORD 4 BITS 0075 00032 FIM 3 1R D 20 18 1 25 20003 0077 20080 JMS DBIN INITIAL ADDRESS 00105 9079 00163 LD 3 0080 00228 CCO RCB LORD 4 BITS 0081 00162 LD 2 0082 00229 WR1 1 10 0 4 8ITS 0083 20236 PRGMi FIM P2 Q IR 4 5 z 22000 0085 88832 FIM PO ADDRESS 1701 READ TO WRITE 00000 0087 60033 SRC 0088 09236 0089 02226 WRR 0090 00102 INC 4 0091 00237 01 0092 88837 SRC P2 0093 00226 WRR 0094 808 32 FIM 32 2 IR 1 20232 0096 00053 SRC P 0097 00237 RD1 0098 00246 RAR 9099 60018 JCN CN NEXT1 20103 0101 00065 JUN REPT Z CALL FOR INPUT DATA 00073 8183 00066 NEXT1 JUN LISTR CALL LISTING ROUTINE 20187 BCD TO BINARY CONVERSION ROUTINE 0105 00234 DBIN FIM P1 18 2 IR 3 0 a8 9197 90036 FIM P2 10 1RC4 20 1805 218 165 2199 2110 9111 8112 8113 8114 8115 0116 0117 119 12 121 122 g123 8124 61 25 0126 8127 0128 8138 8132 8134 0135 0137 9139 0148 0142 0144 0146 0147 8148 6149 9159 0151 0152 0153 0154 0155 156 8157 0158 0160 6161 0152 0163 00210 88222 LDM 14 82182 6 200433 SRC 29233 RDM 20179 XC
116. Model S 52 and Model UVS 54 short wave ultraviolet lamps manufactured by Ultra Violet Products Inc San Gabriel California The lamps should be used without short wave filters and the 1702A to be erased should be placed about one inch away from the lamp tubes MP7 03 Programming System The MP7 03 is the PROM programming board which easily interfaces with the MCS 4 All address and data lines are completely TTL compatible The MP7 03 requires bVDC 0 8 amps 10VDC 0 1 amps and 50 Vrms 1 amp Two Stancor P8180 or equivalent filament transformers 25 2 Vrms 1 amp with their secondaries connected in series provide the Vrms This programmer board is the successor of the MP7 02 The MP7 03 enables programming of Intel s new 1702A a pin for pin replacement for the 1702 When the 7 03 is used under SIM4 01 51 4 02 control with control ROM 0542 replaced by 0543 the 1702 be programmed five times faster than the 1702 in less than five minutes IMPORTANT Only use the A0543 control when programming the new 1702 Never use it when programming the 1702 The programming duty cycle is too high for the 1702 and it may be permanently damaged The MP7 03 features three data control options 1 Data in switch Normal Complement If this switch is in the complement position data into the PROM is complemented 2 Data out switch Normal Complement If this switch is in the complement position
117. NC 1 IRCIOZIRCIOS 0014 0041 SKC lt Z DEFINE ADDRESS 0015 0351 RDM READ RAM DATA TO AC 0016 0024 6017 0033 JCN AZ3BB2 JUMP IF AC 0 90020 0370 DAC 1 0921 0340 WRITE AC 19 2022 0361 CLC 7 CLEAR CARRY REG 0023 0243 LD 3 7 LJAD AC WITH C IRC3 0205 ADD 5 ADD IRCCS 10 0925 0263 XCH 3 7 EXCHANGE 1 3 AND 0026 0242 LD 2 7 LOAD AC WITH In 2 0227 0904 ADD 4 ADD IRC4 TO 0930 0262 XCH 2 EXCHANGE AC WITH IRC2 0031 0100 0032 0015 JUN 7 JUMP UNCONDITIONAL 0033 4044 8834 0144 BB2 FIM 2 lt 100 IRC4 6 IFR 5 4 2935 0166 2036 9013 ISZ 63 BDBN Z IRC6 IRC6 1 SKIP IF IRC6 0 0037 0300 BBL Z RETURN TO CALLING ROUTINE AC 0 SET INDEX REGS 9 e IR 1 IR 2 o IR 3 IR 4 e IR 5 19 SET DIGIT CONTR IR 6 14 READ THE LS DIGIT TO AC AND THEN TRANSFER THE CONTENT OF AC TO IR 3 IR 6 IR 6 1 READ NEXT DIGIT FROM RAM AC YES SET IR 4 6 IR 5 4 NO IR 6 IR 6 1 TRANSFER CONTENT OF AC TO RAM 0 REG 0 CHARACTER 1 CLEAR CARRY IR 3 AC IR 5 3 AC IR 4 Figure12 Flow Chart for BCD to Binary Conversion 7 D A D CONVERTER USING DAC With MCS 4 One application using the Intel MCS 4 single chip computer family is to determine the value of an analog voltage While it was possible to use the conventional a
118. NPPPPF BNPNPPNPPF BNNNNPPPNF BPPNPPPPNF F programming completed In this example the first five data words on the tape are skipped and the next six data words are programmed 1 the ROM locations 005 to 010 indicates the first instruction programmed and the F at end of the listing indicates the completion of the programming 2 To program any portion of the ROM without skipping a section of the tape use a short tape data words in sequence and type P program command XXX initial address YYY final address Start the tape data words may also be entered manually EXAMPLE 2 Typed program command by g11 lt n v5m2 initial address User 16 final address 011 BNNNNPNPPF Listing 012 BNNNPPPPNF of 013 BNNNNPNNPF tape 014 BNPNPPPNPF by 015 BNNNNPNNPF TTY 016 BNPNNPPNPF completed 86 This example shows that the first six instruction words in sequence on tape are read and directly programmed into ROM locations 011 through 16 without skipping FORMAT CHECKING When the programmer detects the first format error data words enter either on tape or manually it will stop programming the ROM and it will print out the address where the format error occurred If a tape is being used the programming system will continue to list the content of the tape and will print out the address of each su
119. OH preceding them and place the instruction patterns into the proper simulated ROM locations 2 Prepare SIM4 02 Hardware Remove ROM chips A0740 through A0743 and plug in the Hardware Simulation Program chips A0750 A0758 Press RESET The teletype should type out a carriage return linefeed and an asterisk to show that the simulation program is ready to accept a directive Determine how much simulated ROM is needed to test the program and which RAMs are least likely to be accessed by the test program using if necessary the and directives Then type in the O directive for this program From now until the testing of this program has been completed and the amended program tape has been punched out DO NOT touch the RESET button If the RESET button is pressed the simulation parameters and any program in the simulated ROM will be destroyed 3 Load Program Place the object tape in the teletype reader and type in The simulation program will read both the addresses and the instructions from the tape and store them in the proper locations Reading will be terminated by any error or by the terminal F punched by the assembler Note that any instructions or data which fall outside the limits defined in the Q directive will be ignored Note also that if the Q directive defines the ROM limits to be more than 512 bytes wraparound overlap is possible Thus location 100 would be overwritten by instructions going into location 612 When the program
120. ORT ROM 1 ROM INPUT PORT ROM 1 ROM INPUT PORT ROM 1 ROM INPUT PORT ROM 1 ROM INPUT PORT ROM 2 ROM INPUT PORT ROM 2 ROM INPUT PORT ROM 2 ROM INPUT PORT ROM 2 ROM INPUT PORT ROM 3 ROM INPUT PORT ROM 3 ROM INPUT PORT ROM 3 ROM INPUT PORT ROM 3 TTL COMPATIBLE IN ROM OUTPUT PORT ROM ROM OUTPUT PORT ROM ROM OUTPUT PORT ROM ROM OUTPUT PORT ROM ROM OUTPUT PORT ROM ROM OUTPUT PORT ROM ROM OUTPUT PORT ROM ROM OUTPUT PORT ROM ROM OUTPUT PORT ROM ROM OUTPUT PORT ROM ROM OUTPUT PORT ROM ROM OUTPUT PORT ROM ROM OUTPUT PORT ROM ROM OUTPUT PORT ROM ROM OUTPUT PORT ROM ROM OUTPUT PORT ROM TTL COMPATIBLE OUT Q N N N FP FP O RAM OUTPUT PORT RAM RAM OUTPUT PORT RAM RAM OUTPUT PORT RAM RAM OUTPUT PORT RAM RAM OUTPUT PORT RAM RAM OUTPUT PORT RAM RAM OUTPUT PORT RAM RAM OUTPUT PORT RAM OUTPUT PORT RAM RAM OUTPUT PORT RAM RAM OUTPUT PORT RAM RAM OUTPUT PORT RAM RAM OUTPUT PORT RAM RAM OUTPUT PORT RAM RAM OUTPUT PORT RAM RAM OUTPUT PORT RAM 69 MOS COMPATIBLE OUT MOS COMPATIBLE OUT N N N N F F O TRANSISTOR BUFFER OUT TRANSISTOR BUFFER OUT o ate 42 1 zi UI CHIP o s lt vss n CM EAM 2 CHIP O 4 3 3 cm Io syne syne P2 D
121. OUTPUT PORT BANK o ac u L D m OUTPUT PORT BANK ROM PORT ROM OUTPUT PORT BANK ROM PORT ROM OUTPUT PORT BANK ROM PORT ROM OUTPUT PORT BANK ROM PORT ROM OUTPUT PORT ROM INPUT PORT ROM OUTPUT PORT ROM INPUT PORT ROM OUTPUT PORT ROM INPUT PORT ROM 7 OUTPUT PORT ROM 7 INPUT PORT ROM OUTPUT PORT TELETYPE RECEIVER CONNECTION OUTPUT PORT BANK TELETYPE TRANSMITTER CONNECTION OUTPUT PORT BANK TAPE READER CONTROL OUTPUT PORT BANK 0 0 ROM OUTPUT PORT ROM OUTPUT PORT BANK 0 A 1 ROM OUTPUT PORT ROM MOS COMPATIBLE OUTPUT PORT BANK 0 2 ROM OUTPUT PORT ROM 40 OUTPUT PORT BANK 0 A 3 ROM OUTPUT PORT ROM ul 959 9 a OUTPUT PORT BANK m 0 0 ROM OUTPUT PORT ROM 1 0 E OUTPUT PORT BANK L lt 0 1 ROM OUTPUT PORT ROM 1 e OUTPUT PORT BANK 0 B 2 ROM OUTPUT PORT ROM 1 9 OUTPUT PORT BANK ROM OUTPUT PORT ROM 1 0 B 3 OUTPUT PORT BANK 0 5 0 ROM OUTPUT PORT ROM 2 OUTPUT PORT BANK ROM OUTPUT PORT ROM OUTPUT PORT BANK 0 C 2 ROM OUTPUT PORT ROM 2 OUTPUT PORT BANK 0 3 ROM OUTPUT PORT ROM 2 OUTPUT PORT BANK 75 PIN CONNECTOR SYMBOL DESCRIPTION OUTPUT PIN R3 A 11 RAM OUTPUT PORT BANK 3 RAM 2 R3 A 12
122. Operand Fields An operand field begins after the space s which terminates the mnemonic field or after the separator which terminates the previous operand field It consists of one or more terms separated by operational signs or and is terminated by separator other than an operational sign such as a space comma or carriage return with no imbedded separators other than the operations signs Each term in the operand field may be a decimal number a register pair designation a register designation a name or the special symbol which has a value equal to the address of the first byte of the current instruc tion The value of the operand is equal to the two s complement algebraic sum of the terms modulo 4096 If the operand is larger than the receiving field in the instruction it is truncated on the left i e the most significant bits are removed as necessary to fit with no error indication except for off page references in the address field of the 152 and conditional jump instructions Some examples of valid operand fields ABC 5 B 6 x 1 The address of the byte immediately preceding the current instruction A B 13 Q Register Pair value 6 Null operand value zero It should be noted that null operand fields must be terminated by a parenthesis asterisk period comma or slash Some invalid operand fields O F Imbedded Separator Invalid term may not begin with Separator is
123. P 3 LOAD ROM DATA H AC WRITE PROM DATA IN H OP 3 DATA SETTLE DELAY 10 MS CLEAR AC LOAD MODE SELECT CHECK 1702A MODE JUMP IF CY 1 PGMA CHECK 1702 MODE JUMP IF CY 1 PROGRAM 1792 JUMP STOP IFNOT PGM MODE SET SRC RAM 1 SEND RAM 1 LOAD R WA BIT ENABLE 1782A PGM TIME 517 MS 011 CLEAR R WA BIT DISABLE 17024 PGM JUMP COMP 811 SET SRC RAM 1 SEND RAM 1 LOAD R W 02 BIT ENABLE 1702 PGM 212 PROGRAM TIME 5 6 SEC CLEAR R W 02 BIT DISABLE 1702 PGM 012 DATA SETTLE TIME 10MS SRC ROM 2 PROM DATA OUT L SRC RAM 2 DATA DSPLY SEND ROM 2 IP2 READ PROM DATA OUT L IP2 SEND RAM 2 PROM DATA OUT DSPLY L WRITE PROM DATA OUT DSPLY L 02 STORE PROM DATA OUT L R9 SET SRC ROM 3 PROM DATA LOAD 64 FOR RAM 3 SRC SET SRC RAM 3 LOAD SRC H SEND ROM 3 IP3 READ PROM DATA OUT H IP3 SEND RAM 3 PROM DATA OUT DSPLY H WRITE PROM DATA OUT OSPLY H 03 STORE PROM DATA OUT H R8 CLEAR CY LOAD ROM DATA L AC SUB PROM DATA OUT L JUMP IF DATA L NO COMP OUT H CLEAR CY 169 001 76 001 52 00241 20028 00155 00064 00168 80126 NOCMP 28049 97034 85082 00235 0 9214 00225 20017 00162 20219 00225 20229 20190 ERROR WAIT 00173 00241 00242 80189 00
124. R LD 2 RAR XCH LD 3 RAR XCH JMS ISZ L DM FIM SRC WM P JUN FIM 154 152 BBL FIM 154 BBL 15 TZ ST SBRI 0 313 13 TEST A lt SBR2 0 lt 0 9 2 3 5 4 3 SBRI lt 2 3 3 SBR2 45 ST1 15 SUBRIUTINES 0 lt 0 0311 ZSILENCE N N N N 55 BY SETTINT BIT 3 OF TO 310 1 DEFINE RAM ADDRESS WRITE DATA TO RAM PORT WAIT FOR DATA INPUT SIGNAL 5 00MS TIME OUT IRC 43IRC1 13 COMPLETE TIMMING FOR BIT SAMPLE DEFINE ROM PORT ADDRESS READ ROM INPUT TO AC COMPLEMENT DATA AND ECHO DO FINAL TIME OUT 300 MS 16 60 1 0 IR 2 0 IRC3 0 IRC4 8 READ DATA INPUT SIOKE DATA IN CARRY LOAD AC IRC2 TRANSFER BIT RESIORE NEW DATA WORD EXTEND REGISTER TO MAKE 8 BITS RETURN TO INPUT IkRCO 1220 5 47MS TIME 011 IRC ijs 1 1058 2 75 MS TIME OUT XI SIM4 01 SIM4 02 PROTOTYPING SYSTEM A General System Description During the development phase of the equipment using the MCS 4 micro computer set the designer will often find it helpful to have a means for testing out his program An interface circuit in which 1701 or 1702 electrically programmable and erasable read only memories simu late the 4001 mask programmable read only memories will help serve this purpose Using this interface it is possible for the system designer to program the 1701 s or 1702 s plug them into the system check out the programs and make c
125. R A MATCH P3 78 1RC6 24 IR 7 z14 COMPR AZ CONT AC PRINT P3 66 IR 6 4 18 7 2 B COMPR A2 REPTB P3 127 IR 6 s7 18 7 5 R COMPR AN FORMT RgnuT 16 DATA STORAGE PA CHIP REG 1 HAR 1 LEAST SIGNIFICANT DATA CHIP REG 1 CHAR MOST SIGNIFICANT BIT DATA DATA1 GET NEXT CHAR IR 6 24 IR 7 z6 F 70 COMPR A2 CONA IF NOT RESTART INPUT P3 56 ZIR 6 4 1807 2 0390 0592 0394 0396 0398 0402 0402 0403 0404 0405 0406 0487 0496 6459 0418 0411 0412 2414 0416 0418 0420 0422 8423 0424 0425 0427 0428 0429 0431 0432 0433 0454 0435 0436 9438 0439 0440 04 41 94 42 94 44 0445 447 0448 0449 0450 0451 0452 0453 0454 0456 0457 0458 0459 0461 0463 0464 0465 0466 0467 0468 0469 0470 0471 0472 2473 0474 9476 0478 04 80 0482 0484 0485 0486 8487 0489 0491 0492 8493 8494 8495 0496 0497 00081 00853 00020 00081 82838 22127 00081 00033 80228 00158 00432 00016 000 53 00236 00246 00228 88237 00246 00229 00169 00248 601 85 20265 02883 00480 08226 00082 00174 00081 00171 62042 86832 00209 00043 00228 82066 00125 00221 00188 00042 00453 00045 00233 00179 00219 00178 00080 00178 00171 00248 00187 00241 89124 00175 801 92 000 32 00016 88833 80237 00244 00229 00236 08244 00228 000 52 00052 50833
126. RE EN2907 2 12 r Fa 44446 gt m 5 3 RESISTOR VALUES ARE IN OHMS 1 4 W 10 eer 592 z bg 5 5 60 en vez Ue 4 CAPACITORS VALUES ARE IN MICROFARADS gt gt ro CR8 ARE OPTIONAL I Sex M C nw 16 i D 6 FACTORY SELECTED R 5 ROR gy Rog 205 200 Figure 24 SIM4 02 Complete Schematic 72 73 188880 1 5 Q R2 Jo ORMO OF G C OCR obo 4 0 O OCRE RED 2 9 05 0 87 empo gt SHS ae eno Q KY eee 2222 OS T cq 2 9 0 4 8 2 3 3 42 4 6 54 G G uno 2 9 17 3 4 1 22 3 4 4 5 70 4 7 Qo NOTES Unless otherwise specified 1 All diodes are 1N914 All transistors are EN2907 Resistor values in ohms 1 4 W 10 Capacitor values are in microfarads A29 and A30 was 3015 R1 R8 option for additional memory only Factory Selected Amphenol Connector PN 261 10043 2 Figure 25 Component Side of SIM4 02 Board MN II IIIAIIIIII IIIIIIIxI 85 s 77 73 Figure 26 Pin Definition Reverse Side of SIM4 02 Board 74 SIM4 02 Board Pin Description Inputs and outputs designated with respect to negative logic DESCRIPTION i5 CONNECTOR DESCRIPTION 67 Jl 0 D 0 5VDC Power Supply OUTP
127. RE NEW DATA WORD EXTEND REGISTER TO MAKE 8 BITS 0040 0000 0041 0341 0333 0223 0361 0024 0154 0050 0100 0243 0051 0342 9150 0242 0951 9342 0040 0001 0044 0077 0046 0076 0047 0351 0045 0340 0245 0370 0265 9361 0247 0370 0261 0361 8161 0131 0243 0045 0340 0175 0930 0120 0367 0040 0000 0044 0060 0320 0266 0361 0045 0351 0041 0353 0373 0340 0141 0145 0166 0165 0022 0242 0054 0017 0320 0272 0044 0080 0321 0045 9344 0045 0354 0366 0055 0351 WRITE 5 ADDI TN 1 gt 2 FIM 0 lt 30 SRC 0 LDM 11 SUB 3 CLC JCN 2 ADDI TN IF JUMP FIM 4 364 IRC08 4 92 0 LD 3 5 4 lt WRR INC 8 LD 2 SRC 4 lt WRR FIM lt 1 1 0351 1 1 FIM 2 lt 363 IRCA4 3 IRC S 1S FIM 3 lt 362 IRC 6 3 IROTI 14 SRC 3 RDM SRC 2 lt WRM LD 5 DAC 5 CLC LD 7 DAC XCH 7 CLC 152 13 LD 3 SRC 2 lt WRM 152 13 5 JMS 3CRLF POSITION CARRIAGE FIM 0 0 IR 0 15 0 FIM 2 lt 3 48 IRC4 3 IR 5 0 LDM 0 XCH 6 CLC SRC 2 RDM SRC 0 DAA WRM INC 1 INC 5 152 63AD1 JCN CN3XXX 7 TEST FOR CARRY FIM 6 lt 15 IRC122 03 IRC132215 LDM 0 XCH 10 FIM 2 lt 30 LDM 1 SRC 2 lt WRO SRC 2 lt RDO 5 6 lt RDM 79 0217 0220 221 0222 0223 0224 0
128. ROL MODULE This module provides the complete interconnection between the SIM4 01 and the MP7 03 In addition to the connectors for both boards there are LED data displays of each microcom puter output port control switches the 50 Vrms transformers and a socket for the PROM being programmed Plug in connectors for each input and out put port are provided The SIM4 01 when used alone with the MCB4 10 is a complete microcomputer except for power supplies See Appendix E for a complete description of the MCB4 10 MCB4 20 SYSTEM INTERCONNECT and CONTROL MODULE This module provides the complete interconnection between the SIM4 02 and the MP7 03 This total package may be used for both a PROM pro grammer and a microcomputer develop mental system The MCB4 20 has the same basic features as the MCB4 10 and in addition it provides a socket which can be used for duplication The MCB4 20 is also fully described Appendix E 5V GND 10V ENABLE 5 DATA OUT DISABLE n DATA MP7 03 SIM 4 01 27 ROM 29 PROGRAMMER TTY DATA OUT TAPE READER TTY PRINTER 25 2 V RNS 1 0A 25 2 V RMS 1 0A T MEVBOABD 9 M AMPS READER 2 8180 SLO BLO 1702 3000 STANCOR 1702A 75 100 VDC R 5V NOTES 1 SIM4 01 and MP7 03 Connectors a Solder lug type Amphenol 72 pin connector P N 225 23621 101 b Wire wrap type Amphenol shown above 72 pin connector P N 261
129. ROM and the selected CM RAM lines are always in a logical true state at A4 time of any instruction cycle CM ROM equals 1 at A3 time indicates to ROM s that the code at A3 time is the chip number of a ROM within their bank This feature allows the user to expand the system to more than 16 ROM chips CM RAM equals 1 at time has no meaning for the RAM chips however it could be meaningful if ROM s and RAM s were controlled by a CM RAM line Figure 4 summarizes the operation of the command lines in the various instruction cycles 15 C Basic Instruction Set Table V shows the basic instruction set of the 4004 CPU Section VII will describe each instruction in detail Those instructions preceded by an asterisk are 2 word instructions that occupy 2 successive locations in ROM MACHINE INSTRUCTIONS Logic 1 Low Voltage Negative Voltage Logic 0 High Voltage Ground OPR OPA D3 D2 D4 Dg D3 D gt D4 Do DESCRIPTION OF OPERATION we 0000 0000 No operation JCN 0001 Jump to ROM address 2 2 2 2 A1 A1 A1 A4 within the same ROM that contains this JCN instruction if condition C1 C2 C3 c4U A2 A2 A2 A2 is true otherwise skip go to the next instruction in sequence 0010 RRRO Fetch immediate direct from ROM Data 02 D4 to index register pair 02 D gt D3 D D4 D4 0 0 location RRR 2 SRC Send register control Send the address contents of index register pair RRR to ROM and RAM at X2 and X3 time in
130. SIM4 02 MP7 03 PROM Programming Program which enables a computer to sample liquid System A0540 A0541 A0543 1 levels in bottles A D Converter using DAC and 5 4 RAM test program the SIM4 01 SIM4 02 SIM4 Hardware Assembler Four PROMs A0740 A0741 Program to control the tape motion of an IBM tape drive A0742 A0743 plug into either SIM4 prototype board Hex programmer for the SIM4 01 MP7 03 enabling assembly of programs on the micro computer PROM programmer itself e MCS 4 logic subroutines AND XOR IOR LOGIC e SIM4 Hardware Simulator Nine PROMs A0750 A0758 Sixteen Digit Decimal Addition Routine A0700 plug into the SIM4 02 providing capability for program Exerciser Program 4001 0009 2 debugging Chebychev polynominal approximation subroutines for PROM Duplication and Verification Program 0544 11 addition subtraction multiplication division sine cosine see Appendix E arctangent exponential and natural logs BCD to Binary Conversion Routine These program listings are available to all Intel micro computer users We encourage all users to submit all non proprietary programs to Intel to add to the program library so that we may make them available to other users NOTES 1 These are the program numbers that should be used when ordering the programs PROMs 2 This is the number that should be used when ordering this program The program is contained in
131. T 1 0 INPUT PINS 4001 2 4 INPUT LEAKAGE CURRENT 4001 2 4 ViH INPUT HIGH VOLTAGE CLOCKS INPUT LOW VOLTAGE VDD Vss 55 V EXCEPT CLOCKS VDD 13 4 5 0 3 4001 2 4 DATA BUS OUTPUT LEAKAGE Vout 12V Chip disabled CURRENT 4001 2 4 OUTPUT HIGH VOLTAGE Vss Vss 0 5 Driving 4000 Series loads only 4001 2 4 loi DATA LINES SINKING 10 18 Vout CURRENT 1 LEVEL 4004 iene CM ROM SINKING CURRENT 65 1 Vout 0V i LEVEL _ 4004 iie CM RAM LINES SINKING 25 4 Vout 0V CURRENT 1 LEVEL 15 32 2 4001 2 4 Vout DATA LINES CM LINES Vsg 12 Vss 10 Vss 6 5 SYNC OUTPUT LOW VOLTAGE 4001 2 4 OUTPUT RESISTANCE 0 250 DATA LINES 0 LEVEL 4004 Rous CM ROM OUTPUT 0 600 RESISTANCE 0 LEVEL RESISTANCE 0 LEVEL CM RAM LINES OUTPUT INPUT CHARACTERISTICS 4001 3 INPUT HIGH VOLTAGE Vss 1 5 Vss 03 4001 3 vu 2 INPUT LOW VOLTAGE Vop Vss 42 v V OUTPUT CHARACTERISTICS mA Vout 0 For T2L compatibility a 12K 0 10 resistor between out put and should be added 3l 4001 2 loi2 OUTPUT LINES SINKING CURRENT 1 LEVEL Vout OV For T2L compatibility a 4003 013 PARALLEL OUT PINS SINKING CURRENT 717 LEVEL 5 6K 2 10 resistor between out put and Vpp should be added 3 4003 SERIAL OUT SINKING m CURRENT 1 LEVEL 10 Vout 0 5
132. THE BREAK 119 00011102 1 0001 i 1180 POINT KEY 1898111110110 1110 NEAR COMPLETION OF A LINE 109 10110002 8 0201 110 02011010 0 02091 122110110001 1111 1 123111110110 1 2111 1241190110001 1 2001 125111119091 0001 196101000000 i 115 10110010 2 1100 116111110119 0 0113 117110110010 8 9901 OUTPUT TO 118311111000 1 90000 MEMORY PORT 119800011100 1 09009 1211110990002 11 10110010 1 2119 121111900001 8110 13101000000 BREAKPOINT NEXT LOCATION NON TRACE MODE TERMINATES TRACE IS INITIATED 9 70111 NON TRACE MODE 1 71110 09110 Figure 1 Trace and Nontrace Modes 149 REG 11 REG 12 REG 13 REG 14 REG 15 REG 10 USED FOR CPU REGISTER SIMULATION Q HIGH ADDRESS LIMIT EXECUTION PARAMETER BREAKPOINT ADDRESS Q LOW ADDRESS LIMIT STACK LEVEL 1 CHIP SELECT STACK LEVEL 2 CHIP SELECT 0 REG 1 REG 9 REG 4 REG 5 8 USED FOR STATUS WORD SIMULATION SAMPLE PROGRAM LOCATED AT 000 TO 015 AND 104 TO 128 STACK POINTER PROGRAM COUNTER LEVEL O CMD LINE SELECTION RDR COMMAND DUMP RAM 15 _ LOCATION 3 1110 1010
133. UT PORT ROM PIN CONNECTOR SYMBOL 6 amp 8 J2 45V 10V 10VDC Power Supply OUTPUT PORT ROM Ground OUTPUT PORT ROM Not Used OUTPUT PORT ROM I A 0 ROM INPUT PORT ROM OUTPUT PORT ROM I A 1 ROM INPUT PORT ROM 9 OUTPUT PORT ROM I A 2 ROM INPUT PORT ROM 0 OUTPUT PORT ROM I A 3 ROM INPUT PORT ROM 0 OUTPUT PORT ROM ROM PORT ROM 1 OUTPUT PORT ROM ROM PORT ROM 1 OUTPUT PORT ROM ROM PORT ROM 1 OUTPUT PORT ROM I 8 3 ROM INPUT PORT ROM 1 OUTPUT PORT ROM TTL COMPATIBLE ROM PORT ROM OUTPUT PORT ROM I 1 ROM INPUT PORT 2 OUTPUT PORT ROM ROM PORT ROM OUTPUT PORT ROM I C 3 ROM INPUT PORT ROM 2 OUTPUT PORT ROM I F 0 ROM INPUT PORT ROM 5 OUTPUT PORT BANK TAPE READER OUTPUT PORT BANK ROM PORT ROM ROM PORT ROM OUTPUT PORT BANK ROM PORT ROM I D 0 ROM INPUT PORT ROM 3 OUTPUT PORT ROM 2 I D 1 ROM INPUT PORT ROM 3 6 OUTPUT PORT ROM 2 I D 2 ROM INPUT PORT ROM 3 w OUTPUT PORT ROM I D 3 ROM INPUT PORT 3 t OUTPUT PORT ROM 7 u I E 0 ROM INPUT PORT ROM 4 lt OUTPUT PORT BANK 0 5 a TTY TRANSMITTER a I E 1 ROM INPUT PORT 4 OUTPUT PORT BANK 0 0 I E 2 ROM INPUT PORT ROM 4 E OUTPUT PORT BANK O I 3 ROM INPUT PORT ROM 4
134. UTINE PRINT FIM 0 lt 16 7 IRC025z13 IRCI2sQ LDM 7 SRC 0 lt WRM INC 1 XCH 3 SRC 0 lt WRM INC 1 XCH 2 SRC lt WRM FIM 4 316 IJ 1 9 0 FIM 1 lt 3208 IR G 2 13 1RC3 0 80 0330 0331 0332 0333 0334 0335 0336 0337 0340 0341 9342 0343 0344 0345 0346 0347 0350 0351 0352 0353 0354 0355 0356 0357 0360 0361 0362 0363 0364 0365 0366 0367 0370 0371 0312 0373 0374 0375 0376 0377 0044 0014 0051 0351 0341 0264 0120 0271 0120 0300 9264 0165 0360 0151 0000 09000 0000 0000 0162 0330 0337 0341 0300 0046 0 14 579 0167 0362 0366 0100 0334 CR LF 517 518 5712 0042 0215 0120 0307 0042 0212 0120 0307 0300 CRLF LF OCTAL FIM 2 lt 12 SRC 4 lt RDM WMP XCH 4 JMS3 SBRI JM S SBR2 XCH 4 ISZ 53519 INC 9 NOP NOP NOP NOP NOP 152 L DM WMP BBL 23ST7 15 FIM 3 lt 312 152 RAR 73 ST12 JUN 03578 ROUTINES FIM 1 lt 3 141 JMS3 PRINT FIM 1 3138 JMS 3PRINT BBL ERC4 O 1205 12 7 SAVE gt IN DELAY ROUTINE 7 DELAY ROUTINE RESTORE SAVED INDEX REG 4 81 2 CCAC NUMBER OF ROTATIONS NUMBER OF DIGITS NUMBER OF 4 BIT WORDS IRC C6 IRC 7 12 IRC2 83IR 3 13 CR IRC 2 83 IR 3 10 LF ADDRESS LABELS USED IN PROGRAM ADDITN 0154 CLEAR 0262 LF 0373 OVERFL 0177 0131 SKP
135. a BBL Or until the instruction limit counter overflows Dump read write memory En Examine RAM word n n must be between 0 63 Words 0 15 are in bank f words 16 31 in bank 2 etc When printed main character 15 will be printed first followed by the remaining main characters of the word in descending order space follwed by status characters g 31 in ascending order is printed after the main characters Output is in hexadecimal with A F corresponding to 10 15 Fn If n l read only memory input port data is read from a file rather than from the teletype Data in the file must consist of a single numeric value per record with the numeric value lying between f and 15 decimal If nZ1l the input port data will be requested from the teletype writer H Prints a two line leader record corresponding to the data printed during trace mode or printed upon reaching break points BBL exits or overflowing the instruction limit counter In Re initializes the program counter to 0 and clears read write memory If nzf the instruction limit counter is 161 Jn Ln Mn Tn Un Wn X set to n If n f the instruction limit counter is left unchanged The initial value for the instruction limit counter is 10 000 Jump to and begin execution at ROM address n Stop either when the break point is reached or the instruction limit counter overflows Operate trace mode with output to the line printer
136. a simulated program counter to maintain the address The JIN instruction is often useful for interpreting the fetched instruction Address for the JIN is computed from the fetched pseudo instruction Each address value is the loca tion of a JMP or JMS to an appropriate routine or the routine itself When fetching pseudo instructions from ROM the FIN is used the FIN instruction must be located on the same ROM chip as the fetched data one cannot use all 256 8 bit bytes of a ROM for pseudo instructions It is sufficient to allow an FIN followed by a BBL on the ROM chip Thus up to 254 bytes of each ROM chip can be used for pseudo instructions The simulated program counter must correspond to this address structure If the FIN and BBL instructions are located in the first two locations of the ROM chip the 254 step program address counter can be imple mented by initializing the chip address to location 2 rather than location O If the interpretive mode program exceeds 254 bytes the program control routine must determine the proper chip to find the next pseudo instruction The instruction is then fetched by a JMS to address O of the appropriate chip 42 IX PROGRAMMING EXAMPLES MCS 4 Program Routine Format Notes Routines A B and C Assume the Form Shown Below Routine D uses Decimal Values for Column 1 and 2 Example ens e EE 0 Where The first column repre
137. a standard 4001 ROM 50 X INTERFACE DESIGN FOR THE MCS 4 SYSTEM A General Discussion MCS 4 amp computer systems are often used to replace random logic controllers in a wide variety of systems each of these sys tems a number of peripheral devices such as keyboards switches indicator lamps numeral displays printer mechanisms relays solenoids etc may have to be interrogated or controlled The engineer who wishes to utilize an MCS 4 system must include as part of his design suitable interface circuits and programs Devices to be operated or interrogated by an MCS 4 computer are attached to the system via the input and output data ports as sociated with the 4001 ROM and 4002 ROM The design of an inter face consists of the following steps 1 Assign peripheral device connections to port connections If the number of available output ports is insufficient 4003 output port expanders may be used When the number of input lines is insufficient multiplexers must be added These multiplexers must be controlled by output ports 2 Develop the necessary level conditioning circuits for each Signal Port inputs and outputs are at MOS levels logic OV with a series output resistance of typically 150A logic 1 7v with a series resistance of typically 2k for outputs Inputs use the same levels and appear as a capacitive load of approximately 5Pf These levels must be converted to the levels necessary to drive soleno
138. accu mulator and carry link are unaffected Mnemonic WRO Write accumulator into RAM status character 0 OPR 1110 0100 Symbolic ACC Mso Description The content of the accumulator is written into the RAM status character 0 of the previously selected RAM register The accumulator and the carry link are unaffected es ee ME Mnemonic WR1 Write accumulator into RAM status character 1 OPR OPA 1110 0101 Symbolic ACC gt Ms eee 1 WR2 Write accumulator into RAM status character 2 OPR 1110 0110 Symbolic ACC WR3 Write accumulator into RAM status character 3 OPR OPA 1110 0111 Symbolic ACC WRR Write port OPR OPA 1110 0010 Symbolic output lines Description The content of the accumulator is transferred to the ROM output port of the previously selected ROM chip The data is available on the output pins until a new WRR is executed on the same chip The ACC content and carry link are un affected The LSB bit of the accumulator appears on I 0p pin 16 of the 4001 operation is performed on I O lines coded as inputs Mnemonic WMP Write memory port OPR 1110 0001 Symbolic ACC output register Description The content of the accumulator is transferred to the RAM output port of the previously selected RAM chip The data is available on the o
139. accumulator and KBP Keyboard Process instructions The special ROM s also communicate with the internal bus The condition logic senses ADD 0 and ACC 0 conditions the state of the carry FF and the state of an external signal TEST to implement JCN jump on condition and ISZ increment index register skip if zero instructions Instruction Register Decoder and Control The instruction register consisting of the OPR Register and OPA Register each 4 bits wide is loaded with the contents of the internal bus at M and time in the instruction cycle through a multiplexer nd holds the instruction fetched from ROM The instructions are decoded in the instruction decoder and appropriately gated with timing signals to provide the con trol signals for the various functional blocks A double cycle FF is set from one of 5 double length instructions Double length instructions are instructions whose OP code is 16 bits wide instead of 8 bits and that require two system cycles 16 clock cycles for their execution Double length instructions are stored in two successive locations in ROM condition FF controls JCN and ISZ instructions and is set by the condition logic The state of an external pin test can control one of the conditions in the JCN instruction Peripheral Circuitry This includes a The data bus input output buffers communicating between data pads and internal bus b Timing and SYNC generator
140. accumulator to 0 ADD 15 WMP ADD 15 generate one clock pulse WMP SRC select output port XCH 1 transfer 2nd half of display WMP transfer to output port SRC select clock port LDM 0 Set accumulator to 0 ADD 15 WMP ADD 15 generate one clock pulse WMP INC set next RAM character ISZ 14 test for no of characters Note that two data characters 8 bits are transferred for each digit to be displayed This loop must be initialized by setting the registers to their initial conditions The following sequence of 4 instructions is sufficient FIM select RAM register for display FIM initialize clock port selector FIM initialize output port selector FIM initialize no of digits and set reg 8 Example 6 Subroutines Proceeding with the example outlined above suppose that the user finds it necessary to display the contents of a number of different RAM registers at different places in the program The sequence of instruc tions could be used whenever this was necessary However by making the entire sequence a subroutine the user can call out the sequence each time it s needed with only a JMS instruction JMS utilizes the address push down stack When a JMS is executed the program counter is pushed up one level and is reloaded with the address to which the jump to take place and execution will proceed from this new location However before the program counter is reloaded the old value is saved
141. affected Mnemonic TCS Transfer carry subtract OPR OPA 1111 1001 Symbolic 1001 ACC if CY 0 1010 gt ACC if CY 1 0 CY Description The accumulator is set to 9 if the carry link is O The accumulator is set to 10 if the carry link is a 1 The carry link is set to O 31 Mnemonic KBP Keyboard process OPR 1111 1100 Symbolic ACC gt KBP ROM gt Description A code conversion is performed on the accumulator content from 1 out of n to binary code If the accumulator con tent has more than one bit on the accumulator will be set to 15 to indicate error The carry link is unaffected The conversion table is shown below ACC before KBP ACC after KBP 0000 0000 0001 gt 0001 0010 0010 0100 FA 0011 1000 vu TN 0100 0011 O 1111 0101 1111 0110 1111 0111 OF 1111 1001 IV PM h 1111 1010 U 1111 1011 gt 1111 1100 5 1111 1101 gt 1111 1110 1111 1111 v Y 1111 Mnemonic DCL Designate command line OPR 1111 1101 Symbolic ag gt CM CM Description The content of the three least significant accumulator bits is transferred to the comand control register within the CPU This instruction provides RAM bank selection when multiple RAM banks are used If no DCL instruction is sent out RAM Bank number zero is automatically selecte
142. alance of the circuitry shown in the schematic is used to implement the input output port functions associated with the 4001 read only mem ories The execution of an SRC instruction which is used to activate a port is indicated to the port control circuitry by the presence of the command signal at X2 time This condition is decoded and used to load a two latch port selection register The contents of this register 57 are in turn decoded by means of four two input NAND gates Execution of a port control instruction is indicated by the presence of the command signal CM during time combined with the appropriate code on the data bus For instance the READ ROM INPUT condition is detected by a seven input NAND gate When this instruction is detected a flip flop consisting of two input NAND gates is set The presence of 1 in the port read control flip flop is used to enable the inputs from one of two multi plexers onto the data bus during X2 time Data is then transferred into the 4004 from an input port at X2 time The port read control flip flop is reset at time so that it will not influence operations on the instruction In general the number of output ports provided by the array of 4002s is adequate However to fully duplicate the effects of the 4001s it may be necessary to implement ROM output ports as well as input ports Although the two latch port selection register and decoder need not be duplicated another seven in
143. ame system with 4008 4009 2 Memory address memory data 1 bus and control lines from both 4008 and 4009 are defined with respect to positive logic The MCS 4 data and control lines from the 4004 are defined with respect to negative logic As a result in program memory used with the 4009 programs should be coded with logic 1 high level and logic 0 low level i e 0000 0000 Note that programs are defined for the 4001 in terms of negative logic such that NOP 0000 0000 PPPP PPPP Carefully check all tapes submitted for metal mask ROMs to be sure that the correct logic definitions are used Input and output data from the 4009 I O bus is defined in terms of positive logic If these interface devices are used for prototyping a 4001 program memory care should be taken to be sure that the I O ports for the 4001s are defined consistent with the 4008 4009 system port associated with the 4009 can have lines with both input and output capability On the 4001 each I O line may have only a single function either input or output The RAM program memory cannot be used as a substitute for the 4002 read write data storage They perform distinctly different functions CM ROM and cannot be used to control 4002s when CM ROM is used for 4008 4009 and the WPM instruction is being used reason is that the WPM instruction is interpreted as a Write Memory WRM by 4002s connected to t
144. an I O instruction it will activate the CM ROM and one CM RAM line during M2 in time for 4001 s and 4002 s to receive the second part of the I O instruction The OPA portion of the I O instruction is a code specifying which I O operation should be performed There are 15 different operations possible The only ones affecting the 4001 OBSKSETDR are RDR read ROM port and WRR write ROM port In tie I O mode of operation the selected 4001 by SRC after receiving will transfer the information present at its I O pins to the data bus at X2 If the instruction received was WRR the data present on the data bus at 2 2 will be latched on the output flip flops associated with the I O lines Only one out of four CM RAM lines is allowed to be activated at any given time CM RAM line selection RAM bank switching is accomplished by the CPU when a designate command line DCL instruction is executed If no DCL is executed prior to SRC the CM RAM will automatically be activated at X2 provided that RESET was applied at least once to the System most likely at the start up time See detailed definition of system instruc tion in Section VII Figure 5 shows the block organization of the 4001 The ROM array has dynamic mode of operation and is divided into two blocks of 16 x 64 cells each Multiplexing is needed for both address to address register data to data bus output buffer operations _ The flip fl
145. any value other than the value 15 binary 1111 the instruction performs a JUMP to an address specified by the in struction This address must be on the same page within the same ROM as the instruction immediately following the ISZ If however the register originally contained 15 the CPU will proceed to execute the next instruction in sequence By loading a register say register 14 with the value 6 on the 10th execution of an ISZ the processor will proceed to the next instruction in sequence rather than jump Execution of the ISZ does not affect the accumulator so that the accumulator does not have to be saved prior to its execution The program sequence which performs the desired action is then Address Instruction Name Mnemonic Description 1 LDM 8 Load 1000 to accumulator 2 XCH 15 Exchange contents of index register 15 and accumulator 3 LDM 6 Load 0110 to accumulator 4 XCH 14 Exchange contents of index register 14 and accumulator 5 FIM 0 Fetch immediate from ROM Data 1100 0000 12 0 to index register pair location 0 6 SRC 0 Send address contents of index register pair 0 to RAM 7 LDM 0 Set accumulator to 0 8 LOOP ADD 15 Add contents of register 15 to accumu lator 9 WMP Write contents of accumulator into RAM output ports 10 ADD 15 Add contents of Register 15 to accumu lator 11 WMP Write contents of accumulator into RAM output ports 12 ISZ 14 Increment contents of reg
146. aracters for each 4002 register are arranged as follows 1 16 characters addressable by an SRC instruction Four 16 character registers constitute the main memory 2 4 characters addressable by the OPA of an I O instruction Four 4 character registers constitute the status character memory 21 Two separate X decoders switch between main status character memories When an I O or RAM instruction is received by the CPU the CPU will activate one CM RAM line during M5 in time for the 4002 s to receive the OPA 2nd part of the instruction which will specify the I O or RAM operation to be performed Shown below is a list of the 15 possible I O and RAM operations The I O and RAM operations are divided into Read operations IOR and Write operations IOW The state of D will determine if the operation is a read or a write 1 for D3 0 for IOW see Basic Instruction Set shown in Section IIIc For each I O instruction the action is as shown in the following table 4001 4002 4004 Data Bus Output I O Oper RAM Op Buffer Enabled E 4001 Data Bus Output Buffer Enabled 4002 Data Bus Output Buffer Enabled E RDR x KE wasa Ed WRR WR NE NEN WR2 uw A WR3 RE NN BECHER MIC NIE ADM x R RDI NEIN pu In the I O mode of operation the selected 4002 chip by SR
147. bsequent format error EXAMPLE 3 Typed P by 029 User 24 BNNNNPPPPN Listing FE 022 amp format error indicated at of address 022 too many char Tape by acters in data field TTY BNPNPNPNPF BPNM FE 024 6 format error indicated at address 024 illegal char acter in data field 6 sequence completed If data words are being entered manually and a format error is encountered programming may be continued by entering the PROGRAM command the address of the error and the final address The error may be corrected and programming completed ERROR CHECKING After each location in ROM is programmed the content of the location is read and compared against the programming data In the event that the programming is not correct the ROM location will be programmed again The MCS 4 programming system allows each location of the ROM to be reprogrammed up to four times will be printed for each reprogramming If a loca tion in ROM will not accept a data word after the fourth time the system will stop programming and will be printed This feature of the system guarantees that the programmed ROM will be correct and incompletely erased or defective ROM s will be identified 87 EXAMPLE 4 Typed P by 006 User 009 lst programming 2nd programming Listed as 3rd programming by 006 System BNNNPNPNPF 7 4
148. c to perform input and output operations The block diagram is shown in Figure 5 In the ROM mode of operation the 4001 will receive an 8 bit address during and A2 time see Figure 2 and a chip number together with CM ROM during A3 time When CM ROM is present only the chip whose metal option code matches the chip number code sent during CSE 1 is allowed to send data out during the following two cycles Mi and M2 The activity of the 4001 in the ROM mode ends at gt Before going into the I O mode of operation we must first review two basic instructions used in conjunc tion with it 1 SRC Instruction Send address to ROM and RAM When the CPU executes an SRC instruction it will send out 8 bits of data during and X3 and will activate the CM ROM and one 1 line at X2 Data at X2 with simultaneous presence of CM ROM is in terpreted by the 4001 as the chip number of the unit that should later perform an I O operation Data at X3 is ignored In the case of the 4002 data at X2 will designate the chip number one out of 4 chips and the register number one out of 4 registers data at X4 will desig nate the 4 bit character one out of 16 to be operated upon After SRC only one 4001 and one 4002 will be ready to execute a fotloviag 1 0 instruction 2 I O and RAM Instructions I O and RAM instructions allow the CPU to communicate with the I O ports of the 4001 s and 4002 s When the CPU receives
149. ccumulator is available on the Symbolic 4009 1 bus at X2 RAM program memory can be loaded four 1111 3 2 1 of 4008 bits at a time The previous SRC address is sent out on lines AO ACC 1 041 0951 041 Og of 4009 through A7 of 4008 SRC Address Ag A of 4008 System Illustrations Using the 4008 and 4009 Four systems are shown where the MCS 4 components are used with standard Intel memory elements as the program memory Notice that several different approaches to chip select port decoding and the 1 elements are shown Example 1 Four 1702 PROMSs and Four 1 Ports This configuration is equivalent to the SIM4 01 system Four 1702As are used for program storage and four four bit I O ports are used In this case D type output latches are used and a one of eight decoder 3205 is used to decode both the input and output strobes Note that the I O bus is buffered from the outputs Buffers are needed only when the current sinking require ment on the bus exceeds 1 6mA In small systems low power TTL could be used and buffers could be avoided Example 2 Read Write Memory for Program Storage This example shows only the RAM portion of a system when RAM is used for program memory Note that the chip selects are tied together in groups of four The chip selects are gated with the F L control line for writing only four bits at a time when executing a WPM instruction They are also gated with the decoding of the chip selects from t
150. computer in a 6 x 6 x 1 space replaces several racks of counters timers and relays that would otherwise be required Ac cording to Comstar the computer s flexible pro gramming is a major advantage Programs on PROMs can be changed half an hour Comstar estimates that the micro computer halved the cost of the control portion of this system and reduced the time required to build it by a factor of two or three The company is now building other types of systems with Intel micro computers including an automatic meat weighing and packaging machine SALES OFFICES NATIONAL SALES MANAGER U S REGIONAL SALES OFFICES CALIFORNIA CALIFORNIA MASSACHUSETTS MINNESOTA Hank O Hara William T O Brien Myles Franklin Mick Carrier j 3065 Bowers Avenue 408 246 7501 TWX 910 338 0026 Telex 34 6372 Santa Clara 95051 ARIZONA Engineering Sales 7155 E Thomas Road No 6 602 945 5781 Scottsdale 85252 CALIFORNIA Jess Huffman 3065 Bowers Avenue 408 246 7501 Santa Clara 95051 Jerry Plymire 3065 Bowers Avenue 408 246 7501 Santa Clara 95051 John Alfoldy 17401 Irvine Blvd Suit K 714 838 1126 TWX 910 595 1114 Tustin 92680 Jim Saxton 17401 Irvine Bivd Suite K 714 838 1126 TWX 910 595 1114 Tustin 92680 Dave Neubauer 17401 Irvine Blvd Suite K 714 838 1126 TWX 910 595 1114 Tustin 92680 Earle Associates Inc 4433 Convoy Street Suite A 714 278 5441 San Diego 92111 COLORADO
151. d RAM status character 3 into accumulator ACCUMULATOR GROUP INSTRUCTIONS 0000 Decrement accumulator 1 Transfer carry subtract and clear carry 010 Set carry O 1 1 Decimal adjust accumulator Keyboard process Converts the contents of the accumulator one out of four code to a binary code 110 1 Designate command line NOTES 1 condition code is assigned as follows 1 Invert jump condition C 1 Jump if accumulator is zero Ca 1 Jump if test signal is a 0 0 Not invert jump condition 1 Jump if carry link is a 1 2 RRR is the address of 1 of 8 index register pairs in the CPU 3 RRRR is the address of 1 of 16 index registers in the CPU 4 Each RAM chip has 4 registers each with twenty 4 bit characters subdivided into 16 main memory characters and 4 status characters Chip number RAM register and main memory character are addressed by an SRC instruction For the selected chip and register however status character locations are selected by the instruction code OPA 5 Extended Mnemonic 6 The SIM4 Hardware Assembler is currently being modified to accept the WPM instruction associated with the 4008 4009 137 SAMPLE ASSEMBLY with a STEP by STEP PROCEDURE As an example assume that one wishes to perform a logical and function on the data at two 4 bit ROM input ports and display the result at a RAM output port The first step of
152. d after appli cation of at lease one RESET DCL remains latched until it is changed The selection is made according to the following truth table ACC CM Enabled Bank No Bank O CM X001 RAM 1 X010 CM 2 Bank 2 X100 CM RAM3 Bank 3 X011 RAM4 RAM2 Bank 4 X101 CM RAM3 Bank 5 X110 CM 2 CM RAM3 Bank 6 X111 CM RAM2 Bank 7 3205 3 of 8 decoder or low power TTL equivalent may be tied to the CM RAM1 CM RAMg and CM RAM3 lines to expand the number of RAM banks to 8 Note that the command lines must be buffered for MOS compatibility See below RAM BANK 0 RAM BANK i 3205 DECODER BANK7 VIII AN INTRODUCTION PROGRAMMING THE 4 A Introduction Writing sequences of instructions for a computer is known as programm ing be able to program a computer effectively the programmer must understand the action of each of the machine instructions The instruction set of the MCS 4 is described in detail in the last section Each machine instruction manipulates data in some way The data may be the contents of the program counter which indicates where the next instruction is to be found the contents of one of the CPU registers accumulator or carry flip flop the contents of RAM or ROM or the signals at a port Programming is probably most ea
153. d to AC The result is then stored back into index register 3 Next the content of index register 2 IR 2 is transfered to AC and the content of index register 4 which is zero is added to AC and the result is stored back into index register 2 The process of checking the second digit is repeated until it is down count to zero Then the program proceeds to set IR 4 to 6 and IR 5 to 4 examines the last BCD digit which is the content of character 2 in the RAM and repeats the process in the same manner except in this case the content of IR 5 is added to index register 3 and the contents of IR 4 is added to index register 2 This is equivalent to adding 100 in binary form to an 8 bit binary number The binary number obtained is stored in IR 2 and IR 3 IR 3 contains the lower order 4 bits and IR 2 contains the higher order 4 bits Index register 6 IR 6 is used as a digit counter to verify that all the 3 BCD digits has been checked The following flow chart further explains the details of the program BCD TO BINARY CONVERSION ROUTINE 0000 90240 0001 0000 FIM 0 lt 0 iR Q 10 0 0002 0042 0093 0990 FIM 1 lt 30 iRC2 320z20 0044 06095 0012 FIM 2 lt 10 1 4 50 1 5 1 10026 0336 LDM 14 LOAD AC WITH 14 0007 0266 XCH 6 EXCHANGE IRC6 AN AC 90010 3841 SKC 9 lt Z DEFINE RAM ADDRESS 0011 0351 RDM READ RAM DATA AC 0012 9263 XCH 3 EXCHANGE AC WITH 1603 0013 0141 BDBN I
154. data read from the PROM is complemented 3 Data out switch Enable Disable If this switch is in the enable position data may be read from the In the disable position the output line may float up to a high level logic 1 As a result the input ports on the prototype system be used for other functions without removing the MP7 03 card MP7 03 Programmer Board Specifications Features Connector High speed programming of Intel s new a Solder lug type Amphenol 1702A three minutes 72 pin connector e Inputs and outputs TTL P N 225 23621 101 compatible b Wire wrap type Amphenol e Board sold complete with trans 72 pin connector formers capacitor and connector P N 261 15636 e Directly interfaces with SIM4 01 c Wire wrap type CDC or SIM4 02 Boards 72 pin connector P N VPBO1E36E00A1 Dimensions 8 4 inches high 9 5 inches deep Power Requirement Vcc 45 0 8 amps ps po may be 2 TTL GRD 0V Supp Y ecause a patr o 19 es 1 6 V 10V 0 1 amps or equivalent are located on the board in DD 4 series with the supply Select the appropriate Vp 50Vrms 1 amp pin for either 9V or 10V operation A micro computer bulletin which describes the modification of the MP7 02 for programming the 1602 1702 is available on request These modifications include complete failsafe circuitry now on MP7 03 to protect the PROMs and the 5OV power supply 89 MCB4 10 SYSTEM INTERCONNECT and CONT
155. ddress is incremented by 2 to correctly give the address of the next instruction to be executed after the return from JMS 12 ADDRESS REGISTER ADDRESS REGISTER JMS 1 RECEIVED E z gt PROGRAM COUNTER RETURN ADDRESS 1 PROGRAM COUNTER PUSHED UP ONE LEVEL JMS 2 JMS 3 RECEIVED PROGRAM COUNTER RECEIVED RETURN ADDRESS 3 RETURN ADDRESS 2 RETURN ADDRESS 2 RETURN ADDRESS 1 RETURN ADDRESS 1 RETURN ADDRESS 3 Ba RECEIVED RECEIVED THE 5 RETURN ADDRESS 15 LOST PROGRAM COUNTER PUSHED DOWN ONE LEVEL Table IV Operation of the Address Register on a Jump to Subroutine Instruction In summary then a JMS instruction pushes the program counter up one level and a BBL instruction pushes the program counter down one level Since there are 3 registers in the push down stack 3 return addresses may be saved If a fourth JMS occurs the deepest return address the first one stored is lost Table IV shows the operation of the address stack 4 Operation of The Command Lines and the SRC Command The CPU command lines CM ROM used to control the ROM s and RAM s by indicating to them how to interpret the data bus content at any given time The command lines allow the implementation of RAM bank chip register and character addressing ROM chip addressing as well as activating the instruction control in each ROM and RAM chip at the time the CPU rece
156. ding the selected RAM address 157 14 Loop Increment contents of register 1110 Jump if result 0 otherwise skip The loop above uses 3 pairs of registers for RAM and port selection and two registers for temporary storage and indexing The initiali zation must provide for loading each of these registers Example 5 The example above might be extended if for example the 4003 s were driving seven segment LED displays 4 line to 7 segment code con verter could be used for each display device driven However the ROM table lookup capability of the 4004 can be utilized to advantage to save these converters Suppose the LED displays are wired as shown in Fig 10 with each LED using two adjacent locations in each of the 4003 s The instruction FIN allows a ROM table to be accessed based on the contents of registers and 1 save register space the fetched data may be loaded over the table addresses The table address may be intialized by an FIM or by the sequence LDM XCH where the data in the LDM represents the high order 4 bits of the table address The low order 4 bits will be derived from the data character itself The loop now becomes as follows FIM 0 initial table address SRC fetch data character RDM Read into ACC XCH T store at register 1 FIN 0 fetch from ROM table SRC select output port XCH 0 fetch 151 half of 7 segments WMP transfer to output port SRC select clock port LDM 0 Set
157. dle portion in OPR and lower portion in of another ROM address or 8 bits of data the upper 4 bits in OPR and the lower 4 bits in OPA The upper 4 bits of instruction will always be fetched before the lower 4 bits of instruction during M and M5 times respectively Table I illustrates the contents of each 4 bit field in the machine instructions b Input Output amp RAM Instructions and Accumulator Group Instructions In these instructions which are all single word the OPR contains a 4 bit code which identifies either the I O instruction or the accumulator group instruction and the OPA contains a 4 bit code which identifies the operation to be performed Table illustrates the contents of each 4 bit field D D D D D D D OPR OPA INPUT OUTPUT amp RAM INSTRUCTIONS ACCUMULATOR GROUP INSTRUCTIONS WHERE X EITHER 0 OR A 1 Table I and Accumulator Group Instruction Formats 11 2 Index Register Organization The index register can be addressed in two modes a By specifying 1 out of 16 possible locations with an code of the form RRRR D See Table III b By specifying 1 out of 8 pairs with an code of the form RRRX 2 See Table III When the index register is used as a pair register the even number register RRRO is used as the location of the middle address or the upper data fetched from the ROM the odd number register RRR1 is used as
158. dna Terrace 312 593 0230 513 771 6441 Cincinnati 45215 Sheridan Assoc Inc 10 Knolicrest Drive 513 761 5432 Cincinnati 45237 Cramer Cleveland 5835 Harper Road 216 248 7740 Cleveland 44139 Sheridan Assoc Inc 7800 Wall Street 216 524 8120 Cleveland 44125 Sheridan Assoc Inc Shiloh Bldg Suite 250 5045 North Main St 513 277 8911 Dayton 45405 TEXAS Cramer Electronics 2970 Blystone 214 350 1355 Dallas 75220 Hamilton A vnet Electronics 2403 Farrington 214 638 2850 Dallas 75207 Hamilton Avnet Electronics 1216 West Clay 713 526 4661 Houston 77019 WISCONSIN Cramer Wisconsin 5626 N 91st Street 414 462 8300 Milwaukee 53225 173 NORTHEAST CONNECTICUT Cramer Connecticut 35 Dodge Avenue North Haven 203 239 5641 New Haven 06473 MARYLAND Cramer EW Baltimore 922 24 Patapsco Avenue 301 354 0100 Baltimore 21230 Cramer EW Washington 16021 Industrial Drive 301 948 0110 Gaithersburg 20760 Hamilton Avnet Electronics 7255 Standard Drive 301 796 5000 Hanover 20176 MASSACHUSETTS Cramer Electronics Inc 85 Wells Avenue 617 969 7700 Newton 02159 Hamilton Avnet Electronics 185 Cambridge Street 617 273 2120 Burlington 01803 NEW JERSEY Hamilton Electro Sales 220 Little Falls Road 201 239 0800 Cedar Grove 07009 Cramer New Jersey No 1 Barett Avenue 201 935 5600 Moonachie 07074 Hamilton Avnet Electronics 1608 Mariton Pike 609 662 9337 Cherry Hill 08034 Crame
159. e a number of display devices are activated one at a time in rapid sequence For sufficiently rapid scanning the eye accepts the data as a continuous display To use the multiplexed mode the dis play device usually requires some form of coincident selection technique For example NIXIE tubes are activated only when the anode supply is present at the same time that the appropri ate cathode is grounded through the proper resistance In a multiplexed NIXIE array one set of 10 or 11 cathode drivers is used in combination with one anode driver for each NIXIE tube Under program control the array is scanned One tube is selected the cathode driver corresponding to the numeral for that position is activated and then the anode driver for that position is activated for a period The same steps are executed for the next position in turn To avoid flicker a scan rate of approximately 100 complete scans per second or higher should be maintained This figure allows a scanning program to have up to 60 instruction execu tions per displayed digit giving a l6 digit display Multiplexed displays typically require high peak driving cur rents to maintain reasonable average brightness The drivers used must be capable of supplying the peak currents Although the technique described above specifically mentioned NIXIE tubes the same technique can be applied to 7 segment LED numeral displays In systems which combine a numeric display and a
160. e 3205 decoder indicates which cycle the unit is executing i e the Aj the the the etc discrete transistors serve to convert data bus levels to TTL levels and vice versa Two 3404 hex latches are wired as the equivalent of three quad latch units These latches act as address registers for the 1701 or 1702 memory array The quad latch units are loaded on the 1 A2 and cycles respectively Those address bits loaded during and A2 drive the 1701 or 1702 address line directly while a 3205 decoder is used to generate the chip select signals for the 1701 or 1702 memory array from the four bits loaded during A3 Two such decoders would be used if a full array of sixteen 1701 s or 1702 s were to be utilized The output of the 1701 or 1702 array is one byte or 8 bits wide multiplexer is used to gate four bits at a time onto the four bit wide data bus first four bits are selected on the 1 cycle the second four bits on the M2 cycle signals at the output of the multiplexer are at TTL levels These levels are converted to the MOS levels on the 4004 data bus by means of set of four discrete level shifter circuits The pull down resistors for these circuits are connected via diode disconnects to a pull down resistor activator circuit This circuit is activated during the Mj and cycles via the two input NAND gate driver This driver receives two of its three inputs from the Mj and M2 decoder The b
161. e to avoid making the whole line a comment line All labels must conform to the rules for the orthography of names Every name used in an operand field in the program to be assembled must occur exactly once in a label field and the numeric value of the name is equal to the address of the instruction or datum on the line with the lable or the value assigned to the label by the pseudo op If the name occurs in more than one label field an error is indicated and the most recent value applies If the name does not occur in a label field an error is indicated and the value zero 0 is used 132 Instruction Mnemonics All of the instruction mnemonics defined in the MCS 4 Users Manual are recognized by the assembler In addition the following extended mnemonics are recognized as particular cases of the conditional jump JTZ Jump on test zero JTN Jump on test not zero on test one JCZ Jump on carry line zero JNC Jump on no carry i e JCO Jump on carry link one JOC Jump on carry JAZ Jump on accumulator zero JNZ Jump on accumulator not zero JAN Jump on accumulator not zero All of the memory and accumulator group instructions and the NOP instruction require no operand field the 152 FIM and JCN instructions require two operand fields all other instructions including the extended mnemonics for the conditional jump instruction require one operand field Pseudo Operators The assembler is provided with
162. e user may type 11000 T5040 or he might type 1000 JO 500 in each case waiting for a before typing the next command line In the second case the instructions between and 100 are executed where in the first case they are not 162 At a break or in trace mode the contents of CPU registers are displayed The following sequence is used for long form output Program counter 4 digit decimal Instruction and 3 character symbolic OP code Modifiers 2 characacter modifier 4 character address or data CY FF 1 digit 0 1 Accumulator 2 digit decimal 8 15 Registers 16 hexadecimal characters in order to R15 RAM Bank No 1 digit decimal RAM Register No 2 digit decimal RAM Main Char No 2 digit decimal Cycle counter 5 digit decimal Short form output omits the modifier and RAM data When an RDR instruction read ROM port is executed the simu lator types INPUT REQUESTED FROM ROM PORT N IN DEC The us r types a one or two digit decimal value corresponding to the 4 lines of the input port When short form messages are used the request message is ROMPT INPUT N 163 Note on use of input files The simulator program will request an input file name with the message INPUT FILE NAME To input the standard data file ROMAR DAT merely type a carriage return However it is possible to break a program into segments and load several of the segments into the simulator one at a
163. ecking and listing functions For high speed programming of Intel s new 1702A three minutes use control A0543 in place of A0542 3 programmer 7 03 This is the programmer board which contains all of the timing and level shifting required to program the Intel ROMs This is the successor of the MP7 02 4 ASR 33 Automatic Send Receive Teletype This provides both the keyboard and paper tape 1 devices for the programming system In addition a short wave ultraviolet light is required if the erasable and reprogrammable 1702s are used This system has two modes of operation 1 Automatic A paper tape is used in conjunction with the tape reader on the teletype The tape contains the program for the ROM 2 Manual The keyboard of the TTY is used to enter the data content of the word to be programmed PROGRAMMING THE 1602 1702 Information is introduced by selectively programming 1 s output high and O s output low into the proper bit locations Note that these ROMs are defined in terms of positive logic Word address selection is done by the same decoding circuitry used in the READ mode The eight output terminals are used as data inputs to determine the information pattern in the eight bits of each word A low data input level ground P on tape will leave a 1 and a high data input level 48V N on tape will allow programming of 0 All eight bits of one word are
164. em flexibility with easy program changes ability to expand or shrink the system and small size and low power Expediency of design because ROM programming is easier than random circuit design system checkout is easier using electri cally programmable and erasable ROM s and ability to insert new microprograms helps prevent system obsolescence Manufacturing economies come from simple DIP package design automatic insertion lower labor costs lower of parts boards When designing with random logic logic gates flip flops etc the designer will usually start with a description of the desired function and attempt to wire counters gates etc to achieve this function Switches displays etc are also connected to the logic To correct errors or make changes in a design usually requires sig nificant changes in wiring often requiring that circuit boards be and replaced by new ones To do the same design with the MCS 4 Micro Computer Set the designer again starts with the functional description However he implements these functions by encoding suitable sequences of instructions in ROM The MCS 4 instruction set is quite complete and allows a wide variety of functions to be performed decimal or binary arithmetic counting decisions table lookup etc Switches displays etc are connected to the system via the input and output ports As a result of this organization almost the entire logic the ent
165. emonic IAC Increment accumulator OPR OPA 1111 0010 Symbolic ACC 1 gt ACC Description The content of the accumulator is incremented by 1 overflow sets the carry link to 0 overflow sets the carry link to a 1 Mnemonic DAC decrement accumulator OPR OPA 1111 1000 Symbolic ACC 1 gt ACC Description The content of the accumulator is decremented by 1 A borrow sets the carry link to 0 no borrow sets the carry link to a 1 EXAMPLE ACC aj a 1 1 1 1 53 52 51 50 a CY ACC Mnemonic RAL Rotate left OPR OPA 1111 0101 Symbolic Co ag ai 1 CY Description The content of the accumulator and carry link are rotated left Mnemonic RAR Rotate right OPR OPA 1111 0110 Symbolic aj 1 Description The content of the accumulator and carry link are rotated right Mnemonic TCC Transmit carry and clear OPR 1111 0111 Symbolic 0 gt CY ag 0 Description The accumulator is cleared The least significant posi tion of the accumulator is set to the value of the carry link The carry link s set to O Mnemonic DAA Decimal adjust accumulator OPR 1111 1011 Symbolic ACC 0000 Em ACC or 0110 Description The accumulator is incremented by 6 if either the carry link is l or if the accumulator content is greater than 9 The carry link is set to a l if the result generates a carry otherwise it is un
166. emory and Interface Set 4008 4009 D SIM4 01 Prototype System E SIM4 02 Prototype System Sample Sixteen Digit Decimal Addition Program Intel ROM Program Number A0700 MCS 4 PROM Programming System A General System Description and Operating Instructions B MP7 03 Programming System MCS 4 Evaluation Kit Using the 4001 0009 Appendices Electrical Characteristics of the MCS 4 System Applications of the 4008 4009 MCS 4 Custom ROM Order Form Teletype Modifications for SIM4 01 SIM4 02 System Interface and Control Modules 4 10 4 20 SIM4 Hardware Assembler for SIM4 01 or SIM4 02 SIM4 Hardware Simulator MCS 4 Fortran Assembler Simulator Software Package MCS Programming Examples gt gt Ordering Information A Sales Offices B Distributors C Ordering Information Packaging Information NOTICE The circuits contained herein are suggested applications only Intel Corporation makes no warranties whatsoever with res pect to the completeness accuracy patent or copyright status or applicability of the circuits to a user s requirements The user is cautioned to check these circuits for applicability to his specific situation prior to use The user is further cautioned that in the event a patent or copyright claim is made against him as a result of the use of these circuits Intel shall have no liability to user with respect to any such claim 1 io
167. er and character and a ROM chip This address is sent to the data bus during X2 and X3 time of the SRC instruction cycle At X2 time the CM ROM line and the selected line are a logic true state to indicate which bank of RAMs and ROMs are to respond to the 8 bit address that is now on the data bus The 8 bit address is interpreted in the following way a The first 4 bits X2 time select one chip out of 16 a flip flop is by the ROM s set in the selected chip b The second 4 bits time are ignored a The first four bits sent out at X2 time Select one out of four chips and one out of four registers The two higher order bits D3 02 select the chip and the two lower order bits D1 Do select the register b The second 4 bits X4 time select one 4 bit character out of 16 address is stored in the address register of the selected chip See Section V for a detailed description of the RAM chip At this time one ROM chip and one RAM chip register and character have been selected the CPU fetches an 1 0 and RAM instruction it will cause the CM ROM and the selected line to be logical true at 2 time This allows the previously selected ROM s and RAM s to receive the modifier of the instruction The selected ROM and RAM will decode the instruction as well as the CPU and appropriately execute it during the execution time of the same instruction cycle It should be added that the CM
168. er has three possible states 1 0 and floating At a given time only 1 output buffer is allowed to drive a data line therefore all the other buffers must be in a floating condition However more than 1 input buffer per data line can receive data at the same time II 4 BIT CENTRAL PROCESSOR UNIT CPU 4004 A Description The 4004 block diagram shown in Figure 3 contains the following functional blocks 1 Address register program counter and stack organizaed as 4 words of 12 bits each and address incrementer 2 Index register 64 bits organized as l6 words of 4 bits each 3 4 bit adder 4 Instruction register 8 bits wide decoder and control 5 Peripheral circuitry The functional blocks communicate internally through a 4 line bus and are shown in Figure 3 The function and composition of each block is as follows ROM CM ROM OUTPUT BUFFER RAMo RAM 4 SYNC 1 Address Register Program counter amp Stack amp Address Incrementer The address register is a dynamic RAM cell array of 4 x 12 bits It contains one level used to store the instruction address program counter and 3 levels used as a stack for subroutine calls The stack address is provided by the effective address counter and by the refresh counter and it is multiplexed to the decoder The address when read is stored in an address buffer and is demultiplexed to the inte
169. eviously selected RAM status character 3 into accumulator DESCRIPTION OF OPERATION ACCUMULATOR GROUP INSTRUCTIONS Transfer carry subtract and clear carry CLC 2 E r TCC STC Set carry Decimal adjust accumulator Keyboard process Converts the contents of the accumulator from a one out of four code to a binary code Designate command line 1 Invert jump condition 1 Jump if accumulator is zero 1 Jump if test signal is 0 0 Notinvert jump condition Ca 1 Jump if carry link is a 1 DCL NOTES 1 The condition code is assigned as follows RR is the address of 1 of 8 index register pairs in the CPU is the address of 1 of 16 index registers the CPU Each RAM chip has 4 registers each with twenty 4 bit characters subdivided into 16 main memory characters and 4 status characters Chip number RAM register and main memory character are addressed by an SRC instruction For the selected chip and register however status character locations are selected by the instruction code OPA Table V Basic CPU Instruction Set Continued 17 IV 4001 256 8 MASK PROGRAMMABLE ROM AND 4 BIT PORT 1 The 4001 performs two basic and distinct functions As a ROM it stores 256 x 8 words of program or data tables as a vehicle of communication with peripheral devices it is provided with 4 I O pins and associated control logi
170. f bytes one or two occupied by the instruction and the types of modifiers which must accompany the instruction are also indicated in Table 1 The types of modifiers required may be none as in the case of NOP CLB CLC etc a register designator indicating one of the sixteen registers on the central processor chip as in the case of Add Load Exchange etc a 4 bit data item as in the case of the BBL or LDM instruc tion an 8 bit data item as in the case of the FIM instruction a register pair designator as in the case of the SRC or JIN instruc tion an 8 bit address as in the case of the ISZ or a 12 bit address as in the case of the JUN instruction In general such addresses will be expressed symbolically by use of labels The JCN FIM and ISZ instructions require two modifiers The JCN must include a condition code in addition to the address code The ISZ instruction must include a single register designator as well as address code while the FIM requires a register pair designation and an 8 bit data item In each case the modifiers must occur in the sequence shown with address or data items following condition codes register or register pair designations For use by the assembler numeric data may be entered in binary decimal or octal format See below under Pseudo Operators 153 INSTRUCTION No Operation Jump Conditional Fetch Immediate Send Register Control Fetch Indirect Jump Indirect Jump Unconditional Jump
171. f this error correcting feature is shown below TYPED ON TTY PROGRAMMED IN ROM one letter removed BNPPNN PNPN NNF gt NPPNPNNN last two letters removed BNNPPNPBNPPPNPNPF NPPPNPNP data word eliminated If any character other than P or N is entered a format error is indicated If the stop character is entered before the error is noticed the entire word field including the B and F must be rubbed out Within the word field a P results in a high level output and N results in a low level output The first data character corresponds to the desired output for data bit 8 pin 11 the second for data bit 7 pin 10 etc 3 Preceding the first word field and following the last word field there must be a leader trailer length of at least 25 characters This should consist of rubout punches 83 4 Between word fields comments not PROM PIN CONFIGURATION containing B s or F s may be inserted az 62 It is important that a carriage return Ai 1 and line feed characters be inserted Ao 2 as a comment just before each DATA OUT 1 As word field or at least between every DESNUDO Aa four word fields When these carriage s DATA OUT 4 returns are inserted the tape may be easily listed on the teletype for purposes of error checking It may also be helpful to insert the word number as a comment at least las SENE every four word fields THIS PIN IS THE DATA INPUT LEA
172. g to key status information for one column of the keyboard arrays execution of the KBP rearranges the data as follows 1 If no key is pressed 0000 the ACC remains at 0000 2 If more than one key is pressed ACC is set to 1111 3 If one key is pressed the ACC indicates the bit position of the key as shown below ACC before ACC after 0001 0001 0010 E 0010 0100 06043 1000 0100 Scanning of keyboard is implemented by moving single in a field of 1 5 across the lines driving the keyboard inputs The 4003 shift register is useful for generating the scans addition the 4003 has the characteristic that if two outputs are connected with one at a logic 1 6v and the other at a logic the result will be equivalent to a logic scanning a keyboard with a moving multiple key presses in a row can be resolved Furthermore if the 4003 is disabled all outputs go to logic and all keys can be sampled simutaneously to determine if a scan is required Figure 13 shows the keyboard interface The ROM inputs are complemented Debouncing of the keyboard inputs etc is accomplished by testing for the same press condition on several successive scans Figure 13 Keyboard Interface Scanned Array 52 Display Display devices such as NIXIE tubes and LED arrays are easily interfaced to the MCS 4 system These displays may be DC driven or multiplexed In the multiplexed mod
173. gned to operate with all types of terminal devices typical example of peripheral interface is the teletype ASR 33 The SIM4 contains three simple transistor TTY interface circuits Refer 58 SIM4 01 SIM4 02 FULL DUPLEX RECEIVE _ FULL DUPLEX RECEIVE Teletype Terminal Strip See Appendix D for details to the appropriate SIM4 schematics for the actual circuit diagrams transistor is used for receiving serial data from the teletype one for transmitting data back to the teletype and the third for tape reader control The teletype must be operating in the full duplex mode Refer to your teletype operating manual for making connections within the TTY itself Since all teletypes are not identical it is impossible to present a general interconnection scheme with either of the SIM4 boards Many models include a nine terminal barrier strip in the rear of the machine It is at this point where the connections are made for full duplex oper ation interconnections to the SIM4 for transmit and receive are made at this same point use the teletype reader with the SIM4 the machine must contain reader power pack The contacts of a 10V dc relay must be connected in series with the TTY automatic reader refer to TTY manual and the coil is connected to the SIM4 tape reader control as shown This relay must be supplied by the user Note that the SIM4 clock generator must remain set at 750 kHz In order t
174. good teletypist may type the source program directly on line with the perforator turned using the punched tape to feed the source back in on pass 2 This tape may also be edited manually off line for purposes of updating the program for re assembly Most minor errors in typing may be corrected by cancelling the line control X or escape and restarting or by modification of the partially typed line 129 A combination of the two methods is also possible reading the tape from an earlier edition in on pass 1 with the perforator turned on making corrections manually by stopping the reader pulling portions to be deleted through and keying in portions to be added The repunched tape is used as text input on pass 2 Samples of the listing generated during pass 1 and pass 2 are given in Figures 2 1 and 2 2 Another example with a step by step procedure is given in Appendix B 0 7 TYPICAL ASSEMBLY FOR A VERY SMALL SAMPLE PROGRAM 0 PS 10 ASSIGN VALUE 10 TO NAME PS 0 15 15 16 1 CLB 17 FIM P5 89 NOTE COMMENT 19 SRC 5 20 sLAB2 RDR 21 JTN LAB2 23 JMS TR3 251 JUN 27 TR3 L DM 28 ADD 29 XCH 30 BBL 31 Figure 2 1 Pass 1 Listing 0 0 0 15 BPPPPPPPPF 16 BNNNNPPPPF 1 7 BPPNPNPNPF BPNPNNPPNF 19 BPPNPNPNNF 20 BNNNPNPNPF 21 BPPPNNPPNF BPPPNPNPPF 23 BPNPNPPPPF BPPPNNPNNF _ 25 BPNPPPPPPF BPPPNPPPPF 27 28BNPPPNPNNF 29 BNPNNPNPNF 30 BNNPPPNNNF 312
175. he 4008 for normal program execution The 1101 256 words x 1 bit is shown A similar system using the 2102 1k words x 1 bit could be developed Example 3 Seven 1702 PROMs one RAM block and seven 1 Ports This example uses a single page of RAM program memory shown in Example 2 in a complete yaten In this case the input ports 8 1 multiplexes which are buffered from the 1 0 bus by a quad three state buffer The input port selection is then the function of the multiplexers The output ports are Intel 3404 latches and the port selection is done using an Intel 3205 decoder Example 4 Eight 1702A PROMs eight RAM Blocks eight 1 Ports Program memory organized with 2k bytes in ROM and 2k bytes in RAM Each basic RAM block can be organized as in Exemple 2 When more than one block of RAM is used the write chip select WCS for each RAM block is generated by properly gating chip select 15 with special decoding for page selection Output port eight is dedicated to this selection function This is only necessary when the RAM program memory is being written In this example standard TTL logic elements are used for I O port selection rather than decoders as shown in previous examples In this case all input ports are three state buffers IMPORTANT The following differences exist between an MCS 4 system using 4001 program memory a system using 4C08 4009 program memory 1 For normal operation 4001 ROMs cannot be used in the s
176. he assembler constructs a name table from the source text and generates a listing The source text entries are prompted by an address location printed on each line of the listing Paper tape reader on off controls are issued by the assembler during the prompting Diagnostics are performed during pass 1 Errors such as duplicated labels name table overflows and unrecognized instruction mnemonics are flagged Operator intervention of the reader operation and subsequent keyboard entries can be used to edit an erroneous source entry A programming tape and a listing of its contents are created during pass 2 Entry of the source tape and any editing during pass 1 must be repeated The assembler decodes the instruction mnemonics searches the name table for addresses and forms binary representations of the machine instructions Simultaneously it controls the read operation punches and lists the object tape and executes further diagnostics The diagnostics will flag errors such as unrecognized instruction mnemonics undefined names and off page references Operating Procedures Two normal modes of operation are possible with the assembler A source tape may be prepared in advance off line using the perforator backspace and rubout character to correct minor errors This tape may be fed with the reader to the assembler twice with the perforator turned off during pass 1 and on during pass 2 if a ROM programmer tape is desired Alternatively
177. he number entered is added to the content of the accumu lator 5 This procedure may be repeated until the content of the sixteen digit accumulator overflows X s will be printed This overflow will automatically reset the system 6 To reset the system at any other time use the reset switch This program uses both the keyboard process routine and decimal addition routine explained earlier in this manual In addition the TTY printing subroutine is used Example of Addition Program Printout On Teletype 1234 Reset System Enter number and add command 1234 Printed result 22 Enter number and add command 1256 Printed result 1111111111111111 Enter sixteen digits 1111111111112367 Printed result 9999999999999999 Enter sixteen digits FR Resulting overflow System automatically reset The listing of tape A0700 follows 77 0000 0001 0002 02093 902004 0205 0206 0207 0010 0211 0012 0013 0014 0015 0216 0017 0220 0021 0222 0023 24 025 0026 0227 0030 0031 0032 0033 0034 00935 0036 0037 0040 0241 0049 0043 0044 9045 0046 0047 0050 9051 0252 0053 0054 0855 0856 0057 0060 0061 0062 0863 0064 0065 0066 0067 0070 0071 0072 0073 0074 0075 0076 0077 01092 SIXTEEN DIGIT INTEGER ADDITION MICROPROGRAM WITH TTY KEYBOARD AND PRINTER INTERFACE 0337 0048 0900 09841 0341 0320 0244 00929 0046 001
178. he same CM line as 4008 4009 in absence of DCL behaves exactly like CM ROM 110 CM RAM 0 DATA BUS i1702A ROM 0 i1702A ROM 3 cs THREE STATE BUFFER YYY B gua LP 4 BIT OUTPUT D 0 ERE LPABIT OUTPUT TYPE LATCH PORT 3 EIL THREE STATE Z INPUT BUFFER 2 PORTO CET THREE STATE INPUT BUFFER PORT 3 Example 1 Four 1702As and Four 1 0 Ports SIM4 01 Equivalent RCSi CHIP SELECT DECODED FROM 4008 WCSi F L WRITE CHIP SELECT ACTIVE LOW w gt SE DERIVED FROM ALL 4008 CHIP SELECTS HIGH READ CHIP SELECT ACTIVE LOW WRITE CONTROL FROM 4008 6 8k 2 n ADDRESS J FROM 4008 11111111 111111 ar z z i1101 a FROM NOTE THAT A SIMILAR MEMORY MODULE CAN BE DEVELOPED USING INTEL S PO RUE 2102 1k STATIC RAM AN OUTPUT PORT MUST BE USED TO SUPPLY HIGHER ORDER ADDRESS BITS FOR WRITING A 2102 MEMORY HANDLE IN THE SAME MANNER AS A MULTIPLE PAGE 1101 SYSTEM Example 2 Read Write Memory for Program Storage 111 j THREE STATE BUFFER V V L 1702 _ a tt OUTPUT PORT 0 OUTPUT PORT 1 OUTPUT PORT 6 0 OUT RAM 3 OUT 2 THREE 5 INO BUFFER i1702A 7 k o Ep n DATA INPUT TO ALL RAMs RAM memory is used f
179. he tape reader in the free off condition and position the tape on the leader 11 The assembler will punch approximately 12 inches of leader and wait for reader input 12 Place the reader in the start mode The assembler will read the tape ignore comments and output line addresses and formatted instruction codes With the punch on a programming tape is created and a listing of the tape such as that shown in figure B 3 is generated Any editing performed during pass 1 must be repeated during pass 2 0 BPPNPNPPPF BPPPPPPPNF 2 BPPNPNPPNF 31 BNNNPNPNPF 43 BNPNNPPPPF S BPNNPNPPPF 6 BPPNPNPPNF 7 BNNNPNPNPF 6 BNPNNPPPNF 9 BPNPNPPPPF BPNNPNPPPF 11 BNPNNPPNPF 12 BNNNPPPPNF 13 BPNPPPPPPF BPPPPPPPPF 15 BPPPPPPPPF 16 104 104 BNNNNPPPPF 105 BNPNNPPNPF 106 BNNPNPNPPF 107 BNPNNPPPP 198 BNNNNPNNPF 109 BNPNNPPPPF 110 BPPPNNPNPF BPNNNNPNPF 112 BNPNNPPPNF 113 BNNNNPNNPF 11 4 BNPNNPPPNF 115 BNPNNPPNPF 116 BNNNNPNNPF 117 BNPNNPPNPF 118 BNNNNNPPPF 1193 BPPPNNNPPF BPNNPNPNNF 121 122 BNPNNPPPNF 123 BNNNNPNNPF 124 BNPNNPPPNF 125 BNNNNPPPNF 126 BPNPPPPPPF BPNNNPPNNF 128 128 128 F Figure 3 Programming Tape Listing Completion of pass 2 is signalled by the printing of an F and the punching of a 12 inch trailer At this point the assembly is complete and PROM or ROM programming may proceed 140 APPENDIX G SIM4 HARDWARE SIMULATOR INTRODUCTION The SI
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181. icating or comparing BANK 0 RAM O Bit 2 will light To continue press Test other wise press Reset and remove Programmed During duplicating or comparing four passes are made before claiming an error DURING DUPLICATE PROMs ARE AUTOMATICALLY COMPARED AFTER EACH LOCATION IS PROGRAMMED b If the program finishes Bank 0 RAM O Bit 3 will light Remove to be Programmed 16 Remove REF PROM from socket 17 Turn PRGM AC switch Off 18 Turn DC Power switch Off e LINE SOCKET GND IOV 45v FI 5 8 49 ll MER CES CONNECT TTY DISCONNECT SIM 4 02 DUPLICATE ENABLE RAM OUT BANK O BANI DISABLE eee 2 2 9 3 2 PROM TO BE PROGRAMED o ROM 3 2 Ram MCE420 ROM OUTPUT PORTS OUTPUT PORTS SYSTEM INTERFACE AND CONTROL MODULE 5 f 4 NOTE 1 Allsignals defined with respect to negative logic at the dual in line I O socket 1 True n logic 1 GND False n logic 0 5V 2 1 TTL Load Drive 1 6mA 4V PORT LOGIC COMPATIBILITY ROM Input Port 0 7 True TTL In ROM Output Port 0 7 False TTL Out RAM Output Port 0 3 Bank 0 1 False TTL Out RAM Output Port 0 3 Bank 2 3 True TTL Out 126 5 OZ VEOW im 1 MP venena 1
182. ids nixies etc For TTL compatibility refer to Appendix A 3 Write the programs necessary to interpret inputs and gen erate the output levels necessary for proper operation of the peripherals Any interface design requires all three of these steps Each design will typically involve decisions concerning the inter action of the three areas For example techniques which reduce the number of output lines may result in more complicated pro grams The following sections describe typical interfaces for a number of common peripheral devices Keyboards Ihe MCS 4 can be programmed to scan and debounce a keyboard or can interface to a keyboard which presents precoded such as ASCII data The output lines from a keyboard with precoded data are read at one or more input ports An input port line or the test line of the 4004 CPU may be interrogated to deter mine if a key has been pressed 51 Scanning and debouncing a keyboard takes more elaborate pro gram The keyboard is usually arranged as an n x m n colums m rows matrix of key switches This type of keyboard is con nected as if it had n inputs and m outputs that is it requires n output lines from the MCS 4 and m input lines Under program control each output is activated in turn The input ports con nected to the keyboard are read and tested to see if a key has been pressed This testing may utilize the instruction After reading into the ACC 4 bits correspondin
183. ignored and search continues for operand 133 Register Designators Instructions which operate on register pairs must be coded with the even numbered register number or an equivalent expression in the operand field Thus SRC 2 refers to registers 2 and 3 not pair 2 in the sense of registers 4 and 5 If it is desired to code register pair numbers the same instruction may be coded SRC 1P Any register pair or in fact any even numbered register may be so defined by a single digit followed by a letter or other non digit non separator It is essential that the register operand field evaluate to an even number for those instructions which operate on register pairs since if the operand evaluates to an odd number the instruction op code will be altered with no indication of error The following are some examples of valid register pair operands 5P 3 PO11 assuming PO11 has been equated to an even number 513 7 truncated to 10 Conditional Jumps The first operand field in the JCN instruction is evaluated in a strictly numeric fashion just as all other operand fields Thus to effect a jump on the condition of zero carry the numeric value of the first operand field of the JCN must be 10 If it is desired to use mnemonic condition names such as CZ or AN etc these names must be equated to their numeric equivalents CZ 10 12 JCN CZ Label To avoid using up valuable name table space on condition names the extended mnemo
184. ily modified to handle 12 bit binary or 2 or 3 digit decimal conversions Execution of the sequence of instructions takes less than one millisecond and as can be seen from the listing occupies some 29 words of read only memory A multiplexer for multiple analog inputs can be added quite easily by providing a separate comparator for each analog input and performing digital multiplexing at the input to the test terminal of the 4004 central processor An alternate use of the structure shown in the first figure permits determining which if any of the several signals is above or below some predetermined analog threshold value The analog threshold value is deposited at the output ports driving the DAC and the outputs of the comparators are then read into the MCS 4 system at an input port or at the test terminal of the CPU ANALOG ANALOG INPUT INPUT 1 Block Diagram of A D Converter using DAC and MCS 4 SET UP FOR SELECTION OF ROM OUTPUT PORT USING RI AS A LOOP COUNTER VALUES IN BINAR 0000 00032 FIM PO 000011118 00015 CLEAR REGISTERS 84 R5 THESE TWO REGISTERS ARE DESIGNATED PAIR 2 OR P2 BY THE FIM INSTRUCTION R4 AND R5 WILL BE USED TO RECEIVE THE RESULT OF THE CONVERSION 0002 00036 FIM P20 00000 ISTART OF MAIN LOOP 0004 00033 ADLP SRCPO SELECT PORT USING CONTENTS OF RO RI 0005 00240 CLB CLEAR ACCUMULATOR AND CARRY FLIP FLOP 0006 00216 LDM 8 LOAD ACCUMULATOR WITH 1000 LDM 8 SETS THE HIGH ORDER BIT OF
185. inal strip See Figures 4 and 6 The receiver current level must be changed from 60mA to 20mA This is accomplished by moving a single wire See Figures 4 and 6 A relay circuit must be introduced into the paper tape reader drive circuit The recommended circuit consists of a relay a resistor a capacitor and suitable mounting fixture An alternate circuit utilizes a thyractor for suppression of inductive spikes This change requires the assembly of a small vector board with the relay circuit on it It may be mounted in the teletype by using two tapped holes in the mounting plate shown in Figure 1 The relay circuit may then be added without alteration of the existing circuit See Figures 2 3 and 6 That is wire to be connected to the brown wire in Figure 2 may be spliced into the brown wire near its connector plug The line and local wires must then be connected to the mode switch as shown Existing reader control circuitry within the teletype need not be altered External Connections 1 A two wire receive loop must be created This is accomplished by the connection of two wires between the teletype and the SIM board in accordance with Figure 6 2 A two wire send loop similar to the receive loop must be created See Figure 6 3 A two wire tape reader loop connecting the reader control relay to the SIM board must be created See Figure 6 P MOUNTING POSITION FOR CIRCUIT CAR
186. indirect Send contents of register pair RRR out as an address f at and A2 time in the Instruction Cycle JUN x s Fs Jump unconditional to ROM address A2 A4 JMS 0 10 1 Jump to subroutine ROM address 2 1 save old address Up 1 level 2 2 2 2 A4 A4 in stack RRRR Increment contents of register RRRR 3 0E 4 RRRR increment contents of register RRRR Go to ROM address 2 A4 PA within the same ROM that contains this 152 instruction if result 0 2 2 2 2 4 otherwise skip go to the next instruction sequence RRRR Add contents of register RRRR to accumulator with carry R RRR Subtract contents of register RRRR to accumulator with borrow R RRR Load contents of register RRRR to accumulator L R RRR Exchange contents of index register RRRR and accumulator DDDD Branch back down 1 level in stack and load data DDDD to accumulator D DD D Load data DODD to accumulator 000 1 Jump if test zero 5 A4A4 100 1 Jump if test not zero 5 A4A4A4A4 100 1 Jump if test one 5 1 1 BBL LDM gt Do gt gt Pu N JTN gt Po gt Po gt Po N JCZ 000 1 001 0 Jump if carry link zero 5 2 A4 Ay A1 Ay 0 00 1 1010 J if JNC ump if no carry 5 A2A2A2A2 A4 A4A4A4 0 00 1 0010 J if i JCO ump if on carry link one 5 A2
187. ing specifications are identical with the 4001 and 4004 Test Conditions Limit 380 WEN Address to Output Delay at A1 A2 X4 4008 Chip Select Output Delay atag 408 wo t Baten WiteTime I O Output Delay 4009 IN Strobe Delay 4009 OUT Strobe Delay 4009 IN Timing Diagram X t vu x 2 s masr SYNC 4004 TL HEEL Amm as Ay jon C3 4008 LX SRC d HIGH 4 BITS except WPM FROM ROM OR RAM XA rrocram instruction DATA BUS 4 4009 ED E cca L L C F L 4008 IN STROBE 14009 WRA G tsi 517 INSTR 0 OUT STROBE 4009 d N INPUT MUST BE VALID 4 DURING SHADE TIME tsz 57 7 INPUT 4009 DON T CARE 22 DON T CARE gt PROGRAM MEMORY ACCESS TIME CHIP SELECT TO DATA OUT MUST BE LESS THAN 90015 2 x rs Capacitance f 1MHz MN Vss TA 25 C Input Capacitance 4008 4009 APPLICATION OF THE 4008 4009 IN MCS 4 SYSTEM The standard memory and 1 interface set 4008 4009 provides the complete control functions performed by the 4001 in MCS 4 systems The 400
188. input the bit is turned off and the next bit in turn tested However if turning on a bit leaves the output of the digital to analog converter still smaller than the analog input signal then that bit will be left turned on The coding for the program consists of testing each of the lines of one port in turn using in line coding then repeating the sequence for the next set of port lines by looping back Setting a bit is accomplished by loading the accumulator with a load immediate instruction LDM and then writing the contents of the accumulator to the output port The output port is selected at the beginning of the program by the combination of fetch immediate FIM and send register control SRC instructions Register 4 R4 is used to contain the current estimate of the value for the 4 bits being tested A bit under test is retained or cleared by updating or not updating the contents of register 4 At the end of the basic 4 line test sequence of instructions the contents of register 4 are saved in an alternate location by a series of exchange XCH instructions and the instruction increment and skip on zero ISZ is used to perform the function of counting the number of passes through the loop and jump ing back to the loop start The loop selects the next port in turn by the increment INC instruction which modified registers RO so that when the next SRC instruction is executed it will select the next port in sequence This basic program can be eas
189. instruction was fetched by the CPU Pin CL on 4001 is used to asynchronously clear the output flip flops associated with the 1 lines Cour 20pF Outputs with loading conditions specified on A C Characteristics table 91 DATA BUS LINES Dg D4 Dz D3 4002 OUTPUT LINES 4001 1 0 OUTPUT LINES CM LINES 4001 1 0 INPUT LINES fis a tw H DATA IN 5V 5 THC 5V e 5V 4001 CLEAR LINE 4001 1 0 OUTPUT LINES 1v 105 4003 A e Characteristics 0 C 70 C Vy 15 5 GND SYMBOL TEST UNIT CONDITIONS e CP TO DATA OUT DELAY ENABLE TO DATA OUT DELAY CP TO SERIAL OUT DELAY 4 NOTES Uy be any time greater than 6 2 Data can occur prior to CP 4003 Timing Diagram WE 1V 5V wH DATA IN 5 1V r DATA OUT 5V Qj tal 2 112 ENABLE E SERIAL OUT Capacitance f 1 MHz OV 25 C Unmeasured Pins Grounded LIMIT pF LIMIT pF PRODUCT SYMBOL TEST PRODUCT SYMBOL TEST 4001 INPUT 1 5 4002 4 CAPACITANCE 4001 2 ES CLOCK INPUT CAPACITANCE 4004 2 CLOCK INPUT 20 CAPACITANCE NOTE 1 Refers to all input pins except data bus I O 4 and b x Typical Load Characteristics SET TIME VS OUTPUT CAPACITANCE
190. ire personality of the machine is determined by the instructions in ROM Very significant modifications of machine characteristics can be made by changing or adding ROM s without making any changes in wiring or circuit boards Thus the set offers tremendous flexibility of design and allows the user to have many of the desirable features of a custom MOS LSI design small package set of components which is uniquely his own for each user s program routines are his proprietary property and yet have none of the disadvantages of long development cycle high development costs etc The short design cycle and flexibility asso ciated with ROM programming allows much more rapid response to market demands than is possible with custom LSI and thus provide insurance against obsolescence B Applications for the MCS 4 Micro Computer Set Heart of the MCS 4 micro computer set is the 4004 CPU This device has a powerful and versatile instruction set which allows the system to perform a wide variety of arithmetic control and decision functions The microprograms stored in the ROM devices give the designer the power of designing custom computers with standard components You can use the MCS 4 almost anywhere Here are a few examples Control Functions Because of low initial cost and flexibility of programming the MCS 4 can be used in place of random logic in systems such as those in process control numeric controls elevator contr
191. is loaded a simulated RESET may be effected by the Z directive If starting at other than location zero or with registers pre loaded with data the appropriate directives may be used to set these up A breakpoint may be set if desired and RAM may be loaded up with data if desired If a subroutine or a part of a subroutine is being tested the stack may be loaded with a 144 return address using the L directive That may then be pushed down with the S directive so that the starting address be loaded into the first subroutine level or the process may be repeated up to three times If it is desired to force an inter rupt at the first occurrence of a JMS instruction the stack pointer may be set to 3 initially so that the first JMS instruction causes a stack overflow If it is desired to achieve more than one breakpoint illegal instructions may be assembled or in serted into the program at the desired points When the simulation attempts execution of one of these locations an inter rupt occurs and the instruction may be replaced or the program counter incremented around it to proceed 4 Execute Program Simulation To start the execution simulation type a T for Trace mode or an N for non Trace mode If at any time it is desired to stop execution simulation whether because of program errors to examine register contents or to make corrections the BREAK key may be depressed and the simulation will be interrupted at the comple
192. ister 14 Go LOOP to ROM address A2 called Loop if result 0 otherwise skip Explanation of Program a b c d e 2 Instruction 1 2 Instruction 3 and 4 Instruction 5 Instruction 6 Instruction 7 Instruction 8 9 10 and 11 Loads the number 8 1000 into index regis ter number 15 1111 Loads the number 6 0110 into index regis ter number 14 1110 Fetches the address of the desired RAM and stores it in an index register pair Sends the stored address to the RAM bank and selects the desired RAM Initializes the accumulator to 0000 Generates one clock pulse as follows Complement of highest order bit of accumulator and Send back to RAM output port Instruction 8 and 9 Initial state of RAM output port Instruction 12 Example 4 Highest order bit of accumulator is complemented again and sent back to the RAM output port In structions 10 and 11 The contents of Register 14 is incremented by 1 0001 The number 7 0111 is now stored in register 14 Since this result is not equal to zero program control jumps to the address specified in the 2nd word of this instruction this case the address stored in the 2nd word is the address of instruction 8 The program then exe cutes the next 4 instructions in sequence and generates a 2nd clock pulse This sequence is repeated a total of 10 times thus generating 10 clock pulses
193. ite data into the RAM program memory This new instruction is called WPM Write Program Memory 1110 0011 When an instruction is to be stored in RAM program memory it is written in two four bit segments The F L signal from the 4008 keeps track of which half is being written When the CPU executes a WPM instruction the chip select lines of the 4008 jammed with 1111 In the system design this should be designated as the RAM channel The W line on the 4008 is also activated by the WPM instruction The previously selected SRC address on line AO through A7 of the 4008 becomes the address of the RAM word being written By appropriately decoding the chip select lines the W line and F L the write strobes can be generated for the memory The line is initially high when power comes 11 then pulses low when every second WPM is executed A high on the F L line means that the first four bits are being written and a low means that the last four bits are being written The 4009 transfers the segment of the instruction to the 1 bus at X2 of the WPM instruction The SRC address sent to RAM is only 8 bits When more than one page of RAM 256 bytes is being written an output port must be used to supply additional address lines for higher order addresses Definition of Write Program Memory Instruction Mnemonic WPM Description The chip select lines of the 4008 are forced to 71111 OPR OPA 1110 0011 at X1 time and the content of the a
194. ives an I O and RAM group instruction In a typical system configuration the CM ROM line can control up to sixteen 4001 s and each line can control up to four 4002 s Each CM RAM line can be selected by the execution of the DCL Designate Command Line instruction The CM ROM line however is always enabled 1 1 If the number of ROM s in the system needs to be more than 16 external circuitry can be used to route CM ROM to two ROM banks The same comment applies to the CM RAM lines if more than 16 RAM s need to be used 13 For the execution of 1 0 and RAM group instruction the follow ing steps are necessary 1 The appropriate command line must be selected by DCL 2 The ROM chip and RAM chip register and character must be selected using the SRC Send Register Control instruction 3 An I O and RAM instruction must be fetched WRM RDM WRR e As w ma As m SYNC DCL SRC I O RAM FETCHED N FETCHED INSTRUCTION FETCHED CM RAM CODE IS TRANSFERRED TO THE COMMAND CONTROL REGISTER CM ROM LJ LJ L LJ LJ LJ CM RAMg LJ CM RANM IS DEACTIVATED CM RAM LJ _ VU J _ i CM RAM IS ACTIVATED THE 8 BIT ADDRESS THE MODIFIER OPA SENT BY THE CPU OF THE 1 0 AND RAM IS RECEIVED BY INSTRUCTION IS RECEIVED
195. keyboard considerable savings in program memory space and external hard ware can be achieved by combining the display scan and keyboard scan The same loop control and output port logic can be used for keyboard column selection and numeral digit position selec tion 53 D Teletype Interface The MCS 4 system is designed to interface with all types of terminal devices Interface with teletype is a typical example The interface consists of three simple transistor circuits which is shown in Fig 15 One transistor is used for receiving serial data from the teletype one for transmitting data back into the teletype and the third one for tape reader control It requires approximately 100 msec for the teletype to transmit or receive serially 8 data plus 3 control bits The first and the last bits are idling bits The second bit is a start bit The following eight bits are data Each bit stays on for about 9 09 msec The MCS 4 system is ideal for this timing control Following is a simple program which is written for this purpose This program not only controls the teletype timing but also stores the data temporarily in the index regis ter 2 and 3 in 4004 CPU chip and prints out the character The flow chart further explains the details of the program TTY TAPE TRANSMITTER READER CONTROL 5 SUPPRESS DATA FROM DATA FROM MCS 4 4001 MCS 4 4001 OR 4002 OR 4002 CHECK PRESENCE OF START BIT YES DELAY FOR 5 5 msec IN
196. l timing using SYNC and 91 9 1 The 4003 is static shift register and does not use these two clocks for its operation INSTRUCTION CYCLE Instruction Sent to CPU From ROM Execution of Instruction Data is Operated on in the CPU Or lt 1 35 us Data or Address is Sent to from the CPU SYNC Memory Subcycles It IOR Th The Selected 4001 Is Enabled The CPU Selected aU The CPU The CPU Is Enabled Device Is Enabled Or 4002 Are Is Enabled Controlling Enabled Data Bus wise The CPU Output Is Enabled Data or Address Data Lower 4 hit Middle 4 bit Higher 4 bit Instruction to CPU OPA Out to BAN s and Address to Bus Address to Address to Address ta RON s 11101 RAM s If ROMS ROM s ROM s Chip OPAto CPU Used Or SRC Sher Select Code and ROM s and RAM s Data to CPU If 10 If FOR IO instructions control the flow of information between accumulator in CPU I O lines in ROM s and RAM s and RAM storage stands for IO Read In this case the CPU will receive data from RAM storage locations or I O input lines of 4001 s The SRC instruction designates the chip number and address for a following instruction Figure 2 MCS 4 Basic Instruction Cycle Figure 2 shows how a basic instruction cycle is subdivided and what the activity is on the data bus during each clock period Each data bus output buff
197. lowing SOURCE NAME FILE The user should then type the name of the file containing his symbolic code followed by a carriage return As all valid names are of the form name DAT only the portion left of the period is typed The assembler will then request whether or not the user desires a listing of his program as it is assembled by typing the statement LIST Y N If you wish to have a listing generated type Y If the user desires to have a listing gener ated the assembler program will then request which output device the disk teletype or line printer the output is to be generated on The user should then type the three letter code corresponding to the desired output device DSK TTY LPT followed by a carriage return If the disk has been chosen as the output device the program will then request a name for the output file The system will also request which number system is to be used for the address and data portion of the output assembly Binary octal or decimal may be chosen by typing B O or D respectively Note that this option has no affect on the number system options within the assembly code Error Messages If in the course of an assembly the error diagnostic routines discover errors within the user s source program error messages will be typed followed by the erroneous line of code The error message will include the line number on which the error occurred and the address where the error occurred In some cases
198. ly Figure 3 shows an example of the TTY output for a very small sample program Only the first 36 words of 1601 tape are shown 159 SOURCE FILE NAME TST4 LIST Y N OUTPUT DSK TTY LPT TTY NUMBER SYSTEM B O D B ASSEMBLY OF TST4 DAT ON 17 MAY 72 AT 13 17 D 16 000000010000 000000010001 000000010011 000000010100 000000010101 000000010111 000000011001 000000011011 000000011100 000000011101 000000011110 SYMBOL TABLE NUMBER SYSTEM B O D D 2 000020 11110000 00101010 01011001 00101011 11101010 00011001 00010100 01010000 00011011 01000000 00010000 11011000 10001011 10110101 11000111 Y N Y 1601 OUTPUT Y N Y 000016 CLB FIM 5 89 SRC 5 RDR JCN T1 LAB2 LAB2 JMS JUN LABA TR3 LDM 8 ADD 11 XCH 5 BBL 7 TR3 000027 OUTPUT TO PTP TTY DSK TTY PAGE NO T OR 0 12 l6 20 28 32 BNNNNNNNNF BNNNNNNNNF BNNNNNNNNF BNNNNNNNNF BPPPPNNNNF BPPPNPNPNF BNNNPPNPPF BPNNNPNPPF BNNNNNNNNF BNNNNNNNNF BNNNNNNNNF BNNNNNNNNF BNNNNNNNNF BNNPNPNPNF BNNNPPNNPF BNPNNNNNNF BPNPPNPNPF BNNNNNNNNF BNNNNNNNNF BNNNNNNNNF BNNNNNNNNF BNNNNNNNNF BNPNPPNNPF BNNNPNPNNF BNNNPNNNNF BPPNNNPPPF BNNNNNNNNF BNNNNNNNNF BNNNNNNNNF BNNNNNNNNF BNNNNNNNNF BNNPNPNPPF BNPNPNNNNF BPPNPPNNNF BNNNNNNNNF BNNNNNNNNF Figure 3 160 Operation of SIM MCS 4 Simulator
199. ment The division of a statement by fields is exemplified in Figure 5 1 The following sections describe the various elements in detail Statements accordingly may assume several configurations Names Eight entries in the name table are accomodated by each 4092 RAM chip Maximums of 31 and 127 names are provided for the SIM4 01 and SIM4 02 boards respectively name consists of or more characters the first of which is a letter The rest of the characters may be letters digits or any of the following special characters lt gt 0 nmn 7 1 4 No imbedded separators are allowed To assure consistent operation distinct names should be unique through the first three characters although in some cases this may not be essential the sum of the binary representations of all characters after the third modulo 4 is used to distinguish names which are identical in the first three characters The following are some examples of valid names CLB CZ POLO A XYZ XYZW Note that the first three are valid names and have no pre assigned values The following are examples of invalid names 35A does not begin with a letter C D contains an imbedded separator Labels The label field of the line of source text begins immediately after the linefeed or STX and ends with the first separator If the label field is null i e no label in the line the first separator must be a spac
200. ms Group worked very closely with Action in both the design and debugging phases of the project BUSINESS MACHINES This general purpose data processing machine for small businesses is built by Omni Electron ics using an Intel micro computer as the heart of the system Suitably programmed this ma chine will tabulate accounts type invoices write checks and even produce personalized form letters Omni says they saved about 3 000 by using an Intel micro computer in place of a mini More over the micro computer enabled them to re duce the whole system to typewriter size They say the micro computer has even more speed than they need and offers the extraordi nary reliability they require in this application In addition to the Intel integrated CPU which does all central processing the machine uses Intel s electrically programmed PROMs for bootstrap programming and Intel s 2102 N channel 1024 bit MOS RAMs as the central memory a memory which stores up to 16K 8 bit bytes Peripheral memory is supplied by one to eight Omni tape decks which store 15 000 000 bits per cartridge 171 An Intel micro computer does all the thinking for this automatic bottle loading machine The micro computer built by Comstar Corporation of Edina Minnesota for Conveyor Specialities tells the machine how to load bottles of different sizes and when to perform each step in the loading process The little
201. n memory character Write the contents of the accumulator into the previously selected RAM output port Output Lines Write the contents of the accumulator into the previously selected ROM output port 1 Lines Write the contents of the accumulator into the previously selected half byte of read write program memory for use with 4008 4009 only Write the contents of the accumulator into the previously selected RAM status character O Write the contents of the accumulator into the previously selected RAM status character 1 0110 Write the contents of the accumulator into the previously selected RAM status character 2 Read the previously selected RAM main memory character into the accumulator Read the contents of the previously selected ROM input port into the accumulator 1 O Lines Add the previously selected RAM main memory character to Read the previously selected RAM status character 0 into accumulator Write the contents of the accumulator into the previously selected 0111 RAM status character 3 Subtract the previously selected RAM main memory character from Read the previously selected RAM status character 1 into accumulator Read the previously selected RAM status character 2 into accumulator Read the previously selected RAM status character 3 into accumulator ACCUMULATOR GROUP INSTRUCTIONS CLB qp 363 0000 Clear bo
202. n numbers for each 1 pin next page Examples of some of the possibl e 1 options are shown below EXAMPLES DESIRED OPTION CONNECTIONS REQUIRED 1 Non inverting output 1 and 3 are connected Inverting output 1 and 4 are connected Non inverting input no input resistor only 5 is connected Inverting input input resistor to Vss 2 6 7 and 9 are connected Non inverting input input resistor to 2 7 8 10 are connected If inputs and outputs mixed on the same port the pins used as the outputs must have the internal resistor connected to either Vpp or Vss 8 and 9 or 8 and 10 must be connected This is necessary for testing purposes For example if there are 1 in verting inputs with no input resistor and 2 non inverting outputs the connection would be made as follows Inputs 2 and 6 are connected Outputs 1 3 8 and 9 are connected or 1 3 8 and 10 are connected If the pins on a port are all inputs or all outputs the internal resistors do not have be connected 4001 CUSTOM ROM PATTERN Programming information should be sent in the form of computer puriched cards or punched paper tape In either case a print out of the truth table must accompany the order Refer to Intel s Data Catalog for complete pattern specifications Alternatively the accompanying truth table may be used Based on thue par ticular customer pattern the characters sh
203. nd colon printed by the assembler The line itself is read by the assembler and echoed back to the printer The listing thereby acts as a rough check on the serial link between the and SIM4 hardware The procedure is as follows 1 Assemble the appropriate hardware consting of the following a SIM4 01 or SIMA 02 board with a minimum of 3 RAMs Intel 4002 and the 4 assembler ROMs A0740 A0741 A0742 and A0743 b An ASR 33 with reader punch and ASCII keyboard teletype wired with a reader on off control relay and serial data link described in the MCS 4 Users Manual c SIMA Power Supplies Ref MCS 4 Users Manual d Customer supplied interconnect wiring Ref MCS 4 Users Manual Connect the hardware as shown in block diagram of figure 1 1 Place the TT Y punch off mode Place the TT Y reader in a free or off condition and position the tape on the leader Reset the SIM4 board customer supplied reset switch is assumed Start the TTY reader O an error occurs flagged by a bell and a special character stop the reader and take corrective action with the keyboard if possible Tape position must be carefully controlled during editing to avoid further erroneous input 8 The tape will be read until the dollar sign is reached At this point pass 1 of the aee is complete and the assembler is awaiting the second entry of the tape for pass 2 9 Turn the punch 10 Place t
204. ng out on the teletype the port number and then typing or accepting the data 10 No interrupt for subroutine stack overflow or underflow will occur when this bit is on 1000 Unconditional jumps and subroutine jumps to ROM page 0 chip 0 are executed directly instread of interpretively permitting direct byte 1 during checkout 143 ERROR MESSAGES Most of the errors which can be detected by the simulation program are identified by a single character typeout followed by ringing the bell once Six different types of errors are identified this way CODE SIGNIFICANCE This is not a valid directive Any printed graphic normally generated by the ASR33 which is not a valid directive evokes this response A question mark bell combination also calls attention to a simulated input request Break condition recognized This occurs normally either when the location counter reaches the value in the break register in execution simulation or when the BREAK key is depressed in simulation or ROM or RAM dumping gt Location counter out of range This error occurs in simulation or ROM punching if an attempt is made to access an address out of the range specified in the most recent directive Invalid op code This error occurs and is recognized during execution simulation after the instruction byte is typed out but before the location counter is incremented so that if it occurs under the control of the N directive the T directive may be ente
205. nics may be used for the conventional conditional jumps The following three instructions will assemble to the same object code provided CZ has been equated to 10 JCN CZ LABEL JCN 10 LABEL JCZ LABEL Data Constants 3 It is desirable to define numeric or address constants to be assembled into the ROM image independent of any instructions such as might be accessed by a FIN instruction This is possible by using a null mnemonic field The assembler will then expect one operand field the first term of which must be a positive number In all other respects the operand field is evaluated the same as any other operand field and it is assembled into one byte of object code truncating to eight bits if necessary with no error indication The following are some examples of valid data constants 0 4 4095 truncated to 255 00 equal to the address The following are some examples of invalid constant data fields ABC does not begin with a number 18 number is not positive 134 ERROR FLAGS Five errors are recognized by the assembler and each one is indicated by a single character typeout followed by a bell Some of the errors are detected in pass 1 and some of them are not detected until pass 2 The typeout for errors detected in pass 2 occurs between the colon typed with the location address and the B which begins the object code for that instruction Corrective action is indicated where it is possible FLA
206. ns ignat in Des ith P h W icrograp 4004 Photom l INTRODUCTION THE ALTERNATIVE TO RANDOM LOGIC SYSTEMS A General Discussion Since its inception digital computer applications have evolved from calculation through data processing and into control The develop ment of the minicomputer has vastly increased the scope of computer usage In particular the use of minicomputers in dedicated appli cations has had a profound effect on systems design Many engineers have found having a minicomputer at the heart of a system offers significant advantages Minicomputer systems are more flexible can be easily personalized for a particular customer s requirements and can be more easily changed or updated than fixed logic design systems For most designers the programming of a mini computer is a much easier and more straightforward procedure than designing a controller with random logic Unfortunately the size and cost of even the smallest minicomputer has limited its use to relatively large and costly systems This has resulted in many smaller systems being implemented with complicated random logic INTEL NOW OFFERS ANOTHER ALTERNATIVE THE MCS 4 MICRO COMPUTER SET This new concept in LSI technology makes the power of a general pur pose computer available to almost every logic designer and represents a strong attack on the dependency of systems manufacturers on compli cated random logic systems This component comp
207. nstruction cycle DC Power Requirement Voltage Vcc Vss 5V 5 TTL GND OV Vpp 10V 5 Current No load operation lec 1 8 Ibp 0 95 amp Worst case loading 32 TTL inputs and outputs Icc 2 75 amps 1 85 amp Connector Wire Wrap type Amphenol 86 pin connector P N 261 10043 2 SIM4 02 Prototyping Board MCS 4 STANDARD MEMORY AND INTERFACE SET 4008 4009 Both prototype systems the SIM4 01 and SIM4 02 are designed to permit the use of 1702A PROMs instead of metal masked 4001 ROMs The TTL used in the prototype systems to simulate the control logic of the 4001 is now embodied in two special interface devices These new devices the 4008 and 4009 provide direct interface to standard program memory either ROM RAM and to TTL 1 0 ports The 4008 is used as the address latching unit accepting twelve bits of address in each of three time periods A1 A2 The address is available to the program memory during M1 and M2 when the CPU accepts instructions and data The program memory may contain up to sixteen 256 byte pages The 4008 also stores the O port selection code so the appropriate input or output port can be selected during the execu tion times X2 and X3 Demultiplexing of the eight bit instruction word from program memory and trans mission to the data bus is carried out by the 4009 at M1 and M2 time By way of a four bit I O bus which can communicate with up to sixteen input and
208. ntrol of the tape reader during these operations but when editing directly from the paper tape it is advisable to manually advance the reader This may be accomplished by using the reader s manual start stop control switch Do not attempt to advance the tape directly Some comments regarding the format of the listing are present below _ 1 Each line must be preceded by a carriage return and a linefeed 2 Lines which are entirely comment must begin with any separator other than a space 3 All unlabeled lines must begin with a space 4 All condition mnemonics must be defined by decimal constants For example the 20th line of the listing contains a CZ which is later defined as a 10 on line 35 5 The pseudo operator is used to adjust the assembly address Line 13 consists of a space equal sign and the number 104 The assembler will interpret this as a command to define the next line as line 104 The subroutine will thereby be located at address 104 6 The pseudo operator is also used the last two lines of the listing to define constants If the equal sign is preceeded by a label the assembler will assign the subsequent value to the label 7 The dollar sign is an assembly terminator Pass 1 of the assembly procedure may now be completed The corrected paper tape will be read line by line by the assembler During this operation a name table is generated and a listing figure B 2 Preceding each line will be an
209. o de Ijo gt 2 4001 Bom Is ied x bid esser Ds a 3 Di SIMULATOR on p 1 D 1 T ING 1702A o i HRS 02 gt 2 9 55 9 8 8 d 5 gi 0 Yuc cup CHIP h T vss M tano 5 I 2 lt m Leste Ds nan Ten T gt vop 4 9 CHIP 2 vss 3 CM EAM ves SZ 2 4 De LI 3 De 1 9 Di 9 Di vse 45 CM RAM 11 syne syne zt US RESET D 9 eg ui z 3 REGET 92 74 2 0 Rem Tf f Oo p syne 8 3 2 Rum 5 9 at Ds 2 5 s io bd 101 Oc M 2 y 15 0 H i ves 46 9 RAM vss 46 4 3 ER x 8 yi 5 5 De 1 0 essers Dy gt er roar 1 e 5 SIMULATOR Is voon 2 ad USING 1702A Ds Se 4 55 H gt o si 15 7 5 5134 g IN k TEST RESET POM 22 V a 0 N Vss CLOCK G NERATOR TEST amp RESET TY SIGNAL GENERATOR INTERFACE 5 5 5 5 At7 5 266 5 3 629 R88 2907 200 34 5 5 2404 TO 4002 RAM
210. o form a completely self contained system The CPU communicates with the other members of the set through a four line data bus and with the peripheral devices through the RAM ROM or SR I O ports The CPU chip con tains 5 command control lines four of which are used to control the RAM chips each line can control up to 4 RAM chips for a total system capacity of 16 RAM s and one which is used to control a bank of up to 16 ROM s GND SYNC 2000203 CM RAM3 SERIAL Qo Qg Figure 1 MCS 4 System Interconnection B Basic System Operation The MCS 4 uses a 10 8 instruction cycle The CPU 4004 generates a synchronizing signal SYNC indicating the start of an instruction cycle and sends it to the ROM s 4001 and RAM s 4002 Basic instruction execution requires 8 or 16 cycles of 750 kHz clock In a typical sequence the CPU sends 12 bits of address in three 4 bit e _ the data bus to the ROM s in the first three cycles A This address selects 1 out of 16 chips and 1 out of 250 Du in that chip The selected chip sends back 8 bits v instruction OPR OPA to the CPU in the next two cycles M This instruction is sent over the 4 line data bus in two 4 2 instruction is then interpreted executed in the final three cycles X xj See Figure 2 When an I O instruction is received from the ROM data is transferred to or from the CPU accumulator on the four ROM I
211. o sense the start character data in is also sensed at the TEST input requires approximately 110 5 for the teletype to transmit or receive eight serial data bits plus three control bits The first and last bits are idling bits the second is the start bit and the following eight bits are data Each bit stays 9 09ms While waiting for data to be transmitted the 4004 is executing a JCN based on the TEST input When the start character is received the processor jumps to the TTY processing routine Under software control the processor can determine the duration of each bit and strobe the character at the proper time A listing of a teletype control program is shown in Section X Part D 59 CAUTION In one mode of operation these prototype systems do not truly simulate the activity of the 4001 After the system is reset and the program counter in the CPU is returned to address zero a two word instruction in the first two steps of the program may be improperly executed This is characteristic of the prototype boards not of the MCS 4 components This is the result of an asyn chronous reset pulse applied to the simulated 4001 ROM memory To insure proper operation of the prototype systems one of the following techniques must be implemented 1 Usa NOP in the first location of program memory ADDRESS 0 Any other single word instruction may also be used 2 Use the SYNC pulse to synchronize the reset signal to the system Then the pro
212. ode of operation the index register provides 16 directly addressable storage loca tions for intermediate computation and control the second mode the index register provides 8 pairs of addressable stor age locations for addressing RAM and ROM as well as for storing data fetched from ROM The index register address is provided by the internal bus and by the refresh counter and is multiplexed to the index register decoder The content of the index register is transferred to the internal bus through a multiplexer Writing into the register is accom plished by transferring the content of the internal bus into a temporary register and then to the index register 4 Adder The 4 bit adder is of the ripple through carry type One term of the addition comes from the ADB register which communicates with the internal bus on one side and can transfer data or data to the adder The other term of the addition comes from the accumulator and carry flip flop Both data and data can be transferred The output of the adder is transferred to the accumulator and carry FF The accumulator is provided with a shifter to implement rotate right and rotate left instructions The accumulator also communicates with the command control register special ROM s the condition flip flop and the internal bus The command control register holds a 3 bit code used for CM RAM line switching The special ROM s perform a code conver sion for DAA decimal adjust
213. ogic 1 negative logic 1 Sem word woe Number Number Number p 0 0 0 0 0 00 Number 128 chet 160 192 224 p 129 161 193 225 130 162 194 226 131 K 195 227 132 164 196 228 133 165 197 229 134 166 198 230 ds 167 199 231 196 168 200 232 p 137 169 201 233 138 170 202 234 139 171 203 235 140 172 204 236 141 173 205 237 142 174 206 238 143 175 207 239 1 44 176 208 240 145 177 209 241 146 178 210 242 147 179 211 243 148 180 212 244 149 181 213 245 150 182 214 246 151 183 215 247 152 184 216 248 153 185 217 249 154 186 218 250 155 219 251 156 ie 220 252 157 189 221 253 158 190 222 254 159 ppp debo 223 255 3065 Powers Avenue Santa Clara California 95051 e 408 246 7501 116 INTEL CORP APPENDIX D TELETYPE MODIFICATIONS FOR SIM4 01 SIM4 02 The SIM4 01 and SIM4 02 micro computer systems and associated software have been designed for interface to a model ASR 33 teletype wired in accordance with the following description The ASR 33 teletype must receive the following internal modifications and external connections Internal Modifications 1 The current source resistor value must be changed to 1450 ohms This is accomplished by moving a single wire See Figures 5 and 6 A full duplex hook up must be created internally This is accomplished by moving two wires on a term
214. ol for developing a system This board con tains one 4004 four 4002s and has provision for up to four 1702As The board should be ordered as SIM4 01 The PROMs should be ordered separately SIM4 02 Prototyping System This board is an expanded version of the SIM4 01 It contains one 4004 four 4002s and has provision for an additional twelve 4002s and sixteen 1702As The board should be ordered as SIM4 02 the type and number of PROMs and RAMs should 1 E 2 also be indicated MP7 03 PROM Programmer i This is the programmer board for 1602A 1702A The three 1702A control ROMs used with the SIM4 cards for an automatic programming system are specified by pattern numbers A0540 A0541 A0543 All items should be ordered individually 010 002 SIM4 Hardware Assembler 025 063 SIMA Hardware Simulator Four PROMs plug into either prototyping board enabling the micro computer prototype to help program itself To order this set of PROMs specify pattern numbers A0740 0741 A0742 and 0743 Nine PROMs plug into the 51 4 02 to aid in debugging of pro grams To order this set of PROMs specify pattern numbers A0750 through A0758 MCS 4 Assembler and Simulator Software Package This software package converts a list of instruction mnemonics into machine instructions and then simulates the operation of the MCS 4 program These programs are written in Fortran IV and are available via
215. ols highway and rail traffic controls chang ing ROM microprograms the whole system can easily be modified and updated E Computer Peripherals The system can be conveniently used in peripheral equipment to control displays keyboards printers readers plotters and to give intelligence to terminals Computing Systems The MCS 4 system is ideally suited for such devices as billing machines cash registers point of sale ter minals and accounting machines For example the adding of two 8 digit numbers can be done in 850 microseconds addition the 5 4 can be efficiently used to decentralize central com puter functions Other Applications The elements of the 5 4 have many applica tions within transportation automotive medical electronics and test systems where inexpensive dedicated computers can improve system performance C Features of the 5 4 4 bit parallel CPU with 45 instructions Decimal and binary arithmetic modes 10 8 ns instruction cycle Addition of Two 8 digit numbers in 850 psec Sixteen 4 bit general purpose registers Nesting of subroutines up to 3 levels Instruction Set includes conditional branching jump to subroutine and indirect fetching 2 phase dynamic operation Synchronous operation with memories Direct compatibility with 4001 4002 and 4003 No interface circuitry to memory and I O required Directly drives up to 4K by 8 ROM 16 4001 s 1280 by 4 RAM 16 4002 s 128 1 0 lines
216. one pseudo operator having two functions It serves to equate labels to values other than instruction addresses and it enables assembly to begin at some address other than 0 The pseudo op consists of one of the following characters in the mnemonic field of a source text line 4 72 14 77 10 98 9 lt gt This special character is followed by a single operand field which when evaluated becomes the value of the pseudo op If the label field of the pseudo op line is null the value of the operand field becomes the address of the next instruction to be assembled If the label field contains a name it is assigned the value of the operand It should be noted that the excessive use of this pseudo op to define the address of the next instruction other than at the beginning of individual ROM pages will lead to discontinuities in the object code which are not recognized by the 1701 programmer and the practice should be avoided Note also that when using the pseudo op to define the address of the next instruction to be assembled the operand field may not contain as yet undefined names since this will result in ambiguities which will not be flagged as erroneous The following are some examples of the proper use of the pseudo op CZ 10 POLL 6 0 This is unnecessary at the beginning of a program since the assembler always begins at zero anyway 512 Next Start at the beginning of ROM page 2
217. op controls the outputting of data is set at see Figure 2 if CM ROM and CSE chip select are 1 CSE is a single 4 input AND gate of the 4 data bus lines using Di or Di according to the chip number that the user wants to assign to the chip This is accomplished by metal mask option The SRC flip flop is set by CM ROM and CSE at see Figure 2 and presets the 1 0 logic for a following input or output operation TIMING generates all internal timing d for the ROM and I O control using SYNC 61 and 00 RESET 1 signal will clear all static flip flops and will inhibit data out The output flip flops associated with 1 0 pins can also be cleared using an external CL pin 1 RESET is used for the start up of the system RESET Vpp GND NEM MEMORY CLOCK Sos ace CLEAR INPUT k Jc 186 1 0 LINES SYNC INPUT PARTIAL DECODER SENSING amp Y DECODE MULTIPLEXING DATA BUS SENSING amp Y DECODE 4 LINES 4 i 7 V 4 CL RESET PRA LINES Figure 5 4001 ROM Block Diagram 19 R OM Options and Ordering the ROM chosen to be either an input or output line Each I O pin on each ROM can be uniquely 55 PIN 1 by metal option Also each input or output can either be inverted or direct When the pin is chosen as an input it may have an on chip resistor connected to either VDD or VSS Figure 6 shows the available options for each I O pin
218. or program storage An accompanying RAM memory figure shows the memory interconnect in detail if Intel s 2102 RAM is used four RAM memory sections can be reduced to one Example 4 Program Memory with Eight Pages of PROM and Eight Pages of RAM 112 APPENDIX MCS 4 CUSTOM ROM ORDER FORM 4001 Metal Masked ROM All custom ROM orders must be submitted on forms provided by Intel Programming information should be sent in the form of computer punched cards or punched paper tape In either case a print out of the truth table must accompany the order Refer to Intel s Data Catalog for complete pattern specifications Alternatively the accompanying truth table may be used Additional forms are available from Intel For Intel use only CUSTOMER S4 1 PPP STD ou 222 P O NUMBER APP 99 DATE DATE O INTEL STANDARD MARKING Intel Pattern The marking as shown at right must contain the Intel logo Number the product type P4001 the four digit Intel pattern num ber PPPP a date code XXXX and the two digit chip ge 2 Chip Number number DD An optional customer identification number may be substituted for the chip number 22 Optional Customer Number Maximum 6 characters spaces MASK OPTION SPECIFICATIONS A CHIP NUMBER Must be specified any number from 0 through 15 DD Customer Numb nr B OPTION Specify the connectio
219. or the 51 4 01 may be used without alterations the SIMA 02 IMPORTANT It should be noted that the 1701 and 1702 s are described in the data sheet with respect to positive logic high level p logic 1 On the other hand the MCS 4 system is defined in terms of negative logic low level n logic 1 a result when 1701 or 1702 ROM s are be ing programmed to simulate the 4001 characters should be defined as P high level n logic 0 or N low level n logic 1 For instance consider the instruction code for ADM one of the 45 instructions for the MCS 4 11101011 When preparing the program tape it should be typed BNNNPNPNNF This is the code that will be put into the 4001 when the final system is defined It will correctly simulate the 4001 operation when the 1701 or 1702 is used with the SIM4 01 or SIMA 02 system The schematics block diagrams for both prototyping systems shown on the following pages The 4004 and the 4002 s are used as they would be in a conventional system Additional circuitry is used to simulate the 4001 ROM s The two phase clocks are generated by the 9602 single shot multivibrator using discrete clock drivers Vpp 10V Vss 5V Prototype System Clock Drivers The 9316 counter together with the 3205 one of eight decoder serve to decode the cycle timing for the system thus simulating one of the functions implemented on the 4001 chips The output of th
220. or the program operation a scope should be used in the B delayed by A mode using the delay time multiplier the program execution can be easily seen The synchronization signals for the B and A traces are 13 of 4002 1 0 and SYNC pin 8 of the 4004 respectively The 4001 0009 has been coded with the internal chip select circuit always activated therefore any address at time will cause the 4001 to be selected This is different from the normal operation of the 4001 where only one code out of 16 at 3 time selects the 4001 The reason for doing so is that we can show the execution of JMS and JUN instructions to any chip number the A4 time code and still use only 1 ROM chip The I O pins of the 4001 0009 are all connected as inverting inputs with no resistors connected The two phase clocks 01 and 02 must be supplied externally according to the MCS 4 data sheet specs The program execution is 110 msec using a clock period of 1 3 usec Although the lines are not used in this configuration they are being pulsed If a scope is hooked up to these lines the waveforms may be observed Both 4002 1 s must be used in order to fully execute the program in the ROM Attached is the program flow with comments and the truth table 96 LLL SINGLE Pass U v ComTiwvoos Voo D 2 ez Sta EN3904 TIME IN MILLISECONDS 0 5 10 15 T 2271 T o 4002 0
221. ords 16 RAM s 1280 x 4 words and 128 I O lines without requiring any interface circuit With the addition of few gates up to 48 ROMS amp RAMS combined and 192 I O lines can be controlled by one CPU The I O function although different from the ROM and RAM functions is physically located in the ROM and RAM chips Each 4001 and 4002 has 4 I O lines for communication with I O devices es ROM The 4001 is a 2048 Bit metal mask programmable ROM providing custom microprogramming capability for the MCS 4 micro computer set Each chip is organized as 256 x 8 bit words which can be used for storing programs or data tables Each chip also has a 4 bit input output I O port which is used to route information to and from the data bus lines in and out of the system 4002 RAM The 4002 performs two functions As a RAM it stores 320 bits arranged as 4 registers of twenty 4 bit characters each a vehicle of communication with peripheral devices it is provided with 4 output lines and associated control logic to perform output operations 4003 SR 4003 is a 10 bit Serial in parallel out serial out shift register Its function is to increase the number of output lines to interface with I O devices such as keyboards displays printers teletypewriters switches readers A D converters etc 4004 CPU The 4004 is a central processor unit designed to work in conjunction with the other members of the MCS 4 micro computer set t
222. orrections as necessary In this way the development check out cycle can be typically reduced to one hour or less With mask programmable ROM s this cycle is usually four to six weeks Intel has developed two microcomputer prototyping kits SIM4 01 and SIM4 02 which use the electrically programmable and erasable ROM The maximum directly addressable system configuration is available with the SIM4 02 The 4004 CPU directly controls up to sixteen 1701 s or 1702 s and up to sixteen RAMs Eight ROM output ports and eight ROM input ports are provided These ports are associated with the first eight ROM the system Of course the user must be aware that individual lines of a ROM port can be used for input or output but not both The input output option is of course fixed at the time that the 4001 is mask programmed Sixteen RAM output ports are also provided In addition all data timing and memory controls signals are brought to the connector to permit future memory expansion The SIMA 01 is designed for small systems This board contains provision for up to four 1701 s or 1702 s and four 4002 s It provides up to four RAM output ports each port contains 4 bits four ROM output ports and four ROM input ports Both systems come complete with the 4004 CPU and four 4002 RAMs Addi tional RAMs and ROMs may be added as required Sockets are provided on the boards for all MCS 4 components and for all ROMs Note that all programs written f
223. ould be written as a P for a high level output n logic 0 negative logic 0 or N for a low level output n logic 1 negative logic 1 Note that BPPPP PPPPF 0000 0000 113 40011 Options O Do PIN 1 1 00 d PIN 16 IZO PIN 16 CONNECTIONS DESIRED LIST NUMBERS amp CIRCLE CONNECTIONS ON SCHEMATIC a For T2L compatibility on the I O lines the supply voltages should be Vpp 55 Veg 5V 5 DATA ROM BUS PATTERN OUTPUT BUFFER PIN 3 SET OUTPUT LOGIC F F 6 yoy 3 Pi Mig P gt Q O XE Z E gt E 8 Ri J IZO PIN 14 CONNECTIONS DESIRED LIST NUMBERS amp CIRCLE CONNECTIONS ON SCHEMATIC a For T2L compatibility on the 1 lines the supply voltages should Vop 10V 5 Vss 5V 5 b If non inverting input option is used V 6 5 Volts maximum not TTL b If non inverting input option is used 6 5 Volts maximum not TTL DATA OUTPUT BUFFER 1 0 PIN im CONNECTIONS DESIRED LIST NUMBERS amp CIRCLE CONNECTIONS ON SCHEMATIC a For T2L compatibility on the 1 lines the supply voltages should be Vpp 10 596 Veg 5V 5 b If non inverting input option is used V 6 5 Volts maximum not TTL DATA BUS OUTPUT BUFFER 1 0 PIN 13 CONNECTIONS D
224. output ports data is transmitted to and from the accumulator of the CPU via the 4009 0 These silicon gate p channel MOS devices packaged in 24 pin dual in line packages can replace more than twelve packages of standard TTL logic in systems similar to either the SIM4 01 or SIM4 02 Appendix B provides the complete specification for the 4008 and 4009 along with examples of various system con figurations FEATURES Directly Compatible With 4004 CPU Interface 1702 PROMs Directly to 4004 CPU Completely Eliminates TTL Interface Permits Program Storage in Alterable Memory Easily Combine PROMs 1702A Metal Mask ROMs 1301 and RAMs 1101 2102 for Program Storage Expanded 1 Port Capability Each Port May be Both Input and Output Up to 16 4 bit Input Ports and 16 4 bit Output Ports Number of 1 Ports is Independent of the Size of the Program Memory I O Ports and Control Lines TTL Compatible Execute MCS 4 Programs from any Mix of Standard Intel ROMs and RAMs New Instruction WPM Write Program Memory is Used for Loading Alterable Program Storage RAM OUTPUT OUTPUT 4004 4002 16 RAMS MAXIMUM 4002 RAM Bg CPU REGISTERS REGISTERS 16 INPUT PORTS AND 16 OUTPUT 4 BIT DATA BUS PORTS MAXIMUM 4008 740 o ADDRESS LATCH MAXIMUM 4k x 8 1 0 PORTS SELECT GATING Basic MCS 4 System Using 4008 and 4009 61 Oo 2
225. perations and the loading of the output flip flops VI 4003 10 BIT SERIAL IN PARALLEL OUT SERIAL OUT SHIFT REGISTER The 4003 is a 10 bit serial in parallel out serial out shift register with enable logic The 4003 is used to expand the number of ROM and RAM I O ports to communicate with peripheral devices such as keyboards printers displays readers teletypewriters etc Data is loaded serially and is available in parallel on 10 output lines which are accessed through enable logic When enabled E low the shift register contents is read out when not enabled E high the parallel out lines are at serial out line is not af fected by the enable logic Data is also available serially permitting an indefinite number of similar devices to be cascaded together to provide shift register length multiples of 10 The data shifting is controlled by the CP signal An internal power on clear circuit will clear the shift register 04 Vss between the application of the supply voltage and the first CP sig nal The 4003 output buffers are push pull ratio type useful for mul tiple key depression rejection when a 4003 is used in conjunction with a keyboard this mode if to three output lines are connected together the state of the output is high Logic 0 if at least one line is high The 4003 is a single phase static shift register however the clock pulse CP maximum width is limited to 10 msec
226. pproach of interfacing an analog to digital converter to the microprocessor a cost saving is achieved by having a microprocessor execute a program which enables a digital to analog converter and a comparator to perform the analog digital converter function The first figure shows how the conversion is achieved The MCS 4 uses a port for input output communication A four wire port is associated with each read only memory or read write memory chip Two of these output ports have been used to drive the inputs of a digital to analog converter DAC The DAC is wired to a comparator which allows the output of the DAC to be compared with the analog input signal The output of the comparator is in turn wired to the test input of the 4004 central processor This test input line is interrogated when the central processor executes a certain conditional jump instruction Whereas the normal instruction execution flow within the MCS 4 system is sequential through program memory when the con ditional jump is executed the processor jumps to a new location in memory starting a new instruction sequence The second figure lists the program for the analog to digital convertor in MCS 4 assembly language The program implements a successive approximation conversion technique Starting with the highest order bit each bit in turn is turned on and the output of the comparator tested If turning on the bit results in a signal from the DAC that is larger than the analog
227. programmed simultaneously by setting the desired bit information patterns on the data input terminals TAPE FORMAT The tape reader used with a model 33 ASR teletype accepts 1 wide paper tape using 7 or 8 bit ASCII code For a tape to correctly program a 1602 1702 it must follow exactly the format rules below Start 7 Stop Character Data Field MSB Pin 11 LSB Pin 4 Leader BPPPNNNNNFBNNNNNNPPF BNPNPPPNNF Trailer Rubout for at Rubout for at least 25 frames Em least 25 frames Word Field 0 Word Field 1 Word Field 255 The format requirements are as follows 1 There must be exactly 256 word fields in consecutive sequence starting with word field 0 all address lines low to program an entire ROM If a short tape is needed to program only a portion of the ROM the same format requirements apply 2 Each word field must consist of ten consecutive characters the first of which must be the start character B Following that start character there must be exactly eight data characters P s or N s and ending with the stop character F NO OTHER CHARACTERS ARE ALLOWED ANYWHERE IN A WORD FIELD If an error is made while preparing a tape and the stop character F has not been typed a typed will eliminate the previous characters entered This is a feature not available on Intel s 7600 programmer the format shown in the Intel Data Catalog must be used when preparing tapes for other programming systems An example o
228. put NAND gate together with a flip flop is provided to detect the condition for a WRITE ROM OUTPUT port four bit latch is provided for each output port to be implemented During the subsequent X cycle the data on the data bus is loaded into the selected port latches These latches then retain the data The flip flop controlling this operation should also be reset at X time The ROM outputs invert the output data and are TTL compatible RAM outputs are MOS compatible Refer to the schematics and pin configurations for both the SIM4 01 and SIM4 02 Discrete interface circuits are provided on the cards to communicate with a teletype Data can be entered through the simulated ROM input ports either from the keyboard or the paper tape reader of the teletype The receiving and transmitting of data are in serial form Other terminal devices such as typical commercial keyboards printers LED s CRTs cassettes can readily communicate with the system with proper single interface These systems may be reset to zero by using a RESET switch as indicated on the board pin connector list Debouncing for the switch is provided on the board The TEST signal may be transmitted directly to the TEST pin of the 4004 or through a debouncer and one shot multivibrator When the TEST signal comes from the one shot the program executed by the CPU should be looping through a JCN instruction waiting for TEST signal Teletype Interface The MCS 4 is desi
229. r Pennsylvania Inc 7300 Route 130 North 609 662 5061 Pennsauken 08110 NEW YORK Cramer Binghamton 3220 Watson Boulevard 607 754 6661 Endwell 13760 Cramer Rochester 3259 Winton Road South 716 275 0300 Rochester 14623 Cramer Syracuse 6716 Joy Road 315 437 6671 East Syracuse 13057 Hamilton Avnet Electronics 6400 Joy Road 315 437 2642 Syracuse 13211 Cramer Long Island 29 Oser Avenue 516 231 5600 Hauppauge L I 11787 Hamilton Avnet Electronics 70 State Street 516 333 5800 Westbury L I 11590 PENNSYLVANIA Sheridan Assoc Inc 4268 North Pike North Pike Pavilion 412 373 1070 Monroeville 15146 SOUTHEAST ALABANA Cramer EW Huntsville Inc 2310 Bob Wallace Avenue 205 539 5722 Huntsville 35805 FLORIDA Cramer EW Hollywood 4035 North 29th Avenue 305 923 8181 Hollywood 33020 Hamilton Avnet Electronics 4020 North 29th Avenue 305 925 5401 Hollywood 33020 Cramer EW Orlando 345 North Graham Ave 305 841 1550 Orlando 32814 GEORGIA Cramer EW Atlanta 3130 Marjan Drive 404 448 9050 Atianta 30340 Hamilton Avnet Electronics 6700 Interstate 85 Access Road 404 448 0800 Atlanta 30071 NORTH CAROLINA Cramer EW Raleigh 3901 Winton Road 919 876 2371 Raleigh 27604 Cramer EW Winston Salem 938 Burke Street 919 725 8711 Winston Salem 27102 PUERTO RICO Cramer Electronics de Puerto Rico Subdivision Industrial Bo Retiro San German 00753 CANADA ONTARIO Cramer Canada
230. r supplies TT Y Automatic PROM Duplicating Comparing with SIM4 02 MP7 03 A0544 PROM Program power supplies General Purpose Micro Processor With 1 and Display with SIM4 02 power supplies Test System for checkout of PROM Programs with SIM4 02 power supplies T he MCB4 20 includes the following Es 2 3 8 9 10 11 12 13 All interconnect circuitry necessary to implement the programming system described paragraph XIII of the 5 4 Users Manual Connectors for the SIM4 02 and MP7 03 boards Two zero insertion force 24 pin sockets for PROMs One socket for the PROM to be programmed one socket for a Duplicating REF PROM and appropriate connections to the MP7 03 connector Teletype receive conditioning circuit transmit source circuit punch and reader control interface circuits on the SIM4 02 and a TTY connect disconnect switch Access to these signals is provided by a 16 pin dip socket labeled TTY socket Flat cable is provided the to TT Y Two control switches for complementing programmer input or output data Eleven 16 pin DIP sockets provide easy access to SIM4 02 input output and miscellaneous control signals This includes 32 ROM inputs 8 ports x 4 bits 32 ROM outputs 8 ports x 4 bits and 64 RAM outputs 16 ports x 4 bits SIM4 02 ROM and RAM output port binary display using light emitting diodes This includes 32 bi
231. rammable and field erasable read only memories If the user wishes to generate such tapes at this time he types Y The program will then request what output device he wishes the tapes to be generated on The choices are the paper tape punch located at the computer center the user s teletypewriter or the disk If the disk is selected the program will request an output file name Following the request for an output file name 1 any the pro gram will type PAGE NO T OR C The user may then type the number of the page ROM chip for which he wishes to generate the programming tape Page 0 corresponds to addresses through 255 page 1 to addresses 256 through 511 etc so the user must type a l or 2 digit decimal number in the range g 15 This must be followed by a comma or a space followed in turn by the letter T or C indicating whether the page is to be output in true 1 or complemented 1 P form For example tapes for use with the SIM4 01 and SIM4 02 boards should be prepared in complemented form After each tape has been gen erated the program will request another page number In the case where output is to disk another file name will be requested prior to the page number If no more tapes are desired typing any character other than a valid page number will cause the program to exit Upon exiting the program will print the amount of central processor time and the amount of terminal time used for the assemb
232. rather than TTY not available on time shared versions Input to RAM word n n must be between g and 63 The terminal will respond by requesting 20 characters Exactly 20 must be typed in the same sequence as used for the E command above However no space is allowed between main characters and status characters The inputs allowed 0 9 A F and correspond to hexadecimal inputs of g through 15 while typed leaves the corresponding character position unchanged If 1 a shorter form of input and output will be used for ROM input port requests etc If n l the long form will be used Examine CPU registers Examine stack and stack pointers Operate trace mode for the next n instructions starting at the current program counter value Break points will terminate the but the instruction limit counter is disabled Execute n instructions then stop and print the status in formation for the last instruction Break points will terminate the sequence but the instruction limit counter is disabled Write into ROM word n n must fall between and 4095 The terminal will request a numeric value in decimal be tween and 255 which will be written into the selected ROM word Exit from the program All commands are followedby a typed carriage return In each case n represents a 1 5 digit decimal number For example to run trace mode for 50 instructions Starting at address 100 decimal th
233. red to examine the error by trying t execute it again Location counter stack overflow or underflow This error is unique in that the interruption occurs after the instruc tion has been executed in simulation T or an N directive will resume execution with the next instruction jumped or returned to Cancel This is the program response to Cancel Control X or ESCAPE typein during data input Except for I M T and N directives it cancels the entire directive If used in the or M directives only the current datum is canceled and the directive is terminated at that point Previous values if any have already been stored in memory If used while the simulation program is requesting input data from a simulated ROM port or the simulated CPU Test line it is equivalent to a break at the beginning of the instruction each case the simulation program returns to accept another directive OPERATING INSTRUCTIONS 1 Assemble Program First assemble the test program on the Hardware Assembler A0740 to A0743 mportant the Hardware Simulation Program will not accept ROM program tapes created by the FORTRAN assembler ASMA as these tapes have bit patterns and addresses together with no identifier for the addresses It is not necessary to assemble the program in one contiguous block of ROM locations since the directive in the simulation program is able to recognize the address fields by the Control A S
234. red with one pole to ground and the wiper wired to the appropriate socket connector in accordance with the MCB4 10 schematic A3 1 16 A3 13 The SIM4 01 is then inserted into the SIM4 01 connector and a bench supply connected to the 5V DC and 10V DC input jacks The actual test may now be performed The reset button is depressed clearing the system s memories and registers and the program executes The result appears at the LED display and may be verified for correctness The display lights of interest are identified on the system s printed circuit board as OUTPUT PORTS RAM 0 RAM 1 BITS 0 1 2 and 3 2 Programming System Consider the actual programming in the hardware sense of the 1702A PROM in the example above The system can perform this function with the addition of an MP7 03 board inserted into the PROGRAMMER BOARD connector An automatic programming system which allows data entry from a keyboard or papertape automatic verification listing of ROM contents and hands off programming is provided by the further addition of a SIM4 01 board with three pre programmed PROMs 40540 0541 A0543 and a modified teletype The switches added in the manual set up are deleted The teletype modification con sists of the addition of simple relay network described by MCS 4 Users Manual The procedure for programming a 1602A 1702A PROM then is as follows Insert MP7 03 and SIM4 01 boards SIM4 01 loaded with
235. ret any number not otherwise indicated as being in another number system as a binary number At any point in the program the current number system can be overridden by following the typed number with the letter B D 155 TABLE 2 Condition Codes for JCN Instruction LLL VN LDSLrIUuCCUlOn Condition Jump If Mnemonic Binary Equivalent no condition NC 0000 test equals zero TZ T 0001 test equals one TN 1 1001 carry equals one CN C1 0010 carry equals zero CZ Cf 1010 accumulator equals zero AZ AG 0100 accumulator non zero AZ 1100 When more than one mnemonic is shown any one of the forms 15 acceptable Li CLB DCL b JCN TZ c TAG JMS 1 1 Figure 1 Examples of labelled unlabelled lines a 11 is a label but the second line is unlabelled b The line is unlabelled but the implies that the jump occurs back to this instruction as long as the CPU test line is at a logic zero C TAG is a label and the Jump to subroutine will enter the routine at 11 1 ie the DCL instruction of Figure la 156 or in the position immediately following the last digit of the number This input will not alter the number system used for numbers not so labelled Numbers designating register pairs or registers of the form RO R15 Pggg P111 7 are not subject to this number system input convention If the assembler comes across a number which will not fit within
236. reviously selected by the last SRC instruction executed OPR OPA 03 D2 D1 Do D3 D2 D4 Do 0000 Write the contents of the accumulator into the previously selected RAM main memory character Write the contents of the accumulator into the previously selected RAM output port Output Lines Write the contents of the accumulator into the previously selected ROM output port 1 Lines Write the contents of the accumulator into the previously selected half byte of read write program memory for use with 4008 4009 only Write the contents of the accumulator into the previously selected RAM status character O Write the contents of the accumulator into the previously selected RAM status character 1 Write the contents of the accumulator into the previously selected RAM status character 2 Write the contents of the accumulator into the previously selected RAM status character 3 Subtract the previously selected RAM main memory character from accumulator with borrow Read the previously selected RAM main memory character into the accumulator Read the contents of the previously selected ROM input port into the accumulator 1 O Lines Add the previously selected RAM main memory character to accumulator with carry Read the previously selected RAM status character O into accumulator Read the previously selected RAM status character 1 into accumulator Read the previously selected RAM status character 2 into accumulator Read the pr
237. rnal bus during A and in three 4 bit slices see Figure 2 for basic instruction The address is incremented by a 4 bit carry look ahead circuit address incre menter after each 4 bit slice is sent out on the data bus The incremented address is transferred back to the address buffer and finally written back into the address register 16 C RAMo me 15 JCM RAM CONTROL JCM RAM OUTPUTS CM CUM OM OM 13 OUTPUT INTERNAL RESET F F 12 15 BUFFER CLOCK i mua CLOCK PHASE 2 2L 7 7 OUTPUT BUFFERS TIMING ADDRESS INCREMENTER AMPLI amp MULTIPLEXER COMMAND CONTROL REGISTER ADDRESS SPECIAL REGISTER ROMs DECODER PROGRAM DRIVER COUNTER amp STACK ACCUMULATOR MUX 4 x 12 BIT AND CARRY F F OPA OPR DYNAMIC DECODER DECODER RAM MUX amp SHIFTER REFRESH BUFFER INSTRUCTION DECODER SEEN REGISTER ADDER EFFECTIVE INSTRUCTION REGISTER ADDRESS COUNTER ADB BUFFER REG INDEX REGISTER 16 x 4 BIT DYNAMIC RAM DECODER DRIVER REFRESH COUNTER amp MUX INTERNAL DATA BUS Figure 3 4004 CPU Block Diagram 8 4 Index Register The index register is a dynamic RAM cell array of 16 x 4 bits and has two modes of operation Im one m
238. rogram attempts to jump or increment to outside the range of the simulated ROM an error interrupt occurs Another error interrupt occurs in the event of an illegal instruction op code during simulated execution The op codes which cause this interrupt are 11111110 11111111 11100011 and all instructions with OPR 0000 except for 00000000 NOP 141 breakpoint register is associated with the simulated execution mode of operation allowing the user to pre set location which will cause an interrupt before execution The BREAK key on the teletype may also be used to interrupt execution and some other types of output During simulated execution a count is kept of the number of simulated machine cycles i e sync pulses used by the test program to assist in checking out programs with critical timing problems 4 Qr s e In Pn m Mn i Dr DIRECTIVES Binary conversion This directive accepts a single decimal number and types out its equivalent in binary A maximum of 12 bits num bers to 4095 may be accomodated at once Decimal adder This directive accepts a string of decimal numbers separated by plus and minus signs and types out the algabraic sum modulo 4096 If the algebraic sum is negative 4095 is logically added to it to give a positive result This directive may be used to perform binary to decimal conversion thus Bnnnn RAM ROM chip assignment This directive must be entered before any other letter
239. rogram by the RDO WRO RD1 WR1 etc instructions respectively The directive is used to define and set aside some part of RAM for use by the simulation program as simulated ROM and other registers and parameters Whole RAM registers are taken by the O directive beginning with the register identified in the first parameter The status locations from exactly 12 registers are used by the simulator The number of main memory locations used is determined by the difference between the second and third parameters of the Q directive Where s and e represent the values in the second and third parameters of the O directive the number of registers used is determined by the formula 5 8 1 This value may be more or less than 12 the number of registers whose status locations are used with no ill effects RAM main memory locations reserved by the Q directive are used solely for program storage The instruction with an address equal to the second parameter of the instruction is loaded into digits and 1 of the register designated by the first parameter of the O directive subsequent instructions are loaded into the following digit pairs according to the addresses The RAM status locations reserved by the simulation program are allocated to the following functions Relative 3 REGISTER LOC N FUNCTIONS 0 0 Simulated Accumulator 0 1 3 Low ROM address limit 1 0 Option word 1 13 High ROM address limit 2 0 Execution paramete
240. rs 2 1 3 Breakpoint address 3 0 Simulated Carry 3 1 3 Simulation Cycle counter 4 0 Simulated Stack pointer 4 7 1 3 Simulated Stack 5 0 Simulated Command line selection 6 7 0 Simulated ROM or RAM chip selection 8 11 0 3 Simulated index registers EXAMPLES Figures 1 2 and 3 are annotated listings generated during actual simulation Figure 1 is a simulation of the AND program described in figures 4 and 5 Figures 2 and 3 represent the simulator s response to various directives entered via a TTY keyboard 148 ASTERISK IS SIMULATOR OUTPUT INITIALIZE vr READY INDICATION 5 MEMORY BLOCK 03 128 IS ASSIGNED noe oe 8 BPPPPPPPNF 2 BPPNPNPPNF 33 BNNNPNPNPF INPUT COMMAND 4 53 BPNNPNPPPF 6 BPPNPNPPNF 7 BNNNPNPNPF amp 1BNPNNPPPNF 9 BP4PNPPPPF BPNNPNPPPF 11 SPECIFIES ORIGIN 19 BNNNPPPPNF 13 BPNPPPPPPF BPPPPPPPPF 15 BPPPPPPPPF 16 104 1 4tBNNNNPPPPF 10SIBNPNAPPNPR 106 1071BNPNNPPPP SIMULATOR ASSIGNS ADDRESS 1081BNANNPNNPF 109 BNPNNPPPPF 110 BPPPNNPNPF BPNNNNPNPF IN ACCORDANCE WITH DATA 1121BNPNNPPPAF 11313 BNNNNPNNPF 1141 BNPNNPPPNF 115 BNPNNPPNPF id 1161BNNNNPNNPF 117 BNPNNPPAPF 1181BNANANPPPF 1191 BPPPNNNPPF DELIMITED BY CONTROL A BPNNPNPNNF 121 18NNPPPPPPF 122 BNPNNPPPNF 193 BNNNNPNNPF CHARACTERS HARDWARE 124 BNPNNPPPNF 125 BNNNNPPPNF 126 BPNPPPPPPF BPNNNPPNNF 128 128 128 ASSEMBLER
241. s Clear markers Check TCS instruction Check TCC CMC RAR instructions Read content of all memory locations Check SBM instruction Check ADM instruction This portion controls the cycle Status character 0 stores the cycle number At the end of the 2nd cycle if pin 13 of the 4002 1 O is connected to test of the program will stop To again RESET signal must be to the system single pass If pin 13 is not connected the 4004 start applied operation to TEST the program will be 1 continuous mode LD MK CK IDX CK FIN CK DCL SUBROUTINES Dat 101 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 SRC 5 LD 11 CLC XCH 11 BBL O SRC SRC SRC SRC SRC SRC SRC SRC BBL Qn FIN FIN FIN FIN FIN FIN FIN FIN BBL O O Q S i 1 DCL XCH RDR BBL 0 B NOP 1111 1111 0000 0000 NOP XV APPENDICES APPENDIX A Electrical Characteristics of the MCS 4 The following pages provide the electrical characteristics for the MCS 4 system For TTL compatibility a resistor should be added between the output and VpD 11 outputs are push pull MOS outputs 12KQ 5 6KQ 4001 4002 OUTPUT PORT OUT 4003 OUT OUTPUT Vss Vcc 5V Vss Figure 38 MCS 4 Output Config
242. s 15 a space is typed instead Unless a space is typed register 10 is incremented 40 4 7 10 15 This routine will print with zero suppression the four digit decimal number in registers 4 through 7 BCD 11 1 7 10 15 This routine converts the 12 bit binary number in registers 1 3 into decimal and prints the four digits with zero suppression 146 RAM USAGE The simulation program to facilitate full usage of the RAM has organized it into a nominal block of 64 registers each containing 16 main memory locations and four status locations Directives which reference RAM as such i e Q M and D always address it by a register number and sometimes by a character position within the register The following chart illustrates this addressing scheme REGISTER DIGIT selected by odd index in SRC instr selected by even index in SRC instr Status _____ 1 2 131 4 5 6 7 8 2 10 n 13 14 15 16 17 18 19 0 Bank O 1 RAMO Port 0 2 3 4 Bank 0 M RAM 1 6 7 Bank 1 RAMO Port 4 Bank 2 RAM 3 Port 11 Bank 4 RAMO 50 Port 12 51 60 Bank 4 61 RAM 3 Port 15 82 63 147 The bank number in the chart above is the value of the accumulator during DCL instruction needed to address that bank of RAMs The port number given corresponds to the number typed out during simulation of the WMP instruction Register positions 16 19 i e the status locations are normally addressed the p
243. s already been accepted or the line has been identified by the assembler as a comment line RUBOUT Delete This character is ignored by the assembler and may occur anywhere in the input text except in front of an SOH The preparation of tapes of source text is facilitated by the fact that erroneous characters accidentally punched into the tape may be effectively removed by backing the tape up in the perforator and repunching the frames with rubouts A dollar sign as the first character following the linefeed or STX signals the end of the source text to the assembler and conditions the punching of the leader or trailer in the object tape A plus or minus sign serves simultaneously as an operational sign in the computation of an operand value and as the terminal delimiter for the term immediately preceeding it The asterisk is recognized by the assembler in an operand field to have a value equal to the address of the first byte of the current instruction NUMBER SYSTEM All numeric values in the source code are recognized by the assembler as decimal and all numeric values generated by the assembler are in decimal Since the internal representation of the numeric values is 12 bit binary the largest value that may be accommodated is 4095 212 1 Decimal numbers in the source text must not exceed 4095 for correct operation of the assembler although there is no such restriction on the computation of values except that the val
244. s character i greater than 15 only status characters are filled The sequence ends with a carriage return following the terminal delimiter of the last number Dump RAM This directive types out in decimal the contents of each RAM location both main memory and status of n registers beginning with register r The typeout may be ended prematurely by depressing the BREAK key 142 Xn Accumulator This directive may be used to display and or alter the contents of the simulated accumulator space or comma follow ing the A will display in binary the contents of the simulated accumulator This or the A may be followed either by a new value to be entered or by a carriage return to end the directive Carry Link This directive may be used to display and or alter the contents of the simulated Carry Link bit The use of this direct ive is the same as for A Index This directive may be used to display and or alter the contents of any one or pair of the simulated index registers a space or comma follows the X all 16 index registers are displayed in decimal Otherwise if the decimal number n is followed by a space index register n may be displayed and or altered as in A If the number n is followed by a comma slash or period index pair number n may be displayed in decimal and or altered as a unit Index registers 2n and 2n 1 are handled together as a single 8 bit number Stack pointer This directive may be used to display
245. s the carry bit set by KEY or as well as the accumulator value and the character in registers 14 and 15 to determine if one of the following conditions obtains 1 The character is some printable graphic between and lt a If so the character is biased to six bit value centered in the byte The carry is turned on if it is a letter normal return is taken acc 0 2 The character is a control character between null and ETB control Y or a printable graphic between space and slash An indirect jump to the address in ROM page 1 contained in index registers 10 and 11 is taken 3 The character is a control between CAN Control X and US Shift Control 0 An unconditional jump to location 256 is taken 4 The character is one of those not generated by a KSR33 teletype or a rubout normal return is taken with the accumulator non zero T6R 205 10 15 This routine combines TTI and TXX such that normal return occurs only on characters 0 through lt lt Characters in group 4 above are ignored and the alternate exits are taken for control characters and delimiters Note that if the address to which the delimiter return is to be made is odd no echo occurs On normal return the character is right justified in registers 14 and 15 and the carry is set if the character is a letter or higher T6L 220 10 15 This routine is the same as T6R except that on normal return the carry is always zero and
246. se specified 1 SN7486 i DATA8 3 1 RESISTORS ARE RATED IN Qs W 10 46 i 2 3 csl A 2 TRANSISTORS ARE SE6021 or 2N3658 or 2N3722 R57 3 PIN NUMBERS ARE SPECIFIED FOR AMPHENOL WIRE WRAP CONNECTORS Figure 32 MP7 03 PROM Programmer 1K Board Schematic DATA DRIVER 94 95 XIV MCS 4 EVALUATION KIT USING THE 4001 0009 This kit provides both a convenient way of evaluating the MCS 4 parts and an educational vehicle to better understand the MCS 4 operation The 4001 009 stores a microprogram that exercises the 4004 and 4002 s and executes all of the 45 instructions in the MCS 4 instruction set Fig 33 shows the hardware that should be used circuit for single pass continuous can be omitted if only continuous operation is sought In this case Og RAM 0 should be connected directly to TEST The RESET signal can be provided by either a one shot circuit or by a pulse generator in the single pulse mode The width of the RESET signal must at least 32 x 8 clock periods 22 350 usec to fully clear the storage If the system is operated in the continuous mode RESET needs to be applied only at power on If the system works in the single pass mode when END of SEQUENCE Pin 04 is 1 the 4004 will hang on a loop where the address to Jump to on a jump on TEST 1 condition is the address of the same jump on condition To get out of the loop RESET must be applied To monit
247. sents the octal address of this byte The second column represents the octal byte value of the instruction word The third column is the address label field and can be blank The fourth column is the mneumonic field terminated by a space or a semicolon The fifth column is the OPA field for the lst byte terminated by a semi colon or space or slash or carriage return The sixth column is the second byte specification field for a 2 word instruction The last column is the comment field preceded by a slash SPECIAL NOTES e Each complete line followed by a carriage return is considered a symbolic record e All source data following slash will be considered comment data by the assembler ignored e Any operand followed by a less than sign lt will be truncated at three 3 bits and used as an octal numeral e The lt will only work with those instructions which manipulate register pairs in the 4004 e The semicolon s used to indicate the end of argument for the first byte of a two 2 byte instruction Arguments for the second byte must immediately follow the semicolon 16 Digit Decimal Addition Routine This program performs the addition of two 16 digit decimal numbers These numbers are stored RAM chip 0 register 0 and 3 The least significant digit of each of these numbers is located in the character 0 of each RAM register and the most significant digits are in character 1
248. sily learned by use of examples the pages that follow a number of sample program segments are described In general the examples are shown in order of increasing complexity These examples have been chosen to illustrate the use of the I O ports basic program loops multiple precision arithmetic and the use of subroutines EXAMPLE 1 Consider the case where it is desired to test the status of a single switch connected to the CPU 4004 chip on the test input pin 10 A jump on condition instruction JCN can be used to perform this test Suppose the JCN instruction JCN TEST 16 2 word instruction is stored at ROM memory locations 2 and 3 The instruction would look as follows OPR OPA C1C2C3CA Location 2 0001 0001 JCN Jump if test signal Logic 0 Location 3 0001 0000 Jump to ROM memory Location 16 When this instruction is executed if the switch connects a logic 0 ground to the test pin of the CPU the program counter in the address register in the CPU will jump to 16 That is the next instruction to be executed would be fetched from ROM Memory location 16 the switch had been connected to a logic 1 negative voltage the program counter would not jump but would be incremented by 1 and hence the instruction in ROM memory location 4 would be executed next Thus the switch status can be tested simply with one instruction Furthermore if it were desired to jump if a test signal equalled a logic
249. t Middle order program counter Field 4 bit PH High order program counter Field 4 bit ai Order i content of the accumulator CM4 Order i content of the command register M RAM main character location Moi RAM status character i DB T Data bus content at time T Stack The 3 registers in the address register other than the program counter Throughout the text page means a block of 256 instructions whose ad dress differs only on the most significant 4 bits all of the instruc tions on one page are all stored in one ROM Example page 7 means all locations having addresses between 0111 0000 0000 and 0111 1111 1111 24 C Format for Describing Each Instruction Each instruction will be described as follows 1 Mnemonic symbol and meaning 2 OPR and OPA code 3 Symbolic representation of the instruction 4 Description of the instruction if necessary 5 Example and or exceptions if necessary D Word Machine Instructions Mnemonic OPR Symbolic Description EEE Mnemonic OPR OPA Symbolic Description NOP No Operation 0000 0000 Not applicable No operation performed LDM Load Data to Accumlator 1101 DDDD DDDD gt ACC The 4 bits of data DDDD stored in the OPA field of instruction word are loaded into the accumulator The previous contents of the accumlator are lost The carry link bit is unaffected Mnemonic OPR Symbolic Description
250. t Low Voltage 4009 Vpp 4 2 12 10 6 5 113 Address Line Sinking 4008 12 Current loro Chip Select and 408 9 13 F L Sinking Current 41 W Output Sinking Current 4008 Data Bus Sinking Current 4009 lots and Strobe Output 4009 Sinking Current 16 4 Output on Resistance 4008 06 gt Bus Output On 4009 130 250 Resistance I O and Strobe Output 4009 on Resistance Output Clamp Current 4008 9 NOTES 1 For TTL compatibility on the I O lines the supply voltages should be Vss 5V 596 Vpp 10V 596 2 Typical values are for TA 259C and nominal supply voltages 3 The address lines will drive a TTL load if a resistor of 470 ohms is connected in series between the address output and the TTL input 4 6 8kohm resistor must be connected between Pin W and for TTL capability V V Pins 1 6 4008 Pins 11 15 20 23 4009 Pins 1 8 16 19 N o o o o 5 5 V V Capacitive Load Only 3 gt Vout 25 Vout 2955 Vout 4 85V 3 3 gt Vout Vss Vout Vss Pins 20 23 mA Vout Vss 2V Pins 20 23 3 3 P P gt BB gt Vout Vss 2V Pins 9 10 16 19 gt Vout Vss 6V All outputs on 4008 Pins 9 10 16 19 4009 107 4008 4009 Characteristics 09 to 70 C Vss Vpp 15V 5 clock sync CM ROM data bus and 1 tim
251. t register 54 152 2 55 41 56 STC ROM ADDRESS MNEMONIC COMMENTS 57 JMS CK DCL subroutine is used to check 58 CK DCL CM RAM lines switching 5 times 59 ISZ 3 60 57 61 SRC 2 62 STC 63 64 155 90 67 68 69 Pointer to 4002 1 0 This section is used to check the jump on condition instruction The numbers refer to the sequence to which the jumps occur Load address for following JIN Restore 4002 1 0 pointer Load markers Load markers 103 LD MK 104 SRC 0 6 105 SUB 4 5106 SUB 5 107 WRM 108 CLB Check SUB instruction 109 ISZ 4 110 104 52 5 112 104 113 CLB Clear Markers 114 SRC 5 115 WMP 116 JIN 7 117 STC 118 INC 8 119 LD 8 120 WRM p Check INC LD DAA instructions 123 WRR 124 DAA 125 WRM 126 ISZ 4 127 117 128 CLB 129 DAC 130 WRM 131 KBP Check DAC KBP instructions 132 WRM 133 ISZ 4 134 129 135 CLB 136 DAA 137 WRM Check DAA IAC instructions 138 IAC 139 ISZ 4 140 136 ROM ADDRESS 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 167 168 169 170 172 173 174 175 176 177 178 179 LDM WRM FIM 178 FIM FIM CLB SRC SRC INC SRC WRM 152 193 SRC MNEMONIC 15 A 0 15 oO oto Un A 0 T 1 _________ ______ Check instruction i i
252. ted by the portion of the I O and RAM instructions Bank switching is accomplished by the CPU after receiving a DCL designate command line instruction Prior to execution of the DCL instruction the desired CM RAM code has been stored in the ac cumulator for example through an LDM instruction During DCL the CM RAM code is transferred from the accumulator to the CM RAM register The RAM bank is then selected starting with the next instruction 20 For chip selection the 4002 is available in two metal options 4002 1 and 4002 2 An external pin Po is also available for chip selection The chip number is assigned as follows Chip No 4002 Option Po Q N O O O 4002 2 VDD PRECHARGE j STATUS CHARACTER MEMORY STATUS 4x4x4CELLS CHARACTER X ADDRESS REGISTER DECODER MAIN MEMORY RAM AND MAIN 4x 16x 4 CELLS MAIN OUTPUT MEMORY TIMING CONTROL REFRESH DECODER COUNTER ADDRESS MUX MEMORY DRIVERS REFRESH AMPLIFIERS MULTIPLEXER DATA BUSS BUFFERS crock 4 1 weeny CONTROL Do 0 0 D3 CLOCK HARD WIRED PHASE2 2 7 91 SELECT SYNC INPS SYNC LIS RESET Figure 7 4002 RAM Block Diagram Presence of CM RAM during X tells 4002 s that an SRC instruction was received For a given combination of data at D gt only the chip with the proper metal option and Po state will be ready for the I O or RAM operation that follows The twenty 4 bit ch
253. th Accumulator and carry CLC 1 1 1 1 00 1 Clear carry IAC 1 1 1 1 0010 Increment accumulator Tid 00 1 1 Complement carry CMA 1 1 1 1 0100 Complement accumulator RAL 4051 Rotate left Accumulator carry RAR 340 11 0110 Rotate right Accumulator and carry 1 1 1 1 01114 Transmit carry to accumulator clear carry DAC 1 1 1 1 1000 Decrement accumulator TCS 11 1 1 100 1 Transfer carry subtract and clear carry STC 1 1 1 1 1010 Set carry 7 1 1 1 10 1 1 Decimal adjust accumulator E 1111 1100 of the accumulator from DCL 1111 1 10 1 Designate command line ere i i NOTES condition code is assigned as follows 1 Invert jump condition 1 Jump if accumulator is zero C471 Jump if test signal is a O intel 0 Not invert jump condition 1 Jump if carry tink isa 1 2 RRR is the address of 1 of 8 index register pairs in the CPU GI RRRR is the address of 1 of 16 index registers in the CPU A ach chip has 4 registers each with twenty 4 bit characters subdivided into 16 main memory characters and 4 status characters Chip number RAM register and main memory character are addressed by SRC instruction For the selected chip and register however status character locations are selected by the instruction code OPA ut 59350 13 4311905 OUDII t SOIN 6L Auvnuaad
254. the character is left justified in registers 14 and 15 leaving the lower two bits zero Both T6R and T6L contain subroutine calls nested three deep and may only be called from the main program except during simulation D10 183 4 7 10 15 This subroutine multiplies the 12 bit binary number in registers 5 7 times ten and adds the number in register 15 to the product then goes to T6R to input another digit This routine may be called repeatedly to input and convert to binary a decimal number A terminal delimiter takes the alternate exit in registers 10 and 11 Register 4 is used for scratch Z47 6 4 7 This routine clears registers 4 through 7 to binary zero in preparation for 010 PUN 80 11 15 This routine prints or punches the character in registers 14 and 15 out on the teletype Registers 11 through 15 are cleared to zero on return IPR 70 11 15 This routine does the same as PUN except that if register 11 is initially even echo mode on input a 15 ms delay occurs to allow the teletype printer to settle RETN 107 11 15 This routine types out a carriage return a null and a linefeed It may only be called from the main routine MSG 66 11 15 This routine types out the character in registers 14 and 15 then follows it with a bell SPACE 63 11 15 This routine types one space DIGIT 53 10 15 This routine types an ASCII digit corresponding to the BCD number in the accumulator If it is zero and the register 10 contain
255. the Instruction Cycle Bw HI R RRO Fetch indirect from ROM Send contents of index register pair location 0 JIN 01 1 O Jump indirect Send contents of register pair RRR out as an address at A1 and A time in the Instruction Cycle c out as an address Data fetched is placed into register pair location RRR 0 JUN r 2 AS Jump unconditional to ROM address A2 A1 2 2 2 2 177124171 i JMS 0101 Jump to subroutine ROM address 2 A4 save old address Up 1 level 2 2 2 2 A1 in stack Increment contents of register 3 0 11 1 RRRR Increment contents of register RRRR Go to ROM address 2 A1 AnA AnA within the same ROM that contains this 152 instruction if result 0 2711270272 TATSI otherwise skip go to the next instruction in sequence AD 1000 RR RR Add contents of register RRRR to accumulator with carry R RRR Subtract contents of register RRRR to accumulator with borrow BEEN R RRR Load contents of register RRRR to accumulator XCH RRRR Exchange contents of index register RRRR and accumulator DD ODD Branch back down 1 level in stack and load data DDDD to accumulator Load data DDDD to accumulator Table V Basic CPU Instruction Set 16 INPUT OUTPUT AND RAM INSTRUCTIONS The RAM s and ROM s operated on in the I O RAM instructions have been p
256. the number all as one string of digits A number typed in may end with a carriage return a comma a space or the letter F or in the case of the directive with plus or minus sign Any other characters will give unpredictable results and should be avoided Rubouts are the only non numeric characters which may be imbed ded within the input number strings with no adverse effects Rubouts are ignored in all cases DESCRIPTION The hardware simulation program allocates a user selected block of RAM main memory locations to hold the ROM instruc tions to be simulated assigning two RAM locations for each simulated ROM location Thus to simulate 512 locations of ROM all 16 RAMs must be used Any RAM locations not allocated for program storage may be accessed in the normal way by the test program In addition the hardware simulation program uses the status characters in twelve consecutive RAM registers equivalent to three RAM chips to hold simulation parameters RAM is assumed to be organized as four consecu tive banks with wraparound of sixteen registers each so that if less than 16 RAMs are used those allocated to program and parameter storage must be in one block of contiguous banks and registers within banks The to tested may have address anywhere the 4096 locations of addressable ROM since the hardware simulator program adds a bias value to all addresses which reference the simulated ROM If the p
257. time As each segment is assembled the assembler will produce the assembled code in the file ROMAR DAT To save the segment that it will not be destroyed by the next assembly the user must rename the ROMAR DAT file with some other name with the extension DAT The last segment assembled is left in the ROMAR DAT file When tbe simulator requests the input file name each segment can be loaded by typing the file name For example a file SEG1 DAT is loaded by typing SEG when the file name is requested After each such named data file is loaded the pro gram will request another file The last file ROMAR DAT is loaded by typing just the carriage return Each file so loaded overlays all previously loaded data except where the newly loaded file contains zeroes NOP s any previously non zero locations are changed by the loading of the file the addresses of the first and last changed locations are typed When assembling a program in segments care must be used to provide sufficient label information for each Segment Because NOP s do not cancel previously loaded data dummy labels may be used as in the following example Suppose a program must call subroutine LBl at address 1100 decimal which has been assembled in a previous segment The proper linkage can be established in the current segment by including the pair of statements 1100D LBl NOP or the pair 1100D LBl 164 APPENDIX I MCS 4 PROGRAMMIN
258. tion of the current instruction Execu tion will resume as if uninterrupted if the T or N directive is typed in after a break 5 Edit Program make corrections to the program the directive is used giving an address and the value s to be entered The I directive alters the contents of the current location counter Thus it should either be noted and restored or the stack pointer may be incremented first and decremented afterwards unless of course the simulation is interrupted at subroutine nest level 3 6 Punch New BNPF Tape After the program works correctly an amended ROM tape may be punched in the format using the P directive Four inches of leader and trailer are punched by this directive If more is needed rubouts nulls shift control P may be punched while the simulation program is waiting for a directive This will not in any way interfere with normal operation of the program The user should remember to turn on the paper tape punch after typing in the second address in the P directive if a tape is to be made If it is desired only to examine the contents of a simulated ROM location this is not necessary 7 Simulation of Segmented Programs If a program is not very large but is scattered over a wide range of addresses it may be possible to accomodate the program in segments Suppose the program occupies the first 32 locations in each of four ROMs 128 locations must be reserved by the
259. to Subroutine Increment Increment and Skip Add Subtract Load Exchange Branch Back Load Immediate Write Main Memory WRite RAM Port Write ROM Port Write Status Char 0 Write Status Char 1 Write Status Char 2 Write Status Char 3 Subtract Main Memory Read Main Memory Read ROM Port Add Main Memory Read Status Char Read Status Char Read Status Char Read Status Char Clear Both Clear Carry Increment Accumulator Complement Carry Complement Rotate Left Rotate Right Co N Transfer Carry and Clear Decrement Accumulator Transfer Carry Subtract Set Carry Decimal Adjust Accumulator Keyboard Process Designate Command Line MNEMONIC NOP JCN FIM SRC FIN JIN JUN JMS INC 152 SUB LD XCH BBL LDM WRM WMP WRR WRG WR1 WR2 WR3 SBM RDM RDR ADM RDG 811 RD2 RD3 CLB CLC IAC CMC CMA RAL RAR TCC DAC TCS STC DAA KBP DCL TABLE 1 BINARY EQUIVALENT lst byte 00000000 00 1 L RRR 010RRR1 LIRRR LIRRR1 0100 0101 0110 1llRRRR 1 RRRR 1001RRRR 1010RRRR 1011 110 1101 11100000 11100001 11190010 11100100 11100101 11100110 11100111 11101004 11101001 11101010 11101011 11101100 11101101 11101110 11101111 11110000 111100401 11110010 11110011 11110100 11110101 11110110 11110111 11111600 11111001 11111919 11111011 11111100 11111101 2nd byte
260. to facilitate loading during actual assembly To accomplish this an ASR 33 teletype was used and the following steps were taken 1 The TTY was placed in the offline mode 2 The paper tape punch control was placed in an on condition 3 Handwritten data was keyed into the teletype keyboard Some typographical errors were edited by using the TT Y s backspace punch control and rubout character The rubout is an all 1 character which effectively deletes any character over which it is superimposed The procedure is as follows 1 Determine the number of backspaces required to return the punch to the erroneous character 2 Depress the paper tape punch backspace control until the erroneous character is reached 3 Enter rubout from the keyboard If a new character must be inserted the previous character and the remaining line or lines must be deleted with rubouts 4 Enter the desired character and remaining lines 138 The assembler s editing features may also be used to simplify the task of correcting errors As an example assume the 18th instruction of the listing RAR were incorrectly entered as RBR it would be unrecognized when assembled A control X control characters are entered by simultaneously depressing the control key and character could be entered after the error The assembler would detect this and respond by requesting the line again The correct line is then entered The assembler maintains co
261. totype system will truly simulate the program memory in the 4001 SIM4 01 SIM4 02 Specifications FEATURES Complete Micro Computer System for Prototyping and or Production 9 Reprogrammable ROMs Simulate 4001s TTY Interface on Clock Two Phase Clock Generator on Card Test and Reset Signal Generator on Card SIM4 01 SPECIFICATIONS Card Dimensions 8 4 inches high 5 7 inches deep MCS 4 Components included on Board sockets included for memory expansion one 4004 four 4002s Maximum Memory Configuration four 4002 RAMs 320 x 4 four 1702 ROMs 1024 x 8 Operating Speed 1 35 us clock period 10 8 us instruction cycle DC Power Requirement Voltage Vec Vss 5 TTL GND OV Vpp 10V 5 Current No load operation lec 1 5 amp 0 6 amp Worst case loading 16 TTL inputs and outputs Icc 1 6 amp lpp 1 5 amp Connector a Solder lug type Amphenol 72 pin connector P N 225 23621 101 b Wire Wrap type Amphenol 72 pin connector P N 261 15636 2 c Wire Wrap type CDC 72 pin connector P N VPBOIE36300A1 SIM4 01 Prototyping Board 60 SIM4 02 SPECIFICATIONS Card Dimensions 11 5 inches high 9 5 inches deep MCS 4 Components included on Board sockets included for memory expansion one 4004 four 4002s Maximum Memory Configuration sixteen 4002 RAMs 1280 x 4 sixteen 1702 ROMs 4096 x 8 Operating Speed 1 35 us clock period 10 8 us i
262. ts of ROM output display and 32 bits of RAM output display The additional 32 bits of RAM output are not displayed but brought out to 16 pin sockets J6 and J7 Data out control switch enables or disables the data from the MP7 03 to the SIM4 02 input ports or provides CPU software control of data out when in the duplicating position A DC power control switch which connects the external 5V and 10V power supplies to the SIM4 02 and MP7 03 Two momentary pushbutton switches which drive the test and reset input lines on the SIM4 02 board Two transformers a switch for 115V AC 220V AC capacitor fuse holder and AC input jack wired to the lated 80V DC which in turn is regulated on MP7 03 to 47V DC programming voltage A PRGM AC switch which controls the programming AC voltage Input jacks for applying externally supplied DC and 10V DC to the assembly Note Internal supplies are not in cluded 5V 4A and 10V 2 supplies required worst case T he setup for the PROM Programming application is shown below The MP7 03 rear and the SIM4 02 board are installed in MCB4 20 MCB4 20 MP7 03 SIM4 02 System 124 1 Micro Processor System When the MCB4 20 is used as a micro processor its features such as the output ports with displays and input ports may be utilized at the discretion of the user As an example consider the testing of SIM4 02 boards loaded with a PROM containing
263. uction word is divided into two 4 bit fields upper 4 bits is called the OPR and contains the operation code The lower 4 bits is called the OPA and contains the modifier For a single word machine instruction the operation code OPR contains the code of the operation that is to be performed add subtract load etc The modifier contains one of 4 things 1 A register address 2 register pair address 3 4 bits of data 4 An instruction modifier 10 For a 2 word machine instruction the lst word is similar to a l word instruction however the modifier contains one of 4 things 1 A register address 2 A register pair address 3 The upper portion of another ROM address 4 A condition for jumping ONE WORD INSTRUCTIONS TWO WORD INSTRUCTIONS 1st INSTRUCTION CYCLE 2nd INSTRUCTION CYCLE D D D D D D Dy D 02 D Dg D D Dy D D2 D Dg 03 D Dy D OPR OPA OPR OPR OP CODE x x INDEX REGISTER MIDDLE ADDRESS LOWER ADDRESS R R R R A3 A3 Ay A OR x x INDEX REGISTER PAIR CONDITION MIDDLE ADDRESS LOWER ADDRESS R u R x Ag 1 A OR DATA MIDDLE ADDRESS LOWER ADDRESS D D D D R R A A OR INDEX REGISTER PAIR Px x fx x REGISTE UPPER DATA LOWER DATA R R R x 02 02 2 02101 D D D Table Machine Instruction Format The 2nd word contains either the mid
264. ue will truncate modulo 4096 at each step Negative numbers may be calculated and are handled in two s complement notation e g N 4096 N FORMAT The assembler is a line statement free format assembler in the following sense each line of the source text except for comment lines assembles into one machine instruction or one byte of data each field of the source code line is defined by its context and not by its fixed position in the line The typical line of source code begins with a linefeed The next character determines the interpretation of the line If it is a dollar sign the previous line is considered as the end of the source text and the assembler proceeds to the next pass If it isa control ASCII start of header SOH header information terminated by a Control B ASCII start of text STX is anticipated If it is an alphabetic character it is interpreted as the first character of a label A space is interpreted as the terminator for a null label field The assembler then expects a mnemonic or a pseudo operand If a 4 or is entered a fatal error results If the first character is any other than those mentioned above the remainder of the line is treated as comment 131 LINE NUMBER AND PRINTED BY ASSEMBLER POSSIBLE OPERANDS COMMENT d cp o S 7 LABEL SEPARATOR PSEUDO OP OR SEPARATORS TERMINATOR INSTRUCTION MNEMONIC Figure 5 1 State
265. ues should be in decimal 7 All conditional jumps should be coded with the JCN mnemonic and the appropriate condition name 8 Comments on source text lines should be preceded by slashes and comment lines must have a slash in column 1 i e the first character after the linefeed 9 Pseudo ops should be avoided except to assign values to condition names at the beginning or end of the program tape where they are easily removed 135 LIST OF OPERATING INSTRUCTIONS Those instructions preceded by an asterisk are 2 word instructions that occupy 2 successive locations in ROM MACHINE INSTRUCTIONS Logic 1 Low Voltage Negative Voltage Logic 0 High Voltage Ground PTION OF OPERATION 03020 Do Ds D gt D4 Dy DESCRI Jump to ROM address 2 2 2 2 A1 A4 A1 A1 within the same ROM that contains this JCN instruction if condition C4 C2 C3 c4U JCN 0001 C4 C2 C3 C4 2 2 2 2 A4 AY is true otherwise skip go to the next instruction in sequence 0010 R RRO Fetch immediate direct from ROM Data 02 D4 to index register pair 02 02 02 02 0 0 Di 0 location RRR Send register control Send the address contents of index register pair RR R to ROM and RAM at X2 and X3 time in the Instruction Cycle Fetch indirect from ROM Send contents of index register pair location 0 out as an address Data fetched is placed into register pair location RRR R R RO Jump
266. ulated sync cycle counter This is 12 bit decimal counter used to tally the number of instruction cycles used during instruction simulation Trace This directive causes the simulation program to begin simulated execution of the test program beginning at the address in the current location counter If instruction execution simulation is interrupted by a breakpoint the keyboard BREAK key or an illegal instruction the T directive will cause the program to resume where it left off just as if the program was never interrupted except insofar as program parameters or registers were modified while interrupted The basic format of the trace listing is where is the decimal location counter iiiiiiii is the binary representation of the first byte of the instruction being simulated c is the resultant carry link bit is the resultant accumulator value and rr is the resultant decimal index or index pair used in the instruction value not index number Any or all of the last three numbers may be omitted on instructions which do not reference their respective registers Non trace This directive is identical to the T directive except that execution proceeds without tracing Options This directive may be used to display and or alter the current option status bits This isa 4 bit binary number with the following significance 1 Input Output and CPU test instructions executed directly when this bit is on instead of typi
267. uration for TTL Compatibility The input options for the 4001 are shown with the detailed des cription of the 4001 I O ports 11 other inputs are high impedance MOS inverters Inputs to the 4001 and 4003 are TTL compatible the 4001 non inverting option is an exception OUT Figure 39 Typical MCS 4 Input and Output Circuitry 102 Absolute Maximum Ratings Ambient Temperature Under Bias to 70 C COMMENT Storage Temperature 55 C to 150 C Stresses above those listed under Absolute Maximum Ratings Input Voltages and Supply Voltage may cause permanent damage to the device This is a stress rating With Respect to 0 5 to 20V only and functional operation of the device at these or any other te s condition above those indicated in the operational sections of this Power Dissipation j 1 0 W specification is not implied D C and Operating Characteristics 4001 4002 4003 4004 to 700 Vpp 15 5 Ves GND 400 1 02 150 unless otherwise specified Logic 0 is defined as the more positive voltage Logic 1 is defined as the more negative voltage Vj VoL SUPPLY CURRENT LIMIT PRODUCT SYMBOL PARAMETER MIN TYP UNIT TEST CONDITIONS AVERAGE SUPPLY CURRENT 15 30 mA TA 259C 4002 1502 AVERAGE SUPPLY CURRENT T 25 C 4003 1003 4004 1504 INPUT CHARACTERISTICS ALL INPUTS EXCEP
268. using the MP7 03 programmer system The same tape may be used for programming the 4001 metal mask ROM See Appendix F SIM4 Hardware Simulator The SIM4 02 Hardware Simulator is a program written for the MCS 4 This program will provide interactive control over the debugging of other MCS 4 programs See Appendix G The minimum configuration required is a SIM4 02 prototype card with three 4002 RAMs and a Teletype When fully stuffed with 16 RAMs test programs up to 512 bytes locations in length may be accomodated The hardware simulation program itself occupies nine full ROMs The Hardware Simulation Program has two basic functions 1 To simulate the execution of a test program tracing its progress and apprehending gross errors 2 To allow the user to dynamically interact with and or modify his test program in order to facilitate the debugging process These two functions are implemented by means of a set of directives or commands which the user types in at the teletype keyboard Some of the directives call for typeouts by the simulator program some of the directives signal the input of data or program modifications and some of the directives involve both typeouts and input response or data 4 MCS 4 Program Library Text editor assembler and loader the MCS 4 Teletype Keyboard Input Routine that runs on the PDP 8 PROM Programming Software Package for the SIM4 01 e Subroutine for driving a Seiko printer 7 03 and
269. uter tron Intel can provide the same arithmetic control and computing functions of a minicomputer in as few as two 16 pin DIP s and costs neafiy 2 orders of magnitude less The set is not designed to compete with the minicomputer but rather to extend the power of the concept into new ranges of applications For example many systems now built of SSI and MSI TTL can now be implemented with a totally self contained system built around this set of devices Heart of each system is a single chip central processor unit CPU which performs all control and data processing functions Auxiliary to the CPU are ROM s which store microprograms and data tables RAM s which store data and instructions and Shift Registers which expand the I O capacity of the system The MCS 4 system communicates with circuits and devices outside the family through ports provided on each RAM and ROM system using this set of devices will usually consist of one CPU from one to 16 ROM s up to 16 RAM s and an arbitrary number of SR s A minimum system could be designed with just one CPU and ROM With these components you can build distributed computers dedicated computers or personalized computers and utilize the almost infinite combinations of microprogramming The designer buys standard devices and with microprogramming of the ROM fulfills his own unique circuit requirements The three major advantages of Intel microcomputers Great syst
270. utput pins until a new WMP is executed on the same RAM chip The content of the ACC and the carry link are unaffected The LSB bit of the accumultor appears on Oo Pin 16 of the 4002 Mnemonic ADM Add from memory with carry OPR OPA 1110 1011 Symbolic ACC CY ACC CY Description The content of the previously selected RAM main memory character is added to the accumulator with carry The RAM character is unaffected Mnemonic SBM Subtract from memory with borrow 1110 1000 Symbolic M ACC CY CY Description The content of the previously selected RAM character is subtracted from the accumulator with borrow The RAM character is unaffected G Accumulator Group Instructions Mnemonic CLB Clear both OPR 1111 0000 Symbolic 0 ACC 0 CY Description Set accumulator and carry link to 0 Mnemon c CLC Clear carry OPR 1111 0001 Symbolic 0 CY Description Set carry link to 0 Mnemonic CMC Complement carry OPR OPA 1111 0011 Symbolic CY CY Description The carry link content is complemented Mnemonic STC Set carry OPR 1111 1010 Symbolic 1 CY Description Set carry link to a 1 Mnemonic CMA Complement Accumulator OPR OPA 1111_ 0100 Symbolic 2 1 0 ACC Description The content of the accumulator is complemented The carry link is unaffected Mn
271. x register is incremented by 1 The accumulator and carry link are unaffected If the result is zero the next instruction after 157 is executed If the result is different from 0 program control is transferred to the instruction located at the 8 bit address 2 2 2 2 1 1 1 1 on the same page ROM where the ISZ instruction is located EXC PTIONS If ISZ is located on words 254 and 255 of a ROM page when ISZ is executed and the result is not zero program control is transferred to the 8 bit address located on the next page in sequence and not on the same page where ISZ is located r s Mnemonic FIM Fetched immediate from ROM lst word OPR 0010 RRRO 2nd word OPR OPA D2D2D2D2 101010101 Symbolic D2D2D2D2 gt RRRO 21010101 RRR1 Description The 2nd word represents 8 bits of data which are loaded into the designated index register pair F Input Output and RAM Instructions The RAM s and ROM s operated on in the I O and RAM instructions have been previously selected by the last SRC instruction executed Mnemonic RDM Read RAM character OPR OPA 1110 1001 Symbolic M ACC Description The content of the previously selected RAM main memory character is transferred to the accumulator The carry link is unaffected The 4 bit data memory is unaffected Mnemonic RDO Read RAM status character 0 OPR OPA 1110 1100 Symbolic Mso AcC

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