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Intel Computer Hardware I/O Processor User's Manual

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1. ssseeeene enm 40 3 9 6 1 Switch S1C2 80332 ReSOt oriei aai 40 3 9 6 2 Switch S6A1 BPCI X Reset 40 3 9 6 3 Switch S8A1 Rotary sessssssssesesseeeeeeeneeneen nennen enn 40 3 9 6 4 Switch SZAT s desc esee a E aee da c eL ER dne rods 40 3 9 6 4 1 S7A1 1 PCI X Bus A Speed Enable corresponding to signal name PBI AD340 3 9 6 4 2 S7A1 2 Reset IOP core corresponding to signal name PBI AD540 3 9 6 4 S7A1 3 Configration Cycle Enable corresponding to signal name PBI AD641 3 9 6 4 4 S7A1 4 PCI X Bus B Speed Enable corresponding to signal name PBI AD1041 3 9 6 4 5 S7A1 5 PCI X Bus B Hot Plug Reset Disable corresponding to signal name PBI AD1141 3 9 6 4 6 Switch S7A1 6 Hot Plug Capable Disabled corresponding to signal name PBI AD1541 3 9 6 4 7 Switch S7A1 7 SMBUS Manageability Address Bit 0 corre sponding to signal name PBI AD1742 3 9 6 4 8 Switch S7A1 8 SMBUS Manageability Address Bit 3 corre sponding to signal name PBI AD1842 3 9 6 4 9 Switch S7A1 9 SMBUS Manageability Address Bit 2 corre sponding to signal name PBI AD1742 3 9 6 4 10 Switch S7A1 10 SMBUS Manageability Address Bit 1 corre sponding to signal name PBI AD1642 3 9 6 5 Jumper J7D1 Flash bit width seeseeeenne 43 3 9 6 6 Jumper J1C1 JTAG Chain essiri 43 3 9 6 7 Jumper J1D2 UART Control 43 3 9 6 8 Jumper J7B4 SMBus Header ssssssseeeee 44 3 9 6 9 Jumper J9D3 Buzzer Volume Contro
2. cens 30 10 Peripheral Bus Feature eissvetscieciexcedensasscanagsennsadaacnecxossdgannaacingcanenaensudaess sauscepansiessndinsaunestaanazonocteens 31 11 Flash ROM Fedu OS osar aane EEEE Aa SEELE ESS ERES TERENAS iE 32 12 Rotary Switch Requirements ecenin ean EEEE EAE EE enne 33 13 Battery Status Buffer Requirements sssssisodssiisiii eredi nsn SK A A 34 14 Reset Requirements Schemes sciare i nE NENN EANA ARARA RENAA 37 15 OWC SUMMANY ciel Gece E ES heh tele a ieee 38 MES ur T 38 i7 Jumper SUMMAN m 39 18 Comieco o Umma N e a TT E A O 39 19 J2D2 GPIO Header DennmitioM aenieith iaae aE E AEAEE oett 39 20 Rotary SWitCh Seling E esre a EO E E 40 21 S7A1 1 PGI X Bus A Speed Enable innert retentu AA KENNERS 40 22 Switch S7A1 2 Reset IOP Settings and Operation Mode seeee 40 23 Switch S7A1 3 RETRY Settings and Operation Mode seeeeen 41 24 S7A1 4 PCI X Bus B Speed Enable Settings and Operation Mode ssessss 41 25 S7A1 5 PCI X Bus B Hot Plug Reset Disable Settings and Operation Mode 41 26 Switch S7A1 6 Hot Plug Capable Disabled Settings and Operation Mode 41 27 Switch S7A1 7 SMBUS Manageability Address Bit 0 Settings and Operation Mode 42 28 Switch S7A1 8 SMBUS Manageability Address Bit 3 Settings and Oper
3. Battery Backup Unit Battery back up circuit for SDRAM Ethernet Intel R 82545EM Gigabit Ethernet Controller Flash ROM 8 MB Flash ROM 3 3 V 16 bit Flash I F Form Factor PCI X card 312 X 107 mm General Purpose I O GPIO Pins are used as described in the appropriate section in this document Hex Display Two 7 segment Hex LED displays JTAG Port ARM compliant JTAG Header Logic Analyzer Logic analyzer connectors on the DDRII SDRAM interface Interposer Card may be used for the memory bus Information supplied separately Memory 256 MB 512 Mb x 16 DDRII SDRAM 400 MHz DIMM ECC Registered Onboard Power Board sources 1 25 V 2 5 V 3 3 V 5 V 12 V and 12 V from primary PCI connector All core voltages are derived from 3 3 V supply Auxiliary power for the Secondary PCI slot Power LED Power on green Primary PCI PCI Express x8 lane RAID Support Support for RAID Implementation Ability to make the devices plugged in the secondary expansion slots Private Integrated XOR engine and two iSCSI CRC32C off load engines Secondary PCI e 1 64 bit PCI X connector 133 MHz 164 bit 100 MHz PCI X Intel R 82545EM Gigabit Ethernet Controller also on the 100 MHz PCI Serial Port Dual RJ11 serial port connectors The 80332 has two integrated UART serial ports which are 16550 compatible
4. Evaluation Platform Board Manual intel Getting Started 2 2 1 2 2 Warning 2 2 1 Note The 80332 is a software development environment for IQ80332 Software updates and additional offerings from vendors can change frequently To keep up to date please visit http www intel ioprocessortools com kshowcase view for the latest updates Kit Content The 80332 Kit contains the following items Q80332 with 400 MHz DDRII SDRAM DIMMs CodelLab Development Environment from Accelerated Technology Incorporated JTAG Emulation unit Serial Cable and RJ11 Adapter Hardware Installation Static charges can severely damage the boards Be sure you are properly grounded before removing the board from the anti static bag First Time Installation and Test For first time installation visually inspect the 80332 for any damage made during shipment Follow the host system manufacturer s instructions for installing a PCI Express adapter card The board is a full length host bus adapter card that requires a PCI Express slot free from obstructions The 1080332 has a x8 read as by eight edge connector Please note at this time the IQ80332 does NOT work in a passive backplane This is due to the nature of the PCI Express linking protocol For the I O processor to successfully come out of reset a link must be established on the PCI Express bus Without another device on a passive backplane to talk to a link is not
5. Memory Flash The OCDemon Flash Memory Programmer window appears The Flash programmer needs a file which is architecture specific in this case In the Flash programmer window select File Open then choose the file Xscale TBD ocd at C MGC Embedded codelab codelab Debug Macraigor Click the Program button 10 Click Browse and Files of type All Files then choose the redboot ROM srec file downloaded and uncompressed from developer com Check box Erase Target Flash Sector s Before Programming Click Program The Flash now programs and verifies click Close when 10096 complete Cycle power to the board to see that the LEDs on the board sequence 8 8 A5 A6 S L then AT This is the normal LED sequence of RedBoot The board may need to be reset more than once Explore the other features of the Flash programming window The contents of the Flash can be erased copied to a file on the host and verified against a file on the host 60 Evaluation Platform Board Manual B 6 Note Note Intel 180332 I O Processor Getting Started and Debugger Debugging Out of Flash JTAG debuggers can be used on two levels with or without the source code When the Flash is programmed the debugger can monitor the executable code halt it step through it and monitor the memory and registers The executable code is disassembled so that the assembly code can be exam
6. Host port connected to the platform board UART The following communication tools can be used Win32 using HyperTerminal UNIX using Kermit Linux using Minicom Solaris using Tip RedBoot Monitor startup Description terminal emulator runs on host and communicates with the board via the serial cable Start Power up the IQ80332 While the reset is asserted the two 7 segment LEDs sequentially display 88 AO through A6 followed by SL Scrub loop When RedBoot is successfully booted it displays the characters A1 on the LEDs When the final state of A1 does not occur reset the processor again The time for reset is approximately 1 or 2 seconds Win32 on Host Connecting with HyperTerminal Evaluation Platform Board Manual 21 Intel IQ80332 I O Processor Getting Started n To bring up a HyperTerminal session on a Win32 platform Go to Start Programs Accessories Communications HyperTerminal HyperTerminal setup screens Connection Description Panel Enter name Connect To Panel e Select host com2 port or whichever port you are using Port Settings e Bits per second 115200 e Data Bits 8 e Parity none e Stop Bits 1 e Flow Control none Start HyperTerminal e Select Call from HyperTerminal panel Reset or power up 80332 board The Host screen reads RedBoot tm debug environment built dd mm yy Mon dd 2004 Platform 80332
7. a The CodelLab Debug environment appears with the Assembly window open Note Mouseovers are available for most of the toolbar icons Leave the mouse over the debug icons across the top on the toolbar to see a brief explanation of each 4 Click on the go icon and let RedBoot boot takes a minute until the RedBoot prompt RedBoot gt appears in the Console window click the Console tab at the bottom of the Debug window to view the Console window 5 From the console window a type diag b hit Enter The RedBoot Diagnostic function is invoked Try out a few of the tests as desired 6 Close the Debugger and EDE environment 7 Reset the board cycle power B 7 2 Manually Loading and Executing an Application Program 1 Launch the CodelLab Debug Environment from the desktop icon 2 Ensure File Program Load Options Load Executable and Symbols is checked 3 file program load options load executable and symbols a Select file open program browse b go find c lt RedBoot downloaded Files VTestI LED O Test1 LED elf 4 Hit Go 80 3 32 and 21 cycle on the LEDs 5 Cycle power on the board 62 Evaluation Platform Board Manual intel Intel IQ80332 I O Processor Getting Started and Debugger B 7 3 Displaying Source Code 1 Launch the CodelLab EDE Debugger and open the Tester I LED ELF program Note Use the File Recent Programs menu for quick access 2 3 4 Select
8. Copyright C 2004 RedHat Inc RAM 0xa0000000 0xa2000000 FLASH 0x00000000 0x00800000 64 blocks of 0x00020000 bytes each IP 192 168 0 1 Default server 0 0 0 0 RedBoot gt For further information on the GDB Insight Debugger refer to the content of the GNUPro CD and or the GNUPro Debugging Tools manual This setup assumes that RedBoot is Flashed on the board 22 Evaluation Platform Board Manual m Intel 1Q80332 I O Processor l n Getting Started 2 6 4 2 Connecting with GDB Below are the GDB commands entered from the command prompt Be sure system path is set to access xscale elf gdb exe File name in example hello Bold type represents input by user gt xscale elf gdb nw hello Start GDB executable loads debug information and symbols GDB set remotebaud 115200 Set baud rate for the 80332 Connect COM port When using Windows command prompt GDB target remote com1 Example screen output from board to host GDB target remote coml Remote debugging using coml GDB When using Linux GDB target remote dev ttyS0 GDB load Load the program to the board may have to wait a few seconds GDB break main Set breakpoint at main GDB continue Start the program using continue verse the usual run Program hits break at main and wait 1 To be supplied separately Evaluation Platform Board Manual 23 Intel IQ80332 I O Processor Getting Started 24
9. Hardware breakpoints step and breakpoint in code in either ROM or RAM without altering the code stacks or other target information Hardware breakpoints handle difficult issues by providing the ability to set the processor conditions that cause the program to halt Use hardware breakpoints to locate problems such as reentrance obscure timing etc The 80332 contains two instruction breakpoint address registers IBCRO and IBCR1 one data breakpoint address register DBRO one configurable data mask address register DBR1 and one data breakpoint control register DBCON The 80332 also supports a 256 entry trace buffer that records program execution information The registers to control the trace buffer are located in CP14 Evaluation Platform Board Manual 67 Intel IQ80332 I O Processor Getting Started and Debugger n B 9 3 C 9 3 Exceptions Trapping A debug exception causes the processor to re direct execution to a debug event handling routine The Intel 80200 processor debug architecture defines the following debug exceptions instruction breakpoint data breakpoint software breakpoint external debug break exception vector trap trace buffer full break When a debug exception occurs the processor actions depend on whether the debug unit is configured for Halt mode or Monitor mode POWERED ARM 68 Evaluation Platform Board Manual
10. Hot Plug Capable Disabled Settings and Operation Mode S7A1 6 Operation Mode Open Hot Plug on Bus B Enabled Closed Disables Hot Plug on Bus B Default mode Evaluation Platform Board Manual 41 Inte IQ80332 I O Processor Hardware Reference Section 3 9 6 4 7 Table 27 3 9 6 4 8 Table 28 3 9 6 4 9 Table 29 3 9 6 4 10 Table 30 42 intel Switch S7A1 7 SMBUS Manageability Address Bit 0 corresponding to signal name PBI AD17 This allows 80332 to address SMBus Slave Address bit 0 PBI A17 Switch S7A1 7 SMBUS Manageability Address Bit 0 Settings and Operation Mode S7A1 6 Operation Mode Open SMBus Manageablity Address Bit 0 1 Default Mode Closed SMBus Manageablity Address Bit 0 0 Switch S7A1 8 SMBUS Manageability Address Bit 3 corresponding to signal name PBI_AD18 This allows 80332 to address SMBus Slave Address bit 3 PBI_A18 Switch S7A1 8 SMBUS Manageability Address Bit 3 Settings and Operation Mode S7A1 8 Operation Mode Open SMBus Manageablity Address Bit 3 1 Default Mode Closed SMBus Manageablity Address Bit 3 0 Switch S7A1 9 SMBUS Manageability Address Bit 2 corresponding to signal name PBI AD17 This allows 80332 to address SMBus Slave Address2 PBI A17 Switch S7A1 9 SMBUS Manageability Address Bit 2 Settings and Operation Mode S7A1 9 Operation Mode Open SMBus Ma
11. This Page Left Intentionally Blank Evaluation Platform Board Manual intel Veneri I s Hardware Reference Section 3 3 1 Functional Diagram Figure 5 shows the functional block for the 80332 Figure 5 Functional Block Diagram Target Market ROMB PCI Express RAID card DDR Il 400 DDR SDRAM HER Battery 1 Backu LED Buzzer p HSV748eNS ans X8 Edge Connector Evaluation Platform Board Manual 25 Intel IQ80332 I O Processor Hardware Reference Section n amp 3 2 Board Form Factor Connectivity Table 6 summarizes the form factor and connectivity features for the 80332 Table 6 Form Factor Connectivity Features Description The IQ80332 is a x8 PCI Express card with form factor depicted by Figure 6 The 80332 connects to the Primary PCI Express bus of the host machine The 80332 has two PCI X expansion slot The 80332 has two serial ports and one RJ 45 Ethernet port The 80332 has one JTAG port compliant with ARM Multi ICE 20 pin connector standard The JTAG is targeted for the Intel XScale core and the CPLD and is used for software debug purposes Figure 6 Board Form Factor i PCI X Slot straddles board edge Cs SS BHEBBED cO BaagpRESSHHRESESBEDERHEEEEESRS la a EM DE DDR II DIMM SERES CPLD C
12. m Intel 1Q80332 I O Processor l ntel Hardware Reference Section 3 8 Board Reset Scheme Figure 10 depicts the reset scheme for the 80332 Table 14 list the reset schemes for the 80332 Table 14 Reset Requirements Schemes Description Primary PCI reset resets all devices on the board It occurs during the power up The SRST signal from the JTAG connector is a bi directional signal that can force a reset similar to the power up reset on the board Figure 10 RESET Sources DDR II SDRAM Reset Button Voltage Monitor Isolation Evaluation Platform Board Manual 37 Inte IQ80332 I O Processor Hardware Reference Section 3 9 3 9 1 Table 15 3 9 2 Table 16 Figure 11 38 Switches and Jumpers Switch Summary Please note that the term open refers to the individual pin of switch S7A1 being pushed in at bottom small dot on pin away from the open label on the switch The term closed refers to the pin being pushed in at the top Please see Figure 11 Default Switch Setting Switch S7A1 on page 38 for more details Switch Summary Switch Association Description m S1C1 80332 Reset S6A1 BPCI X Reset S7A1 1 APCI X Bus PCI XBus A Speed Set Closed S7A1 2 IOP RESET Sets IOP Reset Mode operation Open S7A1 3 IOP RETRY Sets IOP RETRY Mode operation Open S7A1 4 BPCI X Bus P
13. 3 anufacturer ationa Sensor URL http www national com pf LM LM75 html Program Manufacturer Maxim mable Reset d al i 2 a Ai A IC URL http www maxim ic com quick_view2 cfm qv_pk 1524 Registered IDT74SSTU3 Manufacturer IDT Integrated Device Technology Buffer 2864BF URL http www1 idt com pems products taf catID 97 amp genID 74SSTU32864 Program IDTCSPU877 Manufacturer IDT Integrated Device Technology mable PLL BV URL http www1 idt com pems products taf catID 112 amp genID CSPU877 256 bit 1 wire DS2430A_TS Manufacturer Maxim EEPROM OC URL http www maxim ic com quick_view2 cfm qv_pk 2913 3 3V MAX561 Manufacturer Maxim Transceiver URL http www maxim ic com quick view2 cfm qv pk 1544 Battery ADP3801 Manufacturer Analog Devices Charger URL http www analog com UploadedFiles Data Sheets 308746738ADP3801 2 O0 pdf 10 Evaluation Platform Board Manual m Intel 1Q80332 I O Processor l n Introduction 1 5 Terms and Definitions Table 4 Terms and Definitions Acronym Term Definition ARM Refers to both the microprocessor architecture and the company that licenses it CRB Customer Reference Board ICE In Circuit Emulator A piece of hardware used to mimic all the functions of a microprocessor IOP I O processor Joint Test Action Group A hardware port supplied on Intel XScale microarchitecture JTAG evaluation boards used for in depth testing and debug
14. 8 4 4 Debug and Console Windows eseseseeeeeeeenn mener 65 B 8 5 Memory WIndOW cited sieut send eet ex nea catt Ye edu tuu e ed dk E e edu Y 65 B 8 6 Registers WindOW irent apre eoe vast sep Rm are EUER A a M RRRXM Miu UEEA 66 BOT Watch WINdOW ciiin ai vicars devastate cubed Pad du x Rd e ee dn uv 66 B 8 8 Variables WindOw ooi En ee ik reete pupa ase RR x ru t tpa RE e dH ERR 66 Bo DEBUGGING BASICS etre eet t eee ce render v dua Dec e ru eua 67 BOT OVON em 67 B 9 2 Hardware and Software Breakpoints esseeseeeeeneeeene 67 B 9 2 1 Software Breakpoint seriioecsi nan nennen 67 B 9 2 2 Hardware Breakpoints ccccccececeeesceceeeeecceeeseeeaaeeeeeeeaaeeeeseeeaeeneneeas 67 B93 0 9 3 Exceptions Trapplng saeson RR REO pa a Re ER IRE Nu du PERRR E 68 Document Number 274069003US September 2005 5 Contents l n Intel IQ80332 I O Processor Evaluation Platform Board Manual tel Figu 1 res Intel 80332 I O Processor Block Diagram cscessesssssssessessessessseesessessessteesetsnssesieseteeesesseesen 13 S erial YART GOMMUNICALON iets ense eR EHE eR EE E eeu o Rue Re ced qeswec can ERR Ex REM UTERE Re Ye REN RENE 19 JTAG Debug Comtiunicaltlon uee nocendi repere Eres nage rue a de AEAEE ne dad Ru 19 Network Communication Example essen nennen nennen enne 20 Functional Block Diagana 25 Board Form FACOLT A E E T poseer rk lana 26 Inte
15. Processor Bus B3236 02 32 Evaluation Platform Board Manual Intel 3 6 2 3 6 3 3 6 4 3 6 5 3 6 6 Table 12 Inte IQ80332 I O Processor Hardware Reference Section UART The 80332 has two integrated UARTs Each asynchronous serial ports supports all the functions of a 16550 UART The UART signals are connected to a dual RS 232 buffer and then to a RJ 11 serial port connector mounted on the bracket of the evaluation board The serial port and GPIO signals are muxed on the same pins Jumper J1D2 located next to the serial port buffer can disable the buffer to allow the signals to be used as GPIO signals Please see Section 3 9 3 Jumper Summary on page 39 for more details Non Volatile RAM In addition to the 8MB Flash device the IQ80332 has a separate 32k by 8 non volatile RAM device on the peripheral bus The NVRAMs address range is from CE87 0000 to CE87 FFFF in hex Please see Section 4 2 2 Peripheral Bus Memory Map on page 47 for more details Audio Buzzer The 80332 evaluation board has an audio buzzer that is turned on and off by writing to the Buzzer Control Register located in the CPLD Jumper J9D3 adjusts the volume from off to soft to loud Please see Section 3 9 3 Jumper Summary on page 39 for more details The audio buzzer s address range is from CE86 0000 to CE86 FFFF in hex Please see Section 4 2 2 Peripheral Bus Memory Map on page 47 for more details HEX Display
16. Software Development Tools These tools are for evaluation purposes and do not include any support Please contact the vendor directly for additional information and support They include but are not limited to RedHat GNUPro tools ARM RealView Developer Suite WindRiver VxWorks RTOS and Tornado Development Tools Wasabi Systems NetBSD ODS TimeSys Linux RTOS Accelerated Technology Inc Nucleus Plus RTOS and Development Tools Please contact your Intel representative for the latest updates or visit http www intel ioprocessortools com kshowcase view Contents of the Flash The production version of the board contains an image for RedHat RedBoot target monitor Evaluation Platform Board Manual 17 Getting Started Intel IQ80332 I O Processor i n lal 2 5 2 5 1 Target Monitors RedHat RedBoot RedBoot is an acronym for RedHat Embedded Debug and Bootstrap and is the standard embedded system debug bootstrap environment from RedHat replacing the previous generation of debug firmware CygMon and GDB stubs It provides a bootstrap environment for a range of embedded operating systems such as embedded Linux and eCos and includes facilities such as network downloading and debugging It also provides a simple Flash file system for boot images RedBoot provides a set of tools for downloading and executing programs on embedded target systems as well as tools for manipulating the target system s env
17. established Evaluation Platform Board Manual 15 Intel IQ80332 I O Processor Getting Started n 2 2 2 Caution Power Requirements The 80332 requires a 3 3 V supply coming through the PCI Express primary connector Plug the board into a desktop with a PCI Express slot The 80332 has an auxiliary power receptacle J1A1 see Section 3 9 4 Connector Summary that is used to power the secondary PCI X slot This connector is compatible with a standard ATX hard drive power connector Before connecting power to the entire system verify that the auxiliary system power to the secondary PCI X slot and the main power to the 80332 are both connected Both power rails should come up at the same time When there is not a card plugged into the secondary PCI X slot then the auxiliary power can be left unconnected Evaluation Platform Board Manual intel 2 3 2 4 2 4 1 2 4 2 Intel 1 80332 I O Processor Getting Started Factory Settings Make sure that the switch jumper settings are set to proper positions as explained in Section 3 9 Switches and Jumpers on page 38 Development Strategy Supported Tool Buckets For developing and debugging software application the production version of the 80332 kit includes the CodelLab Development Environment Support for the CodelLab development environment is available from ATI Please refer to the enclosed package The kit also contains evaluation copies for several
18. menu under Look In to find the four files listed in step 7 on the hard drive Select all four files and click open The Solution Explorer window now shows these files under Project80332 Evaluation Platform Board Manual 57 Intel IQ80332 I O Processor Getting Started and Debugger n z B 3 2 58 Note Configuration Examine the main menu of CodelLab EDE for NET File Project codellab EDE Tools Help Edit View Build Debug Window Since CodelLab is a plug in to Visual Studio some of these menu items are Visual Studio and some are specific to CodelLab Click on any of these menu items and the drop down menu displays the subordinate menu items Many of these items have defined tool bar symbols function keys and keyboard patterns as alternatives Projects can be built under the codellab EDE menu or under the build menu Always use the codellab EDE menu to perform CodelLab project builds Builds under the build menu invoke the Visual Studio C compiler 1 2 10 12 13 On the main menu select codellab EDE Configuration When the codellab EDE Configuration window appears click on each of the words in the left box Notice that the rest of the window changes when you click on different parts of the menu tree This is a typical feature of CodelLab EDE for NET Click on Toolsets Click on the drop down arrow and select RedHat GNU Tools for XScale T
19. registers and variables The combination of the flow control and data functions allows the developer to debug problems as they occur or to validate the application code As the size of an application grows the need to be able to narrow down the cause of a problem to a few lines of code is imperative Debuggers have a finite set of capabilities and limitations Debuggers can give insight that is difficult to obtain without them but they can fail when they are not used within the limits of their functionality They are intrusive by definition They are software programs that interact with software monitors or hardware JTAG to control a target program Ultimately the debugger works best when the developer understands what it can and can not do and uses it within those constraints Hardware and Software Breakpoints The following section provides a brief overview of breakpoints See the Intel 80332 I O Processor Developer s Manual for more detailed information Software Breakpoints Software breakpoints are setup and utilized via debugger utilities such as CodelLab The abilities of software breakpoints were seen in Section B 7 of this Guide Program execution can be halted at a particular line of code stepped through and executed again to the next breakpoint via debuggers During this process register values memory address contents variable contents and many other useful pieces of information can be monitored Hardware Breakpoints
20. the Files view in the lower tab of the WorkSpace window Bring up blink c and led c source code by double clicking each filename Use the Windows Menu to arrange the windows or maximize minimize and resize manually as desired Press the Mixed tab at the bottom of the blink c window Notice that the assembly along with each C statement Press the Source tab to revert back to C code only B 7 4 Using Breakpoints Note the small gray circles on the sidebar beside each line of source code Single click any of these gray circles and a red dot appears The red dot represents a break point Single click the red dot to remove it or click the Remove all breakpoints icon Place a breakpoint on the following lines of code in blink c 2 DAW RR displayLED leds 8 leds 0 LED display 80 displayLED leds 0 leds 3 LED display 03 displayLED leds 3 leds 2 LED Display 32 displayLED leds 2 leds 1 LED display 21 displayLED leds 16 leds 16 LED display Click the Go icon The yellow arrow stops at the first break point and the HEX display does not change Click the Go icon again The last instruction has now been executed and an 80 is displayed Continue on in this fashion watching the lines execute only as they are called while the yellow arrow shows exactly what line is up next in execution Click the
21. 4 4 1 DRAM For DDR SDRAM Sizes and Configurations see theIntel 80332 1 0 Processor Developer s Manual This section also contains multiple examples of Address Register Programming See the Intel 80332 I O Processor Design Guide section 8 table 34 for supported DDR333 and DDR II configurations For all registers relating to DRAM and other MCU related registers see the Intel 80332 1 0 Processor Developer s Manual 4 2 Components on the Peripheral Bus The 80332 has a peripheral bus which contains the following peripheral devices e Flash ROM CPLD Audio Buzzer Rotary Switch Hex Display Peripheral memory Mapped Register Locations and all registers associated with PBI or the Peripheral Bus Interface Unit can be found in the Intel 80332 I O Processor Developer s Manual Evaluation Platform Board Manual 45 Intel IQ80332 I O Processor Software Reference n 4 2 1 Figure 12 46 Flash ROM The Flash ROM is an 8 MB Intel StrataFlash partt 28F640 that sits on the Peripheral Bus and is accessed using PCEO Flash Connection to Peripheral Bus FLASH 28F640J3A 16 bit 8 Mb Intel 80332 1 0 Processor Intel 80332 I O Processor Bus B3236 02 Under normal operation the very first instruction access by the Intel XScale core begins at location 0x0 on the 80332 Internal Bus By default address 0x0 is pointing to PCEO where flash is located Currently the Intel Flash Reco
22. 7 Table 10 Intel 1Q80332 I O Processor Hardware Reference Section Intel 1080332 I O Processor Evaluation Platform Board Peripheral Bus The 80332 populates the peripheral bus as depicted by Figure 7 Intel 1980332 I O Processor Evaluation Platform Board Peripheral Bus Topology Agilent FLASH 28F640J3C RD HDSP A103 Hex 16 bit DMT 1206 SMT Display 8 Mo Audio Buzzer Intel 80332 pey I O Processor PBI Bus 5 XILINX Grayhill SIMTEK RN HABIGW d STK14C88 3N 35 Rotary Switch ere NVSRAM The devices on the bus include Flash ROM audio buzzer CPLD HEX display NVSRAM and rotary switch Peripheral Bus Features Description The bus width can be 8 bit or 16 bit and runs at 66 MHz The bus is utilized for attaching debug and Flash devices The interfaces devices that are utilized include an audio buzzer CPLD a rotary switch a HEX Display and NVSRAM Evaluation Platform Board Manual 31 Inte IQ80332 I O Processor Hardware Reference Section 3 6 1 Flash ROM Table 11 Flash ROM Features Description Flash is an Intel StrataFlash technology Part number 28F640J3C Flash size is 8 MB The connection to the peripheral bus is depicted by Figure 8 Figure 8 Flash Connection on Peripheral Bus FLASH 28F640J3A 16 bit 8 Mb Intel 80332 y o Processor Intel 80332 I O
23. CI X Bus B speed set Closed S7A1 5 BPCI X Bus PCI X Bus B Hot Plug Reset Closed S7A1 6 BPCI X Bus Hot Plug Capable Disable Closed S7A1 7 SMBUS Bus SMBUS Manageability address bit 5 Open S7A1 8 SMBUS Bus SMBUS Manageability address bit 3 Open S7A1 9 SMBUS Bus SMBUS Manageability address bit 2 Open S7A1 10 SMBUS Bus SMBUS Manageability address bit 1 Open S8A1 CPLD Rotary Switch Position 1 Default Switch Settings of S7A1 Visual Switch S7A1 Closed Open Open Closed Closed Closed Open Open Open Open S7A1 S7A1 S7A1 S7A1 S7A1 S7A1 S7A1 S7A1 S7A1 S7A1 1 2 3 4 5 6 7 8 9 10 Default Switch Setting Switch S7A1 TM Evaluation Platform Board Manual intel 3 9 3 Table 17 3 9 4 Table 18 3 9 5 Table 19 Inte 1Q80332 I O Processor Hardware Reference Section Jumper Summary Jumper Summary Jumper Description Factory Default J1C1 JTAG Chain Enable 1 2 J1D2 Disables UART Open J7B4 SM SCLK to EEPROM SM SDTA to EEPROM 1 2 3 4 J7D1 16 bit Flash Enable Open J9D3 Buzzer Volume Open Connector Summary Connector Summary Connector Description J1D1 RJ45 Network Connector for GbE NIC J1E1 RJ11 Dual Serial Port Connector J1L1 J1M1 J1M2 J1N1 SMA connectors J2M1 J2M2 J1R1 Secondary PCI X Expansion bus Slot J2A1 Secondary PCI X Expansion bus Slot J2D1
24. EEE AE e dp e cr eu bu vee 55 Bi2 2 Software Setup occi estote eiedr e eadcstu t avesc tunes rs e dep RR ER dup xUS 56 Bo Now l eesum 57 B 3 1 Greating a New Project mere pte RH NE RR RE Ha OR Rae ROR Rx dexu exaudi c ie 57 B 3 2 GCONTIQUPATION soccer rene t p iex edv te ad P apt x revo FOR 58 Be EE EC BU 59 MEO He 59 B 4 2 Using Flash Programmer esses esent nennen nter 60 BS Debugging Out of Flash dete ite exe tette tte tte ab aici hacia 61 B 6 Building an Executable File From Example Code seseeeeenn 61 B 7 Running the Code Lab Debugger sessiyani anina n eene enemies 62 B 7 1 Launching and Configuring Debugger ssenee 62 B 7 2 Manually Loading and Executing an Application Program sss 62 B 7 3 Displaying Source Code sesbroci inon 63 B724 gt Using BreakpOintS iss dt rr etate anderen EEA 63 B 7 5 Stepping Through the Code ssssssssseeeeeen nee 64 B 7 6 Setting Code Lab Debug Options ssseseeeneeneeeneennnen nnne 64 B 8 Exploring the Code Lab Debug Windows eeeeeeneeenennm nennen 65 cs TOOL ICONS c 65 B 8 2 Workspace WindOW rientrare d nai ceu aai de Rd Rare ERR rs a A DRERR HR ERREREE 65 BOS Source GOGdO oed le eee eau e pado rv ace e p Rte na 65 B
25. Express Specification Revision 1 0 The addition of the Intel XScale core brings intelligence to the PCI Express to PCI Bridges The 80332 integrates dual PCI Express to PCI X Bridges with the ATU as an integrated secondary PCI device The Upstream PCI Express port implements the PCI to PCI Bridge programming model according to the PCI Express Specification Revision 1 0 The Primary Address Translation Unit is compliant with the PCI X Specification Revision 1 0a definitions of an application bridge For more in depth information in regards to the 80332 please see the Intel 80332 I O Processor Developer s Manual Evaluation Platform Board Manual Figure 1 Intel 80332 I O Processor Block Diagram Intel 1Q80332 I O Processor Introduction 2 channel DMA Timers Interrupt GPIO Unit Bridge Controller IOAPIC Flo XB IOAPIC pons PCle to PCI X Bridge Performance Monitoring Intel XScale 32 64 bit DDR UART 2 2C 16 bit Application Core Bus Interface Units Units PBI Accelerator Unit Interface Unit Memory Controller 2 1 GB s Internal Bus 266 MHz Message AT l A PCI X IOP Bus 133 MHz B PCI X Slot Bus 133 MHz B1240 02 Arbiter SHPC B3613 01 Evaluation Platform Board Manual 13 Intel IQ80332 I O Processor Introduction intel 1 7 Table 5 14 Intel 1980332 I O Processor Evaluation Platform Board Features Summary of Features Feature Definition
26. Flash DIP Swit 107 asa eeprom Intel eme ERROR 80332 CEO Battery f 1 0 RJ 11 s Processor PCI X Rt Angle Slot Serial port C Mounted on Back Side of PCB PCI E Y Edge 312 26 Evaluation Platform Board Manual Table 7 Note Power The 80332 draws power from the PCI Express bus The power requirements for the 80332 are shown in Table 7 below The numbers do not include the power required by a PCI X card mounted on the expansion slot Power Features Voltage Rail Typical Current Maximum Current 3 3 V TBD mA 6971 mA 5 V TBD mA 7 mA 12 V TBD mA 105 mA The maximum current was calculated but not measured This numbers do not include the power required by a PCI X card mounted on the expansion slot s Evaluation Platform Board Manual 27 Inte IQ80332 I O Processor m Hardware Reference Section l n B 3 4 3 4 1 3 4 1 1 28 Memory Subsystem The Memory Controller of 80332 controls the DDR SDRAM memory subsystem It features pro grammable chip selects and support for error correction codes ECC The memory controller can be configured for DDR SDRAM at 333 MHz and DDR II at 400 MHz The memory controller supports pipelined access and arbitration control to maximize performance The memory controller interface configuration support includes Unbuffered DIMMs Registered DIMMs and discrete DDR SDRAM devices This IQ80332 has DDR II at 400 MHz DIMM
27. Hat RedBoot software running on the 1Q80332 Intel 80332 I O Processor Memory Map Figure 13 depicts the memory space for the 80332 before RedBoot boots Intel 80332 I O Processor Memory Map ADDRESS 0000 0000H z Memoryless Boot Registers 0000 0040H ATU Outbound Direct Addressing Window 8000 0000H ATU Outbound Memory Translation Windows SUDO 0000H Code Data External Memory 9000 0000H ATU Outbound I O Translation Window 9001 0000H Code Data External Memory FFFF E000H Peripheral Memory Mapped Registers FFFF E900H I O Processor Reserved Reserved Address External Memory FFFF FFFFH Space Evaluation Platform Board Manual m Intel 1Q80332 I O Processor l n amp Software Reference 4 3 2 RedBoot Intel 80332 I O Processor Memory Map Virtual Address Physical Address Me Description 0x0000 0000 0x0000 0000 2048 SDRAM 64 bit ECC 0x8000 0000 0x8000 0000 128 ATU Outbound Memory Translation Windows 0x8800 0000 ii 128 Unused 0x9000 0000 0x9000 0000 1 ATU OUtbound I O Translation Window 0x9010 0000 P 255 Unused 0xA000 0000 0x0000 0000 512 SDRAM 64 bit ECC Uncached 0xC000 0000 0xC000 0000 8 Flash PCEO 0xC080 0000 224 Unused OxCE80 0000 OxCE80 0000 1 PCE1 Uncached OxCE90 0000 7 23 Unused 0xD000 0000 512 Unused OxF00 0000 OxF00 0000 1 Cache flush OxF010 0000 i 254 Unused PMMR Intel 80332 I O Processor Memo
28. MENT FITNESS FOR ANY PARTICULAR PURPOSE OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL SPECIFICATION OR SAMPLE Intel disclaims all liability including liability for infringement of any proprietary rights relating to use of information in this specification No license express or implied by estoppel or otherwise to any intellectual property rights is granted herein Copyright Intel Corporation 2005 AlertVIEW i960 AnyPoint AppChoice BoardWatch BunnyPeople CablePort Celeron Chips Commerce Cart CT Connect CT Media Dialogic DM3 EtherExpress ETOX FlashFile GatherRound i386 i486 iCat iCOMP Insight960 InstantlP Intel Intel logo Intel386 Intel486 Intel740 IntelDX2 IntelDX4 IntelSX2 Intel ChatPad Intel Create amp Share Intel Dot Station Intel GigaBlade Intel InBusiness Intel Inside Intel Inside logo Intel NetBurst Intel NetStructure Intel Play Intel Play logo Intel Pocket Concert Intel SingleDriver Intel SpeedStep Intel StrataFlash Intel TeamStation Intel WebOutfitter Intel Xeon Intel XScale Itanium JobAnalyst LANDesk LanRover MCS MMX MMX logo NetPort NetportExpress Optimizer logo OverDrive Paragon PC Dads PC Parents Pentium Pentium II Xeon Pentium IIl Xeon Performance at Your Command ProShare RemoteExpress Screamline Shiva SmartDie Solutions960 Sound Mark StorageExpress The Computer Inside The Journey Inside This Way In TokenExpress Trillium Vivonic and VTune are tr
29. Power header for fan J2D2 GPIO tap in Header J1 pn Test headers J2E1 Edge connector for primary PCI Express Bus J5B1 DIMM J7A1 PC104 Mod connector J7B1 J7B2 C4 pin connectors J7B3 Secondary PCI X Expansion Slot Power Please see Section 2 2 2 Power Requirements for more details J7C1 Test header empty J7D2 JTAG CPLD Header J9D1 Power header for battery General Purpose Input Output Header The following table in Section 19 J2D2 GPIO Header Definition on page 39 shows the GPIO signal assignments The GPIO signals are muxed with the serial port signals The serial port must be disabled to use the GPIO signals These pins corespond to Jumer J2D2 J2D2 GPIO Header Definition Pin Signal Pin Signal Pin Signal 1 GND GPIO5 7 GPIO2 2 GPIO7 GPIO4 GPIO1 3 GPIO6 GPIO3 9 GPIOO Evaluation Platform Board Manual 39 Inte IQ80332 I O Processor m Hardware Reference Section 3 9 6 3 9 6 1 3 9 6 2 3 9 6 3 Table 20 3 9 6 4 3 9 6 4 1 Table 21 3 9 6 4 2 Table 22 40 Detail Descriptions of Switches Jumpers Switch S1C2 80332 Reset This switch resets 80332 Switch S6A1 BPCI X Reset This switch resets the PCI X B segment bus Switch S8A1 Rotary Rotary Switch Settings Position Description 1 Factory Default Enables private devices on the secondary PCI X slot Redboot uses this setting to configure private devices Disables priva
30. Remove all breakpoints icon Press Go again and notice that the program loop is infinite Press the Halt icon to stop execution Close the debugger and cycle power to the board Evaluation Platform Board Manual 63 Intel 180332 I O Processor m Getting Started and Debugger l n B 7 5 B 7 6 Note 64 Stepping Through the Code The led c file contains a function that is called from code in blink c This exercise steps through the code and utilizes a few of the most common step tools 1 Launch the debugger open Tester LED and open the blink c and led c files 2 Set a breakpoint on the following line in blink c displayLED eds 8 leds 0 LED display 80 3 Press Go Program execution sit on the first breakpoint 4 Press the Step Over icon and notice how execution jumps over the function call to the next line of execution 5 Now try the Step Into icon and note that the pointer has now jumped into the function displayLED which is located in the led c file 6 Press the Step Over icon again and watch the pointer advance within the function to the next executable line 7 Now press the Step Out of icon and notice how execution leaves the called function and waits on the next executable line in blink c 8 The animate icon can also be used to provide a Step Into effect that occurs at a specified time interval default of 1 second This ca
31. The two pairs of Agilent HDSP A103 seven segment LEDs are used for displaying POST codes or other software generated debug codes Both HEX displays are individually addressed The left HEX display address range is CE84 0000 to CE84 FFFF in hex The right HEX display address range is CE85 0000 to CE85 FFFF in hex Please see Section 4 2 2 Peripheral Bus Memory Map on page 47 for more details Rotary Switch The 80332 provides a Rotary Switch S8A 1 for the user to select from different boot up flavors Setting 1 enables private devices on the secondary PCI X bus Setting 1 allows Redboot to configure and use devices in slot A Position 0 allows the host to see all the devices on the secondary PCI bus The default setting is position 1 Other settings are currently not validated with Redboot Other settings may be used with other software applications Please see Section 4 2 2 Peripheral Bus Memory Map on page 47 for more details on addressing the rotary switch Rotary Switch Requirements Description Rotary switch has a 4 bit resolution 16 positions The connection to the peripheral bus is depicted by Figure 7 Default setting is 1 This enables private devices on PCI X bus Position 0 allows host to see all devices on the secondary bus Evaluation Platform Board Manual 33 Inte IQ80332 I O Processor Hardware Reference Section 3 6 7 Battery Status Intel A CPLD o
32. Y is latched at the de asserting edge of P_RST and it determines when the Primary PCI interface disable PCI configuration cycles by signaling a Retry until the Configuration Cycle Retry bit is cleared in the PCI Configuration and Status Register Table 23 Switch S7A1 3 RETRY Settings and Operation Mode S7A1 3 Operation Mode Open Configuration Retry Enabled use when booting in a host Default mode Closed Configuration Retry Disabled 3 9 6 4 4 S7A1 4 PCI X Bus B Speed Enable corresponding to signal name PBI AD10 This switch allows the user to enables 133 MHz on PCI X segment B Table 24 S7A1 4 PCI X Bus B Speed Enable Settings and Operation Mode S7A1 4 Operation Mode Open Enables 133 MHz on PCI X bus B Closed Enables 100 MHz on PCI X bus B Default Mode 3 9 6 4 5 S7A1 5 PCI X Bus B Hot Plug Reset Disable corresponding to signal name PBI_AD11 This switch allows the user to enables or disable Hot Plug Reset on PCI X segment B Table 25 S7A1 5 PCI X Bus B Hot Plug Reset Disable Settings and Operation Mode S7A1 5 Operation Mode Open PCI X Bus B Hot Plug Enable normal reset mode disabled Closed PCI X Bus B Hot Plug Disable normal reset mode Default Mode 3 9 6 4 6 Switch S7A1 6 Hot Plug Capable Disabled corresponding to signal name PBI_AD15 This switch allows the user to enable hot plug devices on the secondary PCI X bus B Table 26 Switch S7A1 6
33. ademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries The ARM and ARM Powered logo marks the ARM marks are trademarks of ARM Ltd and Intel uses these marks under license from ARM Ltd Other names and brands may be claimed as the property of others 2 September 2005 Document Number 274069003US Contents ntel Intel IQ80332 I O Processor Evaluation Platform Board Manual G Contents 1 niri m M 9 1 1 Document Purpose and SCOPE serio aeeiiaii iainta aE EAA eene enhn nennen nre 9 1 2 Other Related Documents S erns AE hne enn nhnr enne teres entren 9 1 8 Electronic Information assia eaan EEE EEE nmm nennen nnne nennen rennes 10 1 4 Component Refererces uincie eicere i o eo E aee dk YR ask V as La v caeca EE dne dowd 10 1 5 Terms and Definitloris i oriunda ees ete EE tnn enean Raid e neta ens 11 1 6 Intel 80332 I O Processor ttt ttt ttt tenis 12 1 7 Intel 1Q80332 I O Processor Evaluation Platform Board Features ees 14 2 Geing Stared Ems 15 2 1 KE COMIN E 15 2 2 Hardware Installation 0 0 2 cece ceeessseeeeeeeeeeeeeeeeeaaeeeeeeeaaeeeeeeeaaeeaeeeaaeaeeeeeaaeaaeseeaaaeeeeeeeneeaeeess 15 2 2 1 First Time Installation and TeSt eee ccccceeeeeeeeeeeeeeeeeeeeeeeeeeeeeseeeeeeeseeeeeeeeeeeeeeeens 15 2 2 2 Power Requirements cc cccceceeesceceeeeeeceeeeeeeee
34. aeeeeeeaaaeeesseaaeeeeneeaaeeeeseeeaseneneas 16 2 9 Factory Settings eire petri a ae erie ha adeo ree eee oie gees 17 2 4 Development Strategy ssssssssesssseseeeeee eene nemen nne enne n nenne ennemis 17 24 1 supported Tool Buckets eek eire teet ro etre be HEP eed 17 2 4 2 Contents of the Flasher aaa EEEE N 17 2 5 Target Monitors eid de ene ent d Secr aide cbe a aeo Ee EE REDE RE 18 2 534 RedHat RedBOOL aeree eerte fee a api e De ERR Ea Ru Cap du 18 2 6 Host Communications Examples sse nnne nnne 19 2 6 1 Serial UART Communication essessssssseseeeeeeneeeeeeen nennen 19 2 6 0 JTAG Debug Communication 0 000 eee eect eee eeeee ee eee neiaa Ai R S 19 2 6 3 Network Communication essen ener enne nen 20 264 QGNUPrO GDB Insight uci roe uen ever v rete e eed cine 21 2 6 4 1 Communicating with RedBoot seseeeeee en 21 2 6 4 2 Connecting with DB iiec ecd ect ei Ren o e Rex d ek 23 3 Hardware Reference Section ssssssssssssssseeeeee eene eene nennen nnne nenne 25 3 1 afe ife ir IT To pom m 25 3 2 Board Form Factor Connectivity eese E nnn nin nnne 26 o MEE m 27 3 4 Memory SUbSySIOIm ccce dec nen cete eh coget E Due o sy ce xu ucc ev pace Eo ue Den Ga 28 341 DDR SDRAM cece 28 S442 Battery Backup ere ed tad A ER lcu e p Rt eod 28 3 4 2 Flash Memor
35. arting address of the Memory window The ATU header begins at Oxffffe100 and contains a known number 8086 Also look at the base and limit registers for the memory and Flash devices at Oxffffe508 and ffffe688 respectively since they were initialized by RedBoot Use the Intel 80332 I O Processor Developer s Manual to see what the values mean The tabs at the bottom allow the selection of two memory regions to observe Evaluation Platform Board Manual 65 Intel 180332 I O Processor m Getting Started and Debugger l n B 8 6 B 8 7 Note Note B 8 8 66 Registers Window Close all the active windows then bring up the Registers window Resize the this window and its columns to get a good view of all the registers Notice that there is a Flags tab at the bottom of this window This is useful for seeing the system flags defined by the CPSR These are important especially during conditional code execution see the ARM Architecture Reference Manual for more detail but the flags are not changed during this exercise Click on the registers tab of the registers window and click the Animate icon Notice how the register values change during program execution red values are those that were modified during the last execution cycle Click the Halt icon at any time then try right clicking a register row and selecting Go To Memory Notice how the Memory window is brought up and the address contained in that register is shown C
36. ation Mode 42 29 Switch S7A1 9 SMBUS Manageability Address Bit 2 Settings and Operation Mode 42 30 Switch S7A1 10 SMBUS Slave Address 0 Settings and Operation Mode 42 31 Jumper J7D1 Descriptions ceto redet eden arbe eatin abn eee ies 43 32 Jumper J7D1 Settings and Operation Mode ssseeeeeeeeeneeeennnneen 43 39 Jumper J1 C1 Descriptions recette eite A gen delta ences pae tenue au Dii e cu eu Ya EE 43 34 Jumper J1C1 Settings and Operation MOde ccceseceeeneeceeceeeeeeeeeeeeeaaaeaeceeeeeeeeeeeseeesenaeaaees 43 35 Jumper J1D2 Descriptions cootra tee ti eoe tides lien 43 36 Jumper J1D2 Settings and Operation Mode ssssssssssssssseseeen eene 43 3 4 Jumper J7B4 DescripltiOtis ioci de ce edt cerra tute euentu EROE bae bu eun ene tana eles 44 38 Jumper J7B4 Settings and Operation Mode ccccceceeeecceceeeeeeeeeeeeeneaacaeceeeeeeseeeeseeeennaneaeess 44 39 Jumper J9D3 Descriptions esros ni ete pr ede eter getto pa be Pant ee out 44 40 Jumper J9D3 Settings and Operation MOde ccceseceeeececceceeeeeeeeeeeeeeeaaeaeceeeeeeeeeeeseeeeenieeaeess 44 41 Peripheral Bus Memory Map eesssseeeseseeese nennen EAREN AA EA EEAS RAAS 47 42 Intel 1Q80321 Evaluation Platform Board and Intel 1280332 I O processor evaluation platform board Comparisons51 43 Related Documents ether ea ker Po RR N dndu
37. aunching the CodelLab Debugger environment and connection via the JTAG port Toolbar Icons Placing the mouse arrow on any icon displays the text function of that icon When the icon launches a special window i e Watch Memory Call Trace etc the icon brings that window up on the first click and removes the window when pressed again Workspace Window Click on the Workspace icon Click on the Files and Browse tabs and examine the contents Note that there are more files than the original source files When you double click on the source files blink c and led c the source window appears for that file When you double click on an included file the debugger is not be able to find the file Source Code The source code windows are opened by double clicking on the source files in the Workspace window under the files tab Viewing of mixed Assembly and C code or C code only is controlled by the tabs at the bottom of these windows 4 Debug and Console Windows The Debug window displays debugger activity messages while the Debug tab is displayed Script commands can be entered manually at the top of the window Serial output is displayed while the Console tab is active Commands for the running application can be entered at the top of this window Memory Window Click on the Memory window icon Change the address at the top of the window to Oxffffe100 and click on the green arrow to the right or press Enter This changes the viewable st
38. dna M OQ tA A WN KF C Disable interrupts Technically they are disabled at reset but for soft reset this is included Init PBIU Peripheral Bus Interface Unit chip selects Enable I cache Move Flash to OxF0000000 Set TTB and Enable MMU Read DIM for memory parameters Set Memory Parameters Delay Turn DDRAM on Delay Enable Data Cache Enable BTB Flush all Clear ECC error logs Battery Test Enable ECC Scrub loop Write zeros to all memory locations mov r8 r4 save DRAM size mov rO 1 mov rl 1 mov r2 1 mov r3 1 mov r4 1 mov r5 1 mov r6 1 mov r7 1 ldr rll SDRAM BASE scrub Loop stmia r11 r0 r7 subs 612 r12 3432 bne 0 Evaluation Platform Board Manual intel 1Q80321 and IQ80332 Comparisons Intel IQ80332 I O Processor 1Q80321 and IQ80332 Comparisons A This appendix provides a brief description for differences between 1Q80332 and IQ80321 Please also refer to application note Intel 80321 Software Conversion to the Intel 80332 I O Processor Application Note Table 42 Intel 1980321 Evaluation Platform Board and Intel 1980332 I O processor evaluation platform board Comparisons Features intel GB03 VO Processor Evaluation Intel 1 80321 Evaluation Platform Board Platform Board I O Processor 80332 Inte 80321 I O Processor Core Microprocessor Technology Intel XScale microarchitectur
39. e Intel XScale microarchitecture Memory Technology DDRII 400 MHz SDRAM DIMM PC1600 DDR SDRAM 100 MHz Clock Form Factor PC board that attaches to a PC Server Backplane by a PCI Express slot Two PCI X Expansion Slot Extended PC board that attaches to a PC Server Backplane One PCI X Expansion Slot PC Server Backplane Connection PCI Express PCI X 133 MHz 64 Bits or PCI 66 MHz 64 Bits Expansion Card Slot One PCI X 100 MHz 64 bits One PCI X 2 0 266 MHz 64 bit One PCI X 133 MHz 64 bit PCI PCI X Bridge PCI X to PCI X Bridge integrated with the 1Q80332l IBM PCI X Bridge Reference IBM 133 PCI X Bridge http www chips ibm com Interrupt Routing External interrupts are routed through the XINT pins on the 80332 Please see Table 9 for more details External interrupts are routed through the XINT pins on the 80321 They include INTA INTB form PCI X expansion slot INTA from 82544 GBE and UART interrupt Steering and Status registers are in 80321 see Inte 80321 I O Processor Developer s Manual Timers Internal to 80332 Refer to Inte 80332 I O Processor Developer s Manual Internal to the 80321 please refer to the Inte 80321 I O Processor Developer s Manual Local Peripheral Bus 66 MHz multiplexed bus with two chip enables Synch Asynchronous 80332 operates in 66 MHz Asynchronous mode Refer to PBI section in Intef 80332 I O Processor Devel
40. e Solution Explorer window right click Project80332 and select Save Project80332 Evaluation Platform Board Manual Intel B 4 B 4 1 Intel 180332 I O Processor Getting Started and Debugger Flashing with JTAG Overview CodelLab and Raven are capable of reading from writing to and erasing the contents of the Flash on the evaluation board The board comes with RedBoot loaded in the Flash RedBoot is the RedHat debug monitor which initializes the board and has some debug and diagnostic functions It is capable of serial communication with the console of a debug program or with Microsoft HyperTerminal and it prepares the board for accepting an application program CodelLab invokes a Flash programmer written by Macraigor More information on the Flash programmer is located at http www ocdemon net Merchant2 merchant mv Screen CTGY amp Store Code MTS amp Categ ory C odezSoftware This Flash programmer only supports certain file formats Intel Hex Motorola srec and standard elf executable and linking format RedBoot s19 and RedBoot srec are both srec files TBD i32 is an ARM BootMonitor Intel Hex file BootMonitor is an ARM version of a debug monitor which is similar but not identical to RedBoot Macraigor offers conversion tools to convert existing file types to a supported file type These conversion tools are located at C ATI codelab codelab Debug Macraigor Flash Programmer The ReadMe txt fil
41. e Intel World Wide Web WWW Location http www intel com Customer Support US and Canada 1 916 377 7000 1 4 Component References Table 3 provides additional information on the major components of 80332 Table 3 Component Reference Component Part Number Additional Information Intel Manufacturer Intel Corporation StrataFlash 28F640J3C pieles api MA Memory URL http developer intel com design flcomp prodbref 298044 htm Intel R Gigabit 82545EM Manufacturer Intel Corporation Ethernet URL http developer intel com design network products lan controllers 82545 htm Controller Manufacturer Grayhill Rotary Switch DR FC 16 URL http embrace grayhill com embrace Item ASP Item Detail asp PartNo 94HAB16W amp Catalog GroupID Series94HBinaryCoded amp GroupDisplayLabel amp RestSes No Manufacturer Agilent Technologies Hex Display HDSP A103 pL ngran a a URL http www semiconductor agilent com cgi bin morpheus home home jsp pSection LED DMT 1206 Manufacturer RDI AudioBuzzer i SMT URL http www rdi electronics com products Audio DMT 1206 SMT htm NVSRAM STK14C88 3 Manufacturer SIMTEK N 35 URL http www simtek com product information datasheets 256K PDF STK14C88 3 pdf XC9572XL Manufacturer XILINK CPLD 10TQ100C URL http www xilinx com bvdocs publications ds057 pdf Manuf National Temperature LM75CIMX
42. e describes the conversions tools BinToS19 exe converts binary files to srec files and MakelIntelHex exe converts a out files to Intel Hex files When using the BinToS19 exe conversion tool use 0x0 for the starting address For example at the CMD prompt in the directory where BinToS 19 exe is located the command line looks like this C ATI codelab codelab Debug Macraigor Flash Programmer bintos19 C temp redboot_ROM bin 0x0 c temp redboot_ROM s19 Evaluation Platform Board Manual 59 Intel 180332 I O Processor m Getting Started and Debugger l n B 4 2 Using Flash Programmer Note The parallel port must be set to EPP mode or the Macraigor Raven does not work properly Download the RedBoot executable files from the following location http developer intel com design intelxscale dev tools 021022 index htm RedBoot Debug Monitor for the IQ80332 l 11 12 13 Double click on the CodelLab Debug icon on the desktop The Connection Window appears Select Macraigor JTAG Connect a Click Setup Select ARM XScale correct LPT port and Raven do not press OK Click Additional Options check Enable Option then press Configure The Console Options windows now appears Console Port Set appropriately Baud Rate 115200 Data Bits 8 Parity None Stop Bits 1 Then Press OK OK OK this returns to the Connect window Now press Connect Assembly code now visible Select
43. e with the board Serial UART Communication CN A a Laptop computer JTAG Debug Communication Using a JTAG Emulator to communicate with the board Figure 3 Please note that the evaluation board is plugged into a host machine as in the figure below You can use an additional laptop computer but it is not necessary The host computer when loaded with the proper software can communicate with the board JTAG Debug Communication Laptop computer Evaluation Platform Board Manual 19 Intel IQ80332 I O Processor Getting Started n 2 6 3 Network Communication Using a standard network connection the user can communicate with the board via the ethernet port Redboot also allows the user to remotely boot the platform using a BOOTP server through the network Connection Figure 4 Network Communication Example 20 Evaluation Platform Board Manual Intel 2 6 4 2 6 4 1 Intel 1Q80332 I O Processor Getting Started GNUPro GDB Insight Communicating with RedBoot Hardware Setup Host with UNIX Linux or Win32 installed e 1Q80332 with serial cable RedHat RedBoot monitor Flashed to the platform board Recommended Mapping of UART Ports to Host Com Ports
44. etup and become familiar with the IQ80332 1Q80332 and other related hardware and software This appendix steps the user through an example program using CodelLab EDE CodelLab EDE debugger Macraigor Raven JTAG This programming also includes software setup compiling linking debugging example code The user tours the major features of the debugger and explores some of the basics of debugging By the end of this exercise the user has been given a general understanding of the ATI development tools and can begin working on new applications B 1 2 Necessary Hardware and Software This example uses the ATI CodelLab plug in for Microsoft Visual Studio the GNU Pro compiler the Macraigor Raven JTAG connector and the 80332 B 1 3 Related Documents Table 43 Related Documents Document Title Document Intel 80332 I O Processor Developer s Manual 273517 Inte 80200 Processor based on Inte XScale Microarchitecture Developer s Manual 273411 Hot Debug for Inte XScale Core Debug White Paper 273539 ARM Assemblers Guide http www arm com support 574FKU File ADS AssemblerGuide B pdf ADS Debug Target Guide http www arm com support 574FWT File ADS DebugTargetGuide D pdf Code Lab Debug for ARM a This document installs to C Ati docs codelab debug pdf Many of these documents load as part of ATI CodelLab install Start Programs Accelerated Technology Documentation This menu c
45. ging PPCI X Primary PCI X PSU Power Supply Unit SPCI X Secondary PCI X Evaluation Platform Board Manual 11 Intel IQ80332 I O Processor Introduction n 1 6 Intel 80332 I O Processor About the 80332 The 80332 is a multi function device that combines the Intel XScale core with intelligent peripherals and integrates two PCI Express to PCI Bridges The 80332 consolidates into a single system Intel XScale core x8 PCI Express Upstream Link Two PCI Express to PCI Bridges supporting PCI X interface on both segments PCI Standard Hot Plug Controller segment B Address Translation Unit ATU PCI to Internal Bus Application Bridge interfaced to the segment A e High Performance Memory Controller Interrupt Controller with 17 external interrupt inputs Two Direct Memory Access DMA Controller Peripheral Bus Interface PBI Unit Performance Monitor Unit PMU Application Accelerator Unit AAU Two I C Bus Interface Units BIU Two 16550 Compatible UARTS with flow control 4 pins Eight General Purpose Input Output GPIO Ports The 80332 is an integrated processor that addresses the needs of intelligent I O applications and helps reduce intelligent I O system costs PCI Express is an industry standard high performance low latency system interconnect The 80332 PCI Express upstream link is capable of x8 lane widths at 2 5 GHz operation as defined by the PCT
46. he build tool paths now appear in the box and must be modified as stated below in bold Note that the assembler and the linker are invoked by GCC a Compiler path ToolDir BIN XSCALE ELF GCC EXE b Assembler path ToolDir BIN XSCALE ELF GCC EXE c Linker path ToolDir BIN XSCALE ELF GCC EXE d Librarian path ToolDir BIN XSCALE ELF AR EXE In the left box click on Debugging General When the checkboxes are available in your version set all four debug options to false Click Apply and click OK On the main menu click codellab EDE Project Settings When the codellab Project Settings window appears click on C C Assembler in the left box Use the drop down arrow to select C compiler for Build Tool Edit the command line box at the bottom so that it contains the following v Wall specs redboot specs gdwarf 2 O0 c mcpu xscale InputRelPath o OutDir InputName OutputExt Use the drop down arrow to select Assembler for Build Tool Edit the command line box at the bottom so that it contains the following v specs redboot specs o OutDir InputName OutputExt InputRelPath In the left box click on Linker Edit the command line box at the bottom so that it contains the following v specs redboot specs o OutDir ProjectName elf ObjectFiles Libraries Click Apply and then click OK In th
47. ined Debugging with source code allows the user to examine the C code that is being executed This requires that the source code is available and linked by the debugger to the executable code that is running on the evaluation board Building an Executable File From Example Code 1 Launch CodelLab EDE and open Project80332 2 Select codellab EDE Rebuild Project A project can have more than one solution but in this example there is only one solution for the project so there is no difference between Build Project and Build Solution in this example Rebuild cleans and builds Clean deletes the old o files in the project and build compiles links and produces the executable files 3 When there are errors carefully go back through Section B 3 2 Configuration Evaluation Platform Board Manual 61 Intel 180332 I O Processor m Getting Started and Debugger l n z B 7 Running the Code Lab Debugger This section is provided to get the system up and running in the CodelLab Debug environment but it is not intended as a full functional tutorial Please refer to the ATI CodelLab Debug Reference Manual for more detailed information B 7 1 Launching and Configuring Debugger 1 In EDE click on the icon that looks like a red bug The Connect window appears 2 When not configured from Section B 4 2 Using Flash Programmer go to Section B 4 2 and perform steps 2 5 3 Press Connect to enter debug mode
48. intel Intel 1980332 I O Processor Evaluation Platform Board Manual September 2005 Document Number 274069003US Intel IQ80332 I O Processor Evaluation Platform Board Manual INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL amp PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them Intel internal code names are subject to change THIS SPECIFICATION THE Intel Q80332 I O Processor IS PROVIDED AS IS WITH NO WARRANTIES WHATSOEVER INCLUDING ANY WARRANTY OF MERCHANTABILITY NONINFRINGE
49. ironment It can be used for both product development debug support and for end product deployment Flash and network booting Here are some highlights of RedBoot capabilities Boot scripting support Simple command line interface for RedBoot configuration and management accessible via serial terminal or Ethernet telnet see Section 2 6 4 GNUPro GDB Insight on page 21 Integrated GDB stubs for connection to a host based debugger GBD Insight via serial or Ethernet Ethernet connectivity is limited to local network only Attribute Configuration user control of aspects such as system time and date when applicable default Flash image to boot from default fail safe image static IP address etc Configurable and extensible specifically adapted to the target environment Network bootstrap support including setup and download via BOOTP DHCP and TFTP X Y Modem support for image download via serial Power On Self Test Evaluation Platform Board Manual 2 6 1 Figure 2 2 6 2 Figure 3 Intel 1Q80332 I O Processor Getting Started Host Communications Examples How to communicate to the host Serial UART Communication Using a serial connection to communicate with the board Figure 2 Please note that the evlaution board is plugged into a host machine as in the figure below You can use an additional laptop computer but it is not necessary The host computer when loaded with the proper software can communicat
50. l seeeeeeees 44 4 Software Referencoe secedere sen tec kae dana c EXE Sunc Ee oed Enn ea dan ate E dug se ER A 45 4i CUR 45 4 2 Components on the Peripheral Bus ssssssssseeeeeene eene nennen nnns 45 42 1 Fash ROM e 46 4 2 2 Peripheral Bus Memory Map ssssessssseeseeeeeeneneen nemen enne nn nnmis 47 4 3 Board Support Package BSP Examples sse enne 48 4 3 1 Intel 80332 I O Processor Memory Map 48 4 3 2 RedBoot Intel 80332 I O Processor Memory Map e 49 4 3 3 RedBoot Intel 80332 I O Processor Files sssssse 49 4 3 4 RedBoot 80332 DDR Memory Initialization Sequence eseesse 50 A 1280321 and 1Q80332 Comparisons sse nennen 51 4 September 2005 Document Number 274069003US Contents tel Intel IQ80332 I O Processor Evaluation Platform Board Manual G B Getting Started and Debugger sssssssssssssssee ener nnne nen 53 mice c 53 Bled PURDOSG M 53 B 1 2 Necessary Hardware and Software sssssssssssseeeeeeeennn nenne 53 B 1 3 Related DOCUMENIS eite EEE 53 B 1 4 Related Web Sites i eet de so Re Ibex ex ee VE Ya adn 54 Be S5ellpucbssssudeide iM DIL LII E di MM 55 B 2 4 Hardware Setup eere e Gad S E
51. l Q80332 I O Processor Evaluation Platform Board Peripheral Bus Topology 31 Flash Connection on Peripheral Bus ssis eE a 32 JTAG deadupio mE 36 RESET SOUC GE mt 37 Default Switch Setting Switch STAI o oo eee cece cee eeeeeaeeeeeeeeaeeeeeeeaaaeeeeeeeaaeeeeeneaaaeeeseseaaeeeeeneaaas 38 Flash Connection to Peripheral BUS isrener E iA nennen emnes 46 Intel 80332 I O Processor Memory Map tnter 48 Intel 80332 I O Processor Hardware Setup Flow Chart sssss 55 Software FlOW Diagram usce eterne dn AEAEE ud genet eed ete E xe eee cs 56 September 2005 Document Number 274069003US Contents ntel Intel IQ80332 I O Processor Evaluation Platform Board Manual G Examples 1 Intel 80332 I O Processor Related Documentation List 9 2 Electronic InformatiOr uscu ret O ERES ERR u Nar a DM RRRXR RR D MD RER RR EERE 10 3 Component RECON CO sessi eerte eth rote ete enne oe gae rcu ade nb e aab ero eda eed pud 10 Terms amd DegiImtlom rm 11 5 DUMAN OFF OOS aute r Sandee Danse us vs patur aed HUE ENTE EAEE 14 6 Form Factor Connectivity Features sssssessseseeeneeneeeeen n nennen enne nnns 26 Power Features ee texere edge tee ada EE dde te sel eatin tebe ave ou 27 8 Flash Memory Requirements eeeeseesssisseeeeeseeennne ene tnne nnne n tnnt sten trn estne nnn nennen nnns 29 9 External Interrupt Routing to Intel 80332 I O Processor
52. lick on the registers tab Red means that the register value changed since the last fetch as opposed to black which represents no change Register values can be manually changed in this window Watch Window It is often useful during the debugging process to keep an eye on a few select program variables 1 Open the Tester LED Program and bring up led c 2 Click the Watch icon to bring up the Watch window 3 Now add the left and right variables from led c to the watch window For each variable double click the variable name to highlight it then drag it to the watch window 4 Click the Animate icon and observe the changes When focus goes back to the Assembly window during this process try putting a breakpoint in led c then hit Go Variables Window The Variables behaves very similarly to the Watch window except that it shows all active variables Bring up the Variables window click Animate and watch the changes Evaluation Platform Board Manual Intel B 9 B 9 1 B 9 2 B 9 2 1 B 9 2 2 Debugging Basics Overview Debuggers allow developers to interrogate application code by allowing program flow control data observation and data manipulation The flow control functions include the ability to single step through the code step into functions step over functions and run to breakpoint hardware or software The data observation and manipulation functions include access to memory
53. lkex cil emu is eu Rad gg 53 Document Number 274069003US September 2005 7 Intel IQ80332 I O Processor Evaluation Platform Board Manual n Contents Revision History Date Revision Description In Section 3 6 6 Rotary Switch on page 33 and Table 12 08 September 2005 003 Rotary Switch Requirements on page 33 changed Rotary Switch settings 1 and 0 Factory Default is now 1 in Table 20 Rotary Switch Settings on page 40 reverswd 19July 2005 nde Rotary Switch settings 0 and 1 Factory Default is now 1 27 September 2004 001 Initial Release September 2005 Document Number 274069003US intel Introduction 1 1 Document Purpose and Scope This document describes the Intel 1Q80332 I O processor evaluation platform board 1Q80332 using DDR II 400 MHz SDRAM The Intel 80332 I O processor 80332 is intended for rapid intelligent I O development The 80332 is a multi function device that integrates the Intel XScale core ARM architecture compliant with intelligent peripherals including a PCI Express bus application bridge 1 2 Other Related Documents Table 1 Intel 80332 I O Processor Related Documentation List Document Number Inte 80332 I O Processor Developer s Manual 274065 Inte 80332 I O Processor Datasheet 274066 Inte 80332 I O Processor Design Guide 273824 Inte 80332 I O Processor Specification Update 273927 Inte 80332 I O Processor JTAG Support White Pa
54. n be modified in the Settings section of the View Options menu Experiment with this as desired 9 Use Halt to stop the animate mode before the next breakpoint 10 Also note that Go can be pressed at any time to continue execution from the current line to the next breakpoint or program end Setting Code Lab Debug Options Besides the Animate debug time interval setting briefly mentioned in step 8 of the previous exercise many useful options can be accessed from the View Options menu 1 Experiment here by bringing up the Registers window click and change the view options between binary and decimal for example Hint Settings tab Interface Radix 2 Also try bringing up the Memory window click and change the number of columns between 4 and 2 and notice the changes Hint Settings tab Memory Window Number of Columns Press window icons a second time to remove them from view Again there are many features of the debug environment not discussed here Please see the CodelLab manuals for a full description of debug features Evaluation Platform Board Manual B 8 1 B 8 2 B 8 3 B 8 4 B 8 5 Note Exploring the Code Lab Debug Windows This section discusses some basics of the debug environment Some of these windows and concepts have been dealt with during previous exercises in this manual However many new windows are also discussed and basic interaction exercises are given Begin this section by l
55. n the IQ80332 provides the following status for the battery Please see Section 4 2 2 Peripheral Bus Memory Map on page 47 for more details on addressing the CPLD Table 13 Battery Status Buffer Requirements Read dcc BIT Write Name Description 0 2 No backup batter 0 R Battery Present i i 1 Battery backup is present 0 Battery is not fully charged 1 R Battery Charged d g 1 Battery is fully charged 0 Battery backup is not fully discharged 2 R Battery Discharged Pe q 1 Battery backup is fully discharged 0 Disable battery backup 3 R W Battery Enable d 1 Enable battery backup 4 7 d Reserved Undefined 34 Evaluation Platform Board Manual In 3 7 3 7 1 Intel IQ80332 I O Processor Hardware Reference Section Debug Interface Console Serial Port The platform has two serial ports for debug purposes as described in Section 3 6 Intel 1080332 I O Processor Evaluation Platform Board Peripheral Bus on page 31 Evaluation Platform Board Manual 35 Intel 1Q80332 I O Processor Hardware Reference Section 3 7 2 3 7 2 1 Figure 9 36 JTAG Debug The 80332 has a 20 pin JTAG connector J7D2 that is in compliant with ARM Multi ICE guidelines JTAG Port JTAG Port Pin out VTref Vsupply nTRST GND TDI GND TMS GND TCK GND RTCK GND TDO GND nSRST GND DBGRQ GND DBGACK GND A9457 01 Evaluation Platform Board Manual
56. nageablity Address Bit 2 1 Default Mode Closed SMBus Manageablity Address Bit 2 0 Switch S7A1 10 SMBUS Manageability Address Bit 1 corresponding to signal name PBI AD16 This allows 80332 to address SMBus Slave Address 1 PBI A16 Switch S7A1 10 SMBUS Slave Address 0 Settings and Operation Mode S7A1 10 Operation Mode Open SMBus Manageablity Address Bit 1 1 Default Mode Closed SMBus Manageablity Address Bit 1 0 Evaluation Platform Board Manual Inte IQ80332 I O Processor l ntel Hardware Reference Section 3 9 6 5 Jumper J7D1 Flash bit width The Intel 1Q80332 I O processor evaluation platform board expects an 8 bit Flash enable Table 31 Jumper J7D1 Descriptions Jumper Description Factory Default J7D1 8 bit Flash Enable Open Table 32 Jumper J7D1 Settings and Operation Mode Pins Operation Mode 1 2 Enables 16 bit Flash NC 8 bit Flash default mode 3 9 6 6 Jumper J1C1 JTAG Chain Table 33 Jumper J1C1 Descriptions Jumper Description Factory Default J1C1 JTAG Chain Enable 1 2 Table 34 Jumper J1C1 Settings and Operation Mode J1C1 Operation Mode Pins 1 2 Enables JTAG Chain for IOP only Default Mode Pins 3 4 Enables JTAG Chain for IOP CPLD Pins 5 6 Enables JTAG Chain for IOP CPLD GBE Pins 7 8 Enables TRST pull down resistor 3 9 6 7 Jum
57. on the board The memory subsystem of the evaluation board consists of the SDRAM as well as the Flash memory subsystems DDR SDRAM The DDR SDRAM interface consists of a 64 bit wide data path to support up to 3 2 Gbytes sec throughput An 8 bit Error Correction Code ECC is stored into the DDRII SDRAM array along with the data and is checked when the data is read The IQ80332 features on board registered DDRII 400 MHz SDRAM arranged 512 Mbit x16 in density 256 MB and with ECC Battery Backup Battery backup is provided to save any information in DDR during a power failure The evaluation board contains a 4V Li ion battery a charging circuit and a regulator circuit DDRII technology provides enabling data preservation through the self refresh command When the processor receives an active Primary PCI X reset the self refresh command issues driving SCKE signals low Upon seeing this condition the board logic circuit holds SCKE low before the processor loses power Batteries maintain power to DDRII and logic to ensure self refresh mode When the circuit detects PRST returning to inactive state the circuit releases the hold on SCKE Removing the battery can disable the battery circuit When the battery remains in the platform when it is de powered and or removed from the chassis the battery maintains DDRII for about four hours Once power is reapplied the battery is fully charged The CPLD contains information in regards to the batter
58. ontains both the ARM ADS and CodelLab documents Evaluation Platform Board Manual 53 Intel IQ80332 I O Processor Getting Started and Debugger n s B 1 4 Related Web Sites Macraigor http www ocdemon net http developer intel com design intelxscale dev_tools 021022 index htm http developer intel com design iio http developer intel com design iio papers 273961 htm 54 Evaluation Platform Board Manual Intel B 2 B 2 1 Note Note Figure 14 Intel 180332 I O Processor Getting Started and Debugger Setup Hardware Setup Use Figure 14 and the rest of the Intel 80332 I O Processor Evaluation Platform Board Manual to set up the hardware Connect the Raven to the host via the parallel port and to the evaluation board via the 20 pin JTAG connector The parallel port must be configured to EPP mode for the Macraigor Raven to work properly The parallel port setting can be changed in the BIOS setup program or in Control Panel More information on the Raven can be found at the Macraigor web site Test software for the Raven is free and available for download at http www ocdemon net Merchant2 merchant mv Screen CTGY amp Store CodezMTS amp Category C ode pinouts Connect a serial cable from the evaluation board to the host The serial cable connects to the evaluation board with an RJ11 connector and connects to the host computer serial port via an RJ11 to DB9F adapt
59. oper s Manual 2 bit 33 100MHz multiplexed bus with six chip enables Synch Asynchronous IQ80321 operates in 33 MHz Asynchronous mode Refer to PBI section in the I nte 80321 I O Processor Developer s Manual Flash Memory 8 bit or 16 bit 8 MB accessed through Peripheral Bus with chip enable 0 PCEO 16 bit 8 MB accessed through Peripheral Bus with chip enable 0 PCEO Serial Debug Port Two UARTs integrated within the 80332 One UART on the Peripheral bus 16C550 device Network Debug Port Intel 82545EM GbE on the 100 MHz PCI X bus Intel amp 82544 GbE on the PCI X bus Rotary Switch Same Same LED HEX Display Same Same JTAG 20 PIN ARM Compliant 20 PIN ARM Compliant Logic Analyzer Connection Through PCI X or PCI Express Various Mictors Evaluation Platform Board Manual 51 Intel 1Q80332 I O Processor m 1Q80321 and IQ80332 Comparisons l n This Page Left Intentionally Blank 52 Evaluation Platform Board Manual intel Goting ST and Detugen Getting Started and Debugger B B 1 Introduction This appendix pertains to CodelLab version 2 3 and later which uses Microsoft s Visual Studio NET For CodelLab version 2 2 and earlier refer to appendix B For more detailed information on JTAG and the 80332 please see the Intel 80332 I O Processor JTAG Support White Paper B 1 1 Purpose The purpose of this appendix is to help the user s
60. or The serial port configuration is covered in the configuration section below The 80332 plugs into a bus master PCI Express slot on the backplane or platform Intel 80332 I O Processor Hardware Setup Flow Chart Host ed JTAG Evaluation Board Backplane or PCI X Platform Parallel Port Cable Serial Cable 20 Pin JTAG Connector Evaluation Platform Board Manual 55 Intel 1Q80332 I O Processor Getting Started and Debugger B 2 2 Note Figure 15 56 Software Setup intel ATI CodelLab is a plug in to Microsoft Visual Studio NET therefore Microsoft Visual Studio NET must already be loaded on the system To load ATI CodelLab run setup exe under the program directory Do not install over an old version of ATI CodelLab When necessary uninstall CodelLab with Add Remove programs under the Control Panel before reinstalling To view the soft copies of document Adobe Acrobat Reader is needed The latest version can be downloaded at http www adobe com Software Flow Diagram Debug Monitor Code Resides in the Flash ATI Code Lab Macraigor DLL Application Code Loads into Memory Flash Evaluation Board Memory Evaluation Platform Board Manual n Intel IQ80332 I O Processor l n R Getting Started and Debugger B 3 New Project Setup B 3 1 Creating a New Projec
61. per 273963 Inte 80332 I O Processor Product Brief 302746 Inte 80321 Software Conversion to the Inte 80332 I O Processor Application Note 273890 Inte Flash Recovery Utility FRU Reference Manual 274071 IEEE Standard Test Access Port and Boundary Scan Architecture IEEE JTAG 1149 1 1990 http www ieee org PCI Local Bus Specification Revision 2 3 PCI Special Interest Group PCI Express Specification Revision 1 0a PCI Special Interest Group PCI Express Base Specification 1 0a PCI Special Interest Group PCI Express Card Electromechanical Specification 1 0a PCI Special Interest Group PCI Local Bus Specification Revision 2 3 PCI Special Interest Group PCI X Specification Revision 1 0b PCI Special Interest Group PCI Bus Power Management Interface Specification Revision 1 1 PCI Special Interest Group PCI Bus Hot Plug Specification Revision 1 1 PCI Special Interest Group http www pcisig com specifications Intel documentation is available from the local Intel Sales Representative or Intel Literature Sales To obtain Intel literature write to or call Intel Corporation Literature Sales P O Box 5937 Denver CO 80217 9808 1 800 548 4725 or visit the Intel website at http www intel com Evaluation Platform Board Manual Intel IQ80332 I O Processor Introduction 1 3 Table 2 Electronic Information Electronic Information Support Type Location Contact Th
62. per J1D2 UART Control Table 35 Jumper J1D2 Descriptions Jumper Description Factory Default J1D2 UART Control Open Table 36 Jumper J1D2 Settings and Operation Mode J1D2 Operation Mode Pins 1 2 Disables UART RS 232 port NC Enables UART RS 232 port Default Mode Evaluation Platform Board Manual 43 Intel IQ80332 I O Processor Hardware Reference Section 3 9 6 8 Table 37 Table 38 3 9 6 9 Table 39 Table 40 44 Jumper J7B4 SMBus Header Jumper J7B4 Descriptions Jumper Description Factory Default J7B4 SMBus Header 1 2 3 4 Jumper J7B4 Settings and Operation Mode J7B4 Operation Mode Pins 1 2 Connects SM_SCLK to EEPROM U7B2 Default Mode Pins 3 4 Connects SM_SDTA to EEPROM U7B2 Default Mode Pins 5 6 Connects SM_SCLK to GE SMCLK for GBE control Pins 7 8 Connects SM_SDTA to GE_SMDAT for GBE control r Pins 9 10 Connects SM_SCLK to PE SMCLK for PCI E bus control Pins 11 12 Connects SM SDTA to PE SM SDAT for PCI E bus control Jumper J9D3 Buzzer Volume Control Jumper J9D3 Descriptions Jumper Description Factory Default J9D3 Buzzer Volume Open Jumper J9D3 Settings and Operation Mode J9D3 Operation Mode Pins 2 3 Buzzer Volume Soft Pins 1 2 Buzzer Volume Loud NC Buzzer Volume Off Evaluation Platform Board Manual intel aaa rh ia Software Reference
63. ry Mapped OxFFFO 0000 OxFFFO 0000 1 Registers Please see Chapter 17 of the Inte 80332 I O Processor Developer s Manual for more details 4 3 3 RedBoot Intel 80332 I O Processor Files Attached in the kit find a copy of the RedHat eCos for IQ80332 CD Once the CD is installed you may find The RedBoot initialization code source files from the following location From the installed directory RedHat eCos packages hal arm xscale iq80332 current include The RedBoot binary image files downloadable onto Flash from the following location From the installed directory RedHat eCos loaders iq80332 To access RedHat GNUPro tools including RedBoot binaries and source code you may also go to the following location on the Intel site http developer intel com design intelxscale dev_tools 021022 index htm Evaluation Platform Board Manual 49 Intel IQ80332 I O Processor Software Reference 4 3 4 50 intel RedBoot 80332 DDR Memory Initialization Sequence In order to set the correct ECC bits a DDR memory system DIMM or discrete components must be written to with a known value This process requires 64 bit writes to the entire DDR memory intended for use The following explains the sequence for memory initialization by RedBoot on an 80332 board with an ECC DIMM It also includes an example for the scrub ECC initialization code Initialization Sequence 1 O ont ON tn A t N ee e e e e e
64. t 1 Launch CodelLab EDE for NET 2 On the Start Page select New Project a The New Projects window appears b Select CodelLab Projects under Project Types and name the project Project80332 in the name field Note The directory Project80332 is created under the path specified in the Location box c Click OK 3 In the CodelLab EDE Project Wizard Window a Select RedHat GNU Tools for XScale under Build Toolset b Select 80332 under Project Template c Select Application under Project Type d Click Finish 4 Close the Start Page by clicking on the X in the top right corner of the Start Page window 5 The new project is now in the Solution Explorer window When this window is not open open it by View Solution Explorer 6 Right click on Project80332 and select Save Project80332 7 From http developer intel com design iio swsup Testerl LED htm download the following zip file Testerl LED from the Software Support section containing the example code files to the newly created project folder Tester LED zip blink c blink h led c led h These files can be placed in any directory on the hard drive 8 Add the newly downloaded files to the project a In the Solution Explorer window right click on Project80332 and select Add Add Existing Item b In the Add Existing Item window use the drop down
65. te devices on the secondary PCI X slot This setting allows the host to see all y the devices on the secondary PCI bus These settings are meaningless to Redboot Other applications may use these settings for er configuration or software utilization For more information please see Section 3 6 6 Rotary Switch on page 33 Switch S7A1 This 10 pin switch that allows the user to enable or disable various features Please see specifics below S7A1 1 PCI X Bus A Speed Enable corresponding to signal name PBI AD3 This switch allows the user to force the PCI X bus A to run at 133 MHz or 100 MHz S7A1 1 PCI X Bus A Speed Enable S7A1 1 Operation Mode Open Enables 133 MHz on PCI X bus A Closed Enables 100 MHz on PCI X bus A Default Mode S7A1 2 Reset IOP core corresponding to signal name PBI AD5 RESET MODE is latched at the de asserting edge of P_RST and it determines when the 80332 is held in reset until the Intel XScale core Reset bit is cleared in the PCI Configuration and Status Register Switch S7A1 2 Reset IOP Settings and Operation Mode S7A1 2 Operation Mode Open Don t hold in reset enable IOP core Default mode Closed Hold IOP core in reset Evaluation Platform Board Manual m Intel 1Q80332 I O Processor l n Hardware Reference Section 3 9 6 4 3 S7A1 3 Configration Cycle Enable corresponding to signal name PBI AD6 Configuration Cycle Enable or RETR
66. very Utility FRU cannot be used with the IQ80332 An alternative to FRU would be to reprogram the flash through JTAG or using Redboot commands when Redboot is currently loaded onto the board For more information on using Redboot to program the flash please see Redboot Manual Evaluation Platform Board Manual Intel 1Q80332 I O Processor l n amp Software Reference 4 2 2 Peripheral Bus Memory Map The Table 41 is the physical memory map of the devices on the 80332 Peripheral Bus Table 41 Peripheral Bus Memory Map Address Range in Hex Size Data Bus Width Description C000 0000 CO7F FFFF 8 MB 8 bit or 16 bit Flash memory re mapped CE80 0000 CE80 FFFF 64 KB 8 bit Product Code CE81 0000 CE81 FFFF 64 KB 8 bit Board Stepping CE24 0000 CE82 FFFF 64 KB 8 bit CPLD Firmware Revision CE83 0000 CE83 FFFF 64 KB 8 bit Discrete LEDs CE84 0000 CE84 FFFF 64 KB 8 bit Hex Display Left CE85 0000 CE85 FFFF 64 KB 8 bit Hex Display Right CE86 0000 CE86 FFFF 64 KB 8 bit Buzzer Control CE87 0000 CE87 FFFF 64 KB 8 bit 32KB NV RAM CE8D 0000 CE8D FFFF 64 KB 8 bit Rotary Switch CE8E 0000 CE8E FFFF 64 KB 8 bit ESN I O CE8F 0000 CE8F FFFF 64 KB 8 bit Battery Status Evaluation Platform Board Manual 47 Inte IQ80332 I O Processor m Software Reference l n 4 3 4 3 1 Figure 13 48 Board Support Package BSP Examples Examples provided in this section are based on the Red
67. y Requirements sesssssessseeeneeneeeeeneenenen nennen 29 3 5 Jnt rr pt ROUNO siete ls teo eee eoe rete en cun eve ee obe tte Pu Res reo usen eu E ENE ORE 30 3 6 Intel 1Q80332 I O Processor Evaluation Platform Board Peripheral Bus 31 261 Flasi ROM E EET 32 KRAMER 33 3 6 3 Nop volile BAM iet ture bete ceo ee etx tete rine edhe e eue ps 33 3 6 4 Audio BUZO etit oper ERR din O 33 3 0 5 HEX DISHA Y eai a Poet erp Ee ete pee ev Cedo rete ic Ert tenue utut 33 3 6 6 Rotary SWIICIH iie ederent rer eee anssibar cua Rue Cra cpu aux A ME ERU 33 367 Battery Status iue ine este aa deste Dev eps nueces Coe dg 34 PEE D TS Es 35 Document Number 274069003US September 2005 3 Contents l n Intel IQ80332 I O Processor Evaluation Platform Board Manual tel 3 7 1 GConsole Serial Por Leite ccce ceti dee AE EEA 35 3de JTAG DEDU MER 36 WE JTAG POl E 36 3 8 Board Reset Sheme ecceruen Ea E aN 37 3 9 Switches and Jump ers eee r T ANE EE AE EAEE EEE 38 391 E enum E 38 3 9 2 Default Switch Settings of S7A1 Visual 38 3 9 3 Jumper Summary arosine eee e eee eeeeeee RAEAN AAEE E ENEAN 39 394 Connector Sumlimary icit lasted use Edu e EE ane dE Ee tetur EE Eng cenae 39 3 9 5 General Purpose Input Output Header sssssssssssseeeeeene 39 3 9 6 Detail Descriptions of Switches Jumpers
68. y status Please see Section 3 6 7 Battery Status on page 34 for more details Evaluation Platform Board Manual m Intel 1Q80332 I O Processor l n Hardware Reference Section 3 4 2 Flash Memory Requirements Total Flash memory size is 8 MB Table 8 Flash Memory Requirements Description 1Q80332 Total Flash size is 8 MB 80332 Flash technology is based on Intel StrataFlash family 80332 Flash uses a 16 bit interface 80332 Flash utilizes the 80332 Peripheral Bus 80332 May be programmed using the PCI X interface Flash Recovery Utility FRU Utility 80332 May be programmed using a RAM based software target monitor RedHat RedBoot and ARM Firmware Suite 80332 May be programmed using a JTAG emulation debug device Evaluation Platform Board Manual 29 Inte IQ80332 I O Processor Hardware Reference Section 3 5 Table 9 30 Interrupt Routing The 80332 Interrupt routing External Interrupt Routing to Intel 80332 I O Processor Interrupt System Resource HPI Temperature Sensor Header S_INTA PCI X Slot INTB Header S_INTB PCI X Slot INTC Header S_INTC PCI X Slot INTD Header S_INTD PCI X Slot INTA Header P_INTA PCI X Card Edge INTA Header P_INTB PCI X Card Edge INTB Header P_INTC PCI X Card Edge INTC Header P_INTD PCI X Card Edge INTD Header Evaluation Platform Board Manual intel 3 6 Figure

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