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Intel 815E User's Manual

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1. PCI Interface H W Status Monitoring ITE IT8888F PCI Bus PCI Bus LAN2 Proprietary PCI Interface RJ 45 ISA Bus ISA Bus The following sections provide detail information about the functions provided onboard 6 ECB 865 User s Manual ECB 865 2 3 1 82815 GMCH and 82801BA The Intel 815 chipset for use with the universal socket 370 is a high flexibility chipset designed to extend from the basic graphics multimedia PC platform up to the mainstream performance desktop platform The chipset consists of the Intel_ 82815 Graphics and Memory Controller Hub GMCH and an I O Controller Hub ICH or ICH2 for the I O subsystem The GMCH integrates a system memory SDRAM controller that supports a 64 bit 100 133 MHz SDRAM array The Intel 82815 GMCH integrates a Display Cache SDRAM controller that supports a 32 bit 133 MHz SDRAM array for enhanced integrated 2D and 3D graphics performance Multiplexed with the display cache interface is an AGP controller interface to enable graphics configuration and upgrade flexibility with the Intel 815 chipset for use with the universal socket 370 The AGP interface and the internal graphics device are mutually exclusive When the AGP port is populated with an AGP graphics card the integrated graphics is disabled thus the display cache interface is not needed The Intel 815 chipset for use with the universal socket 370 support
2. Display Properties 2 Ux Background Screen Saver Appearance Plus Settings Color Palette Desktop Area 16 Colors Less More 640 by 480 pixels Font Size Refresh Frequency smal Fonts z use hardware default settinc x DmAlModer Tom 7 _DiohyTyve _ e os 84 ECB 865 User s Manual ECB 865 3 Click the Display Type button and the following window should appear Click the Change button to select another driver Display Type 4 Click the Have Disk button Change Display 5 The directory for the drivers may now be entered Type A WINNT40 as shown below Insert the Display driver disk and click OK Install From Disk ECB 865 User s Manual 85 User s Manual 6 The display driver should now be listed as shown below Click OK to accept Change Display m 7 Since this driver is not part of the NT4 0 package the following message will be shown Third party Drivers 2 8 To proceed the driver installation click the Yes button The driver will now be installed and the following message should be shown shortly Installing Driver G 9 Click OK and close the Display Type and Display Properties windows by clicking the Close button in each window 10 After closing the Display Properties window the computer must be restarted for the changes to take effect
3. 8 ECB 865 User s Manual ECB 865 2 3 4 PCI Interface The ICH2 PCI interface provides a 33 MHz Rev 2 2 compliant implementation All PCI signals are 5V tolerant except PME The ICH2 integrates a PCI arbiter that supports up to six external PCI bus masters in addition to the internal ICH2 requests 2 3 5 IDE Interface Bus Master Capability and Synchronous DMA Mode The fast IDE interface supports up to four IDE devices providing an interface for IDE hard disks and CD ROMs Each IDE device can have independent timings The IDE interface supports PIO IDE transfers up to 14 Mbytes sec and Bus Master IDE transfers up 100 Mbytes sec It does not consume any ISA DMA resources The IDE interface integrates 16x32 bit buffers for optimal transfers The ICH2 s IDE system contains two independent IDE signal channels They can be electrically isolated independently They can be configured to the standard primary and secondary channels four devices There are integrated series resistors on the data and control lines Access to these controllers is provided by two standard IDC 40 pin connectors 2 3 6 USB The USB controller provides enhanced support for the Universal Host Controller Interface UHCI This includes support that allows legacy software to use a USB based keyboard and mouse The ICH2 is USB Revision 1 1 compliant The ICH2 contains two USB Host Controllers Each Host Controller includes a root hub with two separate USB ports each
4. WV g E Lg aal ng Open Closed Closed 2 4 The jumper settings are schematically depicted in this manual as follows Open Closed Closed 2 3 A pair of needle nose pliers may be helpful when working with jumpers If you have any doubts about the best hardware configuration for your application contact your local distributor or sales representative before you make any changes 20 ECB 865 User s Manual ECB 865 3 10 1 Clear CMOS JP9 You can use JP9 to clear the CMOS data if necessary To reset the CMOS data short JP1 for just a few seconds and then remove the jumper back to open Clear CMOS JP1 Protect Clear CMOS 1 2 1 2 d QO ee default 3 10 2 Watchdog Timer 3 10 2 1 Enable Disable Onboard Watchdog Timer JP12 You can use JP12 to enable disable the onboard Watchdog timer function if necessary To disable the onboard Watchdog timer function short JP12 to enable the function of Watchdog timer set JP12 to open Enable Disable Onboard Watchdog Timer JP12 Enable Disable 12 12 pre OO C default 3 10 2 2 Watchdog Timer Programming I O Address Select JP6 You can set JP6 to select the Watchdog timer programming I O address The choice is 0553H 0033H and 0543H 0343H Watchdog Timer Programming I O Address Select JP6 0553H 0033H 0543H 0343H 1 2 1 2 JEG OO ee default ECB 865 User s Manual 21 User s Manual 3 10 2 3 Watchdog Timer Time Out Interval Select JP10
5. You can set JP10 to select the Watchdog timer time out interval to be 0 5 1 2 4 8 16 32 or 64 Sec Watchdog Timer Tim Out Interval Select JP10 2 Sec 0 5 Sec 1 Sec 135 135 i LR a OR Bi dii e 246 246 JP10 8 Sec 16 Sec 135 135 dii id NO SBS 24 Odo 246 246 default 135 291 246 32 Sec 135 7 246 3 10 3 COM2 RS 232 422 485 Select JP1 JP2 JP5 The ECB 865 COM2 serial port can be selected as RS 232 RS 422 or RS 485 by setting JP1 amp JP2 JP5 COM2 RS 232 422 485 Select JP1 JP2 JP5 RS 232 246 Jere JP1 OO 135 JP2 1 90 5 JP3 1 Z2 3 JP4 1 3 JP5 1 O 3 default h d RS 422 246 oo ads 135 OOOO bo bh NP IP IS JOO e00 Ow Ww wo 4 Sec 135 008 246 P RS 485 N A o O O0 eo OOOO ll wr ww T Ow Ww CQ E 22 ECB 865 User s Manual ECB 865 3 10 4 M Systems DiskOnChip Memory Address Select JP11 The M systems DiskOnChip memory address can be selected by JP11 The choice is D0000 D1FFF D2000 D3FFF D4000 D5FFF D6000 D7FFF M systems DiskOnChip Memory Address Select JP11 D0000 D2000 D4000 D6000 246 8 246 8 246 8 246 8 COO O oo OOMO COO JP11 eel e ee CON Sect 135 7 1357 1357 1357 default 3 10 5 Proprietary PCI Bus Master Selection JP13 The Proprietary PCI Bus Master is selected by JP13 The choice is Bus Master0 and Bus Master3 Proprietary PCI Bus Master Select J
6. 86 ECB 865 User s Manual ECB 865 11 After the reboot display resolution etc may be configured in the Display Properties window opened by following steps 1 and 2 above An example is shown below Display Properties 12 Before accepting the new settings by pressing OK a test should be performed by clicking the Tes button ECB 865 User s Manual 87 User s Manual Measurement Draw 6 169 07 27 18 24 64 ing 293 21 202 18 18812 18D 58 177 28 19 81 77 22 88 ECB 865 User s Manual ECB 865 Appendix A BIOS Revisions BIOS Rev New Features Bugs Problems Solved Known Problems ECB 865 User s Manual 89 User s Manual Appendix B System Resources Memory Map The following table indicates memory map of ECB 865 The address ranges specify the runtime code length ERLR A Address Range Description Note 00000000h 0009FFFFh SystemboardextensonfoACPIBIOS 000A0000h O00AFFFFH Intel R 82815 Graphics Controller 000B0000h 000BFFFFh Intel R 82815 Graphis Controller 000C0000h 000CBFFFh Intel R 82815 Graphics Controller 000E0000h 000FFFFFh SystemboardextensionforACPIBIOS 00100000h 07EFFFFFh SystemboardextensionforACPIBIOS J E7900000h E79FFFFFH Inte R 82801BA PCI Bridge 244E
7. 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness bo O OOM uuU Evalue Technology Inc ECB 865 A Message to the Customer Evalue Customer Services Each and every Evalue s product is built to the most exacting specifications to ensure reliable performance in the harsh and demanding conditions typical of industrial environments Whether your new Evalue device is destined for the laboratory or the factory floor you can be assured that your product will provide the reliability and ease of operation for which the name Evalue has come to be known Your satisfaction is our primary concern Here is a guide to Evalue s customer services To ensure you get the full benefit of our services please follow the instructions below carefully Technical Support We want you to get the maximum performance from your products So if you run into technical difficulties we are here to help For the most frequently asked questions you can easily find answers in your product documentation These answers are normally a lot more detailed than the ones we can give over the phone So please consult the user s manual first To receive the latest version of the user s manual please visit our Web site at tto www evalue tech com If you still cannot find the answer gather all the
8. Celeron Single Board Computer SBC designed with Intel embedded chipset 815E B which supports the latest Intel FC PGA FC PGA2 Pentium III Celeron processor CopperMine and Tualatin up to 1 1GHz or above and AGP 4X 3D Graphics Accelerator w shared display memory of 4MB SDRAM dual Intel PCl bus Fast Ethernet controllers and M Systems DiskOnChip socket Targeting on the mission critical telecommunication or industrial applications the ECB 865 comes designed with Intel EMD solutions These include Intel 815E B AGPset 82562ET PLC and 82559 10 100Base Tx Fast Ethernet controller Unlike regular commercial solutions Intel EMD solutions provide higher system stability and longer product supply time Intel EMD products typical life cycle is 5 years The long product life cycle guarantee is particularly important for systems that are designed to last for many years This makes it a perfect solution for not only popular Networking Devices like Firewall Gateway Router and e Server but also CTI Computer Telephony Integration equipments such as PBX Digital Logger etc Other onboard features include PC133 FSB Address Data buffer to enhance the ISA bus driving capacity up to 64mA dual UDMA 100 IDE channels two 16C550 compatible serial ports one RS 232 one RS 232 422 485 one multi mode parallel port three 168 pin DIMM sockets allowing for up to 1 5GB of SDRAM to be installed and on board proprietary PCI interface for optional PCI module
9. for a total of 4 USB ports The signals are provided by a 5 x 2 header or an optional USB bracket adapter 2 3 7 Ethernet 2 3 7 1 ICH2 LAN Controller The ICH2 s integrated LAN Controller includes a 32 bit PCI controller that provides enhanced scatter gather bus mastering capabilities and enables the LAN Controller to perform high speed data transfers over the PCI bus Its bus master capabilities enable the component to process high level commands and perform multiple operations this lowers processor utilization by off loading communication tasks from the processor Two large transmit and receive FIFOs of 3 KB each help prevent data under runs and overruns while waiting for bus accesses This enables the integrated LAN Controller to transmit data with minimum interframe spacing IFS The LAN Controller can operate in either full duplex or half duplex mode In full duplex mode the LAN Controller adheres with the IEEE 802 3x Flow Control specification Half duplex performance is enhanced by a proprietary collision reduction mechanism ECB 865 User s Manual 9 User s Manual 2 3 7 2 Intel 82559 The Ethernet interface is based on an Intel 82559 Ethernet controller that supports both 10BASE T and 100BASE TX The 82559 consists of both the Media Access Controller MAC and the physical layer PHY interface combined into a single component solution The 32 bit PCI controller provides enhanced scatter gather bus mastering capabilities and en
10. Reader port Watchdog Timer Can generate a system reset or NMI Jumper selectable time out interval 0 5 1 2 4 8 16 32 64 sec DMA 7 DMA channels 8237 equivalent ECB 865 User s Manual 3 User s Manual e Interrupt 15 interrupt levels 8259 equivalent e Hardware Status Monitoring Monitoring system temperature voltage and cooling fan status Auto throttling control when CPU overheats e Power Management Supports ATX power supply Supports PC98 LAN wake up and modem ring in functions I O peripheral devices support power saving and doze standby suspend modes APM 1 2 compliant VGA Interface e Chipset Intel 815E B 3D Graphics Accelerator e Display Memory Up to 4MB shared display memory e Interface AGP 4X Accelerator Graphics Ports 1 0 compliant e Resolution 1280 x 1024 24bpp Ultra 160 SCSI Interface Optional e Chipset Adaptec 7892 e SCSI Interface Supports 32 bit PCI interface and Ultra 160 SCSI or legacy single ended devices data transfer rates up to 160MB sec Ethernet Interface e Chipset Intel 82801BA ICH2 built in and 82559 PCI bus Ethernet controller onboard support dual Ethernet function e Ethernet Interface PCI 100 10 Mbps IEEE 802 3U compatible dual RJ 45 interfaces e Remote Boot ROM For diskless system SSD Interface One 32 pin DIP socket supports M Systems DiskOnChip 2000 series memory capacity from 8MB to 576MB Expansion Interface One 80 pin proprietary PCI interface f
11. a Place the ECB 865 into the dedicated position in your system m Attach cables to peripherals Note Please ensure that your SBC is properly installed and fixed by mechanism Otherwise the system might be unstable or do not work due to bad contact of golden finger and slot ECB 865 User s Manual 13 User s Manual 3 7 4 815E integrated Graphics Controller The on board graphics controller integrated in 815E GMCH chipset that integrates high performance memory technology for the graphics frame buffer 32 bit data interface 133 Mhz SDRAM interface only Flexible AGP in line Memory Module AIMM implementation support for two1M X16 or one 2M X32 4MB maximum addressable thus increasing the available memory bandwidth for the graphics subsystem to support high color high resolution application The ECB 865 is designed to support high performance graphics and video acceleration for all supported display resolutions display types and color modes on CRT monitor The 815E supports the modes which appear in the table below Bits Per Pixel frequency in Hz Resolution 8 bit Indexed 16 bit 320x200 70 70 70 60 75 85 1280x720 60 75 85 1600900 6075865 607586 41600120 60707275 14 ECB 865 User s Manual ECB 865 3 7 2 Intel 82559 or REALTEK RTL8139C amp 82801BA ICH2 82562ET PHY Network Controller The 82559 or RTL8139C and ICH2 PHY is fully integrated 1OBASE T 100BASE TX LAN solution The 32 bit
12. cards Windows 95 is PnP aware Set this option to No if the operating system such as DOS OS 2 Windows 3 x does not use PnP Note You must set this option correctly or PnP aware adapter cards installed in your computer will not be configured properly 62 ECB 865 User s Manual ECB 865 4 3 5 2 Clear NVRAM This option is used to clear NVRAM and check or update ESCD Extended System Configuration Data data after system power on Set this option to No that will not clear NVRAM and the operation of update ESCD is effective in different ESCD data comparison If you select the Yes setting then the BIOS will update ESCD each time of power on 4 3 5 3 PCI Latency Timer PCI Clocks This option sets the latency of all PCI devices on the PCI bus The settings are in units equal to PCI clocks The settings are 32 64 96 128 160 192 224 or 248 The Optimal and Fail Safe default settings are 64 4 3 5 4 PCI VGA Palette Snoop Leave this field at Disabled Choices are Enabled Disabled 4 3 5 5 Allocate IRQ to PCI VGA Enable Disable to assign a IRQ for PCI VGA Choices are Yes No 4 3 5 6 PCI IDE BusMaster Set this option to Enabled to specify that the IDE controller on the PCI local bus supports bus mastering capability The settings are Disabled or Enabled The default setting is Disabled 4 3 5 7 DMA Channel 0 1 3 5 6 7 Legacy ISA for devices compliant with the original PC AT bus specification PCI ISA
13. 1 2 Floppy A Floppy B Select the appropriate specifications to configure the type of floppy drive that is attached to the system 360 KB 5 1 2 MB 54 720 KB 377 and or 1 44 MB 377 The settings have not been pre installed 52 ECB 865 User s Manual ECB 865 4 3 1 3 Master Disk Slave Disk Select the appropriate values to configure the hard disk type you are using for the master and the slave Available types are 1746 USER AUTO Not Installed and CDROM The settings have not been preinstalled 4 3 1 4 Boot Sector Virus Protection Enabling this option allows the system to issue a warning when any program or virus issues a disk format command or attempts to write to the boot sector of the hard disk drive Further confirmation is required before accessing this particular section of the hard disk drive ECB 865 User s Manual 53 User s Manual 4 3 2 Advanced CMOS Setup Defaults This Setup includes all of the advanced features in the system The detail descriptions are specified as below ANIBIOS SETUP ADVANCED CMOS SETUP CC 2001 American Megatrends Inc All Rights Reserved Quick Boot Enabled Available Options 1st Boot Device Disabled i Disabled Znd Boot Device Disabled J gt Enabled 3rd Boot Device Disabled Try Other Boot Devices Yes S M R R T for Hard Disks Disabled BootUp Hum Lock On Floppy Drive Seek Disabled PS 2 Mouse Support Enabled System Keyboard Absent Primary Display Absent Password Chec
14. 102 ECB 865 User s Manual
15. All Rights Reserved Warning Temperature Disabled Available Options CPU Temperature 1 C 33 F gt Disabled System Temperature 1 C 33 F 60 C 140 F Power Fan 0 RPM 65 C 149 F CPU Fan 0 RPM 70 C 158 F Ucore 4 080V 75 C 167 F 3 300U 4 080V Ubat 4 080V 6 859V 6 859V 4 032V 15 504V 4 100 ESC Exit f4 Sel PgUp PgDn Modi fy F1 Help F2 F3 Color 4 3 7 4 Warning Temperature BIOS Setup Items Optimal Default Failsafe Default Other Options Disabled 60 C 140 F Warning Temperature 75 C 167 F 75 C 167 F 65 C 149 F 70 C 158 F 75 C 167 F ECB 865 User s Manual 67 User s Manual 4 3 7 2 CPU Temperature 4 3 7 3 System Temperature 4 3 7 4 Power Fan 4 3 7 5 System Fan 4 3 7 6 Vbsat 4 3 7 7 5VSB 4 3 7 8 5 000V 4 3 7 9 12 000V 4 3 7 10 12 000V 4 3 7 11 5 000V 44 Flash BIOS Utility Utilize AMI Flash BIOS programming utility to update on board BIOS for the future new BIOS version Please contact your technical window to get this utility if necessary Note Remark or delete any installed Memory Management Utility such as HIMEM SYS EMM386 EXE QEMM EXE etc in the CONFIG SYS files before running Flash programming utility HEEL C H 68 ECB 865 User s Manual ECB 865 5 Driver Installation 5 1 Driver Installation for Ethernet Adapter 5 1 4 Windows 9x The best way to insta
16. E8000000h EBFFFFFFh Inte R 82815 Graphics Controller EFBOOOOOH EFDFFFFFH Inte R 82801BA PClBridge 244E EFCOO000h EFCFFFFFh Intel 8255x based PCI Ethemet Adapter 10 100 EFDFFOOOh EFDFFFFFh Intel 8255x based PCI Ethernet Adapter 10 100 z MEE NE EE R 82815 Graphics Controller FFB80000h FFBFFFFFh Intel r 82802 Firmware Hub Device FFF80000h FFFFFFFFh System board extension for ACPI BIOS EFF80000h EFFFFFFFh Intel FFFF0000h FFFFFFFFh System board extension for PnP BIOS 90 ECB 865 User s Manual ECB 865 I O Map Certain I O addresses are subject to change during boot as PnP managers may relocate devices or functions The addresses shown in the table are typical locations WOPot Descipion Note 0000h 000Fh Direct memory access controller 0010h 001Fh Motheboardresoures S So o 0020h 0021h__ Programmable interrupt controller Motherboard resources S O 002Eh 002Fh Motherboard resources 0040h 0043h System timer 0044h 005Fh Motherboard resources 0060h 0060h 0061h 0061h 0062h 0063h 0064h 0064h 0065h 006Fh 0070h 0071h System CMOS real time clock 0072h 007Fh 0080h 0080h 0081h 0083h 0084h 0086h 0087h 0087h Motherboard resources ooo O 0088h 0088h Motherboard resources ES NEN E D x LS E unm Tani 0089h 008Bh Direct memory access controler lt I O08Ch D8Eh Motherboard resouroes
17. F3 Color 4 3 6 4 OnBoard FDC This option enables the floppy drive controller onboard The settings are Auto Enabled or Disabled 4 3 6 2 OnBoard Serial Porti This option enables serial port 1 onboard and specifies the base I O port address for serial port 1 The settings are Auto Disabled 3F8h SE8h 2E8h and 2F8h The Fail Safe default setting is Auto 4 3 6 3 OnBoard Serial Port2 This option enables serial port 2 onboard and specifies the base I O port address for serial port 2 The settings are Auto Disabled SF8h 2F8h 3E8h and 2E8h The default setting is Auto 64 ECB 865 User s Manual ECB 865 4 3 6 4 On Board Parallel Port There are four optional items Parallel Port Mode EPP Version Parallel Port IRQ and Parallel Port DMA Channel used to control on board parallel port interface while user select I O base address manually The following lists are available options of on board parallel port Disabled on board parallel port function is ineffective and N A 378h locate IRQ7 for this default I O address 278h assign this I O address to LPT1 3BCh assign this I O address to LPT1 4 3 6 4 1 Parallel Port Mode This option specifies the parallel port mode ECP and EPP are both bi directional data transfer schemes that adhere to the IEEE P1284 specifications This Parallel Port Mode includes four options Normal Bi Dir EPP and ECP Setting Description Normal Uni directi
18. FRAME TRDY PAR STOP AD15 AD13 AD11 LOCK D C BEO D AD4 N D2 D GND 3 3V 3 3V A 0 n i gt gt O gt gt UO ECB 865 3 11 38 Signal Description Proprietary PCI Connector J21 3 11 38 1 Address amp Data AD 31 00 Address and Data are multiplexed on the same PCI pins A bus transaction consists of an address phase followed by one or more data phases PCI supports both read and write bursts The address phase is the clock cycle in which FRAME is asserted During the address phase AD 31 00 contain a physical address 32 bits For I O this is a byte address for configuration and memory it is a DWORD address During data phases AD 07 00 contain the least significant byte Isb and AD 31 24 contain the most significant byte msb Write data is stable and valid when IRDY is asserted and read data is stable and valid when TRDY is asserted Data is transferred during those clocks where both IRDY and TRDY are asserted C BE 3 0 Bus Command and Byte Enables are multiplexed on the same PCI pins During the address phase of a transaction C BE 3 0 define the bus command During the data phase C BE 3 0 are used as Byte Enables The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data C BE 0 applies to byte 0 Isb and C BE 3 applies to byte 3 msb PAR Parity is even parity
19. O08Fh 008Fh Direct memory access controller lt lt 0094h 009Fh_ Motherboard resouroes O0AOh OOATh Programmable interrupt controler QOA2h 00BFh Motherboard resouroes o o o o OoOo o OOCOh 00DFh Direct memory access controller lt lt lt E Le od E ENS He NN i Lj 00COh 00DEh Direct memory access controller OOEOh OOEFh Motherboard resources OOFOh OOFFh Numeric data processor 0170h 0177h Secondary Ultra ATA Controller 0170h 0177h Intel R 82801BA Ultra ATA Storage Controller 244B 01FOh 01F7h Primary Ultra ATA Controller 01FOh 01F7h Intel R 82801BA Ultra ATA Storage Controller 244B 02F8h 02FFh Communications Port COM2 0376h 0376h 0376h 0376h 0378h 037Fh 03B0h 03BBh ECB 865 User s Manual 91 User s Manual VOPot Descipion Note 03COh 03DFh__ Intel R 82815 Graphics Controller o J 03FOh 03F3h Standard Floppy Disk Controller 03F4h 03FSh Standard Floppy Disk Controler Primary Ultra ATA Controller Communications Port COM1 a Motherboard resources Motherboard resources a Motherboard resources OCFBhOCFFh PClbus oo O O CO00h CFFFh Inte R 82801BAPCIBridge 244E CEB0h CEBFh Intel R PRO 100 VE Network Connection CFOOh CF3Fh Intel 8255x based PCI Ethernet Adapter 10 100 DE80h DE9Fh Intel R 82801BA BAM USB Universal Host Controller 2442
20. PCI controller provides enhanced scatter gather bus mastering capabilities and enables the 8139C to perform high speed data transfers over the PCI bus Its bus master capabilities enable the component to process high level commands and perform multiple operations which lower CPU utilization by off loading communication tasks from the CPU The ECB 865 equips two LED indicators on the RJ 45 connector to indicate the LAN interface status These messages will provide you a guide for troubleshooting Green LED LAN Activity LED that indicates the data transfer activity Blinking indicates transmission receiving activity On indicates no activity but link is valid Off link is invalid Yellow LED LAN Link Integrity LED that indicates link speed On link speed at 100Mbps Off link speed at 10Mbps 3 7 8 Drivers Support ECB 865 provides on CD Title to support on board VGA and Ethernet device drivers in various operating systems Before installing the device drivers please see the reference files in each sub directory You cannot install drivers from CD Title directly a 815E CHIPSET INTEGRATED GRAPHY Support NT4 0 Windows9x Win2000 environment a INTEL 815E amp ICH2 CHIPSET DRIVER Support NT4 0 Windows9x Win2000 environment a Intel 82559 or REALTEK 8139C Support Dos Windows3 1 Windows9x NT3 5 NT4 0 Novell OS 2 ECB 865 User s Manual 15 User s Manual 3 8 Watchdog Timer Programming When the Watch Dog Ti
21. Soft Off condition If you choose Disabled setting the system will be not resumed by LAN start ECB 865 User s Manual 61 User s Manual 4 3 5 PCI Plug and Play Setup Defaults This section describes configuring the PCI bus system PCI Peripheral Component Interconnect is a system that allows I O devices to operate at speeds nearing CPU s when they communicate with own special components All of options described in this section are important and technical and it is strongly recommended that only experienced users could make any changes to the default settings RMIBIOS SETUP PCI PLUG AND PLAY SETUP C 2001 American Megatrends Inc All Rights Reserved Plug and Play Aware O S Available Options Clear NYRAM on Every Boot E Disabled PCI Latency Timer CPCI Clocks gt Enabled Primary Graphics Adapter Auto PCI VGA Palette Snoop Disabled Allocate IRQ to PCI VGA Yes DMA Channel PnP DMA Channel PnP DMA Channel PnP DMA Channel PnP DMA Channel PnP DMA Channel PnP IRQ3 PCI PnP IRQ4 PCI PnP IRQ5 PCI PnP IRQ PCI PnP IRQS PCI PnP ESC Exit Tl Sel IRQ10 PCI PnP PgUp PgDn Modi fy IRQ11 PCI PnP F1 Help F2 F3 Color 4 3 5 1 Plug and Play Aware O S Set this option to Yes if the operating system installed in the computer is Plug and Play aware BIOS only detects and enables PnP ISA adapter cards that are required for system boot The Windows 95 operating system detects and enables all other PnP aware adapter
22. To program DMA unit 1 and 2 DMA unit 1 and 2 programming over To initialize 8259 interrupt controller Extended NMI sources enabling is in progress The keyboard test has started Clearing the output buffer and checking for stuck keys Issuing the keyboard reset command next 100 ECB 865 User s Manual ECB 865 A keyboard reset error or stuck key was found Issuing the keyboard Controller interface test command next 81 82 The keyboard controller interface test completed Writing the command byte and initializing the circular buffer next 83 Command byte written Global data init done To check for lock key Locked key checking is over Checking for a memory size mismatch with CMOS RAM data next SIL ee for a password or bypassing Setup next Setup code and executing the AMIBIOS Setup utility next do programming after setup Screen message next The first screen message has been displayed The WAIT message is displayed Performing the PS 2 mouse check and extended BIOS data area allocation check next Programming the Setup options next Going for hard disk controller reset Hard disk controller reset done Floppy setup to be done next completed The adaptor ROM check is next The adaptor ROM had control and has now returned control to BIOS POST Performing any required processing after the option ROM returned control Initializing the bus option ROMs from C800 next The floppy drive controller has b
23. at port 80H will be the last test performed In this case the terminal error cannot be displayed on the screen The following POST checkpoint codes are valid for all AMIBIOS products with a core BIOS date of 07 15 95 version 6 27 Enhanced Uncompressed Initialization Codes The uncompressed initialization checkpoint hex codes are listed in order of execution be started M test Doce E memory refresh pu going to 4GB flat mode D3 To start memory sizing start memory sizing Returning to real mode Executing any OEM patches and setting the stack next Passing control to the uncompressed code in shadow RAM at E000 0000h The INIT code is copied to segment 0 and control will be transferred to segment 0 Control is in segment 0 Next checking if Ctrl Home was pressed and verifying the system BIOS checksum If either Ctrl Home was pressed or the system BIOS checksum is bad next will go to checkpoint code EOh Otherwise going to checkpoint code D7h D7 fro pass control to interface module D8 Main BIOS runtime code is to be decompressed D9 Passing control to the main system BIOS in shadow RAM next 96 ECB 865 User s Manual ECB 865 Bootblock Recovery Codes The bootblock recovery checkpoint hex codes are listed in order of execution the base 512KB memory test E6 Enabling the floppy drive controller and Timer IRQs Enabling internal cache memory Initializing the floppy
24. conflict 3 5 4 Installing DOC Align the DOC with the pinholes on the socket Make sure that the notched corner or dot mark pin 1 of DOC corresponds to notched corner of the socket Then press the DOC gently until it fits into place If installation procedure is correct the flash disk can be viewed as a normal hard disk to access read write data now Note Please make sure that your DOC is properly inserted Place the DOC in wrong direction will damage the flash device If you system would like to boot from the flash disk it is recommended to refer to the application note provided by M Systems first You can easily obtain the application note from M Systems DiskOnChip user s manual or from their web site as below http www m sys com 3 6 Expansion Interface The ECB 865 reserves an 80 pin proprietary PCI interface J22 for PCI device such as LAN Audio SCSI Video Capture expansion in the future This installation of expansion module is very simple and easy Without any special tool all you need to do is just make the board to board connection and lock up the screw For more information about the expansion module please refer to the instruction manual attached with each module 3 7 Installing the Single Board Computer To install your ECB 865 into chassis or proprietary environment the following steps have to be followed a Make sure all jumpers are properly set a Install and configure CPU and memory module correctly
25. devices that a given data transfer cycle assertion of PDIOR or PDIOW is a DMA data transfer cycle This signal is used in conjunction with the PCI bus master IDE function It is not associated with any AT compatible DMA channel If the IDE signals are configured for Primary and Secondary this signal is connected to the corresponding signal on the Primary IDE connector If the IDE signals are configured for Primary Master and Primary Slave this signal is used for the Primary Master connector ECB 865 User s Manual 29 User s Manual Secondary DMA Acknowledge This signal directly drives the IDE device DMACK signal It is asserted by PIIX4 to indicate to IDE DMA slave devices that a given data transfer cycle assertion of SDIOR or SDIOW is a DMA data transfer cycle This signal is used in conjunction with the PCI bus master IDE function It is not associated with any AT compatible DMA channel If the IDE signals are configured for Primary and Secondary this signal is connected to the corresponding signal on the Secondary IDE connector If the IDE signals are configured for Primary Master and Primary Slave these signals are used for the Primary Slave connector Primary Disk Act Signal from Primary IDE device indicating Primary IDE device activity The signal level depends on the hard disk type normally active low Secondary Disk Act Signal from Secondary IDE device indicating Secondary IDE device activity The signal level dep
26. display driver for the Chips amp Technologies 69000 PCI display controller 1 Click the Star button on the task bar select Settings and Control Panel from the sub menu This should start the Control Panel as shown below Cential Paral Dispar Piopeited ECB 865 User s Manual 79 User s Manual 3 Click the Advanced button This will show the following window Click the Change button in the Adapter Type frame to select another driver Your display will probably have another driver then the Standard PCI Graphics Adapter VGA installed at this moment 80 ECB 865 User s Manual ECB 865 5 Click the Nexf to continue the display driver installation Update Device Driver Wizard 6 Locate the path of Graphics adapter driver and click the Nex button Update Device Driver Wizard C NC amp TSSS000NWinS8 isi lt Back New Cae ECB 865 User s Manual 81 User s Manual 7 The driver files will now be read and the display adapter is shown as the following Click the Nex button to install the display driver Update Device Driver Wizard Windows driver file search for the device Chips and Tech 69000 PCI Windows is now ready to install the best driver for this device Click Back to select a different driver or click Next to continue Location of driver C ACTABS000 WINSS CHIPS98 INF lt Back E Cancel 8 Click the Finis
27. expansion The PCI modules currently available are Adaptec 7892 Ultra 160 SCSI and Intel 82559 10 100Base Tx Ethernet modules 2 ECB 865 User s Manual ECB 865 2 2 System Specifications General Functions Bus Interface PICMG 2 0 Compliant ISA Driving Capacity Built in Address Data buffer supports driving capacity up to 64mA CPU Supports Intel FCPGA FCPGA2 Pentium III Celeron processor up to 1GHz or above with system bus frequencies of 66 100 133MHz CPU Socket Intel FC Socket 370 BIOS AMI 4Mb FWH BIOS Chipset Intel 815E B AGPset I O Chipset ITE IT8712F A Memory Onboard three 168 pin DIMM sockets support up to 1 5Gbytes SDRAM Enhanced IDE Supports up to four IDE devices Supports Ultra DMA 33 66 100 mode with data transfer rate up to 100MB sec 20 x 2 header x 2 onboard FDD Interface Supports up to two floppy disk drives 5 25 360KB and 1 2MB and or 3 5 720KB 1 44MB and 2 88MB Parallel Port One bi directional parallel port Supports SPP ECP and EPP modes Serial Port One RS 232 serial ports and one RS 232 422 485 serial port Ports can be configured as COM1 COM2 COM3 COM4 or disabled individually 16C550 equivalent IR Interface Supports one IrDA Tx Rx header KB Mouse Connector One 6 pin mini DIN connector supports PS 2 keyboard and mouse USB Connectors Two 5 x 2 header onboard support up to four USB ports Smart Card Reader Connector One 7 x 2 header onboard support a Smart Card
28. used in conjunction with IRDY A data phase is completed on any clock both TRDY and IRDY are sampled asserted During a read TRDY indicates that valid data is present on AD 31 00 During a write it indicates the target is prepared to accept data Wait cycles are inserted until both IRDY and TRDY are asserted together Stop indicates the current target is requesting the master to stop the current transaction LOCK Lock indicates an atomic operation that may require multiple transactions to complete When LOCK is asserted non exclusive transactions may proceed to an address that is not currently locked A grant to start a transaction on PCI does not guarantee control of LOCK Control of LOCK is obtained under its own protocol in conjunction with GNT H It is possible for different agents to use PCI while a single master retains ownership of LOCKZ If a device implements Executable Memory it should also implement LOCK and guarantee complete access exclusion in that memory A target of an access that supports LOCK must provide exclusion to a minimum of 16 bytes aligned Host bridges that have system memory behind them should implement LOCK as a target from the PCI bus point of view and optionally as a master Initialization Device Select is used as a chip select during configuration read and write transactions DEVSEL Device Select when actively driven indicates the driving device has decoded its address as the target of the c
29. 65 3 11 17 Box Header Serial Port 1 Serial Port 2 Connector in RS 422 J9 J12 3 11 18 Signal Description Serial Port 1 Serial Port 2 in RS 422 Mode J9 J12 Serial output This differential signal pair sends serial data to the communication link Data is transferred from Serial Port 2 Transmit Buffer Register to the communication link if the TxD line driver is enabled through the Serial Port 2 s DTR signal Modem control register Serial input This differential signal pair receives serial data from the communication link Received data is available in Serial Port 2 Receiver Buffer Register Request To Send The level of this differential signal pair output is controlled through the Serial Port 2 s RTS signal Modem control register Clear To Send The level of this differential signal pair input could be read from the Serial Port 2 s CTS signal Modem control register 3 11 19 Box Header Serial Port 1 Serial Port 2 Connector in RS 485 J9 J12 NC t0 9 CTSRTS Nc al CTS RTS Da RXDITxD 4 3 Romo nc BEE NC ECB 865 User s Manual 37 User s Manual 3 11 20 Signal Description Serial Port 1 Serial Port 2 in RS 485 Mode J9 J12 RxD TxD Bi directional data signal pair Received data is available in Serial Port 2 Receiver Buffer Register Data is transferred from Serial Port 2 Transmit Buffer Register to the communication line if the TxD line driver is enabled thr
30. CI Bus Master Adapter 30590 BI 3Com Etherlink16 EtherLink16 TP Adapter ECB 865 User s Manual 75 User s Manual 4 Click the Have Disk button to install the Network adapter driver from CD ROM A window as the one shown below should now appear Insert Disk EEE 76 ECB 865 User s Manual ECB 865 6 Select the Intel PRO Adapter from the list as shown below and click the OK button The Network adapter driver should now be installed Select DEM Option Intell R PRO Adapter 7 After the driver installation is complete Protocols Services etc may now be configured for the network to be used An example is shown below 1 Intel 8255x based PCI Ethernet Adapter 10 100 Intel 8255x based PCI Ethernet Adapter 10 100 Bus 0 Slot 12 ECB 865 User s Manual 77 User s Manual 8 Click Close to accept the settings 9 IP Address DNS etc may now be configured for the network to be used Click OK to accept the settings Microsoft TCP IP Properties DNS WINS Address Routing 0 1 Intel 8255 based PCI Ethernet Adapter 10 100 ha 10 To complete the driver installation reboot the computer by clicking the Yes button in the window shown below Network Settings Change 78 ECB 865 User s Manual ECB 865 5 2 Driver Installation for Display Adapter 5 2 4 Windows 9x The following steps will install the
31. DFOOh DFiFh Intel R 82801BA BAM USB Universal Host Controller 2444 Primary Ultra ATA Controller a Intel R 82801BA Ultra ATA Storage Controller 244B HEN Secondary Ultra ATA Controller 92 ECB 865 User s Manual ECB 865 Interrupt Usage The onboard Intel 82801BA provides an ISA compatible interrupt controller with functionality as two 8259A interrupt controllers The two controllers are cascaded to provide 13 external interrupts The actual interrupt settings depend on the PnP handler the table below indicates the typical settings IRQO System timer eS IRQ1 Standard 101 102 Key or Microsoft Natural Keyboard IRQ2 Programmable interrupt controller IRQ3 Communications Port COM2 i IRQ4 Communications Port COM1 Communications Port COM1 IRQS ACPI IRQ Holder for PCI IRQ Steering o o o IROS Inte R 82801BA BAM USB Universal Host Controller 2442 IRQS intel 8255x based PCI Ethernet Adapter 10100 IRQ6 Standard Floppy Disk Controler o ooo o IRQ8 System CMOS real time clock SCI IRQ used by ACPI bus IRQ10 Intel R PRO 100 VE Network Connection a IRQ10 ACPI IRQ Holder for PCI IRQ Steering IRQ10 Intel R 82801BA BAM USB Universal Host Controller 2444 IRQ10 ACPI IRQ Holder for PCI IRQ Steering IRQ11 Intel R 82815 Graphics Controller a IRQ11 ACPI IRQ Holder for PCI IRQ Steering IRQ12 PS 2 Compatible Mouse Port IRQ13 Numeric data processor a I
32. IDE GONE initialization system static output devices will be done next if present configuration before the video ROM test To look for optional video ROM and give control Blind required processing after the video ROM had control CIEL EM is not found performing the display memory read write test next 2F EGAVGA not found Display memory R W test about to begin 30 Display memory R W test passed Look for retrace checking next EN Display memory R W test or retrace checking failed To do alternate display retrace checking 32 Alternate display memory R W test passed To look for the alternate display retrace checking 34 Video display checking is over Setting the display mode next 37 The display mode is set Displaying the power on message next L8 etsleng ne pus ou Pt amd general devices next f present the bus input IPL and general devices next if present 39 Displaying bus initialization errormessage bus initialization error message 3A The new cursor position has been read and saved Displaying the Hit DEL message next Preparing the descriptor tables next Entering protected mode for the memory test next Entered protected mode Enabling interrupts for diagnostics mode next Interrupts enabled if the diagnostics switch is on Initializing data to check memory wraparound at 0 0 next calculation has been done Writing patterns to test memory next patterns to the base 640 KB m
33. If your system installs good quality of SDRAM you can set this option to 2 SCLKs to obtain better memory performance Normally the option will be set to 3 SCLKs 4 3 3 7 SDRAM RAS Precharge This option controls the number of SCLKs for RAS precharge If your system installs good quality of SDRAM you can set this option to 2 SCLKs to obtain better memory performance 4 3 3 8 Internal Graphic Mode Select This option allows the end users to specify the size of video memory shared from system memory 4 3 3 9 USB Function This option will enable on chip USB function to support USB Universal Serial Bus peripheral devices if user chooses the Enabled setting 58 ECB 865 User s Manual ECB 865 4 3 4 Power Management Setup Defaults This APM Advanced Power Management determines how much power energy setting below items to handle system power resource can save The following descriptions will specify the definition of each item in details RHMIBIOS SETUP POWER MANAGEMENT SETUP C 2001 American Megatrends Inc All Rights Reserved ACPI Aware O S Yes Available Options Power Management APM Enabled Ho Green PC Monitor Power State Stand By b Yes Uideo Power Down Mode Suspend Hard Disk Power Down Mode Stand By Hard Disk Time Out CMinute Disabled Suspend Time Out Disabled Throttle Slow Clock Ratio 50 0 Keyboard amp PS 2 Mouse Monitor FDC LPT CO0M Ports Monitor Primary Master IDE Monitor Primary Sla
34. MOS SETUP CC 2001 American Megatrends Inc ALL Rights Reserved 2nd Boot Device Disabled Available Options 3rd Boot Device Disabled gt Disabled Try Other Boot Devices Yes Enabled S M R R T for Hard Disks Disabled Cached WP BootUp Hum Lock On Floppy Drive Seek Disabled PS 72 Mouse Support Enabled System Keyboard Absent Primary Display Absent Password Check Setup Boot To 0572 Ho System BIOS Cacheable Enabled C000 16k Shadow Disabled C400 16k Shadow Disabled C800 16k Shadow Disabled CC00 16k Shadow Disabled D000 16k Shadow Disabled D400 16k Shadow Disabled ESC Exit T Sel D800 16k Shadow Disabled a PgUp PgDn Modi fy DCO0 16k Shadow Disabled F1 Help F2 F3 Color 56 ECB 865 User s Manual ECB 865 4 3 3 Advanced Chipset Setup Defaults This Setup is very important to keep system s stability If you are not technical person do not attempt to change any parameters The best way is to choose optimal default setting RMIBIOS SETUP ADVANCED CHIPSET SETUP CC 2001 American Megatrends Inc fill Rights Reserved CPU Ratio Selection Safe Mode Available Options ICH Delayed Transaction Enabled gt Safe Mode Memory Hole Disabled 0x DRAM Cycle time CSCLKs 678 X CASH Latency CSCLKs 3 Ox RAS to CAS delay CSCLKs 3 5x SDRAM RASH Precharge CSCLKs 3 Ox Internal Graphics Mode Select 1MB 5x CPU Latency Timer Disabled Ox USB Function ALL USB Port 5x USB Device Legacy Support Disabled Ox Clock Sp
35. P 13 Bus Master 0 Bus Master 3 24668 246 8 Co c 1357 1357 default sss o ___ ECB 865 User s Manual 23 User s Manual 3 11 Connector Definitions 3 11 1 System Reset Connector J1 Signal PIN 3 11 2 External Speaker Connector J2 3 11 3 Keyboard Lock amp Power Indicator Connector J3 GND 3 11 4 Primary IDE Secondary IDE Active Indicator Connector J4 ee 24 ECB 865 User s Manual ECB 865 3 11 5 Primary IDE Connector J5 Signal PIN Signa PDDREQ PDIORDY PDDACK pocst o PoDAcT so A eo 38 PDCS3 40 w j 1W NM IM IN IN NM j gt j gt w Qo IW WO ININ IN IN IN N OJA IM CO jo O CO 0o O IN ECB 865 User s Manual 25 User s Manual 3 11 6 Secondary IDE Connector J10 Signal PIN Signa SDDREQ SDIORDY SDDACK _spcsi s SDDACT 39 A eo N Ww C9 V IN IN N N J gt j gt j gt J gt 38 f SDCS3 40 9 lw o o In IN IN IN IN gt 2 l gt l gt gt X o IR IN 1S l O JK IN S o o gt N 26 ECB 865 User s Manual ECB 865 3 11 7 Signal Description Primary amp Secondary IDE Connector J5 amp J10 PDA 2 0 Primary Disk Address 2 0 These signals indicate which byte in either the ATA command block or control block is being addressed If the IDE signals are configured for Primary and Secondary these signals are conne
36. PnP for devices compliant with the Plug and Play standard whether designed for PCI or ISA bus architecture Choices are SA EISA and PnP 4 3 5 8 IRQ3 4 5 7 9 10 11 14 15 These options specify the bus that the named interrupt request lines IRQs are used on These options allow you to specify IRQs for use by legacy ISA adapter cards These options determine if AMIBIOS should remove an IRQ from the pool of available IRQs passed to BIOS configurable devices The available IRQ pool is determined by reading the ESCD NVRAM If more IRQs must be removed from the pool the end user can use these PCI PnP Setup options to remove the IRQ by assigning the option to the SA E SA setting Onboard l O is configurable by AMIBIOS The IRQs used by onboard l O are configured as PCI PnP The settings are PCI PnP or ISA EISA The default settings are PCI PnP ECB 865 User s Manual 63 User s Manual 4 3 6 Peripheral Setup Defaults This section describes I O resources assignment for all of on board peripheral devices RMIBIOS SETUP PERIPHERAL SETUP CC 2001 American Megatrends Inc fill Rights Reserved OnBoard FDC OnBoard Serial Port OnBoard Serial Port2 Serial Port2 Mode OnBoard Parallel Port Parallel Port Mode Parallel Port IRQ Parallel Port DMA Channel On Chip IDE Auto Auto Auto Normal Auto Normal Auto N A Both Available Options gt Auto Disabled Enabled ESC Exit TL Sel PgUp PgDn Modi fy F1 Help F2
37. RQ14_ Intel R 82801BA Ultra ATA Storage Controller 244B IRQ14 Primary Ultra ATA Controller IRQ15 Intel R 82801BA Ultra ATA Storage Controller 244B IRQ15__ Secondary Ultra ATA Controller ECB 865 User s Manual 93 User s Manual DMA channel Usage The DMA circuitry incorporates the functionality of two 8237 DMA controllers with seven programmable channels The controllers are referenced DMA Controller 1 for channels 0 3 and DMA Controller 2 for channels 4 7 Channel 4 is by default used to cascade the two controllers DMA channel Description Note DMAO Available for PC 104 interface amp PCI sit Dma1 Available for PC 104 interface amp PCI sit DMA2 Standard Floppy Disk Controller DMA3 Parallel port if using ECP mode DMA4 Used for cascading DMAS Available for PC 104 interface amp PCI slot DMA6 Available for PC 104 interface amp PCI slot DMA7 Available for PC 104 interface amp PCI slot 94 ECB 865 User s Manual ECB 865 Appendix C AMIBIOS Power On Self Test Every time the system is powered on AMIBIOS executes a power on self test In case of errors they are reported in one of two ways If the error occurs before the display device is initialised a series of beeps sound Beep codes indicate that a fatal error has occurred AMIBIOS Beep Codes are described in the table below if it beeps 1 2 or 3 times Re insert the me
38. T completes 4 3 2 3 Try Other Boot Device Set this option to Yes to try other boot device The settings are Yes or No The default setting is Yes 4 3 2 4 S M A R T for Hard Disks Set this option to Enabled the S M A R T function for Hard Disks The settings are Enabled or Disabled The default setting is Disabled 4 3 2 5 BootUp Num Lock Set this option to Off to turn the Num Lock key off when the computer is booted so you can use the arrow keys on both the numeric keypad and the keyboard The settings are On or Off The default setting is On 4 3 2 6 Floppy Drive Swap Set this option to Enabled to permit drives A or B to be swapped The settings are Enabled or Disabled The default setting is Disabled 4 3 2 7 Floppy Drive Seek Set this option to Enabled to specify that floppy drive A will perform a seek operation at system boot The settings are Enabled or Disabled The default setting is Disabled 4 3 2 8 PS 2 Mouse Support When this option is set to Enabled AMIBIOS supports a PS 2 type mouse The settings are Enabled or Disabled The default setting is Enabled 4 3 2 9 Primary Display This option specifies the type of display monitor and adapter in the computer The settings are Mono CGA40x25 CGA80x25 VGA EGA or Absent The default setting is VGA EGA 4 3 2 10 Password Check This option enables the password checking when the system boots up or runs CMOS Setup It only takes effect after setting Change S
39. User s Manual ECB 865 Intel 815E Tualatin Pentium lll Celeron Full size CPU Card 1 Ed 7 February 2002 Part No 2047865000 ECB 865 FCC STATEMENT THIS DEVICE COMPLIES WITH PART 15 FCC RULES OPERATION IS SUBJECT TO THE FOLLOWING TWO CONDITIONS 1 THIS DEVICE MAY NOT CAUSE HARMFUL INTERFERENCE 2 THIS DEVICE MUST ACCEPT ANY INTERFERENCE RECEIVED INCLUDING INTERFERENCE THAT MAY CAUSE UNDESIRED OPERATION THIS EQUIPMENT HAS BEEN TESTED AND FOUND TO COMPLY WITH THE LIMITS FOR A CLASS A DIGITAL DEVICE PURSUANT TO PART 15 OF THE FCC RULES THESE LIMITS ARE DESIGNED TO PROVIDE REASONABLE PROTECTION AGAINTST HARMFUL INTERFERENCE WHEN THE EQUIPMENT IS OPERATED IN A COMMERCIAL ENVIRONMENT THIS EQUIPMENT GENERATES USES AND CAN RADIATE RADIO FREQUENCY ENERGY AND IF NOT INSTATLLED AND USED IN ACCORDANCE WITH THE INSTRUCTION MANUAL MAY CAUSE HARMFUL INTERFERENCE TO RADIO COMMUNICATIONS OPERATION OF THIS EQUIPMENT IN A RESIDENTIAL AREA IS LIKELY TO CAUSE HARMFUL INTERFERENCE IN WHICH CASE THE USER WILL BE REQUIRED TO CORRECT THE INTERFERENCE AT HIS OWN EXPENSE Ver D l aM Evalue Technology Inc User s Manual Copyright Notice Copyright 2000 2001 Evalue Technology Inc ALL RIGHTS RESERVED No part of this document may be reproduced copied translated or transmitted in any form or by any means electronic or mechanical for any purpose without the prior written permission of the original manufacturer Tr
40. ables the 82559 to perform high speed data transfers over the PCI bus Its bus master capabilities enable the component to process high level commands and perform multiple operations which lowers CPU utilization by off loading communication tasks from the CPU Two large transmit and receive FIFOs of 3 Kbyte each help prevent data under runs and overruns while waiting for bus accesses This enables the 82559 to transmit data with minimum interframe spacing IFS 2 3 8 ITE IT8712F A The Winbond W83977TF AW Super I O chip provides most input output interfaces of the system as the following a COM 1 2 RS 232 RS 422 RS 485 driver are used whereby RS 232 RS 422 and RS 485 are provided Mode can be selected by setting hardware jumper Drivers use charge pumps whereby only 5V is required a LPT Support for SPP EPP and ECP modes Floppy interface Keyboard interface a PS 2 Mouse interface wm IrDA interface for infrared communication This interface shares the controller of COM2 a Provision of buffered ISA databus for BIOS denoted XDBus a NVRam with battery backup for BIOS configuration and real time clock 2 3 9 M Systems DiskOnChip M Systems DiskOnChip 2000 is a high performance single chip flash disk in a standard 32 pin DIP package This unique data storage solution offers cost effective data storage beyond that of traditional hard disks Perfect for applications with limited space and varying capacity requirements The Di
41. across AD 31 00 and C BE 3 0 Parity generation is required by all PCI agents PAR is stable and valid one clock after the address phase For data phases PAR is stable and valid one clock after either IRDY is asserted on a write transaction or TRDY is asserted on a read transaction Once PAR is valid it remains valid until one clock after the completion of the current data phase PAR has the same timing as AD 31 00 but it is delayed by one clock The master drives PAR for address and write data phases the target drives PAR for read data phases ECB 865 User s Manual 45 User s Manual 3 11 38 2 System Clock provides timing for all transactions on PCI and is an input to every PCI device All other PCI signals except RST INTA INTB INTC and INTD are sampled on the rising edge of CLK and all other timing parameters are defined with respect to this edge PCI operates up to 33 MHz or 66 MHz and in general the minimum frequency is DC 0 Hz Reset is used to bring PCl specific registers sequencers and signals to a consistent state What effect RST has on a device beyond the PCI sequencer is beyond the scope of this specification except for reset states of required PCI configuration registers Anytime RST is asserted all PCI output signals must be driven to their benign state In general this means they must be asynchronously tri stated SERR open drain is floated REQ and GNT must both be tri stated they
42. ademark Acknowledgement Brand and product names are trademarks or registered trademarks of their respective owners Disclaimer Evalue Technology Inc reserves the right to make changes without notice to any product including circuits and or software described or contained in this manual in order to improve design and or performance Evalue Technology assumes no responsibility or liability for the use of the described product s conveys no license or title under any patent copyright or mask work rights to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Applications that are described in this manual are for illustration purposes only Evalue Technology Inc makes no representation or warranty that such application will be suitable for the specified use without further testing or modification Life Support Policy Evalue Technologys PRODUCTS ARE NOT FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE PRIOR WRITTEN APPROVAL OF Evalue Technology Inc As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labelling can be reasonably expected to result in significant injury to the user
43. are configured for Primary and Secondary this signal is connected to the corresponding signal on the Secondary IDE connector If the IDE signals are configured for Primary Master and Primary Slave these signals are used for the Primary Slave connector 28 ECB 865 User s Manual ECB 865 Primary IO Channel Ready In normal IDE mode this input signal is directly driven by the corresponding IDE device IORDY signal In an Ultra DMA 33 read cycle this signal is used as STROBE with the PIIX4 latching data on rising and falling edges of STROBE In an Ultra DMA 33 write cycle this signal is used as the DMARDY signal which is negated by the drive to pause Ultra DMA 33 transfers If the IDE signals are configured for Primary and Secondary this signal is connected to the corresponding signal on the Primary IDE connector If the IDE signals are configured for Primary Master and Primary Slave this signal is used for the Primary Master connector This is a Schmitt triggered input Secondary IO Channel Ready In normal IDE mode this input signal is directly driven by the corresponding IDE device IORDY signal In an Ultra DMA 33 read cycle this signal is used as STROBE with the PIIX4 latching data on rising and falling edges of STROBE In an Ultra DMA write cycle this signal is used as the DMARDY signal which is negated by the drive to pause Ultra DMA 33 transfers If the IDE signals are configured for Primary and Secondary this signal i
44. ary this signal is connected to the corresponding signal on the Secondary IDE connector If the IDE signals are configured for Primary Master and Primary Slave these signals are used for the Primary Slave connector Primary Disk IO Write In normal IDE mode this is the command to the IDE device that it may latch data from the PDD 15 0 lines Data is latched by the IDE device on the negation edge of PDIOW The IDE device is selected either by the ATA register file chip selects PDCS1 PDCS3 and the PDA 2 0 lines or the IDE DMA slave arbitration signals PDDACK For Ultra DMA 33 mode this signal is used as the STOP signal which is used to terminate an Ultra DMA 33 transaction If the IDE signals are configured for Primary and Secondary this signal is connected to the corresponding signal on the Primary IDE connector If the IDE signals are configured for Primary Master and Primary Slave this signal is used for the Primary Master connector Secondary Disk IO Write In normal IDE mode this is the command to the IDE device that it may latch data from the SDD 15 0 lines Data is latched by the IDE device on the negation edge of SDIOW The IDE device is selected either by the ATA register file chip selects SDCS1 SDCS3 and the SDA 2 0 lines or the IDE DMA slave arbitration signals SDDACK In read and write cycles this signal is used as the STOP signal which is used to terminate an Ultra DMA 33 transaction If the IDE signals
45. cannot be driven low or high during reset To prevent AD C BE and PAR signals from floating during reset the central resource may drive these lines during reset bus parking but only to a logic low level they may not be driven high RST may be asynchronous to CLK when asserted or deasserted Although asynchronous deassertion is guaranteed to be a clean bounce free edge Except for configuration accesses only devices that are required to boot the system will respond after reset 46 ECB 865 User s Manual ECB 865 3 11 38 3 Interface Control FRAME Cycle Frame is driven by the current master to indicate the beginning and duration of an access FRAME is asserted to indicate a bus transaction is beginning While FRAME is asserted data transfers continue When FRAME is deasserted the transaction is in the final data phase or has completed Initiator Ready indicates the initiating agent s bus master s ability to complete the current data phase of the transaction IRDY is used in conjunction with TRDY A data phase is completed on any clock both IRDY and TRDY are sampled asserted During a write IRDY indicates that valid data is present on AD 31 00 During a read it indicates the master is prepared to accept data Wait cycles are inserted until both IRDY and TRDY are asserted together TRDY Target Ready indicates the target agent s selected device s ability to complete the current data phase of the transaction TRDY is
46. cted to the corresponding signals on the Primary IDE connector If the IDE signals are configured for Primary 0 and Primary 1 these signals are used for the Primary 0 connector SDA 2 0 Secondary Disk Address 2 0 These signals indicate which byte in either the ATA command block or control block is being addressed If the IDE signals are configured for Primary and Secondary these signals are connected to the corresponding signals on the Secondary IDE connector If the IDE signals are configured for Primary Master and Primary Slave these signals are used for the Primary Slave connector PDCS1 Primary Disk Chip Select for 1FOH 1F7H Range For ATA command register block If the IDE signals are configured for Primary and Secondary this output signal is connected to the corresponding signal on the Primary IDE connector If the IDE signals are configured for Primary Master and Primary Slave this signal is used for the Primary Master connector PDCS3 Primary Disk Chip Select for 3FOH 3F7H Range For ATA control register block If the IDE signals are configured for Primary and Secondary this output signal is connected to the corresponding signal on the Primary IDE connector If the IDE signals are configured for Primary Master and Primary Slave this signal is used for the Primary Master connector SDCS1 Secondary Chip Select for 170H 177H Range For ATA command register block If the IDE signals are configured for Primary and Secondary this
47. ctor 5 x 2 header pitch 2 54mm J10 Secondary IDE connector 20 x 2 header pitch 2 54mm J11 Parallel port connector 5 x 2 header pitch 2 54mm J12 Serial port 2 connector 5 x 2 header pitch 2 54mm J13 USB connector 5 x 2 header pitch 2 54mm J14 CPU fan connector 3 x 1 wafer pitch 2 54mm J15 Fast and standard IrDA Infrared 6 x 1 header pitch 2 54mm connector J16 ATX power control connector 4 x 1 wafer pitch 2 54mm J17 Smart card reader connector 7 x 2 header pitch 2 54mm J18 10 100Base Tx Ethernet connector 1 RJ 45 6 pin mini DIN J19 USB connector 5 x 2 header pitch 2 54mm J20 10 100Base Tx Ethernet connector 2 RJ 45 J21 Proprietary PCI connector J22 CRT connector DB 15 female connector J23 M Systems DiskOnChip socket 16 x 2 DIP socket J24 Internal keyboard connector 5 x 1 wafer pitch 2 54mm J25 System fan connector 3 x 1 wafer pitch 2 54mm J26 PS 2 keyboard connector 6 pin mini DIN ECB 865 User s Manual 19 User s Manual 3 10 Setting Jumpers You can configure your board to match the needs of your application by setting jumpers A jumper is the simplest kind of electric switch It consists of two metal pins and a small metal clip often protected by a plastic cover that slides over the pins to connect them To close a jumper you connect the pins with the clip To open a jumper you remove the clip Sometimes a jumper will have three pins labeled 1 2 and 3 In this case you would connect either two pins
48. d or none were present a new driver can be installed now 2 Reboot the computer 3 During the boot up the network adapter should be detected as shown below Click the Next button Update Device Driver Wizard 70 ECB 865 User s Manual ECB 865 4 Click the Nexf button to continue the driver installation Update Device Driver Wizard ECB 865 User s Manual 71 User s Manual 6 Click the Nex button to install the network adapter driver Update Device Driver Wizard 7 Click the Nex button 72 ECB 865 User s Manual ECB 865 8 Click the Finish button Update Device Driver Wizard 9 To complete the installation reboot the computer by clicking the Yes button in the window shown below 10 After the system restarts the network adapter should be installed Protocols clients etc may now be installed for the network in use Further configuration of the adapter may be made in the Advanced section of the driver properties These options may be accessed through the Network icon in the control panel Select the network adapter click the Properties button and select the Advanced tab ECB 865 User s Manual 73 User s Manual 5 1 2 Windows NT 4 0 Ethernet Installation A driver for the Intel 82559 Ethernet controller on board is included in the attached supporting CD ROM The driver for this adapter is denoted Intel amp PRO Adapt
49. drive Start looking for a diskette in drive A and read first sector of the diskette EF A read error occurred while reading the floppy drive in drive A Lo ex searching for the AMIBOOT ROM file in the root directory The AMIBOOT ROM file is not in the root directory Next reading and analyzing the floppy diskette FAT to find the clusters eee O IEEE TT the AMIBOOT ROM file F3 Start Start reading AMIBOOT ROM file cluster by cluster ssi AMIBOOT ROM file cluster by cluster ere AMIBOOT ROM file is not the correct size F5 Next disabling internal cache memory FB Next detecting the type of Flash ROM FC Erasing the Flash ROM FD Programming the Flash ROM EB ROM programming was successful Next restarting the system BIOS ECB 865 User s Manual 97 User s Manual Uncompressed Initialization Codes The following runtime checkpoint hex codes are listed in order of execution These codes are uncompressed in F0000h shadow RAM 3 The NMI is disabled Next checking for a soft reset or a power on condition 1 05 The BIOS stack has been built Next disabling cache memory 06 Uncompressing the POST code next o7 Next initializing the CPU and the CPU data area 08 The CMOS checksum calculation is done next OB Next performing any required initialization before the keyboard BAT command is issued command to the keyboard controller E The keyboard con
50. e through a set of control registers The DRAM controller supports the following features a DRAM type Support for x8 and x16 SDRAM device width Unbuffered and Non ECC SDRAM only a Memory Size 32 MB to 512 MB using 16Mb 64Mb 128Mb 256Mb technology a Addressing Type Asymmetrical addressing only a DRAM Speeds 100 133 MHz for synchronous memory SDRAM a Memory Modules supported Up to 3 double sided DIMMs at 100 MHz system memory bus Up to 2 double sided or 3 single sided DIMMs at 133 MHz system memory bus a Suspend to RAM support 2 3 3 Multiplexed AGP and Display Cache Interface The Intel 82815 GMCH multiplexes an AGP interface with a display cache interface for internal 3D graphics performance improvement The display cache is used only in the internal graphics When an AGP card is installed in the system the GMCH internal graphics will be disabled and the AGP controller will be enabled 2 3 3 1 AGP Interface A single AGP connector is supported by the GMCH AGP interface The AGP buffers operate in one of two selectable modes in order to support the AGP Universal Connector a 3 3 V drive not 5 Volt safe This mode is compliant to the AGP 1 0 and 2 0 specifications m 1 5 V drive not 3 3 Volt safe This mode is compliant with the AGP 2 0 specification The following table shows the AGP Data Rate and the Signaling Levels supported by the Data Rate Signaling Level sv i GMCH 2x AGF YES Yea 4x AGP Yes Ho
51. een configured Configuring the hard disk drive controller next Any initialization required after the option ROM test has completed Configuring the timer data area and printer base address next ECB 865 User s Manual 101 User s Manual RS 232 base address hdi required Initialization before the Coprocessor test next 9C j Required initialization before the Coprocessor test is over Initializing the Coprocessor next Coprocessor initialized Going to do any initialization after Coprocessor test 9E Initialization after the Coprocessor test is complete Checking the extended Keyboard keyboard ID and Num Lock key next Issuing the keyboard ID command next Displaying any soft errors next A3 Soft error display complete Going to set keyboard typematic rate A4 Keyboard typematic rate set To program memory wait states A3 i Goi A4 i enabling parity and the NMI next passing control to the adaptor ROM at E000 next completed Passing control to the adaptor ROM at E000h next A9 the system configuration next Building the multiprocessor table if necessary AC Uncompressing the DMI data and initializing DMI POST next The system configuration is displayed Returned from adaptor ROM at E000h control Performing any initialisation required after the E000 option ROM had control next B1 Copying any code to specific areas Code copying to specific areas is done Passing control to INT 19 h boot loader next
52. emory test below 1MB next Determining the amount of memory above 1MB memory next Data initialized Checking for memory wraparound at 0 0 and finding the total System memory size next ECB 865 User s Manual 99 User s Manual The amount of memory above 1MB has been found and verified Checking for a soft reset and clearing the memory below 1MB for the Soft reset next If this is a power on situation going to checkpoint 4Eh next the memory above 1MB next memory size next Going to checkpoint 52h next Displaying the first 64KB memory size next Performing the sequential and random memory test next 50 Memory testing initialization below 1MB completed Going to adjust displayed memory size for relocation and shadowing The memory size display was adjusted for relocation and shadowing Testing the memory above 1MB next The memory above 1MB has been tested and initialized Saving the memory size information next The memory size information and the CPU registers are saved Entering real mode next 54 Shutdown was successful The CPU is in real mode Disabling the Gate A20 line parity and the NMI next The A20 address line parity and the NMI are disabled Adjusting the memory sizedepending on relocation and shadowing next the Hit DEL message next displayed Staring the DMA and interrupt controller test next DMA 1 base register test passed To do DMA 2 base register test DMA 2 base register test passed
53. ends on the hard disk type normally active low IDE Reset This signal resets all the devices that are attached to the IDE interface IRQ14 15 Interrupt line from hard disk Connected directly to PC AT bus 30 ECB 865 User s Manual ECB 865 3 11 8 Floppy Connector J6 DSKCHG DRVDENO DRVDEN1 WD WE TRAKO wT OO OINI OI OO LOT BR 9O c Q OQ QQ Ajaj Q Q Q Q Q Q Q Q Q Q Q a Z Z Z Z Z EZEZ EZ Zz Zz Z Z Z Zz ECB 865 User s Manual 31 User s Manual 3 11 9 Signal Description Floppy Connector J6 RDATA The read data input signal from the FDD WD Write data This logic low open drain writes pre compensation serial data to the selected FDD An open drain output E Write enable An open drain output MOA Motor A On When set to 0 this pin enables disk drive 0 This is an open drain output DSA Drive Select A When set to 0 this pin enables disk drive A This is an open drain output DSB Drive Select B When set to 0 this pin enables disk drive B This is an open drain output SIDE1 This output signal selects side of the disk in the selected drive DIR Direction of the head step motor An open drain output Logic 1 outward motion Logic 0 inward motion MOB Motor B On When set to 0 this pin enables disk drive 1 This is an open drain output another track density 500 1000kbps at high level has been selected EAE 0 This Schmitt triggered input from t
54. ent History Revision Date By Comment Feb 02 Initial Release Ver D l aM Evalue Technology Inc ECB 865 1 Manual Objectives This manual describes in detail the Evalue Technology ECB 865 Single Board We have tried to include as much information as possible but we have not duplicated information that is provided in the standard IBM Technical References unless it proved to be necessary to aid in the understanding of this board The manual is sectioned and includes a User s Guide that will help the non technical user to get the unit up and running A Troubleshooting Guide is also included to help when things go wrong We strongly recommend that you study this manual carefully before attempting to interface with ECB 865 or change the standard configurations Whilst all the necessary information is available in this manual we would recommend that unless you are confident you contact your supplier for guidance Please be aware that it is possible to create configurations within the CMOS RAM that make booting impossible If this should happen clear the CMOS settings see the description of the Jumper Settings for details If you have any suggestions or find any errors concerning this manual and want to inform us of these please contact our Customer Service department with the relevant details ECB 865 User s Manual 1 User s Manual 2 Introduction 2 1 System Overview The ECB 865 is an all in one Full size Pentium III
55. er This driver may be installed in two ways e During the installation process where the network may be configured as an integrated part In this case the adapter may be chosen or auto detected when the network adapter is to be installed e n the network settings after Windows NT 4 0 is installed The following procedures describe the steps to install the Network adapter driver on Windows NT 4 0 1 Click the Starf button on the task bar Select Settings and Control Pane to start the control panel as shown below J Control Panel DE x B c File Edit View Help a Accessibility Add Remove Console Date Time Devices Options Programs om o s Display Fonts Internet Keyboard Modems d gt A F Mouse Multimedia PC Card Ports PCMCIA i Server Services x System Tape Devices Telephony u i Configures network hardware and software 7 Hu 11111 2 2 8 LLL 74 ECB 865 User s Manual ECB 865 2 Double click the Network icon and click the Adapters tab on the following window A window as the one shown below should now appear Enare m Update Item pte ss 3 Click the Aad button and the following window should appear Select Network Adapter 3Com 3C508 ISA 16 bit Ethernet Adapter EF 3Com Etherlink Il Adapter also 11716 and II 16 TP Big 3Com Etherlink IIl IS amp PCMCIA Adapter EF 3Com EtherLink IIl P
56. experienced electronics personnel should open the PC chassis 3 2 2 Caution Always ground yourself to remove any static charge before touching the board Modern electronic devices are very sensitive to static electric charges As a safety precaution use a grounding wrist strap at all times Place all electronic components in a static dissipative surface or static shielded bag when they are not in the chassis ECB 865 User s Manual 11 User s Manual 3 3 Socket 370 Processor 3 3 4 Installing Celeron Pentium IIl Coppermine Tualatin CPU Liftthe handling lever of CPU socket outwards and upwards to the other end a Align the processor pins with pin holes on the socket Make sure that the notched corner or dot mark pin 1 of the CPU corresponds to the socket s bevel end Then press the CPU gently until it fits into place If this operation is not easy or smooth don t do it forcibly You need to check and rebuild the CPU pin uniformly a Push down the lever to lock processor chip into the socket a Follow the installation guide of cooling fan or heat sink to mount it on CPU surface and lock it on the socket 370 Be sure to follow particular CPU speed and voltage type to adjust the jumper settings properly 3 3 2 Removing CPU m Unlock the cooling fan first m Liftthe lever of CPU socket outwards and upwards to the other end a Carefully lift up the existing CPU to remove it from the socket a Follow the steps of in
57. for USB channel 0 Clock is transmitted along with the data using NRZI encoding The signalling bit rate is up to 12 Mbs IRTX Over Current Off ECB 865 User s Manual 39 User s Manual 3 11 25 Signal Configuration Fast amp Standard IrDA Connector J15 IRRX Infrared Receiver input IRTX Infrared Transmitter output 3 11 26 ATX Power Controller J16 TL Signal PIN Power Good 1 5V Stand b 2 Power On 3 L4 3 11 27 Smart Card Interface J17 PIN Signal CH2 CH1 Signal one SCRPRES 9 NC 9 SCRIO ef wc 6 scRRST ES NC NC 40 ECB 865 User s Manual ECB 865 3 11 28 10 100 BASE Tx Ethernet Connector J18 J20 3 11 29 Signal Description 10 100Base Tx Ethernet Connector J18 J20 TXD TXD Ethernet 10 100Base Tx differential transmitter outputs RXD RXD Ethernet 10 100Base Tx differential receiver inputs ECB 865 User s Manual 41 User s Manual 3 11 30 CRT Connector J22 GREEN 2 gm Zz ANA GND 2 a L peo uH EA BLUE s 13 nsvwc Zz O oO o O1 gt 3 11 31 HSYNC CRT horizontal synchronisation output VSYNC CRT vertical synchronisation output DDCCLK Display Data Channel Clock Used as clock signal to from monitors with DDC interface DDCDAT Display Data Channel Data Used as data signal to from monitors with DDC interface Signal Descrip
58. h button Update Device Driver Wizard m J Chips and Tech 69000 PCI Windows has finished installing an updated driver for your hardware device E Cancel 9 To complete the display driver installation reboot the computer by clicking the Yes button in the window shown below System Settings Change gt To finish setting up your new hardware you must restart your 7 computer Do you want to restart your computer now 82 ECB 865 User s Manual ECB 865 10 Further configuration of the display adapter may be made from the Display Properties window follow step 1 above The Settings tab allows you to change resolution number of colours etc as shown below fences g im Mm Em dme rriv drum eror ru ECB 865 User s Manual 83 User s Manual 5 2 2 Windows NT 4 0 Display Installation A display driver for Windows NT 4 0 is supplied with the system on the Supporting CD ROM The driver installation may be performed by following steps shown below 1 Start the control panel by clicking the Starf button click Settings and Control Panel from the sub menu Double click the Display icon in the control panel as shown below J Control Panel File Edit View Help Accessibility Add Remove Console Date Time Options Programs 5 Internet Keyboard Licensing m ds Multimedia Network ODBC 9 2 5 PC Cad Parts Changes display settings
59. he disk drive is active low when the head is positioned over the outermost track INDEX This Schmitt triggered input from the disk drive is active low when the head is positioned over the beginning of a track marked by an index hole WP Write protected This active low Schmitt input from the disk drive indicates that the diskette is write protected DSKCHG _ Diskette change This signal is active low at power on and whenever the diskette is removed 32 ECB 865 User s Manual ECB 865 3 11 10 ATX Power Button Connector J8 PIN Power Button Control Signal 3 11 11 Parallel Port Connector J11 PIN ERE rare 9 10 ECB 865 User s Manual 33 User s Manual 3 11 12 DB25 Parallel Port Connector J11 m a a a a a a a Zz Zz Zz zZ Z Z Zz q q xn CN CN CN CN CN CN ex CN eo t Ke W al laj Ial TA A Q n me Mrs re Ja a a 34 ECB 865 User s Manual ECB 865 3 11 13 Signal Description Parallel Port Connector J11 The following signal description covers the signal definitions when the parallel port is operated in standard centronic mode The parallel port controller also supports the fast EPP and ECP modes Please refer to reference 2 for further information PD7 0 Parallel data bus from PC board to printer The data lines are able to operate in PS 2 compatible bi directional mode active high input on this pin indicates that the printer is selected This pin
60. information or questions that apply to your problem and with the product close at hand call your dealer Our dealers are well trained and ready to give you the support you need to get the most from your Evalue s products In fact most problems reported are minor and are able to be easily solved over the phone In addition free technical support is available from Evalue s engineers every business day We are always ready to give advice on application requirements or specific information on the installation and operation of any of our products Please do not hesitate to call or e mail us Headquarters Europe Branch Office Evalue Technology Inc Evalue Europe A S 5F 7 No 130 Chien Kang Road Nordre Strandvej 119C Chung Ho City Taipei 3150 Hellebaek Taiwan Denmark Tel 886 2 2228 6111 Tel 45 7025 0310 Fax 886 2 2228 6228 Fax 45 4975 5026 ttp www evalue tech com E mail service Qevalue tech com http www evalue tech com E mail Service eurooe evalue tech com r aAaANuA vA M Evalue Technology Inc User s Manual Product Warranty Evalue warrants to you the original purchaser that each of its products will be free from defects in materials and workmanship for two years from the date of purchase This warranty does not apply to any products which have been repaired or altered by persons other than repair personnel authorized by Evalue or which have been
61. is pulled high internally internally BE active high input indicates that the printer is not ready to receive data This pin is pulled high internally ACK An active low input on this pin indicates that the printer has received data and is ready to accept more data This pin is pulled high internally INIT Output line for the printer initialization This pin is pulled high internally oes active low output from this pin causes the printer to auto feed a line after a line is printed This pin is pulled high internally WEE active low input on this pin indicates that the printer has encountered an error condition This pin is pulled high internally PE An active high input on this pin indicates that the printer has detected the end of the paper This pin is pulled high internally 3 11 14 Box Header Serial Port 1 Serial Port 2 Connector in RS 232 J9 J12 ECB 865 User s Manual 35 User s Manual 3 11 15 Serial Port 1 Serial Port 2 with External DB9 Connector J9 J12 Signal Pi i EMEN Es Do Ll Serial output This signal sends serial data to the communication link The signal is set to a marking state on hardware reset when the transmitter is empty or when loop mode operation is initiated Data Terminal Ready This signal indicates to the modem or data set that the on board UART is ready to establish a communication link pn M MALLA 36 ECB 865 User s Manual ECB 8
62. k Setup Boot To 08 2 No System BIOS Cacheable Enabled C000 16k Shadow Disabled C400 16k Shadow Disabled C800 16k Shadow Disabled CC00 16k Shadow Disabled ESC Exit T Sel DOOO 16k Shadow Disabled 4 PgUp PgDn Modi fy D400 16k Shadow Disabled F1 Help F2 F3 Color 4 3 2 1 Quick Boot Set this option to Enabled to instruct AMIBIOS to boot quickly when the computer is powered on Disabled AMIBIOS tests all system memory AMIBIOS waits up to 40seconds for a READY signal from the IDE hard disk drive AMIBIOS waits for 0 5 seconds after sending a RESET signal to the IDE drive to allow the IDE drive time to get ready again AMIBIOS checks for a lt Del gt key press and runs AMIBIOS Setup if the key has been pressed Enabled AMIBIOS does not test system memory above 1 MB AMIBIOS does not wait up to 40 seconds for a READY signal from the IDE hard disk drive If a READY signal is not received immediately from the IDE drive AMIBIOS does not configure that drive AMIBIOS does not wait for 0 5 seconds after sending a RESET signal to the IDE drive to allow the IDE drive time to get ready again You cannot run AMIBIOS Setup at system boot because there is no delay for the Hit lt Del gt to run Setup message 54 ECB 865 User s Manual ECB 865 4 3 2 2 1 2 3 Boot Device These options determine the sequence of boot drives floppy drive A hard disk drive C or CD ROM drive that the AMIBIOS attempts to boot from after AMIBIOS POS
63. l Port 2 Connector in RS 232 J9 J12 8 11 15 Serial Port 1 Serial Port 2 with External DB9 Connector J9 J12 8 11 16 Signal Description Serial Port 1 Serial Port 2 in RS 232 Mode J9 J12 3 11 1 Box Header Serial Port 1 Serial Port 2 Connector in RS 422 J9 J12 8 11 18 Signal Description Serial Port 1 Serial Port 2 in RS 422 Mode J9 J12 8 11 19 Box Header Serial Port 1 Serial Port 2 Connector in RS 485 J9 J12 3 11 20 Signal Description Serial Port 1 Serial Port 2 in RS 485 Mode J9 J12 8 11 22 Signal Description USB Connector J13 J19 3 11 23 CPU Fan and System Fan Connector J14 J25 3 11 24 Fast amp Standard IrDA Connector J15 8 11 25 Signal Configuration Fast amp Standard IrDA Connector J15 3 11 26 ATX Power Controller J16 BASE Ix Ethernet Connector J18 J20 3 11 29 Signal Description 10 100Base Tx Ethernet Connector J18 J20 8 11 30 CRT Connector J22 83 11 31 Signal Description CRT Connector 8 11 32 Internal Keyboard Connector J24 8 11 33 PS 2 Keyboard Connector J26 8 11 34 Signal Description Int amp PS 2 Keyboard Connector J24 J26 8 11 35 PS 2 Mouse Connector J26 8 11 36 Signal Description PS 2 Mouse Connector J26 8 11 37 Proprietary PCI Connector J21 3 11 38 Signal Description Proprietary PCI Connector J21 AMI BIOS SETUP 4 1 Entering Evalue Technology Inc User s Manual bo O OOM uuU Evalue Technology Inc ECB 865 Document Amendm
64. linked to external devices such as hard disk drives keyboard mouse or floppy drives In addition the board has a number of jumpers that allow you to configure your system to suit your application The following tables list the function of each of the board s jumpers and connectors Jumpers Label Function Note JP1 Serial port RS 232 422 485 select 3 x 2 header pitch 2 54mm JP2 JP5 Serial port RS 232 422 485 select 3 x 1 header pitch 2 54mm JP6 Watchdog timer select 2 x 1 header pitch 2 54mm JP9 Clear CMOS 3 x 1 header pitch 2 54mm JP10 Watchdog timer select 3 x 2 header pitch 2 54mm JP11 M Systems DiskOnChip memory address 4 x 2 header pitch 2 54mm select JP12 Watchdog timer select 2 x 1 header pitch 2 54mm JP13 Proprietary PCI Bus Master Selection 4 x 2 header pitch 2 54mm 18 ECB 865 User s Manual ECB 865 Connectors Label Function Note J1 System reset connector 2 x 1 header pitch 2 54mm J2 External speaker connector 4 x 1 header pitch 2 54mm J3 Keyboard lock and power indicator 4 x 1 header pitch 2 54mm connector J4 Primary IDE Secondary IDE active 2 x 1 header pitch 2 54mm indicator connector J5 Primary IDE connector 20 x 2 header pitch 2 54mm J6 Floppy connector 17 x 2 header pitch 2 54mm J7 AT power button connector J8 ATX power button interface to backplane 2 x 1 header pitch 2 54mm J9 Serial port 1 conne
65. ll the driver for the Ethernet controller is to use the plug and play system of Windows 9x The following procedures illustrate how the installation can be done 1 If a driver for the Ethernet controller is already installed it must be removed first This can be done by following the steps shown below e Click the Starf button click on Settings and on Control panel to open the control panel Your display should now look as below possibly with different size and icons Ek Ed ees Help ure s lene ae Fs sisi hoosi idhe Dipl Find F nat phone Plead NUES Phere F amp a m 2 a 2 D s Farsi Fetoed didadamdFams Hers Mad bioder Mig rag H uk erha Paois Vai coeradr Cynder Scared EE ale e Double click the System icon highlighted above e Select the Device Manager tab ECB 865 User s Manual 69 User s Manual e f the Network adapters line is present expand the line and remove the PCI Ethernet Adapter This is done by selecting the line and clicking the Remove button Before removal of the adapter s your screen might look like this System Properties Display adapters Be Floppy disk controllers Hard disk controllers 24 Infrared devices H E Keyboard Monitors Mouse E Network adapters i Intel 8255x based PCI Ethernet Adapter 10 100 a Ports COM amp LPT System devices Universal Serial Bus controllers e When all adapters are remove
66. mer WDT function is enabled a system reset will be generated unless an application triggers the timer periodically within time out period This allows the system to restart in an orderly way in case of any abnormal condition is found An optional two port WDT is provided on ECB 865 This WDT comes with 8 possible ranges of time intervals from 500ms to 64sec which can be adjusted by setting jumper positions It could be enabled and programmed by reading I O port 0533H or 0543H to issue trigger continuously and disabled by reading I O port 0033H or 0343H A tolerance of 3096 timer limit must be considered For instance if the time out interval is set to 1 second the WDT trigger command must be issued within 700ms at least The below example gives you a reference algorithm for WDT programming via I O port 0533H and 0033H in your application programs Enable WDT MOV DX 0533H IN AL DX Re trigger WDT MOV DX 0533H IN AL DX Disable WDT MOV DX 0033H IN AL DX 16 ECB 865 User s Manual 3 9 Jumper amp Connector 3 9 1 Jumper amp Connector Layout JP3 BH JP5 J15 JP2 RR JP4 J6 JP1 B J11 J18 J13 Js J1 JP6 J17 J18 J3 DIMM1 2 3 4 J2 J7 1 J1 Hf J8 49412 ECB 865 J18 J20 J22 J26 J24 n I P c ms b e m ply Binu gn dod c Om Go 99 EL Socket 370 J14 ECB 865 User s Manual 17 User s Manual 3 9 2 Jumper amp Connector List Connectors on the board are
67. mory SIMMs If the system still beeps replace the memory 6 times Try a different keyboard or replace the keyboard fuse if the keyboard has one 8 times There is an error on the Video adapter or the Video RAM needs a new BIOS ROM chip beeps replace the cache de EE 4 5 7 or l45 7 ori0 tims Fatal error 0 0 0 error If the error occurs after the display device is initialised an error message is displayed ECB 865 User s Manual 95 User s Manual APPENDIX D AMIBIOS POST Check Point List AMIBIOS provides all IBM standard Power On Self Test POST routines as well as enhanced AMIBIOS POST routines The POST routines support CPU internal diagnostics The POST checkpoint codes are accessible via the Manufacturing Test Port I O port 80h Whenever a recoverable error occurs during the POST the system BIOS will display an error message describing the message and explaining the problem in detail so that the problem can be corrected During the POST the BIOS signals a checkpoint by issuing one code to I O address 80H This code can be used to establish how far the BIOS has executed through the power on sequence and what test is currently being performed This is done to help troubleshoot faulty system board If the BIOS detects a terminal error condition it will halt the POST process and attempt to display the checkpoint code written to port 80H If the system hangs before the BIOS detects the terminal error the value
68. nes one interrupt line for a single function device and up to four interrupt lines for a multi function 7 device or connector For a single function device only INTA may be used while the other three interrupt lines have no meaning PIRQ is connected to INTB ECB 865 User s Manual 49 User s Manual 4 AMI BIOS Setup ECB 865 is equipped with the AMI BIOS stored in Flash ROM This BIOS has a built in Setup program that allow users to modify the basic system configuration easily This type of information is stored in CMOS RAM so that it is retained during power off periods 4 4 Entering Setup Turn on or reboot the computer When the message Hit lt DEL gt appears if you want to run SETUP press lt DEL gt key immediately to enter BIOS Setup program If the message disappears before you respond but you still wish to enter Setup please restart the system to try COLD START again by turning the system OFF and then ON or touch the RESET button You may also restart from WARM START by pressing Ctrl lt Alt gt and lt Del gt keys simultaneously If you do not press these keys at the right time and the system will not boot an error message will be displayed and you will again be asked to Press F1 to Run SETUP or Resume In HIFLEX BIOS Setup you can use the keyboard to choose among options or modify the system parameters to match the options with yours system The table below will show you all of keystr
69. oke functions in BIOS Setup _Editing Keys Function Enter Select in the current field Close the current operation and return to previous lt Esc gt level lt PgUp gt Returns to the previous option lt PgDn gt Advances to the next option lt F2 gt lt F3 gt Select background color Show Save current settings and exit Y N in main menu lt F10 gt 50 ECB 865 User s Manual ECB 865 4 2 AMI BIOS Setup Main Menu Once you enter ECB 865 AMI BIOS COMS Setup Utility the Main Menu Standard CMOS Setup will appear on the screen The Main Menu allows you to select from eleven Setup functions and two exit choices Use arrow keys to switch the items and press Enter key to accept or enter the sub menu RMIBIOS HIFLEX SETUP UTILITY VERSION 1 37 CC 2001 American Megatrends Inc fill Rights Reserved Standard CMOS Setu Advanced CMOS Setup Advanced Chipset Setup Power Management Setup PCI Plug and Play Setup Peripheral Setup Harduare Monitor Setup Ruto Detect Hard Disks Change User Passuord Change Supervisor Password Auto Configuration with Optimal Settings Auto Configuration with Fail Safe Settings Save Settings and Exit Exit Without Saving Standard CMOS setup for changing time date hard disk type etc ESC Exit T8 Sel F2 F3 Color F10 Save amp Exit Note It is strongly recommended to reload Optimal setting if CMOS is lost or BIOS is updated ECB 865 User s Manual 51 U
70. on operation at normal speed BiDir Bi direction operation at normal speed The parallel port can be used with devices that adhere to the Enhanced Parallel Port EPP specification EPP uses the existing parallel port signals to provide asymmetric bi directional data transfer driven by the host device The parallel port can be used with devices that adhere to the Extended Capabilities Port ECP specification ECP uses the DMA protocol to achieve data transfer rates up to 2 5 Megabits per second ECP provides symmetric bi directional communicational ECB 865 User s Manual 65 User s Manual 4 3 6 4 2 Parallel Port IRQ This option is only valid if the Onboard Parallel Port option is not set to Disabled This option sets the IRQ used by the parallel port 4 3 6 4 3 Parallel Port DMA Channel This option is only available if On Board Parallel Port is set to fixed I O address and the setting of Parallel Port Mode is ECP This option sets the DMA channel used by ECP capable parallel port 4 3 6 5 On Chip IDE This option specifies the onboard IDE controller channels that will be used The settings are Primary Secondary Both or Disabled 66 ECB 865 User s Manual ECB 865 4 3 7 Hardware Monitor Setup Defaults This setup describes current CPU surface temperature status detected from hardware monitor sensor The status showed on screen will include ANIBIOS SETUP HARDWARE MONITOR SETUP C 2001 American Megatrends Inc
71. or PCI device expansion 4 ECB 865 User s Manual ECB 865 Mechanical and Environmental e Power Supply Voltage 5V 4 75V to 5 25V 12V 11 4V to 12 6V and 12V 11 4V to 12 6V e Typical Power Requirement 5V 6 5A 12V 140mA 12V 30mA w Intel Celeron 466MHz CPU and 128MB SDRAM e Operating Temperature 32 to 140 F 0 to 60 C e Board Size 13 3 L x 4 8 W 338mm x 122mm e Weight 0 5 Kg See SSS I ECB 865 User s Manual 5 User s Manual 2 3 Architecture Overview The following block diagram shows the architecture and main components of ECB 865 Two major chipsets on board are the 82815E Graph Memory Control Hub and 82801BA ICH2 These two devices provide interface to Socket370 processor supports CRT display SDRAM with ECC PCI bus interface ACPI compliant power management USB port SMBus communication and Ultra DMA 33 66 100 IDE Bus Master The onboard super I O chip IT8712F A supports PS 2 Keyboard Mouse two 16C550 UARTs FDC Parallel and Infrared interface In addition the onboard Intel 82559 10 100BASE TX Ethernet controller delivers high speed data transfers over the PCI bus Celeron Pentium IIl Processor FC Socket 370 Intel 82815E Memory CRT GMCH 570 BSS SDRAM DIMM 544 BGA UDMA33 66 100 Card RS 232 mai veetoo mecha zat 166 100 ITE IT8712F A EORR 10 ro USB 4 2 Ports PS 2 KB amp Mouse IrDA IDE 1
72. ough the Serial Port 2 s DTR signal Modem control register The data transmitted will simultaneously be received the in Serial Port 2 Receiver Buffer Register CTS RTS jBi directional control signal pair The level of this differential signal pair could be read from the Serial Port 1 s CTS signal Modem control register The level of this differential signal pair could be controlled through the Serial Port 2 s RTS signal Modem control register Warning Do not select a mode different from the one used by the connected peripheral as this may damage CPU board and or peripheral The transmitter drivers in the port are short circuit protected by a thermal protection circuit The circuit disables the drivers when the die temperature reach 150 C RS 422 mode is typically used in point to point communication Data and control signal pairs should be terminated in the receiver end with a resistor matching the cable impedance typ 100 120 Q The resistors could be placed in the connector housing RS 485 mode is typically used in multi drop applications where more than 2 units are communicating The data and control signal pairs should be terminated in each end of the communication line with a resistor matching the cable impedance typical 100 120 Stubs to substations should be avoided 38 ECB 865 User s Manual ECB 865 3 11 21 USB Connector J13 J19 PIN Signal CH2 CH1 Signal Differential bi directional data signal
73. output signal is connected to the corresponding signal on the Secondary IDE connector If the IDE signals are configured for Primary Master and Primary Slave these signals are used for the Primary Slave connector SDCS3 Secondary Chip Select for 370H 377H Range For ATA control register block If the IDE signals are configured for Primary and Secondary this output signal is connected to the corresponding signal on the Secondary IDE connector If the IDE signals are configured for Primary Master and Primary Slave these signals are used for the Primary Slave connector PDD 15 0 Primary Disk Data 15 0 These signals are used to transfer data to or from the IDE device If the IDE signals are configured for Primary and Secondary these signals are connected to the corresponding signals on the Primary IDE connector If the IDE signals are configured for Primary Master and Primary Slave this signal is used for the Primary Master connector SDD 15 0 Secondary Disk Data 15 0 These signals are used to transfer data to or from the IDE device If the IDE signals are configured for Primary and Secondary these signals are connected to the corresponding signals on the Secondary IDE connector If the IDE signals are configured for Primary Master and Primary Slave these signals are used for the Primary Slave connector ECB 865 User s Manual 27 User s Manual Primary Disk IO Read In normal IDE this is the command to the IDE device that it may d
74. read Spectrum Disabled 5x 9x 3 3 4 4 5 5 6 6 7 7 8 ESC Exit T Sel PgUp PgDn Modi fy F1 Help F2 F3 Color 4 3 3 4 CPU Ratio Selection This option provides different CPU clock Ratios from 3 0x to 8 0x When you change the ratio the overall CPU speed will change accordingly In the default setting of Safe Mode the CPU operates its own original clock rate automatically Note It is strongly recommended to set the default setting of Safe Mode Selecting the higher CPU clock rate may get higher CPU speed but it will cause the system unstable the damages of the system and even burning the CPU 4 3 3 2 ICH Delayed Transaction ICH2 equips an embedded 32 bit post write buffer to support system delay transaction cycles This option provides the compliance with PCI specification version 2 1 devices ECB 865 User s Manual 57 User s Manual 4 3 3 3 Memory Hole This option allows the end user to specify the location of a memory hole for memory space requirement from ISA bus cards 4 3 3 4 DRAM Cycle time SCLKs This option selects the number of SCLKs for an access cycle 4 3 3 5 CAS Latency SCLKs This option controls the number of SCLKs between the time a read command is sampled by the SDRAM and GMCH 82815E samples corresponding data from the SDRAMs 4 3 3 6 SDRAM RAS to CAS Delay This option controls the number of SCLKs SDRAM Clock from a row activate command to a read or write command
75. rive data onto the PDD 15 0 lines Data is latched by PIIX4 on the negation edge of PDIOR The IDE device is selected either by the ATA register file chip selects PDCS1 PDCS3 and the PDA 2 0 lines or the IDE DMA slave arbitration signals PDDACK In an Ultra DMA 33 read cycle this signal is used as DMARDY which is negated by the PIIX4 to pause Ultra DMA 33 transfers In an Ultra DMA 33 write cycle this signal is used as the STROBE signal with the drive latching data on rising and falling edges of STROBE If the IDE signals are configured for Primary and Secondary this signal is connected to the corresponding signal on the Primary IDE connector If the IDE signals are configured for Primary Master and Primary Slave this signal is used for the Primary Master connector Secondary Disk IO Read In normal IDE mode this is the command to the IDE device that it may drive data onto the SDD 15 0 lines Data is latched by the PIIX4 on the negation edge of SDIOR The IDE device is selected either by the ATA register file chip selects SDCS1 SDCS3 and the SDA 2 0 lines or the IDE DMA slave arbitration signals SDDACK In an Ultra DMA 33 read cycle this signal is used as DMARDY which is negated by the PIIX4 to pause Ultra DMA 33 transfers In an Ultra DMA 33 write cycle this signal is used as the STROBE signal with the drive latching data on rising and falling edges of STROBE If the IDE signals are configured for Primary and Second
76. rror is for reporting address parity errors data parity errors on the Special Cycle command or any other system error where the result will be catastrophic If an agent does not want a non maskable interrupt NMI to be generated a different reporting mechanism is required SERR is pure open drain and is actively driven for a single PCI clock by the agent reporting the error The assertion of SERR is synchronous to the clock and meets the setup and hold times of all bused signals However the restoring of SERR to the deasserted state is accomplished by a weak pullup same value as used for s t s which is provided by the system designer and not by the signaling agent or central resource This pullup may take two to three clock periods to fully restore SERR The agent that reports SERR s to the operating system does so anytime SERR is sampled asserted HEEL c 0v 48 ECB 865 User s Manual ECB 865 3 11 38 6 Interrupts Interrupts on PCI are optional and defined as level sensitive asserted low negative true using open drain output drivers The assertion and deassertion of INTx is asynchronous to CLK A device asserts its INTx line when requesting attention from its device driver Once the INTx signal is asserted it remains asserted until the device driver clears the pending request When the request is cleared the device deasserts its INTx signal PCI defi
77. s connected to the corresponding signal on the Secondary IDE connector If the IDE signals are configured for Primary Master and Primary Slave these signals are used for the Primary Slave connector This is a Schmitt triggered input Primary Disk DMA Request This input signal is directly driven from the IDE device DMARQ signal It is asserted by the IDE device to request a data transfer and used in conjunction with the PCI bus master IDE function It is not associated with any AT compatible DMA channel If the IDE signals are configured for Primary and Secondary this signal is connected to the corresponding signal on the Primary IDE connector If the IDE signals are configured for Primary Master and Primary Slave this signal is used for the Primary Master connector Secondary Disk DMA Request This input signal is directly driven from the IDE device DMARQ signal It is asserted by the IDE device to request a data transfer and used in conjunction with the PCI bus master IDE function It is not associated with any AT compatible DMA channel If the IDE signals are configured for Primary and Secondary this signal is connected to the corresponding signal on the Secondary IDE connector If the IDE signals are configured for Primary Master and Primary Slave these signals are used for the Primary Slave connector Primary DMA Acknowledge This signal directly drives the IDE device DMACK signal It is asserted by PIIX4 to indicate to IDE DMA slave
78. s the following processors a Intel Pentium Ill processor based on 0 18 micron technology CPUID 068xh These processors support the AGTL bus interface Intel Celeron processor based on 0 18 micron technology CPUID 068xh This applies to Celeron 533A MHz and 566 MHz processors These processors support the AGTL bus interface m Future 0 13 micron socket 370 processors These processors support the AGTL bus interface The 82815 GMCH along with the 82801BA ICH2 provide the basic functionality and buses of the system a Interface to SDRAM 64 bit data bus Up to 3 double sided DIMMs at 100 MHz system memory bus Up to 2 double sided or 3 single sided DIMMs at 133 MHz system memory bus a PCI Rev 2 2 compliant with support for 33 MHz PCI operations Supports up to 6 Req Gnt pairs m System Management Bus SMBus compatible with most I2C devices a Integrated IDE controller support Ultra ATA 100 66 33 with two 40 pin connectors m 2 USB ports integrated in ICH2 a Integrated LAN controller a AC 97 2 1 compliant link for audio and telephony codecs up to 6 channels Low Pin Count LPC interface Firmware Hub FWH interface support ECB 865 User s Manual 7 User s Manual 2 3 2 DRAM Interface The GMCH integrates a system memory controller that supports a 64 bit 100 133 MHz SDRAM array The only DRAM type supported is industry standard Synchronous DRAM SDRAM The SDRAM controller interface is fully configurabl
79. ser s Manual 4 3 CMOS Setup Reference Table This Setup reference table includes all the Optimal Failsafe and other options setting in each BIOS setup item It is very easy to take a look for crossing reference If you want to go details you can directly refer to item description in sub section 4 3 4 Standard CMOS Setup Menu This Setup page includes all the items in standard CMOS Setup Use the arrow keys to highlight the item and then use the lt PgUp gt lt PgDn gt or lt gt lt gt keys to select the value or number you want in each item and press Enter key to certify it Follow command keys in CMOS Setup table to change Date Time Drive type and Boot Sector Virus Protection Status RMIBIOS SETUP STANDARD CMOS SETUP C 2001 American Megatrends Inc ALl Rights Reserved Date Cmm dd yyyy Mon Dec 31 2001 Base Memory 0 KB Time Chh mm ss 12 20 52 Extd Memory MB Floppy Drive A 1 44 MB 3 Floppy Drive B Hot Installed LBA Blk PIO 32Bit Type Size Cyln Head WPcom Sec Mode Mode Mode Mode Pri Master Auto Off Pri Slave Auto Off Sec Master Auto Off Sec Slave off Boot Sector Virus Protection Disabled ESC Exit T Sel PgUp PgDn Modi fy F1 Help F2 F3 Color 4 3 1 1 Date and Time Configuration Select the Date and Time icon in the Standard CMOS setup The current values for each category are displayed Enter new values through the keyboard or hit the or key to change values 4 3
80. skOnChip 2000 is simply inserted into a 32 pin DIP socket on your platform board and you have a bootable flash disk 10 ECB 865 User s Manual ECB 865 3 Hardware Configuration This chapter explains you the instructions of how to set up your system The additional information shows you how to install M Systems DiskOnChip and program the Watchdog Timer 3 1 Installation Procedure 1 Turn off the power supply 2 Insert the DIMM module be careful with the orientation 3 Insert all external cables for hard disk floppy keyboard mouse USB etc except for flat panel A CRT monitor must be connected in order to change CMOS settings to support flat panel 4 Connect power supply to the board via the PWR1 5 Turn on the power 6 Enter the BIOS setup by pressing the delete key during boot up Use the Auto Configuration with Optimal Settings feature The Peripheral Setup and the Standard CMOS Setup Window must be entered and configured correctly to match the particular system configuration 7 If TFT panel display is to be utilised make sure the panel voltage is correctly set before connecting the display cable and turning on the power 3 2 Safety Precautions 3 2 1 Warning Always completely disconnect the power cord from your chassis or power cable from your board whenever you work with the hardware Do not make connections while the power is on Sensitive electronic components can be damaged by sudden power surges Only
81. stalling a CPU to change to another one or place handling bar to close the opened socket 3 4 Main Memory ECB 865 provides 3 DIMM sockets 168 pin Dual In line Memory Module to support 3 3V SDRAM The maximum memory size is 1 5GB registered type of SDRAM If 100MHz FSB CPU is adopt you have to use PC 100 SDRAM For system compatibility and stability please do not use memory module without brand Both single and double side DIMM module with ECC feature can be used on ECB 865 And it is not necessary to install the DIMM module in order You can install different size of SDRAM module on DIMM1 DIMM2 DIMM3 DIMM4 or all Watch out the contact and lock integrity of memory module with socket it will influence the system s reliability Follow the normal procedure to install your SDRAM module into the DIMM socket Before locking the DIMM module make sure that the memory module has been completely inserted into the DIMM socket Note Please do not change any SDRAM parameter in BIOS setup to increase your system s performance without acquiring technical information in advance 12 ECB 865 User s Manual ECB 865 3 5 M Systems DiskOnChip Flash Disk ECB 865 reserves a 32 pin DIP socket to support M Systems DiskOnChip flash disk up to 288 MB The DiskOnChip is based on pure ISA bus and without PnP Plug and Play function Before the installation make sure that the DiskOnChip I O address jumper is set properly to prevent the I O resource
82. subject to misuse abuse accident or improper installation Evalue assumes no liability under the terms of this warranty as a consequence of such events Because of Evalue s high quality control standards and rigorous testing most of our customers never need to use our repair service If any of Evalue s products is defective it will be repaired or replaced at no charge during the warranty period For out of warranty repairs you will be billed according to the cost of replacement materials service time and freight Please consult your dealer for more details If you think you have a defective product follow these steps 1 Collect all the information about the problem encountered For example CPU type and speed Evalue s products model name hardware amp BIOS revision number other hardware and software used etc Note anything abnormal and list any on screen messages you get when the problem occurs 2 Call your dealer and describe the problem Please have your manual product and any helpful information available 3 If your product is diagnosed as defective obtain an RMA return material authorization number from your dealer This allows us to process your good return more quickly 4 Carefully pack the defective product a complete Repair and Replacement Order Card and a photocopy proof of purchase date such as your sales receipt in a shippable container A product returned without proof of the purchase date is not eligible for
83. tion CRT Connector J22 RED Analog output carrying the red colour signal to the CRT For 75 o cable impedance GREEN Analog output carrying the green colour signal to the CRT For 75 o cable impedance BLUE Analog output carrying the blue colour signal to the CRT For 75 o cable impedance DIG GND Ground reference for HSYNC and VSYNC ANA GND Ground reference for RED GREEN and BLUE ees 120 M JABMMLLLLLLLLLLLLLLLLLLLLLLLLLLLLAA 42 ECB 865 User s Manual ECB 865 3 11 32 Internal Keyboard Connector J24 Bi directional serial data line used to transfer data from or commands to the PC AT keyboard 3 11 36 Signal Description PS 2 Mouse Connector J26 MCLK Bi directional clock signal used to strobe data commands from to the PS 2 mouse MDAT Bi directional serial data line used to transfer data from or commands to the PS 2 mouse ECB 865 User s Manual 43 User s Manual 3 11 37 Proprietary PCI Connector J21 PIN 12V 1 HsYNC J 9 CLK GND GND AD5 Ap3 fo 5V 5V 44 ECB 865 User s Manual AJN NIN NIN IN Qo o Q or oO1 O1 O1 2 IR I IB LO W1W WW IN IN co Oo IN O N J IN 0 1W ID n O Oo ID IH IM O WIM IBRIN 1O1O M H NM JO 4 Signal AGND AGND E GREEN BLUE GND PIRQ GNT RST 3 3V 3 3V AD30 AD28 N AD26 AD24 IDSEL AD22 AD20 GND AD18 AD16
84. tion specifies the speed at which the system clock runs in thermal trip point The settings are expressed as duty cycle of the STPCLK signal This duty cycle indicates the percentage of time the STPCLK signal is asserted while in the over heat mode 4 3 4 9 CPU Critical Temperature Set this option to monitor CPU thermal trip point defined by user If the System Thermal option in CMOS setup is set to Monitor state and CPU surface temperature is over this critical temperature the system will automatically enter speed down mode 60 ECB 865 User s Manual ECB 865 4 3 4 10 Power Button Function This item is used to handle soft power on off regardless of time counting generally speaking it is 4 sec if you set it to On Off You can easily power on off system by pressing power button toggle switch directly This feature is only available on system with ATX power control interface If you use standard AT power supply this option will be ignored However choose the Suspend setting system will be forced into suspend mode when user turn it off unless you can consecutively press the power button for more than 4 second to get in Soft off function 4 3 4 11 Wake Up on Ring This item will be used to wake up system from remote ringing control under Soft Off condition If you choose Disabled setting the system will be not resumed by modem ring 4 3 4 12 Wake Up on LAN This item will be used to wake up system from remote Network control under
85. troller BAT command result has been verified Next performing any necessary INIT after the K B controller BAT command test F The keyboard command byte is written next Next issuing the pin 23 and 24 blocking and unblocking commands Next checking if the End or Ins keys were pressed during power on To initialize CMOS if the initialize CMOS RAM in every boot is set or the lt End gt key is pressed Going to disable DMA and Interrupt controllers pom video display has been disabled Port B has been initialized Next 2 initialising the chipset 0 3 4 The 8254 timer test will begin next 9 The 8254 timer test is over Starting the memory refresh test next 3 5 7 0 1 1 1 1 1 1 0 0 0 1A The memory refresh line is toggling Checking the 15us on off time next 2 Reading the 8042 input port and disabling the MEGAKEY Green PC feature next Making the BIOS code segment writable and performing 2 2 2 2 any necessary configuration before initializing the interrupt vectors 4 The configuration or setup required before interrupt vector initialization has completed Interrupt vector init is about to begin Interrupt vector initialization is done Clearing the password if the POST DIAG switch is on Any initialization before setting video mode to be done 28 Going for monochrome mode and color mode setting 98 ECB 865 User s Manual ECB 865 tx Bienias em static Output deviceq W
86. upervisor Password Setup This option will force system to check password before running Setup if you have already entered the current user password in Change User Password By that time the system will be only able to boot but deny accessing Setup Always Password prompt appears every boot up The system will not boot and deny access Setup with invalid password The best way is to clear CMOS or try to reload BIOS Setup to boot up system ECB 865 User s Manual 55 User s Manual 4 3 2 11 Boot To OS 2 Set this option to Yes to permit AMIBIOS to run with IBM OS 2 The settings are Yes or No The default setting is No 4 3 2 12 System BIOS Cacheable When this option is set to Enabled the contents of the F0000h system memory segment can be read from or written to L2 cache memory The contents of the F0000h memory segment are always copied from the BIOS ROM to system RAM for faster execution The settings are Enabled or Disabled 4 3 2 13 Shadow Memory from Address C000 DFFF 16K Per Segment Each of segments provides three options Disabled Enabled and Cached for faster adapters ROM execution However this shadow function is Chipset oriented and dependent on system hardware feature In general C000 and C800 will be allocated for VGA BIOS and set to Cached to get higher display performance by shadowing and caching feature If user chooses Enabled setting only BIOS shadow function is active RMIBIOS SETUP ADVANCED C
87. urrent access As an input DEVSEL indicates whether any device on the bus has been selected ECB 865 User s Manual 47 User s Manual 3 11 38 4 3 11 38 5 PERR Arbitration Request indicates to the arbiter that this agent desires use of the bus This is a point to point signal Every master has its own REQ which must be tri stated while RST is asserted Grant indicates to the agent that access to the bus has been granted This is a point to point signal Every master has its own GNT which must be ignored while RST is asserted Error Reporting Parity Error is only for the reporting of data parity errors during all PCI transactions except a Special Cycle The PERR pin is sustained tri state and must be driven active by the agent receiving data two clocks following the data when a data parity error is detected The minimum duration of PERR is one clock for each data phase that a data parity error is detected If sequential data phases each have a data parity error the PERR signal will be asserted for more than a single clock PERR must be driven high for one clock before being tri stated as with all sustained tri state signals There are no special conditions when a data parity error may be lost or when reporting of an error may be delayed An agent cannot report a PERR until it has claimed the access by asserting DEVSEL for a target and completed a data phase or is the master of the current transaction System E
88. ut state In Standby mode some power use is curtailed 4 3 4 5 Suspend Time Out Minute This option is the same as Stand by Time out function These two features will be enabled to monitor power of sub items Display Activity Serial port Parallel Port Floppy Pri HDD and Sec HDD independently It is also used to control CPU throttle running function All of sub items will be ineffective in selection of disabling Stand by Time out or Suspend Time out even if it can be choused by user in BIOS setup menu 4 3 4 6 Throttle Slow Clock Ratio This option specifies the speed at which the system clock runs in power saving modes The settings are expressed as duty cycle of the STPCLK signal This duty cycle indicates the percentage of time the STPCLK signal is asserted while in the throttle mode 4 3 4 7 System Thermal Set this option to Monitor for CPU thermal monitoring and speed down control The system will automatically supervise the CPU environmental temperature If the CPU surface temperature reaches the trip point set in Hardware Monitor Setup the thermal detection will be effective and CPU will run in throttle control manner The overall system performance will be reduced to half This option is a trade off of system performance and stability and configurable by user The default setting is gnore You can choose Monitor setting to enable this thermal function 4 3 4 8 Thermal Slow Clock Ratio This op
89. ve IDE Ignore Secondary Master IDE Monitor Secondary Slave IDE Ignore System Thermal Ignore CPU Critical Temperature 75 C 167 F Power Button Function On OF F Restore on AC Power Loss Last State ESC Exit T Sel Wake Up On Ring Disabled PgUp PgDn Modi fu Wake Up On PME Disabled F1 Help F2 F3 Color 4 3 4 1 ACPI Aware O S This item allows you to enable disable the Advanced Configuration and Power Management ACPI The choice Yes No 4 3 4 2 Power Management APM This item allows you to enable disable the Power Management and the Advanced Power Management functions in following items If you set this function to disable the following items in this page will become to dark grey color and can t be selectable 4 3 4 3 Green PC Monitor Power State This option is used to decide what kind of power states is effective There are three options Stand By Suspend and Off in this feature The Stand By option is to turn off light power by handling of Monitor signals The other Suspend mode is to turn off heavy power And the other one Off state is really to turn off the power of the monitor ECB 865 User s Manual 59 User s Manual 4 3 4 4 Stand by Time Out Minute This option specifies the length of the period of system inactivity while the computer is in Full On power state before the computer is placed in Standby mode When this length of time expires the computer enters Standby Timeo
90. warranty service 5 Write the RMA number visibly on the outside of the package and ship it prepaid to your dealer LA ALLAAZAZAZAZAZAZAZAAAALLLLLLALAALLLLLLAALZZZZII Evalue Technology Inc ECB 865 Packing List Before you begin installing your single board please make sure that the following materials have been shipped a 1 ECB 865 Full size Celeron Pentium III single board a 1 Quick Installation Guide a 1 CD ROM contains the followings User s Manual this manual in PDF file Ethernet driver and utilities VGA drivers and utilities Latest BIOS as of the CD ROM was made a Cable set includes the followings 1IDE HDD cable 40 pin pitch 2 54mm 1 FDD cable 34 pin pitch 2 54mm 1 bracket with one Printer port cable 26 pin pitch 2 54mm and one Serial port cable 10 pin pitch 2 0mm 1 bracket with two Serial port cable 10 pin pitch 2 54mm 1 5 pin to 5 pin keyboard cable for passive backplane connection 1 4 pin ATX power control cable for backplane connection If any of these items are missing or damaged please contact your distributor or sales representative immediately Ver D l aM Evalue Technology Inc User s Manual Evalue Technology Inc ECB 865 11 Power Button Connector J8 5 11 11 Parallel Port Connector J11 3 11 12 DB25 Parallel Port Connector J11 83 11 13 Signal Description Parallel Port Connector J11 3 11 14 Box Header Serial Port 1 Seria

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