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Intel 80C186EA User's Manual

1. IMUL Integer multiply signed 1111011w mod 101 Register Byte 25 28 25 28 Register Word 34 37 34 37 Memory Byte 31 34 32 34 Memory Word 40 43 40 43 IMUL Integer Immediate multiply 011010s1 mod reg r m data data 45 0 22 25 22 25 signed 29 32 29 32 DIV Divide unsigned 1111011w mod 110 r m Register Byte 29 29 Register Word 38 38 Memory Byte 35 35 Memory Word 44 44 IDIV Integer divide signed 1111011w mod 1 11 Register Byte 44 52 44 52 Register Word 53 61 53 61 Memory Byte 50 58 50 58 Memory Word 59 67 59 67 ASCII adjust for multiply 11010100 00001010 19 19 AAD ASCII adjust for divide 11010101 00001010 15 15 CBW Convert byte to word 10011000 2 2 CWD Convert word to double word 10011001 4 4 LOGIC Shift Rotate Instructions Register Memory by 1 1101000w mod TTT r m 2 15 2 15 Register Memory by CL 1101001w mod TTT r m 5 n 17 n 5 n 17 n Register Memory by Count 1100000w mod r m count 5 n 17 n 5 n 17 n TTT Instruction 000 ROL 001 ROR 010 RCL 011 RCR 100 SHL SAL 101 SHR 111 SAR And Reg memory and register to either 001000dw modreg r m 3 10 3 10 Immediate to register memory 1000000w mod 100 r m data data if w 1 4 16 4 16 Immediate to accumulator 0010010w data data if 1 3 4 3 4 8 16 bit TEST And function to flags no result Register memory and register 1000010w modreg r m 3 10 3
2. 0 25 lt 0 0 8 G1 V O SLAV UU SS KR KREG 95 61 8 PKK KKK KY PKR KR KR KK Ras KR KRY 1915494 R KK KS BRR KR BRR KK RRR KERR ato 50 SON 115 101011710001 NW mobs peo TRIST 9 9524 OSSIN 5201 10019 4 NIMTO 82 1 22 22 sjndino 14 5 NIMTO pue Figure 15 Powerup Reset Waveforms PRELIMINARY 34 34 80C186EA 80C188EA 801 186 801 188 3881008 eui 0 2 eq JOU LNOMTO YBIY Buiuonisuea O19 lym pejdures spoued NIMTO 40 UBIY I alym SI NISIH JI si NISIH spoued NIMTO 4 1 I NOMTO L SALON 9 657645 spol4eg 110419 7 speed 100412 4 sng 35414 YBIH NISIY Bull MOT WNUIUIN 1NOS3Y NIS34 2001 N30 4 10 262555 2
3. 20 PRELIMINARY 20 intel ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Storage Temperature 65 C to 150 C Case Temperature under Bias 65 C to 150 C Supply Voltage with Respect ke nen 0 5V to 6 5V Voltage on Other Pins with Respect sharia eee 0 5V to 0 5V Recommended Connections Power and ground connections must be made to multiple Vcc and Vss pins Every 80C186EA based circuit board should contain separate power Vcc and ground Vss planes All Vcc and Vgs pins must be connected to the appropriate plane Pins identi fied as N C must not be connected in the system Decoupling capacitors should be placed near the processor The value and type of decoupling capac PRELIMINARY 80 186 80 188 80L186EA 80L188EA NOTICE This data sheet contains preliminary infor mation on new products in production It is valid for the devices indicated in the revision history The specifications are subject to change without notice WARNING Stressing the device beyond the Absolute Maximum may cause permanent damage These are stress ratings only Operation beyond the Operating Conditions is not recommended and ex tended exposure beyond the Operating Conditions may affect device reliability itors is application and board layout dependent The processor can cause transient power sur
4. E 415 4615 RFSH NOTES 272432 6 1 The nine character alphanumeric code XXXXXXXXD underneath the product number is the Intel FPO number 2 Pin names in parentheses apply to the 80C186EA 80L188EA Figure 6 Quad Flat Pack EIAJ Pinout Diagram IR PRELIMINARY n intel 80C186EA 80C188EA 80L186EA 80L188EA Table 8 SQFP Pin Functions with Package Location AD Bus Bus Control Processor Control ADO 1 ALE QSO 29 RESIN 73 UCS 62 AD1 3 BHE RFSH 26 RESOUT 34 LCS 63 AD2 6 50 40 CLKIN 32 AD3 8 ST 39 OSCOUT 33 MCSO PEREQ 57 AD4 12 52 38 CLKOUT 36 MCS1 ERROR 58 AD5 14 RD QSMD 28 TEST BUSY 46 MCS2 59 AD6 16 WR QS1 27 NMI 47 MCS3 NPS 60 AD7 18 ARDY 37 INTO 48 ADS 8 2 SRDY 44 INT1 SELECT 49 PCSO 71 AD9 A9 5 DEN 56 INT2 INTAO 52 PCS1 69 AD10 A10 7 DT R 54 INT3 INTAT 53 PCS2 68 AD11 A11 9 LOCK 45 PDTMR 55 PCS3 67 AD12 A12 13 HOLD 43 PCS4 66 AD13 A13 15 HLDA 42 Powerand Ground PCS5 A1 65 AD14 A14 17 PCS6 A2 64 AD15 A15 19 No Connection 10 16 83 21 11 INO 77 17 84 22 N C 4 Vcc 20 TMR IN 1 76 A18 85 23 25 50 TMR OUT 0 75 A19 S6 24 N C 35 Vcc 51 TMR OUT 1 74 N C 72 Vcc 61 Vss 30 DRQO 79 Vss 31 DRQ1 78 Vss 41 Vss 70 Vss 80 NOTE Pin names in parentheses apply to the 80C186EA 80L188EA Table 9 SQFP Pin Locations w
5. RD WR RFSH DT R 0 25 0 25 0 25 ns 1 LOCK S2 0 A19 16 DEN AD15 0 15 8 AD7 0 0 25 0 25 0 25 ns 1 PRELIMINARY 25 25 80C186EA 80C188EA 80L186EA 80L188EA AC SPECIFICATIONS Continued Characteristics 80C186EA25 80C186EA20 80C186EA 13 Symbol Parameter Min Max Min Max Min Max Units Notes SYNCHRONOUS INPUTS 25 MHz 12 20 MHz 13 MHz TCHIS TEST NMI INT3 0 8 10 10 ns 1 9 T1 0IN ARDY TEST NMI INT3 0 3 3 3 ns 1 9 T1 0IN ARDY Tous AD15 0 AD7 0 ARDY 10 10 10 ns 1 10 SRDY DRQ1 0 AD15 0 AD7 0 ARDY 3 3 3 ns 1 10 SRDY DRQ1 0 Tous HOLD PEREQ ERROR 10 10 10 ns 1 9 80C186EA Only HOLD PEREQ ERROR 3 3 3 ns 1 9 80C186EA Only Tous RESIN to CLKIN 10 10 10 ns 1 RESIN from CLKIN 3 3 3 ns 1 9 NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measured at for high time Vi for low time 3 Only required to guarantee Icc Maximum limits are bounded by Tcp and 4 Specified for a 50 pF load see Figure 13 for capacitive derating information 5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF 6 See Figure 14 for rise and fall times 7 TcHov1 applies to RFSH LOCK and A19 16 only after a HOLD release 8 applies to RD and WR only after a HOLD release 9 Setup and Ho
6. 18 91 43104 NOILVNILS3Q 18 04 SYILNIOd 324005 18 02 0 LINN 7041405 583161934 TVH3N39 18 91 LINN NOILNIIXI SM31SI933 TOYLNOD 543151939 1 02 18 91 83151938 INNOD 83151934 1 I 0 3T18V ANVYDOYd NI LL NI LL 10011 11001 LINN LINN 32 1931 508 7031405 534434 61 95 61 0 10 ysa 91y 0 3148 3148 9 543151938 1N3W93S x 583151934 7041409 AGUS 508 TYNHILNI 543151934 543151934 7041405 7041409 LINN 331103109 ANINIOVNYN 4 nlad 1ANYYILNI YIMOd YOLVYINID 1 0538 2012 4 533 INN OLNI 100350 19313S OVINI ZINI OMI LVINI ZLNI Figure 1 80C186EA 80C188EA Block Diagram Pin names in parentheses apply to the 80 186 801188 NOTE PRELIMINARY 80 186 80 188 801 186 80 188 INTRODUCTION Unless specifically noted all references to the 80 186 apply to the 80 188 80L186EA and 80L188EA References to pins that differ between the 80C186EA 80L186EA and the 80C188EA 801 188 are given in parentheses The L in the part number denotes low voltage operation Physi cally and functionally the C and L devices are identical The 80C186EA is the second product in a new gen eration of low power high integration mic
7. 2 9 2 13 Segment register to register memory 10001100 mod 0 reg 2 11 2 15 Push 11111111 mod 1 10 16 20 Register 01010 reg 10 14 Segment register 000reg110 9 13 Immediate 01101050 data data if s 0 10 14 Push 01100000 36 68 10001111 4000 20 24 Register 01011 reg 10 14 Segment register 000reg111 reg 01 8 12 Pop All 01100001 51 83 XCHG Exchange Register memory with register 1000011w modreg r m 4 17 4 17 Register with accumulator 10010 reg 3 3 IN Input from Fixed port 1110010w port 10 10 Variable port 1110110w 8 7 OUT Output to Fixed port 1110011w port 9 9 Variable port 1110111w 7 7 XLAT Translate byte to AL 11010111 11 15 LEA Load EA to register 10001101 mod reg 6 6 LDS Load pointer to DS 11000101 mod reg mod 11 18 26 LES Load pointer to ES 11000100 mod reg mod 11 18 26 LAHF Load AH with flags 10011111 2 2 ISAHF Store AH into flags 10011110 3 3 IPUSHF Push flags 10011100 9 13 Pop flags 10011101 8 12 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory tr
8. gemere Le gU d O 9 oW o Lo GETO Sto D wiv SES 8 2558 cms SEE 0358 ee 9 D 59055 Loop ENS E 5 9 05 9 lo 0 To gt 2 P I 65 26 S e 2 TES EC 9664 5580 5 2 eles 8058 5 gt R228 gt S 02 55 9 2 9 lt 2 Figure 23 Ready Waveform PRELIMINARY 42 42 intel 80C186EA 80C188EA EXECUTION TIMINGS A determination of program exeuction timing must consider the bus cycles necessary to prefetch in structions as well as the number of execution unit cycles necessary to execute instructions The fol lowing instruction timings represent the minimum execution time in clock cycle for each instruction The timings given are based on the following as sumptions The opcode along with any data or displacement required for execution of a particular instruction has been prefetched and resides in the queue at the time it is needed No wait states or bus HOLDs occur All word data is located on even address bound aries 80C186EA only All jumps and calls include the time required to fetch the opcode of the next instruction at the destination address PRELIMINARY 186EA 80C188EA 80L186EA 80L188EA
9. All instructions which involve memory accesses can require one or two additional clocks above the mini mum timings shown due to the asynchronous hand shake between the bus interface unit BIU and exe cution unit With a 16 bit BIU the 80C186EA has sufficient bus performance to endure that an adequate number of prefetched bytes will reside in the queue 6 bytes most of the time Therefore actual program exeuc tion time will not be substanially greater than that derived from adding the instruction timings shown The 80 188 8 bit BIU is limited in its performance relative to the execution unit A sufficient number of prefetched bytes may not reside in the prefetch queue 4 bytes much of the time Therefore actual program execution time will be substantially greater than that derived from adding the instruction timings shown 43 80C186EA 80C188EA 801 186 801 188 In e 80C186EA 80C188EA Function Format Clock Clock Comments Cycles Cycles DATA TRANSFER Move Register to Register Memory 1000100w modreg r m 2 12 2 12 Register memory to register 1000101w modreg r m 2 9 2 9 Immediate to register memory 1100011w mod 000 r m data data if w 1 12 13 12 13 8 16 bit Immediate to register 1011w reg data data if 1 3 4 3 4 8 16 bit Memory to accumulator 1010000w addr low addr high 8 8 Accumulator to memory 1010001w addr low addr high 9 8 Register memory to segment register 10001110 mod 0 reg
10. 80L186EA 80L188EA Chip Select Unit The 80C186EA Chip Select Unit integrates logic which provides up to 13 programmable chip selects to access both memories and peripherals In addi tion each chip select can be programmed to auto matically terminate a bus cycle independent of the condition of the SRDY and ARDY input pins The chip select lines are available for all memory and bus cycles whether they are generated by the CPU the DMA unit or the Refresh Control Unit Refresh Control Unit The Refresh Control Unit RCU automatically gen erates a periodic memory read bus cycle to keep dynamic or pseudo static memory refreshed A 9 bit counter controls the number of clocks between re fresh requests A 9 bit address generator is maintained by the RCU with the address presented on the A9 1 address lines during the refresh bus cycle Address bits A19 13 are programmable to allow the refresh ad dress block to be located on any 8 Kbyte boundary Power Management The 80 186 has three operational modes to con trol the power consumption of the device They are Power Save Mode Idle Mode and Powerdown Mode Power Save Mode divides the processor clock by a programmable value to take advantage of the fact that current is linearly proportional to frequency An unmasked interrupt NMI or reset will cause the 80 186 to exit Power Save Mode Idle Mode freezes the clocks of the Execution Unit and the Bus Interface Unit
11. AD15 0 AD7 0 ARDY SRDY DRQ1 0 3 3 ns 1 10 Tous HOLD 22 22 ns 1 9 HOLD 3 3 ns 1 9 Tous RESIN to CLKIN 22 22 ns 1 9 RESIN from CLKIN 3 3 ns 1 9 NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measured at for high time for low time 3 Only required to guarantee Icc Maximum limits are bounded by and 4 Specified for a 50 pF load see Figure 13 for capacitive derating information 5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF 6 See Figure 14 for rise and fall times 7 TcHov1 applies to RFSH LOCK and A19 16 only after a HOLD release 8 applies to RD and WR only after HOLD release 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper operation 11 applies to BHE RFSH and A19 16 only after a HOLD release 12 Pin names in parentheses apply to the 80C188EA 80L188EA 28 PRELIMINARY 28 n intel 80C186EA 80C188EA 80L186EA 80L188EA AC SPECIFICATIONS Continued Relative Timings 80C186EA25 20 13 80L186EA 13 8 Symbol Parameter Min Max Unit Notes RELATIVE TIMINGS TLHLL ALE Rising to ALE Falling T 15 ns TAVLL Address Valid to ALE Falling MT 10 ns TPLLL Chip Selects Valid to ALE Falling MT 10 ns 1 TLLAX Address Hold fr
12. 10 Immediate data and register memory 1111011w mod 000 data data if w 1 4 10 4 10 Immediate data and accumulator 1010100w data data if 1 3 4 3 4 8 16 bit Or Reg memory and register to either 000010dw mod reg 3 10 3 10 Immediate to register memory 1000000w mod001 data data if w 1 4 16 4 16 Immediate to accumulator 0000110w data data if 1 3 4 3 4 8 16 bit Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers a PRELIMINARY n intel 80C186EA 80C188EA 80L186EA 80L188EA INSTRUCTION SET SUMMARY Continued 80C186EA 80C188EA Function Format Clock Clock Comments Cycles Cycles LOGIC Continued XOR Exclusive or Reg memory and register to either 001100dw mod reg 3 10 3 10 Immediate to register memory 1000000w mod 110 r m data data if w 1 4 16 4 16 Immediate to accumulator 0011010w data data if 1 3 4 3 4 8 16 bit Invert register memory 1111011w mod 0 10 r m 3 10 3 10 STRING MANIPULATION IMOVS Move byte word 1010010w 14 14 5 Compare byte word 1010011w 22 22 ISCAS Scan byte word 1010111w
13. 16 I 06 15 B1 aD13 13 14 1 405 15 4012 412 12 ape 10 9 8 an3 7 010 410 6 02 5 0 09 9 A10 2 8 Q 80 272432 7 Figure 7 Shrink Quad Flat Pack SQFP Pinout Diagram NOTES 1 XXXXXXXXD indicates the Intel FPO number 2 Pin names in parentheses apply to the 80C188EA PACKAGE THERMAL SPECIFICATIONS The 80 186 801 186 is specified for operation when Tg the case temperature is within the range of 0 to 85 C PLCC package or 0 to 106 QFP EIAJ package Tc may be measured in any environment to determine whether the processor is within the specified operating range The case tem perature must be measured at the center of the top surface TA the ambient temperature can be calculated from Oca thermal resistance from the case to ambi ent with the following equation TA Tc P X Typical values for at various airflows are given in Table 10 P the maximum power consumption specified in watts is calculated by using the maximum ICC as tabulated in the DC specifications and of 5 5V Table 10 Thermal Resistance at Various Airflows in C Watt Airflow Linear ft min m sec 200 400 600 800 1000 0 1 01 2 03 3 04 4 06 5 07 PLCC 29 25 21 19 17 165 Oca 66 63 605 59 58 57 6cA SQFP 70
14. 3 10 Immediate from register memory 100000sw mod 0 11 data data if s w 01 4 16 4 16 Immediate from accumulator 0001110w data data if w 1 3 4 3 4 8 16 bit DEC Decrement Register memory 1111111w mod 001 3 15 3 15 Register 01001 reg 3 3 CMP Compare memory with register 0011101w modreg r m 3 10 3 10 Register with register memory 0011100w modreg r m 3 10 3 10 Immediate with register memory 100000sw mod 111 r m data data if s w 01 3 10 3 10 Immediate with accumulator 0011110w data data if 1 3 4 3 4 8 16 bit Change sign register memory 1111011w mod 0 1 1 3 10 3 10 ASCII adjust for add 00110111 8 8 IDAA Decimal adjust for add 00100111 4 4 AAS ASCII adjust for subtract 00111111 7 7 DAS Decimal adjust for subtract 00101111 4 4 IMUL Multiply unsigned 1111011w mod 100 r m Register Byte 26 28 26 28 Register Word 35 37 35 37 Memory Byte 32 34 32 34 Memory Word 41 43 41 48 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers PRELIMINARY 45 45 80C186EA 80C188EA 801 186 801 188 In INSTRUCTION SET SUMMARY Continued 80C186EA 80C188EA Function Format Clock Clock Comments Cycles Cycles ARITHMETIC Continued
15. 3 30 3 30 ns 1 4 6 4 AD15 0 15 8 7 0 3 34 3 35 ns 1 4 6 TCLOV5 52 0 3 38 3 40 ns 1 4 6 TCHOF RD WR BHE 5 0 27 0 27 ns 1 DT R LOCK S2 0 A19 16 TcLoF DEN AD15 0 A15 8 AD7 0 0 27 0 27 ns 1 NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measured at for high time Vi for low time 3 Only required to guarantee Icc Maximum limits are bounded by Tc and 4 Specified for a 50 pF load see Figure 13 for capacitive derating information 5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF 6 See Figure 14 for rise and fall times 7 TcHov1 applies to RFSH LOCK and A19 16 only after a HOLD release 8 TcHove applies to RD and WR only after a HOLD release 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper operation 11 applies to BHE RFSH and A19 16 only after a HOLD release 12 Pin names in parentheses apply to the 80C188EA 80L188EA PRELIMINARY 27 27 80C186EA 80C188EA 801 186 801 188 SPECIFICATIONS Characteristics 80L186EA13 80L186EA8 Symbol Parameter Min Max Min Max Units Notes SYNCHRONOUS INPUTS 13 MHz 8 MHz TCHIS TEST NMI INT3 0 T1 0IN ARDY 22 22 ns 1 9 TEST NMI INT3 0 T1 0IN ARDY 3 3 ns 1 9 Tous AD15 0 AD7 0 ARDY SRDY DRQ1 0 22 22 ns 1 10
16. 80 188 The Execution Unit EU is an enhanced 8086 CPU core that includes dedicated hardware to speed up effective address calculations enhance execution speed for multiple bit shift and rotate in structions and for multiply and divide instructions string move instructions that operate at full bus bandwidth ten new instructions and static opera tion The Bus Interface Unit BIU is the same as that found on the original 80C186 family products An independent internal bus is used to allow communi cation between the BIU and internal peripherals intel 80C186EA CORE ARCHITECTURE Bus Interface Unit The 80 186 core incorporates a bus controller that generates local bus control signals In addition it employs a HOLD HLDA protocol to share the local bus with other bus masters The bus controller is responsible for generating 20 bits of address read and write strobes bus cycle status information and data for write operations in formation It is also responsible for reading data off the local bus during a read operation SRDY and ARDY input pins are provided to extend a bus cycle beyond the minimum four states clocks The local bus controller also generates two control signals DEN and DT R when interfacing to exter nal transceiver chips This capability allows the addi tion of transceivers for simple buffering of the mulit plexed address data bus Clock Generator The processor provides an on chip clock gene
17. 801 188 INSTRUCTION SET SUMMARY Continued In e 80C186EA 80C188EA Function Format Clock Clock Comments Cycles Cycles CONTROL TRANSFER Continued RET Return from CALL Within segment 11000011 16 20 Within seg adding immed to SP 11000010 data low data high 18 22 Intersegment 11001011 22 30 Intersegment adding immediate to SP 11001010 data low data high 25 33 JE JZ Jump on equal zero 01110100 disp 4 13 4 13 JMP not taken JMP JL JNGE Jump on less not greater or equal 01111100 disp 4 13 4 13 taken JLE JNG Jump on less or equal not greater 01111110 disp 4 13 4 13 JB JNAE Jump on below not above or equal 01110010 disp 4 13 4 13 JBE JNA Jump on below or equal not above 01110110 disp 4 13 4 13 JP JPE Jump on parity parity even 01111010 disp 4 13 4 13 JO Jump on overflow 01110000 disp 4 13 4 13 JS Jump on sign 01111000 disp 4 13 4 13 JNE JNZ Jump on not equal not zero 01110101 disp 4 13 4 13 JNL JGE Jump on not less greater or equal 01111101 disp 4 13 4 13 JNLE JG Jump on not less or equal greater 01111111 disp 4 13 4 13 JNB JAE Jump on not below above or equal 01110011 disp 4 13 4 13 JNBE JA Jump on not below equal above 01110111 disp 4 13 4713 JNP JPO Jump par par odd 01111011 disp
18. 80C186EA interfaces directly with an 80C187 Numerics Coprocessor M 272432 1 Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata October 1995 Order Number 272432 003 COPYRIGHT INTEL CORPORATION 1995 80 186 80 188 801 186 801 188 intel 80C186EA 80C188EA AND 80L186EA 80L188EA 16 Bit High Integration Embedded Processor CONTENTS PAGE INTRODUCTION 4 80C186EA CORE ARCHITECTURE 4 Bus Interface Unit 4 Clock Generator 4 80C186EA PERIPHERAL ARCHITECTURE 5 Interrupt Control Unit 5 Timer Counter Unit 5 DMA Control Unit 7 Chip Select Unit 7 Refresh Control Unit 7 Power Management 7 80C187 Interface 80 186 Only 8 ONCE Test Mode 8
19. additional characteristics for each pin Table 3 lists all the possible symbols for this column The Input Type column indicates the type of input asynchronous or synchronous Asynchronous pins require that setup and hold times be met only in order to guarantee recognition at a particular clock edge Synchronous pins require that setup and hold times be met to guarantee proper operation For example missing the setup or hold time for the SRDY pin a synchronous input will re sult in a system failure or lockup Input pins may also be edge or level sensitive The possible character istics for input pins are S E S L A E and A L The Output States column indicates the output state as a function of the device operating mode Output states are dependent upon the current activi ty of the processor There are four operational states that are different from regular operation bus hold reset Idle Mode and Powerdown Mode Ap propriate characteristics for these states are also in dicated in this column with the legend for all possi ble characteristics in Table 2 The Pin Description column contains a text de scription of each pin As an example consider AD15 0 I O signifies the pins are bidirectional S L signifies that the input function is synchronous and level sensitive H Z signifies that as outputs the pins are high imped ance upon acknowledgement of bus hold R Z sig nifies that the pins float during reset P X
20. at a logic zero state while all peripherals operate normally Powerdown Mode freezes all internal clocks at a logic zero level and disables the crystal oscillator internal registers hold their values provided is maintained Current consumption is reduced to tran sistor leakage only 80C186EA 80C188EA 801 186 801 188 80 187 Interface 80C186EA Only The 80C187 Numerics Coprocessor may be used to extend the 80C186EA instruction set to include floating point and advanced integer instructions Connecting the 80C186EA RESOUT and TEST BUSY pins to the 80C187 enables Numerics Mode operation In Numerics Mode three of the four Mid Range Chip Select MCS pins become handshaking pins for the interface The exchange of data and control information proceeds through four dedicated ports If an 80C187 is not present the 80C186EA config ures itself for regular operation at reset NOTE The 80C187 is not specified for 3V operation and therefore does not interface directly to the 80L186EA ONCE Test Mode To facilitate testing and inspection of devices when fixed into a target system the 80 186 has a test mode available which forces all output and input output pins to be placed in the high impedance state ONCE stands for Circuit Emulation The ONCE mode is selected by forcing the UCS and LCS pins LOW 0 during processor reset these pins are weakly held to a HIGH 1 level while RES
21. data information is transferred during the data phase of the bus cycle NOTE Pin names in parentheses apply to the 80C188EA and 80L188EA PRELIMINARY 11 80C186EA 80C188EA 80L186EA 80L188EA intel Table 3 Pin Descriptions Continued Pin Name Pin Type Input Type Output States Description A18 16 A19 S6 A16 A19 A8 H Z R Z P X These pins provide multiplexed Address during the address phase of the bus cycle Address bits 16 through 19 are presented on these pins and can be latched using ALE A18 16 are driven to a logic 0 during the data phase of the bus cycle On the 8 bit bus versions 15 8 provide valid address information for the entire bus cycle Also during the data phase S6 is driven to a logic 0 to indicate a CPU initiated bus cycle or logic 1 to indicate a DMA initiated bus cycle or a refresh cycle 00 o H Z R Z P 1 Bus cycle Status are encoded on these pins to provide bus transaction information 52 0 are encoded as follows Bus Cycle Initiated Interrupt Acknowledge Read 1 0 Write 1 Processor HALT Queue Instruction Fetch Read Memory Write Memory Passive no bus activity 0000 ALE QSO 2A ge 0 Address Latch Enable output is used to strobe address information into a transparent type latch during the address phase of the bus cycle In Queue Status Mode 050 provides queue
22. facing down Tables 8 and 9 list the 80 186 80 188 pin names with package location for the 80 pin Shrink Quad Flat Pack SQFP component Figure 7 depicts the complete 80 186 80 188 SQFP as viewed from the top side of the component i e con tacts facing down Table 4 PLCC Pin Names with Package Location Address Data Bus Bus Control Processor Control Location Name Location Name Location Name Location ADO 17 ALE QSO 61 RESIN 24 UCS 34 AD1 15 BHE RFSH 64 RESOUT 57 LCS 33 AD2 13 50 52 CLKIN 59 MCSO PEREQ 38 ADS 11 61 53 OSCOUT 58 MCS1 ERROR 37 AD4 8 S2 54 CLKOUT 56 52 36 AES RD GSMD 62 TEST BUSY 47 5 WR QS1 63 PDTMR 40 PCSO 25 AD7 2 ARDY 55 51 27 ADS 8 16 NMI 46 PCS2 28 AD9 A9 14 RDY 39 INTO 45 POSS 29 AD10 A10 12 DEN 39 INT1 SELECT 44 PCS4 30 AD11 A11 10 LOCK 48 INT2 INTAO 42 PCSB M 21 AD12 A12 7 HOLD 50 1 41 PCS6 A2 32 IRQ AD13 A13 5 HLDA 51 TOOUT 22 AD14 A14 3 30 Location 21 DRQO 18 V 26 60 A18 66 SS DRQ1 19 A19 S6 65 9 43 Pin names in parentheses apply to the 80C188EA 80L188EA PRELIMINARY 15 80C186EA 80C188EA 801 186 801 188 Table 5 PLCC Package Location with Pin Names intel Location Name Location Name Locat
23. 0L188EA Table 3 Pin Descriptions Pin Name Output States Description Voc POWER connections consist of six pins which must be shorted externally to a Vcc board plane Vss GROUND connections consist of five pins which must be shorted externally to a Vss board plane CLKIN CLocK INput is an input for an external clock An external oscillator operating at two times the required processor operating frequency can be connected to CLKIN For crystal operation CLKIN along with OSCOUT are the crystal connections to an internal Pierce oscillator OSCOUT H Q R Q P Q OSCillator OUTput is only used when using a crystal to generate the external clock OSCOUT along with CLKIN are the crystal connections to an internal Pierce oscillator This pin is not to be used as 2X clock output for non crystal applications i e this pin is N C for non crystal applications OSCOUT does not float in ONCE mode CLKOUT H Q R Q P Q CLocK OUTput provides a timing reference for inputs and outputs of the processor and is one half the input clock CLKIN frequency CLKOUT has a 5096 duty cycle and transistions every falling edge of CLKIN A L RESet IN causes the processor to immediately terminate any bus cycle in progress and assume an initialized state All pins will be driven to a known state and RESOUT will also be driven active The rising edge low to high transition synchronizes CLKOUT wit
24. 15 15 LODS Load byte wd to AL AX 1010110w 12 12 5705 Store byte wd from AL AX 1010101w 10 10 INS Input byte wd from DX port 0110110w 14 14 OUTS Output byte wd to DX port 0110111w 14 14 Repeated by count in CX REP REPE REPZ REPNE REPNZ IMOVS Move string 11110010 1010010w 8 8 8 8 5 Compare string 11110012 1010011w 5 22 5 22n ISCAS Scan string 1111001z 1010111w 5 15n 5 15n LODS Load string 11110010 1010110w 6 11 6 11n ISTOS Store string 11110010 1010101w 64 9n 6 9n INS Input string 11110010 0110110w 8 8n 8 8n OUTS Output string 11110010 0110111w 8 8n 8 8n CONTROL TRANSFER CALL Call Direct within segment 11101000 disp low disp high 15 19 Register memory 11111111 mod 0 10 13 19 17 27 indirect within segment Direct intersegment 10011010 segment offset 23 31 segment selector Indirect intersegment 11111111 mod 0 11 mod 11 38 54 Unconditional jump Short long 11101011 disp low 14 14 Direct within segment 11101001 disp low disp high 14 14 Register memory 11111111 mod 100 r m 11 17 11 21 indirect within segment Direct intersegment 11101010 segment offset 14 14 segment selector Indirect intersegment 11111111 mod 101 r m mod 11 26 34 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers PRELIMINARY 47 47 80C186EA 80C188EA 801 186
25. 4 13 4 13 Jump on not overflow 01110001 disp 4 13 4 13 JNS Jump on not sign 01111001 disp 4 13 4 13 JCXZ Jump on CX zero 11100011 disp 5 15 5 15 LOOP Loop CX times 11100010 disp 6 16 6 16 LOOP not 3 taken LOOP LOOPZ LOOPE Loop while zero equal 11100001 disp 6 16 6 16 t ken LOOPNZ LOOPNE Loop while not zero equal 11100000 disp 6 16 6 16 ENTER Enter Procedure 11001000 data low data high 0 15 19 1 1 25 29 22 16 1 26 20 n 1 LEAVE Leave Procedure 11001001 8 8 INT Interrupt specified 11001101 type 47 47 Type 3 11001100 45 45 if INT taken if INT not INTO Interrupt on overflow 11001110 48 4 48 4 taken IRET Interrupt return 11001111 28 28 BOUND Detect value out of range 01100010 modreg r m 33 35 33 35 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers PRELIMINARY 48 48 intel INSTRUCTION SET SUMMARY Continued 80C186EA 80C188EA 80L186EA 80L188EA 80C186EA 80C188EA Function Format Clock Clock Comments Cycles Cycles PROCESSOR CONTROL CLC Clear carry 11111000 2 2 Complement carry 11110101 2 2 ISTC Set carry 11111001 2 2 CLD Clear direction 11111100 2 2 ISTD Set direction 11111101 2 2 CLI Clear i
26. 62625 6626 5 252626 262626565 526062626955 5260694 04 Sirti um eom TATE A OTOL IROOM IRIKS KKK 005 e 00 KKK KKK I IR KKK KK MIRO OA ACH SSSR KKK KRISE GN SSS 55555555 909090969095 PRS 55250525205 600500050 060050505050050506050 06060 0906060 05094 KO 009090 KKK KKK KKK KY SON 5 10011 10001 KKK KKK KKK 0 069000 NHK KKK HH KK 0 95 c ORR KKK I KKK I ORO OQ KKK KK KKK KN KKK KKK 00 0606 00 0 000606 cm 29 9 929 9 929 9 929 9 20 9 92 2 2 OF O CSOW 5215500 1no 3 Figure 16 Warm Reset Waveforms 35 35 PRELIMINARY LI 80C186EA 80C188EA 80L186EA 80L188EA intel 2 BUS CYCLE WAVEFORMS Figures 17 through 23 present the various bus cycles that are generated by the processor What is shown in the figure is the relationship of the various bus signals to CLKOUT These figures along with the information present in AC Specifications allow the user to determine all the criti
27. 88 1 VERSUS FREQUENCY AND VOLTAGE The current loc consumption of the processor is essentially composed of two components and lccs is the quiescent current that represents internal device leakage and is measured with all inputs or floating outputs at GND or Vcc no clock applied to the device is equal to the Powerdown current and is typically less than 50 pA is the switching current used to charge and discharge parasitic device capacitance when chang ing logic levels Since lccs is typically much greater than can often be ignored when calculating is related to the voltage and frequency at which the device is operating It is given by the formula Power V X V X Cpgy X f Icc lecs V X Opgy X f Where V Device operating voltage Vcc Cpev Device capacitance f Device operating frequency Device current Measuring Cpgy on a device like the 80C186EA would be difficult Instead Cpgy is calculated using the above formula by measuring at a known and frequency see Table 11 Using this Cpgy val ue can be calculated at any voltage and fre quency within the specified operating range EXAMPLE Calculate the typical when operating at 20 MHz 4 8V Icc lccs 4 8 X 0 515 20 49 mA intel PDTMR PIN DELAY CALCULATION The PDTMR pin provides a delay between the as sertion of NMI an
28. DIFFERENCES BETWEEN THE 80C186XL AND THE 80 186 8 Pinout Compatibility 8 Operating Modes 8 TTL vs CMOS Inputs 8 Timing Specifications 8 PACKAGE INFORMATION 9 Prefix Identification 9 Pin Descriptions 9 80C186EA Pinout 15 CONTENTS PAGE PACKAGE THERMAL SPECIFICATIONS 20 ELECTRICAL SPECIFICATIONS 21 Absolute Maximum Ratings 21 Recommended Connections 21 DC SPECIFICATIONS 22 versus Frequency and Voltage 24 PDTMR Pin Delay Calculation 24 AC SPECIFICATIONS 25 AC Characteristics 80C186EA20 13 25 AC Characteristics 80L186EA13 8 27 Relative Timings 29 AC TEST CONDITIONS 30 AC TIMING WAVEFORMS 30 DERATING CURVES 33 RESET tere 33 BUS CYCLE WAVEFORMS 36 EXECUTION TIMINGS 43 INSTRUCTION SET SUMMARY 44 REVISION HISTORY 50 50 PRELIMINARY 80C186EA 80C188EA 80L186EA 80L188EA 4 46 212 SON SON 29 9594 LINN 1041409 123135 19 5594 583151934 7041409 43151934 1041402 583161934 1
29. ESIN is applied after Voc is stable and the device has been operating Note that a reset will terminate all activity and return the processor to a known operat ing state Any bus operation that is in progress at the time RESIN is asserted will terminate immediately note that most control signals will be driven to their inactive state first before floating While RESIN is active signals RD QSMD UCS LCS MCSO PEREQ MCS1 ERROR LOCK and TEST BUSY are configured as inputs and weakly held high by internal pullup transistors Forcing UCS and LCS low selects ONCE Mode Forcing QSMD low selects Queue Status Mode Forcing TEST BUSY high at reset and low four clocks later enables Numerics Mode Forcing LOCK low is prohibited and results in unspecified operation 33 80 186 80 188 80L186EA 80L188EA V3881208 0 2 pejduues s NIS3H Jeye spoued NIMTO 2 1 jerewxoldde sino20 uoneziuououAs INOMTO LE 8 26 2 sng 18414 0 ubi KJeyeurxoadde ue 3 1108109 4 nov sng 18413 0 YBIH 3 jeyeut uBiu NISIY 0 914849 NDETO P 100534 NIS3Y 2262 Nad IKA ocu aaa aa rare VPC OY POCO d
30. IN is active DIFFERENCES BETWEEN THE 80C186XL AND THE 80C186EA The 80 186 is intended as a direct functional up grade for 80C186XL designs In many cases it will be possible to replace an existing 80C186XL with little or no hardware redesign The following sections describe differences in pinout operating modes and AC and DC specifications to keep in mind Pinout Compatibility The 80 186 requires a PDTMR pin to time the processor s exit from Powerdown Mode The original pin arrangement for the 80C186XL in the PLCC package did not have any spare leads to use for PDTMR so the DT R pin was sacrificed The ar rangement of all the other leads in the 68 lead PLCC is identical between the 80C186XL and the 80C186EA DT R may be synthesized by latching the S1 status output Therefore upgrading a PLCC 80C186XL to PLCC 80C186EA is straightforward intel The 80 lead QFP EIAJ pinouts are different be tween the 80C186XL and the 80 186 In addition to the PDTMR pin the 80C186EA has more power and ground pins and the overall arrangement of pins was shifted A new circuit board layout for the 80C186EA is required Operating Modes The 80C186XL has two operating modes Compati ble and Enhanced Compatible Mode is a pin to pin replacement for the NMOS 80186 except for nu merics coprocessing In Enhanced Mode the proc essor has a Refresh Control Unit the Power Save feature and an interface to the 80C187 Numeric
31. Input Leakage Current except 10 pA OV lt Vin lt RD QSMD UCS LCS 0 MCS1 LOCK and TEST lio Input Leakage Current 275 Vin 0 7 RD QSMD UCS LCS MCSO Note 1 MCS1 LOCK and TEST Output Leakage Current 10 uA 0 45 lt Vout lt 2 5 Supply Current RESET 5 5V 80L186EA 13 65 mA Note 3 80L186EA 8 40 mA Note 3 lcca Supply Current RESET 2 7V 80L186EA 13 34 mA Note 3 80L186EA 8 20 mA Note 3 lips Supply Current Idle 5 5V 80L186EA 13 46 mA 80L186EA 8 28 mA lips Supply Current Idle 2 7V 80L186EA 13 24 mA 80L186EA 8 14 mA 5 Supply Current Powerdown 5 5 80L186EA 13 100 80L186EA 8 100 Ipp3 Supply Current Powerdown 2 7V 80L186EA 13 50 80L186EA 8 50 CouT Output Pin Capacitance 0 15 pF 1 MHz Note 4 Input Pin Capacitance 0 15 pF Te 1 MHz NOTES 1 RD QSMD UCS LCS MCSO MCS1 LOCK and TEST have internal pullups that are only activated during RESET Loading these pins above lo 275 will cause the processor to enter alternate modes of operation 2 Output pins are floated using HOLD or ONCE Mode 3 Measured at worst case temperature and with all outputs loaded as specified in the AC Test Conditions and with the device in RESET RESIN held low 4 Output capacitance is the capacitive load of a floating output pin PRELIMINARY 23 80C186EA 80C188EA 801 186 801 1
32. S of amemory bus cycle is within the address limitations programmed by the user In Numerics Mode 80C186EA only three of the pins become handshaking pins for the 80 187 The CoProcessor REQuest input signals that a data transfer is pending ERROR is an input which indicates that the previous numerics coprocessor operation resulted in an exception condition An interrupt Type 16 is generated when ERROR is sampled active at the beginning of a numerics operation Numerics Coprocessor Select is an output signal generated when the processor accesses the 800187 PCS4 0 H 1 Peripheral Chip Selects go active whenever the address R 1 of a memory or 1 bus cycle is within the address P 1 limitations programmed by the user PCS5 A1 H 1 H X These pins provide a multiplexed function As additional PCS6 A2 R 1 Peripheral Chip Selects they go active whenever the P 1 address of a memory or I O bus cycle is within the address limitations by the user They may also be programmed to provide latched Address A2 1 signals TOOUT Timer OUTput pins can be programmed to provide a T1OUT R 1 single clock or continuous waveform generation P Q depending on the timer mode selected TOIN A L Timer INput is used either as clock or control signals depending on the timer mode selected DRQO A L DMA ReQuest is asserted by an external request when it DRQ1 is prepared for a DMA transfer INTO A E L Maskable INTerrupt input will cause
33. a vector to a specific INT1 SELECT Type interrupt routine To allow interrupt expansion INTO and or INT1 can be used with INTAO and INTA1 to interface with an external slave controller 1 becomes SELECT when the ICU is configured for Slave Mode INT2 INTAO A E L H 1 These pins provide multiplexed functions As inputs they INT3 INTA1 IRQ 2 provide a maskable INTerrupt that will cause the CPU to P 1 vector to a specific Type interrupt routine As outputs each is programmatically controlled to provide an INTerrupt Acknowledge handshake signal to allow interrupt expansion INT3 INTA1 becomes IRQ when the ICU is configured for Slave Mode N C No Connect For compatibility with future products do not connect to these pins NOTE Pin names in parentheses apply to the 80C188EA and 80L188EA 14 PRELIMINARY intel 80C186EA PINOUT Tables 4 and 5 list the 80C186EA pin names with package location for the 68 pin Plastic Leaded Chip Carrier PLCC component Figure 9 depicts the complete 80C186EA 80L186EA pinout PLCC pack age as viewed from the top side of the component i e contacts facing down Tables 6 and 7 list the 80C186EA pin names with package location for the 80 pin Quad Flat Pack EIAJ component Figure 6 depicts the complete 80C186EA 80C188EA 80L186EA 80L188EA 80C186EA 80C188EA EIAJ QFP package as viewed from the top side of the component i e con tacts
34. acitance RESET The processor performs a reset operation any time the RESIN pin is active The RESIN pin is actually synchronized before it is presented internally which means that the clock must be operating before a reset can take effect From a power on state RESIN must be held active low in order to guarantee cor rect initialization of the processor Failure to pro vide RESIN while the device is powering up will result in unspecified operation of the device Figure 15 shows the correct reset sequence when first applying power to the processor An external clock connected to CLKIN must not exceed the Vcc threshold being applied to the processor This is nor mally not a problem if the clock driver is supplied with the same that supplies the processor When attaching a crystal to the device RESIN must remain active until both and CLKOUT are stable the length of time is application specific and de pends on the startup characteristics of the crystal circuit The RESIN pin is designed to operate cor rectly using an RC reset circuit but the designer PRELIMINARY DELAY ns 50 100 150 pF 272432 14 Figure 14 Typical Rise and Fall Variations Versus Load Capacitance must ensure that the ramp time for is not so long that RESIN is never really sampled at a logic low level when Vcc reaches minimum operating conditions Figure 16 shows the timing sequence when R
35. ansfers 44 PRELIMINARY intel 80C186EA 80C188EA 80L186EA 80L188EA INSTRUCTION SET SUMMARY Continued 80C186EA 80C188EA Function Format Clock Clock Comments Cycles Cycles DATA TRANSFER Continued SEGMENT Segment Override 5 00101110 2 2 55 00110110 2 2 05 00111110 2 2 ES 00100110 2 2 ADD Add Reg memory with register to either 000000dw modreg r m 3 10 3 10 Immediate to register memory 100000sw mod 000 data data if s w 01 4 16 4 16 Immediate to accumulator 0000010w data data if 1 3 4 3 4 8 16 bit Add with carry Reg memory with register to either 000100dw modreg r m 3 10 3 10 Immediate to register memory 100000sw mod 0 10 r m data data if s w 01 4 16 4 16 Immediate to accumulator 0001010w data data if 1 3 4 3 4 8 16 bit INC Increment memory 1111111w mod 000 3 15 3 15 Register 01000 reg 3 3 SUB Subtract Reg memory and register to either 001010dw mod reg 3 10 3 10 Immediate from register memory 100000sw mod 101 data data if s w 01 4 16 4 16 Immediate from accumulator 0010110w data data if 1 3 4 3 4 8 16 bit SBB Subtract with borrow Reg memory and register to either 000110dw modreg r m 3 10
36. assigned according to the following Segment reg Register 00 ES 01 CS 10 SS 11 DS REG is assigned according to the following table 16 Bit 1 8 Bit w 0 000 AX 000 AL 001 CX 001 CL 010 DX 010 DL 011 BX 011 BL 100 SP 100 AH 101 BP 101 CH 110 SI 110 DH 111 DI 111 BH The physical addresses of all operands addressed by the BP register are computed using the SS seg ment register The physical addresses of the desti nation operands of the string primitive operations those addressed by the DI register are computed using the ES segment which may not be overridden 49 49 80C186EA 80C188EA 801 186 801 188 REVISION HISTORY Intel 80C186EA 80L186EA devices are marked with a 9 character alphanumeric Intel FPO number un derneath the product number This data sheet up date is valid for devices with an A B C D or E as the ninth character in the FPO number as illustrated in Figure 5 for the 68 lead PLCC package Figure 6 for the 84 lead QFP EIAJ package and Figure 7 for the 80 lead SQFP device Such devices may also be identified by reading a value of 01H 02H 03H from the STEPID register This data sheet replaces the following data sheets 272019 002 80C186EA 272020 002 80C188bEA 272021 002 80L186EA 272022 002 80L188bEA 272307 001 SB80C186EA SB80L186EA 272308 001 SB80C188EA SB80L188EA 50 LI intel ERRATA An 80C186EA 80L186EA with a STEPID value of 01H or 02H has th
37. cal timing analysis needed for a given application T1 T2 13 T1 ALE 19 16 19 16 VALID SEE NOTE BHE RFSH V V A15 8 AD15 0 AD7 0 Mesi PCS6 0 LCS UCS 015 0 VALID 07 0 DT R 272432 17 NOTES 1 During the data phase of the bus cycle A19 S6 is driven high for a DMA or refresh cycle 2 Pin names in parentheses apply to the 80C188EA Figure 17 Read Fetch and Refresh Cycle Waveform 39 PRELIMINARY 80C186EA 80C188EA 801 186 801 188 o x a o ALE A19 16 D7 an 55 ek ru a VALID m 9 5 on 5 5 r lt lt gt 8 H DT R DEN 272432 18 1 During the data phase of the bus cycle A19 S6 is driven high for a DMA cycle 2 Pin names in parentheses apply to the 80C188EA NOTES Figure 18 Write Cycle Waveform 37 37 PRELIMINARY 80C186EA 80C188EA 801 186 801 188 lt lt 272432 19 1 The processor drives these pins to 0 during Idle and Powerdown Modes 2 Pin names in parentheses apply to the 80C188EA NOTES Figure 19 Halt Cycle Waveform PRELIMINARY 38 38 80 186 80 188 801 186 801 188 gt o a 272432 20 1 INTA occurs clock later Slave Mode NOTES 2 Pin names in parentheses app
38. ction boundaries not conditioned by a LOCK prefix HLDA H 1 R 0 P 0 HoLD Acknowledge output to indicate that the processor has relinquished control of the local bus When HLDA is asserted the processor will or has floated its data bus and control signals allowing another bus master to drive the signals directly n H 1 R 1 P 1 Upper Chip Select will go active whenever the address of a memory or I O bus cycle is within the address limitations programmed by the user After reset UCS is configured to be active for memory accesses between OFFCOOH and OFFFFFH During a processor reset UCS and LCS are used to enable ONCE Mode H 1 R 1 P 1 Lower Chip Select will go active whenever the address of a memory bus cycle is within the address limitations programmed by the user LCS is inactive after a reset During a processor reset UCS and LCS are used to enable ONCE Mode Pin names in parentheses apply to the 80C188EA and 80L188EA PRELIMINARY 13 80 186 80 188 80L186EA 80L188EA intel Table 3 Pin Descriptions Continued Pin Pin Input Output Description Name Type Type States A L H 1 These pins provide a multiplexed function If enabled MCS1 ERROR R 1 these pins normally comprise a block of Mid Range Chip MCS2 P 1 Select outputs which will go active whenever the address MCS3 NC
39. d the enabling of the internal clocks when exiting Powerdown A delay is required only when using the on chip oscillator to allow the crystal or resonator circuit time to stabilize NOTE The PDTMR pin function does not apply when RESIN is asserted i e a device reset during Pow erdown is similar to a cold reset and RESIN must remain active until after the oscillator has stabi lized To calculate the value of capacitor required to pro vide a desired delay use the equation 440 X t Opp 5 25 C Where t desired delay in seconds Cpp capacitive load on PDTMR in mi crofarads EXAMPLE To get a delay of 300 a capacitor value of Cpp 440 300 10 6 0 132 uF is required Round up to standard available capaci tive values NOTE The above equation applies to delay times greater than 10 us and will compute the TYPICAL capaci tance needed to achieve the desired delay A delay variance of 50 or 25 can occur due to temperature voltage and device process ex tremes In general higher Vcc and or lower tem perature will decrease delay time while lower and or higher temperature will increase delay time Table 11 Values Parameter Typ Max Units Notes Device in Reset 0 515 0 905 mA V MHz 1 2 Device in Idle 0 391 0 635 mA V MHz 1 2 1 is calculated at 40 C all floating outputs driven to Vcc or GND and all o
40. e Status Mode QS1 provides queue status information along with QSO ARDY Asychronous ReaDY is an input to signal for the end of a bus cycle ARDY is asynchronous on rising CLKOUT and synchronous on falling CLKOUT ARDY or SRDY must be active to terminate any processor bus cycle unless they are ignored due to correct programming of the Chip Select Unit SRDY S L Synchronous ReaDY is an input to signal for the end of a bus cycle ARDY or SRDY must be active to terminate any processor bus cycle unless they are ignored due to correct programming of the Chip Select Unit 2 H Z R Z 1 Data ENable output to control the enable of bidirectional transceivers when buffering a system DEN is active only when data is to be transferred on the bus DT R H Z R Z H Z R WH P 1 Data Transmit Receive output controls the direction of a bi directional buffer in a buffered system DT R is only available on the QFP EIAJ package and the SQFP package LOCK output indicates that the bus cycle in progress is not to be interrupted The processor will not service other bus requests such as HOLD while LOCK is active This pin is configured as a weakly held high input while RESIN is active and must not be driven low HOLD HOLD request input to signal that an external bus master wishes to gain control of the local bus The processor will relinquish control of the local bus between instru
41. e following known errata A device with a STEPID of 01H or 02 can be visually identi fied by noting the presence of an A B or C alpha character next to the FPO number The FPO number location is shown in Figures 5 6 and 7 1 An internal condition with the interrupt controller can cause no acknowledge cycle on the INTA1 line in response to INT1 This errata only occurs when Interrupt 1 is configured in cascade mode and a higher priority interrupt exists This errata will not occur consistantly it is dependent on in terrupt timing An 80C186EA 80L186EA with a STEPID value of 03H has no known errata A device with a STEPID of 03H can be visually identified by noting the presence of a D or E alpha character next to the FPO number The FPO number location is shown in Fig ures 5 6 and 7 PRELIMINARY 50
42. erved CCH Reserved Reserved Reserved 8 Reserved CEH Reserved 10H Reserved 50H Timer 0 Count 90H Reserved DOH Src Lo 12H Reserved 52H 0 Compare 92H Reserved D2H 1 Src Hi 14H Reserved 0 Compare 94 Reserved D4H 1 Dest Lo 16H Reserved 56H Timer 0 Control 96H Reserved D6H DMA1 Dest Hi 18H Reserved 58H Timer 1 Count 98H Reserved D8H DMA1 Count 1AH Reserved 5AH Timer 1 Compare A 9AH Reserved DAH Control 1CH Reserved 1 Compare 9CH Reserved DCH Reserved 1EH Reserved 5EH Timer 1 Control 9EH Reserved DEH Reserved 20H Reserved 60H Timer 2 Count AOH UMCS Refresh Base 22H End of Interrupt 62H Timer 2 Compare A2H LMCS E2H Refresh Time 24H Poll 64H Reserved A4H PACS E4H Refresh Control 26H Poll Status 66H Timer 2 Control A6H MMCS E6H Reserved 28H Interrupt Mask 68H Reserved A8H MPCS E8H Reserved 2AH Priority Mask 6AH Reserved AAH Reserved EAH Reserved 2CH In Service 6CH Reserved ACH Reserved ECH Reserved 2EH Interrupt Request 6EH Reserved AEH Reserved EEH Reserved 30H Interrupt Status 70H Reserved BOH Reserved FOH Power Save 32H Timer Control 72H Reserved B2H Reserved F2H Power Control 34H Int Control 74H Reserved B4H Reserved F4H Reserved 36H 1 Int Control 76H Reserved B6H Reserved F6H Step ID 38H INTO Control 78H Reserved B8H Reserved F8H Reserved 3AH INT1 Control 7AH Reserved BAH Reserved FAH Reserved 3CH INT2 Con
43. ges when its output buffers transition particularly when con nected to large capacitive loads Always connect any unused input pins to an appro priate signal level In particular unused interrupt pins NMI INT3 0 should be connected to Vgs to avoid unwanted interrupts Leave any unused output pin or any pin unconnected 21 80 186 80 188 801 186 801 188 DC SPECIFICATIONS 80 186 80 188 intel Symbol Parameter Min Max Units Conditions Voc Supply Voltage 4 5 5 5 V ViL Input Low Voltage for Pins 0 5 0 3 V Input High Voltage for All Pins 0 7 0 5 V VoL Output Low Voltage 0 45 V lo 3 mA min VoH Output High Voltage Voc 0 5 V 2 min VHYR Input Hysterisis on RESIN 0 30 V li 4 Input Leakage Current except 10 pA OV lt lt Voc RD QSMD UCS LCS MCS0 PEREQ MCS1 ERROR LOCK and TEST BUSY lite Input Leakage Current 275 pA Vin 0 7 RD QSMD UCS LCS 0 Note 1 MCS1 ERROR LOCK and TEST BUSY loL Output Leakage Current 10 0 45 lt Vout lt Note 2 lcc Supply Current Cold RESET 80 186 25 80 188 25 105 mA Notes 3 5 80 186 20 80 188 20 90 mA 80C186EA13 80C188bEA13 65 mA lip Supply Current In Idle Mode 80 186 25 80 188 25 90 mA Note 5 80 186 20 80 188 20 70
44. h CLKIN before the processor begins fetching opcodes at memory location OFFFFOH RESOUT H 0 R 1 P 0 RESet OUTput that indicates the processor is currently in the reset state RESOUT will remain active as long as RESIN remains active When tied to the TEST BUSY pin RESOUT forces the 80C186EA into Numerics Mode PDTMR 1 0 A L H WH R Z P 1 Power Down TiMeR pin normally connected to an external capacitor that determines the amount of time the processor waits after an exit from power down before resuming normal operation The duration of time required will depend on the startup characteristics of the crystal oscillator NMI Non Maskable Interrupt input causes a Type 2 interrupt to be serviced by the CPU NMI is latched internally TEST BUSY TEST AD15 0 AD7 0 1 0 S L H Z R Z P X TEST BUSY is sampled upon reset to determine whether the 80C186EA is to enter Numerics Mode In regular operation the pin is TEST TEST is used during the execution of the WAIT instruction to suspend CPU operation until the pin is sampled active low In Numerics Mode the pin is BUSY BUSY notifies the 80C186EA of 80C187 Numerics Coprocessor activity These pins provide a multiplexed Address and Data bus During the address phase of the bus cycle address bits 0 through 15 0 through 7 on the 8 bit bus versions are presented on the bus and can be latched using ALE 8 or 16 bit
45. i PRELIMINARY intel 80 186 80 188 AND 80L186EA 80L188EA 16 BIT HIGH INTEGRATION EMBEDDED PROCESSORS m 80C186 Upgrade for Power Critical Applications m Fully Static Operation m True CMOS Inputs and Outputs Integrated Feature Set m Speed Versions Available 3V Static 186 CPU Core 13 MHz 80L186EA13 80L188EA 13 Power Save Idle and Powerdown 8 MHz 80L186EA8 80L188EA8 Modes m Direct Addressing Capability to Clock Generator 1 Mbyte Memory and 64 Kbyte I O 2 Independent DMA Channels 3 Programmable 16 Bit Timers W Supports 80C187 Numeric Coprocessor Dynamic RAM Refresh Control Unit Interface 80 186 only Programmable Memory and m Available in the Following Packages Peripheral Chip Select Logic 68 Pin Plastic Leaded Chip Carrier Programmable Wait State Generator PLCC Local Bus Controller 80 Pin EIAJ Quad Flat Pack QFP System Level Testing Support 80 Pin Shrink Quad Flat Pack SQFP ogh impedance Tea Mons m Available in Extended Temperature W Speed Versions Available 5V Range 40 C to 85 25 MHz 80 186 25 80 188 25 20 MHz 80 186 20 80 188 20 13 MHz 80C186EA13 80C188EA 13 80C186EA is CHMOS high integration embedded microprocessor The 80C186EA includes all of the features of an Enhanced Mode 80C186 while adding the additional capabilities of Idle and Powerdown Modes In Numerics Mode the
46. iming Waveforms for AC specification definitions test pins and illustrations AC TIMING WAVEFORMS OUTPUT PIN 272432 8 C 50 pF for all signals Figure 8 AC Test Load CLKOUT 272432 9 Figure 9 Input and Output Clock Waveform 30 PRELIMINARY In 80C186EA 80C188EA 80L186EA 80L188EA 50 CLKOUT VALID 5075 50 VALID VALID 50 50 VALID MAX VALID FLOAT NOTE MAX ov VALID FLOAT NOTE ov 272432 10 2096 Vcc Float 8086 Vcc Figure 10 Output Delay and Float Waveform Voges tas 50 CLKOUT NOTE 272432 11 NOTE RESIN measured to CLKIN not CLKOUT Figure 11 Input Setup and Hold PRELIMINARY 31 31 LI 80C186EA 80C188EA 80L186EA 80L188EA intel CLKOUT ADO 15 00 7 19 16 19 8 ov _ 53 0 LCS UCS 56 0 ov Vec DEN 50 50 ov 272432 12 NOTES 1 Tpxpr for write cycle followed by read cycle 2 Pin names in parentheses apply to tthe 80C188EA Figure 12 Relative Signal Waveform 35 PRELIMINARY 32 intel DERATING CURVES 80C186EA 80C188EA 80L186EA 80L188EA NOM 6 gt in NOM 3 gt NOM 1 lt 5 NOM 8 NOM 1 50 100 150 pF 272432 13 Figure 13 Typical Output Delay Variations Versus Load Cap
47. include the Timers and DMA channels External interrupt sources come from the four input pins INT3 0 The NMI interrupt pin is not controlled by the ICU and is passed direct ly to the CPU Although the timers only have one request input to the ICU separate vector types are generated to service individual interrupts within the Timer Unit Timer Counter Unit The 80C186EA Timer Counter Unit TCU provides three 16 bit programmable timers Two of these are highly flexible and are connected to external pins for control or clocking A third timer is not connected to any external pins and can only be clocked internally However it can be used to clock the other two timer channels The TCU can be used to count external events time external events generate non repeti tive waveforms generate timed interrupts etc 80C186EA 80C188EA 801 186 801 188 intel POB Function Function PCB Function Function Offset Offset Offset Offset 00H Reserved 40H Reserved 80H Reserved COH DMAO Src Lo 02H Reserved 42H Reserved 82H Reserved C2H DMAO Src Hi 04H Reserved 44H Reserved 84H Reserved DMAO Dest Lo 06H Reserved 46H Reserved 86H Reserved C6H DMAO Dest Hi 08H Reserved 48H Reserved 88H Reserved C8H DMAO Count Reserved 4AH Reserved 8AH Reserved CAH DMAO Control OCH Reserved 4CH Reserved 8CH Res
48. ion Name Location Name 1 AD15 A15 18 DRQO 35 MCS3 NCS 52 50 2 AD7 19 DRQ1 36 MCS2 53 St 3 AD14 A14 20 TOIN 37 MCS1 ERROR 54 S2 4 AD6 21 T1IN 38 5 55 ARDY 5 AD13 A13 22 TOOUT 39 DEN 56 CLKOUT 6 AD5 23 T1OUT 40 PDTMR 57 RESOUT 7 AD12 A12 24 RESIN 41 INT3 INTA1 58 OSCOUT 8 AD4 25 PCSO IRQ 59 CLKIN 9 Voc 26 Vss 42 INT2 INTAO 60 Vss 10 AD11 A11 27 PCS1 43 Vcc 61 ALE QSO 11 28 PCS2 44 INT1 SELECT 62 RD QSMD 12 AD10 A10 29 PCS3 45 INTO 63 WR QS1 13 AD2 30 PCS4 46 NMI 64 BHE RFSH 14 AD9 9 31 PCS5 A1 47 TEST BUSY 65 A19 S6 15 AD1 32 PCS6 A2 48 LOCK 66 A18 16 AD8 A8 33 LCS 49 SRDY 67 A17 17 ADO 34 UCS 50 HOLD 68 A16 51 HLDA NOTE Pin names in parentheses apply to the 80C186EA 80L188EA 20 08 555 TE cn VE Qi ANNET A15 015 HLDA AD7 E I HOLD 14 AD14 C SRDY AD6 C 1 LOCK 15 AD13 E TEST BUSY 05 0 I NMI A12 AD12 C I INTO 04 E NBOCTSSERZO INT1 SELECT Yoo H XXXXXXXXD See Note FG A11 AD J INT2 INTAO E C INT2 INTA 1 IRQ A10 010 C PDTMR AD2 O DEN 9 AD9 C MCSO PEREQ 7 MCS 1 ERROR 8 08 C 7 52 ADO CI MCS3 NCS 43 ui 6 qo 18 NOTES 272432 5 1 The nine character alphanumeric code XXXXXXXXD underneath the product number is the Intel FPO number 2 Pin names in parentheses a
49. ith Pin Names 1 ADO 21 16 53 41 Vss 61 Voc 2 ADS A8 22 A17 S4 42 HLDA 62 UCS 3 AD1 23 A18 S5 43 HOLD 63 LCS 4 N C 24 A19 S6 44 SRDY 64 PCS6 A2 5 AD9 9 25 N C 45 LOCK 65 PCS5 A1 6 AD2 26 BHE RFSH 46 TEST BUSY 66 PCS4 7 10 10 27 WR QS1 47 NMI 67 PCS3 8 AD3 28 RD QSMD 48 INTO 68 PCS2 9 AD11 A11 29 ALE QSO 49 INT1 SELECT 69 PCS1 10 30 Vss 50 70 Vss 11 31 Vss 51 71 PCSO 12 AD4 32 x1 52 INT2 INTAO 72 N C 13 AD12 A12 33 2 53 1 73 RES 14 AD5 34 RESET 54 DT R 74 TMR OUT 1 15 AD13 A13 85 N C 55 PDTMR 75 TMR OUT O 16 AD6 36 CLKOUT 56 DEN 76 TMR IN 1 17 AD14 A14 37 ARDY 57 MCSO PEREQ 77 IN 0 18 AD7 38 S2 58 MCS1 ERROR 78 DRQ1 19 AD15 A15 39 51 59 52 79 DRQO 20 Vcc 40 50 60 MCS3 NPS 80 Vss NOTE Pin names in parentheses apply to the 80C186EA 80L188EA PRELIMINARY 19 80 186 80 188 801 186 801 188 CLKOUT RESOUT OSCOUT J CLKIN o TEST BUSY 46 NMI E 47 INTO 48 INT1 SELECT 49 50 51 INT2 INTAO 52 INTS INTAT IRQ D 53 DT R 54 PDTMR 55 DEN 56 MCS0 PEREG 57 MCS1 ERROR 58 52 59 MCS3 NCS C186EA20 XXXXXXXXD See Note PCS6 4A2 PCS5 A1 O RD QSMD ALE QSO WR Qs1 RFSH 419 56 1418 1417 1416 17 014 A14
50. ld are required to guarantee recognition 10 Setup and Hold are required for proper operation 11 applies to BHE RFSH and A19 16 only after a HOLD release 12 Operating conditions for 25 MHz are 0 C to 70 C Voc 5 0 10 Pin names in parentheses apply to the 80C188EA 80L188EA 26 PRELIMINARY 26 n intel 80C186EA 80C188EA 80L186EA 80L188EA AC SPECIFICATIONS Characteristics 80L186EA13 80L186EA8 Symbol Parameter Min Max Min Max Units Notes INPUT CLOCK 13 MHz 8 MHz CLKIN Frequency 0 26 0 16 MHz 1 Tc CLKIN Period 38 5 oo 62 5 oo ns 1 CLKIN High Time 12 oo 12 oo ns 1 2 ToL CLKIN Low Time 12 oo 12 oo ns 1 2 CLKIN Rise Time 1 8 1 8 ns 1 3 CLKIN Fall Time 1 8 1 8 ns 1 3 OUTPUT CLOCK Tcp CLKIN to CLKOUT Delay 0 45 0 95 ns 1 4 T CLKOUT Period 2 Tc 2 Tc ns 1 CLKOUT High Time 1 2 5 7 2 5 ns 1 CLKOUT Low Time 1 2 5 7 2 5 ns 1 CLKOUT Rise Time 1 12 1 12 ns 1 5 CLKOUT Fall Time 1 12 1 12 ns 1 5 OUTPUT DELAYS ALE LOCK 3 27 3 27 ns 1 4 6 7 MCS3 0 LCS UCS 3 32 3 32 ns 1 4 PCS6 0 RD WR 6 8 82 0 DEN DT R 3 30 3 30 ns 1 BHE RFSH A19 16 TcLovi LOCK RESOUT HLDA 3 27 3 27 ns 1 4 6 TOOUT T1OUT TcLov2 RD WR MCS3 0 LCS 3 32 3 35 ns 1 4 6 UCS PCS6 0 1 0 TcLova BHE RFSH DEN A19 16
51. ly to the 80 188 NOTE Figure 21 HOLD HLDA Waveform PRELIMINARY 40 40 intel 80C186EA 80C188EA 80L186EA 80L188EA T2 13 Ti TI HOLD RFSH WR LOCK 15 01 54 Pn scel cunt ads ae Pubs CANA ST eee d A15 8 AD7 0 53 0 PCS6 0 UCS LCS fe e vu NES DT R 1 pcc 272432 22 NOTE 1 Pin names in parentheses apply to the 80C188EA Figure 22 DRAM Refresh Cycle During Hold Acknowledge PRELIMINARY 41 41 80 186 80 188 801 186 80 188 CLKOUT q N eo N c od 5 eed S k AR 32 5 5 des 9 gt 8 ETTE 3 gt lt 8 e us 88 e o5 so oc EE mE 22 S SS 7 o Beef 2 5 25 54151 esse 225 wed Pach 5 gt gt a 5 1 tr s pep qe LUG 2 2 UD bei A gt 22 8 3 298 5 lt
52. ly to the 80C188EA Figure 20 INTA Cycle Waveform 39 39 PRELIMINARY 80C186EA 80C188EA 801 186 801 188 CLKOUT 1 1 1 1 1 1 i 1 einen spes mec ASS qo BE besieges p 1 i EE 22255320 ee a E atur acer ea LE I L r t 1 1 1 1 1 1 1 i 1 i bec quee ete eene aet eee ES 1 1 Seto EE DEUM 12 52 52 15522 ccelo ec Woe Bee P diroda ee 1 1 1 1 1 1 1 1 1 1 1 1 e GRNT MK rd Farinas ene AA EEUU 1 1 1 1 1 1 Eee pacc qase Aq ees dorso um remm 1 1 1 1 1 JE NE ELLA Fuad NK ed NSA GE tease X EIS 1 1 1 1 Wer cucumber EIE pun dec uan b ut cue tu i 1 1 1 1 1 P Mosen eng e eo miei pee ewm Ke rader re ME POS 3 5 5 B 5 p lt T n 5 dcl B a 2 2 a lt lt 2 lt 272432 21 1 Pin names in parentheses app
53. mA 80C186EA13 80C188bEA13 46 mA Ipp Supply Current In Powerdown Mode 80 186 25 80 188 25 100 pA Note 5 80 186 20 80 188 20 100 pA 80 186 13 80 188 13 100 pA CouT Output Pin Capacitance 15 pF 1MHz Note 4 Input Pin Capacitance 15 pF Tp 1MHz NOTES 1 RD QSMD UCS LCS 50 MCS1 ERROR LOCK and TEST BUSY have internal pullups that are only acti vated during RESET Loading these pins above lo 275 will cause the processor to enter alternate modes of operation 2 Output pins are floated using HOLD or ONCE Mode 3 Measured at worst case temperature and Vcc with all outputs loaded as specified in the AC Test Conditions and with the device in RESET RESIN held low RESET is worst case for Icc 4 Output capacitance is the capacitive load of a floating output pin 5 Operating conditions for 25 MHz are 0 C to 70 Voc 5 0 10 22 PRELIMINARY 22 n intel 80C186EA 80C188EA 80L186EA 80L188EA DC SPECIFICATIONS 80L186EA 80L188EA Symbol Parameter Min Max Units Conditions Voc Supply Voltage 2 7 5 5 V ViL Input Low Voltage for All Pins 0 5 0 3 V Input High Voltage for All Pins 0 7 Voc 0 5 V VoL Output Low Voltage 0 45 V lo 1 6 mA min VoH Output High Voltage Voc 0 5 V 1 mA min VHYR Input Hysterisis on RESIN 0 30 V liL 4
54. nterrupt 11111010 2 2 STI Set interrupt 11111011 2 2 Halt 11110100 2 2 WAIT Wait 10011011 6 6 it TEST 0 LOCK Bus lock prefix 11110000 2 2 No Operation 10010000 3 3 TTT LLL are opcode to processor extension Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers The Effective Address EA of the memory operand is computed according to the mod and r m fields ifmod 11 then r mis treated as a REG field ifmod 00 then DISP 0 disp low and disp high are absent ifmod 01 then DISP disp low sign ex tended to 16 bits disp high is absent ifmod 10then DISP disp high disp low ifr m 000 then EA SI DISP ifr m 001 then EA DI DISP ifr m 010 then EA BP SI DISP ifr m 011 then EA BP DI DISP ifr m 100 then EA SI DISP ifr m 101 then EA DI DISP ifr m 110 then EA BP DISP ifr m 111 then EA DISP DISP follows 2nd byte of instruction before data if required 110 then EA except if mod 00 and disp high disp low EA calculation time is 4 clock cycles for all modes and is included in the execution times given whenev er appropriate Segment Override Prefix 00 1 rg 1 1 0 PRELIMINARY reg is
55. o 43 MCS3 NCS 63 N C 4 A17 24 Vss 44 Vcc 64 ADO 5 A18 25 HLDA 45 UCS 65 ADS 8 6 A19 S6 26 HOLD 46 LCS 66 AD1 7 BHE RFSH 27 SRDY 47 PCS6 A2 67 9 A9 8 WR QS1 28 LOCK 48 PCS5 A1 68 AD2 9 RD QSMD 29 TEST BUSY 49 PCS4 69 AD10 A10 10 ALE QSO 30 NMI 50 PCS3 70 AD3 11 N C 31 INTO 51 PCS2 71 AD11 A11 12 32 INT1 SELECT 52 PCS1 72 Vcc 13 Vss 33 Vcc 53 Vss 73 14 N C 34 Vcc 54 PCSO 74 AD4 15 N C 35 INT2 INTAO 55 RESIN 75 AD12 A12 16 CLKIN 36 INT3 INTA1 56 T1OUT 76 AD5 17 OSCOUT IRQ 57 TOOUT 77 AD13 A13 18 RESOUT 37 DT R 58 78 AD6 19 CLKOUT 38 PDTMR 59 TOIN 79 AD14 A14 20 ARDY 39 DEN 60 DRQ1 80 AD7 40 MCSO PEREQ NOTE Pin names in parentheses apply to the 80C186EA 80L188EA MCS3 NCS RESIN PCSO PCS5 A1 6 2 MCS2 MCS1 ERROR 165 1 voc ES 8 65 40 FI MCSO PEREQ ADIL 56 39 IDEN 9 apo 87 38 02 57 410 010 89 56 O INT3 INTA1 IRQ AD3 O 70 55 O INT2 INTA0 4011 71 S80C186EA20 552 XXXXXXXXD See Note ss H vec 73 52 0 INT1 SELECT 04 O74 12 12 E 75 405 775 29 FI TEST BUSY 413 4013777 28 06 78 27 I 5 A14 14 179 26 07 25 RI a 17 asgo 18 56 wR Qs1 RD QSMD E ALE Qs0 CLKIN E CI RESOUT
56. om ALE Falling MT 10 ns TLLWL ALE Falling to WR Falling MT 15 ns 1 ALE Falling to RD Falling MT 15 ns 1 TRHLH RD Rising to ALE Rising 10 ns 1 TWHLH WR Rising to ALE Rising MT 10 ns 1 TAFRL Address Float to RD Falling 0 ns TRLRH RD Falling to RD Rising 2 T 5 ns 2 TWLWH WR Falling to WR Rising 2 5 ns 2 TRHAV RD Rising to Address Active T 15 ns Output Data Hold after WR Rising T 15 ns TWHDEX WR Rising to DEN Rising T 10 ns 1 TWHPH WR Rising to Chip Select Rising MT 10 ns 1 4 TRHPH RD Rising to Chip Select Rising MT 10 ns 1 4 CS Inactive to CS Active T 10 ns 1 1 DEN Inactive to DT R Low 0 ns 5 ONCE UCS LCS Active to RESIN Rising T ns 3 ONCE UCS LCS to RESIN Rising T ns 3 NOTES Assumes equal loading on both pins Can be extended using wait states Not tested Not applicable to latched A2 1 These signals change only on falling T4 For write cycle followed by read cycle Operating conditions for 25 MHz are 0 C to 70 Vcc 5 0V 10 PRELIMINARY 29 80 186 80 188 801 186 801 188 TEST CONDITIONS The AC specifications are tested with the 50 pF load shown in Figure 8 See the Derating Curves section to see how timings vary with load capacitance Specifications are measured at the Vcc 2 crossing point unless otherwise specified See AC T
57. pply to the 80C186EA 80L188EA Figure 5 68 Lead PLCC Pinout Diagram 16 PRELIMINARY n intel 80C186EA 80C188EA 80L186EA 80L188EA Table 6 QFP EIAJ Pin Names with Package Location Address Data Bus Bus Control Processor Control Location Name Location Name Location Name Location ADO 64 ALE QSO 10 RESIN 55 UCS 45 AD1 66 BHE RFSH 7 RESOUT 18 5 46 AD2 68 50 23 CLKIN 16 5 40 70 51 22 OSCOUT 17 MCS1 ERROR 41 AD4 74 52 21 CLKOUT 19 MCS2 42 AD5 76 RD QSMD 9 TEST BUSY 29 MCS3 NCS 43 AD6 78 WR QS1 8 PDTMR 38 PCSO 54 AD7 80 ARDY 20 NMI 30 PCS1 52 ADS 8 65 SRDY 27 INTO 31 PCS2 51 AD9 9 67 DT R 37 INT1 SELECT 32 PCS3 50 AD10 A10 69 DEN 39 INT2 INTAO 35 PCS4 49 AD11 A11 71 LOCK 28 INT3 INTA1 36 PCS5 A1 48 AD12 A12 75 HOLD 26 IRQ PCS6 A2 47 AD13 A13 77 HLDA 25 N C 11 14 TOOUT 57 AD14 A14 79 15 63 TOIN 59 AD15 A15 1 T1OUT 56 A16 3 TAIN 58 A17 4 Power DRQO 61 A18 5 Name Location DRQ1 60 19 56 6 Vss 12 13 24 53 62 Vcc 2 33 34 44 72 73 NOTE Pin names in parentheses apply to the 80C186EA 80L188EA PRELIMINARY 17 LI 80C186EA 80C188EA 80L186EA 80L188EA intel 2 Table 7 QFP EIAJ Package Location with Pin Names Location Name Location Name Location Name Location Name 1 AD15 A15 21 S2 41 MCS1 ERROR 61 DRQO 2 Voc 22 ST 42 MCS2 62 Vss 3 A16 23 S
58. rator for both internal and external clock generation The clock generator features a crystal oscillator a divide by two counter and two low power operating modes The oscillator circuit is designed to be used with ei ther a parallel resonant fundamental or third over tone mode crystal network Alternatively the oscilla tor circuit may be driven from an external clock Source Figure 2 shows the various operating modes of the oscillator circuit The crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide by two counter This counter is used to drive all internal phase clocks and the exter nal CLKOUT signal CLKOUT is a 5096 duty cycle processor clock and can be used to drive other sys tem components All AC timings are referenced to CLKOUT The following parameters are recommended when choosing a crystal Temperature Range Application Specific ESR Equivalent Series Resistance 600 max Shunt Capacitance of Crystal 7 0 pF max C Load Capacitance 20 pF 2pF Drive Level 2 mW max PRELIMINARY 80C186EA 80C188EA 801 186 801 188 OSCOUT 80CI86EA 272432 3 A Crystal Connection NOTE The L4C4 network is only required when using a third overtone crystal External Clock Source N C 80C186EA 272432 4 B Clock Connection Figure 2 Clock Configurations 80C186EA PERIPHERAL ARCHITECTURE The 80C186EA ha
59. rier PLCC package Shrink Quad Flat Pack SQFP and Quad Flat Pack QFP pack age For complete package specifications and infor mation see the Intel Packaging Outlines and Dimen sions Guide Order Number 231369 With the extended temperature range operational characteristics are guaranteed over a temperature range corresponding to 40 C to 85 ambient Package types are identified by a two letter prefix to the part number The prefixes are listed in Table 1 Table 1 Prefix Identification Prefix Note ee bra TN PLCC Extended TS QFP EIAJ Extended SB 1 SQFP Extended Commercial N 1 PLCC Commercial S 1 QFP EIAJ Commercial NOTE 1 The 25 MHz version is only available in commercial tem perature range corresponding to 0 to 70 C ambient Pin Descriptions Each pin or logical set of pins is described in Table 3 There are three columns for each entry in the Pin Description Table The Pin Name column contains a mnemonic that describes the pin function Negation of the signal name for example RESIN denotes a signal that is active low The Pin Type column contains two kinds of informa tion The first symbol indicates whether a pin is pow er P ground input only output only PRELIMINARY 80C186EA 80C188EA 80L186EA 80L188EA input output I O Some pins have multiplexed functions for example A19 S6 Additional symbols indicate
60. roproces Sors It enhances the existing 80C186XL family by offering new features and operating modes The 80C186EA is object code compatible with the 80C186XL embedded processor 80L186EA is the version of the 80C186EA The 80L186EA is functionally identical to the 80C186EA embedded processor Current 80C186EA customers can easily upgrade their de signs to use the 80L186EA and benefit from the re duced power consumption inherent in 3V operation The feature set of the 80C186EA 80L186EA meets the needs of low power space critical applications Low power applications benefit from the static de sign of the CPU core and the integrated peripherals as well as low voltage operation Minimum current consumption is achieved by providing a Powerdown Mode that halts operation of the device and freezes the clock circuits Peripheral design enhancements ensure that non initialized peripherals consume little current Space critical applications benefit from the inte gration of commonly used system peripherals Two flexible DMA channels perform CPU independent data transfers A flexible chip select unit simplifies memory and peripheral interfacing The interrupt unit provides sources for up to 128 external interrupts and will prioritize these interrupts with those generat ed from the on chip peripherals Three general pur pose timer counters round out the feature set of the 80C186EA Figure 1 shows a block diagram of the 80C186EA
61. s Coprocessor The 0 51 and MCSS pins change their functions to constitute handshaking pins for the 80C187 The 80C186EA allows all non 80C187 users to use all the MCS pins for chip selects In regular opera tion all 80C186EA features including those of the Enhanced Mode 80 186 are present except for the interface to the 80C187 Numerics Mode disables the three chip select pins and reconfigures them for connection to the 80C187 TTL vs CMOS Inputs The inputs of the 80C186EA are rated for CMOS switching levels for improved noise immunity but the 80C186XL inputs are rated for TTL switching levels In particular the 80C186EA requires a minimum of 3 5V to recognize a logic one while the 80C186XL requires a minimum of only 1 9V assuming 5 0V operation The solution is to drive the 80C186EA with true CMOS devices such as those from the HC and AC logic families or to use pullup resistors where the added current draw is not a problem Timing Specifications 80C186EA timing relationships are expressed a simplified format over the 80C186XL The AC per formance of an 80 186 at a specified frequency will be very close to that of an 80C186XL at the same frequency Check the timings applicable to your design prior to replacing the 80C186XL PRELIMINARY intel PACKAGE INFORMATION This section describes the pins pinouts and thermal characteristics for the 80C186EA in the Plastic Leaded Chip Car
62. s integrated several common sys tem peripherals with a CPU core to create a com pact yet powerful system The integrated peripher als are designed to be flexible and provide logical interconnections between supporting units e g the interrupt control unit supports interrupt requests from the timer counters or DMA channels The list of integrated peripherals include 4 Input Interrupt Control Unit 3 Channel Timer Counter Unit 2 Channel Unit 13 Output Chip Select Unit Refresh Control Unit Power Management logic The registers associated with each integrated peri heral are contained within a 128 x 16 register file called the Peripheral Control Block PCB The PCB can be located in either memory or 1 space on any 256 byte address boundary Figure 3 provides a list of the registers associated with the PCB when the processor s Interrupt Control Unit is in Master Mode In Slave Mode the defini tions of some registers change Figure 4 provides register definitions specific to Slave Mode PRELIMINARY Interrupt Control Unit The 80C186EA can receive interrupts from a num ber of sources both internal and external The Inter rupt Control Unit ICU serves to merge these re quests on a priority basis for individual service by the CPU Each interrupt source can be independent ly masked by the Interrupt Control Unit or all inter rupts can be globally masked by the CPU Internal interrupt sources
63. signifies that the pins retain their states during Powerdown Mode LI 80C186EA 80C188EA 80L186EA 80L188EA intel 2 Table 2 Pin Description Nomenclature Symbol Description P Power Pin Apply Voltage G Ground Connect to Vss Input Only Pin Output Only Pin Input Output Pin S E Synchronous Edge Sensitive S L Synchronous Level Sensitive A E Asynchronous Edge Sensitive A L Asynchronous Level Sensitive H 1 Output Driven to Vcc during Bus Hold H 0 Output Driven to Vss during Bus Hold H Z Output Floats during Bus Hold H Q Output Remains Active during Bus Hold H X Output Retains Current State during Bus Hold R WH Output Weakly Held at Vcc during Reset R 1 Output Driven to during Reset R 0 Output Driven to Vss during Reset R Z Output Floats during Reset R Q Output Remains Active during Reset R X Output Retains Current State during Reset 11 Output Driven to Vcc during Idle Mode 0 Output Driven to Vgs during Idle Mode Z Output Floats during Idle Mode Output Remains Active during Idle Mode I X Output Retains Current State during Idle Mode P 1 Output Driven to during Powerdown Mode P 0 Output Driven to Vgs during Powerdown Mode 2 Output Floats during Powerdown Mode P Q Output Remains Active during Powerdown Mode P X Output Retains Current State during Powerdown Mode 10 PRELIMINARY 80C186EA 80C188EA 80L186EA 8
64. status information along with QS1 H Z R Z P X Byte High Enable output to indicate that the bus cycle in progress is transferring data over the upper half of the data bus BHE and AO have the following logical encoding AO BHE Encoding For 80C186EA 80L186EA Only Word Transfer Even Byte Transfer Odd Byte Transfer Refresh Operation 1 On the 80C188EA 80L188EA RFSH is asserted low to indicate a Refresh bus cycle H Z R WH P 1 ReaD output signals that the accessed memory or I O device must drive data information onto the data bus Upon reset this pin has an alternate function As QSMD it enables Queue Status Mode when grounded In Queue Status Mode the 80 and 81 pins provide the following information about processor instruction queue interaction QS1 050 Queue Operation No Queue Operation First Opcode Byte Fetched from the Queue Subsequent Byte Fetched from the Queue Empty the Queue O Pin names in parentheses apply to the 80 188 and 801 188 12 PRELIMINARY intel 80C186EA 80C188EA 80L186EA 80L188EA Table 3 Pin Descriptions Continued Pin Name Pin Type Input Type Output States Description WR QS1 H Z R Z P 1 WRite output signals that data available on the data bus are to be written into the accessed memory or 1 device In Queu
65. trol 7CH Reserved BCH Reserved FCH Reserved 3EH INT3 Control 7EH Reserved BEH Reserved FEH Relocation Figure 3 Peripheral Control Block Registers PRELIMINARY intel Function Offset 20H Interrupt Vector 22H Specific EOI 24H Reserved 26H Reserved 28H Interrupt Mask 2AH Priority Mask 2C In Service 2 Interrupt Request 30 Interrupt Status 32 TMRO Interrupt Control 34 DMAO Interrupt Control 36 Interrupt Control 38 TMR 1 Interrupt Control 3A TMR2 Interrupt Control 3C Reserved Reserved Figure 4 80C186EA Slave Mode Peripheral Control Block Registers DMA Control Unit The 80C186EA DMA Contol Unit provides two inde pendent high speed DMA channels Data transfers can occur between memory and 1 space in any combination memory to memory memory to 1 I O to or I O to memory Data can be trans ferred either in bytes or words Transfers may pro ceed to or from either even or odd addresses but even aligned word transfers proceed at a faster rate Each data transfer consumes two bus cycles a mini mum of eight clocks one cycle to fetch data and the other to store data The chip select ready logic may be programmed to point to the memory or 1 space subject to DMA transfers in order to provide hardware chip select lines DMA cycles run at higher priority than general processor execution cycles PRELIMINARY 80C186EA 80C188EA
66. utputs loaded to 50 pF including CLKOUT and OSCOUT 2 Typical Cpgy is calculated at 25 C with all outputs loaded to 50 pF except CLKOUT and OSCOUT which are not loaded 24 PRELIMINARY 24 n intel 80C186EA 80C188EA 801 186 801 188 SPECIFICATIONS Characteristics 80C186EA25 80C186EA20 80C186EA13 CLOCK 25 2 12 20 MHz 13 MHz TE CLKIN Frequency 0 50 0 40 0 26 MHz 1 Tc CLKIN Period 20 oo 25 oo 38 5 ns 1 CLKIN High Time 10 oo 10 12 ns 1 2 CLKIN Low Time 10 10 12 ns 1 2 Tor CLKIN Rise Time 1 8 1 8 1 8 ns 1 3 Tor CLKIN Fall Time 1 8 1 8 1 8 ns 1 3 OUTPUT CLOCK Top CLKIN to CLKOUT Delay 0 15 0 17 0 23 ns 1 4 T CLKOUT Period 2Tc 2 Tc 2 Tc ns 1 CLKOUT High Time 2 5 2 5 2 5 ns 1 CLKOUT Low Time 2 5 2 5 2 5 ns 1 CLKOUT Rise Time 1 6 1 6 1 6 ns 1 5 CLKOUT Fall Time 1 6 1 6 1 6 ns 1 5 OUTPUT DELAYS ALE S2 0 DEN DT R 3 20 3 22 3 25 ns 1 4 6 7 BHE RFSH LOCK A19 16 83 0 LCS UCS PCS6 0 3 25 3 27 3 30 ns 1 4 6 8 _ SINGS S o S al E BHE RFSH DEN LOCK 3 20 3 22 3 25 ns 1 4 6 RESOUT HLDA TOOUT T1OUT A19 16 RD WR MCS3 0 LCS 3 25 3 27 3 30 ns 1 4 6 UCS 56 0 AD15 0 A15 8 AD7 0 NCS INTA1 0 S2 0

Intel 80C186EA User's Manual

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